diff options
Diffstat (limited to 'arch/arm/boot/dts/hi3620.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/hi3620.dtsi | 168 |
1 files changed, 105 insertions, 63 deletions
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index d27827d8d496..b243ff097b66 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -17,6 +17,81 @@ serial1 = &uart1; }; + intc: interrupt-controller@fc001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + /* gic dist base, gic cpu base */ + reg = <0xfc001000 0x1000>, <0xfc000100 0x100>; + }; + + sysctrl@fc802000 { + compatible = "hisilicon,sysctrl"; + reg = <0xfc802000 0x1000>; + smp_reg = <0x31c>; + reboot_reg = <0x4>; + }; + + l2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0xfc100000 0x100000>; + interrupts = <0 15 4>; + cache-unified; + cache-level = <2>; + hisilicon,l2cache-aux = <0x30070000 0xf00f0000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <&intc>; + ranges; + + i2c0: i2c@fcb08000 { + compatible = "hisilicon,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfcb08000 0x1000>; + interrupts = <0 28 4>; + clocks = <&clk_i2c0>; + dmas = <&dma0 18 /* read channel */ + &dma0 19>; /* write channel */ + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c1: i2c@fcb09000 { + compatible = "hisilicon,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfcb09000 0x1000>; + interrupts = <0 29 4>; + clocks = <&clk_i2c1>; + dmas = <&dma0 20 /* read channel */ + &dma0 21>; /* write channel */ + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c2: i2c@fcb0c000 { + compatible = "hisilicon,designware-i2c"; + reg = <0xfcb0c000 0x1000>; + interrupts = <0 62 4>; + clocks = <&clk_i2c2>; + status = "disabled"; + }; + + i2c3: i2c@fcb0d000 { + compatible = "hisilicon,designware-i2c"; + reg = <0xfcb0d000 0x1000>; + interrupts = <0 63 4>; + clocks = <&clk_i2c3>; + status = "disabled"; + }; + amba { #address-cells = <1>; #size-cells = <1>; @@ -24,6 +99,14 @@ interrupt-parent = <&intc>; ranges; + timer@fc000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xfc000600 0x20>; + interrupts = <1 13 0xf01>; + clocks = <&armpll0>; + //clocks = <&smp_twd>; + }; + pmctrl: pmctrl@fca08000 { compatible = "hisilicon,pmctrl"; reg = <0xfca08000 0x1000>; @@ -84,6 +167,14 @@ clock-frequency = <1600000000>; clock-output-names = "clk_armpll1"; }; + /* + smp_twd: smp_twd{ + compatible = "hisilicon,pll"; + #clock-cells = <0>; + clock-frequency = <1600000000>; + clocks = <&armpll0>; + }; + */ peripll: pll2 { compatible = "hisilicon,pll"; #clock-cells = <0>; @@ -577,23 +668,7 @@ status = "disabled"; }; - l2: l2-cache { - compatible = "arm,pl310-cache"; - reg = <0xfc100000 0x100000>; - interrupts = <0 15 4>; - cache-unified; - cache-level = <2>; - hisilicon,l2cache-aux = <0x30070000 0xf00f0000>; - }; - intc: interrupt-controller@fc001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - /* gic dist base, gic cpu base */ - reg = <0xfc001000 0x1000>, <0xfc000100 0x100>; - }; timer0: timer@fc800000 { compatible = "arm,sp804", "arm,primecell"; @@ -620,6 +695,19 @@ status = "disabled"; }; + localtimer: localtimer@fca01000 { + compatible = "hisilicon,local-timer"; + reg = <0xfc800000 0x0020>, /* timer00 */ + <0xfca01000 0x0020>, /* timer20 */ + <0xfca01020 0x0040>, /* timer21 */ + <0xfca02000 0x0020>; /* timer30 */ + /* timer20 & timer21 */ + interrupts = <0 0 4>, /* timer00 */ + <0 4 4>, /* timer20 */ + <0 5 4>, /* timer21 */ + <0 6 4>; /* timer30 */ + }; + timer2: timer@fca01000 { compatible = "arm,sp804", "arm,primecell"; reg = <0xfca01000 0x1000>; @@ -1072,12 +1160,6 @@ pinctrl-single,register-width = <32>; }; - sysctrl@fc802000 { - compatible = "hisilicon,sysctrl"; - reg = <0xfc802000 0x1000>; - smp_reg = <0x31c>; - reboot_reg = <0x4>; - }; dma0: dma@fcd02000 { compatible = "hisilicon,k3-dma-1.0"; @@ -1089,46 +1171,6 @@ status = "disable"; }; - i2c0: i2c@fcb08000 { - compatible = "hisilicon,designware-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfcb08000 0x1000>; - interrupts = <0 28 4>; - clocks = <&clk_i2c0>; - dmas = <&dma0 18 /* read channel */ - &dma0 19>; /* write channel */ - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c1: i2c@fcb09000 { - compatible = "hisilicon,designware-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfcb09000 0x1000>; - interrupts = <0 29 4>; - clocks = <&clk_i2c1>; - dmas = <&dma0 20 /* read channel */ - &dma0 21>; /* write channel */ - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c2: i2c@fcb0c000 { - compatible = "hisilicon,designware-i2c"; - reg = <0xfcb0c000 0x1000>; - interrupts = <0 62 4>; - clocks = <&clk_i2c2>; - status = "disabled"; - }; - - i2c3: i2c@fcb0d000 { - compatible = "hisilicon,designware-i2c"; - reg = <0xfcb0d000 0x1000>; - interrupts = <0 63 4>; - clocks = <&clk_i2c3>; - status = "disabled"; - }; + }; }; }; |