From c1879341cbc8efb0ee605a2e4311728cceab7f95 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Wed, 23 Oct 2013 13:06:29 +0800 Subject: clk: hi3xxx: fix the count of clock divider Since the last item is always <0, 0>, we should add 1 on the count of the clock divider. Signed-off-by: Haojian Zhuang --- drivers/clk/hisilicon/clk-hi3xxx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/hisilicon/clk-hi3xxx.c b/drivers/clk/hisilicon/clk-hi3xxx.c index ade1297ee4b4..adaab5e5480a 100644 --- a/drivers/clk/hisilicon/clk-hi3xxx.c +++ b/drivers/clk/hisilicon/clk-hi3xxx.c @@ -528,7 +528,7 @@ void __init hi3620_clkdiv_setup(struct device_node *np) return; /*table ends with <0, 0>, so plus one to table_num*/ - table_num = max_div - min_div + 1; + table_num = max_div - min_div + 1 + 1; table = kzalloc(sizeof(struct clk_div_table) * table_num, GFP_KERNEL); if (!table) -- cgit v1.2.3