From 026929744054f27ead5ef3dcc7b5b41a525f03b6 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Sat, 8 Jun 2013 22:47:19 +0800 Subject: clk: gate: add CLK_GATE_HIWORD_MASK In Rockchip Cortex-A9 based chips, they don't use paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b1 should be set as gate, it also needs to indicate the change by setting hiword mask (b1 << 16). The patch adds gate flag for this usage. Signed-off-by: Heiko Stuebner Signed-off-by: Haojian Zhuang Signed-off-by: Mike Turquette --- drivers/clk/clk-gate.c | 25 +++++++++++++++++++------ include/linux/clk-provider.h | 5 +++++ 2 files changed, 24 insertions(+), 6 deletions(-) diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 15114febfd92..790306e921c8 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -53,12 +53,18 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) if (gate->lock) spin_lock_irqsave(gate->lock, flags); - reg = readl(gate->reg); - - if (set) - reg |= BIT(gate->bit_idx); - else - reg &= ~BIT(gate->bit_idx); + if (gate->flags & CLK_GATE_HIWORD_MASK) { + reg = BIT(gate->bit_idx + 16); + if (set) + reg |= BIT(gate->bit_idx); + } else { + reg = readl(gate->reg); + + if (set) + reg |= BIT(gate->bit_idx); + else + reg &= ~BIT(gate->bit_idx); + } writel(reg, gate->reg); @@ -121,6 +127,13 @@ struct clk *clk_register_gate(struct device *dev, const char *name, struct clk *clk; struct clk_init_data init; + if (clk_gate_flags & CLK_GATE_HIWORD_MASK) { + if (bit_idx > 16) { + pr_err("gate bit exceeds LOWORD field\n"); + return ERR_PTR(-EINVAL); + } + } + /* allocate the gate */ gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); if (!gate) { diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 16da26acf6f1..227a20d5b9b2 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -218,6 +218,10 @@ void of_fixed_clk_setup(struct device_node *np); * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to * enable the clock. Setting this flag does the opposite: setting the bit * disable the clock and clearing it enables the clock + * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit + * of this register, and mask of gate bits are in higher 16-bit of this + * register. While setting the gate bits, higher 16-bit should also be + * updated to indicate changing gate bits. */ struct clk_gate { struct clk_hw hw; @@ -228,6 +232,7 @@ struct clk_gate { }; #define CLK_GATE_SET_TO_DISABLE BIT(0) +#define CLK_GATE_HIWORD_MASK BIT(1) extern const struct clk_ops clk_gate_ops; struct clk *clk_register_gate(struct device *dev, const char *name, -- cgit v1.2.3 From 635f8824d9c29bbc69f751473437d246b4216be7 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Wed, 9 Oct 2013 16:39:36 +0800 Subject: clk: hi3xxx: support hiword property of clock gate In K3V3, hiword property also exists in clock gate. Signed-off-by: Haojian Zhuang --- drivers/clk/hisilicon/clk-hi3xxx.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/hisilicon/clk-hi3xxx.c b/drivers/clk/hisilicon/clk-hi3xxx.c index 348ba2b179e6..d16d92a4390a 100644 --- a/drivers/clk/hisilicon/clk-hi3xxx.c +++ b/drivers/clk/hisilicon/clk-hi3xxx.c @@ -309,6 +309,8 @@ static void __init hs_clkgate_setup(struct device_node *np) return; if (of_property_read_bool(np, "hisilicon,clkgate-inverted")) flags = CLK_GATE_SET_TO_DISABLE; + if (of_property_read_bool(np, "hiword")) + flags |= CLK_GATE_HIWORD_MASK; /* gate only has the fixed parent */ parent_names = kzalloc(sizeof(char *), GFP_KERNEL); if (!parent_names) -- cgit v1.2.3 From b2530b5ffd51aa3dde2e7b806ba2c8f3f4cf147b Mon Sep 17 00:00:00 2001 From: Zhangfei Gao Date: Wed, 11 Sep 2013 14:00:12 +0800 Subject: clk: hisilicon: add flag hiword timerX_mux should not use CLK_MUX_HIWORD_MASK add hiword to distinguish Introduced from commit 0b47626 ARM: dts: fix the clock setting of sp804 timer Signed-off-by: Zhangfei Gao --- arch/arm/boot/dts/hi3620.dtsi | 23 +++++++++++++++++++++++ drivers/clk/hisilicon/clk-hi3xxx.c | 8 ++++++-- 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index 242a47c8401a..34221f717c88 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -116,6 +116,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc26m &pclk>; + hiword; clock-output-names = "rclk_uart0"; /* reg_offset, enable_bits */ hisilicon,clkmux-reg = <0x100 0x80>; @@ -125,6 +126,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc26m &pclk>; + hiword; clock-output-names = "rclk_uart1"; hisilicon,clkmux-reg = <0x100 0x100>; hisilicon,clkmux-table = <0 0x100>; @@ -133,6 +135,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc26m &pclk>; + hiword; clock-output-names = "rclk_uart2"; hisilicon,clkmux-reg = <0x100 0x200>; hisilicon,clkmux-table = <0 0x200>; @@ -141,6 +144,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc26m &pclk>; + hiword; clock-output-names = "rclk_uart3"; hisilicon,clkmux-reg = <0x100 0x400>; hisilicon,clkmux-table = <0 0x400>; @@ -149,6 +153,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc26m &pclk>; + hiword; clock-output-names = "rclk_uart4"; hisilicon,clkmux-reg = <0x100 0x800>; hisilicon,clkmux-table = <0 0x800>; @@ -158,6 +163,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&pll_usb &pll_peri>; + hiword; clock-output-names = "rclk_hsic"; hisilicon,clkmux-reg = <0x130 0x4>; hisilicon,clkmux-table = <0 0x4>; @@ -184,6 +190,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc26m &refclk_cfgaxi>; + hiword; clock-output-names = "rclk_spi0"; hisilicon,clkmux-reg = <0x100 0x1000>; hisilicon,clkmux-table = <0 0x1000>; @@ -192,6 +199,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc26m &refclk_cfgaxi>; + hiword; clock-output-names = "rclk_spi1"; hisilicon,clkmux-reg = <0x100 0x2000>; hisilicon,clkmux-table = <0 0x2000>; @@ -200,6 +208,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc26m &refclk_cfgaxi>; + hiword; clock-output-names = "rclk_spi2"; hisilicon,clkmux-reg = <0x100 0x4000>; hisilicon,clkmux-table = <0 0x4000>; @@ -279,6 +288,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&pll_usb &pll_peri>; + hiword; clock-output-names = "rclk_shareAXI"; hisilicon,clkmux-reg = <0x24 0x8000>; hisilicon,clkmux-table = <0 0x8000>; @@ -287,6 +297,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&pll_peri &pll_usb>; + hiword; clock-output-names = "rclk_mmc1"; hisilicon,clkmux-reg = <0x108 0x200>; hisilicon,clkmux-table = <0 0x200>; @@ -295,6 +306,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&pll_peri &pll_usb>; + hiword; clock-output-names = "rclk_mmc2"; hisilicon,clkmux-reg = <0x140 0x10>; hisilicon,clkmux-table = <0 0x10>; @@ -303,6 +315,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&pll_peri &pll_usb>; + hiword; clock-output-names = "rclk_mmc3"; hisilicon,clkmux-reg = <0x140 0x200>; hisilicon,clkmux-table = <0 0x200>; @@ -311,6 +324,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&pll_peri &pll_usb>; + hiword; clock-output-names = "rclk_sd"; hisilicon,clkmux-reg = <0x108 0x10>; hisilicon,clkmux-table = <0 0x10>; @@ -318,6 +332,7 @@ refclk_mmc1_parent: refclk@27 { compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; + hiword; clocks = <&osc26m &div_mmc1>; clock-output-names = "rclk_mmc1_parent"; hisilicon,clkmux-reg = <0x108 0x400>; @@ -326,6 +341,7 @@ refclk_venc: refclk@28 { compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; + hiword; clocks = <&pll_peri &pll_usb>; clock-output-names = "rclk_venc"; hisilicon,clkmux-reg = <0x10c 0x800>; @@ -334,6 +350,7 @@ refclk_g2d: refclk@29 { compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; + hiword; clocks = <&pll_peri &pll_usb>; clock-output-names = "rclk_g2d"; hisilicon,clkmux-reg = <0x10c 0x20>; @@ -342,6 +359,7 @@ refclk_vdec: refclk@30 { compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; + hiword; clocks = <&pll_peri &pll_usb>; clock-output-names = "rclk_vdec"; hisilicon,clkmux-reg = <0x110 0x20>; @@ -350,6 +368,7 @@ refclk_vpp: refclk@31 { compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; + hiword; clocks = <&pll_peri &pll_usb>; clock-output-names = "rclk_vpp"; hisilicon,clkmux-reg = <0x110 0x800>; @@ -358,6 +377,7 @@ refclk_ldi0: refclk@32 { compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; + hiword; clocks = <&pll_peri &pll_usb &pll_hdmi>; clock-output-names = "rclk_ldi0"; hisilicon,clkmux-reg = <0x114 0x6000>; @@ -366,6 +386,7 @@ refclk_ldi1: refclk@33 { compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; + hiword; clocks = <&pll_peri &pll_usb &pll_hdmi>; clock-output-names = "rclk_ldi1"; hisilicon,clkmux-reg = <0x118 0xc000>; @@ -639,6 +660,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc32k &pwm_divider>; + hiword; clock-output-names = "pwm0_mux"; hisilicon,clkmux-reg = <0x104 0x400>; hisilicon,clkmux-table = <0 0x400>; @@ -647,6 +669,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc32k &pwm_divider>; + hiword; clock-output-names = "pwm1_mux"; hisilicon,clkmux-reg = <0x104 0x800>; hisilicon,clkmux-table = <0 0x800>; diff --git a/drivers/clk/hisilicon/clk-hi3xxx.c b/drivers/clk/hisilicon/clk-hi3xxx.c index d16d92a4390a..b14c11c0899a 100644 --- a/drivers/clk/hisilicon/clk-hi3xxx.c +++ b/drivers/clk/hisilicon/clk-hi3xxx.c @@ -249,7 +249,7 @@ static void __init hi3620_clkmux_setup(struct device_node *np) struct clk *clk; const char *clk_name, **parent_names = NULL; u32 rdata[2], mask, *table = NULL; - u8 num_parents, shift; + u8 num_parents, shift, flag = 0; void __iomem *reg, *base; int i, ret; @@ -262,6 +262,10 @@ static void __init hi3620_clkmux_setup(struct device_node *np) if (of_property_read_u32_array(np, "hisilicon,clkmux-reg", &rdata[0], 2)) return; + + if (of_property_read_bool(np, "hiword")) + flag = CLK_MUX_HIWORD_MASK; + ret = hi3xxx_parse_mux(np, &num_parents, table); if (ret) return; @@ -277,7 +281,7 @@ static void __init hi3620_clkmux_setup(struct device_node *np) mask = rdata[1] >> shift; clk = clk_register_mux_table(NULL, clk_name, parent_names, num_parents, CLK_SET_RATE_PARENT, reg, shift, mask, - CLK_MUX_HIWORD_MASK, table, + flag, table, &hs_clk.lock); if (IS_ERR(clk)) goto err_clk; -- cgit v1.2.3