1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
|
Device Tree Clock bindings for hi3716
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Clock control register
Required properties:
- compatible : "hisilicon,clkbase"
- reg : Address and size of clkbase.
Device Clocks
Device clocks are required to have one or both of the following sets of
properties:
Gated device clocks:
Required properties:
- compatible : "hisilicon,hi3716-clk-gate"
- gate-reg : shall be the register offset from clkbase and enable bit, reset bit
- clock-output-names : shall be reference name
Mux device clocks:
Required properties:
- compatible : "hisilicon,hi3716-clk-mux"
- mux-reg : shall be the register offset from clkbase and mux_shift mux_width
- mux-table : shall be reg value to be choose clocks accordingly
- clock-output-names : shall be reference name
Fixed divisor device clocks:
Required properties:
- compatible : "hisilicon,hi3716-fixed-divider"
- div-table : shall be divisor sequence
- clock-output-names : shall be reference name according to divisor
Fixed pll clocks:
Required properties:
- compatible : "hisilicon,hi3716-fixed-pll"
- clock-frequency : shall be output clock frequence sequence
- clock-output-names : shall be reference name according to clock-frequnce
For example:
clkbase@f8a22000 {
compatible = "hisilicon,clkbase";
reg = <0xf8a22000 0x1000>;
};
osc24m: osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "osc24mhz";
};
bpll: bpll {
compatible = "hisilicon,hi3716-fixed-pll";
#clock-cells = <1>;
clocks = <&osc24m>;
clock-frequency = <1200000000>,
<600000000>,
<300000000>,
<200000000>,
<150000000>;
clock-output-names = "bpll_fout0",
"bpll_fout1",
"bpll_fout2",
"bpll_fout3",
"bpll_fout4";
};
bpll_fout0_div: bpll_fout0_div {/* 1200Mhz */
compatible = "hisilicon,hi3716-fixed-divider";
#clock-cells = <1>;
clocks = <&bpll 0>;
div-table = <3 14 25 50>;
clock-output-names = "fout0_400m", "fout0_86m",
"fout0_48m", "fout0_24m";
};
bpll_fout3_div: bpll_fout3_div {
compatible = "hisilicon,hi3716-fixed-divider";
#clock-cells = <1>;
clocks = <&bpll 3>;
div-table = <2 4 5 8>;
clock-output-names = "fout3_100m", "fout3_50m",
"fout3_40m", "fout3_25m";
};
clk_sfc_mux: clk_sfc_mux {
compatible = "hisilicon,hi3716-clk-mux";
#clock-cells = <0>;
/* clks: 24M 75M 100M 150M 200M */
clocks = <&osc24m>, <&bpll_fout2_div>,
<&bpll_fout3_div 0>, <&bpll 4>, <&bpll 3>;
/* offset mux_shift mux_width */
mux-reg = <0x5c 8 3>;
/* mux reg value to choose clks */
mux-table = <0 7 6 4 5>;
clock-output-names = "sfc_mux";
};
clk_sfc: clk_sfc {
compatible = "hisilicon,hi3716-clk-gate";
#clock-cells = <0>;
clocks = <&clk_sfc_mux>;
/* offset, enable, reset */
gate-reg = <0x5c 0 4>;
clock-output-names = "sfc";
};
|
