diff options
| author | Bryan O'Donoghue <bryan.odonoghue@linaro.org> | 2019-03-12 12:09:51 +0000 |
|---|---|---|
| committer | Bryan O'Donoghue <bryan.odonoghue@linaro.org> | 2019-03-13 09:49:14 +0000 |
| commit | da0a4b2149894d3ea7956dfe277363ee7554fa48 (patch) | |
| tree | c5b666b8621b9dc53d47ce9a25a62cd83844b570 | |
| parent | 5237239d8ccad40f96163b3f2c30c1a7922fa8b2 (diff) | |
bl1-smc-handler: Ensure the lower-order 16 bits of SPSR are programmedintegration+bl2-el3-eret-fix-v2-01
A bug recently fixed in bl2/aarch32/bl2_el3_entrypoint.S relates to
programming the lower-order 16 bits of the SPSR to populate into the CPSR
on eret.
The BL1 smc-handler code is identical and has the same shortfall in
programming the SPSR from the platform defined struct
entry_point_info->spsr.
msr spsr, r1 will only update bits f->[31:24] and c->[7:0] respectively. In
order to ensure the 16 lower-order processor mode bits x->[15:8] and
c->[7:0].
Fixes: f3b4914be3b4 ('AArch32: Add generic changes in BL1')
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
| -rw-r--r-- | bl1/aarch32/bl1_exceptions.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/bl1/aarch32/bl1_exceptions.S b/bl1/aarch32/bl1_exceptions.S index 6728278f..f2af9ab5 100644 --- a/bl1/aarch32/bl1_exceptions.S +++ b/bl1/aarch32/bl1_exceptions.S @@ -71,7 +71,7 @@ debug_loop: */ ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET] ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)] - msr spsr, r1 + msr spsr_xc, r1 /* Some BL32 stages expect lr_svc to provide the BL33 entry address */ cps #MODE32_svc |