diff options
| author | Bryan O'Donoghue <bryan.odonoghue@linaro.org> | 2019-05-31 12:18:45 +0100 |
|---|---|---|
| committer | Bryan O'Donoghue <bryan.odonoghue@linaro.org> | 2019-05-31 17:08:30 +0100 |
| commit | 5d6615bbeca52d2b368c9d5f1186d44c4febc999 (patch) | |
| tree | ee8238ac7db69c4e2dd5737f182729c03136e807 | |
| parent | 1593f712f59ca5845ca8d2b1b4a531dfbde52cc5 (diff) | |
plat: imx8m: Set AIPSTZ config for when TEE is switched on
Sets up AIPSTZ configuration when TEE is on.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
| -rw-r--r-- | plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c index 078fe0cb..8c00c736 100644 --- a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c +++ b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c @@ -71,6 +71,47 @@ void bl31_tzc380_setup(void) TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); } +#ifdef TEE_IMX8 +static void imx8mm_aips_config(void) +{ + /* config the AIPSTZ1 */ + mmio_write_32(0x301f0000, 0x77777777); + mmio_write_32(0x301f0004, 0x77777777); + mmio_write_32(0x301f0040, 0x0); + mmio_write_32(0x301f0044, 0x0); + mmio_write_32(0x301f0048, 0x0); + mmio_write_32(0x301f004c, 0x0); + mmio_write_32(0x301f0050, 0x0); + + /* config the AIPSTZ2 */ + mmio_write_32(0x305f0000, 0x77777777); + mmio_write_32(0x305f0004, 0x77777777); + mmio_write_32(0x305f0040, 0x0); + mmio_write_32(0x305f0044, 0x0); + mmio_write_32(0x305f0048, 0x0); + mmio_write_32(0x305f004c, 0x0); + mmio_write_32(0x305f0050, 0x0); + + /* config the AIPSTZ3 */ + mmio_write_32(0x309f0000, 0x77777777); + mmio_write_32(0x309f0004, 0x77777777); + mmio_write_32(0x309f0040, 0x0); + mmio_write_32(0x309f0044, 0x0); + mmio_write_32(0x309f0048, 0x0); + mmio_write_32(0x309f004c, 0x0); + mmio_write_32(0x309f0050, 0x0); + + /* config the AIPSTZ4 */ + mmio_write_32(0x32df0000, 0x77777777); + mmio_write_32(0x32df0004, 0x77777777); + mmio_write_32(0x32df0040, 0x0); + mmio_write_32(0x32df0044, 0x0); + mmio_write_32(0x32df0048, 0x0); + mmio_write_32(0x32df004c, 0x0); + mmio_write_32(0x32df0050, 0x0); +} +#endif + void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { @@ -82,6 +123,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); } +#ifdef TEE_IMX8 + /* Setup AIPSTZ config */ + imx8mm_aips_config(); +#endif + /* config CAAM JRaMID set MID to Cortex A */ mmio_write_32(CAAM_JR0MID, CAAM_NS_MID); mmio_write_32(CAAM_JR1MID, CAAM_NS_MID); |