diff options
| author | Bryan O'Donoghue <bryan.odonoghue@linaro.org> | 2019-03-11 15:36:07 +0000 |
|---|---|---|
| committer | Bryan O'Donoghue <bryan.odonoghue@linaro.org> | 2019-03-11 18:03:30 +0000 |
| commit | 026e3549cd15d32f0d4bc2ce3aa5dec13ab540f9 (patch) | |
| tree | 0258f357ee548f6f86880839b4cdf6635d88256b | |
| parent | d079f702fb167d2dbedef4e2ac7ab571268b2949 (diff) | |
bl2-el3: Fix exit to bl32 via eretlinaro-imx7-02
On two different sorts of i.MX7 boards the WaRP7 and PicoPi we have
observed occasional failure to hand over from BL2 to BL32 i.e. from ATF to
OPTEE.
Drilling down into the failure on the subset of boards we see the failure
subsequent to eret.
The root cause of this is that eret only populates the CPSR with the SPSR
when executing in Hyp Mode and not in Secure mode.
Populating CPSR from SPSR when NS = 0 with eret is not architecturally
defined.
This patch addresses the problem by supplementing the eret instruction for
mov pc, lr.
Fixes: b1d27b484f41 ("bl2-el3: Add BL2_EL3 image")
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
| -rw-r--r-- | bl2/aarch32/bl2_el3_entrypoint.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/bl2/aarch32/bl2_el3_entrypoint.S b/bl2/aarch32/bl2_el3_entrypoint.S index cc846ddf..179bd2ed 100644 --- a/bl2/aarch32/bl2_el3_entrypoint.S +++ b/bl2/aarch32/bl2_el3_entrypoint.S @@ -75,7 +75,7 @@ func bl2_run_next_image */ ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET] ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)] - msr spsr, r1 + msr spsr_fsxc, r1 /* Some BL32 stages expect lr_svc to provide the BL33 entry address */ cps #MODE32_svc |