MLK-17590-02 driver: soc: imx: update the busfreq flow on imx8mqrel_imx_4.9.51_8mq_beta_patch

Currently, on imx8mq evk board, we only support 3200mts and 667mts
frequency setpoints. So the DDR DVFS flow need to be updated accordingly.

The dram pll and dram apb clock rate is changed in ATF when doing frequency,
in kernel side, we need to call the clk API to update the clock rate info
in clock tree.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit ff82ef826f8d2e609e5144c2e98de30bc8ea2547)

2 files changed, 18 insertions, 38 deletions

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
index b86842525390..7eece0018b8e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -111,7 +111,7 @@
 
 	busfreq { /* BUSFREQ */
 		compatible = "fsl,imx_busfreq";
-		clocks = <&clk IMX8MQ_DRAM_PLL_OUT>, <&clk IMX8MQ_CLK_DRAM_ALT_SRC>,
+		clocks = <&clk IMX8MQ_DRAM_PLL1>, <&clk IMX8MQ_CLK_DRAM_ALT_SRC>,
 			 <&clk IMX8MQ_CLK_DRAM_APB_SRC>, <&clk IMX8MQ_CLK_DRAM_APB_PRE_DIV>,
 		         <&clk IMX8MQ_CLK_DRAM_CORE>, <&clk IMX8MQ_CLK_DRAM_ALT_ROOT>,
 			 <&clk IMX8MQ_SYS1_PLL_40M>, <&clk IMX8MQ_SYS1_PLL_400M>,
diff --git a/drivers/soc/imx/busfreq-imx8mq.c b/drivers/soc/imx/busfreq-imx8mq.c
index 4d2ce9d8872d..12ee3d6f807d 100644
--- a/drivers/soc/imx/busfreq-imx8mq.c
+++ b/drivers/soc/imx/busfreq-imx8mq.c
@@ -37,6 +37,7 @@
 #define HIGH_FREQ_3200MTS	0x0
 #define AUDIO_FREQ_400MTS	0x1
 #define LOW_BUS_FREQ_100MTS	0x2
+#define LOW_BUS_FREQ_667MTS	0x1
 #define WAIT_BUS_FREQ_DONE	0xf
 
 static struct device *busfreq_dev;
@@ -103,10 +104,6 @@ static void reduce_bus_freq(void)
 {
 	high_bus_freq_mode = 0;
 
-	/* prepare the necessary clk before frequency change */
-	clk_prepare_enable(sys1_pll_40m);
-	clk_prepare_enable(dram_alt_root);
-
 	/*
 	 * below piece of code has some redundant part, keep
 	 * it at present, we may need update the audio freq
@@ -114,16 +111,16 @@ static void reduce_bus_freq(void)
 	 */
 	if (audio_bus_count) {
 		if (cur_bus_freq_mode == BUS_FREQ_HIGH) {
-			clk_prepare_enable(sys1_pll_100m);
 
-			update_bus_freq(LOW_BUS_FREQ_100MTS);
+			update_bus_freq(LOW_BUS_FREQ_667MTS);
 
-			/* correct the clock tree info */
-			clk_disable_unprepare(sys1_pll_100m);
-			clk_set_parent(dram_alt_src, sys1_pll_100m);
-			clk_set_parent(dram_core_clk, dram_alt_root);
-			clk_set_parent(dram_apb_src, sys1_pll_40m);
-			clk_set_rate(dram_apb_pre_div, 20000000);
+			/*
+			 * the dram_apb and dram_core clk rate is changed
+			 * in ATF side, below two lines of code is just used
+			 * to upate the clock tree info in kernel side.
+			 */
+			clk_set_rate(dram_apb_pre_div, 160000000);
+			clk_get_rate(dram_pll_clk);
 			/* reduce the NOC & bus clock */
 			clk_set_rate(noc_div, clk_get_rate(noc_div) / 8);
 			clk_set_rate(ahb_div, clk_get_rate(ahb_div) / 6);
@@ -135,17 +132,11 @@ static void reduce_bus_freq(void)
 		cur_bus_freq_mode = BUS_FREQ_AUDIO;
 	} else {
 		if (cur_bus_freq_mode == BUS_FREQ_HIGH) {
-			clk_prepare_enable(sys1_pll_100m);
 
-			update_bus_freq(LOW_BUS_FREQ_100MTS);
+			update_bus_freq(LOW_BUS_FREQ_667MTS);
 
-			/* correct the clock tree info */
-			clk_disable_unprepare(sys1_pll_100m);
-			clk_set_parent(dram_alt_src, sys1_pll_100m);
-			clk_set_parent(dram_core_clk, dram_alt_root);
-			clk_set_parent(dram_apb_src, sys1_pll_40m);
-			clk_set_rate(dram_apb_pre_div, 20000000);
-			clk_prepare_enable(sys1_pll_400m);
+			clk_set_rate(dram_apb_pre_div, 160000000);
+			clk_get_rate(dram_pll_clk);
 			/* reduce the NOC & bus clock */
 			clk_set_rate(noc_div, clk_get_rate(noc_div) / 8);
 			clk_set_rate(ahb_div, clk_get_rate(ahb_div) / 6);
@@ -157,13 +148,10 @@ static void reduce_bus_freq(void)
 		cur_bus_freq_mode = BUS_FREQ_LOW;
 	}
 
-	clk_disable_unprepare(sys1_pll_40m);
-	clk_disable_unprepare(dram_alt_root);
-
 	if (audio_bus_freq_mode)
-		printk(KERN_DEBUG "ddrc freq set to audio mode: 25MHz\n");
+		printk(KERN_DEBUG "ddrc freq set to audio mode: 167MHz\n");
 	if (low_bus_freq_mode)
-		printk(KERN_DEBUG "ddrc freq set to low bus mode: 25MHz\n");
+		printk(KERN_DEBUG "ddrc freq set to low bus mode: 167MHz\n");
 }
 
 static void reduce_bus_freq_handler(struct work_struct *work)
@@ -220,19 +208,11 @@ static int set_high_bus_freq(int high_bus_freq)
 	if (high_bus_freq_mode)
 		return 0;
 
-	/*  enable the clks needed in frequency */
-	clk_prepare_enable(sys1_pll_800m);
-	clk_prepare_enable(dram_pll_clk);
-
 	/* switch the DDR freqeuncy */
-	update_bus_freq(0x0);
+	update_bus_freq(HIGH_FREQ_3200MTS);
 
-	/* correct the clock tree info */
-	clk_set_parent(dram_apb_src, sys1_pll_800m);
 	clk_set_rate(dram_apb_pre_div, 200000000);
-	clk_set_parent(dram_core_clk, dram_pll_clk);
-	clk_disable_unprepare(sys1_pll_800m);
-	clk_disable_unprepare(dram_pll_clk);
+	clk_get_rate(dram_pll_clk);
 	clk_set_rate(noc_div, 800000000);
 	clk_set_rate(ahb_div, 133333333);
 	clk_set_parent(main_axi_src, sys2_pll_333m);