Merge remote-tracking branch 'fsl-linux-sdk/imx_4.9.51_imx8_beta2' into imx_4.9.y_android_imx8_beta2o8.1.0_1.2.0_8qxp-prco8.1.0_1.1.0_auto-earo8.1.0_1.1.0_8qm-prc2

5 files changed, 46 insertions, 13 deletions

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
index d29b433c4caa..c447e76086d6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
@@ -415,8 +415,8 @@
 
 		pinctrl_i2c0: i2c0grp {
 			fsl,pins = <
-				SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL	0x0600004c
-				SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA	0x0600004c
+				SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL	0x06000021
+				SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA	0x06000021
 			>;
 		};
 
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts
index f850613332fb..c7ad58eaf153 100755
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts
@@ -403,8 +403,8 @@
 
 		pinctrl_lpi2c1: lpi1cgrp {
 			fsl,pins = <
-				SC_P_USB_SS3_TC1_ADMA_I2C1_SCL	0x06000020
-				SC_P_USB_SS3_TC3_ADMA_I2C1_SDA	0x06000020
+				SC_P_USB_SS3_TC1_ADMA_I2C1_SCL	0x06000021
+				SC_P_USB_SS3_TC3_ADMA_I2C1_SDA	0x06000021
 			>;
 		};
 
diff --git a/drivers/gpu/drm/imx/dpu/dpu-crtc.c b/drivers/gpu/drm/imx/dpu/dpu-crtc.c
index b075b390db8b..cf96dfa65682 100644
--- a/drivers/gpu/drm/imx/dpu/dpu-crtc.c
+++ b/drivers/gpu/drm/imx/dpu/dpu-crtc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the
@@ -137,12 +137,13 @@ static void dpu_crtc_enable(struct drm_crtc *crtc)
 	tcon_set_operation_mode(dpu_crtc->tcon);
 }
 
-static void dpu_crtc_disable(struct drm_crtc *crtc)
+static void dpu_crtc_atomic_disable(struct drm_crtc *crtc,
+				    struct drm_crtc_state *old_crtc_state)
 {
 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
 
 	framegen_disable(dpu_crtc->fg);
-	framegen_wait_done(dpu_crtc->fg);
+	framegen_wait_done(dpu_crtc->fg, &old_crtc_state->adjusted_mode);
 	framegen_disable_clock(dpu_crtc->fg);
 
 	WARN_ON(!crtc->state->event);
@@ -512,7 +513,7 @@ static const struct drm_crtc_helper_funcs dpu_helper_funcs = {
 	.atomic_begin = dpu_crtc_atomic_begin,
 	.atomic_flush = dpu_crtc_atomic_flush,
 	.enable = dpu_crtc_enable,
-	.disable = dpu_crtc_disable,
+	.atomic_disable = dpu_crtc_atomic_disable,
 };
 
 static int dpu_enable_vblank(struct drm_crtc *crtc)
diff --git a/drivers/gpu/imx/dpu/dpu-framegen.c b/drivers/gpu/imx/dpu/dpu-framegen.c
index ffbea6618041..fb4ff105fd6f 100644
--- a/drivers/gpu/imx/dpu/dpu-framegen.c
+++ b/drivers/gpu/imx/dpu/dpu-framegen.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the
@@ -96,6 +96,8 @@ typedef enum {
 #define FGSREPD			0x90
 #define FGSRFTD			0x94
 
+#define KHZ			1000
+
 struct dpu_framegen {
 	void __iomem *base;
 	struct clk *clk_pll;
@@ -348,17 +350,47 @@ void framegen_panic_displaymode(struct dpu_framegen *fg, fgdm_t mode)
 }
 EXPORT_SYMBOL_GPL(framegen_panic_displaymode);
 
-void framegen_wait_done(struct dpu_framegen *fg)
+void framegen_wait_done(struct dpu_framegen *fg, struct drm_display_mode *m)
 {
-	unsigned long timeout = jiffies + msecs_to_jiffies(60);
+	unsigned long timeout, pending_framedur_jiffies;
+	int frame_size = m->crtc_htotal * m->crtc_vtotal;
+	int dotclock, pending_framedur_ns;
 	u32 val;
 
+	dotclock = clk_get_rate(fg->clk_disp) / KHZ;
+	if (dotclock == 0) {
+		/* fall back to display mode's clock */
+		dotclock = m->crtc_clock;
+
+		dev_warn(fg->dpu->dev,
+				"pixel clock for FrameGen%d is zero\n", fg->id);
+	}
+
+	/*
+	 * The SoC designer indicates that there are two pending frames
+	 * to complete in the worst case.
+	 * So, three pending frames are enough for sure.
+	 */
+	pending_framedur_ns = div_u64((u64) 3 * frame_size * 1000000, dotclock);
+	pending_framedur_jiffies = nsecs_to_jiffies(pending_framedur_ns);
+	if (pending_framedur_jiffies > (3 * HZ)) {
+		pending_framedur_jiffies = 3 * HZ;
+
+		dev_warn(fg->dpu->dev,
+			 "truncate FrameGen%d pending frame duration to 3sec\n",
+			 fg->id);
+	}
+	timeout = jiffies + pending_framedur_jiffies;
+
 	mutex_lock(&fg->mutex);
 	do {
 		val = dpu_fg_read(fg, FGENSTS);
 	} while ((val & ENSTS) && time_before(jiffies, timeout));
 	mutex_unlock(&fg->mutex);
 
+	dev_dbg(fg->dpu->dev, "FrameGen%d pending frame duration is %ums\n",
+			 fg->id, jiffies_to_msecs(pending_framedur_jiffies));
+
 	if (val & ENSTS)
 		dev_err(fg->dpu->dev, "failed to wait for FrameGen%d done\n",
 			fg->id);
diff --git a/include/video/dpu.h b/include/video/dpu.h
index 5e04432ccab2..8a3cec3ebb35 100644
--- a/include/video/dpu.h
+++ b/include/video/dpu.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2018 NXP
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the
@@ -602,7 +602,7 @@ void framegen_pkickconfig(struct dpu_framegen *fg, bool enable);
 void framegen_sacfg(struct dpu_framegen *fg, unsigned int x, unsigned int y);
 void framegen_displaymode(struct dpu_framegen *fg, fgdm_t mode);
 void framegen_panic_displaymode(struct dpu_framegen *fg, fgdm_t mode);
-void framegen_wait_done(struct dpu_framegen *fg);
+void framegen_wait_done(struct dpu_framegen *fg, struct drm_display_mode *m);
 void framegen_read_timestamp(struct dpu_framegen *fg,
 			     u32 *frame_index, u32 *line_index);
 void framegen_wait_for_frame_counter_moving(struct dpu_framegen *fg);