diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2018-11-29 13:56:02 +0800 |
|---|---|---|
| committer | Bryan O'Donoghue <bryan.odonoghue@linaro.org> | 2019-05-01 17:43:30 +0100 |
| commit | ffb84287d4dcbc7dcaf51c89ad54d6294bfe0774 (patch) | |
| tree | 8f869e28ba3416a7c3586760e3bcaa5234245b3b | |
| parent | fc02f8206c58ee282bdd1bc01e4f4d65134fba60 (diff) | |
MLK-20507 arm64: dts: use clkreq as gpio
- Since the l1ss is not enabled yet, configure
the clkreq# as gpio on 8qm/qxp mek boards.
Re-configure the clkreq# as input and open
drain when l1ss is enabled later.
- Correct the perst# configurations of 8qm.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
(cherry picked from commit cb7ec372ae90798a46b11e979243c3f058d8b26f)
7 files changed, 13 insertions, 13 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8q-arm2.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8q-arm2.dtsi index e28a0e73c9ed..08296e6cf6b6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8q-arm2.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8q-arm2.dtsi @@ -525,7 +525,7 @@ pinctrl_pciea: pcieagrp{ fsl,pins = < - SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x04000021 + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 >; @@ -533,7 +533,7 @@ pinctrl_pcieb: pciebgrp{ fsl,pins = < - SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x04000021 + SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x06000021 SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 >; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2.dts index 1c21d3b9d279..6f3699a3a4fb 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-ddr4-arm2.dts @@ -505,17 +505,17 @@ pinctrl_pciea: pcieagrp{ fsl,pins = < - SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x04000021 + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 - SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x04000021 + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 >; }; pinctrl_pcieb: pciebgrp{ fsl,pins = < - SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x04000021 + SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x06000021 SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021 - SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x04000021 + SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021 >; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts index b5b8b3b5ea95..e409d3b31cc0 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts @@ -775,7 +775,7 @@ pinctrl_pciea: pcieagrp{ fsl,pins = < - SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x04000021 + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000 diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts index 4fe6a555b7a4..5b10d03140b6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts @@ -929,7 +929,7 @@ pinctrl_pciea: pcieagrp{ fsl,pins = < - SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x04000021 + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000 diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi index 1202dc57ef09..479a5a0a5a5f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dtsi @@ -438,10 +438,10 @@ pinctrl_pciea: pcieagrp{ fsl,pins = < - SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x04000021 + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 - SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x04000021 - SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x04000021 + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 + SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021 >; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi index 21229b880e3b..d5ddafadb331 100755 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dtsi @@ -599,7 +599,7 @@ pinctrl_pcieb: pcieagrp{ fsl,pins = < SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 - SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000021 + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 >; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8x-arm2.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8x-arm2.dtsi index 363f7e880fc3..a0c6895c2058 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8x-arm2.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8x-arm2.dtsi @@ -457,7 +457,7 @@ pinctrl_pcieb: pciebgrp{ fsl,pins = < SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 - SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000021 + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 >; }; |