diff options
| author | Rui Miguel Silva <rui.silva@linaro.org> | 2018-02-09 11:47:50 +0000 |
|---|---|---|
| committer | Bryan O'Donoghue <bryan.odonoghue@linaro.org> | 2019-05-01 11:51:24 +0100 |
| commit | 064b8833423f794b54999aeef4b746927ba3cbc5 (patch) | |
| tree | 7dde134dfdcac31ba8f197594490e69b98c881a7 | |
| parent | 26dbd5aae195bcb06e21da98b044a083a2105d4e (diff) | |
ARM: dts: imx7s: add csi and mipi csi2 entries
Add the necessary CSI and MIPI CSI2 entries to support the hardware connections
and setup the necessary properties.
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
| -rw-r--r-- | arch/arm/boot/dts/imx7s.dtsi | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index c2db6514bbb7..d73731668dc7 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -702,6 +702,31 @@ clock-names = "pix", "axi"; status = "disabled"; }; + + csi0: csi@30710000 { + compatible = "fsl,imx7-csi"; + reg = <0x30710000 0x10000>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CSI_MCLK_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + + mipi_csi: mipi-csi@30750000 { + compatible = "fsl,imx7-mipi-csi2"; + reg = <0x30750000 0x10000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_MIPI_CSI_ROOT_CLK>, + <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; + clock-names = "mipi_clk", "phy_clk"; + power-domains = <&pgc_mipi_phy>; + mipi-phy-supply = <®_1p0d>; + csis-phy-reset = <&src 0x28 2>; + bus-width = <4>; + status = "disabled"; + }; }; aips3: aips-bus@30800000 { |