diff options
| author | Rui Miguel Silva <rui.silva@linaro.org> | 2018-02-09 11:55:23 +0000 |
|---|---|---|
| committer | Rui Miguel Silva <rui.silva@linaro.org> | 2018-08-12 16:49:36 +0100 |
| commit | dc0ccb09e02f9a98cd90e0e10349f23e9cc09aaa (patch) | |
| tree | d8cede3f561fc741bba98f782f4f598de68691b7 | |
| parent | 144c059ff3659b77e9e5a4292f91f89ab07fc111 (diff) | |
ARM: dts: imx7s-warp: add support for camera with ov2680
Add the ports and endpoints for a complete connection between the camera
hardware components. Add ov2680 camera entry with the connection to the mipi csi
endpoint and the mipi csi with the csi endpoint.
Also add the pinctrl for the mipi_csi.
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
| -rw-r--r-- | arch/arm/boot/dts/imx7s-warp.dts | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index d5ccd032ce96..d642b6ecece7 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -218,6 +218,20 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + + ov2680: camera@36 { + compatible = "ovti,ov2680"; + reg = <0x36>; + clocks = <&osc>; + clock-names = "xvclk"; + powerdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + + port { + ov2680_mipi_ep: endpoint { + remote-endpoint = <&mipi_sensor_ep>; + }; + }; + }; }; &i2c4 { @@ -321,6 +335,37 @@ status = "okay"; }; +&csi0 { + csi-mux-mipi = <&gpr 0x14 4>; + status = "okay"; + + port { + csi_ep: endpoint { + remote-endpoint = <&csi_mipi_ep>; + }; + }; +}; + +&mipi_csi { + clock-frequency = <166000000>; + status = "okay"; + + port { + mipi_sensor_ep: endpoint1 { + remote-endpoint = <&ov2680_mipi_ep>; + clock-lanes = <0>; + data-lanes = <1>; + csis-hs-settle = <3>; + csis-clk-settle = <0>; + csis-wclk; + }; + + csi_mipi_ep: endpoint2 { + remote-endpoint = <&csi_ep>; + }; + }; +}; + &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; @@ -368,6 +413,13 @@ >; }; + pinctrl_mipi_csi: mipi_csi { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x14 + MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x14 + >; + }; + pinctrl_sai1: sai1grp { fsl,pins = < MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f |