diff options
| author | Bryan O'Donoghue <bryan.odonoghue@linaro.org> | 2017-09-20 16:36:32 +0100 |
|---|---|---|
| committer | Bryan O'Donoghue <bryan.odonoghue@linaro.org> | 2019-05-01 11:51:16 +0100 |
| commit | 7f010c20df961f18431b5832fae037f4ef38755b (patch) | |
| tree | 2e6667325a206a9a66a5cfdc61f505379246bc48 /drivers/nvmem/imx-ocotp.c | |
| parent | e1e5724ce9814e25457d04101fb98f2172016ec6 (diff) | |
nvmem: imx-ocotp: Move i.MX6 write clock setup to dedicated function
The i.MX7S/D has a different set of timing requirements, as a pre-cursor to
adding the i.MX7 timing parameters, move the i.MX6 stuff to a dedicated
function.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Acked-by: Rui Miguel Silva <rui.silva@linaro.org>
Diffstat (limited to 'drivers/nvmem/imx-ocotp.c')
| -rw-r--r-- | drivers/nvmem/imx-ocotp.c | 47 |
1 files changed, 27 insertions, 20 deletions
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c index 803493775861..0cd7e0380aad 100644 --- a/drivers/nvmem/imx-ocotp.c +++ b/drivers/nvmem/imx-ocotp.c @@ -169,6 +169,31 @@ read_end: return ret; } +static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv) +{ + unsigned long clk_rate = 0; + unsigned long strobe_read, relax, strobe_prog; + u32 timing = 0; + + /* 47.3.1.3.1 + * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX] + * fields with timing values to match the current frequency of the + * ipg_clk. OTP writes will work at maximum bus frequencies as long + * as the HW_OCOTP_TIMING parameters are set correctly. + */ + clk_rate = clk_get_rate(priv->clk); + + relax = clk_rate / (1000000000 / DEF_RELAX) - 1; + strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1; + strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1; + + timing = strobe_prog & 0x00000FFF; + timing |= (relax << 12) & 0x0000F000; + timing |= (strobe_read << 16) & 0x003F0000; + + writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING); +} + static int imx_ocotp_write(void *context, unsigned int offset, void *val, size_t bytes) { @@ -176,9 +201,6 @@ static int imx_ocotp_write(void *context, unsigned int offset, void *val, u32 *buf = val; int ret; - unsigned long clk_rate = 0; - unsigned long strobe_read, relax, strobe_prog; - u32 timing = 0; u32 ctrl; u8 waddr; u8 word = 0; @@ -197,23 +219,8 @@ static int imx_ocotp_write(void *context, unsigned int offset, void *val, return ret; } - /* 47.3.1.3.1 - * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX] - * fields with timing values to match the current frequency of the - * ipg_clk. OTP writes will work at maximum bus frequencies as long - * as the HW_OCOTP_TIMING parameters are set correctly. - */ - clk_rate = clk_get_rate(priv->clk); - - relax = clk_rate / (1000000000 / DEF_RELAX) - 1; - strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1; - strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1; - - timing = strobe_prog & 0x00000FFF; - timing |= (relax << 12) & 0x0000F000; - timing |= (strobe_read << 16) & 0x003F0000; - - writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING); + /* Setup the write timing values */ + imx_ocotp_set_imx6_timing(priv); /* 47.3.1.3.2 * Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear. |