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2014-05-23Merge remote-tracking branch 'lsk/v3.10/topic/arm64-hugepages' into ↵Mark Brown
linux-linaro-lsk
2014-05-23arm64: mm: Route pmd thp functions through pte equivalentsSteve Capper
Rather than have separate hugetlb and transparent huge page pmd manipulation functions, re-wire our thp functions to simply call the pte equivalents. This allows THP to take advantage of the new PTE_WRITE logic introduced in: c2c93e5 arm64: mm: Introduce PTE_WRITE To represent splitting THPs we use the PTE_SPECIAL bit as this is not used for pmds. Signed-off-by: Steve Capper <steve.capper@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 9c7e535fcc1725fc2e2d4f0d9dd14137f0243e23) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-22Merge remote-tracking branch 'lsk/v3.10/topic/arm64-misc' into linux-linaro-lskMark Brown
Conflicts: arch/arm64/kernel/debug-monitors.c arch/arm64/mm/dma-mapping.c
2014-05-22Merge remote-tracking branch 'lsk/v3.10/topic/arm64-perf' into linux-linaro-lskMark Brown
Conflicts: arch/arm64/kernel/Makefile
2014-05-22arm64: barriers: make use of barrier options with explicit barriersWill Deacon
When calling our low-level barrier macros directly, we can often suffice with more relaxed behaviour than the default "all accesses, full system" option. This patch updates the users of dsb() to specify the option which they actually require. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 98f7685ee69f871ba991089cb9685f0da07517ea) Signed-off-by: Mark Brown <broonie@linaro.org> Conflicts: arch/arm64/kvm/sys_regs.c
2014-05-22arm64: xchg: prevent warning if return value is unusedWill Deacon
Some users of xchg() don't bother using the return value, which results in a compiler warning like the following (from kgdb): In file included from linux/arch/arm64/include/asm/atomic.h:27:0, from include/linux/atomic.h:4, from include/linux/spinlock.h:402, from include/linux/seqlock.h:35, from include/linux/time.h:5, from include/uapi/linux/timex.h:56, from include/linux/timex.h:56, from include/linux/sched.h:19, from include/linux/pid_namespace.h:4, from kernel/debug/debug_core.c:30: kernel/debug/debug_core.c: In function ‘kgdb_cpu_enter’: linux/arch/arm64/include/asm/cmpxchg.h:75:3: warning: value computed is not used [-Wunused-value] ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) ^ linux/arch/arm64/include/asm/atomic.h:132:30: note: in expansion of macro ‘xchg’ #define atomic_xchg(v, new) (xchg(&((v)->counter), new)) kernel/debug/debug_core.c:504:4: note: in expansion of macro ‘atomic_xchg’ atomic_xchg(&kgdb_active, cpu); ^ This patch makes use of the same trick as we do for cmpxchg, by assigning the return value to a dummy variable in the xchg() macro itself. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit e1dfda9ced9bea1413a736f0d578f8218a7788ec) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-22arm64: Make atomic64_t() return "long", not "long long"Bjorn Helgaas
arm64 sets CONFIG_64BIT=y and hence uses the "long counter" atomic64_t definition from include/linux/types.h. Make atomic64_read() return "long", not "long long". Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit ba6bf8c85cb0d263ca9a98ef6a76ab651a97c60b) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-22arm64: Introduce execute-only page access permissionsCatalin Marinas
The ARMv8 architecture allows execute-only user permissions by clearing the PTE_UXN and PTE_USER bits. The kernel, however, can still access such page, so execute-only page permission does not protect against read(2)/write(2) etc. accesses. Systems requiring such protection must implement/enable features like SECCOMP. This patch changes the arm64 __P100 and __S100 protection_map[] macros to the new __PAGE_EXECONLY attributes. A side effect is that pte_valid_user() no longer triggers for __PAGE_EXECONLY since PTE_USER isn't set. To work around this, the check is done on the PTE_NG bit via the pte_valid_ng() macro. VM_READ is also checked now for page faults. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit bc07c2c6e9ed125d362af0214b6313dca180cb08) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-22arm64: Remove the aux_context structureCatalin Marinas
This patch removes the aux_context structure (and the containing file) to allow the placement of the _aarch64_ctx end magic based on the context stored on the signal stack. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 0e0276d1e1dd063cd14ce377707970d0417a0792) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-22arm64: mm: Remove superfluous "the" in commentGeert Uytterhoeven
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Jiri Kosina <jkosina@suse.cz> (cherry picked from commit aad9061bf37e05d29a2a94ae8fe1e12d8808a0dd) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-22arm64: initialize spinlock for init_mm's contextLeo Yan
ARM64 has defined the spinlock for init_mm's context, so need initialize the spinlock structure; otherwise during the suspend flow it will dump the info for spinlock's bad magic warning as below: [ 39.084394] Disabling non-boot CPUs ... [ 39.092871] BUG: spinlock bad magic on CPU#1, swapper/1/0 [ 39.092896] lock: init_mm+0x338/0x3e0, .magic: 00000000, .owner: <none>/-1, .owner_cpu: 0 [ 39.092907] CPU: 1 PID: 0 Comm: swapper/1 Tainted: G O 3.10.33 #125 [ 39.092912] Call trace: [ 39.092927] [<ffffffc000087e64>] dump_backtrace+0x0/0x16c [ 39.092934] [<ffffffc000087fe0>] show_stack+0x10/0x1c [ 39.092947] [<ffffffc000765334>] dump_stack+0x1c/0x28 [ 39.092953] [<ffffffc0007653b8>] spin_dump+0x78/0x88 [ 39.092960] [<ffffffc0007653ec>] spin_bug+0x24/0x34 [ 39.092971] [<ffffffc000300a28>] do_raw_spin_lock+0x98/0x17c [ 39.092979] [<ffffffc00076cf08>] _raw_spin_lock_irqsave+0x4c/0x60 [ 39.092990] [<ffffffc000094044>] set_mm_context+0x1c/0x6c [ 39.092996] [<ffffffc0000941c8>] __new_context+0x94/0x10c [ 39.093007] [<ffffffc0000d63d4>] idle_task_exit+0x104/0x1b0 [ 39.093014] [<ffffffc00008d91c>] cpu_die+0x14/0x74 [ 39.093021] [<ffffffc000084f74>] arch_cpu_idle_dead+0x8/0x14 [ 39.093030] [<ffffffc0000e7f18>] cpu_startup_entry+0x1ec/0x258 [ 39.093036] [<ffffffc00008d810>] secondary_start_kernel+0x114/0x124 Signed-off-by: Leo Yan <leoy@marvell.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 8f0712037b4ed63dfce844939ac9866054f15ca0) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-21arm64: initialize pgprot info earlier in bootMark Salter
Presently, paging_init() calls init_mem_pgprot() to initialize pgprot values used by macros such as PAGE_KERNEL, PAGE_KERNEL_EXEC, etc. The new fixmap and early_ioremap support also needs to use these macros before paging_init() is called. This patch moves the init_mem_pgprot() call out of paging_init() and into setup_arch() so that pgprot_default gets initialized in time for fixmap and early_ioremap. Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Borislav Petkov <borislav.petkov@amd.com> Cc: Dave Young <dyoung@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> (cherry picked from commit 0bf757c73d6612d3d279de3f61b35062aa9c8b1d) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-21Revert "arm64: virt: ensure visibility of __boot_cpu_mode"Catalin Marinas
This reverts commit 82b2f495fba338d1e3098dde1df54944a9c19751. The __boot_cpu_mode variable is flushed in head.S after being written, therefore the additional cache flushing is no longer required. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 0a997ecc08e0b551119c56d52a591d9e5b38a7cd) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-21arm64: Fix __range_ok macroChristopher Covington
Without this, the following scenario is incorrectly determined to be invalid. addr 0x7f_ffffe000 size 8192 addr_limit 0x80_00000000 This behavior was observed while trying to vmsplice the stack as part of a CRIU dump of a process on a system started with the norandmaps kernel parameter. Signed-off-by: Christopher Covington <cov@codeaurora.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 31b1e940c5d47ee1a01baeccfb1b2b8890822d1a) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-21arm64: rwsem: use asm-generic rwsem implementationWill Deacon
asm-generic offers an atomic-add based rwsem implementation, which can avoid the need for heavier, spinlock-based synchronisation on the fast path. This patch makes use of the optimised implementation for arm64 CPUs. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit c209f79940ac0c75ae8d2f503a2b9d86255e266c) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-21ARM64: perf: support dwarf unwinding in compat modeJean Pihet
Add support for unwinding using the dwarf information in compat mode. Using the correct user stack pointer allows perf to record the frames correctly in the native and compat modes. Note that although the dwarf frame unwinding works ok using libunwind in native mode (on ARMv7 & ARMv8), some changes are required to the libunwind code for the compat mode. Those changes are posted separately on the libunwind mailing list. Tested on ARMv8 platform with v8 and compat v7 binaries, the latter are statically built. Signed-off-by: Jean Pihet <jean.pihet@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 5f888a1d33c48900012e6b4c18296ce7c715dc6c) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-21ARM64: perf: add support for perf registers APIJean Pihet
This patch implements the functions required for the perf registers API, allowing the perf tool to interface kernel register dumps with libunwind in order to provide userspace backtracing. Compat mode is also supported. Only the general purpose user space registers are exported, i.e.: PERF_REG_ARM_X0, ... PERF_REG_ARM_X28, PERF_REG_ARM_FP, PERF_REG_ARM_LR, PERF_REG_ARM_SP, PERF_REG_ARM_PC and not the PERF_REG_ARM_V* registers. Signed-off-by: Jean Pihet <jean.pihet@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 2ee0d7fd36a3f87bc5b29b1ec54ad6728deedb41) Signed-off-by: Mark Brown <broonie@linaro.org> Conflicts: arch/arm64/kernel/Makefile
2014-05-21arm64: barriers: add dmb barrierWill Deacon
Commit 8adbf57fc429 ("irqchip: gic: use dmb ishst instead of dsb when raising a softirq") added an explicit dmb(...) call to the GIC driver. This patch adds a simple dmb() macro to arm64, which expands to a DMB SY instruction. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit d152d22a18c240286c19997a6249ee76ea055926) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-21arm64: Fix !CONFIG_SMP kernel buildCatalin Marinas
Commit fb4a96029c8a (arm64: kernel: fix per-cpu offset restore on resume) uses per_cpu_offset() unconditionally during CPU wakeup, however, this is only defined for the SMP case. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Dave P Martin <Dave.Martin@arm.com> (cherry picked from commit b57fc9e80692043e2a3a74e1d2c047eb700dcd0c) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-21arm64: remove return value form psci_init()Vladimir Murzin
psci_init() is written to return err code if something goes wrong. However, the single user, setup_arch(), doesn't care about it. Moreover, every error path is supplied with a clear message which is enough for pleasant debugging. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 64b4f60f497058f1c6ba118a0260249ee5c091a6) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-21Merge remote-tracking branch 'lsk/v3.10/topic/arm64-kgdb' into ↵Mark Brown
lsk-v3.10-arm64-misc Conflicts: arch/arm64/include/asm/debug-monitors.h arch/arm64/kernel/debug-monitors.c
2014-05-21arm64: Extend the PCI I/O space to 16MBCatalin Marinas
The patch moves the PCI I/O space (currently at 64K) before the earlyprintk mapping and extends it to 16MB. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 22bd1c91fe13d59cff734b69b6757adcfbd8dee9) Signed-off-by: Mark Brown <broonie@linaro.org> Conflicts: Documentation/arm64/memory.txt
2014-05-21Merge remote-tracking branch 'lsk/v3.10/topic/arm64-misc' into linux-linaro-lskMark Brown
2014-05-21Merge remote-tracking branch 'lsk/v3.10/topic/arm64-kgdb' into linux-linaro-lskMark Brown
Conflicts: arch/arm64/Kconfig arch/arm64/include/asm/debug-monitors.h arch/arm64/kernel/Makefile arch/arm64/kernel/debug-monitors.c
2014-05-21misc: debug: remove compilation warningsVijaya Kumar K
typecast instruction_pointer macro to unsigned long to resolve following compiler warnings like warning: format '%lx' expects argument of type 'long unsigned int', but argument 2 has type 'u64' [-Wformat] Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 58dcc204f18af2821f683b235bb376f9db2557f5) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-21arm64: KGDB: Add Basic KGDB supportVijaya Kumar K
Add KGDB debug support for kernel debugging. With this patch, basic KGDB debugging is possible.GDB register layout is updated and GDB tool can establish connection with target and can set/clear breakpoints. Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit bcf5763b0d58d20e288ac52f96cbd7788e262cac) Signed-off-by: Mark Brown <broonie@linaro.org> Conflicts: arch/arm64/kernel/Makefile
2014-05-21arm64: Add macros to manage processor debug stateVijaya Kumar K
Add macros to enable and disable to manage PSTATE.D for debugging. The macros local_dbg_save and local_dbg_restore are moved to irqflags.h file KGDB boot tests fail because of PSTATE.D is masked. unmask it for debugging support Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit c7db4ff5d2b459a579d348532a92fd5885520ce6) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-21arm64: asm: remove redundant "cc" clobbersWill Deacon
cbnz/tbnz don't update the condition flags, so remove the "cc" clobbers from inline asm blocks that only use these instructions to implement conditional branches. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 95c4189689f92fba7ecf9097173404d4928c6e9b) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-21arm64: barriers: allow dsb macro to take option parameterWill Deacon
The dsb instruction takes an option specifying both the target access types and shareability domain. This patch allows such an option to be passed to the dsb macro, resulting in potentially more efficient code. Currently the option is ignored until all callers are updated (unlike ARM, the option is mandated by the assembler). Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 4a7ac12eedd190cdf071e61145defa73df1675c0) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-21arm64: fix typo: s/SERRROR/SERROR/Mark Rutland
Somehow SERROR has acquired an additional 'R' in a couple of headers. This patch removes them before they spread further. As neither instance is in use yet, no other sites need to be fixed up. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit bfb67a5606376bb32cb6f93dc05cda2e8c2038a5) Signed-off-by: Mark Brown <broonie@linaro.org> Conflicts: arch/arm64/include/asm/kvm_arm.h
2014-05-20Merge remote-tracking branch 'lsk/v3.10/topic/arm64-insn' into linux-linaro-lskMark Brown
Conflicts: arch/arm64/kernel/Makefile arch/arm64/kernel/module.c
2014-05-20arm64, jump label: optimize jump label implementationJiang Liu
Optimize jump label implementation for ARM64 by dynamically patching kernel text. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Jiang Liu <liuj97@gmail.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 9732cafd9dc0206479be919baf0067239f0a63ca) Signed-off-by: Mark Brown <broonie@linaro.org> Conflicts: arch/arm64/kernel/Makefile
2014-05-20arm64: introduce aarch64_insn_gen_{nop|branch_imm}() helper functionsJiang Liu
Introduce aarch64_insn_gen_{nop|branch_imm}() helper functions, which will be used to implement jump label on ARM64. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Jiang Liu <liuj97@gmail.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 5c5bf25d4f7a950382f94fc120a5818197b48fe9) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-20arm64: move encode_insn_immediate() from module.c to insn.cJiang Liu
Function encode_insn_immediate() will be used by other instruction manipulate related functions, so move it into insn.c and rename it as aarch64_insn_encode_immediate(). Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Jiang Liu <liuj97@gmail.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit c84fced8d990dd86c523233d38b4685a52a4fc3f) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-20arm64: introduce interfaces to hotpatch kernel and module codeJiang Liu
Introduce three interfaces to patch kernel and module code: aarch64_insn_patch_text_nosync(): patch code without synchronization, it's caller's responsibility to synchronize all CPUs if needed. aarch64_insn_patch_text_sync(): patch code and always synchronize with stop_machine() aarch64_insn_patch_text(): patch code and synchronize with stop_machine() if needed Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Jiang Liu <liuj97@gmail.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit ae16480785de1da84f21d1698f304a52f9790c49) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-20arm64: introduce basic aarch64 instruction decoding helpersJiang Liu
Introduce basic aarch64 instruction decoding helper aarch64_get_insn_class() and aarch64_insn_hotpatch_safe(). Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Jiang Liu <liuj97@gmail.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit b11a64a48ccc7ca0ceb33544206934fbd3cdbb22) Signed-off-by: Mark Brown <broonie@linaro.org> Conflicts: arch/arm64/kernel/Makefile
2014-05-20arm64: arch_timer: Fix mismergeMark Brown
Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-20Merge remote-tracking branch 'lsk/v3.10/topic/arm64-crypto' into ↵Mark Brown
linux-linaro-lsk Conflicts: arch/arm64/include/asm/arch_timer.h arch/arm64/include/asm/hwcap.h arch/arm64/include/uapi/asm/hwcap.h arch/arm64/kernel/setup.c
2014-05-20arm64: advertise ARMv8 extensions to 32-bit compat ELF binariesArd Biesheuvel
This adds support for advertising the presence of ARMv8 Crypto Extensions in the Aarch32 execution state to 32-bit ELF binaries running in 32-bit compat mode under the arm64 kernel. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 4cf761cdccc3b050f768f25dc36342cdfec4efdd) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-20arm64: add AT_HWCAP2 support for 32-bit compatArd Biesheuvel
Add support for the ELF auxv entry AT_HWCAP2 when running 32-bit ELF binaries in compat mode. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 28964d32d495a0753986d464c48c8e1ae73699be) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-19arm64: Add hwcaps for crypto and CRC32 extensions.Steve Capper
Advertise the optional cryptographic and CRC32 instructions to user space where present. Several hwcap bits [3-7] are allocated. Signed-off-by: Steve Capper <steve.capper@linaro.org> [bit 2 is taken now so use bits 3-7 instead] Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 4bff28ccda2b7a3fbdf8e80aef7a599284681dc6) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-19arm64: drop redundant macros from read_cpuid()Ard Biesheuvel
asm/cputype.h contains a bunch of #defines for CPU id registers that essentially map to themselves. Remove the #defines and pass the tokens directly to the inline asm() that reads the registers. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 148eb0a1db8e37a5966afe98223cefe0c1837c26) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-19arm64: support single-step and breakpoint handler hooksSandeepa Prabhu
AArch64 Single Steping and Breakpoint debug exceptions will be used by multiple debug framworks like kprobes & kgdb. This patch implements the hooks for those frameworks to register their own handlers for handling breakpoint and single step events. Reworked the debug exception handler in entry.S: do_dbg to route software breakpoint (BRK64) exception to do_debug_exception() Signed-off-by: Sandeepa Prabhu <sandeepa.prabhu@linaro.org> Signed-off-by: Deepak Saxena <dsaxena@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit ee6214cec7818867f368c35843ea1f3dffcbb57c) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-19arm64: debug: consolidate software breakpoint handlersWill Deacon
The software breakpoint handlers are hooked in directly from ptrace, which makes it difficult to add additional handlers for things like kprobes and kgdb. This patch moves the handling code into debug-monitors.c, where we can dispatch to different debug subsystems more easily. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 1442b6ed249d2b3d2cfcf45b65ac64393495c96c) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-18Merge remote-tracking branch 'lsk/v3.10/topic/arm64-misc' into linux-linaro-lskMark Brown
Conflicts: arch/arm64/Kconfig
2014-05-16arm64: dcache: select DCACHE_WORD_ACCESS for little-endian CPUsWill Deacon
DCACHE_WORD_ACCESS uses the word-at-a-time API for optimised string comparisons in the vfs layer. This patch implements support for load_unaligned_zeropad in much the same way as has been done for ARM, although big-endian systems are also supported. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 7bc13fd33adb9536bd73965cd46bbf7377df097c) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-16arm64: futex: ensure .fixup entries are sufficiently alignedWill Deacon
AArch64 instructions must be 4-byte aligned, so make sure this is true for the futex .fixup section. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 4da7a56c59f28e27e8dcff61b5d7b05f6e203606) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-16arm64: use generic strnlen_user and strncpy_from_user functionsWill Deacon
This patch implements the word-at-a-time interface for arm64 using the same algorithm as ARM. We use the fls64 macro, which expands to a clz instruction via a compiler builtin. Big-endian configurations make use of the implementation from asm-generic. With this implemented, we can replace our byte-at-a-time strnlen_user and strncpy_from_user functions with the optimised generic versions. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 12a0ef7b0ac38677bd2d85f33df5ca0a57868819) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-16arm64: percpu: implement optimised pcpu access using tpidr_el1Will Deacon
This patch implements optimised percpu variable accesses using the el1 r/w thread register (tpidr_el1) along the same lines as arch/arm/. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 7158627686f02319c50c8d9d78f75d4c8d126ff2) Signed-off-by: Mark Brown <broonie@linaro.org>
2014-05-16Merge remote-tracking branch 'lsk/v3.10/topic/arm64-cpu' into ↵Mark Brown
lsk-v3.10-arm64-misc Conflicts: arch/arm64/kernel/smp.c
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