diff options
| author | Douglas Raillard <douglas.raillard@arm.com> | 2016-10-26 13:15:19 +0100 |
|---|---|---|
| committer | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2016-11-08 15:48:33 +0000 |
| commit | 97416437fa05c9afb239ac5a7bc8fbe6a29d34a8 (patch) | |
| tree | 19bf0c64632f2a572e142db1529c854eebb2e502 /framework | |
| parent | fe0be028baf46d1aff09c25d6736bc7a478c2851 (diff) | |
Reformat AArch64 exceptions vector table
Use the vector_base and vector_entry from TF codebase and remove
explicit ".align" ASM pseudo op from the table definition (moved inside
vector_entry macro).
Exception table is now contained in the .vectors section instead of .text
section.
Change-Id: I0b3c10036af942c3f6e8c3e6ba2f05e5cbe33103
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
Diffstat (limited to 'framework')
| -rw-r--r-- | framework/aarch64/exceptions.S | 54 |
1 files changed, 17 insertions, 37 deletions
diff --git a/framework/aarch64/exceptions.S b/framework/aarch64/exceptions.S index 64cc034..b0926a4 100644 --- a/framework/aarch64/exceptions.S +++ b/framework/aarch64/exceptions.S @@ -32,43 +32,34 @@ .globl tftf_vector - .section .text, "ax"; .align 11 - -tftf_vector: - +vector_base tftf_vector //----------------------------------------------------- // Current EL with SP0 : 0x0 - 0x180 //----------------------------------------------------- - .align 7 -SynchronousExceptionSP0: +vector_entry SynchronousExceptionSP0 b SynchronousExceptionSP0 check_vector_size SynchronousExceptionSP0 - .align 7 -IrqSP0: +vector_entry IrqSP0 b IrqSP0 check_vector_size IrqSP0 - .align 7 -FiqSP0: +vector_entry FiqSP0 b FiqSP0 check_vector_size FiqSP0 - .align 7 -SErrorSP0: +vector_entry SErrorSP0 b SErrorSP0 check_vector_size SErrorSP0 //----------------------------------------------------- // Current EL with SPx: 0x200 - 0x380 //----------------------------------------------------- - .align 7 -SynchronousExceptionSPx: +vector_entry SynchronousExceptionSPx b SynchronousExceptionSPx check_vector_size SynchronousExceptionSPx - .align 7 -IrqSPx: +vector_entry IrqSPx #if IMAGE_TFTF /* * TODO: Investigate whether the trusted firmware's code for context @@ -88,64 +79,53 @@ IrqSPx: #endif /* IMAGE_TFTF */ check_vector_size IrqSPx - .align 7 -FiqSPx: +vector_entry FiqSPx b FiqSPx check_vector_size FiqSPx - .align 7 -SErrorSPx: +vector_entry SErrorSPx b SErrorSPx check_vector_size SErrorSPx //----------------------------------------------------- // Lower EL using AArch64 : 0x400 - 0x580 //----------------------------------------------------- - .align 7 -SynchronousExceptionA64: +vector_entry SynchronousExceptionA64 b SynchronousExceptionA64 check_vector_size SynchronousExceptionA64 - .align 7 -IrqA64: +vector_entry IrqA64 b IrqA64 check_vector_size IrqA64 - .align 7 -FiqA64: +vector_entry FiqA64 b FiqA64 check_vector_size FiqA64 - .align 7 -SErrorA64: +vector_entry SErrorA64 b SErrorA64 check_vector_size SErrorA64 //----------------------------------------------------- // Lower EL using AArch32 : 0x0 - 0x180 //----------------------------------------------------- - .align 7 -SynchronousExceptionA32: +vector_entry SynchronousExceptionA32 b SynchronousExceptionA32 check_vector_size SynchronousExceptionA32 - .align 7 -IrqA32: +vector_entry IrqA32 b IrqA32 check_vector_size IrqA32 - .align 7 -FiqA32: +vector_entry FiqA32 b FiqA32 check_vector_size FiqA32 - .align 7 -SErrorA32: +vector_entry SErrorA32 b SErrorA32 check_vector_size SErrorA32 - .align 7 // Note: Exceptions will always be from the same EL, so no need to save spsr func save_regs sub sp, sp, #0x100 |