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Fix a typo for exception vector manipulation.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
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Adjust pc register after IRQ routine because CPU pipeline
increase the pc value while the instruction is not excuted
yet when IRQ interrupt pipeline.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
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Align timer register access to cp15. Then memory map is not necessary
for the test code.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
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add arch version flag in makefile so that this build flag
can be detected when building code.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
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Add stack for IRQ mode for ARMv7. Otherwise, stack operation in
IRQ mode result data abort due to data access to random address.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
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workaround missing udiv instruction because it is optional instruction.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
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Print correct message for non-HYP mode as we are support non-HYP
mode now.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
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Some ARMv8 only assembly is used in aarch32 case, add ARMv7
version assembly code
Signed-off-by: Jun Nie <jun.nie@linaro.org>
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Add vector base address handling in non-hyp mode in entry point
Signed-off-by: Jun Nie <jun.nie@linaro.org>
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some ARMv7 SoC does not support hypervisor mode. Just skip
hypervisor related operation instead of trigger panic.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
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We should never call mp_printf() in ISRs because this function tries
to acquire the printf spinlock, which can put us in a deadlock
situation.
Imagine a test where:
1) We register an ISR for the timer interrupt. This ISR calls mp_printf().
2) We program the timer to fire in the near future.
3) We print something on the console.
Now, if the timer interrupt fires while we were printing on the console
(i.e. while holding the printf lock) then the ISR will never be able to
acquire the lock again and that will just lock up the system.
This also applies to the INFO/VERBOSE/... macros which call into
mp_printf().
This patch removes all prints from ISRs in existing tests.
Change-Id: Idffc02dbdf0f730790b1f1602e50b805073acc27
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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The UINTN type was meant to represent a 'native' integer, i.e. a 32-bit
integer on 32-bit platforms and a 64-bit integer on 64-bit platforms.
The type has been removed because it was used inconsistently across the
codebase.
Change-Id: Id45afde5c110ae807ce8fbbaa1cc48cff61ff76d
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This way it is easier to understand the code and it is still valid even
if the page size changes.
Change-Id: I731ad0aa99a012eae4990ea95f507661a35ab818
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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This patch add a strong implementation of platform_get_core_pos
that supports CPUs that are multi-threaded. It checks the MT
field of the MPIDR value and shifts the affinities accordingly
so that the correect PE index is provided.
NOTE the code has hardcoded the number of PEs per CPU as 1 but
this may change when truly multi-threaded CPUs are made available.
Change-Id: I18174a65e9e089848943310b63fee916362cad13
Signed-off-by: David Cunado <david.cunado@arm.com>
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Change-Id: I9f91932715a558b4571b33101bfc23686baa55d1
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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Add some traces to inform the user that a test is finished. Also print
its result. Print the end of the test session.
The final report will still summarize/repeat everything but the user
now also gets this information as we go along. This is also useful
for tests automation with LAVA.
Change-Id: I8d3b1afd42da1a90d7c203c7deb1d59b18fe6375
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It is needed to add a isb after modifying PSTATE.{D,A,I,F} so that the
effects are seen immediately. For example, this is useful to make sure
that pending interrupt are handled as soon as the interrupts are
enabled.
Some definitions in `include/lib/aarch64/arch_helpers.h` have been moved
inside the file so that isb() is defined before it is used.
This commit makes it unnecesary to have a isb() after any of the
functions modified by this file, so all isb() after them have been
removed across the whole codebase.
The fact that the old version of the functions needed a isb() made it
easy to introduce bugs, as it was easy to forget about the isb(). There
are some cases in the codebase as well, that are now fixed.
Change-Id: If9f9335f8889f2e23900307eb6a6236143577e10
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Change-Id: Iebe05d3d896a101bd46cc9b1c44ab0712cbf4226
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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The migration to the latest model exposed some sequencing issues in TFTF
hotplug and Timer frameworks. The details are as follows:
1. The `tftf_try_cpu_on` function in the hotplug framwork invokes the CPU_ON
and then updated the `cpus_status_map[core_pos].state` based the return of
CPU_ON call. The spin lock protecting the access to the `state` was acquired
after the CPU_ON call which allowed the turned ON cpu to warm boot and execute
hotplug framework functions which depends on the state of this variable. This
resulted in assertion failures because the caller CPU still has not had a
chance to update the variable. This could be solved acquiring the spin lock
prior to making the CPU_ON call, but this solution is not adopted because some
of the CPU_ON Stress test requires to make concurrent calls to PSCI_CPU_ON to
trigger race conditions. Hence the solution is to delay the woken up CPU till
the caller CPU has had a chance to update the variable.
2. The timer handler function in timer framework had a similar problem wherein
`tftf_send_sgi` wokeup the target CPU and it accessed the `interrupt_req_time`
in `tftf_program_timer` prior to the update by the timer handler. This is
resolved by doing the update prior to the `tftf_send_sgi`. Also a dsbish()
is added in the `tftf_send_sgi` so as to ensure that all memory accesses
are completed prior to triggering the SGI.
Change-Id: I7afe99653032fc3ec4a799e58436f5efc4d844a9
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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Quite often, variables that need to be read/written using volatile
accesses are only read using volatile accesses (with ACCESS macro). They
need to be written using volatile writes as well to guarantee correct
ordering with locking functions as they do not introduce a compiler
memory barrier.
All the following statement is valid if considering a CPU that does not
need runtime barriers (DMB, exclusive atomic instructions, etc.) to have
predictable ordering between reads and writes on different threads
(multicore configuration). On the ARM architecture, these runtime
barriers are needed in addition to what the C standard guarantees. These
runtime barriers are typically provided by locking functions, but this
is not sufficient when synchronizing more than just memory accesses (for
example system register access as it is the case in the TF and TFTF).
Locking functions are implemented either as volatile inline assembly, or
can be considered as complete "volatile" blackboxes by the compiler as it
is implemented in pure assembly.
Volatile access only gives ordering guarantees between volatile accesses
in a specific thread, and does not influence the ordering of the
non-volatile accesses. It also gives no guarantee about the ordering
between volatile accesses in different threads. Only a compiler memory
barrier can guarantee an ordering between all kind of access.
Even though GCC currently seems to be quite conservative in its memory
analysis, it could very well determine that a non-volatile variable
local to the compilation unit never sees its address taken and that no
return value of any function depends on this variable, and therefore
that the locking function has no way of seeing it. This allows the
compiler to move the non-volatile write to this variable accross a
function call like spin_lock(). All these behaviors have been tested and
GCC even completely removes the storage space used by the variable if no
volatile access is made or if the variable is not "exposed" in any way.
As these variables are usually only read and written once or in polling
loops, all there accesses are required to be volatile, and using an
ACCESS macro brings no optimization compared to making the variables
volatile themselves.
The Linux kernels' document
Documentation/volatile-considered-harmful.txt does makes the assumption
that all volatile variables should be accessed within locked sections,
and that lock functions act as compiler memory barrier. This is not the
case in our code-base so volatile is still needed.
This patch makes this variables volatile and remove ACCESS macro usage
that becomes useless.
Also, remove the ACCESS macro as it is not needed anymore.
Change-Id: I69c48e28116118e6ff8e089ae8e1fe22c484f3c0
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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Even though the code had a few references to this function and to
ASM_ASSERTION they were only leftover code from when that code was
copied from the Trusted Firmware.
The function asm_assert has actually been implemented, using the plat
crash console for printing the error messages.
All occurrences of ASM_ASSERTION replaced by ENABLE_ASSERTIONS.
Change-Id: I73350eda3eb53d173b7767986c3b0e891b87cf1a
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Make sure that all text is printed before trying to turn the last CPU
off.
Also, use console_flush in the panic functions. This is done in case
the dead loop is replaced by any other kind of handler in the future.
In that case, it is possible that the handler would reinitialize the
console, which would clear its the buffer.
Change-Id: If36b35f4d77f02afcbb06f4d71442a8a70569ef5
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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There are some small functions that can potentially be reused by
different tests. Instead of having them in individual test files, a
new file called test_helpers.c (and its associated header) have been
created.
For now it includes helpers to check if the system supports system
suspend, if the system is ready to perform a system suspend, and if
the system supports PSCI_STAT_COUNT.
Change-Id: Id1851dcc1c84f9180035c4ada3186e2f7913709f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Add output parameters to tftf_program_timer_and_suspend to expose the
return code of tftf_program_timer and tftf_cpu_suspend. Also do better
error reporting than the original function.
Change-Id: I4999106137515e7056848c703825ee01483e8e89
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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Add function to safely program a timer and issue a system suspend PSCI
call in the same way as tftf_program_timer_and_suspend. It exposes the
return code of the timer setup and system suspend PSCI call through
output parameters.
Change-Id: Iea6587ca8f6fc9bac92faed90d8b531aa9a9f46a
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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Allow the user to pass some custom CFLAGS as a make parameter or as
an environment variable.
Internally, the Makefile and *.mk now use the TFTF_CFLAGS variable.
The user CFLAGS are among the last options given to the compiler as
they are appended to TFTF_CFLAGS after all the TFTF_CFLAGS options
defined in the Makefile and *.mk.
Change-Id: I97d032883cb92a23e9ff9edcf8d3470edd6254b5
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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Use the vector_base and vector_entry from TF codebase and remove
explicit ".align" ASM pseudo op from the table definition (moved inside
vector_entry macro).
Exception table is now contained in the .vectors section instead of .text
section.
Change-Id: I0b3c10036af942c3f6e8c3e6ba2f05e5cbe33103
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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This aligns with the AArch64 code which does not have any aarch64
suffix.
Change-Id: I8d890850abf98bf7f828fda433e415bcddc4cb26
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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Exception vector table is conceptually closer to exceptions than to
entrypoint, and this new organization is also aligned on the AArch64
code organization.
Change-Id: Id75637b088b82fcd84c603a2d8799aa5e6a92a1b
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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This patch adds the necessary support to Makefiles in TFTF
to enable build for AArch32.
Change-Id: Ie8dae9323982f1f8d07192de67292c7e262bca07
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This patch adds the TFTF framework support for AArch32. TFTF runs
in HYP mode when compiled for AArch32. The entrypoint, exception
and architecture files are added as part of this patch.
Change-Id: I24d8e6eff9411c2bc536e0ad45f4e375d6e56101
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This patch adds AArch32 support for the suspend framework.
The `asm_tftf_suspend.S` which was AArch64 specific is now
moved in the `aarch64` folder.
Also the suspend test case for AFFLVL3 is now modified to skip
in AArch32 build because it is not a valid affinity level for
AArch32.
Change-Id: I74aa0034f3a7785b996606f523b09bb92c35bfd1
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This patch introduces SMC framework for AArch32. The existing SMC helper
functions have been made architecture-agnostic. The `smc64_args` structure
is renamed to just `smc_args`. Similarly the `smc64_ret_values` is renamed
to `smc_ret_values`. All the users of the SMC helpers are also modified
in this patch.
This patch also removes the `noinline` directive from the function prototype
of `asm_tftf_smc64()`. This is because this assembly function is a separate
compilation unit and the compiler cannot inline it anyway hence making the
`noinline` directive redundant.
Change-Id: I6fc34fc95dc7c0ac030113e43f681dff8d2d7ccf
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This patch pulls in required AArch32 support from ARM Trusted
Firmware. The previous `spinlock.S` file which was AArch64 specific is
now moved into the `aarch64` folder. The `asm_macros.S` file has been
refactored and the common macros are moved to a new file
`asm_macros_common.S`. The makefiles are also updated for these changes.
Change-Id: I46e5f7472ee1025b158c3587e7dc12210425f929
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The sleep function constructs a PSCI state ID, and calls
tftf_program_timer_and_suspend to have the calling CPU suspended for the
specified duration.
Change-Id: I6822e3a051cc147093724d4b92f17516a3641484
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At the moment, get_overall_test_result() iterates through the list of
CPUs by relying on PLATFORM_CORE_COUNT. This might not be correct
on platforms whose topology is flexible like FVP, where
PLATFORM_CORE_COUNT identifies the number of cores in the maximum
possible configuration. In other words, PLATFORM_CORE_COUNT includes
absent CPUs.
This patch uses the for_each_cpu() macro instead, which correctly
skips absent CPUs.
Change-Id: Id8edeb46c94048b08c584d2e9b9f9d29f2873672
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__FUNCTION__ is not compliant with the ISO C standard. Recent Linaro
toolchains (e.g. 5.3) report uses of __FUNCTION__ as an error when
building with --pedantic (which is the case in TFTF).
This patch replaces all uses of __FUNCTION__ by __func__ (introduced
in the C99 standard).
Change-Id: I7cb2a23fb33a2f5dd170878ecc3743ef6d63aa7f
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The functions implemented in plat_common.c can be easily
reused between architectures with minor modification. Hence
this patch moves the file out of the `aarch64` to its parent
directory. The corresponding makefiles are also modified.
Change-Id: Ia77129f14497f3a5801735bf753afc5c6a6f77e3
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This patch moves the asm_macros.S and assert_macros.S in include/common
to the Architecture specific `aarch64` folder. Also earlier this path
being included from both framework.mk and top level Makefile. This patch
corrects that as well.
Change-Id: If127e389279497a729687059106520dcfcb4c8e5
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This patch refactors the xlat_tables library to make it inline
with the refactoring done in Trusted Firmware. The xlat_tables
is now a separate library component in the `lib/` folder.
It also includes all the enhancements done in Trusted Firmware
to the xlat_tables library.
Change-Id: I99f02c32ed44c659f989849507b091df0397442c
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This patch removes the `asm_platform_weak.S` file from TFTF
framework. This is because functions defined by the file are
now removed or reimplemented else where. The entrypoint.S file
is also reworked to make use of `func` and `endfunc` helper
macros. As a result, the framework.mk makefile and the linker
scripts have undergone modifications.
Change-Id: I18925c30f3a8f2b8ce7e827f8be13c81c6e2939b
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This patch removes the unused `wait_for_entrypoint` macro defined
in asm_macros.S. Also the dependant platform function
`platform_is_primary_core` is also removed.
Change-Id: I10ecb9b0ba1dd362a5aaacd43827365154135a5a
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Since commit 8eccdb813efc ("Compile files of stdlib separately"),
the C standard library files are compiled separately. However, the
makefiles for the NS_BL1U and NS_BL2U images haven't been updated
accordingly and still include the former std.c file, which doesn't
exist anymore. As a result, the NS_BL1U and NS_BL2U images fail
to build at the moment.
This patch defines the list of source files for the C standard
library in the framework.mk makefile. This provides an easy way
for any image built by the TFTF build system to include these
files. The TFTF, NS_BL1U and NS_BL2U makefiles have been updated
to make use of it.
Change-Id: Id8fc3c9cab7864570d56bb351836f485db742d6e
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tftf_cpu_on() is passed a context_id parameter. It is passed to
tftf_psci_cpu_on() which ensures that the target CPU enters TFTF in
tftf_hotplug_entry(). The Trusted Firmware passes the preserved to
context_id in x0 but tftf_hotplug_entry() overwrites it immediately.
This patch prevents the context_id value from being overwritten and
adds a new API to access that value. A new test case has been created
to verify it.
Change-Id: Ibd7850eaaacbf476df1a06dbaf55a30e6ba494fa
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Instead of including all C files in std.c, that file has been removed
and each file of the C library is compiled on its own.
Change-Id: Iccefb97f37977ccb96858f05db4a6d281af1292f
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When running the TFTF timer test cases on FVP Foundation model
sometimes they hang. This only happens when the TFTF is built in
debug mode.
For the test case stress_test_timer_framework() the following happens:
do_stress_test() consists of a loop in which a timer is set up, then
the CPU enters suspend mode and the timer IRQ wakes the CPU up. The
instant the timers wake up is a random instant based on the current
system timer plus a random delay.
The reason they failed is that, in debug mode, the debug output
sometimes takes too long to complete, as printing text to the console
can take a relatively long time. As the Foundation model is using the
--use-real-time option, this effect was magnified. During this time,
the timer IRQ is sometimes handled, preventing the CPU from waking up.
When compiling in release mode, this output isn't printed, so the CPU
has enough time to enter suspend mode before the interrupt.
IRQs are now masked when trying to enter suspend mode. That way, even
if it takes some time to actually enter suspend mode, an early
interrupt will become pending and the CPU just won't be able to enter
suspend mode. An extra API called `tftf_program_timer_and_suspend` has
been added to make it easier to develop other test cases where the CPU
may enter suspend mode and a timer is supposed to wake it up.
The timer framework used to unconditionally disable IRQs upon entry
and enabling them upon exit. This means that IRQs used to always be
unmasked, even in the case where they were masked upon entry. This
behaviour has been fixed to preserve the DAIF flags instead (their
state is saved upon entry and restored upon exit).
The test, disabled in a previous commit, has been enabled again.
Change-Id: Ia86619a7f30483d77029e583c94265993f578a0f
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The TFTF assumed that the GIC driver architecture is v2.0 and made
inherent assumptions about the same in the framework. In order to
add support for GICv3 systems, this assumption needs to be removed
and a new ARM GIC layer is introduced which abstracts the GIC
Architecture details. The `arm_gic.c` and `arm_gic.h` contain the
prototypes and definitions for this new layer. Also the GICv2
driver is refactored such that all the functionality is contained
within the driver and the driver is accessed through well defined
API. This essentially means that the GICv2 specific functionality
present earlier in the interrupt framework and SGI framework is
now removed.
Also certain functionality of GICv2 like clearing the
interrupt target register (GICD_ITARGETSR) to leave an interrupt
untargeted cannot be supported generically in GICv3 and hence it is
removed. The timer framework, which made use of this feature, is
modified to not use it anymore.
All the framework and testcases are modified to use the ARM GIC
layer rather than the GICv2 driver directly. The functionality
common across GICv3 and GICv2 drivers are defined in gic_common.c.
Change-Id: Idf50fa14be42cb4dfb507087e340b0404e681e98
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The precondition for any test in TFTF is that when the test starts executing,
only the lead CPU is running and all the other cores are OFF. The framework
used to ensure this by checking the cpu online state as recorded by framework.
But this is not enough as core could still be running from the firmware point
of view. This patch changes this check in the framework to query the firmware
directly to ensure that the cores are OFF before proceeding to the new test.
Change-Id: I10691588115a4a2078a47c3e9e986f9b7b8d5652
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The current TFTF framework always assumes that the lead CPU on re-entering
the framework, should proceed to the next test. This assumption is not
always right. This patch allows the lead CPU to proceed to the next
test only when all the cores have exited the TFTF framework.
Change-Id: Idc6248f4b76cd1602cae451636318b6703952cb2
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The Firmware Update(FWU) feature provides the capability to upgrade
a SoC firmware image from an external interface, such as NOR Flash,
to SoC NVM memories.
In order to carry on the above tasks both Normal and Secure world
FWU images co-operate with each other and complete the Firmware
Update process.
This patch adds support for FWU Normal image(NS_BL1U) to the TFTF
code base.
The tasks carried out by NS_BL1U are as following:
* Load FWU images from external NVM memory to NS RAM.
* Call SMC's to copy and authenticate images.
* Jump to NS_BL2U which carries out next FWU steps.
Change-Id: I59bc85e285cac523acd82706acf96a8f5f4360d6
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