diff options
| author | Srinivas Kandagatla <srinivas.kandagatla@linaro.org> | 2017-03-13 18:19:33 +0000 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2018-06-16 21:38:28 -0700 |
| commit | 5565f93c2c042633cce8eaa34369e6168a2aaabf (patch) | |
| tree | 7e814fd5354aec1d34afe0478ab5d20513be166c | |
| parent | d3b70bf5c6bb63edfc02794c5797c2d78268b3a1 (diff) | |
pcie: qcom: Add support to enable pcie refclk
This patch adds support to enable 100MHz pcie refclk,
On some boards like DB600c this clock is not enabled by default.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
| -rw-r--r-- | Documentation/devicetree/bindings/pci/qcom,pcie.txt | 1 | ||||
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-qcom.c | 21 |
2 files changed, 21 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 1fd703bd73e0..756cbd69b219 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -88,6 +88,7 @@ Definition: Should contain the following entries - "core" Clocks the pcie hw block - "phy" Clocks the pcie PHY block + - "ref" Clocks the pcie refclk - clock-names: Usage: required for apq8084/ipq4019 Value type: <stringlist> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index a1d0198081a6..2c57a81a2a3f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -84,6 +84,7 @@ struct qcom_pcie_resources_2_1_0 { struct clk *iface_clk; struct clk *core_clk; + struct clk *ref_clk; struct clk *phy_clk; struct reset_control *pci_reset; struct reset_control *axi_reset; @@ -225,6 +226,15 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) if (IS_ERR(res->iface_clk)) return PTR_ERR(res->iface_clk); + res->ref_clk = devm_clk_get(dev, "ref"); + + if (IS_ERR(res->ref_clk)) { + if (PTR_ERR(res->ref_clk) == -EPROBE_DEFER) + return PTR_ERR(res->ref_clk); + + res->ref_clk = NULL; + } + res->core_clk = devm_clk_get(dev, "core"); if (IS_ERR(res->core_clk)) return PTR_ERR(res->core_clk); @@ -263,6 +273,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) reset_control_assert(res->por_reset); reset_control_assert(res->pci_reset); clk_disable_unprepare(res->iface_clk); + clk_disable_unprepare(res->ref_clk); clk_disable_unprepare(res->core_clk); clk_disable_unprepare(res->phy_clk); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); @@ -288,10 +299,16 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_assert_ahb; } + ret = clk_prepare_enable(res->ref_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable ref clock\n"); + goto err_assert_ahb; + } + ret = clk_prepare_enable(res->iface_clk); if (ret) { dev_err(dev, "cannot prepare/enable iface clock\n"); - goto err_assert_ahb; + goto err_clk_iface; } ret = clk_prepare_enable(res->phy_clk); @@ -364,6 +381,8 @@ err_clk_core: clk_disable_unprepare(res->phy_clk); err_clk_phy: clk_disable_unprepare(res->iface_clk); +err_clk_iface: + clk_disable_unprepare(res->ref_clk); err_assert_ahb: regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); |