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authorGeorgi Djakov <georgi.djakov@linaro.org>2018-05-16 13:42:00 +0300
committerGeorgi Djakov <georgi.djakov@linaro.org>2018-07-10 18:43:32 +0300
commit0d107b0f5ef961f766ad15719ee94210902a42a0 (patch)
tree3c8380265b760a14758a5f5bcc7a2ab6fff14854
parente72253a3f8ee10de1169cb5f8f58d9c22be130a2 (diff)
arm64: dts: msm8996: Add interconnect properties for i2c
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
-rw-r--r--arch/arm64/boot/dts/qcom/msm8996.dtsi8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 19945ee331d7..4f9072ea982e 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -454,6 +454,8 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c0_default>;
pinctrl-1 = <&blsp2_i2c0_sleep>;
+ interconnects = <&pnoc MASTER_BLSP_2 &bimc SLAVE_EBI_CH0>;
+ interconnect-names = "ddr";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -472,6 +474,8 @@
clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
+ interconnects = <&pnoc MASTER_BLSP_2 &bimc SLAVE_EBI_CH0>;
+ interconnect-names = "ddr";
status = "disabled";
};
@@ -485,6 +489,8 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c1_default>;
pinctrl-1 = <&blsp2_i2c1_sleep>;
+ interconnects = <&pnoc MASTER_BLSP_2 &bimc SLAVE_EBI_CH0>;
+ interconnect-names = "ddr";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -510,6 +516,8 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c2_default>;
pinctrl-1 = <&blsp1_i2c2_sleep>;
+ interconnects = <&pnoc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
+ interconnect-names = "ddr";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";