diff options
author | Linaro CI <ci_notify@linaro.org> | 2018-08-05 21:00:24 +0000 |
---|---|---|
committer | Linaro CI <ci_notify@linaro.org> | 2018-08-05 21:00:24 +0000 |
commit | 5f402556c6aa638b6aae1777790e35faf20ec22d (patch) | |
tree | 661f80b4275d170c67311b8f0b60cd498b4619f9 | |
parent | 528863bcae30be7fdbe40346675c9f9f726c2693 (diff) | |
parent | cd5bc327c70507bcffbfab5260cd4b89e68a1af2 (diff) |
Merge remote-tracking branch 'sdm845-dt/tracking-qcomlt-sdm845-dt' into integration-linux-qcomlt
# Conflicts:
# arch/arm64/boot/dts/qcom/sdm845.dtsi
-rw-r--r-- | Documentation/devicetree/bindings/firmware/qcom,scm.txt | 3 | ||||
-rw-r--r-- | arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 174 | ||||
-rw-r--r-- | arch/arm64/boot/dts/qcom/sdm845.dtsi | 1151 | ||||
-rw-r--r-- | drivers/firmware/qcom_scm.c | 3 |
4 files changed, 1330 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt index fcf6979c0b6d..b07843f05e7d 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt @@ -12,9 +12,10 @@ Required properties: * "qcom,scm-msm8690" for MSM8690 platforms * "qcom,scm-msm8996" for MSM8996 platforms * "qcom,scm-ipq4019" for IPQ4019 platforms + * "qcom,scm-sdm845" for SDM845 platforms * "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc) - clocks: One to three clocks may be required based on compatible. - * No clock required for "qcom,scm-msm8996", "qcom,scm-ipq4019" + * No clock required for "qcom,scm-msm8996", "qcom,scm-ipq4019", "qcom,scm-sdm845" * Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960" * Core, iface, and bus clocks required for "qcom,scm" - clock-names: Must contain "core" for the core clock, "iface" for the interface diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 0ac42d08a79f..af945aaddb55 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -7,11 +7,185 @@ /dts-v1/; +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sdm845.dtsi" / { model = "Qualcomm Technologies, Inc. SDM845 MTP"; compatible = "qcom,sdm845-mtp"; + + aliases { + serial0 = &uart9; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&apps_rsc { + pm8998-rpmh-regulators { + compatible = "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd_l7_l12_l14_l15-supply = <&pm8998_s5>; + + smps2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + qcom,regulator-initial-voltage = <1100000>; + }; + + pm8998_s5: smps5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + qcom,regulator-initial-voltage = <1904000>; + }; + + pm8998_l1: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + qcom,regulator-initial-voltage = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + qcom,allowed-modes = + <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + qcom,mode-threshold-currents = <0 1>; + }; + + pm8998_l2: ldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,regulator-initial-voltage = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + qcom,allowed-modes = + <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + qcom,mode-threshold-currents = <0 30000>; + }; + + + ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,regulator-initial-voltage = <1800000>; + qcom,headroom-voltage = <56000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + regulator-allow-set-load; + qcom,allowed-modes = + <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + qcom,mode-threshold-currents = <0 10000>; + }; + + pm8998_l20: ldo20 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + qcom,regulator-initial-voltage = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + qcom,allowed-modes = + <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + qcom,mode-threshold-currents = <0 10000>; + }; + + pm8998_l26: ldo26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,regulator-initial-voltage = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + qcom,allowed-modes = + <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + qcom,mode-threshold-currents = <0 1>; + }; + + lvs1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + pmi8998-rpmh-regulators { + compatible = "qcom,pmi8998-rpmh-regulators"; + qcom,pmic-id = "b"; + + bob { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + qcom,regulator-initial-voltage = <3312000>; + }; + }; +}; + +&i2c10 { + status = "okay"; + clock-frequency = <400000>; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&uart9 { + status = "okay"; +}; + +&ufshc { + status = "ok"; + + vcc-supply = <&pm8998_l20>; + vcc-voltage-level = <2950000 2960000>; + vcc-max-microamp = <600000>; + vccq2-max-microamp = <600000>; + + qcom,vddp-ref-clk-supply = <&pm8998_l2>; + qcom,vddp-ref-clk-max-microamp = <100>; + +}; + +&ufsphy { + status = "ok"; + + vdda-phy-supply = <&pm8998_l1>; /* 0.88v */ + vdda-pll-supply = <&pm8998_l26>; /* 1.2v */ + vdda-phy-max-microamp = <62900>; + vdda-pll-max-microamp = <18300>; +}; + +/* PINCTRL - additions to nodes defined in sdm845.dtsi */ + +&qup_i2c10_default { + pinconf { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qup_uart9_default { + pinconf-tx { + pins = "gpio4"; + drive-strength = <2>; + bias-disable; + }; + + pinconf-rx { + pins = "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&qup_uart9_sleep { + pinconf { + pins = "gpio4", "gpio5"; + bias-pull-down; + }; }; &adsp_pil { diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index ecda34801d30..1097c7ef31b9 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -5,9 +5,12 @@ * Copyright (c) 2018, The Linux Foundation. All rights reserved. */ +#include <dt-bindings/clock/qcom,gcc-sdm845.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/reset/qcom,sdm845-aoss.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/clock/qcom,gcc-sdm845.h> +#include <dt-bindings/clock/qcom,rpmh.h> / { interrupt-parent = <&intc>; @@ -15,6 +18,41 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + i2c14 = &i2c14; + i2c15 = &i2c15; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + spi4 = &spi4; + spi5 = &spi5; + spi6 = &spi6; + spi7 = &spi7; + spi8 = &spi8; + spi9 = &spi9; + spi10 = &spi10; + spi11 = &spi11; + spi12 = &spi12; + spi13 = &spi13; + spi14 = &spi14; + spi15 = &spi15; + }; + chosen { }; memory@80000000 { @@ -266,6 +304,12 @@ }; }; + firmware { + scm { + compatible = "qcom,scm-sdm845"; + }; + }; + tcsr_mutex: hwlock { compatible = "qcom,tcsr-mutex"; syscon = <&tcsr_mutex_regs 0 0x1000>; @@ -385,6 +429,489 @@ #power-domain-cells = <1>; }; + qupv3_id_0: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x8c0000 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + i2c0: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0x880000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_i2c0_default>; + pinctrl-1 = <&qup_i2c0_sleep>; + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0x880000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_spi0_default>; + pinctrl-1 = <&qup_spi0_sleep>; + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0x884000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_i2c1_default>; + pinctrl-1 = <&qup_i2c1_sleep>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0x884000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_spi1_default>; + pinctrl-1 = <&qup_spi1_sleep>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0x888000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_i2c2_default>; + pinctrl-1 = <&qup_i2c2_sleep>; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0x888000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_spi2_default>; + pinctrl-1 = <&qup_spi2_sleep>; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0x88c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_i2c3_default>; + pinctrl-1 = <&qup_i2c3_sleep>; + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0x88c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_spi3_default>; + pinctrl-1 = <&qup_spi3_sleep>; + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0x890000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_i2c4_default>; + pinctrl-1 = <&qup_i2c4_sleep>; + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0x890000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_spi4_default>; + pinctrl-1 = <&qup_spi4_sleep>; + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0x894000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_i2c5_default>; + pinctrl-1 = <&qup_i2c5_sleep>; + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0x894000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_spi5_default>; + pinctrl-1 = <&qup_spi5_sleep>; + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@898000 { + compatible = "qcom,geni-i2c"; + reg = <0x898000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_i2c6_default>; + pinctrl-1 = <&qup_i2c6_sleep>; + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@898000 { + compatible = "qcom,geni-spi"; + reg = <0x898000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_spi6_default>; + pinctrl-1 = <&qup_spi6_sleep>; + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@89c000 { + compatible = "qcom,geni-i2c"; + reg = <0x89c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_i2c7_default>; + pinctrl-1 = <&qup_i2c7_sleep>; + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi7: spi@89c000 { + compatible = "qcom,geni-spi"; + reg = <0x89c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_spi7_default>; + pinctrl-1 = <&qup_spi7_sleep>; + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xac0000 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + i2c8: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0xa80000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_i2c8_default>; + pinctrl-1 = <&qup_i2c8_sleep>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi8: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0xa80000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_spi8_default>; + pinctrl-1 = <&qup_spi8_sleep>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0xa84000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_i2c9_default>; + pinctrl-1 = <&qup_i2c9_sleep>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi9: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0xa84000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_spi9_default>; + pinctrl-1 = <&qup_spi9_sleep>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart9: serial@a84000 { + compatible = "qcom,geni-debug-uart"; + reg = <0xa84000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_uart9_default>; + pinctrl-1 = <&qup_uart9_sleep>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0xa88000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_i2c10_default>; + pinctrl-1 = <&qup_i2c10_sleep>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi10: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0xa88000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_spi10_default>; + pinctrl-1 = <&qup_spi10_sleep>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0xa8c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_i2c11_default>; + pinctrl-1 = <&qup_i2c11_sleep>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi11: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0xa8c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_spi11_default>; + pinctrl-1 = <&qup_spi11_sleep>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c12: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0xa90000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_i2c12_default>; + pinctrl-1 = <&qup_i2c12_sleep>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi12: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0xa90000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_spi12_default>; + pinctrl-1 = <&qup_spi12_sleep>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c13: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0xa94000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_i2c13_default>; + pinctrl-1 = <&qup_i2c13_sleep>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi13: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0xa94000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_spi13_default>; + pinctrl-1 = <&qup_spi13_sleep>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c14: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0xa98000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_i2c14_default>; + pinctrl-1 = <&qup_i2c14_sleep>; + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi14: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0xa98000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_spi14_default>; + pinctrl-1 = <&qup_spi14_sleep>; + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c15: i2c@a9c000 { + compatible = "qcom,geni-i2c"; + reg = <0xa9c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_i2c15_default>; + pinctrl-1 = <&qup_i2c15_sleep>; + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi15: spi@a9c000 { + compatible = "qcom,geni-spi"; + reg = <0xa9c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_spi15_default>; + pinctrl-1 = <&qup_spi15_sleep>; + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + tcsr_mutex_regs: syscon@1f40000 { compatible = "syscon"; reg = <0x1f40000 0x40000>; @@ -398,6 +925,542 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + + qup_i2c0_default: qup-i2c0-default { + pinmux { + pins = "gpio0", "gpio1"; + function = "qup0"; + }; + }; + + qup_i2c0_sleep: qup-i2c0-sleep { + pinmux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + }; + + qup_i2c1_default: qup-i2c1-default { + pinmux { + pins = "gpio17", "gpio18"; + function = "qup1"; + }; + }; + + qup_i2c1_sleep: qup-i2c1-sleep { + pinmux { + pins = "gpio17", "gpio18"; + function = "gpio"; + }; + }; + + qup_i2c2_default: qup-i2c2-default { + pinmux { + pins = "gpio27", "gpio28"; + function = "qup2"; + }; + }; + + qup_i2c2_sleep: qup-i2c2-sleep { + pinmux { + pins = "gpio27", "gpio28"; + function = "gpio"; + }; + }; + + qup_i2c3_default: qup-i2c3-default { + pinmux { + pins = "gpio41", "gpio42"; + function = "qup3"; + }; + }; + + qup_i2c3_sleep: qup-i2c3-sleep { + pinmux { + pins = "gpio41", "gpio42"; + function = "gpio"; + }; + }; + + qup_i2c4_default: qup-i2c4-default { + pinmux { + pins = "gpio89", "gpio90"; + function = "qup4"; + }; + }; + + qup_i2c4_sleep: qup-i2c4-sleep { + pinmux { + pins = "gpio89", "gpio90"; + function = "gpio"; + }; + }; + + qup_i2c5_default: qup-i2c5-default { + pinmux { + pins = "gpio85", "gpio86"; + function = "qup5"; + }; + }; + + qup_i2c5_sleep: qup-i2c5-sleep { + pinmux { + pins = "gpio85", "gpio86"; + function = "gpio"; + }; + }; + + qup_i2c6_default: qup-i2c6-default { + pinmux { + pins = "gpio45", "gpio46"; + function = "qup6"; + }; + }; + + qup_i2c6_sleep: qup-i2c6-sleep { + pinmux { + pins = "gpio45", "gpio46"; + function = "gpio"; + }; + }; + + qup_i2c7_default: qup-i2c7-default { + pinmux { + pins = "gpio93", "gpio94"; + function = "qup7"; + }; + }; + + qup_i2c7_sleep: qup-i2c7-sleep { + pinmux { + pins = "gpio93", "gpio94"; + function = "gpio"; + }; + }; + + qup_i2c8_default: qup-i2c8-default { + pinmux { + pins = "gpio65", "gpio66"; + function = "qup8"; + }; + }; + + qup_i2c8_sleep: qup-i2c8-sleep { + pinmux { + pins = "gpio65", "gpio66"; + function = "gpio"; + }; + }; + + qup_i2c9_default: qup-i2c9-default { + pinmux { + pins = "gpio6", "gpio7"; + function = "qup9"; + }; + }; + + qup_i2c9_sleep: qup-i2c9-sleep { + pinmux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + }; + + qup_i2c10_default: qup-i2c10-default { + pinmux { + pins = "gpio55", "gpio56"; + function = "qup10"; + }; + }; + + qup_i2c10_sleep: qup-i2c10-sleep { + pinmux { + pins = "gpio55", "gpio56"; + function = "gpio"; + }; + }; + + qup_i2c11_default: qup-i2c11-default { + pinmux { + pins = "gpio31", "gpio32"; + function = "qup11"; + }; + }; + + qup_i2c11_sleep: qup-i2c11-sleep { + pinmux { + pins = "gpio31", "gpio32"; + function = "gpio"; + }; + }; + + qup_i2c12_default: qup-i2c12-default { + pinmux { + pins = "gpio49", "gpio50"; + function = "qup12"; + }; + }; + + qup_i2c12_sleep: qup-i2c12-sleep { + pinmux { + pins = "gpio49", "gpio50"; + function = "gpio"; + }; + }; + + qup_i2c13_default: qup-i2c13-default { + pinmux { + pins = "gpio105", "gpio106"; + function = "qup13"; + }; + }; + + qup_i2c13_sleep: qup-i2c13-sleep { + pinmux { + pins = "gpio105", "gpio106"; + function = "gpio"; + }; + }; + + qup_i2c14_default: qup-i2c14-default { + pinmux { + pins = "gpio33", "gpio34"; + function = "qup14"; + }; + }; + + qup_i2c14_sleep: qup-i2c14-sleep { + pinmux { + pins = "gpio33", "gpio34"; + function = "gpio"; + }; + }; + + qup_i2c15_default: qup-i2c15-default { + pinmux { + pins = "gpio81", "gpio82"; + function = "qup15"; + }; + }; + + qup_i2c15_sleep: qup-i2c15-sleep { + pinmux { + pins = "gpio81", "gpio82"; + function = "gpio"; + }; + }; + + qup_spi0_default: qup-spi0-default { + pinmux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "qup0"; + }; + }; + + qup_spi0_sleep: qup-spi0-sleep { + pinmux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "gpio"; + }; + }; + + qup_spi1_default: qup-spi1-default { + pinmux { + pins = "gpio17", "gpio18", + "gpio19", "gpio20"; + function = "qup1"; + }; + }; + + qup_spi1_sleep: qup-spi1-sleep { + pinmux { + pins = "gpio17", "gpio18", + "gpio19", "gpio20"; + function = "gpio"; + }; + }; + + qup_spi2_default: qup-spi2-default { + pinmux { + pins = "gpio27", "gpio28", + "gpio29", "gpio30"; + function = "qup2"; + }; + }; + + qup_spi2_sleep: qup-spi2-sleep { + pinmux { + pins = "gpio27", "gpio28", + "gpio29", "gpio30"; + function = "gpio"; + }; + }; + + qup_spi3_default: qup-spi3-default { + pinmux { + pins = "gpio41", "gpio42", + "gpio43", "gpio44"; + function = "qup3"; + }; + }; + + qup_spi3_sleep: qup-spi3-sleep { + pinmux { + pins = "gpio41", "gpio42", + "gpio43", "gpio44"; + function = "gpio"; + }; + }; + + qup_spi4_default: qup-spi4-default { + pinmux { + pins = "gpio89", "gpio90", + "gpio91", "gpio92"; + function = "qup4"; + }; + }; + + qup_spi4_sleep: qup-spi4-sleep { + pinmux { + pins = "gpio89", "gpio90", + "gpio91", "gpio92"; + function = "gpio"; + }; + }; + + qup_spi5_default: qup-spi5-default { + pinmux { + pins = "gpio85", "gpio86", + "gpio87", "gpio88"; + function = "qup5"; + }; + }; + + qup_spi5_sleep: qup-spi5-sleep { + pinmux { + pins = "gpio85", "gpio86", + "gpio87", "gpio88"; + function = "gpio"; + }; + }; + + qup_spi6_default: qup-spi6-default { + pinmux { + pins = "gpio45", "gpio46", + "gpio47", "gpio48"; + function = "qup6"; + }; + }; + + qup_spi6_sleep: qup-spi6-sleep { + pinmux { + pins = "gpio45", "gpio46", + "gpio47", "gpio48"; + function = "gpio"; + }; + }; + + qup_spi7_default: qup-spi7-default { + pinmux { + pins = "gpio93", "gpio94", + "gpio95", "gpio96"; + function = "qup7"; + }; + }; + + qup_spi7_sleep: qup-spi7-sleep { + pinmux { + pins = "gpio93", "gpio94", + "gpio95", "gpio96"; + function = "gpio"; + }; + }; + + qup_spi8_default: qup-spi8-default { + pinmux { + pins = "gpio65", "gpio66", + "gpio67", "gpio68"; + function = "qup8"; + }; + }; + + qup_spi8_sleep: qup-spi8-sleep { + pinmux { + pins = "gpio65", "gpio66", + "gpio67", "gpio68"; + function = "gpio"; + }; + }; + + qup_spi9_default: qup-spi9-default { + pinmux { + pins = "gpio6", "gpio7", + "gpio4", "gpio5"; + function = "qup9"; + }; + }; + + qup_spi9_sleep: qup-spi9-sleep { + pinmux { + pins = "gpio6", "gpio7", + "gpio4", "gpio5"; + function = "gpio"; + }; + }; + + qup_spi10_default: qup-spi10-default { + pinmux { + pins = "gpio55", "gpio56", + "gpio53", "gpio54"; + function = "qup10"; + }; + }; + + qup_spi10_sleep: qup-spi10-sleep { + pinmux { + pins = "gpio55", "gpio56", + "gpio53", "gpio54"; + function = "gpio"; + }; + }; + + qup_spi11_default: qup-spi11-default { + pinmux { + pins = "gpio31", "gpio32", + "gpio33", "gpio34"; + function = "qup11"; + }; + }; + + qup_spi11_sleep: qup-spi11-sleep { + pinmux { + pins = "gpio31", "gpio32", + "gpio33", "gpio34"; + function = "gpio"; + }; + }; + + qup_spi12_default: qup-spi12-default { + pinmux { + pins = "gpio49", "gpio50", + "gpio51", "gpio52"; + function = "qup12"; + }; + }; + + qup_spi12_sleep: qup-spi12-sleep { + pinmux { + pins = "gpio49", "gpio50", + "gpio51", "gpio52"; + function = "gpio"; + }; + }; + + qup_spi13_default: qup-spi13-default { + pinmux { + pins = "gpio105", "gpio106", + "gpio107", "gpio108"; + function = "qup13"; + }; + }; + + qup_spi13_sleep: qup-spi13-sleep { + pinmux { + pins = "gpio105", "gpio106", + "gpio107", "gpio108"; + function = "gpio"; + }; + }; + + qup_spi14_default: qup-spi14-default { + pinmux { + pins = "gpio33", "gpio34", + "gpio31", "gpio32"; + function = "qup14"; + }; + }; + + qup_spi14_sleep: qup-spi14-sleep { + pinmux { + pins = "gpio33", "gpio34", + "gpio31", "gpio32"; + function = "gpio"; + }; + }; + + qup_spi15_default: qup-spi15-default { + pinmux { + pins = "gpio81", "gpio82", + "gpio83", "gpio84"; + function = "qup15"; + }; + }; + + qup_spi15_sleep: qup-spi15-sleep { + pinmux { + pins = "gpio81", "gpio82", + "gpio83", "gpio84"; + function = "gpio"; + }; + }; + + qup_uart9_default: qup-uart9-default { + pinmux { + pins = "gpio4", "gpio5"; + function = "qup9"; + }; + }; + + qup_uart9_sleep: qup-uart9-sleep { + pinmux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + }; + + ufs_dev_reset_assert: ufs_dev_reset_assert { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * UFS_RESET driver strengths are having + * different values/steps compared to typical + * GPIO drive strengths. + * + * Following table clarifies: + * + * HDRV value | UFS_RESET | Typical GPIO + * (dec) | (mA) | (mA) + * 0 | 0.8 | 2 + * 1 | 1.55 | 4 + * 2 | 2.35 | 6 + * 3 | 3.1 | 8 + * 4 | 3.9 | 10 + * 5 | 4.65 | 12 + * 6 | 5.4 | 14 + * 7 | 6.15 | 16 + * + * POR value for UFS_RESET HDRV is 3 which means + * 3.1mA and we want to use that. Hence just + * specify 8mA to "drive-strength" binding and + * that should result into writing 3 to HDRV + * field. + */ + drive-strength = <8>; /* default: 3.1 mA */ + output-low; /* active low reset */ + }; + + ufs_dev_reset_deassert: ufs_dev_reset_deassert { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * default: 3.1 mA + * check comments under ufs_dev_reset_assert + */ + drive-strength = <8>; + output-high; /* active low reset */ + }; }; aoss_reset: qcom,reset-controller@c2b0000 { @@ -583,6 +1646,94 @@ <WAKE_TCS 3>, <ACTIVE_TCS 2>, <CONTROL_TCS 1>; + + rpmhcc: clock-controller { + compatible = "qcom,sdm845-rpmh-clk"; + #clock-cells = <1>; + }; + }; + + ufsphy: phy@1d87000 { + compatible = "qcom,sdm845-qmp-ufs-phy"; + reg = <0x1d87000 0x18c>; + #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + status = "disabled"; + + ufsphy_0: lane@0x1d87400 { + reg = <0x1d87400 0x108>, + <0x1d87600 0x1e0>, + <0x1d87c00 0x1dc>; + #phy-cells = <0>; + }; + + ufsphy_1: lane@0x1d87800 { + reg = <0x1d87800 0x108>, + <0x1d87a00 0x1e0>, + <0x1d87c00 0x1dc>; + #phy-cells = <0>; + }; + }; + + ufshc: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x2500>; + interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>; + phys = <&ufsphy_0>, <&ufsphy_1>; + phy-names = "ufsphy_0", "ufsphy_1"; + + lanes-per-direction = <2>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + + power-domains = <&gcc UFS_PHY_GDSC>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + non-removable; + pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; + pinctrl-0 = <&ufs_dev_reset_assert>; + pinctrl-1 = <&ufs_dev_reset_deassert>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "core_reset"; + + status = "disabled"; }; }; }; diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index e778af766fae..97ad56db5a5a 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -606,6 +606,9 @@ static const struct of_device_id qcom_scm_dt_match[] = { { .compatible = "qcom,scm-ipq4019", .data = NULL, /* no clocks */ }, + { .compatible = "qcom,scm-sdm845", + .data = NULL /* no clocks */ + }, { .compatible = "qcom,scm", .data = (void *)(SCM_HAS_CORE_CLK | SCM_HAS_IFACE_CLK |