diff options
| author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2020-09-05 11:40:21 +0530 |
|---|---|---|
| committer | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2020-09-19 22:24:39 +0300 |
| commit | 0af1267d63fc842e428facfd65683f1ed31bce84 (patch) | |
| tree | 9c91df5c44554cc9c27110c0b33d8bfb4ba01915 | |
| parent | 24e770e2d085580a2692cedccc65b774e0159cf7 (diff) | |
pci: controller: dwc: qcom: Harcode PCIe config SID
Hardcode the PCIe config SID table value. This is needed to avoid random
MHI failure observed during reboot on SM8250.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
[mani: stripped out unnecessary settings and ported for upstream]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-qcom.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index ca8ad354e09d..50748016ce96 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -57,6 +57,7 @@ #define PCIE20_PARF_SID_OFFSET 0x234 #define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C #define PCIE20_PARF_DEVICE_TYPE 0x1000 +#define PCIE20_PARF_BDF_TO_SID_TABLE_N 0x2000 #define PCIE20_ELBI_SYS_CTRL 0x04 #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0) @@ -1290,6 +1291,9 @@ static int qcom_pcie_host_init(struct pcie_port *pp) if (ret) goto err; + writel(0x0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N); + writel(0x01000100, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + 0x054); + return 0; err: qcom_ep_reset_assert(pcie); |