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| author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2021-03-10 16:30:31 +0530 |
|---|---|---|
| committer | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2021-03-10 16:34:37 +0530 |
| commit | 096433344896b4a926d1e4cfdb42f5836f7ee80d (patch) | |
| tree | 8c3b4652613a124f0af15b3ab9c54c3af15d8369 | |
| parent | 2f1d6e2158d872fd05a6534cbc53e4f1cc9ef25e (diff) | |
ARM: dts: qcom: sdx55: Add support for PCIe PHY
Add devicetree support for PCIe PHY used in SDX55 platform. This PHY is
used by the PCIe EP controller.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom-sdx55.dtsi | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index eceb6175b706..d29824b9a6b6 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -310,6 +310,42 @@ status = "disabled"; }; + pcie0_phy: phy@1c06000 { + compatible = "qcom,sdx55-qmp-pcie-phy"; + reg = <0x01c06000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie0_lane: lanes@1c06200 { + reg = <0x01c06000 0x104>, /* tx0 */ + <0x01c06200 0x328>, /* rx0 */ + <0x01c06800 0x104>, /* tx1 */ + <0x01c06a00 0x328>, /* rx1 */ + <0x01c07000 0x1c4>, /* serdes */ + <0x01c07200 0x1e8>, /* pcs */ + <0x01c07600 0x800>; /* pcs_misc */ + clocks = <&gcc GCC_PCIE_PIPE_CLK>; + clock-names = "pipe0"; + + #phy-cells = <0>; + clock-output-names = "pcie_pipe_clk"; + }; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x01f40000 0x40000>; |