diff options
| author | Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> | 2021-11-10 17:18:19 +0200 |
|---|---|---|
| committer | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2022-01-28 15:48:55 +0300 |
| commit | e5214583a2c1724210d5b3cde3e292adfdd1da0a (patch) | |
| tree | f300e08e4e28a6ed9d2e3d5f8a726174d3644587 | |
| parent | eac80bd610efe30e34e0ad293f5feb7940cade13 (diff) | |
arm64: dts: qcom: sm8450: add cpufreq support
The change adds a description of a SM8450 cpufreq-epss controller and
references to it from CPU nodes.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm8450.dtsi | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 76e608fa7e39..34ed8cd26862 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1064,6 +1064,21 @@ #freq-domain-cells = <1>; }; + cpufreq_hw: cpufreq@17d91000 { + compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0 0x17d91000 0 0x1000>, + <0 0x17d92000 0 0x1000>, + <0 0x17d93000 0 0x1000>; + reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; + #freq-domain-cells = <1>; + }; + gem_noc: interconnect@19100000 { compatible = "qcom,sm8450-gem-noc"; reg = <0 0x19100000 0 0xbb800>; |