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| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2021-12-02 17:17:25 +0300 |
|---|---|---|
| committer | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2022-01-28 15:50:19 +0300 |
| commit | e951ea84cc5fdbdadb30180a35b2c29073654f3b (patch) | |
| tree | 6c91c3800df3fa12b67cc5d3ebc048e3c43b3f46 | |
| parent | f35aba2f8c2f2ef8d4be7ac374571ca18637d837 (diff) | |
arm64: dts: qcom: sm8450-qrd: enable PCIe0 PHY device
Enable PCIe0 PHY on the SM8450 QRD device.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 13d702946668..64a1a2a635d9 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -345,10 +345,20 @@ }; }; +&pcie0_phy { + status = "okay"; + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; +}; + &qupv3_id_0 { status = "okay"; }; +&qupv3_id_1 { + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <28 4>, <36 4>; }; |