diff options
author | Linaro CI <ci_notify@linaro.org> | 2023-01-30 06:51:51 +0000 |
---|---|---|
committer | Linaro CI <ci_notify@linaro.org> | 2023-01-30 06:51:51 +0000 |
commit | 3d6c7f245d2ff909d1a243ff10887ef1645b8a70 (patch) | |
tree | a05da45c99e5b2340acb8e80cc10eadb64e6e963 | |
parent | 93d4b7b45334ca8683e241969599fdaf283123d8 (diff) | |
parent | de3f446154bcb84ebb6974ad9ae00dbcb72c7646 (diff) |
Merge remote-tracking branch 'sm8450-dts/tracking-qcomlt-sm8450-dts' into integration-linux-qcomlt
-rw-r--r-- | Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 1 | ||||
-rw-r--r-- | Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 16 | ||||
-rw-r--r-- | arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 205 | ||||
-rw-r--r-- | arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 94 | ||||
-rw-r--r-- | arch/arm64/boot/dts/qcom/sm8450.dtsi | 332 | ||||
-rw-r--r-- | include/dt-bindings/power/qcom-rpmpd.h | 1 |
6 files changed, 621 insertions, 28 deletions
diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml index 37d16e16f444..6aef271bd43f 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml @@ -55,6 +55,7 @@ properties: - qcom,pm8350 - qcom,pm8350b - qcom,pm8350c + - qcom,pm8450 - qcom,pm8841 - qcom,pm8909 - qcom,pm8916 diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 8da8ece1d4d7..1758d4a97bdb 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -111,18 +111,28 @@ properties: description: GPIO controlled connection to WAKE# signal maxItems: 1 + msi-map: true + + msi-map-mask: true + required: - compatible - reg - reg-names - - interrupts - - interrupt-names - - "#interrupt-cells" - interrupt-map-mask - interrupt-map - clocks - clock-names +oneOf: + - required: + - interrupts + - interrupt-names + - "#interrupt-cells" + - required: + - msi-map + - msi-map-mask + allOf: - $ref: /schemas/pci/pci-bus.yaml# - if: diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 4de3e1f1c39c..ab97c083ef50 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -8,6 +8,13 @@ #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> #include "sm8450.dtsi" +#include "pm8350.dtsi" +#include "pm8350b.dtsi" +#include "pm8350c.dtsi" +#include "pm8450.dtsi" +#include "pmk8350.dtsi" +#include "pmr735a.dtsi" +#include "pmr735b.dtsi" / { model = "Qualcomm Technologies, Inc. SM8450 HDK"; @@ -15,12 +22,46 @@ aliases { serial0 = &uart7; + serial1 = &uart20; }; chosen { stdout-path = "serial0:115200n8"; }; + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + + lt9611_1v2: lt9611-vdd12-regulator { + compatible = "regulator-fixed"; + regulator-name = "LT9611_1V2"; + + vin-supply = <&vph_pwr>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&tlmm 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + lt9611_3v3: lt9611-3v3 { + compatible = "regulator-fixed"; + regulator-name = "LT9611_3V3"; + + vin-supply = <&vreg_bob>; + gpio = <&tlmm 109 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -30,6 +71,24 @@ regulator-always-on; regulator-boot-on; }; + + wcn6856: wcn6856 { + compatible = "qcom,wcn6855"; + #power-domain-cells = <0>; + + vddaon-supply = <&vreg_s11b_0p95>; + vddcx-supply = <&vreg_s11b_0p95>; + vddmx-supply = <&vreg_s2e_0p85>; + vddrfa1-supply = <&vreg_s1c_1p86>; + vddrfa2-supply = <&vreg_s12b_1p25>; + vddio-supply = <&vreg_s10b_1p8>; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en_state &xo_clk_state>; + + xo-clk-gpios = <&tlmm 204 GPIO_ACTIVE_HIGH>; + wlan-en-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>; + }; }; &apps_rsc { @@ -149,7 +208,7 @@ vreg_s1c_1p86: smps1 { regulator-name = "vreg_s1c_1p86"; - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <1900000>; regulator-max-microvolt = <2024000>; }; @@ -302,7 +361,7 @@ vreg_s2e_0p85: smps2 { regulator-name = "vreg_s2e_0p85"; - regulator-min-microvolt = <500000>; + regulator-min-microvolt = <1012000>; regulator-max-microvolt = <1040000>; }; @@ -350,6 +409,79 @@ }; }; +&dispcc { + status = "okay"; +}; + +&i2c9 { + status = "okay"; + clock-frequency = <400000>; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + + interrupts-extended = <&tlmm 44 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&tlmm 107 GPIO_ACTIVE_HIGH>; + + vdd-supply = <<9611_1v2>; + vcc-supply = <<9611_3v3>; + + pinctrl-names = "default"; + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + vdda-supply = <&vreg_l6b_1p2>; + + ports { + port@1 { + endpoint { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; + }; + }; + }; + +}; + +&dsi0_phy { + status = "okay"; + vdds-supply = <&vreg_l5b_0p88>; +}; + &pcie0 { status = "okay"; max-link-speed = <2>; @@ -359,6 +491,8 @@ status = "okay"; vdda-phy-supply = <&vreg_l5b_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; + + power-domains = <&wcn6856>; }; &pcie1 { @@ -395,6 +529,14 @@ status = "okay"; }; +&qupv3_id_1 { + status = "okay"; +}; + +&qupv3_id_2 { + status = "okay"; +}; + &sdhc_2 { cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>; pinctrl-names = "default", "sleep"; @@ -564,18 +706,77 @@ &tlmm { gpio-reserved-ranges = <28 4>, <36 4>; + bt_en_state: bt-default-state { + bt-en { + pins = "gpio81"; + function = "gpio"; + + drive-strength = <16>; + output-low; + bias-pull-up; + }; + }; + + lt9611_irq_pin: lt9611-irq { + pins = "gpio44"; + function = "gpio"; + bias-disable; + }; + + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio107"; + function = "normal"; + + output-high; + input-disable; + }; + sdc2_card_det_n: sd-card-det-n-state { pins = "gpio92"; function = "gpio"; drive-strength = <2>; bias-pull-up; }; + + xo_clk_state: xo_clk_state { + pinconf { + pins = "gpio204"; + function = "gpio"; + + drive-strength = <16>; + output-low; + bias-pull-down; + }; + }; + + wlan_en_state: wlan_en_state { + pinconf { + pins = "gpio80"; + function = "gpio"; + + drive-strength = <16>; + output-low; + bias-pull-down; + }; + }; }; &uart7 { status = "okay"; }; +&uart20 { + status = "okay"; + bluetooth { + /* a little lie */ + compatible = "qcom,wcn6855-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_state>; + power-domains = <&wcn6856>; + enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; + }; +}; + &ufs_mem_hc { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index ee62514fff68..568a4ceaf399 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -7,6 +7,13 @@ #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sm8450.dtsi" +#include "pm8350.dtsi" +#include "pm8350b.dtsi" +#include "pm8350c.dtsi" +#include "pm8450.dtsi" +#include "pmk8350.dtsi" +#include "pmr735a.dtsi" +#include "pmr735b.dtsi" / { model = "Qualcomm Technologies, Inc. SM8450 QRD"; @@ -14,6 +21,7 @@ aliases { serial0 = &uart7; + serial1 = &uart20; }; chosen { @@ -29,6 +37,24 @@ regulator-always-on; regulator-boot-on; }; + + wcn6856: wcn6856 { + compatible = "qcom,wcn6855"; + #power-domain-cells = <0>; + + vddaon-supply = <&vreg_s11b_0p95>; + vddcx-supply = <&vreg_s11b_0p95>; + vddmx-supply = <&vreg_s2e_0p85>; + vddrfa1-supply = <&vreg_s1c_1p86>; + vddrfa2-supply = <&vreg_s12b_1p25>; + vddio-supply = <&vreg_s10b_1p8>; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en_state &xo_clk_state>; + + xo-clk-gpios = <&tlmm 204 GPIO_ACTIVE_HIGH>; + wlan-en-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>; + }; }; &apps_rsc { @@ -63,13 +89,13 @@ vreg_s11b_0p95: smps11 { regulator-name = "vreg_s11b_0p95"; - regulator-min-microvolt = <848000>; + regulator-min-microvolt = <966000>; regulator-max-microvolt = <1104000>; }; vreg_s12b_1p25: smps12 { regulator-name = "vreg_s12b_1p25"; - regulator-min-microvolt = <1224000>; + regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1400000>; }; @@ -147,7 +173,7 @@ vreg_s1c_1p86: smps1 { regulator-name = "vreg_s1c_1p86"; - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <1900000>; regulator-max-microvolt = <2024000>; }; @@ -300,8 +326,8 @@ vreg_s2e_0p85: smps2 { regulator-name = "vreg_s2e_0p85"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1040000>; + regulator-min-microvolt = <1012000>; + regulator-max-microvolt = <1012000>; }; vreg_l1e_0p8: ldo1 { @@ -339,17 +365,26 @@ regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; + + vreg_l7e_2p8: ldo7 { + regulator-name = "vreg_l7e_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; }; }; &pcie0 { status = "okay"; + max-link-speed = <2>; }; &pcie0_phy { status = "okay"; vdda-phy-supply = <&vreg_l5b_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; + + power-domains = <&wcn6856>; }; &gpi_dma0 { @@ -368,6 +403,10 @@ status = "okay"; }; +&qupv3_id_2 { + status = "okay"; +}; + &remoteproc_adsp { status = "okay"; firmware-name = "qcom/sm8450/adsp.mbn"; @@ -415,18 +454,63 @@ &tlmm { gpio-reserved-ranges = <28 4>, <36 4>; + bt_en_state: bt-default-state { + bt-en { + pins = "gpio81"; + function = "gpio"; + + drive-strength = <16>; + output-low; + bias-pull-up; + }; + }; + sdc2_card_det_n: sd-card-det-n-state { pins = "gpio92"; function = "gpio"; drive-strength = <2>; bias-pull-up; }; + + xo_clk_state: xo_clk_state { + pinconf { + pins = "gpio204"; + function = "gpio"; + + drive-strength = <16>; + output-low; + bias-pull-down; + }; + }; + + wlan_en_state: wlan_en_state { + pinconf { + pins = "gpio80"; + function = "gpio"; + + drive-strength = <16>; + output-low; + bias-pull-down; + }; + }; }; &uart7 { status = "okay"; }; +&uart20 { + status = "okay"; + bluetooth { + /* a little lie */ + compatible = "qcom,wcn6855-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_state>; + power-domains = <&wcn6856>; + enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; + }; +}; + &ufs_mem_hc { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 55e8a77a19ae..90007e3b7bee 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1742,9 +1742,9 @@ ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; - #interrupt-cells = <1>; + msi-map = <0x0 &gic_its 0x5980 0x1>, + <0x100 &gic_its 0x5981 0x1>; + msi-map-mask = <0xff00>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ @@ -1851,9 +1851,9 @@ ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; - #interrupt-cells = <1>; + msi-map = <0x0 &gic_its 0x5a01 0x1>, + <0x100 &gic_its 0x5a00 0x1>; + msi-map-mask = <0xff00>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ @@ -2655,6 +2655,282 @@ status = "disabled"; }; + mdss: mdss@ae00000 { + compatible = "qcom,sm8450-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + /* same path used twice */ + interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, + <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x2800 0x402>; + + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mdss_mdp: mdp@ae01000 { + compatible = "qcom,sm8450-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + + }; + + mdp_opp_table: mdp-opp-table { + compatible = "operating-points-v2"; + + opp-172000000 { + opp-hz = /bits/ 64 <172000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: dsi-phy@ae94400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + dsi1: dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: dsi-phy@ae96400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + + dsi_opp_table: dsi-opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,sm8450-dispcc"; reg = <0 0x0af00000 0 0x20000>; @@ -2662,10 +2938,8 @@ <&rpmhcc RPMH_CXO_CLK_A>, <&gcc GCC_DISP_AHB_CLK>, <&sleep_clk>, - <0>, /* dsi0 */ - <0>, - <0>, /* dsi1 */ - <0>, + <&dsi0_phy 0>, <&dsi0_phy 1>, + <&dsi1_phy 0>, <&dsi1_phy 1>, <0>, /* dp0 */ <0>, <0>, /* dp1 */ @@ -2733,6 +3007,24 @@ #mbox-cells = <2>; }; + spmi_bus: spmi@c42d000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x0c400000 0x0 0x00003000>, + <0x0 0x0c500000 0x0 0x00400000>, + <0x0 0x0c440000 0x0 0x00080000>, + <0x0 0x0c4c0000 0x0 0x00010000>, + <0x0 0x0c42d000 0x0 0x00010000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + tlmm: pinctrl@f100000 { compatible = "qcom,sm8450-tlmm"; reg = <0 0x0f100000 0 0x300000>; @@ -3589,35 +3881,39 @@ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; }; - rpmhpd_opp_low_svs: opp3 { + rpmhpd_opp_low_svs_d1: opp3 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; + }; + + rpmhpd_opp_low_svs: opp4 { opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; }; - rpmhpd_opp_svs: opp4 { + rpmhpd_opp_svs: opp5 { opp-level = <RPMH_REGULATOR_LEVEL_SVS>; }; - rpmhpd_opp_svs_l1: opp5 { + rpmhpd_opp_svs_l1: opp6 { opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; }; - rpmhpd_opp_nom: opp6 { + rpmhpd_opp_nom: opp7 { opp-level = <RPMH_REGULATOR_LEVEL_NOM>; }; - rpmhpd_opp_nom_l1: opp7 { + rpmhpd_opp_nom_l1: opp8 { opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; }; - rpmhpd_opp_nom_l2: opp8 { + rpmhpd_opp_nom_l2: opp9 { opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; }; - rpmhpd_opp_turbo: opp9 { + rpmhpd_opp_turbo: opp10 { opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; }; - rpmhpd_opp_turbo_l1: opp10 { + rpmhpd_opp_turbo_l1: opp11 { opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; }; }; diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 1e19e258a74d..278de6df425e 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -190,6 +190,7 @@ /* SDM845 Power Domain performance levels */ #define RPMH_REGULATOR_LEVEL_RETENTION 16 #define RPMH_REGULATOR_LEVEL_MIN_SVS 48 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56 #define RPMH_REGULATOR_LEVEL_LOW_SVS 64 #define RPMH_REGULATOR_LEVEL_SVS 128 #define RPMH_REGULATOR_LEVEL_SVS_L0 144 |