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2019-10-03Merge remote-tracking branch 'cpuidle/wrk3/automerge/idle-branch' into ↵integration-linux-qcomlt-20191003-065154-v5.4-rc1-171-ga4c3ee14f7e8bLinaro CI
integration-linux-qcomlt
2019-10-03Merge remote-tracking branch 'sm8150-misc/tracking-qcomlt-sm8150-misc' into ↵Linaro CI
integration-linux-qcomlt
2019-10-03Merge remote-tracking branch ↵Linaro CI
'sm8150-defconf/tracking-qcomlt-sm8150-defconfig' into integration-linux-qcomlt # Conflicts: # arch/arm64/configs/defconfig
2019-10-03Merge remote-tracking branch 'sm8150-dt/tracking-qcomlt-sm8150-dt' into ↵Linaro CI
integration-linux-qcomlt # Conflicts: # arch/arm64/boot/dts/qcom/Makefile # arch/arm64/boot/dts/qcom/sm8150-mtp.dts # arch/arm64/boot/dts/qcom/sm8150.dtsi
2019-10-03Merge remote-tracking branch 'sm8150-gcc/tracking-qcomlt-sm8150-gcc' into ↵Linaro CI
integration-linux-qcomlt
2019-10-03Merge remote-tracking branch 'qcs404-cpufreq/tracking-qcomlt-qcs404-cpufreq' ↵Linaro CI
into integration-linux-qcomlt
2019-10-03Merge remote-tracking branch 'qcs404-dt/tracking-qcomlt-qcs404-dt' into ↵Linaro CI
integration-linux-qcomlt
2019-10-03Merge remote-tracking branch ↵Linaro CI
'qcs404-defconfig/tracking-qcomlt-qcs404-defconfig' into integration-linux-qcomlt # Conflicts: # arch/arm64/configs/defconfig
2019-10-03Merge remote-tracking branch 'thermal/wrk3/automerge/thermal-branch' into ↵Linaro CI
integration-linux-qcomlt # Conflicts: # arch/arm64/boot/dts/qcom/pms405.dtsi
2019-10-03Merge remote-tracking branch 'sdm845-db845c/tracking-qcomlt-sdm845-db845c' ↵Linaro CI
into integration-linux-qcomlt # Conflicts: # arch/arm64/boot/dts/qcom/sdm845-db845c.dts
2019-10-03Merge remote-tracking branch 'sdm845-pcie/tracking-qcomlt-sdm845-pcie' into ↵Linaro CI
integration-linux-qcomlt
2019-10-03Merge remote-tracking branch ↵Linaro CI
'distro.config/tracking-qcomlt-config-fragments' into integration-linux-qcomlt
2019-10-03Merge remote-tracking branch ↵Linaro CI
'arm64-defconfig/tracking-qcomlt-arm64-defconfig' into integration-linux-qcomlt # Conflicts: # arch/arm64/configs/defconfig
2019-10-03Merge remote-tracking branch 'ufs/tracking-qcomlt-ufs' into ↵Linaro CI
integration-linux-qcomlt
2019-10-03Merge remote-tracking branch 'iommu/tracking-qcomlt-iommu' into ↵Linaro CI
integration-linux-qcomlt
2019-10-03Merge remote-tracking branch 'drm-msm/tracking-qcomlt-drm-msm' into ↵Linaro CI
integration-linux-qcomlt
2019-10-03Merge remote-tracking branch ↵Linaro CI
'fixes/tracking-qcomlt-fixes-without-devfreq-reverts' into integration-linux-qcomlt
2019-10-03Merge remote-tracking branch 'audio/tracking-qcomlt-audio' into ↵Linaro CI
integration-linux-qcomlt
2019-10-03Merge remote-tracking branch 'wcd9335/tracking-qcomlt-wcd9335' into ↵Linaro CI
integration-linux-qcomlt
2019-10-03Merge remote-tracking branch 'msm8996-dt/tracking-qcomlt-msm8996-dt' into ↵Linaro CI
integration-linux-qcomlt
2019-10-02arm64: config: Enable db845c relates configsBjorn Andersson
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-10-02arm64: dts: qcom: sdm845: Add APSS watchdog nodeBjorn Andersson
Add a node describing the watchdog found in the application subsystem. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-10-02arm64: dts: db845c: add Low speed expansion i2c and spi nodesSrinivas Kandagatla
This patch adds support UART0, I2C0, I2C1 and SPI0 available on Low Speed expansion connector. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
2019-10-02arm64: dts: db845c: add support to analog audioSrinivas Kandagatla
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
2019-10-02arm64: dts: sdm845: add support to hexagon dsp audio supportSrinivas Kandagatla
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
2019-10-02arm64: dts: qcom: db845c: Enable LVS 1 and 2Bjorn Andersson
vreg_lvs1a_1p8 and vreg_lvs2a_1p8 are both feeding pins in the low speed connectors and should as such alway be on, so enable them. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-10-02arm64: dts: qcom: db845c: Enable PCIe controllersBjorn Andersson
Enable the two PCIe controllers found on the Dragonboard845c. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-10-02arm64: dts: qcom: sdm845: Add second PCIe PHY and controllerBjorn Andersson
Add the second PCIe controller and the associated QHP PHY found on SDM845. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-10-02arm64: dts: qcom: sdm845: Add first PCIe controller and PHYBjorn Andersson
Add the GEN2 PCIe controller and PHY found on SDM845. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-10-02PCI: qcom: Add support for SDM845 PCIe controllerBjorn Andersson
The SDM845 has one Gen2 and one Gen3 controller, add support for these. Due to lack of hardware only the Gen2 controller has been verified. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-10-02PCI: qcom: Fix the fixup of PCI_VENDOR_ID_QCOMBjorn Andersson
There exists non-bridge PCIe devices with PCI_VENDOR_ID_QCOM, so limit the fixup to only affect the PCIe 2.0 (0x106) and PCIe 3.0 (0x107) bridges. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-10-02dt-bindings: PCI: qcom: Add support for SDM845 PCIeBjorn Andersson
Add compatible and necessary clocks and resets definitions for the SDM845 PCIe controller. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-10-02phy: qcom: qmp: Add SDM845 QHP PCIe PHYBjorn Andersson
Add the GEN3 QHP PCIe PHY found in SDM845. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-10-02phy: qcom: qmp: Add SDM845 PCIe QMP PHY supportBjorn Andersson
qcom_qmp_phy_init() is extended to support the additional register writes needed in PCS MISC and the appropriate sequences and resources are defined for the GEN2 PCIe QMP PHY found in SDM845. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-10-02phy: qcom: qmp: Use power_on/off ops for PCIeBjorn Andersson
The PCIe PHY needs to be initialized as part of the PCI initialization and should therefore implement the power_on/power_off ops, rather than init/exit. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-10-02phy: qcom-qmp: Increase PHY ready timeoutBjorn Andersson
It's typical for the QHP PHY to take slightly above 1ms to initialize, so increase the timeout of the PHY ready check to 10ms - as already done in the downstream PCIe driver. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-10-02dt-bindings: phy-qcom-qmp: Add SDM845 PCIe to bindingBjorn Andersson
Add the compatible and define necessary clocks and resets for the SDM845 GEN2 QMP PCIe phy and GEN3 QHP PCIe phy. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-10-02usb: xhci: provide a debugfs hook for erasing romVinod Koul
run "echo 4 > /sys/kernel/debug/renesas-usb/rom_erase" to erase firmware when driver is loaded Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-10-02usb: xhci: allow multiple firmware versionsVinod Koul
Allow multiple firmware file versions in table and load them in increasing order as we find them in the file system. Signed-off-by: Vinod Koul <vkoul@kernel.org> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Cc: Christian Lamparter <chunkeey@googlemail.com>
2019-10-02usb: xhci: Add ROM loader for uPD720201Vinod Koul
uPD720201 supports ROM and allows software to program the ROM and boot from it. Add support for detecting if ROM is present, if so load the ROM if not programmed earlier. Signed-off-by: Vinod Koul <vkoul@kernel.org> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Cc: Christian Lamparter <chunkeey@googlemail.com>
2019-10-02usb: xhci: Use register defined and field namesVinod Koul
Instead of using register values and fields lets define them and use in the driver. Signed-off-by: Vinod Koul <vkoul@kernel.org> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Cc: Christian Lamparter <chunkeey@googlemail.com>
2019-10-02usb: xhci: handle uPD720201 and uPD720202 w/o ROMChristian Lamparter
This patch adds a firmware check for the uPD720201K8-711-BAC-A and uPD720202K8-711-BAA-A variant. Both of these chips are listed in Renesas' R19UH0078EJ0500 Rev.5.00 "User's Manual: Hardware" as devices which need a firmware in order to work as they do not have support to load the firmware from an external ROM. Currently, the xhci-pci driver is unable to initialize the hcd in this case. Instead it will wait for 30 seconds and cause a timeout in xhci_handshake() and fails. [ 5.116990] xhci_hcd 0000:45:00.0: new USB bus registered ... [ 32.335215] xhci_hcd 0000:45:00.0: can't setup: -110 [ 32.340179] xhci_hcd 0000:45:00.0: USB bus 2 deregistered [ 32.345587] xhci_hcd 0000:45:00.0: init 0000:45:00.0 fail, -110 [ 32.351496] xhci_hcd: probe of 0000:45:00.0 failed with error -110 Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-10-02usb: xhci: add firmware loader for uPD720201 and uPD720202 w/o ROMChristian Lamparter
This patch adds a firmware loader for the uPD720201K8-711-BAC-A and uPD720202K8-711-BAA-A variant. Both of these chips are listed in Renesas' R19UH0078EJ0500 Rev.5.00 "User's Manual: Hardware" as devices which need the firmware loader on page 2 in order to work as they "do not support the External ROM". The "Firmware Download Sequence" is describe in chapter "7.1 FW Download Interface" R19UH0078EJ0500 Rev.5.00 page 131. The firmware "K2013080.mem" is available from a USB3.0 Host to PCIe Adapter (PP2U-E card) "Firmware download" archive. An alternative version can be sourced from Netgear's WNDR4700 GPL archives. The release notes of the PP2U-E's "Firmware Download" ver 2.0.1.3 (2012-06-15) state that the firmware is for the following devices: - uPD720201 ES 2.0 sample whose revision ID is 2. - uPD720201 ES 2.1 sample & CS sample & Mass product, ID is 3. - uPD720202 ES 2.0 sample & CS sample & Mass product, ID is 2. Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Christian Lamparter <chunkeey@googlemail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> [vkoul: fixed comments: used macros for timeout count and delay removed renesas_fw_alive_check cleaned renesas_fw_callback removed recurion for renesas_fw_download added MODULE_FIRMWARE] Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-10-02phy: qcom-qmp: Add SM8150 QMP UFS PHY supportVinod Koul
SM8150 UFS PHY is v4 of QMP phy. Add support for V4 QMP phy register defines and support for SM8150 QMP UFS PHY. Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-10-02clk: qcom: hfpll: CLK_IGNORE_UNUSEDJorge Ramirez-Ortiz
When COMMON_CLK_DISABLED_UNUSED is set, in an effort to save power and to keep the software model of the clock in line with reality, the framework transverses the clock tree and disables those clocks that were enabled by the firmware but have not been enabled by any device driver. If CPUFREQ is enabled, early during the system boot, it might attempt to change the CPU frequency ("set_rate"). If the HFPLL is selected as a provider, it will then change the rate for this clock. As boot continues, clk_disable_unused_subtree will run. Since it wont find a valid counter (enable_count) for a clock that is actually enabled it will attempt to disable it which will cause the CPU to stop. Notice that in this driver, calls to check whether the clock is enabled are routed via the is_enabled callback which queries the hardware. The following commit, rather than marking the clock critical and forcing the clock to be always enabled, addresses the above scenario making sure the clock is not disabled but it continues to rely on the firmware to enable the clock. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-10-02clk: qcom: hfpll: register as clock providerJorge Ramirez-Ortiz
Make the output of the high frequency pll a clock provider. On the QCS404 this PLL controls cpu frequency scaling. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Stephen Boyd <sboyd@kernel.org>
2019-10-02clk: qcom: hfpll: get parent clock names from DTJorge Ramirez-Ortiz
Allow accessing the parent clock name required for the driver operation using the device tree node. This permits extending the driver to other platforms without having to modify its source code. For backwards compatibility leave the previous value as default. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-10-02clk: qcom: apcs-msm8916: get parent clock names from DTJorge Ramirez-Ortiz
Allow accessing the parent clock names required for the driver operation by using the device tree node. This permits extending the driver to other platforms without having to modify its source code. For backwards compatibility leave previous values as default. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-10-02dt-bindings: mailbox: qcom: Add clock-name optional propertyJorge Ramirez-Ortiz
When the APCS clock is registered (platform dependent), it retrieves its parent names from hardcoded values in the driver. The following commit allows the DT node to provide such clock names to the platform data based clock driver therefore avoiding having to explicitly embed those names in the clock driver source code. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-10-02clk: qcom: gcc: limit GPLL0_AO_OUT operating frequencyJorge Ramirez-Ortiz
Limit the GPLL0_AO_OUT_MAIN operating frequency as per its hardware specifications. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-10 13:00:22 +0000