diff options
| author | Bjorn Andersson <bjorn.andersson@linaro.org> | 2019-05-15 16:14:52 -0700 |
|---|---|---|
| committer | Julan Hsu <julanhsu@google.com> | 2019-08-23 06:01:17 +0000 |
| commit | 5d771cb040f6022f5505b702d40bf3780985826f (patch) | |
| tree | 6d759d7f6c71990b5a6688ad75542e399d7e7783 | |
| parent | 604459dea80f050f690b7a11ba29d5b60834287f (diff) | |
CHROMIUM: arm64: dts: qcom: qcs404: Define SMMU
The QCS404 sports a SMMU500. Introduce this in devicetree, so that we
can wire up the CDSP compute banks to it.
BUG=b:137202421
TEST=Run label_image in loop
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Abhinav Asati <asatiabhi@codeaurora.org>
(cherry picked from commit ff4d260a163bde23080fccf0052a68c9358c255a
https://github.com/ldts/qualcomm-lt-kernel/commits/chromiumos-4.14-iommu-mmap-gw-rebased-for-next)
Change-Id: I836e91f4f8048285781266ded13430cd3cc1afb8
Signed-off-by: Vamsi Singamsetty <vamssi@codeaurora.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/1613946
Reviewed-by: Julan Hsu <julanhsu@google.com>
Tested-by: Julan Hsu <julanhsu@google.com>
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/qcs404.dtsi | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 2d4175bc0a3e..80d4871311fc 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -663,6 +663,50 @@ reg = <0x01905000 0x20000>; }; + apps_iommu: iommu@1e20000 { + compatible = "qcom,qcs404-smmu", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x1e00000 0x40000>; + + #global-interrupts = <1>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names = "iface", "bus"; + #iommu-cells = <1>; + }; + spmi_bus: spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0200f000 0x001000>, |