diff options
| author | Georgi Djakov <georgi.djakov@linaro.org> | 2016-07-14 16:32:50 +0300 |
|---|---|---|
| committer | Srinivas Kandagatla <srinivas.kandagatla@linaro.org> | 2017-04-13 13:52:34 +0200 |
| commit | 2230913612b8b3b6a4a29874ed90953ca62a7695 (patch) | |
| tree | 32d27e905568736b592b9e58579214a6157c6435 | |
| parent | 47e721a05ad5ea179cfd345ea4743c9738d38107 (diff) | |
arm64: dts: msm8916: Add a shared CPU opp table
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/msm8916.dtsi | 23 |
1 files changed, 19 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 20e6b0a06a95..feba63745050 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -111,8 +111,8 @@ reg = <0x0>; next-level-cache = <&L2_0>; clocks = <&apcs 0>; - clock-latency = <200000>; cpu-supply = <&pm8916_spmi_s2>; + operating-points-v2 = <&cpu_opp_table>; }; CPU1: cpu@1 { @@ -121,8 +121,8 @@ reg = <0x1>; next-level-cache = <&L2_0>; clocks = <&apcs 0>; - clock-latency = <200000>; cpu-supply = <&pm8916_spmi_s2>; + operating-points-v2 = <&cpu_opp_table>; }; CPU2: cpu@2 { @@ -131,8 +131,8 @@ reg = <0x2>; next-level-cache = <&L2_0>; clocks = <&apcs 0>; - clock-latency = <200000>; cpu-supply = <&pm8916_spmi_s2>; + operating-points-v2 = <&cpu_opp_table>; }; CPU3: cpu@3 { @@ -141,8 +141,8 @@ reg = <0x3>; next-level-cache = <&L2_0>; clocks = <&apcs 0>; - clock-latency = <200000>; cpu-supply = <&pm8916_spmi_s2>; + operating-points-v2 = <&cpu_opp_table>; }; L2_0: l2-cache { @@ -167,6 +167,21 @@ method = "smc"; }; + /* + * The CPR driver reads the initial voltage settings in efuse + * and populates OPPs. + */ + cpu_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1050000>; + clock-latency-ns = <200000>; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>; |