diff options
author | Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> | 2022-02-28 13:02:24 +0200 |
---|---|---|
committer | Vinod Koul <vkoul@kernel.org> | 2022-08-19 17:41:14 +0530 |
commit | 8e06467233bfa1ca94b881e78a04f91932fbe468 (patch) | |
tree | 91de0aeab877027b775060a9f5aafe469b5d507e | |
parent | 568035b01cfb107af8d2e4bd2fb9aea22cf5b868 (diff) |
clk: qcom: sm8450-camcc: add SM8450 ES variant
Add support of camera clock controller on QCOM SM8450 ES variant.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
-rw-r--r-- | drivers/clk/qcom/camcc-sm8450.c | 54 |
1 files changed, 53 insertions, 1 deletions
diff --git a/drivers/clk/qcom/camcc-sm8450.c b/drivers/clk/qcom/camcc-sm8450.c index e3c09471dadf..f7aaeb944eb0 100644 --- a/drivers/clk/qcom/camcc-sm8450.c +++ b/drivers/clk/qcom/camcc-sm8450.c @@ -175,7 +175,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { }, }; -static const struct alpha_pll_config cam_cc_pll2_config = { +static struct alpha_pll_config cam_cc_pll2_config = { .l = 0x32, .alpha = 0x0, .config_ctl_val = 0x90008820, @@ -867,6 +867,15 @@ static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { { } }; +static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src_es[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(432000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + { } +}; + static struct clk_rcg2 cam_cc_ife_0_clk_src = { .cmd_rcgr = 0x11018, .mnd_width = 0, @@ -891,6 +900,15 @@ static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = { { } }; +static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src_es[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(432000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + { } +}; + static struct clk_rcg2 cam_cc_ife_1_clk_src = { .cmd_rcgr = 0x12018, .mnd_width = 0, @@ -914,6 +932,14 @@ static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = { { } }; +static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src_es[] = { + F(432000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + { } +}; + static struct clk_rcg2 cam_cc_ife_2_clk_src = { .cmd_rcgr = 0x12064, .mnd_width = 0, @@ -1161,6 +1187,14 @@ static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = { { } }; +static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src_es[] = { + F(432000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + { } +}; + static struct clk_rcg2 cam_cc_sfe_0_clk_src = { .cmd_rcgr = 0x13064, .mnd_width = 0, @@ -1184,6 +1218,14 @@ static const struct freq_tbl ftbl_cam_cc_sfe_1_clk_src[] = { { } }; +static const struct freq_tbl ftbl_cam_cc_sfe_1_clk_src_es[] = { + F(432000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + { } +}; + static struct clk_rcg2 cam_cc_sfe_1_clk_src = { .cmd_rcgr = 0x130ac, .mnd_width = 0, @@ -2817,6 +2859,7 @@ static const struct qcom_cc_desc cam_cc_sm8450_desc = { static const struct of_device_id cam_cc_sm8450_match_table[] = { { .compatible = "qcom,sm8450-camcc" }, + { .compatible = "qcom,sm8450es-camcc" }, { } }; MODULE_DEVICE_TABLE(of, cam_cc_sm8450_match_table); @@ -2825,6 +2868,15 @@ static int cam_cc_sm8450_probe(struct platform_device *pdev) { struct regmap *regmap; + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8450es-camcc")) { + cam_cc_pll2_config.config_ctl_val = 0x90008830; + cam_cc_ife_0_clk_src.freq_tbl = ftbl_cam_cc_ife_0_clk_src_es; + cam_cc_ife_1_clk_src.freq_tbl = ftbl_cam_cc_ife_1_clk_src_es; + cam_cc_ife_2_clk_src.freq_tbl = ftbl_cam_cc_ife_2_clk_src_es; + cam_cc_sfe_0_clk_src.freq_tbl = ftbl_cam_cc_sfe_0_clk_src_es; + cam_cc_sfe_1_clk_src.freq_tbl = ftbl_cam_cc_sfe_1_clk_src_es; + } + regmap = qcom_cc_map(pdev, &cam_cc_sm8450_desc); if (IS_ERR(regmap)) return PTR_ERR(regmap); |