diff options
author | Andrey Konovalov <andrey.konovalov@linaro.org> | 2012-09-21 01:55:08 +0400 |
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committer | Andrey Konovalov <andrey.konovalov@linaro.org> | 2012-09-21 01:55:08 +0400 |
commit | 13e6bbdf5e6e44b2168dbc876d8bba61d28f29c7 (patch) | |
tree | 374b750b2e741ca9833b875a910f475d597c0521 | |
parent | 8e287e53dcbdb6ef621b0bc6d7eaf5e7fa2bf94d (diff) | |
parent | ffb66d370de41ad36b249cd9621f58d3a27ecf21 (diff) |
Automatically merging tracking-previous-armlt-arm-arch-fixes into merge-linux-linaro-trackingllt-20120921.0
Conflicting files:
-rw-r--r-- | arch/arm/mm/cache-l2x0.c | 13 | ||||
-rw-r--r-- | arch/arm/mm/context.c | 45 | ||||
-rw-r--r-- | arch/arm/mm/proc-v7-2level.S | 10 |
3 files changed, 40 insertions, 28 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index eaa6847eea4..9f3f2a8d9dd 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -360,9 +360,6 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) l2x0_cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); - aux &= aux_mask; - aux |= aux_val; - /* Determine the number of ways */ switch (l2x0_cache_id & L2X0_CACHE_ID_PART_MASK) { case L2X0_CACHE_ID_PART_L310: @@ -376,6 +373,13 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) sync_reg_offset = L2X0_DUMMY_REG; #endif outer_cache.set_debug = pl310_set_debug; + + /* + * Set bit 22 in the auxiliary control register. If this bit + * is cleared, PL310 treats Normal Shared Non-cacheable + * accesses as Cacheable no-allocate. + */ + aux_val |= 1 << 22; break; case L2X0_CACHE_ID_PART_L210: l2x0_ways = (aux >> 13) & 0xf; @@ -407,6 +411,9 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) /* Make sure that I&D is not locked down when starting */ l2x0_unlock(l2x0_cache_id); + aux &= aux_mask; + aux |= aux_val; + /* l2x0 controller is disabled */ writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL); diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index f988a7284df..efa413ad3bc 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c @@ -23,18 +23,32 @@ DEFINE_PER_CPU(struct mm_struct *, current_mm); #endif #ifdef CONFIG_ARM_LPAE -#define cpu_set_asid(asid) { \ - unsigned long ttbl, ttbh; \ - asm volatile( \ - " mrrc p15, 0, %0, %1, c2 @ read TTBR0\n" \ - " mov %1, %2, lsl #(48 - 32) @ set ASID\n" \ - " mcrr p15, 0, %0, %1, c2 @ set TTBR0\n" \ - : "=&r" (ttbl), "=&r" (ttbh) \ - : "r" (asid & ~ASID_MASK)); \ +static void cpu_set_reserved_ttbr0(void) +{ + unsigned long ttbl = __pa(swapper_pg_dir); + unsigned long ttbh = 0; + + /* + * Set TTBR0 to swapper_pg_dir. Note that swapper_pg_dir only contains + * global entries so the ASID value is not relevant. + */ + asm volatile( + " mcrr p15, 0, %0, %1, c2 @ set TTBR0\n" + : + : "r" (ttbl), "r" (ttbh)); + isb(); } #else -#define cpu_set_asid(asid) \ - asm(" mcr p15, 0, %0, c13, c0, 1\n" : : "r" (asid)) +static void cpu_set_reserved_ttbr0(void) +{ + u32 ttb; + /* Copy TTBR1 into TTBR0 */ + asm volatile( + " mrc p15, 0, %0, c2, c0, 1 @ read TTBR1\n" + " mcr p15, 0, %0, c2, c0, 0 @ set TTBR0\n" + : "=r" (ttb)); + isb(); +} #endif /* @@ -49,15 +63,7 @@ void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) static void flush_context(void) { - u32 ttb; - - /* set the reserved ASID before flushing the TLB */ - cpu_set_asid(0); - /* Copy TTBR1 into TTBR0 */ - asm volatile("mrc p15, 0, %0, c2, c0, 1\n" - "mcr p15, 0, %0, c2, c0, 0" - : "=r" (ttb)); - isb(); + cpu_set_reserved_ttbr0(); local_flush_tlb_all(); if (icache_is_vivt_asid_tagged()) { __flush_icache_all(); @@ -117,6 +123,7 @@ static void reset_context(void *info) flush_context(); set_mm_context(mm, asid); + /* set the new ASID */ cpu_switch_mm(mm->pgd, mm); } diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S index 3a4b3e7b888..72270482a92 100644 --- a/arch/arm/mm/proc-v7-2level.S +++ b/arch/arm/mm/proc-v7-2level.S @@ -46,18 +46,16 @@ ENTRY(cpu_v7_switch_mm) #ifdef CONFIG_ARM_ERRATA_430973 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB #endif -#ifdef CONFIG_ARM_ERRATA_754322 - dsb -#endif - mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID - isb -1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 + mrc p15, 0, r2, c2, c0, 1 @ load TTB 1 + mcr p15, 0, r2, c2, c0, 0 @ into TTB 0 isb #ifdef CONFIG_ARM_ERRATA_754322 dsb #endif mcr p15, 0, r1, c13, c0, 1 @ set context ID isb + mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 + isb #endif mov pc, lr ENDPROC(cpu_v7_switch_mm) |