From 40306c8bc0dbef623fa02815929dace1c75046e2 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:15 +0200 Subject: arm: mach-kirkwood: use plus instead of or for address definitions Since we are going to use IOMEM() to define many base virtual addresses, we can no longer use binary or to define the individual register addresses ("binary or" arithmetic on pointers is not allowed). Instead, use the more conventional plus operator to do so. The binary or operators were actually not useful because the low-order bits of the base address were always zero, so the usage of the binary or operators was effectively identical to a plus operator. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-kirkwood/include/mach/bridge-regs.h | 20 ++-- arch/arm/mach-kirkwood/include/mach/kirkwood.h | 110 +++++++++++----------- 2 files changed, 65 insertions(+), 65 deletions(-) (limited to 'arch/arm/mach-kirkwood/include') diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h index a115142f8690..5c82b7dce4e2 100644 --- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h +++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h @@ -13,37 +13,37 @@ #include -#define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0100) +#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0100) #define CPU_CONFIG_ERROR_PROP 0x00000004 -#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) +#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) #define CPU_RESET 0x00000002 -#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) +#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) #define WDT_RESET_OUT_EN 0x00000002 #define SOFT_RESET_OUT_EN 0x00000004 -#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) +#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) #define SOFT_RESET 0x00000001 -#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) +#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110) #define WDT_INT_REQ 0x0008 #define BRIDGE_INT_TIMER1_CLR (~0x0004) -#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) +#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) #define IRQ_CAUSE_LOW_OFF 0x0000 #define IRQ_MASK_LOW_OFF 0x0004 #define IRQ_CAUSE_HIGH_OFF 0x0010 #define IRQ_MASK_HIGH_OFF 0x0014 -#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) -#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300) +#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) +#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) -#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128) +#define L2_CONFIG_REG (BRIDGE_VIRT_BASE + 0x0128) #define L2_WRITETHROUGH 0x00000010 -#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE | 0x11c) +#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE + 0x11c) #define CGC_BIT_GE0 (0) #define CGC_BIT_PEX0 (2) #define CGC_BIT_USB0 (3) diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h index c5b68510776b..9695592d332b 100644 --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h @@ -61,61 +61,61 @@ /* * Register Map */ -#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000) -#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE | 0x1500) -#define DDR_OPERATION_BASE (DDR_VIRT_BASE | 0x1418) - -#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x10000) -#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000) -#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE | 0x0030) -#define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034) -#define GPIO_LOW_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0100) -#define GPIO_HIGH_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0140) -#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300) -#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600) -#define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) -#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) -#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) -#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) -#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) - -#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000) -#define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x20000) - -#define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x30000) - -#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000) -#define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70) -#define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04) -#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x44000) -#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE | 0x70) -#define PCIE1_STATUS (PCIE1_VIRT_BASE | 0x1a04) - -#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000) - -#define XOR0_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60800) -#define XOR0_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60800) -#define XOR1_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60900) -#define XOR1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60900) -#define XOR0_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60A00) -#define XOR0_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60A00) -#define XOR1_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60B00) -#define XOR1_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60B00) - -#define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x70000) -#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x74000) - -#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000) -#define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x80000) -#define SATA0_IF_CTRL (SATA_VIRT_BASE | 0x2050) -#define SATA0_PHY_MODE_2 (SATA_VIRT_BASE | 0x2330) -#define SATA1_IF_CTRL (SATA_VIRT_BASE | 0x4050) -#define SATA1_PHY_MODE_2 (SATA_VIRT_BASE | 0x4330) - -#define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x90000) - -#define AUDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0xA0000) -#define AUDIO_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0xA0000) +#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x00000) +#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE + 0x1500) +#define DDR_OPERATION_BASE (DDR_VIRT_BASE + 0x1418) + +#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x10000) +#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x10000) +#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE + 0x0030) +#define DEVICE_ID (DEV_BUS_VIRT_BASE + 0x0034) +#define GPIO_LOW_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100) +#define GPIO_HIGH_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0140) +#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x0300) +#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x0600) +#define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000) +#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000) +#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000) +#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100) +#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100) + +#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x20000) +#define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000) + +#define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x30000) + +#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x40000) +#define PCIE_LINK_CTRL (PCIE_VIRT_BASE + 0x70) +#define PCIE_STATUS (PCIE_VIRT_BASE + 0x1a04) +#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x44000) +#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE + 0x70) +#define PCIE1_STATUS (PCIE1_VIRT_BASE + 0x1a04) + +#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x50000) + +#define XOR0_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60800) +#define XOR0_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60800) +#define XOR1_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60900) +#define XOR1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60900) +#define XOR0_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60A00) +#define XOR0_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60A00) +#define XOR1_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60B00) +#define XOR1_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60B00) + +#define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x70000) +#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x74000) + +#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x80000) +#define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x80000) +#define SATA0_IF_CTRL (SATA_VIRT_BASE + 0x2050) +#define SATA0_PHY_MODE_2 (SATA_VIRT_BASE + 0x2330) +#define SATA1_IF_CTRL (SATA_VIRT_BASE + 0x4050) +#define SATA1_PHY_MODE_2 (SATA_VIRT_BASE + 0x4330) + +#define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x90000) + +#define AUDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0xA0000) +#define AUDIO_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0xA0000) /* * Supported devices and revisions. -- cgit v1.2.3 From 060f3d191b1d80312d7c90de2f3c3356db413f40 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:19 +0200 Subject: arm: mach-kirkwood: use IOMEM() for base address definitions We now define all virtual base address constants using IOMEM() so that those are naturally typed as void __iomem pointers, and we do the necessary adjustements in the mach-kirkwood code. Note that we introduce a few temporary additional "unsigned long" casts when calling into plat-orion functions. Those are removed by followup patches converting plat-orion functions to void __iomem pointers as well. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-kirkwood/include/mach/kirkwood.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/mach-kirkwood/include') diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h index 9695592d332b..d3ea68269c90 100644 --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h @@ -37,17 +37,17 @@ #define KIRKWOOD_NAND_MEM_SIZE SZ_1K #define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000 -#define KIRKWOOD_PCIE1_IO_VIRT_BASE 0xfef00000 +#define KIRKWOOD_PCIE1_IO_VIRT_BASE IOMEM(0xfef00000) #define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00100000 #define KIRKWOOD_PCIE1_IO_SIZE SZ_1M #define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000 -#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfee00000 +#define KIRKWOOD_PCIE_IO_VIRT_BASE IOMEM(0xfee00000) #define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000 #define KIRKWOOD_PCIE_IO_SIZE SZ_1M #define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 -#define KIRKWOOD_REGS_VIRT_BASE 0xfed00000 +#define KIRKWOOD_REGS_VIRT_BASE IOMEM(0xfed00000) #define KIRKWOOD_REGS_SIZE SZ_1M #define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000 -- cgit v1.2.3