From 3a15d02839bb63cda65f43b8adcf3411a34b1278 Mon Sep 17 00:00:00 2001
From: Haojian Zhuang <haojian.zhuang@linaro.org>
Date: Thu, 4 Apr 2013 17:06:24 +0800
Subject: ARM: dts: enable framebuffer on hi4511

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
---
 arch/arm/boot/dts/hi3620.dtsi | 72 +++++++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/hi4511.dts  | 30 ++++++++++++++++++
 2 files changed, 102 insertions(+)

diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index b768d2b0dbd..5bd415d5b91 100644
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -848,6 +848,34 @@
 				clock-output-names = "clk_dphy2";
 				hisilicon,hi3620-clkgate = <0x30 0x20000>;
 			};
+			ldiclk0: clkgate@65 {
+				compatible = "hisilicon,hi3620-clk-gate";
+ 				#clock-cells = <0>;
+				clocks = <&refclk_ldi0>;
+				clock-output-names = "clk_ldi0";
+				hisilicon,hi3620-clkgate = <0x30 0x200>;
+			};
+			ldiclk1: clkgate@66 {
+				compatible = "hisilicon,hi3620-clk-gate";
+ 				#clock-cells = <0>;
+				clocks = <&refclk_ldi1>;
+				clock-output-names = "clk_ldi1";
+				hisilicon,hi3620-clkgate = <0x30 0x800>;
+			};
+			edcclk0: clkgate@67 {
+				compatible = "hisilicon,hi3620-clk-gate";
+ 				#clock-cells = <0>;
+				clocks = <&pclk>;
+				clock-output-names = "clk_edc0";
+				hisilicon,hi3620-clkgate = <0x30 0x100>;
+			};
+			edcclk1: clkgate@68 {
+				compatible = "hisilicon,hi3620-clk-gate";
+ 				#clock-cells = <0>;
+				clocks = <&pclk>;
+				clock-output-names = "clk_edc1";
+				hisilicon,hi3620-clkgate = <0x30 0x400>;
+			};
 			dtable: clkdiv@0 {
 				#hisilicon,clkdiv-table-cells = <2>;
  			};
@@ -1544,5 +1572,49 @@
 			clocks = <&kpcclk>;
 			status = "disabled";
 		};
+		edc0: edc@fa202000 {
+			compatible = "hisilicon,hi3620-fb";
+			reg = <0xfa202000 0x1000>;
+			clocks = <&ldiclk0 &edcclk0 &dsiclk0 &lanebyteclk0>;
+			clock-names = "ldi", "edc", "dsi", "lane";
+			interrupts = <0 38 0x4>, <0 39 0x4>, <0 40 0x4>;
+			interrupt-names = "edc", "ldi", "dsi";
+			status = "disabled";
+
+			dsi2xclk0: clkdsi@0 {
+				compatible = "hisilicon,hi3620-phy";
+				#clock-cells = <0>;
+				clocks = <&osc26m>;
+				clock-output-names = "clk_dsi2x0";
+			};
+			dsiclk0: clkdsi@1 {
+				compatible = "hisilicon,clk-fixed-factor";
+				#clock-cells = <0>;
+				clocks = <&dsi2xclk0>;
+				clock-output-names = "clk_dsi0";
+				/*mult, div*/
+				hisilicon,fixed-factor = <1 2>;
+			};
+			lanebyteclk0: clkdsi@2 {
+				compatible = "hisilicon,clk-fixed-factor";
+				#clock-cells = <0>;
+				clocks = <&dsi2xclk0>;
+				clock-output-names = "clk_lanebyte0";
+				/*mult, div*/
+				hisilicon,fixed-factor = <1 8>;
+			};
+			escclk0: clkdsi@3 {
+				compatible = "hisilicon,hi3620-phy-esc";
+				#clock-cells = <0>;
+				clocks = <&lanebyteclk0>;
+				clock-output-names = "clk_dsi_phy_esc0";
+			};
+		};
+		edc1: edc@fa206900 {
+			compatible = "hisilicon,hi3620-fb";
+			clocks = <&ldiclk1 &edcclk1>;
+			clock-names = "ldi", "edc";
+			status = "disabled";
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/hi4511.dts b/arch/arm/boot/dts/hi4511.dts
index a124213bde0..d5a3079bdd2 100644
--- a/arch/arm/boot/dts/hi4511.dts
+++ b/arch/arm/boot/dts/hi4511.dts
@@ -1180,6 +1180,7 @@
 				regulator-name = "LDO16";
 				regulator-min-microvolt = <1500000>;
 				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
 				hisilicon,hi6421-ctrl = <0x30 0x10 0x20>;
 				hisilicon,hi6421-vset = <0x30 0x07>;
 				hisilicon,hi6421-n-voltages = <8>;
@@ -1197,6 +1198,7 @@
 				regulator-name = "LDO17";
 				regulator-min-microvolt = <1500000>;
 				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
 				hisilicon,hi6421-ctrl = <0x31 0x10 0x20>;
 				hisilicon,hi6421-vset = <0x31 0x07>;
 				hisilicon,hi6421-n-voltages = <8>;
@@ -1392,5 +1394,33 @@
 		mcu: mcu@fd000000 {
 			status = "ok";
 		};
+		edc0: edc@fa202000 {
+			hisilicon,pixel-format = "RGBA8888";
+			hisilicon,color-mode = <5>;
+			hisilicon,dsi-clock-frequency = <241000000>;    /* 241MHz, not 300MHz */
+			hisilicon,mipi-mode = "video";
+			hisilicon,mipi-lanes = <4>;
+			status = "ok";
+			
+			display-timings {
+				native-mode = <&timing0>;
+				timing0: timing0 {
+					clock-frequency = <13158>;      /* 13.158MHz pixel clock */
+					hactive = <720>;
+					vactive = <1280>;
+					hsync-active = <0>;
+					vsync-active = <0>;
+					de-active = <1>;
+					pixelclk-active = <1>;
+					hfront-porch = <134>;
+					hback-porch = <53>;
+					hsync-len = <67>;
+					vfront-porch = <7>;
+					vback-porch = <12>;
+					vsync-len = <1>;
+				};
+			};
+		};
+
 	}; /* end of amba */
 };
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