Merge branch 'tracking-qcomlt-apq8016-dt' into integration-linux-qcomlt

* tracking-qcomlt-apq8016-dt: (57 commits)
  arm64: dts: Fix the hypervisor and tz memory region size
  dts: qcom: Add CoreSight components for MSM8916
  arm64: dts: qcom: Add msm8916 CoreSight components
  arm64: dts: qcom: msm8916: Add RPMCC DT node
  arm64: dts: qcom: 8x16: Add fixed rate on-board XO oscillator
  arm64: dts: qcom: fix typo: user LED2 uses GPIO 120, not 10
  arm64: dts: apq8016-sbc: enable spi buses on LS and HS
  arm64: dts: apq8016-sbc: enable i2c buses on LS and HS
  arm64: dts: qcom: Add msm8916 I2C nodes.
  arm64: dts: fix i2c pinconf sleep state function
  arm64: dts: add support to analog audio playback
  arm64: dts: msm8916: add wcd codec support
  arm64: dts: Fix memory region descriptions
  ARM64: dts: Fix the missing usb otg regulators.
  arm64: dts: qcom: apq8016-sbc: Fix LED's naming
  dts: arm64: apq8016-sbc: enable LS 1.8v regulator by default
  arm64: dts: qcom: 8x16: UART2 use DMA for RX and TX
  arm64: dts: qcom: 8x16: Add UART1 configuration nodes
  arm64: dt: Add WCNSS related nodes
  DT: arm64: add iommu dtsi files
  ...

17 files changed, 2360 insertions, 3 deletions

diff --git a/Documentation/devicetree/bindings/arm/msm/ids.txt b/Documentation/devicetree/bindings/arm/msm/ids.txt
new file mode 100644
index 000000000000..9ee8428f4670
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/ids.txt
@@ -0,0 +1,65 @@
+* MSM-ID
+
+The qcom,msm-id entry specifies the MSM chipset and hardware revision.  It can
+optionally be an array of these to indicate multiple hardware that use the same
+device tree.  It is expected that the bootloader will use this information at
+boot-up to decide which device tree to use when given multiple device trees,
+some of which may not be compatible with the actual hardware.  It is the
+bootloader's responsibility to pass the correct device tree to the kernel.
+
+PROPERTIES
+
+- qcom,msm-id:
+	Usage: required
+	Value type: <prop-encoded-array> (<chipset_id, rev_id> [, <c2, r2> ..])
+	Definition:
+		The "chipset_id" consists of three fields as below:
+
+		bits 0-15  = The unique MSM chipset id.
+		bits 16-31 = Reserved.  Should be 0
+
+		chipset_id is an exact match value
+
+		The "rev_id" is a chipset specific 32-bit id that represents
+		the version of the chipset.
+
+		The rev_id is a best match id.  The bootloader will look for
+		the closest possible patch.
+
+* BOARD-ID
+
+The qcom,board-id entry specifies the board type and revision information.  It
+can optionally be an array of these to indicate multiple boards that use the
+same device tree.  It is expected that the bootloader will use this information
+at boot-up to decide which device tree to use when given multiple device trees,
+some of which may not be compatible with the actual hardware.  It is the
+bootloader's responsibility to pass the correct device tree to the kernel.
+
+PROPERTIES
+
+- qcom,board-id:
+	Usage: required
+	Value type: <prop-encoded-array> (<board_id, subtype_id> [, <b2, s2> ..])
+	Definition:
+		The "board_id" consists of three fields as below:
+
+		bits 31-24 = Unusued.
+		bits 23-16 = Platform Version Major
+		bits 15-8  = Platfrom Version Minor
+		bits 7-0   = Platform Type
+
+		Platform Type field is an exact match value.  The Platform
+		Major/Minor field is a best match.  The bootloader will look
+		for the closest possible match.
+
+		The "subtype_id" is unique to a Platform Type/Chipset ID.  For
+		a given Platform Type, there will typically only be a single
+		board and the subtype_id will be 0.  However in some cases board
+		variants may need to be distinquished by different subtype_id
+		values.
+
+		subtype_id is an exact match value.
+
+EXAMPLE:
+	qcom,board-id = <15 2>;
+	qcom,msm-id = <0x1007e 0>;
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 0554fbd72c40..477173c55d0b 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -75,6 +75,88 @@
 		};
 	};
 
+	thermal-zones {
+		cpu-thermal0 {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 5>;
+
+			trips {
+				cpu_alert0: trip@0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu_crit0: trip@1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu-thermal1 {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 6>;
+
+			trips {
+				cpu_alert1: trip@0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu_crit1: trip@1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu-thermal2 {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 7>;
+
+			trips {
+				cpu_alert2: trip@0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu_crit2: trip@1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu-thermal3 {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 8>;
+
+			trips {
+				cpu_alert3: trip@0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu_crit3: trip@1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
 	cpu-pmu {
 		compatible = "qcom,krait-pmu";
 		interrupts = <1 7 0xf04>;
@@ -103,6 +185,29 @@
 			      <0xf9002000 0x1000>;
 		};
 
+		qfprom: qfprom@fc4bc000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "qcom,qfprom";
+			reg = <0xfc4bc000 0x1000>;
+			tsens_calib: calib@d0 {
+				reg = <0xd0 0x18>;
+			};
+			tsens_backup: backup@440 {
+				reg = <0x440 0x10>;
+			};
+		};
+
+		tsens: thermal-sensor@fc4a8000 {
+			compatible = "qcom,msm8974-tsens";
+			reg = <0xfc4a8000 0x2000>;
+			nvmem-cells = <&tsens_calib>, <&tsens_backup>;
+			nvmem-cell-names = "calib", "calib_backup";
+			qcom,tsens-slopes = <3200 3200 3200 3200 3200 3200
+				3200 3200 3200 3200 3200>;
+			#thermal-sensor-cells = <1>;
+		};
+
 		timer@f9020000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -221,6 +326,7 @@
 			compatible = "qcom,gcc-apq8084";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
+			#power-domain-cells = <1>;
 			reg = <0xfc400000 0x4000>;
 		};
 
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 3292bcee9717..b09986185655 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -98,6 +98,88 @@
 		};
 	};
 
+	thermal-zones {
+		cpu-thermal0 {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 5>;
+
+			trips {
+				cpu_alert0: trip@0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu_crit0: trip@1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu-thermal1 {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 6>;
+
+			trips {
+				cpu_alert1: trip@0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu_crit1: trip@1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu-thermal2 {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 7>;
+
+			trips {
+				cpu_alert2: trip@0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu_crit2: trip@1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		cpu-thermal3 {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 8>;
+
+			trips {
+				cpu_alert3: trip@0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu_crit3: trip@1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
 	cpu-pmu {
 		compatible = "qcom,krait-pmu";
 		interrupts = <1 7 0xf04>;
@@ -387,6 +469,29 @@
 			      <0xf9002000 0x1000>;
 		};
 
+		qfprom: qfprom@fc4bc000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "qcom,qfprom";
+			reg = <0xfc4bc000 0x1000>;
+			tsens_calib: calib@d0 {
+				reg = <0xd0 0x18>;
+			};
+			tsens_backup: backup@440 {
+				reg = <0x440 0x10>;
+			};
+		};
+
+		tsens: thermal-sensor@fc4a8000 {
+			compatible = "qcom,msm8974-tsens";
+			reg = <0xfc4a8000 0x2000>;
+			nvmem-cells = <&tsens_calib>, <&tsens_backup>;
+			nvmem-cell-names = "calib", "calib_backup";
+			qcom,tsens-slopes = <3200 3200 3200 3200 3200 3200
+				3200 3200 3200 3200 3200>;
+			#thermal-sensor-cells = <1>;
+		};
+
 		timer@f9020000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -531,6 +636,7 @@
 			compatible = "qcom,gcc-msm8974";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
+			#power-domain-cells = <1>;
 			reg = <0xfc400000 0x4000>;
 		};
 
@@ -543,6 +649,7 @@
 			compatible = "qcom,mmcc-msm8974";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
+			#power-domain-cells = <1>;
 			reg = <0xfd8c0000 0x6000>;
 		};
 
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
index e03c11d9d834..181ac9c16460 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
@@ -10,6 +10,14 @@
 		};
 	};
 
+	pm8916_gpios_default: default {
+		usb_hub_reset_pm {
+			pins = "gpio1";
+			function = PMIC_GPIO_FUNC_NORMAL;
+			output-low;
+		};
+	};
+
 	usb_sw_sel_pm: usb_sw_sel_pm {
 		pinconf {
 			pins = "gpio4";
@@ -34,6 +42,25 @@
 		pinconf {
 			pins = "mpp2", "mpp3";
 			function = PMIC_GPIO_FUNC_NORMAL;
+			power-source = <PM8916_GPIO_VPH>;
+			output-low;	// USB device mode
+		};
+	};
+
+	pm8916_gpios_leds_default: pm8916_gpios_leds_default {
+		pinconf {
+			pins = "gpio1", "gpio2";
+			function = PMIC_GPIO_FUNC_NORMAL;
+			output-low;
+		};
+	};
+};
+
+&pm8916_mpps {
+	pm8916_mpps_leds_default: pm8916_mpps_leds_default {
+		pinconf {
+			pins = "mpp2", "mpp3";
+			function = "digital";
 			output-low;
 		};
 	};
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
index cbeee0bcdf52..c7db0aeaebaa 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
@@ -9,5 +9,69 @@
 			function = "gpio";
 			output-low;
 		};
+
+		usb_id_default: usb_id_default {
+			pins = "gpio121";
+			function = "gpio";
+			drive-strength = <8>;
+			input-enable;
+			bias-pull-up;
+		};
+	};
+
+	msm_gpios_leds_default: msm_gpios_leds_default {
+		pinconf {
+			pins = "gpio21", "gpio120";
+			function = "gpio";
+			output-low;
+		};
+	};
+
+	adv7533_int_active: adv533_int_active {
+		pinmux {
+			function = "gpio";
+			pins = "gpio31";
+		};
+		pinconf {
+			pins = "gpio31";
+			drive-strength = <16>;
+			bias-disable;
+		};
+	};
+
+	adv7533_int_suspend: adv7533_int_suspend {
+		pinmux {
+			function = "gpio";
+			pins = "gpio31";
+		};
+		pinconf {
+			pins = "gpio31";
+			drive-strength = <2>;
+			bias-disable;
+		};
+	};
+
+	adv7533_switch_active: adv7533_switch_active {
+		pinmux {
+			function = "gpio";
+			pins = "gpio32";
+		};
+		pinconf {
+			pins = "gpio32";
+			drive-strength = <16>;
+			bias-disable;
+		};
+	};
+
+	adv7533_switch_suspend: adv7533_switch_suspend {
+		pinmux {
+			function = "gpio";
+			pins = "gpio32";
+		};
+		pinconf {
+			pins = "gpio32";
+			drive-strength = <2>;
+			bias-disable;
+		};
 	};
 };
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts
index 825f489a2af7..b0cac5337fcc 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts
@@ -12,10 +12,11 @@
  */
 
 /dts-v1/;
-
+#include <dt-bindings/arm/qcom-ids.h>
 #include "apq8016-sbc.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. APQ 8016 SBC";
 	compatible = "qcom,apq8016-sbc", "qcom,apq8016", "qcom,sbc";
+	qcom,board-id = <QCOM_BRD_ID(SBC, 1, 0) QCOM_BRD_SUBTYPE_DEFAULT>;
 };
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index 66804ffbc6d2..bc40ec5945aa 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -11,14 +11,17 @@
  * GNU General Public License for more details.
  */
 
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/sound/apq8016-lpass.h>
 #include "msm8916.dtsi"
 #include "pm8916.dtsi"
 #include "apq8016-sbc-soc-pins.dtsi"
 #include "apq8016-sbc-pmic-pins.dtsi"
-
+#include "msm8916-mdss.dtsi"
 / {
 	aliases {
 		serial0 = &blsp1_uart2;
+		serial1 = &blsp1_uart1;
 	};
 
 	chosen {
@@ -33,6 +36,31 @@
 			pinctrl-1 = <&blsp1_uart2_sleep>;
 		};
 
+		i2c@78b6000 {
+		/* On Low speed expansion */
+			status = "okay";
+		};
+
+		i2c@78b8000 {
+		/* On High speed expansion */
+			status = "okay";
+		};
+
+		i2c@78ba000 {
+		/* On Low speed expansion */
+			status = "okay";
+		};
+
+		spi@78b7000 {
+		/* On High speed expansion */
+			status = "okay";
+		};
+
+		spi@78b9000 {
+		/* On Low speed expansion */
+			status = "okay";
+		};
+
 		leds {
 			pinctrl-names = "default";
 			pinctrl-0 = <&msmgpio_leds>,
@@ -84,4 +112,228 @@
 			};
 		};
 	};
+
+	usb2513 {
+		compatible = "smsc,usb3503";
+		reset-gpios = <&pm8916_gpios 3 GPIO_ACTIVE_LOW>;
+		initial-mode = <1>;
+	};
+
+	usb_id: usb-id {
+		interrupt-parent = <&msmgpio>;
+		compatible = "linux,extcon-usb-gpio";
+		id-gpio = <&msmgpio 121 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb_id_default>;
+	};
+
+	leds {
+		pinctrl-names = "default";
+		pinctrl-0 = <&msm_gpios_leds_default>,
+			    <&pm8916_gpios_leds_default>,
+			    <&pm8916_mpps_leds_default>;
+
+		compatible = "gpio-leds";
+
+		led@1 {
+			label = "apq8016-sbc:green:user0";
+			gpios = <&msmgpio 21 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+			default-state = "off";
+		};
+
+		led@2 {
+			label = "apq8016-sbc:green:user1";
+			gpios = <&msmgpio 120 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "mmc0";
+			default-state = "off";
+		};
+
+		led@3 {
+			label = "apq8016-sbc:green:user2";
+			gpios = <&pm8916_gpios 1 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "mmc1";
+			default-state = "off";
+		};
+
+		led@4 {
+			label = "apq8016-sbc:green:user3";
+			gpios = <&pm8916_gpios 2 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "none";
+			default-state = "off";
+		};
+
+		led@5 {
+			label = "apq8016-sbc:yellow:wifi";
+			gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "wlan";
+			default-state = "off";
+		};
+
+		led@6 {
+			label = "apq8016-sbc:blue:bt";
+			gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "bt";
+			default-state = "off";
+		};
+	};
+
+};
+&blsp_dma {
+	status = "okay";
+};
+
+&blsp1_uart1 {
+	status = "okay";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&blsp1_uart1_default>;
+	pinctrl-1 = <&blsp1_uart1_sleep>;
+};
+
+&blsp_spi3 {
+	status = "okay";
+};
+
+&sdhc_1 {
+	vmmc-supply = <&pm8916_l8>;
+	vqmmc-supply = <&pm8916_l5>;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
+	pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
+	status = "okay";
+};
+
+&sdhc_2 {
+	vmmc-supply = <&pm8916_l11>;
+	vqmmc-supply = <&pm8916_l12>;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+	pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+	#address-cells = <0>;
+	interrupt-parent = <&sdhc_2>;
+	interrupts = <0 1 2>;
+	#interrupt-cells = <1>;
+	interrupt-map-mask = <0xffffffff>;
+	interrupt-map = <0 &intc 0 125 0
+			1 &intc 0 221 0
+			2 &msmgpio 38 0>;
+	interrupt-names = "hc_irq", "pwr_irq", "status_irq";
+	cd-gpios = <&msmgpio 38 0x1>;
+
+	status = "okay";
+};
+
+&usb_dev {
+	extcon = <&usb_id>, <&usb_id>;
+	status = "okay";
+};
+
+&usb_host {
+	status = "okay";
+};
+
+&usb_otg {
+	extcon = <&usb_id>, <&usb_id>;
+	dr_mode = "otg";
+	status = "okay";
+	switch-gpio = <&pm8916_gpios 4 GPIO_ACTIVE_HIGH>; // D+/D- lines: 1 - Routed to HUB, 0 - Device
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb_sw_sel_pm>;
+};
+
+&blsp_i2c4 {
+	status = "ok";
+
+	adv_bridge: bridge@39 {
+		status = "ok";
+		compatible = "adi,adv7533";
+		reg = <0x39>;
+		interrupt-parent = <&msmgpio>;
+		//interrupts = <31 2>;
+		adi,dsi-lanes = <4>;
+		pd-gpios = <&msmgpio 32 0>;
+		pinctrl-names = "default","sleep";
+		pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>;
+		pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>;
+		#sound-dai-cells = <0>;
+
+		port {
+			adv_in: endpoint {
+				remote-endpoint = <&dsi_out>;
+			};
+		};
+
+	};
+};
+
+&mdss_dsi0 {
+	status = "ok";
+
+	port {
+		dsi_out: endpoint {
+			remote-endpoint = <&adv_in>;
+		};
+	};
+};
+
+&lpass {
+	status = "okay";
+};
+
+&wcd_codec {
+	status = "okay";
+	clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>;
+	clock-names = "mclk";
+	digital = <&wcd_digital>;
+};
+	/*
+	Internal Codec
+		playback - Primary MI2S
+		capture - Ter MI2S
+
+	External Primary:
+		playback - secondary MI2S
+		capture - Quat MI2S
+
+	External Secondary:
+		playback - Quat MI2S
+		capture - Quat MI2S
+
+	*/
+&sound {
+	status = "okay";
+	pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act &ext_mclk_tlmm_lines_act>;
+	pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus &ext_mclk_tlmm_lines_sus>;
+	pinctrl-names = "default", "sleep";
+	qcom,model = "DB410c";
+
+
+	internal-codec-playback-dai-link@0 {		/* I2S - Internal codec */
+		link-name = "WCD";
+		cpu { /* PRIMARY */
+			sound-dai = <&lpass MI2S_PRIMARY>;
+		};
+		codec {
+			sound-dai = <&wcd_codec 0>;
+		};
+	};
+
+	/* External Primary or External Secondary -ADV7533 HDMI */
+	external-dai-link@0 {
+		link-name = "ADV7533";
+
+		cpu { /* QUAT */
+			sound-dai = <&lpass MI2S_QUATERNARY>;
+		};
+		codec {
+			sound-dai = <&adv_bridge 0>;
+		};
+	};
+};
+
+/* default regulators required for mezzanine boards */
+&pm8916_l15 {
+	regulator-always-on;
 };
diff --git a/arch/arm64/boot/dts/qcom/msm-iommu-v2.dtsi b/arch/arm64/boot/dts/qcom/msm-iommu-v2.dtsi
new file mode 100644
index 000000000000..6f73eb26aaec
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm-iommu-v2.dtsi
@@ -0,0 +1,238 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&soc {
+	gfx_iommu: qcom,iommu@1f00000 {
+		compatible = "qcom,msm-smmu-v2", "qcom,msm-mmu-500";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		reg = <0x1f00000 0x10000>;
+		reg-names = "iommu_base";
+		interrupts = <0 43 0>, <0 42 0>;
+		interrupt-names = "global_cfg_NS_irq", "global_cfg_S_irq";
+		label = "gfx_iommu";
+		qcom,iommu-secure-id = <18>;
+		clocks = <&gcc GCC_SMMU_CFG_CLK>,
+			 <&gcc GCC_GFX_TCU_CLK>;
+		clock-names = "iface_clk", "core_clk";
+		status = "disabled";
+
+		qcom,iommu-ctx@1f09000 {
+			compatible = "qcom,msm-smmu-v2-ctx";
+			reg = <0x1f09000 0x1000>;
+			interrupts = <0 241 0>;
+			qcom,iommu-ctx-sids = <0>;
+			label = "gfx3d_user";
+		};
+
+		qcom,iommu-ctx@1f0a000 {
+			compatible = "qcom,msm-smmu-v2-ctx";
+			reg = <0x1f0a000 0x1000>;
+			interrupts = <0 242 0>;
+			qcom,iommu-ctx-sids = <1>;
+			label = "gfx3d_priv";
+		};
+	};
+
+	apps_iommu: qcom,iommu@1e00000 {
+		compatible = "qcom,msm-smmu-v2", "qcom,msm-mmu-500";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		reg = <0x1e00000 0x40000
+			0x1ef0000 0x3000>;
+		reg-names = "iommu_base", "smmu_local_base";
+		interrupts = <0 43 0>, <0 42 0>;
+		interrupt-names = "global_cfg_NS_irq", "global_cfg_S_irq";
+		label = "apps_iommu";
+		qcom,iommu-secure-id = <17>;
+		clocks = <&gcc GCC_SMMU_CFG_CLK>,
+			 <&gcc GCC_APSS_TCU_CLK>;
+		clock-names = "iface_clk", "core_clk";
+		qcom,cb-base-offset = <0x20000>;
+		status = "disabled";
+
+		qcom,iommu-ctx@1e22000 {
+			compatible = "qcom,msm-smmu-v2-ctx";
+			reg = <0x1e22000 0x1000>;
+			interrupts = <0 70 0>;
+			qcom,iommu-ctx-sids = <0x2000>;
+			label = "jpeg_enc0";
+		};
+
+		qcom,iommu-ctx@1e23000 {
+			compatible = "qcom,msm-smmu-v2-ctx";
+			reg = <0x1e23000 0x1000>;
+			interrupts = <0 70 0>;
+			qcom,iommu-ctx-sids = <0x400>;
+			label = "vfe";
+		};
+
+		qcom,iommu-ctx@1e24000 {
+			compatible = "qcom,msm-smmu-v2-ctx";
+			reg = <0x1e24000 0x1000>;
+			interrupts = <0 70 0>;
+			qcom,iommu-ctx-sids = <0xc00>;
+			label = "mdp_0";
+		};
+
+		venus_ns: qcom,iommu-ctx@1e25000 {
+			compatible = "qcom,msm-smmu-v2-ctx";
+			reg = <0x1e25000 0x1000>;
+			interrupts = <0 70 0>;
+			qcom,iommu-ctx-sids = <0x800 0x801 0x802 0x803
+						0x804 0x805 0x807>;
+			label = "venus_ns";
+		};
+
+		qcom,iommu-ctx@1e26000 {
+			compatible = "qcom,msm-smmu-v2-ctx";
+			reg = <0x1e26000 0x1000>;
+			interrupts = <0 70 0>;
+			qcom,iommu-ctx-sids = <0x402>;
+			label = "cpp";
+		};
+
+		qcom,iommu-ctx@1e27000 {
+			compatible = "qcom,msm-smmu-v2-ctx";
+			reg = <0x1e27000 0x1000>;
+			interrupts = <0 70 0>;
+			qcom,iommu-ctx-sids = <0x1000>;
+			label = "mDSP";
+		};
+
+		qcom,iommu-ctx@1e28000 {
+			compatible = "qcom,msm-smmu-v2-ctx";
+			reg = <0x1e28000 0x1000>;
+			interrupts = <0 70 0>;
+			qcom,iommu-ctx-sids = <0x1400>;
+			label = "gss";
+		};
+
+		qcom,iommu-ctx@1e29000 {
+			compatible = "qcom,msm-smmu-v2-ctx";
+			reg = <0x1e29000 0x1000>;
+			interrupts = <0 70 0>;
+			qcom,iommu-ctx-sids = <0x1800>;
+			label = "a2";
+		};
+
+		qcom,iommu-ctx@1e32000 {
+			compatible = "qcom,msm-smmu-v2-ctx";
+			qcom,secure-context;
+			reg = <0x1e32000 0x1000>;
+			interrupts = <0 70 0>, <0 70 0>;
+			qcom,iommu-ctx-sids = <0xc01>;
+			label = "mdp_1";
+		};
+
+		venus_sec_pixel: qcom,iommu-ctx@1e33000 {
+			compatible = "qcom,msm-smmu-v2-ctx";
+			qcom,secure-context;
+			reg = <0x1e33000 0x1000>;
+			interrupts = <0 70 0>, <0 70 0>;
+			qcom,iommu-ctx-sids = <0x885>;
+			label = "venus_sec_pixel";
+		};
+
+		venus_sec_bitstream: qcom,iommu-ctx@1e34000 {
+			compatible = "qcom,msm-smmu-v2-ctx";
+			qcom,secure-context;
+			reg = <0x1e34000 0x1000>;
+			interrupts = <0 70 0>, <0 70 0>;
+			qcom,iommu-ctx-sids = <0x880 0x881 0x882 0x883 0x884>;
+			label = "venus_sec_bitstream";
+		};
+
+		venus_sec_non_pixel: qcom,iommu-ctx@1e35000 {
+			compatible = "qcom,msm-smmu-v2-ctx";
+			qcom,secure-context;
+			reg = <0x1e35000 0x1000>;
+			interrupts = <0 70 0>, <0 70 0>;
+			qcom,iommu-ctx-sids = <0x887 0x8a0>;
+			label = "venus_sec_non_pixel";
+		};
+
+		venus_fw: qcom,iommu-ctx@1e36000 {
+			compatible = "qcom,msm-smmu-v2-ctx";
+			qcom,secure-context;
+			reg = <0x1e36000 0x1000>;
+			interrupts = <0 70 0>, <0 70 0>;
+			qcom,iommu-ctx-sids = <0x8c0 0x8c6>;
+			label = "venus_fw";
+		};
+
+		periph_rpm: qcom,iommu-ctx@1e37000 {
+			compatible = "qcom,msm-smmu-v2-ctx";
+			qcom,secure-context;
+			reg = <0x1e37000 0x1000>;
+			interrupts = <0 70 0>, <0 70 0>;
+			qcom,iommu-ctx-sids = <0x40>;
+			label = "periph_rpm";
+		};
+
+		qcom,iommu-ctx@1e38000 {
+			compatible = "qcom,msm-smmu-v2-ctx";
+			reg = <0x1e38000 0x1000>;
+			interrupts = <0 70 0>;
+			qcom,iommu-ctx-sids = <0xC0 0xC4 0xC8 0xCC 0xD0 0xD3
+						0xD4 0xD7 0xD8 0xDB 0xDC 0xDF
+						0xF0 0xF3 0xF4 0xF7 0xF8 0xFB
+						0xFC 0xFF>;
+			label = "periph_CE";
+		};
+
+		qcom,iommu-ctx@1e39000 {
+			compatible = "qcom,msm-smmu-v2-ctx";
+			reg = <0x1e39000 0x1000>;
+			interrupts = <0 70 0>;
+			qcom,iommu-ctx-sids = <0x280 0x283 0x284 0x287 0x288
+						0x28B 0x28C 0x28F 0x290 0x293
+						0x294 0x297 0x298 0x29B 0x29C
+						0x29F>;
+			label = "periph_BLSP";
+		};
+
+		qcom,iommu-ctx@1e3a000 {
+			compatible = "qcom,msm-smmu-v2-ctx";
+			reg = <0x1e3a000 0x1000>;
+			interrupts = <0 70 0>;
+			qcom,iommu-ctx-sids = <0x100>;
+			label = "periph_SDC1";
+		};
+
+		qcom,iommu-ctx@1e3b000 {
+			compatible = "qcom,msm-smmu-v2-ctx";
+			reg = <0x1e3b000 0x1000>;
+			interrupts = <0 70 0>;
+			qcom,iommu-ctx-sids = <0x140>;
+			label = "periph_SDC2";
+		};
+
+		qcom,iommu-ctx@1e3c000 {
+			compatible = "qcom,msm-smmu-v2-ctx";
+			reg = <0x1e3c000 0x1000>;
+			interrupts = <0 70 0>;
+			qcom,iommu-ctx-sids = <0x1c0>;
+			label = "periph_audio";
+		};
+
+		qcom,iommu-ctx@1e3d000 {
+			compatible = "qcom,msm-smmu-v2-ctx";
+			reg = <0x1e3d000 0x1000>;
+			interrupts = <0 70 0>;
+			qcom,iommu-ctx-sids = <0x2c0>;
+			label = "periph_USB_HS1";
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi b/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
new file mode 100644
index 000000000000..c008dc7a32bb
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8916-coresight.dtsi
@@ -0,0 +1,254 @@
+/*
+ * Copyright (c) 2013 - 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&soc {
+
+	tpiu@820000 {
+		compatible = "arm,coresight-tpiu", "arm,primecell";
+		reg = <0x820000 0x1000>;
+
+		clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+		clock-names = "apb_pclk", "atclk";
+
+		port {
+			tpiu_in: endpoint {
+				slave-mode;
+				remote-endpoint = <&replicator_out1>;
+			};
+		};
+	};
+
+	funnel@821000 {
+		compatible = "arm,coresight-funnel", "arm,primecell";
+		reg = <0x821000 0x1000>;
+
+		clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+		clock-names = "apb_pclk", "atclk";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/*
+			 * Not described input ports:
+			 * 0 - connected to Resource and Power Manger CPU ETM
+			 * 1 - not-connected
+			 * 2 - connected to Modem CPU ETM
+			 * 3 - not-connected
+			 * 5 - not-connected
+			 * 6 - connected trought funnel to Wireless CPU ETM
+			 * 7 - connected to STM component
+			 */
+			port@4 {
+				reg = <4>;
+				funnel0_in4: endpoint {
+					slave-mode;
+					remote-endpoint = <&funnel1_out>;
+				};
+			};
+			port@8 {
+				reg = <0>;
+				funnel0_out: endpoint {
+					remote-endpoint = <&etf_in>;
+				};
+			};
+		};
+	};
+
+	replicator@824000 {
+		compatible = "qcom,coresight-replicator1x", "arm,primecell";
+		reg = <0x824000 0x1000>;
+
+		clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+		clock-names = "apb_pclk", "atclk";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				replicator_out0: endpoint {
+					remote-endpoint = <&etr_in>;
+				};
+			};
+			port@1 {
+				reg = <1>;
+				replicator_out1: endpoint {
+					remote-endpoint = <&tpiu_in>;
+				};
+			};
+			port@2 {
+				reg = <0>;
+				replicator_in: endpoint {
+					slave-mode;
+					remote-endpoint = <&etf_out>;
+				};
+			};
+		};
+	};
+
+	etf@825000 {
+		compatible = "arm,coresight-tmc", "arm,primecell";
+		reg = <0x825000 0x1000>;
+
+		clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+		clock-names = "apb_pclk", "atclk";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				etf_out: endpoint {
+					remote-endpoint = <&replicator_in>;
+				};
+			};
+			port@1 {
+				reg = <0>;
+				etf_in: endpoint {
+					slave-mode;
+					remote-endpoint = <&funnel0_out>;
+				};
+			};
+		};
+	};
+
+	etr@826000 {
+		compatible = "arm,coresight-tmc", "arm,primecell";
+		reg = <0x826000 0x1000>;
+
+		clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+		clock-names = "apb_pclk", "atclk";
+
+		port {
+			etr_in: endpoint {
+				slave-mode;
+				remote-endpoint = <&replicator_out0>;
+			};
+		};
+	};
+
+	funnel@841000 {	/* APSS funnel only 4 inputs are used */
+		compatible = "arm,coresight-funnel", "arm,primecell";
+		reg = <0x841000 0x1000>;
+
+		clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+		clock-names = "apb_pclk", "atclk";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel1_in0: endpoint {
+					slave-mode;
+					remote-endpoint = <&etm0_out>;
+				};
+			};
+			port@1 {
+				reg = <1>;
+				funnel1_in1: endpoint {
+					slave-mode;
+					remote-endpoint = <&etm1_out>;
+				};
+			};
+			port@2 {
+				reg = <2>;
+				funnel1_in2: endpoint {
+					slave-mode;
+					remote-endpoint = <&etm2_out>;
+				};
+			};
+			port@3 {
+				reg = <3>;
+				funnel1_in3: endpoint {
+					slave-mode;
+					remote-endpoint = <&etm3_out>;
+				};
+			};
+			port@4 {
+				reg = <0>;
+				funnel1_out: endpoint {
+					remote-endpoint = <&funnel0_in4>;
+				};
+			};
+		};
+	};
+
+	etm@85c000 {
+		compatible = "arm,coresight-etm4x", "arm,primecell";
+		reg = <0x85c000 0x1000>;
+
+		clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+		clock-names = "apb_pclk", "atclk";
+
+		cpu = <&CPU0>;
+
+		port {
+			etm0_out: endpoint {
+				remote-endpoint = <&funnel1_in0>;
+			};
+		};
+	};
+
+	etm@85d000 {
+		compatible = "arm,coresight-etm4x", "arm,primecell";
+		reg = <0x85d000 0x1000>;
+
+		clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+		clock-names = "apb_pclk", "atclk";
+
+		cpu = <&CPU1>;
+
+		port {
+			etm1_out: endpoint {
+				remote-endpoint = <&funnel1_in1>;
+			};
+		};
+	};
+
+	etm@85e000 {
+		compatible = "arm,coresight-etm4x", "arm,primecell";
+		reg = <0x85e000 0x1000>;
+
+		clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+		clock-names = "apb_pclk", "atclk";
+
+		cpu = <&CPU2>;
+
+		port {
+			etm2_out: endpoint {
+				remote-endpoint = <&funnel1_in2>;
+			};
+		};
+	};
+
+	etm@85f000 {
+		compatible = "arm,coresight-etm4x", "arm,primecell";
+		reg = <0x85f000 0x1000>;
+
+		clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+		clock-names = "apb_pclk", "atclk";
+
+		cpu = <&CPU3>;
+
+		port {
+			etm3_out: endpoint {
+				remote-endpoint = <&funnel1_in3>;
+			};
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8916-iommu.dtsi b/arch/arm64/boot/dts/qcom/msm8916-iommu.dtsi
new file mode 100644
index 000000000000..82acb8df2a8a
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8916-iommu.dtsi
@@ -0,0 +1,21 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "msm-iommu-v2.dtsi"
+
+&gfx_iommu {
+	status = "ok";
+};
+
+&apps_iommu {
+	status = "ok";
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8916-mdss.dtsi b/arch/arm64/boot/dts/qcom/msm8916-mdss.dtsi
new file mode 100644
index 000000000000..95d3d337ae48
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8916-mdss.dtsi
@@ -0,0 +1,122 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+&soc {
+	gpu: qcom,adreno-3xx@01c00000 {
+		compatible = "qcom,adreno-3xx";
+		#stream-id-cells = <16>;
+		reg = <0x01c00000 0x20000>;
+		reg-names = "kgsl_3d0_reg_memory";
+		interrupts = <0 33 0>;
+		interrupt-names = "kgsl_3d0_irq";
+		clock-names =
+		    "core_clk",
+		    "iface_clk",
+		    "mem_clk",
+		    "mem_iface_clk",
+		    "alt_mem_iface_clk",
+		    "gfx3d_clk_src";
+		clocks =
+		    <&gcc GCC_OXILI_GFX3D_CLK>,
+		    <&gcc GCC_OXILI_AHB_CLK>,
+		    <&gcc GCC_OXILI_GMEM_CLK>,
+		    <&gcc GCC_BIMC_GFX_CLK>,
+		    <&gcc GCC_BIMC_GPU_CLK>,
+		    <&gcc GFX3D_CLK_SRC>;
+		power-domains = <&gcc OXILI_GDSC>;
+		qcom,chipid = <0x03000600>;
+		qcom,gpu-pwrlevels {
+			compatible = "qcom,gpu-pwrlevels";
+			qcom,gpu-pwrlevel@0 {
+				qcom,gpu-freq = <400000000>;
+			};
+			qcom,gpu-pwrlevel@1 {
+				qcom,gpu-freq = <19200000>;
+			};
+		};
+	};
+
+	mdss_mdp: qcom,mdss_mdp@1a00000 {
+		compatible = "qcom,mdss_mdp";
+		reg = <0x1a00000 0x90000>,
+			<0x1ac8000 0x3000>;
+		reg-names = "mdp_phys", "vbif_phys";
+		interrupts = <0 72 0>;
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+
+		power-domains = <&gcc MDSS_GDSC>;
+
+		connectors = <&mdss_dsi0>;
+		gpus = <&gpu>;
+
+		clocks = <&gcc GCC_MDSS_AHB_CLK>,
+			 <&gcc GCC_MDSS_AXI_CLK>,
+			 <&gcc MDP_CLK_SRC>,
+			 <&gcc GCC_MDSS_MDP_CLK>,
+			 <&gcc GCC_MDSS_MDP_CLK>,
+			 <&gcc GCC_MDSS_VSYNC_CLK>;
+		clock-names = "iface_clk", "bus_clk", "core_clk_src",
+			      "core_clk", "lut_clk", "vsync_clk";
+	};
+
+	mdss_dsi0: qcom,mdss_dsi@1a98000 {
+		compatible = "qcom,mdss-dsi-ctrl";
+		label = "MDSS DSI CTRL->0";
+		qcom,dsi-host-index = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x1a98000 0x25c>;
+		reg-names = "dsi_ctrl";
+
+		interrupt-parent = <&mdss_mdp>;
+		interrupts = <4 0>;
+
+		vdda-supply = <&pm8916_l2>;
+		vdd-supply = <&pm8916_l17>;
+		vddio-supply = <&pm8916_l6>;
+
+		clocks = <&gcc GCC_MDSS_MDP_CLK>,
+                         <&gcc GCC_MDSS_AHB_CLK>,
+                         <&gcc GCC_MDSS_AXI_CLK>,
+                         <&gcc GCC_MDSS_AHB_CLK>,
+                         <&gcc GCC_MDSS_BYTE0_CLK>,
+                         <&gcc GCC_MDSS_PCLK0_CLK>,
+                         <&gcc GCC_MDSS_ESC0_CLK>,
+                         <&gcc BYTE0_CLK_SRC>,
+                         <&gcc PCLK0_CLK_SRC>;
+                clock-names = "mdp_core_clk", "iface_clk", "bus_clk",
+			      "core_mmss_clk", "byte_clk", "pixel_clk",
+			      "core_clk", "byte_clk_src", "pixel_clk_src";
+		qcom,dsi-phy = <&mdss_dsi_phy0>;
+	};
+
+	mdss_dsi_phy0: qcom,mdss_dsi_phy@1a98300 {
+		compatible = "qcom,dsi-phy-28nm-lp";
+		qcom,dsi-phy-index = <0>;
+
+		power-domains = <&gcc MDSS_GDSC>;
+
+		reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
+		reg = <0x1a98300 0xd4>,
+		      <0x1a98500 0x280>,
+		      <0x1a98780 0x30>;
+
+		clocks = <&gcc GCC_MDSS_AHB_CLK>;
+		clock-names = "iface_clk";
+
+		vddio-supply = <&pm8916_l6>;
+	};
+};
+
+
diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts
index fced77f0fd3a..6c68b4ed4de2 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts
@@ -13,10 +13,13 @@
 
 /dts-v1/;
 
+#include <dt-bindings/arm/qcom-ids.h>
 #include "msm8916-mtp.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. MSM 8916 MTP";
 	compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp-smb1360",
 			"qcom,msm8916", "qcom,mtp";
+	qcom,board-id = <QCOM_BRD_ID(MTP, 1, 0) QCOM_BRD_SUBTYPE_DEFAULT>,
+			<QCOM_BRD_ID(MTP, 1, 0) QCOM_BRD_SUBTYPE_MTP8916_SMB1360>;
 };
diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
index a1aa0b201e92..a222af32debe 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
@@ -32,3 +32,42 @@
 		};
 	};
 };
+
+&blsp_dma {
+	status = "okay";
+};
+
+&blsp_spi3 {
+	status = "okay";
+};
+
+&sdhc_1 {
+	vmmc-supply = <&pm8916_l8>;
+	vqmmc-supply = <&pm8916_l5>;
+
+	pinctrl-names = "active", "sleep";
+	pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
+	pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
+	status = "okay";
+};
+
+&sdhc_2 {
+	//vmmc-supply = <&pm8916_l11>;
+	vqmmc-supply = <&pm8916_l12>;
+
+	pinctrl-names = "active", "sleep";
+	pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+	pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+	#address-cells = <0>;
+	interrupt-parent = <&sdhc_2>;
+	interrupts = <0 1 2>;
+	#interrupt-cells = <1>;
+	interrupt-map-mask = <0xffffffff>;
+	interrupt-map = <0 &intc 0 125 0
+			1 &intc 0 221 0
+			2 &msmgpio 38 0>;
+	interrupt-names = "hc_irq", "pwr_irq", "status_irq";
+	cd-gpios = <&msmgpio 38 0x1>;
+
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
index 568956859088..5d2e4a5e91ef 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
@@ -12,6 +12,34 @@
  */
 
 &msmgpio {
+	blsp1_uart1_default: blsp1_uart1_default {
+		pinmux {
+			function = "blsp_uart1";
+			//      TX, RX, CTS_N, RTS_N
+			pins = "gpio0", "gpio1",
+			"gpio2", "gpio3";
+		};
+		pinconf {
+			pins = "gpio0", "gpio1",
+			"gpio2", "gpio3";
+			drive-strength = <16>;
+			bias-disable;
+		};	
+	};
+
+	blsp1_uart1_sleep: blsp1_uart1_sleep {
+		pinmux {
+			function = "blsp_uart1";
+			pins = "gpio0", "gpio1",
+			"gpio2", "gpio3";
+		};
+		pinconf {
+			pins = "gpio0", "gpio1",
+			"gpio2", "gpio3";
+			drive-strength = <2>;
+			bias-pull-down;
+		};
+	};
 
 	blsp1_uart2_default: blsp1_uart2_default {
 		pinmux {
@@ -241,6 +269,30 @@
 		};
 	};
 
+	i2c2_default: i2c2_default {
+		pinmux {
+			function = "blsp_i2c2";
+			pins = "gpio6", "gpio7";
+		};
+		pinconf {
+			pins = "gpio6", "gpio7";
+			drive-strength = <2>;
+			bias-disable = <0>;
+		};
+	};
+
+	i2c2_sleep: i2c2_sleep {
+		pinmux {
+			function = "gpio";
+			pins = "gpio6", "gpio7";
+		};
+		pinconf {
+			pins = "gpio6", "gpio7";
+			drive-strength = <2>;
+			bias-disable = <0>;
+		};
+	};
+
 	i2c4_default: i2c4_default {
 		pinmux {
 			function = "blsp_i2c4";
@@ -255,7 +307,7 @@
 
 	i2c4_sleep: i2c4_sleep {
 		pinmux {
-			function = "blsp_i2c4";
+			function = "gpio";
 			pins = "gpio14", "gpio15";
 		};
 		pinconf {
@@ -265,6 +317,30 @@
 		};
 	};
 
+	i2c6_default: i2c6_default {
+		pinmux {
+			function = "blsp_i2c6";
+			pins = "gpio22", "gpio23";
+		};
+		pinconf {
+			pins = "gpio22", "gpio23";
+			drive-strength = <2>;
+			bias-disable = <0>;
+		};
+	};
+
+	i2c6_sleep: i2c6_sleep {
+		pinmux {
+			function = "gpio";
+			pins = "gpio22", "gpio23";
+		};
+		pinconf {
+			pins = "gpio22", "gpio23";
+			drive-strength = <2>;
+			bias-disable = <0>;
+		};
+	};
+
 	sdhc2_cd_pin {
 		sdc2_cd_on: cd_on {
 			pinmux {
@@ -427,4 +503,245 @@
 			};
 		};
 	};
+
+	ext-codec-lines {
+		ext_codec_lines_act: lines_on {
+			pinmux {
+				function = "gpio";
+				pins = "gpio67";
+			};
+			pinconf {
+				pins = "gpio67";
+				drive-strength = <8>;
+				bias-disable;
+				output-high;
+			};
+		};
+		ext_codec_lines_sus: lines_off {
+			pinmux {
+				function = "gpio";
+				pins = "gpio67";
+			};
+			pinconf {
+				pins = "gpio67";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	cdc-pdm-lines {
+		cdc_pdm_lines_act: pdm_lines_on {
+			pinmux {
+				function = "cdc_pdm0";
+				pins = "gpio63", "gpio64", "gpio65", "gpio66",
+				       "gpio67", "gpio68";
+			};
+			pinconf {
+				pins = "gpio63", "gpio64", "gpio65", "gpio66",
+				       "gpio67", "gpio68";
+				drive-strength = <8>;
+				bias-pull-none;
+			};
+		};
+		cdc_pdm_lines_sus: pdm_lines_off {
+			pinmux {
+				function = "cdc_pdm0";
+				pins = "gpio63", "gpio64", "gpio65", "gpio66",
+				       "gpio67", "gpio68";
+			};
+			pinconf {
+				pins = "gpio63", "gpio64", "gpio65", "gpio66",
+				       "gpio67", "gpio68";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	ext-pri-tlmm-lines {
+		ext_pri_tlmm_lines_act: ext_pa_on {
+			pinmux {
+				function = "pri_mi2s";
+				pins = "gpio113", "gpio114", "gpio115",
+				       "gpio116";
+			};
+			pinconf {
+				pins = "gpio113", "gpio114", "gpio115",
+				       "gpio116";
+				drive-strength = <8>;
+				bias-pull-none;
+			};
+		};
+
+		ext_pri_tlmm_lines_sus: ext_pa_off {
+			pinmux {
+				function = "pri_mi2s";
+				pins = "gpio113", "gpio114", "gpio115",
+				       "gpio116";
+			};
+			pinconf {
+				pins = "gpio113", "gpio114", "gpio115",
+				       "gpio116";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	ext-pri-ws-line {
+		ext_pri_ws_act: ext_pa_on {
+			pinmux {
+				function = "pri_mi2s_ws";
+				pins = "gpio110";
+			};
+			pinconf {
+				pins = "gpio110";
+				drive-strength = <8>;
+				bias-pull-none;
+			};
+		};
+
+		ext_pri_ws_sus: ext_pa_off {
+			pinmux {
+				function = "pri_mi2s_ws";
+				pins = "gpio110";
+			};
+			pinconf {
+				pins = "gpio110";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	ext-mclk-tlmm-lines {
+		ext_mclk_tlmm_lines_act: mclk_lines_on {
+			pinmux {
+				function = "pri_mi2s";
+				pins = "gpio116";
+			};
+			pinconf {
+				pins = "gpio116";
+				drive-strength = <8>;
+				bias-pull-none;
+			};
+		};
+		ext_mclk_tlmm_lines_sus: mclk_lines_off {
+			pinmux {
+				function = "pri_mi2s";
+				pins = "gpio116";
+			};
+			pinconf {
+				pins = "gpio116";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	/* secondary Mi2S */
+	ext-sec-tlmm-lines {
+		ext_sec_tlmm_lines_act: tlmm_lines_on {
+			pinmux {
+				function = "sec_mi2s";
+				pins = "gpio112", "gpio117", "gpio118",
+				       "gpio119";
+			};
+			pinconf {
+				pins = "gpio112", "gpio117", "gpio118",
+					"gpio119";
+				drive-strength = <8>;
+				bias-pull-none;
+			};
+		};
+		ext_sec_tlmm_lines_sus: tlmm_lines_off {
+			pinmux {
+				function = "sec_mi2s";
+				pins = "gpio112", "gpio117", "gpio118",
+				       "gpio119";
+			};
+			pinconf {
+				pins = "gpio112", "gpio117", "gpio118",
+					"gpio119";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	cdc-dmic-lines {
+		cdc_dmic_lines_act: dmic_lines_on {
+			pinmux_dmic0_clk {
+				function = "dmic0_clk";
+				pins = "gpio0";
+			};
+			pinmux_dmic0_data {
+				function = "dmic0_data";
+				pins = "gpio1";
+			};
+			pinconf {
+				pins = "gpio0", "gpio1";
+				drive-strength = <8>;
+			};
+		};
+		cdc_dmic_lines_sus: dmic_lines_off {
+			pinconf {
+				pins = "gpio0", "gpio1";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	cross-conn-det {
+		cross_conn_det_act: lines_on {
+			pinmux {
+				function = "gpio";
+				pins = "gpio120";
+			};
+			pinconf {
+				pins = "gpio120";
+				drive-strength = <8>;
+				output-low;
+				bias-pull-down;
+			};
+		};
+		cross_conn_det_sus: lines_off {
+			pinmux {
+				function = "gpio";
+				pins = "gpio120";
+			};
+			pinconf {
+				pins = "gpio120";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	wcnss_default: wcnss_default {
+		pinmux2 {
+			function = "wcss_wlan";
+			pins = "gpio40";
+		};
+		pinmux1 {
+			function = "wcss_wlan";
+			pins = "gpio41";
+		};
+		pinmux0 {
+			function = "wcss_wlan";
+			pins = "gpio42";
+		};
+		pinmux {
+			function = "wcss_wlan";
+			pins = "gpio43", "gpio44";
+		};
+		pinconf {
+			pins = "gpio40", "gpio41", "gpio42", "gpio43",
+			       "gpio44";
+			drive-strength = <6>;
+			bias-pull-up;
+		};
+	};
 };
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 5911de008dd5..000d936691bb 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -14,10 +14,19 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
+#include <dt-bindings/clock/qcom,rpmcc-msm8916.h>
+#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/arm/qcom-ids.h>
 
 / {
 	model = "Qualcomm Technologies, Inc. MSM8916";
 	compatible = "qcom,msm8916";
+	qcom,msm-id =	<QCOM_ID_MSM8916 0>,
+			<QCOM_ID_MSM8216 0>,
+			<QCOM_ID_MSM8116 0>,
+			<QCOM_ID_MSM8616 0>,
+			<QCOM_ID_APQ8016 0>;
+
 
 	interrupt-parent = <&intc>;
 
@@ -37,6 +46,32 @@
 		reg = <0 0 0 0>;
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		reserve_aligned@86000000 {
+			reg = <0x0 0x86000000 0x0 0x0300000>;
+			no-map;
+		};
+
+		smem_mem: smem_region@86300000 {
+			reg = <0x0 0x86300000 0x0 0x0100000>;
+			no-map;
+		};
+
+                hypervisor_mem: hypervisor_region@86400000 {
+                        no-map;
+                        reg = <0x0 0x86400000 0x0 0x0400000>;
+                };
+
+                peripheral_mem: peripheral_region@8b600000 {
+                        no-map;
+                        reg = <0x0 0x8b600000 0x0 0x0600000>;
+                };
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -45,24 +80,130 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0x0>;
+			enable-method = "qcom,arm-cortex-acc";
+			qcom,acc = <&acc0>;
+			next-level-cache = <&L2_0>;
+			clocks = <&a53cc 1>;
+			clock-latency = <200000>;
+			cpu-supply = <&pm8916_s2>;
+			/* cooling options */
+			cooling-min-level = <0>;
+			cooling-max-level = <7>;
+			#cooling-cells = <2>;
+			L2_0: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      power-domain = <&l2ccc_0>;
+			};
 		};
 
 		CPU1: cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0x1>;
+			enable-method = "qcom,arm-cortex-acc";
+			qcom,acc = <&acc1>;
+			next-level-cache = <&L2_0>;
+			clocks = <&a53cc 1>;
+			clock-latency = <200000>;
+			cpu-supply = <&pm8916_s2>;
+			/* cooling options */
+			cooling-min-level = <0>;
+			cooling-max-level = <7>;
+			#cooling-cells = <2>;
 		};
 
 		CPU2: cpu@2 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0x2>;
+			enable-method = "qcom,arm-cortex-acc";
+			qcom,acc = <&acc2>;
+			next-level-cache = <&L2_0>;
+			clocks = <&a53cc 1>;
+			clock-latency = <200000>;
+			cpu-supply = <&pm8916_s2>;
+			/* cooling options */
+			cooling-min-level = <0>;
+			cooling-max-level = <7>;
+			#cooling-cells = <2>;
 		};
 
 		CPU3: cpu@3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0x3>;
+			enable-method = "qcom,arm-cortex-acc";
+			qcom,acc = <&acc3>;
+			next-level-cache = <&L2_0>;
+			clocks = <&a53cc 1>;
+			clock-latency = <200000>;
+			cpu-supply = <&pm8916_s2>;
+			/* cooling options */
+			cooling-min-level = <0>;
+			cooling-max-level = <7>;
+			#cooling-cells = <2>;
+		};
+	};
+
+	cpu-pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
+	};
+
+	thermal-zones {
+		cpu-thermal0 {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 4>;
+
+			trips {
+				cpu_alert0: trip@0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu_crit0: trip@1 {
+					temperature = <95000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert0>;
+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		cpu-thermal1 {
+			polling-delay-passive = <250>;
+			polling-delay = <1000>;
+
+			thermal-sensors = <&tsens 3>;
+
+			trips {
+				cpu_alert1: trip@0 {
+					temperature = <100000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu_crit1: trip@1 {
+					temperature = <125000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert1>;
+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 	};
 
@@ -74,6 +215,15 @@
 			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
+	clocks {
+		xo_board: xo_board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <19200000>;
+			clock-output-names = "xo_board";
+		};
+	};
+
 	soc: soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -95,19 +245,231 @@
 			#interrupt-cells = <2>;
 		};
 
+		tcsr_mutex_regs: syscon@1905000 {
+			compatible = "syscon";
+			reg = <0x1905000 0x20000>;
+		};
+
+		tcsr_mutex: hwlock {
+			compatible = "qcom,tcsr-mutex";
+			syscon = <&tcsr_mutex_regs 0 0x1000>;
+			#hwlock-cells = <1>;
+		};
+
+		smem {
+			compatible = "qcom,smem";
+			reg = <0x60000 0x8000>;
+			reg-names = "aux-mem1";
+
+			memory-region = <&smem_mem>;
+
+			hwlocks = <&tcsr_mutex 3>;
+		};
+
+
+		apcs: syscon@b011000 {
+			compatible = "syscon";
+			reg = <0x0b011000 0x1000>;
+		};
+
+		smd {
+			compatible = "qcom,smd";
+
+			rpm {
+				interrupts = <0 168 1>;
+				qcom,ipc = <&apcs 8 0>;
+				qcom,smd-edge = <15>;
+				qcom,remote-pid = <0xffffffff>;
+
+				rpm_requests {
+					compatible = "qcom,rpm-msm8916";
+					qcom,smd-channels = "rpm_requests";
+
+					rpmcc: qcom,rpmcc {
+						compatible = "qcom,rpmcc-msm8916";
+						#clock-cells = <1>;
+					};
+
+					pm8916-regulators {
+						compatible = "qcom,rpm-pm8916-regulators";
+
+						vdd_l1_l2_l3-supply = <&pm8916_s3>;
+						vdd_l5-supply = <&pm8916_s3>;
+						vdd_l4_l5_l6-supply = <&pm8916_s4>;
+						vdd_l7-supply = <&pm8916_s4>;
+
+						pm8916_s1: s1 {
+							regulator-min-microvolt = <375000>;
+							regulator-max-microvolt = <1562000>;
+						};
+						s2 {
+							regulator-min-microvolt = <375000>;
+							regulator-max-microvolt = <1562000>;
+						};
+						pm8916_s3: s3 {
+							regulator-min-microvolt = <375000>;
+							regulator-max-microvolt = <1562000>;
+						};
+						pm8916_s4: s4 {
+							regulator-min-microvolt = <1800000>;
+							regulator-max-microvolt = <1800000>;
+							regulator-always-on;
+							regulator-boot-on;
+						};
+
+						pm8916_l1: l1 {
+							regulator-min-microvolt = <375000>;
+							regulator-max-microvolt = <1525000>;
+						};
+						pm8916_l2: l2 {
+							regulator-min-microvolt = <375000>;
+							regulator-max-microvolt = <1525000>;
+						};
+						pm8916_l3: l3 {
+							regulator-min-microvolt = <375000>;
+							regulator-max-microvolt = <1525000>;
+						};
+						pm8916_l4: l4 {
+							regulator-min-microvolt = <1750000>;
+							regulator-max-microvolt = <3337000>;
+						};
+						pm8916_l5: l5 {
+							regulator-min-microvolt = <1750000>;
+							regulator-max-microvolt = <3337000>;
+						};
+						pm8916_l6: l6 {
+							regulator-min-microvolt = <1750000>;
+							regulator-max-microvolt = <3337000>;
+						};
+						pm8916_l7: l7 {
+							regulator-min-microvolt = <1750000>;
+							regulator-max-microvolt = <3337000>;
+						};
+						pm8916_l8: l8 {
+							regulator-min-microvolt = <1750000>;
+							regulator-max-microvolt = <3337000>;
+						};
+						pm8916_l9: l9 {
+							regulator-min-microvolt = <1750000>;
+							regulator-max-microvolt = <3337000>;
+						};
+						pm8916_l10: l10 {
+							regulator-min-microvolt = <1750000>;
+							regulator-max-microvolt = <3337000>;
+						};
+						pm8916_l11: l11 {
+							regulator-min-microvolt = <1750000>;
+							regulator-max-microvolt = <3337000>;
+						};
+						pm8916_l12: l12 {
+							regulator-min-microvolt = <1750000>;
+							regulator-max-microvolt = <3337000>;
+						};
+						pm8916_l13: l13 {
+							regulator-min-microvolt = <1750000>;
+							regulator-max-microvolt = <3337000>;
+						};
+						pm8916_l14: l14 {
+							regulator-min-microvolt = <1750000>;
+							regulator-max-microvolt = <3337000>;
+						};
+						pm8916_l15: l15 {
+							regulator-min-microvolt = <1750000>;
+							regulator-max-microvolt = <3337000>;
+						};
+						pm8916_l16: l16 {
+							regulator-min-microvolt = <1750000>;
+							regulator-max-microvolt = <3337000>;
+						};
+						pm8916_l17: l17 {
+							regulator-min-microvolt = <1750000>;
+							regulator-max-microvolt = <3337000>;
+						};
+						pm8916_l18: l18 {
+							regulator-min-microvolt = <1750000>;
+							regulator-max-microvolt = <3337000>;
+						};
+					};
+				};
+			};
+
+			pronto_smd_edge: pronto {
+				interrupts = <0 142 1>;
+
+				qcom,ipc = <&apcs 8 17>;
+				qcom,smd-edge = <6>;
+				qcom,remote-pid = <4>;
+
+#if 0
+				bt {
+					compatible = "qcom,hci-smd";
+					qcom,smd-channels = "APPS_RIVA_BT_CMD", "APPS_RIVA_BT_ACL";
+					qcom,smd-channel-names = "event", "data";
+				};
+
+				ipcrtr {
+					compatible = "qcom,ipcrtr";
+					qcom,smd-channels = "IPCRTR";
+				};
+
+				wifi {
+					compatible = "qcom,wcn3680";
+					qcom,smd-channels = "WLAN_CTRL";
+
+					interrupts = <0 145 0>, <0 146 0>;
+					interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq";
+
+					qcom,wcnss_mmio = <0xfb000000 0x21b000>;
+
+					qcom,tx-enable-gpios = <&apps_smsm 10 0>;
+					qcom,tx-rings-empty-gpios = <&apps_smsm 9 0>;
+				};
+
+				wcnss_ctrl {
+					compatible = "qcom,wcnss-ctrl";
+					qcom,smd-channels = "WCNSS_CTRL";
+
+					qcom,wcnss_mmio = <0xfb21b000 0x3000>;
+				};
+#endif
+			};
+		};
+
 		gcc: qcom,gcc@1800000 {
 			compatible = "qcom,gcc-msm8916";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
+			#power-domain-cells = <1>;
 			reg = <0x1800000 0x80000>;
 		};
 
+		a53cc: qcom,a53cc@0b016000 {
+			compatible = "qcom,clock-a53-msm8916";
+			reg = <0x0b016000 0x40>;
+			#clock-cells = <1>;
+			qcom,apcs = <&apcs>;
+		};
+
+		blsp1_uart1: serial@78af000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x78af000 0x200>;
+			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			dmas = <&blsp_dma 1>, <&blsp_dma 0>;
+			dma-names = "rx", "tx";
+			status = "disabled";
+		};
+
 		blsp1_uart2: serial@78b0000 {
 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 			reg = <0x78b0000 0x200>;
 			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 			clock-names = "core", "iface";
+			dmas = <&blsp_dma 3>, <&blsp_dma 2>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 		};
 
@@ -224,6 +586,21 @@
 			status = "disabled";
 		};
 
+		blsp_i2c2: i2c@78b6000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x78b6000 0x1000>;
+			interrupts = <GIC_SPI 96 0>;
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+				<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+			clock-names = "iface", "core";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&i2c2_default>;
+			pinctrl-1 = <&i2c2_sleep>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		blsp_i2c4: i2c@78b8000 {
 			compatible = "qcom,i2c-qup-v2.2.1";
 			reg = <0x78b8000 0x1000>;
@@ -239,6 +616,21 @@
 			status = "disabled";
 		};
 
+		blsp_i2c6: i2c@78ba000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x78ba000 0x1000>;
+			interrupts = <GIC_SPI 100 0>;
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+				<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
+			clock-names = "iface", "core";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&i2c6_default>;
+			pinctrl-1 = <&i2c6_sleep>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		sdhc_1: sdhci@07824000 {
 			compatible = "qcom,sdhci-msm-v4";
 			reg = <0x07824900 0x11c>, <0x07824000 0x800>;
@@ -291,10 +683,13 @@
 			interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
 				     <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
 
+			v1p8-supply = <&pm8916_l7>;
+			v3p3-supply = <&pm8916_l13>;
 			qcom,vdd-levels = <1 5 7>;
 			qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
 			dr_mode = "peripheral";
 			qcom,otg-control = <2>; // PMIC
+			qcom,manual-pullup;
 
 			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 				 <&gcc GCC_USB_HS_SYSTEM_CLK>,
@@ -314,6 +709,11 @@
 			reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 		};
 
+		l2ccc_0: clock-controller@b011000 {
+			compatible = "qcom,8916-l2ccc";
+			reg = <0x0b011000 0x1000>;
+		};
+
 		timer@b020000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -390,7 +790,189 @@
 			interrupt-controller;
 			#interrupt-cells = <4>;
 		};
+
+		acc0: clock-controller@b088000 {
+			compatible = "qcom,arm-cortex-acc";
+			reg = <0x0b088000 0x1000>,
+			      <0x0b008000 0x1000>;
+		};
+
+		acc1: clock-controller@b098000 {
+			compatible = "qcom,arm-cortex-acc";
+			reg = <0x0b098000 0x1000>,
+			      <0x0b008000 0x1000>;
+		};
+
+		acc2: clock-controller@b0a8000 {
+			compatible = "qcom,arm-cortex-acc";
+			reg = <0x0b0a8000 0x1000>,
+			      <0x0b008000 0x1000>;
+		};
+
+		acc3: clock-controller@b0b8000 {
+			compatible = "qcom,arm-cortex-acc";
+			reg = <0x0b0b8000 0x1000>,
+			      <0x0b008000 0x1000>;
+		};
+
+		/* Audio */
+
+		wcd_digital: codec-digital{
+			compatible = "syscon", "qcom,apq8016-wcd-digital-codec";
+			reg = <0x0771c000 0x400>;
+		};
+
+		lpass: lpass-cpu@07700000 {
+			status = "disabled";
+			compatible = "qcom,lpass-cpu-apq8016";
+			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
+				 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
+				 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
+				 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
+				 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
+				 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>,
+				 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
+
+			clock-names = "ahbix-clk",
+					"pcnoc-mport-clk",
+					"pcnoc-sway-clk",
+					"mi2s-bit-clk0",
+					"mi2s-bit-clk1",
+					"mi2s-bit-clk2",
+					"mi2s-bit-clk3";
+			#sound-dai-cells = <1>;
+
+			interrupts = <0 160 0>;
+			interrupt-names = "lpass-irq-lpaif";
+			reg = <0x07708000 0x10000>, <0x07702000 0x4>, <0x07702004 0x4>;
+			reg-names = "lpass-lpaif", "mic-iomux", "spkr-iomux";
+		};
+
+		sound: sound {
+			status = "disabled";
+			compatible = "qcom,apq8016-sbc-sndcard";
+			reg = <0x07702000 0x4>, <0x07702004 0x4>;
+			reg-names = "mic-iomux", "spkr-iomux";
+		};
+
+	        tcsr: syscon@1937000 {
+			compatible = "qcom,tcsr-msm8916", "syscon";
+			reg = <0x1937000 0x30000>;
+		};
+
+		uqfprom: eeprom@58000 {
+			compatible = "qcom,qfprom-msm8916";
+			reg = <0x58000 0x7000>;
+		};
+
+		cpr@b018000 {
+			compatible = "qcom,cpr";
+			reg = <0xb018000 0x1000>;
+			interrupts = <0 15 1>, <0 16 1>, <0 17 1>;
+			vdd-mx-supply = <&pm8916_l3>;
+			acc-syscon = <&tcsr>;
+			eeprom = <&uqfprom>;
+
+			qcom,cpr-ref-clk = <19200>;
+			qcom,cpr-timer-delay-us = <5000>;
+			qcom,cpr-timer-cons-up = <0>;
+			qcom,cpr-timer-cons-down = <2>;
+			qcom,cpr-up-threshold = <0>;
+			qcom,cpr-down-threshold = <2>;
+			qcom,cpr-idle-clocks = <15>;
+			qcom,cpr-gcnt-us = <1>;
+			qcom,vdd-apc-step-up-limit = <1>;
+			qcom,vdd-apc-step-down-limit = <1>;
+			qcom,cpr-cpus = <&CPU0 &CPU1 &CPU2 &CPU3>;
+		};
+
+		qfprom: qfprom@5c000 {
+			compatible = "qcom,qfprom";
+			reg = <0x5c000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			tsens_caldata: caldata@d0 {
+				reg = <0xd0 0x8>;
+			};
+			tsens_calsel: calsel@ec {
+				reg = <0xec 0x4>;
+			};
+		};
+
+		tsens: thermal-sensor@4a8000 {
+			compatible = "qcom,msm8916-tsens";
+			reg = <0x4a8000 0x2000>;
+			nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
+			nvmem-cell-names = "calib", "calib_sel";
+			qcom,tsens-slopes = <3200 3200 3200 3200 3200>;
+			qcom,sensor-id = <0 1 2 4 5>;
+			#thermal-sensor-cells = <1>;
+		};
+
+		wcnss-smp2p {
+			compatible = "qcom,smp2p";
+			qcom,smem = <451>, <431>;
+
+			interrupts = <0 143 1>;
+
+			qcom,ipc = <&apcs 8 18>;
+
+			qcom,local-pid = <0>;
+			qcom,remote-pid = <4>;
+
+			wcnss_smp2p_out: master-kernel {
+				qcom,entry-name = "master-kernel";
+				qcom,outbound;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			wcnss_smp2p_in: slave-kernel {
+				qcom,entry-name = "slave-kernel";
+				qcom,inbound;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+		};
+
+		pronto_rproc {
+			compatible = "qcom,tz-pil";
+
+			interrupts-extended = <&intc 0 149 1>,
+					      <&wcnss_smp2p_in 0 0>,
+					      <&wcnss_smp2p_in 1 0>,
+					      <&wcnss_smp2p_in 2 0>,
+					      <&wcnss_smp2p_in 3 0>;
+			interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
+
+			clocks = <&gcc GCC_CRYPTO_CLK>,
+				 <&gcc GCC_CRYPTO_AHB_CLK>,
+				 <&gcc GCC_CRYPTO_AXI_CLK>,
+				 <&gcc CRYPTO_CLK_SRC>;
+			clock-names = "scm_core_clk", "scm_iface_clk", "scm_bus_clk", "scm_src_clk";
+
+			qcom,firmware-name = "wcnss";
+			qcom,pas-id = <6>;
+
+			qcom,crash-reason = <422>;
+			qcom,smd-edges = <&pronto_smd_edge>;
+
+			qcom,pll-supply = <&pm8916_l7>;
+			qcom,pll-uV = <1800000>;
+			qcom,pll-uA = <18000>;
+
+			qcom,stop-gpio = <&wcnss_smp2p_out 0 0>;
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&wcnss_default>;
+
+			memory-region = <&peripheral_mem>;
+		};
 	};
 };
 
 #include "msm8916-pins.dtsi"
+#include "msm8916-iommu.dtsi"
+#include "msm8916-coresight.dtsi"
diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi
index b222ece7e3d2..5f6a92516eab 100644
--- a/arch/arm64/boot/dts/qcom/pm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi
@@ -95,5 +95,131 @@
 		reg = <0x1 SPMI_USID>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+
+		regulators {
+			compatible = "qcom,pm8916-regulators";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			s1@1400 {
+				reg = <0x1400 0x300>;
+				status = "disabled";
+			};
+
+			pm8916_s2: s2@1700 {
+				reg = <0x1700 0x300>;
+				status = "ok";
+				regulator-min-microvolt = <1050000>;
+				regulator-max-microvolt = <1350000>;
+			};
+
+			s3@1a00 {
+				reg = <0x1a00 0x300>;
+				status = "disabled";
+			};
+
+			s4@1d00 {
+				reg = <0x1d00 0x300>;
+				status = "disabled";
+			};
+
+			l1@4000 {
+				reg = <0x4000 0x100>;
+				status = "disabled";
+			};
+
+			l2@4100 {
+				reg = <0x4100 0x100>;
+				status = "disabled";
+			};
+
+			l3@4200 {
+				reg = <0x4200 0x100>;
+				status = "disabled";
+			};
+
+			l4@4300 {
+				reg = <0x4300 0x100>;
+				status = "disabled";
+			};
+
+			l5@4400 {
+				reg = <0x4400 0x100>;
+				status = "disabled";
+			};
+
+			l6@4500 {
+				reg = <0x4500 0x100>;
+				status = "disabled";
+			};
+
+			l7@4600 {
+				reg = <0x4600 0x100>;
+				status = "disabled";
+			};
+
+			l8@4700 {
+				reg = <0x4700 0x100>;
+				status = "disabled";
+			};
+
+			l9@4800 {
+				reg = <0x4800 0x100>;
+				status = "disabled";
+			};
+
+			l10@4900 {
+				reg = <0x4900 0x100>;
+				status = "disabled";
+			};
+
+			l11@4a00 {
+				reg = <0x4a00 0x100>;
+				status = "disabled";
+			};
+
+			l12@4b00 {
+				reg = <0x4b00 0x100>;
+				status = "disabled";
+			};
+
+			l13@4c00 {
+				reg = <0x4c00 0x100>;
+				status = "disabled";
+			};
+
+			l14@4d00 {
+				reg = <0x4d00 0x100>;
+				status = "disabled";
+			};
+
+			l15@4e00 {
+				reg = <0x4e00 0x100>;
+				status = "disabled";
+			};
+
+			l16@4f00 {
+				reg = <0x4f00 0x100>;
+				status = "disabled";
+			};
+
+			l17@5000 {
+				reg = <0x5000 0x100>;
+				status = "disabled";
+			};
+
+			l18@5100 {
+				reg = <0x5100 0x100>;
+				status = "disabled";
+			};
+		};
+
+		wcd_codec: codec@f000 {
+			compatible = "qcom,apq8016-wcd-codec";
+			reg = <0xf000 0x200>;
+			#sound-dai-cells = <0>;
+			vddio-supply = <&pm8916_l5>;
+			vdd-pa-supply = <&pm8916_s4>;
+		};
 	};
 };
diff --git a/include/dt-bindings/arm/qcom-ids.h b/include/dt-bindings/arm/qcom-ids.h
new file mode 100644
index 000000000000..a18f34e7d965
--- /dev/null
+++ b/include/dt-bindings/arm/qcom-ids.h
@@ -0,0 +1,33 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_QCOM_IDS_H
+#define __DT_BINDINGS_QCOM_IDS_H
+
+/* qcom,msm-id */
+#define QCOM_ID_MSM8916		206
+#define QCOM_ID_APQ8016		247
+#define QCOM_ID_MSM8216		248
+#define QCOM_ID_MSM8116		249
+#define QCOM_ID_MSM8616		250
+
+/* qcom,board-id */
+#define QCOM_BRD_ID(a, major, minor) \
+	(((major & 0xff) << 16) | ((minor & 0xff) << 8) | QCOM_BRD_ID_##a)
+
+#define QCOM_BRD_ID_MTP		8
+#define QCOM_BRD_ID_DRAGONBRD	10
+#define QCOM_BRD_ID_SBC		24
+
+#define QCOM_BRD_SUBTYPE_DEFAULT		0
+#define QCOM_BRD_SUBTYPE_MTP8916_SMB1360	1
+
+#endif