Orangepi i96 support (mega patch)rda/v2012.04.01-r0

This is https://github.com/orangepi-xunlong/OrangePiRDA_u-boot
5ee06c1afb7c ("add new patch a patch") as a single patch against
a guestimated upstream version.

This is merely a reference tree for later comparisons.

Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
NOT-Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>

1068 files changed, 212576 insertions, 16804 deletions

diff --git a/.checkpatch.conf b/.checkpatch.conf
deleted file mode 100644
index 977db9edbb..0000000000
--- a/.checkpatch.conf
+++ /dev/null
@@ -1,14 +0,0 @@
-# Not Linux, so don't expect a Linux tree.
---no-tree
-
-# Temporary for false positive in checkpatch
---ignore COMPLEX_MACRO
-
-# For CONFIG_SYS_I2C_NOPROBES
---ignore MULTISTATEMENT_MACRO_USE_DO_WHILE
-
-# For simple_strtoul
---ignore CONSIDER_KSTRTO
-
-# For min/max
---ignore MINMAX
diff --git a/.gitignore b/.gitignore
index 0f32fd8954..e351010f09 100644
--- a/.gitignore
+++ b/.gitignore
@@ -5,52 +5,61 @@
 #
 # Normal rules
 #
-
-*.rej
-*.orig
-*.a
+.*
 *.o
+*.o.*
+*.a
+*.s
 *.su
-*~
+*.mod.c
+*.i
+*.lst
+*.order
+*.elf
 *.swp
-*.patch
 *.bin
+*.patch
+*.cfgtmp
+*.rda
+*.img
+
+# host programs on Cygwin
+*.exe
+
+# Build tree
+/build-*
 
 #
 # Top-level generic files
 #
-
-/MLO
+/MLO*
+/SPL
 /System.map
-/u-boot
-/u-boot.hex
-/u-boot.imx
-/u-boot.map
-/u-boot.srec
-/u-boot.ldr
-/u-boot.ldr.hex
-/u-boot.ldr.srec
-/u-boot.img
-/u-boot.kwb
-/u-boot.sha1
-/u-boot.dis
-/u-boot.lds
-/u-boot.ubl
-/u-boot.ais
-/u-boot.dtb
-/u-boot.sb
+/u-boot*
+
+#
+# git files that we don't want to ignore even it they are dot-files
+#
+!.gitignore
+!.mailmap
 
 #
 # Generated files
 #
 
-*.depend*
 /LOG
 /errlog
 /reloc_off
 
+/tpl/
+
+#
+# Generated include files
+#
+/include/config/
 /include/generated/
-asm-offsets.s
+/include/spl-autoconf.mk
+/include/tpl-autoconf.mk
 
 # stgit generated dirs
 patches-*
@@ -71,7 +80,15 @@ cscope.*
 /ctags
 /etags
 
-# OneNAND IPL files
-/onenand_ipl/onenand-ipl*
-/onenand_ipl/board/*/onenand*
-/onenand_ipl/board/*/*.S
+# gnu global files
+GPATH
+GRTAGS
+GSYMS
+GTAGS
+
+*.orig
+*~
+\#*#
+
+/cur.log
+
diff --git a/CleanSpec.mk b/CleanSpec.mk
new file mode 100644
index 0000000000..b84e1b65e7
--- /dev/null
+++ b/CleanSpec.mk
@@ -0,0 +1,49 @@
+# Copyright (C) 2007 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+# If you don't need to do a full clean build but would like to touch
+# a file or delete some intermediate files, add a clean step to the end
+# of the list.  These steps will only be run once, if they haven't been
+# run before.
+#
+# E.g.:
+#     $(call add-clean-step, touch -c external/sqlite/sqlite3.h)
+#     $(call add-clean-step, rm -rf $(PRODUCT_OUT)/obj/STATIC_LIBRARIES/libz_intermediates)
+#
+# Always use "touch -c" and "rm -f" or "rm -rf" to gracefully deal with
+# files that are missing or have been moved.
+#
+# Use $(PRODUCT_OUT) to get to the "out/target/product/blah/" directory.
+# Use $(OUT_DIR) to refer to the "out" directory.
+#
+# If you need to re-do something that's already mentioned, just copy
+# the command and add it to the bottom of the list.  E.g., if a change
+# that you made last week required touching a file and a change you
+# made today requires touching the same file, just copy the old
+# touch step and add it to the end of the list.
+#
+# ************************************************
+# NEWER CLEAN STEPS MUST BE AT THE END OF THE LIST
+# ************************************************
+
+# For example:
+#$(call add-clean-step, rm -rf $(OUT_DIR)/target/common/obj/APPS/AndroidTests_intermediates)
+#$(call add-clean-step, rm -rf $(OUT_DIR)/target/common/obj/JAVA_LIBRARIES/core_intermediates)
+#$(call add-clean-step, find $(OUT_DIR) -type f -name "IGTalkSession*" -print0 | xargs -0 rm -f)
+#$(call add-clean-step, rm -rf $(PRODUCT_OUT)/data/*)
+
+# ************************************************
+# NEWER CLEAN STEPS MUST BE AT THE END OF THE LIST
+# ************************************************
diff --git a/MAINTAINERS b/MAINTAINERS
index 708ded79f6..f796872dca 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -777,6 +777,10 @@ Linus Walleij <linus.walleij@linaro.org>
 	integratorap	various
 	integratorcp	various
 
+Luka Perkov <uboot@lukaperkov.net>
+
+	ib62x0		ARM926EJS
+
 Dave Peverley <dpeverley@mpc-data.co.uk>
 
 	omap730p2	ARM926EJS
@@ -788,6 +792,16 @@ Stelian Pop <stelian@popies.net>
 	at91sam9263ek	ARM926EJS (AT91SAM9263 SoC)
 	at91sam9rlek	ARM926EJS (AT91SAM9RL SoC)
 
+Dave Purdy <david.c.purdy@gmail.com>
+
+	pogo_e02	ARM926EJS (Kirkwood SoC)
+
+Sricharan R <r.sricharan@ti.com>
+
+	omap4_panda	ARM ARMV7 (OMAP4xx SoC)
+	omap4_sdp4430	ARM ARMV7 (OMAP4xx SoC)
+	omap5_evm	ARM ARMV7 (OMAP5xx Soc)
+
 Thierry Reding <thierry.reding@avionic-design.de>
 
 	plutux		Tegra2 (ARM7 & A9 Dual Core)
@@ -860,12 +874,6 @@ Greg Ungerer <greg.ungerer@opengear.com>
 	cm4116		ks8695p
 	cm4148		ks8695p
 
-Aneesh V <aneesh@ti.com>
-
-	omap4_panda	ARM ARMV7 (OMAP4xx SoC)
-	omap4_sdp4430	ARM ARMV7 (OMAP4xx SoC)
-	omap5_evm	ARM ARMV7 (OMAP5xx Soc)
-
 Marek Vasut <marek.vasut@gmail.com>
 
 	balloon3	xscale/pxa
@@ -932,6 +940,10 @@ Sughosh Ganu <urwithsughosh@gmail.com>
 
 	hawkboard	ARM926EJS (OMAP-L138)
 
+Vladimir Zapolskiy <vz@mleia.com>
+
+	devkit3250	lpc32xx
+
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:
@@ -1191,6 +1203,7 @@ Macpaul Lin <macpaul@andestech.com>
 
 	ADP-AG101	N1213 (AG101 SoC)
 	ADP-AG101P	N1213 (AG101P XC5 FPGA)
+	ADP-AG102	N1213f (AG102 SoC with FPU)
 
 #########################################################################
 # OpenRISC Systems:							#
diff --git a/MAKEALL b/MAKEALL
index e5da6f1859..2e8b9973d7 100755..100644
--- a/MAKEALL
+++ b/MAKEALL
@@ -34,6 +34,7 @@ usage()
 	  CROSS_COMPILE    cross-compiler toolchain prefix (default: "")
 	  MAKEALL_LOGDIR   output all logs to here (default: ./LOG/)
 	  BUILD_DIR        output build directory (default: ./)
+	  BUILD_NBUILDS	   number of parallel targets (default: 1)
 
 	Examples:
 	  - build all Power Architecture boards:
@@ -178,18 +179,33 @@ else
 	LOG_DIR="LOG"
 fi
 
-if [ ! "${BUILD_DIR}" ] ; then
-	BUILD_DIR="."
+: ${BUILD_NBUILDS:=1}
+BUILD_MANY=0
+
+if [ "${BUILD_NBUILDS}" -gt 1 ] ; then
+	BUILD_MANY=1
+	: ${BUILD_DIR:=./build}
+	mkdir -p "${BUILD_DIR}/ERR"
+	find "${BUILD_DIR}/ERR/" -type f -exec rm -f {} +
 fi
 
-[ -d ${LOG_DIR} ] || mkdir ${LOG_DIR} || exit 1
+: ${BUILD_DIR:=.}
+
+OUTPUT_PREFIX="${BUILD_DIR}"
+
+[ -d ${LOG_DIR} ] || mkdir "${LOG_DIR}" || exit 1
+find "${LOG_DIR}/" -type f -exec rm -f {} +
 
 LIST=""
 
 # Keep track of the number of builds and errors
 ERR_CNT=0
 ERR_LIST=""
+WRN_CNT=0
+WRN_LIST=""
 TOTAL_CNT=0
+CURRENT_CNT=0
+OLDEST_IDX=1
 RC=0
 
 # Helper funcs for parsing boards.cfg
@@ -326,12 +342,7 @@ LIST_ARM9="$(boards_by_cpu arm920t)	\
 #########################################################################
 ## ARM11 Systems
 #########################################################################
-LIST_ARM11="$(boards_by_cpu arm1136)	\
-	imx31_phycore		\
-	imx31_phycore_eet	\
-	mx31pdk			\
-	smdk6400		\
-"
+LIST_ARM11="$(boards_by_cpu arm1136)"
 
 #########################################################################
 ## ARMV7 Systems
@@ -351,10 +362,7 @@ LIST_at91="$(boards_by_soc at91)"
 
 LIST_pxa="$(boards_by_cpu pxa)"
 
-LIST_ixp="$(boards_by_cpu ixp)
-	pdnb3		\
-	scpu		\
-"
+LIST_ixp="$(boards_by_cpu ixp)"
 
 #########################################################################
 ## ARM groups
@@ -592,41 +600,106 @@ list_target() {
 	echo ""
 }
 
+# Each finished build will have a file called ${donep}${n},
+# where n is the index of the build. Each build
+# we've already noted as finished will have ${skipp}${n}.
+# The code managing the build process will use this information
+# to ensure that only BUILD_NBUILDS builds are in flight at once
+donep="${LOG_DIR}/._done_"
+skipp="${LOG_DIR}/._skip_"
+
 build_target() {
 	target=$1
+	build_idx=$2
 
 	if [ "$ONLY_LIST" == 'y' ] ; then
 		list_target ${target}
 		return
 	fi
 
+	if [ $BUILD_MANY == 1 ] ; then
+		output_dir="${OUTPUT_PREFIX}/${target}"
+		mkdir -p "${output_dir}"
+	else
+		output_dir="${OUTPUT_PREFIX}"
+	fi
+
+	export BUILD_DIR="${output_dir}"
+
 	${MAKE} distclean >/dev/null
 	${MAKE} -s ${target}_config
 
-	${MAKE} ${JOBS} all 2>&1 >${LOG_DIR}/$target.MAKELOG \
-				| tee ${LOG_DIR}/$target.ERR
+	${MAKE} ${JOBS} all \
+		>${LOG_DIR}/$target.MAKELOG 2> ${LOG_DIR}/$target.ERR
 
 	# Check for 'make' errors
 	if [ ${PIPESTATUS[0]} -ne 0 ] ; then
 		RC=1
 	fi
 
-	if [ -s ${LOG_DIR}/$target.ERR ] ; then
-		ERR_CNT=$((ERR_CNT + 1))
-		ERR_LIST="${ERR_LIST} $target"
+	if [ $BUILD_MANY == 1 ] ; then
+		${MAKE} tidy
+
+		if [ -s ${LOG_DIR}/${target}.ERR ] ; then
+			cp ${LOG_DIR}/${target}.ERR ${OUTPUT_PREFIX}/ERR/${target}
+		else
+			rm ${LOG_DIR}/${target}.ERR
+		fi
 	else
-		rm ${LOG_DIR}/$target.ERR
+		if [ -s ${LOG_DIR}/${target}.ERR ] ; then
+			if grep -iw error ${LOG_DIR}/${target}.ERR ; then
+				: $(( ERR_CNT += 1 ))
+				ERR_LIST="${ERR_LIST} $target"
+			else
+				: $(( WRN_CNT += 1 ))
+				WRN_LIST="${WRN_LIST} $target"
+			fi
+		else
+			rm ${LOG_DIR}/${target}.ERR
+		fi
 	fi
 
-	TOTAL_CNT=$((TOTAL_CNT + 1))
-
-	OBJS=${BUILD_DIR}/u-boot
-	if [ -e ${BUILD_DIR}/spl/u-boot-spl ]; then
-		OBJS="${OBJS} ${BUILD_DIR}/spl/u-boot-spl"
+	OBJS=${output_dir}/u-boot
+	if [ -e ${output_dir}/spl/u-boot-spl ]; then
+		OBJS="${OBJS} ${output_dir}/spl/u-boot-spl"
 	fi
 
 	${CROSS_COMPILE}size ${OBJS} | tee -a ${LOG_DIR}/$target.MAKELOG
+
+	[ -e "${LOG_DIR}/${target}.ERR" ] && cat "${LOG_DIR}/${target}.ERR"
+
+	touch "${donep}${build_idx}"
+}
+
+manage_builds() {
+	search_idx=${OLDEST_IDX}
+	if [ "$ONLY_LIST" == 'y' ] ; then return ; fi
+
+	while true; do
+		if [ -e "${donep}${search_idx}" ] ; then
+			: $(( CURRENT_CNT-- ))
+			[ ${OLDEST_IDX} -eq ${search_idx} ] &&
+				: $(( OLDEST_IDX++ ))
+
+			# Only want to count it once
+			rm -f "${donep}${search_idx}"
+			touch "${skipp}${search_idx}"
+		elif [ -e "${skipp}${search_idx}" ] ; then
+			[ ${OLDEST_IDX} -eq ${search_idx} ] &&
+				: $(( OLDEST_IDX++ ))
+		fi
+		: $(( search_idx++ ))
+		if [ ${search_idx} -gt ${TOTAL_CNT} ] ; then
+			if [ ${CURRENT_CNT} -ge ${BUILD_NBUILDS} ] ; then
+				search_idx=${OLDEST_IDX}
+				sleep 1
+			else
+				break
+			fi
+		fi
+	done
 }
+
 build_targets() {
 	for t in "$@" ; do
 		# If a LIST_xxx var exists, use it.  But avoid variable
@@ -639,23 +712,71 @@ build_targets() {
 		if [ -n "${list}" ] ; then
 			build_targets ${list}
 		else
-			build_target ${t}
+			: $((TOTAL_CNT += 1))
+			: $((CURRENT_CNT += 1))
+			rm -f "${donep}${TOTAL_CNT}"
+			rm -f "${skipp}${TOTAL_CNT}"
+			if [ $BUILD_MANY == 1 ] ; then
+				build_target ${t} ${TOTAL_CNT} &
+			else
+				build_target ${t} ${TOTAL_CNT}
+			fi
+		fi
+
+		# We maintain a running count of all the builds we have done.
+		# Each finished build will have a file called ${donep}${n},
+		# where n is the index of the build. Each build
+		# we've already noted as finished will have ${skipp}${n}.
+		# We track the current index via TOTAL_CNT, and the oldest
+		# index. When we exceed the maximum number of parallel builds,
+		# We look from oldest to current for builds that have completed,
+		# and update the current count and oldest index as appropriate.
+		# If we've gone through the entire list, wait a second, and
+		# reprocess the entire list until we find a build that has
+		# completed
+		if [ ${CURRENT_CNT} -ge ${BUILD_NBUILDS} ] ; then
+			manage_builds
 		fi
 	done
 }
 
 #-----------------------------------------------------------------------
 
+kill_children() {
+	kill -- "-$1"
+
+	exit
+}
+
 print_stats() {
 	if [ "$ONLY_LIST" == 'y' ] ; then return ; fi
+
+	rm -f ${donep}* ${skipp}*
+
+	if [ $BUILD_MANY == 1 ] && [ -e "${OUTPUT_PREFIX}/ERR" ] ; then
+		ERR_LIST=`grep -iwl error ${OUTPUT_PREFIX}/ERR/*`
+		ERR_LIST=`for f in $ERR_LIST ; do echo -n " $(basename $f)" ; done`
+		ERR_CNT=`echo $ERR_LIST | wc -w | awk '{print $1}'`
+		WRN_LIST=`grep -iwL error ${OUTPUT_PREFIX}/ERR/*`
+		WRN_LIST=`for f in $WRN_LIST ; do echo -n " $(basename $f)" ; done`
+		WRN_CNT=`echo $WRN_LIST | wc -w | awk '{print $1}'`
+	fi
+
 	echo ""
 	echo "--------------------- SUMMARY ----------------------------"
 	echo "Boards compiled: ${TOTAL_CNT}"
 	if [ ${ERR_CNT} -gt 0 ] ; then
-		echo "Boards with warnings or errors: ${ERR_CNT} (${ERR_LIST} )"
+		echo "Boards with errors: ${ERR_CNT} (${ERR_LIST} )"
+	fi
+	if [ ${WRN_CNT} -gt 0 ] ; then
+		echo "Boards with warnings but no errors: ${WRN_CNT} (${WRN_LIST} )"
 	fi
 	echo "----------------------------------------------------------"
 
+	if [ $BUILD_MANY == 1 ] ; then
+		kill_children $$ &
+	fi
+
 	exit $RC
 }
 
@@ -666,3 +787,4 @@ set -- ${SELECTED} "$@"
 # run PowerPC by default
 [ $# = 0 ] && set -- powerpc
 build_targets "$@"
+wait
diff --git a/Makefile b/Makefile
index 023ea23a38..da80fec62d 100644
--- a/Makefile
+++ b/Makefile
@@ -23,8 +23,8 @@
 
 VERSION = 2012
 PATCHLEVEL = 04
-SUBLEVEL = 01
-EXTRAVERSION =
+SUBLEVEL = 442
+EXTRAVERSION = -rel5.0.2
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else
@@ -58,10 +58,15 @@ VENDOR=
 
 #########################################################################
 # Allow for silent builds
+ifneq (1,$(V))
+export MAKEFLAGS += -s --no-print-directory
+export STDOUT_NULL := 1>/dev/null
+endif
+
 ifeq (,$(findstring s,$(MAKEFLAGS)))
-XECHO = echo
+export XECHO = :
 else
-XECHO = :
+export XECHO = echo
 endif
 
 #########################################################################
@@ -110,6 +115,7 @@ TOPDIR		:= $(SRCTREE)
 LNDIR		:= $(OBJTREE)
 export	TOPDIR SRCTREE OBJTREE SPLTREE
 
+
 MKCONFIG	:= $(SRCTREE)/mkconfig
 export MKCONFIG
 
@@ -140,7 +146,7 @@ unexport CDPATH
 # The "examples" conditionally depend on U-Boot (say, when USE_PRIVATE_LIBGCC
 # is "yes"), so compile examples after U-Boot is compiled.
 SUBDIR_TOOLS = tools
-SUBDIR_EXAMPLES = examples/standalone examples/api
+#SUBDIR_EXAMPLES = examples/standalone examples/api
 SUBDIRS = $(SUBDIR_TOOLS)
 
 .PHONY : $(SUBDIRS) $(VERSION_FILE) $(TIMESTAMP_FILE)
@@ -301,6 +307,9 @@ LIBS += common/libcommon.o
 LIBS += lib/libfdt/libfdt.o
 LIBS += api/libapi.o
 LIBS += post/libpost.o
+LIBS += android/libandroid.o
+LIBS += pdl/common/libpdl_common.o
+LIBS += pdl/pdl-2/libpdl_stage.o
 
 ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
 LIBS += $(CPUDIR)/omap-common/libomap-common.o
@@ -370,12 +379,13 @@ BOARD_SIZE_CHECK =
 endif
 
 # Always append ALL so that arch config.mk's can add custom ones
-ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
+ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(obj)u-boot.img
 
 ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
 ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
 ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin
-ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
+ALL-$(CONFIG_SPL) += $(obj)u-boot$(RDASIGN).rda $(obj)spl/u-boot-spl$(RDASIGN).img \
+                     $(obj)spl/u-boot-spl.bin
 ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
 
 all:		$(ALL-y) $(SUBDIR_EXAMPLES)
@@ -409,41 +419,82 @@ $(obj)u-boot.ldr.srec:	$(obj)u-boot.ldr
 		$(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ -I binary
 
 $(obj)u-boot.img:	$(obj)u-boot.bin
+		$(XECHO)
+		$(XECHO) "	GEN	$(@F)"
 		$(obj)tools/mkimage -A $(ARCH) -T firmware -C none \
 		-O u-boot -a $(CONFIG_SYS_TEXT_BASE) -e 0 \
 		-n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
 			sed -e 's/"[	 ]*$$/ for $(BOARD) board"/') \
-		-d $< $@
+		-d $< $@ $(STDOUT_NULL)
 
 $(obj)u-boot.imx:       $(obj)u-boot.bin
+		$(XECHO)
+		$(XECHO) "	GEN	$(@F)"
 		$(obj)tools/mkimage -n  $(CONFIG_IMX_CONFIG) -T imximage \
-		-e $(CONFIG_SYS_TEXT_BASE) -d $< $@
+		-e $(CONFIG_SYS_TEXT_BASE) -d $< $@ $(STDOUT_NULL)
 
 $(obj)u-boot.kwb:       $(obj)u-boot.bin
+		$(XECHO)
+		$(XECHO) "	GEN	$(@F)"
 		$(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
-		-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
+		-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d \
+		$< $@ $(STDOUT_NULL)
 
 $(obj)u-boot.sha1:	$(obj)u-boot.bin
 		$(obj)tools/ubsha1 $(obj)u-boot.bin
 
+ifeq ($(RDASIGN),)
+$(obj)pdl1$(RDASIGN).bin: $(obj)spl/u-boot-spl.bin
+		cp $< $@
+else
+$(obj)pdl1$(RDASIGN).bin: $(obj)spl/u-boot-spl$(RDASIGN).img
+		cp $< $@
+endif
+
+$(obj)pdl2.bin:	$(obj)u-boot.bin
+		cp $< $@
+
+.PHONY: PDL
+PDL: depend $(obj)pdl1$(RDASIGN).bin $(obj)pdl2$(RDASIGN).bin
+
+$(obj)pdl2-sign.bin: $(obj)u-boot.bin
+		@echo "Signing: $(notdir $@)"
+		rdasign -Sba $(UBOOT_SIGN_FLAGS) -m $^ -x $@
+
+$(obj)spl/u-boot-spl-sign.img: $(obj)spl/u-boot-spl.img
+		rdacryptotool -m indirect $(SPL_SIGN_FLAGS) -i $^ -o $@
+
+$(obj)u-boot-sign.img: $(obj)u-boot.img
+		@echo "Signing: $(notdir $@)"
+		rdasign -Sba $(UBOOT_SIGN_FLAGS) -m $^ -x $@
+
 $(obj)u-boot.dis:	$(obj)u-boot
 		$(OBJDUMP) -d $< > $@
 
 $(obj)u-boot.ubl:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+		$(XECHO)
+		$(XECHO) "	GEN	$(@F)"
 		$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
 		cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $(obj)u-boot-ubl.bin
 		$(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
-		-e $(CONFIG_SYS_TEXT_BASE) -d $(obj)u-boot-ubl.bin $(obj)u-boot.ubl
+		-e $(CONFIG_SYS_TEXT_BASE) -d $(obj)u-boot-ubl.bin \
+		$(obj)u-boot.ubl $(STDOUT_NULL)
 		rm $(obj)u-boot-ubl.bin
 		rm $(obj)spl/u-boot-spl-pad.bin
 
+$(obj)u-boot$(RDASIGN).rda:  $(obj)spl/u-boot-spl$(RDASIGN).img $(obj)u-boot$(RDASIGN).img
+		$(shell $(TOPDIR)/tools/mkrdaimage.sh $(BOARD_NAND_PAGE_SIZE) \
+			$^  $(SPL_APPENDING_TO) $@)
+
 $(obj)u-boot.ais:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+		$(XECHO)
+		$(XECHO) "	GEN	$(@F)"
 		$(obj)tools/mkimage -s -n /dev/null -T aisimage \
 			-e $(CONFIG_SPL_TEXT_BASE) \
 			-d $(obj)spl/u-boot-spl.bin \
-			$(obj)spl/u-boot-spl.ais
+			$(obj)spl/u-boot-spl.ais $(STDOUT_NULL)
 		$(OBJCOPY) ${OBJCFLAGS} -I binary \
-			--pad-to=$(CONFIG_SPL_MAX_SIZE) -O binary \
+			--pad-to=$(CONFIG_SPL_CODE_MAX_SIZE) -O binary \
 			$(obj)spl/u-boot-spl.ais $(obj)spl/u-boot-spl-pad.ais
 		cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.bin > \
 			$(obj)u-boot.ais
@@ -479,26 +530,39 @@ ifeq ($(CONFIG_KALLSYMS),y)
 endif
 
 $(OBJS):	depend
+		$(XECHO)
+		$(XECHO) "	MAKE	$(subst $(obj),,$@)"
 		$(MAKE) -C $(CPUDIR) $(if $(REMOTE_BUILD),$@,$(notdir $@))
 
 $(LIBS):	depend $(SUBDIR_TOOLS)
+		$(XECHO)
+		$(XECHO) "	MAKE	$(dir $(subst $(obj),,$@))"
 		$(MAKE) -C $(dir $(subst $(obj),,$@))
 
 $(LIBBOARD):	depend $(LIBS)
+		$(XECHO)
+		$(XECHO) "	MAKE	$(dir $(subst $(obj),,$@))"
 		$(MAKE) -C $(dir $(subst $(obj),,$@))
 
 $(SUBDIRS):	depend
+		$(XECHO)
+		$(XECHO) "	MAKE	$(subst $(obj),,$@)"
 		$(MAKE) -C $@ all
 
 $(SUBDIR_EXAMPLES): $(obj)u-boot
 
 $(LDSCRIPT):	depend
+		$(XECHO)
+		$(XECHO) "	GEN	$(notdir $@)"
 		$(MAKE) -C $(dir $@) $(notdir $@)
 
 $(obj)u-boot.lds: $(LDSCRIPT)
 		$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
 
+.PHONY: nand_spl
 nand_spl:	$(TIMESTAMP_FILE) $(VERSION_FILE) depend
+		$(XECHO)
+		$(XECHO) "	MAKE	nand_spl/board/$(BOARDDIR)"
 		$(MAKE) -C nand_spl/board/$(BOARDDIR) all
 
 $(obj)u-boot-nand.bin:	nand_spl $(obj)u-boot.bin
@@ -510,10 +574,21 @@ onenand_ipl:	$(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
 $(obj)u-boot-onenand.bin:	onenand_ipl $(obj)u-boot.bin
 		cat $(ONENAND_BIN) $(obj)u-boot.bin > $(obj)u-boot-onenand.bin
 
-$(obj)spl/u-boot-spl.bin:	$(SUBDIR_TOOLS) depend
+.PHONY: u-boot-spl
+u-boot-spl:	$(SUBDIR_TOOLS) depend
+		$(XECHO)
+		$(XECHO) "	MAKE	$@"
 		$(MAKE) -C spl all
 
+$(obj)spl/u-boot-spl.img $(obj)spl/u-boot-spl.bin: u-boot-spl
+		# The line below make dependencies work, no idea why.
+		# Without the line you have to build twice to get get
+		# the new version of u-boot-spl.img linked at this level.
+		@echo "Build $(notdir $@)"
+
 updater:
+		$(XECHO)
+		$(XECHO) "	MAKE	tools/updater"
 		$(MAKE) -C tools/updater all
 
 # Explicitly make _depend in subdirs containing multiple targets to prevent
@@ -556,6 +631,13 @@ SYSTEM_MAP = \
 $(obj)System.map:	$(obj)u-boot
 		@$(call SYSTEM_MAP,$<) > $(obj)System.map
 
+checkthumb:
+	@if test $(call cc-version) -lt 0404; then \
+		echo -n '*** Your GCC does not produce working '; \
+		echo 'binaries in THUMB mode.'; \
+		echo '*** Your board is configured for THUMB mode.'; \
+		false; \
+	fi
 #
 # Auto-generate the autoconf.mk file (which is included by all makefiles)
 #
@@ -740,7 +822,7 @@ clean:
 	@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map}
 	@rm -f $(ONENAND_BIN)
 	@rm -f $(obj)onenand_ipl/u-boot.lds
-	@rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.lds,u-boot-spl.map}
+	@rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.img,u-boot-spl.lds,u-boot-spl.map}
 	@rm -f $(obj)MLO
 	@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
 	@find $(OBJTREE) -type f \
diff --git a/README b/README
index 43074cf65f..67dc444bd4 100644
--- a/README
+++ b/README
@@ -432,6 +432,14 @@ The following options need to be configured:
 		Select high exception vectors of the ARM core, e.g., do not
 		clear the V bit of the c1 register of CP15.
 
+		CONFIG_SYS_THUMB_BUILD
+
+		Use this flag to build U-Boot using the Thumb instruction
+		set for ARM architectures. Thumb instruction set provides
+		better code density. For ARM architectures that support
+		Thumb2 this flag will result in Thumb2 code generated by
+		GCC.
+
 - Linux Kernel Interface:
 		CONFIG_CLOCKS_IN_MHZ
 
@@ -777,6 +785,8 @@ The following options need to be configured:
 		CONFIG_CMD_JFFS2	* JFFS2 Support
 		CONFIG_CMD_KGDB		* kgdb
 		CONFIG_CMD_LDRINFO	  ldrinfo (display Blackfin loader)
+		CONFIG_CMD_LINK_LOCAL	* link-local IP address auto-configuration
+					  (169.254.*.*)
 		CONFIG_CMD_LOADB	  loadb
 		CONFIG_CMD_LOADS	  loads
 		CONFIG_CMD_MD5SUM	  print md5 message digest
@@ -814,7 +824,7 @@ The following options need to be configured:
 		CONFIG_CMD_TIME		* run command and report execution time
 		CONFIG_CMD_USB		* USB support
 		CONFIG_CMD_CDP		* Cisco Discover Protocol support
-		CONFIG_CMD_FSL		* Microblaze FSL support
+		CONFIG_CMD_MFSL		* Microblaze FSL support
 
 
 		EXAMPLE: If you want all functions except of network
@@ -1584,10 +1594,17 @@ The following options need to be configured:
 		CONFIG_BOOTP_NTPSERVER
 		CONFIG_BOOTP_TIMEOFFSET
 		CONFIG_BOOTP_VENDOREX
+		CONFIG_BOOTP_MAY_FAIL
 
 		CONFIG_BOOTP_SERVERIP - TFTP server will be the serverip
 		environment variable, not the BOOTP server.
 
+		CONFIG_BOOTP_MAY_FAIL - If the DHCP server is not found
+		after the configured retry count, the call will fail
+		instead of starting over.  This can be used to fail over
+		to Link-local IP address configuration if the DHCP server
+		is not available.
+
 		CONFIG_BOOTP_DNS2 - If a DHCP client requests the DNS
 		serverip from a DHCP server, it is possible that more
 		than one DNS serverip is offered to the client.
@@ -1618,6 +1635,14 @@ The following options need to be configured:
 		the DHCP timeout and retry process takes a longer than
 		this delay.
 
+ - Link-local IP address negotiation:
+		Negotiate with other link-local clients on the local network
+		for an address that doesn't require explicit configuration.
+		This is especially useful if a DHCP server cannot be guaranteed
+		to exist in all environments that the device must operate.
+
+		See doc/README.link-local for more information.
+
  - CDP Options:
 		CONFIG_CDP_DEVICE_ID
 
@@ -3026,6 +3051,24 @@ to save the current settings.
 	  environment area within the total memory of your DataFlash placed
 	  at the specified address.
 
+- CONFIG_ENV_IS_IN_REMOTE:
+
+	Define this if you have a remote memory space which you
+	want to use for the local device's environment.
+
+	- CONFIG_ENV_ADDR:
+	- CONFIG_ENV_SIZE:
+
+	  These two #defines specify the address and size of the
+	  environment area within the remote memory space. The
+	  local device can get the environment from remote memory
+	  space by SRIO or other links.
+
+BE CAREFUL! For some special cases, the local device can not use
+"saveenv" command. For example, the local device will get the
+environment stored in a remote NOR flash by SRIO link, but it can
+not erase, write this NOR flash by SRIO interface.
+
 - CONFIG_ENV_IS_IN_NAND:
 
 	Define this if you have a NAND device which you want to use
@@ -3462,6 +3505,12 @@ within that device.
 	Specifies that QE/FMAN firmware is located on the primary SPI
 	device.  CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
 
+- CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+	Specifies that QE/FMAN firmware is located in the remote (master)
+	memory space.	CONFIG_SYS_FMAN_FW_ADDR is a virtual address which
+	can be mapped from slave TLB->slave LAW->slave SRIO outbound window
+	->master inbound window->master LAW->the ucode address in master's
+	NOR flash.
 
 Building the Software:
 ======================
diff --git a/android/Makefile b/android/Makefile
new file mode 100644
index 0000000000..fc5b79861a
--- /dev/null
+++ b/android/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2004-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)libandroid.o
+
+COBJS-y += android_boot.o
+
+COBJS	:= $(sort $(COBJS-y))
+SRCS	:= $(COBJS:.o=.c) $(XCOBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+CPPFLAGS += -I..
+
+all:	$(LIB)
+
+$(LIB): $(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/android/android_boot.c b/android/android_boot.c
new file mode 100644
index 0000000000..b3c1beaeee
--- /dev/null
+++ b/android/android_boot.c
@@ -0,0 +1,50 @@
+#include <common.h>
+#include <android/android_boot.h>
+#include <asm/mach-types.h>
+
+void creat_atags(unsigned taddr, const char *cmdline,unsigned raddr, unsigned rsize)
+{
+	unsigned n = 0;
+	unsigned *tags = (unsigned *)taddr;
+
+	//ATAG_CORE
+	tags[n++] = 2;
+	tags[n++] = 0x54410001;
+
+	if(rsize) {
+		//ATAG_INITRD2
+		tags[n++] = 4;
+		tags[n++] = 0x54420005;
+		tags[n++] = raddr;
+		tags[n++] = rsize;
+	}
+	if(cmdline && cmdline[0]) {
+		const char *src;
+		char *dst;
+		unsigned len = 0;
+
+		dst = (char*) (tags + n + 2);
+		src = cmdline;
+		while((*dst++ = *src++)) len++;
+
+		len++;
+		len = (len + 3) & (~3);
+
+		// ATAG_CMDLINE
+		 tags[n++] = 2 + (len / 4);
+		 tags[n++] = 0x54410009;
+
+		 n += (len / 4);
+	 }
+
+	// ATAG_NONE
+	tags[n++] = 0;
+	tags[n++] = 0;
+}
+
+void boot_linux(unsigned kaddr, unsigned taddr)
+{
+	void (*entry)(unsigned,unsigned,unsigned) = (void*) kaddr;
+
+	entry(0, machine_arch_type, taddr);
+}
diff --git a/arch/.gitignore b/arch/.gitignore
deleted file mode 100644
index a1fbe01d57..0000000000
--- a/arch/.gitignore
+++ /dev/null
@@ -1,2 +0,0 @@
-/*/include/asm/arch
-/*/include/asm/proc
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 3c5f987167..8a97e15d1e 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -21,38 +21,58 @@
 # MA 02111-1307 USA
 #
 
-CROSS_COMPILE ?= arm-linux-
+CROSS_COMPILE ?= arm-eabi-
 
 ifndef CONFIG_STANDALONE_LOAD_ADDR
 ifeq ($(SOC),omap3)
 CONFIG_STANDALONE_LOAD_ADDR = 0x80300000
 else
-CONFIG_STANDALONE_LOAD_ADDR = 0xc100000
+CONFIG_STANDALONE_LOAD_ADDR = 0x80008000
 endif
 endif
 
 PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__
 
-# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
-PF_CPPFLAGS_ARM := $(call cc-option,-marm,)
+# Choose between ARM/Thumb instruction sets
+ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
+PF_CPPFLAGS_ARM := $(call cc-option, -mthumb -mthumb-interwork,\
+			$(call cc-option,-marm,)\
+			$(call cc-option,-mno-thumb-interwork,)\
+		)
+else
+PF_CPPFLAGS_ARM := $(call cc-option,-marm,) \
+		$(call cc-option,-mno-thumb-interwork,)
+endif
 
+# Only test once
+ifneq ($(CONFIG_SPL_BUILD),y)
+ALL-$(CONFIG_SYS_THUMB_BUILD)	+= checkthumb
+endif
+ifeq ($(CONFIG_SPL_BUILD),y)
+ ifeq ($(CONFIG_SPL_THUMB_BUILD),y)
+PF_CPPFLAGS_ARM := $(call cc-option, -mthumb -mthumb-interwork,\
+			$(call cc-option,-marm,)\
+			$(call cc-option,-mno-thumb-interwork,)\
+		)
+ endif
+endif
 # Try if EABI is supported, else fall back to old API,
 # i. e. for example:
 # - with ELDK 4.2 (EABI supported), use:
-#	-mabi=aapcs-linux -mno-thumb-interwork
+#	-mabi=aapcs-linux
 # - with ELDK 4.1 (gcc 4.x, no EABI), use:
-#	-mabi=apcs-gnu -mno-thumb-interwork
+#	-mabi=apcs-gnu
 # - with ELDK 3.1 (gcc 3.x), use:
-#	-mapcs-32 -mno-thumb-interwork
+#	-mapcs-32
 PF_CPPFLAGS_ABI := $(call cc-option,\
-			-mabi=aapcs-linux -mno-thumb-interwork,\
-			$(call cc-option,\
-				-mapcs-32,\
+			-mabi=aapcs-linux,\
 				$(call cc-option,\
-					-mabi=apcs-gnu,\
-				)\
-			) $(call cc-option,-mno-thumb-interwork,)\
-		)
+					-mapcs-32,\
+					$(call cc-option,\
+						-mabi=apcs-gnu,\
+					)\
+			)\
+			)
 PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARM) $(PF_CPPFLAGS_ABI)
 
 # For EABI, make sure to provide raise()
diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk
index ffb2e6c3ea..6a3a1bb354 100644
--- a/arch/arm/cpu/arm926ejs/config.mk
+++ b/arch/arm/cpu/arm926ejs/config.mk
@@ -31,3 +31,9 @@ PLATFORM_CPPFLAGS += -march=armv5te
 # =========================================================================
 PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
 PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
+
+ifneq ($(CONFIG_IMX_CONFIG),)
+
+ALL-y	+= $(obj)u-boot.imx
+
+endif
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
new file mode 100644
index 0000000000..ae1f0a5c0c
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License
+# as published by the Free Software Foundation; either version 2
+# of the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA  02110-1301, USA.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB     = $(obj)lib$(SOC).o
+
+COBJS   = cpu.o clk.o devices.o timer.o
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS    := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:    $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
new file mode 100644
index 0000000000..6f26d626a7
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/io.h>
+
+static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
+
+unsigned int get_sys_clk_rate(void)
+{
+	if (readl(&clk->sysclk_ctrl) & CLK_SYSCLK_PLL397)
+		return RTC_CLK_FREQUENCY * 397;
+	else
+		return OSC_CLK_FREQUENCY;
+}
+
+unsigned int get_hclk_pll_rate(void)
+{
+	unsigned long long fin, fref, fcco, fout;
+	u32 val, m_div, n_div, p_div;
+
+	/*
+	 * Valid frequency ranges:
+	 *     1 * 10^6 <=  Fin <=  20 * 10^6
+	 *     1 * 10^6 <= Fref <=  27 * 10^6
+	 *   156 * 10^6 <= Fcco <= 320 * 10^6
+	 */
+
+	fref = fin = get_sys_clk_rate();
+	if (fin > 20000000ULL || fin < 1000000ULL)
+		return 0;
+
+	val = readl(&clk->hclkpll_ctrl);
+	m_div = ((val & CLK_HCLK_PLL_FEEDBACK_DIV_MASK) >> 1) + 1;
+	n_div = ((val & CLK_HCLK_PLL_PREDIV_MASK) >> 9) + 1;
+	if (val & CLK_HCLK_PLL_DIRECT)
+		p_div = 0;
+	else
+		p_div = ((val & CLK_HCLK_PLL_POSTDIV_MASK) >> 11) + 1;
+	p_div = 1 << p_div;
+
+	if (val & CLK_HCLK_PLL_BYPASS) {
+		do_div(fin, p_div);
+		return fin;
+	}
+
+	do_div(fref, n_div);
+	if (fref > 27000000ULL || fref < 1000000ULL)
+		return 0;
+
+	fout = fref * m_div;
+	if (val & CLK_HCLK_PLL_FEEDBACK) {
+		fcco = fout;
+		do_div(fout, p_div);
+	} else
+		fcco = fout * p_div;
+
+	if (fcco > 320000000ULL || fcco < 156000000ULL)
+		return 0;
+
+	return fout;
+}
+
+unsigned int get_hclk_clk_div(void)
+{
+	u32 val;
+
+	val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK;
+
+	return 1 << val;
+}
+
+unsigned int get_hclk_clk_rate(void)
+{
+	return get_hclk_pll_rate() / get_hclk_clk_div();
+}
+
+unsigned int get_periph_clk_div(void)
+{
+	u32 val;
+
+	val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_PERIPH_DIV_MASK;
+
+	return (val >> 2) + 1;
+}
+
+unsigned int get_periph_clk_rate(void)
+{
+	if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))
+		return get_sys_clk_rate();
+
+	return get_hclk_pll_rate() / get_periph_clk_div();
+}
+
+int get_serial_clock(void)
+{
+	return get_periph_clk_rate();
+}
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
new file mode 100644
index 0000000000..e29e130338
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/wdt.h>
+#include <asm/io.h>
+
+static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
+static struct wdt_regs  *wdt = (struct wdt_regs *)WDT_BASE;
+
+void reset_cpu(ulong addr)
+{
+	/* Enable watchdog clock */
+	setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
+
+	/* Reset pulse length is 13005 peripheral clock frames */
+	writel(13000, &wdt->pulse);
+
+	/* Force WDOG_RESET2 and RESOUT_N signal active */
+	writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2,
+	       &wdt->mctrl);
+
+	while (1)
+		/* NOP */;
+}
+
+#if defined(CONFIG_ARCH_CPU_INIT)
+int arch_cpu_init(void)
+{
+	/*
+	 * It might be necessary to flush data cache, if U-boot is loaded
+	 * from kickstart bootloader, e.g. from S1L loader
+	 */
+	flush_dcache_all();
+
+	return 0;
+}
+#else
+#error "You have to select CONFIG_ARCH_CPU_INIT"
+#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	printf("CPU:   NXP LPC32XX\n");
+	printf("CPU clock:        %uMHz\n", get_hclk_pll_rate() / 1000000);
+	printf("AHB bus clock:    %uMHz\n", get_hclk_clk_rate() / 1000000);
+	printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000);
+
+	return 0;
+}
+#endif
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
new file mode 100644
index 0000000000..9f305b5ba5
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/uart.h>
+#include <asm/io.h>
+
+static struct clk_pm_regs    *clk  = (struct clk_pm_regs *)CLK_PM_BASE;
+static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
+
+void lpc32xx_uart_init(unsigned int uart_id)
+{
+	if (uart_id < 1 || uart_id > 7)
+		return;
+
+	/* Disable loopback mode, if it is set by S1L bootloader */
+	clrbits_le32(&ctrl->loop,
+		     UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART));
+
+	if (uart_id < 3 || uart_id > 6)
+		return;
+
+	/* Enable UART system clock */
+	setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id));
+
+	/* Set UART into autoclock mode */
+	clrsetbits_le32(&ctrl->clkmode,
+			UART_CLKMODE_MASK(uart_id),
+			UART_CLKMODE_AUTO(uart_id));
+
+	/* Bypass pre-divider of UART clock */
+	writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
+	       &clk->u3clk + (uart_id - 3));
+}
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/timer.c b/arch/arm/cpu/arm926ejs/lpc32xx/timer.c
new file mode 100644
index 0000000000..1ce2358afd
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/timer.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/timer.h>
+#include <asm/io.h>
+
+static struct timer_regs  *timer0 = (struct timer_regs *)TIMER0_BASE;
+static struct timer_regs  *timer1 = (struct timer_regs *)TIMER1_BASE;
+static struct clk_pm_regs *clk    = (struct clk_pm_regs *)CLK_PM_BASE;
+
+static void lpc32xx_timer_clock(u32 bit, int enable)
+{
+	if (enable)
+		setbits_le32(&clk->timclk_ctrl1, bit);
+	else
+		clrbits_le32(&clk->timclk_ctrl1, bit);
+}
+
+static void lpc32xx_timer_reset(struct timer_regs *timer, u32 freq)
+{
+	writel(TIMER_TCR_COUNTER_RESET,   &timer->tcr);
+	writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr);
+	writel(0, &timer->tc);
+	writel(0, &timer->pr);
+
+	/* Count mode is every rising PCLK edge */
+	writel(TIMER_CTCR_MODE_TIMER, &timer->ctcr);
+
+	/* Set prescale counter value */
+	writel((get_periph_clk_rate() / freq) - 1, &timer->pr);
+}
+
+static void lpc32xx_timer_count(struct timer_regs *timer, int enable)
+{
+	if (enable)
+		writel(TIMER_TCR_COUNTER_ENABLE,  &timer->tcr);
+	else
+		writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr);
+}
+
+int timer_init(void)
+{
+	lpc32xx_timer_clock(CLK_TIMCLK_TIMER0, 1);
+	lpc32xx_timer_reset(timer0, CONFIG_SYS_HZ);
+	lpc32xx_timer_count(timer0, 1);
+
+	return 0;
+}
+
+ulong get_timer(ulong base)
+{
+	return readl(&timer0->tc) - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 1);
+	lpc32xx_timer_reset(timer1, CONFIG_SYS_HZ * 1000);
+	lpc32xx_timer_count(timer1, 1);
+
+	while (readl(&timer1->tc) < usec)
+		/* NOP */;
+
+	lpc32xx_timer_count(timer1, 0);
+	lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 0);
+}
+
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c
index 9cadb7c34c..8b07dae2b9 100644
--- a/arch/arm/cpu/arm926ejs/mx25/generic.c
+++ b/arch/arm/cpu/arm926ejs/mx25/generic.c
@@ -28,10 +28,15 @@
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/imx25-pinmux.h>
+#include <asm/arch/clock.h>
 #ifdef CONFIG_MXC_MMC
 #include <asm/arch/mxcmmc.h>
 #endif
 
+#ifdef CONFIG_FSL_ESDHC
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 /*
  *  get the system pll clock in Hz
  *
@@ -105,6 +110,20 @@ ulong imx_get_perclk(int clk)
 	return lldiv(fref, div);
 }
 
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+	if (clk >= MXC_CLK_NUM)
+		return -1;
+	switch (clk) {
+	case MXC_ARM_CLK:
+		return imx_get_armclk();
+	case MXC_FEC_CLK:
+		return imx_get_ahbclk();
+	default:
+		return imx_get_perclk(clk);
+	}
+}
+
 u32 get_cpu_rev(void)
 {
 	u32 srev;
@@ -182,6 +201,14 @@ int cpu_eth_init(bd_t *bis)
 #endif
 }
 
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC
+	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#endif
+	return 0;
+}
+
 /*
  * Initializes on-chip MMC controllers.
  * to override, implement board_mmc_init()
diff --git a/arch/arm/cpu/arm926ejs/mx28/Makefile b/arch/arm/cpu/arm926ejs/mx28/Makefile
index a2e3f771c2..674a3af1be 100644
--- a/arch/arm/cpu/arm926ejs/mx28/Makefile
+++ b/arch/arm/cpu/arm926ejs/mx28/Makefile
@@ -28,7 +28,7 @@ LIB	= $(obj)lib$(SOC).o
 COBJS	= clock.o mx28.o iomux.o timer.o
 
 ifdef	CONFIG_SPL_BUILD
-COBJS	+= spl_boot.o spl_mem_init.o spl_power_init.o
+COBJS	+= spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o
 endif
 
 SRCS	:= $(START:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c
index dc0338dfb5..a82ff2564b 100644
--- a/arch/arm/cpu/arm926ejs/mx28/mx28.c
+++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c
@@ -51,9 +51,16 @@ void reset_cpu(ulong ignored) __attribute__((noreturn));
 
 void reset_cpu(ulong ignored)
 {
-
 	struct mx28_rtc_regs *rtc_regs =
 		(struct mx28_rtc_regs *)MXS_RTC_BASE;
+	struct mx28_lcdif_regs *lcdif_regs =
+		(struct mx28_lcdif_regs *)MXS_LCDIF_BASE;
+
+	/*
+	 * Shut down the LCD controller as it interferes with BootROM boot mode
+	 * pads sampling.
+	 */
+	writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr);
 
 	/* Wait 1 uS before doing the actual watchdog reset */
 	writel(1, &rtc_regs->hw_rtc_watchdog);
@@ -185,8 +192,12 @@ int arch_cpu_init(void)
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
+	struct mx28_spl_data *data = (struct mx28_spl_data *)
+		((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf);
+
 	printf("Freescale i.MX28 family at %d MHz\n",
 			mxc_get_clock(MXC_ARM_CLK) / 1000000);
+	printf("BOOT:  %s\n", mx28_boot_modes[data->boot_mode_idx].mode);
 	return 0;
 }
 #endif
@@ -279,22 +290,16 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 
 int mx28_dram_init(void)
 {
-	struct mx28_digctl_regs *digctl_regs =
-		(struct mx28_digctl_regs *)MXS_DIGCTL_BASE;
-	uint32_t sz[2];
-
-	sz[0] = readl(&digctl_regs->hw_digctl_scratch0);
-	sz[1] = readl(&digctl_regs->hw_digctl_scratch1);
+	struct mx28_spl_data *data = (struct mx28_spl_data *)
+		((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf);
 
-	if (sz[0] != sz[1]) {
+	if (data->mem_dram_size == 0) {
 		printf("MX28:\n"
-			"Error, the RAM size in HW_DIGCTRL_SCRATCH0 and\n"
-			"HW_DIGCTRL_SCRATCH1 is not the same. Please\n"
-			"verify these two registers contain valid RAM size!\n");
+			"Error, the RAM size passed up from SPL is 0!\n");
 		hang();
 	}
 
-	gd->ram_size = sz[0];
+	gd->ram_size = data->mem_dram_size;
 	return 0;
 }
 
diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28_init.h b/arch/arm/cpu/arm926ejs/mx28/mx28_init.h
index 98d363199d..e3a4493fbd 100644
--- a/arch/arm/cpu/arm926ejs/mx28/mx28_init.h
+++ b/arch/arm/cpu/arm926ejs/mx28/mx28_init.h
@@ -37,5 +37,9 @@ static inline void mx28_power_wait_pswitch(void) { }
 #endif
 
 void mx28_mem_init(void);
+uint32_t mx28_mem_get_size(void);
+
+void mx28_lradc_init(void);
+void mx28_lradc_enable_batt_measurement(void);
 
 #endif	/* __M28_INIT_H__ */
diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_boot.c b/arch/arm/cpu/arm926ejs/mx28/spl_boot.c
index dfb8309e70..a6dfca3f51 100644
--- a/arch/arm/cpu/arm926ejs/mx28/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_boot.c
@@ -28,6 +28,8 @@
 #include <asm/io.h>
 #include <asm/arch/iomux-mx28.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
 
 #include "mx28_init.h"
 
@@ -46,12 +48,65 @@ void early_delay(int delay)
 		;
 }
 
+#define	MUX_CONFIG_BOOTMODE_PAD	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+const iomux_cfg_t iomux_boot[] = {
+	MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
+	MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
+	MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
+	MX28_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
+	MX28_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
+	MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
+};
+
+uint8_t mx28_get_bootmode_index(void)
+{
+	uint8_t bootmode = 0;
+	int i;
+	uint8_t masked;
+
+	/* Setup IOMUX of bootmode pads to GPIO */
+	mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot));
+
+	/* Setup bootmode pins as GPIO input */
+	gpio_direction_input(MX28_PAD_LCD_D00__GPIO_1_0);
+	gpio_direction_input(MX28_PAD_LCD_D01__GPIO_1_1);
+	gpio_direction_input(MX28_PAD_LCD_D02__GPIO_1_2);
+	gpio_direction_input(MX28_PAD_LCD_D03__GPIO_1_3);
+	gpio_direction_input(MX28_PAD_LCD_D04__GPIO_1_4);
+	gpio_direction_input(MX28_PAD_LCD_D05__GPIO_1_5);
+
+	/* Read bootmode pads */
+	bootmode |= (gpio_get_value(MX28_PAD_LCD_D00__GPIO_1_0) ? 1 : 0) << 0;
+	bootmode |= (gpio_get_value(MX28_PAD_LCD_D01__GPIO_1_1) ? 1 : 0) << 1;
+	bootmode |= (gpio_get_value(MX28_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2;
+	bootmode |= (gpio_get_value(MX28_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3;
+	bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4;
+	bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
+
+	for (i = 0; i < ARRAY_SIZE(mx28_boot_modes); i++) {
+		masked = bootmode & mx28_boot_modes[i].boot_mask;
+		if (masked == mx28_boot_modes[i].boot_pads)
+			break;
+	}
+
+	return i;
+}
+
 void mx28_common_spl_init(const iomux_cfg_t *iomux_setup,
 			const unsigned int iomux_size)
 {
+	struct mx28_spl_data *data = (struct mx28_spl_data *)
+		((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf);
+	uint8_t bootmode = mx28_get_bootmode_index();
+
 	mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size);
 	mx28_power_init();
+
 	mx28_mem_init();
+	data->mem_dram_size = mx28_mem_get_size();
+
+	data->boot_mode_idx = bootmode;
+
 	mx28_power_wait_pswitch();
 }
 
@@ -68,8 +123,10 @@ inline void board_init_r(gd_t *id, ulong dest_addr)
 		;
 }
 
+#ifndef CONFIG_SPL_SERIAL_SUPPORT
 void serial_putc(const char c) {}
 void serial_puts(const char *s) {}
+#endif
 void hang(void) __attribute__ ((noreturn));
 void hang(void)
 {
diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_lradc_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_lradc_init.c
new file mode 100644
index 0000000000..88a603c11d
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_lradc_init.c
@@ -0,0 +1,86 @@
+/*
+ * Freescale i.MX28 Battery measurement init
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+
+#include "mx28_init.h"
+
+void mx28_lradc_init(void)
+{
+	struct mx28_lradc_regs *regs = (struct mx28_lradc_regs *)MXS_LRADC_BASE;
+
+	writel(LRADC_CTRL0_SFTRST, &regs->hw_lradc_ctrl0_clr);
+	writel(LRADC_CTRL0_CLKGATE, &regs->hw_lradc_ctrl0_clr);
+	writel(LRADC_CTRL0_ONCHIP_GROUNDREF, &regs->hw_lradc_ctrl0_clr);
+
+	clrsetbits_le32(&regs->hw_lradc_ctrl3,
+			LRADC_CTRL3_CYCLE_TIME_MASK,
+			LRADC_CTRL3_CYCLE_TIME_6MHZ);
+
+	clrsetbits_le32(&regs->hw_lradc_ctrl4,
+			LRADC_CTRL4_LRADC7SELECT_MASK |
+			LRADC_CTRL4_LRADC6SELECT_MASK,
+			LRADC_CTRL4_LRADC7SELECT_CHANNEL7 |
+			LRADC_CTRL4_LRADC6SELECT_CHANNEL10);
+}
+
+void mx28_lradc_enable_batt_measurement(void)
+{
+	struct mx28_lradc_regs *regs = (struct mx28_lradc_regs *)MXS_LRADC_BASE;
+
+	/* Check if the channel is present at all. */
+	if (!(readl(&regs->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT))
+		return;
+
+	writel(LRADC_CTRL1_LRADC7_IRQ_EN, &regs->hw_lradc_ctrl1_clr);
+	writel(LRADC_CTRL1_LRADC7_IRQ, &regs->hw_lradc_ctrl1_clr);
+
+	clrsetbits_le32(&regs->hw_lradc_conversion,
+			LRADC_CONVERSION_SCALE_FACTOR_MASK,
+			LRADC_CONVERSION_SCALE_FACTOR_LI_ION);
+	writel(LRADC_CONVERSION_AUTOMATIC, &regs->hw_lradc_conversion_set);
+
+	/* Configure the channel. */
+	writel((1 << 7) << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
+		&regs->hw_lradc_ctrl2_clr);
+	writel(0xffffffff, &regs->hw_lradc_ch7_clr);
+	clrbits_le32(&regs->hw_lradc_ch7, LRADC_CH_NUM_SAMPLES_MASK);
+	writel(LRADC_CH_ACCUMULATE, &regs->hw_lradc_ch7_clr);
+
+	/* Schedule the channel. */
+	writel(1 << 7, &regs->hw_lradc_ctrl0_set);
+
+	/* Start the channel sampling. */
+	writel(((1 << 7) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) |
+		((1 << 3) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) |
+		100, &regs->hw_lradc_delay3);
+
+	writel(0xffffffff, &regs->hw_lradc_ch7_clr);
+
+	writel(LRADC_DELAY_KICK, &regs->hw_lradc_delay3_set);
+}
diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
index 911bbefc06..9fa5d29e6c 100644
--- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
@@ -39,7 +39,7 @@ uint32_t dram_vals[] = {
 	0x00000000, 0x00000100, 0x00000000, 0x00000000,
 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
 	0x00000000, 0x00000000, 0x00010101, 0x01010101,
-	0x000f0f01, 0x0f02010a, 0x00000000, 0x00010101,
+	0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101,
 	0x00000100, 0x00000100, 0x00000000, 0x00000002,
 	0x01010000, 0x05060302, 0x06005003, 0x0a0000c8,
 	0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612,
@@ -149,6 +149,8 @@ void mx28_mem_setup_cpu_and_hbus(void)
 	/* Disable CPU bypass */
 	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
 		&clkctrl_regs->hw_clkctrl_clkseq_clr);
+
+	early_delay(15000);
 }
 
 void mx28_mem_setup_vdda(void)
@@ -173,10 +175,8 @@ void mx28_mem_setup_vddd(void)
 		&power_regs->hw_power_vdddctrl);
 }
 
-void mx28_mem_get_size(void)
+uint32_t mx28_mem_get_size(void)
 {
-	struct mx28_digctl_regs *digctl_regs =
-		(struct mx28_digctl_regs *)MXS_DIGCTL_BASE;
 	uint32_t sz, da;
 	uint32_t *vt = (uint32_t *)0x20;
 	/* The following is "subs pc, r14, #4", used as return from DABT. */
@@ -187,11 +187,11 @@ void mx28_mem_get_size(void)
 	vt[4] = data_abort_memdetect_handler;
 
 	sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
-	writel(sz, &digctl_regs->hw_digctl_scratch0);
-	writel(sz, &digctl_regs->hw_digctl_scratch1);
 
 	/* Restore the old DABT handler. */
 	vt[4] = da;
+
+	return sz;
 }
 
 void mx28_mem_init(void)
@@ -239,6 +239,4 @@ void mx28_mem_init(void)
 	early_delay(10000);
 
 	mx28_mem_setup_cpu_and_hbus();
-
-	mx28_mem_get_size();
 }
diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
index aa4117d3a2..4b09b0c3ba 100644
--- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
@@ -45,11 +45,11 @@ void mx28_power_clock2pll(void)
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
-	writel(CLKCTRL_PLL0CTRL0_POWER,
-		&clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
+	setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
+			CLKCTRL_PLL0CTRL0_POWER);
 	early_delay(100);
-	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
-		&clkctrl_regs->hw_clkctrl_clkseq_clr);
+	setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
+			CLKCTRL_CLKSEQ_BYPASS_CPU);
 }
 
 void mx28_power_clear_auto_restart(void)
@@ -104,6 +104,62 @@ void mx28_power_set_linreg(void)
 			POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
 }
 
+int mx28_get_batt_volt(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+	uint32_t volt = readl(&power_regs->hw_power_battmonitor);
+	volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
+	volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
+	volt *= 8;
+	return volt;
+}
+
+int mx28_is_batt_ready(void)
+{
+	return (mx28_get_batt_volt() >= 3600);
+}
+
+int mx28_is_batt_good(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+	uint32_t volt = mx28_get_batt_volt();
+
+	if ((volt >= 2400) && (volt <= 4300))
+		return 1;
+
+	clrsetbits_le32(&power_regs->hw_power_5vctrl,
+		POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
+		0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+	writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+		&power_regs->hw_power_5vctrl_clr);
+
+	clrsetbits_le32(&power_regs->hw_power_charge,
+		POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
+		POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
+
+	writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
+	writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+		&power_regs->hw_power_5vctrl_clr);
+
+	early_delay(500000);
+
+	volt = mx28_get_batt_volt();
+
+	if (volt >= 3500)
+		return 0;
+
+	if (volt >= 2400)
+		return 1;
+
+	writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
+		&power_regs->hw_power_charge_clr);
+	writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
+
+	return 0;
+}
+
 void mx28_power_setup_5v_detect(void)
 {
 	struct mx28_power_regs *power_regs =
@@ -399,9 +455,14 @@ void mx28_power_enable_4p2(void)
 	mx28_power_init_4p2_regulator();
 
 	/* Shutdown battery (none present) */
-	clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
-	writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
-	writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
+	if (!mx28_is_batt_ready()) {
+		clrbits_le32(&power_regs->hw_power_dcdc4p2,
+				POWER_DCDC4P2_BO_MASK);
+		writel(POWER_CTRL_DCDC4P2_BO_IRQ,
+				&power_regs->hw_power_ctrl_clr);
+		writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
+				&power_regs->hw_power_ctrl_clr);
+	}
 
 	mx28_power_init_dcdc_4p2_source();
 
@@ -459,6 +520,50 @@ void mx28_powerdown(void)
 		&power_regs->hw_power_reset);
 }
 
+void mx28_batt_boot(void)
+{
+	struct mx28_power_regs *power_regs =
+		(struct mx28_power_regs *)MXS_POWER_BASE;
+
+	clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
+	clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
+
+	clrbits_le32(&power_regs->hw_power_dcdc4p2,
+			POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
+	writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
+
+	/* 5V to battery handoff. */
+	setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+	early_delay(30);
+	clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+
+	writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
+
+	clrsetbits_le32(&power_regs->hw_power_minpwr,
+			POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
+
+	mx28_power_set_linreg();
+
+	clrbits_le32(&power_regs->hw_power_vdddctrl,
+		POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
+
+	clrbits_le32(&power_regs->hw_power_vddactrl,
+		POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
+
+	clrbits_le32(&power_regs->hw_power_vddioctrl,
+		POWER_VDDIOCTRL_DISABLE_FET);
+
+	setbits_le32(&power_regs->hw_power_5vctrl,
+		POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
+
+	setbits_le32(&power_regs->hw_power_5vctrl,
+		POWER_5VCTRL_ENABLE_DCDC);
+
+	clrsetbits_le32(&power_regs->hw_power_5vctrl,
+		POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
+		0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+}
+
 void mx28_handle_5v_conflict(void)
 {
 	struct mx28_power_regs *power_regs =
@@ -483,23 +588,12 @@ void mx28_handle_5v_conflict(void)
 			mx28_powerdown();
 			break;
 		}
-	}
-}
 
-int mx28_get_batt_volt(void)
-{
-	struct mx28_power_regs *power_regs =
-		(struct mx28_power_regs *)MXS_POWER_BASE;
-	uint32_t volt = readl(&power_regs->hw_power_battmonitor);
-	volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
-	volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
-	volt *= 8;
-	return volt;
-}
-
-int mx28_is_batt_ready(void)
-{
-	return (mx28_get_batt_volt() >= 3600);
+		if (tmp & POWER_STS_PSWITCH_MASK) {
+			mx28_batt_boot();
+			break;
+		}
+	}
 }
 
 void mx28_5v_boot(void)
@@ -553,62 +647,44 @@ void mx28_switch_vddd_to_dcdc_source(void)
 		POWER_VDDDCTRL_DISABLE_STEPPING);
 }
 
-int mx28_is_batt_good(void)
+void mx28_power_configure_power_source(void)
 {
+	int batt_ready, batt_good;
 	struct mx28_power_regs *power_regs =
 		(struct mx28_power_regs *)MXS_POWER_BASE;
-	uint32_t volt;
-
-	volt = readl(&power_regs->hw_power_battmonitor);
-	volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
-	volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
-	volt *= 8;
+	struct mx28_lradc_regs *lradc_regs =
+		(struct mx28_lradc_regs *)MXS_LRADC_BASE;
 
-	if ((volt >= 2400) && (volt <= 4300))
-		return 1;
-
-	clrsetbits_le32(&power_regs->hw_power_5vctrl,
-		POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
-		0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
-	writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
-		&power_regs->hw_power_5vctrl_clr);
-
-	clrsetbits_le32(&power_regs->hw_power_charge,
-		POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
-		POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
-
-	writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
-	writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
-		&power_regs->hw_power_5vctrl_clr);
-
-	early_delay(500000);
-
-	volt = readl(&power_regs->hw_power_battmonitor);
-	volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
-	volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
-	volt *= 8;
-
-	if (volt >= 3500)
-		return 0;
-
-	if (volt >= 2400)
-		return 1;
-
-	writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
-		&power_regs->hw_power_charge_clr);
-	writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
+	mx28_src_power_init();
 
-	return 0;
-}
+	batt_ready = mx28_is_batt_ready();
 
-void mx28_power_configure_power_source(void)
-{
-	mx28_src_power_init();
+	if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+		batt_good = mx28_is_batt_good();
+		if (batt_ready) {
+			/* 5V source detected, good battery detected. */
+			mx28_batt_boot();
+		} else {
+			if (batt_good) {
+				/* 5V source detected, low battery detceted. */
+			} else {
+				/* 5V source detected, bad battery detected. */
+				writel(LRADC_CONVERSION_AUTOMATIC,
+					&lradc_regs->hw_lradc_conversion_clr);
+				clrbits_le32(&power_regs->hw_power_battmonitor,
+					POWER_BATTMONITOR_BATT_VAL_MASK);
+			}
+			mx28_5v_boot();
+		}
+	} else {
+		/* 5V not detected, booting from battery. */
+		mx28_batt_boot();
+	}
 
-	mx28_5v_boot();
 	mx28_power_clock2pll();
 
 	mx28_init_batt_bo();
+
 	mx28_switch_vddd_to_dcdc_source();
 }
 
@@ -883,6 +959,13 @@ void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
 			new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
 }
 
+void mx28_setup_batt_detect(void)
+{
+	mx28_lradc_init();
+	mx28_lradc_enable_batt_measurement();
+	early_delay(10);
+}
+
 void mx28_power_init(void)
 {
 	struct mx28_power_regs *power_regs =
@@ -892,6 +975,9 @@ void mx28_power_init(void)
 	mx28_power_clear_auto_restart();
 	mx28_power_set_linreg();
 	mx28_power_setup_5v_detect();
+
+	mx28_setup_batt_detect();
+
 	mx28_power_configure_power_source();
 	mx28_enable_output_rail_protection();
 
diff --git a/arch/arm/cpu/arm926ejs/rda/Makefile b/arch/arm/cpu/arm926ejs/rda/Makefile
new file mode 100644
index 0000000000..a8ebda3a72
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/rda/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS-y	+= timer.o serial.o ifc.o cpu.o
+
+ifdef CONFIG_SPL_BUILD
+COBJS-y	+= spl.o
+endif
+
+SOBJS	= reset.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS	+= lowlevel_init.o
+endif
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/rda/config.mk b/arch/arm/cpu/arm926ejs/rda/config.mk
new file mode 100644
index 0000000000..565adda11d
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/rda/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
+
+PLATFORM_CPPFLAGS += -march=armv5te
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# =========================================================================
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/arch/arm/cpu/arm926ejs/rda/cpu.c b/arch/arm/cpu/arm926ejs/rda/cpu.c
new file mode 100644
index 0000000000..ae7a18ed7c
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/rda/cpu.c
@@ -0,0 +1,12 @@
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+	icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+	dcache_enable();
+#endif
+}
diff --git a/arch/arm/cpu/arm926ejs/rda/ifc.c b/arch/arm/cpu/arm926ejs/rda/ifc.c
new file mode 100644
index 0000000000..cdda6935ea
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/rda/ifc.c
@@ -0,0 +1,171 @@
+#include "common.h"
+#include <errno.h>
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/reg_ifc.h>
+#include <asm/arch/ifc.h>
+
+#ifdef DEBUG
+#include <assert.h>
+#else
+#define assert(...)
+#endif 
+
+#define HAL_TRACE(...)
+
+HAL_IFC_REQUEST_ID_T g_halModuleIfcChannelOwner[SYS_IFC_STD_CHAN_NB];
+
+void hal_IfcOpen(void)
+{
+    u8 channel;
+
+    // Initialize the channel table with unknown requests.
+    for (channel = 0; channel < SYS_IFC_STD_CHAN_NB; channel++)
+    {
+        g_halModuleIfcChannelOwner[channel] = HAL_IFC_NO_REQWEST;
+    }
+}
+
+HAL_IFC_REQUEST_ID_T hal_IfcGetOwner(u8 channel)
+{
+    // Here, we consider the transfer as previously finished.
+    if (channel == HAL_UNKNOWN_CHANNEL) return HAL_IFC_NO_REQWEST;
+
+    // Channel number too big.
+    assert(channel < SYS_IFC_STD_CHAN_NB, channel);
+
+    return g_halModuleIfcChannelOwner[channel];
+}
+
+void hal_IfcChannelRelease(HAL_IFC_REQUEST_ID_T requestId, u8 channel)
+{
+    //u32 status;
+
+    // Here, we consider the transfer as previously finished.
+    if (channel == HAL_UNKNOWN_CHANNEL) return;
+
+    // Channel number too big.
+    assert(channel < SYS_IFC_STD_CHAN_NB, channel);
+
+    //status = hal_SysEnterCriticalSection();
+    if (g_halModuleIfcChannelOwner[channel] == requestId)
+    {
+        // disable this channel
+        hwp_sysIfc->std_ch[channel].control = (SYS_IFC_REQ_SRC(requestId)
+                                            | SYS_IFC_CH_RD_HW_EXCH
+                                            | SYS_IFC_DISABLE);
+        // read the status of this channel
+        if (hwp_sysIfc->std_ch[channel].status & SYS_IFC_ENABLE)
+        {
+            HAL_TRACE(_HAL | TSTDOUT,0," Strange, the released channel not disabled yet");
+        }
+        // Write the TC to 0 for next time the channel is re-enabled
+        hwp_sysIfc->std_ch[channel].tc =  0;
+    }
+    //hal_SysExitCriticalSection(status);
+}
+
+void hal_IfcChannelFlush(HAL_IFC_REQUEST_ID_T requestId, u8 channel)
+{
+    //u32 status;
+
+    // Here, we consider the transfer as previously finished.
+    if (channel == HAL_UNKNOWN_CHANNEL) return;
+
+    // Channel number too big.
+    assert(channel < SYS_IFC_STD_CHAN_NB, channel);
+
+    // Check that the channel is really owned by the peripheral
+    // which is doing the request, it could have been release
+    // automatically or by an IRQ handler.
+    //status = hal_SysEnterCriticalSection();
+    if (g_halModuleIfcChannelOwner[channel] == requestId)
+    {
+        // If fifo not empty, flush it.
+        if ( !(hwp_sysIfc->std_ch[channel].status & SYS_IFC_FIFO_EMPTY) )
+        {
+            hwp_sysIfc->std_ch[channel].control = 
+                hwp_sysIfc->std_ch[channel].control | SYS_IFC_FLUSH;
+        }
+    }
+    //hal_SysExitCriticalSection(status);
+}
+
+BOOL hal_IfcChannelIsFifoEmpty(HAL_IFC_REQUEST_ID_T requestId, u8 channel)
+{
+    //u32 status;
+    BOOL fifoIsEmpty = TRUE;
+    
+    // Here, we consider the transfer as previously finished.
+    if (channel == HAL_UNKNOWN_CHANNEL) return fifoIsEmpty;
+
+    // Channel number too big.
+    assert(channel < SYS_IFC_STD_CHAN_NB, channel);
+
+    // Check that the channel is really owned by the peripheral
+    // which is doing the request, it could have been release
+    // automatically or by an IRQ handler.
+    //status = hal_SysEnterCriticalSection();
+    if (g_halModuleIfcChannelOwner[channel] == requestId)
+    {
+        fifoIsEmpty =
+            (FALSE != (hwp_sysIfc->std_ch[channel].status & SYS_IFC_FIFO_EMPTY));
+    }
+    //hal_SysExitCriticalSection(status);
+
+    return fifoIsEmpty;
+}
+
+u8 hal_IfcTransferStart(HAL_IFC_REQUEST_ID_T requestId, u8* memStartAddr, u32 xferSize, HAL_IFC_MODE_T ifcMode)
+{
+    //u32 status = hal_SysEnterCriticalSection();
+    u8 channel;
+    u8 i;
+
+    // Check buffer alignment depending on the mode
+    if (ifcMode != HAL_IFC_SIZE_8_MODE_MANUAL && ifcMode != HAL_IFC_SIZE_8_MODE_AUTO)
+    {
+        // Then ifcMode == HAL_IFC_SIZE_32, check word alignment
+        assert(((u32)memStartAddr%4) == 0,
+            "HAL IFC: 32 bits transfer misaligned 0x@%08X", memStartAddr);
+    }
+    else
+    {
+        // ifcMode == HAL_IFC_SIZE_8, nothing to check
+    }
+
+    // Check the requested id is not currently already used.
+    for (i = 0; i < SYS_IFC_STD_CHAN_NB ; i++)
+    {
+        if (GET_BITFIELD(hwp_sysIfc->std_ch[i].control, SYS_IFC_REQ_SRC) == requestId)
+        {
+            // This channel is or was used for the requestId request.
+            // Check it is still in use.
+            assert((hwp_sysIfc->std_ch[i].status & SYS_IFC_ENABLE) == 0,
+                    "HAL: Attempt to use the IFC to deal with a %d"
+                    " request still active on channel %d", requestId, i);
+        }
+    }
+
+    channel = SYS_IFC_CH_TO_USE(hwp_sysIfc->get_ch) ;
+
+    if (channel >= SYS_IFC_STD_CHAN_NB)
+    {
+        serial_puts("HAL_UNKNOWN_CHANNEL\n");
+        //hal_SysExitCriticalSection(status);
+        return HAL_UNKNOWN_CHANNEL;
+    }
+
+    g_halModuleIfcChannelOwner[channel]     = requestId;
+    hwp_sysIfc->std_ch[channel].start_addr  =  (u32) memStartAddr;
+    hwp_sysIfc->std_ch[channel].tc          =  xferSize;
+    hwp_sysIfc->std_ch[channel].control     = (SYS_IFC_REQ_SRC(requestId) 
+                                            | ifcMode
+                                            | SYS_IFC_CH_RD_HW_EXCH
+                                            | SYS_IFC_ENABLE);
+
+    //hal_SysExitCriticalSection(status);
+    return channel;
+}
+
diff --git a/arch/arm/cpu/arm926ejs/rda/reset.S b/arch/arm/cpu/arm926ejs/rda/reset.S
new file mode 100644
index 0000000000..51748160ae
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/rda/reset.S
@@ -0,0 +1,32 @@
+/*
+ * Processor reset using WDT for TI TMS320DM644x SoC.
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * -----------------------------------------------------
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+.globl reset_cpu
+reset_cpu:
+	nop
+	nop
+	nop
+	nop
+reset_cpu_loop:
+	b	reset_cpu_loop
+
diff --git a/arch/arm/cpu/arm926ejs/rda/serial.c b/arch/arm/cpu/arm926ejs/rda/serial.c
new file mode 100644
index 0000000000..f7c1d2d244
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/rda/serial.c
@@ -0,0 +1,132 @@
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+#include <asm/arch/reg_sysctrl.h>
+#include <asm/arch/reg_uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void _serial_set_baudrate(int rate)
+{
+    hwp_sysCtrlAp->Cfg_Clk_Uart[2] = 0x36;        // 115200 @ 26MHz
+    //hwp_sysCtrlAp->Cfg_Clk_Uart[2] = 0x05;        // 921600 @ 26MHz
+}
+
+void _serial_enable_rtscts(void)
+{
+     hwp_uart->ctrl |= UART_AUTO_FLOW_CONTROL;
+}
+
+void _serial_disable_rtscts(void)
+{
+     hwp_uart->ctrl &= ~UART_AUTO_FLOW_CONTROL;
+}
+
+void _serial_init(void)
+{
+    _serial_set_baudrate(CONFIG_BAUDRATE);
+    hwp_uart->triggers            = UART_AFC_LEVEL(1); //7 ?
+
+    hwp_uart->ctrl                = UART_ENABLE | UART_DATA_BITS_8_BITS |
+        UART_TX_STOP_BITS_1_BIT | UART_PARITY_ENABLE_NO;
+
+    /* Allow reception */
+    hwp_uart->CMD_Set             = UART_RTS;
+}
+
+void _serial_deinit(void)
+{
+    hwp_uart->ctrl    = 0;
+    hwp_uart->CMD_Clr = UART_RTS;
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+int _serial_tstc(const int port)
+{
+    return (GET_BITFIELD(hwp_uart->status, UART_RX_FIFO_LEVEL));
+}
+
+int _serial_getc(const int port)
+{
+    /* wait for character to arrive */ ;
+    while (!(GET_BITFIELD(hwp_uart->status, UART_RX_FIFO_LEVEL)))
+        ;
+
+    return (hwp_uart->rxtx_buffer & 0xff);
+}
+
+void _serial_putc_hw(const char c, const int port)
+{
+    // Place in the TX Fifo ?
+    while (!(GET_BITFIELD(hwp_uart->status, UART_TX_FIFO_SPACE)))
+        ;
+    hwp_uart->rxtx_buffer = (u32)c;
+}
+
+void _serial_putc(const char c, const int port)
+{
+    if (c == '\n') {
+        _serial_putc_hw('\r', 0); 
+    }
+    _serial_putc_hw(c, 0);
+}
+
+void _serial_puts(const char *s, const int port)
+{
+    while (*s) {
+        _serial_putc(*s++, 0);
+    }
+}
+
+static int hwflow = 0; /* turned off by default */
+int hwflow_onoff(int on)
+{
+	switch(on) {
+	case 0:
+	default:
+		break; /* return current */
+	case 1:
+		hwflow = 1;
+		_serial_enable_rtscts(); /* turn on */
+		break;
+	case -1:
+		hwflow = 0;
+		_serial_disable_rtscts(); /* turn off */
+		break;
+	}
+	return hwflow;
+}
+
+int serial_init(void)
+{
+    //_serial_init(); // already init in boot_test
+    return 0;
+}
+
+int serial_getc(void)
+{
+    return _serial_getc(0);
+}
+
+int serial_tstc(void)
+{
+    return _serial_tstc(0);
+}
+
+void serial_putc(const char c)
+{
+    _serial_putc(c, 0);
+}
+
+void serial_puts(const char *s)
+{
+    _serial_puts(s, 0);
+}
+
+void serial_setbrg (void)
+{
+}
+
diff --git a/arch/arm/cpu/arm926ejs/rda/spl.c b/arch/arm/cpu/arm926ejs/rda/spl.c
new file mode 100644
index 0000000000..5111638288
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/rda/spl.c
@@ -0,0 +1,74 @@
+#include <common.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <nand.h>
+#include <malloc.h>
+
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+
+DECLARE_GLOBAL_DATA_PTR;
+/* Define global data structure pointer to it*/
+static gd_t gdata __attribute__ ((section(".data")));
+static bd_t bdata __attribute__ ((section(".data")));
+
+#else
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
+
+void putc(char c)
+{
+}
+
+#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
+
+inline void hang(void)
+{
+	puts("### ERROR ### Please RESET the board ###\n");
+	for (;;)
+		;
+}
+
+void board_init_f(ulong dummy)
+{
+	relocate_code(CONFIG_SPL_STACK, NULL, CONFIG_SPL_TEXT_BASE);
+}
+
+void board_init_r(gd_t *id, ulong dummy)
+{
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+	gd = &gdata;
+	gd->bd = &bdata;
+	gd->flags |= GD_FLG_RELOC;
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init();          /* serial communications setup */
+	gd->have_console = 1;
+#endif
+	puts("board_init_r\n");
+	while(1)
+		;
+#if 0
+#ifdef CONFIG_SPL_NAND_LOAD
+	nand_init();
+	puts("Nand boot...\n");
+	nand_boot();
+#endif
+#ifdef CONFIG_SPL_SPI_LOAD
+	mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN,
+			CONFIG_SYS_MALLOC_LEN);
+
+	gd = &gdata;
+	gd->bd = &bdata;
+	gd->flags |= GD_FLG_RELOC;
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init();          /* serial communications setup */
+	gd->have_console = 1;
+
+	puts("SPI boot...\n");
+	spi_boot();
+#endif
+#endif
+}
diff --git a/arch/arm/cpu/arm926ejs/rda/timer.c b/arch/arm/cpu/arm926ejs/rda/timer.c
new file mode 100644
index 0000000000..a54081b7b2
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/rda/timer.c
@@ -0,0 +1,93 @@
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+typedef volatile struct
+{
+    REG32                          OSTimer_Ctrl;                 //0x00000000
+    REG32                          OSTimer_CurVal;               //0x00000004
+    REG32                          WDTimer_Ctrl;                 //0x00000008
+    REG32                          WDTimer_LoadVal;              //0x0000000C
+    REG32                          HWTimer_Ctrl;                 //0x00000010
+    REG32                          HWTimer_CurVal;               //0x00000014
+    REG32                          Timer_Irq_Mask_Set;           //0x00000018
+    REG32                          Timer_Irq_Mask_Clr;           //0x0000001C
+    REG32                          Timer_Irq_Clr;                //0x00000020
+    REG32                          Timer_Irq_Cause;              //0x00000024
+} HWP_TIMER_T;
+
+#define hwp_timer                   ((HWP_TIMER_T*)(RDA_TIMER_BASE))
+
+int timer_init(void)
+{
+	gd->timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
+	gd->timer_reset_value = 0;
+
+	/* We are using timer34 in unchained 32-bit mode, full speed */
+	return(0);
+}
+
+void reset_timer(void)
+{
+	gd->timer_reset_value = get_ticks();
+}
+
+/*
+ * Get the current 64 bit timer tick count
+ */
+unsigned long long get_ticks(void)
+{
+	unsigned long now = hwp_timer->HWTimer_CurVal;
+
+	/* increment tbu if tbl has rolled over */
+	if (now < gd->tbl)
+		gd->tbu++;
+	gd->tbl = now;
+
+	return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
+}
+
+ulong get_timer(ulong base)
+{
+	unsigned long long timer_diff;
+
+	timer_diff = get_ticks() - gd->timer_reset_value;
+
+	return (timer_diff / (gd->timer_rate_hz / CONFIG_SYS_HZ)) - base;
+}
+
+#pragma GCC push_options
+#pragma GCC optimize ("O0")
+
+void __udelay(unsigned long usec)
+{
+#if 0 /* our timer is 16kHz, can NOT support udelay */
+	unsigned long long endtime;
+
+	endtime = ((unsigned long long)usec * gd->timer_rate_hz) / 1000000UL;
+	endtime += get_ticks();
+
+	while (get_ticks() < endtime)
+		;
+#else /* use loop instead */
+#define USEC_LOOP (1)
+	int i, j;
+	for (i=0;i<(usec);i++)
+		for (j=0;j<USEC_LOOP;j++)
+			;
+#endif
+}
+
+#pragma GCC pop_options
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index d64ae6936c..6b7a494d7c 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -105,7 +105,7 @@ void init_timer(void)
 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
-	return omap_mmc_init(0);
+	return omap_mmc_init(0, 0, 0);
 }
 #endif
 
diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk
index f532d62e57..5407cb68a8 100644
--- a/arch/arm/cpu/armv7/config.mk
+++ b/arch/arm/cpu/armv7/config.mk
@@ -22,8 +22,11 @@
 #
 PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
-# Make ARMv5 to allow more compilers to work, even though its v7a.
-PLATFORM_CPPFLAGS += -march=armv5
+# If armv7-a is not supported by GCC fall-back to armv5, which is
+# supported by more tool-chains
+PF_CPPFLAGS_ARMV7 := $(call cc-option, -march=armv7-a, -march=armv5)
+PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV7)
+
 # =========================================================================
 #
 # Supply options according to compiler version
diff --git a/arch/arm/cpu/armv7/exynos/Makefile b/arch/arm/cpu/armv7/exynos/Makefile
index 124c38018c..90ec2bd404 100644
--- a/arch/arm/cpu/armv7/exynos/Makefile
+++ b/arch/arm/cpu/armv7/exynos/Makefile
@@ -22,7 +22,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).o
 
-COBJS	+= clock.o soc.o
+COBJS	+= clock.o power.o soc.o system.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 2f7048b6a3..330bd75da9 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -414,6 +414,170 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
 	writel(val, addr);
 }
 
+/* get_lcd_clk: return lcd clock frequency */
+static unsigned long exynos4_get_lcd_clk(void)
+{
+	struct exynos4_clock *clk =
+		(struct exynos4_clock *)samsung_get_base_clock();
+	unsigned long pclk, sclk;
+	unsigned int sel;
+	unsigned int ratio;
+
+	/*
+	 * CLK_SRC_LCD0
+	 * FIMD0_SEL [3:0]
+	 */
+	sel = readl(&clk->src_lcd0);
+	sel = sel & 0xf;
+
+	/*
+	 * 0x6: SCLK_MPLL
+	 * 0x7: SCLK_EPLL
+	 * 0x8: SCLK_VPLL
+	 */
+	if (sel == 0x6)
+		sclk = get_pll_clk(MPLL);
+	else if (sel == 0x7)
+		sclk = get_pll_clk(EPLL);
+	else if (sel == 0x8)
+		sclk = get_pll_clk(VPLL);
+	else
+		return 0;
+
+	/*
+	 * CLK_DIV_LCD0
+	 * FIMD0_RATIO [3:0]
+	 */
+	ratio = readl(&clk->div_lcd0);
+	ratio = ratio & 0xf;
+
+	pclk = sclk / (ratio + 1);
+
+	return pclk;
+}
+
+void exynos4_set_lcd_clk(void)
+{
+	struct exynos4_clock *clk =
+	    (struct exynos4_clock *)samsung_get_base_clock();
+	unsigned int cfg = 0;
+
+	/*
+	 * CLK_GATE_BLOCK
+	 * CLK_CAM	[0]
+	 * CLK_TV	[1]
+	 * CLK_MFC	[2]
+	 * CLK_G3D	[3]
+	 * CLK_LCD0	[4]
+	 * CLK_LCD1	[5]
+	 * CLK_GPS	[7]
+	 */
+	cfg = readl(&clk->gate_block);
+	cfg |= 1 << 4;
+	writel(cfg, &clk->gate_block);
+
+	/*
+	 * CLK_SRC_LCD0
+	 * FIMD0_SEL		[3:0]
+	 * MDNIE0_SEL		[7:4]
+	 * MDNIE_PWM0_SEL	[8:11]
+	 * MIPI0_SEL		[12:15]
+	 * set lcd0 src clock 0x6: SCLK_MPLL
+	 */
+	cfg = readl(&clk->src_lcd0);
+	cfg &= ~(0xf);
+	cfg |= 0x6;
+	writel(cfg, &clk->src_lcd0);
+
+	/*
+	 * CLK_GATE_IP_LCD0
+	 * CLK_FIMD0		[0]
+	 * CLK_MIE0		[1]
+	 * CLK_MDNIE0		[2]
+	 * CLK_DSIM0		[3]
+	 * CLK_SMMUFIMD0	[4]
+	 * CLK_PPMULCD0		[5]
+	 * Gating all clocks for FIMD0
+	 */
+	cfg = readl(&clk->gate_ip_lcd0);
+	cfg |= 1 << 0;
+	writel(cfg, &clk->gate_ip_lcd0);
+
+	/*
+	 * CLK_DIV_LCD0
+	 * FIMD0_RATIO		[3:0]
+	 * MDNIE0_RATIO		[7:4]
+	 * MDNIE_PWM0_RATIO	[11:8]
+	 * MDNIE_PWM_PRE_RATIO	[15:12]
+	 * MIPI0_RATIO		[19:16]
+	 * MIPI0_PRE_RATIO	[23:20]
+	 * set fimd ratio
+	 */
+	cfg &= ~(0xf);
+	cfg |= 0x1;
+	writel(cfg, &clk->div_lcd0);
+}
+
+void exynos4_set_mipi_clk(void)
+{
+	struct exynos4_clock *clk =
+	    (struct exynos4_clock *)samsung_get_base_clock();
+	unsigned int cfg = 0;
+
+	/*
+	 * CLK_SRC_LCD0
+	 * FIMD0_SEL		[3:0]
+	 * MDNIE0_SEL		[7:4]
+	 * MDNIE_PWM0_SEL	[8:11]
+	 * MIPI0_SEL		[12:15]
+	 * set mipi0 src clock 0x6: SCLK_MPLL
+	 */
+	cfg = readl(&clk->src_lcd0);
+	cfg &= ~(0xf << 12);
+	cfg |= (0x6 << 12);
+	writel(cfg, &clk->src_lcd0);
+
+	/*
+	 * CLK_SRC_MASK_LCD0
+	 * FIMD0_MASK		[0]
+	 * MDNIE0_MASK		[4]
+	 * MDNIE_PWM0_MASK	[8]
+	 * MIPI0_MASK		[12]
+	 * set src mask mipi0 0x1: Unmask
+	 */
+	cfg = readl(&clk->src_mask_lcd0);
+	cfg |= (0x1 << 12);
+	writel(cfg, &clk->src_mask_lcd0);
+
+	/*
+	 * CLK_GATE_IP_LCD0
+	 * CLK_FIMD0		[0]
+	 * CLK_MIE0		[1]
+	 * CLK_MDNIE0		[2]
+	 * CLK_DSIM0		[3]
+	 * CLK_SMMUFIMD0	[4]
+	 * CLK_PPMULCD0		[5]
+	 * Gating all clocks for MIPI0
+	 */
+	cfg = readl(&clk->gate_ip_lcd0);
+	cfg |= 1 << 3;
+	writel(cfg, &clk->gate_ip_lcd0);
+
+	/*
+	 * CLK_DIV_LCD0
+	 * FIMD0_RATIO		[3:0]
+	 * MDNIE0_RATIO		[7:4]
+	 * MDNIE_PWM0_RATIO	[11:8]
+	 * MDNIE_PWM_PRE_RATIO	[15:12]
+	 * MIPI0_RATIO		[19:16]
+	 * MIPI0_PRE_RATIO	[23:20]
+	 * set mipi ratio
+	 */
+	cfg &= ~(0xf << 16);
+	cfg |= (0x1 << 16);
+	writel(cfg, &clk->div_lcd0);
+}
+
 unsigned long get_pll_clk(int pllreg)
 {
 	if (cpu_is_exynos5())
@@ -453,3 +617,23 @@ void set_mmc_clk(int dev_index, unsigned int div)
 	else
 		exynos4_set_mmc_clk(dev_index, div);
 }
+
+unsigned long get_lcd_clk(void)
+{
+	if (cpu_is_exynos4())
+		return exynos4_get_lcd_clk();
+	else
+		return 0;
+}
+
+void set_lcd_clk(void)
+{
+	if (cpu_is_exynos4())
+		exynos4_set_lcd_clk();
+}
+
+void set_mipi_clk(void)
+{
+	if (cpu_is_exynos4())
+		exynos4_set_mipi_clk();
+}
diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c
new file mode 100644
index 0000000000..c765304fd5
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/power.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/power.h>
+
+static void exynos4_mipi_phy_control(unsigned int dev_index,
+					unsigned int enable)
+{
+	struct exynos4_power *pmu =
+	    (struct exynos4_power *)samsung_get_base_power();
+	unsigned int addr, cfg = 0;
+
+	if (dev_index == 0)
+		addr = (unsigned int)&pmu->mipi_phy0_control;
+	else
+		addr = (unsigned int)&pmu->mipi_phy1_control;
+
+
+	cfg = readl(addr);
+	if (enable)
+		cfg |= (EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
+	else
+		cfg &= ~(EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
+
+	writel(cfg, addr);
+}
+
+void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable)
+{
+	if (cpu_is_exynos4())
+		exynos4_mipi_phy_control(dev_index, enable);
+}
diff --git a/arch/arm/cpu/armv7/exynos/system.c b/arch/arm/cpu/armv7/exynos/system.c
new file mode 100644
index 0000000000..6c34730b97
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/system.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/system.h>
+
+static void exynos4_set_system_display(void)
+{
+	struct exynos4_sysreg *sysreg =
+	    (struct exynos4_sysreg *)samsung_get_base_sysreg();
+	unsigned int cfg = 0;
+
+	/*
+	 * system register path set
+	 * 0: MIE/MDNIE
+	 * 1: FIMD Bypass
+	 */
+	cfg = readl(&sysreg->display_ctrl);
+	cfg |= (1 << 1);
+	writel(cfg, &sysreg->display_ctrl);
+}
+
+void set_system_display_ctrl(void)
+{
+	if (cpu_is_exynos4())
+		exynos4_set_system_display();
+}
diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c
index 3d58d8ae91..b3195dd6fb 100644
--- a/arch/arm/cpu/armv7/imx-common/cpu.c
+++ b/arch/arm/cpu/armv7/imx-common/cpu.c
@@ -29,12 +29,13 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
 
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
 #endif
 
-static char *get_reset_cause(void)
+char *get_reset_cause(void)
 {
 	u32 cause;
 	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
@@ -127,3 +128,15 @@ void reset_cpu(ulong addr)
 {
 	__raw_writew(4, WDOG1_BASE_ADDR);
 }
+
+u32 get_ahb_clk(void)
+{
+	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	u32 reg, ahb_podf;
+
+	reg = __raw_readl(&imx_ccm->cbcdr);
+	reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
+	ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
+
+	return get_periph_clk() / (ahb_podf + 1);
+}
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index e92f10623a..fc2406bcad 100644
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -30,6 +30,7 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
 #include <div64.h>
+#include <asm/arch/sys_proto.h>
 
 enum pll_clocks {
 	PLL1_CLOCK = 0,
@@ -48,6 +49,42 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
 #endif
 };
 
+#define AHB_CLK_ROOT    133333333
+#define SZ_DEC_1M       1000000
+#define PLL_PD_MAX      16      /* Actual pd+1 */
+#define PLL_MFI_MAX     15
+#define PLL_MFI_MIN     5
+#define ARM_DIV_MAX     8
+#define IPG_DIV_MAX     4
+#define AHB_DIV_MAX     8
+#define EMI_DIV_MAX     8
+#define NFC_DIV_MAX     8
+
+#define MX5_CBCMR	0x00015154
+#define MX5_CBCDR	0x02888945
+
+struct fixed_pll_mfd {
+	u32 ref_clk_hz;
+	u32 mfd;
+};
+
+const struct fixed_pll_mfd fixed_mfd[] = {
+	{CONFIG_SYS_MX5_HCLK, 24 * 16},
+};
+
+struct pll_param {
+	u32 pd;
+	u32 mfi;
+	u32 mfn;
+	u32 mfd;
+};
+
+#define PLL_FREQ_MAX(ref_clk)  (4 * (ref_clk) * PLL_MFI_MAX)
+#define PLL_FREQ_MIN(ref_clk) \
+		((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
+#define MAX_DDR_CLK     420000000
+#define NFC_CLK_MAX     34000000
+
 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 
 void set_usboh3_clk(void)
@@ -192,7 +229,7 @@ u32 get_mcu_main_clk(void)
 /*
  * Get the rate of peripheral's root clock.
  */
-static u32 get_periph_clk(void)
+u32 get_periph_clk(void)
 {
 	u32 reg;
 
@@ -213,22 +250,6 @@ static u32 get_periph_clk(void)
 }
 
 /*
- * Get the rate of ahb clock.
- */
-static u32 get_ahb_clk(void)
-{
-	uint32_t freq, div, reg;
-
-	freq = get_periph_clk();
-
-	reg = __raw_readl(&mxc_ccm->cbcdr);
-	div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
-			MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
-
-	return freq / div;
-}
-
-/*
  * Get the rate of ipg clock.
  */
 static u32 get_ipg_clk(void)
@@ -306,7 +327,7 @@ static u32 get_uart_clk(void)
 /*
  * This function returns the low power audio clock.
  */
-u32 get_lp_apm(void)
+static u32 get_lp_apm(void)
 {
 	u32 ret_val = 0;
 	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
@@ -322,7 +343,7 @@ u32 get_lp_apm(void)
 /*
  * get cspi clock rate.
  */
-u32 imx_get_cspiclk(void)
+static u32 imx_get_cspiclk(void)
 {
 	u32 ret_val = 0, pdf, pre_pdf, clk_sel;
 	u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
@@ -359,8 +380,77 @@ u32 imx_get_cspiclk(void)
 	return ret_val;
 }
 
+static u32 get_axi_a_clk(void)
+{
+	u32 cbcdr =  __raw_readl(&mxc_ccm->cbcdr);
+	u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \
+			>> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET;
+
+	return  get_periph_clk() / (pdf + 1);
+}
+
+static u32 get_axi_b_clk(void)
+{
+	u32 cbcdr =  __raw_readl(&mxc_ccm->cbcdr);
+	u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \
+			>> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET;
+
+	return  get_periph_clk() / (pdf + 1);
+}
+
+static u32 get_emi_slow_clk(void)
+{
+	u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+	u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
+	u32 pdf = (cbcdr & MXC_CCM_CBCDR_EMI_PODF_MASK) \
+			>> MXC_CCM_CBCDR_EMI_PODF_OFFSET;
+
+	if (emi_clk_sel)
+		return  get_ahb_clk() / (pdf + 1);
+
+	return  get_periph_clk() / (pdf + 1);
+}
+
+static u32 get_ddr_clk(void)
+{
+	u32 ret_val = 0;
+	u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
+	u32 ddr_clk_sel = (cbcmr & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) \
+				>> MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET;
+#ifdef CONFIG_MX51
+	u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+	if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
+		u32 ddr_clk_podf = (cbcdr & MXC_CCM_CBCDR_DDR_PODF_MASK) >> \
+					MXC_CCM_CBCDR_DDR_PODF_OFFSET;
+
+		ret_val = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
+		ret_val /= ddr_clk_podf + 1;
+
+		return ret_val;
+	}
+#endif
+	switch (ddr_clk_sel) {
+	case 0:
+		ret_val = get_axi_a_clk();
+		break;
+	case 1:
+		ret_val = get_axi_b_clk();
+		break;
+	case 2:
+		ret_val = get_emi_slow_clk();
+		break;
+	case 3:
+		ret_val = get_ahb_clk();
+		break;
+	default:
+		break;
+	}
+
+	return ret_val;
+}
+
 /*
- * The API of get mxc clockes.
+ * The API of get mxc clocks.
  */
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
@@ -380,10 +470,14 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 	case MXC_FEC_CLK:
 		return decode_pll(mxc_plls[PLL1_CLOCK],
 				    CONFIG_SYS_MX5_HCLK);
+	case MXC_SATA_CLK:
+		return get_ahb_clk();
+	case MXC_DDR_CLK:
+		return get_ddr_clk();
 	default:
 		break;
 	}
-	return -1;
+	return -EINVAL;
 }
 
 u32 imx_get_uartclk(void)
@@ -397,6 +491,362 @@ u32 imx_get_fecclk(void)
 	return mxc_get_clock(MXC_IPG_CLK);
 }
 
+static int gcd(int m, int n)
+{
+	int t;
+	while (m > 0) {
+		if (n > m) {
+			t = m;
+			m = n;
+			n = t;
+		} /* swap */
+		m -= n;
+	}
+	return n;
+}
+
+/*
+ * This is to calculate various parameters based on reference clock and
+ * targeted clock based on the equation:
+ *      t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
+ * This calculation is based on a fixed MFD value for simplicity.
+ */
+static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
+{
+	u64 pd, mfi = 1, mfn, mfd, t1;
+	u32 n_target = target;
+	u32 n_ref = ref, i;
+
+	/*
+	 * Make sure targeted freq is in the valid range.
+	 * Otherwise the following calculation might be wrong!!!
+	 */
+	if (n_target < PLL_FREQ_MIN(ref) ||
+		n_target > PLL_FREQ_MAX(ref)) {
+		printf("Targeted peripheral clock should be"
+			"within [%d - %d]\n",
+			PLL_FREQ_MIN(ref) / SZ_DEC_1M,
+			PLL_FREQ_MAX(ref) / SZ_DEC_1M);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) {
+		if (fixed_mfd[i].ref_clk_hz == ref) {
+			mfd = fixed_mfd[i].mfd;
+			break;
+		}
+	}
+
+	if (i == ARRAY_SIZE(fixed_mfd))
+		return -EINVAL;
+
+	/* Use n_target and n_ref to avoid overflow */
+	for (pd = 1; pd <= PLL_PD_MAX; pd++) {
+		t1 = n_target * pd;
+		do_div(t1, (4 * n_ref));
+		mfi = t1;
+		if (mfi > PLL_MFI_MAX)
+			return -EINVAL;
+		else if (mfi < 5)
+			continue;
+		break;
+	}
+	/*
+	 * Now got pd and mfi already
+	 *
+	 * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
+	 */
+	t1 = n_target * pd;
+	do_div(t1, 4);
+	t1 -= n_ref * mfi;
+	t1 *= mfd;
+	do_div(t1, n_ref);
+	mfn = t1;
+	debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n",
+		ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
+	i = 1;
+	if (mfn != 0)
+		i = gcd(mfd, mfn);
+	pll->pd = (u32)pd;
+	pll->mfi = (u32)mfi;
+	do_div(mfn, i);
+	pll->mfn = (u32)mfn;
+	do_div(mfd, i);
+	pll->mfd = (u32)mfd;
+
+	return 0;
+}
+
+#define calc_div(tgt_clk, src_clk, limit) ({		\
+		u32 v = 0;				\
+		if (((src_clk) % (tgt_clk)) <= 100)	\
+			v = (src_clk) / (tgt_clk);	\
+		else					\
+			v = ((src_clk) / (tgt_clk)) + 1;\
+		if (v > limit)				\
+			v = limit;			\
+		(v - 1);				\
+	})
+
+#define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
+	{	\
+		__raw_writel(0x1232, &pll->ctrl);		\
+		__raw_writel(0x2, &pll->config);		\
+		__raw_writel((((pd) - 1) << 0) | ((fi) << 4),	\
+			&pll->op);				\
+		__raw_writel(fn, &(pll->mfn));			\
+		__raw_writel((fd) - 1, &pll->mfd);		\
+		__raw_writel((((pd) - 1) << 0) | ((fi) << 4),	\
+			&pll->hfs_op);				\
+		__raw_writel(fn, &pll->hfs_mfn);		\
+		__raw_writel((fd) - 1, &pll->hfs_mfd);		\
+		__raw_writel(0x1232, &pll->ctrl);		\
+		while (!__raw_readl(&pll->ctrl) & 0x1)		\
+			;\
+	}
+
+static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
+{
+	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
+	struct mxc_pll_reg *pll = mxc_plls[index];
+
+	switch (index) {
+	case PLL1_CLOCK:
+		/* Switch ARM to PLL2 clock */
+		__raw_writel(ccsr | 0x4, &mxc_ccm->ccsr);
+		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
+					pll_param->mfi, pll_param->mfn,
+					pll_param->mfd);
+		/* Switch back */
+		__raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr);
+		break;
+	case PLL2_CLOCK:
+		/* Switch to pll2 bypass clock */
+		__raw_writel(ccsr | 0x2, &mxc_ccm->ccsr);
+		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
+					pll_param->mfi, pll_param->mfn,
+					pll_param->mfd);
+		/* Switch back */
+		__raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr);
+		break;
+	case PLL3_CLOCK:
+		/* Switch to pll3 bypass clock */
+		__raw_writel(ccsr | 0x1, &mxc_ccm->ccsr);
+		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
+					pll_param->mfi, pll_param->mfn,
+					pll_param->mfd);
+		/* Switch back */
+		__raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);
+		break;
+	case PLL4_CLOCK:
+		/* Switch to pll4 bypass clock */
+		__raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);
+		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
+					pll_param->mfi, pll_param->mfn,
+					pll_param->mfd);
+		/* Switch back */
+		__raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/* Config CPU clock */
+static int config_core_clk(u32 ref, u32 freq)
+{
+	int ret = 0;
+	struct pll_param pll_param;
+
+	memset(&pll_param, 0, sizeof(struct pll_param));
+
+	/* The case that periph uses PLL1 is not considered here */
+	ret = calc_pll_params(ref, freq, &pll_param);
+	if (ret != 0) {
+		printf("Error:Can't find pll parameters: %d\n", ret);
+		return ret;
+	}
+
+	return config_pll_clk(PLL1_CLOCK, &pll_param);
+}
+
+static int config_nfc_clk(u32 nfc_clk)
+{
+	u32 reg;
+	u32 parent_rate = get_emi_slow_clk();
+	u32 div = parent_rate / nfc_clk;
+
+	if (nfc_clk <= 0)
+		return -EINVAL;
+	if (div == 0)
+		div++;
+	if (parent_rate / div > NFC_CLK_MAX)
+		div++;
+	reg = __raw_readl(&mxc_ccm->cbcdr);
+	reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
+	reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
+	__raw_writel(reg, &mxc_ccm->cbcdr);
+	while (__raw_readl(&mxc_ccm->cdhipr) != 0)
+		;
+	return 0;
+}
+
+/* Config main_bus_clock for periphs */
+static int config_periph_clk(u32 ref, u32 freq)
+{
+	int ret = 0;
+	struct pll_param pll_param;
+
+	memset(&pll_param, 0, sizeof(struct pll_param));
+
+	if (__raw_readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
+		ret = calc_pll_params(ref, freq, &pll_param);
+		if (ret != 0) {
+			printf("Error:Can't find pll parameters: %d\n",
+				ret);
+			return ret;
+		}
+		switch ((__raw_readl(&mxc_ccm->cbcmr) & \
+			MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> \
+			MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
+		case 0:
+			return config_pll_clk(PLL1_CLOCK, &pll_param);
+			break;
+		case 1:
+			return config_pll_clk(PLL3_CLOCK, &pll_param);
+			break;
+		default:
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+static int config_ddr_clk(u32 emi_clk)
+{
+	u32 clk_src;
+	s32 shift = 0, clk_sel, div = 1;
+	u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
+	u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+
+	if (emi_clk > MAX_DDR_CLK) {
+		printf("Warning:DDR clock should not exceed %d MHz\n",
+			MAX_DDR_CLK / SZ_DEC_1M);
+		emi_clk = MAX_DDR_CLK;
+	}
+
+	clk_src = get_periph_clk();
+	/* Find DDR clock input */
+	clk_sel = (cbcmr >> 10) & 0x3;
+	switch (clk_sel) {
+	case 0:
+		shift = 16;
+		break;
+	case 1:
+		shift = 19;
+		break;
+	case 2:
+		shift = 22;
+		break;
+	case 3:
+		shift = 10;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if ((clk_src % emi_clk) < 10000000)
+		div = clk_src / emi_clk;
+	else
+		div = (clk_src / emi_clk) + 1;
+	if (div > 8)
+		div = 8;
+
+	cbcdr = cbcdr & ~(0x7 << shift);
+	cbcdr |= ((div - 1) << shift);
+	__raw_writel(cbcdr, &mxc_ccm->cbcdr);
+	while (__raw_readl(&mxc_ccm->cdhipr) != 0)
+		;
+	__raw_writel(0x0, &mxc_ccm->ccdr);
+
+	return 0;
+}
+
+/*
+ * This function assumes the expected core clock has to be changed by
+ * modifying the PLL. This is NOT true always but for most of the times,
+ * it is. So it assumes the PLL output freq is the same as the expected
+ * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
+ * In the latter case, it will try to increase the presc value until
+ * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
+ * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
+ * on the targeted PLL and reference input clock to the PLL. Lastly,
+ * it sets the register based on these values along with the dividers.
+ * Note 1) There is no value checking for the passed-in divider values
+ *         so the caller has to make sure those values are sensible.
+ *      2) Also adjust the NFC divider such that the NFC clock doesn't
+ *         exceed NFC_CLK_MAX.
+ *      3) IPU HSP clock is independent of AHB clock. Even it can go up to
+ *         177MHz for higher voltage, this function fixes the max to 133MHz.
+ *      4) This function should not have allowed diag_printf() calls since
+ *         the serial driver has been stoped. But leave then here to allow
+ *         easy debugging by NOT calling the cyg_hal_plf_serial_stop().
+ */
+int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
+{
+	freq *= SZ_DEC_1M;
+
+	switch (clk) {
+	case MXC_ARM_CLK:
+		if (config_core_clk(ref, freq))
+			return -EINVAL;
+		break;
+	case MXC_PERIPH_CLK:
+		if (config_periph_clk(ref, freq))
+			return -EINVAL;
+		break;
+	case MXC_DDR_CLK:
+		if (config_ddr_clk(freq))
+			return -EINVAL;
+		break;
+	case MXC_NFC_CLK:
+		if (config_nfc_clk(freq))
+			return -EINVAL;
+		break;
+	default:
+		printf("Warning:Unsupported or invalid clock type\n");
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_MX53
+/*
+ * The clock for the external interface can be set to use internal clock
+ * if fuse bank 4, row 3, bit 2 is set.
+ * This is an undocumented feature and it was confirmed by Freescale's support:
+ * Fuses (but not pins) may be used to configure SATA clocks.
+ * Particularly the i.MX53 Fuse_Map contains the next information
+ * about configuring SATA clocks :  SATA_ALT_REF_CLK[1:0] (offset 0x180C)
+ * '00' - 100MHz (External)
+ * '01' - 50MHz (External)
+ * '10' - 120MHz, internal (USB PHY)
+ * '11' - Reserved
+*/
+void mxc_set_sata_internal_clock(void)
+{
+	u32 *tmp_base =
+		(u32 *)(IIM_BASE_ADDR + 0x180c);
+
+	set_usb_phy1_clk();
+
+	writel((readl(tmp_base) & (~0x7)) | 0x4, tmp_base);
+}
+#endif
+
 /*
  * Dump some core clockes.
  */
@@ -419,6 +869,7 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
 	printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
 	printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
+	printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
 
 	return 0;
 }
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index 74ab753a4a..683a7b53af 100644
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -22,6 +22,7 @@
 #include <config.h>
 #include <asm/arch/imx-regs.h>
 #include <generated/asm-offsets.h>
+#include <linux/linkage.h>
 
 /*
  * L2CC Cache setup/invalidation/disable
@@ -326,8 +327,7 @@
 
 .section ".text.init", "x"
 
-.globl lowlevel_init
-lowlevel_init:
+ENTRY(lowlevel_init)
 #if defined(CONFIG_MX51)
 	ldr r0, =GPIO1_BASE_ADDR
 	ldr r1, [r0, #0x0]
@@ -348,6 +348,7 @@ lowlevel_init:
 
 	/* r12 saved upper lr*/
 	mov pc,lr
+ENDPROC(lowlevel_init)
 
 /* Board level setting value */
 W_DP_OP_864:              .word DP_OP_864
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index ef98563ff7..52d5dc4d90 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -24,8 +24,9 @@
 #include <asm/io.h>
 #include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/ccm_regs.h>
+#include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
 
 enum pll_clocks {
 	PLL_SYS,	/* System PLL */
@@ -34,7 +35,7 @@ enum pll_clocks {
 	PLL_ENET,	/* ENET PLL */
 };
 
-struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR;
+struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 
 void enable_usboh3_clk(unsigned char enable)
 {
@@ -92,7 +93,7 @@ static u32 get_mcu_main_clk(void)
 	return freq / (reg + 1);
 }
 
-static u32 get_periph_clk(void)
+u32 get_periph_clk(void)
 {
 	u32 reg, freq = 0;
 
@@ -139,18 +140,6 @@ static u32 get_periph_clk(void)
 	return freq;
 }
 
-
-static u32 get_ahb_clk(void)
-{
-	u32 reg, ahb_podf;
-
-	reg = __raw_readl(&imx_ccm->cbcdr);
-	reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
-	ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
-
-	return get_periph_clk() / (ahb_podf + 1);
-}
-
 static u32 get_ipg_clk(void)
 {
 	u32 reg, ipg_podf;
@@ -303,6 +292,37 @@ u32 imx_get_fecclk(void)
 	return decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
 }
 
+int enable_sata_clock(void)
+{
+	u32 reg = 0;
+	s32 timeout = 100000;
+	struct mxc_ccm_reg *const imx_ccm
+		= (struct mxc_ccm_reg *) CCM_BASE_ADDR;
+
+	/* Enable sata clock */
+	reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
+	reg |= MXC_CCM_CCGR5_CG2_MASK;
+	writel(reg, &imx_ccm->CCGR5);
+
+	/* Enable PLLs */
+	reg = readl(&imx_ccm->analog_pll_enet);
+	reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
+	writel(reg, &imx_ccm->analog_pll_enet);
+	reg |= BM_ANADIG_PLL_SYS_ENABLE;
+	while (timeout--) {
+		if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
+			break;
+	}
+	if (timeout <= 0)
+		return -EIO;
+	reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
+	writel(reg, &imx_ccm->analog_pll_enet);
+	reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA;
+	writel(reg, &imx_ccm->analog_pll_enet);
+
+	return 0 ;
+}
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
 	switch (clk) {
diff --git a/arch/arm/cpu/armv7/mx6/lowlevel_init.S b/arch/arm/cpu/armv7/mx6/lowlevel_init.S
index 1864356d0b..acadef221c 100644
--- a/arch/arm/cpu/armv7/mx6/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx6/lowlevel_init.S
@@ -18,7 +18,8 @@
  */
 .section ".text.init", "x"
 
-.globl lowlevel_init
-lowlevel_init:
+#include <linux/linkage.h>
 
+ENTRY(lowlevel_init)
 	mov pc, lr
+ENDPROC(lowlevel_init)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 543b2cc6d8..90f208809b 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -77,10 +77,40 @@ void init_aips(void)
 	writel(0x00000000, &aips2->opacr4);
 }
 
+/*
+ * Set the VDDSOC
+ *
+ * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
+ * them to the specified millivolt level.
+ * Possible values are from 0.725V to 1.450V in steps of
+ * 0.025V (25mV).
+ */
+void set_vddsoc(u32 mv)
+{
+	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	u32 val, reg = readl(&anatop->reg_core);
+
+	if (mv < 725)
+		val = 0x00;	/* Power gated off */
+	else if (mv > 1450)
+		val = 0x1F;	/* Power FET switched full on. No regulation */
+	else
+		val = (mv - 700) / 25;
+
+	/*
+	 * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
+	 * and set them to the calculated value (0.7V + val * 0.25V)
+	 */
+	reg = (reg & ~(0x1F << 18)) | (val << 18);
+	writel(reg, &anatop->reg_core);
+}
+
 int arch_cpu_init(void)
 {
 	init_aips();
 
+	set_vddsoc(1200);	/* Set VDDSOC to 1.2V */
+
 	return 0;
 }
 #endif
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index 447fcd5eff..2a6625f1c4 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -37,6 +37,7 @@ ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
 COBJS	+= hwinit-common.o
 COBJS	+= clocks-common.o
 COBJS	+= emif-common.o
+COBJS	+= vc.o
 endif
 
 ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 4e7456992f..10d286a6d4 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -245,6 +245,11 @@ void configure_mpu_dpll(void)
 			CM_CLKSEL_DCC_EN_MASK);
 	}
 
+	setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
+		MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
+	setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
+		MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
+
 	params = get_mpu_dpll_params();
 
 	do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
@@ -360,56 +365,51 @@ static void setup_non_essential_dplls(void)
 }
 #endif
 
-void do_scale_tps62361(u32 reg, u32 volt_mv)
+void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv)
 {
-	u32 temp, step;
+	u32 step;
+	int ret = 0;
+
+	/* See if we can first get the GPIO if needed */
+	if (gpio >= 0)
+		ret = gpio_request(gpio, "TPS62361_VSEL0_GPIO");
+	if (ret < 0) {
+		printf("%s: gpio %d request failed %d\n", __func__, gpio, ret);
+		gpio = -1;
+	}
+
+	/* Pull the GPIO low to select SET0 register, while we program SET1 */
+	if (gpio >= 0)
+		gpio_direction_output(gpio, 0);
 
 	step = volt_mv - TPS62361_BASE_VOLT_MV;
 	step /= 10;
 
-	temp = TPS62361_I2C_SLAVE_ADDR |
-	    (reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
-	    (step << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
-	    PRM_VC_VAL_BYPASS_VALID_BIT;
 	debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
-
-	writel(temp, &prcm->prm_vc_val_bypass);
-	if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
-				&prcm->prm_vc_val_bypass, LDELAY)) {
+	if (omap_vc_bypass_send_value(TPS62361_I2C_SLAVE_ADDR, reg, step))
 		puts("Scaling voltage failed for vdd_mpu from TPS\n");
-	}
+
+	/* Pull the GPIO high to select SET1 register */
+	if (gpio >= 0)
+		gpio_direction_output(gpio, 1);
 }
 
 void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
 {
-	u32 temp, offset_code;
-	u32 step = 12660; /* 12.66 mV represented in uV */
+	u32 offset_code;
 	u32 offset = volt_mv;
 
 	/* convert to uV for better accuracy in the calculations */
 	offset *= 1000;
 
-	if (omap_revision() == OMAP4430_ES1_0)
-		offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
-	else
-		offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
-
-	offset_code = (offset + step - 1) / step;
-	/* The code starts at 1 not 0 */
-	offset_code++;
+	offset_code = get_offset_code(offset);
 
 	debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
 		offset_code);
 
-	temp = SMPS_I2C_SLAVE_ADDR |
-	    (vcore_reg << PRM_VC_VAL_BYPASS_REGADDR_SHIFT) |
-	    (offset_code << PRM_VC_VAL_BYPASS_DATA_SHIFT) |
-	    PRM_VC_VAL_BYPASS_VALID_BIT;
-	writel(temp, &prcm->prm_vc_val_bypass);
-	if (!wait_on_value(PRM_VC_VAL_BYPASS_VALID_BIT, 0,
-				&prcm->prm_vc_val_bypass, LDELAY)) {
+	if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR,
+				vcore_reg, offset_code))
 		printf("Scaling voltage failed for 0x%x\n", vcore_reg);
-	}
 }
 
 static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
@@ -452,6 +452,7 @@ void freq_update_core(void)
 {
 	u32 freq_config1 = 0;
 	const struct dpll_params *core_dpll_params;
+	u32 omap_rev = omap_revision();
 
 	core_dpll_params = get_core_dpll_params();
 	/* Put EMIF clock domain in sw wakeup mode */
@@ -477,11 +478,18 @@ void freq_update_core(void)
 		hang();
 	}
 
-	/* Put EMIF clock domain back in hw auto mode */
-	enable_clock_domain(&prcm->cm_memif_clkstctrl,
-				CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
-	wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
-	wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
+	/*
+	 * Putting EMIF in HW_AUTO is seen to be causing issues with
+	 * EMIF clocks and the master DLL. Put EMIF in SW_WKUP
+	 * in OMAP5430 ES1.0 silicon
+	 */
+	if (omap_rev != OMAP5430_ES1_0) {
+		/* Put EMIF clock domain back in hw auto mode */
+		enable_clock_domain(&prcm->cm_memif_clkstctrl,
+					CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
+		wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
+		wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
+	}
 }
 
 void bypass_dpll(u32 *const base)
@@ -529,29 +537,6 @@ void setup_clocks_for_console(void)
 			CD_CLKCTRL_CLKTRCTRL_SHIFT);
 }
 
-void setup_sri2c(void)
-{
-	u32 sys_clk_khz, cycles_hi, cycles_low, temp;
-
-	sys_clk_khz = get_sys_clk_freq() / 1000;
-
-	/*
-	 * Setup the dedicated I2C controller for Voltage Control
-	 * I2C clk - high period 40% low period 60%
-	 */
-	cycles_hi = sys_clk_khz * 4 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
-	cycles_low = sys_clk_khz * 6 / PRM_VC_I2C_CHANNEL_FREQ_KHZ / 10;
-	/* values to be set in register - less by 5 & 7 respectively */
-	cycles_hi -= 5;
-	cycles_low -= 7;
-	temp = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
-	       (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
-	writel(temp, &prcm->prm_vc_cfg_i2c_clk);
-
-	/* Disable high speed mode and all advanced features */
-	writel(0x0, &prcm->prm_vc_cfg_i2c_mode);
-}
-
 void do_enable_clocks(u32 *const *clk_domains,
 			    u32 *const *clk_modules_hw_auto,
 			    u32 *const *clk_modules_explicit_en,
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 62678ff5d3..db509c9295 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -90,20 +90,33 @@ static void do_lpddr2_init(u32 base, u32 cs)
 	 * tZQINIT = 1 us
 	 * Enough loops assuming a maximum of 2GHz
 	 */
+
 	sdelay(2000);
-	set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
+
+	if (omap_revision() >= OMAP5430_ES1_0)
+		set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8);
+	else
+		set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
+
 	set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
+
 	/*
 	 * Enable refresh along with writing MR2
 	 * Encoding of RL in MR2 is (RL - 2)
 	 */
 	mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
 	set_mr(base, cs, mr_addr, RL_FINAL - 2);
+
+	if (omap_revision() >= OMAP5430_ES1_0)
+		set_mr(base, cs, LPDDR2_MR3, 0x1);
 }
 
 static void lpddr2_init(u32 base, const struct emif_regs *regs)
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+	u32 *ext_phy_ctrl_base = 0;
+	u32 *emif_ext_phy_ctrl_base = 0;
+	u32 i = 0;
 
 	/* Not NVM */
 	clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
@@ -119,7 +132,31 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs)
 	 * un-locked frequency & default RL
 	 */
 	writel(regs->sdram_config_init, &emif->emif_sdram_config);
-	writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
+	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+
+	ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
+	emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
+
+	if (omap_revision() >= OMAP5430_ES1_0) {
+		/* Configure external phy control timing registers */
+		for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
+			writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
+			/* Update shadow registers */
+			writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
+		}
+
+		/*
+		 * external phy 6-24 registers do not change with
+		 * ddr frequency
+		 */
+		for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
+			writel(ext_phy_ctrl_const_base[i],
+						emif_ext_phy_ctrl_base++);
+			/* Update shadow registers */
+			writel(ext_phy_ctrl_const_base[i],
+						emif_ext_phy_ctrl_base++);
+		}
+	}
 
 	do_lpddr2_init(base, CS0);
 	if (regs->sdram_config & EMIF_REG_EBANK_MASK)
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index ab46bff5af..cf71ab4443 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -203,21 +203,15 @@ int checkboard(void)
 }
 
 /*
-* This function is called by start_armboot. You can reliably use static
-* data. Any boot-time function that require static data should be
-* called from here
-*/
-int arch_cpu_init(void)
-{
-	return 0;
-}
-
-/*
  *  get_device_type(): tell if GP/HS/EMU/TST
  */
 u32 get_device_type(void)
 {
-	return 0;
+	struct omap_sys_ctrl_regs *ctrl =
+		      (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
+
+	return (readl(&ctrl->control_status) &
+				      (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
 }
 
 /*
diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
index 35f38acf5d..ccc6bb6b85 100644
--- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
@@ -27,9 +27,9 @@
  */
 
 #include <asm/arch/omap.h>
+#include <linux/linkage.h>
 
-.global save_boot_params
-save_boot_params:
+ENTRY(save_boot_params)
 	/*
 	 * See if the rom code passed pointer is valid:
 	 * It is not valid if it is not in non-secure SRAM
@@ -76,10 +76,9 @@ save_boot_params:
 	strb	r2, [r3, #CH_FLAGS_OFFSET]
 1:
 	bx	lr
+ENDPROC(save_boot_params)
 
-
-.globl lowlevel_init
-lowlevel_init:
+ENTRY(lowlevel_init)
 	/*
 	 * Setup a temporary stack
 	 */
@@ -95,12 +94,13 @@ lowlevel_init:
 	 */
 	bl	s_init
 	pop	{ip, pc}
+ENDPROC(lowlevel_init)
 
-.globl set_pl310_ctrl_reg
-set_pl310_ctrl_reg:
+ENTRY(set_pl310_ctrl_reg)
 	PUSH	{r4-r11, lr}	@ save registers - ROM code may pollute
 				@ our registers
 	LDR	r12, =0x102	@ Set PL310 control register - value in R0
 	.word	0xe1600070	@ SMC #0 - hand assembled because -march=armv5
 				@ call ROM Code API to set control register
 	POP	{r4-r11, pc}
+ENDPROC(set_pl310_ctrl_reg)
diff --git a/arch/arm/cpu/armv7/omap-common/reset.S b/arch/arm/cpu/armv7/omap-common/reset.c
index 838b1221ee..234e90a868 100644
--- a/arch/arm/cpu/armv7/omap-common/reset.S
+++ b/arch/arm/cpu/armv7/omap-common/reset.c
@@ -1,6 +1,11 @@
 /*
- * Copyright (c) 2009 Samsung Electronics.
- * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * Common layer for reset related functionality of OMAP based socs.
+ *
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -20,19 +25,12 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
-
 #include <config.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <linux/compiler.h>
 
-.global reset_cpu
-reset_cpu:
-	ldr	r1, rstctl			@ get addr for global reset
-						@ reg
-	ldr	r3, rstbit			@ sw reset bit
-	str	r3, [r1]			@ force reset
-	mov	r0, r0
-_loop_forever:
-	b	_loop_forever
-rstctl:
-	.word	PRM_RSTCTRL
-rstbit:
-	.word	PRM_RSTCTRL_RESET
+void __weak reset_cpu(unsigned long ignored)
+{
+	writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
+}
diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c
index 0f2e0a2d27..4d1ac85d00 100644
--- a/arch/arm/cpu/armv7/omap-common/spl.c
+++ b/arch/arm/cpu/armv7/omap-common/spl.c
@@ -162,6 +162,7 @@ void board_init_r(gd_t *id, ulong dummy)
 #ifdef CONFIG_SPL_MMC_SUPPORT
 	case BOOT_DEVICE_MMC1:
 	case BOOT_DEVICE_MMC2:
+	case BOOT_DEVICE_MMC2_2:
 		spl_mmc_load_image();
 		break;
 #endif
diff --git a/arch/arm/cpu/armv7/omap-common/spl_mmc.c b/arch/arm/cpu/armv7/omap-common/spl_mmc.c
index 6f5b43e559..2f921bb07d 100644
--- a/arch/arm/cpu/armv7/omap-common/spl_mmc.c
+++ b/arch/arm/cpu/armv7/omap-common/spl_mmc.c
@@ -39,10 +39,11 @@ int board_mmc_init(bd_t *bis)
 {
 	switch (omap_boot_device()) {
 	case BOOT_DEVICE_MMC1:
-		omap_mmc_init(0);
+		omap_mmc_init(0, 0, 0);
 		break;
 	case BOOT_DEVICE_MMC2:
-		omap_mmc_init(1);
+	case BOOT_DEVICE_MMC2_2:
+		omap_mmc_init(1, 0, 0);
 		break;
 	}
 	return 0;
diff --git a/arch/arm/cpu/armv7/omap-common/spl_nand.c b/arch/arm/cpu/armv7/omap-common/spl_nand.c
index 1295e88752..8cf55c9a1c 100644
--- a/arch/arm/cpu/armv7/omap-common/spl_nand.c
+++ b/arch/arm/cpu/armv7/omap-common/spl_nand.c
@@ -54,7 +54,7 @@ void spl_nand_load_image(void)
 		 * load parameter image
 		 * load to temp position since nand_spl_load_image reads
 		 * a whole block which is typically larger than
-		 * CONFIG_CMD_SAVEBP_WRITE_SIZE therefore may overwrite
+		 * CONFIG_CMD_SPL_WRITE_SIZE therefore may overwrite
 		 * following sections like BSS
 		 */
 		nand_spl_load_image(CONFIG_CMD_SPL_NAND_OFS,
diff --git a/arch/arm/cpu/armv7/omap-common/vc.c b/arch/arm/cpu/armv7/omap-common/vc.c
new file mode 100644
index 0000000000..a045b77180
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/vc.c
@@ -0,0 +1,138 @@
+/*
+ * Voltage Controller implementation for OMAP
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *	Nishanth Menon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/omap_common.h>
+#include <asm/arch/sys_proto.h>
+
+/*
+ * Define Master code if there are multiple masters on the I2C_SR bus.
+ * Normally not required
+ */
+#ifndef CONFIG_OMAP_VC_I2C_HS_MCODE
+#define CONFIG_OMAP_VC_I2C_HS_MCODE 0x0
+#endif
+
+/* Register defines and masks for VC IP Block */
+/* PRM_VC_CFG_I2C_MODE */
+#define PRM_VC_CFG_I2C_MODE_DFILTEREN_BIT	(0x1 << 6)
+#define PRM_VC_CFG_I2C_MODE_SRMODEEN_BIT	(0x1 << 4)
+#define PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT	(0x1 << 3)
+#define PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT	0x0
+#define PRM_VC_CFG_I2C_MODE_HSMCODE_MASK	0x3
+
+/* PRM_VC_CFG_I2C_CLK */
+#define PRM_VC_CFG_I2C_CLK_HSCLL_SHIFT		24
+#define PRM_VC_CFG_I2C_CLK_HSCLL_MASK		0xFF
+#define PRM_VC_CFG_I2C_CLK_HSCLH_SHIFT		16
+#define PRM_VC_CFG_I2C_CLK_HSCLH_MASK		0xFF
+#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT		0
+#define PRM_VC_CFG_I2C_CLK_SCLH_MASK		0xFF
+#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT		8
+#define PRM_VC_CFG_I2C_CLK_SCLL_MASK		(0xFF << 8)
+
+/* PRM_VC_VAL_BYPASS */
+#define PRM_VC_VAL_BYPASS_VALID_BIT		(0x1 << 24)
+#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT	0
+#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK	0x7F
+#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT		8
+#define PRM_VC_VAL_BYPASS_REGADDR_MASK		0xFF
+#define PRM_VC_VAL_BYPASS_DATA_SHIFT		16
+#define PRM_VC_VAL_BYPASS_DATA_MASK		0xFF
+
+/**
+ * omap_vc_init() - Initialization for Voltage controller
+ * @speed_khz: I2C buspeed in KHz
+ */
+void omap_vc_init(u16 speed_khz)
+{
+	u32 val;
+	u32 sys_clk_khz, cycles_hi, cycles_low;
+
+	sys_clk_khz = get_sys_clk_freq() / 1000;
+
+	if (speed_khz > 400) {
+		puts("higher speed requested - throttle to 400Khz\n");
+		speed_khz = 400;
+	}
+
+	/*
+	 * Setup the dedicated I2C controller for Voltage Control
+	 * I2C clk - high period 40% low period 60%
+	 */
+	speed_khz /= 10;
+	cycles_hi = sys_clk_khz * 4 / speed_khz;
+	cycles_low = sys_clk_khz * 6 / speed_khz;
+	/* values to be set in register - less by 5 & 7 respectively */
+	cycles_hi -= 5;
+	cycles_low -= 7;
+	val = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
+	       (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
+	writel(val, &prcm->prm_vc_cfg_i2c_clk);
+
+	val = CONFIG_OMAP_VC_I2C_HS_MCODE <<
+		PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT;
+	/* No HS mode for now */
+	val &= ~PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT;
+	writel(val, &prcm->prm_vc_cfg_i2c_mode);
+}
+
+/**
+ * omap_vc_bypass_send_value() - Send a data using VC Bypass command
+ * @sa:		7 bit I2C slave address of the PMIC
+ * @reg_addr:	I2C register address(8 bit) address in PMIC
+ * @reg_data:	what 8 bit data to write
+ */
+int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data)
+{
+	/*
+	 * Unfortunately we need to loop here instead of a defined time
+	 * use arbitary large value
+	 */
+	u32 timeout = 0xFFFF;
+	u32 reg_val;
+
+	sa &= PRM_VC_VAL_BYPASS_SLAVEADDR_MASK;
+	reg_addr &= PRM_VC_VAL_BYPASS_REGADDR_MASK;
+	reg_data &= PRM_VC_VAL_BYPASS_DATA_MASK;
+
+	/* program VC to send data */
+	reg_val = sa << PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT |
+	    reg_addr << PRM_VC_VAL_BYPASS_REGADDR_SHIFT |
+	    reg_data << PRM_VC_VAL_BYPASS_DATA_SHIFT;
+	writel(reg_val, &prcm->prm_vc_val_bypass);
+
+	/* Signal VC to send data */
+	writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT, &prcm->prm_vc_val_bypass);
+
+	/* Wait on VC to complete transmission */
+	do {
+		reg_val = readl(&prcm->prm_vc_val_bypass) &
+				PRM_VC_VAL_BYPASS_VALID_BIT;
+		if (!reg_val)
+			break;
+
+		sdelay(100);
+	} while (--timeout);
+
+	/* Optional: cleanup PRM_IRQSTATUS_Ax */
+	/* In case we can do something about it in future.. */
+	if (!timeout)
+		return -1;
+
+	/* All good.. */
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 1fee574364..f2e52e9ce1 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -41,6 +41,7 @@
 #include <asm/arch/gpio.h>
 #include <asm/omap_common.h>
 #include <i2c.h>
+#include <linux/compiler.h>
 
 /* Declarations */
 extern omap3_sysinfo sysinfo;
@@ -244,6 +245,17 @@ void s_init(void)
 		mem_init();
 }
 
+/*
+ * Routine: misc_init_r
+ * Description: A basic misc_init_r that just displays the die ID
+ */
+int __weak misc_init_r(void)
+{
+	dieid_num_r();
+
+	return 0;
+}
+
 /******************************************************************************
  * Routine: wait_for_command_complete
  * Description: Wait for posting to finish on watchdog
diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 567817e0ec..09c51f62aa 100644
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -572,6 +572,22 @@ void prcm_init(void)
 	}
 
 	if (get_cpu_family() == CPU_OMAP36XX) {
+		/*
+		 * In warm reset conditions on OMAP36xx/AM/DM37xx
+		 * the rom code incorrectly sets the DPLL4 clock
+		 * input divider to /6.5. Section 3.5.3.3.3.2.1 of
+		 * the AM/DM37x TRM explains that the /6.5 divider
+		 * is used only when the input clock is 13MHz.
+		 *
+		 * If the part is in this cpu family *and* the input
+		 * clock *is not* 13 MHz, then reset the DPLL4 clock
+		 * input divider to /1 as it should never set to /6.5
+		 * in this case.
+		 */
+		if (sys_clkin_sel != 1) /* 13 MHz */
+			/* Bit 8: DPLL4_CLKINP_DIV */
+			sr32(&prm_base->clksrc_ctrl, 8, 1, 0);
+
 		/* Unlock MPU DPLL (slows things down, and needed later) */
 		sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
 		wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
index c42c5ddcc9..ebf69fa17d 100644
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
@@ -31,22 +31,22 @@
 #include <version.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/clocks_omap3.h>
+#include <linux/linkage.h>
 
 _TEXT_BASE:
 	.word	CONFIG_SYS_TEXT_BASE	/* sdram load addr from config.mk */
 
 #ifdef CONFIG_SPL_BUILD
-.global save_boot_params
-save_boot_params:
+ENTRY(save_boot_params)
 	ldr	r4, =omap3_boot_device
 	ldr	r5, [r0, #0x4]
 	and	r5, r5, #0xff
 	str	r5, [r4]
 	bx	lr
+ENDPROC(save_boot_params)
 #endif
 
-.global omap3_gp_romcode_call
-omap3_gp_romcode_call:
+ENTRY(omap3_gp_romcode_call)
 	PUSH {r4-r12, lr} @ Save all registers from ROM code!
 	MOV r12, r0	@ Copy the Service ID in R12
 	MOV r0, r1	@ Copy parameter to R0
@@ -55,6 +55,7 @@ omap3_gp_romcode_call:
 	.word	0xe1600070	@ SMC #0 to enter monitor - hand assembled
 				@ because we use -march=armv5
 	POP {r4-r12, pc}
+ENDPROC(omap3_gp_romcode_call)
 
 /*
  * Funtion for making PPA HAL API calls in secure devices
@@ -62,8 +63,7 @@ omap3_gp_romcode_call:
  *	R0 - Service ID
  *	R1 - paramer list
  */
-.global do_omap3_emu_romcode_call
-do_omap3_emu_romcode_call:
+ENTRY(do_omap3_emu_romcode_call)
 	PUSH {r4-r12, lr} @ Save all registers from ROM code!
 	MOV r12, r0	@ Copy the Secure Service ID in R12
 	MOV r3, r1	@ Copy the pointer to va_list in R3
@@ -76,14 +76,14 @@ do_omap3_emu_romcode_call:
 	.word	0xe1600071	@ SMC #1 to call PPA service - hand assembled
 				@ because we use -march=armv5
 	POP {r4-r12, pc}
+ENDPROC(do_omap3_emu_romcode_call)
 
 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
 /**************************************************************************
  * cpy_clk_code: relocates clock code into SRAM where its safer to execute
  * R1 = SRAM destination address.
  *************************************************************************/
-.global cpy_clk_code
- cpy_clk_code:
+ENTRY(cpy_clk_code)
 	/* Copy DPLL code into SRAM */
 	adr	r0, go_to_speed		/* get addr of clock setting code */
 	mov	r2, #384		/* r2 size to copy (div by 32 bytes) */
@@ -95,6 +95,7 @@ next2:
 	cmp	r0, r2			/* until source end address [r2] */
 	bne	next2
 	mov	pc, lr			/* back to caller */
+ENDPROC(cpy_clk_code)
 
 /* ***************************************************************************
  *  go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
@@ -109,8 +110,7 @@ next2:
  *        L3 when its not in self refresh seems bad for it.  Normally, this
  *	  code runs from flash before SDR is init so that should be ok.
  ****************************************************************************/
-.global go_to_speed
- go_to_speed:
+ENTRY(go_to_speed)
 	stmfd sp!, {r4 - r6}
 
 	/* move into fast relock bypass */
@@ -171,6 +171,7 @@ wait2:
 	nop
 	ldmfd	sp!, {r4 - r6}
 	mov	pc, lr		/* back to caller, locked */
+ENDPROC(go_to_speed)
 
 _go_to_speed: .word go_to_speed
 
@@ -211,8 +212,7 @@ pll_div_val5:
 
 #endif
 
-.globl lowlevel_init
-lowlevel_init:
+ENTRY(lowlevel_init)
 	ldr	sp, SRAM_STACK
 	str	ip, [sp]	/* stash old link register */
 	mov	ip, lr		/* save link reg across call */
@@ -230,6 +230,7 @@ lowlevel_init:
 
 	/* back to arch calling code */
 	mov	pc, lr
+ENDPROC(lowlevel_init)
 
 	/* the literal pools origin */
 	.ltorg
@@ -480,22 +481,22 @@ per_36x_dpll_param:
 .word 26000,    432,   12,     9,      16,     9,     4,      3,      1
 .word 38400,    360,   15,     9,      16,     5,     4,      3,      1
 
-.globl get_36x_mpu_dpll_param
-get_36x_mpu_dpll_param:
+ENTRY(get_36x_mpu_dpll_param)
 	adr	r0, mpu_36x_dpll_param
 	mov	pc, lr
+ENDPROC(get_36x_mpu_dpll_param)
 
-.globl get_36x_iva_dpll_param
-get_36x_iva_dpll_param:
+ENTRY(get_36x_iva_dpll_param)
 	adr	r0, iva_36x_dpll_param
 	mov	pc, lr
+ENDPROC(get_36x_iva_dpll_param)
 
-.globl get_36x_core_dpll_param
-get_36x_core_dpll_param:
+ENTRY(get_36x_core_dpll_param)
 	adr	r0, core_36x_dpll_param
 	mov	pc, lr
+ENDPROC(get_36x_core_dpll_param)
 
-.globl get_36x_per_dpll_param
-get_36x_per_dpll_param:
+ENTRY(get_36x_per_dpll_param)
 	adr	r0, per_36x_dpll_param
 	mov	pc, lr
+ENDPROC(get_36x_per_dpll_param)
diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c
index e2189f729f..c568951a91 100644
--- a/arch/arm/cpu/armv7/omap4/clocks.c
+++ b/arch/arm/cpu/armv7/omap4/clocks.c
@@ -46,8 +46,6 @@
 #define puts(s)
 #endif
 
-#define abs(x) (((x) < 0) ? ((x)*-1) : (x))
-
 struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
 
 const u32 sys_clk_array[8] = {
@@ -275,47 +273,70 @@ void scale_vcores(void)
 {
 	u32 volt, omap_rev;
 
-	setup_sri2c();
+	omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
 
 	omap_rev = omap_revision();
-	/* TPS - supplies vdd_mpu on 4460 */
-	if (omap_rev >= OMAP4460_ES1_0) {
-		volt = 1203;
-		do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt);
-	}
 
 	/*
-	 * VCORE 1
-	 *
-	 * 4430 : supplies vdd_mpu
-	 * Setting a high voltage for Nitro mode as smart reflex is not enabled.
-	 * We use the maximum possible value in the AVS range because the next
-	 * higher voltage in the discrete range (code >= 0b111010) is way too
-	 * high
-	 *
-	 * 4460 : supplies vdd_core
+	 * Scale Voltage rails:
+	 * 1. VDD_CORE
+	 * 3. VDD_MPU
+	 * 3. VDD_IVA
 	 */
 	if (omap_rev < OMAP4460_ES1_0) {
+		/*
+		 * OMAP4430:
+		 * VDD_CORE = TWL6030 VCORE3
+		 * VDD_MPU = TWL6030 VCORE1
+		 * VDD_IVA = TWL6030 VCORE2
+		 */
+		volt = 1200;
+		do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
+
+		/*
+		 * note on VDD_MPU:
+		 * Setting a high voltage for Nitro mode as smart reflex is not
+		 * enabled. We use the maximum possible value in the AVS range
+		 * because the next higher voltage in the discrete range
+		 * (code >= 0b111010) is way too high.
+		 */
 		volt = 1325;
 		do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
+		volt = 1200;
+		do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
+
 	} else {
+		/*
+		 * OMAP4460:
+		 * VDD_CORE = TWL6030 VCORE1
+		 * VDD_MPU = TPS62361
+		 * VDD_IVA = TWL6030 VCORE2
+		 */
 		volt = 1200;
 		do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
+		/* TPS62361 */
+		volt = 1203;
+		do_scale_tps62361(TPS62361_VSEL0_GPIO,
+				  TPS62361_REG_ADDR_SET1, volt);
+		/* VCORE 2 - supplies vdd_iva */
+		volt = 1200;
+		do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
 	}
+}
 
-	/* VCORE 2 - supplies vdd_iva */
-	volt = 1200;
-	do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
+u32 get_offset_code(u32 offset)
+{
+	u32 offset_code, step = 12660; /* 12.66 mV represented in uV */
 
-	/*
-	 * VCORE 3
-	 * 4430 : supplies vdd_core
-	 * 4460 : not connected
-	 */
-	if (omap_rev < OMAP4460_ES1_0) {
-		volt = 1200;
-		do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
-	}
+	if (omap_revision() == OMAP4430_ES1_0)
+		offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
+	else
+		offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
+
+	offset_code = (offset + step - 1) / step;
+
+	/* The code starts at 1 not 0 */
+	return ++offset_code;
 }
 
 /*
@@ -355,7 +376,6 @@ void enable_basic_clocks(void)
 		&prcm->cm_l4per_gptimer2_clkctrl,
 		&prcm->cm_wkup_wdtimer2_clkctrl,
 		&prcm->cm_l4per_uart3_clkctrl,
-		&prcm->cm_l3init_fsusb_clkctrl,
 		&prcm->cm_l3init_hsusbhost_clkctrl,
 		0
 	};
@@ -432,10 +452,6 @@ void enable_non_essential_clocks(void)
 	};
 
 	u32 *const clk_modules_hw_auto_non_essential[] = {
-		&prcm->cm_mpu_m3_mpu_m3_clkctrl,
-		&prcm->cm_ivahd_ivahd_clkctrl,
-		&prcm->cm_ivahd_sl2_clkctrl,
-		&prcm->cm_dsp_dsp_clkctrl,
 		&prcm->cm_l3_2_gpmc_clkctrl,
 		&prcm->cm_l3instr_l3_3_clkctrl,
 		&prcm->cm_l3instr_l3_instr_clkctrl,
@@ -482,7 +498,6 @@ void enable_non_essential_clocks(void)
 		&prcm->cm_dss_dss_clkctrl,
 		&prcm->cm_sgx_sgx_clkctrl,
 		&prcm->cm_l3init_hsusbhost_clkctrl,
-		&prcm->cm_l3init_fsusb_clkctrl,
 		0
 	};
 
diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c
index 91f83205ed..187e93887b 100644
--- a/arch/arm/cpu/armv7/omap4/hwinit.c
+++ b/arch/arm/cpu/armv7/omap4/hwinit.c
@@ -37,7 +37,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
+u32 *const omap_si_rev = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
 
 static const struct gpio_bank gpio_bank_44xx[6] = {
 	{ (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
@@ -59,8 +59,8 @@ void do_io_settings(void)
 	u32 lpddr2io;
 	struct control_lpddr2io_regs *lpddr2io_regs =
 		(struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
-	struct omap4_sys_ctrl_regs *const ctrl =
-		(struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
+	struct omap_sys_ctrl_regs *const ctrl =
+		(struct omap_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
 
 	u32 omap4_rev = omap_revision();
 
@@ -129,40 +129,40 @@ void init_omap_revision(void)
 
 	switch (arm_rev) {
 	case MIDR_CORTEX_A9_R0P1:
-		*omap4_revision = OMAP4430_ES1_0;
+		*omap_si_rev = OMAP4430_ES1_0;
 		break;
 	case MIDR_CORTEX_A9_R1P2:
 		switch (readl(CONTROL_ID_CODE)) {
 		case OMAP4_CONTROL_ID_CODE_ES2_0:
-			*omap4_revision = OMAP4430_ES2_0;
+			*omap_si_rev = OMAP4430_ES2_0;
 			break;
 		case OMAP4_CONTROL_ID_CODE_ES2_1:
-			*omap4_revision = OMAP4430_ES2_1;
+			*omap_si_rev = OMAP4430_ES2_1;
 			break;
 		case OMAP4_CONTROL_ID_CODE_ES2_2:
-			*omap4_revision = OMAP4430_ES2_2;
+			*omap_si_rev = OMAP4430_ES2_2;
 			break;
 		default:
-			*omap4_revision = OMAP4430_ES2_0;
+			*omap_si_rev = OMAP4430_ES2_0;
 			break;
 		}
 		break;
 	case MIDR_CORTEX_A9_R1P3:
-		*omap4_revision = OMAP4430_ES2_3;
+		*omap_si_rev = OMAP4430_ES2_3;
 		break;
 	case MIDR_CORTEX_A9_R2P10:
 		switch (readl(CONTROL_ID_CODE)) {
 		case OMAP4460_CONTROL_ID_CODE_ES1_1:
-			*omap4_revision = OMAP4460_ES1_1;
+			*omap_si_rev = OMAP4460_ES1_1;
 			break;
 		case OMAP4460_CONTROL_ID_CODE_ES1_0:
 		default:
-			*omap4_revision = OMAP4460_ES1_0;
+			*omap_si_rev = OMAP4460_ES1_0;
 			break;
 		}
 		break;
 	default:
-		*omap4_revision = OMAP4430_SILICON_ID_INVALID;
+		*omap_si_rev = OMAP4430_SILICON_ID_INVALID;
 		break;
 	}
 }
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
index a5ec7d3dcc..b5389606b6 100644
--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -89,6 +89,10 @@ const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
 	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
 	.emif_ddr_phy_ctlr_1		= 0x049ff418
 };
+
+/* Dummy registers for OMAP44xx */
+const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
+
 const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
 	.dmm_lisa_map_0 = 0xFF020100,
 	.dmm_lisa_map_1 = 0,
diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile
index f8ca9ac367..9b261c4df2 100644
--- a/arch/arm/cpu/armv7/omap5/Makefile
+++ b/arch/arm/cpu/armv7/omap5/Makefile
@@ -28,7 +28,7 @@ LIB	=  $(obj)lib$(SOC).o
 COBJS	+= hwinit.o
 COBJS	+= clocks.o
 COBJS	+= emif.o
-COBJS	+= sdram_elpida.o
+COBJS	+= sdram.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c
index dd882a202e..1a59f265f7 100644
--- a/arch/arm/cpu/armv7/omap5/clocks.c
+++ b/arch/arm/cpu/armv7/omap5/clocks.c
@@ -88,6 +88,26 @@ static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
 	{1375, 47, 1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
 };
 
+static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
+	{200, 2, 1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{1000, 20, 1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{375, 8, 1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{400, 12, 1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{375, 17, 1, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
+};
+
+static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
+	{200, 2, 2, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{1000, 20, 2, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{375, 8, 2, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{400, 12, 2, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{375, 17, 2, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
+};
+
 static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = {
 	{275, 2, 2, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
@@ -100,24 +120,24 @@ static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = {
 
 static const struct dpll_params
 			core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
-	{266, 2, 1, 5, 8, 4, 62, 5, 5, 7},		/* 12 MHz   */
+	{266, 2, 2, 5, 8, 4, 62, 5, 5, 7},		/* 12 MHz   */
 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{570, 8, 1, 5, 8, 4, 62, 5, 5, 7},		/* 16.8 MHz */
-	{665, 11, 1, 5, 8, 4, 62, 5, 5, 7},		/* 19.2 MHz */
-	{532, 12, 1, 5, 8, 4, 62, 5, 5, 7},		/* 26 MHz   */
+	{570, 8, 2, 5, 8, 4, 62, 5, 5, 7},		/* 16.8 MHz */
+	{665, 11, 2, 5, 8, 4, 62, 5, 5, 7},		/* 19.2 MHz */
+	{532, 12, 2, 5, 8, 4, 62, 5, 5, 7},		/* 26 MHz   */
 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{665, 23, 1, 5, 8, 4, 62, 5, 5, 7}		/* 38.4 MHz */
+	{665, 23, 2, 5, 8, 4, 62, 5, 5, 7}		/* 38.4 MHz */
 };
 
 static const struct dpll_params
 			core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
-	{266, 2, 2, 5, 8, 4, 62, 5, 5, 7},		/* 12 MHz   */
+	{266, 2, 4, 5, 8, 8, 62, 10, 10, 14},		/* 12 MHz   */
 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{570, 8, 2, 5, 8, 4, 62, 5, 5, 7},		/* 16.8 MHz */
-	{665, 11, 2, 5, 8, 4, 62, 5, 5, 7},		/* 19.2 MHz */
-	{532, 12, 2, 5, 8, 4, 62, 5, 5, 7},		/* 26 MHz   */
+	{570, 8, 4, 5, 8, 8, 62, 10, 10, 14},		/* 16.8 MHz */
+	{665, 11, 4, 5, 8, 8, 62, 10, 10, 14},		/* 19.2 MHz */
+	{532, 12, 4, 8, 8, 8, 62, 10, 10, 14},		/* 26 MHz   */
 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{665, 23, 2, 5, 8, 4, 62, 5, 5, 7}		/* 38.4 MHz */
+	{665, 23, 4, 8, 8, 8, 62, 10, 10, 14}		/* 38.4 MHz */
 };
 
 static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
@@ -131,40 +151,40 @@ static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
 };
 
 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
-	{931, 11, -1, -1, 4, 7, -1, -1},	/* 12 MHz   */
-	{931, 12, -1, -1, 4, 7, -1, -1},	/* 13 MHz   */
-	{665, 11, -1, -1, 4, 7, -1, -1},	/* 16.8 MHz */
-	{727, 14, -1, -1, 4, 7, -1, -1},	/* 19.2 MHz */
-	{931, 25, -1, -1, 4, 7, -1, -1},	/* 26 MHz   */
-	{931, 26, -1, -1, 4, 7, -1, -1},	/* 27 MHz   */
-	{412, 16, -1, -1, 4, 7, -1, -1}		/* 38.4 MHz */
+	{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1},	/* 12 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{2011, 28, -1, -1, 5, 6, -1, -1, -1, -1},	/* 16.8 MHz */
+	{1881, 30, -1, -1, 5, 6, -1, -1, -1, -1},	/* 19.2 MHz */
+	{1165, 25, -1, -1, 5, 6, -1, -1, -1, -1},	/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{1972, 64, -1, -1, 5, 6, -1, -1, -1, -1}	/* 38.4 MHz */
 };
 
 /* ABE M & N values with sys_clk as source */
 static const struct dpll_params
 		abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
-	{49, 5, 1, 1, -1, -1, -1, -1},	/* 12 MHz   */
-	{68, 8, 1, 1, -1, -1, -1, -1},	/* 13 MHz   */
-	{35, 5, 1, 1, -1, -1, -1, -1},	/* 16.8 MHz */
-	{46, 8, 1, 1, -1, -1, -1, -1},	/* 19.2 MHz */
-	{34, 8, 1, 1, -1, -1, -1, -1},	/* 26 MHz   */
-	{29, 7, 1, 1, -1, -1, -1, -1},	/* 27 MHz   */
-	{64, 24, 1, 1, -1, -1, -1, -1}	/* 38.4 MHz */
+	{49, 5, 1, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{35, 5, 1, 1, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
+	{46, 8, 1, 1, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
+	{34, 8, 1, 1, -1, -1, -1, -1, -1, -1},		/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{64, 24, 1, 1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
 };
 
 /* ABE M & N values with 32K clock as source */
 static const struct dpll_params abe_dpll_params_32k_196608khz = {
-	750, 0, 1, 1, -1, -1, -1, -1
+	750, 0, 1, 1, -1, -1, -1, -1, -1, -1
 };
 
 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
-	{80, 0, 2, -1, -1, -1, -1, -1},		/* 12 MHz   */
-	{960, 12, 2, -1, -1, -1, -1, -1},	/* 13 MHz   */
-	{400, 6, 2, -1, -1, -1, -1, -1},	/* 16.8 MHz */
-	{50, 0, 2, -1, -1, -1, -1, -1},		/* 19.2 MHz */
-	{480, 12, 2, -1, -1, -1, -1, -1},	/* 26 MHz   */
-	{320, 8, 2, -1, -1, -1, -1, -1},	/* 27 MHz   */
-	{25, 0, 2, -1, -1, -1, -1, -1}		/* 38.4 MHz */
+	{400, 4, 2, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{400, 6, 2, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{400, 7, 2, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{480, 12, 2, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{400, 15, 2, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
 };
 
 void setup_post_dividers(u32 *const base, const struct dpll_params *params)
@@ -193,7 +213,7 @@ void setup_post_dividers(u32 *const base, const struct dpll_params *params)
 const struct dpll_params *get_mpu_dpll_params(void)
 {
 	u32 sysclk_ind = get_sys_clk_index();
-	return &mpu_dpll_params_1100mhz[sysclk_ind];
+	return &mpu_dpll_params_800mhz[sysclk_ind];
 }
 
 const struct dpll_params *get_core_dpll_params(void)
@@ -201,8 +221,7 @@ const struct dpll_params *get_core_dpll_params(void)
 	u32 sysclk_ind = get_sys_clk_index();
 
 	/* Configuring the DDR to be at 532mhz */
-	return &core_dpll_params_2128mhz_ddr266[sysclk_ind];
-
+	return &core_dpll_params_2128mhz_ddr532[sysclk_ind];
 }
 
 const struct dpll_params *get_per_dpll_params(void)
@@ -243,19 +262,33 @@ void scale_vcores(void)
 {
 	u32 volt;
 
-	setup_sri2c();
+	omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
+
+	/* Palmas settings */
+	volt = VDD_CORE;
+	do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt);
 
-	/* Enable 1.22V from TPS for vdd_mpu */
-	volt = 1220;
-	do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt);
+	volt = VDD_MPU;
+	do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt);
 
-	/* VCORE 1 - for vdd_core */
-	volt = 1000;
-	do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
+	volt = VDD_MM;
+	do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt);
 
-	/* VCORE 2 - for vdd_MM */
-	volt = 1125;
-	do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
+}
+
+u32 get_offset_code(u32 volt_offset)
+{
+	u32 offset_code, step = 10000; /* 10 mV represented in uV */
+
+	volt_offset -= PALMAS_SMPS_BASE_VOLT_UV;
+
+	offset_code = (volt_offset + step - 1) / step;
+
+	/*
+	 * Offset codes 1-6 all give the base voltage in Palmas
+	 * Offset code 0 switches OFF the SMPS
+	 */
+	return offset_code + 6;
 }
 
 /*
@@ -306,6 +339,12 @@ void enable_basic_clocks(void)
 	setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
 			HSMMC_CLKCTRL_CLKSEL_MASK);
 
+	/* Set the correct clock dividers for mmc */
+	setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
+			HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
+	setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
+			HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
+
 	/* Select 32KHz clock as the source of GPTIMER1 */
 	setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
 			GPTIMER1_CLKCTRL_CLKSEL_MASK);
@@ -314,6 +353,18 @@ void enable_basic_clocks(void)
 			 clk_modules_hw_auto_essential,
 			 clk_modules_explicit_en_essential,
 			 1);
+
+	/* Select 384Mhz for GPU as its the POR for ES1.0 */
+	setbits_le32(&prcm->cm_sgx_sgx_clkctrl,
+			CLKSEL_GPU_HYD_GCLK_MASK);
+	setbits_le32(&prcm->cm_sgx_sgx_clkctrl,
+			CLKSEL_GPU_CORE_GCLK_MASK);
+
+	/* Enable SCRM OPT clocks for PER and CORE dpll */
+	setbits_le32(&prcm->cm_wkupaon_scrm_clkctrl,
+			OPTFCLKEN_SCRM_PER_MASK);
+	setbits_le32(&prcm->cm_wkupaon_scrm_clkctrl,
+			OPTFCLKEN_SCRM_CORE_MASK);
 }
 
 void enable_basic_uboot_clocks(void)
@@ -371,6 +422,7 @@ void enable_non_essential_clocks(void)
 		&prcm->cm_l3instr_intrconn_wp1_clkctrl,
 		&prcm->cm_l3init_hsi_clkctrl,
 		&prcm->cm_l3init_hsusbtll_clkctrl,
+		&prcm->cm_l4per_hdq1w_clkctrl,
 		0
 	};
 
@@ -393,7 +445,6 @@ void enable_non_essential_clocks(void)
 		&prcm->cm_l4per_gptimer11_clkctrl,
 		&prcm->cm_l4per_gptimer3_clkctrl,
 		&prcm->cm_l4per_gptimer4_clkctrl,
-		&prcm->cm_l4per_hdq1w_clkctrl,
 		&prcm->cm_l4per_mcspi2_clkctrl,
 		&prcm->cm_l4per_mcspi3_clkctrl,
 		&prcm->cm_l4per_mcspi4_clkctrl,
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index fa8e390c17..d01cc81333 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -38,7 +38,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-u32 *const omap5_revision = (u32 *)OMAP5_SRAM_SCRATCH_OMAP5_REV;
+u32 *const omap_si_rev = (u32 *)OMAP5_SRAM_SCRATCH_OMAP5_REV;
 
 static struct gpio_bank gpio_bank_54xx[6] = {
 	{ (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
@@ -57,6 +57,89 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
  */
 void do_io_settings(void)
 {
+	u32 io_settings = 0, mask = 0;
+	struct omap_sys_ctrl_regs *ioregs_base =
+		      (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
+
+	/* Impedance settings EMMC, C2C 1,2, hsi2 */
+	mask = (ds_mask << 2) | (ds_mask << 8) |
+		(ds_mask << 16) | (ds_mask << 18);
+	io_settings = readl(&(ioregs_base->control_smart1io_padconf_0)) &
+				(~mask);
+	io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
+			(ds_45_ohm << 18) | (ds_60_ohm << 2);
+	writel(io_settings, &(ioregs_base->control_smart1io_padconf_0));
+
+	/* Impedance settings Mcspi2 */
+	mask = (ds_mask << 30);
+	io_settings = readl(&(ioregs_base->control_smart1io_padconf_1)) &
+			(~mask);
+	io_settings |= (ds_60_ohm << 30);
+	writel(io_settings, &(ioregs_base->control_smart1io_padconf_1));
+
+	/* Impedance settings C2C 3,4 */
+	mask = (ds_mask << 14) | (ds_mask << 16);
+	io_settings = readl(&(ioregs_base->control_smart1io_padconf_2)) &
+			(~mask);
+	io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
+	writel(io_settings, &(ioregs_base->control_smart1io_padconf_2));
+
+	/* Slew rate settings EMMC, C2C 1,2 */
+	mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
+	io_settings = readl(&(ioregs_base->control_smart2io_padconf_0)) &
+			(~mask);
+	io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
+	writel(io_settings, &(ioregs_base->control_smart2io_padconf_0));
+
+	/* Slew rate settings hsi2, Mcspi2 */
+	mask = (sc_mask << 24) | (sc_mask << 28);
+	io_settings = readl(&(ioregs_base->control_smart2io_padconf_1)) &
+			(~mask);
+	io_settings |= (sc_fast << 28) | (sc_fast << 24);
+	writel(io_settings, &(ioregs_base->control_smart2io_padconf_1));
+
+	/* Slew rate settings C2C 3,4 */
+	mask = (sc_mask << 16) | (sc_mask << 18);
+	io_settings = readl(&(ioregs_base->control_smart2io_padconf_2)) &
+			(~mask);
+	io_settings |= (sc_na << 16) | (sc_na << 18);
+	writel(io_settings, &(ioregs_base->control_smart2io_padconf_2));
+
+	/* impedance and slew rate settings for usb */
+	mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
+		(usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
+	io_settings = readl(&(ioregs_base->control_smart3io_padconf_1)) &
+			(~mask);
+	io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
+		       (ds_60_ohm << 23) | (sc_fast << 20) |
+		       (sc_fast << 17) | (sc_fast << 14);
+	writel(io_settings, &(ioregs_base->control_smart3io_padconf_1));
+
+	/* LPDDR2 io settings */
+	writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+					&(ioregs_base->control_ddrch1_0));
+	writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+					&(ioregs_base->control_ddrch1_1));
+	writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+					&(ioregs_base->control_ddrch2_0));
+	writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+					&(ioregs_base->control_ddrch2_1));
+	writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
+					&(ioregs_base->control_lpddr2ch1_0));
+	writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
+					&(ioregs_base->control_lpddr2ch1_1));
+	writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
+					&(ioregs_base->control_ddrio_0));
+	writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
+					&(ioregs_base->control_ddrio_1));
+	writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
+					&(ioregs_base->control_ddrio_2));
+
+	/* Efuse settings */
+	writel(EFUSE_1, &(ioregs_base->control_efuse_1));
+	writel(EFUSE_2, &(ioregs_base->control_efuse_2));
+	writel(EFUSE_3, &(ioregs_base->control_efuse_3));
+	writel(EFUSE_4, &(ioregs_base->control_efuse_4));
 }
 #endif
 
@@ -71,8 +154,23 @@ void init_omap_revision(void)
 
 	switch (rev) {
 	case MIDR_CORTEX_A15_R0P0:
-		*omap5_revision = OMAP5430_ES1_0;
+		*omap_si_rev = OMAP5430_ES1_0;
+		break;
 	default:
-		*omap5_revision = OMAP5430_SILICON_ID_INVALID;
+		*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
 	}
 }
+
+void reset_cpu(ulong ignored)
+{
+	u32 omap_rev = omap_revision();
+
+	/*
+	 * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
+	 * So use cold reset in case instead.
+	 */
+	if (omap_rev == OMAP5430_ES1_0)
+		writel(PRM_RSTCTRL_RESET << 0x1, PRM_RSTCTRL);
+	else
+		writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
+}
diff --git a/arch/arm/cpu/armv7/omap5/sdram_elpida.c b/arch/arm/cpu/armv7/omap5/sdram.c
index ad198e6d1b..b2b5753e89 100644
--- a/arch/arm/cpu/armv7/omap5/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -1,5 +1,5 @@
 /*
- * Timing and Organization details of the Elpida parts used in OMAP5
+ * Timing and Organization details of the ddr device parts used in OMAP5
  * EVM
  *
  * (C) Copyright 2010
@@ -48,31 +48,76 @@
  */
 
 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-
-const struct emif_regs emif_regs_elpida_532_mhz_1cs = {
-	.sdram_config_init		= 0x80801aB2,
-	.sdram_config			= 0x808022B2,
+const struct emif_regs emif_regs_532_mhz_2cs = {
+	.sdram_config_init		= 0x80800EBA,
+	.sdram_config			= 0x808022BA,
 	.ref_ctrl			= 0x0000081A,
 	.sdram_tim1			= 0x772F6873,
-	.sdram_tim2			= 0x304A129A,
-	.sdram_tim3			= 0x02F7E45F,
+	.sdram_tim2			= 0x304a129a,
+	.sdram_tim3			= 0x02f7e45f,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x000b3215,
+	.temp_alert_config		= 0x08000a05,
+	.emif_ddr_phy_ctlr_1_init	= 0x0E28420d,
+	.emif_ddr_phy_ctlr_1		= 0x0E28420d,
+	.emif_ddr_ext_phy_ctrl_1	= 0x04020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x28C518A3,
+	.emif_ddr_ext_phy_ctrl_3	= 0x518A3146,
+	.emif_ddr_ext_phy_ctrl_4	= 0x0014628C,
+	.emif_ddr_ext_phy_ctrl_5	= 0x04010040
+};
+
+const struct emif_regs emif_regs_266_mhz_2cs = {
+	.sdram_config_init		= 0x80800EBA,
+	.sdram_config			= 0x808022BA,
+	.ref_ctrl			= 0x0000040D,
+	.sdram_tim1			= 0x2A86B419,
+	.sdram_tim2			= 0x1025094A,
+	.sdram_tim3			= 0x026BA22F,
 	.read_idle_ctrl			= 0x00050000,
-	.zq_config			= 0x000B3215,
-	.temp_alert_config		= 0x08000A05,
-	.emif_ddr_phy_ctlr_1_init	= 0x0E38200D,
-	.emif_ddr_phy_ctlr_1		= 0x0E38200D
+	.zq_config			= 0x000b3215,
+	.temp_alert_config		= 0x08000a05,
+	.emif_ddr_phy_ctlr_1_init	= 0x0E28420d,
+	.emif_ddr_phy_ctlr_1		= 0x0E28420d,
+	.emif_ddr_ext_phy_ctrl_1	= 0x04020080,
+	.emif_ddr_ext_phy_ctrl_2	= 0x0A414829,
+	.emif_ddr_ext_phy_ctrl_3	= 0x14829052,
+	.emif_ddr_ext_phy_ctrl_4	= 0x000520A4,
+	.emif_ddr_ext_phy_ctrl_5	= 0x04010040
 };
 
-const struct dmm_lisa_map_regs lisa_map_4G_x_1_x_2 = {
-	.dmm_lisa_map_0 = 0xFF020100,
+const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
+	.dmm_lisa_map_0 = 0x0,
 	.dmm_lisa_map_1 = 0,
 	.dmm_lisa_map_2 = 0,
-	.dmm_lisa_map_3 = 0x80640300
+	.dmm_lisa_map_3 = 0x80740300
+};
+
+const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+	0x01004010,
+	0x00001004,
+	0x04010040,
+	0x01004010,
+	0x00001004,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x80080080,
+	0x00800800,
+	0x08102040,
+	0x00000001,
+	0x540A8150,
+	0xA81502a0,
+	0x002A0540,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000077
 };
 
 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 {
-	*regs = &emif_regs_elpida_532_mhz_1cs;
+	*regs = &emif_regs_532_mhz_2cs;
 }
 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 	__attribute__((weak, alias("emif_get_reg_dump_sdp")));
@@ -80,7 +125,7 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 						**dmm_lisa_regs)
 {
-	*dmm_lisa_regs = &lisa_map_4G_x_1_x_2;
+	*dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
 }
 
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
@@ -88,11 +133,11 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 
 #else
 
-static const struct lpddr2_device_details elpida_4G_S4_details = {
+static const struct lpddr2_device_details dev_4G_S4_details = {
 	.type		= LPDDR2_TYPE_S4,
 	.density	= LPDDR2_DENSITY_4Gb,
 	.io_width	= LPDDR2_IO_WIDTH_32,
-	.manufacturer	= LPDDR2_MANUFACTURER_ELPIDA
+	.manufacturer	= LPDDR2_MANUFACTURER_SAMSUNG
 };
 
 static void emif_get_device_details_sdp(u32 emif_nr,
@@ -100,10 +145,8 @@ static void emif_get_device_details_sdp(u32 emif_nr,
 		struct lpddr2_device_details *cs1_device_details)
 {
 	/* EMIF1 & EMIF2 have identical configuration */
-	*cs0_device_details = elpida_4G_S4_details;
-
-	/* Nothing is conected on cs1 */
-	cs1_device_details = NULL;
+	*cs0_device_details = dev_4G_S4_details;
+	*cs1_device_details = dev_4G_S4_details;
 }
 
 void emif_get_device_details(u32 emif_nr,
@@ -137,7 +180,7 @@ static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
 	.tFAW		= 50
 };
 
-static const struct lpddr2_min_tck min_tck_elpida = {
+static const struct lpddr2_min_tck min_tck = {
 	.tRL		= 3,
 	.tRP_AB		= 3,
 	.tRCD		= 3,
@@ -152,13 +195,13 @@ static const struct lpddr2_min_tck min_tck_elpida = {
 	.tFAW		= 8
 };
 
-static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
+static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
 	&timings_jedec_532_mhz
 };
 
-static const struct lpddr2_device_timings elpida_4G_S4_timings = {
-	.ac_timings	= elpida_ac_timings,
-	.min_tck	= &min_tck_elpida,
+static const struct lpddr2_device_timings dev_4G_S4_timings = {
+	.ac_timings	= ac_timings,
+	.min_tck	= &min_tck,
 };
 
 void emif_get_device_timings_sdp(u32 emif_nr,
@@ -166,8 +209,8 @@ void emif_get_device_timings_sdp(u32 emif_nr,
 		const struct lpddr2_device_timings **cs1_device_timings)
 {
 	/* Identical devices on EMIF1 & EMIF2 */
-	*cs0_device_timings = &elpida_4G_S4_timings;
-	*cs1_device_timings = NULL;
+	*cs0_device_timings = &dev_4G_S4_timings;
+	*cs1_device_timings = &dev_4G_S4_timings;
 }
 
 void emif_get_device_timings(u32 emif_nr,
diff --git a/arch/arm/cpu/armv7/rda/Makefile b/arch/arm/cpu/armv7/rda/Makefile
new file mode 100644
index 0000000000..b09e7b48ca
--- /dev/null
+++ b/arch/arm/cpu/armv7/rda/Makefile
@@ -0,0 +1,62 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS-y	+= timer.o serial.o ifc.o cpu.o rda_sys.o ispi.o
+COBJS-$(CONFIG_SPL_SIGNATURE_CHECK_IMAGE) += rda_crypto.o rda_romapi.o
+
+ifdef CONFIG_SPL_BUILD
+COBJS-y	+= spl.o
+COBJS-$(CONFIG_SPL_XMODEM_LOAD) += xmodem_boot.o
+else
+ifdef CONFIG_MDCOM
+COBJS-y	+= mdcom.o
+endif
+endif
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS	+= lowlevel_init.o
+endif
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/rda/config.mk b/arch/arm/cpu/armv7/rda/config.mk
new file mode 100644
index 0000000000..79fde41c14
--- /dev/null
+++ b/arch/arm/cpu/armv7/rda/config.mk
@@ -0,0 +1,95 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+include $(TOPDIR)/slt.mk
+include $(TOPDIR)/customer.mk
+include $(TOPDIR)/board/$(SOC)/$(BOARD)/config.mk
+
+image_flags :=
+
+ifneq ($(TARGET_SYSTEMIMAGE_USE_UBIFS),)
+image_flags += -DUBIFS_SYSTEM_IMAGE
+endif
+
+ifneq ($(TARGET_USERIMAGES_USE_UBIFS),)
+image_flags += -DUBIFS_USER_IMAGES
+endif
+
+ifneq ($(TARGET_SYSTEMIMAGE_USE_EXT4),)
+image_flags += -DEXTFS_SYSTEM_IMAGE
+endif
+
+ifneq ($(TARGET_USERIMAGES_USE_EXT4),)
+image_flags += -DEXTFS_USER_IMAGES
+endif
+
+image_flags += -DSPL_APPENDING_TO=$(SPL_APPENDING_TO)
+
+pdl_flags :=
+ifeq ($(pdl), 1)
+pdl_flags += -DCONFIG_RDA_PDL
+endif
+
+nand_flags :=
+ifneq ($(BOARD_NAND_PAGE_SIZE),)
+nand_flags += -DNAND_PAGE_SIZE=$(BOARD_NAND_PAGE_SIZE)
+else
+nand_flags += -DNAND_PAGE_SIZE=4096
+endif
+ifneq ($(BOARD_FLASH_BLOCK_SIZE),)
+nand_flags += -DNAND_BLOCK_SIZE=$(BOARD_FLASH_BLOCK_SIZE)
+else
+nand_flags += -DNAND_BLOCK_SIZE=262144
+endif
+ifneq ($(BOARD_NAND_SPARE_SIZE),)
+nand_flags += -DNAND_SPARE_SIZE=$(BOARD_NAND_SPARE_SIZE)
+else
+nand_flags += -DNAND_SPARE_SIZE=218
+endif
+ifneq ($(BOARD_NAND_ECCMSGLEN),)
+nand_flags += -DNAND_ECCMSGLEN=$(BOARD_NAND_ECCMSGLEN)
+else
+nand_flags += -DNAND_ECCMSGLEN=1024
+endif
+ifneq ($(BOARD_NAND_ECCBITS),)
+nand_flags += -DNAND_ECCBITS=$(BOARD_NAND_ECCBITS)
+else
+nand_flags += -DNAND_ECCBITS=24
+endif
+ifneq ($(BOARD_NAND_OOB_SIZE),)
+nand_flags += -DNAND_OOBSIZE=$(BOARD_NAND_OOB_SIZE)
+else
+nand_flags += -DNAND_OOBSIZE=32
+endif
+
+build_variant_flags :=
+
+ifneq ($(UBOOT_VARIANT), user)
+build_variant_flags += -DCONFIG_UBOOT_VARIANT_DEBUG
+endif
+
+ifneq ($(BUILD_DISPLAY_ID),)
+build_variant_flags += -DBUILD_DISPLAY_ID="\"$(BUILD_DISPLAY_ID)\""
+endif
+
+PLATFORM_CPPFLAGS += $(image_flags) $(pdl_flags) $(build_variant_flags) $(nand_flags)
+
diff --git a/arch/arm/cpu/armv7/rda/cpu.c b/arch/arm/cpu/armv7/rda/cpu.c
new file mode 100644
index 0000000000..e040455aa6
--- /dev/null
+++ b/arch/arm/cpu/armv7/rda/cpu.c
@@ -0,0 +1,87 @@
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+void enable_neon(void)
+{
+	/* enable cp10 and cp11 */
+	uint32_t val;
+
+	__asm__ volatile("mrc	p15, 0, %0, c1, c1, 2" : "=r" (val));
+	printf("CPU:   p15-c1-c1 (NSACR): 0x%08x", val);
+	val |= (3<<10);
+	val &= ~(3<<14);
+	__asm__ volatile("mcr	p15, 0, %0, c1, c1, 2" :: "r" (val));
+	printf(" -> 0x%08x\n", val);
+
+	__asm__ volatile("mrc	p15, 0, %0, c1, c0, 2" : "=r" (val));
+	printf("CPU:   p15-c1-c0 (CPACR): 0x%08x", val);
+	val |= (3<<22)|(3<<20);
+	__asm__ volatile("mcr	p15, 0, %0, c1, c0, 2" :: "r" (val));
+	printf(" -> 0x%08x\n", val);
+
+	/* set enable bit in fpexc */
+	val = (1<<30);
+	__asm__ volatile("mcr  p10, 7, %0, c8, c0, 0" :: "r" (val));
+}
+
+#if (defined(CONFIG_MACH_RDA8810E) \
+||defined(CONFIG_MACH_RDA8820) \
+||defined(CONFIG_MACH_RDA8810H) \
+||defined(CONFIG_MACH_RDA8850E))
+/* SMP MACHs */
+void smp_setup(void)
+{
+	asm volatile(
+		"mrc    p15, 0, r0, c1, c0, 1\n"
+		"orr    r0, r0, #0x40\n"
+		"mcr    p15, 0, r0, c1, c0, 1\n");
+}
+#endif
+
+void enable_caches(void)
+{
+#if (defined(CONFIG_MACH_RDA8810E) \
+||defined(CONFIG_MACH_RDA8820) \
+||defined(CONFIG_MACH_RDA8810H) \
+||defined(CONFIG_MACH_RDA8850E))
+	printf("CPU: enable smp\n");
+	smp_setup();
+#endif
+#ifndef CONFIG_SYS_ICACHE_OFF
+	printf("CPU: enable instruction caches\n");
+	icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+	printf("CPU: enable data caches\n");
+	dcache_enable();
+#endif
+#ifndef CONFIG_SYS_NEON_OFF
+	printf("CPU: enable neon\n");
+	enable_neon();
+#endif
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+/* Print CPU information */
+int print_cpuinfo(void)
+{
+#if defined(CONFIG_MACH_RDAARM926EJS)
+	printf("RDAARM926EJS FPGA\n");
+#elif defined(CONFIG_MACH_RDA8810)
+	printf("RDA8810 SoC\n");
+#elif defined(CONFIG_MACH_RDA8810E)
+	printf("RDA8810E SoC\n");
+#elif defined(CONFIG_MACH_RDA8820)
+	printf("RDA8820 SoC\n");
+#elif defined(CONFIG_MACH_RDA8850)
+	printf("RDA8850 SoC\n");
+#elif defined(CONFIG_MACH_RDA8850E)
+	printf("RDA8850E SoC\n");
+#elif defined(CONFIG_MACH_RDA8810H)
+	printf("RDA8810H SoC\n");
+#else
+#error "Unknown RDA CPU"
+#endif
+	return 0;
+}
+#endif	/* CONFIG_DISPLAY_CPUINFO */ 
diff --git a/arch/arm/cpu/armv7/rda/ifc.c b/arch/arm/cpu/armv7/rda/ifc.c
new file mode 100644
index 0000000000..f280cac0af
--- /dev/null
+++ b/arch/arm/cpu/armv7/rda/ifc.c
@@ -0,0 +1,172 @@
+#include "common.h"
+#include <errno.h>
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/reg_ifc.h>
+#include <asm/arch/ifc.h>
+
+#undef assert
+#ifdef DEBUG
+#include <assert.h>
+#else
+#define assert(...)
+#endif 
+
+#define HAL_TRACE(...)
+
+HAL_IFC_REQUEST_ID_T g_halModuleIfcChannelOwner[SYS_IFC_STD_CHAN_NB];
+
+void hal_IfcOpen(void)
+{
+    u8 channel;
+
+    // Initialize the channel table with unknown requests.
+    for (channel = 0; channel < SYS_IFC_STD_CHAN_NB; channel++)
+    {
+        g_halModuleIfcChannelOwner[channel] = HAL_IFC_NO_REQWEST;
+    }
+}
+
+HAL_IFC_REQUEST_ID_T hal_IfcGetOwner(u8 channel)
+{
+    // Here, we consider the transfer as previously finished.
+    if (channel == HAL_UNKNOWN_CHANNEL) return HAL_IFC_NO_REQWEST;
+
+    // Channel number too big.
+    assert(channel < SYS_IFC_STD_CHAN_NB, channel);
+
+    return g_halModuleIfcChannelOwner[channel];
+}
+
+void hal_IfcChannelRelease(HAL_IFC_REQUEST_ID_T requestId, u8 channel)
+{
+    //u32 status;
+
+    // Here, we consider the transfer as previously finished.
+    if (channel == HAL_UNKNOWN_CHANNEL) return;
+
+    // Channel number too big.
+    assert(channel < SYS_IFC_STD_CHAN_NB, channel);
+
+    //status = hal_SysEnterCriticalSection();
+    if (g_halModuleIfcChannelOwner[channel] == requestId)
+    {
+        // disable this channel
+        hwp_sysIfc->std_ch[channel].control = (SYS_IFC_REQ_SRC(requestId)
+                                            | SYS_IFC_CH_RD_HW_EXCH
+                                            | SYS_IFC_DISABLE);
+        // read the status of this channel
+        if (hwp_sysIfc->std_ch[channel].status & SYS_IFC_ENABLE)
+        {
+            HAL_TRACE(_HAL | TSTDOUT,0," Strange, the released channel not disabled yet");
+        }
+        // Write the TC to 0 for next time the channel is re-enabled
+        hwp_sysIfc->std_ch[channel].tc =  0;
+    }
+    //hal_SysExitCriticalSection(status);
+}
+
+void hal_IfcChannelFlush(HAL_IFC_REQUEST_ID_T requestId, u8 channel)
+{
+    //u32 status;
+
+    // Here, we consider the transfer as previously finished.
+    if (channel == HAL_UNKNOWN_CHANNEL) return;
+
+    // Channel number too big.
+    assert(channel < SYS_IFC_STD_CHAN_NB, channel);
+
+    // Check that the channel is really owned by the peripheral
+    // which is doing the request, it could have been release
+    // automatically or by an IRQ handler.
+    //status = hal_SysEnterCriticalSection();
+    if (g_halModuleIfcChannelOwner[channel] == requestId)
+    {
+        // If fifo not empty, flush it.
+        if ( !(hwp_sysIfc->std_ch[channel].status & SYS_IFC_FIFO_EMPTY) )
+        {
+            hwp_sysIfc->std_ch[channel].control = 
+                hwp_sysIfc->std_ch[channel].control | SYS_IFC_FLUSH;
+        }
+    }
+    //hal_SysExitCriticalSection(status);
+}
+
+BOOL hal_IfcChannelIsFifoEmpty(HAL_IFC_REQUEST_ID_T requestId, u8 channel)
+{
+    //u32 status;
+    BOOL fifoIsEmpty = TRUE;
+    
+    // Here, we consider the transfer as previously finished.
+    if (channel == HAL_UNKNOWN_CHANNEL) return fifoIsEmpty;
+
+    // Channel number too big.
+    assert(channel < SYS_IFC_STD_CHAN_NB, channel);
+
+    // Check that the channel is really owned by the peripheral
+    // which is doing the request, it could have been release
+    // automatically or by an IRQ handler.
+    //status = hal_SysEnterCriticalSection();
+    if (g_halModuleIfcChannelOwner[channel] == requestId)
+    {
+        fifoIsEmpty =
+            (FALSE != (hwp_sysIfc->std_ch[channel].status & SYS_IFC_FIFO_EMPTY));
+    }
+    //hal_SysExitCriticalSection(status);
+
+    return fifoIsEmpty;
+}
+
+u8 hal_IfcTransferStart(HAL_IFC_REQUEST_ID_T requestId, u8* memStartAddr, u32 xferSize, HAL_IFC_MODE_T ifcMode)
+{
+    //u32 status = hal_SysEnterCriticalSection();
+    u8 channel;
+    u8 i;
+
+    // Check buffer alignment depending on the mode
+    if (ifcMode != HAL_IFC_SIZE_8_MODE_MANUAL && ifcMode != HAL_IFC_SIZE_8_MODE_AUTO)
+    {
+        // Then ifcMode == HAL_IFC_SIZE_32, check word alignment
+        assert(((u32)memStartAddr%4) == 0,
+            "HAL IFC: 32 bits transfer misaligned 0x@%08X", memStartAddr);
+    }
+    else
+    {
+        // ifcMode == HAL_IFC_SIZE_8, nothing to check
+    }
+
+    // Check the requested id is not currently already used.
+    for (i = 0; i < SYS_IFC_STD_CHAN_NB ; i++)
+    {
+        if (GET_BITFIELD(hwp_sysIfc->std_ch[i].control, SYS_IFC_REQ_SRC) == requestId)
+        {
+            // This channel is or was used for the requestId request.
+            // Check it is still in use.
+            assert((hwp_sysIfc->std_ch[i].status & SYS_IFC_ENABLE) == 0,
+                    "HAL: Attempt to use the IFC to deal with a %d"
+                    " request still active on channel %d", requestId, i);
+        }
+    }
+
+    channel = SYS_IFC_CH_TO_USE(hwp_sysIfc->get_ch) ;
+
+    if (channel >= SYS_IFC_STD_CHAN_NB)
+    {
+        serial_puts("HAL_UNKNOWN_CHANNEL\n");
+        //hal_SysExitCriticalSection(status);
+        return HAL_UNKNOWN_CHANNEL;
+    }
+
+    g_halModuleIfcChannelOwner[channel]     = requestId;
+    hwp_sysIfc->std_ch[channel].start_addr  =  (u32) memStartAddr;
+    hwp_sysIfc->std_ch[channel].tc          =  xferSize;
+    hwp_sysIfc->std_ch[channel].control     = (SYS_IFC_REQ_SRC(requestId) 
+                                            | ifcMode
+                                            | SYS_IFC_CH_RD_HW_EXCH
+                                            | SYS_IFC_ENABLE);
+
+    //hal_SysExitCriticalSection(status);
+    return channel;
+}
+
diff --git a/arch/arm/cpu/armv7/rda/ispi.c b/arch/arm/cpu/armv7/rda/ispi.c
new file mode 100644
index 0000000000..d466ef0ced
--- /dev/null
+++ b/arch/arm/cpu/armv7/rda/ispi.c
@@ -0,0 +1,314 @@
+/*
+ * (C) Copyright 2013
+ * RDA Microelectronics Inc.
+ *
+ * Derived from drivers/spi/rda_ispi.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+#include <common.h>
+#include <linux/types.h>
+#include <asm/arch/reg_spi.h>
+#include <asm/arch/ispi.h>
+
+#ifdef CONFIG_MACH_RDA8850E 
+#include <asm/arch/reg_rf_spi.h>
+
+#define RDA6220_ADDR_MASK               0xFF
+#define RDA6220_ADDR_OFFSET             23
+#define RDA6220_DATA_MASK               0xFFFF
+#define RDA6220_DATA_OFFSET             7
+
+#define RDA6220_WRITE_FMT(addr, data) (((addr & RDA6220_ADDR_MASK) << RDA6220_ADDR_OFFSET) |\
+        ((data & RDA6220_DATA_MASK) << RDA6220_DATA_OFFSET))
+
+#define RDA6220_READ_FMT(addr, data)  ( ((addr & RDA6220_ADDR_MASK) << RDA6220_ADDR_OFFSET)|\
+        ((data & RDA6220_DATA_MASK) << RDA6220_DATA_OFFSET)|\
+        1<<31);
+
+void modem_RfspiOpen(void)
+{
+	//  Setter
+	hwp_rfSpi->Ctrl = 0x8fd82e45;
+
+	// To remove the "FORCE ZERO" in case of low-active CS
+	hwp_rfSpi->Command = 0;
+	hwp_rfSpi->Divider = RF_SPI_DIVIDER(23);
+}
+
+void modem_rf_spiWrite(const u8 *Cmd, u32 CmdSize)
+{
+	u32 loop=0;
+
+	// Flush the Tx fifo
+	hwp_rfSpi->Command = RF_SPI_FLUSH_CMD_FIFO | RF_SPI_FLUSH_RX_FIFO;
+	for (loop=0; loop<CmdSize; loop++)
+	{
+	    hwp_rfSpi->Cmd_Data = Cmd[loop];
+	}
+	// Set the cmd size
+	hwp_rfSpi->Cmd_Size = RF_SPI_CMD_SIZE(CmdSize);
+
+	// And send the command
+	hwp_rfSpi->Command = RF_SPI_SEND_CMD;
+
+	// Wait for the SPI to start - at least one byte has been sent
+	while(GET_BITFIELD(hwp_rfSpi->Status, RF_SPI_CMD_DATA_LEVEL) >= CmdSize);
+	// Wait for the SPI to finish
+	while((hwp_rfSpi->Status & RF_SPI_ACTIVE_STATUS) != 0);
+}
+
+
+void modem_RfspiWrite(const u8 addr, u32 data)
+{
+	u8 cmd[4] = {0};
+	u32 cmd_word = RDA6220_WRITE_FMT(addr, data);
+
+	cmd[0] = (cmd_word >> 24) & 0xff;
+	cmd[1] = (cmd_word >>16) & 0xff;
+	cmd[2] = (cmd_word >> 8) & 0xff;
+	cmd[3] = (cmd_word >> 0) & 0xff;
+
+	modem_rf_spiWrite(cmd, 4);
+}
+
+void modem_RfspiInit_624M(void)
+{
+	modem_RfspiOpen();
+
+	modem_RfspiWrite(0x30, 0x5182);
+
+	mdelay(10);  // delay 10 ms
+	modem_RfspiWrite(0x30, 0x5187);
+	mdelay(10);  // delay 10 ms
+	//  xtal setting
+	modem_RfspiWrite(0xb0, 0xe404);
+	modem_RfspiWrite(0xb8, 0x1800);
+	modem_RfspiWrite(0xba, 0x0401);
+	modem_RfspiWrite(0xc0, 0x0008);
+	modem_RfspiWrite(0xfe, 0x4000);
+	modem_RfspiWrite(0x10, 0x0880);
+	modem_RfspiWrite(0x20, 0x03e4);
+	modem_RfspiWrite(0x22, 0x0488);
+	modem_RfspiWrite(0xe8, 0x1000);
+	modem_RfspiWrite(0xe6, 0x0000);
+	modem_RfspiWrite(0xe4, 0x0c00);
+	modem_RfspiWrite(0xe4, 0x8c00);
+	modem_RfspiWrite(0xfe, 0x0000);
+	modem_RfspiWrite(0x4e, 0xe538);
+	modem_RfspiWrite(0x4c, 0x04b9);
+	modem_RfspiWrite(0x4c, 0x84b9);
+
+}
+
+void modem_8850eeco2_RfspiInit_624M(void)
+{
+	modem_RfspiOpen();
+
+	modem_RfspiWrite(0x30, 0x5182);
+
+	mdelay(10);  // delay 10 ms
+	modem_RfspiWrite(0x30, 0x5187);
+	mdelay(10);  // delay 10 ms
+	//  xtal setting
+
+	modem_RfspiWrite(0xfe, 0x4000);
+	modem_RfspiWrite(0x10, 0x0880);
+	modem_RfspiWrite(0xfe, 0x0000);
+}
+#endif
+
+static HWP_SPI_T *hwp_ispi = hwp_spi3;
+
+void ispi_open(int modemSpi)
+{
+	u32 cfgReg = 0;
+	u32 ctrlReg = 0;
+
+	// spi_clk_freq = APB2 / ((div+1)*2)
+	// the maximum clock frequency is 7MHz~8MHz
+	// the spi clock frequency is 5MHz when div is 0x13
+	cfgReg = 0x130003;
+	ctrlReg = 0x2019d821;
+
+	if (modemSpi)
+		hwp_ispi = hwp_mspi2;
+	else
+		hwp_ispi = hwp_spi3;
+
+	// Activate the ISPI.
+	hwp_ispi->cfg = cfgReg;
+	hwp_ispi->ctrl = ctrlReg;
+
+	// No IRQ.
+	hwp_ispi->irq = 0;
+}
+
+static u8 ispi_tx_fifo_avail(void)
+{
+	u8 freeRoom;
+
+	// Get avail level.
+	freeRoom = GET_BITFIELD(hwp_ispi->status, SPI_TX_SPACE);
+
+	return freeRoom;
+}
+
+static int ispi_tx_finished(void)
+{
+	u32 spiStatus;
+	spiStatus = hwp_ispi->status;
+
+	// If ISPI FSM is active and the TX Fifo is empty
+	// (ie available space == Fifo size), the tf is not done
+	if ((!(hwp_ispi->status & SPI_ACTIVE_STATUS))
+	    && (SPI_TX_FIFO_SIZE == GET_BITFIELD(spiStatus, SPI_TX_SPACE))) {
+		return TRUE;
+	} else {
+		return FALSE;
+	}
+}
+
+static u32 ispi_send_data(u32 csId, u32 data, int read)
+{
+	u32 freeRoom;
+
+	// Clear data upper bit to only keep the data frame.
+	u32 reg = data & ~(SPI_CS_MASK | SPI_READ_ENA_MASK);
+
+	// Add CS and read mode bit
+	reg |= SPI_CS(csId) | (read ? SPI_READ_ENA : 0);
+
+	// Enter critical section.
+	//u32 status = hwp_sysIrq->SC;
+
+	// Check FIFO availability.
+	freeRoom = GET_BITFIELD(hwp_ispi->status, SPI_TX_SPACE);
+
+	if (freeRoom > 0) {
+		// Write data.
+		hwp_ispi->rxtx_buffer = reg;
+
+		// Exit critical section.
+		//hwp_sysIrq->SC = status;
+		return 1;
+	} else {
+		// Exit critical section.
+		//hwp_sysIrq->SC = status;
+		return 0;
+	}
+}
+
+static u32 ispi_get_data(u32 * recData)
+{
+	u32 nbAvailable;
+
+	// Enter critical section.
+	//u32 status = hwp_sysIrq->SC;
+
+	nbAvailable = GET_BITFIELD(hwp_ispi->status, SPI_RX_LEVEL);
+
+	if (nbAvailable > 0) {
+		*recData = hwp_ispi->rxtx_buffer;
+
+		// Exit critical section.
+		//hwp_sysIrq->SC = status;
+		return 1;
+	} else {
+		// Exit critical section.
+		//hwp_sysIrq->SC = status;
+		return 0;
+	}
+}
+
+void ispi_reg_write(u32 regIdx, u32 value)
+{
+	u32 wrData;
+
+	wrData = (0 << 25) | ((regIdx & 0x1ff) << 16) | (value & 0xffff);
+
+	while (ispi_tx_fifo_avail() < 1 ||
+	       ispi_send_data(0, wrData, FALSE) == 0) ;
+
+	//wait until any previous transfers have ended
+	while (!ispi_tx_finished()) ;
+}
+
+u32 ispi_reg_read(u32 regIdx)
+{
+	u32 wrData, rdData = 0;
+	u32 count;
+
+	wrData = (1 << 25) | ((regIdx & 0x1ff) << 16) | 0;
+
+	while (ispi_tx_fifo_avail() < 1 ||
+	       ispi_send_data(0, wrData, TRUE) == 0) ;
+
+	//wait until any previous transfers have ended
+	while (!ispi_tx_finished()) ;
+
+	count = ispi_get_data(&rdData);
+	if (1 != count)
+		serial_puts("ABB ISPI count err!");
+
+	rdData &= 0xffff;
+
+	return rdData;
+}
+
+u16 rda_read_efuse(int page_index)
+{
+	u16 rvalue, wvalue;
+
+	ispi_open(1);
+
+	wvalue = 0x2e0 | page_index;
+	pmu_reg_write(0x51, wvalue);
+	udelay(2000);
+	wvalue = 0x2f0 | page_index;
+	pmu_reg_write(0x51, wvalue);
+	rvalue = pmu_reg_read(0x52);
+	pmu_reg_write(0x51, 0x0200);
+
+	ispi_open(0);
+	return rvalue;
+}
+
+#ifdef EFUSE_DUMP
+void dump_efuse(void)
+{
+	u16 rvalue,wvalue;
+	int i;
+
+	ispi_open(1);
+
+	for(i = 0;i<16;i++){
+		wvalue = 0x2e0 | i;
+		pmu_reg_write(0x51, wvalue);
+		udelay(2000);
+		wvalue = 0x2f0 | i;
+		pmu_reg_write(0x51, wvalue);
+		rvalue = pmu_reg_read(0x52);
+		pmu_reg_write(0x51, 0x0200);
+
+		printf("page%d = %d \n", i, rvalue);
+	}
+	ispi_open(0);
+}
+#endif
diff --git a/arch/arm/cpu/armv7/rda/mdcom.c b/arch/arm/cpu/armv7/rda/mdcom.c
new file mode 100644
index 0000000000..8bb9e082c4
--- /dev/null
+++ b/arch/arm/cpu/armv7/rda/mdcom.c
@@ -0,0 +1,877 @@
+#include "common.h"
+#include <errno.h>
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/reg_sysctrl.h>
+#include <asm/arch/reg_mdcom.h>
+#include <asm/arch/reg_xcpu.h>
+#include <asm/arch/defs_mdcom.h>
+#include <asm/arch/mdcom.h>
+#include <asm/arch/factory.h>
+#include <asm/arch/rda_iomap.h>
+#include <asm/arch/reg_cfg_regs.h>
+
+
+static u32 modem_logic_base_addr = 0x02000000;
+void rda_mdcom_set_logic_base_addr(u32 base)
+{
+	modem_logic_base_addr = base & 0xffff0000;
+	printf("## Set modem logic base address %#x\n", modem_logic_base_addr);
+}
+
+#define RDA_MODEM_IN_DDR(addr, modem_logic_base_addr)	\
+	(((u32)(addr) & 0x0F000000) == (modem_logic_base_addr & 0x0F000000))
+
+/*
+ * Convert a modem address to an AP address
+ */
+u32 rda_mdcom_address_modem2ap(u32 addr)
+{
+#if defined(_TGT_MODEM_MEM_SIZE) && (_TGT_MODEM_MEM_SIZE > 0)
+	if (RDA_MODEM_IN_DDR(addr, modem_logic_base_addr))
+		return (RDA_MODEM_RAM_BASE - modem_logic_base_addr + addr);
+	else
+		return RDA_ADD_M2A(addr);
+#else
+	return RDA_ADD_M2A(addr);
+#endif
+}
+
+/*
+ * Setup modem running env
+ */
+int rda_mdcom_setup_run_env(u32 pc, u32 param)
+{
+	RDA_BOOT_HST_MONITOR_X_CTX_T *ctx =
+		(RDA_BOOT_HST_MONITOR_X_CTX_T *)RDA_BOOT_CTX_ADD;
+	ctx->cmdType = 0xFF;
+	ctx->pc = pc;
+	ctx->sp = 0;
+	ctx->param = (void *)param;
+	ctx->returnedValue = (void *)0;
+
+#if defined(_TGT_MODEM_MEM_SIZE) && (_TGT_MODEM_MEM_SIZE > 0)
+	// Set DDR access offset
+	if (RDA_MODEM_IN_DDR(pc, modem_logic_base_addr)) {
+#ifdef CONFIG_MACH_RDA8850E
+		u32 offs = RDA_MODEM_RAM_BASE - modem_logic_base_addr;
+
+		/* 0x1000000 alignment */
+		if(offs & 0xffffff) {
+			printf("\nERROR: modem memory map offset %#x is not aligned to 0x1000000.\n", offs);
+			printf("ERROR: modem cannot work, abort.\n");
+			return -1;
+		}
+
+		hwp_configRegs->Mem_mode_Sel = 0;
+		hwp_configRegs->H2X_DDR_Offset = offs;
+		hwp_configRegs->H2X_WD_DDR_Offset = offs;
+#else
+		u32 offs = CFG_REGS_H2X_DDR_OFFSET((RDA_MODEM_RAM_BASE - modem_logic_base_addr) >> 24);
+		hwp_configRegs->H2X_DDR_Offset = offs;
+#endif
+	};
+#endif
+
+	return 0;
+}
+
+/*
+ * Modem calibration data section address
+ */
+void rda_mdcom_get_calib_section(u32 *addr, u32 *len)
+{
+	if (addr)
+		*addr = RDA_MODEM_CAL_ADDR;
+	if (len)
+		*len = RDA_MODEM_CAL_LEN;
+}
+
+/*
+ * Modem extended calibration data section address
+ */
+void rda_mdcom_get_ext_calib_section(u32 *addr, u32 *len)
+{
+	if (addr)
+		*addr = RDA_MODEM_EXT_CAL_ADDR;
+	if (len)
+		*len = RDA_MODEM_EXT_CAL_LEN;
+}
+
+/*
+ * Modem factory section address
+ */
+void rda_mdcom_get_factory_section(u32 *addr, u32 *len)
+{
+	if (addr)
+		*addr = RDA_MODEM_FACT_ADDR;
+	if (len)
+		*len = RDA_MODEM_FACT_LEN;
+}
+
+/*
+ * AP factory section address
+ */
+void rda_mdcom_get_ap_factory_section(u32 *addr, u32 *len)
+{
+	if (addr)
+		*addr = RDA_AP_FACT_ADDR;
+	if (len)
+		*len = RDA_AP_FACT_LEN;
+}
+
+/*
+ * Reset cause
+ */
+u32 rda_mdcom_get_reset_cause(void)
+{
+	return ((RDA_AP_MBX_HEARTBEAT_T *)RDA_AP_MBX_HEARTBEAT_ADD)->resetCause;
+}
+
+/*
+ * Interface version
+ */
+u32 rda_mdcom_get_interface_version(void)
+{
+	return ((RDA_AP_MBX_HEARTBEAT_T *)RDA_AP_MBX_HEARTBEAT_ADD)->version;
+}
+
+/*
+ * Magic number
+ */
+int rda_mdcom_system_started_before(void)
+{
+	RDA_AP_MBX_MAGIC_NUMBER_T *magic =
+		(RDA_AP_MBX_MAGIC_NUMBER_T *)RDA_AP_MBX_MAGIC_NUMBER_ADD;
+	return magic->sysStarted == RDA_MAGIC_SYSTEM_STARTED_FLAG;
+}
+
+void rda_mdcom_set_system_started_flag(void)
+{
+	RDA_AP_MBX_MAGIC_NUMBER_T *magic =
+		(RDA_AP_MBX_MAGIC_NUMBER_T *)RDA_AP_MBX_MAGIC_NUMBER_ADD;
+	magic->sysStarted = RDA_MAGIC_SYSTEM_STARTED_FLAG;
+}
+
+int rda_mdcom_modem_crashed_before(void)
+{
+	RDA_AP_MBX_MAGIC_NUMBER_T *magic =
+		(RDA_AP_MBX_MAGIC_NUMBER_T *)RDA_AP_MBX_MAGIC_NUMBER_ADD;
+	return magic->modemCrashed == RDA_MAGIC_MODEM_CRASH_FLAG;
+}
+
+int rda_mdcom_calib_update_cmd_valid(void)
+{
+	RDA_AP_MBX_MAGIC_NUMBER_T *magic =
+		(RDA_AP_MBX_MAGIC_NUMBER_T *)RDA_AP_MBX_MAGIC_NUMBER_ADD;
+	if (magic->factUpdateCmd == RDA_MAGIC_FACT_UPD_CMD_FLAG &&
+			(magic->factUpdateType &
+			 RDA_MAGIC_FACT_UPD_TYPE_FLAG_MASK) ==
+			RDA_MAGIC_FACT_UPD_TYPE_FLAG &&
+			(magic->factUpdateType & RDA_MAGIC_FACT_UPD_TYPE_CALIB))
+		return 1;
+	else
+		return 0;
+}
+
+int rda_mdcom_factory_update_cmd_valid(void)
+{
+	RDA_AP_MBX_MAGIC_NUMBER_T *magic =
+		(RDA_AP_MBX_MAGIC_NUMBER_T *)RDA_AP_MBX_MAGIC_NUMBER_ADD;
+	if (magic->factUpdateCmd == RDA_MAGIC_FACT_UPD_CMD_FLAG &&
+			(magic->factUpdateType &
+			 RDA_MAGIC_FACT_UPD_TYPE_FLAG_MASK) ==
+			RDA_MAGIC_FACT_UPD_TYPE_FLAG &&
+			(magic->factUpdateType & RDA_MAGIC_FACT_UPD_TYPE_FACT))
+		return 1;
+	else
+		return 0;
+}
+
+int rda_mdcom_ap_factory_update_cmd_valid(void)
+{
+	RDA_AP_MBX_MAGIC_NUMBER_T *magic =
+		(RDA_AP_MBX_MAGIC_NUMBER_T *)RDA_AP_MBX_MAGIC_NUMBER_ADD;
+	if (magic->factUpdateCmd == RDA_MAGIC_FACT_UPD_CMD_FLAG &&
+			(magic->factUpdateType &
+			 RDA_MAGIC_FACT_UPD_TYPE_FLAG_MASK) ==
+			RDA_MAGIC_FACT_UPD_TYPE_FLAG &&
+			(magic->factUpdateType & RDA_MAGIC_FACT_UPD_TYPE_AP_FACT))
+		return 1;
+	else
+		return 0;
+}
+
+/*
+ * Modem log info
+ */
+static int rda_mdcom_modem_address_valid(u32 addr)
+{
+	if ((addr >= RDA_MODEM_INTSRAM_BASE &&
+				addr < RDA_MODEM_INTSRAM_END) ||
+			(addr >= RDA_MODEM_RAM_BASE &&
+			 addr < RDA_MODEM_RAM_END)) {
+		return 1;
+	}
+	return 0;
+}
+
+void rda_mdcom_init_all_log_info(void)
+{
+	/* Init log info */
+	RDA_AP_MBX_LOG_BUF_INFO_T *log =
+		(RDA_AP_MBX_LOG_BUF_INFO_T *)RDA_AP_MBX_LOG_BUF_INFO_ADD;
+	memset(log, 0, sizeof(*log));
+	/* Init modem crash flag */
+	RDA_AP_MBX_MAGIC_NUMBER_T *magic =
+		(RDA_AP_MBX_MAGIC_NUMBER_T *)RDA_AP_MBX_MAGIC_NUMBER_ADD;
+	magic->modemCrashed = 0;
+	magic->factUpdateCmd = 0;
+	magic->factUpdateType = 0;
+	/* Init heartbeat structure members */
+	memset((RDA_AP_MBX_HEARTBEAT_T *)RDA_AP_MBX_HEARTBEAT_ADD, 0,
+			sizeof(RDA_AP_MBX_HEARTBEAT_T));
+}
+
+void rda_mdcom_get_modem_log_info(u32 *addr, u32 *len)
+{
+	RDA_AP_MBX_LOG_BUF_INFO_T *log =
+		(RDA_AP_MBX_LOG_BUF_INFO_T *)RDA_AP_MBX_LOG_BUF_INFO_ADD;
+	u32 log_addr = rda_mdcom_address_modem2ap(log->modemAddr);
+	u32 log_len = log->modemLen;
+
+	/* Check whether the address is valid */
+	if (!rda_mdcom_modem_address_valid(log_addr) ||
+			log_len > RDA_AP_MBX_MAX_MODEM_LOG_LEN) {
+		log_addr = 0;
+		log_len = 0;
+	}
+
+	if (addr)
+		*addr = log_addr;
+	if (len)
+		*len = log_len;
+}
+
+void rda_mdcom_get_modem_exception_info(u32 *addr, u32 *len)
+{
+	RDA_AP_MBX_LOG_BUF_INFO_T *log =
+		(RDA_AP_MBX_LOG_BUF_INFO_T *)RDA_AP_MBX_LOG_BUF_INFO_ADD;
+	u32 exc_addr = RDA_ADD_M2A(log->modemExcAddr);
+	u32 exc_len = log->modemExcLen;
+
+	/* Check whether the address is valid */
+	if (!rda_mdcom_modem_address_valid(exc_addr) ||
+			exc_len > RDA_AP_MBX_MAX_MODEM_EXC_LEN) {
+		exc_addr = 0;
+		exc_len = 0;
+	}
+
+	if (addr)
+		*addr = exc_addr;
+	if (len)
+		*len = exc_len;
+}
+
+/*
+ * Modem XCPU info
+ */
+void rda_mdcom_show_xcpu_info(void)
+{
+	printf("\n");
+	printf("Modem XCPU info:\n");
+	printf("----------------\n");
+	printf("Cause = 0x%08x\n", hwp_xcpu->cp0_Cause);
+	printf("Status = 0x%08x\n", hwp_xcpu->cp0_Status);
+	printf("BadAddr = 0x%08x\n", hwp_xcpu->cp0_BadVAddr);
+	printf("EPC = 0x%08x\n", hwp_xcpu->cp0_EPC);
+	printf("RA = 0x%08x\n", hwp_xcpu->Regfile_RA);
+	printf("PC = 0x%08x\n", hwp_xcpu->rf0_addr);
+	printf("----------------\n");
+}
+
+/*
+ * Modem software version info
+ */
+void rda_mdcom_show_software_version(void)
+{
+	int i = 0;
+	char buf[256];
+	char *str;
+	RDA_MODEM_MAP_VERSION_T *version;
+	RDA_MODEM_MAP_MODULE_T *map;
+	RDA_MODEM_MAP_MODULE_T **ptr =
+		(RDA_MODEM_MAP_MODULE_T **)RDA_MODEM_MAP_PTR;
+
+	printf("\n");
+	map = (RDA_MODEM_MAP_MODULE_T *)rda_mdcom_address_modem2ap(
+			(u32)*ptr);
+	if (!ptr || !rda_mdcom_modem_address_valid((u32)map)) {
+		printf("No modem software versions\n");
+		return;
+	}
+
+	printf("Modem software versions:\n");
+	printf("------------------------\n");
+	for (i = 0; i < RDA_MODEM_MAP_QTY; i++, map++) {
+		if (!map->version)
+			continue;
+		version = (RDA_MODEM_MAP_VERSION_T *)
+			rda_mdcom_address_modem2ap((u32)map->version);
+		if (!rda_mdcom_modem_address_valid((u32)version))
+			continue;
+		printf("[%02d]\n", i);
+		printf("revision = %d / 0x %07x\n",
+				version->revision,
+				version->revision);
+		printf("number = %d\n", version->number);
+		printf("date = %d\n", version->date);
+		str = (char *)rda_mdcom_address_modem2ap((u32)version->string);
+		if (version->string &&
+				rda_mdcom_modem_address_valid((u32)str)) {
+			snprintf(buf, sizeof(buf), "%s", str);
+			buf[sizeof(buf) - 1] = '\0';
+			printf("string = %s\n", buf);
+		} else {
+			printf("string = <n/a>\n");
+		}
+	}
+	printf("------------------------\n");
+}
+
+/*
+ * Communication channels
+ */
+static struct rda_mdcom_channel rda_rda_mdcom_chn[] = {
+	/* AT command channel */
+	{
+		RDA_MDCOM_LINE_AT_CMD,
+		RDA_MDCOM_LINE_AT_CMD_FC,
+		(struct rda_mdcom_channel_head*)RDA_MDCOM_CHN_AT_HEAD_ADD_READ,
+		(void *)RDA_MDCOM_CHN_AT_BUF_ADD_READ,
+		RDA_MDCOM_CHN_AT_BUF_LEN_READ-1,
+		(struct rda_mdcom_channel_head*)RDA_MDCOM_CHN_AT_HEAD_ADD_WRITE,
+		(void *)RDA_MDCOM_CHN_AT_BUF_ADD_WRITE,
+		RDA_MDCOM_CHN_AT_BUF_LEN_WRITE-1
+	},
+
+	/* SYSTEM command channel */
+	{
+		RDA_MDCOM_LINE_SYSTEM,
+		RDA_MDCOM_LINE_SYSTEM_FC,
+		(struct rda_mdcom_channel_head*)RDA_MDCOM_CHN_SYS_HEAD_ADD_READ,
+		(void *)RDA_MDCOM_CHN_SYS_BUF_ADD_READ,
+		RDA_MDCOM_CHN_SYS_BUF_LEN_READ-1,
+		(struct rda_mdcom_channel_head*)RDA_MDCOM_CHN_SYS_HEAD_ADD_WRITE,
+		(void *)RDA_MDCOM_CHN_SYS_BUF_ADD_WRITE,
+		RDA_MDCOM_CHN_SYS_BUF_LEN_WRITE-1
+	},
+
+	/* TRACE communciation channel */
+	{
+		RDA_MDCOM_LINE_TRACE,
+		RDA_MDCOM_LINE_TRACE_FC,
+		(struct rda_mdcom_channel_head*)RDA_MDCOM_CHN_TRACE_HEAD_ADD_READ,
+		(void *)RDA_MDCOM_CHN_TRACE_BUF_ADD_READ,
+		RDA_MDCOM_CHN_TRACE_BUF_LEN_READ-1,
+		(struct rda_mdcom_channel_head*)RDA_MDCOM_CHN_TRACE_HEAD_ADD_WRITE,
+		(void *)RDA_MDCOM_CHN_TRACE_BUF_ADD_WRITE,
+		RDA_MDCOM_CHN_TRACE_BUF_LEN_WRITE-1
+	}
+};
+
+int rda_mdcom_init_port(int port_id)
+{
+	switch (port_id) {
+	case RDA_MDCOM_PORT0:
+		hwp_mdComregs->Mask_Set = COMREGS_IRQ0_MASK_SET(0);
+		hwp_mdComregs->Mask_Clr = COMREGS_IRQ0_MASK_CLR(0xFF);
+		hwp_mdComregs->ItReg_Set = COMREGS_IRQ0_SET(0);
+		hwp_mdComregs->ItReg_Clr = COMREGS_IRQ0_CLR(0xFF);
+		return 0;
+
+	case RDA_MDCOM_PORT1:
+		hwp_mdComregs->Mask_Set = COMREGS_IRQ1_MASK_SET(0);
+		hwp_mdComregs->Mask_Clr = COMREGS_IRQ1_MASK_CLR(0xFF);
+		hwp_mdComregs->ItReg_Set = COMREGS_IRQ1_SET(0);
+		hwp_mdComregs->ItReg_Clr = COMREGS_IRQ1_CLR(0xFF);
+		return 0;
+
+	default:
+		return -EINVAL;
+	}
+}
+
+int rda_mdcom_line_set(int port_id, int line_id)
+{
+	if (line_id & ~0x7) {
+		return -EINVAL;
+	}
+
+	switch (port_id) {
+	case RDA_MDCOM_PORT0:
+		hwp_mdComregs->ItReg_Set = COMREGS_IRQ0_SET(1 << line_id);
+		return 0;
+
+	case RDA_MDCOM_PORT1:
+		hwp_mdComregs->ItReg_Set = COMREGS_IRQ1_SET(1 << line_id);
+		return 0;
+
+	default:
+		return -EINVAL;
+	}
+}
+
+int rda_mdcom_line_clear(int port_id, int line_id)
+{
+	if (line_id & ~0x7) {
+		return -EINVAL;
+	}
+
+	switch (port_id) {
+	case RDA_MDCOM_PORT0:
+		hwp_mdComregs->ItReg_Clr = COMREGS_IRQ0_CLR(1 << line_id);
+		return 0;
+
+	case RDA_MDCOM_PORT1:
+		hwp_mdComregs->ItReg_Clr = COMREGS_IRQ0_CLR(1 << line_id);
+		return 0;
+
+	default:
+		return -EINVAL;
+	}
+}
+
+int rda_mdcom_line_set_check(int port_id, int line_id)
+{
+	if (line_id & ~0x7) {
+		return 0;
+	}
+
+	switch (port_id) {
+	case RDA_MDCOM_PORT0:
+		return !!(hwp_mdComregs->ItReg_Clr & COMREGS_IRQ0_CLR(1 << line_id));
+
+	case RDA_MDCOM_PORT1:
+		return !!(hwp_mdComregs->ItReg_Clr & COMREGS_IRQ1_CLR(1 << line_id));
+
+	default:
+		return 0;
+	}
+}
+
+int rda_mdcom_line_clear_check(int port_id, int line_id)
+{
+	if (line_id & ~0x7) {
+		return 0;
+	}
+
+	switch (port_id) {
+	case RDA_MDCOM_PORT0:
+		return !(hwp_mdComregs->ItReg_Set & COMREGS_IRQ0_SET(1 << line_id));
+
+	case RDA_MDCOM_PORT1:
+		return !(hwp_mdComregs->ItReg_Set & COMREGS_IRQ0_SET(1 << line_id));
+
+	default:
+		return 0;
+	}
+}
+
+int rda_mdcom_line_set_wait(int port_id, int line_id, int waittime)
+{
+	unsigned long end_time = get_ticks() + waittime;
+
+	if (line_id & ~0x7) {
+		return 0;
+	}
+
+	switch (port_id) {
+	case RDA_MDCOM_PORT0:
+		while (!(hwp_mdComregs->ItReg_Clr & COMREGS_IRQ0_CLR(1 << line_id))) {
+			if ((waittime >= 0) && (end_time <= get_ticks()))
+				return 0;
+		}
+		return 1;
+
+	case RDA_MDCOM_PORT1:
+		while (!(hwp_mdComregs->ItReg_Clr & COMREGS_IRQ1_CLR(1 << line_id))) {
+			if ((waittime >= 0) && (end_time <= get_ticks()))
+				return 0;
+		}
+		return 1;
+
+	default:
+		return 0;
+	}
+}
+
+int rda_mdcom_line_clear_wait(int port_id, int line_id, int waittime)
+{
+	unsigned long end_time = get_ticks() + waittime;
+
+	if (line_id & ~0x7) {
+		return 0;
+	}
+
+	switch (port_id) {
+	case RDA_MDCOM_PORT0:
+		while (hwp_mdComregs->ItReg_Set & COMREGS_IRQ0_SET(1 << line_id)) {
+			if ((waittime >= 0) && (end_time <= get_ticks()))
+				return 0;
+		}
+		return 1;
+
+	case RDA_MDCOM_PORT1:
+		while (hwp_mdComregs->ItReg_Set & COMREGS_IRQ0_SET(1 << line_id)) {
+			if ((waittime >= 0) && (end_time <= get_ticks()))
+				return 0;
+		}
+		return 1;
+
+	default:
+		return 0;
+	}
+}
+
+void rda_mdcom_port_show(void)
+{
+	printf("RDA MDCOM ports stauts:\n");
+	printf("REGISTER Cause     = 0x%.16x\n", hwp_mdComregs->Cause);
+	printf("REGISTER Mask_Set  = 0x%.16x\n", hwp_mdComregs->Mask_Set);
+	printf("REGISTER Mask_Clr  = 0x%.16x\n", hwp_mdComregs->Mask_Clr);
+	printf("REGISTER ItReg_Set = 0x%.16x\n", hwp_mdComregs->ItReg_Set);
+	printf("REGISTER ItReg_Clr = 0x%.16x\n", hwp_mdComregs->ItReg_Clr);
+	printf("RDA MDCOM ports stauts end.\n");
+}
+
+int rda_mdcom_channel_init(const unsigned int channel)
+{
+	if (channel >= sizeof(rda_rda_mdcom_chn) / sizeof(struct rda_mdcom_channel)) {
+		return -EINVAL;
+	}
+
+	memset(rda_rda_mdcom_chn[channel].read_buf_head, 0,
+	       sizeof(struct rda_mdcom_channel_head));
+	memset(rda_rda_mdcom_chn[channel].write_buf_head, 0,
+	       sizeof(struct rda_mdcom_channel_head));
+	return 0;
+}
+
+int rda_mdcom_channel_all_init(void)
+{
+	return rda_mdcom_channel_init(RDA_MDCOM_CHANNEL_AT) ||
+		rda_mdcom_channel_init(RDA_MDCOM_CHANNEL_SYSTEM) ||
+		rda_mdcom_channel_init(RDA_MDCOM_CHANNEL_TRACE);
+}
+
+int rda_mdcom_channel_buf_send_stream(const unsigned int channel, void *buf,
+				      int size, int waittime)
+{
+	unsigned long end_time = get_ticks() + waittime;
+	struct rda_mdcom_channel* channel_ptr;
+	struct rda_mdcom_channel_head* channel_head_ptr;
+	int buffer_size_mask;
+	int count = 0;
+
+	if (channel >= sizeof(rda_rda_mdcom_chn) / sizeof(struct rda_mdcom_channel)) {
+		return -EINVAL;
+	}
+
+	if (size < 0) {
+		return -EINVAL;
+	}
+
+	channel_ptr = &rda_rda_mdcom_chn[channel];
+	channel_head_ptr = channel_ptr->write_buf_head;
+	buffer_size_mask = channel_ptr->write_buf_size_mask;
+
+	while (1) {
+		int write_offset = channel_head_ptr->write_offset;
+		int remain_len = (buffer_size_mask + 1) -
+				 ((write_offset - channel_head_ptr->read_offset) & buffer_size_mask);
+
+		if (remain_len > buffer_size_mask + 1 - write_offset) {
+			remain_len = buffer_size_mask + 1 - write_offset;
+		}
+
+		if (remain_len) {
+			if (remain_len > size) {
+				remain_len = size;
+			}
+
+			memcpy(((char*)channel_ptr->write_buf) + write_offset, buf, remain_len);
+			channel_head_ptr->write_offset = (write_offset + remain_len) & buffer_size_mask;
+			size -= remain_len;
+			buf = (char*)buf + remain_len;
+			count += remain_len;
+
+			if (!size) {
+				return count;
+			}
+		} else if ((waittime >= 0) && (end_time <= get_ticks())) {
+			return count;
+		}
+	}
+}
+
+int rda_mdcom_channel_buf_send_dgram(const unsigned int channel, void *buf,
+				     int size, int waittime)
+{
+	unsigned long end_time = get_ticks() + waittime;
+	struct rda_mdcom_channel* channel_ptr;
+	struct rda_mdcom_channel_head* channel_head_ptr;
+	int buffer_size_mask, write_offset;
+
+	if (channel >= sizeof(rda_rda_mdcom_chn) / sizeof(struct rda_mdcom_channel)) {
+		return -EINVAL;
+	}
+
+	if (size < 0) {
+		return -EINVAL;
+	}
+
+	channel_ptr = &rda_rda_mdcom_chn[channel];
+	channel_head_ptr = channel_ptr->write_buf_head;
+	buffer_size_mask = channel_ptr->write_buf_size_mask;
+	write_offset = ALIGN(channel_head_ptr->write_offset, 4) & buffer_size_mask;
+
+	while (1) {
+		int remain_len = (buffer_size_mask + 1) -
+				 ((write_offset - channel_head_ptr->read_offset) & buffer_size_mask);
+
+		if (remain_len >= size) {
+			remain_len = buffer_size_mask + 1 - write_offset;
+
+			if (remain_len > size) {
+				remain_len = size;
+			}
+
+			memcpy(((char*)channel_ptr->write_buf) + write_offset, buf,
+			       remain_len);
+
+			if (remain_len != size) {
+				memcpy(channel_ptr->write_buf, (char*)buf + remain_len,
+				       size - remain_len);
+			}
+			channel_head_ptr->write_offset = (write_offset + size) &
+							 buffer_size_mask;
+			return 0;
+		}
+
+		if ((waittime >= 0) && (end_time <= get_ticks())) {
+			return -EAGAIN;
+		}
+	}
+}
+
+int rda_mdcom_channel_buf_send_available(const unsigned int channel)
+{
+	struct rda_mdcom_channel* channel_ptr;
+	struct rda_mdcom_channel_head* channel_head_ptr;
+	int buffer_size_mask;
+	int read_offset;
+	int write_offset;
+
+	if (channel >= sizeof(rda_rda_mdcom_chn)/sizeof(struct rda_mdcom_channel)) {
+		return 0;
+	}
+
+	channel_ptr = &rda_rda_mdcom_chn[channel];
+	channel_head_ptr = channel_ptr->write_buf_head;
+	buffer_size_mask = channel_ptr->write_buf_size_mask;
+	read_offset = channel_head_ptr->read_offset;
+	write_offset = channel_head_ptr->write_offset;
+
+	return ((buffer_size_mask + 1) - ((write_offset - read_offset) & buffer_size_mask));
+}
+
+int rda_mdcom_channel_buf_recv_stream(const unsigned int channel, void *buf,
+				      int size, int waittime)
+{
+	unsigned long end_time = get_ticks() + waittime;
+	struct rda_mdcom_channel* channel_ptr;
+	struct rda_mdcom_channel_head* channel_head_ptr;
+	int buffer_size_mask;
+	int count = 0;
+	int buf_offset = 0;
+
+	if (channel >= sizeof(rda_rda_mdcom_chn) / sizeof(struct rda_mdcom_channel)) {
+		return -EINVAL;
+	}
+
+	if (size < 0) {
+		return -EINVAL;
+	}
+
+	channel_ptr = &rda_rda_mdcom_chn[channel];
+	channel_head_ptr = channel_ptr->read_buf_head;
+	buffer_size_mask = channel_ptr->read_buf_size_mask;
+
+	while (1) {
+		int read_offset = channel_head_ptr->read_offset;
+		int remain_len = channel_head_ptr->write_offset - read_offset;
+
+		if (remain_len < 0) {
+			remain_len = buffer_size_mask + 1 - read_offset;
+		}
+
+		if (remain_len) {
+			if (remain_len > size) {
+				remain_len = size;
+			}
+
+			memcpy((char *)buf + buf_offset, ((char*)channel_ptr->read_buf) + read_offset, remain_len);
+			channel_head_ptr->read_offset = (read_offset + remain_len) &
+							buffer_size_mask;
+			size -= remain_len;
+			count += remain_len;
+			buf_offset += remain_len;
+
+			if (!size) {
+				return count;
+			}
+		} else if ((waittime >= 0) && (end_time <= get_ticks())) {
+			return count;
+		}
+	}
+}
+
+int rda_mdcom_channel_buf_recv_dgram(const unsigned int channel, void *buf,
+				     int size, int waittime)
+{
+	unsigned long end_time = get_ticks() + waittime;
+	struct rda_mdcom_channel* channel_ptr;
+	struct rda_mdcom_channel_head* channel_head_ptr;
+	int buffer_size_mask, read_offset;
+
+	if (channel >= sizeof(rda_rda_mdcom_chn) / sizeof(struct rda_mdcom_channel)) {
+		return -EINVAL;
+	}
+
+	if (size < 0) {
+		return -EINVAL;
+	}
+
+	channel_ptr = &rda_rda_mdcom_chn[channel];
+	channel_head_ptr = channel_ptr->read_buf_head;
+	buffer_size_mask = channel_ptr->read_buf_size_mask;
+	read_offset = ALIGN(channel_head_ptr->read_offset, 4) & buffer_size_mask;
+
+	while (1) {
+		int remain_len = (channel_head_ptr->write_offset - read_offset +
+				  buffer_size_mask + 1) & buffer_size_mask;
+
+		if (remain_len >= size) {
+			remain_len = buffer_size_mask + 1 - read_offset;
+
+			if (remain_len > size) {
+				remain_len = size;
+			}
+
+			memcpy(buf, ((char*)channel_ptr->read_buf) + read_offset, remain_len);
+
+			if (remain_len != size) {
+				memcpy(((char *)buf + remain_len), channel_ptr->read_buf, size - remain_len);
+			}
+			channel_head_ptr->read_offset = (read_offset + size) & buffer_size_mask;
+
+			return 0;
+		}
+
+		if ((waittime >= 0) && (end_time <= get_ticks())) {
+			return -EAGAIN;
+		}
+	}
+}
+
+int rda_mdcom_channel_buf_recv_available(const unsigned int channel)
+{
+	struct rda_mdcom_channel* channel_ptr;
+	struct rda_mdcom_channel_head* channel_head_ptr;
+	int buffer_size_mask;
+	int read_offset;
+	int write_offset;
+
+	if (channel >= sizeof(rda_rda_mdcom_chn) / sizeof(struct rda_mdcom_channel)) {
+		return 0;
+	}
+
+	channel_ptr = &rda_rda_mdcom_chn[channel];
+	channel_head_ptr = channel_ptr->write_buf_head;
+	buffer_size_mask = channel_ptr->write_buf_size_mask;
+	read_offset = channel_head_ptr->read_offset;
+	write_offset = channel_head_ptr->write_offset;
+
+	return ((write_offset - read_offset) & buffer_size_mask);
+}
+
+void rda_mdcom_channel_show(const unsigned int channel)
+{
+	printf("RDA MDCOM channel %d stauts:\n", channel);
+
+	if (channel >= sizeof(rda_rda_mdcom_chn) / sizeof(struct rda_mdcom_channel)) {
+		printf("Channel number is out of range, ERROR!\n");
+	} else {
+		struct rda_mdcom_channel* channel_ptr = &rda_rda_mdcom_chn[channel];
+		struct rda_mdcom_channel_head* channel_head_ptr;
+		printf("Read buffer head address  = 0x%p\n",
+		       channel_ptr->read_buf_head);
+		printf("Read buffer address       = 0x%p\n",
+		       channel_ptr->read_buf);
+		printf("Read buffer length        = %d\n",
+		       channel_ptr->read_buf_size_mask + 1);
+		channel_head_ptr = channel_ptr->read_buf_head;
+		printf("Read buffer offset read   = 0x%x\n",
+		       channel_head_ptr->read_offset);
+		printf("Read buffer offset write  = 0x%x\n",
+		       channel_head_ptr->write_offset);
+
+		printf("Write buffer head address = 0x%p\n",
+		       channel_ptr->write_buf_head);
+		printf("Write buffer address      = 0x%p\n",
+		       channel_ptr->write_buf);
+		printf("Write buffer length       = %d\n",
+		       channel_ptr->write_buf_size_mask + 1);
+		channel_head_ptr = channel_ptr->write_buf_head;
+		printf("Write buffer offset read  = 0x%x\n",
+		       channel_head_ptr->read_offset);
+		printf("Write buffer offset write = 0x%x\n",
+		       channel_head_ptr->write_offset);
+	}
+
+	printf("RDA MDCOM channel %d stauts end.\n", channel);
+}
+
+int rda_mdcom_tstc(const unsigned int channel)
+{
+	struct rda_mdcom_channel_head* channel_head_ptr;
+
+	if (channel >= sizeof(rda_rda_mdcom_chn) / sizeof(struct rda_mdcom_channel)) {
+		return 0;
+	}
+
+	channel_head_ptr = rda_rda_mdcom_chn[channel].read_buf_head;
+
+	return (channel_head_ptr->write_offset != channel_head_ptr->read_offset);
+}
+
+int rda_mdcom_getc(const unsigned int channel)
+{
+	char c = 0;
+
+	rda_mdcom_channel_buf_recv_stream(channel, &c, 1, -1);
+	return c;
+}
+
+void rda_mdcom_putc(const char c, const unsigned int channel)
+{
+	rda_mdcom_channel_buf_send_stream(channel, (void*)&c, 1, -1);
+}
+
+void rda_mdcom_puts(const char *s, const unsigned int channel)
+{
+	rda_mdcom_channel_buf_send_stream(channel, (void*)s, strlen(s), -1);
+}
+
diff --git a/arch/arm/cpu/armv7/rda/rda_crypto.c b/arch/arm/cpu/armv7/rda/rda_crypto.c
new file mode 100644
index 0000000000..63eca2e271
--- /dev/null
+++ b/arch/arm/cpu/armv7/rda/rda_crypto.c
@@ -0,0 +1,260 @@
+#include <common.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <nand.h>
+#include <malloc.h>
+#include <image.h>
+#include <usb/usbserial.h>
+#include <asm/arch/rda_sys.h>
+#include <asm/arch/rda_crypto.h>
+#include <pdl.h>
+
+//#define RDA_CRYPTO_DEBUG
+
+#ifdef CONFIG_SIGNATURE_CHECK_IMAGE
+
+struct pubkey_cert_t {
+	struct {
+		uint16_t se_cfg; // vendor_id and key_index
+		uint8_t dummy[94];           // 96
+		struct pubkey pubkey;        // +64
+	} c;
+	struct sig signature;                // +96
+};
+
+struct rda_cert_t {
+	// R&D Certificate:
+	// Create a signature with name[16] =
+	//    "  R&D-CERT"(10)
+	//    "F:0000"(6)
+	// zeros[16] = 0...
+	// Then Hash:
+	//     sig.name, zeros, UNIQUE-ID
+	struct sig rnd_cert;           // 96
+
+	// free space without sign checking:
+	uint8_t dummy[160];            // 160
+};
+
+
+struct rda_se_image {
+	uint8_t               spl_code[48128+160];
+	struct sig            image_signature;      // 96
+	struct rda_cert_t     cert;                 // 256
+	struct pubkey_cert_t  vendor_pubkey_cert;   // 256
+};
+
+#ifdef RDA_CRYPTO_DEBUG
+#    define puts_deb(a) puts(a)
+#else
+#    define puts_deb(a)
+#    define debug_dump_key_and_signature(h,pk,sig,d,l)
+#endif
+
+#ifdef RDA_CRYPTO_DEBUG
+static void debug_dump_key_and_signature(
+	const char *header, const struct pubkey *pk, const struct sig *sig,
+	const void *data, unsigned data_len)
+{
+	if (sig) {
+		printf("%s signature:\n", header);
+		rda_dump_buf((char *)sig, 96);
+	}
+	if (pk) {
+		printf("%s public key:\n", header);
+		rda_dump_buf((char *)pk, 64);
+	}
+	if (data) {
+		printf("%s data:\n", header);
+		rda_dump_buf((char *)data, data_len);
+	}
+}
+#endif
+
+
+static int check_rnd_certificate(
+	const struct rda_cert_t  *certs,
+	const struct pubkey      *pubkey,
+	struct spl_security_info *info)
+{
+	int ret;
+	const struct sig *rnd_signature = &certs->rnd_cert;
+	struct {
+		uint8_t message[32];
+		struct chip_unique_id id;
+	} hashme;
+
+	puts_deb("Checking R&D Certificate\n");
+
+	// create message
+	memset(&hashme, 0, sizeof(hashme));
+	memcpy(hashme.message, rnd_signature->name, 16);
+	hashme.id = info->chip_unique_id;
+
+	// Dump the R&D hashme
+	debug_dump_key_and_signature("R&D hashme", pubkey, rnd_signature,
+		(char *)&hashme, sizeof(hashme));
+
+	ret = signature_check(
+		(const uint8_t*)&hashme, sizeof(hashme),
+		rnd_signature,
+		pubkey);
+
+	return ret;
+}
+
+
+static void get_device_security_context(
+	const struct rda_se_image *image,
+	struct spl_security_info  *info)
+{
+	// Get ROM public key and context
+	info->secure_mode = get_chip_security_context(
+				&info->chip_security_context,
+				&info->pubkey);
+
+	int flags = info->chip_security_context.flags;
+
+	// Fix the return code if security hasn't been enabled
+	if ((flags & RDA_SE_CFG_SECURITY_ENABLE_BIT) == 0) {
+		puts_deb("(Security disabled by efuse flags)\n");
+		info->secure_mode = ROM_API_SECURITY_DISABLED;
+		return;
+	}
+
+	// Check if we a using the customer public-key certificate
+	if (flags & RDA_SE_CFG_INDIRECT_SIGN_BIT) {
+		const struct pubkey_cert_t *vendor_cert = &image->vendor_pubkey_cert;
+		puts_deb("(Using vendor pkcert as per efuse flags)\n");
+
+		// The vendor pkey cert has already been verified
+		// by the bootrom. For debugging check again here:
+#ifdef RDA_CRYPTO_DEBUG
+		// Dump the PKCERT data
+		debug_dump_key_and_signature("PKCERT",
+		        &info->pubkey, &vendor_cert->signature,
+			&vendor_cert->c, sizeof(vendor_cert->c));
+
+		int ret;
+		ret = signature_check(
+			(uint8_t*)&vendor_cert->c, sizeof(vendor_cert->c),
+			&vendor_cert->signature,
+			&info->pubkey);
+		printf("PKCERT check return %d\n", ret);
+#endif
+		// copy public key certificate
+		info->pubkey = vendor_cert->c.pubkey;
+	}
+
+	// Sanity check for PKEY
+	if (memcmp(&info->pubkey, "RDASEd", 6) != 0) {
+		puts_deb("(Public key for signature check invalid)\n");
+		info->secure_mode = -1; // better: ROM_API_SECURITY_INVALID_PKEY
+		return;
+	}
+
+	// Dump the keys and signature when debugging
+	debug_dump_key_and_signature("PDL1 -",
+	        &info->pubkey, &image->image_signature, NULL, 0);
+
+	// Check if device is in R&D mode
+	int rnd_status = check_rnd_certificate(&image->cert, &info->pubkey, info);
+	if (rnd_status == 0) {
+		puts("(R&D mode override) ");
+		// ... and disable security...
+		info->secure_mode = ROM_API_SECURITY_DISABLED;
+	}
+}
+
+
+int set_security_context(struct spl_security_info *info, const void *_image)
+{
+	const struct rda_se_image *image = _image;
+
+	memset(info, 0, sizeof(*info));
+
+	if (memcmp(romapi->magic, "RDA API", 8) != 0) {
+		puts("Board security: Not present\n");
+		info->secure_mode = ROM_API_SECURITY_UNAVAILABLE;
+	}
+	else {
+		puts("Board security: present ");
+
+		info->version = romapi->version;
+		get_chip_id(&info->chip_id);
+		get_chip_true_random(info->random, 32);
+		get_chip_unique(&info->chip_unique_id);
+
+		get_device_security_context(image, info);
+
+		switch (info->secure_mode) {
+		case ROM_API_SECURITY_ENABLED:
+			puts("and enabled.\n");
+			break;
+		case ROM_API_SECURITY_DISABLED:
+			puts("but disabled.\n");
+			break;
+		case ROM_API_INVALID_KEYINDEX:
+		case ROM_API_INVALID_VENDOR_ID:
+			puts("but has invalid key-index or vendor-id!\n");
+			break;
+		default:
+			puts("but has invalid configuration!\n");
+			break;
+		}
+	}
+	return info->secure_mode;
+}
+
+int image_sign_verify(const uint8_t *buffer, uint32_t len)
+{
+	spl_bd_t *spl_board_info = (spl_bd_t *)CONFIG_SPL_BOARD_INFO_ADDR;
+	struct spl_security_info *info = &spl_board_info->spl_security_info;
+
+	len -= sizeof(struct sig);
+	const struct sig *signature = (const struct sig *)(buffer + len);
+
+	puts("Verify image:\n");
+
+	// Check security mode
+	int secure_mode = info->secure_mode;
+	switch (secure_mode) {
+	case ROM_API_SECURITY_ENABLED:
+		// Check the signature of the image
+		debug_dump_key_and_signature("bootloader -",
+		         &info->pubkey, signature, NULL, 0);
+		return signature_check(buffer, len, signature, &info->pubkey);
+	case ROM_API_SECURITY_DISABLED:
+	case ROM_API_SECURITY_UNAVAILABLE:
+		return 0;
+	default:
+		return secure_mode; // This is != 0 -> verify error
+	}
+}
+
+int image_sign_verify_uimage(image_header_t *hdr)
+{
+	return image_sign_verify((const uint8_t *)hdr,
+	                         image_get_image_size(hdr) + sizeof(struct sig));
+}
+
+#else
+int set_security_context(struct spl_security_info *info, const void *_image)
+{
+	memset(info, 0, sizeof(*info));
+
+	if (memcmp(romapi->magic, "RDA API", 8) == 0) {
+		puts("Board security: present ");
+
+		info->version = romapi->version;
+		get_chip_unique(&info->chip_unique_id);
+	}
+	return ROM_API_SECURITY_DISABLED;
+}
+
+int image_sign_verify(const uint8_t *buffer, uint32_t len)
+{
+	return 0;
+}
+#endif
+
diff --git a/arch/arm/cpu/armv7/rda/rda_romapi.c b/arch/arm/cpu/armv7/rda/rda_romapi.c
new file mode 100644
index 0000000000..3eca055ed5
--- /dev/null
+++ b/arch/arm/cpu/armv7/rda/rda_romapi.c
@@ -0,0 +1,133 @@
+/*
+ * Warning:
+ *
+ * This file is a mess of debugging and ROM bug workarounds.
+ */
+
+/* Enable a workaround for a bug in the bootrom romapi. */
+#define RDA8810_VENDOR_EFUSE_WORKAROUND
+
+/* Enable debugging certificates in pdl1: */
+//#define RDA_CRYPTO_DEBUG_FAKE_ROMCERT
+
+
+
+#ifdef RDA_CRYPTO_DEBUG_FAKE_ROMCERT
+/*
+ * Debugging version og get_chip_security_context().
+ * This version is enabled with RDA_CRYPTO_DEBUG_FAKE_ROMCERT
+ *
+TEST DATA
+   Use this secret key (file: rdatest.sec, pw: pa$$w0rd):
+
+"Comment: RDA PDL-Test-01 secret key
+UkRBU0VkQksAAAAq0Ai4xjiIrmda3G8qI6q3B4gPbVQMPISmUkRBIFBETC1UZXN0LTAxACU+PXqYnPYI
+gGYdDrpN5PljQAAht3pYTN4bNgtA6oRp/sEVIrSXZiEkZPRGsnqlGPGFRHn3MMsDZBz/FhZGdE1m2FnD
+YYgQMg=="
+ */
+int get_chip_security_context(
+	struct chip_security_context *context,
+	struct pubkey *pubkey)
+{
+	const struct chip_security_context c = {
+		3, 0x42,
+		RDA_SE_CFG_SECURITY_ENABLE_BIT |
+		RDA_SE_CFG_INDIRECT_SIGN_BIT |
+		RDA_SE_CFG_UNLOCK_ALLOWED
+	};
+	const struct pubkey pk = {
+		/* Public key: rdatest.pub */
+		{'R','D','A','S'}, {'E','d'},{}, "RDA PDL-Test-01 ",
+		{ 0x25,0x3e,0x3d,0x7a,0x98,0x9c,0xf6,0x08  },
+		{ 0x7b,0x4a,0x5a,0xa8,0xa1,0xda,0x92,0xea,0x9e,0x90,0xa8,0x7e,
+		  0xfa,0x76,0x37,0x52,0xe0,0xe0,0x40,0x63,0x09,0x02,0xd3,0x86,
+		  0x8b,0x9d,0xe0,0xae,0xf3,0x57,0xd7,0x44  }
+	};
+
+	// Set the hardcoded debug public key and context
+	*context = c;
+	*pubkey = pk;
+
+	return ROM_API_SECURITY_ENABLED;
+}
+#endif
+
+
+
+#ifdef RDA8810_VENDOR_EFUSE_WORKAROUND
+
+#include <common.h>
+#include <asm/arch/rda_crypto.h>
+#include <asm/arch/ispi.h>
+
+#define RDA_EFUSE_INDEX_SECURITY        (11)
+
+/*
+  Fuse layout:
+	VVVVVVVV.T.H.I.S.KKKK
+  VVVVVVVV: Vendor ID - 6bit + 2bit armour
+         T: Trace disable
+         H: Host serial disable
+         I: Indirectly signed image
+         S: Security enable
+      KKKK: RDA Public Key Index - 3bit + 1 bit armour
+*/
+/* define bit for rda se config */
+#define RDA_SE_CFG_KEY_INDEX(n)         (((n)&0xF)<<0)
+#define RDA_SE_CFG_GET_KEY_INDEX(r)     (((r)>>0)&0xF)
+#define RDA_SE_CFG_SECURITY_ENABLE_BIT  (1<<4)
+#define RDA_SE_CFG_INDIRECT_SIGN_BIT    (1<<5)
+#define RDA_SE_CFG_HOST_DISABLE_BIT     (1<<6)
+#define RDA_SE_CFG_TRACE_DISABLE_BIT    (1<<7)
+#define RDA_SE_CFG_VENDOR_ID(n)         (((n)&0xFF)<<8)
+#define RDA_SE_CFG_GET_VENDOR_ID(r)     (((r)>>8)&0xFF)
+
+// RDA Public Key index map
+//   (armour 6 indexes in 4 bits)
+static const uint8_t keyindex_map[16] = {
+	15, 15, 15,  0, 15,  1,  2, 15,
+	15,  3,  4, 15,  5, 15, 15, 15
+};
+
+// Vendor ID
+//   (armour 50 vendor ID'd in 8 bits)
+static int valid_vendor_id( unsigned vendor )
+{
+	unsigned c;
+	unsigned i = vendor >> 2;
+	c = ((i & 0xaa)>>1) + (i & 0x55);
+	c = ((c & 0xcc)>>2) + (c & 0x33);
+	c = ((c & 0xf0)>>4) + (c & 0x0f);
+	return ((vendor & 3) + c) == 5;
+}
+#endif
+
+
+
+
+#ifndef RDA_CRYPTO_DEBUG_FAKE_ROMCERT
+int get_chip_security_context(
+	struct chip_security_context *context,
+	struct pubkey *pubkey)
+{
+	int ret = romapi->get_chip_security_context(context, pubkey);
+
+#ifdef RDA8810_VENDOR_EFUSE_WORKAROUND
+	if (ret == ROM_API_INVALID_VENDOR_ID && romapi->version == 100) {
+		uint16_t sec = rda_read_efuse(RDA_EFUSE_INDEX_SECURITY);
+
+		// check validity of key index
+		int key = keyindex_map[RDA_SE_CFG_GET_KEY_INDEX(sec)];
+
+		// check validity of vendor id
+		int vendor = RDA_SE_CFG_GET_VENDOR_ID(sec);
+		if (valid_vendor_id(vendor)) {
+			context->rda_key_index = key;
+			context->vendor_id = vendor;
+			ret = 0;
+		}
+	}
+#endif
+	return ret;
+}
+#endif
diff --git a/arch/arm/cpu/armv7/rda/rda_sys.c b/arch/arm/cpu/armv7/rda/rda_sys.c
new file mode 100644
index 0000000000..2e612a358a
--- /dev/null
+++ b/arch/arm/cpu/armv7/rda/rda_sys.c
@@ -0,0 +1,507 @@
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/reg_sysctrl.h>
+#include <asm/arch/reg_md_sysctrl.h>
+#include <asm/arch/reg_cfg_regs.h>
+#include <asm/arch/reg_keypad.h>
+#include <asm/arch/reg_gpio.h>
+#include <asm/arch/hwcfg.h>
+#include <asm/arch/ispi.h>
+#include <asm/arch/reg_md_sysctrl.h>
+#include <asm/arch/hwcfg.h>
+#include <asm/arch/rda_sys.h>
+#include <asm/arch/spl_board_info.h>
+#ifdef CONFIG_CMD_MISC
+#include <usb/usbserial.h>
+#include <asm/arch/mdcom.h>
+#endif
+
+#define RDA_AP_MBX_HWCFG_SWCFG_ADD	(RDA_MD_MAILBOX_BASE + 0x1AE0)
+#define RDA_HWCFG_SWCFG			(*(u32 *)RDA_AP_MBX_HWCFG_SWCFG_ADD)
+
+/*
+ * Hardware and software configuration
+ */
+void hwcfg_swcfg_init(void)
+{
+	u16 hwcfg, swcfg;
+
+	RDA_HWCFG_SWCFG = hwp_sysCtrlMd->Reset_Cause;
+
+	hwcfg = rda_hwcfg_reg_get();
+	swcfg = rda_swcfg_reg_get();
+
+	/* clear the sw boot modes handled by bootloader */
+	rda_swcfg_reg_set(swcfg & ~(RDA_SW_CFG_BIT_2 |
+				RDA_SW_CFG_BIT_3 |
+				RDA_SW_CFG_BIT_4 |
+				RDA_SW_CFG_BIT_5 |
+				RDA_SW_CFG_BIT_6));
+
+	/* clear the hw boot modes for download/factory modes */
+	rda_hwcfg_reg_set(hwcfg & ~(RDA_HW_CFG_BIT_10 |
+				RDA_HW_CFG_BIT_11 |
+				RDA_HW_CFG_BIT_12 |
+				RDA_HW_CFG_BIT_13 |
+				RDA_HW_CFG_BIT_14 |
+				RDA_HW_CFG_BIT_15));
+
+}
+
+void rda_hwcfg_reg_set(u16 hwcfg)
+{
+	hwp_sysCtrlMd->Reset_Cause = SET_BITFIELD(hwp_sysCtrlMd->Reset_Cause,
+			SYS_CTRL_BOOT_MODE, hwcfg);
+	hwp_sysCtrlAp->Reset_Cause = hwp_sysCtrlMd->Reset_Cause;
+}
+
+u16 rda_hwcfg_reg_get(void)
+{
+	u16 hwcfg = GET_BITFIELD(hwp_sysCtrlMd->Reset_Cause, SYS_CTRL_BOOT_MODE);
+	return hwcfg;
+}
+
+u16 rda_hwcfg_get(void)
+{
+	u16 hwcfg = GET_BITFIELD(RDA_HWCFG_SWCFG, SYS_CTRL_BOOT_MODE);
+	return hwcfg;
+}
+
+void rda_swcfg_reg_set(u16 swcfg)
+{
+	hwp_sysCtrlMd->Reset_Cause = SET_BITFIELD(hwp_sysCtrlMd->Reset_Cause,
+			SYS_CTRL_SW_BOOT_MODE, swcfg);
+	hwp_sysCtrlAp->Reset_Cause = hwp_sysCtrlMd->Reset_Cause;
+}
+
+u16 rda_swcfg_reg_get(void)
+{
+	u16 swcfg = GET_BITFIELD(hwp_sysCtrlMd->Reset_Cause, SYS_CTRL_SW_BOOT_MODE);
+	return swcfg;
+}
+
+u16 rda_swcfg_get(void)
+{
+	u16 swcfg = GET_BITFIELD(RDA_HWCFG_SWCFG, SYS_CTRL_SW_BOOT_MODE);
+	return swcfg;
+}
+
+u16 rda_prod_id_get(void)
+{
+	u16 prod_id = GET_BITFIELD(hwp_configRegs->CHIP_ID, CFG_REGS_PROD_ID);
+	return prod_id;
+}
+
+u16 rda_metal_id_get(void)
+{
+	u16 metal_id = GET_BITFIELD(hwp_configRegs->CHIP_ID, CFG_REGS_METAL_ID);
+	return metal_id;
+}
+
+u16 rda_bond_id_get(void)
+{
+	u16 bond_id = GET_BITFIELD(hwp_configRegs->CHIP_ID, CFG_REGS_BOND_ID);
+	return bond_id;
+}
+
+void rda_nand_iodrive_set(void)
+{
+	u32 value = hwp_configRegs->IO_Drive1_Select & (~ CFG_REGS_NFLSH_DRIVE_MASK);
+
+	 hwp_configRegs->IO_Drive1_Select = value | CFG_REGS_NFLSH_DRIVE_SLOW_AND_WEAK;
+}
+
+/*
+ * System-level control
+ */
+enum media_type rda_media_get(void)
+{
+#ifdef CONFIG_SDMMC_BOOT
+	return MEDIA_MMC;
+#else
+	u16 hwcfg = rda_hwcfg_get();
+#ifdef CONFIG_MACH_RDA8810H
+/*
+ * HW BOOT MODE
+ *
+ * BIT_2   BIT1   BIT0         MODE
+ *    0     0       0          emmc
+ *    0     0       1          spi nand
+ *    0     1       0          spi nor
+ *    0     1       1          t-card0(run)
+ *    1     0       0          t-card1(update)
+ *    1     0       1          nand 8bit
+ *    1     1       0          nand 16bit
+ *    1     1       1          reserved
+ */
+	u32 bm_media = RDA_HW_CFG_GET_BM_IDX(hwcfg);
+
+	if (bm_media == RDA_MODE_EMMC)
+		return MEDIA_MMC;
+	else if (bm_media == RDA_MODE_SPINAND)
+		return MEDIA_SPINAND;
+	else if ((bm_media == RDA_MODE_NAND_8BIT)
+		|| (bm_media == RDA_MODE_NAND_16BIT))
+		return MEDIA_NAND;
+#else
+	u16 metal_id = rda_metal_id_get();
+	u16 prod_id = rda_prod_id_get();
+	u16 metal_new_bm;
+
+	if (prod_id == 0x8810)
+		metal_new_bm = 0xB;
+	else if (prod_id == 0x810E || prod_id == 0x8850 || prod_id == 0x850E)
+		metal_new_bm = 0x2;
+	else
+		metal_new_bm = 0;
+
+	if (metal_id < metal_new_bm) {
+		/* SDMMC or SPI NAND */
+		if (hwcfg & RDA_HW_CFG_BIT_3) {
+			if (hwcfg & RDA_HW_CFG_BIT_7)
+				return MEDIA_MMC;
+			else
+				return MEDIA_NAND;
+		} else if (hwcfg & RDA_HW_CFG_BIT_4) {
+			return MEDIA_MMC;
+		}
+		/* EMMC */
+		if (hwcfg & RDA_HW_CFG_BIT_2)
+			return MEDIA_MMC;
+		/* PARALLEL NAND */
+		if (!(hwcfg & RDA_HW_CFG_BIT_4))
+			return MEDIA_NAND;
+
+	} else {
+		/* SPI NAND */
+		if (hwcfg & RDA_HW_CFG_BIT_3)
+			return MEDIA_NAND;
+		/* EMMC */
+		if (hwcfg & RDA_HW_CFG_BIT_2)
+			return MEDIA_MMC;
+		/* PARALLEL NAND */
+		if (!(hwcfg & RDA_HW_CFG_BIT_4))
+			return MEDIA_NAND;
+	}
+#endif
+#endif
+	return MEDIA_UNKNOWN;
+}
+
+void reset_cpu(ulong addr)
+{
+#ifdef CONFIG_RDA_PDL
+	enable_charger(1);
+#endif
+
+	while (1) {
+		/* to unlock first */
+		hwp_sysCtrlMd->REG_DBG = 0xa50001;
+		/* reset */
+		hwp_sysCtrlMd->Sys_Rst_Set |= SYS_CTRL_SOFT_RST;
+	}
+}
+
+void shutdown_system(void)
+{
+#ifdef CONFIG_RDA_PDL
+	enable_charger(1);
+#endif
+
+	while (1) {
+		/* to unlock first */
+		hwp_sysCtrlMd->REG_DBG = 0xa50001;
+		/* shutdown */
+		hwp_sysCtrlMd->WakeUp = 0;
+	}
+}
+
+int rda_bm_is_calib(void)
+{
+	u16 swcfg = rda_swcfg_get();
+	return !!(swcfg & RDA_SW_CFG_BIT_4);
+}
+
+int rda_bm_is_autocall(void)
+{
+	u16 swcfg = rda_swcfg_get();
+	return !!(swcfg & RDA_SW_CFG_BIT_5);
+}
+
+int rda_bm_is_download(void)
+{
+#ifdef CONFIG_RDA_PDL /* for PDL mode, always enable download mode */
+	return 1;
+#else
+	u16 hwcfg = rda_hwcfg_get();
+	return !!(hwcfg & RDA_HW_CFG_BIT_11);
+#endif
+}
+
+/* Check if download keys are pressed. */
+int rda_bm_download_key_pressed(void)
+{
+	int key_power = !!(hwp_apKeypad->KP_STATUS & KEYPAD_KP_ON);
+	int key_vol_up = !!(hwp_apGpioD->gpio_val & 0x40); /* GPIO D6 */
+#ifdef CONFIG_SDMMC_BOOT
+	int key_vol_down = !!(hwp_apGpioD->gpio_val & 0x20); /* GPIO D5 */
+	return (key_power && key_vol_up && !key_vol_down);
+#else
+	return (key_power && key_vol_up);
+#endif
+}
+
+void rda_reboot(enum reboot_type type)
+{
+	u16 hwcfg = rda_hwcfg_reg_get();
+	u16 swcfg = rda_swcfg_reg_get();
+	int key_vol_down;
+
+	hwcfg &= ~(RDA_HW_CFG_BIT_10 | RDA_HW_CFG_BIT_11 |
+		RDA_HW_CFG_BIT_12 | RDA_HW_CFG_BIT_13 |
+		RDA_HW_CFG_BIT_14 | RDA_HW_CFG_BIT_15);
+
+	switch (type) {
+	case REBOOT_TO_DOWNLOAD_MODE:
+		hwcfg |= RDA_HW_CFG_BIT_11 | RDA_HW_CFG_BIT_12 |
+			RDA_HW_CFG_BIT_14;
+		key_vol_down = !!(hwp_apGpioD->gpio_val & 0x20); /* GPIO D5 */
+		if (key_vol_down)
+			hwcfg |= RDA_HW_CFG_BIT_10 | RDA_HW_CFG_BIT_13;
+		break;
+	case REBOOT_TO_FASTBOOT_MODE:
+		swcfg |= RDA_SW_CFG_BIT_2;
+		break;
+	case REBOOT_TO_RECOVERY_MODE:
+		swcfg |= RDA_SW_CFG_BIT_3;
+		break;
+	case REBOOT_TO_CALIB_MODE:
+		swcfg |= RDA_SW_CFG_BIT_4;
+		break;
+	case REBOOT_TO_PDL2_MODE:
+		swcfg |= RDA_SW_CFG_BIT_6;
+		break;
+	default:
+		break;
+	}
+
+	rda_hwcfg_reg_set(hwcfg);
+	rda_swcfg_reg_set(swcfg);
+	reset_cpu(0);
+}
+
+void enable_vibrator(int enable)
+{
+	u32 value;
+
+	ispi_open(1);
+
+	value = ispi_reg_read(0x03);
+
+	if (enable)
+		value |= 0x20;
+	else
+		value &= ~0x20;
+	if (rda_metal_id_get() >= 9)
+		value ^= 0x20;
+
+	ispi_reg_write(0x03, value);
+
+	ispi_open(0);
+}
+
+void enable_charger(int enable)
+{
+	u32 val;
+
+	ispi_open(1);
+	val = ispi_reg_read(0x15);
+	if (enable) {
+		val &= ~((1 << 15) | (1 << 14));
+	} else {
+		val |= (1 << 15);
+		val &= ~(1 << 14);
+	}
+	ispi_reg_write(0x15, val);
+	ispi_open(0);
+}
+
+void rda_dump_buf(char *data, size_t len)
+{
+    char temp_buf[64];
+    size_t i, off = 0;
+
+    memset(temp_buf, 0, 64);
+    for (i=0;i<len;i++) {
+        if(i%8 == 0) {
+            sprintf(&temp_buf[off], "  ");
+            off += 2;
+        }
+        sprintf(&temp_buf[off], "%02x ", data[i]);
+        off += 3;
+        if((i+1)%16 == 0 || (i+1) == len) {
+            printf("%8d %s\n", (unsigned int)i/16,temp_buf);
+            memset(temp_buf, 0, 64);
+            off = 0;
+        }
+    }
+    printf("\n");
+}
+
+void print_cur_time(void)
+{
+	unsigned long long time = ticks2usec(get_ticks());
+	printf("\n****** [CURRENT TIME: %3d.%06d] ******\n\n",
+			(int)(time / 1000000),
+			(int)(time % 1000000));
+}
+
+#ifdef CONFIG_CMD_MISC
+
+int usb_cable_connected(void)
+{
+	u32 val;
+
+	ispi_open(1);
+	val = ispi_reg_read(0x14);
+	ispi_open(0);
+	if (val & (1 << 8))
+		return 1;
+	else
+		return 0;
+}
+
+int system_rebooted(void)
+{
+	static int system_rebooted_flag = -1;
+
+	if (system_rebooted_flag == -1) {
+		if (rda_mdcom_system_started_before())
+			system_rebooted_flag = 1;
+		else
+			system_rebooted_flag = 0;
+		rda_mdcom_set_system_started_flag();
+	}
+	return system_rebooted_flag;
+}
+
+static int boot_key_long_pressed = 0;
+
+void save_current_boot_key_state(void)
+{
+	int boot_key_on = ((hwp_apKeypad->KP_STATUS & KEYPAD_KP_ON) != 0);
+	int start_by_boot_key = ((rda_hwcfg_get() & RDA_HW_CFG_BIT_12) != 0);
+	boot_key_long_pressed = (boot_key_on && start_by_boot_key);
+}
+
+int get_saved_boot_key_state(void)
+{
+	return boot_key_long_pressed;
+}
+
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	struct spl_security_info *info = get_bd_spl_security_info();
+	const uint32_t *id256 = (uint32_t *)info->chip_unique_id.id;
+
+	serialnr->low = id256[0];
+	serialnr->high = id256[1];
+
+	if ((serialnr->low | serialnr->high) == 0) {
+		serialnr->low  = 0x90abcdef;
+		serialnr->high = 0x12345678;
+	}
+
+	/* Set serialno enviroment variable */
+	char tmp[32];
+	sprintf(tmp, "%08x%08x", serialnr->high, serialnr->low);
+	setenv("serialno", tmp);
+}
+
+static int boot_mode = RDA_BM_NORMAL;
+
+void rda_bm_init(void)
+{
+	u16 hwcfg = rda_hwcfg_get();
+	u16 swcfg = rda_swcfg_get();
+#ifndef CONFIG_RDA_PDL
+	int rebooted = system_rebooted();
+	u32 fastboot_key_mask, all_key_mask;
+#endif
+	char str[2];
+	struct tag_serialnr serialnr;
+	get_board_serial(&serialnr);
+
+	printf("RDA: HW_CFG 0x%04x\n", hwcfg);
+	printf("RDA: SW_CFG 0x%04x\n", swcfg);
+	printf("RDA: ID PROD %04x M %03x B %01x\n",
+		rda_prod_id_get(), rda_metal_id_get(),
+		rda_bond_id_get());
+
+#ifdef CONFIG_RDA_PDL
+	/* PDL: always enable download mode */
+	boot_mode = RDA_BM_FORCEDOWNLOAD;
+#else
+	/* SPL */
+	boot_mode = RDA_BM_NORMAL;
+
+	if (swcfg & RDA_SW_CFG_BIT_2) {
+		boot_mode = RDA_BM_FASTBOOT;
+	} else if (swcfg & RDA_SW_CFG_BIT_3) {
+		boot_mode = RDA_BM_RECOVERY;
+	} else if (swcfg & RDA_SW_CFG_BIT_4) {
+		boot_mode = RDA_BM_CALIB;
+	} else if (swcfg & RDA_SW_CFG_BIT_5) {
+		boot_mode = RDA_BM_AUTOCALL;
+	} else if (swcfg & RDA_SW_CFG_BIT_6) {
+		/* force to 'pdl2', called by kernel */
+		boot_mode = RDA_BM_FORCEDOWNLOAD;
+	} else if ((hwcfg & RDA_HW_CFG_BIT_10) && (hwcfg & RDA_HW_CFG_BIT_11)) {
+		/*
+		 * If power key, vol-up, and vol-down are all pressed, consider
+		 * it as normal boot (for T-Card)
+		 */
+		boot_mode = RDA_BM_NORMAL;
+	} else if ((hwcfg & RDA_HW_CFG_BIT_10) && !rebooted) {
+		/* Distinguish between factory mode and h/w force reset */
+		boot_mode = RDA_BM_FACTORY;
+	} else if (hwcfg & RDA_HW_CFG_BIT_11) {
+		/* Force download mode for pdl2 */
+		boot_mode = RDA_BM_FORCEDOWNLOAD;
+	} else if (usb_cable_connected()) {
+		all_key_mask = RDA_HW_CFG_BIT_15 | RDA_HW_CFG_BIT_14 |
+			RDA_HW_CFG_BIT_13 | RDA_HW_CFG_BIT_12 |
+			RDA_HW_CFG_BIT_11 | RDA_HW_CFG_BIT_10;
+		/* Fastboot keys are volume-up + volume-down keys */
+		fastboot_key_mask = RDA_HW_CFG_BIT_13 | RDA_HW_CFG_BIT_14;
+
+		if ((hwcfg & fastboot_key_mask) == fastboot_key_mask &&
+			(hwcfg & all_key_mask & ~fastboot_key_mask) == 0) {
+			/*
+			 * All the keys are up, except for the fastboot keys;
+			 * and the usb cable is plugged in
+			 */
+			boot_mode = RDA_BM_FASTBOOT;
+		}
+	}
+#endif /* !CONFIG_RDA_PDL */
+
+	printf("RDA: Boot_Mode %d\n", boot_mode);
+
+	sprintf(str, "%1d", boot_mode);
+	setenv ("bootmode", str);
+}
+
+enum rda_bm_type rda_bm_get(void)
+{
+	return boot_mode;
+}
+
+void rda_bm_set(enum rda_bm_type bm)
+{
+	boot_mode = bm;
+}
+
+#endif /* CONFIG_CMD_MISC */
+
diff --git a/arch/arm/cpu/armv7/rda/serial.c b/arch/arm/cpu/armv7/rda/serial.c
new file mode 100644
index 0000000000..f7c1d2d244
--- /dev/null
+++ b/arch/arm/cpu/armv7/rda/serial.c
@@ -0,0 +1,132 @@
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+#include <asm/arch/reg_sysctrl.h>
+#include <asm/arch/reg_uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void _serial_set_baudrate(int rate)
+{
+    hwp_sysCtrlAp->Cfg_Clk_Uart[2] = 0x36;        // 115200 @ 26MHz
+    //hwp_sysCtrlAp->Cfg_Clk_Uart[2] = 0x05;        // 921600 @ 26MHz
+}
+
+void _serial_enable_rtscts(void)
+{
+     hwp_uart->ctrl |= UART_AUTO_FLOW_CONTROL;
+}
+
+void _serial_disable_rtscts(void)
+{
+     hwp_uart->ctrl &= ~UART_AUTO_FLOW_CONTROL;
+}
+
+void _serial_init(void)
+{
+    _serial_set_baudrate(CONFIG_BAUDRATE);
+    hwp_uart->triggers            = UART_AFC_LEVEL(1); //7 ?
+
+    hwp_uart->ctrl                = UART_ENABLE | UART_DATA_BITS_8_BITS |
+        UART_TX_STOP_BITS_1_BIT | UART_PARITY_ENABLE_NO;
+
+    /* Allow reception */
+    hwp_uart->CMD_Set             = UART_RTS;
+}
+
+void _serial_deinit(void)
+{
+    hwp_uart->ctrl    = 0;
+    hwp_uart->CMD_Clr = UART_RTS;
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+int _serial_tstc(const int port)
+{
+    return (GET_BITFIELD(hwp_uart->status, UART_RX_FIFO_LEVEL));
+}
+
+int _serial_getc(const int port)
+{
+    /* wait for character to arrive */ ;
+    while (!(GET_BITFIELD(hwp_uart->status, UART_RX_FIFO_LEVEL)))
+        ;
+
+    return (hwp_uart->rxtx_buffer & 0xff);
+}
+
+void _serial_putc_hw(const char c, const int port)
+{
+    // Place in the TX Fifo ?
+    while (!(GET_BITFIELD(hwp_uart->status, UART_TX_FIFO_SPACE)))
+        ;
+    hwp_uart->rxtx_buffer = (u32)c;
+}
+
+void _serial_putc(const char c, const int port)
+{
+    if (c == '\n') {
+        _serial_putc_hw('\r', 0); 
+    }
+    _serial_putc_hw(c, 0);
+}
+
+void _serial_puts(const char *s, const int port)
+{
+    while (*s) {
+        _serial_putc(*s++, 0);
+    }
+}
+
+static int hwflow = 0; /* turned off by default */
+int hwflow_onoff(int on)
+{
+	switch(on) {
+	case 0:
+	default:
+		break; /* return current */
+	case 1:
+		hwflow = 1;
+		_serial_enable_rtscts(); /* turn on */
+		break;
+	case -1:
+		hwflow = 0;
+		_serial_disable_rtscts(); /* turn off */
+		break;
+	}
+	return hwflow;
+}
+
+int serial_init(void)
+{
+    //_serial_init(); // already init in boot_test
+    return 0;
+}
+
+int serial_getc(void)
+{
+    return _serial_getc(0);
+}
+
+int serial_tstc(void)
+{
+    return _serial_tstc(0);
+}
+
+void serial_putc(const char c)
+{
+    _serial_putc(c, 0);
+}
+
+void serial_puts(const char *s)
+{
+    _serial_puts(s, 0);
+}
+
+void serial_setbrg (void)
+{
+}
+
diff --git a/arch/arm/cpu/armv7/rda/spl.c b/arch/arm/cpu/armv7/rda/spl.c
new file mode 100644
index 0000000000..93bbb85c42
--- /dev/null
+++ b/arch/arm/cpu/armv7/rda/spl.c
@@ -0,0 +1,189 @@
+#include <common.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <nand.h>
+#include <malloc.h>
+#include <image.h>
+#include <usb/usbserial.h>
+#include <asm/arch/rda_sys.h>
+#include <asm/arch/spl_board_info.h>
+#include <asm/arch/rda_crypto.h>
+#include <pdl.h>
+
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+
+DECLARE_GLOBAL_DATA_PTR;
+/* Define global data structure pointer to it*/
+static gd_t gdata __attribute__ ((section(".data")));
+static bd_t bdata __attribute__ ((section(".data")));
+
+#else
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
+
+void putc(char c)
+{
+}
+
+#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
+
+void board_init_f(ulong dummy)
+{
+	relocate_code(CONFIG_SPL_STACK, NULL, CONFIG_SPL_TEXT_BASE);
+}
+
+#ifdef CONFIG_SPL_CHECK_IMAGE
+int check_uimage(unsigned int *buf)
+{
+	image_header_t *hdr = (image_header_t *)buf;
+	puts("Check Image ");
+	if (!image_check_magic(hdr)) {
+		printf("Magic Error %x\n", image_get_magic(hdr));
+		rda_dump_buf((char *)buf, 256);
+		return -1;
+	}
+	puts(".");
+	if (!image_check_hcrc(hdr)) {
+		printf("HCRC Error %x\n", image_get_hcrc(hdr));
+		rda_dump_buf((char *)buf, 256);
+		return -2;
+	}
+	puts(".");
+	if (!image_check_dcrc(hdr)) {
+		printf("DCRC Error %x\n", image_get_dcrc(hdr));
+		rda_dump_buf((char *)buf, 256);
+		//rda_dump_buf(buf, 
+		//	image_get_header_size() + image_get_size(hdr));
+		return -3;
+	}
+	puts(".");
+#ifdef CONFIG_SIGNATURE_CHECK_IMAGE
+	if (image_sign_verify_uimage(hdr) != 0) {
+		printf("Image Signature check failed!\n");
+		return -4;
+	}
+#endif
+	puts(" Done\n");
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_EMMC_LOAD
+extern void emmc_init(void);
+extern void emmc_boot(void);
+#endif
+
+#ifdef CONFIG_SPL_XMODEM_LOAD
+extern void xmodem_boot(void);
+#endif
+
+extern void hwcfg_swcfg_init(void);
+extern int clock_init(void);
+
+
+#ifdef CONFIG_SIGNATURE_CHECK_IMAGE
+static const uint8_t *get_spl_load_addr(void)
+{
+	const uint8_t *spl_image = (uint8_t*)CONFIG_SPL_LOAD_ADDRESS + CONFIG_UIMAGEHDR_SIZE;
+	return spl_image;
+}
+#endif
+
+void board_init_r(gd_t *id, ulong dummy)
+{
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+	gd = &gdata;
+	gd->bd = &bdata;
+	gd->flags |= GD_FLG_RELOC;
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init();          /* serial communications setup */
+	gd->have_console = 1;
+#endif
+	hwcfg_swcfg_init();
+	clock_init();
+
+#ifdef CONFIG_SIGNATURE_CHECK_IMAGE
+	// Set the security contex (or get the unique ID of the device)
+	struct spl_security_info *info = get_bd_spl_security_info();
+	const uint8_t *spl_image = get_spl_load_addr();
+
+	puts("SETTING SECURITY CONTEXT\n");
+	set_security_context(info, spl_image);
+#endif
+
+#ifndef CONFIG_RDA_PDL
+	/* Note BIT3 for SPINAND got higher priority */
+#ifdef CONFIG_SPL_EMMC_SUPPORT
+	if (rda_media_get() == MEDIA_MMC) {
+		puts("Init emmc ...\n");
+		emmc_init();
+	}
+#endif
+
+#ifdef CONFIG_SPL_NAND_SUPPORT
+	if (rda_media_get() == MEDIA_NAND || rda_media_get() == MEDIA_SPINAND) {
+		puts("Init nand ...\n");
+		nand_init();
+	}
+#endif
+#endif
+
+#ifdef CONFIG_RDA_PDL
+	drv_usbser_init();
+	pdl_main();
+#else
+	/* A workaround to handle the timing issue when detecting
+	 * download mode in h/w */
+	if( !rda_bm_is_autocall() &&
+		!rda_bm_is_calib() &&
+		!rda_bm_is_download() &&
+		rda_bm_download_key_pressed()) {
+		puts("Download key pressed. Enter download mode ...\n");
+		rda_reboot(REBOOT_TO_DOWNLOAD_MODE);
+	}
+#endif
+
+#ifdef CONFIG_SPL_EMMC_LOAD
+	if (rda_media_get() == MEDIA_MMC) {
+		puts("EMMC boot ...\n");
+		emmc_boot();
+	}
+#endif
+
+#ifdef CONFIG_SPL_NAND_LOAD
+	if (rda_media_get() == MEDIA_NAND || rda_media_get() == MEDIA_SPINAND) {
+		puts("NAND boot ...\n");
+		nand_boot();
+	}
+#endif
+
+#ifdef CONFIG_SPL_SPI_LOAD
+	mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN,
+			CONFIG_SYS_MALLOC_LEN);
+
+	gd = &gdata;
+	gd->bd = &bdata;
+	gd->flags |= GD_FLG_RELOC;
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init();          /* serial communications setup */
+	gd->have_console = 1;
+
+	puts("SPI boot...\n");
+	spi_boot();
+#endif
+
+#ifdef CONFIG_SPL_XMODEM_LOAD
+	puts("Xmodem boot ...\n");
+	xmodem_boot();
+#endif
+
+	/*
+	should never go here
+	*/
+	while(1)
+	;
+}
diff --git a/arch/arm/cpu/armv7/rda/timer.c b/arch/arm/cpu/armv7/rda/timer.c
new file mode 100644
index 0000000000..9da8958dc2
--- /dev/null
+++ b/arch/arm/cpu/armv7/rda/timer.c
@@ -0,0 +1,132 @@
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+#include <asm/arch/reg_timer.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+typedef union
+{
+    unsigned long long timer;
+    struct
+    {
+        unsigned long  timer_l     :32;
+        unsigned long  timer_h     :32;
+    } fields;
+} RDA_TIMER;
+
+#if (CONFIG_SYS_HZ_CLOCK == 2000000)
+/* optimize for 2M Hz */
+static unsigned long tick_to_ms(unsigned long long tick) __attribute__((unused));
+static unsigned long tick_to_ms(unsigned long long tick)
+{
+    return (u32)(tick >> 11);  // divide 2048
+}
+
+static unsigned long long ms_to_tick(unsigned long ms)
+{
+    return (((unsigned long long)ms) << 11); // x 2048
+}
+
+static unsigned long tick_to_us(unsigned long long tick)
+{
+    return (unsigned long)(tick >> 1);    // divide 2
+}
+
+static unsigned long long us_to_tick(unsigned long ms)
+{
+    return (((unsigned long long)ms) << 1);  // x2
+}
+#else
+/* need to calc */
+#error "Timer is not 2M Hz"
+#endif
+
+static void rda_timer_get(RDA_TIMER *timer)
+{
+    /* always read low 32bit first */
+    timer->fields.timer_l = 
+        (unsigned long)(hwp_apTimer->HWTimer_LockVal_L);
+    timer->fields.timer_h = 
+        (unsigned long)(hwp_apTimer->HWTimer_LockVal_H);
+}
+
+static void rda_timeout_setup_ms(RDA_TIMER *timer, unsigned long ms)
+	__attribute__((unused));
+static void rda_timeout_setup_ms(RDA_TIMER *timer, unsigned long ms)
+{
+    timer->timer = get_ticks() + ms_to_tick(ms);
+}
+
+static void rda_timeout_setup_us(RDA_TIMER *timer, unsigned long us)
+{
+    timer->timer = get_ticks() + us_to_tick(us);
+}
+
+static int rda_timeout_check(RDA_TIMER *timer)
+{
+    return (get_ticks() > timer->timer);
+}
+
+int timer_init(void)
+{
+	gd->timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
+	gd->timer_reset_value = 0;
+
+	/* We are using timer34 in unchained 32-bit mode, full speed */
+	return(0);
+}
+
+void reset_timer(void)
+{
+	gd->timer_reset_value = get_ticks();
+}
+
+/*
+ * Get the current 64 bit timer tick count
+ */
+unsigned long long get_ticks(void)
+{
+    RDA_TIMER timer;
+
+    rda_timer_get(&timer);
+    return timer.timer;
+}
+
+ulong	usec2ticks    (unsigned long usec)
+{
+	return (ulong)us_to_tick(usec);
+}
+
+ulong	ticks2usec    (unsigned long ticks)
+{
+	return tick_to_us(ticks);
+}
+
+ulong get_timer(ulong base)
+{
+	unsigned long long timer_diff;
+
+	timer_diff = get_ticks() - gd->timer_reset_value;
+
+	return (timer_diff / (gd->timer_rate_hz / CONFIG_SYS_HZ)) - base;
+}
+
+void __udelay(unsigned long usec)
+{
+    RDA_TIMER timer;
+
+    rda_timeout_setup_us(&timer, usec);
+    while(!rda_timeout_check(&timer))
+        ;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ_CLOCK;
+}
diff --git a/arch/arm/cpu/armv7/rda/xmodem_boot.c b/arch/arm/cpu/armv7/rda/xmodem_boot.c
new file mode 100644
index 0000000000..48b3047f03
--- /dev/null
+++ b/arch/arm/cpu/armv7/rda/xmodem_boot.c
@@ -0,0 +1,75 @@
+#include <common.h>
+#include <asm/io.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <xyzModem.h>
+
+void _serial_enable_rtscts(void);
+#ifdef CONFIG_SPL_CHECK_IMAGE
+int check_uimage(unsigned int *buf);
+#endif
+
+static int getcxmodem(void) {
+	if (tstc())
+		return (getc());
+	return -1;
+}
+
+static ulong load_serial_xmodem (ulong offset)
+{
+	int size;
+	int err;
+	int res;
+	connection_info_t info;
+	char ymodemBuf[1024];
+	ulong store_addr = ~0;
+	ulong addr = 0;
+
+	size = 0;
+	info.mode = xyzModem_xmodem;
+	_serial_enable_rtscts();
+	mdelay(10);
+	res = xyzModem_stream_open (&info, &err);
+	if (!res) {
+		while ((res =
+			xyzModem_stream_read (ymodemBuf, 1024, &err)) > 0) {
+			store_addr = addr + offset;
+			size += res;
+			addr += res;
+			memcpy ((char *) (store_addr), ymodemBuf,res);
+		}
+	} else {
+		printf ("%s\n", xyzModem_error (err));
+	}
+
+	xyzModem_stream_close (&err);
+	xyzModem_stream_terminate (false, &getcxmodem);
+
+
+	flush_cache (offset, size);
+	printf("\nXmodem Download Success.\n");
+	printf("Total Size = 0x%08x = %d Bytes\n", size, size);
+
+	return offset;
+}
+
+void xmodem_boot(void)
+{
+	__attribute__((noreturn)) void (*uboot)(void);
+
+	load_serial_xmodem(CONFIG_SYS_XMODEM_U_BOOT_DST);
+
+#ifdef CONFIG_SPL_CHECK_IMAGE
+	if (check_uimage((unsigned int*)CONFIG_SYS_XMODEM_U_BOOT_DST)) {
+		printf("Xmodem boot failed.\n");
+		return;
+	}
+#endif
+
+	/*
+	 * Jump to U-Boot image
+	 */
+	printf("Running U-Boot ...\n");
+	uboot = (void *)CONFIG_SYS_XMODEM_U_BOOT_START;
+	(*uboot)();
+}
diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.S b/arch/arm/cpu/armv7/s5pc1xx/cache.S
index c7d62212bd..000192c254 100644
--- a/arch/arm/cpu/armv7/s5pc1xx/cache.S
+++ b/arch/arm/cpu/armv7/s5pc1xx/cache.S
@@ -25,20 +25,22 @@
 
 .align 5
 
+#include <linux/linkage.h>
+
 #ifndef CONFIG_SYS_L2CACHE_OFF
-.global v7_outer_cache_enable
-v7_outer_cache_enable:
+ENTRY(v7_outer_cache_enable)
 	push	{r0, r1, r2, lr}
 	mrc	15, 0, r3, cr1, cr0, 1
 	orr	r3, r3, #2
 	mcr	15, 0, r3, cr1, cr0, 1
 	pop	{r1, r2, r3, pc}
+ENDPROC(v7_outer_cache_enable)
 
-.global v7_outer_cache_disable
-v7_outer_cache_disable:
+ENTRY(v7_outer_cache_disable)
 	push	{r0, r1, r2, lr}
 	mrc	15, 0, r3, cr1, cr0, 1
 	bic	r3, r3, #2
 	mcr	15, 0, r3, cr1, cr0, 1
 	pop	{r1, r2, r3, pc}
+ENDPROC(v7_outer_cache_disable)
 #endif
diff --git a/arch/arm/cpu/armv7/s5pc1xx/reset.S b/arch/arm/cpu/armv7/s5pc1xx/reset.S
index 70fa146cf3..c7a41d03d2 100644
--- a/arch/arm/cpu/armv7/s5pc1xx/reset.S
+++ b/arch/arm/cpu/armv7/s5pc1xx/reset.S
@@ -22,12 +22,12 @@
  */
 
 #include <asm/arch/cpu.h>
+#include <linux/linkage.h>
 
 #define S5PC100_SWRESET			0xE0200000
 #define S5PC110_SWRESET			0xE0102000
 
-.globl reset_cpu
-reset_cpu:
+ENTRY(reset_cpu)
 	ldr	r1, =S5PC100_PRO_ID
 	ldr	r2, [r1]
 	ldr	r4, =0x00010000
@@ -45,3 +45,4 @@ reset_cpu:
 	str	r2, [r1]
 _loop_forever:
 	b	_loop_forever
+ENDPROC(reset_cpu)
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index ef08a55abc..3fd8ded9c6 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -31,8 +31,8 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <version.h>
 #include <asm/system.h>
+#include <linux/linkage.h>
 
 .globl _start
 _start: b	reset
@@ -158,7 +158,11 @@ reset:
 
 /* Set stackpointer in internal RAM to call board_init_f */
 call_board_init_f:
+#ifdef CONFIG_SPL_BUILD
+	ldr	sp, =(CONFIG_SPL_STACK)
+#else
 	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
+#endif
 	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
 	ldr	r0,=0x00000000
 	bl	board_init_f
@@ -172,8 +176,7 @@ call_board_init_f:
  * after relocating the monitor code.
  *
  */
-	.globl	relocate_code
-relocate_code:
+ENTRY(relocate_code)
 	mov	r4, r0	/* save addr_sp */
 	mov	r5, r1	/* save addr of gd */
 	mov	r6, r2	/* save addr of destination */
@@ -257,12 +260,17 @@ clear_bss:
 	add	r0, r0, r4
 	add	r1, r1, r4
 #endif
+
+	cmp	r0, r1
+	beq	clbss_d
+
 	mov	r2, #0x00000000		/* clear			    */
 
 clbss_l:str	r2, [r0]		/* clear loop...		    */
 	add	r0, r0, #4
 	cmp	r0, r1
 	bne	clbss_l
+clbss_d:
 
 /*
  * We are done. Do not return, instead branch to second part of board
@@ -289,6 +297,7 @@ jump_2_ram:
 
 _board_init_r_ofs:
 	.word board_init_r - _start
+ENDPROC(relocate_code)
 
 /*************************************************************************
  *
@@ -298,8 +307,7 @@ _board_init_r_ofs:
  * CONFIG_SYS_ICACHE_OFF is defined.
  *
  *************************************************************************/
-.globl cpu_init_cp15
-cpu_init_cp15:
+ENTRY(cpu_init_cp15)
 	/*
 	 * Invalidate L1 I/D
 	 */
@@ -325,7 +333,7 @@ cpu_init_cp15:
 #endif
 	mcr	p15, 0, r0, c1, c0, 0
 	mov	pc, lr			@ back to my caller
-
+ENDPROC(cpu_init_cp15)
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 /*************************************************************************
@@ -336,7 +344,7 @@ cpu_init_cp15:
  * setup memory timing
  *
  *************************************************************************/
-cpu_init_crit:
+ENTRY(cpu_init_crit)
 	/*
 	 * Jump to board specific initialization...
 	 * The Mask ROM will have already initialized
@@ -347,6 +355,7 @@ cpu_init_crit:
 	bl	lowlevel_init		@ go setup pll,mux,memory
 	mov	lr, ip			@ restore link
 	mov	pc, lr			@ back to my caller
+ENDPROC(cpu_init_crit)
 #endif
 
 #ifndef CONFIG_SPL_BUILD
diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile
index e9ac6c9a71..08c4137a34 100644
--- a/arch/arm/cpu/armv7/tegra2/Makefile
+++ b/arch/arm/cpu/armv7/tegra2/Makefile
@@ -27,6 +27,7 @@
 # flags for any startup files it might use.
 CFLAGS_arch/arm/cpu/armv7/tegra2/ap20.o += -march=armv4t
 CFLAGS_arch/arm/cpu/armv7/tegra2/clock.o += -march=armv4t
+CFLAGS_arch/arm/cpu/armv7/tegra2/warmboot_avp.o += -march=armv4t
 
 include $(TOPDIR)/config.mk
 
@@ -34,7 +35,10 @@ LIB	=  $(obj)lib$(SOC).o
 
 SOBJS	:= lowlevel_init.o
 COBJS-y	:= ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
+COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
+COBJS-$(CONFIG_TEGRA_PMU) += pmu.o
 COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
+COBJS-$(CONFIG_TEGRA2_LP0) += crypto.o warmboot.o warmboot_avp.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c
index b749821e5a..698bfd0e17 100644
--- a/arch/arm/cpu/armv7/tegra2/ap20.c
+++ b/arch/arm/cpu/armv7/tegra2/ap20.c
@@ -21,16 +21,53 @@
 * MA 02111-1307 USA
 */
 
-#include "ap20.h"
 #include <asm/io.h>
 #include <asm/arch/tegra2.h>
+#include <asm/arch/ap20.h>
 #include <asm/arch/clk_rst.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/fuse.h>
+#include <asm/arch/gp_padctrl.h>
 #include <asm/arch/pmc.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/scu.h>
+#include <asm/arch/warmboot.h>
 #include <common.h>
 
+int tegra_get_chip_type(void)
+{
+	struct apb_misc_gp_ctlr *gp;
+	struct fuse_regs *fuse = (struct fuse_regs *)TEGRA2_FUSE_BASE;
+	uint tegra_sku_id, rev;
+
+	/*
+	 * This is undocumented, Chip ID is bits 15:8 of the register
+	 * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
+	 * Tegra30
+	 */
+	gp = (struct apb_misc_gp_ctlr *)TEGRA2_APB_MISC_GP_BASE;
+	rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
+
+	tegra_sku_id = readl(&fuse->sku_info) & 0xff;
+
+	switch (rev) {
+	case CHIPID_TEGRA2:
+		switch (tegra_sku_id) {
+		case SKU_ID_T20:
+			return TEGRA_SOC_T20;
+		case SKU_ID_T25SE:
+		case SKU_ID_AP25:
+		case SKU_ID_T25:
+		case SKU_ID_AP25E:
+		case SKU_ID_T25E:
+			return TEGRA_SOC_T25;
+		}
+		break;
+	}
+	/* unknown sku id */
+	return TEGRA_SOC_UNKNOWN;
+}
+
 /* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */
 static int ap20_cpu_is_cortexa9(void)
 {
@@ -286,6 +323,11 @@ void init_pmc_scratch(void)
 
 	/* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
 	writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20);
+
+#ifdef CONFIG_TEGRA2_LP0
+	/* save Sdram params to PMC 2, 4, and 24 for WB0 */
+	warmboot_save_sdram_params();
+#endif
 }
 
 void tegra2_start(void)
diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c
index a797e6fc30..a50b1b988a 100644
--- a/arch/arm/cpu/armv7/tegra2/board.c
+++ b/arch/arm/cpu/armv7/tegra2/board.c
@@ -23,12 +23,12 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include "ap20.h"
+#include <asm/arch/ap20.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/funcmux.h>
+#include <asm/arch/pmc.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/tegra2.h>
-#include <asm/arch/pmc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/armv7/tegra2/clock.c
index 39376ab86e..ccad351639 100644
--- a/arch/arm/cpu/armv7/tegra2/clock.c
+++ b/arch/arm/cpu/armv7/tegra2/clock.c
@@ -410,6 +410,16 @@ enum clock_osc_freq clock_get_osc_freq(void)
 	return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
 }
 
+int clock_get_osc_bypass(void)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	reg = readl(&clkrst->crc_osc_ctrl);
+	return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
+}
+
 /* Returns a pointer to the registers of the given pll */
 static struct clk_pll *get_pll(enum clock_id clkid)
 {
@@ -420,6 +430,28 @@ static struct clk_pll *get_pll(enum clock_id clkid)
 	return &clkrst->crc_pll[clkid];
 }
 
+int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
+		u32 *divp, u32 *cpcon, u32 *lfcon)
+{
+	struct clk_pll *pll = get_pll(clkid);
+	u32 data;
+
+	assert(clkid != CLOCK_ID_USB);
+
+	/* Safety check, adds to code size but is small */
+	if (!clock_id_isvalid(clkid) || clkid == CLOCK_ID_USB)
+		return -1;
+	data = readl(&pll->pll_base);
+	*divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
+	*divn = (data & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT;
+	*divp = (data & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
+	data = readl(&pll->pll_misc);
+	*cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT;
+	*lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT;
+
+	return 0;
+}
+
 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
 		u32 divp, u32 cpcon, u32 lfcon)
 {
@@ -1027,7 +1059,10 @@ void clock_early_init(void)
 		clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
 		break;
 
-	case CLOCK_OSC_FREQ_13_0:
+	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+		clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8);
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
+		break;
 	case CLOCK_OSC_FREQ_19_2:
 	default:
 		/*
diff --git a/arch/arm/cpu/armv7/tegra2/crypto.c b/arch/arm/cpu/armv7/tegra2/crypto.c
new file mode 100644
index 0000000000..5f0b240e27
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/crypto.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010 - 2011 NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include "crypto.h"
+#include "aes.h"
+
+static u8 zero_key[16];
+
+#define AES_CMAC_CONST_RB 0x87  /* from RFC 4493, Figure 2.2 */
+
+enum security_op {
+	SECURITY_SIGN		= 1 << 0,	/* Sign the data */
+	SECURITY_ENCRYPT	= 1 << 1,	/* Encrypt the data */
+};
+
+static void debug_print_vector(char *name, u32 num_bytes, u8 *data)
+{
+	u32 i;
+
+	debug("%s [%d] @0x%08x", name, num_bytes, (u32)data);
+	for (i = 0; i < num_bytes; i++) {
+		if (i % 16 == 0)
+			debug(" = ");
+		debug("%02x", data[i]);
+		if ((i+1) % 16 != 0)
+			debug(" ");
+	}
+	debug("\n");
+}
+
+/**
+ * Apply chain data to the destination using EOR
+ *
+ * Each array is of length AES_AES_KEY_LENGTH.
+ *
+ * \param cbc_chain_data	Chain data
+ * \param src			Source data
+ * \param dst			Destination data, which is modified here
+ */
+static void apply_cbc_chain_data(u8 *cbc_chain_data, u8 *src, u8 *dst)
+{
+	int i;
+
+	for (i = 0; i < 16; i++)
+		*dst++ = *src++ ^ *cbc_chain_data++;
+}
+
+/**
+ * Encrypt some data with AES.
+ *
+ * \param key_schedule		Expanded key to use
+ * \param src			Source data to encrypt
+ * \param dst			Destination buffer
+ * \param num_aes_blocks	Number of AES blocks to encrypt
+ */
+static void encrypt_object(u8 *key_schedule, u8 *src, u8 *dst,
+			   u32 num_aes_blocks)
+{
+	u8 tmp_data[AES_KEY_LENGTH];
+	u8 *cbc_chain_data;
+	u32 i;
+
+	cbc_chain_data = zero_key;	/* Convenient array of 0's for IV */
+
+	for (i = 0; i < num_aes_blocks; i++) {
+		debug("encrypt_object: block %d of %d\n", i, num_aes_blocks);
+		debug_print_vector("AES Src", AES_KEY_LENGTH, src);
+
+		/* Apply the chain data */
+		apply_cbc_chain_data(cbc_chain_data, src, tmp_data);
+		debug_print_vector("AES Xor", AES_KEY_LENGTH, tmp_data);
+
+		/* encrypt the AES block */
+		aes_encrypt(tmp_data, key_schedule, dst);
+		debug_print_vector("AES Dst", AES_KEY_LENGTH, dst);
+
+		/* Update pointers for next loop. */
+		cbc_chain_data = dst;
+		src += AES_KEY_LENGTH;
+		dst += AES_KEY_LENGTH;
+	}
+}
+
+/**
+ * Shift a vector left by one bit
+ *
+ * \param in	Input vector
+ * \param out	Output vector
+ * \param size	Length of vector in bytes
+ */
+static void left_shift_vector(u8 *in, u8 *out, int size)
+{
+	int carry = 0;
+	int i;
+
+	for (i = size - 1; i >= 0; i--) {
+		out[i] = (in[i] << 1) | carry;
+		carry = in[i] >> 7;	/* get most significant bit */
+	}
+}
+
+/**
+ * Sign a block of data, putting the result into dst.
+ *
+ * \param key			Input AES key, length AES_KEY_LENGTH
+ * \param key_schedule		Expanded key to use
+ * \param src			Source data of length 'num_aes_blocks' blocks
+ * \param dst			Destination buffer, length AES_KEY_LENGTH
+ * \param num_aes_blocks	Number of AES blocks to encrypt
+ */
+static void sign_object(u8 *key, u8 *key_schedule, u8 *src, u8 *dst,
+			u32 num_aes_blocks)
+{
+	u8 tmp_data[AES_KEY_LENGTH];
+	u8 left[AES_KEY_LENGTH];
+	u8 k1[AES_KEY_LENGTH];
+	u8 *cbc_chain_data;
+	unsigned i;
+
+	cbc_chain_data = zero_key;	/* Convenient array of 0's for IV */
+
+	/* compute K1 constant needed by AES-CMAC calculation */
+	for (i = 0; i < AES_KEY_LENGTH; i++)
+		tmp_data[i] = 0;
+
+	encrypt_object(key_schedule, tmp_data, left, 1);
+	debug_print_vector("AES(key, nonce)", AES_KEY_LENGTH, left);
+
+	left_shift_vector(left, k1, sizeof(left));
+	debug_print_vector("L", AES_KEY_LENGTH, left);
+
+	if ((left[0] >> 7) != 0) /* get MSB of L */
+		k1[AES_KEY_LENGTH-1] ^= AES_CMAC_CONST_RB;
+	debug_print_vector("K1", AES_KEY_LENGTH, k1);
+
+	/* compute the AES-CMAC value */
+	for (i = 0; i < num_aes_blocks; i++) {
+		/* Apply the chain data */
+		apply_cbc_chain_data(cbc_chain_data, src, tmp_data);
+
+		/* for the final block, XOR K1 into the IV */
+		if (i == num_aes_blocks - 1)
+			apply_cbc_chain_data(tmp_data, k1, tmp_data);
+
+		/* encrypt the AES block */
+		aes_encrypt(tmp_data, key_schedule, dst);
+
+		debug("sign_obj: block %d of %d\n", i, num_aes_blocks);
+		debug_print_vector("AES-CMAC Src", AES_KEY_LENGTH, src);
+		debug_print_vector("AES-CMAC Xor", AES_KEY_LENGTH, tmp_data);
+		debug_print_vector("AES-CMAC Dst", AES_KEY_LENGTH, dst);
+
+		/* Update pointers for next loop. */
+		cbc_chain_data = dst;
+		src += AES_KEY_LENGTH;
+	}
+
+	debug_print_vector("AES-CMAC Hash", AES_KEY_LENGTH, dst);
+}
+
+/**
+ * Encrypt and sign a block of data (depending on security mode).
+ *
+ * \param key		Input AES key, length AES_KEY_LENGTH
+ * \param oper		Security operations mask to perform (enum security_op)
+ * \param src		Source data
+ * \param length	Size of source data
+ * \param sig_dst	Destination address for signature, AES_KEY_LENGTH bytes
+ */
+static int encrypt_and_sign(u8 *key, enum security_op oper, u8 *src,
+			    u32 length, u8 *sig_dst)
+{
+	u32 num_aes_blocks;
+	u8 key_schedule[AES_EXPAND_KEY_LENGTH];
+
+	debug("encrypt_and_sign: length = %d\n", length);
+	debug_print_vector("AES key", AES_KEY_LENGTH, key);
+
+	/*
+	 * The only need for a key is for signing/checksum purposes, so
+	 * if not encrypting, expand a key of 0s.
+	 */
+	aes_expand_key(oper & SECURITY_ENCRYPT ? key : zero_key, key_schedule);
+
+	num_aes_blocks = (length + AES_KEY_LENGTH - 1) / AES_KEY_LENGTH;
+
+	if (oper & SECURITY_ENCRYPT) {
+		/* Perform this in place, resulting in src being encrypted. */
+		debug("encrypt_and_sign: begin encryption\n");
+		encrypt_object(key_schedule, src, src, num_aes_blocks);
+		debug("encrypt_and_sign: end encryption\n");
+	}
+
+	if (oper & SECURITY_SIGN) {
+		/* encrypt the data, overwriting the result in signature. */
+		debug("encrypt_and_sign: begin signing\n");
+		sign_object(key, key_schedule, src, sig_dst, num_aes_blocks);
+		debug("encrypt_and_sign: end signing\n");
+	}
+
+	return 0;
+}
+
+int sign_data_block(u8 *source, unsigned length, u8 *signature)
+{
+	return encrypt_and_sign(zero_key, SECURITY_SIGN, source,
+				length, signature);
+}
diff --git a/arch/arm/cpu/armv7/tegra2/crypto.h b/arch/arm/cpu/armv7/tegra2/crypto.h
new file mode 100644
index 0000000000..aff67e77b0
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/crypto.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010 - 2011 NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CRYPTO_H_
+#define _CRYPTO_H_
+
+/**
+ * Sign a block of data
+ *
+ * \param source	Source data
+ * \param length	Size of source data
+ * \param signature	Destination address for signature, AES_KEY_LENGTH bytes
+ */
+int sign_data_block(u8 *source, unsigned length, u8 *signature);
+
+#endif /* #ifndef _CRYPTO_H_ */
diff --git a/arch/arm/cpu/armv7/tegra2/emc.c b/arch/arm/cpu/armv7/tegra2/emc.c
new file mode 100644
index 0000000000..c0e5c565f1
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/emc.c
@@ -0,0 +1,286 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <asm/arch/ap20.h>
+#include <asm/arch/apb_misc.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/emc.h>
+#include <asm/arch/tegra2.h>
+
+/*
+ * The EMC registers have shadow registers.  When the EMC clock is updated
+ * in the clock controller, the shadow registers are copied to the active
+ * registers, allowing glitchless memory bus frequency changes.
+ * This function updates the shadow registers for a new clock frequency,
+ * and relies on the clock lock on the emc clock to avoid races between
+ * multiple frequency changes
+ */
+
+/*
+ * This table defines the ordering of the registers provided to
+ * tegra_set_mmc()
+ * TODO: Convert to fdt version once available
+ */
+static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = {
+	0x2c,	/* RC */
+	0x30,	/* RFC */
+	0x34,	/* RAS */
+	0x38,	/* RP */
+	0x3c,	/* R2W */
+	0x40,	/* W2R */
+	0x44,	/* R2P */
+	0x48,	/* W2P */
+	0x4c,	/* RD_RCD */
+	0x50,	/* WR_RCD */
+	0x54,	/* RRD */
+	0x58,	/* REXT */
+	0x5c,	/* WDV */
+	0x60,	/* QUSE */
+	0x64,	/* QRST */
+	0x68,	/* QSAFE */
+	0x6c,	/* RDV */
+	0x70,	/* REFRESH */
+	0x74,	/* BURST_REFRESH_NUM */
+	0x78,	/* PDEX2WR */
+	0x7c,	/* PDEX2RD */
+	0x80,	/* PCHG2PDEN */
+	0x84,	/* ACT2PDEN */
+	0x88,	/* AR2PDEN */
+	0x8c,	/* RW2PDEN */
+	0x90,	/* TXSR */
+	0x94,	/* TCKE */
+	0x98,	/* TFAW */
+	0x9c,	/* TRPAB */
+	0xa0,	/* TCLKSTABLE */
+	0xa4,	/* TCLKSTOP */
+	0xa8,	/* TREFBW */
+	0xac,	/* QUSE_EXTRA */
+	0x114,	/* FBIO_CFG6 */
+	0xb0,	/* ODT_WRITE */
+	0xb4,	/* ODT_READ */
+	0x104,	/* FBIO_CFG5 */
+	0x2bc,	/* CFG_DIG_DLL */
+	0x2c0,	/* DLL_XFORM_DQS */
+	0x2c4,	/* DLL_XFORM_QUSE */
+	0x2e0,	/* ZCAL_REF_CNT */
+	0x2e4,	/* ZCAL_WAIT_CNT */
+	0x2a8,	/* AUTO_CAL_INTERVAL */
+	0x2d0,	/* CFG_CLKTRIM_0 */
+	0x2d4,	/* CFG_CLKTRIM_1 */
+	0x2d8,	/* CFG_CLKTRIM_2 */
+};
+
+struct emc_ctlr *emc_get_controller(const void *blob)
+{
+	fdt_addr_t addr;
+	int node;
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_EMC);
+	if (node > 0) {
+		addr = fdtdec_get_addr(blob, node, "reg");
+		if (addr != FDT_ADDR_T_NONE)
+			return (struct emc_ctlr *)addr;
+	}
+	return NULL;
+}
+
+/* Error codes we use */
+enum {
+	ERR_NO_EMC_NODE = -10,
+	ERR_NO_EMC_REG,
+	ERR_NO_FREQ,
+	ERR_FREQ_NOT_FOUND,
+	ERR_BAD_REGS,
+	ERR_NO_RAM_CODE,
+	ERR_RAM_CODE_NOT_FOUND,
+};
+
+/**
+ * Find EMC tables for the given ram code.
+ *
+ * The tegra EMC binding has two options, one using the ram code and one not.
+ * We detect which is in use by looking for the nvidia,use-ram-code property.
+ * If this is not present, then the EMC tables are directly below 'node',
+ * otherwise we select the correct emc-tables subnode based on the 'ram_code'
+ * value.
+ *
+ * @param blob		Device tree blob
+ * @param node		EMC node (nvidia,tegra20-emc compatible string)
+ * @param ram_code	RAM code to select (0-3, or -1 if unknown)
+ * @return 0 if ok, otherwise a -ve ERR_ code (see enum above)
+ */
+static int find_emc_tables(const void *blob, int node, int ram_code)
+{
+	int need_ram_code;
+	int depth;
+	int offset;
+
+	/* If we are using RAM codes, scan through the tables for our code */
+	need_ram_code = fdtdec_get_bool(blob, node, "nvidia,use-ram-code");
+	if (!need_ram_code)
+		return node;
+	if (ram_code == -1) {
+		debug("%s: RAM code required but not supplied\n", __func__);
+		return ERR_NO_RAM_CODE;
+	}
+
+	offset = node;
+	depth = 0;
+	do {
+		/*
+		 * Sadly there is no compatible string so we cannot use
+		 * fdtdec_next_compatible_subnode().
+		 */
+		offset = fdt_next_node(blob, offset, &depth);
+		if (depth <= 0)
+			break;
+
+		/* Make sure this is a direct subnode */
+		if (depth != 1)
+			continue;
+		if (strcmp("emc-tables", fdt_get_name(blob, offset, NULL)))
+			continue;
+
+		if (fdtdec_get_int(blob, offset, "nvidia,ram-code", -1)
+				== ram_code)
+			return offset;
+	} while (1);
+
+	debug("%s: Could not find tables for RAM code %d\n", __func__,
+	      ram_code);
+	return ERR_RAM_CODE_NOT_FOUND;
+}
+
+/**
+ * Decode the EMC node of the device tree, returning a pointer to the emc
+ * controller and the table to be used for the given rate.
+ *
+ * @param blob	Device tree blob
+ * @param rate	Clock speed of memory controller in Hz (=2x memory bus rate)
+ * @param emcp	Returns address of EMC controller registers
+ * @param tablep Returns pointer to table to program into EMC. There are
+ *		TEGRA_EMC_NUM_REGS entries, destined for offsets as per the
+ *		emc_reg_addr array.
+ * @return 0 if ok, otherwise a -ve error code which will allow someone to
+ * figure out roughly what went wrong by looking at this code.
+ */
+static int decode_emc(const void *blob, unsigned rate, struct emc_ctlr **emcp,
+		      const u32 **tablep)
+{
+	struct apb_misc_pp_ctlr *pp =
+		(struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
+	int ram_code;
+	int depth;
+	int node;
+
+	ram_code = (readl(&pp->strapping_opt_a) & RAM_CODE_MASK)
+			>> RAM_CODE_SHIFT;
+	/*
+	 * The EMC clock rate is twice the bus rate, and the bus rate is
+	 * measured in kHz
+	 */
+	rate = rate / 2 / 1000;
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_EMC);
+	if (node < 0) {
+		debug("%s: No EMC node found in FDT\n", __func__);
+		return ERR_NO_EMC_NODE;
+	}
+	*emcp = (struct emc_ctlr *)fdtdec_get_addr(blob, node, "reg");
+	if (*emcp == (struct emc_ctlr *)FDT_ADDR_T_NONE) {
+		debug("%s: No EMC node reg property\n", __func__);
+		return ERR_NO_EMC_REG;
+	}
+
+	/* Work out the parent node which contains our EMC tables */
+	node = find_emc_tables(blob, node, ram_code & 3);
+	if (node < 0)
+		return node;
+
+	depth = 0;
+	for (;;) {
+		int node_rate;
+
+		node = fdtdec_next_compatible_subnode(blob, node,
+				COMPAT_NVIDIA_TEGRA20_EMC_TABLE, &depth);
+		if (node < 0)
+			break;
+		node_rate = fdtdec_get_int(blob, node, "clock-frequency", -1);
+		if (node_rate == -1) {
+			debug("%s: Missing clock-frequency\n", __func__);
+			return ERR_NO_FREQ; /* we expect this property */
+		}
+
+		if (node_rate == rate)
+			break;
+	}
+	if (node < 0) {
+		debug("%s: No node found for clock frequency %d\n", __func__,
+		      rate);
+		return ERR_FREQ_NOT_FOUND;
+	}
+
+	*tablep = fdtdec_locate_array(blob, node, "nvidia,emc-registers",
+				      TEGRA_EMC_NUM_REGS);
+	if (!*tablep) {
+		debug("%s: node '%s' array missing / wrong size\n", __func__,
+		      fdt_get_name(blob, node, NULL));
+		return ERR_BAD_REGS;
+	}
+
+	/* All seems well */
+	return 0;
+}
+
+int tegra_set_emc(const void *blob, unsigned rate)
+{
+	struct emc_ctlr *emc;
+	const u32 *table;
+	int err, i;
+
+	err = decode_emc(blob, rate, &emc, &table);
+	if (err) {
+		debug("Warning: no valid EMC (%d), memory timings unset\n",
+		       err);
+		return err;
+	}
+
+	debug("%s: Table found, setting EMC values as follows:\n", __func__);
+	for (i = 0; i < TEGRA_EMC_NUM_REGS; i++) {
+		u32 value = fdt32_to_cpu(table[i]);
+		u32 addr = (uintptr_t)emc + emc_reg_addr[i];
+
+		debug("   %#x: %#x\n", addr, value);
+		writel(value, addr);
+	}
+
+	/* trigger emc with new settings */
+	clock_adjust_periph_pll_div(PERIPH_ID_EMC, CLOCK_ID_MEMORY,
+				clock_get_rate(CLOCK_ID_MEMORY), NULL);
+	debug("EMC clock set to %lu\n",
+	      clock_get_periph_rate(PERIPH_ID_EMC, CLOCK_ID_MEMORY));
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/tegra2/funcmux.c b/arch/arm/cpu/armv7/tegra2/funcmux.c
index c1d2dfec5f..0ef7753021 100644
--- a/arch/arm/cpu/armv7/tegra2/funcmux.c
+++ b/arch/arm/cpu/armv7/tegra2/funcmux.c
@@ -169,6 +169,22 @@ int funcmux_select(enum periph_id id, int config)
 		}
 		break;
 
+	case PERIPH_ID_KBC:
+		if (config == FUNCMUX_DEFAULT) {
+			enum pmux_pingrp grp[] = {PINGRP_KBCA, PINGRP_KBCB,
+				PINGRP_KBCC, PINGRP_KBCD, PINGRP_KBCE,
+				PINGRP_KBCF};
+			int i;
+
+			for (i = 0; i < ARRAY_SIZE(grp); i++) {
+				pinmux_tristate_disable(grp[i]);
+				pinmux_set_func(grp[i], PMUX_FUNC_KBC);
+				pinmux_set_pullupdown(grp[i], PMUX_PULL_UP);
+			}
+
+			break;
+		}
+
 	default:
 		debug("%s: invalid periph_id %d", __func__, id);
 		return -1;
diff --git a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S
index 6b866476ce..d117f23a62 100644
--- a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S
@@ -25,10 +25,10 @@
 
 #include <config.h>
 #include <version.h>
+#include <linux/linkage.h>
 
 	.align	5
-.global reset_cpu
-reset_cpu:
+ENTRY(reset_cpu)
 	ldr	r1, rstctl			@ get addr for global reset
 						@ reg
 	ldr	r3, [r1]
@@ -39,3 +39,4 @@ _loop_forever:
 	b	_loop_forever
 rstctl:
 	.word	PRM_RSTCTRL
+ENDPROC(reset_cpu)
diff --git a/arch/arm/cpu/armv7/tegra2/pmu.c b/arch/arm/cpu/armv7/tegra2/pmu.c
new file mode 100644
index 0000000000..46738023ff
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/pmu.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <tps6586x.h>
+#include <asm/io.h>
+#include <asm/arch/ap20.h>
+#include <asm/arch/tegra2.h>
+#include <asm/arch/tegra_i2c.h>
+#include <asm/arch/sys_proto.h>
+
+#define VDD_CORE_NOMINAL_T25	0x17	/* 1.3v */
+#define VDD_CPU_NOMINAL_T25	0x10	/* 1.125v */
+
+#define VDD_CORE_NOMINAL_T20	0x16	/* 1.275v */
+#define VDD_CPU_NOMINAL_T20	0x0f	/* 1.1v */
+
+#define VDD_RELATION		0x02	/*  50mv */
+#define VDD_TRANSITION_STEP	0x06	/* 150mv */
+#define VDD_TRANSITION_RATE	0x06	/* 3.52mv/us */
+
+int pmu_set_nominal(void)
+{
+	int core, cpu, bus;
+
+	/* by default, the table has been filled with T25 settings */
+	switch (tegra_get_chip_type()) {
+	case TEGRA_SOC_T20:
+		core = VDD_CORE_NOMINAL_T20;
+		cpu = VDD_CPU_NOMINAL_T20;
+		break;
+	case TEGRA_SOC_T25:
+		core = VDD_CORE_NOMINAL_T25;
+		cpu = VDD_CPU_NOMINAL_T25;
+		break;
+	default:
+		debug("%s: Unknown chip type\n", __func__);
+		return -1;
+	}
+
+	bus = tegra_i2c_get_dvc_bus_num();
+	if (bus == -1) {
+		debug("%s: Cannot find DVC I2C bus\n", __func__);
+		return -1;
+	}
+	tps6586x_init(bus);
+	tps6586x_set_pwm_mode(TPS6586X_PWM_SM1);
+	return tps6586x_adjust_sm0_sm1(core, cpu, VDD_TRANSITION_STEP,
+				VDD_TRANSITION_RATE, VDD_RELATION);
+}
diff --git a/arch/arm/cpu/armv7/tegra2/warmboot.c b/arch/arm/cpu/armv7/tegra2/warmboot.c
new file mode 100644
index 0000000000..25d896888a
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/warmboot.c
@@ -0,0 +1,386 @@
+/*
+ * (C) Copyright 2010 - 2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/ap20.h>
+#include <asm/arch/clk_rst.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pmc.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra2.h>
+#include <asm/arch/fuse.h>
+#include <asm/arch/emc.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/warmboot.h>
+#include <asm/arch/sdram_param.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_TEGRA_CLOCK_SCALING
+#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA2_LP0"
+#endif
+
+/*
+ * This is the place in SRAM where the SDRAM parameters are stored. There
+ * are 4 blocks, one for each RAM code
+ */
+#define SDRAM_PARAMS_BASE	(AP20_BASE_PA_SRAM + 0x188)
+
+/* TODO: If we later add support for the Misc GP controller, refactor this */
+union xm2cfga_reg {
+	struct {
+		u32 reserved0:2;
+		u32 hsm_en:1;
+		u32 reserved1:2;
+		u32 preemp_en:1;
+		u32 vref_en:1;
+		u32 reserved2:5;
+		u32 cal_drvdn:5;
+		u32 reserved3:3;
+		u32 cal_drvup:5;
+		u32 reserved4:3;
+		u32 cal_drvdn_slwr:2;
+		u32 cal_drvup_slwf:2;
+	};
+	u32 word;
+};
+
+union xm2cfgd_reg {
+	struct {
+		u32 reserved0:2;
+		u32 hsm_en:1;
+		u32 schmt_en:1;
+		u32 lpmd:2;
+		u32 vref_en:1;
+		u32 reserved1:5;
+		u32 cal_drvdn:5;
+		u32 reserved2:3;
+		u32 cal_drvup:5;
+		u32 reserved3:3;
+		u32 cal_drvdn_slwr:2;
+		u32 cal_drvup_slwf:2;
+	};
+	u32 word;
+};
+
+/*
+ * TODO: This register is not documented in the TRM yet. We could move this
+ * into the EMC and give it a proper interface, but not while it is
+ * undocumented.
+ */
+union fbio_spare_reg {
+	struct {
+		u32 reserved:24;
+		u32 cfg_wb0:8;
+	};
+	u32 word;
+};
+
+/* We pack the resume information into these unions for later */
+union scratch2_reg {
+	struct {
+		u32 pllm_base_divm:5;
+		u32 pllm_base_divn:10;
+		u32 pllm_base_divp:3;
+		u32 pllm_misc_lfcon:4;
+		u32 pllm_misc_cpcon:4;
+		u32 gp_xm2cfga_padctrl_preemp:1;
+		u32 gp_xm2cfgd_padctrl_schmt:1;
+		u32 osc_ctrl_xobp:1;
+		u32 memory_type:3;
+	};
+	u32 word;
+};
+
+union scratch4_reg {
+	struct {
+		u32 emc_clock_divider:8;
+		u32 pllm_stable_time:8;
+		u32 pllx_stable_time:8;
+		u32 emc_fbio_spare_cfg_wb0:8;
+	};
+	u32 word;
+};
+
+union scratch24_reg {
+	struct {
+		u32 emc_auto_cal_wait:8;
+		u32 emc_pin_program_wait:8;
+		u32 warmboot_wait:8;
+		u32 reserved:8;
+	};
+	u32 word;
+};
+
+int warmboot_save_sdram_params(void)
+{
+	u32 ram_code;
+	struct sdram_params sdram;
+	struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
+	struct apb_misc_gp_ctlr *gp =
+			(struct apb_misc_gp_ctlr *)TEGRA2_APB_MISC_GP_BASE;
+	struct emc_ctlr *emc = emc_get_controller(gd->fdt_blob);
+	union scratch2_reg scratch2;
+	union scratch4_reg scratch4;
+	union scratch24_reg scratch24;
+	union xm2cfga_reg xm2cfga;
+	union xm2cfgd_reg xm2cfgd;
+	union fbio_spare_reg fbio_spare;
+
+	/* get ram code that is used as index to array sdram_params in BCT */
+	ram_code = (readl(&pmt->pmt_strap_opt_a) >>
+			STRAP_OPT_A_RAM_CODE_SHIFT) & 3;
+	memcpy(&sdram,
+	       (char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code),
+	       sizeof(sdram));
+
+	xm2cfga.word = readl(&gp->xm2cfga);
+	xm2cfgd.word = readl(&gp->xm2cfgd);
+
+	scratch2.word = 0;
+	scratch2.osc_ctrl_xobp = clock_get_osc_bypass();
+
+	/* Get the memory PLL settings */
+	{
+		u32 divm, divn, divp, cpcon, lfcon;
+
+		if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp,
+					&cpcon, &lfcon))
+			return -1;
+		scratch2.pllm_base_divm = divm;
+		scratch2.pllm_base_divn = divn;
+		scratch2.pllm_base_divp = divp;
+		scratch2.pllm_misc_cpcon = cpcon;
+		scratch2.pllm_misc_lfcon = lfcon;
+	}
+
+	scratch2.gp_xm2cfga_padctrl_preemp = xm2cfga.preemp_en;
+	scratch2.gp_xm2cfgd_padctrl_schmt = xm2cfgd.schmt_en;
+	scratch2.memory_type = sdram.memory_type;
+	writel(scratch2.word, &pmc->pmc_scratch2);
+
+	/* collect data from various sources for pmc_scratch4 */
+	fbio_spare.word = readl(&emc->fbio_spare);
+	scratch4.word = 0;
+	scratch4.emc_fbio_spare_cfg_wb0 = fbio_spare.cfg_wb0;
+	scratch4.emc_clock_divider = sdram.emc_clock_divider;
+	scratch4.pllm_stable_time = -1;
+	scratch4.pllx_stable_time = -1;
+	writel(scratch4.word, &pmc->pmc_scratch4);
+
+	/* collect various data from sdram for pmc_scratch24 */
+	scratch24.word = 0;
+	scratch24.emc_pin_program_wait = sdram.emc_pin_program_wait;
+	scratch24.emc_auto_cal_wait = sdram.emc_auto_cal_wait;
+	scratch24.warmboot_wait = sdram.warm_boot_wait;
+	writel(scratch24.word, &pmc->pmc_scratch24);
+
+	return 0;
+}
+
+static u32 get_major_version(void)
+{
+	u32 major_id;
+	struct apb_misc_gp_ctlr *gp =
+		(struct apb_misc_gp_ctlr *)TEGRA2_APB_MISC_GP_BASE;
+
+	major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >>
+			HIDREV_MAJORPREV_SHIFT;
+	return major_id;
+}
+
+static int is_production_mode_fuse_set(struct fuse_regs *fuse)
+{
+	return readl(&fuse->production_mode);
+}
+
+static int is_odm_production_mode_fuse_set(struct fuse_regs *fuse)
+{
+	return readl(&fuse->security_mode);
+}
+
+static int is_failure_analysis_mode(struct fuse_regs *fuse)
+{
+	return readl(&fuse->fa);
+}
+
+static int ap20_is_odm_production_mode(void)
+{
+	struct fuse_regs *fuse = (struct fuse_regs *)TEGRA2_FUSE_BASE;
+
+	if (!is_failure_analysis_mode(fuse) &&
+	    is_odm_production_mode_fuse_set(fuse))
+		return 1;
+	else
+		return 0;
+}
+
+static int ap20_is_production_mode(void)
+{
+	struct fuse_regs *fuse = (struct fuse_regs *)TEGRA2_FUSE_BASE;
+
+	if (get_major_version() == 0)
+		return 1;
+
+	if (!is_failure_analysis_mode(fuse) &&
+	    is_production_mode_fuse_set(fuse) &&
+	    !is_odm_production_mode_fuse_set(fuse))
+		return 1;
+	else
+		return 0;
+}
+
+static enum fuse_operating_mode fuse_get_operation_mode(void)
+{
+	u32 chip_id;
+	struct apb_misc_gp_ctlr *gp =
+		(struct apb_misc_gp_ctlr *)TEGRA2_APB_MISC_GP_BASE;
+
+	chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >>
+			HIDREV_CHIPID_SHIFT;
+	if (chip_id == CHIPID_TEGRA2) {
+		if (ap20_is_odm_production_mode()) {
+			printf("!! odm_production_mode is not supported !!\n");
+			return MODE_UNDEFINED;
+		} else
+			if (ap20_is_production_mode())
+				return MODE_PRODUCTION;
+			else
+				return MODE_UNDEFINED;
+	}
+	return MODE_UNDEFINED;
+}
+
+static void determine_crypto_options(int *is_encrypted, int *is_signed,
+				     int *use_zero_key)
+{
+	switch (fuse_get_operation_mode()) {
+	case MODE_PRODUCTION:
+		*is_encrypted = 0;
+		*is_signed = 1;
+		*use_zero_key = 1;
+		break;
+	case MODE_UNDEFINED:
+	default:
+		*is_encrypted = 0;
+		*is_signed = 0;
+		*use_zero_key  = 0;
+		break;
+	}
+}
+
+static int sign_wb_code(u32 start, u32 length, int use_zero_key)
+{
+	int err;
+	u8 *source;		/* Pointer to source */
+	u8 *hash;
+
+	/* Calculate AES block parameters. */
+	source = (u8 *)(start + offsetof(struct wb_header, random_aes_block));
+	length -= offsetof(struct wb_header, random_aes_block);
+	hash = (u8 *)(start + offsetof(struct wb_header, hash));
+	err = sign_data_block(source, length, hash);
+
+	return err;
+}
+
+int warmboot_prepare_code(u32 seg_address, u32 seg_length)
+{
+	int err = 0;
+	u32 length;			/* length of the signed/encrypt code */
+	struct wb_header *dst_header;	/* Pointer to dest WB header */
+	int is_encrypted;		/* Segment is encrypted */
+	int is_signed;			/* Segment is signed */
+	int use_zero_key;		/* Use key of all zeros */
+
+	/* Determine crypto options. */
+	determine_crypto_options(&is_encrypted, &is_signed, &use_zero_key);
+
+	/* Get the actual code limits. */
+	length = roundup(((u32)wb_end - (u32)wb_start), 16);
+
+	/*
+	 * The region specified by seg_address must be in SDRAM and must be
+	 * nonzero in length.
+	 */
+	if (seg_length == 0 || seg_address < NV_PA_SDRAM_BASE ||
+		seg_address + seg_length >= NV_PA_SDRAM_BASE + gd->ram_size) {
+		err = -EFAULT;
+		goto fail;
+	}
+
+	/* Things must be 16-byte aligned. */
+	if ((seg_length & 0xF) || (seg_address & 0xF)) {
+		err = -EINVAL;
+		goto fail;
+	}
+
+	/* Will the code fit? (destination includes wb_header + wb code) */
+	if (seg_length < (length + sizeof(struct wb_header))) {
+		err = -EINVAL;
+		goto fail;
+	}
+
+	dst_header = (struct wb_header *)seg_address;
+	memset((char *)dst_header, 0, sizeof(struct wb_header));
+
+	/* Populate the random_aes_block as requested. */
+	{
+		u32 *aes_block = (u32 *)&(dst_header->random_aes_block);
+		u32 *end = (u32 *)(((u32)aes_block) +
+				   sizeof(dst_header->random_aes_block));
+
+		do {
+			*aes_block++ = 0;
+		} while (aes_block < end);
+	}
+
+	/* Populate the header. */
+	dst_header->length_insecure = length + sizeof(struct wb_header);
+	dst_header->length_secure = length + sizeof(struct wb_header);
+	dst_header->destination = AP20_WB_RUN_ADDRESS;
+	dst_header->entry_point = AP20_WB_RUN_ADDRESS;
+	dst_header->code_length = length;
+
+	if (is_encrypted) {
+		printf("!!!! Encryption is not supported !!!!\n");
+		dst_header->length_insecure = 0;
+		err = -EACCES;
+		goto fail;
+	} else
+		/* copy the wb code directly following dst_header. */
+		memcpy((char *)(dst_header+1), (char *)wb_start, length);
+
+	if (is_signed)
+		err = sign_wb_code(seg_address, dst_header->length_insecure,
+				   use_zero_key);
+
+fail:
+	if (err)
+		printf("Warning: warmboot code copy failed (error=%d)\n", err);
+
+	return err;
+}
diff --git a/arch/arm/cpu/armv7/tegra2/warmboot_avp.c b/arch/arm/cpu/armv7/tegra2/warmboot_avp.c
new file mode 100644
index 0000000000..70bcd8e5f3
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/warmboot_avp.c
@@ -0,0 +1,250 @@
+/*
+ * (C) Copyright 2010 - 2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ap20.h>
+#include <asm/arch/clk_rst.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/flow.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/pmc.h>
+#include <asm/arch/tegra2.h>
+#include <asm/arch/warmboot.h>
+#include "warmboot_avp.h"
+
+#define DEBUG_RESET_CORESIGHT
+
+void wb_start(void)
+{
+	struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
+	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	union osc_ctrl_reg osc_ctrl;
+	union pllx_base_reg pllx_base;
+	union pllx_misc_reg pllx_misc;
+	union scratch3_reg scratch3;
+	u32 reg;
+
+	/* enable JTAG & TBE */
+	writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &pmt->pmt_cfg_ctl);
+
+	/* Are we running where we're supposed to be? */
+	asm volatile (
+		"adr	%0, wb_start;"	/* reg: wb_start address */
+		: "=r"(reg)		/* output */
+					/* no input, no clobber list */
+	);
+
+	if (reg != AP20_WB_RUN_ADDRESS)
+		goto do_reset;
+
+	/* Are we running with AVP? */
+	if (readl(NV_PA_PG_UP_BASE + PG_UP_TAG_0) != PG_UP_TAG_AVP)
+		goto do_reset;
+
+#ifdef DEBUG_RESET_CORESIGHT
+	/* Assert CoreSight reset */
+	reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]);
+	reg |= SWR_CSITE_RST;
+	writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]);
+#endif
+
+	/* TODO: Set the drive strength - maybe make this a board parameter? */
+	osc_ctrl.word = readl(&clkrst->crc_osc_ctrl);
+	osc_ctrl.xofs = 4;
+	osc_ctrl.xoe = 1;
+	writel(osc_ctrl.word, &clkrst->crc_osc_ctrl);
+
+	/* Power up the CPU complex if necessary */
+	if (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU)) {
+		reg = PWRGATE_TOGGLE_PARTID_CPU | PWRGATE_TOGGLE_START;
+		writel(reg, &pmc->pmc_pwrgate_toggle);
+		while (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU))
+			;
+	}
+
+	/* Remove the I/O clamps from the CPU power partition. */
+	reg = readl(&pmc->pmc_remove_clamping);
+	reg |= CPU_CLMP;
+	writel(reg, &pmc->pmc_remove_clamping);
+
+	reg = EVENT_ZERO_VAL_20 | EVENT_MSEC | EVENT_MODE_STOP;
+	writel(reg, &flow->halt_cop_events);
+
+	/* Assert CPU complex reset */
+	reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_L]);
+	reg |= CPU_RST;
+	writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_L]);
+
+	/* Hold both CPUs in reset */
+	reg = CPU_CMPLX_CPURESET0 | CPU_CMPLX_CPURESET1 | CPU_CMPLX_DERESET0 |
+	      CPU_CMPLX_DERESET1 | CPU_CMPLX_DBGRESET0 | CPU_CMPLX_DBGRESET1;
+	writel(reg, &clkrst->crc_cpu_cmplx_set);
+
+	/* Halt CPU1 at the flow controller for uni-processor configurations */
+	writel(EVENT_MODE_STOP, &flow->halt_cpu1_events);
+
+	/*
+	 * Set the CPU reset vector. SCRATCH41 contains the physical
+	 * address of the CPU-side restoration code.
+	 */
+	reg = readl(&pmc->pmc_scratch41);
+	writel(reg, EXCEP_VECTOR_CPU_RESET_VECTOR);
+
+	/* Select CPU complex clock source */
+	writel(CCLK_PLLP_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
+
+	/* Start the CPU0 clock and stop the CPU1 clock */
+	reg = CPU_CMPLX_CPU_BRIDGE_CLKDIV_4 | CPU_CMPLX_CPU0_CLK_STP_RUN |
+	      CPU_CMPLX_CPU1_CLK_STP_STOP;
+	writel(reg, &clkrst->crc_clk_cpu_cmplx);
+
+	/* Enable the CPU complex clock */
+	reg = readl(&clkrst->crc_clk_out_enb[TEGRA_DEV_L]);
+	reg |= CLK_ENB_CPU;
+	writel(reg, &clkrst->crc_clk_out_enb[TEGRA_DEV_L]);
+
+	/* Make sure the resets were held for at least 2 microseconds */
+	reg = readl(TIMER_USEC_CNTR);
+	while (readl(TIMER_USEC_CNTR) <= (reg + 2))
+		;
+
+#ifdef DEBUG_RESET_CORESIGHT
+	/*
+	 * De-assert CoreSight reset.
+	 * NOTE: We're leaving the CoreSight clock on the oscillator for
+	 *	now. It will be restored to its original clock source
+	 *	when the CPU-side restoration code runs.
+	 */
+	reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]);
+	reg &= ~SWR_CSITE_RST;
+	writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]);
+#endif
+
+	/* Unlock the CPU CoreSight interfaces */
+	reg = 0xC5ACCE55;
+	writel(reg, CSITE_CPU_DBG0_LAR);
+	writel(reg, CSITE_CPU_DBG1_LAR);
+
+	/*
+	 * Sample the microsecond timestamp again. This is the time we must
+	 * use when returning from LP0 for PLL stabilization delays.
+	 */
+	reg = readl(TIMER_USEC_CNTR);
+	writel(reg, &pmc->pmc_scratch1);
+
+	pllx_base.word = 0;
+	pllx_misc.word = 0;
+	scratch3.word = readl(&pmc->pmc_scratch3);
+
+	/* Get the OSC. For 19.2 MHz, use 19 to make the calculations easier */
+	reg = (readl(TIMER_USEC_CFG) & USEC_CFG_DIVISOR_MASK) + 1;
+
+	/*
+	 * According to the TRM, for 19.2MHz OSC, the USEC_DIVISOR is 0x5f, and
+	 * USEC_DIVIDEND is 0x04. So, if USEC_DIVISOR > 26, OSC is 19.2 MHz.
+	 *
+	 * reg is used to calculate the pllx freq, which is used to determine if
+	 * to set dccon or not.
+	 */
+	if (reg > 26)
+		reg = 19;
+
+	/* PLLX_BASE.PLLX_DIVM */
+	if (scratch3.pllx_base_divm == reg)
+		reg = 0;
+	else
+		reg = 1;
+
+	/* PLLX_BASE.PLLX_DIVN */
+	pllx_base.divn = scratch3.pllx_base_divn;
+	reg = scratch3.pllx_base_divn << reg;
+
+	/* PLLX_BASE.PLLX_DIVP */
+	pllx_base.divp = scratch3.pllx_base_divp;
+	reg = reg >> scratch3.pllx_base_divp;
+
+	pllx_base.bypass = 1;
+
+	/* PLLX_MISC_DCCON must be set for pllx frequency > 600 MHz. */
+	if (reg > 600)
+		pllx_misc.dccon = 1;
+
+	/* PLLX_MISC_LFCON */
+	pllx_misc.lfcon = scratch3.pllx_misc_lfcon;
+
+	/* PLLX_MISC_CPCON */
+	pllx_misc.cpcon = scratch3.pllx_misc_cpcon;
+
+	writel(pllx_misc.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_misc);
+	writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
+
+	pllx_base.enable = 1;
+	writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
+	pllx_base.bypass = 0;
+	writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
+
+	writel(0, flow->halt_cpu_events);
+
+	reg = CPU_CMPLX_CPURESET0 | CPU_CMPLX_DBGRESET0 | CPU_CMPLX_DERESET0;
+	writel(reg, &clkrst->crc_cpu_cmplx_clr);
+
+	reg = PLLM_OUT1_RSTN_RESET_DISABLE | PLLM_OUT1_CLKEN_ENABLE |
+	      PLLM_OUT1_RATIO_VAL_8;
+	writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out);
+
+	reg = SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 | SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 |
+	      SCLK_SWAKE_RUN_SRC_PLLM_OUT1 | SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 |
+	      SCLK_SYS_STATE_IDLE;
+	writel(reg, &clkrst->crc_sclk_brst_pol);
+
+	/* avp_resume: no return after the write */
+	reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_L]);
+	reg &= ~CPU_RST;
+	writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_L]);
+
+	/* avp_halt: */
+avp_halt:
+	reg = EVENT_MODE_STOP | EVENT_JTAG;
+	writel(reg, flow->halt_cop_events);
+	goto avp_halt;
+
+do_reset:
+	/*
+	 * Execution comes here if something goes wrong. The chip is reset and
+	 * a cold boot is performed.
+	 */
+	writel(SWR_TRIG_SYS_RST, &clkrst->crc_rst_dev[TEGRA_DEV_L]);
+	goto do_reset;
+}
+
+/*
+ * wb_end() is a dummy function, and must be directly following wb_start(),
+ * and is used to calculate the size of wb_start().
+ */
+void wb_end(void)
+{
+}
diff --git a/arch/arm/cpu/armv7/tegra2/warmboot_avp.h b/arch/arm/cpu/armv7/tegra2/warmboot_avp.h
new file mode 100644
index 0000000000..4b71c07843
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/warmboot_avp.h
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2010, 2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _WARMBOOT_AVP_H_
+#define _WARMBOOT_AVP_H_
+
+#define TEGRA_DEV_L			0
+#define TEGRA_DEV_H			1
+#define TEGRA_DEV_U			2
+
+#define SIMPLE_PLLX			(CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
+#define SIMPLE_PLLE			(CLOCK_ID_EPCI - CLOCK_ID_FIRST_SIMPLE)
+
+#define TIMER_USEC_CNTR			(NV_PA_TMRUS_BASE + 0)
+#define TIMER_USEC_CFG			(NV_PA_TMRUS_BASE + 4)
+
+#define USEC_CFG_DIVISOR_MASK		0xffff
+
+#define CONFIG_CTL_TBE			(1 << 7)
+#define CONFIG_CTL_JTAG			(1 << 6)
+
+#define CPU_RST				(1 << 0)
+#define CLK_ENB_CPU			(1 << 0)
+#define SWR_TRIG_SYS_RST		(1 << 2)
+#define SWR_CSITE_RST			(1 << 9)
+
+#define PWRGATE_STATUS_CPU		(1 << 0)
+#define PWRGATE_TOGGLE_PARTID_CPU	(0 << 0)
+#define PWRGATE_TOGGLE_START		(1 << 8)
+
+#define CPU_CMPLX_CPU_BRIDGE_CLKDIV_4	(3 << 0)
+#define CPU_CMPLX_CPU0_CLK_STP_STOP	(1 << 8)
+#define CPU_CMPLX_CPU0_CLK_STP_RUN	(0 << 8)
+#define CPU_CMPLX_CPU1_CLK_STP_STOP	(1 << 9)
+#define CPU_CMPLX_CPU1_CLK_STP_RUN	(0 << 9)
+
+#define CPU_CMPLX_CPURESET0		(1 << 0)
+#define CPU_CMPLX_CPURESET1		(1 << 1)
+#define CPU_CMPLX_DERESET0		(1 << 4)
+#define CPU_CMPLX_DERESET1		(1 << 5)
+#define CPU_CMPLX_DBGRESET0		(1 << 12)
+#define CPU_CMPLX_DBGRESET1		(1 << 13)
+
+#define PLLM_OUT1_RSTN_RESET_DISABLE	(1 << 0)
+#define PLLM_OUT1_CLKEN_ENABLE		(1 << 1)
+#define PLLM_OUT1_RATIO_VAL_8		(8 << 8)
+
+#define SCLK_SYS_STATE_IDLE		(1 << 28)
+#define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1	(7 << 12)
+#define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1	(7 << 8)
+#define SCLK_SWAKE_RUN_SRC_PLLM_OUT1	(7 << 4)
+#define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1	(7 << 0)
+
+#define EVENT_ZERO_VAL_20		(20 << 0)
+#define EVENT_MSEC			(1 << 24)
+#define EVENT_JTAG			(1 << 28)
+#define EVENT_MODE_STOP			(2 << 29)
+
+#define CCLK_PLLP_BURST_POLICY		0x20004444
+
+#endif
diff --git a/arch/arm/cpu/armv7/u8500/lowlevel.S b/arch/arm/cpu/armv7/u8500/lowlevel.S
index cffdfd1381..289cfb0779 100644
--- a/arch/arm/cpu/armv7/u8500/lowlevel.S
+++ b/arch/arm/cpu/armv7/u8500/lowlevel.S
@@ -20,16 +20,17 @@
  */
 
 #include <config.h>
+#include <linux/linkage.h>
 
-.globl lowlevel_init
-lowlevel_init:
+ENTRY(lowlevel_init)
 	mov	pc, lr
+ENDPROC(lowlevel_init)
 
 	.align	5
-.globl reset_cpu
-reset_cpu:
+ENTRY(reset_cpu)
 	ldr r0, =CFG_PRCMU_BASE
 	ldr r1, =0x1
 	str r1, [r0, #0x228]
 _loop_forever:
 	b	_loop_forever
+ENDPROC(reset_cpu)
diff --git a/arch/arm/cpu/ixp/npe/npe.c b/arch/arm/cpu/ixp/npe/npe.c
index f0e02bf7d9..1fe3a95eaf 100644
--- a/arch/arm/cpu/ixp/npe/npe.c
+++ b/arch/arm/cpu/ixp/npe/npe.c
@@ -518,7 +518,7 @@ static void npe_halt(struct eth_device *dev)
 }
 
 
-static int npe_send(struct eth_device *dev, volatile void *packet, int len)
+static int npe_send(struct eth_device *dev, void *packet, int len)
 {
 	struct npe *p_npe = (struct npe *)dev->priv;
 	u8 *dest;
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index d5ca02c5f5..f95be58135 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -193,4 +193,15 @@
 		clocks = <&tegra_car 59>;	/* PERIPH_ID_USB3 */
 	};
 
+	emc@7000f400 {
+		#address-cells = < 1 >;
+		#size-cells = < 0 >;
+		compatible = "nvidia,tegra20-emc";
+		reg = <0x7000f400 0x200>;
+	};
+
+	kbc@7000e200 {
+		compatible = "nvidia,tegra20-kbc";
+		reg = <0x7000e200 0x0078>;
+	};
 };
diff --git a/arch/arm/include/asm/arch b/arch/arm/include/asm/arch
new file mode 120000
index 0000000000..802cf12ac7
--- /dev/null
+++ b/arch/arm/include/asm/arch
@@ -0,0 +1 @@
+arch-rda
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
index 943526b94a..26cc300e70 100644
--- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
@@ -159,6 +159,6 @@ typedef struct hsmmc {
 #define mmc_reg_out(addr, mask, val)\
 	writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
 
-int omap_mmc_init(int dev_index);
+int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
 
 #endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h
index ff0f6415d8..637fb4bd14 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -33,5 +33,8 @@ unsigned long get_arm_clk(void);
 unsigned long get_pwm_clk(void);
 unsigned long get_uart_clk(int dev_index);
 void set_mmc_clk(int dev_index, unsigned int div);
+unsigned long get_lcd_clk(void);
+void set_lcd_clk(void);
+void set_mipi_clk(void);
 
 #endif
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index 89f2c2e3e9..ac4ddc7354 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -29,6 +29,7 @@
 /* EXYNOS4 */
 #define EXYNOS4_GPIO_PART3_BASE		0x03860000
 #define EXYNOS4_PRO_ID			0x10000000
+#define EXYNOS4_SYSREG_BASE		0x10010000
 #define EXYNOS4_POWER_BASE		0x10020000
 #define EXYNOS4_SWRESET			0x10020400
 #define EXYNOS4_CLOCK_BASE		0x10030000
@@ -40,6 +41,7 @@
 #define EXYNOS4_GPIO_PART2_BASE		0x11000000
 #define EXYNOS4_GPIO_PART1_BASE		0x11400000
 #define EXYNOS4_FIMD_BASE		0x11C00000
+#define EXYNOS4_MIPI_DSIM_BASE		0x11C80000
 #define EXYNOS4_USBOTG_BASE		0x12480000
 #define EXYNOS4_MMC_BASE		0x12510000
 #define EXYNOS4_SROMC_BASE		0x12570000
@@ -65,6 +67,7 @@
 #define EXYNOS5_GPIO_PART3_BASE		0x10D10000
 #define EXYNOS5_DMC_CTRL_BASE		0x10DD0000
 #define EXYNOS5_GPIO_PART1_BASE		0x11400000
+#define EXYNOS5_MIPI_DSIM_BASE		0x11D00000
 #define EXYNOS5_MMC_BASE		0x12200000
 #define EXYNOS5_SROMC_BASE		0x12250000
 #define EXYNOS5_USBOTG_BASE		0x12480000
@@ -127,7 +130,9 @@ static inline unsigned int samsung_get_base_##device(void)	\
 
 SAMSUNG_BASE(adc, ADC_BASE)
 SAMSUNG_BASE(clock, CLOCK_BASE)
+SAMSUNG_BASE(sysreg, SYSREG_BASE)
 SAMSUNG_BASE(fimd, FIMD_BASE)
+SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)
 SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
 SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
 SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
diff --git a/arch/arm/include/asm/arch-exynos/dsim.h b/arch/arm/include/asm/arch-exynos/dsim.h
new file mode 100644
index 0000000000..e148aca2e8
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/dsim.h
@@ -0,0 +1,181 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: InKi Dae <inki.dae@samsung.com>
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_DSIM_H_
+#define __ASM_ARM_ARCH_DSIM_H_
+
+#ifndef __ASSEMBLY__
+
+struct exynos_mipi_dsim {
+	unsigned int	status;
+	unsigned int	swrst;
+	unsigned int	clkctrl;
+	unsigned int	timeout;
+	unsigned int	config;
+	unsigned int	escmode;
+	unsigned int	mdresol;
+	unsigned int	mvporch;
+	unsigned int	mhporch;
+	unsigned int	msync;
+	unsigned int	sdresol;
+	unsigned int	intsrc;
+	unsigned int	intmsk;
+	unsigned int	pkthdr;
+	unsigned int	payload;
+	unsigned int	rxfifo;
+	unsigned int	fifothld;
+	unsigned int	fifoctrl;
+	unsigned int	memacchr;
+	unsigned int	pllctrl;
+	unsigned int	plltmr;
+	unsigned int	phyacchr;
+	unsigned int	phyacchr1;
+};
+
+#endif	/* __ASSEMBLY__ */
+
+/*
+ * Bit Definitions
+ */
+/* DSIM_STATUS */
+#define DSIM_STOP_STATE_DAT(x)	(((x) & 0xf) << 0)
+#define DSIM_STOP_STATE_CLK	(1 << 8)
+#define DSIM_TX_READY_HS_CLK	(1 << 10)
+#define DSIM_PLL_STABLE		(1 << 31)
+
+/* DSIM_SWRST */
+#define DSIM_FUNCRST		(1 << 16)
+#define DSIM_SWRST		(1 << 0)
+
+/* EXYNOS_DSIM_TIMEOUT */
+#define DSIM_LPDR_TOUT_SHIFT	(0)
+#define DSIM_BTA_TOUT_SHIFT	(16)
+
+/* EXYNOS_DSIM_CLKCTRL */
+#define DSIM_LANE_ESC_CLKEN_SHIFT	(19)
+#define DSIM_BYTE_CLKEN_SHIFT		(24)
+#define DSIM_BYTE_CLK_SRC_SHIFT		(25)
+#define DSIM_PLL_BYPASS_SHIFT		(27)
+#define DSIM_ESC_CLKEN_SHIFT		(28)
+#define DSIM_TX_REQUEST_HSCLK_SHIFT	(31)
+#define DSIM_LANE_ESC_CLKEN(x)		(((x) & 0x1f) << \
+						DSIM_LANE_ESC_CLKEN_SHIFT)
+#define DSIM_BYTE_CLK_ENABLE		(1 << DSIM_BYTE_CLKEN_SHIFT)
+#define DSIM_BYTE_CLK_DISABLE		(0 << DSIM_BYTE_CLKEN_SHIFT)
+#define DSIM_PLL_BYPASS_EXTERNAL	(1 << DSIM_PLL_BYPASS_SHIFT)
+#define DSIM_ESC_CLKEN_ENABLE		(1 << DSIM_ESC_CLKEN_SHIFT)
+#define DSIM_ESC_CLKEN_DISABLE		(0 << DSIM_ESC_CLKEN_SHIFT)
+
+/* EXYNOS_DSIM_CONFIG */
+#define DSIM_NUM_OF_DATALANE_SHIFT	(5)
+#define DSIM_SUBPIX_SHIFT		(8)
+#define DSIM_MAINPIX_SHIFT		(12)
+#define DSIM_SUBVC_SHIFT		(16)
+#define DSIM_MAINVC_SHIFT		(18)
+#define DSIM_HSA_MODE_SHIFT		(20)
+#define DSIM_HBP_MODE_SHIFT		(21)
+#define DSIM_HFP_MODE_SHIFT		(22)
+#define DSIM_HSE_MODE_SHIFT		(23)
+#define DSIM_AUTO_MODE_SHIFT		(24)
+#define DSIM_VIDEO_MODE_SHIFT		(25)
+#define DSIM_BURST_MODE_SHIFT		(26)
+#define DSIM_EOT_PACKET_SHIFT		(28)
+#define DSIM_AUTO_FLUSH_SHIFT		(29)
+#define DSIM_LANE_ENx(x)		(((x) & 0x1f) << 0)
+
+#define DSIM_NUM_OF_DATA_LANE(x)	((x) << DSIM_NUM_OF_DATALANE_SHIFT)
+
+/* EXYNOS_DSIM_ESCMODE */
+#define DSIM_TX_LPDT_SHIFT		(6)
+#define DSIM_CMD_LPDT_SHIFT		(7)
+#define DSIM_TX_LPDT_LP			(1 << DSIM_TX_LPDT_SHIFT)
+#define DSIM_CMD_LPDT_LP		(1 << DSIM_CMD_LPDT_SHIFT)
+#define DSIM_STOP_STATE_CNT_SHIFT	(21)
+#define DSIM_FORCE_STOP_STATE_SHIFT	(20)
+
+/* EXYNOS_DSIM_MDRESOL */
+#define DSIM_MAIN_STAND_BY		(1 << 31)
+#define DSIM_MAIN_VRESOL(x)		(((x) & 0x7ff) << 16)
+#define DSIM_MAIN_HRESOL(x)		(((x) & 0X7ff) << 0)
+
+/* EXYNOS_DSIM_MVPORCH */
+#define DSIM_CMD_ALLOW_SHIFT		(28)
+#define DSIM_STABLE_VFP_SHIFT		(16)
+#define DSIM_MAIN_VBP_SHIFT		(0)
+#define DSIM_CMD_ALLOW_MASK		(0xf << DSIM_CMD_ALLOW_SHIFT)
+#define DSIM_STABLE_VFP_MASK		(0x7ff << DSIM_STABLE_VFP_SHIFT)
+#define DSIM_MAIN_VBP_MASK		(0x7ff << DSIM_MAIN_VBP_SHIFT)
+
+/* EXYNOS_DSIM_MHPORCH */
+#define DSIM_MAIN_HFP_SHIFT		(16)
+#define DSIM_MAIN_HBP_SHIFT		(0)
+#define DSIM_MAIN_HFP_MASK		((0xffff) << DSIM_MAIN_HFP_SHIFT)
+#define DSIM_MAIN_HBP_MASK		((0xffff) << DSIM_MAIN_HBP_SHIFT)
+
+/* EXYNOS_DSIM_MSYNC */
+#define DSIM_MAIN_VSA_SHIFT		(22)
+#define DSIM_MAIN_HSA_SHIFT		(0)
+#define DSIM_MAIN_VSA_MASK		((0x3ff) << DSIM_MAIN_VSA_SHIFT)
+#define DSIM_MAIN_HSA_MASK		((0xffff) << DSIM_MAIN_HSA_SHIFT)
+
+/* EXYNOS_DSIM_SDRESOL */
+#define DSIM_SUB_STANDY_SHIFT		(31)
+#define DSIM_SUB_VRESOL_SHIFT		(16)
+#define DSIM_SUB_HRESOL_SHIFT		(0)
+#define DSIM_SUB_STANDY_MASK		((0x1) << DSIM_SUB_STANDY_SHIFT)
+#define DSIM_SUB_VRESOL_MASK		((0x7ff) << DSIM_SUB_VRESOL_SHIFT)
+#define DSIM_SUB_HRESOL_MASK		((0x7ff) << DSIM_SUB_HRESOL_SHIFT)
+
+/* EXYNOS_DSIM_INTSRC */
+#define INTSRC_FRAME_DONE		(1 << 24)
+#define INTSRC_PLL_STABLE		(1 << 31)
+#define INTSRC_SWRST_RELEASE		(1 << 30)
+
+/* EXYNOS_DSIM_INTMSK */
+#define INTMSK_FRAME_DONE		(1 << 24)
+
+/* EXYNOS_DSIM_FIFOCTRL */
+#define SFR_HEADER_EMPTY		(1 << 22)
+
+/* EXYNOS_DSIM_PKTHDR */
+#define DSIM_PKTHDR_DI(x)		(((x) & 0x3f) << 0)
+#define DSIM_PKTHDR_DAT0(x)		((x) << 8)
+#define DSIM_PKTHDR_DAT1(x)		((x) << 16)
+
+/* EXYNOS_DSIM_PHYACCHR */
+#define DSIM_AFC_CTL(x)			(((x) & 0x7) << 5)
+#define DSIM_AFC_CTL_SHIFT		(5)
+#define DSIM_AFC_EN			(1 << 14)
+
+/* EXYNOS_DSIM_PHYACCHR1 */
+#define DSIM_DPDN_SWAP_DATA_SHIFT	(0)
+
+/* EXYNOS_DSIM_PLLCTRL */
+#define DSIM_SCALER_SHIFT		(1)
+#define DSIM_MAIN_SHIFT			(4)
+#define DSIM_PREDIV_SHIFT		(13)
+#define DSIM_PRECTRL_SHIFT		(20)
+#define DSIM_PLL_EN_SHIFT		(23)
+#define DSIM_FREQ_BAND_SHIFT		(24)
+#define DSIM_ZEROCTRL_SHIFT		(28)
+
+#endif
diff --git a/arch/arm/include/asm/arch-exynos/ehci-s5p.h b/arch/arm/include/asm/arch-exynos/ehci-s5p.h
new file mode 100644
index 0000000000..68feb85ede
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/ehci-s5p.h
@@ -0,0 +1,66 @@
+/*
+ * SAMSUNG S5P USB HOST EHCI Controller
+ *
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ *	Vivek Gautam <gautam.vivek@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__
+#define __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__
+
+#define CLK_24MHZ		5
+
+#define HOST_CTRL0_PHYSWRSTALL			(1 << 31)
+#define HOST_CTRL0_COMMONON_N			(1 << 9)
+#define HOST_CTRL0_SIDDQ			(1 << 6)
+#define HOST_CTRL0_FORCESLEEP			(1 << 5)
+#define HOST_CTRL0_FORCESUSPEND			(1 << 4)
+#define HOST_CTRL0_WORDINTERFACE		(1 << 3)
+#define HOST_CTRL0_UTMISWRST			(1 << 2)
+#define HOST_CTRL0_LINKSWRST			(1 << 1)
+#define HOST_CTRL0_PHYSWRST			(1 << 0)
+
+#define HOST_CTRL0_FSEL_MASK			(7 << 16)
+
+#define EHCICTRL_ENAINCRXALIGN			(1 << 29)
+#define EHCICTRL_ENAINCR4			(1 << 28)
+#define EHCICTRL_ENAINCR8			(1 << 27)
+#define EHCICTRL_ENAINCR16			(1 << 26)
+
+/* Register map for PHY control */
+struct s5p_usb_phy {
+	unsigned int usbphyctrl0;
+	unsigned int usbphytune0;
+	unsigned int reserved1[2];
+	unsigned int hsicphyctrl1;
+	unsigned int hsicphytune1;
+	unsigned int reserved2[2];
+	unsigned int hsicphyctrl2;
+	unsigned int hsicphytune2;
+	unsigned int reserved3[2];
+	unsigned int ehcictrl;
+	unsigned int ohcictrl;
+	unsigned int usbotgsys;
+	unsigned int reserved4;
+	unsigned int usbotgtune;
+};
+
+/* Switch on the VBUS power. */
+int board_usb_vbus_init(void);
+
+#endif /* __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ */
diff --git a/arch/arm/include/asm/arch-exynos/fb.h b/arch/arm/include/asm/arch-exynos/fb.h
new file mode 100644
index 0000000000..b10b0da07e
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/fb.h
@@ -0,0 +1,446 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * aint with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_FB_H_
+#define __ASM_ARM_ARCH_FB_H_
+
+#ifndef __ASSEMBLY__
+struct exynos4_fb {
+	unsigned int vidcon0;
+	unsigned int vidcon1;
+	unsigned int vidcon2;
+	unsigned int vidcon3;
+	unsigned int vidtcon0;
+	unsigned int vidtcon1;
+	unsigned int vidtcon2;
+	unsigned int vidtcon3;
+	unsigned int wincon0;
+	unsigned int wincon1;
+	unsigned int wincon2;
+	unsigned int wincon3;
+	unsigned int wincon4;
+
+	unsigned int winshmap;
+	unsigned int res1;
+
+	unsigned int winchmap2;
+	unsigned int vidosd0a;
+	unsigned int vidosd0b;
+	unsigned int vidosd0c;
+	unsigned int res2;
+
+	unsigned int vidosd1a;
+	unsigned int vidosd1b;
+	unsigned int vidosd1c;
+	unsigned int vidosd1d;
+
+	unsigned int vidosd2a;
+	unsigned int vidosd2b;
+	unsigned int vidosd2c;
+	unsigned int vidosd2d;
+
+	unsigned int vidosd3a;
+	unsigned int vidosd3b;
+	unsigned int vidosd3c;
+	unsigned int res3;
+
+	unsigned int vidosd4a;
+	unsigned int vidosd4b;
+	unsigned int vidosd4c;
+	unsigned int res4[5];
+
+	unsigned int vidw00add0b0;
+	unsigned int vidw00add0b1;
+	unsigned int vidw01add0b0;
+	unsigned int vidw01add0b1;
+
+	unsigned int vidw02add0b0;
+	unsigned int vidw02add0b1;
+	unsigned int vidw03add0b0;
+	unsigned int vidw03add0b1;
+	unsigned int vidw04add0b0;
+	unsigned int vidw04add0b1;
+	unsigned int res5[2];
+
+	unsigned int vidw00add1b0;
+	unsigned int vidw00add1b1;
+	unsigned int vidw01add1b0;
+	unsigned int vidw01add1b1;
+
+	unsigned int vidw02add1b0;
+	unsigned int vidw02add1b1;
+	unsigned int vidw03add1b0;
+	unsigned int vidw03add1b1;
+
+	unsigned int vidw04add1b0;
+	unsigned int vidw04add1b1;
+	unsigned int res7[2];
+
+	unsigned int vidw00add2;
+	unsigned int vidw01add2;
+	unsigned int vidw02add2;
+	unsigned int vidw03add2;
+	unsigned int vidw04add2;
+	unsigned int res8[7];
+
+	unsigned int vidintcon0;
+	unsigned int vidintcon1;
+	unsigned int res9[1];
+
+	unsigned int w1keycon0;
+	unsigned int w1keycon1;
+	unsigned int w2keycon0;
+	unsigned int w2keycon1;
+	unsigned int w3keycon0;
+	unsigned int w3keycon1;
+	unsigned int w4keycon0;
+	unsigned int w4keycon1;
+
+	unsigned int w1keyalpha;
+	unsigned int w2keyalpha;
+	unsigned int w3keyalpha;
+	unsigned int w4keyalpha;
+
+	unsigned int dithmode;
+	unsigned int res10[2];
+
+	unsigned int win0map;
+	unsigned int win1map;
+	unsigned int win2map;
+	unsigned int win3map;
+	unsigned int win4map;
+	unsigned int res11[1];
+
+	unsigned int wpalcon_h;
+	unsigned int wpalcon_l;
+
+	unsigned int trigcon;
+	unsigned int res12[2];
+
+	unsigned int i80ifcona0;
+	unsigned int i80ifcona1;
+	unsigned int i80ifconb0;
+	unsigned int i80ifconb1;
+
+	unsigned int colorgaincon;
+	unsigned int res13[2];
+
+	unsigned int ldi_cmdcon0;
+	unsigned int ldi_cmdcon1;
+	unsigned int res14[1];
+
+	/* To be updated */
+
+	unsigned char res15[156];
+	unsigned int dualrgb;
+};
+#endif
+
+/*
+ *  Register offsets
+*/
+#define EXYNOS_WINCON(x)				(x * 0x04)
+#define EXYNOS_VIDOSD(x)				(x * 0x10)
+#define EXYNOS_BUFFER_OFFSET(x)				(x * 0x08)
+#define EXYNOS_BUFFER_SIZE(x)				(x * 0x04)
+
+/*
+ * Bit Definitions
+*/
+
+/* VIDCON0 */
+#define EXYNOS_VIDCON0_DSI_DISABLE			(0 << 30)
+#define EXYNOS_VIDCON0_DSI_ENABLE			(1 << 30)
+#define EXYNOS_VIDCON0_SCAN_PROGRESSIVE			(0 << 29)
+#define EXYNOS_VIDCON0_SCAN_INTERLACE			(1 << 29)
+#define EXYNOS_VIDCON0_SCAN_MASK			(1 << 29)
+#define EXYNOS_VIDCON0_VIDOUT_RGB			(0 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_ITU			(1 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_I80LDI0			(2 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_I80LDI1			(3 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_WB_RGB			(4 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI0		(6 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI1		(7 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_MASK			(7 << 26)
+#define EXYNOS_VIDCON0_PNRMODE_RGB_P			(0 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_BGR_P			(1 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_RGB_S			(2 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_BGR_S			(3 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_MASK			(3 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_SHIFT			(17)
+#define EXYNOS_VIDCON0_CLKVALUP_ALWAYS			(0 << 16)
+#define EXYNOS_VIDCON0_CLKVALUP_START_FRAME		(1 << 16)
+#define EXYNOS_VIDCON0_CLKVALUP_MASK			(1 << 16)
+#define EXYNOS_VIDCON0_CLKVAL_F(x)			(((x) & 0xff) << 6)
+#define EXYNOS_VIDCON0_VCLKEN_NORMAL			(0 << 5)
+#define EXYNOS_VIDCON0_VCLKEN_FREERUN			(1 << 5)
+#define EXYNOS_VIDCON0_VCLKEN_MASK			(1 << 5)
+#define EXYNOS_VIDCON0_CLKDIR_DIRECTED			(0 << 4)
+#define EXYNOS_VIDCON0_CLKDIR_DIVIDED			(1 << 4)
+#define EXYNOS_VIDCON0_CLKDIR_MASK			(1 << 4)
+#define EXYNOS_VIDCON0_CLKSEL_HCLK			(0 << 2)
+#define EXYNOS_VIDCON0_CLKSEL_SCLK			(1 << 2)
+#define EXYNOS_VIDCON0_CLKSEL_MASK			(1 << 2)
+#define EXYNOS_VIDCON0_ENVID_ENABLE			(1 << 1)
+#define EXYNOS_VIDCON0_ENVID_DISABLE			(0 << 1)
+#define EXYNOS_VIDCON0_ENVID_F_ENABLE			(1 << 0)
+#define EXYNOS_VIDCON0_ENVID_F_DISABLE			(0 << 0)
+
+/* VIDCON1 */
+#define EXYNOS_VIDCON1_IVCLK_FALLING_EDGE		(0 << 7)
+#define EXYNOS_VIDCON1_IVCLK_RISING_EDGE		(1 << 7)
+#define EXYNOS_VIDCON1_IHSYNC_NORMAL			(0 << 6)
+#define EXYNOS_VIDCON1_IHSYNC_INVERT			(1 << 6)
+#define EXYNOS_VIDCON1_IVSYNC_NORMAL			(0 << 5)
+#define EXYNOS_VIDCON1_IVSYNC_INVERT			(1 << 5)
+#define EXYNOS_VIDCON1_IVDEN_NORMAL			(0 << 4)
+#define EXYNOS_VIDCON1_IVDEN_INVERT			(1 << 4)
+
+/* VIDCON2 */
+#define EXYNOS_VIDCON2_EN601_DISABLE			(0 << 23)
+#define EXYNOS_VIDCON2_EN601_ENABLE			(1 << 23)
+#define EXYNOS_VIDCON2_EN601_MASK			(1 << 23)
+#define EXYNOS_VIDCON2_WB_DISABLE			(0 << 15)
+#define EXYNOS_VIDCON2_WB_ENABLE			(1 << 15)
+#define EXYNOS_VIDCON2_WB_MASK				(1 << 15)
+#define EXYNOS_VIDCON2_TVFORMATSEL_HW			(0 << 14)
+#define EXYNOS_VIDCON2_TVFORMATSEL_SW			(1 << 14)
+#define EXYNOS_VIDCON2_TVFORMATSEL_MASK			(1 << 14)
+#define EXYNOS_VIDCON2_TVFORMATSEL_YUV422		(1 << 12)
+#define EXYNOS_VIDCON2_TVFORMATSEL_YUV444		(2 << 12)
+#define EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK		(3 << 12)
+#define EXYNOS_VIDCON2_ORGYUV_YCBCR			(0 << 8)
+#define EXYNOS_VIDCON2_ORGYUV_CBCRY			(1 << 8)
+#define EXYNOS_VIDCON2_ORGYUV_MASK			(1 << 8)
+#define EXYNOS_VIDCON2_YUVORD_CBCR			(0 << 7)
+#define EXYNOS_VIDCON2_YUVORD_CRCB			(1 << 7)
+#define EXYNOS_VIDCON2_YUVORD_MASK			(1 << 7)
+
+/* PRTCON */
+#define EXYNOS_PRTCON_UPDATABLE				(0 << 11)
+#define EXYNOS_PRTCON_PROTECT				(1 << 11)
+
+/* VIDTCON0 */
+#define EXYNOS_VIDTCON0_VBPDE(x)			(((x) & 0xff) << 24)
+#define EXYNOS_VIDTCON0_VBPD(x)				(((x) & 0xff) << 16)
+#define EXYNOS_VIDTCON0_VFPD(x)				(((x) & 0xff) << 8)
+#define EXYNOS_VIDTCON0_VSPW(x)				(((x) & 0xff) << 0)
+
+/* VIDTCON1 */
+#define EXYNOS_VIDTCON1_VFPDE(x)			(((x) & 0xff) << 24)
+#define EXYNOS_VIDTCON1_HBPD(x)				(((x) & 0xff) << 16)
+#define EXYNOS_VIDTCON1_HFPD(x)				(((x) & 0xff) << 8)
+#define EXYNOS_VIDTCON1_HSPW(x)				(((x) & 0xff) << 0)
+
+/* VIDTCON2 */
+#define EXYNOS_VIDTCON2_LINEVAL(x)			(((x) & 0x7ff) << 11)
+#define EXYNOS_VIDTCON2_HOZVAL(x)			(((x) & 0x7ff) << 0)
+
+/* Window 0~4 Control - WINCONx */
+#define EXYNOS_WINCON_DATAPATH_DMA			(0 << 22)
+#define EXYNOS_WINCON_DATAPATH_LOCAL			(1 << 22)
+#define EXYNOS_WINCON_DATAPATH_MASK			(1 << 22)
+#define EXYNOS_WINCON_BUFSEL_0				(0 << 20)
+#define EXYNOS_WINCON_BUFSEL_1				(1 << 20)
+#define EXYNOS_WINCON_BUFSEL_MASK			(1 << 20)
+#define EXYNOS_WINCON_BUFSEL_SHIFT			(20)
+#define EXYNOS_WINCON_BUFAUTO_DISABLE			(0 << 19)
+#define EXYNOS_WINCON_BUFAUTO_ENABLE			(1 << 19)
+#define EXYNOS_WINCON_BUFAUTO_MASK			(1 << 19)
+#define EXYNOS_WINCON_BITSWP_DISABLE			(0 << 18)
+#define EXYNOS_WINCON_BITSWP_ENABLE			(1 << 18)
+#define EXYNOS_WINCON_BITSWP_SHIFT			(18)
+#define EXYNOS_WINCON_BYTESWP_DISABLE			(0 << 17)
+#define EXYNOS_WINCON_BYTESWP_ENABLE			(1 << 17)
+#define EXYNOS_WINCON_BYTESWP_SHIFT			(17)
+#define EXYNOS_WINCON_HAWSWP_DISABLE			(0 << 16)
+#define EXYNOS_WINCON_HAWSWP_ENABLE			(1 << 16)
+#define EXYNOS_WINCON_HAWSWP_SHIFT			(16)
+#define EXYNOS_WINCON_WSWP_DISABLE			(0 << 15)
+#define EXYNOS_WINCON_WSWP_ENABLE			(1 << 15)
+#define EXYNOS_WINCON_WSWP_SHIFT			(15)
+#define EXYNOS_WINCON_INRGB_RGB				(0 << 13)
+#define EXYNOS_WINCON_INRGB_YUV				(1 << 13)
+#define EXYNOS_WINCON_INRGB_MASK			(1 << 13)
+#define EXYNOS_WINCON_BURSTLEN_16WORD			(0 << 9)
+#define EXYNOS_WINCON_BURSTLEN_8WORD			(1 << 9)
+#define EXYNOS_WINCON_BURSTLEN_4WORD			(2 << 9)
+#define EXYNOS_WINCON_BURSTLEN_MASK			(3 << 9)
+#define EXYNOS_WINCON_ALPHA_MULTI_DISABLE		(0 << 7)
+#define EXYNOS_WINCON_ALPHA_MULTI_ENABLE		(1 << 7)
+#define EXYNOS_WINCON_BLD_PLANE				(0 << 6)
+#define EXYNOS_WINCON_BLD_PIXEL				(1 << 6)
+#define EXYNOS_WINCON_BLD_MASK				(1 << 6)
+#define EXYNOS_WINCON_BPPMODE_1BPP			(0 << 2)
+#define EXYNOS_WINCON_BPPMODE_2BPP			(1 << 2)
+#define EXYNOS_WINCON_BPPMODE_4BPP			(2 << 2)
+#define EXYNOS_WINCON_BPPMODE_8BPP_PAL			(3 << 2)
+#define EXYNOS_WINCON_BPPMODE_8BPP			(4 << 2)
+#define EXYNOS_WINCON_BPPMODE_16BPP_565			(5 << 2)
+#define EXYNOS_WINCON_BPPMODE_16BPP_A555		(6 << 2)
+#define EXYNOS_WINCON_BPPMODE_18BPP_666			(8 << 2)
+#define EXYNOS_WINCON_BPPMODE_18BPP_A665		(9 << 2)
+#define EXYNOS_WINCON_BPPMODE_24BPP_888			(0xb << 2)
+#define EXYNOS_WINCON_BPPMODE_24BPP_A887		(0xc << 2)
+#define EXYNOS_WINCON_BPPMODE_32BPP			(0xd << 2)
+#define EXYNOS_WINCON_BPPMODE_16BPP_A444		(0xe << 2)
+#define EXYNOS_WINCON_BPPMODE_15BPP_555			(0xf << 2)
+#define EXYNOS_WINCON_BPPMODE_MASK			(0xf << 2)
+#define EXYNOS_WINCON_BPPMODE_SHIFT			(2)
+#define EXYNOS_WINCON_ALPHA0_SEL			(0 << 1)
+#define EXYNOS_WINCON_ALPHA1_SEL			(1 << 1)
+#define EXYNOS_WINCON_ALPHA_SEL_MASK			(1 << 1)
+#define EXYNOS_WINCON_ENWIN_DISABLE			(0 << 0)
+#define EXYNOS_WINCON_ENWIN_ENABLE			(1 << 0)
+
+/* WINCON1 special */
+#define EXYNOS_WINCON1_VP_DISABLE			(0 << 24)
+#define EXYNOS_WINCON1_VP_ENABLE			(1 << 24)
+#define EXYNOS_WINCON1_LOCALSEL_FIMC1			(0 << 23)
+#define EXYNOS_WINCON1_LOCALSEL_VP			(1 << 23)
+#define EXYNOS_WINCON1_LOCALSEL_MASK			(1 << 23)
+
+/* WINSHMAP */
+#define EXYNOS_WINSHMAP_PROTECT(x)			(((x) & 0x1f) << 10)
+#define EXYNOS_WINSHMAP_CH_ENABLE(x)			(1 << (x))
+#define EXYNOS_WINSHMAP_CH_DISABLE(x)			(1 << (x))
+#define EXYNOS_WINSHMAP_LOCAL_ENABLE(x)			(0x20 << (x))
+#define EXYNOS_WINSHMAP_LOCAL_DISABLE(x)		(0x20 << (x))
+
+/* VIDOSDxA, VIDOSDxB */
+#define EXYNOS_VIDOSD_LEFT_X(x)				(((x) & 0x7ff) << 11)
+#define EXYNOS_VIDOSD_TOP_Y(x)				(((x) & 0x7ff) << 0)
+#define EXYNOS_VIDOSD_RIGHT_X(x)			(((x) & 0x7ff) << 11)
+#define EXYNOS_VIDOSD_BOTTOM_Y(x)			(((x) & 0x7ff) << 0)
+
+/* VIDOSD0C, VIDOSDxD */
+#define EXYNOS_VIDOSD_SIZE(x)				(((x) & 0xffffff) << 0)
+
+/* VIDOSDxC (1~4) */
+#define EXYNOS_VIDOSD_ALPHA0_R(x)			(((x) & 0xf) << 20)
+#define EXYNOS_VIDOSD_ALPHA0_G(x)			(((x) & 0xf) << 16)
+#define EXYNOS_VIDOSD_ALPHA0_B(x)			(((x) & 0xf) << 12)
+#define EXYNOS_VIDOSD_ALPHA1_R(x)			(((x) & 0xf) << 8)
+#define EXYNOS_VIDOSD_ALPHA1_G(x)			(((x) & 0xf) << 4)
+#define EXYNOS_VIDOSD_ALPHA1_B(x)			(((x) & 0xf) << 0)
+#define EXYNOS_VIDOSD_ALPHA0_SHIFT			(12)
+#define EXYNOS_VIDOSD_ALPHA1_SHIFT			(0)
+
+/* Start Address */
+#define EXYNOS_VIDADDR_START_VBANK(x)			(((x) & 0xff) << 24)
+#define EXYNOS_VIDADDR_START_VBASEU(x)			(((x) & 0xffffff) << 0)
+
+/* End Address */
+#define EXYNOS_VIDADDR_END_VBASEL(x)			(((x) & 0xffffff) << 0)
+
+/* Buffer Size */
+#define EXYNOS_VIDADDR_OFFSIZE(x)			(((x) & 0x1fff) << 13)
+#define EXYNOS_VIDADDR_PAGEWIDTH(x)			(((x) & 0x1fff) << 0)
+
+/* WIN Color Map */
+#define EXYNOS_WINMAP_COLOR(x)				((x) & 0xffffff)
+
+/* VIDINTCON0 */
+#define EXYNOS_VIDINTCON0_SYSMAINCON_DISABLE		(0 << 19)
+#define EXYNOS_VIDINTCON0_SYSMAINCON_ENABLE		(1 << 19)
+#define EXYNOS_VIDINTCON0_SYSSUBCON_DISABLE		(0 << 18)
+#define EXYNOS_VIDINTCON0_SYSSUBCON_ENABLE		(1 << 18)
+#define EXYNOS_VIDINTCON0_SYSIFDONE_DISABLE		(0 << 17)
+#define EXYNOS_VIDINTCON0_SYSIFDONE_ENABLE		(1 << 17)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_BACK		(0 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_VSYNC		(1 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_ACTIVE		(2 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_FRONT		(3 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_MASK		(3 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL1_NONE		(0 << 13)
+#define EXYNOS_VIDINTCON0_FRAMESEL1_BACK		(1 << 13)
+#define EXYNOS_VIDINTCON0_FRAMESEL1_VSYNC		(2 << 13)
+#define EXYNOS_VIDINTCON0_FRAMESEL1_FRONT		(3 << 13)
+#define EXYNOS_VIDINTCON0_INTFRMEN_DISABLE		(0 << 12)
+#define EXYNOS_VIDINTCON0_INTFRMEN_ENABLE		(1 << 12)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN4			(1 << 11)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN3			(1 << 10)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN2			(1 << 9)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN1			(1 << 6)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN0			(1 << 5)
+#define EXYNOS_VIDINTCON0_FIFOSEL_ALL			(0x73 << 5)
+#define EXYNOS_VIDINTCON0_FIFOSEL_MASK			(0x73 << 5)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_25			(0 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_50			(1 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_75			(2 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_EMPTY		(3 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_FULL		(4 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_MASK		(7 << 2)
+#define EXYNOS_VIDINTCON0_INTFIFO_DISABLE		(0 << 1)
+#define EXYNOS_VIDINTCON0_INTFIFO_ENABLE		(1 << 1)
+#define EXYNOS_VIDINTCON0_INT_DISABLE			(0 << 0)
+#define EXYNOS_VIDINTCON0_INT_ENABLE			(1 << 0)
+#define EXYNOS_VIDINTCON0_INT_MASK			(1 << 0)
+
+/* VIDINTCON1 */
+#define EXYNOS_VIDINTCON1_INTVPPEND			(1 << 5)
+#define EXYNOS_VIDINTCON1_INTI80PEND			(1 << 2)
+#define EXYNOS_VIDINTCON1_INTFRMPEND			(1 << 1)
+#define EXYNOS_VIDINTCON1_INTFIFOPEND			(1 << 0)
+
+/* WINMAP */
+#define EXYNOS_WINMAP_ENABLE				(1 << 24)
+
+/* WxKEYCON0 (1~4) */
+#define EXYNOS_KEYCON0_KEYBLEN_DISABLE			(0 << 26)
+#define EXYNOS_KEYCON0_KEYBLEN_ENABLE			(1 << 26)
+#define EXYNOS_KEYCON0_KEY_DISABLE			(0 << 25)
+#define EXYNOS_KEYCON0_KEY_ENABLE			(1 << 25)
+#define EXYNOS_KEYCON0_DIRCON_MATCH_FG			(0 << 24)
+#define EXYNOS_KEYCON0_DIRCON_MATCH_BG			(1 << 24)
+#define EXYNOS_KEYCON0_COMPKEY(x)			(((x) & 0xffffff) << 0)
+
+/* WxKEYCON1 (1~4) */
+#define EXYNOS_KEYCON1_COLVAL(x)			(((x) & 0xffffff) << 0)
+
+/* DUALRGB */
+#define EXYNOS_DUALRGB_BYPASS_SINGLE			(0x00 << 0)
+#define EXYNOS_DUALRGB_BYPASS_DUAL			(0x01 << 0)
+#define EXYNOS_DUALRGB_MIE_DUAL				(0x10 << 0)
+#define EXYNOS_DUALRGB_MIE_SINGLE			(0x11 << 0)
+#define EXYNOS_DUALRGB_LINESPLIT			(0x0 << 2)
+#define EXYNOS_DUALRGB_FRAMESPLIT			(0x1 << 2)
+#define EXYNOS_DUALRGB_SUB_CNT(x)			((x & 0xfff) << 4)
+#define EXYNOS_DUALRGB_VDEN_EN_DISABLE			(0x0 << 16)
+#define EXYNOS_DUALRGB_VDEN_EN_ENABLE			(0x1 << 16)
+#define EXYNOS_DUALRGB_MAIN_CNT(x)			((x & 0xfff) << 18)
+
+/* I80IFCONA0 and I80IFCONA1 */
+#define EXYNOS_LCD_CS_SETUP(x)				(((x) & 0xf) << 16)
+#define EXYNOS_LCD_WR_SETUP(x)				(((x) & 0xf) << 12)
+#define EXYNOS_LCD_WR_ACT(x)				(((x) & 0xf) << 8)
+#define EXYNOS_LCD_WR_HOLD(x)				(((x) & 0xf) << 4)
+#define EXYNOS_RSPOL_LOW				(0 << 2)
+#define EXYNOS_RSPOL_HIGH				(1 << 2)
+#define EXYNOS_I80IFEN_DISABLE				(0 << 0)
+#define EXYNOS_I80IFEN_ENABLE				(1 << 0)
+
+/* TRIGCON */
+#define EXYNOS_I80SOFT_TRIG_EN				(1 << 0)
+#define EXYNOS_I80START_TRIG				(1 << 1)
+#define EXYNOS_I80STATUS_TRIG_DONE			(1 << 2)
+
+#endif /* _REGS_FB_H */
diff --git a/arch/arm/include/asm/arch-exynos/mipi_dsim.h b/arch/arm/include/asm/arch-exynos/mipi_dsim.h
new file mode 100644
index 0000000000..ef6a3d1123
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/mipi_dsim.h
@@ -0,0 +1,380 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: InKi Dae <inki.dae@samsung.com>
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _DSIM_H
+#define _DSIM_H
+
+#include <linux/list.h>
+#include <linux/fb.h>
+
+#define PANEL_NAME_SIZE		(32)
+
+enum mipi_dsim_interface_type {
+	DSIM_COMMAND,
+	DSIM_VIDEO
+};
+
+enum mipi_dsim_virtual_ch_no {
+	DSIM_VIRTUAL_CH_0,
+	DSIM_VIRTUAL_CH_1,
+	DSIM_VIRTUAL_CH_2,
+	DSIM_VIRTUAL_CH_3
+};
+
+enum mipi_dsim_burst_mode_type {
+	DSIM_NON_BURST_SYNC_EVENT,
+	DSIM_BURST_SYNC_EVENT,
+	DSIM_NON_BURST_SYNC_PULSE,
+	DSIM_BURST,
+	DSIM_NON_VIDEO_MODE
+};
+
+enum mipi_dsim_no_of_data_lane {
+	DSIM_DATA_LANE_1,
+	DSIM_DATA_LANE_2,
+	DSIM_DATA_LANE_3,
+	DSIM_DATA_LANE_4
+};
+
+enum mipi_dsim_byte_clk_src {
+	DSIM_PLL_OUT_DIV8,
+	DSIM_EXT_CLK_DIV8,
+	DSIM_EXT_CLK_BYPASS
+};
+
+enum mipi_dsim_pixel_format {
+	DSIM_CMD_3BPP,
+	DSIM_CMD_8BPP,
+	DSIM_CMD_12BPP,
+	DSIM_CMD_16BPP,
+	DSIM_VID_16BPP_565,
+	DSIM_VID_18BPP_666PACKED,
+	DSIM_18BPP_666LOOSELYPACKED,
+	DSIM_24BPP_888
+};
+
+/* MIPI DSI Processor-to-Peripheral transaction types */
+enum {
+	MIPI_DSI_V_SYNC_START				= 0x01,
+	MIPI_DSI_V_SYNC_END				= 0x11,
+	MIPI_DSI_H_SYNC_START				= 0x21,
+	MIPI_DSI_H_SYNC_END				= 0x31,
+
+	MIPI_DSI_COLOR_MODE_OFF				= 0x02,
+	MIPI_DSI_COLOR_MODE_ON				= 0x12,
+	MIPI_DSI_SHUTDOWN_PERIPHERAL			= 0x22,
+	MIPI_DSI_TURN_ON_PERIPHERAL			= 0x32,
+
+	MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM		= 0x03,
+	MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM		= 0x13,
+	MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM		= 0x23,
+
+	MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM		= 0x04,
+	MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM		= 0x14,
+	MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM		= 0x24,
+
+	MIPI_DSI_DCS_SHORT_WRITE			= 0x05,
+	MIPI_DSI_DCS_SHORT_WRITE_PARAM			= 0x15,
+
+	MIPI_DSI_DCS_READ				= 0x06,
+
+	MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE		= 0x37,
+
+	MIPI_DSI_END_OF_TRANSMISSION			= 0x08,
+
+	MIPI_DSI_NULL_PACKET				= 0x09,
+	MIPI_DSI_BLANKING_PACKET			= 0x19,
+	MIPI_DSI_GENERIC_LONG_WRITE			= 0x29,
+	MIPI_DSI_DCS_LONG_WRITE				= 0x39,
+
+	MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20	= 0x0c,
+	MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24		= 0x1c,
+	MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16		= 0x2c,
+
+	MIPI_DSI_PACKED_PIXEL_STREAM_30			= 0x0d,
+	MIPI_DSI_PACKED_PIXEL_STREAM_36			= 0x1d,
+	MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12		= 0x3d,
+
+	MIPI_DSI_PACKED_PIXEL_STREAM_16			= 0x0e,
+	MIPI_DSI_PACKED_PIXEL_STREAM_18			= 0x1e,
+	MIPI_DSI_PIXEL_STREAM_3BYTE_18			= 0x2e,
+	MIPI_DSI_PACKED_PIXEL_STREAM_24			= 0x3e,
+};
+
+/*
+ * struct mipi_dsim_config - interface for configuring mipi-dsi controller.
+ *
+ * @auto_flush: enable or disable Auto flush of MD FIFO using VSYNC pulse.
+ * @eot_disable: enable or disable EoT packet in HS mode.
+ * @auto_vertical_cnt: specifies auto vertical count mode.
+ *	in Video mode, the vertical line transition uses line counter
+ *	configured by VSA, VBP, and Vertical resolution.
+ *	If this bit is set to '1', the line counter does not use VSA and VBP
+ *	registers.(in command mode, this variable is ignored)
+ * @hse: set horizontal sync event mode.
+ *	In VSYNC pulse and Vporch area, MIPI DSI master transfers only HSYNC
+ *	start packet to MIPI DSI slave at MIPI DSI spec1.1r02.
+ *	this bit transfers HSYNC end packet in VSYNC pulse and Vporch area
+ *	(in mommand mode, this variable is ignored)
+ * @hfp: specifies HFP disable mode.
+ *	if this variable is set, DSI master ignores HFP area in VIDEO mode.
+ *	(in command mode, this variable is ignored)
+ * @hbp: specifies HBP disable mode.
+ *	if this variable is set, DSI master ignores HBP area in VIDEO mode.
+ *	(in command mode, this variable is ignored)
+ * @hsa: specifies HSA disable mode.
+ *	if this variable is set, DSI master ignores HSA area in VIDEO mode.
+ *	(in command mode, this variable is ignored)
+ * @e_interface: specifies interface to be used.(CPU or RGB interface)
+ * @e_virtual_ch: specifies virtual channel number that main or
+ *	sub diaplsy uses.
+ * @e_pixel_format: specifies pixel stream format for main or sub display.
+ * @e_burst_mode: selects Burst mode in Video mode.
+ *	in Non-burst mode, RGB data area is filled with RGB data and NULL
+ *	packets, according to input bandwidth of RGB interface.
+ *	In Burst mode, RGB data area is filled with RGB data only.
+ * @e_no_data_lane: specifies data lane count to be used by Master.
+ * @e_byte_clk: select byte clock source. (it must be DSIM_PLL_OUT_DIV8)
+ *	DSIM_EXT_CLK_DIV8 and DSIM_EXT_CLK_BYPASSS are not supported.
+ * @pll_stable_time: specifies the PLL Timer for stability of the ganerated
+ *	clock(System clock cycle base)
+ *	if the timer value goes to 0x00000000, the clock stable bit of status
+ *	and interrupt register is set.
+ * @esc_clk: specifies escape clock frequency for getting the escape clock
+ *	prescaler value.
+ * @stop_holding_cnt: specifies the interval value between transmitting
+ *	read packet(or write "set_tear_on" command) and BTA request.
+ *	after transmitting read packet or write "set_tear_on" command,
+ *	BTA requests to D-PHY automatically. this counter value specifies
+ *	the interval between them.
+ * @bta_timeout: specifies the timer for BTA.
+ *	this register specifies time out from BTA request to change
+ *	the direction with respect to Tx escape clock.
+ * @rx_timeout: specifies the timer for LP Rx mode timeout.
+ *	this register specifies time out on how long RxValid deasserts,
+ *	after RxLpdt asserts with respect to Tx escape clock.
+ *	- RxValid specifies Rx data valid indicator.
+ *	- RxLpdt specifies an indicator that D-PHY is under RxLpdt mode.
+ *	- RxValid and RxLpdt specifies signal from D-PHY.
+ */
+struct mipi_dsim_config {
+	unsigned char			auto_flush;
+	unsigned char			eot_disable;
+
+	unsigned char			auto_vertical_cnt;
+	unsigned char			hse;
+	unsigned char			hfp;
+	unsigned char			hbp;
+	unsigned char			hsa;
+
+	enum mipi_dsim_interface_type	e_interface;
+	enum mipi_dsim_virtual_ch_no	e_virtual_ch;
+	enum mipi_dsim_pixel_format	e_pixel_format;
+	enum mipi_dsim_burst_mode_type	e_burst_mode;
+	enum mipi_dsim_no_of_data_lane	e_no_data_lane;
+	enum mipi_dsim_byte_clk_src	e_byte_clk;
+
+	/*
+	 * ===========================================
+	 * |    P    |    M    |    S    |    MHz    |
+	 * -------------------------------------------
+	 * |    3    |   100   |    3    |    100    |
+	 * |    3    |   100   |    2    |    200    |
+	 * |    3    |    63   |    1    |    252    |
+	 * |    4    |   100   |    1    |    300    |
+	 * |    4    |   110   |    1    |    330    |
+	 * |   12    |   350   |    1    |    350    |
+	 * |    3    |   100   |    1    |    400    |
+	 * |    4    |   150   |    1    |    450    |
+	 * |    6    |   118   |    1    |    472    |
+	 * |	3    |   120   |    1    |    480    |
+	 * |   12    |   250   |    0    |    500    |
+	 * |    4    |   100   |    0    |    600    |
+	 * |    3    |    81   |    0    |    648    |
+	 * |    3    |    88   |    0    |    704    |
+	 * |    3    |    90   |    0    |    720    |
+	 * |    3    |   100   |    0    |    800    |
+	 * |   12    |   425   |    0    |    850    |
+	 * |    4    |   150   |    0    |    900    |
+	 * |   12    |   475   |    0    |    950    |
+	 * |    6    |   250   |    0    |   1000    |
+	 * -------------------------------------------
+	 */
+
+	/*
+	 * pms could be calculated as the following.
+	 * M * 24 / P * 2 ^ S = MHz
+	 */
+	unsigned char			p;
+	unsigned short			m;
+	unsigned char			s;
+
+	unsigned int			pll_stable_time;
+	unsigned long			esc_clk;
+
+	unsigned short			stop_holding_cnt;
+	unsigned char			bta_timeout;
+	unsigned short			rx_timeout;
+};
+
+/*
+ * struct mipi_dsim_device - global interface for mipi-dsi driver.
+ *
+ * @dsim_config: infomation for configuring mipi-dsi controller.
+ * @master_ops: callbacks to mipi-dsi operations.
+ * @dsim_lcd_dev: pointer to activated ddi device.
+ *	(it would be registered by mipi-dsi driver.)
+ * @dsim_lcd_drv: pointer to activated_ddi driver.
+ *	(it would be registered by mipi-dsi driver.)
+ * @state: specifies status of MIPI-DSI controller.
+ *	the status could be RESET, INIT, STOP, HSCLKEN and ULPS.
+ * @data_lane: specifiec enabled data lane number.
+ *	this variable would be set by driver according to e_no_data_lane
+ *	automatically.
+ * @e_clk_src: select byte clock source.
+ * @pd: pointer to MIPI-DSI driver platform data.
+ */
+struct mipi_dsim_device {
+	struct mipi_dsim_config		*dsim_config;
+	struct mipi_dsim_master_ops	*master_ops;
+	struct mipi_dsim_lcd_device	*dsim_lcd_dev;
+	struct mipi_dsim_lcd_driver	*dsim_lcd_drv;
+
+	unsigned int			state;
+	unsigned int			data_lane;
+	enum mipi_dsim_byte_clk_src	e_clk_src;
+
+	struct exynos_platform_mipi_dsim	*pd;
+};
+
+/*
+ * struct exynos_platform_mipi_dsim - interface to platform data
+ *	for mipi-dsi driver.
+ *
+ * @lcd_panel_name: specifies lcd panel name registered to mipi-dsi driver.
+ *	lcd panel driver searched would be actived.
+ * @dsim_config: pointer of structure for configuring mipi-dsi controller.
+ * @lcd_panel_info: pointer for lcd panel specific structure.
+ *	this structure specifies width, height, timing and polarity and so on.
+ * @lcd_power: callback pointer for enabling or disabling lcd power.
+ * @mipi_power: callback pointer for enabling or disabling mipi power.
+ * @phy_enable: pointer to a callback controlling D-PHY enable/reset
+ */
+struct exynos_platform_mipi_dsim {
+	char				lcd_panel_name[PANEL_NAME_SIZE];
+
+	struct mipi_dsim_config		*dsim_config;
+	void				*lcd_panel_info;
+
+	int (*lcd_power)(void);
+	int (*mipi_power)(void);
+	void (*phy_enable)(unsigned int dev_index, unsigned int enable);
+};
+
+/*
+ * struct mipi_dsim_master_ops - callbacks to mipi-dsi operations.
+ *
+ * @cmd_write: transfer command to lcd panel at LP mode.
+ * @cmd_read: read command from rx register.
+ * @get_dsim_frame_done: get the status that all screen data have been
+ *	transferred to mipi-dsi.
+ * @clear_dsim_frame_done: clear frame done status.
+ * @get_fb_frame_done: get frame done status of display controller.
+ * @trigger: trigger display controller.
+ *	- this one would be used only in case of CPU mode.
+ */
+struct mipi_dsim_master_ops {
+	int (*cmd_write)(struct mipi_dsim_device *dsim, unsigned int data_id,
+		unsigned int data0, unsigned int data1);
+	int (*cmd_read)(struct mipi_dsim_device *dsim, unsigned int data_id,
+		unsigned int data0, unsigned int data1);
+	int (*get_dsim_frame_done)(struct mipi_dsim_device *dsim);
+	int (*clear_dsim_frame_done)(struct mipi_dsim_device *dsim);
+
+	int (*get_fb_frame_done)(void);
+	void (*trigger)(struct fb_info *info);
+};
+
+/*
+ * device structure for mipi-dsi based lcd panel.
+ *
+ * @name: name of the device to use with this device, or an
+ *	alias for that name.
+ * @id: id of device to be registered.
+ * @bus_id: bus id for identifing connected bus
+ *	and this bus id should be same as id of mipi_dsim_device.
+ * @master: pointer to mipi-dsi master device object.
+ * @platform_data: lcd panel specific platform data.
+ */
+struct mipi_dsim_lcd_device {
+	char			*name;
+	int			id;
+	int			bus_id;
+
+	struct mipi_dsim_device *master;
+	void			*platform_data;
+};
+
+/*
+ * driver structure for mipi-dsi based lcd panel.
+ *
+ * this structure should be registered by lcd panel driver.
+ * mipi-dsi driver seeks lcd panel registered through name field
+ * and calls these callback functions in appropriate time.
+ *
+ * @name: name of the driver to use with this device, or an
+ *	alias for that name.
+ * @id: id of driver to be registered.
+ *	this id would be used for finding device object registered.
+ * @mipi_panel_init: callback pointer for initializing lcd panel based on mipi
+ *	dsi interface.
+ * @mipi_display_on: callback pointer for lcd panel display on.
+ */
+struct mipi_dsim_lcd_driver {
+	char			*name;
+	int			id;
+
+	int	(*mipi_panel_init)(struct mipi_dsim_device *dsim_dev);
+	void	(*mipi_display_on)(struct mipi_dsim_device *dsim_dev);
+};
+
+int exynos_mipi_dsi_init(void);
+
+/*
+ * register mipi_dsim_lcd_driver object defined by lcd panel driver
+ * to mipi-dsi driver.
+ */
+int exynos_mipi_dsi_register_lcd_driver(struct mipi_dsim_lcd_driver
+						*lcd_drv);
+
+/*
+ * register mipi_dsim_lcd_device to mipi-dsi master.
+ */
+int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device
+						*lcd_dev);
+
+void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd);
+
+/* panel driver init based on mipi dsi interface */
+void s6e8ax0_init(void);
+
+#endif /* _DSIM_H */
diff --git a/arch/arm/include/asm/arch-exynos/mmc.h b/arch/arm/include/asm/arch-exynos/mmc.h
index 30f82b8aaf..0f701c9012 100644
--- a/arch/arm/include/asm/arch-exynos/mmc.h
+++ b/arch/arm/include/asm/arch-exynos/mmc.h
@@ -21,53 +21,54 @@
 #ifndef __ASM_ARCH_MMC_H_
 #define __ASM_ARCH_MMC_H_
 
-#ifndef __ASSEMBLY__
-struct s5p_mmc {
-	unsigned int	sysad;
-	unsigned short	blksize;
-	unsigned short	blkcnt;
-	unsigned int	argument;
-	unsigned short	trnmod;
-	unsigned short	cmdreg;
-	unsigned int	rspreg0;
-	unsigned int	rspreg1;
-	unsigned int	rspreg2;
-	unsigned int	rspreg3;
-	unsigned int	bdata;
-	unsigned int	prnsts;
-	unsigned char	hostctl;
-	unsigned char	pwrcon;
-	unsigned char	blkgap;
-	unsigned char	wakcon;
-	unsigned short	clkcon;
-	unsigned char	timeoutcon;
-	unsigned char	swrst;
-	unsigned int	norintsts;	/* errintsts */
-	unsigned int	norintstsen;	/* errintstsen */
-	unsigned int	norintsigen;	/* errintsigen */
-	unsigned short	acmd12errsts;
-	unsigned char	res1[2];
-	unsigned int	capareg;
-	unsigned char	res2[4];
-	unsigned int	maxcurr;
-	unsigned char	res3[0x34];
-	unsigned int	control2;
-	unsigned int	control3;
-	unsigned char	res4[4];
-	unsigned int	control4;
-	unsigned char	res5[0x6e];
-	unsigned short	hcver;
-	unsigned char	res6[0xFF00];
-};
+#define SDHCI_CONTROL2		0x80
+#define SDHCI_CONTROL3		0x84
+#define SDHCI_CONTROL4		0x8C
 
-struct mmc_host {
-	struct s5p_mmc *reg;
-	unsigned int version;	/* SDHCI spec. version */
-	unsigned int clock;	/* Current clock (MHz) */
-	int dev_index;
-};
+#define SDHCI_CTRL2_ENSTAASYNCCLR	(1 << 31)
+#define SDHCI_CTRL2_ENCMDCNFMSK		(1 << 30)
+#define SDHCI_CTRL2_CDINVRXD3		(1 << 29)
+#define SDHCI_CTRL2_SLCARDOUT		(1 << 28)
 
-int s5p_mmc_init(int dev_index, int bus_width);
+#define SDHCI_CTRL2_FLTCLKSEL_MASK	(0xf << 24)
+#define SDHCI_CTRL2_FLTCLKSEL_SHIFT	(24)
+#define SDHCI_CTRL2_FLTCLKSEL(_x)	((_x) << 24)
 
-#endif	/* __ASSEMBLY__ */
+#define SDHCI_CTRL2_LVLDAT_MASK		(0xff << 16)
+#define SDHCI_CTRL2_LVLDAT_SHIFT	(16)
+#define SDHCI_CTRL2_LVLDAT(_x)		((_x) << 16)
+
+#define SDHCI_CTRL2_ENFBCLKTX		(1 << 15)
+#define SDHCI_CTRL2_ENFBCLKRX		(1 << 14)
+#define SDHCI_CTRL2_SDCDSEL		(1 << 13)
+#define SDHCI_CTRL2_SDSIGPC		(1 << 12)
+#define SDHCI_CTRL2_ENBUSYCHKTXSTART	(1 << 11)
+
+#define SDHCI_CTRL2_DFCNT_MASK(_x)	((_x) << 9)
+#define SDHCI_CTRL2_DFCNT_SHIFT		(9)
+
+#define SDHCI_CTRL2_ENCLKOUTHOLD	(1 << 8)
+#define SDHCI_CTRL2_RWAITMODE		(1 << 7)
+#define SDHCI_CTRL2_DISBUFRD		(1 << 6)
+#define SDHCI_CTRL2_SELBASECLK_MASK(_x)	((_x) << 4)
+#define SDHCI_CTRL2_SELBASECLK_SHIFT	(4)
+#define SDHCI_CTRL2_PWRSYNC		(1 << 3)
+#define SDHCI_CTRL2_ENCLKOUTMSKCON	(1 << 1)
+#define SDHCI_CTRL2_HWINITFIN		(1 << 0)
+
+#define SDHCI_CTRL3_FCSEL3		(1 << 31)
+#define SDHCI_CTRL3_FCSEL2		(1 << 23)
+#define SDHCI_CTRL3_FCSEL1		(1 << 15)
+#define SDHCI_CTRL3_FCSEL0		(1 << 7)
+
+#define SDHCI_CTRL4_DRIVE_MASK(_x)	((_x) << 16)
+#define SDHCI_CTRL4_DRIVE_SHIFT		(16)
+
+int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
+
+static inline unsigned int s5p_mmc_init(int index, int bus_width)
+{
+	unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
+	return s5p_sdhci_init(base, 52000000, 400000, index);
+}
 #endif
diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h
index fb442f7f1f..6444fd04ec 100644
--- a/arch/arm/include/asm/arch-exynos/power.h
+++ b/arch/arm/include/asm/arch-exynos/power.h
@@ -227,4 +227,10 @@ struct exynos4_power {
 };
 #endif	/* __ASSEMBLY__ */
 
+void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable);
+
+#define EXYNOS_MIPI_PHY_ENABLE		(1 << 0)
+#define EXYNOS_MIPI_PHY_SRESETN		(1 << 1)
+#define EXYNOS_MIPI_PHY_MRESETN		(1 << 2)
+
 #endif
diff --git a/arch/arm/include/asm/arch-exynos/system.h b/arch/arm/include/asm/arch-exynos/system.h
new file mode 100644
index 0000000000..c85f949da4
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/system.h
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_SYSTEM_H_
+#define __ASM_ARM_ARCH_SYSTEM_H_
+
+#ifndef __ASSEMBLY__
+struct exynos4_sysreg {
+	unsigned char	res1[0x210];
+	unsigned int	display_ctrl;
+	unsigned int	display_ctrl2;
+	unsigned int	camera_control;
+	unsigned int	audio_endian;
+	unsigned int	jtag_con;
+};
+
+struct exynos5_sysreg {
+	unsigned char	res1[0x214];
+	unsigned int	disp1blk_cfg;
+	unsigned int	disp2blk_cfg;
+	unsigned int	hdcp_e_fuse;
+	unsigned int	gsclblk_cfg0;
+	unsigned int	gsclblk_cfg1;
+	unsigned int	reserved;
+	unsigned int	ispblk_cfg;
+	unsigned int	usb20phy_cfg;
+	unsigned int	mipi_dphy;
+	unsigned int	dptx_dphy;
+	unsigned int	phyclk_sel;
+};
+#endif
+
+void set_system_display_ctrl(void);
+
+#endif	/* _EXYNOS4_SYSTEM_H */
diff --git a/arch/arm/include/asm/arch-exynos/tzpc.h b/arch/arm/include/asm/arch-exynos/tzpc.h
index 2c9a07be45..c5eb4b1cc2 100644
--- a/arch/arm/include/asm/arch-exynos/tzpc.h
+++ b/arch/arm/include/asm/arch-exynos/tzpc.h
@@ -22,7 +22,7 @@
 #define __TZPC_H_
 
 #ifndef __ASSEMBLY__
-struct exynos5_tzpc {
+struct exynos_tzpc {
 	unsigned int r0size;
 	char res1[0x7FC];
 	unsigned int decprot0stat;
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h
new file mode 100644
index 0000000000..c1dad0a444
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef _LPC32XX_CLK_H
+#define _LPC32XX_CLK_H
+
+#include <asm/types.h>
+
+#define OSC_CLK_FREQUENCY	13000000
+#define RTC_CLK_FREQUENCY	32768
+
+/* Clocking and Power Control Registers */
+struct clk_pm_regs {
+	u32 reserved0[5];
+	u32 boot_map;		/* Boot Map Control Register		*/
+	u32 p0_intr_er;		/* Port 0/1 Start and Interrupt Enable	*/
+	u32 usbdiv_ctrl;	/* USB Clock Pre-Divide Register	*/
+	/* Internal Start Signal Sources Registers	*/
+	u32 start_er_int;	/* Start Enable Register		*/
+	u32 start_rsr_int;	/* Start Raw Status Register		*/
+	u32 start_sr_int;	/* Start Status Register		*/
+	u32 start_apr_int;	/* Start Activation Polarity Register	*/
+	/* Device Pin Start Signal Sources Registers	*/
+	u32 start_er_pin;	/* Start Enable Register		*/
+	u32 start_rsr_pin;	/* Start Raw Status Register		*/
+	u32 start_sr_pin;	/* Start Status Register		*/
+	u32 start_apr_pin;	/* Start Activation Polarity Register	*/
+	/* Clock Control Registers			*/
+	u32 hclkdiv_ctrl;	/* HCLK Divider Control Register	*/
+	u32 pwr_ctrl;		/* Power Control Register		*/
+	u32 pll397_ctrl;	/* PLL397 Control Register		*/
+	u32 osc_ctrl;		/* Main Oscillator Control Register	*/
+	u32 sysclk_ctrl;	/* SYSCLK Control Register		*/
+	u32 lcdclk_ctrl;	/* LCD Clock Control Register		*/
+	u32 hclkpll_ctrl;	/* HCLK PLL Control Register		*/
+	u32 reserved1;
+	u32 adclk_ctrl1;	/* ADC Clock Control1 Register		*/
+	u32 usb_ctrl;		/* USB Control Register			*/
+	u32 sdramclk_ctrl;	/* SDRAM Clock Control Register		*/
+	u32 ddr_lap_nom;	/* DDR Calibration Nominal Value	*/
+	u32 ddr_lap_count;	/* DDR Calibration Measured Value	*/
+	u32 ddr_cal_delay;	/* DDR Calibration Delay Value		*/
+	u32 ssp_ctrl;		/* SSP Control Register			*/
+	u32 i2s_ctrl;		/* I2S Clock Control Register		*/
+	u32 ms_ctrl;		/* Memory Card Control Register		*/
+	u32 reserved2[3];
+	u32 macclk_ctrl;	/* Ethernet MAC Clock Control Register	*/
+	u32 reserved3[4];
+	u32 test_clk;		/* Test Clock Selection Register	*/
+	u32 sw_int;		/* Software Interrupt Register		*/
+	u32 i2cclk_ctrl;	/* I2C Clock Control Register		*/
+	u32 keyclk_ctrl;	/* Keyboard Scan Clock Control Register	*/
+	u32 adclk_ctrl;		/* ADC Clock Control Register		*/
+	u32 pwmclk_ctrl;	/* PWM Clock Control Register		*/
+	u32 timclk_ctrl;	/* Watchdog and Highspeed Timer Control */
+	u32 timclk_ctrl1;	/* Motor and Timer Clock Control	*/
+	u32 spi_ctrl;		/* SPI Control Register			*/
+	u32 flashclk_ctrl;	/* NAND Flash Clock Control Register	*/
+	u32 reserved4;
+	u32 u3clk;		/* UART 3 Clock Control Register	*/
+	u32 u4clk;		/* UART 4 Clock Control Register	*/
+	u32 u5clk;		/* UART 5 Clock Control Register	*/
+	u32 u6clk;		/* UART 6 Clock Control Register	*/
+	u32 irdaclk;		/* IrDA Clock Control Register		*/
+	u32 uartclk_ctrl;	/* UART Clock Control Register		*/
+	u32 dmaclk_ctrl;	/* DMA Clock Control Register		*/
+	u32 autoclk_ctrl;	/* Autoclock Control Register		*/
+};
+
+/* HCLK Divider Control Register bits */
+#define CLK_HCLK_DDRAM_HALF		(0x2 << 7)
+#define CLK_HCLK_DDRAM_NOMINAL		(0x1 << 7)
+#define CLK_HCLK_DDRAM_STOPPED		(0x0 << 7)
+#define CLK_HCLK_PERIPH_DIV_MASK	(0x1F << 2)
+#define CLK_HCLK_PERIPH_DIV(n)		((((n) - 1) & 0x1F) << 2)
+#define CLK_HCLK_ARM_PLL_DIV_MASK	(0x3 << 0)
+#define CLK_HCLK_ARM_PLL_DIV_4		(0x2 << 0)
+#define CLK_HCLK_ARM_PLL_DIV_2		(0x1 << 0)
+#define CLK_HCLK_ARM_PLL_DIV_1		(0x0 << 0)
+
+/* Power Control Register bits */
+#define CLK_PWR_HCLK_RUN_PERIPH		(1 << 10)
+#define CLK_PWR_EMC_SREFREQ		(1 << 9)
+#define CLK_PWR_EMC_SREFREQ_UPDATE	(1 << 8)
+#define CLK_PWR_SDRAM_SREFREQ		(1 << 7)
+#define CLK_PWR_HIGHCORE_LEVEL		(1 << 5)
+#define CLK_PWR_SYSCLKEN_LEVEL		(1 << 4)
+#define CLK_PWR_SYSCLKEN_CTRL		(1 << 3)
+#define CLK_PWR_NORMAL_RUN		(1 << 2)
+#define CLK_PWR_HIGHCORE_CTRL		(1 << 1)
+#define CLK_PWR_STOP_MODE		(1 << 0)
+
+/* SYSCLK Control Register bits */
+#define CLK_SYSCLK_PLL397		(1 << 1)
+#define CLK_SYSCLK_MUX			(1 << 0)
+
+/* HCLK PLL Control Register bits */
+#define CLK_HCLK_PLL_OPERATING		(1 << 16)
+#define CLK_HCLK_PLL_BYPASS		(1 << 15)
+#define CLK_HCLK_PLL_DIRECT		(1 << 14)
+#define CLK_HCLK_PLL_FEEDBACK		(1 << 13)
+#define CLK_HCLK_PLL_POSTDIV_MASK	(0x3 << 11)
+#define CLK_HCLK_PLL_POSTDIV_16		(0x3 << 11)
+#define CLK_HCLK_PLL_POSTDIV_8		(0x2 << 11)
+#define CLK_HCLK_PLL_POSTDIV_4		(0x1 << 11)
+#define CLK_HCLK_PLL_POSTDIV_2		(0x0 << 11)
+#define CLK_HCLK_PLL_PREDIV_MASK	(0x3 << 9)
+#define CLK_HCLK_PLL_PREDIV_4		(0x3 << 9)
+#define CLK_HCLK_PLL_PREDIV_3		(0x2 << 9)
+#define CLK_HCLK_PLL_PREDIV_2		(0x1 << 9)
+#define CLK_HCLK_PLL_PREDIV_1		(0x0 << 9)
+#define CLK_HCLK_PLL_FEEDBACK_DIV_MASK	(0xFF << 1)
+#define CLK_HCLK_PLL_FEEDBACK_DIV(n)	((((n) - 1) & 0xFF) << 1)
+#define CLK_HCLK_PLL_LOCKED		(1 << 0)
+
+/* Ethernet MAC Clock Control Register bits	*/
+#define CLK_MAC_RMII			(0x3 << 3)
+#define CLK_MAC_MII			(0x1 << 3)
+#define CLK_MAC_MASTER			(1 << 2)
+#define CLK_MAC_SLAVE			(1 << 1)
+#define CLK_MAC_REG			(1 << 0)
+
+/* Timer Clock Control1 Register bits */
+#define CLK_TIMCLK_MOTOR		(1 << 6)
+#define CLK_TIMCLK_TIMER3		(1 << 5)
+#define CLK_TIMCLK_TIMER2		(1 << 4)
+#define CLK_TIMCLK_TIMER1		(1 << 3)
+#define CLK_TIMCLK_TIMER0		(1 << 2)
+#define CLK_TIMCLK_TIMER5		(1 << 1)
+#define CLK_TIMCLK_TIMER4		(1 << 0)
+
+/* Timer Clock Control Register bits */
+#define CLK_TIMCLK_HSTIMER		(1 << 1)
+#define CLK_TIMCLK_WATCHDOG		(1 << 0)
+
+/* UART Clock Control Register bits */
+#define CLK_UART(n)			(1 << ((n) - 3))
+
+/* UARTn Clock Select Registers bits */
+#define CLK_UART_HCLK			(1 << 16)
+#define CLK_UART_X_DIV(n)		(((n) & 0xFF) << 8)
+#define CLK_UART_Y_DIV(n)		(((n) & 0xFF) << 0)
+
+/* DMA Clock Control Register bits */
+#define CLK_DMA_ENABLE			(1 << 0)
+
+unsigned int get_sys_clk_rate(void);
+unsigned int get_hclk_pll_rate(void);
+unsigned int get_hclk_clk_div(void);
+unsigned int get_hclk_clk_rate(void);
+unsigned int get_periph_clk_div(void);
+unsigned int get_periph_clk_rate(void);
+
+#endif /* _LPC32XX_CLK_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h
new file mode 100644
index 0000000000..41fcd323be
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -0,0 +1,76 @@
+/*
+ * Common definitions for LPC32XX board configurations
+ *
+ * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef _LPC32XX_CONFIG_H
+#define _LPC32XX_CONFIG_H
+
+/* Basic CPU architecture */
+#define CONFIG_ARM926EJS
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_NR_DRAM_BANKS_MAX	2
+
+/* 1KHz clock tick */
+#define CONFIG_SYS_HZ			1000
+
+/* UART configuration */
+#if (CONFIG_SYS_LPC32XX_UART >= 3) && (CONFIG_SYS_LPC32XX_UART <= 6)
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_CONS_INDEX		(CONFIG_SYS_LPC32XX_UART - 2)
+#elif	(CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
+	(CONFIG_SYS_LPC32XX_UART == 7)
+#define CONFIG_LPC32XX_HSUART
+#else
+#error "define CONFIG_SYS_LPC32XX_UART in the range from 1 to 7"
+#endif
+
+#if defined(CONFIG_SYS_NS16550_SERIAL)
+#define CONFIG_SYS_NS16550
+
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#define CONFIG_SYS_NS16550_COM1		UART3_BASE
+#define CONFIG_SYS_NS16550_COM2		UART4_BASE
+#define CONFIG_SYS_NS16550_COM3		UART5_BASE
+#define CONFIG_SYS_NS16550_COM4		UART6_BASE
+#endif
+
+#if defined(CONFIG_LPC32XX_HSUART)
+#if	CONFIG_SYS_LPC32XX_UART == 1
+#define HS_UART_BASE			HS_UART1_BASE
+#elif	CONFIG_SYS_LPC32XX_UART == 2
+#define HS_UART_BASE			HS_UART2_BASE
+#else	/* CONFIG_SYS_LPC32XX_UART == 7 */
+#define HS_UART_BASE			HS_UART7_BASE
+#endif
+#endif
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+		{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
+
+/* NOR Flash */
+#if defined(CONFIG_SYS_FLASH_CFI)
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_PROTECTION
+#endif
+
+#endif /* _LPC32XX_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h b/arch/arm/include/asm/arch-lpc32xx/cpu.h
new file mode 100644
index 0000000000..c5343c36e5
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/cpu.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef _LPC32XX_CPU_H
+#define _LPC32XX_CPU_H
+
+/* LPC32XX Memory map */
+
+/* AHB physical base addresses */
+#define SLC_NAND_BASE	0x20020000	/* SLC NAND Flash registers base    */
+#define SSP0_BASE	0x20084000	/* SSP0 registers base              */
+#define SD_CARD_BASE	0x20098000	/* SD card interface registers base */
+#define MLC_NAND_BASE	0x200A8000	/* MLC NAND Flash registers base    */
+#define DMA_BASE	0x31000000	/* DMA controller registers base    */
+#define USB_BASE	0x31020000	/* USB registers base               */
+#define LCD_BASE	0x31040000	/* LCD registers base               */
+#define ETHERNET_BASE	0x31060000	/* Ethernet registers base          */
+#define EMC_BASE	0x31080000	/* EMC configuration registers base */
+
+/* FAB peripherals base addresses */
+#define CLK_PM_BASE	0x40004000	/* System control registers base    */
+#define HS_UART1_BASE	0x40014000	/* High speed UART 1 registers base */
+#define HS_UART2_BASE	0x40018000	/* High speed UART 2 registers base */
+#define HS_UART7_BASE	0x4001C000	/* High speed UART 7 registers base */
+#define RTC_BASE	0x40024000	/* RTC registers base               */
+#define GPIO_BASE	0x40028000	/* GPIO registers base              */
+#define WDT_BASE	0x4003C000	/* Watchdog timer registers base    */
+#define TIMER0_BASE	0x40044000	/* Timer0 registers base            */
+#define TIMER1_BASE	0x4004C000	/* Timer1 registers base            */
+#define UART_CTRL_BASE	0x40054000	/* UART control regsisters base     */
+
+/* APB peripherals base addresses */
+#define UART3_BASE	0x40080000	/* UART 3 registers base            */
+#define UART4_BASE	0x40088000	/* UART 4 registers base            */
+#define UART5_BASE	0x40090000	/* UART 5 registers base            */
+#define UART6_BASE	0x40098000	/* UART 6 registers base            */
+
+/* External SDRAM Memory Bank base addresses */
+#define EMC_DYCS0_BASE	0x80000000	/* SDRAM DYCS0 base address         */
+#define EMC_DYCS1_BASE	0xA0000000	/* SDRAM DYCS1 base address         */
+
+/* External Static Memory Bank base addresses */
+#define EMC_CS0_BASE	0xE0000000
+#define EMC_CS1_BASE	0xE1000000
+#define EMC_CS2_BASE	0xE2000000
+#define EMC_CS3_BASE	0xE3000000
+
+#endif /* _LPC32XX_CPU_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/emc.h b/arch/arm/include/asm/arch-lpc32xx/emc.h
new file mode 100644
index 0000000000..feb03bd069
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/emc.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef _LPC32XX_EMC_H
+#define _LPC32XX_EMC_H
+
+#include <asm/types.h>
+
+/* EMC Registers */
+struct emc_regs {
+	u32 ctrl;		/* Controls operation of the EMC             */
+	u32 status;		/* Provides EMC status information           */
+	u32 config;		/* Configures operation of the EMC           */
+	u32 reserved0[5];
+	u32 control;		/* Controls dyn memory operation             */
+	u32 refresh;		/* Configures dyn memory refresh operation   */
+	u32 read_config;	/* Configures the dyn memory read strategy   */
+	u32 reserved1;
+	u32 t_rp;		/* Precharge command period                  */
+	u32 t_ras;		/* Active to precharge command period        */
+	u32 t_srex;		/* Self-refresh exit time                    */
+	u32 reserved2[2];
+	u32 t_wr;		/* Write recovery time                       */
+	u32 t_rc;		/* Active to active command period           */
+	u32 t_rfc;		/* Auto-refresh period                       */
+	u32 t_xsr;		/* Exit self-refresh to active command time  */
+	u32 t_rrd;		/* Active bank A to active bank B latency    */
+	u32 t_mrd;		/* Load mode register to active command time */
+	u32 t_cdlr;		/* Last data in to read command time         */
+	u32 reserved3[8];
+	u32 extended_wait;	/* time for static memory rd/wr transfers    */
+	u32 reserved4[31];
+	u32 config0;		/* Configuration information for the SDRAM   */
+	u32 rascas0;		/* RAS and CAS latencies for the SDRAM       */
+	u32 reserved5[6];
+	u32 config1;		/* Configuration information for the SDRAM   */
+	u32 rascas1;		/* RAS and CAS latencies for the SDRAM       */
+	u32 reserved6[54];
+	struct emc_stat_t {
+		u32 config;	/* Static memory configuration               */
+		u32 waitwen;	/* Delay from chip select to write enable    */
+		u32 waitoen;	/* Delay to output enable                    */
+		u32 waitrd;	/* Delay to a read access                    */
+		u32 waitpage;	/* Delay for async page mode read            */
+		u32 waitwr;	/* Delay to a write access                   */
+		u32 waitturn;	/* Number of bus turnaround cycles           */
+		u32 reserved;
+	} stat[4];
+	u32 reserved7[96];
+	struct emc_ahb_t {
+		u32 control;	/* Control register for AHB                  */
+		u32 status;	/* Status register for AHB                   */
+		u32 timeout;	/* Timeout register for AHB                  */
+		u32 reserved[5];
+	} ahb[5];
+};
+
+/* Static Memory Configuration Register bits */
+#define EMC_STAT_CONFIG_WP		(1 << 20)
+#define EMC_STAT_CONFIG_EW		(1 << 8)
+#define EMC_STAT_CONFIG_PB		(1 << 7)
+#define EMC_STAT_CONFIG_PC		(1 << 6)
+#define EMC_STAT_CONFIG_PM		(1 << 3)
+#define EMC_STAT_CONFIG_32BIT		(2 << 0)
+#define EMC_STAT_CONFIG_16BIT		(1 << 0)
+#define EMC_STAT_CONFIG_8BIT		(0 << 0)
+
+/* Static Memory Delay Registers */
+#define EMC_STAT_WAITWEN(n)		(((n) - 1) & 0x0F)
+#define EMC_STAT_WAITOEN(n)		(((n) - 1) & 0x0F)
+#define EMC_STAT_WAITRD(n)		(((n) - 1) & 0x1F)
+#define EMC_STAT_WAITPAGE(n)		(((n) - 1) & 0x1F)
+#define EMC_STAT_WAITWR(n)		(((n) - 2) & 0x1F)
+#define EMC_STAT_WAITTURN(n)		(((n) - 1) & 0x0F)
+
+#endif /* _LPC32XX_EMC_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
new file mode 100644
index 0000000000..b2cbfcd66d
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef _LPC32XX_SYS_PROTO_H
+#define _LPC32XX_SYS_PROTO_H
+
+void lpc32xx_uart_init(unsigned int uart_id);
+
+#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/timer.h b/arch/arm/include/asm/arch-lpc32xx/timer.h
new file mode 100644
index 0000000000..7d637637ef
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/timer.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef _LPC32XX_TIMER_H
+#define _LPC32XX_TIMER_H
+
+#include <asm/types.h>
+
+/* Timer/Counter Registers */
+struct timer_regs {
+	u32 ir;			/* Interrupt Register		*/
+	u32 tcr;		/* Timer Control Register	*/
+	u32 tc;			/* Timer Counter		*/
+	u32 pr;			/* Prescale Register		*/
+	u32 pc;			/* Prescale Counter		*/
+	u32 mcr;		/* Match Control Register	*/
+	u32 mr[4];		/* Match Registers		*/
+	u32 ccr;		/* Capture Control Register	*/
+	u32 cr[4];		/* Capture Registers		*/
+	u32 emr;		/* External Match Register	*/
+	u32 reserved[12];
+	u32 ctcr;		/* Count Control Register	*/
+};
+
+/* Timer/Counter Interrupt Register bits */
+#define TIMER_IR_CR(n)			(1 << ((n) + 4))
+#define TIMER_IR_MR(n)			(1 << (n))
+
+/* Timer/Counter Timer Control Register bits */
+#define TIMER_TCR_COUNTER_RESET		(1 << 1)
+#define TIMER_TCR_COUNTER_ENABLE	(1 << 0)
+#define TIMER_TCR_COUNTER_DISABLE	(0 << 0)
+
+/* Timer/Counter Match Control Register bits */
+#define TIMER_MCR_STOP(n)		(1 << (3 * (n) + 2))
+#define TIMER_MCR_RESET(n)		(1 << (3 * (n) + 1))
+#define TIMER_MCR_INTERRUPT(n)		(1 << (3 * (n)))
+
+/* Timer/Counter Capture Control Register bits */
+#define TIMER_CCR_INTERRUPT(n)		(1 << (3 * (n) + 2))
+#define TIMER_CCR_FALLING_EDGE(n)	(1 << (3 * (n) + 1))
+#define TIMER_CCR_RISING_EDGE(n)	(1 << (3 * (n)))
+
+/* Timer/Counter External Match Register bits */
+#define TIMER_EMR_EMC_TOGGLE(n)		(0x3 << (2 * (n) + 4))
+#define TIMER_EMR_EMC_SET(n)		(0x2 << (2 * (n) + 4))
+#define TIMER_EMR_EMC_CLEAR(n)		(0x1 << (2 * (n) + 4))
+#define TIMER_EMR_EMC_NOTHING(n)	(0x0 << (2 * (n) + 4))
+#define TIMER_EMR_EM(n)			(1 << (n))
+
+/* Timer/Counter Count Control Register bits */
+#define TIMER_CTCR_INPUT(n)		((n) << 2)
+#define TIMER_CTCR_MODE_COUNTER_BOTH	(0x3 << 0)
+#define TIMER_CTCR_MODE_COUNTER_FALLING	(0x2 << 0)
+#define TIMER_CTCR_MODE_COUNTER_RISING	(0x1 << 0)
+#define TIMER_CTCR_MODE_TIMER		(0x0 << 0)
+
+#endif /* _LPC32XX_TIMER_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/uart.h b/arch/arm/include/asm/arch-lpc32xx/uart.h
new file mode 100644
index 0000000000..ec12893236
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/uart.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef _LPC32XX_UART_H
+#define _LPC32XX_UART_H
+
+#include <asm/types.h>
+
+/* 14-clock UART Registers */
+struct hsuart_regs {
+	union {
+		u32 rx;		/* Receiver FIFO		*/
+		u32 tx;		/* Transmitter FIFO		*/
+	};
+	u32 level;		/* FIFO Level Register		*/
+	u32 iir;		/* Interrupt ID Register	*/
+	u32 ctrl;		/* Control Register		*/
+	u32 rate;		/* Rate Control Register	*/
+};
+
+/* 14-clock UART Receiver FIFO Register bits */
+#define HSUART_RX_BREAK			(1 << 10)
+#define HSUART_RX_ERROR			(1 << 9)
+#define HSUART_RX_EMPTY			(1 << 8)
+#define HSUART_RX_DATA			(0xff << 0)
+
+/* 14-clock UART Level Register bits */
+#define HSUART_LEVEL_TX			(0xff << 8)
+#define HSUART_LEVEL_RX			(0xff << 0)
+
+/* 14-clock UART Interrupt Identification Register bits */
+#define HSUART_IIR_TX_INT_SET		(1 << 6)
+#define HSUART_IIR_RX_OE		(1 << 5)
+#define HSUART_IIR_BRK			(1 << 4)
+#define HSUART_IIR_FE			(1 << 3)
+#define HSUART_IIR_RX_TIMEOUT		(1 << 2)
+#define HSUART_IIR_RX_TRIG		(1 << 1)
+#define HSUART_IIR_TX			(1 << 0)
+
+/* 14-clock UART Control Register bits */
+#define HSUART_CTRL_HRTS_INV		(1 << 21)
+#define HSUART_CTRL_HRTS_TRIG_48	(0x3 << 19)
+#define HSUART_CTRL_HRTS_TRIG_32	(0x2 << 19)
+#define HSUART_CTRL_HRTS_TRIG_16	(0x1 << 19)
+#define HSUART_CTRL_HRTS_TRIG_8		(0x0 << 19)
+#define HSUART_CTRL_HRTS_EN		(1 << 18)
+#define HSUART_CTRL_TMO_16		(0x3 << 16)
+#define HSUART_CTRL_TMO_8		(0x2 << 16)
+#define HSUART_CTRL_TMO_4		(0x1 << 16)
+#define HSUART_CTRL_TMO_DISABLED	(0x0 << 16)
+#define HSUART_CTRL_HCTS_INV		(1 << 15)
+#define HSUART_CTRL_HCTS_EN		(1 << 14)
+#define HSUART_CTRL_HSU_OFFSET(n)	((n) << 9)
+#define HSUART_CTRL_HSU_BREAK		(1 << 8)
+#define HSUART_CTRL_HSU_ERR_INT_EN	(1 << 7)
+#define HSUART_CTRL_HSU_RX_INT_EN	(1 << 6)
+#define HSUART_CTRL_HSU_TX_INT_EN	(1 << 5)
+#define HSUART_CTRL_HSU_RX_TRIG_48	(0x5 << 2)
+#define HSUART_CTRL_HSU_RX_TRIG_32	(0x4 << 2)
+#define HSUART_CTRL_HSU_RX_TRIG_16	(0x3 << 2)
+#define HSUART_CTRL_HSU_RX_TRIG_8	(0x2 << 2)
+#define HSUART_CTRL_HSU_RX_TRIG_4	(0x1 << 2)
+#define HSUART_CTRL_HSU_RX_TRIG_1	(0x0 << 2)
+#define HSUART_CTRL_HSU_TX_TRIG_16	(0x3 << 0)
+#define HSUART_CTRL_HSU_TX_TRIG_8	(0x2 << 0)
+#define HSUART_CTRL_HSU_TX_TRIG_4	(0x1 << 0)
+#define HSUART_CTRL_HSU_TX_TRIG_0	(0x0 << 0)
+
+/* UART Control Registers */
+struct uart_ctrl_regs {
+	u32 ctrl;		/* Control Register		*/
+	u32 clkmode;		/* Clock Mode Register		*/
+	u32 loop;		/* Loopback Control Register	*/
+};
+
+/* UART Control Register bits */
+#define UART_CTRL_UART3_MD_CTRL		(1 << 11)
+#define UART_CTRL_HDPX_INV		(1 << 10)
+#define UART_CTRL_HDPX_EN		(1 << 9)
+#define UART_CTRL_UART6_IRDA		(1 << 5)
+#define UART_CTRL_IR_TX6_INV		(1 << 4)
+#define UART_CTRL_IR_RX6_INV		(1 << 3)
+#define UART_CTRL_IR_RX_LENGTH		(1 << 2)
+#define UART_CTRL_IR_TX_LENGTH		(1 << 1)
+#define UART_CTRL_UART5_USB_MODE	(1 << 0)
+
+/* UART Clock Mode Register bits */
+#define UART_CLKMODE_STATX(n)		(1 << ((n) + 16))
+#define UART_CLKMODE_STAT		(1 << 14)
+#define UART_CLKMODE_MASK(n)		(0x3 << (2 * (n) - 2))
+#define UART_CLKMODE_AUTO(n)		(0x2 << (2 * (n) - 2))
+#define UART_CLKMODE_ON(n)		(0x1 << (2 * (n) - 2))
+#define UART_CLKMODE_OFF(n)		(0x0 << (2 * (n) - 2))
+
+/* UART Loopback Control Register bits */
+#define UART_LOOPBACK(n)		(1 << ((n) - 1))
+
+#endif /* _LPC32XX_UART_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/wdt.h b/arch/arm/include/asm/arch-lpc32xx/wdt.h
new file mode 100644
index 0000000000..133f29fc4b
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/wdt.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef _LPC32XX_WDT_H
+#define _LPC32XX_WDT_H
+
+#include <asm/types.h>
+
+/* Watchdog Timer Registers */
+struct wdt_regs {
+	u32 isr;		/* Interrupt Status Register		*/
+	u32 ctrl;		/* Control Register			*/
+	u32 counter;		/* Counter Value Register		*/
+	u32 mctrl;		/* Match Control Register		*/
+	u32 match0;		/* Match 0 Register			*/
+	u32 emr;		/* External Match Control Register	*/
+	u32 pulse;		/* Reset Pulse Length Register		*/
+	u32 res;		/* Reset Source Register		*/
+};
+
+/* Watchdog Timer Control Register bits */
+#define WDTIM_CTRL_PAUSE_EN		(1 << 2)
+#define WDTIM_CTRL_RESET_COUNT		(1 << 1)
+#define WDTIM_CTRL_COUNT_ENAB		(1 << 0)
+
+/* Watchdog Timer Match Control Register bits */
+#define WDTIM_MCTRL_RESFRC2		(1 << 6)
+#define WDTIM_MCTRL_RESFRC1		(1 << 5)
+#define WDTIM_MCTRL_M_RES2		(1 << 4)
+#define WDTIM_MCTRL_M_RES1		(1 << 3)
+#define WDTIM_MCTRL_STOP_COUNT0		(1 << 2)
+#define WDTIM_MCTRL_RESET_COUNT0	(1 << 1)
+#define WDTIM_MCTRL_MR0_INT		(1 << 0)
+
+#endif /* _LPC32XX_WDT_H */
diff --git a/arch/arm/include/asm/arch-mx25/clock.h b/arch/arm/include/asm/arch-mx25/clock.h
index c59f588570..0f47eaf053 100644
--- a/arch/arm/include/asm/arch-mx25/clock.h
+++ b/arch/arm/include/asm/arch-mx25/clock.h
@@ -26,11 +26,34 @@
 #ifndef __ASM_ARCH_CLOCK_H
 #define __ASM_ARCH_CLOCK_H
 
+enum mxc_clock {
+	MXC_CSI_CLK,
+	MXC_EPIT_CLK,
+	MXC_ESAI_CLK,
+	MXC_ESDHC1_CLK,
+	MXC_ESDHC2_CLK,
+	MXC_GPT_CLK,
+	MXC_I2C_CLK,
+	MXC_LCDC_CLK,
+	MXC_NFC_CLK,
+	MXC_OWIRE_CLK,
+	MXC_PWM_CLK,
+	MXC_SIM1_CLK,
+	MXC_SIM2_CLK,
+	MXC_SSI1_CLK,
+	MXC_SSI2_CLK,
+	MXC_UART_CLK,
+	MXC_ARM_CLK,
+	MXC_FEC_CLK,
+	MXC_CLK_NUM
+};
+
 ulong imx_get_perclk(int clk);
 ulong imx_get_ahbclk(void);
 
 #define imx_get_uartclk() imx_get_perclk(15)
 #define imx_get_fecclk() (imx_get_ahbclk()/2)
 
+unsigned int mxc_get_clock(enum mxc_clock clk);
 
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h
index 7f9449b2d0..cf925d70d5 100644
--- a/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -34,6 +34,9 @@
 #define _IMX_REGS_H
 
 #ifndef __ASSEMBLY__
+
+#include <asm/types.h>
+
 #ifdef CONFIG_FEC_MXC
 extern void mx25_fec_init_pins(void);
 #endif
diff --git a/arch/arm/include/asm/arch-mx28/imx-regs.h b/arch/arm/include/asm/arch-mx28/imx-regs.h
index f9e6c535f2..37d0a93768 100644
--- a/arch/arm/include/asm/arch-mx28/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx28/imx-regs.h
@@ -30,6 +30,8 @@
 #include <asm/arch/regs-digctl.h>
 #include <asm/arch/regs-gpmi.h>
 #include <asm/arch/regs-i2c.h>
+#include <asm/arch/regs-lcdif.h>
+#include <asm/arch/regs-lradc.h>
 #include <asm/arch/regs-ocotp.h>
 #include <asm/arch/regs-pinctrl.h>
 #include <asm/arch/regs-power.h>
diff --git a/arch/arm/include/asm/arch-mx28/regs-lcdif.h b/arch/arm/include/asm/arch-mx28/regs-lcdif.h
new file mode 100644
index 0000000000..cb47e41fdc
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/regs-lcdif.h
@@ -0,0 +1,212 @@
+/*
+ * Freescale i.MX28 LCDIF Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#ifndef __MX28_REGS_LCDIF_H__
+#define __MX28_REGS_LCDIF_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mx28_lcdif_regs {
+	mx28_reg_32(hw_lcdif_ctrl)		/* 0x00 */
+	mx28_reg_32(hw_lcdif_ctrl1)		/* 0x10 */
+	mx28_reg_32(hw_lcdif_ctrl2)		/* 0x20 */
+	mx28_reg_32(hw_lcdif_transfer_count)	/* 0x30 */
+	mx28_reg_32(hw_lcdif_cur_buf)		/* 0x40 */
+	mx28_reg_32(hw_lcdif_next_buf)		/* 0x50 */
+	mx28_reg_32(hw_lcdif_timing)		/* 0x60 */
+	mx28_reg_32(hw_lcdif_vdctrl0)		/* 0x70 */
+	mx28_reg_32(hw_lcdif_vdctrl1)		/* 0x80 */
+	mx28_reg_32(hw_lcdif_vdctrl2)		/* 0x90 */
+	mx28_reg_32(hw_lcdif_vdctrl3)		/* 0xa0 */
+	mx28_reg_32(hw_lcdif_vdctrl4)		/* 0xb0 */
+	mx28_reg_32(hw_lcdif_dvictrl0)		/* 0xc0 */
+	mx28_reg_32(hw_lcdif_dvictrl1)		/* 0xd0 */
+	mx28_reg_32(hw_lcdif_dvictrl2)		/* 0xe0 */
+	mx28_reg_32(hw_lcdif_dvictrl3)		/* 0xf0 */
+	mx28_reg_32(hw_lcdif_dvictrl4)		/* 0x100 */
+	mx28_reg_32(hw_lcdif_csc_coeffctrl0)	/* 0x110 */
+	mx28_reg_32(hw_lcdif_csc_coeffctrl1)	/* 0x120 */
+	mx28_reg_32(hw_lcdif_csc_coeffctrl2)	/* 0x130 */
+	mx28_reg_32(hw_lcdif_csc_coeffctrl3)	/* 0x140 */
+	mx28_reg_32(hw_lcdif_csc_coeffctrl4)	/* 0x150 */
+	mx28_reg_32(hw_lcdif_csc_offset)	/* 0x160 */
+	mx28_reg_32(hw_lcdif_csc_limit)		/* 0x170 */
+	mx28_reg_32(hw_lcdif_data)		/* 0x180 */
+	mx28_reg_32(hw_lcdif_bm_error_stat)	/* 0x190 */
+	mx28_reg_32(hw_lcdif_crc_stat)		/* 0x1a0 */
+	mx28_reg_32(hw_lcdif_lcdif_stat)	/* 0x1b0 */
+	mx28_reg_32(hw_lcdif_version)		/* 0x1c0 */
+	mx28_reg_32(hw_lcdif_debug0)		/* 0x1d0 */
+	mx28_reg_32(hw_lcdif_debug1)		/* 0x1e0 */
+	mx28_reg_32(hw_lcdif_debug2)		/* 0x1f0 */
+};
+#endif
+
+#define	LCDIF_CTRL_SFTRST					(1 << 31)
+#define	LCDIF_CTRL_CLKGATE					(1 << 30)
+#define	LCDIF_CTRL_YCBCR422_INPUT				(1 << 29)
+#define	LCDIF_CTRL_READ_WRITEB					(1 << 28)
+#define	LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE				(1 << 27)
+#define	LCDIF_CTRL_DATA_SHIFT_DIR				(1 << 26)
+#define	LCDIF_CTRL_SHIFT_NUM_BITS_MASK				(0x1f << 21)
+#define	LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET			21
+#define	LCDIF_CTRL_DVI_MODE					(1 << 20)
+#define	LCDIF_CTRL_BYPASS_COUNT					(1 << 19)
+#define	LCDIF_CTRL_VSYNC_MODE					(1 << 18)
+#define	LCDIF_CTRL_DOTCLK_MODE					(1 << 17)
+#define	LCDIF_CTRL_DATA_SELECT					(1 << 16)
+#define	LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK			(0x3 << 14)
+#define	LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET			14
+#define	LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK			(0x3 << 12)
+#define	LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET			12
+#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK			(0x3 << 10)
+#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET			10
+#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT			(0 << 10)
+#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT			(1 << 10)
+#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT			(2 << 10)
+#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT			(3 << 10)
+#define	LCDIF_CTRL_WORD_LENGTH_MASK				(0x3 << 8)
+#define	LCDIF_CTRL_WORD_LENGTH_OFFSET				8
+#define	LCDIF_CTRL_WORD_LENGTH_16BIT				(0 << 8)
+#define	LCDIF_CTRL_WORD_LENGTH_8BIT				(1 << 8)
+#define	LCDIF_CTRL_WORD_LENGTH_18BIT				(2 << 8)
+#define	LCDIF_CTRL_WORD_LENGTH_24BIT				(3 << 8)
+#define	LCDIF_CTRL_RGB_TO_YCBCR422_CSC				(1 << 7)
+#define	LCDIF_CTRL_LCDIF_MASTER					(1 << 5)
+#define	LCDIF_CTRL_DATA_FORMAT_16_BIT				(1 << 3)
+#define	LCDIF_CTRL_DATA_FORMAT_18_BIT				(1 << 2)
+#define	LCDIF_CTRL_DATA_FORMAT_24_BIT				(1 << 1)
+#define	LCDIF_CTRL_RUN						(1 << 0)
+
+#define	LCDIF_CTRL1_COMBINE_MPU_WR_STRB				(1 << 27)
+#define	LCDIF_CTRL1_BM_ERROR_IRQ_EN				(1 << 26)
+#define	LCDIF_CTRL1_BM_ERROR_IRQ				(1 << 25)
+#define	LCDIF_CTRL1_RECOVER_ON_UNDERFLOW			(1 << 24)
+#define	LCDIF_CTRL1_INTERLACE_FIELDS				(1 << 23)
+#define	LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD		(1 << 22)
+#define	LCDIF_CTRL1_FIFO_CLEAR					(1 << 21)
+#define	LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS			(1 << 20)
+#define	LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK			(0xf << 16)
+#define	LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET			16
+#define	LCDIF_CTRL1_OVERFLOW_IRQ_EN				(1 << 15)
+#define	LCDIF_CTRL1_UNDERFLOW_IRQ_EN				(1 << 14)
+#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN			(1 << 13)
+#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN				(1 << 12)
+#define	LCDIF_CTRL1_OVERFLOW_IRQ				(1 << 11)
+#define	LCDIF_CTRL1_UNDERFLOW_IRQ				(1 << 10)
+#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ				(1 << 9)
+#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ				(1 << 8)
+#define	LCDIF_CTRL1_BUSY_ENABLE					(1 << 2)
+#define	LCDIF_CTRL1_MODE86					(1 << 1)
+#define	LCDIF_CTRL1_RESET					(1 << 0)
+
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_MASK			(0x7 << 21)
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET			21
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1			(0x0 << 21)
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2			(0x1 << 21)
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4			(0x2 << 21)
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8			(0x3 << 21)
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16			(0x4 << 21)
+#define	LCDIF_CTRL2_BURST_LEN_8					(1 << 20)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_MASK			(0x7 << 16)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET			16
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_RGB			(0x0 << 16)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_RBG			(0x1 << 16)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_GBR			(0x2 << 16)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_GRB			(0x3 << 16)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_BRG			(0x4 << 16)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_BGR			(0x5 << 16)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK			(0x7 << 12)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET			12
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB			(0x0 << 12)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG			(0x1 << 12)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR			(0x2 << 12)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB			(0x3 << 12)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG			(0x4 << 12)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR			(0x5 << 12)
+#define	LCDIF_CTRL2_READ_PACK_DIR				(1 << 10)
+#define	LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT		(1 << 9)
+#define	LCDIF_CTRL2_READ_MODE_6_BIT_INPUT			(1 << 8)
+#define	LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK		(0x7 << 4)
+#define	LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET	4
+#define	LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK			(0x7 << 1)
+#define	LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET			1
+
+#define	LCDIF_TRANSFER_COUNT_V_COUNT_MASK			(0xffff << 16)
+#define	LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET			16
+#define	LCDIF_TRANSFER_COUNT_H_COUNT_MASK			(0xffff << 0)
+#define	LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET			0
+
+#define	LCDIF_CUR_BUF_ADDR_MASK					0xffffffff
+#define	LCDIF_CUR_BUF_ADDR_OFFSET				0
+
+#define	LCDIF_NEXT_BUF_ADDR_MASK				0xffffffff
+#define	LCDIF_NEXT_BUF_ADDR_OFFSET				0
+
+#define	LCDIF_TIMING_CMD_HOLD_MASK				(0xff << 24)
+#define	LCDIF_TIMING_CMD_HOLD_OFFSET				24
+#define	LCDIF_TIMING_CMD_SETUP_MASK				(0xff << 16)
+#define	LCDIF_TIMING_CMD_SETUP_OFFSET				16
+#define	LCDIF_TIMING_DATA_HOLD_MASK				(0xff << 8)
+#define	LCDIF_TIMING_DATA_HOLD_OFFSET				8
+#define	LCDIF_TIMING_DATA_SETUP_MASK				(0xff << 0)
+#define	LCDIF_TIMING_DATA_SETUP_OFFSET				0
+
+#define	LCDIF_VDCTRL0_VSYNC_OEB					(1 << 29)
+#define	LCDIF_VDCTRL0_ENABLE_PRESENT				(1 << 28)
+#define	LCDIF_VDCTRL0_VSYNC_POL					(1 << 27)
+#define	LCDIF_VDCTRL0_HSYNC_POL					(1 << 26)
+#define	LCDIF_VDCTRL0_DOTCLK_POL				(1 << 25)
+#define	LCDIF_VDCTRL0_ENABLE_POL				(1 << 24)
+#define	LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT				(1 << 21)
+#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT			(1 << 20)
+#define	LCDIF_VDCTRL0_HALF_LINE					(1 << 19)
+#define	LCDIF_VDCTRL0_HALF_LINE_MODE				(1 << 18)
+#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK			0x3ffff
+#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET			0
+
+#define	LCDIF_VDCTRL1_VSYNC_PERIOD_MASK				0xffffffff
+#define	LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET			0
+
+#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK			(0x3fff << 18)
+#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET			18
+#define	LCDIF_VDCTRL2_HSYNC_PERIOD_MASK				0x3ffff
+#define	LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET			0
+
+#define	LCDIF_VDCTRL3_MUX_SYNC_SIGNALS				(1 << 29)
+#define	LCDIF_VDCTRL3_VSYNC_ONLY				(1 << 28)
+#define	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK			(0xfff << 16)
+#define	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET		16
+#define	LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK			(0xffff << 0)
+#define	LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET			0
+
+#define	LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK			(0x7 << 29)
+#define	LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET			29
+#define	LCDIF_VDCTRL4_SYNC_SIGNALS_ON				(1 << 18)
+#define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK		0x3ffff
+#define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET		0
+
+#endif /* __MX28_REGS_LCDIF_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/regs-lradc.h b/arch/arm/include/asm/arch-mx28/regs-lradc.h
new file mode 100644
index 0000000000..16e2bbf4cb
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx28/regs-lradc.h
@@ -0,0 +1,400 @@
+/*
+ * Freescale i.MX28 LRADC Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#ifndef __MX28_REGS_LRADC_H__
+#define __MX28_REGS_LRADC_H__
+
+#include <asm/arch/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mx28_lradc_regs {
+	mx28_reg_32(hw_lradc_ctrl0);
+	mx28_reg_32(hw_lradc_ctrl1);
+	mx28_reg_32(hw_lradc_ctrl2);
+	mx28_reg_32(hw_lradc_ctrl3);
+	mx28_reg_32(hw_lradc_status);
+	mx28_reg_32(hw_lradc_ch0);
+	mx28_reg_32(hw_lradc_ch1);
+	mx28_reg_32(hw_lradc_ch2);
+	mx28_reg_32(hw_lradc_ch3);
+	mx28_reg_32(hw_lradc_ch4);
+	mx28_reg_32(hw_lradc_ch5);
+	mx28_reg_32(hw_lradc_ch6);
+	mx28_reg_32(hw_lradc_ch7);
+	mx28_reg_32(hw_lradc_delay0);
+	mx28_reg_32(hw_lradc_delay1);
+	mx28_reg_32(hw_lradc_delay2);
+	mx28_reg_32(hw_lradc_delay3);
+	mx28_reg_32(hw_lradc_debug0);
+	mx28_reg_32(hw_lradc_debug1);
+	mx28_reg_32(hw_lradc_conversion);
+	mx28_reg_32(hw_lradc_ctrl4);
+	mx28_reg_32(hw_lradc_treshold0);
+	mx28_reg_32(hw_lradc_treshold1);
+	mx28_reg_32(hw_lradc_version);
+};
+#endif
+
+#define	LRADC_CTRL0_SFTRST					(1 << 31)
+#define	LRADC_CTRL0_CLKGATE					(1 << 30)
+#define	LRADC_CTRL0_ONCHIP_GROUNDREF				(1 << 26)
+#define	LRADC_CTRL0_BUTTON1_DETECT_ENABLE			(1 << 25)
+#define	LRADC_CTRL0_BUTTON0_DETECT_ENABLE			(1 << 24)
+#define	LRADC_CTRL0_TOUCH_DETECT_ENABLE				(1 << 23)
+#define	LRADC_CTRL0_TOUCH_SCREEN_TYPE				(1 << 22)
+#define	LRADC_CTRL0_YNLRSW					(1 << 21)
+#define	LRADC_CTRL0_YPLLSW_MASK					(0x3 << 19)
+#define	LRADC_CTRL0_YPLLSW_OFFSET				19
+#define	LRADC_CTRL0_XNURSW_MASK					(0x3 << 17)
+#define	LRADC_CTRL0_XNURSW_OFFSET				17
+#define	LRADC_CTRL0_XPULSW					(1 << 16)
+#define	LRADC_CTRL0_SCHEDULE_MASK				0xff
+#define	LRADC_CTRL0_SCHEDULE_OFFSET				0
+
+#define	LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN			(1 << 28)
+#define	LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN			(1 << 27)
+#define	LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN			(1 << 26)
+#define	LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN			(1 << 25)
+#define	LRADC_CTRL1_TOUCH_DETECT_IRQ_EN				(1 << 24)
+#define	LRADC_CTRL1_LRADC7_IRQ_EN				(1 << 23)
+#define	LRADC_CTRL1_LRADC6_IRQ_EN				(1 << 22)
+#define	LRADC_CTRL1_LRADC5_IRQ_EN				(1 << 21)
+#define	LRADC_CTRL1_LRADC4_IRQ_EN				(1 << 20)
+#define	LRADC_CTRL1_LRADC3_IRQ_EN				(1 << 19)
+#define	LRADC_CTRL1_LRADC2_IRQ_EN				(1 << 18)
+#define	LRADC_CTRL1_LRADC1_IRQ_EN				(1 << 17)
+#define	LRADC_CTRL1_LRADC0_IRQ_EN				(1 << 16)
+#define	LRADC_CTRL1_BUTTON1_DETECT_IRQ				(1 << 12)
+#define	LRADC_CTRL1_BUTTON0_DETECT_IRQ				(1 << 11)
+#define	LRADC_CTRL1_THRESHOLD1_DETECT_IRQ			(1 << 10)
+#define	LRADC_CTRL1_THRESHOLD0_DETECT_IRQ			(1 << 9)
+#define	LRADC_CTRL1_TOUCH_DETECT_IRQ				(1 << 8)
+#define	LRADC_CTRL1_LRADC7_IRQ					(1 << 7)
+#define	LRADC_CTRL1_LRADC6_IRQ					(1 << 6)
+#define	LRADC_CTRL1_LRADC5_IRQ					(1 << 5)
+#define	LRADC_CTRL1_LRADC4_IRQ					(1 << 4)
+#define	LRADC_CTRL1_LRADC3_IRQ					(1 << 3)
+#define	LRADC_CTRL1_LRADC2_IRQ					(1 << 2)
+#define	LRADC_CTRL1_LRADC1_IRQ					(1 << 1)
+#define	LRADC_CTRL1_LRADC0_IRQ					(1 << 0)
+
+#define	LRADC_CTRL2_DIVIDE_BY_TWO_MASK				(0xff << 24)
+#define	LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET			24
+#define	LRADC_CTRL2_TEMPSENSE_PWD				(1 << 15)
+#define	LRADC_CTRL2_VTHSENSE_MASK				(0x3 << 13)
+#define	LRADC_CTRL2_VTHSENSE_OFFSET				13
+#define	LRADC_CTRL2_DISABLE_MUXAMP_BYPASS			(1 << 12)
+#define	LRADC_CTRL2_TEMP_SENSOR_IENABLE1			(1 << 9)
+#define	LRADC_CTRL2_TEMP_SENSOR_IENABLE0			(1 << 8)
+#define	LRADC_CTRL2_TEMP_ISRC1_MASK				(0xf << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_OFFSET				4
+#define	LRADC_CTRL2_TEMP_ISRC1_300				(0xf << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_280				(0xe << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_260				(0xd << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_240				(0xc << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_220				(0xb << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_200				(0xa << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_180				(0x9 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_160				(0x8 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_140				(0x7 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_120				(0x6 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_100				(0x5 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_80				(0x4 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_60				(0x3 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_40				(0x2 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_20				(0x1 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_ZERO				(0x0 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC0_MASK				(0xf << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_OFFSET				0
+#define	LRADC_CTRL2_TEMP_ISRC0_300				(0xf << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_280				(0xe << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_260				(0xd << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_240				(0xc << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_220				(0xb << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_200				(0xa << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_180				(0x9 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_160				(0x8 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_140				(0x7 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_120				(0x6 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_100				(0x5 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_80				(0x4 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_60				(0x3 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_40				(0x2 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_20				(0x1 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_ZERO				(0x0 << 0)
+
+#define	LRADC_CTRL3_DISCARD_MASK				(0x3 << 24)
+#define	LRADC_CTRL3_DISCARD_OFFSET				24
+#define	LRADC_CTRL3_DISCARD_1_SAMPLE				(0x1 << 24)
+#define	LRADC_CTRL3_DISCARD_2_SAMPLES				(0x2 << 24)
+#define	LRADC_CTRL3_DISCARD_3_SAMPLES				(0x3 << 24)
+#define	LRADC_CTRL3_FORCE_ANALOG_PWUP				(1 << 23)
+#define	LRADC_CTRL3_FORCE_ANALOG_PWDN				(1 << 22)
+#define	LRADC_CTRL3_CYCLE_TIME_MASK				(0x3 << 8)
+#define	LRADC_CTRL3_CYCLE_TIME_OFFSET				8
+#define	LRADC_CTRL3_CYCLE_TIME_6MHZ				(0x0 << 8)
+#define	LRADC_CTRL3_CYCLE_TIME_4MHZ				(0x1 << 8)
+#define	LRADC_CTRL3_CYCLE_TIME_3MHZ				(0x2 << 8)
+#define	LRADC_CTRL3_CYCLE_TIME_2MHZ				(0x3 << 8)
+#define	LRADC_CTRL3_HIGH_TIME_MASK				(0x3 << 4)
+#define	LRADC_CTRL3_HIGH_TIME_OFFSET				4
+#define	LRADC_CTRL3_HIGH_TIME_42NS				(0x0 << 4)
+#define	LRADC_CTRL3_HIGH_TIME_83NS				(0x1 << 4)
+#define	LRADC_CTRL3_HIGH_TIME_125NS				(0x2 << 4)
+#define	LRADC_CTRL3_HIGH_TIME_250NS				(0x3 << 4)
+#define	LRADC_CTRL3_DELAY_CLOCK					(1 << 1)
+#define	LRADC_CTRL3_INVERT_CLOCK				(1 << 0)
+
+#define	LRADC_STATUS_BUTTON1_PRESENT				(1 << 28)
+#define	LRADC_STATUS_BUTTON0_PRESENT				(1 << 27)
+#define	LRADC_STATUS_TEMP1_PRESENT				(1 << 26)
+#define	LRADC_STATUS_TEMP0_PRESENT				(1 << 25)
+#define	LRADC_STATUS_TOUCH_PANEL_PRESENT			(1 << 24)
+#define	LRADC_STATUS_CHANNEL7_PRESENT				(1 << 23)
+#define	LRADC_STATUS_CHANNEL6_PRESENT				(1 << 22)
+#define	LRADC_STATUS_CHANNEL5_PRESENT				(1 << 21)
+#define	LRADC_STATUS_CHANNEL4_PRESENT				(1 << 20)
+#define	LRADC_STATUS_CHANNEL3_PRESENT				(1 << 19)
+#define	LRADC_STATUS_CHANNEL2_PRESENT				(1 << 18)
+#define	LRADC_STATUS_CHANNEL1_PRESENT				(1 << 17)
+#define	LRADC_STATUS_CHANNEL0_PRESENT				(1 << 16)
+#define	LRADC_STATUS_BUTTON1_DETECT_RAW				(1 << 2)
+#define	LRADC_STATUS_BUTTON0_DETECT_RAW				(1 << 1)
+#define	LRADC_STATUS_TOUCH_DETECT_RAW				(1 << 0)
+
+#define	LRADC_CH_TOGGLE						(1 << 31)
+#define	LRADC_CH7_TESTMODE_TOGGLE				(1 << 30)
+#define	LRADC_CH_ACCUMULATE					(1 << 29)
+#define	LRADC_CH_NUM_SAMPLES_MASK				(0x1f << 24)
+#define	LRADC_CH_NUM_SAMPLES_OFFSET				24
+#define	LRADC_CH_VALUE_MASK					0x3ffff
+#define	LRADC_CH_VALUE_OFFSET					0
+
+#define	LRADC_DELAY_TRIGGER_LRADCS_MASK				(0xff << 24)
+#define	LRADC_DELAY_TRIGGER_LRADCS_OFFSET			24
+#define	LRADC_DELAY_KICK					(1 << 20)
+#define	LRADC_DELAY_TRIGGER_DELAYS_MASK				(0xf << 16)
+#define	LRADC_DELAY_TRIGGER_DELAYS_OFFSET			16
+#define	LRADC_DELAY_LOOP_COUNT_MASK				(0x1f << 11)
+#define	LRADC_DELAY_LOOP_COUNT_OFFSET				11
+#define	LRADC_DELAY_DELAY_MASK					0x7ff
+#define	LRADC_DELAY_DELAY_OFFSET				0
+
+#define	LRADC_DEBUG0_READONLY_MASK				(0xffff << 16)
+#define	LRADC_DEBUG0_READONLY_OFFSET				16
+#define	LRADC_DEBUG0_STATE_MASK					(0xfff << 0)
+#define	LRADC_DEBUG0_STATE_OFFSET				0
+
+#define	LRADC_DEBUG1_REQUEST_MASK				(0xff << 16)
+#define	LRADC_DEBUG1_REQUEST_OFFSET				16
+#define	LRADC_DEBUG1_TESTMODE_COUNT_MASK			(0x1f << 8)
+#define	LRADC_DEBUG1_TESTMODE_COUNT_OFFSET			8
+#define	LRADC_DEBUG1_TESTMODE6					(1 << 2)
+#define	LRADC_DEBUG1_TESTMODE5					(1 << 1)
+#define	LRADC_DEBUG1_TESTMODE					(1 << 0)
+
+#define	LRADC_CONVERSION_AUTOMATIC				(1 << 20)
+#define	LRADC_CONVERSION_SCALE_FACTOR_MASK			(0x3 << 16)
+#define	LRADC_CONVERSION_SCALE_FACTOR_OFFSET			16
+#define	LRADC_CONVERSION_SCALE_FACTOR_NIMH			(0x0 << 16)
+#define	LRADC_CONVERSION_SCALE_FACTOR_DUAL_NIMH			(0x1 << 16)
+#define	LRADC_CONVERSION_SCALE_FACTOR_LI_ION			(0x2 << 16)
+#define	LRADC_CONVERSION_SCALE_FACTOR_ALT_LI_ION		(0x3 << 16)
+#define	LRADC_CONVERSION_SCALED_BATT_VOLTAGE_MASK		0x3ff
+#define	LRADC_CONVERSION_SCALED_BATT_VOLTAGE_OFFSET		0
+
+#define	LRADC_CTRL4_LRADC7SELECT_MASK				(0xf << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_OFFSET				28
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL0			(0x0 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL1			(0x1 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL2			(0x2 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL3			(0x3 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL4			(0x4 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL5			(0x5 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL6			(0x6 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL7			(0x7 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL8			(0x8 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL9			(0x9 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL10			(0xa << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL11			(0xb << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL12			(0xc << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL13			(0xd << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL14			(0xe << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL15			(0xf << 28)
+#define	LRADC_CTRL4_LRADC6SELECT_MASK				(0xf << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_OFFSET				24
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL0			(0x0 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL1			(0x1 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL2			(0x2 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL3			(0x3 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL4			(0x4 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL5			(0x5 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL6			(0x6 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL7			(0x7 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL8			(0x8 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL9			(0x9 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL10			(0xa << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL11			(0xb << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL12			(0xc << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL13			(0xd << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL14			(0xe << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL15			(0xf << 24)
+#define	LRADC_CTRL4_LRADC5SELECT_MASK				(0xf << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_OFFSET				20
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL0			(0x0 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL1			(0x1 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL2			(0x2 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL3			(0x3 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL4			(0x4 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL5			(0x5 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL6			(0x6 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL7			(0x7 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL8			(0x8 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL9			(0x9 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL10			(0xa << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL11			(0xb << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL12			(0xc << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL13			(0xd << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL14			(0xe << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL15			(0xf << 20)
+#define	LRADC_CTRL4_LRADC4SELECT_MASK				(0xf << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_OFFSET				16
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL0			(0x0 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL1			(0x1 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL2			(0x2 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL3			(0x3 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL4			(0x4 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL5			(0x5 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL6			(0x6 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL7			(0x7 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL8			(0x8 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL9			(0x9 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL10			(0xa << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL11			(0xb << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL12			(0xc << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL13			(0xd << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL14			(0xe << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL15			(0xf << 16)
+#define	LRADC_CTRL4_LRADC3SELECT_MASK				(0xf << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_OFFSET				12
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL0			(0x0 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL1			(0x1 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL2			(0x2 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL3			(0x3 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL4			(0x4 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL5			(0x5 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL6			(0x6 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL7			(0x7 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL8			(0x8 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL9			(0x9 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL10			(0xa << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL11			(0xb << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL12			(0xc << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL13			(0xd << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL14			(0xe << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL15			(0xf << 12)
+#define	LRADC_CTRL4_LRADC2SELECT_MASK				(0xf << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_OFFSET				8
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL0			(0x0 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL1			(0x1 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL2			(0x2 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL3			(0x3 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL4			(0x4 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL5			(0x5 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL6			(0x6 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL7			(0x7 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL8			(0x8 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL9			(0x9 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL10			(0xa << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL11			(0xb << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL12			(0xc << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL13			(0xd << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL14			(0xe << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL15			(0xf << 8)
+#define	LRADC_CTRL4_LRADC1SELECT_MASK				(0xf << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_OFFSET				4
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL0			(0x0 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL1			(0x1 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL2			(0x2 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL3			(0x3 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL4			(0x4 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL5			(0x5 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL6			(0x6 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL7			(0x7 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL8			(0x8 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL9			(0x9 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL10			(0xa << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL11			(0xb << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL12			(0xc << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL13			(0xd << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL14			(0xe << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL15			(0xf << 4)
+#define	LRADC_CTRL4_LRADC0SELECT_MASK				0xf
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL0			(0x0 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL1			(0x1 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL2			(0x2 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL3			(0x3 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL4			(0x4 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL5			(0x5 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL6			(0x6 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL7			(0x7 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL8			(0x8 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL9			(0x9 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL10			(0xa << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL11			(0xb << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL12			(0xc << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL13			(0xd << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL14			(0xe << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL15			(0xf << 0)
+
+#define	LRADC_THRESHOLD_ENABLE					(1 << 24)
+#define	LRADC_THRESHOLD_BATTCHRG_DISABLE			(1 << 23)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_MASK			(0x7 << 20)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_OFFSET			20
+#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL0			(0x0 << 20)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL1			(0x1 << 20)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL2			(0x2 << 20)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL3			(0x3 << 20)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL4			(0x4 << 20)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL5			(0x5 << 20)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL6			(0x6 << 20)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL7			(0x7 << 20)
+#define	LRADC_THRESHOLD_SETTING_MASK				(0x3 << 18)
+#define	LRADC_THRESHOLD_SETTING_OFFSET				18
+#define	LRADC_THRESHOLD_SETTING_NO_COMPARE			(0x0 << 18)
+#define	LRADC_THRESHOLD_SETTING_DETECT_LOW			(0x1 << 18)
+#define	LRADC_THRESHOLD_SETTING_DETECT_HIGH			(0x2 << 18)
+#define	LRADC_THRESHOLD_SETTING_RESERVED			(0x3 << 18)
+#define	LRADC_THRESHOLD_VALUE_MASK				0x3ffff
+#define	LRADC_THRESHOLD_VALUE_OFFSET				0
+
+#define	LRADC_VERSION_MAJOR_MASK				(0xff << 24)
+#define	LRADC_VERSION_MAJOR_OFFSET				24
+#define	LRADC_VERSION_MINOR_MASK				(0xff << 16)
+#define	LRADC_VERSION_MINOR_OFFSET				16
+#define	LRADC_VERSION_STEP_MASK					0xffff
+#define	LRADC_VERSION_STEP_OFFSET				0
+
+#endif	/* __MX28_REGS_LRADC_H__ */
diff --git a/arch/arm/include/asm/arch-mx28/sys_proto.h b/arch/arm/include/asm/arch-mx28/sys_proto.h
index 15d8de31ee..e701c6409e 100644
--- a/arch/arm/include/asm/arch-mx28/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx28/sys_proto.h
@@ -39,6 +39,36 @@ void mx28_common_spl_init(const iomux_cfg_t *iomux_setup,
 			const unsigned int iomux_size);
 #endif
 
+struct mx28_pair {
+	uint8_t	boot_pads;
+	uint8_t boot_mask;
+	const char *mode;
+};
+
+static const struct mx28_pair mx28_boot_modes[] = {
+	{ 0x00, 0x0f, "USB #0" },
+	{ 0x01, 0x1f, "I2C #0, master, 3V3" },
+	{ 0x11, 0x1f, "I2C #0, master, 1V8" },
+	{ 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" },
+	{ 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" },
+	{ 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" },
+	{ 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" },
+	{ 0x04, 0x1f, "NAND, 3V3" },
+	{ 0x14, 0x1f, "NAND, 1V8" },
+	{ 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" },
+	{ 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" },
+	{ 0x09, 0x1f, "SSP SD/MMC #0, 3V3" },
+	{ 0x19, 0x1f, "SSP SD/MMC #0, 1V8" },
+	{ 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" },
+	{ 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" },
+	{ 0x00, 0x00, "Reserved/Unknown/Wrong" },
+};
+
+struct mx28_spl_data {
+	uint8_t		boot_mode_idx;
+	uint32_t	mem_dram_size;
+};
+
 int mx28_dram_init(void);
 
 #endif	/* __MX28_H__ */
diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h
index ea972a3985..35ee8155de 100644
--- a/arch/arm/include/asm/arch-mx5/clock.h
+++ b/arch/arm/include/asm/arch-mx5/clock.h
@@ -32,6 +32,10 @@ enum mxc_clock {
 	MXC_UART_CLK,
 	MXC_CSPI_CLK,
 	MXC_FEC_CLK,
+	MXC_SATA_CLK,
+	MXC_DDR_CLK,
+	MXC_NFC_CLK,
+	MXC_PERIPH_CLK,
 };
 
 unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
@@ -39,10 +43,11 @@ unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);
 u32 imx_get_uartclk(void);
 u32 imx_get_fecclk(void);
 unsigned int mxc_get_clock(enum mxc_clock clk);
-
+int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
 void set_usb_phy2_clk(void);
 void enable_usb_phy2_clk(unsigned char enable);
 void set_usboh3_clk(void);
 void enable_usboh3_clk(unsigned char enable);
+void mxc_set_sata_internal_clock(void);
 
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h
index bdeafbc0df..4e0fc1bc1d 100644
--- a/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -76,6 +76,9 @@ struct mxc_ccm_reg {
 	u32 CCGR4;
 	u32 CCGR5;
 	u32 CCGR6;	/* 0x0080 */
+#ifdef CONFIG_MX53
+	u32 CCGR7;      /* 0x0084 */
+#endif
 	u32 cmeor;
 };
 
@@ -84,6 +87,9 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CACRR_ARM_PODF_MASK		0x7
 
 /* Define the bits in register CBCDR */
+#define MXC_CCM_CBCDR_DDR_HIFREQ_SEL		(0x1 << 30)
+#define MXC_CCM_CBCDR_DDR_PODF_MASK		(0x7 << 27)
+#define MXC_CCM_CBCDR_DDR_PODF_OFFSET		27
 #define MXC_CCM_CBCDR_EMI_CLK_SEL		(0x1 << 26)
 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL		(0x1 << 25)
 #define MXC_CCM_CBCDR_EMI_PODF_OFFSET		22
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 4fa66587a0..cef419077e 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -43,6 +43,7 @@
 #define NFC_BASE_ADDR_AXI       0xF7FF0000
 #define IRAM_BASE_ADDR          0xF8000000
 #define CS1_BASE_ADDR           0xF4000000
+#define SATA_BASE_ADDR		0x10000000
 #else
 #error "CPU_TYPE not defined"
 #endif
@@ -93,6 +94,7 @@
 #define GPIO5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000DC000)
 #define GPIO6_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E0000)
 #define GPIO7_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E4000)
+#define UART4_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000F0000)
 #endif
 /*
  * AIPS 2
@@ -133,6 +135,10 @@
 #define VPU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F4000)
 #define SAHARA_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000F8000)
 
+#if defined(CONFIG_MX53)
+#define UART5_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00090000)
+#endif
+
 /*
  * WEIM CSnGCR1
  */
@@ -485,6 +491,11 @@ struct iim_regs {
 	} bank[4];
 };
 
+struct fuse_bank0_regs {
+	u32	fuse0_23[24];
+	u32	gp[8];
+};
+
 struct fuse_bank1_regs {
 	u32	fuse0_8[9];
 	u32	mac_addr[6];
diff --git a/arch/arm/include/asm/arch-mx5/iomux.h b/arch/arm/include/asm/arch-mx5/iomux.h
index 760371b48f..e3765a37e3 100644
--- a/arch/arm/include/asm/arch-mx5/iomux.h
+++ b/arch/arm/include/asm/arch-mx5/iomux.h
@@ -66,8 +66,8 @@ typedef enum iomux_pad_config {
 	PAD_CTL_HYS_ENABLE = 0x1 << 8,	/* Hysteresis enabled */
 	PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,/* DDR input CMOS */
 	PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,/* DDR input DDR */
-	PAD_CTL_DRV_VOT_LOW = 0x0 << 13, /* Low voltage mode */
-	PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,/* High voltage mode */
+	PAD_CTL_DRV_VOT_LOW = 0x1 << 13, /* Low voltage mode */
+	PAD_CTL_DRV_VOT_HIGH = 0x0 << 13,/* High voltage mode */
 } iomux_pad_config_t;
 
 /* various IOMUX input functions */
diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h
index 13d12ee1a4..7b5246eea6 100644
--- a/arch/arm/include/asm/arch-mx5/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx5/sys_proto.h
@@ -35,5 +35,8 @@ void set_chipselect_size(int const);
  */
 
 int fecmxc_initialize(bd_t *bis);
+u32 get_ahb_clk(void);
+u32 get_periph_clk(void);
+char *get_reset_cause(void);
 
 #endif
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 613809bdd6..b91d8bf450 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -47,5 +47,6 @@ u32 imx_get_uartclk(void);
 u32 imx_get_fecclk(void);
 unsigned int mxc_get_clock(enum mxc_clock clk);
 void enable_usboh3_clk(unsigned char enable);
+int enable_sata_clock(void);
 
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx6/ccm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 4af0b90164..0e605c26f5 100644
--- a/arch/arm/include/asm/arch-mx6/ccm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -20,7 +20,7 @@
 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
 
-struct imx_ccm_reg {
+struct mxc_ccm_reg {
 	u32 ccr;	/* 0x0000 */
 	u32 ccdr;
 	u32 csr;
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 6d25c8d983..e165810ddc 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -436,5 +436,14 @@ struct anatop_regs {
 	u32	digprog;		/* 0x260 */
 };
 
+struct iomuxc_base_regs {
+	u32     gpr[14];        /* 0x000 */
+	u32     obsrv[5];       /* 0x038 */
+	u32     swmux_ctl[197]; /* 0x04c */
+	u32     swpad_ctl[250]; /* 0x360 */
+	u32     swgrp[26];      /* 0x748 */
+	u32     daisy[104];     /* 0x7b0..94c */
+};
+
 #endif /* __ASSEMBLER__*/
 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/iomux-v3.h b/arch/arm/include/asm/arch-mx6/iomux-v3.h
index 4558f4fba2..788b413219 100644
--- a/arch/arm/include/asm/arch-mx6/iomux-v3.h
+++ b/arch/arm/include/asm/arch-mx6/iomux-v3.h
@@ -100,4 +100,115 @@ typedef u64 iomux_v3_cfg_t;
 int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
 int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count);
 
+/*
+ * IOMUXC_GPR13 bit fields
+ */
+#define IOMUXC_GPR13_SDMA_STOP_REQ	(1<<30)
+#define IOMUXC_GPR13_CAN2_STOP_REQ	(1<<29)
+#define IOMUXC_GPR13_CAN1_STOP_REQ	(1<<28)
+#define IOMUXC_GPR13_ENET_STOP_REQ	(1<<27)
+#define IOMUXC_GPR13_SATA_PHY_8_MASK	(7<<24)
+#define IOMUXC_GPR13_SATA_PHY_7_MASK	(0x1f<<19)
+#define IOMUXC_GPR13_SATA_PHY_6_SHIFT	16
+#define IOMUXC_GPR13_SATA_PHY_6_MASK	(7<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+#define IOMUXC_GPR13_SATA_SPEED_MASK	(1<<15)
+#define IOMUXC_GPR13_SATA_PHY_5_MASK	(1<<14)
+#define IOMUXC_GPR13_SATA_PHY_4_MASK	(7<<11)
+#define IOMUXC_GPR13_SATA_PHY_3_MASK	(0x1f<<7)
+#define IOMUXC_GPR13_SATA_PHY_2_MASK	(0x1f<<2)
+#define IOMUXC_GPR13_SATA_PHY_1_MASK	(3<<0)
+
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB	(0b000<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB	(0b001<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB	(0b010<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB	(0b011<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB	(0b100<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB	(0b101<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB	(0b110<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB	(0b111<<24)
+
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1I	(0b10000<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1M	(0b10000<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1X	(0b11010<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2I	(0b10010<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2M	(0b10010<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2X	(0b11010<<19)
+
+#define IOMUXC_GPR13_SATA_SPEED_1P5G	(0<<15)
+#define IOMUXC_GPR13_SATA_SPEED_3G	(1<<15)
+
+#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED	(0<<14)
+#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_ENABLED		(1<<14)
+
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_16_16	(0<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_14_16	(1<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16	(2<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_10_16	(3<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16		(4<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16		(5<<11)
+
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB	(0b0000<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB	(0b0001<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB	(0b0010<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB	(0b0011<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB	(0b0100<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB	(0b0101<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB	(0b0110<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB	(0b0111<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB	(0b1000<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB	(0b1001<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB	(0b1010<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB	(0b1011<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB	(0b1100<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB	(0b1101<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB	(0b1110<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB	(0b1111<<7)
+
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V	(0b00000<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V	(0b00001<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V	(0b00010<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V	(0b00011<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V	(0b00100<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V	(0b00101<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V	(0b00110<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V	(0b00111<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V	(0b01000<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V	(0b01001<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V	(0b01010<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V	(0b01011<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V	(0b01100<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V	(0b01101<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V	(0b01110<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V	(0b01111<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V	(0b10000<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V	(0b10001<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V	(0b10010<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V	(0b10011<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V	(0b10100<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V	(0b10101<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V	(0b10110<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V	(0b10111<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V	(0b11000<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V	(0b11001<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V	(0b11010<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V	(0b11011<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V	(0b11100<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V	(0b11101<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V	(0b11110<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V	(0b11111<<2)
+
+#define IOMUXC_GPR13_SATA_PHY_1_FAST	0
+#define IOMUXC_GPR13_SATA_PHY_1_MEDIUM	1
+#define IOMUXC_GPR13_SATA_PHY_1_SLOW	2
+
+#define IOMUXC_GPR13_SATA_MASK (IOMUXC_GPR13_SATA_PHY_8_MASK \
+				|IOMUXC_GPR13_SATA_PHY_7_MASK \
+				|IOMUXC_GPR13_SATA_PHY_6_MASK \
+				|IOMUXC_GPR13_SATA_SPEED_MASK \
+				|IOMUXC_GPR13_SATA_PHY_5_MASK \
+				|IOMUXC_GPR13_SATA_PHY_4_MASK \
+				|IOMUXC_GPR13_SATA_PHY_3_MASK \
+				|IOMUXC_GPR13_SATA_PHY_2_MASK \
+				|IOMUXC_GPR13_SATA_PHY_1_MASK)
+
 #endif	/* __MACH_IOMUX_V3_H__*/
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 668e77af6a..711b30dfe2 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -28,11 +28,14 @@
 
 u32 get_cpu_rev(void);
 
+void set_vddsoc(u32 mv);
+
 /*
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()
  */
 
 int fecmxc_initialize(bd_t *bis);
-
+u32 get_ahb_clk(void);
+u32 get_periph_clk(void);
 #endif
diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h
index 84308e04b3..457f99d2c5 100644
--- a/arch/arm/include/asm/arch-omap3/cpu.h
+++ b/arch/arm/include/asm/arch-omap3/cpu.h
@@ -474,12 +474,11 @@ struct prm {
 	u8 res3[0x1c];
 	u32 clksrc_ctrl;	/* 0x1270 */
 };
-#else /* __ASSEMBLY__ */
-#define PRM_RSTCTRL		0x48307250
-#define PRM_RSTCTRL_RESET	0x04
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */
 
+#define PRM_RSTCTRL		0x48307250
+#define PRM_RSTCTRL_RESET	0x04
 #define SYSCLKDIV_1		(0x1 << 6)
 #define SYSCLKDIV_2		(0x1 << 7)
 
diff --git a/arch/arm/include/asm/arch-omap3/mmc_host_def.h b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
index f8c42c0d20..3ce1f07b8a 100644
--- a/arch/arm/include/asm/arch-omap3/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
@@ -33,7 +33,9 @@ typedef struct t2 {
 	unsigned int devconf0;		/* 0x274 */
 	unsigned char res2[0x060];	/* 0x278 */
 	unsigned int devconf1;		/* 0x2D8 */
-	unsigned char res3[0x244];	/* 0x2DC */
+	unsigned char res3[0x16C];	/* 0x2DC */
+	unsigned int ctl_prog_io1;	/* 0x448 */
+	unsigned char res4[0x0D4];	/* 0x44C */
 	unsigned int pbias_lite;	/* 0x520 */
 } t2_t;
 
@@ -48,6 +50,8 @@ typedef struct t2 {
 #define PBIASSPEEDCTRL0			(1 << 2)
 #define PBIASLITEPWRDNZ1		(1 << 9)
 
+#define CTLPROGIO1SPEEDCTRL		(1 << 20)
+
 /*
  * OMAP HSMMC register definitions
  */
@@ -191,6 +195,6 @@ struct hsmmc {
 #define mmc_reg_out(addr, mask, val)\
 	writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
 
-int omap_mmc_init(int dev_index);
+int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
 
 #endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h
index 6daef49e97..71f183de8d 100644
--- a/arch/arm/include/asm/arch-omap3/mux.h
+++ b/arch/arm/include/asm/arch-omap3/mux.h
@@ -445,6 +445,12 @@
 #define CONTROL_PADCONF_STRBEN_DLY1	0x0224
 #define CONTROL_PADCONF_SYS_BOOT8	0x0226
 
+/* AM/DM37xx specific */
+#define CONTROL_PADCONF_GPIO127		0x0A54
+#define CONTROL_PADCONF_GPIO126		0x0A56
+#define CONTROL_PADCONF_GPIO128		0x0A58
+#define CONTROL_PADCONF_GPIO129		0x0A5A
+
 #define MUX_VAL(OFFSET,VALUE)\
 	writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
 
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
index cd304e8684..617729c32b 100644
--- a/arch/arm/include/asm/arch-omap4/clocks.h
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -652,23 +652,9 @@ struct omap4_scrm_regs {
 #define OMAP_SYS_CLK_IND_38_4_MHZ	6
 #define OMAP_32K_CLK_FREQ		32768
 
-/* PRM_VC_CFG_I2C_CLK */
-#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT		0
-#define PRM_VC_CFG_I2C_CLK_SCLH_MASK		0xFF
-#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT		8
-#define PRM_VC_CFG_I2C_CLK_SCLL_MASK		(0xFF << 8)
-
 /* PRM_VC_VAL_BYPASS */
 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ	400
 
-#define PRM_VC_VAL_BYPASS_VALID_BIT	0x1000000
-#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT	0
-#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK	0x7F
-#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT		8
-#define PRM_VC_VAL_BYPASS_REGADDR_MASK		0xFF
-#define PRM_VC_VAL_BYPASS_DATA_SHIFT		16
-#define PRM_VC_VAL_BYPASS_DATA_MASK		0xFF
-
 /* SMPS */
 #define SMPS_I2C_SLAVE_ADDR	0x12
 #define SMPS_REG_ADDR_VCORE1	0x55
@@ -754,10 +740,10 @@ extern struct omap4_prcm_regs *const prcm;
 extern const u32 sys_clk_array[8];
 
 void scale_vcores(void);
-void do_scale_tps62361(u32 reg, u32 volt_mv);
+void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
+u32 get_offset_code(u32 offset);
 u32 omap_ddr_clk(void);
 void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
-void setup_sri2c(void);
 void setup_post_dividers(u32 *const base, const struct dpll_params *params);
 u32 get_sys_clk_index(void);
 void enable_basic_clocks(void);
diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h
index 08b9c99353..feddb7de51 100644
--- a/arch/arm/include/asm/arch-omap4/cpu.h
+++ b/arch/arm/include/asm/arch-omap4/cpu.h
@@ -168,4 +168,15 @@ struct watchdog {
 #define OMAP_GPIO_CLEARDATAOUT		0x0190
 #define OMAP_GPIO_SETDATAOUT		0x0194
 
+/*
+ * PRCM
+ */
+
+/* PRM */
+#define PRM_BASE		0x4A306000
+#define PRM_DEVICE_BASE		(PRM_BASE + 0x1B00)
+
+#define PRM_RSTCTRL		PRM_DEVICE_BASE
+#define PRM_RSTCTRL_RESET	0x01
+
 #endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
index ce1bce1fdd..2114046e71 100644
--- a/arch/arm/include/asm/arch-omap4/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
@@ -169,6 +169,6 @@ struct hsmmc {
 #define mmc_reg_out(addr, mask, val)\
 	writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
 
-int omap_mmc_init(int dev_index);
+int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
 
 #endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap4/mux_omap4.h b/arch/arm/include/asm/arch-omap4/mux_omap4.h
index 30bfad7c20..4de7c70bf6 100644
--- a/arch/arm/include/asm/arch-omap4/mux_omap4.h
+++ b/arch/arm/include/asm/arch-omap4/mux_omap4.h
@@ -34,7 +34,7 @@ struct pad_conf_entry {
 
 	u16 val;
 
-} __attribute__ ((packed));
+};
 
 #ifdef CONFIG_OFF_PADCONF
 #define OFF_PD          (1 << 12)
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index 416c6de314..47c5883025 100644
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -101,17 +101,6 @@
 #define TCLR_AR			(0x1 << 1)
 #define TCLR_PRE		(0x1 << 5)
 
-/*
- * PRCM
- */
-
-/* PRM */
-#define PRM_BASE		0x4A306000
-#define PRM_DEVICE_BASE		(PRM_BASE + 0x1B00)
-
-#define PRM_RSTCTRL		PRM_DEVICE_BASE
-#define PRM_RSTCTRL_RESET	0x01
-
 /* Control Module */
 #define LDOSRAM_ACTMODE_VSET_IN_MASK	(0x1F << 5)
 #define LDOSRAM_VOLT_CTRL_OVERRIDE	0x0401040f
@@ -139,18 +128,24 @@ struct s32ktimer {
 	unsigned int s32k_cr;	/* 0x10 */
 };
 
-struct omap4_sys_ctrl_regs {
+#define DEVICE_TYPE_SHIFT (0x8)
+#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
+#define DEVICE_GP 0x3
+
+struct omap_sys_ctrl_regs {
 	unsigned int pad1[129];
 	unsigned int control_id_code;			/* 0x4A002204 */
 	unsigned int pad11[22];
 	unsigned int control_std_fuse_opp_bgap;		/* 0x4a002260 */
-	unsigned int pad2[47];
+	unsigned int pad2[24];				/* 0x4a002264 */
+	unsigned int control_status;			/* 0x4a0022c4 */
+	unsigned int pad3[22];				/* 0x4a0022c8 */
 	unsigned int control_ldosram_iva_voltage_ctrl;	/* 0x4A002320 */
 	unsigned int control_ldosram_mpu_voltage_ctrl;	/* 0x4A002324 */
 	unsigned int control_ldosram_core_voltage_ctrl;	/* 0x4A002328 */
-	unsigned int pad3[260277];
+	unsigned int pad4[260277];
 	unsigned int control_pbiaslite;                 /* 0x4A100600 */
-	unsigned int pad4[63];
+	unsigned int pad5[63];
 	unsigned int control_efuse_1;			/* 0x4A100700 */
 	unsigned int control_efuse_2;			/* 0x4A100704 */
 };
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index b8dbc2c9a2..c6e3ad26ff 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -55,6 +55,8 @@ u32 omap_sdram_size(void);
 u32 cortex_rev(void);
 void init_omap_revision(void);
 void do_io_settings(void);
+void omap_vc_init(u16 speed_khz);
+int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
 /*
  * This is used to verify if the configuration header
  * was executed by Romcode prior to control of transfer
@@ -112,10 +114,4 @@ static inline u32 omap_hw_init_context(void)
 #endif
 }
 
-static inline u32 omap_revision(void)
-{
-	extern u32 *const omap4_revision;
-	return *omap4_revision;
-}
-
 #endif
diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h
index d0e6dd68da..f32cf3eeef 100644
--- a/arch/arm/include/asm/arch-omap5/clocks.h
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -473,9 +473,11 @@ struct omap5_prcm_regs {
 	u32 cm_wkup_rtc_clkctrl;		/* 4ae07880 */
 	u32 pad214;				/* 4ae07884 */
 	u32 cm_wkup_bandgap_clkctrl;		/* 4ae07888 */
-	u32 pad215[197];			/* 4ae0788c */
+	u32 pad215[1];				/* 4ae0788c */
+	u32 cm_wkupaon_scrm_clkctrl;		/* 4ae07890 */
+	u32 pad216[195];
 	u32 prm_vc_val_bypass;			/* 4ae07ba0 */
-	u32 pad216[4];
+	u32 pad217[4];
 	u32 prm_vc_cfg_i2c_mode;		/* 4ae07bb4 */
 	u32 prm_vc_cfg_i2c_clk;			/* 4ae07bb8 */
 };
@@ -514,6 +516,10 @@ struct omap5_prcm_regs {
 /* CM_IDLEST_DPLL fields */
 #define ST_DPLL_CLK_MASK		1
 
+/* SGX */
+#define CLKSEL_GPU_HYD_GCLK_MASK		(1 << 25)
+#define CLKSEL_GPU_CORE_GCLK_MASK		(1 << 24)
+
 /* CM_CLKSEL_DPLL */
 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT	24
 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK		(0xFF << 24)
@@ -591,6 +597,7 @@ struct omap5_prcm_regs {
 
 /* CM_L3INIT_HSMMCn_CLKCTRL */
 #define HSMMC_CLKCTRL_CLKSEL_MASK		(1 << 24)
+#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK		(1 << 25)
 
 /* CM_WKUP_GPTIMER1_CLKCTRL */
 #define GPTIMER1_CLKCTRL_CLKSEL_MASK		(1 << 24)
@@ -610,36 +617,33 @@ struct omap5_prcm_regs {
 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT	25
 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK	(1 << 25)
 
+/* CM_WKUPAON_SCRM_CLKCTRL */
+#define OPTFCLKEN_SCRM_PER_SHIFT		9
+#define OPTFCLKEN_SCRM_PER_MASK			(1 << 9)
+#define OPTFCLKEN_SCRM_CORE_SHIFT		8
+#define OPTFCLKEN_SCRM_CORE_MASK		(1 << 8)
+
 /* Clock frequencies */
 #define OMAP_SYS_CLK_FREQ_38_4_MHZ	38400000
 #define OMAP_SYS_CLK_IND_38_4_MHZ	6
 #define OMAP_32K_CLK_FREQ		32768
 
-/* PRM_VC_CFG_I2C_CLK */
-#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT		0
-#define PRM_VC_CFG_I2C_CLK_SCLH_MASK		0xFF
-#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT		8
-#define PRM_VC_CFG_I2C_CLK_SCLL_MASK		(0xFF << 8)
-
 /* PRM_VC_VAL_BYPASS */
 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ	400
 
-#define PRM_VC_VAL_BYPASS_VALID_BIT	0x1000000
-#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT	0
-#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK	0x7F
-#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT		8
-#define PRM_VC_VAL_BYPASS_REGADDR_MASK		0xFF
-#define PRM_VC_VAL_BYPASS_DATA_SHIFT		16
-#define PRM_VC_VAL_BYPASS_DATA_MASK		0xFF
-
 /* SMPS */
 #define SMPS_I2C_SLAVE_ADDR	0x12
-#define SMPS_REG_ADDR_VCORE1	0x55
-#define SMPS_REG_ADDR_VCORE2	0x5B
-#define SMPS_REG_ADDR_VCORE3	0x61
+#define SMPS_REG_ADDR_12_MPU	0x23
+#define SMPS_REG_ADDR_45_IVA	0x2B
+#define SMPS_REG_ADDR_8_CORE	0x37
+
+/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */
+#define VDD_MPU		1000
+#define VDD_MM		1000
+#define VDD_CORE	1040
 
-#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV		607700
-#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV	709000
+/* Standard offset is 0.5v expressed in uv */
+#define PALMAS_SMPS_BASE_VOLT_UV 500000
 
 /* TPS */
 #define TPS62361_I2C_SLAVE_ADDR		0x60
@@ -677,7 +681,7 @@ struct dpll_regs {
 	u32 cm_div_h12_dpll;
 	u32 cm_div_h13_dpll;
 	u32 cm_div_h14_dpll;
-	u32 reserved[2];
+	u32 reserved[3];
 	u32 cm_div_h22_dpll;
 	u32 cm_div_h23_dpll;
 };
@@ -700,10 +704,10 @@ extern struct omap5_prcm_regs *const prcm;
 extern const u32 sys_clk_array[8];
 
 void scale_vcores(void);
-void do_scale_tps62361(u32 reg, u32 volt_mv);
+void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
+u32 get_offset_code(u32 offset);
 u32 omap_ddr_clk(void);
 void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
-void setup_sri2c(void);
 void setup_post_dividers(u32 *const base, const struct dpll_params *params);
 u32 get_sys_clk_index(void);
 void enable_basic_clocks(void);
diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
index 0697a732de..8ef17c9a14 100644
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -172,4 +172,15 @@ struct watchdog {
 #define OMAP_GPIO_CLEARDATAOUT		0x0190
 #define OMAP_GPIO_SETDATAOUT		0x0194
 
+/*
+ * PRCM
+ */
+
+/* PRM */
+#define PRM_BASE		0x4AE06000
+#define PRM_DEVICE_BASE		(PRM_BASE + 0x1B00)
+
+#define PRM_RSTCTRL		PRM_DEVICE_BASE
+#define PRM_RSTCTRL_RESET	0x01
+
 #endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-omap5/mmc_host_def.h b/arch/arm/include/asm/arch-omap5/mmc_host_def.h
index ce1bce1fdd..2114046e71 100644
--- a/arch/arm/include/asm/arch-omap5/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap5/mmc_host_def.h
@@ -169,6 +169,6 @@ struct hsmmc {
 #define mmc_reg_out(addr, mask, val)\
 	writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
 
-int omap_mmc_init(int dev_index);
+int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
 
 #endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap5/mux_omap5.h b/arch/arm/include/asm/arch-omap5/mux_omap5.h
index b8c21853f0..4a6ed8b455 100644
--- a/arch/arm/include/asm/arch-omap5/mux_omap5.h
+++ b/arch/arm/include/asm/arch-omap5/mux_omap5.h
@@ -34,7 +34,7 @@ struct pad_conf_entry {
 
 	u16 val;
 
-} __attribute__ ((__packed__));
+};
 
 #ifdef CONFIG_OFF_PADCONF
 #define OFF_PD          (1 << 12)
@@ -87,258 +87,256 @@ struct pad_conf_entry {
 #define CORE_REVISION		0x0000
 #define CORE_HWINFO		0x0004
 #define CORE_SYSCONFIG		0x0010
-#define GPMC_AD0		0x0040
-#define GPMC_AD1		0x0042
-#define GPMC_AD2		0x0044
-#define GPMC_AD3		0x0046
-#define GPMC_AD4		0x0048
-#define GPMC_AD5		0x004A
-#define GPMC_AD6		0x004C
-#define GPMC_AD7		0x004E
-#define GPMC_AD8		0x0050
-#define GPMC_AD9		0x0052
-#define GPMC_AD10		0x0054
-#define GPMC_AD11		0x0056
-#define GPMC_AD12		0x0058
-#define GPMC_AD13		0x005A
-#define GPMC_AD14		0x005C
-#define GPMC_AD15		0x005E
-#define GPMC_A16		0x0060
-#define GPMC_A17		0x0062
-#define GPMC_A18		0x0064
-#define GPMC_A19		0x0066
-#define GPMC_A20		0x0068
-#define GPMC_A21		0x006A
-#define GPMC_A22		0x006C
-#define GPMC_A23		0x006E
-#define GPMC_A24		0x0070
-#define GPMC_A25		0x0072
-#define GPMC_NCS0		0x0074
-#define GPMC_NCS1		0x0076
-#define GPMC_NCS2		0x0078
-#define GPMC_NCS3		0x007A
-#define GPMC_NWP		0x007C
-#define GPMC_CLK		0x007E
-#define GPMC_NADV_ALE		0x0080
-#define GPMC_NOE		0x0082
-#define GPMC_NWE		0x0084
-#define GPMC_NBE0_CLE		0x0086
-#define GPMC_NBE1		0x0088
-#define GPMC_WAIT0		0x008A
-#define GPMC_WAIT1		0x008C
-#define C2C_DATA11		0x008E
-#define C2C_DATA12		0x0090
-#define C2C_DATA13		0x0092
-#define C2C_DATA14		0x0094
-#define C2C_DATA15		0x0096
-#define HDMI_HPD		0x0098
-#define HDMI_CEC		0x009A
-#define HDMI_DDC_SCL		0x009C
-#define HDMI_DDC_SDA		0x009E
-#define CSI21_DX0		0x00A0
-#define CSI21_DY0		0x00A2
-#define CSI21_DX1		0x00A4
-#define CSI21_DY1		0x00A6
-#define CSI21_DX2		0x00A8
-#define CSI21_DY2		0x00AA
-#define CSI21_DX3		0x00AC
-#define CSI21_DY3		0x00AE
-#define CSI21_DX4		0x00B0
-#define CSI21_DY4		0x00B2
-#define CSI22_DX0		0x00B4
-#define CSI22_DY0		0x00B6
-#define CSI22_DX1		0x00B8
-#define CSI22_DY1		0x00BA
-#define CAM_SHUTTER		0x00BC
-#define CAM_STROBE		0x00BE
-#define CAM_GLOBALRESET		0x00C0
-#define USBB1_ULPITLL_CLK	0x00C2
-#define USBB1_ULPITLL_STP	0x00C4
-#define USBB1_ULPITLL_DIR	0x00C6
-#define USBB1_ULPITLL_NXT	0x00C8
-#define USBB1_ULPITLL_DAT0	0x00CA
-#define USBB1_ULPITLL_DAT1	0x00CC
-#define USBB1_ULPITLL_DAT2	0x00CE
-#define USBB1_ULPITLL_DAT3	0x00D0
-#define USBB1_ULPITLL_DAT4	0x00D2
-#define USBB1_ULPITLL_DAT5	0x00D4
-#define USBB1_ULPITLL_DAT6	0x00D6
-#define USBB1_ULPITLL_DAT7	0x00D8
-#define USBB1_HSIC_DATA		0x00DA
-#define USBB1_HSIC_STROBE	0x00DC
-#define USBC1_ICUSB_DP		0x00DE
-#define USBC1_ICUSB_DM		0x00E0
-#define SDMMC1_CLK		0x00E2
-#define SDMMC1_CMD		0x00E4
-#define SDMMC1_DAT0		0x00E6
-#define SDMMC1_DAT1		0x00E8
-#define SDMMC1_DAT2		0x00EA
-#define SDMMC1_DAT3		0x00EC
-#define SDMMC1_DAT4		0x00EE
-#define SDMMC1_DAT5		0x00F0
-#define SDMMC1_DAT6		0x00F2
-#define SDMMC1_DAT7		0x00F4
-#define ABE_MCBSP2_CLKX		0x00F6
-#define ABE_MCBSP2_DR		0x00F8
-#define ABE_MCBSP2_DX		0x00FA
-#define ABE_MCBSP2_FSX		0x00FC
-#define ABE_MCBSP1_CLKX		0x00FE
-#define ABE_MCBSP1_DR		0x0100
-#define ABE_MCBSP1_DX		0x0102
-#define ABE_MCBSP1_FSX		0x0104
-#define ABE_PDM_UL_DATA		0x0106
-#define ABE_PDM_DL_DATA		0x0108
-#define ABE_PDM_FRAME		0x010A
-#define ABE_PDM_LB_CLK		0x010C
-#define ABE_CLKS		0x010E
-#define ABE_DMIC_CLK1		0x0110
-#define ABE_DMIC_DIN1		0x0112
-#define ABE_DMIC_DIN2		0x0114
-#define ABE_DMIC_DIN3		0x0116
-#define UART2_CTS		0x0118
-#define UART2_RTS		0x011A
-#define UART2_RX		0x011C
-#define UART2_TX		0x011E
-#define HDQ_SIO			0x0120
-#define I2C1_SCL		0x0122
-#define I2C1_SDA		0x0124
-#define I2C2_SCL		0x0126
-#define I2C2_SDA		0x0128
-#define I2C3_SCL		0x012A
-#define I2C3_SDA		0x012C
-#define I2C4_SCL		0x012E
-#define I2C4_SDA		0x0130
-#define MCSPI1_CLK		0x0132
-#define MCSPI1_SOMI		0x0134
-#define MCSPI1_SIMO		0x0136
-#define MCSPI1_CS0		0x0138
-#define MCSPI1_CS1		0x013A
-#define MCSPI1_CS2		0x013C
-#define MCSPI1_CS3		0x013E
-#define UART3_CTS_RCTX		0x0140
-#define UART3_RTS_SD		0x0142
-#define UART3_RX_IRRX		0x0144
-#define UART3_TX_IRTX		0x0146
-#define SDMMC5_CLK		0x0148
-#define SDMMC5_CMD		0x014A
-#define SDMMC5_DAT0		0x014C
-#define SDMMC5_DAT1		0x014E
-#define SDMMC5_DAT2		0x0150
-#define SDMMC5_DAT3		0x0152
-#define MCSPI4_CLK		0x0154
-#define MCSPI4_SIMO		0x0156
-#define MCSPI4_SOMI		0x0158
-#define MCSPI4_CS0		0x015A
-#define UART4_RX		0x015C
-#define UART4_TX		0x015E
-#define USBB2_ULPITLL_CLK	0x0160
-#define USBB2_ULPITLL_STP	0x0162
-#define USBB2_ULPITLL_DIR	0x0164
-#define USBB2_ULPITLL_NXT	0x0166
-#define USBB2_ULPITLL_DAT0	0x0168
-#define USBB2_ULPITLL_DAT1	0x016A
-#define USBB2_ULPITLL_DAT2	0x016C
-#define USBB2_ULPITLL_DAT3	0x016E
-#define USBB2_ULPITLL_DAT4	0x0170
-#define USBB2_ULPITLL_DAT5	0x0172
-#define USBB2_ULPITLL_DAT6	0x0174
-#define USBB2_ULPITLL_DAT7	0x0176
-#define USBB2_HSIC_DATA		0x0178
-#define USBB2_HSIC_STROBE	0x017A
-#define UNIPRO_TX0		0x017C
-#define UNIPRO_TY0		0x017E
-#define UNIPRO_TX1		0x0180
-#define UNIPRO_TY1		0x0182
-#define UNIPRO_TX2		0x0184
-#define UNIPRO_TY2		0x0186
-#define UNIPRO_RX0		0x0188
-#define UNIPRO_RY0		0x018A
-#define UNIPRO_RX1		0x018C
-#define UNIPRO_RY1		0x018E
-#define UNIPRO_RX2		0x0190
-#define UNIPRO_RY2		0x0192
-#define USBA0_OTG_CE		0x0194
-#define USBA0_OTG_DP		0x0196
-#define USBA0_OTG_DM		0x0198
-#define FREF_CLK1_OUT		0x019A
-#define FREF_CLK2_OUT		0x019C
-#define SYS_NIRQ1		0x019E
-#define SYS_NIRQ2		0x01A0
-#define SYS_BOOT0		0x01A2
-#define SYS_BOOT1		0x01A4
-#define SYS_BOOT2		0x01A6
-#define SYS_BOOT3		0x01A8
-#define SYS_BOOT4		0x01AA
-#define SYS_BOOT5		0x01AC
-#define DPM_EMU0		0x01AE
-#define DPM_EMU1		0x01B0
-#define DPM_EMU2		0x01B2
-#define DPM_EMU3		0x01B4
-#define DPM_EMU4		0x01B6
-#define DPM_EMU5		0x01B8
-#define DPM_EMU6		0x01BA
-#define DPM_EMU7		0x01BC
-#define DPM_EMU8		0x01BE
-#define DPM_EMU9		0x01C0
-#define DPM_EMU10		0x01C2
-#define DPM_EMU11		0x01C4
-#define DPM_EMU12		0x01C6
-#define DPM_EMU13		0x01C8
-#define DPM_EMU14		0x01CA
-#define DPM_EMU15		0x01CC
-#define DPM_EMU16		0x01CE
-#define DPM_EMU17		0x01D0
-#define DPM_EMU18		0x01D2
-#define DPM_EMU19		0x01D4
-#define WAKEUPEVENT_0		0x01D8
-#define WAKEUPEVENT_1		0x01DC
-#define WAKEUPEVENT_2		0x01E0
-#define WAKEUPEVENT_3		0x01E4
-#define WAKEUPEVENT_4		0x01E8
-#define WAKEUPEVENT_5		0x01EC
-#define WAKEUPEVENT_6		0x01F0
+#define EMMC_CLK		0x0040
+#define EMMC_CMD		0x0042
+#define EMMC_DATA0		0x0044
+#define EMMC_DATA1		0x0046
+#define EMMC_DATA2		0x0048
+#define EMMC_DATA3		0x004a
+#define EMMC_DATA4		0x004c
+#define EMMC_DATA5		0x004e
+#define EMMC_DATA6		0x0050
+#define EMMC_DATA7		0x0052
+#define C2C_CLKOUT0		0x0054
+#define C2C_CLKOUT1		0x0056
+#define C2C_CLKIN0		0x0058
+#define C2C_CLKIN1		0x005a
+#define C2C_DATAIN0		0x005c
+#define C2C_DATAIN1		0x005e
+#define C2C_DATAIN2		0x0060
+#define C2C_DATAIN3		0x0062
+#define C2C_DATAIN4		0x0064
+#define C2C_DATAIN5		0x0066
+#define C2C_DATAIN6		0x0068
+#define C2C_DATAIN7		0x006a
+#define C2C_DATAOUT0		0x006c
+#define C2C_DATAOUT1		0x006e
+#define C2C_DATAOUT2		0x0070
+#define C2C_DATAOUT3		0x0072
+#define C2C_DATAOUT4		0x0074
+#define C2C_DATAOUT5		0x0076
+#define C2C_DATAOUT6		0x0078
+#define C2C_DATAOUT7		0x007a
+#define C2C_DATA8		0x007c
+#define C2C_DATA9		0x007e
+#define C2C_DATA10		0x0080
+#define C2C_DATA11		0x0082
+#define C2C_DATA12		0x0084
+#define C2C_DATA13		0x0086
+#define C2C_DATA14		0x0088
+#define C2C_DATA15		0x008a
+#define LLIA_WAKEREQOUT		0x008c
+#define LLIB_WAKEREQOUT		0x008e
+#define HSI1_ACREADY		0x0090
+#define HSI1_CAREADY		0x0092
+#define HSI1_ACWAKE		0x0094
+#define HSI1_CAWAKE		0x0096
+#define HSI1_ACFLAG		0x0098
+#define HSI1_ACDATA		0x009a
+#define HSI1_CAFLAG		0x009c
+#define HSI1_CADATA		0x009e
+#define UART1_TX		0x00a0
+#define UART1_CTS		0x00a2
+#define UART1_RX		0x00a4
+#define UART1_RTS		0x00a6
+#define HSI2_CAREADY		0x00a8
+#define HSI2_ACREADY		0x00aa
+#define HSI2_CAWAKE		0x00ac
+#define HSI2_ACWAKE		0x00ae
+#define HSI2_CAFLAG		0x00b0
+#define HSI2_CADATA		0x00b2
+#define HSI2_ACFLAG		0x00b4
+#define HSI2_ACDATA		0x00b6
+#define UART2_RTS		0x00b8
+#define UART2_CTS		0x00ba
+#define UART2_RX		0x00bc
+#define UART2_TX		0x00be
+#define USBB1_HSIC_STROBE	0x00c0
+#define USBB1_HSIC_DATA		0x00c2
+#define USBB2_HSIC_STROBE	0x00c4
+#define USBB2_HSIC_DATA		0x00c6
+#define TIMER10_PWM_EVT		0x00c8
+#define DSIPORTA_TE0		0x00ca
+#define DSIPORTA_LANE0X		0x00cc
+#define DSIPORTA_LANE0Y		0x00ce
+#define DSIPORTA_LANE1X		0x00d0
+#define DSIPORTA_LANE1Y		0x00d2
+#define DSIPORTA_LANE2X		0x00d4
+#define DSIPORTA_LANE2Y		0x00d6
+#define DSIPORTA_LANE3X		0x00d8
+#define DSIPORTA_LANE3Y		0x00da
+#define DSIPORTA_LANE4X		0x00dc
+#define DSIPORTA_LANE4Y		0x00de
+#define DSIPORTC_LANE0X		0x00e0
+#define DSIPORTC_LANE0Y		0x00e2
+#define DSIPORTC_LANE1X		0x00e4
+#define DSIPORTC_LANE1Y		0x00e6
+#define DSIPORTC_LANE2X		0x00e8
+#define DSIPORTC_LANE2Y		0x00ea
+#define DSIPORTC_LANE3X		0x00ec
+#define DSIPORTC_LANE3Y		0x00ee
+#define DSIPORTC_LANE4X		0x00f0
+#define DSIPORTC_LANE4Y		0x00f2
+#define DSIPORTC_TE0		0x00f4
+#define TIMER9_PWM_EVT		0x00f6
+#define I2C4_SCL		0x00f8
+#define I2C4_SDA		0x00fa
+#define MCSPI2_CLK		0x00fc
+#define MCSPI2_SIMO		0x00fe
+#define MCSPI2_SOMI		0x0100
+#define MCSPI2_CS0		0x0102
+#define RFBI_DATA15		0x0104
+#define RFBI_DATA14		0x0106
+#define RFBI_DATA13		0x0108
+#define RFBI_DATA12		0x010a
+#define RFBI_DATA11		0x010c
+#define RFBI_DATA10		0x010e
+#define RFBI_DATA9		0x0110
+#define RFBI_DATA8		0x0112
+#define RFBI_DATA7		0x0114
+#define RFBI_DATA6		0x0116
+#define RFBI_DATA5		0x0118
+#define RFBI_DATA4		0x011a
+#define RFBI_DATA3		0x011c
+#define RFBI_DATA2		0x011e
+#define RFBI_DATA1		0x0120
+#define RFBI_DATA0		0x0122
+#define RFBI_WE			0x0124
+#define RFBI_CS0		0x0126
+#define RFBI_A0			0x0128
+#define RFBI_RE			0x012a
+#define RFBI_HSYNC0		0x012c
+#define RFBI_TE_VSYNC0		0x012e
+#define GPIO6_182		0x0130
+#define GPIO6_183		0x0132
+#define GPIO6_184		0x0134
+#define GPIO6_185		0x0136
+#define GPIO6_186		0x0138
+#define GPIO6_187		0x013a
+#define HDMI_CEC		0x013c
+#define HDMI_HPD		0x013e
+#define HDMI_DDC_SCL		0x0140
+#define HDMI_DDC_SDA		0x0142
+#define CSIPORTC_LANE0X		0x0144
+#define CSIPORTC_LANE0Y		0x0146
+#define CSIPORTC_LANE1X		0x0148
+#define CSIPORTC_LANE1Y		0x014a
+#define CSIPORTB_LANE0X		0x014c
+#define CSIPORTB_LANE0Y		0x014e
+#define CSIPORTB_LANE1X		0x0150
+#define CSIPORTB_LANE1Y		0x0152
+#define CSIPORTB_LANE2X		0x0154
+#define CSIPORTB_LANE2Y		0x0156
+#define CSIPORTA_LANE0X		0x0158
+#define CSIPORTA_LANE0Y		0x015a
+#define CSIPORTA_LANE1X		0x015c
+#define CSIPORTA_LANE1Y		0x015e
+#define CSIPORTA_LANE2X		0x0160
+#define CSIPORTA_LANE2Y		0x0162
+#define CSIPORTA_LANE3X		0x0164
+#define CSIPORTA_LANE3Y		0x0166
+#define CSIPORTA_LANE4X		0x0168
+#define CSIPORTA_LANE4Y		0x016a
+#define CAM_SHUTTER		0x016c
+#define CAM_STROBE		0x016e
+#define CAM_GLOBALRESET		0x0170
+#define TIMER11_PWM_EVT		0x0172
+#define TIMER5_PWM_EVT		0x0174
+#define TIMER6_PWM_EVT		0x0176
+#define TIMER8_PWM_EVT		0x0178
+#define I2C3_SCL		0x017a
+#define I2C3_SDA		0x017c
+#define GPIO8_233		0x017e
+#define GPIO8_234		0x0180
+#define ABE_CLKS		0x0182
+#define ABEDMIC_DIN1		0x0184
+#define ABEDMIC_DIN2		0x0186
+#define ABEDMIC_DIN3		0x0188
+#define ABEDMIC_CLK1		0x018a
+#define ABEDMIC_CLK2		0x018c
+#define ABEDMIC_CLK3		0x018e
+#define ABESLIMBUS1_CLOCK	0x0190
+#define ABESLIMBUS1_DATA	0x0192
+#define ABEMCBSP2_DR		0x0194
+#define ABEMCBSP2_DX		0x0196
+#define ABEMCBSP2_FSX		0x0198
+#define ABEMCBSP2_CLKX		0x019a
+#define ABEMCPDM_UL_DATA	0x019c
+#define ABEMCPDM_DL_DATA	0x019e
+#define ABEMCPDM_FRAME		0x01a0
+#define ABEMCPDM_LB_CLK		0x01a2
+#define WLSDIO_CLK		0x01a4
+#define WLSDIO_CMD		0x01a6
+#define WLSDIO_DATA0		0x01a8
+#define WLSDIO_DATA1		0x01aa
+#define WLSDIO_DATA2		0x01ac
+#define WLSDIO_DATA3		0x01ae
+#define UART5_RX		0x01b0
+#define UART5_TX		0x01b2
+#define UART5_CTS		0x01b4
+#define UART5_RTS		0x01b6
+#define I2C2_SCL		0x01b8
+#define I2C2_SDA		0x01ba
+#define MCSPI1_CLK		0x01bc
+#define MCSPI1_SOMI		0x01be
+#define MCSPI1_SIMO		0x01c0
+#define MCSPI1_CS0		0x01c2
+#define MCSPI1_CS1		0x01c4
+#define I2C5_SCL		0x01c6
+#define I2C5_SDA		0x01c8
+#define PERSLIMBUS2_CLOCK	0x01ca
+#define PERSLIMBUS2_DATA	0x01cc
+#define UART6_TX		0x01ce
+#define UART6_RX		0x01d0
+#define UART6_CTS		0x01d2
+#define UART6_RTS		0x01d4
+#define UART3_CTS_RCTX		0x01d6
+#define UART3_RTS_IRSD		0x01d8
+#define UART3_TX_IRTX		0x01da
+#define UART3_RX_IRRX		0x01dc
+#define USBB3_HSIC_STROBE	0x01de
+#define USBB3_HSIC_DATA		0x01e0
+#define SDCARD_CLK		0x01e2
+#define SDCARD_CMD		0x01e4
+#define SDCARD_DATA2		0x01e6
+#define SDCARD_DATA3		0x01e8
+#define SDCARD_DATA0		0x01ea
+#define SDCARD_DATA1		0x01ec
+#define USBD0_HS_DP		0x01ee
+#define USBD0_HS_DM		0x01f0
+#define I2C1_PMIC_SCL		0x01f2
+#define I2C1_PMIC_SDA		0x01f4
+#define USBD0_SS_RX		0x01f6
 
-#define WKUP_REVISION		0x0000
-#define WKUP_HWINFO		0x0004
-#define WKUP_SYSCONFIG		0x0010
-#define PAD0_SIM_IO		0x0040
-#define PAD1_SIM_CLK		0x0042
-#define PAD0_SIM_RESET		0x0044
-#define PAD1_SIM_CD		0x0046
-#define PAD0_SIM_PWRCTRL		0x0048
-#define PAD1_SR_SCL		0x004A
-#define PAD0_SR_SDA		0x004C
-#define PAD1_FREF_XTAL_IN		0x004E
-#define PAD0_FREF_SLICER_IN	0x0050
-#define PAD1_FREF_CLK_IOREQ	0x0052
-#define PAD0_FREF_CLK0_OUT		0x0054
-#define PAD1_FREF_CLK3_REQ		0x0056
-#define PAD0_FREF_CLK3_OUT		0x0058
-#define PAD1_FREF_CLK4_REQ		0x005A
-#define PAD0_FREF_CLK4_OUT		0x005C
-#define PAD1_SYS_32K		0x005E
-#define PAD0_SYS_NRESPWRON		0x0060
-#define PAD1_SYS_NRESWARM		0x0062
-#define PAD0_SYS_PWR_REQ		0x0064
-#define PAD1_SYS_PWRON_RESET	0x0066
-#define PAD0_SYS_BOOT6		0x0068
-#define PAD1_SYS_BOOT7		0x006A
-#define PAD0_JTAG_NTRST		0x006C
-#define PAD1_JTAG_TCK		0x006D
-#define PAD0_JTAG_RTCK		0x0070
-#define PAD1_JTAG_TMS_TMSC		0x0072
-#define PAD0_JTAG_TDI		0x0074
-#define PAD1_JTAG_TDO		0x0076
-#define PADCONF_WAKEUPEVENT_0	0x007C
-#define CONTROL_SMART1NOPMIO_PADCONF_0		0x05A0
-#define CONTROL_SMART1NOPMIO_PADCONF_1		0x05A4
-#define PADCONF_MODE		0x05A8
-#define CONTROL_XTAL_OSCILLATOR			0x05AC
-#define CONTROL_CONTROL_I2C_2			0x0604
-#define CONTROL_CONTROL_JTAG			0x0608
-#define CONTROL_CONTROL_SYS			0x060C
-#define CONTROL_SPARE_RW		0x0614
-#define CONTROL_SPARE_R		0x0618
-#define CONTROL_SPARE_R_C0		0x061C
+#define LLIA_WAKEREQIN		0x0040
+#define LLIB_WAKEREQIN		0x0042
+#define DRM_EMU0		0x0044
+#define DRM_EMU1		0x0046
+#define JTAG_NTRST		0x0048
+#define JTAG_TCK		0x004a
+#define JTAG_RTCK		0x004c
+#define JTAG_TMSC		0x004e
+#define JTAG_TDI		0x0050
+#define JTAG_TDO		0x0052
+#define SYS_32K			0x0054
+#define FREF_CLK_IOREQ		0x0056
+#define FREF_CLK0_OUT		0x0058
+#define FREF_CLK1_OUT		0x005a
+#define FREF_CLK2_OUT		0x005c
+#define FREF_CLK2_REQ		0x005e
+#define FREF_CLK1_REQ		0x0060
+#define SYS_NRESPWRON		0x0062
+#define SYS_NRESWARM		0x0064
+#define SYS_PWR_REQ		0x0066
+#define SYS_NIRQ1		0x0068
+#define SYS_NIRQ2		0x006a
+#define SR_PMIC_SCL		0x006c
+#define SR_PMIC_SDA		0x006e
+#define SYS_BOOT0		0x0070
+#define SYS_BOOT1		0x0072
+#define SYS_BOOT2		0x0074
+#define SYS_BOOT3		0x0076
+#define SYS_BOOT4		0x0078
+#define SYS_BOOT5		0x007a
 
 #endif /* _MUX_OMAP5_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index d811d6ec23..e3f55d2020 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -98,17 +98,6 @@
 #define TCLR_AR			(0x1 << 1)
 #define TCLR_PRE		(0x1 << 5)
 
-/*
- * PRCM
- */
-
-/* PRM */
-#define PRM_BASE		0x4AE06000
-#define PRM_DEVICE_BASE		(PRM_BASE + 0x1B00)
-
-#define PRM_RSTCTRL		PRM_DEVICE_BASE
-#define PRM_RSTCTRL_RESET	0x01
-
 /* Control Module */
 #define LDOSRAM_ACTMODE_VSET_IN_MASK	(0x1F << 5)
 #define LDOSRAM_VOLT_CTRL_OVERRIDE	0x0401040f
@@ -125,9 +114,10 @@
 /* CONTROL_EFUSE_2 */
 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1		0x00ffc000
 
-#define MMC1_PWRDNZ					(1 << 26)
-#define MMC1_PBIASLITE_PWRDNZ				(1 << 22)
-#define MMC1_PBIASLITE_VMODE				(1 << 21)
+#define SDCARD_PWRDNZ					(1 << 26)
+#define SDCARD_BIAS_HIZ_MODE				(1 << 25)
+#define SDCARD_BIAS_PWRDNZ				(1 << 22)
+#define SDCARD_PBIASLITE_VMODE				(1 << 21)
 
 #ifndef __ASSEMBLY__
 
@@ -136,32 +126,117 @@ struct s32ktimer {
 	unsigned int s32k_cr;	/* 0x10 */
 };
 
-struct omap4_sys_ctrl_regs {
-	unsigned int pad1[129];
-	unsigned int control_id_code;			/* 0x4A002204 */
-	unsigned int pad11[22];
-	unsigned int control_std_fuse_opp_bgap;		/* 0x4a002260 */
-	unsigned int pad2[47];
-	unsigned int control_ldosram_iva_voltage_ctrl;	/* 0x4A002320 */
-	unsigned int control_ldosram_mpu_voltage_ctrl;	/* 0x4A002324 */
-	unsigned int control_ldosram_core_voltage_ctrl;	/* 0x4A002328 */
-	unsigned int pad3[260277];
-	unsigned int control_pbiaslite;			/* 0x4A100600 */
-	unsigned int pad4[63];
-	unsigned int control_efuse_1;			/* 0x4A100700 */
-	unsigned int control_efuse_2;			/* 0x4A100704 */
+#define DEVICE_TYPE_SHIFT 0x6
+#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
+#define DEVICE_GP 0x3
+
+struct omap_sys_ctrl_regs {
+	u32 pad0[77]; /* 0x4A002000 */
+	u32 control_status; /* 0x4A002134 */
+	u32 pad1[794]; /* 0x4A002138 */
+	u32 control_paconf_global; /* 0x4A002DA0 */
+	u32 control_paconf_mode;  /* 0x4A002DA4 */
+	u32 control_smart1io_padconf_0; /* 0x4A002DA8 */
+	u32 control_smart1io_padconf_1; /* 0x4A002DAC */
+	u32 control_smart1io_padconf_2; /* 0x4A002DB0 */
+	u32 control_smart2io_padconf_0; /* 0x4A002DB4 */
+	u32 control_smart2io_padconf_1; /* 0x4A002DB8 */
+	u32 control_smart2io_padconf_2; /* 0x4A002DBC */
+	u32 control_smart3io_padconf_0; /* 0x4A002DC0 */
+	u32 control_smart3io_padconf_1; /* 0x4A002DC4 */
+	u32 pad2[14];
+	u32 control_pbias; /* 0x4A002E00 */
+	u32 control_i2c_0; /* 0x4A002E04 */
+	u32 control_camera_rx; /* 0x4A002E08 */
+	u32 control_hdmi_tx_phy; /* 0x4A002E0C */
+	u32 control_uniportm; /* 0x4A002E10 */
+	u32 control_dsiphy; /* 0x4A002E14 */
+	u32 control_mcbsplp; /* 0x4A002E18 */
+	u32 control_usb2phycore; /* 0x4A002E1C */
+	u32 control_hdmi_1; /*0x4A002E20*/
+	u32 control_hsi; /*0x4A002E24*/
+	u32 pad3[2];
+	u32 control_ddr3ch1_0; /*0x4A002E30*/
+	u32 control_ddr3ch2_0; /*0x4A002E34*/
+	u32 control_ddrch1_0;	/*0x4A002E38*/
+	u32 control_ddrch1_1;	/*0x4A002E3C*/
+	u32 control_ddrch2_0;	/*0x4A002E40*/
+	u32 control_ddrch2_1;	/*0x4A002E44*/
+	u32 control_lpddr2ch1_0; /*0x4A002E48*/
+	u32 control_lpddr2ch1_1; /*0x4A002E4C*/
+	u32 control_ddrio_0;  /*0x4A002E50*/
+	u32 control_ddrio_1;  /*0x4A002E54*/
+	u32 control_ddrio_2;  /*0x4A002E58*/
+	u32 control_hyst_1; /*0x4A002E5C*/
+	u32 control_usbb_hsic_control; /*0x4A002E60*/
+	u32 control_c2c; /*0x4A002E64*/
+	u32 control_core_control_spare_rw; /*0x4A002E68*/
+	u32 control_core_control_spare_r; /*0x4A002E6C*/
+	u32 control_core_control_spare_r_c0; /*0x4A002E70*/
+	u32 control_srcomp_north_side; /*0x4A002E74*/
+	u32 control_srcomp_south_side; /*0x4A002E78*/
+	u32 control_srcomp_east_side; /*0x4A002E7C*/
+	u32 control_srcomp_west_side; /*0x4A002E80*/
+	u32 control_srcomp_code_latch; /*0x4A002E84*/
+	u32 pad4[3680198];
+	u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */
+	u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */
+	u32 control_padconf_mode; /* 0x4AE0CDA8 */
+	u32 control_xtal_oscillator; /* 0x4AE0CDAC */
+	u32 control_i2c_2; /* 0x4AE0CDB0 */
+	u32 control_ckobuffer; /* 0x4AE0CDB4 */
+	u32 control_wkup_control_spare_rw; /* 0x4AE0CDB8 */
+	u32 control_wkup_control_spare_r; /* 0x4AE0CDBC */
+	u32 control_wkup_control_spare_r_c0; /* 0x4AE0CDC0 */
+	u32 control_srcomp_east_side_wkup; /* 0x4AE0CDC4 */
+	u32 control_efuse_1; /* 0x4AE0CDC8 */
+	u32 control_efuse_2; /* 0x4AE0CDCC */
+	u32 control_efuse_3; /* 0x4AE0CDD0 */
+	u32 control_efuse_4; /* 0x4AE0CDD4 */
+	u32 control_efuse_5; /* 0x4AE0CDD8 */
+	u32 control_efuse_6; /* 0x4AE0CDDC */
+	u32 control_efuse_7; /* 0x4AE0CDE0 */
+	u32 control_efuse_8; /* 0x4AE0CDE4 */
+	u32 control_efuse_9; /* 0x4AE0CDE8 */
+	u32 control_efuse_10; /* 0x4AE0CDEC */
+	u32 control_efuse_11; /* 0x4AE0CDF0 */
+	u32 control_efuse_12; /* 0x4AE0CDF4 */
+	u32 control_efuse_13; /* 0x4AE0CDF8 */
 };
 
-struct control_lpddr2io_regs {
-	unsigned int control_lpddr2io1_0;
-	unsigned int control_lpddr2io1_1;
-	unsigned int control_lpddr2io1_2;
-	unsigned int control_lpddr2io1_3;
-	unsigned int control_lpddr2io2_0;
-	unsigned int control_lpddr2io2_1;
-	unsigned int control_lpddr2io2_2;
-	unsigned int control_lpddr2io2_3;
-};
+/* Output impedance control */
+#define ds_120_ohm	0x0
+#define ds_60_ohm	0x1
+#define ds_45_ohm	0x2
+#define ds_30_ohm	0x3
+#define ds_mask		0x3
+
+/* Slew rate control */
+#define sc_slow		0x0
+#define sc_medium	0x1
+#define sc_fast		0x2
+#define sc_na		0x3
+#define sc_mask		0x3
+
+/* Target capacitance control */
+#define lb_5_12_pf	0x0
+#define lb_12_25_pf	0x1
+#define lb_25_50_pf	0x2
+#define lb_50_80_pf	0x3
+#define lb_mask		0x3
+
+#define usb_i_mask	0x7
+
+#define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN   0x80828082
+#define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200
+#define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421
+#define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
+#define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
+
+#define EFUSE_1 0x45145100
+#define EFUSE_2 0x45145100
+#define EFUSE_3 0x45145100
+#define EFUSE_4 0x45145100
 #endif /* __ASSEMBLY__ */
 
 /*
@@ -169,7 +244,7 @@ struct control_lpddr2io_regs {
  * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
  * at 0x40304000(EMU base) so that our code works for both EMU and GP
  */
-#define NON_SECURE_SRAM_START	0x40304000
+#define NON_SECURE_SRAM_START	0x40300000
 #define NON_SECURE_SRAM_END	0x40320000	/* Not inclusive */
 /* base address for indirect vectors (internal boot mode) */
 #define SRAM_ROM_VECT_BASE	0x4031F000
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 40a7c57489..8396a22141 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -55,6 +55,8 @@ u32 omap_sdram_size(void);
 u32 cortex_rev(void);
 void init_omap_revision(void);
 void do_io_settings(void);
+void omap_vc_init(u16 speed_khz);
+int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
 
 /*
  * This is used to verify if the configuration header
@@ -113,10 +115,4 @@ static inline u32 omap_hw_init_context(void)
 #endif
 }
 
-static inline u32 omap_revision(void)
-{
-	extern u32 *const omap5_revision;
-	return *omap5_revision;
-}
-
 #endif
diff --git a/arch/arm/include/asm/arch-rda/chip_id.h b/arch/arm/include/asm/arch-rda/chip_id.h
new file mode 100644
index 0000000000..765b43d9d6
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/chip_id.h
@@ -0,0 +1,46 @@
+/////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//            Copyright (C) 2003-2007, Coolsand Technologies, Inc.            //
+//                            All Rights Reserved                             //
+//                                                                            //
+//      This source code is the property of Coolsand Technologies and is      //
+//      confidential.  Any  modification, distribution,  reproduction or      //
+//      exploitation  of  any content of this file is totally forbidden,      //
+//      except  with the  written permission  of  Coolsand Technologies.      //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//  $HeadURL: http://svn.rdamicro.com/svn/developing1/Sources/chip/branches/8810/defs/include/chip_id.h $ //
+//    $Author: huazeng $                                                        // 
+//    $Date: 2013-04-16 15:10:28 +0800 (Tue, 16 Apr 2013) $                     //   
+//    $Revision: 20171 $                                                          //   
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+/// @file chip_id.h
+/// This file contains the ID of the supported chips
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+
+#ifndef _CHIP_ID_H_
+#define _CHIP_ID_H_
+
+#define CHIP_ASIC_ID_DEPRECATED_JADE        1
+#define CHIP_ASIC_ID_DEPRECATED_GRANITE     2
+#define CHIP_ASIC_ID_GREENSTONE             3
+#define CHIP_ASIC_ID_DEPRECATED_NEPHRITE    4
+#define CHIP_ASIC_ID_DEPRECATED_EMERALD     5
+#define CHIP_ASIC_ID_GALLITE                6
+#define CHIP_ASIC_ID_DEPRECATED_ESPERITE    7
+#define CHIP_ASIC_ID_8808                   8
+#define CHIP_ASIC_ID_8809                   9
+#define CHIP_ASIC_ID_8810                   10
+#define CHIP_ASIC_ID_8809P                  11
+#define CHIP_ASIC_ID_8810E                  12
+#define CHIP_ASIC_ID_8850                   13
+
+#define CHIP_ASIC_ID_QTY                    13
+
+#endif // _CHIP_ID_H_
+
+
diff --git a/arch/arm/include/asm/arch-rda/cs_types.h b/arch/arm/include/asm/arch-rda/cs_types.h
new file mode 100644
index 0000000000..de3ade7ea3
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/cs_types.h
@@ -0,0 +1,281 @@
+////////////////////////////////////////////////////////////////////////////////
+//        Copyright (C) 2002-2006, Coolsand Technologies, Inc.
+//                       All Rights Reserved
+//
+// This source code is property of Coolsand. The information contained in this
+// file is confidential. Distribution, reproduction, as well as exploitation,
+// or transmisison of any content of this file is not allowed except if
+// expressly permitted.Infringements result in damage claims!
+//
+// FILENAME: cs_types.h
+//
+// DESCRIPTION:
+//   This file defines all basic data types used by all files in Coolsand
+//   development environment.
+//
+// REVISION HISTORY:
+//   NAME            DATE            REMAKS
+//   SHK           2006-10-29     Created initial version 1.0
+//   Romuald       2007-04-25     Added PRIVATE, PROTECTED, REG16 and REG32
+//   zhaoyong      2008-08-08     clean up
+////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __CS_TYPE_H__
+#define __CS_TYPE_H__
+
+#define MAX_INT8                    127
+#define MIN_INT8                    (-MAX_INT8 - 1)
+#define MAX_UINT8                   255
+#define MIN_UINT8                   0
+#define MAX_INT16                   32767
+#define MIN_INT16                   (-MAX_INT16 - 1)
+#define MAX_UINT16                  65535
+#define MIN_UINT16                  0
+#define MAX_INT32                   2147483647L
+#define MIN_INT32                   (-MAX_INT32 - 1)
+#define MAX_UINT32                  4294967295U
+#define MIN_UINT32                  0U
+#ifdef WITH_LONG_LONG
+#define INTMAX_MAX                  0x7fffffffffffffff
+#define INTMAX_MIN                  -(0x7fffffffffffffff-1)
+#define UINTMAX_MAX                 0xffffffffffffffff
+#else
+#define INTMAX_MAX                  0x7fffffff
+#define INTMAX_MIN                  -(0x7fffffff-1)
+#define UINTMAX_MAX                 0xffffffff
+#endif
+#define INT_MAX                     (char *)(1<<31)
+#define LONG_MAX                    0x7fffffff
+#define LONG_MIN                    -(0x7fffffff-1)
+#define ULONG_MAX                   0xffffffff
+
+
+typedef unsigned char               u8;
+typedef unsigned short              u16;
+typedef unsigned int		        u32;
+//typedef char                        s8;
+typedef short                       s16;
+//typedef long                        s32;
+#ifdef __cplusplus
+#else
+typedef unsigned char               bool;
+#endif
+
+typedef char                        ascii;
+typedef unsigned char               byte;           /*  unsigned 8-bit data     */
+typedef unsigned short              word;           /*  unsigned 16-bit data    */
+typedef unsigned long               dword;          /*  unsigned 32-bit data    */
+typedef unsigned char               uint8;
+typedef signed char                 int8;
+typedef unsigned short int          uint16;
+typedef signed short int            int16;
+typedef unsigned int                uint32;
+typedef signed int                  int32;
+typedef char                        boolean;
+typedef unsigned int                size_t;
+typedef int                         ssize_t;
+#ifdef WITH_LONG_LONG
+typedef unsigned long long          uintmax_t;
+typedef long long                   intmax_t;
+#else
+typedef unsigned long               uintmax_t;
+typedef long                        intmax_t;
+#endif
+
+typedef unsigned long               UINT32;
+typedef unsigned short              UINT16;
+typedef long                        INT32;
+typedef short                       INT16;
+typedef unsigned char               UINT8;
+typedef char                        INT8;
+#if defined(_M_IX86)
+#pragma warning(disable:4142)
+typedef __int64                     UINT64;
+typedef __int64                     INT64;
+#else
+typedef unsigned long long          UINT64;
+typedef long long                   INT64;
+#endif
+typedef unsigned char               BOOL;
+typedef short                       WCHAR;
+typedef char                        CHAR;
+typedef unsigned char               BYTE;
+typedef float                       FLOAT;
+typedef double                      DOUBLE;
+typedef UINT32                      HANDLE;
+typedef UINT8*                      PUINT8;
+typedef UINT32*                     PUINT32;
+typedef INT32*                      PINT32;
+typedef UINT16*                     PUINT16;
+typedef INT16*                      PINT16;
+typedef CHAR *                      PCHAR;
+typedef void*                       PVOID;
+typedef unsigned short              WORD;
+typedef unsigned long               DWORD;  /* actually long, but this should be okay */
+typedef volatile unsigned char      REG8;
+typedef volatile unsigned short     REG16;
+typedef volatile unsigned int       REG32;
+typedef int                         INT;
+typedef char                        S8;
+typedef char *                      PS8;
+typedef unsigned char               U8;
+typedef unsigned char   *           PU8;
+typedef unsigned short              pBOOL; 
+typedef short int                   S16; 
+typedef short int *                 PS16; 
+typedef unsigned short int          U16; 
+typedef unsigned short int *        PU16;
+typedef int                         S32;
+typedef int *                       PS32;
+typedef unsigned int                U32;
+typedef unsigned int *              PU32;
+typedef float                       float32;
+typedef unsigned long long          U64;
+typedef long long                   S64;
+
+#define PUBLIC
+#define SRVAPI
+#define PROTECTED
+#define LOCAL                       static
+#define PRIVATE                     static
+#define EXPORT                      extern
+#define REG                         register
+#define CONST                       const
+#define VOLATILE                    volatile
+#define VOID                        void
+#define INLINE                      static inline // Do compiler directives
+
+#ifdef ENABLE_DEPRECATED
+#define DEPRECATED __attribute__ ((deprecated))
+#else
+#define DEPRECATED
+#endif /* ENABLE_DEPRECATED */
+
+#define TRUE                        (1==1)
+#define FALSE                       (1==0)
+//#define NULL                        0
+#define CS_NULL                     (void*)0
+#define NIL                         0
+#define CS_NIL                      0
+#define HNULL                       0
+#define NULL_CHAR                   '\0'
+
+#define OFFSETOF(s,m)                   ((UINT32)&(((s *)0)->m)) // Get the address offset of the specified member.
+//#define ALIGN(val,exp)                  (((val) + ((exp)-1)) & ~((exp)-1))
+//#define ARRAY_SIZE(a)                   (sizeof(a)/sizeof(a[0]))
+#define LAST_ELEMENT(x)                 (&x[ARRAY_SIZE(x)-1])
+#define TCHAR_SIZEOF(sz)                (sizeof(sz)/sizeof(TCHAR))
+#define BOUND(x, min, max)              ( (x) < (min) ? (min) : ((x) > (max) ? (max):(x)) )
+#define ROUND_SIZEOF(t)                 ((sizeof(t)+sizeof(int)-1)&~(sizeof(int)-1))
+#define IS_32BIT_ALIGN(nAdd)            ((UINT32)(((UINT32)(nAdd)) & 0x3)==0)
+#define IS_16_ALIGN(nSize)              ((UINT32)(((UINT32)(nSize))& 0x0f) == 0)
+#define S_LAST_MEMBER_ADDR(ptr, type)   ((UINT8*)(ptr) + SIZEOF(type))
+#define S_MEMBER_ADDR(s_prt, offset)    ((UINT8*)(s_prt) + offset)
+#define MSB(x)                          (((x) >> 8) & 0xff) // most signif byte of 2-byte integer
+#define LSB(x)                          ((x) & 0xff)        // least signif byte of 2-byte integer
+#define MAKE_WORD(p)                    (((UINT16)(p)[0] << 8) | (UINT16)(p)[1])
+#define MAKE_DWORD(p)                   (((UINT32)(p)[0] << 24) | ((UINT32)(p)[1] << 16) | ((UINT32)(p)[2] << 8) | (UINT32)(p)[3])
+#define SWAP16(p)                       (((UINT16)((UINT16*)(p))[1] << 8) | (UINT16)((UINT16*)(p))[0])
+#define SWAP32(p)                       (((UINT32)((UINT32*)(p))[3] << 24) | ((UINT32)((UINT32*)(p))[2] << 16) | ((UINT32)((UINT32*)(p))[1] << 8) | (UINT32)((UINT32*)(p))[0])
+#define SWAPT(v1,v2,typ)                {typ v; v  = v1; v1 = v2; v2 = v;}
+
+/* align size withe the specified bits.*/
+#define ALIGN_SIZE(x, align)            (((UINT32)(x)+align-1)&~(align-1))
+#define Arg(arg, type)                  (*(type *)(arg))
+#define NextArg(arg, type)              ((arg) = (TCHAR *)(arg) + roundedsizeof(type))
+// Get the data from "arg" to "in".
+#define ARG_IN(r,arg,type)              (memcpy(&(r), (type *) (arg), sizeof (arg)))
+// Put the data from "w" to "arg".
+#define ARG_OUT(arg, w, type)           (memcpy((type *) (arg), &(w), sizeof (w)))
+#define ABS(x) ((x<0)?(-(x)):(x))
+//#define MAX(a,b)                        (((a) > (b)) ? (a) : (b))
+//#define MIN(a,b)                        (((a) < (b)) ? (a) : (b))
+#define MAKEINT16(a, b)                 ((INT16)(((UINT8)(a)) | ((INT16)((UINT8)(b))) << 8))
+#define MAKEINT32(a, b)                 ((INT32)(((UINT16)(a)) | ((INT32)((UINT16)(b))) << 16))
+#define MAKEUINT16(a, b)                ((UINT16)(((UINT8)(a)) | ((UINT16)((UINT8)(b))) << 8))
+#define MAKEUINT32(a, b)                ((UINT32)(((UINT16)(a)) | ((UINT32)((UINT16)(b))) << 16))
+#define LOINT8(w)                       ((INT8)(w))
+#define HIINT8(w)                       ((INT8)((UINT16)(w) >> 8))
+#define LOUINT8(w)                      ((UINT8)(w))
+#define HIUINT8(w)                      ((UINT8)((UINT16)(w) >> 8))
+#define LOINT16(l)                      ((INT16)(l))
+#define HIINT16(l)                      ((INT16)((UINT32)(l) >> 16))
+#define LOUINT16(l)                     ((UINT16)(l))
+#define HIUINT16(l)                     ((UINT16)((UINT32)(l) >> 16))
+//#define offsetof(TYPE, MEMBER)          ((u32) &((TYPE *)0)->MEMBER)
+#define offsetofvar(VAR, MEMBER)        (((u32) &(VAR.MEMBER)) - ((u32) &VAR))
+/* Remove const cast-away warnings from gcc -Wcast-qual */
+#define __UNCONST(a)                    ((void *)(unsigned long)(const void *)(a))
+#define __P(protos)  protos
+//#define ALIGN(val,exp)                  (((val) + ((exp)-1)) & ~((exp)-1))
+//#define ARRAY_SIZE(a)                   (sizeof(a)/sizeof(a[0]))
+#define LAST_ELEMENT(x)                 (&x[ARRAY_SIZE(x)-1])
+#define TCHAR_SIZEOF(sz)                (sizeof(sz)/sizeof(TCHAR))
+#define BOUND(x, min, max)              ( (x) < (min) ? (min) : ((x) > (max) ? (max):(x)) )
+#define roundedsizeof(t)                ((sizeof(t)+sizeof(int)-1)&~(sizeof(int)-1))
+#define IS_32BIT_ALIGN(nAdd)            ((UINT32)(((UINT32)(nAdd)) & 0x3)==0)
+#define IS_16_ALIGN(nSize)              ((UINT32)(((UINT32)(nSize))& 0x0f) == 0)
+#define ABS(x)                          ((x<0)?(-(x)):(x))
+
+// Set a breakpoint, to enter GDB.
+#define BREAKPOINT                      asm volatile("break 1\n\tnop\n\tnop\n\tnop")
+#define BKPT                            BREAKPOINT;
+#define GDB_FUNC_IN_RAM                 __attribute__((section(".ram")))
+
+// Preprocessor macros.
+#define STRINGIFY_VALUE(s) STRINGIFY(s)
+#define STRINGIFY(s) #s
+
+//#define cpu_to_le32(x)		(x)
+//#define le32_to_cpu(x)		(x)
+
+#if defined(UNICODE)
+#undef SIZEOF
+#define SIZEOF(type) (sizeof(type)/sizeof(UINT16))
+typedef UINT16* PSTR;
+typedef CONST UINT16* PCSTR;
+typedef UINT16 TCHAR;
+#undef TEXT
+#define TEXT(x) L ## x
+#else
+#undef SIZEOF
+#define SIZEOF(type) sizeof(type)
+typedef UINT8* PSTR;
+typedef CONST UINT8* PCSTR;
+typedef UINT8 TCHAR;
+typedef UINT8* PTCHAR;
+#undef TEXT
+#define TEXT(x) x
+#endif
+
+#define CPP_START  extern "C" {
+#define CPP_END    }
+#define TSTXT(x)  x
+
+/// From http://www.ibm.com/developerworks/linux/library/l-gcc-hacks/
+/// Macro to use in a if statement to tell the compiler this branch
+/// is likely taken, and optimize accordingly.
+#define LIKELY(x)   __builtin_expect(!!(x), 1)
+/// Macro to use in a if statement to tell the compiler this branch
+/// is unlikely take, and optimize accordingly.
+#define UNLIKELY(x) __builtin_expect(!!(x), 0)
+
+
+/// For packing structure
+#define PACKED      __attribute__((packed))
+
+/// To describe alignment
+#define ALIGNED(a)  __attribute__((aligned(a)))
+
+// C++ needs to know that types and declarations are C, not C++.
+#ifdef __cplusplus
+# define EXTERN_C_START extern "C" {
+# define EXTERN_C_END }
+#else
+# define EXTERN_C_START
+# define EXTERN_C_END
+#endif
+
+
+#endif // __CS_TYPE_H__
+
diff --git a/arch/arm/include/asm/arch-rda/defs_mdcom.h b/arch/arm/include/asm/arch-rda/defs_mdcom.h
new file mode 100644
index 0000000000..748b743fcf
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/defs_mdcom.h
@@ -0,0 +1,160 @@
+#ifndef  _DEFS_MDCOM_H_
+#define  _DEFS_MDCOM_H_
+
+#include <asm/arch/hardware.h>
+
+#ifdef RDA_MDCOM_DEBUG
+#define rdamddbg(fmt,args...)	printf (fmt ,##args)
+#else
+#define rdamddbg(fmt,args...)
+#endif /* RDA_MDCOM_DEBUG */
+
+/*
+ * Convert modem address to AP address
+ */
+#define RDA_ADD_M2A(x)		(((x) & 0x0FFFFFFF) | 0x10000000)
+
+/*
+ * Modem boot context address
+ */
+#define RDA_BOOT_CTX_ADD	0x11C00100
+
+/*
+ * Modem map pointer
+ */
+#define RDA_MODEM_MAP_PTR	0x11C0027C
+#define RDA_MODEM_MAP_QTY	0x1A
+
+/*
+ * Modem RAM info
+ */
+#if defined(_TGT_MODEM_MEM_SIZE) && (_TGT_MODEM_MEM_SIZE > 0)
+#define RDA_MODEM_RAM_BASE	(PHYS_SDRAM_1 + ((_TGT_MODEM_MEM_BASE) << 20))
+#define RDA_MODEM_RAM_SIZE	(_TGT_MODEM_MEM_SIZE << 20)
+#define RDA_GSM_MODEM_RAM_END (RDA_MODEM_RAM_BASE + (_TGT_MODEM_GSM_MEM_SIZE << 20))
+#define RDA_MODEM_RAM_END	RDA_GSM_MODEM_RAM_END
+#ifdef _TGT_MODEM_WCDMA_MEM_SIZE
+#define RDA_WCDMA_MODEM_RAM_END (RDA_GSM_MODEM_RAM_END + (_TGT_MODEM_WCDMA_MEM_SIZE << 20))
+#endif
+#else
+#define RDA_MODEM_RAM_BASE	RDA_MD_PSRAM_BASE
+#define RDA_MODEM_RAM_SIZE	RDA_MD_PSRAM_SIZE
+#define RDA_MODEM_RAM_END	(RDA_MODEM_RAM_BASE + RDA_MODEM_RAM_SIZE)
+#endif
+
+#define RDA_MODEM_INTSRAM_BASE	(0x11C00000)
+#define RDA_MODEM_INTSRAM_SIZE	(0x18000)
+#define RDA_MODEM_INTSRAM_END	\
+	(RDA_MODEM_INTSRAM_BASE + RDA_MODEM_INTSRAM_SIZE)
+
+/*
+ * HEARTBEAT data
+ */
+#define RDA_AP_MBX_HEARTBEAT_ADD	(RDA_MD_MAILBOX_BASE + 0)
+
+/*
+ * CHANNEL
+ */
+#define RDA_MDCOM_CHN_AT_HEAD_ADD_READ		0x00200430
+#define RDA_MDCOM_CHN_AT_HEAD_ADD_WRITE		0x00200C40
+#define RDA_MDCOM_CHN_AT_BUF_ADD_READ		0x00200440
+#define RDA_MDCOM_CHN_AT_BUF_ADD_WRITE		0x00200C50
+#define RDA_MDCOM_CHN_AT_BUF_LEN_READ		2048
+#define RDA_MDCOM_CHN_AT_BUF_LEN_WRITE		2048
+
+#define RDA_MDCOM_CHN_SYS_HEAD_ADD_READ		0x00200010
+#define RDA_MDCOM_CHN_SYS_HEAD_ADD_WRITE	0x00200220
+#define RDA_MDCOM_CHN_SYS_BUF_ADD_READ		0x00200020
+#define RDA_MDCOM_CHN_SYS_BUF_ADD_WRITE		0x00200230
+#define RDA_MDCOM_CHN_SYS_BUF_LEN_READ		512
+#define RDA_MDCOM_CHN_SYS_BUF_LEN_WRITE		512
+
+#define RDA_MDCOM_CHN_TRACE_HEAD_ADD_READ	0x00201450
+#define RDA_MDCOM_CHN_TRACE_HEAD_ADD_WRITE	0x00201860
+#define RDA_MDCOM_CHN_TRACE_BUF_ADD_READ	0x00201460
+#define RDA_MDCOM_CHN_TRACE_BUF_ADD_WRITE	0x00201870
+#define RDA_MDCOM_CHN_TRACE_BUF_LEN_READ	1024
+#define RDA_MDCOM_CHN_TRACE_BUF_LEN_WRITE	512
+
+/*
+ * MAGIC NUMBER
+ */
+#define RDA_AP_MBX_MAGIC_NUMBER_ADD	(RDA_MD_MAILBOX_BASE + 0x1A70)
+#define RDA_MAGIC_SYSTEM_STARTED_FLAG	0x057a67ed
+#define RDA_MAGIC_MODEM_CRASH_FLAG	0x9db09db0
+#define RDA_MAGIC_FACT_UPD_CMD_FLAG	0xfac40c3d
+#define RDA_MAGIC_FACT_UPD_TYPE_FLAG	0x496efa00
+#define RDA_MAGIC_FACT_UPD_TYPE_FLAG_MASK	0xFFFFFF00
+#define RDA_MAGIC_FACT_UPD_TYPE_CALIB	0x1
+#define RDA_MAGIC_FACT_UPD_TYPE_FACT	0x2
+#define RDA_MAGIC_FACT_UPD_TYPE_AP_FACT	0x4
+
+/*
+ * LOG BUFFER INFO
+ */
+#define RDA_AP_MBX_LOG_BUF_INFO_ADD	(RDA_MD_MAILBOX_BASE + 0x1A80)
+#define RDA_AP_MBX_MAX_MODEM_LOG_LEN	0x10000
+#define RDA_AP_MBX_MAX_MODEM_EXC_LEN	0x1000
+
+
+/*
+ * BOOT_HST_MONITOR_X_CTX_T
+ * This structure is  used by the HOST execution command
+ * It can store PC, SP, param ptr and returned value ptr
+ * The command type field could reveal itself as really
+ * relevant in the future
+ */
+typedef volatile struct {
+	u32	cmdType;         // 0x00000000
+	u32	pc;              // 0x00000004
+	u32	sp;              // 0x00000008
+	void*	param;           // 0x0000000c
+	void*	returnedValue;   // 0x00000010
+} RDA_BOOT_HST_MONITOR_X_CTX_T;
+
+typedef struct
+{
+	u32	revision;	//0x00000000
+	u32	number;		//0x00000004
+	u32	date;		//0x00000008
+	u8*	string;		//0x0000000C
+} RDA_MODEM_MAP_VERSION_T; //Size : 0x10
+
+typedef struct
+{
+    RDA_MODEM_MAP_VERSION_T*	version;	//0x00000000
+    void*			access;		//0x00000004
+} RDA_MODEM_MAP_MODULE_T; //Size : 0x8
+
+typedef struct
+{
+	/* Modem heartbeat counter */
+	volatile u32 bpCounter;
+	/* AP heartbeat counter */
+	volatile u32 apCounter;
+	/* System reset cause */
+	u32 resetCause;
+	/* Communication interface version */
+	u32 version;
+} RDA_AP_MBX_HEARTBEAT_T;
+
+typedef struct {
+	u32 sysStarted;
+	u32 modemCrashed;
+	u32 factUpdateCmd;
+	u32 factUpdateType;
+} RDA_AP_MBX_MAGIC_NUMBER_T;
+
+typedef struct {
+	u32 modemAddr;
+	u32 modemLen;
+	u32 modemExcAddr;
+	u32 modemExcLen;
+	struct {
+		u32 apAddr;
+		u32 apLen;
+		u32 reserved[2];
+	} apLog[5];
+} RDA_AP_MBX_LOG_BUF_INFO_T;
+
+#endif //  _DEFS_MDCOM_H_
diff --git a/arch/arm/include/asm/arch-rda/dma.h b/arch/arm/include/asm/arch-rda/dma.h
new file mode 100644
index 0000000000..8b8f553b2a
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/dma.h
@@ -0,0 +1,73 @@
+/***************************************************************
+*
+* Copyright(C) RDA Micro Company.,2012
+* All Rights Reserved. Confidential
+*
+****************************************************************
+*
+* Project: RDA8810
+* File Name: arch/arm/include/asm/dma.h
+*
+* Author: Jason Tao
+* Creation Date: 2012-11-15
+*
+*****************************************************************
+*
+* Definition of registers of DMA
+*
+*****************************************************************
+*/
+
+
+#ifndef __DMA_H__
+#define __DMA_H__
+
+#include <asm/types.h>
+
+#define BIT(x)  (1UL << (x))
+
+#define RDA_DMA_CHAN_REG    0x00
+
+#define RDA_DMA_STATUS_REG  0x04
+#define RDA_DMA_STA_INT      BIT(2)
+
+#define RDA_DMA_CTL_REG     0x08
+#define RDA_DMA_CTL_EN    BIT(0)
+#define RDA_DMA_CTL_INT_MASK    BIT(1)
+#define RDA_DMA_CTL_INT_CLE     BIT(2)
+#define RDA_DMA_CTL_SRC_SEL     BIT(24)
+#define RDA_DMA_CTL_DST_SEL    BIT(25)
+
+#define RDA_DMA_SRC_REG     0x0C
+#define RDA_DMA_DST_REG     0x10
+#define RDA_DMA_XFER_SIZE_REG   0x18
+
+/* In general, data will be transisted via AXI bus. */
+#define RDA_DMA_NOR_MODE	 (0x00000000)
+/* Fast write mode : bit25 is for control writing via sram port. */
+#define RDA_DMA_FW_MODE     RDA_DMA_CTL_DST_SEL
+/* Fast read mode : bit24 is for control reading via sram port. */
+#define RDA_DMA_FR_MODE      RDA_DMA_CTL_SRC_SEL
+#define RDA_DMA_MODE_MASK       (RDA_DMA_CTL_SRC_SEL | RDA_DMA_CTL_DST_SEL)
+
+struct rda_dma_chan_params {
+    u32 src_addr;
+    u32 dst_addr;
+    u32 xfer_size;
+    u32 dma_mode;
+};
+
+int rda_set_dma_params(u8 ch, struct rda_dma_chan_params *params);
+
+void rda_start_dma(u8 ch);
+
+void rda_stop_dma(u8 ch);
+
+void rda_poll_dma(u8 ch);
+
+int rda_request_dma(u8 *dma_ch_out);
+
+void rda_free_dma(u8 ch);
+
+#endif /* __DMA_H__ */
+
diff --git a/arch/arm/include/asm/arch-rda/factory.h b/arch/arm/include/asm/arch-rda/factory.h
new file mode 100644
index 0000000000..45b9227f04
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/factory.h
@@ -0,0 +1,104 @@
+#ifndef __FACTORY_DATA_H__
+#define __FACTORY_DATA_H__
+
+#include "defs_mdcom.h"
+
+/* data size define */
+#define RDA_MODEM_CAL_LEN		8192 /* rf/audio calibration data */
+#define RDA_MODEM_FACT_LEN		4096 /* modem factory info */
+#define RDA_AP_FACT_LEN			4096 /* ap factory info */
+#define RDA_MODEM_EXT_CAL_LEN	16384 /* extended rf/audio calibration data, includes wcdma data */
+#define RDA_FACT_TOTAL_LEN		\
+	(RDA_MODEM_CAL_LEN + RDA_MODEM_FACT_LEN + RDA_AP_FACT_LEN \
+	 + RDA_MODEM_EXT_CAL_LEN)
+
+/* loading addresses */
+/* extended calibration data loading address */
+#define RDA_MODEM_EXT_CAL_ADDR		(RDA_MODEM_RAM_END - RDA_FACT_TOTAL_LEN)
+/* calibration data loading address */
+#define RDA_MODEM_CAL_ADDR			(RDA_MODEM_EXT_CAL_ADDR + RDA_MODEM_EXT_CAL_LEN)
+/* modem factory info loading address */
+#define RDA_MODEM_FACT_ADDR			(RDA_MODEM_CAL_ADDR + RDA_MODEM_CAL_LEN)
+/* ap factory info loading address */
+#define RDA_AP_FACT_ADDR			(RDA_MODEM_FACT_ADDR + RDA_MODEM_FACT_LEN)
+
+/* version define & magic number */
+#define AP_FACTORY_MAJOR_VERSION	2
+#define AP_FACTORY_MINOR_VERSION	1 /* always be 1 */
+#define AP_FACTORY_MARK_VERSION		0xFAC40000
+#define AP_FACTORY_VERSION_NUMBER	(AP_FACTORY_MARK_VERSION | \
+		(AP_FACTORY_MAJOR_VERSION << 8) | AP_FACTORY_MINOR_VERSION)
+#define AP_FACTORY_CLOCK_MAGIC		0x55515263
+
+/* old version compatibility */
+#define AP_FACTORY_MAJOR_VERSION_1				1
+#define AP_FACTORY_VERSION_1_LEN			(RDA_MODEM_CAL_LEN + \
+										RDA_MODEM_FACT_LEN + RDA_AP_FACT_LEN)
+#define AP_FACTORY_VERSION_1_NUMBER			(AP_FACTORY_MARK_VERSION | \
+						(AP_FACTORY_MAJOR_VERSION_1 << 8) | AP_FACTORY_MINOR_VERSION)
+
+#define FACT_NAME_LEN				128
+#define AP_FACTORY_CLOCK_CFG_LEN	1024
+#define GS_CALI_DATA_LEN			32
+
+struct ap_factory_config {
+	unsigned int version;
+	unsigned int crc;
+	unsigned char lcd_name[FACT_NAME_LEN];
+	unsigned char bootlogo_name[FACT_NAME_LEN];
+	unsigned char clock_config[AP_FACTORY_CLOCK_CFG_LEN];
+	unsigned char gs_cali_data[GS_CALI_DATA_LEN];
+};
+
+struct factory_data_sector {
+	unsigned char modem_calib_data[RDA_MODEM_CAL_LEN];
+	unsigned char modem_factory_data[RDA_MODEM_FACT_LEN];
+	unsigned char ap_factory_data[RDA_AP_FACT_LEN];
+	unsigned char modem_ext_calib_data[RDA_MODEM_EXT_CAL_LEN];
+};
+
+int factory_load(void);
+unsigned long factory_get_all(unsigned char *buf);
+const unsigned char* factory_get_ap_factory(void);
+const unsigned char* factory_get_modem_calib(void);
+const unsigned char* factory_get_modem_ext_calib(void);
+const unsigned char* factory_get_modem_factory(void);
+const unsigned char* factory_get_lcd_name(void);
+const unsigned char* factory_get_bootlogo_name(void);
+int factory_set_ap_factory(unsigned char *data);
+int factory_set_modem_calib(unsigned char *data);
+int factory_set_modem_ext_calib(unsigned char *data);
+int factory_set_modem_factory(unsigned char *data);
+int factory_burn(void);
+int factory_update_modem_calib(unsigned char *data);
+int factory_update_modem_ext_calib(unsigned char *data);
+int factory_update_modem_factory(unsigned char *data);
+int factory_update_ap_factory(unsigned char *data);
+int factory_update_all(unsigned char *data, unsigned long size);
+int factory_copy_from_mem(const u8 *buf);
+
+
+/* Define a simple message function, for PC calib tool and u-boot.
+   Borrow ap_factory_data top 1024 bytes to send and receive message. */
+#define RDA_AP_CALIB_MSG_MAGIC	0xca1b5353
+#define RDA_AP_CALIB_MSG_LEN	1024
+#define RDA_AP_CALIB_MSG_ADDR	(RDA_AP_FACT_ADDR + RDA_AP_FACT_LEN - RDA_AP_CALIB_MSG_LEN)
+
+#define RDA_AP_CALIB_MSG_DATA_LEN	1012
+struct ap_calib_message {
+	unsigned int magic; /* must be RDA_AP_CALIB_MSG_MAGIC */
+	unsigned int id; /* see below defines */
+	unsigned int size; /* the size of message data */
+	unsigned char data[RDA_AP_CALIB_MSG_DATA_LEN];
+};
+
+/* PC calib tool -> u-boot */
+#define RDA_AP_CALIB_MSG_SET_PRDINFO			0x1
+int factory_get_ap_calib_msg(unsigned int *id, unsigned int *size, unsigned char *data);
+
+/* u-boot -> PC calib tool */
+#define RDA_AP_CALIB_MSG_GET_PRDINFO			0x80000001
+int factory_set_ap_calib_msg(unsigned int id, unsigned int size, unsigned char *data);
+
+
+#endif
diff --git a/arch/arm/include/asm/arch-rda/global_macros.h b/arch/arm/include/asm/arch-rda/global_macros.h
new file mode 100644
index 0000000000..10bb7ecce3
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/global_macros.h
@@ -0,0 +1,67 @@
+//==============================================================================
+//                                                                              
+//            Copyright (C) 2012-2013, RDA Microelectronics.                    
+//                            All Rights Reserved                               
+//                                                                              
+//      This source code is the property of RDA Microelectronics and is         
+//      confidential.  Any  modification, distribution,  reproduction or        
+//      exploitation  of  any content of this file is totally forbidden,        
+//      except  with the  written permission  of   RDA Microelectronics.        
+//                                                                              
+//==============================================================================
+//                                                                              
+//    THIS FILE WAS GENERATED FROM ITS CORRESPONDING XML VERSION WITH COOLXML.  
+//                                                                              
+//                       !!! PLEASE DO NOT EDIT !!!                             
+//                                                                              
+//  $HeadURL$                                                                   
+//  $Author$                                                                    
+//  $Date$                                                                      
+//  $Revision$                                                                  
+//                                                                              
+//==============================================================================
+//
+/// @file
+//
+//==============================================================================
+
+#ifndef _GLOBAL_MACROS_H_
+#define _GLOBAL_MACROS_H_
+
+
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+
+
+
+//#define KSEG0(addr)     ( (addr) | 0x80000000 )
+//#define KSEG1(addr)     ( (addr) | 0xa0000000 )
+#define KSEG0(addr)     ( (addr) )
+#define KSEG1(addr)     ( (addr) )
+
+
+/* Define access cached or uncached */
+#define MEM_ACCESS_CACHED(addr)     ((UINT32*)((UINT32)(addr)&0xdfffffff))
+#define MEM_ACCESS_UNCACHED(addr)   ((UINT32*)((UINT32)(addr)|0x20000000))
+
+/* Register access for assembly */
+#define BASE_HI(val) (((0xa0000000 | val) & 0xffff8000) + (val & 0x8000))
+#define BASE_LO(val) (((val) & 0x7fff) - (val & 0x8000))
+
+
+/* to extract bitfield from register value */
+#define GET_BITFIELD(dword, bitfield) (((dword) & (bitfield ## _MASK)) >> (bitfield ## _SHIFT))
+
+#define EXP2(n) (1<<(n))
+
+
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/hardware.h b/arch/arm/include/asm/arch-rda/hardware.h
new file mode 100644
index 0000000000..f498734273
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/hardware.h
@@ -0,0 +1,19 @@
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <config.h>
+#include <asm/sizes.h>
+
+#ifndef __ASSEMBLY__ 
+typedef volatile unsigned int REG32;
+typedef unsigned char               BOOL;
+
+#define TRUE                        (1==1)
+#define FALSE                       (1==0)
+#endif
+
+/* to extract bitfield from register value */
+#define GET_BITFIELD(dword, bitfield) (((dword) & (bitfield ## _MASK)) >> (bitfield ## _SHIFT)) 
+#define SET_BITFIELD(dword, bitfield, value) (((dword) & ~(bitfield ## _MASK)) | (bitfield(value)))
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-rda/hw_test.h b/arch/arm/include/asm/arch-rda/hw_test.h
new file mode 100644
index 0000000000..5dec670f6c
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/hw_test.h
@@ -0,0 +1,61 @@
+#ifndef __RDA_HW_TEST_H__
+#define __RDA_HW_TEST_H__
+
+#ifdef CONFIG_VPU_TEST
+extern void vpu_sta_test(int times);
+extern int  vpu_md5_test(int times);
+#else
+static inline void vpu_sta_test(int times){};
+static inline int  vpu_md5_test(int times){return 0;};
+#endif /* CONFIG_VPU_TEST */
+
+#ifdef CONFIG_CPU_TEST
+extern void cpu_pll_test(int times);
+#else
+static inline void cpu_pll_test(int times){};
+#endif /*CONFIG_CPU_TEST */
+
+#ifdef CONFIG_DDR_TEST
+extern int ddr_mem_copy_test(int times,unsigned int src_addr, unsigned int des_addr, unsigned int nword);
+#else
+static inline int ddr_mem_copy_test(int times,unsigned int src_addr, unsigned int des_addr, unsigned int nword){return 0;}
+#endif /* CONFIG_DDR_TEST */
+
+#ifdef CONFIG_TIMER_TEST
+extern int tim_test(int timer_id,int times);
+#else
+static inline int tim_test(int timer_id,int times){ return 0;}
+#endif /* CONFIG_TIMER_TEST */
+
+#ifdef CONFIG_UART_TEST
+extern int uart_test(int uart_id,int times);
+#else
+static inline int uart_test(int uart_id,int times){ return 0;}
+#endif /* CONFIG_UART_TEST */
+
+#ifdef CONFIG_GIC_TEST
+extern int gic_test(int times);
+#else
+static inline int gic_test(int times){ return 0;}
+#endif /* CONFIG_GIC_TEST */
+
+#ifdef CONFIG_CACHE_TEST
+extern int cpu_cache_test(int times);
+#else
+static inline int cpu_cache_test(int times){ return 0;}
+#endif /* CONFIG_CACHE_TEST */
+
+#ifdef CONFIG_MIPI_LOOP_TEST
+extern int test_dsi_csi_loop(int times);
+#else
+static inline int test_dsi_csi_loop(int times) {return 0;};
+#endif /* CONFIG_MIPI_LOOP_TEST */
+
+#ifdef CONFIG_I2C_TEST
+extern int test_i2c(int id,int times);
+#else
+static inline int test_i2c(int id,int times){ return 0;}
+#endif /* CONFIG_I2C_TEST */
+
+
+#endif /*__RDA_HW_TEST_H__*/
diff --git a/arch/arm/include/asm/arch-rda/hwcfg.h b/arch/arm/include/asm/arch-rda/hwcfg.h
new file mode 100644
index 0000000000..aee369e7bb
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/hwcfg.h
@@ -0,0 +1,64 @@
+#ifndef __RDA_HWCFG_H
+#define __RDA_HWCFG_H
+
+/*
+ * HW BOOT MODE
+ * BIT_15: 1 - force download
+ * BIT_14: 1 - volume up
+ * BIT_13: 1 - volume down
+ * BIT_12: 1 - key on (power on key)
+ * BIT_11: 1 - force DL (skip NAND loading)
+ * BIT_10: 1 - to skip USB init (for cases USB init may fail)
+ *         (in bootloader, this bit is used for calibration and driver test)
+ * BIT_7 : if BIT_3 == 1 (SPI FLASH): 1 - SDMMC, 1 - SPI FLASH
+ *         if BIT_3 == 0 (NAND/eMMC): 1 - 4K SLC/8K MLC, 0 - 2K SLC/4K MLC
+ * BIT_4 : if BIT_3 == 1 (SPI FLASH): 1 - SPI NAND, 0 - SPI NOR
+ *         if BIT_3 == 0 (NAND/eMMC): 1 - SDMMC, 0 - NAND/eMMC
+ * BIT_3 : 1 - use SPI NAND, 0 - use NAND/eMMC
+ * BIT_2 : 1 - use eMMC, 0 - use NAND
+ * BIT_1 : 1 - 8bit NAND, 0 - 16bit NAND
+ * BIT_0 : 1 - MLC, 0 - SLC
+ */
+#define RDA_HW_CFG_BIT_15    (1 << 15)
+#define RDA_HW_CFG_BIT_14    (1 << 14)
+#define RDA_HW_CFG_BIT_13    (1 << 13)
+#define RDA_HW_CFG_BIT_12    (1 << 12)
+#define RDA_HW_CFG_BIT_11    (1 << 11)
+#define RDA_HW_CFG_BIT_10    (1 << 10)
+#define RDA_HW_CFG_BIT_7     (1 << 7)
+#define RDA_HW_CFG_BIT_4     (1 << 4)
+#define RDA_HW_CFG_BIT_3     (1 << 3)
+#define RDA_HW_CFG_BIT_2     (1 << 2)
+#define RDA_HW_CFG_BIT_1     (1 << 1)
+#define RDA_HW_CFG_BIT_0     (1 << 0)
+
+/*
+ * SW BOOT MODE
+ * BIT_6 : PDL2
+ * BIT_5 : Autocall
+ * BIT_4 : Calib
+ * BIT_3 : Recovery
+ * BIT_2 : Fastboot
+ * BIT_1 : ROM force run
+ * BIT_0 : Modem EBC valid
+ */
+#define RDA_SW_CFG_BIT_6	(1 << 6)
+#define RDA_SW_CFG_BIT_5	(1 << 5)
+#define RDA_SW_CFG_BIT_4	(1 << 4)
+#define RDA_SW_CFG_BIT_3	(1 << 3)
+#define RDA_SW_CFG_BIT_2	(1 << 2)
+#define RDA_SW_CFG_BIT_1	(1 << 1)
+#define RDA_SW_CFG_BIT_0	(1 << 0)
+
+void rda_hwcfg_reg_set(u16);
+u16 rda_hwcfg_reg_get(void);
+u16 rda_hwcfg_get(void);
+void rda_swcfg_reg_set(u16);
+u16 rda_swcfg_reg_get(void);
+u16 rda_swcfg_get(void);
+u16 rda_prod_id_get(void);
+u16 rda_metal_id_get(void);
+u16 rda_bond_id_get(void);
+void rda_nand_iodrive_set(void);
+
+#endif // __RDA_HWCFG_H
diff --git a/arch/arm/include/asm/arch-rda/ifc.h b/arch/arm/include/asm/arch-rda/ifc.h
new file mode 100644
index 0000000000..099d4a1020
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/ifc.h
@@ -0,0 +1,55 @@
+#ifndef  _IFC_H_
+#define  _IFC_H_
+
+#include <asm/arch/hardware.h>
+
+#define HAL_UNKNOWN_CHANNEL      0xff
+
+typedef enum {
+    HAL_IFC_UART_TX,
+    HAL_IFC_UART_RX,
+    HAL_IFC_UART2_TX,
+    HAL_IFC_UART2_RX,
+    HAL_IFC_SPI_TX,
+    HAL_IFC_SPI_RX,
+    HAL_IFC_SPI2_TX,
+    HAL_IFC_SPI2_RX,
+    HAL_IFC_SPI3_TX,
+    HAL_IFC_SPI3_RX,
+    HAL_IFC_SDMMC_TX,
+    HAL_IFC_SDMMC_RX,
+    HAL_IFC_SDMMC2_TX,
+    HAL_IFC_SDMMC2_RX,
+    HAL_IFC_SDMMC3_TX,
+    HAL_IFC_SDMMC3_RX,
+    HAL_IFC_NFSC_TX,
+    HAL_IFC_NFSC_RX,
+    HAL_IFC_UART3_TX,
+    HAL_IFC_UART3_RX,
+    HAL_IFC_NO_REQWEST
+} HAL_IFC_REQUEST_ID_T;
+
+// =============================================================================
+// HAL_IFC_MODE_T
+// -----------------------------------------------------------------------------
+/// Define the mode used to configure an IFC transfer. This enum describes
+/// the width (8 or 32 bits) and if the transfer is autodisabled or manually
+/// disabled.
+// =============================================================================
+typedef enum
+{
+    HAL_IFC_SIZE_8_MODE_MANUAL  = (0 | 0),
+    HAL_IFC_SIZE_8_MODE_AUTO    = (0 | SYS_IFC_AUTODISABLE),
+    HAL_IFC_SIZE_32_MODE_MANUAL = (SYS_IFC_SIZE_WORD | 0),
+    HAL_IFC_SIZE_32_MODE_AUTO   = (SYS_IFC_SIZE_WORD | SYS_IFC_AUTODISABLE),
+} HAL_IFC_MODE_T;
+
+void hal_IfcOpen(void);
+HAL_IFC_REQUEST_ID_T hal_IfcGetOwner(u8 channel);
+void hal_IfcChannelRelease(HAL_IFC_REQUEST_ID_T requestId, u8 channel);
+void hal_IfcChannelFlush(HAL_IFC_REQUEST_ID_T requestId, u8 channel);
+BOOL hal_IfcChannelIsFifoEmpty(HAL_IFC_REQUEST_ID_T requestId, u8 channel);
+u8 hal_IfcTransferStart(HAL_IFC_REQUEST_ID_T requestId, u8* memStartAddr, u32 xferSize, HAL_IFC_MODE_T ifcMode);
+
+#endif //  _IFC_H 
+
diff --git a/arch/arm/include/asm/arch-rda/iomap_rda8810.h b/arch/arm/include/asm/arch-rda/iomap_rda8810.h
new file mode 100644
index 0000000000..256b189b30
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/iomap_rda8810.h
@@ -0,0 +1,162 @@
+#ifndef __IOMAP_RDA8810_H
+#define __IOMAP_RDA8810_H
+
+#include <asm/sizes.h>
+
+#define RDA_SRAM_BASE         0x00100000
+#define RDA_SRAM_SIZE         SZ_64K
+
+#define RDA_MD_MAILBOX_BASE   0x00200000
+#define RDA_MD_MAILBOX_SIZE   SZ_8K
+
+#define RDA_MODEM_BASE        0x10000000
+#define RDA_MODEM_SIZE        SZ_256M
+
+#define RDA_MD_SYSCTRL_BASE   0x11A00000
+#define RDA_MD_SYSCTRL_SIZE   SZ_4K
+
+#define RDA_GPIO_BASE         0x11A08000
+#define RDA_GPIO_SIZE         SZ_4K
+
+#define RDA_CFG_REGS_BASE     0x11A09000
+#define RDA_CFG_REGS_SIZE     SZ_4K
+
+#define RDA_MODEM_SPI2_BASE   0x11A14000
+#define RDA_MODEM_SPI2_SIZE   SZ_4K
+
+#define RDA_MODEM_XCPU_BASE   0x11A16000
+#define RDA_MODEM_XCPU_SIZE   SZ_4K
+
+#define RDA_MODEM_BCPU_BASE   0x11909000
+#define RDA_MODEM_BCPU_SIZE   SZ_4K
+
+#define RDA_MD_PSRAM_BASE     (RDA_MODEM_BASE + 0x02000000)
+#define RDA_MD_PSRAM_SIZE     SZ_4M
+
+#define RDA_CAMERA_BASE       0x20000000
+#define RDA_CAMERA_SIZE       SZ_256K
+
+#define RDA_GOUDA_MEM_BASE    0x20040000
+#define RDA_GOUDA_MEM_SIZE    SZ_256K
+
+#define RDA_GPU_BASE          0x20080000
+#define RDA_GPU_SIZE          SZ_256K
+
+#define RDA_VOC_BASE          0x200C0000
+#define RDA_VOC_SIZE          SZ_256K
+
+#define RDA_USB_BASE          0x20400000
+#define RDA_USB_SIZE          SZ_256K
+
+#define RDA_SPIFLASH_BASE     0x20440000
+#define RDA_SPIFLASH_SIZE     SZ_256K
+
+#define RDA_CONNECT_BASE      0x21000000
+#define RDA_CONNECT_SIZE      SZ_4K
+
+#define RDA_L2CC_BASE         0x21100000
+#define RDA_L2CC_SIZE         SZ_4K
+
+/* APB0 */
+#define RDA_INTC_BASE         0x20800000
+#define RDA_INTC_SIZE         SZ_4K
+
+#define RDA_IMEM_BASE         0x20810000
+#define RDA_IMEM_SIZE         SZ_4K
+
+#define RDA_DMA_BASE          0x20820000
+#define RDA_DMA_SIZE          SZ_4K
+
+#define RDA_VPU_BASE          0x20830000
+#define RDA_VPU_SIZE          SZ_4K
+
+#define RDA_GOUDA_BASE        0x20840000
+#define RDA_GOUDA_SIZE        SZ_4K
+
+#define RDA_CAMERA_DMA_BASE   0x20850000
+#define RDA_CAMERA_DMA_SIZE   SZ_4K
+
+/* APB1 */
+#define RDA_SYSCTRL_BASE      0x20900000
+#define RDA_SYSCTRL_SIZE      SZ_4K
+
+#define RDA_TIMER_BASE        0x20910000
+#define RDA_TIMER_SIZE        SZ_4K
+
+#define RDA_KEYPAD_BASE       0x20920000
+#define RDA_KEYPAD_SIZE       SZ_4K
+
+#define RDA_GPIO_A_BASE       0x20930000
+#define RDA_GPIO_A_SIZE       SZ_4K
+
+#define RDA_GPIO_B_BASE       0x20931000
+#define RDA_GPIO_B_SIZE       SZ_4K
+
+#define RDA_GPIO_D_BASE       0x20932000
+#define RDA_GPIO_D_SIZE       SZ_4K
+
+#define RDA_PWM_BASE          0x20940000
+#define RDA_PWM_SIZE          SZ_4K
+
+#define RDA_I2C1_BASE         0x20950000
+#define RDA_I2C1_SIZE         SZ_4K
+
+#define RDA_I2C2_BASE         0x20960000
+#define RDA_I2C2_SIZE         SZ_4K
+
+#define RDA_I2C3_BASE         0x20970000
+#define RDA_I2C3_SIZE         SZ_4K
+
+#define RDA_COMREGS_BASE      0x20980000
+#define RDA_COMREGS_SIZE      SZ_4K
+
+#define RDA_DMC400_BASE       0x20990000
+#define RDA_DMC400_SIZE       SZ_4K
+
+#define RDA_DDRPHY_BASE       0x209A0000
+#define RDA_DDRPHY_SIZE       SZ_4K
+
+#define RDA_DBGAPB_BASE       0x209B0000
+#define RDA_DBGAPB_SIZE       SZ_4K
+
+#define RDA_AIF_BASE          0x209E0000
+#define RDA_AIF_SIZE          SZ_4K
+
+#define RDA_AUIFC_BASE        0x209F0000
+#define RDA_AUIFC_SIZE        SZ_4K
+
+/* APB2 */
+#define RDA_UART1_BASE        0x20A00000
+#define RDA_UART1_SIZE        SZ_4K
+
+#define RDA_UART2_BASE        0x20A10000
+#define RDA_UART2_SIZE        SZ_4K
+
+#define RDA_SPI1_BASE         0x20A20000
+#define RDA_SPI1_SIZE         SZ_4K
+
+#define RDA_SPI2_BASE         0x20A30000
+#define RDA_SPI2_SIZE         SZ_4K
+
+#define RDA_SPI3_BASE         0x20A40000
+#define RDA_SPI3_SIZE         SZ_4K
+
+#define RDA_SDMMC1_BASE       0x20A50000
+#define RDA_SDMMC1_SIZE       SZ_4K
+
+#define RDA_SDMMC2_BASE       0x20A60000
+#define RDA_SDMMC2_SIZE       SZ_4K
+
+#define RDA_SDMMC3_BASE       0x20A70000
+#define RDA_SDMMC3_SIZE       SZ_4K
+
+#define RDA_NAND_BASE         0x20A80000
+#define RDA_NAND_SIZE         SZ_16K
+
+#define RDA_UART3_BASE        0x20A90000
+#define RDA_UART3_SIZE        SZ_16K
+
+#define RDA_IFC_BASE          0x20AF0000
+#define RDA_IFC_SIZE          SZ_4K
+
+#endif /* __IOMAP_RDA8810_H */
diff --git a/arch/arm/include/asm/arch-rda/iomap_rda8810e.h b/arch/arm/include/asm/arch-rda/iomap_rda8810e.h
new file mode 100644
index 0000000000..2b9bcac307
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/iomap_rda8810e.h
@@ -0,0 +1,180 @@
+#ifndef __IOMAP_RDA8810E_H
+#define __IOMAP_RDA8810E_H
+
+#include <asm/sizes.h>
+
+#define RDA_SRAM_BASE         0x00100000
+#define RDA_SRAM_SIZE         SZ_64K
+
+#define RDA_MD_MAILBOX_BASE   0x00200000
+#define RDA_MD_MAILBOX_SIZE   SZ_8K
+
+#define RDA_MODEM_BASE        0x10000000
+#define RDA_MODEM_SIZE        SZ_256M
+
+#define RDA_MD_SYSCTRL_BASE   0x11A00000
+#define RDA_MD_SYSCTRL_SIZE   SZ_4K
+
+#define RDA_GPIO_BASE         0x11A08000
+#define RDA_GPIO_SIZE         SZ_4K
+
+#define RDA_CFG_REGS_BASE     0x11A09000
+#define RDA_CFG_REGS_SIZE     SZ_4K
+
+#define RDA_MODEM_SPI2_BASE   0x11A14000
+#define RDA_MODEM_SPI2_SIZE   SZ_4K
+
+#define RDA_MODEM_XCPU_BASE   0x11A16000
+#define RDA_MODEM_XCPU_SIZE   SZ_4K
+
+#define RDA_MODEM_BCPU_BASE   0x11909000
+#define RDA_MODEM_BCPU_SIZE   SZ_4K
+
+#define RDA_MD_PSRAM_BASE     (RDA_MODEM_BASE + 0x02000000)
+#define RDA_MD_PSRAM_SIZE     SZ_4M
+
+#define RDA_CAMERA_BASE       0x20000000
+#define RDA_CAMERA_SIZE       SZ_256K
+
+#define RDA_GOUDA_MEM_BASE    0x20040000
+#define RDA_GOUDA_MEM_SIZE    SZ_256K
+
+#define RDA_GPU_BASE          0x20080000
+#define RDA_GPU_SIZE          SZ_256K
+
+#define RDA_VOC_BASE          0x200C0000
+#define RDA_VOC_SIZE          SZ_256K
+
+#define RDA_VOC2_BASE         0x20100000
+#define RDA_VOC2_SIZE         SZ_256K
+
+#define RDA_USB_BASE          0x20400000
+#define RDA_USB_SIZE          SZ_256K
+
+#define RDA_SPIFLASH_BASE     0x20440000
+#define RDA_SPIFLASH_SIZE     SZ_256K
+
+#define RDA_CONNECT_BASE      0x21000000
+#define RDA_CONNECT_SIZE      SZ_4K
+
+#define RDA_L2CC_BASE         0x21100000
+#define RDA_L2CC_SIZE         SZ_4K
+
+/* APB0 */
+#define RDA_INTC_BASE         0x20800000
+#define RDA_INTC_SIZE         SZ_4K
+
+#define RDA_IMEM_BASE         0x20810000
+#define RDA_IMEM_SIZE         SZ_4K
+
+#define RDA_DMA_BASE          0x20820000
+#define RDA_DMA_SIZE          SZ_4K
+
+#define RDA_GOUDA_BASE        0x20840000
+#define RDA_GOUDA_SIZE        SZ_4K
+
+#define RDA_CAMERA_DMA_BASE   0x20850000
+#define RDA_CAMERA_DMA_SIZE   SZ_4K
+
+#define RDA_MMU_GOUDA_BASE    0x20860000
+#define RDA_MMU_GOUDA_SIZE    SZ_64K
+
+#define RDA_MMU_CAMERA_BASE   0x20870000
+#define RDA_MMU_CAMERA_SIZE   SZ_64K
+
+#define RDA_MMU_VOC1_BASE     0x20880000
+#define RDA_MMU_VOC1_SIZE     SZ_64K
+
+#define RDA_MMU_VOC2_BASE     0x20890000
+#define RDA_MMU_VOC2_SIZE     SZ_64K
+
+/* APB1 */
+#define RDA_SYSCTRL_BASE      0x20900000
+#define RDA_SYSCTRL_SIZE      SZ_4K
+
+#define RDA_TIMER_BASE        0x20910000
+#define RDA_TIMER_SIZE        SZ_4K
+
+#define RDA_KEYPAD_BASE       0x20920000
+#define RDA_KEYPAD_SIZE       SZ_4K
+
+#define RDA_GPIO_A_BASE       0x20930000
+#define RDA_GPIO_A_SIZE       SZ_4K
+
+#define RDA_GPIO_B_BASE       0x20931000
+#define RDA_GPIO_B_SIZE       SZ_4K
+
+#define RDA_GPIO_D_BASE       0x20932000
+#define RDA_GPIO_D_SIZE       SZ_4K
+
+#define RDA_GPIO_E_BASE       0x20933000
+#define RDA_GPIO_E_SIZE       SZ_4K
+
+#define RDA_PWM_BASE          0x20940000
+#define RDA_PWM_SIZE          SZ_4K
+
+#define RDA_I2C1_BASE         0x20950000
+#define RDA_I2C1_SIZE         SZ_4K
+
+#define RDA_I2C2_BASE         0x20960000
+#define RDA_I2C2_SIZE         SZ_4K
+
+#define RDA_I2C3_BASE         0x20970000
+#define RDA_I2C3_SIZE         SZ_4K
+
+#define RDA_COMREGS_BASE      0x20980000
+#define RDA_COMREGS_SIZE      SZ_4K
+
+#define RDA_DMC400_BASE       0x20990000
+#define RDA_DMC400_SIZE       SZ_4K
+
+#define RDA_DDRPHY_BASE       0x209A0000
+#define RDA_DDRPHY_SIZE       SZ_4K
+
+#define RDA_DBGAPB_BASE       0x209B0000
+#define RDA_DBGAPB_SIZE       SZ_4K
+
+#define RDA_AIF2_BASE         0x209D0000
+#define RDA_AIF2_SIZE         SZ_4K
+
+#define RDA_AIF_BASE          0x209E0000
+#define RDA_AIF_SIZE          SZ_4K
+
+#define RDA_AUIFC_BASE        0x209F0000
+#define RDA_AUIFC_SIZE        SZ_4K
+
+/* APB2 */
+#define RDA_UART1_BASE        0x20A00000
+#define RDA_UART1_SIZE        SZ_4K
+
+#define RDA_UART2_BASE        0x20A10000
+#define RDA_UART2_SIZE        SZ_4K
+
+#define RDA_SPI1_BASE         0x20A20000
+#define RDA_SPI1_SIZE         SZ_4K
+
+#define RDA_SPI2_BASE         0x20A30000
+#define RDA_SPI2_SIZE         SZ_4K
+
+#define RDA_SPI3_BASE         0x20A40000
+#define RDA_SPI3_SIZE         SZ_4K
+
+#define RDA_SDMMC1_BASE       0x20A50000
+#define RDA_SDMMC1_SIZE       SZ_4K
+
+#define RDA_SDMMC2_BASE       0x20A60000
+#define RDA_SDMMC2_SIZE       SZ_4K
+
+#define RDA_SDMMC3_BASE       0x20A70000
+#define RDA_SDMMC3_SIZE       SZ_4K
+
+#define RDA_NAND_BASE         0x20A80000
+#define RDA_NAND_SIZE         SZ_16K
+
+#define RDA_UART3_BASE        0x20A90000
+#define RDA_UART3_SIZE        SZ_16K
+
+#define RDA_IFC_BASE          0x20AF0000
+#define RDA_IFC_SIZE          SZ_4K
+
+#endif /* __IOMAP_RDA8810E_H */
diff --git a/arch/arm/include/asm/arch-rda/iomap_rda8810h.h b/arch/arm/include/asm/arch-rda/iomap_rda8810h.h
new file mode 100644
index 0000000000..200ecf1980
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/iomap_rda8810h.h
@@ -0,0 +1,192 @@
+#ifndef __IOMAP_RDA8810H_H
+#define __IOMAP_RDA8810H_H
+
+#include <asm/sizes.h>
+
+#define RDA_SRAM_BASE         0x00100000
+#define RDA_SRAM_SIZE         SZ_64K
+
+#define RDA_MD_MAILBOX_BASE   0x00200000
+#define RDA_MD_MAILBOX_SIZE   SZ_8K
+
+#define RDA_MODEM_BASE        0x10000000
+#define RDA_MODEM_SIZE        SZ_256M
+
+#define RDA_MD_SYSCTRL_BASE   0x11A00000
+#define RDA_MD_SYSCTRL_SIZE   SZ_4K
+
+#define RDA_GPIO_BASE         0x11A08000
+#define RDA_GPIO_SIZE         SZ_4K
+
+#define RDA_CFG_REGS_BASE     0x11A09000
+#define RDA_CFG_REGS_SIZE     SZ_4K
+
+#define RDA_MODEM_SPI2_BASE   0x11A14000
+#define RDA_MODEM_SPI2_SIZE   SZ_4K
+
+#define RDA_MODEM_XCPU_BASE   0x11A16000
+#define RDA_MODEM_XCPU_SIZE   SZ_4K
+
+#define RDA_MODEM_BCPU_BASE   0x11909000
+#define RDA_MODEM_BCPU_SIZE   SZ_4K
+
+#define RDA_MD_PSRAM_BASE     (RDA_MODEM_BASE + 0x02000000)
+#define RDA_MD_PSRAM_SIZE     SZ_4M
+
+#define RDA_CAMERA_BASE       0x20000000
+#define RDA_CAMERA_SIZE       SZ_256K
+
+#define RDA_GOUDA_MEM_BASE    0x20040000
+#define RDA_GOUDA_MEM_SIZE    SZ_256K
+
+#define RDA_CAMERA2_BASE      0x20080000
+#define RDA_CAMERA2_SIZE      SZ_256K
+
+#define RDA_VOC_BASE          0x200C0000
+#define RDA_VOC_SIZE          SZ_256K
+
+#define RDA_USB_BASE          0x20400000
+#define RDA_USB_SIZE          SZ_256K
+
+#define RDA_SPIFLASH_BASE     0x20440000
+#define RDA_SPIFLASH_SIZE     SZ_256K
+
+#define RDA_ETHERNET_MAC_BASE     0x20480000
+#define RDA_ETHERNET_MAC_SIZE     SZ_256K
+
+#define RDA_CONNECT_BASE      0x21000000
+#define RDA_CONNECT_SIZE      SZ_1M
+
+#define RDA_L2CC_BASE         0x21100000
+#define RDA_L2CC_SIZE         SZ_4K
+
+/* APB0 */
+#define RDA_INTC_BASE         0x20800000
+#define RDA_INTC_SIZE         SZ_64K
+
+#define RDA_IMEM_BASE         0x20810000
+#define RDA_IMEM_SIZE         SZ_64K
+
+#define RDA_DMA_BASE          0x20820000
+#define RDA_DMA_SIZE          SZ_64K
+
+#define RDA_VPU_BASE          0x20830000
+#define RDA_VPU_SIZE          SZ_64K
+
+#define RDA_GOUDA_BASE        0x20840000
+#define RDA_GOUDA_SIZE        SZ_64K
+
+#define RDA_CAMERA_DMA_BASE   0x20850000
+#define RDA_CAMERA_DMA_SIZE   SZ_64K
+
+#define RDA_MALI_GOUDA_BASE   0x20860000
+#define RDA_MALI_GOUDA_SIZE   SZ_64K
+
+#define RDA_MMU_CAMERA2_BASE  0x20870000
+#define RDA_MMU_CAMERA2_SIZE  SZ_64K
+
+#define RDA_MMU_VOC1_BASE     0x20880000
+#define RDA_MMU_VOC1_SIZE     SZ_64K
+
+/* APB1 */
+#define RDA_SYSCTRL_BASE      0x20900000
+#define RDA_SYSCTRL_SIZE      SZ_64K
+
+#define RDA_TIMER_BASE        0x20910000
+#define RDA_TIMER_SIZE        SZ_4K
+
+#define RDA_TIMER1_BASE        0x20911000
+#define RDA_TIMER1_SIZE        SZ_4K
+
+#define RDA_TIMER2_BASE        0x20912000
+#define RDA_TIMER2_SIZE        SZ_4K
+
+#define RDA_KEYPAD_BASE       0x20920000
+#define RDA_KEYPAD_SIZE       SZ_64K
+
+#define RDA_GPIO_A_BASE       0x20930000
+#define RDA_GPIO_A_SIZE       SZ_4K
+
+#define RDA_GPIO_B_BASE       0x20931000
+#define RDA_GPIO_B_SIZE       SZ_4K
+
+#define RDA_GPIO_D_BASE       0x20932000
+#define RDA_GPIO_D_SIZE       SZ_4K
+
+#define RDA_GPIO_E_BASE       0x20933000
+#define RDA_GPIO_E_SIZE       SZ_4K
+
+#define RDA_PWM_BASE          0x20940000
+#define RDA_PWM_SIZE          SZ_64K
+
+#define RDA_COMREGS_BASE      0x20980000
+#define RDA_COMREGS_SIZE      SZ_64K
+
+#define RDA_DMC400_BASE       0x20990000
+#define RDA_DMC400_SIZE       SZ_4K
+
+#define RDA_DMCPAGESPY_BASE   0x20991000
+#define RDA_DMCPAGESPY_SIZE   SZ_4K
+
+#define RDA_DDRPHY_BASE       0x209A0000
+#define RDA_DDRPHY_SIZE       SZ_64K
+
+#define RDA_DBGAPB_BASE       0x209B0000
+#define RDA_DBGAPB_SIZE       SZ_64K
+
+#define RDA_AIF2_BASE         0x209D0000
+#define RDA_AIF2_SIZE         SZ_64K
+
+#define RDA_AIF_BASE          0x209E0000
+#define RDA_AIF_SIZE          SZ_64K
+
+#define RDA_AUIFC_BASE        0x209F0000
+#define RDA_AUIFC_SIZE        SZ_64K
+
+/* APB2 */
+#define RDA_UART1_BASE        0x20A00000
+#define RDA_UART1_SIZE        SZ_4K
+
+#define RDA_UART2_BASE        0x20A10000
+#define RDA_UART2_SIZE        SZ_4K
+
+#define RDA_SPI1_BASE         0x20A20000
+#define RDA_SPI1_SIZE         SZ_4K
+
+#define RDA_SPI2_BASE         0x20A30000
+#define RDA_SPI2_SIZE         SZ_4K
+
+#define RDA_SPI3_BASE         0x20A40000
+#define RDA_SPI3_SIZE         SZ_4K
+
+#define RDA_SDMMC1_BASE       0x20A50000
+#define RDA_SDMMC1_SIZE       SZ_4K
+
+#define RDA_SDMMC2_BASE       0x20A60000
+#define RDA_SDMMC2_SIZE       SZ_4K
+
+#define RDA_SDMMC3_BASE       0x20A70000
+#define RDA_SDMMC3_SIZE       SZ_4K
+
+#define RDA_NAND_BASE         0x20A80000
+#define RDA_NAND_SIZE         SZ_64K
+
+#define RDA_UART3_BASE        0x20A90000
+#define RDA_UART3_SIZE        SZ_16K
+
+#define RDA_A7MP2APB_BASE     0x20AA0000
+#define RDA_A7MP2APB_SIZE     SZ_64K
+
+#define RDA_I2C1_BASE         0x20AB0000
+#define RDA_I2C1_SIZE         SZ_64K
+
+#define RDA_I2C2_BASE         0x20AC0000
+#define RDA_I2C2_SIZE         SZ_64K
+
+#define RDA_I2C3_BASE         0x20AD0000
+#define RDA_I2C3_SIZE         SZ_64K
+
+#define RDA_IFC_BASE          0x20AF0000
+#define RDA_IFC_SIZE          SZ_4K
+
+#endif /* __IOMAP_RDA8810H_H */
diff --git a/arch/arm/include/asm/arch-rda/iomap_rda8820.h b/arch/arm/include/asm/arch-rda/iomap_rda8820.h
new file mode 100644
index 0000000000..b1cfef3381
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/iomap_rda8820.h
@@ -0,0 +1,196 @@
+#ifndef __IOMAP_RDA8820_H
+#define __IOMAP_RDA8820_H
+
+#define RDA_SRAM_BASE         0x00100000
+#define RDA_SRAM_SIZE         SZ_64K
+
+#define RDA_MD_MAILBOX_BASE   0x00200000
+#define RDA_MD_MAILBOX_SIZE   SZ_8K
+
+#define RDA_MODEM_BASE        0x10000000
+#define RDA_MODEM_SIZE        SZ_256M
+
+#define RDA_MD_SYSCTRL_BASE   0x11A00000
+#define RDA_MD_SYSCTRL_SIZE   SZ_4K
+
+#define RDA_GPIO_BASE         0x11A08000
+#define RDA_GPIO_SIZE         SZ_4K
+
+#define RDA_CFG_REGS_BASE     0x11A09000
+#define RDA_CFG_REGS_SIZE     SZ_4K
+
+#define RDA_MODEM_SPI2_BASE   0x11A14000
+#define RDA_MODEM_SPI2_SIZE   SZ_4K
+
+#define RDA_MODEM_XCPU_BASE   0x11A17000
+#define RDA_MODEM_XCPU_SIZE   SZ_4K
+
+#define RDA_MODEM_BCPU_BASE   0x11909000
+#define RDA_MODEM_BCPU_SIZE   SZ_4K
+
+#define RDA_MD_PSRAM_BASE     (RDA_MODEM_BASE + 0x02000000)
+#define RDA_MD_PSRAM_SIZE     SZ_16M
+
+#define RDA_CAMERA_BASE       0x20000000
+#define RDA_CAMERA_SIZE       SZ_256K
+
+#define RDA_GOUDA_MEM_BASE    0x20040000
+#define RDA_GOUDA_MEM_SIZE    SZ_256K
+
+#define RDA_GPU_BASE          0x20080000
+#define RDA_GPU_SIZE          SZ_256K
+
+#define RDA_VOC_BASE          0x200C0000
+#define RDA_VOC_SIZE          SZ_256K
+
+#define RDA_VOC2_BASE         0x20100000
+#define RDA_VOC2_SIZE         SZ_256K
+
+#define RDA_USB_BASE          0x20400000
+#define RDA_USB_SIZE          SZ_256K
+
+#define RDA_SPIFLASH_BASE     0x20440000
+#define RDA_SPIFLASH_SIZE     SZ_256K
+
+#define RDA_CONNECT_BASE      0x21000000
+#define RDA_CONNECT_SIZE      SZ_4K
+
+#define RDA_L2CC_BASE         0x21100000
+#define RDA_L2CC_SIZE         SZ_4K
+
+/* APB0 */
+#define RDA_INTC_BASE         0x20800000
+#define RDA_INTC_SIZE         SZ_4K
+
+#define RDA_IMEM_BASE         0x20810000
+#define RDA_IMEM_SIZE         SZ_4K
+
+#define RDA_DMA_BASE          0x20820000
+#define RDA_DMA_SIZE          SZ_4K
+
+#define RDA_VPU_BASE          0x20830000
+#define RDA_VPU_SIZE          SZ_64K
+
+#define RDA_GOUDA_BASE        0x20840000
+#define RDA_GOUDA_SIZE        SZ_4K
+
+#define RDA_CAMERA_DMA_BASE   0x20850000
+#define RDA_CAMERA_DMA_SIZE   SZ_4K
+
+#define RDA_CAMERA2_DMA_BASE  0x20860000
+#define RDA_CAMERA2_DMA_SIZE  SZ_64K
+
+#define RDA_GPU_BASE          0x20870000
+#define RDA_GPU_SIZE          SZ_64K
+
+#define RDA_AES_BASE          0x20880000
+#define RDA_AES_SIZE          SZ_64K
+
+#define RDA_JPEG_BASE         0x20890000
+#define RDA_JPEG_SIZE         SZ_64K
+
+/* APB1 */
+#define RDA_SYSCTRL_BASE      0x20900000
+#define RDA_SYSCTRL_SIZE      SZ_4K
+
+#define RDA_TIMER_BASE        0x20910000
+#define RDA_TIMER_SIZE        SZ_4K
+
+#define RDA_KEYPAD_BASE       0x20920000
+#define RDA_KEYPAD_SIZE       SZ_4K
+
+#define RDA_GPIO_A_BASE       0x20930000
+#define RDA_GPIO_A_SIZE       SZ_4K
+
+#define RDA_GPIO_B_BASE       0x20931000
+#define RDA_GPIO_B_SIZE       SZ_4K
+
+#define RDA_GPIO_D_BASE       0x20932000
+#define RDA_GPIO_D_SIZE       SZ_4K
+
+#define RDA_GPIO_E_BASE       0x20933000
+#define RDA_GPIO_E_SIZE       SZ_4K
+
+#define RDA_PWM_BASE          0x20940000
+#define RDA_PWM_SIZE          SZ_4K
+
+#define RDA_LVDS_BASE         0x20950000
+#define RDA_LVDS_SIZE         SZ_4K
+
+#define RDA_TVCLK_BASE        0x20960000
+#define RDA_TVCLK_SIZE        SZ_4K
+
+#define RDA_GIC400_BASE       0x20970000
+#define RDA_GIC400_SIZE       SZ_4K
+
+#define RDA_COMREGS_BASE      0x20980000
+#define RDA_COMREGS_SIZE      SZ_4K
+
+#define RDA_DMC400_BASE       0x20990000
+#define RDA_DMC400_SIZE       SZ_4K
+
+#define RDA_DDRPHY_BASE       0x209A0000
+#define RDA_DDRPHY_SIZE       SZ_4K
+
+#define RDA_PDCTRL_BASE       0x209B0000
+#define RDA_PDCTRL_SIZE       SZ_4K
+
+#define RDA_ISP_BASE          0x209C0000
+#define RDA_ISP_SIZE          SZ_4K
+
+#define RDA_AIF2_BASE         0x209D0000
+#define RDA_AIF2_SIZE         SZ_4K
+
+#define RDA_AIF_BASE          0x209E0000
+#define RDA_AIF_SIZE          SZ_4K
+
+#define RDA_AUIFC_BASE        0x209F0000
+#define RDA_AUIFC_SIZE        SZ_4K
+
+/* APB2 */
+#define RDA_UART1_BASE        0x20A00000
+#define RDA_UART1_SIZE        SZ_4K
+
+#define RDA_UART2_BASE        0x20A10000
+#define RDA_UART2_SIZE        SZ_4K
+
+#define RDA_SPI1_BASE         0x20A20000
+#define RDA_SPI1_SIZE         SZ_4K
+
+#define RDA_SPI2_BASE         0x20A30000
+#define RDA_SPI2_SIZE         SZ_4K
+
+#define RDA_SPI3_BASE         0x20A40000
+#define RDA_SPI3_SIZE         SZ_4K
+
+#define RDA_SDMMC1_BASE       0x20A50000
+#define RDA_SDMMC1_SIZE       SZ_4K
+
+#define RDA_SDMMC2_BASE       0x20A60000
+#define RDA_SDMMC2_SIZE       SZ_4K
+
+#define RDA_SDMMC3_BASE       0x20A70000
+#define RDA_SDMMC3_SIZE       SZ_4K
+
+#define RDA_NAND_BASE         0x20A80000
+#define RDA_NAND_SIZE         SZ_16K
+
+#define RDA_UART3_BASE        0x20A90000
+#define RDA_UART3_SIZE        SZ_16K
+
+#define RDA_I2C1_BASE         0x20AB0000
+#define RDA_I2C1_SIZE         SZ_4K
+
+#define RDA_I2C2_BASE         0x20AC0000
+#define RDA_I2C2_SIZE         SZ_4K
+
+#define RDA_I2C3_BASE         0x20AD0000
+#define RDA_I2C3_SIZE         SZ_4K
+
+#define RDA_UART4_BASE        0x20AE0000
+#define RDA_UART4_SIZE        SZ_16K
+
+#define RDA_IFC_BASE          0x20AF0000
+#define RDA_IFC_SIZE          SZ_4K
+
+#endif /* __IOMAP_RDA8820_H */
diff --git a/arch/arm/include/asm/arch-rda/iomap_rda8850.h b/arch/arm/include/asm/arch-rda/iomap_rda8850.h
new file mode 100644
index 0000000000..0cfad5dae8
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/iomap_rda8850.h
@@ -0,0 +1,163 @@
+#ifndef __IOMAP_RDA8850_H
+#define __IOMAP_RDA8850_H
+
+#define RDA_SRAM_BASE         0x00100000
+#define RDA_SRAM_SIZE         SZ_64K
+
+#define RDA_MD_MAILBOX_BASE   0x00200000
+#define RDA_MD_MAILBOX_SIZE   SZ_8K
+
+#define RDA_MODEM_BASE        0x10000000
+#define RDA_MODEM_SIZE        SZ_256M
+
+#define RDA_MD_SYSCTRL_BASE   0x11A00000
+#define RDA_MD_SYSCTRL_SIZE   SZ_4K
+
+#define RDA_GPIO_BASE         0x11A08000
+#define RDA_GPIO_SIZE         SZ_4K
+
+#define RDA_CFG_REGS_BASE     0x11A09000
+#define RDA_CFG_REGS_SIZE     SZ_4K
+
+#define RDA_MODEM_SPI2_BASE   0x11A14000
+#define RDA_MODEM_SPI2_SIZE   SZ_4K
+
+#define RDA_MODEM_XCPU_BASE   0x11A16000
+#define RDA_MODEM_XCPU_SIZE   SZ_4K
+
+#define RDA_MODEM_BCPU_BASE   0x1190D000
+#define RDA_MODEM_BCPU_SIZE   SZ_4K
+
+#define RDA_MD_PSRAM_BASE     (RDA_MODEM_BASE + 0x02000000)
+#define RDA_MD_PSRAM_SIZE     SZ_16M
+
+#define RDA_CAMERA_BASE       0x20000000
+#define RDA_CAMERA_SIZE       SZ_256K
+
+#define RDA_GOUDA_MEM_BASE    0x20040000
+#define RDA_GOUDA_MEM_SIZE    SZ_256K
+
+#define RDA_GPU_BASE          0x20080000
+#define RDA_GPU_SIZE          SZ_256K
+
+#define RDA_VOC_BASE          0x200C0000
+#define RDA_VOC_SIZE          SZ_256K
+
+#define RDA_VOC2_BASE         0x20100000
+#define RDA_VOC2_SIZE         SZ_256K
+
+#define RDA_USB_BASE          0x20400000
+#define RDA_USB_SIZE          SZ_256K
+
+#define RDA_SPIFLASH_BASE     0x20440000
+#define RDA_SPIFLASH_SIZE     SZ_256K
+
+#define RDA_CONNECT_BASE      0x21000000
+#define RDA_CONNECT_SIZE      SZ_4K
+
+#define RDA_L2CC_BASE         0x21100000
+#define RDA_L2CC_SIZE         SZ_4K
+
+/* APB0 */
+#define RDA_INTC_BASE         0x20800000
+#define RDA_INTC_SIZE         SZ_4K
+
+#define RDA_IMEM_BASE         0x20810000
+#define RDA_IMEM_SIZE         SZ_4K
+
+#define RDA_DMA_BASE          0x20820000
+#define RDA_DMA_SIZE          SZ_4K
+
+#define RDA_VPU_BASE          0x20830000
+#define RDA_VPU_SIZE          SZ_64K
+
+#define RDA_GOUDA_BASE        0x20840000
+#define RDA_GOUDA_SIZE        SZ_4K
+
+#define RDA_CAMERA_DMA_BASE   0x20850000
+#define RDA_CAMERA_DMA_SIZE   SZ_4K
+
+/* APB1 */
+#define RDA_SYSCTRL_BASE      0x20900000
+#define RDA_SYSCTRL_SIZE      SZ_4K
+
+#define RDA_TIMER_BASE        0x20910000
+#define RDA_TIMER_SIZE        SZ_4K
+
+#define RDA_KEYPAD_BASE       0x20920000
+#define RDA_KEYPAD_SIZE       SZ_4K
+
+#define RDA_GPIO_A_BASE       0x20930000
+#define RDA_GPIO_A_SIZE       SZ_4K
+
+#define RDA_GPIO_B_BASE       0x20931000
+#define RDA_GPIO_B_SIZE       SZ_4K
+
+#define RDA_GPIO_D_BASE       0x20932000
+#define RDA_GPIO_D_SIZE       SZ_4K
+
+#define RDA_PWM_BASE          0x20940000
+#define RDA_PWM_SIZE          SZ_4K
+
+#define RDA_I2C1_BASE         0x20950000
+#define RDA_I2C1_SIZE         SZ_4K
+
+#define RDA_I2C2_BASE         0x20960000
+#define RDA_I2C2_SIZE         SZ_4K
+
+#define RDA_I2C3_BASE         0x20970000
+#define RDA_I2C3_SIZE         SZ_4K
+
+#define RDA_COMREGS_BASE      0x20980000
+#define RDA_COMREGS_SIZE      SZ_4K
+
+#define RDA_DMC400_BASE       0x20990000
+#define RDA_DMC400_SIZE       SZ_4K
+
+#define RDA_DDRPHY_BASE       0x209A0000
+#define RDA_DDRPHY_SIZE       SZ_4K
+
+#define RDA_APDEBUG_BASE      0x209B0000
+#define RDA_APDEBUG_SIZE      SZ_4K
+
+#define RDA_AIF_BASE          0x209E0000
+#define RDA_AIF_SIZE          SZ_4K
+
+#define RDA_AUIFC_BASE        0x209F0000
+#define RDA_AUIFC_SIZE        SZ_4K
+
+/* APB2 */
+#define RDA_UART1_BASE        0x20A00000
+#define RDA_UART1_SIZE        SZ_4K
+
+#define RDA_UART2_BASE        0x20A10000
+#define RDA_UART2_SIZE        SZ_4K
+
+#define RDA_SPI1_BASE         0x20A20000
+#define RDA_SPI1_SIZE         SZ_4K
+
+#define RDA_SPI2_BASE         0x20A30000
+#define RDA_SPI2_SIZE         SZ_4K
+
+#define RDA_SPI3_BASE         0x20A40000
+#define RDA_SPI3_SIZE         SZ_4K
+
+#define RDA_SDMMC1_BASE       0x20A50000
+#define RDA_SDMMC1_SIZE       SZ_4K
+
+#define RDA_SDMMC2_BASE       0x20A60000
+#define RDA_SDMMC2_SIZE       SZ_4K
+
+#define RDA_SDMMC3_BASE       0x20A70000
+#define RDA_SDMMC3_SIZE       SZ_4K
+
+#define RDA_NAND_BASE         0x20A80000
+#define RDA_NAND_SIZE         SZ_16K
+
+#define RDA_UART3_BASE        0x20A90000
+#define RDA_UART3_SIZE        SZ_16K
+
+#define RDA_IFC_BASE          0x20AF0000
+#define RDA_IFC_SIZE          SZ_4K
+
+#endif /* __IOMAP_RDA8850_H */
diff --git a/arch/arm/include/asm/arch-rda/iomap_rda8850e.h b/arch/arm/include/asm/arch-rda/iomap_rda8850e.h
new file mode 100644
index 0000000000..dfa6a7e781
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/iomap_rda8850e.h
@@ -0,0 +1,184 @@
+#ifndef __IOMAP_RDA8850_H
+#define __IOMAP_RDA8850_H
+
+#define RDA_SRAM_BASE         0x00100000
+#define RDA_SRAM_SIZE         SZ_64K
+
+#define RDA_MD_MAILBOX_BASE   0x00200000
+#define RDA_MD_MAILBOX_SIZE   SZ_8K
+
+#define RDA_MODEM_BASE        0x10000000
+#define RDA_MODEM_SIZE        SZ_256M
+
+#define RDA_MD_SYSCTRL_BASE   0x11A00000
+#define RDA_MD_SYSCTRL_SIZE   SZ_4K
+
+#define RDA_GPIO_BASE         0x11A08000
+#define RDA_GPIO_SIZE         SZ_4K
+
+#define RDA_CFG_REGS_BASE     0x11A09000
+#define RDA_CFG_REGS_SIZE     SZ_4K
+
+#define RDA_CFG_RF_SPI_BASE 0x11A0E000
+#define RDA_CFG_SIZE SZ_4K
+
+#define RDA_MODEM_SPI2_BASE   0x11A14000
+#define RDA_MODEM_SPI2_SIZE   SZ_4K
+
+#define RDA_MODEM_XCPU_BASE   0x11A16000
+#define RDA_MODEM_XCPU_SIZE   SZ_4K
+
+#define RDA_MODEM_BCPU_BASE   0x11909000
+#define RDA_MODEM_BCPU_SIZE   SZ_4K
+
+#define RDA_MD_PSRAM_BASE     (RDA_MODEM_BASE + 0x02000000)
+#define RDA_MD_PSRAM_SIZE     SZ_4M
+
+#define RDA_CAMERA_BASE       0x20000000
+#define RDA_CAMERA_SIZE       SZ_256K
+
+#define RDA_GOUDA_MEM_BASE    0x20040000
+#define RDA_GOUDA_MEM_SIZE    SZ_256K
+
+#define RDA_VOC_BASE          0x200C0000
+#define RDA_VOC_SIZE          SZ_256K
+
+#define RDA_USB_BASE          0x20400000
+#define RDA_USB_SIZE          SZ_256K
+
+#define RDA_SPIFLASH_BASE     0x20440000
+#define RDA_SPIFLASH_SIZE     SZ_256K
+
+#define RDA_CONNECT_BASE      0x21000000
+#define RDA_CONNECT_SIZE      SZ_4K
+
+#define RDA_L2CC_BASE         0x21100000
+#define RDA_L2CC_SIZE         SZ_4K
+
+/* APB0 */
+#define RDA_INTC_BASE         0x20800000
+#define RDA_INTC_SIZE         SZ_64K
+
+#define RDA_IMEM_BASE         0x20810000
+#define RDA_IMEM_SIZE         SZ_64K
+
+#define RDA_DMA_BASE          0x20820000
+#define RDA_DMA_SIZE          SZ_64K
+
+#define RDA_VPU_BASE          0x20830000
+#define RDA_VPU_SIZE          SZ_64K
+
+#define RDA_GOUDA_BASE        0x20840000
+#define RDA_GOUDA_SIZE        SZ_64K
+
+#define RDA_CAMERA_DMA_BASE   0x20850000
+#define RDA_CAMERA_DMA_SIZE   SZ_64K
+
+#define RDA_LCDC_BASE         0x20860000
+#define RDA_LCDC_SIZE         SZ_664K
+
+#define RDA_GPU_BASE          0x20870000
+#define RDA_GPU_SIZE          SZ_64K
+
+#define RDA_JPEG_BASE         0x20890000
+#define RDA_JPEG_SIZE         SZ_64K
+
+#define RDA_CPU_DEBUG_BASE    0x208C0000
+#define RDA_CPU_DEBUG_SIZE    SZ_256K
+
+/* APB1 */
+#define RDA_SYSCTRL_BASE      0x20900000
+#define RDA_SYSCTRL_SIZE      SZ_64K
+
+#define RDA_TIMER_BASE        0x20910000
+#define RDA_TIMER_SIZE        SZ_64K
+
+#define RDA_KEYPAD_BASE       0x20920000
+#define RDA_KEYPAD_SIZE       SZ_64K
+
+#define RDA_GPIO_A_BASE       0x20930000
+#define RDA_GPIO_A_SIZE       SZ_4K
+
+#define RDA_GPIO_B_BASE       0x20931000
+#define RDA_GPIO_B_SIZE       SZ_4K
+
+#define RDA_GPIO_D_BASE       0x20932000
+#define RDA_GPIO_D_SIZE       SZ_4K
+
+#define RDA_PWM_BASE          0x20940000
+#define RDA_PWM_SIZE          SZ_4K
+
+#define RDA_TV_CLK_CTRL_BASE  0x20960000
+#define RDA_TV_CLK_CTRL_SIZE  SZ_64K
+
+#define RDA_COMREGS_BASE      0x20980000
+#define RDA_COMREGS_SIZE      SZ_4K
+
+#define RDA_DMC400_BASE       0x20990000
+#define RDA_DMC400_SIZE       SZ_4K
+
+#define RDA_DDRPHY_BASE       0x209A0000
+#define RDA_DDRPHY_SIZE       SZ_4K
+
+#define RDA_APDEBUG_BASE      0x209B0000
+#define RDA_APDEBUG_SIZE      SZ_4K
+
+#define RDA_AIF2_BASE         0x209D0000
+#define RDA_AIF2_SIZE         SZ_64K
+
+#define RDA_AIF_BASE          0x209E0000
+#define RDA_AIF_SIZE          SZ_4K
+
+#define RDA_AUIFC_BASE        0x209F0000
+#define RDA_AUIFC_SIZE        SZ_4K
+
+/* APB2 */
+#define RDA_UART1_BASE        0x20A00000
+#define RDA_UART1_SIZE        SZ_4K
+
+#define RDA_UART2_BASE        0x20A10000
+#define RDA_UART2_SIZE        SZ_4K
+
+#define RDA_SPI1_BASE         0x20A20000
+#define RDA_SPI1_SIZE         SZ_4K
+
+#define RDA_SPI2_BASE         0x20A30000
+#define RDA_SPI2_SIZE         SZ_4K
+
+#define RDA_SPI3_BASE         0x20A40000
+#define RDA_SPI3_SIZE         SZ_4K
+
+#define RDA_SDMMC1_BASE       0x20A50000
+#define RDA_SDMMC1_SIZE       SZ_4K
+
+#define RDA_SDMMC2_BASE       0x20A60000
+#define RDA_SDMMC2_SIZE       SZ_4K
+
+#define RDA_SDMMC3_BASE       0x20A70000
+#define RDA_SDMMC3_SIZE       SZ_4K
+
+#define RDA_NAND_BASE         0x20A80000
+#define RDA_NAND_SIZE         SZ_64K
+
+#define RDA_UART3_BASE        0x20A90000
+#define RDA_UART3_SIZE        SZ_16K
+
+#define RDA_GIC_BASE          0x20AA0000
+#define RDA_GIC_SIZE          SZ_64K
+
+#define RDA_I2C1_BASE         0x20AB0000
+#define RDA_I2C1_SIZE         SZ_64K
+
+#define RDA_I2C2_BASE         0x20AC0000
+#define RDA_I2C2_SIZE         SZ_64K
+
+#define RDA_I2C3_BASE         0x20AD0000
+#define RDA_I2C3_SIZE         SZ_64K
+
+#define RDA_UART4_BASE        0x20AE0000
+#define RDA_UART4_SIZE        SZ_64K
+
+#define RDA_IFC_BASE          0x20AF0000
+#define RDA_IFC_SIZE          SZ_4K
+
+#endif /* __IOMAP_RDA8850_H */
diff --git a/arch/arm/include/asm/arch-rda/iomap_rdaarm926ejs.h b/arch/arm/include/asm/arch-rda/iomap_rdaarm926ejs.h
new file mode 100644
index 0000000000..8bc634f72f
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/iomap_rdaarm926ejs.h
@@ -0,0 +1,48 @@
+#ifndef __IOMAP_RDAARM926EJS_H
+#define __IOMAP_RDAARM926EJS_H
+
+#include <asm/sizes.h>
+
+#define RDA_INTC_BASE         0x01AF0000
+#define RDA_INTC_SIZE         SZ_4K
+
+#define RDA_TIMER_BASE        0x01A02000
+#define RDA_TIMER_SIZE        SZ_4K
+
+#define RDA_GPIO_BASE         0x01A03000
+#define RDA_GPIO_SIZE         SZ_4K
+
+#define RDA_KEYPAD_BASE       0x01A05000
+#define RDA_KEYPAD_SIZE       SZ_4K
+
+#define RDA_I2C1_BASE         0x01A07000
+#define RDA_I2C1_SIZE         SZ_4K
+
+#define RDA_I2C2_BASE         0x01A22000
+#define RDA_I2C2_SIZE         SZ_4K
+
+#define RDA_I2C3_BASE         0x01A23000
+#define RDA_I2C3_SIZE         SZ_4K
+
+#define RDA_IFC_BASE          0x01A09000
+#define RDA_IFC_SIZE          SZ_4K
+
+#define RDA_UART1_BASE        0x01A15000
+#define RDA_UART1_SIZE        SZ_4K
+
+#define RDA_UART2_BASE        0x01A16000
+#define RDA_UART2_SIZE        SZ_4K
+
+#define RDA_SDMMC1_BASE       0x01A17000
+#define RDA_SDMMC1_SIZE       SZ_4K
+
+#define RDA_GOUDA_BASE        0x01A21000
+#define RDA_GOUDA_SIZE        SZ_4K
+
+#define RDA_NAND_BASE         0x01A26000
+#define RDA_NAND_SIZE         SZ_16K
+
+#define RDA_USB_BASE          0x01A80000
+#define RDA_USB_SIZE          SZ_64K
+
+#endif /* __IOMAP_RDAARM926EJS_H */
diff --git a/arch/arm/include/asm/arch-rda/irqs.h b/arch/arm/include/asm/arch-rda/irqs.h
new file mode 100644
index 0000000000..9812d0014d
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/irqs.h
@@ -0,0 +1,58 @@
+/* include/asm-arm/arch-goldfish/irqs.h
+**
+** Copyright (C) 2007 Google, Inc.
+**
+** This software is licensed under the terms of the GNU General Public
+** License version 2, as published by the Free Software Foundation, and
+** may be copied, distributed, and modified under those terms.
+**
+** This program is distributed in the hope that it will be useful,
+** but WITHOUT ANY WARRANTY; without even the implied warranty of
+** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+** GNU General Public License for more details.
+**
+*/
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#define RDA_IRQ_PULSE_DUMMY    0
+#define RDA_IRQ_I2C            1
+#define RDA_IRQ_NAND_NFSC      2
+#define RDA_IRQ_SDMMC1         3
+#define RDA_IRQ_SDMMC2         4
+#define RDA_IRQ_SDMMC3         5
+#define RDA_IRQ_SPI1           6
+#define RDA_IRQ_SPI2           7
+#define RDA_IRQ_SPI3           8
+#define RDA_IRQ_UART1          9
+#define RDA_IRQ_UART2          10
+#define RDA_IRQ_UART3          11
+#define RDA_IRQ_GPIO1          12
+#define RDA_IRQ_GPIO2          13
+#define RDA_IRQ_GPIO3          14
+#define RDA_IRQ_KEYPAD         15
+#define RDA_IRQ_TIMER          16
+#define RDA_IRQ_TIMEROS        17
+#define RDA_IRQ_COMREG0        18
+#define RDA_IRQ_COMREG1        19
+#define RDA_IRQ_USB            20
+#define RDA_IRQ_DMC            21
+#define RDA_IRQ_DMA            22
+#define RDA_IRQ_CAMERA         23
+#define RDA_IRQ_GOUDA          24
+#define RDA_IRQ_GPU            25
+#define RDA_IRQ_VPU_JPG        26
+#define RDA_IRQ_VPU_HOST       27
+#define RDA_IRQ_VOC            28
+#define RDA_IRQ_AUIFC0         29
+#define RDA_IRQ_AUIFC1         30
+#define RDA_IRQ_L2CC           31
+
+#define RDA_IRQ_NUM            32
+
+#define RDA_IRQ_MASK_ALL       0xFFFFFFFF
+
+#define NR_IRQS         RDA_IRQ_NUM
+
+#endif
diff --git a/arch/arm/include/asm/arch-rda/ispi.h b/arch/arm/include/asm/arch-rda/ispi.h
new file mode 100644
index 0000000000..eabec39107
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/ispi.h
@@ -0,0 +1,12 @@
+#ifndef __ISPI_H__
+#define __ISPI_H_
+
+#define pmu_reg_write ispi_reg_write
+#define pmu_reg_read ispi_reg_read
+
+void ispi_open(int modemSpi);
+void ispi_reg_write(u32 regIdx, u32 value);
+u32 ispi_reg_read(u32 regIdx);
+u16 rda_read_efuse(int page_index);
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/mdcom.h b/arch/arm/include/asm/arch-rda/mdcom.h
new file mode 100644
index 0000000000..ffb520c5c9
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/mdcom.h
@@ -0,0 +1,166 @@
+#ifndef  _MDCOM_H_
+#define  _MDCOM_H_
+
+#ifdef RDA_MDCOM_DEBUG
+#define rdamddbg(fmt,args...)	printf (fmt ,##args)
+#else
+#define rdamddbg(fmt,args...)
+#endif /* RDA_MDCOM_DEBUG */
+
+/*
+ * Note :
+ * The number of version will be updated according to version of BP.
+ */
+#define RDA_BP_VER		0x00010001
+
+
+typedef enum
+{
+	/* Normal cause, ie power up */
+	RDA_RESET_CAUSE_NORMAL = 0x0,
+	/* The reset was caused by a watchdog */
+	RDA_RESET_CAUSE_WATCHDOG = 0x1,
+	/* The reset was caused by a soft restart, triggered by the function */
+	RDA_RESET_CAUSE_RESTART = 0x2,
+	/* The reset was initiated from the Host Interface. */
+	RDA_RESET_CAUSE_HOST_DEBUG = 0x3,
+	/* The reset was caused by alarm, from the calendar. */
+	RDA_RESET_CAUSE_ALARM = 0x4,
+
+	RDA_RESET_CAUSE_CHARGER = 0x80,
+
+	RDA_RESET_CAUSE_QTY
+
+} RDA_RESET_CAUSE_T;
+
+/*
+ * PORT, LINE
+ */
+typedef enum {
+	RDA_MDCOM_PORT0,
+	RDA_MDCOM_PORT1,
+} rda_mdcom_port_id_t;
+
+typedef enum {
+	RDA_MDCOM_LINE_MODEM_RESET,   // inform AP Modem reset done
+	RDA_MDCOM_LINE_DL_HANDSHAKE,  // for AP download BB code
+	RDA_MDCOM_LINE_CMD_START,     // for port1 command start
+	RDA_MDCOM_LINE_SLEEP_WAKEUP,  // for sleep/wakeup status
+	RDA_MDCOM_LINE_EXCEPTION,     // for exception
+} rda_mdcom_port0_line_id_t;
+
+typedef enum {
+	RDA_MDCOM_LINE_AT_CMD,        // for AT command
+	RDA_MDCOM_LINE_AT_CMD_FC,     // for AT command Flow control
+	RDA_MDCOM_LINE_SYSTEM,        // for SYSTEM command
+	RDA_MDCOM_LINE_SYSTEM_FC,     // for AT command Flow control
+	RDA_MDCOM_LINE_TRACE,		  // for Trace communciation
+	RDA_MDCOM_LINE_TRACE_FC,	  // for Trace communciation Flow control
+} rda_mdcom_port1_line_id_t;
+
+void rda_mdcom_set_logic_base_addr(u32 base);
+
+u32 rda_mdcom_address_modem2ap(u32 addr);
+
+int rda_mdcom_setup_run_env(u32 pc, u32 param);
+
+void rda_mdcom_get_calib_section(u32 *addr, u32 *len);
+void rda_mdcom_get_ext_calib_section(u32 *addr, u32 *len);
+void rda_mdcom_get_factory_section(u32 *addr, u32 *len);
+void rda_mdcom_get_ap_factory_section(u32 *addr, u32 *len);
+
+u32 rda_mdcom_get_reset_cause(void);
+u32 rda_mdcom_get_interface_version(void);
+
+int rda_mdcom_system_started_before(void);
+void rda_mdcom_set_system_started_flag(void);
+int rda_mdcom_modem_crashed_before(void);
+int rda_mdcom_calib_update_cmd_valid(void);
+int rda_mdcom_factory_update_cmd_valid(void);
+int rda_mdcom_ap_factory_update_cmd_valid(void);
+
+void rda_mdcom_init_all_log_info(void);
+void rda_mdcom_get_modem_log_info(u32 *addr, u32 *len);
+void rda_mdcom_get_modem_exception_info(u32 *addr, u32 *len);
+
+void rda_mdcom_show_xcpu_info(void);
+void rda_mdcom_show_software_version(void);
+
+int rda_mdcom_init_port(int port_id);
+
+int rda_mdcom_line_set(int port_id, int line_id);
+int rda_mdcom_line_set_check(int port_id, int line_id);
+int rda_mdcom_line_set_wait(int port_id, int line_id, int waittime);
+
+int rda_mdcom_line_clear(int port_id, int line_id);
+int rda_mdcom_line_clear_check(int port_id, int line_id);
+int rda_mdcom_line_clear_wait(int port_id, int line_id, int waittime);
+
+void rda_mdcom_port_show(void);
+
+typedef enum {
+	RDA_MDCOM_CHANNEL_AT,		// for AT command
+	RDA_MDCOM_CHANNEL_SYSTEM,	// for SYSTEM command
+	RDA_MDCOM_CHANNEL_TRACE,	// for Trace communication
+} rda_mdcom_channel_id_t;
+
+struct rda_mdcom_channel_head {
+	volatile int read_offset;	// offset of the read pointer
+	volatile int write_offset;	// offset of the write pointer
+	volatile int reserved0;		// reserved
+	volatile int reserved1;		// reserved
+};
+
+struct rda_mdcom_channel {
+	int data_line_id;
+	int fc_line_id;
+
+	// the address of 16-byte buffer head
+	struct rda_mdcom_channel_head* read_buf_head;
+	void* read_buf;			// the start address of modem to AP buffer
+	int read_buf_size_mask;		// the mask of modem to AP buffer size
+
+	// the address of 16-byte buffer head
+	struct rda_mdcom_channel_head* write_buf_head;
+	void* write_buf;		// the start address of AP to modem buffer
+	int write_buf_size_mask;	// the mask of AP to modem buffer size
+};
+
+int rda_mdcom_channel_init(const unsigned int channel);
+int rda_mdcom_channel_all_init(void);
+int rda_mdcom_channel_buf_send_stream(const unsigned int channel, void *buf, int size, int waittime);
+int rda_mdcom_channel_buf_send_dgram(const unsigned int channel, void *buf, int size, int waittime);
+int rda_mdcom_channel_buf_recv_stream(const unsigned int channel, void *buf, int size, int waittime);
+int rda_mdcom_channel_buf_recv_dgram(const unsigned int channel, void *buf, int size, int waittime);
+int rda_mdcom_channel_buf_send_available(const unsigned int channel);
+int rda_mdcom_channel_buf_recv_available(const unsigned int channel);
+void rda_mdcom_channel_show(const unsigned int channel);
+
+/*
+ * AT COMMAND Channel
+ */
+/* emulate a tty device */
+int rda_mdcom_tstc(const unsigned int channel);
+int rda_mdcom_getc(const unsigned int channel);
+void rda_mdcom_putc(const char c, const unsigned int channel);
+void rda_mdcom_puts(const char *s, const unsigned int channel);
+
+/*
+ * SYSTEM MESSAGE Channel
+ */
+int rda_mdcom_send_sys_msg(
+	struct rda_mdcom_channel *channel,
+	int msg_id,
+	void *send_msg, int send_size,
+	void *response, int resp_buf_size,
+	int *resp_size
+);
+
+int rda_mdcom_parse_sys_msg(
+	struct rda_mdcom_channel *channel,
+	int msg_id,
+	void *send_msg, int send_size,
+	void *response, int *resp_size
+);
+
+#endif //  _MDCOM_H_
diff --git a/arch/arm/include/asm/arch-rda/mtdparts_def.h b/arch/arm/include/asm/arch-rda/mtdparts_def.h
new file mode 100644
index 0000000000..57652abdb6
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/mtdparts_def.h
@@ -0,0 +1,58 @@
+#ifndef __ASM_ARCH_MTDPARTS_DEF_H
+#define __ASM_ARCH_MTDPARTS_DEF_H
+
+#include <rda/tgt_ap_flash_parts.h>
+
+
+#define SEPARATOR "#"
+
+#define SYSTEM_PKT_LEN	"4096"
+
+#define DEFAULT_FSIMG_PKT_LEN   "4096"
+
+#define USERDATA_IMAGE_ATTR	\
+	"userdata("	\
+	DEFAULT_FSIMG_PKT_LEN	\
+	")"
+
+#define CUSTOMER_IMAGE_ATTR	\
+	"customer("	\
+	DEFAULT_FSIMG_PKT_LEN	\
+	")"
+
+#define VENDOR_IMAGE_ATTR	\
+	"vendor("	\
+	DEFAULT_FSIMG_PKT_LEN	\
+	")"
+
+#define SYSTEM_IMAGE_ATTR	\
+	"system("	\
+	SYSTEM_PKT_LEN	\
+	")"
+
+#define CACHE_IMAGE_ATTR	\
+	"cache("	\
+	DEFAULT_FSIMG_PKT_LEN	\
+	")"
+
+#define IMAGE_ATTR	\
+	"pdl(8)"	\
+	SEPARATOR	\
+	"bootloader(4096)"	\
+	SEPARATOR	\
+	"modem(4096)"	\
+	SEPARATOR	\
+	"boot(4096)"	\
+	SEPARATOR	\
+	SYSTEM_IMAGE_ATTR	\
+	SEPARATOR	\
+	CUSTOMER_IMAGE_ATTR	\
+	SEPARATOR	\
+	VENDOR_IMAGE_ATTR	\
+	SEPARATOR	\
+	USERDATA_IMAGE_ATTR	\
+	SEPARATOR	\
+	CACHE_IMAGE_ATTR	\
+	SEPARATOR	\
+	"recovery(4096)"
+#endif /* __ASM_ARCH_MTDPARTS_DEF_H */
diff --git a/arch/arm/include/asm/arch-rda/prdinfo.h b/arch/arm/include/asm/arch-rda/prdinfo.h
new file mode 100644
index 0000000000..13ee77a5c6
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/prdinfo.h
@@ -0,0 +1,62 @@
+#ifndef __PRDINFO_H__
+#define __PRDINFO_H__
+
+#define PRDINFO_PART_NAME	"misc"
+#define PRDINFO_TOTAL_SIZE	(16*1024)
+
+/* 0 ~ 1024, produce infomation,
+   includes pdl/calibration/test results */
+#define PRDINFO_DATA_OFFSET		0
+#define PRDINFO_DATA_MAX_SIZE	1024
+#define PDL_IMAGE_MAX_NUM		16
+#define PDL_IMAGE_NAME_LEN		31
+#define FACTORY_TAG_NUM		0xFAC12345
+struct prdinfo
+{
+	uint8_t pdl_result;
+	uint8_t cali_result;
+	uint8_t autocall_result;
+	uint8_t factorytest_result;
+
+	uint32_t pdl_image_count;
+	struct {
+		char name[PDL_IMAGE_NAME_LEN];
+		uint8_t result;
+	} pdl_images[PDL_IMAGE_MAX_NUM];
+
+	uint32_t factory_tag; /* force to factory mode */
+
+	uint8_t imei_result;
+	uint8_t psn_result;
+	uint8_t mbsn_result;
+	uint8_t macaddr_result;
+	uint8_t btaddr_result;
+
+	uint8_t reserve[27];
+};
+
+/* 1024 ~ (PRDINFO_TOTAL_SIZE - 4), reserved */
+
+/* (PRDINFO_TOTAL_SIZE - 4) ~ PRDINFO_TOTAL_SIZE,
+   crc for all (PRDINFO_TOTAL_SIZE-4) data */
+#define PRDINFO_CRC_OFFSET	(PRDINFO_TOTAL_SIZE-4)
+#define PRDINFO_CRC_SIZE	4
+
+
+/* related functions int u-boot */
+int prdinfo_init(char *image_list);
+int prdinfo_load(void);
+int prdinfo_save(void);
+int prdinfo_update_all(char *buf, unsigned long sz);
+void prdinfo_dump(void);
+int prdinfo_set_data(struct prdinfo *info);
+int prdinfo_get_data(struct prdinfo *info);
+int prdinfo_set_pdl_result(uint8_t rt, uint32_t ftm_tag);
+int prdinfo_set_cali_result(uint8_t rt);
+int prdinfo_set_autocall_result(uint8_t rt);
+int prdinfo_set_coupling_result(uint8_t rt);
+int prdinfo_set_factorytest_result(uint8_t rt);
+int prdinfo_set_pdl_image_download_result(char *image_name, uint8_t dl_rt);
+uint32_t prdinfo_get_factory_tag(void);
+
+#endif
diff --git a/arch/arm/include/asm/arch-rda/rda_crypto.h b/arch/arm/include/asm/arch-rda/rda_crypto.h
new file mode 100644
index 0000000000..db957d2fdd
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/rda_crypto.h
@@ -0,0 +1,11 @@
+#ifndef __RDA_CRYPTO_H__
+
+#include <image.h>
+#include <asm/arch/spl_board_info.h>
+
+int set_security_context(struct spl_security_info *info, const void *image);
+
+int image_sign_verify_uimage(image_header_t *hdr);
+int image_sign_verify(const uint8_t *buffer, uint32_t len);
+
+#endif
diff --git a/arch/arm/include/asm/arch-rda/rda_iomap.h b/arch/arm/include/asm/arch-rda/rda_iomap.h
new file mode 100644
index 0000000000..0b71f96d50
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/rda_iomap.h
@@ -0,0 +1,25 @@
+#ifndef __IOMAP_H
+#define __IOMAP_H
+
+#include <common.h>
+
+#ifdef CONFIG_MACH_RDAARM926EJS
+#include "iomap_rdaarm926ejs.h"
+#elif defined(CONFIG_MACH_RDA8810)
+#include "iomap_rda8810.h"
+#elif defined(CONFIG_MACH_RDA8810E)
+#include "iomap_rda8810e.h"
+#elif defined(CONFIG_MACH_RDA8820)
+#include "iomap_rda8820.h"
+#elif defined(CONFIG_MACH_RDA8850)
+#include "iomap_rda8850.h"
+#elif defined(CONFIG_MACH_RDA8850E)
+#include "iomap_rda8850e.h"
+#elif defined(CONFIG_MACH_RDA8810H)
+#include "iomap_rda8810h.h"
+#else
+#error "No MACH defined"
+#endif
+
+#endif // __IOMAP_H
+
diff --git a/arch/arm/include/asm/arch-rda/rda_sys.h b/arch/arm/include/asm/arch-rda/rda_sys.h
new file mode 100644
index 0000000000..8c81a0e473
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/rda_sys.h
@@ -0,0 +1,67 @@
+#ifndef __RDA_SYS_H__
+#define __RDA_SYS_H__
+
+/*RDA_BOOTMODE_TYPE*/
+#define    RDA_MODE_EMMC                0
+#define    RDA_MODE_SPINAND             1
+#define    RDA_MODE_SPINOR              2
+#define    RDA_MODE_TCARD_RUN           3
+#define    RDA_MODE_TCARD_UPDATE        4
+#define    RDA_MODE_NAND_8BIT           5
+#define    RDA_MODE_NAND_16BIT          6
+#define    RDA_MODE_RESERVED            7
+
+#define RDA_HW_CFG_GET_BM_IDX(r)     (((r)>>0)&0x7)
+
+enum media_type {
+	MEDIA_NAND = 0x10,
+	MEDIA_MMC = 0x11,
+	MEDIA_SPINAND = 0x12,
+	MEDIA_UNKNOWN = 0xff,
+};
+enum media_type rda_media_get(void);
+u16 rda_metal_id_get(void);
+void shutdown_system(void);
+
+int rda_bm_is_calib(void);
+int rda_bm_is_autocall(void);
+int rda_bm_is_download(void);
+int rda_bm_download_key_pressed(void);
+
+enum reboot_type {
+	REBOOT_TO_NORMAL_MODE,
+	REBOOT_TO_DOWNLOAD_MODE,
+	REBOOT_TO_FASTBOOT_MODE,
+	REBOOT_TO_RECOVERY_MODE,
+	REBOOT_TO_CALIB_MODE,
+	REBOOT_TO_PDL2_MODE,
+};
+void rda_reboot(enum reboot_type type);
+
+void enable_vibrator(int enable);
+void enable_charger(int enable);
+
+void rda_dump_buf(char *data, size_t len);
+void print_cur_time(void);
+
+#ifdef CONFIG_CMD_MISC
+int usb_cable_connected(void);
+int system_rebooted(void);
+void save_current_boot_key_state(void);
+int get_saved_boot_key_state(void);
+enum rda_bm_type
+{
+	RDA_BM_NORMAL = 0,
+	RDA_BM_CALIB = 1,
+	RDA_BM_FACTORY = 2,
+	RDA_BM_FASTBOOT = 3,
+	RDA_BM_RECOVERY = 4,
+	RDA_BM_AUTOCALL = 5,
+	RDA_BM_FORCEDOWNLOAD = 6,
+};
+void rda_bm_init(void);
+enum rda_bm_type rda_bm_get(void);
+void rda_bm_set(enum rda_bm_type bm);
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-rda/reg_camera.h b/arch/arm/include/asm/arch-rda/reg_camera.h
new file mode 100644
index 0000000000..5b76edbacd
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_camera.h
@@ -0,0 +1,4 @@
+#ifdef CONFIG_MACH_RDA8850E
+#include "reg_camera_rda8850e.h"
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/reg_camera_rda8850e.h b/arch/arm/include/asm/arch-rda/reg_camera_rda8850e.h
new file mode 100644
index 0000000000..610428b058
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_camera_rda8850e.h
@@ -0,0 +1,397 @@
+//==============================================================================
+//
+//            Copyright (C) 2012-2021,RDA, Inc.
+//                            All Rights Reserved
+//
+//      This source code is the property of Coolsand Technologies and is
+//      confidential.  Any  modification, distribution,  reproduction or
+//      exploitation  of  any content of this file is totally forbidden,
+//      except  with the  written permission  of  RDA.
+//
+//==============================================================================
+
+
+#ifndef _CAMERA_H_
+#define _CAMERA_H_
+
+#include "cs_types.h"
+
+#include "iomap_rda8850e.h"
+// =============================================================================
+//  MACROS
+// =============================================================================
+#define FIFORAM_SIZE                             (128)
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+// ============================================================================
+// CAMERA_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+#define REG_CAMERA_BASE             RDA_CAMERA_BASE
+
+typedef volatile struct
+{
+	REG32	CTRL;                         //0x00000000
+	REG32	STATUS;                       //0x00000004
+	REG32	DATA;                         //0x00000008
+	REG32	IRQ_MASK;                     //0x0000000C
+	REG32	IRQ_CLEAR;                    //0x00000010
+	REG32	IRQ_CAUSE;                    //0x00000014
+	REG32	CMD_SET;                      //0x00000018
+	REG32	CMD_CLR;                      //0x0000001C
+	REG32	DSTWINCOL;                    //0x00000020
+	REG32	DSTWINROW;                    //0x00000024
+	REG32	CLK_OUT;                      //0x00000028
+	REG32	SCALE_CFG;                    //0x0000002c
+	REG32	CAM_SPI_REG_0;                //0x00000030
+	REG32	CAM_SPI_REG_1;                //0x00000034
+	REG32	CAM_SPI_REG_2;                //0x00000038
+	REG32	CAM_SPI_REG_3;                //0x0000003c
+	REG32	CAM_SPI_REG_4;                //0x00000040
+	REG32	CAM_SPI_REG_5;                //0x00000044
+	REG32	CAM_SPI_REG_6;                //0x00000048
+	REG32	CAM_SPI_OBSERVE_REG_0;        //0x0000004c, read only
+	REG32	CAM_SPI_OBSERVE_REG_1;        //0x00000050, read only
+    	REG32	CSI_CONFIG_REG0;                         //0x00000054
+	REG32	CSI_CONFIG_REG1;                       //0x00000058
+	REG32	CSI_CONFIG_REG2;                         //0x0000005C
+	REG32	CSI_CONFIG_REG3;                     //0x00000060
+	REG32	CSI_CONFIG_REG4;                     //0x00000064
+	REG32	CSI_CONFIG_REG5;                     //0x00000068
+	REG32	CSI_CONFIG_REG6;                     //0x0000006C
+	REG32	CSI_CONFIG_REG7;                     //0x00000070
+	REG32	CSI_OBSERVE_REG4;                    //0x00000074
+	REG32	CSI_OBSERVE_REG5;                    //0x00000078
+	REG32	CSI_OBSERVE_REG6;                      //0x0000007C  read only
+	REG32	CSI_OBSERVE_REG7;                      //0x00000080   read only
+	REG32	CSI_ENABLE_PHY;				//0x00000084
+	REG32	DCT_SHIFTR_Y_REG0;				//0x00000088
+	REG32	DCT_SHIFTR_Y_REG1;				//0x0000008C
+	REG32	CAM_AXI_CONFIG;               //0x00000090
+	REG32	CAM_FRAME_START_ADDR;         //0x00000094
+	REG32	CAM_FRAME_SIZE;               //0x00000098
+	REG32	CAM_TC_COUNT;                 //0x0000009C
+	REG32	CAM_FRAME_START_U_ADDR;         //0x000000A0
+	REG32	CAM_FRAME_START_V_ADDR;         //0x000000A4
+	REG32	CAM_FRAME2_START_ADDR;         //0x000000A8
+	REG32	CAM_FRAME2_START_U_ADDR;         //0x000000AC
+	REG32	CAM_FRAME2_START_V_ADDR;         //0x000000B0
+	REG32	CFG_CAM_C2CSE;				//0x000000B4
+} HWP_CAMERA_T;
+
+#define hwp_camera                  ((HWP_CAMERA_T*) (REG_CAMERA_BASE))
+
+
+//CTRL
+#define CAMERA_ENABLE               (1<<0)
+#define CAMERA_ENABLE_ENABLE        (1<<0)
+#define CAMERA_ENABLE_DISABLE       (0<<0)
+#define CAMERA_DCT_ENABLE               (1<<1)
+#define CAMERA_DCT_DISABLE			(0<<1)
+#define CAMERA_1_BUFENABLE               (1<<2)
+#define CAMERA_1_BUFENABLE_ENABLE        (1<<2)
+#define CAMERA_1_BUFENABLE_DISABLE       (0<<2)
+#define CAMERA_OUT_CLK_GATE_EN (1 << 3)
+#define CAMERA_DATAFORMAT(n)        (((n)&3)<<4)
+#define CAMERA_DATAFORMAT_RGB565    (0<<4)
+#define CAMERA_DATAFORMAT_YUV422    (1<<4)
+#define CAMERA_DATAFORMAT_JPEG      (2<<4)
+#define CAMERA_DATAFORMAT_RESERVE   (3<<4)
+#define CAMERA_ISP_ENABLE			(1 << 6)
+#define CAMERA_RGB_RFIST		(1 << 7)
+#define CAMERA_RESET_POL            (1<<8)
+#define CAMERA_RESET_POL_INVERT     (1<<8)
+#define CAMERA_RESET_POL_NORMAL     (0<<8)
+#define CAMERA_PWDN_POL             (1<<9)
+#define CAMERA_PWDN_POL_INVERT      (1<<9)
+#define CAMERA_PWDN_POL_NORMAL      (0<<9)
+#define CAMERA_VSYNC_POL            (1<<10)
+#define CAMERA_VSYNC_POL_INVERT     (1<<10)
+#define CAMERA_VSYNC_POL_NORMAL     (0<<10)
+#define CAMERA_HREF_POL             (1<<11)
+#define CAMERA_HREF_POL_INVERT      (1<<11)
+#define CAMERA_HREF_POL_NORMAL      (0<<11)
+#define CAMERA_LINEBUF_ISP_ENABLE	(1 << 12)
+#define CAMERA_LINEBUF_IF	(1 << 13)
+#define CAMERA_VSYNC_DROP           (1<<14)
+#define CAMERA_VSYNC_DROP_DROP      (1<<14)
+#define CAMERA_VSYNC_DROP_NORMAL    (0<<14)
+#define CAMERA_DECIMFRM(n)          (((n)&3)<<16)
+#define CAMERA_DECIMFRM_ORIGINAL    (0<<16)
+#define CAMERA_DECIMFRM_DIV_2       (1<<16)
+#define CAMERA_DECIMFRM_DIV_3       (2<<16)
+#define CAMERA_DECIMFRM_DIV_4       (3<<16)
+#define CAMERA_DECIMCOL(n)          (((n)&3)<<18)
+#define CAMERA_DECIMCOL_ORIGINAL    (0<<18)
+#define CAMERA_DECIMCOL_DIV_2       (1<<18)
+#define CAMERA_DECIMCOL_DIV_3       (2<<18)
+#define CAMERA_DECIMCOL_DIV_4       (3<<18)
+#define CAMERA_DECIMROW(n)          (((n)&3)<<20)
+#define CAMERA_DECIMROW_ORIGINAL    (0<<20)
+#define CAMERA_DECIMROW_DIV_2       (1<<20)
+#define CAMERA_DECIMROW_DIV_3       (2<<20)
+#define CAMERA_DECIMROW_DIV_4       (3<<20)
+#define CAMERA_REORDER(n)           (((n)&7)<<24)
+#define CAMERA_CROPEN               (1<<28)
+#define CAMERA_CROPEN_ENABLE        (1<<28)
+#define CAMERA_CROPEN_DISABLE       (0<<28)
+#define CAMERA_BIST_MODE            (1<<30)
+#define CAMERA_BIST_MODE_BIST       (1<<30)
+#define CAMERA_BIST_MODE_NORMAL     (0<<30)
+#define CAMERA_TEST                 (1<<31)
+#define CAMERA_TEST_TEST            (1<<31)
+#define CAMERA_TEST_NORMAL          (0<<31)
+
+//STATUS
+#define CAMERA_OVFL                 (1<<0)
+#define CAMERA_VSYNC_R              (1<<1)
+#define CAMERA_VSYNC_F              (1<<2)
+#define CAMERA_DMA_DONE             (1<<3)
+#define CAMERA_FIFO_EMPTY           (1<<4)
+
+//DATA
+#define CAMERA_RX_DATA(n)           (((n)&0xFFFFFFFF)<<0)
+
+//IRQ_MASK
+//#define CAMERA_OVFL               (1<<0)
+//#define CAMERA_VSYNC_R            (1<<1)
+//#define CAMERA_VSYNC_F            (1<<2)
+//#define CAMERA_DMA_DONE           (1<<3)
+
+//IRQ_CLEAR
+//#define CAMERA_OVFL               (1<<0)
+//#define CAMERA_VSYNC_R            (1<<1)
+//#define CAMERA_VSYNC_F            (1<<2)
+//#define CAMERA_DMA_DONE           (1<<3)
+
+//IRQ_CAUSE
+//#define CAMERA_OVFL               (1<<0)
+//#define CAMERA_VSYNC_R            (1<<1)
+//#define CAMERA_VSYNC_F            (1<<2)
+//#define CAMERA_DMA_DONE           (1<<3)
+
+//CMD_SET,modified by xiankuiwei
+#define CAMERA_RESET                (1<<0)
+#define CAMERA_PWDN                 (1<<4)
+#define CAMERA_FIFO_RESET           (1<<8)
+
+//CMD_CLR
+//#define CAMERA_PWDN               (1<<4)
+//#define CAMERA_RESET              (1<<0)
+
+//DSTWINCOL,modified by xiankuiwei
+#define CAMERA_DSTWINCOLSTART(n)    (((n)&0xFFF)<<16)
+#define CAMERA_DSTWINCOLEND(n)      (((n)&0xFFF)<<0)
+
+//DSTWINROW
+#define CAMERA_DSTWINROWSTART(n)    (((n)&0xFFF)<<16)
+#define CAMERA_DSTWINROWEND(n)      (((n)&0xFFF)<<0)
+
+// SCALE CONFIG, no use now
+#define CAM_SCALE_EN            (1<<0)
+#define CAM_SCALE_COL(n)      (((n)&0x3)<<8)
+#define CAM_SCALE_ROW(n)     (((n)&0x3)<<16)
+
+/*************************************************************/
+/***************** SPI CAMERA CONFIGURATION ********************/
+/*************************************************************/
+
+// Here, spi master mode means the sensor works as the SPI master.
+// master mode 1 means 1 data ouput with SSN, master mode 2 means the other master modes.
+
+//--------------------------------
+// camera_spi_reg_0
+//--------------------------------
+// the number of lines per frame
+#define CAM_SPI_REG_LINE_PER_FRM(n)     (((n)&0x3ff)<<22)
+// the number of words(32 bits) per line
+#define CAM_SPI_REG_BLK_PER_LINE(n)     (((n)&0x3ff)<<12)
+// VSYNC high effective
+#define CAM_SPI_REG_VSYNC_INV_EN        (1<<11)
+// HREF low effective
+#define CAM_SPI_REG_HREF_INV_EN           (1<<10)
+// OVFL low effective
+#define CAM_SPI_REG_OVFL_INV_EN           (1<<9)
+// little endian enable
+#define CAM_SPI_REG_LITTLE_END_EN        (1<<8)
+// module reset when ovfl enable
+#define CAM_SPI_REG_OVFL_RST_EN           (1<<7)
+// observe the overflow when vsync effective
+#define CAM_SPI_REG_OVFL_OBS                 (1<<6)
+// reset the module when overflow in vsync effective
+#define CAM_SPI_REG_OVFL_RST                  (1<<5)
+/************************************************
+YUV data output format
+        3'b000: Y0-U0-Y1-V0                3'b001: Y0-V0-Y1-U0
+        3'b010: U0-Y0-V0-Y1                3'b011: U0-Y1-V0-Y0
+        3'b100: V0-Y1-U0-Y0                3'b101: V0-Y0-U0-Y1
+        3'b110: Y1-V0-Y0-U0                3'b111: Y1-U0-Y0-V0
+*************************************************/
+#define CAM_SPI_REG_YUV_OUT_FMT(n)      (((n)&0x7)<<2)
+// SPI master mode 1 enable
+#define CAM_SPI_REG_MASTER_EN               (1<<1)
+// SPI slave mode enable
+#define CAM_SPI_REG_SLAVE_EN                  (1<<0)
+
+//--------------------------------
+// camera_spi_reg_1
+//--------------------------------
+#define CAM_SPI_REG_CLK_DIV(n)                ((n)&0xffff)      // camera clock divider
+#define CAM_SPI_REG_SSN_HIGH_EN             (1<<17) // SSN high enable, only for master mode 1
+
+//--------------------------------
+// camera_spi_reg_2
+//--------------------------------
+// only take effect in slave mode which is not supported yet
+
+//--------------------------------
+// camera_spi_reg_3
+//--------------------------------
+// only take effect in slave mode which is not supported yet
+
+//--------------------------------
+// camera_spi_reg_4
+//--------------------------------
+#define CAM_SPI_REG_BLK_PER_PACK(n)              (((n)&0x3ff)<<6)
+#define CAM_SPI_REG_IMG_WIDTH_FROM_REG      (1<<5)
+#define CAM_SPI_REG_IMG_HEIGHT_FROM_REG     (1<<4)
+#define CAM_SPI_REG_PACK_SIZE_FROM_REG       (1<<3)
+#define CAM_SPI_REG_LINE(n)                             (((n)&0x3)<<1)
+#define CAM_SPI_REG_MASTER2_EN                      (1<<0)
+
+//--------------------------------
+// camera_spi_reg_5
+//--------------------------------
+#define CAM_SPI_REG_SYNC_CODE(n)                ((n)&0xffffff)
+
+//--------------------------------
+// camera_spi_reg_6
+//--------------------------------
+// frame_start packet id, only in master mode 2
+#define CAM_SPI_REG_FRM_START_PKT_ID(n)            (((n)&0xff)<<24)
+// frame_end packet id, only in master mode 2
+#define CAM_SPI_REG_FRM_ENDN_PKT_ID(n)             (((n)&0xff)<<16)
+// line_start packet id, only in master mode 2
+#define CAM_SPI_REG_LINE_START_PKT_ID(n)           (((n)&0xff)<<8)
+// data packet id, only in master mode 2
+#define CAM_SPI_REG_DATA_PKT_ID(n)               ((n)&0xff)
+
+//--------------------------------
+// camera_spi_observe_reg_0 (read only)
+//--------------------------------
+
+//--------------------------------
+// camera_spi_observe_reg_1 (read only)
+//--------------------------------
+
+//--------------------------------
+// csi_config_reg0
+//--------------------------------
+#define CSI_NUM_D_TERM_EN(n)          (((n)&0XFF)<<0)
+#define CSI_CUR_FRAME_LINE_NUM(n)          (((n)&0X3FF)<<8)
+#define CSI_VC_ID_SET(n)          (((n)&3)<<18)
+#define CSI_DATA_LP_IN_CHOOSE(n)          (((n)&3)<<20)
+#define CSI_DATA_LP_INV           (1<<22)
+#define CSI_CLK_LP_INV           (1<<23)
+#define CSI_TRAIL_DATA_WRONG_CHOOSE    (1<<24)
+#define CSI_SYNC_BYPASS       (1<<25)
+#define CSI_RDATA_BIT_INV_EN               (1<<26)
+#define CSI_HS_SYNC_FIND_EN        (1<<27)
+#define CSI_LINE_PACKET_ENABLE       (1<<28)
+#define CSI_ECC_BYPASS                 (1<<29)
+#define CSI_DATA_LANE_CHOOSE            (1<<30)
+#define CSI_MODULE_ENABLE          (1<<31)
+
+//--------------------------------
+// csi_config_reg01
+//--------------------------------
+#define CSI_NUM_HS_SETTLE(n)          (((n)&0XFF)<<0)
+#define CSI_LP_DATA_LENGTH_CHOSSE(n)          (((n)&7)<<8)
+#define CSI_DATA_CLK_LP_POSEEDGE_CHOSSE(n)          (((n)&7)<<11)
+#define CSI_CLK_LP_CK_INV        (1<<14)
+#define CSI_RCLR_MASK_EN        (1<<15)
+#define CSI_RINC_MASK_EN        (1<<16)
+#define CSI_HS_ENALBE_MASK_EN        (1<<17)
+#define CSI_DEN_INV_BIT        (1<<18)
+#define CSI_HSYNC_INV_BIT        (1<<19)
+#define CSI_VSYNC_INV_BIT        (1<<20)
+#define CSI_HS_DATA2_ENABLE_REG  (1<<21)
+
+#define CSI_HS_TATA1_ENALBE_REG   (1<<22)
+#define CSI_HS_DATA1_ENABLE_CHOSSE           (1<<23)
+#define CSI_HS_DATA1_ENALBE_DRE    (1<<24)
+#define CSI_DATA2_TER_ENABLE_REG         (1<<25)
+#define CSI_DATAL_TER_ENABLE_REG           (1<<26)
+#define CSI_DATAL_TER_ENABLE_DR    (1<<27)
+#define CSI_LP_DATA_INTERRUPT_CLR  (1<<28)
+#define CSI_LP_CMD_INTERRUPT_CLR       (1<<29)
+#define CSI_LP_DATA_CLR            (1<<30)
+#define CSI_LP_CMD_CLR          (1<<31)
+
+//--------------------------------
+// csi_config_reg02
+//--------------------------------
+#define CSI_NUM_C_TERM_EN(n)          (((n)&0XFFFF)<<16)
+#define CSI_NUM_HS_SETTLE_CLK(n)          (((n)&0XFFFF)<<0)
+
+//--------------------------------
+// csi_config_reg03
+//--------------------------------
+#define CSI_DLY_SEL_REG(n)          (((n)&3)<<0)
+#define CSI_DLY_SEL_DATA2_REG(n)          (((n)&3)<<2)
+#define CSI_DLY_SEL_DATA1_REG(n)          (((n)&3)<<4)
+#define CSI_CLK_LP_IN_CHOOSE_BIT(n)          (((n)&3)<<6)
+#define CSI_PU_LPRX_REG        (1<<8)
+#define CSI_PU_HSRX_REG        (1<<9)
+#define CSI_PU_DR        (1<<10)
+#define CSI_AVDD1V8_2V8_SEL_REG        (1<<11)
+#define CSI_HS_CLK_ENABLE_REG        (1<<12)
+#define CSI_HS_CLK_ENABLE_CHOOSE_BIT        (1<<13)
+#define CSI_HS_CLK_ENALBE_DR        (1<<14)
+#define CSI_CLK_TERMINAL_ENABLE_REG        (1<<15)
+#define CSI_CLK_TERMINAL_ENABLE_DR        (1<<16)
+#define CSI_OBSERVE_REG_5_LOW8_CHOOSE	(1 << 17)
+#define CSI_ECC_ERROR_FLAG_REG	(1 << 18)
+#define CSI_ECC_ERROR_DR (1 << 19)
+#define CSI_CHANNEL_SEL (1 << 20)
+#define CSI_TWO_LANE_BYTE_REVERSE (1 << 21)
+#define CSI_DATA2_LANE_BIT_REVERSE (1 << 22)
+#define CSI_DATA1_LANE_BIT_REVERSE (1 << 23)
+#define CSI_DATA2_HAS_NO_MASK (1 << 24)
+#define CSI_DATA1_HAS_NO_MASK (1 << 25)
+#define CSI_PU_LRX_D2_REG (1 << 26)
+#define CSI_PU_LRX_D1_REG (1 << 27)
+#define CSI_PU_LRX_CLK_REG (1 << 28)
+#define CSI_CLK_EDGE_SEL (1 << 29)
+#define CSI_CLK_X2_SEL (1 << 30)
+#define CSI_SINGLE_DATALANE_EN (1 << 31)
+
+//--------------------------------
+// csi_config_reg04,modified in 8850e by xiankuiwei
+//--------------------------------
+#define CSI_NUM_HS_CLK_USEFUL(n)          (((n)&0X7FFFFFFF)<<0)
+#define CSI_NUM_HS_CLK_USEFUL_EN         (1<<31)
+
+//--------------------------------
+// csi_config_reg05
+//--------------------------------
+#define CSI_LP_CMD_OUT(n)          (((n)&0XFF)<<0)
+#define CSI_PHY_CLK_STATE(n)          (((n)&0X1FF)<<10)
+#define CSI_HS_DATA_ERROR_FLAG        (1<<28)
+#define CSI_ERR_ECC_CORRECTED_FLAG        (1<<29)
+#define CSI_ERR_DATA_CORRECTED_FLAG        (1<<30)
+#define CSI_ERR_DATA_ZERO_FLAG        (1<<31)
+
+//--------------------------------
+// csi_observe_reg6 (read only)
+//--------------------------------
+
+//--------------------------------
+// csi_observe_reg6 (read only)
+//--------------------------------
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/reg_cfg_regs.h b/arch/arm/include/asm/arch-rda/reg_cfg_regs.h
new file mode 100644
index 0000000000..613c9cd659
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_cfg_regs.h
@@ -0,0 +1,16 @@
+#ifdef CONFIG_MACH_RDA8810
+#include "reg_cfg_regs_rda8810.h"
+#elif defined(CONFIG_MACH_RDA8810E)
+#include "reg_cfg_regs_rda8810e.h"
+#elif defined(CONFIG_MACH_RDA8820)
+#include "reg_cfg_regs_rda8820.h"
+#elif defined(CONFIG_MACH_RDA8850)
+#include "reg_cfg_regs_rda8850.h"
+#elif defined(CONFIG_MACH_RDA8850E)
+#include "reg_cfg_regs_rda8850e.h"
+#elif defined(CONFIG_MACH_RDA8810H)
+#include "reg_cfg_regs_rda8810h.h"
+#else
+#error "unknown MACH"
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8810.h b/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8810.h
new file mode 100644
index 0000000000..50f80fcf38
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8810.h
@@ -0,0 +1,1056 @@
+#ifndef _REG_IFC_H_
+#define _REG_IFC_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+#define PROD_ID                                  (0X8810)
+
+// ============================================================================
+// BB_GPIO_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// BB GPIO Map
+    BB_PIN_NONE_0                               = 0x00000000,
+    BB_PIN_1                                    = 0x00000001,
+    BB_PIN_2                                    = 0x00000002,
+    BB_PIN_3                                    = 0x00000003,
+    BB_PIN_4                                    = 0x00000004,
+    BB_PIN_5                                    = 0x00000005,
+    BB_PIN_UART1_RXD                            = 0x00000006,
+    BB_PIN_UART2_RXD                            = 0x00000007,
+    BB_PIN_UART2_TXD                            = 0x00000008,
+    BB_PIN_SSD1_CLK                             = 0x00000009,
+    BB_PIN_SSD1_CMD                             = 0x0000000A,
+    BB_PIN_SDAT1_0                              = 0x0000000B,
+    BB_PIN_SDAT1_1                              = 0x0000000C,
+    BB_PIN_SDAT1_2                              = 0x0000000D,
+    BB_PIN_SDAT1_3                              = 0x0000000E,
+    BB_PIN_SSD2_CLK                             = 0x0000000F,
+    BB_PIN_SSD2_CMD                             = 0x00000010,
+    BB_PIN_SDAT2_0                              = 0x00000011,
+    BB_PIN_SDAT2_1                              = 0x00000012,
+    BB_PIN_SDAT2_2                              = 0x00000013,
+    BB_PIN_SDAT2_3                              = 0x00000014,
+    BB_PIN_SPI1_CLK                             = 0x00000015,
+    BB_PIN_SPI1_CS_0                            = 0x00000016,
+    BB_PIN_SPI1_DIO                             = 0x00000017,
+    BB_PIN_SPI1_DI                              = 0x00000018,
+    BB_PIN_SIM2_RST                             = 0x00000019,
+    BB_PIN_SIM2_CLK                             = 0x0000001A,
+    BB_PIN_SIM2_DIO                             = 0x0000001B,
+    BB_PIN_SIM3_RST                             = 0x0000001C,
+    BB_PIN_SIM3_CLK                             = 0x0000001D,
+    BB_PIN_SIM3_DIO                             = 0x0000001E
+} BB_GPIO_MAPPING_T;
+
+#define BB_GPIO_NB                               (31)
+
+// ============================================================================
+// AP_GPIO_A_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP GPIO A Map
+    AP_PIN_I2C2_SCL                             = 0x00000000,
+    AP_PIN_I2C2_SDA                             = 0x00000001,
+    AP_PIN_SPI2_CLK                             = 0x00000002,
+    AP_PIN_SPI2_DIO                             = 0x00000003,
+    AP_PIN_SPI2_DI                              = 0x00000004,
+    AP_PIN_SPI2_CS_0                            = 0x00000005,
+    AP_PIN_SPI2_CS_1                            = 0x00000006,
+    AP_PIN_KEYIN_4                              = 0x00000007,
+    AP_PIN_CLK_OUT                              = 0x00000008,
+    AP_PIN_I2S_BCK                              = 0x00000009,
+    AP_PIN_I2S_LRCK                             = 0x0000000A,
+    AP_PIN_I2S_DI_0                             = 0x0000000B,
+    AP_PIN_I2S_DI_1                             = 0x0000000C,
+    AP_PIN_I2S_DO                               = 0x0000000D,
+    AP_PIN_UART1_TXD                            = 0x0000000E,
+    AP_PIN_UART1_CTS                            = 0x0000000F,
+    AP_PIN_UART1_RTS                            = 0x00000010,
+    AP_PIN_SPI1_CS_1                            = 0x00000011,
+    AP_PIN_LCD_DATA_6                           = 0x00000012,
+    AP_PIN_LCD_DATA_7                           = 0x00000013,
+    AP_PIN_LCD_WR                               = 0x00000014,
+    AP_PIN_LCD_RS                               = 0x00000015,
+    AP_PIN_LCD_RD                               = 0x00000016,
+    AP_PIN_LCD_FMARK                            = 0x00000017,
+    AP_PIN_LCD_DATA_8                           = 0x00000018,
+    AP_PIN_LCD_DATA_9                           = 0x00000019,
+    AP_PIN_LCD_DATA_10                          = 0x0000001A,
+    AP_PIN_LCD_DATA_11                          = 0x0000001B,
+    AP_PIN_LCD_DATA_12                          = 0x0000001C,
+    AP_PIN_LCD_DATA_13                          = 0x0000001D,
+    AP_PIN_LCD_DATA_14                          = 0x0000001E,
+    AP_PIN_LCD_DATA_15                          = 0x0000001F
+} AP_GPIO_A_MAPPING_T;
+
+#define AP_GPIO_A_NB                             (32)
+
+// ============================================================================
+// AP_GPIO_B_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP GPIO B Map
+    AP_PIN_KEYIN_0                              = 0x00000000,
+    AP_PIN_KEYIN_1                              = 0x00000001,
+    AP_PIN_KEYIN_2                              = 0x00000002,
+    AP_PIN_KEYOUT_0                             = 0x00000003,
+    AP_PIN_KEYOUT_1                             = 0x00000004,
+    AP_PIN_KEYOUT_2                             = 0x00000005,
+    AP_PIN_I2C3_SCL                             = 0x00000006,
+    AP_PIN_I2C3_SDA                             = 0x00000007,
+    AP_PIN_UART2_CTS                            = 0x00000008,
+    AP_PIN_UART2_RTS                            = 0x00000009,
+    AP_PIN_CAM_RST                              = 0x0000000A,
+    AP_PIN_CAM_PDN                              = 0x0000000B,
+    AP_PIN_CAM_CLK                              = 0x0000000C,
+    AP_PIN_CAM_VSYNC                            = 0x0000000D,
+    AP_PIN_CAM_HREF                             = 0x0000000E,
+    AP_PIN_CAM_PCLK                             = 0x0000000F,
+    AP_PIN_CAM_DATA_0                           = 0x00000010,
+    AP_PIN_CAM_DATA_1                           = 0x00000011,
+    AP_PIN_CAM_DATA_2                           = 0x00000012,
+    AP_PIN_CAM_DATA_3                           = 0x00000013,
+    AP_PIN_CAM_DATA_4                           = 0x00000014,
+    AP_PIN_CAM_DATA_5                           = 0x00000015,
+    AP_PIN_CAM_DATA_6                           = 0x00000016,
+    AP_PIN_CAM_DATA_7                           = 0x00000017,
+    AP_PIN_M_SPI_CS_0                           = 0x00000018,
+    AP_PIN_NFCLE                                = 0x00000019,
+    AP_PIN_NFWEN                                = 0x0000001A,
+    AP_PIN_NFWPN                                = 0x0000001B,
+    AP_PIN_NFREN                                = 0x0000001C,
+    AP_PIN_NFRB                                 = 0x0000001D,
+    AP_PIN_I2C1_SCL                             = 0x0000001E,
+    AP_PIN_I2C1_SDA                             = 0x0000001F
+} AP_GPIO_B_MAPPING_T;
+
+#define AP_GPIO_B_NB                             (32)
+
+// ============================================================================
+// AP_GPIO_D_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP GPIO D Map
+    AP_PIN_UART3_RXD                            = 0x00000000,
+    AP_PIN_UART3_TXD                            = 0x00000001,
+    AP_PIN_UART3_CTS                            = 0x00000002,
+    AP_PIN_UART3_RTS                            = 0x00000003,
+    AP_PIN_NFDQS                                = 0x00000004
+} AP_GPIO_D_MAPPING_T;
+
+#define AP_GPIO_D_NB                             (5)
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+// ============================================================================
+// CFG_REGS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+#define REG_CONFIG_REGS_BASE        0x01A09000
+
+typedef volatile struct
+{
+    REG32                          CHIP_ID;                      //0x00000000
+    /// This register contain the synthesis date and version
+    REG32                          Build_Version;                //0x00000004
+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+    /// bit n to '0' selects Alt.
+    REG32                          BB_GPIO_Mode;                 //0x00000008
+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+    /// bit n to '0' selects Alt.
+    REG32                          AP_GPIO_A_Mode;               //0x0000000C
+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+    /// bit n to '0' selects Alt.
+    REG32                          AP_GPIO_B_Mode;               //0x00000010
+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+    /// bit n to '0' selects Alt.
+    REG32                          AP_GPIO_D_Mode;               //0x00000014
+    REG32                          Alt_mux_select;               //0x00000018
+    REG32                          IO_Drive1_Select;             //0x0000001C
+    REG32                          IO_Drive2_Select;             //0x00000020
+    REG32                          RAM_DRIVE;                    //0x00000024
+    REG32                          H2X_AP_Offset;                //0x00000028
+    REG32                          H2X_DDR_Offset;               //0x0000002C
+    REG32                          audio_pd_set;                 //0x00000030
+    REG32                          audio_pd_clr;                 //0x00000034
+    REG32                          audio_sel_cfg;                //0x00000038
+    REG32                          audio_mic_cfg;                //0x0000003C
+    REG32                          audio_spk_cfg;                //0x00000040
+    REG32                          audio_rcv_gain;               //0x00000044
+    REG32                          audio_head_gain;              //0x00000048
+    REG32                          TSC_DATA;                     //0x0000004C
+    REG32                          GPADC_DATA_CH[8];             //0x00000050
+} HWP_CFG_REGS_T;
+
+#define hwp_configRegs              ((HWP_CFG_REGS_T*)(RDA_CFG_REGS_BASE))
+
+
+//CHIP_ID
+#define CFG_REGS_METAL_ID(n)        (((n)&0xFFF)<<0)
+#define CFG_REGS_METAL_ID_MASK      (0xFFF<<0)
+#define CFG_REGS_METAL_ID_SHIFT     (0)
+#define CFG_REGS_BOND_ID(n)         (((n)&7)<<12)
+#define CFG_REGS_BOND_ID_MASK       (7<<12)
+#define CFG_REGS_BOND_ID_SHIFT      (12)
+#define CFG_REGS_PROD_ID(n)         (((n)&0xFFFF)<<16)
+#define CFG_REGS_PROD_ID_MASK       (0xFFFF<<16)
+#define CFG_REGS_PROD_ID_SHIFT      (16)
+
+//Build_Version
+#define CFG_REGS_MAJOR(n)           (((n)&15)<<28)
+#define CFG_REGS_YEAR(n)            (((n)&15)<<24)
+#define CFG_REGS_MONTH(n)           (((n)&0xFF)<<16)
+#define CFG_REGS_DAY(n)             (((n)&0xFF)<<8)
+#define CFG_REGS_BUILD_STYLE_FPGA   (0<<4)
+#define CFG_REGS_BUILD_STYLE_CHIP   (1<<4)
+#define CFG_REGS_BUILD_STYLE_FPGA_USB (2<<4)
+#define CFG_REGS_BUILD_STYLE_FPGA_GSM (3<<4)
+#define CFG_REGS_BUILD_REVISION(n)  (((n)&15)<<0)
+
+//BB_GPIO_Mode
+#define CFG_REGS_MODE_BB_PIN_NONE_0 (1<<0)
+#define CFG_REGS_MODE_BB_PIN_NONE_0_MASK (1<<0)
+#define CFG_REGS_MODE_BB_PIN_NONE_0_SHIFT (0)
+#define CFG_REGS_MODE_BB_PIN_NONE_0_ALT (0<<0)
+#define CFG_REGS_MODE_BB_PIN_NONE_0_GPIO (1<<0)
+#define CFG_REGS_MODE_BB_PIN_1      (1<<1)
+#define CFG_REGS_MODE_BB_PIN_1_MASK (1<<1)
+#define CFG_REGS_MODE_BB_PIN_1_SHIFT (1)
+#define CFG_REGS_MODE_BB_PIN_1_ALT  (0<<1)
+#define CFG_REGS_MODE_BB_PIN_1_GPIO (1<<1)
+#define CFG_REGS_MODE_BB_PIN_2      (1<<2)
+#define CFG_REGS_MODE_BB_PIN_2_MASK (1<<2)
+#define CFG_REGS_MODE_BB_PIN_2_SHIFT (2)
+#define CFG_REGS_MODE_BB_PIN_2_ALT  (0<<2)
+#define CFG_REGS_MODE_BB_PIN_2_GPIO (1<<2)
+#define CFG_REGS_MODE_BB_PIN_3      (1<<3)
+#define CFG_REGS_MODE_BB_PIN_3_MASK (1<<3)
+#define CFG_REGS_MODE_BB_PIN_3_SHIFT (3)
+#define CFG_REGS_MODE_BB_PIN_3_ALT  (0<<3)
+#define CFG_REGS_MODE_BB_PIN_3_GPIO (1<<3)
+#define CFG_REGS_MODE_BB_PIN_4      (1<<4)
+#define CFG_REGS_MODE_BB_PIN_4_MASK (1<<4)
+#define CFG_REGS_MODE_BB_PIN_4_SHIFT (4)
+#define CFG_REGS_MODE_BB_PIN_4_ALT  (0<<4)
+#define CFG_REGS_MODE_BB_PIN_4_GPIO (1<<4)
+#define CFG_REGS_MODE_BB_PIN_5      (1<<5)
+#define CFG_REGS_MODE_BB_PIN_5_MASK (1<<5)
+#define CFG_REGS_MODE_BB_PIN_5_SHIFT (5)
+#define CFG_REGS_MODE_BB_PIN_5_ALT  (0<<5)
+#define CFG_REGS_MODE_BB_PIN_5_GPIO (1<<5)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD (1<<6)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_MASK (1<<6)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_SHIFT (6)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_ALT (0<<6)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_GPIO (1<<6)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD (1<<7)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_MASK (1<<7)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_SHIFT (7)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_ALT (0<<7)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_GPIO (1<<7)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD (1<<8)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_MASK (1<<8)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_SHIFT (8)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_ALT (0<<8)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_GPIO (1<<8)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK (1<<9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_MASK (1<<9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_SHIFT (9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_ALT (0<<9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_GPIO (1<<9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD (1<<10)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_MASK (1<<10)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_SHIFT (10)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_ALT (0<<10)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_GPIO (1<<10)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0 (1<<11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_MASK (1<<11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_SHIFT (11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_ALT (0<<11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_GPIO (1<<11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1 (1<<12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_MASK (1<<12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_SHIFT (12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_ALT (0<<12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_GPIO (1<<12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2 (1<<13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_MASK (1<<13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_SHIFT (13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_ALT (0<<13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_GPIO (1<<13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3 (1<<14)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_MASK (1<<14)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_SHIFT (14)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_ALT (0<<14)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_GPIO (1<<14)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK (1<<15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_MASK (1<<15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_SHIFT (15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_ALT (0<<15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_GPIO (1<<15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD (1<<16)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_MASK (1<<16)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_SHIFT (16)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_ALT (0<<16)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_GPIO (1<<16)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0 (1<<17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_MASK (1<<17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_SHIFT (17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_ALT (0<<17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_GPIO (1<<17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1 (1<<18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_MASK (1<<18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_SHIFT (18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_ALT (0<<18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_GPIO (1<<18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2 (1<<19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_MASK (1<<19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_SHIFT (19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_ALT (0<<19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_GPIO (1<<19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3 (1<<20)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_MASK (1<<20)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_SHIFT (20)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_ALT (0<<20)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_GPIO (1<<20)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK (1<<21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_MASK (1<<21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_SHIFT (21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_ALT (0<<21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_GPIO (1<<21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0 (1<<22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_MASK (1<<22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_SHIFT (22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_ALT (0<<22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_GPIO (1<<22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO (1<<23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_MASK (1<<23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_SHIFT (23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_ALT (0<<23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_GPIO (1<<23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI (1<<24)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_MASK (1<<24)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_SHIFT (24)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_ALT (0<<24)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_GPIO (1<<24)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST (1<<25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_MASK (1<<25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_SHIFT (25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_ALT (0<<25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_GPIO (1<<25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK (1<<26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_MASK (1<<26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_SHIFT (26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_ALT (0<<26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_GPIO (1<<26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO (1<<27)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_MASK (1<<27)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_SHIFT (27)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_ALT (0<<27)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_GPIO (1<<27)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST (1<<28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_MASK (1<<28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_SHIFT (28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_ALT (0<<28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_GPIO (1<<28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK (1<<29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_MASK (1<<29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_SHIFT (29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_ALT (0<<29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_GPIO (1<<29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO (1<<30)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_MASK (1<<30)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_SHIFT (30)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_ALT (0<<30)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_GPIO (1<<30)
+#define CFG_REGS_BB_GPIO_MODE(n)    (((n)&0x7FFFFFFF)<<0)
+#define CFG_REGS_BB_GPIO_MODE_MASK  (0x7FFFFFFF<<0)
+#define CFG_REGS_BB_GPIO_MODE_SHIFT (0)
+
+//AP_GPIO_A_Mode
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_MASK (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_SHIFT (0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_ALT (0<<0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_GPIO (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA (1<<1)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_MASK (1<<1)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_SHIFT (1)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_ALT (0<<1)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_GPIO (1<<1)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_MASK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_SHIFT (2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_ALT (0<<2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_GPIO (1<<2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_MASK (1<<3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_SHIFT (3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_ALT (0<<3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_GPIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI (1<<4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_MASK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_SHIFT (4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_ALT (0<<4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_GPIO (1<<4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0 (1<<5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_MASK (1<<5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_SHIFT (5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_ALT (0<<5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_GPIO (1<<5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1 (1<<6)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_MASK (1<<6)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_SHIFT (6)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_ALT (0<<6)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_GPIO (1<<6)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4 (1<<7)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_MASK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_SHIFT (7)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_ALT (0<<7)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_GPIO (1<<7)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT (1<<8)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_MASK (1<<8)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_SHIFT (8)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_ALT (0<<8)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_GPIO (1<<8)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_MASK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_SHIFT (9)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_ALT (0<<9)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_GPIO (1<<9)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_MASK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_SHIFT (10)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_ALT (0<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_GPIO (1<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0 (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_MASK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_SHIFT (11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_ALT (0<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_GPIO (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1 (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_MASK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_SHIFT (12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_ALT (0<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_GPIO (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO_MASK (1<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO_SHIFT (13)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO_ALT (0<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO_GPIO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD (1<<14)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_MASK (1<<14)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_SHIFT (14)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_ALT (0<<14)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_GPIO (1<<14)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS (1<<15)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_MASK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_SHIFT (15)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_ALT (0<<15)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_GPIO (1<<15)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS (1<<16)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_MASK (1<<16)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_SHIFT (16)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_ALT (0<<16)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_GPIO (1<<16)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1 (1<<17)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_MASK (1<<17)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_SHIFT (17)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_ALT (0<<17)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_GPIO (1<<17)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6 (1<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_MASK (1<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_SHIFT (18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_ALT (0<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_GPIO (1<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7 (1<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_MASK (1<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_SHIFT (19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_ALT (0<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_GPIO (1<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR (1<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR_MASK (1<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR_SHIFT (20)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR_ALT (0<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR_GPIO (1<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS (1<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS_MASK (1<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS_SHIFT (21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS_ALT (0<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS_GPIO (1<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD (1<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD_MASK (1<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD_SHIFT (22)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD_ALT (0<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD_GPIO (1<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK (1<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_MASK (1<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_SHIFT (23)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_ALT (0<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_GPIO (1<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8 (1<<24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_MASK (1<<24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_SHIFT (24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_ALT (0<<24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_GPIO (1<<24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9 (1<<25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_MASK (1<<25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_SHIFT (25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_ALT (0<<25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_GPIO (1<<25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10 (1<<26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_MASK (1<<26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_SHIFT (26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_ALT (0<<26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_GPIO (1<<26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11 (1<<27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_MASK (1<<27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_SHIFT (27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_ALT (0<<27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_GPIO (1<<27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12 (1<<28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_MASK (1<<28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_SHIFT (28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_ALT (0<<28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_GPIO (1<<28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13 (1<<29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_MASK (1<<29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_SHIFT (29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_ALT (0<<29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_GPIO (1<<29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14 (1<<30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_MASK (1<<30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_SHIFT (30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_ALT (0<<30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_GPIO (1<<30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15 (1<<31)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_MASK (1<<31)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_SHIFT (31)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_ALT (0<<31)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_GPIO (1<<31)
+#define CFG_REGS_AP_GPIO_A_MODE(n)  (((n)&0xFFFFFFFF)<<0)
+#define CFG_REGS_AP_GPIO_A_MODE_MASK (0xFFFFFFFF<<0)
+#define CFG_REGS_AP_GPIO_A_MODE_SHIFT (0)
+
+//AP_GPIO_B_Mode
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0 (1<<0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_MASK (1<<0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_SHIFT (0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_ALT (0<<0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_GPIO (1<<0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1 (1<<1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_MASK (1<<1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_SHIFT (1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_ALT (0<<1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_GPIO (1<<1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2 (1<<2)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_MASK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_SHIFT (2)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_ALT (0<<2)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_GPIO (1<<2)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0 (1<<3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_MASK (1<<3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_SHIFT (3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_ALT (0<<3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_GPIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1 (1<<4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_MASK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_SHIFT (4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_ALT (0<<4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_GPIO (1<<4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2 (1<<5)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_MASK (1<<5)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_SHIFT (5)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_ALT (0<<5)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_GPIO (1<<5)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL (1<<6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_MASK (1<<6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_SHIFT (6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_ALT (0<<6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_GPIO (1<<6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA (1<<7)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_MASK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_SHIFT (7)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_ALT (0<<7)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_GPIO (1<<7)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS (1<<8)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_MASK (1<<8)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_SHIFT (8)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_ALT (0<<8)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_GPIO (1<<8)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS (1<<9)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_MASK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_SHIFT (9)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_ALT (0<<9)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_GPIO (1<<9)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST_MASK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST_SHIFT (10)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST_ALT (0<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST_GPIO (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_MASK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_SHIFT (11)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_ALT (0<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_GPIO (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_MASK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_SHIFT (12)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_ALT (0<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_GPIO (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_MASK (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_SHIFT (13)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_ALT (0<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_GPIO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_MASK (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_SHIFT (14)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_ALT (0<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_GPIO (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_MASK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_SHIFT (15)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_ALT (0<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_GPIO (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0 (1<<16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_MASK (1<<16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_SHIFT (16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_ALT (0<<16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_GPIO (1<<16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1 (1<<17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_MASK (1<<17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_SHIFT (17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_ALT (0<<17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_GPIO (1<<17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2 (1<<18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_MASK (1<<18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_SHIFT (18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_ALT (0<<18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_GPIO (1<<18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3 (1<<19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_MASK (1<<19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_SHIFT (19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_ALT (0<<19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_GPIO (1<<19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4 (1<<20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_MASK (1<<20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_SHIFT (20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_ALT (0<<20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_GPIO (1<<20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5 (1<<21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_MASK (1<<21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_SHIFT (21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_ALT (0<<21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_GPIO (1<<21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6 (1<<22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_MASK (1<<22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_SHIFT (22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_ALT (0<<22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_GPIO (1<<22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7 (1<<23)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_MASK (1<<23)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_SHIFT (23)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_ALT (0<<23)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_GPIO (1<<23)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0 (1<<24)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_MASK (1<<24)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_SHIFT (24)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_ALT (0<<24)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_GPIO (1<<24)
+#define CFG_REGS_MODE_AP_PIN_NFCLE  (1<<25)
+#define CFG_REGS_MODE_AP_PIN_NFCLE_MASK (1<<25)
+#define CFG_REGS_MODE_AP_PIN_NFCLE_SHIFT (25)
+#define CFG_REGS_MODE_AP_PIN_NFCLE_ALT (0<<25)
+#define CFG_REGS_MODE_AP_PIN_NFCLE_GPIO (1<<25)
+#define CFG_REGS_MODE_AP_PIN_NFWEN  (1<<26)
+#define CFG_REGS_MODE_AP_PIN_NFWEN_MASK (1<<26)
+#define CFG_REGS_MODE_AP_PIN_NFWEN_SHIFT (26)
+#define CFG_REGS_MODE_AP_PIN_NFWEN_ALT (0<<26)
+#define CFG_REGS_MODE_AP_PIN_NFWEN_GPIO (1<<26)
+#define CFG_REGS_MODE_AP_PIN_NFWPN  (1<<27)
+#define CFG_REGS_MODE_AP_PIN_NFWPN_MASK (1<<27)
+#define CFG_REGS_MODE_AP_PIN_NFWPN_SHIFT (27)
+#define CFG_REGS_MODE_AP_PIN_NFWPN_ALT (0<<27)
+#define CFG_REGS_MODE_AP_PIN_NFWPN_GPIO (1<<27)
+#define CFG_REGS_MODE_AP_PIN_NFREN  (1<<28)
+#define CFG_REGS_MODE_AP_PIN_NFREN_MASK (1<<28)
+#define CFG_REGS_MODE_AP_PIN_NFREN_SHIFT (28)
+#define CFG_REGS_MODE_AP_PIN_NFREN_ALT (0<<28)
+#define CFG_REGS_MODE_AP_PIN_NFREN_GPIO (1<<28)
+#define CFG_REGS_MODE_AP_PIN_NFRB   (1<<29)
+#define CFG_REGS_MODE_AP_PIN_NFRB_MASK (1<<29)
+#define CFG_REGS_MODE_AP_PIN_NFRB_SHIFT (29)
+#define CFG_REGS_MODE_AP_PIN_NFRB_ALT (0<<29)
+#define CFG_REGS_MODE_AP_PIN_NFRB_GPIO (1<<29)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL (1<<30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_MASK (1<<30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_SHIFT (30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_ALT (0<<30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_GPIO (1<<30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA (1<<31)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_MASK (1<<31)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_SHIFT (31)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_ALT (0<<31)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_GPIO (1<<31)
+#define CFG_REGS_AP_GPIO_B_MODE(n)  (((n)&0xFFFFFFFF)<<0)
+#define CFG_REGS_AP_GPIO_B_MODE_MASK (0xFFFFFFFF<<0)
+#define CFG_REGS_AP_GPIO_B_MODE_SHIFT (0)
+
+//AP_GPIO_D_Mode
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD (1<<0)
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_MASK (1<<0)
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_SHIFT (0)
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_ALT (0<<0)
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_GPIO (1<<0)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD (1<<1)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_MASK (1<<1)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_SHIFT (1)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_ALT (0<<1)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_GPIO (1<<1)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS (1<<2)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_MASK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_SHIFT (2)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_ALT (0<<2)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_GPIO (1<<2)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS (1<<3)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_MASK (1<<3)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_SHIFT (3)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_ALT (0<<3)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_GPIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_NFDQS  (1<<4)
+#define CFG_REGS_MODE_AP_PIN_NFDQS_MASK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_NFDQS_SHIFT (4)
+#define CFG_REGS_MODE_AP_PIN_NFDQS_ALT (0<<4)
+#define CFG_REGS_MODE_AP_PIN_NFDQS_GPIO (1<<4)
+#define CFG_REGS_AP_GPIO_D_MODE(n)  (((n)&31)<<0)
+#define CFG_REGS_AP_GPIO_D_MODE_MASK (31<<0)
+#define CFG_REGS_AP_GPIO_D_MODE_SHIFT (0)
+
+//Alt_mux_select
+#define CFG_REGS_LCD_MODE_MASK      (3<<0)
+#define CFG_REGS_LCD_MODE_PARALLEL_16BIT (0<<0)
+#define CFG_REGS_LCD_MODE_DSI       (1<<0)
+#define CFG_REGS_LCD_MODE_RGB_24BIT (2<<0)
+#define CFG_REGS_LCD_MODE_RGB_16BIT (3<<0)
+#define CFG_REGS_SPI_LCD_MASK       (1<<2)
+#define CFG_REGS_SPI_LCD_NONE       (0<<2)
+#define CFG_REGS_SPI_LCD_SPI_LCD    (1<<2)
+#define CFG_REGS_CAM_I2C2_MASK      (1<<3)
+#define CFG_REGS_CAM_I2C2_CAM       (0<<3)
+#define CFG_REGS_CAM_I2C2_I2C2      (1<<3)
+#define CFG_REGS_CSI2_MASK          (3<<4)
+#define CFG_REGS_CSI2_PARALLEL_CAM  (0<<4)
+#define CFG_REGS_CSI2_CSI2          (1<<4)
+#define CFG_REGS_CSI2_SPI_CAM       (2<<4)
+#define CFG_REGS_UART2_MASK         (1<<6)
+#define CFG_REGS_UART2_HOST_UART    (0<<6)
+#define CFG_REGS_UART2_UART2        (1<<6)
+#define CFG_REGS_UART1_8LINE_MASK   (1<<7)
+#define CFG_REGS_UART1_8LINE_UART2  (0<<7)
+#define CFG_REGS_UART1_8LINE_UART1_8_LINE (1<<7)
+#define CFG_REGS_DAI_MASK           (3<<8)
+#define CFG_REGS_DAI_I2S            (0<<8)
+#define CFG_REGS_DAI_DAI            (1<<8)
+#define CFG_REGS_DAI_DAI_SIMPLE     (2<<8)
+#define CFG_REGS_KEYIN_3_MASK       (1<<10)
+#define CFG_REGS_KEYIN_3_SPI2_CS_1  (0<<10)
+#define CFG_REGS_KEYIN_3_KEYIN_3    (1<<10)
+#define CFG_REGS_LPSCO_1_MASK       (1<<11)
+#define CFG_REGS_LPSCO_1_KEYIN_4    (0<<11)
+#define CFG_REGS_LPSCO_1_LPSCO_1    (1<<11)
+#define CFG_REGS_SPI1_CS_2_MASK     (1<<12)
+#define CFG_REGS_SPI1_CS_2_KEYIN_1  (0<<12)
+#define CFG_REGS_SPI1_CS_2_SPI1_CS_2 (1<<12)
+#define CFG_REGS_I2S_DI_2_MASK      (1<<13)
+#define CFG_REGS_I2S_DI_2_KEYIN_2   (0<<13)
+#define CFG_REGS_I2S_DI_2_I2S_DI_2  (1<<13)
+#define CFG_REGS_TCO_0_MASK         (1<<14)
+#define CFG_REGS_TCO_0_KEYOUT_0     (0<<14)
+#define CFG_REGS_TCO_0_TCO_0        (1<<14)
+#define CFG_REGS_TCO_1_MASK         (1<<15)
+#define CFG_REGS_TCO_1_KEYOUT_1     (0<<15)
+#define CFG_REGS_TCO_1_TCO_1        (1<<15)
+#define CFG_REGS_TCO_2_MASK         (1<<16)
+#define CFG_REGS_TCO_2_KEYOUT_2     (0<<16)
+#define CFG_REGS_TCO_2_TCO_2        (1<<16)
+#define CFG_REGS_KEYOUT_3_4_MASK    (1<<17)
+#define CFG_REGS_KEYOUT_3_4_I2C3    (0<<17)
+#define CFG_REGS_KEYOUT_3_4_KEYOUT_3_4 (1<<17)
+#define CFG_REGS_KEYOUT_6_MASK      (1<<18)
+#define CFG_REGS_KEYOUT_6_UART2_RTS (0<<18)
+#define CFG_REGS_KEYOUT_6_KEYOUT_6  (1<<18)
+#define CFG_REGS_KEYOUT_7_MASK      (1<<19)
+#define CFG_REGS_KEYOUT_7_UART1_RTS (0<<19)
+#define CFG_REGS_KEYOUT_7_KEYOUT_7  (1<<19)
+#define CFG_REGS_GPO_0_MASK         (3<<20)
+#define CFG_REGS_GPO_0_GPO_0        (0<<20)
+#define CFG_REGS_GPO_0_PWT          (1<<20)
+#define CFG_REGS_GPO_0_KEYIN_5      (2<<20)
+#define CFG_REGS_GPO_1_MASK         (3<<22)
+#define CFG_REGS_GPO_1_GPO_1        (0<<22)
+#define CFG_REGS_GPO_1_LPG          (1<<22)
+#define CFG_REGS_GPO_1_KEYOUT_5     (2<<22)
+#define CFG_REGS_GPO_2_MASK         (3<<24)
+#define CFG_REGS_GPO_2_GPO_2        (0<<24)
+#define CFG_REGS_GPO_2_PWL_1        (1<<24)
+#define CFG_REGS_GPO_2_CLK_32K      (2<<24)
+#define CFG_REGS_GPO_3_MASK         (1<<26)
+#define CFG_REGS_GPO_3_LCD_CS_1     (0<<26)
+#define CFG_REGS_GPO_3_GPO_3        (1<<26)
+#define CFG_REGS_GPO_4_MASK         (1<<27)
+#define CFG_REGS_GPO_4_LCD_CS_0     (0<<27)
+#define CFG_REGS_GPO_4_GPO_4        (1<<27)
+#define CFG_REGS_CLK_OUT_MASK       (1<<28)
+#define CFG_REGS_CLK_OUT_HST_CLK    (0<<28)
+#define CFG_REGS_CLK_OUT_CLK_OUT    (1<<28)
+#define CFG_REGS_DEBUG_MASK         (1<<29)
+#define CFG_REGS_DEBUG_NONE         (0<<29)
+#define CFG_REGS_DEBUG_DEBUG_MONITOR (1<<29)
+#define CFG_REGS_AP_SPI1_MASK       (1<<30)
+#define CFG_REGS_AP_SPI1_BB_SPI1    (0<<30)
+#define CFG_REGS_AP_SPI1_AP_SPI1    (1<<30)
+#define CFG_REGS_LCD24_CAM_MASK     (1<<31)
+#define CFG_REGS_LCD24_CAM_NAND_IO  (0<<31)
+#define CFG_REGS_LCD24_CAM_CAM_IO   (1<<31)
+
+//IO_Drive1_Select
+#define CFG_REGS_DDR_DRIVE_MASK     (7<<0)
+#define CFG_REGS_DDR_DRIVE_FAST_AND_MOST_WEAK (7<<0)
+#define CFG_REGS_DDR_DRIVE_FAST_AND_WEAK (6<<0)
+#define CFG_REGS_DDR_DRIVE_FAST_AND_STRONG (5<<0)
+#define CFG_REGS_DDR_DRIVE_FAST_AND_MOST_STRONG (4<<0)
+#define CFG_REGS_DDR_DRIVE_SLOW_AND_MOST_WEAK (3<<0)
+#define CFG_REGS_DDR_DRIVE_SLOW_AND_WEAK (2<<0)
+#define CFG_REGS_DDR_DRIVE_SLOW_AND_STRONG (1<<0)
+#define CFG_REGS_DDR_DRIVE_SLOW_AND_MOST_STRONG (0<<0)
+#define CFG_REGS_PSRAM1_DRIVE_MASK  (7<<3)
+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_MOST_WEAK (7<<3)
+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_WEAK (6<<3)
+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_STRONG (5<<3)
+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_MOST_STRONG (4<<3)
+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_MOST_WEAK (3<<3)
+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_WEAK (2<<3)
+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_STRONG (1<<3)
+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_MOST_STRONG (0<<3)
+#define CFG_REGS_PSRAM2_DRIVE_MASK  (7<<6)
+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_MOST_WEAK (7<<6)
+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_WEAK (6<<6)
+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_STRONG (5<<6)
+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_MOST_STRONG (4<<6)
+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_MOST_WEAK (3<<6)
+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_WEAK (2<<6)
+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_STRONG (1<<6)
+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_MOST_STRONG (0<<6)
+#define CFG_REGS_NFLSH_DRIVE_MASK   (7<<9)
+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_MOST_WEAK (7<<9)
+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_WEAK (6<<9)
+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_STRONG (5<<9)
+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_MOST_STRONG (4<<9)
+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_MOST_WEAK (3<<9)
+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_WEAK (2<<9)
+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_STRONG (1<<9)
+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_MOST_STRONG (0<<9)
+#define CFG_REGS_LCD1_DRIVE_MASK    (7<<12)
+#define CFG_REGS_LCD1_DRIVE_FAST_AND_MOST_WEAK (7<<12)
+#define CFG_REGS_LCD1_DRIVE_FAST_AND_WEAK (6<<12)
+#define CFG_REGS_LCD1_DRIVE_FAST_AND_STRONG (5<<12)
+#define CFG_REGS_LCD1_DRIVE_FAST_AND_MOST_STRONG (4<<12)
+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_MOST_WEAK (3<<12)
+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_WEAK (2<<12)
+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_STRONG (1<<12)
+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_MOST_STRONG (0<<12)
+#define CFG_REGS_LCD2_DRIVE_MASK    (7<<15)
+#define CFG_REGS_LCD2_DRIVE_FAST_AND_MOST_WEAK (7<<15)
+#define CFG_REGS_LCD2_DRIVE_FAST_AND_WEAK (6<<15)
+#define CFG_REGS_LCD2_DRIVE_FAST_AND_STRONG (5<<15)
+#define CFG_REGS_LCD2_DRIVE_FAST_AND_MOST_STRONG (4<<15)
+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_MOST_WEAK (3<<15)
+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_WEAK (2<<15)
+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_STRONG (1<<15)
+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_MOST_STRONG (0<<15)
+#define CFG_REGS_SDAT1_DRIVE_MASK   (7<<18)
+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_MOST_WEAK (7<<18)
+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_WEAK (6<<18)
+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_STRONG (5<<18)
+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_MOST_STRONG (4<<18)
+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_MOST_WEAK (3<<18)
+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_WEAK (2<<18)
+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_STRONG (1<<18)
+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_MOST_STRONG (0<<18)
+#define CFG_REGS_SDAT2_DRIVE_MASK   (7<<21)
+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_MOST_WEAK (7<<21)
+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_WEAK (6<<21)
+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_STRONG (5<<21)
+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_MOST_STRONG (4<<21)
+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_MOST_WEAK (3<<21)
+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_WEAK (2<<21)
+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_STRONG (1<<21)
+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_MOST_STRONG (0<<21)
+#define CFG_REGS_CAM_DRIVE_MASK     (3<<24)
+#define CFG_REGS_CAM_DRIVE_MOST_STRONG (0<<24)
+#define CFG_REGS_CAM_DRIVE_STRONG   (1<<24)
+#define CFG_REGS_CAM_DRIVE_WEAK     (2<<24)
+#define CFG_REGS_CAM_DRIVE_MOST_WEAK (3<<24)
+#define CFG_REGS_SIM1_DRIVE_MASK    (3<<26)
+#define CFG_REGS_SIM1_DRIVE_MOST_STRONG (0<<26)
+#define CFG_REGS_SIM1_DRIVE_STRONG  (1<<26)
+#define CFG_REGS_SIM1_DRIVE_WEAK    (2<<26)
+#define CFG_REGS_SIM1_DRIVE_MOST_WEAK (3<<26)
+#define CFG_REGS_SIM2_DRIVE_MASK    (3<<28)
+#define CFG_REGS_SIM2_DRIVE_MOST_STRONG (0<<28)
+#define CFG_REGS_SIM2_DRIVE_STRONG  (1<<28)
+#define CFG_REGS_SIM2_DRIVE_WEAK    (2<<28)
+#define CFG_REGS_SIM2_DRIVE_MOST_WEAK (3<<28)
+#define CFG_REGS_SIM3_DRIVE_MASK    (3<<30)
+#define CFG_REGS_SIM3_DRIVE_MOST_STRONG (0<<30)
+#define CFG_REGS_SIM3_DRIVE_STRONG  (1<<30)
+#define CFG_REGS_SIM3_DRIVE_WEAK    (2<<30)
+#define CFG_REGS_SIM3_DRIVE_MOST_WEAK (3<<30)
+
+//IO_Drive2_Select
+#define CFG_REGS_GPIO_DRIVE_MASK    (3<<0)
+#define CFG_REGS_GPIO_DRIVE_MOST_STRONG (0<<0)
+#define CFG_REGS_GPIO_DRIVE_STRONG  (1<<0)
+#define CFG_REGS_GPIO_DRIVE_WEAK    (2<<0)
+#define CFG_REGS_GPIO_DRIVE_MOST_WEAK (3<<0)
+
+//RAM_DRIVE
+#define CFG_REGS_MBRAM_A(n)         (((n)&7)<<0)
+#define CFG_REGS_MBRAM_A_MASK       (7<<0)
+#define CFG_REGS_MBRAM_A_SHIFT      (0)
+#define CFG_REGS_MBRAM_W(n)         (((n)&3)<<3)
+#define CFG_REGS_MBRAM_W_MASK       (3<<3)
+#define CFG_REGS_MBRAM_W_SHIFT      (3)
+#define CFG_REGS_MBRAM_R            (1<<5)
+#define CFG_REGS_BBRAM_A(n)         (((n)&7)<<6)
+#define CFG_REGS_BBRAM_A_MASK       (7<<6)
+#define CFG_REGS_BBRAM_A_SHIFT      (6)
+#define CFG_REGS_BBRAM_W(n)         (((n)&3)<<9)
+#define CFG_REGS_BBRAM_W_MASK       (3<<9)
+#define CFG_REGS_BBRAM_W_SHIFT      (9)
+#define CFG_REGS_BBRAM_R            (1<<11)
+#define CFG_REGS_XP_A(n)            (((n)&7)<<12)
+#define CFG_REGS_XP_A_MASK          (7<<12)
+#define CFG_REGS_XP_A_SHIFT         (12)
+#define CFG_REGS_XP_W(n)            (((n)&3)<<15)
+#define CFG_REGS_XP_W_MASK          (3<<15)
+#define CFG_REGS_XP_W_SHIFT         (15)
+#define CFG_REGS_XP_R               (1<<17)
+#define CFG_REGS_BP_A(n)            (((n)&7)<<18)
+#define CFG_REGS_BP_A_MASK          (7<<18)
+#define CFG_REGS_BP_A_SHIFT         (18)
+#define CFG_REGS_BP_W(n)            (((n)&3)<<21)
+#define CFG_REGS_BP_W_MASK          (3<<21)
+#define CFG_REGS_BP_W_SHIFT         (21)
+#define CFG_REGS_BP_R               (1<<23)
+#define CFG_REGS_EV_A(n)            (((n)&7)<<24)
+#define CFG_REGS_EV_A_MASK          (7<<24)
+#define CFG_REGS_EV_A_SHIFT         (24)
+#define CFG_REGS_EV_W(n)            (((n)&3)<<27)
+#define CFG_REGS_EV_W_MASK          (3<<27)
+#define CFG_REGS_EV_W_SHIFT         (27)
+#define CFG_REGS_EV_R               (1<<29)
+
+//H2X_AP_Offset
+#define CFG_REGS_H2X_AP_OFFSET(n)   (((n)&0xFF)<<0)
+#define CFG_REGS_H2X_AP_OFFSET_MASK (0xFF<<0)
+#define CFG_REGS_H2X_AP_OFFSET_SHIFT (0)
+
+//H2X_DDR_Offset
+#define CFG_REGS_H2X_DDR_OFFSET(n)  (((n)&0xFF)<<0)
+#define CFG_REGS_H2X_DDR_OFFSET_MASK (0xFF<<0)
+#define CFG_REGS_H2X_DDR_OFFSET_SHIFT (0)
+
+//audio_pd_set
+#define CFG_REGS_AU_DEEP_PD_N       (1<<0)
+#define CFG_REGS_AU_REF_PD_N        (1<<1)
+#define CFG_REGS_AU_MIC_PD_N        (1<<2)
+#define CFG_REGS_AU_AUXMIC_PD_N     (1<<3)
+#define CFG_REGS_AU_AD_PD_N         (1<<4)
+#define CFG_REGS_AU_DAC_PD_N        (1<<5)
+#define CFG_REGS_AU_DAC_RESET_N     (1<<8)
+#define CFG_REGS_AU_PLL_PU          (1<<16)
+
+//audio_pd_clr
+//#define CFG_REGS_AU_DEEP_PD_N     (1<<0)
+//#define CFG_REGS_AU_REF_PD_N      (1<<1)
+//#define CFG_REGS_AU_MIC_PD_N      (1<<2)
+//#define CFG_REGS_AU_AUXMIC_PD_N   (1<<3)
+//#define CFG_REGS_AU_AD_PD_N       (1<<4)
+//#define CFG_REGS_AU_DAC_PD_N      (1<<5)
+//#define CFG_REGS_AU_DAC_RESET_N   (1<<8)
+//#define CFG_REGS_AU_PLL_PU        (1<<16)
+
+//audio_sel_cfg
+#define CFG_REGS_AU_AUXMIC_SEL      (1<<0)
+#define CFG_REGS_AU_SPK_SEL         (1<<1)
+#define CFG_REGS_AU_SPK_MONO_SEL    (1<<2)
+#define CFG_REGS_AU_RCV_SEL         (1<<3)
+#define CFG_REGS_AU_HEAD_SEL        (1<<4)
+
+//audio_mic_cfg
+#define CFG_REGS_AU_MIC_GAIN(n)     (((n)&15)<<0)
+#define CFG_REGS_AU_MIC_GAIN_MASK   (15<<0)
+#define CFG_REGS_AU_MIC_GAIN_SHIFT  (0)
+#define CFG_REGS_AU_MIC_MUTE_N      (1<<4)
+
+//audio_spk_cfg
+#define CFG_REGS_AU_SPK_GAIN(n)     (((n)&15)<<0)
+#define CFG_REGS_AU_SPK_GAIN_MASK   (15<<0)
+#define CFG_REGS_AU_SPK_GAIN_SHIFT  (0)
+#define CFG_REGS_AU_SPK_MUTE_N      (1<<4)
+
+//audio_rcv_gain
+#define CFG_REGS_AU_RCV_GAIN(n)     (((n)&15)<<0)
+#define CFG_REGS_AU_RCV_GAIN_MASK   (15<<0)
+#define CFG_REGS_AU_RCV_GAIN_SHIFT  (0)
+
+//audio_head_gain
+#define CFG_REGS_AU_HEAD_GAIN(n)    (((n)&15)<<0)
+#define CFG_REGS_AU_HEAD_GAIN_MASK  (15<<0)
+#define CFG_REGS_AU_HEAD_GAIN_SHIFT (0)
+
+//TSC_DATA
+#define CFG_REGS_TSC_X_VALUE_BIT(n) (((n)&0x3FF)<<0)
+#define CFG_REGS_TSC_X_VALUE_BIT_MASK (0x3FF<<0)
+#define CFG_REGS_TSC_X_VALUE_BIT_SHIFT (0)
+#define CFG_REGS_TSC_X_VALUE_VALID  (1<<10)
+#define CFG_REGS_TSC_Y_VALUE_BIT(n) (((n)&0x3FF)<<11)
+#define CFG_REGS_TSC_Y_VALUE_BIT_MASK (0x3FF<<11)
+#define CFG_REGS_TSC_Y_VALUE_BIT_SHIFT (11)
+#define CFG_REGS_TSC_Y_VALUE_VALID  (1<<21)
+
+//GPADC_DATA_CH
+#define CFG_REGS_GPADC_DATA(n)      (((n)&0x3FF)<<0)
+#define CFG_REGS_GPADC_DATA_MASK    (0x3FF<<0)
+#define CFG_REGS_GPADC_DATA_SHIFT   (0)
+#define CFG_REGS_GPADC_VALID        (1<<10)
+#define CFG_REGS_GPADC_CH_EN        (1<<31)
+
+
+
+
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8810e.h b/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8810e.h
new file mode 100644
index 0000000000..e659daf337
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8810e.h
@@ -0,0 +1,1302 @@
+//==============================================================================
+//
+//            Copyright (C) 2012-2014, RDA Microelectronics.
+//                            All Rights Reserved
+//
+//      This source code is the property of RDA Microelectronics and is
+//      confidential.  Any  modification, distribution,  reproduction or
+//      exploitation  of  any content of this file is totally forbidden,
+//      except  with the  written permission  of   RDA Microelectronics.
+//
+//==============================================================================
+//
+//    THIS FILE WAS GENERATED FROM ITS CORRESPONDING XML VERSION WITH COOLXML.
+//
+//                       !!! PLEASE DO NOT EDIT !!!
+//
+//  $HeadURL$
+//  $Author$
+//  $Date$
+//  $Revision$
+//
+//==============================================================================
+//
+/// @file
+//
+//==============================================================================
+
+#ifndef _CFG_REGS_H_
+#define _CFG_REGS_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+#ifdef CT_ASM
+#error "You are trying to use in an assembly code the normal H description of 'cfg_regs'."
+#endif
+
+
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+#define PROD_ID                                 (0X810E)
+
+// ============================================================================
+// BB_GPIO_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// BB GPIO Map
+    BB_PIN_NONE_0                               = 0x00000000,
+    BB_PIN_1                                    = 0x00000001,
+    BB_PIN_2                                    = 0x00000002,
+    BB_PIN_3                                    = 0x00000003,
+    BB_PIN_4                                    = 0x00000004,
+    BB_PIN_5                                    = 0x00000005,
+    BB_PIN_UART1_RXD                            = 0x00000006,
+    BB_PIN_UART2_RXD                            = 0x00000007,
+    BB_PIN_UART2_TXD                            = 0x00000008,
+    BB_PIN_SSD1_CLK                             = 0x00000009,
+    BB_PIN_SSD1_CMD                             = 0x0000000A,
+    BB_PIN_SDAT1_0                              = 0x0000000B,
+    BB_PIN_SDAT1_1                              = 0x0000000C,
+    BB_PIN_SDAT1_2                              = 0x0000000D,
+    BB_PIN_SDAT1_3                              = 0x0000000E,
+    BB_PIN_SSD2_CLK                             = 0x0000000F,
+    BB_PIN_SSD2_CMD                             = 0x00000010,
+    BB_PIN_SDAT2_0                              = 0x00000011,
+    BB_PIN_SDAT2_1                              = 0x00000012,
+    BB_PIN_SDAT2_2                              = 0x00000013,
+    BB_PIN_SDAT2_3                              = 0x00000014,
+    BB_PIN_SPI1_CLK                             = 0x00000015,
+    BB_PIN_SPI1_CS_0                            = 0x00000016,
+    BB_PIN_SPI1_DIO                             = 0x00000017,
+    BB_PIN_SPI1_DI                              = 0x00000018,
+    BB_PIN_SIM2_RST                             = 0x00000019,
+    BB_PIN_SIM2_CLK                             = 0x0000001A,
+    BB_PIN_SIM2_DIO                             = 0x0000001B,
+    BB_PIN_SIM3_RST                             = 0x0000001C,
+    BB_PIN_SIM3_CLK                             = 0x0000001D,
+    BB_PIN_SIM3_DIO                             = 0x0000001E
+} BB_GPIO_MAPPING_T;
+
+#define BB_GPIO_NB                              (31)
+
+// ============================================================================
+// AP_GPIO_A_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP GPIO A Map
+    AP_PIN_I2C2_SCL                             = 0x00000000,
+    AP_PIN_I2C2_SDA                             = 0x00000001,
+    AP_PIN_SPI2_CLK                             = 0x00000002,
+    AP_PIN_SPI2_DIO                             = 0x00000003,
+    AP_PIN_SPI2_DI                              = 0x00000004,
+    AP_PIN_SPI2_CS_0                            = 0x00000005,
+    AP_PIN_SPI2_CS_1                            = 0x00000006,
+    AP_PIN_KEYIN_4                              = 0x00000007,
+    AP_PIN_CLK_OUT                              = 0x00000008,
+    AP_PIN_I2S_BCK                              = 0x00000009,
+    AP_PIN_I2S_LRCK                             = 0x0000000A,
+    AP_PIN_I2S_DI_0                             = 0x0000000B,
+    AP_PIN_I2S_DI_1                             = 0x0000000C,
+    AP_PIN_I2S_DO                               = 0x0000000D,
+    AP_PIN_UART1_TXD                            = 0x0000000E,
+    AP_PIN_UART1_CTS                            = 0x0000000F,
+    AP_PIN_UART1_RTS                            = 0x00000010,
+    AP_PIN_SPI1_CS_1                            = 0x00000011,
+    AP_PIN_LCD_DATA_6                           = 0x00000012,
+    AP_PIN_LCD_DATA_7                           = 0x00000013,
+    AP_PIN_LCD_WR                               = 0x00000014,
+    AP_PIN_LCD_RS                               = 0x00000015,
+    AP_PIN_LCD_RD                               = 0x00000016,
+    AP_PIN_LCD_FMARK                            = 0x00000017,
+    AP_PIN_LCD_DATA_8                           = 0x00000018,
+    AP_PIN_LCD_DATA_9                           = 0x00000019,
+    AP_PIN_LCD_DATA_10                          = 0x0000001A,
+    AP_PIN_LCD_DATA_11                          = 0x0000001B,
+    AP_PIN_LCD_DATA_12                          = 0x0000001C,
+    AP_PIN_LCD_DATA_13                          = 0x0000001D,
+    AP_PIN_LCD_DATA_14                          = 0x0000001E,
+    AP_PIN_LCD_DATA_15                          = 0x0000001F
+} AP_GPIO_A_MAPPING_T;
+
+#define AP_GPIO_A_NB                            (32)
+
+// ============================================================================
+// AP_GPIO_B_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP GPIO B Map
+    AP_PIN_KEYIN_0                              = 0x00000000,
+    AP_PIN_KEYIN_1                              = 0x00000001,
+    AP_PIN_KEYIN_2                              = 0x00000002,
+    AP_PIN_KEYOUT_0                             = 0x00000003,
+    AP_PIN_KEYOUT_1                             = 0x00000004,
+    AP_PIN_KEYOUT_2                             = 0x00000005,
+    AP_PIN_I2C3_SCL                             = 0x00000006,
+    AP_PIN_I2C3_SDA                             = 0x00000007,
+    AP_PIN_UART2_CTS                            = 0x00000008,
+    AP_PIN_UART2_RTS                            = 0x00000009,
+    AP_PIN_CAM_RST                              = 0x0000000A,
+    AP_PIN_CAM_PDN                              = 0x0000000B,
+    AP_PIN_CAM_CLK                              = 0x0000000C,
+    AP_PIN_CAM_VSYNC                            = 0x0000000D,
+    AP_PIN_CAM_HREF                             = 0x0000000E,
+    AP_PIN_CAM_PCLK                             = 0x0000000F,
+    AP_PIN_CAM_DATA_0                           = 0x00000010,
+    AP_PIN_CAM_DATA_1                           = 0x00000011,
+    AP_PIN_CAM_DATA_2                           = 0x00000012,
+    AP_PIN_CAM_DATA_3                           = 0x00000013,
+    AP_PIN_CAM_DATA_4                           = 0x00000014,
+    AP_PIN_CAM_DATA_5                           = 0x00000015,
+    AP_PIN_CAM_DATA_6                           = 0x00000016,
+    AP_PIN_CAM_DATA_7                           = 0x00000017,
+    AP_PIN_M_SPI_CS_0                           = 0x00000018,
+    AP_PIN_NFCLE                                = 0x00000019,
+    AP_PIN_NFWEN                                = 0x0000001A,
+    AP_PIN_NFWPN                                = 0x0000001B,
+    AP_PIN_NFREN                                = 0x0000001C,
+    AP_PIN_NFRB                                 = 0x0000001D,
+    AP_PIN_I2C1_SCL                             = 0x0000001E,
+    AP_PIN_I2C1_SDA                             = 0x0000001F
+} AP_GPIO_B_MAPPING_T;
+
+#define AP_GPIO_B_NB                            (32)
+
+// ============================================================================
+// AP_GPIO_D_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP GPIO D Map
+    AP_PIN_UART3_RXD                            = 0x00000000,
+    AP_PIN_UART3_TXD                            = 0x00000001,
+    AP_PIN_UART3_CTS                            = 0x00000002,
+    AP_PIN_UART3_RTS                            = 0x00000003,
+    AP_PIN_NFDQS                                = 0x00000004,
+    AP_PIN_VOLUME_DN                            = 0x00000005,
+    AP_PIN_VOLUME_UP                            = 0x00000006,
+    AP_PIN_PLUGIN                               = 0x00000007,
+    AP_PIN_NFCEN_1                              = 0x00000008,
+    AP_PIN_NFCEN_2                              = 0x00000009,
+    AP_PIN_NFCEN_3                              = 0x0000000A,
+    AP_PIN_I2S2_BCK                             = 0x0000000B,
+    AP_PIN_I2S2_LRCK                            = 0x0000000C,
+    AP_PIN_I2S2_DI_0                            = 0x0000000D,
+    AP_PIN_I2S2_DI_1                            = 0x0000000E,
+    AP_PIN_I2S2_DO                              = 0x0000000F
+} AP_GPIO_D_MAPPING_T;
+
+#define AP_GPIO_D_NB                            (16)
+
+// ============================================================================
+// AP_GPIO_E_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP GPIO E Map
+    AP_PIN_I2CBB_SCL                            = 0x00000000,
+    AP_PIN_I2CBB_SDA                            = 0x00000001,
+    AP_PIN_CAM2_RST                             = 0x00000002,
+    AP_PIN_CAM2_PDN                             = 0x00000003,
+    AP_PIN_CAM2_CLK                             = 0x00000004,
+    AP_PIN_CAM2_VSYNC                           = 0x00000005,
+    AP_PIN_CAM2_HREF                            = 0x00000006,
+    AP_PIN_CAM2_PCLK                            = 0x00000007,
+    AP_PIN_CAM2_DATA_0                          = 0x00000008,
+    AP_PIN_CAM2_DATA_1                          = 0x00000009,
+    AP_PIN_CAM2_DATA_2                          = 0x0000000A,
+    AP_PIN_CAM2_DATA_3                          = 0x0000000B,
+    AP_PIN_CAM2_DATA_4                          = 0x0000000C,
+    AP_PIN_CAM2_DATA_5                          = 0x0000000D,
+    AP_PIN_CAM2_DATA_6                          = 0x0000000E,
+    AP_PIN_CAM2_DATA_7                          = 0x0000000F
+} AP_GPIO_E_MAPPING_T;
+
+#define AP_GPIO_E_NB                            (16)
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+// ============================================================================
+// CFG_REGS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+#define REG_CONFIG_REGS_BASE       0x01A09000
+
+typedef volatile struct
+{
+    REG32                          CHIP_ID;                      //0x00000000
+    /// This register contain the synthesis date and version
+    REG32                          Build_Version;                //0x00000004
+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+    /// bit n to '0' selects Alt.
+    REG32                          BB_GPIO_Mode;                 //0x00000008
+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+    /// bit n to '0' selects Alt.
+    REG32                          AP_GPIO_A_Mode;               //0x0000000C
+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+    /// bit n to '0' selects Alt.
+    REG32                          AP_GPIO_B_Mode;               //0x00000010
+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+    /// bit n to '0' selects Alt.
+    REG32                          AP_GPIO_D_Mode;               //0x00000014
+    REG32                          Alt_mux_select;               //0x00000018
+    REG32                          IO_Drive1_Select;             //0x0000001C
+    REG32                          IO_Drive2_Select;             //0x00000020
+    REG32                          RAM_DRIVE;                    //0x00000024
+    REG32                          H2X_AP_Offset;                //0x00000028
+    REG32                          H2X_DDR_Offset;               //0x0000002C
+    REG32                          audio_pd_set;                 //0x00000030
+    REG32                          audio_pd_clr;                 //0x00000034
+    REG32                          audio_sel_cfg;                //0x00000038
+    REG32                          audio_mic_cfg;                //0x0000003C
+    REG32                          audio_spk_cfg;                //0x00000040
+    REG32                          audio_rcv_gain;               //0x00000044
+    REG32                          audio_head_gain;              //0x00000048
+    REG32                          TSC_DATA;                     //0x0000004C
+    REG32                          GPADC_DATA_CH[8];             //0x00000050
+    REG32                          Alt_mux_select2;              //0x00000070
+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+    /// bit n to '0' selects Alt.
+    REG32                          AP_GPIO_E_Mode;               //0x00000074
+} HWP_CFG_REGS_T;
+
+#define hwp_configRegs             ((HWP_CFG_REGS_T*) (RDA_CFG_REGS_BASE))
+
+
+//CHIP_ID
+#define CFG_REGS_METAL_ID(n)       (((n)&0xFFF)<<0)
+#define CFG_REGS_METAL_ID_MASK     (0xFFF<<0)
+#define CFG_REGS_METAL_ID_SHIFT    (0)
+#define CFG_REGS_BOND_ID(n)        (((n)&7)<<12)
+#define CFG_REGS_BOND_ID_MASK      (7<<12)
+#define CFG_REGS_BOND_ID_SHIFT     (12)
+#define CFG_REGS_PROD_ID(n)        (((n)&0xFFFF)<<16)
+#define CFG_REGS_PROD_ID_MASK      (0xFFFF<<16)
+#define CFG_REGS_PROD_ID_SHIFT     (16)
+
+//Build_Version
+#define CFG_REGS_MAJOR(n)          (((n)&15)<<28)
+#define CFG_REGS_YEAR(n)           (((n)&15)<<24)
+#define CFG_REGS_MONTH(n)          (((n)&0xFF)<<16)
+#define CFG_REGS_DAY(n)            (((n)&0xFF)<<8)
+#define CFG_REGS_BUILD_STYLE_FPGA  (0<<4)
+#define CFG_REGS_BUILD_STYLE_CHIP  (1<<4)
+#define CFG_REGS_BUILD_STYLE_FPGA_USB (2<<4)
+#define CFG_REGS_BUILD_STYLE_FPGA_GSM (3<<4)
+#define CFG_REGS_BUILD_REVISION(n) (((n)&15)<<0)
+
+//BB_GPIO_Mode
+#define CFG_REGS_MODE_BB_PIN_NONE_0 (1<<0)
+#define CFG_REGS_MODE_BB_PIN_NONE_0_MASK (1<<0)
+#define CFG_REGS_MODE_BB_PIN_NONE_0_SHIFT (0)
+#define CFG_REGS_MODE_BB_PIN_NONE_0_ALT (0<<0)
+#define CFG_REGS_MODE_BB_PIN_NONE_0_GPIO (1<<0)
+#define CFG_REGS_MODE_BB_PIN_1     (1<<1)
+#define CFG_REGS_MODE_BB_PIN_1_MASK (1<<1)
+#define CFG_REGS_MODE_BB_PIN_1_SHIFT (1)
+#define CFG_REGS_MODE_BB_PIN_1_ALT (0<<1)
+#define CFG_REGS_MODE_BB_PIN_1_GPIO (1<<1)
+#define CFG_REGS_MODE_BB_PIN_2     (1<<2)
+#define CFG_REGS_MODE_BB_PIN_2_MASK (1<<2)
+#define CFG_REGS_MODE_BB_PIN_2_SHIFT (2)
+#define CFG_REGS_MODE_BB_PIN_2_ALT (0<<2)
+#define CFG_REGS_MODE_BB_PIN_2_GPIO (1<<2)
+#define CFG_REGS_MODE_BB_PIN_3     (1<<3)
+#define CFG_REGS_MODE_BB_PIN_3_MASK (1<<3)
+#define CFG_REGS_MODE_BB_PIN_3_SHIFT (3)
+#define CFG_REGS_MODE_BB_PIN_3_ALT (0<<3)
+#define CFG_REGS_MODE_BB_PIN_3_GPIO (1<<3)
+#define CFG_REGS_MODE_BB_PIN_4     (1<<4)
+#define CFG_REGS_MODE_BB_PIN_4_MASK (1<<4)
+#define CFG_REGS_MODE_BB_PIN_4_SHIFT (4)
+#define CFG_REGS_MODE_BB_PIN_4_ALT (0<<4)
+#define CFG_REGS_MODE_BB_PIN_4_GPIO (1<<4)
+#define CFG_REGS_MODE_BB_PIN_5     (1<<5)
+#define CFG_REGS_MODE_BB_PIN_5_MASK (1<<5)
+#define CFG_REGS_MODE_BB_PIN_5_SHIFT (5)
+#define CFG_REGS_MODE_BB_PIN_5_ALT (0<<5)
+#define CFG_REGS_MODE_BB_PIN_5_GPIO (1<<5)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD (1<<6)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_MASK (1<<6)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_SHIFT (6)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_ALT (0<<6)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_GPIO (1<<6)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD (1<<7)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_MASK (1<<7)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_SHIFT (7)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_ALT (0<<7)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_GPIO (1<<7)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD (1<<8)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_MASK (1<<8)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_SHIFT (8)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_ALT (0<<8)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_GPIO (1<<8)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK (1<<9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_MASK (1<<9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_SHIFT (9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_ALT (0<<9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_GPIO (1<<9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD (1<<10)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_MASK (1<<10)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_SHIFT (10)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_ALT (0<<10)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_GPIO (1<<10)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0 (1<<11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_MASK (1<<11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_SHIFT (11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_ALT (0<<11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_GPIO (1<<11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1 (1<<12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_MASK (1<<12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_SHIFT (12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_ALT (0<<12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_GPIO (1<<12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2 (1<<13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_MASK (1<<13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_SHIFT (13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_ALT (0<<13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_GPIO (1<<13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3 (1<<14)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_MASK (1<<14)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_SHIFT (14)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_ALT (0<<14)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_GPIO (1<<14)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK (1<<15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_MASK (1<<15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_SHIFT (15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_ALT (0<<15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_GPIO (1<<15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD (1<<16)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_MASK (1<<16)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_SHIFT (16)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_ALT (0<<16)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_GPIO (1<<16)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0 (1<<17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_MASK (1<<17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_SHIFT (17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_ALT (0<<17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_GPIO (1<<17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1 (1<<18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_MASK (1<<18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_SHIFT (18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_ALT (0<<18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_GPIO (1<<18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2 (1<<19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_MASK (1<<19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_SHIFT (19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_ALT (0<<19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_GPIO (1<<19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3 (1<<20)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_MASK (1<<20)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_SHIFT (20)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_ALT (0<<20)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_GPIO (1<<20)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK (1<<21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_MASK (1<<21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_SHIFT (21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_ALT (0<<21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_GPIO (1<<21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0 (1<<22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_MASK (1<<22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_SHIFT (22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_ALT (0<<22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_GPIO (1<<22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO (1<<23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_MASK (1<<23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_SHIFT (23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_ALT (0<<23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_GPIO (1<<23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI (1<<24)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_MASK (1<<24)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_SHIFT (24)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_ALT (0<<24)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_GPIO (1<<24)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST (1<<25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_MASK (1<<25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_SHIFT (25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_ALT (0<<25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_GPIO (1<<25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK (1<<26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_MASK (1<<26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_SHIFT (26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_ALT (0<<26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_GPIO (1<<26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO (1<<27)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_MASK (1<<27)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_SHIFT (27)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_ALT (0<<27)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_GPIO (1<<27)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST (1<<28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_MASK (1<<28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_SHIFT (28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_ALT (0<<28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_GPIO (1<<28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK (1<<29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_MASK (1<<29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_SHIFT (29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_ALT (0<<29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_GPIO (1<<29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO (1<<30)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_MASK (1<<30)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_SHIFT (30)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_ALT (0<<30)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_GPIO (1<<30)
+#define CFG_REGS_BB_GPIO_MODE(n)   (((n)&0x7FFFFFFF)<<0)
+#define CFG_REGS_BB_GPIO_MODE_MASK (0x7FFFFFFF<<0)
+#define CFG_REGS_BB_GPIO_MODE_SHIFT (0)
+
+//AP_GPIO_A_Mode
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_MASK (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_SHIFT (0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_ALT (0<<0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_GPIO (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA (1<<1)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_MASK (1<<1)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_SHIFT (1)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_ALT (0<<1)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_GPIO (1<<1)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_MASK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_SHIFT (2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_ALT (0<<2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_GPIO (1<<2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_MASK (1<<3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_SHIFT (3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_ALT (0<<3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_GPIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI (1<<4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_MASK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_SHIFT (4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_ALT (0<<4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_GPIO (1<<4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0 (1<<5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_MASK (1<<5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_SHIFT (5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_ALT (0<<5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_GPIO (1<<5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1 (1<<6)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_MASK (1<<6)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_SHIFT (6)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_ALT (0<<6)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_GPIO (1<<6)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4 (1<<7)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_MASK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_SHIFT (7)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_ALT (0<<7)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_GPIO (1<<7)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT (1<<8)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_MASK (1<<8)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_SHIFT (8)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_ALT (0<<8)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_GPIO (1<<8)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_MASK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_SHIFT (9)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_ALT (0<<9)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_GPIO (1<<9)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_MASK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_SHIFT (10)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_ALT (0<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_GPIO (1<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0 (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_MASK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_SHIFT (11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_ALT (0<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_GPIO (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1 (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_MASK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_SHIFT (12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_ALT (0<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_GPIO (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO_MASK (1<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO_SHIFT (13)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO_ALT (0<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO_GPIO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD (1<<14)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_MASK (1<<14)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_SHIFT (14)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_ALT (0<<14)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_GPIO (1<<14)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS (1<<15)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_MASK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_SHIFT (15)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_ALT (0<<15)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_GPIO (1<<15)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS (1<<16)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_MASK (1<<16)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_SHIFT (16)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_ALT (0<<16)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_GPIO (1<<16)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1 (1<<17)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_MASK (1<<17)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_SHIFT (17)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_ALT (0<<17)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_GPIO (1<<17)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6 (1<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_MASK (1<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_SHIFT (18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_ALT (0<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_GPIO (1<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7 (1<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_MASK (1<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_SHIFT (19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_ALT (0<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_GPIO (1<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR (1<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR_MASK (1<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR_SHIFT (20)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR_ALT (0<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR_GPIO (1<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS (1<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS_MASK (1<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS_SHIFT (21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS_ALT (0<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS_GPIO (1<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD (1<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD_MASK (1<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD_SHIFT (22)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD_ALT (0<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD_GPIO (1<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK (1<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_MASK (1<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_SHIFT (23)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_ALT (0<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_GPIO (1<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8 (1<<24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_MASK (1<<24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_SHIFT (24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_ALT (0<<24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_GPIO (1<<24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9 (1<<25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_MASK (1<<25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_SHIFT (25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_ALT (0<<25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_GPIO (1<<25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10 (1<<26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_MASK (1<<26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_SHIFT (26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_ALT (0<<26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_GPIO (1<<26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11 (1<<27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_MASK (1<<27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_SHIFT (27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_ALT (0<<27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_GPIO (1<<27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12 (1<<28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_MASK (1<<28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_SHIFT (28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_ALT (0<<28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_GPIO (1<<28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13 (1<<29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_MASK (1<<29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_SHIFT (29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_ALT (0<<29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_GPIO (1<<29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14 (1<<30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_MASK (1<<30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_SHIFT (30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_ALT (0<<30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_GPIO (1<<30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15 (1<<31)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_MASK (1<<31)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_SHIFT (31)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_ALT (0<<31)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_GPIO (1<<31)
+#define CFG_REGS_AP_GPIO_A_MODE(n) (((n)&0xFFFFFFFF)<<0)
+#define CFG_REGS_AP_GPIO_A_MODE_MASK (0xFFFFFFFF<<0)
+#define CFG_REGS_AP_GPIO_A_MODE_SHIFT (0)
+
+//AP_GPIO_B_Mode
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0 (1<<0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_MASK (1<<0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_SHIFT (0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_ALT (0<<0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_GPIO (1<<0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1 (1<<1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_MASK (1<<1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_SHIFT (1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_ALT (0<<1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_GPIO (1<<1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2 (1<<2)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_MASK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_SHIFT (2)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_ALT (0<<2)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_GPIO (1<<2)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0 (1<<3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_MASK (1<<3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_SHIFT (3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_ALT (0<<3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_GPIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1 (1<<4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_MASK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_SHIFT (4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_ALT (0<<4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_GPIO (1<<4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2 (1<<5)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_MASK (1<<5)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_SHIFT (5)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_ALT (0<<5)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_GPIO (1<<5)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL (1<<6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_MASK (1<<6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_SHIFT (6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_ALT (0<<6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_GPIO (1<<6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA (1<<7)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_MASK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_SHIFT (7)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_ALT (0<<7)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_GPIO (1<<7)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS (1<<8)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_MASK (1<<8)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_SHIFT (8)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_ALT (0<<8)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_GPIO (1<<8)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS (1<<9)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_MASK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_SHIFT (9)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_ALT (0<<9)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_GPIO (1<<9)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST_MASK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST_SHIFT (10)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST_ALT (0<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST_GPIO (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_MASK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_SHIFT (11)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_ALT (0<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_GPIO (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_MASK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_SHIFT (12)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_ALT (0<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_GPIO (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_MASK (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_SHIFT (13)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_ALT (0<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_GPIO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_MASK (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_SHIFT (14)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_ALT (0<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_GPIO (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_MASK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_SHIFT (15)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_ALT (0<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_GPIO (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0 (1<<16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_MASK (1<<16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_SHIFT (16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_ALT (0<<16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_GPIO (1<<16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1 (1<<17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_MASK (1<<17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_SHIFT (17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_ALT (0<<17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_GPIO (1<<17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2 (1<<18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_MASK (1<<18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_SHIFT (18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_ALT (0<<18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_GPIO (1<<18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3 (1<<19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_MASK (1<<19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_SHIFT (19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_ALT (0<<19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_GPIO (1<<19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4 (1<<20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_MASK (1<<20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_SHIFT (20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_ALT (0<<20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_GPIO (1<<20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5 (1<<21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_MASK (1<<21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_SHIFT (21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_ALT (0<<21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_GPIO (1<<21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6 (1<<22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_MASK (1<<22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_SHIFT (22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_ALT (0<<22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_GPIO (1<<22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7 (1<<23)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_MASK (1<<23)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_SHIFT (23)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_ALT (0<<23)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_GPIO (1<<23)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0 (1<<24)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_MASK (1<<24)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_SHIFT (24)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_ALT (0<<24)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_GPIO (1<<24)
+#define CFG_REGS_MODE_AP_PIN_NFCLE (1<<25)
+#define CFG_REGS_MODE_AP_PIN_NFCLE_MASK (1<<25)
+#define CFG_REGS_MODE_AP_PIN_NFCLE_SHIFT (25)
+#define CFG_REGS_MODE_AP_PIN_NFCLE_ALT (0<<25)
+#define CFG_REGS_MODE_AP_PIN_NFCLE_GPIO (1<<25)
+#define CFG_REGS_MODE_AP_PIN_NFWEN (1<<26)
+#define CFG_REGS_MODE_AP_PIN_NFWEN_MASK (1<<26)
+#define CFG_REGS_MODE_AP_PIN_NFWEN_SHIFT (26)
+#define CFG_REGS_MODE_AP_PIN_NFWEN_ALT (0<<26)
+#define CFG_REGS_MODE_AP_PIN_NFWEN_GPIO (1<<26)
+#define CFG_REGS_MODE_AP_PIN_NFWPN (1<<27)
+#define CFG_REGS_MODE_AP_PIN_NFWPN_MASK (1<<27)
+#define CFG_REGS_MODE_AP_PIN_NFWPN_SHIFT (27)
+#define CFG_REGS_MODE_AP_PIN_NFWPN_ALT (0<<27)
+#define CFG_REGS_MODE_AP_PIN_NFWPN_GPIO (1<<27)
+#define CFG_REGS_MODE_AP_PIN_NFREN (1<<28)
+#define CFG_REGS_MODE_AP_PIN_NFREN_MASK (1<<28)
+#define CFG_REGS_MODE_AP_PIN_NFREN_SHIFT (28)
+#define CFG_REGS_MODE_AP_PIN_NFREN_ALT (0<<28)
+#define CFG_REGS_MODE_AP_PIN_NFREN_GPIO (1<<28)
+#define CFG_REGS_MODE_AP_PIN_NFRB  (1<<29)
+#define CFG_REGS_MODE_AP_PIN_NFRB_MASK (1<<29)
+#define CFG_REGS_MODE_AP_PIN_NFRB_SHIFT (29)
+#define CFG_REGS_MODE_AP_PIN_NFRB_ALT (0<<29)
+#define CFG_REGS_MODE_AP_PIN_NFRB_GPIO (1<<29)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL (1<<30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_MASK (1<<30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_SHIFT (30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_ALT (0<<30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_GPIO (1<<30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA (1<<31)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_MASK (1<<31)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_SHIFT (31)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_ALT (0<<31)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_GPIO (1<<31)
+#define CFG_REGS_AP_GPIO_B_MODE(n) (((n)&0xFFFFFFFF)<<0)
+#define CFG_REGS_AP_GPIO_B_MODE_MASK (0xFFFFFFFF<<0)
+#define CFG_REGS_AP_GPIO_B_MODE_SHIFT (0)
+
+//AP_GPIO_D_Mode
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD (1<<0)
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_MASK (1<<0)
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_SHIFT (0)
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_ALT (0<<0)
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_GPIO (1<<0)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD (1<<1)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_MASK (1<<1)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_SHIFT (1)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_ALT (0<<1)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_GPIO (1<<1)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS (1<<2)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_MASK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_SHIFT (2)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_ALT (0<<2)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_GPIO (1<<2)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS (1<<3)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_MASK (1<<3)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_SHIFT (3)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_ALT (0<<3)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_GPIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_NFDQS (1<<4)
+#define CFG_REGS_MODE_AP_PIN_NFDQS_MASK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_NFDQS_SHIFT (4)
+#define CFG_REGS_MODE_AP_PIN_NFDQS_ALT (0<<4)
+#define CFG_REGS_MODE_AP_PIN_NFDQS_GPIO (1<<4)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN (1<<5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_MASK (1<<5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_SHIFT (5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_ALT (0<<5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_GPIO (1<<5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP (1<<6)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_MASK (1<<6)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_SHIFT (6)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_ALT (0<<6)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_GPIO (1<<6)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN (1<<7)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN_MASK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN_SHIFT (7)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN_ALT (0<<7)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN_GPIO (1<<7)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1 (1<<8)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1_MASK (1<<8)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1_SHIFT (8)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1_ALT (0<<8)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1_GPIO (1<<8)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2 (1<<9)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2_MASK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2_SHIFT (9)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2_ALT (0<<9)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2_GPIO (1<<9)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3 (1<<10)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3_MASK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3_SHIFT (10)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3_ALT (0<<10)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3_GPIO (1<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_MASK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_SHIFT (11)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_ALT (0<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_GPIO (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_MASK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_SHIFT (12)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_ALT (0<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_GPIO (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0 (1<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_MASK (1<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_SHIFT (13)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_ALT (0<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_GPIO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1 (1<<14)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_MASK (1<<14)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_SHIFT (14)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_ALT (0<<14)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_GPIO (1<<14)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO (1<<15)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO_MASK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO_SHIFT (15)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO_ALT (0<<15)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO_GPIO (1<<15)
+#define CFG_REGS_AP_GPIO_D_MODE(n) (((n)&0xFFFF)<<0)
+#define CFG_REGS_AP_GPIO_D_MODE_MASK (0xFFFF<<0)
+#define CFG_REGS_AP_GPIO_D_MODE_SHIFT (0)
+
+//Alt_mux_select
+#define CFG_REGS_LCD_MODE_MASK     (3<<0)
+#define CFG_REGS_LCD_MODE_PARALLEL_16BIT (0<<0)
+#define CFG_REGS_LCD_MODE_DSI      (1<<0)
+#define CFG_REGS_LCD_MODE_RGB_24BIT (2<<0)
+#define CFG_REGS_LCD_MODE_RGB_16BIT (3<<0)
+#define CFG_REGS_SPI_LCD_MASK      (1<<2)
+#define CFG_REGS_SPI_LCD_NONE      (0<<2)
+#define CFG_REGS_SPI_LCD_SPI_LCD   (1<<2)
+#define CFG_REGS_CAM_I2C2_MASK     (1<<3)
+#define CFG_REGS_CAM_I2C2_CAM      (0<<3)
+#define CFG_REGS_CAM_I2C2_I2C2     (1<<3)
+#define CFG_REGS_CSI2_MASK         (3<<4)
+#define CFG_REGS_CSI2_PARALLEL_CAM (0<<4)
+#define CFG_REGS_CSI2_CSI2         (1<<4)
+#define CFG_REGS_CSI2_SPI_CAM      (2<<4)
+#define CFG_REGS_UART2_MASK        (1<<6)
+#define CFG_REGS_UART2_HOST_UART   (0<<6)
+#define CFG_REGS_UART2_UART2       (1<<6)
+#define CFG_REGS_UART1_8LINE_MASK  (1<<7)
+#define CFG_REGS_UART1_8LINE_UART2 (0<<7)
+#define CFG_REGS_UART1_8LINE_UART1_8_LINE (1<<7)
+#define CFG_REGS_DAI_MASK          (3<<8)
+#define CFG_REGS_DAI_I2S           (0<<8)
+#define CFG_REGS_DAI_DAI           (1<<8)
+#define CFG_REGS_DAI_DAI_SIMPLE    (2<<8)
+#define CFG_REGS_KEYIN_3_MASK      (1<<10)
+#define CFG_REGS_KEYIN_3_SPI2_CS_1 (0<<10)
+#define CFG_REGS_KEYIN_3_KEYIN_3   (1<<10)
+#define CFG_REGS_LPSCO_1_MASK      (1<<11)
+#define CFG_REGS_LPSCO_1_KEYIN_4   (0<<11)
+#define CFG_REGS_LPSCO_1_LPSCO_1   (1<<11)
+#define CFG_REGS_SPI1_CS_2_MASK    (1<<12)
+#define CFG_REGS_SPI1_CS_2_KEYIN_1 (0<<12)
+#define CFG_REGS_SPI1_CS_2_SPI1_CS_2 (1<<12)
+#define CFG_REGS_I2S_DI_2_MASK     (1<<13)
+#define CFG_REGS_I2S_DI_2_KEYIN_2  (0<<13)
+#define CFG_REGS_I2S_DI_2_I2S_DI_2 (1<<13)
+#define CFG_REGS_TCO_0_MASK        (1<<14)
+#define CFG_REGS_TCO_0_KEYOUT_0    (0<<14)
+#define CFG_REGS_TCO_0_TCO_0       (1<<14)
+#define CFG_REGS_TCO_1_MASK        (1<<15)
+#define CFG_REGS_TCO_1_KEYOUT_1    (0<<15)
+#define CFG_REGS_TCO_1_TCO_1       (1<<15)
+#define CFG_REGS_TCO_2_MASK        (1<<16)
+#define CFG_REGS_TCO_2_KEYOUT_2    (0<<16)
+#define CFG_REGS_TCO_2_TCO_2       (1<<16)
+#define CFG_REGS_KEYOUT_3_4_MASK   (1<<17)
+#define CFG_REGS_KEYOUT_3_4_I2C3   (0<<17)
+#define CFG_REGS_KEYOUT_3_4_KEYOUT_3_4 (1<<17)
+#define CFG_REGS_KEYOUT_6_MASK     (1<<18)
+#define CFG_REGS_KEYOUT_6_UART2_RTS (0<<18)
+#define CFG_REGS_KEYOUT_6_KEYOUT_6 (1<<18)
+#define CFG_REGS_KEYOUT_7_MASK     (1<<19)
+#define CFG_REGS_KEYOUT_7_UART1_RTS (0<<19)
+#define CFG_REGS_KEYOUT_7_KEYOUT_7 (1<<19)
+#define CFG_REGS_GPO_0_MASK        (3<<20)
+#define CFG_REGS_GPO_0_GPO_0       (0<<20)
+#define CFG_REGS_GPO_0_PWT         (1<<20)
+#define CFG_REGS_GPO_0_KEYIN_5     (2<<20)
+#define CFG_REGS_GPO_1_MASK        (3<<22)
+#define CFG_REGS_GPO_1_GPO_1       (0<<22)
+#define CFG_REGS_GPO_1_LPG         (1<<22)
+#define CFG_REGS_GPO_1_KEYOUT_5    (2<<22)
+#define CFG_REGS_GPO_2_MASK        (3<<24)
+#define CFG_REGS_GPO_2_GPO_2       (0<<24)
+#define CFG_REGS_GPO_2_PWL_1       (1<<24)
+#define CFG_REGS_GPO_2_CLK_32K     (2<<24)
+#define CFG_REGS_GPO_3_MASK        (1<<26)
+#define CFG_REGS_GPO_3_LCD_CS_1    (0<<26)
+#define CFG_REGS_GPO_3_GPO_3       (1<<26)
+#define CFG_REGS_GPO_4_MASK        (1<<27)
+#define CFG_REGS_GPO_4_LCD_CS_0    (0<<27)
+#define CFG_REGS_GPO_4_GPO_4       (1<<27)
+#define CFG_REGS_CLK_OUT_MASK      (1<<28)
+#define CFG_REGS_CLK_OUT_HST_CLK   (0<<28)
+#define CFG_REGS_CLK_OUT_CLK_OUT   (1<<28)
+#define CFG_REGS_DEBUG_MASK        (1<<29)
+#define CFG_REGS_DEBUG_NONE        (0<<29)
+#define CFG_REGS_DEBUG_DEBUG_MONITOR (1<<29)
+#define CFG_REGS_AP_SPI1_MASK      (1<<30)
+#define CFG_REGS_AP_SPI1_BB_SPI1   (0<<30)
+#define CFG_REGS_AP_SPI1_AP_SPI1   (1<<30)
+#define CFG_REGS_RGB_CAM_MASK      (1<<31)
+#define CFG_REGS_RGB_CAM_DISABLE   (0<<31)
+#define CFG_REGS_RGB_CAM_ENABLE    (1<<31)
+
+//IO_Drive1_Select
+#define CFG_REGS_DDR_DRIVE_MASK    (7<<0)
+#define CFG_REGS_DDR_DRIVE_FAST_AND_MOST_WEAK (7<<0)
+#define CFG_REGS_DDR_DRIVE_FAST_AND_WEAK (6<<0)
+#define CFG_REGS_DDR_DRIVE_FAST_AND_STRONG (5<<0)
+#define CFG_REGS_DDR_DRIVE_FAST_AND_MOST_STRONG (4<<0)
+#define CFG_REGS_DDR_DRIVE_SLOW_AND_MOST_WEAK (3<<0)
+#define CFG_REGS_DDR_DRIVE_SLOW_AND_WEAK (2<<0)
+#define CFG_REGS_DDR_DRIVE_SLOW_AND_STRONG (1<<0)
+#define CFG_REGS_DDR_DRIVE_SLOW_AND_MOST_STRONG (0<<0)
+#define CFG_REGS_PSRAM1_DRIVE_MASK (7<<3)
+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_MOST_WEAK (7<<3)
+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_WEAK (6<<3)
+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_STRONG (5<<3)
+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_MOST_STRONG (4<<3)
+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_MOST_WEAK (3<<3)
+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_WEAK (2<<3)
+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_STRONG (1<<3)
+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_MOST_STRONG (0<<3)
+#define CFG_REGS_PSRAM2_DRIVE_MASK (7<<6)
+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_MOST_WEAK (7<<6)
+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_WEAK (6<<6)
+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_STRONG (5<<6)
+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_MOST_STRONG (4<<6)
+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_MOST_WEAK (3<<6)
+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_WEAK (2<<6)
+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_STRONG (1<<6)
+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_MOST_STRONG (0<<6)
+#define CFG_REGS_NFLSH_DRIVE_MASK  (7<<9)
+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_MOST_WEAK (7<<9)
+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_WEAK (6<<9)
+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_STRONG (5<<9)
+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_MOST_STRONG (4<<9)
+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_MOST_WEAK (3<<9)
+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_WEAK (2<<9)
+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_STRONG (1<<9)
+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_MOST_STRONG (0<<9)
+#define CFG_REGS_LCD1_DRIVE_MASK   (7<<12)
+#define CFG_REGS_LCD1_DRIVE_FAST_AND_MOST_WEAK (7<<12)
+#define CFG_REGS_LCD1_DRIVE_FAST_AND_WEAK (6<<12)
+#define CFG_REGS_LCD1_DRIVE_FAST_AND_STRONG (5<<12)
+#define CFG_REGS_LCD1_DRIVE_FAST_AND_MOST_STRONG (4<<12)
+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_MOST_WEAK (3<<12)
+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_WEAK (2<<12)
+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_STRONG (1<<12)
+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_MOST_STRONG (0<<12)
+#define CFG_REGS_LCD2_DRIVE_MASK   (7<<15)
+#define CFG_REGS_LCD2_DRIVE_FAST_AND_MOST_WEAK (7<<15)
+#define CFG_REGS_LCD2_DRIVE_FAST_AND_WEAK (6<<15)
+#define CFG_REGS_LCD2_DRIVE_FAST_AND_STRONG (5<<15)
+#define CFG_REGS_LCD2_DRIVE_FAST_AND_MOST_STRONG (4<<15)
+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_MOST_WEAK (3<<15)
+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_WEAK (2<<15)
+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_STRONG (1<<15)
+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_MOST_STRONG (0<<15)
+#define CFG_REGS_SDAT1_DRIVE_MASK  (7<<18)
+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_MOST_WEAK (7<<18)
+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_WEAK (6<<18)
+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_STRONG (5<<18)
+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_MOST_STRONG (4<<18)
+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_MOST_WEAK (3<<18)
+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_WEAK (2<<18)
+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_STRONG (1<<18)
+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_MOST_STRONG (0<<18)
+#define CFG_REGS_SDAT2_DRIVE_MASK  (7<<21)
+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_MOST_WEAK (7<<21)
+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_WEAK (6<<21)
+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_STRONG (5<<21)
+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_MOST_STRONG (4<<21)
+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_MOST_WEAK (3<<21)
+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_WEAK (2<<21)
+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_STRONG (1<<21)
+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_MOST_STRONG (0<<21)
+#define CFG_REGS_CAM_DRIVE_MASK    (3<<24)
+#define CFG_REGS_CAM_DRIVE_MOST_STRONG (0<<24)
+#define CFG_REGS_CAM_DRIVE_STRONG  (1<<24)
+#define CFG_REGS_CAM_DRIVE_WEAK    (2<<24)
+#define CFG_REGS_CAM_DRIVE_MOST_WEAK (3<<24)
+#define CFG_REGS_SIM1_DRIVE_MASK   (3<<26)
+#define CFG_REGS_SIM1_DRIVE_MOST_STRONG (0<<26)
+#define CFG_REGS_SIM1_DRIVE_STRONG (1<<26)
+#define CFG_REGS_SIM1_DRIVE_WEAK   (2<<26)
+#define CFG_REGS_SIM1_DRIVE_MOST_WEAK (3<<26)
+#define CFG_REGS_SIM2_DRIVE_MASK   (3<<28)
+#define CFG_REGS_SIM2_DRIVE_MOST_STRONG (0<<28)
+#define CFG_REGS_SIM2_DRIVE_STRONG (1<<28)
+#define CFG_REGS_SIM2_DRIVE_WEAK   (2<<28)
+#define CFG_REGS_SIM2_DRIVE_MOST_WEAK (3<<28)
+#define CFG_REGS_SIM3_DRIVE_MASK   (3<<30)
+#define CFG_REGS_SIM3_DRIVE_MOST_STRONG (0<<30)
+#define CFG_REGS_SIM3_DRIVE_STRONG (1<<30)
+#define CFG_REGS_SIM3_DRIVE_WEAK   (2<<30)
+#define CFG_REGS_SIM3_DRIVE_MOST_WEAK (3<<30)
+
+//IO_Drive2_Select
+#define CFG_REGS_GPIO_DRIVE_MASK   (3<<0)
+#define CFG_REGS_GPIO_DRIVE_MOST_STRONG (0<<0)
+#define CFG_REGS_GPIO_DRIVE_STRONG (1<<0)
+#define CFG_REGS_GPIO_DRIVE_WEAK   (2<<0)
+#define CFG_REGS_GPIO_DRIVE_MOST_WEAK (3<<0)
+#define CFG_REGS_CAM2_DRIVE_MASK   (3<<2)
+#define CFG_REGS_CAM2_DRIVE_MOST_STRONG (0<<2)
+#define CFG_REGS_CAM2_DRIVE_STRONG (1<<2)
+#define CFG_REGS_CAM2_DRIVE_WEAK   (2<<2)
+#define CFG_REGS_CAM2_DRIVE_MOST_WEAK (3<<2)
+
+//RAM_DRIVE
+#define CFG_REGS_MBRAM_A(n)        (((n)&7)<<0)
+#define CFG_REGS_MBRAM_A_MASK      (7<<0)
+#define CFG_REGS_MBRAM_A_SHIFT     (0)
+#define CFG_REGS_MBRAM_W(n)        (((n)&3)<<3)
+#define CFG_REGS_MBRAM_W_MASK      (3<<3)
+#define CFG_REGS_MBRAM_W_SHIFT     (3)
+#define CFG_REGS_MBRAM_R           (1<<5)
+#define CFG_REGS_BBRAM_A(n)        (((n)&7)<<6)
+#define CFG_REGS_BBRAM_A_MASK      (7<<6)
+#define CFG_REGS_BBRAM_A_SHIFT     (6)
+#define CFG_REGS_BBRAM_W(n)        (((n)&3)<<9)
+#define CFG_REGS_BBRAM_W_MASK      (3<<9)
+#define CFG_REGS_BBRAM_W_SHIFT     (9)
+#define CFG_REGS_BBRAM_R           (1<<11)
+#define CFG_REGS_XP_A(n)           (((n)&7)<<12)
+#define CFG_REGS_XP_A_MASK         (7<<12)
+#define CFG_REGS_XP_A_SHIFT        (12)
+#define CFG_REGS_XP_W(n)           (((n)&3)<<15)
+#define CFG_REGS_XP_W_MASK         (3<<15)
+#define CFG_REGS_XP_W_SHIFT        (15)
+#define CFG_REGS_XP_R              (1<<17)
+#define CFG_REGS_BP_A(n)           (((n)&7)<<18)
+#define CFG_REGS_BP_A_MASK         (7<<18)
+#define CFG_REGS_BP_A_SHIFT        (18)
+#define CFG_REGS_BP_W(n)           (((n)&3)<<21)
+#define CFG_REGS_BP_W_MASK         (3<<21)
+#define CFG_REGS_BP_W_SHIFT        (21)
+#define CFG_REGS_BP_R              (1<<23)
+#define CFG_REGS_EV_A(n)           (((n)&7)<<24)
+#define CFG_REGS_EV_A_MASK         (7<<24)
+#define CFG_REGS_EV_A_SHIFT        (24)
+#define CFG_REGS_EV_W(n)           (((n)&3)<<27)
+#define CFG_REGS_EV_W_MASK         (3<<27)
+#define CFG_REGS_EV_W_SHIFT        (27)
+#define CFG_REGS_EV_R              (1<<29)
+
+//H2X_AP_Offset
+#define CFG_REGS_H2X_AP_OFFSET(n)  (((n)&0xFF)<<0)
+#define CFG_REGS_H2X_AP_OFFSET_MASK (0xFF<<0)
+#define CFG_REGS_H2X_AP_OFFSET_SHIFT (0)
+
+//H2X_DDR_Offset
+#define CFG_REGS_H2X_DDR_OFFSET(n) (((n)&0xFF)<<0)
+#define CFG_REGS_H2X_DDR_OFFSET_MASK (0xFF<<0)
+#define CFG_REGS_H2X_DDR_OFFSET_SHIFT (0)
+
+//audio_pd_set
+#define CFG_REGS_AU_DEEP_PD_N      (1<<0)
+#define CFG_REGS_AU_REF_PD_N       (1<<1)
+#define CFG_REGS_AU_MIC_PD_N       (1<<2)
+#define CFG_REGS_AU_AUXMIC_PD_N    (1<<3)
+#define CFG_REGS_AU_AD_PD_N        (1<<4)
+#define CFG_REGS_AU_DAC_PD_N       (1<<5)
+#define CFG_REGS_AU_DAC_RESET_N    (1<<8)
+#define CFG_REGS_AU_PLL_PU         (1<<16)
+
+//audio_pd_clr
+//#define CFG_REGS_AU_DEEP_PD_N    (1<<0)
+//#define CFG_REGS_AU_REF_PD_N     (1<<1)
+//#define CFG_REGS_AU_MIC_PD_N     (1<<2)
+//#define CFG_REGS_AU_AUXMIC_PD_N  (1<<3)
+//#define CFG_REGS_AU_AD_PD_N      (1<<4)
+//#define CFG_REGS_AU_DAC_PD_N     (1<<5)
+//#define CFG_REGS_AU_DAC_RESET_N  (1<<8)
+//#define CFG_REGS_AU_PLL_PU       (1<<16)
+
+//audio_sel_cfg
+#define CFG_REGS_AU_AUXMIC_SEL     (1<<0)
+#define CFG_REGS_AU_SPK_SEL        (1<<1)
+#define CFG_REGS_AU_SPK_MONO_SEL   (1<<2)
+#define CFG_REGS_AU_RCV_SEL        (1<<3)
+#define CFG_REGS_AU_HEAD_SEL       (1<<4)
+
+//audio_mic_cfg
+#define CFG_REGS_AU_MIC_GAIN(n)    (((n)&15)<<0)
+#define CFG_REGS_AU_MIC_GAIN_MASK  (15<<0)
+#define CFG_REGS_AU_MIC_GAIN_SHIFT (0)
+#define CFG_REGS_AU_MIC_MUTE_N     (1<<4)
+
+//audio_spk_cfg
+#define CFG_REGS_AU_SPK_GAIN(n)    (((n)&15)<<0)
+#define CFG_REGS_AU_SPK_GAIN_MASK  (15<<0)
+#define CFG_REGS_AU_SPK_GAIN_SHIFT (0)
+#define CFG_REGS_AU_SPK_MUTE_N     (1<<4)
+#define CFG_REGS_AU_SPK_VOC_GAIN_EN (1<<8)
+
+//audio_rcv_gain
+#define CFG_REGS_AU_RCV_GAIN(n)    (((n)&15)<<0)
+#define CFG_REGS_AU_RCV_GAIN_MASK  (15<<0)
+#define CFG_REGS_AU_RCV_GAIN_SHIFT (0)
+#define CFG_REGS_AU_RCV_VOC_GAIN_EN (1<<8)
+
+//audio_head_gain
+#define CFG_REGS_AU_HEAD_GAIN(n)   (((n)&15)<<0)
+#define CFG_REGS_AU_HEAD_GAIN_MASK (15<<0)
+#define CFG_REGS_AU_HEAD_GAIN_SHIFT (0)
+#define CFG_REGS_AU_HEAD_VOC_GAIN_EN (1<<8)
+
+//TSC_DATA
+#define CFG_REGS_TSC_X_VALUE_BIT(n) (((n)&0x3FF)<<0)
+#define CFG_REGS_TSC_X_VALUE_BIT_MASK (0x3FF<<0)
+#define CFG_REGS_TSC_X_VALUE_BIT_SHIFT (0)
+#define CFG_REGS_TSC_X_VALUE_VALID (1<<10)
+#define CFG_REGS_TSC_Y_VALUE_BIT(n) (((n)&0x3FF)<<11)
+#define CFG_REGS_TSC_Y_VALUE_BIT_MASK (0x3FF<<11)
+#define CFG_REGS_TSC_Y_VALUE_BIT_SHIFT (11)
+#define CFG_REGS_TSC_Y_VALUE_VALID (1<<21)
+
+//GPADC_DATA_CH
+#define CFG_REGS_GPADC_DATA(n)     (((n)&0x3FF)<<0)
+#define CFG_REGS_GPADC_DATA_MASK   (0x3FF<<0)
+#define CFG_REGS_GPADC_DATA_SHIFT  (0)
+#define CFG_REGS_GPADC_VALID       (1<<10)
+#define CFG_REGS_GPADC_CH_EN       (1<<31)
+
+//Alt_mux_select2
+#define CFG_REGS_UART1_SDIO2_MASK  (1<<0)
+#define CFG_REGS_UART1_SDIO2_SDIO2 (0<<0)
+#define CFG_REGS_UART1_SDIO2_UART1 (1<<0)
+#define CFG_REGS_JTAG_EN_MASK      (1<<1)
+#define CFG_REGS_JTAG_EN_DISABLE   (0<<1)
+#define CFG_REGS_JTAG_EN_ENABLE    (1<<1)
+#define CFG_REGS_LCD_RGB_17_16_MASK (1<<2)
+#define CFG_REGS_LCD_RGB_17_16_LCD_CS (0<<2)
+#define CFG_REGS_LCD_RGB_17_16_LCD_DATA (1<<2)
+#define CFG_REGS_CSI2_2_MASK       (3<<3)
+#define CFG_REGS_CSI2_2_PARALLEL_CAM (0<<3)
+#define CFG_REGS_CSI2_2_CSI2       (1<<3)
+#define CFG_REGS_CSI2_2_SPI_CAM    (2<<3)
+#define CFG_REGS_RGB_CAM_2_MASK    (1<<5)
+#define CFG_REGS_RGB_CAM_2_DISABLE (0<<5)
+#define CFG_REGS_RGB_CAM_2_ENABLE  (1<<5)
+#define CFG_REGS_MAC_EN_MASK       (1<<6)
+#define CFG_REGS_MAC_EN_DISABLE    (0<<6)
+#define CFG_REGS_MAC_EN_ENABLE     (1<<6)
+#define CFG_REGS_IOMUX_CFG_RESERVED(n) (((n)&0x1FFFFFF)<<7)
+
+//AP_GPIO_E_Mode
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_MASK (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_SHIFT (0)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_ALT (0<<0)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_GPIO (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA (1<<1)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_MASK (1<<1)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_SHIFT (1)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_ALT (0<<1)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_GPIO (1<<1)
+#define CFG_REGS_MODE_AP_PIN_CAM2_RST (1<<2)
+#define CFG_REGS_MODE_AP_PIN_CAM2_RST_MASK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_CAM2_RST_SHIFT (2)
+#define CFG_REGS_MODE_AP_PIN_CAM2_RST_ALT (0<<2)
+#define CFG_REGS_MODE_AP_PIN_CAM2_RST_GPIO (1<<2)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PDN (1<<3)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_MASK (1<<3)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_SHIFT (3)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_ALT (0<<3)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_GPIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_CAM2_CLK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_MASK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_SHIFT (4)
+#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_ALT (0<<4)
+#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_GPIO (1<<4)
+#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC (1<<5)
+#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_MASK (1<<5)
+#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_SHIFT (5)
+#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_ALT (0<<5)
+#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_GPIO (1<<5)
+#define CFG_REGS_MODE_AP_PIN_CAM2_HREF (1<<6)
+#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_MASK (1<<6)
+#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_SHIFT (6)
+#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_ALT (0<<6)
+#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_GPIO (1<<6)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_MASK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_SHIFT (7)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_ALT (0<<7)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_GPIO (1<<7)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0 (1<<8)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_MASK (1<<8)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_SHIFT (8)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_ALT (0<<8)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_GPIO (1<<8)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1 (1<<9)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_MASK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_SHIFT (9)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_ALT (0<<9)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_GPIO (1<<9)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2 (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_MASK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_SHIFT (10)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_ALT (0<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_GPIO (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3 (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_MASK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_SHIFT (11)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_ALT (0<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_GPIO (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4 (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_MASK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_SHIFT (12)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_ALT (0<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_GPIO (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5 (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_MASK (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_SHIFT (13)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_ALT (0<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_GPIO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6 (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_MASK (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_SHIFT (14)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_ALT (0<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_GPIO (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7 (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_MASK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_SHIFT (15)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_ALT (0<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_GPIO (1<<15)
+#define CFG_REGS_AP_GPIO_E_MODE(n) (((n)&0xFFFF)<<0)
+#define CFG_REGS_AP_GPIO_E_MODE_MASK (0xFFFF<<0)
+#define CFG_REGS_AP_GPIO_E_MODE_SHIFT (0)
+
+
+
+
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8810h.h b/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8810h.h
new file mode 100644
index 0000000000..e659daf337
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8810h.h
@@ -0,0 +1,1302 @@
+//==============================================================================
+//
+//            Copyright (C) 2012-2014, RDA Microelectronics.
+//                            All Rights Reserved
+//
+//      This source code is the property of RDA Microelectronics and is
+//      confidential.  Any  modification, distribution,  reproduction or
+//      exploitation  of  any content of this file is totally forbidden,
+//      except  with the  written permission  of   RDA Microelectronics.
+//
+//==============================================================================
+//
+//    THIS FILE WAS GENERATED FROM ITS CORRESPONDING XML VERSION WITH COOLXML.
+//
+//                       !!! PLEASE DO NOT EDIT !!!
+//
+//  $HeadURL$
+//  $Author$
+//  $Date$
+//  $Revision$
+//
+//==============================================================================
+//
+/// @file
+//
+//==============================================================================
+
+#ifndef _CFG_REGS_H_
+#define _CFG_REGS_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+#ifdef CT_ASM
+#error "You are trying to use in an assembly code the normal H description of 'cfg_regs'."
+#endif
+
+
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+#define PROD_ID                                 (0X810E)
+
+// ============================================================================
+// BB_GPIO_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// BB GPIO Map
+    BB_PIN_NONE_0                               = 0x00000000,
+    BB_PIN_1                                    = 0x00000001,
+    BB_PIN_2                                    = 0x00000002,
+    BB_PIN_3                                    = 0x00000003,
+    BB_PIN_4                                    = 0x00000004,
+    BB_PIN_5                                    = 0x00000005,
+    BB_PIN_UART1_RXD                            = 0x00000006,
+    BB_PIN_UART2_RXD                            = 0x00000007,
+    BB_PIN_UART2_TXD                            = 0x00000008,
+    BB_PIN_SSD1_CLK                             = 0x00000009,
+    BB_PIN_SSD1_CMD                             = 0x0000000A,
+    BB_PIN_SDAT1_0                              = 0x0000000B,
+    BB_PIN_SDAT1_1                              = 0x0000000C,
+    BB_PIN_SDAT1_2                              = 0x0000000D,
+    BB_PIN_SDAT1_3                              = 0x0000000E,
+    BB_PIN_SSD2_CLK                             = 0x0000000F,
+    BB_PIN_SSD2_CMD                             = 0x00000010,
+    BB_PIN_SDAT2_0                              = 0x00000011,
+    BB_PIN_SDAT2_1                              = 0x00000012,
+    BB_PIN_SDAT2_2                              = 0x00000013,
+    BB_PIN_SDAT2_3                              = 0x00000014,
+    BB_PIN_SPI1_CLK                             = 0x00000015,
+    BB_PIN_SPI1_CS_0                            = 0x00000016,
+    BB_PIN_SPI1_DIO                             = 0x00000017,
+    BB_PIN_SPI1_DI                              = 0x00000018,
+    BB_PIN_SIM2_RST                             = 0x00000019,
+    BB_PIN_SIM2_CLK                             = 0x0000001A,
+    BB_PIN_SIM2_DIO                             = 0x0000001B,
+    BB_PIN_SIM3_RST                             = 0x0000001C,
+    BB_PIN_SIM3_CLK                             = 0x0000001D,
+    BB_PIN_SIM3_DIO                             = 0x0000001E
+} BB_GPIO_MAPPING_T;
+
+#define BB_GPIO_NB                              (31)
+
+// ============================================================================
+// AP_GPIO_A_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP GPIO A Map
+    AP_PIN_I2C2_SCL                             = 0x00000000,
+    AP_PIN_I2C2_SDA                             = 0x00000001,
+    AP_PIN_SPI2_CLK                             = 0x00000002,
+    AP_PIN_SPI2_DIO                             = 0x00000003,
+    AP_PIN_SPI2_DI                              = 0x00000004,
+    AP_PIN_SPI2_CS_0                            = 0x00000005,
+    AP_PIN_SPI2_CS_1                            = 0x00000006,
+    AP_PIN_KEYIN_4                              = 0x00000007,
+    AP_PIN_CLK_OUT                              = 0x00000008,
+    AP_PIN_I2S_BCK                              = 0x00000009,
+    AP_PIN_I2S_LRCK                             = 0x0000000A,
+    AP_PIN_I2S_DI_0                             = 0x0000000B,
+    AP_PIN_I2S_DI_1                             = 0x0000000C,
+    AP_PIN_I2S_DO                               = 0x0000000D,
+    AP_PIN_UART1_TXD                            = 0x0000000E,
+    AP_PIN_UART1_CTS                            = 0x0000000F,
+    AP_PIN_UART1_RTS                            = 0x00000010,
+    AP_PIN_SPI1_CS_1                            = 0x00000011,
+    AP_PIN_LCD_DATA_6                           = 0x00000012,
+    AP_PIN_LCD_DATA_7                           = 0x00000013,
+    AP_PIN_LCD_WR                               = 0x00000014,
+    AP_PIN_LCD_RS                               = 0x00000015,
+    AP_PIN_LCD_RD                               = 0x00000016,
+    AP_PIN_LCD_FMARK                            = 0x00000017,
+    AP_PIN_LCD_DATA_8                           = 0x00000018,
+    AP_PIN_LCD_DATA_9                           = 0x00000019,
+    AP_PIN_LCD_DATA_10                          = 0x0000001A,
+    AP_PIN_LCD_DATA_11                          = 0x0000001B,
+    AP_PIN_LCD_DATA_12                          = 0x0000001C,
+    AP_PIN_LCD_DATA_13                          = 0x0000001D,
+    AP_PIN_LCD_DATA_14                          = 0x0000001E,
+    AP_PIN_LCD_DATA_15                          = 0x0000001F
+} AP_GPIO_A_MAPPING_T;
+
+#define AP_GPIO_A_NB                            (32)
+
+// ============================================================================
+// AP_GPIO_B_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP GPIO B Map
+    AP_PIN_KEYIN_0                              = 0x00000000,
+    AP_PIN_KEYIN_1                              = 0x00000001,
+    AP_PIN_KEYIN_2                              = 0x00000002,
+    AP_PIN_KEYOUT_0                             = 0x00000003,
+    AP_PIN_KEYOUT_1                             = 0x00000004,
+    AP_PIN_KEYOUT_2                             = 0x00000005,
+    AP_PIN_I2C3_SCL                             = 0x00000006,
+    AP_PIN_I2C3_SDA                             = 0x00000007,
+    AP_PIN_UART2_CTS                            = 0x00000008,
+    AP_PIN_UART2_RTS                            = 0x00000009,
+    AP_PIN_CAM_RST                              = 0x0000000A,
+    AP_PIN_CAM_PDN                              = 0x0000000B,
+    AP_PIN_CAM_CLK                              = 0x0000000C,
+    AP_PIN_CAM_VSYNC                            = 0x0000000D,
+    AP_PIN_CAM_HREF                             = 0x0000000E,
+    AP_PIN_CAM_PCLK                             = 0x0000000F,
+    AP_PIN_CAM_DATA_0                           = 0x00000010,
+    AP_PIN_CAM_DATA_1                           = 0x00000011,
+    AP_PIN_CAM_DATA_2                           = 0x00000012,
+    AP_PIN_CAM_DATA_3                           = 0x00000013,
+    AP_PIN_CAM_DATA_4                           = 0x00000014,
+    AP_PIN_CAM_DATA_5                           = 0x00000015,
+    AP_PIN_CAM_DATA_6                           = 0x00000016,
+    AP_PIN_CAM_DATA_7                           = 0x00000017,
+    AP_PIN_M_SPI_CS_0                           = 0x00000018,
+    AP_PIN_NFCLE                                = 0x00000019,
+    AP_PIN_NFWEN                                = 0x0000001A,
+    AP_PIN_NFWPN                                = 0x0000001B,
+    AP_PIN_NFREN                                = 0x0000001C,
+    AP_PIN_NFRB                                 = 0x0000001D,
+    AP_PIN_I2C1_SCL                             = 0x0000001E,
+    AP_PIN_I2C1_SDA                             = 0x0000001F
+} AP_GPIO_B_MAPPING_T;
+
+#define AP_GPIO_B_NB                            (32)
+
+// ============================================================================
+// AP_GPIO_D_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP GPIO D Map
+    AP_PIN_UART3_RXD                            = 0x00000000,
+    AP_PIN_UART3_TXD                            = 0x00000001,
+    AP_PIN_UART3_CTS                            = 0x00000002,
+    AP_PIN_UART3_RTS                            = 0x00000003,
+    AP_PIN_NFDQS                                = 0x00000004,
+    AP_PIN_VOLUME_DN                            = 0x00000005,
+    AP_PIN_VOLUME_UP                            = 0x00000006,
+    AP_PIN_PLUGIN                               = 0x00000007,
+    AP_PIN_NFCEN_1                              = 0x00000008,
+    AP_PIN_NFCEN_2                              = 0x00000009,
+    AP_PIN_NFCEN_3                              = 0x0000000A,
+    AP_PIN_I2S2_BCK                             = 0x0000000B,
+    AP_PIN_I2S2_LRCK                            = 0x0000000C,
+    AP_PIN_I2S2_DI_0                            = 0x0000000D,
+    AP_PIN_I2S2_DI_1                            = 0x0000000E,
+    AP_PIN_I2S2_DO                              = 0x0000000F
+} AP_GPIO_D_MAPPING_T;
+
+#define AP_GPIO_D_NB                            (16)
+
+// ============================================================================
+// AP_GPIO_E_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP GPIO E Map
+    AP_PIN_I2CBB_SCL                            = 0x00000000,
+    AP_PIN_I2CBB_SDA                            = 0x00000001,
+    AP_PIN_CAM2_RST                             = 0x00000002,
+    AP_PIN_CAM2_PDN                             = 0x00000003,
+    AP_PIN_CAM2_CLK                             = 0x00000004,
+    AP_PIN_CAM2_VSYNC                           = 0x00000005,
+    AP_PIN_CAM2_HREF                            = 0x00000006,
+    AP_PIN_CAM2_PCLK                            = 0x00000007,
+    AP_PIN_CAM2_DATA_0                          = 0x00000008,
+    AP_PIN_CAM2_DATA_1                          = 0x00000009,
+    AP_PIN_CAM2_DATA_2                          = 0x0000000A,
+    AP_PIN_CAM2_DATA_3                          = 0x0000000B,
+    AP_PIN_CAM2_DATA_4                          = 0x0000000C,
+    AP_PIN_CAM2_DATA_5                          = 0x0000000D,
+    AP_PIN_CAM2_DATA_6                          = 0x0000000E,
+    AP_PIN_CAM2_DATA_7                          = 0x0000000F
+} AP_GPIO_E_MAPPING_T;
+
+#define AP_GPIO_E_NB                            (16)
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+// ============================================================================
+// CFG_REGS_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+#define REG_CONFIG_REGS_BASE       0x01A09000
+
+typedef volatile struct
+{
+    REG32                          CHIP_ID;                      //0x00000000
+    /// This register contain the synthesis date and version
+    REG32                          Build_Version;                //0x00000004
+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+    /// bit n to '0' selects Alt.
+    REG32                          BB_GPIO_Mode;                 //0x00000008
+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+    /// bit n to '0' selects Alt.
+    REG32                          AP_GPIO_A_Mode;               //0x0000000C
+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+    /// bit n to '0' selects Alt.
+    REG32                          AP_GPIO_B_Mode;               //0x00000010
+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+    /// bit n to '0' selects Alt.
+    REG32                          AP_GPIO_D_Mode;               //0x00000014
+    REG32                          Alt_mux_select;               //0x00000018
+    REG32                          IO_Drive1_Select;             //0x0000001C
+    REG32                          IO_Drive2_Select;             //0x00000020
+    REG32                          RAM_DRIVE;                    //0x00000024
+    REG32                          H2X_AP_Offset;                //0x00000028
+    REG32                          H2X_DDR_Offset;               //0x0000002C
+    REG32                          audio_pd_set;                 //0x00000030
+    REG32                          audio_pd_clr;                 //0x00000034
+    REG32                          audio_sel_cfg;                //0x00000038
+    REG32                          audio_mic_cfg;                //0x0000003C
+    REG32                          audio_spk_cfg;                //0x00000040
+    REG32                          audio_rcv_gain;               //0x00000044
+    REG32                          audio_head_gain;              //0x00000048
+    REG32                          TSC_DATA;                     //0x0000004C
+    REG32                          GPADC_DATA_CH[8];             //0x00000050
+    REG32                          Alt_mux_select2;              //0x00000070
+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+    /// bit n to '0' selects Alt.
+    REG32                          AP_GPIO_E_Mode;               //0x00000074
+} HWP_CFG_REGS_T;
+
+#define hwp_configRegs             ((HWP_CFG_REGS_T*) (RDA_CFG_REGS_BASE))
+
+
+//CHIP_ID
+#define CFG_REGS_METAL_ID(n)       (((n)&0xFFF)<<0)
+#define CFG_REGS_METAL_ID_MASK     (0xFFF<<0)
+#define CFG_REGS_METAL_ID_SHIFT    (0)
+#define CFG_REGS_BOND_ID(n)        (((n)&7)<<12)
+#define CFG_REGS_BOND_ID_MASK      (7<<12)
+#define CFG_REGS_BOND_ID_SHIFT     (12)
+#define CFG_REGS_PROD_ID(n)        (((n)&0xFFFF)<<16)
+#define CFG_REGS_PROD_ID_MASK      (0xFFFF<<16)
+#define CFG_REGS_PROD_ID_SHIFT     (16)
+
+//Build_Version
+#define CFG_REGS_MAJOR(n)          (((n)&15)<<28)
+#define CFG_REGS_YEAR(n)           (((n)&15)<<24)
+#define CFG_REGS_MONTH(n)          (((n)&0xFF)<<16)
+#define CFG_REGS_DAY(n)            (((n)&0xFF)<<8)
+#define CFG_REGS_BUILD_STYLE_FPGA  (0<<4)
+#define CFG_REGS_BUILD_STYLE_CHIP  (1<<4)
+#define CFG_REGS_BUILD_STYLE_FPGA_USB (2<<4)
+#define CFG_REGS_BUILD_STYLE_FPGA_GSM (3<<4)
+#define CFG_REGS_BUILD_REVISION(n) (((n)&15)<<0)
+
+//BB_GPIO_Mode
+#define CFG_REGS_MODE_BB_PIN_NONE_0 (1<<0)
+#define CFG_REGS_MODE_BB_PIN_NONE_0_MASK (1<<0)
+#define CFG_REGS_MODE_BB_PIN_NONE_0_SHIFT (0)
+#define CFG_REGS_MODE_BB_PIN_NONE_0_ALT (0<<0)
+#define CFG_REGS_MODE_BB_PIN_NONE_0_GPIO (1<<0)
+#define CFG_REGS_MODE_BB_PIN_1     (1<<1)
+#define CFG_REGS_MODE_BB_PIN_1_MASK (1<<1)
+#define CFG_REGS_MODE_BB_PIN_1_SHIFT (1)
+#define CFG_REGS_MODE_BB_PIN_1_ALT (0<<1)
+#define CFG_REGS_MODE_BB_PIN_1_GPIO (1<<1)
+#define CFG_REGS_MODE_BB_PIN_2     (1<<2)
+#define CFG_REGS_MODE_BB_PIN_2_MASK (1<<2)
+#define CFG_REGS_MODE_BB_PIN_2_SHIFT (2)
+#define CFG_REGS_MODE_BB_PIN_2_ALT (0<<2)
+#define CFG_REGS_MODE_BB_PIN_2_GPIO (1<<2)
+#define CFG_REGS_MODE_BB_PIN_3     (1<<3)
+#define CFG_REGS_MODE_BB_PIN_3_MASK (1<<3)
+#define CFG_REGS_MODE_BB_PIN_3_SHIFT (3)
+#define CFG_REGS_MODE_BB_PIN_3_ALT (0<<3)
+#define CFG_REGS_MODE_BB_PIN_3_GPIO (1<<3)
+#define CFG_REGS_MODE_BB_PIN_4     (1<<4)
+#define CFG_REGS_MODE_BB_PIN_4_MASK (1<<4)
+#define CFG_REGS_MODE_BB_PIN_4_SHIFT (4)
+#define CFG_REGS_MODE_BB_PIN_4_ALT (0<<4)
+#define CFG_REGS_MODE_BB_PIN_4_GPIO (1<<4)
+#define CFG_REGS_MODE_BB_PIN_5     (1<<5)
+#define CFG_REGS_MODE_BB_PIN_5_MASK (1<<5)
+#define CFG_REGS_MODE_BB_PIN_5_SHIFT (5)
+#define CFG_REGS_MODE_BB_PIN_5_ALT (0<<5)
+#define CFG_REGS_MODE_BB_PIN_5_GPIO (1<<5)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD (1<<6)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_MASK (1<<6)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_SHIFT (6)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_ALT (0<<6)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_GPIO (1<<6)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD (1<<7)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_MASK (1<<7)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_SHIFT (7)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_ALT (0<<7)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_GPIO (1<<7)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD (1<<8)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_MASK (1<<8)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_SHIFT (8)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_ALT (0<<8)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_GPIO (1<<8)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK (1<<9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_MASK (1<<9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_SHIFT (9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_ALT (0<<9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_GPIO (1<<9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD (1<<10)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_MASK (1<<10)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_SHIFT (10)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_ALT (0<<10)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_GPIO (1<<10)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0 (1<<11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_MASK (1<<11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_SHIFT (11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_ALT (0<<11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_GPIO (1<<11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1 (1<<12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_MASK (1<<12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_SHIFT (12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_ALT (0<<12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_GPIO (1<<12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2 (1<<13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_MASK (1<<13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_SHIFT (13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_ALT (0<<13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_GPIO (1<<13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3 (1<<14)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_MASK (1<<14)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_SHIFT (14)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_ALT (0<<14)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_GPIO (1<<14)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK (1<<15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_MASK (1<<15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_SHIFT (15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_ALT (0<<15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_GPIO (1<<15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD (1<<16)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_MASK (1<<16)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_SHIFT (16)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_ALT (0<<16)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_GPIO (1<<16)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0 (1<<17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_MASK (1<<17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_SHIFT (17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_ALT (0<<17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_GPIO (1<<17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1 (1<<18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_MASK (1<<18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_SHIFT (18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_ALT (0<<18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_GPIO (1<<18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2 (1<<19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_MASK (1<<19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_SHIFT (19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_ALT (0<<19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_GPIO (1<<19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3 (1<<20)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_MASK (1<<20)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_SHIFT (20)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_ALT (0<<20)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_GPIO (1<<20)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK (1<<21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_MASK (1<<21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_SHIFT (21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_ALT (0<<21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_GPIO (1<<21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0 (1<<22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_MASK (1<<22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_SHIFT (22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_ALT (0<<22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_GPIO (1<<22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO (1<<23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_MASK (1<<23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_SHIFT (23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_ALT (0<<23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_GPIO (1<<23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI (1<<24)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_MASK (1<<24)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_SHIFT (24)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_ALT (0<<24)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_GPIO (1<<24)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST (1<<25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_MASK (1<<25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_SHIFT (25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_ALT (0<<25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_GPIO (1<<25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK (1<<26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_MASK (1<<26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_SHIFT (26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_ALT (0<<26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_GPIO (1<<26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO (1<<27)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_MASK (1<<27)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_SHIFT (27)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_ALT (0<<27)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_GPIO (1<<27)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST (1<<28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_MASK (1<<28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_SHIFT (28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_ALT (0<<28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_GPIO (1<<28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK (1<<29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_MASK (1<<29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_SHIFT (29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_ALT (0<<29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_GPIO (1<<29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO (1<<30)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_MASK (1<<30)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_SHIFT (30)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_ALT (0<<30)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_GPIO (1<<30)
+#define CFG_REGS_BB_GPIO_MODE(n)   (((n)&0x7FFFFFFF)<<0)
+#define CFG_REGS_BB_GPIO_MODE_MASK (0x7FFFFFFF<<0)
+#define CFG_REGS_BB_GPIO_MODE_SHIFT (0)
+
+//AP_GPIO_A_Mode
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_MASK (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_SHIFT (0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_ALT (0<<0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_GPIO (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA (1<<1)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_MASK (1<<1)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_SHIFT (1)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_ALT (0<<1)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_GPIO (1<<1)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_MASK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_SHIFT (2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_ALT (0<<2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_GPIO (1<<2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_MASK (1<<3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_SHIFT (3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_ALT (0<<3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_GPIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI (1<<4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_MASK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_SHIFT (4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_ALT (0<<4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_GPIO (1<<4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0 (1<<5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_MASK (1<<5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_SHIFT (5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_ALT (0<<5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_GPIO (1<<5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1 (1<<6)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_MASK (1<<6)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_SHIFT (6)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_ALT (0<<6)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_GPIO (1<<6)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4 (1<<7)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_MASK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_SHIFT (7)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_ALT (0<<7)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_GPIO (1<<7)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT (1<<8)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_MASK (1<<8)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_SHIFT (8)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_ALT (0<<8)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_GPIO (1<<8)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_MASK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_SHIFT (9)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_ALT (0<<9)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_GPIO (1<<9)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_MASK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_SHIFT (10)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_ALT (0<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_GPIO (1<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0 (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_MASK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_SHIFT (11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_ALT (0<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_GPIO (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1 (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_MASK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_SHIFT (12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_ALT (0<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_GPIO (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO_MASK (1<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO_SHIFT (13)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO_ALT (0<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO_GPIO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD (1<<14)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_MASK (1<<14)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_SHIFT (14)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_ALT (0<<14)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_GPIO (1<<14)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS (1<<15)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_MASK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_SHIFT (15)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_ALT (0<<15)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_GPIO (1<<15)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS (1<<16)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_MASK (1<<16)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_SHIFT (16)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_ALT (0<<16)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_GPIO (1<<16)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1 (1<<17)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_MASK (1<<17)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_SHIFT (17)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_ALT (0<<17)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_GPIO (1<<17)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6 (1<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_MASK (1<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_SHIFT (18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_ALT (0<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_GPIO (1<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7 (1<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_MASK (1<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_SHIFT (19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_ALT (0<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_GPIO (1<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR (1<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR_MASK (1<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR_SHIFT (20)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR_ALT (0<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR_GPIO (1<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS (1<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS_MASK (1<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS_SHIFT (21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS_ALT (0<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS_GPIO (1<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD (1<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD_MASK (1<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD_SHIFT (22)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD_ALT (0<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD_GPIO (1<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK (1<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_MASK (1<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_SHIFT (23)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_ALT (0<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_GPIO (1<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8 (1<<24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_MASK (1<<24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_SHIFT (24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_ALT (0<<24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_GPIO (1<<24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9 (1<<25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_MASK (1<<25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_SHIFT (25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_ALT (0<<25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_GPIO (1<<25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10 (1<<26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_MASK (1<<26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_SHIFT (26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_ALT (0<<26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_GPIO (1<<26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11 (1<<27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_MASK (1<<27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_SHIFT (27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_ALT (0<<27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_GPIO (1<<27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12 (1<<28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_MASK (1<<28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_SHIFT (28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_ALT (0<<28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_GPIO (1<<28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13 (1<<29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_MASK (1<<29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_SHIFT (29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_ALT (0<<29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_GPIO (1<<29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14 (1<<30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_MASK (1<<30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_SHIFT (30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_ALT (0<<30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_GPIO (1<<30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15 (1<<31)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_MASK (1<<31)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_SHIFT (31)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_ALT (0<<31)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_GPIO (1<<31)
+#define CFG_REGS_AP_GPIO_A_MODE(n) (((n)&0xFFFFFFFF)<<0)
+#define CFG_REGS_AP_GPIO_A_MODE_MASK (0xFFFFFFFF<<0)
+#define CFG_REGS_AP_GPIO_A_MODE_SHIFT (0)
+
+//AP_GPIO_B_Mode
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0 (1<<0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_MASK (1<<0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_SHIFT (0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_ALT (0<<0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_GPIO (1<<0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1 (1<<1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_MASK (1<<1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_SHIFT (1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_ALT (0<<1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_GPIO (1<<1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2 (1<<2)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_MASK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_SHIFT (2)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_ALT (0<<2)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_GPIO (1<<2)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0 (1<<3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_MASK (1<<3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_SHIFT (3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_ALT (0<<3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_GPIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1 (1<<4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_MASK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_SHIFT (4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_ALT (0<<4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_GPIO (1<<4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2 (1<<5)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_MASK (1<<5)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_SHIFT (5)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_ALT (0<<5)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_GPIO (1<<5)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL (1<<6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_MASK (1<<6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_SHIFT (6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_ALT (0<<6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_GPIO (1<<6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA (1<<7)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_MASK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_SHIFT (7)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_ALT (0<<7)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_GPIO (1<<7)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS (1<<8)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_MASK (1<<8)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_SHIFT (8)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_ALT (0<<8)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_GPIO (1<<8)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS (1<<9)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_MASK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_SHIFT (9)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_ALT (0<<9)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_GPIO (1<<9)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST_MASK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST_SHIFT (10)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST_ALT (0<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST_GPIO (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_MASK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_SHIFT (11)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_ALT (0<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_GPIO (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_MASK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_SHIFT (12)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_ALT (0<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_GPIO (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_MASK (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_SHIFT (13)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_ALT (0<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_GPIO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_MASK (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_SHIFT (14)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_ALT (0<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_GPIO (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_MASK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_SHIFT (15)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_ALT (0<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_GPIO (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0 (1<<16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_MASK (1<<16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_SHIFT (16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_ALT (0<<16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_GPIO (1<<16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1 (1<<17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_MASK (1<<17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_SHIFT (17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_ALT (0<<17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_GPIO (1<<17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2 (1<<18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_MASK (1<<18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_SHIFT (18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_ALT (0<<18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_GPIO (1<<18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3 (1<<19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_MASK (1<<19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_SHIFT (19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_ALT (0<<19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_GPIO (1<<19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4 (1<<20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_MASK (1<<20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_SHIFT (20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_ALT (0<<20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_GPIO (1<<20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5 (1<<21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_MASK (1<<21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_SHIFT (21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_ALT (0<<21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_GPIO (1<<21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6 (1<<22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_MASK (1<<22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_SHIFT (22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_ALT (0<<22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_GPIO (1<<22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7 (1<<23)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_MASK (1<<23)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_SHIFT (23)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_ALT (0<<23)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_GPIO (1<<23)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0 (1<<24)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_MASK (1<<24)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_SHIFT (24)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_ALT (0<<24)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_GPIO (1<<24)
+#define CFG_REGS_MODE_AP_PIN_NFCLE (1<<25)
+#define CFG_REGS_MODE_AP_PIN_NFCLE_MASK (1<<25)
+#define CFG_REGS_MODE_AP_PIN_NFCLE_SHIFT (25)
+#define CFG_REGS_MODE_AP_PIN_NFCLE_ALT (0<<25)
+#define CFG_REGS_MODE_AP_PIN_NFCLE_GPIO (1<<25)
+#define CFG_REGS_MODE_AP_PIN_NFWEN (1<<26)
+#define CFG_REGS_MODE_AP_PIN_NFWEN_MASK (1<<26)
+#define CFG_REGS_MODE_AP_PIN_NFWEN_SHIFT (26)
+#define CFG_REGS_MODE_AP_PIN_NFWEN_ALT (0<<26)
+#define CFG_REGS_MODE_AP_PIN_NFWEN_GPIO (1<<26)
+#define CFG_REGS_MODE_AP_PIN_NFWPN (1<<27)
+#define CFG_REGS_MODE_AP_PIN_NFWPN_MASK (1<<27)
+#define CFG_REGS_MODE_AP_PIN_NFWPN_SHIFT (27)
+#define CFG_REGS_MODE_AP_PIN_NFWPN_ALT (0<<27)
+#define CFG_REGS_MODE_AP_PIN_NFWPN_GPIO (1<<27)
+#define CFG_REGS_MODE_AP_PIN_NFREN (1<<28)
+#define CFG_REGS_MODE_AP_PIN_NFREN_MASK (1<<28)
+#define CFG_REGS_MODE_AP_PIN_NFREN_SHIFT (28)
+#define CFG_REGS_MODE_AP_PIN_NFREN_ALT (0<<28)
+#define CFG_REGS_MODE_AP_PIN_NFREN_GPIO (1<<28)
+#define CFG_REGS_MODE_AP_PIN_NFRB  (1<<29)
+#define CFG_REGS_MODE_AP_PIN_NFRB_MASK (1<<29)
+#define CFG_REGS_MODE_AP_PIN_NFRB_SHIFT (29)
+#define CFG_REGS_MODE_AP_PIN_NFRB_ALT (0<<29)
+#define CFG_REGS_MODE_AP_PIN_NFRB_GPIO (1<<29)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL (1<<30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_MASK (1<<30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_SHIFT (30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_ALT (0<<30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_GPIO (1<<30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA (1<<31)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_MASK (1<<31)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_SHIFT (31)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_ALT (0<<31)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_GPIO (1<<31)
+#define CFG_REGS_AP_GPIO_B_MODE(n) (((n)&0xFFFFFFFF)<<0)
+#define CFG_REGS_AP_GPIO_B_MODE_MASK (0xFFFFFFFF<<0)
+#define CFG_REGS_AP_GPIO_B_MODE_SHIFT (0)
+
+//AP_GPIO_D_Mode
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD (1<<0)
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_MASK (1<<0)
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_SHIFT (0)
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_ALT (0<<0)
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_GPIO (1<<0)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD (1<<1)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_MASK (1<<1)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_SHIFT (1)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_ALT (0<<1)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_GPIO (1<<1)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS (1<<2)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_MASK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_SHIFT (2)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_ALT (0<<2)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_GPIO (1<<2)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS (1<<3)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_MASK (1<<3)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_SHIFT (3)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_ALT (0<<3)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_GPIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_NFDQS (1<<4)
+#define CFG_REGS_MODE_AP_PIN_NFDQS_MASK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_NFDQS_SHIFT (4)
+#define CFG_REGS_MODE_AP_PIN_NFDQS_ALT (0<<4)
+#define CFG_REGS_MODE_AP_PIN_NFDQS_GPIO (1<<4)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN (1<<5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_MASK (1<<5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_SHIFT (5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_ALT (0<<5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_GPIO (1<<5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP (1<<6)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_MASK (1<<6)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_SHIFT (6)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_ALT (0<<6)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_GPIO (1<<6)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN (1<<7)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN_MASK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN_SHIFT (7)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN_ALT (0<<7)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN_GPIO (1<<7)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1 (1<<8)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1_MASK (1<<8)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1_SHIFT (8)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1_ALT (0<<8)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1_GPIO (1<<8)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2 (1<<9)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2_MASK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2_SHIFT (9)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2_ALT (0<<9)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2_GPIO (1<<9)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3 (1<<10)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3_MASK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3_SHIFT (10)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3_ALT (0<<10)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3_GPIO (1<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_MASK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_SHIFT (11)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_ALT (0<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_GPIO (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_MASK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_SHIFT (12)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_ALT (0<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_GPIO (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0 (1<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_MASK (1<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_SHIFT (13)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_ALT (0<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_GPIO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1 (1<<14)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_MASK (1<<14)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_SHIFT (14)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_ALT (0<<14)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_GPIO (1<<14)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO (1<<15)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO_MASK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO_SHIFT (15)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO_ALT (0<<15)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO_GPIO (1<<15)
+#define CFG_REGS_AP_GPIO_D_MODE(n) (((n)&0xFFFF)<<0)
+#define CFG_REGS_AP_GPIO_D_MODE_MASK (0xFFFF<<0)
+#define CFG_REGS_AP_GPIO_D_MODE_SHIFT (0)
+
+//Alt_mux_select
+#define CFG_REGS_LCD_MODE_MASK     (3<<0)
+#define CFG_REGS_LCD_MODE_PARALLEL_16BIT (0<<0)
+#define CFG_REGS_LCD_MODE_DSI      (1<<0)
+#define CFG_REGS_LCD_MODE_RGB_24BIT (2<<0)
+#define CFG_REGS_LCD_MODE_RGB_16BIT (3<<0)
+#define CFG_REGS_SPI_LCD_MASK      (1<<2)
+#define CFG_REGS_SPI_LCD_NONE      (0<<2)
+#define CFG_REGS_SPI_LCD_SPI_LCD   (1<<2)
+#define CFG_REGS_CAM_I2C2_MASK     (1<<3)
+#define CFG_REGS_CAM_I2C2_CAM      (0<<3)
+#define CFG_REGS_CAM_I2C2_I2C2     (1<<3)
+#define CFG_REGS_CSI2_MASK         (3<<4)
+#define CFG_REGS_CSI2_PARALLEL_CAM (0<<4)
+#define CFG_REGS_CSI2_CSI2         (1<<4)
+#define CFG_REGS_CSI2_SPI_CAM      (2<<4)
+#define CFG_REGS_UART2_MASK        (1<<6)
+#define CFG_REGS_UART2_HOST_UART   (0<<6)
+#define CFG_REGS_UART2_UART2       (1<<6)
+#define CFG_REGS_UART1_8LINE_MASK  (1<<7)
+#define CFG_REGS_UART1_8LINE_UART2 (0<<7)
+#define CFG_REGS_UART1_8LINE_UART1_8_LINE (1<<7)
+#define CFG_REGS_DAI_MASK          (3<<8)
+#define CFG_REGS_DAI_I2S           (0<<8)
+#define CFG_REGS_DAI_DAI           (1<<8)
+#define CFG_REGS_DAI_DAI_SIMPLE    (2<<8)
+#define CFG_REGS_KEYIN_3_MASK      (1<<10)
+#define CFG_REGS_KEYIN_3_SPI2_CS_1 (0<<10)
+#define CFG_REGS_KEYIN_3_KEYIN_3   (1<<10)
+#define CFG_REGS_LPSCO_1_MASK      (1<<11)
+#define CFG_REGS_LPSCO_1_KEYIN_4   (0<<11)
+#define CFG_REGS_LPSCO_1_LPSCO_1   (1<<11)
+#define CFG_REGS_SPI1_CS_2_MASK    (1<<12)
+#define CFG_REGS_SPI1_CS_2_KEYIN_1 (0<<12)
+#define CFG_REGS_SPI1_CS_2_SPI1_CS_2 (1<<12)
+#define CFG_REGS_I2S_DI_2_MASK     (1<<13)
+#define CFG_REGS_I2S_DI_2_KEYIN_2  (0<<13)
+#define CFG_REGS_I2S_DI_2_I2S_DI_2 (1<<13)
+#define CFG_REGS_TCO_0_MASK        (1<<14)
+#define CFG_REGS_TCO_0_KEYOUT_0    (0<<14)
+#define CFG_REGS_TCO_0_TCO_0       (1<<14)
+#define CFG_REGS_TCO_1_MASK        (1<<15)
+#define CFG_REGS_TCO_1_KEYOUT_1    (0<<15)
+#define CFG_REGS_TCO_1_TCO_1       (1<<15)
+#define CFG_REGS_TCO_2_MASK        (1<<16)
+#define CFG_REGS_TCO_2_KEYOUT_2    (0<<16)
+#define CFG_REGS_TCO_2_TCO_2       (1<<16)
+#define CFG_REGS_KEYOUT_3_4_MASK   (1<<17)
+#define CFG_REGS_KEYOUT_3_4_I2C3   (0<<17)
+#define CFG_REGS_KEYOUT_3_4_KEYOUT_3_4 (1<<17)
+#define CFG_REGS_KEYOUT_6_MASK     (1<<18)
+#define CFG_REGS_KEYOUT_6_UART2_RTS (0<<18)
+#define CFG_REGS_KEYOUT_6_KEYOUT_6 (1<<18)
+#define CFG_REGS_KEYOUT_7_MASK     (1<<19)
+#define CFG_REGS_KEYOUT_7_UART1_RTS (0<<19)
+#define CFG_REGS_KEYOUT_7_KEYOUT_7 (1<<19)
+#define CFG_REGS_GPO_0_MASK        (3<<20)
+#define CFG_REGS_GPO_0_GPO_0       (0<<20)
+#define CFG_REGS_GPO_0_PWT         (1<<20)
+#define CFG_REGS_GPO_0_KEYIN_5     (2<<20)
+#define CFG_REGS_GPO_1_MASK        (3<<22)
+#define CFG_REGS_GPO_1_GPO_1       (0<<22)
+#define CFG_REGS_GPO_1_LPG         (1<<22)
+#define CFG_REGS_GPO_1_KEYOUT_5    (2<<22)
+#define CFG_REGS_GPO_2_MASK        (3<<24)
+#define CFG_REGS_GPO_2_GPO_2       (0<<24)
+#define CFG_REGS_GPO_2_PWL_1       (1<<24)
+#define CFG_REGS_GPO_2_CLK_32K     (2<<24)
+#define CFG_REGS_GPO_3_MASK        (1<<26)
+#define CFG_REGS_GPO_3_LCD_CS_1    (0<<26)
+#define CFG_REGS_GPO_3_GPO_3       (1<<26)
+#define CFG_REGS_GPO_4_MASK        (1<<27)
+#define CFG_REGS_GPO_4_LCD_CS_0    (0<<27)
+#define CFG_REGS_GPO_4_GPO_4       (1<<27)
+#define CFG_REGS_CLK_OUT_MASK      (1<<28)
+#define CFG_REGS_CLK_OUT_HST_CLK   (0<<28)
+#define CFG_REGS_CLK_OUT_CLK_OUT   (1<<28)
+#define CFG_REGS_DEBUG_MASK        (1<<29)
+#define CFG_REGS_DEBUG_NONE        (0<<29)
+#define CFG_REGS_DEBUG_DEBUG_MONITOR (1<<29)
+#define CFG_REGS_AP_SPI1_MASK      (1<<30)
+#define CFG_REGS_AP_SPI1_BB_SPI1   (0<<30)
+#define CFG_REGS_AP_SPI1_AP_SPI1   (1<<30)
+#define CFG_REGS_RGB_CAM_MASK      (1<<31)
+#define CFG_REGS_RGB_CAM_DISABLE   (0<<31)
+#define CFG_REGS_RGB_CAM_ENABLE    (1<<31)
+
+//IO_Drive1_Select
+#define CFG_REGS_DDR_DRIVE_MASK    (7<<0)
+#define CFG_REGS_DDR_DRIVE_FAST_AND_MOST_WEAK (7<<0)
+#define CFG_REGS_DDR_DRIVE_FAST_AND_WEAK (6<<0)
+#define CFG_REGS_DDR_DRIVE_FAST_AND_STRONG (5<<0)
+#define CFG_REGS_DDR_DRIVE_FAST_AND_MOST_STRONG (4<<0)
+#define CFG_REGS_DDR_DRIVE_SLOW_AND_MOST_WEAK (3<<0)
+#define CFG_REGS_DDR_DRIVE_SLOW_AND_WEAK (2<<0)
+#define CFG_REGS_DDR_DRIVE_SLOW_AND_STRONG (1<<0)
+#define CFG_REGS_DDR_DRIVE_SLOW_AND_MOST_STRONG (0<<0)
+#define CFG_REGS_PSRAM1_DRIVE_MASK (7<<3)
+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_MOST_WEAK (7<<3)
+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_WEAK (6<<3)
+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_STRONG (5<<3)
+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_MOST_STRONG (4<<3)
+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_MOST_WEAK (3<<3)
+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_WEAK (2<<3)
+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_STRONG (1<<3)
+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_MOST_STRONG (0<<3)
+#define CFG_REGS_PSRAM2_DRIVE_MASK (7<<6)
+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_MOST_WEAK (7<<6)
+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_WEAK (6<<6)
+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_STRONG (5<<6)
+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_MOST_STRONG (4<<6)
+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_MOST_WEAK (3<<6)
+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_WEAK (2<<6)
+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_STRONG (1<<6)
+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_MOST_STRONG (0<<6)
+#define CFG_REGS_NFLSH_DRIVE_MASK  (7<<9)
+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_MOST_WEAK (7<<9)
+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_WEAK (6<<9)
+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_STRONG (5<<9)
+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_MOST_STRONG (4<<9)
+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_MOST_WEAK (3<<9)
+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_WEAK (2<<9)
+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_STRONG (1<<9)
+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_MOST_STRONG (0<<9)
+#define CFG_REGS_LCD1_DRIVE_MASK   (7<<12)
+#define CFG_REGS_LCD1_DRIVE_FAST_AND_MOST_WEAK (7<<12)
+#define CFG_REGS_LCD1_DRIVE_FAST_AND_WEAK (6<<12)
+#define CFG_REGS_LCD1_DRIVE_FAST_AND_STRONG (5<<12)
+#define CFG_REGS_LCD1_DRIVE_FAST_AND_MOST_STRONG (4<<12)
+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_MOST_WEAK (3<<12)
+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_WEAK (2<<12)
+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_STRONG (1<<12)
+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_MOST_STRONG (0<<12)
+#define CFG_REGS_LCD2_DRIVE_MASK   (7<<15)
+#define CFG_REGS_LCD2_DRIVE_FAST_AND_MOST_WEAK (7<<15)
+#define CFG_REGS_LCD2_DRIVE_FAST_AND_WEAK (6<<15)
+#define CFG_REGS_LCD2_DRIVE_FAST_AND_STRONG (5<<15)
+#define CFG_REGS_LCD2_DRIVE_FAST_AND_MOST_STRONG (4<<15)
+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_MOST_WEAK (3<<15)
+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_WEAK (2<<15)
+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_STRONG (1<<15)
+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_MOST_STRONG (0<<15)
+#define CFG_REGS_SDAT1_DRIVE_MASK  (7<<18)
+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_MOST_WEAK (7<<18)
+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_WEAK (6<<18)
+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_STRONG (5<<18)
+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_MOST_STRONG (4<<18)
+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_MOST_WEAK (3<<18)
+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_WEAK (2<<18)
+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_STRONG (1<<18)
+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_MOST_STRONG (0<<18)
+#define CFG_REGS_SDAT2_DRIVE_MASK  (7<<21)
+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_MOST_WEAK (7<<21)
+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_WEAK (6<<21)
+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_STRONG (5<<21)
+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_MOST_STRONG (4<<21)
+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_MOST_WEAK (3<<21)
+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_WEAK (2<<21)
+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_STRONG (1<<21)
+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_MOST_STRONG (0<<21)
+#define CFG_REGS_CAM_DRIVE_MASK    (3<<24)
+#define CFG_REGS_CAM_DRIVE_MOST_STRONG (0<<24)
+#define CFG_REGS_CAM_DRIVE_STRONG  (1<<24)
+#define CFG_REGS_CAM_DRIVE_WEAK    (2<<24)
+#define CFG_REGS_CAM_DRIVE_MOST_WEAK (3<<24)
+#define CFG_REGS_SIM1_DRIVE_MASK   (3<<26)
+#define CFG_REGS_SIM1_DRIVE_MOST_STRONG (0<<26)
+#define CFG_REGS_SIM1_DRIVE_STRONG (1<<26)
+#define CFG_REGS_SIM1_DRIVE_WEAK   (2<<26)
+#define CFG_REGS_SIM1_DRIVE_MOST_WEAK (3<<26)
+#define CFG_REGS_SIM2_DRIVE_MASK   (3<<28)
+#define CFG_REGS_SIM2_DRIVE_MOST_STRONG (0<<28)
+#define CFG_REGS_SIM2_DRIVE_STRONG (1<<28)
+#define CFG_REGS_SIM2_DRIVE_WEAK   (2<<28)
+#define CFG_REGS_SIM2_DRIVE_MOST_WEAK (3<<28)
+#define CFG_REGS_SIM3_DRIVE_MASK   (3<<30)
+#define CFG_REGS_SIM3_DRIVE_MOST_STRONG (0<<30)
+#define CFG_REGS_SIM3_DRIVE_STRONG (1<<30)
+#define CFG_REGS_SIM3_DRIVE_WEAK   (2<<30)
+#define CFG_REGS_SIM3_DRIVE_MOST_WEAK (3<<30)
+
+//IO_Drive2_Select
+#define CFG_REGS_GPIO_DRIVE_MASK   (3<<0)
+#define CFG_REGS_GPIO_DRIVE_MOST_STRONG (0<<0)
+#define CFG_REGS_GPIO_DRIVE_STRONG (1<<0)
+#define CFG_REGS_GPIO_DRIVE_WEAK   (2<<0)
+#define CFG_REGS_GPIO_DRIVE_MOST_WEAK (3<<0)
+#define CFG_REGS_CAM2_DRIVE_MASK   (3<<2)
+#define CFG_REGS_CAM2_DRIVE_MOST_STRONG (0<<2)
+#define CFG_REGS_CAM2_DRIVE_STRONG (1<<2)
+#define CFG_REGS_CAM2_DRIVE_WEAK   (2<<2)
+#define CFG_REGS_CAM2_DRIVE_MOST_WEAK (3<<2)
+
+//RAM_DRIVE
+#define CFG_REGS_MBRAM_A(n)        (((n)&7)<<0)
+#define CFG_REGS_MBRAM_A_MASK      (7<<0)
+#define CFG_REGS_MBRAM_A_SHIFT     (0)
+#define CFG_REGS_MBRAM_W(n)        (((n)&3)<<3)
+#define CFG_REGS_MBRAM_W_MASK      (3<<3)
+#define CFG_REGS_MBRAM_W_SHIFT     (3)
+#define CFG_REGS_MBRAM_R           (1<<5)
+#define CFG_REGS_BBRAM_A(n)        (((n)&7)<<6)
+#define CFG_REGS_BBRAM_A_MASK      (7<<6)
+#define CFG_REGS_BBRAM_A_SHIFT     (6)
+#define CFG_REGS_BBRAM_W(n)        (((n)&3)<<9)
+#define CFG_REGS_BBRAM_W_MASK      (3<<9)
+#define CFG_REGS_BBRAM_W_SHIFT     (9)
+#define CFG_REGS_BBRAM_R           (1<<11)
+#define CFG_REGS_XP_A(n)           (((n)&7)<<12)
+#define CFG_REGS_XP_A_MASK         (7<<12)
+#define CFG_REGS_XP_A_SHIFT        (12)
+#define CFG_REGS_XP_W(n)           (((n)&3)<<15)
+#define CFG_REGS_XP_W_MASK         (3<<15)
+#define CFG_REGS_XP_W_SHIFT        (15)
+#define CFG_REGS_XP_R              (1<<17)
+#define CFG_REGS_BP_A(n)           (((n)&7)<<18)
+#define CFG_REGS_BP_A_MASK         (7<<18)
+#define CFG_REGS_BP_A_SHIFT        (18)
+#define CFG_REGS_BP_W(n)           (((n)&3)<<21)
+#define CFG_REGS_BP_W_MASK         (3<<21)
+#define CFG_REGS_BP_W_SHIFT        (21)
+#define CFG_REGS_BP_R              (1<<23)
+#define CFG_REGS_EV_A(n)           (((n)&7)<<24)
+#define CFG_REGS_EV_A_MASK         (7<<24)
+#define CFG_REGS_EV_A_SHIFT        (24)
+#define CFG_REGS_EV_W(n)           (((n)&3)<<27)
+#define CFG_REGS_EV_W_MASK         (3<<27)
+#define CFG_REGS_EV_W_SHIFT        (27)
+#define CFG_REGS_EV_R              (1<<29)
+
+//H2X_AP_Offset
+#define CFG_REGS_H2X_AP_OFFSET(n)  (((n)&0xFF)<<0)
+#define CFG_REGS_H2X_AP_OFFSET_MASK (0xFF<<0)
+#define CFG_REGS_H2X_AP_OFFSET_SHIFT (0)
+
+//H2X_DDR_Offset
+#define CFG_REGS_H2X_DDR_OFFSET(n) (((n)&0xFF)<<0)
+#define CFG_REGS_H2X_DDR_OFFSET_MASK (0xFF<<0)
+#define CFG_REGS_H2X_DDR_OFFSET_SHIFT (0)
+
+//audio_pd_set
+#define CFG_REGS_AU_DEEP_PD_N      (1<<0)
+#define CFG_REGS_AU_REF_PD_N       (1<<1)
+#define CFG_REGS_AU_MIC_PD_N       (1<<2)
+#define CFG_REGS_AU_AUXMIC_PD_N    (1<<3)
+#define CFG_REGS_AU_AD_PD_N        (1<<4)
+#define CFG_REGS_AU_DAC_PD_N       (1<<5)
+#define CFG_REGS_AU_DAC_RESET_N    (1<<8)
+#define CFG_REGS_AU_PLL_PU         (1<<16)
+
+//audio_pd_clr
+//#define CFG_REGS_AU_DEEP_PD_N    (1<<0)
+//#define CFG_REGS_AU_REF_PD_N     (1<<1)
+//#define CFG_REGS_AU_MIC_PD_N     (1<<2)
+//#define CFG_REGS_AU_AUXMIC_PD_N  (1<<3)
+//#define CFG_REGS_AU_AD_PD_N      (1<<4)
+//#define CFG_REGS_AU_DAC_PD_N     (1<<5)
+//#define CFG_REGS_AU_DAC_RESET_N  (1<<8)
+//#define CFG_REGS_AU_PLL_PU       (1<<16)
+
+//audio_sel_cfg
+#define CFG_REGS_AU_AUXMIC_SEL     (1<<0)
+#define CFG_REGS_AU_SPK_SEL        (1<<1)
+#define CFG_REGS_AU_SPK_MONO_SEL   (1<<2)
+#define CFG_REGS_AU_RCV_SEL        (1<<3)
+#define CFG_REGS_AU_HEAD_SEL       (1<<4)
+
+//audio_mic_cfg
+#define CFG_REGS_AU_MIC_GAIN(n)    (((n)&15)<<0)
+#define CFG_REGS_AU_MIC_GAIN_MASK  (15<<0)
+#define CFG_REGS_AU_MIC_GAIN_SHIFT (0)
+#define CFG_REGS_AU_MIC_MUTE_N     (1<<4)
+
+//audio_spk_cfg
+#define CFG_REGS_AU_SPK_GAIN(n)    (((n)&15)<<0)
+#define CFG_REGS_AU_SPK_GAIN_MASK  (15<<0)
+#define CFG_REGS_AU_SPK_GAIN_SHIFT (0)
+#define CFG_REGS_AU_SPK_MUTE_N     (1<<4)
+#define CFG_REGS_AU_SPK_VOC_GAIN_EN (1<<8)
+
+//audio_rcv_gain
+#define CFG_REGS_AU_RCV_GAIN(n)    (((n)&15)<<0)
+#define CFG_REGS_AU_RCV_GAIN_MASK  (15<<0)
+#define CFG_REGS_AU_RCV_GAIN_SHIFT (0)
+#define CFG_REGS_AU_RCV_VOC_GAIN_EN (1<<8)
+
+//audio_head_gain
+#define CFG_REGS_AU_HEAD_GAIN(n)   (((n)&15)<<0)
+#define CFG_REGS_AU_HEAD_GAIN_MASK (15<<0)
+#define CFG_REGS_AU_HEAD_GAIN_SHIFT (0)
+#define CFG_REGS_AU_HEAD_VOC_GAIN_EN (1<<8)
+
+//TSC_DATA
+#define CFG_REGS_TSC_X_VALUE_BIT(n) (((n)&0x3FF)<<0)
+#define CFG_REGS_TSC_X_VALUE_BIT_MASK (0x3FF<<0)
+#define CFG_REGS_TSC_X_VALUE_BIT_SHIFT (0)
+#define CFG_REGS_TSC_X_VALUE_VALID (1<<10)
+#define CFG_REGS_TSC_Y_VALUE_BIT(n) (((n)&0x3FF)<<11)
+#define CFG_REGS_TSC_Y_VALUE_BIT_MASK (0x3FF<<11)
+#define CFG_REGS_TSC_Y_VALUE_BIT_SHIFT (11)
+#define CFG_REGS_TSC_Y_VALUE_VALID (1<<21)
+
+//GPADC_DATA_CH
+#define CFG_REGS_GPADC_DATA(n)     (((n)&0x3FF)<<0)
+#define CFG_REGS_GPADC_DATA_MASK   (0x3FF<<0)
+#define CFG_REGS_GPADC_DATA_SHIFT  (0)
+#define CFG_REGS_GPADC_VALID       (1<<10)
+#define CFG_REGS_GPADC_CH_EN       (1<<31)
+
+//Alt_mux_select2
+#define CFG_REGS_UART1_SDIO2_MASK  (1<<0)
+#define CFG_REGS_UART1_SDIO2_SDIO2 (0<<0)
+#define CFG_REGS_UART1_SDIO2_UART1 (1<<0)
+#define CFG_REGS_JTAG_EN_MASK      (1<<1)
+#define CFG_REGS_JTAG_EN_DISABLE   (0<<1)
+#define CFG_REGS_JTAG_EN_ENABLE    (1<<1)
+#define CFG_REGS_LCD_RGB_17_16_MASK (1<<2)
+#define CFG_REGS_LCD_RGB_17_16_LCD_CS (0<<2)
+#define CFG_REGS_LCD_RGB_17_16_LCD_DATA (1<<2)
+#define CFG_REGS_CSI2_2_MASK       (3<<3)
+#define CFG_REGS_CSI2_2_PARALLEL_CAM (0<<3)
+#define CFG_REGS_CSI2_2_CSI2       (1<<3)
+#define CFG_REGS_CSI2_2_SPI_CAM    (2<<3)
+#define CFG_REGS_RGB_CAM_2_MASK    (1<<5)
+#define CFG_REGS_RGB_CAM_2_DISABLE (0<<5)
+#define CFG_REGS_RGB_CAM_2_ENABLE  (1<<5)
+#define CFG_REGS_MAC_EN_MASK       (1<<6)
+#define CFG_REGS_MAC_EN_DISABLE    (0<<6)
+#define CFG_REGS_MAC_EN_ENABLE     (1<<6)
+#define CFG_REGS_IOMUX_CFG_RESERVED(n) (((n)&0x1FFFFFF)<<7)
+
+//AP_GPIO_E_Mode
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_MASK (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_SHIFT (0)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_ALT (0<<0)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_GPIO (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA (1<<1)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_MASK (1<<1)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_SHIFT (1)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_ALT (0<<1)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_GPIO (1<<1)
+#define CFG_REGS_MODE_AP_PIN_CAM2_RST (1<<2)
+#define CFG_REGS_MODE_AP_PIN_CAM2_RST_MASK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_CAM2_RST_SHIFT (2)
+#define CFG_REGS_MODE_AP_PIN_CAM2_RST_ALT (0<<2)
+#define CFG_REGS_MODE_AP_PIN_CAM2_RST_GPIO (1<<2)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PDN (1<<3)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_MASK (1<<3)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_SHIFT (3)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_ALT (0<<3)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_GPIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_CAM2_CLK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_MASK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_SHIFT (4)
+#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_ALT (0<<4)
+#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_GPIO (1<<4)
+#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC (1<<5)
+#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_MASK (1<<5)
+#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_SHIFT (5)
+#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_ALT (0<<5)
+#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_GPIO (1<<5)
+#define CFG_REGS_MODE_AP_PIN_CAM2_HREF (1<<6)
+#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_MASK (1<<6)
+#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_SHIFT (6)
+#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_ALT (0<<6)
+#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_GPIO (1<<6)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_MASK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_SHIFT (7)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_ALT (0<<7)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_GPIO (1<<7)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0 (1<<8)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_MASK (1<<8)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_SHIFT (8)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_ALT (0<<8)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_GPIO (1<<8)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1 (1<<9)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_MASK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_SHIFT (9)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_ALT (0<<9)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_GPIO (1<<9)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2 (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_MASK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_SHIFT (10)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_ALT (0<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_GPIO (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3 (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_MASK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_SHIFT (11)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_ALT (0<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_GPIO (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4 (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_MASK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_SHIFT (12)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_ALT (0<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_GPIO (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5 (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_MASK (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_SHIFT (13)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_ALT (0<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_GPIO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6 (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_MASK (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_SHIFT (14)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_ALT (0<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_GPIO (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7 (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_MASK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_SHIFT (15)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_ALT (0<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_GPIO (1<<15)
+#define CFG_REGS_AP_GPIO_E_MODE(n) (((n)&0xFFFF)<<0)
+#define CFG_REGS_AP_GPIO_E_MODE_MASK (0xFFFF<<0)
+#define CFG_REGS_AP_GPIO_E_MODE_SHIFT (0)
+
+
+
+
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8820.h b/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8820.h
new file mode 100644
index 0000000000..3ff671b6fd
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8820.h
@@ -0,0 +1,1300 @@
+//==============================================================================
+//
+//            Copyright (C) 2012-2014, RDA Microelectronics.
+//                            All Rights Reserved
+//
+//      This source code is the property of RDA Microelectronics and is
+//      confidential.  Any  modification, distribution,  reproduction or
+//      exploitation  of  any content of this file is totally forbidden,
+//      except  with the  written permission  of   RDA Microelectronics.
+//
+//==============================================================================
+//
+//    THIS FILE WAS GENERATED FROM ITS CORRESPONDING XML VERSION WITH COOLXML.
+//
+//                       !!! PLEASE DO NOT EDIT !!!
+//
+//  $HeadURL$
+//  $Author$
+//  $Date$
+//  $Revision$
+//
+//==============================================================================
+//
+/// @file
+//
+//==============================================================================
+
+#ifndef _CFG_REGS_H_
+#define _CFG_REGS_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+#ifdef CT_ASM
+#error "You are trying to use in an assembly code the normal H description of 'cfg_regs'."
+#endif
+
+
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+#define PROD_ID                                 (0X810E)
+
+// ============================================================================
+// BB_GPIO_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// BB GPIO Map
+    BB_PIN_NONE_0                               = 0x00000000,
+    BB_PIN_1                                    = 0x00000001,
+    BB_PIN_2                                    = 0x00000002,
+    BB_PIN_3                                    = 0x00000003,
+    BB_PIN_4                                    = 0x00000004,
+    BB_PIN_5                                    = 0x00000005,
+    BB_PIN_UART1_RXD                            = 0x00000006,
+    BB_PIN_UART2_RXD                            = 0x00000007,
+    BB_PIN_UART2_TXD                            = 0x00000008,
+    BB_PIN_SSD1_CLK                             = 0x00000009,
+    BB_PIN_SSD1_CMD                             = 0x0000000A,
+    BB_PIN_SDAT1_0                              = 0x0000000B,
+    BB_PIN_SDAT1_1                              = 0x0000000C,
+    BB_PIN_SDAT1_2                              = 0x0000000D,
+    BB_PIN_SDAT1_3                              = 0x0000000E,
+    BB_PIN_SSD2_CLK                             = 0x0000000F,
+    BB_PIN_SSD2_CMD                             = 0x00000010,
+    BB_PIN_SDAT2_0                              = 0x00000011,
+    BB_PIN_SDAT2_1                              = 0x00000012,
+    BB_PIN_SDAT2_2                              = 0x00000013,
+    BB_PIN_SDAT2_3                              = 0x00000014,
+    BB_PIN_SPI1_CLK                             = 0x00000015,
+    BB_PIN_SPI1_CS_0                            = 0x00000016,
+    BB_PIN_SPI1_DIO                             = 0x00000017,
+    BB_PIN_SPI1_DI                              = 0x00000018,
+    BB_PIN_SIM2_RST                             = 0x00000019,
+    BB_PIN_SIM2_CLK                             = 0x0000001A,
+    BB_PIN_SIM2_DIO                             = 0x0000001B,
+    BB_PIN_SIM3_RST                             = 0x0000001C,
+    BB_PIN_SIM3_CLK                             = 0x0000001D,
+    BB_PIN_SIM3_DIO                             = 0x0000001E
+} BB_GPIO_MAPPING_T;
+
+#define BB_GPIO_NB                              (31)
+
+// ============================================================================
+// AP_GPIO_A_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP GPIO A Map
+    AP_PIN_I2C2_SCL                             = 0x00000000,
+    AP_PIN_I2C2_SDA                             = 0x00000001,
+    AP_PIN_SPI2_CLK                             = 0x00000002,
+    AP_PIN_SPI2_DIO                             = 0x00000003,
+    AP_PIN_SPI2_DI                              = 0x00000004,
+    AP_PIN_SPI2_CS_0                            = 0x00000005,
+    AP_PIN_SPI2_CS_1                            = 0x00000006,
+    AP_PIN_KEYIN_4                              = 0x00000007,
+    AP_PIN_CLK_OUT                              = 0x00000008,
+    AP_PIN_I2S_BCK                              = 0x00000009,
+    AP_PIN_I2S_LRCK                             = 0x0000000A,
+    AP_PIN_I2S_DI_0                             = 0x0000000B,
+    AP_PIN_I2S_DI_1                             = 0x0000000C,
+    AP_PIN_I2S_DO                               = 0x0000000D,
+    AP_PIN_UART1_TXD                            = 0x0000000E,
+    AP_PIN_UART1_CTS                            = 0x0000000F,
+    AP_PIN_UART1_RTS                            = 0x00000010,
+    AP_PIN_SPI1_CS_1                            = 0x00000011,
+    AP_PIN_LCD_DATA_6                           = 0x00000012,
+    AP_PIN_LCD_DATA_7                           = 0x00000013,
+    AP_PIN_LCD_WR                               = 0x00000014,
+    AP_PIN_LCD_RS                               = 0x00000015,
+    AP_PIN_LCD_RD                               = 0x00000016,
+    AP_PIN_LCD_FMARK                            = 0x00000017,
+    AP_PIN_LCD_DATA_8                           = 0x00000018,
+    AP_PIN_LCD_DATA_9                           = 0x00000019,
+    AP_PIN_LCD_DATA_10                          = 0x0000001A,
+    AP_PIN_LCD_DATA_11                          = 0x0000001B,
+    AP_PIN_LCD_DATA_12                          = 0x0000001C,
+    AP_PIN_LCD_DATA_13                          = 0x0000001D,
+    AP_PIN_LCD_DATA_14                          = 0x0000001E,
+    AP_PIN_LCD_DATA_15                          = 0x0000001F
+} AP_GPIO_A_MAPPING_T;
+
+#define AP_GPIO_A_NB                            (32)
+
+// ============================================================================
+// AP_GPIO_B_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP GPIO B Map
+    AP_PIN_KEYIN_0                              = 0x00000000,
+    AP_PIN_KEYIN_1                              = 0x00000001,
+    AP_PIN_KEYIN_2                              = 0x00000002,
+    AP_PIN_KEYOUT_0                             = 0x00000003,
+    AP_PIN_KEYOUT_1                             = 0x00000004,
+    AP_PIN_KEYOUT_2                             = 0x00000005,
+    AP_PIN_I2C3_SCL                             = 0x00000006,
+    AP_PIN_I2C3_SDA                             = 0x00000007,
+    AP_PIN_UART2_CTS                            = 0x00000008,
+    AP_PIN_UART2_RTS                            = 0x00000009,
+    AP_PIN_CAM_RST                              = 0x0000000A,
+    AP_PIN_CAM_PDN                              = 0x0000000B,
+    AP_PIN_CAM_CLK                              = 0x0000000C,
+    AP_PIN_CAM_VSYNC                            = 0x0000000D,
+    AP_PIN_CAM_HREF                             = 0x0000000E,
+    AP_PIN_CAM_PCLK                             = 0x0000000F,
+    AP_PIN_CAM_DATA_0                           = 0x00000010,
+    AP_PIN_CAM_DATA_1                           = 0x00000011,
+    AP_PIN_CAM_DATA_2                           = 0x00000012,
+    AP_PIN_CAM_DATA_3                           = 0x00000013,
+    AP_PIN_CAM_DATA_4                           = 0x00000014,
+    AP_PIN_CAM_DATA_5                           = 0x00000015,
+    AP_PIN_CAM_DATA_6                           = 0x00000016,
+    AP_PIN_CAM_DATA_7                           = 0x00000017,
+    AP_PIN_M_SPI_CS_0                           = 0x00000018,
+    AP_PIN_NFCLE                                = 0x00000019,
+    AP_PIN_NFWEN                                = 0x0000001A,
+    AP_PIN_NFWPN                                = 0x0000001B,
+    AP_PIN_NFREN                                = 0x0000001C,
+    AP_PIN_NFRB                                 = 0x0000001D,
+    AP_PIN_I2C1_SCL                             = 0x0000001E,
+    AP_PIN_I2C1_SDA                             = 0x0000001F
+} AP_GPIO_B_MAPPING_T;
+
+#define AP_GPIO_B_NB                            (32)
+
+// ============================================================================
+// AP_GPIO_D_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP GPIO D Map
+    AP_PIN_UART3_RXD                            = 0x00000000,
+    AP_PIN_UART3_TXD                            = 0x00000001,
+    AP_PIN_UART3_CTS                            = 0x00000002,
+    AP_PIN_UART3_RTS                            = 0x00000003,
+    AP_PIN_NFDQS                                = 0x00000004,
+    AP_PIN_VOLUME_DN                            = 0x00000005,
+    AP_PIN_VOLUME_UP                            = 0x00000006,
+    AP_PIN_PLUGIN                               = 0x00000007,
+    AP_PIN_NFCEN_1                              = 0x00000008,
+    AP_PIN_NFCEN_2                              = 0x00000009,
+    AP_PIN_NFCEN_3                              = 0x0000000A,
+    AP_PIN_I2S2_BCK                             = 0x0000000B,
+    AP_PIN_I2S2_LRCK                            = 0x0000000C,
+    AP_PIN_I2S2_DI_0                            = 0x0000000D,
+    AP_PIN_I2S2_DI_1                            = 0x0000000E,
+    AP_PIN_I2S2_DO                              = 0x0000000F
+} AP_GPIO_D_MAPPING_T;
+
+#define AP_GPIO_D_NB                            (16)
+
+// ============================================================================
+// AP_GPIO_E_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP GPIO E Map
+    AP_PIN_I2CBB_SCL                            = 0x00000000,
+    AP_PIN_I2CBB_SDA                            = 0x00000001,
+    AP_PIN_CAM2_RST                             = 0x00000002,
+    AP_PIN_CAM2_PDN                             = 0x00000003,
+    AP_PIN_CAM2_CLK                             = 0x00000004,
+    AP_PIN_CAM2_VSYNC                           = 0x00000005,
+    AP_PIN_CAM2_HREF                            = 0x00000006,
+    AP_PIN_CAM2_PCLK                            = 0x00000007,
+    AP_PIN_CAM2_DATA_0                          = 0x00000008,
+    AP_PIN_CAM2_DATA_1                          = 0x00000009,
+    AP_PIN_CAM2_DATA_2                          = 0x0000000A,
+    AP_PIN_CAM2_DATA_3                          = 0x0000000B,
+    AP_PIN_CAM2_DATA_4                          = 0x0000000C,
+    AP_PIN_CAM2_DATA_5                          = 0x0000000D,
+    AP_PIN_CAM2_DATA_6                          = 0x0000000E,
+    AP_PIN_CAM2_DATA_7                          = 0x0000000F
+} AP_GPIO_E_MAPPING_T;
+
+#define AP_GPIO_E_NB                            (16)
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+// ============================================================================
+// CFG_REGS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef volatile struct
+{
+    REG32                          CHIP_ID;                      //0x00000000
+    /// This register contain the synthesis date and version
+    REG32                          Build_Version;                //0x00000004
+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+    /// bit n to '0' selects Alt.
+    REG32                          BB_GPIO_Mode;                 //0x00000008
+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+    /// bit n to '0' selects Alt.
+    REG32                          AP_GPIO_A_Mode;               //0x0000000C
+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+    /// bit n to '0' selects Alt.
+    REG32                          AP_GPIO_B_Mode;               //0x00000010
+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+    /// bit n to '0' selects Alt.
+    REG32                          AP_GPIO_D_Mode;               //0x00000014
+    REG32                          Alt_mux_select;               //0x00000018
+    REG32                          IO_Drive1_Select;             //0x0000001C
+    REG32                          IO_Drive2_Select;             //0x00000020
+    REG32                          RAM_DRIVE;                    //0x00000024
+    REG32                          H2X_AP_Offset;                //0x00000028
+    REG32                          H2X_DDR_Offset;               //0x0000002C
+    REG32                          audio_pd_set;                 //0x00000030
+    REG32                          audio_pd_clr;                 //0x00000034
+    REG32                          audio_sel_cfg;                //0x00000038
+    REG32                          audio_mic_cfg;                //0x0000003C
+    REG32                          audio_spk_cfg;                //0x00000040
+    REG32                          audio_rcv_gain;               //0x00000044
+    REG32                          audio_head_gain;              //0x00000048
+    REG32                          TSC_DATA;                     //0x0000004C
+    REG32                          GPADC_DATA_CH[8];             //0x00000050
+    REG32                          Alt_mux_select2;              //0x00000070
+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+    /// bit n to '0' selects Alt.
+    REG32                          AP_GPIO_E_Mode;               //0x00000074
+} HWP_CFG_REGS_T;
+
+#define hwp_configRegs             ((HWP_CFG_REGS_T*)(RDA_CFG_REGS_BASE))
+
+
+//CHIP_ID
+#define CFG_REGS_METAL_ID(n)       (((n)&0xFFF)<<0)
+#define CFG_REGS_METAL_ID_MASK     (0xFFF<<0)
+#define CFG_REGS_METAL_ID_SHIFT    (0)
+#define CFG_REGS_BOND_ID(n)        (((n)&7)<<12)
+#define CFG_REGS_BOND_ID_MASK      (7<<12)
+#define CFG_REGS_BOND_ID_SHIFT     (12)
+#define CFG_REGS_PROD_ID(n)        (((n)&0xFFFF)<<16)
+#define CFG_REGS_PROD_ID_MASK      (0xFFFF<<16)
+#define CFG_REGS_PROD_ID_SHIFT     (16)
+
+//Build_Version
+#define CFG_REGS_MAJOR(n)          (((n)&15)<<28)
+#define CFG_REGS_YEAR(n)           (((n)&15)<<24)
+#define CFG_REGS_MONTH(n)          (((n)&0xFF)<<16)
+#define CFG_REGS_DAY(n)            (((n)&0xFF)<<8)
+#define CFG_REGS_BUILD_STYLE_FPGA  (0<<4)
+#define CFG_REGS_BUILD_STYLE_CHIP  (1<<4)
+#define CFG_REGS_BUILD_STYLE_FPGA_USB (2<<4)
+#define CFG_REGS_BUILD_STYLE_FPGA_GSM (3<<4)
+#define CFG_REGS_BUILD_REVISION(n) (((n)&15)<<0)
+
+//BB_GPIO_Mode
+#define CFG_REGS_MODE_BB_PIN_NONE_0 (1<<0)
+#define CFG_REGS_MODE_BB_PIN_NONE_0_MASK (1<<0)
+#define CFG_REGS_MODE_BB_PIN_NONE_0_SHIFT (0)
+#define CFG_REGS_MODE_BB_PIN_NONE_0_ALT (0<<0)
+#define CFG_REGS_MODE_BB_PIN_NONE_0_GPIO (1<<0)
+#define CFG_REGS_MODE_BB_PIN_1     (1<<1)
+#define CFG_REGS_MODE_BB_PIN_1_MASK (1<<1)
+#define CFG_REGS_MODE_BB_PIN_1_SHIFT (1)
+#define CFG_REGS_MODE_BB_PIN_1_ALT (0<<1)
+#define CFG_REGS_MODE_BB_PIN_1_GPIO (1<<1)
+#define CFG_REGS_MODE_BB_PIN_2     (1<<2)
+#define CFG_REGS_MODE_BB_PIN_2_MASK (1<<2)
+#define CFG_REGS_MODE_BB_PIN_2_SHIFT (2)
+#define CFG_REGS_MODE_BB_PIN_2_ALT (0<<2)
+#define CFG_REGS_MODE_BB_PIN_2_GPIO (1<<2)
+#define CFG_REGS_MODE_BB_PIN_3     (1<<3)
+#define CFG_REGS_MODE_BB_PIN_3_MASK (1<<3)
+#define CFG_REGS_MODE_BB_PIN_3_SHIFT (3)
+#define CFG_REGS_MODE_BB_PIN_3_ALT (0<<3)
+#define CFG_REGS_MODE_BB_PIN_3_GPIO (1<<3)
+#define CFG_REGS_MODE_BB_PIN_4     (1<<4)
+#define CFG_REGS_MODE_BB_PIN_4_MASK (1<<4)
+#define CFG_REGS_MODE_BB_PIN_4_SHIFT (4)
+#define CFG_REGS_MODE_BB_PIN_4_ALT (0<<4)
+#define CFG_REGS_MODE_BB_PIN_4_GPIO (1<<4)
+#define CFG_REGS_MODE_BB_PIN_5     (1<<5)
+#define CFG_REGS_MODE_BB_PIN_5_MASK (1<<5)
+#define CFG_REGS_MODE_BB_PIN_5_SHIFT (5)
+#define CFG_REGS_MODE_BB_PIN_5_ALT (0<<5)
+#define CFG_REGS_MODE_BB_PIN_5_GPIO (1<<5)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD (1<<6)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_MASK (1<<6)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_SHIFT (6)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_ALT (0<<6)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_GPIO (1<<6)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD (1<<7)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_MASK (1<<7)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_SHIFT (7)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_ALT (0<<7)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_GPIO (1<<7)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD (1<<8)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_MASK (1<<8)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_SHIFT (8)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_ALT (0<<8)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_GPIO (1<<8)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK (1<<9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_MASK (1<<9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_SHIFT (9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_ALT (0<<9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_GPIO (1<<9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD (1<<10)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_MASK (1<<10)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_SHIFT (10)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_ALT (0<<10)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_GPIO (1<<10)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0 (1<<11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_MASK (1<<11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_SHIFT (11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_ALT (0<<11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_GPIO (1<<11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1 (1<<12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_MASK (1<<12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_SHIFT (12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_ALT (0<<12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_GPIO (1<<12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2 (1<<13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_MASK (1<<13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_SHIFT (13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_ALT (0<<13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_GPIO (1<<13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3 (1<<14)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_MASK (1<<14)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_SHIFT (14)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_ALT (0<<14)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_GPIO (1<<14)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK (1<<15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_MASK (1<<15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_SHIFT (15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_ALT (0<<15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_GPIO (1<<15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD (1<<16)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_MASK (1<<16)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_SHIFT (16)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_ALT (0<<16)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_GPIO (1<<16)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0 (1<<17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_MASK (1<<17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_SHIFT (17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_ALT (0<<17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_GPIO (1<<17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1 (1<<18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_MASK (1<<18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_SHIFT (18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_ALT (0<<18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_GPIO (1<<18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2 (1<<19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_MASK (1<<19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_SHIFT (19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_ALT (0<<19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_GPIO (1<<19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3 (1<<20)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_MASK (1<<20)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_SHIFT (20)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_ALT (0<<20)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_GPIO (1<<20)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK (1<<21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_MASK (1<<21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_SHIFT (21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_ALT (0<<21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_GPIO (1<<21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0 (1<<22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_MASK (1<<22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_SHIFT (22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_ALT (0<<22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_GPIO (1<<22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO (1<<23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_MASK (1<<23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_SHIFT (23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_ALT (0<<23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_GPIO (1<<23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI (1<<24)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_MASK (1<<24)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_SHIFT (24)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_ALT (0<<24)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_GPIO (1<<24)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST (1<<25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_MASK (1<<25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_SHIFT (25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_ALT (0<<25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_GPIO (1<<25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK (1<<26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_MASK (1<<26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_SHIFT (26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_ALT (0<<26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_GPIO (1<<26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO (1<<27)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_MASK (1<<27)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_SHIFT (27)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_ALT (0<<27)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_GPIO (1<<27)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST (1<<28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_MASK (1<<28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_SHIFT (28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_ALT (0<<28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_GPIO (1<<28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK (1<<29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_MASK (1<<29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_SHIFT (29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_ALT (0<<29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_GPIO (1<<29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO (1<<30)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_MASK (1<<30)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_SHIFT (30)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_ALT (0<<30)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_GPIO (1<<30)
+#define CFG_REGS_BB_GPIO_MODE(n)   (((n)&0x7FFFFFFF)<<0)
+#define CFG_REGS_BB_GPIO_MODE_MASK (0x7FFFFFFF<<0)
+#define CFG_REGS_BB_GPIO_MODE_SHIFT (0)
+
+//AP_GPIO_A_Mode
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_MASK (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_SHIFT (0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_ALT (0<<0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_GPIO (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA (1<<1)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_MASK (1<<1)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_SHIFT (1)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_ALT (0<<1)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_GPIO (1<<1)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_MASK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_SHIFT (2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_ALT (0<<2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_GPIO (1<<2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_MASK (1<<3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_SHIFT (3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_ALT (0<<3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_GPIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI (1<<4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_MASK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_SHIFT (4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_ALT (0<<4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_GPIO (1<<4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0 (1<<5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_MASK (1<<5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_SHIFT (5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_ALT (0<<5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_GPIO (1<<5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1 (1<<6)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_MASK (1<<6)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_SHIFT (6)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_ALT (0<<6)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_GPIO (1<<6)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4 (1<<7)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_MASK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_SHIFT (7)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_ALT (0<<7)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_GPIO (1<<7)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT (1<<8)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_MASK (1<<8)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_SHIFT (8)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_ALT (0<<8)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_GPIO (1<<8)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_MASK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_SHIFT (9)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_ALT (0<<9)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_GPIO (1<<9)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_MASK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_SHIFT (10)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_ALT (0<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_GPIO (1<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0 (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_MASK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_SHIFT (11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_ALT (0<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_GPIO (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1 (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_MASK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_SHIFT (12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_ALT (0<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_GPIO (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO_MASK (1<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO_SHIFT (13)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO_ALT (0<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO_GPIO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD (1<<14)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_MASK (1<<14)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_SHIFT (14)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_ALT (0<<14)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_GPIO (1<<14)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS (1<<15)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_MASK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_SHIFT (15)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_ALT (0<<15)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_GPIO (1<<15)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS (1<<16)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_MASK (1<<16)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_SHIFT (16)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_ALT (0<<16)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_GPIO (1<<16)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1 (1<<17)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_MASK (1<<17)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_SHIFT (17)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_ALT (0<<17)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_GPIO (1<<17)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6 (1<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_MASK (1<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_SHIFT (18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_ALT (0<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_GPIO (1<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7 (1<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_MASK (1<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_SHIFT (19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_ALT (0<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_GPIO (1<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR (1<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR_MASK (1<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR_SHIFT (20)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR_ALT (0<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR_GPIO (1<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS (1<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS_MASK (1<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS_SHIFT (21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS_ALT (0<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS_GPIO (1<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD (1<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD_MASK (1<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD_SHIFT (22)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD_ALT (0<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD_GPIO (1<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK (1<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_MASK (1<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_SHIFT (23)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_ALT (0<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_GPIO (1<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8 (1<<24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_MASK (1<<24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_SHIFT (24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_ALT (0<<24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_GPIO (1<<24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9 (1<<25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_MASK (1<<25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_SHIFT (25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_ALT (0<<25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_GPIO (1<<25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10 (1<<26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_MASK (1<<26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_SHIFT (26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_ALT (0<<26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_GPIO (1<<26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11 (1<<27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_MASK (1<<27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_SHIFT (27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_ALT (0<<27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_GPIO (1<<27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12 (1<<28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_MASK (1<<28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_SHIFT (28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_ALT (0<<28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_GPIO (1<<28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13 (1<<29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_MASK (1<<29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_SHIFT (29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_ALT (0<<29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_GPIO (1<<29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14 (1<<30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_MASK (1<<30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_SHIFT (30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_ALT (0<<30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_GPIO (1<<30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15 (1<<31)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_MASK (1<<31)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_SHIFT (31)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_ALT (0<<31)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_GPIO (1<<31)
+#define CFG_REGS_AP_GPIO_A_MODE(n) (((n)&0xFFFFFFFF)<<0)
+#define CFG_REGS_AP_GPIO_A_MODE_MASK (0xFFFFFFFF<<0)
+#define CFG_REGS_AP_GPIO_A_MODE_SHIFT (0)
+
+//AP_GPIO_B_Mode
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0 (1<<0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_MASK (1<<0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_SHIFT (0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_ALT (0<<0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_GPIO (1<<0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1 (1<<1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_MASK (1<<1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_SHIFT (1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_ALT (0<<1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_GPIO (1<<1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2 (1<<2)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_MASK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_SHIFT (2)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_ALT (0<<2)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_GPIO (1<<2)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0 (1<<3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_MASK (1<<3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_SHIFT (3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_ALT (0<<3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_GPIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1 (1<<4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_MASK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_SHIFT (4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_ALT (0<<4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_GPIO (1<<4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2 (1<<5)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_MASK (1<<5)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_SHIFT (5)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_ALT (0<<5)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_GPIO (1<<5)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL (1<<6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_MASK (1<<6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_SHIFT (6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_ALT (0<<6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_GPIO (1<<6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA (1<<7)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_MASK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_SHIFT (7)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_ALT (0<<7)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_GPIO (1<<7)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS (1<<8)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_MASK (1<<8)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_SHIFT (8)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_ALT (0<<8)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_GPIO (1<<8)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS (1<<9)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_MASK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_SHIFT (9)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_ALT (0<<9)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_GPIO (1<<9)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST_MASK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST_SHIFT (10)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST_ALT (0<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST_GPIO (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_MASK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_SHIFT (11)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_ALT (0<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_GPIO (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_MASK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_SHIFT (12)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_ALT (0<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_GPIO (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_MASK (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_SHIFT (13)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_ALT (0<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_GPIO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_MASK (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_SHIFT (14)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_ALT (0<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_GPIO (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_MASK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_SHIFT (15)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_ALT (0<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_GPIO (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0 (1<<16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_MASK (1<<16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_SHIFT (16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_ALT (0<<16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_GPIO (1<<16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1 (1<<17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_MASK (1<<17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_SHIFT (17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_ALT (0<<17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_GPIO (1<<17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2 (1<<18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_MASK (1<<18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_SHIFT (18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_ALT (0<<18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_GPIO (1<<18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3 (1<<19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_MASK (1<<19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_SHIFT (19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_ALT (0<<19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_GPIO (1<<19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4 (1<<20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_MASK (1<<20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_SHIFT (20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_ALT (0<<20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_GPIO (1<<20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5 (1<<21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_MASK (1<<21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_SHIFT (21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_ALT (0<<21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_GPIO (1<<21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6 (1<<22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_MASK (1<<22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_SHIFT (22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_ALT (0<<22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_GPIO (1<<22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7 (1<<23)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_MASK (1<<23)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_SHIFT (23)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_ALT (0<<23)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_GPIO (1<<23)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0 (1<<24)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_MASK (1<<24)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_SHIFT (24)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_ALT (0<<24)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_GPIO (1<<24)
+#define CFG_REGS_MODE_AP_PIN_NFCLE (1<<25)
+#define CFG_REGS_MODE_AP_PIN_NFCLE_MASK (1<<25)
+#define CFG_REGS_MODE_AP_PIN_NFCLE_SHIFT (25)
+#define CFG_REGS_MODE_AP_PIN_NFCLE_ALT (0<<25)
+#define CFG_REGS_MODE_AP_PIN_NFCLE_GPIO (1<<25)
+#define CFG_REGS_MODE_AP_PIN_NFWEN (1<<26)
+#define CFG_REGS_MODE_AP_PIN_NFWEN_MASK (1<<26)
+#define CFG_REGS_MODE_AP_PIN_NFWEN_SHIFT (26)
+#define CFG_REGS_MODE_AP_PIN_NFWEN_ALT (0<<26)
+#define CFG_REGS_MODE_AP_PIN_NFWEN_GPIO (1<<26)
+#define CFG_REGS_MODE_AP_PIN_NFWPN (1<<27)
+#define CFG_REGS_MODE_AP_PIN_NFWPN_MASK (1<<27)
+#define CFG_REGS_MODE_AP_PIN_NFWPN_SHIFT (27)
+#define CFG_REGS_MODE_AP_PIN_NFWPN_ALT (0<<27)
+#define CFG_REGS_MODE_AP_PIN_NFWPN_GPIO (1<<27)
+#define CFG_REGS_MODE_AP_PIN_NFREN (1<<28)
+#define CFG_REGS_MODE_AP_PIN_NFREN_MASK (1<<28)
+#define CFG_REGS_MODE_AP_PIN_NFREN_SHIFT (28)
+#define CFG_REGS_MODE_AP_PIN_NFREN_ALT (0<<28)
+#define CFG_REGS_MODE_AP_PIN_NFREN_GPIO (1<<28)
+#define CFG_REGS_MODE_AP_PIN_NFRB  (1<<29)
+#define CFG_REGS_MODE_AP_PIN_NFRB_MASK (1<<29)
+#define CFG_REGS_MODE_AP_PIN_NFRB_SHIFT (29)
+#define CFG_REGS_MODE_AP_PIN_NFRB_ALT (0<<29)
+#define CFG_REGS_MODE_AP_PIN_NFRB_GPIO (1<<29)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL (1<<30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_MASK (1<<30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_SHIFT (30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_ALT (0<<30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_GPIO (1<<30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA (1<<31)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_MASK (1<<31)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_SHIFT (31)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_ALT (0<<31)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_GPIO (1<<31)
+#define CFG_REGS_AP_GPIO_B_MODE(n) (((n)&0xFFFFFFFF)<<0)
+#define CFG_REGS_AP_GPIO_B_MODE_MASK (0xFFFFFFFF<<0)
+#define CFG_REGS_AP_GPIO_B_MODE_SHIFT (0)
+
+//AP_GPIO_D_Mode
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD (1<<0)
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_MASK (1<<0)
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_SHIFT (0)
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_ALT (0<<0)
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_GPIO (1<<0)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD (1<<1)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_MASK (1<<1)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_SHIFT (1)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_ALT (0<<1)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_GPIO (1<<1)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS (1<<2)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_MASK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_SHIFT (2)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_ALT (0<<2)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_GPIO (1<<2)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS (1<<3)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_MASK (1<<3)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_SHIFT (3)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_ALT (0<<3)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_GPIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_NFDQS (1<<4)
+#define CFG_REGS_MODE_AP_PIN_NFDQS_MASK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_NFDQS_SHIFT (4)
+#define CFG_REGS_MODE_AP_PIN_NFDQS_ALT (0<<4)
+#define CFG_REGS_MODE_AP_PIN_NFDQS_GPIO (1<<4)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN (1<<5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_MASK (1<<5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_SHIFT (5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_ALT (0<<5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_GPIO (1<<5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP (1<<6)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_MASK (1<<6)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_SHIFT (6)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_ALT (0<<6)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_GPIO (1<<6)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN (1<<7)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN_MASK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN_SHIFT (7)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN_ALT (0<<7)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN_GPIO (1<<7)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1 (1<<8)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1_MASK (1<<8)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1_SHIFT (8)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1_ALT (0<<8)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1_GPIO (1<<8)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2 (1<<9)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2_MASK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2_SHIFT (9)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2_ALT (0<<9)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2_GPIO (1<<9)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3 (1<<10)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3_MASK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3_SHIFT (10)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3_ALT (0<<10)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3_GPIO (1<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_MASK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_SHIFT (11)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_ALT (0<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_GPIO (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_MASK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_SHIFT (12)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_ALT (0<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_GPIO (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0 (1<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_MASK (1<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_SHIFT (13)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_ALT (0<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_GPIO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1 (1<<14)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_MASK (1<<14)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_SHIFT (14)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_ALT (0<<14)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_GPIO (1<<14)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO (1<<15)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO_MASK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO_SHIFT (15)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO_ALT (0<<15)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO_GPIO (1<<15)
+#define CFG_REGS_AP_GPIO_D_MODE(n) (((n)&0xFFFF)<<0)
+#define CFG_REGS_AP_GPIO_D_MODE_MASK (0xFFFF<<0)
+#define CFG_REGS_AP_GPIO_D_MODE_SHIFT (0)
+
+//Alt_mux_select
+#define CFG_REGS_LCD_MODE_MASK     (3<<0)
+#define CFG_REGS_LCD_MODE_PARALLEL_16BIT (0<<0)
+#define CFG_REGS_LCD_MODE_DSI      (1<<0)
+#define CFG_REGS_LCD_MODE_RGB_24BIT (2<<0)
+#define CFG_REGS_LCD_MODE_RGB_16BIT (3<<0)
+#define CFG_REGS_SPI_LCD_MASK      (1<<2)
+#define CFG_REGS_SPI_LCD_NONE      (0<<2)
+#define CFG_REGS_SPI_LCD_SPI_LCD   (1<<2)
+#define CFG_REGS_CAM_I2C2_MASK     (1<<3)
+#define CFG_REGS_CAM_I2C2_CAM      (0<<3)
+#define CFG_REGS_CAM_I2C2_I2C2     (1<<3)
+#define CFG_REGS_CSI2_MASK         (3<<4)
+#define CFG_REGS_CSI2_PARALLEL_CAM (0<<4)
+#define CFG_REGS_CSI2_CSI2         (1<<4)
+#define CFG_REGS_CSI2_SPI_CAM      (2<<4)
+#define CFG_REGS_UART2_MASK        (1<<6)
+#define CFG_REGS_UART2_HOST_UART   (0<<6)
+#define CFG_REGS_UART2_UART2       (1<<6)
+#define CFG_REGS_UART1_8LINE_MASK  (1<<7)
+#define CFG_REGS_UART1_8LINE_UART2 (0<<7)
+#define CFG_REGS_UART1_8LINE_UART1_8_LINE (1<<7)
+#define CFG_REGS_DAI_MASK          (3<<8)
+#define CFG_REGS_DAI_I2S           (0<<8)
+#define CFG_REGS_DAI_DAI           (1<<8)
+#define CFG_REGS_DAI_DAI_SIMPLE    (2<<8)
+#define CFG_REGS_KEYIN_3_MASK      (1<<10)
+#define CFG_REGS_KEYIN_3_SPI2_CS_1 (0<<10)
+#define CFG_REGS_KEYIN_3_KEYIN_3   (1<<10)
+#define CFG_REGS_LPSCO_1_MASK      (1<<11)
+#define CFG_REGS_LPSCO_1_KEYIN_4   (0<<11)
+#define CFG_REGS_LPSCO_1_LPSCO_1   (1<<11)
+#define CFG_REGS_SPI1_CS_2_MASK    (1<<12)
+#define CFG_REGS_SPI1_CS_2_KEYIN_1 (0<<12)
+#define CFG_REGS_SPI1_CS_2_SPI1_CS_2 (1<<12)
+#define CFG_REGS_I2S_DI_2_MASK     (1<<13)
+#define CFG_REGS_I2S_DI_2_KEYIN_2  (0<<13)
+#define CFG_REGS_I2S_DI_2_I2S_DI_2 (1<<13)
+#define CFG_REGS_TCO_0_MASK        (1<<14)
+#define CFG_REGS_TCO_0_KEYOUT_0    (0<<14)
+#define CFG_REGS_TCO_0_TCO_0       (1<<14)
+#define CFG_REGS_TCO_1_MASK        (1<<15)
+#define CFG_REGS_TCO_1_KEYOUT_1    (0<<15)
+#define CFG_REGS_TCO_1_TCO_1       (1<<15)
+#define CFG_REGS_TCO_2_MASK        (1<<16)
+#define CFG_REGS_TCO_2_KEYOUT_2    (0<<16)
+#define CFG_REGS_TCO_2_TCO_2       (1<<16)
+#define CFG_REGS_KEYOUT_3_4_MASK   (1<<17)
+#define CFG_REGS_KEYOUT_3_4_I2C3   (0<<17)
+#define CFG_REGS_KEYOUT_3_4_KEYOUT_3_4 (1<<17)
+#define CFG_REGS_KEYOUT_6_MASK     (1<<18)
+#define CFG_REGS_KEYOUT_6_UART2_RTS (0<<18)
+#define CFG_REGS_KEYOUT_6_KEYOUT_6 (1<<18)
+#define CFG_REGS_KEYOUT_7_MASK     (1<<19)
+#define CFG_REGS_KEYOUT_7_UART1_RTS (0<<19)
+#define CFG_REGS_KEYOUT_7_KEYOUT_7 (1<<19)
+#define CFG_REGS_GPO_0_MASK        (3<<20)
+#define CFG_REGS_GPO_0_GPO_0       (0<<20)
+#define CFG_REGS_GPO_0_PWT         (1<<20)
+#define CFG_REGS_GPO_0_KEYIN_5     (2<<20)
+#define CFG_REGS_GPO_1_MASK        (3<<22)
+#define CFG_REGS_GPO_1_GPO_1       (0<<22)
+#define CFG_REGS_GPO_1_LPG         (1<<22)
+#define CFG_REGS_GPO_1_KEYOUT_5    (2<<22)
+#define CFG_REGS_GPO_2_MASK        (3<<24)
+#define CFG_REGS_GPO_2_GPO_2       (0<<24)
+#define CFG_REGS_GPO_2_PWL_1       (1<<24)
+#define CFG_REGS_GPO_2_CLK_32K     (2<<24)
+#define CFG_REGS_GPO_3_MASK        (1<<26)
+#define CFG_REGS_GPO_3_LCD_CS_1    (0<<26)
+#define CFG_REGS_GPO_3_GPO_3       (1<<26)
+#define CFG_REGS_GPO_4_MASK        (1<<27)
+#define CFG_REGS_GPO_4_LCD_CS_0    (0<<27)
+#define CFG_REGS_GPO_4_GPO_4       (1<<27)
+#define CFG_REGS_CLK_OUT_MASK      (1<<28)
+#define CFG_REGS_CLK_OUT_HST_CLK   (0<<28)
+#define CFG_REGS_CLK_OUT_CLK_OUT   (1<<28)
+#define CFG_REGS_DEBUG_MASK        (1<<29)
+#define CFG_REGS_DEBUG_NONE        (0<<29)
+#define CFG_REGS_DEBUG_DEBUG_MONITOR (1<<29)
+#define CFG_REGS_AP_SPI1_MASK      (1<<30)
+#define CFG_REGS_AP_SPI1_BB_SPI1   (0<<30)
+#define CFG_REGS_AP_SPI1_AP_SPI1   (1<<30)
+#define CFG_REGS_RGB_CAM_MASK      (1<<31)
+#define CFG_REGS_RGB_CAM_DISABLE   (0<<31)
+#define CFG_REGS_RGB_CAM_ENABLE    (1<<31)
+
+//IO_Drive1_Select
+#define CFG_REGS_DDR_DRIVE_MASK    (7<<0)
+#define CFG_REGS_DDR_DRIVE_FAST_AND_MOST_WEAK (7<<0)
+#define CFG_REGS_DDR_DRIVE_FAST_AND_WEAK (6<<0)
+#define CFG_REGS_DDR_DRIVE_FAST_AND_STRONG (5<<0)
+#define CFG_REGS_DDR_DRIVE_FAST_AND_MOST_STRONG (4<<0)
+#define CFG_REGS_DDR_DRIVE_SLOW_AND_MOST_WEAK (3<<0)
+#define CFG_REGS_DDR_DRIVE_SLOW_AND_WEAK (2<<0)
+#define CFG_REGS_DDR_DRIVE_SLOW_AND_STRONG (1<<0)
+#define CFG_REGS_DDR_DRIVE_SLOW_AND_MOST_STRONG (0<<0)
+#define CFG_REGS_PSRAM1_DRIVE_MASK (7<<3)
+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_MOST_WEAK (7<<3)
+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_WEAK (6<<3)
+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_STRONG (5<<3)
+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_MOST_STRONG (4<<3)
+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_MOST_WEAK (3<<3)
+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_WEAK (2<<3)
+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_STRONG (1<<3)
+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_MOST_STRONG (0<<3)
+#define CFG_REGS_PSRAM2_DRIVE_MASK (7<<6)
+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_MOST_WEAK (7<<6)
+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_WEAK (6<<6)
+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_STRONG (5<<6)
+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_MOST_STRONG (4<<6)
+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_MOST_WEAK (3<<6)
+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_WEAK (2<<6)
+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_STRONG (1<<6)
+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_MOST_STRONG (0<<6)
+#define CFG_REGS_NFLSH_DRIVE_MASK  (7<<9)
+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_MOST_WEAK (7<<9)
+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_WEAK (6<<9)
+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_STRONG (5<<9)
+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_MOST_STRONG (4<<9)
+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_MOST_WEAK (3<<9)
+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_WEAK (2<<9)
+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_STRONG (1<<9)
+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_MOST_STRONG (0<<9)
+#define CFG_REGS_LCD1_DRIVE_MASK   (7<<12)
+#define CFG_REGS_LCD1_DRIVE_FAST_AND_MOST_WEAK (7<<12)
+#define CFG_REGS_LCD1_DRIVE_FAST_AND_WEAK (6<<12)
+#define CFG_REGS_LCD1_DRIVE_FAST_AND_STRONG (5<<12)
+#define CFG_REGS_LCD1_DRIVE_FAST_AND_MOST_STRONG (4<<12)
+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_MOST_WEAK (3<<12)
+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_WEAK (2<<12)
+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_STRONG (1<<12)
+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_MOST_STRONG (0<<12)
+#define CFG_REGS_LCD2_DRIVE_MASK   (7<<15)
+#define CFG_REGS_LCD2_DRIVE_FAST_AND_MOST_WEAK (7<<15)
+#define CFG_REGS_LCD2_DRIVE_FAST_AND_WEAK (6<<15)
+#define CFG_REGS_LCD2_DRIVE_FAST_AND_STRONG (5<<15)
+#define CFG_REGS_LCD2_DRIVE_FAST_AND_MOST_STRONG (4<<15)
+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_MOST_WEAK (3<<15)
+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_WEAK (2<<15)
+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_STRONG (1<<15)
+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_MOST_STRONG (0<<15)
+#define CFG_REGS_SDAT1_DRIVE_MASK  (7<<18)
+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_MOST_WEAK (7<<18)
+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_WEAK (6<<18)
+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_STRONG (5<<18)
+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_MOST_STRONG (4<<18)
+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_MOST_WEAK (3<<18)
+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_WEAK (2<<18)
+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_STRONG (1<<18)
+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_MOST_STRONG (0<<18)
+#define CFG_REGS_SDAT2_DRIVE_MASK  (7<<21)
+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_MOST_WEAK (7<<21)
+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_WEAK (6<<21)
+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_STRONG (5<<21)
+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_MOST_STRONG (4<<21)
+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_MOST_WEAK (3<<21)
+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_WEAK (2<<21)
+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_STRONG (1<<21)
+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_MOST_STRONG (0<<21)
+#define CFG_REGS_CAM_DRIVE_MASK    (3<<24)
+#define CFG_REGS_CAM_DRIVE_MOST_STRONG (0<<24)
+#define CFG_REGS_CAM_DRIVE_STRONG  (1<<24)
+#define CFG_REGS_CAM_DRIVE_WEAK    (2<<24)
+#define CFG_REGS_CAM_DRIVE_MOST_WEAK (3<<24)
+#define CFG_REGS_SIM1_DRIVE_MASK   (3<<26)
+#define CFG_REGS_SIM1_DRIVE_MOST_STRONG (0<<26)
+#define CFG_REGS_SIM1_DRIVE_STRONG (1<<26)
+#define CFG_REGS_SIM1_DRIVE_WEAK   (2<<26)
+#define CFG_REGS_SIM1_DRIVE_MOST_WEAK (3<<26)
+#define CFG_REGS_SIM2_DRIVE_MASK   (3<<28)
+#define CFG_REGS_SIM2_DRIVE_MOST_STRONG (0<<28)
+#define CFG_REGS_SIM2_DRIVE_STRONG (1<<28)
+#define CFG_REGS_SIM2_DRIVE_WEAK   (2<<28)
+#define CFG_REGS_SIM2_DRIVE_MOST_WEAK (3<<28)
+#define CFG_REGS_SIM3_DRIVE_MASK   (3<<30)
+#define CFG_REGS_SIM3_DRIVE_MOST_STRONG (0<<30)
+#define CFG_REGS_SIM3_DRIVE_STRONG (1<<30)
+#define CFG_REGS_SIM3_DRIVE_WEAK   (2<<30)
+#define CFG_REGS_SIM3_DRIVE_MOST_WEAK (3<<30)
+
+//IO_Drive2_Select
+#define CFG_REGS_GPIO_DRIVE_MASK   (3<<0)
+#define CFG_REGS_GPIO_DRIVE_MOST_STRONG (0<<0)
+#define CFG_REGS_GPIO_DRIVE_STRONG (1<<0)
+#define CFG_REGS_GPIO_DRIVE_WEAK   (2<<0)
+#define CFG_REGS_GPIO_DRIVE_MOST_WEAK (3<<0)
+#define CFG_REGS_CAM2_DRIVE_MASK   (3<<2)
+#define CFG_REGS_CAM2_DRIVE_MOST_STRONG (0<<2)
+#define CFG_REGS_CAM2_DRIVE_STRONG (1<<2)
+#define CFG_REGS_CAM2_DRIVE_WEAK   (2<<2)
+#define CFG_REGS_CAM2_DRIVE_MOST_WEAK (3<<2)
+
+//RAM_DRIVE
+#define CFG_REGS_MBRAM_A(n)        (((n)&7)<<0)
+#define CFG_REGS_MBRAM_A_MASK      (7<<0)
+#define CFG_REGS_MBRAM_A_SHIFT     (0)
+#define CFG_REGS_MBRAM_W(n)        (((n)&3)<<3)
+#define CFG_REGS_MBRAM_W_MASK      (3<<3)
+#define CFG_REGS_MBRAM_W_SHIFT     (3)
+#define CFG_REGS_MBRAM_R           (1<<5)
+#define CFG_REGS_BBRAM_A(n)        (((n)&7)<<6)
+#define CFG_REGS_BBRAM_A_MASK      (7<<6)
+#define CFG_REGS_BBRAM_A_SHIFT     (6)
+#define CFG_REGS_BBRAM_W(n)        (((n)&3)<<9)
+#define CFG_REGS_BBRAM_W_MASK      (3<<9)
+#define CFG_REGS_BBRAM_W_SHIFT     (9)
+#define CFG_REGS_BBRAM_R           (1<<11)
+#define CFG_REGS_XP_A(n)           (((n)&7)<<12)
+#define CFG_REGS_XP_A_MASK         (7<<12)
+#define CFG_REGS_XP_A_SHIFT        (12)
+#define CFG_REGS_XP_W(n)           (((n)&3)<<15)
+#define CFG_REGS_XP_W_MASK         (3<<15)
+#define CFG_REGS_XP_W_SHIFT        (15)
+#define CFG_REGS_XP_R              (1<<17)
+#define CFG_REGS_BP_A(n)           (((n)&7)<<18)
+#define CFG_REGS_BP_A_MASK         (7<<18)
+#define CFG_REGS_BP_A_SHIFT        (18)
+#define CFG_REGS_BP_W(n)           (((n)&3)<<21)
+#define CFG_REGS_BP_W_MASK         (3<<21)
+#define CFG_REGS_BP_W_SHIFT        (21)
+#define CFG_REGS_BP_R              (1<<23)
+#define CFG_REGS_EV_A(n)           (((n)&7)<<24)
+#define CFG_REGS_EV_A_MASK         (7<<24)
+#define CFG_REGS_EV_A_SHIFT        (24)
+#define CFG_REGS_EV_W(n)           (((n)&3)<<27)
+#define CFG_REGS_EV_W_MASK         (3<<27)
+#define CFG_REGS_EV_W_SHIFT        (27)
+#define CFG_REGS_EV_R              (1<<29)
+
+//H2X_AP_Offset
+#define CFG_REGS_H2X_AP_OFFSET(n)  (((n)&0xFF)<<0)
+#define CFG_REGS_H2X_AP_OFFSET_MASK (0xFF<<0)
+#define CFG_REGS_H2X_AP_OFFSET_SHIFT (0)
+
+//H2X_DDR_Offset
+#define CFG_REGS_H2X_DDR_OFFSET(n) (((n)&0xFF)<<0)
+#define CFG_REGS_H2X_DDR_OFFSET_MASK (0xFF<<0)
+#define CFG_REGS_H2X_DDR_OFFSET_SHIFT (0)
+
+//audio_pd_set
+#define CFG_REGS_AU_DEEP_PD_N      (1<<0)
+#define CFG_REGS_AU_REF_PD_N       (1<<1)
+#define CFG_REGS_AU_MIC_PD_N       (1<<2)
+#define CFG_REGS_AU_AUXMIC_PD_N    (1<<3)
+#define CFG_REGS_AU_AD_PD_N        (1<<4)
+#define CFG_REGS_AU_DAC_PD_N       (1<<5)
+#define CFG_REGS_AU_DAC_RESET_N    (1<<8)
+#define CFG_REGS_AU_PLL_PU         (1<<16)
+
+//audio_pd_clr
+//#define CFG_REGS_AU_DEEP_PD_N    (1<<0)
+//#define CFG_REGS_AU_REF_PD_N     (1<<1)
+//#define CFG_REGS_AU_MIC_PD_N     (1<<2)
+//#define CFG_REGS_AU_AUXMIC_PD_N  (1<<3)
+//#define CFG_REGS_AU_AD_PD_N      (1<<4)
+//#define CFG_REGS_AU_DAC_PD_N     (1<<5)
+//#define CFG_REGS_AU_DAC_RESET_N  (1<<8)
+//#define CFG_REGS_AU_PLL_PU       (1<<16)
+
+//audio_sel_cfg
+#define CFG_REGS_AU_AUXMIC_SEL     (1<<0)
+#define CFG_REGS_AU_SPK_SEL        (1<<1)
+#define CFG_REGS_AU_SPK_MONO_SEL   (1<<2)
+#define CFG_REGS_AU_RCV_SEL        (1<<3)
+#define CFG_REGS_AU_HEAD_SEL       (1<<4)
+
+//audio_mic_cfg
+#define CFG_REGS_AU_MIC_GAIN(n)    (((n)&15)<<0)
+#define CFG_REGS_AU_MIC_GAIN_MASK  (15<<0)
+#define CFG_REGS_AU_MIC_GAIN_SHIFT (0)
+#define CFG_REGS_AU_MIC_MUTE_N     (1<<4)
+
+//audio_spk_cfg
+#define CFG_REGS_AU_SPK_GAIN(n)    (((n)&15)<<0)
+#define CFG_REGS_AU_SPK_GAIN_MASK  (15<<0)
+#define CFG_REGS_AU_SPK_GAIN_SHIFT (0)
+#define CFG_REGS_AU_SPK_MUTE_N     (1<<4)
+#define CFG_REGS_AU_SPK_VOC_GAIN_EN (1<<8)
+
+//audio_rcv_gain
+#define CFG_REGS_AU_RCV_GAIN(n)    (((n)&15)<<0)
+#define CFG_REGS_AU_RCV_GAIN_MASK  (15<<0)
+#define CFG_REGS_AU_RCV_GAIN_SHIFT (0)
+#define CFG_REGS_AU_RCV_VOC_GAIN_EN (1<<8)
+
+//audio_head_gain
+#define CFG_REGS_AU_HEAD_GAIN(n)   (((n)&15)<<0)
+#define CFG_REGS_AU_HEAD_GAIN_MASK (15<<0)
+#define CFG_REGS_AU_HEAD_GAIN_SHIFT (0)
+#define CFG_REGS_AU_HEAD_VOC_GAIN_EN (1<<8)
+
+//TSC_DATA
+#define CFG_REGS_TSC_X_VALUE_BIT(n) (((n)&0x3FF)<<0)
+#define CFG_REGS_TSC_X_VALUE_BIT_MASK (0x3FF<<0)
+#define CFG_REGS_TSC_X_VALUE_BIT_SHIFT (0)
+#define CFG_REGS_TSC_X_VALUE_VALID (1<<10)
+#define CFG_REGS_TSC_Y_VALUE_BIT(n) (((n)&0x3FF)<<11)
+#define CFG_REGS_TSC_Y_VALUE_BIT_MASK (0x3FF<<11)
+#define CFG_REGS_TSC_Y_VALUE_BIT_SHIFT (11)
+#define CFG_REGS_TSC_Y_VALUE_VALID (1<<21)
+
+//GPADC_DATA_CH
+#define CFG_REGS_GPADC_DATA(n)     (((n)&0x3FF)<<0)
+#define CFG_REGS_GPADC_DATA_MASK   (0x3FF<<0)
+#define CFG_REGS_GPADC_DATA_SHIFT  (0)
+#define CFG_REGS_GPADC_VALID       (1<<10)
+#define CFG_REGS_GPADC_CH_EN       (1<<31)
+
+//Alt_mux_select2
+#define CFG_REGS_UART1_SDIO2_MASK  (1<<0)
+#define CFG_REGS_UART1_SDIO2_SDIO2 (0<<0)
+#define CFG_REGS_UART1_SDIO2_UART1 (1<<0)
+#define CFG_REGS_JTAG_EN_MASK      (1<<1)
+#define CFG_REGS_JTAG_EN_DISABLE   (0<<1)
+#define CFG_REGS_JTAG_EN_ENABLE    (1<<1)
+#define CFG_REGS_LCD_RGB_17_16_MASK (1<<2)
+#define CFG_REGS_LCD_RGB_17_16_LCD_CS (0<<2)
+#define CFG_REGS_LCD_RGB_17_16_LCD_DATA (1<<2)
+#define CFG_REGS_CSI2_2_MASK       (3<<3)
+#define CFG_REGS_CSI2_2_PARALLEL_CAM (0<<3)
+#define CFG_REGS_CSI2_2_CSI2       (1<<3)
+#define CFG_REGS_CSI2_2_SPI_CAM    (2<<3)
+#define CFG_REGS_RGB_CAM_2_MASK    (1<<5)
+#define CFG_REGS_RGB_CAM_2_DISABLE (0<<5)
+#define CFG_REGS_RGB_CAM_2_ENABLE  (1<<5)
+#define CFG_REGS_MAC_EN_MASK       (1<<6)
+#define CFG_REGS_MAC_EN_DISABLE    (0<<6)
+#define CFG_REGS_MAC_EN_ENABLE     (1<<6)
+#define CFG_REGS_IOMUX_CFG_RESERVED(n) (((n)&0x1FFFFFF)<<7)
+
+//AP_GPIO_E_Mode
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_MASK (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_SHIFT (0)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_ALT (0<<0)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_GPIO (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA (1<<1)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_MASK (1<<1)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_SHIFT (1)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_ALT (0<<1)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_GPIO (1<<1)
+#define CFG_REGS_MODE_AP_PIN_CAM2_RST (1<<2)
+#define CFG_REGS_MODE_AP_PIN_CAM2_RST_MASK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_CAM2_RST_SHIFT (2)
+#define CFG_REGS_MODE_AP_PIN_CAM2_RST_ALT (0<<2)
+#define CFG_REGS_MODE_AP_PIN_CAM2_RST_GPIO (1<<2)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PDN (1<<3)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_MASK (1<<3)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_SHIFT (3)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_ALT (0<<3)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_GPIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_CAM2_CLK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_MASK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_SHIFT (4)
+#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_ALT (0<<4)
+#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_GPIO (1<<4)
+#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC (1<<5)
+#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_MASK (1<<5)
+#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_SHIFT (5)
+#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_ALT (0<<5)
+#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_GPIO (1<<5)
+#define CFG_REGS_MODE_AP_PIN_CAM2_HREF (1<<6)
+#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_MASK (1<<6)
+#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_SHIFT (6)
+#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_ALT (0<<6)
+#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_GPIO (1<<6)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_MASK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_SHIFT (7)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_ALT (0<<7)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_GPIO (1<<7)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0 (1<<8)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_MASK (1<<8)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_SHIFT (8)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_ALT (0<<8)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_GPIO (1<<8)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1 (1<<9)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_MASK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_SHIFT (9)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_ALT (0<<9)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_GPIO (1<<9)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2 (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_MASK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_SHIFT (10)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_ALT (0<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_GPIO (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3 (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_MASK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_SHIFT (11)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_ALT (0<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_GPIO (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4 (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_MASK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_SHIFT (12)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_ALT (0<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_GPIO (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5 (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_MASK (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_SHIFT (13)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_ALT (0<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_GPIO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6 (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_MASK (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_SHIFT (14)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_ALT (0<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_GPIO (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7 (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_MASK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_SHIFT (15)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_ALT (0<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_GPIO (1<<15)
+#define CFG_REGS_AP_GPIO_E_MODE(n) (((n)&0xFFFF)<<0)
+#define CFG_REGS_AP_GPIO_E_MODE_MASK (0xFFFF<<0)
+#define CFG_REGS_AP_GPIO_E_MODE_SHIFT (0)
+
+
+
+
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8850.h b/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8850.h
new file mode 100644
index 0000000000..046c2e872b
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8850.h
@@ -0,0 +1,1254 @@
+#ifndef _CFG_REGS_H_

+#define _CFG_REGS_H_

+

+#include <asm/arch/hardware.h>

+#include <asm/arch/rda_iomap.h>

+

+#ifdef CT_ASM

+#error "You are trying to use in an assembly code the normal H description of 'cfg_regs'."

+#endif

+

+

+

+// =============================================================================

+//  MACROS

+// =============================================================================

+#define PROD_ID                                 (0X8850)

+

+// ============================================================================

+// BB_GPIO_MAPPING_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// BB GPIO Map

+    BB_PIN_NONE_0                               = 0x00000000,

+    BB_PIN_1                                    = 0x00000001,

+    BB_PIN_2                                    = 0x00000002,

+    BB_PIN_3                                    = 0x00000003,

+    BB_PIN_4                                    = 0x00000004,

+    BB_PIN_5                                    = 0x00000005,

+    BB_PIN_UART1_RXD                            = 0x00000006,

+    BB_PIN_UART2_RXD                            = 0x00000007,

+    BB_PIN_UART2_TXD                            = 0x00000008,

+    BB_PIN_SSD1_CLK                             = 0x00000009,

+    BB_PIN_SSD1_CMD                             = 0x0000000A,

+    BB_PIN_SDAT1_0                              = 0x0000000B,

+    BB_PIN_SDAT1_1                              = 0x0000000C,

+    BB_PIN_SDAT1_2                              = 0x0000000D,

+    BB_PIN_SDAT1_3                              = 0x0000000E,

+    BB_PIN_SSD2_CLK                             = 0x0000000F,

+    BB_PIN_SSD2_CMD                             = 0x00000010,

+    BB_PIN_SDAT2_0                              = 0x00000011,

+    BB_PIN_SDAT2_1                              = 0x00000012,

+    BB_PIN_SDAT2_2                              = 0x00000013,

+    BB_PIN_SDAT2_3                              = 0x00000014,

+    BB_PIN_SPI1_CLK                             = 0x00000015,

+    BB_PIN_SPI1_CS_0                            = 0x00000016,

+    BB_PIN_SPI1_DIO                             = 0x00000017,

+    BB_PIN_SPI1_DI                              = 0x00000018,

+    BB_PIN_SIM2_RST                             = 0x00000019,

+    BB_PIN_SIM2_CLK                             = 0x0000001A,

+    BB_PIN_SIM2_DIO                             = 0x0000001B,

+    BB_PIN_SIM3_RST                             = 0x0000001C,

+    BB_PIN_SIM3_CLK                             = 0x0000001D,

+    BB_PIN_SIM3_DIO                             = 0x0000001E

+} BB_GPIO_MAPPING_T;

+

+#define BB_GPIO_NB                              (31)

+

+// ============================================================================

+// AP_GPIO_A_MAPPING_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// AP GPIO A Map

+    AP_PIN_I2C2_SCL                             = 0x00000000,

+    AP_PIN_I2C2_SDA                             = 0x00000001,

+    AP_PIN_SPI2_CLK                             = 0x00000002,

+    AP_PIN_SPI2_DIO                             = 0x00000003,

+    AP_PIN_SPI2_DI                              = 0x00000004,

+    AP_PIN_SPI2_CS_0                            = 0x00000005,

+    AP_PIN_SPI2_CS_1                            = 0x00000006,

+    AP_PIN_KEYIN_4                              = 0x00000007,

+    AP_PIN_CLK_OUT                              = 0x00000008,

+    AP_PIN_I2S_BCK                              = 0x00000009,

+    AP_PIN_I2S_LRCK                             = 0x0000000A,

+    AP_PIN_I2S_DI_0                             = 0x0000000B,

+    AP_PIN_I2S_DI_1                             = 0x0000000C,

+    AP_PIN_I2S_DO                               = 0x0000000D,

+    AP_PIN_UART1_TXD                            = 0x0000000E,

+    AP_PIN_UART1_CTS                            = 0x0000000F,

+    AP_PIN_UART1_RTS                            = 0x00000010,

+    AP_PIN_SPI1_CS_1                            = 0x00000011,

+    AP_PIN_LCD_WR                               = 0x00000012,

+    AP_PIN_LCD_RS                               = 0x00000013,

+    AP_PIN_LCD_RD                               = 0x00000014,

+    AP_PIN_LCD_FMARK                            = 0x00000015,

+    AP_PIN_LCD_DATA_6                           = 0x00000016,

+    AP_PIN_LCD_DATA_7                           = 0x00000017,

+    AP_PIN_LCD_DATA_8                           = 0x00000018,

+    AP_PIN_LCD_DATA_9                           = 0x00000019,

+    AP_PIN_LCD_DATA_10                          = 0x0000001A,

+    AP_PIN_LCD_DATA_11                          = 0x0000001B,

+    AP_PIN_LCD_DATA_12                          = 0x0000001C,

+    AP_PIN_LCD_DATA_13                          = 0x0000001D,

+    AP_PIN_LCD_DATA_14                          = 0x0000001E,

+    AP_PIN_LCD_DATA_15                          = 0x0000001F

+} AP_GPIO_A_MAPPING_T;

+

+#define AP_GPIO_A_NB                            (32)

+

+// ============================================================================

+// AP_GPIO_B_MAPPING_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// AP GPIO B Map

+    AP_PIN_KEYIN_0                              = 0x00000000,

+    AP_PIN_KEYIN_1                              = 0x00000001,

+    AP_PIN_KEYIN_2                              = 0x00000002,

+    AP_PIN_KEYOUT_0                             = 0x00000003,

+    AP_PIN_KEYOUT_1                             = 0x00000004,

+    AP_PIN_KEYOUT_2                             = 0x00000005,

+    AP_PIN_I2C3_SCL                             = 0x00000006,

+    AP_PIN_I2C3_SDA                             = 0x00000007,

+    AP_PIN_UART2_CTS                            = 0x00000008,

+    AP_PIN_UART2_RTS                            = 0x00000009,

+    AP_PIN_CAM_RST                              = 0x0000000A,

+    AP_PIN_CAM_PDN                              = 0x0000000B,

+    AP_PIN_CAM_CLK                              = 0x0000000C,

+    AP_PIN_CAM_VSYNC                            = 0x0000000D,

+    AP_PIN_CAM_HREF                             = 0x0000000E,

+    AP_PIN_CAM_PCLK                             = 0x0000000F,

+    AP_PIN_CAM_DATA_0                           = 0x00000010,

+    AP_PIN_CAM_DATA_1                           = 0x00000011,

+    AP_PIN_CAM_DATA_2                           = 0x00000012,

+    AP_PIN_CAM_DATA_3                           = 0x00000013,

+    AP_PIN_CAM_DATA_4                           = 0x00000014,

+    AP_PIN_CAM_DATA_5                           = 0x00000015,

+    AP_PIN_CAM_DATA_6                           = 0x00000016,

+    AP_PIN_CAM_DATA_7                           = 0x00000017,

+    AP_PIN_M_SPI_CS_0                           = 0x00000018,

+    AP_PIN_NFCLE                                = 0x00000019,

+    AP_PIN_NFWEN                                = 0x0000001A,

+    AP_PIN_NFWPN                                = 0x0000001B,

+    AP_PIN_NFREN                                = 0x0000001C,

+    AP_PIN_NFRB                                 = 0x0000001D,

+    AP_PIN_I2C1_SCL                             = 0x0000001E,

+    AP_PIN_I2C1_SDA                             = 0x0000001F

+} AP_GPIO_B_MAPPING_T;

+

+#define AP_GPIO_B_NB                            (32)

+

+// ============================================================================

+// AP_GPIO_D_MAPPING_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// AP GPIO D Map

+    AP_PIN_UART3_RXD                            = 0x00000000,

+    AP_PIN_UART3_TXD                            = 0x00000001,

+    AP_PIN_UART3_CTS                            = 0x00000002,

+    AP_PIN_UART3_RTS                            = 0x00000003,

+    AP_PIN_NFDQS                                = 0x00000004,

+    AP_PIN_VOLUME_DN                            = 0x00000005,

+    AP_PIN_VOLUME_UP                            = 0x00000006,

+    AP_PIN_PLUGIN                               = 0x00000007,

+    AP_PIN_NFD_8                                = 0x00000008,

+    AP_PIN_NFD_9                                = 0x00000009,

+    AP_PIN_NFD_10                               = 0x0000000A,

+    AP_PIN_NFD_11                               = 0x0000000B,

+    AP_PIN_NFD_12                               = 0x0000000C,

+    AP_PIN_NFD_13                               = 0x0000000D,

+    AP_PIN_NFD_14                               = 0x0000000E,

+    AP_PIN_NFD_15                               = 0x0000000F,

+    AP_PIN_LCD_DATA_16                          = 0x00000010,

+    AP_PIN_LCD_DATA_17                          = 0x00000011,

+    AP_PIN_LCD_DATA_18                          = 0x00000012,

+    AP_PIN_LCD_DATA_19                          = 0x00000013,

+    AP_PIN_LCD_DATA_20                          = 0x00000014,

+    AP_PIN_LCD_DATA_21                          = 0x00000015,

+    AP_PIN_LCD_DATA_22                          = 0x00000016,

+    AP_PIN_LCD_DATA_23                          = 0x00000017,

+    AP_PIN_NFCEN_1                              = 0x00000018,

+    AP_PIN_NFCEN_2                              = 0x00000019,

+    AP_PIN_NFCEN_3                              = 0x0000001A,

+    AP_PIN_I2S2_BCK                             = 0x0000001B,

+    AP_PIN_I2S2_LRCK                            = 0x0000001C,

+    AP_PIN_I2S2_DI_0                            = 0x0000001D,

+    AP_PIN_I2S2_DI_1                            = 0x0000001E,

+    AP_PIN_I2S2_DO                              = 0x0000001F

+} AP_GPIO_D_MAPPING_T;

+

+#define AP_GPIO_D_NB                            (32)

+

+// =============================================================================

+//  TYPES

+// =============================================================================

+

+// ============================================================================

+// CFG_REGS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef volatile struct

+{

+    REG32                          CHIP_ID;                      //0x00000000

+    /// This register contain the synthesis date and version

+    REG32                          Build_Version;                //0x00000004

+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting

+    /// bit n to '0' selects Alt.

+    REG32                          BB_GPIO_Mode;                 //0x00000008

+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting

+    /// bit n to '0' selects Alt.

+    REG32                          AP_GPIO_A_Mode;               //0x0000000C

+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting

+    /// bit n to '0' selects Alt.

+    REG32                          AP_GPIO_B_Mode;               //0x00000010

+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting

+    /// bit n to '0' selects Alt.

+    REG32                          AP_GPIO_D_Mode;               //0x00000014

+    REG32                          Alt_mux_select;               //0x00000018

+    REG32                          IO_Drive1_Select;             //0x0000001C

+    REG32                          IO_Drive2_Select;             //0x00000020

+    REG32                          RAM_DRIVE;                    //0x00000024

+    REG32                          H2X_AP_Offset;                //0x00000028

+    REG32                          H2X_DDR_Offset;               //0x0000002C

+    REG32                          audio_pd_set;                 //0x00000030

+    REG32                          audio_pd_clr;                 //0x00000034

+    REG32                          audio_sel_cfg;                //0x00000038

+    REG32                          audio_mic_cfg;                //0x0000003C

+    REG32                          audio_spk_cfg;                //0x00000040

+    REG32                          audio_rcv_gain;               //0x00000044

+    REG32                          audio_head_gain;              //0x00000048

+    REG32                          TSC_DATA;                     //0x0000004C

+    REG32                          GPADC_DATA_CH[8];             //0x00000050

+    REG32                          Alt_mux_select2;              //0x00000070

+    REG32                          Mem_mode_Sel;                 //0x00000074

+} HWP_CFG_REGS_T;

+

+#define hwp_configRegs             ((HWP_CFG_REGS_T*)(RDA_CFG_REGS_BASE))

+

+

+//CHIP_ID

+#define CFG_REGS_METAL_ID(n)       (((n)&0xFFF)<<0)

+#define CFG_REGS_METAL_ID_MASK     (0xFFF<<0)

+#define CFG_REGS_METAL_ID_SHIFT    (0)

+#define CFG_REGS_BOND_ID(n)        (((n)&7)<<12)

+#define CFG_REGS_BOND_ID_MASK      (7<<12)

+#define CFG_REGS_BOND_ID_SHIFT     (12)

+#define CFG_REGS_PROD_ID(n)        (((n)&0xFFFF)<<16)

+#define CFG_REGS_PROD_ID_MASK      (0xFFFF<<16)

+#define CFG_REGS_PROD_ID_SHIFT     (16)

+

+//Build_Version

+#define CFG_REGS_MAJOR(n)          (((n)&15)<<28)

+#define CFG_REGS_YEAR(n)           (((n)&15)<<24)

+#define CFG_REGS_MONTH(n)          (((n)&0xFF)<<16)

+#define CFG_REGS_DAY(n)            (((n)&0xFF)<<8)

+#define CFG_REGS_BUILD_STYLE_FPGA  (0<<4)

+#define CFG_REGS_BUILD_STYLE_CHIP  (1<<4)

+#define CFG_REGS_BUILD_STYLE_FPGA_USB (2<<4)

+#define CFG_REGS_BUILD_STYLE_FPGA_GSM (3<<4)

+#define CFG_REGS_BUILD_REVISION(n) (((n)&15)<<0)

+

+//BB_GPIO_Mode

+#define CFG_REGS_MODE_BB_PIN_NONE_0 (1<<0)

+#define CFG_REGS_MODE_BB_PIN_NONE_0_MASK (1<<0)

+#define CFG_REGS_MODE_BB_PIN_NONE_0_SHIFT (0)

+#define CFG_REGS_MODE_BB_PIN_NONE_0_ALT (0<<0)

+#define CFG_REGS_MODE_BB_PIN_NONE_0_GPIO (1<<0)

+#define CFG_REGS_MODE_BB_PIN_1     (1<<1)

+#define CFG_REGS_MODE_BB_PIN_1_MASK (1<<1)

+#define CFG_REGS_MODE_BB_PIN_1_SHIFT (1)

+#define CFG_REGS_MODE_BB_PIN_1_ALT (0<<1)

+#define CFG_REGS_MODE_BB_PIN_1_GPIO (1<<1)

+#define CFG_REGS_MODE_BB_PIN_2     (1<<2)

+#define CFG_REGS_MODE_BB_PIN_2_MASK (1<<2)

+#define CFG_REGS_MODE_BB_PIN_2_SHIFT (2)

+#define CFG_REGS_MODE_BB_PIN_2_ALT (0<<2)

+#define CFG_REGS_MODE_BB_PIN_2_GPIO (1<<2)

+#define CFG_REGS_MODE_BB_PIN_3     (1<<3)

+#define CFG_REGS_MODE_BB_PIN_3_MASK (1<<3)

+#define CFG_REGS_MODE_BB_PIN_3_SHIFT (3)

+#define CFG_REGS_MODE_BB_PIN_3_ALT (0<<3)

+#define CFG_REGS_MODE_BB_PIN_3_GPIO (1<<3)

+#define CFG_REGS_MODE_BB_PIN_4     (1<<4)

+#define CFG_REGS_MODE_BB_PIN_4_MASK (1<<4)

+#define CFG_REGS_MODE_BB_PIN_4_SHIFT (4)

+#define CFG_REGS_MODE_BB_PIN_4_ALT (0<<4)

+#define CFG_REGS_MODE_BB_PIN_4_GPIO (1<<4)

+#define CFG_REGS_MODE_BB_PIN_5     (1<<5)

+#define CFG_REGS_MODE_BB_PIN_5_MASK (1<<5)

+#define CFG_REGS_MODE_BB_PIN_5_SHIFT (5)

+#define CFG_REGS_MODE_BB_PIN_5_ALT (0<<5)

+#define CFG_REGS_MODE_BB_PIN_5_GPIO (1<<5)

+#define CFG_REGS_MODE_BB_PIN_UART1_RXD (1<<6)

+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_MASK (1<<6)

+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_SHIFT (6)

+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_ALT (0<<6)

+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_GPIO (1<<6)

+#define CFG_REGS_MODE_BB_PIN_UART2_RXD (1<<7)

+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_MASK (1<<7)

+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_SHIFT (7)

+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_ALT (0<<7)

+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_GPIO (1<<7)

+#define CFG_REGS_MODE_BB_PIN_UART2_TXD (1<<8)

+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_MASK (1<<8)

+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_SHIFT (8)

+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_ALT (0<<8)

+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_GPIO (1<<8)

+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK (1<<9)

+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_MASK (1<<9)

+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_SHIFT (9)

+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_ALT (0<<9)

+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_GPIO (1<<9)

+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD (1<<10)

+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_MASK (1<<10)

+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_SHIFT (10)

+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_ALT (0<<10)

+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_GPIO (1<<10)

+#define CFG_REGS_MODE_BB_PIN_SDAT1_0 (1<<11)

+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_MASK (1<<11)

+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_SHIFT (11)

+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_ALT (0<<11)

+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_GPIO (1<<11)

+#define CFG_REGS_MODE_BB_PIN_SDAT1_1 (1<<12)

+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_MASK (1<<12)

+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_SHIFT (12)

+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_ALT (0<<12)

+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_GPIO (1<<12)

+#define CFG_REGS_MODE_BB_PIN_SDAT1_2 (1<<13)

+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_MASK (1<<13)

+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_SHIFT (13)

+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_ALT (0<<13)

+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_GPIO (1<<13)

+#define CFG_REGS_MODE_BB_PIN_SDAT1_3 (1<<14)

+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_MASK (1<<14)

+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_SHIFT (14)

+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_ALT (0<<14)

+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_GPIO (1<<14)

+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK (1<<15)

+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_MASK (1<<15)

+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_SHIFT (15)

+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_ALT (0<<15)

+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_GPIO (1<<15)

+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD (1<<16)

+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_MASK (1<<16)

+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_SHIFT (16)

+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_ALT (0<<16)

+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_GPIO (1<<16)

+#define CFG_REGS_MODE_BB_PIN_SDAT2_0 (1<<17)

+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_MASK (1<<17)

+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_SHIFT (17)

+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_ALT (0<<17)

+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_GPIO (1<<17)

+#define CFG_REGS_MODE_BB_PIN_SDAT2_1 (1<<18)

+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_MASK (1<<18)

+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_SHIFT (18)

+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_ALT (0<<18)

+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_GPIO (1<<18)

+#define CFG_REGS_MODE_BB_PIN_SDAT2_2 (1<<19)

+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_MASK (1<<19)

+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_SHIFT (19)

+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_ALT (0<<19)

+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_GPIO (1<<19)

+#define CFG_REGS_MODE_BB_PIN_SDAT2_3 (1<<20)

+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_MASK (1<<20)

+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_SHIFT (20)

+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_ALT (0<<20)

+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_GPIO (1<<20)

+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK (1<<21)

+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_MASK (1<<21)

+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_SHIFT (21)

+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_ALT (0<<21)

+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_GPIO (1<<21)

+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0 (1<<22)

+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_MASK (1<<22)

+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_SHIFT (22)

+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_ALT (0<<22)

+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_GPIO (1<<22)

+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO (1<<23)

+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_MASK (1<<23)

+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_SHIFT (23)

+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_ALT (0<<23)

+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_GPIO (1<<23)

+#define CFG_REGS_MODE_BB_PIN_SPI1_DI (1<<24)

+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_MASK (1<<24)

+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_SHIFT (24)

+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_ALT (0<<24)

+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_GPIO (1<<24)

+#define CFG_REGS_MODE_BB_PIN_SIM2_RST (1<<25)

+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_MASK (1<<25)

+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_SHIFT (25)

+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_ALT (0<<25)

+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_GPIO (1<<25)

+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK (1<<26)

+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_MASK (1<<26)

+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_SHIFT (26)

+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_ALT (0<<26)

+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_GPIO (1<<26)

+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO (1<<27)

+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_MASK (1<<27)

+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_SHIFT (27)

+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_ALT (0<<27)

+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_GPIO (1<<27)

+#define CFG_REGS_MODE_BB_PIN_SIM3_RST (1<<28)

+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_MASK (1<<28)

+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_SHIFT (28)

+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_ALT (0<<28)

+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_GPIO (1<<28)

+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK (1<<29)

+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_MASK (1<<29)

+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_SHIFT (29)

+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_ALT (0<<29)

+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_GPIO (1<<29)

+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO (1<<30)

+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_MASK (1<<30)

+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_SHIFT (30)

+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_ALT (0<<30)

+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_GPIO (1<<30)

+#define CFG_REGS_BB_GPIO_MODE(n)   (((n)&0x7FFFFFFF)<<0)

+#define CFG_REGS_BB_GPIO_MODE_MASK (0x7FFFFFFF<<0)

+#define CFG_REGS_BB_GPIO_MODE_SHIFT (0)

+

+//AP_GPIO_A_Mode

+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL (1<<0)

+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_MASK (1<<0)

+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_SHIFT (0)

+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_ALT (0<<0)

+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_GPIO (1<<0)

+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA (1<<1)

+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_MASK (1<<1)

+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_SHIFT (1)

+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_ALT (0<<1)

+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_GPIO (1<<1)

+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK (1<<2)

+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_MASK (1<<2)

+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_SHIFT (2)

+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_ALT (0<<2)

+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_GPIO (1<<2)

+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO (1<<3)

+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_MASK (1<<3)

+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_SHIFT (3)

+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_ALT (0<<3)

+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_GPIO (1<<3)

+#define CFG_REGS_MODE_AP_PIN_SPI2_DI (1<<4)

+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_MASK (1<<4)

+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_SHIFT (4)

+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_ALT (0<<4)

+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_GPIO (1<<4)

+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0 (1<<5)

+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_MASK (1<<5)

+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_SHIFT (5)

+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_ALT (0<<5)

+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_GPIO (1<<5)

+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1 (1<<6)

+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_MASK (1<<6)

+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_SHIFT (6)

+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_ALT (0<<6)

+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_GPIO (1<<6)

+#define CFG_REGS_MODE_AP_PIN_KEYIN_4 (1<<7)

+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_MASK (1<<7)

+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_SHIFT (7)

+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_ALT (0<<7)

+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_GPIO (1<<7)

+#define CFG_REGS_MODE_AP_PIN_CLK_OUT (1<<8)

+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_MASK (1<<8)

+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_SHIFT (8)

+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_ALT (0<<8)

+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_GPIO (1<<8)

+#define CFG_REGS_MODE_AP_PIN_I2S_BCK (1<<9)

+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_MASK (1<<9)

+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_SHIFT (9)

+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_ALT (0<<9)

+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_GPIO (1<<9)

+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK (1<<10)

+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_MASK (1<<10)

+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_SHIFT (10)

+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_ALT (0<<10)

+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_GPIO (1<<10)

+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0 (1<<11)

+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_MASK (1<<11)

+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_SHIFT (11)

+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_ALT (0<<11)

+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_GPIO (1<<11)

+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1 (1<<12)

+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_MASK (1<<12)

+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_SHIFT (12)

+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_ALT (0<<12)

+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_GPIO (1<<12)

+#define CFG_REGS_MODE_AP_PIN_I2S_DO (1<<13)

+#define CFG_REGS_MODE_AP_PIN_I2S_DO_MASK (1<<13)

+#define CFG_REGS_MODE_AP_PIN_I2S_DO_SHIFT (13)

+#define CFG_REGS_MODE_AP_PIN_I2S_DO_ALT (0<<13)

+#define CFG_REGS_MODE_AP_PIN_I2S_DO_GPIO (1<<13)

+#define CFG_REGS_MODE_AP_PIN_UART1_TXD (1<<14)

+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_MASK (1<<14)

+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_SHIFT (14)

+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_ALT (0<<14)

+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_GPIO (1<<14)

+#define CFG_REGS_MODE_AP_PIN_UART1_CTS (1<<15)

+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_MASK (1<<15)

+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_SHIFT (15)

+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_ALT (0<<15)

+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_GPIO (1<<15)

+#define CFG_REGS_MODE_AP_PIN_UART1_RTS (1<<16)

+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_MASK (1<<16)

+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_SHIFT (16)

+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_ALT (0<<16)

+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_GPIO (1<<16)

+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1 (1<<17)

+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_MASK (1<<17)

+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_SHIFT (17)

+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_ALT (0<<17)

+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_GPIO (1<<17)

+#define CFG_REGS_MODE_AP_PIN_LCD_WR (1<<18)

+#define CFG_REGS_MODE_AP_PIN_LCD_WR_MASK (1<<18)

+#define CFG_REGS_MODE_AP_PIN_LCD_WR_SHIFT (18)

+#define CFG_REGS_MODE_AP_PIN_LCD_WR_ALT (0<<18)

+#define CFG_REGS_MODE_AP_PIN_LCD_WR_GPIO (1<<18)

+#define CFG_REGS_MODE_AP_PIN_LCD_RS (1<<19)

+#define CFG_REGS_MODE_AP_PIN_LCD_RS_MASK (1<<19)

+#define CFG_REGS_MODE_AP_PIN_LCD_RS_SHIFT (19)

+#define CFG_REGS_MODE_AP_PIN_LCD_RS_ALT (0<<19)

+#define CFG_REGS_MODE_AP_PIN_LCD_RS_GPIO (1<<19)

+#define CFG_REGS_MODE_AP_PIN_LCD_RD (1<<20)

+#define CFG_REGS_MODE_AP_PIN_LCD_RD_MASK (1<<20)

+#define CFG_REGS_MODE_AP_PIN_LCD_RD_SHIFT (20)

+#define CFG_REGS_MODE_AP_PIN_LCD_RD_ALT (0<<20)

+#define CFG_REGS_MODE_AP_PIN_LCD_RD_GPIO (1<<20)

+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK (1<<21)

+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_MASK (1<<21)

+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_SHIFT (21)

+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_ALT (0<<21)

+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_GPIO (1<<21)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6 (1<<22)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_MASK (1<<22)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_SHIFT (22)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_ALT (0<<22)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_GPIO (1<<22)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7 (1<<23)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_MASK (1<<23)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_SHIFT (23)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_ALT (0<<23)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_GPIO (1<<23)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8 (1<<24)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_MASK (1<<24)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_SHIFT (24)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_ALT (0<<24)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_GPIO (1<<24)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9 (1<<25)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_MASK (1<<25)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_SHIFT (25)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_ALT (0<<25)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_GPIO (1<<25)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10 (1<<26)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_MASK (1<<26)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_SHIFT (26)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_ALT (0<<26)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_GPIO (1<<26)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11 (1<<27)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_MASK (1<<27)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_SHIFT (27)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_ALT (0<<27)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_GPIO (1<<27)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12 (1<<28)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_MASK (1<<28)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_SHIFT (28)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_ALT (0<<28)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_GPIO (1<<28)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13 (1<<29)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_MASK (1<<29)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_SHIFT (29)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_ALT (0<<29)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_GPIO (1<<29)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14 (1<<30)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_MASK (1<<30)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_SHIFT (30)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_ALT (0<<30)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_GPIO (1<<30)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15 (1<<31)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_MASK (1<<31)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_SHIFT (31)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_ALT (0<<31)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_GPIO (1<<31)

+#define CFG_REGS_AP_GPIO_A_MODE(n) (((n)&0xFFFFFFFF)<<0)

+#define CFG_REGS_AP_GPIO_A_MODE_MASK (0xFFFFFFFF<<0)

+#define CFG_REGS_AP_GPIO_A_MODE_SHIFT (0)

+

+//AP_GPIO_B_Mode

+#define CFG_REGS_MODE_AP_PIN_KEYIN_0 (1<<0)

+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_MASK (1<<0)

+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_SHIFT (0)

+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_ALT (0<<0)

+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_GPIO (1<<0)

+#define CFG_REGS_MODE_AP_PIN_KEYIN_1 (1<<1)

+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_MASK (1<<1)

+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_SHIFT (1)

+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_ALT (0<<1)

+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_GPIO (1<<1)

+#define CFG_REGS_MODE_AP_PIN_KEYIN_2 (1<<2)

+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_MASK (1<<2)

+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_SHIFT (2)

+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_ALT (0<<2)

+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_GPIO (1<<2)

+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0 (1<<3)

+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_MASK (1<<3)

+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_SHIFT (3)

+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_ALT (0<<3)

+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_GPIO (1<<3)

+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1 (1<<4)

+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_MASK (1<<4)

+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_SHIFT (4)

+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_ALT (0<<4)

+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_GPIO (1<<4)

+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2 (1<<5)

+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_MASK (1<<5)

+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_SHIFT (5)

+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_ALT (0<<5)

+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_GPIO (1<<5)

+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL (1<<6)

+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_MASK (1<<6)

+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_SHIFT (6)

+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_ALT (0<<6)

+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_GPIO (1<<6)

+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA (1<<7)

+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_MASK (1<<7)

+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_SHIFT (7)

+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_ALT (0<<7)

+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_GPIO (1<<7)

+#define CFG_REGS_MODE_AP_PIN_UART2_CTS (1<<8)

+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_MASK (1<<8)

+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_SHIFT (8)

+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_ALT (0<<8)

+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_GPIO (1<<8)

+#define CFG_REGS_MODE_AP_PIN_UART2_RTS (1<<9)

+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_MASK (1<<9)

+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_SHIFT (9)

+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_ALT (0<<9)

+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_GPIO (1<<9)

+#define CFG_REGS_MODE_AP_PIN_CAM_RST (1<<10)

+#define CFG_REGS_MODE_AP_PIN_CAM_RST_MASK (1<<10)

+#define CFG_REGS_MODE_AP_PIN_CAM_RST_SHIFT (10)

+#define CFG_REGS_MODE_AP_PIN_CAM_RST_ALT (0<<10)

+#define CFG_REGS_MODE_AP_PIN_CAM_RST_GPIO (1<<10)

+#define CFG_REGS_MODE_AP_PIN_CAM_PDN (1<<11)

+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_MASK (1<<11)

+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_SHIFT (11)

+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_ALT (0<<11)

+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_GPIO (1<<11)

+#define CFG_REGS_MODE_AP_PIN_CAM_CLK (1<<12)

+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_MASK (1<<12)

+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_SHIFT (12)

+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_ALT (0<<12)

+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_GPIO (1<<12)

+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC (1<<13)

+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_MASK (1<<13)

+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_SHIFT (13)

+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_ALT (0<<13)

+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_GPIO (1<<13)

+#define CFG_REGS_MODE_AP_PIN_CAM_HREF (1<<14)

+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_MASK (1<<14)

+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_SHIFT (14)

+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_ALT (0<<14)

+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_GPIO (1<<14)

+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK (1<<15)

+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_MASK (1<<15)

+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_SHIFT (15)

+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_ALT (0<<15)

+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_GPIO (1<<15)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0 (1<<16)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_MASK (1<<16)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_SHIFT (16)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_ALT (0<<16)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_GPIO (1<<16)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1 (1<<17)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_MASK (1<<17)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_SHIFT (17)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_ALT (0<<17)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_GPIO (1<<17)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2 (1<<18)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_MASK (1<<18)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_SHIFT (18)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_ALT (0<<18)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_GPIO (1<<18)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3 (1<<19)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_MASK (1<<19)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_SHIFT (19)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_ALT (0<<19)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_GPIO (1<<19)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4 (1<<20)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_MASK (1<<20)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_SHIFT (20)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_ALT (0<<20)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_GPIO (1<<20)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5 (1<<21)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_MASK (1<<21)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_SHIFT (21)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_ALT (0<<21)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_GPIO (1<<21)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6 (1<<22)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_MASK (1<<22)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_SHIFT (22)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_ALT (0<<22)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_GPIO (1<<22)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7 (1<<23)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_MASK (1<<23)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_SHIFT (23)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_ALT (0<<23)

+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_GPIO (1<<23)

+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0 (1<<24)

+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_MASK (1<<24)

+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_SHIFT (24)

+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_ALT (0<<24)

+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_GPIO (1<<24)

+#define CFG_REGS_MODE_AP_PIN_NFCLE (1<<25)

+#define CFG_REGS_MODE_AP_PIN_NFCLE_MASK (1<<25)

+#define CFG_REGS_MODE_AP_PIN_NFCLE_SHIFT (25)

+#define CFG_REGS_MODE_AP_PIN_NFCLE_ALT (0<<25)

+#define CFG_REGS_MODE_AP_PIN_NFCLE_GPIO (1<<25)

+#define CFG_REGS_MODE_AP_PIN_NFWEN (1<<26)

+#define CFG_REGS_MODE_AP_PIN_NFWEN_MASK (1<<26)

+#define CFG_REGS_MODE_AP_PIN_NFWEN_SHIFT (26)

+#define CFG_REGS_MODE_AP_PIN_NFWEN_ALT (0<<26)

+#define CFG_REGS_MODE_AP_PIN_NFWEN_GPIO (1<<26)

+#define CFG_REGS_MODE_AP_PIN_NFWPN (1<<27)

+#define CFG_REGS_MODE_AP_PIN_NFWPN_MASK (1<<27)

+#define CFG_REGS_MODE_AP_PIN_NFWPN_SHIFT (27)

+#define CFG_REGS_MODE_AP_PIN_NFWPN_ALT (0<<27)

+#define CFG_REGS_MODE_AP_PIN_NFWPN_GPIO (1<<27)

+#define CFG_REGS_MODE_AP_PIN_NFREN (1<<28)

+#define CFG_REGS_MODE_AP_PIN_NFREN_MASK (1<<28)

+#define CFG_REGS_MODE_AP_PIN_NFREN_SHIFT (28)

+#define CFG_REGS_MODE_AP_PIN_NFREN_ALT (0<<28)

+#define CFG_REGS_MODE_AP_PIN_NFREN_GPIO (1<<28)

+#define CFG_REGS_MODE_AP_PIN_NFRB  (1<<29)

+#define CFG_REGS_MODE_AP_PIN_NFRB_MASK (1<<29)

+#define CFG_REGS_MODE_AP_PIN_NFRB_SHIFT (29)

+#define CFG_REGS_MODE_AP_PIN_NFRB_ALT (0<<29)

+#define CFG_REGS_MODE_AP_PIN_NFRB_GPIO (1<<29)

+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL (1<<30)

+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_MASK (1<<30)

+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_SHIFT (30)

+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_ALT (0<<30)

+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_GPIO (1<<30)

+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA (1<<31)

+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_MASK (1<<31)

+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_SHIFT (31)

+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_ALT (0<<31)

+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_GPIO (1<<31)

+#define CFG_REGS_AP_GPIO_B_MODE(n) (((n)&0xFFFFFFFF)<<0)

+#define CFG_REGS_AP_GPIO_B_MODE_MASK (0xFFFFFFFF<<0)

+#define CFG_REGS_AP_GPIO_B_MODE_SHIFT (0)

+

+//AP_GPIO_D_Mode

+#define CFG_REGS_MODE_AP_PIN_UART3_RXD (1<<0)

+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_MASK (1<<0)

+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_SHIFT (0)

+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_ALT (0<<0)

+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_GPIO (1<<0)

+#define CFG_REGS_MODE_AP_PIN_UART3_TXD (1<<1)

+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_MASK (1<<1)

+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_SHIFT (1)

+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_ALT (0<<1)

+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_GPIO (1<<1)

+#define CFG_REGS_MODE_AP_PIN_UART3_CTS (1<<2)

+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_MASK (1<<2)

+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_SHIFT (2)

+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_ALT (0<<2)

+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_GPIO (1<<2)

+#define CFG_REGS_MODE_AP_PIN_UART3_RTS (1<<3)

+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_MASK (1<<3)

+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_SHIFT (3)

+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_ALT (0<<3)

+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_GPIO (1<<3)

+#define CFG_REGS_MODE_AP_PIN_NFDQS (1<<4)

+#define CFG_REGS_MODE_AP_PIN_NFDQS_MASK (1<<4)

+#define CFG_REGS_MODE_AP_PIN_NFDQS_SHIFT (4)

+#define CFG_REGS_MODE_AP_PIN_NFDQS_ALT (0<<4)

+#define CFG_REGS_MODE_AP_PIN_NFDQS_GPIO (1<<4)

+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN (1<<5)

+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_MASK (1<<5)

+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_SHIFT (5)

+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_ALT (0<<5)

+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_GPIO (1<<5)

+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP (1<<6)

+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_MASK (1<<6)

+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_SHIFT (6)

+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_ALT (0<<6)

+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_GPIO (1<<6)

+#define CFG_REGS_MODE_AP_PIN_PLUGIN (1<<7)

+#define CFG_REGS_MODE_AP_PIN_PLUGIN_MASK (1<<7)

+#define CFG_REGS_MODE_AP_PIN_PLUGIN_SHIFT (7)

+#define CFG_REGS_MODE_AP_PIN_PLUGIN_ALT (0<<7)

+#define CFG_REGS_MODE_AP_PIN_PLUGIN_GPIO (1<<7)

+#define CFG_REGS_MODE_AP_PIN_NFD_8 (1<<8)

+#define CFG_REGS_MODE_AP_PIN_NFD_8_MASK (1<<8)

+#define CFG_REGS_MODE_AP_PIN_NFD_8_SHIFT (8)

+#define CFG_REGS_MODE_AP_PIN_NFD_8_ALT (0<<8)

+#define CFG_REGS_MODE_AP_PIN_NFD_8_GPIO (1<<8)

+#define CFG_REGS_MODE_AP_PIN_NFD_9 (1<<9)

+#define CFG_REGS_MODE_AP_PIN_NFD_9_MASK (1<<9)

+#define CFG_REGS_MODE_AP_PIN_NFD_9_SHIFT (9)

+#define CFG_REGS_MODE_AP_PIN_NFD_9_ALT (0<<9)

+#define CFG_REGS_MODE_AP_PIN_NFD_9_GPIO (1<<9)

+#define CFG_REGS_MODE_AP_PIN_NFD_10 (1<<10)

+#define CFG_REGS_MODE_AP_PIN_NFD_10_MASK (1<<10)

+#define CFG_REGS_MODE_AP_PIN_NFD_10_SHIFT (10)

+#define CFG_REGS_MODE_AP_PIN_NFD_10_ALT (0<<10)

+#define CFG_REGS_MODE_AP_PIN_NFD_10_GPIO (1<<10)

+#define CFG_REGS_MODE_AP_PIN_NFD_11 (1<<11)

+#define CFG_REGS_MODE_AP_PIN_NFD_11_MASK (1<<11)

+#define CFG_REGS_MODE_AP_PIN_NFD_11_SHIFT (11)

+#define CFG_REGS_MODE_AP_PIN_NFD_11_ALT (0<<11)

+#define CFG_REGS_MODE_AP_PIN_NFD_11_GPIO (1<<11)

+#define CFG_REGS_MODE_AP_PIN_NFD_12 (1<<12)

+#define CFG_REGS_MODE_AP_PIN_NFD_12_MASK (1<<12)

+#define CFG_REGS_MODE_AP_PIN_NFD_12_SHIFT (12)

+#define CFG_REGS_MODE_AP_PIN_NFD_12_ALT (0<<12)

+#define CFG_REGS_MODE_AP_PIN_NFD_12_GPIO (1<<12)

+#define CFG_REGS_MODE_AP_PIN_NFD_13 (1<<13)

+#define CFG_REGS_MODE_AP_PIN_NFD_13_MASK (1<<13)

+#define CFG_REGS_MODE_AP_PIN_NFD_13_SHIFT (13)

+#define CFG_REGS_MODE_AP_PIN_NFD_13_ALT (0<<13)

+#define CFG_REGS_MODE_AP_PIN_NFD_13_GPIO (1<<13)

+#define CFG_REGS_MODE_AP_PIN_NFD_14 (1<<14)

+#define CFG_REGS_MODE_AP_PIN_NFD_14_MASK (1<<14)

+#define CFG_REGS_MODE_AP_PIN_NFD_14_SHIFT (14)

+#define CFG_REGS_MODE_AP_PIN_NFD_14_ALT (0<<14)

+#define CFG_REGS_MODE_AP_PIN_NFD_14_GPIO (1<<14)

+#define CFG_REGS_MODE_AP_PIN_NFD_15 (1<<15)

+#define CFG_REGS_MODE_AP_PIN_NFD_15_MASK (1<<15)

+#define CFG_REGS_MODE_AP_PIN_NFD_15_SHIFT (15)

+#define CFG_REGS_MODE_AP_PIN_NFD_15_ALT (0<<15)

+#define CFG_REGS_MODE_AP_PIN_NFD_15_GPIO (1<<15)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_16 (1<<16)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_16_MASK (1<<16)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_16_SHIFT (16)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_16_ALT (0<<16)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_16_GPIO (1<<16)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_17 (1<<17)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_17_MASK (1<<17)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_17_SHIFT (17)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_17_ALT (0<<17)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_17_GPIO (1<<17)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_18 (1<<18)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_18_MASK (1<<18)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_18_SHIFT (18)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_18_ALT (0<<18)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_18_GPIO (1<<18)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_19 (1<<19)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_19_MASK (1<<19)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_19_SHIFT (19)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_19_ALT (0<<19)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_19_GPIO (1<<19)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_20 (1<<20)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_20_MASK (1<<20)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_20_SHIFT (20)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_20_ALT (0<<20)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_20_GPIO (1<<20)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_21 (1<<21)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_21_MASK (1<<21)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_21_SHIFT (21)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_21_ALT (0<<21)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_21_GPIO (1<<21)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_22 (1<<22)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_22_MASK (1<<22)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_22_SHIFT (22)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_22_ALT (0<<22)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_22_GPIO (1<<22)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_23 (1<<23)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_23_MASK (1<<23)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_23_SHIFT (23)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_23_ALT (0<<23)

+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_23_GPIO (1<<23)

+#define CFG_REGS_MODE_AP_PIN_NFCEN_1 (1<<24)

+#define CFG_REGS_MODE_AP_PIN_NFCEN_1_MASK (1<<24)

+#define CFG_REGS_MODE_AP_PIN_NFCEN_1_SHIFT (24)

+#define CFG_REGS_MODE_AP_PIN_NFCEN_1_ALT (0<<24)

+#define CFG_REGS_MODE_AP_PIN_NFCEN_1_GPIO (1<<24)

+#define CFG_REGS_MODE_AP_PIN_NFCEN_2 (1<<25)

+#define CFG_REGS_MODE_AP_PIN_NFCEN_2_MASK (1<<25)

+#define CFG_REGS_MODE_AP_PIN_NFCEN_2_SHIFT (25)

+#define CFG_REGS_MODE_AP_PIN_NFCEN_2_ALT (0<<25)

+#define CFG_REGS_MODE_AP_PIN_NFCEN_2_GPIO (1<<25)

+#define CFG_REGS_MODE_AP_PIN_NFCEN_3 (1<<26)

+#define CFG_REGS_MODE_AP_PIN_NFCEN_3_MASK (1<<26)

+#define CFG_REGS_MODE_AP_PIN_NFCEN_3_SHIFT (26)

+#define CFG_REGS_MODE_AP_PIN_NFCEN_3_ALT (0<<26)

+#define CFG_REGS_MODE_AP_PIN_NFCEN_3_GPIO (1<<26)

+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK (1<<27)

+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_MASK (1<<27)

+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_SHIFT (27)

+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_ALT (0<<27)

+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_GPIO (1<<27)

+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK (1<<28)

+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_MASK (1<<28)

+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_SHIFT (28)

+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_ALT (0<<28)

+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_GPIO (1<<28)

+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0 (1<<29)

+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_MASK (1<<29)

+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_SHIFT (29)

+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_ALT (0<<29)

+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_GPIO (1<<29)

+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1 (1<<30)

+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_MASK (1<<30)

+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_SHIFT (30)

+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_ALT (0<<30)

+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_GPIO (1<<30)

+#define CFG_REGS_MODE_AP_PIN_I2S2_DO (1<<31)

+#define CFG_REGS_MODE_AP_PIN_I2S2_DO_MASK (1<<31)

+#define CFG_REGS_MODE_AP_PIN_I2S2_DO_SHIFT (31)

+#define CFG_REGS_MODE_AP_PIN_I2S2_DO_ALT (0<<31)

+#define CFG_REGS_MODE_AP_PIN_I2S2_DO_GPIO (1<<31)

+#define CFG_REGS_AP_GPIO_D_MODE(n) (((n)&0xFFFFFFFF)<<0)

+#define CFG_REGS_AP_GPIO_D_MODE_MASK (0xFFFFFFFF<<0)

+#define CFG_REGS_AP_GPIO_D_MODE_SHIFT (0)

+

+//Alt_mux_select

+#define CFG_REGS_LCD_MODE_MASK     (3<<0)

+#define CFG_REGS_LCD_MODE_PARALLEL_16BIT (0<<0)

+#define CFG_REGS_LCD_MODE_DSI      (1<<0)

+#define CFG_REGS_LCD_MODE_RGB_24BIT (2<<0)

+#define CFG_REGS_LCD_MODE_RGB_16BIT (3<<0)

+#define CFG_REGS_SPI_LCD_MASK      (1<<2)

+#define CFG_REGS_SPI_LCD_NONE      (0<<2)

+#define CFG_REGS_SPI_LCD_SPI_LCD   (1<<2)

+#define CFG_REGS_CAM_I2C2_MASK     (1<<3)

+#define CFG_REGS_CAM_I2C2_CAM      (0<<3)

+#define CFG_REGS_CAM_I2C2_I2C2     (1<<3)

+#define CFG_REGS_CSI2_MASK         (3<<4)

+#define CFG_REGS_CSI2_PARALLEL_CAM (0<<4)

+#define CFG_REGS_CSI2_CSI2         (1<<4)

+#define CFG_REGS_CSI2_SPI_CAM      (2<<4)

+#define CFG_REGS_UART2_MASK        (1<<6)

+#define CFG_REGS_UART2_HOST_UART   (0<<6)

+#define CFG_REGS_UART2_UART2       (1<<6)

+#define CFG_REGS_UART1_8LINE_MASK  (1<<7)

+#define CFG_REGS_UART1_8LINE_UART2 (0<<7)

+#define CFG_REGS_UART1_8LINE_UART1_8_LINE (1<<7)

+#define CFG_REGS_DAI_MASK          (3<<8)

+#define CFG_REGS_DAI_I2S           (0<<8)

+#define CFG_REGS_DAI_DAI           (1<<8)

+#define CFG_REGS_DAI_DAI_SIMPLE    (2<<8)

+#define CFG_REGS_KEYIN_3_MASK      (1<<10)

+#define CFG_REGS_KEYIN_3_SPI2_CS_1 (0<<10)

+#define CFG_REGS_KEYIN_3_KEYIN_3   (1<<10)

+#define CFG_REGS_LPSCO_1_MASK      (1<<11)

+#define CFG_REGS_LPSCO_1_KEYIN_4   (0<<11)

+#define CFG_REGS_LPSCO_1_LPSCO_1   (1<<11)

+#define CFG_REGS_SPI1_CS_2_MASK    (1<<12)

+#define CFG_REGS_SPI1_CS_2_KEYIN_1 (0<<12)

+#define CFG_REGS_SPI1_CS_2_SPI1_CS_2 (1<<12)

+#define CFG_REGS_I2S_DI_2_MASK     (1<<13)

+#define CFG_REGS_I2S_DI_2_KEYIN_2  (0<<13)

+#define CFG_REGS_I2S_DI_2_I2S_DI_2 (1<<13)

+#define CFG_REGS_TCO_0_MASK        (1<<14)

+#define CFG_REGS_TCO_0_KEYOUT_0    (0<<14)

+#define CFG_REGS_TCO_0_TCO_0       (1<<14)

+#define CFG_REGS_TCO_1_MASK        (1<<15)

+#define CFG_REGS_TCO_1_KEYOUT_1    (0<<15)

+#define CFG_REGS_TCO_1_TCO_1       (1<<15)

+#define CFG_REGS_TCO_2_MASK        (1<<16)

+#define CFG_REGS_TCO_2_KEYOUT_2    (0<<16)

+#define CFG_REGS_TCO_2_TCO_2       (1<<16)

+#define CFG_REGS_KEYOUT_3_4_MASK   (1<<17)

+#define CFG_REGS_KEYOUT_3_4_I2C3   (0<<17)

+#define CFG_REGS_KEYOUT_3_4_KEYOUT_3_4 (1<<17)

+#define CFG_REGS_KEYOUT_6_MASK     (1<<18)

+#define CFG_REGS_KEYOUT_6_UART2_RTS (0<<18)

+#define CFG_REGS_KEYOUT_6_KEYOUT_6 (1<<18)

+#define CFG_REGS_KEYOUT_7_MASK     (1<<19)

+#define CFG_REGS_KEYOUT_7_UART1_RTS (0<<19)

+#define CFG_REGS_KEYOUT_7_KEYOUT_7 (1<<19)

+#define CFG_REGS_GPO_0_MASK        (3<<20)

+#define CFG_REGS_GPO_0_GPO_0       (0<<20)

+#define CFG_REGS_GPO_0_PWT         (1<<20)

+#define CFG_REGS_GPO_0_KEYIN_5     (2<<20)

+#define CFG_REGS_GPO_1_MASK        (3<<22)

+#define CFG_REGS_GPO_1_GPO_1       (0<<22)

+#define CFG_REGS_GPO_1_LPG         (1<<22)

+#define CFG_REGS_GPO_1_KEYOUT_5    (2<<22)

+#define CFG_REGS_GPO_2_MASK        (3<<24)

+#define CFG_REGS_GPO_2_GPO_2       (0<<24)

+#define CFG_REGS_GPO_2_PWL_1       (1<<24)

+#define CFG_REGS_GPO_2_CLK_32K     (2<<24)

+#define CFG_REGS_GPO_3_MASK        (1<<26)

+#define CFG_REGS_GPO_3_LCD_CS_1    (0<<26)

+#define CFG_REGS_GPO_3_GPO_3       (1<<26)

+#define CFG_REGS_GPO_4_MASK        (1<<27)

+#define CFG_REGS_GPO_4_LCD_CS_0    (0<<27)

+#define CFG_REGS_GPO_4_GPO_4       (1<<27)

+#define CFG_REGS_CLK_OUT_MASK      (1<<28)

+#define CFG_REGS_CLK_OUT_HST_CLK   (0<<28)

+#define CFG_REGS_CLK_OUT_CLK_OUT   (1<<28)

+#define CFG_REGS_AP_SPI1_MASK      (1<<29)

+#define CFG_REGS_AP_SPI1_BB_SPI1   (0<<29)

+#define CFG_REGS_AP_SPI1_AP_SPI1   (1<<29)

+#define CFG_REGS_DEBUG_MASK        (3<<30)

+#define CFG_REGS_DEBUG_NONE        (0<<30)

+#define CFG_REGS_DEBUG_AP_MONITOR  (1<<30)

+#define CFG_REGS_DEBUG_WD_MONITOR  (2<<30)

+

+//IO_Drive1_Select

+#define CFG_REGS_DDR_DRIVE_MASK    (7<<0)

+#define CFG_REGS_DDR_DRIVE_FAST_AND_MOST_WEAK (7<<0)

+#define CFG_REGS_DDR_DRIVE_FAST_AND_WEAK (6<<0)

+#define CFG_REGS_DDR_DRIVE_FAST_AND_STRONG (5<<0)

+#define CFG_REGS_DDR_DRIVE_FAST_AND_MOST_STRONG (4<<0)

+#define CFG_REGS_DDR_DRIVE_SLOW_AND_MOST_WEAK (3<<0)

+#define CFG_REGS_DDR_DRIVE_SLOW_AND_WEAK (2<<0)

+#define CFG_REGS_DDR_DRIVE_SLOW_AND_STRONG (1<<0)

+#define CFG_REGS_DDR_DRIVE_SLOW_AND_MOST_STRONG (0<<0)

+#define CFG_REGS_PSRAM1_DRIVE_MASK (7<<3)

+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_MOST_WEAK (7<<3)

+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_WEAK (6<<3)

+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_STRONG (5<<3)

+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_MOST_STRONG (4<<3)

+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_MOST_WEAK (3<<3)

+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_WEAK (2<<3)

+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_STRONG (1<<3)

+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_MOST_STRONG (0<<3)

+#define CFG_REGS_PSRAM2_DRIVE_MASK (7<<6)

+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_MOST_WEAK (7<<6)

+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_WEAK (6<<6)

+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_STRONG (5<<6)

+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_MOST_STRONG (4<<6)

+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_MOST_WEAK (3<<6)

+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_WEAK (2<<6)

+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_STRONG (1<<6)

+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_MOST_STRONG (0<<6)

+#define CFG_REGS_NFLSH_DRIVE_MASK  (7<<9)

+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_MOST_WEAK (7<<9)

+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_WEAK (6<<9)

+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_STRONG (5<<9)

+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_MOST_STRONG (4<<9)

+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_MOST_WEAK (3<<9)

+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_WEAK (2<<9)

+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_STRONG (1<<9)

+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_MOST_STRONG (0<<9)

+#define CFG_REGS_LCD1_DRIVE_MASK   (7<<12)

+#define CFG_REGS_LCD1_DRIVE_FAST_AND_MOST_WEAK (7<<12)

+#define CFG_REGS_LCD1_DRIVE_FAST_AND_WEAK (6<<12)

+#define CFG_REGS_LCD1_DRIVE_FAST_AND_STRONG (5<<12)

+#define CFG_REGS_LCD1_DRIVE_FAST_AND_MOST_STRONG (4<<12)

+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_MOST_WEAK (3<<12)

+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_WEAK (2<<12)

+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_STRONG (1<<12)

+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_MOST_STRONG (0<<12)

+#define CFG_REGS_LCD2_DRIVE_MASK   (7<<15)

+#define CFG_REGS_LCD2_DRIVE_FAST_AND_MOST_WEAK (7<<15)

+#define CFG_REGS_LCD2_DRIVE_FAST_AND_WEAK (6<<15)

+#define CFG_REGS_LCD2_DRIVE_FAST_AND_STRONG (5<<15)

+#define CFG_REGS_LCD2_DRIVE_FAST_AND_MOST_STRONG (4<<15)

+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_MOST_WEAK (3<<15)

+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_WEAK (2<<15)

+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_STRONG (1<<15)

+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_MOST_STRONG (0<<15)

+#define CFG_REGS_SDAT1_DRIVE_MASK  (7<<18)

+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_MOST_WEAK (7<<18)

+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_WEAK (6<<18)

+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_STRONG (5<<18)

+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_MOST_STRONG (4<<18)

+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_MOST_WEAK (3<<18)

+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_WEAK (2<<18)

+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_STRONG (1<<18)

+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_MOST_STRONG (0<<18)

+#define CFG_REGS_SDAT2_DRIVE_MASK  (7<<21)

+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_MOST_WEAK (7<<21)

+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_WEAK (6<<21)

+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_STRONG (5<<21)

+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_MOST_STRONG (4<<21)

+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_MOST_WEAK (3<<21)

+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_WEAK (2<<21)

+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_STRONG (1<<21)

+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_MOST_STRONG (0<<21)

+#define CFG_REGS_CAM_DRIVE_MASK    (3<<24)

+#define CFG_REGS_CAM_DRIVE_MOST_STRONG (0<<24)

+#define CFG_REGS_CAM_DRIVE_STRONG  (1<<24)

+#define CFG_REGS_CAM_DRIVE_WEAK    (2<<24)

+#define CFG_REGS_CAM_DRIVE_MOST_WEAK (3<<24)

+#define CFG_REGS_SIM1_DRIVE_MASK   (3<<26)

+#define CFG_REGS_SIM1_DRIVE_MOST_STRONG (0<<26)

+#define CFG_REGS_SIM1_DRIVE_STRONG (1<<26)

+#define CFG_REGS_SIM1_DRIVE_WEAK   (2<<26)

+#define CFG_REGS_SIM1_DRIVE_MOST_WEAK (3<<26)

+#define CFG_REGS_SIM2_DRIVE_MASK   (3<<28)

+#define CFG_REGS_SIM2_DRIVE_MOST_STRONG (0<<28)

+#define CFG_REGS_SIM2_DRIVE_STRONG (1<<28)

+#define CFG_REGS_SIM2_DRIVE_WEAK   (2<<28)

+#define CFG_REGS_SIM2_DRIVE_MOST_WEAK (3<<28)

+#define CFG_REGS_SIM3_DRIVE_MASK   (3<<30)

+#define CFG_REGS_SIM3_DRIVE_MOST_STRONG (0<<30)

+#define CFG_REGS_SIM3_DRIVE_STRONG (1<<30)

+#define CFG_REGS_SIM3_DRIVE_WEAK   (2<<30)

+#define CFG_REGS_SIM3_DRIVE_MOST_WEAK (3<<30)

+

+//IO_Drive2_Select

+#define CFG_REGS_GPIO_DRIVE_MASK   (3<<0)

+#define CFG_REGS_GPIO_DRIVE_MOST_STRONG (0<<0)

+#define CFG_REGS_GPIO_DRIVE_STRONG (1<<0)

+#define CFG_REGS_GPIO_DRIVE_WEAK   (2<<0)

+#define CFG_REGS_GPIO_DRIVE_MOST_WEAK (3<<0)

+

+//RAM_DRIVE

+#define CFG_REGS_MBRAM_A(n)        (((n)&7)<<0)

+#define CFG_REGS_MBRAM_A_MASK      (7<<0)

+#define CFG_REGS_MBRAM_A_SHIFT     (0)

+#define CFG_REGS_MBRAM_W(n)        (((n)&3)<<3)

+#define CFG_REGS_MBRAM_W_MASK      (3<<3)

+#define CFG_REGS_MBRAM_W_SHIFT     (3)

+#define CFG_REGS_MBRAM_R           (1<<5)

+#define CFG_REGS_BBRAM_A(n)        (((n)&7)<<6)

+#define CFG_REGS_BBRAM_A_MASK      (7<<6)

+#define CFG_REGS_BBRAM_A_SHIFT     (6)

+#define CFG_REGS_BBRAM_W(n)        (((n)&3)<<9)

+#define CFG_REGS_BBRAM_W_MASK      (3<<9)

+#define CFG_REGS_BBRAM_W_SHIFT     (9)

+#define CFG_REGS_BBRAM_R           (1<<11)

+#define CFG_REGS_XP_A(n)           (((n)&7)<<12)

+#define CFG_REGS_XP_A_MASK         (7<<12)

+#define CFG_REGS_XP_A_SHIFT        (12)

+#define CFG_REGS_XP_W(n)           (((n)&3)<<15)

+#define CFG_REGS_XP_W_MASK         (3<<15)

+#define CFG_REGS_XP_W_SHIFT        (15)

+#define CFG_REGS_XP_R              (1<<17)

+#define CFG_REGS_BP_A(n)           (((n)&7)<<18)

+#define CFG_REGS_BP_A_MASK         (7<<18)

+#define CFG_REGS_BP_A_SHIFT        (18)

+#define CFG_REGS_BP_W(n)           (((n)&3)<<21)

+#define CFG_REGS_BP_W_MASK         (3<<21)

+#define CFG_REGS_BP_W_SHIFT        (21)

+#define CFG_REGS_BP_R              (1<<23)

+#define CFG_REGS_EV_A(n)           (((n)&7)<<24)

+#define CFG_REGS_EV_A_MASK         (7<<24)

+#define CFG_REGS_EV_A_SHIFT        (24)

+#define CFG_REGS_EV_W(n)           (((n)&3)<<27)

+#define CFG_REGS_EV_W_MASK         (3<<27)

+#define CFG_REGS_EV_W_SHIFT        (27)

+#define CFG_REGS_EV_R              (1<<29)

+

+//H2X_AP_Offset

+#define CFG_REGS_H2X_AP_OFFSET(n)  (((n)&0xFF)<<0)

+#define CFG_REGS_H2X_AP_OFFSET_MASK (0xFF<<0)

+#define CFG_REGS_H2X_AP_OFFSET_SHIFT (0)

+

+//H2X_DDR_Offset

+#define CFG_REGS_H2X_DDR_OFFSET(n) (((n)&0xFFFFFFF)<<4)

+#define CFG_REGS_H2X_DDR_OFFSET_MASK (0xFFFFFFF<<4)

+#define CFG_REGS_H2X_DDR_OFFSET_SHIFT (4)

+

+//audio_pd_set

+#define CFG_REGS_AU_DEEP_PD_N      (1<<0)

+#define CFG_REGS_AU_REF_PD_N       (1<<1)

+#define CFG_REGS_AU_MIC_PD_N       (1<<2)

+#define CFG_REGS_AU_AUXMIC_PD_N    (1<<3)

+#define CFG_REGS_AU_AD_PD_N        (1<<4)

+#define CFG_REGS_AU_DAC_PD_N       (1<<5)

+#define CFG_REGS_AU_DAC_RESET_N    (1<<8)

+#define CFG_REGS_AU_PLL_PU         (1<<16)

+

+//audio_pd_clr

+//#define CFG_REGS_AU_DEEP_PD_N    (1<<0)

+//#define CFG_REGS_AU_REF_PD_N     (1<<1)

+//#define CFG_REGS_AU_MIC_PD_N     (1<<2)

+//#define CFG_REGS_AU_AUXMIC_PD_N  (1<<3)

+//#define CFG_REGS_AU_AD_PD_N      (1<<4)

+//#define CFG_REGS_AU_DAC_PD_N     (1<<5)

+//#define CFG_REGS_AU_DAC_RESET_N  (1<<8)

+//#define CFG_REGS_AU_PLL_PU       (1<<16)

+

+//audio_sel_cfg

+#define CFG_REGS_AU_AUXMIC_SEL     (1<<0)

+#define CFG_REGS_AU_SPK_SEL        (1<<1)

+#define CFG_REGS_AU_SPK_MONO_SEL   (1<<2)

+#define CFG_REGS_AU_RCV_SEL        (1<<3)

+#define CFG_REGS_AU_HEAD_SEL       (1<<4)

+

+//audio_mic_cfg

+#define CFG_REGS_AU_MIC_GAIN(n)    (((n)&15)<<0)

+#define CFG_REGS_AU_MIC_GAIN_MASK  (15<<0)

+#define CFG_REGS_AU_MIC_GAIN_SHIFT (0)

+#define CFG_REGS_AU_MIC_MUTE_N     (1<<4)

+

+//audio_spk_cfg

+#define CFG_REGS_AU_SPK_GAIN(n)    (((n)&15)<<0)

+#define CFG_REGS_AU_SPK_GAIN_MASK  (15<<0)

+#define CFG_REGS_AU_SPK_GAIN_SHIFT (0)

+#define CFG_REGS_AU_SPK_MUTE_N     (1<<4)

+#define CFG_REGS_AU_SPK_VOC_GAIN_EN (1<<8)

+

+//audio_rcv_gain

+#define CFG_REGS_AU_RCV_GAIN(n)    (((n)&15)<<0)

+#define CFG_REGS_AU_RCV_GAIN_MASK  (15<<0)

+#define CFG_REGS_AU_RCV_GAIN_SHIFT (0)

+#define CFG_REGS_AU_RCV_VOC_GAIN_EN (1<<8)

+

+//audio_head_gain

+#define CFG_REGS_AU_HEAD_GAIN(n)   (((n)&15)<<0)

+#define CFG_REGS_AU_HEAD_GAIN_MASK (15<<0)

+#define CFG_REGS_AU_HEAD_GAIN_SHIFT (0)

+#define CFG_REGS_AU_HEAD_VOC_GAIN_EN (1<<8)

+

+//TSC_DATA

+#define CFG_REGS_TSC_X_VALUE_BIT(n) (((n)&0x3FF)<<0)

+#define CFG_REGS_TSC_X_VALUE_BIT_MASK (0x3FF<<0)

+#define CFG_REGS_TSC_X_VALUE_BIT_SHIFT (0)

+#define CFG_REGS_TSC_X_VALUE_VALID (1<<10)

+#define CFG_REGS_TSC_Y_VALUE_BIT(n) (((n)&0x3FF)<<11)

+#define CFG_REGS_TSC_Y_VALUE_BIT_MASK (0x3FF<<11)

+#define CFG_REGS_TSC_Y_VALUE_BIT_SHIFT (11)

+#define CFG_REGS_TSC_Y_VALUE_VALID (1<<21)

+

+//GPADC_DATA_CH

+#define CFG_REGS_GPADC_DATA(n)     (((n)&0x3FF)<<0)

+#define CFG_REGS_GPADC_DATA_MASK   (0x3FF<<0)

+#define CFG_REGS_GPADC_DATA_SHIFT  (0)

+#define CFG_REGS_GPADC_VALID       (1<<10)

+#define CFG_REGS_GPADC_CH_EN       (1<<31)

+

+//Alt_mux_select2

+#define CFG_REGS_UART1_SDIO2_MASK  (1<<0)

+#define CFG_REGS_UART1_SDIO2_SDIO2 (0<<0)

+#define CFG_REGS_UART1_SDIO2_UART1 (1<<0)

+#define CFG_REGS_RFSPI_WD_MODE_MASK (1<<1)

+#define CFG_REGS_RFSPI_WD_MODE_SPLIT (0<<1)

+#define CFG_REGS_RFSPI_WD_MODE_AUTO (1<<1)

+#define CFG_REGS_LCD_RGB_17_16_MASK (1<<2)

+#define CFG_REGS_LCD_RGB_17_16_LCD_CS (0<<2)

+#define CFG_REGS_LCD_RGB_17_16_LCD_DATA (1<<2)

+#define CFG_REGS_JTAG_EN_MASK      (1<<3)

+#define CFG_REGS_JTAG_EN_DISABLE   (0<<3)

+#define CFG_REGS_JTAG_EN_ENABLE    (1<<3)

+#define CFG_REGS_RFIF_TEST_MASK    (1<<4)

+#define CFG_REGS_RFIF_TEST_DISABLE (0<<4)

+#define CFG_REGS_RFIF_TEST_ENABLE  (1<<4)

+#define CFG_REGS_IOMUX_CFG_RESERVED(n) (((n)&0x7FFFFFF)<<5)

+

+//Mem_mode_Sel

+#define CFG_REGS_MPMC_EN_MASK      (1<<0)

+#define CFG_REGS_MPMC_EN_DISABLE   (0<<0)

+#define CFG_REGS_MPMC_EN_ENABLE    (1<<0)

+#define CFG_REGS_PSRAM_EN_MASK     (1<<4)

+#define CFG_REGS_PSRAM_EN_DISABLE  (0<<4)

+#define CFG_REGS_PSRAM_EN_ENABLE   (1<<4)

+#define CFG_REGS_PSRAM_128_MASK    (1<<8)

+#define CFG_REGS_PSRAM_128_DISABLE (0<<8)

+#define CFG_REGS_PSRAM_128_ENABLE  (1<<8)

+

+

+

+

+

+#endif

+

diff --git a/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8850e.h b/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8850e.h
new file mode 100644
index 0000000000..5ef2d1bd6b
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_cfg_regs_rda8850e.h
@@ -0,0 +1,1297 @@
+//==============================================================================
+//
+//            Copyright (C) 2012-2014, RDA Microelectronics.
+//                            All Rights Reserved
+//
+//      This source code is the property of RDA Microelectronics and is
+//      confidential.  Any  modification, distribution,  reproduction or
+//      exploitation  of  any content of this file is totally forbidden,
+//      except  with the  written permission  of   RDA Microelectronics.
+//
+//==============================================================================
+//
+//    THIS FILE WAS GENERATED FROM ITS CORRESPONDING XML VERSION WITH COOLXML.
+//
+//                       !!! PLEASE DO NOT EDIT !!!
+//
+//  $HeadURL$
+//  $Author$
+//  $Date$
+//  $Revision$
+//
+//==============================================================================
+//
+/// @file
+//
+//==============================================================================
+
+#ifndef _CFG_REGS_H_
+#define _CFG_REGS_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+#ifdef CT_ASM
+#error "You are trying to use in an assembly code the normal H description of 'cfg_regs'."
+#endif
+
+
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+#define PROD_ID                                 (0X810E)
+
+// ============================================================================
+// BB_GPIO_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// BB GPIO Map
+    BB_PIN_NONE_0                               = 0x00000000,
+    BB_PIN_1                                    = 0x00000001,
+    BB_PIN_2                                    = 0x00000002,
+    BB_PIN_3                                    = 0x00000003,
+    BB_PIN_4                                    = 0x00000004,
+    BB_PIN_5                                    = 0x00000005,
+    BB_PIN_UART1_RXD                            = 0x00000006,
+    BB_PIN_UART2_RXD                            = 0x00000007,
+    BB_PIN_UART2_TXD                            = 0x00000008,
+    BB_PIN_SSD1_CLK                             = 0x00000009,
+    BB_PIN_SSD1_CMD                             = 0x0000000A,
+    BB_PIN_SDAT1_0                              = 0x0000000B,
+    BB_PIN_SDAT1_1                              = 0x0000000C,
+    BB_PIN_SDAT1_2                              = 0x0000000D,
+    BB_PIN_SDAT1_3                              = 0x0000000E,
+    BB_PIN_SSD2_CLK                             = 0x0000000F,
+    BB_PIN_SSD2_CMD                             = 0x00000010,
+    BB_PIN_SDAT2_0                              = 0x00000011,
+    BB_PIN_SDAT2_1                              = 0x00000012,
+    BB_PIN_SDAT2_2                              = 0x00000013,
+    BB_PIN_SDAT2_3                              = 0x00000014,
+    BB_PIN_SPI1_CLK                             = 0x00000015,
+    BB_PIN_SPI1_CS_0                            = 0x00000016,
+    BB_PIN_SPI1_DIO                             = 0x00000017,
+    BB_PIN_SPI1_DI                              = 0x00000018,
+    BB_PIN_SIM2_RST                             = 0x00000019,
+    BB_PIN_SIM2_CLK                             = 0x0000001A,
+    BB_PIN_SIM2_DIO                             = 0x0000001B,
+    BB_PIN_SIM3_RST                             = 0x0000001C,
+    BB_PIN_SIM3_CLK                             = 0x0000001D,
+    BB_PIN_SIM3_DIO                             = 0x0000001E
+} BB_GPIO_MAPPING_T;
+
+#define BB_GPIO_NB                              (31)
+
+// ============================================================================
+// AP_GPIO_A_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP GPIO A Map
+    AP_PIN_I2C2_SCL                             = 0x00000000,
+    AP_PIN_I2C2_SDA                             = 0x00000001,
+    AP_PIN_SPI2_CLK                             = 0x00000002,
+    AP_PIN_SPI2_DIO                             = 0x00000003,
+    AP_PIN_SPI2_DI                              = 0x00000004,
+    AP_PIN_SPI2_CS_0                            = 0x00000005,
+    AP_PIN_SPI2_CS_1                            = 0x00000006,
+    AP_PIN_KEYIN_4                              = 0x00000007,
+    AP_PIN_CLK_OUT                              = 0x00000008,
+    AP_PIN_I2S_BCK                              = 0x00000009,
+    AP_PIN_I2S_LRCK                             = 0x0000000A,
+    AP_PIN_I2S_DI_0                             = 0x0000000B,
+    AP_PIN_I2S_DI_1                             = 0x0000000C,
+    AP_PIN_I2S_DO                               = 0x0000000D,
+    AP_PIN_UART1_TXD                            = 0x0000000E,
+    AP_PIN_UART1_CTS                            = 0x0000000F,
+    AP_PIN_UART1_RTS                            = 0x00000010,
+    AP_PIN_SPI1_CS_1                            = 0x00000011,
+    AP_PIN_LCD_DATA_6                           = 0x00000012,
+    AP_PIN_LCD_DATA_7                           = 0x00000013,
+    AP_PIN_LCD_WR                               = 0x00000014,
+    AP_PIN_LCD_RS                               = 0x00000015,
+    AP_PIN_LCD_RD                               = 0x00000016,
+    AP_PIN_LCD_FMARK                            = 0x00000017,
+    AP_PIN_LCD_DATA_8                           = 0x00000018,
+    AP_PIN_LCD_DATA_9                           = 0x00000019,
+    AP_PIN_LCD_DATA_10                          = 0x0000001A,
+    AP_PIN_LCD_DATA_11                          = 0x0000001B,
+    AP_PIN_LCD_DATA_12                          = 0x0000001C,
+    AP_PIN_LCD_DATA_13                          = 0x0000001D,
+    AP_PIN_LCD_DATA_14                          = 0x0000001E,
+    AP_PIN_LCD_DATA_15                          = 0x0000001F
+} AP_GPIO_A_MAPPING_T;
+
+#define AP_GPIO_A_NB                            (32)
+
+// ============================================================================
+// AP_GPIO_B_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP GPIO B Map
+    AP_PIN_KEYIN_0                              = 0x00000000,
+    AP_PIN_KEYIN_1                              = 0x00000001,
+    AP_PIN_KEYIN_2                              = 0x00000002,
+    AP_PIN_KEYOUT_0                             = 0x00000003,
+    AP_PIN_KEYOUT_1                             = 0x00000004,
+    AP_PIN_KEYOUT_2                             = 0x00000005,
+    AP_PIN_I2C3_SCL                             = 0x00000006,
+    AP_PIN_I2C3_SDA                             = 0x00000007,
+    AP_PIN_UART2_CTS                            = 0x00000008,
+    AP_PIN_UART2_RTS                            = 0x00000009,
+    AP_PIN_CAM_RST                              = 0x0000000A,
+    AP_PIN_CAM_PDN                              = 0x0000000B,
+    AP_PIN_CAM_CLK                              = 0x0000000C,
+    AP_PIN_CAM_VSYNC                            = 0x0000000D,
+    AP_PIN_CAM_HREF                             = 0x0000000E,
+    AP_PIN_CAM_PCLK                             = 0x0000000F,
+    AP_PIN_CAM_DATA_0                           = 0x00000010,
+    AP_PIN_CAM_DATA_1                           = 0x00000011,
+    AP_PIN_CAM_DATA_2                           = 0x00000012,
+    AP_PIN_CAM_DATA_3                           = 0x00000013,
+    AP_PIN_CAM_DATA_4                           = 0x00000014,
+    AP_PIN_CAM_DATA_5                           = 0x00000015,
+    AP_PIN_CAM_DATA_6                           = 0x00000016,
+    AP_PIN_CAM_DATA_7                           = 0x00000017,
+    AP_PIN_M_SPI_CS_0                           = 0x00000018,
+    AP_PIN_NFCLE                                = 0x00000019,
+    AP_PIN_NFWEN                                = 0x0000001A,
+    AP_PIN_NFWPN                                = 0x0000001B,
+    AP_PIN_NFREN                                = 0x0000001C,
+    AP_PIN_NFRB                                 = 0x0000001D,
+    AP_PIN_I2C1_SCL                             = 0x0000001E,
+    AP_PIN_I2C1_SDA                             = 0x0000001F
+} AP_GPIO_B_MAPPING_T;
+
+#define AP_GPIO_B_NB                            (32)
+
+// ============================================================================
+// AP_GPIO_D_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP GPIO D Map
+    AP_PIN_UART3_RXD                            = 0x00000000,
+    AP_PIN_UART3_TXD                            = 0x00000001,
+    AP_PIN_UART3_CTS                            = 0x00000002,
+    AP_PIN_UART3_RTS                            = 0x00000003,
+    AP_PIN_NFDQS                                = 0x00000004,
+    AP_PIN_VOLUME_DN                            = 0x00000005,
+    AP_PIN_VOLUME_UP                            = 0x00000006,
+    AP_PIN_PLUGIN                               = 0x00000007,
+    AP_PIN_NFCEN_1                              = 0x00000008,
+    AP_PIN_NFCEN_2                              = 0x00000009,
+    AP_PIN_NFCEN_3                              = 0x0000000A,
+    AP_PIN_I2S2_BCK                             = 0x0000000B,
+    AP_PIN_I2S2_LRCK                            = 0x0000000C,
+    AP_PIN_I2S2_DI_0                            = 0x0000000D,
+    AP_PIN_I2S2_DI_1                            = 0x0000000E,
+    AP_PIN_I2S2_DO                              = 0x0000000F
+} AP_GPIO_D_MAPPING_T;
+
+#define AP_GPIO_D_NB                            (16)
+
+// ============================================================================
+// AP_GPIO_E_MAPPING_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef enum
+{
+/// AP GPIO E Map
+    AP_PIN_I2CBB_SCL                            = 0x00000000,
+    AP_PIN_I2CBB_SDA                            = 0x00000001,
+    AP_PIN_CAM2_RST                             = 0x00000002,
+    AP_PIN_CAM2_PDN                             = 0x00000003,
+    AP_PIN_CAM2_CLK                             = 0x00000004,
+    AP_PIN_CAM2_VSYNC                           = 0x00000005,
+    AP_PIN_CAM2_HREF                            = 0x00000006,
+    AP_PIN_CAM2_PCLK                            = 0x00000007,
+    AP_PIN_CAM2_DATA_0                          = 0x00000008,
+    AP_PIN_CAM2_DATA_1                          = 0x00000009,
+    AP_PIN_CAM2_DATA_2                          = 0x0000000A,
+    AP_PIN_CAM2_DATA_3                          = 0x0000000B,
+    AP_PIN_CAM2_DATA_4                          = 0x0000000C,
+    AP_PIN_CAM2_DATA_5                          = 0x0000000D,
+    AP_PIN_CAM2_DATA_6                          = 0x0000000E,
+    AP_PIN_CAM2_DATA_7                          = 0x0000000F
+} AP_GPIO_E_MAPPING_T;
+
+#define AP_GPIO_E_NB                            (16)
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+// ============================================================================
+// CFG_REGS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef volatile struct
+{
+    REG32                          CHIP_ID;                      //0x00000000
+    /// This register contain the synthesis date and version
+    REG32                          Build_Version;                //0x00000004
+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+    /// bit n to '0' selects Alt.
+    REG32                          BB_GPIO_Mode;                 //0x00000008
+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+    /// bit n to '0' selects Alt.
+    REG32                          AP_GPIO_A_Mode;               //0x0000000C
+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+    /// bit n to '0' selects Alt.
+    REG32                          AP_GPIO_B_Mode;               //0x00000010
+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+    /// bit n to '0' selects Alt.
+    REG32                          AP_GPIO_D_Mode;               //0x00000014
+    REG32                          Alt_mux_select;               //0x00000018
+    REG32                          IO_Drive1_Select;             //0x0000001C
+    REG32                          IO_Drive2_Select;             //0x00000020
+    REG32                          RAM_DRIVE;                    //0x00000024
+    REG32                          H2X_AP_Offset;                //0x00000028
+    REG32                          H2X_DDR_Offset;               //0x0000002C
+    REG32                          H2X_WD_DDR_Offset;            //0x00000030
+    REG32                          audio_pd_set;                 //0x00000034
+    REG32                          audio_pd_clr;                 //0x00000038
+    REG32                          audio_sel_cfg;                //0x0000003C
+    REG32                          audio_mic_cfg;                //0x00000040
+    REG32                          audio_spk_cfg;                //0x00000044
+    REG32                          audio_rcv_gain;               //0x00000048
+    REG32                          audio_head_gain;              //0x0000004C
+    REG32                          TSC_DATA;                     //0x00000050
+    REG32                          GPADC_DATA_CH[8];             //0x00000054
+    REG32                          Alt_mux_select2;              //0x00000074
+    REG32                          Mem_mode_Sel;                 //0x00000078
+    /// Setting bit n to '1' selects GPIO Usage for PAD connected to GPIOn. Setting
+    /// bit n to '0' selects Alt.
+    REG32                          AP_GPIO_E_Mode;               //0x0000007C
+} HWP_CFG_REGS_T;
+
+#define hwp_configRegs             ((HWP_CFG_REGS_T*)(RDA_CFG_REGS_BASE))
+
+
+//CHIP_ID
+#define CFG_REGS_METAL_ID(n)       (((n)&0xFFF)<<0)
+#define CFG_REGS_METAL_ID_MASK     (0xFFF<<0)
+#define CFG_REGS_METAL_ID_SHIFT    (0)
+#define CFG_REGS_BOND_ID(n)        (((n)&7)<<12)
+#define CFG_REGS_BOND_ID_MASK      (7<<12)
+#define CFG_REGS_BOND_ID_SHIFT     (12)
+#define CFG_REGS_PROD_ID(n)        (((n)&0xFFFF)<<16)
+#define CFG_REGS_PROD_ID_MASK      (0xFFFF<<16)
+#define CFG_REGS_PROD_ID_SHIFT     (16)
+
+//Build_Version
+#define CFG_REGS_MAJOR(n)          (((n)&15)<<28)
+#define CFG_REGS_YEAR(n)           (((n)&15)<<24)
+#define CFG_REGS_MONTH(n)          (((n)&0xFF)<<16)
+#define CFG_REGS_DAY(n)            (((n)&0xFF)<<8)
+#define CFG_REGS_BUILD_STYLE_FPGA  (0<<4)
+#define CFG_REGS_BUILD_STYLE_CHIP  (1<<4)
+#define CFG_REGS_BUILD_STYLE_FPGA_USB (2<<4)
+#define CFG_REGS_BUILD_STYLE_FPGA_GSM (3<<4)
+#define CFG_REGS_BUILD_REVISION(n) (((n)&15)<<0)
+
+//BB_GPIO_Mode
+#define CFG_REGS_MODE_BB_PIN_NONE_0 (1<<0)
+#define CFG_REGS_MODE_BB_PIN_NONE_0_MASK (1<<0)
+#define CFG_REGS_MODE_BB_PIN_NONE_0_SHIFT (0)
+#define CFG_REGS_MODE_BB_PIN_NONE_0_ALT (0<<0)
+#define CFG_REGS_MODE_BB_PIN_NONE_0_GPIO (1<<0)
+#define CFG_REGS_MODE_BB_PIN_1     (1<<1)
+#define CFG_REGS_MODE_BB_PIN_1_MASK (1<<1)
+#define CFG_REGS_MODE_BB_PIN_1_SHIFT (1)
+#define CFG_REGS_MODE_BB_PIN_1_ALT (0<<1)
+#define CFG_REGS_MODE_BB_PIN_1_GPIO (1<<1)
+#define CFG_REGS_MODE_BB_PIN_2     (1<<2)
+#define CFG_REGS_MODE_BB_PIN_2_MASK (1<<2)
+#define CFG_REGS_MODE_BB_PIN_2_SHIFT (2)
+#define CFG_REGS_MODE_BB_PIN_2_ALT (0<<2)
+#define CFG_REGS_MODE_BB_PIN_2_GPIO (1<<2)
+#define CFG_REGS_MODE_BB_PIN_3     (1<<3)
+#define CFG_REGS_MODE_BB_PIN_3_MASK (1<<3)
+#define CFG_REGS_MODE_BB_PIN_3_SHIFT (3)
+#define CFG_REGS_MODE_BB_PIN_3_ALT (0<<3)
+#define CFG_REGS_MODE_BB_PIN_3_GPIO (1<<3)
+#define CFG_REGS_MODE_BB_PIN_4     (1<<4)
+#define CFG_REGS_MODE_BB_PIN_4_MASK (1<<4)
+#define CFG_REGS_MODE_BB_PIN_4_SHIFT (4)
+#define CFG_REGS_MODE_BB_PIN_4_ALT (0<<4)
+#define CFG_REGS_MODE_BB_PIN_4_GPIO (1<<4)
+#define CFG_REGS_MODE_BB_PIN_5     (1<<5)
+#define CFG_REGS_MODE_BB_PIN_5_MASK (1<<5)
+#define CFG_REGS_MODE_BB_PIN_5_SHIFT (5)
+#define CFG_REGS_MODE_BB_PIN_5_ALT (0<<5)
+#define CFG_REGS_MODE_BB_PIN_5_GPIO (1<<5)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD (1<<6)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_MASK (1<<6)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_SHIFT (6)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_ALT (0<<6)
+#define CFG_REGS_MODE_BB_PIN_UART1_RXD_GPIO (1<<6)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD (1<<7)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_MASK (1<<7)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_SHIFT (7)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_ALT (0<<7)
+#define CFG_REGS_MODE_BB_PIN_UART2_RXD_GPIO (1<<7)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD (1<<8)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_MASK (1<<8)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_SHIFT (8)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_ALT (0<<8)
+#define CFG_REGS_MODE_BB_PIN_UART2_TXD_GPIO (1<<8)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK (1<<9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_MASK (1<<9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_SHIFT (9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_ALT (0<<9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CLK_GPIO (1<<9)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD (1<<10)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_MASK (1<<10)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_SHIFT (10)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_ALT (0<<10)
+#define CFG_REGS_MODE_BB_PIN_SSD1_CMD_GPIO (1<<10)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0 (1<<11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_MASK (1<<11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_SHIFT (11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_ALT (0<<11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_0_GPIO (1<<11)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1 (1<<12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_MASK (1<<12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_SHIFT (12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_ALT (0<<12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_1_GPIO (1<<12)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2 (1<<13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_MASK (1<<13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_SHIFT (13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_ALT (0<<13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_2_GPIO (1<<13)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3 (1<<14)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_MASK (1<<14)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_SHIFT (14)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_ALT (0<<14)
+#define CFG_REGS_MODE_BB_PIN_SDAT1_3_GPIO (1<<14)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK (1<<15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_MASK (1<<15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_SHIFT (15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_ALT (0<<15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CLK_GPIO (1<<15)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD (1<<16)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_MASK (1<<16)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_SHIFT (16)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_ALT (0<<16)
+#define CFG_REGS_MODE_BB_PIN_SSD2_CMD_GPIO (1<<16)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0 (1<<17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_MASK (1<<17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_SHIFT (17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_ALT (0<<17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_0_GPIO (1<<17)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1 (1<<18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_MASK (1<<18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_SHIFT (18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_ALT (0<<18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_1_GPIO (1<<18)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2 (1<<19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_MASK (1<<19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_SHIFT (19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_ALT (0<<19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_2_GPIO (1<<19)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3 (1<<20)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_MASK (1<<20)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_SHIFT (20)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_ALT (0<<20)
+#define CFG_REGS_MODE_BB_PIN_SDAT2_3_GPIO (1<<20)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK (1<<21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_MASK (1<<21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_SHIFT (21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_ALT (0<<21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CLK_GPIO (1<<21)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0 (1<<22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_MASK (1<<22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_SHIFT (22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_ALT (0<<22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_CS_0_GPIO (1<<22)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO (1<<23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_MASK (1<<23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_SHIFT (23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_ALT (0<<23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DIO_GPIO (1<<23)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI (1<<24)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_MASK (1<<24)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_SHIFT (24)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_ALT (0<<24)
+#define CFG_REGS_MODE_BB_PIN_SPI1_DI_GPIO (1<<24)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST (1<<25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_MASK (1<<25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_SHIFT (25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_ALT (0<<25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_RST_GPIO (1<<25)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK (1<<26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_MASK (1<<26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_SHIFT (26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_ALT (0<<26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_CLK_GPIO (1<<26)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO (1<<27)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_MASK (1<<27)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_SHIFT (27)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_ALT (0<<27)
+#define CFG_REGS_MODE_BB_PIN_SIM2_DIO_GPIO (1<<27)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST (1<<28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_MASK (1<<28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_SHIFT (28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_ALT (0<<28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_RST_GPIO (1<<28)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK (1<<29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_MASK (1<<29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_SHIFT (29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_ALT (0<<29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_CLK_GPIO (1<<29)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO (1<<30)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_MASK (1<<30)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_SHIFT (30)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_ALT (0<<30)
+#define CFG_REGS_MODE_BB_PIN_SIM3_DIO_GPIO (1<<30)
+#define CFG_REGS_BB_GPIO_MODE(n)   (((n)&0x7FFFFFFF)<<0)
+#define CFG_REGS_BB_GPIO_MODE_MASK (0x7FFFFFFF<<0)
+#define CFG_REGS_BB_GPIO_MODE_SHIFT (0)
+
+//AP_GPIO_A_Mode
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_MASK (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_SHIFT (0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_ALT (0<<0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SCL_GPIO (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA (1<<1)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_MASK (1<<1)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_SHIFT (1)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_ALT (0<<1)
+#define CFG_REGS_MODE_AP_PIN_I2C2_SDA_GPIO (1<<1)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_MASK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_SHIFT (2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_ALT (0<<2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CLK_GPIO (1<<2)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_MASK (1<<3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_SHIFT (3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_ALT (0<<3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DIO_GPIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI (1<<4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_MASK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_SHIFT (4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_ALT (0<<4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_DI_GPIO (1<<4)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0 (1<<5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_MASK (1<<5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_SHIFT (5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_ALT (0<<5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_0_GPIO (1<<5)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1 (1<<6)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_MASK (1<<6)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_SHIFT (6)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_ALT (0<<6)
+#define CFG_REGS_MODE_AP_PIN_SPI2_CS_1_GPIO (1<<6)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4 (1<<7)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_MASK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_SHIFT (7)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_ALT (0<<7)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_4_GPIO (1<<7)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT (1<<8)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_MASK (1<<8)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_SHIFT (8)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_ALT (0<<8)
+#define CFG_REGS_MODE_AP_PIN_CLK_OUT_GPIO (1<<8)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_MASK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_SHIFT (9)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_ALT (0<<9)
+#define CFG_REGS_MODE_AP_PIN_I2S_BCK_GPIO (1<<9)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_MASK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_SHIFT (10)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_ALT (0<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S_LRCK_GPIO (1<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0 (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_MASK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_SHIFT (11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_ALT (0<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_0_GPIO (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1 (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_MASK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_SHIFT (12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_ALT (0<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DI_1_GPIO (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO_MASK (1<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO_SHIFT (13)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO_ALT (0<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S_DO_GPIO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD (1<<14)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_MASK (1<<14)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_SHIFT (14)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_ALT (0<<14)
+#define CFG_REGS_MODE_AP_PIN_UART1_TXD_GPIO (1<<14)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS (1<<15)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_MASK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_SHIFT (15)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_ALT (0<<15)
+#define CFG_REGS_MODE_AP_PIN_UART1_CTS_GPIO (1<<15)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS (1<<16)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_MASK (1<<16)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_SHIFT (16)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_ALT (0<<16)
+#define CFG_REGS_MODE_AP_PIN_UART1_RTS_GPIO (1<<16)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1 (1<<17)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_MASK (1<<17)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_SHIFT (17)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_ALT (0<<17)
+#define CFG_REGS_MODE_AP_PIN_SPI1_CS_1_GPIO (1<<17)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6 (1<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_MASK (1<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_SHIFT (18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_ALT (0<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_6_GPIO (1<<18)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7 (1<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_MASK (1<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_SHIFT (19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_ALT (0<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_7_GPIO (1<<19)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR (1<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR_MASK (1<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR_SHIFT (20)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR_ALT (0<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_WR_GPIO (1<<20)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS (1<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS_MASK (1<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS_SHIFT (21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS_ALT (0<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RS_GPIO (1<<21)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD (1<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD_MASK (1<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD_SHIFT (22)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD_ALT (0<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_RD_GPIO (1<<22)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK (1<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_MASK (1<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_SHIFT (23)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_ALT (0<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_FMARK_GPIO (1<<23)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8 (1<<24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_MASK (1<<24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_SHIFT (24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_ALT (0<<24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_8_GPIO (1<<24)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9 (1<<25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_MASK (1<<25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_SHIFT (25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_ALT (0<<25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_9_GPIO (1<<25)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10 (1<<26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_MASK (1<<26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_SHIFT (26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_ALT (0<<26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_10_GPIO (1<<26)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11 (1<<27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_MASK (1<<27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_SHIFT (27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_ALT (0<<27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_11_GPIO (1<<27)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12 (1<<28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_MASK (1<<28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_SHIFT (28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_ALT (0<<28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_12_GPIO (1<<28)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13 (1<<29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_MASK (1<<29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_SHIFT (29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_ALT (0<<29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_13_GPIO (1<<29)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14 (1<<30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_MASK (1<<30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_SHIFT (30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_ALT (0<<30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_14_GPIO (1<<30)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15 (1<<31)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_MASK (1<<31)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_SHIFT (31)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_ALT (0<<31)
+#define CFG_REGS_MODE_AP_PIN_LCD_DATA_15_GPIO (1<<31)
+#define CFG_REGS_AP_GPIO_A_MODE(n) (((n)&0xFFFFFFFF)<<0)
+#define CFG_REGS_AP_GPIO_A_MODE_MASK (0xFFFFFFFF<<0)
+#define CFG_REGS_AP_GPIO_A_MODE_SHIFT (0)
+
+//AP_GPIO_B_Mode
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0 (1<<0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_MASK (1<<0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_SHIFT (0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_ALT (0<<0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_0_GPIO (1<<0)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1 (1<<1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_MASK (1<<1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_SHIFT (1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_ALT (0<<1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_1_GPIO (1<<1)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2 (1<<2)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_MASK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_SHIFT (2)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_ALT (0<<2)
+#define CFG_REGS_MODE_AP_PIN_KEYIN_2_GPIO (1<<2)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0 (1<<3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_MASK (1<<3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_SHIFT (3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_ALT (0<<3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_0_GPIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1 (1<<4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_MASK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_SHIFT (4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_ALT (0<<4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_1_GPIO (1<<4)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2 (1<<5)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_MASK (1<<5)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_SHIFT (5)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_ALT (0<<5)
+#define CFG_REGS_MODE_AP_PIN_KEYOUT_2_GPIO (1<<5)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL (1<<6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_MASK (1<<6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_SHIFT (6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_ALT (0<<6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SCL_GPIO (1<<6)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA (1<<7)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_MASK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_SHIFT (7)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_ALT (0<<7)
+#define CFG_REGS_MODE_AP_PIN_I2C3_SDA_GPIO (1<<7)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS (1<<8)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_MASK (1<<8)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_SHIFT (8)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_ALT (0<<8)
+#define CFG_REGS_MODE_AP_PIN_UART2_CTS_GPIO (1<<8)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS (1<<9)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_MASK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_SHIFT (9)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_ALT (0<<9)
+#define CFG_REGS_MODE_AP_PIN_UART2_RTS_GPIO (1<<9)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST_MASK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST_SHIFT (10)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST_ALT (0<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM_RST_GPIO (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_MASK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_SHIFT (11)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_ALT (0<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM_PDN_GPIO (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_MASK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_SHIFT (12)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_ALT (0<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM_CLK_GPIO (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_MASK (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_SHIFT (13)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_ALT (0<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM_VSYNC_GPIO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_MASK (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_SHIFT (14)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_ALT (0<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM_HREF_GPIO (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_MASK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_SHIFT (15)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_ALT (0<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM_PCLK_GPIO (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0 (1<<16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_MASK (1<<16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_SHIFT (16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_ALT (0<<16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_0_GPIO (1<<16)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1 (1<<17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_MASK (1<<17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_SHIFT (17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_ALT (0<<17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_1_GPIO (1<<17)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2 (1<<18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_MASK (1<<18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_SHIFT (18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_ALT (0<<18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_2_GPIO (1<<18)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3 (1<<19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_MASK (1<<19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_SHIFT (19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_ALT (0<<19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_3_GPIO (1<<19)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4 (1<<20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_MASK (1<<20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_SHIFT (20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_ALT (0<<20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_4_GPIO (1<<20)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5 (1<<21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_MASK (1<<21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_SHIFT (21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_ALT (0<<21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_5_GPIO (1<<21)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6 (1<<22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_MASK (1<<22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_SHIFT (22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_ALT (0<<22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_6_GPIO (1<<22)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7 (1<<23)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_MASK (1<<23)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_SHIFT (23)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_ALT (0<<23)
+#define CFG_REGS_MODE_AP_PIN_CAM_DATA_7_GPIO (1<<23)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0 (1<<24)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_MASK (1<<24)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_SHIFT (24)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_ALT (0<<24)
+#define CFG_REGS_MODE_AP_PIN_M_SPI_CS_0_GPIO (1<<24)
+#define CFG_REGS_MODE_AP_PIN_NFCLE (1<<25)
+#define CFG_REGS_MODE_AP_PIN_NFCLE_MASK (1<<25)
+#define CFG_REGS_MODE_AP_PIN_NFCLE_SHIFT (25)
+#define CFG_REGS_MODE_AP_PIN_NFCLE_ALT (0<<25)
+#define CFG_REGS_MODE_AP_PIN_NFCLE_GPIO (1<<25)
+#define CFG_REGS_MODE_AP_PIN_NFWEN (1<<26)
+#define CFG_REGS_MODE_AP_PIN_NFWEN_MASK (1<<26)
+#define CFG_REGS_MODE_AP_PIN_NFWEN_SHIFT (26)
+#define CFG_REGS_MODE_AP_PIN_NFWEN_ALT (0<<26)
+#define CFG_REGS_MODE_AP_PIN_NFWEN_GPIO (1<<26)
+#define CFG_REGS_MODE_AP_PIN_NFWPN (1<<27)
+#define CFG_REGS_MODE_AP_PIN_NFWPN_MASK (1<<27)
+#define CFG_REGS_MODE_AP_PIN_NFWPN_SHIFT (27)
+#define CFG_REGS_MODE_AP_PIN_NFWPN_ALT (0<<27)
+#define CFG_REGS_MODE_AP_PIN_NFWPN_GPIO (1<<27)
+#define CFG_REGS_MODE_AP_PIN_NFREN (1<<28)
+#define CFG_REGS_MODE_AP_PIN_NFREN_MASK (1<<28)
+#define CFG_REGS_MODE_AP_PIN_NFREN_SHIFT (28)
+#define CFG_REGS_MODE_AP_PIN_NFREN_ALT (0<<28)
+#define CFG_REGS_MODE_AP_PIN_NFREN_GPIO (1<<28)
+#define CFG_REGS_MODE_AP_PIN_NFRB  (1<<29)
+#define CFG_REGS_MODE_AP_PIN_NFRB_MASK (1<<29)
+#define CFG_REGS_MODE_AP_PIN_NFRB_SHIFT (29)
+#define CFG_REGS_MODE_AP_PIN_NFRB_ALT (0<<29)
+#define CFG_REGS_MODE_AP_PIN_NFRB_GPIO (1<<29)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL (1<<30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_MASK (1<<30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_SHIFT (30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_ALT (0<<30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SCL_GPIO (1<<30)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA (1<<31)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_MASK (1<<31)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_SHIFT (31)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_ALT (0<<31)
+#define CFG_REGS_MODE_AP_PIN_I2C1_SDA_GPIO (1<<31)
+#define CFG_REGS_AP_GPIO_B_MODE(n) (((n)&0xFFFFFFFF)<<0)
+#define CFG_REGS_AP_GPIO_B_MODE_MASK (0xFFFFFFFF<<0)
+#define CFG_REGS_AP_GPIO_B_MODE_SHIFT (0)
+
+//AP_GPIO_D_Mode
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD (1<<0)
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_MASK (1<<0)
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_SHIFT (0)
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_ALT (0<<0)
+#define CFG_REGS_MODE_AP_PIN_UART3_RXD_GPIO (1<<0)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD (1<<1)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_MASK (1<<1)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_SHIFT (1)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_ALT (0<<1)
+#define CFG_REGS_MODE_AP_PIN_UART3_TXD_GPIO (1<<1)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS (1<<2)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_MASK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_SHIFT (2)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_ALT (0<<2)
+#define CFG_REGS_MODE_AP_PIN_UART3_CTS_GPIO (1<<2)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS (1<<3)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_MASK (1<<3)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_SHIFT (3)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_ALT (0<<3)
+#define CFG_REGS_MODE_AP_PIN_UART3_RTS_GPIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_NFDQS (1<<4)
+#define CFG_REGS_MODE_AP_PIN_NFDQS_MASK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_NFDQS_SHIFT (4)
+#define CFG_REGS_MODE_AP_PIN_NFDQS_ALT (0<<4)
+#define CFG_REGS_MODE_AP_PIN_NFDQS_GPIO (1<<4)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN (1<<5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_MASK (1<<5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_SHIFT (5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_ALT (0<<5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_DN_GPIO (1<<5)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP (1<<6)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_MASK (1<<6)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_SHIFT (6)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_ALT (0<<6)
+#define CFG_REGS_MODE_AP_PIN_VOLUME_UP_GPIO (1<<6)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN (1<<7)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN_MASK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN_SHIFT (7)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN_ALT (0<<7)
+#define CFG_REGS_MODE_AP_PIN_PLUGIN_GPIO (1<<7)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1 (1<<8)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1_MASK (1<<8)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1_SHIFT (8)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1_ALT (0<<8)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_1_GPIO (1<<8)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2 (1<<9)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2_MASK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2_SHIFT (9)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2_ALT (0<<9)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_2_GPIO (1<<9)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3 (1<<10)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3_MASK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3_SHIFT (10)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3_ALT (0<<10)
+#define CFG_REGS_MODE_AP_PIN_NFCEN_3_GPIO (1<<10)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_MASK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_SHIFT (11)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_ALT (0<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S2_BCK_GPIO (1<<11)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_MASK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_SHIFT (12)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_ALT (0<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S2_LRCK_GPIO (1<<12)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0 (1<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_MASK (1<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_SHIFT (13)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_ALT (0<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_0_GPIO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1 (1<<14)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_MASK (1<<14)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_SHIFT (14)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_ALT (0<<14)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DI_1_GPIO (1<<14)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO (1<<15)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO_MASK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO_SHIFT (15)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO_ALT (0<<15)
+#define CFG_REGS_MODE_AP_PIN_I2S2_DO_GPIO (1<<15)
+#define CFG_REGS_AP_GPIO_D_MODE(n) (((n)&0xFFFF)<<0)
+#define CFG_REGS_AP_GPIO_D_MODE_MASK (0xFFFF<<0)
+#define CFG_REGS_AP_GPIO_D_MODE_SHIFT (0)
+
+//Alt_mux_select
+#define CFG_REGS_LCD_MODE_MASK     (3<<0)
+#define CFG_REGS_LCD_MODE_PARALLEL_16BIT (0<<0)
+#define CFG_REGS_LCD_MODE_DSI      (1<<0)
+#define CFG_REGS_LCD_MODE_RGB_24BIT (2<<0)
+#define CFG_REGS_LCD_MODE_RGB_16BIT (3<<0)
+#define CFG_REGS_SPI_LCD_MASK      (1<<2)
+#define CFG_REGS_SPI_LCD_NONE      (0<<2)
+#define CFG_REGS_SPI_LCD_SPI_LCD   (1<<2)
+#define CFG_REGS_CAM_I2C2_MASK     (1<<3)
+#define CFG_REGS_CAM_I2C2_CAM      (0<<3)
+#define CFG_REGS_CAM_I2C2_I2C2     (1<<3)
+#define CFG_REGS_CSI2_MASK         (3<<4)
+#define CFG_REGS_CSI2_PARALLEL_CAM (0<<4)
+#define CFG_REGS_CSI2_CSI2         (1<<4)
+#define CFG_REGS_CSI2_SPI_CAM      (2<<4)
+#define CFG_REGS_UART2_MASK        (1<<6)
+#define CFG_REGS_UART2_HOST_UART   (0<<6)
+#define CFG_REGS_UART2_UART2       (1<<6)
+#define CFG_REGS_UART1_8LINE_MASK  (1<<7)
+#define CFG_REGS_UART1_8LINE_UART2 (0<<7)
+#define CFG_REGS_UART1_8LINE_UART1_8_LINE (1<<7)
+#define CFG_REGS_DAI_MASK          (3<<8)
+#define CFG_REGS_DAI_I2S           (0<<8)
+#define CFG_REGS_DAI_DAI           (1<<8)
+#define CFG_REGS_DAI_DAI_SIMPLE    (2<<8)
+#define CFG_REGS_KEYIN_3_MASK      (1<<10)
+#define CFG_REGS_KEYIN_3_SPI2_CS_1 (0<<10)
+#define CFG_REGS_KEYIN_3_KEYIN_3   (1<<10)
+#define CFG_REGS_LPSCO_1_MASK      (1<<11)
+#define CFG_REGS_LPSCO_1_KEYIN_4   (0<<11)
+#define CFG_REGS_LPSCO_1_LPSCO_1   (1<<11)
+#define CFG_REGS_SPI1_CS_2_MASK    (1<<12)
+#define CFG_REGS_SPI1_CS_2_KEYIN_1 (0<<12)
+#define CFG_REGS_SPI1_CS_2_SPI1_CS_2 (1<<12)
+#define CFG_REGS_I2S_DI_2_MASK     (1<<13)
+#define CFG_REGS_I2S_DI_2_KEYIN_2  (0<<13)
+#define CFG_REGS_I2S_DI_2_I2S_DI_2 (1<<13)
+#define CFG_REGS_TCO_0_MASK        (1<<14)
+#define CFG_REGS_TCO_0_KEYOUT_0    (0<<14)
+#define CFG_REGS_TCO_0_TCO_0       (1<<14)
+#define CFG_REGS_TCO_1_MASK        (1<<15)
+#define CFG_REGS_TCO_1_KEYOUT_1    (0<<15)
+#define CFG_REGS_TCO_1_TCO_1       (1<<15)
+#define CFG_REGS_TCO_2_MASK        (1<<16)
+#define CFG_REGS_TCO_2_KEYOUT_2    (0<<16)
+#define CFG_REGS_TCO_2_TCO_2       (1<<16)
+#define CFG_REGS_KEYOUT_3_4_MASK   (1<<17)
+#define CFG_REGS_KEYOUT_3_4_I2C3   (0<<17)
+#define CFG_REGS_KEYOUT_3_4_KEYOUT_3_4 (1<<17)
+#define CFG_REGS_KEYOUT_6_MASK     (1<<18)
+#define CFG_REGS_KEYOUT_6_UART2_RTS (0<<18)
+#define CFG_REGS_KEYOUT_6_KEYOUT_6 (1<<18)
+#define CFG_REGS_KEYOUT_7_MASK     (1<<19)
+#define CFG_REGS_KEYOUT_7_UART1_RTS (0<<19)
+#define CFG_REGS_KEYOUT_7_KEYOUT_7 (1<<19)
+#define CFG_REGS_GPO_0_MASK        (3<<20)
+#define CFG_REGS_GPO_0_GPO_0       (0<<20)
+#define CFG_REGS_GPO_0_PWT         (1<<20)
+#define CFG_REGS_GPO_0_KEYIN_5     (2<<20)
+#define CFG_REGS_GPO_1_MASK        (3<<22)
+#define CFG_REGS_GPO_1_GPO_1       (0<<22)
+#define CFG_REGS_GPO_1_LPG         (1<<22)
+#define CFG_REGS_GPO_1_KEYOUT_5    (2<<22)
+#define CFG_REGS_GPO_2_MASK        (3<<24)
+#define CFG_REGS_GPO_2_GPO_2       (0<<24)
+#define CFG_REGS_GPO_2_PWL_1       (1<<24)
+#define CFG_REGS_GPO_2_CLK_32K     (2<<24)
+#define CFG_REGS_GPO_3_MASK        (1<<26)
+#define CFG_REGS_GPO_3_LCD_CS_1    (0<<26)
+#define CFG_REGS_GPO_3_GPO_3       (1<<26)
+#define CFG_REGS_GPO_4_MASK        (1<<27)
+#define CFG_REGS_GPO_4_LCD_CS_0    (0<<27)
+#define CFG_REGS_GPO_4_GPO_4       (1<<27)
+#define CFG_REGS_CLK_OUT_MASK      (1<<28)
+#define CFG_REGS_CLK_OUT_HST_CLK   (0<<28)
+#define CFG_REGS_CLK_OUT_CLK_OUT   (1<<28)
+#define CFG_REGS_DEBUG_MASK        (1<<29)
+#define CFG_REGS_DEBUG_NONE        (0<<29)
+#define CFG_REGS_DEBUG_DEBUG_MONITOR (1<<29)
+#define CFG_REGS_AP_SPI1_MASK      (1<<30)
+#define CFG_REGS_AP_SPI1_BB_SPI1   (0<<30)
+#define CFG_REGS_AP_SPI1_AP_SPI1   (1<<30)
+#define CFG_REGS_RGB_CAM_MASK      (1<<31)
+#define CFG_REGS_RGB_CAM_DISABLE   (0<<31)
+#define CFG_REGS_RGB_CAM_ENABLE    (1<<31)
+
+//IO_Drive1_Select
+#define CFG_REGS_DDR_DRIVE_MASK    (7<<0)
+#define CFG_REGS_DDR_DRIVE_FAST_AND_MOST_WEAK (7<<0)
+#define CFG_REGS_DDR_DRIVE_FAST_AND_WEAK (6<<0)
+#define CFG_REGS_DDR_DRIVE_FAST_AND_STRONG (5<<0)
+#define CFG_REGS_DDR_DRIVE_FAST_AND_MOST_STRONG (4<<0)
+#define CFG_REGS_DDR_DRIVE_SLOW_AND_MOST_WEAK (3<<0)
+#define CFG_REGS_DDR_DRIVE_SLOW_AND_WEAK (2<<0)
+#define CFG_REGS_DDR_DRIVE_SLOW_AND_STRONG (1<<0)
+#define CFG_REGS_DDR_DRIVE_SLOW_AND_MOST_STRONG (0<<0)
+#define CFG_REGS_PSRAM1_DRIVE_MASK (7<<3)
+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_MOST_WEAK (7<<3)
+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_WEAK (6<<3)
+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_STRONG (5<<3)
+#define CFG_REGS_PSRAM1_DRIVE_FAST_AND_MOST_STRONG (4<<3)
+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_MOST_WEAK (3<<3)
+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_WEAK (2<<3)
+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_STRONG (1<<3)
+#define CFG_REGS_PSRAM1_DRIVE_SLOW_AND_MOST_STRONG (0<<3)
+#define CFG_REGS_PSRAM2_DRIVE_MASK (7<<6)
+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_MOST_WEAK (7<<6)
+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_WEAK (6<<6)
+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_STRONG (5<<6)
+#define CFG_REGS_PSRAM2_DRIVE_FAST_AND_MOST_STRONG (4<<6)
+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_MOST_WEAK (3<<6)
+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_WEAK (2<<6)
+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_STRONG (1<<6)
+#define CFG_REGS_PSRAM2_DRIVE_SLOW_AND_MOST_STRONG (0<<6)
+#define CFG_REGS_NFLSH_DRIVE_MASK  (7<<9)
+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_MOST_WEAK (7<<9)
+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_WEAK (6<<9)
+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_STRONG (5<<9)
+#define CFG_REGS_NFLSH_DRIVE_FAST_AND_MOST_STRONG (4<<9)
+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_MOST_WEAK (3<<9)
+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_WEAK (2<<9)
+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_STRONG (1<<9)
+#define CFG_REGS_NFLSH_DRIVE_SLOW_AND_MOST_STRONG (0<<9)
+#define CFG_REGS_LCD1_DRIVE_MASK   (7<<12)
+#define CFG_REGS_LCD1_DRIVE_FAST_AND_MOST_WEAK (7<<12)
+#define CFG_REGS_LCD1_DRIVE_FAST_AND_WEAK (6<<12)
+#define CFG_REGS_LCD1_DRIVE_FAST_AND_STRONG (5<<12)
+#define CFG_REGS_LCD1_DRIVE_FAST_AND_MOST_STRONG (4<<12)
+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_MOST_WEAK (3<<12)
+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_WEAK (2<<12)
+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_STRONG (1<<12)
+#define CFG_REGS_LCD1_DRIVE_SLOW_AND_MOST_STRONG (0<<12)
+#define CFG_REGS_LCD2_DRIVE_MASK   (7<<15)
+#define CFG_REGS_LCD2_DRIVE_FAST_AND_MOST_WEAK (7<<15)
+#define CFG_REGS_LCD2_DRIVE_FAST_AND_WEAK (6<<15)
+#define CFG_REGS_LCD2_DRIVE_FAST_AND_STRONG (5<<15)
+#define CFG_REGS_LCD2_DRIVE_FAST_AND_MOST_STRONG (4<<15)
+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_MOST_WEAK (3<<15)
+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_WEAK (2<<15)
+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_STRONG (1<<15)
+#define CFG_REGS_LCD2_DRIVE_SLOW_AND_MOST_STRONG (0<<15)
+#define CFG_REGS_SDAT1_DRIVE_MASK  (7<<18)
+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_MOST_WEAK (7<<18)
+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_WEAK (6<<18)
+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_STRONG (5<<18)
+#define CFG_REGS_SDAT1_DRIVE_FAST_AND_MOST_STRONG (4<<18)
+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_MOST_WEAK (3<<18)
+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_WEAK (2<<18)
+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_STRONG (1<<18)
+#define CFG_REGS_SDAT1_DRIVE_SLOW_AND_MOST_STRONG (0<<18)
+#define CFG_REGS_SDAT2_DRIVE_MASK  (7<<21)
+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_MOST_WEAK (7<<21)
+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_WEAK (6<<21)
+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_STRONG (5<<21)
+#define CFG_REGS_SDAT2_DRIVE_FAST_AND_MOST_STRONG (4<<21)
+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_MOST_WEAK (3<<21)
+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_WEAK (2<<21)
+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_STRONG (1<<21)
+#define CFG_REGS_SDAT2_DRIVE_SLOW_AND_MOST_STRONG (0<<21)
+#define CFG_REGS_CAM_DRIVE_MASK    (3<<24)
+#define CFG_REGS_CAM_DRIVE_MOST_STRONG (0<<24)
+#define CFG_REGS_CAM_DRIVE_STRONG  (1<<24)
+#define CFG_REGS_CAM_DRIVE_WEAK    (2<<24)
+#define CFG_REGS_CAM_DRIVE_MOST_WEAK (3<<24)
+#define CFG_REGS_SIM1_DRIVE_MASK   (3<<26)
+#define CFG_REGS_SIM1_DRIVE_MOST_STRONG (0<<26)
+#define CFG_REGS_SIM1_DRIVE_STRONG (1<<26)
+#define CFG_REGS_SIM1_DRIVE_WEAK   (2<<26)
+#define CFG_REGS_SIM1_DRIVE_MOST_WEAK (3<<26)
+#define CFG_REGS_SIM2_DRIVE_MASK   (3<<28)
+#define CFG_REGS_SIM2_DRIVE_MOST_STRONG (0<<28)
+#define CFG_REGS_SIM2_DRIVE_STRONG (1<<28)
+#define CFG_REGS_SIM2_DRIVE_WEAK   (2<<28)
+#define CFG_REGS_SIM2_DRIVE_MOST_WEAK (3<<28)
+#define CFG_REGS_SIM3_DRIVE_MASK   (3<<30)
+#define CFG_REGS_SIM3_DRIVE_MOST_STRONG (0<<30)
+#define CFG_REGS_SIM3_DRIVE_STRONG (1<<30)
+#define CFG_REGS_SIM3_DRIVE_WEAK   (2<<30)
+#define CFG_REGS_SIM3_DRIVE_MOST_WEAK (3<<30)
+
+//IO_Drive2_Select
+#define CFG_REGS_GPIO_DRIVE_MASK   (3<<0)
+#define CFG_REGS_GPIO_DRIVE_MOST_STRONG (0<<0)
+#define CFG_REGS_GPIO_DRIVE_STRONG (1<<0)
+#define CFG_REGS_GPIO_DRIVE_WEAK   (2<<0)
+#define CFG_REGS_GPIO_DRIVE_MOST_WEAK (3<<0)
+#define CFG_REGS_CAM2_DRIVE_MASK   (3<<2)
+#define CFG_REGS_CAM2_DRIVE_MOST_STRONG (0<<2)
+#define CFG_REGS_CAM2_DRIVE_STRONG (1<<2)
+#define CFG_REGS_CAM2_DRIVE_WEAK   (2<<2)
+#define CFG_REGS_CAM2_DRIVE_MOST_WEAK (3<<2)
+
+//RAM_DRIVE
+#define CFG_REGS_MBRAM_A(n)        (((n)&7)<<0)
+#define CFG_REGS_MBRAM_A_MASK      (7<<0)
+#define CFG_REGS_MBRAM_A_SHIFT     (0)
+#define CFG_REGS_MBRAM_W(n)        (((n)&3)<<3)
+#define CFG_REGS_MBRAM_W_MASK      (3<<3)
+#define CFG_REGS_MBRAM_W_SHIFT     (3)
+#define CFG_REGS_MBRAM_R           (1<<5)
+#define CFG_REGS_BBRAM_A(n)        (((n)&7)<<6)
+#define CFG_REGS_BBRAM_A_MASK      (7<<6)
+#define CFG_REGS_BBRAM_A_SHIFT     (6)
+#define CFG_REGS_BBRAM_W(n)        (((n)&3)<<9)
+#define CFG_REGS_BBRAM_W_MASK      (3<<9)
+#define CFG_REGS_BBRAM_W_SHIFT     (9)
+#define CFG_REGS_BBRAM_R           (1<<11)
+#define CFG_REGS_XP_A(n)           (((n)&7)<<12)
+#define CFG_REGS_XP_A_MASK         (7<<12)
+#define CFG_REGS_XP_A_SHIFT        (12)
+#define CFG_REGS_XP_W(n)           (((n)&3)<<15)
+#define CFG_REGS_XP_W_MASK         (3<<15)
+#define CFG_REGS_XP_W_SHIFT        (15)
+#define CFG_REGS_XP_R              (1<<17)
+#define CFG_REGS_BP_A(n)           (((n)&7)<<18)
+#define CFG_REGS_BP_A_MASK         (7<<18)
+#define CFG_REGS_BP_A_SHIFT        (18)
+#define CFG_REGS_BP_W(n)           (((n)&3)<<21)
+#define CFG_REGS_BP_W_MASK         (3<<21)
+#define CFG_REGS_BP_W_SHIFT        (21)
+#define CFG_REGS_BP_R              (1<<23)
+#define CFG_REGS_EV_A(n)           (((n)&7)<<24)
+#define CFG_REGS_EV_A_MASK         (7<<24)
+#define CFG_REGS_EV_A_SHIFT        (24)
+#define CFG_REGS_EV_W(n)           (((n)&3)<<27)
+#define CFG_REGS_EV_W_MASK         (3<<27)
+#define CFG_REGS_EV_W_SHIFT        (27)
+#define CFG_REGS_EV_R              (1<<29)
+
+//H2X_AP_Offset
+#define CFG_REGS_H2X_AP_OFFSET(n)  (((n)&0xFF)<<0)
+#define CFG_REGS_H2X_AP_OFFSET_MASK (0xFF<<0)
+#define CFG_REGS_H2X_AP_OFFSET_SHIFT (0)
+
+//audio_pd_set
+#define CFG_REGS_AU_DEEP_PD_N      (1<<0)
+#define CFG_REGS_AU_REF_PD_N       (1<<1)
+#define CFG_REGS_AU_MIC_PD_N       (1<<2)
+#define CFG_REGS_AU_AUXMIC_PD_N    (1<<3)
+#define CFG_REGS_AU_AD_PD_N        (1<<4)
+#define CFG_REGS_AU_DAC_PD_N       (1<<5)
+#define CFG_REGS_AU_DAC_RESET_N    (1<<8)
+#define CFG_REGS_AU_PLL_PU         (1<<16)
+
+//audio_pd_clr
+//#define CFG_REGS_AU_DEEP_PD_N    (1<<0)
+//#define CFG_REGS_AU_REF_PD_N     (1<<1)
+//#define CFG_REGS_AU_MIC_PD_N     (1<<2)
+//#define CFG_REGS_AU_AUXMIC_PD_N  (1<<3)
+//#define CFG_REGS_AU_AD_PD_N      (1<<4)
+//#define CFG_REGS_AU_DAC_PD_N     (1<<5)
+//#define CFG_REGS_AU_DAC_RESET_N  (1<<8)
+//#define CFG_REGS_AU_PLL_PU       (1<<16)
+
+//audio_sel_cfg
+#define CFG_REGS_AU_AUXMIC_SEL     (1<<0)
+#define CFG_REGS_AU_SPK_SEL        (1<<1)
+#define CFG_REGS_AU_SPK_MONO_SEL   (1<<2)
+#define CFG_REGS_AU_RCV_SEL        (1<<3)
+#define CFG_REGS_AU_HEAD_SEL       (1<<4)
+
+//audio_mic_cfg
+#define CFG_REGS_AU_MIC_GAIN(n)    (((n)&15)<<0)
+#define CFG_REGS_AU_MIC_GAIN_MASK  (15<<0)
+#define CFG_REGS_AU_MIC_GAIN_SHIFT (0)
+#define CFG_REGS_AU_MIC_MUTE_N     (1<<4)
+
+//audio_spk_cfg
+#define CFG_REGS_AU_SPK_GAIN(n)    (((n)&15)<<0)
+#define CFG_REGS_AU_SPK_GAIN_MASK  (15<<0)
+#define CFG_REGS_AU_SPK_GAIN_SHIFT (0)
+#define CFG_REGS_AU_SPK_MUTE_N     (1<<4)
+#define CFG_REGS_AU_SPK_VOC_GAIN_EN (1<<8)
+
+//audio_rcv_gain
+#define CFG_REGS_AU_RCV_GAIN(n)    (((n)&15)<<0)
+#define CFG_REGS_AU_RCV_GAIN_MASK  (15<<0)
+#define CFG_REGS_AU_RCV_GAIN_SHIFT (0)
+#define CFG_REGS_AU_RCV_VOC_GAIN_EN (1<<8)
+
+//audio_head_gain
+#define CFG_REGS_AU_HEAD_GAIN(n)   (((n)&15)<<0)
+#define CFG_REGS_AU_HEAD_GAIN_MASK (15<<0)
+#define CFG_REGS_AU_HEAD_GAIN_SHIFT (0)
+#define CFG_REGS_AU_HEAD_VOC_GAIN_EN (1<<8)
+
+//TSC_DATA
+#define CFG_REGS_TSC_X_VALUE_BIT(n) (((n)&0x3FF)<<0)
+#define CFG_REGS_TSC_X_VALUE_BIT_MASK (0x3FF<<0)
+#define CFG_REGS_TSC_X_VALUE_BIT_SHIFT (0)
+#define CFG_REGS_TSC_X_VALUE_VALID (1<<10)
+#define CFG_REGS_TSC_Y_VALUE_BIT(n) (((n)&0x3FF)<<11)
+#define CFG_REGS_TSC_Y_VALUE_BIT_MASK (0x3FF<<11)
+#define CFG_REGS_TSC_Y_VALUE_BIT_SHIFT (11)
+#define CFG_REGS_TSC_Y_VALUE_VALID (1<<21)
+
+//GPADC_DATA_CH
+#define CFG_REGS_GPADC_DATA(n)     (((n)&0x3FF)<<0)
+#define CFG_REGS_GPADC_DATA_MASK   (0x3FF<<0)
+#define CFG_REGS_GPADC_DATA_SHIFT  (0)
+#define CFG_REGS_GPADC_VALID       (1<<10)
+#define CFG_REGS_GPADC_CH_EN       (1<<31)
+
+//Alt_mux_select2
+#define CFG_REGS_UART1_SDIO2_MASK  (1<<0)
+#define CFG_REGS_UART1_SDIO2_SDIO2 (0<<0)
+#define CFG_REGS_UART1_SDIO2_UART1 (1<<0)
+#define CFG_REGS_JTAG_EN_MASK      (1<<1)
+#define CFG_REGS_JTAG_EN_DISABLE   (0<<1)
+#define CFG_REGS_JTAG_EN_ENABLE    (1<<1)
+#define CFG_REGS_LCD_RGB_17_16_MASK (1<<2)
+#define CFG_REGS_LCD_RGB_17_16_LCD_CS (0<<2)
+#define CFG_REGS_LCD_RGB_17_16_LCD_DATA (1<<2)
+#define CFG_REGS_CSI2_2_MASK       (3<<3)
+#define CFG_REGS_CSI2_2_PARALLEL_CAM (0<<3)
+#define CFG_REGS_CSI2_2_CSI2       (1<<3)
+#define CFG_REGS_CSI2_2_SPI_CAM    (2<<3)
+#define CFG_REGS_RGB_CAM_2_MASK    (1<<5)
+#define CFG_REGS_RGB_CAM_2_DISABLE (0<<5)
+#define CFG_REGS_RGB_CAM_2_ENABLE  (1<<5)
+#define CFG_REGS_MAC_EN_MASK       (1<<6)
+#define CFG_REGS_MAC_EN_DISABLE    (0<<6)
+#define CFG_REGS_MAC_EN_ENABLE     (1<<6)
+#define CFG_REGS_IOMUX_CFG_RESERVED(n) (((n)&0x1FFFFFF)<<7)
+
+//AP_GPIO_E_Mode
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_MASK (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_SHIFT (0)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_ALT (0<<0)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SCL_GPIO (1<<0)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA (1<<1)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_MASK (1<<1)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_SHIFT (1)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_ALT (0<<1)
+#define CFG_REGS_MODE_AP_PIN_I2CBB_SDA_GPIO (1<<1)
+#define CFG_REGS_MODE_AP_PIN_CAM2_RST (1<<2)
+#define CFG_REGS_MODE_AP_PIN_CAM2_RST_MASK (1<<2)
+#define CFG_REGS_MODE_AP_PIN_CAM2_RST_SHIFT (2)
+#define CFG_REGS_MODE_AP_PIN_CAM2_RST_ALT (0<<2)
+#define CFG_REGS_MODE_AP_PIN_CAM2_RST_GPIO (1<<2)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PDN (1<<3)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_MASK (1<<3)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_SHIFT (3)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_ALT (0<<3)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PDN_GPIO (1<<3)
+#define CFG_REGS_MODE_AP_PIN_CAM2_CLK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_MASK (1<<4)
+#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_SHIFT (4)
+#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_ALT (0<<4)
+#define CFG_REGS_MODE_AP_PIN_CAM2_CLK_GPIO (1<<4)
+#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC (1<<5)
+#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_MASK (1<<5)
+#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_SHIFT (5)
+#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_ALT (0<<5)
+#define CFG_REGS_MODE_AP_PIN_CAM2_VSYNC_GPIO (1<<5)
+#define CFG_REGS_MODE_AP_PIN_CAM2_HREF (1<<6)
+#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_MASK (1<<6)
+#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_SHIFT (6)
+#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_ALT (0<<6)
+#define CFG_REGS_MODE_AP_PIN_CAM2_HREF_GPIO (1<<6)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_MASK (1<<7)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_SHIFT (7)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_ALT (0<<7)
+#define CFG_REGS_MODE_AP_PIN_CAM2_PCLK_GPIO (1<<7)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0 (1<<8)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_MASK (1<<8)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_SHIFT (8)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_ALT (0<<8)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_0_GPIO (1<<8)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1 (1<<9)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_MASK (1<<9)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_SHIFT (9)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_ALT (0<<9)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_1_GPIO (1<<9)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2 (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_MASK (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_SHIFT (10)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_ALT (0<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_2_GPIO (1<<10)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3 (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_MASK (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_SHIFT (11)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_ALT (0<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_3_GPIO (1<<11)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4 (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_MASK (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_SHIFT (12)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_ALT (0<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_4_GPIO (1<<12)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5 (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_MASK (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_SHIFT (13)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_ALT (0<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_5_GPIO (1<<13)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6 (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_MASK (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_SHIFT (14)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_ALT (0<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_6_GPIO (1<<14)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7 (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_MASK (1<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_SHIFT (15)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_ALT (0<<15)
+#define CFG_REGS_MODE_AP_PIN_CAM2_DATA_7_GPIO (1<<15)
+#define CFG_REGS_AP_GPIO_E_MODE(n) (((n)&0xFFFF)<<0)
+#define CFG_REGS_AP_GPIO_E_MODE_MASK (0xFFFF<<0)
+#define CFG_REGS_AP_GPIO_E_MODE_SHIFT (0)
+
+
+
+
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/reg_gpio.h b/arch/arm/include/asm/arch-rda/reg_gpio.h
new file mode 100644
index 0000000000..e26f099ec3
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_gpio.h
@@ -0,0 +1,141 @@
+//==============================================================================
+//
+//            Copyright (C) 2012-2013, RDA Microelectronics.
+//                            All Rights Reserved
+//
+//      This source code is the property of RDA Microelectronics and is
+//      confidential.  Any  modification, distribution,  reproduction or
+//      exploitation  of  any content of this file is totally forbidden,
+//      except  with the  written permission  of   RDA Microelectronics.
+//
+//==============================================================================
+//
+//    THIS FILE WAS GENERATED FROM ITS CORRESPONDING XML VERSION WITH COOLXML.
+//
+//                       !!! PLEASE DO NOT EDIT !!!
+//
+//  $HeadURL$
+//  $Author$
+//  $Date$
+//  $Revision$
+//
+//==============================================================================
+//
+/// @file
+//
+//==============================================================================
+
+#ifndef _REG_GPIO_H_
+#define _REG_GPIO_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+#define IDX_GPIO_DCON                           (0)
+#define IDX_GPO_CHG                             (0)
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+// ============================================================================
+// GPIO_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+typedef volatile struct
+{
+    REG32                          gpio_oen_val;                 //0x00000000
+    REG32                          gpio_oen_set_out;             //0x00000004
+    REG32                          gpio_oen_set_in;              //0x00000008
+    REG32                          gpio_val;                     //0x0000000C
+    REG32                          gpio_set;                     //0x00000010
+    REG32                          gpio_clr;                     //0x00000014
+    REG32                          gpint_ctrl_set;               //0x00000018
+    REG32                          gpint_ctrl_clr;               //0x0000001C
+    REG32                          int_clr;                      //0x00000020
+    REG32                          int_status;                   //0x00000024
+    REG32                          chg_ctrl;                     //0x00000028
+    REG32                          chg_cmd;                      //0x0000002C
+    REG32                          gpo_set;                      //0x00000030
+    REG32                          gpo_clr;                      //0x00000034
+} HWP_GPIO_T;
+
+#define hwp_apGpioA                ((HWP_GPIO_T*) (RDA_GPIO_A_BASE))
+#define hwp_apGpioB                ((HWP_GPIO_T*) (RDA_GPIO_B_BASE))
+#define hwp_apGpioD                ((HWP_GPIO_T*) (RDA_GPIO_D_BASE))
+#if defined(CONFIG_MACH_RDA8810E) || defined(CONFIG_MACH_RDA8810H)
+#define hwp_apGpioE                ((HWP_GPIO_T*) (RDA_GPIO_E_BASE))
+#endif
+#define hwp_gpio                   ((HWP_GPIO_T*) (RDA_GPIO_BASE))
+
+
+//gpio_oen_val
+#define GPIO_OEN_VAL(n)            (((n)&0xFFFFFFFF)<<0)
+#define GPIO_OEN_VAL_INPUT         (0x1<<0)
+#define GPIO_OEN_VAL_OUTPUT        (0x0<<0)
+
+//gpio_oen_set_out
+#define GPIO_OEN_SET_OUT(n)        (((n)&0xFFFFFFFF)<<0)
+
+//gpio_oen_set_in
+#define GPIO_OEN_SET_IN(n)         (((n)&0xFFFFFFFF)<<0)
+
+//gpio_val
+#define GPIO_GPIO_VAL(n)           (((n)&0xFFFFFFFF)<<0)
+
+//gpio_set
+#define GPIO_GPIO_SET(n)           (((n)&0xFFFFFFFF)<<0)
+
+//gpio_clr
+#define GPIO_GPIO_CLR(n)           (((n)&0xFFFFFFFF)<<0)
+
+//gpint_ctrl_set
+#define GPIO_GPINT_R_SET(n)        (((n)&0xFF)<<0)
+#define GPIO_GPINT_F_SET(n)        (((n)&0xFF)<<8)
+#define GPIO_DBN_EN_SET(n)         (((n)&0xFF)<<16)
+#define GPIO_GPINT_MODE_SET(n)     (((n)&0xFF)<<24)
+
+//gpint_ctrl_clr
+#define GPIO_GPINT_R_CLR(n)        (((n)&0xFF)<<0)
+#define GPIO_GPINT_F_CLR(n)        (((n)&0xFF)<<8)
+#define GPIO_DBN_EN_CLR(n)         (((n)&0xFF)<<16)
+#define GPIO_GPINT_MODE_CLR(n)     (((n)&0xFF)<<24)
+
+//int_clr
+#define GPIO_GPINT_CLR(n)          (((n)&0xFF)<<0)
+
+//int_status
+#define GPIO_GPINT_STATUS(n)       (((n)&0xFF)<<0)
+#define GPIO_GPINT_STATUS_MASK     (0xFF<<0)
+#define GPIO_GPINT_STATUS_SHIFT    (0)
+
+//chg_ctrl
+#define GPIO_OUT_TIME(n)           (((n)&15)<<0)
+#define GPIO_WAIT_TIME(n)          (((n)&0x3F)<<4)
+#define GPIO_INT_MODE_L2H          (0<<16)
+#define GPIO_INT_MODE_H2L          (1<<16)
+#define GPIO_INT_MODE_RR           (3<<16)
+
+//chg_cmd
+#define GPIO_DCON_MODE_SET         (1<<0)
+#define GPIO_CHG_MODE_SET          (1<<4)
+#define GPIO_DCON_MODE_CLR         (1<<8)
+#define GPIO_CHG_MODE_CLR          (1<<12)
+#define GPIO_CHG_DOWN              (1<<24)
+
+//gpo_set
+#define GPIO_GPO_SET(n)            (((n)&31)<<0)
+
+//gpo_clr
+#define GPIO_GPO_CLR(n)            (((n)&31)<<0)
+
+
+
+
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/reg_i2c.h b/arch/arm/include/asm/arch-rda/reg_i2c.h
new file mode 100644
index 0000000000..8b39b9f527
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_i2c.h
@@ -0,0 +1,93 @@
+#ifndef _REG_I2C_H_
+#define _REG_I2C_H_
+
+//#include "iomap.h"
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+// ============================================================================
+// I2C_MASTER_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef volatile struct
+{
+    REG32                          CTRL;                         //0x00000000
+    REG32                          STATUS;                       //0x00000004
+    REG32                          TXRX_BUFFER;                  //0x00000008
+    REG32                          CMD;                          //0x0000000C
+    REG32                          IRQ_CLR;                      //0x00000010
+    REG32			   CTRL1;	                 //0x00000014
+} HWP_I2C_MASTER_T;
+
+#define hwp_i2cMaster               ((HWP_I2C_MASTER_T*)(RDA_I2C1_BASE))
+#define hwp_i2cMaster2              ((HWP_I2C_MASTER_T*)(RDA_I2C2_BASE))
+#define hwp_i2cMaster3              ((HWP_I2C_MASTER_T*)(RDA_I2C3_BASE))
+
+//CTRL
+#define I2C_MASTER_EN               (1<<0)
+#define I2C_MASTER_CLEAR_FIFO	    (1<<7)
+#define I2C_MASTER_IRQ_MASK         (1<<8)
+#define I2C_MASTER_TX_FIFO_THRESHOLD(n) (((n)&0x1F)<<1)
+#define I2C_MASTER_TX_FIFO_THRESHOLD_MASK (0x1F<<1)
+#define I2C_MASTER_RX_READ_NUM(n) (((n)&0x1F)<<9)
+#define I2C_MASTER_RX_READ_NUM_MASK  (0x1F <<9)
+#define I2C_MASTER_TIMEOUT_THRESHOLD_MASK	(0x3<<14)
+#define I2C_MASTER_TIMEOUT_THRESHOLD_SHIFT	14
+#define I2C_MASTER_CLOCK_PRESCALE(n) (((n)&0xFFFF)<<16)
+#define I2C_MASTER_CLOCK_PRESCALE_MASK (0xFFFF<<16)
+
+//CTRL1
+#define I2C_MASTER_DMA_MODE (1 << 0)
+#define I2C_MASTER_TXFIFO_OVER_IRQ_MASK         (1<<1)
+#define I2C_MASTER_TXFIFO_UNDER_IRQ_MASK         (1<<2)
+#define I2C_MASTER_RXFIFO_OVER_IRQ_MASK         (1<<3)
+#define I2C_MASTER_RXFIFO_UNDER_IRQ_MASK         (1<<4)
+#define I2C_MASTER_TXFIFO_EMPTY_IRQ_MASK         (1<<5)
+#define I2C_MASTER_RXFIFO_NUM_IRQ_MASK         (1<<6)
+#define I2C_MASTER_TX_DMA_IRQ_MASK         (1<<7)
+#define I2C_MASTER_RX_DMA_IRQ_MASK         (1<<8)
+#define I2C_MASTER_TX_DMA_COUNTER(n)  (((n)&0x7FF)<< 9)
+#define I2C_MASTER_TX_DMA_COUNTER_MASK (0x7FF<<9)
+#define I2C_MASTER_RX_DMA_COUNTER(n)  (((n)&0x7FF)<< 20)
+#define I2C_MASTER_RX_DMA_COUNTER_MASK (0x7FF<<20)
+
+//STATUS
+#define I2C_MASTER_IRQ_CAUSE        (1<<0)
+#define I2C_MASTER_IRQ_TX_DMA        (1<<1)
+#define I2C_MASTER_IRQ_RX_DMA        (1<<2)
+#define I2C_MASTER_IRQ_STATUS       (1<<4)
+#define I2C_MASTER_IRQ_TX_DMA_DONE        (1<<5)
+#define I2C_MASTER_IRQ_RX_DMA_DONE        (1<<6)
+#define I2C_MASTER_TIP              (1<<8)
+#define I2C_MASTER_AL               (1<<12)
+#define I2C_MASTER_BUSY             (1<<16)
+#define I2C_MASTER_IRQ_RX_OVF       (1<<17)
+#define I2C_MASTER_IRQ_RX_UDF       (1<<18)
+#define I2C_MASTER_IRQ_TX_OVF       (1<<19)
+#define I2C_MASTER_IRQ_TX_UDF       (1<<20)
+
+//#define I2C_MASTER_RXACK            (1<<20)
+#define I2C_MASTER_RX_FIFO_DATA_NUM(n) (((n)&0x1F)<<21)
+#define I2C_MASTER_RX_FIFO_DATA_NUM_MASK (0x1F<<21)
+#define I2C_MASTER_TX_FIFO_FREE_NUM(n) (((n)&0x1F)<<26)
+#define I2C_MASTER_TX_FIFO_FREE_NUM_MASK (0x1F<<26)
+#define I2C_MASTER_TIMEOUT        (1<<31)
+
+//TXRX_BUFFER
+#define I2C_MASTER_TX_DATA(n)       (((n)&0xFF)<<0)
+#define I2C_MASTER_RX_DATA(n)       (((n)&0xFF)<<0)
+
+//CMD
+#define I2C_MASTER_ACK              (1<<0)
+#define I2C_MASTER_RD               (1<<4)
+#define I2C_MASTER_STO              (1<<8)
+#define I2C_MASTER_FORCE_STO        (1<<9)
+#define I2C_MASTER_WR               (1<<12)
+#define I2C_MASTER_STA              (1<<16)
+
+//IRQ_CLR
+#define I2C_MASTER_IRQ_CLR          (1<<0)
+
+#endif /* _REG_I2C_H_ */
+
diff --git a/arch/arm/include/asm/arch-rda/reg_ifc.h b/arch/arm/include/asm/arch-rda/reg_ifc.h
new file mode 100644
index 0000000000..f5b69ccf98
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_ifc.h
@@ -0,0 +1,5 @@
+#ifdef CONFIG_MACH_RDA8810
+#include "reg_ifc_v1.h"
+#else
+#include "reg_ifc_v3.h"
+#endif
diff --git a/arch/arm/include/asm/arch-rda/reg_ifc_v1.h b/arch/arm/include/asm/arch-rda/reg_ifc_v1.h
new file mode 100644
index 0000000000..e37786fc5d
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_ifc_v1.h
@@ -0,0 +1,106 @@
+#ifndef _REG_IFC_H_
+#define _REG_IFC_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+#define SYS_IFC_ADDR_ALIGN                       (0)
+#define SYS_IFC_TC_LEN                           (23)
+#define SYS_IFC_STD_CHAN_NB                      7      //(SYS_IFC_NB_STD_CHANNEL)
+#define SYS_IFC_RFSPI_CHAN                       (1)
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+// ============================================================================
+// SYS_IFC_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef volatile struct
+{
+    REG32                          get_ch;                       //0x00000000
+    REG32                          dma_status;                   //0x00000004
+    REG32                          debug_status;                 //0x00000008
+    REG32 Reserved_0000000C;                    //0x0000000C
+    struct
+    {
+        REG32                      control;                      //0x00000010
+        REG32                      status;                       //0x00000014
+        REG32                      start_addr;                   //0x00000018
+        REG32                      tc;                           //0x0000001C
+    } std_ch[SYS_IFC_STD_CHAN_NB];
+    // REG32 Reserved_00000080;                 //0x00000080
+    REG32                          ch_rfspi_control;             //0x00000080
+    REG32                          ch_rfspi_status;              //0x00000084
+    REG32                          ch_rfspi_start_addr;          //0x00000088
+    REG32                          ch_rfspi_end_addr;            //0x0000008C
+    REG32                          ch_rfspi_tc;                  //0x00000090
+} HWP_SYS_IFC_T;
+
+#define hwp_sysIfc                  ((HWP_SYS_IFC_T*)(RDA_IFC_BASE))
+
+
+//get_ch
+#define SYS_IFC_CH_TO_USE(n)        (((n)&15)<<0)
+#define SYS_IFC_CH_TO_USE_MASK      (15<<0)
+#define SYS_IFC_CH_TO_USE_SHIFT     (0)
+
+//dma_status
+#define SYS_IFC_CH_ENABLE(n)        (((n)&0xFF)<<0)
+#define SYS_IFC_CH_BUSY(n)          (((n)&0x7F)<<16)
+
+//debug_status
+#define SYS_IFC_DBG_STATUS          (1<<0)
+
+//control
+#define SYS_IFC_ENABLE              (1<<0)
+#define SYS_IFC_DISABLE             (1<<1)
+#define SYS_IFC_CH_RD_HW_EXCH       (1<<2)
+#define SYS_IFC_CH_WR_HW_EXCH       (1<<3)
+#define SYS_IFC_AUTODISABLE         (1<<4)
+#define SYS_IFC_SIZE(n)             (((n)&3)<<5)
+#define SYS_IFC_SIZE_MASK           (3<<5)
+#define SYS_IFC_SIZE_SHIFT          (5)
+#define SYS_IFC_SIZE_BYTE           (0<<5)
+#define SYS_IFC_SIZE_HALF_WORD      (1<<5)
+#define SYS_IFC_SIZE_WORD           (2<<5)
+#define SYS_IFC_REQ_SRC(n)          (((n)&31)<<8)
+#define SYS_IFC_REQ_SRC_MASK        (31<<8)
+#define SYS_IFC_REQ_SRC_SHIFT       (8)
+#define SYS_IFC_FLUSH               (1<<16)
+
+//status
+//#define SYS_IFC_ENABLE            (1<<0)
+#define SYS_IFC_FIFO_EMPTY          (1<<4)
+
+//start_addr
+#define SYS_IFC_START_ADDR(n)       (((n)&0x3FFFFFF)<<0)
+
+//tc
+#define SYS_IFC_TC(n)               (((n)&0x7FFFFF)<<0)
+
+//ch_rfspi_control
+//#define SYS_IFC_ENABLE            (1<<0)
+//#define SYS_IFC_DISABLE           (1<<1)
+
+//ch_rfspi_status
+//#define SYS_IFC_ENABLE            (1<<0)
+//#define SYS_IFC_FIFO_EMPTY        (1<<4)
+#define SYS_IFC_FIFO_LEVEL(n)       (((n)&31)<<8)
+
+//ch_rfspi_start_addr
+#define SYS_IFC_START_AHB_ADDR(n)   (((n)&0x3FFFFFF)<<0)
+
+//ch_rfspi_end_addr
+#define SYS_IFC_END_AHB_ADDR(n)     (((n)&0x3FFFFFF)<<0)
+
+//ch_rfspi_tc
+//#define SYS_IFC_TC(n)             (((n)&0x3FFF)<<0)
+
+#endif /* _REG_IFC_H_ */
+
diff --git a/arch/arm/include/asm/arch-rda/reg_ifc_v3.h b/arch/arm/include/asm/arch-rda/reg_ifc_v3.h
new file mode 100644
index 0000000000..ecbb137aba
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_ifc_v3.h
@@ -0,0 +1,207 @@
+#ifndef _REG_IFC_H_
+#define _REG_IFC_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+#define SYS_IFC_STD_CHAN_NB                      (8)      //(SYS_IFC_NB_STD_CHANNEL)
+#define SYS_IFC_STD_CHAN_NB_SCATTER              (3)
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+// ============================================================================
+// SYS_IFC_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef volatile struct
+{
+    REG32                          get_ch;                       //0x00000000
+    REG32                          dma_status;                   //0x00000004
+    REG32                          debug_status;                 //0x00000008
+    REG32 Reserved_0000000C;                    //0x0000000C
+    union 
+    {
+    struct
+    {
+        REG32                      control;                      //0x00000010
+        REG32                      status;                       //0x00000014
+        REG32                      start_addr1;                  //0x00000018
+        REG32                      tc1;                          //0x0000001C
+        REG32                      start_addr2;                  //0x00000020
+        REG32                      tc2;                          //0x00000024
+        REG32                      start_addr3;                  //0x00000028
+        REG32                      tc3;                          //0x0000002C
+        REG32                      start_addr4;                  //0x00000030
+        REG32                      tc4;                          //0x00000034
+        REG32                      start_addr5;                  //0x00000038
+        REG32                      tc5;                          //0x0000003C
+        REG32                      start_addr6;                  //0x00000040
+        REG32                      tc6;                          //0x00000044
+        REG32                      start_addr7;                  //0x00000048
+        REG32                      tc7;                          //0x0000004C
+        REG32                      start_addr8;                  //0x00000050
+        REG32                      tc8;                          //0x00000054
+        REG32 Reserved_00000048[14];            //0x00000048
+    } std_ch_scatter[SYS_IFC_STD_CHAN_NB_SCATTER];
+    struct
+    {
+        REG32                      control;                      //0x00000190
+        REG32                      status;                       //0x00000194
+        REG32                      start_addr;                   //0x00000198
+        REG32                      tc;                           //0x0000019C
+        REG32 Reserved_00000010[28];            //0x00000010
+    } std_ch[SYS_IFC_STD_CHAN_NB];
+    };
+} HWP_SYS_IFC_T;
+
+#define hwp_sysIfc                  ((HWP_SYS_IFC_T*)(RDA_IFC_BASE))
+
+
+//get_ch
+#define SYS_IFC_CH_TO_USE(n)        (((n)&15)<<0)
+#define SYS_IFC_CH_TO_USE_MASK      (15<<0)
+#define SYS_IFC_CH_TO_USE_SHIFT     (0)
+
+//dma_status
+#define SYS_IFC_CH_ENABLE(n)        (((n)&0xFF)<<0)
+#define SYS_IFC_CH_BUSY(n)          (((n)&0x7F)<<16)
+
+//debug_status
+#define SYS_IFC_DBG_STATUS          (1<<0)
+
+//control
+#define SYS_IFC_ENABLE              (1<<0)
+#define SYS_IFC_DISABLE             (1<<1)
+#define SYS_IFC_CH_RD_HW_EXCH       (1<<2)
+#define SYS_IFC_CH_WR_HW_EXCH       (1<<3)
+#define SYS_IFC_AUTODISABLE         (1<<4)
+#define SYS_IFC_SIZE(n)             (((n)&3)<<5)
+#define SYS_IFC_SIZE_MASK           (3<<5)
+#define SYS_IFC_SIZE_SHIFT          (5)
+#define SYS_IFC_SIZE_BYTE           (0<<5)
+#define SYS_IFC_SIZE_HALF_WORD      (1<<5)
+#define SYS_IFC_SIZE_WORD           (2<<5)
+#define SYS_IFC_REQ_SRC(n)          (((n)&31)<<8)
+#define SYS_IFC_REQ_SRC_MASK        (31<<8)
+#define SYS_IFC_REQ_SRC_SHIFT       (8)
+#define SYS_IFC_REQ_SRC_SYS_ID_TX_SCI1 (0<<8)
+#define SYS_IFC_REQ_SRC_SYS_ID_RX_SCI1 (1<<8)
+#define SYS_IFC_REQ_SRC_SYS_ID_TX_SCI2 (2<<8)
+#define SYS_IFC_REQ_SRC_SYS_ID_RX_SCI2 (3<<8)
+#define SYS_IFC_REQ_SRC_SYS_ID_TX_SCI3 (4<<8)
+#define SYS_IFC_REQ_SRC_SYS_ID_RX_SCI3 (5<<8)
+#define SYS_IFC_REQ_SRC_SYS_ID_TX_SPI1 (6<<8)
+#define SYS_IFC_REQ_SRC_SYS_ID_RX_SPI1 (7<<8)
+#define SYS_IFC_REQ_SRC_SYS_ID_TX_SPI2 (8<<8)
+#define SYS_IFC_REQ_SRC_SYS_ID_RX_SPI2 (9<<8)
+#define SYS_IFC_REQ_SRC_SYS_ID_TX_I2C (10<<8)
+#define SYS_IFC_REQ_SRC_SYS_ID_RX_I2C (11<<8)
+#define SYS_IFC_REQ_SRC_SYS_ID_TX_DEBUG_UART (12<<8)
+#define SYS_IFC_REQ_SRC_SYS_ID_RX_DEBUG_UART (13<<8)
+#define SYS_IFC_FLUSH             (1<<16)
+#define SYS_IFC_ADDR_CNT(n)       (((n)&7)<<17)
+
+//status
+//#define SYS_IFC_ENABLE          (1<<0)
+#define SYS_IFC_FIFO_EMPTY        (1<<4)
+
+//start_addr1
+#define SYS_IFC_START_ADDR1(n)    (((n)&0xFFFFFFFF)<<0)
+
+//tc1
+#define SYS_IFC_TC1(n)            (((n)&0x7FFFFF)<<0)
+
+//start_addr2
+#define SYS_IFC_START_ADDR2(n)    (((n)&0xFFFFFFFF)<<0)
+
+//tc2
+#define SYS_IFC_TC2(n)            (((n)&0x7FFFFF)<<0)
+
+//start_addr3
+#define SYS_IFC_START_ADDR3(n)    (((n)&0xFFFFFFFF)<<0)
+
+//tc3
+#define SYS_IFC_TC3(n)            (((n)&0x7FFFFF)<<0)
+
+//start_addr4
+#define SYS_IFC_START_ADDR4(n)    (((n)&0xFFFFFFFF)<<0)
+
+//tc4
+#define SYS_IFC_TC4(n)            (((n)&0x7FFFFF)<<0)
+
+//start_addr5
+#define SYS_IFC_START_ADDR5(n)    (((n)&0xFFFFFFFF)<<0)
+
+//tc5
+#define SYS_IFC_TC5(n)            (((n)&0x7FFFFF)<<0)
+
+//start_addr6
+#define SYS_IFC_START_ADDR6(n)    (((n)&0xFFFFFFFF)<<0)
+
+//tc6
+#define SYS_IFC_TC6(n)            (((n)&0x7FFFFF)<<0)
+
+//start_addr7
+#define SYS_IFC_START_ADDR7(n)    (((n)&0xFFFFFFFF)<<0)
+
+//tc7
+#define SYS_IFC_TC7(n)            (((n)&0x7FFFFF)<<0)
+
+//start_addr8
+#define SYS_IFC_START_ADDR8(n)    (((n)&0xFFFFFFFF)<<0)
+
+//tc8
+#define SYS_IFC_TC8(n)            (((n)&0x7FFFFF)<<0)
+
+//control
+//#define SYS_IFC_ENABLE          (1<<0)
+//#define SYS_IFC_DISABLE         (1<<1)
+//#define SYS_IFC_CH_RD_HW_EXCH   (1<<2)
+//#define SYS_IFC_CH_WR_HW_EXCH   (1<<3)
+//#define SYS_IFC_AUTODISABLE     (1<<4)
+//#define SYS_IFC_SIZE(n)         (((n)&3)<<5)
+//#define SYS_IFC_SIZE_MASK       (3<<5)
+//#define SYS_IFC_SIZE_SHIFT      (5)
+//#define SYS_IFC_SIZE_BYTE       (0<<5)
+//#define SYS_IFC_SIZE_HALF_WORD  (1<<5)
+//#define SYS_IFC_SIZE_WORD       (2<<5)
+//#define SYS_IFC_REQ_SRC(n)      (((n)&31)<<8)
+//#define SYS_IFC_REQ_SRC_MASK    (31<<8)
+//#define SYS_IFC_REQ_SRC_SHIFT   (8)
+//#define SYS_IFC_REQ_SRC_SYS_ID_TX_SCI1 (0<<8)
+//#define SYS_IFC_REQ_SRC_SYS_ID_RX_SCI1 (1<<8)
+//#define SYS_IFC_REQ_SRC_SYS_ID_TX_SCI2 (2<<8)
+//#define SYS_IFC_REQ_SRC_SYS_ID_RX_SCI2 (3<<8)
+//#define SYS_IFC_REQ_SRC_SYS_ID_TX_SCI3 (4<<8)
+//#define SYS_IFC_REQ_SRC_SYS_ID_RX_SCI3 (5<<8)
+//#define SYS_IFC_REQ_SRC_SYS_ID_TX_SPI1 (6<<8)
+//#define SYS_IFC_REQ_SRC_SYS_ID_RX_SPI1 (7<<8)
+//#define SYS_IFC_REQ_SRC_SYS_ID_TX_SPI2 (8<<8)
+//#define SYS_IFC_REQ_SRC_SYS_ID_RX_SPI2 (9<<8)
+//#define SYS_IFC_REQ_SRC_SYS_ID_TX_I2C (10<<8)
+//#define SYS_IFC_REQ_SRC_SYS_ID_RX_I2C (11<<8)
+//#define SYS_IFC_REQ_SRC_SYS_ID_TX_DEBUG_UART (12<<8)
+//#define SYS_IFC_REQ_SRC_SYS_ID_RX_DEBUG_UART (13<<8)
+//#define SYS_IFC_FLUSH           (1<<16)
+
+//status
+//#define SYS_IFC_ENABLE          (1<<0)
+//#define SYS_IFC_FIFO_EMPTY      (1<<4)
+
+//start_addr
+#define SYS_IFC_START_ADDR(n)     (((n)&0xFFFFFFFF)<<0)
+
+//tc
+#define SYS_IFC_TC(n)             (((n)&0x7FFFFF)<<0)
+
+
+
+
+#endif /* _REG_IFC_H_ */
+
diff --git a/arch/arm/include/asm/arch-rda/reg_keypad.h b/arch/arm/include/asm/arch-rda/reg_keypad.h
new file mode 100644
index 0000000000..24ccb1c53f
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_keypad.h
@@ -0,0 +1,89 @@
+#ifndef _KEYPAD_H_
+#define _KEYPAD_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+/// Number of key in the keypad
+#define KEY_NB                                  (64)
+/// Number of key in the low data register
+#define LOW_KEY_NB                              (32)
+/// Number of key in the high data register
+#define HIGH_KEY_NB                             (32)
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+// ============================================================================
+// KEYPAD_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+
+typedef volatile struct
+{
+    REG32                          KP_DATA_L;                    //0x00000000
+    REG32                          KP_DATA_H;                    //0x00000004
+    REG32                          KP_STATUS;                    //0x00000008
+    REG32                          KP_CTRL;                      //0x0000000C
+    REG32                          KP_IRQ_MASK;                  //0x00000010
+    REG32                          KP_IRQ_CAUSE;                 //0x00000014
+    REG32                          KP_IRQ_CLR;                   //0x00000018
+} HWP_KEYPAD_T;
+
+#define hwp_apKeypad               ((HWP_KEYPAD_T*) (RDA_KEYPAD_BASE))
+
+
+//KP_DATA_L
+#define KEYPAD_KP_DATA_L(n)        (((n)&0xFFFFFFFF)<<0)
+#define KEYPAD_KP_DATA_L_MASK      (0xFFFFFFFF<<0)
+#define KEYPAD_KP_DATA_L_SHIFT     (0)
+
+//KP_DATA_H
+#define KEYPAD_KP_DATA_H(n)        (((n)&0xFFFFFFFF)<<0)
+#define KEYPAD_KP_DATA_H_MASK      (0xFFFFFFFF<<0)
+#define KEYPAD_KP_DATA_H_SHIFT     (0)
+
+//KP_STATUS
+#define KEYPAD_KEYIN_STATUS(n)     (((n)&0xFF)<<0)
+#define KEYPAD_KEYIN_STATUS_MASK   (0xFF<<0)
+#define KEYPAD_KEYIN_STATUS_SHIFT  (0)
+#define KEYPAD_KP_ON               (1<<31)
+#define KEYPAD_KP_ON_MASK          (1<<31)
+#define KEYPAD_KP_ON_SHIFT         (31)
+
+//KP_CTRL
+#define KEYPAD_KP_EN               (1<<0)
+#define KEYPAD_KP_DBN_TIME(n)      (((n)&0xFF)<<2)
+#define KEYPAD_KP_ITV_TIME(n)      (((n)&0x3F)<<10)
+#define KEYPAD_KP_IN_MASK(n)       (((n)&0xFF)<<16)
+#define KEYPAD_KP_OUT_MASK(n)      (((n)&0xFF)<<24)
+
+//KP_IRQ_MASK
+#define KEYPAD_KP_EVT0_IRQ_MASK    (1<<0)
+#define KEYPAD_KP_EVT1_IRQ_MASK    (1<<1)
+#define KEYPAD_KP_ITV_IRQ_MASK     (1<<2)
+
+//KP_IRQ_CAUSE
+#define KEYPAD_KP_EVT0_IRQ_CAUSE   (1<<0)
+#define KEYPAD_KP_EVT1_IRQ_CAUSE   (1<<1)
+#define KEYPAD_KP_ITV_IRQ_CAUSE    (1<<2)
+#define KEYPAD_KP_EVT0_IRQ_STATUS  (1<<16)
+#define KEYPAD_KP_EVT1_IRQ_STATUS  (1<<17)
+#define KEYPAD_KP_ITV_IRQ_STATUS   (1<<18)
+
+//KP_IRQ_CLR
+#define KEYPAD_KP_IRQ_CLR          (1<<0)
+
+
+
+
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/reg_md_sysctrl.h b/arch/arm/include/asm/arch-rda/reg_md_sysctrl.h
new file mode 100644
index 0000000000..1512065c2e
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_md_sysctrl.h
@@ -0,0 +1,16 @@
+#ifdef CONFIG_MACH_RDA8810
+#include "reg_md_sysctrl_rda8810.h"
+#elif defined(CONFIG_MACH_RDA8810E)
+#include "reg_md_sysctrl_rda8810e.h"
+#elif defined(CONFIG_MACH_RDA8820)
+#include "reg_md_sysctrl_rda8820.h"
+#elif defined(CONFIG_MACH_RDA8850)
+#include "reg_md_sysctrl_rda8850.h"
+#elif defined(CONFIG_MACH_RDA8850E)
+#include "reg_md_sysctrl_rda8850e.h"
+#elif defined(CONFIG_MACH_RDA8810H)
+#include "reg_md_sysctrl_rda8810h.h"
+#else
+#error "unknown MACH"
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8810.h b/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8810.h
new file mode 100644
index 0000000000..efae979e5f
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8810.h
@@ -0,0 +1,958 @@
+#ifndef _REG_MD_SYSCTRL_H_
+#define _REG_MD_SYSCTRL_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+
+// ============================================================================
+// CPU_ID_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// CPU IDs
+    XCPU                                        = 0x00000000,
+    BCPU                                        = 0x00000001
+} CPU_ID_T;
+
+
+// ============================================================================
+// SYS_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// System side System clocks
+    SYS_XCPU                                    = 0x00000000,
+    SYS_XCPU_INT                                = 0x00000001,
+    SYS_PCLK_CONF                               = 0x00000002,
+    SYS_PCLK_DATA                               = 0x00000003,
+    SYS_AMBA                                    = 0x00000004,
+    SYS_DMA                                     = 0x00000005,
+    SYS_EBC                                     = 0x00000006,
+    SYS_IFC_CH0                                 = 0x00000007,
+    SYS_IFC_CH1                                 = 0x00000008,
+    SYS_IFC_CH2                                 = 0x00000009,
+    SYS_IFC_CH3                                 = 0x0000000A,
+    SYS_IFC_DBG                                 = 0x0000000B,
+    SYS_A2A                                     = 0x0000000C,
+    SYS_AXI2AHB                                 = 0x0000000D,
+    SYS_AHB2AXI                                 = 0x0000000E,
+    SYS_EXT_AHB                                 = 0x0000000F,
+    SYS_DEBUG_UART                              = 0x00000010,
+    SYS_DBGHST                                  = 0x00000011,
+/// System side divided clock (either divided by module or by sys_ctrl)
+    SYSD_SCI1                                   = 0x00000012,
+    SYSD_SCI2                                   = 0x00000013,
+    SYSD_SCI3                                   = 0x00000014,
+    SYSD_RF_SPI                                 = 0x00000015,
+    SYSD_OSC                                    = 0x00000016,
+/// the following don't have an auto enable
+    SYS_GPIO                                    = 0x00000017,
+    SYS_IRQ                                     = 0x00000018,
+    SYS_TCU                                     = 0x00000019,
+    SYS_TIMER                                   = 0x0000001A,
+    SYS_COM_REGS                                = 0x0000001B,
+    SYS_DP_AP                                   = 0x0000001C,
+/// the following are sharing their enable
+    SYS_SCI1                                    = 0x0000001D,
+    SYS_SCI2                                    = 0x0000001E,
+    SYS_SCI3                                    = 0x0000001F,
+/// keep last
+    SYS_NOGATE                                  = 0x00000020
+} SYS_CLKS_T;
+
+#define NB_SYS_CLK_XCPU                         (2)
+#define NB_SYS_CLK_AEN                          (23)
+#define NB_SYS_CLK_EN                           (29)
+#define NB_SYS_CLK                              (33)
+
+// ============================================================================
+// PER_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// System side divided clock (either divided by module or by sys_ctrl)
+    PERD_SPI1                                   = 0x00000000,
+/// System side divided clock (either divided by module or by sys_ctrl)
+    PERD_SPI2                                   = 0x00000001,
+    PER_SPY                                     = 0x00000002,
+    PER_TEST                                    = 0x00000003
+} PER_CLKS_T;
+
+#define NB_PER_CLK_AEN                          (2)
+#define NB_PER_CLK_EN                           (4)
+#define NB_PER_CLK                              (4)
+
+// ============================================================================
+// BB_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// Baseband side System clocks
+    BB_BCPU                                     = 0x00000000,
+    BB_BCPU_INT                                 = 0x00000001,
+    BB_AMBA                                     = 0x00000002,
+    BB_PCLK_CONF                                = 0x00000003,
+    BB_PCLK_DATA                                = 0x00000004,
+    BB_EXCOR                                    = 0x00000005,
+    BB_IFC_CH2                                  = 0x00000006,
+    BB_IFC_CH3                                  = 0x00000007,
+    BB_SRAM                                     = 0x00000008,
+    BB_A2A                                      = 0x00000009,
+    BB_ITLV                                     = 0x0000000A,
+    BB_VITERBI                                  = 0x0000000B,
+    BB_CIPHER                                   = 0x0000000C,
+    BB_RF_IF                                    = 0x0000000D,
+    BB_COPRO                                    = 0x0000000E,
+    BB_CP2_REG                                  = 0x0000000F,
+    BB_XCOR                                     = 0x00000010,
+    BB_EVITAC                                   = 0x00000011,
+/// the following don't have an auto enable
+    BB_IRQ                                      = 0x00000012,
+    BB_COM_REGS                                 = 0x00000013,
+    BB_CORDIC                                   = 0x00000014
+} BB_CLKS_T;
+
+#define NB_BB_CLK_AEN                           (18)
+#define NB_BB_CLK_EN                            (21)
+#define NB_BB_CLK                               (21)
+/// Other clocks
+/// clocks with auto enble
+/// the debug host clock auto enable is not used in host mode, only in uart mode
+#define OC_HOST_UART                            (0)
+
+// ============================================================================
+// OTHER_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+    OC_DEBUG_UART                               = 0x00000000,
+    OC_RF_RX                                    = 0x00000001,
+    OC_RF_TX                                    = 0x00000002,
+    OC_MEM_BRIDGE                               = 0x00000003,
+/// the following don't have an auto enable
+    OC_LPS                                      = 0x00000004,
+    OC_GPIO                                     = 0x00000005,
+    OC_CLK_OUT                                  = 0x00000006,
+    OC_MEM_CLK_OUT                              = 0x00000007,
+    OC_TCU                                      = 0x00000008
+} OTHER_CLKS_T;
+
+#define NB_OTHER_CLK_AEN                        (4)
+#define NB_OTHER_CLK_EN                         (9)
+#define NB_OTHER_CLK                            (9)
+
+// ============================================================================
+// RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// System side resets
+    RST_XCPU                                    = 0x00000000,
+    RST_SYS_IRQ                                 = 0x00000001,
+    RST_SYS_A2A                                 = 0x00000002,
+    RST_SYS_AHB2AXI                             = 0x00000003,
+    RST_SYS_AXI2AHB                             = 0x00000004,
+    RST_DMA                                     = 0x00000005,
+    RST_TIMER                                   = 0x00000006,
+    RST_TCU                                     = 0x00000007,
+    RST_GPIO                                    = 0x00000008,
+    RST_CFG                                     = 0x00000009,
+    RST_SPI1                                    = 0x0000000A,
+    RST_SPI2                                    = 0x0000000B,
+    RST_RF_SPI                                  = 0x0000000C,
+    RST_SCI1                                    = 0x0000000D,
+    RST_SCI2                                    = 0x0000000E,
+    RST_SCI3                                    = 0x0000000F,
+    RST_SPY                                     = 0x00000010,
+    RST_MEM_BRIDGE                              = 0x00000011,
+    RST_EXT_AHB                                 = 0x00000012,
+    RST_DP_AP                                   = 0x00000013,
+    RST_COMREGS                                 = 0x00000014,
+    RST_COMREGS_AP                              = 0x00000015,
+    RST_AP_CLKEN                                = 0x00000016,
+    RST_AP_RST                                  = 0x00000017,
+    RST_MEM_CHK                                 = 0x00000018,
+    RST_BCPU                                    = 0x00000019,
+    RST_BB_IRQ                                  = 0x0000001A,
+    RST_BB_A2A                                  = 0x0000001B,
+    RST_BB_IFC                                  = 0x0000001C,
+    RST_BB_SRAM                                 = 0x0000001D,
+    RST_ITLV                                    = 0x0000001E,
+    RST_VITERBI                                 = 0x0000001F,
+    RST_CIPHER                                  = 0x00000020,
+    RST_XCOR                                    = 0x00000021,
+    RST_COPRO                                   = 0x00000022,
+    RST_RF_IF                                   = 0x00000023,
+    RST_EXCOR                                   = 0x00000024,
+    RST_EVITAC                                  = 0x00000025,
+    RST_CORDIC                                  = 0x00000026,
+    RST_TCU_BB                                  = 0x00000027,
+    RST_BB_FULL                                 = 0x00000028,
+    RST_SYS_FULL                                = 0x00000029
+} RESETS_T;
+
+#define NB_SRST                                 (25)
+/// Baseband side resets
+#define BOUND_BRST_FIRST                        (25)
+#define BOUND_BRST_AFTER                        (40)
+/// The following reset does not have register
+#define NR_RST_REG                              (41)
+#define NB_RST                                  (42)
+#define NB_BRST                                 (BOUND_BRST_AFTER-BOUND_BRST_FIRST)
+
+// ============================================================================
+// RESET_OTHERS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// Reset Other : resync on corresponding clock other
+    RSTO_DBG_HOST                               = 0x00000000,
+    RSTO_RF_RX                                  = 0x00000001,
+    RSTO_RF_TX                                  = 0x00000002,
+    RSTO_MEM_BRIDGE                             = 0x00000003,
+    RSTO_LPS                                    = 0x00000004,
+    RSTO_GPIO                                   = 0x00000005,
+    RSTO_WDTIMER                                = 0x00000006,
+    RSTO_TCU                                    = 0x00000007
+} RESET_OTHERS_T;
+
+#define BOUND_RSTO_RF_FIRST                     (1)
+#define BOUND_RSTO_RF_AFTER                     (3)
+#define NB_RSTO                                 (8)
+/// For REG_DBG protect lock/unlock value
+#define SYS_CTRL_PROTECT_LOCK                   (0XA50000)
+#define SYS_CTRL_PROTECT_UNLOCK                 (0XA50001)
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+// ============================================================================
+// SYS_CTRL_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef volatile struct
+{
+    /// <strong>This register is used to Lock and Unlock the protected registers.</strong>
+    REG32                          REG_DBG;                      //0x00000000
+    /// This register is protected.
+    REG32                          Sys_Rst_Set;                  //0x00000004
+    REG32                          Sys_Rst_Clr;                  //0x00000008
+    /// This register is protected.
+    REG32                          BB_Rst_Set;                   //0x0000000C
+    REG32                          BB_Rst_Clr;                   //0x00000010
+    REG32                          Clk_Sys_Mode;                 //0x00000014
+    REG32                          Clk_Sys_Enable;               //0x00000018
+    /// This register is protected.
+    REG32                          Clk_Sys_Disable;              //0x0000001C
+    REG32                          Clk_Per_Mode;                 //0x00000020
+    REG32                          Clk_Per_Enable;               //0x00000024
+    /// This register is protected.
+    REG32                          Clk_Per_Disable;              //0x00000028
+    REG32                          Clk_BB_Mode;                  //0x0000002C
+    REG32                          Clk_BB_Enable;                //0x00000030
+    /// This register is protected.
+    REG32                          Clk_BB_Disable;               //0x00000034
+    REG32                          Clk_Other_Mode;               //0x00000038
+    REG32                          Clk_Other_Enable;             //0x0000003C
+    /// This register is protected.
+    REG32                          Clk_Other_Disable;            //0x00000040
+    /// Register protected by Write_Unlocked_H.
+    REG32                          Pll_Ctrl;                     //0x00000044
+    /// This register is protected.
+    REG32                          Sel_Clock;                    //0x00000048
+    REG32                          Cfg_Clk_Sys;                  //0x0000004C
+    REG32                          Cfg_Clk_Mem_Bridge;           //0x00000050
+    /// This register is protected.
+    REG32                          Cfg_Clk_Out;                  //0x00000054
+    REG32                          Cfg_Clk_Host_Uart;            //0x00000058
+    REG32                          Cfg_Clk_Auxclk;               //0x0000005C
+    /// This register is protected.
+    REG32                          Cfg_AHB;                      //0x00000060
+    /// This register is protected. Used to unsplit masters manualy.
+    REG32                          Ctrl_AHB;                     //0x00000064
+    REG32                          XCpu_Dbg_BKP;                 //0x00000068
+    REG32                          XCpu_Dbg_Addr;                //0x0000006C
+    REG32                          BCpu_Dbg_BKP;                 //0x00000070
+    REG32                          BCpu_Dbg_Addr;                //0x00000074
+    REG32                          Cfg_Cpus_Cache_Ram_Disable;   //0x00000078
+    REG32                          Reset_Cause;                  //0x0000007C
+    /// This register is protected.
+    REG32                          WakeUp;                       //0x00000080
+    REG32                          AP_Ctrl;                      //0x00000084
+    /// This register is protected.
+    REG32                          Ignore_Charger;               //0x00000088
+    REG32 Reserved_0000008C[28];                //0x0000008C
+    /// This register is reserved.
+    REG32                          Cfg_Reserve;                  //0x000000FC
+} HWP_SYS_CTRL_T;
+
+#define hwp_sysCtrlMd               ((HWP_SYS_CTRL_T*)(RDA_MD_SYSCTRL_BASE))
+
+
+//REG_DBG
+#define SYS_CTRL_SCRATCH(n)        (((n)&0xFFFF)<<0)
+#define SYS_CTRL_WRITE_UNLOCK_STATUS (1<<30)
+#define SYS_CTRL_WRITE_UNLOCK      (1<<31)
+
+//Sys_Rst_Set
+#define SYS_CTRL_SET_RST_XCPU      (1<<0)
+#define SYS_CTRL_SET_RST_SYS_IRQ   (1<<1)
+#define SYS_CTRL_SET_RST_SYS_A2A   (1<<2)
+#define SYS_CTRL_SET_RST_SYS_AHB2AXI (1<<3)
+#define SYS_CTRL_SET_RST_SYS_AXI2AHB (1<<4)
+#define SYS_CTRL_SET_RST_DMA       (1<<5)
+#define SYS_CTRL_SET_RST_TIMER     (1<<6)
+#define SYS_CTRL_SET_RST_TCU       (1<<7)
+#define SYS_CTRL_SET_RST_GPIO      (1<<8)
+#define SYS_CTRL_SET_RST_CFG       (1<<9)
+#define SYS_CTRL_SET_RST_SPI1      (1<<10)
+#define SYS_CTRL_SET_RST_SPI2      (1<<11)
+#define SYS_CTRL_SET_RST_RF_SPI    (1<<12)
+#define SYS_CTRL_SET_RST_SCI1      (1<<13)
+#define SYS_CTRL_SET_RST_SCI2      (1<<14)
+#define SYS_CTRL_SET_RST_SCI3      (1<<15)
+#define SYS_CTRL_SET_RST_SPY       (1<<16)
+#define SYS_CTRL_SET_RST_MEM_BRIDGE (1<<17)
+#define SYS_CTRL_SET_RST_EXT_AHB   (1<<18)
+#define SYS_CTRL_SET_RST_DP_AP     (1<<19)
+#define SYS_CTRL_SET_RST_COMREGS   (1<<20)
+#define SYS_CTRL_SET_RST_COMREGS_AP (1<<21)
+#define SYS_CTRL_SET_RST_AP_CLKEN  (1<<22)
+#define SYS_CTRL_SET_RST_AP_RST    (1<<23)
+#define SYS_CTRL_SET_RST_MEM_CHK   (1<<24)
+#define SYS_CTRL_SET_RST_OUT       (1<<30)
+#define SYS_CTRL_SOFT_RST          (1<<31)
+#define SYS_CTRL_SET_SYS_RST(n)    (((n)&0x1FFFFFF)<<0)
+#define SYS_CTRL_SET_SYS_RST_MASK  (0x1FFFFFF<<0)
+#define SYS_CTRL_SET_SYS_RST_SHIFT (0)
+
+//Sys_Rst_Clr
+#define SYS_CTRL_CLR_RST_XCPU      (1<<0)
+#define SYS_CTRL_CLR_RST_SYS_IRQ   (1<<1)
+#define SYS_CTRL_CLR_RST_SYS_A2A   (1<<2)
+#define SYS_CTRL_CLR_RST_SYS_AHB2AXI (1<<3)
+#define SYS_CTRL_CLR_RST_SYS_AXI2AHB (1<<4)
+#define SYS_CTRL_CLR_RST_DMA       (1<<5)
+#define SYS_CTRL_CLR_RST_TIMER     (1<<6)
+#define SYS_CTRL_CLR_RST_TCU       (1<<7)
+#define SYS_CTRL_CLR_RST_GPIO      (1<<8)
+#define SYS_CTRL_CLR_RST_CFG       (1<<9)
+#define SYS_CTRL_CLR_RST_SPI1      (1<<10)
+#define SYS_CTRL_CLR_RST_SPI2      (1<<11)
+#define SYS_CTRL_CLR_RST_RF_SPI    (1<<12)
+#define SYS_CTRL_CLR_RST_SCI1      (1<<13)
+#define SYS_CTRL_CLR_RST_SCI2      (1<<14)
+#define SYS_CTRL_CLR_RST_SCI3      (1<<15)
+#define SYS_CTRL_CLR_RST_SPY       (1<<16)
+#define SYS_CTRL_CLR_RST_MEM_BRIDGE (1<<17)
+#define SYS_CTRL_CLR_RST_EXT_AHB   (1<<18)
+#define SYS_CTRL_CLR_RST_DP_AP     (1<<19)
+#define SYS_CTRL_CLR_RST_COMREGS   (1<<20)
+#define SYS_CTRL_CLR_RST_COMREGS_AP (1<<21)
+#define SYS_CTRL_CLR_RST_AP_CLKEN  (1<<22)
+#define SYS_CTRL_CLR_RST_AP_RST    (1<<23)
+#define SYS_CTRL_CLR_RST_MEM_CHK   (1<<24)
+#define SYS_CTRL_CLR_RST_OUT       (1<<30)
+#define SYS_CTRL_CLR_SYS_RST(n)    (((n)&0x1FFFFFF)<<0)
+#define SYS_CTRL_CLR_SYS_RST_MASK  (0x1FFFFFF<<0)
+#define SYS_CTRL_CLR_SYS_RST_SHIFT (0)
+
+//BB_Rst_Set
+#define SYS_CTRL_SET_RST_BCPU      (1<<0)
+#define SYS_CTRL_SET_RST_BB_IRQ    (1<<1)
+#define SYS_CTRL_SET_RST_BB_A2A    (1<<2)
+#define SYS_CTRL_SET_RST_BB_IFC    (1<<3)
+#define SYS_CTRL_SET_RST_BB_SRAM   (1<<4)
+#define SYS_CTRL_SET_RST_ITLV      (1<<5)
+#define SYS_CTRL_SET_RST_VITERBI   (1<<6)
+#define SYS_CTRL_SET_RST_CIPHER    (1<<7)
+#define SYS_CTRL_SET_RST_XCOR      (1<<8)
+#define SYS_CTRL_SET_RST_COPRO     (1<<9)
+#define SYS_CTRL_SET_RST_RF_IF     (1<<10)
+#define SYS_CTRL_SET_RST_EXCOR     (1<<11)
+#define SYS_CTRL_SET_RST_EVITAC    (1<<12)
+#define SYS_CTRL_SET_RST_CORDIC    (1<<13)
+#define SYS_CTRL_SET_RST_TCU_BB    (1<<14)
+#define SYS_CTRL_SET_RST_BB_FULL   (1<<31)
+#define SYS_CTRL_SET_BB_RST(n)     (((n)&0x7FFF)<<0)
+#define SYS_CTRL_SET_BB_RST_MASK   (0x7FFF<<0)
+#define SYS_CTRL_SET_BB_RST_SHIFT  (0)
+
+//BB_Rst_Clr
+#define SYS_CTRL_CLR_RST_BCPU      (1<<0)
+#define SYS_CTRL_CLR_RST_BB_IRQ    (1<<1)
+#define SYS_CTRL_CLR_RST_BB_A2A    (1<<2)
+#define SYS_CTRL_CLR_RST_BB_IFC    (1<<3)
+#define SYS_CTRL_CLR_RST_BB_SRAM   (1<<4)
+#define SYS_CTRL_CLR_RST_ITLV      (1<<5)
+#define SYS_CTRL_CLR_RST_VITERBI   (1<<6)
+#define SYS_CTRL_CLR_RST_CIPHER    (1<<7)
+#define SYS_CTRL_CLR_RST_XCOR      (1<<8)
+#define SYS_CTRL_CLR_RST_COPRO     (1<<9)
+#define SYS_CTRL_CLR_RST_RF_IF     (1<<10)
+#define SYS_CTRL_CLR_RST_EXCOR     (1<<11)
+#define SYS_CTRL_CLR_RST_EVITAC    (1<<12)
+#define SYS_CTRL_CLR_RST_CORDIC    (1<<13)
+#define SYS_CTRL_CLR_RST_TCU_BB    (1<<14)
+#define SYS_CTRL_CLR_RST_BB_FULL   (1<<31)
+#define SYS_CTRL_CLR_BB_RST(n)     (((n)&0x7FFF)<<0)
+#define SYS_CTRL_CLR_BB_RST_MASK   (0x7FFF<<0)
+#define SYS_CTRL_CLR_BB_RST_SHIFT  (0)
+
+//Clk_Sys_Mode
+#define SYS_CTRL_MODE_SYS_XCPU     (1<<0)
+#define SYS_CTRL_MODE_SYS_XCPU_INT_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_SYS_XCPU_INT_MANUAL (1<<1)
+#define SYS_CTRL_MODE_SYS_PCLK_CONF_AUTOMATIC (0<<2)
+#define SYS_CTRL_MODE_SYS_PCLK_CONF_MANUAL (1<<2)
+#define SYS_CTRL_MODE_SYS_PCLK_DATA_AUTOMATIC (0<<3)
+#define SYS_CTRL_MODE_SYS_PCLK_DATA_MANUAL (1<<3)
+#define SYS_CTRL_MODE_SYS_AMBA_AUTOMATIC (0<<4)
+#define SYS_CTRL_MODE_SYS_AMBA_MANUAL (1<<4)
+#define SYS_CTRL_MODE_SYS_DMA_AUTOMATIC (0<<5)
+#define SYS_CTRL_MODE_SYS_DMA_MANUAL (1<<5)
+#define SYS_CTRL_MODE_SYS_EBC_AUTOMATIC (0<<6)
+#define SYS_CTRL_MODE_SYS_EBC_MANUAL (1<<6)
+#define SYS_CTRL_MODE_SYS_IFC_CH0_AUTOMATIC (0<<7)
+#define SYS_CTRL_MODE_SYS_IFC_CH0_MANUAL (1<<7)
+#define SYS_CTRL_MODE_SYS_IFC_CH1_AUTOMATIC (0<<8)
+#define SYS_CTRL_MODE_SYS_IFC_CH1_MANUAL (1<<8)
+#define SYS_CTRL_MODE_SYS_IFC_CH2_AUTOMATIC (0<<9)
+#define SYS_CTRL_MODE_SYS_IFC_CH2_MANUAL (1<<9)
+#define SYS_CTRL_MODE_SYS_IFC_CH3_AUTOMATIC (0<<10)
+#define SYS_CTRL_MODE_SYS_IFC_CH3_MANUAL (1<<10)
+#define SYS_CTRL_MODE_SYS_IFC_DBG_AUTOMATIC (0<<11)
+#define SYS_CTRL_MODE_SYS_IFC_DBG_MANUAL (1<<11)
+#define SYS_CTRL_MODE_SYS_A2A_AUTOMATIC (0<<12)
+#define SYS_CTRL_MODE_SYS_A2A_MANUAL (1<<12)
+#define SYS_CTRL_MODE_SYS_AXI2AHB_AUTOMATIC (0<<13)
+#define SYS_CTRL_MODE_SYS_AXI2AHB_MANUAL (1<<13)
+#define SYS_CTRL_MODE_SYS_AHB2AXI_AUTOMATIC (0<<14)
+#define SYS_CTRL_MODE_SYS_AHB2AXI_MANUAL (1<<14)
+#define SYS_CTRL_MODE_SYS_EXT_AHB_AUTOMATIC (0<<15)
+#define SYS_CTRL_MODE_SYS_EXT_AHB_MANUAL (1<<15)
+#define SYS_CTRL_MODE_SYS_DEBUG_UART_AUTOMATIC (0<<16)
+#define SYS_CTRL_MODE_SYS_DEBUG_UART_MANUAL (1<<16)
+#define SYS_CTRL_MODE_SYS_DBGHST_AUTOMATIC (0<<17)
+#define SYS_CTRL_MODE_SYS_DBGHST_MANUAL (1<<17)
+#define SYS_CTRL_MODE_SYSD_SCI1_AUTOMATIC (0<<18)
+#define SYS_CTRL_MODE_SYSD_SCI1_MANUAL (1<<18)
+#define SYS_CTRL_MODE_SYSD_SCI2_AUTOMATIC (0<<19)
+#define SYS_CTRL_MODE_SYSD_SCI2_MANUAL (1<<19)
+#define SYS_CTRL_MODE_SYSD_SCI3_AUTOMATIC (0<<20)
+#define SYS_CTRL_MODE_SYSD_SCI3_MANUAL (1<<20)
+#define SYS_CTRL_MODE_SYSD_RF_SPI_AUTOMATIC (0<<21)
+#define SYS_CTRL_MODE_SYSD_RF_SPI_MANUAL (1<<21)
+#define SYS_CTRL_MODE_SYSD_OSC_AUTOMATIC (0<<22)
+#define SYS_CTRL_MODE_SYSD_OSC_MANUAL (1<<22)
+#define SYS_CTRL_MODE_CLK_SYS(n)   (((n)&0x3FFFFF)<<1)
+#define SYS_CTRL_MODE_CLK_SYS_MASK (0x3FFFFF<<1)
+#define SYS_CTRL_MODE_CLK_SYS_SHIFT (1)
+
+//Clk_Sys_Enable
+#define SYS_CTRL_ENABLE_SYS_XCPU   (1<<0)
+#define SYS_CTRL_ENABLE_SYS_XCPU_INT (1<<1)
+#define SYS_CTRL_ENABLE_SYS_PCLK_CONF (1<<2)
+#define SYS_CTRL_ENABLE_SYS_PCLK_DATA (1<<3)
+#define SYS_CTRL_ENABLE_SYS_AMBA   (1<<4)
+#define SYS_CTRL_ENABLE_SYS_DMA    (1<<5)
+#define SYS_CTRL_ENABLE_SYS_EBC    (1<<6)
+#define SYS_CTRL_ENABLE_SYS_IFC_CH0 (1<<7)
+#define SYS_CTRL_ENABLE_SYS_IFC_CH1 (1<<8)
+#define SYS_CTRL_ENABLE_SYS_IFC_CH2 (1<<9)
+#define SYS_CTRL_ENABLE_SYS_IFC_CH3 (1<<10)
+#define SYS_CTRL_ENABLE_SYS_IFC_DBG (1<<11)
+#define SYS_CTRL_ENABLE_SYS_A2A    (1<<12)
+#define SYS_CTRL_ENABLE_SYS_AXI2AHB (1<<13)
+#define SYS_CTRL_ENABLE_SYS_AHB2AXI (1<<14)
+#define SYS_CTRL_ENABLE_SYS_EXT_AHB (1<<15)
+#define SYS_CTRL_ENABLE_SYS_DEBUG_UART (1<<16)
+#define SYS_CTRL_ENABLE_SYS_DBGHST (1<<17)
+#define SYS_CTRL_ENABLE_SYSD_SCI1  (1<<18)
+#define SYS_CTRL_ENABLE_SYSD_SCI2  (1<<19)
+#define SYS_CTRL_ENABLE_SYSD_SCI3  (1<<20)
+#define SYS_CTRL_ENABLE_SYSD_RF_SPI (1<<21)
+#define SYS_CTRL_ENABLE_SYSD_OSC   (1<<22)
+#define SYS_CTRL_ENABLE_SYS_GPIO   (1<<23)
+#define SYS_CTRL_ENABLE_SYS_IRQ    (1<<24)
+#define SYS_CTRL_ENABLE_SYS_TCU    (1<<25)
+#define SYS_CTRL_ENABLE_SYS_TIMER  (1<<26)
+#define SYS_CTRL_ENABLE_SYS_COM_REGS (1<<27)
+#define SYS_CTRL_ENABLE_SYS_DP_AP  (1<<28)
+#define SYS_CTRL_ENABLE_CLK_SYS(n) (((n)&0x1FFFFFFF)<<0)
+#define SYS_CTRL_ENABLE_CLK_SYS_MASK (0x1FFFFFFF<<0)
+#define SYS_CTRL_ENABLE_CLK_SYS_SHIFT (0)
+
+//Clk_Sys_Disable
+#define SYS_CTRL_DISABLE_SYS_XCPU  (1<<0)
+#define SYS_CTRL_DISABLE_SYS_XCPU_INT (1<<1)
+#define SYS_CTRL_DISABLE_SYS_PCLK_CONF (1<<2)
+#define SYS_CTRL_DISABLE_SYS_PCLK_DATA (1<<3)
+#define SYS_CTRL_DISABLE_SYS_AMBA  (1<<4)
+#define SYS_CTRL_DISABLE_SYS_DMA   (1<<5)
+#define SYS_CTRL_DISABLE_SYS_EBC   (1<<6)
+#define SYS_CTRL_DISABLE_SYS_IFC_CH0 (1<<7)
+#define SYS_CTRL_DISABLE_SYS_IFC_CH1 (1<<8)
+#define SYS_CTRL_DISABLE_SYS_IFC_CH2 (1<<9)
+#define SYS_CTRL_DISABLE_SYS_IFC_CH3 (1<<10)
+#define SYS_CTRL_DISABLE_SYS_IFC_DBG (1<<11)
+#define SYS_CTRL_DISABLE_SYS_A2A   (1<<12)
+#define SYS_CTRL_DISABLE_SYS_AXI2AHB (1<<13)
+#define SYS_CTRL_DISABLE_SYS_AHB2AXI (1<<14)
+#define SYS_CTRL_DISABLE_SYS_EXT_AHB (1<<15)
+#define SYS_CTRL_DISABLE_SYS_DEBUG_UART (1<<16)
+#define SYS_CTRL_DISABLE_SYS_DBGHST (1<<17)
+#define SYS_CTRL_DISABLE_SYSD_SCI1 (1<<18)
+#define SYS_CTRL_DISABLE_SYSD_SCI2 (1<<19)
+#define SYS_CTRL_DISABLE_SYSD_SCI3 (1<<20)
+#define SYS_CTRL_DISABLE_SYSD_RF_SPI (1<<21)
+#define SYS_CTRL_DISABLE_SYSD_OSC  (1<<22)
+#define SYS_CTRL_DISABLE_SYS_GPIO  (1<<23)
+#define SYS_CTRL_DISABLE_SYS_IRQ   (1<<24)
+#define SYS_CTRL_DISABLE_SYS_TCU   (1<<25)
+#define SYS_CTRL_DISABLE_SYS_TIMER (1<<26)
+#define SYS_CTRL_DISABLE_SYS_COM_REGS (1<<27)
+#define SYS_CTRL_DISABLE_SYS_DP_AP (1<<28)
+#define SYS_CTRL_DISABLE_CLK_SYS(n) (((n)&0x1FFFFFFF)<<0)
+#define SYS_CTRL_DISABLE_CLK_SYS_MASK (0x1FFFFFFF<<0)
+#define SYS_CTRL_DISABLE_CLK_SYS_SHIFT (0)
+
+//Clk_Per_Mode
+#define SYS_CTRL_MODE_PERD_SPI1_AUTOMATIC (0<<0)
+#define SYS_CTRL_MODE_PERD_SPI1_MANUAL (1<<0)
+#define SYS_CTRL_MODE_PERD_SPI2_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_PERD_SPI2_MANUAL (1<<1)
+#define SYS_CTRL_MODE_CLK_PER(n)   (((n)&3)<<0)
+#define SYS_CTRL_MODE_CLK_PER_MASK (3<<0)
+#define SYS_CTRL_MODE_CLK_PER_SHIFT (0)
+
+//Clk_Per_Enable
+#define SYS_CTRL_ENABLE_PERD_SPI1  (1<<0)
+#define SYS_CTRL_ENABLE_PERD_SPI2  (1<<1)
+#define SYS_CTRL_ENABLE_PER_SPY    (1<<2)
+#define SYS_CTRL_ENABLE_PER_TEST   (1<<3)
+#define SYS_CTRL_ENABLE_CLK_PER(n) (((n)&15)<<0)
+#define SYS_CTRL_ENABLE_CLK_PER_MASK (15<<0)
+#define SYS_CTRL_ENABLE_CLK_PER_SHIFT (0)
+
+//Clk_Per_Disable
+#define SYS_CTRL_DISABLE_PERD_SPI1 (1<<0)
+#define SYS_CTRL_DISABLE_PERD_SPI2 (1<<1)
+#define SYS_CTRL_DISABLE_PER_SPY   (1<<2)
+#define SYS_CTRL_DISABLE_PER_TEST  (1<<3)
+#define SYS_CTRL_DISABLE_CLK_PER(n) (((n)&15)<<0)
+#define SYS_CTRL_DISABLE_CLK_PER_MASK (15<<0)
+#define SYS_CTRL_DISABLE_CLK_PER_SHIFT (0)
+
+//Clk_BB_Mode
+#define SYS_CTRL_MODE_BB_BCPU      (1<<0)
+#define SYS_CTRL_MODE_BB_BCPU_INT_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_BB_BCPU_INT_MANUAL (1<<1)
+#define SYS_CTRL_MODE_BB_AMBA_AUTOMATIC (0<<2)
+#define SYS_CTRL_MODE_BB_AMBA_MANUAL (1<<2)
+#define SYS_CTRL_MODE_BB_PCLK_CONF_AUTOMATIC (0<<3)
+#define SYS_CTRL_MODE_BB_PCLK_CONF_MANUAL (1<<3)
+#define SYS_CTRL_MODE_BB_PCLK_DATA_AUTOMATIC (0<<4)
+#define SYS_CTRL_MODE_BB_PCLK_DATA_MANUAL (1<<4)
+#define SYS_CTRL_MODE_BB_EXCOR_AUTOMATIC (0<<5)
+#define SYS_CTRL_MODE_BB_EXCOR_MANUAL (1<<5)
+#define SYS_CTRL_MODE_BB_IFC_CH2_AUTOMATIC (0<<6)
+#define SYS_CTRL_MODE_BB_IFC_CH2_MANUAL (1<<6)
+#define SYS_CTRL_MODE_BB_IFC_CH3_AUTOMATIC (0<<7)
+#define SYS_CTRL_MODE_BB_IFC_CH3_MANUAL (1<<7)
+#define SYS_CTRL_MODE_BB_SRAM_AUTOMATIC (0<<8)
+#define SYS_CTRL_MODE_BB_SRAM_MANUAL (1<<8)
+#define SYS_CTRL_MODE_BB_A2A_AUTOMATIC (0<<9)
+#define SYS_CTRL_MODE_BB_A2A_MANUAL (1<<9)
+#define SYS_CTRL_MODE_BB_ITLV_AUTOMATIC (0<<10)
+#define SYS_CTRL_MODE_BB_ITLV_MANUAL (1<<10)
+#define SYS_CTRL_MODE_BB_VITERBI_AUTOMATIC (0<<11)
+#define SYS_CTRL_MODE_BB_VITERBI_MANUAL (1<<11)
+#define SYS_CTRL_MODE_BB_CIPHER_AUTOMATIC (0<<12)
+#define SYS_CTRL_MODE_BB_CIPHER_MANUAL (1<<12)
+#define SYS_CTRL_MODE_BB_RF_IF_AUTOMATIC (0<<13)
+#define SYS_CTRL_MODE_BB_RF_IF_MANUAL (1<<13)
+#define SYS_CTRL_MODE_BB_COPRO_AUTOMATIC (0<<14)
+#define SYS_CTRL_MODE_BB_COPRO_MANUAL (1<<14)
+#define SYS_CTRL_MODE_BB_CP2_REG_AUTOMATIC (0<<15)
+#define SYS_CTRL_MODE_BB_CP2_REG_MANUAL (1<<15)
+#define SYS_CTRL_MODE_BB_XCOR_AUTOMATIC (0<<16)
+#define SYS_CTRL_MODE_BB_XCOR_MANUAL (1<<16)
+#define SYS_CTRL_MODE_BB_EVITAC_AUTOMATIC (0<<17)
+#define SYS_CTRL_MODE_BB_EVITAC_MANUAL (1<<17)
+#define SYS_CTRL_MODE_CLK_BB(n)    (((n)&0x1FFFF)<<1)
+#define SYS_CTRL_MODE_CLK_BB_MASK  (0x1FFFF<<1)
+#define SYS_CTRL_MODE_CLK_BB_SHIFT (1)
+
+//Clk_BB_Enable
+#define SYS_CTRL_ENABLE_BB_BCPU    (1<<0)
+#define SYS_CTRL_ENABLE_BB_BCPU_INT (1<<1)
+#define SYS_CTRL_ENABLE_BB_AMBA    (1<<2)
+#define SYS_CTRL_ENABLE_BB_PCLK_CONF (1<<3)
+#define SYS_CTRL_ENABLE_BB_PCLK_DATA (1<<4)
+#define SYS_CTRL_ENABLE_BB_EXCOR   (1<<5)
+#define SYS_CTRL_ENABLE_BB_IFC_CH2 (1<<6)
+#define SYS_CTRL_ENABLE_BB_IFC_CH3 (1<<7)
+#define SYS_CTRL_ENABLE_BB_SRAM    (1<<8)
+#define SYS_CTRL_ENABLE_BB_A2A     (1<<9)
+#define SYS_CTRL_ENABLE_BB_ITLV    (1<<10)
+#define SYS_CTRL_ENABLE_BB_VITERBI (1<<11)
+#define SYS_CTRL_ENABLE_BB_CIPHER  (1<<12)
+#define SYS_CTRL_ENABLE_BB_RF_IF   (1<<13)
+#define SYS_CTRL_ENABLE_BB_COPRO   (1<<14)
+#define SYS_CTRL_ENABLE_BB_CP2_REG (1<<15)
+#define SYS_CTRL_ENABLE_BB_XCOR    (1<<16)
+#define SYS_CTRL_ENABLE_BB_EVITAC  (1<<17)
+#define SYS_CTRL_ENABLE_BB_IRQ     (1<<18)
+#define SYS_CTRL_ENABLE_BB_COM_REGS (1<<19)
+#define SYS_CTRL_ENABLE_BB_CORDIC  (1<<20)
+#define SYS_CTRL_ENABLE_CLK_BB(n)  (((n)&0x1FFFFF)<<0)
+#define SYS_CTRL_ENABLE_CLK_BB_MASK (0x1FFFFF<<0)
+#define SYS_CTRL_ENABLE_CLK_BB_SHIFT (0)
+
+//Clk_BB_Disable
+#define SYS_CTRL_DISABLE_BB_BCPU   (1<<0)
+#define SYS_CTRL_DISABLE_BB_BCPU_INT (1<<1)
+#define SYS_CTRL_DISABLE_BB_AMBA   (1<<2)
+#define SYS_CTRL_DISABLE_BB_PCLK_CONF (1<<3)
+#define SYS_CTRL_DISABLE_BB_PCLK_DATA (1<<4)
+#define SYS_CTRL_DISABLE_BB_EXCOR  (1<<5)
+#define SYS_CTRL_DISABLE_BB_IFC_CH2 (1<<6)
+#define SYS_CTRL_DISABLE_BB_IFC_CH3 (1<<7)
+#define SYS_CTRL_DISABLE_BB_SRAM   (1<<8)
+#define SYS_CTRL_DISABLE_BB_A2A    (1<<9)
+#define SYS_CTRL_DISABLE_BB_ITLV   (1<<10)
+#define SYS_CTRL_DISABLE_BB_VITERBI (1<<11)
+#define SYS_CTRL_DISABLE_BB_CIPHER (1<<12)
+#define SYS_CTRL_DISABLE_BB_RF_IF  (1<<13)
+#define SYS_CTRL_DISABLE_BB_COPRO  (1<<14)
+#define SYS_CTRL_DISABLE_BB_CP2_REG (1<<15)
+#define SYS_CTRL_DISABLE_BB_XCOR   (1<<16)
+#define SYS_CTRL_DISABLE_BB_EVITAC (1<<17)
+#define SYS_CTRL_DISABLE_BB_IRQ    (1<<18)
+#define SYS_CTRL_DISABLE_BB_COM_REGS (1<<19)
+#define SYS_CTRL_DISABLE_BB_CORDIC (1<<20)
+#define SYS_CTRL_DISABLE_CLK_BB(n) (((n)&0x1FFFFF)<<0)
+#define SYS_CTRL_DISABLE_CLK_BB_MASK (0x1FFFFF<<0)
+#define SYS_CTRL_DISABLE_CLK_BB_SHIFT (0)
+
+//Clk_Other_Mode
+#define SYS_CTRL_MODE_OC_DEBUG_UART_AUTOMATIC (0<<0)
+#define SYS_CTRL_MODE_OC_DEBUG_UART_MANUAL (1<<0)
+#define SYS_CTRL_MODE_OC_RF_RX_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_OC_RF_RX_MANUAL (1<<1)
+#define SYS_CTRL_MODE_OC_RF_TX_AUTOMATIC (0<<2)
+#define SYS_CTRL_MODE_OC_RF_TX_MANUAL (1<<2)
+#define SYS_CTRL_MODE_OC_MEM_BRIDGE_AUTOMATIC (0<<3)
+#define SYS_CTRL_MODE_OC_MEM_BRIDGE_MANUAL (1<<3)
+#define SYS_CTRL_MODE_CLK_OTHER(n) (((n)&15)<<0)
+#define SYS_CTRL_MODE_CLK_OTHER_MASK (15<<0)
+#define SYS_CTRL_MODE_CLK_OTHER_SHIFT (0)
+
+//Clk_Other_Enable
+#define SYS_CTRL_ENABLE_OC_DEBUG_UART (1<<0)
+#define SYS_CTRL_ENABLE_OC_RF_RX   (1<<1)
+#define SYS_CTRL_ENABLE_OC_RF_TX   (1<<2)
+#define SYS_CTRL_ENABLE_OC_MEM_BRIDGE (1<<3)
+#define SYS_CTRL_ENABLE_OC_LPS     (1<<4)
+#define SYS_CTRL_ENABLE_OC_GPIO    (1<<5)
+#define SYS_CTRL_ENABLE_OC_CLK_OUT (1<<6)
+#define SYS_CTRL_ENABLE_OC_MEM_CLK_OUT (1<<7)
+#define SYS_CTRL_ENABLE_OC_TCU     (1<<8)
+#define SYS_CTRL_ENABLE_CLK_OTHER(n) (((n)&0x1FF)<<0)
+#define SYS_CTRL_ENABLE_CLK_OTHER_MASK (0x1FF<<0)
+#define SYS_CTRL_ENABLE_CLK_OTHER_SHIFT (0)
+
+//Clk_Other_Disable
+#define SYS_CTRL_DISABLE_OC_DEBUG_UART (1<<0)
+#define SYS_CTRL_DISABLE_OC_RF_RX  (1<<1)
+#define SYS_CTRL_DISABLE_OC_RF_TX  (1<<2)
+#define SYS_CTRL_DISABLE_OC_MEM_BRIDGE (1<<3)
+#define SYS_CTRL_DISABLE_OC_LPS    (1<<4)
+#define SYS_CTRL_DISABLE_OC_GPIO   (1<<5)
+#define SYS_CTRL_DISABLE_OC_CLK_OUT (1<<6)
+#define SYS_CTRL_DISABLE_OC_MEM_CLK_OUT (1<<7)
+#define SYS_CTRL_DISABLE_OC_TCU    (1<<8)
+#define SYS_CTRL_DISABLE_CLK_OTHER(n) (((n)&0x1FF)<<0)
+#define SYS_CTRL_DISABLE_CLK_OTHER_MASK (0x1FF<<0)
+#define SYS_CTRL_DISABLE_CLK_OTHER_SHIFT (0)
+
+//Pll_Ctrl
+#define SYS_CTRL_PLL_ENABLE        (1<<0)
+#define SYS_CTRL_PLL_ENABLE_MASK   (1<<0)
+#define SYS_CTRL_PLL_ENABLE_SHIFT  (0)
+#define SYS_CTRL_PLL_ENABLE_POWER_DOWN (0<<0)
+#define SYS_CTRL_PLL_ENABLE_ENABLE (1<<0)
+#define SYS_CTRL_PLL_LOCK_RESET    (1<<4)
+#define SYS_CTRL_PLL_LOCK_RESET_MASK (1<<4)
+#define SYS_CTRL_PLL_LOCK_RESET_SHIFT (4)
+#define SYS_CTRL_PLL_LOCK_RESET_RESET (0<<4)
+#define SYS_CTRL_PLL_LOCK_RESET_NO_RESET (1<<4)
+#define SYS_CTRL_PLL_BYPASS        (1<<8)
+#define SYS_CTRL_PLL_BYPASS_MASK   (1<<8)
+#define SYS_CTRL_PLL_BYPASS_SHIFT  (8)
+#define SYS_CTRL_PLL_BYPASS_PASS   (0<<8)
+#define SYS_CTRL_PLL_BYPASS_BYPASS (1<<8)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE (1<<12)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_MASK (1<<12)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_SHIFT (12)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_ENABLE (1<<12)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_DISABLE (0<<12)
+#define SYS_CTRL_PLL_XP_CFG(n)     (((n)&4369)<<0)
+#define SYS_CTRL_PLL_XP_CFG_MASK   (4369<<0)
+#define SYS_CTRL_PLL_XP_CFG_SHIFT  (0)
+
+//Sel_Clock
+#define SYS_CTRL_SLOW_SEL_RF_OSCILLATOR (1<<0)
+#define SYS_CTRL_SLOW_SEL_RF_RF    (0<<0)
+#define SYS_CTRL_SYS_SEL_FAST_SLOW (1<<4)
+#define SYS_CTRL_SYS_SEL_FAST_FAST (0<<4)
+#define SYS_CTRL_TCU_13M_L_26M     (1<<5)
+#define SYS_CTRL_TCU_13M_L_13M     (0<<5)
+#define SYS_CTRL_PLL_DISABLE_LPS_DISABLE (1<<6)
+#define SYS_CTRL_PLL_DISABLE_LPS_ENABLE (0<<6)
+#define SYS_CTRL_DIGEN_H_ENABLE    (1<<7)
+#define SYS_CTRL_DIGEN_H_DISABLE   (0<<7)
+#define SYS_CTRL_RF_DETECTED_OK    (1<<20)
+#define SYS_CTRL_RF_DETECTED_NO    (0<<20)
+#define SYS_CTRL_RF_DETECT_BYPASS  (1<<21)
+#define SYS_CTRL_RF_DETECT_RESET   (1<<22)
+#define SYS_CTRL_RF_SELECTED_L     (1<<23)
+#define SYS_CTRL_PLL_LOCKED        (1<<24)
+#define SYS_CTRL_PLL_LOCKED_MASK   (1<<24)
+#define SYS_CTRL_PLL_LOCKED_SHIFT  (24)
+#define SYS_CTRL_PLL_LOCKED_LOCKED (1<<24)
+#define SYS_CTRL_PLL_LOCKED_NOT_LOCKED (0<<24)
+#define SYS_CTRL_PLL_BYPASS_LOCK   (1<<27)
+#define SYS_CTRL_FAST_SELECTED_L   (1<<31)
+#define SYS_CTRL_FAST_SELECTED_L_MASK (1<<31)
+#define SYS_CTRL_FAST_SELECTED_L_SHIFT (31)
+
+//Cfg_Clk_Sys
+#define SYS_CTRL_FREQ(n)           (((n)&15)<<0)
+#define SYS_CTRL_FREQ_MASK         (15<<0)
+#define SYS_CTRL_FREQ_SHIFT        (0)
+#define SYS_CTRL_FREQ_312M         (13<<0)
+#define SYS_CTRL_FREQ_250M         (12<<0)
+#define SYS_CTRL_FREQ_208M         (11<<0)
+#define SYS_CTRL_FREQ_178M         (10<<0)
+#define SYS_CTRL_FREQ_156M         (9<<0)
+#define SYS_CTRL_FREQ_139M         (8<<0)
+#define SYS_CTRL_FREQ_125M         (7<<0)
+#define SYS_CTRL_FREQ_113M         (6<<0)
+#define SYS_CTRL_FREQ_104M         (5<<0)
+#define SYS_CTRL_FREQ_89M          (4<<0)
+#define SYS_CTRL_FREQ_78M          (3<<0)
+#define SYS_CTRL_FREQ_52M          (2<<0)
+#define SYS_CTRL_FREQ_39M          (1<<0)
+#define SYS_CTRL_FREQ_26M          (0<<0)
+#define SYS_CTRL_FORCE_DIV_UPDATE  (1<<4)
+#define SYS_CTRL_REQ_DIV_UPDATE    (1<<8)
+
+//Cfg_Clk_Mem_Bridge
+#define SYS_CTRL_MEM_FREQ(n)       (((n)&15)<<0)
+#define SYS_CTRL_MEM_FREQ_MASK     (15<<0)
+#define SYS_CTRL_MEM_FREQ_SHIFT    (0)
+#define SYS_CTRL_MEM_FREQ_312M     (13<<0)
+#define SYS_CTRL_MEM_FREQ_250M     (12<<0)
+#define SYS_CTRL_MEM_FREQ_208M     (11<<0)
+#define SYS_CTRL_MEM_FREQ_178M     (10<<0)
+#define SYS_CTRL_MEM_FREQ_156M     (9<<0)
+#define SYS_CTRL_MEM_FREQ_139M     (8<<0)
+#define SYS_CTRL_MEM_FREQ_125M     (7<<0)
+#define SYS_CTRL_MEM_FREQ_113M     (6<<0)
+#define SYS_CTRL_MEM_FREQ_104M     (5<<0)
+#define SYS_CTRL_MEM_FREQ_89M      (4<<0)
+#define SYS_CTRL_MEM_FREQ_78M      (3<<0)
+#define SYS_CTRL_MEM_FREQ_52M      (2<<0)
+#define SYS_CTRL_MEM_FREQ_39M      (1<<0)
+#define SYS_CTRL_MEM_FREQ_26M      (0<<0)
+#define SYS_CTRL_DDR_MODE_EN_NORMAL_MODE (0<<6)
+#define SYS_CTRL_DDR_MODE_EN_DDR_MODE (1<<6)
+#define SYS_CTRL_DDR_FAST_CLK_POL_INVERT (1<<7)
+#define SYS_CTRL_DDR_FAST_CLK_POL_NORMAL (0<<7)
+#define SYS_CTRL_DDR_DQSL_I(n)     (((n)&3)<<8)
+#define SYS_CTRL_DDR_DQSU_I(n)     (((n)&3)<<10)
+#define SYS_CTRL_DDR_DQSL_O(n)     (((n)&3)<<12)
+#define SYS_CTRL_DDR_DQSU_O(n)     (((n)&3)<<14)
+#define SYS_CTRL_DDR_PLL_OFF       (1<<16)
+#define SYS_CTRL_MEM_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_Out
+#define SYS_CTRL_CLKOUT_DIVIDER(n) (((n)&31)<<0)
+#define SYS_CTRL_CLKOUT_SEL_OSC    (0<<8)
+#define SYS_CTRL_CLKOUT_SEL_RF     (1<<8)
+#define SYS_CTRL_CLKOUT_SEL_DIVIDER (2<<8)
+
+//Cfg_Clk_Host_Uart
+#define SYS_CTRL_HOST_UART_DIVIDER(n) (((n)&0x3FF)<<0)
+#define SYS_CTRL_HOST_UART_DIVIDER_MASK (0x3FF<<0)
+#define SYS_CTRL_HOST_UART_DIVIDER_SHIFT (0)
+#define SYS_CTRL_HOST_UART_SEL_PLL_SLOW (0<<12)
+#define SYS_CTRL_HOST_UART_SEL_PLL_PLL (1<<12)
+
+//Cfg_Clk_Auxclk
+#define SYS_CTRL_AUXCLK_EN_DISABLE (0<<0)
+#define SYS_CTRL_AUXCLK_EN_ENABLE  (1<<0)
+
+//Cfg_AHB
+#define SYS_CTRL_SYS_NEW_ARBITRATION_ENABLE (1<<0)
+#define SYS_CTRL_SYS_NEW_ARBITRATION_DISABLE (0<<0)
+#define SYS_CTRL_ENABLE_SYS_MID_BIST_ENABLE (1<<1)
+#define SYS_CTRL_ENABLE_SYS_MID_BIST_DISABLE (0<<1)
+#define SYS_CTRL_ENABLE_SYS_MID_DMA_ENABLE (1<<2)
+#define SYS_CTRL_ENABLE_SYS_MID_DMA_DISABLE (0<<2)
+#define SYS_CTRL_ENABLE_SYS_MID_XCPU_ENABLE (1<<3)
+#define SYS_CTRL_ENABLE_SYS_MID_XCPU_DISABLE (0<<3)
+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_ENABLE (1<<4)
+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_DISABLE (0<<4)
+#define SYS_CTRL_ENABLE_SYS_MID_IFC_ENABLE (1<<5)
+#define SYS_CTRL_ENABLE_SYS_MID_IFC_DISABLE (0<<5)
+#define SYS_CTRL_ENABLE_SYS_MID_AXI2AHB_ENABLE (1<<6)
+#define SYS_CTRL_ENABLE_SYS_MID_AXI2AHB_DISABLE (0<<6)
+#define SYS_CTRL_BB_NEW_ARBITRATION_ENABLE (1<<16)
+#define SYS_CTRL_BB_NEW_ARBITRATION_DISABLE (0<<16)
+#define SYS_CTRL_ENABLE_BB_MID_BIST_ENABLE (1<<17)
+#define SYS_CTRL_ENABLE_BB_MID_BIST_DISABLE (0<<17)
+#define SYS_CTRL_ENABLE_BB_MID_IFC_ENABLE (1<<18)
+#define SYS_CTRL_ENABLE_BB_MID_IFC_DISABLE (0<<18)
+#define SYS_CTRL_ENABLE_BB_MID_BCPU_ENABLE (1<<19)
+#define SYS_CTRL_ENABLE_BB_MID_BCPU_DISABLE (0<<19)
+#define SYS_CTRL_ENABLE_BB_MID_AHB2AHB_ENABLE (1<<20)
+#define SYS_CTRL_ENABLE_BB_MID_AHB2AHB_DISABLE (0<<20)
+#define SYS_CTRL_SYS_ENABLE(n)     (((n)&0x3F)<<1)
+#define SYS_CTRL_SYS_ENABLE_MASK   (0x3F<<1)
+#define SYS_CTRL_SYS_ENABLE_SHIFT  (1)
+#define SYS_CTRL_BB_ENABLE(n)      (((n)&15)<<17)
+#define SYS_CTRL_BB_ENABLE_MASK    (15<<17)
+#define SYS_CTRL_BB_ENABLE_SHIFT   (17)
+
+//Ctrl_AHB
+#define SYS_CTRL_SPLIT_SYS_MID_BIST_NORMAL (1<<0)
+#define SYS_CTRL_SPLIT_SYS_MID_BIST_FORCE (0<<0)
+#define SYS_CTRL_SPLIT_SYS_MID_DMA_NORMAL (1<<1)
+#define SYS_CTRL_SPLIT_SYS_MID_DMA_FORCE (0<<1)
+#define SYS_CTRL_SPLIT_SYS_MID_XCPU_NORMAL (1<<2)
+#define SYS_CTRL_SPLIT_SYS_MID_XCPU_FORCE (0<<2)
+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_NORMAL (1<<3)
+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_FORCE (0<<3)
+#define SYS_CTRL_SPLIT_SYS_MID_IFC_NORMAL (1<<4)
+#define SYS_CTRL_SPLIT_SYS_MID_IFC_FORCE (0<<4)
+#define SYS_CTRL_SPLIT_SYS_MID_AXI2AHB_NORMAL (1<<5)
+#define SYS_CTRL_SPLIT_SYS_MID_AXI2AHB_FORCE (0<<5)
+#define SYS_CTRL_SPLIT_BB_MID_BIST_NORMAL (1<<16)
+#define SYS_CTRL_SPLIT_BB_MID_BIST_FORCE (0<<16)
+#define SYS_CTRL_SPLIT_BB_MID_IFC_NORMAL (1<<17)
+#define SYS_CTRL_SPLIT_BB_MID_IFC_FORCE (0<<17)
+#define SYS_CTRL_SPLIT_BB_MID_BCPU_NORMAL (1<<18)
+#define SYS_CTRL_SPLIT_BB_MID_BCPU_FORCE (0<<18)
+#define SYS_CTRL_SPLIT_BB_MID_AHB2AHB_NORMAL (1<<19)
+#define SYS_CTRL_SPLIT_BB_MID_AHB2AHB_FORCE (0<<19)
+#define SYS_CTRL_SYS_FORCE_HSPLIT(n) (((n)&0x3F)<<0)
+#define SYS_CTRL_SYS_FORCE_HSPLIT_MASK (0x3F<<0)
+#define SYS_CTRL_SYS_FORCE_HSPLIT_SHIFT (0)
+#define SYS_CTRL_BB_FORCE_HSPLIT(n) (((n)&15)<<16)
+#define SYS_CTRL_BB_FORCE_HSPLIT_MASK (15<<16)
+#define SYS_CTRL_BB_FORCE_HSPLIT_SHIFT (16)
+
+//XCpu_Dbg_BKP
+#define SYS_CTRL_BKPT_EN           (1<<0)
+#define SYS_CTRL_BKPT_MODE(n)      (((n)&3)<<4)
+#define SYS_CTRL_BKPT_MODE_I       (0<<4)
+#define SYS_CTRL_BKPT_MODE_R       (1<<4)
+#define SYS_CTRL_BKPT_MODE_W       (2<<4)
+#define SYS_CTRL_BKPT_MODE_RW      (3<<4)
+#define SYS_CTRL_STALLED           (1<<8)
+
+//XCpu_Dbg_Addr
+#define SYS_CTRL_BREAKPOINT_ADDRESS(n) (((n)&0x3FFFFFF)<<0)
+
+//BCpu_Dbg_BKP
+//#define SYS_CTRL_BKPT_EN         (1<<0)
+//#define SYS_CTRL_BKPT_MODE(n)    (((n)&3)<<4)
+//#define SYS_CTRL_BKPT_MODE_I     (0<<4)
+//#define SYS_CTRL_BKPT_MODE_R     (1<<4)
+//#define SYS_CTRL_BKPT_MODE_W     (2<<4)
+//#define SYS_CTRL_BKPT_MODE_RW    (3<<4)
+//#define SYS_CTRL_STALLED         (1<<8)
+
+//BCpu_Dbg_Addr
+//#define SYS_CTRL_BREAKPOINT_ADDRESS(n) (((n)&0x3FFFFFF)<<0)
+
+//Cfg_Cpus_Cache_Ram_Disable
+#define SYS_CTRL_XCPU_USE_MODE     (1<<0)
+#define SYS_CTRL_XCPU_CLK_OFF_MODE (1<<1)
+#define SYS_CTRL_BCPU_USE_MODE     (1<<16)
+#define SYS_CTRL_BCPU_CLK_OFF_MODE (1<<17)
+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE(n) (((n)&3)<<0)
+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE_MASK (3<<0)
+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE_SHIFT (0)
+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE(n) (((n)&3)<<16)
+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE_MASK (3<<16)
+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE_SHIFT (16)
+
+//Reset_Cause
+#define SYS_CTRL_WATCHDOG_RESET_HAPPENED (1<<0)
+#define SYS_CTRL_WATCHDOG_RESET_NO (0<<0)
+#define SYS_CTRL_APSOFT_RESET_HAPPENED (1<<1)
+#define SYS_CTRL_APSOFT_RESET_NO   (0<<1)
+#define SYS_CTRL_GLOBALSOFT_RESET_HAPPENED (1<<4)
+#define SYS_CTRL_GLOBALSOFT_RESET_NO (0<<4)
+#define SYS_CTRL_HOSTDEBUG_RESET_HAPPENED (1<<5)
+#define SYS_CTRL_HOSTDEBUG_RESET_NO (0<<5)
+#define SYS_CTRL_ALARMCAUSE_HAPPENED (1<<6)
+#define SYS_CTRL_ALARMCAUSE_NO     (0<<6)
+#define SYS_CTRL_MEMCHECKDONE_MASK (1<<7)
+#define SYS_CTRL_MEMCHECKDONE_SHIFT (7)
+#define SYS_CTRL_MEMCHECKDONE_DONE (1<<7)
+#define SYS_CTRL_MEMCHECKDONE_RUNNING (0<<7)
+#define SYS_CTRL_BOOT_MODE(n)      (((n)&0xFFFF)<<8)
+#define SYS_CTRL_BOOT_MODE_MASK    (0xFFFF<<8)
+#define SYS_CTRL_BOOT_MODE_SHIFT   (8)
+#define SYS_CTRL_SW_BOOT_MODE(n)   (((n)&0x7F)<<24)
+#define SYS_CTRL_SW_BOOT_MODE_MASK (0x7F<<24)
+#define SYS_CTRL_SW_BOOT_MODE_SHIFT (24)
+#define SYS_CTRL_FONCTIONAL_TEST_MODE (1<<31)
+
+//WakeUp
+#define SYS_CTRL_FORCE_WAKEUP      (1<<0)
+
+//AP_Ctrl
+#define SYS_CTRL_AP_INT_STATUS     (1<<0)
+#define SYS_CTRL_AP_INT_MASK       (1<<16)
+#define SYS_CTRL_AP_DEEPSLEEP_EN   (1<<24)
+
+//Ignore_Charger
+#define SYS_CTRL_IGNORE_CHARGER    (1<<0)
+
+//Cfg_Reserve
+#define SYS_CTRL_RESERVE(n)        (((n)&0x3FFF)<<0)
+#define SYS_CTRL_AUIFC_CH0_IRQ_MASK (1<<14)
+#define SYS_CTRL_AUIFC_CH1_IRQ_MASK (1<<15)
+
+
+
+
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8810e.h b/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8810e.h
new file mode 100644
index 0000000000..0ecd75897f
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8810e.h
@@ -0,0 +1,979 @@
+#ifndef _REG_MD_SYSCTRL_H_

+#define _REG_MD_SYSCTRL_H_

+

+#include <asm/arch/hardware.h>

+#include <asm/arch/rda_iomap.h>

+

+// =============================================================================

+//  MACROS

+// =============================================================================

+

+// ============================================================================

+// CPU_ID_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// CPU IDs

+    XCPU                                        = 0x00000000,

+    BCPU                                        = 0x00000001

+} CPU_ID_T;

+

+

+// ============================================================================

+// SYS_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// System side System clocks

+    SYS_XCPU                                    = 0x00000000,

+    SYS_XCPU_INT                                = 0x00000001,

+    SYS_PCLK_CONF                               = 0x00000002,

+    SYS_PCLK_DATA                               = 0x00000003,

+    SYS_AMBA                                    = 0x00000004,

+    SYS_DMA                                     = 0x00000005,

+    SYS_EBC                                     = 0x00000006,

+    SYS_IFC_CH0                                 = 0x00000007,

+    SYS_IFC_CH1                                 = 0x00000008,

+    SYS_IFC_CH2                                 = 0x00000009,

+    SYS_IFC_CH3                                 = 0x0000000A,

+    SYS_IFC_DBG                                 = 0x0000000B,

+    SYS_A2A                                     = 0x0000000C,

+    SYS_AXI2AHB                                 = 0x0000000D,

+    SYS_AHB2AXI                                 = 0x0000000E,

+    SYS_EXT_AHB                                 = 0x0000000F,

+    SYS_DEBUG_UART                              = 0x00000010,

+    SYS_DBGHST                                  = 0x00000011,

+/// System side divided clock (either divided by module or by sys_ctrl)

+    SYSD_SCI1                                   = 0x00000012,

+    SYSD_SCI2                                   = 0x00000013,

+    SYSD_SCI3                                   = 0x00000014,

+    SYSD_RF_SPI                                 = 0x00000015,

+    SYSD_OSC                                    = 0x00000016,

+/// the following don't have an auto enable

+    SYS_GPIO                                    = 0x00000017,

+    SYS_IRQ                                     = 0x00000018,

+    SYS_TCU                                     = 0x00000019,

+    SYS_TIMER                                   = 0x0000001A,

+    SYS_COM_REGS                                = 0x0000001B,

+    SYS_DP_AP                                   = 0x0000001C,

+/// the following are sharing their enable

+    SYS_SCI1                                    = 0x0000001D,

+    SYS_SCI2                                    = 0x0000001E,

+    SYS_SCI3                                    = 0x0000001F,

+/// keep last

+    SYS_NOGATE                                  = 0x00000020

+} SYS_CLKS_T;

+

+#define NB_SYS_CLK_XCPU                         (2)

+#define NB_SYS_CLK_AEN                          (23)

+#define NB_SYS_CLK_EN                           (29)

+#define NB_SYS_CLK                              (33)

+

+// ============================================================================

+// PER_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+    PER_I2C                                     = 0x00000000,

+/// System side divided clock (either divided by module or by sys_ctrl)

+    PERD_SPI1                                   = 0x00000001,

+/// System side divided clock (either divided by module or by sys_ctrl)

+    PERD_SPI2                                   = 0x00000002,

+    PER_SPY                                     = 0x00000003,

+    PER_TEST                                    = 0x00000004

+} PER_CLKS_T;

+

+#define NB_PER_CLK_AEN                          (3)

+#define NB_PER_CLK_EN                           (5)

+#define NB_PER_CLK                              (5)

+

+// ============================================================================

+// BB_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// Baseband side System clocks

+    BB_BCPU                                     = 0x00000000,

+    BB_BCPU_INT                                 = 0x00000001,

+    BB_AMBA                                     = 0x00000002,

+    BB_PCLK_CONF                                = 0x00000003,

+    BB_PCLK_DATA                                = 0x00000004,

+    BB_EXCOR                                    = 0x00000005,

+    BB_IFC_CH2                                  = 0x00000006,

+    BB_IFC_CH3                                  = 0x00000007,

+    BB_SRAM                                     = 0x00000008,

+    BB_A2A                                      = 0x00000009,

+    BB_ITLV                                     = 0x0000000A,

+    BB_VITERBI                                  = 0x0000000B,

+    BB_CIPHER                                   = 0x0000000C,

+    BB_RF_IF                                    = 0x0000000D,

+    BB_COPRO                                    = 0x0000000E,

+    BB_CP2_REG                                  = 0x0000000F,

+    BB_XCOR                                     = 0x00000010,

+    BB_EVITAC                                   = 0x00000011,

+/// the following don't have an auto enable

+    BB_IRQ                                      = 0x00000012,

+    BB_COM_REGS                                 = 0x00000013,

+    BB_CORDIC                                   = 0x00000014

+} BB_CLKS_T;

+

+#define NB_BB_CLK_AEN                           (18)

+#define NB_BB_CLK_EN                            (21)

+#define NB_BB_CLK                               (21)

+/// Other clocks

+/// clocks with auto enble

+/// the debug host clock auto enable is not used in host mode, only in uart mode

+#define OC_HOST_UART                            (0)

+

+// ============================================================================

+// OTHER_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+    OC_DEBUG_UART                               = 0x00000000,

+    OC_RF_RX                                    = 0x00000001,

+    OC_RF_TX                                    = 0x00000002,

+    OC_MEM_BRIDGE                               = 0x00000003,

+/// the following don't have an auto enable

+    OC_LPS                                      = 0x00000004,

+    OC_GPIO                                     = 0x00000005,

+    OC_CLK_OUT                                  = 0x00000006,

+    OC_MEM_CLK_OUT                              = 0x00000007,

+    OC_TCU                                      = 0x00000008

+} OTHER_CLKS_T;

+

+#define NB_OTHER_CLK_AEN                        (4)

+#define NB_OTHER_CLK_EN                         (9)

+#define NB_OTHER_CLK                            (9)

+

+// ============================================================================

+// RESETS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// System side resets

+    RST_XCPU                                    = 0x00000000,

+    RST_SYS_IRQ                                 = 0x00000001,

+    RST_SYS_A2A                                 = 0x00000002,

+    RST_SYS_AHB2AXI                             = 0x00000003,

+    RST_SYS_AXI2AHB                             = 0x00000004,

+    RST_DMA                                     = 0x00000005,

+    RST_TIMER                                   = 0x00000006,

+    RST_TCU                                     = 0x00000007,

+    RST_GPIO                                    = 0x00000008,

+    RST_I2C                                     = 0x00000009,

+    RST_SPI1                                    = 0x0000000A,

+    RST_SPI2                                    = 0x0000000B,

+    RST_RF_SPI                                  = 0x0000000C,

+    RST_SCI1                                    = 0x0000000D,

+    RST_SCI2                                    = 0x0000000E,

+    RST_SCI3                                    = 0x0000000F,

+    RST_SPY                                     = 0x00000010,

+    RST_MEM_BRIDGE                              = 0x00000011,

+    RST_EXT_AHB                                 = 0x00000012,

+    RST_DP_AP                                   = 0x00000013,

+    RST_COMREGS                                 = 0x00000014,

+    RST_COMREGS_AP                              = 0x00000015,

+    RST_AP_CLKEN                                = 0x00000016,

+    RST_AP_RST                                  = 0x00000017,

+    RST_MEM_CHK                                 = 0x00000018,

+    RST_AP_RST1                                 = 0x00000019,

+    RST_AP_RST2                                 = 0x0000001A,

+    RST_AP_RST3                                 = 0x0000001B,

+    RST_AP_RST4                                 = 0x0000001C,

+    RST_AP_RST5                                 = 0x0000001D,

+    RST_BCPU                                    = 0x0000001E,

+    RST_BB_IRQ                                  = 0x0000001F,

+    RST_BB_A2A                                  = 0x00000020,

+    RST_BB_IFC                                  = 0x00000021,

+    RST_BB_SRAM                                 = 0x00000022,

+    RST_ITLV                                    = 0x00000023,

+    RST_VITERBI                                 = 0x00000024,

+    RST_CIPHER                                  = 0x00000025,

+    RST_XCOR                                    = 0x00000026,

+    RST_COPRO                                   = 0x00000027,

+    RST_RF_IF                                   = 0x00000028,

+    RST_EXCOR                                   = 0x00000029,

+    RST_EVITAC                                  = 0x0000002A,

+    RST_CORDIC                                  = 0x0000002B,

+    RST_TCU_BB                                  = 0x0000002C,

+    RST_BB_FULL                                 = 0x0000002D,

+    RST_SYS_FULL                                = 0x0000002E

+} RESETS_T;

+

+#define NB_SRST                                 (30)

+/// Baseband side resets

+#define BOUND_BRST_FIRST                        (30)

+#define BOUND_BRST_AFTER                        (45)

+/// The following reset does not have register

+#define NR_RST_REG                              (46)

+#define NB_RST                                  (47)

+#define NB_BRST                                 (BOUND_BRST_AFTER-BOUND_BRST_FIRST)

+

+// ============================================================================

+// RESET_OTHERS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// Reset Other : resync on corresponding clock other

+    RSTO_DBG_HOST                               = 0x00000000,

+    RSTO_RF_RX                                  = 0x00000001,

+    RSTO_RF_TX                                  = 0x00000002,

+    RSTO_MEM_BRIDGE                             = 0x00000003,

+    RSTO_LPS                                    = 0x00000004,

+    RSTO_GPIO                                   = 0x00000005,

+    RSTO_WDTIMER                                = 0x00000006,

+    RSTO_TCU                                    = 0x00000007

+} RESET_OTHERS_T;

+

+#define BOUND_RSTO_RF_FIRST                     (1)

+#define BOUND_RSTO_RF_AFTER                     (3)

+#define NB_RSTO                                 (8)

+/// For REG_DBG protect lock/unlock value

+#define SYS_CTRL_PROTECT_LOCK                   (0XA50000)

+#define SYS_CTRL_PROTECT_UNLOCK                 (0XA50001)

+

+// =============================================================================

+//  TYPES

+// =============================================================================

+

+// ============================================================================

+// SYS_CTRL_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef volatile struct

+{

+    /// <strong>This register is used to Lock and Unlock the protected registers.</strong>

+    REG32                          REG_DBG;                      //0x00000000

+    /// This register is protected.

+    REG32                          Sys_Rst_Set;                  //0x00000004

+    REG32                          Sys_Rst_Clr;                  //0x00000008

+    /// This register is protected.

+    REG32                          BB_Rst_Set;                   //0x0000000C

+    REG32                          BB_Rst_Clr;                   //0x00000010

+    REG32                          Clk_Sys_Mode;                 //0x00000014

+    REG32                          Clk_Sys_Enable;               //0x00000018

+    /// This register is protected.

+    REG32                          Clk_Sys_Disable;              //0x0000001C

+    REG32                          Clk_Per_Mode;                 //0x00000020

+    REG32                          Clk_Per_Enable;               //0x00000024

+    /// This register is protected.

+    REG32                          Clk_Per_Disable;              //0x00000028

+    REG32                          Clk_BB_Mode;                  //0x0000002C

+    REG32                          Clk_BB_Enable;                //0x00000030

+    /// This register is protected.

+    REG32                          Clk_BB_Disable;               //0x00000034

+    REG32                          Clk_Other_Mode;               //0x00000038

+    REG32                          Clk_Other_Enable;             //0x0000003C

+    /// This register is protected.

+    REG32                          Clk_Other_Disable;            //0x00000040

+    /// Register protected by Write_Unlocked_H.

+    REG32                          Pll_Ctrl;                     //0x00000044

+    /// This register is protected.

+    REG32                          Sel_Clock;                    //0x00000048

+    REG32                          Cfg_Clk_Sys;                  //0x0000004C

+    REG32                          Cfg_Clk_Mem_Bridge;           //0x00000050

+    /// This register is protected.

+    REG32                          Cfg_Clk_Out;                  //0x00000054

+    REG32                          Cfg_Clk_Host_Uart;            //0x00000058

+    REG32                          Cfg_Clk_Auxclk;               //0x0000005C

+    /// This register is protected.

+    REG32                          Cfg_AHB;                      //0x00000060

+    /// This register is protected. Used to unsplit masters manualy.

+    REG32                          Ctrl_AHB;                     //0x00000064

+    REG32                          XCpu_Dbg_BKP;                 //0x00000068

+    REG32                          XCpu_Dbg_Addr;                //0x0000006C

+    REG32                          BCpu_Dbg_BKP;                 //0x00000070

+    REG32                          BCpu_Dbg_Addr;                //0x00000074

+    REG32                          Cfg_Cpus_Cache_Ram_Disable;   //0x00000078

+    REG32                          Reset_Cause;                  //0x0000007C

+    /// This register is protected.

+    REG32                          WakeUp;                       //0x00000080

+    REG32                          AP_Ctrl;                      //0x00000084

+    /// This register is protected.

+    REG32                          Ignore_Charger;               //0x00000088

+    REG32 Reserved_0000008C[28];                //0x0000008C

+    /// This register is reserved.

+    REG32                          Cfg_Reserve;                  //0x000000FC

+} HWP_SYS_CTRL_T;

+

+#define hwp_sysCtrlMd               ((HWP_SYS_CTRL_T*)(RDA_MD_SYSCTRL_BASE))

+

+

+//REG_DBG

+#define SYS_CTRL_SCRATCH(n)        (((n)&0xFFFF)<<0)

+#define SYS_CTRL_WRITE_UNLOCK_STATUS (1<<30)

+#define SYS_CTRL_WRITE_UNLOCK      (1<<31)

+

+//Sys_Rst_Set

+#define SYS_CTRL_SET_RST_XCPU      (1<<0)

+#define SYS_CTRL_SET_RST_SYS_IRQ   (1<<1)

+#define SYS_CTRL_SET_RST_SYS_A2A   (1<<2)

+#define SYS_CTRL_SET_RST_SYS_AHB2AXI (1<<3)

+#define SYS_CTRL_SET_RST_SYS_AXI2AHB (1<<4)

+#define SYS_CTRL_SET_RST_DMA       (1<<5)

+#define SYS_CTRL_SET_RST_TIMER     (1<<6)

+#define SYS_CTRL_SET_RST_TCU       (1<<7)

+#define SYS_CTRL_SET_RST_GPIO      (1<<8)

+#define SYS_CTRL_SET_RST_I2C       (1<<9)

+#define SYS_CTRL_SET_RST_SPI1      (1<<10)

+#define SYS_CTRL_SET_RST_SPI2      (1<<11)

+#define SYS_CTRL_SET_RST_RF_SPI    (1<<12)

+#define SYS_CTRL_SET_RST_SCI1      (1<<13)

+#define SYS_CTRL_SET_RST_SCI2      (1<<14)

+#define SYS_CTRL_SET_RST_SCI3      (1<<15)

+#define SYS_CTRL_SET_RST_SPY       (1<<16)

+#define SYS_CTRL_SET_RST_MEM_BRIDGE (1<<17)

+#define SYS_CTRL_SET_RST_EXT_AHB   (1<<18)

+#define SYS_CTRL_SET_RST_DP_AP     (1<<19)

+#define SYS_CTRL_SET_RST_COMREGS   (1<<20)

+#define SYS_CTRL_SET_RST_COMREGS_AP (1<<21)

+#define SYS_CTRL_SET_RST_AP_CLKEN  (1<<22)

+#define SYS_CTRL_SET_RST_AP_RST    (1<<23)

+#define SYS_CTRL_SET_RST_MEM_CHK   (1<<24)

+#define SYS_CTRL_SET_RST_AP_RST1   (1<<25)

+#define SYS_CTRL_SET_RST_AP_RST2   (1<<26)

+#define SYS_CTRL_SET_RST_AP_RST3   (1<<27)

+#define SYS_CTRL_SET_RST_AP_RST4   (1<<28)

+#define SYS_CTRL_SET_RST_AP_RST5   (1<<29)

+#define SYS_CTRL_SET_RST_OUT       (1<<30)

+#define SYS_CTRL_SOFT_RST          (1<<31)

+#define SYS_CTRL_SET_SYS_RST(n)    (((n)&0x3FFFFFFF)<<0)

+#define SYS_CTRL_SET_SYS_RST_MASK  (0x3FFFFFFF<<0)

+#define SYS_CTRL_SET_SYS_RST_SHIFT (0)

+

+//Sys_Rst_Clr

+#define SYS_CTRL_CLR_RST_XCPU      (1<<0)

+#define SYS_CTRL_CLR_RST_SYS_IRQ   (1<<1)

+#define SYS_CTRL_CLR_RST_SYS_A2A   (1<<2)

+#define SYS_CTRL_CLR_RST_SYS_AHB2AXI (1<<3)

+#define SYS_CTRL_CLR_RST_SYS_AXI2AHB (1<<4)

+#define SYS_CTRL_CLR_RST_DMA       (1<<5)

+#define SYS_CTRL_CLR_RST_TIMER     (1<<6)

+#define SYS_CTRL_CLR_RST_TCU       (1<<7)

+#define SYS_CTRL_CLR_RST_GPIO      (1<<8)

+#define SYS_CTRL_CLR_RST_I2C       (1<<9)

+#define SYS_CTRL_CLR_RST_SPI1      (1<<10)

+#define SYS_CTRL_CLR_RST_SPI2      (1<<11)

+#define SYS_CTRL_CLR_RST_RF_SPI    (1<<12)

+#define SYS_CTRL_CLR_RST_SCI1      (1<<13)

+#define SYS_CTRL_CLR_RST_SCI2      (1<<14)

+#define SYS_CTRL_CLR_RST_SCI3      (1<<15)

+#define SYS_CTRL_CLR_RST_SPY       (1<<16)

+#define SYS_CTRL_CLR_RST_MEM_BRIDGE (1<<17)

+#define SYS_CTRL_CLR_RST_EXT_AHB   (1<<18)

+#define SYS_CTRL_CLR_RST_DP_AP     (1<<19)

+#define SYS_CTRL_CLR_RST_COMREGS   (1<<20)

+#define SYS_CTRL_CLR_RST_COMREGS_AP (1<<21)

+#define SYS_CTRL_CLR_RST_AP_CLKEN  (1<<22)

+#define SYS_CTRL_CLR_RST_AP_RST    (1<<23)

+#define SYS_CTRL_CLR_RST_MEM_CHK   (1<<24)

+#define SYS_CTRL_CLR_RST_AP_RST1   (1<<25)

+#define SYS_CTRL_CLR_RST_AP_RST2   (1<<26)

+#define SYS_CTRL_CLR_RST_AP_RST3   (1<<27)

+#define SYS_CTRL_CLR_RST_AP_RST4   (1<<28)

+#define SYS_CTRL_CLR_RST_AP_RST5   (1<<29)

+#define SYS_CTRL_CLR_RST_OUT       (1<<30)

+#define SYS_CTRL_CLR_SYS_RST(n)    (((n)&0x3FFFFFFF)<<0)

+#define SYS_CTRL_CLR_SYS_RST_MASK  (0x3FFFFFFF<<0)

+#define SYS_CTRL_CLR_SYS_RST_SHIFT (0)

+

+//BB_Rst_Set

+#define SYS_CTRL_SET_RST_BCPU      (1<<0)

+#define SYS_CTRL_SET_RST_BB_IRQ    (1<<1)

+#define SYS_CTRL_SET_RST_BB_A2A    (1<<2)

+#define SYS_CTRL_SET_RST_BB_IFC    (1<<3)

+#define SYS_CTRL_SET_RST_BB_SRAM   (1<<4)

+#define SYS_CTRL_SET_RST_ITLV      (1<<5)

+#define SYS_CTRL_SET_RST_VITERBI   (1<<6)

+#define SYS_CTRL_SET_RST_CIPHER    (1<<7)

+#define SYS_CTRL_SET_RST_XCOR      (1<<8)

+#define SYS_CTRL_SET_RST_COPRO     (1<<9)

+#define SYS_CTRL_SET_RST_RF_IF     (1<<10)

+#define SYS_CTRL_SET_RST_EXCOR     (1<<11)

+#define SYS_CTRL_SET_RST_EVITAC    (1<<12)

+#define SYS_CTRL_SET_RST_CORDIC    (1<<13)

+#define SYS_CTRL_SET_RST_TCU_BB    (1<<14)

+#define SYS_CTRL_SET_RST_BB_FULL   (1<<31)

+#define SYS_CTRL_SET_BB_RST(n)     (((n)&0x7FFF)<<0)

+#define SYS_CTRL_SET_BB_RST_MASK   (0x7FFF<<0)

+#define SYS_CTRL_SET_BB_RST_SHIFT  (0)

+

+//BB_Rst_Clr

+#define SYS_CTRL_CLR_RST_BCPU      (1<<0)

+#define SYS_CTRL_CLR_RST_BB_IRQ    (1<<1)

+#define SYS_CTRL_CLR_RST_BB_A2A    (1<<2)

+#define SYS_CTRL_CLR_RST_BB_IFC    (1<<3)

+#define SYS_CTRL_CLR_RST_BB_SRAM   (1<<4)

+#define SYS_CTRL_CLR_RST_ITLV      (1<<5)

+#define SYS_CTRL_CLR_RST_VITERBI   (1<<6)

+#define SYS_CTRL_CLR_RST_CIPHER    (1<<7)

+#define SYS_CTRL_CLR_RST_XCOR      (1<<8)

+#define SYS_CTRL_CLR_RST_COPRO     (1<<9)

+#define SYS_CTRL_CLR_RST_RF_IF     (1<<10)

+#define SYS_CTRL_CLR_RST_EXCOR     (1<<11)

+#define SYS_CTRL_CLR_RST_EVITAC    (1<<12)

+#define SYS_CTRL_CLR_RST_CORDIC    (1<<13)

+#define SYS_CTRL_CLR_RST_TCU_BB    (1<<14)

+#define SYS_CTRL_CLR_RST_BB_FULL   (1<<31)

+#define SYS_CTRL_CLR_BB_RST(n)     (((n)&0x7FFF)<<0)

+#define SYS_CTRL_CLR_BB_RST_MASK   (0x7FFF<<0)

+#define SYS_CTRL_CLR_BB_RST_SHIFT  (0)

+

+//Clk_Sys_Mode

+#define SYS_CTRL_MODE_SYS_XCPU     (1<<0)

+#define SYS_CTRL_MODE_SYS_XCPU_INT_AUTOMATIC (0<<1)

+#define SYS_CTRL_MODE_SYS_XCPU_INT_MANUAL (1<<1)

+#define SYS_CTRL_MODE_SYS_PCLK_CONF_AUTOMATIC (0<<2)

+#define SYS_CTRL_MODE_SYS_PCLK_CONF_MANUAL (1<<2)

+#define SYS_CTRL_MODE_SYS_PCLK_DATA_AUTOMATIC (0<<3)

+#define SYS_CTRL_MODE_SYS_PCLK_DATA_MANUAL (1<<3)

+#define SYS_CTRL_MODE_SYS_AMBA_AUTOMATIC (0<<4)

+#define SYS_CTRL_MODE_SYS_AMBA_MANUAL (1<<4)

+#define SYS_CTRL_MODE_SYS_DMA_AUTOMATIC (0<<5)

+#define SYS_CTRL_MODE_SYS_DMA_MANUAL (1<<5)

+#define SYS_CTRL_MODE_SYS_EBC_AUTOMATIC (0<<6)

+#define SYS_CTRL_MODE_SYS_EBC_MANUAL (1<<6)

+#define SYS_CTRL_MODE_SYS_IFC_CH0_AUTOMATIC (0<<7)

+#define SYS_CTRL_MODE_SYS_IFC_CH0_MANUAL (1<<7)

+#define SYS_CTRL_MODE_SYS_IFC_CH1_AUTOMATIC (0<<8)

+#define SYS_CTRL_MODE_SYS_IFC_CH1_MANUAL (1<<8)

+#define SYS_CTRL_MODE_SYS_IFC_CH2_AUTOMATIC (0<<9)

+#define SYS_CTRL_MODE_SYS_IFC_CH2_MANUAL (1<<9)

+#define SYS_CTRL_MODE_SYS_IFC_CH3_AUTOMATIC (0<<10)

+#define SYS_CTRL_MODE_SYS_IFC_CH3_MANUAL (1<<10)

+#define SYS_CTRL_MODE_SYS_IFC_DBG_AUTOMATIC (0<<11)

+#define SYS_CTRL_MODE_SYS_IFC_DBG_MANUAL (1<<11)

+#define SYS_CTRL_MODE_SYS_A2A_AUTOMATIC (0<<12)

+#define SYS_CTRL_MODE_SYS_A2A_MANUAL (1<<12)

+#define SYS_CTRL_MODE_SYS_AXI2AHB_AUTOMATIC (0<<13)

+#define SYS_CTRL_MODE_SYS_AXI2AHB_MANUAL (1<<13)

+#define SYS_CTRL_MODE_SYS_AHB2AXI_AUTOMATIC (0<<14)

+#define SYS_CTRL_MODE_SYS_AHB2AXI_MANUAL (1<<14)

+#define SYS_CTRL_MODE_SYS_EXT_AHB_AUTOMATIC (0<<15)

+#define SYS_CTRL_MODE_SYS_EXT_AHB_MANUAL (1<<15)

+#define SYS_CTRL_MODE_SYS_DEBUG_UART_AUTOMATIC (0<<16)

+#define SYS_CTRL_MODE_SYS_DEBUG_UART_MANUAL (1<<16)

+#define SYS_CTRL_MODE_SYS_DBGHST_AUTOMATIC (0<<17)

+#define SYS_CTRL_MODE_SYS_DBGHST_MANUAL (1<<17)

+#define SYS_CTRL_MODE_SYSD_SCI1_AUTOMATIC (0<<18)

+#define SYS_CTRL_MODE_SYSD_SCI1_MANUAL (1<<18)

+#define SYS_CTRL_MODE_SYSD_SCI2_AUTOMATIC (0<<19)

+#define SYS_CTRL_MODE_SYSD_SCI2_MANUAL (1<<19)

+#define SYS_CTRL_MODE_SYSD_SCI3_AUTOMATIC (0<<20)

+#define SYS_CTRL_MODE_SYSD_SCI3_MANUAL (1<<20)

+#define SYS_CTRL_MODE_SYSD_RF_SPI_AUTOMATIC (0<<21)

+#define SYS_CTRL_MODE_SYSD_RF_SPI_MANUAL (1<<21)

+#define SYS_CTRL_MODE_SYSD_OSC_AUTOMATIC (0<<22)

+#define SYS_CTRL_MODE_SYSD_OSC_MANUAL (1<<22)

+#define SYS_CTRL_MODE_CLK_SYS(n)   (((n)&0x3FFFFF)<<1)

+#define SYS_CTRL_MODE_CLK_SYS_MASK (0x3FFFFF<<1)

+#define SYS_CTRL_MODE_CLK_SYS_SHIFT (1)

+

+//Clk_Sys_Enable

+#define SYS_CTRL_ENABLE_SYS_XCPU   (1<<0)

+#define SYS_CTRL_ENABLE_SYS_XCPU_INT (1<<1)

+#define SYS_CTRL_ENABLE_SYS_PCLK_CONF (1<<2)

+#define SYS_CTRL_ENABLE_SYS_PCLK_DATA (1<<3)

+#define SYS_CTRL_ENABLE_SYS_AMBA   (1<<4)

+#define SYS_CTRL_ENABLE_SYS_DMA    (1<<5)

+#define SYS_CTRL_ENABLE_SYS_EBC    (1<<6)

+#define SYS_CTRL_ENABLE_SYS_IFC_CH0 (1<<7)

+#define SYS_CTRL_ENABLE_SYS_IFC_CH1 (1<<8)

+#define SYS_CTRL_ENABLE_SYS_IFC_CH2 (1<<9)

+#define SYS_CTRL_ENABLE_SYS_IFC_CH3 (1<<10)

+#define SYS_CTRL_ENABLE_SYS_IFC_DBG (1<<11)

+#define SYS_CTRL_ENABLE_SYS_A2A    (1<<12)

+#define SYS_CTRL_ENABLE_SYS_AXI2AHB (1<<13)

+#define SYS_CTRL_ENABLE_SYS_AHB2AXI (1<<14)

+#define SYS_CTRL_ENABLE_SYS_EXT_AHB (1<<15)

+#define SYS_CTRL_ENABLE_SYS_DEBUG_UART (1<<16)

+#define SYS_CTRL_ENABLE_SYS_DBGHST (1<<17)

+#define SYS_CTRL_ENABLE_SYSD_SCI1  (1<<18)

+#define SYS_CTRL_ENABLE_SYSD_SCI2  (1<<19)

+#define SYS_CTRL_ENABLE_SYSD_SCI3  (1<<20)

+#define SYS_CTRL_ENABLE_SYSD_RF_SPI (1<<21)

+#define SYS_CTRL_ENABLE_SYSD_OSC   (1<<22)

+#define SYS_CTRL_ENABLE_SYS_GPIO   (1<<23)

+#define SYS_CTRL_ENABLE_SYS_IRQ    (1<<24)

+#define SYS_CTRL_ENABLE_SYS_TCU    (1<<25)

+#define SYS_CTRL_ENABLE_SYS_TIMER  (1<<26)

+#define SYS_CTRL_ENABLE_SYS_COM_REGS (1<<27)

+#define SYS_CTRL_ENABLE_SYS_DP_AP  (1<<28)

+#define SYS_CTRL_ENABLE_CLK_SYS(n) (((n)&0x1FFFFFFF)<<0)

+#define SYS_CTRL_ENABLE_CLK_SYS_MASK (0x1FFFFFFF<<0)

+#define SYS_CTRL_ENABLE_CLK_SYS_SHIFT (0)

+

+//Clk_Sys_Disable

+#define SYS_CTRL_DISABLE_SYS_XCPU  (1<<0)

+#define SYS_CTRL_DISABLE_SYS_XCPU_INT (1<<1)

+#define SYS_CTRL_DISABLE_SYS_PCLK_CONF (1<<2)

+#define SYS_CTRL_DISABLE_SYS_PCLK_DATA (1<<3)

+#define SYS_CTRL_DISABLE_SYS_AMBA  (1<<4)

+#define SYS_CTRL_DISABLE_SYS_DMA   (1<<5)

+#define SYS_CTRL_DISABLE_SYS_EBC   (1<<6)

+#define SYS_CTRL_DISABLE_SYS_IFC_CH0 (1<<7)

+#define SYS_CTRL_DISABLE_SYS_IFC_CH1 (1<<8)

+#define SYS_CTRL_DISABLE_SYS_IFC_CH2 (1<<9)

+#define SYS_CTRL_DISABLE_SYS_IFC_CH3 (1<<10)

+#define SYS_CTRL_DISABLE_SYS_IFC_DBG (1<<11)

+#define SYS_CTRL_DISABLE_SYS_A2A   (1<<12)

+#define SYS_CTRL_DISABLE_SYS_AXI2AHB (1<<13)

+#define SYS_CTRL_DISABLE_SYS_AHB2AXI (1<<14)

+#define SYS_CTRL_DISABLE_SYS_EXT_AHB (1<<15)

+#define SYS_CTRL_DISABLE_SYS_DEBUG_UART (1<<16)

+#define SYS_CTRL_DISABLE_SYS_DBGHST (1<<17)

+#define SYS_CTRL_DISABLE_SYSD_SCI1 (1<<18)

+#define SYS_CTRL_DISABLE_SYSD_SCI2 (1<<19)

+#define SYS_CTRL_DISABLE_SYSD_SCI3 (1<<20)

+#define SYS_CTRL_DISABLE_SYSD_RF_SPI (1<<21)

+#define SYS_CTRL_DISABLE_SYSD_OSC  (1<<22)

+#define SYS_CTRL_DISABLE_SYS_GPIO  (1<<23)

+#define SYS_CTRL_DISABLE_SYS_IRQ   (1<<24)

+#define SYS_CTRL_DISABLE_SYS_TCU   (1<<25)

+#define SYS_CTRL_DISABLE_SYS_TIMER (1<<26)

+#define SYS_CTRL_DISABLE_SYS_COM_REGS (1<<27)

+#define SYS_CTRL_DISABLE_SYS_DP_AP (1<<28)

+#define SYS_CTRL_DISABLE_CLK_SYS(n) (((n)&0x1FFFFFFF)<<0)

+#define SYS_CTRL_DISABLE_CLK_SYS_MASK (0x1FFFFFFF<<0)

+#define SYS_CTRL_DISABLE_CLK_SYS_SHIFT (0)

+

+//Clk_Per_Mode

+#define SYS_CTRL_MODE_PER_I2C_AUTOMATIC (0<<0)

+#define SYS_CTRL_MODE_PER_I2C_MANUAL (1<<0)

+#define SYS_CTRL_MODE_PERD_SPI1_AUTOMATIC (0<<1)

+#define SYS_CTRL_MODE_PERD_SPI1_MANUAL (1<<1)

+#define SYS_CTRL_MODE_PERD_SPI2_AUTOMATIC (0<<2)

+#define SYS_CTRL_MODE_PERD_SPI2_MANUAL (1<<2)

+#define SYS_CTRL_MODE_CLK_PER(n)   (((n)&7)<<0)

+#define SYS_CTRL_MODE_CLK_PER_MASK (7<<0)

+#define SYS_CTRL_MODE_CLK_PER_SHIFT (0)

+

+//Clk_Per_Enable

+#define SYS_CTRL_ENABLE_PER_I2C    (1<<0)

+#define SYS_CTRL_ENABLE_PERD_SPI1  (1<<1)

+#define SYS_CTRL_ENABLE_PERD_SPI2  (1<<2)

+#define SYS_CTRL_ENABLE_PER_SPY    (1<<3)

+#define SYS_CTRL_ENABLE_PER_TEST   (1<<4)

+#define SYS_CTRL_ENABLE_CLK_PER(n) (((n)&31)<<0)

+#define SYS_CTRL_ENABLE_CLK_PER_MASK (31<<0)

+#define SYS_CTRL_ENABLE_CLK_PER_SHIFT (0)

+

+//Clk_Per_Disable

+#define SYS_CTRL_DISABLE_PER_I2C   (1<<0)

+#define SYS_CTRL_DISABLE_PERD_SPI1 (1<<1)

+#define SYS_CTRL_DISABLE_PERD_SPI2 (1<<2)

+#define SYS_CTRL_DISABLE_PER_SPY   (1<<3)

+#define SYS_CTRL_DISABLE_PER_TEST  (1<<4)

+#define SYS_CTRL_DISABLE_CLK_PER(n) (((n)&31)<<0)

+#define SYS_CTRL_DISABLE_CLK_PER_MASK (31<<0)

+#define SYS_CTRL_DISABLE_CLK_PER_SHIFT (0)

+

+//Clk_BB_Mode

+#define SYS_CTRL_MODE_BB_BCPU      (1<<0)

+#define SYS_CTRL_MODE_BB_BCPU_INT_AUTOMATIC (0<<1)

+#define SYS_CTRL_MODE_BB_BCPU_INT_MANUAL (1<<1)

+#define SYS_CTRL_MODE_BB_AMBA_AUTOMATIC (0<<2)

+#define SYS_CTRL_MODE_BB_AMBA_MANUAL (1<<2)

+#define SYS_CTRL_MODE_BB_PCLK_CONF_AUTOMATIC (0<<3)

+#define SYS_CTRL_MODE_BB_PCLK_CONF_MANUAL (1<<3)

+#define SYS_CTRL_MODE_BB_PCLK_DATA_AUTOMATIC (0<<4)

+#define SYS_CTRL_MODE_BB_PCLK_DATA_MANUAL (1<<4)

+#define SYS_CTRL_MODE_BB_EXCOR_AUTOMATIC (0<<5)

+#define SYS_CTRL_MODE_BB_EXCOR_MANUAL (1<<5)

+#define SYS_CTRL_MODE_BB_IFC_CH2_AUTOMATIC (0<<6)

+#define SYS_CTRL_MODE_BB_IFC_CH2_MANUAL (1<<6)

+#define SYS_CTRL_MODE_BB_IFC_CH3_AUTOMATIC (0<<7)

+#define SYS_CTRL_MODE_BB_IFC_CH3_MANUAL (1<<7)

+#define SYS_CTRL_MODE_BB_SRAM_AUTOMATIC (0<<8)

+#define SYS_CTRL_MODE_BB_SRAM_MANUAL (1<<8)

+#define SYS_CTRL_MODE_BB_A2A_AUTOMATIC (0<<9)

+#define SYS_CTRL_MODE_BB_A2A_MANUAL (1<<9)

+#define SYS_CTRL_MODE_BB_ITLV_AUTOMATIC (0<<10)

+#define SYS_CTRL_MODE_BB_ITLV_MANUAL (1<<10)

+#define SYS_CTRL_MODE_BB_VITERBI_AUTOMATIC (0<<11)

+#define SYS_CTRL_MODE_BB_VITERBI_MANUAL (1<<11)

+#define SYS_CTRL_MODE_BB_CIPHER_AUTOMATIC (0<<12)

+#define SYS_CTRL_MODE_BB_CIPHER_MANUAL (1<<12)

+#define SYS_CTRL_MODE_BB_RF_IF_AUTOMATIC (0<<13)

+#define SYS_CTRL_MODE_BB_RF_IF_MANUAL (1<<13)

+#define SYS_CTRL_MODE_BB_COPRO_AUTOMATIC (0<<14)

+#define SYS_CTRL_MODE_BB_COPRO_MANUAL (1<<14)

+#define SYS_CTRL_MODE_BB_CP2_REG_AUTOMATIC (0<<15)

+#define SYS_CTRL_MODE_BB_CP2_REG_MANUAL (1<<15)

+#define SYS_CTRL_MODE_BB_XCOR_AUTOMATIC (0<<16)

+#define SYS_CTRL_MODE_BB_XCOR_MANUAL (1<<16)

+#define SYS_CTRL_MODE_BB_EVITAC_AUTOMATIC (0<<17)

+#define SYS_CTRL_MODE_BB_EVITAC_MANUAL (1<<17)

+#define SYS_CTRL_MODE_CLK_BB(n)    (((n)&0x1FFFF)<<1)

+#define SYS_CTRL_MODE_CLK_BB_MASK  (0x1FFFF<<1)

+#define SYS_CTRL_MODE_CLK_BB_SHIFT (1)

+

+//Clk_BB_Enable

+#define SYS_CTRL_ENABLE_BB_BCPU    (1<<0)

+#define SYS_CTRL_ENABLE_BB_BCPU_INT (1<<1)

+#define SYS_CTRL_ENABLE_BB_AMBA    (1<<2)

+#define SYS_CTRL_ENABLE_BB_PCLK_CONF (1<<3)

+#define SYS_CTRL_ENABLE_BB_PCLK_DATA (1<<4)

+#define SYS_CTRL_ENABLE_BB_EXCOR   (1<<5)

+#define SYS_CTRL_ENABLE_BB_IFC_CH2 (1<<6)

+#define SYS_CTRL_ENABLE_BB_IFC_CH3 (1<<7)

+#define SYS_CTRL_ENABLE_BB_SRAM    (1<<8)

+#define SYS_CTRL_ENABLE_BB_A2A     (1<<9)

+#define SYS_CTRL_ENABLE_BB_ITLV    (1<<10)

+#define SYS_CTRL_ENABLE_BB_VITERBI (1<<11)

+#define SYS_CTRL_ENABLE_BB_CIPHER  (1<<12)

+#define SYS_CTRL_ENABLE_BB_RF_IF   (1<<13)

+#define SYS_CTRL_ENABLE_BB_COPRO   (1<<14)

+#define SYS_CTRL_ENABLE_BB_CP2_REG (1<<15)

+#define SYS_CTRL_ENABLE_BB_XCOR    (1<<16)

+#define SYS_CTRL_ENABLE_BB_EVITAC  (1<<17)

+#define SYS_CTRL_ENABLE_BB_IRQ     (1<<18)

+#define SYS_CTRL_ENABLE_BB_COM_REGS (1<<19)

+#define SYS_CTRL_ENABLE_BB_CORDIC  (1<<20)

+#define SYS_CTRL_ENABLE_CLK_BB(n)  (((n)&0x1FFFFF)<<0)

+#define SYS_CTRL_ENABLE_CLK_BB_MASK (0x1FFFFF<<0)

+#define SYS_CTRL_ENABLE_CLK_BB_SHIFT (0)

+

+//Clk_BB_Disable

+#define SYS_CTRL_DISABLE_BB_BCPU   (1<<0)

+#define SYS_CTRL_DISABLE_BB_BCPU_INT (1<<1)

+#define SYS_CTRL_DISABLE_BB_AMBA   (1<<2)

+#define SYS_CTRL_DISABLE_BB_PCLK_CONF (1<<3)

+#define SYS_CTRL_DISABLE_BB_PCLK_DATA (1<<4)

+#define SYS_CTRL_DISABLE_BB_EXCOR  (1<<5)

+#define SYS_CTRL_DISABLE_BB_IFC_CH2 (1<<6)

+#define SYS_CTRL_DISABLE_BB_IFC_CH3 (1<<7)

+#define SYS_CTRL_DISABLE_BB_SRAM   (1<<8)

+#define SYS_CTRL_DISABLE_BB_A2A    (1<<9)

+#define SYS_CTRL_DISABLE_BB_ITLV   (1<<10)

+#define SYS_CTRL_DISABLE_BB_VITERBI (1<<11)

+#define SYS_CTRL_DISABLE_BB_CIPHER (1<<12)

+#define SYS_CTRL_DISABLE_BB_RF_IF  (1<<13)

+#define SYS_CTRL_DISABLE_BB_COPRO  (1<<14)

+#define SYS_CTRL_DISABLE_BB_CP2_REG (1<<15)

+#define SYS_CTRL_DISABLE_BB_XCOR   (1<<16)

+#define SYS_CTRL_DISABLE_BB_EVITAC (1<<17)

+#define SYS_CTRL_DISABLE_BB_IRQ    (1<<18)

+#define SYS_CTRL_DISABLE_BB_COM_REGS (1<<19)

+#define SYS_CTRL_DISABLE_BB_CORDIC (1<<20)

+#define SYS_CTRL_DISABLE_CLK_BB(n) (((n)&0x1FFFFF)<<0)

+#define SYS_CTRL_DISABLE_CLK_BB_MASK (0x1FFFFF<<0)

+#define SYS_CTRL_DISABLE_CLK_BB_SHIFT (0)

+

+//Clk_Other_Mode

+#define SYS_CTRL_MODE_OC_DEBUG_UART_AUTOMATIC (0<<0)

+#define SYS_CTRL_MODE_OC_DEBUG_UART_MANUAL (1<<0)

+#define SYS_CTRL_MODE_OC_RF_RX_AUTOMATIC (0<<1)

+#define SYS_CTRL_MODE_OC_RF_RX_MANUAL (1<<1)

+#define SYS_CTRL_MODE_OC_RF_TX_AUTOMATIC (0<<2)

+#define SYS_CTRL_MODE_OC_RF_TX_MANUAL (1<<2)

+#define SYS_CTRL_MODE_OC_MEM_BRIDGE_AUTOMATIC (0<<3)

+#define SYS_CTRL_MODE_OC_MEM_BRIDGE_MANUAL (1<<3)

+#define SYS_CTRL_MODE_CLK_OTHER(n) (((n)&15)<<0)

+#define SYS_CTRL_MODE_CLK_OTHER_MASK (15<<0)

+#define SYS_CTRL_MODE_CLK_OTHER_SHIFT (0)

+

+//Clk_Other_Enable

+#define SYS_CTRL_ENABLE_OC_DEBUG_UART (1<<0)

+#define SYS_CTRL_ENABLE_OC_RF_RX   (1<<1)

+#define SYS_CTRL_ENABLE_OC_RF_TX   (1<<2)

+#define SYS_CTRL_ENABLE_OC_MEM_BRIDGE (1<<3)

+#define SYS_CTRL_ENABLE_OC_LPS     (1<<4)

+#define SYS_CTRL_ENABLE_OC_GPIO    (1<<5)

+#define SYS_CTRL_ENABLE_OC_CLK_OUT (1<<6)

+#define SYS_CTRL_ENABLE_OC_MEM_CLK_OUT (1<<7)

+#define SYS_CTRL_ENABLE_OC_TCU     (1<<8)

+#define SYS_CTRL_ENABLE_CLK_OTHER(n) (((n)&0x1FF)<<0)

+#define SYS_CTRL_ENABLE_CLK_OTHER_MASK (0x1FF<<0)

+#define SYS_CTRL_ENABLE_CLK_OTHER_SHIFT (0)

+

+//Clk_Other_Disable

+#define SYS_CTRL_DISABLE_OC_DEBUG_UART (1<<0)

+#define SYS_CTRL_DISABLE_OC_RF_RX  (1<<1)

+#define SYS_CTRL_DISABLE_OC_RF_TX  (1<<2)

+#define SYS_CTRL_DISABLE_OC_MEM_BRIDGE (1<<3)

+#define SYS_CTRL_DISABLE_OC_LPS    (1<<4)

+#define SYS_CTRL_DISABLE_OC_GPIO   (1<<5)

+#define SYS_CTRL_DISABLE_OC_CLK_OUT (1<<6)

+#define SYS_CTRL_DISABLE_OC_MEM_CLK_OUT (1<<7)

+#define SYS_CTRL_DISABLE_OC_TCU    (1<<8)

+#define SYS_CTRL_DISABLE_CLK_OTHER(n) (((n)&0x1FF)<<0)

+#define SYS_CTRL_DISABLE_CLK_OTHER_MASK (0x1FF<<0)

+#define SYS_CTRL_DISABLE_CLK_OTHER_SHIFT (0)

+

+//Pll_Ctrl

+#define SYS_CTRL_PLL_ENABLE        (1<<0)

+#define SYS_CTRL_PLL_ENABLE_MASK   (1<<0)

+#define SYS_CTRL_PLL_ENABLE_SHIFT  (0)

+#define SYS_CTRL_PLL_ENABLE_POWER_DOWN (0<<0)

+#define SYS_CTRL_PLL_ENABLE_ENABLE (1<<0)

+#define SYS_CTRL_PLL_LOCK_RESET    (1<<4)

+#define SYS_CTRL_PLL_LOCK_RESET_MASK (1<<4)

+#define SYS_CTRL_PLL_LOCK_RESET_SHIFT (4)

+#define SYS_CTRL_PLL_LOCK_RESET_RESET (0<<4)

+#define SYS_CTRL_PLL_LOCK_RESET_NO_RESET (1<<4)

+#define SYS_CTRL_PLL_BYPASS        (1<<8)

+#define SYS_CTRL_PLL_BYPASS_MASK   (1<<8)

+#define SYS_CTRL_PLL_BYPASS_SHIFT  (8)

+#define SYS_CTRL_PLL_BYPASS_PASS   (0<<8)

+#define SYS_CTRL_PLL_BYPASS_BYPASS (1<<8)

+#define SYS_CTRL_PLL_CLK_FAST_ENABLE (1<<12)

+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_MASK (1<<12)

+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_SHIFT (12)

+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_ENABLE (1<<12)

+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_DISABLE (0<<12)

+#define SYS_CTRL_PLL_XP_CFG(n)     (((n)&4369)<<0)

+#define SYS_CTRL_PLL_XP_CFG_MASK   (4369<<0)

+#define SYS_CTRL_PLL_XP_CFG_SHIFT  (0)

+

+//Sel_Clock

+#define SYS_CTRL_SLOW_SEL_RF_OSCILLATOR (1<<0)

+#define SYS_CTRL_SLOW_SEL_RF_RF    (0<<0)

+#define SYS_CTRL_SYS_SEL_FAST_SLOW (1<<4)

+#define SYS_CTRL_SYS_SEL_FAST_FAST (0<<4)

+#define SYS_CTRL_TCU_13M_L_26M     (1<<5)

+#define SYS_CTRL_TCU_13M_L_13M     (0<<5)

+#define SYS_CTRL_PLL_DISABLE_LPS_DISABLE (1<<6)

+#define SYS_CTRL_PLL_DISABLE_LPS_ENABLE (0<<6)

+#define SYS_CTRL_DIGEN_H_ENABLE    (1<<7)

+#define SYS_CTRL_DIGEN_H_DISABLE   (0<<7)

+#define SYS_CTRL_RF_DETECTED_OK    (1<<20)

+#define SYS_CTRL_RF_DETECTED_NO    (0<<20)

+#define SYS_CTRL_RF_DETECT_BYPASS  (1<<21)

+#define SYS_CTRL_RF_DETECT_RESET   (1<<22)

+#define SYS_CTRL_RF_SELECTED_L     (1<<23)

+#define SYS_CTRL_PLL_LOCKED        (1<<24)

+#define SYS_CTRL_PLL_LOCKED_MASK   (1<<24)

+#define SYS_CTRL_PLL_LOCKED_SHIFT  (24)

+#define SYS_CTRL_PLL_LOCKED_LOCKED (1<<24)

+#define SYS_CTRL_PLL_LOCKED_NOT_LOCKED (0<<24)

+#define SYS_CTRL_PLL_BYPASS_LOCK   (1<<27)

+#define SYS_CTRL_FAST_SELECTED_L   (1<<31)

+#define SYS_CTRL_FAST_SELECTED_L_MASK (1<<31)

+#define SYS_CTRL_FAST_SELECTED_L_SHIFT (31)

+

+//Cfg_Clk_Sys

+#define SYS_CTRL_FREQ(n)           (((n)&15)<<0)

+#define SYS_CTRL_FREQ_MASK         (15<<0)

+#define SYS_CTRL_FREQ_SHIFT        (0)

+#define SYS_CTRL_FREQ_312M         (13<<0)

+#define SYS_CTRL_FREQ_250M         (12<<0)

+#define SYS_CTRL_FREQ_208M         (11<<0)

+#define SYS_CTRL_FREQ_178M         (10<<0)

+#define SYS_CTRL_FREQ_156M         (9<<0)

+#define SYS_CTRL_FREQ_139M         (8<<0)

+#define SYS_CTRL_FREQ_125M         (7<<0)

+#define SYS_CTRL_FREQ_113M         (6<<0)

+#define SYS_CTRL_FREQ_104M         (5<<0)

+#define SYS_CTRL_FREQ_89M          (4<<0)

+#define SYS_CTRL_FREQ_78M          (3<<0)

+#define SYS_CTRL_FREQ_52M          (2<<0)

+#define SYS_CTRL_FREQ_39M          (1<<0)

+#define SYS_CTRL_FREQ_26M          (0<<0)

+#define SYS_CTRL_FORCE_DIV_UPDATE  (1<<4)

+#define SYS_CTRL_REQ_DIV_UPDATE    (1<<8)

+

+//Cfg_Clk_Mem_Bridge

+#define SYS_CTRL_MEM_FREQ(n)       (((n)&15)<<0)

+#define SYS_CTRL_MEM_FREQ_MASK     (15<<0)

+#define SYS_CTRL_MEM_FREQ_SHIFT    (0)

+#define SYS_CTRL_MEM_FREQ_312M     (13<<0)

+#define SYS_CTRL_MEM_FREQ_250M     (12<<0)

+#define SYS_CTRL_MEM_FREQ_208M     (11<<0)

+#define SYS_CTRL_MEM_FREQ_178M     (10<<0)

+#define SYS_CTRL_MEM_FREQ_156M     (9<<0)

+#define SYS_CTRL_MEM_FREQ_139M     (8<<0)

+#define SYS_CTRL_MEM_FREQ_125M     (7<<0)

+#define SYS_CTRL_MEM_FREQ_113M     (6<<0)

+#define SYS_CTRL_MEM_FREQ_104M     (5<<0)

+#define SYS_CTRL_MEM_FREQ_89M      (4<<0)

+#define SYS_CTRL_MEM_FREQ_78M      (3<<0)

+#define SYS_CTRL_MEM_FREQ_52M      (2<<0)

+#define SYS_CTRL_MEM_FREQ_39M      (1<<0)

+#define SYS_CTRL_MEM_FREQ_26M      (0<<0)

+#define SYS_CTRL_DDR_MODE_EN_NORMAL_MODE (0<<4)

+#define SYS_CTRL_DDR_MODE_EN_DDR_MODE (1<<4)

+#define SYS_CTRL_DDR_FAST_CLK_POL_INVERT (1<<5)

+#define SYS_CTRL_DDR_FAST_CLK_POL_NORMAL (0<<5)

+#define SYS_CTRL_DDR_DQSL_O(n)     (((n)&31)<<6)

+#define SYS_CTRL_DDR_DQSU_O(n)     (((n)&31)<<11)

+#define SYS_CTRL_DDR_DQS_OEN(n)    (((n)&31)<<16)

+#define SYS_CTRL_DDR_DQSL_I(n)     (((n)&31)<<21)

+#define SYS_CTRL_DDR_DQSU_I(n)     (((n)&31)<<26)

+#define SYS_CTRL_MEM_REQ_DIV_UPDATE (1<<31)

+

+//Cfg_Clk_Out

+#define SYS_CTRL_CLKOUT_DIVIDER(n) (((n)&31)<<0)

+#define SYS_CTRL_CLKOUT_SEL_OSC    (0<<8)

+#define SYS_CTRL_CLKOUT_SEL_RF     (1<<8)

+#define SYS_CTRL_CLKOUT_SEL_DIVIDER (2<<8)

+

+//Cfg_Clk_Host_Uart

+#define SYS_CTRL_HOST_UART_DIVIDER(n) (((n)&0x3FF)<<0)

+#define SYS_CTRL_HOST_UART_DIVIDER_MASK (0x3FF<<0)

+#define SYS_CTRL_HOST_UART_DIVIDER_SHIFT (0)

+#define SYS_CTRL_HOST_UART_SEL_PLL_SLOW (0<<12)

+#define SYS_CTRL_HOST_UART_SEL_PLL_PLL (1<<12)

+

+//Cfg_Clk_Auxclk

+#define SYS_CTRL_AUXCLK_EN_DISABLE (0<<0)

+#define SYS_CTRL_AUXCLK_EN_ENABLE  (1<<0)

+

+//Cfg_AHB

+#define SYS_CTRL_SYS_NEW_ARBITRATION_ENABLE (1<<0)

+#define SYS_CTRL_SYS_NEW_ARBITRATION_DISABLE (0<<0)

+#define SYS_CTRL_ENABLE_SYS_MID_BIST_ENABLE (1<<1)

+#define SYS_CTRL_ENABLE_SYS_MID_BIST_DISABLE (0<<1)

+#define SYS_CTRL_ENABLE_SYS_MID_DMA_ENABLE (1<<2)

+#define SYS_CTRL_ENABLE_SYS_MID_DMA_DISABLE (0<<2)

+#define SYS_CTRL_ENABLE_SYS_MID_XCPU_ENABLE (1<<3)

+#define SYS_CTRL_ENABLE_SYS_MID_XCPU_DISABLE (0<<3)

+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_ENABLE (1<<4)

+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_DISABLE (0<<4)

+#define SYS_CTRL_ENABLE_SYS_MID_IFC_ENABLE (1<<5)

+#define SYS_CTRL_ENABLE_SYS_MID_IFC_DISABLE (0<<5)

+#define SYS_CTRL_ENABLE_SYS_MID_AXI2AHB_ENABLE (1<<6)

+#define SYS_CTRL_ENABLE_SYS_MID_AXI2AHB_DISABLE (0<<6)

+#define SYS_CTRL_BB_NEW_ARBITRATION_ENABLE (1<<16)

+#define SYS_CTRL_BB_NEW_ARBITRATION_DISABLE (0<<16)

+#define SYS_CTRL_ENABLE_BB_MID_BIST_ENABLE (1<<17)

+#define SYS_CTRL_ENABLE_BB_MID_BIST_DISABLE (0<<17)

+#define SYS_CTRL_ENABLE_BB_MID_IFC_ENABLE (1<<18)

+#define SYS_CTRL_ENABLE_BB_MID_IFC_DISABLE (0<<18)

+#define SYS_CTRL_ENABLE_BB_MID_BCPU_ENABLE (1<<19)

+#define SYS_CTRL_ENABLE_BB_MID_BCPU_DISABLE (0<<19)

+#define SYS_CTRL_ENABLE_BB_MID_AHB2AHB_ENABLE (1<<20)

+#define SYS_CTRL_ENABLE_BB_MID_AHB2AHB_DISABLE (0<<20)

+#define SYS_CTRL_SYS_ENABLE(n)     (((n)&0x3F)<<1)

+#define SYS_CTRL_SYS_ENABLE_MASK   (0x3F<<1)

+#define SYS_CTRL_SYS_ENABLE_SHIFT  (1)

+#define SYS_CTRL_BB_ENABLE(n)      (((n)&15)<<17)

+#define SYS_CTRL_BB_ENABLE_MASK    (15<<17)

+#define SYS_CTRL_BB_ENABLE_SHIFT   (17)

+

+//Ctrl_AHB

+#define SYS_CTRL_SPLIT_SYS_MID_BIST_NORMAL (1<<0)

+#define SYS_CTRL_SPLIT_SYS_MID_BIST_FORCE (0<<0)

+#define SYS_CTRL_SPLIT_SYS_MID_DMA_NORMAL (1<<1)

+#define SYS_CTRL_SPLIT_SYS_MID_DMA_FORCE (0<<1)

+#define SYS_CTRL_SPLIT_SYS_MID_XCPU_NORMAL (1<<2)

+#define SYS_CTRL_SPLIT_SYS_MID_XCPU_FORCE (0<<2)

+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_NORMAL (1<<3)

+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_FORCE (0<<3)

+#define SYS_CTRL_SPLIT_SYS_MID_IFC_NORMAL (1<<4)

+#define SYS_CTRL_SPLIT_SYS_MID_IFC_FORCE (0<<4)

+#define SYS_CTRL_SPLIT_SYS_MID_AXI2AHB_NORMAL (1<<5)

+#define SYS_CTRL_SPLIT_SYS_MID_AXI2AHB_FORCE (0<<5)

+#define SYS_CTRL_SPLIT_BB_MID_BIST_NORMAL (1<<16)

+#define SYS_CTRL_SPLIT_BB_MID_BIST_FORCE (0<<16)

+#define SYS_CTRL_SPLIT_BB_MID_IFC_NORMAL (1<<17)

+#define SYS_CTRL_SPLIT_BB_MID_IFC_FORCE (0<<17)

+#define SYS_CTRL_SPLIT_BB_MID_BCPU_NORMAL (1<<18)

+#define SYS_CTRL_SPLIT_BB_MID_BCPU_FORCE (0<<18)

+#define SYS_CTRL_SPLIT_BB_MID_AHB2AHB_NORMAL (1<<19)

+#define SYS_CTRL_SPLIT_BB_MID_AHB2AHB_FORCE (0<<19)

+#define SYS_CTRL_SYS_FORCE_HSPLIT(n) (((n)&0x3F)<<0)

+#define SYS_CTRL_SYS_FORCE_HSPLIT_MASK (0x3F<<0)

+#define SYS_CTRL_SYS_FORCE_HSPLIT_SHIFT (0)

+#define SYS_CTRL_BB_FORCE_HSPLIT(n) (((n)&15)<<16)

+#define SYS_CTRL_BB_FORCE_HSPLIT_MASK (15<<16)

+#define SYS_CTRL_BB_FORCE_HSPLIT_SHIFT (16)

+

+//XCpu_Dbg_BKP

+#define SYS_CTRL_BKPT_EN           (1<<0)

+#define SYS_CTRL_BKPT_MODE(n)      (((n)&3)<<4)

+#define SYS_CTRL_BKPT_MODE_I       (0<<4)

+#define SYS_CTRL_BKPT_MODE_R       (1<<4)

+#define SYS_CTRL_BKPT_MODE_W       (2<<4)

+#define SYS_CTRL_BKPT_MODE_RW      (3<<4)

+#define SYS_CTRL_STALLED           (1<<8)

+

+//XCpu_Dbg_Addr

+#define SYS_CTRL_BREAKPOINT_ADDRESS(n) (((n)&0x3FFFFFF)<<0)

+

+//BCpu_Dbg_BKP

+//#define SYS_CTRL_BKPT_EN         (1<<0)

+//#define SYS_CTRL_BKPT_MODE(n)    (((n)&3)<<4)

+//#define SYS_CTRL_BKPT_MODE_I     (0<<4)

+//#define SYS_CTRL_BKPT_MODE_R     (1<<4)

+//#define SYS_CTRL_BKPT_MODE_W     (2<<4)

+//#define SYS_CTRL_BKPT_MODE_RW    (3<<4)

+//#define SYS_CTRL_STALLED         (1<<8)

+

+//BCpu_Dbg_Addr

+//#define SYS_CTRL_BREAKPOINT_ADDRESS(n) (((n)&0x3FFFFFF)<<0)

+

+//Cfg_Cpus_Cache_Ram_Disable

+#define SYS_CTRL_XCPU_USE_MODE     (1<<0)

+#define SYS_CTRL_XCPU_CLK_OFF_MODE (1<<1)

+#define SYS_CTRL_BCPU_USE_MODE     (1<<16)

+#define SYS_CTRL_BCPU_CLK_OFF_MODE (1<<17)

+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE(n) (((n)&3)<<0)

+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE_MASK (3<<0)

+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE_SHIFT (0)

+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE(n) (((n)&3)<<16)

+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE_MASK (3<<16)

+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE_SHIFT (16)

+

+//Reset_Cause

+#define SYS_CTRL_WATCHDOG_RESET_HAPPENED (1<<0)

+#define SYS_CTRL_WATCHDOG_RESET_NO (0<<0)

+#define SYS_CTRL_APSOFT_RESET_HAPPENED (1<<1)

+#define SYS_CTRL_APSOFT_RESET_NO   (0<<1)

+#define SYS_CTRL_GLOBALSOFT_RESET_HAPPENED (1<<4)

+#define SYS_CTRL_GLOBALSOFT_RESET_NO (0<<4)

+#define SYS_CTRL_HOSTDEBUG_RESET_HAPPENED (1<<5)

+#define SYS_CTRL_HOSTDEBUG_RESET_NO (0<<5)

+#define SYS_CTRL_ALARMCAUSE_HAPPENED (1<<6)

+#define SYS_CTRL_ALARMCAUSE_NO     (0<<6)

+#define SYS_CTRL_MEMCHECKDONE_MASK (1<<7)

+#define SYS_CTRL_MEMCHECKDONE_SHIFT (7)

+#define SYS_CTRL_MEMCHECKDONE_DONE (1<<7)

+#define SYS_CTRL_MEMCHECKDONE_RUNNING (0<<7)

+#define SYS_CTRL_BOOT_MODE(n)      (((n)&0xFFFF)<<8)

+#define SYS_CTRL_BOOT_MODE_MASK    (0xFFFF<<8)

+#define SYS_CTRL_BOOT_MODE_SHIFT   (8)

+#define SYS_CTRL_SW_BOOT_MODE(n)   (((n)&0x7F)<<24)

+#define SYS_CTRL_SW_BOOT_MODE_MASK (0x7F<<24)

+#define SYS_CTRL_SW_BOOT_MODE_SHIFT (24)

+#define SYS_CTRL_FONCTIONAL_TEST_MODE (1<<31)

+

+//WakeUp

+#define SYS_CTRL_FORCE_WAKEUP      (1<<0)

+

+//AP_Ctrl

+#define SYS_CTRL_AP_INT_STATUS     (1<<0)

+#define SYS_CTRL_AP_INT_MASK       (1<<16)

+#define SYS_CTRL_AP_DEEPSLEEP_EN   (1<<24)

+

+//Ignore_Charger

+#define SYS_CTRL_IGNORE_CHARGER    (1<<0)

+

+//Cfg_Reserve

+#define SYS_CTRL_RESERVE_L(n)      (((n)&0x3FFF)<<0)

+#define SYS_CTRL_AUIFC_CH0_IRQ_MASK (1<<14)

+#define SYS_CTRL_AUIFC_CH1_IRQ_MASK (1<<15)

+#define SYS_CTRL_RESERVE_H(n)      (((n)&0xFFFF)<<16)

+

+

+

+

+

+#endif

+

diff --git a/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8810h.h b/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8810h.h
new file mode 100644
index 0000000000..0ecd75897f
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8810h.h
@@ -0,0 +1,979 @@
+#ifndef _REG_MD_SYSCTRL_H_

+#define _REG_MD_SYSCTRL_H_

+

+#include <asm/arch/hardware.h>

+#include <asm/arch/rda_iomap.h>

+

+// =============================================================================

+//  MACROS

+// =============================================================================

+

+// ============================================================================

+// CPU_ID_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// CPU IDs

+    XCPU                                        = 0x00000000,

+    BCPU                                        = 0x00000001

+} CPU_ID_T;

+

+

+// ============================================================================

+// SYS_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// System side System clocks

+    SYS_XCPU                                    = 0x00000000,

+    SYS_XCPU_INT                                = 0x00000001,

+    SYS_PCLK_CONF                               = 0x00000002,

+    SYS_PCLK_DATA                               = 0x00000003,

+    SYS_AMBA                                    = 0x00000004,

+    SYS_DMA                                     = 0x00000005,

+    SYS_EBC                                     = 0x00000006,

+    SYS_IFC_CH0                                 = 0x00000007,

+    SYS_IFC_CH1                                 = 0x00000008,

+    SYS_IFC_CH2                                 = 0x00000009,

+    SYS_IFC_CH3                                 = 0x0000000A,

+    SYS_IFC_DBG                                 = 0x0000000B,

+    SYS_A2A                                     = 0x0000000C,

+    SYS_AXI2AHB                                 = 0x0000000D,

+    SYS_AHB2AXI                                 = 0x0000000E,

+    SYS_EXT_AHB                                 = 0x0000000F,

+    SYS_DEBUG_UART                              = 0x00000010,

+    SYS_DBGHST                                  = 0x00000011,

+/// System side divided clock (either divided by module or by sys_ctrl)

+    SYSD_SCI1                                   = 0x00000012,

+    SYSD_SCI2                                   = 0x00000013,

+    SYSD_SCI3                                   = 0x00000014,

+    SYSD_RF_SPI                                 = 0x00000015,

+    SYSD_OSC                                    = 0x00000016,

+/// the following don't have an auto enable

+    SYS_GPIO                                    = 0x00000017,

+    SYS_IRQ                                     = 0x00000018,

+    SYS_TCU                                     = 0x00000019,

+    SYS_TIMER                                   = 0x0000001A,

+    SYS_COM_REGS                                = 0x0000001B,

+    SYS_DP_AP                                   = 0x0000001C,

+/// the following are sharing their enable

+    SYS_SCI1                                    = 0x0000001D,

+    SYS_SCI2                                    = 0x0000001E,

+    SYS_SCI3                                    = 0x0000001F,

+/// keep last

+    SYS_NOGATE                                  = 0x00000020

+} SYS_CLKS_T;

+

+#define NB_SYS_CLK_XCPU                         (2)

+#define NB_SYS_CLK_AEN                          (23)

+#define NB_SYS_CLK_EN                           (29)

+#define NB_SYS_CLK                              (33)

+

+// ============================================================================

+// PER_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+    PER_I2C                                     = 0x00000000,

+/// System side divided clock (either divided by module or by sys_ctrl)

+    PERD_SPI1                                   = 0x00000001,

+/// System side divided clock (either divided by module or by sys_ctrl)

+    PERD_SPI2                                   = 0x00000002,

+    PER_SPY                                     = 0x00000003,

+    PER_TEST                                    = 0x00000004

+} PER_CLKS_T;

+

+#define NB_PER_CLK_AEN                          (3)

+#define NB_PER_CLK_EN                           (5)

+#define NB_PER_CLK                              (5)

+

+// ============================================================================

+// BB_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// Baseband side System clocks

+    BB_BCPU                                     = 0x00000000,

+    BB_BCPU_INT                                 = 0x00000001,

+    BB_AMBA                                     = 0x00000002,

+    BB_PCLK_CONF                                = 0x00000003,

+    BB_PCLK_DATA                                = 0x00000004,

+    BB_EXCOR                                    = 0x00000005,

+    BB_IFC_CH2                                  = 0x00000006,

+    BB_IFC_CH3                                  = 0x00000007,

+    BB_SRAM                                     = 0x00000008,

+    BB_A2A                                      = 0x00000009,

+    BB_ITLV                                     = 0x0000000A,

+    BB_VITERBI                                  = 0x0000000B,

+    BB_CIPHER                                   = 0x0000000C,

+    BB_RF_IF                                    = 0x0000000D,

+    BB_COPRO                                    = 0x0000000E,

+    BB_CP2_REG                                  = 0x0000000F,

+    BB_XCOR                                     = 0x00000010,

+    BB_EVITAC                                   = 0x00000011,

+/// the following don't have an auto enable

+    BB_IRQ                                      = 0x00000012,

+    BB_COM_REGS                                 = 0x00000013,

+    BB_CORDIC                                   = 0x00000014

+} BB_CLKS_T;

+

+#define NB_BB_CLK_AEN                           (18)

+#define NB_BB_CLK_EN                            (21)

+#define NB_BB_CLK                               (21)

+/// Other clocks

+/// clocks with auto enble

+/// the debug host clock auto enable is not used in host mode, only in uart mode

+#define OC_HOST_UART                            (0)

+

+// ============================================================================

+// OTHER_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+    OC_DEBUG_UART                               = 0x00000000,

+    OC_RF_RX                                    = 0x00000001,

+    OC_RF_TX                                    = 0x00000002,

+    OC_MEM_BRIDGE                               = 0x00000003,

+/// the following don't have an auto enable

+    OC_LPS                                      = 0x00000004,

+    OC_GPIO                                     = 0x00000005,

+    OC_CLK_OUT                                  = 0x00000006,

+    OC_MEM_CLK_OUT                              = 0x00000007,

+    OC_TCU                                      = 0x00000008

+} OTHER_CLKS_T;

+

+#define NB_OTHER_CLK_AEN                        (4)

+#define NB_OTHER_CLK_EN                         (9)

+#define NB_OTHER_CLK                            (9)

+

+// ============================================================================

+// RESETS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// System side resets

+    RST_XCPU                                    = 0x00000000,

+    RST_SYS_IRQ                                 = 0x00000001,

+    RST_SYS_A2A                                 = 0x00000002,

+    RST_SYS_AHB2AXI                             = 0x00000003,

+    RST_SYS_AXI2AHB                             = 0x00000004,

+    RST_DMA                                     = 0x00000005,

+    RST_TIMER                                   = 0x00000006,

+    RST_TCU                                     = 0x00000007,

+    RST_GPIO                                    = 0x00000008,

+    RST_I2C                                     = 0x00000009,

+    RST_SPI1                                    = 0x0000000A,

+    RST_SPI2                                    = 0x0000000B,

+    RST_RF_SPI                                  = 0x0000000C,

+    RST_SCI1                                    = 0x0000000D,

+    RST_SCI2                                    = 0x0000000E,

+    RST_SCI3                                    = 0x0000000F,

+    RST_SPY                                     = 0x00000010,

+    RST_MEM_BRIDGE                              = 0x00000011,

+    RST_EXT_AHB                                 = 0x00000012,

+    RST_DP_AP                                   = 0x00000013,

+    RST_COMREGS                                 = 0x00000014,

+    RST_COMREGS_AP                              = 0x00000015,

+    RST_AP_CLKEN                                = 0x00000016,

+    RST_AP_RST                                  = 0x00000017,

+    RST_MEM_CHK                                 = 0x00000018,

+    RST_AP_RST1                                 = 0x00000019,

+    RST_AP_RST2                                 = 0x0000001A,

+    RST_AP_RST3                                 = 0x0000001B,

+    RST_AP_RST4                                 = 0x0000001C,

+    RST_AP_RST5                                 = 0x0000001D,

+    RST_BCPU                                    = 0x0000001E,

+    RST_BB_IRQ                                  = 0x0000001F,

+    RST_BB_A2A                                  = 0x00000020,

+    RST_BB_IFC                                  = 0x00000021,

+    RST_BB_SRAM                                 = 0x00000022,

+    RST_ITLV                                    = 0x00000023,

+    RST_VITERBI                                 = 0x00000024,

+    RST_CIPHER                                  = 0x00000025,

+    RST_XCOR                                    = 0x00000026,

+    RST_COPRO                                   = 0x00000027,

+    RST_RF_IF                                   = 0x00000028,

+    RST_EXCOR                                   = 0x00000029,

+    RST_EVITAC                                  = 0x0000002A,

+    RST_CORDIC                                  = 0x0000002B,

+    RST_TCU_BB                                  = 0x0000002C,

+    RST_BB_FULL                                 = 0x0000002D,

+    RST_SYS_FULL                                = 0x0000002E

+} RESETS_T;

+

+#define NB_SRST                                 (30)

+/// Baseband side resets

+#define BOUND_BRST_FIRST                        (30)

+#define BOUND_BRST_AFTER                        (45)

+/// The following reset does not have register

+#define NR_RST_REG                              (46)

+#define NB_RST                                  (47)

+#define NB_BRST                                 (BOUND_BRST_AFTER-BOUND_BRST_FIRST)

+

+// ============================================================================

+// RESET_OTHERS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// Reset Other : resync on corresponding clock other

+    RSTO_DBG_HOST                               = 0x00000000,

+    RSTO_RF_RX                                  = 0x00000001,

+    RSTO_RF_TX                                  = 0x00000002,

+    RSTO_MEM_BRIDGE                             = 0x00000003,

+    RSTO_LPS                                    = 0x00000004,

+    RSTO_GPIO                                   = 0x00000005,

+    RSTO_WDTIMER                                = 0x00000006,

+    RSTO_TCU                                    = 0x00000007

+} RESET_OTHERS_T;

+

+#define BOUND_RSTO_RF_FIRST                     (1)

+#define BOUND_RSTO_RF_AFTER                     (3)

+#define NB_RSTO                                 (8)

+/// For REG_DBG protect lock/unlock value

+#define SYS_CTRL_PROTECT_LOCK                   (0XA50000)

+#define SYS_CTRL_PROTECT_UNLOCK                 (0XA50001)

+

+// =============================================================================

+//  TYPES

+// =============================================================================

+

+// ============================================================================

+// SYS_CTRL_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef volatile struct

+{

+    /// <strong>This register is used to Lock and Unlock the protected registers.</strong>

+    REG32                          REG_DBG;                      //0x00000000

+    /// This register is protected.

+    REG32                          Sys_Rst_Set;                  //0x00000004

+    REG32                          Sys_Rst_Clr;                  //0x00000008

+    /// This register is protected.

+    REG32                          BB_Rst_Set;                   //0x0000000C

+    REG32                          BB_Rst_Clr;                   //0x00000010

+    REG32                          Clk_Sys_Mode;                 //0x00000014

+    REG32                          Clk_Sys_Enable;               //0x00000018

+    /// This register is protected.

+    REG32                          Clk_Sys_Disable;              //0x0000001C

+    REG32                          Clk_Per_Mode;                 //0x00000020

+    REG32                          Clk_Per_Enable;               //0x00000024

+    /// This register is protected.

+    REG32                          Clk_Per_Disable;              //0x00000028

+    REG32                          Clk_BB_Mode;                  //0x0000002C

+    REG32                          Clk_BB_Enable;                //0x00000030

+    /// This register is protected.

+    REG32                          Clk_BB_Disable;               //0x00000034

+    REG32                          Clk_Other_Mode;               //0x00000038

+    REG32                          Clk_Other_Enable;             //0x0000003C

+    /// This register is protected.

+    REG32                          Clk_Other_Disable;            //0x00000040

+    /// Register protected by Write_Unlocked_H.

+    REG32                          Pll_Ctrl;                     //0x00000044

+    /// This register is protected.

+    REG32                          Sel_Clock;                    //0x00000048

+    REG32                          Cfg_Clk_Sys;                  //0x0000004C

+    REG32                          Cfg_Clk_Mem_Bridge;           //0x00000050

+    /// This register is protected.

+    REG32                          Cfg_Clk_Out;                  //0x00000054

+    REG32                          Cfg_Clk_Host_Uart;            //0x00000058

+    REG32                          Cfg_Clk_Auxclk;               //0x0000005C

+    /// This register is protected.

+    REG32                          Cfg_AHB;                      //0x00000060

+    /// This register is protected. Used to unsplit masters manualy.

+    REG32                          Ctrl_AHB;                     //0x00000064

+    REG32                          XCpu_Dbg_BKP;                 //0x00000068

+    REG32                          XCpu_Dbg_Addr;                //0x0000006C

+    REG32                          BCpu_Dbg_BKP;                 //0x00000070

+    REG32                          BCpu_Dbg_Addr;                //0x00000074

+    REG32                          Cfg_Cpus_Cache_Ram_Disable;   //0x00000078

+    REG32                          Reset_Cause;                  //0x0000007C

+    /// This register is protected.

+    REG32                          WakeUp;                       //0x00000080

+    REG32                          AP_Ctrl;                      //0x00000084

+    /// This register is protected.

+    REG32                          Ignore_Charger;               //0x00000088

+    REG32 Reserved_0000008C[28];                //0x0000008C

+    /// This register is reserved.

+    REG32                          Cfg_Reserve;                  //0x000000FC

+} HWP_SYS_CTRL_T;

+

+#define hwp_sysCtrlMd               ((HWP_SYS_CTRL_T*)(RDA_MD_SYSCTRL_BASE))

+

+

+//REG_DBG

+#define SYS_CTRL_SCRATCH(n)        (((n)&0xFFFF)<<0)

+#define SYS_CTRL_WRITE_UNLOCK_STATUS (1<<30)

+#define SYS_CTRL_WRITE_UNLOCK      (1<<31)

+

+//Sys_Rst_Set

+#define SYS_CTRL_SET_RST_XCPU      (1<<0)

+#define SYS_CTRL_SET_RST_SYS_IRQ   (1<<1)

+#define SYS_CTRL_SET_RST_SYS_A2A   (1<<2)

+#define SYS_CTRL_SET_RST_SYS_AHB2AXI (1<<3)

+#define SYS_CTRL_SET_RST_SYS_AXI2AHB (1<<4)

+#define SYS_CTRL_SET_RST_DMA       (1<<5)

+#define SYS_CTRL_SET_RST_TIMER     (1<<6)

+#define SYS_CTRL_SET_RST_TCU       (1<<7)

+#define SYS_CTRL_SET_RST_GPIO      (1<<8)

+#define SYS_CTRL_SET_RST_I2C       (1<<9)

+#define SYS_CTRL_SET_RST_SPI1      (1<<10)

+#define SYS_CTRL_SET_RST_SPI2      (1<<11)

+#define SYS_CTRL_SET_RST_RF_SPI    (1<<12)

+#define SYS_CTRL_SET_RST_SCI1      (1<<13)

+#define SYS_CTRL_SET_RST_SCI2      (1<<14)

+#define SYS_CTRL_SET_RST_SCI3      (1<<15)

+#define SYS_CTRL_SET_RST_SPY       (1<<16)

+#define SYS_CTRL_SET_RST_MEM_BRIDGE (1<<17)

+#define SYS_CTRL_SET_RST_EXT_AHB   (1<<18)

+#define SYS_CTRL_SET_RST_DP_AP     (1<<19)

+#define SYS_CTRL_SET_RST_COMREGS   (1<<20)

+#define SYS_CTRL_SET_RST_COMREGS_AP (1<<21)

+#define SYS_CTRL_SET_RST_AP_CLKEN  (1<<22)

+#define SYS_CTRL_SET_RST_AP_RST    (1<<23)

+#define SYS_CTRL_SET_RST_MEM_CHK   (1<<24)

+#define SYS_CTRL_SET_RST_AP_RST1   (1<<25)

+#define SYS_CTRL_SET_RST_AP_RST2   (1<<26)

+#define SYS_CTRL_SET_RST_AP_RST3   (1<<27)

+#define SYS_CTRL_SET_RST_AP_RST4   (1<<28)

+#define SYS_CTRL_SET_RST_AP_RST5   (1<<29)

+#define SYS_CTRL_SET_RST_OUT       (1<<30)

+#define SYS_CTRL_SOFT_RST          (1<<31)

+#define SYS_CTRL_SET_SYS_RST(n)    (((n)&0x3FFFFFFF)<<0)

+#define SYS_CTRL_SET_SYS_RST_MASK  (0x3FFFFFFF<<0)

+#define SYS_CTRL_SET_SYS_RST_SHIFT (0)

+

+//Sys_Rst_Clr

+#define SYS_CTRL_CLR_RST_XCPU      (1<<0)

+#define SYS_CTRL_CLR_RST_SYS_IRQ   (1<<1)

+#define SYS_CTRL_CLR_RST_SYS_A2A   (1<<2)

+#define SYS_CTRL_CLR_RST_SYS_AHB2AXI (1<<3)

+#define SYS_CTRL_CLR_RST_SYS_AXI2AHB (1<<4)

+#define SYS_CTRL_CLR_RST_DMA       (1<<5)

+#define SYS_CTRL_CLR_RST_TIMER     (1<<6)

+#define SYS_CTRL_CLR_RST_TCU       (1<<7)

+#define SYS_CTRL_CLR_RST_GPIO      (1<<8)

+#define SYS_CTRL_CLR_RST_I2C       (1<<9)

+#define SYS_CTRL_CLR_RST_SPI1      (1<<10)

+#define SYS_CTRL_CLR_RST_SPI2      (1<<11)

+#define SYS_CTRL_CLR_RST_RF_SPI    (1<<12)

+#define SYS_CTRL_CLR_RST_SCI1      (1<<13)

+#define SYS_CTRL_CLR_RST_SCI2      (1<<14)

+#define SYS_CTRL_CLR_RST_SCI3      (1<<15)

+#define SYS_CTRL_CLR_RST_SPY       (1<<16)

+#define SYS_CTRL_CLR_RST_MEM_BRIDGE (1<<17)

+#define SYS_CTRL_CLR_RST_EXT_AHB   (1<<18)

+#define SYS_CTRL_CLR_RST_DP_AP     (1<<19)

+#define SYS_CTRL_CLR_RST_COMREGS   (1<<20)

+#define SYS_CTRL_CLR_RST_COMREGS_AP (1<<21)

+#define SYS_CTRL_CLR_RST_AP_CLKEN  (1<<22)

+#define SYS_CTRL_CLR_RST_AP_RST    (1<<23)

+#define SYS_CTRL_CLR_RST_MEM_CHK   (1<<24)

+#define SYS_CTRL_CLR_RST_AP_RST1   (1<<25)

+#define SYS_CTRL_CLR_RST_AP_RST2   (1<<26)

+#define SYS_CTRL_CLR_RST_AP_RST3   (1<<27)

+#define SYS_CTRL_CLR_RST_AP_RST4   (1<<28)

+#define SYS_CTRL_CLR_RST_AP_RST5   (1<<29)

+#define SYS_CTRL_CLR_RST_OUT       (1<<30)

+#define SYS_CTRL_CLR_SYS_RST(n)    (((n)&0x3FFFFFFF)<<0)

+#define SYS_CTRL_CLR_SYS_RST_MASK  (0x3FFFFFFF<<0)

+#define SYS_CTRL_CLR_SYS_RST_SHIFT (0)

+

+//BB_Rst_Set

+#define SYS_CTRL_SET_RST_BCPU      (1<<0)

+#define SYS_CTRL_SET_RST_BB_IRQ    (1<<1)

+#define SYS_CTRL_SET_RST_BB_A2A    (1<<2)

+#define SYS_CTRL_SET_RST_BB_IFC    (1<<3)

+#define SYS_CTRL_SET_RST_BB_SRAM   (1<<4)

+#define SYS_CTRL_SET_RST_ITLV      (1<<5)

+#define SYS_CTRL_SET_RST_VITERBI   (1<<6)

+#define SYS_CTRL_SET_RST_CIPHER    (1<<7)

+#define SYS_CTRL_SET_RST_XCOR      (1<<8)

+#define SYS_CTRL_SET_RST_COPRO     (1<<9)

+#define SYS_CTRL_SET_RST_RF_IF     (1<<10)

+#define SYS_CTRL_SET_RST_EXCOR     (1<<11)

+#define SYS_CTRL_SET_RST_EVITAC    (1<<12)

+#define SYS_CTRL_SET_RST_CORDIC    (1<<13)

+#define SYS_CTRL_SET_RST_TCU_BB    (1<<14)

+#define SYS_CTRL_SET_RST_BB_FULL   (1<<31)

+#define SYS_CTRL_SET_BB_RST(n)     (((n)&0x7FFF)<<0)

+#define SYS_CTRL_SET_BB_RST_MASK   (0x7FFF<<0)

+#define SYS_CTRL_SET_BB_RST_SHIFT  (0)

+

+//BB_Rst_Clr

+#define SYS_CTRL_CLR_RST_BCPU      (1<<0)

+#define SYS_CTRL_CLR_RST_BB_IRQ    (1<<1)

+#define SYS_CTRL_CLR_RST_BB_A2A    (1<<2)

+#define SYS_CTRL_CLR_RST_BB_IFC    (1<<3)

+#define SYS_CTRL_CLR_RST_BB_SRAM   (1<<4)

+#define SYS_CTRL_CLR_RST_ITLV      (1<<5)

+#define SYS_CTRL_CLR_RST_VITERBI   (1<<6)

+#define SYS_CTRL_CLR_RST_CIPHER    (1<<7)

+#define SYS_CTRL_CLR_RST_XCOR      (1<<8)

+#define SYS_CTRL_CLR_RST_COPRO     (1<<9)

+#define SYS_CTRL_CLR_RST_RF_IF     (1<<10)

+#define SYS_CTRL_CLR_RST_EXCOR     (1<<11)

+#define SYS_CTRL_CLR_RST_EVITAC    (1<<12)

+#define SYS_CTRL_CLR_RST_CORDIC    (1<<13)

+#define SYS_CTRL_CLR_RST_TCU_BB    (1<<14)

+#define SYS_CTRL_CLR_RST_BB_FULL   (1<<31)

+#define SYS_CTRL_CLR_BB_RST(n)     (((n)&0x7FFF)<<0)

+#define SYS_CTRL_CLR_BB_RST_MASK   (0x7FFF<<0)

+#define SYS_CTRL_CLR_BB_RST_SHIFT  (0)

+

+//Clk_Sys_Mode

+#define SYS_CTRL_MODE_SYS_XCPU     (1<<0)

+#define SYS_CTRL_MODE_SYS_XCPU_INT_AUTOMATIC (0<<1)

+#define SYS_CTRL_MODE_SYS_XCPU_INT_MANUAL (1<<1)

+#define SYS_CTRL_MODE_SYS_PCLK_CONF_AUTOMATIC (0<<2)

+#define SYS_CTRL_MODE_SYS_PCLK_CONF_MANUAL (1<<2)

+#define SYS_CTRL_MODE_SYS_PCLK_DATA_AUTOMATIC (0<<3)

+#define SYS_CTRL_MODE_SYS_PCLK_DATA_MANUAL (1<<3)

+#define SYS_CTRL_MODE_SYS_AMBA_AUTOMATIC (0<<4)

+#define SYS_CTRL_MODE_SYS_AMBA_MANUAL (1<<4)

+#define SYS_CTRL_MODE_SYS_DMA_AUTOMATIC (0<<5)

+#define SYS_CTRL_MODE_SYS_DMA_MANUAL (1<<5)

+#define SYS_CTRL_MODE_SYS_EBC_AUTOMATIC (0<<6)

+#define SYS_CTRL_MODE_SYS_EBC_MANUAL (1<<6)

+#define SYS_CTRL_MODE_SYS_IFC_CH0_AUTOMATIC (0<<7)

+#define SYS_CTRL_MODE_SYS_IFC_CH0_MANUAL (1<<7)

+#define SYS_CTRL_MODE_SYS_IFC_CH1_AUTOMATIC (0<<8)

+#define SYS_CTRL_MODE_SYS_IFC_CH1_MANUAL (1<<8)

+#define SYS_CTRL_MODE_SYS_IFC_CH2_AUTOMATIC (0<<9)

+#define SYS_CTRL_MODE_SYS_IFC_CH2_MANUAL (1<<9)

+#define SYS_CTRL_MODE_SYS_IFC_CH3_AUTOMATIC (0<<10)

+#define SYS_CTRL_MODE_SYS_IFC_CH3_MANUAL (1<<10)

+#define SYS_CTRL_MODE_SYS_IFC_DBG_AUTOMATIC (0<<11)

+#define SYS_CTRL_MODE_SYS_IFC_DBG_MANUAL (1<<11)

+#define SYS_CTRL_MODE_SYS_A2A_AUTOMATIC (0<<12)

+#define SYS_CTRL_MODE_SYS_A2A_MANUAL (1<<12)

+#define SYS_CTRL_MODE_SYS_AXI2AHB_AUTOMATIC (0<<13)

+#define SYS_CTRL_MODE_SYS_AXI2AHB_MANUAL (1<<13)

+#define SYS_CTRL_MODE_SYS_AHB2AXI_AUTOMATIC (0<<14)

+#define SYS_CTRL_MODE_SYS_AHB2AXI_MANUAL (1<<14)

+#define SYS_CTRL_MODE_SYS_EXT_AHB_AUTOMATIC (0<<15)

+#define SYS_CTRL_MODE_SYS_EXT_AHB_MANUAL (1<<15)

+#define SYS_CTRL_MODE_SYS_DEBUG_UART_AUTOMATIC (0<<16)

+#define SYS_CTRL_MODE_SYS_DEBUG_UART_MANUAL (1<<16)

+#define SYS_CTRL_MODE_SYS_DBGHST_AUTOMATIC (0<<17)

+#define SYS_CTRL_MODE_SYS_DBGHST_MANUAL (1<<17)

+#define SYS_CTRL_MODE_SYSD_SCI1_AUTOMATIC (0<<18)

+#define SYS_CTRL_MODE_SYSD_SCI1_MANUAL (1<<18)

+#define SYS_CTRL_MODE_SYSD_SCI2_AUTOMATIC (0<<19)

+#define SYS_CTRL_MODE_SYSD_SCI2_MANUAL (1<<19)

+#define SYS_CTRL_MODE_SYSD_SCI3_AUTOMATIC (0<<20)

+#define SYS_CTRL_MODE_SYSD_SCI3_MANUAL (1<<20)

+#define SYS_CTRL_MODE_SYSD_RF_SPI_AUTOMATIC (0<<21)

+#define SYS_CTRL_MODE_SYSD_RF_SPI_MANUAL (1<<21)

+#define SYS_CTRL_MODE_SYSD_OSC_AUTOMATIC (0<<22)

+#define SYS_CTRL_MODE_SYSD_OSC_MANUAL (1<<22)

+#define SYS_CTRL_MODE_CLK_SYS(n)   (((n)&0x3FFFFF)<<1)

+#define SYS_CTRL_MODE_CLK_SYS_MASK (0x3FFFFF<<1)

+#define SYS_CTRL_MODE_CLK_SYS_SHIFT (1)

+

+//Clk_Sys_Enable

+#define SYS_CTRL_ENABLE_SYS_XCPU   (1<<0)

+#define SYS_CTRL_ENABLE_SYS_XCPU_INT (1<<1)

+#define SYS_CTRL_ENABLE_SYS_PCLK_CONF (1<<2)

+#define SYS_CTRL_ENABLE_SYS_PCLK_DATA (1<<3)

+#define SYS_CTRL_ENABLE_SYS_AMBA   (1<<4)

+#define SYS_CTRL_ENABLE_SYS_DMA    (1<<5)

+#define SYS_CTRL_ENABLE_SYS_EBC    (1<<6)

+#define SYS_CTRL_ENABLE_SYS_IFC_CH0 (1<<7)

+#define SYS_CTRL_ENABLE_SYS_IFC_CH1 (1<<8)

+#define SYS_CTRL_ENABLE_SYS_IFC_CH2 (1<<9)

+#define SYS_CTRL_ENABLE_SYS_IFC_CH3 (1<<10)

+#define SYS_CTRL_ENABLE_SYS_IFC_DBG (1<<11)

+#define SYS_CTRL_ENABLE_SYS_A2A    (1<<12)

+#define SYS_CTRL_ENABLE_SYS_AXI2AHB (1<<13)

+#define SYS_CTRL_ENABLE_SYS_AHB2AXI (1<<14)

+#define SYS_CTRL_ENABLE_SYS_EXT_AHB (1<<15)

+#define SYS_CTRL_ENABLE_SYS_DEBUG_UART (1<<16)

+#define SYS_CTRL_ENABLE_SYS_DBGHST (1<<17)

+#define SYS_CTRL_ENABLE_SYSD_SCI1  (1<<18)

+#define SYS_CTRL_ENABLE_SYSD_SCI2  (1<<19)

+#define SYS_CTRL_ENABLE_SYSD_SCI3  (1<<20)

+#define SYS_CTRL_ENABLE_SYSD_RF_SPI (1<<21)

+#define SYS_CTRL_ENABLE_SYSD_OSC   (1<<22)

+#define SYS_CTRL_ENABLE_SYS_GPIO   (1<<23)

+#define SYS_CTRL_ENABLE_SYS_IRQ    (1<<24)

+#define SYS_CTRL_ENABLE_SYS_TCU    (1<<25)

+#define SYS_CTRL_ENABLE_SYS_TIMER  (1<<26)

+#define SYS_CTRL_ENABLE_SYS_COM_REGS (1<<27)

+#define SYS_CTRL_ENABLE_SYS_DP_AP  (1<<28)

+#define SYS_CTRL_ENABLE_CLK_SYS(n) (((n)&0x1FFFFFFF)<<0)

+#define SYS_CTRL_ENABLE_CLK_SYS_MASK (0x1FFFFFFF<<0)

+#define SYS_CTRL_ENABLE_CLK_SYS_SHIFT (0)

+

+//Clk_Sys_Disable

+#define SYS_CTRL_DISABLE_SYS_XCPU  (1<<0)

+#define SYS_CTRL_DISABLE_SYS_XCPU_INT (1<<1)

+#define SYS_CTRL_DISABLE_SYS_PCLK_CONF (1<<2)

+#define SYS_CTRL_DISABLE_SYS_PCLK_DATA (1<<3)

+#define SYS_CTRL_DISABLE_SYS_AMBA  (1<<4)

+#define SYS_CTRL_DISABLE_SYS_DMA   (1<<5)

+#define SYS_CTRL_DISABLE_SYS_EBC   (1<<6)

+#define SYS_CTRL_DISABLE_SYS_IFC_CH0 (1<<7)

+#define SYS_CTRL_DISABLE_SYS_IFC_CH1 (1<<8)

+#define SYS_CTRL_DISABLE_SYS_IFC_CH2 (1<<9)

+#define SYS_CTRL_DISABLE_SYS_IFC_CH3 (1<<10)

+#define SYS_CTRL_DISABLE_SYS_IFC_DBG (1<<11)

+#define SYS_CTRL_DISABLE_SYS_A2A   (1<<12)

+#define SYS_CTRL_DISABLE_SYS_AXI2AHB (1<<13)

+#define SYS_CTRL_DISABLE_SYS_AHB2AXI (1<<14)

+#define SYS_CTRL_DISABLE_SYS_EXT_AHB (1<<15)

+#define SYS_CTRL_DISABLE_SYS_DEBUG_UART (1<<16)

+#define SYS_CTRL_DISABLE_SYS_DBGHST (1<<17)

+#define SYS_CTRL_DISABLE_SYSD_SCI1 (1<<18)

+#define SYS_CTRL_DISABLE_SYSD_SCI2 (1<<19)

+#define SYS_CTRL_DISABLE_SYSD_SCI3 (1<<20)

+#define SYS_CTRL_DISABLE_SYSD_RF_SPI (1<<21)

+#define SYS_CTRL_DISABLE_SYSD_OSC  (1<<22)

+#define SYS_CTRL_DISABLE_SYS_GPIO  (1<<23)

+#define SYS_CTRL_DISABLE_SYS_IRQ   (1<<24)

+#define SYS_CTRL_DISABLE_SYS_TCU   (1<<25)

+#define SYS_CTRL_DISABLE_SYS_TIMER (1<<26)

+#define SYS_CTRL_DISABLE_SYS_COM_REGS (1<<27)

+#define SYS_CTRL_DISABLE_SYS_DP_AP (1<<28)

+#define SYS_CTRL_DISABLE_CLK_SYS(n) (((n)&0x1FFFFFFF)<<0)

+#define SYS_CTRL_DISABLE_CLK_SYS_MASK (0x1FFFFFFF<<0)

+#define SYS_CTRL_DISABLE_CLK_SYS_SHIFT (0)

+

+//Clk_Per_Mode

+#define SYS_CTRL_MODE_PER_I2C_AUTOMATIC (0<<0)

+#define SYS_CTRL_MODE_PER_I2C_MANUAL (1<<0)

+#define SYS_CTRL_MODE_PERD_SPI1_AUTOMATIC (0<<1)

+#define SYS_CTRL_MODE_PERD_SPI1_MANUAL (1<<1)

+#define SYS_CTRL_MODE_PERD_SPI2_AUTOMATIC (0<<2)

+#define SYS_CTRL_MODE_PERD_SPI2_MANUAL (1<<2)

+#define SYS_CTRL_MODE_CLK_PER(n)   (((n)&7)<<0)

+#define SYS_CTRL_MODE_CLK_PER_MASK (7<<0)

+#define SYS_CTRL_MODE_CLK_PER_SHIFT (0)

+

+//Clk_Per_Enable

+#define SYS_CTRL_ENABLE_PER_I2C    (1<<0)

+#define SYS_CTRL_ENABLE_PERD_SPI1  (1<<1)

+#define SYS_CTRL_ENABLE_PERD_SPI2  (1<<2)

+#define SYS_CTRL_ENABLE_PER_SPY    (1<<3)

+#define SYS_CTRL_ENABLE_PER_TEST   (1<<4)

+#define SYS_CTRL_ENABLE_CLK_PER(n) (((n)&31)<<0)

+#define SYS_CTRL_ENABLE_CLK_PER_MASK (31<<0)

+#define SYS_CTRL_ENABLE_CLK_PER_SHIFT (0)

+

+//Clk_Per_Disable

+#define SYS_CTRL_DISABLE_PER_I2C   (1<<0)

+#define SYS_CTRL_DISABLE_PERD_SPI1 (1<<1)

+#define SYS_CTRL_DISABLE_PERD_SPI2 (1<<2)

+#define SYS_CTRL_DISABLE_PER_SPY   (1<<3)

+#define SYS_CTRL_DISABLE_PER_TEST  (1<<4)

+#define SYS_CTRL_DISABLE_CLK_PER(n) (((n)&31)<<0)

+#define SYS_CTRL_DISABLE_CLK_PER_MASK (31<<0)

+#define SYS_CTRL_DISABLE_CLK_PER_SHIFT (0)

+

+//Clk_BB_Mode

+#define SYS_CTRL_MODE_BB_BCPU      (1<<0)

+#define SYS_CTRL_MODE_BB_BCPU_INT_AUTOMATIC (0<<1)

+#define SYS_CTRL_MODE_BB_BCPU_INT_MANUAL (1<<1)

+#define SYS_CTRL_MODE_BB_AMBA_AUTOMATIC (0<<2)

+#define SYS_CTRL_MODE_BB_AMBA_MANUAL (1<<2)

+#define SYS_CTRL_MODE_BB_PCLK_CONF_AUTOMATIC (0<<3)

+#define SYS_CTRL_MODE_BB_PCLK_CONF_MANUAL (1<<3)

+#define SYS_CTRL_MODE_BB_PCLK_DATA_AUTOMATIC (0<<4)

+#define SYS_CTRL_MODE_BB_PCLK_DATA_MANUAL (1<<4)

+#define SYS_CTRL_MODE_BB_EXCOR_AUTOMATIC (0<<5)

+#define SYS_CTRL_MODE_BB_EXCOR_MANUAL (1<<5)

+#define SYS_CTRL_MODE_BB_IFC_CH2_AUTOMATIC (0<<6)

+#define SYS_CTRL_MODE_BB_IFC_CH2_MANUAL (1<<6)

+#define SYS_CTRL_MODE_BB_IFC_CH3_AUTOMATIC (0<<7)

+#define SYS_CTRL_MODE_BB_IFC_CH3_MANUAL (1<<7)

+#define SYS_CTRL_MODE_BB_SRAM_AUTOMATIC (0<<8)

+#define SYS_CTRL_MODE_BB_SRAM_MANUAL (1<<8)

+#define SYS_CTRL_MODE_BB_A2A_AUTOMATIC (0<<9)

+#define SYS_CTRL_MODE_BB_A2A_MANUAL (1<<9)

+#define SYS_CTRL_MODE_BB_ITLV_AUTOMATIC (0<<10)

+#define SYS_CTRL_MODE_BB_ITLV_MANUAL (1<<10)

+#define SYS_CTRL_MODE_BB_VITERBI_AUTOMATIC (0<<11)

+#define SYS_CTRL_MODE_BB_VITERBI_MANUAL (1<<11)

+#define SYS_CTRL_MODE_BB_CIPHER_AUTOMATIC (0<<12)

+#define SYS_CTRL_MODE_BB_CIPHER_MANUAL (1<<12)

+#define SYS_CTRL_MODE_BB_RF_IF_AUTOMATIC (0<<13)

+#define SYS_CTRL_MODE_BB_RF_IF_MANUAL (1<<13)

+#define SYS_CTRL_MODE_BB_COPRO_AUTOMATIC (0<<14)

+#define SYS_CTRL_MODE_BB_COPRO_MANUAL (1<<14)

+#define SYS_CTRL_MODE_BB_CP2_REG_AUTOMATIC (0<<15)

+#define SYS_CTRL_MODE_BB_CP2_REG_MANUAL (1<<15)

+#define SYS_CTRL_MODE_BB_XCOR_AUTOMATIC (0<<16)

+#define SYS_CTRL_MODE_BB_XCOR_MANUAL (1<<16)

+#define SYS_CTRL_MODE_BB_EVITAC_AUTOMATIC (0<<17)

+#define SYS_CTRL_MODE_BB_EVITAC_MANUAL (1<<17)

+#define SYS_CTRL_MODE_CLK_BB(n)    (((n)&0x1FFFF)<<1)

+#define SYS_CTRL_MODE_CLK_BB_MASK  (0x1FFFF<<1)

+#define SYS_CTRL_MODE_CLK_BB_SHIFT (1)

+

+//Clk_BB_Enable

+#define SYS_CTRL_ENABLE_BB_BCPU    (1<<0)

+#define SYS_CTRL_ENABLE_BB_BCPU_INT (1<<1)

+#define SYS_CTRL_ENABLE_BB_AMBA    (1<<2)

+#define SYS_CTRL_ENABLE_BB_PCLK_CONF (1<<3)

+#define SYS_CTRL_ENABLE_BB_PCLK_DATA (1<<4)

+#define SYS_CTRL_ENABLE_BB_EXCOR   (1<<5)

+#define SYS_CTRL_ENABLE_BB_IFC_CH2 (1<<6)

+#define SYS_CTRL_ENABLE_BB_IFC_CH3 (1<<7)

+#define SYS_CTRL_ENABLE_BB_SRAM    (1<<8)

+#define SYS_CTRL_ENABLE_BB_A2A     (1<<9)

+#define SYS_CTRL_ENABLE_BB_ITLV    (1<<10)

+#define SYS_CTRL_ENABLE_BB_VITERBI (1<<11)

+#define SYS_CTRL_ENABLE_BB_CIPHER  (1<<12)

+#define SYS_CTRL_ENABLE_BB_RF_IF   (1<<13)

+#define SYS_CTRL_ENABLE_BB_COPRO   (1<<14)

+#define SYS_CTRL_ENABLE_BB_CP2_REG (1<<15)

+#define SYS_CTRL_ENABLE_BB_XCOR    (1<<16)

+#define SYS_CTRL_ENABLE_BB_EVITAC  (1<<17)

+#define SYS_CTRL_ENABLE_BB_IRQ     (1<<18)

+#define SYS_CTRL_ENABLE_BB_COM_REGS (1<<19)

+#define SYS_CTRL_ENABLE_BB_CORDIC  (1<<20)

+#define SYS_CTRL_ENABLE_CLK_BB(n)  (((n)&0x1FFFFF)<<0)

+#define SYS_CTRL_ENABLE_CLK_BB_MASK (0x1FFFFF<<0)

+#define SYS_CTRL_ENABLE_CLK_BB_SHIFT (0)

+

+//Clk_BB_Disable

+#define SYS_CTRL_DISABLE_BB_BCPU   (1<<0)

+#define SYS_CTRL_DISABLE_BB_BCPU_INT (1<<1)

+#define SYS_CTRL_DISABLE_BB_AMBA   (1<<2)

+#define SYS_CTRL_DISABLE_BB_PCLK_CONF (1<<3)

+#define SYS_CTRL_DISABLE_BB_PCLK_DATA (1<<4)

+#define SYS_CTRL_DISABLE_BB_EXCOR  (1<<5)

+#define SYS_CTRL_DISABLE_BB_IFC_CH2 (1<<6)

+#define SYS_CTRL_DISABLE_BB_IFC_CH3 (1<<7)

+#define SYS_CTRL_DISABLE_BB_SRAM   (1<<8)

+#define SYS_CTRL_DISABLE_BB_A2A    (1<<9)

+#define SYS_CTRL_DISABLE_BB_ITLV   (1<<10)

+#define SYS_CTRL_DISABLE_BB_VITERBI (1<<11)

+#define SYS_CTRL_DISABLE_BB_CIPHER (1<<12)

+#define SYS_CTRL_DISABLE_BB_RF_IF  (1<<13)

+#define SYS_CTRL_DISABLE_BB_COPRO  (1<<14)

+#define SYS_CTRL_DISABLE_BB_CP2_REG (1<<15)

+#define SYS_CTRL_DISABLE_BB_XCOR   (1<<16)

+#define SYS_CTRL_DISABLE_BB_EVITAC (1<<17)

+#define SYS_CTRL_DISABLE_BB_IRQ    (1<<18)

+#define SYS_CTRL_DISABLE_BB_COM_REGS (1<<19)

+#define SYS_CTRL_DISABLE_BB_CORDIC (1<<20)

+#define SYS_CTRL_DISABLE_CLK_BB(n) (((n)&0x1FFFFF)<<0)

+#define SYS_CTRL_DISABLE_CLK_BB_MASK (0x1FFFFF<<0)

+#define SYS_CTRL_DISABLE_CLK_BB_SHIFT (0)

+

+//Clk_Other_Mode

+#define SYS_CTRL_MODE_OC_DEBUG_UART_AUTOMATIC (0<<0)

+#define SYS_CTRL_MODE_OC_DEBUG_UART_MANUAL (1<<0)

+#define SYS_CTRL_MODE_OC_RF_RX_AUTOMATIC (0<<1)

+#define SYS_CTRL_MODE_OC_RF_RX_MANUAL (1<<1)

+#define SYS_CTRL_MODE_OC_RF_TX_AUTOMATIC (0<<2)

+#define SYS_CTRL_MODE_OC_RF_TX_MANUAL (1<<2)

+#define SYS_CTRL_MODE_OC_MEM_BRIDGE_AUTOMATIC (0<<3)

+#define SYS_CTRL_MODE_OC_MEM_BRIDGE_MANUAL (1<<3)

+#define SYS_CTRL_MODE_CLK_OTHER(n) (((n)&15)<<0)

+#define SYS_CTRL_MODE_CLK_OTHER_MASK (15<<0)

+#define SYS_CTRL_MODE_CLK_OTHER_SHIFT (0)

+

+//Clk_Other_Enable

+#define SYS_CTRL_ENABLE_OC_DEBUG_UART (1<<0)

+#define SYS_CTRL_ENABLE_OC_RF_RX   (1<<1)

+#define SYS_CTRL_ENABLE_OC_RF_TX   (1<<2)

+#define SYS_CTRL_ENABLE_OC_MEM_BRIDGE (1<<3)

+#define SYS_CTRL_ENABLE_OC_LPS     (1<<4)

+#define SYS_CTRL_ENABLE_OC_GPIO    (1<<5)

+#define SYS_CTRL_ENABLE_OC_CLK_OUT (1<<6)

+#define SYS_CTRL_ENABLE_OC_MEM_CLK_OUT (1<<7)

+#define SYS_CTRL_ENABLE_OC_TCU     (1<<8)

+#define SYS_CTRL_ENABLE_CLK_OTHER(n) (((n)&0x1FF)<<0)

+#define SYS_CTRL_ENABLE_CLK_OTHER_MASK (0x1FF<<0)

+#define SYS_CTRL_ENABLE_CLK_OTHER_SHIFT (0)

+

+//Clk_Other_Disable

+#define SYS_CTRL_DISABLE_OC_DEBUG_UART (1<<0)

+#define SYS_CTRL_DISABLE_OC_RF_RX  (1<<1)

+#define SYS_CTRL_DISABLE_OC_RF_TX  (1<<2)

+#define SYS_CTRL_DISABLE_OC_MEM_BRIDGE (1<<3)

+#define SYS_CTRL_DISABLE_OC_LPS    (1<<4)

+#define SYS_CTRL_DISABLE_OC_GPIO   (1<<5)

+#define SYS_CTRL_DISABLE_OC_CLK_OUT (1<<6)

+#define SYS_CTRL_DISABLE_OC_MEM_CLK_OUT (1<<7)

+#define SYS_CTRL_DISABLE_OC_TCU    (1<<8)

+#define SYS_CTRL_DISABLE_CLK_OTHER(n) (((n)&0x1FF)<<0)

+#define SYS_CTRL_DISABLE_CLK_OTHER_MASK (0x1FF<<0)

+#define SYS_CTRL_DISABLE_CLK_OTHER_SHIFT (0)

+

+//Pll_Ctrl

+#define SYS_CTRL_PLL_ENABLE        (1<<0)

+#define SYS_CTRL_PLL_ENABLE_MASK   (1<<0)

+#define SYS_CTRL_PLL_ENABLE_SHIFT  (0)

+#define SYS_CTRL_PLL_ENABLE_POWER_DOWN (0<<0)

+#define SYS_CTRL_PLL_ENABLE_ENABLE (1<<0)

+#define SYS_CTRL_PLL_LOCK_RESET    (1<<4)

+#define SYS_CTRL_PLL_LOCK_RESET_MASK (1<<4)

+#define SYS_CTRL_PLL_LOCK_RESET_SHIFT (4)

+#define SYS_CTRL_PLL_LOCK_RESET_RESET (0<<4)

+#define SYS_CTRL_PLL_LOCK_RESET_NO_RESET (1<<4)

+#define SYS_CTRL_PLL_BYPASS        (1<<8)

+#define SYS_CTRL_PLL_BYPASS_MASK   (1<<8)

+#define SYS_CTRL_PLL_BYPASS_SHIFT  (8)

+#define SYS_CTRL_PLL_BYPASS_PASS   (0<<8)

+#define SYS_CTRL_PLL_BYPASS_BYPASS (1<<8)

+#define SYS_CTRL_PLL_CLK_FAST_ENABLE (1<<12)

+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_MASK (1<<12)

+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_SHIFT (12)

+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_ENABLE (1<<12)

+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_DISABLE (0<<12)

+#define SYS_CTRL_PLL_XP_CFG(n)     (((n)&4369)<<0)

+#define SYS_CTRL_PLL_XP_CFG_MASK   (4369<<0)

+#define SYS_CTRL_PLL_XP_CFG_SHIFT  (0)

+

+//Sel_Clock

+#define SYS_CTRL_SLOW_SEL_RF_OSCILLATOR (1<<0)

+#define SYS_CTRL_SLOW_SEL_RF_RF    (0<<0)

+#define SYS_CTRL_SYS_SEL_FAST_SLOW (1<<4)

+#define SYS_CTRL_SYS_SEL_FAST_FAST (0<<4)

+#define SYS_CTRL_TCU_13M_L_26M     (1<<5)

+#define SYS_CTRL_TCU_13M_L_13M     (0<<5)

+#define SYS_CTRL_PLL_DISABLE_LPS_DISABLE (1<<6)

+#define SYS_CTRL_PLL_DISABLE_LPS_ENABLE (0<<6)

+#define SYS_CTRL_DIGEN_H_ENABLE    (1<<7)

+#define SYS_CTRL_DIGEN_H_DISABLE   (0<<7)

+#define SYS_CTRL_RF_DETECTED_OK    (1<<20)

+#define SYS_CTRL_RF_DETECTED_NO    (0<<20)

+#define SYS_CTRL_RF_DETECT_BYPASS  (1<<21)

+#define SYS_CTRL_RF_DETECT_RESET   (1<<22)

+#define SYS_CTRL_RF_SELECTED_L     (1<<23)

+#define SYS_CTRL_PLL_LOCKED        (1<<24)

+#define SYS_CTRL_PLL_LOCKED_MASK   (1<<24)

+#define SYS_CTRL_PLL_LOCKED_SHIFT  (24)

+#define SYS_CTRL_PLL_LOCKED_LOCKED (1<<24)

+#define SYS_CTRL_PLL_LOCKED_NOT_LOCKED (0<<24)

+#define SYS_CTRL_PLL_BYPASS_LOCK   (1<<27)

+#define SYS_CTRL_FAST_SELECTED_L   (1<<31)

+#define SYS_CTRL_FAST_SELECTED_L_MASK (1<<31)

+#define SYS_CTRL_FAST_SELECTED_L_SHIFT (31)

+

+//Cfg_Clk_Sys

+#define SYS_CTRL_FREQ(n)           (((n)&15)<<0)

+#define SYS_CTRL_FREQ_MASK         (15<<0)

+#define SYS_CTRL_FREQ_SHIFT        (0)

+#define SYS_CTRL_FREQ_312M         (13<<0)

+#define SYS_CTRL_FREQ_250M         (12<<0)

+#define SYS_CTRL_FREQ_208M         (11<<0)

+#define SYS_CTRL_FREQ_178M         (10<<0)

+#define SYS_CTRL_FREQ_156M         (9<<0)

+#define SYS_CTRL_FREQ_139M         (8<<0)

+#define SYS_CTRL_FREQ_125M         (7<<0)

+#define SYS_CTRL_FREQ_113M         (6<<0)

+#define SYS_CTRL_FREQ_104M         (5<<0)

+#define SYS_CTRL_FREQ_89M          (4<<0)

+#define SYS_CTRL_FREQ_78M          (3<<0)

+#define SYS_CTRL_FREQ_52M          (2<<0)

+#define SYS_CTRL_FREQ_39M          (1<<0)

+#define SYS_CTRL_FREQ_26M          (0<<0)

+#define SYS_CTRL_FORCE_DIV_UPDATE  (1<<4)

+#define SYS_CTRL_REQ_DIV_UPDATE    (1<<8)

+

+//Cfg_Clk_Mem_Bridge

+#define SYS_CTRL_MEM_FREQ(n)       (((n)&15)<<0)

+#define SYS_CTRL_MEM_FREQ_MASK     (15<<0)

+#define SYS_CTRL_MEM_FREQ_SHIFT    (0)

+#define SYS_CTRL_MEM_FREQ_312M     (13<<0)

+#define SYS_CTRL_MEM_FREQ_250M     (12<<0)

+#define SYS_CTRL_MEM_FREQ_208M     (11<<0)

+#define SYS_CTRL_MEM_FREQ_178M     (10<<0)

+#define SYS_CTRL_MEM_FREQ_156M     (9<<0)

+#define SYS_CTRL_MEM_FREQ_139M     (8<<0)

+#define SYS_CTRL_MEM_FREQ_125M     (7<<0)

+#define SYS_CTRL_MEM_FREQ_113M     (6<<0)

+#define SYS_CTRL_MEM_FREQ_104M     (5<<0)

+#define SYS_CTRL_MEM_FREQ_89M      (4<<0)

+#define SYS_CTRL_MEM_FREQ_78M      (3<<0)

+#define SYS_CTRL_MEM_FREQ_52M      (2<<0)

+#define SYS_CTRL_MEM_FREQ_39M      (1<<0)

+#define SYS_CTRL_MEM_FREQ_26M      (0<<0)

+#define SYS_CTRL_DDR_MODE_EN_NORMAL_MODE (0<<4)

+#define SYS_CTRL_DDR_MODE_EN_DDR_MODE (1<<4)

+#define SYS_CTRL_DDR_FAST_CLK_POL_INVERT (1<<5)

+#define SYS_CTRL_DDR_FAST_CLK_POL_NORMAL (0<<5)

+#define SYS_CTRL_DDR_DQSL_O(n)     (((n)&31)<<6)

+#define SYS_CTRL_DDR_DQSU_O(n)     (((n)&31)<<11)

+#define SYS_CTRL_DDR_DQS_OEN(n)    (((n)&31)<<16)

+#define SYS_CTRL_DDR_DQSL_I(n)     (((n)&31)<<21)

+#define SYS_CTRL_DDR_DQSU_I(n)     (((n)&31)<<26)

+#define SYS_CTRL_MEM_REQ_DIV_UPDATE (1<<31)

+

+//Cfg_Clk_Out

+#define SYS_CTRL_CLKOUT_DIVIDER(n) (((n)&31)<<0)

+#define SYS_CTRL_CLKOUT_SEL_OSC    (0<<8)

+#define SYS_CTRL_CLKOUT_SEL_RF     (1<<8)

+#define SYS_CTRL_CLKOUT_SEL_DIVIDER (2<<8)

+

+//Cfg_Clk_Host_Uart

+#define SYS_CTRL_HOST_UART_DIVIDER(n) (((n)&0x3FF)<<0)

+#define SYS_CTRL_HOST_UART_DIVIDER_MASK (0x3FF<<0)

+#define SYS_CTRL_HOST_UART_DIVIDER_SHIFT (0)

+#define SYS_CTRL_HOST_UART_SEL_PLL_SLOW (0<<12)

+#define SYS_CTRL_HOST_UART_SEL_PLL_PLL (1<<12)

+

+//Cfg_Clk_Auxclk

+#define SYS_CTRL_AUXCLK_EN_DISABLE (0<<0)

+#define SYS_CTRL_AUXCLK_EN_ENABLE  (1<<0)

+

+//Cfg_AHB

+#define SYS_CTRL_SYS_NEW_ARBITRATION_ENABLE (1<<0)

+#define SYS_CTRL_SYS_NEW_ARBITRATION_DISABLE (0<<0)

+#define SYS_CTRL_ENABLE_SYS_MID_BIST_ENABLE (1<<1)

+#define SYS_CTRL_ENABLE_SYS_MID_BIST_DISABLE (0<<1)

+#define SYS_CTRL_ENABLE_SYS_MID_DMA_ENABLE (1<<2)

+#define SYS_CTRL_ENABLE_SYS_MID_DMA_DISABLE (0<<2)

+#define SYS_CTRL_ENABLE_SYS_MID_XCPU_ENABLE (1<<3)

+#define SYS_CTRL_ENABLE_SYS_MID_XCPU_DISABLE (0<<3)

+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_ENABLE (1<<4)

+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_DISABLE (0<<4)

+#define SYS_CTRL_ENABLE_SYS_MID_IFC_ENABLE (1<<5)

+#define SYS_CTRL_ENABLE_SYS_MID_IFC_DISABLE (0<<5)

+#define SYS_CTRL_ENABLE_SYS_MID_AXI2AHB_ENABLE (1<<6)

+#define SYS_CTRL_ENABLE_SYS_MID_AXI2AHB_DISABLE (0<<6)

+#define SYS_CTRL_BB_NEW_ARBITRATION_ENABLE (1<<16)

+#define SYS_CTRL_BB_NEW_ARBITRATION_DISABLE (0<<16)

+#define SYS_CTRL_ENABLE_BB_MID_BIST_ENABLE (1<<17)

+#define SYS_CTRL_ENABLE_BB_MID_BIST_DISABLE (0<<17)

+#define SYS_CTRL_ENABLE_BB_MID_IFC_ENABLE (1<<18)

+#define SYS_CTRL_ENABLE_BB_MID_IFC_DISABLE (0<<18)

+#define SYS_CTRL_ENABLE_BB_MID_BCPU_ENABLE (1<<19)

+#define SYS_CTRL_ENABLE_BB_MID_BCPU_DISABLE (0<<19)

+#define SYS_CTRL_ENABLE_BB_MID_AHB2AHB_ENABLE (1<<20)

+#define SYS_CTRL_ENABLE_BB_MID_AHB2AHB_DISABLE (0<<20)

+#define SYS_CTRL_SYS_ENABLE(n)     (((n)&0x3F)<<1)

+#define SYS_CTRL_SYS_ENABLE_MASK   (0x3F<<1)

+#define SYS_CTRL_SYS_ENABLE_SHIFT  (1)

+#define SYS_CTRL_BB_ENABLE(n)      (((n)&15)<<17)

+#define SYS_CTRL_BB_ENABLE_MASK    (15<<17)

+#define SYS_CTRL_BB_ENABLE_SHIFT   (17)

+

+//Ctrl_AHB

+#define SYS_CTRL_SPLIT_SYS_MID_BIST_NORMAL (1<<0)

+#define SYS_CTRL_SPLIT_SYS_MID_BIST_FORCE (0<<0)

+#define SYS_CTRL_SPLIT_SYS_MID_DMA_NORMAL (1<<1)

+#define SYS_CTRL_SPLIT_SYS_MID_DMA_FORCE (0<<1)

+#define SYS_CTRL_SPLIT_SYS_MID_XCPU_NORMAL (1<<2)

+#define SYS_CTRL_SPLIT_SYS_MID_XCPU_FORCE (0<<2)

+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_NORMAL (1<<3)

+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_FORCE (0<<3)

+#define SYS_CTRL_SPLIT_SYS_MID_IFC_NORMAL (1<<4)

+#define SYS_CTRL_SPLIT_SYS_MID_IFC_FORCE (0<<4)

+#define SYS_CTRL_SPLIT_SYS_MID_AXI2AHB_NORMAL (1<<5)

+#define SYS_CTRL_SPLIT_SYS_MID_AXI2AHB_FORCE (0<<5)

+#define SYS_CTRL_SPLIT_BB_MID_BIST_NORMAL (1<<16)

+#define SYS_CTRL_SPLIT_BB_MID_BIST_FORCE (0<<16)

+#define SYS_CTRL_SPLIT_BB_MID_IFC_NORMAL (1<<17)

+#define SYS_CTRL_SPLIT_BB_MID_IFC_FORCE (0<<17)

+#define SYS_CTRL_SPLIT_BB_MID_BCPU_NORMAL (1<<18)

+#define SYS_CTRL_SPLIT_BB_MID_BCPU_FORCE (0<<18)

+#define SYS_CTRL_SPLIT_BB_MID_AHB2AHB_NORMAL (1<<19)

+#define SYS_CTRL_SPLIT_BB_MID_AHB2AHB_FORCE (0<<19)

+#define SYS_CTRL_SYS_FORCE_HSPLIT(n) (((n)&0x3F)<<0)

+#define SYS_CTRL_SYS_FORCE_HSPLIT_MASK (0x3F<<0)

+#define SYS_CTRL_SYS_FORCE_HSPLIT_SHIFT (0)

+#define SYS_CTRL_BB_FORCE_HSPLIT(n) (((n)&15)<<16)

+#define SYS_CTRL_BB_FORCE_HSPLIT_MASK (15<<16)

+#define SYS_CTRL_BB_FORCE_HSPLIT_SHIFT (16)

+

+//XCpu_Dbg_BKP

+#define SYS_CTRL_BKPT_EN           (1<<0)

+#define SYS_CTRL_BKPT_MODE(n)      (((n)&3)<<4)

+#define SYS_CTRL_BKPT_MODE_I       (0<<4)

+#define SYS_CTRL_BKPT_MODE_R       (1<<4)

+#define SYS_CTRL_BKPT_MODE_W       (2<<4)

+#define SYS_CTRL_BKPT_MODE_RW      (3<<4)

+#define SYS_CTRL_STALLED           (1<<8)

+

+//XCpu_Dbg_Addr

+#define SYS_CTRL_BREAKPOINT_ADDRESS(n) (((n)&0x3FFFFFF)<<0)

+

+//BCpu_Dbg_BKP

+//#define SYS_CTRL_BKPT_EN         (1<<0)

+//#define SYS_CTRL_BKPT_MODE(n)    (((n)&3)<<4)

+//#define SYS_CTRL_BKPT_MODE_I     (0<<4)

+//#define SYS_CTRL_BKPT_MODE_R     (1<<4)

+//#define SYS_CTRL_BKPT_MODE_W     (2<<4)

+//#define SYS_CTRL_BKPT_MODE_RW    (3<<4)

+//#define SYS_CTRL_STALLED         (1<<8)

+

+//BCpu_Dbg_Addr

+//#define SYS_CTRL_BREAKPOINT_ADDRESS(n) (((n)&0x3FFFFFF)<<0)

+

+//Cfg_Cpus_Cache_Ram_Disable

+#define SYS_CTRL_XCPU_USE_MODE     (1<<0)

+#define SYS_CTRL_XCPU_CLK_OFF_MODE (1<<1)

+#define SYS_CTRL_BCPU_USE_MODE     (1<<16)

+#define SYS_CTRL_BCPU_CLK_OFF_MODE (1<<17)

+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE(n) (((n)&3)<<0)

+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE_MASK (3<<0)

+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE_SHIFT (0)

+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE(n) (((n)&3)<<16)

+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE_MASK (3<<16)

+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE_SHIFT (16)

+

+//Reset_Cause

+#define SYS_CTRL_WATCHDOG_RESET_HAPPENED (1<<0)

+#define SYS_CTRL_WATCHDOG_RESET_NO (0<<0)

+#define SYS_CTRL_APSOFT_RESET_HAPPENED (1<<1)

+#define SYS_CTRL_APSOFT_RESET_NO   (0<<1)

+#define SYS_CTRL_GLOBALSOFT_RESET_HAPPENED (1<<4)

+#define SYS_CTRL_GLOBALSOFT_RESET_NO (0<<4)

+#define SYS_CTRL_HOSTDEBUG_RESET_HAPPENED (1<<5)

+#define SYS_CTRL_HOSTDEBUG_RESET_NO (0<<5)

+#define SYS_CTRL_ALARMCAUSE_HAPPENED (1<<6)

+#define SYS_CTRL_ALARMCAUSE_NO     (0<<6)

+#define SYS_CTRL_MEMCHECKDONE_MASK (1<<7)

+#define SYS_CTRL_MEMCHECKDONE_SHIFT (7)

+#define SYS_CTRL_MEMCHECKDONE_DONE (1<<7)

+#define SYS_CTRL_MEMCHECKDONE_RUNNING (0<<7)

+#define SYS_CTRL_BOOT_MODE(n)      (((n)&0xFFFF)<<8)

+#define SYS_CTRL_BOOT_MODE_MASK    (0xFFFF<<8)

+#define SYS_CTRL_BOOT_MODE_SHIFT   (8)

+#define SYS_CTRL_SW_BOOT_MODE(n)   (((n)&0x7F)<<24)

+#define SYS_CTRL_SW_BOOT_MODE_MASK (0x7F<<24)

+#define SYS_CTRL_SW_BOOT_MODE_SHIFT (24)

+#define SYS_CTRL_FONCTIONAL_TEST_MODE (1<<31)

+

+//WakeUp

+#define SYS_CTRL_FORCE_WAKEUP      (1<<0)

+

+//AP_Ctrl

+#define SYS_CTRL_AP_INT_STATUS     (1<<0)

+#define SYS_CTRL_AP_INT_MASK       (1<<16)

+#define SYS_CTRL_AP_DEEPSLEEP_EN   (1<<24)

+

+//Ignore_Charger

+#define SYS_CTRL_IGNORE_CHARGER    (1<<0)

+

+//Cfg_Reserve

+#define SYS_CTRL_RESERVE_L(n)      (((n)&0x3FFF)<<0)

+#define SYS_CTRL_AUIFC_CH0_IRQ_MASK (1<<14)

+#define SYS_CTRL_AUIFC_CH1_IRQ_MASK (1<<15)

+#define SYS_CTRL_RESERVE_H(n)      (((n)&0xFFFF)<<16)

+

+

+

+

+

+#endif

+

diff --git a/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8820.h b/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8820.h
new file mode 100644
index 0000000000..52ac62f983
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8820.h
@@ -0,0 +1,1427 @@
+#ifndef _REG_MD_SYSCTRL_H_

+#define _REG_MD_SYSCTRL_H_

+

+#include <asm/arch/hardware.h>

+#include <asm/arch/rda_iomap.h>

+

+// =============================================================================

+//  MACROS

+// =============================================================================

+

+// ============================================================================

+// CPU_ID_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// CPU IDs

+    XCPU                                        = 0x00000000,

+    BCPU                                        = 0x00000001,

+    WCPU                                        = 0x00000002

+} CPU_ID_T;

+

+#define NB_MODEM_CPU                            (3)

+

+// ============================================================================

+// SYS_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// System side System clocks

+    SYS_XCPU                                    = 0x00000000,

+    SYS_XCPU_INT                                = 0x00000001,

+    SYS_PCLK_CONF                               = 0x00000002,

+    SYS_PCLK_DATA                               = 0x00000003,

+    SYS_AMBA                                    = 0x00000004,

+    SYS_DMA                                     = 0x00000005,

+    SYS_EBC                                     = 0x00000006,

+    SYS_IFC_CH0                                 = 0x00000007,

+    SYS_IFC_CH1                                 = 0x00000008,

+    SYS_IFC_CH2                                 = 0x00000009,

+    SYS_IFC_CH3                                 = 0x0000000A,

+    SYS_IFC_DBG                                 = 0x0000000B,

+    SYS_A2A                                     = 0x0000000C,

+    SYS_AXI2AHB                                 = 0x0000000D,

+    SYS_AHB2AXI                                 = 0x0000000E,

+    SYS_EXT_AHB                                 = 0x0000000F,

+    SYS_DEBUG_UART                              = 0x00000010,

+    SYS_DBGHST                                  = 0x00000011,

+    SYS_A2A_WD                                  = 0x00000012,

+    SYS_DMA2                                    = 0x00000013,

+/// System side divided clock (either divided by module or by sys_ctrl)

+    SYSD_SCI1                                   = 0x00000014,

+    SYSD_SCI2                                   = 0x00000015,

+    SYSD_SCI3                                   = 0x00000016,

+    SYSD_RF_SPI                                 = 0x00000017,

+    SYSD_OSC                                    = 0x00000018,

+/// the following don't have an auto enable

+    SYS_GPIO                                    = 0x00000019,

+    SYS_IRQ                                     = 0x0000001A,

+    SYS_TCU                                     = 0x0000001B,

+    SYS_TIMER                                   = 0x0000001C,

+    SYS_COM_REGS                                = 0x0000001D,

+/// the following are sharing their enable

+    SYS_SCI1                                    = 0x0000001E,

+    SYS_SCI2                                    = 0x0000001F,

+    SYS_SCI3                                    = 0x00000020,

+/// keep last

+    SYS_NOGATE                                  = 0x00000021

+} SYS_CLKS_T;

+

+#define NB_SYS_CLK_XCPU                         (2)

+#define NB_SYS_CLK_AEN                          (25)

+#define NB_SYS_CLK_EN                           (30)

+#define NB_SYS_CLK                              (34)

+

+// ============================================================================

+// SYS2_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// WCDMA Baseband side System clocks

+    SYS_MPMC                                    = 0x00000000,

+    SYS_MPMCREG                                 = 0x00000001,

+/// the following don't have an auto enable

+    SYS_DP_BB                                   = 0x00000002,

+    SYS_DP_WD                                   = 0x00000003,

+    SYS_DP_AP                                   = 0x00000004

+} SYS2_CLKS_T;

+

+#define NB_SYS2_CLK_AEN                         (2)

+#define NB_SYS2_CLK_EN                          (5)

+#define NB_SYS2_CLK                             (5)

+

+// ============================================================================

+// PER_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+    PER_I2C                                     = 0x00000000,

+/// System side divided clock (either divided by module or by sys_ctrl)

+    PERD_SPI1                                   = 0x00000001,

+/// System side divided clock (either divided by module or by sys_ctrl)

+    PERD_SPI2                                   = 0x00000002,

+    PER_SPY                                     = 0x00000003,

+    PER_TEST                                    = 0x00000004

+} PER_CLKS_T;

+

+#define NB_PER_CLK_AEN                          (3)

+#define NB_PER_CLK_EN                           (5)

+#define NB_PER_CLK                              (5)

+

+// ============================================================================

+// BB_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// Baseband side System clocks

+    BB_BCPU                                     = 0x00000000,

+    BB_BCPU_INT                                 = 0x00000001,

+    BB_AMBA                                     = 0x00000002,

+    BB_PCLK_CONF                                = 0x00000003,

+    BB_PCLK_DATA                                = 0x00000004,

+    BB_EXCOR                                    = 0x00000005,

+    BB_IFC_CH2                                  = 0x00000006,

+    BB_IFC_CH3                                  = 0x00000007,

+    BB_SRAM                                     = 0x00000008,

+    BB_A2A                                      = 0x00000009,

+    BB_ITLV                                     = 0x0000000A,

+    BB_VITERBI                                  = 0x0000000B,

+    BB_CIPHER                                   = 0x0000000C,

+    BB_RF_IF                                    = 0x0000000D,

+    BB_COPRO                                    = 0x0000000E,

+    BB_CP2_REG                                  = 0x0000000F,

+    BB_XCOR                                     = 0x00000010,

+    BB_EVITAC                                   = 0x00000011,

+    BB_ROM                                      = 0x00000012,

+    BB_MPMC                                     = 0x00000013,

+    BB_VTB                                      = 0x00000014,

+/// the following don't have an auto enable

+    BB_IRQ                                      = 0x00000015,

+    BB_COM_REGS                                 = 0x00000016,

+    BB_CORDIC                                   = 0x00000017,

+    BB_DP                                       = 0x00000018

+} BB_CLKS_T;

+

+#define NB_BB_CLK_AEN                           (21)

+#define NB_BB_CLK_EN                            (25)

+#define NB_BB_CLK                               (25)

+

+// ============================================================================

+// WD_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// WCDMA Baseband side System clocks

+    WD_WCPU                                     = 0x00000000,

+    WD_AMBA                                     = 0x00000001,

+    WD_PCLK_CONF                                = 0x00000002,

+    WD_PCLK_DATA                                = 0x00000003,

+    WD_A2A                                      = 0x00000004,

+    WD_IFC_CH_SPI                               = 0x00000005,

+    WD_MPMC                                     = 0x00000006,

+    WD_EXT_AHB                                  = 0x00000007,

+    WDD_OSC                                     = 0x00000008,

+/// the following don't have an auto enable

+    WD_IRQ                                      = 0x00000009,

+    WD_AXI                                      = 0x0000000A,

+    WD_DP                                       = 0x0000000B,

+    WD_MODEM                                    = 0x0000000C,

+    WD_COM_REGS                                 = 0x0000000D,

+    WD_TIMER                                    = 0x0000000E,

+    WD_SDMA                                     = 0x0000000F,

+    WD_SLPC                                     = 0x00000010,

+    WD_SLPT                                     = 0x00000011,

+    WD_SPI1                                     = 0x00000012,

+    WD_SPI2                                     = 0x00000013,

+    WD_RFIF                                     = 0x00000014,

+    WD_PAGE_SPY                                 = 0x00000015

+} WD_CLKS_T;

+

+#define NB_WD_CLK_AEN                           (9)

+#define NB_WD_CLK_EN                            (22)

+#define NB_WD_CLK                               (22)

+/// Other clocks

+/// clocks with auto enble

+/// the debug host clock auto enable is not used in host mode, only in uart mode

+#define OC_HOST_UART                            (0)

+

+// ============================================================================

+// OTHER_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+    OC_DEBUG_UART                               = 0x00000000,

+    OC_RF_RX                                    = 0x00000001,

+    OC_RF_TX                                    = 0x00000002,

+    OC_MEM_BRIDGE                               = 0x00000003,

+/// the following don't have an auto enable

+    OC_LPS                                      = 0x00000004,

+    OC_GPIO                                     = 0x00000005,

+    OC_CLK_OUT                                  = 0x00000006,

+    OC_MEM_CLK_OUT                              = 0x00000007,

+    OC_TCU                                      = 0x00000008,

+    OC_WD_CHIP                                  = 0x00000009,

+    OC_WD_ADC                                   = 0x0000000A,

+    OC_WD_TURBO                                 = 0x0000000B,

+    OC_WD_OSC                                   = 0x0000000C,

+    OC_MPMC                                     = 0x0000000D,

+    OC_BB_VTB                                   = 0x0000000E

+} OTHER_CLKS_T;

+

+#define NB_OTHER_CLK_AEN                        (4)

+#define NB_OTHER_CLK_EN                         (15)

+#define NB_OTHER_CLK                            (15)

+

+// ============================================================================

+// RESETS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// System side resets

+    RST_XCPU                                    = 0x00000000,

+    RST_SYS_IRQ                                 = 0x00000001,

+    RST_SYS_A2A                                 = 0x00000002,

+    RST_SYS_AHB2AXI                             = 0x00000003,

+    RST_SYS_AXI2AHB                             = 0x00000004,

+    RST_DMA                                     = 0x00000005,

+    RST_TIMER                                   = 0x00000006,

+    RST_TCU                                     = 0x00000007,

+    RST_GPIO                                    = 0x00000008,

+    RST_I2C                                     = 0x00000009,

+    RST_CFG                                     = 0x0000000A,

+    RST_SPI1                                    = 0x0000000B,

+    RST_SPI2                                    = 0x0000000C,

+    RST_RF_SPI                                  = 0x0000000D,

+    RST_SCI1                                    = 0x0000000E,

+    RST_SCI2                                    = 0x0000000F,

+    RST_SCI3                                    = 0x00000010,

+    RST_SPY                                     = 0x00000011,

+    RST_MEM_BRIDGE                              = 0x00000012,

+    RST_EXT_AHB                                 = 0x00000013,

+    RST_DP_BB                                   = 0x00000014,

+    RST_DP_AP                                   = 0x00000015,

+    RST_COMREGS                                 = 0x00000016,

+    RST_COMREGS_AP                              = 0x00000017,

+    RST_AP_CLKEN                                = 0x00000018,

+    RST_AP_RST                                  = 0x00000019,

+    RST_MEM_CHK                                 = 0x0000001A,

+    RST_MPMC                                    = 0x0000001B,

+    RST_SYS_A2A_WD                              = 0x0000001C,

+    RST_COMREGS_WD                              = 0x0000001D,

+    RST_BCPU                                    = 0x0000001E,

+    RST_BB_IRQ                                  = 0x0000001F,

+    RST_BB_A2A                                  = 0x00000020,

+    RST_BB_IFC                                  = 0x00000021,

+    RST_BB_SRAM                                 = 0x00000022,

+    RST_ITLV                                    = 0x00000023,

+    RST_VITERBI                                 = 0x00000024,

+    RST_CIPHER                                  = 0x00000025,

+    RST_XCOR                                    = 0x00000026,

+    RST_COPRO                                   = 0x00000027,

+    RST_RF_IF                                   = 0x00000028,

+    RST_EXCOR                                   = 0x00000029,

+    RST_EVITAC                                  = 0x0000002A,

+    RST_CORDIC                                  = 0x0000002B,

+    RST_TCU_BB                                  = 0x0000002C,

+    RST_BB_DP                                   = 0x0000002D,

+    RST_BB_ROM                                  = 0x0000002E,

+    RST_MPMC_BB                                 = 0x0000002F,

+    RST_BB_VTB                                  = 0x00000030,

+    RST_BB_FULL                                 = 0x00000031,

+    RST_SYS_FULL                                = 0x00000032

+} RESETS_T;

+

+#define NB_SRST                                 (30)

+/// Baseband side resets

+#define BOUND_BRST_FIRST                        (30)

+#define BOUND_BRST_AFTER                        (49)

+/// The following reset does not have register

+#define NR_RST_REG                              (50)

+#define NB_RST                                  (51)

+#define NB_BRST                                 (BOUND_BRST_AFTER-BOUND_BRST_FIRST)

+

+// ============================================================================

+// RESET_OTHERS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// Reset Other : resync on corresponding clock other

+    RSTO_DBG_HOST                               = 0x00000000,

+    RSTO_RF_RX                                  = 0x00000001,

+    RSTO_RF_TX                                  = 0x00000002,

+    RSTO_MEM_BRIDGE                             = 0x00000003,

+    RSTO_LPS                                    = 0x00000004,

+    RSTO_GPIO                                   = 0x00000005,

+    RSTO_WDTIMER                                = 0x00000006,

+    RSTO_TCU                                    = 0x00000007,

+    RSTO_MPMC                                   = 0x00000008,

+    RSTO_VTB                                    = 0x00000009

+} RESET_OTHERS_T;

+

+#define BOUND_RSTO_RF_FIRST                     (1)

+#define BOUND_RSTO_RF_AFTER                     (3)

+#define NB_RSTO                                 (10)

+

+// ============================================================================

+// WD_RESETS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// WD side resets

+    WD_RST_WCPU                                 = 0x00000000,

+    WD_RST_IRQ                                  = 0x00000001,

+    WD_RST_DP                                   = 0x00000002,

+    WD_RST_MODEM                                = 0x00000003,

+    WD_RST_A2A                                  = 0x00000004,

+    WD_RST_IFC                                  = 0x00000005,

+    WD_RST_SDMA                                 = 0x00000006,

+    WD_RST_SLPC                                 = 0x00000007,

+    WD_RST_SLPT                                 = 0x00000008,

+    WD_RST_SPI1                                 = 0x00000009,

+    WD_RST_SPI2                                 = 0x0000000A,

+    WD_RST_RFIF                                 = 0x0000000B,

+    WD_RST_COMREGS                              = 0x0000000C,

+    WD_RST_TIMER                                = 0x0000000D,

+    WD_RST_MPMC                                 = 0x0000000E,

+    WD_RST_EXT_AHB                              = 0x0000000F,

+    WD_RST_PAGE_SPY                             = 0x00000010,

+    WD_RST_FULL                                 = 0x00000011

+} WD_RESETS_T;

+

+#define NB_WD_RST_BOUND                         (17)

+#define NB_WD_RST                               (18)

+

+// ============================================================================

+// AP_RESETS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// AP side resets

+    AP_RST_0                                    = 0x00000000,

+    AP_RST_1                                    = 0x00000001,

+    AP_RST_2                                    = 0x00000002,

+    AP_RST_3                                    = 0x00000003,

+    AP_RST_4                                    = 0x00000004

+} AP_RESETS_T;

+

+#define NB_AP_RST_BOUND                         (5)

+#define NB_AP_RST                               (5)

+/// For REG_DBG protect lock/unlock value

+#define SYS_CTRL_PROTECT_LOCK                   (0XA50000)

+#define SYS_CTRL_PROTECT_UNLOCK                 (0XA50001)

+

+// =============================================================================

+//  TYPES

+// =============================================================================

+

+// ============================================================================

+// SYS_CTRL_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef volatile struct

+{

+    /// <strong>This register is used to Lock and Unlock the protected registers.</strong>

+    REG32                          REG_DBG;                      //0x00000000

+    /// This register is protected.

+    REG32                          Sys_Rst_Set;                  //0x00000004

+    REG32                          Sys_Rst_Clr;                  //0x00000008

+    /// This register is protected.

+    REG32                          BB_Rst_Set;                   //0x0000000C

+    REG32                          BB_Rst_Clr;                   //0x00000010

+    REG32                          Clk_Sys_Mode;                 //0x00000014

+    REG32                          Clk_Sys_Enable;               //0x00000018

+    /// This register is protected.

+    REG32                          Clk_Sys_Disable;              //0x0000001C

+    REG32                          Clk_Per_Mode;                 //0x00000020

+    REG32                          Clk_Per_Enable;               //0x00000024

+    /// This register is protected.

+    REG32                          Clk_Per_Disable;              //0x00000028

+    REG32                          Clk_BB_Mode;                  //0x0000002C

+    REG32                          Clk_BB_Enable;                //0x00000030

+    /// This register is protected.

+    REG32                          Clk_BB_Disable;               //0x00000034

+    REG32                          Clk_Other_Mode;               //0x00000038

+    REG32                          Clk_Other_Enable;             //0x0000003C

+    /// This register is protected.

+    REG32                          Clk_Other_Disable;            //0x00000040

+    /// Register protected by Write_Unlocked_H.

+    REG32                          Pll_Ctrl;                     //0x00000044

+    /// This register is protected.

+    REG32                          Sel_Clock;                    //0x00000048

+    REG32                          Cfg_Clk_Sys;                  //0x0000004C

+    REG32                          Cfg_Clk_Mem_Bridge;           //0x00000050

+    /// This register is protected.

+    REG32                          Cfg_Clk_Out;                  //0x00000054

+    REG32                          Cfg_Clk_Host_Uart;            //0x00000058

+    REG32                          Cfg_Clk_Auxclk;               //0x0000005C

+    /// This register is protected.

+    REG32                          Cfg_AHB;                      //0x00000060

+    /// This register is protected. Used to unsplit masters manualy.

+    REG32                          Ctrl_AHB;                     //0x00000064

+    REG32                          XCpu_Dbg_BKP;                 //0x00000068

+    REG32                          XCpu_Dbg_Addr;                //0x0000006C

+    REG32                          BCpu_Dbg_BKP;                 //0x00000070

+    REG32                          BCpu_Dbg_Addr;                //0x00000074

+    REG32                          Cfg_Cpus_Cache_Ram_Disable;   //0x00000078

+    REG32                          Reset_Cause;                  //0x0000007C

+    /// This register is protected.

+    REG32                          WakeUp;                       //0x00000080

+    REG32                          AP_Ctrl;                      //0x00000084

+    /// This register is protected.

+    REG32                          Ignore_Charger;               //0x00000088

+    REG32                          Clk_SYS2_Mode;                //0x0000008C

+    REG32                          Clk_SYS2_Enable;              //0x00000090

+    /// This register is protected.

+    REG32                          Clk_SYS2_Disable;             //0x00000094

+    /// Register protected by Write_Unlocked_H.

+    REG32                          WD_Pll_Ctrl;                  //0x00000098

+    /// This register is protected.

+    REG32                          WD_Sel_Clock;                 //0x0000009C

+    /// This register is protected.

+    REG32                          WD_Rst_Set;                   //0x000000A0

+    REG32                          WD_Rst_Clr;                   //0x000000A4

+    /// This register is protected.

+    REG32                          AP_Rst_Set;                   //0x000000A8

+    REG32                          AP_Rst_Clr;                   //0x000000AC

+    REG32                          Clk_WD_Mode;                  //0x000000B0

+    REG32                          Clk_WD_Enable;                //0x000000B4

+    /// This register is protected.

+    REG32                          Clk_WD_Disable;               //0x000000B8

+    REG32                          Cfg_Clk_MPMC;                 //0x000000BC

+    REG32                          Cfg_MPMC_DQS;                 //0x000000C0

+    REG32                          Cfg_Clk_BB_VTB;               //0x000000C4

+    REG32 Reserved_000000C8[13];                //0x000000C8

+    /// This register is reserved.

+    REG32                          Cfg_Reserve;                  //0x000000FC

+} HWP_SYS_CTRL_T;

+

+#define hwp_sysCtrlMd               ((HWP_SYS_CTRL_T*)(RDA_MD_SYSCTRL_BASE))

+

+

+//REG_DBG

+#define SYS_CTRL_SCRATCH(n)        (((n)&0xFFFF)<<0)

+#define SYS_CTRL_WRITE_UNLOCK_STATUS (1<<30)

+#define SYS_CTRL_WRITE_UNLOCK      (1<<31)

+

+//Sys_Rst_Set

+#define SYS_CTRL_SET_RST_XCPU      (1<<0)

+#define SYS_CTRL_SET_RST_SYS_IRQ   (1<<1)

+#define SYS_CTRL_SET_RST_SYS_A2A   (1<<2)

+#define SYS_CTRL_SET_RST_SYS_AHB2AXI (1<<3)

+#define SYS_CTRL_SET_RST_SYS_AXI2AHB (1<<4)

+#define SYS_CTRL_SET_RST_DMA       (1<<5)

+#define SYS_CTRL_SET_RST_TIMER     (1<<6)

+#define SYS_CTRL_SET_RST_TCU       (1<<7)

+#define SYS_CTRL_SET_RST_GPIO      (1<<8)

+#define SYS_CTRL_SET_RST_I2C       (1<<9)

+#define SYS_CTRL_SET_RST_CFG       (1<<10)

+#define SYS_CTRL_SET_RST_SPI1      (1<<11)

+#define SYS_CTRL_SET_RST_SPI2      (1<<12)

+#define SYS_CTRL_SET_RST_RF_SPI    (1<<13)

+#define SYS_CTRL_SET_RST_SCI1      (1<<14)

+#define SYS_CTRL_SET_RST_SCI2      (1<<15)

+#define SYS_CTRL_SET_RST_SCI3      (1<<16)

+#define SYS_CTRL_SET_RST_SPY       (1<<17)

+#define SYS_CTRL_SET_RST_MEM_BRIDGE (1<<18)

+#define SYS_CTRL_SET_RST_EXT_AHB   (1<<19)

+#define SYS_CTRL_SET_RST_DP_BB     (1<<20)

+#define SYS_CTRL_SET_RST_DP_AP     (1<<21)

+#define SYS_CTRL_SET_RST_COMREGS   (1<<22)

+#define SYS_CTRL_SET_RST_COMREGS_AP (1<<23)

+#define SYS_CTRL_SET_RST_AP_CLKEN  (1<<24)

+#define SYS_CTRL_SET_RST_AP_RST    (1<<25)

+#define SYS_CTRL_SET_RST_MEM_CHK   (1<<26)

+#define SYS_CTRL_SET_RST_MPMC      (1<<27)

+#define SYS_CTRL_SET_RST_SYS_A2A_WD (1<<28)

+#define SYS_CTRL_SET_RST_COMREGS_WD (1<<29)

+#define SYS_CTRL_SET_RST_OUT       (1<<30)

+#define SYS_CTRL_SOFT_RST          (1<<31)

+#define SYS_CTRL_SET_SYS_RST(n)    (((n)&0x3FFFFFFF)<<0)

+#define SYS_CTRL_SET_SYS_RST_MASK  (0x3FFFFFFF<<0)

+#define SYS_CTRL_SET_SYS_RST_SHIFT (0)

+

+//Sys_Rst_Clr

+#define SYS_CTRL_CLR_RST_XCPU      (1<<0)

+#define SYS_CTRL_CLR_RST_SYS_IRQ   (1<<1)

+#define SYS_CTRL_CLR_RST_SYS_A2A   (1<<2)

+#define SYS_CTRL_CLR_RST_SYS_AHB2AXI (1<<3)

+#define SYS_CTRL_CLR_RST_SYS_AXI2AHB (1<<4)

+#define SYS_CTRL_CLR_RST_DMA       (1<<5)

+#define SYS_CTRL_CLR_RST_TIMER     (1<<6)

+#define SYS_CTRL_CLR_RST_TCU       (1<<7)

+#define SYS_CTRL_CLR_RST_GPIO      (1<<8)

+#define SYS_CTRL_CLR_RST_I2C       (1<<9)

+#define SYS_CTRL_CLR_RST_CFG       (1<<10)

+#define SYS_CTRL_CLR_RST_SPI1      (1<<11)

+#define SYS_CTRL_CLR_RST_SPI2      (1<<12)

+#define SYS_CTRL_CLR_RST_RF_SPI    (1<<13)

+#define SYS_CTRL_CLR_RST_SCI1      (1<<14)

+#define SYS_CTRL_CLR_RST_SCI2      (1<<15)

+#define SYS_CTRL_CLR_RST_SCI3      (1<<16)

+#define SYS_CTRL_CLR_RST_SPY       (1<<17)

+#define SYS_CTRL_CLR_RST_MEM_BRIDGE (1<<18)

+#define SYS_CTRL_CLR_RST_EXT_AHB   (1<<19)

+#define SYS_CTRL_CLR_RST_DP_BB     (1<<20)

+#define SYS_CTRL_CLR_RST_DP_AP     (1<<21)

+#define SYS_CTRL_CLR_RST_COMREGS   (1<<22)

+#define SYS_CTRL_CLR_RST_COMREGS_AP (1<<23)

+#define SYS_CTRL_CLR_RST_AP_CLKEN  (1<<24)

+#define SYS_CTRL_CLR_RST_AP_RST    (1<<25)

+#define SYS_CTRL_CLR_RST_MEM_CHK   (1<<26)

+#define SYS_CTRL_CLR_RST_MPMC      (1<<27)

+#define SYS_CTRL_CLR_RST_SYS_A2A_WD (1<<28)

+#define SYS_CTRL_CLR_RST_COMREGS_WD (1<<29)

+#define SYS_CTRL_CLR_RST_OUT       (1<<30)

+#define SYS_CTRL_CLR_SYS_RST(n)    (((n)&0x3FFFFFFF)<<0)

+#define SYS_CTRL_CLR_SYS_RST_MASK  (0x3FFFFFFF<<0)

+#define SYS_CTRL_CLR_SYS_RST_SHIFT (0)

+

+//BB_Rst_Set

+#define SYS_CTRL_SET_RST_BCPU      (1<<0)

+#define SYS_CTRL_SET_RST_BB_IRQ    (1<<1)

+#define SYS_CTRL_SET_RST_BB_A2A    (1<<2)

+#define SYS_CTRL_SET_RST_BB_IFC    (1<<3)

+#define SYS_CTRL_SET_RST_BB_SRAM   (1<<4)

+#define SYS_CTRL_SET_RST_ITLV      (1<<5)

+#define SYS_CTRL_SET_RST_VITERBI   (1<<6)

+#define SYS_CTRL_SET_RST_CIPHER    (1<<7)

+#define SYS_CTRL_SET_RST_XCOR      (1<<8)

+#define SYS_CTRL_SET_RST_COPRO     (1<<9)

+#define SYS_CTRL_SET_RST_RF_IF     (1<<10)

+#define SYS_CTRL_SET_RST_EXCOR     (1<<11)

+#define SYS_CTRL_SET_RST_EVITAC    (1<<12)

+#define SYS_CTRL_SET_RST_CORDIC    (1<<13)

+#define SYS_CTRL_SET_RST_TCU_BB    (1<<14)

+#define SYS_CTRL_SET_RST_BB_DP     (1<<15)

+#define SYS_CTRL_SET_RST_BB_ROM    (1<<16)

+#define SYS_CTRL_SET_RST_MPMC_BB   (1<<17)

+#define SYS_CTRL_SET_RST_BB_VTB    (1<<18)

+#define SYS_CTRL_SET_RST_BB_FULL   (1<<31)

+#define SYS_CTRL_SET_BB_RST(n)     (((n)&0x7FFFF)<<0)

+#define SYS_CTRL_SET_BB_RST_MASK   (0x7FFFF<<0)

+#define SYS_CTRL_SET_BB_RST_SHIFT  (0)

+

+//BB_Rst_Clr

+#define SYS_CTRL_CLR_RST_BCPU      (1<<0)

+#define SYS_CTRL_CLR_RST_BB_IRQ    (1<<1)

+#define SYS_CTRL_CLR_RST_BB_A2A    (1<<2)

+#define SYS_CTRL_CLR_RST_BB_IFC    (1<<3)

+#define SYS_CTRL_CLR_RST_BB_SRAM   (1<<4)

+#define SYS_CTRL_CLR_RST_ITLV      (1<<5)

+#define SYS_CTRL_CLR_RST_VITERBI   (1<<6)

+#define SYS_CTRL_CLR_RST_CIPHER    (1<<7)

+#define SYS_CTRL_CLR_RST_XCOR      (1<<8)

+#define SYS_CTRL_CLR_RST_COPRO     (1<<9)

+#define SYS_CTRL_CLR_RST_RF_IF     (1<<10)

+#define SYS_CTRL_CLR_RST_EXCOR     (1<<11)

+#define SYS_CTRL_CLR_RST_EVITAC    (1<<12)

+#define SYS_CTRL_CLR_RST_CORDIC    (1<<13)

+#define SYS_CTRL_CLR_RST_TCU_BB    (1<<14)

+#define SYS_CTRL_CLR_RST_BB_DP     (1<<15)

+#define SYS_CTRL_CLR_RST_BB_ROM    (1<<16)

+#define SYS_CTRL_CLR_RST_MPMC_BB   (1<<17)

+#define SYS_CTRL_CLR_RST_BB_VTB    (1<<18)

+#define SYS_CTRL_CLR_RST_BB_FULL   (1<<31)

+#define SYS_CTRL_CLR_BB_RST(n)     (((n)&0x7FFFF)<<0)

+#define SYS_CTRL_CLR_BB_RST_MASK   (0x7FFFF<<0)

+#define SYS_CTRL_CLR_BB_RST_SHIFT  (0)

+

+//Clk_Sys_Mode

+#define SYS_CTRL_MODE_SYS_XCPU     (1<<0)

+#define SYS_CTRL_MODE_SYS_XCPU_INT_AUTOMATIC (0<<1)

+#define SYS_CTRL_MODE_SYS_XCPU_INT_MANUAL (1<<1)

+#define SYS_CTRL_MODE_SYS_PCLK_CONF_AUTOMATIC (0<<2)

+#define SYS_CTRL_MODE_SYS_PCLK_CONF_MANUAL (1<<2)

+#define SYS_CTRL_MODE_SYS_PCLK_DATA_AUTOMATIC (0<<3)

+#define SYS_CTRL_MODE_SYS_PCLK_DATA_MANUAL (1<<3)

+#define SYS_CTRL_MODE_SYS_AMBA_AUTOMATIC (0<<4)

+#define SYS_CTRL_MODE_SYS_AMBA_MANUAL (1<<4)

+#define SYS_CTRL_MODE_SYS_DMA_AUTOMATIC (0<<5)

+#define SYS_CTRL_MODE_SYS_DMA_MANUAL (1<<5)

+#define SYS_CTRL_MODE_SYS_EBC_AUTOMATIC (0<<6)

+#define SYS_CTRL_MODE_SYS_EBC_MANUAL (1<<6)

+#define SYS_CTRL_MODE_SYS_IFC_CH0_AUTOMATIC (0<<7)

+#define SYS_CTRL_MODE_SYS_IFC_CH0_MANUAL (1<<7)

+#define SYS_CTRL_MODE_SYS_IFC_CH1_AUTOMATIC (0<<8)

+#define SYS_CTRL_MODE_SYS_IFC_CH1_MANUAL (1<<8)

+#define SYS_CTRL_MODE_SYS_IFC_CH2_AUTOMATIC (0<<9)

+#define SYS_CTRL_MODE_SYS_IFC_CH2_MANUAL (1<<9)

+#define SYS_CTRL_MODE_SYS_IFC_CH3_AUTOMATIC (0<<10)

+#define SYS_CTRL_MODE_SYS_IFC_CH3_MANUAL (1<<10)

+#define SYS_CTRL_MODE_SYS_IFC_DBG_AUTOMATIC (0<<11)

+#define SYS_CTRL_MODE_SYS_IFC_DBG_MANUAL (1<<11)

+#define SYS_CTRL_MODE_SYS_A2A_AUTOMATIC (0<<12)

+#define SYS_CTRL_MODE_SYS_A2A_MANUAL (1<<12)

+#define SYS_CTRL_MODE_SYS_AXI2AHB_AUTOMATIC (0<<13)

+#define SYS_CTRL_MODE_SYS_AXI2AHB_MANUAL (1<<13)

+#define SYS_CTRL_MODE_SYS_AHB2AXI_AUTOMATIC (0<<14)

+#define SYS_CTRL_MODE_SYS_AHB2AXI_MANUAL (1<<14)

+#define SYS_CTRL_MODE_SYS_EXT_AHB_AUTOMATIC (0<<15)

+#define SYS_CTRL_MODE_SYS_EXT_AHB_MANUAL (1<<15)

+#define SYS_CTRL_MODE_SYS_DEBUG_UART_AUTOMATIC (0<<16)

+#define SYS_CTRL_MODE_SYS_DEBUG_UART_MANUAL (1<<16)

+#define SYS_CTRL_MODE_SYS_DBGHST_AUTOMATIC (0<<17)

+#define SYS_CTRL_MODE_SYS_DBGHST_MANUAL (1<<17)

+#define SYS_CTRL_MODE_SYS_A2A_WD_AUTOMATIC (0<<18)

+#define SYS_CTRL_MODE_SYS_A2A_WD_MANUAL (1<<18)

+#define SYS_CTRL_MODE_SYS_DMA2_AUTOMATIC (0<<19)

+#define SYS_CTRL_MODE_SYS_DMA2_MANUAL (1<<19)

+#define SYS_CTRL_MODE_SYSD_SCI1_AUTOMATIC (0<<20)

+#define SYS_CTRL_MODE_SYSD_SCI1_MANUAL (1<<20)

+#define SYS_CTRL_MODE_SYSD_SCI2_AUTOMATIC (0<<21)

+#define SYS_CTRL_MODE_SYSD_SCI2_MANUAL (1<<21)

+#define SYS_CTRL_MODE_SYSD_SCI3_AUTOMATIC (0<<22)

+#define SYS_CTRL_MODE_SYSD_SCI3_MANUAL (1<<22)

+#define SYS_CTRL_MODE_SYSD_RF_SPI_AUTOMATIC (0<<23)

+#define SYS_CTRL_MODE_SYSD_RF_SPI_MANUAL (1<<23)

+#define SYS_CTRL_MODE_SYSD_OSC_AUTOMATIC (0<<24)

+#define SYS_CTRL_MODE_SYSD_OSC_MANUAL (1<<24)

+#define SYS_CTRL_MODE_CLK_SYS(n)   (((n)&0xFFFFFF)<<1)

+#define SYS_CTRL_MODE_CLK_SYS_MASK (0xFFFFFF<<1)

+#define SYS_CTRL_MODE_CLK_SYS_SHIFT (1)

+

+//Clk_Sys_Enable

+#define SYS_CTRL_ENABLE_SYS_XCPU   (1<<0)

+#define SYS_CTRL_ENABLE_SYS_XCPU_INT (1<<1)

+#define SYS_CTRL_ENABLE_SYS_PCLK_CONF (1<<2)

+#define SYS_CTRL_ENABLE_SYS_PCLK_DATA (1<<3)

+#define SYS_CTRL_ENABLE_SYS_AMBA   (1<<4)

+#define SYS_CTRL_ENABLE_SYS_DMA    (1<<5)

+#define SYS_CTRL_ENABLE_SYS_EBC    (1<<6)

+#define SYS_CTRL_ENABLE_SYS_IFC_CH0 (1<<7)

+#define SYS_CTRL_ENABLE_SYS_IFC_CH1 (1<<8)

+#define SYS_CTRL_ENABLE_SYS_IFC_CH2 (1<<9)

+#define SYS_CTRL_ENABLE_SYS_IFC_CH3 (1<<10)

+#define SYS_CTRL_ENABLE_SYS_IFC_DBG (1<<11)

+#define SYS_CTRL_ENABLE_SYS_A2A    (1<<12)

+#define SYS_CTRL_ENABLE_SYS_AXI2AHB (1<<13)

+#define SYS_CTRL_ENABLE_SYS_AHB2AXI (1<<14)

+#define SYS_CTRL_ENABLE_SYS_EXT_AHB (1<<15)

+#define SYS_CTRL_ENABLE_SYS_DEBUG_UART (1<<16)

+#define SYS_CTRL_ENABLE_SYS_DBGHST (1<<17)

+#define SYS_CTRL_ENABLE_SYS_A2A_WD (1<<18)

+#define SYS_CTRL_ENABLE_SYS_DMA2   (1<<19)

+#define SYS_CTRL_ENABLE_SYSD_SCI1  (1<<20)

+#define SYS_CTRL_ENABLE_SYSD_SCI2  (1<<21)

+#define SYS_CTRL_ENABLE_SYSD_SCI3  (1<<22)

+#define SYS_CTRL_ENABLE_SYSD_RF_SPI (1<<23)

+#define SYS_CTRL_ENABLE_SYSD_OSC   (1<<24)

+#define SYS_CTRL_ENABLE_SYS_GPIO   (1<<25)

+#define SYS_CTRL_ENABLE_SYS_IRQ    (1<<26)

+#define SYS_CTRL_ENABLE_SYS_TCU    (1<<27)

+#define SYS_CTRL_ENABLE_SYS_TIMER  (1<<28)

+#define SYS_CTRL_ENABLE_SYS_COM_REGS (1<<29)

+#define SYS_CTRL_ENABLE_CLK_SYS(n) (((n)&0x3FFFFFFF)<<0)

+#define SYS_CTRL_ENABLE_CLK_SYS_MASK (0x3FFFFFFF<<0)

+#define SYS_CTRL_ENABLE_CLK_SYS_SHIFT (0)

+

+//Clk_Sys_Disable

+#define SYS_CTRL_DISABLE_SYS_XCPU  (1<<0)

+#define SYS_CTRL_DISABLE_SYS_XCPU_INT (1<<1)

+#define SYS_CTRL_DISABLE_SYS_PCLK_CONF (1<<2)

+#define SYS_CTRL_DISABLE_SYS_PCLK_DATA (1<<3)

+#define SYS_CTRL_DISABLE_SYS_AMBA  (1<<4)

+#define SYS_CTRL_DISABLE_SYS_DMA   (1<<5)

+#define SYS_CTRL_DISABLE_SYS_EBC   (1<<6)

+#define SYS_CTRL_DISABLE_SYS_IFC_CH0 (1<<7)

+#define SYS_CTRL_DISABLE_SYS_IFC_CH1 (1<<8)

+#define SYS_CTRL_DISABLE_SYS_IFC_CH2 (1<<9)

+#define SYS_CTRL_DISABLE_SYS_IFC_CH3 (1<<10)

+#define SYS_CTRL_DISABLE_SYS_IFC_DBG (1<<11)

+#define SYS_CTRL_DISABLE_SYS_A2A   (1<<12)

+#define SYS_CTRL_DISABLE_SYS_AXI2AHB (1<<13)

+#define SYS_CTRL_DISABLE_SYS_AHB2AXI (1<<14)

+#define SYS_CTRL_DISABLE_SYS_EXT_AHB (1<<15)

+#define SYS_CTRL_DISABLE_SYS_DEBUG_UART (1<<16)

+#define SYS_CTRL_DISABLE_SYS_DBGHST (1<<17)

+#define SYS_CTRL_DISABLE_SYS_A2A_WD (1<<18)

+#define SYS_CTRL_DISABLE_SYS_DMA2  (1<<19)

+#define SYS_CTRL_DISABLE_SYSD_SCI1 (1<<20)

+#define SYS_CTRL_DISABLE_SYSD_SCI2 (1<<21)

+#define SYS_CTRL_DISABLE_SYSD_SCI3 (1<<22)

+#define SYS_CTRL_DISABLE_SYSD_RF_SPI (1<<23)

+#define SYS_CTRL_DISABLE_SYSD_OSC  (1<<24)

+#define SYS_CTRL_DISABLE_SYS_GPIO  (1<<25)

+#define SYS_CTRL_DISABLE_SYS_IRQ   (1<<26)

+#define SYS_CTRL_DISABLE_SYS_TCU   (1<<27)

+#define SYS_CTRL_DISABLE_SYS_TIMER (1<<28)

+#define SYS_CTRL_DISABLE_SYS_COM_REGS (1<<29)

+#define SYS_CTRL_DISABLE_CLK_SYS(n) (((n)&0x3FFFFFFF)<<0)

+#define SYS_CTRL_DISABLE_CLK_SYS_MASK (0x3FFFFFFF<<0)

+#define SYS_CTRL_DISABLE_CLK_SYS_SHIFT (0)

+

+//Clk_Per_Mode

+#define SYS_CTRL_MODE_PER_I2C_AUTOMATIC (0<<0)

+#define SYS_CTRL_MODE_PER_I2C_MANUAL (1<<0)

+#define SYS_CTRL_MODE_PERD_SPI1_AUTOMATIC (0<<1)

+#define SYS_CTRL_MODE_PERD_SPI1_MANUAL (1<<1)

+#define SYS_CTRL_MODE_PERD_SPI2_AUTOMATIC (0<<2)

+#define SYS_CTRL_MODE_PERD_SPI2_MANUAL (1<<2)

+#define SYS_CTRL_MODE_CLK_PER(n)   (((n)&7)<<0)

+#define SYS_CTRL_MODE_CLK_PER_MASK (7<<0)

+#define SYS_CTRL_MODE_CLK_PER_SHIFT (0)

+

+//Clk_Per_Enable

+#define SYS_CTRL_ENABLE_PER_I2C    (1<<0)

+#define SYS_CTRL_ENABLE_PERD_SPI1  (1<<1)

+#define SYS_CTRL_ENABLE_PERD_SPI2  (1<<2)

+#define SYS_CTRL_ENABLE_PER_SPY    (1<<3)

+#define SYS_CTRL_ENABLE_PER_TEST   (1<<4)

+#define SYS_CTRL_ENABLE_CLK_PER(n) (((n)&31)<<0)

+#define SYS_CTRL_ENABLE_CLK_PER_MASK (31<<0)

+#define SYS_CTRL_ENABLE_CLK_PER_SHIFT (0)

+

+//Clk_Per_Disable

+#define SYS_CTRL_DISABLE_PER_I2C   (1<<0)

+#define SYS_CTRL_DISABLE_PERD_SPI1 (1<<1)

+#define SYS_CTRL_DISABLE_PERD_SPI2 (1<<2)

+#define SYS_CTRL_DISABLE_PER_SPY   (1<<3)

+#define SYS_CTRL_DISABLE_PER_TEST  (1<<4)

+#define SYS_CTRL_DISABLE_CLK_PER(n) (((n)&31)<<0)

+#define SYS_CTRL_DISABLE_CLK_PER_MASK (31<<0)

+#define SYS_CTRL_DISABLE_CLK_PER_SHIFT (0)

+

+//Clk_BB_Mode

+#define SYS_CTRL_MODE_BB_BCPU      (1<<0)

+#define SYS_CTRL_MODE_BB_BCPU_INT_AUTOMATIC (0<<1)

+#define SYS_CTRL_MODE_BB_BCPU_INT_MANUAL (1<<1)

+#define SYS_CTRL_MODE_BB_AMBA_AUTOMATIC (0<<2)

+#define SYS_CTRL_MODE_BB_AMBA_MANUAL (1<<2)

+#define SYS_CTRL_MODE_BB_PCLK_CONF_AUTOMATIC (0<<3)

+#define SYS_CTRL_MODE_BB_PCLK_CONF_MANUAL (1<<3)

+#define SYS_CTRL_MODE_BB_PCLK_DATA_AUTOMATIC (0<<4)

+#define SYS_CTRL_MODE_BB_PCLK_DATA_MANUAL (1<<4)

+#define SYS_CTRL_MODE_BB_EXCOR_AUTOMATIC (0<<5)

+#define SYS_CTRL_MODE_BB_EXCOR_MANUAL (1<<5)

+#define SYS_CTRL_MODE_BB_IFC_CH2_AUTOMATIC (0<<6)

+#define SYS_CTRL_MODE_BB_IFC_CH2_MANUAL (1<<6)

+#define SYS_CTRL_MODE_BB_IFC_CH3_AUTOMATIC (0<<7)

+#define SYS_CTRL_MODE_BB_IFC_CH3_MANUAL (1<<7)

+#define SYS_CTRL_MODE_BB_SRAM_AUTOMATIC (0<<8)

+#define SYS_CTRL_MODE_BB_SRAM_MANUAL (1<<8)

+#define SYS_CTRL_MODE_BB_A2A_AUTOMATIC (0<<9)

+#define SYS_CTRL_MODE_BB_A2A_MANUAL (1<<9)

+#define SYS_CTRL_MODE_BB_ITLV_AUTOMATIC (0<<10)

+#define SYS_CTRL_MODE_BB_ITLV_MANUAL (1<<10)

+#define SYS_CTRL_MODE_BB_VITERBI_AUTOMATIC (0<<11)

+#define SYS_CTRL_MODE_BB_VITERBI_MANUAL (1<<11)

+#define SYS_CTRL_MODE_BB_CIPHER_AUTOMATIC (0<<12)

+#define SYS_CTRL_MODE_BB_CIPHER_MANUAL (1<<12)

+#define SYS_CTRL_MODE_BB_RF_IF_AUTOMATIC (0<<13)

+#define SYS_CTRL_MODE_BB_RF_IF_MANUAL (1<<13)

+#define SYS_CTRL_MODE_BB_COPRO_AUTOMATIC (0<<14)

+#define SYS_CTRL_MODE_BB_COPRO_MANUAL (1<<14)

+#define SYS_CTRL_MODE_BB_CP2_REG_AUTOMATIC (0<<15)

+#define SYS_CTRL_MODE_BB_CP2_REG_MANUAL (1<<15)

+#define SYS_CTRL_MODE_BB_XCOR_AUTOMATIC (0<<16)

+#define SYS_CTRL_MODE_BB_XCOR_MANUAL (1<<16)

+#define SYS_CTRL_MODE_BB_EVITAC_AUTOMATIC (0<<17)

+#define SYS_CTRL_MODE_BB_EVITAC_MANUAL (1<<17)

+#define SYS_CTRL_MODE_BB_ROM_AUTOMATIC (0<<18)

+#define SYS_CTRL_MODE_BB_ROM_MANUAL (1<<18)

+#define SYS_CTRL_MODE_BB_MPMC_AUTOMATIC (0<<19)

+#define SYS_CTRL_MODE_BB_MPMC_MANUAL (1<<19)

+#define SYS_CTRL_MODE_BB_VTB_AUTOMATIC (0<<20)

+#define SYS_CTRL_MODE_BB_VTB_MANUAL (1<<20)

+#define SYS_CTRL_MODE_CLK_BB(n)    (((n)&0xFFFFF)<<1)

+#define SYS_CTRL_MODE_CLK_BB_MASK  (0xFFFFF<<1)

+#define SYS_CTRL_MODE_CLK_BB_SHIFT (1)

+

+//Clk_BB_Enable

+#define SYS_CTRL_ENABLE_BB_BCPU    (1<<0)

+#define SYS_CTRL_ENABLE_BB_BCPU_INT (1<<1)

+#define SYS_CTRL_ENABLE_BB_AMBA    (1<<2)

+#define SYS_CTRL_ENABLE_BB_PCLK_CONF (1<<3)

+#define SYS_CTRL_ENABLE_BB_PCLK_DATA (1<<4)

+#define SYS_CTRL_ENABLE_BB_EXCOR   (1<<5)

+#define SYS_CTRL_ENABLE_BB_IFC_CH2 (1<<6)

+#define SYS_CTRL_ENABLE_BB_IFC_CH3 (1<<7)

+#define SYS_CTRL_ENABLE_BB_SRAM    (1<<8)

+#define SYS_CTRL_ENABLE_BB_A2A     (1<<9)

+#define SYS_CTRL_ENABLE_BB_ITLV    (1<<10)

+#define SYS_CTRL_ENABLE_BB_VITERBI (1<<11)

+#define SYS_CTRL_ENABLE_BB_CIPHER  (1<<12)

+#define SYS_CTRL_ENABLE_BB_RF_IF   (1<<13)

+#define SYS_CTRL_ENABLE_BB_COPRO   (1<<14)

+#define SYS_CTRL_ENABLE_BB_CP2_REG (1<<15)

+#define SYS_CTRL_ENABLE_BB_XCOR    (1<<16)

+#define SYS_CTRL_ENABLE_BB_EVITAC  (1<<17)

+#define SYS_CTRL_ENABLE_BB_ROM     (1<<18)

+#define SYS_CTRL_ENABLE_BB_MPMC    (1<<19)

+#define SYS_CTRL_ENABLE_BB_VTB     (1<<20)

+#define SYS_CTRL_ENABLE_BB_IRQ     (1<<21)

+#define SYS_CTRL_ENABLE_BB_COM_REGS (1<<22)

+#define SYS_CTRL_ENABLE_BB_CORDIC  (1<<23)

+#define SYS_CTRL_ENABLE_BB_DP      (1<<24)

+#define SYS_CTRL_ENABLE_CLK_BB(n)  (((n)&0x1FFFFFF)<<0)

+#define SYS_CTRL_ENABLE_CLK_BB_MASK (0x1FFFFFF<<0)

+#define SYS_CTRL_ENABLE_CLK_BB_SHIFT (0)

+

+//Clk_BB_Disable

+#define SYS_CTRL_DISABLE_BB_BCPU   (1<<0)

+#define SYS_CTRL_DISABLE_BB_BCPU_INT (1<<1)

+#define SYS_CTRL_DISABLE_BB_AMBA   (1<<2)

+#define SYS_CTRL_DISABLE_BB_PCLK_CONF (1<<3)

+#define SYS_CTRL_DISABLE_BB_PCLK_DATA (1<<4)

+#define SYS_CTRL_DISABLE_BB_EXCOR  (1<<5)

+#define SYS_CTRL_DISABLE_BB_IFC_CH2 (1<<6)

+#define SYS_CTRL_DISABLE_BB_IFC_CH3 (1<<7)

+#define SYS_CTRL_DISABLE_BB_SRAM   (1<<8)

+#define SYS_CTRL_DISABLE_BB_A2A    (1<<9)

+#define SYS_CTRL_DISABLE_BB_ITLV   (1<<10)

+#define SYS_CTRL_DISABLE_BB_VITERBI (1<<11)

+#define SYS_CTRL_DISABLE_BB_CIPHER (1<<12)

+#define SYS_CTRL_DISABLE_BB_RF_IF  (1<<13)

+#define SYS_CTRL_DISABLE_BB_COPRO  (1<<14)

+#define SYS_CTRL_DISABLE_BB_CP2_REG (1<<15)

+#define SYS_CTRL_DISABLE_BB_XCOR   (1<<16)

+#define SYS_CTRL_DISABLE_BB_EVITAC (1<<17)

+#define SYS_CTRL_DISABLE_BB_ROM    (1<<18)

+#define SYS_CTRL_DISABLE_BB_MPMC   (1<<19)

+#define SYS_CTRL_DISABLE_BB_VTB    (1<<20)

+#define SYS_CTRL_DISABLE_BB_IRQ    (1<<21)

+#define SYS_CTRL_DISABLE_BB_COM_REGS (1<<22)

+#define SYS_CTRL_DISABLE_BB_CORDIC (1<<23)

+#define SYS_CTRL_DISABLE_BB_DP     (1<<24)

+#define SYS_CTRL_DISABLE_CLK_BB(n) (((n)&0x1FFFFFF)<<0)

+#define SYS_CTRL_DISABLE_CLK_BB_MASK (0x1FFFFFF<<0)

+#define SYS_CTRL_DISABLE_CLK_BB_SHIFT (0)

+

+//Clk_Other_Mode

+#define SYS_CTRL_MODE_OC_DEBUG_UART_AUTOMATIC (0<<0)

+#define SYS_CTRL_MODE_OC_DEBUG_UART_MANUAL (1<<0)

+#define SYS_CTRL_MODE_OC_RF_RX_AUTOMATIC (0<<1)

+#define SYS_CTRL_MODE_OC_RF_RX_MANUAL (1<<1)

+#define SYS_CTRL_MODE_OC_RF_TX_AUTOMATIC (0<<2)

+#define SYS_CTRL_MODE_OC_RF_TX_MANUAL (1<<2)

+#define SYS_CTRL_MODE_OC_MEM_BRIDGE_AUTOMATIC (0<<3)

+#define SYS_CTRL_MODE_OC_MEM_BRIDGE_MANUAL (1<<3)

+#define SYS_CTRL_MODE_CLK_OTHER(n) (((n)&15)<<0)

+#define SYS_CTRL_MODE_CLK_OTHER_MASK (15<<0)

+#define SYS_CTRL_MODE_CLK_OTHER_SHIFT (0)

+

+//Clk_Other_Enable

+#define SYS_CTRL_ENABLE_OC_DEBUG_UART (1<<0)

+#define SYS_CTRL_ENABLE_OC_RF_RX   (1<<1)

+#define SYS_CTRL_ENABLE_OC_RF_TX   (1<<2)

+#define SYS_CTRL_ENABLE_OC_MEM_BRIDGE (1<<3)

+#define SYS_CTRL_ENABLE_OC_LPS     (1<<4)

+#define SYS_CTRL_ENABLE_OC_GPIO    (1<<5)

+#define SYS_CTRL_ENABLE_OC_CLK_OUT (1<<6)

+#define SYS_CTRL_ENABLE_OC_MEM_CLK_OUT (1<<7)

+#define SYS_CTRL_ENABLE_OC_TCU     (1<<8)

+#define SYS_CTRL_ENABLE_OC_WD_CHIP (1<<9)

+#define SYS_CTRL_ENABLE_OC_WD_ADC  (1<<10)

+#define SYS_CTRL_ENABLE_OC_WD_TURBO (1<<11)

+#define SYS_CTRL_ENABLE_OC_WD_OSC  (1<<12)

+#define SYS_CTRL_ENABLE_OC_MPMC    (1<<13)

+#define SYS_CTRL_ENABLE_OC_BB_VTB  (1<<14)

+#define SYS_CTRL_ENABLE_CLK_OTHER(n) (((n)&0x7FFF)<<0)

+#define SYS_CTRL_ENABLE_CLK_OTHER_MASK (0x7FFF<<0)

+#define SYS_CTRL_ENABLE_CLK_OTHER_SHIFT (0)

+

+//Clk_Other_Disable

+#define SYS_CTRL_DISABLE_OC_DEBUG_UART (1<<0)

+#define SYS_CTRL_DISABLE_OC_RF_RX  (1<<1)

+#define SYS_CTRL_DISABLE_OC_RF_TX  (1<<2)

+#define SYS_CTRL_DISABLE_OC_MEM_BRIDGE (1<<3)

+#define SYS_CTRL_DISABLE_OC_LPS    (1<<4)

+#define SYS_CTRL_DISABLE_OC_GPIO   (1<<5)

+#define SYS_CTRL_DISABLE_OC_CLK_OUT (1<<6)

+#define SYS_CTRL_DISABLE_OC_MEM_CLK_OUT (1<<7)

+#define SYS_CTRL_DISABLE_OC_TCU    (1<<8)

+#define SYS_CTRL_DISABLE_OC_WD_CHIP (1<<9)

+#define SYS_CTRL_DISABLE_OC_WD_ADC (1<<10)

+#define SYS_CTRL_DISABLE_OC_WD_TURBO (1<<11)

+#define SYS_CTRL_DISABLE_OC_WD_OSC (1<<12)

+#define SYS_CTRL_DISABLE_OC_MPMC   (1<<13)

+#define SYS_CTRL_DISABLE_OC_BB_VTB (1<<14)

+#define SYS_CTRL_DISABLE_CLK_OTHER(n) (((n)&0x7FFF)<<0)

+#define SYS_CTRL_DISABLE_CLK_OTHER_MASK (0x7FFF<<0)

+#define SYS_CTRL_DISABLE_CLK_OTHER_SHIFT (0)

+

+//Pll_Ctrl

+#define SYS_CTRL_PLL_ENABLE        (1<<0)

+#define SYS_CTRL_PLL_ENABLE_MASK   (1<<0)

+#define SYS_CTRL_PLL_ENABLE_SHIFT  (0)

+#define SYS_CTRL_PLL_ENABLE_POWER_DOWN (0<<0)

+#define SYS_CTRL_PLL_ENABLE_ENABLE (1<<0)

+#define SYS_CTRL_PLL_LOCK_RESET    (1<<4)

+#define SYS_CTRL_PLL_LOCK_RESET_MASK (1<<4)

+#define SYS_CTRL_PLL_LOCK_RESET_SHIFT (4)

+#define SYS_CTRL_PLL_LOCK_RESET_RESET (0<<4)

+#define SYS_CTRL_PLL_LOCK_RESET_NO_RESET (1<<4)

+#define SYS_CTRL_PLL_BYPASS        (1<<8)

+#define SYS_CTRL_PLL_BYPASS_MASK   (1<<8)

+#define SYS_CTRL_PLL_BYPASS_SHIFT  (8)

+#define SYS_CTRL_PLL_BYPASS_PASS   (0<<8)

+#define SYS_CTRL_PLL_BYPASS_BYPASS (1<<8)

+#define SYS_CTRL_PLL_CLK_FAST_ENABLE (1<<12)

+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_MASK (1<<12)

+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_SHIFT (12)

+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_ENABLE (1<<12)

+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_DISABLE (0<<12)

+#define SYS_CTRL_PLL_XP_CFG(n)     (((n)&4369)<<0)

+#define SYS_CTRL_PLL_XP_CFG_MASK   (4369<<0)

+#define SYS_CTRL_PLL_XP_CFG_SHIFT  (0)

+

+//Sel_Clock

+#define SYS_CTRL_SLOW_SEL_RF_OSCILLATOR (1<<0)

+#define SYS_CTRL_SLOW_SEL_RF_RF    (0<<0)

+#define SYS_CTRL_SYS_SEL_FAST_SLOW (1<<4)

+#define SYS_CTRL_SYS_SEL_FAST_FAST (0<<4)

+#define SYS_CTRL_TCU_13M_L_26M     (1<<5)

+#define SYS_CTRL_TCU_13M_L_13M     (0<<5)

+#define SYS_CTRL_PLL_DISABLE_LPS_DISABLE (1<<6)

+#define SYS_CTRL_PLL_DISABLE_LPS_ENABLE (0<<6)

+#define SYS_CTRL_DIGEN_H_ENABLE    (1<<7)

+#define SYS_CTRL_DIGEN_H_DISABLE   (0<<7)

+#define SYS_CTRL_RF_DETECTED_OK    (1<<20)

+#define SYS_CTRL_RF_DETECTED_NO    (0<<20)

+#define SYS_CTRL_RF_DETECT_BYPASS  (1<<21)

+#define SYS_CTRL_RF_DETECT_RESET   (1<<22)

+#define SYS_CTRL_RF_SELECTED_L     (1<<23)

+#define SYS_CTRL_PLL_LOCKED        (1<<24)

+#define SYS_CTRL_PLL_LOCKED_MASK   (1<<24)

+#define SYS_CTRL_PLL_LOCKED_SHIFT  (24)

+#define SYS_CTRL_PLL_LOCKED_LOCKED (1<<24)

+#define SYS_CTRL_PLL_LOCKED_NOT_LOCKED (0<<24)

+#define SYS_CTRL_PLL_BYPASS_LOCK   (1<<27)

+#define SYS_CTRL_FAST_SELECTED_L   (1<<31)

+#define SYS_CTRL_FAST_SELECTED_L_MASK (1<<31)

+#define SYS_CTRL_FAST_SELECTED_L_SHIFT (31)

+

+//Cfg_Clk_Sys

+#define SYS_CTRL_FREQ(n)           (((n)&15)<<0)

+#define SYS_CTRL_FREQ_MASK         (15<<0)

+#define SYS_CTRL_FREQ_SHIFT        (0)

+#define SYS_CTRL_FREQ_312M         (13<<0)

+#define SYS_CTRL_FREQ_250M         (12<<0)

+#define SYS_CTRL_FREQ_208M         (11<<0)

+#define SYS_CTRL_FREQ_178M         (10<<0)

+#define SYS_CTRL_FREQ_156M         (9<<0)

+#define SYS_CTRL_FREQ_139M         (8<<0)

+#define SYS_CTRL_FREQ_125M         (7<<0)

+#define SYS_CTRL_FREQ_113M         (6<<0)

+#define SYS_CTRL_FREQ_104M         (5<<0)

+#define SYS_CTRL_FREQ_89M          (4<<0)

+#define SYS_CTRL_FREQ_78M          (3<<0)

+#define SYS_CTRL_FREQ_52M          (2<<0)

+#define SYS_CTRL_FREQ_39M          (1<<0)

+#define SYS_CTRL_FREQ_26M          (0<<0)

+#define SYS_CTRL_FORCE_DIV_UPDATE  (1<<4)

+#define SYS_CTRL_REQ_DIV_UPDATE    (1<<8)

+

+//Cfg_Clk_Mem_Bridge

+#define SYS_CTRL_MEM_FREQ(n)       (((n)&15)<<0)

+#define SYS_CTRL_MEM_FREQ_MASK     (15<<0)

+#define SYS_CTRL_MEM_FREQ_SHIFT    (0)

+#define SYS_CTRL_MEM_FREQ_312M     (13<<0)

+#define SYS_CTRL_MEM_FREQ_250M     (12<<0)

+#define SYS_CTRL_MEM_FREQ_208M     (11<<0)

+#define SYS_CTRL_MEM_FREQ_178M     (10<<0)

+#define SYS_CTRL_MEM_FREQ_156M     (9<<0)

+#define SYS_CTRL_MEM_FREQ_139M     (8<<0)

+#define SYS_CTRL_MEM_FREQ_125M     (7<<0)

+#define SYS_CTRL_MEM_FREQ_113M     (6<<0)

+#define SYS_CTRL_MEM_FREQ_104M     (5<<0)

+#define SYS_CTRL_MEM_FREQ_89M      (4<<0)

+#define SYS_CTRL_MEM_FREQ_78M      (3<<0)

+#define SYS_CTRL_MEM_FREQ_52M      (2<<0)

+#define SYS_CTRL_MEM_FREQ_39M      (1<<0)

+#define SYS_CTRL_MEM_FREQ_26M      (0<<0)

+#define SYS_CTRL_DDR_MODE_EN_NORMAL_MODE (0<<4)

+#define SYS_CTRL_DDR_MODE_EN_DDR_MODE (1<<4)

+#define SYS_CTRL_DDR_FAST_CLK_POL_INVERT (1<<5)

+#define SYS_CTRL_DDR_FAST_CLK_POL_NORMAL (0<<5)

+#define SYS_CTRL_DDR_DQSL_O(n)     (((n)&31)<<6)

+#define SYS_CTRL_DDR_DQSU_O(n)     (((n)&31)<<11)

+#define SYS_CTRL_DDR_DQS_OEN(n)    (((n)&31)<<16)

+#define SYS_CTRL_DDR_DQSL_I(n)     (((n)&31)<<21)

+#define SYS_CTRL_DDR_DQSU_I(n)     (((n)&31)<<26)

+#define SYS_CTRL_MEM_REQ_DIV_UPDATE (1<<31)

+

+//Cfg_Clk_Out

+#define SYS_CTRL_CLKOUT_DIVIDER(n) (((n)&31)<<0)

+#define SYS_CTRL_CLKOUT_SEL_OSC    (0<<8)

+#define SYS_CTRL_CLKOUT_SEL_RF     (1<<8)

+#define SYS_CTRL_CLKOUT_SEL_DIVIDER (2<<8)

+

+//Cfg_Clk_Host_Uart

+#define SYS_CTRL_HOST_UART_DIVIDER(n) (((n)&0x3FF)<<0)

+#define SYS_CTRL_HOST_UART_DIVIDER_MASK (0x3FF<<0)

+#define SYS_CTRL_HOST_UART_DIVIDER_SHIFT (0)

+#define SYS_CTRL_HOST_UART_SEL_PLL_SLOW (0<<12)

+#define SYS_CTRL_HOST_UART_SEL_PLL_PLL (1<<12)

+

+//Cfg_Clk_Auxclk

+#define SYS_CTRL_AUXCLK_EN_DISABLE (0<<0)

+#define SYS_CTRL_AUXCLK_EN_ENABLE  (1<<0)

+

+//Cfg_AHB

+#define SYS_CTRL_SYS_NEW_ARBITRATION_ENABLE (1<<0)

+#define SYS_CTRL_SYS_NEW_ARBITRATION_DISABLE (0<<0)

+#define SYS_CTRL_ENABLE_SYS_MID_DMA_ENABLE (1<<1)

+#define SYS_CTRL_ENABLE_SYS_MID_DMA_DISABLE (0<<1)

+#define SYS_CTRL_ENABLE_SYS_MID_XCPU_ENABLE (1<<2)

+#define SYS_CTRL_ENABLE_SYS_MID_XCPU_DISABLE (0<<2)

+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_ENABLE (1<<3)

+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_DISABLE (0<<3)

+#define SYS_CTRL_ENABLE_SYS_MID_IFC_ENABLE (1<<4)

+#define SYS_CTRL_ENABLE_SYS_MID_IFC_DISABLE (0<<4)

+#define SYS_CTRL_ENABLE_SYS_MID_AXI2AHB_ENABLE (1<<5)

+#define SYS_CTRL_ENABLE_SYS_MID_AXI2AHB_DISABLE (0<<5)

+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_WD_ENABLE (1<<6)

+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_WD_DISABLE (0<<6)

+#define SYS_CTRL_ENABLE_SYS_MID_DMA2_ENABLE (1<<7)

+#define SYS_CTRL_ENABLE_SYS_MID_DMA2_DISABLE (0<<7)

+#define SYS_CTRL_BB_NEW_ARBITRATION_ENABLE (1<<16)

+#define SYS_CTRL_BB_NEW_ARBITRATION_DISABLE (0<<16)

+#define SYS_CTRL_ENABLE_BB_MID_IFC_ENABLE (1<<17)

+#define SYS_CTRL_ENABLE_BB_MID_IFC_DISABLE (0<<17)

+#define SYS_CTRL_ENABLE_BB_MID_BCPU_ENABLE (1<<18)

+#define SYS_CTRL_ENABLE_BB_MID_BCPU_DISABLE (0<<18)

+#define SYS_CTRL_ENABLE_BB_MID_AHB2AHB_ENABLE (1<<19)

+#define SYS_CTRL_ENABLE_BB_MID_AHB2AHB_DISABLE (0<<19)

+#define SYS_CTRL_SYS_ENABLE(n)     (((n)&0x7F)<<1)

+#define SYS_CTRL_SYS_ENABLE_MASK   (0x7F<<1)

+#define SYS_CTRL_SYS_ENABLE_SHIFT  (1)

+#define SYS_CTRL_BB_ENABLE(n)      (((n)&7)<<17)

+#define SYS_CTRL_BB_ENABLE_MASK    (7<<17)

+#define SYS_CTRL_BB_ENABLE_SHIFT   (17)

+

+//Ctrl_AHB

+#define SYS_CTRL_SPLIT_SYS_MID_DMA_NORMAL (1<<0)

+#define SYS_CTRL_SPLIT_SYS_MID_DMA_FORCE (0<<0)

+#define SYS_CTRL_SPLIT_SYS_MID_XCPU_NORMAL (1<<1)

+#define SYS_CTRL_SPLIT_SYS_MID_XCPU_FORCE (0<<1)

+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_NORMAL (1<<2)

+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_FORCE (0<<2)

+#define SYS_CTRL_SPLIT_SYS_MID_IFC_NORMAL (1<<3)

+#define SYS_CTRL_SPLIT_SYS_MID_IFC_FORCE (0<<3)

+#define SYS_CTRL_SPLIT_SYS_MID_AXI2AHB_NORMAL (1<<4)

+#define SYS_CTRL_SPLIT_SYS_MID_AXI2AHB_FORCE (0<<4)

+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_WD_NORMAL (1<<5)

+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_WD_FORCE (0<<5)

+#define SYS_CTRL_SPLIT_SYS_MID_DMA2_NORMAL (1<<6)

+#define SYS_CTRL_SPLIT_SYS_MID_DMA2_FORCE (0<<6)

+#define SYS_CTRL_SPLIT_BB_MID_IFC_NORMAL (1<<16)

+#define SYS_CTRL_SPLIT_BB_MID_IFC_FORCE (0<<16)

+#define SYS_CTRL_SPLIT_BB_MID_BCPU_NORMAL (1<<17)

+#define SYS_CTRL_SPLIT_BB_MID_BCPU_FORCE (0<<17)

+#define SYS_CTRL_SPLIT_BB_MID_AHB2AHB_NORMAL (1<<18)

+#define SYS_CTRL_SPLIT_BB_MID_AHB2AHB_FORCE (0<<18)

+#define SYS_CTRL_SYS_FORCE_HSPLIT(n) (((n)&0x7F)<<0)

+#define SYS_CTRL_SYS_FORCE_HSPLIT_MASK (0x7F<<0)

+#define SYS_CTRL_SYS_FORCE_HSPLIT_SHIFT (0)

+#define SYS_CTRL_BB_FORCE_HSPLIT(n) (((n)&7)<<16)

+#define SYS_CTRL_BB_FORCE_HSPLIT_MASK (7<<16)

+#define SYS_CTRL_BB_FORCE_HSPLIT_SHIFT (16)

+

+//XCpu_Dbg_BKP

+#define SYS_CTRL_BKPT_EN           (1<<0)

+#define SYS_CTRL_BKPT_MODE(n)      (((n)&3)<<4)

+#define SYS_CTRL_BKPT_MODE_I       (0<<4)

+#define SYS_CTRL_BKPT_MODE_R       (1<<4)

+#define SYS_CTRL_BKPT_MODE_W       (2<<4)

+#define SYS_CTRL_BKPT_MODE_RW      (3<<4)

+#define SYS_CTRL_STALLED           (1<<8)

+

+//XCpu_Dbg_Addr

+#define SYS_CTRL_BREAKPOINT_ADDRESS(n) (((n)&0x3FFFFFF)<<0)

+

+//BCpu_Dbg_BKP

+//#define SYS_CTRL_BKPT_EN         (1<<0)

+//#define SYS_CTRL_BKPT_MODE(n)    (((n)&3)<<4)

+//#define SYS_CTRL_BKPT_MODE_I     (0<<4)

+//#define SYS_CTRL_BKPT_MODE_R     (1<<4)

+//#define SYS_CTRL_BKPT_MODE_W     (2<<4)

+//#define SYS_CTRL_BKPT_MODE_RW    (3<<4)

+//#define SYS_CTRL_STALLED         (1<<8)

+

+//BCpu_Dbg_Addr

+//#define SYS_CTRL_BREAKPOINT_ADDRESS(n) (((n)&0x3FFFFFF)<<0)

+

+//Cfg_Cpus_Cache_Ram_Disable

+#define SYS_CTRL_XCPU_USE_MODE     (1<<0)

+#define SYS_CTRL_XCPU_CLK_OFF_MODE (1<<1)

+#define SYS_CTRL_BCPU_USE_MODE     (1<<16)

+#define SYS_CTRL_BCPU_CLK_OFF_MODE (1<<17)

+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE(n) (((n)&3)<<0)

+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE_MASK (3<<0)

+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE_SHIFT (0)

+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE(n) (((n)&3)<<16)

+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE_MASK (3<<16)

+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE_SHIFT (16)

+

+//Reset_Cause

+#define SYS_CTRL_WATCHDOG_RESET_HAPPENED (1<<0)

+#define SYS_CTRL_WATCHDOG_RESET_NO (0<<0)

+#define SYS_CTRL_APSOFT_RESET_HAPPENED (1<<1)

+#define SYS_CTRL_APSOFT_RESET_NO   (0<<1)

+#define SYS_CTRL_GLOBALSOFT_RESET_HAPPENED (1<<4)

+#define SYS_CTRL_GLOBALSOFT_RESET_NO (0<<4)

+#define SYS_CTRL_HOSTDEBUG_RESET_HAPPENED (1<<5)

+#define SYS_CTRL_HOSTDEBUG_RESET_NO (0<<5)

+#define SYS_CTRL_ALARMCAUSE_HAPPENED (1<<6)

+#define SYS_CTRL_ALARMCAUSE_NO     (0<<6)

+#define SYS_CTRL_MEMCHECKDONE_MASK (1<<7)

+#define SYS_CTRL_MEMCHECKDONE_SHIFT (7)

+#define SYS_CTRL_MEMCHECKDONE_DONE (1<<7)

+#define SYS_CTRL_MEMCHECKDONE_RUNNING (0<<7)

+#define SYS_CTRL_BOOT_MODE(n)      (((n)&0xFFFF)<<8)

+#define SYS_CTRL_BOOT_MODE_MASK    (0xFFFF<<8)

+#define SYS_CTRL_BOOT_MODE_SHIFT   (8)

+#define SYS_CTRL_SW_BOOT_MODE(n)   (((n)&0x7F)<<24)

+#define SYS_CTRL_SW_BOOT_MODE_MASK (0x7F<<24)

+#define SYS_CTRL_SW_BOOT_MODE_SHIFT (24)

+#define SYS_CTRL_FONCTIONAL_TEST_MODE (1<<31)

+

+//WakeUp

+#define SYS_CTRL_FORCE_WAKEUP      (1<<0)

+

+//AP_Ctrl

+#define SYS_CTRL_AP_INT_STATUS     (1<<0)

+#define SYS_CTRL_AP_INT_MASK       (1<<16)

+#define SYS_CTRL_AP_DEEPSLEEP_EN   (1<<24)

+

+//Ignore_Charger

+#define SYS_CTRL_IGNORE_CHARGER    (1<<0)

+

+//Clk_SYS2_Mode

+#define SYS_CTRL_MODE_SYS_MPMC_AUTOMATIC (0<<0)

+#define SYS_CTRL_MODE_SYS_MPMC_MANUAL (1<<0)

+#define SYS_CTRL_MODE_SYS_MPMCREG_AUTOMATIC (0<<1)

+#define SYS_CTRL_MODE_SYS_MPMCREG_MANUAL (1<<1)

+#define SYS_CTRL_MODE_CLK_SYS2(n)  (((n)&3)<<0)

+#define SYS_CTRL_MODE_CLK_SYS2_MASK (3<<0)

+#define SYS_CTRL_MODE_CLK_SYS2_SHIFT (0)

+

+//Clk_SYS2_Enable

+#define SYS_CTRL_ENABLE_SYS_MPMC   (1<<0)

+#define SYS_CTRL_ENABLE_SYS_MPMCREG (1<<1)

+#define SYS_CTRL_ENABLE_SYS_DP_BB  (1<<2)

+#define SYS_CTRL_ENABLE_SYS_DP_WD  (1<<3)

+#define SYS_CTRL_ENABLE_SYS_DP_AP  (1<<4)

+#define SYS_CTRL_ENABLE_CLK_SYS2(n) (((n)&31)<<0)

+#define SYS_CTRL_ENABLE_CLK_SYS2_MASK (31<<0)

+#define SYS_CTRL_ENABLE_CLK_SYS2_SHIFT (0)

+

+//Clk_SYS2_Disable

+#define SYS_CTRL_DISABLE_SYS_MPMC  (1<<0)

+#define SYS_CTRL_DISABLE_SYS_MPMCREG (1<<1)

+#define SYS_CTRL_DISABLE_SYS_DP_BB (1<<2)

+#define SYS_CTRL_DISABLE_SYS_DP_WD (1<<3)

+#define SYS_CTRL_DISABLE_SYS_DP_AP (1<<4)

+#define SYS_CTRL_DISABLE_CLK_SYS2(n) (((n)&31)<<0)

+#define SYS_CTRL_DISABLE_CLK_SYS2_MASK (31<<0)

+#define SYS_CTRL_DISABLE_CLK_SYS2_SHIFT (0)

+

+//WD_Pll_Ctrl

+#define SYS_CTRL_WD_PLL_ENABLE     (1<<0)

+#define SYS_CTRL_WD_PLL_ENABLE_MASK (1<<0)

+#define SYS_CTRL_WD_PLL_ENABLE_SHIFT (0)

+#define SYS_CTRL_WD_PLL_ENABLE_POWER_DOWN (0<<0)

+#define SYS_CTRL_WD_PLL_ENABLE_ENABLE (1<<0)

+#define SYS_CTRL_WD_PLL_LOCK_RESET (1<<4)

+#define SYS_CTRL_WD_PLL_LOCK_RESET_MASK (1<<4)

+#define SYS_CTRL_WD_PLL_LOCK_RESET_SHIFT (4)

+#define SYS_CTRL_WD_PLL_LOCK_RESET_RESET (0<<4)

+#define SYS_CTRL_WD_PLL_LOCK_RESET_NO_RESET (1<<4)

+#define SYS_CTRL_WD_PLL_BYPASS     (1<<8)

+#define SYS_CTRL_WD_PLL_BYPASS_MASK (1<<8)

+#define SYS_CTRL_WD_PLL_BYPASS_SHIFT (8)

+#define SYS_CTRL_WD_PLL_BYPASS_PASS (0<<8)

+#define SYS_CTRL_WD_PLL_BYPASS_BYPASS (1<<8)

+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE (1<<12)

+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE_MASK (1<<12)

+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE_SHIFT (12)

+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE_ENABLE (1<<12)

+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE_DISABLE (0<<12)

+#define SYS_CTRL_PLL_WD_CFG(n)     (((n)&4369)<<0)

+#define SYS_CTRL_PLL_WD_CFG_MASK   (4369<<0)

+#define SYS_CTRL_PLL_WD_CFG_SHIFT  (0)

+

+//WD_Sel_Clock

+#define SYS_CTRL_WD_CLK_ADC_POL_INVERT (1<<0)

+#define SYS_CTRL_WD_CLK_ADC_POL_NORMAL (0<<0)

+#define SYS_CTRL_WD_SYS_SEL_FAST_SLOW (1<<4)

+#define SYS_CTRL_WD_SYS_SEL_FAST_FAST (0<<4)

+#define SYS_CTRL_WD_PLL_BYPASS_LOCK (1<<8)

+#define SYS_CTRL_WD_PLL_LOCKED     (1<<20)

+#define SYS_CTRL_WD_PLL_LOCKED_MASK (1<<20)

+#define SYS_CTRL_WD_PLL_LOCKED_SHIFT (20)

+#define SYS_CTRL_WD_PLL_LOCKED_LOCKED (1<<20)

+#define SYS_CTRL_WD_PLL_LOCKED_NOT_LOCKED (0<<20)

+#define SYS_CTRL_WD_FAST_SELECTED_L (1<<24)

+#define SYS_CTRL_WD_FAST_SELECTED_L_MASK (1<<24)

+#define SYS_CTRL_WD_FAST_SELECTED_L_SHIFT (24)

+

+//WD_Rst_Set

+#define SYS_CTRL_SET_WD_RST_WCPU   (1<<0)

+#define SYS_CTRL_SET_WD_RST_IRQ    (1<<1)

+#define SYS_CTRL_SET_WD_RST_DP     (1<<2)

+#define SYS_CTRL_SET_WD_RST_MODEM  (1<<3)

+#define SYS_CTRL_SET_WD_RST_A2A    (1<<4)

+#define SYS_CTRL_SET_WD_RST_IFC    (1<<5)

+#define SYS_CTRL_SET_WD_RST_SDMA   (1<<6)

+#define SYS_CTRL_SET_WD_RST_SLPC   (1<<7)

+#define SYS_CTRL_SET_WD_RST_SLPT   (1<<8)

+#define SYS_CTRL_SET_WD_RST_SPI1   (1<<9)

+#define SYS_CTRL_SET_WD_RST_SPI2   (1<<10)

+#define SYS_CTRL_SET_WD_RST_RFIF   (1<<11)

+#define SYS_CTRL_SET_WD_RST_COMREGS (1<<12)

+#define SYS_CTRL_SET_WD_RST_TIMER  (1<<13)

+#define SYS_CTRL_SET_WD_RST_MPMC   (1<<14)

+#define SYS_CTRL_SET_WD_RST_EXT_AHB (1<<15)

+#define SYS_CTRL_SET_WD_RST_PAGE_SPY (1<<16)

+#define SYS_CTRL_SET_WD_RST_FULL   (1<<31)

+#define SYS_CTRL_SET_WD_RST(n)     (((n)&0x1FFFF)<<0)

+#define SYS_CTRL_SET_WD_RST_MASK   (0x1FFFF<<0)

+#define SYS_CTRL_SET_WD_RST_SHIFT  (0)

+

+//WD_Rst_Clr

+#define SYS_CTRL_CLR_WD_RST_WCPU   (1<<0)

+#define SYS_CTRL_CLR_WD_RST_IRQ    (1<<1)

+#define SYS_CTRL_CLR_WD_RST_DP     (1<<2)

+#define SYS_CTRL_CLR_WD_RST_MODEM  (1<<3)

+#define SYS_CTRL_CLR_WD_RST_A2A    (1<<4)

+#define SYS_CTRL_CLR_WD_RST_IFC    (1<<5)

+#define SYS_CTRL_CLR_WD_RST_SDMA   (1<<6)

+#define SYS_CTRL_CLR_WD_RST_SLPC   (1<<7)

+#define SYS_CTRL_CLR_WD_RST_SLPT   (1<<8)

+#define SYS_CTRL_CLR_WD_RST_SPI1   (1<<9)

+#define SYS_CTRL_CLR_WD_RST_SPI2   (1<<10)

+#define SYS_CTRL_CLR_WD_RST_RFIF   (1<<11)

+#define SYS_CTRL_CLR_WD_RST_COMREGS (1<<12)

+#define SYS_CTRL_CLR_WD_RST_TIMER  (1<<13)

+#define SYS_CTRL_CLR_WD_RST_MPMC   (1<<14)

+#define SYS_CTRL_CLR_WD_RST_EXT_AHB (1<<15)

+#define SYS_CTRL_CLR_WD_RST_PAGE_SPY (1<<16)

+#define SYS_CTRL_CLR_WD_RST_FULL   (1<<31)

+#define SYS_CTRL_CLR_WD_RST(n)     (((n)&0x1FFFF)<<0)

+#define SYS_CTRL_CLR_WD_RST_MASK   (0x1FFFF<<0)

+#define SYS_CTRL_CLR_WD_RST_SHIFT  (0)

+

+//AP_Rst_Set

+#define SYS_CTRL_SET_AP_RST_0      (1<<0)

+#define SYS_CTRL_SET_AP_RST_1      (1<<1)

+#define SYS_CTRL_SET_AP_RST_2      (1<<2)

+#define SYS_CTRL_SET_AP_RST_3      (1<<3)

+#define SYS_CTRL_SET_AP_RST_4      (1<<4)

+#define SYS_CTRL_SET_AP_RST(n)     (((n)&31)<<0)

+#define SYS_CTRL_SET_AP_RST_MASK   (31<<0)

+#define SYS_CTRL_SET_AP_RST_SHIFT  (0)

+

+//AP_Rst_Clr

+#define SYS_CTRL_CLR_AP_RST_0      (1<<0)

+#define SYS_CTRL_CLR_AP_RST_1      (1<<1)

+#define SYS_CTRL_CLR_AP_RST_2      (1<<2)

+#define SYS_CTRL_CLR_AP_RST_3      (1<<3)

+#define SYS_CTRL_CLR_AP_RST_4      (1<<4)

+#define SYS_CTRL_CLR_AP_RST(n)     (((n)&31)<<0)

+#define SYS_CTRL_CLR_AP_RST_MASK   (31<<0)

+#define SYS_CTRL_CLR_AP_RST_SHIFT  (0)

+

+//Clk_WD_Mode

+#define SYS_CTRL_MODE_WD_WCPU      (1<<0)

+#define SYS_CTRL_MODE_WD_AMBA_AUTOMATIC (0<<1)

+#define SYS_CTRL_MODE_WD_AMBA_MANUAL (1<<1)

+#define SYS_CTRL_MODE_WD_PCLK_CONF_AUTOMATIC (0<<2)

+#define SYS_CTRL_MODE_WD_PCLK_CONF_MANUAL (1<<2)

+#define SYS_CTRL_MODE_WD_PCLK_DATA_AUTOMATIC (0<<3)

+#define SYS_CTRL_MODE_WD_PCLK_DATA_MANUAL (1<<3)

+#define SYS_CTRL_MODE_WD_A2A_AUTOMATIC (0<<4)

+#define SYS_CTRL_MODE_WD_A2A_MANUAL (1<<4)

+#define SYS_CTRL_MODE_WD_IFC_CH_SPI_AUTOMATIC (0<<5)

+#define SYS_CTRL_MODE_WD_IFC_CH_SPI_MANUAL (1<<5)

+#define SYS_CTRL_MODE_WD_MPMC_AUTOMATIC (0<<6)

+#define SYS_CTRL_MODE_WD_MPMC_MANUAL (1<<6)

+#define SYS_CTRL_MODE_WD_EXT_AHB_AUTOMATIC (0<<7)

+#define SYS_CTRL_MODE_WD_EXT_AHB_MANUAL (1<<7)

+#define SYS_CTRL_MODE_WDD_OSC_AUTOMATIC (0<<8)

+#define SYS_CTRL_MODE_WDD_OSC_MANUAL (1<<8)

+#define SYS_CTRL_MODE_CLK_WD(n)    (((n)&0xFF)<<1)

+#define SYS_CTRL_MODE_CLK_WD_MASK  (0xFF<<1)

+#define SYS_CTRL_MODE_CLK_WD_SHIFT (1)

+

+//Clk_WD_Enable

+#define SYS_CTRL_ENABLE_WD_WCPU    (1<<0)

+#define SYS_CTRL_ENABLE_WD_AMBA    (1<<1)

+#define SYS_CTRL_ENABLE_WD_PCLK_CONF (1<<2)

+#define SYS_CTRL_ENABLE_WD_PCLK_DATA (1<<3)

+#define SYS_CTRL_ENABLE_WD_A2A     (1<<4)

+#define SYS_CTRL_ENABLE_WD_IFC_CH_SPI (1<<5)

+#define SYS_CTRL_ENABLE_WD_MPMC    (1<<6)

+#define SYS_CTRL_ENABLE_WD_EXT_AHB (1<<7)

+#define SYS_CTRL_ENABLE_WDD_OSC    (1<<8)

+#define SYS_CTRL_ENABLE_WD_IRQ     (1<<9)

+#define SYS_CTRL_ENABLE_WD_AXI     (1<<10)

+#define SYS_CTRL_ENABLE_WD_DP      (1<<11)

+#define SYS_CTRL_ENABLE_WD_MODEM   (1<<12)

+#define SYS_CTRL_ENABLE_WD_COM_REGS (1<<13)

+#define SYS_CTRL_ENABLE_WD_TIMER   (1<<14)

+#define SYS_CTRL_ENABLE_WD_SDMA    (1<<15)

+#define SYS_CTRL_ENABLE_WD_SLPC    (1<<16)

+#define SYS_CTRL_ENABLE_WD_SLPT    (1<<17)

+#define SYS_CTRL_ENABLE_WD_SPI1    (1<<18)

+#define SYS_CTRL_ENABLE_WD_SPI2    (1<<19)

+#define SYS_CTRL_ENABLE_WD_RFIF    (1<<20)

+#define SYS_CTRL_ENABLE_WD_PAGE_SPY (1<<21)

+#define SYS_CTRL_ENABLE_CLK_WD(n)  (((n)&0x3FFFFF)<<0)

+#define SYS_CTRL_ENABLE_CLK_WD_MASK (0x3FFFFF<<0)

+#define SYS_CTRL_ENABLE_CLK_WD_SHIFT (0)

+

+//Clk_WD_Disable

+#define SYS_CTRL_DISABLE_WD_WCPU   (1<<0)

+#define SYS_CTRL_DISABLE_WD_AMBA   (1<<1)

+#define SYS_CTRL_DISABLE_WD_PCLK_CONF (1<<2)

+#define SYS_CTRL_DISABLE_WD_PCLK_DATA (1<<3)

+#define SYS_CTRL_DISABLE_WD_A2A    (1<<4)

+#define SYS_CTRL_DISABLE_WD_IFC_CH_SPI (1<<5)

+#define SYS_CTRL_DISABLE_WD_MPMC   (1<<6)

+#define SYS_CTRL_DISABLE_WD_EXT_AHB (1<<7)

+#define SYS_CTRL_DISABLE_WDD_OSC   (1<<8)

+#define SYS_CTRL_DISABLE_WD_IRQ    (1<<9)

+#define SYS_CTRL_DISABLE_WD_AXI    (1<<10)

+#define SYS_CTRL_DISABLE_WD_DP     (1<<11)

+#define SYS_CTRL_DISABLE_WD_MODEM  (1<<12)

+#define SYS_CTRL_DISABLE_WD_COM_REGS (1<<13)

+#define SYS_CTRL_DISABLE_WD_TIMER  (1<<14)

+#define SYS_CTRL_DISABLE_WD_SDMA   (1<<15)

+#define SYS_CTRL_DISABLE_WD_SLPC   (1<<16)

+#define SYS_CTRL_DISABLE_WD_SLPT   (1<<17)

+#define SYS_CTRL_DISABLE_WD_SPI1   (1<<18)

+#define SYS_CTRL_DISABLE_WD_SPI2   (1<<19)

+#define SYS_CTRL_DISABLE_WD_RFIF   (1<<20)

+#define SYS_CTRL_DISABLE_WD_PAGE_SPY (1<<21)

+#define SYS_CTRL_DISABLE_CLK_WD(n) (((n)&0x3FFFFF)<<0)

+#define SYS_CTRL_DISABLE_CLK_WD_MASK (0x3FFFFF<<0)

+#define SYS_CTRL_DISABLE_CLK_WD_SHIFT (0)

+

+//Cfg_Clk_MPMC

+#define SYS_CTRL_MPMC_FREQ(n)      (((n)&15)<<0)

+#define SYS_CTRL_MPMC_FREQ_MASK    (15<<0)

+#define SYS_CTRL_MPMC_FREQ_SHIFT   (0)

+#define SYS_CTRL_MPMC_FREQ_312M    (13<<0)

+#define SYS_CTRL_MPMC_FREQ_250M    (12<<0)

+#define SYS_CTRL_MPMC_FREQ_208M    (11<<0)

+#define SYS_CTRL_MPMC_FREQ_178M    (10<<0)

+#define SYS_CTRL_MPMC_FREQ_156M    (9<<0)

+#define SYS_CTRL_MPMC_FREQ_139M    (8<<0)

+#define SYS_CTRL_MPMC_FREQ_125M    (7<<0)

+#define SYS_CTRL_MPMC_FREQ_113M    (6<<0)

+#define SYS_CTRL_MPMC_FREQ_104M    (5<<0)

+#define SYS_CTRL_MPMC_FREQ_89M     (4<<0)

+#define SYS_CTRL_MPMC_FREQ_78M     (3<<0)

+#define SYS_CTRL_MPMC_FREQ_52M     (2<<0)

+#define SYS_CTRL_MPMC_FREQ_39M     (1<<0)

+#define SYS_CTRL_MPMC_FREQ_26M     (0<<0)

+#define SYS_CTRL_CLK_MPMC_DELAY(n) (((n)&31)<<8)

+#define SYS_CTRL_CLK_MPMC_DELAY_POL (1<<13)

+#define SYS_CTRL_CLK_MPMC_FEEDBACK(n) (((n)&31)<<14)

+#define SYS_CTRL_CLK_MPMC_FEEDBACK_POL (1<<19)

+#define SYS_CTRL_MPMC_REQ_DIV_UPDATE (1<<31)

+

+//Cfg_MPMC_DQS

+#define SYS_CTRL_MPMC_DQSL_O(n)    (((n)&31)<<0)

+#define SYS_CTRL_MPMC_DQSU_O(n)    (((n)&31)<<6)

+#define SYS_CTRL_MPMC_DQS_OEN(n)   (((n)&31)<<12)

+#define SYS_CTRL_MPMC_DQSL_I(n)    (((n)&31)<<18)

+#define SYS_CTRL_MPMC_DQSU_I(n)    (((n)&31)<<24)

+

+//Cfg_Clk_BB_VTB

+#define SYS_CTRL_BB_VTB_FREQ(n)    (((n)&15)<<0)

+#define SYS_CTRL_BB_VTB_FREQ_MASK  (15<<0)

+#define SYS_CTRL_BB_VTB_FREQ_SHIFT (0)

+#define SYS_CTRL_BB_VTB_FREQ_312M  (13<<0)

+#define SYS_CTRL_BB_VTB_FREQ_250M  (12<<0)

+#define SYS_CTRL_BB_VTB_FREQ_208M  (11<<0)

+#define SYS_CTRL_BB_VTB_FREQ_178M  (10<<0)

+#define SYS_CTRL_BB_VTB_FREQ_156M  (9<<0)

+#define SYS_CTRL_BB_VTB_FREQ_139M  (8<<0)

+#define SYS_CTRL_BB_VTB_FREQ_125M  (7<<0)

+#define SYS_CTRL_BB_VTB_FREQ_113M  (6<<0)

+#define SYS_CTRL_BB_VTB_FREQ_104M  (5<<0)

+#define SYS_CTRL_BB_VTB_FREQ_89M   (4<<0)

+#define SYS_CTRL_BB_VTB_FREQ_78M   (3<<0)

+#define SYS_CTRL_BB_VTB_FREQ_52M   (2<<0)

+#define SYS_CTRL_BB_VTB_FREQ_39M   (1<<0)

+#define SYS_CTRL_BB_VTB_FREQ_26M   (0<<0)

+#define SYS_CTRL_BB_VTB_REQ_DIV_UPDATE (1<<31)

+

+//Cfg_Reserve

+#define SYS_CTRL_RESERVE_L(n)      (((n)&0x3FFF)<<0)

+#define SYS_CTRL_AUIFC_CH0_IRQ_MASK (1<<14)

+#define SYS_CTRL_AUIFC_CH1_IRQ_MASK (1<<15)

+#define SYS_CTRL_RESERVE_H(n)      (((n)&0xFFFF)<<16)

+

+

+

+

+

+#endif

+

diff --git a/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8850.h b/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8850.h
new file mode 100644
index 0000000000..4afdaeea23
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8850.h
@@ -0,0 +1,1363 @@
+#ifndef _REG_MD_SYSCTRL_H_

+#define _REG_MD_SYSCTRL_H_

+

+#include <asm/arch/hardware.h>

+#include <asm/arch/rda_iomap.h>

+

+// =============================================================================

+//  MACROS

+// =============================================================================

+

+// ============================================================================

+// CPU_ID_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// CPU IDs

+    XCPU                                        = 0x00000000,

+    BCPU                                        = 0x00000001,

+    WCPU                                        = 0x00000002

+} CPU_ID_T;

+

+#define NB_MODEM_CPU                            (3)

+

+// ============================================================================

+// SYS_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// System side System clocks

+    SYS_XCPU                                    = 0x00000000,

+    SYS_XCPU_INT                                = 0x00000001,

+    SYS_PCLK_CONF                               = 0x00000002,

+    SYS_PCLK_DATA                               = 0x00000003,

+    SYS_AMBA                                    = 0x00000004,

+    SYS_DMA                                     = 0x00000005,

+    SYS_EBC                                     = 0x00000006,

+    SYS_IFC_CH0                                 = 0x00000007,

+    SYS_IFC_CH1                                 = 0x00000008,

+    SYS_IFC_CH2                                 = 0x00000009,

+    SYS_IFC_CH3                                 = 0x0000000A,

+    SYS_IFC_DBG                                 = 0x0000000B,

+    SYS_A2A                                     = 0x0000000C,

+    SYS_AXI2AHB                                 = 0x0000000D,

+    SYS_AHB2AXI                                 = 0x0000000E,

+    SYS_EXT_AHB                                 = 0x0000000F,

+    SYS_DEBUG_UART                              = 0x00000010,

+    SYS_DBGHST                                  = 0x00000011,

+    SYS_A2A_WD                                  = 0x00000012,

+/// System side divided clock (either divided by module or by sys_ctrl)

+    SYSD_SCI1                                   = 0x00000013,

+    SYSD_SCI2                                   = 0x00000014,

+    SYSD_SCI3                                   = 0x00000015,

+    SYSD_RF_SPI                                 = 0x00000016,

+    SYSD_OSC                                    = 0x00000017,

+/// the following don't have an auto enable

+    SYS_GPIO                                    = 0x00000018,

+    SYS_IRQ                                     = 0x00000019,

+    SYS_TCU                                     = 0x0000001A,

+    SYS_TIMER                                   = 0x0000001B,

+    SYS_COM_REGS                                = 0x0000001C,

+/// the following are sharing their enable

+    SYS_SCI1                                    = 0x0000001D,

+    SYS_SCI2                                    = 0x0000001E,

+    SYS_SCI3                                    = 0x0000001F,

+/// keep last

+    SYS_NOGATE                                  = 0x00000020

+} SYS_CLKS_T;

+

+#define NB_SYS_CLK_XCPU                         (2)

+#define NB_SYS_CLK_AEN                          (24)

+#define NB_SYS_CLK_EN                           (29)

+#define NB_SYS_CLK                              (33)

+

+// ============================================================================

+// SYS2_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// WCDMA Baseband side System clocks

+    SYS_MPMC                                    = 0x00000000,

+    SYS_MPMCREG                                 = 0x00000001,

+/// the following don't have an auto enable

+    SYS_DP_BB                                   = 0x00000002,

+    SYS_DP_WD                                   = 0x00000003,

+    SYS_DP_AP                                   = 0x00000004

+} SYS2_CLKS_T;

+

+#define NB_SYS2_CLK_AEN                         (2)

+#define NB_SYS2_CLK_EN                          (5)

+#define NB_SYS2_CLK                             (5)

+

+// ============================================================================

+// PER_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// System side divided clock (either divided by module or by sys_ctrl)

+    PERD_SPI1                                   = 0x00000000,

+/// System side divided clock (either divided by module or by sys_ctrl)

+    PERD_SPI2                                   = 0x00000001,

+    PER_SPY                                     = 0x00000002,

+    PER_TEST                                    = 0x00000003

+} PER_CLKS_T;

+

+#define NB_PER_CLK_AEN                          (2)

+#define NB_PER_CLK_EN                           (4)

+#define NB_PER_CLK                              (4)

+

+// ============================================================================

+// BB_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// Baseband side System clocks

+    BB_BCPU                                     = 0x00000000,

+    BB_BCPU_INT                                 = 0x00000001,

+    BB_AMBA                                     = 0x00000002,

+    BB_PCLK_CONF                                = 0x00000003,

+    BB_PCLK_DATA                                = 0x00000004,

+    BB_EXCOR                                    = 0x00000005,

+    BB_IFC_CH2                                  = 0x00000006,

+    BB_IFC_CH3                                  = 0x00000007,

+    BB_SRAM                                     = 0x00000008,

+    BB_A2A                                      = 0x00000009,

+    BB_ITLV                                     = 0x0000000A,

+    BB_VITERBI                                  = 0x0000000B,

+    BB_CIPHER                                   = 0x0000000C,

+    BB_RF_IF                                    = 0x0000000D,

+    BB_COPRO                                    = 0x0000000E,

+    BB_CP2_REG                                  = 0x0000000F,

+    BB_XCOR                                     = 0x00000010,

+    BB_EVITAC                                   = 0x00000011,

+    BB_ROM                                      = 0x00000012,

+    BB_MPMC                                     = 0x00000013,

+/// the following don't have an auto enable

+    BB_IRQ                                      = 0x00000014,

+    BB_COM_REGS                                 = 0x00000015,

+    BB_CORDIC                                   = 0x00000016,

+    BB_DP                                       = 0x00000017

+} BB_CLKS_T;

+

+#define NB_BB_CLK_AEN                           (20)

+#define NB_BB_CLK_EN                            (24)

+#define NB_BB_CLK                               (24)

+

+// ============================================================================

+// WD_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// WCDMA Baseband side System clocks

+    WD_WCPU                                     = 0x00000000,

+    WD_AMBA                                     = 0x00000001,

+    WD_PCLK_CONF                                = 0x00000002,

+    WD_PCLK_DATA                                = 0x00000003,

+    WD_A2A                                      = 0x00000004,

+    WD_IFC_CH_SPI                               = 0x00000005,

+    WD_MPMC                                     = 0x00000006,

+    WDD_OSC                                     = 0x00000007,

+/// the following don't have an auto enable

+    WD_IRQ                                      = 0x00000008,

+    WD_AXI                                      = 0x00000009,

+    WD_DP                                       = 0x0000000A,

+    WD_MODEM                                    = 0x0000000B,

+    WD_COM_REGS                                 = 0x0000000C,

+    WD_TIMER                                    = 0x0000000D,

+    WD_SDMA                                     = 0x0000000E,

+    WD_SLPC                                     = 0x0000000F,

+    WD_SLPT                                     = 0x00000010,

+    WD_SPI1                                     = 0x00000011,

+    WD_SPI2                                     = 0x00000012,

+    WD_RFIF                                     = 0x00000013

+} WD_CLKS_T;

+

+#define NB_WD_CLK_AEN                           (8)

+#define NB_WD_CLK_EN                            (20)

+#define NB_WD_CLK                               (20)

+/// Other clocks

+/// clocks with auto enble

+/// the debug host clock auto enable is not used in host mode, only in uart mode

+#define OC_HOST_UART                            (0)

+

+// ============================================================================

+// OTHER_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+    OC_DEBUG_UART                               = 0x00000000,

+    OC_RF_RX                                    = 0x00000001,

+    OC_RF_TX                                    = 0x00000002,

+    OC_MEM_BRIDGE                               = 0x00000003,

+/// the following don't have an auto enable

+    OC_LPS                                      = 0x00000004,

+    OC_GPIO                                     = 0x00000005,

+    OC_CLK_OUT                                  = 0x00000006,

+    OC_MEM_CLK_OUT                              = 0x00000007,

+    OC_TCU                                      = 0x00000008,

+    OC_WD_CHIP                                  = 0x00000009,

+    OC_WD_ADC                                   = 0x0000000A,

+    OC_WD_TURBO                                 = 0x0000000B,

+    OC_WD_OSC                                   = 0x0000000C,

+    OC_MPMC                                     = 0x0000000D

+} OTHER_CLKS_T;

+

+#define NB_OTHER_CLK_AEN                        (4)

+#define NB_OTHER_CLK_EN                         (14)

+#define NB_OTHER_CLK                            (14)

+

+// ============================================================================

+// RESETS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// System side resets

+    RST_XCPU                                    = 0x00000000,

+    RST_SYS_IRQ                                 = 0x00000001,

+    RST_SYS_A2A                                 = 0x00000002,

+    RST_SYS_AHB2AXI                             = 0x00000003,

+    RST_SYS_AXI2AHB                             = 0x00000004,

+    RST_DMA                                     = 0x00000005,

+    RST_TIMER                                   = 0x00000006,

+    RST_TCU                                     = 0x00000007,

+    RST_GPIO                                    = 0x00000008,

+    RST_CFG                                     = 0x00000009,

+    RST_SPI1                                    = 0x0000000A,

+    RST_SPI2                                    = 0x0000000B,

+    RST_RF_SPI                                  = 0x0000000C,

+    RST_SCI1                                    = 0x0000000D,

+    RST_SCI2                                    = 0x0000000E,

+    RST_SCI3                                    = 0x0000000F,

+    RST_SPY                                     = 0x00000010,

+    RST_MEM_BRIDGE                              = 0x00000011,

+    RST_EXT_AHB                                 = 0x00000012,

+    RST_DP_BB                                   = 0x00000013,

+    RST_DP_AP                                   = 0x00000014,

+    RST_COMREGS                                 = 0x00000015,

+    RST_COMREGS_AP                              = 0x00000016,

+    RST_AP_CLKEN                                = 0x00000017,

+    RST_AP_RST                                  = 0x00000018,

+    RST_MEM_CHK                                 = 0x00000019,

+    RST_MPMC                                    = 0x0000001A,

+    RST_SYS_A2A_WD                              = 0x0000001B,

+    RST_COMREGS_WD                              = 0x0000001C,

+    RST_BCPU                                    = 0x0000001D,

+    RST_BB_IRQ                                  = 0x0000001E,

+    RST_BB_A2A                                  = 0x0000001F,

+    RST_BB_IFC                                  = 0x00000020,

+    RST_BB_SRAM                                 = 0x00000021,

+    RST_ITLV                                    = 0x00000022,

+    RST_VITERBI                                 = 0x00000023,

+    RST_CIPHER                                  = 0x00000024,

+    RST_XCOR                                    = 0x00000025,

+    RST_COPRO                                   = 0x00000026,

+    RST_RF_IF                                   = 0x00000027,

+    RST_EXCOR                                   = 0x00000028,

+    RST_EVITAC                                  = 0x00000029,

+    RST_CORDIC                                  = 0x0000002A,

+    RST_TCU_BB                                  = 0x0000002B,

+    RST_BB_DP                                   = 0x0000002C,

+    RST_BB_ROM                                  = 0x0000002D,

+    RST_MPMC_BB                                 = 0x0000002E,

+    RST_BB_FULL                                 = 0x0000002F,

+    RST_SYS_FULL                                = 0x00000030

+} RESETS_T;

+

+#define NB_SRST                                 (29)

+/// Baseband side resets

+#define BOUND_BRST_FIRST                        (29)

+#define BOUND_BRST_AFTER                        (47)

+/// The following reset does not have register

+#define NR_RST_REG                              (48)

+#define NB_RST                                  (49)

+#define NB_BRST                                 (BOUND_BRST_AFTER-BOUND_BRST_FIRST)

+

+// ============================================================================

+// RESET_OTHERS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// Reset Other : resync on corresponding clock other

+    RSTO_DBG_HOST                               = 0x00000000,

+    RSTO_RF_RX                                  = 0x00000001,

+    RSTO_RF_TX                                  = 0x00000002,

+    RSTO_MEM_BRIDGE                             = 0x00000003,

+    RSTO_LPS                                    = 0x00000004,

+    RSTO_GPIO                                   = 0x00000005,

+    RSTO_WDTIMER                                = 0x00000006,

+    RSTO_TCU                                    = 0x00000007,

+    RSTO_MPMC                                   = 0x00000008

+} RESET_OTHERS_T;

+

+#define BOUND_RSTO_RF_FIRST                     (1)

+#define BOUND_RSTO_RF_AFTER                     (3)

+#define NB_RSTO                                 (9)

+

+// ============================================================================

+// WD_RESETS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// WD side resets

+    WD_RST_WCPU                                 = 0x00000000,

+    WD_RST_IRQ                                  = 0x00000001,

+    WD_RST_DP                                   = 0x00000002,

+    WD_RST_MODEM                                = 0x00000003,

+    WD_RST_A2A                                  = 0x00000004,

+    WD_RST_IFC                                  = 0x00000005,

+    WD_RST_SDMA                                 = 0x00000006,

+    WD_RST_SLPC                                 = 0x00000007,

+    WD_RST_SLPT                                 = 0x00000008,

+    WD_RST_SPI1                                 = 0x00000009,

+    WD_RST_SPI2                                 = 0x0000000A,

+    WD_RST_RFIF                                 = 0x0000000B,

+    WD_RST_COMREGS                              = 0x0000000C,

+    WD_RST_TIMER                                = 0x0000000D,

+    WD_RST_MPMC                                 = 0x0000000E,

+    WD_RST_FULL                                 = 0x0000000F

+} WD_RESETS_T;

+

+#define NB_WD_RST_BOUND                         (15)

+#define NB_WD_RST                               (16)

+

+// ============================================================================

+// AP_RESETS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// AP side resets

+    AP_RST_0                                    = 0x00000000,

+    AP_RST_1                                    = 0x00000001,

+    AP_RST_2                                    = 0x00000002,

+    AP_RST_3                                    = 0x00000003,

+    AP_RST_4                                    = 0x00000004

+} AP_RESETS_T;

+

+#define NB_AP_RST_BOUND                         (5)

+#define NB_AP_RST                               (5)

+/// For REG_DBG protect lock/unlock value

+#define SYS_CTRL_PROTECT_LOCK                   (0XA50000)

+#define SYS_CTRL_PROTECT_UNLOCK                 (0XA50001)

+

+// =============================================================================

+//  TYPES

+// =============================================================================

+

+// ============================================================================

+// SYS_CTRL_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef volatile struct

+{

+    /// <strong>This register is used to Lock and Unlock the protected registers.</strong>

+    REG32                          REG_DBG;                      //0x00000000

+    /// This register is protected.

+    REG32                          Sys_Rst_Set;                  //0x00000004

+    REG32                          Sys_Rst_Clr;                  //0x00000008

+    /// This register is protected.

+    REG32                          BB_Rst_Set;                   //0x0000000C

+    REG32                          BB_Rst_Clr;                   //0x00000010

+    REG32                          Clk_Sys_Mode;                 //0x00000014

+    REG32                          Clk_Sys_Enable;               //0x00000018

+    /// This register is protected.

+    REG32                          Clk_Sys_Disable;              //0x0000001C

+    REG32                          Clk_Per_Mode;                 //0x00000020

+    REG32                          Clk_Per_Enable;               //0x00000024

+    /// This register is protected.

+    REG32                          Clk_Per_Disable;              //0x00000028

+    REG32                          Clk_BB_Mode;                  //0x0000002C

+    REG32                          Clk_BB_Enable;                //0x00000030

+    /// This register is protected.

+    REG32                          Clk_BB_Disable;               //0x00000034

+    REG32                          Clk_Other_Mode;               //0x00000038

+    REG32                          Clk_Other_Enable;             //0x0000003C

+    /// This register is protected.

+    REG32                          Clk_Other_Disable;            //0x00000040

+    /// Register protected by Write_Unlocked_H.

+    REG32                          Pll_Ctrl;                     //0x00000044

+    /// This register is protected.

+    REG32                          Sel_Clock;                    //0x00000048

+    REG32                          Cfg_Clk_Sys;                  //0x0000004C

+    REG32                          Cfg_Clk_Mem_Bridge;           //0x00000050

+    /// This register is protected.

+    REG32                          Cfg_Clk_Out;                  //0x00000054

+    REG32                          Cfg_Clk_Host_Uart;            //0x00000058

+    REG32                          Cfg_Clk_Auxclk;               //0x0000005C

+    /// This register is protected.

+    REG32                          Cfg_AHB;                      //0x00000060

+    /// This register is protected. Used to unsplit masters manualy.

+    REG32                          Ctrl_AHB;                     //0x00000064

+    REG32                          XCpu_Dbg_BKP;                 //0x00000068

+    REG32                          XCpu_Dbg_Addr;                //0x0000006C

+    REG32                          BCpu_Dbg_BKP;                 //0x00000070

+    REG32                          BCpu_Dbg_Addr;                //0x00000074

+    REG32                          Cfg_Cpus_Cache_Ram_Disable;   //0x00000078

+    REG32                          Reset_Cause;                  //0x0000007C

+    /// This register is protected.

+    REG32                          WakeUp;                       //0x00000080

+    REG32                          AP_Ctrl;                      //0x00000084

+    /// This register is protected.

+    REG32                          Ignore_Charger;               //0x00000088

+    REG32                          Clk_SYS2_Mode;                //0x0000008C

+    REG32                          Clk_SYS2_Enable;              //0x00000090

+    /// This register is protected.

+    REG32                          Clk_SYS2_Disable;             //0x00000094

+    /// Register protected by Write_Unlocked_H.

+    REG32                          WD_Pll_Ctrl;                  //0x00000098

+    /// This register is protected.

+    REG32                          WD_Sel_Clock;                 //0x0000009C

+    /// This register is protected.

+    REG32                          WD_Rst_Set;                   //0x000000A0

+    REG32                          WD_Rst_Clr;                   //0x000000A4

+    /// This register is protected.

+    REG32                          AP_Rst_Set;                   //0x000000A8

+    REG32                          AP_Rst_Clr;                   //0x000000AC

+    REG32                          Clk_WD_Mode;                  //0x000000B0

+    REG32                          Clk_WD_Enable;                //0x000000B4

+    /// This register is protected.

+    REG32                          Clk_WD_Disable;               //0x000000B8

+    REG32                          Cfg_Clk_MPMC;                 //0x000000BC

+    REG32                          Cfg_MPMC_DQS;                 //0x000000C0

+    REG32 Reserved_000000C4[14];                //0x000000C4

+    /// This register is reserved.

+    REG32                          Cfg_Reserve;                  //0x000000FC

+} HWP_SYS_CTRL_T;

+

+#define hwp_sysCtrlMd               ((HWP_SYS_CTRL_T*)(RDA_MD_SYSCTRL_BASE))

+

+

+//REG_DBG

+#define SYS_CTRL_SCRATCH(n)        (((n)&0xFFFF)<<0)

+#define SYS_CTRL_WRITE_UNLOCK_STATUS (1<<30)

+#define SYS_CTRL_WRITE_UNLOCK      (1<<31)

+

+//Sys_Rst_Set

+#define SYS_CTRL_SET_RST_XCPU      (1<<0)

+#define SYS_CTRL_SET_RST_SYS_IRQ   (1<<1)

+#define SYS_CTRL_SET_RST_SYS_A2A   (1<<2)

+#define SYS_CTRL_SET_RST_SYS_AHB2AXI (1<<3)

+#define SYS_CTRL_SET_RST_SYS_AXI2AHB (1<<4)

+#define SYS_CTRL_SET_RST_DMA       (1<<5)

+#define SYS_CTRL_SET_RST_TIMER     (1<<6)

+#define SYS_CTRL_SET_RST_TCU       (1<<7)

+#define SYS_CTRL_SET_RST_GPIO      (1<<8)

+#define SYS_CTRL_SET_RST_CFG       (1<<9)

+#define SYS_CTRL_SET_RST_SPI1      (1<<10)

+#define SYS_CTRL_SET_RST_SPI2      (1<<11)

+#define SYS_CTRL_SET_RST_RF_SPI    (1<<12)

+#define SYS_CTRL_SET_RST_SCI1      (1<<13)

+#define SYS_CTRL_SET_RST_SCI2      (1<<14)

+#define SYS_CTRL_SET_RST_SCI3      (1<<15)

+#define SYS_CTRL_SET_RST_SPY       (1<<16)

+#define SYS_CTRL_SET_RST_MEM_BRIDGE (1<<17)

+#define SYS_CTRL_SET_RST_EXT_AHB   (1<<18)

+#define SYS_CTRL_SET_RST_DP_BB     (1<<19)

+#define SYS_CTRL_SET_RST_DP_AP     (1<<20)

+#define SYS_CTRL_SET_RST_COMREGS   (1<<21)

+#define SYS_CTRL_SET_RST_COMREGS_AP (1<<22)

+#define SYS_CTRL_SET_RST_AP_CLKEN  (1<<23)

+#define SYS_CTRL_SET_RST_AP_RST    (1<<24)

+#define SYS_CTRL_SET_RST_MEM_CHK   (1<<25)

+#define SYS_CTRL_SET_RST_MPMC      (1<<26)

+#define SYS_CTRL_SET_RST_SYS_A2A_WD (1<<27)

+#define SYS_CTRL_SET_RST_COMREGS_WD (1<<28)

+#define SYS_CTRL_SET_RST_OUT       (1<<30)

+#define SYS_CTRL_SOFT_RST          (1<<31)

+#define SYS_CTRL_SET_SYS_RST(n)    (((n)&0x1FFFFFFF)<<0)

+#define SYS_CTRL_SET_SYS_RST_MASK  (0x1FFFFFFF<<0)

+#define SYS_CTRL_SET_SYS_RST_SHIFT (0)

+

+//Sys_Rst_Clr

+#define SYS_CTRL_CLR_RST_XCPU      (1<<0)

+#define SYS_CTRL_CLR_RST_SYS_IRQ   (1<<1)

+#define SYS_CTRL_CLR_RST_SYS_A2A   (1<<2)

+#define SYS_CTRL_CLR_RST_SYS_AHB2AXI (1<<3)

+#define SYS_CTRL_CLR_RST_SYS_AXI2AHB (1<<4)

+#define SYS_CTRL_CLR_RST_DMA       (1<<5)

+#define SYS_CTRL_CLR_RST_TIMER     (1<<6)

+#define SYS_CTRL_CLR_RST_TCU       (1<<7)

+#define SYS_CTRL_CLR_RST_GPIO      (1<<8)

+#define SYS_CTRL_CLR_RST_CFG       (1<<9)

+#define SYS_CTRL_CLR_RST_SPI1      (1<<10)

+#define SYS_CTRL_CLR_RST_SPI2      (1<<11)

+#define SYS_CTRL_CLR_RST_RF_SPI    (1<<12)

+#define SYS_CTRL_CLR_RST_SCI1      (1<<13)

+#define SYS_CTRL_CLR_RST_SCI2      (1<<14)

+#define SYS_CTRL_CLR_RST_SCI3      (1<<15)

+#define SYS_CTRL_CLR_RST_SPY       (1<<16)

+#define SYS_CTRL_CLR_RST_MEM_BRIDGE (1<<17)

+#define SYS_CTRL_CLR_RST_EXT_AHB   (1<<18)

+#define SYS_CTRL_CLR_RST_DP_BB     (1<<19)

+#define SYS_CTRL_CLR_RST_DP_AP     (1<<20)

+#define SYS_CTRL_CLR_RST_COMREGS   (1<<21)

+#define SYS_CTRL_CLR_RST_COMREGS_AP (1<<22)

+#define SYS_CTRL_CLR_RST_AP_CLKEN  (1<<23)

+#define SYS_CTRL_CLR_RST_AP_RST    (1<<24)

+#define SYS_CTRL_CLR_RST_MEM_CHK   (1<<25)

+#define SYS_CTRL_CLR_RST_MPMC      (1<<26)

+#define SYS_CTRL_CLR_RST_SYS_A2A_WD (1<<27)

+#define SYS_CTRL_CLR_RST_COMREGS_WD (1<<28)

+#define SYS_CTRL_CLR_RST_OUT       (1<<30)

+#define SYS_CTRL_CLR_SYS_RST(n)    (((n)&0x1FFFFFFF)<<0)

+#define SYS_CTRL_CLR_SYS_RST_MASK  (0x1FFFFFFF<<0)

+#define SYS_CTRL_CLR_SYS_RST_SHIFT (0)

+

+//BB_Rst_Set

+#define SYS_CTRL_SET_RST_BCPU      (1<<0)

+#define SYS_CTRL_SET_RST_BB_IRQ    (1<<1)

+#define SYS_CTRL_SET_RST_BB_A2A    (1<<2)

+#define SYS_CTRL_SET_RST_BB_IFC    (1<<3)

+#define SYS_CTRL_SET_RST_BB_SRAM   (1<<4)

+#define SYS_CTRL_SET_RST_ITLV      (1<<5)

+#define SYS_CTRL_SET_RST_VITERBI   (1<<6)

+#define SYS_CTRL_SET_RST_CIPHER    (1<<7)

+#define SYS_CTRL_SET_RST_XCOR      (1<<8)

+#define SYS_CTRL_SET_RST_COPRO     (1<<9)

+#define SYS_CTRL_SET_RST_RF_IF     (1<<10)

+#define SYS_CTRL_SET_RST_EXCOR     (1<<11)

+#define SYS_CTRL_SET_RST_EVITAC    (1<<12)

+#define SYS_CTRL_SET_RST_CORDIC    (1<<13)

+#define SYS_CTRL_SET_RST_TCU_BB    (1<<14)

+#define SYS_CTRL_SET_RST_BB_DP     (1<<15)

+#define SYS_CTRL_SET_RST_BB_ROM    (1<<16)

+#define SYS_CTRL_SET_RST_MPMC_BB   (1<<17)

+#define SYS_CTRL_SET_RST_BB_FULL   (1<<31)

+#define SYS_CTRL_SET_BB_RST(n)     (((n)&0x3FFFF)<<0)

+#define SYS_CTRL_SET_BB_RST_MASK   (0x3FFFF<<0)

+#define SYS_CTRL_SET_BB_RST_SHIFT  (0)

+

+//BB_Rst_Clr

+#define SYS_CTRL_CLR_RST_BCPU      (1<<0)

+#define SYS_CTRL_CLR_RST_BB_IRQ    (1<<1)

+#define SYS_CTRL_CLR_RST_BB_A2A    (1<<2)

+#define SYS_CTRL_CLR_RST_BB_IFC    (1<<3)

+#define SYS_CTRL_CLR_RST_BB_SRAM   (1<<4)

+#define SYS_CTRL_CLR_RST_ITLV      (1<<5)

+#define SYS_CTRL_CLR_RST_VITERBI   (1<<6)

+#define SYS_CTRL_CLR_RST_CIPHER    (1<<7)

+#define SYS_CTRL_CLR_RST_XCOR      (1<<8)

+#define SYS_CTRL_CLR_RST_COPRO     (1<<9)

+#define SYS_CTRL_CLR_RST_RF_IF     (1<<10)

+#define SYS_CTRL_CLR_RST_EXCOR     (1<<11)

+#define SYS_CTRL_CLR_RST_EVITAC    (1<<12)

+#define SYS_CTRL_CLR_RST_CORDIC    (1<<13)

+#define SYS_CTRL_CLR_RST_TCU_BB    (1<<14)

+#define SYS_CTRL_CLR_RST_BB_DP     (1<<15)

+#define SYS_CTRL_CLR_RST_BB_ROM    (1<<16)

+#define SYS_CTRL_CLR_RST_MPMC_BB   (1<<17)

+#define SYS_CTRL_CLR_RST_BB_FULL   (1<<31)

+#define SYS_CTRL_CLR_BB_RST(n)     (((n)&0x3FFFF)<<0)

+#define SYS_CTRL_CLR_BB_RST_MASK   (0x3FFFF<<0)

+#define SYS_CTRL_CLR_BB_RST_SHIFT  (0)

+

+//Clk_Sys_Mode

+#define SYS_CTRL_MODE_SYS_XCPU     (1<<0)

+#define SYS_CTRL_MODE_SYS_XCPU_INT_AUTOMATIC (0<<1)

+#define SYS_CTRL_MODE_SYS_XCPU_INT_MANUAL (1<<1)

+#define SYS_CTRL_MODE_SYS_PCLK_CONF_AUTOMATIC (0<<2)

+#define SYS_CTRL_MODE_SYS_PCLK_CONF_MANUAL (1<<2)

+#define SYS_CTRL_MODE_SYS_PCLK_DATA_AUTOMATIC (0<<3)

+#define SYS_CTRL_MODE_SYS_PCLK_DATA_MANUAL (1<<3)

+#define SYS_CTRL_MODE_SYS_AMBA_AUTOMATIC (0<<4)

+#define SYS_CTRL_MODE_SYS_AMBA_MANUAL (1<<4)

+#define SYS_CTRL_MODE_SYS_DMA_AUTOMATIC (0<<5)

+#define SYS_CTRL_MODE_SYS_DMA_MANUAL (1<<5)

+#define SYS_CTRL_MODE_SYS_EBC_AUTOMATIC (0<<6)

+#define SYS_CTRL_MODE_SYS_EBC_MANUAL (1<<6)

+#define SYS_CTRL_MODE_SYS_IFC_CH0_AUTOMATIC (0<<7)

+#define SYS_CTRL_MODE_SYS_IFC_CH0_MANUAL (1<<7)

+#define SYS_CTRL_MODE_SYS_IFC_CH1_AUTOMATIC (0<<8)

+#define SYS_CTRL_MODE_SYS_IFC_CH1_MANUAL (1<<8)

+#define SYS_CTRL_MODE_SYS_IFC_CH2_AUTOMATIC (0<<9)

+#define SYS_CTRL_MODE_SYS_IFC_CH2_MANUAL (1<<9)

+#define SYS_CTRL_MODE_SYS_IFC_CH3_AUTOMATIC (0<<10)

+#define SYS_CTRL_MODE_SYS_IFC_CH3_MANUAL (1<<10)

+#define SYS_CTRL_MODE_SYS_IFC_DBG_AUTOMATIC (0<<11)

+#define SYS_CTRL_MODE_SYS_IFC_DBG_MANUAL (1<<11)

+#define SYS_CTRL_MODE_SYS_A2A_AUTOMATIC (0<<12)

+#define SYS_CTRL_MODE_SYS_A2A_MANUAL (1<<12)

+#define SYS_CTRL_MODE_SYS_AXI2AHB_AUTOMATIC (0<<13)

+#define SYS_CTRL_MODE_SYS_AXI2AHB_MANUAL (1<<13)

+#define SYS_CTRL_MODE_SYS_AHB2AXI_AUTOMATIC (0<<14)

+#define SYS_CTRL_MODE_SYS_AHB2AXI_MANUAL (1<<14)

+#define SYS_CTRL_MODE_SYS_EXT_AHB_AUTOMATIC (0<<15)

+#define SYS_CTRL_MODE_SYS_EXT_AHB_MANUAL (1<<15)

+#define SYS_CTRL_MODE_SYS_DEBUG_UART_AUTOMATIC (0<<16)

+#define SYS_CTRL_MODE_SYS_DEBUG_UART_MANUAL (1<<16)

+#define SYS_CTRL_MODE_SYS_DBGHST_AUTOMATIC (0<<17)

+#define SYS_CTRL_MODE_SYS_DBGHST_MANUAL (1<<17)

+#define SYS_CTRL_MODE_SYS_A2A_WD_AUTOMATIC (0<<18)

+#define SYS_CTRL_MODE_SYS_A2A_WD_MANUAL (1<<18)

+#define SYS_CTRL_MODE_SYSD_SCI1_AUTOMATIC (0<<19)

+#define SYS_CTRL_MODE_SYSD_SCI1_MANUAL (1<<19)

+#define SYS_CTRL_MODE_SYSD_SCI2_AUTOMATIC (0<<20)

+#define SYS_CTRL_MODE_SYSD_SCI2_MANUAL (1<<20)

+#define SYS_CTRL_MODE_SYSD_SCI3_AUTOMATIC (0<<21)

+#define SYS_CTRL_MODE_SYSD_SCI3_MANUAL (1<<21)

+#define SYS_CTRL_MODE_SYSD_RF_SPI_AUTOMATIC (0<<22)

+#define SYS_CTRL_MODE_SYSD_RF_SPI_MANUAL (1<<22)

+#define SYS_CTRL_MODE_SYSD_OSC_AUTOMATIC (0<<23)

+#define SYS_CTRL_MODE_SYSD_OSC_MANUAL (1<<23)

+#define SYS_CTRL_MODE_CLK_SYS(n)   (((n)&0x7FFFFF)<<1)

+#define SYS_CTRL_MODE_CLK_SYS_MASK (0x7FFFFF<<1)

+#define SYS_CTRL_MODE_CLK_SYS_SHIFT (1)

+

+//Clk_Sys_Enable

+#define SYS_CTRL_ENABLE_SYS_XCPU   (1<<0)

+#define SYS_CTRL_ENABLE_SYS_XCPU_INT (1<<1)

+#define SYS_CTRL_ENABLE_SYS_PCLK_CONF (1<<2)

+#define SYS_CTRL_ENABLE_SYS_PCLK_DATA (1<<3)

+#define SYS_CTRL_ENABLE_SYS_AMBA   (1<<4)

+#define SYS_CTRL_ENABLE_SYS_DMA    (1<<5)

+#define SYS_CTRL_ENABLE_SYS_EBC    (1<<6)

+#define SYS_CTRL_ENABLE_SYS_IFC_CH0 (1<<7)

+#define SYS_CTRL_ENABLE_SYS_IFC_CH1 (1<<8)

+#define SYS_CTRL_ENABLE_SYS_IFC_CH2 (1<<9)

+#define SYS_CTRL_ENABLE_SYS_IFC_CH3 (1<<10)

+#define SYS_CTRL_ENABLE_SYS_IFC_DBG (1<<11)

+#define SYS_CTRL_ENABLE_SYS_A2A    (1<<12)

+#define SYS_CTRL_ENABLE_SYS_AXI2AHB (1<<13)

+#define SYS_CTRL_ENABLE_SYS_AHB2AXI (1<<14)

+#define SYS_CTRL_ENABLE_SYS_EXT_AHB (1<<15)

+#define SYS_CTRL_ENABLE_SYS_DEBUG_UART (1<<16)

+#define SYS_CTRL_ENABLE_SYS_DBGHST (1<<17)

+#define SYS_CTRL_ENABLE_SYS_A2A_WD (1<<18)

+#define SYS_CTRL_ENABLE_SYSD_SCI1  (1<<19)

+#define SYS_CTRL_ENABLE_SYSD_SCI2  (1<<20)

+#define SYS_CTRL_ENABLE_SYSD_SCI3  (1<<21)

+#define SYS_CTRL_ENABLE_SYSD_RF_SPI (1<<22)

+#define SYS_CTRL_ENABLE_SYSD_OSC   (1<<23)

+#define SYS_CTRL_ENABLE_SYS_GPIO   (1<<24)

+#define SYS_CTRL_ENABLE_SYS_IRQ    (1<<25)

+#define SYS_CTRL_ENABLE_SYS_TCU    (1<<26)

+#define SYS_CTRL_ENABLE_SYS_TIMER  (1<<27)

+#define SYS_CTRL_ENABLE_SYS_COM_REGS (1<<28)

+#define SYS_CTRL_ENABLE_CLK_SYS(n) (((n)&0x1FFFFFFF)<<0)

+#define SYS_CTRL_ENABLE_CLK_SYS_MASK (0x1FFFFFFF<<0)

+#define SYS_CTRL_ENABLE_CLK_SYS_SHIFT (0)

+

+//Clk_Sys_Disable

+#define SYS_CTRL_DISABLE_SYS_XCPU  (1<<0)

+#define SYS_CTRL_DISABLE_SYS_XCPU_INT (1<<1)

+#define SYS_CTRL_DISABLE_SYS_PCLK_CONF (1<<2)

+#define SYS_CTRL_DISABLE_SYS_PCLK_DATA (1<<3)

+#define SYS_CTRL_DISABLE_SYS_AMBA  (1<<4)

+#define SYS_CTRL_DISABLE_SYS_DMA   (1<<5)

+#define SYS_CTRL_DISABLE_SYS_EBC   (1<<6)

+#define SYS_CTRL_DISABLE_SYS_IFC_CH0 (1<<7)

+#define SYS_CTRL_DISABLE_SYS_IFC_CH1 (1<<8)

+#define SYS_CTRL_DISABLE_SYS_IFC_CH2 (1<<9)

+#define SYS_CTRL_DISABLE_SYS_IFC_CH3 (1<<10)

+#define SYS_CTRL_DISABLE_SYS_IFC_DBG (1<<11)

+#define SYS_CTRL_DISABLE_SYS_A2A   (1<<12)

+#define SYS_CTRL_DISABLE_SYS_AXI2AHB (1<<13)

+#define SYS_CTRL_DISABLE_SYS_AHB2AXI (1<<14)

+#define SYS_CTRL_DISABLE_SYS_EXT_AHB (1<<15)

+#define SYS_CTRL_DISABLE_SYS_DEBUG_UART (1<<16)

+#define SYS_CTRL_DISABLE_SYS_DBGHST (1<<17)

+#define SYS_CTRL_DISABLE_SYS_A2A_WD (1<<18)

+#define SYS_CTRL_DISABLE_SYSD_SCI1 (1<<19)

+#define SYS_CTRL_DISABLE_SYSD_SCI2 (1<<20)

+#define SYS_CTRL_DISABLE_SYSD_SCI3 (1<<21)

+#define SYS_CTRL_DISABLE_SYSD_RF_SPI (1<<22)

+#define SYS_CTRL_DISABLE_SYSD_OSC  (1<<23)

+#define SYS_CTRL_DISABLE_SYS_GPIO  (1<<24)

+#define SYS_CTRL_DISABLE_SYS_IRQ   (1<<25)

+#define SYS_CTRL_DISABLE_SYS_TCU   (1<<26)

+#define SYS_CTRL_DISABLE_SYS_TIMER (1<<27)

+#define SYS_CTRL_DISABLE_SYS_COM_REGS (1<<28)

+#define SYS_CTRL_DISABLE_CLK_SYS(n) (((n)&0x1FFFFFFF)<<0)

+#define SYS_CTRL_DISABLE_CLK_SYS_MASK (0x1FFFFFFF<<0)

+#define SYS_CTRL_DISABLE_CLK_SYS_SHIFT (0)

+

+//Clk_Per_Mode

+#define SYS_CTRL_MODE_PERD_SPI1_AUTOMATIC (0<<0)

+#define SYS_CTRL_MODE_PERD_SPI1_MANUAL (1<<0)

+#define SYS_CTRL_MODE_PERD_SPI2_AUTOMATIC (0<<1)

+#define SYS_CTRL_MODE_PERD_SPI2_MANUAL (1<<1)

+#define SYS_CTRL_MODE_CLK_PER(n)   (((n)&3)<<0)

+#define SYS_CTRL_MODE_CLK_PER_MASK (3<<0)

+#define SYS_CTRL_MODE_CLK_PER_SHIFT (0)

+

+//Clk_Per_Enable

+#define SYS_CTRL_ENABLE_PERD_SPI1  (1<<0)

+#define SYS_CTRL_ENABLE_PERD_SPI2  (1<<1)

+#define SYS_CTRL_ENABLE_PER_SPY    (1<<2)

+#define SYS_CTRL_ENABLE_PER_TEST   (1<<3)

+#define SYS_CTRL_ENABLE_CLK_PER(n) (((n)&15)<<0)

+#define SYS_CTRL_ENABLE_CLK_PER_MASK (15<<0)

+#define SYS_CTRL_ENABLE_CLK_PER_SHIFT (0)

+

+//Clk_Per_Disable

+#define SYS_CTRL_DISABLE_PERD_SPI1 (1<<0)

+#define SYS_CTRL_DISABLE_PERD_SPI2 (1<<1)

+#define SYS_CTRL_DISABLE_PER_SPY   (1<<2)

+#define SYS_CTRL_DISABLE_PER_TEST  (1<<3)

+#define SYS_CTRL_DISABLE_CLK_PER(n) (((n)&15)<<0)

+#define SYS_CTRL_DISABLE_CLK_PER_MASK (15<<0)

+#define SYS_CTRL_DISABLE_CLK_PER_SHIFT (0)

+

+//Clk_BB_Mode

+#define SYS_CTRL_MODE_BB_BCPU      (1<<0)

+#define SYS_CTRL_MODE_BB_BCPU_INT_AUTOMATIC (0<<1)

+#define SYS_CTRL_MODE_BB_BCPU_INT_MANUAL (1<<1)

+#define SYS_CTRL_MODE_BB_AMBA_AUTOMATIC (0<<2)

+#define SYS_CTRL_MODE_BB_AMBA_MANUAL (1<<2)

+#define SYS_CTRL_MODE_BB_PCLK_CONF_AUTOMATIC (0<<3)

+#define SYS_CTRL_MODE_BB_PCLK_CONF_MANUAL (1<<3)

+#define SYS_CTRL_MODE_BB_PCLK_DATA_AUTOMATIC (0<<4)

+#define SYS_CTRL_MODE_BB_PCLK_DATA_MANUAL (1<<4)

+#define SYS_CTRL_MODE_BB_EXCOR_AUTOMATIC (0<<5)

+#define SYS_CTRL_MODE_BB_EXCOR_MANUAL (1<<5)

+#define SYS_CTRL_MODE_BB_IFC_CH2_AUTOMATIC (0<<6)

+#define SYS_CTRL_MODE_BB_IFC_CH2_MANUAL (1<<6)

+#define SYS_CTRL_MODE_BB_IFC_CH3_AUTOMATIC (0<<7)

+#define SYS_CTRL_MODE_BB_IFC_CH3_MANUAL (1<<7)

+#define SYS_CTRL_MODE_BB_SRAM_AUTOMATIC (0<<8)

+#define SYS_CTRL_MODE_BB_SRAM_MANUAL (1<<8)

+#define SYS_CTRL_MODE_BB_A2A_AUTOMATIC (0<<9)

+#define SYS_CTRL_MODE_BB_A2A_MANUAL (1<<9)

+#define SYS_CTRL_MODE_BB_ITLV_AUTOMATIC (0<<10)

+#define SYS_CTRL_MODE_BB_ITLV_MANUAL (1<<10)

+#define SYS_CTRL_MODE_BB_VITERBI_AUTOMATIC (0<<11)

+#define SYS_CTRL_MODE_BB_VITERBI_MANUAL (1<<11)

+#define SYS_CTRL_MODE_BB_CIPHER_AUTOMATIC (0<<12)

+#define SYS_CTRL_MODE_BB_CIPHER_MANUAL (1<<12)

+#define SYS_CTRL_MODE_BB_RF_IF_AUTOMATIC (0<<13)

+#define SYS_CTRL_MODE_BB_RF_IF_MANUAL (1<<13)

+#define SYS_CTRL_MODE_BB_COPRO_AUTOMATIC (0<<14)

+#define SYS_CTRL_MODE_BB_COPRO_MANUAL (1<<14)

+#define SYS_CTRL_MODE_BB_CP2_REG_AUTOMATIC (0<<15)

+#define SYS_CTRL_MODE_BB_CP2_REG_MANUAL (1<<15)

+#define SYS_CTRL_MODE_BB_XCOR_AUTOMATIC (0<<16)

+#define SYS_CTRL_MODE_BB_XCOR_MANUAL (1<<16)

+#define SYS_CTRL_MODE_BB_EVITAC_AUTOMATIC (0<<17)

+#define SYS_CTRL_MODE_BB_EVITAC_MANUAL (1<<17)

+#define SYS_CTRL_MODE_BB_ROM_AUTOMATIC (0<<18)

+#define SYS_CTRL_MODE_BB_ROM_MANUAL (1<<18)

+#define SYS_CTRL_MODE_BB_MPMC_AUTOMATIC (0<<19)

+#define SYS_CTRL_MODE_BB_MPMC_MANUAL (1<<19)

+#define SYS_CTRL_MODE_CLK_BB(n)    (((n)&0x7FFFF)<<1)

+#define SYS_CTRL_MODE_CLK_BB_MASK  (0x7FFFF<<1)

+#define SYS_CTRL_MODE_CLK_BB_SHIFT (1)

+

+//Clk_BB_Enable

+#define SYS_CTRL_ENABLE_BB_BCPU    (1<<0)

+#define SYS_CTRL_ENABLE_BB_BCPU_INT (1<<1)

+#define SYS_CTRL_ENABLE_BB_AMBA    (1<<2)

+#define SYS_CTRL_ENABLE_BB_PCLK_CONF (1<<3)

+#define SYS_CTRL_ENABLE_BB_PCLK_DATA (1<<4)

+#define SYS_CTRL_ENABLE_BB_EXCOR   (1<<5)

+#define SYS_CTRL_ENABLE_BB_IFC_CH2 (1<<6)

+#define SYS_CTRL_ENABLE_BB_IFC_CH3 (1<<7)

+#define SYS_CTRL_ENABLE_BB_SRAM    (1<<8)

+#define SYS_CTRL_ENABLE_BB_A2A     (1<<9)

+#define SYS_CTRL_ENABLE_BB_ITLV    (1<<10)

+#define SYS_CTRL_ENABLE_BB_VITERBI (1<<11)

+#define SYS_CTRL_ENABLE_BB_CIPHER  (1<<12)

+#define SYS_CTRL_ENABLE_BB_RF_IF   (1<<13)

+#define SYS_CTRL_ENABLE_BB_COPRO   (1<<14)

+#define SYS_CTRL_ENABLE_BB_CP2_REG (1<<15)

+#define SYS_CTRL_ENABLE_BB_XCOR    (1<<16)

+#define SYS_CTRL_ENABLE_BB_EVITAC  (1<<17)

+#define SYS_CTRL_ENABLE_BB_ROM     (1<<18)

+#define SYS_CTRL_ENABLE_BB_MPMC    (1<<19)

+#define SYS_CTRL_ENABLE_BB_IRQ     (1<<20)

+#define SYS_CTRL_ENABLE_BB_COM_REGS (1<<21)

+#define SYS_CTRL_ENABLE_BB_CORDIC  (1<<22)

+#define SYS_CTRL_ENABLE_BB_DP      (1<<23)

+#define SYS_CTRL_ENABLE_CLK_BB(n)  (((n)&0xFFFFFF)<<0)

+#define SYS_CTRL_ENABLE_CLK_BB_MASK (0xFFFFFF<<0)

+#define SYS_CTRL_ENABLE_CLK_BB_SHIFT (0)

+

+//Clk_BB_Disable

+#define SYS_CTRL_DISABLE_BB_BCPU   (1<<0)

+#define SYS_CTRL_DISABLE_BB_BCPU_INT (1<<1)

+#define SYS_CTRL_DISABLE_BB_AMBA   (1<<2)

+#define SYS_CTRL_DISABLE_BB_PCLK_CONF (1<<3)

+#define SYS_CTRL_DISABLE_BB_PCLK_DATA (1<<4)

+#define SYS_CTRL_DISABLE_BB_EXCOR  (1<<5)

+#define SYS_CTRL_DISABLE_BB_IFC_CH2 (1<<6)

+#define SYS_CTRL_DISABLE_BB_IFC_CH3 (1<<7)

+#define SYS_CTRL_DISABLE_BB_SRAM   (1<<8)

+#define SYS_CTRL_DISABLE_BB_A2A    (1<<9)

+#define SYS_CTRL_DISABLE_BB_ITLV   (1<<10)

+#define SYS_CTRL_DISABLE_BB_VITERBI (1<<11)

+#define SYS_CTRL_DISABLE_BB_CIPHER (1<<12)

+#define SYS_CTRL_DISABLE_BB_RF_IF  (1<<13)

+#define SYS_CTRL_DISABLE_BB_COPRO  (1<<14)

+#define SYS_CTRL_DISABLE_BB_CP2_REG (1<<15)

+#define SYS_CTRL_DISABLE_BB_XCOR   (1<<16)

+#define SYS_CTRL_DISABLE_BB_EVITAC (1<<17)

+#define SYS_CTRL_DISABLE_BB_ROM    (1<<18)

+#define SYS_CTRL_DISABLE_BB_MPMC   (1<<19)

+#define SYS_CTRL_DISABLE_BB_IRQ    (1<<20)

+#define SYS_CTRL_DISABLE_BB_COM_REGS (1<<21)

+#define SYS_CTRL_DISABLE_BB_CORDIC (1<<22)

+#define SYS_CTRL_DISABLE_BB_DP     (1<<23)

+#define SYS_CTRL_DISABLE_CLK_BB(n) (((n)&0xFFFFFF)<<0)

+#define SYS_CTRL_DISABLE_CLK_BB_MASK (0xFFFFFF<<0)

+#define SYS_CTRL_DISABLE_CLK_BB_SHIFT (0)

+

+//Clk_Other_Mode

+#define SYS_CTRL_MODE_OC_DEBUG_UART_AUTOMATIC (0<<0)

+#define SYS_CTRL_MODE_OC_DEBUG_UART_MANUAL (1<<0)

+#define SYS_CTRL_MODE_OC_RF_RX_AUTOMATIC (0<<1)

+#define SYS_CTRL_MODE_OC_RF_RX_MANUAL (1<<1)

+#define SYS_CTRL_MODE_OC_RF_TX_AUTOMATIC (0<<2)

+#define SYS_CTRL_MODE_OC_RF_TX_MANUAL (1<<2)

+#define SYS_CTRL_MODE_OC_MEM_BRIDGE_AUTOMATIC (0<<3)

+#define SYS_CTRL_MODE_OC_MEM_BRIDGE_MANUAL (1<<3)

+#define SYS_CTRL_MODE_CLK_OTHER(n) (((n)&15)<<0)

+#define SYS_CTRL_MODE_CLK_OTHER_MASK (15<<0)

+#define SYS_CTRL_MODE_CLK_OTHER_SHIFT (0)

+

+//Clk_Other_Enable

+#define SYS_CTRL_ENABLE_OC_DEBUG_UART (1<<0)

+#define SYS_CTRL_ENABLE_OC_RF_RX   (1<<1)

+#define SYS_CTRL_ENABLE_OC_RF_TX   (1<<2)

+#define SYS_CTRL_ENABLE_OC_MEM_BRIDGE (1<<3)

+#define SYS_CTRL_ENABLE_OC_LPS     (1<<4)

+#define SYS_CTRL_ENABLE_OC_GPIO    (1<<5)

+#define SYS_CTRL_ENABLE_OC_CLK_OUT (1<<6)

+#define SYS_CTRL_ENABLE_OC_MEM_CLK_OUT (1<<7)

+#define SYS_CTRL_ENABLE_OC_TCU     (1<<8)

+#define SYS_CTRL_ENABLE_OC_WD_CHIP (1<<9)

+#define SYS_CTRL_ENABLE_OC_WD_ADC  (1<<10)

+#define SYS_CTRL_ENABLE_OC_WD_TURBO (1<<11)

+#define SYS_CTRL_ENABLE_OC_WD_OSC  (1<<12)

+#define SYS_CTRL_ENABLE_OC_MPMC    (1<<13)

+#define SYS_CTRL_ENABLE_CLK_OTHER(n) (((n)&0x3FFF)<<0)

+#define SYS_CTRL_ENABLE_CLK_OTHER_MASK (0x3FFF<<0)

+#define SYS_CTRL_ENABLE_CLK_OTHER_SHIFT (0)

+

+//Clk_Other_Disable

+#define SYS_CTRL_DISABLE_OC_DEBUG_UART (1<<0)

+#define SYS_CTRL_DISABLE_OC_RF_RX  (1<<1)

+#define SYS_CTRL_DISABLE_OC_RF_TX  (1<<2)

+#define SYS_CTRL_DISABLE_OC_MEM_BRIDGE (1<<3)

+#define SYS_CTRL_DISABLE_OC_LPS    (1<<4)

+#define SYS_CTRL_DISABLE_OC_GPIO   (1<<5)

+#define SYS_CTRL_DISABLE_OC_CLK_OUT (1<<6)

+#define SYS_CTRL_DISABLE_OC_MEM_CLK_OUT (1<<7)

+#define SYS_CTRL_DISABLE_OC_TCU    (1<<8)

+#define SYS_CTRL_DISABLE_OC_WD_CHIP (1<<9)

+#define SYS_CTRL_DISABLE_OC_WD_ADC (1<<10)

+#define SYS_CTRL_DISABLE_OC_WD_TURBO (1<<11)

+#define SYS_CTRL_DISABLE_OC_WD_OSC (1<<12)

+#define SYS_CTRL_DISABLE_OC_MPMC   (1<<13)

+#define SYS_CTRL_DISABLE_CLK_OTHER(n) (((n)&0x3FFF)<<0)

+#define SYS_CTRL_DISABLE_CLK_OTHER_MASK (0x3FFF<<0)

+#define SYS_CTRL_DISABLE_CLK_OTHER_SHIFT (0)

+

+//Pll_Ctrl

+#define SYS_CTRL_PLL_ENABLE        (1<<0)

+#define SYS_CTRL_PLL_ENABLE_MASK   (1<<0)

+#define SYS_CTRL_PLL_ENABLE_SHIFT  (0)

+#define SYS_CTRL_PLL_ENABLE_POWER_DOWN (0<<0)

+#define SYS_CTRL_PLL_ENABLE_ENABLE (1<<0)

+#define SYS_CTRL_PLL_LOCK_RESET    (1<<4)

+#define SYS_CTRL_PLL_LOCK_RESET_MASK (1<<4)

+#define SYS_CTRL_PLL_LOCK_RESET_SHIFT (4)

+#define SYS_CTRL_PLL_LOCK_RESET_RESET (0<<4)

+#define SYS_CTRL_PLL_LOCK_RESET_NO_RESET (1<<4)

+#define SYS_CTRL_PLL_BYPASS        (1<<8)

+#define SYS_CTRL_PLL_BYPASS_MASK   (1<<8)

+#define SYS_CTRL_PLL_BYPASS_SHIFT  (8)

+#define SYS_CTRL_PLL_BYPASS_PASS   (0<<8)

+#define SYS_CTRL_PLL_BYPASS_BYPASS (1<<8)

+#define SYS_CTRL_PLL_CLK_FAST_ENABLE (1<<12)

+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_MASK (1<<12)

+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_SHIFT (12)

+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_ENABLE (1<<12)

+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_DISABLE (0<<12)

+#define SYS_CTRL_PLL_XP_CFG(n)     (((n)&4369)<<0)

+#define SYS_CTRL_PLL_XP_CFG_MASK   (4369<<0)

+#define SYS_CTRL_PLL_XP_CFG_SHIFT  (0)

+

+//Sel_Clock

+#define SYS_CTRL_SLOW_SEL_RF_OSCILLATOR (1<<0)

+#define SYS_CTRL_SLOW_SEL_RF_RF    (0<<0)

+#define SYS_CTRL_SYS_SEL_FAST_SLOW (1<<4)

+#define SYS_CTRL_SYS_SEL_FAST_FAST (0<<4)

+#define SYS_CTRL_TCU_13M_L_26M     (1<<5)

+#define SYS_CTRL_TCU_13M_L_13M     (0<<5)

+#define SYS_CTRL_PLL_DISABLE_LPS_DISABLE (1<<6)

+#define SYS_CTRL_PLL_DISABLE_LPS_ENABLE (0<<6)

+#define SYS_CTRL_DIGEN_H_ENABLE    (1<<7)

+#define SYS_CTRL_DIGEN_H_DISABLE   (0<<7)

+#define SYS_CTRL_RF_DETECTED_OK    (1<<20)

+#define SYS_CTRL_RF_DETECTED_NO    (0<<20)

+#define SYS_CTRL_RF_DETECT_BYPASS  (1<<21)

+#define SYS_CTRL_RF_DETECT_RESET   (1<<22)

+#define SYS_CTRL_RF_SELECTED_L     (1<<23)

+#define SYS_CTRL_PLL_LOCKED        (1<<24)

+#define SYS_CTRL_PLL_LOCKED_MASK   (1<<24)

+#define SYS_CTRL_PLL_LOCKED_SHIFT  (24)

+#define SYS_CTRL_PLL_LOCKED_LOCKED (1<<24)

+#define SYS_CTRL_PLL_LOCKED_NOT_LOCKED (0<<24)

+#define SYS_CTRL_PLL_BYPASS_LOCK   (1<<27)

+#define SYS_CTRL_FAST_SELECTED_L   (1<<31)

+#define SYS_CTRL_FAST_SELECTED_L_MASK (1<<31)

+#define SYS_CTRL_FAST_SELECTED_L_SHIFT (31)

+

+//Cfg_Clk_Sys

+#define SYS_CTRL_FREQ(n)           (((n)&15)<<0)

+#define SYS_CTRL_FREQ_MASK         (15<<0)

+#define SYS_CTRL_FREQ_SHIFT        (0)

+#define SYS_CTRL_FREQ_312M         (13<<0)

+#define SYS_CTRL_FREQ_250M         (12<<0)

+#define SYS_CTRL_FREQ_208M         (11<<0)

+#define SYS_CTRL_FREQ_178M         (10<<0)

+#define SYS_CTRL_FREQ_156M         (9<<0)

+#define SYS_CTRL_FREQ_139M         (8<<0)

+#define SYS_CTRL_FREQ_125M         (7<<0)

+#define SYS_CTRL_FREQ_113M         (6<<0)

+#define SYS_CTRL_FREQ_104M         (5<<0)

+#define SYS_CTRL_FREQ_89M          (4<<0)

+#define SYS_CTRL_FREQ_78M          (3<<0)

+#define SYS_CTRL_FREQ_52M          (2<<0)

+#define SYS_CTRL_FREQ_39M          (1<<0)

+#define SYS_CTRL_FREQ_26M          (0<<0)

+#define SYS_CTRL_FORCE_DIV_UPDATE  (1<<4)

+#define SYS_CTRL_REQ_DIV_UPDATE    (1<<8)

+

+//Cfg_Clk_Mem_Bridge

+#define SYS_CTRL_MEM_FREQ(n)       (((n)&15)<<0)

+#define SYS_CTRL_MEM_FREQ_MASK     (15<<0)

+#define SYS_CTRL_MEM_FREQ_SHIFT    (0)

+#define SYS_CTRL_MEM_FREQ_312M     (13<<0)

+#define SYS_CTRL_MEM_FREQ_250M     (12<<0)

+#define SYS_CTRL_MEM_FREQ_208M     (11<<0)

+#define SYS_CTRL_MEM_FREQ_178M     (10<<0)

+#define SYS_CTRL_MEM_FREQ_156M     (9<<0)

+#define SYS_CTRL_MEM_FREQ_139M     (8<<0)

+#define SYS_CTRL_MEM_FREQ_125M     (7<<0)

+#define SYS_CTRL_MEM_FREQ_113M     (6<<0)

+#define SYS_CTRL_MEM_FREQ_104M     (5<<0)

+#define SYS_CTRL_MEM_FREQ_89M      (4<<0)

+#define SYS_CTRL_MEM_FREQ_78M      (3<<0)

+#define SYS_CTRL_MEM_FREQ_52M      (2<<0)

+#define SYS_CTRL_MEM_FREQ_39M      (1<<0)

+#define SYS_CTRL_MEM_FREQ_26M      (0<<0)

+#define SYS_CTRL_DDR_MODE_EN_NORMAL_MODE (0<<4)

+#define SYS_CTRL_DDR_MODE_EN_DDR_MODE (1<<4)

+#define SYS_CTRL_DDR_FAST_CLK_POL_INVERT (1<<5)

+#define SYS_CTRL_DDR_FAST_CLK_POL_NORMAL (0<<5)

+#define SYS_CTRL_DDR_DQSL_O(n)     (((n)&31)<<6)

+#define SYS_CTRL_DDR_DQSU_O(n)     (((n)&31)<<11)

+#define SYS_CTRL_DDR_DQS_OEN(n)    (((n)&31)<<16)

+#define SYS_CTRL_DDR_DQSL_I(n)     (((n)&31)<<21)

+#define SYS_CTRL_DDR_DQSU_I(n)     (((n)&31)<<26)

+#define SYS_CTRL_MEM_REQ_DIV_UPDATE (1<<31)

+

+//Cfg_Clk_Out

+#define SYS_CTRL_CLKOUT_DIVIDER(n) (((n)&31)<<0)

+#define SYS_CTRL_CLKOUT_SEL_OSC    (0<<8)

+#define SYS_CTRL_CLKOUT_SEL_RF     (1<<8)

+#define SYS_CTRL_CLKOUT_SEL_DIVIDER (2<<8)

+

+//Cfg_Clk_Host_Uart

+#define SYS_CTRL_HOST_UART_DIVIDER(n) (((n)&0x3FF)<<0)

+#define SYS_CTRL_HOST_UART_DIVIDER_MASK (0x3FF<<0)

+#define SYS_CTRL_HOST_UART_DIVIDER_SHIFT (0)

+#define SYS_CTRL_HOST_UART_SEL_PLL_SLOW (0<<12)

+#define SYS_CTRL_HOST_UART_SEL_PLL_PLL (1<<12)

+

+//Cfg_Clk_Auxclk

+#define SYS_CTRL_AUXCLK_EN_DISABLE (0<<0)

+#define SYS_CTRL_AUXCLK_EN_ENABLE  (1<<0)

+

+//Cfg_AHB

+#define SYS_CTRL_SYS_NEW_ARBITRATION_ENABLE (1<<0)

+#define SYS_CTRL_SYS_NEW_ARBITRATION_DISABLE (0<<0)

+#define SYS_CTRL_ENABLE_SYS_MID_DMA_ENABLE (1<<1)

+#define SYS_CTRL_ENABLE_SYS_MID_DMA_DISABLE (0<<1)

+#define SYS_CTRL_ENABLE_SYS_MID_XCPU_ENABLE (1<<2)

+#define SYS_CTRL_ENABLE_SYS_MID_XCPU_DISABLE (0<<2)

+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_ENABLE (1<<3)

+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_DISABLE (0<<3)

+#define SYS_CTRL_ENABLE_SYS_MID_IFC_ENABLE (1<<4)

+#define SYS_CTRL_ENABLE_SYS_MID_IFC_DISABLE (0<<4)

+#define SYS_CTRL_ENABLE_SYS_MID_AXI2AHB_ENABLE (1<<5)

+#define SYS_CTRL_ENABLE_SYS_MID_AXI2AHB_DISABLE (0<<5)

+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_WD_ENABLE (1<<6)

+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_WD_DISABLE (0<<6)

+#define SYS_CTRL_BB_NEW_ARBITRATION_ENABLE (1<<16)

+#define SYS_CTRL_BB_NEW_ARBITRATION_DISABLE (0<<16)

+#define SYS_CTRL_ENABLE_BB_MID_IFC_ENABLE (1<<17)

+#define SYS_CTRL_ENABLE_BB_MID_IFC_DISABLE (0<<17)

+#define SYS_CTRL_ENABLE_BB_MID_BCPU_ENABLE (1<<18)

+#define SYS_CTRL_ENABLE_BB_MID_BCPU_DISABLE (0<<18)

+#define SYS_CTRL_ENABLE_BB_MID_AHB2AHB_ENABLE (1<<19)

+#define SYS_CTRL_ENABLE_BB_MID_AHB2AHB_DISABLE (0<<19)

+#define SYS_CTRL_SYS_ENABLE(n)     (((n)&0x3F)<<1)

+#define SYS_CTRL_SYS_ENABLE_MASK   (0x3F<<1)

+#define SYS_CTRL_SYS_ENABLE_SHIFT  (1)

+#define SYS_CTRL_BB_ENABLE(n)      (((n)&7)<<17)

+#define SYS_CTRL_BB_ENABLE_MASK    (7<<17)

+#define SYS_CTRL_BB_ENABLE_SHIFT   (17)

+

+//Ctrl_AHB

+#define SYS_CTRL_SPLIT_SYS_MID_DMA_NORMAL (1<<0)

+#define SYS_CTRL_SPLIT_SYS_MID_DMA_FORCE (0<<0)

+#define SYS_CTRL_SPLIT_SYS_MID_XCPU_NORMAL (1<<1)

+#define SYS_CTRL_SPLIT_SYS_MID_XCPU_FORCE (0<<1)

+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_NORMAL (1<<2)

+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_FORCE (0<<2)

+#define SYS_CTRL_SPLIT_SYS_MID_IFC_NORMAL (1<<3)

+#define SYS_CTRL_SPLIT_SYS_MID_IFC_FORCE (0<<3)

+#define SYS_CTRL_SPLIT_SYS_MID_AXI2AHB_NORMAL (1<<4)

+#define SYS_CTRL_SPLIT_SYS_MID_AXI2AHB_FORCE (0<<4)

+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_WD_NORMAL (1<<5)

+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_WD_FORCE (0<<5)

+#define SYS_CTRL_SPLIT_BB_MID_IFC_NORMAL (1<<16)

+#define SYS_CTRL_SPLIT_BB_MID_IFC_FORCE (0<<16)

+#define SYS_CTRL_SPLIT_BB_MID_BCPU_NORMAL (1<<17)

+#define SYS_CTRL_SPLIT_BB_MID_BCPU_FORCE (0<<17)

+#define SYS_CTRL_SPLIT_BB_MID_AHB2AHB_NORMAL (1<<18)

+#define SYS_CTRL_SPLIT_BB_MID_AHB2AHB_FORCE (0<<18)

+#define SYS_CTRL_SYS_FORCE_HSPLIT(n) (((n)&0x3F)<<0)

+#define SYS_CTRL_SYS_FORCE_HSPLIT_MASK (0x3F<<0)

+#define SYS_CTRL_SYS_FORCE_HSPLIT_SHIFT (0)

+#define SYS_CTRL_BB_FORCE_HSPLIT(n) (((n)&7)<<16)

+#define SYS_CTRL_BB_FORCE_HSPLIT_MASK (7<<16)

+#define SYS_CTRL_BB_FORCE_HSPLIT_SHIFT (16)

+

+//XCpu_Dbg_BKP

+#define SYS_CTRL_BKPT_EN           (1<<0)

+#define SYS_CTRL_BKPT_MODE(n)      (((n)&3)<<4)

+#define SYS_CTRL_BKPT_MODE_I       (0<<4)

+#define SYS_CTRL_BKPT_MODE_R       (1<<4)

+#define SYS_CTRL_BKPT_MODE_W       (2<<4)

+#define SYS_CTRL_BKPT_MODE_RW      (3<<4)

+#define SYS_CTRL_STALLED           (1<<8)

+

+//XCpu_Dbg_Addr

+#define SYS_CTRL_BREAKPOINT_ADDRESS(n) (((n)&0x3FFFFFF)<<0)

+

+//BCpu_Dbg_BKP

+//#define SYS_CTRL_BKPT_EN         (1<<0)

+//#define SYS_CTRL_BKPT_MODE(n)    (((n)&3)<<4)

+//#define SYS_CTRL_BKPT_MODE_I     (0<<4)

+//#define SYS_CTRL_BKPT_MODE_R     (1<<4)

+//#define SYS_CTRL_BKPT_MODE_W     (2<<4)

+//#define SYS_CTRL_BKPT_MODE_RW    (3<<4)

+//#define SYS_CTRL_STALLED         (1<<8)

+

+//BCpu_Dbg_Addr

+//#define SYS_CTRL_BREAKPOINT_ADDRESS(n) (((n)&0x3FFFFFF)<<0)

+

+//Cfg_Cpus_Cache_Ram_Disable

+#define SYS_CTRL_XCPU_USE_MODE     (1<<0)

+#define SYS_CTRL_XCPU_CLK_OFF_MODE (1<<1)

+#define SYS_CTRL_BCPU_USE_MODE     (1<<16)

+#define SYS_CTRL_BCPU_CLK_OFF_MODE (1<<17)

+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE(n) (((n)&3)<<0)

+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE_MASK (3<<0)

+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE_SHIFT (0)

+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE(n) (((n)&3)<<16)

+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE_MASK (3<<16)

+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE_SHIFT (16)

+

+//Reset_Cause

+#define SYS_CTRL_WATCHDOG_RESET_HAPPENED (1<<0)

+#define SYS_CTRL_WATCHDOG_RESET_NO (0<<0)

+#define SYS_CTRL_APSOFT_RESET_HAPPENED (1<<1)

+#define SYS_CTRL_APSOFT_RESET_NO   (0<<1)

+#define SYS_CTRL_GLOBALSOFT_RESET_HAPPENED (1<<4)

+#define SYS_CTRL_GLOBALSOFT_RESET_NO (0<<4)

+#define SYS_CTRL_HOSTDEBUG_RESET_HAPPENED (1<<5)

+#define SYS_CTRL_HOSTDEBUG_RESET_NO (0<<5)

+#define SYS_CTRL_ALARMCAUSE_HAPPENED (1<<6)

+#define SYS_CTRL_ALARMCAUSE_NO     (0<<6)

+#define SYS_CTRL_MEMCHECKDONE_MASK (1<<7)

+#define SYS_CTRL_MEMCHECKDONE_SHIFT (7)

+#define SYS_CTRL_MEMCHECKDONE_DONE (1<<7)

+#define SYS_CTRL_MEMCHECKDONE_RUNNING (0<<7)

+#define SYS_CTRL_BOOT_MODE(n)      (((n)&0xFFFF)<<8)

+#define SYS_CTRL_BOOT_MODE_MASK    (0xFFFF<<8)

+#define SYS_CTRL_BOOT_MODE_SHIFT   (8)

+#define SYS_CTRL_SW_BOOT_MODE(n)   (((n)&0x7F)<<24)

+#define SYS_CTRL_SW_BOOT_MODE_MASK (0x7F<<24)

+#define SYS_CTRL_SW_BOOT_MODE_SHIFT (24)

+#define SYS_CTRL_FONCTIONAL_TEST_MODE (1<<31)

+

+//WakeUp

+#define SYS_CTRL_FORCE_WAKEUP      (1<<0)

+

+//AP_Ctrl

+#define SYS_CTRL_AP_INT_STATUS     (1<<0)

+#define SYS_CTRL_AP_INT_MASK       (1<<16)

+#define SYS_CTRL_AP_DEEPSLEEP_EN   (1<<24)

+

+//Ignore_Charger

+#define SYS_CTRL_IGNORE_CHARGER    (1<<0)

+

+//Clk_SYS2_Mode

+#define SYS_CTRL_MODE_SYS_MPMC_AUTOMATIC (0<<0)

+#define SYS_CTRL_MODE_SYS_MPMC_MANUAL (1<<0)

+#define SYS_CTRL_MODE_SYS_MPMCREG_AUTOMATIC (0<<1)

+#define SYS_CTRL_MODE_SYS_MPMCREG_MANUAL (1<<1)

+#define SYS_CTRL_MODE_CLK_SYS2(n)  (((n)&3)<<0)

+#define SYS_CTRL_MODE_CLK_SYS2_MASK (3<<0)

+#define SYS_CTRL_MODE_CLK_SYS2_SHIFT (0)

+

+//Clk_SYS2_Enable

+#define SYS_CTRL_ENABLE_SYS_MPMC   (1<<0)

+#define SYS_CTRL_ENABLE_SYS_MPMCREG (1<<1)

+#define SYS_CTRL_ENABLE_SYS_DP_BB  (1<<2)

+#define SYS_CTRL_ENABLE_SYS_DP_WD  (1<<3)

+#define SYS_CTRL_ENABLE_SYS_DP_AP  (1<<4)

+#define SYS_CTRL_ENABLE_CLK_SYS2(n) (((n)&31)<<0)

+#define SYS_CTRL_ENABLE_CLK_SYS2_MASK (31<<0)

+#define SYS_CTRL_ENABLE_CLK_SYS2_SHIFT (0)

+

+//Clk_SYS2_Disable

+#define SYS_CTRL_DISABLE_SYS_MPMC  (1<<0)

+#define SYS_CTRL_DISABLE_SYS_MPMCREG (1<<1)

+#define SYS_CTRL_DISABLE_SYS_DP_BB (1<<2)

+#define SYS_CTRL_DISABLE_SYS_DP_WD (1<<3)

+#define SYS_CTRL_DISABLE_SYS_DP_AP (1<<4)

+#define SYS_CTRL_DISABLE_CLK_SYS2(n) (((n)&31)<<0)

+#define SYS_CTRL_DISABLE_CLK_SYS2_MASK (31<<0)

+#define SYS_CTRL_DISABLE_CLK_SYS2_SHIFT (0)

+

+//WD_Pll_Ctrl

+#define SYS_CTRL_WD_PLL_ENABLE     (1<<0)

+#define SYS_CTRL_WD_PLL_ENABLE_MASK (1<<0)

+#define SYS_CTRL_WD_PLL_ENABLE_SHIFT (0)

+#define SYS_CTRL_WD_PLL_ENABLE_POWER_DOWN (0<<0)

+#define SYS_CTRL_WD_PLL_ENABLE_ENABLE (1<<0)

+#define SYS_CTRL_WD_PLL_LOCK_RESET (1<<4)

+#define SYS_CTRL_WD_PLL_LOCK_RESET_MASK (1<<4)

+#define SYS_CTRL_WD_PLL_LOCK_RESET_SHIFT (4)

+#define SYS_CTRL_WD_PLL_LOCK_RESET_RESET (0<<4)

+#define SYS_CTRL_WD_PLL_LOCK_RESET_NO_RESET (1<<4)

+#define SYS_CTRL_WD_PLL_BYPASS     (1<<8)

+#define SYS_CTRL_WD_PLL_BYPASS_MASK (1<<8)

+#define SYS_CTRL_WD_PLL_BYPASS_SHIFT (8)

+#define SYS_CTRL_WD_PLL_BYPASS_PASS (0<<8)

+#define SYS_CTRL_WD_PLL_BYPASS_BYPASS (1<<8)

+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE (1<<12)

+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE_MASK (1<<12)

+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE_SHIFT (12)

+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE_ENABLE (1<<12)

+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE_DISABLE (0<<12)

+#define SYS_CTRL_PLL_WD_CFG(n)     (((n)&4369)<<0)

+#define SYS_CTRL_PLL_WD_CFG_MASK   (4369<<0)

+#define SYS_CTRL_PLL_WD_CFG_SHIFT  (0)

+

+//WD_Sel_Clock

+#define SYS_CTRL_WD_CLK_ADC_POL_INVERT (1<<0)

+#define SYS_CTRL_WD_CLK_ADC_POL_NORMAL (0<<0)

+#define SYS_CTRL_WD_SYS_SEL_FAST_SLOW (1<<4)

+#define SYS_CTRL_WD_SYS_SEL_FAST_FAST (0<<4)

+#define SYS_CTRL_WD_PLL_BYPASS_LOCK (1<<8)

+#define SYS_CTRL_WD_PLL_LOCKED     (1<<20)

+#define SYS_CTRL_WD_PLL_LOCKED_MASK (1<<20)

+#define SYS_CTRL_WD_PLL_LOCKED_SHIFT (20)

+#define SYS_CTRL_WD_PLL_LOCKED_LOCKED (1<<20)

+#define SYS_CTRL_WD_PLL_LOCKED_NOT_LOCKED (0<<20)

+#define SYS_CTRL_WD_FAST_SELECTED_L (1<<24)

+#define SYS_CTRL_WD_FAST_SELECTED_L_MASK (1<<24)

+#define SYS_CTRL_WD_FAST_SELECTED_L_SHIFT (24)

+

+//WD_Rst_Set

+#define SYS_CTRL_SET_WD_RST_WCPU   (1<<0)

+#define SYS_CTRL_SET_WD_RST_IRQ    (1<<1)

+#define SYS_CTRL_SET_WD_RST_DP     (1<<2)

+#define SYS_CTRL_SET_WD_RST_MODEM  (1<<3)

+#define SYS_CTRL_SET_WD_RST_A2A    (1<<4)

+#define SYS_CTRL_SET_WD_RST_IFC    (1<<5)

+#define SYS_CTRL_SET_WD_RST_SDMA   (1<<6)

+#define SYS_CTRL_SET_WD_RST_SLPC   (1<<7)

+#define SYS_CTRL_SET_WD_RST_SLPT   (1<<8)

+#define SYS_CTRL_SET_WD_RST_SPI1   (1<<9)

+#define SYS_CTRL_SET_WD_RST_SPI2   (1<<10)

+#define SYS_CTRL_SET_WD_RST_RFIF   (1<<11)

+#define SYS_CTRL_SET_WD_RST_COMREGS (1<<12)

+#define SYS_CTRL_SET_WD_RST_TIMER  (1<<13)

+#define SYS_CTRL_SET_WD_RST_MPMC   (1<<14)

+#define SYS_CTRL_SET_WD_RST_FULL   (1<<31)

+#define SYS_CTRL_SET_WD_RST(n)     (((n)&0x7FFF)<<0)

+#define SYS_CTRL_SET_WD_RST_MASK   (0x7FFF<<0)

+#define SYS_CTRL_SET_WD_RST_SHIFT  (0)

+

+//WD_Rst_Clr

+#define SYS_CTRL_CLR_WD_RST_WCPU   (1<<0)

+#define SYS_CTRL_CLR_WD_RST_IRQ    (1<<1)

+#define SYS_CTRL_CLR_WD_RST_DP     (1<<2)

+#define SYS_CTRL_CLR_WD_RST_MODEM  (1<<3)

+#define SYS_CTRL_CLR_WD_RST_A2A    (1<<4)

+#define SYS_CTRL_CLR_WD_RST_IFC    (1<<5)

+#define SYS_CTRL_CLR_WD_RST_SDMA   (1<<6)

+#define SYS_CTRL_CLR_WD_RST_SLPC   (1<<7)

+#define SYS_CTRL_CLR_WD_RST_SLPT   (1<<8)

+#define SYS_CTRL_CLR_WD_RST_SPI1   (1<<9)

+#define SYS_CTRL_CLR_WD_RST_SPI2   (1<<10)

+#define SYS_CTRL_CLR_WD_RST_RFIF   (1<<11)

+#define SYS_CTRL_CLR_WD_RST_COMREGS (1<<12)

+#define SYS_CTRL_CLR_WD_RST_TIMER  (1<<13)

+#define SYS_CTRL_CLR_WD_RST_MPMC   (1<<14)

+#define SYS_CTRL_CLR_WD_RST_FULL   (1<<31)

+#define SYS_CTRL_CLR_WD_RST(n)     (((n)&0x7FFF)<<0)

+#define SYS_CTRL_CLR_WD_RST_MASK   (0x7FFF<<0)

+#define SYS_CTRL_CLR_WD_RST_SHIFT  (0)

+

+//AP_Rst_Set

+#define SYS_CTRL_SET_AP_RST_0      (1<<0)

+#define SYS_CTRL_SET_AP_RST_1      (1<<1)

+#define SYS_CTRL_SET_AP_RST_2      (1<<2)

+#define SYS_CTRL_SET_AP_RST_3      (1<<3)

+#define SYS_CTRL_SET_AP_RST_4      (1<<4)

+#define SYS_CTRL_SET_AP_RST(n)     (((n)&31)<<0)

+#define SYS_CTRL_SET_AP_RST_MASK   (31<<0)

+#define SYS_CTRL_SET_AP_RST_SHIFT  (0)

+

+//AP_Rst_Clr

+#define SYS_CTRL_CLR_AP_RST_0      (1<<0)

+#define SYS_CTRL_CLR_AP_RST_1      (1<<1)

+#define SYS_CTRL_CLR_AP_RST_2      (1<<2)

+#define SYS_CTRL_CLR_AP_RST_3      (1<<3)

+#define SYS_CTRL_CLR_AP_RST_4      (1<<4)

+#define SYS_CTRL_CLR_AP_RST(n)     (((n)&31)<<0)

+#define SYS_CTRL_CLR_AP_RST_MASK   (31<<0)

+#define SYS_CTRL_CLR_AP_RST_SHIFT  (0)

+

+//Clk_WD_Mode

+#define SYS_CTRL_MODE_WD_WCPU      (1<<0)

+#define SYS_CTRL_MODE_WD_AMBA_AUTOMATIC (0<<1)

+#define SYS_CTRL_MODE_WD_AMBA_MANUAL (1<<1)

+#define SYS_CTRL_MODE_WD_PCLK_CONF_AUTOMATIC (0<<2)

+#define SYS_CTRL_MODE_WD_PCLK_CONF_MANUAL (1<<2)

+#define SYS_CTRL_MODE_WD_PCLK_DATA_AUTOMATIC (0<<3)

+#define SYS_CTRL_MODE_WD_PCLK_DATA_MANUAL (1<<3)

+#define SYS_CTRL_MODE_WD_A2A_AUTOMATIC (0<<4)

+#define SYS_CTRL_MODE_WD_A2A_MANUAL (1<<4)

+#define SYS_CTRL_MODE_WD_IFC_CH_SPI_AUTOMATIC (0<<5)

+#define SYS_CTRL_MODE_WD_IFC_CH_SPI_MANUAL (1<<5)

+#define SYS_CTRL_MODE_WD_MPMC_AUTOMATIC (0<<6)

+#define SYS_CTRL_MODE_WD_MPMC_MANUAL (1<<6)

+#define SYS_CTRL_MODE_WDD_OSC_AUTOMATIC (0<<7)

+#define SYS_CTRL_MODE_WDD_OSC_MANUAL (1<<7)

+#define SYS_CTRL_MODE_CLK_WD(n)    (((n)&0x7F)<<1)

+#define SYS_CTRL_MODE_CLK_WD_MASK  (0x7F<<1)

+#define SYS_CTRL_MODE_CLK_WD_SHIFT (1)

+

+//Clk_WD_Enable

+#define SYS_CTRL_ENABLE_WD_WCPU    (1<<0)

+#define SYS_CTRL_ENABLE_WD_AMBA    (1<<1)

+#define SYS_CTRL_ENABLE_WD_PCLK_CONF (1<<2)

+#define SYS_CTRL_ENABLE_WD_PCLK_DATA (1<<3)

+#define SYS_CTRL_ENABLE_WD_A2A     (1<<4)

+#define SYS_CTRL_ENABLE_WD_IFC_CH_SPI (1<<5)

+#define SYS_CTRL_ENABLE_WD_MPMC    (1<<6)

+#define SYS_CTRL_ENABLE_WDD_OSC    (1<<7)

+#define SYS_CTRL_ENABLE_WD_IRQ     (1<<8)

+#define SYS_CTRL_ENABLE_WD_AXI     (1<<9)

+#define SYS_CTRL_ENABLE_WD_DP      (1<<10)

+#define SYS_CTRL_ENABLE_WD_MODEM   (1<<11)

+#define SYS_CTRL_ENABLE_WD_COM_REGS (1<<12)

+#define SYS_CTRL_ENABLE_WD_TIMER   (1<<13)

+#define SYS_CTRL_ENABLE_WD_SDMA    (1<<14)

+#define SYS_CTRL_ENABLE_WD_SLPC    (1<<15)

+#define SYS_CTRL_ENABLE_WD_SLPT    (1<<16)

+#define SYS_CTRL_ENABLE_WD_SPI1    (1<<17)

+#define SYS_CTRL_ENABLE_WD_SPI2    (1<<18)

+#define SYS_CTRL_ENABLE_WD_RFIF    (1<<19)

+#define SYS_CTRL_ENABLE_CLK_WD(n)  (((n)&0xFFFFF)<<0)

+#define SYS_CTRL_ENABLE_CLK_WD_MASK (0xFFFFF<<0)

+#define SYS_CTRL_ENABLE_CLK_WD_SHIFT (0)

+

+//Clk_WD_Disable

+#define SYS_CTRL_DISABLE_WD_WCPU   (1<<0)

+#define SYS_CTRL_DISABLE_WD_AMBA   (1<<1)

+#define SYS_CTRL_DISABLE_WD_PCLK_CONF (1<<2)

+#define SYS_CTRL_DISABLE_WD_PCLK_DATA (1<<3)

+#define SYS_CTRL_DISABLE_WD_A2A    (1<<4)

+#define SYS_CTRL_DISABLE_WD_IFC_CH_SPI (1<<5)

+#define SYS_CTRL_DISABLE_WD_MPMC   (1<<6)

+#define SYS_CTRL_DISABLE_WDD_OSC   (1<<7)

+#define SYS_CTRL_DISABLE_WD_IRQ    (1<<8)

+#define SYS_CTRL_DISABLE_WD_AXI    (1<<9)

+#define SYS_CTRL_DISABLE_WD_DP     (1<<10)

+#define SYS_CTRL_DISABLE_WD_MODEM  (1<<11)

+#define SYS_CTRL_DISABLE_WD_COM_REGS (1<<12)

+#define SYS_CTRL_DISABLE_WD_TIMER  (1<<13)

+#define SYS_CTRL_DISABLE_WD_SDMA   (1<<14)

+#define SYS_CTRL_DISABLE_WD_SLPC   (1<<15)

+#define SYS_CTRL_DISABLE_WD_SLPT   (1<<16)

+#define SYS_CTRL_DISABLE_WD_SPI1   (1<<17)

+#define SYS_CTRL_DISABLE_WD_SPI2   (1<<18)

+#define SYS_CTRL_DISABLE_WD_RFIF   (1<<19)

+#define SYS_CTRL_DISABLE_CLK_WD(n) (((n)&0xFFFFF)<<0)

+#define SYS_CTRL_DISABLE_CLK_WD_MASK (0xFFFFF<<0)

+#define SYS_CTRL_DISABLE_CLK_WD_SHIFT (0)

+

+//Cfg_Clk_MPMC

+#define SYS_CTRL_MPMC_FREQ(n)      (((n)&15)<<0)

+#define SYS_CTRL_MPMC_FREQ_MASK    (15<<0)

+#define SYS_CTRL_MPMC_FREQ_SHIFT   (0)

+#define SYS_CTRL_MPMC_FREQ_312M    (13<<0)

+#define SYS_CTRL_MPMC_FREQ_250M    (12<<0)

+#define SYS_CTRL_MPMC_FREQ_208M    (11<<0)

+#define SYS_CTRL_MPMC_FREQ_178M    (10<<0)

+#define SYS_CTRL_MPMC_FREQ_156M    (9<<0)

+#define SYS_CTRL_MPMC_FREQ_139M    (8<<0)

+#define SYS_CTRL_MPMC_FREQ_125M    (7<<0)

+#define SYS_CTRL_MPMC_FREQ_113M    (6<<0)

+#define SYS_CTRL_MPMC_FREQ_104M    (5<<0)

+#define SYS_CTRL_MPMC_FREQ_89M     (4<<0)

+#define SYS_CTRL_MPMC_FREQ_78M     (3<<0)

+#define SYS_CTRL_MPMC_FREQ_52M     (2<<0)

+#define SYS_CTRL_MPMC_FREQ_39M     (1<<0)

+#define SYS_CTRL_MPMC_FREQ_26M     (0<<0)

+#define SYS_CTRL_CLK_MPMC_DELAY(n) (((n)&31)<<8)

+#define SYS_CTRL_CLK_MPMC_DELAY_POL (1<<13)

+#define SYS_CTRL_CLK_MPMC_FEEDBACK(n) (((n)&31)<<14)

+#define SYS_CTRL_CLK_MPMC_FEEDBACK_POL (1<<19)

+#define SYS_CTRL_MPMC_REQ_DIV_UPDATE (1<<31)

+

+//Cfg_MPMC_DQS

+#define SYS_CTRL_MPMC_DQSL_O(n)    (((n)&31)<<0)

+#define SYS_CTRL_MPMC_DQSU_O(n)    (((n)&31)<<6)

+#define SYS_CTRL_MPMC_DQS_OEN(n)   (((n)&31)<<12)

+#define SYS_CTRL_MPMC_DQSL_I(n)    (((n)&31)<<18)

+#define SYS_CTRL_MPMC_DQSU_I(n)    (((n)&31)<<24)

+

+//Cfg_Reserve

+#define SYS_CTRL_RESERVE(n)        (((n)&0x3FFF)<<0)

+#define SYS_CTRL_AUIFC_CH0_IRQ_MASK (1<<14)

+#define SYS_CTRL_AUIFC_CH1_IRQ_MASK (1<<15)

+#define SYS_CTRL_RESERVE2(n)       (((n)&0xFFFF)<<16)

+

+

+

+

+

+#endif

+

diff --git a/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8850e.h b/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8850e.h
new file mode 100644
index 0000000000..f0928a1d6e
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_md_sysctrl_rda8850e.h
@@ -0,0 +1,1363 @@
+#ifndef _REG_MD_SYSCTRL_H_
+#define _REG_MD_SYSCTRL_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+
+// ============================================================================
+// CPU_ID_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// CPU IDs
+    XCPU                                        = 0x00000000,
+    BCPU                                        = 0x00000001,
+    WCPU                                        = 0x00000002
+} CPU_ID_T;
+
+#define NB_MODEM_CPU                            (3)
+
+// ============================================================================
+// SYS_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// System side System clocks
+    SYS_XCPU                                    = 0x00000000,
+    SYS_XCPU_INT                                = 0x00000001,
+    SYS_PCLK_CONF                               = 0x00000002,
+    SYS_PCLK_DATA                               = 0x00000003,
+    SYS_AMBA                                    = 0x00000004,
+    SYS_DMA                                     = 0x00000005,
+    SYS_EBC                                     = 0x00000006,
+    SYS_IFC_CH0                                 = 0x00000007,
+    SYS_IFC_CH1                                 = 0x00000008,
+    SYS_IFC_CH2                                 = 0x00000009,
+    SYS_IFC_CH3                                 = 0x0000000A,
+    SYS_IFC_DBG                                 = 0x0000000B,
+    SYS_A2A                                     = 0x0000000C,
+    SYS_AXI2AHB                                 = 0x0000000D,
+    SYS_AHB2AXI                                 = 0x0000000E,
+    SYS_EXT_AHB                                 = 0x0000000F,
+    SYS_DEBUG_UART                              = 0x00000010,
+    SYS_DBGHST                                  = 0x00000011,
+    SYS_A2A_WD                                  = 0x00000012,
+/// System side divided clock (either divided by module or by sys_ctrl)
+    SYSD_SCI1                                   = 0x00000013,
+    SYSD_SCI2                                   = 0x00000014,
+    SYSD_SCI3                                   = 0x00000015,
+    SYSD_RF_SPI                                 = 0x00000016,
+    SYSD_OSC                                    = 0x00000017,
+/// the following don't have an auto enable
+    SYS_GPIO                                    = 0x00000018,
+    SYS_IRQ                                     = 0x00000019,
+    SYS_TCU                                     = 0x0000001A,
+    SYS_TIMER                                   = 0x0000001B,
+    SYS_COM_REGS                                = 0x0000001C,
+/// the following are sharing their enable
+    SYS_SCI1                                    = 0x0000001D,
+    SYS_SCI2                                    = 0x0000001E,
+    SYS_SCI3                                    = 0x0000001F,
+/// keep last
+    SYS_NOGATE                                  = 0x00000020
+} SYS_CLKS_T;
+
+#define NB_SYS_CLK_XCPU                         (2)
+#define NB_SYS_CLK_AEN                          (24)
+#define NB_SYS_CLK_EN                           (29)
+#define NB_SYS_CLK                              (33)
+
+// ============================================================================
+// SYS2_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// WCDMA Baseband side System clocks
+    SYS_MPMC                                    = 0x00000000,
+    SYS_MPMCREG                                 = 0x00000001,
+/// the following don't have an auto enable
+    SYS_DP_BB                                   = 0x00000002,
+    SYS_DP_WD                                   = 0x00000003,
+    SYS_DP_AP                                   = 0x00000004
+} SYS2_CLKS_T;
+
+#define NB_SYS2_CLK_AEN                         (2)
+#define NB_SYS2_CLK_EN                          (5)
+#define NB_SYS2_CLK                             (5)
+
+// ============================================================================
+// PER_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// System side divided clock (either divided by module or by sys_ctrl)
+    PERD_SPI1                                   = 0x00000000,
+/// System side divided clock (either divided by module or by sys_ctrl)
+    PERD_SPI2                                   = 0x00000001,
+    PER_SPY                                     = 0x00000002,
+    PER_TEST                                    = 0x00000003
+} PER_CLKS_T;
+
+#define NB_PER_CLK_AEN                          (2)
+#define NB_PER_CLK_EN                           (4)
+#define NB_PER_CLK                              (4)
+
+// ============================================================================
+// BB_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// Baseband side System clocks
+    BB_BCPU                                     = 0x00000000,
+    BB_BCPU_INT                                 = 0x00000001,
+    BB_AMBA                                     = 0x00000002,
+    BB_PCLK_CONF                                = 0x00000003,
+    BB_PCLK_DATA                                = 0x00000004,
+    BB_EXCOR                                    = 0x00000005,
+    BB_IFC_CH2                                  = 0x00000006,
+    BB_IFC_CH3                                  = 0x00000007,
+    BB_SRAM                                     = 0x00000008,
+    BB_A2A                                      = 0x00000009,
+    BB_ITLV                                     = 0x0000000A,
+    BB_VITERBI                                  = 0x0000000B,
+    BB_CIPHER                                   = 0x0000000C,
+    BB_RF_IF                                    = 0x0000000D,
+    BB_COPRO                                    = 0x0000000E,
+    BB_CP2_REG                                  = 0x0000000F,
+    BB_XCOR                                     = 0x00000010,
+    BB_EVITAC                                   = 0x00000011,
+    BB_ROM                                      = 0x00000012,
+    BB_MPMC                                     = 0x00000013,
+/// the following don't have an auto enable
+    BB_IRQ                                      = 0x00000014,
+    BB_COM_REGS                                 = 0x00000015,
+    BB_CORDIC                                   = 0x00000016,
+    BB_DP                                       = 0x00000017
+} BB_CLKS_T;
+
+#define NB_BB_CLK_AEN                           (20)
+#define NB_BB_CLK_EN                            (24)
+#define NB_BB_CLK                               (24)
+
+// ============================================================================
+// WD_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// WCDMA Baseband side System clocks
+    WD_WCPU                                     = 0x00000000,
+    WD_AMBA                                     = 0x00000001,
+    WD_PCLK_CONF                                = 0x00000002,
+    WD_PCLK_DATA                                = 0x00000003,
+    WD_A2A                                      = 0x00000004,
+    WD_IFC_CH_SPI                               = 0x00000005,
+    WD_MPMC                                     = 0x00000006,
+    WDD_OSC                                     = 0x00000007,
+/// the following don't have an auto enable
+    WD_IRQ                                      = 0x00000008,
+    WD_AXI                                      = 0x00000009,
+    WD_DP                                       = 0x0000000A,
+    WD_MODEM                                    = 0x0000000B,
+    WD_COM_REGS                                 = 0x0000000C,
+    WD_TIMER                                    = 0x0000000D,
+    WD_SDMA                                     = 0x0000000E,
+    WD_SLPC                                     = 0x0000000F,
+    WD_SLPT                                     = 0x00000010,
+    WD_SPI1                                     = 0x00000011,
+    WD_SPI2                                     = 0x00000012,
+    WD_RFIF                                     = 0x00000013
+} WD_CLKS_T;
+
+#define NB_WD_CLK_AEN                           (8)
+#define NB_WD_CLK_EN                            (20)
+#define NB_WD_CLK                               (20)
+/// Other clocks
+/// clocks with auto enble
+/// the debug host clock auto enable is not used in host mode, only in uart mode
+#define OC_HOST_UART                            (0)
+
+// ============================================================================
+// OTHER_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+    OC_DEBUG_UART                               = 0x00000000,
+    OC_RF_RX                                    = 0x00000001,
+    OC_RF_TX                                    = 0x00000002,
+    OC_MEM_BRIDGE                               = 0x00000003,
+/// the following don't have an auto enable
+    OC_LPS                                      = 0x00000004,
+    OC_GPIO                                     = 0x00000005,
+    OC_CLK_OUT                                  = 0x00000006,
+    OC_MEM_CLK_OUT                              = 0x00000007,
+    OC_TCU                                      = 0x00000008,
+    OC_WD_CHIP                                  = 0x00000009,
+    OC_WD_ADC                                   = 0x0000000A,
+    OC_WD_TURBO                                 = 0x0000000B,
+    OC_WD_OSC                                   = 0x0000000C,
+    OC_MPMC                                     = 0x0000000D
+} OTHER_CLKS_T;
+
+#define NB_OTHER_CLK_AEN                        (4)
+#define NB_OTHER_CLK_EN                         (14)
+#define NB_OTHER_CLK                            (14)
+
+// ============================================================================
+// RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// System side resets
+    RST_XCPU                                    = 0x00000000,
+    RST_SYS_IRQ                                 = 0x00000001,
+    RST_SYS_A2A                                 = 0x00000002,
+    RST_SYS_AHB2AXI                             = 0x00000003,
+    RST_SYS_AXI2AHB                             = 0x00000004,
+    RST_DMA                                     = 0x00000005,
+    RST_TIMER                                   = 0x00000006,
+    RST_TCU                                     = 0x00000007,
+    RST_GPIO                                    = 0x00000008,
+    RST_CFG                                     = 0x00000009,
+    RST_SPI1                                    = 0x0000000A,
+    RST_SPI2                                    = 0x0000000B,
+    RST_RF_SPI                                  = 0x0000000C,
+    RST_SCI1                                    = 0x0000000D,
+    RST_SCI2                                    = 0x0000000E,
+    RST_SCI3                                    = 0x0000000F,
+    RST_SPY                                     = 0x00000010,
+    RST_MEM_BRIDGE                              = 0x00000011,
+    RST_EXT_AHB                                 = 0x00000012,
+    RST_DP_BB                                   = 0x00000013,
+    RST_DP_AP                                   = 0x00000014,
+    RST_COMREGS                                 = 0x00000015,
+    RST_COMREGS_AP                              = 0x00000016,
+    RST_AP_CLKEN                                = 0x00000017,
+    RST_AP_RST                                  = 0x00000018,
+    RST_MEM_CHK                                 = 0x00000019,
+    RST_MPMC                                    = 0x0000001A,
+    RST_SYS_A2A_WD                              = 0x0000001B,
+    RST_COMREGS_WD                              = 0x0000001C,
+    RST_BCPU                                    = 0x0000001D,
+    RST_BB_IRQ                                  = 0x0000001E,
+    RST_BB_A2A                                  = 0x0000001F,
+    RST_BB_IFC                                  = 0x00000020,
+    RST_BB_SRAM                                 = 0x00000021,
+    RST_ITLV                                    = 0x00000022,
+    RST_VITERBI                                 = 0x00000023,
+    RST_CIPHER                                  = 0x00000024,
+    RST_XCOR                                    = 0x00000025,
+    RST_COPRO                                   = 0x00000026,
+    RST_RF_IF                                   = 0x00000027,
+    RST_EXCOR                                   = 0x00000028,
+    RST_EVITAC                                  = 0x00000029,
+    RST_CORDIC                                  = 0x0000002A,
+    RST_TCU_BB                                  = 0x0000002B,
+    RST_BB_DP                                   = 0x0000002C,
+    RST_BB_ROM                                  = 0x0000002D,
+    RST_MPMC_BB                                 = 0x0000002E,
+    RST_BB_FULL                                 = 0x0000002F,
+    RST_SYS_FULL                                = 0x00000030
+} RESETS_T;
+
+#define NB_SRST                                 (29)
+/// Baseband side resets
+#define BOUND_BRST_FIRST                        (29)
+#define BOUND_BRST_AFTER                        (47)
+/// The following reset does not have register
+#define NR_RST_REG                              (48)
+#define NB_RST                                  (49)
+#define NB_BRST                                 (BOUND_BRST_AFTER-BOUND_BRST_FIRST)
+
+// ============================================================================
+// RESET_OTHERS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// Reset Other : resync on corresponding clock other
+    RSTO_DBG_HOST                               = 0x00000000,
+    RSTO_RF_RX                                  = 0x00000001,
+    RSTO_RF_TX                                  = 0x00000002,
+    RSTO_MEM_BRIDGE                             = 0x00000003,
+    RSTO_LPS                                    = 0x00000004,
+    RSTO_GPIO                                   = 0x00000005,
+    RSTO_WDTIMER                                = 0x00000006,
+    RSTO_TCU                                    = 0x00000007,
+    RSTO_MPMC                                   = 0x00000008
+} RESET_OTHERS_T;
+
+#define BOUND_RSTO_RF_FIRST                     (1)
+#define BOUND_RSTO_RF_AFTER                     (3)
+#define NB_RSTO                                 (9)
+
+// ============================================================================
+// WD_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// WD side resets
+    WD_RST_WCPU                                 = 0x00000000,
+    WD_RST_IRQ                                  = 0x00000001,
+    WD_RST_DP                                   = 0x00000002,
+    WD_RST_MODEM                                = 0x00000003,
+    WD_RST_A2A                                  = 0x00000004,
+    WD_RST_IFC                                  = 0x00000005,
+    WD_RST_SDMA                                 = 0x00000006,
+    WD_RST_SLPC                                 = 0x00000007,
+    WD_RST_SLPT                                 = 0x00000008,
+    WD_RST_SPI1                                 = 0x00000009,
+    WD_RST_SPI2                                 = 0x0000000A,
+    WD_RST_RFIF                                 = 0x0000000B,
+    WD_RST_COMREGS                              = 0x0000000C,
+    WD_RST_TIMER                                = 0x0000000D,
+    WD_RST_MPMC                                 = 0x0000000E,
+    WD_RST_FULL                                 = 0x0000000F
+} WD_RESETS_T;
+
+#define NB_WD_RST_BOUND                         (15)
+#define NB_WD_RST                               (16)
+
+// ============================================================================
+// AP_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP side resets
+    AP_RST_0                                    = 0x00000000,
+    AP_RST_1                                    = 0x00000001,
+    AP_RST_2                                    = 0x00000002,
+    AP_RST_3                                    = 0x00000003,
+    AP_RST_4                                    = 0x00000004
+} AP_RESETS_T;
+
+#define NB_AP_RST_BOUND                         (5)
+#define NB_AP_RST                               (5)
+/// For REG_DBG protect lock/unlock value
+#define SYS_CTRL_PROTECT_LOCK                   (0XA50000)
+#define SYS_CTRL_PROTECT_UNLOCK                 (0XA50001)
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+// ============================================================================
+// SYS_CTRL_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef volatile struct
+{
+    /// <strong>This register is used to Lock and Unlock the protected registers.</strong>
+    REG32                          REG_DBG;                      //0x00000000
+    /// This register is protected.
+    REG32                          Sys_Rst_Set;                  //0x00000004
+    REG32                          Sys_Rst_Clr;                  //0x00000008
+    /// This register is protected.
+    REG32                          BB_Rst_Set;                   //0x0000000C
+    REG32                          BB_Rst_Clr;                   //0x00000010
+    REG32                          Clk_Sys_Mode;                 //0x00000014
+    REG32                          Clk_Sys_Enable;               //0x00000018
+    /// This register is protected.
+    REG32                          Clk_Sys_Disable;              //0x0000001C
+    REG32                          Clk_Per_Mode;                 //0x00000020
+    REG32                          Clk_Per_Enable;               //0x00000024
+    /// This register is protected.
+    REG32                          Clk_Per_Disable;              //0x00000028
+    REG32                          Clk_BB_Mode;                  //0x0000002C
+    REG32                          Clk_BB_Enable;                //0x00000030
+    /// This register is protected.
+    REG32                          Clk_BB_Disable;               //0x00000034
+    REG32                          Clk_Other_Mode;               //0x00000038
+    REG32                          Clk_Other_Enable;             //0x0000003C
+    /// This register is protected.
+    REG32                          Clk_Other_Disable;            //0x00000040
+    /// Register protected by Write_Unlocked_H.
+    REG32                          Pll_Ctrl;                     //0x00000044
+    /// This register is protected.
+    REG32                          Sel_Clock;                    //0x00000048
+    REG32                          Cfg_Clk_Sys;                  //0x0000004C
+    REG32                          Cfg_Clk_Mem_Bridge;           //0x00000050
+    /// This register is protected.
+    REG32                          Cfg_Clk_Out;                  //0x00000054
+    REG32                          Cfg_Clk_Host_Uart;            //0x00000058
+    REG32                          Cfg_Clk_Auxclk;               //0x0000005C
+    /// This register is protected.
+    REG32                          Cfg_AHB;                      //0x00000060
+    /// This register is protected. Used to unsplit masters manualy.
+    REG32                          Ctrl_AHB;                     //0x00000064
+    REG32                          XCpu_Dbg_BKP;                 //0x00000068
+    REG32                          XCpu_Dbg_Addr;                //0x0000006C
+    REG32                          BCpu_Dbg_BKP;                 //0x00000070
+    REG32                          BCpu_Dbg_Addr;                //0x00000074
+    REG32                          Cfg_Cpus_Cache_Ram_Disable;   //0x00000078
+    REG32                          Reset_Cause;                  //0x0000007C
+    /// This register is protected.
+    REG32                          WakeUp;                       //0x00000080
+    REG32                          AP_Ctrl;                      //0x00000084
+    /// This register is protected.
+    REG32                          Ignore_Charger;               //0x00000088
+    REG32                          Clk_SYS2_Mode;                //0x0000008C
+    REG32                          Clk_SYS2_Enable;              //0x00000090
+    /// This register is protected.
+    REG32                          Clk_SYS2_Disable;             //0x00000094
+    /// Register protected by Write_Unlocked_H.
+    REG32                          WD_Pll_Ctrl;                  //0x00000098
+    /// This register is protected.
+    REG32                          WD_Sel_Clock;                 //0x0000009C
+    /// This register is protected.
+    REG32                          WD_Rst_Set;                   //0x000000A0
+    REG32                          WD_Rst_Clr;                   //0x000000A4
+    /// This register is protected.
+    REG32                          AP_Rst_Set;                   //0x000000A8
+    REG32                          AP_Rst_Clr;                   //0x000000AC
+    REG32                          Clk_WD_Mode;                  //0x000000B0
+    REG32                          Clk_WD_Enable;                //0x000000B4
+    /// This register is protected.
+    REG32                          Clk_WD_Disable;               //0x000000B8
+    REG32                          Cfg_Clk_MPMC;                 //0x000000BC
+    REG32                          Cfg_MPMC_DQS;                 //0x000000C0
+    REG32 Reserved_000000C4[14];                //0x000000C4
+    /// This register is reserved.
+    REG32                          Cfg_Reserve;                  //0x000000FC
+} HWP_SYS_CTRL_T;
+
+#define hwp_sysCtrlMd               ((HWP_SYS_CTRL_T*)(RDA_MD_SYSCTRL_BASE))
+
+
+//REG_DBG
+#define SYS_CTRL_SCRATCH(n)        (((n)&0xFFFF)<<0)
+#define SYS_CTRL_WRITE_UNLOCK_STATUS (1<<30)
+#define SYS_CTRL_WRITE_UNLOCK      (1<<31)
+
+//Sys_Rst_Set
+#define SYS_CTRL_SET_RST_XCPU      (1<<0)
+#define SYS_CTRL_SET_RST_SYS_IRQ   (1<<1)
+#define SYS_CTRL_SET_RST_SYS_A2A   (1<<2)
+#define SYS_CTRL_SET_RST_SYS_AHB2AXI (1<<3)
+#define SYS_CTRL_SET_RST_SYS_AXI2AHB (1<<4)
+#define SYS_CTRL_SET_RST_DMA       (1<<5)
+#define SYS_CTRL_SET_RST_TIMER     (1<<6)
+#define SYS_CTRL_SET_RST_TCU       (1<<7)
+#define SYS_CTRL_SET_RST_GPIO      (1<<8)
+#define SYS_CTRL_SET_RST_CFG       (1<<9)
+#define SYS_CTRL_SET_RST_SPI1      (1<<10)
+#define SYS_CTRL_SET_RST_SPI2      (1<<11)
+#define SYS_CTRL_SET_RST_RF_SPI    (1<<12)
+#define SYS_CTRL_SET_RST_SCI1      (1<<13)
+#define SYS_CTRL_SET_RST_SCI2      (1<<14)
+#define SYS_CTRL_SET_RST_SCI3      (1<<15)
+#define SYS_CTRL_SET_RST_SPY       (1<<16)
+#define SYS_CTRL_SET_RST_MEM_BRIDGE (1<<17)
+#define SYS_CTRL_SET_RST_EXT_AHB   (1<<18)
+#define SYS_CTRL_SET_RST_DP_BB     (1<<19)
+#define SYS_CTRL_SET_RST_DP_AP     (1<<20)
+#define SYS_CTRL_SET_RST_COMREGS   (1<<21)
+#define SYS_CTRL_SET_RST_COMREGS_AP (1<<22)
+#define SYS_CTRL_SET_RST_AP_CLKEN  (1<<23)
+#define SYS_CTRL_SET_RST_AP_RST    (1<<24)
+#define SYS_CTRL_SET_RST_MEM_CHK   (1<<25)
+#define SYS_CTRL_SET_RST_MPMC      (1<<26)
+#define SYS_CTRL_SET_RST_SYS_A2A_WD (1<<27)
+#define SYS_CTRL_SET_RST_COMREGS_WD (1<<28)
+#define SYS_CTRL_SET_RST_OUT       (1<<30)
+#define SYS_CTRL_SOFT_RST          (1<<31)
+#define SYS_CTRL_SET_SYS_RST(n)    (((n)&0x1FFFFFFF)<<0)
+#define SYS_CTRL_SET_SYS_RST_MASK  (0x1FFFFFFF<<0)
+#define SYS_CTRL_SET_SYS_RST_SHIFT (0)
+
+//Sys_Rst_Clr
+#define SYS_CTRL_CLR_RST_XCPU      (1<<0)
+#define SYS_CTRL_CLR_RST_SYS_IRQ   (1<<1)
+#define SYS_CTRL_CLR_RST_SYS_A2A   (1<<2)
+#define SYS_CTRL_CLR_RST_SYS_AHB2AXI (1<<3)
+#define SYS_CTRL_CLR_RST_SYS_AXI2AHB (1<<4)
+#define SYS_CTRL_CLR_RST_DMA       (1<<5)
+#define SYS_CTRL_CLR_RST_TIMER     (1<<6)
+#define SYS_CTRL_CLR_RST_TCU       (1<<7)
+#define SYS_CTRL_CLR_RST_GPIO      (1<<8)
+#define SYS_CTRL_CLR_RST_CFG       (1<<9)
+#define SYS_CTRL_CLR_RST_SPI1      (1<<10)
+#define SYS_CTRL_CLR_RST_SPI2      (1<<11)
+#define SYS_CTRL_CLR_RST_RF_SPI    (1<<12)
+#define SYS_CTRL_CLR_RST_SCI1      (1<<13)
+#define SYS_CTRL_CLR_RST_SCI2      (1<<14)
+#define SYS_CTRL_CLR_RST_SCI3      (1<<15)
+#define SYS_CTRL_CLR_RST_SPY       (1<<16)
+#define SYS_CTRL_CLR_RST_MEM_BRIDGE (1<<17)
+#define SYS_CTRL_CLR_RST_EXT_AHB   (1<<18)
+#define SYS_CTRL_CLR_RST_DP_BB     (1<<19)
+#define SYS_CTRL_CLR_RST_DP_AP     (1<<20)
+#define SYS_CTRL_CLR_RST_COMREGS   (1<<21)
+#define SYS_CTRL_CLR_RST_COMREGS_AP (1<<22)
+#define SYS_CTRL_CLR_RST_AP_CLKEN  (1<<23)
+#define SYS_CTRL_CLR_RST_AP_RST    (1<<24)
+#define SYS_CTRL_CLR_RST_MEM_CHK   (1<<25)
+#define SYS_CTRL_CLR_RST_MPMC      (1<<26)
+#define SYS_CTRL_CLR_RST_SYS_A2A_WD (1<<27)
+#define SYS_CTRL_CLR_RST_COMREGS_WD (1<<28)
+#define SYS_CTRL_CLR_RST_OUT       (1<<30)
+#define SYS_CTRL_CLR_SYS_RST(n)    (((n)&0x1FFFFFFF)<<0)
+#define SYS_CTRL_CLR_SYS_RST_MASK  (0x1FFFFFFF<<0)
+#define SYS_CTRL_CLR_SYS_RST_SHIFT (0)
+
+//BB_Rst_Set
+#define SYS_CTRL_SET_RST_BCPU      (1<<0)
+#define SYS_CTRL_SET_RST_BB_IRQ    (1<<1)
+#define SYS_CTRL_SET_RST_BB_A2A    (1<<2)
+#define SYS_CTRL_SET_RST_BB_IFC    (1<<3)
+#define SYS_CTRL_SET_RST_BB_SRAM   (1<<4)
+#define SYS_CTRL_SET_RST_ITLV      (1<<5)
+#define SYS_CTRL_SET_RST_VITERBI   (1<<6)
+#define SYS_CTRL_SET_RST_CIPHER    (1<<7)
+#define SYS_CTRL_SET_RST_XCOR      (1<<8)
+#define SYS_CTRL_SET_RST_COPRO     (1<<9)
+#define SYS_CTRL_SET_RST_RF_IF     (1<<10)
+#define SYS_CTRL_SET_RST_EXCOR     (1<<11)
+#define SYS_CTRL_SET_RST_EVITAC    (1<<12)
+#define SYS_CTRL_SET_RST_CORDIC    (1<<13)
+#define SYS_CTRL_SET_RST_TCU_BB    (1<<14)
+#define SYS_CTRL_SET_RST_BB_DP     (1<<15)
+#define SYS_CTRL_SET_RST_BB_ROM    (1<<16)
+#define SYS_CTRL_SET_RST_MPMC_BB   (1<<17)
+#define SYS_CTRL_SET_RST_BB_FULL   (1<<31)
+#define SYS_CTRL_SET_BB_RST(n)     (((n)&0x3FFFF)<<0)
+#define SYS_CTRL_SET_BB_RST_MASK   (0x3FFFF<<0)
+#define SYS_CTRL_SET_BB_RST_SHIFT  (0)
+
+//BB_Rst_Clr
+#define SYS_CTRL_CLR_RST_BCPU      (1<<0)
+#define SYS_CTRL_CLR_RST_BB_IRQ    (1<<1)
+#define SYS_CTRL_CLR_RST_BB_A2A    (1<<2)
+#define SYS_CTRL_CLR_RST_BB_IFC    (1<<3)
+#define SYS_CTRL_CLR_RST_BB_SRAM   (1<<4)
+#define SYS_CTRL_CLR_RST_ITLV      (1<<5)
+#define SYS_CTRL_CLR_RST_VITERBI   (1<<6)
+#define SYS_CTRL_CLR_RST_CIPHER    (1<<7)
+#define SYS_CTRL_CLR_RST_XCOR      (1<<8)
+#define SYS_CTRL_CLR_RST_COPRO     (1<<9)
+#define SYS_CTRL_CLR_RST_RF_IF     (1<<10)
+#define SYS_CTRL_CLR_RST_EXCOR     (1<<11)
+#define SYS_CTRL_CLR_RST_EVITAC    (1<<12)
+#define SYS_CTRL_CLR_RST_CORDIC    (1<<13)
+#define SYS_CTRL_CLR_RST_TCU_BB    (1<<14)
+#define SYS_CTRL_CLR_RST_BB_DP     (1<<15)
+#define SYS_CTRL_CLR_RST_BB_ROM    (1<<16)
+#define SYS_CTRL_CLR_RST_MPMC_BB   (1<<17)
+#define SYS_CTRL_CLR_RST_BB_FULL   (1<<31)
+#define SYS_CTRL_CLR_BB_RST(n)     (((n)&0x3FFFF)<<0)
+#define SYS_CTRL_CLR_BB_RST_MASK   (0x3FFFF<<0)
+#define SYS_CTRL_CLR_BB_RST_SHIFT  (0)
+
+//Clk_Sys_Mode
+#define SYS_CTRL_MODE_SYS_XCPU     (1<<0)
+#define SYS_CTRL_MODE_SYS_XCPU_INT_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_SYS_XCPU_INT_MANUAL (1<<1)
+#define SYS_CTRL_MODE_SYS_PCLK_CONF_AUTOMATIC (0<<2)
+#define SYS_CTRL_MODE_SYS_PCLK_CONF_MANUAL (1<<2)
+#define SYS_CTRL_MODE_SYS_PCLK_DATA_AUTOMATIC (0<<3)
+#define SYS_CTRL_MODE_SYS_PCLK_DATA_MANUAL (1<<3)
+#define SYS_CTRL_MODE_SYS_AMBA_AUTOMATIC (0<<4)
+#define SYS_CTRL_MODE_SYS_AMBA_MANUAL (1<<4)
+#define SYS_CTRL_MODE_SYS_DMA_AUTOMATIC (0<<5)
+#define SYS_CTRL_MODE_SYS_DMA_MANUAL (1<<5)
+#define SYS_CTRL_MODE_SYS_EBC_AUTOMATIC (0<<6)
+#define SYS_CTRL_MODE_SYS_EBC_MANUAL (1<<6)
+#define SYS_CTRL_MODE_SYS_IFC_CH0_AUTOMATIC (0<<7)
+#define SYS_CTRL_MODE_SYS_IFC_CH0_MANUAL (1<<7)
+#define SYS_CTRL_MODE_SYS_IFC_CH1_AUTOMATIC (0<<8)
+#define SYS_CTRL_MODE_SYS_IFC_CH1_MANUAL (1<<8)
+#define SYS_CTRL_MODE_SYS_IFC_CH2_AUTOMATIC (0<<9)
+#define SYS_CTRL_MODE_SYS_IFC_CH2_MANUAL (1<<9)
+#define SYS_CTRL_MODE_SYS_IFC_CH3_AUTOMATIC (0<<10)
+#define SYS_CTRL_MODE_SYS_IFC_CH3_MANUAL (1<<10)
+#define SYS_CTRL_MODE_SYS_IFC_DBG_AUTOMATIC (0<<11)
+#define SYS_CTRL_MODE_SYS_IFC_DBG_MANUAL (1<<11)
+#define SYS_CTRL_MODE_SYS_A2A_AUTOMATIC (0<<12)
+#define SYS_CTRL_MODE_SYS_A2A_MANUAL (1<<12)
+#define SYS_CTRL_MODE_SYS_AXI2AHB_AUTOMATIC (0<<13)
+#define SYS_CTRL_MODE_SYS_AXI2AHB_MANUAL (1<<13)
+#define SYS_CTRL_MODE_SYS_AHB2AXI_AUTOMATIC (0<<14)
+#define SYS_CTRL_MODE_SYS_AHB2AXI_MANUAL (1<<14)
+#define SYS_CTRL_MODE_SYS_EXT_AHB_AUTOMATIC (0<<15)
+#define SYS_CTRL_MODE_SYS_EXT_AHB_MANUAL (1<<15)
+#define SYS_CTRL_MODE_SYS_DEBUG_UART_AUTOMATIC (0<<16)
+#define SYS_CTRL_MODE_SYS_DEBUG_UART_MANUAL (1<<16)
+#define SYS_CTRL_MODE_SYS_DBGHST_AUTOMATIC (0<<17)
+#define SYS_CTRL_MODE_SYS_DBGHST_MANUAL (1<<17)
+#define SYS_CTRL_MODE_SYS_A2A_WD_AUTOMATIC (0<<18)
+#define SYS_CTRL_MODE_SYS_A2A_WD_MANUAL (1<<18)
+#define SYS_CTRL_MODE_SYSD_SCI1_AUTOMATIC (0<<19)
+#define SYS_CTRL_MODE_SYSD_SCI1_MANUAL (1<<19)
+#define SYS_CTRL_MODE_SYSD_SCI2_AUTOMATIC (0<<20)
+#define SYS_CTRL_MODE_SYSD_SCI2_MANUAL (1<<20)
+#define SYS_CTRL_MODE_SYSD_SCI3_AUTOMATIC (0<<21)
+#define SYS_CTRL_MODE_SYSD_SCI3_MANUAL (1<<21)
+#define SYS_CTRL_MODE_SYSD_RF_SPI_AUTOMATIC (0<<22)
+#define SYS_CTRL_MODE_SYSD_RF_SPI_MANUAL (1<<22)
+#define SYS_CTRL_MODE_SYSD_OSC_AUTOMATIC (0<<23)
+#define SYS_CTRL_MODE_SYSD_OSC_MANUAL (1<<23)
+#define SYS_CTRL_MODE_CLK_SYS(n)   (((n)&0x7FFFFF)<<1)
+#define SYS_CTRL_MODE_CLK_SYS_MASK (0x7FFFFF<<1)
+#define SYS_CTRL_MODE_CLK_SYS_SHIFT (1)
+
+//Clk_Sys_Enable
+#define SYS_CTRL_ENABLE_SYS_XCPU   (1<<0)
+#define SYS_CTRL_ENABLE_SYS_XCPU_INT (1<<1)
+#define SYS_CTRL_ENABLE_SYS_PCLK_CONF (1<<2)
+#define SYS_CTRL_ENABLE_SYS_PCLK_DATA (1<<3)
+#define SYS_CTRL_ENABLE_SYS_AMBA   (1<<4)
+#define SYS_CTRL_ENABLE_SYS_DMA    (1<<5)
+#define SYS_CTRL_ENABLE_SYS_EBC    (1<<6)
+#define SYS_CTRL_ENABLE_SYS_IFC_CH0 (1<<7)
+#define SYS_CTRL_ENABLE_SYS_IFC_CH1 (1<<8)
+#define SYS_CTRL_ENABLE_SYS_IFC_CH2 (1<<9)
+#define SYS_CTRL_ENABLE_SYS_IFC_CH3 (1<<10)
+#define SYS_CTRL_ENABLE_SYS_IFC_DBG (1<<11)
+#define SYS_CTRL_ENABLE_SYS_A2A    (1<<12)
+#define SYS_CTRL_ENABLE_SYS_AXI2AHB (1<<13)
+#define SYS_CTRL_ENABLE_SYS_AHB2AXI (1<<14)
+#define SYS_CTRL_ENABLE_SYS_EXT_AHB (1<<15)
+#define SYS_CTRL_ENABLE_SYS_DEBUG_UART (1<<16)
+#define SYS_CTRL_ENABLE_SYS_DBGHST (1<<17)
+#define SYS_CTRL_ENABLE_SYS_A2A_WD (1<<18)
+#define SYS_CTRL_ENABLE_SYSD_SCI1  (1<<19)
+#define SYS_CTRL_ENABLE_SYSD_SCI2  (1<<20)
+#define SYS_CTRL_ENABLE_SYSD_SCI3  (1<<21)
+#define SYS_CTRL_ENABLE_SYSD_RF_SPI (1<<22)
+#define SYS_CTRL_ENABLE_SYSD_OSC   (1<<23)
+#define SYS_CTRL_ENABLE_SYS_GPIO   (1<<24)
+#define SYS_CTRL_ENABLE_SYS_IRQ    (1<<25)
+#define SYS_CTRL_ENABLE_SYS_TCU    (1<<26)
+#define SYS_CTRL_ENABLE_SYS_TIMER  (1<<27)
+#define SYS_CTRL_ENABLE_SYS_COM_REGS (1<<28)
+#define SYS_CTRL_ENABLE_CLK_SYS(n) (((n)&0x1FFFFFFF)<<0)
+#define SYS_CTRL_ENABLE_CLK_SYS_MASK (0x1FFFFFFF<<0)
+#define SYS_CTRL_ENABLE_CLK_SYS_SHIFT (0)
+
+//Clk_Sys_Disable
+#define SYS_CTRL_DISABLE_SYS_XCPU  (1<<0)
+#define SYS_CTRL_DISABLE_SYS_XCPU_INT (1<<1)
+#define SYS_CTRL_DISABLE_SYS_PCLK_CONF (1<<2)
+#define SYS_CTRL_DISABLE_SYS_PCLK_DATA (1<<3)
+#define SYS_CTRL_DISABLE_SYS_AMBA  (1<<4)
+#define SYS_CTRL_DISABLE_SYS_DMA   (1<<5)
+#define SYS_CTRL_DISABLE_SYS_EBC   (1<<6)
+#define SYS_CTRL_DISABLE_SYS_IFC_CH0 (1<<7)
+#define SYS_CTRL_DISABLE_SYS_IFC_CH1 (1<<8)
+#define SYS_CTRL_DISABLE_SYS_IFC_CH2 (1<<9)
+#define SYS_CTRL_DISABLE_SYS_IFC_CH3 (1<<10)
+#define SYS_CTRL_DISABLE_SYS_IFC_DBG (1<<11)
+#define SYS_CTRL_DISABLE_SYS_A2A   (1<<12)
+#define SYS_CTRL_DISABLE_SYS_AXI2AHB (1<<13)
+#define SYS_CTRL_DISABLE_SYS_AHB2AXI (1<<14)
+#define SYS_CTRL_DISABLE_SYS_EXT_AHB (1<<15)
+#define SYS_CTRL_DISABLE_SYS_DEBUG_UART (1<<16)
+#define SYS_CTRL_DISABLE_SYS_DBGHST (1<<17)
+#define SYS_CTRL_DISABLE_SYS_A2A_WD (1<<18)
+#define SYS_CTRL_DISABLE_SYSD_SCI1 (1<<19)
+#define SYS_CTRL_DISABLE_SYSD_SCI2 (1<<20)
+#define SYS_CTRL_DISABLE_SYSD_SCI3 (1<<21)
+#define SYS_CTRL_DISABLE_SYSD_RF_SPI (1<<22)
+#define SYS_CTRL_DISABLE_SYSD_OSC  (1<<23)
+#define SYS_CTRL_DISABLE_SYS_GPIO  (1<<24)
+#define SYS_CTRL_DISABLE_SYS_IRQ   (1<<25)
+#define SYS_CTRL_DISABLE_SYS_TCU   (1<<26)
+#define SYS_CTRL_DISABLE_SYS_TIMER (1<<27)
+#define SYS_CTRL_DISABLE_SYS_COM_REGS (1<<28)
+#define SYS_CTRL_DISABLE_CLK_SYS(n) (((n)&0x1FFFFFFF)<<0)
+#define SYS_CTRL_DISABLE_CLK_SYS_MASK (0x1FFFFFFF<<0)
+#define SYS_CTRL_DISABLE_CLK_SYS_SHIFT (0)
+
+//Clk_Per_Mode
+#define SYS_CTRL_MODE_PERD_SPI1_AUTOMATIC (0<<0)
+#define SYS_CTRL_MODE_PERD_SPI1_MANUAL (1<<0)
+#define SYS_CTRL_MODE_PERD_SPI2_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_PERD_SPI2_MANUAL (1<<1)
+#define SYS_CTRL_MODE_CLK_PER(n)   (((n)&3)<<0)
+#define SYS_CTRL_MODE_CLK_PER_MASK (3<<0)
+#define SYS_CTRL_MODE_CLK_PER_SHIFT (0)
+
+//Clk_Per_Enable
+#define SYS_CTRL_ENABLE_PERD_SPI1  (1<<0)
+#define SYS_CTRL_ENABLE_PERD_SPI2  (1<<1)
+#define SYS_CTRL_ENABLE_PER_SPY    (1<<2)
+#define SYS_CTRL_ENABLE_PER_TEST   (1<<3)
+#define SYS_CTRL_ENABLE_CLK_PER(n) (((n)&15)<<0)
+#define SYS_CTRL_ENABLE_CLK_PER_MASK (15<<0)
+#define SYS_CTRL_ENABLE_CLK_PER_SHIFT (0)
+
+//Clk_Per_Disable
+#define SYS_CTRL_DISABLE_PERD_SPI1 (1<<0)
+#define SYS_CTRL_DISABLE_PERD_SPI2 (1<<1)
+#define SYS_CTRL_DISABLE_PER_SPY   (1<<2)
+#define SYS_CTRL_DISABLE_PER_TEST  (1<<3)
+#define SYS_CTRL_DISABLE_CLK_PER(n) (((n)&15)<<0)
+#define SYS_CTRL_DISABLE_CLK_PER_MASK (15<<0)
+#define SYS_CTRL_DISABLE_CLK_PER_SHIFT (0)
+
+//Clk_BB_Mode
+#define SYS_CTRL_MODE_BB_BCPU      (1<<0)
+#define SYS_CTRL_MODE_BB_BCPU_INT_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_BB_BCPU_INT_MANUAL (1<<1)
+#define SYS_CTRL_MODE_BB_AMBA_AUTOMATIC (0<<2)
+#define SYS_CTRL_MODE_BB_AMBA_MANUAL (1<<2)
+#define SYS_CTRL_MODE_BB_PCLK_CONF_AUTOMATIC (0<<3)
+#define SYS_CTRL_MODE_BB_PCLK_CONF_MANUAL (1<<3)
+#define SYS_CTRL_MODE_BB_PCLK_DATA_AUTOMATIC (0<<4)
+#define SYS_CTRL_MODE_BB_PCLK_DATA_MANUAL (1<<4)
+#define SYS_CTRL_MODE_BB_EXCOR_AUTOMATIC (0<<5)
+#define SYS_CTRL_MODE_BB_EXCOR_MANUAL (1<<5)
+#define SYS_CTRL_MODE_BB_IFC_CH2_AUTOMATIC (0<<6)
+#define SYS_CTRL_MODE_BB_IFC_CH2_MANUAL (1<<6)
+#define SYS_CTRL_MODE_BB_IFC_CH3_AUTOMATIC (0<<7)
+#define SYS_CTRL_MODE_BB_IFC_CH3_MANUAL (1<<7)
+#define SYS_CTRL_MODE_BB_SRAM_AUTOMATIC (0<<8)
+#define SYS_CTRL_MODE_BB_SRAM_MANUAL (1<<8)
+#define SYS_CTRL_MODE_BB_A2A_AUTOMATIC (0<<9)
+#define SYS_CTRL_MODE_BB_A2A_MANUAL (1<<9)
+#define SYS_CTRL_MODE_BB_ITLV_AUTOMATIC (0<<10)
+#define SYS_CTRL_MODE_BB_ITLV_MANUAL (1<<10)
+#define SYS_CTRL_MODE_BB_VITERBI_AUTOMATIC (0<<11)
+#define SYS_CTRL_MODE_BB_VITERBI_MANUAL (1<<11)
+#define SYS_CTRL_MODE_BB_CIPHER_AUTOMATIC (0<<12)
+#define SYS_CTRL_MODE_BB_CIPHER_MANUAL (1<<12)
+#define SYS_CTRL_MODE_BB_RF_IF_AUTOMATIC (0<<13)
+#define SYS_CTRL_MODE_BB_RF_IF_MANUAL (1<<13)
+#define SYS_CTRL_MODE_BB_COPRO_AUTOMATIC (0<<14)
+#define SYS_CTRL_MODE_BB_COPRO_MANUAL (1<<14)
+#define SYS_CTRL_MODE_BB_CP2_REG_AUTOMATIC (0<<15)
+#define SYS_CTRL_MODE_BB_CP2_REG_MANUAL (1<<15)
+#define SYS_CTRL_MODE_BB_XCOR_AUTOMATIC (0<<16)
+#define SYS_CTRL_MODE_BB_XCOR_MANUAL (1<<16)
+#define SYS_CTRL_MODE_BB_EVITAC_AUTOMATIC (0<<17)
+#define SYS_CTRL_MODE_BB_EVITAC_MANUAL (1<<17)
+#define SYS_CTRL_MODE_BB_ROM_AUTOMATIC (0<<18)
+#define SYS_CTRL_MODE_BB_ROM_MANUAL (1<<18)
+#define SYS_CTRL_MODE_BB_MPMC_AUTOMATIC (0<<19)
+#define SYS_CTRL_MODE_BB_MPMC_MANUAL (1<<19)
+#define SYS_CTRL_MODE_CLK_BB(n)    (((n)&0x7FFFF)<<1)
+#define SYS_CTRL_MODE_CLK_BB_MASK  (0x7FFFF<<1)
+#define SYS_CTRL_MODE_CLK_BB_SHIFT (1)
+
+//Clk_BB_Enable
+#define SYS_CTRL_ENABLE_BB_BCPU    (1<<0)
+#define SYS_CTRL_ENABLE_BB_BCPU_INT (1<<1)
+#define SYS_CTRL_ENABLE_BB_AMBA    (1<<2)
+#define SYS_CTRL_ENABLE_BB_PCLK_CONF (1<<3)
+#define SYS_CTRL_ENABLE_BB_PCLK_DATA (1<<4)
+#define SYS_CTRL_ENABLE_BB_EXCOR   (1<<5)
+#define SYS_CTRL_ENABLE_BB_IFC_CH2 (1<<6)
+#define SYS_CTRL_ENABLE_BB_IFC_CH3 (1<<7)
+#define SYS_CTRL_ENABLE_BB_SRAM    (1<<8)
+#define SYS_CTRL_ENABLE_BB_A2A     (1<<9)
+#define SYS_CTRL_ENABLE_BB_ITLV    (1<<10)
+#define SYS_CTRL_ENABLE_BB_VITERBI (1<<11)
+#define SYS_CTRL_ENABLE_BB_CIPHER  (1<<12)
+#define SYS_CTRL_ENABLE_BB_RF_IF   (1<<13)
+#define SYS_CTRL_ENABLE_BB_COPRO   (1<<14)
+#define SYS_CTRL_ENABLE_BB_CP2_REG (1<<15)
+#define SYS_CTRL_ENABLE_BB_XCOR    (1<<16)
+#define SYS_CTRL_ENABLE_BB_EVITAC  (1<<17)
+#define SYS_CTRL_ENABLE_BB_ROM     (1<<18)
+#define SYS_CTRL_ENABLE_BB_MPMC    (1<<19)
+#define SYS_CTRL_ENABLE_BB_IRQ     (1<<20)
+#define SYS_CTRL_ENABLE_BB_COM_REGS (1<<21)
+#define SYS_CTRL_ENABLE_BB_CORDIC  (1<<22)
+#define SYS_CTRL_ENABLE_BB_DP      (1<<23)
+#define SYS_CTRL_ENABLE_CLK_BB(n)  (((n)&0xFFFFFF)<<0)
+#define SYS_CTRL_ENABLE_CLK_BB_MASK (0xFFFFFF<<0)
+#define SYS_CTRL_ENABLE_CLK_BB_SHIFT (0)
+
+//Clk_BB_Disable
+#define SYS_CTRL_DISABLE_BB_BCPU   (1<<0)
+#define SYS_CTRL_DISABLE_BB_BCPU_INT (1<<1)
+#define SYS_CTRL_DISABLE_BB_AMBA   (1<<2)
+#define SYS_CTRL_DISABLE_BB_PCLK_CONF (1<<3)
+#define SYS_CTRL_DISABLE_BB_PCLK_DATA (1<<4)
+#define SYS_CTRL_DISABLE_BB_EXCOR  (1<<5)
+#define SYS_CTRL_DISABLE_BB_IFC_CH2 (1<<6)
+#define SYS_CTRL_DISABLE_BB_IFC_CH3 (1<<7)
+#define SYS_CTRL_DISABLE_BB_SRAM   (1<<8)
+#define SYS_CTRL_DISABLE_BB_A2A    (1<<9)
+#define SYS_CTRL_DISABLE_BB_ITLV   (1<<10)
+#define SYS_CTRL_DISABLE_BB_VITERBI (1<<11)
+#define SYS_CTRL_DISABLE_BB_CIPHER (1<<12)
+#define SYS_CTRL_DISABLE_BB_RF_IF  (1<<13)
+#define SYS_CTRL_DISABLE_BB_COPRO  (1<<14)
+#define SYS_CTRL_DISABLE_BB_CP2_REG (1<<15)
+#define SYS_CTRL_DISABLE_BB_XCOR   (1<<16)
+#define SYS_CTRL_DISABLE_BB_EVITAC (1<<17)
+#define SYS_CTRL_DISABLE_BB_ROM    (1<<18)
+#define SYS_CTRL_DISABLE_BB_MPMC   (1<<19)
+#define SYS_CTRL_DISABLE_BB_IRQ    (1<<20)
+#define SYS_CTRL_DISABLE_BB_COM_REGS (1<<21)
+#define SYS_CTRL_DISABLE_BB_CORDIC (1<<22)
+#define SYS_CTRL_DISABLE_BB_DP     (1<<23)
+#define SYS_CTRL_DISABLE_CLK_BB(n) (((n)&0xFFFFFF)<<0)
+#define SYS_CTRL_DISABLE_CLK_BB_MASK (0xFFFFFF<<0)
+#define SYS_CTRL_DISABLE_CLK_BB_SHIFT (0)
+
+//Clk_Other_Mode
+#define SYS_CTRL_MODE_OC_DEBUG_UART_AUTOMATIC (0<<0)
+#define SYS_CTRL_MODE_OC_DEBUG_UART_MANUAL (1<<0)
+#define SYS_CTRL_MODE_OC_RF_RX_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_OC_RF_RX_MANUAL (1<<1)
+#define SYS_CTRL_MODE_OC_RF_TX_AUTOMATIC (0<<2)
+#define SYS_CTRL_MODE_OC_RF_TX_MANUAL (1<<2)
+#define SYS_CTRL_MODE_OC_MEM_BRIDGE_AUTOMATIC (0<<3)
+#define SYS_CTRL_MODE_OC_MEM_BRIDGE_MANUAL (1<<3)
+#define SYS_CTRL_MODE_CLK_OTHER(n) (((n)&15)<<0)
+#define SYS_CTRL_MODE_CLK_OTHER_MASK (15<<0)
+#define SYS_CTRL_MODE_CLK_OTHER_SHIFT (0)
+
+//Clk_Other_Enable
+#define SYS_CTRL_ENABLE_OC_DEBUG_UART (1<<0)
+#define SYS_CTRL_ENABLE_OC_RF_RX   (1<<1)
+#define SYS_CTRL_ENABLE_OC_RF_TX   (1<<2)
+#define SYS_CTRL_ENABLE_OC_MEM_BRIDGE (1<<3)
+#define SYS_CTRL_ENABLE_OC_LPS     (1<<4)
+#define SYS_CTRL_ENABLE_OC_GPIO    (1<<5)
+#define SYS_CTRL_ENABLE_OC_CLK_OUT (1<<6)
+#define SYS_CTRL_ENABLE_OC_MEM_CLK_OUT (1<<7)
+#define SYS_CTRL_ENABLE_OC_TCU     (1<<8)
+#define SYS_CTRL_ENABLE_OC_WD_CHIP (1<<9)
+#define SYS_CTRL_ENABLE_OC_WD_ADC  (1<<10)
+#define SYS_CTRL_ENABLE_OC_WD_TURBO (1<<11)
+#define SYS_CTRL_ENABLE_OC_WD_OSC  (1<<12)
+#define SYS_CTRL_ENABLE_OC_MPMC    (1<<13)
+#define SYS_CTRL_ENABLE_CLK_OTHER(n) (((n)&0x3FFF)<<0)
+#define SYS_CTRL_ENABLE_CLK_OTHER_MASK (0x3FFF<<0)
+#define SYS_CTRL_ENABLE_CLK_OTHER_SHIFT (0)
+
+//Clk_Other_Disable
+#define SYS_CTRL_DISABLE_OC_DEBUG_UART (1<<0)
+#define SYS_CTRL_DISABLE_OC_RF_RX  (1<<1)
+#define SYS_CTRL_DISABLE_OC_RF_TX  (1<<2)
+#define SYS_CTRL_DISABLE_OC_MEM_BRIDGE (1<<3)
+#define SYS_CTRL_DISABLE_OC_LPS    (1<<4)
+#define SYS_CTRL_DISABLE_OC_GPIO   (1<<5)
+#define SYS_CTRL_DISABLE_OC_CLK_OUT (1<<6)
+#define SYS_CTRL_DISABLE_OC_MEM_CLK_OUT (1<<7)
+#define SYS_CTRL_DISABLE_OC_TCU    (1<<8)
+#define SYS_CTRL_DISABLE_OC_WD_CHIP (1<<9)
+#define SYS_CTRL_DISABLE_OC_WD_ADC (1<<10)
+#define SYS_CTRL_DISABLE_OC_WD_TURBO (1<<11)
+#define SYS_CTRL_DISABLE_OC_WD_OSC (1<<12)
+#define SYS_CTRL_DISABLE_OC_MPMC   (1<<13)
+#define SYS_CTRL_DISABLE_CLK_OTHER(n) (((n)&0x3FFF)<<0)
+#define SYS_CTRL_DISABLE_CLK_OTHER_MASK (0x3FFF<<0)
+#define SYS_CTRL_DISABLE_CLK_OTHER_SHIFT (0)
+
+//Pll_Ctrl
+#define SYS_CTRL_PLL_ENABLE        (1<<0)
+#define SYS_CTRL_PLL_ENABLE_MASK   (1<<0)
+#define SYS_CTRL_PLL_ENABLE_SHIFT  (0)
+#define SYS_CTRL_PLL_ENABLE_POWER_DOWN (0<<0)
+#define SYS_CTRL_PLL_ENABLE_ENABLE (1<<0)
+#define SYS_CTRL_PLL_LOCK_RESET    (1<<4)
+#define SYS_CTRL_PLL_LOCK_RESET_MASK (1<<4)
+#define SYS_CTRL_PLL_LOCK_RESET_SHIFT (4)
+#define SYS_CTRL_PLL_LOCK_RESET_RESET (0<<4)
+#define SYS_CTRL_PLL_LOCK_RESET_NO_RESET (1<<4)
+#define SYS_CTRL_PLL_BYPASS        (1<<8)
+#define SYS_CTRL_PLL_BYPASS_MASK   (1<<8)
+#define SYS_CTRL_PLL_BYPASS_SHIFT  (8)
+#define SYS_CTRL_PLL_BYPASS_PASS   (0<<8)
+#define SYS_CTRL_PLL_BYPASS_BYPASS (1<<8)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE (1<<12)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_MASK (1<<12)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_SHIFT (12)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_ENABLE (1<<12)
+#define SYS_CTRL_PLL_CLK_FAST_ENABLE_DISABLE (0<<12)
+#define SYS_CTRL_PLL_XP_CFG(n)     (((n)&4369)<<0)
+#define SYS_CTRL_PLL_XP_CFG_MASK   (4369<<0)
+#define SYS_CTRL_PLL_XP_CFG_SHIFT  (0)
+
+//Sel_Clock
+#define SYS_CTRL_SLOW_SEL_RF_OSCILLATOR (1<<0)
+#define SYS_CTRL_SLOW_SEL_RF_RF    (0<<0)
+#define SYS_CTRL_SYS_SEL_FAST_SLOW (1<<4)
+#define SYS_CTRL_SYS_SEL_FAST_FAST (0<<4)
+#define SYS_CTRL_TCU_13M_L_26M     (1<<5)
+#define SYS_CTRL_TCU_13M_L_13M     (0<<5)
+#define SYS_CTRL_PLL_DISABLE_LPS_DISABLE (1<<6)
+#define SYS_CTRL_PLL_DISABLE_LPS_ENABLE (0<<6)
+#define SYS_CTRL_DIGEN_H_ENABLE    (1<<7)
+#define SYS_CTRL_DIGEN_H_DISABLE   (0<<7)
+#define SYS_CTRL_RF_DETECTED_OK    (1<<20)
+#define SYS_CTRL_RF_DETECTED_NO    (0<<20)
+#define SYS_CTRL_RF_DETECT_BYPASS  (1<<21)
+#define SYS_CTRL_RF_DETECT_RESET   (1<<22)
+#define SYS_CTRL_RF_SELECTED_L     (1<<23)
+#define SYS_CTRL_PLL_LOCKED        (1<<24)
+#define SYS_CTRL_PLL_LOCKED_MASK   (1<<24)
+#define SYS_CTRL_PLL_LOCKED_SHIFT  (24)
+#define SYS_CTRL_PLL_LOCKED_LOCKED (1<<24)
+#define SYS_CTRL_PLL_LOCKED_NOT_LOCKED (0<<24)
+#define SYS_CTRL_PLL_BYPASS_LOCK   (1<<27)
+#define SYS_CTRL_FAST_SELECTED_L   (1<<31)
+#define SYS_CTRL_FAST_SELECTED_L_MASK (1<<31)
+#define SYS_CTRL_FAST_SELECTED_L_SHIFT (31)
+
+//Cfg_Clk_Sys
+#define SYS_CTRL_FREQ(n)           (((n)&15)<<0)
+#define SYS_CTRL_FREQ_MASK         (15<<0)
+#define SYS_CTRL_FREQ_SHIFT        (0)
+#define SYS_CTRL_FREQ_312M         (13<<0)
+#define SYS_CTRL_FREQ_250M         (12<<0)
+#define SYS_CTRL_FREQ_208M         (11<<0)
+#define SYS_CTRL_FREQ_178M         (10<<0)
+#define SYS_CTRL_FREQ_156M         (9<<0)
+#define SYS_CTRL_FREQ_139M         (8<<0)
+#define SYS_CTRL_FREQ_125M         (7<<0)
+#define SYS_CTRL_FREQ_113M         (6<<0)
+#define SYS_CTRL_FREQ_104M         (5<<0)
+#define SYS_CTRL_FREQ_89M          (4<<0)
+#define SYS_CTRL_FREQ_78M          (3<<0)
+#define SYS_CTRL_FREQ_52M          (2<<0)
+#define SYS_CTRL_FREQ_39M          (1<<0)
+#define SYS_CTRL_FREQ_26M          (0<<0)
+#define SYS_CTRL_FORCE_DIV_UPDATE  (1<<4)
+#define SYS_CTRL_REQ_DIV_UPDATE    (1<<8)
+
+//Cfg_Clk_Mem_Bridge
+#define SYS_CTRL_MEM_FREQ(n)       (((n)&15)<<0)
+#define SYS_CTRL_MEM_FREQ_MASK     (15<<0)
+#define SYS_CTRL_MEM_FREQ_SHIFT    (0)
+#define SYS_CTRL_MEM_FREQ_312M     (13<<0)
+#define SYS_CTRL_MEM_FREQ_250M     (12<<0)
+#define SYS_CTRL_MEM_FREQ_208M     (11<<0)
+#define SYS_CTRL_MEM_FREQ_178M     (10<<0)
+#define SYS_CTRL_MEM_FREQ_156M     (9<<0)
+#define SYS_CTRL_MEM_FREQ_139M     (8<<0)
+#define SYS_CTRL_MEM_FREQ_125M     (7<<0)
+#define SYS_CTRL_MEM_FREQ_113M     (6<<0)
+#define SYS_CTRL_MEM_FREQ_104M     (5<<0)
+#define SYS_CTRL_MEM_FREQ_89M      (4<<0)
+#define SYS_CTRL_MEM_FREQ_78M      (3<<0)
+#define SYS_CTRL_MEM_FREQ_52M      (2<<0)
+#define SYS_CTRL_MEM_FREQ_39M      (1<<0)
+#define SYS_CTRL_MEM_FREQ_26M      (0<<0)
+#define SYS_CTRL_DDR_MODE_EN_NORMAL_MODE (0<<4)
+#define SYS_CTRL_DDR_MODE_EN_DDR_MODE (1<<4)
+#define SYS_CTRL_DDR_FAST_CLK_POL_INVERT (1<<5)
+#define SYS_CTRL_DDR_FAST_CLK_POL_NORMAL (0<<5)
+#define SYS_CTRL_DDR_DQSL_O(n)     (((n)&31)<<6)
+#define SYS_CTRL_DDR_DQSU_O(n)     (((n)&31)<<11)
+#define SYS_CTRL_DDR_DQS_OEN(n)    (((n)&31)<<16)
+#define SYS_CTRL_DDR_DQSL_I(n)     (((n)&31)<<21)
+#define SYS_CTRL_DDR_DQSU_I(n)     (((n)&31)<<26)
+#define SYS_CTRL_MEM_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_Out
+#define SYS_CTRL_CLKOUT_DIVIDER(n) (((n)&31)<<0)
+#define SYS_CTRL_CLKOUT_SEL_OSC    (0<<8)
+#define SYS_CTRL_CLKOUT_SEL_RF     (1<<8)
+#define SYS_CTRL_CLKOUT_SEL_DIVIDER (2<<8)
+
+//Cfg_Clk_Host_Uart
+#define SYS_CTRL_HOST_UART_DIVIDER(n) (((n)&0x3FF)<<0)
+#define SYS_CTRL_HOST_UART_DIVIDER_MASK (0x3FF<<0)
+#define SYS_CTRL_HOST_UART_DIVIDER_SHIFT (0)
+#define SYS_CTRL_HOST_UART_SEL_PLL_SLOW (0<<12)
+#define SYS_CTRL_HOST_UART_SEL_PLL_PLL (1<<12)
+
+//Cfg_Clk_Auxclk
+#define SYS_CTRL_AUXCLK_EN_DISABLE (0<<0)
+#define SYS_CTRL_AUXCLK_EN_ENABLE  (1<<0)
+
+//Cfg_AHB
+#define SYS_CTRL_SYS_NEW_ARBITRATION_ENABLE (1<<0)
+#define SYS_CTRL_SYS_NEW_ARBITRATION_DISABLE (0<<0)
+#define SYS_CTRL_ENABLE_SYS_MID_DMA_ENABLE (1<<1)
+#define SYS_CTRL_ENABLE_SYS_MID_DMA_DISABLE (0<<1)
+#define SYS_CTRL_ENABLE_SYS_MID_XCPU_ENABLE (1<<2)
+#define SYS_CTRL_ENABLE_SYS_MID_XCPU_DISABLE (0<<2)
+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_ENABLE (1<<3)
+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_DISABLE (0<<3)
+#define SYS_CTRL_ENABLE_SYS_MID_IFC_ENABLE (1<<4)
+#define SYS_CTRL_ENABLE_SYS_MID_IFC_DISABLE (0<<4)
+#define SYS_CTRL_ENABLE_SYS_MID_AXI2AHB_ENABLE (1<<5)
+#define SYS_CTRL_ENABLE_SYS_MID_AXI2AHB_DISABLE (0<<5)
+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_WD_ENABLE (1<<6)
+#define SYS_CTRL_ENABLE_SYS_MID_AHB2AHB_WD_DISABLE (0<<6)
+#define SYS_CTRL_BB_NEW_ARBITRATION_ENABLE (1<<16)
+#define SYS_CTRL_BB_NEW_ARBITRATION_DISABLE (0<<16)
+#define SYS_CTRL_ENABLE_BB_MID_IFC_ENABLE (1<<17)
+#define SYS_CTRL_ENABLE_BB_MID_IFC_DISABLE (0<<17)
+#define SYS_CTRL_ENABLE_BB_MID_BCPU_ENABLE (1<<18)
+#define SYS_CTRL_ENABLE_BB_MID_BCPU_DISABLE (0<<18)
+#define SYS_CTRL_ENABLE_BB_MID_AHB2AHB_ENABLE (1<<19)
+#define SYS_CTRL_ENABLE_BB_MID_AHB2AHB_DISABLE (0<<19)
+#define SYS_CTRL_SYS_ENABLE(n)     (((n)&0x3F)<<1)
+#define SYS_CTRL_SYS_ENABLE_MASK   (0x3F<<1)
+#define SYS_CTRL_SYS_ENABLE_SHIFT  (1)
+#define SYS_CTRL_BB_ENABLE(n)      (((n)&7)<<17)
+#define SYS_CTRL_BB_ENABLE_MASK    (7<<17)
+#define SYS_CTRL_BB_ENABLE_SHIFT   (17)
+
+//Ctrl_AHB
+#define SYS_CTRL_SPLIT_SYS_MID_DMA_NORMAL (1<<0)
+#define SYS_CTRL_SPLIT_SYS_MID_DMA_FORCE (0<<0)
+#define SYS_CTRL_SPLIT_SYS_MID_XCPU_NORMAL (1<<1)
+#define SYS_CTRL_SPLIT_SYS_MID_XCPU_FORCE (0<<1)
+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_NORMAL (1<<2)
+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_FORCE (0<<2)
+#define SYS_CTRL_SPLIT_SYS_MID_IFC_NORMAL (1<<3)
+#define SYS_CTRL_SPLIT_SYS_MID_IFC_FORCE (0<<3)
+#define SYS_CTRL_SPLIT_SYS_MID_AXI2AHB_NORMAL (1<<4)
+#define SYS_CTRL_SPLIT_SYS_MID_AXI2AHB_FORCE (0<<4)
+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_WD_NORMAL (1<<5)
+#define SYS_CTRL_SPLIT_SYS_MID_AHB2AHB_WD_FORCE (0<<5)
+#define SYS_CTRL_SPLIT_BB_MID_IFC_NORMAL (1<<16)
+#define SYS_CTRL_SPLIT_BB_MID_IFC_FORCE (0<<16)
+#define SYS_CTRL_SPLIT_BB_MID_BCPU_NORMAL (1<<17)
+#define SYS_CTRL_SPLIT_BB_MID_BCPU_FORCE (0<<17)
+#define SYS_CTRL_SPLIT_BB_MID_AHB2AHB_NORMAL (1<<18)
+#define SYS_CTRL_SPLIT_BB_MID_AHB2AHB_FORCE (0<<18)
+#define SYS_CTRL_SYS_FORCE_HSPLIT(n) (((n)&0x3F)<<0)
+#define SYS_CTRL_SYS_FORCE_HSPLIT_MASK (0x3F<<0)
+#define SYS_CTRL_SYS_FORCE_HSPLIT_SHIFT (0)
+#define SYS_CTRL_BB_FORCE_HSPLIT(n) (((n)&7)<<16)
+#define SYS_CTRL_BB_FORCE_HSPLIT_MASK (7<<16)
+#define SYS_CTRL_BB_FORCE_HSPLIT_SHIFT (16)
+
+//XCpu_Dbg_BKP
+#define SYS_CTRL_BKPT_EN           (1<<0)
+#define SYS_CTRL_BKPT_MODE(n)      (((n)&3)<<4)
+#define SYS_CTRL_BKPT_MODE_I       (0<<4)
+#define SYS_CTRL_BKPT_MODE_R       (1<<4)
+#define SYS_CTRL_BKPT_MODE_W       (2<<4)
+#define SYS_CTRL_BKPT_MODE_RW      (3<<4)
+#define SYS_CTRL_STALLED           (1<<8)
+
+//XCpu_Dbg_Addr
+#define SYS_CTRL_BREAKPOINT_ADDRESS(n) (((n)&0x3FFFFFF)<<0)
+
+//BCpu_Dbg_BKP
+//#define SYS_CTRL_BKPT_EN         (1<<0)
+//#define SYS_CTRL_BKPT_MODE(n)    (((n)&3)<<4)
+//#define SYS_CTRL_BKPT_MODE_I     (0<<4)
+//#define SYS_CTRL_BKPT_MODE_R     (1<<4)
+//#define SYS_CTRL_BKPT_MODE_W     (2<<4)
+//#define SYS_CTRL_BKPT_MODE_RW    (3<<4)
+//#define SYS_CTRL_STALLED         (1<<8)
+
+//BCpu_Dbg_Addr
+//#define SYS_CTRL_BREAKPOINT_ADDRESS(n) (((n)&0x3FFFFFF)<<0)
+
+//Cfg_Cpus_Cache_Ram_Disable
+#define SYS_CTRL_XCPU_USE_MODE     (1<<0)
+#define SYS_CTRL_XCPU_CLK_OFF_MODE (1<<1)
+#define SYS_CTRL_BCPU_USE_MODE     (1<<16)
+#define SYS_CTRL_BCPU_CLK_OFF_MODE (1<<17)
+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE(n) (((n)&3)<<0)
+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE_MASK (3<<0)
+#define SYS_CTRL_XCPU_CACHE_RAM_DISABLE_SHIFT (0)
+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE(n) (((n)&3)<<16)
+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE_MASK (3<<16)
+#define SYS_CTRL_BCPU_CACHE_RAM_DISABLE_SHIFT (16)
+
+//Reset_Cause
+#define SYS_CTRL_WATCHDOG_RESET_HAPPENED (1<<0)
+#define SYS_CTRL_WATCHDOG_RESET_NO (0<<0)
+#define SYS_CTRL_APSOFT_RESET_HAPPENED (1<<1)
+#define SYS_CTRL_APSOFT_RESET_NO   (0<<1)
+#define SYS_CTRL_GLOBALSOFT_RESET_HAPPENED (1<<4)
+#define SYS_CTRL_GLOBALSOFT_RESET_NO (0<<4)
+#define SYS_CTRL_HOSTDEBUG_RESET_HAPPENED (1<<5)
+#define SYS_CTRL_HOSTDEBUG_RESET_NO (0<<5)
+#define SYS_CTRL_ALARMCAUSE_HAPPENED (1<<6)
+#define SYS_CTRL_ALARMCAUSE_NO     (0<<6)
+#define SYS_CTRL_MEMCHECKDONE_MASK (1<<7)
+#define SYS_CTRL_MEMCHECKDONE_SHIFT (7)
+#define SYS_CTRL_MEMCHECKDONE_DONE (1<<7)
+#define SYS_CTRL_MEMCHECKDONE_RUNNING (0<<7)
+#define SYS_CTRL_BOOT_MODE(n)      (((n)&0xFFFF)<<8)
+#define SYS_CTRL_BOOT_MODE_MASK    (0xFFFF<<8)
+#define SYS_CTRL_BOOT_MODE_SHIFT   (8)
+#define SYS_CTRL_SW_BOOT_MODE(n)   (((n)&0x7F)<<24)
+#define SYS_CTRL_SW_BOOT_MODE_MASK (0x7F<<24)
+#define SYS_CTRL_SW_BOOT_MODE_SHIFT (24)
+#define SYS_CTRL_FONCTIONAL_TEST_MODE (1<<31)
+
+//WakeUp
+#define SYS_CTRL_FORCE_WAKEUP      (1<<0)
+
+//AP_Ctrl
+#define SYS_CTRL_AP_INT_STATUS     (1<<0)
+#define SYS_CTRL_AP_INT_MASK       (1<<16)
+#define SYS_CTRL_AP_DEEPSLEEP_EN   (1<<24)
+
+//Ignore_Charger
+#define SYS_CTRL_IGNORE_CHARGER    (1<<0)
+
+//Clk_SYS2_Mode
+#define SYS_CTRL_MODE_SYS_MPMC_AUTOMATIC (0<<0)
+#define SYS_CTRL_MODE_SYS_MPMC_MANUAL (1<<0)
+#define SYS_CTRL_MODE_SYS_MPMCREG_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_SYS_MPMCREG_MANUAL (1<<1)
+#define SYS_CTRL_MODE_CLK_SYS2(n)  (((n)&3)<<0)
+#define SYS_CTRL_MODE_CLK_SYS2_MASK (3<<0)
+#define SYS_CTRL_MODE_CLK_SYS2_SHIFT (0)
+
+//Clk_SYS2_Enable
+#define SYS_CTRL_ENABLE_SYS_MPMC   (1<<0)
+#define SYS_CTRL_ENABLE_SYS_MPMCREG (1<<1)
+#define SYS_CTRL_ENABLE_SYS_DP_BB  (1<<2)
+#define SYS_CTRL_ENABLE_SYS_DP_WD  (1<<3)
+#define SYS_CTRL_ENABLE_SYS_DP_AP  (1<<4)
+#define SYS_CTRL_ENABLE_CLK_SYS2(n) (((n)&31)<<0)
+#define SYS_CTRL_ENABLE_CLK_SYS2_MASK (31<<0)
+#define SYS_CTRL_ENABLE_CLK_SYS2_SHIFT (0)
+
+//Clk_SYS2_Disable
+#define SYS_CTRL_DISABLE_SYS_MPMC  (1<<0)
+#define SYS_CTRL_DISABLE_SYS_MPMCREG (1<<1)
+#define SYS_CTRL_DISABLE_SYS_DP_BB (1<<2)
+#define SYS_CTRL_DISABLE_SYS_DP_WD (1<<3)
+#define SYS_CTRL_DISABLE_SYS_DP_AP (1<<4)
+#define SYS_CTRL_DISABLE_CLK_SYS2(n) (((n)&31)<<0)
+#define SYS_CTRL_DISABLE_CLK_SYS2_MASK (31<<0)
+#define SYS_CTRL_DISABLE_CLK_SYS2_SHIFT (0)
+
+//WD_Pll_Ctrl
+#define SYS_CTRL_WD_PLL_ENABLE     (1<<0)
+#define SYS_CTRL_WD_PLL_ENABLE_MASK (1<<0)
+#define SYS_CTRL_WD_PLL_ENABLE_SHIFT (0)
+#define SYS_CTRL_WD_PLL_ENABLE_POWER_DOWN (0<<0)
+#define SYS_CTRL_WD_PLL_ENABLE_ENABLE (1<<0)
+#define SYS_CTRL_WD_PLL_LOCK_RESET (1<<4)
+#define SYS_CTRL_WD_PLL_LOCK_RESET_MASK (1<<4)
+#define SYS_CTRL_WD_PLL_LOCK_RESET_SHIFT (4)
+#define SYS_CTRL_WD_PLL_LOCK_RESET_RESET (0<<4)
+#define SYS_CTRL_WD_PLL_LOCK_RESET_NO_RESET (1<<4)
+#define SYS_CTRL_WD_PLL_BYPASS     (1<<8)
+#define SYS_CTRL_WD_PLL_BYPASS_MASK (1<<8)
+#define SYS_CTRL_WD_PLL_BYPASS_SHIFT (8)
+#define SYS_CTRL_WD_PLL_BYPASS_PASS (0<<8)
+#define SYS_CTRL_WD_PLL_BYPASS_BYPASS (1<<8)
+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE (1<<12)
+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE_MASK (1<<12)
+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE_SHIFT (12)
+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE_ENABLE (1<<12)
+#define SYS_CTRL_WD_PLL_CLK_FAST_ENABLE_DISABLE (0<<12)
+#define SYS_CTRL_PLL_WD_CFG(n)     (((n)&4369)<<0)
+#define SYS_CTRL_PLL_WD_CFG_MASK   (4369<<0)
+#define SYS_CTRL_PLL_WD_CFG_SHIFT  (0)
+
+//WD_Sel_Clock
+#define SYS_CTRL_WD_CLK_ADC_POL_INVERT (1<<0)
+#define SYS_CTRL_WD_CLK_ADC_POL_NORMAL (0<<0)
+#define SYS_CTRL_WD_SYS_SEL_FAST_SLOW (1<<4)
+#define SYS_CTRL_WD_SYS_SEL_FAST_FAST (0<<4)
+#define SYS_CTRL_WD_PLL_BYPASS_LOCK (1<<8)
+#define SYS_CTRL_WD_PLL_LOCKED     (1<<20)
+#define SYS_CTRL_WD_PLL_LOCKED_MASK (1<<20)
+#define SYS_CTRL_WD_PLL_LOCKED_SHIFT (20)
+#define SYS_CTRL_WD_PLL_LOCKED_LOCKED (1<<20)
+#define SYS_CTRL_WD_PLL_LOCKED_NOT_LOCKED (0<<20)
+#define SYS_CTRL_WD_FAST_SELECTED_L (1<<24)
+#define SYS_CTRL_WD_FAST_SELECTED_L_MASK (1<<24)
+#define SYS_CTRL_WD_FAST_SELECTED_L_SHIFT (24)
+
+//WD_Rst_Set
+#define SYS_CTRL_SET_WD_RST_WCPU   (1<<0)
+#define SYS_CTRL_SET_WD_RST_IRQ    (1<<1)
+#define SYS_CTRL_SET_WD_RST_DP     (1<<2)
+#define SYS_CTRL_SET_WD_RST_MODEM  (1<<3)
+#define SYS_CTRL_SET_WD_RST_A2A    (1<<4)
+#define SYS_CTRL_SET_WD_RST_IFC    (1<<5)
+#define SYS_CTRL_SET_WD_RST_SDMA   (1<<6)
+#define SYS_CTRL_SET_WD_RST_SLPC   (1<<7)
+#define SYS_CTRL_SET_WD_RST_SLPT   (1<<8)
+#define SYS_CTRL_SET_WD_RST_SPI1   (1<<9)
+#define SYS_CTRL_SET_WD_RST_SPI2   (1<<10)
+#define SYS_CTRL_SET_WD_RST_RFIF   (1<<11)
+#define SYS_CTRL_SET_WD_RST_COMREGS (1<<12)
+#define SYS_CTRL_SET_WD_RST_TIMER  (1<<13)
+#define SYS_CTRL_SET_WD_RST_MPMC   (1<<14)
+#define SYS_CTRL_SET_WD_RST_FULL   (1<<31)
+#define SYS_CTRL_SET_WD_RST(n)     (((n)&0x7FFF)<<0)
+#define SYS_CTRL_SET_WD_RST_MASK   (0x7FFF<<0)
+#define SYS_CTRL_SET_WD_RST_SHIFT  (0)
+
+//WD_Rst_Clr
+#define SYS_CTRL_CLR_WD_RST_WCPU   (1<<0)
+#define SYS_CTRL_CLR_WD_RST_IRQ    (1<<1)
+#define SYS_CTRL_CLR_WD_RST_DP     (1<<2)
+#define SYS_CTRL_CLR_WD_RST_MODEM  (1<<3)
+#define SYS_CTRL_CLR_WD_RST_A2A    (1<<4)
+#define SYS_CTRL_CLR_WD_RST_IFC    (1<<5)
+#define SYS_CTRL_CLR_WD_RST_SDMA   (1<<6)
+#define SYS_CTRL_CLR_WD_RST_SLPC   (1<<7)
+#define SYS_CTRL_CLR_WD_RST_SLPT   (1<<8)
+#define SYS_CTRL_CLR_WD_RST_SPI1   (1<<9)
+#define SYS_CTRL_CLR_WD_RST_SPI2   (1<<10)
+#define SYS_CTRL_CLR_WD_RST_RFIF   (1<<11)
+#define SYS_CTRL_CLR_WD_RST_COMREGS (1<<12)
+#define SYS_CTRL_CLR_WD_RST_TIMER  (1<<13)
+#define SYS_CTRL_CLR_WD_RST_MPMC   (1<<14)
+#define SYS_CTRL_CLR_WD_RST_FULL   (1<<31)
+#define SYS_CTRL_CLR_WD_RST(n)     (((n)&0x7FFF)<<0)
+#define SYS_CTRL_CLR_WD_RST_MASK   (0x7FFF<<0)
+#define SYS_CTRL_CLR_WD_RST_SHIFT  (0)
+
+//AP_Rst_Set
+#define SYS_CTRL_SET_AP_RST_0      (1<<0)
+#define SYS_CTRL_SET_AP_RST_1      (1<<1)
+#define SYS_CTRL_SET_AP_RST_2      (1<<2)
+#define SYS_CTRL_SET_AP_RST_3      (1<<3)
+#define SYS_CTRL_SET_AP_RST_4      (1<<4)
+#define SYS_CTRL_SET_AP_RST(n)     (((n)&31)<<0)
+#define SYS_CTRL_SET_AP_RST_MASK   (31<<0)
+#define SYS_CTRL_SET_AP_RST_SHIFT  (0)
+
+//AP_Rst_Clr
+#define SYS_CTRL_CLR_AP_RST_0      (1<<0)
+#define SYS_CTRL_CLR_AP_RST_1      (1<<1)
+#define SYS_CTRL_CLR_AP_RST_2      (1<<2)
+#define SYS_CTRL_CLR_AP_RST_3      (1<<3)
+#define SYS_CTRL_CLR_AP_RST_4      (1<<4)
+#define SYS_CTRL_CLR_AP_RST(n)     (((n)&31)<<0)
+#define SYS_CTRL_CLR_AP_RST_MASK   (31<<0)
+#define SYS_CTRL_CLR_AP_RST_SHIFT  (0)
+
+//Clk_WD_Mode
+#define SYS_CTRL_MODE_WD_WCPU      (1<<0)
+#define SYS_CTRL_MODE_WD_AMBA_AUTOMATIC (0<<1)
+#define SYS_CTRL_MODE_WD_AMBA_MANUAL (1<<1)
+#define SYS_CTRL_MODE_WD_PCLK_CONF_AUTOMATIC (0<<2)
+#define SYS_CTRL_MODE_WD_PCLK_CONF_MANUAL (1<<2)
+#define SYS_CTRL_MODE_WD_PCLK_DATA_AUTOMATIC (0<<3)
+#define SYS_CTRL_MODE_WD_PCLK_DATA_MANUAL (1<<3)
+#define SYS_CTRL_MODE_WD_A2A_AUTOMATIC (0<<4)
+#define SYS_CTRL_MODE_WD_A2A_MANUAL (1<<4)
+#define SYS_CTRL_MODE_WD_IFC_CH_SPI_AUTOMATIC (0<<5)
+#define SYS_CTRL_MODE_WD_IFC_CH_SPI_MANUAL (1<<5)
+#define SYS_CTRL_MODE_WD_MPMC_AUTOMATIC (0<<6)
+#define SYS_CTRL_MODE_WD_MPMC_MANUAL (1<<6)
+#define SYS_CTRL_MODE_WDD_OSC_AUTOMATIC (0<<7)
+#define SYS_CTRL_MODE_WDD_OSC_MANUAL (1<<7)
+#define SYS_CTRL_MODE_CLK_WD(n)    (((n)&0x7F)<<1)
+#define SYS_CTRL_MODE_CLK_WD_MASK  (0x7F<<1)
+#define SYS_CTRL_MODE_CLK_WD_SHIFT (1)
+
+//Clk_WD_Enable
+#define SYS_CTRL_ENABLE_WD_WCPU    (1<<0)
+#define SYS_CTRL_ENABLE_WD_AMBA    (1<<1)
+#define SYS_CTRL_ENABLE_WD_PCLK_CONF (1<<2)
+#define SYS_CTRL_ENABLE_WD_PCLK_DATA (1<<3)
+#define SYS_CTRL_ENABLE_WD_A2A     (1<<4)
+#define SYS_CTRL_ENABLE_WD_IFC_CH_SPI (1<<5)
+#define SYS_CTRL_ENABLE_WD_MPMC    (1<<6)
+#define SYS_CTRL_ENABLE_WDD_OSC    (1<<7)
+#define SYS_CTRL_ENABLE_WD_IRQ     (1<<8)
+#define SYS_CTRL_ENABLE_WD_AXI     (1<<9)
+#define SYS_CTRL_ENABLE_WD_DP      (1<<10)
+#define SYS_CTRL_ENABLE_WD_MODEM   (1<<11)
+#define SYS_CTRL_ENABLE_WD_COM_REGS (1<<12)
+#define SYS_CTRL_ENABLE_WD_TIMER   (1<<13)
+#define SYS_CTRL_ENABLE_WD_SDMA    (1<<14)
+#define SYS_CTRL_ENABLE_WD_SLPC    (1<<15)
+#define SYS_CTRL_ENABLE_WD_SLPT    (1<<16)
+#define SYS_CTRL_ENABLE_WD_SPI1    (1<<17)
+#define SYS_CTRL_ENABLE_WD_SPI2    (1<<18)
+#define SYS_CTRL_ENABLE_WD_RFIF    (1<<19)
+#define SYS_CTRL_ENABLE_CLK_WD(n)  (((n)&0xFFFFF)<<0)
+#define SYS_CTRL_ENABLE_CLK_WD_MASK (0xFFFFF<<0)
+#define SYS_CTRL_ENABLE_CLK_WD_SHIFT (0)
+
+//Clk_WD_Disable
+#define SYS_CTRL_DISABLE_WD_WCPU   (1<<0)
+#define SYS_CTRL_DISABLE_WD_AMBA   (1<<1)
+#define SYS_CTRL_DISABLE_WD_PCLK_CONF (1<<2)
+#define SYS_CTRL_DISABLE_WD_PCLK_DATA (1<<3)
+#define SYS_CTRL_DISABLE_WD_A2A    (1<<4)
+#define SYS_CTRL_DISABLE_WD_IFC_CH_SPI (1<<5)
+#define SYS_CTRL_DISABLE_WD_MPMC   (1<<6)
+#define SYS_CTRL_DISABLE_WDD_OSC   (1<<7)
+#define SYS_CTRL_DISABLE_WD_IRQ    (1<<8)
+#define SYS_CTRL_DISABLE_WD_AXI    (1<<9)
+#define SYS_CTRL_DISABLE_WD_DP     (1<<10)
+#define SYS_CTRL_DISABLE_WD_MODEM  (1<<11)
+#define SYS_CTRL_DISABLE_WD_COM_REGS (1<<12)
+#define SYS_CTRL_DISABLE_WD_TIMER  (1<<13)
+#define SYS_CTRL_DISABLE_WD_SDMA   (1<<14)
+#define SYS_CTRL_DISABLE_WD_SLPC   (1<<15)
+#define SYS_CTRL_DISABLE_WD_SLPT   (1<<16)
+#define SYS_CTRL_DISABLE_WD_SPI1   (1<<17)
+#define SYS_CTRL_DISABLE_WD_SPI2   (1<<18)
+#define SYS_CTRL_DISABLE_WD_RFIF   (1<<19)
+#define SYS_CTRL_DISABLE_CLK_WD(n) (((n)&0xFFFFF)<<0)
+#define SYS_CTRL_DISABLE_CLK_WD_MASK (0xFFFFF<<0)
+#define SYS_CTRL_DISABLE_CLK_WD_SHIFT (0)
+
+//Cfg_Clk_MPMC
+#define SYS_CTRL_MPMC_FREQ(n)      (((n)&15)<<0)
+#define SYS_CTRL_MPMC_FREQ_MASK    (15<<0)
+#define SYS_CTRL_MPMC_FREQ_SHIFT   (0)
+#define SYS_CTRL_MPMC_FREQ_312M    (13<<0)
+#define SYS_CTRL_MPMC_FREQ_250M    (12<<0)
+#define SYS_CTRL_MPMC_FREQ_208M    (11<<0)
+#define SYS_CTRL_MPMC_FREQ_178M    (10<<0)
+#define SYS_CTRL_MPMC_FREQ_156M    (9<<0)
+#define SYS_CTRL_MPMC_FREQ_139M    (8<<0)
+#define SYS_CTRL_MPMC_FREQ_125M    (7<<0)
+#define SYS_CTRL_MPMC_FREQ_113M    (6<<0)
+#define SYS_CTRL_MPMC_FREQ_104M    (5<<0)
+#define SYS_CTRL_MPMC_FREQ_89M     (4<<0)
+#define SYS_CTRL_MPMC_FREQ_78M     (3<<0)
+#define SYS_CTRL_MPMC_FREQ_52M     (2<<0)
+#define SYS_CTRL_MPMC_FREQ_39M     (1<<0)
+#define SYS_CTRL_MPMC_FREQ_26M     (0<<0)
+#define SYS_CTRL_CLK_MPMC_DELAY(n) (((n)&31)<<8)
+#define SYS_CTRL_CLK_MPMC_DELAY_POL (1<<13)
+#define SYS_CTRL_CLK_MPMC_FEEDBACK(n) (((n)&31)<<14)
+#define SYS_CTRL_CLK_MPMC_FEEDBACK_POL (1<<19)
+#define SYS_CTRL_MPMC_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_MPMC_DQS
+#define SYS_CTRL_MPMC_DQSL_O(n)    (((n)&31)<<0)
+#define SYS_CTRL_MPMC_DQSU_O(n)    (((n)&31)<<6)
+#define SYS_CTRL_MPMC_DQS_OEN(n)   (((n)&31)<<12)
+#define SYS_CTRL_MPMC_DQSL_I(n)    (((n)&31)<<18)
+#define SYS_CTRL_MPMC_DQSU_I(n)    (((n)&31)<<24)
+
+//Cfg_Reserve
+#define SYS_CTRL_RESERVE(n)        (((n)&0x3FFF)<<0)
+#define SYS_CTRL_AUIFC_CH0_IRQ_MASK (1<<14)
+#define SYS_CTRL_AUIFC_CH1_IRQ_MASK (1<<15)
+#define SYS_CTRL_RESERVE2(n)       (((n)&0xFFFF)<<16)
+
+
+
+
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/reg_mdcom.h b/arch/arm/include/asm/arch-rda/reg_mdcom.h
new file mode 100644
index 0000000000..a9223a4f21
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_mdcom.h
@@ -0,0 +1,80 @@
+#ifndef _REG_MDCOM_H_
+#define _REG_MDCOM_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+typedef volatile struct
+{
+    REG32                          Snapshot;                     //0x00000000
+    REG32                          Snapshot_Cfg;                 //0x00000004
+    REG32                          Cause;                        //0x00000008
+    REG32                          Mask_Set;                     //0x0000000C
+    REG32                          Mask_Clr;                     //0x00000010
+    /// If accesses to ItReg_Set and ItReg_Clr registers are done simultaneously
+    /// from both CPUs and affecting the same bits, the priority is given to set
+    /// a bit.
+    REG32                          ItReg_Set;                    //0x00000014
+    /// If accesses to ItReg_Set and ItReg_Clr registers are done simultaneously
+    /// from both CPUs and affecting the same bits, the priority is given to set
+    /// a bit.
+    REG32                          ItReg_Clr;                    //0x00000018
+} HWP_COMREGS_T;
+
+#define hwp_mdComregs               ((HWP_COMREGS_T*)(RDA_COMREGS_BASE))
+
+
+//Snapshot
+#define COMREGS_SNAPSHOT(n)         (((n)&3)<<0)
+
+//Snapshot_Cfg
+#define COMREGS_SNAPSHOT_CFG_WRAP_2 (2<<0)
+#define COMREGS_SNAPSHOT_CFG_WRAP_3 (3<<0)
+
+//Cause
+#define COMREGS_IRQ0_CAUSE(n)       (((n)&0xFF)<<0)
+#define COMREGS_IRQ0_CAUSE_MASK     (0xFF<<0)
+#define COMREGS_IRQ0_CAUSE_SHIFT    (0)
+#define COMREGS_IRQ1_CAUSE(n)       (((n)&0xFF)<<8)
+#define COMREGS_IRQ1_CAUSE_MASK     (0xFF<<8)
+#define COMREGS_IRQ1_CAUSE_SHIFT    (8)
+
+//Mask_Set
+#define COMREGS_IRQ0_MASK_SET(n)    (((n)&0xFF)<<0)
+#define COMREGS_IRQ0_MASK_SET_MASK  (0xFF<<0)
+#define COMREGS_IRQ0_MASK_SET_SHIFT (0)
+#define COMREGS_IRQ1_MASK_SET(n)    (((n)&0xFF)<<8)
+#define COMREGS_IRQ1_MASK_SET_MASK  (0xFF<<8)
+#define COMREGS_IRQ1_MASK_SET_SHIFT (8)
+
+//Mask_Clr
+#define COMREGS_IRQ0_MASK_CLR(n)    (((n)&0xFF)<<0)
+#define COMREGS_IRQ0_MASK_CLR_MASK  (0xFF<<0)
+#define COMREGS_IRQ0_MASK_CLR_SHIFT (0)
+#define COMREGS_IRQ1_MASK_CLR(n)    (((n)&0xFF)<<8)
+#define COMREGS_IRQ1_MASK_CLR_MASK  (0xFF<<8)
+#define COMREGS_IRQ1_MASK_CLR_SHIFT (8)
+
+//ItReg_Set
+#define COMREGS_IRQ0_SET(n)         (((n)&0xFF)<<0)
+#define COMREGS_IRQ0_SET_MASK       (0xFF<<0)
+#define COMREGS_IRQ0_SET_SHIFT      (0)
+#define COMREGS_IRQ1_SET(n)         (((n)&0xFF)<<8)
+#define COMREGS_IRQ1_SET_MASK       (0xFF<<8)
+#define COMREGS_IRQ1_SET_SHIFT      (8)
+#define COMREGS_IRQ(n)              (((n)&0xFFFF)<<0)
+#define COMREGS_IRQ_MASK            (0xFFFF<<0)
+#define COMREGS_IRQ_SHIFT           (0)
+
+//ItReg_Clr
+#define COMREGS_IRQ0_CLR(n)         (((n)&0xFF)<<0)
+#define COMREGS_IRQ0_CLR_MASK       (0xFF<<0)
+#define COMREGS_IRQ0_CLR_SHIFT      (0)
+#define COMREGS_IRQ1_CLR(n)         (((n)&0xFF)<<8)
+#define COMREGS_IRQ1_CLR_MASK       (0xFF<<8)
+#define COMREGS_IRQ1_CLR_SHIFT      (8)
+//#define COMREGS_IRQ(n)            (((n)&0xFFFF)<<0)
+//#define COMREGS_IRQ_MASK          (0xFFFF<<0)
+//#define COMREGS_IRQ_SHIFT         (0)
+
+#endif
diff --git a/arch/arm/include/asm/arch-rda/reg_mmc.h b/arch/arm/include/asm/arch-rda/reg_mmc.h
new file mode 100644
index 0000000000..87d8e3e3c3
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_mmc.h
@@ -0,0 +1,245 @@
+#ifndef _REG_SDMMC_H_
+#define _REG_SDMMC_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+// ============================================================================
+// SDMMC_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef volatile struct
+{
+    REG32                          apbi_ctrl_sdmmc;              //0x00000000
+    REG32 Reserved_00000004;                    //0x00000004
+    REG32                          APBI_FIFO_TxRx;               //0x00000008
+    REG32 Reserved_0000000C[509];               //0x0000000C
+    REG32                          SDMMC_CONFIG;                 //0x00000800
+    REG32                          SDMMC_STATUS;                 //0x00000804
+    REG32                          SDMMC_CMD_INDEX;              //0x00000808
+    REG32                          SDMMC_CMD_ARG;                //0x0000080C
+    REG32                          SDMMC_RESP_INDEX;             //0x00000810
+    REG32                          SDMMC_RESP_ARG3;              //0x00000814
+    REG32                          SDMMC_RESP_ARG2;              //0x00000818
+    REG32                          SDMMC_RESP_ARG1;              //0x0000081C
+    REG32                          SDMMC_RESP_ARG0;              //0x00000820
+    REG32                          SDMMC_DATA_WIDTH;             //0x00000824
+    REG32                          SDMMC_BLOCK_SIZE;             //0x00000828
+    REG32                          SDMMC_BLOCK_CNT;              //0x0000082C
+    REG32                          SDMMC_INT_STATUS;             //0x00000830
+    REG32                          SDMMC_INT_MASK;               //0x00000834
+    REG32                          SDMMC_INT_CLEAR;              //0x00000838
+    REG32                          SDMMC_TRANS_SPEED;            //0x0000083C
+    REG32                          SDMMC_MCLK_ADJUST;            //0x00000840
+} HWP_SDMMC_T;
+
+//apbi_ctrl_sdmmc
+#define SDMMC_L_ENDIAN(n)           (((n)&7)<<0)
+#define SDMMC_SOFT_RST_L            (1<<3)
+
+//APBI_FIFO_TxRx
+#define SDMMC_DATA_IN(n)            (((n)&0xFFFFFFFF)<<0)
+#define SDMMC_DATA_OUT(n)           (((n)&0xFFFFFFFF)<<0)
+
+//SDMMC_CONFIG
+#define SDMMC_SDMMC_SENDCMD         (1<<0)
+#define SDMMC_SDMMC_SUSPEND         (1<<1)
+#define SDMMC_RSP_EN                (1<<4)
+#define SDMMC_RSP_SEL(n)            (((n)&3)<<5)
+#define SDMMC_RSP_SEL_R2            (2<<5)
+#define SDMMC_RSP_SEL_R3            (1<<5)
+#define SDMMC_RSP_SEL_OTHER         (0<<5)
+#define SDMMC_RD_WT_EN              (1<<8)
+#define SDMMC_RD_WT_SEL             (1<<9)
+#define SDMMC_RD_WT_SEL_READ        (0<<9)
+#define SDMMC_RD_WT_SEL_WRITE       (1<<9)
+#define SDMMC_S_M_SEL               (1<<10)
+#define SDMMC_S_M_SEL_SIMPLE        (0<<10)
+#define SDMMC_S_M_SEL_MULTIPLE      (1<<10)
+#define SDMMC_AUTO_FLAG_EN          (1<<16)
+
+//SDMMC_STATUS
+#define SDMMC_NOT_SDMMC_OVER        (1<<0)
+#define SDMMC_BUSY                  (1<<1)
+#define SDMMC_DL_BUSY               (1<<2)
+#define SDMMC_SUSPEND               (1<<3)
+#define SDMMC_RSP_ERROR             (1<<8)
+#define SDMMC_NO_RSP_ERROR          (1<<9)
+#define SDMMC_CRC_STATUS(n)         (((n)&7)<<12)
+#define SDMMC_DATA_ERROR(n)         (((n)&0xFF)<<16)
+#define SDMMC_DAT3_VAL              (1<<24)
+#define SDMMC_DATA0_VAL             (1 << 26)
+
+//SDMMC_CMD_INDEX
+#define SDMMC_COMMAND(n)            (((n)&0x3F)<<0)
+
+//SDMMC_CMD_ARG
+#define SDMMC_ARGUMENT(n)           (((n)&0xFFFFFFFF)<<0)
+
+//SDMMC_RESP_INDEX
+#define SDMMC_RESPONSE(n)           (((n)&0x3F)<<0)
+
+//SDMMC_RESP_ARG3
+#define SDMMC_ARGUMENT3(n)          (((n)&0xFFFFFFFF)<<0)
+
+//SDMMC_RESP_ARG2
+#define SDMMC_ARGUMENT2(n)          (((n)&0xFFFFFFFF)<<0)
+
+//SDMMC_RESP_ARG1
+#define SDMMC_ARGUMENT1(n)          (((n)&0xFFFFFFFF)<<0)
+
+//SDMMC_RESP_ARG0
+#define SDMMC_ARGUMENT0(n)          (((n)&0xFFFFFFFF)<<0)
+
+//SDMMC_DATA_WIDTH
+#define SDMMC_SDMMC_DATA_WIDTH(n)   (((n)&15)<<0)
+
+//SDMMC_BLOCK_SIZE
+#define SDMMC_SDMMC_BLOCK_SIZE(n)   (((n)&15)<<0)
+
+//SDMMC_BLOCK_CNT
+#define SDMMC_SDMMC_BLOCK_CNT(n)    (((n)&0xFFFF)<<0)
+
+//SDMMC_INT_STATUS
+#define SDMMC_NO_RSP_INT            (1<<0)
+#define SDMMC_RSP_ERR_INT           (1<<1)
+#define SDMMC_RD_ERR_INT            (1<<2)
+#define SDMMC_WR_ERR_INT            (1<<3)
+#define SDMMC_DAT_OVER_INT          (1<<4)
+#define SDMMC_TXDMA_DONE_INT        (1<<5)
+#define SDMMC_RXDMA_DONE_INT        (1<<6)
+#define SDMMC_NO_RSP_SC             (1<<8)
+#define SDMMC_RSP_ERR_SC            (1<<9)
+#define SDMMC_RD_ERR_SC             (1<<10)
+#define SDMMC_WR_ERR_SC             (1<<11)
+#define SDMMC_DAT_OVER_SC           (1<<12)
+#define SDMMC_TXDMA_DONE_SC         (1<<13)
+#define SDMMC_RXDMA_DONE_SC         (1<<14)
+
+//SDMMC_INT_MASK
+#define SDMMC_NO_RSP_MK             (1<<0)
+#define SDMMC_RSP_ERR_MK            (1<<1)
+#define SDMMC_RD_ERR_MK             (1<<2)
+#define SDMMC_WR_ERR_MK             (1<<3)
+#define SDMMC_DAT_OVER_MK           (1<<4)
+#define SDMMC_TXDMA_DONE_MK         (1<<5)
+#define SDMMC_RXDMA_DONE_MK         (1<<6)
+
+//SDMMC_INT_CLEAR
+#define SDMMC_NO_RSP_CL             (1<<0)
+#define SDMMC_RSP_ERR_CL            (1<<1)
+#define SDMMC_RD_ERR_CL             (1<<2)
+#define SDMMC_WR_ERR_CL             (1<<3)
+#define SDMMC_DAT_OVER_CL           (1<<4)
+#define SDMMC_TXDMA_DONE_CL         (1<<5)
+#define SDMMC_RXDMA_DONE_CL         (1<<6)
+
+//SDMMC_TRANS_SPEED
+#define SDMMC_SDMMC_TRANS_SPEED(n)  (((n)&0xFF)<<0)
+
+//SDMMC_MCLK_ADJUST
+#define SDMMC_SDMMC_MCLK_ADJUST(n)  (((n)&15)<<0)
+#define SDMMC_CLK_INV               (1<<4)
+
+// =============================================================================
+// MACROS
+// =============================================================================
+// =============================================================================
+// HAL_SDMMC_ACMD_SEL
+// -----------------------------------------------------------------------------
+/// Macro to mark a command as application specific
+// =============================================================================
+#define HAL_SDMMC_ACMD_SEL         0x80000000
+
+
+// =============================================================================
+// HAL_SDMMC_CMD_MASK
+// -----------------------------------------------------------------------------
+/// Mask to get from a HAL_SDMMC_CMD_T value the corresponding 
+/// command index
+// =============================================================================
+#define HAL_SDMMC_CMD_MASK 0x3F
+
+
+
+// =============================================================================
+// HAL_SDMMC_CMD_T
+// -----------------------------------------------------------------------------
+// SD commands
+// =============================================================================
+typedef enum
+{
+    HAL_SDMMC_CMD_GO_IDLE_STATE         = 0,
+    HAL_SDMMC_CMD_MMC_SEND_OP_COND      = 1,
+    HAL_SDMMC_CMD_ALL_SEND_CID            = 2,
+    HAL_SDMMC_CMD_SEND_RELATIVE_ADDR    = 3,
+    HAL_SDMMC_CMD_SET_DSR                = 4,
+    HAL_SDMMC_CMD_SWITCH           = 6,
+    HAL_SDMMC_CMD_SELECT_CARD            = 7,
+    HAL_SDMMC_CMD_SEND_IF_COND          = 8,
+    HAL_SDMMC_CMD_SEND_CSD                = 9,
+    HAL_SDMMC_CMD_STOP_TRANSMISSION        = 12,
+    HAL_SDMMC_CMD_SEND_STATUS            = 13,
+    HAL_SDMMC_CMD_SET_BLOCKLEN            = 16,
+    HAL_SDMMC_CMD_READ_SINGLE_BLOCK        = 17,
+    HAL_SDMMC_CMD_READ_MULT_BLOCK        = 18,
+    HAL_SDMMC_CMD_WRITE_SINGLE_BLOCK    = 24,
+    HAL_SDMMC_CMD_WRITE_MULT_BLOCK        = 25,
+    HAL_SDMMC_CMD_APP_CMD                = 55,
+    HAL_SDMMC_CMD_SET_BUS_WIDTH            = (6 | HAL_SDMMC_ACMD_SEL),
+    HAL_SDMMC_CMD_SEND_NUM_WR_BLOCKS    = (22| HAL_SDMMC_ACMD_SEL),
+    HAL_SDMMC_CMD_SET_WR_BLK_COUNT        = (23| HAL_SDMMC_ACMD_SEL),
+    HAL_SDMMC_CMD_SEND_OP_COND            = (41| HAL_SDMMC_ACMD_SEL)
+} HAL_SDMMC_CMD_T;
+
+// =============================================================================
+// HAL_SDMMC_OP_STATUS_T
+// -----------------------------------------------------------------------------
+/// This structure is used the module operation status. It is different from the 
+/// IRQ status.
+// =============================================================================
+typedef union
+{
+    u32 reg;
+    struct
+    {
+        u32 operationNotOver     :1;
+        /// Module is busy ?
+        u32 busy                 :1;
+        u32 dataLineBusy         :1;
+        /// '1' means the controller will not perform the new command when SDMMC_SENDCMD= '1'.
+        u32 suspend              :1;
+        u32                      :4;
+        u32 responseCrcError     :1;
+        /// 1 as long as no reponse to a command has been received.
+        u32 noResponseReceived   :1;
+        u32                      :2;
+        /// CRC check for SD/MMC write operation
+        /// "101" transmission error
+        /// "010" transmission right
+        /// "111" flash programming error
+        u32 crcStatus            :3;
+        u32                      :1;
+        /// 8 bits data CRC check, "00000000" means no data error, 
+        /// "00000001" means DATA0 CRC check error, "10000000" means 
+        /// DATA7 CRC check error, each bit match one data line.
+        u32 dataError            :8;
+    } fields;
+} HAL_SDMMC_OP_STATUS_T;
+
+typedef enum
+{
+    HAL_SDMMC_DIRECTION_READ,
+    HAL_SDMMC_DIRECTION_WRITE,
+    HAL_SDMMC_DIRECTION_QTY
+} HAL_SDMMC_DIRECTION_T;
+
+typedef enum
+{
+    HAL_SDMMC_DATA_BUS_WIDTH_1 = 0x0,
+    HAL_SDMMC_DATA_BUS_WIDTH_4 = 0x2
+} HAL_SDMMC_DATA_BUS_WIDTH_T;
+
+#endif /* _REG_SDMMC_H_ */
+
diff --git a/arch/arm/include/asm/arch-rda/reg_nand.h b/arch/arm/include/asm/arch-rda/reg_nand.h
new file mode 100644
index 0000000000..5fd490c606
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_nand.h
@@ -0,0 +1,17 @@
+#ifndef _REG_NAND_H_
+#define _REG_NAND_H_
+
+#include <common.h>
+
+#ifdef CONFIG_NAND_RDA_V1
+#include "reg_nand_v1.h"
+#elif defined(CONFIG_NAND_RDA_V2)
+#include "reg_nand_v2.h"
+#elif defined(CONFIG_NAND_RDA_V3)
+#include "reg_nand_v3.h"
+#else
+#error "undefined RDA NAND Controller Version"
+#endif
+
+#endif /* _REG_NAND_H_ */
+
diff --git a/arch/arm/include/asm/arch-rda/reg_nand_v1.h b/arch/arm/include/asm/arch-rda/reg_nand_v1.h
new file mode 100644
index 0000000000..8b5b5ddb13
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_nand_v1.h
@@ -0,0 +1,106 @@
+#ifndef _REG_NAND_V1_H_
+#define _REG_NAND_V1_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+#define REG_NANDFC_BASE     RDA_NAND_BASE
+
+#define NANDFC_DATA_BUF         (REG_NANDFC_BASE + 0x0000)
+#define NANDFC_OOB_BUF          (REG_NANDFC_BASE + 0x1000)
+
+#if defined(CONFIG_MACH_RDA8810) || defined(CONFIG_MACH_RDA8850) || \
+	defined(CONFIG_MACH_RDAARM926EJS)
+#define NANDFC_REG_DCMD_ADDR    (REG_NANDFC_BASE + 0x2000)
+//#define NANDFC_REG_OP_START     (REG_NANDFC_BASE + 0x2004)
+//#define NANDFC_REG_CMD_PTR      (REG_NANDFC_BASE + 0x2008)
+#define NANDFC_REG_COL_ADDR     (REG_NANDFC_BASE + 0x200c)
+#define NANDFC_REG_CONFIG_A     (REG_NANDFC_BASE + 0x2010)
+#define NANDFC_REG_CONFIG_B     (REG_NANDFC_BASE + 0x2014)
+#define NANDFC_REG_BUF_CTRL     (REG_NANDFC_BASE + 0x2018)
+#define NANDFC_REG_BUSY_FLAG    (REG_NANDFC_BASE + 0x201c)
+#define NANDFC_REG_INT_MASK     (REG_NANDFC_BASE + 0x2020)
+#define NANDFC_REG_INT_STAT     (REG_NANDFC_BASE + 0x2024)
+#define NANDFC_REG_IDCODE_A     (REG_NANDFC_BASE + 0x2028)
+#define NANDFC_REG_IDCODE_B     (REG_NANDFC_BASE + 0x202c)
+//#define NANDFC_REG_DMA_REQ      (REG_NANDFC_BASE + 0x2030)
+//#define NANDFC_REG_CMD_DEF_A    (REG_NANDFC_BASE + 0x2034)
+#define NANDFC_REG_CMD_DEF_B    (REG_NANDFC_BASE + 0x2038)
+#define NANDFC_REG_OP_STATUS    (REG_NANDFC_BASE + 0x203c)
+#define NANDFC_REG_IDTPYE       (REG_NANDFC_BASE + 0x2040)
+#define NANDFC_REG_DELAY        (REG_NANDFC_BASE + 0x2054)
+#else
+/* for 8810e, 8820, or later */
+#define NANDFC_REG_DCMD_ADDR    (REG_NANDFC_BASE + 0x3000)
+//#define NANDFC_REG_OP_START     (REG_NANDFC_BASE + 0x3004)
+//#define NANDFC_REG_CMD_PTR      (REG_NANDFC_BASE + 0x3008)
+#define NANDFC_REG_COL_ADDR     (REG_NANDFC_BASE + 0x300c)
+#define NANDFC_REG_CONFIG_A     (REG_NANDFC_BASE + 0x3010)
+#define NANDFC_REG_CONFIG_B     (REG_NANDFC_BASE + 0x3014)
+#define NANDFC_REG_BUF_CTRL     (REG_NANDFC_BASE + 0x3018)
+#define NANDFC_REG_BUSY_FLAG    (REG_NANDFC_BASE + 0x301c)
+#define NANDFC_REG_INT_MASK     (REG_NANDFC_BASE + 0x3020)
+#define NANDFC_REG_INT_STAT     (REG_NANDFC_BASE + 0x3024)
+#define NANDFC_REG_IDCODE_A     (REG_NANDFC_BASE + 0x3028)
+#define NANDFC_REG_IDCODE_B     (REG_NANDFC_BASE + 0x302c)
+//#define NANDFC_REG_DMA_REQ      (REG_NANDFC_BASE + 0x3030)
+//#define NANDFC_REG_CMD_DEF_A    (REG_NANDFC_BASE + 0x3034)
+//#define NANDFC_REG_CMD_DEF_B    (REG_NANDFC_BASE + 0x3038)
+#define NANDFC_REG_OP_STATUS    (REG_NANDFC_BASE + 0x303c)
+#define NANDFC_REG_IDTPYE       (REG_NANDFC_BASE + 0x3040)
+#define NANDFC_REG_DELAY        (REG_NANDFC_BASE + 0x3054)
+#endif
+
+// NANDFC_REG_DCMD_ADDR
+#define NANDFC_DCMD(n)          (((n)&0xFF)<<24)
+#define NANDFC_PAGE_ADDR(n)     (((n)&0x000FFFFF)<<0)
+
+// NANDFC_REG_CONFIG_A
+#define NANDFC_CYCLE(n)         (((n)&0x0F)<<0)
+#define NANDFC_CHIP_SEL(n)      (((n)&0x0F)<<4)
+#define NANDFC_TIMING(n)        (((n)&0xFF)<<8)
+#define NANDFC_POLARITY_IO(n)   (((n)&0x01)<<16)
+#define NANDFC_POLARITY_MEM(n)  (((n)&0x01)<<17)
+#define NANDFC_WDITH_16BIT(n)   (((n)&0x01)<<18)
+
+// NANDFC_REG_CONFIG_B
+#define NANDFC_HWECC(n)         (((n)&0x01)<<7)
+#define NANDFC_ECC_MODE(n)      (((n)&0x0F)<<0)
+
+// NANDFC_REG_BUF_CTRL
+#define NANDFC_BUF_DIRECT(n)    (((n)&0x01)<<2)
+
+// NANDFC_REG_INT_STAT
+#define NANDFC_INT_ECC_ERR      (1<<0)
+#define NANDFC_INT_PROG_ERR     (1<<1)
+#define NANDFC_INT_ERASE_ERR    (1<<2)
+#define NANDFC_INT_TIMEOUT      (1<<3)
+#define NANDFC_INT_DONE         (1<<4)
+#define NANDFC_INT_CRC_FAIL     (1<<5)
+#define NANDFC_INT_ECC_ERR_0    (1<<6)
+#define NANDFC_INT_ECC_ERR_1    (1<<7)
+#define NANDFC_INT_ECC_ERR_2    (1<<8)
+#define NANDFC_INT_ECC_CRC_0    (1<<9)
+#define NANDFC_INT_ECC_CRC_1    (1<<10)
+#define NANDFC_INT_ECC_CRC_2    (1<<11)
+#define NANDFC_INT_ERR_ALL      (0x0FEF)
+#define NANDFC_INT_CLR_MASK     (0x0FDE)
+
+typedef enum
+{
+    NAND_TYPE_512S         = 0,   // 512+16, 64Mb, 128Mb, 256Mb
+    NAND_TYPE_512L         = 1,   // 512+16, 512Mb, 1Gb, 2Gb
+    NAND_TYPE_2KS          = 2,   // 2048+64, 1Gb (2 byte Row addresses)
+    NAND_TYPE_2KL          = 3,   // 2048+64, 2Gb, 4Gb, 8Gb, 16Gb (3 byte Row Addresses)
+    NAND_TYPE_MLC2K        = 4,   // MLC, 2048+64
+    NAND_TYPE_MLC4K        = 5,   // MLC, 4096+224, 16Gb, 32Gb
+    NAND_TYPE_SLC4K        = 6,   // SLC, 4096+224, 16Gb, 32Gb
+    NAND_TYPE_MLC8K        = 7,   // MLC, 8192+224, 16Gb, 32Gb
+    NAND_TYPE_SLC8K        = 8,   // SLC, 8192+224, 16Gb, 32Gb
+    NAND_TYPE_MLC16K        = 9,   // MLC,
+    NAND_TYPE_SLC16K        = 10,   // SLC,
+    NAND_TYPE_INVALID      = 0xff
+} NAND_FLASH_TYPE;
+
+#endif /* _REG_NAND_V1_H_ */
+
diff --git a/arch/arm/include/asm/arch-rda/reg_nand_v2.h b/arch/arm/include/asm/arch-rda/reg_nand_v2.h
new file mode 100644
index 0000000000..78c68e916b
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_nand_v2.h
@@ -0,0 +1,111 @@
+#ifndef _REG_NAND_V2_H_
+#define _REG_NAND_V2_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+#define REG_NANDFC_BASE     RDA_NAND_BASE
+
+#define NANDFC_DATA_BUF         (REG_NANDFC_BASE + 0x0000)
+#define NANDFC_OOB_BUF          (REG_NANDFC_BASE + 0x1000)
+
+#if defined(CONFIG_MACH_RDA8810) || defined(CONFIG_MACH_RDA8850) || \
+	defined(CONFIG_MACH_RDAARM926EJS)
+#define NANDFC_REG_DCMD_ADDR    (REG_NANDFC_BASE + 0x2000)
+//#define NANDFC_REG_OP_START     (REG_NANDFC_BASE + 0x2004)
+//#define NANDFC_REG_CMD_PTR      (REG_NANDFC_BASE + 0x2008)
+#define NANDFC_REG_COL_ADDR     (REG_NANDFC_BASE + 0x200c)
+#define NANDFC_REG_CONFIG_A     (REG_NANDFC_BASE + 0x2010)
+#define NANDFC_REG_CONFIG_B     (REG_NANDFC_BASE + 0x2014)
+#define NANDFC_REG_BUF_CTRL     (REG_NANDFC_BASE + 0x2018)
+#define NANDFC_REG_BUSY_FLAG    (REG_NANDFC_BASE + 0x201c)
+#define NANDFC_REG_INT_MASK     (REG_NANDFC_BASE + 0x2020)
+#define NANDFC_REG_INT_STAT     (REG_NANDFC_BASE + 0x2024)
+#define NANDFC_REG_IDCODE_A     (REG_NANDFC_BASE + 0x2028)
+#define NANDFC_REG_IDCODE_B     (REG_NANDFC_BASE + 0x202c)
+//#define NANDFC_REG_DMA_REQ      (REG_NANDFC_BASE + 0x2030)
+//#define NANDFC_REG_CMD_DEF_A    (REG_NANDFC_BASE + 0x2034)
+//#define NANDFC_REG_CMD_DEF_B    (REG_NANDFC_BASE + 0x2038)
+#define NANDFC_REG_OP_STATUS    (REG_NANDFC_BASE + 0x203c)
+#define NANDFC_REG_IDTPYE       (REG_NANDFC_BASE + 0x2040)
+#define NANDFC_REG_DELAY        (REG_NANDFC_BASE + 0x2054)
+#else
+/* for 8810e, 8820, or later */
+#define NANDFC_REG_DCMD_ADDR    (REG_NANDFC_BASE + 0x3000)
+//#define NANDFC_REG_OP_START     (REG_NANDFC_BASE + 0x3004)
+//#define NANDFC_REG_CMD_PTR      (REG_NANDFC_BASE + 0x3008)
+#define NANDFC_REG_COL_ADDR     (REG_NANDFC_BASE + 0x300c)
+#define NANDFC_REG_CONFIG_A     (REG_NANDFC_BASE + 0x3010)
+#define NANDFC_REG_CONFIG_B     (REG_NANDFC_BASE + 0x3014)
+#define NANDFC_REG_BUF_CTRL     (REG_NANDFC_BASE + 0x3018)
+#define NANDFC_REG_BUSY_FLAG    (REG_NANDFC_BASE + 0x301c)
+#define NANDFC_REG_INT_MASK     (REG_NANDFC_BASE + 0x3020)
+#define NANDFC_REG_INT_STAT     (REG_NANDFC_BASE + 0x3024)
+#define NANDFC_REG_IDCODE_A     (REG_NANDFC_BASE + 0x3028)
+#define NANDFC_REG_IDCODE_B     (REG_NANDFC_BASE + 0x302c)
+//#define NANDFC_REG_DMA_REQ      (REG_NANDFC_BASE + 0x3030)
+//#define NANDFC_REG_CMD_DEF_A    (REG_NANDFC_BASE + 0x3034)
+//#define NANDFC_REG_CMD_DEF_B    (REG_NANDFC_BASE + 0x3038)
+#define NANDFC_REG_OP_STATUS    (REG_NANDFC_BASE + 0x303c)
+#define NANDFC_REG_IDTPYE       (REG_NANDFC_BASE + 0x3040)
+#define NANDFC_REG_DELAY        (REG_NANDFC_BASE + 0x3054)
+#endif
+
+// NANDFC_REG_DCMD_ADDR
+#define NANDFC_DCMD(n)          (((n)&0xFF)<<24)
+#define NANDFC_PAGE_ADDR(n)     (((n)&0x000FFFFF)<<0)
+
+// NANDFC_REG_CONFIG_A
+#define NANDFC_CYCLE(n)         (((n)&0x0F)<<0)
+#define NANDFC_CHIP_SEL(n)      (((n)&0x0F)<<4)
+#define NANDFC_TIMING(n)        (((n)&0xFF)<<8)
+#define NANDFC_POLARITY_IO(n)   (((n)&0x01)<<16)
+#define NANDFC_POLARITY_MEM(n)  (((n)&0x01)<<17)
+#define NANDFC_WDITH_16BIT(n)   (((n)&0x01)<<18)
+
+// NANDFC_REG_CONFIG_B
+#define NANDFC_HWECC(n)         (((n)&0x01)<<7)
+#define NANDFC_ECC_MODE(n)      (((n)&0x0F)<<0)
+
+// NANDFC_REG_BUF_CTRL
+#define NANDFC_BUF_DIRECT(n)    (((n)&0x01)<<2)
+
+// NANDFC_REG_INT_STAT
+#define NANDFC_INT_ECC_ERR      (1<<0)
+#define NANDFC_INT_PROG_ERR     (1<<1)
+#define NANDFC_INT_ERASE_ERR    (1<<2)
+#define NANDFC_INT_TIMEOUT      (1<<3)
+#define NANDFC_INT_DONE         (1<<4)
+#define NANDFC_INT_CRC_FAIL     (1<<5)
+#define NANDFC_INT_ECC_ERR_0    (1<<6)
+#define NANDFC_INT_ECC_ERR_1    (1<<7)
+#define NANDFC_INT_ECC_ERR_2    (1<<8)
+#define NANDFC_INT_ECC_CRC_0    (1<<9)
+#define NANDFC_INT_ECC_CRC_1    (1<<10)
+#define NANDFC_INT_ECC_CRC_2    (1<<11)
+#define NANDFC_INT_STAT_IDLE    (1<<21)
+#define NANDFC_INT_ERR_ALL      (0x01EF)  /* CRC bits do not work anymore */
+#define NANDFC_INT_CLR_MASK     (0x0FDE)
+
+typedef enum
+{
+    NAND_TYPE_2K           = 0,   // support 3 byte Row Addresses only
+    NAND_TYPE_4K           = 1,
+    NAND_TYPE_8K           = 2,
+    NAND_TYPE_INVALID      = 0xff
+} NAND_FLASH_TYPE;
+
+typedef enum
+{
+    NAND_ECC_2K24BIT       = 0,   // support 2K nand only
+    NAND_ECC_RESERVE       = 1,
+    NAND_ECC_1K96BIT       = 2,   // 4K use as 3K or 8K use as 6K
+    NAND_ECC_1K64BIT       = 3,   // 8K only, use as 8K, need 7xx spare, leave 1x oob
+    NAND_ECC_1K56BIT       = 4,   // 8K only, use as 8K, need 7xx spare, leave more oob
+    NAND_ECC_1K40BIT       = 5,   // 8K only, use as 8K, need 6xx spare
+    NAND_ECC_1K24BIT       = 6,   // 4K/8K, 4K need 224 spare
+    NAND_ECC_INVALID       = 0xFF,
+} NAND_ECC_TYPE;
+
+#endif /* _REG_NAND_V2_H_ */
+
diff --git a/arch/arm/include/asm/arch-rda/reg_nand_v3.h b/arch/arm/include/asm/arch-rda/reg_nand_v3.h
new file mode 100644
index 0000000000..042c88bf06
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_nand_v3.h
@@ -0,0 +1,151 @@
+#ifndef _REG_NAND_V3_H_
+#define _REG_NAND_V3_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+#define REG_NANDFC_BASE     RDA_NAND_BASE
+
+#define NANDFC_DATA_BUF         (REG_NANDFC_BASE + 0x0000)
+#define NANDFC_OOB_BUF          (REG_NANDFC_BASE + 0x1000)
+
+/* for 8810e, 8820, or later */
+#define NANDFC_REG_DCMD_ADDR    (REG_NANDFC_BASE + 0x3000)
+//#define NANDFC_REG_OP_START     (REG_NANDFC_BASE + 0x3004)
+//#define NANDFC_REG_CMD_PTR      (REG_NANDFC_BASE + 0x3008)
+#define NANDFC_REG_COL_ADDR     (REG_NANDFC_BASE + 0x300c)
+#define NANDFC_REG_CONFIG_A     (REG_NANDFC_BASE + 0x3010)
+#define NANDFC_REG_CONFIG_B     (REG_NANDFC_BASE + 0x3014)
+#define NANDFC_REG_BUF_CTRL     (REG_NANDFC_BASE + 0x3018)
+#define NANDFC_REG_BUSY_FLAG    (REG_NANDFC_BASE + 0x301c)
+#define NANDFC_REG_INT_MASK     (REG_NANDFC_BASE + 0x3020)
+#define NANDFC_REG_INT_STAT     (REG_NANDFC_BASE + 0x3024)
+#define NANDFC_REG_IDCODE_A     (REG_NANDFC_BASE + 0x3028)
+#define NANDFC_REG_IDCODE_B     (REG_NANDFC_BASE + 0x302c)
+//#define NANDFC_REG_DMA_REQ      (REG_NANDFC_BASE + 0x3030)
+//#define NANDFC_REG_CMD_DEF_A    (REG_NANDFC_BASE + 0x3034)
+//#define NANDFC_REG_CMD_DEF_B    (REG_NANDFC_BASE + 0x3038)
+#define NANDFC_REG_OP_STATUS    (REG_NANDFC_BASE + 0x303c)
+#define NANDFC_REG_IDTPYE       (REG_NANDFC_BASE + 0x3040)
+#define NANDFC_REG_TIMING_MODE  (REG_NANDFC_BASE + 0x3048)
+#define NANDFC_REG_SYNC_DELAY  (REG_NANDFC_BASE + 0x304c)
+#define NANDFC_REG_IRBN_COUNT  (REG_NANDFC_BASE + 0x3054)
+#define NANDFC_REG_PAGE_PARA  (REG_NANDFC_BASE + 0x305c)
+#define NANDFC_REG_COMMAND_FIFO (REG_NANDFC_BASE + 0x3070)
+#define NANDFC_REG_COMMAND_EXEC_STATUS (REG_NANDFC_BASE + 0x3074)
+#define NANDFC_REG_COMMAND_STATUS0 (REG_NANDFC_BASE + 0x3078)
+#define NANDFC_REG_COMMAND_STATUS1 (REG_NANDFC_BASE + 0x307c)
+#define NANDFC_REG_SCRAMBLE_START_DATA (REG_NANDFC_BASE + 0x3080)
+#define NANDFC_REG_BRICK_FSM_TIME0 (REG_NANDFC_BASE + 0x3084)
+#define NANDFC_REG_BRICK_FSM_TIME1 (REG_NANDFC_BASE + 0x3088)
+#define NANDFC_REG_BRICK_FSM_TIME2 (REG_NANDFC_BASE + 0x308c)
+#define NANDFC_REG_BRICK_FIFO_WRITE_POINTER (REG_NANDFC_BASE + 0x3090)
+#define NANDFC_REG_BCH_DATA (REG_NANDFC_BASE + 0x3094)
+#define NANDFC_REG_BCH_OOB (REG_NANDFC_BASE + 0x3098)
+#define NANDFC_REG_MESSAGE_OOB_SIZE (REG_NANDFC_BASE + 0x309c)
+
+// NANDFC_REG_DCMD_ADDR
+#define NANDFC_DCMD(n)          (((n)&0xFF)<<24)
+#define NANDFC_PAGE_ADDR(n)     (((n)&0x00FFFFFF)<<0)
+
+// NANDFC_REG_CONFIG_A
+#define NANDFC_CYCLE(n)         ((((n)&0x0F)<<0) | ((((n) >> 4)&0x1)<<30))
+#define NANDFC_CHIP_SEL(n)      (((n)&0x0F)<<4)
+#define NANDFC_TIMING(n)        (((n)&0xFF)<<8)
+#define NANDFC_POLARITY_IO(n)   (((n)&0x01)<<16)
+#define NANDFC_POLARITY_MEM(n)  (((n)&0x01)<<17)
+#define NANDFC_CMDFULL_STA(n) (((n)&0x01)<<31)
+#define NANDFC_BRICK_COMMAND(n) (((n)&0x01)<<25)
+#define NANDFC_WDITH_16BIT(n)   (((n)&0x01)<<18)
+#define NANDFC_SCRAMBLE_ENABLE(n)   (((n)&0x01)<<24)
+
+//NNADFC_REG_BCH_DATA
+#define NANDFC_BCH_KK_DATA(n) (((n)&0x1FFF) << 0)
+#define NANDFC_BCH_NN_DATA(n) (((n)&0x1FFF) << 16)
+
+//NNADFC_REG_BCH_DATA
+#define NANDFC_BCH_KK_OOB(n) (((n)&0x1FFF) << 0)
+#define NANDFC_BCH_NN_OOB(n) (((n)&0x1FFF) << 16)
+
+//NNADFC_REG_MESSAGE_OOB_SIZE
+#define NANDFC_OOB_SIZE(n) (((n)&0xFFF) << 0)
+#define NANDFC_MESSAGE_SIZE(n) (((n)&0x3FFF) << 16)
+
+//NANDFC_REG_BRICK_FIFO_WRITE_POINTER
+#define NANDFC_BRICK_DATA(n) (((n)&0xFF) << 24)
+#define NANDFC_BRICK_R_WIDTH(n) (((n)&0x1) << 18)
+#define NANDFC_BRICK_W_WIDTH(n) (((n)&0x1) << 19)
+#define NANDFC_BRICK_DATA_NUM(n) (((n)&0x3FFF) << 4)
+#define NANDFC_BRICK_NEXT_ACT(n) (((n)&0xF) << 0)
+
+typedef enum
+{
+    NAND_ECC_24BIT           = 0,
+    NAND_ECC_96BIT_WITHOUT_CRC  = 1,
+    NAND_ECC_96BIT_WITH_CRC             = 2,
+    NAND_ECC_64BIT           = 3,
+    NAND_ECC_56BIT           = 4,
+    NAND_ECC_40BIT           = 5,
+    NAND_ECC_24BIT_1       = 6,
+    NAND_ECC_48BIT           = 7,
+    NAND_ECC_32BIT           = 8,
+    NAND_ECC_16BIT           = 9,
+    NAND_ECC_8BIT             = 10,
+    NAND_ECC_72BIT           = 11,
+    NAND_ECC_80BIT           = 12,
+    NAND_ECC_88BIT           = 13,
+} NAND_BCHMODE_TYPE;
+
+#define NANDFC_SCRAMBLE(n)         (((n)&0x01)<<24)
+
+// NANDFC_REG_CONFIG_B
+#define NANDFC_HWECC(n)         (((n)&0x01)<<7)
+#define NANDFC_ECC_MODE(n)      (((n)&0x0f)<<0)
+
+// NANDFC_REG_BUF_CTRL
+#define NANDFC_BUF_DIRECT(n)    (((n)&0x01)<<2)
+
+// NANDFC_REG_INT_STAT
+#define NANDFC_INT_ECC_ERR      (1<<0)
+#define NANDFC_INT_PROG_ERR     (1<<1)
+#define NANDFC_INT_ERASE_ERR    (1<<2)
+#define NANDFC_INT_TIMEOUT      (1<<3)
+#define NANDFC_INT_DONE         (1<<4)
+#define NANDFC_INT_CRC_FAIL     (1<<5)
+#define NANDFC_INT_COMMAND_FIFO_EMPTY  (1<<6)
+#define NANDFC_INT_ECC_ERR_0    (1<<7)
+#define NANDFC_INT_ECC_ERR_1    (1<<8)
+#define NANDFC_INT_ECC_ERR_1    (1<<8)
+#define NANDFC_INT_ECC_ERR_2    (1<<10)
+#define NANDFC_INT_ECC_ERR_3    (1<<10)
+#define NANDFC_INT_ECC_ERR_4    (1<<11)
+#define NANDFC_INT_ECC_ERR_5    (1<<12)
+#define NANDFC_INT_ECC_ERR_6    (1<<13)
+#define NANDFC_INT_ECC_ERR_7    (1<<14)
+#define NANDFC_INT_ECC_CRC_0    (1<<15)
+#define NANDFC_INT_ECC_CRC_1    (1<<16)
+#define NANDFC_INT_ECC_CRC_2    (1<<17)
+#define NANDFC_INT_ECC_CRC_3    (1<<18)
+#define NANDFC_INT_ECC_CRC_4    (1<<19)
+#define NANDFC_INT_ECC_CRC_5    (1<<20)
+#define NANDFC_INT_ECC_CRC_6    (1<<21)
+#define NANDFC_COMMAND_FIFO_OVERFLOW (1 << 22)
+#define NANDFC_INT_ERR_ALL      (0x3FFF87)
+#define NANDFC_INT_CLR_MASK     (0x3FFF9F)
+
+typedef enum
+{
+    NAND_TYPE_4K           = 0,
+    NAND_TYPE_2K           = 1,
+    NAND_TYPE_8K           = 2,
+    NAND_TYPE_16K          = 3,
+    NAND_TYPE_3K           = 4,
+    NAND_TYPE_7K           = 5,
+    NAND_TYPE_14K          = 6
+} NAND_FLASH_TYPE;
+
+//NANDFC_REG_PAGE_PARA
+#define NANDFC_PAGE_SIZE(n)         (((n)&0x07FFF)<<16)
+#define NANDFC_PACKAGE_NUM(n)      (((n)&0x0F)<<0)
+#endif /* _REG_NAND_V3_H_ */
+
diff --git a/arch/arm/include/asm/arch-rda/reg_rf_spi.h b/arch/arm/include/asm/arch-rda/reg_rf_spi.h
new file mode 100644
index 0000000000..ac7b35bdf6
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_rf_spi.h
@@ -0,0 +1,152 @@
+#ifndef _RF_SPI_H_
+#define _RF_SPI_H_
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+#define SPI_TX_FIFO_SIZE                         (16)
+#define SPI_RX_FIFO_SIZE                         (16)
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+// ============================================================================
+// SPI_T
+// -----------------------------------------------------------------------------
+///
+// =============================================================================
+
+typedef volatile struct
+{
+    REG32                          Ctrl;                         //0x00000000
+    REG32                          Status;                       //0x00000004
+    REG32                          Rx_Data;                      //0x00000008
+    REG32                          Command;                      //0x0000000C
+    REG32                          Cmd_Size;                     //0x00000010
+    REG32                          Cmd_Data;                     //0x00000014
+    REG32                          Gain_Size;                    //0x00000018
+    REG32                          Gain_Data;                    //0x0000001C
+    REG32                          IRQ;                          //0x00000020
+    REG32                          IRQ_Mask;                     //0x00000024
+    REG32                          IRQ_Threshold;                //0x00000028
+    REG32                          Divider;                      //0x0000002C
+} HWP_RF_SPI_T;
+
+#define hwp_rfSpi                  ((HWP_RF_SPI_T*) (RDA_CFG_RF_SPI_BASE))
+
+//Ctrl
+#define RF_SPI_ENABLE              (1<<0)
+#define RF_SPI_CS_POLARITY         (1<<1)
+#define RF_SPI_DIGRF_READ          (1<<2)
+#define RF_SPI_CLOCKED_BACK2BACK   (1<<3)
+#define RF_SPI_INPUT_MODE          (1<<4)
+#define RF_SPI_CLOCK_POLARITY      (1<<5)
+#define RF_SPI_CLOCK_DELAY(n)      (((n)&3)<<6)
+#define RF_SPI_DO_DELAY(n)         (((n)&3)<<8)
+#define RF_SPI_DI_DELAY(n)         (((n)&3)<<10)
+#define RF_SPI_CS_DELAY(n)         (((n)&3)<<12)
+#define RF_SPI_CS_END_HOLD(n)      (((n)&3)<<14)
+#define RF_SPI_FRAME_SIZE(n)       (((n)&31)<<16)
+#define RF_SPI_FRAME_SIZE_MASK     (31<<16)
+#define RF_SPI_FRAME_SIZE_SHIFT    (16)
+#define RF_SPI_CS_END_PULSE(n)     (((n)&3)<<22)
+#define RF_SPI_INPUT_FRAME_SIZE(n) (((n)&31)<<24)
+#define RF_SPI_INPUT_FRAME_SIZE_MASK (31<<24)
+#define RF_SPI_INPUT_FRAME_SIZE_SHIFT (24)
+#define RF_SPI_TURNAROUND_TIME(n)  (((n)&3)<<30)
+
+//Status
+#define RF_SPI_ACTIVE_STATUS       (1<<0)
+#define RF_SPI_ERROR_CMD           (1<<1)
+#define RF_SPI_TABLE_OVF           (1<<6)
+#define RF_SPI_TABLE_UDF           (1<<7)
+#define RF_SPI_CMD_LEVEL(n)        (((n)&0x3F)<<8)
+#define RF_SPI_CMD_LEVEL_MASK      (0x3F<<8)
+#define RF_SPI_CMD_LEVEL_SHIFT     (8)
+#define RF_SPI_CMD_OVF             (1<<14)
+#define RF_SPI_CMD_UDF             (1<<15)
+#define RF_SPI_CMD_DATA_LEVEL(n)   (((n)&0x1FF)<<16)
+#define RF_SPI_CMD_DATA_LEVEL_MASK (0x1FF<<16)
+#define RF_SPI_CMD_DATA_LEVEL_SHIFT (16)
+#define RF_SPI_CMD_DATA_OVF        (1<<25)
+#define RF_SPI_CMD_DATA_UDF        (1<<26)
+#define RF_SPI_RX_LEVEL(n)         (((n)&7)<<27)
+#define RF_SPI_RX_LEVEL_MASK       (7<<27)
+#define RF_SPI_RX_LEVEL_SHIFT      (27)
+#define RF_SPI_RX_OVF              (1<<30)
+#define RF_SPI_RX_UDF              (1<<31)
+
+//Rx_Data
+#define RF_SPI_RX_DATA(n)          (((n)&0xFF)<<0)
+
+//Command
+#define RF_SPI_SEND_CMD            (1<<0)
+#define RF_SPI_FLUSH_CMD_FIFO      (1<<8)
+#define RF_SPI_FLUSH_RX_FIFO       (1<<16)
+#define RF_SPI_RESTART_GAIN        (1<<24)
+#define RF_SPI_RELOAD_GAIN         (1<<28)
+#define RF_SPI_DRIVE_ZERO          (1<<31)
+
+//Cmd_Size
+#define RF_SPI_CMD_SIZE(n)         (((n)&0xFF)<<0)
+#define RF_SPI_CMD_MARK            (1<<31)
+
+//Cmd_Data
+#define RF_SPI_CMD_DATA(n)         (((n)&0xFF)<<0)
+
+//Gain_Size
+#define RF_SPI_GAIN_SIZE(n)        (((n)&15)<<0)
+
+//Gain_Data
+#define RF_SPI_GAIN_DATA(n)        (((n)&0xFF)<<0)
+
+//IRQ
+#define RF_SPI_CMD_DATA_DMA_DONE_CAUSE (1<<0)
+#define RF_SPI_CMD_FIFO_EMPTY_CAUSE (1<<2)
+#define RF_SPI_CMD_THRESHOLD_CAUSE (1<<3)
+#define RF_SPI_RX_FIFO_FULL_CAUSE  (1<<4)
+#define RF_SPI_RX_THRESHOLD_CAUSE  (1<<5)
+#define RF_SPI_ERROR_CAUSE         (1<<6)
+#define RF_SPI_CMD_DATA_DMA_DONE_STATUS (1<<16)
+#define RF_SPI_CMD_FIFO_EMPTY_STATUS (1<<18)
+#define RF_SPI_CMD_THRESHOLD_STATUS (1<<19)
+#define RF_SPI_RX_FIFO_FULL_STATUS (1<<20)
+#define RF_SPI_RX_THRESHOLD_STATUS (1<<21)
+#define RF_SPI_ERROR_STATUS        (1<<22)
+#define RF_SPI_ALL_CAUSE(n)        (((n)&0x7D)<<0)
+#define RF_SPI_ALL_CAUSE_MASK      (0x7D<<0)
+#define RF_SPI_ALL_CAUSE_SHIFT     (0)
+#define RF_SPI_ALL_STATUS(n)       (((n)&0x7D)<<16)
+#define RF_SPI_ALL_STATUS_MASK     (0x7D<<16)
+#define RF_SPI_ALL_STATUS_SHIFT    (16)
+
+//IRQ_Mask
+#define RF_SPI_CMD_DATA_DMA_DONE_MASK (1<<0)
+#define RF_SPI_CMD_FIFO_EMPTY_MASK (1<<2)
+#define RF_SPI_CMD_THRESHOLD_MASK  (1<<3)
+#define RF_SPI_RX_FIFO_FULL_MASK   (1<<4)
+#define RF_SPI_RX_THRESHOLD_MASK   (1<<5)
+#define RF_SPI_ERROR_MASK          (1<<6)
+#define RF_SPI_ALL_MASK(n)         (((n)&0x7D)<<0)
+#define RF_SPI_ALL_MASK_MASK       (0x7D<<0)
+#define RF_SPI_ALL_MASK_SHIFT      (0)
+
+//IRQ_Threshold
+#define RF_SPI_CMD_THRESHOLD(n)    (((n)&0x3F)<<8)
+#define RF_SPI_RX_THRESHOLD(n)     (((n)&3)<<24)
+
+//Divider
+#define RF_SPI_DIVIDER(n)          (((n)&0x3F)<<1)
+#define RF_SPI_DIVIDER_MASK        (0x3F<<1)
+#define RF_SPI_DIVIDER_SHIFT       (1)
+#define RF_SPI_CLOCK_LIMITER       (1<<28)
+#define RF_SPI_CLOCK_LIMITER_MASK  (1<<28)
+#define RF_SPI_CLOCK_LIMITER_SHIFT (28)
+
+
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/reg_spi.h b/arch/arm/include/asm/arch-rda/reg_spi.h
new file mode 100644
index 0000000000..8664bc2215
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_spi.h
@@ -0,0 +1,245 @@
+#ifndef _SPI_H_
+#define _SPI_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+#define SPI_TX_FIFO_SIZE                         (16)
+#define SPI_RX_FIFO_SIZE                         (16)
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+// ============================================================================
+// SPI_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+
+typedef volatile struct
+{
+    REG32                          ctrl;                         //0x00000000
+    REG32                          status;                       //0x00000004
+    /// Spi1 fifo size (rxtx_buffer): 8bits.
+    ///  Spi2 fifo size (rxtx_buffer): 8bits.
+    ///  Spi3 fifo size (rxtx_buffer): 32bits.
+    ///  <table border="1"> <!-- border should be in css--> <caption> <big>32b FIFO
+    /// only </big> </caption> <tr> <th>rxtx_buffer: </th> <th>Range [31]</th> <th>Range
+    /// [30:29]</th> <th>Range [28:26]</th> <th>Range [25]</th> <th>Range [24:16]</th>
+    /// <th>Range [15:0]</th> </tr> <tr> <td>DATA_IN: </td> <td>READ_ENA</td> <td>CS</td>
+    /// <td/> <td>R/W</td> <td>ADDRESS</td> <td>DATA</td> </tr> <tr> <td>DATA_OUT:
+    /// </td> <td>READ_ENA</td> <td>CS</td> <td/> <td>R/W</td> <td>ADDRESS</td> <td>DATA</td>
+    /// </tr> </table>
+    REG32                          rxtx_buffer;                  //0x00000008
+    REG32                          cfg;                          //0x0000000C
+    REG32                          pattern;                      //0x00000010
+    REG32                          stream;                       //0x00000014
+    REG32                          pin_control;                  //0x00000018
+    REG32                          irq;                          //0x0000001C
+} HWP_SPI_T;
+
+#define hwp_spi1			((HWP_SPI_T*) (RDA_SPI1_BASE))
+#define hwp_spi2			((HWP_SPI_T*) (RDA_SPI2_BASE))
+#define hwp_spi3			((HWP_SPI_T*) (RDA_SPI3_BASE))
+#define hwp_mspi2			((HWP_SPI_T*) (RDA_MODEM_SPI2_BASE))
+
+//ctrl
+#define SPI_ENABLE                  (1<<0)
+#define SPI_CS_SEL(n)               (((n)&3)<<1)
+#define SPI_CS_SEL_MASK             (3<<1)
+#define SPI_CS_SEL_SHIFT            (1)
+#define SPI_CS_SEL_CS0              (0<<1)
+#define SPI_CS_SEL_CS1              (1<<1)
+#define SPI_CS_SEL_CS2              (2<<1)
+#define SPI_CS_SEL_CS3              (3<<1)
+#define SPI_INPUT_MODE              (1<<4)
+#define SPI_CLOCK_POLARITY          (1<<5)
+#define SPI_CLOCK_DELAY(n)          (((n)&3)<<6)
+#define SPI_DO_DELAY(n)             (((n)&3)<<8)
+#define SPI_DI_DELAY(n)             (((n)&3)<<10)
+#define SPI_CS_DELAY(n)             (((n)&3)<<12)
+#define SPI_CS_PULSE(n)             (((n)&3)<<14)
+#define SPI_FRAME_SIZE(n)           (((n)&31)<<16)
+#define SPI_TX_SW_SHIFT             (1<<21)
+#define SPI_OE_DELAY(n)             (((n)&31)<<24)
+#define SPI_CTRL_DATA_MUX_SEL       (1<<29)
+#define SPI_CTRL_DATA_MUX_SEL_MASK  (1<<29)
+#define SPI_CTRL_DATA_MUX_SEL_SHIFT (29)
+#define SPI_CTRL_DATA_MUX_SEL_CTRL_REG_SEL (0<<29)
+#define SPI_CTRL_DATA_MUX_SEL_DATA_REG_SEL (1<<29)
+#define SPI_INPUT_SEL(n)            (((n)&3)<<30)
+
+//status
+#define SPI_ACTIVE_STATUS           (1<<0)
+#define SPI_CAUSE_RX_OVF_IRQ        (1<<3)
+#define SPI_CAUSE_TX_TH_IRQ         (1<<4)
+#define SPI_CAUSE_TX_DMA_IRQ        (1<<5)
+#define SPI_CAUSE_RX_TH_IRQ         (1<<6)
+#define SPI_CAUSE_RX_DMA_IRQ        (1<<7)
+#define SPI_TX_OVF                  (1<<9)
+#define SPI_RX_UDF                  (1<<10)
+#define SPI_RX_OVF                  (1<<11)
+#define SPI_TX_TH                   (1<<12)
+#define SPI_TX_DMA_DONE             (1<<13)
+#define SPI_RX_TH                   (1<<14)
+#define SPI_RX_DMA_DONE             (1<<15)
+#define SPI_TX_SPACE(n)             (((n)&31)<<16)
+#define SPI_TX_SPACE_MASK           (31<<16)
+#define SPI_TX_SPACE_SHIFT          (16)
+#define SPI_RX_LEVEL(n)             (((n)&31)<<24)
+#define SPI_RX_LEVEL_MASK           (31<<24)
+#define SPI_RX_LEVEL_SHIFT          (24)
+#define SPI_FIFO_FLUSH              (1<<30)
+#define SPI_IRQ_CAUSE(n)            (((n)&31)<<3)
+#define SPI_IRQ_CAUSE_MASK          (31<<3)
+#define SPI_IRQ_CAUSE_SHIFT         (3)
+
+//rxtx_buffer
+#define SPI_DATA_IN(n)              (((n)&0xFFFFFFFF)<<0)
+#define SPI_DATA_OUT(n)             (((n)&0xFFFFFFFF)<<0)
+#define SPI_CS(n)                   (((n)&3)<<29)
+#define SPI_CS_MASK                 (3<<29)
+#define SPI_CS_SHIFT                (29)
+#define SPI_READ_ENA                (1<<31)
+#define SPI_READ_ENA_MASK           (1<<31)
+#define SPI_READ_ENA_SHIFT          (31)
+
+//cfg
+#define SPI_CS_POLARITY_0           (1<<0)
+#define SPI_CS_POLARITY_0_MASK      (1<<0)
+#define SPI_CS_POLARITY_0_SHIFT     (0)
+#define SPI_CS_POLARITY_0_ACTIVE_HIGH (0<<0)
+#define SPI_CS_POLARITY_0_ACTIVE_LOW (1<<0)
+#define SPI_CS_POLARITY_1           (1<<1)
+#define SPI_CS_POLARITY_1_MASK      (1<<1)
+#define SPI_CS_POLARITY_1_SHIFT     (1)
+#define SPI_CS_POLARITY_1_ACTIVE_HIGH (0<<1)
+#define SPI_CS_POLARITY_1_ACTIVE_LOW (1<<1)
+#define SPI_CS_POLARITY_2           (1<<2)
+#define SPI_CS_POLARITY_2_MASK      (1<<2)
+#define SPI_CS_POLARITY_2_SHIFT     (2)
+#define SPI_CS_POLARITY_2_ACTIVE_HIGH (0<<2)
+#define SPI_CS_POLARITY_2_ACTIVE_LOW (1<<2)
+#define SPI_CS_POLARITY_3           (1<<3)
+#define SPI_CS_POLARITY_3_MASK      (1<<3)
+#define SPI_CS_POLARITY_3_SHIFT     (3)
+#define SPI_CS_POLARITY_3_ACTIVE_HIGH (0<<3)
+#define SPI_CS_POLARITY_3_ACTIVE_LOW (1<<3)
+#define SPI_CLOCK_DIVIDER(n)        (((n)&0x3FF)<<16)
+#define SPI_CLOCK_DIVIDER_MASK      (0x3FF<<16)
+#define SPI_CLOCK_DIVIDER_SHIFT     (16)
+#define SPI_CLOCK_LIMITER           (1<<28)
+#define SPI_CLOCK_LIMITER_MASK      (1<<28)
+#define SPI_CLOCK_LIMITER_SHIFT     (28)
+#define SPI_CS_POLARITY(n)          (((n)&15)<<0)
+#define SPI_CS_POLARITY_MASK        (15<<0)
+#define SPI_CS_POLARITY_SHIFT       (0)
+
+//pattern
+#define SPI_PATTERN(n)              (((n)&0xFF)<<0)
+#define SPI_PATTERN_MODE            (1<<8)
+#define SPI_PATTERN_MODE_MASK       (1<<8)
+#define SPI_PATTERN_MODE_SHIFT      (8)
+#define SPI_PATTERN_MODE_DISABLED   (0<<8)
+#define SPI_PATTERN_MODE_ENABLED    (1<<8)
+#define SPI_PATTERN_SELECTOR        (1<<9)
+#define SPI_PATTERN_SELECTOR_MASK   (1<<9)
+#define SPI_PATTERN_SELECTOR_SHIFT  (9)
+#define SPI_PATTERN_SELECTOR_UNTIL  (0<<9)
+#define SPI_PATTERN_SELECTOR_WHILE  (1<<9)
+
+//stream
+#define SPI_TX_STREAM_BIT           (1<<0)
+#define SPI_TX_STREAM_BIT_MASK      (1<<0)
+#define SPI_TX_STREAM_BIT_SHIFT     (0)
+#define SPI_TX_STREAM_BIT_ZERO      (0<<0)
+#define SPI_TX_STREAM_BIT_ONE       (1<<0)
+#define SPI_TX_STREAM_MODE          (1<<8)
+#define SPI_TX_STREAM_MODE_MASK     (1<<8)
+#define SPI_TX_STREAM_MODE_SHIFT    (8)
+#define SPI_TX_STREAM_MODE_DISABLED (0<<8)
+#define SPI_TX_STREAM_MODE_ENABLED  (1<<8)
+#define SPI_TX_STREAM_STOP_WITH_RX_DMA_DONE (1<<16)
+#define SPI_TX_STREAM_STOP_WITH_RX_DMA_DONE_MASK (1<<16)
+#define SPI_TX_STREAM_STOP_WITH_RX_DMA_DONE_SHIFT (16)
+#define SPI_TX_STREAM_STOP_WITH_RX_DMA_DONE_DISABLED (0<<16)
+#define SPI_TX_STREAM_STOP_WITH_RX_DMA_DONE_ENABLED (1<<16)
+
+//pin_control
+#define SPI_CLK_CTRL(n)             (((n)&3)<<0)
+#define SPI_CLK_CTRL_MASK           (3<<0)
+#define SPI_CLK_CTRL_SHIFT          (0)
+#define SPI_CLK_CTRL_SPI_CTRL       (0<<0)
+#define SPI_CLK_CTRL_INPUT_CTRL     (1<<0)
+#define SPI_CLK_CTRL_FORCE_0_CTRL   (2<<0)
+#define SPI_CLK_CTRL_FORCE_1_CTRL   (3<<0)
+#define SPI_DO_CTRL(n)              (((n)&3)<<2)
+#define SPI_DO_CTRL_MASK            (3<<2)
+#define SPI_DO_CTRL_SHIFT           (2)
+#define SPI_DO_CTRL_SPI_CTRL        (0<<2)
+#define SPI_DO_CTRL_INPUT_CTRL      (1<<2)
+#define SPI_DO_CTRL_FORCE_0_CTRL    (2<<2)
+#define SPI_DO_CTRL_FORCE_1_CTRL    (3<<2)
+#define SPI_CS0_CTRL(n)             (((n)&3)<<4)
+#define SPI_CS0_CTRL_MASK           (3<<4)
+#define SPI_CS0_CTRL_SHIFT          (4)
+#define SPI_CS0_CTRL_SPI_CTRL       (0<<4)
+#define SPI_CS0_CTRL_INPUT_CTRL     (1<<4)
+#define SPI_CS0_CTRL_FORCE_0_CTRL   (2<<4)
+#define SPI_CS0_CTRL_FORCE_1_CTRL   (3<<4)
+#define SPI_CS1_CTRL(n)             (((n)&3)<<6)
+#define SPI_CS1_CTRL_MASK           (3<<6)
+#define SPI_CS1_CTRL_SHIFT          (6)
+#define SPI_CS1_CTRL_SPI_CTRL       (0<<6)
+#define SPI_CS1_CTRL_INPUT_CTRL     (1<<6)
+#define SPI_CS1_CTRL_FORCE_0_CTRL   (2<<6)
+#define SPI_CS1_CTRL_FORCE_1_CTRL   (3<<6)
+#define SPI_CS2_CTRL(n)             (((n)&3)<<8)
+#define SPI_CS2_CTRL_MASK           (3<<8)
+#define SPI_CS2_CTRL_SHIFT          (8)
+#define SPI_CS2_CTRL_SPI_CTRL       (0<<8)
+#define SPI_CS2_CTRL_INPUT_CTRL     (1<<8)
+#define SPI_CS2_CTRL_FORCE_0_CTRL   (2<<8)
+#define SPI_CS2_CTRL_FORCE_1_CTRL   (3<<8)
+#define SPI_CS3_CTRL(n)             (((n)&3)<<10)
+#define SPI_CS3_CTRL_MASK           (3<<10)
+#define SPI_CS3_CTRL_SHIFT          (10)
+#define SPI_CS3_CTRL_SPI_CTRL       (0<<10)
+#define SPI_CS3_CTRL_INPUT_CTRL     (1<<10)
+#define SPI_CS3_CTRL_FORCE_0_CTRL   (2<<10)
+#define SPI_CS3_CTRL_FORCE_1_CTRL   (3<<10)
+
+//irq
+#define SPI_MASK_RX_OVF_IRQ         (1<<0)
+#define SPI_MASK_TX_TH_IRQ          (1<<1)
+#define SPI_MASK_TX_DMA_IRQ         (1<<2)
+#define SPI_MASK_RX_TH_IRQ          (1<<3)
+#define SPI_MASK_RX_DMA_IRQ         (1<<4)
+#define SPI_TX_THRESHOLD(n)         (((n)&3)<<5)
+#define SPI_TX_THRESHOLD_MASK       (3<<5)
+#define SPI_TX_THRESHOLD_SHIFT      (5)
+#define SPI_TX_THRESHOLD_1_EMPTY_SLOT (0<<5)
+#define SPI_TX_THRESHOLD_4_EMPTY_SLOTS (1<<5)
+#define SPI_TX_THRESHOLD_8_EMPTY_SLOTS (2<<5)
+#define SPI_TX_THRESHOLD_12_EMPTY_SLOTS (3<<5)
+#define SPI_RX_THRESHOLD(n)         (((n)&3)<<7)
+#define SPI_RX_THRESHOLD_MASK       (3<<7)
+#define SPI_RX_THRESHOLD_SHIFT      (7)
+#define SPI_RX_THRESHOLD_1_VALID_DATA (0<<7)
+#define SPI_RX_THRESHOLD_4_VALID_DATA (1<<7)
+#define SPI_RX_THRESHOLD_8_VALID_DATA (2<<7)
+#define SPI_RX_THRESHOLD_12_VALID_DATA (3<<7)
+#define SPI_IRQ_MASK(n)             (((n)&31)<<0)
+#define SPI_IRQ_MASK_MASK           (31<<0)
+#define SPI_IRQ_MASK_SHIFT          (0)
+
+
+
+
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/reg_sysctrl.h b/arch/arm/include/asm/arch-rda/reg_sysctrl.h
new file mode 100644
index 0000000000..f4678e51eb
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_sysctrl.h
@@ -0,0 +1,15 @@
+#ifdef CONFIG_MACH_RDA8810
+#include "reg_sysctrl_rda8810.h"
+#elif defined(CONFIG_MACH_RDA8810E)
+#include "reg_sysctrl_rda8810e.h"
+#elif defined(CONFIG_MACH_RDA8820)
+#include "reg_sysctrl_rda8820.h"
+#elif defined(CONFIG_MACH_RDA8850)
+#include "reg_sysctrl_rda8850.h"
+#elif defined(CONFIG_MACH_RDA8850E)
+#include "reg_sysctrl_rda8850e.h"
+#elif defined(CONFIG_MACH_RDA8810H)
+#include "reg_sysctrl_rda8810h.h"
+#else
+#error "unknown MACH"
+#endif
diff --git a/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8810.h b/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8810.h
new file mode 100644
index 0000000000..a0a7181a54
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8810.h
@@ -0,0 +1,1471 @@
+#ifndef _REG_SYSCTRL_H_
+#define _REG_SYSCTRL_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+
+// ============================================================================
+// AP_CPU_ID_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// CPU IDs
+    CPU0                                        = 0x00000000,
+    CPU1                                        = 0x00000001
+} AP_CPU_ID_T;
+
+
+// ============================================================================
+// CPU_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP CPU side System clocks
+    CPU_CORE                                    = 0x00000000,
+/// the following don't have an auto enable
+    CPU_DUMMY                                   = 0x00000001
+} CPU_CLKS_T;
+
+#define NB_CPU_CLK_AEN                           (1)
+#define NB_CPU_CLK_EN                            (2)
+#define NB_CPU_CLK                               (2)
+
+// ============================================================================
+// AXI_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AXI side System clocks: AXI and AHB0 and APB0
+    AHB0_CONF                                   = 0x00000000,
+    APB0_CONF                                   = 0x00000001,
+    AXI_VOC                                     = 0x00000002,
+    AXI_DMA                                     = 0x00000003,
+/// the following don't have an auto enable
+    AXI_ALWAYS                                  = 0x00000004,
+    AXI_CONNECT                                 = 0x00000005,
+    APB0_IRQ                                    = 0x00000006
+} AXI_CLKS_T;
+
+#define NB_AXI_CLK_AEN                           (4)
+#define NB_AXI_CLK_EN                            (7)
+#define NB_AXI_CLK                               (7)
+
+// ============================================================================
+// AXIDIV2_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AXIdiv2 side System clocks
+    AXIDIV2_IMEM                                = 0x00000000,
+/// the following don't have an auto enable
+    AXIDIV2_ALWAYS                              = 0x00000001,
+    AXIDIV2_CONNECT                             = 0x00000002,
+    AXIDIV2_VPU                                 = 0x00000003
+} AXIDIV2_CLKS_T;
+
+#define NB_AXIDIV2_CLK_AEN                       (1)
+#define NB_AXIDIV2_CLK_EN                        (4)
+#define NB_AXIDIV2_CLK                           (4)
+
+// ============================================================================
+// GCG_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP GCG side System clocks
+    GCG_APB_CONF                                = 0x00000000,
+    GCG_GOUDA                                   = 0x00000001,
+    GCG_CAMERA                                  = 0x00000002,
+/// the following don't have an auto enable
+    GCG_ALWAYS                                  = 0x00000003,
+    GCG_CONNECT                                 = 0x00000004
+} GCG_CLKS_T;
+
+#define NB_GCG_CLK_AEN                           (3)
+#define NB_GCG_CLK_EN                            (5)
+#define NB_GCG_CLK                               (5)
+
+// ============================================================================
+// AHB1_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AHB1 side System clocks
+    AHB1_USBC                                   = 0x00000000,
+/// the following don't have an auto enable
+    AHB1_ALWAYS                                 = 0x00000001,
+    AHB1_SPIFLASH                               = 0x00000002
+} AHB1_CLKS_T;
+
+#define NB_AHB1_CLK_AEN                          (1)
+#define NB_AHB1_CLK_EN                           (3)
+#define NB_AHB1_CLK                              (3)
+
+// ============================================================================
+// APB1_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP APB1 side System clocks
+    APB1_CONF                                   = 0x00000000,
+    APB1_AIF                                    = 0x00000001,
+    APB1_AUIFC                                  = 0x00000002,
+    APB1_AUIFC_CH0                              = 0x00000003,
+    APB1_AUIFC_CH1                              = 0x00000004,
+    APB1_I2C1                                   = 0x00000005,
+    APB1_I2C2                                   = 0x00000006,
+    APB1_I2C3                                   = 0x00000007,
+/// AP APB1 side divided clock (either divided by module or by clock_ctrl)
+    APB1D_OSC                                   = 0x00000008,
+    APB1D_PWM                                   = 0x00000009,
+/// the following don't have an auto enable
+    APB1_ALWAYS                                 = 0x0000000A,
+    APB1_DAPLITE                                = 0x0000000B,
+    APB1_TIMER                                  = 0x0000000C,
+    APB1_GPIO                                   = 0x0000000D
+} APB1_CLKS_T;
+
+#define NB_APB1_CLK_AEN                          (10)
+#define NB_APB1_CLK_EN                           (14)
+#define NB_APB1_CLK                              (14)
+
+// ============================================================================
+// APB2_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP APB2 side System clocks
+    APB2_CONF                                   = 0x00000000,
+    APB2_IFC                                    = 0x00000001,
+    APB2_IFC_CH0                                = 0x00000002,
+    APB2_IFC_CH1                                = 0x00000003,
+    APB2_IFC_CH2                                = 0x00000004,
+    APB2_IFC_CH3                                = 0x00000005,
+    APB2_IFC_CH4                                = 0x00000006,
+    APB2_IFC_CH5                                = 0x00000007,
+    APB2_IFC_CH6                                = 0x00000008,
+    APB2_IFC_CH7                                = 0x00000009,
+    APB2_UART1                                  = 0x0000000A,
+    APB2_UART2                                  = 0x0000000B,
+    APB2_UART3                                  = 0x0000000C,
+    APB2_SPI1                                   = 0x0000000D,
+    APB2_SPI2                                   = 0x0000000E,
+    APB2_SPI3                                   = 0x0000000F,
+    APB2_SDMMC1                                 = 0x00000010,
+    APB2_SDMMC2                                 = 0x00000011,
+    APB2_SDMMC3                                 = 0x00000012,
+/// the following don't have an auto enable
+    APB2_ALWAYS                                 = 0x00000013,
+    APB2_NANDFLASH                              = 0x00000014
+} APB2_CLKS_T;
+
+#define NB_APB2_CLK_AEN                          (19)
+#define NB_APB2_CLK_EN                           (21)
+#define NB_APB2_CLK                              (21)
+
+// ============================================================================
+// MEM_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP MEM side System clocks
+    MEM_CONF                                    = 0x00000000,
+/// the following don't have an auto enable
+    MEM_DMC                                     = 0x00000001,
+    MEM_GPU                                     = 0x00000002,
+    MEM_VPU                                     = 0x00000003,
+    MEM_DDRPHY_P                                = 0x00000004,
+    MEM_CONNECT                                 = 0x00000005
+} MEM_CLKS_T;
+
+#define NB_MEM_CLK_AEN                           (1)
+#define NB_MEM_CLK_EN                            (6)
+#define NB_MEM_CLK                               (6)
+
+// ============================================================================
+// APO_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP side Other clocks
+/// clocks with auto enble
+    APOC_VPU                                    = 0x00000000,
+    APOC_BCK                                    = 0x00000001,
+    APOC_UART1                                  = 0x00000002,
+    APOC_UART2                                  = 0x00000003,
+    APOC_UART3                                  = 0x00000004,
+    APOC_VOC_CORE                               = 0x00000005,
+    APOC_VOC                                    = 0x00000006,
+/// the following don't have an auto enable
+    APOC_VOC_ALWAYS                             = 0x00000007,
+    APOC_DDRPHY_N                               = 0x00000008,
+    APOC_DDRPHY2XP                              = 0x00000009,
+    APOC_DDRPHY2XN                              = 0x0000000A,
+    APOC_GPU                                    = 0x0000000B,
+    APOC_USBPHY                                 = 0x0000000C,
+    APOC_CSI                                    = 0x0000000D,
+    APOC_DSI                                    = 0x0000000E,
+    APOC_GPIO                                   = 0x0000000F,
+    APOC_SPIFLASH                               = 0x00000010,
+    APOC_PIX                                    = 0x00000011,
+    APOC_PDGB                                   = 0x00000012
+} APO_CLKS_T;
+
+#define NB_CLK_VOC_AEN_SYNC                      (5)
+#define NB_CLK_VOC_CORE                          (6)
+#define NB_APO_CLK_AEN                           (7)
+#define NB_CLK_VOC_END                           (8)
+#define NB_APO_CLK_EN                            (19)
+#define NB_APO_CLK                               (19)
+
+// ============================================================================
+// CPU_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP CPU side resets
+    CPU_RST_CORE                                = 0x00000000,
+    CPU_RST_SYS                                 = 0x00000001
+} CPU_RESETS_T;
+
+#define NB_CPU_RST                               (2)
+
+// ============================================================================
+// AXI_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AXI side resets: AXI and AHB0 and APB0
+    AXI_RST_VOC                                 = 0x00000000,
+    AXI_RST_DMA                                 = 0x00000001,
+    AXI_RST_SYS                                 = 0x00000002,
+    AXI_RST_CONNECT                             = 0x00000003,
+    AHB0_RST_GPU                                = 0x00000004,
+    APB0_RST_VPU                                = 0x00000005,
+    APB0_RST_IRQ                                = 0x00000006
+} AXI_RESETS_T;
+
+#define NB_AXI_RST                               (7)
+
+// ============================================================================
+// AXIDIV2_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AXIDIV2 side resets
+    AXIDIV2_RST_IMEM                            = 0x00000000,
+    AXIDIV2_RST_SYS                             = 0x00000001,
+    AXIDIV2_RST_VPU                             = 0x00000002
+} AXIDIV2_RESETS_T;
+
+#define NB_AXIDIV2_RST                           (3)
+
+// ============================================================================
+// GCG_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP GCG side resets
+    GCG_RST_SYS                                 = 0x00000000,
+    GCG_RST_GOUDA                               = 0x00000001,
+    GCG_RST_CAMERA                              = 0x00000002
+} GCG_RESETS_T;
+
+#define NB_GCG_RST                               (3)
+
+// ============================================================================
+// AHB1_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AHB1 side resets
+    AHB1_RST_SYS                                = 0x00000000,
+    AHB1_RST_USBC                               = 0x00000001,
+    AHB1_RST_SPIFLASH                           = 0x00000002
+} AHB1_RESETS_T;
+
+#define NB_AHB1_RST                              (3)
+
+// ============================================================================
+// APB1_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP APB1 side resets
+    APB1_RST_SYS                                = 0x00000000,
+    APB1_RST_TIMER                              = 0x00000001,
+    APB1_RST_KEYPAD                             = 0x00000002,
+    APB1_RST_GPIO                               = 0x00000003,
+    APB1_RST_PWM                                = 0x00000004,
+    APB1_RST_AIF                                = 0x00000005,
+    APB1_RST_AUIFC                              = 0x00000006,
+    APB1_RST_I2C1                               = 0x00000007,
+    APB1_RST_I2C2                               = 0x00000008,
+    APB1_RST_I2C3                               = 0x00000009,
+    APB1_RST_COM_REGS                           = 0x0000000A,
+    APB1_RST_DMC                                = 0x0000000B,
+    APB1_RST_DDRPHY_P                           = 0x0000000C,
+    APB1_RST_BB2G_XCPU                          = 0x0000000D,
+    APB1_RST_BB2G_BCPU                          = 0x0000000E,
+    APB1_RST_BB2G_AHBC                          = 0x0000000F,
+    APB1_RST_BB2G_DMA                           = 0x00000010,
+    APB1_RST_BB2G_A2A                           = 0x00000011,
+    APB1_RST_BB2G_XIFC                          = 0x00000012,
+    APB1_RST_BB2G_BIFC                          = 0x00000013,
+    APB1_RST_BB2G_BAHBC                         = 0x00000014,
+    APB1_RST_BB2G_MEM_BRIDGE                    = 0x00000015
+} APB1_RESETS_T;
+
+#define NB_APB1_RST                              (22)
+
+// ============================================================================
+// APB2_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP APB2 side resets
+    APB2_RST_SYS                                = 0x00000000,
+    APB2_RST_IFC                                = 0x00000001,
+    APB2_RST_UART1                              = 0x00000002,
+    APB2_RST_UART2                              = 0x00000003,
+    APB2_RST_UART3                              = 0x00000004,
+    APB2_RST_SPI1                               = 0x00000005,
+    APB2_RST_SPI2                               = 0x00000006,
+    APB2_RST_SPI3                               = 0x00000007,
+    APB2_RST_SDMMC1                             = 0x00000008,
+    APB2_RST_SDMMC2                             = 0x00000009,
+    APB2_RST_SDMMC3                             = 0x0000000A,
+    APB2_RST_NANDFLASH                          = 0x0000000B
+} APB2_RESETS_T;
+
+#define NB_APB2_RST                              (12)
+
+// ============================================================================
+// MEM_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP MEM side resets
+    MEM_RST_SYS                                 = 0x00000000,
+    MEM_RST_GPU                                 = 0x00000001,
+    MEM_RST_VPU                                 = 0x00000002,
+    MEM_RST_DMC                                 = 0x00000003,
+    MEM_RST_DDRPHY_P                            = 0x00000004
+} MEM_RESETS_T;
+
+#define NB_MEM_RST                               (5)
+
+// ============================================================================
+// AP_OTHERS_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP Reset Other : resync on corresponding clock other
+    AP_RSTO_VOC                                 = 0x00000000,
+    AP_RSTO_DDRPHY_N                            = 0x00000001,
+    AP_RSTO_DDRPHY2XP                           = 0x00000002,
+    AP_RSTO_DDRPHY2XN                           = 0x00000003,
+    AP_RSTO_GPU                                 = 0x00000004,
+    AP_RSTO_VPU                                 = 0x00000005,
+    AP_RSTO_BCK                                 = 0x00000006,
+    AP_RSTO_UART1                               = 0x00000007,
+    AP_RSTO_UART2                               = 0x00000008,
+    AP_RSTO_UART3                               = 0x00000009,
+    AP_RSTO_GPIO                                = 0x0000000A,
+    AP_RSTO_TIMER                               = 0x0000000B,
+    AP_RSTO_USBC                                = 0x0000000C,
+    AP_RSTO_DSI                                 = 0x0000000D,
+    AP_RSTO_SPIFLASH                            = 0x0000000E,
+    AP_RSTO_TCK                                 = 0x0000000F,
+    AP_RSTO_PDBG_XTAL                           = 0x00000010
+} AP_OTHERS_RESETS_T;
+
+#define NB_AP_RSTO                               (17)
+/// For REG_DBG protect lock/unlock value
+#define AP_CTRL_PROTECT_LOCK                     (0XA50000)
+#define AP_CTRL_PROTECT_UNLOCK                   (0XA50001)
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+// ============================================================================
+// SYS_CTRL_AP_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef volatile struct
+{
+    /// <strong>This register is used to Lock and Unlock the protected registers.</strong>
+    REG32                          REG_DBG;                      //0x00000000
+    /// Register protected by Write_Unlocked_H.
+    REG32                          Cfg_Pll_Ctrl[4];              //0x00000004
+    /// This register is protected.
+    REG32                          Sel_Clock;                    //0x00000014
+    REG32                          Reset_Cause;                  //0x00000018
+    /// This register is protected.
+    REG32                          CPU_Rst_Set;                  //0x0000001C
+    REG32                          CPU_Rst_Clr;                  //0x00000020
+    /// This register is protected.
+    REG32                          AXI_Rst_Set;                  //0x00000024
+    REG32                          AXI_Rst_Clr;                  //0x00000028
+    /// This register is protected.
+    REG32                          AXIDIV2_Rst_Set;              //0x0000002C
+    REG32                          AXIDIV2_Rst_Clr;              //0x00000030
+    /// This register is protected.
+    REG32                          GCG_Rst_Set;                  //0x00000034
+    REG32                          GCG_Rst_Clr;                  //0x00000038
+    /// This register is protected.
+    REG32                          AHB1_Rst_Set;                 //0x0000003C
+    REG32                          AHB1_Rst_Clr;                 //0x00000040
+    /// This register is protected.
+    REG32                          APB1_Rst_Set;                 //0x00000044
+    REG32                          APB1_Rst_Clr;                 //0x00000048
+    /// This register is protected.
+    REG32                          APB2_Rst_Set;                 //0x0000004C
+    REG32                          APB2_Rst_Clr;                 //0x00000050
+    /// This register is protected.
+    REG32                          MEM_Rst_Set;                  //0x00000054
+    REG32                          MEM_Rst_Clr;                  //0x00000058
+    REG32                          Clk_CPU_Mode;                 //0x0000005C
+    REG32                          Clk_CPU_Enable;               //0x00000060
+    /// This register is protected.
+    REG32                          Clk_CPU_Disable;              //0x00000064
+    REG32                          Clk_AXI_Mode;                 //0x00000068
+    REG32                          Clk_AXI_Enable;               //0x0000006C
+    /// This register is protected.
+    REG32                          Clk_AXI_Disable;              //0x00000070
+    REG32                          Clk_AXIDIV2_Mode;             //0x00000074
+    REG32                          Clk_AXIDIV2_Enable;           //0x00000078
+    /// This register is protected.
+    REG32                          Clk_AXIDIV2_Disable;          //0x0000007C
+    REG32                          Clk_GCG_Mode;                 //0x00000080
+    REG32                          Clk_GCG_Enable;               //0x00000084
+    /// This register is protected.
+    REG32                          Clk_GCG_Disable;              //0x00000088
+    REG32                          Clk_AHB1_Mode;                //0x0000008C
+    REG32                          Clk_AHB1_Enable;              //0x00000090
+    /// This register is protected.
+    REG32                          Clk_AHB1_Disable;             //0x00000094
+    REG32                          Clk_APB1_Mode;                //0x00000098
+    REG32                          Clk_APB1_Enable;              //0x0000009C
+    /// This register is protected.
+    REG32                          Clk_APB1_Disable;             //0x000000A0
+    REG32                          Clk_APB2_Mode;                //0x000000A4
+    REG32                          Clk_APB2_Enable;              //0x000000A8
+    /// This register is protected.
+    REG32                          Clk_APB2_Disable;             //0x000000AC
+    REG32                          Clk_MEM_Mode;                 //0x000000B0
+    REG32                          Clk_MEM_Enable;               //0x000000B4
+    /// This register is protected.
+    REG32                          Clk_MEM_Disable;              //0x000000B8
+    REG32                          Clk_APO_Mode;                 //0x000000BC
+    REG32                          Clk_APO_Enable;               //0x000000C0
+    /// This register is protected.
+    REG32                          Clk_APO_Disable;              //0x000000C4
+    REG32                          Cfg_Clk_AP_CPU;               //0x000000C8
+    REG32                          Cfg_Clk_AP_AXI;               //0x000000CC
+    REG32                          Cfg_Clk_AP_GCG;               //0x000000D0
+    REG32                          Cfg_Clk_AP_AHB1;              //0x000000D4
+    REG32                          Cfg_Clk_AP_APB1;              //0x000000D8
+    REG32                          Cfg_Clk_AP_APB2;              //0x000000DC
+    REG32                          Cfg_Clk_AP_MEM;               //0x000000E0
+    REG32                          Cfg_Clk_AP_GPU;               //0x000000E4
+    REG32                          Cfg_Clk_AP_VPU;               //0x000000E8
+    REG32                          Cfg_Clk_AP_VOC;               //0x000000EC
+    REG32                          Cfg_Clk_AP_SFLSH;             //0x000000F0
+    REG32                          Cfg_Clk_Uart[3];              //0x000000F4
+    REG32                          L2cc_Ctrl;                    //0x00000100
+    REG32                          Spi_Ctrl;                     //0x00000104
+    REG32                          Memory_Margin;                //0x00000108
+    REG32                          Memory_Margin2;               //0x0000010C
+    REG32                          Memory_Observe;               //0x00000110
+    REG32 Reserved_00000114[58];                //0x00000114
+    /// This register is reserved.
+    REG32                          Cfg_Reserve;                  //0x000001FC
+} HWP_SYS_CTRL_AP_T;
+
+#define hwp_sysCtrlAp               ((HWP_SYS_CTRL_AP_T*)(RDA_SYSCTRL_BASE))
+
+
+//REG_DBG
+#define SYS_CTRL_AP_SCRATCH(n)      (((n)&0xFFFF)<<0)
+#define SYS_CTRL_AP_WRITE_UNLOCK_STATUS (1<<30)
+#define SYS_CTRL_AP_WRITE_UNLOCK    (1<<31)
+
+//Cfg_Pll_Ctrl
+#define SYS_CTRL_AP_AP_PLL_ENABLE   (1<<0)
+#define SYS_CTRL_AP_AP_PLL_ENABLE_MASK (1<<0)
+#define SYS_CTRL_AP_AP_PLL_ENABLE_SHIFT (0)
+#define SYS_CTRL_AP_AP_PLL_ENABLE_POWER_DOWN (0<<0)
+#define SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE (1<<0)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET (1<<4)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_MASK (1<<4)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_SHIFT (4)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_RESET (0<<4)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET (1<<4)
+#define SYS_CTRL_AP_AP_PLL_BYPASS   (1<<8)
+#define SYS_CTRL_AP_AP_PLL_BYPASS_MASK (1<<8)
+#define SYS_CTRL_AP_AP_PLL_BYPASS_SHIFT (8)
+#define SYS_CTRL_AP_AP_PLL_BYPASS_PASS (0<<8)
+#define SYS_CTRL_AP_AP_PLL_BYPASS_BYPASS (1<<8)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE (1<<12)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_MASK (1<<12)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_SHIFT (12)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_ENABLE (1<<12)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_DISABLE (0<<12)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(n) (((n)&31)<<16)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW_MASK (31<<16)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW_SHIFT (16)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(n) (((n)&31)<<24)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH_MASK (31<<24)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH_SHIFT (24)
+#define SYS_CTRL_AP_PLL_AP_CFG(n)   (((n)&0x1F1F1111)<<0)
+#define SYS_CTRL_AP_PLL_AP_CFG_MASK (0x1F1F1111<<0)
+#define SYS_CTRL_AP_PLL_AP_CFG_SHIFT (0)
+
+//Sel_Clock
+#define SYS_CTRL_AP_SLOW_SEL_RF_OSCILLATOR (1<<0)
+#define SYS_CTRL_AP_SLOW_SEL_RF_RF  (0<<0)
+#define SYS_CTRL_AP_CPU_SEL_FAST_SLOW (1<<4)
+#define SYS_CTRL_AP_CPU_SEL_FAST_FAST (0<<4)
+#define SYS_CTRL_AP_BUS_SEL_FAST_SLOW (1<<5)
+#define SYS_CTRL_AP_BUS_SEL_FAST_FAST (0<<5)
+#define SYS_CTRL_AP_TIMER_SEL_FAST_SLOW (1<<7)
+#define SYS_CTRL_AP_TIMER_SEL_FAST_FAST (0<<7)
+#define SYS_CTRL_AP_RF_DETECTED_OK  (1<<8)
+#define SYS_CTRL_AP_RF_DETECTED_NO  (0<<8)
+#define SYS_CTRL_AP_RF_DETECT_BYPASS (1<<9)
+#define SYS_CTRL_AP_RF_DETECT_RESET (1<<10)
+#define SYS_CTRL_AP_RF_SELECTED_L   (1<<11)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU  (1<<12)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU_MASK (1<<12)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU_SHIFT (12)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU_LOCKED (1<<12)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU_NOT_LOCKED (0<<12)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS  (1<<13)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS_MASK (1<<13)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS_SHIFT (13)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS_LOCKED (1<<13)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS_NOT_LOCKED (0<<13)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM  (1<<14)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM_MASK (1<<14)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM_SHIFT (14)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM_LOCKED (1<<14)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM_NOT_LOCKED (0<<14)
+#define SYS_CTRL_AP_PLL_LOCKED_USB  (1<<15)
+#define SYS_CTRL_AP_PLL_LOCKED_USB_MASK (1<<15)
+#define SYS_CTRL_AP_PLL_LOCKED_USB_SHIFT (15)
+#define SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED (1<<15)
+#define SYS_CTRL_AP_PLL_LOCKED_USB_NOT_LOCKED (0<<15)
+#define SYS_CTRL_AP_PLL_BYPASS_LOCK_CPU (1<<20)
+#define SYS_CTRL_AP_PLL_BYPASS_LOCK_BUS (1<<21)
+#define SYS_CTRL_AP_FAST_SELECTED_CPU_L (1<<30)
+#define SYS_CTRL_AP_FAST_SELECTED_CPU_L_MASK (1<<30)
+#define SYS_CTRL_AP_FAST_SELECTED_CPU_L_SHIFT (30)
+#define SYS_CTRL_AP_FAST_SELECTED_BUS_L (1<<31)
+#define SYS_CTRL_AP_FAST_SELECTED_BUS_L_MASK (1<<31)
+#define SYS_CTRL_AP_FAST_SELECTED_BUS_L_SHIFT (31)
+
+//Reset_Cause
+#define SYS_CTRL_AP_WATCHDOG_RESET_HAPPENED (1<<0)
+#define SYS_CTRL_AP_WATCHDOG_RESET_NO (0<<0)
+#define SYS_CTRL_AP_GLOBALSOFT_RESET_HAPPENED (1<<4)
+#define SYS_CTRL_AP_GLOBALSOFT_RESET_NO (0<<4)
+#define SYS_CTRL_AP_HOSTDEBUG_RESET_HAPPENED (1<<5)
+#define SYS_CTRL_AP_HOSTDEBUG_RESET_NO (0<<5)
+#define SYS_CTRL_AP_ALARMCAUSE_HAPPENED (1<<6)
+#define SYS_CTRL_AP_ALARMCAUSE_NO   (0<<6)
+#define SYS_CTRL_AP_BOOT_MODE(n)    (((n)&0xFFFF)<<8)
+#define SYS_CTRL_AP_BOOT_MODE_MASK  (0xFFFF<<8)
+#define SYS_CTRL_AP_BOOT_MODE_SHIFT (8)
+#define SYS_CTRL_AP_SW_BOOT_MODE(n) (((n)&0x7F)<<24)
+#define SYS_CTRL_AP_SW_BOOT_MODE_MASK (0x7F<<24)
+#define SYS_CTRL_AP_SW_BOOT_MODE_SHIFT (24)
+#define SYS_CTRL_AP_FONCTIONAL_TEST_MODE (1<<31)
+
+//CPU_Rst_Set
+#define SYS_CTRL_AP_SET_CPU_RST_CORE (1<<0)
+#define SYS_CTRL_AP_SET_CPU_RST_SYS (1<<1)
+#define SYS_CTRL_AP_SOFT_RST        (1<<31)
+#define SYS_CTRL_AP_SET_CPU_RST(n)  (((n)&3)<<0)
+#define SYS_CTRL_AP_SET_CPU_RST_MASK (3<<0)
+#define SYS_CTRL_AP_SET_CPU_RST_SHIFT (0)
+
+//CPU_Rst_Clr
+#define SYS_CTRL_AP_CLR_CPU_RST_CORE (1<<0)
+#define SYS_CTRL_AP_CLR_CPU_RST_SYS (1<<1)
+#define SYS_CTRL_AP_CLR_CPU_RST(n)  (((n)&3)<<0)
+#define SYS_CTRL_AP_CLR_CPU_RST_MASK (3<<0)
+#define SYS_CTRL_AP_CLR_CPU_RST_SHIFT (0)
+
+//AXI_Rst_Set
+#define SYS_CTRL_AP_SET_AXI_RST_VOC (1<<0)
+#define SYS_CTRL_AP_SET_AXI_RST_DMA (1<<1)
+#define SYS_CTRL_AP_SET_AXI_RST_SYS (1<<2)
+#define SYS_CTRL_AP_SET_AXI_RST_CONNECT (1<<3)
+#define SYS_CTRL_AP_SET_AHB0_RST_GPU (1<<4)
+#define SYS_CTRL_AP_SET_APB0_RST_VPU (1<<5)
+#define SYS_CTRL_AP_SET_APB0_RST_IRQ (1<<6)
+#define SYS_CTRL_AP_SET_AXI_RST(n)  (((n)&0x7F)<<0)
+#define SYS_CTRL_AP_SET_AXI_RST_MASK (0x7F<<0)
+#define SYS_CTRL_AP_SET_AXI_RST_SHIFT (0)
+
+//AXI_Rst_Clr
+#define SYS_CTRL_AP_CLR_AXI_RST_VOC (1<<0)
+#define SYS_CTRL_AP_CLR_AXI_RST_DMA (1<<1)
+#define SYS_CTRL_AP_CLR_AXI_RST_SYS (1<<2)
+#define SYS_CTRL_AP_CLR_AXI_RST_CONNECT (1<<3)
+#define SYS_CTRL_AP_CLR_AHB0_RST_GPU (1<<4)
+#define SYS_CTRL_AP_CLR_APB0_RST_VPU (1<<5)
+#define SYS_CTRL_AP_CLR_APB0_RST_IRQ (1<<6)
+#define SYS_CTRL_AP_CLR_AXI_RST(n)  (((n)&0x7F)<<0)
+#define SYS_CTRL_AP_CLR_AXI_RST_MASK (0x7F<<0)
+#define SYS_CTRL_AP_CLR_AXI_RST_SHIFT (0)
+
+//AXIDIV2_Rst_Set
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_IMEM (1<<0)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_SYS (1<<1)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_VPU (1<<2)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_MASK (7<<0)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_SHIFT (0)
+
+//AXIDIV2_Rst_Clr
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_IMEM (1<<0)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_SYS (1<<1)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_VPU (1<<2)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_MASK (7<<0)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_SHIFT (0)
+
+//GCG_Rst_Set
+#define SYS_CTRL_AP_SET_GCG_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_GCG_RST_GOUDA (1<<1)
+#define SYS_CTRL_AP_SET_GCG_RST_CAMERA (1<<2)
+#define SYS_CTRL_AP_SET_GCG_RST(n)  (((n)&7)<<0)
+#define SYS_CTRL_AP_SET_GCG_RST_MASK (7<<0)
+#define SYS_CTRL_AP_SET_GCG_RST_SHIFT (0)
+
+//GCG_Rst_Clr
+#define SYS_CTRL_AP_CLR_GCG_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_GCG_RST_GOUDA (1<<1)
+#define SYS_CTRL_AP_CLR_GCG_RST_CAMERA (1<<2)
+#define SYS_CTRL_AP_CLR_GCG_RST(n)  (((n)&7)<<0)
+#define SYS_CTRL_AP_CLR_GCG_RST_MASK (7<<0)
+#define SYS_CTRL_AP_CLR_GCG_RST_SHIFT (0)
+
+//AHB1_Rst_Set
+#define SYS_CTRL_AP_SET_AHB1_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_AHB1_RST_USBC (1<<1)
+#define SYS_CTRL_AP_SET_AHB1_RST_SPIFLASH (1<<2)
+#define SYS_CTRL_AP_SET_AHB1_RST(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_SET_AHB1_RST_MASK (7<<0)
+#define SYS_CTRL_AP_SET_AHB1_RST_SHIFT (0)
+
+//AHB1_Rst_Clr
+#define SYS_CTRL_AP_CLR_AHB1_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_AHB1_RST_USBC (1<<1)
+#define SYS_CTRL_AP_CLR_AHB1_RST_SPIFLASH (1<<2)
+#define SYS_CTRL_AP_CLR_AHB1_RST(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_CLR_AHB1_RST_MASK (7<<0)
+#define SYS_CTRL_AP_CLR_AHB1_RST_SHIFT (0)
+
+//APB1_Rst_Set
+#define SYS_CTRL_AP_SET_APB1_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_APB1_RST_TIMER (1<<1)
+#define SYS_CTRL_AP_SET_APB1_RST_KEYPAD (1<<2)
+#define SYS_CTRL_AP_SET_APB1_RST_GPIO (1<<3)
+#define SYS_CTRL_AP_SET_APB1_RST_PWM (1<<4)
+#define SYS_CTRL_AP_SET_APB1_RST_AIF (1<<5)
+#define SYS_CTRL_AP_SET_APB1_RST_AUIFC (1<<6)
+#define SYS_CTRL_AP_SET_APB1_RST_I2C1 (1<<7)
+#define SYS_CTRL_AP_SET_APB1_RST_I2C2 (1<<8)
+#define SYS_CTRL_AP_SET_APB1_RST_I2C3 (1<<9)
+#define SYS_CTRL_AP_SET_APB1_RST_COM_REGS (1<<10)
+#define SYS_CTRL_AP_SET_APB1_RST_DMC (1<<11)
+#define SYS_CTRL_AP_SET_APB1_RST_DDRPHY_P (1<<12)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_XCPU (1<<13)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BCPU (1<<14)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_AHBC (1<<15)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_DMA (1<<16)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_A2A (1<<17)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_XIFC (1<<18)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BIFC (1<<19)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BAHBC (1<<20)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_MEM_BRIDGE (1<<21)
+#define SYS_CTRL_AP_SET_APB1_RST(n) (((n)&0x3FFFFF)<<0)
+#define SYS_CTRL_AP_SET_APB1_RST_MASK (0x3FFFFF<<0)
+#define SYS_CTRL_AP_SET_APB1_RST_SHIFT (0)
+
+//APB1_Rst_Clr
+#define SYS_CTRL_AP_CLR_APB1_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_APB1_RST_TIMER (1<<1)
+#define SYS_CTRL_AP_CLR_APB1_RST_KEYPAD (1<<2)
+#define SYS_CTRL_AP_CLR_APB1_RST_GPIO (1<<3)
+#define SYS_CTRL_AP_CLR_APB1_RST_PWM (1<<4)
+#define SYS_CTRL_AP_CLR_APB1_RST_AIF (1<<5)
+#define SYS_CTRL_AP_CLR_APB1_RST_AUIFC (1<<6)
+#define SYS_CTRL_AP_CLR_APB1_RST_I2C1 (1<<7)
+#define SYS_CTRL_AP_CLR_APB1_RST_I2C2 (1<<8)
+#define SYS_CTRL_AP_CLR_APB1_RST_I2C3 (1<<9)
+#define SYS_CTRL_AP_CLR_APB1_RST_COM_REGS (1<<10)
+#define SYS_CTRL_AP_CLR_APB1_RST_DMC (1<<11)
+#define SYS_CTRL_AP_CLR_APB1_RST_DDRPHY_P (1<<12)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_XCPU (1<<13)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BCPU (1<<14)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_AHBC (1<<15)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_DMA (1<<16)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_A2A (1<<17)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_XIFC (1<<18)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BIFC (1<<19)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BAHBC (1<<20)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_MEM_BRIDGE (1<<21)
+#define SYS_CTRL_AP_CLR_APB1_RST(n) (((n)&0x3FFFFF)<<0)
+#define SYS_CTRL_AP_CLR_APB1_RST_MASK (0x3FFFFF<<0)
+#define SYS_CTRL_AP_CLR_APB1_RST_SHIFT (0)
+
+//APB2_Rst_Set
+#define SYS_CTRL_AP_SET_APB2_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_APB2_RST_IFC (1<<1)
+#define SYS_CTRL_AP_SET_APB2_RST_UART1 (1<<2)
+#define SYS_CTRL_AP_SET_APB2_RST_UART2 (1<<3)
+#define SYS_CTRL_AP_SET_APB2_RST_UART3 (1<<4)
+#define SYS_CTRL_AP_SET_APB2_RST_SPI1 (1<<5)
+#define SYS_CTRL_AP_SET_APB2_RST_SPI2 (1<<6)
+#define SYS_CTRL_AP_SET_APB2_RST_SPI3 (1<<7)
+#define SYS_CTRL_AP_SET_APB2_RST_SDMMC1 (1<<8)
+#define SYS_CTRL_AP_SET_APB2_RST_SDMMC2 (1<<9)
+#define SYS_CTRL_AP_SET_APB2_RST_SDMMC3 (1<<10)
+#define SYS_CTRL_AP_SET_APB2_RST_NANDFLASH (1<<11)
+#define SYS_CTRL_AP_SET_APB2_RST(n) (((n)&0xFFF)<<0)
+#define SYS_CTRL_AP_SET_APB2_RST_MASK (0xFFF<<0)
+#define SYS_CTRL_AP_SET_APB2_RST_SHIFT (0)
+
+//APB2_Rst_Clr
+#define SYS_CTRL_AP_CLR_APB2_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_APB2_RST_IFC (1<<1)
+#define SYS_CTRL_AP_CLR_APB2_RST_UART1 (1<<2)
+#define SYS_CTRL_AP_CLR_APB2_RST_UART2 (1<<3)
+#define SYS_CTRL_AP_CLR_APB2_RST_UART3 (1<<4)
+#define SYS_CTRL_AP_CLR_APB2_RST_SPI1 (1<<5)
+#define SYS_CTRL_AP_CLR_APB2_RST_SPI2 (1<<6)
+#define SYS_CTRL_AP_CLR_APB2_RST_SPI3 (1<<7)
+#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC1 (1<<8)
+#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC2 (1<<9)
+#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC3 (1<<10)
+#define SYS_CTRL_AP_CLR_APB2_RST_NANDFLASH (1<<11)
+#define SYS_CTRL_AP_CLR_APB2_RST(n) (((n)&0xFFF)<<0)
+#define SYS_CTRL_AP_CLR_APB2_RST_MASK (0xFFF<<0)
+#define SYS_CTRL_AP_CLR_APB2_RST_SHIFT (0)
+
+//MEM_Rst_Set
+#define SYS_CTRL_AP_SET_MEM_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_MEM_RST_GPU (1<<1)
+#define SYS_CTRL_AP_SET_MEM_RST_VPU (1<<2)
+#define SYS_CTRL_AP_SET_MEM_RST_DMC (1<<3)
+#define SYS_CTRL_AP_SET_MEM_RST_DDRPHY_P (1<<4)
+#define SYS_CTRL_AP_SET_MEM_RST(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_SET_MEM_RST_MASK (31<<0)
+#define SYS_CTRL_AP_SET_MEM_RST_SHIFT (0)
+
+//MEM_Rst_Clr
+#define SYS_CTRL_AP_CLR_MEM_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_MEM_RST_GPU (1<<1)
+#define SYS_CTRL_AP_CLR_MEM_RST_VPU (1<<2)
+#define SYS_CTRL_AP_CLR_MEM_RST_DMC (1<<3)
+#define SYS_CTRL_AP_CLR_MEM_RST_DDRPHY_P (1<<4)
+#define SYS_CTRL_AP_CLR_MEM_RST(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_CLR_MEM_RST_MASK (31<<0)
+#define SYS_CTRL_AP_CLR_MEM_RST_SHIFT (0)
+
+//Clk_CPU_Mode
+#define SYS_CTRL_AP_MODE_CLK_CPU_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_CLK_CPU_MANUAL (1<<0)
+
+//Clk_CPU_Enable
+#define SYS_CTRL_AP_ENABLE_CPU_CORE (1<<0)
+#define SYS_CTRL_AP_ENABLE_CPU_DUMMY (1<<1)
+#define SYS_CTRL_AP_ENABLE_CLK_CPU(n) (((n)&3)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_CPU_MASK (3<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_CPU_SHIFT (0)
+
+//Clk_CPU_Disable
+#define SYS_CTRL_AP_DISABLE_CPU_CORE (1<<0)
+#define SYS_CTRL_AP_DISABLE_CPU_DUMMY (1<<1)
+#define SYS_CTRL_AP_DISABLE_CLK_CPU(n) (((n)&3)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_CPU_MASK (3<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_CPU_SHIFT (0)
+
+//Clk_AXI_Mode
+#define SYS_CTRL_AP_MODE_AHB0_CONF_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_AHB0_CONF_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_APB0_CONF_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_APB0_CONF_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_AXI_VOC_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_AXI_VOC_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_AXI_DMA_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_AXI_DMA_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_CLK_AXI(n) (((n)&15)<<0)
+#define SYS_CTRL_AP_MODE_CLK_AXI_MASK (15<<0)
+#define SYS_CTRL_AP_MODE_CLK_AXI_SHIFT (0)
+
+//Clk_AXI_Enable
+#define SYS_CTRL_AP_ENABLE_AHB0_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_APB0_CONF (1<<1)
+#define SYS_CTRL_AP_ENABLE_AXI_VOC  (1<<2)
+#define SYS_CTRL_AP_ENABLE_AXI_DMA  (1<<3)
+#define SYS_CTRL_AP_ENABLE_AXI_ALWAYS (1<<4)
+#define SYS_CTRL_AP_ENABLE_AXI_CONNECT (1<<5)
+#define SYS_CTRL_AP_ENABLE_APB0_IRQ (1<<6)
+#define SYS_CTRL_AP_ENABLE_CLK_AXI(n) (((n)&0x7F)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AXI_MASK (0x7F<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AXI_SHIFT (0)
+
+//Clk_AXI_Disable
+#define SYS_CTRL_AP_DISABLE_AHB0_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_APB0_CONF (1<<1)
+#define SYS_CTRL_AP_DISABLE_AXI_VOC (1<<2)
+#define SYS_CTRL_AP_DISABLE_AXI_DMA (1<<3)
+#define SYS_CTRL_AP_DISABLE_AXI_ALWAYS (1<<4)
+#define SYS_CTRL_AP_DISABLE_AXI_CONNECT (1<<5)
+#define SYS_CTRL_AP_DISABLE_APB0_IRQ (1<<6)
+#define SYS_CTRL_AP_DISABLE_CLK_AXI(n) (((n)&0x7F)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AXI_MASK (0x7F<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AXI_SHIFT (0)
+
+//Clk_AXIDIV2_Mode
+#define SYS_CTRL_AP_MODE_CLK_AXIDIV2_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_CLK_AXIDIV2_MANUAL (1<<0)
+
+//Clk_AXIDIV2_Enable
+#define SYS_CTRL_AP_ENABLE_AXIDIV2_IMEM (1<<0)
+#define SYS_CTRL_AP_ENABLE_AXIDIV2_ALWAYS (1<<1)
+#define SYS_CTRL_AP_ENABLE_AXIDIV2_CONNECT (1<<2)
+#define SYS_CTRL_AP_ENABLE_AXIDIV2_VPU (1<<3)
+#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2(n) (((n)&15)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2_MASK (15<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2_SHIFT (0)
+
+//Clk_AXIDIV2_Disable
+#define SYS_CTRL_AP_DISABLE_AXIDIV2_IMEM (1<<0)
+#define SYS_CTRL_AP_DISABLE_AXIDIV2_ALWAYS (1<<1)
+#define SYS_CTRL_AP_DISABLE_AXIDIV2_CONNECT (1<<2)
+#define SYS_CTRL_AP_DISABLE_AXIDIV2_VPU (1<<3)
+#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2(n) (((n)&15)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2_MASK (15<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2_SHIFT (0)
+
+//Clk_GCG_Mode
+#define SYS_CTRL_AP_MODE_GCG_APB_CONF_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_GCG_APB_CONF_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_GCG_GOUDA_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_GCG_GOUDA_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_GCG_CAMERA_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_GCG_CAMERA_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_CLK_GCG(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_MODE_CLK_GCG_MASK (7<<0)
+#define SYS_CTRL_AP_MODE_CLK_GCG_SHIFT (0)
+
+//Clk_GCG_Enable
+#define SYS_CTRL_AP_ENABLE_GCG_APB_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_GCG_GOUDA (1<<1)
+#define SYS_CTRL_AP_ENABLE_GCG_CAMERA (1<<2)
+#define SYS_CTRL_AP_ENABLE_GCG_ALWAYS (1<<3)
+#define SYS_CTRL_AP_ENABLE_GCG_CONNECT (1<<4)
+#define SYS_CTRL_AP_ENABLE_CLK_GCG(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_GCG_MASK (31<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_GCG_SHIFT (0)
+
+//Clk_GCG_Disable
+#define SYS_CTRL_AP_DISABLE_GCG_APB_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_GCG_GOUDA (1<<1)
+#define SYS_CTRL_AP_DISABLE_GCG_CAMERA (1<<2)
+#define SYS_CTRL_AP_DISABLE_GCG_ALWAYS (1<<3)
+#define SYS_CTRL_AP_DISABLE_GCG_CONNECT (1<<4)
+#define SYS_CTRL_AP_DISABLE_CLK_GCG(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_GCG_MASK (31<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_GCG_SHIFT (0)
+
+//Clk_AHB1_Mode
+#define SYS_CTRL_AP_MODE_CLK_AHB1_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_CLK_AHB1_MANUAL (1<<0)
+
+//Clk_AHB1_Enable
+#define SYS_CTRL_AP_ENABLE_AHB1_USBC (1<<0)
+#define SYS_CTRL_AP_ENABLE_AHB1_ALWAYS (1<<1)
+#define SYS_CTRL_AP_ENABLE_AHB1_SPIFLASH (1<<2)
+#define SYS_CTRL_AP_ENABLE_CLK_AHB1(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AHB1_MASK (7<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AHB1_SHIFT (0)
+
+//Clk_AHB1_Disable
+#define SYS_CTRL_AP_DISABLE_AHB1_USBC (1<<0)
+#define SYS_CTRL_AP_DISABLE_AHB1_ALWAYS (1<<1)
+#define SYS_CTRL_AP_DISABLE_AHB1_SPIFLASH (1<<2)
+#define SYS_CTRL_AP_DISABLE_CLK_AHB1(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AHB1_MASK (7<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AHB1_SHIFT (0)
+
+//Clk_APB1_Mode
+#define SYS_CTRL_AP_MODE_APB1_CONF_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_APB1_CONF_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_APB1_AIF_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_APB1_AIF_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH0_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH0_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH1_AUTOMATIC (0<<4)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH1_MANUAL (1<<4)
+#define SYS_CTRL_AP_MODE_APB1_I2C1_AUTOMATIC (0<<5)
+#define SYS_CTRL_AP_MODE_APB1_I2C1_MANUAL (1<<5)
+#define SYS_CTRL_AP_MODE_APB1_I2C2_AUTOMATIC (0<<6)
+#define SYS_CTRL_AP_MODE_APB1_I2C2_MANUAL (1<<6)
+#define SYS_CTRL_AP_MODE_APB1_I2C3_AUTOMATIC (0<<7)
+#define SYS_CTRL_AP_MODE_APB1_I2C3_MANUAL (1<<7)
+#define SYS_CTRL_AP_MODE_APB1D_OSC_AUTOMATIC (0<<8)
+#define SYS_CTRL_AP_MODE_APB1D_OSC_MANUAL (1<<8)
+#define SYS_CTRL_AP_MODE_APB1D_PWM_AUTOMATIC (0<<9)
+#define SYS_CTRL_AP_MODE_APB1D_PWM_MANUAL (1<<9)
+#define SYS_CTRL_AP_MODE_CLK_APB1(n) (((n)&0x3FF)<<0)
+#define SYS_CTRL_AP_MODE_CLK_APB1_MASK (0x3FF<<0)
+#define SYS_CTRL_AP_MODE_CLK_APB1_SHIFT (0)
+
+//Clk_APB1_Enable
+#define SYS_CTRL_AP_ENABLE_APB1_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_APB1_AIF (1<<1)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC (1<<2)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH0 (1<<3)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH1 (1<<4)
+#define SYS_CTRL_AP_ENABLE_APB1_I2C1 (1<<5)
+#define SYS_CTRL_AP_ENABLE_APB1_I2C2 (1<<6)
+#define SYS_CTRL_AP_ENABLE_APB1_I2C3 (1<<7)
+#define SYS_CTRL_AP_ENABLE_APB1D_OSC (1<<8)
+#define SYS_CTRL_AP_ENABLE_APB1D_PWM (1<<9)
+#define SYS_CTRL_AP_ENABLE_APB1_ALWAYS (1<<10)
+#define SYS_CTRL_AP_ENABLE_APB1_DAPLITE (1<<11)
+#define SYS_CTRL_AP_ENABLE_APB1_TIMER (1<<12)
+#define SYS_CTRL_AP_ENABLE_APB1_GPIO (1<<13)
+#define SYS_CTRL_AP_ENABLE_CLK_APB1(n) (((n)&0x3FFF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APB1_MASK (0x3FFF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APB1_SHIFT (0)
+
+//Clk_APB1_Disable
+#define SYS_CTRL_AP_DISABLE_APB1_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_APB1_AIF (1<<1)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC (1<<2)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH0 (1<<3)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH1 (1<<4)
+#define SYS_CTRL_AP_DISABLE_APB1_I2C1 (1<<5)
+#define SYS_CTRL_AP_DISABLE_APB1_I2C2 (1<<6)
+#define SYS_CTRL_AP_DISABLE_APB1_I2C3 (1<<7)
+#define SYS_CTRL_AP_DISABLE_APB1D_OSC (1<<8)
+#define SYS_CTRL_AP_DISABLE_APB1D_PWM (1<<9)
+#define SYS_CTRL_AP_DISABLE_APB1_ALWAYS (1<<10)
+#define SYS_CTRL_AP_DISABLE_APB1_DAPLITE (1<<11)
+#define SYS_CTRL_AP_DISABLE_APB1_TIMER (1<<12)
+#define SYS_CTRL_AP_DISABLE_APB1_GPIO (1<<13)
+#define SYS_CTRL_AP_DISABLE_CLK_APB1(n) (((n)&0x3FFF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APB1_MASK (0x3FFF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APB1_SHIFT (0)
+
+//Clk_APB2_Mode
+#define SYS_CTRL_AP_MODE_APB2_CONF_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_APB2_CONF_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_APB2_IFC_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_APB2_IFC_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH0_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH0_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH1_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH1_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH2_AUTOMATIC (0<<4)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH2_MANUAL (1<<4)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH3_AUTOMATIC (0<<5)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH3_MANUAL (1<<5)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH4_AUTOMATIC (0<<6)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH4_MANUAL (1<<6)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH5_AUTOMATIC (0<<7)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH5_MANUAL (1<<7)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH6_AUTOMATIC (0<<8)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH6_MANUAL (1<<8)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH7_AUTOMATIC (0<<9)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH7_MANUAL (1<<9)
+#define SYS_CTRL_AP_MODE_APB2_UART1_AUTOMATIC (0<<10)
+#define SYS_CTRL_AP_MODE_APB2_UART1_MANUAL (1<<10)
+#define SYS_CTRL_AP_MODE_APB2_UART2_AUTOMATIC (0<<11)
+#define SYS_CTRL_AP_MODE_APB2_UART2_MANUAL (1<<11)
+#define SYS_CTRL_AP_MODE_APB2_UART3_AUTOMATIC (0<<12)
+#define SYS_CTRL_AP_MODE_APB2_UART3_MANUAL (1<<12)
+#define SYS_CTRL_AP_MODE_APB2_SPI1_AUTOMATIC (0<<13)
+#define SYS_CTRL_AP_MODE_APB2_SPI1_MANUAL (1<<13)
+#define SYS_CTRL_AP_MODE_APB2_SPI2_AUTOMATIC (0<<14)
+#define SYS_CTRL_AP_MODE_APB2_SPI2_MANUAL (1<<14)
+#define SYS_CTRL_AP_MODE_APB2_SPI3_AUTOMATIC (0<<15)
+#define SYS_CTRL_AP_MODE_APB2_SPI3_MANUAL (1<<15)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC1_AUTOMATIC (0<<16)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC1_MANUAL (1<<16)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC2_AUTOMATIC (0<<17)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC2_MANUAL (1<<17)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC3_AUTOMATIC (0<<18)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC3_MANUAL (1<<18)
+#define SYS_CTRL_AP_MODE_CLK_APB2(n) (((n)&0x7FFFF)<<0)
+#define SYS_CTRL_AP_MODE_CLK_APB2_MASK (0x7FFFF<<0)
+#define SYS_CTRL_AP_MODE_CLK_APB2_SHIFT (0)
+
+//Clk_APB2_Enable
+#define SYS_CTRL_AP_ENABLE_APB2_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC (1<<1)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH0 (1<<2)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH1 (1<<3)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH2 (1<<4)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH3 (1<<5)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH4 (1<<6)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH5 (1<<7)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH6 (1<<8)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH7 (1<<9)
+#define SYS_CTRL_AP_ENABLE_APB2_UART1 (1<<10)
+#define SYS_CTRL_AP_ENABLE_APB2_UART2 (1<<11)
+#define SYS_CTRL_AP_ENABLE_APB2_UART3 (1<<12)
+#define SYS_CTRL_AP_ENABLE_APB2_SPI1 (1<<13)
+#define SYS_CTRL_AP_ENABLE_APB2_SPI2 (1<<14)
+#define SYS_CTRL_AP_ENABLE_APB2_SPI3 (1<<15)
+#define SYS_CTRL_AP_ENABLE_APB2_SDMMC1 (1<<16)
+#define SYS_CTRL_AP_ENABLE_APB2_SDMMC2 (1<<17)
+#define SYS_CTRL_AP_ENABLE_APB2_SDMMC3 (1<<18)
+#define SYS_CTRL_AP_ENABLE_APB2_ALWAYS (1<<19)
+#define SYS_CTRL_AP_ENABLE_APB2_NANDFLASH (1<<20)
+#define SYS_CTRL_AP_ENABLE_CLK_APB2(n) (((n)&0x1FFFFF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APB2_MASK (0x1FFFFF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APB2_SHIFT (0)
+
+//Clk_APB2_Disable
+#define SYS_CTRL_AP_DISABLE_APB2_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC (1<<1)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH0 (1<<2)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH1 (1<<3)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH2 (1<<4)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH3 (1<<5)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH4 (1<<6)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH5 (1<<7)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH6 (1<<8)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH7 (1<<9)
+#define SYS_CTRL_AP_DISABLE_APB2_UART1 (1<<10)
+#define SYS_CTRL_AP_DISABLE_APB2_UART2 (1<<11)
+#define SYS_CTRL_AP_DISABLE_APB2_UART3 (1<<12)
+#define SYS_CTRL_AP_DISABLE_APB2_SPI1 (1<<13)
+#define SYS_CTRL_AP_DISABLE_APB2_SPI2 (1<<14)
+#define SYS_CTRL_AP_DISABLE_APB2_SPI3 (1<<15)
+#define SYS_CTRL_AP_DISABLE_APB2_SDMMC1 (1<<16)
+#define SYS_CTRL_AP_DISABLE_APB2_SDMMC2 (1<<17)
+#define SYS_CTRL_AP_DISABLE_APB2_SDMMC3 (1<<18)
+#define SYS_CTRL_AP_DISABLE_APB2_ALWAYS (1<<19)
+#define SYS_CTRL_AP_DISABLE_APB2_NANDFLASH (1<<20)
+#define SYS_CTRL_AP_DISABLE_CLK_APB2(n) (((n)&0x1FFFFF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APB2_MASK (0x1FFFFF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APB2_SHIFT (0)
+
+//Clk_MEM_Mode
+#define SYS_CTRL_AP_MODE_CLK_MEM_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_CLK_MEM_MANUAL (1<<0)
+
+//Clk_MEM_Enable
+#define SYS_CTRL_AP_ENABLE_MEM_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_MEM_DMC  (1<<1)
+#define SYS_CTRL_AP_ENABLE_MEM_GPU  (1<<2)
+#define SYS_CTRL_AP_ENABLE_MEM_VPU  (1<<3)
+#define SYS_CTRL_AP_ENABLE_MEM_DDRPHY_P (1<<4)
+#define SYS_CTRL_AP_ENABLE_MEM_CONNECT (1<<5)
+#define SYS_CTRL_AP_ENABLE_CLK_MEM(n) (((n)&0x3F)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_MEM_MASK (0x3F<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_MEM_SHIFT (0)
+
+//Clk_MEM_Disable
+#define SYS_CTRL_AP_DISABLE_MEM_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_MEM_DMC (1<<1)
+#define SYS_CTRL_AP_DISABLE_MEM_GPU (1<<2)
+#define SYS_CTRL_AP_DISABLE_MEM_VPU (1<<3)
+#define SYS_CTRL_AP_DISABLE_MEM_DDRPHY_P (1<<4)
+#define SYS_CTRL_AP_DISABLE_MEM_CONNECT (1<<5)
+#define SYS_CTRL_AP_DISABLE_CLK_MEM(n) (((n)&0x3F)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_MEM_MASK (0x3F<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_MEM_SHIFT (0)
+
+//Clk_APO_Mode
+#define SYS_CTRL_AP_MODE_APOC_VPU_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_APOC_VPU_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_APOC_BCK_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_APOC_BCK_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_APOC_UART1_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_APOC_UART1_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_APOC_UART2_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_APOC_UART2_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_APOC_UART3_AUTOMATIC (0<<4)
+#define SYS_CTRL_AP_MODE_APOC_UART3_MANUAL (1<<4)
+#define SYS_CTRL_AP_MODE_APOC_VOC_CORE_AUTOMATIC (0<<5)
+#define SYS_CTRL_AP_MODE_APOC_VOC_CORE_MANUAL (1<<5)
+#define SYS_CTRL_AP_MODE_APOC_VOC_AUTOMATIC (0<<6)
+#define SYS_CTRL_AP_MODE_APOC_VOC_MANUAL (1<<6)
+#define SYS_CTRL_AP_MODE_CLK_APO(n) (((n)&0x7F)<<0)
+#define SYS_CTRL_AP_MODE_CLK_APO_MASK (0x7F<<0)
+#define SYS_CTRL_AP_MODE_CLK_APO_SHIFT (0)
+
+//Clk_APO_Enable
+#define SYS_CTRL_AP_ENABLE_APOC_VPU (1<<0)
+#define SYS_CTRL_AP_ENABLE_APOC_BCK (1<<1)
+#define SYS_CTRL_AP_ENABLE_APOC_UART1 (1<<2)
+#define SYS_CTRL_AP_ENABLE_APOC_UART2 (1<<3)
+#define SYS_CTRL_AP_ENABLE_APOC_UART3 (1<<4)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC_CORE (1<<5)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC (1<<6)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC_ALWAYS (1<<7)
+#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY_N (1<<8)
+#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY2XP (1<<9)
+#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY2XN (1<<10)
+#define SYS_CTRL_AP_ENABLE_APOC_GPU (1<<11)
+#define SYS_CTRL_AP_ENABLE_APOC_USBPHY (1<<12)
+#define SYS_CTRL_AP_ENABLE_APOC_CSI (1<<13)
+#define SYS_CTRL_AP_ENABLE_APOC_DSI (1<<14)
+#define SYS_CTRL_AP_ENABLE_APOC_GPIO (1<<15)
+#define SYS_CTRL_AP_ENABLE_APOC_SPIFLASH (1<<16)
+#define SYS_CTRL_AP_ENABLE_APOC_PIX (1<<17)
+#define SYS_CTRL_AP_ENABLE_APOC_PDGB (1<<18)
+#define SYS_CTRL_AP_ENABLE_CLK_APO(n) (((n)&0x7FFFF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APO_MASK (0x7FFFF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APO_SHIFT (0)
+
+//Clk_APO_Disable
+#define SYS_CTRL_AP_DISABLE_APOC_VPU (1<<0)
+#define SYS_CTRL_AP_DISABLE_APOC_BCK (1<<1)
+#define SYS_CTRL_AP_DISABLE_APOC_UART1 (1<<2)
+#define SYS_CTRL_AP_DISABLE_APOC_UART2 (1<<3)
+#define SYS_CTRL_AP_DISABLE_APOC_UART3 (1<<4)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC_CORE (1<<5)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC (1<<6)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC_ALWAYS (1<<7)
+#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY_N (1<<8)
+#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY2XP (1<<9)
+#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY2XN (1<<10)
+#define SYS_CTRL_AP_DISABLE_APOC_GPU (1<<11)
+#define SYS_CTRL_AP_DISABLE_APOC_USBPHY (1<<12)
+#define SYS_CTRL_AP_DISABLE_APOC_CSI (1<<13)
+#define SYS_CTRL_AP_DISABLE_APOC_DSI (1<<14)
+#define SYS_CTRL_AP_DISABLE_APOC_GPIO (1<<15)
+#define SYS_CTRL_AP_DISABLE_APOC_SPIFLASH (1<<16)
+#define SYS_CTRL_AP_DISABLE_APOC_PIX (1<<17)
+#define SYS_CTRL_AP_DISABLE_APOC_PDGB (1<<18)
+#define SYS_CTRL_AP_DISABLE_CLK_APO(n) (((n)&0x7FFFF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APO_MASK (0x7FFFF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APO_SHIFT (0)
+
+//Cfg_Clk_AP_CPU
+#define SYS_CTRL_AP_AP_CPU_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_BUS_DIV_SEL(n)  (((n)&3)<<16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_MASK (3<<16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_SHIFT (16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_DIV2 (0<<16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_DIV3 (1<<16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_DIV4 (2<<16)
+#define SYS_CTRL_AP_AP_CPU_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_AXI
+#define SYS_CTRL_AP_AP_AXI_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_AXI_SRC_SEL  (1<<12)
+#define SYS_CTRL_AP_AP_AXI_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_GCG
+#define SYS_CTRL_AP_AP_GCG_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_GCG_SRC_SEL  (1<<12)
+#define SYS_CTRL_AP_AP_GCG_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_AHB1
+#define SYS_CTRL_AP_AP_AHB1_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_AHB1_SRC_SEL (1<<12)
+#define SYS_CTRL_AP_AP_AHB1_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_APB1
+#define SYS_CTRL_AP_AP_APB1_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_APB1_SRC_SEL (1<<12)
+#define SYS_CTRL_AP_AP_APB1_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_APB2
+#define SYS_CTRL_AP_AP_APB2_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_APB2_SRC_SEL (1<<12)
+#define SYS_CTRL_AP_AP_APB2_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_MEM
+#define SYS_CTRL_AP_AP_MEM_SRC_DIV2 (1<<12)
+
+//Cfg_Clk_AP_GPU
+#define SYS_CTRL_AP_AP_GPU_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_GPU_SRC_DIV2 (1<<12)
+#define SYS_CTRL_AP_AP_GPU_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_VPU
+#define SYS_CTRL_AP_AP_VPU_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_VPU_SRC_DIV2 (1<<12)
+#define SYS_CTRL_AP_AP_VPU_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_VOC
+#define SYS_CTRL_AP_AP_VOC_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_VOC_SRC_DIV2 (1<<12)
+#define SYS_CTRL_AP_AP_VOC_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_SFLSH
+#define SYS_CTRL_AP_AP_SFLSH_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_SFLSH_SRC_DIV2 (1<<12)
+#define SYS_CTRL_AP_AP_SFLSH_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_Uart
+#define SYS_CTRL_AP_UART_DIVIDER(n) (((n)&0x3FF)<<0)
+#define SYS_CTRL_AP_UART_DIVIDER_MASK (0x3FF<<0)
+#define SYS_CTRL_AP_UART_DIVIDER_SHIFT (0)
+#define SYS_CTRL_AP_UART_SEL_PLL_SLOW (0<<12)
+#define SYS_CTRL_AP_UART_SEL_PLL_PLL (1<<12)
+
+//L2cc_Ctrl
+#define SYS_CTRL_AP_ARQOS_L2CC_1_M(n) (((n)&15)<<0)
+#define SYS_CTRL_AP_ARQOS_L2CC_1_M_MASK (15<<0)
+#define SYS_CTRL_AP_ARQOS_L2CC_1_M_SHIFT (0)
+#define SYS_CTRL_AP_AWQOS_L2CC_1_M(n) (((n)&15)<<4)
+#define SYS_CTRL_AP_AWQOS_L2CC_1_M_MASK (15<<4)
+#define SYS_CTRL_AP_AWQOS_L2CC_1_M_SHIFT (4)
+#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M(n) (((n)&15)<<8)
+#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M_MASK (15<<8)
+#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M_SHIFT (8)
+#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M(n) (((n)&15)<<12)
+#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M_MASK (15<<12)
+#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M_SHIFT (12)
+#define SYS_CTRL_AP_ARAP_L2CC_1_M   (1<<16)
+#define SYS_CTRL_AP_AWAP_L2CC_1_M   (1<<17)
+#define SYS_CTRL_AP_ARAP_MODEM_MEM_AHBS_M (1<<18)
+#define SYS_CTRL_AP_AWAP_MODEM_MEM_AHBS_M (1<<19)
+#define SYS_CTRL_AP_ARAP_MERGE1M    (1<<20)
+#define SYS_CTRL_AP_AWAP_MERGE1M    (1<<21)
+#define SYS_CTRL_AP_ARAP_MERGE2M    (1<<22)
+#define SYS_CTRL_AP_AWAP_MERGE2M    (1<<23)
+#define SYS_CTRL_AP_RESERVE1(n)     (((n)&0xFF)<<24)
+#define SYS_CTRL_AP_RESERVE1_MASK   (0xFF<<24)
+#define SYS_CTRL_AP_RESERVE1_SHIFT  (24)
+
+//Spi_Ctrl
+#define SYS_CTRL_AP_LIMITED_EN_SPI1 (1<<0)
+#define SYS_CTRL_AP_LPSEN_SPI1      (1<<1)
+#define SYS_CTRL_AP_LIMITED_EN_SPI2 (1<<2)
+#define SYS_CTRL_AP_LPSEN_SPI2      (1<<3)
+#define SYS_CTRL_AP_LIMITED_EN_SPI3 (1<<4)
+#define SYS_CTRL_AP_LPSEN_SPI3      (1<<5)
+#define SYS_CTRL_AP_FBUSWID_NFSC    (1<<6)
+#define SYS_CTRL_AP_RESERVE3        (1<<7)
+#define SYS_CTRL_AP_DMC_CFG(n)      (((n)&0x3FF)<<8)
+#define SYS_CTRL_AP_DMC_CFG_MASK    (0x3FF<<8)
+#define SYS_CTRL_AP_DMC_CFG_SHIFT   (8)
+#define SYS_CTRL_AP_RESERVE2(n)     (((n)&0x3FFF)<<18)
+#define SYS_CTRL_AP_RESERVE2_MASK   (0x3FFF<<18)
+#define SYS_CTRL_AP_RESERVE2_SHIFT  (18)
+
+//Memory_Margin
+#define SYS_CTRL_AP_EMAW_VOC(n)     (((n)&3)<<0)
+#define SYS_CTRL_AP_EMAW_VOC_MASK   (3<<0)
+#define SYS_CTRL_AP_EMAW_VOC_SHIFT  (0)
+#define SYS_CTRL_AP_EMA_VOC(n)      (((n)&7)<<2)
+#define SYS_CTRL_AP_EMA_VOC_MASK    (7<<2)
+#define SYS_CTRL_AP_EMA_VOC_SHIFT   (2)
+#define SYS_CTRL_AP_EMAW_VPU(n)     (((n)&3)<<5)
+#define SYS_CTRL_AP_EMAW_VPU_MASK   (3<<5)
+#define SYS_CTRL_AP_EMAW_VPU_SHIFT  (5)
+#define SYS_CTRL_AP_EMA_VPU(n)      (((n)&7)<<7)
+#define SYS_CTRL_AP_EMA_VPU_MASK    (7<<7)
+#define SYS_CTRL_AP_EMA_VPU_SHIFT   (7)
+#define SYS_CTRL_AP_EMAW_GPU(n)     (((n)&3)<<10)
+#define SYS_CTRL_AP_EMAW_GPU_MASK   (3<<10)
+#define SYS_CTRL_AP_EMAW_GPU_SHIFT  (10)
+#define SYS_CTRL_AP_EMA_GPU(n)      (((n)&7)<<12)
+#define SYS_CTRL_AP_EMA_GPU_MASK    (7<<12)
+#define SYS_CTRL_AP_EMA_GPU_SHIFT   (12)
+#define SYS_CTRL_AP_EMAW_GOUDA(n)   (((n)&3)<<15)
+#define SYS_CTRL_AP_EMAW_GOUDA_MASK (3<<15)
+#define SYS_CTRL_AP_EMAW_GOUDA_SHIFT (15)
+#define SYS_CTRL_AP_EMA_GOUDA(n)    (((n)&7)<<17)
+#define SYS_CTRL_AP_EMA_GOUDA_MASK  (7<<17)
+#define SYS_CTRL_AP_EMA_GOUDA_SHIFT (17)
+#define SYS_CTRL_AP_EMAW_IMEM(n)    (((n)&3)<<20)
+#define SYS_CTRL_AP_EMAW_IMEM_MASK  (3<<20)
+#define SYS_CTRL_AP_EMAW_IMEM_SHIFT (20)
+#define SYS_CTRL_AP_EMA_IMEM(n)     (((n)&7)<<22)
+#define SYS_CTRL_AP_EMA_IMEM_MASK   (7<<22)
+#define SYS_CTRL_AP_EMA_IMEM_SHIFT  (22)
+#define SYS_CTRL_AP_EMAW_USB(n)     (((n)&3)<<25)
+#define SYS_CTRL_AP_EMAW_USB_MASK   (3<<25)
+#define SYS_CTRL_AP_EMAW_USB_SHIFT  (25)
+#define SYS_CTRL_AP_EMA_USB(n)      (((n)&7)<<27)
+#define SYS_CTRL_AP_EMA_USB_MASK    (7<<27)
+#define SYS_CTRL_AP_EMA_USB_SHIFT   (27)
+
+//Memory_Margin2
+#define SYS_CTRL_AP_EMAW_NFSC(n)    (((n)&3)<<0)
+#define SYS_CTRL_AP_EMAW_NFSC_MASK  (3<<0)
+#define SYS_CTRL_AP_EMAW_NFSC_SHIFT (0)
+#define SYS_CTRL_AP_EMA_NFSC(n)     (((n)&7)<<2)
+#define SYS_CTRL_AP_EMA_NFSC_MASK   (7<<2)
+#define SYS_CTRL_AP_EMA_NFSC_SHIFT  (2)
+#define SYS_CTRL_AP_EMA_VPUROM(n)   (((n)&7)<<5)
+#define SYS_CTRL_AP_EMA_VPUROM_MASK (7<<5)
+#define SYS_CTRL_AP_EMA_VPUROM_SHIFT (5)
+#define SYS_CTRL_AP_EMA_IMEMROM(n)  (((n)&7)<<8)
+#define SYS_CTRL_AP_EMA_IMEMROM_MASK (7<<8)
+#define SYS_CTRL_AP_EMA_IMEMROM_SHIFT (8)
+#define SYS_CTRL_AP_KEN_VPUROM      (1<<11)
+#define SYS_CTRL_AP_PGEN_VPUROM     (1<<12)
+#define SYS_CTRL_AP_KEN_IMEMROM     (1<<13)
+#define SYS_CTRL_AP_PGEN_IMEMROM    (1<<14)
+
+//Memory_Observe
+#define SYS_CTRL_AP_MEM_OBSERVE(n)  (((n)&0xFFFFFFFF)<<0)
+
+//Cfg_Reserve
+#define SYS_CTRL_AP_RESERVE(n)      (((n)&0xFFFFFFFF)<<0)
+
+#endif
diff --git a/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8810e.h b/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8810e.h
new file mode 100644
index 0000000000..ab7ba4c951
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8810e.h
@@ -0,0 +1,1578 @@
+#ifndef _REG_SYSCTRL_H_
+#define _REG_SYSCTRL_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+
+// ============================================================================
+// AP_CPU_ID_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// CPU IDs
+    CPU0                                        = 0x00000000,
+    CPU1                                        = 0x00000001
+} AP_CPU_ID_T;
+
+
+// ============================================================================
+// CPU_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP CPU side System clocks
+    CPU_CORE                                    = 0x00000000,
+/// the following don't have an auto enable
+    CPU_DUMMY                                   = 0x00000001
+} CPU_CLKS_T;
+
+#define NB_CPU_CLK_AEN                           (1)
+#define NB_CPU_CLK_EN                            (2)
+#define NB_CPU_CLK                               (2)
+
+// ============================================================================
+// AXI_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AXI side System clocks: AXI and AHB0 and APB0
+    AHB0_CONF                                   = 0x00000000,
+    APB0_CONF                                   = 0x00000001,
+    AXI_VOC                                     = 0x00000002,
+    AXI_DMA                                     = 0x00000003,
+/// the following don't have an auto enable
+    AXI_ALWAYS                                  = 0x00000004,
+    AXI_CONNECT                                 = 0x00000005,
+    APB0_IRQ                                    = 0x00000006
+} AXI_CLKS_T;
+
+#define NB_AXI_CLK_AEN                           (4)
+#define NB_AXI_CLK_EN                            (7)
+#define NB_AXI_CLK                               (7)
+
+// ============================================================================
+// AXIDIV2_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AXIdiv2 side System clocks
+    AXIDIV2_IMEM                                = 0x00000000,
+/// the following don't have an auto enable
+    AXIDIV2_ALWAYS                              = 0x00000001,
+    AXIDIV2_CONNECT                             = 0x00000002,
+    AXIDIV2_VPU                                 = 0x00000003
+} AXIDIV2_CLKS_T;
+
+#define NB_AXIDIV2_CLK_AEN                       (1)
+#define NB_AXIDIV2_CLK_EN                        (4)
+#define NB_AXIDIV2_CLK                           (4)
+
+// ============================================================================
+// GCG_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP GCG side System clocks
+    GCG_APB_CONF                                = 0x00000000,
+    GCG_GOUDA                                   = 0x00000001,
+    GCG_CAMERA                                  = 0x00000002,
+/// the following don't have an auto enable
+    GCG_ALWAYS                                  = 0x00000003,
+    GCG_CONNECT                                 = 0x00000004
+} GCG_CLKS_T;
+
+#define NB_GCG_CLK_AEN                           (3)
+#define NB_GCG_CLK_EN                            (5)
+#define NB_GCG_CLK                               (5)
+
+// ============================================================================
+// AHB1_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AHB1 side System clocks
+    AHB1_USBC                                   = 0x00000000,
+/// the following don't have an auto enable
+    AHB1_ALWAYS                                 = 0x00000001,
+    AHB1_SPIFLASH                               = 0x00000002
+} AHB1_CLKS_T;
+
+#define NB_AHB1_CLK_AEN                          (1)
+#define NB_AHB1_CLK_EN                           (3)
+#define NB_AHB1_CLK                              (3)
+
+// ============================================================================
+// APB1_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP APB1 side System clocks
+    APB1_CONF                                   = 0x00000000,
+    APB1_AIF                                    = 0x00000001,
+    APB1_AUIFC                                  = 0x00000002,
+    APB1_AUIFC_CH0                              = 0x00000003,
+    APB1_AUIFC_CH1                              = 0x00000004,
+    APB1_I2C1                                   = 0x00000005,
+    APB1_I2C2                                   = 0x00000006,
+    APB1_I2C3                                   = 0x00000007,
+/// AP APB1 side divided clock (either divided by module or by clock_ctrl)
+    APB1D_OSC                                   = 0x00000008,
+    APB1D_PWM                                   = 0x00000009,
+/// the following don't have an auto enable
+    APB1_ALWAYS                                 = 0x0000000A,
+    APB1_DAPLITE                                = 0x0000000B,
+    APB1_TIMER                                  = 0x0000000C,
+    APB1_GPIO                                   = 0x0000000D
+} APB1_CLKS_T;
+
+#define NB_APB1_CLK_AEN                          (10)
+#define NB_APB1_CLK_EN                           (14)
+#define NB_APB1_CLK                              (14)
+
+// ============================================================================
+// APB2_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP APB2 side System clocks
+    APB2_CONF                                   = 0x00000000,
+    APB2_IFC                                    = 0x00000001,
+    APB2_IFC_CH0                                = 0x00000002,
+    APB2_IFC_CH1                                = 0x00000003,
+    APB2_IFC_CH2                                = 0x00000004,
+    APB2_IFC_CH3                                = 0x00000005,
+    APB2_IFC_CH4                                = 0x00000006,
+    APB2_IFC_CH5                                = 0x00000007,
+    APB2_IFC_CH6                                = 0x00000008,
+    APB2_IFC_CH7                                = 0x00000009,
+    APB2_UART1                                  = 0x0000000A,
+    APB2_UART2                                  = 0x0000000B,
+    APB2_UART3                                  = 0x0000000C,
+    APB2_SPI1                                   = 0x0000000D,
+    APB2_SPI2                                   = 0x0000000E,
+    APB2_SPI3                                   = 0x0000000F,
+    APB2_SDMMC1                                 = 0x00000010,
+    APB2_SDMMC2                                 = 0x00000011,
+    APB2_SDMMC3                                 = 0x00000012,
+/// the following don't have an auto enable
+    APB2_ALWAYS                                 = 0x00000013,
+    APB2_NANDFLASH                              = 0x00000014
+} APB2_CLKS_T;
+
+#define NB_APB2_CLK_AEN                          (19)
+#define NB_APB2_CLK_EN                           (21)
+#define NB_APB2_CLK                              (21)
+
+// ============================================================================
+// MEM_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP MEM side System clocks
+    MEM_CONF                                    = 0x00000000,
+/// the following don't have an auto enable
+    MEM_DMC                                     = 0x00000001,
+    MEM_GPU                                     = 0x00000002,
+    MEM_VPU                                     = 0x00000003,
+    MEM_DDRPHY_P                                = 0x00000004,
+    MEM_CONNECT                                 = 0x00000005
+} MEM_CLKS_T;
+
+#define NB_MEM_CLK_AEN                           (1)
+#define NB_MEM_CLK_EN                            (6)
+#define NB_MEM_CLK                               (6)
+
+// ============================================================================
+// APO_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP side Other clocks
+/// clocks with auto enble
+    APOC_VPU                                    = 0x00000000,
+    APOC_BCK                                    = 0x00000001,
+    APOC_UART1                                  = 0x00000002,
+    APOC_UART2                                  = 0x00000003,
+    APOC_UART3                                  = 0x00000004,
+    APOC_VOC_CORE                               = 0x00000005,
+    APOC_VOC                                    = 0x00000006,
+/// the following don't have an auto enable
+    APOC_VOC_ALWAYS                             = 0x00000007,
+    APOC_DDRPHY_N                               = 0x00000008,
+    APOC_DDRPHY2XP                              = 0x00000009,
+    APOC_DDRPHY2XN                              = 0x0000000A,
+    APOC_GPU                                    = 0x0000000B,
+    APOC_USBPHY                                 = 0x0000000C,
+    APOC_CSI                                    = 0x0000000D,
+    APOC_DSI                                    = 0x0000000E,
+    APOC_GPIO                                   = 0x0000000F,
+    APOC_SPIFLASH                               = 0x00000010,
+    APOC_PIX                                    = 0x00000011,
+    APOC_PDGB                                   = 0x00000012
+} APO_CLKS_T;
+
+#define NB_CLK_VOC_AEN_SYNC                      (5)
+#define NB_CLK_VOC_CORE                          (6)
+#define NB_APO_CLK_AEN                           (7)
+#define NB_CLK_VOC_END                           (8)
+#define NB_APO_CLK_EN                            (19)
+#define NB_APO_CLK                               (19)
+
+// ============================================================================
+// CPU_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP CPU side resets
+    CPU_RST_CORE                                = 0x00000000,
+    CPU_RST_SYS                                 = 0x00000001
+} CPU_RESETS_T;
+
+#define NB_CPU_RST                               (2)
+
+// ============================================================================
+// AXI_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AXI side resets: AXI and AHB0 and APB0
+    AXI_RST_VOC                                 = 0x00000000,
+    AXI_RST_DMA                                 = 0x00000001,
+    AXI_RST_SYS                                 = 0x00000002,
+    AXI_RST_CONNECT                             = 0x00000003,
+    AHB0_RST_GPU                                = 0x00000004,
+    APB0_RST_VPU                                = 0x00000005,
+    APB0_RST_IRQ                                = 0x00000006
+} AXI_RESETS_T;
+
+#define NB_AXI_RST                               (7)
+
+// ============================================================================
+// AXIDIV2_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AXIDIV2 side resets
+    AXIDIV2_RST_IMEM                            = 0x00000000,
+    AXIDIV2_RST_SYS                             = 0x00000001,
+    AXIDIV2_RST_VPU                             = 0x00000002
+} AXIDIV2_RESETS_T;
+
+#define NB_AXIDIV2_RST                           (3)
+
+// ============================================================================
+// GCG_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP GCG side resets
+    GCG_RST_SYS                                 = 0x00000000,
+    GCG_RST_GOUDA                               = 0x00000001,
+    GCG_RST_CAMERA                              = 0x00000002
+} GCG_RESETS_T;
+
+#define NB_GCG_RST                               (3)
+
+// ============================================================================
+// AHB1_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AHB1 side resets
+    AHB1_RST_SYS                                = 0x00000000,
+    AHB1_RST_USBC                               = 0x00000001,
+    AHB1_RST_SPIFLASH                           = 0x00000002
+} AHB1_RESETS_T;
+
+#define NB_AHB1_RST                              (3)
+
+// ============================================================================
+// APB1_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP APB1 side resets
+    APB1_RST_SYS                                = 0x00000000,
+    APB1_RST_TIMER                              = 0x00000001,
+    APB1_RST_KEYPAD                             = 0x00000002,
+    APB1_RST_GPIO                               = 0x00000003,
+    APB1_RST_PWM                                = 0x00000004,
+    APB1_RST_AIF                                = 0x00000005,
+    APB1_RST_AUIFC                              = 0x00000006,
+    APB1_RST_I2C1                               = 0x00000007,
+    APB1_RST_I2C2                               = 0x00000008,
+    APB1_RST_I2C3                               = 0x00000009,
+    APB1_RST_COM_REGS                           = 0x0000000A,
+    APB1_RST_DMC                                = 0x0000000B,
+    APB1_RST_DDRPHY_P                           = 0x0000000C,
+    APB1_RST_BB2G_XCPU                          = 0x0000000D,
+    APB1_RST_BB2G_BCPU                          = 0x0000000E,
+    APB1_RST_BB2G_AHBC                          = 0x0000000F,
+    APB1_RST_BB2G_DMA                           = 0x00000010,
+    APB1_RST_BB2G_A2A                           = 0x00000011,
+    APB1_RST_BB2G_XIFC                          = 0x00000012,
+    APB1_RST_BB2G_BIFC                          = 0x00000013,
+    APB1_RST_BB2G_BAHBC                         = 0x00000014,
+    APB1_RST_BB2G_MEM_BRIDGE                    = 0x00000015
+} APB1_RESETS_T;
+
+#define NB_APB1_RST                              (22)
+
+// ============================================================================
+// APB2_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP APB2 side resets
+    APB2_RST_SYS                                = 0x00000000,
+    APB2_RST_IFC                                = 0x00000001,
+    APB2_RST_UART1                              = 0x00000002,
+    APB2_RST_UART2                              = 0x00000003,
+    APB2_RST_UART3                              = 0x00000004,
+    APB2_RST_SPI1                               = 0x00000005,
+    APB2_RST_SPI2                               = 0x00000006,
+    APB2_RST_SPI3                               = 0x00000007,
+    APB2_RST_SDMMC1                             = 0x00000008,
+    APB2_RST_SDMMC2                             = 0x00000009,
+    APB2_RST_SDMMC3                             = 0x0000000A,
+    APB2_RST_NANDFLASH                          = 0x0000000B
+} APB2_RESETS_T;
+
+#define NB_APB2_RST                              (12)
+
+// ============================================================================
+// MEM_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP MEM side resets
+    MEM_RST_SYS                                 = 0x00000000,
+    MEM_RST_GPU                                 = 0x00000001,
+    MEM_RST_VPU                                 = 0x00000002,
+    MEM_RST_DMC                                 = 0x00000003,
+    MEM_RST_DDRPHY_P                            = 0x00000004
+} MEM_RESETS_T;
+
+#define NB_MEM_RST                               (5)
+
+// ============================================================================
+// AP_OTHERS_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP Reset Other : resync on corresponding clock other
+    AP_RSTO_VOC                                 = 0x00000000,
+    AP_RSTO_DDRPHY_N                            = 0x00000001,
+    AP_RSTO_DDRPHY2XP                           = 0x00000002,
+    AP_RSTO_DDRPHY2XN                           = 0x00000003,
+    AP_RSTO_GPU                                 = 0x00000004,
+    AP_RSTO_VPU                                 = 0x00000005,
+    AP_RSTO_BCK                                 = 0x00000006,
+    AP_RSTO_UART1                               = 0x00000007,
+    AP_RSTO_UART2                               = 0x00000008,
+    AP_RSTO_UART3                               = 0x00000009,
+    AP_RSTO_GPIO                                = 0x0000000A,
+    AP_RSTO_TIMER                               = 0x0000000B,
+    AP_RSTO_USBC                                = 0x0000000C,
+    AP_RSTO_DSI                                 = 0x0000000D,
+    AP_RSTO_SPIFLASH                            = 0x0000000E,
+    AP_RSTO_TCK                                 = 0x0000000F,
+    AP_RSTO_PDBG_XTAL                           = 0x00000010
+} AP_OTHERS_RESETS_T;
+
+#define NB_AP_RSTO                               (17)
+/// For REG_DBG protect lock/unlock value
+#define AP_CTRL_PROTECT_LOCK                     (0XA50000)
+#define AP_CTRL_PROTECT_UNLOCK                   (0XA50001)
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+// ============================================================================
+// SYS_CTRL_AP_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef volatile struct
+{
+    /// <strong>This register is used to Lock and Unlock the protected registers.</strong>
+    REG32                          REG_DBG;                      //0x00000000
+    /// Register protected by Write_Unlocked_H.
+    REG32                          Cfg_Pll_Ctrl[4];              //0x00000004
+    /// This register is protected.
+    REG32                          Sel_Clock;                    //0x00000014
+    REG32                          Reset_Cause;                  //0x00000018
+    /// This register is protected.
+    REG32                          CPU_Rst_Set;                  //0x0000001C
+    REG32                          CPU_Rst_Clr;                  //0x00000020
+    /// This register is protected.
+    REG32                          AXI_Rst_Set;                  //0x00000024
+    REG32                          AXI_Rst_Clr;                  //0x00000028
+    /// This register is protected.
+    REG32                          AXIDIV2_Rst_Set;              //0x0000002C
+    REG32                          AXIDIV2_Rst_Clr;              //0x00000030
+    /// This register is protected.
+    REG32                          GCG_Rst_Set;                  //0x00000034
+    REG32                          GCG_Rst_Clr;                  //0x00000038
+    /// This register is protected.
+    REG32                          AHB1_Rst_Set;                 //0x0000003C
+    REG32                          AHB1_Rst_Clr;                 //0x00000040
+    /// This register is protected.
+    REG32                          APB1_Rst_Set;                 //0x00000044
+    REG32                          APB1_Rst_Clr;                 //0x00000048
+    /// This register is protected.
+    REG32                          APB2_Rst_Set;                 //0x0000004C
+    REG32                          APB2_Rst_Clr;                 //0x00000050
+    /// This register is protected.
+    REG32                          MEM_Rst_Set;                  //0x00000054
+    REG32                          MEM_Rst_Clr;                  //0x00000058
+    REG32                          Clk_CPU_Mode;                 //0x0000005C
+    REG32                          Clk_CPU_Enable;               //0x00000060
+    /// This register is protected.
+    REG32                          Clk_CPU_Disable;              //0x00000064
+    REG32                          Clk_AXI_Mode;                 //0x00000068
+    REG32                          Clk_AXI_Enable;               //0x0000006C
+    /// This register is protected.
+    REG32                          Clk_AXI_Disable;              //0x00000070
+    REG32                          Clk_AXIDIV2_Mode;             //0x00000074
+    REG32                          Clk_AXIDIV2_Enable;           //0x00000078
+    /// This register is protected.
+    REG32                          Clk_AXIDIV2_Disable;          //0x0000007C
+    REG32                          Clk_GCG_Mode;                 //0x00000080
+    REG32                          Clk_GCG_Enable;               //0x00000084
+    /// This register is protected.
+    REG32                          Clk_GCG_Disable;              //0x00000088
+    REG32                          Clk_AHB1_Mode;                //0x0000008C
+    REG32                          Clk_AHB1_Enable;              //0x00000090
+    /// This register is protected.
+    REG32                          Clk_AHB1_Disable;             //0x00000094
+    REG32                          Clk_APB1_Mode;                //0x00000098
+    REG32                          Clk_APB1_Enable;              //0x0000009C
+    /// This register is protected.
+    REG32                          Clk_APB1_Disable;             //0x000000A0
+    REG32                          Clk_APB2_Mode;                //0x000000A4
+    REG32                          Clk_APB2_Enable;              //0x000000A8
+    /// This register is protected.
+    REG32                          Clk_APB2_Disable;             //0x000000AC
+    REG32                          Clk_MEM_Mode;                 //0x000000B0
+    REG32                          Clk_MEM_Enable;               //0x000000B4
+    /// This register is protected.
+    REG32                          Clk_MEM_Disable;              //0x000000B8
+    REG32                          Clk_APO_Mode;                 //0x000000BC
+    REG32                          Clk_APO_Enable;               //0x000000C0
+    /// This register is protected.
+    REG32                          Clk_APO_Disable;              //0x000000C4
+    REG32                          Cfg_Clk_AP_CPU;               //0x000000C8
+    REG32                          Cfg_Clk_AP_AXI;               //0x000000CC
+    REG32                          Cfg_Clk_AP_GCG;               //0x000000D0
+    REG32                          Cfg_Clk_AP_AHB1;              //0x000000D4
+    REG32                          Cfg_Clk_AP_APB1;              //0x000000D8
+    REG32                          Cfg_Clk_AP_APB2;              //0x000000DC
+    REG32                          Cfg_Clk_AP_MEM;               //0x000000E0
+    REG32                          Cfg_Clk_AP_GPU;               //0x000000E4
+    REG32                          Cfg_Clk_AP_VPU;               //0x000000E8
+    REG32                          Cfg_Clk_AP_VOC;               //0x000000EC
+    REG32                          Cfg_Clk_AP_SFLSH;             //0x000000F0
+    REG32                          Cfg_Clk_Uart[3];              //0x000000F4
+    REG32                          L2cc_Ctrl;                    //0x00000100
+    REG32                          Spi_Ctrl;                     //0x00000104
+    REG32                          Memory_Margin;                //0x00000108
+    REG32                          Memory_Margin2;               //0x0000010C
+    REG32                          Memory_Observe;               //0x00000110
+    REG32                          Cfg_Clk_AP_VOC2;               //0x00000114
+    REG32                          Cfg_Clk_EMMC;               //0x00000118
+    REG32                          Test_Pulse;               //0x0000011C
+    REG32 Reserved_00000114[49];                //0x00000120
+    /// This register is reserved.
+    REG32                          Cfg_Cpu_Reserve0;                  //0x000001E4
+    REG32                          Cfg_Cpu_Reserve1;                  //0x000001E8
+    REG32                          Cfg_Cpu_Reserve2;                  //0x000001EC
+    REG32                          Cfg_Cpu_Reserve3;                  //0x000001F0
+    REG32                          Cfg_Cpu_Reserve4;                  //0x000001F4
+    REG32                          Cfg_Cpu_Reserve5;                  //0x000001F8
+    REG32                          Cfg_Reserve;                  //0x000001FC
+} HWP_SYS_CTRL_AP_T;
+
+#define hwp_sysCtrlAp               ((HWP_SYS_CTRL_AP_T*)(RDA_SYSCTRL_BASE))
+
+
+//REG_DBG
+#define SYS_CTRL_AP_SCRATCH(n)      (((n)&0xFFFF)<<0)
+#define SYS_CTRL_AP_WRITE_UNLOCK_STATUS (1<<30)
+#define SYS_CTRL_AP_WRITE_UNLOCK    (1<<31)
+
+//Cfg_Pll_Ctrl
+#define SYS_CTRL_AP_AP_PLL_ENABLE   (1<<0)
+#define SYS_CTRL_AP_AP_PLL_ENABLE_MASK (1<<0)
+#define SYS_CTRL_AP_AP_PLL_ENABLE_SHIFT (0)
+#define SYS_CTRL_AP_AP_PLL_ENABLE_POWER_DOWN (0<<0)
+#define SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE (1<<0)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET (1<<4)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_MASK (1<<4)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_SHIFT (4)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_RESET (0<<4)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET (1<<4)
+#define SYS_CTRL_AP_AP_PLL_BYPASS   (1<<8)
+#define SYS_CTRL_AP_AP_PLL_BYPASS_MASK (1<<8)
+#define SYS_CTRL_AP_AP_PLL_BYPASS_SHIFT (8)
+#define SYS_CTRL_AP_AP_PLL_BYPASS_PASS (0<<8)
+#define SYS_CTRL_AP_AP_PLL_BYPASS_BYPASS (1<<8)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE (1<<12)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_MASK (1<<12)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_SHIFT (12)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_ENABLE (1<<12)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_DISABLE (0<<12)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(n) (((n)&31)<<16)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW_MASK (31<<16)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW_SHIFT (16)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(n) (((n)&31)<<24)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH_MASK (31<<24)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH_SHIFT (24)
+#define SYS_CTRL_AP_PLL_AP_CFG(n)   (((n)&0x1F1F1111)<<0)
+#define SYS_CTRL_AP_PLL_AP_CFG_MASK (0x1F1F1111<<0)
+#define SYS_CTRL_AP_PLL_AP_CFG_SHIFT (0)
+
+//Sel_Clock
+#define SYS_CTRL_AP_SLOW_SEL_RF_OSCILLATOR (1<<0)
+#define SYS_CTRL_AP_SLOW_SEL_RF_RF  (0<<0)
+#define SYS_CTRL_AP_TIMER_SEL_FAST_SLOW (1<<1)
+#define SYS_CTRL_AP_TIMER_SEL_FAST_FAST (0<<1)
+#define SYS_CTRL_AP_TIMER2_SEL_FAST_SLOW (1<<2)
+#define SYS_CTRL_AP_TIMER2_SEL_FAST_FAST (0<<2)
+#define SYS_CTRL_AP_TIMER3_SEL_FAST_SLOW (1<<3)
+#define SYS_CTRL_AP_TIMER3_SEL_FAST_FAST (0<<3)
+#define SYS_CTRL_AP_CPU_SEL_FAST_SLOW (1<<4)
+#define SYS_CTRL_AP_CPU_SEL_FAST_FAST (0<<4)
+#define SYS_CTRL_AP_BUS_SEL_FAST_SLOW (1<<5)
+#define SYS_CTRL_AP_BUS_SEL_FAST_FAST (0<<5)
+#define SYS_CTRL_AP_RF_DETECTED_OK  (1<<8)
+#define SYS_CTRL_AP_RF_DETECTED_NO  (0<<8)
+#define SYS_CTRL_AP_RF_DETECT_BYPASS (1<<9)
+#define SYS_CTRL_AP_RF_DETECT_RESET (1<<10)
+#define SYS_CTRL_AP_RF_SELECTED_L   (1<<11)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU  (1<<12)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU_MASK (1<<12)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU_SHIFT (12)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU_LOCKED (1<<12)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU_NOT_LOCKED (0<<12)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS  (1<<13)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS_MASK (1<<13)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS_SHIFT (13)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS_LOCKED (1<<13)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS_NOT_LOCKED (0<<13)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM  (1<<14)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM_MASK (1<<14)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM_SHIFT (14)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM_LOCKED (1<<14)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM_NOT_LOCKED (0<<14)
+#define SYS_CTRL_AP_PLL_LOCKED_USB  (1<<15)
+#define SYS_CTRL_AP_PLL_LOCKED_USB_MASK (1<<15)
+#define SYS_CTRL_AP_PLL_LOCKED_USB_SHIFT (15)
+#define SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED (1<<15)
+#define SYS_CTRL_AP_PLL_LOCKED_USB_NOT_LOCKED (0<<15)
+#define SYS_CTRL_AP_PLL_BYPASS_LOCK_CPU (1<<20)
+#define SYS_CTRL_AP_PLL_BYPASS_LOCK_BUS (1<<21)
+#define SYS_CTRL_AP_FAST_SELECTED_CPU_L (1<<30)
+#define SYS_CTRL_AP_FAST_SELECTED_CPU_L_MASK (1<<30)
+#define SYS_CTRL_AP_FAST_SELECTED_CPU_L_SHIFT (30)
+#define SYS_CTRL_AP_FAST_SELECTED_BUS_L (1<<31)
+#define SYS_CTRL_AP_FAST_SELECTED_BUS_L_MASK (1<<31)
+#define SYS_CTRL_AP_FAST_SELECTED_BUS_L_SHIFT (31)
+
+//Reset_Cause
+#define SYS_CTRL_AP_WATCHDOG_RESET_HAPPENED (1<<0)
+#define SYS_CTRL_AP_WATCHDOG_RESET_NO (0<<0)
+#define SYS_CTRL_AP_GLOBALSOFT_RESET_HAPPENED (1<<4)
+#define SYS_CTRL_AP_GLOBALSOFT_RESET_NO (0<<4)
+#define SYS_CTRL_AP_HOSTDEBUG_RESET_HAPPENED (1<<5)
+#define SYS_CTRL_AP_HOSTDEBUG_RESET_NO (0<<5)
+#define SYS_CTRL_AP_ALARMCAUSE_HAPPENED (1<<6)
+#define SYS_CTRL_AP_ALARMCAUSE_NO   (0<<6)
+#define SYS_CTRL_AP_BOOT_MODE(n)    (((n)&0xFFFF)<<8)
+#define SYS_CTRL_AP_BOOT_MODE_MASK  (0xFFFF<<8)
+#define SYS_CTRL_AP_BOOT_MODE_SHIFT (8)
+#define SYS_CTRL_AP_SW_BOOT_MODE(n) (((n)&0x7F)<<24)
+#define SYS_CTRL_AP_SW_BOOT_MODE_MASK (0x7F<<24)
+#define SYS_CTRL_AP_SW_BOOT_MODE_SHIFT (24)
+#define SYS_CTRL_AP_FONCTIONAL_TEST_MODE (1<<31)
+
+//CPU_Rst_Set
+#define SYS_CTRL_AP_SET_CPU_RST_CORE (1<<0)
+#define SYS_CTRL_AP_SET_CPU_RST_CORE1 (1<<1)
+#define SYS_CTRL_AP_SET_CPU_RST_CORE2 (1<<2)
+#define SYS_CTRL_AP_SET_CPU_RST_CORE3 (1<<3)
+#define SYS_CTRL_AP_SET_CPU_RST_L2 (1<<4)
+#define SYS_CTRL_AP_SET_CPU_RST_SYS (1<<5)
+#define SYS_CTRL_AP_SOFT_RST        (1<<31)
+#define SYS_CTRL_AP_SET_CPU_RST(n)  (((n)&0xF)<<0)
+#define SYS_CTRL_AP_SET_CPU_RST_MASK (0xF<<0)
+#define SYS_CTRL_AP_SET_CPU_RST_SHIFT (0)
+
+//CPU_Rst_Clr
+#define SYS_CTRL_AP_CLR_CPU_RST_CORE (1<<0)
+#define SYS_CTRL_AP_CLR_CPU_RST_CORE1 (1<<1)
+#define SYS_CTRL_AP_CLR_CPU_RST_CORE2 (1<<2)
+#define SYS_CTRL_AP_CLR_CPU_RST_CORE3 (1<<3)
+#define SYS_CTRL_AP_CLR_CPU_RST_L2 (1<<4)
+#define SYS_CTRL_AP_CLR_CPU_RST_SYS (1<<5)
+#define SYS_CTRL_AP_CLR_CPU_RST(n)  (((n)&0xF)<<0)
+#define SYS_CTRL_AP_CLR_CPU_RST_MASK (0xF<<0)
+#define SYS_CTRL_AP_CLR_CPU_RST_SHIFT (0)
+
+//AXI_Rst_Set
+#define SYS_CTRL_AP_SET_AXI_RST_VOC (1<<0)
+#define SYS_CTRL_AP_SET_AXI_RST_VOC2 (1<<1)
+#define SYS_CTRL_AP_SET_AXI_RST_DMA (1<<2)
+#define SYS_CTRL_AP_SET_AXI_RST_SYS (1<<3)
+#define SYS_CTRL_AP_SET_AXI_RST_CONNECT (1<<4)
+#define SYS_CTRL_AP_SET_APB0_RST_GPU (1<<5)
+#define SYS_CTRL_AP_SET_APB0_RST_VPU (1<<6)
+#define SYS_CTRL_AP_SET_APB0_RST_IRQ (1<<7)
+#define SYS_CTRL_AP_SET_AXI_RST(n)  (((n)&0xFF)<<0)
+#define SYS_CTRL_AP_SET_AXI_RST_MASK (0xFF<<0)
+#define SYS_CTRL_AP_SET_AXI_RST_SHIFT (0)
+
+//AXI_Rst_Clr
+#define SYS_CTRL_AP_CLR_AXI_RST_VOC (1<<0)
+#define SYS_CTRL_AP_CLR_AXI_RST_VOC2 (1<<1)
+#define SYS_CTRL_AP_CLR_AXI_RST_DMA (1<<2)
+#define SYS_CTRL_AP_CLR_AXI_RST_SYS (1<<3)
+#define SYS_CTRL_AP_CLR_AXI_RST_CONNECT (1<<4)
+#define SYS_CTRL_AP_CLR_APB0_RST_GPU (1<<5)
+#define SYS_CTRL_AP_CLR_APB0_RST_VPU (1<<6)
+#define SYS_CTRL_AP_CLR_APB0_RST_IRQ (1<<7)
+#define SYS_CTRL_AP_CLR_AXI_RST(n)  (((n)&0xFF)<<0)
+#define SYS_CTRL_AP_CLR_AXI_RST_MASK (0xFF<<0)
+#define SYS_CTRL_AP_CLR_AXI_RST_SHIFT (0)
+
+//AXIDIV2_Rst_Set
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_IMEM (1<<0)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_SYS (1<<1)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_VPU (1<<2)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_MASK (7<<0)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_SHIFT (0)
+
+//AXIDIV2_Rst_Clr
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_IMEM (1<<0)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_SYS (1<<1)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_VPU (1<<2)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_MASK (7<<0)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_SHIFT (0)
+
+//GCG_Rst_Set
+#define SYS_CTRL_AP_SET_GCG_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_GCG_RST_GOUDA (1<<1)
+#define SYS_CTRL_AP_SET_GCG_RST_CAMERA (1<<2)
+#define SYS_CTRL_AP_SET_GCG_RST_CAMERA2 (1<<3)
+#define SYS_CTRL_AP_SET_GCG_RST(n)  (((n)&0xF)<<0)
+#define SYS_CTRL_AP_SET_GCG_RST_MASK (0xF<<0)
+#define SYS_CTRL_AP_SET_GCG_RST_SHIFT (0)
+
+//GCG_Rst_Clr
+#define SYS_CTRL_AP_CLR_GCG_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_GCG_RST_GOUDA (1<<1)
+#define SYS_CTRL_AP_CLR_GCG_RST_CAMERA (1<<2)
+#define SYS_CTRL_AP_CLR_GCG_RST_CAMERA2 (1<<3)
+#define SYS_CTRL_AP_CLR_GCG_RST(n)  (((n)&0xF)<<0)
+#define SYS_CTRL_AP_CLR_GCG_RST_MASK (0xF<<0)
+#define SYS_CTRL_AP_CLR_GCG_RST_SHIFT (0)
+
+//AHB1_Rst_Set
+#define SYS_CTRL_AP_SET_AHB1_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_AHB1_RST_USBC (1<<1)
+#define SYS_CTRL_AP_SET_AHB1_RST_SPIFLASH (1<<2)
+#define SYS_CTRL_AP_SET_AHB1_RST_EMAC (1<<3)
+#define SYS_CTRL_AP_SET_AHB1_RST(n) (((n)&0xF)<<0)
+#define SYS_CTRL_AP_SET_AHB1_RST_MASK (0xF<<0)
+#define SYS_CTRL_AP_SET_AHB1_RST_SHIFT (0)
+
+//AHB1_Rst_Clr
+#define SYS_CTRL_AP_CLR_AHB1_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_AHB1_RST_USBC (1<<1)
+#define SYS_CTRL_AP_CLR_AHB1_RST_SPIFLASH (1<<2)
+#define SYS_CTRL_AP_CLR_AHB1_RST_EMAC (1<<3)
+#define SYS_CTRL_AP_CLR_AHB1_RST(n) (((n)&0xF)<<0)
+#define SYS_CTRL_AP_CLR_AHB1_RST_MASK (0xF<<0)
+#define SYS_CTRL_AP_CLR_AHB1_RST_SHIFT (0)
+
+//APB1_Rst_Set
+#define SYS_CTRL_AP_SET_APB1_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_APB1_RST_TIMER (1<<1)
+#define SYS_CTRL_AP_SET_APB1_RST_KEYPAD (1<<2)
+#define SYS_CTRL_AP_SET_APB1_RST_GPIO (1<<3)
+#define SYS_CTRL_AP_SET_APB1_RST_PWM (1<<4)
+#define SYS_CTRL_AP_SET_APB1_RST_AIF (1<<5)
+#define SYS_CTRL_AP_SET_APB1_RST_AIF2 (1<<6)
+#define SYS_CTRL_AP_SET_APB1_RST_AUIFC (1<<7)
+#define SYS_CTRL_AP_SET_APB1_RST_COM_REGS (1<<8)
+#define SYS_CTRL_AP_SET_APB1_RST_DMC (1<<9)
+#define SYS_CTRL_AP_SET_APB1_RST_DDRPHY_P (1<<10)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_XCPU (1<<11)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BCPU (1<<12)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_AHBC (1<<13)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_DMA (1<<14)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_A2A (1<<15)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_XIFC (1<<16)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BIFC (1<<17)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BAHBC (1<<18)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_MEM_BRIDGE (1<<19)
+#define SYS_CTRL_AP_SET_APB1_RST(n) (((n)&0xFFFFF)<<0)
+#define SYS_CTRL_AP_SET_APB1_RST_MASK (0xFFFFF<<0)
+#define SYS_CTRL_AP_SET_APB1_RST_SHIFT (0)
+
+//APB1_Rst_Clr
+#define SYS_CTRL_AP_CLR_APB1_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_APB1_RST_TIMER (1<<1)
+#define SYS_CTRL_AP_CLR_APB1_RST_KEYPAD (1<<2)
+#define SYS_CTRL_AP_CLR_APB1_RST_GPIO (1<<3)
+#define SYS_CTRL_AP_CLR_APB1_RST_PWM (1<<4)
+#define SYS_CTRL_AP_CLR_APB1_RST_AIF (1<<5)
+#define SYS_CTRL_AP_CLR_APB1_RST_AIF2 (1<<6)
+#define SYS_CTRL_AP_CLR_APB1_RST_AUIFC (1<<7)
+#define SYS_CTRL_AP_CLR_APB1_RST_COM_REGS (1<<8)
+#define SYS_CTRL_AP_CLR_APB1_RST_DMC (1<<9)
+#define SYS_CTRL_AP_CLR_APB1_RST_DDRPHY_P (1<<10)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_XCPU (1<<11)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BCPU (1<<12)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_AHBC (1<<13)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_DMA (1<<14)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_A2A (1<<15)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_XIFC (1<<16)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BIFC (1<<17)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BAHBC (1<<18)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_MEM_BRIDGE (1<<19)
+#define SYS_CTRL_AP_CLR_APB1_RST(n) (((n)&0xFFFFF)<<0)
+#define SYS_CTRL_AP_CLR_APB1_RST_MASK (0xFFFFF<<0)
+#define SYS_CTRL_AP_CLR_APB1_RST_SHIFT (0)
+
+//APB2_Rst_Set
+#define SYS_CTRL_AP_SET_APB2_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_APB2_RST_IFC (1<<1)
+#define SYS_CTRL_AP_SET_APB2_RST_UART1 (1<<2)
+#define SYS_CTRL_AP_SET_APB2_RST_UART2 (1<<3)
+#define SYS_CTRL_AP_SET_APB2_RST_UART3 (1<<4)
+#define SYS_CTRL_AP_SET_APB2_RST_SPI1 (1<<5)
+#define SYS_CTRL_AP_SET_APB2_RST_SPI2 (1<<6)
+#define SYS_CTRL_AP_SET_APB2_RST_SPI3 (1<<7)
+#define SYS_CTRL_AP_SET_APB2_RST_SDMMC1 (1<<8)
+#define SYS_CTRL_AP_SET_APB2_RST_SDMMC2 (1<<9)
+#define SYS_CTRL_AP_SET_APB2_RST_SDMMC3 (1<<10)
+#define SYS_CTRL_AP_SET_APB2_RST_NANDFLASH (1<<11)
+#define SYS_CTRL_AP_SET_APB2_RST_I2C1 (1<<12)
+#define SYS_CTRL_AP_SET_APB2_RST_I2C2 (1<<13)
+#define SYS_CTRL_AP_SET_APB2_RST_I2C3 (1<<14)
+#define SYS_CTRL_AP_SET_APB2_RST(n) (((n)&0x7FFF)<<0)
+#define SYS_CTRL_AP_SET_APB2_RST_MASK (0x7FFF<<0)
+#define SYS_CTRL_AP_SET_APB2_RST_SHIFT (0)
+
+//APB2_Rst_Clr
+#define SYS_CTRL_AP_CLR_APB2_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_APB2_RST_IFC (1<<1)
+#define SYS_CTRL_AP_CLR_APB2_RST_UART1 (1<<2)
+#define SYS_CTRL_AP_CLR_APB2_RST_UART2 (1<<3)
+#define SYS_CTRL_AP_CLR_APB2_RST_UART3 (1<<4)
+#define SYS_CTRL_AP_CLR_APB2_RST_SPI1 (1<<5)
+#define SYS_CTRL_AP_CLR_APB2_RST_SPI2 (1<<6)
+#define SYS_CTRL_AP_CLR_APB2_RST_SPI3 (1<<7)
+#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC1 (1<<8)
+#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC2 (1<<9)
+#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC3 (1<<10)
+#define SYS_CTRL_AP_CLR_APB2_RST_NANDFLASH (1<<11)
+#define SYS_CTRL_AP_CLR_APB2_RST_I2C1 (1<<12)
+#define SYS_CTRL_AP_CLR_APB2_RST_I2C2 (1<<13)
+#define SYS_CTRL_AP_CLR_APB2_RST_I2C3 (1<<14)
+#define SYS_CTRL_AP_CLR_APB2_RST(n) (((n)&0x7FFF)<<0)
+#define SYS_CTRL_AP_CLR_APB2_RST_MASK (0x7FFF<<0)
+#define SYS_CTRL_AP_CLR_APB2_RST_SHIFT (0)
+
+//MEM_Rst_Set
+#define SYS_CTRL_AP_SET_MEM_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_MEM_RST_DMC (1<<1)
+#define SYS_CTRL_AP_SET_MEM_RST_DDRPHY_P (1<<2)
+#define SYS_CTRL_AP_SET_MEM_RST(n)  (((n)&0x7)<<0)
+#define SYS_CTRL_AP_SET_MEM_RST_MASK (0x7<<0)
+#define SYS_CTRL_AP_SET_MEM_RST_SHIFT (0)
+
+//MEM_Rst_Clr
+#define SYS_CTRL_AP_CLR_MEM_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_MEM_RST_DMC (1<<1)
+#define SYS_CTRL_AP_CLR_MEM_RST_DDRPHY_P (1<<2)
+#define SYS_CTRL_AP_CLR_MEM_RST(n)  (((n)&0x7)<<0)
+#define SYS_CTRL_AP_CLR_MEM_RST_MASK (0x7<<0)
+#define SYS_CTRL_AP_CLR_MEM_RST_SHIFT (0)
+
+//Clk_CPU_Mode
+#define SYS_CTRL_AP_MODE_CLK_CPU_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_CLK_CPU_MANUAL (1<<0)
+
+//Clk_CPU_Enable
+#define SYS_CTRL_AP_ENABLE_CPU_CORE (1<<0)
+#define SYS_CTRL_AP_ENABLE_CPU_DUMMY (1<<1)
+#define SYS_CTRL_AP_ENABLE_CLK_CPU(n) (((n)&3)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_CPU_MASK (3<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_CPU_SHIFT (0)
+
+//Clk_CPU_Disable
+#define SYS_CTRL_AP_DISABLE_CPU_CORE (1<<0)
+#define SYS_CTRL_AP_DISABLE_CPU_DUMMY (1<<1)
+#define SYS_CTRL_AP_DISABLE_CLK_CPU(n) (((n)&3)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_CPU_MASK (3<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_CPU_SHIFT (0)
+
+//Clk_AXI_Mode
+#define SYS_CTRL_AP_MODE_AHB0_CONF_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_AHB0_CONF_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_APB0_CONF_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_APB0_CONF_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_AXI_VOC_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_AXI_VOC_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_AXI_VOC2_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_AXI_VOC2_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_AXI_DMA_AUTOMATIC (0<<4)
+#define SYS_CTRL_AP_MODE_AXI_DMA_MANUAL (1<<4)
+#define SYS_CTRL_AP_MODE_CLK_AXI(n) (((n)&0x1F)<<0)
+#define SYS_CTRL_AP_MODE_CLK_AXI_MASK (0x1F<<0)
+#define SYS_CTRL_AP_MODE_CLK_AXI_SHIFT (0)
+
+//Clk_AXI_Enable
+#define SYS_CTRL_AP_ENABLE_AHB0_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_APB0_CONF (1<<1)
+#define SYS_CTRL_AP_ENABLE_AXI_VOC  (1<<2)
+#define SYS_CTRL_AP_ENABLE_AXI_VOC2  (1<<3)
+#define SYS_CTRL_AP_ENABLE_AXI_DMA  (1<<4)
+#define SYS_CTRL_AP_ENABLE_AXI_ALWAYS (1<<5)
+#define SYS_CTRL_AP_ENABLE_AXI_CONNECT (1<<6)
+#define SYS_CTRL_AP_ENABLE_AXI_VPU (1<<7)
+#define SYS_CTRL_AP_ENABLE_APB0_IRQ (1<<8)
+#define SYS_CTRL_AP_ENABLE_CLK_AXI(n) (((n)&0x1FF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AXI_MASK (0x1FF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AXI_SHIFT (0)
+
+//Clk_AXI_Disable
+#define SYS_CTRL_AP_DISABLE_AHB0_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_APB0_CONF (1<<1)
+#define SYS_CTRL_AP_DISABLE_AXI_VOC (1<<2)
+#define SYS_CTRL_AP_DISABLE_AXI_VOC2 (1<<3)
+#define SYS_CTRL_AP_DISABLE_AXI_DMA (1<<4)
+#define SYS_CTRL_AP_DISABLE_AXI_ALWAYS (1<<5)
+#define SYS_CTRL_AP_DISABLE_AXI_CONNECT (1<<6)
+#define SYS_CTRL_AP_DISABLE_AXI_VPU (1<<7)
+#define SYS_CTRL_AP_DISABLE_APB0_IRQ (1<<8)
+#define SYS_CTRL_AP_DISABLE_CLK_AXI(n) (((n)&0x1FF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AXI_MASK (0x1FF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AXI_SHIFT (0)
+
+//Clk_AXIDIV2_Mode
+#define SYS_CTRL_AP_MODE_CLK_AXIDIV2_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_CLK_AXIDIV2_MANUAL (1<<0)
+
+//Clk_AXIDIV2_Enable
+#define SYS_CTRL_AP_ENABLE_AXIDIV2_IMEM (1<<0)
+#define SYS_CTRL_AP_ENABLE_AXIDIV2_ALWAYS (1<<1)
+#define SYS_CTRL_AP_ENABLE_AXIDIV2_CONNECT (1<<2)
+#define SYS_CTRL_AP_ENABLE_AXIDIV2_VPU (1<<3)
+#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2(n) (((n)&15)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2_MASK (15<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2_SHIFT (0)
+
+//Clk_AXIDIV2_Disable
+#define SYS_CTRL_AP_DISABLE_AXIDIV2_IMEM (1<<0)
+#define SYS_CTRL_AP_DISABLE_AXIDIV2_ALWAYS (1<<1)
+#define SYS_CTRL_AP_DISABLE_AXIDIV2_CONNECT (1<<2)
+#define SYS_CTRL_AP_DISABLE_AXIDIV2_VPU (1<<3)
+#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2(n) (((n)&15)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2_MASK (15<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2_SHIFT (0)
+
+//Clk_GCG_Mode
+#define SYS_CTRL_AP_MODE_GCG_APB_CONF_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_GCG_APB_CONF_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_GCG_GOUDA_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_GCG_GOUDA_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_GCG_CAMERA_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_GCG_CAMERA_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_GCG_CAMERA2_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_GCG_CAMERA2_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_CLK_GCG(n) (((n)&0xF)<<0)
+#define SYS_CTRL_AP_MODE_CLK_GCG_MASK (0xF<<0)
+#define SYS_CTRL_AP_MODE_CLK_GCG_SHIFT (0)
+
+//Clk_GCG_Enable
+#define SYS_CTRL_AP_ENABLE_GCG_APB_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_GCG_GOUDA (1<<1)
+#define SYS_CTRL_AP_ENABLE_GCG_CAMERA (1<<2)
+#define SYS_CTRL_AP_ENABLE_GCG_CAMERA2 (1<<3)
+#define SYS_CTRL_AP_ENABLE_GCG_ALWAYS (1<<4)
+#define SYS_CTRL_AP_ENABLE_GCG_CONNECT (1<<5)
+#define SYS_CTRL_AP_ENABLE_GCG_GOUDA_AW (1<<6)
+#define SYS_CTRL_AP_ENABLE_GCG_GOUDA_DPI (1<<7)
+#define SYS_CTRL_AP_ENABLE_CLK_GCG(n) (((n)&0xFF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_GCG_MASK (0xFF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_GCG_SHIFT (0)
+
+//Clk_GCG_Disable
+#define SYS_CTRL_AP_DISABLE_GCG_APB_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_GCG_GOUDA (1<<1)
+#define SYS_CTRL_AP_DISABLE_GCG_CAMERA (1<<2)
+#define SYS_CTRL_AP_DISABLE_GCG_CAMERA2 (1<<3)
+#define SYS_CTRL_AP_DISABLE_GCG_ALWAYS (1<<4)
+#define SYS_CTRL_AP_DISABLE_GCG_CONNECT (1<<5)
+#define SYS_CTRL_AP_DISABLE_GCG_GOUDA_AW (1<<6)
+#define SYS_CTRL_AP_DISABLE_GCG_GOUDA_DPI (1<<7)
+#define SYS_CTRL_AP_DISABLE_CLK_GCG(n) (((n)&0xFF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_GCG_MASK (0xFF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_GCG_SHIFT (0)
+
+//Clk_AHB1_Mode
+#define SYS_CTRL_AP_MODE_CLK_AHB1_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_CLK_AHB1_MANUAL (1<<0)
+
+//Clk_AHB1_Enable
+#define SYS_CTRL_AP_ENABLE_AHB1_USBC (1<<0)
+#define SYS_CTRL_AP_ENABLE_AHB1_ALWAYS (1<<1)
+#define SYS_CTRL_AP_ENABLE_AHB1_SPIFLASH (1<<2)
+#define SYS_CTRL_AP_ENABLE_AHB1_EMAC (1<<3)
+#define SYS_CTRL_AP_ENABLE_CLK_AHB1(n) (((n)&0xF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AHB1_MASK (0xF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AHB1_SHIFT (0)
+
+//Clk_AHB1_Disable
+#define SYS_CTRL_AP_DISABLE_AHB1_USBC (1<<0)
+#define SYS_CTRL_AP_DISABLE_AHB1_ALWAYS (1<<1)
+#define SYS_CTRL_AP_DISABLE_AHB1_SPIFLASH (1<<2)
+#define SYS_CTRL_AP_DISABLE_AHB1_EMAC (1<<3)
+#define SYS_CTRL_AP_DISABLE_CLK_AHB1(n) (((n)&0xF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AHB1_MASK (0xF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AHB1_SHIFT (0)
+
+//Clk_APB1_Mode
+#define SYS_CTRL_AP_MODE_APB1_CONF_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_APB1_CONF_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_APB1_AIF_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_APB1_AIF_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_APB1_AIF2_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_APB1_AIF2_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH0_AUTOMATIC (0<<4)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH0_MANUAL (1<<4)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH1_AUTOMATIC (0<<5)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH1_MANUAL (1<<5)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH2_AUTOMATIC (0<<6)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH2_MANUAL (1<<6)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH3_AUTOMATIC (0<<7)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH3_MANUAL (1<<7)
+#define SYS_CTRL_AP_MODE_APB1D_OSC_AUTOMATIC (0<<8)
+#define SYS_CTRL_AP_MODE_APB1D_OSC_MANUAL (1<<8)
+#define SYS_CTRL_AP_MODE_APB1D_OSC2_AUTOMATIC (0<<9)
+#define SYS_CTRL_AP_MODE_APB1D_OSC2_MANUAL (1<<9)
+#define SYS_CTRL_AP_MODE_APB1D_OSC3_AUTOMATIC (0<<10)
+#define SYS_CTRL_AP_MODE_APB1D_OSC3_MANUAL (1<<10)
+#define SYS_CTRL_AP_MODE_APB1D_PWM_AUTOMATIC (0<<11)
+#define SYS_CTRL_AP_MODE_APB1D_PWM_MANUAL (1<<11)
+#define SYS_CTRL_AP_MODE_CLK_APB1(n) (((n)&0xFFF)<<0)
+#define SYS_CTRL_AP_MODE_CLK_APB1_MASK (0xFFF<<0)
+#define SYS_CTRL_AP_MODE_CLK_APB1_SHIFT (0)
+
+//Clk_APB1_Enable
+#define SYS_CTRL_AP_ENABLE_APB1_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_APB1_AIF (1<<1)
+#define SYS_CTRL_AP_ENABLE_APB1_AIF2 (1<<2)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC (1<<3)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH0 (1<<4)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH1 (1<<5)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH2 (1<<6)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH3 (1<<7)
+#define SYS_CTRL_AP_ENABLE_APB1D_OSC (1<<8)
+#define SYS_CTRL_AP_ENABLE_APB1D_OSC2 (1<<9)
+#define SYS_CTRL_AP_ENABLE_APB1D_OSC3 (1<<10)
+#define SYS_CTRL_AP_ENABLE_APB1D_PWM (1<<11)
+#define SYS_CTRL_AP_ENABLE_APB1_ALWAYS (1<<12)
+#define SYS_CTRL_AP_ENABLE_APB1_DAPLITE (1<<13)
+#define SYS_CTRL_AP_ENABLE_APB1_TIMER (1<<14)
+#define SYS_CTRL_AP_ENABLE_APB1_GPIO (1<<15)
+#define SYS_CTRL_AP_ENABLE_CLK_APB1(n) (((n)&0xFFFF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APB1_MASK (0xFFFF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APB1_SHIFT (0)
+
+//Clk_APB1_Disable
+#define SYS_CTRL_AP_DISABLE_APB1_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_APB1_AIF (1<<1)
+#define SYS_CTRL_AP_DISABLE_APB1_AIF2 (1<<2)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC (1<<3)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH0 (1<<4)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH1 (1<<5)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH2 (1<<6)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH3 (1<<7)
+#define SYS_CTRL_AP_DISABLE_APB1D_OSC (1<<8)
+#define SYS_CTRL_AP_DISABLE_APB1D_OSC2 (1<<9)
+#define SYS_CTRL_AP_DISABLE_APB1D_OSC3 (1<<10)
+#define SYS_CTRL_AP_DISABLE_APB1D_PWM (1<<11)
+#define SYS_CTRL_AP_DISABLE_APB1_ALWAYS (1<<12)
+#define SYS_CTRL_AP_DISABLE_APB1_DAPLITE (1<<13)
+#define SYS_CTRL_AP_DISABLE_APB1_TIMER (1<<14)
+#define SYS_CTRL_AP_DISABLE_APB1_GPIO (1<<15)
+#define SYS_CTRL_AP_DISABLE_CLK_APB1(n) (((n)&0xFFFF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APB1_MASK (0xFFFF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APB1_SHIFT (0)
+
+//Clk_APB2_Mode
+#define SYS_CTRL_AP_MODE_APB2_CONF_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_APB2_CONF_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_APB2_IFC_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_APB2_IFC_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH0_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH0_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH1_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH1_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH2_AUTOMATIC (0<<4)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH2_MANUAL (1<<4)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH3_AUTOMATIC (0<<5)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH3_MANUAL (1<<5)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH4_AUTOMATIC (0<<6)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH4_MANUAL (1<<6)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH5_AUTOMATIC (0<<7)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH5_MANUAL (1<<7)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH6_AUTOMATIC (0<<8)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH6_MANUAL (1<<8)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH7_AUTOMATIC (0<<9)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH7_MANUAL (1<<9)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH8_AUTOMATIC (0<<10)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH8_MANUAL (1<<10)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH9_AUTOMATIC (0<<11)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH9_MANUAL (1<<11)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH10_AUTOMATIC (0<<12)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH10_MANUAL (1<<12)
+#define SYS_CTRL_AP_MODE_APB2_UART1_AUTOMATIC (0<<13)
+#define SYS_CTRL_AP_MODE_APB2_UART1_MANUAL (1<<13)
+#define SYS_CTRL_AP_MODE_APB2_UART2_AUTOMATIC (0<<14)
+#define SYS_CTRL_AP_MODE_APB2_UART2_MANUAL (1<<14)
+#define SYS_CTRL_AP_MODE_APB2_UART3_AUTOMATIC (0<<15)
+#define SYS_CTRL_AP_MODE_APB2_UART3_MANUAL (1<<15)
+#define SYS_CTRL_AP_MODE_APB2_SPI1_AUTOMATIC (0<<16)
+#define SYS_CTRL_AP_MODE_APB2_SPI1_MANUAL (1<<16)
+#define SYS_CTRL_AP_MODE_APB2_SPI2_AUTOMATIC (0<<17)
+#define SYS_CTRL_AP_MODE_APB2_SPI2_MANUAL (1<<17)
+#define SYS_CTRL_AP_MODE_APB2_SPI3_AUTOMATIC (0<<18)
+#define SYS_CTRL_AP_MODE_APB2_SPI3_MANUAL (1<<18)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC1_AUTOMATIC (0<<19)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC1_MANUAL (1<<19)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC2_AUTOMATIC (0<<20)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC2_MANUAL (1<<20)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC3_AUTOMATIC (0<<21)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC3_MANUAL (1<<21)
+#define SYS_CTRL_AP_MODE_APB2_I2C1_AUTOMATIC (0<<22)
+#define SYS_CTRL_AP_MODE_APB2_I2C1_MANUAL (1<<22)
+#define SYS_CTRL_AP_MODE_APB2_I2C2_AUTOMATIC (0<<23)
+#define SYS_CTRL_AP_MODE_APB2_I2C2_MANUAL (1<<23)
+#define SYS_CTRL_AP_MODE_APB2_I2C3_AUTOMATIC (0<<24)
+#define SYS_CTRL_AP_MODE_APB2_I2C3_MANUAL (1<<24)
+#define SYS_CTRL_AP_MODE_CLK_APB2(n) (((n)&0x1FFFFFF)<<0)
+#define SYS_CTRL_AP_MODE_CLK_APB2_MASK (0x1FFFFFF<<0)
+#define SYS_CTRL_AP_MODE_CLK_APB2_SHIFT (0)
+
+//Clk_APB2_Enable
+#define SYS_CTRL_AP_ENABLE_APB2_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC (1<<1)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH0 (1<<2)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH1 (1<<3)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH2 (1<<4)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH3 (1<<5)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH4 (1<<6)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH5 (1<<7)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH6 (1<<8)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH7 (1<<9)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH8 (1<<10)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH9 (1<<11)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH10 (1<<12)
+#define SYS_CTRL_AP_ENABLE_APB2_UART1 (1<<13)
+#define SYS_CTRL_AP_ENABLE_APB2_UART2 (1<<14)
+#define SYS_CTRL_AP_ENABLE_APB2_UART3 (1<<15)
+#define SYS_CTRL_AP_ENABLE_APB2_SPI1 (1<<16)
+#define SYS_CTRL_AP_ENABLE_APB2_SPI2 (1<<17)
+#define SYS_CTRL_AP_ENABLE_APB2_SPI3 (1<<18)
+#define SYS_CTRL_AP_ENABLE_APB2_SDMMC1 (1<<19)
+#define SYS_CTRL_AP_ENABLE_APB2_SDMMC2 (1<<20)
+#define SYS_CTRL_AP_ENABLE_APB2_SDMMC3 (1<<21)
+#define SYS_CTRL_AP_ENABLE_APB2_I2C1 (1<<22)
+#define SYS_CTRL_AP_ENABLE_APB2_I2C2 (1<<23)
+#define SYS_CTRL_AP_ENABLE_APB2_I2C3 (1<<24)
+#define SYS_CTRL_AP_ENABLE_APB2_ALWAYS (1<<25)
+#define SYS_CTRL_AP_ENABLE_APB2_NANDFLASH (1<<26)
+#define SYS_CTRL_AP_ENABLE_CLK_APB2(n) (((n)&0x7FFFFFF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APB2_MASK (0x7FFFFFF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APB2_SHIFT (0)
+
+//Clk_APB2_Disable
+#define SYS_CTRL_AP_DISABLE_APB2_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC (1<<1)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH0 (1<<2)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH1 (1<<3)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH2 (1<<4)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH3 (1<<5)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH4 (1<<6)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH5 (1<<7)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH6 (1<<8)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH7 (1<<9)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH8 (1<<10)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH9 (1<<11)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH10 (1<<12)
+#define SYS_CTRL_AP_DISABLE_APB2_UART1 (1<<13)
+#define SYS_CTRL_AP_DISABLE_APB2_UART2 (1<<14)
+#define SYS_CTRL_AP_DISABLE_APB2_UART3 (1<<15)
+#define SYS_CTRL_AP_DISABLE_APB2_SPI1 (1<<16)
+#define SYS_CTRL_AP_DISABLE_APB2_SPI2 (1<<17)
+#define SYS_CTRL_AP_DISABLE_APB2_SPI3 (1<<18)
+#define SYS_CTRL_AP_DISABLE_APB2_SDMMC1 (1<<19)
+#define SYS_CTRL_AP_DISABLE_APB2_SDMMC2 (1<<20)
+#define SYS_CTRL_AP_DISABLE_APB2_SDMMC3 (1<<21)
+#define SYS_CTRL_AP_DISABLE_APB2_I2C1 (1<<22)
+#define SYS_CTRL_AP_DISABLE_APB2_I2C2 (1<<23)
+#define SYS_CTRL_AP_DISABLE_APB2_I2C3 (1<<24)
+#define SYS_CTRL_AP_DISABLE_APB2_ALWAYS (1<<25)
+#define SYS_CTRL_AP_DISABLE_APB2_NANDFLASH (1<<26)
+#define SYS_CTRL_AP_DISABLE_CLK_APB2(n) (((n)&0x7FFFFFF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APB2_MASK (0x7FFFFFF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APB2_SHIFT (0)
+
+//Clk_MEM_Mode
+#define SYS_CTRL_AP_MODE_CLK_MEM_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_CLK_MEM_MANUAL (1<<0)
+
+//Clk_MEM_Enable
+#define SYS_CTRL_AP_ENABLE_MEM_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_MEM_DMC  (1<<1)
+#define SYS_CTRL_AP_ENABLE_MEM_DDRPHY_P (1<<2)
+#define SYS_CTRL_AP_ENABLE_MEM_CONNECT (1<<3)
+#define SYS_CTRL_AP_ENABLE_CLK_MEM(n) (((n)&0xF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_MEM_MASK (0xF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_MEM_SHIFT (0)
+
+//Clk_MEM_Disable
+#define SYS_CTRL_AP_DISABLE_MEM_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_MEM_DMC (1<<1)
+#define SYS_CTRL_AP_DISABLE_MEM_DDRPHY_P (1<<2)
+#define SYS_CTRL_AP_DISABLE_MEM_CONNECT (1<<3)
+#define SYS_CTRL_AP_DISABLE_CLK_MEM(n) (((n)&0xF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_MEM_MASK (0xF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_MEM_SHIFT (0)
+
+//Clk_APO_Mode
+#define SYS_CTRL_AP_MODE_APOC_BCK_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_APOC_BCK_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_APOC_BCK2_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_APOC_BCK2_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_APOC_UART1_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_APOC_UART1_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_APOC_UART2_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_APOC_UART2_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_APOC_UART3_AUTOMATIC (0<<4)
+#define SYS_CTRL_AP_MODE_APOC_UART3_MANUAL (1<<4)
+#define SYS_CTRL_AP_MODE_APOC_VOC_CORE_AUTOMATIC (0<<5)
+#define SYS_CTRL_AP_MODE_APOC_VOC_CORE_MANUAL (1<<5)
+#define SYS_CTRL_AP_MODE_APOC_VOC2_CORE_AUTOMATIC (0<<6)
+#define SYS_CTRL_AP_MODE_APOC_VOC2_CORE_MANUAL (1<<6)
+#define SYS_CTRL_AP_MODE_APOC_VOC_AUTOMATIC (0<<7)
+#define SYS_CTRL_AP_MODE_APOC_VOC_MANUAL (1<<7)
+#define SYS_CTRL_AP_MODE_APOC_VOC2_AUTOMATIC (0<<8)
+#define SYS_CTRL_AP_MODE_APOC_VOC2_MANUAL (1<<8)
+#define SYS_CTRL_AP_MODE_CLK_APO(n) (((n)&01FF)<<0)
+#define SYS_CTRL_AP_MODE_CLK_APO_MASK (0x1FF<<0)
+#define SYS_CTRL_AP_MODE_CLK_APO_SHIFT (0)
+
+//Clk_APO_Enable
+#define SYS_CTRL_AP_ENABLE_APOC_BCK (1<<0)
+#define SYS_CTRL_AP_ENABLE_APOC_BCK2 (1<<1)
+#define SYS_CTRL_AP_ENABLE_APOC_UART1 (1<<2)
+#define SYS_CTRL_AP_ENABLE_APOC_UART2 (1<<3)
+#define SYS_CTRL_AP_ENABLE_APOC_UART3 (1<<4)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC_CORE (1<<5)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC2_CORE (1<<6)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC (1<<7)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC2 (1<<8)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC_ALWAYS (1<<9)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC2_ALWAYS (1<<10)
+#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY_N (1<<11)
+#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY2XP (1<<12)
+#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY2XN (1<<13)
+#define SYS_CTRL_AP_ENABLE_APOC_VPU (1<<14)
+#define SYS_CTRL_AP_ENABLE_APOC_GPU (1<<15)
+#define SYS_CTRL_AP_ENABLE_APOC_USBPHY (1<<16)
+#define SYS_CTRL_AP_ENABLE_APOC_CSI (1<<17)
+#define SYS_CTRL_AP_ENABLE_APOC_CSI2 (1<<18)
+#define SYS_CTRL_AP_ENABLE_APOC_DSI (1<<19)
+#define SYS_CTRL_AP_ENABLE_APOC_GPIO (1<<20)
+#define SYS_CTRL_AP_ENABLE_APOC_SPIFLASH (1<<21)
+#define SYS_CTRL_AP_ENABLE_APOC_PIX (1<<22)
+#define SYS_CTRL_AP_ENABLE_APOC_PIX2 (1<<23)
+#define SYS_CTRL_AP_ENABLE_APOC_PDGB (1<<24)
+#define SYS_CTRL_AP_ENABLE_CLK_APO(n) (((n)&0x1FFFFFF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APO_MASK (0x1FFFFFF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APO_SHIFT (0)
+
+//Clk_APO_Disable
+#define SYS_CTRL_AP_DISABLE_APOC_BCK (1<<0)
+#define SYS_CTRL_AP_DISABLE_APOC_BCK2 (1<<1)
+#define SYS_CTRL_AP_DISABLE_APOC_UART1 (1<<2)
+#define SYS_CTRL_AP_DISABLE_APOC_UART2 (1<<3)
+#define SYS_CTRL_AP_DISABLE_APOC_UART3 (1<<4)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC_CORE (1<<5)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC2_CORE (1<<6)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC (1<<7)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC2 (1<<8)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC_ALWAYS (1<<9)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC2_ALWAYS (1<<10)
+#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY_N (1<<11)
+#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY2XP (1<<12)
+#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY2XN (1<<13)
+#define SYS_CTRL_AP_DISABLE_APOC_VPU (1<<14)
+#define SYS_CTRL_AP_DISABLE_APOC_GPU (1<<15)
+#define SYS_CTRL_AP_DISABLE_APOC_USBPHY (1<<16)
+#define SYS_CTRL_AP_DISABLE_APOC_CSI (1<<17)
+#define SYS_CTRL_AP_DISABLE_APOC_CSI2 (1<<18)
+#define SYS_CTRL_AP_DISABLE_APOC_DSI (1<<19)
+#define SYS_CTRL_AP_DISABLE_APOC_GPIO (1<<20)
+#define SYS_CTRL_AP_DISABLE_APOC_SPIFLASH (1<<21)
+#define SYS_CTRL_AP_DISABLE_APOC_PIX (1<<22)
+#define SYS_CTRL_AP_DISABLE_APOC_PIX2 (1<<23)
+#define SYS_CTRL_AP_DISABLE_APOC_PDGB (1<<24)
+#define SYS_CTRL_AP_DISABLE_CLK_APO(n) (((n)&0x1FFFFFF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APO_MASK (0x1FFFFFF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APO_SHIFT (0)
+
+//Cfg_Clk_AP_CPU
+#define SYS_CTRL_AP_AP_CPU_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_BUS_DIV_SEL(n)  (((n)&3)<<16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_MASK (3<<16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_SHIFT (16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_DIV2 (0<<16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_DIV3 (1<<16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_DIV4 (2<<16)
+#define SYS_CTRL_AP_DBG_CLKDIV_SEL(n)  (((n)&15)<<20)
+#define SYS_CTRL_AP_DBG_CLKDIV_DIV_SEL_MASK (15<<20)
+#define SYS_CTRL_AP_DBG_CLKDIV_SEL_SHIFT (20)
+#define SYS_CTRL_AP_AP_CPU_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_AXI
+#define SYS_CTRL_AP_AP_AXI_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_AXI_SRC_SEL  (1<<12)
+#define SYS_CTRL_AP_AP_AXI_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_GCG
+#define SYS_CTRL_AP_AP_GCG_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_GCG_SRC_SEL  (1<<12)
+#define SYS_CTRL_AP_AP_GCG_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_AHB1
+#define SYS_CTRL_AP_AP_AHB1_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_AHB1_SRC_SEL (1<<12)
+#define SYS_CTRL_AP_AP_AHB1_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_APB1
+#define SYS_CTRL_AP_AP_APB1_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_APB1_SRC_SEL (1<<12)
+#define SYS_CTRL_AP_AP_APB1_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_APB2
+#define SYS_CTRL_AP_AP_APB2_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_APB2_SRC_SEL (1<<12)
+#define SYS_CTRL_AP_AP_APB2_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_MEM
+#define SYS_CTRL_AP_AP_MEM_SRC_DIV2 (1<<12)
+
+//Cfg_Clk_AP_GPU
+#define SYS_CTRL_AP_AP_GPU_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_GPU_SRC_DIV2 (1<<12)
+#define SYS_CTRL_AP_AP_GPU_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_VPU
+#define SYS_CTRL_AP_AP_VPU_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_VPU_SRC_DIV2 (1<<12)
+#define SYS_CTRL_AP_AP_VPU_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_VOC
+#define SYS_CTRL_AP_AP_VOC_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_VOC_SRC_DIV2 (1<<12)
+#define SYS_CTRL_AP_AP_VOC_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_SFLSH
+#define SYS_CTRL_AP_AP_SFLSH_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_SFLSH_SRC_DIV2 (1<<12)
+#define SYS_CTRL_AP_AP_SFLSH_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_Uart
+#define SYS_CTRL_AP_UART_DIVIDER(n) (((n)&0x3FF)<<0)
+#define SYS_CTRL_AP_UART_DIVIDER_MASK (0x3FF<<0)
+#define SYS_CTRL_AP_UART_DIVIDER_SHIFT (0)
+#define SYS_CTRL_AP_UART_SEL_PLL_SLOW (0<<12)
+#define SYS_CTRL_AP_UART_SEL_PLL_PLL (1<<12)
+
+//L2cc_Ctrl
+#define SYS_CTRL_AP_ARQOS_L2CC_1_M(n) (((n)&15)<<0)
+#define SYS_CTRL_AP_ARQOS_L2CC_1_M_MASK (15<<0)
+#define SYS_CTRL_AP_ARQOS_L2CC_1_M_SHIFT (0)
+#define SYS_CTRL_AP_AWQOS_L2CC_1_M(n) (((n)&15)<<4)
+#define SYS_CTRL_AP_AWQOS_L2CC_1_M_MASK (15<<4)
+#define SYS_CTRL_AP_AWQOS_L2CC_1_M_SHIFT (4)
+#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M(n) (((n)&15)<<8)
+#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M_MASK (15<<8)
+#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M_SHIFT (8)
+#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M(n) (((n)&15)<<12)
+#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M_MASK (15<<12)
+#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M_SHIFT (12)
+#define SYS_CTRL_AP_ARAP_L2CC_1_M   (1<<16)
+#define SYS_CTRL_AP_AWAP_L2CC_1_M   (1<<17)
+#define SYS_CTRL_AP_ARAP_MODEM_MEM_AHBS_M (1<<18)
+#define SYS_CTRL_AP_AWAP_MODEM_MEM_AHBS_M (1<<19)
+#define SYS_CTRL_AP_ARAP_MERGE1M    (1<<20)
+#define SYS_CTRL_AP_AWAP_MERGE1M    (1<<21)
+#define SYS_CTRL_AP_ARAP_MERGE2M    (1<<22)
+#define SYS_CTRL_AP_AWAP_MERGE2M    (1<<23)
+#define SYS_CTRL_AP_RESERVE1(n)     (((n)&0xFF)<<24)
+#define SYS_CTRL_AP_RESERVE1_MASK   (0xFF<<24)
+#define SYS_CTRL_AP_RESERVE1_SHIFT  (24)
+
+//Spi_Ctrl
+#define SYS_CTRL_AP_LIMITED_EN_SPI1 (1<<0)
+#define SYS_CTRL_AP_LPSEN_SPI1      (1<<1)
+#define SYS_CTRL_AP_LIMITED_EN_SPI2 (1<<2)
+#define SYS_CTRL_AP_LPSEN_SPI2      (1<<3)
+#define SYS_CTRL_AP_LIMITED_EN_SPI3 (1<<4)
+#define SYS_CTRL_AP_LPSEN_SPI3      (1<<5)
+#define SYS_CTRL_AP_FBUSWID_NFSC    (1<<6)
+#define SYS_CTRL_AP_RESERVE3        (1<<7)
+#define SYS_CTRL_AP_DMC_CFG(n)      (((n)&0x3FF)<<8)
+#define SYS_CTRL_AP_DMC_CFG_MASK    (0x3FF<<8)
+#define SYS_CTRL_AP_DMC_CFG_SHIFT   (8)
+#define SYS_CTRL_AP_RESERVE2(n)     (((n)&0x3FFF)<<18)
+#define SYS_CTRL_AP_RESERVE2_MASK   (0x3FFF<<18)
+#define SYS_CTRL_AP_RESERVE2_SHIFT  (18)
+
+//Memory_Margin
+#define SYS_CTRL_AP_EMAW_VOC(n)     (((n)&3)<<0)
+#define SYS_CTRL_AP_EMAW_VOC_MASK   (3<<0)
+#define SYS_CTRL_AP_EMAW_VOC_SHIFT  (0)
+#define SYS_CTRL_AP_EMA_VOC(n)      (((n)&7)<<2)
+#define SYS_CTRL_AP_EMA_VOC_MASK    (7<<2)
+#define SYS_CTRL_AP_EMA_VOC_SHIFT   (2)
+#define SYS_CTRL_AP_EMAW_VPU(n)     (((n)&3)<<5)
+#define SYS_CTRL_AP_EMAW_VPU_MASK   (3<<5)
+#define SYS_CTRL_AP_EMAW_VPU_SHIFT  (5)
+#define SYS_CTRL_AP_EMA_VPU(n)      (((n)&7)<<7)
+#define SYS_CTRL_AP_EMA_VPU_MASK    (7<<7)
+#define SYS_CTRL_AP_EMA_VPU_SHIFT   (7)
+#define SYS_CTRL_AP_EMAW_GPU(n)     (((n)&3)<<10)
+#define SYS_CTRL_AP_EMAW_GPU_MASK   (3<<10)
+#define SYS_CTRL_AP_EMAW_GPU_SHIFT  (10)
+#define SYS_CTRL_AP_EMA_GPU(n)      (((n)&7)<<12)
+#define SYS_CTRL_AP_EMA_GPU_MASK    (7<<12)
+#define SYS_CTRL_AP_EMA_GPU_SHIFT   (12)
+#define SYS_CTRL_AP_EMAW_GOUDA(n)   (((n)&3)<<15)
+#define SYS_CTRL_AP_EMAW_GOUDA_MASK (3<<15)
+#define SYS_CTRL_AP_EMAW_GOUDA_SHIFT (15)
+#define SYS_CTRL_AP_EMA_GOUDA(n)    (((n)&7)<<17)
+#define SYS_CTRL_AP_EMA_GOUDA_MASK  (7<<17)
+#define SYS_CTRL_AP_EMA_GOUDA_SHIFT (17)
+#define SYS_CTRL_AP_EMAW_IMEM(n)    (((n)&3)<<20)
+#define SYS_CTRL_AP_EMAW_IMEM_MASK  (3<<20)
+#define SYS_CTRL_AP_EMAW_IMEM_SHIFT (20)
+#define SYS_CTRL_AP_EMA_IMEM(n)     (((n)&7)<<22)
+#define SYS_CTRL_AP_EMA_IMEM_MASK   (7<<22)
+#define SYS_CTRL_AP_EMA_IMEM_SHIFT  (22)
+#define SYS_CTRL_AP_EMAW_USB(n)     (((n)&3)<<25)
+#define SYS_CTRL_AP_EMAW_USB_MASK   (3<<25)
+#define SYS_CTRL_AP_EMAW_USB_SHIFT  (25)
+#define SYS_CTRL_AP_EMA_USB(n)      (((n)&7)<<27)
+#define SYS_CTRL_AP_EMA_USB_MASK    (7<<27)
+#define SYS_CTRL_AP_EMA_USB_SHIFT   (27)
+
+//Memory_Margin2
+#define SYS_CTRL_AP_EMAW_NFSC(n)    (((n)&3)<<0)
+#define SYS_CTRL_AP_EMAW_NFSC_MASK  (3<<0)
+#define SYS_CTRL_AP_EMAW_NFSC_SHIFT (0)
+#define SYS_CTRL_AP_EMA_NFSC(n)     (((n)&7)<<2)
+#define SYS_CTRL_AP_EMA_NFSC_MASK   (7<<2)
+#define SYS_CTRL_AP_EMA_NFSC_SHIFT  (2)
+#define SYS_CTRL_AP_EMA_VPUROM(n)   (((n)&7)<<5)
+#define SYS_CTRL_AP_EMA_VPUROM_MASK (7<<5)
+#define SYS_CTRL_AP_EMA_VPUROM_SHIFT (5)
+#define SYS_CTRL_AP_EMA_IMEMROM(n)  (((n)&7)<<8)
+#define SYS_CTRL_AP_EMA_IMEMROM_MASK (7<<8)
+#define SYS_CTRL_AP_EMA_IMEMROM_SHIFT (8)
+#define SYS_CTRL_AP_KEN_VPUROM      (1<<11)
+#define SYS_CTRL_AP_PGEN_VPUROM     (1<<12)
+#define SYS_CTRL_AP_KEN_IMEMROM     (1<<13)
+#define SYS_CTRL_AP_PGEN_IMEMROM    (1<<14)
+
+//Memory_Observe
+#define SYS_CTRL_AP_MEM_OBSERVE(n)  (((n)&0xFFFFFFFF)<<0)
+
+//Cfg_Clk_AP_VOC2
+#define SYS_CTRL_AP_AP_VOC2_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_VOC2_FREQ_MASK (31 << 0)
+#define SYS_CTRL_AP_AP_VOC2_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_VOC2_SRC_DIV2  (1<<12)
+#define SYS_CTRL_AP_AP_VOC2_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_EMMC
+#define SYS_CTRL_AP_EMMC_DATA_STB_DLY(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_EMMC_DATA_STB_DLY_MASK (31 << 0)
+#define SYS_CTRL_AP_EMMC_DATA_STB_DLY_SHIFT 0
+#define SYS_CTRL_AP_EMMC_CLK_DLY(n)  (((n)&31)<<8)
+#define SYS_CTRL_AP_EMMC_CLK_DLY_MASK (31 << 8)
+#define SYS_CTRL_AP_EMMC_CLK_DLY_SHIFT 8
+#define SYS_CTRL_AP_EMMC_CLK_POL  (1<<13)
+
+//Test_Pulse
+#define SYS_CTRL_AP_PULSE_COUNTER(n)  (((n)&0xFFFFFFFF)<<0)
+
+//Cfg_Reserve
+#define SYS_CTRL_AP_RESERVE(n)      (((n)&0xFFFFFFFF)<<0)
+
+#endif
diff --git a/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8810h.h b/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8810h.h
new file mode 100644
index 0000000000..ab7ba4c951
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8810h.h
@@ -0,0 +1,1578 @@
+#ifndef _REG_SYSCTRL_H_
+#define _REG_SYSCTRL_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+
+// ============================================================================
+// AP_CPU_ID_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// CPU IDs
+    CPU0                                        = 0x00000000,
+    CPU1                                        = 0x00000001
+} AP_CPU_ID_T;
+
+
+// ============================================================================
+// CPU_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP CPU side System clocks
+    CPU_CORE                                    = 0x00000000,
+/// the following don't have an auto enable
+    CPU_DUMMY                                   = 0x00000001
+} CPU_CLKS_T;
+
+#define NB_CPU_CLK_AEN                           (1)
+#define NB_CPU_CLK_EN                            (2)
+#define NB_CPU_CLK                               (2)
+
+// ============================================================================
+// AXI_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AXI side System clocks: AXI and AHB0 and APB0
+    AHB0_CONF                                   = 0x00000000,
+    APB0_CONF                                   = 0x00000001,
+    AXI_VOC                                     = 0x00000002,
+    AXI_DMA                                     = 0x00000003,
+/// the following don't have an auto enable
+    AXI_ALWAYS                                  = 0x00000004,
+    AXI_CONNECT                                 = 0x00000005,
+    APB0_IRQ                                    = 0x00000006
+} AXI_CLKS_T;
+
+#define NB_AXI_CLK_AEN                           (4)
+#define NB_AXI_CLK_EN                            (7)
+#define NB_AXI_CLK                               (7)
+
+// ============================================================================
+// AXIDIV2_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AXIdiv2 side System clocks
+    AXIDIV2_IMEM                                = 0x00000000,
+/// the following don't have an auto enable
+    AXIDIV2_ALWAYS                              = 0x00000001,
+    AXIDIV2_CONNECT                             = 0x00000002,
+    AXIDIV2_VPU                                 = 0x00000003
+} AXIDIV2_CLKS_T;
+
+#define NB_AXIDIV2_CLK_AEN                       (1)
+#define NB_AXIDIV2_CLK_EN                        (4)
+#define NB_AXIDIV2_CLK                           (4)
+
+// ============================================================================
+// GCG_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP GCG side System clocks
+    GCG_APB_CONF                                = 0x00000000,
+    GCG_GOUDA                                   = 0x00000001,
+    GCG_CAMERA                                  = 0x00000002,
+/// the following don't have an auto enable
+    GCG_ALWAYS                                  = 0x00000003,
+    GCG_CONNECT                                 = 0x00000004
+} GCG_CLKS_T;
+
+#define NB_GCG_CLK_AEN                           (3)
+#define NB_GCG_CLK_EN                            (5)
+#define NB_GCG_CLK                               (5)
+
+// ============================================================================
+// AHB1_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AHB1 side System clocks
+    AHB1_USBC                                   = 0x00000000,
+/// the following don't have an auto enable
+    AHB1_ALWAYS                                 = 0x00000001,
+    AHB1_SPIFLASH                               = 0x00000002
+} AHB1_CLKS_T;
+
+#define NB_AHB1_CLK_AEN                          (1)
+#define NB_AHB1_CLK_EN                           (3)
+#define NB_AHB1_CLK                              (3)
+
+// ============================================================================
+// APB1_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP APB1 side System clocks
+    APB1_CONF                                   = 0x00000000,
+    APB1_AIF                                    = 0x00000001,
+    APB1_AUIFC                                  = 0x00000002,
+    APB1_AUIFC_CH0                              = 0x00000003,
+    APB1_AUIFC_CH1                              = 0x00000004,
+    APB1_I2C1                                   = 0x00000005,
+    APB1_I2C2                                   = 0x00000006,
+    APB1_I2C3                                   = 0x00000007,
+/// AP APB1 side divided clock (either divided by module or by clock_ctrl)
+    APB1D_OSC                                   = 0x00000008,
+    APB1D_PWM                                   = 0x00000009,
+/// the following don't have an auto enable
+    APB1_ALWAYS                                 = 0x0000000A,
+    APB1_DAPLITE                                = 0x0000000B,
+    APB1_TIMER                                  = 0x0000000C,
+    APB1_GPIO                                   = 0x0000000D
+} APB1_CLKS_T;
+
+#define NB_APB1_CLK_AEN                          (10)
+#define NB_APB1_CLK_EN                           (14)
+#define NB_APB1_CLK                              (14)
+
+// ============================================================================
+// APB2_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP APB2 side System clocks
+    APB2_CONF                                   = 0x00000000,
+    APB2_IFC                                    = 0x00000001,
+    APB2_IFC_CH0                                = 0x00000002,
+    APB2_IFC_CH1                                = 0x00000003,
+    APB2_IFC_CH2                                = 0x00000004,
+    APB2_IFC_CH3                                = 0x00000005,
+    APB2_IFC_CH4                                = 0x00000006,
+    APB2_IFC_CH5                                = 0x00000007,
+    APB2_IFC_CH6                                = 0x00000008,
+    APB2_IFC_CH7                                = 0x00000009,
+    APB2_UART1                                  = 0x0000000A,
+    APB2_UART2                                  = 0x0000000B,
+    APB2_UART3                                  = 0x0000000C,
+    APB2_SPI1                                   = 0x0000000D,
+    APB2_SPI2                                   = 0x0000000E,
+    APB2_SPI3                                   = 0x0000000F,
+    APB2_SDMMC1                                 = 0x00000010,
+    APB2_SDMMC2                                 = 0x00000011,
+    APB2_SDMMC3                                 = 0x00000012,
+/// the following don't have an auto enable
+    APB2_ALWAYS                                 = 0x00000013,
+    APB2_NANDFLASH                              = 0x00000014
+} APB2_CLKS_T;
+
+#define NB_APB2_CLK_AEN                          (19)
+#define NB_APB2_CLK_EN                           (21)
+#define NB_APB2_CLK                              (21)
+
+// ============================================================================
+// MEM_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP MEM side System clocks
+    MEM_CONF                                    = 0x00000000,
+/// the following don't have an auto enable
+    MEM_DMC                                     = 0x00000001,
+    MEM_GPU                                     = 0x00000002,
+    MEM_VPU                                     = 0x00000003,
+    MEM_DDRPHY_P                                = 0x00000004,
+    MEM_CONNECT                                 = 0x00000005
+} MEM_CLKS_T;
+
+#define NB_MEM_CLK_AEN                           (1)
+#define NB_MEM_CLK_EN                            (6)
+#define NB_MEM_CLK                               (6)
+
+// ============================================================================
+// APO_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP side Other clocks
+/// clocks with auto enble
+    APOC_VPU                                    = 0x00000000,
+    APOC_BCK                                    = 0x00000001,
+    APOC_UART1                                  = 0x00000002,
+    APOC_UART2                                  = 0x00000003,
+    APOC_UART3                                  = 0x00000004,
+    APOC_VOC_CORE                               = 0x00000005,
+    APOC_VOC                                    = 0x00000006,
+/// the following don't have an auto enable
+    APOC_VOC_ALWAYS                             = 0x00000007,
+    APOC_DDRPHY_N                               = 0x00000008,
+    APOC_DDRPHY2XP                              = 0x00000009,
+    APOC_DDRPHY2XN                              = 0x0000000A,
+    APOC_GPU                                    = 0x0000000B,
+    APOC_USBPHY                                 = 0x0000000C,
+    APOC_CSI                                    = 0x0000000D,
+    APOC_DSI                                    = 0x0000000E,
+    APOC_GPIO                                   = 0x0000000F,
+    APOC_SPIFLASH                               = 0x00000010,
+    APOC_PIX                                    = 0x00000011,
+    APOC_PDGB                                   = 0x00000012
+} APO_CLKS_T;
+
+#define NB_CLK_VOC_AEN_SYNC                      (5)
+#define NB_CLK_VOC_CORE                          (6)
+#define NB_APO_CLK_AEN                           (7)
+#define NB_CLK_VOC_END                           (8)
+#define NB_APO_CLK_EN                            (19)
+#define NB_APO_CLK                               (19)
+
+// ============================================================================
+// CPU_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP CPU side resets
+    CPU_RST_CORE                                = 0x00000000,
+    CPU_RST_SYS                                 = 0x00000001
+} CPU_RESETS_T;
+
+#define NB_CPU_RST                               (2)
+
+// ============================================================================
+// AXI_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AXI side resets: AXI and AHB0 and APB0
+    AXI_RST_VOC                                 = 0x00000000,
+    AXI_RST_DMA                                 = 0x00000001,
+    AXI_RST_SYS                                 = 0x00000002,
+    AXI_RST_CONNECT                             = 0x00000003,
+    AHB0_RST_GPU                                = 0x00000004,
+    APB0_RST_VPU                                = 0x00000005,
+    APB0_RST_IRQ                                = 0x00000006
+} AXI_RESETS_T;
+
+#define NB_AXI_RST                               (7)
+
+// ============================================================================
+// AXIDIV2_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AXIDIV2 side resets
+    AXIDIV2_RST_IMEM                            = 0x00000000,
+    AXIDIV2_RST_SYS                             = 0x00000001,
+    AXIDIV2_RST_VPU                             = 0x00000002
+} AXIDIV2_RESETS_T;
+
+#define NB_AXIDIV2_RST                           (3)
+
+// ============================================================================
+// GCG_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP GCG side resets
+    GCG_RST_SYS                                 = 0x00000000,
+    GCG_RST_GOUDA                               = 0x00000001,
+    GCG_RST_CAMERA                              = 0x00000002
+} GCG_RESETS_T;
+
+#define NB_GCG_RST                               (3)
+
+// ============================================================================
+// AHB1_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AHB1 side resets
+    AHB1_RST_SYS                                = 0x00000000,
+    AHB1_RST_USBC                               = 0x00000001,
+    AHB1_RST_SPIFLASH                           = 0x00000002
+} AHB1_RESETS_T;
+
+#define NB_AHB1_RST                              (3)
+
+// ============================================================================
+// APB1_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP APB1 side resets
+    APB1_RST_SYS                                = 0x00000000,
+    APB1_RST_TIMER                              = 0x00000001,
+    APB1_RST_KEYPAD                             = 0x00000002,
+    APB1_RST_GPIO                               = 0x00000003,
+    APB1_RST_PWM                                = 0x00000004,
+    APB1_RST_AIF                                = 0x00000005,
+    APB1_RST_AUIFC                              = 0x00000006,
+    APB1_RST_I2C1                               = 0x00000007,
+    APB1_RST_I2C2                               = 0x00000008,
+    APB1_RST_I2C3                               = 0x00000009,
+    APB1_RST_COM_REGS                           = 0x0000000A,
+    APB1_RST_DMC                                = 0x0000000B,
+    APB1_RST_DDRPHY_P                           = 0x0000000C,
+    APB1_RST_BB2G_XCPU                          = 0x0000000D,
+    APB1_RST_BB2G_BCPU                          = 0x0000000E,
+    APB1_RST_BB2G_AHBC                          = 0x0000000F,
+    APB1_RST_BB2G_DMA                           = 0x00000010,
+    APB1_RST_BB2G_A2A                           = 0x00000011,
+    APB1_RST_BB2G_XIFC                          = 0x00000012,
+    APB1_RST_BB2G_BIFC                          = 0x00000013,
+    APB1_RST_BB2G_BAHBC                         = 0x00000014,
+    APB1_RST_BB2G_MEM_BRIDGE                    = 0x00000015
+} APB1_RESETS_T;
+
+#define NB_APB1_RST                              (22)
+
+// ============================================================================
+// APB2_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP APB2 side resets
+    APB2_RST_SYS                                = 0x00000000,
+    APB2_RST_IFC                                = 0x00000001,
+    APB2_RST_UART1                              = 0x00000002,
+    APB2_RST_UART2                              = 0x00000003,
+    APB2_RST_UART3                              = 0x00000004,
+    APB2_RST_SPI1                               = 0x00000005,
+    APB2_RST_SPI2                               = 0x00000006,
+    APB2_RST_SPI3                               = 0x00000007,
+    APB2_RST_SDMMC1                             = 0x00000008,
+    APB2_RST_SDMMC2                             = 0x00000009,
+    APB2_RST_SDMMC3                             = 0x0000000A,
+    APB2_RST_NANDFLASH                          = 0x0000000B
+} APB2_RESETS_T;
+
+#define NB_APB2_RST                              (12)
+
+// ============================================================================
+// MEM_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP MEM side resets
+    MEM_RST_SYS                                 = 0x00000000,
+    MEM_RST_GPU                                 = 0x00000001,
+    MEM_RST_VPU                                 = 0x00000002,
+    MEM_RST_DMC                                 = 0x00000003,
+    MEM_RST_DDRPHY_P                            = 0x00000004
+} MEM_RESETS_T;
+
+#define NB_MEM_RST                               (5)
+
+// ============================================================================
+// AP_OTHERS_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP Reset Other : resync on corresponding clock other
+    AP_RSTO_VOC                                 = 0x00000000,
+    AP_RSTO_DDRPHY_N                            = 0x00000001,
+    AP_RSTO_DDRPHY2XP                           = 0x00000002,
+    AP_RSTO_DDRPHY2XN                           = 0x00000003,
+    AP_RSTO_GPU                                 = 0x00000004,
+    AP_RSTO_VPU                                 = 0x00000005,
+    AP_RSTO_BCK                                 = 0x00000006,
+    AP_RSTO_UART1                               = 0x00000007,
+    AP_RSTO_UART2                               = 0x00000008,
+    AP_RSTO_UART3                               = 0x00000009,
+    AP_RSTO_GPIO                                = 0x0000000A,
+    AP_RSTO_TIMER                               = 0x0000000B,
+    AP_RSTO_USBC                                = 0x0000000C,
+    AP_RSTO_DSI                                 = 0x0000000D,
+    AP_RSTO_SPIFLASH                            = 0x0000000E,
+    AP_RSTO_TCK                                 = 0x0000000F,
+    AP_RSTO_PDBG_XTAL                           = 0x00000010
+} AP_OTHERS_RESETS_T;
+
+#define NB_AP_RSTO                               (17)
+/// For REG_DBG protect lock/unlock value
+#define AP_CTRL_PROTECT_LOCK                     (0XA50000)
+#define AP_CTRL_PROTECT_UNLOCK                   (0XA50001)
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+// ============================================================================
+// SYS_CTRL_AP_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef volatile struct
+{
+    /// <strong>This register is used to Lock and Unlock the protected registers.</strong>
+    REG32                          REG_DBG;                      //0x00000000
+    /// Register protected by Write_Unlocked_H.
+    REG32                          Cfg_Pll_Ctrl[4];              //0x00000004
+    /// This register is protected.
+    REG32                          Sel_Clock;                    //0x00000014
+    REG32                          Reset_Cause;                  //0x00000018
+    /// This register is protected.
+    REG32                          CPU_Rst_Set;                  //0x0000001C
+    REG32                          CPU_Rst_Clr;                  //0x00000020
+    /// This register is protected.
+    REG32                          AXI_Rst_Set;                  //0x00000024
+    REG32                          AXI_Rst_Clr;                  //0x00000028
+    /// This register is protected.
+    REG32                          AXIDIV2_Rst_Set;              //0x0000002C
+    REG32                          AXIDIV2_Rst_Clr;              //0x00000030
+    /// This register is protected.
+    REG32                          GCG_Rst_Set;                  //0x00000034
+    REG32                          GCG_Rst_Clr;                  //0x00000038
+    /// This register is protected.
+    REG32                          AHB1_Rst_Set;                 //0x0000003C
+    REG32                          AHB1_Rst_Clr;                 //0x00000040
+    /// This register is protected.
+    REG32                          APB1_Rst_Set;                 //0x00000044
+    REG32                          APB1_Rst_Clr;                 //0x00000048
+    /// This register is protected.
+    REG32                          APB2_Rst_Set;                 //0x0000004C
+    REG32                          APB2_Rst_Clr;                 //0x00000050
+    /// This register is protected.
+    REG32                          MEM_Rst_Set;                  //0x00000054
+    REG32                          MEM_Rst_Clr;                  //0x00000058
+    REG32                          Clk_CPU_Mode;                 //0x0000005C
+    REG32                          Clk_CPU_Enable;               //0x00000060
+    /// This register is protected.
+    REG32                          Clk_CPU_Disable;              //0x00000064
+    REG32                          Clk_AXI_Mode;                 //0x00000068
+    REG32                          Clk_AXI_Enable;               //0x0000006C
+    /// This register is protected.
+    REG32                          Clk_AXI_Disable;              //0x00000070
+    REG32                          Clk_AXIDIV2_Mode;             //0x00000074
+    REG32                          Clk_AXIDIV2_Enable;           //0x00000078
+    /// This register is protected.
+    REG32                          Clk_AXIDIV2_Disable;          //0x0000007C
+    REG32                          Clk_GCG_Mode;                 //0x00000080
+    REG32                          Clk_GCG_Enable;               //0x00000084
+    /// This register is protected.
+    REG32                          Clk_GCG_Disable;              //0x00000088
+    REG32                          Clk_AHB1_Mode;                //0x0000008C
+    REG32                          Clk_AHB1_Enable;              //0x00000090
+    /// This register is protected.
+    REG32                          Clk_AHB1_Disable;             //0x00000094
+    REG32                          Clk_APB1_Mode;                //0x00000098
+    REG32                          Clk_APB1_Enable;              //0x0000009C
+    /// This register is protected.
+    REG32                          Clk_APB1_Disable;             //0x000000A0
+    REG32                          Clk_APB2_Mode;                //0x000000A4
+    REG32                          Clk_APB2_Enable;              //0x000000A8
+    /// This register is protected.
+    REG32                          Clk_APB2_Disable;             //0x000000AC
+    REG32                          Clk_MEM_Mode;                 //0x000000B0
+    REG32                          Clk_MEM_Enable;               //0x000000B4
+    /// This register is protected.
+    REG32                          Clk_MEM_Disable;              //0x000000B8
+    REG32                          Clk_APO_Mode;                 //0x000000BC
+    REG32                          Clk_APO_Enable;               //0x000000C0
+    /// This register is protected.
+    REG32                          Clk_APO_Disable;              //0x000000C4
+    REG32                          Cfg_Clk_AP_CPU;               //0x000000C8
+    REG32                          Cfg_Clk_AP_AXI;               //0x000000CC
+    REG32                          Cfg_Clk_AP_GCG;               //0x000000D0
+    REG32                          Cfg_Clk_AP_AHB1;              //0x000000D4
+    REG32                          Cfg_Clk_AP_APB1;              //0x000000D8
+    REG32                          Cfg_Clk_AP_APB2;              //0x000000DC
+    REG32                          Cfg_Clk_AP_MEM;               //0x000000E0
+    REG32                          Cfg_Clk_AP_GPU;               //0x000000E4
+    REG32                          Cfg_Clk_AP_VPU;               //0x000000E8
+    REG32                          Cfg_Clk_AP_VOC;               //0x000000EC
+    REG32                          Cfg_Clk_AP_SFLSH;             //0x000000F0
+    REG32                          Cfg_Clk_Uart[3];              //0x000000F4
+    REG32                          L2cc_Ctrl;                    //0x00000100
+    REG32                          Spi_Ctrl;                     //0x00000104
+    REG32                          Memory_Margin;                //0x00000108
+    REG32                          Memory_Margin2;               //0x0000010C
+    REG32                          Memory_Observe;               //0x00000110
+    REG32                          Cfg_Clk_AP_VOC2;               //0x00000114
+    REG32                          Cfg_Clk_EMMC;               //0x00000118
+    REG32                          Test_Pulse;               //0x0000011C
+    REG32 Reserved_00000114[49];                //0x00000120
+    /// This register is reserved.
+    REG32                          Cfg_Cpu_Reserve0;                  //0x000001E4
+    REG32                          Cfg_Cpu_Reserve1;                  //0x000001E8
+    REG32                          Cfg_Cpu_Reserve2;                  //0x000001EC
+    REG32                          Cfg_Cpu_Reserve3;                  //0x000001F0
+    REG32                          Cfg_Cpu_Reserve4;                  //0x000001F4
+    REG32                          Cfg_Cpu_Reserve5;                  //0x000001F8
+    REG32                          Cfg_Reserve;                  //0x000001FC
+} HWP_SYS_CTRL_AP_T;
+
+#define hwp_sysCtrlAp               ((HWP_SYS_CTRL_AP_T*)(RDA_SYSCTRL_BASE))
+
+
+//REG_DBG
+#define SYS_CTRL_AP_SCRATCH(n)      (((n)&0xFFFF)<<0)
+#define SYS_CTRL_AP_WRITE_UNLOCK_STATUS (1<<30)
+#define SYS_CTRL_AP_WRITE_UNLOCK    (1<<31)
+
+//Cfg_Pll_Ctrl
+#define SYS_CTRL_AP_AP_PLL_ENABLE   (1<<0)
+#define SYS_CTRL_AP_AP_PLL_ENABLE_MASK (1<<0)
+#define SYS_CTRL_AP_AP_PLL_ENABLE_SHIFT (0)
+#define SYS_CTRL_AP_AP_PLL_ENABLE_POWER_DOWN (0<<0)
+#define SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE (1<<0)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET (1<<4)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_MASK (1<<4)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_SHIFT (4)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_RESET (0<<4)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET (1<<4)
+#define SYS_CTRL_AP_AP_PLL_BYPASS   (1<<8)
+#define SYS_CTRL_AP_AP_PLL_BYPASS_MASK (1<<8)
+#define SYS_CTRL_AP_AP_PLL_BYPASS_SHIFT (8)
+#define SYS_CTRL_AP_AP_PLL_BYPASS_PASS (0<<8)
+#define SYS_CTRL_AP_AP_PLL_BYPASS_BYPASS (1<<8)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE (1<<12)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_MASK (1<<12)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_SHIFT (12)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_ENABLE (1<<12)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_DISABLE (0<<12)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(n) (((n)&31)<<16)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW_MASK (31<<16)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW_SHIFT (16)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(n) (((n)&31)<<24)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH_MASK (31<<24)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH_SHIFT (24)
+#define SYS_CTRL_AP_PLL_AP_CFG(n)   (((n)&0x1F1F1111)<<0)
+#define SYS_CTRL_AP_PLL_AP_CFG_MASK (0x1F1F1111<<0)
+#define SYS_CTRL_AP_PLL_AP_CFG_SHIFT (0)
+
+//Sel_Clock
+#define SYS_CTRL_AP_SLOW_SEL_RF_OSCILLATOR (1<<0)
+#define SYS_CTRL_AP_SLOW_SEL_RF_RF  (0<<0)
+#define SYS_CTRL_AP_TIMER_SEL_FAST_SLOW (1<<1)
+#define SYS_CTRL_AP_TIMER_SEL_FAST_FAST (0<<1)
+#define SYS_CTRL_AP_TIMER2_SEL_FAST_SLOW (1<<2)
+#define SYS_CTRL_AP_TIMER2_SEL_FAST_FAST (0<<2)
+#define SYS_CTRL_AP_TIMER3_SEL_FAST_SLOW (1<<3)
+#define SYS_CTRL_AP_TIMER3_SEL_FAST_FAST (0<<3)
+#define SYS_CTRL_AP_CPU_SEL_FAST_SLOW (1<<4)
+#define SYS_CTRL_AP_CPU_SEL_FAST_FAST (0<<4)
+#define SYS_CTRL_AP_BUS_SEL_FAST_SLOW (1<<5)
+#define SYS_CTRL_AP_BUS_SEL_FAST_FAST (0<<5)
+#define SYS_CTRL_AP_RF_DETECTED_OK  (1<<8)
+#define SYS_CTRL_AP_RF_DETECTED_NO  (0<<8)
+#define SYS_CTRL_AP_RF_DETECT_BYPASS (1<<9)
+#define SYS_CTRL_AP_RF_DETECT_RESET (1<<10)
+#define SYS_CTRL_AP_RF_SELECTED_L   (1<<11)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU  (1<<12)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU_MASK (1<<12)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU_SHIFT (12)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU_LOCKED (1<<12)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU_NOT_LOCKED (0<<12)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS  (1<<13)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS_MASK (1<<13)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS_SHIFT (13)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS_LOCKED (1<<13)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS_NOT_LOCKED (0<<13)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM  (1<<14)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM_MASK (1<<14)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM_SHIFT (14)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM_LOCKED (1<<14)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM_NOT_LOCKED (0<<14)
+#define SYS_CTRL_AP_PLL_LOCKED_USB  (1<<15)
+#define SYS_CTRL_AP_PLL_LOCKED_USB_MASK (1<<15)
+#define SYS_CTRL_AP_PLL_LOCKED_USB_SHIFT (15)
+#define SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED (1<<15)
+#define SYS_CTRL_AP_PLL_LOCKED_USB_NOT_LOCKED (0<<15)
+#define SYS_CTRL_AP_PLL_BYPASS_LOCK_CPU (1<<20)
+#define SYS_CTRL_AP_PLL_BYPASS_LOCK_BUS (1<<21)
+#define SYS_CTRL_AP_FAST_SELECTED_CPU_L (1<<30)
+#define SYS_CTRL_AP_FAST_SELECTED_CPU_L_MASK (1<<30)
+#define SYS_CTRL_AP_FAST_SELECTED_CPU_L_SHIFT (30)
+#define SYS_CTRL_AP_FAST_SELECTED_BUS_L (1<<31)
+#define SYS_CTRL_AP_FAST_SELECTED_BUS_L_MASK (1<<31)
+#define SYS_CTRL_AP_FAST_SELECTED_BUS_L_SHIFT (31)
+
+//Reset_Cause
+#define SYS_CTRL_AP_WATCHDOG_RESET_HAPPENED (1<<0)
+#define SYS_CTRL_AP_WATCHDOG_RESET_NO (0<<0)
+#define SYS_CTRL_AP_GLOBALSOFT_RESET_HAPPENED (1<<4)
+#define SYS_CTRL_AP_GLOBALSOFT_RESET_NO (0<<4)
+#define SYS_CTRL_AP_HOSTDEBUG_RESET_HAPPENED (1<<5)
+#define SYS_CTRL_AP_HOSTDEBUG_RESET_NO (0<<5)
+#define SYS_CTRL_AP_ALARMCAUSE_HAPPENED (1<<6)
+#define SYS_CTRL_AP_ALARMCAUSE_NO   (0<<6)
+#define SYS_CTRL_AP_BOOT_MODE(n)    (((n)&0xFFFF)<<8)
+#define SYS_CTRL_AP_BOOT_MODE_MASK  (0xFFFF<<8)
+#define SYS_CTRL_AP_BOOT_MODE_SHIFT (8)
+#define SYS_CTRL_AP_SW_BOOT_MODE(n) (((n)&0x7F)<<24)
+#define SYS_CTRL_AP_SW_BOOT_MODE_MASK (0x7F<<24)
+#define SYS_CTRL_AP_SW_BOOT_MODE_SHIFT (24)
+#define SYS_CTRL_AP_FONCTIONAL_TEST_MODE (1<<31)
+
+//CPU_Rst_Set
+#define SYS_CTRL_AP_SET_CPU_RST_CORE (1<<0)
+#define SYS_CTRL_AP_SET_CPU_RST_CORE1 (1<<1)
+#define SYS_CTRL_AP_SET_CPU_RST_CORE2 (1<<2)
+#define SYS_CTRL_AP_SET_CPU_RST_CORE3 (1<<3)
+#define SYS_CTRL_AP_SET_CPU_RST_L2 (1<<4)
+#define SYS_CTRL_AP_SET_CPU_RST_SYS (1<<5)
+#define SYS_CTRL_AP_SOFT_RST        (1<<31)
+#define SYS_CTRL_AP_SET_CPU_RST(n)  (((n)&0xF)<<0)
+#define SYS_CTRL_AP_SET_CPU_RST_MASK (0xF<<0)
+#define SYS_CTRL_AP_SET_CPU_RST_SHIFT (0)
+
+//CPU_Rst_Clr
+#define SYS_CTRL_AP_CLR_CPU_RST_CORE (1<<0)
+#define SYS_CTRL_AP_CLR_CPU_RST_CORE1 (1<<1)
+#define SYS_CTRL_AP_CLR_CPU_RST_CORE2 (1<<2)
+#define SYS_CTRL_AP_CLR_CPU_RST_CORE3 (1<<3)
+#define SYS_CTRL_AP_CLR_CPU_RST_L2 (1<<4)
+#define SYS_CTRL_AP_CLR_CPU_RST_SYS (1<<5)
+#define SYS_CTRL_AP_CLR_CPU_RST(n)  (((n)&0xF)<<0)
+#define SYS_CTRL_AP_CLR_CPU_RST_MASK (0xF<<0)
+#define SYS_CTRL_AP_CLR_CPU_RST_SHIFT (0)
+
+//AXI_Rst_Set
+#define SYS_CTRL_AP_SET_AXI_RST_VOC (1<<0)
+#define SYS_CTRL_AP_SET_AXI_RST_VOC2 (1<<1)
+#define SYS_CTRL_AP_SET_AXI_RST_DMA (1<<2)
+#define SYS_CTRL_AP_SET_AXI_RST_SYS (1<<3)
+#define SYS_CTRL_AP_SET_AXI_RST_CONNECT (1<<4)
+#define SYS_CTRL_AP_SET_APB0_RST_GPU (1<<5)
+#define SYS_CTRL_AP_SET_APB0_RST_VPU (1<<6)
+#define SYS_CTRL_AP_SET_APB0_RST_IRQ (1<<7)
+#define SYS_CTRL_AP_SET_AXI_RST(n)  (((n)&0xFF)<<0)
+#define SYS_CTRL_AP_SET_AXI_RST_MASK (0xFF<<0)
+#define SYS_CTRL_AP_SET_AXI_RST_SHIFT (0)
+
+//AXI_Rst_Clr
+#define SYS_CTRL_AP_CLR_AXI_RST_VOC (1<<0)
+#define SYS_CTRL_AP_CLR_AXI_RST_VOC2 (1<<1)
+#define SYS_CTRL_AP_CLR_AXI_RST_DMA (1<<2)
+#define SYS_CTRL_AP_CLR_AXI_RST_SYS (1<<3)
+#define SYS_CTRL_AP_CLR_AXI_RST_CONNECT (1<<4)
+#define SYS_CTRL_AP_CLR_APB0_RST_GPU (1<<5)
+#define SYS_CTRL_AP_CLR_APB0_RST_VPU (1<<6)
+#define SYS_CTRL_AP_CLR_APB0_RST_IRQ (1<<7)
+#define SYS_CTRL_AP_CLR_AXI_RST(n)  (((n)&0xFF)<<0)
+#define SYS_CTRL_AP_CLR_AXI_RST_MASK (0xFF<<0)
+#define SYS_CTRL_AP_CLR_AXI_RST_SHIFT (0)
+
+//AXIDIV2_Rst_Set
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_IMEM (1<<0)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_SYS (1<<1)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_VPU (1<<2)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_MASK (7<<0)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_SHIFT (0)
+
+//AXIDIV2_Rst_Clr
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_IMEM (1<<0)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_SYS (1<<1)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_VPU (1<<2)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_MASK (7<<0)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_SHIFT (0)
+
+//GCG_Rst_Set
+#define SYS_CTRL_AP_SET_GCG_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_GCG_RST_GOUDA (1<<1)
+#define SYS_CTRL_AP_SET_GCG_RST_CAMERA (1<<2)
+#define SYS_CTRL_AP_SET_GCG_RST_CAMERA2 (1<<3)
+#define SYS_CTRL_AP_SET_GCG_RST(n)  (((n)&0xF)<<0)
+#define SYS_CTRL_AP_SET_GCG_RST_MASK (0xF<<0)
+#define SYS_CTRL_AP_SET_GCG_RST_SHIFT (0)
+
+//GCG_Rst_Clr
+#define SYS_CTRL_AP_CLR_GCG_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_GCG_RST_GOUDA (1<<1)
+#define SYS_CTRL_AP_CLR_GCG_RST_CAMERA (1<<2)
+#define SYS_CTRL_AP_CLR_GCG_RST_CAMERA2 (1<<3)
+#define SYS_CTRL_AP_CLR_GCG_RST(n)  (((n)&0xF)<<0)
+#define SYS_CTRL_AP_CLR_GCG_RST_MASK (0xF<<0)
+#define SYS_CTRL_AP_CLR_GCG_RST_SHIFT (0)
+
+//AHB1_Rst_Set
+#define SYS_CTRL_AP_SET_AHB1_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_AHB1_RST_USBC (1<<1)
+#define SYS_CTRL_AP_SET_AHB1_RST_SPIFLASH (1<<2)
+#define SYS_CTRL_AP_SET_AHB1_RST_EMAC (1<<3)
+#define SYS_CTRL_AP_SET_AHB1_RST(n) (((n)&0xF)<<0)
+#define SYS_CTRL_AP_SET_AHB1_RST_MASK (0xF<<0)
+#define SYS_CTRL_AP_SET_AHB1_RST_SHIFT (0)
+
+//AHB1_Rst_Clr
+#define SYS_CTRL_AP_CLR_AHB1_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_AHB1_RST_USBC (1<<1)
+#define SYS_CTRL_AP_CLR_AHB1_RST_SPIFLASH (1<<2)
+#define SYS_CTRL_AP_CLR_AHB1_RST_EMAC (1<<3)
+#define SYS_CTRL_AP_CLR_AHB1_RST(n) (((n)&0xF)<<0)
+#define SYS_CTRL_AP_CLR_AHB1_RST_MASK (0xF<<0)
+#define SYS_CTRL_AP_CLR_AHB1_RST_SHIFT (0)
+
+//APB1_Rst_Set
+#define SYS_CTRL_AP_SET_APB1_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_APB1_RST_TIMER (1<<1)
+#define SYS_CTRL_AP_SET_APB1_RST_KEYPAD (1<<2)
+#define SYS_CTRL_AP_SET_APB1_RST_GPIO (1<<3)
+#define SYS_CTRL_AP_SET_APB1_RST_PWM (1<<4)
+#define SYS_CTRL_AP_SET_APB1_RST_AIF (1<<5)
+#define SYS_CTRL_AP_SET_APB1_RST_AIF2 (1<<6)
+#define SYS_CTRL_AP_SET_APB1_RST_AUIFC (1<<7)
+#define SYS_CTRL_AP_SET_APB1_RST_COM_REGS (1<<8)
+#define SYS_CTRL_AP_SET_APB1_RST_DMC (1<<9)
+#define SYS_CTRL_AP_SET_APB1_RST_DDRPHY_P (1<<10)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_XCPU (1<<11)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BCPU (1<<12)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_AHBC (1<<13)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_DMA (1<<14)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_A2A (1<<15)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_XIFC (1<<16)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BIFC (1<<17)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BAHBC (1<<18)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_MEM_BRIDGE (1<<19)
+#define SYS_CTRL_AP_SET_APB1_RST(n) (((n)&0xFFFFF)<<0)
+#define SYS_CTRL_AP_SET_APB1_RST_MASK (0xFFFFF<<0)
+#define SYS_CTRL_AP_SET_APB1_RST_SHIFT (0)
+
+//APB1_Rst_Clr
+#define SYS_CTRL_AP_CLR_APB1_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_APB1_RST_TIMER (1<<1)
+#define SYS_CTRL_AP_CLR_APB1_RST_KEYPAD (1<<2)
+#define SYS_CTRL_AP_CLR_APB1_RST_GPIO (1<<3)
+#define SYS_CTRL_AP_CLR_APB1_RST_PWM (1<<4)
+#define SYS_CTRL_AP_CLR_APB1_RST_AIF (1<<5)
+#define SYS_CTRL_AP_CLR_APB1_RST_AIF2 (1<<6)
+#define SYS_CTRL_AP_CLR_APB1_RST_AUIFC (1<<7)
+#define SYS_CTRL_AP_CLR_APB1_RST_COM_REGS (1<<8)
+#define SYS_CTRL_AP_CLR_APB1_RST_DMC (1<<9)
+#define SYS_CTRL_AP_CLR_APB1_RST_DDRPHY_P (1<<10)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_XCPU (1<<11)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BCPU (1<<12)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_AHBC (1<<13)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_DMA (1<<14)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_A2A (1<<15)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_XIFC (1<<16)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BIFC (1<<17)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BAHBC (1<<18)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_MEM_BRIDGE (1<<19)
+#define SYS_CTRL_AP_CLR_APB1_RST(n) (((n)&0xFFFFF)<<0)
+#define SYS_CTRL_AP_CLR_APB1_RST_MASK (0xFFFFF<<0)
+#define SYS_CTRL_AP_CLR_APB1_RST_SHIFT (0)
+
+//APB2_Rst_Set
+#define SYS_CTRL_AP_SET_APB2_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_APB2_RST_IFC (1<<1)
+#define SYS_CTRL_AP_SET_APB2_RST_UART1 (1<<2)
+#define SYS_CTRL_AP_SET_APB2_RST_UART2 (1<<3)
+#define SYS_CTRL_AP_SET_APB2_RST_UART3 (1<<4)
+#define SYS_CTRL_AP_SET_APB2_RST_SPI1 (1<<5)
+#define SYS_CTRL_AP_SET_APB2_RST_SPI2 (1<<6)
+#define SYS_CTRL_AP_SET_APB2_RST_SPI3 (1<<7)
+#define SYS_CTRL_AP_SET_APB2_RST_SDMMC1 (1<<8)
+#define SYS_CTRL_AP_SET_APB2_RST_SDMMC2 (1<<9)
+#define SYS_CTRL_AP_SET_APB2_RST_SDMMC3 (1<<10)
+#define SYS_CTRL_AP_SET_APB2_RST_NANDFLASH (1<<11)
+#define SYS_CTRL_AP_SET_APB2_RST_I2C1 (1<<12)
+#define SYS_CTRL_AP_SET_APB2_RST_I2C2 (1<<13)
+#define SYS_CTRL_AP_SET_APB2_RST_I2C3 (1<<14)
+#define SYS_CTRL_AP_SET_APB2_RST(n) (((n)&0x7FFF)<<0)
+#define SYS_CTRL_AP_SET_APB2_RST_MASK (0x7FFF<<0)
+#define SYS_CTRL_AP_SET_APB2_RST_SHIFT (0)
+
+//APB2_Rst_Clr
+#define SYS_CTRL_AP_CLR_APB2_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_APB2_RST_IFC (1<<1)
+#define SYS_CTRL_AP_CLR_APB2_RST_UART1 (1<<2)
+#define SYS_CTRL_AP_CLR_APB2_RST_UART2 (1<<3)
+#define SYS_CTRL_AP_CLR_APB2_RST_UART3 (1<<4)
+#define SYS_CTRL_AP_CLR_APB2_RST_SPI1 (1<<5)
+#define SYS_CTRL_AP_CLR_APB2_RST_SPI2 (1<<6)
+#define SYS_CTRL_AP_CLR_APB2_RST_SPI3 (1<<7)
+#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC1 (1<<8)
+#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC2 (1<<9)
+#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC3 (1<<10)
+#define SYS_CTRL_AP_CLR_APB2_RST_NANDFLASH (1<<11)
+#define SYS_CTRL_AP_CLR_APB2_RST_I2C1 (1<<12)
+#define SYS_CTRL_AP_CLR_APB2_RST_I2C2 (1<<13)
+#define SYS_CTRL_AP_CLR_APB2_RST_I2C3 (1<<14)
+#define SYS_CTRL_AP_CLR_APB2_RST(n) (((n)&0x7FFF)<<0)
+#define SYS_CTRL_AP_CLR_APB2_RST_MASK (0x7FFF<<0)
+#define SYS_CTRL_AP_CLR_APB2_RST_SHIFT (0)
+
+//MEM_Rst_Set
+#define SYS_CTRL_AP_SET_MEM_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_MEM_RST_DMC (1<<1)
+#define SYS_CTRL_AP_SET_MEM_RST_DDRPHY_P (1<<2)
+#define SYS_CTRL_AP_SET_MEM_RST(n)  (((n)&0x7)<<0)
+#define SYS_CTRL_AP_SET_MEM_RST_MASK (0x7<<0)
+#define SYS_CTRL_AP_SET_MEM_RST_SHIFT (0)
+
+//MEM_Rst_Clr
+#define SYS_CTRL_AP_CLR_MEM_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_MEM_RST_DMC (1<<1)
+#define SYS_CTRL_AP_CLR_MEM_RST_DDRPHY_P (1<<2)
+#define SYS_CTRL_AP_CLR_MEM_RST(n)  (((n)&0x7)<<0)
+#define SYS_CTRL_AP_CLR_MEM_RST_MASK (0x7<<0)
+#define SYS_CTRL_AP_CLR_MEM_RST_SHIFT (0)
+
+//Clk_CPU_Mode
+#define SYS_CTRL_AP_MODE_CLK_CPU_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_CLK_CPU_MANUAL (1<<0)
+
+//Clk_CPU_Enable
+#define SYS_CTRL_AP_ENABLE_CPU_CORE (1<<0)
+#define SYS_CTRL_AP_ENABLE_CPU_DUMMY (1<<1)
+#define SYS_CTRL_AP_ENABLE_CLK_CPU(n) (((n)&3)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_CPU_MASK (3<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_CPU_SHIFT (0)
+
+//Clk_CPU_Disable
+#define SYS_CTRL_AP_DISABLE_CPU_CORE (1<<0)
+#define SYS_CTRL_AP_DISABLE_CPU_DUMMY (1<<1)
+#define SYS_CTRL_AP_DISABLE_CLK_CPU(n) (((n)&3)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_CPU_MASK (3<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_CPU_SHIFT (0)
+
+//Clk_AXI_Mode
+#define SYS_CTRL_AP_MODE_AHB0_CONF_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_AHB0_CONF_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_APB0_CONF_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_APB0_CONF_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_AXI_VOC_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_AXI_VOC_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_AXI_VOC2_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_AXI_VOC2_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_AXI_DMA_AUTOMATIC (0<<4)
+#define SYS_CTRL_AP_MODE_AXI_DMA_MANUAL (1<<4)
+#define SYS_CTRL_AP_MODE_CLK_AXI(n) (((n)&0x1F)<<0)
+#define SYS_CTRL_AP_MODE_CLK_AXI_MASK (0x1F<<0)
+#define SYS_CTRL_AP_MODE_CLK_AXI_SHIFT (0)
+
+//Clk_AXI_Enable
+#define SYS_CTRL_AP_ENABLE_AHB0_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_APB0_CONF (1<<1)
+#define SYS_CTRL_AP_ENABLE_AXI_VOC  (1<<2)
+#define SYS_CTRL_AP_ENABLE_AXI_VOC2  (1<<3)
+#define SYS_CTRL_AP_ENABLE_AXI_DMA  (1<<4)
+#define SYS_CTRL_AP_ENABLE_AXI_ALWAYS (1<<5)
+#define SYS_CTRL_AP_ENABLE_AXI_CONNECT (1<<6)
+#define SYS_CTRL_AP_ENABLE_AXI_VPU (1<<7)
+#define SYS_CTRL_AP_ENABLE_APB0_IRQ (1<<8)
+#define SYS_CTRL_AP_ENABLE_CLK_AXI(n) (((n)&0x1FF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AXI_MASK (0x1FF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AXI_SHIFT (0)
+
+//Clk_AXI_Disable
+#define SYS_CTRL_AP_DISABLE_AHB0_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_APB0_CONF (1<<1)
+#define SYS_CTRL_AP_DISABLE_AXI_VOC (1<<2)
+#define SYS_CTRL_AP_DISABLE_AXI_VOC2 (1<<3)
+#define SYS_CTRL_AP_DISABLE_AXI_DMA (1<<4)
+#define SYS_CTRL_AP_DISABLE_AXI_ALWAYS (1<<5)
+#define SYS_CTRL_AP_DISABLE_AXI_CONNECT (1<<6)
+#define SYS_CTRL_AP_DISABLE_AXI_VPU (1<<7)
+#define SYS_CTRL_AP_DISABLE_APB0_IRQ (1<<8)
+#define SYS_CTRL_AP_DISABLE_CLK_AXI(n) (((n)&0x1FF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AXI_MASK (0x1FF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AXI_SHIFT (0)
+
+//Clk_AXIDIV2_Mode
+#define SYS_CTRL_AP_MODE_CLK_AXIDIV2_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_CLK_AXIDIV2_MANUAL (1<<0)
+
+//Clk_AXIDIV2_Enable
+#define SYS_CTRL_AP_ENABLE_AXIDIV2_IMEM (1<<0)
+#define SYS_CTRL_AP_ENABLE_AXIDIV2_ALWAYS (1<<1)
+#define SYS_CTRL_AP_ENABLE_AXIDIV2_CONNECT (1<<2)
+#define SYS_CTRL_AP_ENABLE_AXIDIV2_VPU (1<<3)
+#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2(n) (((n)&15)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2_MASK (15<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2_SHIFT (0)
+
+//Clk_AXIDIV2_Disable
+#define SYS_CTRL_AP_DISABLE_AXIDIV2_IMEM (1<<0)
+#define SYS_CTRL_AP_DISABLE_AXIDIV2_ALWAYS (1<<1)
+#define SYS_CTRL_AP_DISABLE_AXIDIV2_CONNECT (1<<2)
+#define SYS_CTRL_AP_DISABLE_AXIDIV2_VPU (1<<3)
+#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2(n) (((n)&15)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2_MASK (15<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2_SHIFT (0)
+
+//Clk_GCG_Mode
+#define SYS_CTRL_AP_MODE_GCG_APB_CONF_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_GCG_APB_CONF_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_GCG_GOUDA_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_GCG_GOUDA_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_GCG_CAMERA_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_GCG_CAMERA_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_GCG_CAMERA2_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_GCG_CAMERA2_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_CLK_GCG(n) (((n)&0xF)<<0)
+#define SYS_CTRL_AP_MODE_CLK_GCG_MASK (0xF<<0)
+#define SYS_CTRL_AP_MODE_CLK_GCG_SHIFT (0)
+
+//Clk_GCG_Enable
+#define SYS_CTRL_AP_ENABLE_GCG_APB_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_GCG_GOUDA (1<<1)
+#define SYS_CTRL_AP_ENABLE_GCG_CAMERA (1<<2)
+#define SYS_CTRL_AP_ENABLE_GCG_CAMERA2 (1<<3)
+#define SYS_CTRL_AP_ENABLE_GCG_ALWAYS (1<<4)
+#define SYS_CTRL_AP_ENABLE_GCG_CONNECT (1<<5)
+#define SYS_CTRL_AP_ENABLE_GCG_GOUDA_AW (1<<6)
+#define SYS_CTRL_AP_ENABLE_GCG_GOUDA_DPI (1<<7)
+#define SYS_CTRL_AP_ENABLE_CLK_GCG(n) (((n)&0xFF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_GCG_MASK (0xFF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_GCG_SHIFT (0)
+
+//Clk_GCG_Disable
+#define SYS_CTRL_AP_DISABLE_GCG_APB_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_GCG_GOUDA (1<<1)
+#define SYS_CTRL_AP_DISABLE_GCG_CAMERA (1<<2)
+#define SYS_CTRL_AP_DISABLE_GCG_CAMERA2 (1<<3)
+#define SYS_CTRL_AP_DISABLE_GCG_ALWAYS (1<<4)
+#define SYS_CTRL_AP_DISABLE_GCG_CONNECT (1<<5)
+#define SYS_CTRL_AP_DISABLE_GCG_GOUDA_AW (1<<6)
+#define SYS_CTRL_AP_DISABLE_GCG_GOUDA_DPI (1<<7)
+#define SYS_CTRL_AP_DISABLE_CLK_GCG(n) (((n)&0xFF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_GCG_MASK (0xFF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_GCG_SHIFT (0)
+
+//Clk_AHB1_Mode
+#define SYS_CTRL_AP_MODE_CLK_AHB1_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_CLK_AHB1_MANUAL (1<<0)
+
+//Clk_AHB1_Enable
+#define SYS_CTRL_AP_ENABLE_AHB1_USBC (1<<0)
+#define SYS_CTRL_AP_ENABLE_AHB1_ALWAYS (1<<1)
+#define SYS_CTRL_AP_ENABLE_AHB1_SPIFLASH (1<<2)
+#define SYS_CTRL_AP_ENABLE_AHB1_EMAC (1<<3)
+#define SYS_CTRL_AP_ENABLE_CLK_AHB1(n) (((n)&0xF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AHB1_MASK (0xF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AHB1_SHIFT (0)
+
+//Clk_AHB1_Disable
+#define SYS_CTRL_AP_DISABLE_AHB1_USBC (1<<0)
+#define SYS_CTRL_AP_DISABLE_AHB1_ALWAYS (1<<1)
+#define SYS_CTRL_AP_DISABLE_AHB1_SPIFLASH (1<<2)
+#define SYS_CTRL_AP_DISABLE_AHB1_EMAC (1<<3)
+#define SYS_CTRL_AP_DISABLE_CLK_AHB1(n) (((n)&0xF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AHB1_MASK (0xF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AHB1_SHIFT (0)
+
+//Clk_APB1_Mode
+#define SYS_CTRL_AP_MODE_APB1_CONF_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_APB1_CONF_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_APB1_AIF_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_APB1_AIF_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_APB1_AIF2_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_APB1_AIF2_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH0_AUTOMATIC (0<<4)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH0_MANUAL (1<<4)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH1_AUTOMATIC (0<<5)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH1_MANUAL (1<<5)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH2_AUTOMATIC (0<<6)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH2_MANUAL (1<<6)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH3_AUTOMATIC (0<<7)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH3_MANUAL (1<<7)
+#define SYS_CTRL_AP_MODE_APB1D_OSC_AUTOMATIC (0<<8)
+#define SYS_CTRL_AP_MODE_APB1D_OSC_MANUAL (1<<8)
+#define SYS_CTRL_AP_MODE_APB1D_OSC2_AUTOMATIC (0<<9)
+#define SYS_CTRL_AP_MODE_APB1D_OSC2_MANUAL (1<<9)
+#define SYS_CTRL_AP_MODE_APB1D_OSC3_AUTOMATIC (0<<10)
+#define SYS_CTRL_AP_MODE_APB1D_OSC3_MANUAL (1<<10)
+#define SYS_CTRL_AP_MODE_APB1D_PWM_AUTOMATIC (0<<11)
+#define SYS_CTRL_AP_MODE_APB1D_PWM_MANUAL (1<<11)
+#define SYS_CTRL_AP_MODE_CLK_APB1(n) (((n)&0xFFF)<<0)
+#define SYS_CTRL_AP_MODE_CLK_APB1_MASK (0xFFF<<0)
+#define SYS_CTRL_AP_MODE_CLK_APB1_SHIFT (0)
+
+//Clk_APB1_Enable
+#define SYS_CTRL_AP_ENABLE_APB1_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_APB1_AIF (1<<1)
+#define SYS_CTRL_AP_ENABLE_APB1_AIF2 (1<<2)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC (1<<3)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH0 (1<<4)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH1 (1<<5)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH2 (1<<6)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH3 (1<<7)
+#define SYS_CTRL_AP_ENABLE_APB1D_OSC (1<<8)
+#define SYS_CTRL_AP_ENABLE_APB1D_OSC2 (1<<9)
+#define SYS_CTRL_AP_ENABLE_APB1D_OSC3 (1<<10)
+#define SYS_CTRL_AP_ENABLE_APB1D_PWM (1<<11)
+#define SYS_CTRL_AP_ENABLE_APB1_ALWAYS (1<<12)
+#define SYS_CTRL_AP_ENABLE_APB1_DAPLITE (1<<13)
+#define SYS_CTRL_AP_ENABLE_APB1_TIMER (1<<14)
+#define SYS_CTRL_AP_ENABLE_APB1_GPIO (1<<15)
+#define SYS_CTRL_AP_ENABLE_CLK_APB1(n) (((n)&0xFFFF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APB1_MASK (0xFFFF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APB1_SHIFT (0)
+
+//Clk_APB1_Disable
+#define SYS_CTRL_AP_DISABLE_APB1_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_APB1_AIF (1<<1)
+#define SYS_CTRL_AP_DISABLE_APB1_AIF2 (1<<2)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC (1<<3)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH0 (1<<4)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH1 (1<<5)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH2 (1<<6)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH3 (1<<7)
+#define SYS_CTRL_AP_DISABLE_APB1D_OSC (1<<8)
+#define SYS_CTRL_AP_DISABLE_APB1D_OSC2 (1<<9)
+#define SYS_CTRL_AP_DISABLE_APB1D_OSC3 (1<<10)
+#define SYS_CTRL_AP_DISABLE_APB1D_PWM (1<<11)
+#define SYS_CTRL_AP_DISABLE_APB1_ALWAYS (1<<12)
+#define SYS_CTRL_AP_DISABLE_APB1_DAPLITE (1<<13)
+#define SYS_CTRL_AP_DISABLE_APB1_TIMER (1<<14)
+#define SYS_CTRL_AP_DISABLE_APB1_GPIO (1<<15)
+#define SYS_CTRL_AP_DISABLE_CLK_APB1(n) (((n)&0xFFFF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APB1_MASK (0xFFFF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APB1_SHIFT (0)
+
+//Clk_APB2_Mode
+#define SYS_CTRL_AP_MODE_APB2_CONF_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_APB2_CONF_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_APB2_IFC_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_APB2_IFC_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH0_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH0_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH1_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH1_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH2_AUTOMATIC (0<<4)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH2_MANUAL (1<<4)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH3_AUTOMATIC (0<<5)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH3_MANUAL (1<<5)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH4_AUTOMATIC (0<<6)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH4_MANUAL (1<<6)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH5_AUTOMATIC (0<<7)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH5_MANUAL (1<<7)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH6_AUTOMATIC (0<<8)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH6_MANUAL (1<<8)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH7_AUTOMATIC (0<<9)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH7_MANUAL (1<<9)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH8_AUTOMATIC (0<<10)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH8_MANUAL (1<<10)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH9_AUTOMATIC (0<<11)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH9_MANUAL (1<<11)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH10_AUTOMATIC (0<<12)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH10_MANUAL (1<<12)
+#define SYS_CTRL_AP_MODE_APB2_UART1_AUTOMATIC (0<<13)
+#define SYS_CTRL_AP_MODE_APB2_UART1_MANUAL (1<<13)
+#define SYS_CTRL_AP_MODE_APB2_UART2_AUTOMATIC (0<<14)
+#define SYS_CTRL_AP_MODE_APB2_UART2_MANUAL (1<<14)
+#define SYS_CTRL_AP_MODE_APB2_UART3_AUTOMATIC (0<<15)
+#define SYS_CTRL_AP_MODE_APB2_UART3_MANUAL (1<<15)
+#define SYS_CTRL_AP_MODE_APB2_SPI1_AUTOMATIC (0<<16)
+#define SYS_CTRL_AP_MODE_APB2_SPI1_MANUAL (1<<16)
+#define SYS_CTRL_AP_MODE_APB2_SPI2_AUTOMATIC (0<<17)
+#define SYS_CTRL_AP_MODE_APB2_SPI2_MANUAL (1<<17)
+#define SYS_CTRL_AP_MODE_APB2_SPI3_AUTOMATIC (0<<18)
+#define SYS_CTRL_AP_MODE_APB2_SPI3_MANUAL (1<<18)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC1_AUTOMATIC (0<<19)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC1_MANUAL (1<<19)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC2_AUTOMATIC (0<<20)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC2_MANUAL (1<<20)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC3_AUTOMATIC (0<<21)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC3_MANUAL (1<<21)
+#define SYS_CTRL_AP_MODE_APB2_I2C1_AUTOMATIC (0<<22)
+#define SYS_CTRL_AP_MODE_APB2_I2C1_MANUAL (1<<22)
+#define SYS_CTRL_AP_MODE_APB2_I2C2_AUTOMATIC (0<<23)
+#define SYS_CTRL_AP_MODE_APB2_I2C2_MANUAL (1<<23)
+#define SYS_CTRL_AP_MODE_APB2_I2C3_AUTOMATIC (0<<24)
+#define SYS_CTRL_AP_MODE_APB2_I2C3_MANUAL (1<<24)
+#define SYS_CTRL_AP_MODE_CLK_APB2(n) (((n)&0x1FFFFFF)<<0)
+#define SYS_CTRL_AP_MODE_CLK_APB2_MASK (0x1FFFFFF<<0)
+#define SYS_CTRL_AP_MODE_CLK_APB2_SHIFT (0)
+
+//Clk_APB2_Enable
+#define SYS_CTRL_AP_ENABLE_APB2_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC (1<<1)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH0 (1<<2)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH1 (1<<3)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH2 (1<<4)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH3 (1<<5)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH4 (1<<6)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH5 (1<<7)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH6 (1<<8)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH7 (1<<9)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH8 (1<<10)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH9 (1<<11)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH10 (1<<12)
+#define SYS_CTRL_AP_ENABLE_APB2_UART1 (1<<13)
+#define SYS_CTRL_AP_ENABLE_APB2_UART2 (1<<14)
+#define SYS_CTRL_AP_ENABLE_APB2_UART3 (1<<15)
+#define SYS_CTRL_AP_ENABLE_APB2_SPI1 (1<<16)
+#define SYS_CTRL_AP_ENABLE_APB2_SPI2 (1<<17)
+#define SYS_CTRL_AP_ENABLE_APB2_SPI3 (1<<18)
+#define SYS_CTRL_AP_ENABLE_APB2_SDMMC1 (1<<19)
+#define SYS_CTRL_AP_ENABLE_APB2_SDMMC2 (1<<20)
+#define SYS_CTRL_AP_ENABLE_APB2_SDMMC3 (1<<21)
+#define SYS_CTRL_AP_ENABLE_APB2_I2C1 (1<<22)
+#define SYS_CTRL_AP_ENABLE_APB2_I2C2 (1<<23)
+#define SYS_CTRL_AP_ENABLE_APB2_I2C3 (1<<24)
+#define SYS_CTRL_AP_ENABLE_APB2_ALWAYS (1<<25)
+#define SYS_CTRL_AP_ENABLE_APB2_NANDFLASH (1<<26)
+#define SYS_CTRL_AP_ENABLE_CLK_APB2(n) (((n)&0x7FFFFFF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APB2_MASK (0x7FFFFFF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APB2_SHIFT (0)
+
+//Clk_APB2_Disable
+#define SYS_CTRL_AP_DISABLE_APB2_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC (1<<1)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH0 (1<<2)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH1 (1<<3)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH2 (1<<4)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH3 (1<<5)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH4 (1<<6)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH5 (1<<7)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH6 (1<<8)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH7 (1<<9)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH8 (1<<10)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH9 (1<<11)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH10 (1<<12)
+#define SYS_CTRL_AP_DISABLE_APB2_UART1 (1<<13)
+#define SYS_CTRL_AP_DISABLE_APB2_UART2 (1<<14)
+#define SYS_CTRL_AP_DISABLE_APB2_UART3 (1<<15)
+#define SYS_CTRL_AP_DISABLE_APB2_SPI1 (1<<16)
+#define SYS_CTRL_AP_DISABLE_APB2_SPI2 (1<<17)
+#define SYS_CTRL_AP_DISABLE_APB2_SPI3 (1<<18)
+#define SYS_CTRL_AP_DISABLE_APB2_SDMMC1 (1<<19)
+#define SYS_CTRL_AP_DISABLE_APB2_SDMMC2 (1<<20)
+#define SYS_CTRL_AP_DISABLE_APB2_SDMMC3 (1<<21)
+#define SYS_CTRL_AP_DISABLE_APB2_I2C1 (1<<22)
+#define SYS_CTRL_AP_DISABLE_APB2_I2C2 (1<<23)
+#define SYS_CTRL_AP_DISABLE_APB2_I2C3 (1<<24)
+#define SYS_CTRL_AP_DISABLE_APB2_ALWAYS (1<<25)
+#define SYS_CTRL_AP_DISABLE_APB2_NANDFLASH (1<<26)
+#define SYS_CTRL_AP_DISABLE_CLK_APB2(n) (((n)&0x7FFFFFF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APB2_MASK (0x7FFFFFF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APB2_SHIFT (0)
+
+//Clk_MEM_Mode
+#define SYS_CTRL_AP_MODE_CLK_MEM_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_CLK_MEM_MANUAL (1<<0)
+
+//Clk_MEM_Enable
+#define SYS_CTRL_AP_ENABLE_MEM_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_MEM_DMC  (1<<1)
+#define SYS_CTRL_AP_ENABLE_MEM_DDRPHY_P (1<<2)
+#define SYS_CTRL_AP_ENABLE_MEM_CONNECT (1<<3)
+#define SYS_CTRL_AP_ENABLE_CLK_MEM(n) (((n)&0xF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_MEM_MASK (0xF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_MEM_SHIFT (0)
+
+//Clk_MEM_Disable
+#define SYS_CTRL_AP_DISABLE_MEM_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_MEM_DMC (1<<1)
+#define SYS_CTRL_AP_DISABLE_MEM_DDRPHY_P (1<<2)
+#define SYS_CTRL_AP_DISABLE_MEM_CONNECT (1<<3)
+#define SYS_CTRL_AP_DISABLE_CLK_MEM(n) (((n)&0xF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_MEM_MASK (0xF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_MEM_SHIFT (0)
+
+//Clk_APO_Mode
+#define SYS_CTRL_AP_MODE_APOC_BCK_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_APOC_BCK_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_APOC_BCK2_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_APOC_BCK2_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_APOC_UART1_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_APOC_UART1_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_APOC_UART2_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_APOC_UART2_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_APOC_UART3_AUTOMATIC (0<<4)
+#define SYS_CTRL_AP_MODE_APOC_UART3_MANUAL (1<<4)
+#define SYS_CTRL_AP_MODE_APOC_VOC_CORE_AUTOMATIC (0<<5)
+#define SYS_CTRL_AP_MODE_APOC_VOC_CORE_MANUAL (1<<5)
+#define SYS_CTRL_AP_MODE_APOC_VOC2_CORE_AUTOMATIC (0<<6)
+#define SYS_CTRL_AP_MODE_APOC_VOC2_CORE_MANUAL (1<<6)
+#define SYS_CTRL_AP_MODE_APOC_VOC_AUTOMATIC (0<<7)
+#define SYS_CTRL_AP_MODE_APOC_VOC_MANUAL (1<<7)
+#define SYS_CTRL_AP_MODE_APOC_VOC2_AUTOMATIC (0<<8)
+#define SYS_CTRL_AP_MODE_APOC_VOC2_MANUAL (1<<8)
+#define SYS_CTRL_AP_MODE_CLK_APO(n) (((n)&01FF)<<0)
+#define SYS_CTRL_AP_MODE_CLK_APO_MASK (0x1FF<<0)
+#define SYS_CTRL_AP_MODE_CLK_APO_SHIFT (0)
+
+//Clk_APO_Enable
+#define SYS_CTRL_AP_ENABLE_APOC_BCK (1<<0)
+#define SYS_CTRL_AP_ENABLE_APOC_BCK2 (1<<1)
+#define SYS_CTRL_AP_ENABLE_APOC_UART1 (1<<2)
+#define SYS_CTRL_AP_ENABLE_APOC_UART2 (1<<3)
+#define SYS_CTRL_AP_ENABLE_APOC_UART3 (1<<4)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC_CORE (1<<5)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC2_CORE (1<<6)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC (1<<7)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC2 (1<<8)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC_ALWAYS (1<<9)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC2_ALWAYS (1<<10)
+#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY_N (1<<11)
+#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY2XP (1<<12)
+#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY2XN (1<<13)
+#define SYS_CTRL_AP_ENABLE_APOC_VPU (1<<14)
+#define SYS_CTRL_AP_ENABLE_APOC_GPU (1<<15)
+#define SYS_CTRL_AP_ENABLE_APOC_USBPHY (1<<16)
+#define SYS_CTRL_AP_ENABLE_APOC_CSI (1<<17)
+#define SYS_CTRL_AP_ENABLE_APOC_CSI2 (1<<18)
+#define SYS_CTRL_AP_ENABLE_APOC_DSI (1<<19)
+#define SYS_CTRL_AP_ENABLE_APOC_GPIO (1<<20)
+#define SYS_CTRL_AP_ENABLE_APOC_SPIFLASH (1<<21)
+#define SYS_CTRL_AP_ENABLE_APOC_PIX (1<<22)
+#define SYS_CTRL_AP_ENABLE_APOC_PIX2 (1<<23)
+#define SYS_CTRL_AP_ENABLE_APOC_PDGB (1<<24)
+#define SYS_CTRL_AP_ENABLE_CLK_APO(n) (((n)&0x1FFFFFF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APO_MASK (0x1FFFFFF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APO_SHIFT (0)
+
+//Clk_APO_Disable
+#define SYS_CTRL_AP_DISABLE_APOC_BCK (1<<0)
+#define SYS_CTRL_AP_DISABLE_APOC_BCK2 (1<<1)
+#define SYS_CTRL_AP_DISABLE_APOC_UART1 (1<<2)
+#define SYS_CTRL_AP_DISABLE_APOC_UART2 (1<<3)
+#define SYS_CTRL_AP_DISABLE_APOC_UART3 (1<<4)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC_CORE (1<<5)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC2_CORE (1<<6)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC (1<<7)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC2 (1<<8)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC_ALWAYS (1<<9)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC2_ALWAYS (1<<10)
+#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY_N (1<<11)
+#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY2XP (1<<12)
+#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY2XN (1<<13)
+#define SYS_CTRL_AP_DISABLE_APOC_VPU (1<<14)
+#define SYS_CTRL_AP_DISABLE_APOC_GPU (1<<15)
+#define SYS_CTRL_AP_DISABLE_APOC_USBPHY (1<<16)
+#define SYS_CTRL_AP_DISABLE_APOC_CSI (1<<17)
+#define SYS_CTRL_AP_DISABLE_APOC_CSI2 (1<<18)
+#define SYS_CTRL_AP_DISABLE_APOC_DSI (1<<19)
+#define SYS_CTRL_AP_DISABLE_APOC_GPIO (1<<20)
+#define SYS_CTRL_AP_DISABLE_APOC_SPIFLASH (1<<21)
+#define SYS_CTRL_AP_DISABLE_APOC_PIX (1<<22)
+#define SYS_CTRL_AP_DISABLE_APOC_PIX2 (1<<23)
+#define SYS_CTRL_AP_DISABLE_APOC_PDGB (1<<24)
+#define SYS_CTRL_AP_DISABLE_CLK_APO(n) (((n)&0x1FFFFFF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APO_MASK (0x1FFFFFF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APO_SHIFT (0)
+
+//Cfg_Clk_AP_CPU
+#define SYS_CTRL_AP_AP_CPU_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_BUS_DIV_SEL(n)  (((n)&3)<<16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_MASK (3<<16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_SHIFT (16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_DIV2 (0<<16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_DIV3 (1<<16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_DIV4 (2<<16)
+#define SYS_CTRL_AP_DBG_CLKDIV_SEL(n)  (((n)&15)<<20)
+#define SYS_CTRL_AP_DBG_CLKDIV_DIV_SEL_MASK (15<<20)
+#define SYS_CTRL_AP_DBG_CLKDIV_SEL_SHIFT (20)
+#define SYS_CTRL_AP_AP_CPU_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_AXI
+#define SYS_CTRL_AP_AP_AXI_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_AXI_SRC_SEL  (1<<12)
+#define SYS_CTRL_AP_AP_AXI_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_GCG
+#define SYS_CTRL_AP_AP_GCG_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_GCG_SRC_SEL  (1<<12)
+#define SYS_CTRL_AP_AP_GCG_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_AHB1
+#define SYS_CTRL_AP_AP_AHB1_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_AHB1_SRC_SEL (1<<12)
+#define SYS_CTRL_AP_AP_AHB1_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_APB1
+#define SYS_CTRL_AP_AP_APB1_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_APB1_SRC_SEL (1<<12)
+#define SYS_CTRL_AP_AP_APB1_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_APB2
+#define SYS_CTRL_AP_AP_APB2_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_APB2_SRC_SEL (1<<12)
+#define SYS_CTRL_AP_AP_APB2_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_MEM
+#define SYS_CTRL_AP_AP_MEM_SRC_DIV2 (1<<12)
+
+//Cfg_Clk_AP_GPU
+#define SYS_CTRL_AP_AP_GPU_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_GPU_SRC_DIV2 (1<<12)
+#define SYS_CTRL_AP_AP_GPU_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_VPU
+#define SYS_CTRL_AP_AP_VPU_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_VPU_SRC_DIV2 (1<<12)
+#define SYS_CTRL_AP_AP_VPU_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_VOC
+#define SYS_CTRL_AP_AP_VOC_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_VOC_SRC_DIV2 (1<<12)
+#define SYS_CTRL_AP_AP_VOC_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_SFLSH
+#define SYS_CTRL_AP_AP_SFLSH_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_SFLSH_SRC_DIV2 (1<<12)
+#define SYS_CTRL_AP_AP_SFLSH_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_Uart
+#define SYS_CTRL_AP_UART_DIVIDER(n) (((n)&0x3FF)<<0)
+#define SYS_CTRL_AP_UART_DIVIDER_MASK (0x3FF<<0)
+#define SYS_CTRL_AP_UART_DIVIDER_SHIFT (0)
+#define SYS_CTRL_AP_UART_SEL_PLL_SLOW (0<<12)
+#define SYS_CTRL_AP_UART_SEL_PLL_PLL (1<<12)
+
+//L2cc_Ctrl
+#define SYS_CTRL_AP_ARQOS_L2CC_1_M(n) (((n)&15)<<0)
+#define SYS_CTRL_AP_ARQOS_L2CC_1_M_MASK (15<<0)
+#define SYS_CTRL_AP_ARQOS_L2CC_1_M_SHIFT (0)
+#define SYS_CTRL_AP_AWQOS_L2CC_1_M(n) (((n)&15)<<4)
+#define SYS_CTRL_AP_AWQOS_L2CC_1_M_MASK (15<<4)
+#define SYS_CTRL_AP_AWQOS_L2CC_1_M_SHIFT (4)
+#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M(n) (((n)&15)<<8)
+#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M_MASK (15<<8)
+#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M_SHIFT (8)
+#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M(n) (((n)&15)<<12)
+#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M_MASK (15<<12)
+#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M_SHIFT (12)
+#define SYS_CTRL_AP_ARAP_L2CC_1_M   (1<<16)
+#define SYS_CTRL_AP_AWAP_L2CC_1_M   (1<<17)
+#define SYS_CTRL_AP_ARAP_MODEM_MEM_AHBS_M (1<<18)
+#define SYS_CTRL_AP_AWAP_MODEM_MEM_AHBS_M (1<<19)
+#define SYS_CTRL_AP_ARAP_MERGE1M    (1<<20)
+#define SYS_CTRL_AP_AWAP_MERGE1M    (1<<21)
+#define SYS_CTRL_AP_ARAP_MERGE2M    (1<<22)
+#define SYS_CTRL_AP_AWAP_MERGE2M    (1<<23)
+#define SYS_CTRL_AP_RESERVE1(n)     (((n)&0xFF)<<24)
+#define SYS_CTRL_AP_RESERVE1_MASK   (0xFF<<24)
+#define SYS_CTRL_AP_RESERVE1_SHIFT  (24)
+
+//Spi_Ctrl
+#define SYS_CTRL_AP_LIMITED_EN_SPI1 (1<<0)
+#define SYS_CTRL_AP_LPSEN_SPI1      (1<<1)
+#define SYS_CTRL_AP_LIMITED_EN_SPI2 (1<<2)
+#define SYS_CTRL_AP_LPSEN_SPI2      (1<<3)
+#define SYS_CTRL_AP_LIMITED_EN_SPI3 (1<<4)
+#define SYS_CTRL_AP_LPSEN_SPI3      (1<<5)
+#define SYS_CTRL_AP_FBUSWID_NFSC    (1<<6)
+#define SYS_CTRL_AP_RESERVE3        (1<<7)
+#define SYS_CTRL_AP_DMC_CFG(n)      (((n)&0x3FF)<<8)
+#define SYS_CTRL_AP_DMC_CFG_MASK    (0x3FF<<8)
+#define SYS_CTRL_AP_DMC_CFG_SHIFT   (8)
+#define SYS_CTRL_AP_RESERVE2(n)     (((n)&0x3FFF)<<18)
+#define SYS_CTRL_AP_RESERVE2_MASK   (0x3FFF<<18)
+#define SYS_CTRL_AP_RESERVE2_SHIFT  (18)
+
+//Memory_Margin
+#define SYS_CTRL_AP_EMAW_VOC(n)     (((n)&3)<<0)
+#define SYS_CTRL_AP_EMAW_VOC_MASK   (3<<0)
+#define SYS_CTRL_AP_EMAW_VOC_SHIFT  (0)
+#define SYS_CTRL_AP_EMA_VOC(n)      (((n)&7)<<2)
+#define SYS_CTRL_AP_EMA_VOC_MASK    (7<<2)
+#define SYS_CTRL_AP_EMA_VOC_SHIFT   (2)
+#define SYS_CTRL_AP_EMAW_VPU(n)     (((n)&3)<<5)
+#define SYS_CTRL_AP_EMAW_VPU_MASK   (3<<5)
+#define SYS_CTRL_AP_EMAW_VPU_SHIFT  (5)
+#define SYS_CTRL_AP_EMA_VPU(n)      (((n)&7)<<7)
+#define SYS_CTRL_AP_EMA_VPU_MASK    (7<<7)
+#define SYS_CTRL_AP_EMA_VPU_SHIFT   (7)
+#define SYS_CTRL_AP_EMAW_GPU(n)     (((n)&3)<<10)
+#define SYS_CTRL_AP_EMAW_GPU_MASK   (3<<10)
+#define SYS_CTRL_AP_EMAW_GPU_SHIFT  (10)
+#define SYS_CTRL_AP_EMA_GPU(n)      (((n)&7)<<12)
+#define SYS_CTRL_AP_EMA_GPU_MASK    (7<<12)
+#define SYS_CTRL_AP_EMA_GPU_SHIFT   (12)
+#define SYS_CTRL_AP_EMAW_GOUDA(n)   (((n)&3)<<15)
+#define SYS_CTRL_AP_EMAW_GOUDA_MASK (3<<15)
+#define SYS_CTRL_AP_EMAW_GOUDA_SHIFT (15)
+#define SYS_CTRL_AP_EMA_GOUDA(n)    (((n)&7)<<17)
+#define SYS_CTRL_AP_EMA_GOUDA_MASK  (7<<17)
+#define SYS_CTRL_AP_EMA_GOUDA_SHIFT (17)
+#define SYS_CTRL_AP_EMAW_IMEM(n)    (((n)&3)<<20)
+#define SYS_CTRL_AP_EMAW_IMEM_MASK  (3<<20)
+#define SYS_CTRL_AP_EMAW_IMEM_SHIFT (20)
+#define SYS_CTRL_AP_EMA_IMEM(n)     (((n)&7)<<22)
+#define SYS_CTRL_AP_EMA_IMEM_MASK   (7<<22)
+#define SYS_CTRL_AP_EMA_IMEM_SHIFT  (22)
+#define SYS_CTRL_AP_EMAW_USB(n)     (((n)&3)<<25)
+#define SYS_CTRL_AP_EMAW_USB_MASK   (3<<25)
+#define SYS_CTRL_AP_EMAW_USB_SHIFT  (25)
+#define SYS_CTRL_AP_EMA_USB(n)      (((n)&7)<<27)
+#define SYS_CTRL_AP_EMA_USB_MASK    (7<<27)
+#define SYS_CTRL_AP_EMA_USB_SHIFT   (27)
+
+//Memory_Margin2
+#define SYS_CTRL_AP_EMAW_NFSC(n)    (((n)&3)<<0)
+#define SYS_CTRL_AP_EMAW_NFSC_MASK  (3<<0)
+#define SYS_CTRL_AP_EMAW_NFSC_SHIFT (0)
+#define SYS_CTRL_AP_EMA_NFSC(n)     (((n)&7)<<2)
+#define SYS_CTRL_AP_EMA_NFSC_MASK   (7<<2)
+#define SYS_CTRL_AP_EMA_NFSC_SHIFT  (2)
+#define SYS_CTRL_AP_EMA_VPUROM(n)   (((n)&7)<<5)
+#define SYS_CTRL_AP_EMA_VPUROM_MASK (7<<5)
+#define SYS_CTRL_AP_EMA_VPUROM_SHIFT (5)
+#define SYS_CTRL_AP_EMA_IMEMROM(n)  (((n)&7)<<8)
+#define SYS_CTRL_AP_EMA_IMEMROM_MASK (7<<8)
+#define SYS_CTRL_AP_EMA_IMEMROM_SHIFT (8)
+#define SYS_CTRL_AP_KEN_VPUROM      (1<<11)
+#define SYS_CTRL_AP_PGEN_VPUROM     (1<<12)
+#define SYS_CTRL_AP_KEN_IMEMROM     (1<<13)
+#define SYS_CTRL_AP_PGEN_IMEMROM    (1<<14)
+
+//Memory_Observe
+#define SYS_CTRL_AP_MEM_OBSERVE(n)  (((n)&0xFFFFFFFF)<<0)
+
+//Cfg_Clk_AP_VOC2
+#define SYS_CTRL_AP_AP_VOC2_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_VOC2_FREQ_MASK (31 << 0)
+#define SYS_CTRL_AP_AP_VOC2_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_VOC2_SRC_DIV2  (1<<12)
+#define SYS_CTRL_AP_AP_VOC2_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_EMMC
+#define SYS_CTRL_AP_EMMC_DATA_STB_DLY(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_EMMC_DATA_STB_DLY_MASK (31 << 0)
+#define SYS_CTRL_AP_EMMC_DATA_STB_DLY_SHIFT 0
+#define SYS_CTRL_AP_EMMC_CLK_DLY(n)  (((n)&31)<<8)
+#define SYS_CTRL_AP_EMMC_CLK_DLY_MASK (31 << 8)
+#define SYS_CTRL_AP_EMMC_CLK_DLY_SHIFT 8
+#define SYS_CTRL_AP_EMMC_CLK_POL  (1<<13)
+
+//Test_Pulse
+#define SYS_CTRL_AP_PULSE_COUNTER(n)  (((n)&0xFFFFFFFF)<<0)
+
+//Cfg_Reserve
+#define SYS_CTRL_AP_RESERVE(n)      (((n)&0xFFFFFFFF)<<0)
+
+#endif
diff --git a/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8820.h b/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8820.h
new file mode 100644
index 0000000000..ab7ba4c951
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8820.h
@@ -0,0 +1,1578 @@
+#ifndef _REG_SYSCTRL_H_
+#define _REG_SYSCTRL_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+
+// ============================================================================
+// AP_CPU_ID_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// CPU IDs
+    CPU0                                        = 0x00000000,
+    CPU1                                        = 0x00000001
+} AP_CPU_ID_T;
+
+
+// ============================================================================
+// CPU_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP CPU side System clocks
+    CPU_CORE                                    = 0x00000000,
+/// the following don't have an auto enable
+    CPU_DUMMY                                   = 0x00000001
+} CPU_CLKS_T;
+
+#define NB_CPU_CLK_AEN                           (1)
+#define NB_CPU_CLK_EN                            (2)
+#define NB_CPU_CLK                               (2)
+
+// ============================================================================
+// AXI_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AXI side System clocks: AXI and AHB0 and APB0
+    AHB0_CONF                                   = 0x00000000,
+    APB0_CONF                                   = 0x00000001,
+    AXI_VOC                                     = 0x00000002,
+    AXI_DMA                                     = 0x00000003,
+/// the following don't have an auto enable
+    AXI_ALWAYS                                  = 0x00000004,
+    AXI_CONNECT                                 = 0x00000005,
+    APB0_IRQ                                    = 0x00000006
+} AXI_CLKS_T;
+
+#define NB_AXI_CLK_AEN                           (4)
+#define NB_AXI_CLK_EN                            (7)
+#define NB_AXI_CLK                               (7)
+
+// ============================================================================
+// AXIDIV2_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AXIdiv2 side System clocks
+    AXIDIV2_IMEM                                = 0x00000000,
+/// the following don't have an auto enable
+    AXIDIV2_ALWAYS                              = 0x00000001,
+    AXIDIV2_CONNECT                             = 0x00000002,
+    AXIDIV2_VPU                                 = 0x00000003
+} AXIDIV2_CLKS_T;
+
+#define NB_AXIDIV2_CLK_AEN                       (1)
+#define NB_AXIDIV2_CLK_EN                        (4)
+#define NB_AXIDIV2_CLK                           (4)
+
+// ============================================================================
+// GCG_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP GCG side System clocks
+    GCG_APB_CONF                                = 0x00000000,
+    GCG_GOUDA                                   = 0x00000001,
+    GCG_CAMERA                                  = 0x00000002,
+/// the following don't have an auto enable
+    GCG_ALWAYS                                  = 0x00000003,
+    GCG_CONNECT                                 = 0x00000004
+} GCG_CLKS_T;
+
+#define NB_GCG_CLK_AEN                           (3)
+#define NB_GCG_CLK_EN                            (5)
+#define NB_GCG_CLK                               (5)
+
+// ============================================================================
+// AHB1_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AHB1 side System clocks
+    AHB1_USBC                                   = 0x00000000,
+/// the following don't have an auto enable
+    AHB1_ALWAYS                                 = 0x00000001,
+    AHB1_SPIFLASH                               = 0x00000002
+} AHB1_CLKS_T;
+
+#define NB_AHB1_CLK_AEN                          (1)
+#define NB_AHB1_CLK_EN                           (3)
+#define NB_AHB1_CLK                              (3)
+
+// ============================================================================
+// APB1_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP APB1 side System clocks
+    APB1_CONF                                   = 0x00000000,
+    APB1_AIF                                    = 0x00000001,
+    APB1_AUIFC                                  = 0x00000002,
+    APB1_AUIFC_CH0                              = 0x00000003,
+    APB1_AUIFC_CH1                              = 0x00000004,
+    APB1_I2C1                                   = 0x00000005,
+    APB1_I2C2                                   = 0x00000006,
+    APB1_I2C3                                   = 0x00000007,
+/// AP APB1 side divided clock (either divided by module or by clock_ctrl)
+    APB1D_OSC                                   = 0x00000008,
+    APB1D_PWM                                   = 0x00000009,
+/// the following don't have an auto enable
+    APB1_ALWAYS                                 = 0x0000000A,
+    APB1_DAPLITE                                = 0x0000000B,
+    APB1_TIMER                                  = 0x0000000C,
+    APB1_GPIO                                   = 0x0000000D
+} APB1_CLKS_T;
+
+#define NB_APB1_CLK_AEN                          (10)
+#define NB_APB1_CLK_EN                           (14)
+#define NB_APB1_CLK                              (14)
+
+// ============================================================================
+// APB2_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP APB2 side System clocks
+    APB2_CONF                                   = 0x00000000,
+    APB2_IFC                                    = 0x00000001,
+    APB2_IFC_CH0                                = 0x00000002,
+    APB2_IFC_CH1                                = 0x00000003,
+    APB2_IFC_CH2                                = 0x00000004,
+    APB2_IFC_CH3                                = 0x00000005,
+    APB2_IFC_CH4                                = 0x00000006,
+    APB2_IFC_CH5                                = 0x00000007,
+    APB2_IFC_CH6                                = 0x00000008,
+    APB2_IFC_CH7                                = 0x00000009,
+    APB2_UART1                                  = 0x0000000A,
+    APB2_UART2                                  = 0x0000000B,
+    APB2_UART3                                  = 0x0000000C,
+    APB2_SPI1                                   = 0x0000000D,
+    APB2_SPI2                                   = 0x0000000E,
+    APB2_SPI3                                   = 0x0000000F,
+    APB2_SDMMC1                                 = 0x00000010,
+    APB2_SDMMC2                                 = 0x00000011,
+    APB2_SDMMC3                                 = 0x00000012,
+/// the following don't have an auto enable
+    APB2_ALWAYS                                 = 0x00000013,
+    APB2_NANDFLASH                              = 0x00000014
+} APB2_CLKS_T;
+
+#define NB_APB2_CLK_AEN                          (19)
+#define NB_APB2_CLK_EN                           (21)
+#define NB_APB2_CLK                              (21)
+
+// ============================================================================
+// MEM_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP MEM side System clocks
+    MEM_CONF                                    = 0x00000000,
+/// the following don't have an auto enable
+    MEM_DMC                                     = 0x00000001,
+    MEM_GPU                                     = 0x00000002,
+    MEM_VPU                                     = 0x00000003,
+    MEM_DDRPHY_P                                = 0x00000004,
+    MEM_CONNECT                                 = 0x00000005
+} MEM_CLKS_T;
+
+#define NB_MEM_CLK_AEN                           (1)
+#define NB_MEM_CLK_EN                            (6)
+#define NB_MEM_CLK                               (6)
+
+// ============================================================================
+// APO_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP side Other clocks
+/// clocks with auto enble
+    APOC_VPU                                    = 0x00000000,
+    APOC_BCK                                    = 0x00000001,
+    APOC_UART1                                  = 0x00000002,
+    APOC_UART2                                  = 0x00000003,
+    APOC_UART3                                  = 0x00000004,
+    APOC_VOC_CORE                               = 0x00000005,
+    APOC_VOC                                    = 0x00000006,
+/// the following don't have an auto enable
+    APOC_VOC_ALWAYS                             = 0x00000007,
+    APOC_DDRPHY_N                               = 0x00000008,
+    APOC_DDRPHY2XP                              = 0x00000009,
+    APOC_DDRPHY2XN                              = 0x0000000A,
+    APOC_GPU                                    = 0x0000000B,
+    APOC_USBPHY                                 = 0x0000000C,
+    APOC_CSI                                    = 0x0000000D,
+    APOC_DSI                                    = 0x0000000E,
+    APOC_GPIO                                   = 0x0000000F,
+    APOC_SPIFLASH                               = 0x00000010,
+    APOC_PIX                                    = 0x00000011,
+    APOC_PDGB                                   = 0x00000012
+} APO_CLKS_T;
+
+#define NB_CLK_VOC_AEN_SYNC                      (5)
+#define NB_CLK_VOC_CORE                          (6)
+#define NB_APO_CLK_AEN                           (7)
+#define NB_CLK_VOC_END                           (8)
+#define NB_APO_CLK_EN                            (19)
+#define NB_APO_CLK                               (19)
+
+// ============================================================================
+// CPU_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP CPU side resets
+    CPU_RST_CORE                                = 0x00000000,
+    CPU_RST_SYS                                 = 0x00000001
+} CPU_RESETS_T;
+
+#define NB_CPU_RST                               (2)
+
+// ============================================================================
+// AXI_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AXI side resets: AXI and AHB0 and APB0
+    AXI_RST_VOC                                 = 0x00000000,
+    AXI_RST_DMA                                 = 0x00000001,
+    AXI_RST_SYS                                 = 0x00000002,
+    AXI_RST_CONNECT                             = 0x00000003,
+    AHB0_RST_GPU                                = 0x00000004,
+    APB0_RST_VPU                                = 0x00000005,
+    APB0_RST_IRQ                                = 0x00000006
+} AXI_RESETS_T;
+
+#define NB_AXI_RST                               (7)
+
+// ============================================================================
+// AXIDIV2_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AXIDIV2 side resets
+    AXIDIV2_RST_IMEM                            = 0x00000000,
+    AXIDIV2_RST_SYS                             = 0x00000001,
+    AXIDIV2_RST_VPU                             = 0x00000002
+} AXIDIV2_RESETS_T;
+
+#define NB_AXIDIV2_RST                           (3)
+
+// ============================================================================
+// GCG_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP GCG side resets
+    GCG_RST_SYS                                 = 0x00000000,
+    GCG_RST_GOUDA                               = 0x00000001,
+    GCG_RST_CAMERA                              = 0x00000002
+} GCG_RESETS_T;
+
+#define NB_GCG_RST                               (3)
+
+// ============================================================================
+// AHB1_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AHB1 side resets
+    AHB1_RST_SYS                                = 0x00000000,
+    AHB1_RST_USBC                               = 0x00000001,
+    AHB1_RST_SPIFLASH                           = 0x00000002
+} AHB1_RESETS_T;
+
+#define NB_AHB1_RST                              (3)
+
+// ============================================================================
+// APB1_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP APB1 side resets
+    APB1_RST_SYS                                = 0x00000000,
+    APB1_RST_TIMER                              = 0x00000001,
+    APB1_RST_KEYPAD                             = 0x00000002,
+    APB1_RST_GPIO                               = 0x00000003,
+    APB1_RST_PWM                                = 0x00000004,
+    APB1_RST_AIF                                = 0x00000005,
+    APB1_RST_AUIFC                              = 0x00000006,
+    APB1_RST_I2C1                               = 0x00000007,
+    APB1_RST_I2C2                               = 0x00000008,
+    APB1_RST_I2C3                               = 0x00000009,
+    APB1_RST_COM_REGS                           = 0x0000000A,
+    APB1_RST_DMC                                = 0x0000000B,
+    APB1_RST_DDRPHY_P                           = 0x0000000C,
+    APB1_RST_BB2G_XCPU                          = 0x0000000D,
+    APB1_RST_BB2G_BCPU                          = 0x0000000E,
+    APB1_RST_BB2G_AHBC                          = 0x0000000F,
+    APB1_RST_BB2G_DMA                           = 0x00000010,
+    APB1_RST_BB2G_A2A                           = 0x00000011,
+    APB1_RST_BB2G_XIFC                          = 0x00000012,
+    APB1_RST_BB2G_BIFC                          = 0x00000013,
+    APB1_RST_BB2G_BAHBC                         = 0x00000014,
+    APB1_RST_BB2G_MEM_BRIDGE                    = 0x00000015
+} APB1_RESETS_T;
+
+#define NB_APB1_RST                              (22)
+
+// ============================================================================
+// APB2_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP APB2 side resets
+    APB2_RST_SYS                                = 0x00000000,
+    APB2_RST_IFC                                = 0x00000001,
+    APB2_RST_UART1                              = 0x00000002,
+    APB2_RST_UART2                              = 0x00000003,
+    APB2_RST_UART3                              = 0x00000004,
+    APB2_RST_SPI1                               = 0x00000005,
+    APB2_RST_SPI2                               = 0x00000006,
+    APB2_RST_SPI3                               = 0x00000007,
+    APB2_RST_SDMMC1                             = 0x00000008,
+    APB2_RST_SDMMC2                             = 0x00000009,
+    APB2_RST_SDMMC3                             = 0x0000000A,
+    APB2_RST_NANDFLASH                          = 0x0000000B
+} APB2_RESETS_T;
+
+#define NB_APB2_RST                              (12)
+
+// ============================================================================
+// MEM_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP MEM side resets
+    MEM_RST_SYS                                 = 0x00000000,
+    MEM_RST_GPU                                 = 0x00000001,
+    MEM_RST_VPU                                 = 0x00000002,
+    MEM_RST_DMC                                 = 0x00000003,
+    MEM_RST_DDRPHY_P                            = 0x00000004
+} MEM_RESETS_T;
+
+#define NB_MEM_RST                               (5)
+
+// ============================================================================
+// AP_OTHERS_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP Reset Other : resync on corresponding clock other
+    AP_RSTO_VOC                                 = 0x00000000,
+    AP_RSTO_DDRPHY_N                            = 0x00000001,
+    AP_RSTO_DDRPHY2XP                           = 0x00000002,
+    AP_RSTO_DDRPHY2XN                           = 0x00000003,
+    AP_RSTO_GPU                                 = 0x00000004,
+    AP_RSTO_VPU                                 = 0x00000005,
+    AP_RSTO_BCK                                 = 0x00000006,
+    AP_RSTO_UART1                               = 0x00000007,
+    AP_RSTO_UART2                               = 0x00000008,
+    AP_RSTO_UART3                               = 0x00000009,
+    AP_RSTO_GPIO                                = 0x0000000A,
+    AP_RSTO_TIMER                               = 0x0000000B,
+    AP_RSTO_USBC                                = 0x0000000C,
+    AP_RSTO_DSI                                 = 0x0000000D,
+    AP_RSTO_SPIFLASH                            = 0x0000000E,
+    AP_RSTO_TCK                                 = 0x0000000F,
+    AP_RSTO_PDBG_XTAL                           = 0x00000010
+} AP_OTHERS_RESETS_T;
+
+#define NB_AP_RSTO                               (17)
+/// For REG_DBG protect lock/unlock value
+#define AP_CTRL_PROTECT_LOCK                     (0XA50000)
+#define AP_CTRL_PROTECT_UNLOCK                   (0XA50001)
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+// ============================================================================
+// SYS_CTRL_AP_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef volatile struct
+{
+    /// <strong>This register is used to Lock and Unlock the protected registers.</strong>
+    REG32                          REG_DBG;                      //0x00000000
+    /// Register protected by Write_Unlocked_H.
+    REG32                          Cfg_Pll_Ctrl[4];              //0x00000004
+    /// This register is protected.
+    REG32                          Sel_Clock;                    //0x00000014
+    REG32                          Reset_Cause;                  //0x00000018
+    /// This register is protected.
+    REG32                          CPU_Rst_Set;                  //0x0000001C
+    REG32                          CPU_Rst_Clr;                  //0x00000020
+    /// This register is protected.
+    REG32                          AXI_Rst_Set;                  //0x00000024
+    REG32                          AXI_Rst_Clr;                  //0x00000028
+    /// This register is protected.
+    REG32                          AXIDIV2_Rst_Set;              //0x0000002C
+    REG32                          AXIDIV2_Rst_Clr;              //0x00000030
+    /// This register is protected.
+    REG32                          GCG_Rst_Set;                  //0x00000034
+    REG32                          GCG_Rst_Clr;                  //0x00000038
+    /// This register is protected.
+    REG32                          AHB1_Rst_Set;                 //0x0000003C
+    REG32                          AHB1_Rst_Clr;                 //0x00000040
+    /// This register is protected.
+    REG32                          APB1_Rst_Set;                 //0x00000044
+    REG32                          APB1_Rst_Clr;                 //0x00000048
+    /// This register is protected.
+    REG32                          APB2_Rst_Set;                 //0x0000004C
+    REG32                          APB2_Rst_Clr;                 //0x00000050
+    /// This register is protected.
+    REG32                          MEM_Rst_Set;                  //0x00000054
+    REG32                          MEM_Rst_Clr;                  //0x00000058
+    REG32                          Clk_CPU_Mode;                 //0x0000005C
+    REG32                          Clk_CPU_Enable;               //0x00000060
+    /// This register is protected.
+    REG32                          Clk_CPU_Disable;              //0x00000064
+    REG32                          Clk_AXI_Mode;                 //0x00000068
+    REG32                          Clk_AXI_Enable;               //0x0000006C
+    /// This register is protected.
+    REG32                          Clk_AXI_Disable;              //0x00000070
+    REG32                          Clk_AXIDIV2_Mode;             //0x00000074
+    REG32                          Clk_AXIDIV2_Enable;           //0x00000078
+    /// This register is protected.
+    REG32                          Clk_AXIDIV2_Disable;          //0x0000007C
+    REG32                          Clk_GCG_Mode;                 //0x00000080
+    REG32                          Clk_GCG_Enable;               //0x00000084
+    /// This register is protected.
+    REG32                          Clk_GCG_Disable;              //0x00000088
+    REG32                          Clk_AHB1_Mode;                //0x0000008C
+    REG32                          Clk_AHB1_Enable;              //0x00000090
+    /// This register is protected.
+    REG32                          Clk_AHB1_Disable;             //0x00000094
+    REG32                          Clk_APB1_Mode;                //0x00000098
+    REG32                          Clk_APB1_Enable;              //0x0000009C
+    /// This register is protected.
+    REG32                          Clk_APB1_Disable;             //0x000000A0
+    REG32                          Clk_APB2_Mode;                //0x000000A4
+    REG32                          Clk_APB2_Enable;              //0x000000A8
+    /// This register is protected.
+    REG32                          Clk_APB2_Disable;             //0x000000AC
+    REG32                          Clk_MEM_Mode;                 //0x000000B0
+    REG32                          Clk_MEM_Enable;               //0x000000B4
+    /// This register is protected.
+    REG32                          Clk_MEM_Disable;              //0x000000B8
+    REG32                          Clk_APO_Mode;                 //0x000000BC
+    REG32                          Clk_APO_Enable;               //0x000000C0
+    /// This register is protected.
+    REG32                          Clk_APO_Disable;              //0x000000C4
+    REG32                          Cfg_Clk_AP_CPU;               //0x000000C8
+    REG32                          Cfg_Clk_AP_AXI;               //0x000000CC
+    REG32                          Cfg_Clk_AP_GCG;               //0x000000D0
+    REG32                          Cfg_Clk_AP_AHB1;              //0x000000D4
+    REG32                          Cfg_Clk_AP_APB1;              //0x000000D8
+    REG32                          Cfg_Clk_AP_APB2;              //0x000000DC
+    REG32                          Cfg_Clk_AP_MEM;               //0x000000E0
+    REG32                          Cfg_Clk_AP_GPU;               //0x000000E4
+    REG32                          Cfg_Clk_AP_VPU;               //0x000000E8
+    REG32                          Cfg_Clk_AP_VOC;               //0x000000EC
+    REG32                          Cfg_Clk_AP_SFLSH;             //0x000000F0
+    REG32                          Cfg_Clk_Uart[3];              //0x000000F4
+    REG32                          L2cc_Ctrl;                    //0x00000100
+    REG32                          Spi_Ctrl;                     //0x00000104
+    REG32                          Memory_Margin;                //0x00000108
+    REG32                          Memory_Margin2;               //0x0000010C
+    REG32                          Memory_Observe;               //0x00000110
+    REG32                          Cfg_Clk_AP_VOC2;               //0x00000114
+    REG32                          Cfg_Clk_EMMC;               //0x00000118
+    REG32                          Test_Pulse;               //0x0000011C
+    REG32 Reserved_00000114[49];                //0x00000120
+    /// This register is reserved.
+    REG32                          Cfg_Cpu_Reserve0;                  //0x000001E4
+    REG32                          Cfg_Cpu_Reserve1;                  //0x000001E8
+    REG32                          Cfg_Cpu_Reserve2;                  //0x000001EC
+    REG32                          Cfg_Cpu_Reserve3;                  //0x000001F0
+    REG32                          Cfg_Cpu_Reserve4;                  //0x000001F4
+    REG32                          Cfg_Cpu_Reserve5;                  //0x000001F8
+    REG32                          Cfg_Reserve;                  //0x000001FC
+} HWP_SYS_CTRL_AP_T;
+
+#define hwp_sysCtrlAp               ((HWP_SYS_CTRL_AP_T*)(RDA_SYSCTRL_BASE))
+
+
+//REG_DBG
+#define SYS_CTRL_AP_SCRATCH(n)      (((n)&0xFFFF)<<0)
+#define SYS_CTRL_AP_WRITE_UNLOCK_STATUS (1<<30)
+#define SYS_CTRL_AP_WRITE_UNLOCK    (1<<31)
+
+//Cfg_Pll_Ctrl
+#define SYS_CTRL_AP_AP_PLL_ENABLE   (1<<0)
+#define SYS_CTRL_AP_AP_PLL_ENABLE_MASK (1<<0)
+#define SYS_CTRL_AP_AP_PLL_ENABLE_SHIFT (0)
+#define SYS_CTRL_AP_AP_PLL_ENABLE_POWER_DOWN (0<<0)
+#define SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE (1<<0)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET (1<<4)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_MASK (1<<4)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_SHIFT (4)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_RESET (0<<4)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET (1<<4)
+#define SYS_CTRL_AP_AP_PLL_BYPASS   (1<<8)
+#define SYS_CTRL_AP_AP_PLL_BYPASS_MASK (1<<8)
+#define SYS_CTRL_AP_AP_PLL_BYPASS_SHIFT (8)
+#define SYS_CTRL_AP_AP_PLL_BYPASS_PASS (0<<8)
+#define SYS_CTRL_AP_AP_PLL_BYPASS_BYPASS (1<<8)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE (1<<12)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_MASK (1<<12)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_SHIFT (12)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_ENABLE (1<<12)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_DISABLE (0<<12)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(n) (((n)&31)<<16)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW_MASK (31<<16)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW_SHIFT (16)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(n) (((n)&31)<<24)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH_MASK (31<<24)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH_SHIFT (24)
+#define SYS_CTRL_AP_PLL_AP_CFG(n)   (((n)&0x1F1F1111)<<0)
+#define SYS_CTRL_AP_PLL_AP_CFG_MASK (0x1F1F1111<<0)
+#define SYS_CTRL_AP_PLL_AP_CFG_SHIFT (0)
+
+//Sel_Clock
+#define SYS_CTRL_AP_SLOW_SEL_RF_OSCILLATOR (1<<0)
+#define SYS_CTRL_AP_SLOW_SEL_RF_RF  (0<<0)
+#define SYS_CTRL_AP_TIMER_SEL_FAST_SLOW (1<<1)
+#define SYS_CTRL_AP_TIMER_SEL_FAST_FAST (0<<1)
+#define SYS_CTRL_AP_TIMER2_SEL_FAST_SLOW (1<<2)
+#define SYS_CTRL_AP_TIMER2_SEL_FAST_FAST (0<<2)
+#define SYS_CTRL_AP_TIMER3_SEL_FAST_SLOW (1<<3)
+#define SYS_CTRL_AP_TIMER3_SEL_FAST_FAST (0<<3)
+#define SYS_CTRL_AP_CPU_SEL_FAST_SLOW (1<<4)
+#define SYS_CTRL_AP_CPU_SEL_FAST_FAST (0<<4)
+#define SYS_CTRL_AP_BUS_SEL_FAST_SLOW (1<<5)
+#define SYS_CTRL_AP_BUS_SEL_FAST_FAST (0<<5)
+#define SYS_CTRL_AP_RF_DETECTED_OK  (1<<8)
+#define SYS_CTRL_AP_RF_DETECTED_NO  (0<<8)
+#define SYS_CTRL_AP_RF_DETECT_BYPASS (1<<9)
+#define SYS_CTRL_AP_RF_DETECT_RESET (1<<10)
+#define SYS_CTRL_AP_RF_SELECTED_L   (1<<11)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU  (1<<12)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU_MASK (1<<12)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU_SHIFT (12)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU_LOCKED (1<<12)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU_NOT_LOCKED (0<<12)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS  (1<<13)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS_MASK (1<<13)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS_SHIFT (13)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS_LOCKED (1<<13)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS_NOT_LOCKED (0<<13)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM  (1<<14)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM_MASK (1<<14)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM_SHIFT (14)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM_LOCKED (1<<14)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM_NOT_LOCKED (0<<14)
+#define SYS_CTRL_AP_PLL_LOCKED_USB  (1<<15)
+#define SYS_CTRL_AP_PLL_LOCKED_USB_MASK (1<<15)
+#define SYS_CTRL_AP_PLL_LOCKED_USB_SHIFT (15)
+#define SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED (1<<15)
+#define SYS_CTRL_AP_PLL_LOCKED_USB_NOT_LOCKED (0<<15)
+#define SYS_CTRL_AP_PLL_BYPASS_LOCK_CPU (1<<20)
+#define SYS_CTRL_AP_PLL_BYPASS_LOCK_BUS (1<<21)
+#define SYS_CTRL_AP_FAST_SELECTED_CPU_L (1<<30)
+#define SYS_CTRL_AP_FAST_SELECTED_CPU_L_MASK (1<<30)
+#define SYS_CTRL_AP_FAST_SELECTED_CPU_L_SHIFT (30)
+#define SYS_CTRL_AP_FAST_SELECTED_BUS_L (1<<31)
+#define SYS_CTRL_AP_FAST_SELECTED_BUS_L_MASK (1<<31)
+#define SYS_CTRL_AP_FAST_SELECTED_BUS_L_SHIFT (31)
+
+//Reset_Cause
+#define SYS_CTRL_AP_WATCHDOG_RESET_HAPPENED (1<<0)
+#define SYS_CTRL_AP_WATCHDOG_RESET_NO (0<<0)
+#define SYS_CTRL_AP_GLOBALSOFT_RESET_HAPPENED (1<<4)
+#define SYS_CTRL_AP_GLOBALSOFT_RESET_NO (0<<4)
+#define SYS_CTRL_AP_HOSTDEBUG_RESET_HAPPENED (1<<5)
+#define SYS_CTRL_AP_HOSTDEBUG_RESET_NO (0<<5)
+#define SYS_CTRL_AP_ALARMCAUSE_HAPPENED (1<<6)
+#define SYS_CTRL_AP_ALARMCAUSE_NO   (0<<6)
+#define SYS_CTRL_AP_BOOT_MODE(n)    (((n)&0xFFFF)<<8)
+#define SYS_CTRL_AP_BOOT_MODE_MASK  (0xFFFF<<8)
+#define SYS_CTRL_AP_BOOT_MODE_SHIFT (8)
+#define SYS_CTRL_AP_SW_BOOT_MODE(n) (((n)&0x7F)<<24)
+#define SYS_CTRL_AP_SW_BOOT_MODE_MASK (0x7F<<24)
+#define SYS_CTRL_AP_SW_BOOT_MODE_SHIFT (24)
+#define SYS_CTRL_AP_FONCTIONAL_TEST_MODE (1<<31)
+
+//CPU_Rst_Set
+#define SYS_CTRL_AP_SET_CPU_RST_CORE (1<<0)
+#define SYS_CTRL_AP_SET_CPU_RST_CORE1 (1<<1)
+#define SYS_CTRL_AP_SET_CPU_RST_CORE2 (1<<2)
+#define SYS_CTRL_AP_SET_CPU_RST_CORE3 (1<<3)
+#define SYS_CTRL_AP_SET_CPU_RST_L2 (1<<4)
+#define SYS_CTRL_AP_SET_CPU_RST_SYS (1<<5)
+#define SYS_CTRL_AP_SOFT_RST        (1<<31)
+#define SYS_CTRL_AP_SET_CPU_RST(n)  (((n)&0xF)<<0)
+#define SYS_CTRL_AP_SET_CPU_RST_MASK (0xF<<0)
+#define SYS_CTRL_AP_SET_CPU_RST_SHIFT (0)
+
+//CPU_Rst_Clr
+#define SYS_CTRL_AP_CLR_CPU_RST_CORE (1<<0)
+#define SYS_CTRL_AP_CLR_CPU_RST_CORE1 (1<<1)
+#define SYS_CTRL_AP_CLR_CPU_RST_CORE2 (1<<2)
+#define SYS_CTRL_AP_CLR_CPU_RST_CORE3 (1<<3)
+#define SYS_CTRL_AP_CLR_CPU_RST_L2 (1<<4)
+#define SYS_CTRL_AP_CLR_CPU_RST_SYS (1<<5)
+#define SYS_CTRL_AP_CLR_CPU_RST(n)  (((n)&0xF)<<0)
+#define SYS_CTRL_AP_CLR_CPU_RST_MASK (0xF<<0)
+#define SYS_CTRL_AP_CLR_CPU_RST_SHIFT (0)
+
+//AXI_Rst_Set
+#define SYS_CTRL_AP_SET_AXI_RST_VOC (1<<0)
+#define SYS_CTRL_AP_SET_AXI_RST_VOC2 (1<<1)
+#define SYS_CTRL_AP_SET_AXI_RST_DMA (1<<2)
+#define SYS_CTRL_AP_SET_AXI_RST_SYS (1<<3)
+#define SYS_CTRL_AP_SET_AXI_RST_CONNECT (1<<4)
+#define SYS_CTRL_AP_SET_APB0_RST_GPU (1<<5)
+#define SYS_CTRL_AP_SET_APB0_RST_VPU (1<<6)
+#define SYS_CTRL_AP_SET_APB0_RST_IRQ (1<<7)
+#define SYS_CTRL_AP_SET_AXI_RST(n)  (((n)&0xFF)<<0)
+#define SYS_CTRL_AP_SET_AXI_RST_MASK (0xFF<<0)
+#define SYS_CTRL_AP_SET_AXI_RST_SHIFT (0)
+
+//AXI_Rst_Clr
+#define SYS_CTRL_AP_CLR_AXI_RST_VOC (1<<0)
+#define SYS_CTRL_AP_CLR_AXI_RST_VOC2 (1<<1)
+#define SYS_CTRL_AP_CLR_AXI_RST_DMA (1<<2)
+#define SYS_CTRL_AP_CLR_AXI_RST_SYS (1<<3)
+#define SYS_CTRL_AP_CLR_AXI_RST_CONNECT (1<<4)
+#define SYS_CTRL_AP_CLR_APB0_RST_GPU (1<<5)
+#define SYS_CTRL_AP_CLR_APB0_RST_VPU (1<<6)
+#define SYS_CTRL_AP_CLR_APB0_RST_IRQ (1<<7)
+#define SYS_CTRL_AP_CLR_AXI_RST(n)  (((n)&0xFF)<<0)
+#define SYS_CTRL_AP_CLR_AXI_RST_MASK (0xFF<<0)
+#define SYS_CTRL_AP_CLR_AXI_RST_SHIFT (0)
+
+//AXIDIV2_Rst_Set
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_IMEM (1<<0)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_SYS (1<<1)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_VPU (1<<2)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_MASK (7<<0)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_SHIFT (0)
+
+//AXIDIV2_Rst_Clr
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_IMEM (1<<0)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_SYS (1<<1)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_VPU (1<<2)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_MASK (7<<0)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_SHIFT (0)
+
+//GCG_Rst_Set
+#define SYS_CTRL_AP_SET_GCG_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_GCG_RST_GOUDA (1<<1)
+#define SYS_CTRL_AP_SET_GCG_RST_CAMERA (1<<2)
+#define SYS_CTRL_AP_SET_GCG_RST_CAMERA2 (1<<3)
+#define SYS_CTRL_AP_SET_GCG_RST(n)  (((n)&0xF)<<0)
+#define SYS_CTRL_AP_SET_GCG_RST_MASK (0xF<<0)
+#define SYS_CTRL_AP_SET_GCG_RST_SHIFT (0)
+
+//GCG_Rst_Clr
+#define SYS_CTRL_AP_CLR_GCG_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_GCG_RST_GOUDA (1<<1)
+#define SYS_CTRL_AP_CLR_GCG_RST_CAMERA (1<<2)
+#define SYS_CTRL_AP_CLR_GCG_RST_CAMERA2 (1<<3)
+#define SYS_CTRL_AP_CLR_GCG_RST(n)  (((n)&0xF)<<0)
+#define SYS_CTRL_AP_CLR_GCG_RST_MASK (0xF<<0)
+#define SYS_CTRL_AP_CLR_GCG_RST_SHIFT (0)
+
+//AHB1_Rst_Set
+#define SYS_CTRL_AP_SET_AHB1_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_AHB1_RST_USBC (1<<1)
+#define SYS_CTRL_AP_SET_AHB1_RST_SPIFLASH (1<<2)
+#define SYS_CTRL_AP_SET_AHB1_RST_EMAC (1<<3)
+#define SYS_CTRL_AP_SET_AHB1_RST(n) (((n)&0xF)<<0)
+#define SYS_CTRL_AP_SET_AHB1_RST_MASK (0xF<<0)
+#define SYS_CTRL_AP_SET_AHB1_RST_SHIFT (0)
+
+//AHB1_Rst_Clr
+#define SYS_CTRL_AP_CLR_AHB1_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_AHB1_RST_USBC (1<<1)
+#define SYS_CTRL_AP_CLR_AHB1_RST_SPIFLASH (1<<2)
+#define SYS_CTRL_AP_CLR_AHB1_RST_EMAC (1<<3)
+#define SYS_CTRL_AP_CLR_AHB1_RST(n) (((n)&0xF)<<0)
+#define SYS_CTRL_AP_CLR_AHB1_RST_MASK (0xF<<0)
+#define SYS_CTRL_AP_CLR_AHB1_RST_SHIFT (0)
+
+//APB1_Rst_Set
+#define SYS_CTRL_AP_SET_APB1_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_APB1_RST_TIMER (1<<1)
+#define SYS_CTRL_AP_SET_APB1_RST_KEYPAD (1<<2)
+#define SYS_CTRL_AP_SET_APB1_RST_GPIO (1<<3)
+#define SYS_CTRL_AP_SET_APB1_RST_PWM (1<<4)
+#define SYS_CTRL_AP_SET_APB1_RST_AIF (1<<5)
+#define SYS_CTRL_AP_SET_APB1_RST_AIF2 (1<<6)
+#define SYS_CTRL_AP_SET_APB1_RST_AUIFC (1<<7)
+#define SYS_CTRL_AP_SET_APB1_RST_COM_REGS (1<<8)
+#define SYS_CTRL_AP_SET_APB1_RST_DMC (1<<9)
+#define SYS_CTRL_AP_SET_APB1_RST_DDRPHY_P (1<<10)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_XCPU (1<<11)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BCPU (1<<12)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_AHBC (1<<13)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_DMA (1<<14)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_A2A (1<<15)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_XIFC (1<<16)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BIFC (1<<17)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BAHBC (1<<18)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_MEM_BRIDGE (1<<19)
+#define SYS_CTRL_AP_SET_APB1_RST(n) (((n)&0xFFFFF)<<0)
+#define SYS_CTRL_AP_SET_APB1_RST_MASK (0xFFFFF<<0)
+#define SYS_CTRL_AP_SET_APB1_RST_SHIFT (0)
+
+//APB1_Rst_Clr
+#define SYS_CTRL_AP_CLR_APB1_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_APB1_RST_TIMER (1<<1)
+#define SYS_CTRL_AP_CLR_APB1_RST_KEYPAD (1<<2)
+#define SYS_CTRL_AP_CLR_APB1_RST_GPIO (1<<3)
+#define SYS_CTRL_AP_CLR_APB1_RST_PWM (1<<4)
+#define SYS_CTRL_AP_CLR_APB1_RST_AIF (1<<5)
+#define SYS_CTRL_AP_CLR_APB1_RST_AIF2 (1<<6)
+#define SYS_CTRL_AP_CLR_APB1_RST_AUIFC (1<<7)
+#define SYS_CTRL_AP_CLR_APB1_RST_COM_REGS (1<<8)
+#define SYS_CTRL_AP_CLR_APB1_RST_DMC (1<<9)
+#define SYS_CTRL_AP_CLR_APB1_RST_DDRPHY_P (1<<10)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_XCPU (1<<11)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BCPU (1<<12)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_AHBC (1<<13)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_DMA (1<<14)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_A2A (1<<15)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_XIFC (1<<16)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BIFC (1<<17)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BAHBC (1<<18)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_MEM_BRIDGE (1<<19)
+#define SYS_CTRL_AP_CLR_APB1_RST(n) (((n)&0xFFFFF)<<0)
+#define SYS_CTRL_AP_CLR_APB1_RST_MASK (0xFFFFF<<0)
+#define SYS_CTRL_AP_CLR_APB1_RST_SHIFT (0)
+
+//APB2_Rst_Set
+#define SYS_CTRL_AP_SET_APB2_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_APB2_RST_IFC (1<<1)
+#define SYS_CTRL_AP_SET_APB2_RST_UART1 (1<<2)
+#define SYS_CTRL_AP_SET_APB2_RST_UART2 (1<<3)
+#define SYS_CTRL_AP_SET_APB2_RST_UART3 (1<<4)
+#define SYS_CTRL_AP_SET_APB2_RST_SPI1 (1<<5)
+#define SYS_CTRL_AP_SET_APB2_RST_SPI2 (1<<6)
+#define SYS_CTRL_AP_SET_APB2_RST_SPI3 (1<<7)
+#define SYS_CTRL_AP_SET_APB2_RST_SDMMC1 (1<<8)
+#define SYS_CTRL_AP_SET_APB2_RST_SDMMC2 (1<<9)
+#define SYS_CTRL_AP_SET_APB2_RST_SDMMC3 (1<<10)
+#define SYS_CTRL_AP_SET_APB2_RST_NANDFLASH (1<<11)
+#define SYS_CTRL_AP_SET_APB2_RST_I2C1 (1<<12)
+#define SYS_CTRL_AP_SET_APB2_RST_I2C2 (1<<13)
+#define SYS_CTRL_AP_SET_APB2_RST_I2C3 (1<<14)
+#define SYS_CTRL_AP_SET_APB2_RST(n) (((n)&0x7FFF)<<0)
+#define SYS_CTRL_AP_SET_APB2_RST_MASK (0x7FFF<<0)
+#define SYS_CTRL_AP_SET_APB2_RST_SHIFT (0)
+
+//APB2_Rst_Clr
+#define SYS_CTRL_AP_CLR_APB2_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_APB2_RST_IFC (1<<1)
+#define SYS_CTRL_AP_CLR_APB2_RST_UART1 (1<<2)
+#define SYS_CTRL_AP_CLR_APB2_RST_UART2 (1<<3)
+#define SYS_CTRL_AP_CLR_APB2_RST_UART3 (1<<4)
+#define SYS_CTRL_AP_CLR_APB2_RST_SPI1 (1<<5)
+#define SYS_CTRL_AP_CLR_APB2_RST_SPI2 (1<<6)
+#define SYS_CTRL_AP_CLR_APB2_RST_SPI3 (1<<7)
+#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC1 (1<<8)
+#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC2 (1<<9)
+#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC3 (1<<10)
+#define SYS_CTRL_AP_CLR_APB2_RST_NANDFLASH (1<<11)
+#define SYS_CTRL_AP_CLR_APB2_RST_I2C1 (1<<12)
+#define SYS_CTRL_AP_CLR_APB2_RST_I2C2 (1<<13)
+#define SYS_CTRL_AP_CLR_APB2_RST_I2C3 (1<<14)
+#define SYS_CTRL_AP_CLR_APB2_RST(n) (((n)&0x7FFF)<<0)
+#define SYS_CTRL_AP_CLR_APB2_RST_MASK (0x7FFF<<0)
+#define SYS_CTRL_AP_CLR_APB2_RST_SHIFT (0)
+
+//MEM_Rst_Set
+#define SYS_CTRL_AP_SET_MEM_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_MEM_RST_DMC (1<<1)
+#define SYS_CTRL_AP_SET_MEM_RST_DDRPHY_P (1<<2)
+#define SYS_CTRL_AP_SET_MEM_RST(n)  (((n)&0x7)<<0)
+#define SYS_CTRL_AP_SET_MEM_RST_MASK (0x7<<0)
+#define SYS_CTRL_AP_SET_MEM_RST_SHIFT (0)
+
+//MEM_Rst_Clr
+#define SYS_CTRL_AP_CLR_MEM_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_MEM_RST_DMC (1<<1)
+#define SYS_CTRL_AP_CLR_MEM_RST_DDRPHY_P (1<<2)
+#define SYS_CTRL_AP_CLR_MEM_RST(n)  (((n)&0x7)<<0)
+#define SYS_CTRL_AP_CLR_MEM_RST_MASK (0x7<<0)
+#define SYS_CTRL_AP_CLR_MEM_RST_SHIFT (0)
+
+//Clk_CPU_Mode
+#define SYS_CTRL_AP_MODE_CLK_CPU_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_CLK_CPU_MANUAL (1<<0)
+
+//Clk_CPU_Enable
+#define SYS_CTRL_AP_ENABLE_CPU_CORE (1<<0)
+#define SYS_CTRL_AP_ENABLE_CPU_DUMMY (1<<1)
+#define SYS_CTRL_AP_ENABLE_CLK_CPU(n) (((n)&3)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_CPU_MASK (3<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_CPU_SHIFT (0)
+
+//Clk_CPU_Disable
+#define SYS_CTRL_AP_DISABLE_CPU_CORE (1<<0)
+#define SYS_CTRL_AP_DISABLE_CPU_DUMMY (1<<1)
+#define SYS_CTRL_AP_DISABLE_CLK_CPU(n) (((n)&3)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_CPU_MASK (3<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_CPU_SHIFT (0)
+
+//Clk_AXI_Mode
+#define SYS_CTRL_AP_MODE_AHB0_CONF_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_AHB0_CONF_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_APB0_CONF_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_APB0_CONF_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_AXI_VOC_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_AXI_VOC_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_AXI_VOC2_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_AXI_VOC2_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_AXI_DMA_AUTOMATIC (0<<4)
+#define SYS_CTRL_AP_MODE_AXI_DMA_MANUAL (1<<4)
+#define SYS_CTRL_AP_MODE_CLK_AXI(n) (((n)&0x1F)<<0)
+#define SYS_CTRL_AP_MODE_CLK_AXI_MASK (0x1F<<0)
+#define SYS_CTRL_AP_MODE_CLK_AXI_SHIFT (0)
+
+//Clk_AXI_Enable
+#define SYS_CTRL_AP_ENABLE_AHB0_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_APB0_CONF (1<<1)
+#define SYS_CTRL_AP_ENABLE_AXI_VOC  (1<<2)
+#define SYS_CTRL_AP_ENABLE_AXI_VOC2  (1<<3)
+#define SYS_CTRL_AP_ENABLE_AXI_DMA  (1<<4)
+#define SYS_CTRL_AP_ENABLE_AXI_ALWAYS (1<<5)
+#define SYS_CTRL_AP_ENABLE_AXI_CONNECT (1<<6)
+#define SYS_CTRL_AP_ENABLE_AXI_VPU (1<<7)
+#define SYS_CTRL_AP_ENABLE_APB0_IRQ (1<<8)
+#define SYS_CTRL_AP_ENABLE_CLK_AXI(n) (((n)&0x1FF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AXI_MASK (0x1FF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AXI_SHIFT (0)
+
+//Clk_AXI_Disable
+#define SYS_CTRL_AP_DISABLE_AHB0_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_APB0_CONF (1<<1)
+#define SYS_CTRL_AP_DISABLE_AXI_VOC (1<<2)
+#define SYS_CTRL_AP_DISABLE_AXI_VOC2 (1<<3)
+#define SYS_CTRL_AP_DISABLE_AXI_DMA (1<<4)
+#define SYS_CTRL_AP_DISABLE_AXI_ALWAYS (1<<5)
+#define SYS_CTRL_AP_DISABLE_AXI_CONNECT (1<<6)
+#define SYS_CTRL_AP_DISABLE_AXI_VPU (1<<7)
+#define SYS_CTRL_AP_DISABLE_APB0_IRQ (1<<8)
+#define SYS_CTRL_AP_DISABLE_CLK_AXI(n) (((n)&0x1FF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AXI_MASK (0x1FF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AXI_SHIFT (0)
+
+//Clk_AXIDIV2_Mode
+#define SYS_CTRL_AP_MODE_CLK_AXIDIV2_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_CLK_AXIDIV2_MANUAL (1<<0)
+
+//Clk_AXIDIV2_Enable
+#define SYS_CTRL_AP_ENABLE_AXIDIV2_IMEM (1<<0)
+#define SYS_CTRL_AP_ENABLE_AXIDIV2_ALWAYS (1<<1)
+#define SYS_CTRL_AP_ENABLE_AXIDIV2_CONNECT (1<<2)
+#define SYS_CTRL_AP_ENABLE_AXIDIV2_VPU (1<<3)
+#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2(n) (((n)&15)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2_MASK (15<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2_SHIFT (0)
+
+//Clk_AXIDIV2_Disable
+#define SYS_CTRL_AP_DISABLE_AXIDIV2_IMEM (1<<0)
+#define SYS_CTRL_AP_DISABLE_AXIDIV2_ALWAYS (1<<1)
+#define SYS_CTRL_AP_DISABLE_AXIDIV2_CONNECT (1<<2)
+#define SYS_CTRL_AP_DISABLE_AXIDIV2_VPU (1<<3)
+#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2(n) (((n)&15)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2_MASK (15<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2_SHIFT (0)
+
+//Clk_GCG_Mode
+#define SYS_CTRL_AP_MODE_GCG_APB_CONF_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_GCG_APB_CONF_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_GCG_GOUDA_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_GCG_GOUDA_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_GCG_CAMERA_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_GCG_CAMERA_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_GCG_CAMERA2_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_GCG_CAMERA2_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_CLK_GCG(n) (((n)&0xF)<<0)
+#define SYS_CTRL_AP_MODE_CLK_GCG_MASK (0xF<<0)
+#define SYS_CTRL_AP_MODE_CLK_GCG_SHIFT (0)
+
+//Clk_GCG_Enable
+#define SYS_CTRL_AP_ENABLE_GCG_APB_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_GCG_GOUDA (1<<1)
+#define SYS_CTRL_AP_ENABLE_GCG_CAMERA (1<<2)
+#define SYS_CTRL_AP_ENABLE_GCG_CAMERA2 (1<<3)
+#define SYS_CTRL_AP_ENABLE_GCG_ALWAYS (1<<4)
+#define SYS_CTRL_AP_ENABLE_GCG_CONNECT (1<<5)
+#define SYS_CTRL_AP_ENABLE_GCG_GOUDA_AW (1<<6)
+#define SYS_CTRL_AP_ENABLE_GCG_GOUDA_DPI (1<<7)
+#define SYS_CTRL_AP_ENABLE_CLK_GCG(n) (((n)&0xFF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_GCG_MASK (0xFF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_GCG_SHIFT (0)
+
+//Clk_GCG_Disable
+#define SYS_CTRL_AP_DISABLE_GCG_APB_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_GCG_GOUDA (1<<1)
+#define SYS_CTRL_AP_DISABLE_GCG_CAMERA (1<<2)
+#define SYS_CTRL_AP_DISABLE_GCG_CAMERA2 (1<<3)
+#define SYS_CTRL_AP_DISABLE_GCG_ALWAYS (1<<4)
+#define SYS_CTRL_AP_DISABLE_GCG_CONNECT (1<<5)
+#define SYS_CTRL_AP_DISABLE_GCG_GOUDA_AW (1<<6)
+#define SYS_CTRL_AP_DISABLE_GCG_GOUDA_DPI (1<<7)
+#define SYS_CTRL_AP_DISABLE_CLK_GCG(n) (((n)&0xFF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_GCG_MASK (0xFF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_GCG_SHIFT (0)
+
+//Clk_AHB1_Mode
+#define SYS_CTRL_AP_MODE_CLK_AHB1_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_CLK_AHB1_MANUAL (1<<0)
+
+//Clk_AHB1_Enable
+#define SYS_CTRL_AP_ENABLE_AHB1_USBC (1<<0)
+#define SYS_CTRL_AP_ENABLE_AHB1_ALWAYS (1<<1)
+#define SYS_CTRL_AP_ENABLE_AHB1_SPIFLASH (1<<2)
+#define SYS_CTRL_AP_ENABLE_AHB1_EMAC (1<<3)
+#define SYS_CTRL_AP_ENABLE_CLK_AHB1(n) (((n)&0xF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AHB1_MASK (0xF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AHB1_SHIFT (0)
+
+//Clk_AHB1_Disable
+#define SYS_CTRL_AP_DISABLE_AHB1_USBC (1<<0)
+#define SYS_CTRL_AP_DISABLE_AHB1_ALWAYS (1<<1)
+#define SYS_CTRL_AP_DISABLE_AHB1_SPIFLASH (1<<2)
+#define SYS_CTRL_AP_DISABLE_AHB1_EMAC (1<<3)
+#define SYS_CTRL_AP_DISABLE_CLK_AHB1(n) (((n)&0xF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AHB1_MASK (0xF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AHB1_SHIFT (0)
+
+//Clk_APB1_Mode
+#define SYS_CTRL_AP_MODE_APB1_CONF_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_APB1_CONF_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_APB1_AIF_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_APB1_AIF_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_APB1_AIF2_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_APB1_AIF2_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH0_AUTOMATIC (0<<4)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH0_MANUAL (1<<4)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH1_AUTOMATIC (0<<5)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH1_MANUAL (1<<5)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH2_AUTOMATIC (0<<6)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH2_MANUAL (1<<6)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH3_AUTOMATIC (0<<7)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH3_MANUAL (1<<7)
+#define SYS_CTRL_AP_MODE_APB1D_OSC_AUTOMATIC (0<<8)
+#define SYS_CTRL_AP_MODE_APB1D_OSC_MANUAL (1<<8)
+#define SYS_CTRL_AP_MODE_APB1D_OSC2_AUTOMATIC (0<<9)
+#define SYS_CTRL_AP_MODE_APB1D_OSC2_MANUAL (1<<9)
+#define SYS_CTRL_AP_MODE_APB1D_OSC3_AUTOMATIC (0<<10)
+#define SYS_CTRL_AP_MODE_APB1D_OSC3_MANUAL (1<<10)
+#define SYS_CTRL_AP_MODE_APB1D_PWM_AUTOMATIC (0<<11)
+#define SYS_CTRL_AP_MODE_APB1D_PWM_MANUAL (1<<11)
+#define SYS_CTRL_AP_MODE_CLK_APB1(n) (((n)&0xFFF)<<0)
+#define SYS_CTRL_AP_MODE_CLK_APB1_MASK (0xFFF<<0)
+#define SYS_CTRL_AP_MODE_CLK_APB1_SHIFT (0)
+
+//Clk_APB1_Enable
+#define SYS_CTRL_AP_ENABLE_APB1_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_APB1_AIF (1<<1)
+#define SYS_CTRL_AP_ENABLE_APB1_AIF2 (1<<2)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC (1<<3)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH0 (1<<4)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH1 (1<<5)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH2 (1<<6)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH3 (1<<7)
+#define SYS_CTRL_AP_ENABLE_APB1D_OSC (1<<8)
+#define SYS_CTRL_AP_ENABLE_APB1D_OSC2 (1<<9)
+#define SYS_CTRL_AP_ENABLE_APB1D_OSC3 (1<<10)
+#define SYS_CTRL_AP_ENABLE_APB1D_PWM (1<<11)
+#define SYS_CTRL_AP_ENABLE_APB1_ALWAYS (1<<12)
+#define SYS_CTRL_AP_ENABLE_APB1_DAPLITE (1<<13)
+#define SYS_CTRL_AP_ENABLE_APB1_TIMER (1<<14)
+#define SYS_CTRL_AP_ENABLE_APB1_GPIO (1<<15)
+#define SYS_CTRL_AP_ENABLE_CLK_APB1(n) (((n)&0xFFFF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APB1_MASK (0xFFFF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APB1_SHIFT (0)
+
+//Clk_APB1_Disable
+#define SYS_CTRL_AP_DISABLE_APB1_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_APB1_AIF (1<<1)
+#define SYS_CTRL_AP_DISABLE_APB1_AIF2 (1<<2)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC (1<<3)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH0 (1<<4)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH1 (1<<5)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH2 (1<<6)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH3 (1<<7)
+#define SYS_CTRL_AP_DISABLE_APB1D_OSC (1<<8)
+#define SYS_CTRL_AP_DISABLE_APB1D_OSC2 (1<<9)
+#define SYS_CTRL_AP_DISABLE_APB1D_OSC3 (1<<10)
+#define SYS_CTRL_AP_DISABLE_APB1D_PWM (1<<11)
+#define SYS_CTRL_AP_DISABLE_APB1_ALWAYS (1<<12)
+#define SYS_CTRL_AP_DISABLE_APB1_DAPLITE (1<<13)
+#define SYS_CTRL_AP_DISABLE_APB1_TIMER (1<<14)
+#define SYS_CTRL_AP_DISABLE_APB1_GPIO (1<<15)
+#define SYS_CTRL_AP_DISABLE_CLK_APB1(n) (((n)&0xFFFF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APB1_MASK (0xFFFF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APB1_SHIFT (0)
+
+//Clk_APB2_Mode
+#define SYS_CTRL_AP_MODE_APB2_CONF_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_APB2_CONF_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_APB2_IFC_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_APB2_IFC_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH0_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH0_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH1_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH1_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH2_AUTOMATIC (0<<4)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH2_MANUAL (1<<4)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH3_AUTOMATIC (0<<5)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH3_MANUAL (1<<5)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH4_AUTOMATIC (0<<6)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH4_MANUAL (1<<6)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH5_AUTOMATIC (0<<7)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH5_MANUAL (1<<7)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH6_AUTOMATIC (0<<8)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH6_MANUAL (1<<8)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH7_AUTOMATIC (0<<9)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH7_MANUAL (1<<9)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH8_AUTOMATIC (0<<10)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH8_MANUAL (1<<10)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH9_AUTOMATIC (0<<11)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH9_MANUAL (1<<11)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH10_AUTOMATIC (0<<12)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH10_MANUAL (1<<12)
+#define SYS_CTRL_AP_MODE_APB2_UART1_AUTOMATIC (0<<13)
+#define SYS_CTRL_AP_MODE_APB2_UART1_MANUAL (1<<13)
+#define SYS_CTRL_AP_MODE_APB2_UART2_AUTOMATIC (0<<14)
+#define SYS_CTRL_AP_MODE_APB2_UART2_MANUAL (1<<14)
+#define SYS_CTRL_AP_MODE_APB2_UART3_AUTOMATIC (0<<15)
+#define SYS_CTRL_AP_MODE_APB2_UART3_MANUAL (1<<15)
+#define SYS_CTRL_AP_MODE_APB2_SPI1_AUTOMATIC (0<<16)
+#define SYS_CTRL_AP_MODE_APB2_SPI1_MANUAL (1<<16)
+#define SYS_CTRL_AP_MODE_APB2_SPI2_AUTOMATIC (0<<17)
+#define SYS_CTRL_AP_MODE_APB2_SPI2_MANUAL (1<<17)
+#define SYS_CTRL_AP_MODE_APB2_SPI3_AUTOMATIC (0<<18)
+#define SYS_CTRL_AP_MODE_APB2_SPI3_MANUAL (1<<18)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC1_AUTOMATIC (0<<19)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC1_MANUAL (1<<19)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC2_AUTOMATIC (0<<20)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC2_MANUAL (1<<20)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC3_AUTOMATIC (0<<21)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC3_MANUAL (1<<21)
+#define SYS_CTRL_AP_MODE_APB2_I2C1_AUTOMATIC (0<<22)
+#define SYS_CTRL_AP_MODE_APB2_I2C1_MANUAL (1<<22)
+#define SYS_CTRL_AP_MODE_APB2_I2C2_AUTOMATIC (0<<23)
+#define SYS_CTRL_AP_MODE_APB2_I2C2_MANUAL (1<<23)
+#define SYS_CTRL_AP_MODE_APB2_I2C3_AUTOMATIC (0<<24)
+#define SYS_CTRL_AP_MODE_APB2_I2C3_MANUAL (1<<24)
+#define SYS_CTRL_AP_MODE_CLK_APB2(n) (((n)&0x1FFFFFF)<<0)
+#define SYS_CTRL_AP_MODE_CLK_APB2_MASK (0x1FFFFFF<<0)
+#define SYS_CTRL_AP_MODE_CLK_APB2_SHIFT (0)
+
+//Clk_APB2_Enable
+#define SYS_CTRL_AP_ENABLE_APB2_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC (1<<1)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH0 (1<<2)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH1 (1<<3)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH2 (1<<4)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH3 (1<<5)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH4 (1<<6)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH5 (1<<7)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH6 (1<<8)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH7 (1<<9)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH8 (1<<10)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH9 (1<<11)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH10 (1<<12)
+#define SYS_CTRL_AP_ENABLE_APB2_UART1 (1<<13)
+#define SYS_CTRL_AP_ENABLE_APB2_UART2 (1<<14)
+#define SYS_CTRL_AP_ENABLE_APB2_UART3 (1<<15)
+#define SYS_CTRL_AP_ENABLE_APB2_SPI1 (1<<16)
+#define SYS_CTRL_AP_ENABLE_APB2_SPI2 (1<<17)
+#define SYS_CTRL_AP_ENABLE_APB2_SPI3 (1<<18)
+#define SYS_CTRL_AP_ENABLE_APB2_SDMMC1 (1<<19)
+#define SYS_CTRL_AP_ENABLE_APB2_SDMMC2 (1<<20)
+#define SYS_CTRL_AP_ENABLE_APB2_SDMMC3 (1<<21)
+#define SYS_CTRL_AP_ENABLE_APB2_I2C1 (1<<22)
+#define SYS_CTRL_AP_ENABLE_APB2_I2C2 (1<<23)
+#define SYS_CTRL_AP_ENABLE_APB2_I2C3 (1<<24)
+#define SYS_CTRL_AP_ENABLE_APB2_ALWAYS (1<<25)
+#define SYS_CTRL_AP_ENABLE_APB2_NANDFLASH (1<<26)
+#define SYS_CTRL_AP_ENABLE_CLK_APB2(n) (((n)&0x7FFFFFF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APB2_MASK (0x7FFFFFF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APB2_SHIFT (0)
+
+//Clk_APB2_Disable
+#define SYS_CTRL_AP_DISABLE_APB2_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC (1<<1)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH0 (1<<2)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH1 (1<<3)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH2 (1<<4)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH3 (1<<5)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH4 (1<<6)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH5 (1<<7)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH6 (1<<8)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH7 (1<<9)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH8 (1<<10)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH9 (1<<11)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH10 (1<<12)
+#define SYS_CTRL_AP_DISABLE_APB2_UART1 (1<<13)
+#define SYS_CTRL_AP_DISABLE_APB2_UART2 (1<<14)
+#define SYS_CTRL_AP_DISABLE_APB2_UART3 (1<<15)
+#define SYS_CTRL_AP_DISABLE_APB2_SPI1 (1<<16)
+#define SYS_CTRL_AP_DISABLE_APB2_SPI2 (1<<17)
+#define SYS_CTRL_AP_DISABLE_APB2_SPI3 (1<<18)
+#define SYS_CTRL_AP_DISABLE_APB2_SDMMC1 (1<<19)
+#define SYS_CTRL_AP_DISABLE_APB2_SDMMC2 (1<<20)
+#define SYS_CTRL_AP_DISABLE_APB2_SDMMC3 (1<<21)
+#define SYS_CTRL_AP_DISABLE_APB2_I2C1 (1<<22)
+#define SYS_CTRL_AP_DISABLE_APB2_I2C2 (1<<23)
+#define SYS_CTRL_AP_DISABLE_APB2_I2C3 (1<<24)
+#define SYS_CTRL_AP_DISABLE_APB2_ALWAYS (1<<25)
+#define SYS_CTRL_AP_DISABLE_APB2_NANDFLASH (1<<26)
+#define SYS_CTRL_AP_DISABLE_CLK_APB2(n) (((n)&0x7FFFFFF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APB2_MASK (0x7FFFFFF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APB2_SHIFT (0)
+
+//Clk_MEM_Mode
+#define SYS_CTRL_AP_MODE_CLK_MEM_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_CLK_MEM_MANUAL (1<<0)
+
+//Clk_MEM_Enable
+#define SYS_CTRL_AP_ENABLE_MEM_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_MEM_DMC  (1<<1)
+#define SYS_CTRL_AP_ENABLE_MEM_DDRPHY_P (1<<2)
+#define SYS_CTRL_AP_ENABLE_MEM_CONNECT (1<<3)
+#define SYS_CTRL_AP_ENABLE_CLK_MEM(n) (((n)&0xF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_MEM_MASK (0xF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_MEM_SHIFT (0)
+
+//Clk_MEM_Disable
+#define SYS_CTRL_AP_DISABLE_MEM_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_MEM_DMC (1<<1)
+#define SYS_CTRL_AP_DISABLE_MEM_DDRPHY_P (1<<2)
+#define SYS_CTRL_AP_DISABLE_MEM_CONNECT (1<<3)
+#define SYS_CTRL_AP_DISABLE_CLK_MEM(n) (((n)&0xF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_MEM_MASK (0xF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_MEM_SHIFT (0)
+
+//Clk_APO_Mode
+#define SYS_CTRL_AP_MODE_APOC_BCK_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_APOC_BCK_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_APOC_BCK2_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_APOC_BCK2_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_APOC_UART1_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_APOC_UART1_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_APOC_UART2_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_APOC_UART2_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_APOC_UART3_AUTOMATIC (0<<4)
+#define SYS_CTRL_AP_MODE_APOC_UART3_MANUAL (1<<4)
+#define SYS_CTRL_AP_MODE_APOC_VOC_CORE_AUTOMATIC (0<<5)
+#define SYS_CTRL_AP_MODE_APOC_VOC_CORE_MANUAL (1<<5)
+#define SYS_CTRL_AP_MODE_APOC_VOC2_CORE_AUTOMATIC (0<<6)
+#define SYS_CTRL_AP_MODE_APOC_VOC2_CORE_MANUAL (1<<6)
+#define SYS_CTRL_AP_MODE_APOC_VOC_AUTOMATIC (0<<7)
+#define SYS_CTRL_AP_MODE_APOC_VOC_MANUAL (1<<7)
+#define SYS_CTRL_AP_MODE_APOC_VOC2_AUTOMATIC (0<<8)
+#define SYS_CTRL_AP_MODE_APOC_VOC2_MANUAL (1<<8)
+#define SYS_CTRL_AP_MODE_CLK_APO(n) (((n)&01FF)<<0)
+#define SYS_CTRL_AP_MODE_CLK_APO_MASK (0x1FF<<0)
+#define SYS_CTRL_AP_MODE_CLK_APO_SHIFT (0)
+
+//Clk_APO_Enable
+#define SYS_CTRL_AP_ENABLE_APOC_BCK (1<<0)
+#define SYS_CTRL_AP_ENABLE_APOC_BCK2 (1<<1)
+#define SYS_CTRL_AP_ENABLE_APOC_UART1 (1<<2)
+#define SYS_CTRL_AP_ENABLE_APOC_UART2 (1<<3)
+#define SYS_CTRL_AP_ENABLE_APOC_UART3 (1<<4)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC_CORE (1<<5)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC2_CORE (1<<6)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC (1<<7)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC2 (1<<8)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC_ALWAYS (1<<9)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC2_ALWAYS (1<<10)
+#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY_N (1<<11)
+#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY2XP (1<<12)
+#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY2XN (1<<13)
+#define SYS_CTRL_AP_ENABLE_APOC_VPU (1<<14)
+#define SYS_CTRL_AP_ENABLE_APOC_GPU (1<<15)
+#define SYS_CTRL_AP_ENABLE_APOC_USBPHY (1<<16)
+#define SYS_CTRL_AP_ENABLE_APOC_CSI (1<<17)
+#define SYS_CTRL_AP_ENABLE_APOC_CSI2 (1<<18)
+#define SYS_CTRL_AP_ENABLE_APOC_DSI (1<<19)
+#define SYS_CTRL_AP_ENABLE_APOC_GPIO (1<<20)
+#define SYS_CTRL_AP_ENABLE_APOC_SPIFLASH (1<<21)
+#define SYS_CTRL_AP_ENABLE_APOC_PIX (1<<22)
+#define SYS_CTRL_AP_ENABLE_APOC_PIX2 (1<<23)
+#define SYS_CTRL_AP_ENABLE_APOC_PDGB (1<<24)
+#define SYS_CTRL_AP_ENABLE_CLK_APO(n) (((n)&0x1FFFFFF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APO_MASK (0x1FFFFFF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APO_SHIFT (0)
+
+//Clk_APO_Disable
+#define SYS_CTRL_AP_DISABLE_APOC_BCK (1<<0)
+#define SYS_CTRL_AP_DISABLE_APOC_BCK2 (1<<1)
+#define SYS_CTRL_AP_DISABLE_APOC_UART1 (1<<2)
+#define SYS_CTRL_AP_DISABLE_APOC_UART2 (1<<3)
+#define SYS_CTRL_AP_DISABLE_APOC_UART3 (1<<4)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC_CORE (1<<5)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC2_CORE (1<<6)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC (1<<7)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC2 (1<<8)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC_ALWAYS (1<<9)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC2_ALWAYS (1<<10)
+#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY_N (1<<11)
+#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY2XP (1<<12)
+#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY2XN (1<<13)
+#define SYS_CTRL_AP_DISABLE_APOC_VPU (1<<14)
+#define SYS_CTRL_AP_DISABLE_APOC_GPU (1<<15)
+#define SYS_CTRL_AP_DISABLE_APOC_USBPHY (1<<16)
+#define SYS_CTRL_AP_DISABLE_APOC_CSI (1<<17)
+#define SYS_CTRL_AP_DISABLE_APOC_CSI2 (1<<18)
+#define SYS_CTRL_AP_DISABLE_APOC_DSI (1<<19)
+#define SYS_CTRL_AP_DISABLE_APOC_GPIO (1<<20)
+#define SYS_CTRL_AP_DISABLE_APOC_SPIFLASH (1<<21)
+#define SYS_CTRL_AP_DISABLE_APOC_PIX (1<<22)
+#define SYS_CTRL_AP_DISABLE_APOC_PIX2 (1<<23)
+#define SYS_CTRL_AP_DISABLE_APOC_PDGB (1<<24)
+#define SYS_CTRL_AP_DISABLE_CLK_APO(n) (((n)&0x1FFFFFF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APO_MASK (0x1FFFFFF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APO_SHIFT (0)
+
+//Cfg_Clk_AP_CPU
+#define SYS_CTRL_AP_AP_CPU_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_BUS_DIV_SEL(n)  (((n)&3)<<16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_MASK (3<<16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_SHIFT (16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_DIV2 (0<<16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_DIV3 (1<<16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_DIV4 (2<<16)
+#define SYS_CTRL_AP_DBG_CLKDIV_SEL(n)  (((n)&15)<<20)
+#define SYS_CTRL_AP_DBG_CLKDIV_DIV_SEL_MASK (15<<20)
+#define SYS_CTRL_AP_DBG_CLKDIV_SEL_SHIFT (20)
+#define SYS_CTRL_AP_AP_CPU_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_AXI
+#define SYS_CTRL_AP_AP_AXI_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_AXI_SRC_SEL  (1<<12)
+#define SYS_CTRL_AP_AP_AXI_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_GCG
+#define SYS_CTRL_AP_AP_GCG_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_GCG_SRC_SEL  (1<<12)
+#define SYS_CTRL_AP_AP_GCG_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_AHB1
+#define SYS_CTRL_AP_AP_AHB1_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_AHB1_SRC_SEL (1<<12)
+#define SYS_CTRL_AP_AP_AHB1_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_APB1
+#define SYS_CTRL_AP_AP_APB1_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_APB1_SRC_SEL (1<<12)
+#define SYS_CTRL_AP_AP_APB1_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_APB2
+#define SYS_CTRL_AP_AP_APB2_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_APB2_SRC_SEL (1<<12)
+#define SYS_CTRL_AP_AP_APB2_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_MEM
+#define SYS_CTRL_AP_AP_MEM_SRC_DIV2 (1<<12)
+
+//Cfg_Clk_AP_GPU
+#define SYS_CTRL_AP_AP_GPU_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_GPU_SRC_DIV2 (1<<12)
+#define SYS_CTRL_AP_AP_GPU_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_VPU
+#define SYS_CTRL_AP_AP_VPU_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_VPU_SRC_DIV2 (1<<12)
+#define SYS_CTRL_AP_AP_VPU_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_VOC
+#define SYS_CTRL_AP_AP_VOC_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_VOC_SRC_DIV2 (1<<12)
+#define SYS_CTRL_AP_AP_VOC_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_SFLSH
+#define SYS_CTRL_AP_AP_SFLSH_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_SFLSH_SRC_DIV2 (1<<12)
+#define SYS_CTRL_AP_AP_SFLSH_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_Uart
+#define SYS_CTRL_AP_UART_DIVIDER(n) (((n)&0x3FF)<<0)
+#define SYS_CTRL_AP_UART_DIVIDER_MASK (0x3FF<<0)
+#define SYS_CTRL_AP_UART_DIVIDER_SHIFT (0)
+#define SYS_CTRL_AP_UART_SEL_PLL_SLOW (0<<12)
+#define SYS_CTRL_AP_UART_SEL_PLL_PLL (1<<12)
+
+//L2cc_Ctrl
+#define SYS_CTRL_AP_ARQOS_L2CC_1_M(n) (((n)&15)<<0)
+#define SYS_CTRL_AP_ARQOS_L2CC_1_M_MASK (15<<0)
+#define SYS_CTRL_AP_ARQOS_L2CC_1_M_SHIFT (0)
+#define SYS_CTRL_AP_AWQOS_L2CC_1_M(n) (((n)&15)<<4)
+#define SYS_CTRL_AP_AWQOS_L2CC_1_M_MASK (15<<4)
+#define SYS_CTRL_AP_AWQOS_L2CC_1_M_SHIFT (4)
+#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M(n) (((n)&15)<<8)
+#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M_MASK (15<<8)
+#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M_SHIFT (8)
+#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M(n) (((n)&15)<<12)
+#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M_MASK (15<<12)
+#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M_SHIFT (12)
+#define SYS_CTRL_AP_ARAP_L2CC_1_M   (1<<16)
+#define SYS_CTRL_AP_AWAP_L2CC_1_M   (1<<17)
+#define SYS_CTRL_AP_ARAP_MODEM_MEM_AHBS_M (1<<18)
+#define SYS_CTRL_AP_AWAP_MODEM_MEM_AHBS_M (1<<19)
+#define SYS_CTRL_AP_ARAP_MERGE1M    (1<<20)
+#define SYS_CTRL_AP_AWAP_MERGE1M    (1<<21)
+#define SYS_CTRL_AP_ARAP_MERGE2M    (1<<22)
+#define SYS_CTRL_AP_AWAP_MERGE2M    (1<<23)
+#define SYS_CTRL_AP_RESERVE1(n)     (((n)&0xFF)<<24)
+#define SYS_CTRL_AP_RESERVE1_MASK   (0xFF<<24)
+#define SYS_CTRL_AP_RESERVE1_SHIFT  (24)
+
+//Spi_Ctrl
+#define SYS_CTRL_AP_LIMITED_EN_SPI1 (1<<0)
+#define SYS_CTRL_AP_LPSEN_SPI1      (1<<1)
+#define SYS_CTRL_AP_LIMITED_EN_SPI2 (1<<2)
+#define SYS_CTRL_AP_LPSEN_SPI2      (1<<3)
+#define SYS_CTRL_AP_LIMITED_EN_SPI3 (1<<4)
+#define SYS_CTRL_AP_LPSEN_SPI3      (1<<5)
+#define SYS_CTRL_AP_FBUSWID_NFSC    (1<<6)
+#define SYS_CTRL_AP_RESERVE3        (1<<7)
+#define SYS_CTRL_AP_DMC_CFG(n)      (((n)&0x3FF)<<8)
+#define SYS_CTRL_AP_DMC_CFG_MASK    (0x3FF<<8)
+#define SYS_CTRL_AP_DMC_CFG_SHIFT   (8)
+#define SYS_CTRL_AP_RESERVE2(n)     (((n)&0x3FFF)<<18)
+#define SYS_CTRL_AP_RESERVE2_MASK   (0x3FFF<<18)
+#define SYS_CTRL_AP_RESERVE2_SHIFT  (18)
+
+//Memory_Margin
+#define SYS_CTRL_AP_EMAW_VOC(n)     (((n)&3)<<0)
+#define SYS_CTRL_AP_EMAW_VOC_MASK   (3<<0)
+#define SYS_CTRL_AP_EMAW_VOC_SHIFT  (0)
+#define SYS_CTRL_AP_EMA_VOC(n)      (((n)&7)<<2)
+#define SYS_CTRL_AP_EMA_VOC_MASK    (7<<2)
+#define SYS_CTRL_AP_EMA_VOC_SHIFT   (2)
+#define SYS_CTRL_AP_EMAW_VPU(n)     (((n)&3)<<5)
+#define SYS_CTRL_AP_EMAW_VPU_MASK   (3<<5)
+#define SYS_CTRL_AP_EMAW_VPU_SHIFT  (5)
+#define SYS_CTRL_AP_EMA_VPU(n)      (((n)&7)<<7)
+#define SYS_CTRL_AP_EMA_VPU_MASK    (7<<7)
+#define SYS_CTRL_AP_EMA_VPU_SHIFT   (7)
+#define SYS_CTRL_AP_EMAW_GPU(n)     (((n)&3)<<10)
+#define SYS_CTRL_AP_EMAW_GPU_MASK   (3<<10)
+#define SYS_CTRL_AP_EMAW_GPU_SHIFT  (10)
+#define SYS_CTRL_AP_EMA_GPU(n)      (((n)&7)<<12)
+#define SYS_CTRL_AP_EMA_GPU_MASK    (7<<12)
+#define SYS_CTRL_AP_EMA_GPU_SHIFT   (12)
+#define SYS_CTRL_AP_EMAW_GOUDA(n)   (((n)&3)<<15)
+#define SYS_CTRL_AP_EMAW_GOUDA_MASK (3<<15)
+#define SYS_CTRL_AP_EMAW_GOUDA_SHIFT (15)
+#define SYS_CTRL_AP_EMA_GOUDA(n)    (((n)&7)<<17)
+#define SYS_CTRL_AP_EMA_GOUDA_MASK  (7<<17)
+#define SYS_CTRL_AP_EMA_GOUDA_SHIFT (17)
+#define SYS_CTRL_AP_EMAW_IMEM(n)    (((n)&3)<<20)
+#define SYS_CTRL_AP_EMAW_IMEM_MASK  (3<<20)
+#define SYS_CTRL_AP_EMAW_IMEM_SHIFT (20)
+#define SYS_CTRL_AP_EMA_IMEM(n)     (((n)&7)<<22)
+#define SYS_CTRL_AP_EMA_IMEM_MASK   (7<<22)
+#define SYS_CTRL_AP_EMA_IMEM_SHIFT  (22)
+#define SYS_CTRL_AP_EMAW_USB(n)     (((n)&3)<<25)
+#define SYS_CTRL_AP_EMAW_USB_MASK   (3<<25)
+#define SYS_CTRL_AP_EMAW_USB_SHIFT  (25)
+#define SYS_CTRL_AP_EMA_USB(n)      (((n)&7)<<27)
+#define SYS_CTRL_AP_EMA_USB_MASK    (7<<27)
+#define SYS_CTRL_AP_EMA_USB_SHIFT   (27)
+
+//Memory_Margin2
+#define SYS_CTRL_AP_EMAW_NFSC(n)    (((n)&3)<<0)
+#define SYS_CTRL_AP_EMAW_NFSC_MASK  (3<<0)
+#define SYS_CTRL_AP_EMAW_NFSC_SHIFT (0)
+#define SYS_CTRL_AP_EMA_NFSC(n)     (((n)&7)<<2)
+#define SYS_CTRL_AP_EMA_NFSC_MASK   (7<<2)
+#define SYS_CTRL_AP_EMA_NFSC_SHIFT  (2)
+#define SYS_CTRL_AP_EMA_VPUROM(n)   (((n)&7)<<5)
+#define SYS_CTRL_AP_EMA_VPUROM_MASK (7<<5)
+#define SYS_CTRL_AP_EMA_VPUROM_SHIFT (5)
+#define SYS_CTRL_AP_EMA_IMEMROM(n)  (((n)&7)<<8)
+#define SYS_CTRL_AP_EMA_IMEMROM_MASK (7<<8)
+#define SYS_CTRL_AP_EMA_IMEMROM_SHIFT (8)
+#define SYS_CTRL_AP_KEN_VPUROM      (1<<11)
+#define SYS_CTRL_AP_PGEN_VPUROM     (1<<12)
+#define SYS_CTRL_AP_KEN_IMEMROM     (1<<13)
+#define SYS_CTRL_AP_PGEN_IMEMROM    (1<<14)
+
+//Memory_Observe
+#define SYS_CTRL_AP_MEM_OBSERVE(n)  (((n)&0xFFFFFFFF)<<0)
+
+//Cfg_Clk_AP_VOC2
+#define SYS_CTRL_AP_AP_VOC2_FREQ(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_VOC2_FREQ_MASK (31 << 0)
+#define SYS_CTRL_AP_AP_VOC2_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_VOC2_SRC_DIV2  (1<<12)
+#define SYS_CTRL_AP_AP_VOC2_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_EMMC
+#define SYS_CTRL_AP_EMMC_DATA_STB_DLY(n)  (((n)&31)<<0)
+#define SYS_CTRL_AP_EMMC_DATA_STB_DLY_MASK (31 << 0)
+#define SYS_CTRL_AP_EMMC_DATA_STB_DLY_SHIFT 0
+#define SYS_CTRL_AP_EMMC_CLK_DLY(n)  (((n)&31)<<8)
+#define SYS_CTRL_AP_EMMC_CLK_DLY_MASK (31 << 8)
+#define SYS_CTRL_AP_EMMC_CLK_DLY_SHIFT 8
+#define SYS_CTRL_AP_EMMC_CLK_POL  (1<<13)
+
+//Test_Pulse
+#define SYS_CTRL_AP_PULSE_COUNTER(n)  (((n)&0xFFFFFFFF)<<0)
+
+//Cfg_Reserve
+#define SYS_CTRL_AP_RESERVE(n)      (((n)&0xFFFFFFFF)<<0)
+
+#endif
diff --git a/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8850.h b/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8850.h
new file mode 100644
index 0000000000..6b0169fc89
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8850.h
@@ -0,0 +1,1540 @@
+#ifndef _REG_SYSCTRL_H_

+#define _REG_SYSCTRL_H_

+

+#include <asm/arch/hardware.h>

+#include <asm/arch/rda_iomap.h>

+

+// =============================================================================

+//  MACROS

+// =============================================================================

+

+// ============================================================================

+// AP_CPU_ID_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// CPU IDs

+    CPU0                                        = 0x00000000,

+    CPU1                                        = 0x00000001

+} AP_CPU_ID_T;

+

+

+// ============================================================================

+// CPU_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// AP CPU side System clocks

+    CPU_CORE                                    = 0x00000000,

+/// the following don't have an auto enable

+    CPU_DUMMY                                   = 0x00000001

+} CPU_CLKS_T;

+

+#define NB_CPU_CLK_AEN                          (1)

+#define NB_CPU_CLK_EN                           (2)

+#define NB_CPU_CLK                              (2)

+

+// ============================================================================

+// AXI_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// AP AXI side System clocks: AXI and AHB0 and APB0

+    AHB0_CONF                                   = 0x00000000,

+    APB0_CONF                                   = 0x00000001,

+    AXI_VOC                                     = 0x00000002,

+    AXI_VOC2                                    = 0x00000003,

+    AXI_DMA                                     = 0x00000004,

+/// the following don't have an auto enable

+    AXI_ALWAYS                                  = 0x00000005,

+    AXI_CONNECT                                 = 0x00000006,

+    APB0_IRQ                                    = 0x00000007

+} AXI_CLKS_T;

+

+#define NB_AXI_CLK_AEN                          (5)

+#define NB_AXI_CLK_EN                           (8)

+#define NB_AXI_CLK                              (8)

+

+// ============================================================================

+// AXIDIV2_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// AP AXIdiv2 side System clocks

+    AXIDIV2_IMEM                                = 0x00000000,

+/// the following don't have an auto enable

+    AXIDIV2_ALWAYS                              = 0x00000001,

+    AXIDIV2_CONNECT                             = 0x00000002,

+    AXIDIV2_VPU                                 = 0x00000003

+} AXIDIV2_CLKS_T;

+

+#define NB_AXIDIV2_CLK_AEN                      (1)

+#define NB_AXIDIV2_CLK_EN                       (4)

+#define NB_AXIDIV2_CLK                          (4)

+

+// ============================================================================

+// GCG_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// AP GCG side System clocks

+    GCG_APB_CONF                                = 0x00000000,

+    GCG_GOUDA                                   = 0x00000001,

+    GCG_CAMERA                                  = 0x00000002,

+/// the following don't have an auto enable

+    GCG_ALWAYS                                  = 0x00000003,

+    GCG_CONNECT                                 = 0x00000004

+} GCG_CLKS_T;

+

+#define NB_GCG_CLK_AEN                          (3)

+#define NB_GCG_CLK_EN                           (5)

+#define NB_GCG_CLK                              (5)

+

+// ============================================================================

+// AHB1_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// AP AHB1 side System clocks

+    AHB1_USBC                                   = 0x00000000,

+/// the following don't have an auto enable

+    AHB1_ALWAYS                                 = 0x00000001,

+    AHB1_SPIFLASH                               = 0x00000002

+} AHB1_CLKS_T;

+

+#define NB_AHB1_CLK_AEN                         (1)

+#define NB_AHB1_CLK_EN                          (3)

+#define NB_AHB1_CLK                             (3)

+

+// ============================================================================

+// APB1_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// AP APB1 side System clocks

+    APB1_CONF                                   = 0x00000000,

+    APB1_AIF                                    = 0x00000001,

+    APB1_AIF2                                   = 0x00000002,

+    APB1_AUIFC                                  = 0x00000003,

+    APB1_AUIFC_CH0                              = 0x00000004,

+    APB1_AUIFC_CH1                              = 0x00000005,

+    APB1_AUIFC_CH2                              = 0x00000006,

+    APB1_AUIFC_CH3                              = 0x00000007,

+    APB1_I2C1                                   = 0x00000008,

+    APB1_I2C2                                   = 0x00000009,

+    APB1_I2C3                                   = 0x0000000A,

+/// AP APB1 side divided clock (either divided by module or by clock_ctrl)

+    APB1D_OSC                                   = 0x0000000B,

+    APB1D_PWM                                   = 0x0000000C,

+/// the following don't have an auto enable

+    APB1_ALWAYS                                 = 0x0000000D,

+    APB1_DAPLITE                                = 0x0000000E,

+    APB1_TIMER                                  = 0x0000000F,

+    APB1_GPIO                                   = 0x00000010

+} APB1_CLKS_T;

+

+#define NB_APB1_CLK_AEN                         (13)

+#define NB_APB1_CLK_EN                          (17)

+#define NB_APB1_CLK                             (17)

+

+// ============================================================================

+// APB2_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// AP APB2 side System clocks

+    APB2_CONF                                   = 0x00000000,

+    APB2_IFC                                    = 0x00000001,

+    APB2_IFC_CH0                                = 0x00000002,

+    APB2_IFC_CH1                                = 0x00000003,

+    APB2_IFC_CH2                                = 0x00000004,

+    APB2_IFC_CH3                                = 0x00000005,

+    APB2_IFC_CH4                                = 0x00000006,

+    APB2_IFC_CH5                                = 0x00000007,

+    APB2_IFC_CH6                                = 0x00000008,

+    APB2_IFC_CH7                                = 0x00000009,

+    APB2_UART1                                  = 0x0000000A,

+    APB2_UART2                                  = 0x0000000B,

+    APB2_UART3                                  = 0x0000000C,

+    APB2_SPI1                                   = 0x0000000D,

+    APB2_SPI2                                   = 0x0000000E,

+    APB2_SPI3                                   = 0x0000000F,

+    APB2_SDMMC1                                 = 0x00000010,

+    APB2_SDMMC2                                 = 0x00000011,

+    APB2_SDMMC3                                 = 0x00000012,

+/// the following don't have an auto enable

+    APB2_ALWAYS                                 = 0x00000013,

+    APB2_NANDFLASH                              = 0x00000014

+} APB2_CLKS_T;

+

+#define NB_APB2_CLK_AEN                         (19)

+#define NB_APB2_CLK_EN                          (21)

+#define NB_APB2_CLK                             (21)

+

+// ============================================================================

+// MEM_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// AP MEM side System clocks

+    MEM_CONF                                    = 0x00000000,

+/// the following don't have an auto enable

+    MEM_DMC                                     = 0x00000001,

+    MEM_GPU                                     = 0x00000002,

+    MEM_VPU                                     = 0x00000003,

+    MEM_DDRPHY_P                                = 0x00000004,

+    MEM_CONNECT                                 = 0x00000005

+} MEM_CLKS_T;

+

+#define NB_MEM_CLK_AEN                          (1)

+#define NB_MEM_CLK_EN                           (6)

+#define NB_MEM_CLK                              (6)

+

+// ============================================================================

+// APO_CLKS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// AP side Other clocks

+/// clocks with auto enble

+    APOC_VPU                                    = 0x00000000,

+    APOC_BCK                                    = 0x00000001,

+    APOC_BCK2                                   = 0x00000002,

+    APOC_UART1                                  = 0x00000003,

+    APOC_UART2                                  = 0x00000004,

+    APOC_UART3                                  = 0x00000005,

+    APOC_VOC_CORE                               = 0x00000006,

+    APOC_VOC2_CORE                              = 0x00000007,

+    APOC_VOC                                    = 0x00000008,

+    APOC_VOC2                                   = 0x00000009,

+/// the following don't have an auto enable

+    APOC_VOC_ALWAYS                             = 0x0000000A,

+    APOC_VOC2_ALWAYS                            = 0x0000000B,

+    APOC_DDRPHY_N                               = 0x0000000C,

+    APOC_DDRPHY2XP                              = 0x0000000D,

+    APOC_DDRPHY2XN                              = 0x0000000E,

+    APOC_GPU                                    = 0x0000000F,

+    APOC_USBPHY                                 = 0x00000010,

+    APOC_CSI                                    = 0x00000011,

+    APOC_DSI                                    = 0x00000012,

+    APOC_GPIO                                   = 0x00000013,

+    APOC_SPIFLASH                               = 0x00000014,

+    APOC_PIX                                    = 0x00000015,

+    APOC_PDGB                                   = 0x00000016

+} APO_CLKS_T;

+

+#define NB_CLK_VOC_AEN_SYNC                     (6)

+#define NB_CLK_VOC_CORE                         (8)

+#define NB_APO_CLK_AEN                          (10)

+#define NB_CLK_VOC_END                          (12)

+#define NB_APO_CLK_EN                           (23)

+#define NB_APO_CLK                              (23)

+

+// ============================================================================

+// CPU_RESETS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// AP CPU side resets

+    CPU_RST_CORE                                = 0x00000000,

+    CPU_RST_SYS                                 = 0x00000001

+} CPU_RESETS_T;

+

+#define NB_CPU_RST                              (2)

+

+// ============================================================================

+// AXI_RESETS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// AP AXI side resets: AXI and AHB0 and APB0

+    AXI_RST_VOC                                 = 0x00000000,

+    AXI_RST_VOC2                                = 0x00000001,

+    AXI_RST_DMA                                 = 0x00000002,

+    AXI_RST_SYS                                 = 0x00000003,

+    AXI_RST_CONNECT                             = 0x00000004,

+    AHB0_RST_GPU                                = 0x00000005,

+    APB0_RST_VPU                                = 0x00000006,

+    APB0_RST_IRQ                                = 0x00000007

+} AXI_RESETS_T;

+

+#define NB_AXI_RST                              (8)

+

+// ============================================================================

+// AXIDIV2_RESETS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// AP AXIDIV2 side resets

+    AXIDIV2_RST_IMEM                            = 0x00000000,

+    AXIDIV2_RST_SYS                             = 0x00000001,

+    AXIDIV2_RST_VPU                             = 0x00000002

+} AXIDIV2_RESETS_T;

+

+#define NB_AXIDIV2_RST                          (3)

+

+// ============================================================================

+// GCG_RESETS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// AP GCG side resets

+    GCG_RST_SYS                                 = 0x00000000,

+    GCG_RST_GOUDA                               = 0x00000001,

+    GCG_RST_CAMERA                              = 0x00000002

+} GCG_RESETS_T;

+

+#define NB_GCG_RST                              (3)

+

+// ============================================================================

+// AHB1_RESETS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// AP AHB1 side resets

+    AHB1_RST_SYS                                = 0x00000000,

+    AHB1_RST_USBC                               = 0x00000001,

+    AHB1_RST_SPIFLASH                           = 0x00000002

+} AHB1_RESETS_T;

+

+#define NB_AHB1_RST                             (3)

+

+// ============================================================================

+// APB1_RESETS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// AP APB1 side resets

+    APB1_RST_SYS                                = 0x00000000,

+    APB1_RST_TIMER                              = 0x00000001,

+    APB1_RST_KEYPAD                             = 0x00000002,

+    APB1_RST_GPIO                               = 0x00000003,

+    APB1_RST_PWM                                = 0x00000004,

+    APB1_RST_AIF                                = 0x00000005,

+    APB1_RST_AIF2                               = 0x00000006,

+    APB1_RST_AUIFC                              = 0x00000007,

+    APB1_RST_I2C1                               = 0x00000008,

+    APB1_RST_I2C2                               = 0x00000009,

+    APB1_RST_I2C3                               = 0x0000000A,

+    APB1_RST_COM_REGS                           = 0x0000000B,

+    APB1_RST_DMC                                = 0x0000000C,

+    APB1_RST_DDRPHY_P                           = 0x0000000D,

+    APB1_RST_BB2G_XCPU                          = 0x0000000E,

+    APB1_RST_BB2G_BCPU                          = 0x0000000F,

+    APB1_RST_BB2G_AHBC                          = 0x00000010,

+    APB1_RST_BB2G_DMA                           = 0x00000011,

+    APB1_RST_BB2G_A2A                           = 0x00000012,

+    APB1_RST_BB2G_XIFC                          = 0x00000013,

+    APB1_RST_BB2G_BIFC                          = 0x00000014,

+    APB1_RST_BB2G_BAHBC                         = 0x00000015,

+    APB1_RST_BB2G_MEM_BRIDGE                    = 0x00000016

+} APB1_RESETS_T;

+

+#define NB_APB1_RST                             (23)

+

+// ============================================================================

+// APB2_RESETS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// AP APB2 side resets

+    APB2_RST_SYS                                = 0x00000000,

+    APB2_RST_IFC                                = 0x00000001,

+    APB2_RST_UART1                              = 0x00000002,

+    APB2_RST_UART2                              = 0x00000003,

+    APB2_RST_UART3                              = 0x00000004,

+    APB2_RST_SPI1                               = 0x00000005,

+    APB2_RST_SPI2                               = 0x00000006,

+    APB2_RST_SPI3                               = 0x00000007,

+    APB2_RST_SDMMC1                             = 0x00000008,

+    APB2_RST_SDMMC2                             = 0x00000009,

+    APB2_RST_SDMMC3                             = 0x0000000A,

+    APB2_RST_NANDFLASH                          = 0x0000000B

+} APB2_RESETS_T;

+

+#define NB_APB2_RST                             (12)

+

+// ============================================================================

+// MEM_RESETS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// AP MEM side resets

+    MEM_RST_SYS                                 = 0x00000000,

+    MEM_RST_GPU                                 = 0x00000001,

+    MEM_RST_VPU                                 = 0x00000002,

+    MEM_RST_DMC                                 = 0x00000003,

+    MEM_RST_DDRPHY_P                            = 0x00000004

+} MEM_RESETS_T;

+

+#define NB_MEM_RST                              (5)

+

+// ============================================================================

+// AP_OTHERS_RESETS_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef enum

+{

+/// AP Reset Other : resync on corresponding clock other

+    AP_RSTO_VOC                                 = 0x00000000,

+    AP_RSTO_VOC2                                = 0x00000001,

+    AP_RSTO_DDRPHY_N                            = 0x00000002,

+    AP_RSTO_DDRPHY2XP                           = 0x00000003,

+    AP_RSTO_DDRPHY2XN                           = 0x00000004,

+    AP_RSTO_GPU                                 = 0x00000005,

+    AP_RSTO_VPU                                 = 0x00000006,

+    AP_RSTO_BCK                                 = 0x00000007,

+    AP_RSTO_BCK2                                = 0x00000008,

+    AP_RSTO_UART1                               = 0x00000009,

+    AP_RSTO_UART2                               = 0x0000000A,

+    AP_RSTO_UART3                               = 0x0000000B,

+    AP_RSTO_GPIO                                = 0x0000000C,

+    AP_RSTO_TIMER                               = 0x0000000D,

+    AP_RSTO_USBC                                = 0x0000000E,

+    AP_RSTO_DSI                                 = 0x0000000F,

+    AP_RSTO_SPIFLASH                            = 0x00000010,

+    AP_RSTO_TCK                                 = 0x00000011,

+    AP_RSTO_PDBG_XTAL                           = 0x00000012

+} AP_OTHERS_RESETS_T;

+

+#define NB_AP_RSTO                              (19)

+/// For REG_DBG protect lock/unlock value

+#define AP_CTRL_PROTECT_LOCK                    (0XA50000)

+#define AP_CTRL_PROTECT_UNLOCK                  (0XA50001)

+

+// =============================================================================

+//  TYPES

+// =============================================================================

+

+// ============================================================================

+// SYS_CTRL_AP_T

+// -----------------------------------------------------------------------------

+/// 

+// =============================================================================

+typedef volatile struct

+{

+    /// <strong>This register is used to Lock and Unlock the protected registers.</strong>

+    REG32                          REG_DBG;                      //0x00000000

+    /// Register protected by Write_Unlocked_H.

+    REG32                          Cfg_Pll_Ctrl[4];              //0x00000004

+    /// This register is protected.

+    REG32                          Sel_Clock;                    //0x00000014

+    REG32                          Reset_Cause;                  //0x00000018

+    /// This register is protected.

+    REG32                          CPU_Rst_Set;                  //0x0000001C

+    REG32                          CPU_Rst_Clr;                  //0x00000020

+    /// This register is protected.

+    REG32                          AXI_Rst_Set;                  //0x00000024

+    REG32                          AXI_Rst_Clr;                  //0x00000028

+    /// This register is protected.

+    REG32                          AXIDIV2_Rst_Set;              //0x0000002C

+    REG32                          AXIDIV2_Rst_Clr;              //0x00000030

+    /// This register is protected.

+    REG32                          GCG_Rst_Set;                  //0x00000034

+    REG32                          GCG_Rst_Clr;                  //0x00000038

+    /// This register is protected.

+    REG32                          AHB1_Rst_Set;                 //0x0000003C

+    REG32                          AHB1_Rst_Clr;                 //0x00000040

+    /// This register is protected.

+    REG32                          APB1_Rst_Set;                 //0x00000044

+    REG32                          APB1_Rst_Clr;                 //0x00000048

+    /// This register is protected.

+    REG32                          APB2_Rst_Set;                 //0x0000004C

+    REG32                          APB2_Rst_Clr;                 //0x00000050

+    /// This register is protected.

+    REG32                          MEM_Rst_Set;                  //0x00000054

+    REG32                          MEM_Rst_Clr;                  //0x00000058

+    REG32                          Clk_CPU_Mode;                 //0x0000005C

+    REG32                          Clk_CPU_Enable;               //0x00000060

+    /// This register is protected.

+    REG32                          Clk_CPU_Disable;              //0x00000064

+    REG32                          Clk_AXI_Mode;                 //0x00000068

+    REG32                          Clk_AXI_Enable;               //0x0000006C

+    /// This register is protected.

+    REG32                          Clk_AXI_Disable;              //0x00000070

+    REG32                          Clk_AXIDIV2_Mode;             //0x00000074

+    REG32                          Clk_AXIDIV2_Enable;           //0x00000078

+    /// This register is protected.

+    REG32                          Clk_AXIDIV2_Disable;          //0x0000007C

+    REG32                          Clk_GCG_Mode;                 //0x00000080

+    REG32                          Clk_GCG_Enable;               //0x00000084

+    /// This register is protected.

+    REG32                          Clk_GCG_Disable;              //0x00000088

+    REG32                          Clk_AHB1_Mode;                //0x0000008C

+    REG32                          Clk_AHB1_Enable;              //0x00000090

+    /// This register is protected.

+    REG32                          Clk_AHB1_Disable;             //0x00000094

+    REG32                          Clk_APB1_Mode;                //0x00000098

+    REG32                          Clk_APB1_Enable;              //0x0000009C

+    /// This register is protected.

+    REG32                          Clk_APB1_Disable;             //0x000000A0

+    REG32                          Clk_APB2_Mode;                //0x000000A4

+    REG32                          Clk_APB2_Enable;              //0x000000A8

+    /// This register is protected.

+    REG32                          Clk_APB2_Disable;             //0x000000AC

+    REG32                          Clk_MEM_Mode;                 //0x000000B0

+    REG32                          Clk_MEM_Enable;               //0x000000B4

+    /// This register is protected.

+    REG32                          Clk_MEM_Disable;              //0x000000B8

+    REG32                          Clk_APO_Mode;                 //0x000000BC

+    REG32                          Clk_APO_Enable;               //0x000000C0

+    /// This register is protected.

+    REG32                          Clk_APO_Disable;              //0x000000C4

+    REG32                          Cfg_Clk_AP_CPU;               //0x000000C8

+    REG32                          Cfg_Clk_AP_AXI;               //0x000000CC

+    REG32                          Cfg_Clk_AP_GCG;               //0x000000D0

+    REG32                          Cfg_Clk_AP_AHB1;              //0x000000D4

+    REG32                          Cfg_Clk_AP_APB1;              //0x000000D8

+    REG32                          Cfg_Clk_AP_APB2;              //0x000000DC

+    REG32                          Cfg_Clk_AP_MEM;               //0x000000E0

+    REG32                          Cfg_Clk_AP_GPU;               //0x000000E4

+    REG32                          Cfg_Clk_AP_VPU;               //0x000000E8

+    REG32                          Cfg_Clk_AP_VOC;               //0x000000EC

+    REG32                          Cfg_Clk_AP_SFLSH;             //0x000000F0

+    REG32                          Cfg_Clk_Uart[3];              //0x000000F4

+    REG32                          L2cc_Ctrl;                    //0x00000100

+    REG32                          Spi_Ctrl;                     //0x00000104

+    REG32                          Memory_Margin;                //0x00000108

+    REG32                          Memory_Margin2;               //0x0000010C

+    REG32                          Memory_Observe;               //0x00000110

+    REG32                          Cfg_Clk_AP_VOC2;              //0x00000114

+    REG32 Reserved_00000118[57];                //0x00000118

+    /// This register is reserved.

+    REG32                          Cfg_Reserve;                  //0x000001FC

+} HWP_SYS_CTRL_AP_T;

+

+#define hwp_sysCtrlAp              ((HWP_SYS_CTRL_AP_T*)(RDA_SYSCTRL_BASE))

+

+

+//REG_DBG

+#define SYS_CTRL_AP_SCRATCH(n)     (((n)&0xFFFF)<<0)

+#define SYS_CTRL_AP_WRITE_UNLOCK_STATUS (1<<30)

+#define SYS_CTRL_AP_WRITE_UNLOCK   (1<<31)

+

+//Cfg_Pll_Ctrl

+#define SYS_CTRL_AP_AP_PLL_ENABLE  (1<<0)

+#define SYS_CTRL_AP_AP_PLL_ENABLE_MASK (1<<0)

+#define SYS_CTRL_AP_AP_PLL_ENABLE_SHIFT (0)

+#define SYS_CTRL_AP_AP_PLL_ENABLE_POWER_DOWN (0<<0)

+#define SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE (1<<0)

+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET (1<<4)

+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_MASK (1<<4)

+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_SHIFT (4)

+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_RESET (0<<4)

+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET (1<<4)

+#define SYS_CTRL_AP_AP_PLL_BYPASS  (1<<8)

+#define SYS_CTRL_AP_AP_PLL_BYPASS_MASK (1<<8)

+#define SYS_CTRL_AP_AP_PLL_BYPASS_SHIFT (8)

+#define SYS_CTRL_AP_AP_PLL_BYPASS_PASS (0<<8)

+#define SYS_CTRL_AP_AP_PLL_BYPASS_BYPASS (1<<8)

+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE (1<<12)

+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_MASK (1<<12)

+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_SHIFT (12)

+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_ENABLE (1<<12)

+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_DISABLE (0<<12)

+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(n) (((n)&31)<<16)

+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW_MASK (31<<16)

+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW_SHIFT (16)

+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(n) (((n)&31)<<24)

+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH_MASK (31<<24)

+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH_SHIFT (24)

+#define SYS_CTRL_AP_PLL_AP_CFG(n)  (((n)&0x1F1F1111)<<0)

+#define SYS_CTRL_AP_PLL_AP_CFG_MASK (0x1F1F1111<<0)

+#define SYS_CTRL_AP_PLL_AP_CFG_SHIFT (0)

+

+//Sel_Clock

+#define SYS_CTRL_AP_SLOW_SEL_RF_OSCILLATOR (1<<0)

+#define SYS_CTRL_AP_SLOW_SEL_RF_RF (0<<0)

+#define SYS_CTRL_AP_CPU_SEL_FAST_SLOW (1<<4)

+#define SYS_CTRL_AP_CPU_SEL_FAST_FAST (0<<4)

+#define SYS_CTRL_AP_BUS_SEL_FAST_SLOW (1<<5)

+#define SYS_CTRL_AP_BUS_SEL_FAST_FAST (0<<5)

+#define SYS_CTRL_AP_TIMER_SEL_FAST_SLOW (1<<7)

+#define SYS_CTRL_AP_TIMER_SEL_FAST_FAST (0<<7)

+#define SYS_CTRL_AP_RF_DETECTED_OK (1<<8)

+#define SYS_CTRL_AP_RF_DETECTED_NO (0<<8)

+#define SYS_CTRL_AP_RF_DETECT_BYPASS (1<<9)

+#define SYS_CTRL_AP_RF_DETECT_RESET (1<<10)

+#define SYS_CTRL_AP_RF_SELECTED_L  (1<<11)

+#define SYS_CTRL_AP_PLL_LOCKED_CPU (1<<12)

+#define SYS_CTRL_AP_PLL_LOCKED_CPU_MASK (1<<12)

+#define SYS_CTRL_AP_PLL_LOCKED_CPU_SHIFT (12)

+#define SYS_CTRL_AP_PLL_LOCKED_CPU_LOCKED (1<<12)

+#define SYS_CTRL_AP_PLL_LOCKED_CPU_NOT_LOCKED (0<<12)

+#define SYS_CTRL_AP_PLL_LOCKED_BUS (1<<13)

+#define SYS_CTRL_AP_PLL_LOCKED_BUS_MASK (1<<13)

+#define SYS_CTRL_AP_PLL_LOCKED_BUS_SHIFT (13)

+#define SYS_CTRL_AP_PLL_LOCKED_BUS_LOCKED (1<<13)

+#define SYS_CTRL_AP_PLL_LOCKED_BUS_NOT_LOCKED (0<<13)

+#define SYS_CTRL_AP_PLL_LOCKED_MEM (1<<14)

+#define SYS_CTRL_AP_PLL_LOCKED_MEM_MASK (1<<14)

+#define SYS_CTRL_AP_PLL_LOCKED_MEM_SHIFT (14)

+#define SYS_CTRL_AP_PLL_LOCKED_MEM_LOCKED (1<<14)

+#define SYS_CTRL_AP_PLL_LOCKED_MEM_NOT_LOCKED (0<<14)

+#define SYS_CTRL_AP_PLL_LOCKED_USB (1<<15)

+#define SYS_CTRL_AP_PLL_LOCKED_USB_MASK (1<<15)

+#define SYS_CTRL_AP_PLL_LOCKED_USB_SHIFT (15)

+#define SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED (1<<15)

+#define SYS_CTRL_AP_PLL_LOCKED_USB_NOT_LOCKED (0<<15)

+#define SYS_CTRL_AP_PLL_BYPASS_LOCK_CPU (1<<20)

+#define SYS_CTRL_AP_PLL_BYPASS_LOCK_BUS (1<<21)

+#define SYS_CTRL_AP_FAST_SELECTED_CPU_L (1<<30)

+#define SYS_CTRL_AP_FAST_SELECTED_CPU_L_MASK (1<<30)

+#define SYS_CTRL_AP_FAST_SELECTED_CPU_L_SHIFT (30)

+#define SYS_CTRL_AP_FAST_SELECTED_BUS_L (1<<31)

+#define SYS_CTRL_AP_FAST_SELECTED_BUS_L_MASK (1<<31)

+#define SYS_CTRL_AP_FAST_SELECTED_BUS_L_SHIFT (31)

+

+//Reset_Cause

+#define SYS_CTRL_AP_WATCHDOG_RESET_HAPPENED (1<<0)

+#define SYS_CTRL_AP_WATCHDOG_RESET_NO (0<<0)

+#define SYS_CTRL_AP_GLOBALSOFT_RESET_HAPPENED (1<<4)

+#define SYS_CTRL_AP_GLOBALSOFT_RESET_NO (0<<4)

+#define SYS_CTRL_AP_HOSTDEBUG_RESET_HAPPENED (1<<5)

+#define SYS_CTRL_AP_HOSTDEBUG_RESET_NO (0<<5)

+#define SYS_CTRL_AP_ALARMCAUSE_HAPPENED (1<<6)

+#define SYS_CTRL_AP_ALARMCAUSE_NO  (0<<6)

+#define SYS_CTRL_AP_BOOT_MODE(n)   (((n)&0xFFFF)<<8)

+#define SYS_CTRL_AP_BOOT_MODE_MASK (0xFFFF<<8)

+#define SYS_CTRL_AP_BOOT_MODE_SHIFT (8)

+#define SYS_CTRL_AP_SW_BOOT_MODE(n) (((n)&0x7F)<<24)

+#define SYS_CTRL_AP_SW_BOOT_MODE_MASK (0x7F<<24)

+#define SYS_CTRL_AP_SW_BOOT_MODE_SHIFT (24)

+#define SYS_CTRL_AP_FONCTIONAL_TEST_MODE (1<<31)

+

+//CPU_Rst_Set

+#define SYS_CTRL_AP_SET_CPU_RST_CORE (1<<0)

+#define SYS_CTRL_AP_SET_CPU_RST_SYS (1<<1)

+#define SYS_CTRL_AP_SOFT_RST       (1<<31)

+#define SYS_CTRL_AP_SET_CPU_RST(n) (((n)&3)<<0)

+#define SYS_CTRL_AP_SET_CPU_RST_MASK (3<<0)

+#define SYS_CTRL_AP_SET_CPU_RST_SHIFT (0)

+

+//CPU_Rst_Clr

+#define SYS_CTRL_AP_CLR_CPU_RST_CORE (1<<0)

+#define SYS_CTRL_AP_CLR_CPU_RST_SYS (1<<1)

+#define SYS_CTRL_AP_CLR_CPU_RST(n) (((n)&3)<<0)

+#define SYS_CTRL_AP_CLR_CPU_RST_MASK (3<<0)

+#define SYS_CTRL_AP_CLR_CPU_RST_SHIFT (0)

+

+//AXI_Rst_Set

+#define SYS_CTRL_AP_SET_AXI_RST_VOC (1<<0)

+#define SYS_CTRL_AP_SET_AXI_RST_VOC2 (1<<1)

+#define SYS_CTRL_AP_SET_AXI_RST_DMA (1<<2)

+#define SYS_CTRL_AP_SET_AXI_RST_SYS (1<<3)

+#define SYS_CTRL_AP_SET_AXI_RST_CONNECT (1<<4)

+#define SYS_CTRL_AP_SET_AHB0_RST_GPU (1<<5)

+#define SYS_CTRL_AP_SET_APB0_RST_VPU (1<<6)

+#define SYS_CTRL_AP_SET_APB0_RST_IRQ (1<<7)

+#define SYS_CTRL_AP_SET_AXI_RST(n) (((n)&0xFF)<<0)

+#define SYS_CTRL_AP_SET_AXI_RST_MASK (0xFF<<0)

+#define SYS_CTRL_AP_SET_AXI_RST_SHIFT (0)

+

+//AXI_Rst_Clr

+#define SYS_CTRL_AP_CLR_AXI_RST_VOC (1<<0)

+#define SYS_CTRL_AP_CLR_AXI_RST_VOC2 (1<<1)

+#define SYS_CTRL_AP_CLR_AXI_RST_DMA (1<<2)

+#define SYS_CTRL_AP_CLR_AXI_RST_SYS (1<<3)

+#define SYS_CTRL_AP_CLR_AXI_RST_CONNECT (1<<4)

+#define SYS_CTRL_AP_CLR_AHB0_RST_GPU (1<<5)

+#define SYS_CTRL_AP_CLR_APB0_RST_VPU (1<<6)

+#define SYS_CTRL_AP_CLR_APB0_RST_IRQ (1<<7)

+#define SYS_CTRL_AP_CLR_AXI_RST(n) (((n)&0xFF)<<0)

+#define SYS_CTRL_AP_CLR_AXI_RST_MASK (0xFF<<0)

+#define SYS_CTRL_AP_CLR_AXI_RST_SHIFT (0)

+

+//AXIDIV2_Rst_Set

+#define SYS_CTRL_AP_SET_AXIDIV2_RST_IMEM (1<<0)

+#define SYS_CTRL_AP_SET_AXIDIV2_RST_SYS (1<<1)

+#define SYS_CTRL_AP_SET_AXIDIV2_RST_VPU (1<<2)

+#define SYS_CTRL_AP_SET_AXIDIV2_RST(n) (((n)&7)<<0)

+#define SYS_CTRL_AP_SET_AXIDIV2_RST_MASK (7<<0)

+#define SYS_CTRL_AP_SET_AXIDIV2_RST_SHIFT (0)

+

+//AXIDIV2_Rst_Clr

+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_IMEM (1<<0)

+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_SYS (1<<1)

+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_VPU (1<<2)

+#define SYS_CTRL_AP_CLR_AXIDIV2_RST(n) (((n)&7)<<0)

+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_MASK (7<<0)

+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_SHIFT (0)

+

+//GCG_Rst_Set

+#define SYS_CTRL_AP_SET_GCG_RST_SYS (1<<0)

+#define SYS_CTRL_AP_SET_GCG_RST_GOUDA (1<<1)

+#define SYS_CTRL_AP_SET_GCG_RST_CAMERA (1<<2)

+#define SYS_CTRL_AP_SET_GCG_RST(n) (((n)&7)<<0)

+#define SYS_CTRL_AP_SET_GCG_RST_MASK (7<<0)

+#define SYS_CTRL_AP_SET_GCG_RST_SHIFT (0)

+

+//GCG_Rst_Clr

+#define SYS_CTRL_AP_CLR_GCG_RST_SYS (1<<0)

+#define SYS_CTRL_AP_CLR_GCG_RST_GOUDA (1<<1)

+#define SYS_CTRL_AP_CLR_GCG_RST_CAMERA (1<<2)

+#define SYS_CTRL_AP_CLR_GCG_RST(n) (((n)&7)<<0)

+#define SYS_CTRL_AP_CLR_GCG_RST_MASK (7<<0)

+#define SYS_CTRL_AP_CLR_GCG_RST_SHIFT (0)

+

+//AHB1_Rst_Set

+#define SYS_CTRL_AP_SET_AHB1_RST_SYS (1<<0)

+#define SYS_CTRL_AP_SET_AHB1_RST_USBC (1<<1)

+#define SYS_CTRL_AP_SET_AHB1_RST_SPIFLASH (1<<2)

+#define SYS_CTRL_AP_SET_AHB1_RST(n) (((n)&7)<<0)

+#define SYS_CTRL_AP_SET_AHB1_RST_MASK (7<<0)

+#define SYS_CTRL_AP_SET_AHB1_RST_SHIFT (0)

+

+//AHB1_Rst_Clr

+#define SYS_CTRL_AP_CLR_AHB1_RST_SYS (1<<0)

+#define SYS_CTRL_AP_CLR_AHB1_RST_USBC (1<<1)

+#define SYS_CTRL_AP_CLR_AHB1_RST_SPIFLASH (1<<2)

+#define SYS_CTRL_AP_CLR_AHB1_RST(n) (((n)&7)<<0)

+#define SYS_CTRL_AP_CLR_AHB1_RST_MASK (7<<0)

+#define SYS_CTRL_AP_CLR_AHB1_RST_SHIFT (0)

+

+//APB1_Rst_Set

+#define SYS_CTRL_AP_SET_APB1_RST_SYS (1<<0)

+#define SYS_CTRL_AP_SET_APB1_RST_TIMER (1<<1)

+#define SYS_CTRL_AP_SET_APB1_RST_KEYPAD (1<<2)

+#define SYS_CTRL_AP_SET_APB1_RST_GPIO (1<<3)

+#define SYS_CTRL_AP_SET_APB1_RST_PWM (1<<4)

+#define SYS_CTRL_AP_SET_APB1_RST_AIF (1<<5)

+#define SYS_CTRL_AP_SET_APB1_RST_AIF2 (1<<6)

+#define SYS_CTRL_AP_SET_APB1_RST_AUIFC (1<<7)

+#define SYS_CTRL_AP_SET_APB1_RST_I2C1 (1<<8)

+#define SYS_CTRL_AP_SET_APB1_RST_I2C2 (1<<9)

+#define SYS_CTRL_AP_SET_APB1_RST_I2C3 (1<<10)

+#define SYS_CTRL_AP_SET_APB1_RST_COM_REGS (1<<11)

+#define SYS_CTRL_AP_SET_APB1_RST_DMC (1<<12)

+#define SYS_CTRL_AP_SET_APB1_RST_DDRPHY_P (1<<13)

+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_XCPU (1<<14)

+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BCPU (1<<15)

+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_AHBC (1<<16)

+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_DMA (1<<17)

+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_A2A (1<<18)

+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_XIFC (1<<19)

+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BIFC (1<<20)

+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BAHBC (1<<21)

+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_MEM_BRIDGE (1<<22)

+#define SYS_CTRL_AP_SET_APB1_RST(n) (((n)&0x7FFFFF)<<0)

+#define SYS_CTRL_AP_SET_APB1_RST_MASK (0x7FFFFF<<0)

+#define SYS_CTRL_AP_SET_APB1_RST_SHIFT (0)

+

+//APB1_Rst_Clr

+#define SYS_CTRL_AP_CLR_APB1_RST_SYS (1<<0)

+#define SYS_CTRL_AP_CLR_APB1_RST_TIMER (1<<1)

+#define SYS_CTRL_AP_CLR_APB1_RST_KEYPAD (1<<2)

+#define SYS_CTRL_AP_CLR_APB1_RST_GPIO (1<<3)

+#define SYS_CTRL_AP_CLR_APB1_RST_PWM (1<<4)

+#define SYS_CTRL_AP_CLR_APB1_RST_AIF (1<<5)

+#define SYS_CTRL_AP_CLR_APB1_RST_AIF2 (1<<6)

+#define SYS_CTRL_AP_CLR_APB1_RST_AUIFC (1<<7)

+#define SYS_CTRL_AP_CLR_APB1_RST_I2C1 (1<<8)

+#define SYS_CTRL_AP_CLR_APB1_RST_I2C2 (1<<9)

+#define SYS_CTRL_AP_CLR_APB1_RST_I2C3 (1<<10)

+#define SYS_CTRL_AP_CLR_APB1_RST_COM_REGS (1<<11)

+#define SYS_CTRL_AP_CLR_APB1_RST_DMC (1<<12)

+#define SYS_CTRL_AP_CLR_APB1_RST_DDRPHY_P (1<<13)

+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_XCPU (1<<14)

+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BCPU (1<<15)

+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_AHBC (1<<16)

+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_DMA (1<<17)

+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_A2A (1<<18)

+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_XIFC (1<<19)

+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BIFC (1<<20)

+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BAHBC (1<<21)

+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_MEM_BRIDGE (1<<22)

+#define SYS_CTRL_AP_CLR_APB1_RST(n) (((n)&0x7FFFFF)<<0)

+#define SYS_CTRL_AP_CLR_APB1_RST_MASK (0x7FFFFF<<0)

+#define SYS_CTRL_AP_CLR_APB1_RST_SHIFT (0)

+

+//APB2_Rst_Set

+#define SYS_CTRL_AP_SET_APB2_RST_SYS (1<<0)

+#define SYS_CTRL_AP_SET_APB2_RST_IFC (1<<1)

+#define SYS_CTRL_AP_SET_APB2_RST_UART1 (1<<2)

+#define SYS_CTRL_AP_SET_APB2_RST_UART2 (1<<3)

+#define SYS_CTRL_AP_SET_APB2_RST_UART3 (1<<4)

+#define SYS_CTRL_AP_SET_APB2_RST_SPI1 (1<<5)

+#define SYS_CTRL_AP_SET_APB2_RST_SPI2 (1<<6)

+#define SYS_CTRL_AP_SET_APB2_RST_SPI3 (1<<7)

+#define SYS_CTRL_AP_SET_APB2_RST_SDMMC1 (1<<8)

+#define SYS_CTRL_AP_SET_APB2_RST_SDMMC2 (1<<9)

+#define SYS_CTRL_AP_SET_APB2_RST_SDMMC3 (1<<10)

+#define SYS_CTRL_AP_SET_APB2_RST_NANDFLASH (1<<11)

+#define SYS_CTRL_AP_SET_APB2_RST(n) (((n)&0xFFF)<<0)

+#define SYS_CTRL_AP_SET_APB2_RST_MASK (0xFFF<<0)

+#define SYS_CTRL_AP_SET_APB2_RST_SHIFT (0)

+

+//APB2_Rst_Clr

+#define SYS_CTRL_AP_CLR_APB2_RST_SYS (1<<0)

+#define SYS_CTRL_AP_CLR_APB2_RST_IFC (1<<1)

+#define SYS_CTRL_AP_CLR_APB2_RST_UART1 (1<<2)

+#define SYS_CTRL_AP_CLR_APB2_RST_UART2 (1<<3)

+#define SYS_CTRL_AP_CLR_APB2_RST_UART3 (1<<4)

+#define SYS_CTRL_AP_CLR_APB2_RST_SPI1 (1<<5)

+#define SYS_CTRL_AP_CLR_APB2_RST_SPI2 (1<<6)

+#define SYS_CTRL_AP_CLR_APB2_RST_SPI3 (1<<7)

+#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC1 (1<<8)

+#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC2 (1<<9)

+#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC3 (1<<10)

+#define SYS_CTRL_AP_CLR_APB2_RST_NANDFLASH (1<<11)

+#define SYS_CTRL_AP_CLR_APB2_RST(n) (((n)&0xFFF)<<0)

+#define SYS_CTRL_AP_CLR_APB2_RST_MASK (0xFFF<<0)

+#define SYS_CTRL_AP_CLR_APB2_RST_SHIFT (0)

+

+//MEM_Rst_Set

+#define SYS_CTRL_AP_SET_MEM_RST_SYS (1<<0)

+#define SYS_CTRL_AP_SET_MEM_RST_GPU (1<<1)

+#define SYS_CTRL_AP_SET_MEM_RST_VPU (1<<2)

+#define SYS_CTRL_AP_SET_MEM_RST_DMC (1<<3)

+#define SYS_CTRL_AP_SET_MEM_RST_DDRPHY_P (1<<4)

+#define SYS_CTRL_AP_SET_MEM_RST(n) (((n)&31)<<0)

+#define SYS_CTRL_AP_SET_MEM_RST_MASK (31<<0)

+#define SYS_CTRL_AP_SET_MEM_RST_SHIFT (0)

+

+//MEM_Rst_Clr

+#define SYS_CTRL_AP_CLR_MEM_RST_SYS (1<<0)

+#define SYS_CTRL_AP_CLR_MEM_RST_GPU (1<<1)

+#define SYS_CTRL_AP_CLR_MEM_RST_VPU (1<<2)

+#define SYS_CTRL_AP_CLR_MEM_RST_DMC (1<<3)

+#define SYS_CTRL_AP_CLR_MEM_RST_DDRPHY_P (1<<4)

+#define SYS_CTRL_AP_CLR_MEM_RST(n) (((n)&31)<<0)

+#define SYS_CTRL_AP_CLR_MEM_RST_MASK (31<<0)

+#define SYS_CTRL_AP_CLR_MEM_RST_SHIFT (0)

+

+//Clk_CPU_Mode

+#define SYS_CTRL_AP_MODE_CLK_CPU_AUTOMATIC (0<<0)

+#define SYS_CTRL_AP_MODE_CLK_CPU_MANUAL (1<<0)

+

+//Clk_CPU_Enable

+#define SYS_CTRL_AP_ENABLE_CPU_CORE (1<<0)

+#define SYS_CTRL_AP_ENABLE_CPU_DUMMY (1<<1)

+#define SYS_CTRL_AP_ENABLE_CLK_CPU(n) (((n)&3)<<0)

+#define SYS_CTRL_AP_ENABLE_CLK_CPU_MASK (3<<0)

+#define SYS_CTRL_AP_ENABLE_CLK_CPU_SHIFT (0)

+

+//Clk_CPU_Disable

+#define SYS_CTRL_AP_DISABLE_CPU_CORE (1<<0)

+#define SYS_CTRL_AP_DISABLE_CPU_DUMMY (1<<1)

+#define SYS_CTRL_AP_DISABLE_CLK_CPU(n) (((n)&3)<<0)

+#define SYS_CTRL_AP_DISABLE_CLK_CPU_MASK (3<<0)

+#define SYS_CTRL_AP_DISABLE_CLK_CPU_SHIFT (0)

+

+//Clk_AXI_Mode

+#define SYS_CTRL_AP_MODE_AHB0_CONF_AUTOMATIC (0<<0)

+#define SYS_CTRL_AP_MODE_AHB0_CONF_MANUAL (1<<0)

+#define SYS_CTRL_AP_MODE_APB0_CONF_AUTOMATIC (0<<1)

+#define SYS_CTRL_AP_MODE_APB0_CONF_MANUAL (1<<1)

+#define SYS_CTRL_AP_MODE_AXI_VOC_AUTOMATIC (0<<2)

+#define SYS_CTRL_AP_MODE_AXI_VOC_MANUAL (1<<2)

+#define SYS_CTRL_AP_MODE_AXI_VOC2_AUTOMATIC (0<<3)

+#define SYS_CTRL_AP_MODE_AXI_VOC2_MANUAL (1<<3)

+#define SYS_CTRL_AP_MODE_AXI_DMA_AUTOMATIC (0<<4)

+#define SYS_CTRL_AP_MODE_AXI_DMA_MANUAL (1<<4)

+#define SYS_CTRL_AP_MODE_CLK_AXI(n) (((n)&31)<<0)

+#define SYS_CTRL_AP_MODE_CLK_AXI_MASK (31<<0)

+#define SYS_CTRL_AP_MODE_CLK_AXI_SHIFT (0)

+

+//Clk_AXI_Enable

+#define SYS_CTRL_AP_ENABLE_AHB0_CONF (1<<0)

+#define SYS_CTRL_AP_ENABLE_APB0_CONF (1<<1)

+#define SYS_CTRL_AP_ENABLE_AXI_VOC (1<<2)

+#define SYS_CTRL_AP_ENABLE_AXI_VOC2 (1<<3)

+#define SYS_CTRL_AP_ENABLE_AXI_DMA (1<<4)

+#define SYS_CTRL_AP_ENABLE_AXI_ALWAYS (1<<5)

+#define SYS_CTRL_AP_ENABLE_AXI_CONNECT (1<<6)

+#define SYS_CTRL_AP_ENABLE_APB0_IRQ (1<<7)

+#define SYS_CTRL_AP_ENABLE_CLK_AXI(n) (((n)&0xFF)<<0)

+#define SYS_CTRL_AP_ENABLE_CLK_AXI_MASK (0xFF<<0)

+#define SYS_CTRL_AP_ENABLE_CLK_AXI_SHIFT (0)

+

+//Clk_AXI_Disable

+#define SYS_CTRL_AP_DISABLE_AHB0_CONF (1<<0)

+#define SYS_CTRL_AP_DISABLE_APB0_CONF (1<<1)

+#define SYS_CTRL_AP_DISABLE_AXI_VOC (1<<2)

+#define SYS_CTRL_AP_DISABLE_AXI_VOC2 (1<<3)

+#define SYS_CTRL_AP_DISABLE_AXI_DMA (1<<4)

+#define SYS_CTRL_AP_DISABLE_AXI_ALWAYS (1<<5)

+#define SYS_CTRL_AP_DISABLE_AXI_CONNECT (1<<6)

+#define SYS_CTRL_AP_DISABLE_APB0_IRQ (1<<7)

+#define SYS_CTRL_AP_DISABLE_CLK_AXI(n) (((n)&0xFF)<<0)

+#define SYS_CTRL_AP_DISABLE_CLK_AXI_MASK (0xFF<<0)

+#define SYS_CTRL_AP_DISABLE_CLK_AXI_SHIFT (0)

+

+//Clk_AXIDIV2_Mode

+#define SYS_CTRL_AP_MODE_CLK_AXIDIV2_AUTOMATIC (0<<0)

+#define SYS_CTRL_AP_MODE_CLK_AXIDIV2_MANUAL (1<<0)

+

+//Clk_AXIDIV2_Enable

+#define SYS_CTRL_AP_ENABLE_AXIDIV2_IMEM (1<<0)

+#define SYS_CTRL_AP_ENABLE_AXIDIV2_ALWAYS (1<<1)

+#define SYS_CTRL_AP_ENABLE_AXIDIV2_CONNECT (1<<2)

+#define SYS_CTRL_AP_ENABLE_AXIDIV2_VPU (1<<3)

+#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2(n) (((n)&15)<<0)

+#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2_MASK (15<<0)

+#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2_SHIFT (0)

+

+//Clk_AXIDIV2_Disable

+#define SYS_CTRL_AP_DISABLE_AXIDIV2_IMEM (1<<0)

+#define SYS_CTRL_AP_DISABLE_AXIDIV2_ALWAYS (1<<1)

+#define SYS_CTRL_AP_DISABLE_AXIDIV2_CONNECT (1<<2)

+#define SYS_CTRL_AP_DISABLE_AXIDIV2_VPU (1<<3)

+#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2(n) (((n)&15)<<0)

+#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2_MASK (15<<0)

+#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2_SHIFT (0)

+

+//Clk_GCG_Mode

+#define SYS_CTRL_AP_MODE_GCG_APB_CONF_AUTOMATIC (0<<0)

+#define SYS_CTRL_AP_MODE_GCG_APB_CONF_MANUAL (1<<0)

+#define SYS_CTRL_AP_MODE_GCG_GOUDA_AUTOMATIC (0<<1)

+#define SYS_CTRL_AP_MODE_GCG_GOUDA_MANUAL (1<<1)

+#define SYS_CTRL_AP_MODE_GCG_CAMERA_AUTOMATIC (0<<2)

+#define SYS_CTRL_AP_MODE_GCG_CAMERA_MANUAL (1<<2)

+#define SYS_CTRL_AP_MODE_CLK_GCG(n) (((n)&7)<<0)

+#define SYS_CTRL_AP_MODE_CLK_GCG_MASK (7<<0)

+#define SYS_CTRL_AP_MODE_CLK_GCG_SHIFT (0)

+

+//Clk_GCG_Enable

+#define SYS_CTRL_AP_ENABLE_GCG_APB_CONF (1<<0)

+#define SYS_CTRL_AP_ENABLE_GCG_GOUDA (1<<1)

+#define SYS_CTRL_AP_ENABLE_GCG_CAMERA (1<<2)

+#define SYS_CTRL_AP_ENABLE_GCG_ALWAYS (1<<3)

+#define SYS_CTRL_AP_ENABLE_GCG_CONNECT (1<<4)

+#define SYS_CTRL_AP_ENABLE_CLK_GCG(n) (((n)&31)<<0)

+#define SYS_CTRL_AP_ENABLE_CLK_GCG_MASK (31<<0)

+#define SYS_CTRL_AP_ENABLE_CLK_GCG_SHIFT (0)

+

+//Clk_GCG_Disable

+#define SYS_CTRL_AP_DISABLE_GCG_APB_CONF (1<<0)

+#define SYS_CTRL_AP_DISABLE_GCG_GOUDA (1<<1)

+#define SYS_CTRL_AP_DISABLE_GCG_CAMERA (1<<2)

+#define SYS_CTRL_AP_DISABLE_GCG_ALWAYS (1<<3)

+#define SYS_CTRL_AP_DISABLE_GCG_CONNECT (1<<4)

+#define SYS_CTRL_AP_DISABLE_CLK_GCG(n) (((n)&31)<<0)

+#define SYS_CTRL_AP_DISABLE_CLK_GCG_MASK (31<<0)

+#define SYS_CTRL_AP_DISABLE_CLK_GCG_SHIFT (0)

+

+//Clk_AHB1_Mode

+#define SYS_CTRL_AP_MODE_CLK_AHB1_AUTOMATIC (0<<0)

+#define SYS_CTRL_AP_MODE_CLK_AHB1_MANUAL (1<<0)

+

+//Clk_AHB1_Enable

+#define SYS_CTRL_AP_ENABLE_AHB1_USBC (1<<0)

+#define SYS_CTRL_AP_ENABLE_AHB1_ALWAYS (1<<1)

+#define SYS_CTRL_AP_ENABLE_AHB1_SPIFLASH (1<<2)

+#define SYS_CTRL_AP_ENABLE_CLK_AHB1(n) (((n)&7)<<0)

+#define SYS_CTRL_AP_ENABLE_CLK_AHB1_MASK (7<<0)

+#define SYS_CTRL_AP_ENABLE_CLK_AHB1_SHIFT (0)

+

+//Clk_AHB1_Disable

+#define SYS_CTRL_AP_DISABLE_AHB1_USBC (1<<0)

+#define SYS_CTRL_AP_DISABLE_AHB1_ALWAYS (1<<1)

+#define SYS_CTRL_AP_DISABLE_AHB1_SPIFLASH (1<<2)

+#define SYS_CTRL_AP_DISABLE_CLK_AHB1(n) (((n)&7)<<0)

+#define SYS_CTRL_AP_DISABLE_CLK_AHB1_MASK (7<<0)

+#define SYS_CTRL_AP_DISABLE_CLK_AHB1_SHIFT (0)

+

+//Clk_APB1_Mode

+#define SYS_CTRL_AP_MODE_APB1_CONF_AUTOMATIC (0<<0)

+#define SYS_CTRL_AP_MODE_APB1_CONF_MANUAL (1<<0)

+#define SYS_CTRL_AP_MODE_APB1_AIF_AUTOMATIC (0<<1)

+#define SYS_CTRL_AP_MODE_APB1_AIF_MANUAL (1<<1)

+#define SYS_CTRL_AP_MODE_APB1_AIF2_AUTOMATIC (0<<2)

+#define SYS_CTRL_AP_MODE_APB1_AIF2_MANUAL (1<<2)

+#define SYS_CTRL_AP_MODE_APB1_AUIFC_AUTOMATIC (0<<3)

+#define SYS_CTRL_AP_MODE_APB1_AUIFC_MANUAL (1<<3)

+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH0_AUTOMATIC (0<<4)

+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH0_MANUAL (1<<4)

+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH1_AUTOMATIC (0<<5)

+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH1_MANUAL (1<<5)

+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH2_AUTOMATIC (0<<6)

+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH2_MANUAL (1<<6)

+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH3_AUTOMATIC (0<<7)

+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH3_MANUAL (1<<7)

+#define SYS_CTRL_AP_MODE_APB1_I2C1_AUTOMATIC (0<<8)

+#define SYS_CTRL_AP_MODE_APB1_I2C1_MANUAL (1<<8)

+#define SYS_CTRL_AP_MODE_APB1_I2C2_AUTOMATIC (0<<9)

+#define SYS_CTRL_AP_MODE_APB1_I2C2_MANUAL (1<<9)

+#define SYS_CTRL_AP_MODE_APB1_I2C3_AUTOMATIC (0<<10)

+#define SYS_CTRL_AP_MODE_APB1_I2C3_MANUAL (1<<10)

+#define SYS_CTRL_AP_MODE_APB1D_OSC_AUTOMATIC (0<<11)

+#define SYS_CTRL_AP_MODE_APB1D_OSC_MANUAL (1<<11)

+#define SYS_CTRL_AP_MODE_APB1D_PWM_AUTOMATIC (0<<12)

+#define SYS_CTRL_AP_MODE_APB1D_PWM_MANUAL (1<<12)

+#define SYS_CTRL_AP_MODE_CLK_APB1(n) (((n)&0x1FFF)<<0)

+#define SYS_CTRL_AP_MODE_CLK_APB1_MASK (0x1FFF<<0)

+#define SYS_CTRL_AP_MODE_CLK_APB1_SHIFT (0)

+

+//Clk_APB1_Enable

+#define SYS_CTRL_AP_ENABLE_APB1_CONF (1<<0)

+#define SYS_CTRL_AP_ENABLE_APB1_AIF (1<<1)

+#define SYS_CTRL_AP_ENABLE_APB1_AIF2 (1<<2)

+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC (1<<3)

+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH0 (1<<4)

+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH1 (1<<5)

+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH2 (1<<6)

+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH3 (1<<7)

+#define SYS_CTRL_AP_ENABLE_APB1_I2C1 (1<<8)

+#define SYS_CTRL_AP_ENABLE_APB1_I2C2 (1<<9)

+#define SYS_CTRL_AP_ENABLE_APB1_I2C3 (1<<10)

+#define SYS_CTRL_AP_ENABLE_APB1D_OSC (1<<11)

+#define SYS_CTRL_AP_ENABLE_APB1D_PWM (1<<12)

+#define SYS_CTRL_AP_ENABLE_APB1_ALWAYS (1<<13)

+#define SYS_CTRL_AP_ENABLE_APB1_DAPLITE (1<<14)

+#define SYS_CTRL_AP_ENABLE_APB1_TIMER (1<<15)

+#define SYS_CTRL_AP_ENABLE_APB1_GPIO (1<<16)

+#define SYS_CTRL_AP_ENABLE_CLK_APB1(n) (((n)&0x1FFFF)<<0)

+#define SYS_CTRL_AP_ENABLE_CLK_APB1_MASK (0x1FFFF<<0)

+#define SYS_CTRL_AP_ENABLE_CLK_APB1_SHIFT (0)

+

+//Clk_APB1_Disable

+#define SYS_CTRL_AP_DISABLE_APB1_CONF (1<<0)

+#define SYS_CTRL_AP_DISABLE_APB1_AIF (1<<1)

+#define SYS_CTRL_AP_DISABLE_APB1_AIF2 (1<<2)

+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC (1<<3)

+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH0 (1<<4)

+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH1 (1<<5)

+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH2 (1<<6)

+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH3 (1<<7)

+#define SYS_CTRL_AP_DISABLE_APB1_I2C1 (1<<8)

+#define SYS_CTRL_AP_DISABLE_APB1_I2C2 (1<<9)

+#define SYS_CTRL_AP_DISABLE_APB1_I2C3 (1<<10)

+#define SYS_CTRL_AP_DISABLE_APB1D_OSC (1<<11)

+#define SYS_CTRL_AP_DISABLE_APB1D_PWM (1<<12)

+#define SYS_CTRL_AP_DISABLE_APB1_ALWAYS (1<<13)

+#define SYS_CTRL_AP_DISABLE_APB1_DAPLITE (1<<14)

+#define SYS_CTRL_AP_DISABLE_APB1_TIMER (1<<15)

+#define SYS_CTRL_AP_DISABLE_APB1_GPIO (1<<16)

+#define SYS_CTRL_AP_DISABLE_CLK_APB1(n) (((n)&0x1FFFF)<<0)

+#define SYS_CTRL_AP_DISABLE_CLK_APB1_MASK (0x1FFFF<<0)

+#define SYS_CTRL_AP_DISABLE_CLK_APB1_SHIFT (0)

+

+//Clk_APB2_Mode

+#define SYS_CTRL_AP_MODE_APB2_CONF_AUTOMATIC (0<<0)

+#define SYS_CTRL_AP_MODE_APB2_CONF_MANUAL (1<<0)

+#define SYS_CTRL_AP_MODE_APB2_IFC_AUTOMATIC (0<<1)

+#define SYS_CTRL_AP_MODE_APB2_IFC_MANUAL (1<<1)

+#define SYS_CTRL_AP_MODE_APB2_IFC_CH0_AUTOMATIC (0<<2)

+#define SYS_CTRL_AP_MODE_APB2_IFC_CH0_MANUAL (1<<2)

+#define SYS_CTRL_AP_MODE_APB2_IFC_CH1_AUTOMATIC (0<<3)

+#define SYS_CTRL_AP_MODE_APB2_IFC_CH1_MANUAL (1<<3)

+#define SYS_CTRL_AP_MODE_APB2_IFC_CH2_AUTOMATIC (0<<4)

+#define SYS_CTRL_AP_MODE_APB2_IFC_CH2_MANUAL (1<<4)

+#define SYS_CTRL_AP_MODE_APB2_IFC_CH3_AUTOMATIC (0<<5)

+#define SYS_CTRL_AP_MODE_APB2_IFC_CH3_MANUAL (1<<5)

+#define SYS_CTRL_AP_MODE_APB2_IFC_CH4_AUTOMATIC (0<<6)

+#define SYS_CTRL_AP_MODE_APB2_IFC_CH4_MANUAL (1<<6)

+#define SYS_CTRL_AP_MODE_APB2_IFC_CH5_AUTOMATIC (0<<7)

+#define SYS_CTRL_AP_MODE_APB2_IFC_CH5_MANUAL (1<<7)

+#define SYS_CTRL_AP_MODE_APB2_IFC_CH6_AUTOMATIC (0<<8)

+#define SYS_CTRL_AP_MODE_APB2_IFC_CH6_MANUAL (1<<8)

+#define SYS_CTRL_AP_MODE_APB2_IFC_CH7_AUTOMATIC (0<<9)

+#define SYS_CTRL_AP_MODE_APB2_IFC_CH7_MANUAL (1<<9)

+#define SYS_CTRL_AP_MODE_APB2_UART1_AUTOMATIC (0<<10)

+#define SYS_CTRL_AP_MODE_APB2_UART1_MANUAL (1<<10)

+#define SYS_CTRL_AP_MODE_APB2_UART2_AUTOMATIC (0<<11)

+#define SYS_CTRL_AP_MODE_APB2_UART2_MANUAL (1<<11)

+#define SYS_CTRL_AP_MODE_APB2_UART3_AUTOMATIC (0<<12)

+#define SYS_CTRL_AP_MODE_APB2_UART3_MANUAL (1<<12)

+#define SYS_CTRL_AP_MODE_APB2_SPI1_AUTOMATIC (0<<13)

+#define SYS_CTRL_AP_MODE_APB2_SPI1_MANUAL (1<<13)

+#define SYS_CTRL_AP_MODE_APB2_SPI2_AUTOMATIC (0<<14)

+#define SYS_CTRL_AP_MODE_APB2_SPI2_MANUAL (1<<14)

+#define SYS_CTRL_AP_MODE_APB2_SPI3_AUTOMATIC (0<<15)

+#define SYS_CTRL_AP_MODE_APB2_SPI3_MANUAL (1<<15)

+#define SYS_CTRL_AP_MODE_APB2_SDMMC1_AUTOMATIC (0<<16)

+#define SYS_CTRL_AP_MODE_APB2_SDMMC1_MANUAL (1<<16)

+#define SYS_CTRL_AP_MODE_APB2_SDMMC2_AUTOMATIC (0<<17)

+#define SYS_CTRL_AP_MODE_APB2_SDMMC2_MANUAL (1<<17)

+#define SYS_CTRL_AP_MODE_APB2_SDMMC3_AUTOMATIC (0<<18)

+#define SYS_CTRL_AP_MODE_APB2_SDMMC3_MANUAL (1<<18)

+#define SYS_CTRL_AP_MODE_CLK_APB2(n) (((n)&0x7FFFF)<<0)

+#define SYS_CTRL_AP_MODE_CLK_APB2_MASK (0x7FFFF<<0)

+#define SYS_CTRL_AP_MODE_CLK_APB2_SHIFT (0)

+

+//Clk_APB2_Enable

+#define SYS_CTRL_AP_ENABLE_APB2_CONF (1<<0)

+#define SYS_CTRL_AP_ENABLE_APB2_IFC (1<<1)

+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH0 (1<<2)

+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH1 (1<<3)

+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH2 (1<<4)

+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH3 (1<<5)

+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH4 (1<<6)

+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH5 (1<<7)

+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH6 (1<<8)

+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH7 (1<<9)

+#define SYS_CTRL_AP_ENABLE_APB2_UART1 (1<<10)

+#define SYS_CTRL_AP_ENABLE_APB2_UART2 (1<<11)

+#define SYS_CTRL_AP_ENABLE_APB2_UART3 (1<<12)

+#define SYS_CTRL_AP_ENABLE_APB2_SPI1 (1<<13)

+#define SYS_CTRL_AP_ENABLE_APB2_SPI2 (1<<14)

+#define SYS_CTRL_AP_ENABLE_APB2_SPI3 (1<<15)

+#define SYS_CTRL_AP_ENABLE_APB2_SDMMC1 (1<<16)

+#define SYS_CTRL_AP_ENABLE_APB2_SDMMC2 (1<<17)

+#define SYS_CTRL_AP_ENABLE_APB2_SDMMC3 (1<<18)

+#define SYS_CTRL_AP_ENABLE_APB2_ALWAYS (1<<19)

+#define SYS_CTRL_AP_ENABLE_APB2_NANDFLASH (1<<20)

+#define SYS_CTRL_AP_ENABLE_CLK_APB2(n) (((n)&0x1FFFFF)<<0)

+#define SYS_CTRL_AP_ENABLE_CLK_APB2_MASK (0x1FFFFF<<0)

+#define SYS_CTRL_AP_ENABLE_CLK_APB2_SHIFT (0)

+

+//Clk_APB2_Disable

+#define SYS_CTRL_AP_DISABLE_APB2_CONF (1<<0)

+#define SYS_CTRL_AP_DISABLE_APB2_IFC (1<<1)

+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH0 (1<<2)

+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH1 (1<<3)

+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH2 (1<<4)

+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH3 (1<<5)

+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH4 (1<<6)

+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH5 (1<<7)

+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH6 (1<<8)

+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH7 (1<<9)

+#define SYS_CTRL_AP_DISABLE_APB2_UART1 (1<<10)

+#define SYS_CTRL_AP_DISABLE_APB2_UART2 (1<<11)

+#define SYS_CTRL_AP_DISABLE_APB2_UART3 (1<<12)

+#define SYS_CTRL_AP_DISABLE_APB2_SPI1 (1<<13)

+#define SYS_CTRL_AP_DISABLE_APB2_SPI2 (1<<14)

+#define SYS_CTRL_AP_DISABLE_APB2_SPI3 (1<<15)

+#define SYS_CTRL_AP_DISABLE_APB2_SDMMC1 (1<<16)

+#define SYS_CTRL_AP_DISABLE_APB2_SDMMC2 (1<<17)

+#define SYS_CTRL_AP_DISABLE_APB2_SDMMC3 (1<<18)

+#define SYS_CTRL_AP_DISABLE_APB2_ALWAYS (1<<19)

+#define SYS_CTRL_AP_DISABLE_APB2_NANDFLASH (1<<20)

+#define SYS_CTRL_AP_DISABLE_CLK_APB2(n) (((n)&0x1FFFFF)<<0)

+#define SYS_CTRL_AP_DISABLE_CLK_APB2_MASK (0x1FFFFF<<0)

+#define SYS_CTRL_AP_DISABLE_CLK_APB2_SHIFT (0)

+

+//Clk_MEM_Mode

+#define SYS_CTRL_AP_MODE_CLK_MEM_AUTOMATIC (0<<0)

+#define SYS_CTRL_AP_MODE_CLK_MEM_MANUAL (1<<0)

+

+//Clk_MEM_Enable

+#define SYS_CTRL_AP_ENABLE_MEM_CONF (1<<0)

+#define SYS_CTRL_AP_ENABLE_MEM_DMC (1<<1)

+#define SYS_CTRL_AP_ENABLE_MEM_GPU (1<<2)

+#define SYS_CTRL_AP_ENABLE_MEM_VPU (1<<3)

+#define SYS_CTRL_AP_ENABLE_MEM_DDRPHY_P (1<<4)

+#define SYS_CTRL_AP_ENABLE_MEM_CONNECT (1<<5)

+#define SYS_CTRL_AP_ENABLE_CLK_MEM(n) (((n)&0x3F)<<0)

+#define SYS_CTRL_AP_ENABLE_CLK_MEM_MASK (0x3F<<0)

+#define SYS_CTRL_AP_ENABLE_CLK_MEM_SHIFT (0)

+

+//Clk_MEM_Disable

+#define SYS_CTRL_AP_DISABLE_MEM_CONF (1<<0)

+#define SYS_CTRL_AP_DISABLE_MEM_DMC (1<<1)

+#define SYS_CTRL_AP_DISABLE_MEM_GPU (1<<2)

+#define SYS_CTRL_AP_DISABLE_MEM_VPU (1<<3)

+#define SYS_CTRL_AP_DISABLE_MEM_DDRPHY_P (1<<4)

+#define SYS_CTRL_AP_DISABLE_MEM_CONNECT (1<<5)

+#define SYS_CTRL_AP_DISABLE_CLK_MEM(n) (((n)&0x3F)<<0)

+#define SYS_CTRL_AP_DISABLE_CLK_MEM_MASK (0x3F<<0)

+#define SYS_CTRL_AP_DISABLE_CLK_MEM_SHIFT (0)

+

+//Clk_APO_Mode

+#define SYS_CTRL_AP_MODE_APOC_VPU_AUTOMATIC (0<<0)

+#define SYS_CTRL_AP_MODE_APOC_VPU_MANUAL (1<<0)

+#define SYS_CTRL_AP_MODE_APOC_BCK_AUTOMATIC (0<<1)

+#define SYS_CTRL_AP_MODE_APOC_BCK_MANUAL (1<<1)

+#define SYS_CTRL_AP_MODE_APOC_BCK2_AUTOMATIC (0<<2)

+#define SYS_CTRL_AP_MODE_APOC_BCK2_MANUAL (1<<2)

+#define SYS_CTRL_AP_MODE_APOC_UART1_AUTOMATIC (0<<3)

+#define SYS_CTRL_AP_MODE_APOC_UART1_MANUAL (1<<3)

+#define SYS_CTRL_AP_MODE_APOC_UART2_AUTOMATIC (0<<4)

+#define SYS_CTRL_AP_MODE_APOC_UART2_MANUAL (1<<4)

+#define SYS_CTRL_AP_MODE_APOC_UART3_AUTOMATIC (0<<5)

+#define SYS_CTRL_AP_MODE_APOC_UART3_MANUAL (1<<5)

+#define SYS_CTRL_AP_MODE_APOC_VOC_CORE_AUTOMATIC (0<<6)

+#define SYS_CTRL_AP_MODE_APOC_VOC_CORE_MANUAL (1<<6)

+#define SYS_CTRL_AP_MODE_APOC_VOC2_CORE_AUTOMATIC (0<<7)

+#define SYS_CTRL_AP_MODE_APOC_VOC2_CORE_MANUAL (1<<7)

+#define SYS_CTRL_AP_MODE_APOC_VOC_AUTOMATIC (0<<8)

+#define SYS_CTRL_AP_MODE_APOC_VOC_MANUAL (1<<8)

+#define SYS_CTRL_AP_MODE_APOC_VOC2_AUTOMATIC (0<<9)

+#define SYS_CTRL_AP_MODE_APOC_VOC2_MANUAL (1<<9)

+#define SYS_CTRL_AP_MODE_CLK_APO(n) (((n)&0x3FF)<<0)

+#define SYS_CTRL_AP_MODE_CLK_APO_MASK (0x3FF<<0)

+#define SYS_CTRL_AP_MODE_CLK_APO_SHIFT (0)

+

+//Clk_APO_Enable

+#define SYS_CTRL_AP_ENABLE_APOC_VPU (1<<0)

+#define SYS_CTRL_AP_ENABLE_APOC_BCK (1<<1)

+#define SYS_CTRL_AP_ENABLE_APOC_BCK2 (1<<2)

+#define SYS_CTRL_AP_ENABLE_APOC_UART1 (1<<3)

+#define SYS_CTRL_AP_ENABLE_APOC_UART2 (1<<4)

+#define SYS_CTRL_AP_ENABLE_APOC_UART3 (1<<5)

+#define SYS_CTRL_AP_ENABLE_APOC_VOC_CORE (1<<6)

+#define SYS_CTRL_AP_ENABLE_APOC_VOC2_CORE (1<<7)

+#define SYS_CTRL_AP_ENABLE_APOC_VOC (1<<8)

+#define SYS_CTRL_AP_ENABLE_APOC_VOC2 (1<<9)

+#define SYS_CTRL_AP_ENABLE_APOC_VOC_ALWAYS (1<<10)

+#define SYS_CTRL_AP_ENABLE_APOC_VOC2_ALWAYS (1<<11)

+#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY_N (1<<12)

+#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY2XP (1<<13)

+#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY2XN (1<<14)

+#define SYS_CTRL_AP_ENABLE_APOC_GPU (1<<15)

+#define SYS_CTRL_AP_ENABLE_APOC_USBPHY (1<<16)

+#define SYS_CTRL_AP_ENABLE_APOC_CSI (1<<17)

+#define SYS_CTRL_AP_ENABLE_APOC_DSI (1<<18)

+#define SYS_CTRL_AP_ENABLE_APOC_GPIO (1<<19)

+#define SYS_CTRL_AP_ENABLE_APOC_SPIFLASH (1<<20)

+#define SYS_CTRL_AP_ENABLE_APOC_PIX (1<<21)

+#define SYS_CTRL_AP_ENABLE_APOC_PDGB (1<<22)

+#define SYS_CTRL_AP_ENABLE_CLK_APO(n) (((n)&0x7FFFFF)<<0)

+#define SYS_CTRL_AP_ENABLE_CLK_APO_MASK (0x7FFFFF<<0)

+#define SYS_CTRL_AP_ENABLE_CLK_APO_SHIFT (0)

+

+//Clk_APO_Disable

+#define SYS_CTRL_AP_DISABLE_APOC_VPU (1<<0)

+#define SYS_CTRL_AP_DISABLE_APOC_BCK (1<<1)

+#define SYS_CTRL_AP_DISABLE_APOC_BCK2 (1<<2)

+#define SYS_CTRL_AP_DISABLE_APOC_UART1 (1<<3)

+#define SYS_CTRL_AP_DISABLE_APOC_UART2 (1<<4)

+#define SYS_CTRL_AP_DISABLE_APOC_UART3 (1<<5)

+#define SYS_CTRL_AP_DISABLE_APOC_VOC_CORE (1<<6)

+#define SYS_CTRL_AP_DISABLE_APOC_VOC2_CORE (1<<7)

+#define SYS_CTRL_AP_DISABLE_APOC_VOC (1<<8)

+#define SYS_CTRL_AP_DISABLE_APOC_VOC2 (1<<9)

+#define SYS_CTRL_AP_DISABLE_APOC_VOC_ALWAYS (1<<10)

+#define SYS_CTRL_AP_DISABLE_APOC_VOC2_ALWAYS (1<<11)

+#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY_N (1<<12)

+#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY2XP (1<<13)

+#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY2XN (1<<14)

+#define SYS_CTRL_AP_DISABLE_APOC_GPU (1<<15)

+#define SYS_CTRL_AP_DISABLE_APOC_USBPHY (1<<16)

+#define SYS_CTRL_AP_DISABLE_APOC_CSI (1<<17)

+#define SYS_CTRL_AP_DISABLE_APOC_DSI (1<<18)

+#define SYS_CTRL_AP_DISABLE_APOC_GPIO (1<<19)

+#define SYS_CTRL_AP_DISABLE_APOC_SPIFLASH (1<<20)

+#define SYS_CTRL_AP_DISABLE_APOC_PIX (1<<21)

+#define SYS_CTRL_AP_DISABLE_APOC_PDGB (1<<22)

+#define SYS_CTRL_AP_DISABLE_CLK_APO(n) (((n)&0x7FFFFF)<<0)

+#define SYS_CTRL_AP_DISABLE_CLK_APO_MASK (0x7FFFFF<<0)

+#define SYS_CTRL_AP_DISABLE_CLK_APO_SHIFT (0)

+

+//Cfg_Clk_AP_CPU

+#define SYS_CTRL_AP_AP_CPU_FREQ(n) (((n)&31)<<0)

+#define SYS_CTRL_AP_AP_CPU_FREQ_MASK (31<<0)

+#define SYS_CTRL_AP_AP_CPU_FREQ_SHIFT (0)

+#define SYS_CTRL_AP_AP_CPU_FREQ_19M (6<<0)

+#define SYS_CTRL_AP_AP_CPU_FREQ_20M (7<<0)

+#define SYS_CTRL_AP_AP_CPU_FREQ_300M (26<<0)

+#define SYS_CTRL_AP_AP_CPU_FREQ_340M (27<<0)

+#define SYS_CTRL_AP_AP_CPU_FREQ_400M (28<<0)

+#define SYS_CTRL_AP_AP_CPU_FREQ_480M (29<<0)

+#define SYS_CTRL_AP_AP_CPU_FREQ_600M (30<<0)

+#define SYS_CTRL_AP_AP_CPU_FREQ_1_2G (31<<0)

+#define SYS_CTRL_AP_BUS_DIV_SEL(n) (((n)&3)<<16)

+#define SYS_CTRL_AP_BUS_DIV_SEL_MASK (3<<16)

+#define SYS_CTRL_AP_BUS_DIV_SEL_SHIFT (16)

+#define SYS_CTRL_AP_BUS_DIV_SEL_DIV2 (0<<16)

+#define SYS_CTRL_AP_BUS_DIV_SEL_DIV3 (1<<16)

+#define SYS_CTRL_AP_BUS_DIV_SEL_DIV4 (2<<16)

+#define SYS_CTRL_AP_AP_CPU_REQ_DIV_UPDATE (1<<31)

+

+//Cfg_Clk_AP_AXI

+#define SYS_CTRL_AP_AP_AXI_FREQ(n) (((n)&31)<<0)

+#define SYS_CTRL_AP_AP_AXI_FREQ_MASK (31<<0)

+#define SYS_CTRL_AP_AP_AXI_FREQ_SHIFT (0)

+#define SYS_CTRL_AP_AP_AXI_FREQ_19M (6<<0)

+#define SYS_CTRL_AP_AP_AXI_FREQ_20M (7<<0)

+#define SYS_CTRL_AP_AP_AXI_FREQ_300M (26<<0)

+#define SYS_CTRL_AP_AP_AXI_FREQ_340M (27<<0)

+#define SYS_CTRL_AP_AP_AXI_FREQ_400M (28<<0)

+#define SYS_CTRL_AP_AP_AXI_FREQ_480M (29<<0)

+#define SYS_CTRL_AP_AP_AXI_FREQ_600M (30<<0)

+#define SYS_CTRL_AP_AP_AXI_FREQ_1_2G (31<<0)

+#define SYS_CTRL_AP_AP_AXI_SRC_SEL (1<<12)

+#define SYS_CTRL_AP_AP_AXI_REQ_DIV_UPDATE (1<<31)

+

+//Cfg_Clk_AP_GCG

+#define SYS_CTRL_AP_AP_GCG_FREQ(n) (((n)&31)<<0)

+#define SYS_CTRL_AP_AP_GCG_FREQ_MASK (31<<0)

+#define SYS_CTRL_AP_AP_GCG_FREQ_SHIFT (0)

+#define SYS_CTRL_AP_AP_GCG_FREQ_19M (6<<0)

+#define SYS_CTRL_AP_AP_GCG_FREQ_20M (7<<0)

+#define SYS_CTRL_AP_AP_GCG_FREQ_300M (26<<0)

+#define SYS_CTRL_AP_AP_GCG_FREQ_340M (27<<0)

+#define SYS_CTRL_AP_AP_GCG_FREQ_400M (28<<0)

+#define SYS_CTRL_AP_AP_GCG_FREQ_480M (29<<0)

+#define SYS_CTRL_AP_AP_GCG_FREQ_600M (30<<0)

+#define SYS_CTRL_AP_AP_GCG_FREQ_1_2G (31<<0)

+#define SYS_CTRL_AP_AP_GCG_SRC_SEL (1<<12)

+#define SYS_CTRL_AP_AP_GCG_REQ_DIV_UPDATE (1<<31)

+

+//Cfg_Clk_AP_AHB1

+#define SYS_CTRL_AP_AP_AHB1_FREQ(n) (((n)&31)<<0)

+#define SYS_CTRL_AP_AP_AHB1_FREQ_MASK (31<<0)

+#define SYS_CTRL_AP_AP_AHB1_FREQ_SHIFT (0)

+#define SYS_CTRL_AP_AP_AHB1_FREQ_19M (6<<0)

+#define SYS_CTRL_AP_AP_AHB1_FREQ_20M (7<<0)

+#define SYS_CTRL_AP_AP_AHB1_FREQ_300M (26<<0)

+#define SYS_CTRL_AP_AP_AHB1_FREQ_340M (27<<0)

+#define SYS_CTRL_AP_AP_AHB1_FREQ_400M (28<<0)

+#define SYS_CTRL_AP_AP_AHB1_FREQ_480M (29<<0)

+#define SYS_CTRL_AP_AP_AHB1_FREQ_600M (30<<0)

+#define SYS_CTRL_AP_AP_AHB1_FREQ_1_2G (31<<0)

+#define SYS_CTRL_AP_AP_AHB1_SRC_SEL (1<<12)

+#define SYS_CTRL_AP_AP_AHB1_REQ_DIV_UPDATE (1<<31)

+

+//Cfg_Clk_AP_APB1

+#define SYS_CTRL_AP_AP_APB1_FREQ(n) (((n)&31)<<0)

+#define SYS_CTRL_AP_AP_APB1_FREQ_MASK (31<<0)

+#define SYS_CTRL_AP_AP_APB1_FREQ_SHIFT (0)

+#define SYS_CTRL_AP_AP_APB1_FREQ_19M (6<<0)

+#define SYS_CTRL_AP_AP_APB1_FREQ_20M (7<<0)

+#define SYS_CTRL_AP_AP_APB1_FREQ_300M (26<<0)

+#define SYS_CTRL_AP_AP_APB1_FREQ_340M (27<<0)

+#define SYS_CTRL_AP_AP_APB1_FREQ_400M (28<<0)

+#define SYS_CTRL_AP_AP_APB1_FREQ_480M (29<<0)

+#define SYS_CTRL_AP_AP_APB1_FREQ_600M (30<<0)

+#define SYS_CTRL_AP_AP_APB1_FREQ_1_2G (31<<0)

+#define SYS_CTRL_AP_AP_APB1_SRC_SEL (1<<12)

+#define SYS_CTRL_AP_AP_APB1_REQ_DIV_UPDATE (1<<31)

+

+//Cfg_Clk_AP_APB2

+#define SYS_CTRL_AP_AP_APB2_FREQ(n) (((n)&31)<<0)

+#define SYS_CTRL_AP_AP_APB2_FREQ_MASK (31<<0)

+#define SYS_CTRL_AP_AP_APB2_FREQ_SHIFT (0)

+#define SYS_CTRL_AP_AP_APB2_FREQ_19M (6<<0)

+#define SYS_CTRL_AP_AP_APB2_FREQ_20M (7<<0)

+#define SYS_CTRL_AP_AP_APB2_FREQ_300M (26<<0)

+#define SYS_CTRL_AP_AP_APB2_FREQ_340M (27<<0)

+#define SYS_CTRL_AP_AP_APB2_FREQ_400M (28<<0)

+#define SYS_CTRL_AP_AP_APB2_FREQ_480M (29<<0)

+#define SYS_CTRL_AP_AP_APB2_FREQ_600M (30<<0)

+#define SYS_CTRL_AP_AP_APB2_FREQ_1_2G (31<<0)

+#define SYS_CTRL_AP_AP_APB2_SRC_SEL (1<<12)

+#define SYS_CTRL_AP_AP_APB2_REQ_DIV_UPDATE (1<<31)

+

+//Cfg_Clk_AP_MEM

+#define SYS_CTRL_AP_AP_MEM_SRC_DIV2 (1<<12)

+

+//Cfg_Clk_AP_GPU

+#define SYS_CTRL_AP_AP_GPU_FREQ(n) (((n)&31)<<0)

+#define SYS_CTRL_AP_AP_GPU_FREQ_MASK (31<<0)

+#define SYS_CTRL_AP_AP_GPU_FREQ_SHIFT (0)

+#define SYS_CTRL_AP_AP_GPU_FREQ_19M (6<<0)

+#define SYS_CTRL_AP_AP_GPU_FREQ_20M (7<<0)

+#define SYS_CTRL_AP_AP_GPU_FREQ_300M (26<<0)

+#define SYS_CTRL_AP_AP_GPU_FREQ_340M (27<<0)

+#define SYS_CTRL_AP_AP_GPU_FREQ_400M (28<<0)

+#define SYS_CTRL_AP_AP_GPU_FREQ_480M (29<<0)

+#define SYS_CTRL_AP_AP_GPU_FREQ_600M (30<<0)

+#define SYS_CTRL_AP_AP_GPU_FREQ_1_2G (31<<0)

+#define SYS_CTRL_AP_AP_GPU_SRC_DIV2 (1<<12)

+#define SYS_CTRL_AP_AP_GPU_REQ_DIV_UPDATE (1<<31)

+

+//Cfg_Clk_AP_VPU

+#define SYS_CTRL_AP_AP_VPU_FREQ(n) (((n)&31)<<0)

+#define SYS_CTRL_AP_AP_VPU_FREQ_MASK (31<<0)

+#define SYS_CTRL_AP_AP_VPU_FREQ_SHIFT (0)

+#define SYS_CTRL_AP_AP_VPU_FREQ_19M (6<<0)

+#define SYS_CTRL_AP_AP_VPU_FREQ_20M (7<<0)

+#define SYS_CTRL_AP_AP_VPU_FREQ_300M (26<<0)

+#define SYS_CTRL_AP_AP_VPU_FREQ_340M (27<<0)

+#define SYS_CTRL_AP_AP_VPU_FREQ_400M (28<<0)

+#define SYS_CTRL_AP_AP_VPU_FREQ_480M (29<<0)

+#define SYS_CTRL_AP_AP_VPU_FREQ_600M (30<<0)

+#define SYS_CTRL_AP_AP_VPU_FREQ_1_2G (31<<0)

+#define SYS_CTRL_AP_AP_VPU_SRC_DIV2 (1<<12)

+#define SYS_CTRL_AP_AP_VPU_REQ_DIV_UPDATE (1<<31)

+

+//Cfg_Clk_AP_VOC

+#define SYS_CTRL_AP_AP_VOC_FREQ(n) (((n)&31)<<0)

+#define SYS_CTRL_AP_AP_VOC_FREQ_MASK (31<<0)

+#define SYS_CTRL_AP_AP_VOC_FREQ_SHIFT (0)

+#define SYS_CTRL_AP_AP_VOC_FREQ_19M (6<<0)

+#define SYS_CTRL_AP_AP_VOC_FREQ_20M (7<<0)

+#define SYS_CTRL_AP_AP_VOC_FREQ_300M (26<<0)

+#define SYS_CTRL_AP_AP_VOC_FREQ_340M (27<<0)

+#define SYS_CTRL_AP_AP_VOC_FREQ_400M (28<<0)

+#define SYS_CTRL_AP_AP_VOC_FREQ_480M (29<<0)

+#define SYS_CTRL_AP_AP_VOC_FREQ_600M (30<<0)

+#define SYS_CTRL_AP_AP_VOC_FREQ_1_2G (31<<0)

+#define SYS_CTRL_AP_AP_VOC_SRC_DIV2 (1<<12)

+#define SYS_CTRL_AP_AP_VOC_REQ_DIV_UPDATE (1<<31)

+

+//Cfg_Clk_AP_SFLSH

+#define SYS_CTRL_AP_AP_SFLSH_FREQ(n) (((n)&31)<<0)

+#define SYS_CTRL_AP_AP_SFLSH_FREQ_MASK (31<<0)

+#define SYS_CTRL_AP_AP_SFLSH_FREQ_SHIFT (0)

+#define SYS_CTRL_AP_AP_SFLSH_FREQ_19M (6<<0)

+#define SYS_CTRL_AP_AP_SFLSH_FREQ_20M (7<<0)

+#define SYS_CTRL_AP_AP_SFLSH_FREQ_300M (26<<0)

+#define SYS_CTRL_AP_AP_SFLSH_FREQ_340M (27<<0)

+#define SYS_CTRL_AP_AP_SFLSH_FREQ_400M (28<<0)

+#define SYS_CTRL_AP_AP_SFLSH_FREQ_480M (29<<0)

+#define SYS_CTRL_AP_AP_SFLSH_FREQ_600M (30<<0)

+#define SYS_CTRL_AP_AP_SFLSH_FREQ_1_2G (31<<0)

+#define SYS_CTRL_AP_AP_SFLSH_SRC_DIV2 (1<<12)

+#define SYS_CTRL_AP_AP_SFLSH_REQ_DIV_UPDATE (1<<31)

+

+//Cfg_Clk_Uart

+#define SYS_CTRL_AP_UART_DIVIDER(n) (((n)&0x3FF)<<0)

+#define SYS_CTRL_AP_UART_DIVIDER_MASK (0x3FF<<0)

+#define SYS_CTRL_AP_UART_DIVIDER_SHIFT (0)

+#define SYS_CTRL_AP_UART_SEL_PLL_SLOW (0<<12)

+#define SYS_CTRL_AP_UART_SEL_PLL_PLL (1<<12)

+

+//L2cc_Ctrl

+#define SYS_CTRL_AP_ARQOS_L2CC_1_M(n) (((n)&15)<<0)

+#define SYS_CTRL_AP_ARQOS_L2CC_1_M_MASK (15<<0)

+#define SYS_CTRL_AP_ARQOS_L2CC_1_M_SHIFT (0)

+#define SYS_CTRL_AP_AWQOS_L2CC_1_M(n) (((n)&15)<<4)

+#define SYS_CTRL_AP_AWQOS_L2CC_1_M_MASK (15<<4)

+#define SYS_CTRL_AP_AWQOS_L2CC_1_M_SHIFT (4)

+#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M(n) (((n)&15)<<8)

+#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M_MASK (15<<8)

+#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M_SHIFT (8)

+#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M(n) (((n)&15)<<12)

+#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M_MASK (15<<12)

+#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M_SHIFT (12)

+#define SYS_CTRL_AP_ARAP_L2CC_1_M  (1<<16)

+#define SYS_CTRL_AP_AWAP_L2CC_1_M  (1<<17)

+#define SYS_CTRL_AP_ARAP_MODEM_MEM_AHBS_M (1<<18)

+#define SYS_CTRL_AP_AWAP_MODEM_MEM_AHBS_M (1<<19)

+#define SYS_CTRL_AP_ARAP_MERGE1M   (1<<20)

+#define SYS_CTRL_AP_AWAP_MERGE1M   (1<<21)

+#define SYS_CTRL_AP_ARAP_MERGE2M   (1<<22)

+#define SYS_CTRL_AP_AWAP_MERGE2M   (1<<23)

+#define SYS_CTRL_AP_RESERVE1(n)    (((n)&0xFF)<<24)

+#define SYS_CTRL_AP_RESERVE1_MASK  (0xFF<<24)

+#define SYS_CTRL_AP_RESERVE1_SHIFT (24)

+

+//Spi_Ctrl

+#define SYS_CTRL_AP_LIMITED_EN_SPI1 (1<<0)

+#define SYS_CTRL_AP_LPSEN_SPI1     (1<<1)

+#define SYS_CTRL_AP_LIMITED_EN_SPI2 (1<<2)

+#define SYS_CTRL_AP_LPSEN_SPI2     (1<<3)

+#define SYS_CTRL_AP_LIMITED_EN_SPI3 (1<<4)

+#define SYS_CTRL_AP_LPSEN_SPI3     (1<<5)

+#define SYS_CTRL_AP_FBUSWID_NFSC   (1<<6)

+#define SYS_CTRL_AP_RESERVE3       (1<<7)

+#define SYS_CTRL_AP_DMC_CFG(n)     (((n)&0x3FF)<<8)

+#define SYS_CTRL_AP_DMC_CFG_MASK   (0x3FF<<8)

+#define SYS_CTRL_AP_DMC_CFG_SHIFT  (8)

+#define SYS_CTRL_AP_RESERVE2(n)    (((n)&0x3FFF)<<18)

+#define SYS_CTRL_AP_RESERVE2_MASK  (0x3FFF<<18)

+#define SYS_CTRL_AP_RESERVE2_SHIFT (18)

+

+//Memory_Margin

+#define SYS_CTRL_AP_EMAW_VOC(n)    (((n)&3)<<0)

+#define SYS_CTRL_AP_EMAW_VOC_MASK  (3<<0)

+#define SYS_CTRL_AP_EMAW_VOC_SHIFT (0)

+#define SYS_CTRL_AP_EMA_VOC(n)     (((n)&7)<<2)

+#define SYS_CTRL_AP_EMA_VOC_MASK   (7<<2)

+#define SYS_CTRL_AP_EMA_VOC_SHIFT  (2)

+#define SYS_CTRL_AP_EMAW_VPU(n)    (((n)&3)<<5)

+#define SYS_CTRL_AP_EMAW_VPU_MASK  (3<<5)

+#define SYS_CTRL_AP_EMAW_VPU_SHIFT (5)

+#define SYS_CTRL_AP_EMA_VPU(n)     (((n)&7)<<7)

+#define SYS_CTRL_AP_EMA_VPU_MASK   (7<<7)

+#define SYS_CTRL_AP_EMA_VPU_SHIFT  (7)

+#define SYS_CTRL_AP_EMAW_GPU(n)    (((n)&3)<<10)

+#define SYS_CTRL_AP_EMAW_GPU_MASK  (3<<10)

+#define SYS_CTRL_AP_EMAW_GPU_SHIFT (10)

+#define SYS_CTRL_AP_EMA_GPU(n)     (((n)&7)<<12)

+#define SYS_CTRL_AP_EMA_GPU_MASK   (7<<12)

+#define SYS_CTRL_AP_EMA_GPU_SHIFT  (12)

+#define SYS_CTRL_AP_EMAW_GOUDA(n)  (((n)&3)<<15)

+#define SYS_CTRL_AP_EMAW_GOUDA_MASK (3<<15)

+#define SYS_CTRL_AP_EMAW_GOUDA_SHIFT (15)

+#define SYS_CTRL_AP_EMA_GOUDA(n)   (((n)&7)<<17)

+#define SYS_CTRL_AP_EMA_GOUDA_MASK (7<<17)

+#define SYS_CTRL_AP_EMA_GOUDA_SHIFT (17)

+#define SYS_CTRL_AP_EMAW_IMEM(n)   (((n)&3)<<20)

+#define SYS_CTRL_AP_EMAW_IMEM_MASK (3<<20)

+#define SYS_CTRL_AP_EMAW_IMEM_SHIFT (20)

+#define SYS_CTRL_AP_EMA_IMEM(n)    (((n)&7)<<22)

+#define SYS_CTRL_AP_EMA_IMEM_MASK  (7<<22)

+#define SYS_CTRL_AP_EMA_IMEM_SHIFT (22)

+#define SYS_CTRL_AP_EMAW_USB(n)    (((n)&3)<<25)

+#define SYS_CTRL_AP_EMAW_USB_MASK  (3<<25)

+#define SYS_CTRL_AP_EMAW_USB_SHIFT (25)

+#define SYS_CTRL_AP_EMA_USB(n)     (((n)&7)<<27)

+#define SYS_CTRL_AP_EMA_USB_MASK   (7<<27)

+#define SYS_CTRL_AP_EMA_USB_SHIFT  (27)

+

+//Memory_Margin2

+#define SYS_CTRL_AP_EMAW_NFSC(n)   (((n)&3)<<0)

+#define SYS_CTRL_AP_EMAW_NFSC_MASK (3<<0)

+#define SYS_CTRL_AP_EMAW_NFSC_SHIFT (0)

+#define SYS_CTRL_AP_EMA_NFSC(n)    (((n)&7)<<2)

+#define SYS_CTRL_AP_EMA_NFSC_MASK  (7<<2)

+#define SYS_CTRL_AP_EMA_NFSC_SHIFT (2)

+#define SYS_CTRL_AP_EMA_VPUROM(n)  (((n)&7)<<5)

+#define SYS_CTRL_AP_EMA_VPUROM_MASK (7<<5)

+#define SYS_CTRL_AP_EMA_VPUROM_SHIFT (5)

+#define SYS_CTRL_AP_EMA_IMEMROM(n) (((n)&7)<<8)

+#define SYS_CTRL_AP_EMA_IMEMROM_MASK (7<<8)

+#define SYS_CTRL_AP_EMA_IMEMROM_SHIFT (8)

+#define SYS_CTRL_AP_KEN_VPUROM     (1<<11)

+#define SYS_CTRL_AP_PGEN_VPUROM    (1<<12)

+#define SYS_CTRL_AP_KEN_IMEMROM    (1<<13)

+#define SYS_CTRL_AP_PGEN_IMEMROM   (1<<14)

+

+//Memory_Observe

+#define SYS_CTRL_AP_MEM_OBSERVE(n) (((n)&0xFFFFFFFF)<<0)

+

+//Cfg_Clk_AP_VOC2

+//#define SYS_CTRL_AP_AP_VOC_FREQ(n) (((n)&31)<<0)

+//#define SYS_CTRL_AP_AP_VOC_FREQ_MASK (31<<0)

+//#define SYS_CTRL_AP_AP_VOC_FREQ_SHIFT (0)

+//#define SYS_CTRL_AP_AP_VOC_FREQ_19M (6<<0)

+//#define SYS_CTRL_AP_AP_VOC_FREQ_20M (7<<0)

+//#define SYS_CTRL_AP_AP_VOC_FREQ_300M (26<<0)

+//#define SYS_CTRL_AP_AP_VOC_FREQ_340M (27<<0)

+//#define SYS_CTRL_AP_AP_VOC_FREQ_400M (28<<0)

+//#define SYS_CTRL_AP_AP_VOC_FREQ_480M (29<<0)

+//#define SYS_CTRL_AP_AP_VOC_FREQ_600M (30<<0)

+//#define SYS_CTRL_AP_AP_VOC_FREQ_1_2G (31<<0)

+//#define SYS_CTRL_AP_AP_VOC_SRC_DIV2 (1<<12)

+//#define SYS_CTRL_AP_AP_VOC_REQ_DIV_UPDATE (1<<31)

+

+//Cfg_Reserve

+#define SYS_CTRL_AP_RESERVE(n)     (((n)&0x3FFFFFFF)<<0)

+#define SYS_CTRL_AP_AUIFC_CH0_IRQ_MASK (1<<30)

+#define SYS_CTRL_AP_AUIFC_CH1_IRQ_MASK (1<<31)

+

+

+

+

+

+#endif

+

diff --git a/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8850e.h b/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8850e.h
new file mode 100644
index 0000000000..9ae0041a35
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_sysctrl_rda8850e.h
@@ -0,0 +1,1540 @@
+#ifndef _REG_SYSCTRL_H_
+#define _REG_SYSCTRL_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+
+// ============================================================================
+// AP_CPU_ID_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// CPU IDs
+    CPU0                                        = 0x00000000,
+    CPU1                                        = 0x00000001
+} AP_CPU_ID_T;
+
+
+// ============================================================================
+// CPU_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP CPU side System clocks
+    CPU_CORE                                    = 0x00000000,
+/// the following don't have an auto enable
+    CPU_DUMMY                                   = 0x00000001
+} CPU_CLKS_T;
+
+#define NB_CPU_CLK_AEN                          (1)
+#define NB_CPU_CLK_EN                           (2)
+#define NB_CPU_CLK                              (2)
+
+// ============================================================================
+// AXI_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AXI side System clocks: AXI and AHB0 and APB0
+    AHB0_CONF                                   = 0x00000000,
+    APB0_CONF                                   = 0x00000001,
+    AXI_VOC                                     = 0x00000002,
+    AXI_VOC2                                    = 0x00000003,
+    AXI_DMA                                     = 0x00000004,
+/// the following don't have an auto enable
+    AXI_ALWAYS                                  = 0x00000005,
+    AXI_CONNECT                                 = 0x00000006,
+    APB0_IRQ                                    = 0x00000007
+} AXI_CLKS_T;
+
+#define NB_AXI_CLK_AEN                          (5)
+#define NB_AXI_CLK_EN                           (8)
+#define NB_AXI_CLK                              (8)
+
+// ============================================================================
+// AXIDIV2_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AXIdiv2 side System clocks
+    AXIDIV2_IMEM                                = 0x00000000,
+/// the following don't have an auto enable
+    AXIDIV2_ALWAYS                              = 0x00000001,
+    AXIDIV2_CONNECT                             = 0x00000002,
+    AXIDIV2_VPU                                 = 0x00000003
+} AXIDIV2_CLKS_T;
+
+#define NB_AXIDIV2_CLK_AEN                      (1)
+#define NB_AXIDIV2_CLK_EN                       (4)
+#define NB_AXIDIV2_CLK                          (4)
+
+// ============================================================================
+// GCG_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP GCG side System clocks
+    GCG_APB_CONF                                = 0x00000000,
+    GCG_GOUDA                                   = 0x00000001,
+    GCG_CAMERA                                  = 0x00000002,
+/// the following don't have an auto enable
+    GCG_ALWAYS                                  = 0x00000003,
+    GCG_CONNECT                                 = 0x00000004
+} GCG_CLKS_T;
+
+#define NB_GCG_CLK_AEN                          (3)
+#define NB_GCG_CLK_EN                           (5)
+#define NB_GCG_CLK                              (5)
+
+// ============================================================================
+// AHB1_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AHB1 side System clocks
+    AHB1_USBC                                   = 0x00000000,
+/// the following don't have an auto enable
+    AHB1_ALWAYS                                 = 0x00000001,
+    AHB1_SPIFLASH                               = 0x00000002
+} AHB1_CLKS_T;
+
+#define NB_AHB1_CLK_AEN                         (1)
+#define NB_AHB1_CLK_EN                          (3)
+#define NB_AHB1_CLK                             (3)
+
+// ============================================================================
+// APB1_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP APB1 side System clocks
+    APB1_CONF                                   = 0x00000000,
+    APB1_AIF                                    = 0x00000001,
+    APB1_AIF2                                   = 0x00000002,
+    APB1_AUIFC                                  = 0x00000003,
+    APB1_AUIFC_CH0                              = 0x00000004,
+    APB1_AUIFC_CH1                              = 0x00000005,
+    APB1_AUIFC_CH2                              = 0x00000006,
+    APB1_AUIFC_CH3                              = 0x00000007,
+    APB1_I2C1                                   = 0x00000008,
+    APB1_I2C2                                   = 0x00000009,
+    APB1_I2C3                                   = 0x0000000A,
+/// AP APB1 side divided clock (either divided by module or by clock_ctrl)
+    APB1D_OSC                                   = 0x0000000B,
+    APB1D_PWM                                   = 0x0000000C,
+/// the following don't have an auto enable
+    APB1_ALWAYS                                 = 0x0000000D,
+    APB1_DAPLITE                                = 0x0000000E,
+    APB1_TIMER                                  = 0x0000000F,
+    APB1_GPIO                                   = 0x00000010
+} APB1_CLKS_T;
+
+#define NB_APB1_CLK_AEN                         (13)
+#define NB_APB1_CLK_EN                          (17)
+#define NB_APB1_CLK                             (17)
+
+// ============================================================================
+// APB2_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP APB2 side System clocks
+    APB2_CONF                                   = 0x00000000,
+    APB2_IFC                                    = 0x00000001,
+    APB2_IFC_CH0                                = 0x00000002,
+    APB2_IFC_CH1                                = 0x00000003,
+    APB2_IFC_CH2                                = 0x00000004,
+    APB2_IFC_CH3                                = 0x00000005,
+    APB2_IFC_CH4                                = 0x00000006,
+    APB2_IFC_CH5                                = 0x00000007,
+    APB2_IFC_CH6                                = 0x00000008,
+    APB2_IFC_CH7                                = 0x00000009,
+    APB2_UART1                                  = 0x0000000A,
+    APB2_UART2                                  = 0x0000000B,
+    APB2_UART3                                  = 0x0000000C,
+    APB2_SPI1                                   = 0x0000000D,
+    APB2_SPI2                                   = 0x0000000E,
+    APB2_SPI3                                   = 0x0000000F,
+    APB2_SDMMC1                                 = 0x00000010,
+    APB2_SDMMC2                                 = 0x00000011,
+    APB2_SDMMC3                                 = 0x00000012,
+/// the following don't have an auto enable
+    APB2_ALWAYS                                 = 0x00000013,
+    APB2_NANDFLASH                              = 0x00000014
+} APB2_CLKS_T;
+
+#define NB_APB2_CLK_AEN                         (19)
+#define NB_APB2_CLK_EN                          (21)
+#define NB_APB2_CLK                             (21)
+
+// ============================================================================
+// MEM_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP MEM side System clocks
+    MEM_CONF                                    = 0x00000000,
+/// the following don't have an auto enable
+    MEM_DMC                                     = 0x00000001,
+    MEM_GPU                                     = 0x00000002,
+    MEM_VPU                                     = 0x00000003,
+    MEM_DDRPHY_P                                = 0x00000004,
+    MEM_CONNECT                                 = 0x00000005
+} MEM_CLKS_T;
+
+#define NB_MEM_CLK_AEN                          (1)
+#define NB_MEM_CLK_EN                           (6)
+#define NB_MEM_CLK                              (6)
+
+// ============================================================================
+// APO_CLKS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP side Other clocks
+/// clocks with auto enble
+    APOC_VPU                                    = 0x00000000,
+    APOC_BCK                                    = 0x00000001,
+    APOC_BCK2                                   = 0x00000002,
+    APOC_UART1                                  = 0x00000003,
+    APOC_UART2                                  = 0x00000004,
+    APOC_UART3                                  = 0x00000005,
+    APOC_VOC_CORE                               = 0x00000006,
+    APOC_VOC2_CORE                              = 0x00000007,
+    APOC_VOC                                    = 0x00000008,
+    APOC_VOC2                                   = 0x00000009,
+/// the following don't have an auto enable
+    APOC_VOC_ALWAYS                             = 0x0000000A,
+    APOC_VOC2_ALWAYS                            = 0x0000000B,
+    APOC_DDRPHY_N                               = 0x0000000C,
+    APOC_DDRPHY2XP                              = 0x0000000D,
+    APOC_DDRPHY2XN                              = 0x0000000E,
+    APOC_GPU                                    = 0x0000000F,
+    APOC_USBPHY                                 = 0x00000010,
+    APOC_CSI                                    = 0x00000011,
+    APOC_DSI                                    = 0x00000012,
+    APOC_GPIO                                   = 0x00000013,
+    APOC_SPIFLASH                               = 0x00000014,
+    APOC_PIX                                    = 0x00000015,
+    APOC_PDGB                                   = 0x00000016
+} APO_CLKS_T;
+
+#define NB_CLK_VOC_AEN_SYNC                     (6)
+#define NB_CLK_VOC_CORE                         (8)
+#define NB_APO_CLK_AEN                          (10)
+#define NB_CLK_VOC_END                          (12)
+#define NB_APO_CLK_EN                           (23)
+#define NB_APO_CLK                              (23)
+
+// ============================================================================
+// CPU_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP CPU side resets
+    CPU_RST_CORE                                = 0x00000000,
+    CPU_RST_SYS                                 = 0x00000001
+} CPU_RESETS_T;
+
+#define NB_CPU_RST                              (2)
+
+// ============================================================================
+// AXI_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AXI side resets: AXI and AHB0 and APB0
+    AXI_RST_VOC                                 = 0x00000000,
+    AXI_RST_VOC2                                = 0x00000001,
+    AXI_RST_DMA                                 = 0x00000002,
+    AXI_RST_SYS                                 = 0x00000003,
+    AXI_RST_CONNECT                             = 0x00000004,
+    AHB0_RST_GPU                                = 0x00000005,
+    APB0_RST_VPU                                = 0x00000006,
+    APB0_RST_IRQ                                = 0x00000007
+} AXI_RESETS_T;
+
+#define NB_AXI_RST                              (8)
+
+// ============================================================================
+// AXIDIV2_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AXIDIV2 side resets
+    AXIDIV2_RST_IMEM                            = 0x00000000,
+    AXIDIV2_RST_SYS                             = 0x00000001,
+    AXIDIV2_RST_VPU                             = 0x00000002
+} AXIDIV2_RESETS_T;
+
+#define NB_AXIDIV2_RST                          (3)
+
+// ============================================================================
+// GCG_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP GCG side resets
+    GCG_RST_SYS                                 = 0x00000000,
+    GCG_RST_GOUDA                               = 0x00000001,
+    GCG_RST_CAMERA                              = 0x00000002
+} GCG_RESETS_T;
+
+#define NB_GCG_RST                              (3)
+
+// ============================================================================
+// AHB1_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP AHB1 side resets
+    AHB1_RST_SYS                                = 0x00000000,
+    AHB1_RST_USBC                               = 0x00000001,
+    AHB1_RST_SPIFLASH                           = 0x00000002
+} AHB1_RESETS_T;
+
+#define NB_AHB1_RST                             (3)
+
+// ============================================================================
+// APB1_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP APB1 side resets
+    APB1_RST_SYS                                = 0x00000000,
+    APB1_RST_TIMER                              = 0x00000001,
+    APB1_RST_KEYPAD                             = 0x00000002,
+    APB1_RST_GPIO                               = 0x00000003,
+    APB1_RST_PWM                                = 0x00000004,
+    APB1_RST_AIF                                = 0x00000005,
+    APB1_RST_AIF2                               = 0x00000006,
+    APB1_RST_AUIFC                              = 0x00000007,
+    APB1_RST_I2C1                               = 0x00000008,
+    APB1_RST_I2C2                               = 0x00000009,
+    APB1_RST_I2C3                               = 0x0000000A,
+    APB1_RST_COM_REGS                           = 0x0000000B,
+    APB1_RST_DMC                                = 0x0000000C,
+    APB1_RST_DDRPHY_P                           = 0x0000000D,
+    APB1_RST_BB2G_XCPU                          = 0x0000000E,
+    APB1_RST_BB2G_BCPU                          = 0x0000000F,
+    APB1_RST_BB2G_AHBC                          = 0x00000010,
+    APB1_RST_BB2G_DMA                           = 0x00000011,
+    APB1_RST_BB2G_A2A                           = 0x00000012,
+    APB1_RST_BB2G_XIFC                          = 0x00000013,
+    APB1_RST_BB2G_BIFC                          = 0x00000014,
+    APB1_RST_BB2G_BAHBC                         = 0x00000015,
+    APB1_RST_BB2G_MEM_BRIDGE                    = 0x00000016
+} APB1_RESETS_T;
+
+#define NB_APB1_RST                             (23)
+
+// ============================================================================
+// APB2_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP APB2 side resets
+    APB2_RST_SYS                                = 0x00000000,
+    APB2_RST_IFC                                = 0x00000001,
+    APB2_RST_UART1                              = 0x00000002,
+    APB2_RST_UART2                              = 0x00000003,
+    APB2_RST_UART3                              = 0x00000004,
+    APB2_RST_SPI1                               = 0x00000005,
+    APB2_RST_SPI2                               = 0x00000006,
+    APB2_RST_SPI3                               = 0x00000007,
+    APB2_RST_SDMMC1                             = 0x00000008,
+    APB2_RST_SDMMC2                             = 0x00000009,
+    APB2_RST_SDMMC3                             = 0x0000000A,
+    APB2_RST_NANDFLASH                          = 0x0000000B
+} APB2_RESETS_T;
+
+#define NB_APB2_RST                             (12)
+
+// ============================================================================
+// MEM_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP MEM side resets
+    MEM_RST_SYS                                 = 0x00000000,
+    MEM_RST_GPU                                 = 0x00000001,
+    MEM_RST_VPU                                 = 0x00000002,
+    MEM_RST_DMC                                 = 0x00000003,
+    MEM_RST_DDRPHY_P                            = 0x00000004
+} MEM_RESETS_T;
+
+#define NB_MEM_RST                              (5)
+
+// ============================================================================
+// AP_OTHERS_RESETS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef enum
+{
+/// AP Reset Other : resync on corresponding clock other
+    AP_RSTO_VOC                                 = 0x00000000,
+    AP_RSTO_VOC2                                = 0x00000001,
+    AP_RSTO_DDRPHY_N                            = 0x00000002,
+    AP_RSTO_DDRPHY2XP                           = 0x00000003,
+    AP_RSTO_DDRPHY2XN                           = 0x00000004,
+    AP_RSTO_GPU                                 = 0x00000005,
+    AP_RSTO_VPU                                 = 0x00000006,
+    AP_RSTO_BCK                                 = 0x00000007,
+    AP_RSTO_BCK2                                = 0x00000008,
+    AP_RSTO_UART1                               = 0x00000009,
+    AP_RSTO_UART2                               = 0x0000000A,
+    AP_RSTO_UART3                               = 0x0000000B,
+    AP_RSTO_GPIO                                = 0x0000000C,
+    AP_RSTO_TIMER                               = 0x0000000D,
+    AP_RSTO_USBC                                = 0x0000000E,
+    AP_RSTO_DSI                                 = 0x0000000F,
+    AP_RSTO_SPIFLASH                            = 0x00000010,
+    AP_RSTO_TCK                                 = 0x00000011,
+    AP_RSTO_PDBG_XTAL                           = 0x00000012
+} AP_OTHERS_RESETS_T;
+
+#define NB_AP_RSTO                              (19)
+/// For REG_DBG protect lock/unlock value
+#define AP_CTRL_PROTECT_LOCK                    (0XA50000)
+#define AP_CTRL_PROTECT_UNLOCK                  (0XA50001)
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+// ============================================================================
+// SYS_CTRL_AP_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef volatile struct
+{
+    /// <strong>This register is used to Lock and Unlock the protected registers.</strong>
+    REG32                          REG_DBG;                      //0x00000000
+    /// Register protected by Write_Unlocked_H.
+    REG32                          Cfg_Pll_Ctrl[4];              //0x00000004
+    /// This register is protected.
+    REG32                          Sel_Clock;                    //0x00000014
+    REG32                          Reset_Cause;                  //0x00000018
+    /// This register is protected.
+    REG32                          CPU_Rst_Set;                  //0x0000001C
+    REG32                          CPU_Rst_Clr;                  //0x00000020
+    /// This register is protected.
+    REG32                          AXI_Rst_Set;                  //0x00000024
+    REG32                          AXI_Rst_Clr;                  //0x00000028
+    /// This register is protected.
+    REG32                          AXIDIV2_Rst_Set;              //0x0000002C
+    REG32                          AXIDIV2_Rst_Clr;              //0x00000030
+    /// This register is protected.
+    REG32                          GCG_Rst_Set;                  //0x00000034
+    REG32                          GCG_Rst_Clr;                  //0x00000038
+    /// This register is protected.
+    REG32                          AHB1_Rst_Set;                 //0x0000003C
+    REG32                          AHB1_Rst_Clr;                 //0x00000040
+    /// This register is protected.
+    REG32                          APB1_Rst_Set;                 //0x00000044
+    REG32                          APB1_Rst_Clr;                 //0x00000048
+    /// This register is protected.
+    REG32                          APB2_Rst_Set;                 //0x0000004C
+    REG32                          APB2_Rst_Clr;                 //0x00000050
+    /// This register is protected.
+    REG32                          MEM_Rst_Set;                  //0x00000054
+    REG32                          MEM_Rst_Clr;                  //0x00000058
+    REG32                          Clk_CPU_Mode;                 //0x0000005C
+    REG32                          Clk_CPU_Enable;               //0x00000060
+    /// This register is protected.
+    REG32                          Clk_CPU_Disable;              //0x00000064
+    REG32                          Clk_AXI_Mode;                 //0x00000068
+    REG32                          Clk_AXI_Enable;               //0x0000006C
+    /// This register is protected.
+    REG32                          Clk_AXI_Disable;              //0x00000070
+    REG32                          Clk_AXIDIV2_Mode;             //0x00000074
+    REG32                          Clk_AXIDIV2_Enable;           //0x00000078
+    /// This register is protected.
+    REG32                          Clk_AXIDIV2_Disable;          //0x0000007C
+    REG32                          Clk_GCG_Mode;                 //0x00000080
+    REG32                          Clk_GCG_Enable;               //0x00000084
+    /// This register is protected.
+    REG32                          Clk_GCG_Disable;              //0x00000088
+    REG32                          Clk_AHB1_Mode;                //0x0000008C
+    REG32                          Clk_AHB1_Enable;              //0x00000090
+    /// This register is protected.
+    REG32                          Clk_AHB1_Disable;             //0x00000094
+    REG32                          Clk_APB1_Mode;                //0x00000098
+    REG32                          Clk_APB1_Enable;              //0x0000009C
+    /// This register is protected.
+    REG32                          Clk_APB1_Disable;             //0x000000A0
+    REG32                          Clk_APB2_Mode;                //0x000000A4
+    REG32                          Clk_APB2_Enable;              //0x000000A8
+    /// This register is protected.
+    REG32                          Clk_APB2_Disable;             //0x000000AC
+    REG32                          Clk_MEM_Mode;                 //0x000000B0
+    REG32                          Clk_MEM_Enable;               //0x000000B4
+    /// This register is protected.
+    REG32                          Clk_MEM_Disable;              //0x000000B8
+    REG32                          Clk_APO_Mode;                 //0x000000BC
+    REG32                          Clk_APO_Enable;               //0x000000C0
+    /// This register is protected.
+    REG32                          Clk_APO_Disable;              //0x000000C4
+    REG32                          Cfg_Clk_AP_CPU;               //0x000000C8
+    REG32                          Cfg_Clk_AP_AXI;               //0x000000CC
+    REG32                          Cfg_Clk_AP_GCG;               //0x000000D0
+    REG32                          Cfg_Clk_AP_AHB1;              //0x000000D4
+    REG32                          Cfg_Clk_AP_APB1;              //0x000000D8
+    REG32                          Cfg_Clk_AP_APB2;              //0x000000DC
+    REG32                          Cfg_Clk_AP_MEM;               //0x000000E0
+    REG32                          Cfg_Clk_AP_GPU;               //0x000000E4
+    REG32                          Cfg_Clk_AP_VPU;               //0x000000E8
+    REG32                          Cfg_Clk_AP_VOC;               //0x000000EC
+    REG32                          Cfg_Clk_AP_SFLSH;             //0x000000F0
+    REG32                          Cfg_Clk_Uart[3];              //0x000000F4
+    REG32                          L2cc_Ctrl;                    //0x00000100
+    REG32                          Spi_Ctrl;                     //0x00000104
+    REG32                          Memory_Margin;                //0x00000108
+    REG32                          Memory_Margin2;               //0x0000010C
+    REG32                          Memory_Observe;               //0x00000110
+    REG32                          Cfg_Clk_AP_VOC2;              //0x00000114
+    REG32 Reserved_00000118[57];                //0x00000118
+    /// This register is reserved.
+    REG32                          Cfg_Reserve;                  //0x000001FC
+} HWP_SYS_CTRL_AP_T;
+
+#define hwp_sysCtrlAp              ((HWP_SYS_CTRL_AP_T*)(RDA_SYSCTRL_BASE))
+
+
+//REG_DBG
+#define SYS_CTRL_AP_SCRATCH(n)     (((n)&0xFFFF)<<0)
+#define SYS_CTRL_AP_WRITE_UNLOCK_STATUS (1<<30)
+#define SYS_CTRL_AP_WRITE_UNLOCK   (1<<31)
+
+//Cfg_Pll_Ctrl
+#define SYS_CTRL_AP_AP_PLL_ENABLE  (1<<0)
+#define SYS_CTRL_AP_AP_PLL_ENABLE_MASK (1<<0)
+#define SYS_CTRL_AP_AP_PLL_ENABLE_SHIFT (0)
+#define SYS_CTRL_AP_AP_PLL_ENABLE_POWER_DOWN (0<<0)
+#define SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE (1<<0)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET (1<<4)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_MASK (1<<4)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_SHIFT (4)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_RESET (0<<4)
+#define SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET (1<<4)
+#define SYS_CTRL_AP_AP_PLL_BYPASS  (1<<8)
+#define SYS_CTRL_AP_AP_PLL_BYPASS_MASK (1<<8)
+#define SYS_CTRL_AP_AP_PLL_BYPASS_SHIFT (8)
+#define SYS_CTRL_AP_AP_PLL_BYPASS_PASS (0<<8)
+#define SYS_CTRL_AP_AP_PLL_BYPASS_BYPASS (1<<8)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE (1<<12)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_MASK (1<<12)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_SHIFT (12)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_ENABLE (1<<12)
+#define SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_DISABLE (0<<12)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(n) (((n)&31)<<16)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW_MASK (31<<16)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW_SHIFT (16)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(n) (((n)&31)<<24)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH_MASK (31<<24)
+#define SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH_SHIFT (24)
+#define SYS_CTRL_AP_PLL_AP_CFG(n)  (((n)&0x1F1F1111)<<0)
+#define SYS_CTRL_AP_PLL_AP_CFG_MASK (0x1F1F1111<<0)
+#define SYS_CTRL_AP_PLL_AP_CFG_SHIFT (0)
+
+//Sel_Clock
+#define SYS_CTRL_AP_SLOW_SEL_RF_OSCILLATOR (1<<0)
+#define SYS_CTRL_AP_SLOW_SEL_RF_RF (0<<0)
+#define SYS_CTRL_AP_CPU_SEL_FAST_SLOW (1<<4)
+#define SYS_CTRL_AP_CPU_SEL_FAST_FAST (0<<4)
+#define SYS_CTRL_AP_BUS_SEL_FAST_SLOW (1<<5)
+#define SYS_CTRL_AP_BUS_SEL_FAST_FAST (0<<5)
+#define SYS_CTRL_AP_TIMER_SEL_FAST_SLOW (1<<7)
+#define SYS_CTRL_AP_TIMER_SEL_FAST_FAST (0<<7)
+#define SYS_CTRL_AP_RF_DETECTED_OK (1<<8)
+#define SYS_CTRL_AP_RF_DETECTED_NO (0<<8)
+#define SYS_CTRL_AP_RF_DETECT_BYPASS (1<<9)
+#define SYS_CTRL_AP_RF_DETECT_RESET (1<<10)
+#define SYS_CTRL_AP_RF_SELECTED_L  (1<<11)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU (1<<12)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU_MASK (1<<12)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU_SHIFT (12)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU_LOCKED (1<<12)
+#define SYS_CTRL_AP_PLL_LOCKED_CPU_NOT_LOCKED (0<<12)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS (1<<13)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS_MASK (1<<13)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS_SHIFT (13)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS_LOCKED (1<<13)
+#define SYS_CTRL_AP_PLL_LOCKED_BUS_NOT_LOCKED (0<<13)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM (1<<14)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM_MASK (1<<14)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM_SHIFT (14)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM_LOCKED (1<<14)
+#define SYS_CTRL_AP_PLL_LOCKED_MEM_NOT_LOCKED (0<<14)
+#define SYS_CTRL_AP_PLL_LOCKED_USB (1<<15)
+#define SYS_CTRL_AP_PLL_LOCKED_USB_MASK (1<<15)
+#define SYS_CTRL_AP_PLL_LOCKED_USB_SHIFT (15)
+#define SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED (1<<15)
+#define SYS_CTRL_AP_PLL_LOCKED_USB_NOT_LOCKED (0<<15)
+#define SYS_CTRL_AP_PLL_BYPASS_LOCK_CPU (1<<20)
+#define SYS_CTRL_AP_PLL_BYPASS_LOCK_BUS (1<<21)
+#define SYS_CTRL_AP_FAST_SELECTED_CPU_L (1<<30)
+#define SYS_CTRL_AP_FAST_SELECTED_CPU_L_MASK (1<<30)
+#define SYS_CTRL_AP_FAST_SELECTED_CPU_L_SHIFT (30)
+#define SYS_CTRL_AP_FAST_SELECTED_BUS_L (1<<31)
+#define SYS_CTRL_AP_FAST_SELECTED_BUS_L_MASK (1<<31)
+#define SYS_CTRL_AP_FAST_SELECTED_BUS_L_SHIFT (31)
+
+//Reset_Cause
+#define SYS_CTRL_AP_WATCHDOG_RESET_HAPPENED (1<<0)
+#define SYS_CTRL_AP_WATCHDOG_RESET_NO (0<<0)
+#define SYS_CTRL_AP_GLOBALSOFT_RESET_HAPPENED (1<<4)
+#define SYS_CTRL_AP_GLOBALSOFT_RESET_NO (0<<4)
+#define SYS_CTRL_AP_HOSTDEBUG_RESET_HAPPENED (1<<5)
+#define SYS_CTRL_AP_HOSTDEBUG_RESET_NO (0<<5)
+#define SYS_CTRL_AP_ALARMCAUSE_HAPPENED (1<<6)
+#define SYS_CTRL_AP_ALARMCAUSE_NO  (0<<6)
+#define SYS_CTRL_AP_BOOT_MODE(n)   (((n)&0xFFFF)<<8)
+#define SYS_CTRL_AP_BOOT_MODE_MASK (0xFFFF<<8)
+#define SYS_CTRL_AP_BOOT_MODE_SHIFT (8)
+#define SYS_CTRL_AP_SW_BOOT_MODE(n) (((n)&0x7F)<<24)
+#define SYS_CTRL_AP_SW_BOOT_MODE_MASK (0x7F<<24)
+#define SYS_CTRL_AP_SW_BOOT_MODE_SHIFT (24)
+#define SYS_CTRL_AP_FONCTIONAL_TEST_MODE (1<<31)
+
+//CPU_Rst_Set
+#define SYS_CTRL_AP_SET_CPU_RST_CORE (1<<0)
+#define SYS_CTRL_AP_SET_CPU_RST_SYS (1<<1)
+#define SYS_CTRL_AP_SOFT_RST       (1<<31)
+#define SYS_CTRL_AP_SET_CPU_RST(n) (((n)&3)<<0)
+#define SYS_CTRL_AP_SET_CPU_RST_MASK (3<<0)
+#define SYS_CTRL_AP_SET_CPU_RST_SHIFT (0)
+
+//CPU_Rst_Clr
+#define SYS_CTRL_AP_CLR_CPU_RST_CORE (1<<0)
+#define SYS_CTRL_AP_CLR_CPU_RST_SYS (1<<1)
+#define SYS_CTRL_AP_CLR_CPU_RST(n) (((n)&3)<<0)
+#define SYS_CTRL_AP_CLR_CPU_RST_MASK (3<<0)
+#define SYS_CTRL_AP_CLR_CPU_RST_SHIFT (0)
+
+//AXI_Rst_Set
+#define SYS_CTRL_AP_SET_AXI_RST_VOC (1<<0)
+#define SYS_CTRL_AP_SET_AXI_RST_VOC2 (1<<1)
+#define SYS_CTRL_AP_SET_AXI_RST_DMA (1<<2)
+#define SYS_CTRL_AP_SET_AXI_RST_SYS (1<<3)
+#define SYS_CTRL_AP_SET_AXI_RST_CONNECT (1<<4)
+#define SYS_CTRL_AP_SET_AHB0_RST_GPU (1<<5)
+#define SYS_CTRL_AP_SET_APB0_RST_VPU (1<<6)
+#define SYS_CTRL_AP_SET_APB0_RST_IRQ (1<<7)
+#define SYS_CTRL_AP_SET_AXI_RST(n) (((n)&0xFF)<<0)
+#define SYS_CTRL_AP_SET_AXI_RST_MASK (0xFF<<0)
+#define SYS_CTRL_AP_SET_AXI_RST_SHIFT (0)
+
+//AXI_Rst_Clr
+#define SYS_CTRL_AP_CLR_AXI_RST_VOC (1<<0)
+#define SYS_CTRL_AP_CLR_AXI_RST_VOC2 (1<<1)
+#define SYS_CTRL_AP_CLR_AXI_RST_DMA (1<<2)
+#define SYS_CTRL_AP_CLR_AXI_RST_SYS (1<<3)
+#define SYS_CTRL_AP_CLR_AXI_RST_CONNECT (1<<4)
+#define SYS_CTRL_AP_CLR_AHB0_RST_GPU (1<<5)
+#define SYS_CTRL_AP_CLR_APB0_RST_VPU (1<<6)
+#define SYS_CTRL_AP_CLR_APB0_RST_IRQ (1<<7)
+#define SYS_CTRL_AP_CLR_AXI_RST(n) (((n)&0xFF)<<0)
+#define SYS_CTRL_AP_CLR_AXI_RST_MASK (0xFF<<0)
+#define SYS_CTRL_AP_CLR_AXI_RST_SHIFT (0)
+
+//AXIDIV2_Rst_Set
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_IMEM (1<<0)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_SYS (1<<1)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_VPU (1<<2)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_MASK (7<<0)
+#define SYS_CTRL_AP_SET_AXIDIV2_RST_SHIFT (0)
+
+//AXIDIV2_Rst_Clr
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_IMEM (1<<0)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_SYS (1<<1)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_VPU (1<<2)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_MASK (7<<0)
+#define SYS_CTRL_AP_CLR_AXIDIV2_RST_SHIFT (0)
+
+//GCG_Rst_Set
+#define SYS_CTRL_AP_SET_GCG_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_GCG_RST_GOUDA (1<<1)
+#define SYS_CTRL_AP_SET_GCG_RST_CAMERA (1<<2)
+#define SYS_CTRL_AP_SET_GCG_RST(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_SET_GCG_RST_MASK (7<<0)
+#define SYS_CTRL_AP_SET_GCG_RST_SHIFT (0)
+
+//GCG_Rst_Clr
+#define SYS_CTRL_AP_CLR_GCG_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_GCG_RST_GOUDA (1<<1)
+#define SYS_CTRL_AP_CLR_GCG_RST_CAMERA (1<<2)
+#define SYS_CTRL_AP_CLR_GCG_RST(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_CLR_GCG_RST_MASK (7<<0)
+#define SYS_CTRL_AP_CLR_GCG_RST_SHIFT (0)
+
+//AHB1_Rst_Set
+#define SYS_CTRL_AP_SET_AHB1_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_AHB1_RST_USBC (1<<1)
+#define SYS_CTRL_AP_SET_AHB1_RST_SPIFLASH (1<<2)
+#define SYS_CTRL_AP_SET_AHB1_RST(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_SET_AHB1_RST_MASK (7<<0)
+#define SYS_CTRL_AP_SET_AHB1_RST_SHIFT (0)
+
+//AHB1_Rst_Clr
+#define SYS_CTRL_AP_CLR_AHB1_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_AHB1_RST_USBC (1<<1)
+#define SYS_CTRL_AP_CLR_AHB1_RST_SPIFLASH (1<<2)
+#define SYS_CTRL_AP_CLR_AHB1_RST(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_CLR_AHB1_RST_MASK (7<<0)
+#define SYS_CTRL_AP_CLR_AHB1_RST_SHIFT (0)
+
+//APB1_Rst_Set
+#define SYS_CTRL_AP_SET_APB1_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_APB1_RST_TIMER (1<<1)
+#define SYS_CTRL_AP_SET_APB1_RST_KEYPAD (1<<2)
+#define SYS_CTRL_AP_SET_APB1_RST_GPIO (1<<3)
+#define SYS_CTRL_AP_SET_APB1_RST_PWM (1<<4)
+#define SYS_CTRL_AP_SET_APB1_RST_AIF (1<<5)
+#define SYS_CTRL_AP_SET_APB1_RST_AIF2 (1<<6)
+#define SYS_CTRL_AP_SET_APB1_RST_AUIFC (1<<7)
+#define SYS_CTRL_AP_SET_APB1_RST_I2C1 (1<<8)
+#define SYS_CTRL_AP_SET_APB1_RST_I2C2 (1<<9)
+#define SYS_CTRL_AP_SET_APB1_RST_I2C3 (1<<10)
+#define SYS_CTRL_AP_SET_APB1_RST_COM_REGS (1<<11)
+#define SYS_CTRL_AP_SET_APB1_RST_DMC (1<<12)
+#define SYS_CTRL_AP_SET_APB1_RST_DDRPHY_P (1<<13)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_XCPU (1<<14)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BCPU (1<<15)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_AHBC (1<<16)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_DMA (1<<17)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_A2A (1<<18)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_XIFC (1<<19)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BIFC (1<<20)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_BAHBC (1<<21)
+#define SYS_CTRL_AP_SET_APB1_RST_BB2G_MEM_BRIDGE (1<<22)
+#define SYS_CTRL_AP_SET_APB1_RST(n) (((n)&0x7FFFFF)<<0)
+#define SYS_CTRL_AP_SET_APB1_RST_MASK (0x7FFFFF<<0)
+#define SYS_CTRL_AP_SET_APB1_RST_SHIFT (0)
+
+//APB1_Rst_Clr
+#define SYS_CTRL_AP_CLR_APB1_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_APB1_RST_TIMER (1<<1)
+#define SYS_CTRL_AP_CLR_APB1_RST_KEYPAD (1<<2)
+#define SYS_CTRL_AP_CLR_APB1_RST_GPIO (1<<3)
+#define SYS_CTRL_AP_CLR_APB1_RST_PWM (1<<4)
+#define SYS_CTRL_AP_CLR_APB1_RST_AIF (1<<5)
+#define SYS_CTRL_AP_CLR_APB1_RST_AIF2 (1<<6)
+#define SYS_CTRL_AP_CLR_APB1_RST_AUIFC (1<<7)
+#define SYS_CTRL_AP_CLR_APB1_RST_I2C1 (1<<8)
+#define SYS_CTRL_AP_CLR_APB1_RST_I2C2 (1<<9)
+#define SYS_CTRL_AP_CLR_APB1_RST_I2C3 (1<<10)
+#define SYS_CTRL_AP_CLR_APB1_RST_COM_REGS (1<<11)
+#define SYS_CTRL_AP_CLR_APB1_RST_DMC (1<<12)
+#define SYS_CTRL_AP_CLR_APB1_RST_DDRPHY_P (1<<13)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_XCPU (1<<14)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BCPU (1<<15)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_AHBC (1<<16)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_DMA (1<<17)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_A2A (1<<18)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_XIFC (1<<19)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BIFC (1<<20)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_BAHBC (1<<21)
+#define SYS_CTRL_AP_CLR_APB1_RST_BB2G_MEM_BRIDGE (1<<22)
+#define SYS_CTRL_AP_CLR_APB1_RST(n) (((n)&0x7FFFFF)<<0)
+#define SYS_CTRL_AP_CLR_APB1_RST_MASK (0x7FFFFF<<0)
+#define SYS_CTRL_AP_CLR_APB1_RST_SHIFT (0)
+
+//APB2_Rst_Set
+#define SYS_CTRL_AP_SET_APB2_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_APB2_RST_IFC (1<<1)
+#define SYS_CTRL_AP_SET_APB2_RST_UART1 (1<<2)
+#define SYS_CTRL_AP_SET_APB2_RST_UART2 (1<<3)
+#define SYS_CTRL_AP_SET_APB2_RST_UART3 (1<<4)
+#define SYS_CTRL_AP_SET_APB2_RST_SPI1 (1<<5)
+#define SYS_CTRL_AP_SET_APB2_RST_SPI2 (1<<6)
+#define SYS_CTRL_AP_SET_APB2_RST_SPI3 (1<<7)
+#define SYS_CTRL_AP_SET_APB2_RST_SDMMC1 (1<<8)
+#define SYS_CTRL_AP_SET_APB2_RST_SDMMC2 (1<<9)
+#define SYS_CTRL_AP_SET_APB2_RST_SDMMC3 (1<<10)
+#define SYS_CTRL_AP_SET_APB2_RST_NANDFLASH (1<<11)
+#define SYS_CTRL_AP_SET_APB2_RST(n) (((n)&0xFFF)<<0)
+#define SYS_CTRL_AP_SET_APB2_RST_MASK (0xFFF<<0)
+#define SYS_CTRL_AP_SET_APB2_RST_SHIFT (0)
+
+//APB2_Rst_Clr
+#define SYS_CTRL_AP_CLR_APB2_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_APB2_RST_IFC (1<<1)
+#define SYS_CTRL_AP_CLR_APB2_RST_UART1 (1<<2)
+#define SYS_CTRL_AP_CLR_APB2_RST_UART2 (1<<3)
+#define SYS_CTRL_AP_CLR_APB2_RST_UART3 (1<<4)
+#define SYS_CTRL_AP_CLR_APB2_RST_SPI1 (1<<5)
+#define SYS_CTRL_AP_CLR_APB2_RST_SPI2 (1<<6)
+#define SYS_CTRL_AP_CLR_APB2_RST_SPI3 (1<<7)
+#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC1 (1<<8)
+#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC2 (1<<9)
+#define SYS_CTRL_AP_CLR_APB2_RST_SDMMC3 (1<<10)
+#define SYS_CTRL_AP_CLR_APB2_RST_NANDFLASH (1<<11)
+#define SYS_CTRL_AP_CLR_APB2_RST(n) (((n)&0xFFF)<<0)
+#define SYS_CTRL_AP_CLR_APB2_RST_MASK (0xFFF<<0)
+#define SYS_CTRL_AP_CLR_APB2_RST_SHIFT (0)
+
+//MEM_Rst_Set
+#define SYS_CTRL_AP_SET_MEM_RST_SYS (1<<0)
+#define SYS_CTRL_AP_SET_MEM_RST_GPU (1<<1)
+#define SYS_CTRL_AP_SET_MEM_RST_VPU (1<<2)
+#define SYS_CTRL_AP_SET_MEM_RST_DMC (1<<3)
+#define SYS_CTRL_AP_SET_MEM_RST_DDRPHY_P (1<<4)
+#define SYS_CTRL_AP_SET_MEM_RST(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_SET_MEM_RST_MASK (31<<0)
+#define SYS_CTRL_AP_SET_MEM_RST_SHIFT (0)
+
+//MEM_Rst_Clr
+#define SYS_CTRL_AP_CLR_MEM_RST_SYS (1<<0)
+#define SYS_CTRL_AP_CLR_MEM_RST_GPU (1<<1)
+#define SYS_CTRL_AP_CLR_MEM_RST_VPU (1<<2)
+#define SYS_CTRL_AP_CLR_MEM_RST_DMC (1<<3)
+#define SYS_CTRL_AP_CLR_MEM_RST_DDRPHY_P (1<<4)
+#define SYS_CTRL_AP_CLR_MEM_RST(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_CLR_MEM_RST_MASK (31<<0)
+#define SYS_CTRL_AP_CLR_MEM_RST_SHIFT (0)
+
+//Clk_CPU_Mode
+#define SYS_CTRL_AP_MODE_CLK_CPU_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_CLK_CPU_MANUAL (1<<0)
+
+//Clk_CPU_Enable
+#define SYS_CTRL_AP_ENABLE_CPU_CORE (1<<0)
+#define SYS_CTRL_AP_ENABLE_CPU_DUMMY (1<<1)
+#define SYS_CTRL_AP_ENABLE_CLK_CPU(n) (((n)&3)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_CPU_MASK (3<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_CPU_SHIFT (0)
+
+//Clk_CPU_Disable
+#define SYS_CTRL_AP_DISABLE_CPU_CORE (1<<0)
+#define SYS_CTRL_AP_DISABLE_CPU_DUMMY (1<<1)
+#define SYS_CTRL_AP_DISABLE_CLK_CPU(n) (((n)&3)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_CPU_MASK (3<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_CPU_SHIFT (0)
+
+//Clk_AXI_Mode
+#define SYS_CTRL_AP_MODE_AHB0_CONF_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_AHB0_CONF_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_APB0_CONF_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_APB0_CONF_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_AXI_VOC_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_AXI_VOC_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_AXI_VOC2_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_AXI_VOC2_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_AXI_DMA_AUTOMATIC (0<<4)
+#define SYS_CTRL_AP_MODE_AXI_DMA_MANUAL (1<<4)
+#define SYS_CTRL_AP_MODE_CLK_AXI(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_MODE_CLK_AXI_MASK (31<<0)
+#define SYS_CTRL_AP_MODE_CLK_AXI_SHIFT (0)
+
+//Clk_AXI_Enable
+#define SYS_CTRL_AP_ENABLE_AHB0_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_APB0_CONF (1<<1)
+#define SYS_CTRL_AP_ENABLE_AXI_VOC (1<<2)
+#define SYS_CTRL_AP_ENABLE_AXI_VOC2 (1<<3)
+#define SYS_CTRL_AP_ENABLE_AXI_DMA (1<<4)
+#define SYS_CTRL_AP_ENABLE_AXI_ALWAYS (1<<5)
+#define SYS_CTRL_AP_ENABLE_AXI_CONNECT (1<<6)
+#define SYS_CTRL_AP_ENABLE_APB0_IRQ (1<<7)
+#define SYS_CTRL_AP_ENABLE_CLK_AXI(n) (((n)&0xFF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AXI_MASK (0xFF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AXI_SHIFT (0)
+
+//Clk_AXI_Disable
+#define SYS_CTRL_AP_DISABLE_AHB0_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_APB0_CONF (1<<1)
+#define SYS_CTRL_AP_DISABLE_AXI_VOC (1<<2)
+#define SYS_CTRL_AP_DISABLE_AXI_VOC2 (1<<3)
+#define SYS_CTRL_AP_DISABLE_AXI_DMA (1<<4)
+#define SYS_CTRL_AP_DISABLE_AXI_ALWAYS (1<<5)
+#define SYS_CTRL_AP_DISABLE_AXI_CONNECT (1<<6)
+#define SYS_CTRL_AP_DISABLE_APB0_IRQ (1<<7)
+#define SYS_CTRL_AP_DISABLE_CLK_AXI(n) (((n)&0xFF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AXI_MASK (0xFF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AXI_SHIFT (0)
+
+//Clk_AXIDIV2_Mode
+#define SYS_CTRL_AP_MODE_CLK_AXIDIV2_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_CLK_AXIDIV2_MANUAL (1<<0)
+
+//Clk_AXIDIV2_Enable
+#define SYS_CTRL_AP_ENABLE_AXIDIV2_IMEM (1<<0)
+#define SYS_CTRL_AP_ENABLE_AXIDIV2_ALWAYS (1<<1)
+#define SYS_CTRL_AP_ENABLE_AXIDIV2_CONNECT (1<<2)
+#define SYS_CTRL_AP_ENABLE_AXIDIV2_VPU (1<<3)
+#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2(n) (((n)&15)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2_MASK (15<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AXIDIV2_SHIFT (0)
+
+//Clk_AXIDIV2_Disable
+#define SYS_CTRL_AP_DISABLE_AXIDIV2_IMEM (1<<0)
+#define SYS_CTRL_AP_DISABLE_AXIDIV2_ALWAYS (1<<1)
+#define SYS_CTRL_AP_DISABLE_AXIDIV2_CONNECT (1<<2)
+#define SYS_CTRL_AP_DISABLE_AXIDIV2_VPU (1<<3)
+#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2(n) (((n)&15)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2_MASK (15<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AXIDIV2_SHIFT (0)
+
+//Clk_GCG_Mode
+#define SYS_CTRL_AP_MODE_GCG_APB_CONF_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_GCG_APB_CONF_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_GCG_GOUDA_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_GCG_GOUDA_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_GCG_CAMERA_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_GCG_CAMERA_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_CLK_GCG(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_MODE_CLK_GCG_MASK (7<<0)
+#define SYS_CTRL_AP_MODE_CLK_GCG_SHIFT (0)
+
+//Clk_GCG_Enable
+#define SYS_CTRL_AP_ENABLE_GCG_APB_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_GCG_GOUDA (1<<1)
+#define SYS_CTRL_AP_ENABLE_GCG_CAMERA (1<<2)
+#define SYS_CTRL_AP_ENABLE_GCG_ALWAYS (1<<3)
+#define SYS_CTRL_AP_ENABLE_GCG_CONNECT (1<<4)
+#define SYS_CTRL_AP_ENABLE_CLK_GCG(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_GCG_MASK (31<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_GCG_SHIFT (0)
+
+//Clk_GCG_Disable
+#define SYS_CTRL_AP_DISABLE_GCG_APB_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_GCG_GOUDA (1<<1)
+#define SYS_CTRL_AP_DISABLE_GCG_CAMERA (1<<2)
+#define SYS_CTRL_AP_DISABLE_GCG_ALWAYS (1<<3)
+#define SYS_CTRL_AP_DISABLE_GCG_CONNECT (1<<4)
+#define SYS_CTRL_AP_DISABLE_CLK_GCG(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_GCG_MASK (31<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_GCG_SHIFT (0)
+
+//Clk_AHB1_Mode
+#define SYS_CTRL_AP_MODE_CLK_AHB1_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_CLK_AHB1_MANUAL (1<<0)
+
+//Clk_AHB1_Enable
+#define SYS_CTRL_AP_ENABLE_AHB1_USBC (1<<0)
+#define SYS_CTRL_AP_ENABLE_AHB1_ALWAYS (1<<1)
+#define SYS_CTRL_AP_ENABLE_AHB1_SPIFLASH (1<<2)
+#define SYS_CTRL_AP_ENABLE_CLK_AHB1(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AHB1_MASK (7<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_AHB1_SHIFT (0)
+
+//Clk_AHB1_Disable
+#define SYS_CTRL_AP_DISABLE_AHB1_USBC (1<<0)
+#define SYS_CTRL_AP_DISABLE_AHB1_ALWAYS (1<<1)
+#define SYS_CTRL_AP_DISABLE_AHB1_SPIFLASH (1<<2)
+#define SYS_CTRL_AP_DISABLE_CLK_AHB1(n) (((n)&7)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AHB1_MASK (7<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_AHB1_SHIFT (0)
+
+//Clk_APB1_Mode
+#define SYS_CTRL_AP_MODE_APB1_CONF_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_APB1_CONF_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_APB1_AIF_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_APB1_AIF_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_APB1_AIF2_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_APB1_AIF2_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH0_AUTOMATIC (0<<4)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH0_MANUAL (1<<4)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH1_AUTOMATIC (0<<5)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH1_MANUAL (1<<5)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH2_AUTOMATIC (0<<6)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH2_MANUAL (1<<6)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH3_AUTOMATIC (0<<7)
+#define SYS_CTRL_AP_MODE_APB1_AUIFC_CH3_MANUAL (1<<7)
+#define SYS_CTRL_AP_MODE_APB1_I2C1_AUTOMATIC (0<<8)
+#define SYS_CTRL_AP_MODE_APB1_I2C1_MANUAL (1<<8)
+#define SYS_CTRL_AP_MODE_APB1_I2C2_AUTOMATIC (0<<9)
+#define SYS_CTRL_AP_MODE_APB1_I2C2_MANUAL (1<<9)
+#define SYS_CTRL_AP_MODE_APB1_I2C3_AUTOMATIC (0<<10)
+#define SYS_CTRL_AP_MODE_APB1_I2C3_MANUAL (1<<10)
+#define SYS_CTRL_AP_MODE_APB1D_OSC_AUTOMATIC (0<<11)
+#define SYS_CTRL_AP_MODE_APB1D_OSC_MANUAL (1<<11)
+#define SYS_CTRL_AP_MODE_APB1D_PWM_AUTOMATIC (0<<12)
+#define SYS_CTRL_AP_MODE_APB1D_PWM_MANUAL (1<<12)
+#define SYS_CTRL_AP_MODE_CLK_APB1(n) (((n)&0x1FFF)<<0)
+#define SYS_CTRL_AP_MODE_CLK_APB1_MASK (0x1FFF<<0)
+#define SYS_CTRL_AP_MODE_CLK_APB1_SHIFT (0)
+
+//Clk_APB1_Enable
+#define SYS_CTRL_AP_ENABLE_APB1_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_APB1_AIF (1<<1)
+#define SYS_CTRL_AP_ENABLE_APB1_AIF2 (1<<2)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC (1<<3)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH0 (1<<4)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH1 (1<<5)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH2 (1<<6)
+#define SYS_CTRL_AP_ENABLE_APB1_AUIFC_CH3 (1<<7)
+#define SYS_CTRL_AP_ENABLE_APB1_I2C1 (1<<8)
+#define SYS_CTRL_AP_ENABLE_APB1_I2C2 (1<<9)
+#define SYS_CTRL_AP_ENABLE_APB1_I2C3 (1<<10)
+#define SYS_CTRL_AP_ENABLE_APB1D_OSC (1<<11)
+#define SYS_CTRL_AP_ENABLE_APB1D_PWM (1<<12)
+#define SYS_CTRL_AP_ENABLE_APB1_ALWAYS (1<<13)
+#define SYS_CTRL_AP_ENABLE_APB1_DAPLITE (1<<14)
+#define SYS_CTRL_AP_ENABLE_APB1_TIMER (1<<15)
+#define SYS_CTRL_AP_ENABLE_APB1_GPIO (1<<16)
+#define SYS_CTRL_AP_ENABLE_CLK_APB1(n) (((n)&0x1FFFF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APB1_MASK (0x1FFFF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APB1_SHIFT (0)
+
+//Clk_APB1_Disable
+#define SYS_CTRL_AP_DISABLE_APB1_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_APB1_AIF (1<<1)
+#define SYS_CTRL_AP_DISABLE_APB1_AIF2 (1<<2)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC (1<<3)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH0 (1<<4)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH1 (1<<5)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH2 (1<<6)
+#define SYS_CTRL_AP_DISABLE_APB1_AUIFC_CH3 (1<<7)
+#define SYS_CTRL_AP_DISABLE_APB1_I2C1 (1<<8)
+#define SYS_CTRL_AP_DISABLE_APB1_I2C2 (1<<9)
+#define SYS_CTRL_AP_DISABLE_APB1_I2C3 (1<<10)
+#define SYS_CTRL_AP_DISABLE_APB1D_OSC (1<<11)
+#define SYS_CTRL_AP_DISABLE_APB1D_PWM (1<<12)
+#define SYS_CTRL_AP_DISABLE_APB1_ALWAYS (1<<13)
+#define SYS_CTRL_AP_DISABLE_APB1_DAPLITE (1<<14)
+#define SYS_CTRL_AP_DISABLE_APB1_TIMER (1<<15)
+#define SYS_CTRL_AP_DISABLE_APB1_GPIO (1<<16)
+#define SYS_CTRL_AP_DISABLE_CLK_APB1(n) (((n)&0x1FFFF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APB1_MASK (0x1FFFF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APB1_SHIFT (0)
+
+//Clk_APB2_Mode
+#define SYS_CTRL_AP_MODE_APB2_CONF_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_APB2_CONF_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_APB2_IFC_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_APB2_IFC_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH0_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH0_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH1_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH1_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH2_AUTOMATIC (0<<4)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH2_MANUAL (1<<4)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH3_AUTOMATIC (0<<5)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH3_MANUAL (1<<5)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH4_AUTOMATIC (0<<6)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH4_MANUAL (1<<6)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH5_AUTOMATIC (0<<7)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH5_MANUAL (1<<7)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH6_AUTOMATIC (0<<8)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH6_MANUAL (1<<8)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH7_AUTOMATIC (0<<9)
+#define SYS_CTRL_AP_MODE_APB2_IFC_CH7_MANUAL (1<<9)
+#define SYS_CTRL_AP_MODE_APB2_UART1_AUTOMATIC (0<<10)
+#define SYS_CTRL_AP_MODE_APB2_UART1_MANUAL (1<<10)
+#define SYS_CTRL_AP_MODE_APB2_UART2_AUTOMATIC (0<<11)
+#define SYS_CTRL_AP_MODE_APB2_UART2_MANUAL (1<<11)
+#define SYS_CTRL_AP_MODE_APB2_UART3_AUTOMATIC (0<<12)
+#define SYS_CTRL_AP_MODE_APB2_UART3_MANUAL (1<<12)
+#define SYS_CTRL_AP_MODE_APB2_SPI1_AUTOMATIC (0<<13)
+#define SYS_CTRL_AP_MODE_APB2_SPI1_MANUAL (1<<13)
+#define SYS_CTRL_AP_MODE_APB2_SPI2_AUTOMATIC (0<<14)
+#define SYS_CTRL_AP_MODE_APB2_SPI2_MANUAL (1<<14)
+#define SYS_CTRL_AP_MODE_APB2_SPI3_AUTOMATIC (0<<15)
+#define SYS_CTRL_AP_MODE_APB2_SPI3_MANUAL (1<<15)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC1_AUTOMATIC (0<<16)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC1_MANUAL (1<<16)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC2_AUTOMATIC (0<<17)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC2_MANUAL (1<<17)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC3_AUTOMATIC (0<<18)
+#define SYS_CTRL_AP_MODE_APB2_SDMMC3_MANUAL (1<<18)
+#define SYS_CTRL_AP_MODE_CLK_APB2(n) (((n)&0x7FFFF)<<0)
+#define SYS_CTRL_AP_MODE_CLK_APB2_MASK (0x7FFFF<<0)
+#define SYS_CTRL_AP_MODE_CLK_APB2_SHIFT (0)
+
+//Clk_APB2_Enable
+#define SYS_CTRL_AP_ENABLE_APB2_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC (1<<1)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH0 (1<<2)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH1 (1<<3)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH2 (1<<4)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH3 (1<<5)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH4 (1<<6)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH5 (1<<7)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH6 (1<<8)
+#define SYS_CTRL_AP_ENABLE_APB2_IFC_CH7 (1<<9)
+#define SYS_CTRL_AP_ENABLE_APB2_UART1 (1<<10)
+#define SYS_CTRL_AP_ENABLE_APB2_UART2 (1<<11)
+#define SYS_CTRL_AP_ENABLE_APB2_UART3 (1<<12)
+#define SYS_CTRL_AP_ENABLE_APB2_SPI1 (1<<13)
+#define SYS_CTRL_AP_ENABLE_APB2_SPI2 (1<<14)
+#define SYS_CTRL_AP_ENABLE_APB2_SPI3 (1<<15)
+#define SYS_CTRL_AP_ENABLE_APB2_SDMMC1 (1<<16)
+#define SYS_CTRL_AP_ENABLE_APB2_SDMMC2 (1<<17)
+#define SYS_CTRL_AP_ENABLE_APB2_SDMMC3 (1<<18)
+#define SYS_CTRL_AP_ENABLE_APB2_ALWAYS (1<<19)
+#define SYS_CTRL_AP_ENABLE_APB2_NANDFLASH (1<<20)
+#define SYS_CTRL_AP_ENABLE_CLK_APB2(n) (((n)&0x1FFFFF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APB2_MASK (0x1FFFFF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APB2_SHIFT (0)
+
+//Clk_APB2_Disable
+#define SYS_CTRL_AP_DISABLE_APB2_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC (1<<1)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH0 (1<<2)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH1 (1<<3)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH2 (1<<4)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH3 (1<<5)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH4 (1<<6)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH5 (1<<7)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH6 (1<<8)
+#define SYS_CTRL_AP_DISABLE_APB2_IFC_CH7 (1<<9)
+#define SYS_CTRL_AP_DISABLE_APB2_UART1 (1<<10)
+#define SYS_CTRL_AP_DISABLE_APB2_UART2 (1<<11)
+#define SYS_CTRL_AP_DISABLE_APB2_UART3 (1<<12)
+#define SYS_CTRL_AP_DISABLE_APB2_SPI1 (1<<13)
+#define SYS_CTRL_AP_DISABLE_APB2_SPI2 (1<<14)
+#define SYS_CTRL_AP_DISABLE_APB2_SPI3 (1<<15)
+#define SYS_CTRL_AP_DISABLE_APB2_SDMMC1 (1<<16)
+#define SYS_CTRL_AP_DISABLE_APB2_SDMMC2 (1<<17)
+#define SYS_CTRL_AP_DISABLE_APB2_SDMMC3 (1<<18)
+#define SYS_CTRL_AP_DISABLE_APB2_ALWAYS (1<<19)
+#define SYS_CTRL_AP_DISABLE_APB2_NANDFLASH (1<<20)
+#define SYS_CTRL_AP_DISABLE_CLK_APB2(n) (((n)&0x1FFFFF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APB2_MASK (0x1FFFFF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APB2_SHIFT (0)
+
+//Clk_MEM_Mode
+#define SYS_CTRL_AP_MODE_CLK_MEM_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_CLK_MEM_MANUAL (1<<0)
+
+//Clk_MEM_Enable
+#define SYS_CTRL_AP_ENABLE_MEM_CONF (1<<0)
+#define SYS_CTRL_AP_ENABLE_MEM_DMC (1<<1)
+#define SYS_CTRL_AP_ENABLE_MEM_GPU (1<<2)
+#define SYS_CTRL_AP_ENABLE_MEM_VPU (1<<3)
+#define SYS_CTRL_AP_ENABLE_MEM_DDRPHY_P (1<<4)
+#define SYS_CTRL_AP_ENABLE_MEM_CONNECT (1<<5)
+#define SYS_CTRL_AP_ENABLE_CLK_MEM(n) (((n)&0x3F)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_MEM_MASK (0x3F<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_MEM_SHIFT (0)
+
+//Clk_MEM_Disable
+#define SYS_CTRL_AP_DISABLE_MEM_CONF (1<<0)
+#define SYS_CTRL_AP_DISABLE_MEM_DMC (1<<1)
+#define SYS_CTRL_AP_DISABLE_MEM_GPU (1<<2)
+#define SYS_CTRL_AP_DISABLE_MEM_VPU (1<<3)
+#define SYS_CTRL_AP_DISABLE_MEM_DDRPHY_P (1<<4)
+#define SYS_CTRL_AP_DISABLE_MEM_CONNECT (1<<5)
+#define SYS_CTRL_AP_DISABLE_CLK_MEM(n) (((n)&0x3F)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_MEM_MASK (0x3F<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_MEM_SHIFT (0)
+
+//Clk_APO_Mode
+#define SYS_CTRL_AP_MODE_APOC_VPU_AUTOMATIC (0<<0)
+#define SYS_CTRL_AP_MODE_APOC_VPU_MANUAL (1<<0)
+#define SYS_CTRL_AP_MODE_APOC_BCK_AUTOMATIC (0<<1)
+#define SYS_CTRL_AP_MODE_APOC_BCK_MANUAL (1<<1)
+#define SYS_CTRL_AP_MODE_APOC_BCK2_AUTOMATIC (0<<2)
+#define SYS_CTRL_AP_MODE_APOC_BCK2_MANUAL (1<<2)
+#define SYS_CTRL_AP_MODE_APOC_UART1_AUTOMATIC (0<<3)
+#define SYS_CTRL_AP_MODE_APOC_UART1_MANUAL (1<<3)
+#define SYS_CTRL_AP_MODE_APOC_UART2_AUTOMATIC (0<<4)
+#define SYS_CTRL_AP_MODE_APOC_UART2_MANUAL (1<<4)
+#define SYS_CTRL_AP_MODE_APOC_UART3_AUTOMATIC (0<<5)
+#define SYS_CTRL_AP_MODE_APOC_UART3_MANUAL (1<<5)
+#define SYS_CTRL_AP_MODE_APOC_VOC_CORE_AUTOMATIC (0<<6)
+#define SYS_CTRL_AP_MODE_APOC_VOC_CORE_MANUAL (1<<6)
+#define SYS_CTRL_AP_MODE_APOC_VOC2_CORE_AUTOMATIC (0<<7)
+#define SYS_CTRL_AP_MODE_APOC_VOC2_CORE_MANUAL (1<<7)
+#define SYS_CTRL_AP_MODE_APOC_VOC_AUTOMATIC (0<<8)
+#define SYS_CTRL_AP_MODE_APOC_VOC_MANUAL (1<<8)
+#define SYS_CTRL_AP_MODE_APOC_VOC2_AUTOMATIC (0<<9)
+#define SYS_CTRL_AP_MODE_APOC_VOC2_MANUAL (1<<9)
+#define SYS_CTRL_AP_MODE_CLK_APO(n) (((n)&0x3FF)<<0)
+#define SYS_CTRL_AP_MODE_CLK_APO_MASK (0x3FF<<0)
+#define SYS_CTRL_AP_MODE_CLK_APO_SHIFT (0)
+
+//Clk_APO_Enable
+#define SYS_CTRL_AP_ENABLE_APOC_VPU (1<<0)
+#define SYS_CTRL_AP_ENABLE_APOC_BCK (1<<1)
+#define SYS_CTRL_AP_ENABLE_APOC_BCK2 (1<<2)
+#define SYS_CTRL_AP_ENABLE_APOC_UART1 (1<<3)
+#define SYS_CTRL_AP_ENABLE_APOC_UART2 (1<<4)
+#define SYS_CTRL_AP_ENABLE_APOC_UART3 (1<<5)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC_CORE (1<<6)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC2_CORE (1<<7)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC (1<<8)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC2 (1<<9)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC_ALWAYS (1<<10)
+#define SYS_CTRL_AP_ENABLE_APOC_VOC2_ALWAYS (1<<11)
+#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY_N (1<<12)
+#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY2XP (1<<13)
+#define SYS_CTRL_AP_ENABLE_APOC_DDRPHY2XN (1<<14)
+#define SYS_CTRL_AP_ENABLE_APOC_GPU (1<<15)
+#define SYS_CTRL_AP_ENABLE_APOC_USBPHY (1<<16)
+#define SYS_CTRL_AP_ENABLE_APOC_CSI (1<<17)
+#define SYS_CTRL_AP_ENABLE_APOC_DSI (1<<18)
+#define SYS_CTRL_AP_ENABLE_APOC_GPIO (1<<19)
+#define SYS_CTRL_AP_ENABLE_APOC_SPIFLASH (1<<20)
+#define SYS_CTRL_AP_ENABLE_APOC_PIX (1<<21)
+#define SYS_CTRL_AP_ENABLE_APOC_PDGB (1<<22)
+#define SYS_CTRL_AP_ENABLE_CLK_APO(n) (((n)&0x7FFFFF)<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APO_MASK (0x7FFFFF<<0)
+#define SYS_CTRL_AP_ENABLE_CLK_APO_SHIFT (0)
+
+//Clk_APO_Disable
+#define SYS_CTRL_AP_DISABLE_APOC_VPU (1<<0)
+#define SYS_CTRL_AP_DISABLE_APOC_BCK (1<<1)
+#define SYS_CTRL_AP_DISABLE_APOC_BCK2 (1<<2)
+#define SYS_CTRL_AP_DISABLE_APOC_UART1 (1<<3)
+#define SYS_CTRL_AP_DISABLE_APOC_UART2 (1<<4)
+#define SYS_CTRL_AP_DISABLE_APOC_UART3 (1<<5)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC_CORE (1<<6)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC2_CORE (1<<7)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC (1<<8)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC2 (1<<9)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC_ALWAYS (1<<10)
+#define SYS_CTRL_AP_DISABLE_APOC_VOC2_ALWAYS (1<<11)
+#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY_N (1<<12)
+#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY2XP (1<<13)
+#define SYS_CTRL_AP_DISABLE_APOC_DDRPHY2XN (1<<14)
+#define SYS_CTRL_AP_DISABLE_APOC_GPU (1<<15)
+#define SYS_CTRL_AP_DISABLE_APOC_USBPHY (1<<16)
+#define SYS_CTRL_AP_DISABLE_APOC_CSI (1<<17)
+#define SYS_CTRL_AP_DISABLE_APOC_DSI (1<<18)
+#define SYS_CTRL_AP_DISABLE_APOC_GPIO (1<<19)
+#define SYS_CTRL_AP_DISABLE_APOC_SPIFLASH (1<<20)
+#define SYS_CTRL_AP_DISABLE_APOC_PIX (1<<21)
+#define SYS_CTRL_AP_DISABLE_APOC_PDGB (1<<22)
+#define SYS_CTRL_AP_DISABLE_CLK_APO(n) (((n)&0x7FFFFF)<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APO_MASK (0x7FFFFF<<0)
+#define SYS_CTRL_AP_DISABLE_CLK_APO_SHIFT (0)
+
+//Cfg_Clk_AP_CPU
+#define SYS_CTRL_AP_AP_CPU_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_CPU_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_BUS_DIV_SEL(n) (((n)&3)<<16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_MASK (3<<16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_SHIFT (16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_DIV2 (0<<16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_DIV3 (1<<16)
+#define SYS_CTRL_AP_BUS_DIV_SEL_DIV4 (2<<16)
+#define SYS_CTRL_AP_AP_CPU_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_AXI
+#define SYS_CTRL_AP_AP_AXI_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_AXI_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_AXI_SRC_SEL (1<<12)
+#define SYS_CTRL_AP_AP_AXI_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_GCG
+#define SYS_CTRL_AP_AP_GCG_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_GCG_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_GCG_SRC_SEL (1<<12)
+#define SYS_CTRL_AP_AP_GCG_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_AHB1
+#define SYS_CTRL_AP_AP_AHB1_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_AHB1_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_AHB1_SRC_SEL (1<<12)
+#define SYS_CTRL_AP_AP_AHB1_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_APB1
+#define SYS_CTRL_AP_AP_APB1_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_APB1_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_APB1_SRC_SEL (1<<12)
+#define SYS_CTRL_AP_AP_APB1_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_APB2
+#define SYS_CTRL_AP_AP_APB2_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_APB2_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_APB2_SRC_SEL (1<<12)
+#define SYS_CTRL_AP_AP_APB2_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_MEM
+#define SYS_CTRL_AP_AP_MEM_SRC_DIV2 (1<<12)
+
+//Cfg_Clk_AP_GPU
+#define SYS_CTRL_AP_AP_GPU_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_GPU_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_GPU_SRC_DIV2 (1<<12)
+#define SYS_CTRL_AP_AP_GPU_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_VPU
+#define SYS_CTRL_AP_AP_VPU_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_VPU_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_VPU_SRC_DIV2 (1<<12)
+#define SYS_CTRL_AP_AP_VPU_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_VOC
+#define SYS_CTRL_AP_AP_VOC_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_VOC_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_VOC_SRC_DIV2 (1<<12)
+#define SYS_CTRL_AP_AP_VOC_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_AP_SFLSH
+#define SYS_CTRL_AP_AP_SFLSH_FREQ(n) (((n)&31)<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_MASK (31<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_SHIFT (0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_19M (6<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_20M (7<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_300M (26<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_340M (27<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_400M (28<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_480M (29<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_600M (30<<0)
+#define SYS_CTRL_AP_AP_SFLSH_FREQ_1_2G (31<<0)
+#define SYS_CTRL_AP_AP_SFLSH_SRC_DIV2 (1<<12)
+#define SYS_CTRL_AP_AP_SFLSH_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Clk_Uart
+#define SYS_CTRL_AP_UART_DIVIDER(n) (((n)&0x3FF)<<0)
+#define SYS_CTRL_AP_UART_DIVIDER_MASK (0x3FF<<0)
+#define SYS_CTRL_AP_UART_DIVIDER_SHIFT (0)
+#define SYS_CTRL_AP_UART_SEL_PLL_SLOW (0<<12)
+#define SYS_CTRL_AP_UART_SEL_PLL_PLL (1<<12)
+
+//L2cc_Ctrl
+#define SYS_CTRL_AP_ARQOS_L2CC_1_M(n) (((n)&15)<<0)
+#define SYS_CTRL_AP_ARQOS_L2CC_1_M_MASK (15<<0)
+#define SYS_CTRL_AP_ARQOS_L2CC_1_M_SHIFT (0)
+#define SYS_CTRL_AP_AWQOS_L2CC_1_M(n) (((n)&15)<<4)
+#define SYS_CTRL_AP_AWQOS_L2CC_1_M_MASK (15<<4)
+#define SYS_CTRL_AP_AWQOS_L2CC_1_M_SHIFT (4)
+#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M(n) (((n)&15)<<8)
+#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M_MASK (15<<8)
+#define SYS_CTRL_AP_ARQOS_MODEM_MEM_AHBS_M_SHIFT (8)
+#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M(n) (((n)&15)<<12)
+#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M_MASK (15<<12)
+#define SYS_CTRL_AP_AWQOS_MODEM_MEM_AHBS_M_SHIFT (12)
+#define SYS_CTRL_AP_ARAP_L2CC_1_M  (1<<16)
+#define SYS_CTRL_AP_AWAP_L2CC_1_M  (1<<17)
+#define SYS_CTRL_AP_ARAP_MODEM_MEM_AHBS_M (1<<18)
+#define SYS_CTRL_AP_AWAP_MODEM_MEM_AHBS_M (1<<19)
+#define SYS_CTRL_AP_ARAP_MERGE1M   (1<<20)
+#define SYS_CTRL_AP_AWAP_MERGE1M   (1<<21)
+#define SYS_CTRL_AP_ARAP_MERGE2M   (1<<22)
+#define SYS_CTRL_AP_AWAP_MERGE2M   (1<<23)
+#define SYS_CTRL_AP_RESERVE1(n)    (((n)&0xFF)<<24)
+#define SYS_CTRL_AP_RESERVE1_MASK  (0xFF<<24)
+#define SYS_CTRL_AP_RESERVE1_SHIFT (24)
+
+//Spi_Ctrl
+#define SYS_CTRL_AP_LIMITED_EN_SPI1 (1<<0)
+#define SYS_CTRL_AP_LPSEN_SPI1     (1<<1)
+#define SYS_CTRL_AP_LIMITED_EN_SPI2 (1<<2)
+#define SYS_CTRL_AP_LPSEN_SPI2     (1<<3)
+#define SYS_CTRL_AP_LIMITED_EN_SPI3 (1<<4)
+#define SYS_CTRL_AP_LPSEN_SPI3     (1<<5)
+#define SYS_CTRL_AP_FBUSWID_NFSC   (1<<6)
+#define SYS_CTRL_AP_RESERVE3       (1<<7)
+#define SYS_CTRL_AP_DMC_CFG(n)     (((n)&0x3FF)<<8)
+#define SYS_CTRL_AP_DMC_CFG_MASK   (0x3FF<<8)
+#define SYS_CTRL_AP_DMC_CFG_SHIFT  (8)
+#define SYS_CTRL_AP_RESERVE2(n)    (((n)&0x3FFF)<<18)
+#define SYS_CTRL_AP_RESERVE2_MASK  (0x3FFF<<18)
+#define SYS_CTRL_AP_RESERVE2_SHIFT (18)
+
+//Memory_Margin
+#define SYS_CTRL_AP_EMAW_VOC(n)    (((n)&3)<<0)
+#define SYS_CTRL_AP_EMAW_VOC_MASK  (3<<0)
+#define SYS_CTRL_AP_EMAW_VOC_SHIFT (0)
+#define SYS_CTRL_AP_EMA_VOC(n)     (((n)&7)<<2)
+#define SYS_CTRL_AP_EMA_VOC_MASK   (7<<2)
+#define SYS_CTRL_AP_EMA_VOC_SHIFT  (2)
+#define SYS_CTRL_AP_EMAW_VPU(n)    (((n)&3)<<5)
+#define SYS_CTRL_AP_EMAW_VPU_MASK  (3<<5)
+#define SYS_CTRL_AP_EMAW_VPU_SHIFT (5)
+#define SYS_CTRL_AP_EMA_VPU(n)     (((n)&7)<<7)
+#define SYS_CTRL_AP_EMA_VPU_MASK   (7<<7)
+#define SYS_CTRL_AP_EMA_VPU_SHIFT  (7)
+#define SYS_CTRL_AP_EMAW_GPU(n)    (((n)&3)<<10)
+#define SYS_CTRL_AP_EMAW_GPU_MASK  (3<<10)
+#define SYS_CTRL_AP_EMAW_GPU_SHIFT (10)
+#define SYS_CTRL_AP_EMA_GPU(n)     (((n)&7)<<12)
+#define SYS_CTRL_AP_EMA_GPU_MASK   (7<<12)
+#define SYS_CTRL_AP_EMA_GPU_SHIFT  (12)
+#define SYS_CTRL_AP_EMAW_GOUDA(n)  (((n)&3)<<15)
+#define SYS_CTRL_AP_EMAW_GOUDA_MASK (3<<15)
+#define SYS_CTRL_AP_EMAW_GOUDA_SHIFT (15)
+#define SYS_CTRL_AP_EMA_GOUDA(n)   (((n)&7)<<17)
+#define SYS_CTRL_AP_EMA_GOUDA_MASK (7<<17)
+#define SYS_CTRL_AP_EMA_GOUDA_SHIFT (17)
+#define SYS_CTRL_AP_EMAW_IMEM(n)   (((n)&3)<<20)
+#define SYS_CTRL_AP_EMAW_IMEM_MASK (3<<20)
+#define SYS_CTRL_AP_EMAW_IMEM_SHIFT (20)
+#define SYS_CTRL_AP_EMA_IMEM(n)    (((n)&7)<<22)
+#define SYS_CTRL_AP_EMA_IMEM_MASK  (7<<22)
+#define SYS_CTRL_AP_EMA_IMEM_SHIFT (22)
+#define SYS_CTRL_AP_EMAW_USB(n)    (((n)&3)<<25)
+#define SYS_CTRL_AP_EMAW_USB_MASK  (3<<25)
+#define SYS_CTRL_AP_EMAW_USB_SHIFT (25)
+#define SYS_CTRL_AP_EMA_USB(n)     (((n)&7)<<27)
+#define SYS_CTRL_AP_EMA_USB_MASK   (7<<27)
+#define SYS_CTRL_AP_EMA_USB_SHIFT  (27)
+
+//Memory_Margin2
+#define SYS_CTRL_AP_EMAW_NFSC(n)   (((n)&3)<<0)
+#define SYS_CTRL_AP_EMAW_NFSC_MASK (3<<0)
+#define SYS_CTRL_AP_EMAW_NFSC_SHIFT (0)
+#define SYS_CTRL_AP_EMA_NFSC(n)    (((n)&7)<<2)
+#define SYS_CTRL_AP_EMA_NFSC_MASK  (7<<2)
+#define SYS_CTRL_AP_EMA_NFSC_SHIFT (2)
+#define SYS_CTRL_AP_EMA_VPUROM(n)  (((n)&7)<<5)
+#define SYS_CTRL_AP_EMA_VPUROM_MASK (7<<5)
+#define SYS_CTRL_AP_EMA_VPUROM_SHIFT (5)
+#define SYS_CTRL_AP_EMA_IMEMROM(n) (((n)&7)<<8)
+#define SYS_CTRL_AP_EMA_IMEMROM_MASK (7<<8)
+#define SYS_CTRL_AP_EMA_IMEMROM_SHIFT (8)
+#define SYS_CTRL_AP_KEN_VPUROM     (1<<11)
+#define SYS_CTRL_AP_PGEN_VPUROM    (1<<12)
+#define SYS_CTRL_AP_KEN_IMEMROM    (1<<13)
+#define SYS_CTRL_AP_PGEN_IMEMROM   (1<<14)
+
+//Memory_Observe
+#define SYS_CTRL_AP_MEM_OBSERVE(n) (((n)&0xFFFFFFFF)<<0)
+
+//Cfg_Clk_AP_VOC2
+//#define SYS_CTRL_AP_AP_VOC_FREQ(n) (((n)&31)<<0)
+//#define SYS_CTRL_AP_AP_VOC_FREQ_MASK (31<<0)
+//#define SYS_CTRL_AP_AP_VOC_FREQ_SHIFT (0)
+//#define SYS_CTRL_AP_AP_VOC_FREQ_19M (6<<0)
+//#define SYS_CTRL_AP_AP_VOC_FREQ_20M (7<<0)
+//#define SYS_CTRL_AP_AP_VOC_FREQ_300M (26<<0)
+//#define SYS_CTRL_AP_AP_VOC_FREQ_340M (27<<0)
+//#define SYS_CTRL_AP_AP_VOC_FREQ_400M (28<<0)
+//#define SYS_CTRL_AP_AP_VOC_FREQ_480M (29<<0)
+//#define SYS_CTRL_AP_AP_VOC_FREQ_600M (30<<0)
+//#define SYS_CTRL_AP_AP_VOC_FREQ_1_2G (31<<0)
+//#define SYS_CTRL_AP_AP_VOC_SRC_DIV2 (1<<12)
+//#define SYS_CTRL_AP_AP_VOC_REQ_DIV_UPDATE (1<<31)
+
+//Cfg_Reserve
+#define SYS_CTRL_AP_RESERVE(n)     (((n)&0x3FFFFFFF)<<0)
+#define SYS_CTRL_AP_AUIFC_CH0_IRQ_MASK (1<<30)
+#define SYS_CTRL_AP_AUIFC_CH1_IRQ_MASK (1<<31)
+
+
+
+
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/reg_timer.h b/arch/arm/include/asm/arch-rda/reg_timer.h
new file mode 100644
index 0000000000..80a4021caa
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_timer.h
@@ -0,0 +1,112 @@
+#ifndef _REG_TIMER_H_
+#define _REG_TIMER_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+#define NB_INTERVAL                              (1)
+#define INT_TIMER_NB_BITS                        (56)
+#define HW_TIMER_NB_BITS                         (64)
+
+// ============================================================================
+// TIMER_AP_T
+// -----------------------------------------------------------------------------
+typedef volatile struct
+{
+    REG32                          OSTimer_LoadVal_L;            //0x00000000
+    REG32                          OSTimer_Ctrl;                 //0x00000004
+    REG32                          OSTimer_CurVal_L;             //0x00000008
+    REG32                          OSTimer_CurVal_H;             //0x0000000C
+    REG32                          OSTimer_LockVal_L;            //0x00000010
+    REG32                          OSTimer_LockVal_H;            //0x00000014
+    REG32                          HWTimer_Ctrl;                 //0x00000018
+    REG32                          HWTimer_CurVal_L;             //0x0000001C
+    REG32                          HWTimer_CurVal_H;             //0x00000020
+    REG32                          HWTimer_LockVal_L;            //0x00000024
+    REG32                          HWTimer_LockVal_H;            //0x00000028
+    REG32                          Timer_Irq_Mask_Set;           //0x0000002C
+    REG32                          Timer_Irq_Mask_Clr;           //0x00000030
+    REG32                          Timer_Irq_Clr;                //0x00000034
+    REG32                          Timer_Irq_Cause;              //0x00000038
+} HWP_TIMER_AP_T;
+
+#define hwp_apTimer                 ((HWP_TIMER_AP_T*)(RDA_TIMER_BASE))
+
+//OSTimer_LoadVal_L
+#define TIMER_AP_OS_LOADVAL_L(n)    (((n)&0xFFFFFFFF)<<0)
+
+//OSTimer_Ctrl
+#define TIMER_AP_OS_LOADVAL_H(n)    (((n)&0xFFFFFF)<<0)
+#define TIMER_AP_OS_LOADVAL_H_MASK  (0xFFFFFF<<0)
+#define TIMER_AP_OS_LOADVAL_H_SHIFT (0)
+#define TIMER_AP_ENABLE             (1<<24)
+#define TIMER_AP_ENABLED            (1<<25)
+#define TIMER_AP_CLEARED            (1<<26)
+#define TIMER_AP_REPEAT             (1<<28)
+#define TIMER_AP_WRAP               (1<<29)
+#define TIMER_AP_LOAD               (1<<30)
+
+//OSTimer_CurVal_L
+#define TIMER_AP_OS_CURVAL_L(n)     (((n)&0xFFFFFFFF)<<0)
+
+//OSTimer_CurVal_H
+#define TIMER_AP_OS_CURVAL_H(n)     (((n)&0xFFFFFF)<<0)
+#define TIMER_AP_OS_CURVAL_H_MASK   (0xFFFFFF<<0)
+#define TIMER_AP_OS_CURVAL_H_SHIFT  (0)
+
+//OSTimer_LockVal_L
+#define TIMER_AP_OS_LOCKVAL_L(n)    (((n)&0xFFFFFFFF)<<0)
+#define TIMER_AP_OS_LOCKVAL_L_MASK  (0xFFFFFFFF<<0)
+#define TIMER_AP_OS_LOCKVAL_L_SHIFT (0)
+
+//OSTimer_LockVal_H
+#define TIMER_AP_OS_LOCKVAL_H(n)    (((n)&0xFFFFFF)<<0)
+#define TIMER_AP_OS_LOCKVAL_H_MASK  (0xFFFFFF<<0)
+#define TIMER_AP_OS_LOCKVAL_H_SHIFT (0)
+
+//HWTimer_Ctrl
+#define TIMER_AP_INTERVAL_EN        (1<<8)
+#define TIMER_AP_INTERVAL(n)        (((n)&3)<<0)
+
+//HWTimer_CurVal_L
+#define TIMER_AP_HW_CURVAL_L(n)     (((n)&0xFFFFFFFF)<<0)
+
+//HWTimer_CurVal_H
+#define TIMER_AP_HW_CURVAL_H(n)     (((n)&0xFFFFFFFF)<<0)
+
+//HWTimer_LockVal_L
+#define TIMER_AP_HW_LOCKVAL_L(n)    (((n)&0xFFFFFFFF)<<0)
+
+//HWTimer_LockVal_H
+#define TIMER_AP_HW_LOCKVAL_H(n)    (((n)&0xFFFFFFFF)<<0)
+
+//Timer_Irq_Mask_Set
+#define TIMER_AP_OSTIMER_MASK       (1<<0)
+#define TIMER_AP_HWTIMER_WRAP_MASK  (1<<1)
+#define TIMER_AP_HWTIMER_ITV_MASK   (1<<2)
+
+//Timer_Irq_Mask_Clr
+//#define TIMER_AP_OSTIMER_MASK     (1<<0)
+//#define TIMER_AP_HWTIMER_WRAP_MASK (1<<1)
+//#define TIMER_AP_HWTIMER_ITV_MASK (1<<2)
+
+//Timer_Irq_Clr
+#define TIMER_AP_OSTIMER_CLR        (1<<0)
+#define TIMER_AP_HWTIMER_WRAP_CLR   (1<<1)
+#define TIMER_AP_HWTIMER_ITV_CLR    (1<<2)
+
+//Timer_Irq_Cause
+#define TIMER_AP_OSTIMER_CAUSE      (1<<0)
+#define TIMER_AP_HWTIMER_WRAP_CAUSE (1<<1)
+#define TIMER_AP_HWTIMER_ITV_CAUSE  (1<<2)
+#define TIMER_AP_OSTIMER_STATUS     (1<<16)
+#define TIMER_AP_HWTIMER_WRAP_STATUS (1<<17)
+#define TIMER_AP_HWTIMER_ITV_STATUS (1<<18)
+#define TIMER_AP_OTHER_TIMS_IRQ(n)  (((n)&3)<<1)
+#define TIMER_AP_OTHER_TIMS_IRQ_MASK (3<<1)
+#define TIMER_AP_OTHER_TIMS_IRQ_SHIFT (1)
+
+#endif /* _REG_TIMER_H_ */
diff --git a/arch/arm/include/asm/arch-rda/reg_uart.h b/arch/arm/include/asm/arch-rda/reg_uart.h
new file mode 100644
index 0000000000..f3d5a7fdd0
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_uart.h
@@ -0,0 +1,478 @@
+#ifndef _REG_UART_H_
+#define _REG_UART_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+#define UART_RX_FIFO_SIZE                        (32)
+#define UART_TX_FIFO_SIZE                        (16)
+#define NB_RX_FIFO_BITS                          (5)
+#define NB_TX_FIFO_BITS                          (4)
+
+typedef volatile struct
+{
+    REG32                          ctrl;                         //0x00000000
+    REG32                          status;                       //0x00000004
+    REG32                          rxtx_buffer;                  //0x00000008
+    REG32                          irq_mask;                     //0x0000000C
+    REG32                          irq_cause;                    //0x00000010
+    REG32                          triggers;                     //0x00000014
+    REG32                          CMD_Set;                      //0x00000018
+    REG32                          CMD_Clr;                      //0x0000001C
+} HWP_UART_T;
+
+#define hwp_uart1                   ((HWP_UART_T*)(RDA_UART1_BASE))
+#define hwp_uart2                   ((HWP_UART_T*)(RDA_UART2_BASE))
+#define hwp_uart3                   ((HWP_UART_T*)(RDA_UART3_BASE))
+#define hwp_uart                    hwp_uart3
+
+//ctrl
+#define UART_ENABLE                 (1<<0)
+#define UART_ENABLE_DISABLE         (0<<0)
+#define UART_ENABLE_ENABLE          (1<<0)
+#define UART_DATA_BITS              (1<<1)
+#define UART_DATA_BITS_7_BITS       (0<<1)
+#define UART_DATA_BITS_8_BITS       (1<<1)
+#define UART_TX_STOP_BITS           (1<<2)
+#define UART_TX_STOP_BITS_1_BIT     (0<<2)
+#define UART_TX_STOP_BITS_2_BITS    (1<<2)
+#define UART_PARITY_ENABLE          (1<<3)
+#define UART_PARITY_ENABLE_NO       (0<<3)
+#define UART_PARITY_ENABLE_YES      (1<<3)
+#define UART_PARITY_SELECT(n)       (((n)&3)<<4)
+#define UART_PARITY_SELECT_ODD      (0<<4)
+#define UART_PARITY_SELECT_EVEN     (1<<4)
+#define UART_PARITY_SELECT_SPACE    (2<<4)
+#define UART_PARITY_SELECT_MARK     (3<<4)
+#define UART_DIVISOR_MODE           (1<<20)
+#define UART_IRDA_ENABLE            (1<<21)
+#define UART_DMA_MODE               (1<<22)
+#define UART_DMA_MODE_DISABLE       (0<<22)
+#define UART_DMA_MODE_ENABLE        (1<<22)
+#define UART_AUTO_FLOW_CONTROL      (1<<23)
+#define UART_AUTO_FLOW_CONTROL_ENABLE (1<<23)
+#define UART_AUTO_FLOW_CONTROL_DISABLE (0<<23)
+#define UART_LOOP_BACK_MODE         (1<<24)
+#define UART_RX_LOCK_ERR            (1<<25)
+#define UART_RX_BREAK_LENGTH(n)     (((n)&15)<<28)
+
+//status
+#define UART_RX_FIFO_LEVEL(n)       (((n)&0x3F)<<0)
+#define UART_RX_FIFO_LEVEL_MASK     (0x3F<<0)
+#define UART_RX_FIFO_LEVEL_SHIFT    (0)
+#define UART_TX_FIFO_SPACE(n)       (((n)&31)<<8)
+#define UART_TX_FIFO_SPACE_MASK     (31<<8)
+#define UART_TX_FIFO_SPACE_SHIFT    (8)
+#define UART_TX_ACTIVE              (1<<14)
+#define UART_RX_ACTIVE              (1<<15)
+#define UART_RX_OVERFLOW_ERR        (1<<16)
+#define UART_TX_OVERFLOW_ERR        (1<<17)
+#define UART_RX_PARITY_ERR          (1<<18)
+#define UART_RX_FRAMING_ERR         (1<<19)
+#define UART_RX_BREAK_INT           (1<<20)
+#define UART_DCTS                   (1<<24)
+#define UART_CTS                    (1<<25)
+#define UART_DTR                    (1<<28)
+#define UART_CLK_ENABLED            (1<<31)
+
+//rxtx_buffer
+#define UART_RX_DATA(n)             (((n)&0xFF)<<0)
+#define UART_TX_DATA(n)             (((n)&0xFF)<<0)
+
+//irq_mask
+#define UART_TX_MODEM_STATUS        (1<<0)
+#define UART_RX_DATA_AVAILABLE      (1<<1)
+#define UART_TX_DATA_NEEDED         (1<<2)
+#define UART_RX_TIMEOUT             (1<<3)
+#define UART_RX_LINE_ERR            (1<<4)
+#define UART_TX_DMA_DONE            (1<<5)
+#define UART_RX_DMA_DONE            (1<<6)
+#define UART_RX_DMA_TIMEOUT         (1<<7)
+#define UART_DTR_RISE               (1<<8)
+#define UART_DTR_FALL               (1<<9)
+
+//irq_cause
+//#define UART_TX_MODEM_STATUS      (1<<0)
+//#define UART_RX_DATA_AVAILABLE    (1<<1)
+//#define UART_TX_DATA_NEEDED       (1<<2)
+//#define UART_RX_TIMEOUT           (1<<3)
+//#define UART_RX_LINE_ERR          (1<<4)
+//#define UART_TX_DMA_DONE          (1<<5)
+//#define UART_RX_DMA_DONE          (1<<6)
+//#define UART_RX_DMA_TIMEOUT       (1<<7)
+//#define UART_DTR_RISE             (1<<8)
+//#define UART_DTR_FALL             (1<<9)
+#define UART_TX_MODEM_STATUS_U      (1<<16)
+#define UART_RX_DATA_AVAILABLE_U    (1<<17)
+#define UART_TX_DATA_NEEDED_U       (1<<18)
+#define UART_RX_TIMEOUT_U           (1<<19)
+#define UART_RX_LINE_ERR_U          (1<<20)
+#define UART_TX_DMA_DONE_U          (1<<21)
+#define UART_RX_DMA_DONE_U          (1<<22)
+#define UART_RX_DMA_TIMEOUT_U       (1<<23)
+#define UART_DTR_RISE_U             (1<<24)
+#define UART_DTR_FALL_U             (1<<25)
+
+//triggers
+#define UART_RX_TRIGGER(n)          (((n)&31)<<0)
+#define UART_TX_TRIGGER(n)          (((n)&15)<<8)
+#define UART_AFC_LEVEL(n)           (((n)&31)<<16)
+
+//CMD_Set
+#define UART_RI                     (1<<0)
+#define UART_DCD                    (1<<1)
+#define UART_DSR                    (1<<2)
+#define UART_TX_BREAK_CONTROL       (1<<3)
+#define UART_TX_FINISH_N_WAIT       (1<<4)
+#define UART_RTS                    (1<<5)
+#define UART_RX_FIFO_RESET          (1<<6)
+#define UART_TX_FIFO_RESET          (1<<7)
+
+//CMD_Clr
+//#define UART_RI                   (1<<0)
+//#define UART_DCD                  (1<<1)
+//#define UART_DSR                  (1<<2)
+//#define UART_TX_BREAK_CONTROL     (1<<3)
+//#define UART_TX_FINISH_N_WAIT     (1<<4)
+//#define UART_RTS                  (1<<5)
+
+#define CHIP_STD_UART_QTY 2
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+
+// ============================================================================
+// HAL_UART_DATA_BITS_T
+// -----------------------------------------------------------------------------
+/// UART data length
+// =============================================================================
+typedef enum
+{
+/// Data is 7 bits
+    HAL_UART_7_DATA_BITS                        = 0x00000000,
+/// Data is 8 bits
+    HAL_UART_8_DATA_BITS                        = 0x00000001,
+    HAL_UART_DATA_BITS_QTY                      = 0x00000002
+} HAL_UART_DATA_BITS_T;
+
+
+// ============================================================================
+// HAL_UART_STOP_BITS_QTY_T
+// -----------------------------------------------------------------------------
+/// Number of stop bits
+// =============================================================================
+typedef enum
+{
+/// There is 1 stop bit
+    HAL_UART_1_STOP_BIT                         = 0x00000000,
+/// There are 2 stop bits
+    HAL_UART_2_STOP_BITS                        = 0x00000001,
+    HAL_UART_STOP_BITS_QTY                      = 0x00000002
+} HAL_UART_STOP_BITS_QTY_T;
+
+
+// ============================================================================
+// HAL_UART_PARITY_CFG_T
+// -----------------------------------------------------------------------------
+/// Data parity control selection If enabled, a parity check can be performed
+// =============================================================================
+typedef enum
+{
+/// No parity check
+    HAL_UART_NO_PARITY                          = 0x00000000,
+/// Parity check is odd
+    HAL_UART_ODD_PARITY                         = 0x00000001,
+/// Parity check is even
+    HAL_UART_EVEN_PARITY                        = 0x00000002,
+/// Parity check is always 0 (space)
+    HAL_UART_SPACE_PARITY                       = 0x00000003,
+/// Parity check is always 1 (mark)
+    HAL_UART_MARK_PARITY                        = 0x00000004,
+    HAL_UART_PARITY_QTY                         = 0x00000005
+} HAL_UART_PARITY_CFG_T;
+
+
+// ============================================================================
+// HAL_UART_RX_TRIGGER_CFG_T
+// -----------------------------------------------------------------------------
+/// Reception FIFO trigger (or treshold) level The Uarts can be configured to generate
+/// an interrupt when the reception FIFO is above a configurable threshold (Rx FIFO
+/// trigger
+// =============================================================================
+typedef enum
+{
+/// One data received in the Rx FIFO
+    HAL_UART_RX_TRIG_1                          = 0x00000000,
+/// 1/4 of the Rx FIFO is full
+    HAL_UART_RX_TRIG_QUARTER                    = 0x00000001,
+/// 1/2 of the Rx FIFO is full
+    HAL_UART_RX_TRIG_HALF                       = 0x00000002,
+/// Rx FIFO is almost full
+    HAL_UART_RX_TRIG_NEARFULL                   = 0x00000003,
+    HAL_UART_RX_TRIG_QTY                        = 0x00000004
+} HAL_UART_RX_TRIGGER_CFG_T;
+
+
+// ============================================================================
+// HAL_UART_TX_TRIGGER_CFG_T
+// -----------------------------------------------------------------------------
+/// Tranmission FIFO trigger (or treshold) level. The Uarts can be configured to
+/// generate an interrupt when the emission FIFO is below a configurable threshold
+/// (Tx FIFO trigger
+// =============================================================================
+typedef enum
+{
+/// Tx FIFO empty
+    HAL_UART_TX_TRIG_EMPTY                      = 0x00000000,
+/// Less than 1/4 of the Tx FIFO left to send
+    HAL_UART_TX_TRIG_QUARTER                    = 0x00000001,
+/// Less than 1/2 of the Tx FIFO left to send
+    HAL_UART_TX_TRIG_HALF                       = 0x00000002,
+/// Less thant 3/4 of the Tx FIFO left to send
+    HAL_UART_TX_TRIG_3QUARTER                   = 0x00000003,
+    HAL_UART_TX_TRIG_QTY                        = 0x00000004
+} HAL_UART_TX_TRIGGER_CFG_T;
+
+
+// ============================================================================
+// HAL_UART_AFC_MODE_T
+// -----------------------------------------------------------------------------
+/// Auto Flow Control. Controls the Rx Fifo level at which the Uart_RTS Auto Flow
+/// Control will be set inactive high (see UART Operation for more details on AFC).
+/// The Uart_RTS Auto Flow Control will be set inactive high when quantity of data
+/// in Rx Fifo &amp;gt; AFC Level
+// =============================================================================
+typedef enum
+{
+/// RTS inactive with 1 data in the Rx FIFO
+    HAL_UART_AFC_MODE_RX_TRIG_1                 = 0x00000000,
+/// RTS inactive with 2 data in the Rx FIFO
+    HAL_UART_AFC_MODE_RX_TRIG_2                 = 0x00000001,
+/// RTS inactive with 3 data in the Rx FIFO
+    HAL_UART_AFC_MODE_RX_TRIG_3                 = 0x00000002,
+/// RTS inactive with 4 data in the Rx FIFO
+    HAL_UART_AFC_MODE_RX_TRIG_4                 = 0x00000003,
+/// RTS inactive with 5 data in the Rx FIFO
+    HAL_UART_AFC_MODE_RX_TRIG_5                 = 0x00000004,
+/// RTS inactive with 6 data in the Rx FIFO
+    HAL_UART_AFC_MODE_RX_TRIG_6                 = 0x00000005,
+/// RTS inactive with 7 data in the Rx FIFO
+    HAL_UART_AFC_MODE_RX_TRIG_7                 = 0x00000006,
+/// RTS inactive with 8 data in the Rx FIFO
+    HAL_UART_AFC_MODE_RX_TRIG_8                 = 0x00000007,
+/// RTS inactive with 9 data in the Rx FIFO
+    HAL_UART_AFC_MODE_RX_TRIG_9                 = 0x00000008,
+/// RTS inactive with 10 data in the Rx FIFO
+    HAL_UART_AFC_MODE_RX_TRIG_10                = 0x00000009,
+/// RTS inactive with 11 data in the Rx FIFO
+    HAL_UART_AFC_MODE_RX_TRIG_11                = 0x0000000A,
+/// RTS inactive with 12 data in the Rx FIFO
+    HAL_UART_AFC_MODE_RX_TRIG_12                = 0x0000000B,
+/// RTS inactive with 13 data in the Rx FIFO
+    HAL_UART_AFC_MODE_RX_TRIG_13                = 0x0000000C,
+/// RTS inactive with 14 data in the Rx FIFO
+    HAL_UART_AFC_MODE_RX_TRIG_14                = 0x0000000D,
+/// RTS inactive with 15 data in the Rx FIFO
+    HAL_UART_AFC_MODE_RX_TRIG_15                = 0x0000000E,
+/// RTS inactive with 16 data in the Rx FIFO
+    HAL_UART_AFC_MODE_RX_TRIG_16                = 0x0000000F,
+/// Hardware flow control is disabled. \n &amp;lt;B&amp;gt; NEVER USE THIS MODE &amp;lt;/B&amp;gt;
+    HAL_UART_AFC_MODE_DISABLE                   = 0x00000010,
+    HAL_UART_AFC_MODE_QTY                       = 0x00000011,
+/// AFC mode is loopback \n When set, data on the Uart_Tx line is held high, while
+/// the serial output is looped back to the serial input line, internally.
+    HAL_UART_AFC_LOOP_BACK                      = 0x00000020
+} HAL_UART_AFC_MODE_T;
+
+
+// ============================================================================
+// HAL_UART_IRDA_MODE_T
+// -----------------------------------------------------------------------------
+/// IrDA protocole enabling IrDA SIR mode is available, and can be activated when
+/// the user open the Uart
+// =============================================================================
+typedef enum
+{
+/// IrDA mode disabled
+    HAL_UART_IRDA_MODE_DISABLE                  = 0x00000000,
+/// IrDA mode enabled
+    HAL_UART_IRDA_MODE_ENABLE                   = 0x00000001,
+    HAL_UART_IRDA_MODE_QTY                      = 0x00000002
+} HAL_UART_IRDA_MODE_T;
+
+
+// ============================================================================
+// HAL_UART_BAUD_RATE_T
+// -----------------------------------------------------------------------------
+/// Baudrate available with the modifiable system clock UARTs are able to run at
+/// a wide selection of baud rates. This must be configured at the UART opening
+// =============================================================================
+typedef enum
+{
+/// 2.4 KBaud (Serial and IrDA)
+    HAL_UART_BAUD_RATE_2400                     = 0x00000960,
+/// 4.8 KBaud (Serial and IrDA)
+    HAL_UART_BAUD_RATE_4800                     = 0x000012C0,
+/// 9.6 KBaud (Serial and IrDA)
+    HAL_UART_BAUD_RATE_9600                     = 0x00002580,
+/// 14.4 KBaud (Serial and IrDA)
+    HAL_UART_BAUD_RATE_14400                    = 0x00003840,
+/// 19.2 KBaud (Serial and IrDA)
+    HAL_UART_BAUD_RATE_19200                    = 0x00004B00,
+/// 28.8 KBaud (Serial and IrDA)
+    HAL_UART_BAUD_RATE_28800                    = 0x00007080,
+/// 33.6 KBaud (Serial and IrDA)
+    HAL_UART_BAUD_RATE_33600                    = 0x00008340,
+/// 38.4 KBaud (Serial and IrDA)
+    HAL_UART_BAUD_RATE_38400                    = 0x00009600,
+/// 57.6 KBaud (Serial and IrDA)
+    HAL_UART_BAUD_RATE_57600                    = 0x0000E100,
+/// 115.2 KBaud (Serial and IrDA)
+    HAL_UART_BAUD_RATE_115200                   = 0x0001C200,
+/// 230.4 KBaud (Available only in serial mode)
+    HAL_UART_BAUD_RATE_230400                   = 0x00038400,
+/// 460.8 KBaud (Available only in serial mode)
+    HAL_UART_BAUD_RATE_460800                   = 0x00070800,
+/// 921.6 KBaud (Available only in serial mode)
+    HAL_UART_BAUD_RATE_921600                   = 0x000E1000,
+/// 1843.2 KBaud (Available only in serial mode)
+    HAL_UART_BAUD_RATE_1843200                  = 0x001C2000,
+    HAL_UART_BAUD_RATE_QTY                      = 0x001C2001
+} HAL_UART_BAUD_RATE_T;
+
+
+// ============================================================================
+// HAL_UART_TRANSFERT_MODE_T
+// -----------------------------------------------------------------------------
+/// Data transfert mode: via DMA or direct. To allow for an easy use of the Uart
+/// modules, a non blocking hardware abstraction layer interface is provided
+// =============================================================================
+typedef enum
+{
+/// Direct polling: The application sends/receives the data directly to/from the
+/// hardware module. The number of bytes actually sent/received is returned. No IRQ
+/// is generated.
+    HAL_UART_TRANSFERT_MODE_DIRECT_POLLING      = 0x00000000,
+/// Direct Irq: The application sends/receives the data directly to/from the hardware
+/// module. The number of bytes actually sent/received is returned.An irq can be
+/// generated when the Tx/Rx FIFO reaches the pre-programmed level.
+    HAL_UART_TRANSFERT_MODE_DIRECT_IRQ          = 0x00000001,
+/// DMA polling: The application sends/receives the data through a DMA to the hardware
+/// module. When no DMA channel is available, the function returns 0. No byte is
+/// sent. When a DMA resource is available, the function returns the number of bytes
+/// to send. They will all be sent. A function allows to check if the previous DMA
+/// transfer is finished. No new DMA transfer for the same Uart and in the same direction
+/// is allowed until the previous transfer is finished.
+    HAL_UART_TRANSFERT_MODE_DMA_POLLING         = 0x00000002,
+/// The application sends/receives the data through a DMA to the hardware module.
+/// When no DMA channel is available, the function returns 0. No byte is sent. When
+/// a DMA resource is available, the function returns the number of bytes to send.
+/// They will all be sent. An Irq is generated when the current transfer is finished.
+/// No new DMA transfer for the same Uart and in the same direction is allowed until
+/// the previous transfer is finished.
+    HAL_UART_TRANSFERT_MODE_DMA_IRQ             = 0x00000003,
+/// The transfert is off.
+    HAL_UART_TRANSFERT_MODE_OFF                 = 0x00000004,
+    HAL_UART_TRANSFERT_MODE_QTY                 = 0x00000005
+} HAL_UART_TRANSFERT_MODE_T;
+
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+// ============================================================================
+// HAL_UART_CFG_T
+// -----------------------------------------------------------------------------
+/// UART Configuration Structure This structure defines the Uart behavior
+// =============================================================================
+typedef struct
+{
+    /// Data format
+    HAL_UART_DATA_BITS_T           data;                         //0x00000000
+    /// Number of stop bits
+    HAL_UART_STOP_BITS_QTY_T       stop;                         //0x00000004
+    /// Parity check
+    HAL_UART_PARITY_CFG_T          parity;                       //0x00000008
+    /// Trigger for the Rx FIFO
+    HAL_UART_RX_TRIGGER_CFG_T      rx_trigger;                   //0x0000000C
+    /// Trigger for the Tx FIFO
+    HAL_UART_TX_TRIGGER_CFG_T      tx_trigger;                   //0x00000010
+    /// Hardware Flow control
+    HAL_UART_AFC_MODE_T            afc;                          //0x00000014
+    /// IrDA mode
+    HAL_UART_IRDA_MODE_T           irda;                         //0x00000018
+    /// Baud Rate
+    HAL_UART_BAUD_RATE_T           rate;                         //0x0000001C
+    /// Reception transfer mode
+    HAL_UART_TRANSFERT_MODE_T      rx_mode;                      //0x00000020
+    /// Transmission transfer mode
+    HAL_UART_TRANSFERT_MODE_T      tx_mode;                      //0x00000024
+} HAL_UART_CFG_T; //Size : 0x28
+
+
+
+// ============================================================================
+// HAL_UART_IRQ_STATUS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef struct
+{
+    u32                            txModemStatus:1;
+    u32                            rxDataAvailable:1;
+    u32                            txDataNeeded:1;
+    u32                            rxTimeout:1;
+    u32                            rxLineErr:1;
+    u32                            txDmaDone:1;
+    u32                            rxDmaDone:1;
+    u32                            rxDmaTimeout:1;
+} HAL_UART_IRQ_STATUS_T;
+//unused
+#define HAL_UART_IRQ_STATUS_TXMODEMSTATUS (1<<0)
+#define HAL_UART_IRQ_STATUS_RXDATAAVAILABLE (1<<1)
+#define HAL_UART_IRQ_STATUS_TXDATANEEDED (1<<2)
+#define HAL_UART_IRQ_STATUS_RXTIMEOUT (1<<3)
+#define HAL_UART_IRQ_STATUS_RXLINEERR (1<<4)
+#define HAL_UART_IRQ_STATUS_TXDMADONE (1<<5)
+#define HAL_UART_IRQ_STATUS_RXDMADONE (1<<6)
+#define HAL_UART_IRQ_STATUS_RXDMATIMEOUT (1<<7)
+
+
+
+// ============================================================================
+// HAL_UART_ERROR_STATUS_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef struct
+{
+    u32                            _:4;
+    u32                            rxOvflErr:1;
+    u32                            txOvflErr:1;
+    u32                            rxParityErr:1;
+    u32                            rxFramingErr:1;
+    u32                            rxBreakInt:1;
+} HAL_UART_ERROR_STATUS_T;
+//unused
+#define HAL_UART_ERROR_STATUS__(n)  (((n)&15)<<0)
+#define HAL_UART_ERROR_STATUS_RXOVFLERR (1<<4)
+#define HAL_UART_ERROR_STATUS_TXOVFLERR (1<<5)
+#define HAL_UART_ERROR_STATUS_RXPARITYERR (1<<6)
+#define HAL_UART_ERROR_STATUS_RXFRAMINGERR (1<<7)
+#define HAL_UART_ERROR_STATUS_RXBREAKINT (1<<8)
+
+
+/// Uart 0 is the trace uart and is unavailable for this driver
+/// The numbering starts at 1 for consistency.
+/// The HAL_UART_QTY value is defined as the number of UARTS
+/// avalaible for the chip on which the driver is running, and
+/// can therefore be used for consistency checks
+typedef enum {
+    HAL_UART_1                                  = 0x00000001,
+    HAL_UART_2                                  = 0x00000002,
+    HAL_UART_QTY                                = CHIP_STD_UART_QTY+1
+} HAL_UART_ID_T;   
+
+#endif /* _REG_UART_H_ */
diff --git a/arch/arm/include/asm/arch-rda/reg_xcpu.h b/arch/arm/include/asm/arch-rda/reg_xcpu.h
new file mode 100644
index 0000000000..166fbaff89
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/reg_xcpu.h
@@ -0,0 +1,314 @@
+//==============================================================================
+//                                                                              
+//            Copyright (C) 2012-2013, RDA Microelectronics.                    
+//                            All Rights Reserved                               
+//                                                                              
+//      This source code is the property of RDA Microelectronics and is         
+//      confidential.  Any  modification, distribution,  reproduction or        
+//      exploitation  of  any content of this file is totally forbidden,        
+//      except  with the  written permission  of   RDA Microelectronics.        
+//                                                                              
+//==============================================================================
+//                                                                              
+//    THIS FILE WAS GENERATED FROM ITS CORRESPONDING XML VERSION WITH COOLXML.  
+//                                                                              
+//                       !!! PLEASE DO NOT EDIT !!!                             
+//                                                                              
+//  $HeadURL$                                                                   
+//  $Author$                                                                    
+//  $Date$                                                                      
+//  $Revision$                                                                  
+//                                                                              
+//==============================================================================
+//
+/// @file
+//
+//==============================================================================
+
+#ifndef _XCPU_H_
+#define _XCPU_H_
+
+#ifdef CT_ASM
+#error "You are trying to use in an assembly code the normal H description of 'xcpu'."
+#endif
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/rda_iomap.h>
+
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+// ============================================================================
+// XCPU_T
+// -----------------------------------------------------------------------------
+/// 
+// =============================================================================
+typedef volatile struct
+{
+    REG32 Reserved_00000000;                    //0x00000000
+    REG32                          rf0_addr;                     //0x00000004
+    REG32 Reserved_00000008[97];                //0x00000008
+    REG32                          cp0_adr_BadVAddr;             //0x0000018C
+    REG32                          cp0_Cause;                    //0x00000190
+    REG32                          cp0_Status;                   //0x00000194
+    REG32                          cp0_EPC;                      //0x00000198
+    REG32 Reserved_0000019C[5];                 //0x0000019C
+    REG32                          cp0_BadVAddr;                 //0x000001B0
+    REG32 Reserved_000001B4[19];                //0x000001B4
+    REG32                          rf0_data;                     //0x00000200
+    REG32 Reserved_00000204[5];                 //0x00000204
+    REG32                          dc0_result;                   //0x00000218
+    REG32 Reserved_0000021C[89];                //0x0000021C
+    REG32 Reserved_00000380;                    //0x00000380
+    REG32                          Regfile_AT;                   //0x00000384
+    REG32                          Regfile_V0;                   //0x00000388
+    REG32                          Regfile_V1;                   //0x0000038C
+    REG32                          Regfile_A0;                   //0x00000390
+    REG32                          Regfile_A1;                   //0x00000394
+    REG32                          Regfile_A2;                   //0x00000398
+    REG32                          Regfile_A3;                   //0x0000039C
+    REG32                          Regfile_T0;                   //0x000003A0
+    REG32                          Regfile_T1;                   //0x000003A4
+    REG32                          Regfile_T2;                   //0x000003A8
+    REG32                          Regfile_T3;                   //0x000003AC
+    REG32                          Regfile_T4;                   //0x000003B0
+    REG32                          Regfile_T5;                   //0x000003B4
+    REG32                          Regfile_T6;                   //0x000003B8
+    REG32                          Regfile_T7;                   //0x000003BC
+    REG32                          Regfile_S0;                   //0x000003C0
+    REG32                          Regfile_S1;                   //0x000003C4
+    REG32                          Regfile_S2;                   //0x000003C8
+    REG32                          Regfile_S3;                   //0x000003CC
+    REG32                          Regfile_S4;                   //0x000003D0
+    REG32                          Regfile_S5;                   //0x000003D4
+    REG32                          Regfile_S6;                   //0x000003D8
+    REG32                          Regfile_S7;                   //0x000003DC
+    REG32                          Regfile_T8;                   //0x000003E0
+    REG32                          Regfile_T9;                   //0x000003E4
+    REG32                          Regfile_K0;                   //0x000003E8
+    REG32                          Regfile_K1;                   //0x000003EC
+    REG32                          Regfile_GP;                   //0x000003F0
+    REG32                          Regfile_SP;                   //0x000003F4
+    REG32                          Regfile_S8;                   //0x000003F8
+    REG32                          Regfile_RA;                   //0x000003FC
+    REG32 Reserved_00000400[16];                //0x00000400
+    REG32                          Debug_Page_Address;           //0x00000440
+    REG32                          Cache_Control;                //0x00000444
+} HWP_XCPU_T;
+
+#define hwp_xcpu                   ((HWP_XCPU_T*) (RDA_MODEM_XCPU_BASE))
+#define hwp_bcpu                   ((HWP_XCPU_T*) (RDA_MODEM_BCPU_BASE))
+
+
+//rf0_addr
+#define XCPU_RF0_ADDR(n)           (((n)&0xFFFFFFFF)<<0)
+
+//cp0_adr_BadVAddr
+#define XCPU_CP0_ADR_BADVADDR(n)   (((n)&0xFFFFFFFF)<<0)
+
+//cp0_Cause
+#define XCPU_CP0_CAUSE_EXCCODE(n)  (((n)&15)<<2)
+#define XCPU_CP0_CAUSE_EXCCODE_MASK (15<<2)
+#define XCPU_CP0_CAUSE_EXCCODE_SHIFT (2)
+#define XCPU_CP0_CAUSE_EXCCODE_INT (0<<2)
+#define XCPU_CP0_CAUSE_EXCCODE_MOD (1<<2)
+#define XCPU_CP0_CAUSE_EXCCODE_TLBL (2<<2)
+#define XCPU_CP0_CAUSE_EXCCODE_TLBS (3<<2)
+#define XCPU_CP0_CAUSE_EXCCODE_ADEL (4<<2)
+#define XCPU_CP0_CAUSE_EXCCODE_ADES (5<<2)
+#define XCPU_CP0_CAUSE_EXCCODE_IBE (6<<2)
+#define XCPU_CP0_CAUSE_EXCCODE_DBE (7<<2)
+#define XCPU_CP0_CAUSE_EXCCODE_SYS (8<<2)
+#define XCPU_CP0_CAUSE_EXCCODE_PB  (9<<2)
+#define XCPU_CP0_CAUSE_EXCCODE_RI  (10<<2)
+#define XCPU_CP0_CAUSE_EXCCODE_CPU (11<<2)
+#define XCPU_CP0_CAUSE_EXCCODE_OV  (12<<2)
+#define XCPU_CP0_CAUSE_IP_SOFT(n)  (((n)&3)<<8)
+#define XCPU_CP0_CAUSE_IP_SOFT_MASK (3<<8)
+#define XCPU_CP0_CAUSE_IP_SOFT_SHIFT (8)
+#define XCPU_CP0_CAUSE_IP_EXT(n)   (((n)&0x3F)<<10)
+#define XCPU_CP0_CAUSE_IP_EXT_MASK (0x3F<<10)
+#define XCPU_CP0_CAUSE_IP_EXT_SHIFT (10)
+#define XCPU_CP0_CAUSE_CE(n)       (((n)&3)<<28)
+#define XCPU_CP0_CAUSE_CE_MASK     (3<<28)
+#define XCPU_CP0_CAUSE_CE_SHIFT    (28)
+#define XCPU_CP0_CAUSE_BD_MASK     (1<<31)
+#define XCPU_CP0_CAUSE_BD_SHIFT    (31)
+#define XCPU_CP0_CAUSE_BD_NORMAL   (0<<31)
+#define XCPU_CP0_CAUSE_BD_DELAY_SLOT (1<<31)
+#define XCPU_CP0_CAUSE_IP(n)       (((n)&0xFF)<<8)
+#define XCPU_CP0_CAUSE_IP_MASK     (0xFF<<8)
+#define XCPU_CP0_CAUSE_IP_SHIFT    (8)
+
+//cp0_Status
+#define XCPU_CP0_STATUS_IEC_MASK   (1<<0)
+#define XCPU_CP0_STATUS_IEC_SHIFT  (0)
+#define XCPU_CP0_STATUS_IEC_DISABLE (0<<0)
+#define XCPU_CP0_STATUS_IEC_ENABLE (1<<0)
+#define XCPU_CP0_STATUS_KUC_MASK   (1<<1)
+#define XCPU_CP0_STATUS_KUC_SHIFT  (1)
+#define XCPU_CP0_STATUS_KUC_KERNEL (0<<1)
+#define XCPU_CP0_STATUS_KUC_USER   (1<<1)
+#define XCPU_CP0_STATUS_IEP_MASK   (1<<2)
+#define XCPU_CP0_STATUS_IEP_SHIFT  (2)
+#define XCPU_CP0_STATUS_IEP_DISABLE (0<<2)
+#define XCPU_CP0_STATUS_IEP_ENABLE (1<<2)
+#define XCPU_CP0_STATUS_KUP_MASK   (1<<3)
+#define XCPU_CP0_STATUS_KUP_SHIFT  (3)
+#define XCPU_CP0_STATUS_KUP_KERNEL (0<<3)
+#define XCPU_CP0_STATUS_KUP_USER   (1<<3)
+#define XCPU_CP0_STATUS_IEO_MASK   (1<<4)
+#define XCPU_CP0_STATUS_IEO_SHIFT  (4)
+#define XCPU_CP0_STATUS_IEO_DISABLE (0<<4)
+#define XCPU_CP0_STATUS_IEO_ENABLE (1<<4)
+#define XCPU_CP0_STATUS_KUO_MASK   (1<<5)
+#define XCPU_CP0_STATUS_KUO_SHIFT  (5)
+#define XCPU_CP0_STATUS_KUO_KERNEL (0<<5)
+#define XCPU_CP0_STATUS_KUO_USER   (1<<5)
+#define XCPU_CP0_STATUS_KUI        (1<<6)
+#define XCPU_CP0_STATUS_INTMASK(n) (((n)&0xFF)<<8)
+#define XCPU_CP0_STREAMING_DISABLE (1<<16)
+#define XCPU_CP0_STATUS_CM         (1<<19)
+#define XCPU_CP0_STATUS_TS         (1<<21)
+#define XCPU_CP0_STATUS_BEV        (1<<22)
+#define XCPU_CP0_STATUS_RE         (1<<25)
+#define XCPU_CP0_STATUS_CU_0       (1<<28)
+#define XCPU_CP0_STATUS_CU_1       (1<<29)
+#define XCPU_CP0_STATUS_CU_2       (1<<30)
+#define XCPU_CP0_STATUS_CU_3       (1<<31)
+#define XCPU_CP0_STATUS_CU_123(n)  (((n)&7)<<29)
+#define XCPU_CP0_STATUS_CU_123_MASK (7<<29)
+#define XCPU_CP0_STATUS_CU_123_SHIFT (29)
+#define XCPU_CP0_STATUS_CU(n)      (((n)&15)<<28)
+#define XCPU_CP0_STATUS_CU_MASK    (15<<28)
+#define XCPU_CP0_STATUS_CU_SHIFT   (28)
+
+//cp0_EPC
+#define XCPU_CP0_EPC(n)            (((n)&0xFFFFFFFF)<<0)
+
+//cp0_BadVAddr
+#define XCPU_CP0_BADVADDR(n)       (((n)&0xFFFFFFFF)<<0)
+
+//rf0_data
+#define XCPU_RF0_DATA(n)           (((n)&0xFFFFFFFF)<<0)
+
+//dc0_result
+#define XCPU_DC0_RESULT(n)         (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_AT
+#define XCPU_AT(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_V0
+#define XCPU_V0(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_V1
+#define XCPU_V1(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_A0
+#define XCPU_A0(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_A1
+#define XCPU_A1(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_A2
+#define XCPU_A2(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_A3
+#define XCPU_A3(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_T0
+#define XCPU_T0(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_T1
+#define XCPU_T1(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_T2
+#define XCPU_T2(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_T3
+#define XCPU_T3(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_T4
+#define XCPU_T4(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_T5
+#define XCPU_T5(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_T6
+#define XCPU_T6(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_T7
+#define XCPU_T7(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_S0
+#define XCPU_S0(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_S1
+#define XCPU_S1(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_S2
+#define XCPU_S2(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_S3
+#define XCPU_S3(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_S4
+#define XCPU_S4(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_S5
+#define XCPU_S5(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_S6
+#define XCPU_S6(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_S7
+#define XCPU_S7(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_T8
+#define XCPU_T8(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_T9
+#define XCPU_T9(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_K0
+#define XCPU_K0(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_K1
+#define XCPU_K1(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_GP
+#define XCPU_GP(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_SP
+#define XCPU_SP(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_S8
+#define XCPU_S8(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Regfile_RA
+#define XCPU_RA(n)                 (((n)&0xFFFFFFFF)<<0)
+
+//Debug_Page_Address
+#define XCPU_DEBUG_PAGE_ADDRESS(n) (((n)&15)<<0)
+#define XCPU_DEBUG_PAGE_ADDRESS_MASK (15<<0)
+#define XCPU_DEBUG_PAGE_ADDRESS_SHIFT (0)
+#define XCPU_DEBUG_PAGE_ADDRESS_ITAG (0<<0)
+#define XCPU_DEBUG_PAGE_ADDRESS_DTAG (8<<0)
+
+//Cache_Control
+#define XCPU_DCACHE_INHIBIT        (1<<0)
+#define XCPU_ICACHE_INHIBIT        (1<<1)
+#define XCPU_CACHE_HIT_DISABLE     (1<<2)
+
+
+
+
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-rda/rom_api_trampolin.h b/arch/arm/include/asm/arch-rda/rom_api_trampolin.h
new file mode 100644
index 0000000000..2104ed8559
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/rom_api_trampolin.h
@@ -0,0 +1,180 @@
+
+#ifndef __RDA_ROM_API_H__
+#define __RDA_ROM_API_H__
+
+struct chip_id {
+	// ASIC information
+	uint32_t  chip;     // CHIP(31:15) NA(15:15) BOND(14:12) METAL(11:0)
+	uint32_t  res1;
+	// Production information
+	uint16_t  date;     // YYYY:MMMM:DDDDD
+	uint16_t  wafer;
+	uint16_t  xy;
+	uint16_t  res2;
+};
+
+struct chip_security_context {
+	// Security context
+	uint8_t   rda_key_index; // 0-5 : 0 default key
+	uint8_t   vendor_id;     // 0-50
+	uint16_t  flags;
+#define RDA_SE_CFG_UNLOCK_ALLOWED       (1<<0)
+#define RDA_SE_CFG_SECURITY_ENABLE_BIT  (1<<4)
+#define RDA_SE_CFG_INDIRECT_SIGN_BIT    (1<<5)
+#define RDA_SE_CFG_HOST_DISABLE_BIT     (1<<6)
+#define RDA_SE_CFG_TRACE_DISABLE_BIT    (1<<7)
+};
+
+struct chip_unique_id {
+	uint8_t	  id[32];
+};
+
+/* security */
+#define RDASIGN     "RDAS"
+#define PKALG       "Ed"
+#define KDFALG      "BK"
+
+#define SIGBYTES    64
+#define PUBLICBYTES 32
+#define SECRETBYTES 64
+#define FPLEN        8
+
+struct pubkey {
+	uint8_t rdasign[4];//RDAS
+	uint8_t pkalg[2];  //Ed
+	uint8_t dummy[2];
+	uint8_t name[16];
+	uint8_t fingerprint[FPLEN];
+	uint8_t pubkey[PUBLICBYTES];
+};
+
+// RDASEdPo
+struct sig {
+	uint8_t rdasign[4];//RDAS
+	uint8_t pkalg[2];  //Ed
+	uint8_t hashalg[2];//Po/B2/SH
+	uint8_t name[16];
+	uint8_t fingerprint[FPLEN];
+	uint8_t sig[SIGBYTES];
+};
+
+
+/* ROM Cryto API */
+
+struct ROM_crypto_api {
+	char     magic[8];  // "RDA API"
+	unsigned version;   // 100
+
+	// signature
+	int (*signature_open) (
+		const uint8_t *message, unsigned length,
+		const struct sig    *sig,
+		const struct pubkey *pubkey);
+/* Return values */
+#define ROM_API_SIGNATURE_OK      0
+#define ROM_API_SIGNATURE_FAIL   -1
+// positive values is for invalid arguments
+
+	// hash
+	unsigned sz_hash_context;
+	int (*hash_init) ( unsigned *S, uint8_t outlen );
+	int (*hash_update) ( unsigned *S, const uint8_t *in, unsigned inlen );
+	int (*hash_final) ( unsigned *S, uint8_t *out, uint8_t outlen );
+
+	// info API
+	void (*get_chip_id) (struct chip_id *id);
+	void (*get_chip_unique) (struct chip_unique_id *out);
+	int (*get_chip_security_context) (struct chip_security_context *context,
+                                          struct pubkey *pubkey);
+/* Return values */
+#define ROM_API_SECURITY_ENABLED      0
+#define ROM_API_SECURITY_DISABLED     1
+#define ROM_API_INVALID_KEYINDEX      2
+#define ROM_API_INVALID_VENDOR_ID     3
+#define ROM_API_SECURITY_UNAVAILABLE  4
+
+	// RND
+	void (*get_chip_true_random) (uint8_t *out, uint8_t outlen);
+
+	// NEW in v101:
+	int (*signature_open_w_hash)(uint8_t message_hash[64],
+                              const struct sig    *signature,
+                              const struct pubkey *pubkey);
+/* Return values */
+// same as signature_open() plus ROM_API_UNAVAILABLE if method is unavailable.
+#define ROM_API_UNAVAILABLE 100
+
+	// Future extension
+	unsigned dummy[19];
+};
+
+#ifndef BOOTROM
+
+// The ROMAPI is allocated either at 0x3f00 or 0xff00.
+// 8810  - 0xff00
+// 8810H - 0x3f00
+#ifndef ROMAPI_BASE
+#  define ROMAPI_BASE 0xff00
+#endif
+
+static const struct ROM_crypto_api *romapi = (void*)ROMAPI_BASE;
+
+
+// info API
+
+static void inline get_chip_id(struct chip_id *id)
+{
+	romapi->get_chip_id(id);
+}
+
+
+static inline void get_chip_unique(struct chip_unique_id *id )
+{
+	romapi->get_chip_unique(id);
+}
+
+/* Replaced with a enhanced version in arch/arm/rda/rda_romapi.c */
+int get_chip_security_context(struct chip_security_context *context, struct pubkey *pubkey);
+/*
+static inline int get_chip_security_context(struct chip_security_context *context, struct pubkey *pubkey)
+{
+	return romapi->get_chip_security_context(context, pubkey);
+}*/
+
+
+//
+// RND
+//
+static inline void get_chip_true_random(uint8_t *out, uint8_t outlen)
+{
+	romapi->get_chip_true_random(out, outlen);
+}
+
+//
+// SIGNATURE CHECK
+//
+static inline int signature_check(
+		const uint8_t *message, unsigned length,
+		const struct sig    *sig,
+		const struct pubkey *pubkey)
+{
+	return romapi->signature_open(message, length, sig, pubkey);
+}
+
+// NEW in v101:
+//
+// SIGNATURE CHECK variant that can be used to check larger than RAM messages
+//
+static inline int signature_check_w_hash(
+		uint8_t message_hash[64],
+		const struct sig    *sig,
+		const struct pubkey *pubkey)
+{
+	if (romapi->signature_open_w_hash)
+		return romapi->signature_open_w_hash(message_hash, sig, pubkey);
+	else
+		return ROM_API_UNAVAILABLE;
+}
+
+#endif
+#endif
diff --git a/arch/arm/include/asm/arch-rda/spl_board_info.h b/arch/arm/include/asm/arch-rda/spl_board_info.h
new file mode 100644
index 0000000000..f931d1bb06
--- /dev/null
+++ b/arch/arm/include/asm/arch-rda/spl_board_info.h
@@ -0,0 +1,43 @@
+#ifndef _SPL_BOARD_INFO_H_
+#define _SPL_BOARD_INFO_H_
+
+#include <asm/arch/rom_api_trampolin.h>
+
+/*!!!
+ *struct size must < CONFIG_SPL_BOARD_INFO_SIZE (512 bytes)
+ */
+typedef struct spl_bd_info {
+	struct {
+		unsigned long ddr_auto_cal_offs;
+		u16 ddr_auto_cal_flag;
+		u16 ddr_auto_cal_val[10];
+	} spl_ddr_cal_info;
+
+	struct spl_security_info {
+		u32                          version;
+		int                          secure_mode;
+		struct chip_id               chip_id;
+		struct chip_security_context chip_security_context;
+		struct chip_unique_id        chip_unique_id;
+		struct pubkey                pubkey;
+		u8                           random[32];
+	} spl_security_info;
+
+	struct spl_emmc_info{
+		u8 manufacturer_id;
+		u8 reserved[3];
+	} spl_emmc_info;
+} spl_bd_t;
+
+static inline spl_bd_t *get_spl_bd_info(void)
+{
+	spl_bd_t *p = (spl_bd_t *)CONFIG_SPL_BOARD_INFO_ADDR;
+
+	return p;
+}
+
+#define get_bd_spl_security_info() &get_spl_bd_info()->spl_security_info
+#define get_bd_spl_ddr_cal_info() &get_spl_bd_info()->spl_ddr_cal_info
+#define get_bd_spl_emmc_info() &get_spl_bd_info()->spl_emmc_info
+#endif	/* _SPL_BOARD_INFO_H_ */
+
diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
index adef4ee21d..0f701c9012 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
@@ -21,53 +21,54 @@
 #ifndef __ASM_ARCH_MMC_H_
 #define __ASM_ARCH_MMC_H_
 
-#ifndef __ASSEMBLY__
-struct s5p_mmc {
-	unsigned int	sysad;
-	unsigned short	blksize;
-	unsigned short	blkcnt;
-	unsigned int	argument;
-	unsigned short	trnmod;
-	unsigned short	cmdreg;
-	unsigned int	rspreg0;
-	unsigned int	rspreg1;
-	unsigned int	rspreg2;
-	unsigned int	rspreg3;
-	unsigned int	bdata;
-	unsigned int	prnsts;
-	unsigned char	hostctl;
-	unsigned char	pwrcon;
-	unsigned char	blkgap;
-	unsigned char	wakcon;
-	unsigned short	clkcon;
-	unsigned char	timeoutcon;
-	unsigned char	swrst;
-	unsigned int	norintsts;	/* errintsts */
-	unsigned int	norintstsen;	/* errintstsen */
-	unsigned int	norintsigen;	/* errintsigen */
-	unsigned short	acmd12errsts;
-	unsigned char	res1[2];
-	unsigned int	capareg;
-	unsigned char	res2[4];
-	unsigned int	maxcurr;
-	unsigned char	res3[0x34];
-	unsigned int	control2;
-	unsigned int	control3;
-	unsigned char	res4[4];
-	unsigned int	control4;
-	unsigned char	res5[0x6e];
-	unsigned short	hcver;
-	unsigned char	res6[0xFFF00];
-};
+#define SDHCI_CONTROL2		0x80
+#define SDHCI_CONTROL3		0x84
+#define SDHCI_CONTROL4		0x8C
 
-struct mmc_host {
-	struct s5p_mmc *reg;
-	unsigned int version;	/* SDHCI spec. version */
-	unsigned int clock;	/* Current clock (MHz) */
-	int dev_index;
-};
+#define SDHCI_CTRL2_ENSTAASYNCCLR	(1 << 31)
+#define SDHCI_CTRL2_ENCMDCNFMSK		(1 << 30)
+#define SDHCI_CTRL2_CDINVRXD3		(1 << 29)
+#define SDHCI_CTRL2_SLCARDOUT		(1 << 28)
 
-int s5p_mmc_init(int dev_index, int bus_width);
+#define SDHCI_CTRL2_FLTCLKSEL_MASK	(0xf << 24)
+#define SDHCI_CTRL2_FLTCLKSEL_SHIFT	(24)
+#define SDHCI_CTRL2_FLTCLKSEL(_x)	((_x) << 24)
 
-#endif	/* __ASSEMBLY__ */
+#define SDHCI_CTRL2_LVLDAT_MASK		(0xff << 16)
+#define SDHCI_CTRL2_LVLDAT_SHIFT	(16)
+#define SDHCI_CTRL2_LVLDAT(_x)		((_x) << 16)
+
+#define SDHCI_CTRL2_ENFBCLKTX		(1 << 15)
+#define SDHCI_CTRL2_ENFBCLKRX		(1 << 14)
+#define SDHCI_CTRL2_SDCDSEL		(1 << 13)
+#define SDHCI_CTRL2_SDSIGPC		(1 << 12)
+#define SDHCI_CTRL2_ENBUSYCHKTXSTART	(1 << 11)
+
+#define SDHCI_CTRL2_DFCNT_MASK(_x)	((_x) << 9)
+#define SDHCI_CTRL2_DFCNT_SHIFT		(9)
+
+#define SDHCI_CTRL2_ENCLKOUTHOLD	(1 << 8)
+#define SDHCI_CTRL2_RWAITMODE		(1 << 7)
+#define SDHCI_CTRL2_DISBUFRD		(1 << 6)
+#define SDHCI_CTRL2_SELBASECLK_MASK(_x)	((_x) << 4)
+#define SDHCI_CTRL2_SELBASECLK_SHIFT	(4)
+#define SDHCI_CTRL2_PWRSYNC		(1 << 3)
+#define SDHCI_CTRL2_ENCLKOUTMSKCON	(1 << 1)
+#define SDHCI_CTRL2_HWINITFIN		(1 << 0)
+
+#define SDHCI_CTRL3_FCSEL3		(1 << 31)
+#define SDHCI_CTRL3_FCSEL2		(1 << 23)
+#define SDHCI_CTRL3_FCSEL1		(1 << 15)
+#define SDHCI_CTRL3_FCSEL0		(1 << 7)
+
+#define SDHCI_CTRL4_DRIVE_MASK(_x)	((_x) << 16)
+#define SDHCI_CTRL4_DRIVE_SHIFT		(16)
+
+int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
+
+static inline unsigned int s5p_mmc_init(int index, int bus_width)
+{
+	unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
+	return s5p_sdhci_init(base, 52000000, 400000, index);
+}
 #endif
diff --git a/arch/arm/cpu/armv7/tegra2/ap20.h b/arch/arm/include/asm/arch-tegra2/ap20.h
index a4b4d73a40..d222c44233 100644
--- a/arch/arm/cpu/armv7/tegra2/ap20.h
+++ b/arch/arm/include/asm/arch-tegra2/ap20.h
@@ -100,3 +100,10 @@ void tegra2_start(void);
 
 /* This is the main entry into U-Boot, used by the Cortex-A9 */
 extern void _start(void);
+
+/**
+ * Works out the SOC type used for clocks settings
+ *
+ * @return	SOC type - see TEGRA_SOC...
+ */
+int tegra_get_chip_type(void);
diff --git a/arch/arm/include/asm/arch-tegra2/apb_misc.h b/arch/arm/include/asm/arch-tegra2/apb_misc.h
new file mode 100644
index 0000000000..eb69d18d01
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/apb_misc.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _GP_PADCTRL_H_
+#define _GP_PADCTRL_H_
+
+/* APB_MISC_PP registers */
+struct apb_misc_pp_ctlr {
+	u32	reserved0[2];
+	u32	strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */
+};
+
+/* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */
+#define RAM_CODE_SHIFT		4
+#define RAM_CODE_MASK		(0xf << RAM_CODE_SHIFT)
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h b/arch/arm/include/asm/arch-tegra2/clk_rst.h
index 415e420012..8c3be91514 100644
--- a/arch/arm/include/asm/arch-tegra2/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h
@@ -117,6 +117,7 @@ struct clk_rst_ctlr {
 #define PLL_CPCON_MASK		(15U << PLL_CPCON_SHIFT)
 
 #define PLL_LFCON_SHIFT		4
+#define PLL_LFCON_MASK		(15U << PLL_LFCON_SHIFT)
 
 #define PLLU_VCO_FREQ_SHIFT	20
 #define PLLU_VCO_FREQ_MASK	(1U << PLLU_VCO_FREQ_SHIFT)
@@ -124,6 +125,8 @@ struct clk_rst_ctlr {
 /* CLK_RST_CONTROLLER_OSC_CTRL_0 */
 #define OSC_FREQ_SHIFT		30
 #define OSC_FREQ_MASK		(3U << OSC_FREQ_SHIFT)
+#define OSC_XOBP_SHIFT		1
+#define OSC_XOBP_MASK		(1U << OSC_XOBP_SHIFT)
 
 /*
  * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits
diff --git a/arch/arm/include/asm/arch-tegra2/clock.h b/arch/arm/include/asm/arch-tegra2/clock.h
index 6b12c76e8d..1d3ae38644 100644
--- a/arch/arm/include/asm/arch-tegra2/clock.h
+++ b/arch/arm/include/asm/arch-tegra2/clock.h
@@ -210,6 +210,21 @@ enum clock_osc_freq clock_get_osc_freq(void);
 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
 		u32 divp, u32 cpcon, u32 lfcon);
 
+/**
+ * Read low-level parameters of a PLL.
+ *
+ * @param id	clock id to read (note: USB is not supported)
+ * @param divm	returns input divider
+ * @param divn	returns feedback divider
+ * @param divp	returns post divider 2^n
+ * @param cpcon	returns charge pump setup control
+ * @param lfcon	returns loop filter setup control
+ *
+ * @returns 0 if ok, -1 on error (invalid clock id)
+ */
+int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
+		      u32 *divp, u32 *cpcon, u32 *lfcon);
+
 /*
  * Enable a clock
  *
@@ -368,6 +383,13 @@ void clock_ll_start_uart(enum periph_id periph_id);
  */
 enum periph_id clock_decode_periph_id(const void *blob, int node);
 
+/**
+ * Checks if the oscillator bypass is enabled (XOBP bit)
+ *
+ * @return 1 if bypass is enabled, 0 if not
+ */
+int clock_get_osc_bypass(void);
+
 /*
  * Checks that clocks are valid and prints a warning if not
  *
diff --git a/arch/arm/include/asm/arch-tegra2/emc.h b/arch/arm/include/asm/arch-tegra2/emc.h
new file mode 100644
index 0000000000..deb3d36ed2
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/emc.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ARCH_EMC_H_
+#define _ARCH_EMC_H_
+
+#include <asm/types.h>
+
+#define TEGRA_EMC_NUM_REGS	46
+
+/* EMC Registers */
+struct emc_ctlr {
+	u32 cfg;		/* 0x00: EMC_CFG */
+	u32 reserved0[3];	/* 0x04 ~ 0x0C */
+	u32 adr_cfg;		/* 0x10: EMC_ADR_CFG */
+	u32 adr_cfg1;		/* 0x14: EMC_ADR_CFG_1 */
+	u32 reserved1[2];	/* 0x18 ~ 0x18 */
+	u32 refresh_ctrl;	/* 0x20: EMC_REFCTRL */
+	u32 pin;		/* 0x24: EMC_PIN */
+	u32 timing_ctrl;	/* 0x28: EMC_TIMING_CONTROL */
+	u32 rc;			/* 0x2C: EMC_RC */
+	u32 rfc;		/* 0x30: EMC_RFC */
+	u32 ras;		/* 0x34: EMC_RAS */
+	u32 rp;			/* 0x38: EMC_RP */
+	u32 r2w;		/* 0x3C: EMC_R2W */
+	u32 w2r;		/* 0x40: EMC_W2R */
+	u32 r2p;		/* 0x44: EMC_R2P */
+	u32 w2p;		/* 0x48: EMC_W2P */
+	u32 rd_rcd;		/* 0x4C: EMC_RD_RCD */
+	u32 wd_rcd;		/* 0x50: EMC_WD_RCD */
+	u32 rrd;		/* 0x54: EMC_RRD */
+	u32 rext;		/* 0x58: EMC_REXT */
+	u32 wdv;		/* 0x5C: EMC_WDV */
+	u32 quse;		/* 0x60: EMC_QUSE */
+	u32 qrst;		/* 0x64: EMC_QRST */
+	u32 qsafe;		/* 0x68: EMC_QSAFE */
+	u32 rdv;		/* 0x6C: EMC_RDV */
+	u32 refresh;		/* 0x70: EMC_REFRESH */
+	u32 burst_refresh_num;	/* 0x74: EMC_BURST_REFRESH_NUM */
+	u32 pdex2wr;		/* 0x78: EMC_PDEX2WR */
+	u32 pdex2rd;		/* 0x7c: EMC_PDEX2RD */
+	u32 pchg2pden;		/* 0x80: EMC_PCHG2PDEN */
+	u32 act2pden;		/* 0x84: EMC_ACT2PDEN */
+	u32 ar2pden;		/* 0x88: EMC_AR2PDEN */
+	u32 rw2pden;		/* 0x8C: EMC_RW2PDEN */
+	u32 txsr;		/* 0x90: EMC_TXSR */
+	u32 tcke;		/* 0x94: EMC_TCKE */
+	u32 tfaw;		/* 0x98: EMC_TFAW */
+	u32 trpab;		/* 0x9C: EMC_TRPAB */
+	u32 tclkstable;		/* 0xA0: EMC_TCLKSTABLE */
+	u32 tclkstop;		/* 0xA4: EMC_TCLKSTOP */
+	u32 trefbw;		/* 0xA8: EMC_TREFBW */
+	u32 quse_extra;		/* 0xAC: EMC_QUSE_EXTRA */
+	u32 odt_write;		/* 0xB0: EMC_ODT_WRITE */
+	u32 odt_read;		/* 0xB4: EMC_ODT_READ */
+	u32 reserved2[5];	/* 0xB8 ~ 0xC8 */
+	u32 mrs;		/* 0xCC: EMC_MRS */
+	u32 emrs;		/* 0xD0: EMC_EMRS */
+	u32 ref;		/* 0xD4: EMC_REF */
+	u32 pre;		/* 0xD8: EMC_PRE */
+	u32 nop;		/* 0xDC: EMC_NOP */
+	u32 self_ref;		/* 0xE0: EMC_SELF_REF */
+	u32 dpd;		/* 0xE4: EMC_DPD */
+	u32 mrw;		/* 0xE8: EMC_MRW */
+	u32 mrr;		/* 0xEC: EMC_MRR */
+	u32 reserved3;		/* 0xF0: */
+	u32 fbio_cfg1;		/* 0xF4: EMC_FBIO_CFG1 */
+	u32 fbio_dqsib_dly;	/* 0xF8: EMC_FBIO_DQSIB_DLY */
+	u32 fbio_dqsib_dly_msb;	/* 0xFC: EMC_FBIO_DQSIB_DLY_MSG */
+	u32 fbio_spare;		/* 0x100: SBIO_SPARE */
+				/* There are more registers ... */
+};
+
+/**
+ * Set up the EMC for the given rate. The timing parameters are retrieved
+ * from the device tree "nvidia,tegra20-emc" node and its
+ * "nvidia,tegra20-emc-table" sub-nodes.
+ *
+ * @param blob	Device tree blob
+ * @param rate	Clock speed of memory controller in Hz (=2x memory bus rate)
+ * @return 0 if ok, else -ve error code (look in emc.c to decode it)
+ */
+int tegra_set_emc(const void *blob, unsigned rate);
+
+/**
+ * Get a pointer to the EMC controller from the device tree.
+ *
+ * @param blob	Device tree blob
+ * @return pointer to EMC controller
+ */
+struct emc_ctlr *emc_get_controller(const void *blob);
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra2/flow.h b/arch/arm/include/asm/arch-tegra2/flow.h
new file mode 100644
index 0000000000..cce6cbf7d0
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/flow.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2010, 2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _FLOW_H_
+#define _FLOW_H_
+
+struct flow_ctlr {
+	u32	halt_cpu_events;
+	u32	halt_cop_events;
+	u32	cpu_csr;
+	u32	cop_csr;
+	u32	halt_cpu1_events;
+	u32	cpu1_csr;
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra2/fuse.h b/arch/arm/include/asm/arch-tegra2/fuse.h
new file mode 100644
index 0000000000..b7e3808a4f
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/fuse.h
@@ -0,0 +1,39 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _FUSE_H_
+#define _FUSE_H_
+
+/* FUSE registers */
+struct fuse_regs {
+	u32 reserved0[64];		/* 0x00 - 0xFC: */
+	u32 production_mode;		/* 0x100: FUSE_PRODUCTION_MODE */
+	u32 reserved1[3];		/* 0x104 - 0x10c: */
+	u32 sku_info;			/* 0x110 */
+	u32 reserved2[13];		/* 0x114 - 0x144: */
+	u32 fa;				/* 0x148: FUSE_FA */
+	u32 reserved3[21];		/* 0x14C - 0x19C: */
+	u32 security_mode;		/* 0x1A0: FUSE_SECURITY_MODE */
+};
+
+#endif	/* ifndef _FUSE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra2/gp_padctrl.h b/arch/arm/include/asm/arch-tegra2/gp_padctrl.h
new file mode 100644
index 0000000000..1755ab2eaa
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/gp_padctrl.h
@@ -0,0 +1,73 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _GP_PADCTRL_H_
+#define _GP_PADCTRL_H_
+
+/* APB_MISC_GP and padctrl registers */
+struct apb_misc_gp_ctlr {
+	u32	modereg;	/* 0x00: APB_MISC_GP_MODEREG */
+	u32	hidrev;		/* 0x04: APB_MISC_GP_HIDREV */
+	u32	reserved0[22];	/* 0x08 - 0x5C: */
+	u32	emu_revid;	/* 0x60: APB_MISC_GP_EMU_REVID */
+	u32	xactor_scratch;	/* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
+	u32	aocfg1;		/* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
+	u32	aocfg2;		/* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
+	u32	atcfg1;		/* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
+	u32	atcfg2;		/* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
+	u32	cdevcfg1;	/* 0x78: APB_MISC_GP_CDEV1CFGPADCTRL */
+	u32	cdevcfg2;	/* 0x7C: APB_MISC_GP_CDEV2CFGPADCTRL */
+	u32	csuscfg;	/* 0x80: APB_MISC_GP_CSUSCFGPADCTRL */
+	u32	dap1cfg;	/* 0x84: APB_MISC_GP_DAP1CFGPADCTRL */
+	u32	dap2cfg;	/* 0x88: APB_MISC_GP_DAP2CFGPADCTRL */
+	u32	dap3cfg;	/* 0x8C: APB_MISC_GP_DAP3CFGPADCTRL */
+	u32	dap4cfg;	/* 0x90: APB_MISC_GP_DAP4CFGPADCTRL */
+	u32	dbgcfg;		/* 0x94: APB_MISC_GP_DBGCFGPADCTRL */
+	u32	lcdcfg1;	/* 0x98: APB_MISC_GP_LCDCFG1PADCTRL */
+	u32	lcdcfg2;	/* 0x9C: APB_MISC_GP_LCDCFG2PADCTRL */
+	u32	sdmmc2_cfg;	/* 0xA0: APB_MISC_GP_SDMMC2CFGPADCTRL */
+	u32	sdmmc3_cfg;	/* 0xA4: APB_MISC_GP_SDMMC3CFGPADCTRL */
+	u32	spicfg;		/* 0xA8: APB_MISC_GP_SPICFGPADCTRL */
+	u32	uaacfg;		/* 0xAC: APB_MISC_GP_UAACFGPADCTRL */
+	u32	uabcfg;		/* 0xB0: APB_MISC_GP_UABCFGPADCTRL */
+	u32	uart2cfg;	/* 0xB4: APB_MISC_GP_UART2CFGPADCTRL */
+	u32	uart3cfg;	/* 0xB8: APB_MISC_GP_UART3CFGPADCTRL */
+	u32	vicfg1;		/* 0xBC: APB_MISC_GP_VICFG1PADCTRL */
+	u32	vicfg2;		/* 0xC0: APB_MISC_GP_VICFG2PADCTRL */
+	u32	xm2cfga;	/* 0xC4: APB_MISC_GP_XM2CFGAPADCTRL */
+	u32	xm2cfgc;	/* 0xC8: APB_MISC_GP_XM2CFGCPADCTRL */
+	u32	xm2cfgd;	/* 0xCC: APB_MISC_GP_XM2CFGDPADCTRL */
+	u32	xm2clkcfg;	/* 0xD0: APB_MISC_GP_XM2CLKCFGPADCTRL */
+	u32	memcomp;	/* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */
+};
+
+/* bit fields definitions for APB_MISC_GP_HIDREV register */
+#define HIDREV_CHIPID_SHIFT		8
+#define HIDREV_CHIPID_MASK		(0xff << HIDREV_CHIPID_SHIFT)
+#define HIDREV_MAJORPREV_SHIFT		4
+#define HIDREV_MAJORPREV_MASK		(0xf << HIDREV_MAJORPREV_SHIFT)
+
+/* CHIPID field returned from APB_MISC_GP_HIDREV register */
+#define CHIPID_TEGRA2				0x20
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra2/pmu.h b/arch/arm/include/asm/arch-tegra2/pmu.h
new file mode 100644
index 0000000000..390815fc24
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/pmu.h
@@ -0,0 +1,30 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ARCH_PMU_H_
+#define _ARCH_PMU_H_
+
+/* Set core and CPU voltages to nominal levels */
+int pmu_set_nominal(void);
+
+#endif	/* _ARCH_PMU_H_ */
diff --git a/arch/arm/include/asm/arch-tegra2/sdram_param.h b/arch/arm/include/asm/arch-tegra2/sdram_param.h
new file mode 100644
index 0000000000..6c427d0841
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/sdram_param.h
@@ -0,0 +1,148 @@
+/*
+ *  (C) Copyright 2010, 2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SDRAM_PARAM_H_
+#define _SDRAM_PARAM_H_
+
+/*
+ * Defines the number of 32-bit words provided in each set of SDRAM parameters
+ * for arbitration configuration data.
+ */
+#define BCT_SDRAM_ARB_CONFIG_WORDS 27
+
+enum memory_type {
+	MEMORY_TYPE_NONE = 0,
+	MEMORY_TYPE_DDR,
+	MEMORY_TYPE_LPDDR,
+	MEMORY_TYPE_DDR2,
+	MEMORY_TYPE_LPDDR2,
+	MEMORY_TYPE_NUM,
+	MEMORY_TYPE_FORCE32 = 0x7FFFFFFF
+};
+
+/* Defines the SDRAM parameter structure */
+struct sdram_params {
+	enum memory_type memory_type;
+	u32 pllm_charge_pump_setup_control;
+	u32 pllm_loop_filter_setup_control;
+	u32 pllm_input_divider;
+	u32 pllm_feedback_divider;
+	u32 pllm_post_divider;
+	u32 pllm_stable_time;
+	u32 emc_clock_divider;
+	u32 emc_auto_cal_interval;
+	u32 emc_auto_cal_config;
+	u32 emc_auto_cal_wait;
+	u32 emc_pin_program_wait;
+	u32 emc_rc;
+	u32 emc_rfc;
+	u32 emc_ras;
+	u32 emc_rp;
+	u32 emc_r2w;
+	u32 emc_w2r;
+	u32 emc_r2p;
+	u32 emc_w2p;
+	u32 emc_rd_rcd;
+	u32 emc_wr_rcd;
+	u32 emc_rrd;
+	u32 emc_rext;
+	u32 emc_wdv;
+	u32 emc_quse;
+	u32 emc_qrst;
+	u32 emc_qsafe;
+	u32 emc_rdv;
+	u32 emc_refresh;
+	u32 emc_burst_refresh_num;
+	u32 emc_pdex2wr;
+	u32 emc_pdex2rd;
+	u32 emc_pchg2pden;
+	u32 emc_act2pden;
+	u32 emc_ar2pden;
+	u32 emc_rw2pden;
+	u32 emc_txsr;
+	u32 emc_tcke;
+	u32 emc_tfaw;
+	u32 emc_trpab;
+	u32 emc_tclkstable;
+	u32 emc_tclkstop;
+	u32 emc_trefbw;
+	u32 emc_quseextra;
+	u32 emc_fbioc_fg1;
+	u32 emc_fbio_dqsib_dly;
+	u32 emc_fbio_dqsib_dly_msb;
+	u32 emc_fbio_quse_dly;
+	u32 emc_fbio_quse_dly_msb;
+	u32 emc_fbio_cfg5;
+	u32 emc_fbio_cfg6;
+	u32 emc_fbio_spare;
+	u32 emc_mrs;
+	u32 emc_emrs;
+	u32 emc_mrw1;
+	u32 emc_mrw2;
+	u32 emc_mrw3;
+	u32 emc_mrw_reset_command;
+	u32 emc_mrw_reset_init_wait;
+	u32 emc_adr_cfg;
+	u32 emc_adr_cfg1;
+	u32 emc_emem_cfg;
+	u32 emc_low_latency_config;
+	u32 emc_cfg;
+	u32 emc_cfg2;
+	u32 emc_dbg;
+	u32 ahb_arbitration_xbar_ctrl;
+	u32 emc_cfg_dig_dll;
+	u32 emc_dll_xform_dqs;
+	u32 emc_dll_xform_quse;
+	u32 warm_boot_wait;
+	u32 emc_ctt_term_ctrl;
+	u32 emc_odt_write;
+	u32 emc_odt_read;
+	u32 emc_zcal_ref_cnt;
+	u32 emc_zcal_wait_cnt;
+	u32 emc_zcal_mrw_cmd;
+	u32 emc_mrs_reset_dll;
+	u32 emc_mrw_zq_init_dev0;
+	u32 emc_mrw_zq_init_dev1;
+	u32 emc_mrw_zq_init_wait;
+	u32 emc_mrs_reset_dll_wait;
+	u32 emc_emrs_emr2;
+	u32 emc_emrs_emr3;
+	u32 emc_emrs_ddr2_dll_enable;
+	u32 emc_mrs_ddr2_dll_reset;
+	u32 emc_emrs_ddr2_ocd_calib;
+	u32 emc_edr2_wait;
+	u32 emc_cfg_clktrim0;
+	u32 emc_cfg_clktrim1;
+	u32 emc_cfg_clktrim2;
+	u32 pmc_ddr_pwr;
+	u32 apb_misc_gp_xm2cfga_padctrl;
+	u32 apb_misc_gp_xm2cfgc_padctrl;
+	u32 apb_misc_gp_xm2cfgc_padctrl2;
+	u32 apb_misc_gp_xm2cfgd_padctrl;
+	u32 apb_misc_gp_xm2cfgd_padctrl2;
+	u32 apb_misc_gp_xm2clkcfg_padctrl;
+	u32 apb_misc_gp_xm2comp_padctrl;
+	u32 apb_misc_gp_xm2vttgen_padctrl;
+	u32 arbitration_config[BCT_SDRAM_ARB_CONFIG_WORDS];
+};
+#endif
diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h
index ca1881e3a2..d4ada10ea8 100644
--- a/arch/arm/include/asm/arch-tegra2/tegra2.h
+++ b/arch/arm/include/asm/arch-tegra2/tegra2.h
@@ -33,6 +33,7 @@
 #define NV_PA_GPIO_BASE		0x6000D000
 #define NV_PA_EVP_BASE		0x6000F000
 #define NV_PA_APB_MISC_BASE	0x70000000
+#define TEGRA2_APB_MISC_GP_BASE	(NV_PA_APB_MISC_BASE + 0x0800)
 #define NV_PA_APB_UARTA_BASE	(NV_PA_APB_MISC_BASE + 0x6000)
 #define NV_PA_APB_UARTB_BASE	(NV_PA_APB_MISC_BASE + 0x6040)
 #define NV_PA_APB_UARTC_BASE	(NV_PA_APB_MISC_BASE + 0x6200)
@@ -40,6 +41,7 @@
 #define NV_PA_APB_UARTE_BASE	(NV_PA_APB_MISC_BASE + 0x6400)
 #define TEGRA2_SPI_BASE		(NV_PA_APB_MISC_BASE + 0xC380)
 #define TEGRA2_PMC_BASE		(NV_PA_APB_MISC_BASE + 0xE400)
+#define TEGRA2_FUSE_BASE	(NV_PA_APB_MISC_BASE + 0xF800)
 #define NV_PA_CSITE_BASE	0x70040000
 #define TEGRA_USB1_BASE		0xC5000000
 #define TEGRA_USB3_BASE		0xC5008000
@@ -54,6 +56,29 @@
 struct timerus {
 	unsigned int cntr_1us;
 };
+
+/* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
+#define AP20_WB_RUN_ADDRESS	0x40020000
+
+/* These are the available SKUs (product types) for Tegra */
+enum {
+	SKU_ID_T20		= 0x8,
+	SKU_ID_T25SE		= 0x14,
+	SKU_ID_AP25		= 0x17,
+	SKU_ID_T25		= 0x18,
+	SKU_ID_AP25E		= 0x1b,
+	SKU_ID_T25E		= 0x1c,
+};
+
+/* These are the SOC categories that affect clocking */
+enum {
+	TEGRA_SOC_T20,
+	TEGRA_SOC_T25,
+
+	TEGRA_SOC_COUNT,
+	TEGRA_SOC_UNKNOWN	= -1,
+};
+
 #else  /* __ASSEMBLY__ */
 #define PRM_RSTCTRL		TEGRA2_PMC_BASE
 #endif
diff --git a/arch/arm/include/asm/arch-tegra2/tegra_i2c.h b/arch/arm/include/asm/arch-tegra2/tegra_i2c.h
index 0a7d99c585..cfb136c466 100644
--- a/arch/arm/include/asm/arch-tegra2/tegra_i2c.h
+++ b/arch/arm/include/asm/arch-tegra2/tegra_i2c.h
@@ -154,4 +154,11 @@ struct i2c_ctlr {
 #define I2C_INT_ARBITRATION_LOST_SHIFT	2
 #define I2C_INT_ARBITRATION_LOST_MASK	(1 << I2C_INT_ARBITRATION_LOST_SHIFT)
 
+/**
+ * Returns the bus number of the DVC controller
+ *
+ * @return number of bus, or -1 if there is no DVC active
+ */
+int tegra_i2c_get_dvc_bus_num(void);
+
 #endif
diff --git a/arch/arm/include/asm/arch-tegra2/warmboot.h b/arch/arm/include/asm/arch-tegra2/warmboot.h
new file mode 100644
index 0000000000..99ac2e7d23
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/warmboot.h
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2010, 2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _WARM_BOOT_H_
+#define _WARM_BOOT_H_
+
+#define STRAP_OPT_A_RAM_CODE_SHIFT	4
+#define STRAP_OPT_A_RAM_CODE_MASK	(0xf << STRAP_OPT_A_RAM_CODE_SHIFT)
+
+/* Defines the supported operating modes */
+enum fuse_operating_mode {
+	MODE_PRODUCTION = 3,
+	MODE_UNDEFINED,
+};
+
+/* Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) */
+enum {
+	HASH_LENGTH = 4
+};
+
+/* Defines the storage for a hash value (128 bits) */
+struct hash {
+	u32 hash[HASH_LENGTH];
+};
+
+/*
+ * Defines the code header information for the boot rom.
+ *
+ * The code immediately follows the code header.
+ *
+ * Note that the code header needs to be 16 bytes aligned to preserve
+ * the alignment of relevant data for hash and decryption computations without
+ * requiring extra copies to temporary memory areas.
+ */
+struct wb_header {
+	u32 length_insecure;	/* length of the code header */
+	u32 reserved[3];
+	struct hash hash;	/* hash of header+code, starts next field*/
+	struct hash random_aes_block;	/* a data block to aid security. */
+	u32 length_secure;	/* length of the code header */
+	u32 destination;	/* destination address to put the wb code */
+	u32 entry_point;	/* execution address of the wb code */
+	u32 code_length;	/* length of the code */
+};
+
+/*
+ * The warm boot code needs direct access to these registers since it runs in
+ * SRAM and cannot call other U-Boot code.
+ */
+union osc_ctrl_reg {
+	struct {
+		u32 xoe:1;
+		u32 xobp:1;
+		u32 reserved0:2;
+		u32 xofs:6;
+		u32 reserved1:2;
+		u32 xods:5;
+		u32 reserved2:3;
+		u32 oscfi_spare:8;
+		u32 pll_ref_div:2;
+		u32 osc_freq:2;
+	};
+	u32 word;
+};
+
+union pllx_base_reg {
+	struct {
+		u32 divm:5;
+		u32 reserved0:3;
+		u32 divn:10;
+		u32 reserved1:2;
+		u32 divp:3;
+		u32 reserved2:4;
+		u32 lock:1;
+		u32 reserved3:1;
+		u32 ref_dis:1;
+		u32 enable:1;
+		u32 bypass:1;
+	};
+	u32 word;
+};
+
+union pllx_misc_reg {
+	struct {
+		u32 vcocon:4;
+		u32 lfcon:4;
+		u32 cpcon:4;
+		u32 lock_sel:6;
+		u32 reserved0:1;
+		u32 lock_enable:1;
+		u32 reserved1:1;
+		u32 dccon:1;
+		u32 pts:2;
+		u32 reserved2:6;
+		u32 out1_div_byp:1;
+		u32 out1_inv_clk:1;
+	};
+	u32 word;
+};
+
+/*
+ * TODO: This register is not documented in the TRM yet. We could move this
+ * into the EMC and give it a proper interface, but not while it is
+ * undocumented.
+ */
+union scratch3_reg {
+	struct {
+		u32 pllx_base_divm:5;
+		u32 pllx_base_divn:10;
+		u32 pllx_base_divp:3;
+		u32 pllx_misc_lfcon:4;
+		u32 pllx_misc_cpcon:4;
+	};
+	u32 word;
+};
+
+
+/**
+ * Save warmboot memory settings for a later resume
+ *
+ * @return 0 if ok, -1 on error
+ */
+int warmboot_save_sdram_params(void);
+
+int warmboot_prepare_code(u32 seg_address, u32 seg_length);
+int sign_data_block(u8 *source, u32 length, u8 *signature);
+void wb_start(void);	/* Start of WB assembly code */
+void wb_end(void);	/* End of WB assembly code */
+
+#endif
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index 5bbb0a0464..fb3a013c20 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -31,6 +31,8 @@ enum dma_data_direction {
 };
 
 static void *dma_alloc_coherent(size_t len, unsigned long *handle)
+__attribute__((unused));
+static void *dma_alloc_coherent(size_t len, unsigned long *handle)
 {
 	*handle = (unsigned long)malloc(len);
 	return (void *)*handle;
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index e5c7d2cabe..f1e3ad212e 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -226,8 +226,8 @@
 #define EMIF_REG_CS_TIM_MASK			(0xf << 0)
 
 /* PWR_MGMT_CTRL_SHDW */
-#define EMIF_REG_PD_TIM_SHDW_SHIFT			8
-#define EMIF_REG_PD_TIM_SHDW_MASK			(0xf << 8)
+#define EMIF_REG_PD_TIM_SHDW_SHIFT			12
+#define EMIF_REG_PD_TIM_SHDW_MASK			(0xf << 12)
 #define EMIF_REG_SR_TIM_SHDW_SHIFT			4
 #define EMIF_REG_SR_TIM_SHDW_MASK			(0xf << 4)
 #define EMIF_REG_CS_TIM_SHDW_SHIFT			0
@@ -530,6 +530,8 @@
 	(DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)|\
 	(0xFF << EMIF_SYS_ADDR_SHIFT))
 
+#define EMIF_EXT_PHY_CTRL_TIMING_REG	0x5
+#define EMIF_EXT_PHY_CTRL_CONST_REG	0x13
 
 /* Reg mapping structure */
 struct emif_reg_struct {
@@ -580,10 +582,64 @@ struct emif_reg_struct {
 	u32 emif_zq_config;
 	u32 emif_temp_alert_config;
 	u32 emif_l3_err_log;
-	u32 padding6[4];
+	u32 emif_rd_wr_lvl_rmp_win;
+	u32 emif_rd_wr_lvl_rmp_ctl;
+	u32 emif_rd_wr_lvl_ctl;
+	u32 padding6[1];
 	u32 emif_ddr_phy_ctrl_1;
 	u32 emif_ddr_phy_ctrl_1_shdw;
 	u32 emif_ddr_phy_ctrl_2;
+	u32 padding7[12];
+	u32 emif_rd_wr_exec_thresh;
+	u32 padding8[55];
+	u32 emif_ddr_ext_phy_ctrl_1;
+	u32 emif_ddr_ext_phy_ctrl_1_shdw;
+	u32 emif_ddr_ext_phy_ctrl_2;
+	u32 emif_ddr_ext_phy_ctrl_2_shdw;
+	u32 emif_ddr_ext_phy_ctrl_3;
+	u32 emif_ddr_ext_phy_ctrl_3_shdw;
+	u32 emif_ddr_ext_phy_ctrl_4;
+	u32 emif_ddr_ext_phy_ctrl_4_shdw;
+	u32 emif_ddr_ext_phy_ctrl_5;
+	u32 emif_ddr_ext_phy_ctrl_5_shdw;
+	u32 emif_ddr_ext_phy_ctrl_6;
+	u32 emif_ddr_ext_phy_ctrl_6_shdw;
+	u32 emif_ddr_ext_phy_ctrl_7;
+	u32 emif_ddr_ext_phy_ctrl_7_shdw;
+	u32 emif_ddr_ext_phy_ctrl_8;
+	u32 emif_ddr_ext_phy_ctrl_8_shdw;
+	u32 emif_ddr_ext_phy_ctrl_9;
+	u32 emif_ddr_ext_phy_ctrl_9_shdw;
+	u32 emif_ddr_ext_phy_ctrl_10;
+	u32 emif_ddr_ext_phy_ctrl_10_shdw;
+	u32 emif_ddr_ext_phy_ctrl_11;
+	u32 emif_ddr_ext_phy_ctrl_11_shdw;
+	u32 emif_ddr_ext_phy_ctrl_12;
+	u32 emif_ddr_ext_phy_ctrl_12_shdw;
+	u32 emif_ddr_ext_phy_ctrl_13;
+	u32 emif_ddr_ext_phy_ctrl_13_shdw;
+	u32 emif_ddr_ext_phy_ctrl_14;
+	u32 emif_ddr_ext_phy_ctrl_14_shdw;
+	u32 emif_ddr_ext_phy_ctrl_15;
+	u32 emif_ddr_ext_phy_ctrl_15_shdw;
+	u32 emif_ddr_ext_phy_ctrl_16;
+	u32 emif_ddr_ext_phy_ctrl_16_shdw;
+	u32 emif_ddr_ext_phy_ctrl_17;
+	u32 emif_ddr_ext_phy_ctrl_17_shdw;
+	u32 emif_ddr_ext_phy_ctrl_18;
+	u32 emif_ddr_ext_phy_ctrl_18_shdw;
+	u32 emif_ddr_ext_phy_ctrl_19;
+	u32 emif_ddr_ext_phy_ctrl_19_shdw;
+	u32 emif_ddr_ext_phy_ctrl_20;
+	u32 emif_ddr_ext_phy_ctrl_20_shdw;
+	u32 emif_ddr_ext_phy_ctrl_21;
+	u32 emif_ddr_ext_phy_ctrl_21_shdw;
+	u32 emif_ddr_ext_phy_ctrl_22;
+	u32 emif_ddr_ext_phy_ctrl_22_shdw;
+	u32 emif_ddr_ext_phy_ctrl_23;
+	u32 emif_ddr_ext_phy_ctrl_23_shdw;
+	u32 emif_ddr_ext_phy_ctrl_24;
+	u32 emif_ddr_ext_phy_ctrl_24_shdw;
 };
 
 struct dmm_lisa_map_regs {
@@ -593,6 +649,8 @@ struct dmm_lisa_map_regs {
 	u32 dmm_lisa_map_3;
 };
 
+extern const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
+
 #define CS0	0
 #define CS1	1
 /* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
@@ -748,7 +806,11 @@ struct dmm_lisa_map_regs {
 #define DPD_ENABLE	1
 
 /* Maximum delay before Low Power Modes */
+#ifndef CONFIG_OMAP54XX
 #define REG_CS_TIM		0xF
+#else
+#define REG_CS_TIM		0x0
+#endif
 #define REG_SR_TIM		0xF
 #define REG_PD_TIM		0xF
 
@@ -776,7 +838,7 @@ struct dmm_lisa_map_regs {
 /* EMIF_L3_CONFIG register value */
 #define EMIF_L3_CONFIG_VAL_SYS_10_LL_0	0x0A0000FF
 #define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0	0x0A300000
-#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0	0x0A300000
+#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0	0x0A500000
 
 /*
  * Value of bits 12:31 of DDR_PHY_CTRL_1 register:
@@ -798,6 +860,7 @@ struct dmm_lisa_map_regs {
 *		: So nWR is don't care
 */
 #define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3	0x23
+#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8	0xc3
 
 /* MR2 */
 #define MR2_RL3_WL1			1
@@ -1005,6 +1068,11 @@ struct emif_regs {
 	u32 temp_alert_config;
 	u32 emif_ddr_phy_ctlr_1_init;
 	u32 emif_ddr_phy_ctlr_1;
+	u32 emif_ddr_ext_phy_ctrl_1;
+	u32 emif_ddr_ext_phy_ctrl_2;
+	u32 emif_ddr_ext_phy_ctrl_3;
+	u32 emif_ddr_ext_phy_ctrl_4;
+	u32 emif_ddr_ext_phy_ctrl_5;
 };
 
 /* assert macros */
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 1fbc531a08..5f5f8d038f 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -75,42 +75,42 @@ static inline phys_addr_t virt_to_phys(void * vaddr)
 #define __arch_putw(v,a)		(*(volatile unsigned short *)(a) = (v))
 #define __arch_putl(v,a)		(*(volatile unsigned int *)(a) = (v))
 
-extern inline void __raw_writesb(unsigned int addr, const void *data, int bytelen)
+static inline void __raw_writesb(unsigned int addr, const void *data, int bytelen)
 {
 	uint8_t *buf = (uint8_t *)data;
 	while(bytelen--)
 		__arch_putb(*buf++, addr);
 }
 
-extern inline void __raw_writesw(unsigned int addr, const void *data, int wordlen)
+static inline void __raw_writesw(unsigned int addr, const void *data, int wordlen)
 {
 	uint16_t *buf = (uint16_t *)data;
 	while(wordlen--)
 		__arch_putw(*buf++, addr);
 }
 
-extern inline void __raw_writesl(unsigned int addr, const void *data, int longlen)
+static inline void __raw_writesl(unsigned int addr, const void *data, int longlen)
 {
 	uint32_t *buf = (uint32_t *)data;
 	while(longlen--)
 		__arch_putl(*buf++, addr);
 }
 
-extern inline void __raw_readsb(unsigned int addr, void *data, int bytelen)
+static inline void __raw_readsb(unsigned int addr, void *data, int bytelen)
 {
 	uint8_t *buf = (uint8_t *)data;
 	while(bytelen--)
 		*buf++ = __arch_getb(addr);
 }
 
-extern inline void __raw_readsw(unsigned int addr, void *data, int wordlen)
+static inline void __raw_readsw(unsigned int addr, void *data, int wordlen)
 {
 	uint16_t *buf = (uint16_t *)data;
 	while(wordlen--)
 		*buf++ = __arch_getw(addr);
 }
 
-extern inline void __raw_readsl(unsigned int addr, void *data, int longlen)
+static inline void __raw_readsl(unsigned int addr, void *data, int longlen)
 {
 	uint32_t *buf = (uint32_t *)data;
 	while(longlen--)
diff --git a/arch/arm/include/asm/linkage.h b/arch/arm/include/asm/linkage.h
new file mode 100644
index 0000000000..dbe4b4e31a
--- /dev/null
+++ b/arch/arm/include/asm/linkage.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+#define __ALIGN .align 0
+#define __ALIGN_STR ".align 0"
+
+#endif
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
index 2d5c3bc376..47ab00aca0 100644
--- a/arch/arm/include/asm/mach-types.h
+++ b/arch/arm/include/asm/mach-types.h
@@ -1105,6 +1105,13 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_UBISYS_P9D_EVP       3493
 #define MACH_TYPE_ATDGP318             3494
 #define MACH_TYPE_OMAP5_SEVM           3777
+#define MACH_TYPE_RDAARM926EJS         5001
+#define MACH_TYPE_RDA8810              5002
+#define MACH_TYPE_RDA8810E             5003
+#define MACH_TYPE_RDA8820              5004
+#define MACH_TYPE_RDA8850              5005
+#define MACH_TYPE_RDA8850E              5006
+#define MACH_TYPE_RDA8810H              5007
 
 #ifdef CONFIG_ARCH_EBSA110
 # ifdef machine_arch_type
@@ -14222,6 +14229,89 @@ extern unsigned int __machine_arch_type;
 # define machine_is_omap5_sevm()      (0)
 #endif
 
+#ifdef CONFIG_MACH_RDAARM926EJS
+#ifdef machine_arch_type
+#undef machine_arch_type
+#define machine_arch_type	__machine_arch_type
+#else
+#define machine_arch_type	MACH_TYPE_RDAARM926EJS
+#endif
+#define machine_is_rdaarm926ejs()	(machine_arch_type == MACH_TYPE_RDAARM926EJS)
+#else
+#define machine_is_rdaarm926ejs()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RDA8810
+#ifdef machine_arch_type
+#undef machine_arch_type
+#define machine_arch_type	__machine_arch_type
+#else
+#define machine_arch_type	MACH_TYPE_RDA8810
+#endif
+#define machine_is_rda8810()	(machine_arch_type == MACH_TYPE_RDA8810)
+#else
+#define machine_is_rda8810()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RDA8810E
+#ifdef machine_arch_type
+#undef machine_arch_type
+#define machine_arch_type	__machine_arch_type
+#else
+#define machine_arch_type	MACH_TYPE_RDA8810E
+#endif
+#define machine_is_rda8810e()	(machine_arch_type == MACH_TYPE_RDA8810E)
+#else
+#define machine_is_rda8810e()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RDA8820
+#ifdef machine_arch_type
+#undef machine_arch_type
+#define machine_arch_type	__machine_arch_type
+#else
+#define machine_arch_type	MACH_TYPE_RDA8820
+#endif
+#define machine_is_rda8820()	(machine_arch_type == MACH_TYPE_RDA8820)
+#else
+#define machine_is_rda8820()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RDA8850
+#ifdef machine_arch_type
+#undef machine_arch_type
+#define machine_arch_type	__machine_arch_type
+#else
+#define machine_arch_type	MACH_TYPE_RDA8850
+#endif
+#define machine_is_rda8850()	(machine_arch_type == MACH_TYPE_RDA8850)
+#else
+#define machine_is_rda8850()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RDA8850E
+#ifdef machine_arch_type
+#undef machine_arch_type
+#define machine_arch_type	__machine_arch_type
+#else
+#define machine_arch_type	MACH_TYPE_RDA8850E
+#endif
+#define machine_is_rda8850E()	(machine_arch_type == MACH_TYPE_RDA8850E)
+#else
+#define machine_is_rda8850E()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RDA8810H
+#ifdef machine_arch_type
+#undef machine_arch_type
+#define machine_arch_type	__machine_arch_type
+#else
+#define machine_arch_type	MACH_TYPE_RDA8810H
+#endif
+#define machine_is_rda8810h()	(machine_arch_type == MACH_TYPE_RDA8810H)
+#else
+#define machine_is_rda8810h()	(0)
+#endif
 /*
  * These have not yet been registered
  */
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 6f25948e20..459b6b16e2 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -45,7 +45,7 @@ void preloader_console_init(void);
 #define BOOT_DEVICE_ONE_NAND    4
 #define BOOT_DEVICE_MMC1        5
 #define BOOT_DEVICE_MMC2        6
-#define BOOT_DEVICE_MMC3	7
+#define BOOT_DEVICE_MMC2_2	7
 #elif defined(CONFIG_OMAP44XX) /* OMAP4 */
 #define BOOT_DEVICE_NONE	0
 #define BOOT_DEVICE_XIP		1
@@ -54,6 +54,7 @@ void preloader_console_init(void);
 #define BOOT_DEVICE_ONE_NAND	4
 #define BOOT_DEVICE_MMC1	5
 #define BOOT_DEVICE_MMC2	6
+#define BOOT_DEVICE_MMC2_2	0xFF
 #elif defined(CONFIG_OMAP34XX)	/* OMAP3 */
 #define BOOT_DEVICE_NONE	0
 #define BOOT_DEVICE_XIP		1
@@ -62,11 +63,13 @@ void preloader_console_init(void);
 #define BOOT_DEVICE_MMC2	5 /*emmc*/
 #define BOOT_DEVICE_MMC1	6
 #define BOOT_DEVICE_XIPWAIT	7
+#define BOOT_DEVICE_MMC2_2      0xFF
 #elif defined(CONFIG_AM33XX)	/* AM33XX */
 #define BOOT_DEVICE_NAND	5
 #define BOOT_DEVICE_MMC1	8
 #define BOOT_DEVICE_MMC2	0
 #define BOOT_DEVICE_UART	65
+#define BOOT_DEVICE_MMC2_2      0xFF
 #endif
 
 /* Boot type */
@@ -108,6 +111,12 @@ void spl_ymodem_load_image(void);
 void spl_board_init(void);
 #endif
 
+static inline u32 omap_revision(void)
+{
+	extern u32 *const omap_si_rev;
+	return *omap_si_rev;
+}
+
 /*
  * silicon revisions.
  * Moving this to common, so that most of code can be moved to common,
diff --git a/arch/arm/include/asm/proc b/arch/arm/include/asm/proc
new file mode 120000
index 0000000000..c7f3c20248
--- /dev/null
+++ b/arch/arm/include/asm/proc
@@ -0,0 +1 @@
+proc-armv
\ No newline at end of file
diff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h
index 20e1653930..eac3800729 100644
--- a/arch/arm/include/asm/u-boot.h
+++ b/arch/arm/include/asm/u-boot.h
@@ -38,7 +38,6 @@
 
 typedef struct bd_info {
     int			bi_baudrate;	/* serial console baudrate */
-    unsigned long	bi_ip_addr;	/* IP Address */
     ulong	        bi_arch_number;	/* unique id for this board */
     ulong	        bi_boot_params;	/* where this board expects params */
 	unsigned long	bi_arm_freq; /* arm frequency */
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 5270c11262..3bb303ec31 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -64,6 +64,9 @@
 #include "../drivers/net/lan91c96.h"
 #endif
 
+/* For test nand easily */
+//#define DO_TEST_NAND_EASILY
+
 DECLARE_GLOBAL_DATA_PTR;
 
 ulong monitor_flash_len;
@@ -454,7 +457,9 @@ static char *failed = "*** failed ***\n";
  *
  ************************************************************************
  */
-
+#ifdef TGT_AP_DO_NAND_TEST
+extern void test_nand_easily(void);
+#endif
 void board_init_r(gd_t *id, ulong dest_addr)
 {
 	ulong malloc_start;
@@ -532,6 +537,11 @@ void board_init_r(gd_t *id, ulong dest_addr)
 #if defined(CONFIG_CMD_NAND)
 	puts("NAND:  ");
 	nand_init();		/* go init the NAND */
+
+#ifdef TGT_AP_DO_NAND_TEST
+	test_nand_easily();
+#endif
+
 #endif
 
 #if defined(CONFIG_CMD_ONENAND)
@@ -555,9 +565,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
 	arm_pci_init();
 #endif
 
-	/* IP Address */
-	gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
-
 	stdio_init();	/* get the devices list going. */
 
 	jumptable_init();
@@ -595,14 +602,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
 
 	/* Initialize from environment */
 	load_addr = getenv_ulong("loadaddr", 16, load_addr);
-#if defined(CONFIG_CMD_NET)
-	{
-		char *s = getenv("bootfile");
-
-		if (s != NULL)
-			copy_filename(BootFile, s, sizeof(BootFile));
-	}
-#endif
 
 #ifdef CONFIG_BOARD_LATE_INIT
 	board_late_init();
@@ -646,7 +645,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
 		setenv("mem", (char *)memsz);
 	}
 #endif
-
 	/* main_loop() can return to retry autoboot, if so just run it again. */
 	for (;;) {
 		main_loop();
diff --git a/arch/avr32/include/asm/u-boot.h b/arch/avr32/include/asm/u-boot.h
index ff1ed23db9..1d2959a2ad 100644
--- a/arch/avr32/include/asm/u-boot.h
+++ b/arch/avr32/include/asm/u-boot.h
@@ -24,7 +24,6 @@
 
 typedef struct bd_info {
 	unsigned long		bi_baudrate;
-	unsigned long		bi_ip_addr;
 	unsigned char		bi_phy_id[4];
 	unsigned long		bi_board_number;
 	void			*bi_boot_params;
diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c
index d626c29c00..b390a6c8f8 100644
--- a/arch/avr32/lib/board.c
+++ b/arch/avr32/lib/board.c
@@ -316,8 +316,6 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
 	/* initialize environment */
 	env_relocate();
 
-	bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
-
 	stdio_init();
 	jumptable_init();
 	console_init_r();
@@ -329,9 +327,6 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
 	bb_miiphy_init();
 #endif
 #if defined(CONFIG_CMD_NET)
-	s = getenv("bootfile");
-	if (s)
-		copy_filename(BootFile, s, sizeof(BootFile));
 	puts("Net:   ");
 	eth_initialize(gd->bd);
 #endif
diff --git a/arch/blackfin/cpu/.gitignore b/arch/blackfin/cpu/.gitignore
deleted file mode 100644
index ba986d8ba8..0000000000
--- a/arch/blackfin/cpu/.gitignore
+++ /dev/null
@@ -1,4 +0,0 @@
-bootrom-asm-offsets.[chs]
-
-init.lds
-init.elf
diff --git a/arch/blackfin/cpu/bootrom-asm-offsets.awk b/arch/blackfin/cpu/bootrom-asm-offsets.awk
index 1d61824254..1d61824254 100755..100644
--- a/arch/blackfin/cpu/bootrom-asm-offsets.awk
+++ b/arch/blackfin/cpu/bootrom-asm-offsets.awk
diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h
index 1a8de4906d..25cd833865 100644
--- a/arch/blackfin/include/asm/config.h
+++ b/arch/blackfin/include/asm/config.h
@@ -109,14 +109,8 @@
 #ifndef CONFIG_SYS_MALLOC_BASE
 # define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
 #endif
-#ifndef CONFIG_SYS_GBL_DATA_ADDR
-# define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE)
-#endif
-#ifndef CONFIG_SYS_BD_INFO_ADDR
-# define CONFIG_SYS_BD_INFO_ADDR (CONFIG_SYS_GBL_DATA_ADDR - GENERATED_BD_INFO_SIZE)
-#endif
 #ifndef CONFIG_STACKBASE
-# define CONFIG_STACKBASE (CONFIG_SYS_BD_INFO_ADDR - 4)
+# define CONFIG_STACKBASE (CONFIG_SYS_MALLOC_BASE - 4)
 #endif
 #ifndef CONFIG_SYS_MEMTEST_START
 # define CONFIG_SYS_MEMTEST_START 0
diff --git a/arch/blackfin/include/asm/global_data.h b/arch/blackfin/include/asm/global_data.h
index 67aa30f04c..973ea2929a 100644
--- a/arch/blackfin/include/asm/global_data.h
+++ b/arch/blackfin/include/asm/global_data.h
@@ -73,6 +73,6 @@ typedef struct global_data {
 #define GD_FLG_DISABLE_CONSOLE	0x00040	/* Disable console (in & out)		*/
 #define GD_FLG_ENV_READY	0x00080	/* Environment imported into hash table	*/
 
-#define DECLARE_GLOBAL_DATA_PTR     register gd_t * volatile gd asm ("P3")
+#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("P3")
 
 #endif
diff --git a/arch/blackfin/include/asm/u-boot.h b/arch/blackfin/include/asm/u-boot.h
index 9712fc00ee..df81183e81 100644
--- a/arch/blackfin/include/asm/u-boot.h
+++ b/arch/blackfin/include/asm/u-boot.h
@@ -30,7 +30,6 @@
 
 typedef struct bd_info {
 	int bi_baudrate;		/* serial console baudrate */
-	unsigned long bi_ip_addr;	/* IP Address */
 	unsigned long bi_boot_params;	/* where this board expects params */
 	unsigned long bi_memstart;	/* start of DRAM memory */
 	phys_size_t bi_memsize;		/* size  of DRAM memory in bytes */
diff --git a/arch/blackfin/lib/.gitignore b/arch/blackfin/lib/.gitignore
deleted file mode 100644
index 09f1be04eb..0000000000
--- a/arch/blackfin/lib/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-u-boot.lds
diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c
index e3ee4cd353..c380d271e7 100644
--- a/arch/blackfin/lib/board.c
+++ b/arch/blackfin/lib/board.c
@@ -86,7 +86,6 @@ static void display_global_data(void)
 	printf(" |-jt(%p): %p\n", gd->jt, *(gd->jt));
 	printf(" \\-bd: %p\n", gd->bd);
 	printf("   |-bi_baudrate: %x\n", bd->bi_baudrate);
-	printf("   |-bi_ip_addr: %lx\n", bd->bi_ip_addr);
 	printf("   |-bi_boot_params: %lx\n", bd->bi_boot_params);
 	printf("   |-bi_memstart: %lx\n", bd->bi_memstart);
 	printf("   |-bi_memsize: %lx\n", bd->bi_memsize);
@@ -181,6 +180,46 @@ void init_cplbtables(void)
 	}
 }
 
+static int global_board_data_init(void)
+{
+#ifndef CONFIG_SYS_GBL_DATA_ADDR
+# define CONFIG_SYS_GBL_DATA_ADDR 0
+#endif
+#ifndef CONFIG_SYS_BD_INFO_ADDR
+# define CONFIG_SYS_BD_INFO_ADDR 0
+#endif
+
+	bd_t *bd;
+
+	if (CONFIG_SYS_GBL_DATA_ADDR) {
+		gd = (gd_t *) (CONFIG_SYS_GBL_DATA_ADDR);
+		memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
+	} else {
+		static gd_t _bfin_gd;
+		gd = &_bfin_gd;
+	}
+
+	if (CONFIG_SYS_BD_INFO_ADDR) {
+		bd = (bd_t *) (CONFIG_SYS_BD_INFO_ADDR);
+		memset(bd, 0, GENERATED_BD_INFO_SIZE);
+	} else {
+		static bd_t _bfin_bd;
+		bd = &_bfin_bd;
+	}
+	gd->bd = bd;
+
+	bd->bi_r_version = version_string;
+	bd->bi_cpu = MK_STR(CONFIG_BFIN_CPU);
+	bd->bi_board_name = BFIN_BOARD_NAME;
+	bd->bi_vco = get_vco();
+	bd->bi_cclk = get_cclk();
+	bd->bi_sclk = get_sclk();
+	bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+
+	return 0;
+}
+
 /*
  * All attempts to come up with a "common" initialization sequence
  * that works for all boards and architectures failed: some of the
@@ -201,7 +240,6 @@ extern int timer_init(void);
 
 void board_init_f(ulong bootflag)
 {
-	bd_t *bd;
 	char buf[32];
 
 #ifdef CONFIG_BOARD_EARLY_INIT_F
@@ -234,21 +272,8 @@ void board_init_f(ulong bootflag)
 		hang();
 #endif
 	serial_early_puts("Init global data\n");
-	gd = (gd_t *) (CONFIG_SYS_GBL_DATA_ADDR);
-	memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
 
-	bd = (bd_t *) (CONFIG_SYS_BD_INFO_ADDR);
-	gd->bd = bd;
-	memset((void *)bd, 0, GENERATED_BD_INFO_SIZE);
-
-	bd->bi_r_version = version_string;
-	bd->bi_cpu = MK_STR(CONFIG_BFIN_CPU);
-	bd->bi_board_name = BFIN_BOARD_NAME;
-	bd->bi_vco = get_vco();
-	bd->bi_cclk = get_cclk();
-	bd->bi_sclk = get_sclk();
-	bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+	global_board_data_init();
 
 	/* Initialize */
 	serial_early_puts("IRQ init\n");
@@ -276,7 +301,7 @@ void board_init_f(ulong bootflag)
 
 	if (CONFIG_MEM_SIZE) {
 		printf("RAM:   ");
-		print_size(bd->bi_memsize, "\n");
+		print_size(gd->bd->bi_memsize, "\n");
 	}
 
 #if defined(CONFIG_POST)
@@ -294,15 +319,8 @@ static void board_net_init_r(bd_t *bd)
 	bb_miiphy_init();
 #endif
 #ifdef CONFIG_CMD_NET
-	char *s;
-
-	if ((s = getenv("bootfile")) != NULL)
-		copy_filename(BootFile, s, sizeof(BootFile));
-
-	bd->bi_ip_addr = getenv_IPaddr("ipaddr");
-
 	printf("Net:   ");
-	eth_initialize(gd->bd);
+	eth_initialize(bd);
 #endif
 }
 
diff --git a/arch/m68k/include/asm/u-boot.h b/arch/m68k/include/asm/u-boot.h
index 0a48bbdbe6..973c9ee098 100644
--- a/arch/m68k/include/asm/u-boot.h
+++ b/arch/m68k/include/asm/u-boot.h
@@ -47,7 +47,6 @@ typedef struct bd_info {
 	unsigned long bi_mbar_base;	/* base of internal registers */
 	unsigned long bi_bootflags;	/* boot / reboot flag (for LynxOS) */
 	unsigned long bi_boot_params;	/* where this board expects params */
-	unsigned long bi_ip_addr;	/* IP Address */
 	unsigned short bi_ethspeed;	/* Ethernet speed in Mbps */
 	unsigned long bi_intfreq;	/* Internal Freq, in MHz */
 	unsigned long bi_busfreq;	/* Bus Freq, in MHz */
diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c
index 1526967fe3..65a8595c2b 100644
--- a/arch/m68k/lib/board.c
+++ b/arch/m68k/lib/board.c
@@ -507,15 +507,6 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	/* relocate environment function pointers etc. */
 	env_relocate ();
 
-	/*
-	 * Fill in missing fields of bd_info.
-	 * We do this here, where we have "normal" access to the
-	 * environment; we used to do this still running from ROM,
-	 * where had to use getenv_f(), which can be pretty slow when
-	 * the environment is in EEPROM.
-	 */
-	bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
-
 	WATCHDOG_RESET ();
 
 #if defined(CONFIG_PCI)
@@ -568,11 +559,6 @@ void board_init_r (gd_t *id, ulong dest_addr)
 
 	/* Initialize from environment */
 	load_addr = getenv_ulong("loadaddr", 16, load_addr);
-#if defined(CONFIG_CMD_NET)
-	if ((s = getenv ("bootfile")) != NULL) {
-		copy_filename (BootFile, s, sizeof (BootFile));
-	}
-#endif
 
 	WATCHDOG_RESET ();
 
diff --git a/arch/microblaze/include/asm/u-boot.h b/arch/microblaze/include/asm/u-boot.h
index 21c72d5940..a0b1dbf9e6 100644
--- a/arch/microblaze/include/asm/u-boot.h
+++ b/arch/microblaze/include/asm/u-boot.h
@@ -40,7 +40,6 @@ typedef struct bd_info {
 	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
 	unsigned long	bi_sramstart;	/* start of SRAM memory */
 	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
-	unsigned long	bi_ip_addr;	/* IP Address */
 	unsigned long	bi_baudrate;	/* Console Baudrate */
 } bd_t;
 
diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c
index 9828b7630f..f3679d536b 100644
--- a/arch/microblaze/lib/board.c
+++ b/arch/microblaze/lib/board.c
@@ -176,19 +176,12 @@ void board_init (void)
 	load_addr = getenv_ulong("loadaddr", 16, load_addr);
 
 #if defined(CONFIG_CMD_NET)
-	/* IP Address */
-	bd->bi_ip_addr = getenv_IPaddr("ipaddr");
-
 	printf("Net:   ");
 	eth_initialize(gd->bd);
 
 	uchar enetaddr[6];
 	eth_getenv_enetaddr("ethaddr", enetaddr);
 	printf("MAC:   %pM\n", enetaddr);
-
-	s = getenv("bootfile");
-	if (s != NULL)
-		copy_filename(BootFile, s, sizeof(BootFile));
 #endif
 
 	/* main_loop */
diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_eth.c b/arch/mips/cpu/mips32/au1x00/au1x00_eth.c
index c51079961c..ac03a452bc 100644
--- a/arch/mips/cpu/mips32/au1x00/au1x00_eth.c
+++ b/arch/mips/cpu/mips32/au1x00/au1x00_eth.c
@@ -147,7 +147,8 @@ int  au1x00_miiphy_write(const char *devname, unsigned char addr,
 }
 #endif
 
-static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){
+static int au1x00_send(struct eth_device *dev, void *packet, int length)
+{
 	volatile mac_fifo_t *fifo_tx =
 		(volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
 	int i;
diff --git a/arch/mips/include/asm/u-boot.h b/arch/mips/include/asm/u-boot.h
index edb87bb066..590649aa3e 100644
--- a/arch/mips/include/asm/u-boot.h
+++ b/arch/mips/include/asm/u-boot.h
@@ -33,7 +33,6 @@
 
 typedef struct bd_info {
 	int		bi_baudrate;	/* serial console baudrate */
-	unsigned long	bi_ip_addr;	/* IP Address */
 	unsigned long	bi_arch_number;	/* unique id for this board */
 	unsigned long	bi_boot_params;	/* where this board expects params */
 	unsigned long	bi_memstart;	/* start of DRAM memory */
diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c
index 38e6e77a34..59a80011da 100644
--- a/arch/mips/lib/board.c
+++ b/arch/mips/lib/board.c
@@ -320,9 +320,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
 	/* relocate environment function pointers etc. */
 	env_relocate();
 
-	/* IP Address */
-	bd->bi_ip_addr = getenv_IPaddr("ipaddr");
-
 #if defined(CONFIG_PCI)
 	/*
 	 * Do pci configuration
@@ -342,14 +339,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
 
 	/* Initialize from environment */
 	load_addr = getenv_ulong("loadaddr", 16, load_addr);
-#if defined(CONFIG_CMD_NET)
-	{
-		char *s = getenv("bootfile");
-
-		if (s != NULL)
-			copy_filename(BootFile, s, sizeof(BootFile));
-	}
-#endif
 
 #ifdef CONFIG_CMD_SPI
 	puts("SPI:   ");
diff --git a/arch/nds32/cpu/n1213/ag102/Makefile b/arch/nds32/cpu/n1213/ag102/Makefile
new file mode 100644
index 0000000000..8716c4e858
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag102/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS-y	:= cpu.o timer.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS	:= lowlevel_init.o
+endif
+
+ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+SOBJS	+= watchdog.o
+endif
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/ag102/asm-offsets.c b/arch/nds32/cpu/n1213/ag102/asm-offsets.c
new file mode 100644
index 0000000000..4769a9521d
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag102/asm-offsets.c
@@ -0,0 +1,54 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * Generate definitions needed by assembly language modules.
+ * This code generates raw asm output which is post-processed to extract
+ * and format the required data.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <common.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+#ifdef CONFIG_FTSMC020
+	OFFSET(FTSMC020_BANK0_CR,	ftsmc020, bank[0].cr);
+	OFFSET(FTSMC020_BANK0_TPR,	ftsmc020, bank[0].tpr);
+#endif
+	BLANK();
+#ifdef CONFIG_FTAHBC020S
+	OFFSET(FTAHBC020S_SLAVE_BSR_6,	ftahbc02s, s_bsr[6]);
+	OFFSET(FTAHBC020S_CR,		ftahbc02s, cr);
+#endif
+	BLANK();
+#ifdef CONFIG_ANDES_PCU
+	OFFSET(ANDES_PCU_PCS4,		andes_pcu, pcs4.parm);	/* 0x104 */
+#endif
+	BLANK();
+#ifdef CONFIG_DWCDDR21MCTL
+	OFFSET(DWCDDR21MCTL_CCR,	dwcddr21mctl, ccr);	/* 0x04 */
+	OFFSET(DWCDDR21MCTL_DCR,	dwcddr21mctl, dcr);	/* 0x04 */
+	OFFSET(DWCDDR21MCTL_IOCR,	dwcddr21mctl, iocr);	/* 0x08 */
+	OFFSET(DWCDDR21MCTL_CSR,	dwcddr21mctl, csr);	/* 0x0c */
+	OFFSET(DWCDDR21MCTL_DRR,	dwcddr21mctl, drr);	/* 0x10 */
+	OFFSET(DWCDDR21MCTL_DLLCR0,	dwcddr21mctl, dllcr[0]); /* 0x24 */
+	OFFSET(DWCDDR21MCTL_DLLCR1,	dwcddr21mctl, dllcr[1]); /* 0x28 */
+	OFFSET(DWCDDR21MCTL_DLLCR2,	dwcddr21mctl, dllcr[2]); /* 0x2c */
+	OFFSET(DWCDDR21MCTL_DLLCR3,	dwcddr21mctl, dllcr[3]); /* 0x30 */
+	OFFSET(DWCDDR21MCTL_DLLCR4,	dwcddr21mctl, dllcr[4]); /* 0x34 */
+	OFFSET(DWCDDR21MCTL_DLLCR5,	dwcddr21mctl, dllcr[5]); /* 0x38 */
+	OFFSET(DWCDDR21MCTL_DLLCR6,	dwcddr21mctl, dllcr[6]); /* 0x3c */
+	OFFSET(DWCDDR21MCTL_DLLCR7,	dwcddr21mctl, dllcr[7]); /* 0x40 */
+	OFFSET(DWCDDR21MCTL_DLLCR8,	dwcddr21mctl, dllcr[8]); /* 0x44 */
+	OFFSET(DWCDDR21MCTL_DLLCR9,	dwcddr21mctl, dllcr[9]); /* 0x48 */
+	OFFSET(DWCDDR21MCTL_RSLR0,	dwcddr21mctl, rslr[0]);	/* 0x4c */
+	OFFSET(DWCDDR21MCTL_RDGR0,	dwcddr21mctl, rdgr[0]);	/* 0x5c */
+	OFFSET(DWCDDR21MCTL_DTAR,	dwcddr21mctl, dtar);	/* 0xa4 */
+	OFFSET(DWCDDR21MCTL_MR,		dwcddr21mctl, mr);	/* 0x1f0 */
+#endif
+	return 0;
+}
diff --git a/arch/nds32/cpu/n1213/ag102/cpu.c b/arch/nds32/cpu/n1213/ag102/cpu.c
new file mode 100644
index 0000000000..ed88b522a4
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag102/cpu.c
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* CPU specific code */
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+
+#include <faraday/ftwdt010_wdt.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+	disable_interrupts();
+
+#ifdef CONFIG_MMU
+	/* turn off I/D-cache */
+	icache_disable();
+	dcache_disable();
+
+	/* flush I/D-cache */
+	invalidate_icac();
+	invalidate_dcac();
+#endif
+
+	return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	disable_interrupts();
+
+	/*
+	 * reset to the base addr of andesboot.
+	 * currently no ROM loader at addr 0.
+	 * do not use reset_cpu(0);
+	 */
+#ifdef CONFIG_FTWDT010_WATCHDOG
+	/*
+	 * workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead
+	 * automatic hardware reset when booting Linux.
+	 * Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.
+	 */
+	ftwdt010_wdt_reset();
+#endif /* CONFIG_FTWDT010_WATCHDOG */
+	hang();
+
+	/*NOTREACHED*/
+}
+
+static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
+{
+	if (cache == ICACHE)
+		return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
+					>> ICM_CFG_OFF_ISZ) - 1);
+	else
+		return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
+					>> DCM_CFG_OFF_DSZ) - 1);
+}
+
+void dcache_flush_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(DCACHE);
+
+	while (end > start) {
+		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
+		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
+		start += line_size;
+	}
+}
+
+void icache_inval_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(ICACHE);
+	while (end > start) {
+		__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
+		start += line_size;
+	}
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+	dcache_flush_range(addr, addr + size);
+	icache_inval_range(addr, addr + size);
+}
+
+void icache_enable(void)
+{
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x01\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void icache_disable(void)
+{
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x01\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int icache_status(void)
+{
+	int ret;
+
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0,  $p0, 0x01\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	);
+
+	 return ret;
+}
+
+void dcache_enable(void)
+{
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"ori	$p0, $p0, 0x02\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+void dcache_disable(void)
+{
+	 __asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"li	$p1, ~0x02\n\t"
+		"and	$p0, $p0, $p1\n\t"
+		"mtsr	$p0, $mr8\n\t"
+		"isb\n\t"
+	);
+}
+
+int dcache_status(void)
+{
+	int ret;
+
+	__asm__ __volatile__ (
+		"mfsr	$p0, $mr8\n\t"
+		"andi	%0, $p0, 0x02\n\t"
+		: "=r" (ret)
+		:
+		: "memory"
+	 );
+
+	 return ret;
+}
diff --git a/arch/nds32/cpu/n1213/ag102/lowlevel_init.S b/arch/nds32/cpu/n1213/ag102/lowlevel_init.S
new file mode 100644
index 0000000000..d842afa4ba
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag102/lowlevel_init.S
@@ -0,0 +1,297 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+.text
+
+#include <common.h>
+#include <config.h>
+
+#include <asm/macro.h>
+#include <generated/asm-offsets.h>
+
+/*
+ * parameters for Synopsys DWC DDR2/DDR1 Memory Controller
+ */
+#define DDR2C_BASE_A		(CONFIG_DWCDDR21MCTL_BASE)
+#define DDR2C_CCR_A		(DDR2C_BASE_A + DWCDDR21MCTL_CCR)
+#define DDR2C_DCR_A		(DDR2C_BASE_A + DWCDDR21MCTL_DCR)
+#define DDR2C_IOCR_A		(DDR2C_BASE_A + DWCDDR21MCTL_IOCR)
+#define DDR2C_CSR_A		(DDR2C_BASE_A + DWCDDR21MCTL_CSR)
+#define DDR2C_DRR_A		(DDR2C_BASE_A + DWCDDR21MCTL_DRR)
+#define DDR2C_DLLCR0_A		(DDR2C_BASE_A + DWCDDR21MCTL_DLLCR0)
+#define DDR2C_DLLCR1_A		(DDR2C_BASE_A + DWCDDR21MCTL_DLLCR1)
+#define DDR2C_DLLCR2_A		(DDR2C_BASE_A + DWCDDR21MCTL_DLLCR2)
+#define DDR2C_DLLCR3_A		(DDR2C_BASE_A + DWCDDR21MCTL_DLLCR3)
+#define DDR2C_DLLCR4_A		(DDR2C_BASE_A + DWCDDR21MCTL_DLLCR4)
+#define DDR2C_DLLCR5_A		(DDR2C_BASE_A + DWCDDR21MCTL_DLLCR5)
+#define DDR2C_DLLCR6_A		(DDR2C_BASE_A + DWCDDR21MCTL_DLLCR6)
+#define DDR2C_DLLCR7_A		(DDR2C_BASE_A + DWCDDR21MCTL_DLLCR7)
+#define DDR2C_DLLCR8_A		(DDR2C_BASE_A + DWCDDR21MCTL_DLLCR8)
+#define DDR2C_DLLCR9_A		(DDR2C_BASE_A + DWCDDR21MCTL_DLLCR9)
+#define DDR2C_RSLR0_A		(DDR2C_BASE_A + DWCDDR21MCTL_RSLR0)
+#define DDR2C_RDGR0_A		(DDR2C_BASE_A + DWCDDR21MCTL_RDGR0)
+#define DDR2C_DTAR_A		(DDR2C_BASE_A + DWCDDR21MCTL_DTAR)
+#define DDR2C_MR_A		(DDR2C_BASE_A + DWCDDR21MCTL_MR)
+
+#define DDR2C_CCR_D		CONFIG_SYS_DWCDDR21MCTL_CCR
+#define DDR2C_CCR_D2		CONFIG_SYS_DWCDDR21MCTL_CCR2
+#define DDR2C_DCR_D		CONFIG_SYS_DWCDDR21MCTL_DCR
+#define DDR2C_IOCR_D		CONFIG_SYS_DWCDDR21MCTL_IOCR
+#define DDR2C_CSR_D		CONFIG_SYS_DWCDDR21MCTL_CSR
+#define DDR2C_DRR_D		CONFIG_SYS_DWCDDR21MCTL_DRR
+#define DDR2C_RSLR0_D		CONFIG_SYS_DWCDDR21MCTL_RSLR0
+#define DDR2C_RDGR0_D		CONFIG_SYS_DWCDDR21MCTL_RDGR0
+#define DDR2C_DTAR_D		CONFIG_SYS_DWCDDR21MCTL_DTAR
+#define DDR2C_MR_D		CONFIG_SYS_DWCDDR21MCTL_MR
+
+#define DDR2C_DLLCR0_D	CONFIG_SYS_DWCDDR21MCTL_DLLCR0	/* 0-9 are same */
+
+/*
+ * parameters for the ahbc controller
+ */
+#define AHBC_CR_A		(CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
+#define AHBC_BSR6_A	(CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
+
+#define AHBC_BSR6_D		CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
+
+/*
+ * parameters for the ANDES PCU controller
+ */
+#define PCU_PCS4_A		(CONFIG_ANDES_PCU_BASE + ANDES_PCU_PCS4)
+#define PCU_PCS4_D		CONFIG_SYS_ANDES_CPU_PCS4
+
+/*
+ * numeric 7 segment display
+ */
+.macro	led, num
+	write32	CONFIG_DEBUG_LED, \num
+.endm
+
+/*
+ * Waiting for SDRAM to set up
+ */
+/*
+.macro	wait_sdram
+	li	$r0, DDR2C_CSR_A
+1:
+	lwi	$r1, [$r0+FTSDMC021_CR2]
+	bnez	$r1, 1b
+.endm
+*/
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+.globl	lowlevel_init
+lowlevel_init:
+	move	$r10, $lp
+
+	/* U200 */
+!	led	0x00
+!	jal	scale_to_500mhz
+
+	led	0x10
+	jal	mem_init
+
+	led	0x20
+	jal	remap
+
+	led	0x30
+	ret	$r10
+
+scale_to_500mhz:
+	move	$r11, $lp
+
+	/*
+	 * scale to 500Mhz
+	 */
+	led	0x01
+	write32	PCU_PCS4_A, 0x1102000f			! save data to PCS4
+
+	move	$lp, $r11
+	ret
+
+mem_init:
+	move	$r11, $lp
+
+	/*
+	 * config AHB Controller
+	 */
+	led	0x12
+	write32	AHBC_BSR6_A, AHBC_BSR6_D
+
+	/*
+	 * config Synopsys DWC DDR2/DDR1 Memory Controller
+	 */
+ddr2c_init:
+set_dcr:
+	led	0x14
+	write32	DDR2C_DCR_A, DDR2C_DCR_D			! 0x000020d4
+
+auto_sizing:
+	/*
+	 * ebios: $r10->$r7, $r11->$r8, $r12->$r9, $r13->$r12, $r14->$r13
+	 */
+set_iocr:
+	led	0x19
+	write32 DDR2C_IOCR_A, DDR2C_IOCR_D
+set_drr:
+	led	0x16
+	write32	DDR2C_DRR_A, DDR2C_DRR_D			! 0x00034812
+set_dllcr:
+	led	0x18
+	write32 DDR2C_DLLCR0_A, DDR2C_DLLCR0_D
+	write32 DDR2C_DLLCR1_A, DDR2C_DLLCR0_D
+	write32 DDR2C_DLLCR2_A, DDR2C_DLLCR0_D
+	write32 DDR2C_DLLCR3_A, DDR2C_DLLCR0_D
+	write32 DDR2C_DLLCR4_A, DDR2C_DLLCR0_D
+	write32 DDR2C_DLLCR5_A, DDR2C_DLLCR0_D
+	write32 DDR2C_DLLCR6_A, DDR2C_DLLCR0_D
+	write32 DDR2C_DLLCR7_A, DDR2C_DLLCR0_D
+	write32 DDR2C_DLLCR8_A, DDR2C_DLLCR0_D
+	write32 DDR2C_DLLCR9_A, DDR2C_DLLCR0_D
+set_rslr0:
+	write32 DDR2C_RSLR0_A, DDR2C_RSLR0_D			! 0x00000040
+set_rdgr0:
+	write32 DDR2C_RDGR0_A, DDR2C_RDGR0_D			! 0x000055cf
+set_dtar:
+	led	0x15
+	write32	DDR2C_DTAR_A, DDR2C_DTAR_D			! 0x00100000
+set_mode:
+	led	0x17
+	write32	DDR2C_MR_A, DDR2C_MR_D				! 0x00000852
+set_ccr:
+	write32 DDR2C_CCR_A, DDR2C_CCR_D
+
+#ifdef TRIGGER_INIT:
+trigger_init:
+	write32 DDR2C_CCR_A, DDR2C_CCR_D			! 0x80020000
+
+	/* Wait for ddr init state to be set */
+	msync	ALL
+	isb
+
+	/* Wait until the config initialization is finish */
+1:
+	la	$r4, DDR2C_CSR_A
+	lwi	$r5, [$r4]
+	srli	$r5, $r5, 23
+	bnez	$r5, 1b
+#endif
+
+data_training:
+!	write32	DDR2C_CCR_A, DDR2C_CCR_D2			! 0x40020004
+
+	/* Wait for ddr init state to be set */
+	msync	ALL
+	isb
+
+	/* wait until the ddr data trainning is complete */
+1:
+	la	$r4, DDR2C_CSR_A
+	lwi	$r5, [$r4]
+	srli	$r6, $r5, 23
+	bnez	$r6, 1b
+
+	lwi	$r1, [$r4]
+	srli	$r6, $r5, 20
+	li	$r5, 0x00ffffff
+	swi	$r1, [$r4]
+	bnez	$r6, ddr2c_init
+
+	led	0x1a
+	move	$lp, $r11
+	ret
+
+remap:
+	move	$r11, $lp
+#ifdef __NDS32_N1213_43U1H__	/* NDS32 V0 ISA - AG101 Only */
+	bal	2f
+relo_base:
+	move	$r0, $lp
+#else
+relo_base:
+	mfusr	$r0, $pc
+#endif /* __NDS32_N1213_43U1H__ */
+
+	/*
+	 * Remapping
+	 */
+#ifdef CONFIG_MEM_REMAP
+	/*
+	 * Copy ROM code to SDRAM base for memory remap layout.
+	 * This is not the real relocation, the real relocation is the function
+	 * relocate_code() is start.S which supports the systems is memory
+	 * remapped or not.
+	 */
+	/*
+	 * Doing memory remap is essential for preparing some non-OS or RTOS
+	 * applications.
+	 *
+	 * This is also a must on ADP-AG101 board.
+	 * The reason is because the ROM/FLASH circuit on PCB board.
+	 * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
+	 * ROM/FLASH is used to boot.
+	 *
+	 * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
+	 * and the FLASH is connected to BANK1.
+	 * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
+	 * and the FLASH is connected to BANK0.
+	 * It will occur problem when doing flash probing if the flash is at
+	 * BANK0 (0x00000000) while memory remapping was skipped.
+	 *
+	 * Other board like ADP-AG101P may not enable this since there is only
+	 * a FLASH connected to bank0.
+	 */
+	led	0x21
+	li	$r4, PHYS_SDRAM_0_AT_INIT		/* 0x10000000 */
+	li	$r5, 0x0
+	la	$r1, relo_base				/* get $pc or $lp */
+	sub	$r2, $r0, $r1
+	sethi	$r6, hi20(_end)
+	ori	$r6, $r6, lo12(_end)
+	add	$r6, $r6, $r2
+1:
+	lwi.p	$r7, [$r5], #4
+	swi.p	$r7, [$r4], #4
+	blt	$r5, $r6, 1b
+
+	/* set remap bit */
+	/*
+	 * MEM remap bit is operational
+	 * - use it to map writeable memory at 0x00000000, in place of flash
+	 * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
+	 * - after  remap: flash/rom 0x80000000, sdram: 0x00000000
+	 */
+	led	0x2c
+	setbf15	AHBC_CR_A, FTAHBC020S_CR_REMAP		! 0x1
+
+#endif /* #ifdef CONFIG_MEM_REMAP */
+	move	$lp, $r11
+2:
+	ret
+
+.globl show_led
+show_led:
+    li      $r8, (CONFIG_DEBUG_LED)
+    swi     $r7, [$r8]
+    ret
+#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/nds32/cpu/n1213/ag102/timer.c b/arch/nds32/cpu/n1213/ag102/timer.c
new file mode 100644
index 0000000000..caa36b8be8
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag102/timer.c
@@ -0,0 +1,205 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <faraday/fttmr010.h>
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init(void)
+{
+	struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+	unsigned int cr;
+
+	debug("%s()\n", __func__);
+
+	/* disable timers */
+	writel(0, &tmr->cr);
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	/* use 32768Hz oscillator for RTC, WDT, TIMER */
+	ftpmu010_32768osc_enable();
+#endif
+
+	/* setup timer */
+	writel(TIMER_LOAD_VAL, &tmr->timer3_load);
+	writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
+	writel(0, &tmr->timer3_match1);
+	writel(0, &tmr->timer3_match2);
+
+	/* we don't want timer to issue interrupts */
+	writel(FTTMR010_TM3_MATCH1 |
+	       FTTMR010_TM3_MATCH2 |
+	       FTTMR010_TM3_OVERFLOW,
+	       &tmr->interrupt_mask);
+
+	cr = readl(&tmr->cr);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	cr |= FTTMR010_TM3_CLOCK;	/* use external clock */
+#endif
+	cr |= FTTMR010_TM3_ENABLE;
+	writel(cr, &tmr->cr);
+
+	/* init the timestamp and lastdec value */
+	reset_timer_masked();
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * reset time
+ */
+void reset_timer_masked(void)
+{
+	struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+	/* capure current decrementer value time */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+	lastdec = readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2);
+#endif
+	timestamp = 0;		/* start "advancing" time stamp from 0 */
+
+	debug("%s(): lastdec = %lx\n", __func__, lastdec);
+}
+
+void reset_timer(void)
+{
+	debug("%s()\n", __func__);
+	reset_timer_masked();
+}
+
+/*
+ * return timer ticks
+ */
+ulong get_timer_masked(void)
+{
+	struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+	/* current tick value */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+	ulong now = readl(&tmr->timer3_counter) / \
+			(CONFIG_SYS_CLK_FREQ / 2 / 1024);
+#endif
+
+	debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
+
+	if (lastdec >= now) {
+		/*
+		 * normal mode (non roll)
+		 * move stamp fordward with absoulte diff ticks
+		 */
+		timestamp += lastdec - now;
+	} else {
+		/*
+		 * we have overflow of the count down timer
+		 *
+		 * nts = ts + ld + (TLV - now)
+		 * ts=old stamp, ld=time that passed before passing through -1
+		 * (TLV-now) amount of time after passing though -1
+		 * nts = new "advancing time stamp"...it could also roll and
+		 * cause problems.
+		 */
+		timestamp += lastdec + TIMER_LOAD_VAL - now;
+	}
+
+	lastdec = now;
+
+	debug("%s() returns %lx\n", __func__, timestamp);
+
+	return timestamp;
+}
+
+/*
+ * return difference between timer ticks and base
+ */
+ulong get_timer(ulong base)
+{
+	debug("%s(%lx)\n", __func__, base);
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	debug("%s(%lx)\n", __func__, t);
+	timestamp = t;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay(unsigned long usec)
+{
+	struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+#else
+	long tmo = usec * ((CONFIG_SYS_CLK_FREQ / 2) / 1000) / 1000;
+#endif
+	unsigned long now, last = readl(&tmr->timer3_counter);
+
+	debug("%s(%lu)\n", __func__, usec);
+	while (tmo > 0) {
+		now = readl(&tmr->timer3_counter);
+		if (now > last) /* count down timer overflow */
+			tmo -= TIMER_LOAD_VAL + last - now;
+		else
+			tmo -= last - now;
+		last = now;
+	}
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	debug("%s()\n", __func__);
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	debug("%s()\n", __func__);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+	return CONFIG_SYS_HZ;
+#else
+	return CONFIG_SYS_CLK_FREQ;
+#endif
+}
diff --git a/arch/nds32/cpu/n1213/ag102/watchdog.S b/arch/nds32/cpu/n1213/ag102/watchdog.S
new file mode 100644
index 0000000000..56cecda78f
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag102/watchdog.S
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch-ag102/ag102.h>
+#include <linux/linkage.h>
+
+.text
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+ENTRY(turnoff_watchdog)
+
+#define WD_CR		0xC
+#define WD_ENABLE	0x1
+
+	! Turn off the watchdog, according to Faraday FTWDT010 spec
+	li 	$p0, (CONFIG_FTWDT010_BASE+WD_CR)	! Get the addr of WD CR
+	lwi	$p1, [$p0]				! Get the config of WD
+	andi	$p1, $p1, 0x1f				! Wipe out useless bits
+	li	$r0, ~WD_ENABLE
+	and	$p1, $p1, $r0				! Set WD disable
+	sw	$p1, [$p0]				! Write back to WD CR
+
+	! Disable Interrupts by clear GIE in $PSW reg
+	setgie.d
+
+	ret
+
+ENDPROC(turnoff_watchdog)
+#endif
diff --git a/arch/nds32/include/asm/arch-ag102/ag102.h b/arch/nds32/include/asm/arch-ag102/ag102.h
new file mode 100644
index 0000000000..a12a8c52b7
--- /dev/null
+++ b/arch/nds32/include/asm/arch-ag102/ag102.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __AG102_H
+#define __AG102_H
+
+/*
+ * Hardware register bases
+ */
+
+/* PCI Controller */
+#define CONFIG_FTPCI100_BASE		0x90000000
+/* LPC Controller */
+#define CONFIG_LPC_IO_BASE		0x90100000
+/* LPC Controller */
+#define CONFIG_LPC_BASE			0x90200000
+
+/* NDS32 Data Local Memory 01 */
+#define CONFIG_NDS_DLM1_BASE		0x90300000
+/* NDS32 Data Local Memory 02 */
+#define CONFIG_NDS_DLM2_BASE		0x90400000
+
+/* Synopsys DWC DDR2/1 Controller */
+#define CONFIG_DWCDDR21MCTL_BASE	0x90500000
+/* DMA Controller */
+#define CONFIG_FTDMAC020_BASE		0x90600000
+/* FTIDE020_S IDE (ATA) Controller */
+#define CONFIG_FTIDE020S_BASE		0x90700000
+/* USB OTG Controller */
+#define CONFIG_FZOTG266HD0A_BASE	0x90800000
+/* Andes L2 Cache Controller */
+#define CONFIG_NCEL2C100_BASE		0x90900000
+/* XGI XG22 GPU */
+#define CONFIG_XGI_XG22_BASE		0x90A00000
+/* GMAC Ethernet Controller */
+#define CONFIG_FTGMAC100_BASE		0x90B00000
+/* AHB Controller */
+#define CONFIG_FTAHBC020S_BASE		0x90C00000
+/* AHB-to-APB Bridge Controller */
+#define CONFIG_FTAPBBRG020S_01_BASE	0x90D00000
+/* External AHB2AHB Controller */
+#define CONFIG_EXT_AHB2AHB_BASE		0x90E00000
+/* Andes Multi-core Interrupt Controller */
+#define CONFIG_NCEMIC100_BASE		0x90F00000
+
+/*
+ * APB Device definitions
+ */
+/* Compat Flash Controller */
+#define CONFIG_FTCFC010_BASE		0x94000000
+/* APB - SSP (SPI) (without AC97) Controller */
+#define CONFIG_FTSSP010_01_BASE		0x94100000
+/* UART1 - APB STUART Controller (UART0 in Linux) */
+#define CONFIG_FTUART010_01_BASE	0x94200000
+/* FTSDC010 SD Controller */
+#define CONFIG_FTSDC010_BASE		0x94400000
+/* APB - SSP with HDA/AC97 Controller */
+#define CONFIG_FTSSP010_02_BASE		0x94500000
+/* UART2 - APB STUART Controller (UART1 in Linux) */
+#define CONFIG_FTUART010_02_BASE	0x94600000
+/* PCU Controller */
+#define CONFIG_ANDES_PCU_BASE		0x94800000
+/* FTTMR010 Timer */
+#define CONFIG_FTTMR010_BASE		0x94900000
+/* Watch Dog Controller */
+#define CONFIG_FTWDT010_BASE		0x94A00000
+/* FTRTC010 Real Time Clock */
+#define CONFIG_FTRTC010_BASE		0x98B00000
+/* GPIO Controller */
+#define CONFIG_FTGPIO010_BASE		0x94C00000
+/* I2C Controller */
+#define CONFIG_FTIIC010_BASE		0x94E00000
+/* PWM - Pulse Width Modulator Controller */
+#define CONFIG_FTPWM010_BASE		0x94F00000
+
+/* Debug LED */
+#define CONFIG_DEBUG_LED		0x902FFFFC
+/* Power Management Unit */
+#define CONFIG_FTPMU010_BASE		0x98100000
+
+#endif	/* __AG102_H */
diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h
index 7b52b989bc..259e4e7ad9 100644
--- a/arch/nds32/include/asm/mach-types.h
+++ b/arch/nds32/include/asm/mach-types.h
@@ -40,4 +40,18 @@ extern unsigned int __machine_arch_type;
 # define machine_is_adpag101p()	(1)
 #endif
 
+#define MACH_TYPE_ADPAG102             2
+
+#ifdef CONFIG_ARCH_ADPAG102
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADPAG102
+# endif
+# define machine_is_adpag102()	(machine_arch_type == MACH_TYPE_ADPAG102)
+#else
+# define machine_is_adpag102()	(2)
+#endif
+
 #endif /* __ASM_NDS32_MACH_TYPE_H */
diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h
index 9a697501d1..eabbf38fb1 100644
--- a/arch/nds32/include/asm/u-boot.h
+++ b/arch/nds32/include/asm/u-boot.h
@@ -40,7 +40,6 @@
 
 typedef struct bd_info {
 	int		bi_baudrate;	/* serial console baudrate */
-	unsigned long	bi_ip_addr;	/* IP Address */
 	unsigned char	bi_enetaddr[6]; /* Ethernet adress */
 	unsigned long	bi_arch_number;	/* unique id for this board */
 	unsigned long	bi_boot_params;	/* where this board expects params */
diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c
index 074aabf1e4..7121313a83 100644
--- a/arch/nds32/lib/board.c
+++ b/arch/nds32/lib/board.c
@@ -369,9 +369,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
 	nds32_pci_init();
 #endif
 
-	/* IP Address */
-	gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
-
 	stdio_init();	/* get the devices list going. */
 
 	jumptable_init();
@@ -402,12 +399,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
 	/* Initialize from environment */
 	load_addr = getenv_ulong("loadaddr", 16, load_addr);
 
-#if defined(CONFIG_CMD_NET)
-	s = getenv("bootfile");
-	if (s != NULL)
-		copy_filename(BootFile, s, sizeof(BootFile));
-#endif
-
 #ifdef BOARD_LATE_INIT
 	board_late_init();
 #endif
diff --git a/arch/nios2/include/asm/u-boot.h b/arch/nios2/include/asm/u-boot.h
index f7c70ff0c1..315ef8bedb 100644
--- a/arch/nios2/include/asm/u-boot.h
+++ b/arch/nios2/include/asm/u-boot.h
@@ -39,7 +39,6 @@ typedef struct bd_info {
 	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
 	unsigned long	bi_sramstart;	/* start of SRAM memory */
 	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
-	unsigned long	bi_ip_addr;	/* IP Address */
 	unsigned long	bi_baudrate;	/* Console Baudrate */
 } bd_t;
 
diff --git a/arch/nios2/lib/board.c b/arch/nios2/lib/board.c
index 65de26e5c9..ca8a3e5246 100644
--- a/arch/nios2/lib/board.c
+++ b/arch/nios2/lib/board.c
@@ -143,8 +143,6 @@ void board_init (void)
 	WATCHDOG_RESET ();
 	env_relocate();
 
-	bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
-
 	WATCHDOG_RESET ();
 	stdio_init();
 	jumptable_init();
diff --git a/arch/openrisc/include/asm/u-boot.h b/arch/openrisc/include/asm/u-boot.h
index 2913994932..76b813273f 100644
--- a/arch/openrisc/include/asm/u-boot.h
+++ b/arch/openrisc/include/asm/u-boot.h
@@ -33,7 +33,6 @@
 
 typedef struct bd_info {
 	unsigned long	bi_baudrate;	/* serial console baudrate */
-	unsigned long	bi_ip_addr;	/* IP Address */
 	unsigned long	bi_arch_number;	/* unique id for this board */
 	unsigned long	bi_boot_params;	/* where this board expects params */
 	unsigned long	bi_memstart;	/* start of DRAM memory */
diff --git a/arch/powerpc/cpu/mpc8220/fec.c b/arch/powerpc/cpu/mpc8220/fec.c
index 2053fea571..aaf9be107a 100644
--- a/arch/powerpc/cpu/mpc8220/fec.c
+++ b/arch/powerpc/cpu/mpc8220/fec.c
@@ -624,7 +624,7 @@ static void rfifo_print (char *devname, mpc8220_fec_priv * fec)
 
 /********************************************************************/
 
-static int mpc8220_fec_send (struct eth_device *dev, volatile void *eth_data,
+static int mpc8220_fec_send(struct eth_device *dev, void *eth_data,
 			     int data_length)
 {
 	/*
@@ -787,8 +787,7 @@ static int mpc8220_fec_recv (struct eth_device *dev)
 			 */
 /*			memcpy(buff, frame->head, 14);
 			memcpy(buff + 14, frame->data, frame_length);*/
-			NetReceive ((volatile uchar *) pRbd->dataPointer,
-				    frame_length);
+			NetReceive((uchar *)pRbd->dataPointer, frame_length);
 			len = frame_length;
 		}
 		/*
diff --git a/arch/powerpc/cpu/mpc824x/.gitignore b/arch/powerpc/cpu/mpc824x/.gitignore
deleted file mode 100644
index 2d79931e96..0000000000
--- a/arch/powerpc/cpu/mpc824x/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/bedbug_603e.c
diff --git a/arch/powerpc/cpu/mpc8260/ether_fcc.c b/arch/powerpc/cpu/mpc8260/ether_fcc.c
index 879ec0ea23..18534516a4 100644
--- a/arch/powerpc/cpu/mpc8260/ether_fcc.c
+++ b/arch/powerpc/cpu/mpc8260/ether_fcc.c
@@ -142,7 +142,7 @@ static RTXBD rtx __attribute__ ((aligned(8)));
 #error "rtx must be 64-bit aligned"
 #endif
 
-static int fec_send(struct eth_device* dev, volatile void *packet, int length)
+static int fec_send(struct eth_device *dev, void *packet, int length)
 {
     int i;
     int result = 0;
@@ -1049,11 +1049,11 @@ eth_loopback_test (void)
 					}
 					else {
 						ushort datlen = bdp->cbd_datlen;
-						Ethernet_t *ehp;
+						struct ethernet_hdr *ehp;
 						ushort prot;
 						int ours, tb, n, nbytes;
 
-						ehp = (Ethernet_t *) \
+						ehp = (struct ethernet_hdr *) \
 							&ecp->rxbufs[i][0];
 
 						ours = memcmp (ehp->et_src, \
@@ -1063,9 +1063,8 @@ eth_loopback_test (void)
 						tb = prot & 0x8000;
 						n = prot & 0x7fff;
 
-						nbytes = ELBT_BUFSZ - \
-							offsetof (Ethernet_t, \
-								et_dsap) - \
+						nbytes = ELBT_BUFSZ -
+							ETHER_HDR_SIZE -
 							ELBT_CRCSZ;
 
 						/* check the frame is correct */
@@ -1080,10 +1079,10 @@ eth_loopback_test (void)
 								patwords[n];
 							uint nbb;
 
-							nbb = badbits ( \
-								&ehp->et_dsap, \
-								nbytes, \
-								patword);
+							nbb = badbits(
+							    ((uchar *)&ehp) +
+							    ETHER_HDR_SIZE,
+							    nbytes, patword);
 
 							ecp->rxeacc.badbit += \
 								nbb;
diff --git a/arch/powerpc/cpu/mpc8260/ether_scc.c b/arch/powerpc/cpu/mpc8260/ether_scc.c
index 1c040f0f5b..3c71219575 100644
--- a/arch/powerpc/cpu/mpc8260/ether_scc.c
+++ b/arch/powerpc/cpu/mpc8260/ether_scc.c
@@ -105,7 +105,7 @@ typedef volatile struct CommonBufferDescriptor {
 static RTXBD *rtx;
 
 
-static int sec_send(struct eth_device *dev, volatile void *packet, int length)
+static int sec_send(struct eth_device *dev, void *packet, int length)
 {
     int i;
     int result = 0;
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 2e4a06c35a..2cd5db7c59 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -37,6 +37,7 @@
 #include <asm/mmu.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
+#include <asm/fsl_srio.h>
 #include <linux/compiler.h>
 #include "mp.h"
 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
@@ -48,8 +49,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern void srio_init(void);
-
 #ifdef CONFIG_QE
 extern qe_iop_conf_t qe_iop_conf_tab[];
 extern void qe_config_iopin(u8 port, u8 pin, int dir,
@@ -443,6 +442,12 @@ skip_l2:
 
 #ifdef CONFIG_SYS_SRIO
 	srio_init();
+#ifdef CONFIG_SRIOBOOT_MASTER
+	srio_boot_master();
+#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
+	srio_boot_master_release_slave();
+#endif
+#endif
 #endif
 
 #if defined(CONFIG_MP)
diff --git a/arch/powerpc/cpu/mpc85xx/ether_fcc.c b/arch/powerpc/cpu/mpc85xx/ether_fcc.c
index 41c3c84ae5..7d372aaef6 100644
--- a/arch/powerpc/cpu/mpc85xx/ether_fcc.c
+++ b/arch/powerpc/cpu/mpc85xx/ether_fcc.c
@@ -138,7 +138,7 @@ static RTXBD rtx __attribute__ ((aligned(8)));
 
 #undef ET_DEBUG
 
-static int fec_send(struct eth_device* dev, volatile void *packet, int length)
+static int fec_send(struct eth_device *dev, void *packet, int length)
 {
     int i = 0;
     int result = 0;
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 4d37d6e863..8e99ef6c68 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
  * Copyright (C) 2003  Motorola,Inc.
  *
  * See file CREDITS for list of people who contributed to this
@@ -179,41 +179,50 @@ l2_disabled:
 	andi.	r1,r3,L1CSR0_DCE@l
 	beq	2b
 
+/*
+ * Ne need to setup interrupt vector for NAND SPL
+ * because NAND SPL never compiles it.
+ */
+#if !defined(CONFIG_NAND_SPL)
 	/* Setup interrupt vectors */
 	lis	r1,CONFIG_SYS_MONITOR_BASE@h
 	mtspr	IVPR,r1
 
-	li	r1,0x0100
-	mtspr	IVOR0,r1	/* 0: Critical input */
-	li	r1,0x0200
-	mtspr	IVOR1,r1	/* 1: Machine check */
-	li	r1,0x0300
-	mtspr	IVOR2,r1	/* 2: Data storage */
-	li	r1,0x0400
-	mtspr	IVOR3,r1	/* 3: Instruction storage */
-	li	r1,0x0500
-	mtspr	IVOR4,r1	/* 4: External interrupt */
-	li	r1,0x0600
-	mtspr	IVOR5,r1	/* 5: Alignment */
-	li	r1,0x0700
-	mtspr	IVOR6,r1	/* 6: Program check */
-	li	r1,0x0800
-	mtspr	IVOR7,r1	/* 7: floating point unavailable */
-	li	r1,0x0900
-	mtspr	IVOR8,r1	/* 8: System call */
+	lis	r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h
+	ori	r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l
+
+	addi	r4,r3,CriticalInput - _start + _START_OFFSET
+	mtspr	IVOR0,r4	/* 0: Critical input */
+	addi	r4,r3,MachineCheck - _start + _START_OFFSET
+	mtspr	IVOR1,r4	/* 1: Machine check */
+	addi	r4,r3,DataStorage - _start + _START_OFFSET
+	mtspr	IVOR2,r4	/* 2: Data storage */
+	addi	r4,r3,InstStorage - _start + _START_OFFSET
+	mtspr	IVOR3,r4	/* 3: Instruction storage */
+	addi	r4,r3,ExtInterrupt - _start + _START_OFFSET
+	mtspr	IVOR4,r4	/* 4: External interrupt */
+	addi	r4,r3,Alignment - _start + _START_OFFSET
+	mtspr	IVOR5,r4	/* 5: Alignment */
+	addi	r4,r3,ProgramCheck - _start + _START_OFFSET
+	mtspr	IVOR6,r4	/* 6: Program check */
+	addi	r4,r3,FPUnavailable - _start + _START_OFFSET
+	mtspr	IVOR7,r4	/* 7: floating point unavailable */
+	addi	r4,r3,SystemCall - _start + _START_OFFSET
+	mtspr	IVOR8,r4	/* 8: System call */
 	/* 9: Auxiliary processor unavailable(unsupported) */
-	li	r1,0x0a00
-	mtspr	IVOR10,r1	/* 10: Decrementer */
-	li	r1,0x0b00
-	mtspr	IVOR11,r1	/* 11: Interval timer */
-	li	r1,0x0c00
-	mtspr	IVOR12,r1	/* 12: Watchdog timer */
-	li	r1,0x0d00
-	mtspr	IVOR13,r1	/* 13: Data TLB error */
-	li	r1,0x0e00
-	mtspr	IVOR14,r1	/* 14: Instruction TLB error */
-	li	r1,0x0f00
-	mtspr	IVOR15,r1	/* 15: Debug */
+	addi	r4,r3,Decrementer - _start + _START_OFFSET
+	mtspr	IVOR10,r4	/* 10: Decrementer */
+	addi	r4,r3,IntervalTimer - _start + _START_OFFSET
+	mtspr	IVOR11,r4	/* 11: Interval timer */
+	addi	r4,r3,WatchdogTimer - _start + _START_OFFSET
+	mtspr	IVOR12,r4	/* 12: Watchdog timer */
+	addi	r4,r3,DataTLBError - _start + _START_OFFSET
+	mtspr	IVOR13,r4	/* 13: Data TLB error */
+	addi	r4,r3,InstructionTLBError - _start + _START_OFFSET
+	mtspr	IVOR14,r4	/* 14: Instruction TLB error */
+	addi	r4,r3,DebugBreakpoint - _start + _START_OFFSET
+	mtspr	IVOR15,r4	/* 15: Debug */
+#endif
 
 	/* Clear and set up some registers. */
 	li      r0,0x0000
@@ -434,13 +443,15 @@ create_ccsr_new_tlb:
 	ori     r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l
 	lis     r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
 	ori     r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
+#ifdef CONFIG_ENABLE_36BIT_PHYS
 	lis	r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
 	ori	r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
+	mtspr   MAS7, r7
+#endif
 	mtspr   MAS0, r0
 	mtspr   MAS1, r1
 	mtspr   MAS2, r2
 	mtspr   MAS3, r3
-	mtspr   MAS7, r7
 	isync
 	msync
 	tlbwe
@@ -456,12 +467,14 @@ create_ccsr_old_tlb:
 	ori     r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l
 	lis     r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h
 	ori     r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l
+#ifdef CONFIG_ENABLE_36BIT_PHYS
 	li	r7, 0	/* The default CCSR address is always a 32-bit number */
+	mtspr   MAS7, r7
+#endif
 	mtspr   MAS0, r0
 	/* MAS1 is the same as above */
 	mtspr   MAS2, r2
 	mtspr   MAS3, r3
-	mtspr   MAS7, r7
 	isync
 	msync
 	tlbwe
@@ -1490,6 +1503,39 @@ trap_init:
 	cmplw	0,r7,r8
 	blt	2b
 
+	/* Update IVORs as per relocated vector table address */
+	li	r7,0x0100
+	mtspr	IVOR0,r7	/* 0: Critical input */
+	li	r7,0x0200
+	mtspr	IVOR1,r7	/* 1: Machine check */
+	li	r7,0x0300
+	mtspr	IVOR2,r7	/* 2: Data storage */
+	li	r7,0x0400
+	mtspr	IVOR3,r7	/* 3: Instruction storage */
+	li	r7,0x0500
+	mtspr	IVOR4,r7	/* 4: External interrupt */
+	li	r7,0x0600
+	mtspr	IVOR5,r7	/* 5: Alignment */
+	li	r7,0x0700
+	mtspr	IVOR6,r7	/* 6: Program check */
+	li	r7,0x0800
+	mtspr	IVOR7,r7	/* 7: floating point unavailable */
+	li	r7,0x0900
+	mtspr	IVOR8,r7	/* 8: System call */
+	/* 9: Auxiliary processor unavailable(unsupported) */
+	li	r7,0x0a00
+	mtspr	IVOR10,r7	/* 10: Decrementer */
+	li	r7,0x0b00
+	mtspr	IVOR11,r7	/* 11: Interval timer */
+	li	r7,0x0c00
+	mtspr	IVOR12,r7	/* 12: Watchdog timer */
+	li	r7,0x0d00
+	mtspr	IVOR13,r7	/* 13: Data TLB error */
+	li	r7,0x0e00
+	mtspr	IVOR14,r7	/* 14: Instruction TLB error */
+	li	r7,0x0f00
+	mtspr	IVOR15,r7	/* 15: Debug */
+
 	lis	r7,0x0
 	mtspr	IVPR,r7
 
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
index 04bc73170a..8ba9399169 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2009-2012 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -51,13 +51,14 @@ SECTIONS
   PROVIDE (erotext = .);
   .reloc   :
   {
-    KEEP(*(.got))
     _GOT2_TABLE_ = .;
     KEEP(*(.got2))
+    KEEP(*(.got))
+    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
     _FIXUP_TABLE_ = .;
     KEEP(*(.fixup))
   }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
   __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
 
   .data    :
@@ -87,7 +88,7 @@ SECTIONS
 
   .bootpg ADDR(.text) - 0x1000 :
   {
-    arch/powerpc/cpu/mpc85xx/start.o	KEEP(*(.bootpg))
+    KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg))
   } :text = 0xffff
 
   . = ADDR(.text) + 0x80000;
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
index 852f9aa4a3..668158f702 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
@@ -37,10 +37,12 @@ SECTIONS
 	.reloc : {
 		_GOT2_TABLE_ = .;
 		KEEP(*(.got2))
+		KEEP(*(.got))
+		PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
 		_FIXUP_TABLE_ = .;
 		KEEP(*(.fixup))
 	}
-	__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+	__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
 	__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
 
 	. = ALIGN(8);
diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c
index f2a2c3a736..b348a98c58 100644
--- a/arch/powerpc/cpu/mpc8xx/fec.c
+++ b/arch/powerpc/cpu/mpc8xx/fec.c
@@ -139,7 +139,7 @@ typedef volatile struct CommonBufferDescriptor {
 
 static RTXBD *rtx = NULL;
 
-static int fec_send(struct eth_device* dev, volatile void *packet, int length);
+static int fec_send(struct eth_device *dev, void *packet, int length);
 static int fec_recv(struct eth_device* dev);
 static int fec_init(struct eth_device* dev, bd_t * bd);
 static void fec_halt(struct eth_device* dev);
@@ -193,7 +193,7 @@ int fec_initialize(bd_t *bis)
 	return 1;
 }
 
-static int fec_send(struct eth_device* dev, volatile void *packet, int length)
+static int fec_send(struct eth_device *dev, void *packet, int length)
 {
 	int j, rc;
 	struct ether_fcc_info_s *efis = dev->priv;
@@ -267,14 +267,14 @@ static int fec_recv (struct eth_device *dev)
 				rtx->rxbd[rxIdx].cbd_sc);
 #endif
 		} else {
-			volatile uchar *rx = NetRxPackets[rxIdx];
+			uchar *rx = NetRxPackets[rxIdx];
 
 			length -= 4;
 
 #if defined(CONFIG_CMD_CDP)
 			if ((rx[0] & 1) != 0
 			    && memcmp ((uchar *) rx, NetBcastAddr, 6) != 0
-			    && memcmp ((uchar *) rx, NetCDPAddr, 6) != 0)
+			    && !is_cdp_packet((uchar *)rx))
 				rx = NULL;
 #endif
 			/*
diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c
index e376c64d52..2c93e24f3c 100644
--- a/arch/powerpc/cpu/mpc8xx/scc.c
+++ b/arch/powerpc/cpu/mpc8xx/scc.c
@@ -65,7 +65,7 @@ typedef volatile struct CommonBufferDescriptor {
 
 static RTXBD *rtx;
 
-static int scc_send(struct eth_device* dev, volatile void *packet, int length);
+static int scc_send(struct eth_device *dev, void *packet, int length);
 static int scc_recv(struct eth_device* dev);
 static int scc_init (struct eth_device* dev, bd_t * bd);
 static void scc_halt(struct eth_device* dev);
@@ -90,7 +90,7 @@ int scc_initialize(bd_t *bis)
 	return 1;
 }
 
-static int scc_send(struct eth_device* dev, volatile void *packet, int length)
+static int scc_send(struct eth_device *dev, void *packet, int length)
 {
 	int i, j=0;
 #if 0
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index e46d328067..c7f394972b 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -21,6 +21,16 @@
 #include <config.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
+#include <asm/fsl_srio.h>
+
+#define SRIO_PORT_ACCEPT_ALL 0x10000001
+#define SRIO_IB_ATMU_AR 0x80f55000
+#define SRIO_OB_ATMU_AR_MAINT 0x80077000
+#define SRIO_OB_ATMU_AR_RW 0x80045000
+#define SRIO_LCSBA1CSR_OFFSET 0x5c
+#define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */
+#define SRIO_RW_WIN_SIZE 0x100000 /* 1M */
+#define SRIO_LCSBA1CSR 0x60000000
 
 #if defined(CONFIG_FSL_CORENET)
 	#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
@@ -84,3 +94,203 @@ void srio_init(void)
 		setbits_be32(&gur->devdisr, _DEVDISR_RMU);
 	}
 }
+
+#ifdef CONFIG_SRIOBOOT_MASTER
+void srio_boot_master(void)
+{
+	struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+
+	/* set port accept-all */
+	out_be32((void *)&srio->impl.port[CONFIG_SRIOBOOT_MASTER_PORT].ptaacr,
+				SRIO_PORT_ACCEPT_ALL);
+
+	debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n",
+			CONFIG_SRIOBOOT_MASTER_PORT);
+	/* configure inbound window for slave's u-boot image */
+	debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
+			"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
+			(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1,
+			(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1,
+			CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
+	out_be32((void *)&srio->atmu
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwtar,
+			CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 >> 12);
+	out_be32((void *)&srio->atmu
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwbar,
+			CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 >> 12);
+	out_be32((void *)&srio->atmu
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwar,
+			SRIO_IB_ATMU_AR
+			| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
+
+	/* configure inbound window for slave's u-boot image */
+	debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
+			"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
+			(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2,
+			(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2,
+			CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
+	out_be32((void *)&srio->atmu
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwtar,
+			CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 >> 12);
+	out_be32((void *)&srio->atmu
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwbar,
+			CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 >> 12);
+	out_be32((void *)&srio->atmu
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwar,
+			SRIO_IB_ATMU_AR
+			| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
+
+	/* configure inbound window for slave's ucode */
+	debug("SRIOBOOT - MASTER: Inbound window for slave's ucode; "
+			"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
+			(u64)CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS,
+			(u64)CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS,
+			CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE);
+	out_be32((void *)&srio->atmu
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwtar,
+			CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS >> 12);
+	out_be32((void *)&srio->atmu
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwbar,
+			CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS >> 12);
+	out_be32((void *)&srio->atmu
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwar,
+			SRIO_IB_ATMU_AR
+			| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE));
+
+	/* configure inbound window for slave's ENV */
+	debug("SRIOBOOT - MASTER: Inbound window for slave's ENV; "
+			"Local = 0x%llx, Siro = 0x%llx, Size = 0x%x\n",
+			CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS,
+			CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS,
+			CONFIG_SRIOBOOT_SLAVE_ENV_SIZE);
+	out_be32((void *)&srio->atmu
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwtar,
+			CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS >> 12);
+	out_be32((void *)&srio->atmu
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwbar,
+			CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS >> 12);
+	out_be32((void *)&srio->atmu
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwar,
+			SRIO_IB_ATMU_AR
+			| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_ENV_SIZE));
+}
+
+#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
+void srio_boot_master_release_slave(void)
+{
+	struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+	u32 escsr;
+	debug("SRIOBOOT - MASTER: "
+			"Check the port status and release slave core ...\n");
+
+	escsr = in_be32((void *)&srio->lp_serial
+			.port[CONFIG_SRIOBOOT_MASTER_PORT].pescsr);
+	if (escsr & 0x2) {
+		if (escsr & 0x10100) {
+			debug("SRIOBOOT - MASTER: Port [ %d ] is error.\n",
+					CONFIG_SRIOBOOT_MASTER_PORT);
+		} else {
+			debug("SRIOBOOT - MASTER: "
+					"Port [ %d ] is ready, now release slave's core ...\n",
+					CONFIG_SRIOBOOT_MASTER_PORT);
+			/*
+			 * configure outbound window
+			 * with maintenance attribute to set slave's LCSBA1CSR
+			 */
+			out_be32((void *)&srio->atmu
+				.port[CONFIG_SRIOBOOT_MASTER_PORT]
+				.outbw[1].rowtar, 0);
+			out_be32((void *)&srio->atmu
+				.port[CONFIG_SRIOBOOT_MASTER_PORT]
+				.outbw[1].rowtear, 0);
+			if (CONFIG_SRIOBOOT_MASTER_PORT)
+				out_be32((void *)&srio->atmu
+					.port[CONFIG_SRIOBOOT_MASTER_PORT]
+					.outbw[1].rowbar,
+					CONFIG_SYS_SRIO2_MEM_PHYS >> 12);
+			else
+				out_be32((void *)&srio->atmu
+					.port[CONFIG_SRIOBOOT_MASTER_PORT]
+					.outbw[1].rowbar,
+					CONFIG_SYS_SRIO1_MEM_PHYS >> 12);
+			out_be32((void *)&srio->atmu
+					.port[CONFIG_SRIOBOOT_MASTER_PORT]
+					.outbw[1].rowar,
+					SRIO_OB_ATMU_AR_MAINT
+					| atmu_size_mask(SRIO_MAINT_WIN_SIZE));
+
+			/*
+			 * configure outbound window
+			 * with R/W attribute to set slave's BRR
+			 */
+			out_be32((void *)&srio->atmu
+				.port[CONFIG_SRIOBOOT_MASTER_PORT]
+				.outbw[2].rowtar,
+				SRIO_LCSBA1CSR >> 9);
+			out_be32((void *)&srio->atmu
+				.port[CONFIG_SRIOBOOT_MASTER_PORT]
+				.outbw[2].rowtear, 0);
+			if (CONFIG_SRIOBOOT_MASTER_PORT)
+				out_be32((void *)&srio->atmu
+					.port[CONFIG_SRIOBOOT_MASTER_PORT]
+					.outbw[2].rowbar,
+					(CONFIG_SYS_SRIO2_MEM_PHYS
+					+ SRIO_MAINT_WIN_SIZE) >> 12);
+			else
+				out_be32((void *)&srio->atmu
+					.port[CONFIG_SRIOBOOT_MASTER_PORT]
+					.outbw[2].rowbar,
+					(CONFIG_SYS_SRIO1_MEM_PHYS
+					+ SRIO_MAINT_WIN_SIZE) >> 12);
+			out_be32((void *)&srio->atmu
+				.port[CONFIG_SRIOBOOT_MASTER_PORT]
+				.outbw[2].rowar,
+				SRIO_OB_ATMU_AR_RW
+				| atmu_size_mask(SRIO_RW_WIN_SIZE));
+
+			/*
+			 * Set the LCSBA1CSR register in slave
+			 * by the maint-outbound window
+			 */
+			if (CONFIG_SRIOBOOT_MASTER_PORT) {
+				out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
+					+ SRIO_LCSBA1CSR_OFFSET,
+					SRIO_LCSBA1CSR);
+				while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
+					+ SRIO_LCSBA1CSR_OFFSET)
+					!= SRIO_LCSBA1CSR)
+					;
+				/*
+				 * And then set the BRR register
+				 * to release slave core
+				 */
+				out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
+					+ SRIO_MAINT_WIN_SIZE
+					+ CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET,
+					CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK);
+			} else {
+				out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
+					+ SRIO_LCSBA1CSR_OFFSET,
+					SRIO_LCSBA1CSR);
+				while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
+					+ SRIO_LCSBA1CSR_OFFSET)
+					!= SRIO_LCSBA1CSR)
+					;
+				/*
+				 * And then set the BRR register
+				 * to release slave core
+				 */
+				out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
+					+ SRIO_MAINT_WIN_SIZE
+					+ CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET,
+					CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK);
+			}
+			debug("SRIOBOOT - MASTER: "
+					"Release slave successfully! Now the slave should start up!\n");
+		}
+	} else
+		debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n",
+				CONFIG_SRIOBOOT_MASTER_PORT);
+}
+#endif
+#endif
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 8654625fac..191629b628 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -65,6 +65,11 @@
 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	1
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 
 #elif defined(CONFIG_MPC8555)
 #define CONFIG_MAX_CPUS			1
@@ -85,6 +90,11 @@
 #define MAX_QE_RISC			2
 #define QE_NUM_OF_SNUM			28
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	1
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 
 #elif defined(CONFIG_MPC8569)
 #define CONFIG_MAX_CPUS			1
@@ -94,6 +104,11 @@
 #define MAX_QE_RISC			4
 #define QE_NUM_OF_SNUM			46
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	1
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 
 #elif defined(CONFIG_MPC8572)
 #define CONFIG_MAX_CPUS			2
@@ -298,6 +313,11 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 
 #elif defined(CONFIG_PPC_P2040)
 #define CONFIG_MAX_CPUS			4
@@ -317,6 +337,9 @@
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 
 #elif defined(CONFIG_PPC_P2041)
 #define CONFIG_MAX_CPUS			4
@@ -338,6 +361,9 @@
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 
 #elif defined(CONFIG_PPC_P3041)
 #define CONFIG_MAX_CPUS			4
@@ -359,6 +385,9 @@
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 
 #elif defined(CONFIG_PPC_P3060)
 #define CONFIG_MAX_CPUS			8
@@ -375,6 +404,9 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 
 #elif defined(CONFIG_PPC_P4040)
 #define CONFIG_MAX_CPUS			4
@@ -387,6 +419,9 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 
 #elif defined(CONFIG_PPC_P4080)
 #define CONFIG_MAX_CPUS			8
@@ -417,6 +452,11 @@
 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 
 /* P5010 is single core version of P5020 */
 #elif defined(CONFIG_PPC_P5010)
@@ -438,6 +478,9 @@
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 
 #elif defined(CONFIG_PPC_P5020)
 #define CONFIG_MAX_CPUS			2
@@ -458,6 +501,9 @@
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 
 #else
 #error Processor type not defined for this platform
diff --git a/arch/powerpc/include/asm/fsl_srio.h b/arch/powerpc/include/asm/fsl_srio.h
new file mode 100644
index 0000000000..a905a266c4
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_srio.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _FSL_SRIO_H_
+#define _FSL_SRIO_H_
+
+enum atmu_size {
+	ATMU_SIZE_4K = 0xb,
+	ATMU_SIZE_8K,
+	ATMU_SIZE_16K,
+	ATMU_SIZE_32K,
+	ATMU_SIZE_64K,
+	ATMU_SIZE_128K,
+	ATMU_SIZE_256K,
+	ATMU_SIZE_512K,
+	ATMU_SIZE_1M,
+	ATMU_SIZE_2M,
+	ATMU_SIZE_4M,
+	ATMU_SIZE_8M,
+	ATMU_SIZE_16M,
+	ATMU_SIZE_32M,
+	ATMU_SIZE_64M,
+	ATMU_SIZE_128M,
+	ATMU_SIZE_256M,
+	ATMU_SIZE_512M,
+	ATMU_SIZE_1G,
+	ATMU_SIZE_2G,
+	ATMU_SIZE_4G,
+	ATMU_SIZE_8G,
+	ATMU_SIZE_16G,
+	ATMU_SIZE_32G,
+	ATMU_SIZE_64G,
+};
+
+#define atmu_size_mask(sz)	(__ilog2_u64(sz) - 1)
+#define atmu_size_bytes(x)	(1ULL << ((x & 0x3f) + 1))
+
+extern void srio_init(void);
+#ifdef CONFIG_SRIOBOOT_MASTER
+extern void srio_boot_master(void);
+#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
+extern void srio_boot_master_release_slave(void);
+#endif
+#endif
+#endif
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 9b08cb8c1a..632e3c1669 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1353,171 +1353,235 @@ typedef struct ccsr_cpm {
 } ccsr_cpm_t;
 #endif
 
-/* RapidIO Registers */
-typedef struct ccsr_rio {
-	u32	didcar;		/* Device Identity Capability */
-	u32	dicar;		/* Device Information Capability */
-	u32	aidcar;		/* Assembly Identity Capability */
-	u32	aicar;		/* Assembly Information Capability */
-	u32	pefcar;		/* Processing Element Features Capability */
-	u32	spicar;		/* Switch Port Information Capability */
-	u32	socar;		/* Source Operations Capability */
-	u32	docar;		/* Destination Operations Capability */
+#ifdef CONFIG_SYS_SRIO
+/* Architectural regsiters */
+struct rio_arch {
+	u32	didcar;	/* Device Identity CAR */
+	u32	dicar;	/* Device Information CAR */
+	u32	aidcar;	/* Assembly Identity CAR */
+	u32	aicar;	/* Assembly Information CAR */
+	u32	pefcar;	/* Processing Element Features CAR */
+	u8	res0[4];
+	u32	socar;	/* Source Operations CAR */
+	u32	docar;	/* Destination Operations CAR */
 	u8	res1[32];
-	u32	msr;		/* Mailbox Cmd And Status */
-	u32	pwdcsr;		/* Port-Write & Doorbell Cmd And Status */
+	u32	mcsr;	/* Mailbox CSR */
+	u32	pwdcsr;	/* Port-Write and Doorbell CSR */
 	u8	res2[4];
 	u32	pellccsr;	/* Processing Element Logic Layer CCSR */
 	u8	res3[12];
-	u32	lcsbacsr;	/* Local Cfg Space Base Addr Cmd & Status */
-	u32	bdidcsr;	/* Base Device ID Cmd & Status */
+	u32	lcsbacsr;	/* Local Configuration Space BACSR */
+	u32	bdidcsr;	/* Base Device ID CSR */
 	u8	res4[4];
-	u32	hbdidlcsr;	/* Host Base Device ID Lock Cmd & Status */
-	u32	ctcsr;		/* Component Tag Cmd & Status */
-	u8	res5[144];
-	u32	pmbh0csr;	/* Port Maint. Block Hdr 0 Cmd & Status */
-	u8	res6[28];
-	u32	pltoccsr;	/* Port Link Time-out Ctrl Cmd & Status */
-	u32	prtoccsr;	/* Port Response Time-out Ctrl Cmd & Status */
-	u8	res7[20];
-	u32	pgccsr;		/* Port General Cmd & Status */
-	u32	plmreqcsr;	/* Port Link Maint. Request Cmd & Status */
-	u32	plmrespcsr;	/* Port Link Maint. Response Cmd & Status */
-	u32	plascsr;	/* Port Local Ackid Status Cmd & Status */
-	u8	res8[12];
-	u32	pescsr;		/* Port Error & Status Cmd & Status */
-	u32	pccsr;		/* Port Control Cmd & Status */
-	u8	res9[65184];
-	u32	cr;		/* Port Control Cmd & Status */
-	u8	res10[12];
-	u32	pcr;		/* Port Configuration */
-	u32	peir;		/* Port Error Injection */
-	u8	res11[3048];
-	u32	rowtar0;	/* RIO Outbound Window Translation Addr 0 */
-	u8	res12[12];
-	u32	rowar0;		/* RIO Outbound Attrs 0 */
-	u8	res13[12];
-	u32	rowtar1;	/* RIO Outbound Window Translation Addr 1 */
-	u8	res14[4];
-	u32	rowbar1;	/* RIO Outbound Window Base Addr 1 */
-	u8	res15[4];
-	u32	rowar1;		/* RIO Outbound Attrs 1 */
-	u8	res16[12];
-	u32	rowtar2;	/* RIO Outbound Window Translation Addr 2 */
-	u8	res17[4];
-	u32	rowbar2;	/* RIO Outbound Window Base Addr 2 */
-	u8	res18[4];
-	u32	rowar2;		/* RIO Outbound Attrs 2 */
-	u8	res19[12];
-	u32	rowtar3;	/* RIO Outbound Window Translation Addr 3 */
-	u8	res20[4];
-	u32	rowbar3;	/* RIO Outbound Window Base Addr 3 */
-	u8	res21[4];
-	u32	rowar3;		/* RIO Outbound Attrs 3 */
-	u8	res22[12];
-	u32	rowtar4;	/* RIO Outbound Window Translation Addr 4 */
-	u8	res23[4];
-	u32	rowbar4;	/* RIO Outbound Window Base Addr 4 */
-	u8	res24[4];
-	u32	rowar4;		/* RIO Outbound Attrs 4 */
-	u8	res25[12];
-	u32	rowtar5;	/* RIO Outbound Window Translation Addr 5 */
-	u8	res26[4];
-	u32	rowbar5;	/* RIO Outbound Window Base Addr 5 */
-	u8	res27[4];
-	u32	rowar5;		/* RIO Outbound Attrs 5 */
-	u8	res28[12];
-	u32	rowtar6;	/* RIO Outbound Window Translation Addr 6 */
-	u8	res29[4];
-	u32	rowbar6;	/* RIO Outbound Window Base Addr 6 */
-	u8	res30[4];
-	u32	rowar6;		/* RIO Outbound Attrs 6 */
-	u8	res31[12];
-	u32	rowtar7;	/* RIO Outbound Window Translation Addr 7 */
-	u8	res32[4];
-	u32	rowbar7;	/* RIO Outbound Window Base Addr 7 */
-	u8	res33[4];
-	u32	rowar7;		/* RIO Outbound Attrs 7 */
-	u8	res34[12];
-	u32	rowtar8;	/* RIO Outbound Window Translation Addr 8 */
-	u8	res35[4];
-	u32	rowbar8;	/* RIO Outbound Window Base Addr 8 */
-	u8	res36[4];
-	u32	rowar8;		/* RIO Outbound Attrs 8 */
-	u8	res37[76];
-	u32	riwtar4;	/* RIO Inbound Window Translation Addr 4 */
-	u8	res38[4];
-	u32	riwbar4;	/* RIO Inbound Window Base Addr 4 */
-	u8	res39[4];
-	u32	riwar4;		/* RIO Inbound Attrs 4 */
-	u8	res40[12];
-	u32	riwtar3;	/* RIO Inbound Window Translation Addr 3 */
-	u8	res41[4];
-	u32	riwbar3;	/* RIO Inbound Window Base Addr 3 */
-	u8	res42[4];
-	u32	riwar3;		/* RIO Inbound Attrs 3 */
-	u8	res43[12];
-	u32	riwtar2;	/* RIO Inbound Window Translation Addr 2 */
-	u8	res44[4];
-	u32	riwbar2;	/* RIO Inbound Window Base Addr 2 */
-	u8	res45[4];
-	u32	riwar2;		/* RIO Inbound Attrs 2 */
-	u8	res46[12];
-	u32	riwtar1;	/* RIO Inbound Window Translation Addr 1 */
-	u8	res47[4];
-	u32	riwbar1;	/* RIO Inbound Window Base Addr 1 */
-	u8	res48[4];
-	u32	riwar1;		/* RIO Inbound Attrs 1 */
-	u8	res49[12];
-	u32	riwtar0;	/* RIO Inbound Window Translation Addr 0 */
-	u8	res50[12];
-	u32	riwar0;		/* RIO Inbound Attrs 0 */
-	u8	res51[12];
-	u32	pnfedr;		/* Port Notification/Fatal Error Detect */
-	u32	pnfedir;	/* Port Notification/Fatal Error Detect */
-	u32	pnfeier;	/* Port Notification/Fatal Error IRQ Enable */
-	u32	pecr;		/* Port Error Control */
-	u32	pepcsr0;	/* Port Error Packet/Control Symbol 0 */
-	u32	pepr1;		/* Port Error Packet 1 */
-	u32	pepr2;		/* Port Error Packet 2 */
-	u8	res52[4];
-	u32	predr;		/* Port Recoverable Error Detect */
-	u8	res53[4];
-	u32	pertr;		/* Port Error Recovery Threshold */
-	u32	prtr;		/* Port Retry Threshold */
-	u8	res54[464];
-	u32	omr;		/* Outbound Mode */
-	u32	osr;		/* Outbound Status */
-	u32	eodqtpar;	/* Extended Outbound Desc Queue Tail Ptr Addr */
-	u32	odqtpar;	/* Outbound Desc Queue Tail Ptr Addr */
-	u32	eosar;		/* Extended Outbound Unit Source Addr */
-	u32	osar;		/* Outbound Unit Source Addr */
-	u32	odpr;		/* Outbound Destination Port */
-	u32	odatr;		/* Outbound Destination Attrs */
-	u32	odcr;		/* Outbound Doubleword Count */
-	u32	eodqhpar;	/* Extended Outbound Desc Queue Head Ptr Addr */
-	u32	odqhpar;	/* Outbound Desc Queue Head Ptr Addr */
-	u8	res55[52];
-	u32	imr;		/* Outbound Mode */
-	u32	isr;		/* Inbound Status */
-	u32	eidqtpar;	/* Extended Inbound Desc Queue Tail Ptr Addr */
-	u32	idqtpar;	/* Inbound Desc Queue Tail Ptr Addr */
-	u32	eifqhpar;	/* Extended Inbound Frame Queue Head Ptr Addr */
-	u32	ifqhpar;	/* Inbound Frame Queue Head Ptr Addr */
-	u8	res56[1000];
-	u32	dmr;		/* Doorbell Mode */
-	u32	dsr;		/* Doorbell Status */
-	u32	edqtpar;	/* Extended Doorbell Queue Tail Ptr Addr */
-	u32	dqtpar;		/* Doorbell Queue Tail Ptr Addr */
-	u32	edqhpar;	/* Extended Doorbell Queue Head Ptr Addr */
-	u32	dqhpar;		/* Doorbell Queue Head Ptr Addr */
-	u8	res57[104];
-	u32	pwmr;		/* Port-Write Mode */
-	u32	pwsr;		/* Port-Write Status */
-	u32	epwqbar;	/* Extended Port-Write Queue Base Addr */
-	u32	pwqbar;		/* Port-Write Queue Base Addr */
-	u8	res58[60176];
-} ccsr_rio_t;
+	u32	hbdidlcsr;	/* Host Base Device ID Lock CSR */
+	u32	ctcsr;	/* Component Tag CSR */
+};
+
+/* Extended Features Space: 1x/4x LP-Serial Port registers */
+struct rio_lp_serial_port {
+	u32	plmreqcsr;	/* Port Link Maintenance Request CSR */
+	u32	plmrespcsr;	/* Port Link Maintenance Response CS */
+	u32	plascsr;	/* Port Local Ackid Status CSR */
+	u8	res0[12];
+	u32	pescsr;	/* Port Error and Status CSR */
+	u32	pccsr;	/* Port Control CSR */
+};
+
+/* Extended Features Space: 1x/4x LP-Serial registers */
+struct rio_lp_serial {
+	u32	pmbh0csr;	/* Port Maintenance Block Header 0 CSR */
+	u8	res0[28];
+	u32	pltoccsr;	/* Port Link Time-out CCSR */
+	u32	prtoccsr;	/* Port Response Time-out CCSR */
+	u8	res1[20];
+	u32	pgccsr;	/* Port General CSR */
+	struct rio_lp_serial_port	port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+};
+
+/* Logical error reporting registers */
+struct rio_logical_err {
+	u32	erbh;	/* Error Reporting Block Header Register */
+	u8	res0[4];
+	u32	ltledcsr;	/* Logical/Transport layer error DCSR */
+	u32	ltleecsr;	/* Logical/Transport layer error ECSR */
+	u8	res1[4];
+	u32	ltlaccsr;	/* Logical/Transport layer ACCSR */
+	u32	ltldidccsr;	/* Logical/Transport layer DID CCSR */
+	u32	ltlcccsr;	/* Logical/Transport layer control CCSR */
+};
+
+/* Physical error reporting port registers */
+struct rio_phys_err_port {
+	u32	edcsr;	/* Port error detect CSR */
+	u32	erecsr;	/* Port error rate enable CSR */
+	u32	ecacsr;	/* Port error capture attributes CSR */
+	u32	pcseccsr0;	/* Port packet/control symbol ECCSR 0 */
+	u32	peccsr[3];	/* Port error capture CSR */
+	u8	res0[12];
+	u32	ercsr;	/* Port error rate CSR */
+	u32	ertcsr;	/* Port error rate threshold CSR */
+	u8	res1[16];
+};
+
+/* Physical error reporting registers */
+struct rio_phys_err {
+	struct rio_phys_err_port	port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+};
+
+/* Implementation Space: General Port-Common */
+struct rio_impl_common {
+	u8	res0[4];
+	u32	llcr;	/* Logical Layer Configuration Register */
+	u8	res1[8];
+	u32	epwisr;	/* Error / Port-Write Interrupt SR */
+	u8	res2[12];
+	u32	lretcr;	/* Logical Retry Error Threshold CR */
+	u8	res3[92];
+	u32	pretcr;	/* Physical Retry Erorr Threshold CR */
+	u8	res4[124];
+};
+
+/* Implementation Space: Port Specific */
+struct rio_impl_port_spec {
+	u32	adidcsr;	/* Port Alt. Device ID CSR */
+	u8	res0[28];
+	u32	ptaacr;	/* Port Pass-Through/Accept-All CR */
+	u32	lopttlcr;
+	u8	res1[8];
+	u32	iecsr;	/* Port Implementation Error CSR */
+	u8	res2[12];
+	u32	pcr;		/* Port Phsyical Configuration Register */
+	u8	res3[20];
+	u32	slcsr;	/* Port Serial Link CSR */
+	u8	res4[4];
+	u32	sleicr;	/* Port Serial Link Error Injection */
+	u32	a0txcr;	/* Port Arbitration 0 Tx CR */
+	u32	a1txcr;	/* Port Arbitration 1 Tx CR */
+	u32	a2txcr;	/* Port Arbitration 2 Tx CR */
+	u32	mreqtxbacr[3];	/* Port Request Tx Buffer ACR */
+	u32	mrspfctxbacr;	/* Port Response/Flow Control Tx Buffer ACR */
+};
+
+/* Implementation Space: register */
+struct rio_implement {
+	struct rio_impl_common	com;
+	struct rio_impl_port_spec	port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+};
+
+/* Revision Control Register */
+struct rio_rev_ctrl {
+	u32	ipbrr[2];	/* IP Block Revision Register */
+};
+
+struct rio_atmu_row {
+	u32	rowtar; /* RapidIO Outbound Window TAR */
+	u32	rowtear; /* RapidIO Outbound Window TEAR */
+	u32	rowbar;
+	u8	res0[4];
+	u32	rowar; /* RapidIO Outbound Attributes Register */
+	u32	rowsr[3]; /* Port RapidIO outbound window segment register */
+};
+
+struct rio_atmu_riw {
+	u32	riwtar; /* RapidIO Inbound Window Translation AR */
+	u8	res0[4];
+	u32	riwbar; /* RapidIO Inbound Window Base AR */
+	u8	res1[4];
+	u32	riwar; /* RapidIO Inbound Attributes Register */
+	u8	res2[12];
+};
+
+/* ATMU window registers */
+struct rio_atmu_win {
+	struct rio_atmu_row	outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM];
+	u8	res0[64];
+	struct rio_atmu_riw	inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM];
+};
+
+struct rio_atmu {
+	struct rio_atmu_win	port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+};
+
+#ifdef CONFIG_SYS_FSL_RMU
+struct rio_msg {
+	u32	omr; /* Outbound Mode Register */
+	u32	osr; /* Outbound Status Register */
+	u32	eodqdpar; /* Extended Outbound DQ DPAR */
+	u32	odqdpar; /* Outbound Descriptor Queue DPAR */
+	u32	eosar; /* Extended Outbound Unit Source AR */
+	u32	osar; /* Outbound Unit Source AR */
+	u32	odpr; /* Outbound Destination Port Register */
+	u32	odatr; /* Outbound Destination Attributes Register */
+	u32	odcr; /* Outbound Doubleword Count Register */
+	u32	eodqepar; /* Extended Outbound DQ EPAR */
+	u32	odqepar; /* Outbound Descriptor Queue EPAR */
+	u32	oretr; /* Outbound Retry Error Threshold Register */
+	u32	omgr; /* Outbound Multicast Group Register */
+	u32	omlr; /* Outbound Multicast List Register */
+	u8	res0[40];
+	u32	imr;	 /* Outbound Mode Register */
+	u32	isr; /* Inbound Status Register */
+	u32	eidqdpar; /* Extended Inbound Descriptor Queue DPAR */
+	u32	idqdpar; /* Inbound Descriptor Queue DPAR */
+	u32	eifqepar; /* Extended Inbound Frame Queue EPAR */
+	u32	ifqepar; /* Inbound Frame Queue EPAR */
+	u32	imirir; /* Inbound Maximum Interrutp RIR */
+	u8	res1[4];
+	u32 eihqepar; /* Extended inbound message header queue EPAR */
+	u32 ihqepar; /* Inbound message header queue EPAR */
+	u8	res2[120];
+};
+
+struct rio_dbell {
+	u32	odmr; /* Outbound Doorbell Mode Register */
+	u32	odsr; /* Outbound Doorbell Status Register */
+	u8	res0[16];
+	u32	oddpr; /* Outbound Doorbell Destination Port */
+	u32	oddatr; /* Outbound Doorbell Destination AR */
+	u8	res1[12];
+	u32	oddretr; /* Outbound Doorbell Retry Threshold CR */
+	u8	res2[48];
+	u32	idmr; /* Inbound Doorbell Mode Register */
+	u32	idsr;	 /* Inbound Doorbell Status Register */
+	u32	iedqdpar; /* Extended Inbound Doorbell Queue DPAR */
+	u32	iqdpar; /* Inbound Doorbell Queue DPAR */
+	u32	iedqepar; /* Extended Inbound Doorbell Queue EPAR */
+	u32	idqepar; /* Inbound Doorbell Queue EPAR */
+	u32	idmirir; /* Inbound Doorbell Max Interrupt RIR */
+};
+
+struct rio_pw {
+	u32	pwmr; /* Port-Write Mode Register */
+	u32	pwsr; /* Port-Write Status Register */
+	u32	epwqbar; /* Extended Port-Write Queue BAR */
+	u32	pwqbar; /* Port-Write Queue Base Address Register */
+};
+#endif
+
+/* RapidIO Registers */
+struct ccsr_rio {
+	struct rio_arch	arch;
+	u8	res0[144];
+	struct rio_lp_serial	lp_serial;
+	u8	res1[1152];
+	struct rio_logical_err	logical_err;
+	u8	res2[32];
+	struct rio_phys_err	phys_err;
+	u8	res3[63808];
+	struct rio_implement	impl;
+	u8	res4[2552];
+	struct rio_rev_ctrl	rev;
+	struct rio_atmu	atmu;
+#ifdef CONFIG_SYS_FSL_RMU
+	u8	res5[8192];
+	struct rio_msg	msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM];
+	u8	res6[512];
+	struct rio_dbell	dbell;
+	u8	res7[100];
+	struct rio_pw	pw;
+#endif
+};
+#endif
 
 /* Quick Engine Block Pin Muxing Registers */
 typedef struct par_io {
@@ -2443,6 +2507,7 @@ struct ccsr_rman {
 
 #define CONFIG_SYS_MPC85xx_PIC_OFFSET		0x40000
 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET		0xE0000
+#define CONFIG_SYS_FSL_SRIO_OFFSET		0xC0000
 
 #define CONFIG_SYS_FSL_CPC_ADDR	\
 	(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
@@ -2516,6 +2581,8 @@ struct ccsr_rman {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
 #define CONFIG_SYS_FSL_FM2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
+#define CONFIG_SYS_FSL_SRIO_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
 
 #define CONFIG_SYS_PCI1_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h
index b2fa2b574b..1552054117 100644
--- a/arch/powerpc/include/asm/u-boot.h
+++ b/arch/powerpc/include/asm/u-boot.h
@@ -63,7 +63,6 @@ typedef struct bd_info {
 	unsigned long   bi_vcofreq;     /* VCO Freq, in MHz */
 #endif
 	unsigned long	bi_bootflags;	/* boot / reboot flag (Unused) */
-	unsigned long	bi_ip_addr;	/* IP Address */
 	unsigned char	bi_enetaddr[6];	/* OLD: see README.enetaddr */
 	unsigned short	bi_ethspeed;	/* Ethernet speed in Mbps */
 	unsigned long	bi_intfreq;	/* Internal Freq, in MHz */
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index d5b75e5fbd..fea310eedd 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -877,9 +877,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
 #endif
 #endif /* CONFIG_CMD_NET */
 
-	/* IP Address */
-	bd->bi_ip_addr = getenv_IPaddr("ipaddr");
-
 	WATCHDOG_RESET();
 
 #if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT)
@@ -935,14 +932,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
 
 	/* Initialize from environment */
 	load_addr = getenv_ulong("loadaddr", 16, load_addr);
-#if defined(CONFIG_CMD_NET)
-	{
-		char *s = getenv("bootfile");
-
-		if (s != NULL)
-			copy_filename(BootFile, s, sizeof(BootFile));
-	}
-#endif
 
 	WATCHDOG_RESET();
 
diff --git a/arch/sandbox/include/asm/u-boot.h b/arch/sandbox/include/asm/u-boot.h
index 166ef14341..de8120a723 100644
--- a/arch/sandbox/include/asm/u-boot.h
+++ b/arch/sandbox/include/asm/u-boot.h
@@ -45,7 +45,6 @@ typedef struct bd_info {
 	unsigned long	bi_sramstart;	/* start of SRAM memory */
 	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
 	unsigned long	bi_bootflags;	/* boot / reboot flag (for LynxOS) */
-	unsigned long	bi_ip_addr;	/* IP Address */
 	unsigned short	bi_ethspeed;	/* Ethernet speed in Mbps */
 	unsigned long	bi_intfreq;	/* Internal Freq, in MHz */
 	unsigned long	bi_busfreq;	/* Bus Freq, in MHz */
diff --git a/arch/sandbox/lib/board.c b/arch/sandbox/lib/board.c
index 306d1ec332..c173bf96f0 100644
--- a/arch/sandbox/lib/board.c
+++ b/arch/sandbox/lib/board.c
@@ -235,9 +235,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
 	/* initialize environment */
 	env_relocate();
 
-	/* IP Address */
-	gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
-
 	stdio_init();	/* get the devices list going. */
 
 	jumptable_init();
diff --git a/arch/sh/include/asm/u-boot.h b/arch/sh/include/asm/u-boot.h
index 45745129a0..6c04daf3bc 100644
--- a/arch/sh/include/asm/u-boot.h
+++ b/arch/sh/include/asm/u-boot.h
@@ -33,7 +33,6 @@ typedef struct bd_info {
 	unsigned long   bi_flashoffset; /* reserved area for startup monitor */
 	unsigned long   bi_sramstart;   /* start of SRAM memory */
 	unsigned long   bi_sramsize;    /* size  of SRAM memory */
-	unsigned long   bi_ip_addr;     /* IP Address */
 	unsigned long   bi_baudrate;    /* Console Baudrate */
 	unsigned long	bi_boot_params; /* where this board expects params */
 } bd_t;
diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c
index eb021e806c..34d7881f44 100644
--- a/arch/sh/lib/board.c
+++ b/arch/sh/lib/board.c
@@ -100,14 +100,6 @@ static int sh_mem_env_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_CMD_NET)
-static int sh_net_init(void)
-{
-	gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
-	return 0;
-}
-#endif
-
 #if defined(CONFIG_CMD_MMC)
 static int sh_mmc_init(void)
 {
@@ -145,9 +137,6 @@ init_fnc_t *init_sequence[] =
 #ifdef CONFIG_BOARD_LATE_INIT
 	board_late_init,
 #endif
-#if defined(CONFIG_CMD_NET)
-	sh_net_init,		/* SH specific eth init */
-#endif
 #if defined(CONFIG_CMD_MMC)
 	sh_mmc_init,
 #endif
@@ -201,15 +190,8 @@ void sh_generic_init(void)
 	bb_miiphy_init();
 #endif
 #if defined(CONFIG_CMD_NET)
-	{
-		char *s;
-		puts("Net:   ");
-		eth_initialize(gd->bd);
-
-		s = getenv("bootfile");
-		if (s != NULL)
-			copy_filename(BootFile, s, sizeof(BootFile));
-	}
+	puts("Net:   ");
+	eth_initialize(gd->bd);
 #endif /* CONFIG_CMD_NET */
 
 	while (1) {
diff --git a/arch/sparc/include/asm/u-boot.h b/arch/sparc/include/asm/u-boot.h
index 1d94087aab..8d011185a0 100644
--- a/arch/sparc/include/asm/u-boot.h
+++ b/arch/sparc/include/asm/u-boot.h
@@ -51,7 +51,6 @@ typedef struct bd_info {
 	unsigned long bi_sramstart;	/* start of SRAM memory */
 	unsigned long bi_sramsize;	/* size  of SRAM memory */
 	unsigned long bi_bootflags;	/* boot / reboot flag (for LynxOS) */
-	unsigned long bi_ip_addr;	/* IP Address */
 	unsigned short bi_ethspeed;	/* Ethernet speed in Mbps */
 	unsigned long bi_intfreq;	/* Internal Freq, in MHz */
 	unsigned long bi_busfreq;	/* Bus Freq, in MHz */
diff --git a/arch/sparc/lib/board.c b/arch/sparc/lib/board.c
index c0d260840c..7e48775dfe 100644
--- a/arch/sparc/lib/board.c
+++ b/arch/sparc/lib/board.c
@@ -333,8 +333,6 @@ void board_init_f(ulong bootflag)
 	mac_read_from_eeprom();
 #endif
 
-	/* IP Address */
-	bd->bi_ip_addr = getenv_IPaddr("ipaddr");
 #if defined(CONFIG_PCI)
 	/*
 	 * Do pci configuration
@@ -359,11 +357,6 @@ void board_init_f(ulong bootflag)
 
 	/* Initialize from environment */
 	load_addr = getenv_ulong("loadaddr", 16, load_addr);
-#if defined(CONFIG_CMD_NET)
-	if ((s = getenv("bootfile")) != NULL) {
-		copy_filename(BootFile, s, sizeof(BootFile));
-	}
-#endif /* CONFIG_CMD_NET */
 
 	WATCHDOG_RESET();
 
diff --git a/arch/x86/include/asm/init_helpers.h b/arch/x86/include/asm/init_helpers.h
index 192f18e1d5..8afb443290 100644
--- a/arch/x86/include/asm/init_helpers.h
+++ b/arch/x86/include/asm/init_helpers.h
@@ -36,9 +36,7 @@ int set_reloc_flag_r(void);
 int mem_malloc_init_r(void);
 int init_bd_struct_r(void);
 int flash_init_r(void);
-int init_ip_address_r(void);
 int status_led_set_r(void);
-int set_bootfile_r(void);
 int set_load_addr_r(void);
 
 #endif	/* !_INIT_HELPERS_H_ */
diff --git a/arch/x86/include/asm/u-boot.h b/arch/x86/include/asm/u-boot.h
index 26450ebc44..da667c50a4 100644
--- a/arch/x86/include/asm/u-boot.h
+++ b/arch/x86/include/asm/u-boot.h
@@ -45,7 +45,6 @@ typedef struct bd_info {
 	unsigned long	bi_sramstart;	/* start of SRAM memory */
 	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
 	unsigned long	bi_bootflags;	/* boot / reboot flag (for LynxOS) */
-	unsigned long	bi_ip_addr;	/* IP Address */
 	unsigned short	bi_ethspeed;	/* Ethernet speed in Mbps */
 	unsigned long	bi_intfreq;	/* Internal Freq, in MHz */
 	unsigned long	bi_busfreq;	/* Bus Freq, in MHz */
diff --git a/arch/x86/lib/board.c b/arch/x86/lib/board.c
index 5f0b62cea6..90cf7fc888 100644
--- a/arch/x86/lib/board.c
+++ b/arch/x86/lib/board.c
@@ -157,9 +157,6 @@ init_fnc_t *init_sequence_r[] = {
 	flash_init_r,
 #endif
 	env_relocate_r,
-#ifdef CONFIG_CMD_NET
-	init_ip_address_r,
-#endif
 #ifdef CONFIG_PCI
 	pci_init_r,
 #endif
@@ -180,9 +177,6 @@ init_fnc_t *init_sequence_r[] = {
 	status_led_set_r,
 #endif
 	set_load_addr_r,
-#if defined(CONFIG_CMD_NET)
-	set_bootfile_r,
-#endif
 #if defined(CONFIG_CMD_IDE)
 	ide_init_r,
 #endif
diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c
index 9f4dee034f..9ec34ff992 100644
--- a/arch/x86/lib/init_helpers.c
+++ b/arch/x86/lib/init_helpers.c
@@ -179,14 +179,6 @@ int flash_init_r(void)
 }
 #endif
 
-int init_ip_address_r(void)
-{
-	/* IP Address */
-	bd_data.bi_ip_addr = getenv_IPaddr("ipaddr");
-
-	return 0;
-}
-
 #ifdef CONFIG_STATUS_LED
 int status_led_set_r(void)
 {
@@ -196,18 +188,6 @@ int status_led_set_r(void)
 }
 #endif
 
-int set_bootfile_r(void)
-{
-	char *s;
-
-	s = getenv("bootfile");
-
-	if (s != NULL)
-		copy_filename(BootFile, s, sizeof(BootFile));
-
-	return 0;
-}
-
 int set_load_addr_r(void)
 {
 	/* Initialize from environment */
diff --git a/board/gdsys/neo/Makefile b/board/AndesTech/adp-ag102/Makefile
index dc5b5b887a..1cbf2d46dd 100644
--- a/board/gdsys/neo/Makefile
+++ b/board/AndesTech/adp-ag102/Makefile
@@ -1,6 +1,6 @@
 #
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
+# Copyright (C) 2011 Andes Technology Corporation
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -25,15 +25,13 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	= $(BOARD).o
-SOBJS   =
+COBJS	:= adp-ag102.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
 
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
 
 #########################################################################
 
diff --git a/board/AndesTech/adp-ag102/adp-ag102.c b/board/AndesTech/adp-ag102/adp-ag102.c
new file mode 100644
index 0000000000..5a25632250
--- /dev/null
+++ b/board/AndesTech/adp-ag102/adp-ag102.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <faraday/ftsdc010.h>
+#ifdef CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+	/*
+	 * refer to BOOT_PARAMETER_PA_BASE within
+	 * "linux/arch/nds32/include/asm/misc_spec.h"
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_ADPAG102;
+	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+	ftsmc020_init();	/* initialize Flash */
+#endif /* CONFIG_SYS_NO_FLASH */
+	return 0;
+}
+
+int dram_init(void)
+{
+	unsigned long sdram_base = PHYS_SDRAM_0;
+	unsigned long expected_size = PHYS_SDRAM_0_SIZE;
+	unsigned long actual_size;
+
+	actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+	gd->ram_size = actual_size;
+
+	if (expected_size != actual_size) {
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+	}
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+	return ftgmac100_initialize(bd);
+}
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = FLASH_CFI_8BIT;
+		info->chipwidth = FLASH_CFI_BY8;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else {
+		return 0;
+	}
+}
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+void pci_init_board(void)
+{
+	/* should be pci_ftpci100_init() */
+	extern void pci_ftpci_init();
+
+	pci_ftpci_init();
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	ftsdc010_mmc_init(0);
+	return 0;
+}
+#endif
diff --git a/board/Marvell/db64360/mv_eth.c b/board/Marvell/db64360/mv_eth.c
index e89ea43d7b..1874cd1e73 100644
--- a/board/Marvell/db64360/mv_eth.c
+++ b/board/Marvell/db64360/mv_eth.c
@@ -95,8 +95,6 @@ int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length);
 #ifndef  UPDATE_STATS_BY_SOFTWARE
 static void mv64360_eth_print_stat (struct eth_device *dev);
 #endif
-/* Processes a received packet */
-extern void NetReceive (volatile uchar *, int);
 
 extern unsigned int INTERNAL_REG_BASE_ADDR;
 
@@ -192,8 +190,7 @@ int db64360_eth_poll (struct eth_device *dev)
 	return mv64360_eth_receive (dev);
 }
 
-int db64360_eth_transmit (struct eth_device *dev, volatile void *packet,
-			  int length)
+int db64360_eth_transmit(struct eth_device *dev, void *packet, int length)
 {
 	mv64360_eth_xmit (dev, packet, length);
 	return 0;
diff --git a/board/Marvell/db64360/mv_eth.h b/board/Marvell/db64360/mv_eth.h
index 142910b598..bd8e05dafd 100644
--- a/board/Marvell/db64360/mv_eth.h
+++ b/board/Marvell/db64360/mv_eth.h
@@ -167,9 +167,7 @@ struct mv64360_eth_priv {
 
 int mv64360_eth_init (struct eth_device *dev);
 int mv64360_eth_stop (struct eth_device *dev);
-int mv64360_eth_start_xmit (struct eth_device*, volatile void* packet, int length);
-/*	return db64360_eth0_poll(); */
-
+int mv64360_eth_start_xmit(struct eth_device *dev, void *packet, int length);
 int mv64360_eth_open (struct eth_device *dev);
 
 
diff --git a/board/Marvell/db64460/mv_eth.c b/board/Marvell/db64460/mv_eth.c
index a763d795cb..a24a7e8072 100644
--- a/board/Marvell/db64460/mv_eth.c
+++ b/board/Marvell/db64460/mv_eth.c
@@ -95,8 +95,6 @@ int mv64460_eth_xmit (struct eth_device *, volatile void *packet, int length);
 #ifndef  UPDATE_STATS_BY_SOFTWARE
 static void mv64460_eth_print_stat (struct eth_device *dev);
 #endif
-/* Processes a received packet */
-extern void NetReceive (volatile uchar *, int);
 
 extern unsigned int INTERNAL_REG_BASE_ADDR;
 
@@ -192,8 +190,7 @@ int db64460_eth_poll (struct eth_device *dev)
 	return mv64460_eth_receive (dev);
 }
 
-int db64460_eth_transmit (struct eth_device *dev, volatile void *packet,
-			  int length)
+int db64460_eth_transmit(struct eth_device *dev, void *packet, int length)
 {
 	mv64460_eth_xmit (dev, packet, length);
 	return 0;
diff --git a/board/Marvell/db64460/mv_eth.h b/board/Marvell/db64460/mv_eth.h
index cbe751a4ce..af4e818fe8 100644
--- a/board/Marvell/db64460/mv_eth.h
+++ b/board/Marvell/db64460/mv_eth.h
@@ -166,9 +166,7 @@ struct mv64460_eth_priv {
 
 int mv64460_eth_init (struct eth_device *dev);
 int mv64460_eth_stop (struct eth_device *dev);
-int mv64460_eth_start_xmit (struct eth_device*, volatile void* packet, int length);
-/*	return db64460_eth0_poll(); */
-
+int mv64460_eth_start_xmit(struct eth_device *dev, void *packet, int length);
 int mv64460_eth_open (struct eth_device *dev);
 
 
diff --git a/board/avnet/fx12mm/.gitignore b/board/avnet/fx12mm/.gitignore
deleted file mode 100644
index b644f59941..0000000000
--- a/board/avnet/fx12mm/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-config.tmp
diff --git a/board/avnet/v5fx30teval/.gitignore b/board/avnet/v5fx30teval/.gitignore
deleted file mode 100644
index f6418a0c50..0000000000
--- a/board/avnet/v5fx30teval/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/config.tmp
diff --git a/board/cloudengines/pogo_e02/Makefile b/board/cloudengines/pogo_e02/Makefile
new file mode 100644
index 0000000000..7f866910e8
--- /dev/null
+++ b/board/cloudengines/pogo_e02/Makefile
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= pogo_e02.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/cloudengines/pogo_e02/kwbimage.cfg b/board/cloudengines/pogo_e02/kwbimage.cfg
new file mode 100644
index 0000000000..a02e88d97b
--- /dev/null
+++ b/board/cloudengines/pogo_e02/kwbimage.cfg
@@ -0,0 +1,169 @@
+#
+# Copyright (C) 2012
+# David Purdy <david.c.purdy@gmail.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla <at> marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; If not, see <http://www.gnu.org/licenses/>.
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	nand
+NAND_ECC_MODE	default
+NAND_PAGE_SIZE	0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xffd100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xffd01400 0x43000c30	# DDR Configuration register
+# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xffd01404 0x37543000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xffd01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xffd0140c 0x00000a33	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xffd01410 0x000000cc	#  DDR Address Control
+# bit1-0:   00, Cs0width=x8
+# bit3-2:   11, Cs0size=1Gb
+# bit5-4:   00, Cs1width=x8
+# bit7-6:   11, Cs1size=1Gb
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xffd01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xffd01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xffd0141c 0x00000c52	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xffd01420 0x00000040	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    0,  DDR drive strenght normal
+# bit2:    0,  DDR ODT control lsd (disabled)
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, (disabled)
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xffd01424 0x0000f17f	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xffd01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xffd0147c 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xffd01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xffd01504 0x0ffffff1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xffd01508 0x10000000	# CS[1]n Base address to 256Mb
+DATA 0xffd0150c 0x00000000	# CS[2]n Size, window disabled
+
+DATA 0xffd01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xffd0151c 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xffd01494 0x00030000	#  DDR ODT Control (Low)
+# bit3-0:  2, ODT0Rd, MODT[0] asserted during read from DRAM CS1
+# bit7-4:  1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
+# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xffd01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xffd0149c 0x0000e803	# CPU ODT Control
+DATA 0xffd01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/cloudengines/pogo_e02/pogo_e02.c b/board/cloudengines/pogo_e02/pogo_e02.c
new file mode 100644
index 0000000000..ff3421d576
--- /dev/null
+++ b/board/cloudengines/pogo_e02/pogo_e02.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2012
+ * David Purdy <david.c.purdy@gmail.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include "pogo_e02.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the  below configuration configures mainly initial LED status
+	 */
+	kw_config_gpio(POGO_E02_OE_VAL_LOW,
+			POGO_E02_OE_VAL_HIGH,
+			POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	u32 kwmpp_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,
+		MPP8_UART0_RTS,
+		MPP9_UART0_CTS,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_SD_CLK,
+		MPP13_SD_CMD,
+		MPP14_SD_D0,
+		MPP15_SD_D1,
+		MPP16_SD_D2,
+		MPP17_SD_D3,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP29_TSMP9,	/* USB Power Enable */
+		MPP48_GPIO,	/* LED green */
+		MPP49_GPIO,	/* LED orange */
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Boot parameters address */
+	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and initialize PHY */
+void reset_phy(void)
+{
+	u16 reg;
+	u16 devadr;
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+		printf("Err..(%s) could not read PHY dev address\n", __func__);
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	debug("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/cloudengines/pogo_e02/pogo_e02.h b/board/cloudengines/pogo_e02/pogo_e02.h
new file mode 100644
index 0000000000..40b4bab9e0
--- /dev/null
+++ b/board/cloudengines/pogo_e02/pogo_e02.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2012
+ * David Purdy <david.c.purdy@gmail.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __POGO_E02_H
+#define __POGO_E02_H
+
+/* GPIO configuration */
+#define POGO_E02_OE_LOW				(~(0))
+#define POGO_E02_OE_HIGH			(~(0))
+#define POGO_E02_OE_VAL_LOW			(1 << 29)
+#define POGO_E02_OE_VAL_HIGH			0
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG			10
+#define MV88E1116_CPRSP_CR3_REG			21
+#define MV88E1116_MAC_CTRL_REG			21
+#define MV88E1116_PGADR_REG			22
+#define MV88E1116_RGMII_TXTM_CTRL		(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL		(1 << 5)
+
+#endif /* __POGO_E02_H */
diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c
index 7af1f41af2..89e6b08e7f 100644
--- a/board/cm_t35/cm_t35.c
+++ b/board/cm_t35/cm_t35.c
@@ -100,17 +100,6 @@ int board_init(void)
 }
 
 /*
- * Routine: misc_init_r
- * Description: display die ID
- */
-int misc_init_r(void)
-{
-	dieid_num_r();
-
-	return 0;
-}
-
-/*
  * Routine: set_muxconf_regs
  * Description: Setting up the configuration Mux registers specific to the
  *		hardware. Many pins need to be moved from protect to primary
@@ -241,6 +230,12 @@ static void cm_t3x_set_common_muxconf(void)
 	/* I2C1 */
 	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)); /*I2C1_SCL*/
 	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)); /*I2C1_SDA*/
+	/* I2C2 */
+	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)); /*I2C2_SCL*/
+	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)); /*I2C2_SDA*/
+	/* I2C3 */
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)); /*I2C3_SCL*/
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)); /*I2C3_SDA*/
 
 	/* control and debug */
 	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)); /*SYS_32K*/
@@ -318,7 +313,7 @@ void set_muxconf_regs(void)
 #ifdef CONFIG_GENERIC_MMC
 int board_mmc_init(bd_t *bis)
 {
-	return omap_mmc_init(0);
+	return omap_mmc_init(0, 0, 0);
 }
 #endif
 
diff --git a/board/comelit/dig297/dig297.c b/board/comelit/dig297/dig297.c
index 65482813d2..c6c10717b7 100644
--- a/board/comelit/dig297/dig297.c
+++ b/board/comelit/dig297/dig297.c
@@ -147,7 +147,7 @@ void set_muxconf_regs(void)
 #ifdef CONFIG_GENERIC_MMC
 int board_mmc_init(bd_t *bis)
 {
-	omap_mmc_init(0);
+	omap_mmc_init(0, 0, 0);
 	return 0;
 }
 #endif
diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c
index 435711a2ab..aaff2e868b 100644
--- a/board/corscience/tricorder/tricorder.c
+++ b/board/corscience/tricorder/tricorder.c
@@ -80,7 +80,7 @@ void set_muxconf_regs(void)
 #if defined(CONFIG_GENERIC_MMC) && !(defined(CONFIG_SPL_BUILD))
 int board_mmc_init(bd_t *bis)
 {
-	return omap_mmc_init(0);
+	return omap_mmc_init(0, 0, 0);
 }
 #endif
 
diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c
index 43632c2fd8..7e000404ee 100644
--- a/board/davinci/ea20/ea20.c
+++ b/board/davinci/ea20/ea20.c
@@ -272,7 +272,7 @@ int board_init(void)
 	return 0;
 }
 
-#ifdef BOARD_LATE_INIT
+#ifdef CONFIG_BOARD_LATE_INIT
 
 int board_late_init(void)
 {
@@ -287,7 +287,7 @@ int board_late_init(void)
 
 	return 0;
 }
-#endif /* BOARD_LATE_INIT */
+#endif /* CONFIG_BOARD_LATE_INIT */
 
 #ifdef CONFIG_DRIVER_TI_EMAC
 
diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c
index 53df4761f6..3d28ea84de 100644
--- a/board/denx/m28evk/m28evk.c
+++ b/board/denx/m28evk/m28evk.c
@@ -90,6 +90,8 @@ int board_mmc_init(bd_t *bis)
 {
 	/* Configure WP as input. */
 	gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10);
+	/* Turn on the power to the card. */
+	gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
 
 	return mxsmmc_initialize(bis, 0, m28_mmc_wp);
 }
@@ -103,10 +105,18 @@ int board_mmc_init(bd_t *bis)
 
 int fecmxc_mii_postcall(int phy)
 {
+#if	defined(CONFIG_DENX_M28_V11) || defined(CONFIG_DENX_M28_V10)
+	/* KZ8031 PHY on old boards. */
+	const uint32_t freq = 0x0080;
+#else
+	/* KZ8021 PHY on new boards. */
+	const uint32_t freq = 0x0000;
+#endif
+
 	miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
 	miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
 	if (phy == 3)
-		miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180);
+		miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8100 | freq);
 	return 0;
 }
 
@@ -123,6 +133,14 @@ int board_eth_init(bd_t *bis)
 		CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
 		CLKCTRL_ENET_TIME_SEL_RMII_CLK);
 
+#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10)
+	/* Reset the new PHY */
+	gpio_direction_output(MX28_PAD_AUART2_RTS__GPIO_3_11, 0);
+	udelay(10000);
+	gpio_set_value(MX28_PAD_AUART2_RTS__GPIO_3_11, 1);
+	udelay(10000);
+#endif
+
 	ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
 	if (ret) {
 		printf("FEC MXS: Unable to init FEC0\n");
diff --git a/board/denx/m28evk/spl_boot.c b/board/denx/m28evk/spl_boot.c
index a04fe180c1..7a125925de 100644
--- a/board/denx/m28evk/spl_boot.c
+++ b/board/denx/m28evk/spl_boot.c
@@ -109,8 +109,9 @@ const iomux_cfg_t iomux_setup[] = {
 		(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
 	MX28_PAD_SSP0_SCK__SSP0_SCK |
 		(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
-	MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0,	/* Power .. FIXME */
-	MX28_PAD_AUART2_CTS__GPIO_3_10,	/* WP ... FIXME */
+	MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0 |
+		(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),	/* Power */
+	MX28_PAD_AUART2_CTS__GPIO_3_10,	/* WP */
 
 	/* GPMI NAND */
 	MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
@@ -147,6 +148,9 @@ const iomux_cfg_t iomux_setup[] = {
 	MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
 	MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
 	MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
+#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10)
+	MX28_PAD_AUART2_RTS__GPIO_3_11,	/* PHY reset */
+#endif
 
 	/* I2C */
 	MX28_PAD_I2C0_SCL__I2C0_SCL,
diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
index 41b5ba0490..fb082457ed 100644
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@@ -697,7 +697,6 @@ U_BOOT_CMD(
  */
 int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	bd_t *bd = gd->bd;
 	char *buf;
 	ulong crc;
 	char str[32];
@@ -730,12 +729,7 @@ int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		/*
 		 * Update whole ip-addr
 		 */
-		bd->bi_ip_addr = ipaddr;
-		sprintf(str, "%ld.%ld.%ld.%ld",
-			(bd->bi_ip_addr & 0xff000000) >> 24,
-			(bd->bi_ip_addr & 0x00ff0000) >> 16,
-			(bd->bi_ip_addr & 0x0000ff00) >> 8,
-			(bd->bi_ip_addr & 0x000000ff));
+		sprintf(str, "%pI4", &ipaddr);
 		setenv("ipaddr", str);
 		printf("Updated ip_addr from bp_eeprom to %s!\n", str);
 	}
diff --git a/board/esd/cpci750/mv_eth.c b/board/esd/cpci750/mv_eth.c
index a3bde81575..9455b62eb0 100644
--- a/board/esd/cpci750/mv_eth.c
+++ b/board/esd/cpci750/mv_eth.c
@@ -95,8 +95,6 @@ int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length);
 #ifndef  UPDATE_STATS_BY_SOFTWARE
 static void mv64360_eth_print_stat (struct eth_device *dev);
 #endif
-/* Processes a received packet */
-extern void NetReceive (volatile uchar *, int);
 
 extern unsigned int INTERNAL_REG_BASE_ADDR;
 
@@ -192,8 +190,7 @@ int db64360_eth_poll (struct eth_device *dev)
 	return mv64360_eth_receive (dev);
 }
 
-int db64360_eth_transmit (struct eth_device *dev, volatile void *packet,
-			  int length)
+int db64360_eth_transmit(struct eth_device *dev, void *packet, int length)
 {
 	mv64360_eth_xmit (dev, packet, length);
 	return 0;
diff --git a/board/esd/cpci750/mv_eth.h b/board/esd/cpci750/mv_eth.h
index b761135349..3d0cb10dd5 100644
--- a/board/esd/cpci750/mv_eth.h
+++ b/board/esd/cpci750/mv_eth.h
@@ -168,9 +168,7 @@ struct mv64360_eth_priv {
 
 int mv64360_eth_init (struct eth_device *dev);
 int mv64360_eth_stop (struct eth_device *dev);
-int mv64360_eth_start_xmit (struct eth_device*, volatile void* packet, int length);
-/*	return db64360_eth0_poll(); */
-
+int mv64360_eth_start_xmit(struct eth_device *dev, void *packet, int length);
 int mv64360_eth_open (struct eth_device *dev);
 
 
diff --git a/board/esg/ima3-mx53/Makefile b/board/esg/ima3-mx53/Makefile
new file mode 100644
index 0000000000..f3b13bccaf
--- /dev/null
+++ b/board/esg/ima3-mx53/Makefile
@@ -0,0 +1,41 @@
+#
+# Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
+#
+# Based on ti/evm/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= ima3-mx53.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/esg/ima3-mx53/ima3-mx53.c b/board/esg/ima3-mx53/ima3-mx53.c
new file mode 100644
index 0000000000..9ecf31d7c2
--- /dev/null
+++ b/board/esg/ima3-mx53/ima3-mx53.c
@@ -0,0 +1,302 @@
+/*
+ * (C) Copyright 2012, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/errno.h>
+#include <netdev.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/gpio.h>
+
+/* NOR flash configuration */
+#define IMA3_MX53_CS0GCR1	(CSEN | DSZ(2))
+#define IMA3_MX53_CS0GCR2	0
+#define IMA3_MX53_CS0RCR1	(RCSN(2) | OEN(1) | RWSC(15))
+#define IMA3_MX53_CS0RCR2	0
+#define IMA3_MX53_CS0WCR1	(WBED1 | WCSN(2) | WEN(1) | WWSC(15))
+#define IMA3_MX53_CS0WCR2	0
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void weim_nor_settings(void)
+{
+	struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
+
+	writel(IMA3_MX53_CS0GCR1, &weim_regs->cs0gcr1);
+	writel(IMA3_MX53_CS0GCR2, &weim_regs->cs0gcr2);
+	writel(IMA3_MX53_CS0RCR1, &weim_regs->cs0rcr1);
+	writel(IMA3_MX53_CS0RCR2, &weim_regs->cs0rcr2);
+	writel(IMA3_MX53_CS0WCR1, &weim_regs->cs0wcr1);
+	writel(IMA3_MX53_CS0WCR2, &weim_regs->cs0wcr2);
+	writel(0x0, &weim_regs->wcr);
+
+	set_chipselect_size(CS0_128);
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
+			PHYS_SDRAM_1_SIZE);
+	return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+	/* UART4 RXD */
+	mxc_request_iomux(MX53_PIN_CSI0_D13, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX53_PIN_CSI0_D13,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+		PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
+		PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	mxc_iomux_set_input(MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
+
+	/* UART4 TXD */
+	mxc_request_iomux(MX53_PIN_CSI0_D12, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX53_PIN_CSI0_D12,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+		PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
+		PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
+}
+
+static void setup_iomux_fec(void)
+{
+	/*FEC_MDIO*/
+	mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
+		PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU |
+		PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
+
+	/*FEC_MDC*/
+	mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
+
+	/* FEC RXD3 */
+	mxc_request_iomux(MX53_PIN_KEY_COL0, IOMUX_CONFIG_ALT6);
+	mxc_iomux_set_pad(MX53_PIN_KEY_COL0, PAD_CTL_HYS_ENABLE |
+		PAD_CTL_PKE_ENABLE);
+
+	/* FEC RXD2 */
+	mxc_request_iomux(MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT6);
+	mxc_iomux_set_pad(MX53_PIN_KEY_COL2, PAD_CTL_HYS_ENABLE |
+		PAD_CTL_PKE_ENABLE);
+
+	/* FEC RXD1 */
+	mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, PAD_CTL_HYS_ENABLE |
+		PAD_CTL_PKE_ENABLE);
+
+	/* FEC RXD0 */
+	mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, PAD_CTL_HYS_ENABLE |
+		PAD_CTL_PKE_ENABLE);
+
+	/* FEC TXD3 */
+	mxc_request_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT6);
+	mxc_iomux_set_pad(MX53_PIN_GPIO_19, PAD_CTL_DRV_HIGH);
+
+	/* FEC TXD2 */
+	mxc_request_iomux(MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT6);
+	mxc_iomux_set_pad(MX53_PIN_KEY_ROW2, PAD_CTL_DRV_HIGH);
+
+	/* FEC TXD1 */
+	mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
+
+	/* FEC TXD0 */
+	mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
+
+	/* FEC TX_EN */
+	mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
+
+	/* FEC TX_CLK */
+	mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, PAD_CTL_HYS_ENABLE |
+		PAD_CTL_PKE_ENABLE);
+
+	/* FEC RX_ER */
+	mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, PAD_CTL_HYS_ENABLE |
+		PAD_CTL_PKE_ENABLE);
+
+	/* FEC RX_DV */
+	mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, PAD_CTL_HYS_ENABLE |
+		PAD_CTL_PKE_ENABLE);
+
+	/* FEC CRS */
+	mxc_request_iomux(MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT6);
+	mxc_iomux_set_pad(MX53_PIN_KEY_COL3, PAD_CTL_HYS_ENABLE |
+		PAD_CTL_PKE_ENABLE);
+
+	/* FEC COL */
+	mxc_request_iomux(MX53_PIN_KEY_ROW1, IOMUX_CONFIG_ALT6);
+	mxc_iomux_set_pad(MX53_PIN_KEY_ROW1, PAD_CTL_HYS_ENABLE |
+		PAD_CTL_PKE_ENABLE);
+	mxc_iomux_set_input(MX53_FEC_FEC_COL_SELECT_INPUT, 0x0);
+
+	/* FEC RX_CLK */
+	mxc_request_iomux(MX53_PIN_KEY_COL1, IOMUX_CONFIG_ALT6);
+	mxc_iomux_set_pad(MX53_PIN_KEY_COL1, PAD_CTL_HYS_ENABLE |
+		PAD_CTL_PKE_ENABLE);
+	mxc_iomux_set_input(MX53_FEC_FEC_RX_CLK_SELECT_INPUT, 0x0);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg = { MMC_SDHC1_BASE_ADDR, 1 };
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	int ret;
+
+	ret = !gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_1));
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX53_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX53_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX53_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX53_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX53_PIN_GPIO_1,
+		PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
+		PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
+		PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PKE_ENABLE);
+	gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_1));
+
+	mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
+	mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
+		PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE |
+		PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH);
+	mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+	mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+	mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+	mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+
+	return fsl_esdhc_initialize(bis, &esdhc_cfg);
+}
+#endif
+
+static void setup_iomux_spi(void)
+{
+	/* SCLK */
+	mxc_request_iomux(MX53_PIN_CSI0_D8, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+	mxc_iomux_set_input(MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT, 0x1);
+	/* MOSI */
+	mxc_request_iomux(MX53_PIN_CSI0_D9, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+	mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT, 0x1);
+	/* MISO */
+	mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT3);
+	mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+	mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT, 0x1);
+	/* SSEL 0 */
+	mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
+		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D11), 1);
+}
+
+int board_early_init_f(void)
+{
+	/* configure I/O pads */
+	setup_iomux_uart();
+	setup_iomux_fec();
+
+	weim_nor_settings();
+
+	/* configure spi */
+	setup_iomux_spi();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	mxc_set_sata_internal_clock();
+
+	return 0;
+}
+
+#if defined(CONFIG_RESET_PHY_R)
+#include <miiphy.h>
+
+void reset_phy(void)
+{
+	unsigned short reg;
+
+	/* reset the phy */
+	miiphy_reset("FEC", CONFIG_PHY_ADDR);
+
+	/* set hard link to 100Mbit, full-duplex */
+	miiphy_read("FEC", CONFIG_PHY_ADDR, MII_BMCR, &reg);
+	reg &= ~BMCR_ANENABLE;
+	reg |= (BMCR_SPEED100 | BMCR_FULLDPLX);
+	miiphy_write("FEC", CONFIG_PHY_ADDR, MII_BMCR, reg);
+
+	miiphy_read("FEC", CONFIG_PHY_ADDR, 0x16, &reg);
+	reg |= (1 << 5);
+	miiphy_write("FEC", CONFIG_PHY_ADDR, 0x16, reg);
+}
+#endif
+
+int checkboard(void)
+{
+	puts("Board: IMA3_MX53\n");
+
+	return 0;
+}
diff --git a/board/esg/ima3-mx53/imximage.cfg b/board/esg/ima3-mx53/imximage.cfg
new file mode 100644
index 0000000000..fa6b42ddcc
--- /dev/null
+++ b/board/esg/ima3-mx53/imximage.cfg
@@ -0,0 +1,108 @@
+#
+# (C) Copyright 2012
+# Stefano Babic DENX Software Engineering sbabic@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not write to the Free Software
+# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.imxmage for more details about how-to configure
+# and create imximage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+# image version
+
+IMAGE_VERSION 2
+
+# Boot Device : one of
+# spi, sd (the board has no nand neither onenand)
+
+BOOT_FROM	nor
+
+# Device Configuration Data (DCD)
+#
+# Each entry must have the format:
+# Addr-type           Address        Value
+#
+# where:
+#	Addr-type register length (1,2 or 4 bytes)
+#	Address	  absolute address of the register
+#	value	  value to be stored in the register
+
+# IOMUX for RAM only
+DATA 4 0x53fa8554 0x300020
+DATA 4 0x53fa8560 0x300020
+DATA 4 0x53fa8594 0x300020
+DATA 4 0x53fa8584 0x300020
+DATA 4 0x53fa8558 0x300040
+DATA 4 0x53fa8568 0x300040
+DATA 4 0x53fa8590 0x300040
+DATA 4 0x53fa857c 0x300040
+DATA 4 0x53fa8564 0x300040
+DATA 4 0x53fa8580 0x300040
+DATA 4 0x53fa8570 0x300220
+DATA 4 0x53fa8578 0x300220
+DATA 4 0x53fa872c 0x300000
+DATA 4 0x53fa8728 0x300000
+DATA 4 0x53fa871c 0x300000
+DATA 4 0x53fa8718 0x300000
+DATA 4 0x53fa8574 0x300020
+DATA 4 0x53fa8588 0x300020
+DATA 4 0x53fa855c 0x0
+DATA 4 0x53fa858c 0x0
+DATA 4 0x53fa856c 0x300040
+DATA 4 0x53fa86f0 0x300000
+DATA 4 0x53fa8720 0x300000
+DATA 4 0x53fa86fc 0x0
+DATA 4 0x53fa86f4 0x0
+DATA 4 0x53fa8714 0x0
+DATA 4 0x53fa8724 0x4000000
+#
+# DDR RAM
+DATA 4 0x63fd9088 0x40404040
+DATA 4 0x63fd9090 0x40404040
+DATA 4 0x63fd907C 0x01420143
+DATA 4 0x63fd9080 0x01450146
+DATA 4 0x63fd9018 0x00111740
+DATA 4 0x63fd9000 0x84190000
+# esdcfgX
+DATA 4 0x63fd900C 0x9f5152e3
+DATA 4 0x63fd9010 0xb68e8a63
+DATA 4 0x63fd9014 0x01ff00db
+# Read/Write command delay
+DATA 4 0x63fd902c 0x000026d2
+# Out of reset delays
+DATA 4 0x63fd9030 0x00ff0e21
+# ESDCTL ODT timing control
+DATA 4 0x63fd9008 0x12273030
+# ESDCTL power down control
+DATA 4 0x63fd9004 0x0002002d
+# Set registers in DDR memory chips
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00028031
+DATA 4 0x63fd901c 0x052080b0
+DATA 4 0x63fd901c 0x04008040
+# ESDCTL refresh control
+DATA 4 0x63fd9020 0x00005800
+# PHY ZQ HW control
+DATA 4 0x63fd9040 0x05380003
+# PHY ODT control
+DATA 4 0x63fd9058 0x00022222
+# start DDR3
+DATA 4 0x63fd901c 0x00000000
diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c
index eb87edcbfe..a3a32761da 100644
--- a/board/evb64260/eth.c
+++ b/board/evb64260/eth.c
@@ -246,8 +246,7 @@ gt6426x_eth_poll(void *v)
 /**************************************************************************
 TRANSMIT - Transmit a frame
 ***************************************************************************/
-int
-gt6426x_eth_transmit(void *v, volatile char *p, unsigned int s)
+int gt6426x_eth_transmit(void *v, char *p, unsigned int s)
 {
 	struct eth_device *wp = (struct eth_device *)v;
 	struct eth_dev_s *dev = (struct eth_dev_s *)wp->priv;
diff --git a/board/evb64260/eth.h b/board/evb64260/eth.h
index beb6db16df..76bd725921 100644
--- a/board/evb64260/eth.h
+++ b/board/evb64260/eth.h
@@ -68,7 +68,7 @@ extern char *eth0_rx_buffer[NR];
 extern char *eth_data;
 
 extern int gt6426x_eth_poll(void *v);
-extern int gt6426x_eth_transmit(void *v, volatile char *p, unsigned int s);
+extern int gt6426x_eth_transmit(void *v, char *p, unsigned int s);
 extern void gt6426x_eth_disable(void *v);
 extern int gt6426x_eth_probe(void *v, bd_t *bis);
 
diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c
index 09ef5615d2..c4566ddd4f 100644
--- a/board/freescale/common/p_corenet/law.c
+++ b/board/freescale/common/p_corenet/law.c
@@ -48,6 +48,19 @@ struct law_entry law_table[] = {
 #ifdef CONFIG_SYS_NAND_BASE_PHYS
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 #endif
+#ifdef CONFIG_SRIOBOOT_SLAVE
+#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0)
+	SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+				LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
+	SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+				LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
+#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1)
+	SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+				LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
+	SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+				LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
+#endif
+#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c
index 6a0026a2cf..da2162728f 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -66,6 +66,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIOBOOT_SLAVE)
+	/*
+	 * SRIOBOOT-SLAVE. When slave boot, the address of the
+	 * space is at 0xfff00000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_SLAVE_ADDR,
+			CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+			0, 0, BOOKE_PAGESZ_1M, 1),
 #else
 	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -138,6 +147,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 16, BOOKE_PAGESZ_1M, 1),
 #endif
+#ifdef CONFIG_SRIOBOOT_SLAVE
+	/*
+	 * SRIOBOOT-SLAVE. 1M space from 0xffe00000 for fetching ucode
+	 * and ENV from master
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR,
+		CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+		0, 17, BOOKE_PAGESZ_1M, 1),
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
index b1eecc495d..a33c936fa0 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -62,10 +62,6 @@ int checkboard (void)
 	else
 		printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
 
-#ifdef CONFIG_PHYS_64BIT
-	puts("36-bit Addressing\n");
-#endif
-
 	/* Display the RCW, so that no one gets confused as to what RCW
 	 * we're actually using for this boot.
 	 */
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index c9f85c857b..6d0bfde232 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -68,12 +68,7 @@ int checkboard (void)
 	u8 vboot;
 	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
-	puts("Board: MPC8536DS ");
-#ifdef CONFIG_PHYS_64BIT
-	puts("(36-bit addrmap) ");
-#endif
-
-	printf ("Sys ID: 0x%02x, "
+	printf("Board: MPC8536DS Sys ID: 0x%02x, "
 		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
 		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
 		in_8(pixis_base + PIXIS_PVER));
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index b20299e36f..33a02ba8d3 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -45,11 +45,7 @@ int checkboard (void)
 	u8 vboot;
 	u8 *pixis_base = (u8 *)PIXIS_BASE;
 
-	puts ("Board: MPC8572DS ");
-#ifdef CONFIG_PHYS_64BIT
-	puts ("(36-bit addrmap) ");
-#endif
-	printf ("Sys ID: 0x%02x, "
+	printf("Board: MPC8572DS Sys ID: 0x%02x, "
 		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
 		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
 		in_8(pixis_base + PIXIS_PVER));
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index 455569e422..6a0a3a2b37 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -50,9 +50,6 @@ int checkboard(void)
 	else
 		puts ("Promjet\n");
 
-#ifdef CONFIG_PHYS_64BIT
-	printf ("       36-bit physical address map\n");
-#endif
 	return 0;
 }
 
diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c
index 396761bdff..6587c454fe 100644
--- a/board/freescale/mx28evk/iomux.c
+++ b/board/freescale/mx28evk/iomux.c
@@ -26,6 +26,7 @@
 #include <asm/arch/sys_proto.h>
 
 #define	MUX_CONFIG_SSP0	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_GPMI	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
 #define	MUX_CONFIG_ENET	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
 #define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
 #define	MUX_CONFIG_SSP2	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
@@ -55,6 +56,26 @@ const iomux_cfg_t iomux_setup[] = {
 	MX28_PAD_PWM3__GPIO_3_28 |
 		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
 
+#ifdef CONFIG_NAND_MXS
+	/* GPMI NAND */
+	MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_RDN__GPMI_RDN |
+		(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+	MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
+#endif
+
 	/* FEC0 */
 	MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
 	MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index d736141e28..dec966ddd6 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -27,6 +27,7 @@
 #include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/clock.h>
 #include <asm/errno.h>
@@ -35,6 +36,9 @@
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <asm/gpio.h>
+#include <pmic.h>
+#include <dialog_pmic.h>
+#include <fsl_pmic.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -58,6 +62,18 @@ void dram_init_banksize(void)
 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 }
 
+u32 get_board_rev(void)
+{
+	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+	struct fuse_bank *bank = &iim->bank[0];
+	struct fuse_bank0_regs *fuse =
+		(struct fuse_bank0_regs *)bank->fuse_regs;
+
+	int rev = readl(&fuse->gp[6]);
+
+	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
+
 static void setup_iomux_uart(void)
 {
 	/* UART1 RXD */
@@ -81,10 +97,9 @@ static void setup_iomux_uart(void)
 #ifdef CONFIG_USB_EHCI_MX5
 int board_ehci_hcd_init(int port)
 {
-	/* request VBUS power enable pin, GPIO[8}, gpio7 */
+	/* request VBUS power enable pin, GPIO7_8 */
 	mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1);
-	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 0);
-	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
+	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
 	return 0;
 }
 #endif
@@ -290,6 +305,103 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+static void setup_iomux_i2c(void)
+{
+	/* I2C1 SDA */
+	mxc_request_iomux(MX53_PIN_CSI0_D8,
+		IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+	mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
+		INPUT_CTL_PATH0);
+	mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
+		PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+		PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
+		PAD_CTL_PUE_PULL |
+		PAD_CTL_ODE_OPENDRAIN_ENABLE);
+	/* I2C1 SCL */
+	mxc_request_iomux(MX53_PIN_CSI0_D9,
+		IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+	mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
+		INPUT_CTL_PATH0);
+	mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
+		PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
+		PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
+		PAD_CTL_PUE_PULL |
+		PAD_CTL_ODE_OPENDRAIN_ENABLE);
+}
+
+static int power_init(void)
+{
+	unsigned int val;
+	int ret = -1;
+	struct pmic *p;
+
+	if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
+		pmic_dialog_init();
+		p = get_pmic();
+
+		/* Set VDDA to 1.25V */
+		val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
+		ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
+
+		ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
+		val |= DA9052_SUPPLY_VBCOREGO;
+		ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val);
+
+		/* Set Vcc peripheral to 1.30V */
+		ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
+		ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
+	}
+
+	if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
+		pmic_init();
+		p = get_pmic();
+
+		/* Set VDDGP to 1.25V for 1GHz on SW1 */
+		pmic_reg_read(p, REG_SW_0, &val);
+		val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
+		ret = pmic_reg_write(p, REG_SW_0, val);
+
+		/* Set VCC as 1.30V on SW2 */
+		pmic_reg_read(p, REG_SW_1, &val);
+		val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
+		ret |= pmic_reg_write(p, REG_SW_1, val);
+
+		/* Set global reset timer to 4s */
+		pmic_reg_read(p, REG_POWER_CTL2, &val);
+		val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
+		ret |= pmic_reg_write(p, REG_POWER_CTL2, val);
+
+		/* Set VUSBSEL and VUSBEN for USB PHY supply*/
+		pmic_reg_read(p, REG_MODE_0, &val);
+		val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
+		ret |= pmic_reg_write(p, REG_MODE_0, val);
+
+		/* Set SWBST to 5V in auto mode */
+		val = SWBST_AUTO;
+		ret |= pmic_reg_write(p, SWBST_CTRL, val);
+	}
+
+	return ret;
+}
+
+static void clock_1GHz(void)
+{
+	int ret;
+	u32 ref_clk = CONFIG_SYS_MX5_HCLK;
+	/*
+	 * After increasing voltage to 1.25V, we can switch
+	 * CPU clock to 1GHz and DDR to 400MHz safely
+	 */
+	ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
+	if (ret)
+		printf("CPU:   Switch CPU clock to 1GHZ failed\n");
+
+	ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
+	ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
+	if (ret)
+		printf("CPU:   Switch DDR clock to 400MHz failed\n");
+}
+
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
@@ -298,10 +410,38 @@ int board_early_init_f(void)
 	return 0;
 }
 
+int print_cpuinfo(void)
+{
+	u32 cpurev;
+
+	cpurev = get_cpu_rev();
+	printf("CPU:   Freescale i.MX%x family rev%d.%d at %d MHz\n",
+		(cpurev & 0xFF000) >> 12,
+		(cpurev & 0x000F0) >> 4,
+		(cpurev & 0x0000F) >> 0,
+		mxc_get_clock(MXC_ARM_CLK) / 1000000);
+	printf("Reset cause: %s\n", get_reset_cause());
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	setup_iomux_i2c();
+	if (!power_init())
+		clock_1GHz();
+	print_cpuinfo();
+
+	return 0;
+}
+#endif
+
 int board_init(void)
 {
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
+	mxc_set_sata_internal_clock();
+
 	return 0;
 }
 
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index fda3e41a03..29cbfed120 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -25,6 +25,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx6x_pins.h>
 #include <asm/arch/iomux-v3.h>
+#include <asm/arch/clock.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <mmc.h>
@@ -50,6 +51,10 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |		\
 	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
 
+#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
 int dram_init(void)
 {
        gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -122,6 +127,22 @@ iomux_v3_cfg_t enet_pads2[] = {
 	MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 };
 
+/* Button assignments for J14 */
+static iomux_v3_cfg_t button_pads[] = {
+	/* Menu */
+	MX6Q_PAD_NANDF_D1__GPIO_2_1	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+	/* Back */
+	MX6Q_PAD_NANDF_D2__GPIO_2_2	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+	/* Labelled Search (mapped to Power under Android) */
+	MX6Q_PAD_NANDF_D3__GPIO_2_3	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+	/* Home */
+	MX6Q_PAD_NANDF_D4__GPIO_2_4	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+	/* Volume Down */
+	MX6Q_PAD_GPIO_19__GPIO_4_5	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+	/* Volume Up */
+	MX6Q_PAD_GPIO_18__GPIO_7_13	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+};
+
 static void setup_iomux_enet(void)
 {
 	gpio_direction_output(87, 0);  /* GPIO 3-23 */
@@ -135,7 +156,7 @@ static void setup_iomux_enet(void)
 
 	/* Need delay 10ms according to KSZ9021 spec */
 	udelay(1000 * 10);
-	gpio_direction_output(87, 1);  /* GPIO 3-23 */
+	gpio_set_value(87, 1);  /* GPIO 3-23 */
 
 	imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
 }
@@ -267,11 +288,44 @@ int board_eth_init(bd_t *bis)
 	return 0;
 }
 
+static void setup_buttons(void)
+{
+	imx_iomux_v3_setup_multiple_pads(button_pads,
+					 ARRAY_SIZE(button_pads));
+}
+
+#ifdef CONFIG_CMD_SATA
+
+int setup_sata(void)
+{
+	struct iomuxc_base_regs *const iomuxc_regs
+		= (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
+	int ret = enable_sata_clock();
+	if (ret)
+		return ret;
+
+	clrsetbits_le32(&iomuxc_regs->gpr[13],
+			IOMUXC_GPR13_SATA_MASK,
+			IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
+			|IOMUXC_GPR13_SATA_PHY_7_SATA2M
+			|IOMUXC_GPR13_SATA_SPEED_3G
+			|(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+			|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
+			|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
+			|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
+			|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+			|IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
+	return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
-       setup_iomux_uart();
+	setup_iomux_uart();
+	setup_buttons();
 
-       return 0;
+	return 0;
 }
 
 int board_init(void)
@@ -283,6 +337,10 @@ int board_init(void)
 	setup_spi();
 #endif
 
+#ifdef CONFIG_CMD_SATA
+	setup_sata();
+#endif
+
        return 0;
 }
 
@@ -292,3 +350,94 @@ int checkboard(void)
 
        return 0;
 }
+
+struct button_key {
+	char const	*name;
+	unsigned	gpnum;
+	char		ident;
+};
+
+static struct button_key const buttons[] = {
+	{"back",	GPIO_NUMBER(2, 2),	'B'},
+	{"home",	GPIO_NUMBER(2, 4),	'H'},
+	{"menu",	GPIO_NUMBER(2, 1),	'M'},
+	{"search",	GPIO_NUMBER(2, 3),	'S'},
+	{"volup",	GPIO_NUMBER(7, 13),	'V'},
+	{"voldown",	GPIO_NUMBER(4, 5),	'v'},
+};
+
+/*
+ * generate a null-terminated string containing the buttons pressed
+ * returns number of keys pressed
+ */
+static int read_keys(char *buf)
+{
+	int i, numpressed = 0;
+	for (i = 0; i < ARRAY_SIZE(buttons); i++) {
+		if (!gpio_get_value(buttons[i].gpnum))
+			buf[numpressed++] = buttons[i].ident;
+	}
+	buf[numpressed] = '\0';
+	return numpressed;
+}
+
+static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	char envvalue[ARRAY_SIZE(buttons)+1];
+	int numpressed = read_keys(envvalue);
+	setenv("keybd", envvalue);
+	return numpressed == 0;
+}
+
+U_BOOT_CMD(
+	kbd, 1, 1, do_kbd,
+	"Tests for keypresses, sets 'keybd' environment variable",
+	"Returns 0 (true) to shell if key is pressed."
+);
+
+#ifdef CONFIG_PREBOOT
+static char const kbd_magic_prefix[] = "key_magic";
+static char const kbd_command_prefix[] = "key_cmd";
+
+static void preboot_keys(void)
+{
+	int numpressed;
+	char keypress[ARRAY_SIZE(buttons)+1];
+	numpressed = read_keys(keypress);
+	if (numpressed) {
+		char *kbd_magic_keys = getenv("magic_keys");
+		char *suffix;
+		/*
+		 * loop over all magic keys
+		 */
+		for (suffix = kbd_magic_keys; *suffix; ++suffix) {
+			char *keys;
+			char magic[sizeof(kbd_magic_prefix) + 1];
+			sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
+			keys = getenv(magic);
+			if (keys) {
+				if (!strcmp(keys, keypress))
+					break;
+			}
+		}
+		if (*suffix) {
+			char cmd_name[sizeof(kbd_command_prefix) + 1];
+			char *cmd;
+			sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
+			cmd = getenv(cmd_name);
+			if (cmd) {
+				setenv("preboot", cmd);
+				return;
+			}
+		}
+	}
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_PREBOOT
+	preboot_keys();
+#endif
+	return 0;
+}
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c
index e5d8423df0..36c8545059 100644
--- a/board/freescale/p1010rdb/ddr.c
+++ b/board/freescale/p1010rdb/ddr.c
@@ -31,7 +31,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CONFIG_DDR_RAW_TIMING
+#ifndef CONFIG_SYS_DDR_RAW_TIMING
 #define CONFIG_SYS_DRAM_SIZE	1024
 
 fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
@@ -165,7 +165,7 @@ phys_size_t fixed_sdram(void)
 	return ddr_size;
 }
 
-#else /* CONFIG_DDR_RAW_TIMING */
+#else /* CONFIG_SYS_DDR_RAW_TIMING */
 /*
  * Samsung K4B2G0846C-HCF8
  * The following timing are for "downshift"
@@ -247,4 +247,4 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	}
 }
 
-#endif /* CONFIG_DDR_RAW_TIMING */
+#endif /* CONFIG_SYS_DDR_RAW_TIMING */
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index b9e66f7fa7..79a6ead7dd 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -165,11 +165,7 @@ int checkboard(void)
 	struct cpu_type *cpu;
 
 	cpu = gd->cpu;
-	printf("Board: %sRDB ", cpu->name);
-#ifdef CONFIG_PHYS_64BIT
-	puts("(36-bit addrmap)");
-#endif
-	puts("\n");
+	printf("Board: %sRDB\n", cpu->name);
 
 	return 0;
 }
diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
index 456d9b0e34..aca30f3680 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -56,12 +56,8 @@ int checkboard(void)
 {
 	u8 sw;
 
-	puts("Board: P1022DS ");
-#ifdef CONFIG_PHYS_64BIT
-	puts("(36-bit addrmap) ");
-#endif
-
-	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+	printf("Board: P1022DS Sys ID: 0x%02x, "
+	       "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
 		in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
 
 	sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c
index 546819cb59..082976a924 100644
--- a/board/freescale/p1023rds/p1023rds.c
+++ b/board/freescale/p1023rds/p1023rds.c
@@ -197,6 +197,12 @@ void ft_board_setup(void *blob, bd_t *bd)
 
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 
+	/* By default NOR is on, and NAND is disabled */
+#ifdef CONFIG_NAND_U_BOOT
+	do_fixup_by_path_string(blob, "nor_flash", "status", "disabled");
+	do_fixup_by_path_string(blob, "nand_flash", "status", "okay");
+#endif
+
 	fdt_fixup_fman_ethernet(blob);
 }
 #endif
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index cfbae69119..437eaf0fdd 100644
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -110,9 +110,7 @@ int checkboard (void)
 
 	cpu = gd->cpu;
 	printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
-#ifdef CONFIG_PHYS_64BIT
-	puts ("(36-bit addrmap) \n");
-#endif
+
 	setbits_be32(&pgpio->gpdir, GPIO_DIR);
 
 /*
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index f0cbde72ab..88ba56f457 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -15,7 +15,7 @@
 #include <asm/io.h>
 #include <asm/fsl_law.h>
 
-#ifdef CONFIG_DDR_RAW_TIMING
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
 #if	defined(CONFIG_P1020RDB_PROTO) || \
 	defined(CONFIG_P1021RDB) || \
 	defined(CONFIG_P1020UTM)
@@ -204,7 +204,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 
 	return 0;
 }
-#endif /* CONFIG_DDR_RAW_TIMING */
+#endif /* CONFIG_SYS_DDR_RAW_TIMING */
 
 /* Fixed sdram init -- doesn't use serial presence detect. */
 phys_size_t fixed_sdram(void)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index a60c5a20a9..aa39260ca7 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -225,13 +225,7 @@ int checkboard(void)
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	u8 in, out, io_config, val;
 
-	printf("Board: %s ", CONFIG_BOARDNAME);
-
-#ifdef CONFIG_PHYS_64BIT
-	puts("(36-bit addrmap) ");
-#endif
-
-	printf("CPLD: V%d.%d PCBA: V%d.0\n",
+	printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
 		in_8(&cpld_data->cpld_rev_major) & 0x0F,
 		in_8(&cpld_data->cpld_rev_minor) & 0x0F,
 		in_8(&cpld_data->pcba_rev) & 0x0F);
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index d3af6cf185..e8d31a4acf 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -61,12 +61,8 @@ int checkboard(void)
 {
 	u8 sw;
 
-	puts("Board: P2020DS ");
-#ifdef CONFIG_PHYS_64BIT
-	puts("(36-bit addrmap) ");
-#endif
-
-	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+	printf("Board: P2020DS Sys ID: 0x%02x, "
+	       "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
 		in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
 
 	sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index 1f6a34b3d9..976c8d290b 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -54,10 +54,6 @@ int checkboard(void)
 	sw = CPLD_READ(fbank_sel);
 	printf("vBank: %d\n", sw & 0x1);
 
-#ifdef CONFIG_PHYS_64BIT
-	puts("36-bit Addressing\n");
-#endif
-
 	/*
 	 * Display the RCW, so that no one gets confused as to what RCW
 	 * we're actually using for this boot.
diff --git a/board/freescale/p3060qds/p3060qds.c b/board/freescale/p3060qds/p3060qds.c
index c6c74f2004..c7cca2a0cc 100644
--- a/board/freescale/p3060qds/p3060qds.c
+++ b/board/freescale/p3060qds/p3060qds.c
@@ -68,9 +68,6 @@ int checkboard(void)
 	else
 		printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
 
-#ifdef CONFIG_PHYS_64BIT
-	puts("36-bit Addressing\n");
-#endif
 	puts("Reset Configuration Word (RCW):");
 	for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
 		u32 rcw = in_be32(&gur->rcwsr[i]);
diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
index 8b80533d98..bc9b7d0a97 100644
--- a/board/gdsys/405ep/405ep.c
+++ b/board/gdsys/405ep/405ep.c
@@ -28,12 +28,9 @@
 #include <asm/ppc4xx-gpio.h>
 #include <asm/global_data.h>
 
+#include "405ep.h"
 #include <gdsys_fpga.h>
 
-#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
-#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
-#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
-
 #define REFLECTION_TESTPATTERN 0xdede
 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
 
@@ -55,7 +52,6 @@ void print_fpga_state(unsigned dev)
 int board_early_init_f(void)
 {
 	unsigned k;
-	unsigned ctr;
 
 	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
 		gd->fpga_state[k] = 0;
@@ -73,26 +69,29 @@ int board_early_init_f(void)
 	 * -> ca. 15 us
 	 */
 	mtebc(EBC0_CFG, 0xa8400000);	/* ebc always driven */
+	return 0;
+}
 
-	/*
-	 * setup io-latches for reset
-	 */
-	out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
-	out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+int board_early_init_r(void)
+{
+	unsigned k;
+	unsigned ctr;
 
-	/*
-	 * set "startup-finished"-gpios
-	 */
-	gpio_write_bit(21, 0);
-	gpio_write_bit(22, 1);
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+		gd->fpga_state[k] = 0;
 
 	/*
-	 * wait for fpga-done
+	 * reset FPGA
 	 */
+	gd405ep_init();
+
+	gd405ep_set_fpga_reset(1);
+
+	gd405ep_setup_hw();
+
 	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
 		ctr = 0;
-		while (!(in_le16((void *)LATCH2_BASE)
-			& CONFIG_SYS_FPGA_DONE(k))) {
+		while (!gd405ep_get_fpga_done(k)) {
 			udelay(100000);
 			if (ctr++ > 5) {
 				gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
@@ -101,15 +100,13 @@ int board_early_init_f(void)
 		}
 	}
 
-	/*
-	 * setup io-latches for boot (stop reset)
-	 */
 	udelay(10);
-	out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
-	out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+
+	gd405ep_set_fpga_reset(0);
 
 	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
-		ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
+		struct ihs_fpga *fpga =
+			(struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k);
 #ifdef CONFIG_SYS_FPGA_NO_RFL_HI
 		u16 *reflection_target = &fpga->reflection_low;
 #else
diff --git a/board/gdsys/405ep/405ep.h b/board/gdsys/405ep/405ep.h
new file mode 100644
index 0000000000..5647dbc62b
--- /dev/null
+++ b/board/gdsys/405ep/405ep.h
@@ -0,0 +1,10 @@
+#ifndef __405EP_H_
+#define __405EP_H_
+
+/* functions to be provided by board implementation */
+void gd405ep_init(void);
+void gd405ep_set_fpga_reset(unsigned state);
+void gd405ep_setup_hw(void);
+int gd405ep_get_fpga_done(unsigned fpga);
+
+#endif /* __405EP_H_ */
diff --git a/board/gdsys/405ep/Makefile b/board/gdsys/405ep/Makefile
index feb5cecf0b..38e5ea4e1d 100644
--- a/board/gdsys/405ep/Makefile
+++ b/board/gdsys/405ep/Makefile
@@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
+COBJS-$(CONFIG_NEO) += neo.o
 COBJS-$(CONFIG_IO) += io.o
 COBJS-$(CONFIG_IOCON) += iocon.o
 COBJS-$(CONFIG_DLVISION_10G) += dlvision-10g.o
diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c
index f55afbd129..644493baaf 100644
--- a/board/gdsys/405ep/dlvision-10g.c
+++ b/board/gdsys/405ep/dlvision-10g.c
@@ -26,16 +26,20 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/ppc4xx-gpio.h>
+#include <dtt.h>
 
+#include "405ep.h"
 #include <gdsys_fpga.h>
 
 #include "../common/osd.h"
 
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
-#define LATCH2_MC2_PRESENT_N 0x0080
-
 #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
 
+#define LATCH2_MC2_PRESENT_N 0x0080
+
 enum {
 	UNITTYPE_VIDEO_USER = 0,
 	UNITTYPE_MAIN_USER = 1,
@@ -46,6 +50,8 @@ enum {
 enum {
 	HWVER_101 = 0,
 	HWVER_110 = 1,
+	HWVER_120 = 2,
+	HWVER_130 = 3,
 };
 
 enum {
@@ -65,6 +71,14 @@ enum {
 	RAM_DDR2_64 = 2,
 };
 
+int misc_init_r(void)
+{
+	/* startup fans */
+	dtt_init();
+
+	return 0;
+}
+
 static unsigned int get_hwver(void)
 {
 	u16 latch3 = in_le16((void *)LATCH3_BASE);
@@ -81,7 +95,7 @@ static unsigned int get_mc2_present(void)
 
 static void print_fpga_info(unsigned dev)
 {
-	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
+	struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev);
 	u16 versions = in_le16(&fpga->versions);
 	u16 fpga_version = in_le16(&fpga->fpga_version);
 	u16 fpga_features = in_le16(&fpga->fpga_features);
@@ -146,7 +160,15 @@ static void print_fpga_info(unsigned dev)
 		break;
 
 	case HWVER_110:
-		printf(" HW-Ver 1.10\n");
+		printf(" HW-Ver 1.10-1.12\n");
+		break;
+
+	case HWVER_120:
+		printf(" HW-Ver 1.20\n");
+		break;
+
+	case HWVER_130:
+		printf(" HW-Ver 1.30\n");
 		break;
 
 	default:
@@ -223,32 +245,31 @@ static void print_fpga_info(unsigned dev)
  */
 int checkboard(void)
 {
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
+	char *s = getenv("serial#");
 
-	printf("Board: ");
+	puts("Board: ");
 
-	printf("DLVision 10G");
+	puts("DLVision 10G");
 
-	if (i > 0) {
+	if (s != NULL) {
 		puts(", serial# ");
-		puts(buf);
+		puts(s);
 	}
 
 	puts("\n");
 
-	print_fpga_info(0);
-	if (get_mc2_present())
-		print_fpga_info(1);
-
 	return 0;
 }
 
 int last_stage_init(void)
 {
-	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
+	struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
 	u16 versions = in_le16(&fpga->versions);
 
+	print_fpga_info(0);
+	if (get_mc2_present())
+		print_fpga_info(1);
+
 	if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER)
 		return 0;
 
@@ -261,3 +282,32 @@ int last_stage_init(void)
 
 	return 0;
 }
+
+void gd405ep_init(void)
+{
+}
+
+void gd405ep_set_fpga_reset(unsigned state)
+{
+	if (state) {
+		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+	} else {
+		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+	}
+}
+
+void gd405ep_setup_hw(void)
+{
+	/*
+	 * set "startup-finished"-gpios
+	 */
+	gpio_write_bit(21, 0);
+	gpio_write_bit(22, 1);
+}
+
+int gd405ep_get_fpga_done(unsigned fpga)
+{
+	return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
+}
diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c
index db1ea7f0c5..070dcbbdfc 100644
--- a/board/gdsys/405ep/io.c
+++ b/board/gdsys/405ep/io.c
@@ -27,10 +27,16 @@
 #include <asm/io.h>
 #include <asm/ppc4xx-gpio.h>
 
+#include <dtt.h>
 #include <miiphy.h>
 
+#include "405ep.h"
 #include <gdsys_fpga.h>
 
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+
 #define PHYREG_CONTROL				0
 #define PHYREG_PAGE_ADDRESS			22
 #define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1	16
@@ -47,6 +53,14 @@ enum {
 	HWVER_122 = 3,
 };
 
+int misc_init_r(void)
+{
+	/* startup fans */
+	dtt_init();
+
+	return 0;
+}
+
 int configure_gbit_phy(unsigned char addr)
 {
 	unsigned short value;
@@ -87,9 +101,23 @@ err_out:
  */
 int checkboard(void)
 {
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
+	char *s = getenv("serial#");
+
+	puts("Board: CATCenter Io");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+
+	puts("\n");
+
+	return 0;
+}
+
+static void print_fpga_info(void)
+{
+	struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
 	u16 versions = in_le16(&fpga->versions);
 	u16 fpga_version = in_le16(&fpga->fpga_version);
 	u16 fpga_features = in_le16(&fpga->fpga_features);
@@ -103,15 +131,7 @@ int checkboard(void)
 	feature_channels = fpga_features & 0x007f;
 	feature_expansion = fpga_features & (1<<15);
 
-	printf("Board: ");
-
-	printf("CATCenter Io");
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	puts("\n       ");
+	puts("FPGA:  ");
 
 	switch (unit_type) {
 	case UNITTYPE_CCD_SWITCH:
@@ -152,8 +172,6 @@ int checkboard(void)
 	printf(" %d channel(s)", feature_channels);
 
 	printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
-
-	return 0;
 }
 
 /*
@@ -161,9 +179,11 @@ int checkboard(void)
  */
 int last_stage_init(void)
 {
-	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
+	struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
 	unsigned int k;
 
+	print_fpga_info();
+
 	miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
 		bb_miiphy_read, bb_miiphy_write);
 
@@ -175,3 +195,32 @@ int last_stage_init(void)
 
 	return 0;
 }
+
+void gd405ep_init(void)
+{
+}
+
+void gd405ep_set_fpga_reset(unsigned state)
+{
+	if (state) {
+		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+	} else {
+		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+	}
+}
+
+void gd405ep_setup_hw(void)
+{
+	/*
+	 * set "startup-finished"-gpios
+	 */
+	gpio_write_bit(21, 0);
+	gpio_write_bit(22, 1);
+}
+
+int gd405ep_get_fpga_done(unsigned fpga)
+{
+	return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
+}
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index ce53340894..0fc7db2012 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -27,10 +27,15 @@
 #include <asm/io.h>
 #include <asm/ppc4xx-gpio.h>
 
+#include "405ep.h"
 #include <gdsys_fpga.h>
 
 #include "../common/osd.h"
 
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+
 enum {
 	UNITTYPE_MAIN_SERVER = 0,
 	UNITTYPE_MAIN_USER = 1,
@@ -69,9 +74,25 @@ enum {
  */
 int checkboard(void)
 {
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
+	char *s = getenv("serial#");
+
+	puts("Board: ");
+
+	puts("IoCon");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+
+	puts("\n");
+
+	return 0;
+}
+
+static void print_fpga_info(void)
+{
+	struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
 	u16 versions = in_le16(&fpga->versions);
 	u16 fpga_version = in_le16(&fpga->fpga_version);
 	u16 fpga_features = in_le16(&fpga->fpga_features);
@@ -95,16 +116,6 @@ int checkboard(void)
 	feature_carriers = (fpga_features & 0x000c) >> 2;
 	feature_video_channels = fpga_features & 0x0003;
 
-	printf("Board: ");
-
-	printf("IoCon");
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	puts("\n       ");
-
 	switch (unit_type) {
 	case UNITTYPE_MAIN_USER:
 		printf("Mainchannel");
@@ -205,12 +216,12 @@ int checkboard(void)
 	printf(", %d carrier(s)", feature_carriers);
 
 	printf(", %d video channel(s)\n", feature_video_channels);
-
-	return 0;
 }
 
 int last_stage_init(void)
 {
+	print_fpga_info();
+
 	return osd_probe(0);
 }
 
@@ -231,3 +242,32 @@ int fpga_gpio_get(int pin)
 {
 	return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin;
 }
+
+void gd405ep_init(void)
+{
+}
+
+void gd405ep_set_fpga_reset(unsigned state)
+{
+	if (state) {
+		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+	} else {
+		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+	}
+}
+
+void gd405ep_setup_hw(void)
+{
+	/*
+	 * set "startup-finished"-gpios
+	 */
+	gpio_write_bit(21, 0);
+	gpio_write_bit(22, 1);
+}
+
+int gd405ep_get_fpga_done(unsigned fpga)
+{
+	return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
+}
diff --git a/board/gdsys/405ep/neo.c b/board/gdsys/405ep/neo.c
new file mode 100644
index 0000000000..d336e55c5d
--- /dev/null
+++ b/board/gdsys/405ep/neo.c
@@ -0,0 +1,161 @@
+/*
+ * (C) Copyright 2011
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+#include <dtt.h>
+
+#include "405ep.h"
+#include <gdsys_fpga.h>
+
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+
+enum {
+	UNITTYPE_CCX16 = 1,
+	UNITTYPE_CCIP216 = 2,
+};
+
+enum {
+	HWVER_300 = 3,
+};
+
+int misc_init_r(void)
+{
+	/* startup fans */
+	dtt_init();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	puts("Board: CATCenter Neo");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+
+	puts("\n");
+
+	return 0;
+}
+
+static void print_fpga_info(void)
+{
+	struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
+	u16 versions = in_le16(&fpga->versions);
+	u16 fpga_version = in_le16(&fpga->fpga_version);
+	u16 fpga_features = in_le16(&fpga->fpga_features);
+	int fpga_state = get_fpga_state(0);
+	unsigned unit_type;
+	unsigned hardware_version;
+	unsigned feature_channels;
+
+	puts("FPGA:  ");
+	if (fpga_state & FPGA_STATE_DONE_FAILED) {
+		printf(" done timed out\n");
+		return;
+	}
+
+	if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
+		printf(" refelectione test failed\n");
+		return;
+	}
+
+	unit_type = (versions & 0xf000) >> 12;
+	hardware_version = versions & 0x000f;
+	feature_channels = fpga_features & 0x007f;
+
+	switch (unit_type) {
+	case UNITTYPE_CCX16:
+		printf("CCX-Switch");
+		break;
+
+	default:
+		printf("UnitType %d(not supported)", unit_type);
+		break;
+	}
+
+	switch (hardware_version) {
+	case HWVER_300:
+		printf(" HW-Ver 3.00-3.12\n");
+		break;
+
+	default:
+		printf(" HW-Ver %d(not supported)\n",
+		       hardware_version);
+		break;
+	}
+
+	printf("       FPGA V %d.%02d, features:",
+		fpga_version / 100, fpga_version % 100);
+
+	printf(" %d channel(s)\n", feature_channels);
+}
+
+int last_stage_init(void)
+{
+	print_fpga_info();
+
+	return 0;
+}
+
+void gd405ep_init(void)
+{
+}
+
+void gd405ep_set_fpga_reset(unsigned state)
+{
+	if (state) {
+		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+	} else {
+		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+	}
+}
+
+void gd405ep_setup_hw(void)
+{
+	/*
+	 * set "startup-finished"-gpios
+	 */
+	gpio_write_bit(21, 0);
+	gpio_write_bit(22, 1);
+}
+
+int gd405ep_get_fpga_done(unsigned fpga)
+{
+	/*
+	 * Neo hardware has no FPGA-DONE GPIO
+	 */
+	return 1;
+}
diff --git a/board/gdsys/405ex/405ex.c b/board/gdsys/405ex/405ex.c
index 0d25214f42..5766c0f562 100644
--- a/board/gdsys/405ex/405ex.c
+++ b/board/gdsys/405ex/405ex.c
@@ -219,7 +219,8 @@ int board_early_init_r(void)
 	gd405ex_set_fpga_reset(0);
 
 	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
-		ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
+		struct ihs_fpga *fpga =
+			(struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k);
 #ifdef CONFIG_SYS_FPGA_NO_RFL_HI
 		u16 *reflection_target = &fpga->reflection_low;
 #else
diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c
index 177141dcc3..41fdef7da8 100644
--- a/board/gdsys/405ex/io64.c
+++ b/board/gdsys/405ex/io64.c
@@ -100,7 +100,7 @@ int misc_init_r(void)
 
 static void print_fpga_info(unsigned dev)
 {
-	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
+	struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev);
 	u16 versions = in_le16(&fpga->versions);
 	u16 fpga_version = in_le16(&fpga->fpga_version);
 	u16 fpga_features = in_le16(&fpga->fpga_features);
@@ -242,8 +242,8 @@ int last_stage_init(void)
 {
 	unsigned int k;
 	unsigned int fpga;
-	ihs_fpga_t *fpga0 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
-	ihs_fpga_t *fpga1 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(1);
+	struct ihs_fpga *fpga0 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
+	struct ihs_fpga *fpga1 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(1);
 	int failed = 0;
 	char str_phys[] = "Setup PHYs -";
 	char str_serdes[] = "Start SERDES blocks";
diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index 5065f9d5e4..a192c9851b 100644
--- a/board/gdsys/common/osd.c
+++ b/board/gdsys/common/osd.c
@@ -70,8 +70,8 @@ enum {
 #if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
 static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
 {
-	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
-	ihs_i2c_t *i2c = &fpga->i2c;
+	struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
+	struct ihs_i2c *i2c = &fpga->i2c;
 
 	while (in_le16(&fpga->extended_interrupt) & (1 << 12))
 		;
@@ -81,8 +81,8 @@ static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
 
 static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg)
 {
-	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
-	ihs_i2c_t *i2c = &fpga->i2c;
+	struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
+	struct ihs_i2c *i2c = &fpga->i2c;
 	unsigned int ctr = 0;
 
 	while (in_le16(&fpga->extended_interrupt) & (1 << 12))
@@ -129,7 +129,7 @@ static void mpc92469ac_calc_parameters(unsigned int fout,
 
 static void mpc92469ac_set(unsigned screen, unsigned int fout)
 {
-	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
+	struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
 	unsigned int n;
 	unsigned int m;
 	unsigned int bitval = 0;
@@ -265,8 +265,8 @@ static void ics8n3qv01_set(unsigned screen, unsigned int fout)
 static int osd_write_videomem(unsigned screen, unsigned offset,
 	u16 *data, size_t charcount)
 {
-	ihs_fpga_t *fpga =
-		(ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
+	struct ihs_fpga *fpga =
+		(struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(screen);
 	unsigned int k;
 
 	for (k = 0; k < charcount; ++k) {
@@ -318,8 +318,8 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 int osd_probe(unsigned screen)
 {
-	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
-	ihs_osd_t *osd = &fpga->osd;
+	struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
+	struct ihs_osd *osd = &fpga->osd;
 	u16 version = in_le16(&osd->version);
 	u16 features = in_le16(&osd->features);
 	unsigned width;
diff --git a/board/gdsys/neo/neo.c b/board/gdsys/neo/neo.c
deleted file mode 100644
index d21d599fa7..0000000000
--- a/board/gdsys/neo/neo.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-#define HWTYPE_CCX16	1
-#define HWREV_300	3
-
-int board_early_init_f(void)
-{
-	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
-	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical */
-	mtdcr(UIC0PR, 0xFFFFFF80);	/* set int polarities */
-	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
-	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest prio */
-	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-
-	/*
-	 * EBC Configuration Register: set ready timeout to 512 ebc-clks
-	 * -> ca. 15 us
-	 */
-	mtebc(EBC0_CFG, 0xa8400000);	/* ebc always driven */
-
-	return 0;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-	u16 val = in_le16((void *)CONFIG_FPGA_BASE + 2);
-	u8 unit_type;
-	u8 hardware_cpu_ports;
-	u8 hardware_con_ports;
-	u8 hardware_version;
-
-	printf("Board: CATCenter Neo");
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	puts("\n       ");
-
-	unit_type = (val & 0xf000) >> 12;
-	hardware_cpu_ports = ((val & 0x0f00) >> 8) * 8;
-	hardware_con_ports = ((val & 0x00f0) >> 4) * 2;
-	hardware_version = val & 0x000f;
-
-	switch (unit_type) {
-	case HWTYPE_CCX16:
-		printf("CCX16-FPGA (80 UARTs)");
-		break;
-
-	default:
-		printf("UnitType %d, unsupported", unit_type);
-		break;
-	}
-
-	printf(", %d cpu ports, %d console ports,",
-	       hardware_cpu_ports, hardware_con_ports);
-
-	switch (hardware_version) {
-	case HWREV_300:
-		printf(" HW-Ver 3.00\n");
-		break;
-
-	default:
-		printf(" HW-Ver %d, unsupported\n",
-		       hardware_version);
-		break;
-	}
-
-	return 0;
-}
diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c
index e593b43d48..8f75af19d4 100644
--- a/board/htkw/mcx/mcx.c
+++ b/board/htkw/mcx/mcx.c
@@ -69,17 +69,6 @@ int board_init(void)
 }
 
 /*
- * Routine: misc_init_r
- * Description: late init.
- */
-int misc_init_r(void)
-{
-	dieid_num_r();
-
-	return 0;
-}
-
-/*
  * Routine: set_muxconf_regs
  * Description: Setting up the configuration Mux registers specific to the
  *		hardware. Many pins need to be moved from protect to primary
@@ -93,7 +82,7 @@ void set_muxconf_regs(void)
 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
-	return omap_mmc_init(0);
+	return omap_mmc_init(0, 0, 0);
 }
 #endif
 
diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c
index 6a3777eb8c..971e31b5f3 100644
--- a/board/isee/igep0020/igep0020.c
+++ b/board/isee/igep0020/igep0020.c
@@ -52,8 +52,6 @@ static const u32 gpmc_lan_config[] = {
 int board_init(void)
 {
 	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
-	/* board id for Linux */
-	gd->bd->bi_arch_number = MACH_TYPE_IGEP0020;
 	/* boot param addr */
 	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
 
@@ -96,7 +94,7 @@ static void setup_net_chip(void)
 #ifdef CONFIG_GENERIC_MMC
 int board_mmc_init(bd_t *bis)
 {
-	omap_mmc_init(0);
+	omap_mmc_init(0, 0, 0);
 	return 0;
 }
 #endif
diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c
index 6a927350b4..653c1b5abb 100644
--- a/board/isee/igep0030/igep0030.c
+++ b/board/isee/igep0030/igep0030.c
@@ -39,8 +39,6 @@ DECLARE_GLOBAL_DATA_PTR;
 int board_init(void)
 {
 	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
-	/* board id for Linux */
-	gd->bd->bi_arch_number = MACH_TYPE_IGEP0030;
 	/* boot param addr */
 	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
 
@@ -50,7 +48,7 @@ int board_init(void)
 #ifdef CONFIG_GENERIC_MMC
 int board_mmc_init(bd_t *bis)
 {
-	omap_mmc_init(0);
+	omap_mmc_init(0, 0, 0);
 	return 0;
 }
 #endif
diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c
index 0a105bf281..d316f33cd1 100644
--- a/board/logicpd/am3517evm/am3517evm.c
+++ b/board/logicpd/am3517evm/am3517evm.c
@@ -79,7 +79,7 @@ void set_muxconf_regs(void)
 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
-       omap_mmc_init(0);
+       omap_mmc_init(0, 0, 0);
        return 0;
 }
 #endif
diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
index bc7ec68f14..12bcfcb877 100644
--- a/board/logicpd/omap3som/omap3logic.c
+++ b/board/logicpd/omap3som/omap3logic.c
@@ -140,21 +140,10 @@ int board_init(void)
 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
-	return omap_mmc_init(0);
+	return omap_mmc_init(0, 0, 0);
 }
 #endif
 
-/*
- * Routine: misc_init_r
- * Description: display die ID register
- */
-int misc_init_r(void)
-{
-	dieid_num_r();
-
-	return 0;
-}
-
 #ifdef CONFIG_SMC911X
 /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
 static const u32 gpmc_lan92xx_config[] = {
diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c
index dec0b2611f..90b6b0fde5 100644
--- a/board/logicpd/zoom1/zoom1.c
+++ b/board/logicpd/zoom1/zoom1.c
@@ -92,7 +92,7 @@ void set_muxconf_regs(void)
 #ifdef CONFIG_GENERIC_MMC
 int board_mmc_init(bd_t *bis)
 {
-	omap_mmc_init(0);
+	omap_mmc_init(0, 0, 0);
 	return 0;
 }
 #endif
diff --git a/board/logicpd/zoom2/zoom2.c b/board/logicpd/zoom2/zoom2.c
index be3083d9c3..8e18019801 100644
--- a/board/logicpd/zoom2/zoom2.c
+++ b/board/logicpd/zoom2/zoom2.c
@@ -183,7 +183,7 @@ void set_muxconf_regs (void)
 #ifdef CONFIG_GENERIC_MMC
 int board_mmc_init(bd_t *bis)
 {
-	omap_mmc_init(0);
+	omap_mmc_init(0, 0, 0);
 	return 0;
 }
 #endif
diff --git a/board/matrix_vision/mvblx/mvblx.c b/board/matrix_vision/mvblx/mvblx.c
index 74b5b19be2..f68f312215 100644
--- a/board/matrix_vision/mvblx/mvblx.c
+++ b/board/matrix_vision/mvblx/mvblx.c
@@ -106,8 +106,8 @@ void set_muxconf_regs(void)
 #ifdef CONFIG_GENERIC_MMC
 int board_mmc_init(bd_t *bis)
 {
-	omap_mmc_init(0);
-	omap_mmc_init(1);
+	omap_mmc_init(0, 0, 0);
+	omap_mmc_init(1, 0, 0);
 	return 0;
 }
 #endif
diff --git a/board/nvidia/common/Makefile b/board/nvidia/common/Makefile
index 3e748fdd20..a93d4583e7 100644
--- a/board/nvidia/common/Makefile
+++ b/board/nvidia/common/Makefile
@@ -27,6 +27,7 @@ LIB	= $(obj)lib$(VENDOR).o
 
 COBJS-y += board.o
 COBJS-$(CONFIG_SPI_UART_SWITCH) += uart-spi-switch.o
+COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 85dd359ec9..2e22133591 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -23,6 +23,7 @@
 
 #include <common.h>
 #include <ns16550.h>
+#include <linux/compiler.h>
 #include <asm/io.h>
 #include <asm/arch/tegra2.h>
 #include <asm/arch/sys_proto.h>
@@ -30,12 +31,17 @@
 #include <asm/arch/board.h>
 #include <asm/arch/clk_rst.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/emc.h>
 #include <asm/arch/pinmux.h>
+#include <asm/arch/pmc.h>
+#include <asm/arch/pmu.h>
 #include <asm/arch/uart.h>
+#include <asm/arch/warmboot.h>
 #include <spi.h>
 #include <asm/arch/usb.h>
 #include <i2c.h>
 #include "board.h"
+#include "emc.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -59,11 +65,28 @@ void __pin_mux_usb(void)
 void pin_mux_usb(void) __attribute__((weak, alias("__pin_mux_usb")));
 
 /*
+ * Routine: power_det_init
+ * Description: turn off power detects
+ */
+static void power_det_init(void)
+{
+#if defined(CONFIG_TEGRA2)
+	struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
+
+	/* turn off power detects */
+	writel(0, &pmc->pmc_pwr_det_latch);
+	writel(0, &pmc->pmc_pwr_det);
+#endif
+}
+
+/*
  * Routine: board_init
  * Description: Early hardware init.
  */
 int board_init(void)
 {
+	__maybe_unused int err;
+
 	/* Do clocks and UART first so that printf() works */
 	clock_init();
 	clock_verify();
@@ -76,18 +99,35 @@ int board_init(void)
 #endif
 	/* boot param addr */
 	gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
+
+	power_det_init();
+
 #ifdef CONFIG_TEGRA_I2C
 #ifndef CONFIG_SYS_I2C_INIT_BOARD
 #error "You must define CONFIG_SYS_I2C_INIT_BOARD to use i2c on Nvidia boards"
 #endif
 	i2c_init_board();
-#endif
+# ifdef CONFIG_TEGRA_PMU
+	if (pmu_set_nominal())
+		debug("Failed to select nominal voltages\n");
+#  ifdef CONFIG_TEGRA_CLOCK_SCALING
+	err = board_emc_init();
+	if (err)
+		debug("Memory controller init failed: %d\n", err);
+#  endif
+# endif /* CONFIG_TEGRA_PMU */
+#endif /* CONFIG_TEGRA_I2C */
 
 #ifdef CONFIG_USB_EHCI_TEGRA
 	pin_mux_usb();
 	board_usb_init(gd->fdt_blob);
 #endif
 
+#ifdef CONFIG_TEGRA2_LP0
+	/* prepare the WB code to LP0 location */
+	warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
+#endif
+
 	return 0;
 }
 
diff --git a/board/nvidia/common/emc.c b/board/nvidia/common/emc.c
new file mode 100644
index 0000000000..8e4290ceed
--- /dev/null
+++ b/board/nvidia/common/emc.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ap20.h>
+#include <asm/arch/clk_rst.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/emc.h>
+#include <asm/arch/pmu.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/tegra2.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* These rates are hard-coded for now, until fdt provides them */
+#define EMC_SDRAM_RATE_T20	(333000 * 2 * 1000)
+#define EMC_SDRAM_RATE_T25	(380000 * 2 * 1000)
+
+int board_emc_init(void)
+{
+	unsigned rate;
+
+	switch (tegra_get_chip_type()) {
+	default:
+	case TEGRA_SOC_T20:
+		rate  = EMC_SDRAM_RATE_T20;
+		break;
+	case TEGRA_SOC_T25:
+		rate  = EMC_SDRAM_RATE_T25;
+		break;
+	}
+	return tegra_set_emc(gd->fdt_blob, rate);
+}
diff --git a/board/nvidia/common/emc.h b/board/nvidia/common/emc.h
new file mode 100644
index 0000000000..ec1b115f45
--- /dev/null
+++ b/board/nvidia/common/emc.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _NVIDIA_EMC_H_
+#define _NVIDIA_EMC_H_
+
+int board_emc_init(void);
+
+#endif
diff --git a/board/nvidia/dts/tegra2-seaboard.dts b/board/nvidia/dts/tegra2-seaboard.dts
index 6ba3ec48f1..335253953b 100644
--- a/board/nvidia/dts/tegra2-seaboard.dts
+++ b/board/nvidia/dts/tegra2-seaboard.dts
@@ -89,4 +89,68 @@
 	i2c@7000c500 {
 		clock-frequency = <100000>;
 	};
+
+	emc@7000f400 {
+		emc-table@190000 {
+			reg = < 190000 >;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = < 190000 >;
+			nvidia,emc-registers = < 0x0000000c 0x00000026
+				0x00000009 0x00000003 0x00000004 0x00000004
+				0x00000002 0x0000000c 0x00000003 0x00000003
+				0x00000002 0x00000001 0x00000004 0x00000005
+				0x00000004 0x00000009 0x0000000d 0x0000059f
+				0x00000000 0x00000003 0x00000003 0x00000003
+				0x00000003 0x00000001 0x0000000b 0x000000c8
+				0x00000003 0x00000007 0x00000004 0x0000000f
+				0x00000002 0x00000000 0x00000000 0x00000002
+				0x00000000 0x00000000 0x00000083 0xa06204ae
+				0x007dc010 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 >;
+		};
+		emc-table@380000 {
+			reg = < 380000 >;
+			compatible = "nvidia,tegra20-emc-table";
+			clock-frequency = < 380000 >;
+			nvidia,emc-registers = < 0x00000017 0x0000004b
+				0x00000012 0x00000006 0x00000004 0x00000005
+				0x00000003 0x0000000c 0x00000006 0x00000006
+				0x00000003 0x00000001 0x00000004 0x00000005
+				0x00000004 0x00000009 0x0000000d 0x00000b5f
+				0x00000000 0x00000003 0x00000003 0x00000006
+				0x00000006 0x00000001 0x00000011 0x000000c8
+				0x00000003 0x0000000e 0x00000007 0x0000000f
+				0x00000002 0x00000000 0x00000000 0x00000002
+				0x00000000 0x00000000 0x00000083 0xe044048b
+				0x007d8010 0x00000000 0x00000000 0x00000000
+				0x00000000 0x00000000 0x00000000 0x00000000 >;
+		};
+	};
+
+	kbc@7000e200 {
+		linux,keymap = <0x00020011 0x0003001f 0x0004001e 0x0005002c
+			0x000701d0 0x0107007d 0x02060064 0x02070038 0x03000006
+			0x03010005 0x03020013 0x03030012 0x03040021 0x03050020
+			0x0306002d 0x04000008 0x04010007 0x04020014 0x04030023
+			0x04040022 0x0405002f 0x0406002e 0x04070039 0x0500000a
+			0x05010009 0x05020016 0x05030015 0x05040024 0x05050031
+			0x05060030 0x0507002b 0x0600000c 0x0601000b 0x06020018
+			0x06030017 0x06040026 0x06050025 0x06060033 0x06070032
+			0x0701000d 0x0702001b 0x0703001c 0x0707008b 0x08040036
+			0x0805002a 0x09050061 0x0907001d 0x0b00001a 0x0b010019
+			0x0b020028 0x0b030027 0x0b040035 0x0b050034 0x0c000044
+			0x0c010043 0x0c02000e 0x0c030004 0x0c040003 0x0c050067
+			0x0c0600d2 0x0c070077 0x0d00006e 0x0d01006f 0x0d030068
+			0x0d04006d 0x0d05006a 0x0d06006c 0x0d070069 0x0e000057
+			0x0e010058 0x0e020042 0x0e030010 0x0e04003e 0x0e05003d
+			0x0e060002 0x0e070041 0x0f000001 0x0f010029 0x0f02003f
+			0x0f03000f 0x0f04003b 0x0f05003c 0x0f06003a 0x0f070040
+			0x14000047 0x15000049 0x15010048 0x1502004b 0x1504004f
+			0x16010062 0x1602004d 0x1603004c 0x16040051 0x16050050
+			0x16070052 0x1b010037 0x1b03004a 0x1b04004e 0x1b050053
+			0x1c050073 0x1d030066 0x1d04006b 0x1d0500e0 0x1d060072
+			0x1d0700e1 0x1e000045 0x1e010046 0x1e020071
+			0x1f04008a>;
+		linux,fn-keymap = <0x05040002>;
+	};
 };
diff --git a/board/overo/overo.c b/board/overo/overo.c
index 7b4064cdb1..f973870830 100644
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -403,7 +403,7 @@ int board_eth_init(bd_t *bis)
 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
-	omap_mmc_init(0);
+	omap_mmc_init(0, 0, 0);
 	return 0;
 }
 #endif
diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c
index 58a676d455..3a62e9d633 100644
--- a/board/pandora/pandora.c
+++ b/board/pandora/pandora.c
@@ -32,6 +32,7 @@
 #include <common.h>
 #include <twl4030.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/gpio.h>
@@ -45,6 +46,10 @@ DECLARE_GLOBAL_DATA_PTR;
 #define TWL4030_BB_CFG_BBSEL_3200MV	(3 << 2)
 #define TWL4030_BB_CFG_BBISEL_500UA	2
 
+#define CONTROL_WKUP_CTRL		0x48002a5c
+#define GPIO_IO_PWRDNZ			(1 << 6)
+#define PBIASLITEVMODE1			(1 << 8)
+
 /*
  * Routine: board_init
  * Description: Early hardware init.
@@ -60,29 +65,52 @@ int board_init(void)
 	return 0;
 }
 
+static void set_output_gpio(unsigned int gpio, int value)
+{
+	int ret;
+
+	ret = gpio_request(gpio, "");
+	if (ret != 0) {
+		printf("could not request GPIO %u\n", gpio);
+		return;
+	}
+	ret = gpio_direction_output(gpio, value);
+	if (ret != 0)
+		printf("could not set GPIO %u to %d\n", gpio, value);
+}
+
 /*
  * Routine: misc_init_r
  * Description: Configure board specific parts
  */
 int misc_init_r(void)
 {
-	struct gpio *gpio1_base = (struct gpio *)OMAP34XX_GPIO1_BASE;
-	struct gpio *gpio4_base = (struct gpio *)OMAP34XX_GPIO4_BASE;
-	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
-	struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
+	t2_t *t2_base = (t2_t *)T2_BASE;
+	u32 pbias_lite;
 
 	twl4030_led_init(TWL4030_LED_LEDEN_LEDBON);
 
-	/* Configure GPIOs to output */
-	writel(~(GPIO14 | GPIO15 | GPIO16 | GPIO23), &gpio1_base->oe);
-	writel(~GPIO22, &gpio4_base->oe);	/* 118 */
-	writel(~(GPIO0 | GPIO1 | GPIO28 | GPIO29 | GPIO30 | GPIO31),
-		&gpio5_base->oe);	/* 128, 129, 156-159 */
-	writel(~GPIO4, &gpio6_base->oe);	/* 164 */
+	/* set up dual-voltage GPIOs to 1.8V */
+	pbias_lite = readl(&t2_base->pbias_lite);
+	pbias_lite &= ~PBIASLITEVMODE1;
+	pbias_lite |= PBIASLITEPWRDNZ1;
+	writel(pbias_lite, &t2_base->pbias_lite);
+	if (get_cpu_family() == CPU_OMAP36XX)
+		writel(readl(CONTROL_WKUP_CTRL) | GPIO_IO_PWRDNZ,
+			CONTROL_WKUP_CTRL);
+
+	/* make sure audio and BT chips are in powerdown state */
+	set_output_gpio(14, 0);
+	set_output_gpio(15, 0);
+	set_output_gpio(118, 0);
+
+	/* enable USB supply */
+	set_output_gpio(164, 1);
 
-	/* Set GPIOs */
-	writel(GPIO28, &gpio5_base->setdataout);
-	writel(GPIO4, &gpio6_base->setdataout);
+	/* wifi needs a short pulse to enter powersave state */
+	set_output_gpio(23, 1);
+	udelay(5000);
+	gpio_direction_output(23, 0);
 
 	/* Enable battery backup capacitor (3.2V, 0.5mA charge current) */
 	twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
@@ -103,12 +131,15 @@ int misc_init_r(void)
 void set_muxconf_regs(void)
 {
 	MUX_PANDORA();
+	if (get_cpu_family() == CPU_OMAP36XX) {
+		MUX_PANDORA_3730();
+	}
 }
 
 #ifdef CONFIG_GENERIC_MMC
 int board_mmc_init(bd_t *bis)
 {
-	omap_mmc_init(0);
+	omap_mmc_init(0, 0, 0);
 	return 0;
 }
 #endif
diff --git a/board/pandora/pandora.h b/board/pandora/pandora.h
index f0ad16b0a4..fea8bf259a 100644
--- a/board/pandora/pandora.h
+++ b/board/pandora/pandora.h
@@ -399,4 +399,10 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
 	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
 
+#define MUX_PANDORA_3730() \
+	MUX_VAL(CP(GPIO126),		(IEN  | PTD | DIS | M4)) /*GPIO_126 - MMC1_WP*/\
+	MUX_VAL(CP(GPIO127),		(IEN  | PTD | DIS | M4)) /*GPIO_127 - MMC2_WP*/\
+	MUX_VAL(CP(GPIO128),		(IDIS | PTD | DIS | M4)) /*GPIO_128 - LED_MMC1*/\
+	MUX_VAL(CP(GPIO129),		(IDIS | PTD | DIS | M4)) /*GPIO_129 - LED_MMC2*/
+
 #endif
diff --git a/board/prodrive/p3mx/mv_eth.c b/board/prodrive/p3mx/mv_eth.c
index 9e3213bdff..06f816d2a1 100644
--- a/board/prodrive/p3mx/mv_eth.c
+++ b/board/prodrive/p3mx/mv_eth.c
@@ -109,8 +109,6 @@ int phy_setup_aneg (char *devname, unsigned char addr);
 #ifndef	 UPDATE_STATS_BY_SOFTWARE
 static void mv64460_eth_print_stat (struct eth_device *dev);
 #endif
-/* Processes a received packet */
-extern void NetReceive (volatile uchar *, int);
 
 extern unsigned int INTERNAL_REG_BASE_ADDR;
 
@@ -204,8 +202,7 @@ int db64460_eth_poll (struct eth_device *dev)
 	return mv64460_eth_receive (dev);
 }
 
-int db64460_eth_transmit (struct eth_device *dev, volatile void *packet,
-			  int length)
+int db64460_eth_transmit(struct eth_device *dev, void *packet, int length)
 {
 	mv64460_eth_xmit (dev, packet, length);
 	return 0;
diff --git a/board/prodrive/p3mx/mv_eth.h b/board/prodrive/p3mx/mv_eth.h
index af1527479f..8cc00dc9c6 100644
--- a/board/prodrive/p3mx/mv_eth.h
+++ b/board/prodrive/p3mx/mv_eth.h
@@ -166,9 +166,7 @@ struct mv64460_eth_priv {
 
 int mv64460_eth_init (struct eth_device *dev);
 int mv64460_eth_stop (struct eth_device *dev);
-int mv64460_eth_start_xmit (struct eth_device*, volatile void* packet, int length);
-/*	return db64460_eth0_poll(); */
-
+int mv64460_eth_start_xmit(struct eth_device *dev, void *packet, int length);
 int mv64460_eth_open (struct eth_device *dev);
 
 
diff --git a/board/raidsonic/ib62x0/Makefile b/board/raidsonic/ib62x0/Makefile
new file mode 100644
index 0000000000..d450f8d0ab
--- /dev/null
+++ b/board/raidsonic/ib62x0/Makefile
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= ib62x0.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c
new file mode 100644
index 0000000000..65f2c2ea6a
--- /dev/null
+++ b/board/raidsonic/ib62x0/ib62x0.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2011-2012
+ * Gerald Kerma <dreagle@doukki.net>
+ * Luka Perkov <uboot@lukaperkov.net>
+ * Simon Baatz <gmbnomis@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include "ib62x0.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the below configuration configures mainly initial LED status
+	 */
+	kw_config_gpio(IB62x0_OE_VAL_LOW,
+			IB62x0_OE_VAL_HIGH,
+			IB62x0_OE_LOW, IB62x0_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	u32 kwmpp_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP8_TW_SDA,
+		MPP9_TW_SCK,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_SATA1_ACTn,
+		MPP21_SATA0_ACTn,
+		MPP22_GPIO,     /* Power LED red */
+		MPP24_GPIO,     /* Power off device */
+		MPP25_GPIO,     /* Power LED green */
+		MPP27_GPIO,     /* USB transfer LED */
+		MPP28_GPIO,     /* Reset button */
+		MPP29_GPIO,     /* USB Copy button */
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+	return 0;
+}
diff --git a/board/raidsonic/ib62x0/ib62x0.h b/board/raidsonic/ib62x0/ib62x0.h
new file mode 100644
index 0000000000..0c30690697
--- /dev/null
+++ b/board/raidsonic/ib62x0/ib62x0.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2011-2012
+ * Gerald Kerma <dreagle@doukki.net>
+ * Simon Baatz <gmbnomis@gmail.com>
+ * Luka Perkov <uboot@lukaperkov.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __IB62x0_H
+#define __IB62x0_H
+
+#define IB62x0_OE_LOW		(~(1 << 22 | 1 << 24 | 1 << 25 | 1 << 27))
+#define IB62x0_OE_HIGH		(~(0))
+#define IB62x0_OE_VAL_LOW	0
+#define IB62x0_OE_VAL_HIGH	0
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG		10
+#define MV88E1116_CPRSP_CR3_REG		21
+#define MV88E1116_MAC_CTRL_REG		21
+#define MV88E1116_PGADR_REG		22
+#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
+
+#endif /* __IB62x0_H */
diff --git a/board/raidsonic/ib62x0/kwbimage.cfg b/board/raidsonic/ib62x0/kwbimage.cfg
new file mode 100644
index 0000000000..bd594ebd5d
--- /dev/null
+++ b/board/raidsonic/ib62x0/kwbimage.cfg
@@ -0,0 +1,169 @@
+#
+# Copyright (C) 2011-2012
+# Gerald Kerma <dreagle@doukki.net>
+# Simon Baatz <gmbnomis@gmail.com>
+# Luka Perkov <uboot@lukaperkov.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	nand	# change from nand to uart if building UART image
+NAND_ECC_MODE	default
+NAND_PAGE_SIZE	0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xffd100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xffd01400 0x43000c30	# DDR Configuration register
+# bit13-0:  0xc30, (3120 DDR2 clks refresh rate)
+# bit23-14: 0x0,
+# bit24:    0x1,     enable exit self refresh mode on DDR access
+# bit25:    0x1,     required
+# bit29-26: 0x0,
+# bit31-30: 0x1,
+
+DATA 0xffd01404 0x37543000	# DDR Controller Control Low
+# bit4:     0x0, addr/cmd in smame cycle
+# bit5:     0x0, clk is driven during self refresh, we don't care for APX
+# bit6:     0x0, use recommended falling edge of clk for addr/cmd
+# bit14:    0x0, input buffer always powered up
+# bit18:    0x1, cpu lock transaction enabled
+# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 0x3, required
+# bit31:    0x0, no additional STARTBURST delay
+
+DATA 0xffd01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11-8:  TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xffd0140c 0x00000a33	# DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: 0x0, required
+
+DATA 0xffd01410 0x0000000c	# DDR Address Control
+# bit1-0:   00,  Cs0width (x8)
+# bit3-2:   11,  Cs0size (1Gb)
+# bit5-4:   00,  Cs1width (x8)
+# bit7-6:   11,  Cs1size (1Gb)
+# bit9-8:   00,  Cs2width (nonexistent
+# bit11-10: 00,  Cs2size  (nonexistent
+# bit13-12: 00,  Cs3width (nonexistent
+# bit15-14: 00,  Cs3size  (nonexistent
+# bit16:    0,   Cs0AddrSel
+# bit17:    0,   Cs1AddrSel
+# bit18:    0,   Cs2AddrSel
+# bit19:    0,   Cs3AddrSel
+# bit31-20: 0x0, required
+
+DATA 0xffd01414 0x00000000	# DDR Open Pages Control
+# bit0:    0,   OpenPage enabled
+# bit31-1: 0x0, required
+
+DATA 0xffd01418 0x00000000	# DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0x0, required
+
+DATA 0xffd0141c 0x00000c52	# DDR Mode
+# bit2-0:   0x2, BurstLen=2 required
+# bit3:     0x0, BurstType=0 required
+# bit6-4:   0x4, CL=5
+# bit7:     0x0, TestMode=0 normal
+# bit8:     0x0, DLL reset=0 normal
+# bit11-9:  0x6, auto-precharge write recovery ????????????
+# bit12:    0x0, PD must be zero
+# bit31-13: 0x0, required
+
+DATA 0xffd01420 0x00000040	# DDR Extended Mode
+# bit0:     0,   DDR DLL enabled
+# bit1:     0,   DDR drive strenght normal
+# bit2:     1,   DDR ODT control lsd (disabled)
+# bit5-3:   0x0, required
+# bit6:     0,   DDR ODT control msb, (disabled)
+# bit9-7:   0x0, required
+# bit10:    0,   differential DQS enabled
+# bit11:    0,   required
+# bit12:    0,   DDR output buffer enabled
+# bit31-13: 0x0, required
+
+DATA 0xffd01424 0x0000f17f	# DDR Controller Control High
+# bit2-0:   0x7, required
+# bit3:     0x1, MBUS Burst Chop disabled
+# bit6-4:   0x7, required
+# bit7:     0x0,
+# bit8:     0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9:     0x0, no half clock cycle addition to dataout
+# bit10:    0x0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11:    0x0, 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 0xf, required
+# bit31-16: 0,   required
+
+DATA 0xffd01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xffd0147c 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xffd01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xffd01504 0x0ffffff1	# CS[0]n Size
+# bit0:     0x1,     Window enabled
+# bit1:     0x0,     Write Protect disabled
+# bit3-2:   0x0,     CS0 hit selected
+# bit23-4:  0xfffff, required
+# bit31-24: 0x0f,    Size (i.e. 256MB)
+
+DATA 0xffd01508 0x10000000	# CS[1]n Base address to 256Mb
+DATA 0xffd0150c 0x00000000	# CS[1]n Size, window disabled
+
+DATA 0xffd01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xffd0151c 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xffd01494 0x00030000	# DDR ODT Control (Low)
+# bit3-0:     ODT0Rd, MODT[0] asserted during read from DRAM CS1
+# bit7-4:     ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
+# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xffd01498 0x00000000	# DDR ODT Control (High)
+# bit1-0:  0x0, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  0x1, ODT1 active NEVER!
+# bit31-4: 0x0, required
+
+DATA 0xffd0149c 0x0000e803	# CPU ODT Control
+DATA 0xffd01480 0x00000001	# DDR Initialization Control
+# bit0: 0x1, enable DDR init upon this register write
+
+DATA 0xFFD20134 0x66666666      # L2 RAM Timing 0 Register
+DATA 0xFFD20138 0x66666666      # L2 RAM Timing 1 Register
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/rda/common/Makefile b/board/rda/common/Makefile
new file mode 100644
index 0000000000..cfed607650
--- /dev/null
+++ b/board/rda/common/Makefile
@@ -0,0 +1,83 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(VENDOR).o
+
+COBJS-y	+= misc.o board.o
+ifndef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_VPU_TEST) += vpu_test.o rda_md5.o
+COBJS-$(CONFIG_CPU_TEST) += cpu_test.o
+COBJS-$(CONFIG_DDR_TEST) += ddr_test.o
+COBJS-$(CONFIG_TIMER_TEST) += timer_test.o
+COBJS-$(CONFIG_UART_TEST) += uart_test.o
+COBJS-$(CONFIG_I2C_TEST) += i2c_test.o
+COBJS-$(CONFIG_GIC_TEST) += gic_test.o
+COBJS-$(CONFIG_CACHE_TEST) += a7_cp15_reg.o		\
+				cache_test.o
+COBJS-$(CONFIG_MIPI_LOOP_TEST) += rda_lcdc.o		\
+				rda_mipi_dsi.o		\
+			        hal_camera.o 		\
+			        mipi_loop_test.o
+
+endif
+
+CPPFLAGS_board/$(VENDOR)/common/vpu_test.o += -I$(TOPDIR)/board/$(VENDOR)/common/include
+CPPFLAGS_board/$(VENDOR)/common/rda_md5.o += -I$(TOPDIR)/board/$(VENDOR)/common/include
+CPPFLAGS_board/$(VENDOR)/common/cpu_test.o += -I$(TOPDIR)/board/$(VENDOR)/common/include
+CPPFLAGS_board/$(VENDOR)/common/ddr_test.o += -I$(TOPDIR)/board/$(VENDOR)/common/include
+CPPFLAGS_board/$(VENDOR)/common/timer_test.o += -I$(TOPDIR)/board/$(VENDOR)/common/include
+CPPFLAGS_board/$(VENDOR)/common/uart_test.o += -I$(TOPDIR)/board/$(VENDOR)/common/include
+CPPFLAGS_board/$(VENDOR)/common/i2c_test.o += -I$(TOPDIR)/board/$(VENDOR)/common/include
+CPPFLAGS_board/$(VENDOR)/common/gic_test.o += -I$(TOPDIR)/board/$(VENDOR)/common/include
+CPPFLAGS_board/$(VENDOR)/common/cache_test.o += -I$(TOPDIR)/board/$(VENDOR)/common/include
+
+CPPFLAGS_board/$(VENDOR)/common/rda_lcdc.o += -I$(TOPDIR)/board/$(VENDOR)/common/include
+CPPFLAGS_board/$(VENDOR)/common/rda_mipi_dsi.o += -I$(TOPDIR)/board/$(VENDOR)/common/include
+CPPFLAGS_board/$(VENDOR)/common/hal_camera.o += -I$(TOPDIR)/board/$(VENDOR)/common/include
+CPPFLAGS_board/$(VENDOR)/common/mipi_loop_test.o += -I$(TOPDIR)/board/$(VENDOR)/common/include
+COBJS   := $(COBJS-y)
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak *~ .depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/rda/common/a7_cp15_reg.S b/board/rda/common/a7_cp15_reg.S
new file mode 100644
index 0000000000..122a457f56
--- /dev/null
+++ b/board/rda/common/a7_cp15_reg.S
@@ -0,0 +1,238 @@
+/* read cp15 main id register */
+.globl	read_cp15_midr
+read_cp15_midr:
+	mrc	p15,0,r0,c0,c0,0
+	mov pc,lr
+
+/* read cp15 multiprocessor id register */
+.globl	read_cp15_mpidr
+read_cp15_mpidr:
+	mrc	p15,0,r0,c0,c0,5
+	mov pc,lr
+
+/* read cp15 revision id register */
+.globl	read_cp15_revidr
+read_cp15_revidr:
+	mrc	p15,0,r0,c0,c0,6
+	mov pc,lr
+
+/* read cp15 cache size id register */
+.globl	read_cp15_ccsidr
+read_cp15_ccsidr:
+	mrc	p15,1,r0,c0,c0,0
+	mov pc,lr
+
+/* read cp15 cache level id register */
+.globl	read_cp15_clidr
+read_cp15_clidr:
+	mrc	p15,1,r0,c0,c0,1
+	mov pc,lr
+
+/* read cp15 cache size selection register */
+.globl	read_cp15_csselr
+read_cp15_csselr:
+	mrc	p15,2,r0,c0,c0,0
+	mov 	r0,r0
+	nop
+	nop
+	mov pc,lr
+
+/* write cp15 cache size selection register */
+.globl	write_cp15_csselr
+write_cp15_csselr:
+	mcr	p15,2,r0,c0,c0,0
+	mov 	r0,r0
+	nop
+	nop
+	mov pc,lr
+
+/* read cp15 system control register */
+.globl	read_cp15_sctlr
+read_cp15_sctlr:
+	mrc	p15,0,r0,c1,c0,0
+	mov	pc,lr
+
+/* write cp15 system control register */
+.globl	write_cp15_sctlr
+write_cp15_sctlr:
+	mcr	p15,0,r0,c1,c0,0
+	mov	pc,lr
+
+/* read cp15 secure configuration register */
+.globl	read_cp15_scr
+read_cp15_scr:
+	mrc	p15,0,r0,c1,c1,0
+	mov	pc,lr
+
+/* write cp15 secure configuration register */
+.globl	write_cp15_scr
+write_cp15_scr:
+	mcr	p15,0,r0,c1,c1,0
+	mov	pc,lr
+
+/* read cp15 l2 control register */
+.globl	read_cp15_l2ctlr
+read_cp15_l2ctlr:
+	mrc	p15,1,r0,c9,c0,2
+	mov	pc,lr
+
+.globl	read_cp15_ttbr0
+read_cp15_ttbr0:
+	mrc	p15,0,r0,c2,c0,0
+	mov	pc,lr
+
+.globl	write_cp15_ttbr0
+write_cp15_ttbr0:
+	mcr	p15,0,r0,c2,c0,0
+	mov	pc,lr
+
+.globl	read_cp15_ttbr1
+read_cp15_ttbr1:
+	mrc	p15,0,r0,c2,c0,1
+	mov	pc,lr
+
+.globl	write_cp15_ttbr1
+write_cp15_ttbr1:
+	mcr	p15,0,r0,c2,c0,1
+	mov	pc,lr
+
+.globl	read_cp15_ttbcr
+read_cp15_ttbcr:
+	mrc	p15,0,r0,c2,c0,2
+	mov	pc,lr
+
+.globl	write_cp15_ttbcr
+write_cp15_ttbcr:
+	mcr	p15,0,r0,c2,c0,2
+	mov	pc,lr
+
+.globl	read_cp15_htcr
+read_cp15_htcr:
+	mrc	p15,4,r0,c2,c0,2
+	mov	pc,lr
+
+.globl	write_cp15_htcr
+write_cp15_htcr:
+	mcr	p15,4,r0,c2,c0,2
+	mov	pc,lr
+
+.globl	write_cp15_dacr
+write_cp15_dacr:
+	mcr	p15,0,r0,c3,c0,0
+	mov	pc,lr
+
+
+/*
+ * r0: des addr
+ * r1: src addr
+ * r2: size
+ */
+.globl	__copy_bytes
+__copy_bytes:
+	stmfd	sp!,{r4-r11,lr}
+__copy_bytes_start:
+	cmp	r2,#0x0
+	beq	__copy_bytes_end
+	ldrb	r4,[r1]
+	strb	r4,[r0]
+	add	r0,r0,#0x1
+	add	r1,r1,#0x1
+	sub	r2,r2,#0x1
+	b	__copy_bytes_start
+__copy_bytes_end:
+	ldmfd	sp!,{r4-r11,pc}
+
+.globl	__nop_dly
+__nop_dly:
+	nop
+	mov	pc,lr
+
+/* read cpu cpsr register */
+.globl	read_cpu_cpsr
+read_cp15_cpsr:
+	mrs	r0,cpsr
+	mov	pc,lr
+
+/* write cpu cpsr register */
+.globl	write_cpu_cpsr
+write_cp15_cpsr:
+	msr	cpsr,r0
+	mov	pc,lr
+
+.globl	cp15_disable_all_cache
+cp15_disable_all_cache:
+	dsb
+	isb
+	mov	r0,#0
+	mcr	p15,0,r0,c8,c7,0  // invalidate TLBs
+	mcr	p15,0,r0,c7,c5,0  // invalidate instruction cache
+	mcr	p15,0,r0,c7,c5,6  // invalidate branch prediction
+	mcr	p15,0,r0,c7,c10,4 // CP15DSB
+	mcr	p15,0,r0,c7,c5,4  // CP15ISB
+
+	mrc	p15,0,r0,c1,c0,0
+	bic	r0,r0,#0x00002000 // vector bit = 0
+	bic	r0,r0,#0x00000004 // disable dcache
+	bic	r0,r0,#0x00000001 // disable mmu
+	orr	r0,r0,#0x00000002 // enable aligh checking
+	orr	r0,r0,#0x00000800 // enable prediction
+	bic	r0,r0,#0x00001000 // disable icache
+	mcr	p15,0,r0,c1,c0,0
+	dsb
+	isb
+	mov	pc,lr
+
+.globl	cp15_enable_dcache
+cp15_enable_dcache:
+	dsb
+	isb
+	mrc	p15,0,r0,c1,c0,0
+	orr	r0,r0,#0x00000004 // enable dcache
+	mcr	p15,0,r0,c1,c0,0
+	mov	pc,lr
+
+.globl	cp15_enable_icache
+cp15_enable_icache:
+	dsb
+	isb
+	mrc	p15,0,r0,c1,c0,0
+	orr	r0,r0,#0x00001000 // enable icache
+	mcr	p15,0,r0,c1,c0,0
+	mov	pc,lr
+
+.globl	cp15_enable_mmu
+cp15_enable_mmu:
+	mrc	p15,0,r0,c1,c0,0
+	orr	r0,r0,#0x00000800 // enable prediction
+	orr	r0,r0,#0x00000001 // enable mmu
+	mcr	p15,0,r0,c1,c0,0
+
+	mcr	p15,0,r0,c7,c5,4  // CP15ISB
+	mov	pc,lr
+
+.globl	cp15_disable_dcache
+cp15_disable_dcache:
+	dsb
+	isb
+	mrc	p15,0,r0,c1,c0,0
+	bic	r0,r0,#0x00000004 // disable dcache
+	mcr	p15,0,r0,c1,c0,0
+	mov	pc,lr
+
+.globl	cp15_disable_icache
+cp15_disable_icache:
+	dsb
+	isb
+	mrc	p15,0,r0,c1,c0,0
+	bic	r0,r0,#0x00001000 // disable icache
+	mcr	p15,0,r0,c1,c0,0
+	mov	pc,lr
+
+.globl	cp15_disable_mmu
+cp15_disable_mmu:
+	mrc	p15,0,r0,c1,c0,0
+	bic	r0,r0,#0x00000001 // disable mmu
+	mcr	p15,0,r0,c1,c0,0
+
+	mcr	p15,0,r0,c7,c5,4  // CP15ISB
+	mov	pc,lr
diff --git a/board/rda/common/board.c b/board/rda/common/board.c
new file mode 100644
index 0000000000..0fc11eff7c
--- /dev/null
+++ b/board/rda/common/board.c
@@ -0,0 +1,48 @@
+#include <common.h>
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PHYS_SDRAM_1			(0x80000000) /* DRAM Start */
+#define LINUX_BOOT_PARAM_ADDR		(PHYS_SDRAM_1 + 0x100)
+
+#ifdef CONFIG_MACH_RDA8810
+#define BOARD_NAME	"RDA8810"
+#elif defined(CONFIG_MACH_RDA8810E)
+#define BOARD_NAME	"RDA8810E"
+#elif defined(CONFIG_MACH_RDA8810H)
+#define BOARD_NAME	"RDA8810H"
+#elif defined(CONFIG_MACH_RDA8820)
+#define BOARD_NAME	"RDA8820"
+#elif defined(CONFIG_MACH_RDA8850)
+#define BOARD_NAME	"RDA8850"
+#elif defined(CONFIG_MACH_RDA8850E)
+#define BOARD_NAME	"RDA8850E"
+#else
+#define BOARD_NAME	"UNKNOWN"
+#endif
+
+int checkboard (void){
+	puts("Board: "BOARD_NAME"\n");
+	return 0;
+}
+
+/*
+ * get_board_rev() - setup to pass kernel board revision information
+ * Returns:
+ * bit[0-3]	Maximum cpu clock rate supported by onboard SoC
+ */
+u32 get_board_rev(void)
+{
+	u32 rev = 0;
+	return rev;
+}
+
+int board_init(void)
+{
+	/* arch number of the board */
+	gd->bd->bi_arch_number = machine_arch_type;
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+	return 0;
+}
+
diff --git a/board/rda/common/cache_test.c b/board/rda/common/cache_test.c
new file mode 100644
index 0000000000..f5e204421a
--- /dev/null
+++ b/board/rda/common/cache_test.c
@@ -0,0 +1,510 @@
+#include <common.h>
+#include <asm/arch/global_macros.h>
+#include <asm/arch/cs_types.h>
+#include <asm/arch/rda_iomap.h>
+#include <asm/arch/reg_timer.h>
+#include "a7_cp15_reg.h"
+
+#define d_printf printf
+#define n_printf printf
+
+#define L2C_SZ_1K	0x00000400
+#define L2C_SZ_16K	0x00004000
+#define L2C_SZ_256K	0x00040000
+
+#define L2C_FILL_SIZE	256
+#define L2C_WAY_NUM     16
+#define L2C_WAY_SIZE	0x4000
+#define L2C_LINE_SIZE	32
+#define BANK_NUM	3
+
+/* SRAM start address is 0x00100000 */
+#define CONFIG_SRAM_START	0x00100000
+/* SRAM size is 64KB */
+#define CONFIG_SRAM_SIZE	0x00010000
+/* DRAM start address is 0x80000000 */
+#define CONFIG_DRAM_START	0x80000000
+/* DRAM size is 256MB */
+#define CONFIG_DRAM_SIZE	0x10000000
+/* IO start address is 0x20000000 */
+#define CONFIG_IO_START		0x20000000
+/* IO size is 0x256MB */
+#define CONFIG_IO_SIZE		0x10000000
+/* MMU TLB address is 0x00108000 */
+#define CONFIG_TEST_MMU_TLB_ADDR (CONFIG_SRAM_START + 0x8000)
+
+#define GET_ARRAY_SIZE(array)	(sizeof(array) / sizeof((array)[0]))
+
+/* tick / 2000 = n ms ,freq = 2MHz */
+#define TICK_TO_MS(tick)	((tick) / 2000)
+#define MS_TO_TICK(ms)	((ms) * 2000)
+
+typedef struct
+{
+	int id;
+	const char *name;
+}armv7_cache_t;
+
+typedef struct
+{
+	unsigned int sel;
+	unsigned int num_sets;
+	unsigned int size;
+}armv7_cache_size_t;
+
+static const armv7_cache_t a7_cache_tab[] =
+{
+	{0,"l1 d-cache"},
+	{1,"l1 i-cache"},
+	{2,"l2 cache"},
+};
+
+static const armv7_cache_size_t a7_cache_size_tab[] =
+{
+	{0,0x1F, 8,},//l1 d-cache
+	{0,0x3F, 16},
+	{0,0x7F, 32},
+	{0,0xFF, 64},
+	{1,0x7F, 8,},//l1 i-cache
+	{1,0xFF, 16},
+	{1,0x1FF,32},
+	{1,0x3FF,64},
+	{2,0xFF, 128,},//l2 cache
+	{2,0x1FF,256},
+	{2,0x3FF,512},
+	{2,0x7FF,1024},
+};
+
+struct bank_info {
+	struct {
+		u32 start;
+		u32 size;
+	}ram[BANK_NUM];
+};
+
+#if 0
+static struct bank_info ram_table;
+static u32 ttb_base = 0;
+
+static void *l2c_base = (void *)RDA_L2CC_BASE;
+static u32 l2c_way_mask = 0;	/* Bitmask of active ways */
+static u32 l2c_size = 0;
+static u32 l2c_sets = 0;
+static u32 l2c_ways = 0;
+#endif
+
+static u8 *test_phyaddr = (u8 *)(CONFIG_DRAM_START + 0x04000000);
+
+typedef union
+{
+    unsigned long long timer;
+    struct
+    {
+        unsigned int timer_l     :32;
+        unsigned int timer_h     :32;
+    }fields;
+}TIMER;
+
+
+static void timer_get(TIMER *timer)
+{
+	timer->fields.timer_h = (unsigned int)(hwp_apTimer->HWTimer_LockVal_H);
+	timer->fields.timer_l = (unsigned int)(hwp_apTimer->HWTimer_LockVal_L);
+	if(timer->fields.timer_h != hwp_apTimer->HWTimer_LockVal_H) {
+		timer->fields.timer_h = (unsigned int)(hwp_apTimer->HWTimer_LockVal_H);
+		timer->fields.timer_l = (unsigned int)(hwp_apTimer->HWTimer_LockVal_L);
+	}
+}
+
+static void timer_start(TIMER *timer)
+{
+	timer_get(timer);
+}
+
+static unsigned long long timer_stop(TIMER *timer)
+{
+	unsigned long long start,end,elaps;
+	start = timer->timer;
+	timer_get(timer);
+	end = timer->timer;
+	if(start <= end)
+		elaps = end - start;
+	else
+		elaps = (unsigned long long )0xFFFFFFFFFFFFFFFFULL - (start - end);
+	return elaps;
+}
+
+static int is_cpu_secure(void)
+{
+	unsigned int is_secure;
+	unsigned int scr = read_cp15_scr();
+	d_printf("scr = %x\n",scr);
+	scr &= 0x01;
+	is_secure =  (scr == 0) ? (1) : (0);
+	return is_secure;
+}
+
+static int is_l2cache_exist(void)
+{
+	unsigned int existed = 0;
+	unsigned int clidr = read_cp15_clidr();
+	d_printf("clidr = %x\n",clidr);
+	clidr = (clidr >> 3) & 0x7;//bit[5:3]
+	if(clidr)
+		existed = 1;
+	return existed;
+}
+
+/*
+ *level = 0: L1 D-Cache
+ *level = 1: L1 I-Cache
+ *level = 2: L2 D-Cache
+ */
+static int select_cache(int level)
+{
+	unsigned int csselr = 0;
+
+	if((level < 0) || (level > 2)) {
+		d_printf("select cache error,level is %d\n",level);
+		return -1;
+	}
+	d_printf("select %s\n",a7_cache_tab[level].name);
+	csselr = read_cp15_csselr();
+	d_printf("\ncsselr = %x\n",csselr);
+
+	csselr &= ~(0xF << 0);//bit[3:0]
+	csselr |= level;
+	write_cp15_csselr(csselr);
+	return 0;
+}
+
+static int parse_cache_info(int level,unsigned int val)
+{
+	unsigned int line_size,asso,ways,num_sets,wa,ra,wb,wt;
+	int i,num;
+
+	d_printf("\nparse value %x\n",val);
+
+	line_size = val & 0x7;
+	asso = (val >> 3) & 0x3FF;
+	num_sets = (val >> 13) & 0x7FFF;
+	wa = (val >> 28) & 0x1;
+	ra = (val >> 29) & 0x1;
+	wb = (val >> 30) & 0x1;
+	wt = (val >> 31) & 0x1;
+
+	if(wt)
+		n_printf("Write-Through:    Yes\n");
+	else
+		n_printf("Write-Through:    No\n");
+	if(wb)
+		n_printf("Write-Back:       Yes\n");
+	else
+		n_printf("Write-Back:       No\n");
+	if(ra)
+		n_printf("Read-Allocation:  Yes\n");
+	else
+		n_printf("Read-Allocation:  No\n");
+	if(wa)
+		n_printf("Write-Allocation: Yes\n");
+	else
+		n_printf("Write-Allocation: No\n");
+
+	ways = asso + 1;
+	n_printf("Associativity is %d-ways\n",ways);
+
+	line_size = line_size * 8;
+	n_printf("%d words per line\n\n",line_size);
+
+	num = GET_ARRAY_SIZE(a7_cache_size_tab);
+	for(i = 0;i < num;i++) {
+		if((level == a7_cache_size_tab[i].sel)
+			&& (num_sets == a7_cache_size_tab[i].num_sets))
+			break;
+	}
+	if(i >= num) {
+		n_printf("parse cache size error\n");
+		return -1;
+	}
+	n_printf("%s size is %d KB\n",
+			a7_cache_tab[level].name,
+			a7_cache_size_tab[i].size);
+	return 0;
+}
+
+static int print_cache_info(int level)
+{
+	unsigned int ccsidr;
+	if(select_cache(level)) {
+		n_printf("select cache failed\n");
+		return -1;
+	}
+	ccsidr = read_cp15_ccsidr();
+	parse_cache_info(level,ccsidr);
+	return 0;
+}
+
+static void read_sys_ctrl_reg(void)
+{
+	unsigned int val = read_cp15_sctlr();
+	n_printf("sctlr is %x\n",val);
+}
+
+static int init_test_buffer(void)
+{
+	int i;
+	for(i = 0;i < L2C_FILL_SIZE;i++)
+		test_phyaddr[i] = i;
+	return 0;
+}
+#if 0
+static void init_banks(void)
+{
+	/*
+	 * Page table is at end of DRAM, and 16K align.
+	 */
+	ttb_base = CONFIG_TEST_MMU_TLB_ADDR;
+
+	/* SRAM address */
+	ram_table.ram[0].start = CONFIG_SRAM_START;
+	ram_table.ram[0].size  = CONFIG_SRAM_SIZE;
+	/* IOMAP address */
+	ram_table.ram[1].start = CONFIG_IO_START;
+	ram_table.ram[1].size = CONFIG_IO_SIZE;
+	/* DDRAM address */
+	ram_table.ram[2].start = CONFIG_DRAM_START;
+	ram_table.ram[2].size  = CONFIG_DRAM_SIZE;
+}
+
+unsigned int init_pgtable(void)
+{
+	int i;
+	unsigned int *page_table = (unsigned int *)ttb_base;
+	unsigned int val = 0xFFFFFFFF;
+
+	/* Set up an identity-mapping for all 4GB, rw for everyone */
+	for (i = 0; i < 4096; i++) {
+		/*
+		 * Section description definition
+		 *
+		 * TEX[2:0]----AP[1:0]----CB
+		 *    000              11               00
+		 */
+		page_table[i] = (i << 20) | (3 << 10) | 0x2;
+	}
+	/*
+	 * Update memory attribute
+	 * TEX[2:0]----AP[1:0]----CB
+	 *    001              11               11
+	 */
+	page_table[0] = (0 << 20) | (1 << 12) | (3 << 10) | 0xE;
+	page_table[1] = (1 << 20) | (1 << 12) | (3 << 10) | 0xE;
+	for (i = (ram_table.ram[1].start >> 20);
+		i < ((ram_table.ram[1].start + ram_table.ram[1].size) >> 20);
+		i++) {
+		/*
+		 * Update memory attribute
+		 * TEX[2:0]----AP[1:0]----CB
+		 *    000              11               00
+		 */
+		page_table[i] = (i << 20) | (3 << 10) | 0x2;
+	}
+	for (i = (ram_table.ram[2].start >> 20);
+		i < ((ram_table.ram[2].start + ram_table.ram[2].size) >> 20);
+		i++) {
+		/*
+		 * Update memory attribute
+		 * TEX[2:0]----AP[1:0]----CB
+		 *    001              11               11
+		 */
+		page_table[i] = (i << 20) | (1 << 12) | (3 << 10) | 0xE;
+	}
+	// set TTBR0
+	write_cp15_ttbr0((unsigned int)page_table);
+	for(i = 0;i < 0x1000;i++)
+		__nop_dly();
+
+	// TODO: set TTBR1
+	//write_cp15_ttbr1((unsigned int)page_table);
+
+	// TODO: set TTBCR
+	//write_cp15_ttbcr(0);
+
+	// TODO: set HTCR
+	//write_cp15_htcr(0);
+
+	// write access domain register
+	write_cp15_dacr(val);
+	for(i = 0;i < 0x1000;i++)
+		__nop_dly();
+
+	d_printf("page table address is %x\n",(unsigned int)page_table);
+	d_printf("dommain access control register value is %x\n",val);
+	return 0;
+}
+
+void cpu_setup_mmu(int enabled)
+{
+	int i;
+	if(enabled) {
+		init_banks();
+		init_pgtable();
+
+		cp15_enable_mmu();
+		for(i = 0;i < 0x1000;i++)
+			__nop_dly();
+		d_printf("MMU enabled\n");
+	} else {
+		cp15_disable_mmu();
+		for(i = 0;i < 0x1000;i++)
+			__nop_dly();
+		d_printf("MMU disabled\n");
+	}
+}
+#endif
+static int gen_fibonacci_num(int n)
+{
+	volatile int a = 0,b = 1,s = 0;
+	while(n--) {
+		s += a;
+		s += b;
+		a += b;
+		b += b;
+	}
+	return s;
+}
+
+static int test_icache(unsigned int test_num)
+{
+	volatile int i = test_num;
+	TIMER timer;
+	unsigned int tick;
+	int cost;
+
+	d_printf("test icache\n");
+	timer_start(&timer);
+	d_printf("timer started\n");
+
+	while (i--) {
+		gen_fibonacci_num(10);
+	};
+
+	tick = timer_stop(&timer);
+	cost = TICK_TO_MS(tick);
+	d_printf("<<<<<<<< Ins total time = %d ms\n",cost);
+	return cost;
+}
+
+static int test_dcache(unsigned int test_num)
+{
+	volatile u8 value = 0;
+	u32 i = 0;
+	u32 j = 0;
+	TIMER timer;
+	unsigned int tick;
+	int cost;
+
+	d_printf("test dcache\n");
+	timer_start(&timer);
+	d_printf("timer started\n");
+
+	for (i = 0; i < test_num; i++) {
+		for (j = 0; j < L2C_FILL_SIZE; j++) {
+			value = test_phyaddr[j];
+		}
+	}
+	value = value;
+	tick = timer_stop(&timer);
+	cost = TICK_TO_MS(tick);
+	d_printf("<<<<<<<< Data total time = %d ms\n",cost);
+	return cost;
+}
+
+void l2cache_test(void)
+{
+	unsigned int cost_time[4];
+
+	n_printf("\n\n");
+	n_printf("====== L2 cache test ======\r\n");
+
+	n_printf("\n========> check cpu secure state\n");
+	if(is_cpu_secure()) {
+		n_printf("cpu is in secure state\n");
+	} else {
+		n_printf("cpu is in none secure state\n");
+	}
+
+	n_printf("\n========> check l2 cache existing\n");
+	if(!is_l2cache_exist()) {
+		n_printf("l2 cache do not exist\n");
+		return;
+	} else {
+		n_printf("exist l2 cache\n");
+	}
+
+	n_printf("\n========> print L1 data cache info\n");
+	print_cache_info(0);
+
+	n_printf("\n========> print L1 instruction cache info\n");
+	print_cache_info(1);
+
+	n_printf("\n========> print L2 data cache info\n");
+	print_cache_info(2);
+
+	n_printf("\n========> test cache: disable L1,L2 cache\n");
+
+	n_printf("read sys ctrl register before disable cache\n");
+	read_sys_ctrl_reg();
+	icache_disable();
+	dcache_disable();
+	n_printf("read sys ctrl register after disable cache\n");
+	read_sys_ctrl_reg();
+
+	init_test_buffer();
+	cost_time[0] = test_icache(0x10000);
+	cost_time[1] = test_dcache(0x1000);
+
+	n_printf("\n========> test cache: enable  L1,L2 cache\n");
+	/*
+	 * set TTBR0,TTBR1,DACR,HTCR
+	 * enable MMU,I-cache,D-cache
+	 */
+	icache_enable();
+	dcache_enable();
+	n_printf("read sys ctrl register after enable cache\n");
+	read_sys_ctrl_reg();
+
+	n_printf("delay n ms ...\n");
+	mdelay(10);
+	/* run test program */
+	cost_time[2] = test_icache(0x10000);
+	cost_time[3] = test_dcache(0x1000);
+
+	read_sys_ctrl_reg();
+
+	/* print result */
+	n_printf("\n========> test cache result\n");
+
+	n_printf("\n========> L1,L2 Disabled\n"
+			"I-Cache tests cost time: %8d ms "
+			"D-Cache tests cost time: %8d ms ",
+			cost_time[0],cost_time[1]);
+
+	n_printf("\n========> L1,L2 Enabled\n"
+			"I-Cache tests cost time: %8d ms "
+			"D-Cache tests cost time: %8d ms ",
+			cost_time[2],cost_time[3]);
+	n_printf("\n========> test cache finished !\n");
+}
+
+int cpu_cache_test(int times)
+{
+	int n = 0;
+	while(n < times) {
+		n++;
+		n_printf("\ncpu_cache_test: %d / %d \n",n,times);
+		l2cache_test();
+		n_printf("\ncpu_cache_test end\n");
+	}
+	return 0;
+}
diff --git a/board/rda/common/cpu_test.c b/board/rda/common/cpu_test.c
new file mode 100644
index 0000000000..36a83aa143
--- /dev/null
+++ b/board/rda/common/cpu_test.c
@@ -0,0 +1,58 @@
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/reg_sysctrl.h>
+
+#ifdef CONFIG_MACH_RDA8810
+static void apsys_cpupll_switch(int on)
+{
+	volatile u32 *clock_reg = &hwp_sysCtrlAp->Sel_Clock;
+	volatile u32 *pll_ctrl_reg = &hwp_sysCtrlAp->Cfg_Pll_Ctrl[0];
+
+	if (on) {
+		int val;
+		u32 clk_value = readl(clock_reg);
+
+		val  = SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE |
+			SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET |
+			SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(6)|
+			SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(30);
+		writel(val, pll_ctrl_reg);
+		val = readl(pll_ctrl_reg);
+		val |= SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_ENABLE;
+		writel(val, pll_ctrl_reg);
+
+		clk_value &= ~(1 << 4);
+		writel(clk_value, clock_reg);
+	} else {
+		int val;
+		u32 clk_value = readl(clock_reg);
+
+		clk_value |= SYS_CTRL_AP_CPU_SEL_FAST_SLOW;
+		writel(clk_value, clock_reg);
+		val = SYS_CTRL_AP_AP_PLL_ENABLE_POWER_DOWN |
+			SYS_CTRL_AP_AP_PLL_LOCK_RESET_RESET;
+		writel(val, pll_ctrl_reg);
+	}
+}
+#else
+static void apsys_cpupll_switch(int on)
+{
+}
+#endif
+
+void cpu_pll_test(int times)
+{
+	int i;
+
+	printf("cpu pll switch test....\n");
+	for(i = 0; i < times; i++) {
+		printf("on/off %d times\r", i+1);
+		apsys_cpupll_switch(0);
+		udelay(100);
+		apsys_cpupll_switch(1);
+		udelay(100);
+	}
+	printf("\n cpu pll finished\n");
+
+}
+
diff --git a/board/rda/common/ddr_test.c b/board/rda/common/ddr_test.c
new file mode 100644
index 0000000000..a390e55a4d
--- /dev/null
+++ b/board/rda/common/ddr_test.c
@@ -0,0 +1,80 @@
+#include <common.h>
+
+#if defined(CONFIG_MACH_RDA8810E) || defined(CONFIG_MACH_RDA8810H) || defined(CONFIG_MACH_RDA8850E)
+
+#define DDR_TEST_DEBUG
+
+#ifdef DDR_TEST_DEBUG
+#define d_printf	printf
+#else
+#define d_printf(...)	do{}while(0)
+#endif
+
+/* HWTIMER frequency is 2M,so 1 tick is 0.5 us */
+#define TIME_TICK_TO_US(t)	(t/2)
+#define DDR_MEM_START_ADDR	0X80000000
+#define DDR_MEM_END_ADDR	0XBFFFFFFF
+
+int ddr_mem_copy_test(int times,unsigned int src_addr, unsigned int des_addr, unsigned int nword)
+{
+	unsigned int err = 0;
+	unsigned int *ptr_src,*ptr_des,n = 0;
+	int count = 0;
+	unsigned long long tick1 = 0,tick2 = 0;
+
+	/* checkt test times value */
+	if((times <= 0)
+		||(src_addr<DDR_MEM_START_ADDR)
+		||(src_addr>DDR_MEM_END_ADDR)
+		||(des_addr<DDR_MEM_START_ADDR)
+		||(des_addr>DDR_MEM_END_ADDR)) {
+
+		printf("\nInvalid parameters,times: %d\t,src_addr: 0x%x\t,des_addr: 0x%x\t, nword: 0x%x\n",
+			times,src_addr, des_addr,nword);
+		return -1;
+	}
+	printf("\n_ddr_mem_copy_test,times:%d\t,src_addr: 0x%x\t,des_addr: 0x%x\t, nword: 0x%x\n",
+		times,src_addr, des_addr,nword);
+LAB_COPY:
+	tick1 = get_ticks();
+	d_printf("tick1: %llu\n",tick1);
+	/* copy data from src to des */
+	ptr_src = (unsigned int *)src_addr;
+	ptr_des = (unsigned int *)des_addr;
+	n = nword;
+	d_printf("data copying...\n");
+	while(n--) {
+		*ptr_des++ = *ptr_src++;
+	}
+	/* compare src and des */
+	ptr_src = (unsigned int *)src_addr;
+	ptr_des = (unsigned int *)des_addr;
+	n = nword;
+	d_printf("data checking...\n");
+	while(n--) {
+		if(*ptr_des != *ptr_src) {
+			err = 1;
+			break;
+		}
+		ptr_des++;
+		ptr_src++;
+	}
+	tick2 = get_ticks();
+	d_printf("tick2: %llu\n",tick2);
+	tick1 = (tick2 > tick1)?(tick2 - tick1):(tick1 - tick2);
+	d_printf("tick2 - tick1: %llu\n",tick1);
+	printf("\n\ncost time: %llu us\n",TIME_TICK_TO_US(tick1));
+	count++;
+	/* print result message */
+	if(err != 0) {
+		printf("ddr memory copy test error.	times: %d\t,position: %d\n",count,nword-n);
+		return -1;
+	} else {
+		printf("ddr memory copy test success.	times: %d\t\n",count);
+	}
+	/* check loop */
+	if(count < times)
+		goto LAB_COPY;
+	return 0;
+}
+#endif
diff --git a/board/rda/common/gic_test.c b/board/rda/common/gic_test.c
new file mode 100644
index 0000000000..78a7311a92
--- /dev/null
+++ b/board/rda/common/gic_test.c
@@ -0,0 +1,422 @@
+#include <common.h>
+#include <asm/arch/cs_types.h>
+#include <asm/arch/global_macros.h>
+#include <asm/arch/reg_sysctrl.h>
+#include "rda_gic.h"
+
+#define GIC_TEST_DEBUG
+
+#ifdef GIC_TEST_DEBUG
+#define d_printf printf
+#else
+#define d_printf(...) do{}while(0)
+#endif
+
+#define n_printf printf
+
+#define RW_DELAY	10000
+
+#define readl(addr)	(*((volatile unsigned int *)(addr)))
+#define writel(val,addr) (*((volatile unsigned int *)(addr)) = (val))
+
+static int g_irq_num = 0;
+static int g_cpu_num = 0;
+static int read_gic_type(void);
+static void soft_dly(unsigned int);
+
+static int read_gic_type(void)
+{
+	unsigned int reg,security_ext,it_num,cpu_num;
+
+	reg = readl(RDA_GICD_BASE + GIC_DIST_CTR);
+	d_printf("CPU CTR reg is %x\n",reg);
+	security_ext = (reg >> 10) & 0x1;
+	it_num = ((reg & 0x1F) + 1 ) * 32;
+	cpu_num = ((reg >> 5) & 0x7) + 1;
+	g_irq_num = it_num;
+	g_cpu_num = cpu_num;
+	if(security_ext)
+		n_printf("have security extension,");
+	else
+		n_printf("no security extension,");
+	n_printf("irq number: %d, cpu number: %d\n",it_num,cpu_num);
+	if((it_num > 0) && (it_num < 1020))
+		return 0;
+	else
+		return -1;
+}
+
+static void soft_dly(unsigned int n)
+{
+	while(n--);
+}
+
+void show_cpu_if_info(void)
+{
+	unsigned int reg,ver_minor,ver_major,vid;
+	reg = readl(RDA_GICC_BASE + GIC_CPU_IID);
+	d_printf("CPU IID reg is %x\n",reg);
+	vid = 0x0FFF & reg;
+	ver_minor = (reg >> 12) & 0xF;
+	ver_major = (reg >> 16) & 0xF;
+	if(vid != VID_ARM) {
+		n_printf("unknown vendor id %x\n",vid);
+		return;
+	}
+	n_printf("CPU INTERFACE: ARM,vendor id: %x, version number: %x.%x\n",
+			vid,ver_major,ver_minor);
+}
+
+void show_dist_info(void)
+{
+	unsigned int reg,ver_major,ver_minor,vid;
+	reg = readl(RDA_GICD_BASE + GIC_DIST_IID);
+	d_printf("DIST IID reg is %x\n",reg);
+	vid = 0x0FFF & reg;
+	ver_minor = (reg >> 12) & 0xF;
+	ver_major = (reg >> 16) & 0xF;
+	if(vid != VID_ARM) {
+		n_printf("unknown vendor id %x\n",vid);
+		return;
+	}
+	n_printf("DISTRIBUTOR: ARM,vendor id: %x, version number: %x.%x\n",
+			vid,ver_major,ver_minor);
+}
+
+void gic_simple_init(void)
+{
+	int icfg_num;
+	int itarget_num;
+	int ipri_num;
+	int isen_num;
+	int icpend_num;
+	int i;
+	unsigned int addr,val;
+
+	/* get irq number and cpu number */
+	if(read_gic_type()) {
+		n_printf("read gic type error! irq number is %d\n",g_irq_num);
+		return;
+	}
+	icfg_num = g_irq_num * 2 / 32;
+	itarget_num = g_irq_num * 8 / 32;
+	ipri_num = g_irq_num * 8 / 32;
+	isen_num = g_irq_num / 32;
+	icpend_num = g_irq_num / 32;
+
+	d_printf("icfg_num = %d,itarget_num = %d,ipri_num = %d,isen_num = %d,icpend_num = %d\n",
+			icfg_num,itarget_num,ipri_num,isen_num,icpend_num);
+
+	/* disable distrabutor */
+	writel(0x0,RDA_GICD_BASE + GIC_DIST_CTRL);
+	d_printf("dist ctrl = %x\n",readl(RDA_GICD_BASE + GIC_DIST_CTRL));
+
+	/* disable all PPI interrups,enable all SGI,SPI interrups */
+	writel(0xFFFF0000,RDA_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
+	soft_dly(RW_DELAY);
+	writel(0x0000FFFF,RDA_GICD_BASE + GIC_DIST_ENABLE_SET);
+	soft_dly(RW_DELAY);
+	val = readl(RDA_GICD_BASE + GIC_DIST_ENABLE_SET);
+	d_printf("ien %x = %x\n",RDA_GICD_BASE + GIC_DIST_ENABLE_SET,val);
+	for(i = 1;i < isen_num;i++) {
+		addr = RDA_GICD_BASE + GIC_DIST_ENABLE_SET + i * 4;
+		writel(0xFFFFFFFF,addr);
+		soft_dly(RW_DELAY);
+		val = readl(addr);
+		d_printf("ien %x = %x\n",addr,val);
+	}
+	/* set SPIs irq trigger mode, 0: high level sensitive,1:edge triggered */
+	for(i = 2;i < icfg_num;i++){
+		addr = RDA_GICD_BASE + GIC_DIST_CONFIG + i * 4;
+		writel(0,addr);
+		soft_dly(RW_DELAY);
+		val = readl(addr);
+		d_printf("icfg %x = %x\n",addr,val);
+	}
+	/* set SGIs irq target cpu0 */
+	for(i = 0;i < 4;i++) {
+		addr = RDA_GICD_BASE + GIC_DIST_TARGET + i * 4;
+		writel(0x0,addr);
+		soft_dly(RW_DELAY);
+		val = readl(addr);
+		d_printf("itarget %x = %x\n",addr,val);
+	}
+	/* set PPIs irq target cpu0 */
+	for(i = 4;i < 8;i++) {
+		addr = RDA_GICD_BASE + GIC_DIST_TARGET + i * 4;
+		writel(0x0,addr);
+		soft_dly(RW_DELAY);
+		val = readl(addr);
+		d_printf("itarget %x = %x\n",addr,val);
+	}
+	/* set SPIs irq target cpu0 */
+	for(i = 8;i < itarget_num;i++) {
+		addr = RDA_GICD_BASE + GIC_DIST_TARGET + i * 4;
+		writel(0x0,addr);
+		soft_dly(RW_DELAY);
+		val = readl(addr);
+		d_printf("itarget %x = %x\n",addr,val);
+	}
+	/* set irq priority,0 is the highest priority */
+	for(i = 0;i < ipri_num;i++){
+		addr = RDA_GICD_BASE + GIC_DIST_PRI + i * 4;
+		writel(0x0,addr);
+		soft_dly(RW_DELAY);
+		val = readl(addr);
+		d_printf("ipri %x = %x\n",addr,val);
+	}
+	/* clear all pending IRQs */
+	for(i = 0;i < icpend_num;i++) {
+		addr = RDA_GICD_BASE + GIC_DIST_PENDING_CLEAR + i * 4;
+		writel(0xFFFFFFFF,addr);
+		soft_dly(RW_DELAY);
+	}
+	/* clear all active IRQs */
+	for(i = 0;i < icpend_num;i++) {
+		addr = RDA_GICD_BASE + GIC_DIST_ACTIVE_CLEAR + i * 4;
+		writel(0xFFFFFFFF,addr);
+		soft_dly(RW_DELAY);
+	}
+	/* enable cpu interface */
+	writel(0x3,RDA_GICC_BASE + GIC_CPU_CTRL);
+	soft_dly(RW_DELAY);
+	val = readl(RDA_GICC_BASE + GIC_CPU_CTRL);
+	d_printf("cpu ctrl= %x\n",val);
+	/* set cpu interface priority mask,all irq can be sent to CPU */
+	writel(0xFF,RDA_GICC_BASE + GIC_CPU_PRIMASK);
+	soft_dly(RW_DELAY);
+	val = readl(RDA_GICC_BASE + GIC_CPU_PRIMASK);
+	d_printf("cpu mask = %x\n",val);
+	/* enable distrabutor */
+	writel(0x3,RDA_GICD_BASE + GIC_DIST_CTRL);
+	soft_dly(RW_DELAY);
+	val = readl(RDA_GICD_BASE + GIC_DIST_CTRL);
+	d_printf("dist ctrl = %x\n",val);
+	d_printf("\n\n");
+}
+
+void test_enable_irq(void)
+{
+	unsigned int mask,val,addr;
+	int i,j = 0;
+
+	n_printf("\n\n");
+	/* disable dist */
+	writel(0x0,RDA_GICD_BASE + GIC_DIST_CTRL);
+	/* disable all irq */
+	for(addr = 0x180;addr < 0x200; addr +=4) {
+		writel(0xFFFFFFFF,RDA_GICD_BASE + addr);
+	}
+	/* enable irq */
+	for(addr = 0x100;addr < 0x180; addr +=4) {
+		n_printf("reg %x enable test starts.\n",addr);
+		for(i = 0;i < 32;i++) {
+			val = 1 << i;
+			mask = val;
+			writel(val,RDA_GICD_BASE + addr);
+			soft_dly(RW_DELAY);
+			val = readl(RDA_GICD_BASE + addr);
+			if(val & mask) {
+				n_printf("bit %d enable operation success !!!\n",i);
+				j++;
+			}
+		}
+		n_printf("reg %x enable test finished.\n\n",addr);
+	}
+	/* disable all irq */
+	for(addr = 0x180;addr < 0x200; addr +=4) {
+		writel(val,RDA_GICD_BASE + addr);
+	}
+	n_printf(" %d IRQs enable operation test success !!!\n",j);
+}
+
+void test_disable_irq(void)
+{
+	unsigned int mask,val,addr;
+	int i,j = 0;
+
+	n_printf("\n\n");
+	writel(0x0,RDA_GICD_BASE + GIC_DIST_CTRL);
+
+	/* 0~15 SGIs is allways enabled */
+	addr = 0x180;
+	n_printf("reg %x disable test starts\n",addr);
+	for(i = 0;i < 16;i++) {
+		val = 1 << i;
+		mask = val;
+		writel(val,RDA_GICD_BASE + addr);
+		soft_dly(RW_DELAY);
+		val = readl(RDA_GICD_BASE + addr);
+		if((val & mask) != 0) {
+			n_printf("bit %d disable operation success !!!\n",i);
+		} else {
+			n_printf("bit %d disable operation failed ###\n",i);
+			j++;
+		}
+	}
+	/* 16~24 is unused, 25~31 PPIs is normally used */
+	addr = 0x180;
+	n_printf("reg %x disable test starts\n",addr);
+	for(i = 25;i < 32;i++) {
+		val = 1 << i;
+		mask = val;
+		writel(val,RDA_GICD_BASE + addr);
+		soft_dly(RW_DELAY);
+		val = readl(RDA_GICD_BASE + addr);
+		if((val & mask) == 0) {
+			n_printf("bit %d disable operation success !!!\n",i);
+		} else {
+			n_printf("bit %d disable operation failed ###\n",i);
+			j++;
+		}
+	}
+	/* 32~95 SGIs is normally used */
+	for(addr = 0x184;addr < 0x200; addr +=4) {
+		n_printf("reg %x disable test starts\n",addr);
+		for(i = 0;i < 32;i++) {
+			val = 1 << i;
+			mask = val;
+			writel(val,RDA_GICD_BASE + addr);
+			soft_dly(RW_DELAY);
+			val = readl(RDA_GICD_BASE + addr);
+			if((val & mask) == 0) {
+				if(addr < 0x18C)
+					n_printf("bit %d disable operation success !!!\n",i);
+			} else {
+				n_printf("bit %d disable operation failed ###\n",i);
+				j++;
+			}
+		}
+		n_printf("reg %x disable test finished\n\n",addr);
+	}
+	n_printf(" %d IRQs disable operation test failed.\n",j);
+}
+
+/*******************************************************************************
+ *	@name:		gic_simple_test
+ *	@param:		void
+ *	@return:	void
+ *	@descipt:
+ *		This simple test would pend some interrupts and GIC forward
+ *		these signals to CPU, once CPU recognize it,a IRQ is occured
+ *		and it jump into do_irq() to process this event;
+ *		This simple test will pend all SPIs interrupts and PPIs
+ *		interrupts.
+ ******************************************************************************
+ */
+void gic_simple_test(void)
+{
+	unsigned int reg_idx,reg_pos,reg_active,reg_pend;
+	int i,j,err,irq_id;
+
+	/* Start to test SPIs IRQs */
+	mdelay(10);
+	n_printf("\nstart %d SPIs interrupts test ...\n\n",(g_irq_num-32));
+	j = 0;
+	err = 0;
+	/* enable all SPIs */
+	writel(0xFFFFFFFF,RDA_GICD_BASE + GIC_DIST_ENABLE_SET + 4);
+	writel(0xFFFFFFFF,RDA_GICD_BASE + GIC_DIST_ENABLE_SET + 8);
+	/* pending SPIs */
+	for(i = 32;i < g_irq_num;i++) {
+		j = 1 << (i % 32);
+		reg_idx = (i / 32 + 1) * 4;
+		reg_pos = j;
+		irq_id = i + 32;
+		if(irq_id == g_irq_num)
+			break;
+		reg_active = readl(RDA_GICD_BASE + GIC_DIST_ACTIVE_SET + reg_idx);
+		reg_pend   = readl(RDA_GICD_BASE + GIC_DIST_PENDING_SET + reg_idx);
+		n_printf("pending before, pend state: %x, active state: %x\n",
+				(reg_active & reg_pos),(reg_pend & reg_pos));
+
+		n_printf("pending irq and waiting for it occur ... id is %d\n",irq_id);
+		writel(j,RDA_GICD_BASE + GIC_DIST_PENDING_SET + reg_idx);
+		mdelay(200);
+
+		reg_active = readl(RDA_GICD_BASE + GIC_DIST_ACTIVE_SET + reg_idx);
+		reg_pend   = readl(RDA_GICD_BASE + GIC_DIST_PENDING_SET + reg_idx);
+		n_printf("pending after, pend state: %x, active state: %x\n",
+				(reg_active & reg_pos),(reg_pend & reg_pos));
+		if(reg_pend & reg_pos) {
+			writel(j,RDA_GICD_BASE + GIC_DIST_PENDING_CLEAR + reg_idx);
+			n_printf("error! CPU do not response the IRQ which id is %d\n",irq_id);
+			err++;
+		}
+		n_printf("\n");
+	}
+	if(err)
+		n_printf("all SPI irq test finished, have %d irq errors\n",err);
+	else
+		n_printf("all SPI irq test success !\n");
+
+	/* Start to test PPIs IRQs */
+	mdelay(10);
+	n_printf("\nstart %d PPIs interrupts test ...\n\n",15);
+	j = 0;
+	err = 0;
+	/* enable PPIs */
+	writel(0xFFFF0000,RDA_GICD_BASE + GIC_DIST_ENABLE_SET);
+	/* pending PPIs */
+	for(i = 16;i < 32;i++) {
+		j = 1 << (i % 32);
+		reg_idx = (i / 32 + 0) * 4;
+		reg_pos = j;
+		irq_id = i;
+		/* the PPI 16 ~ 24 is not available */
+		if((irq_id >= 16) && ( irq_id <= 24)) {
+			continue;
+		}
+		reg_active = readl(RDA_GICD_BASE + GIC_DIST_ACTIVE_SET + reg_idx);
+		reg_pend   = readl(RDA_GICD_BASE + GIC_DIST_PENDING_SET + reg_idx);
+		n_printf("pending before, pend state: %x, active state: %x\n",
+				(reg_active & reg_pos),(reg_pend & reg_pos));
+
+		n_printf("pending irq and waiting for it occur ... id is %d\n",irq_id);
+		writel(j,RDA_GICD_BASE + GIC_DIST_PENDING_SET + reg_idx);
+		mdelay(200);
+
+		reg_active = readl(RDA_GICD_BASE + GIC_DIST_ACTIVE_SET + reg_idx);
+		reg_pend   = readl(RDA_GICD_BASE + GIC_DIST_PENDING_SET + reg_idx);
+		n_printf("pending after, pend state: %x, active state: %x\n",
+				(reg_active & reg_pos),(reg_pend & reg_pos));
+		if(reg_pend & reg_pos) {
+			writel(j,RDA_GICD_BASE + GIC_DIST_PENDING_CLEAR + reg_idx);
+			n_printf("error! CPU do not response the IRQ which id is %d\n",irq_id);
+			err++;
+		}
+		d_printf("\n");
+	}
+	/* disable PPIs */
+	writel(0xFFFF0000,RDA_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
+	if(err)
+		n_printf("all PPI irq test finished, have %d irq errors\n",err);
+	else
+		n_printf("all PPI irq test success !\n");
+}
+
+void gic_test_entry(void)
+{
+	n_printf("entry gic test\n");
+	show_dist_info();
+	show_cpu_if_info();
+	gic_simple_init();
+	gic_simple_test();
+	test_enable_irq();
+	test_disable_irq();
+	mdelay(1000);
+	n_printf("delay 1 second ...\n");
+	mdelay(1000);
+}
+
+int gic_test(int times)
+{
+	int n = 0;
+	while(n < times) {
+		n++;
+		n_printf("\ngic_test: %d / %d\n",n,times);
+		gic_test_entry();
+		n_printf("\ngic_test end\n");
+	}
+	return 0;
+}
diff --git a/board/rda/common/hal_camera.c b/board/rda/common/hal_camera.c
new file mode 100644
index 0000000000..0646dccd26
--- /dev/null
+++ b/board/rda/common/hal_camera.c
@@ -0,0 +1,639 @@
+////////////////////////////////////////////////////////////////////////////////
+//																			//
+//			Copyright (C) 2012-2022, RDA, Inc.			//
+//							All Rights Reserved							 //
+//																			//
+//	  This source code is the property of Coolsand Technologies and is	  //
+//	  confidential.  Any  modification, distribution,  reproduction or	  //
+//	  exploitation  of  any content of this file is totally forbidden,	  //
+//	  except  with the  written permission  of RDA.	  //
+//																			//
+////////////////////////////////////////////////////////////////////////////////
+
+#include <common.h>
+#include <asm/arch/cs_types.h>
+#include <asm/arch/reg_camera.h>
+
+#include "hal_camera.h"
+#include "hal_gpio.h"
+
+#include <asm/arch/reg_ifc.h>
+#include <asm/arch/ifc.h>
+#include <asm/arch/reg_cfg_regs.h>
+
+#ifdef TGT_CAMERA_PDN_CHANGE_WITH_ATV
+extern BOOL IsAtvPowerOn(void);
+#endif
+
+VOID hal_print(UINT32 x)
+{
+	 printf("%x\n", (unsigned int)x);
+}
+#define hal_HstSendEvent(x) hal_print(x)
+
+#define HAL_ASSERT(...)
+#define HAL_TRACE(...)
+
+#define CAMERA_DEBUG(BOOL, mess)				   \
+	if (!(BOOL)) {			\
+		printf("%s\n",mess);							 \
+	}
+
+
+// ============================================================================
+// MACROS
+// ============================================================================
+//
+/// Flag to enable the Camera Module test mode. This is useful when the
+/// Debug Bus needs to be used: the Camera Bus and the Debug Bus are
+/// multiplexed in the chip IOMux, so they cannot be used both at same
+/// time. The idea of the Camera test mode is to displays a dummy image
+/// instead of getting its data from the sensor.
+/// So, when CT_RELEASE=cool_profile, the test mode is enabled: the PXTS,
+/// EXL or signal spy cannot be used along with the Camera. When the camera
+/// needs to be used, use CT_RELEASE=debug, for instance.
+#ifdef ENABLE_PXTS
+#define CAM_TEST_MODE	 CAMERA_TEST
+#else
+#define CAM_TEST_MODE	 0 // CAMERA_TEST
+#endif
+
+#ifdef HAL_CAMERA_PRINTF
+#define HAL_CAMERA_TRACE(a, ...)	HAL_TRACE(HAL_CAMERA_TRC, 0, a, ##__VA_ARGS__)
+#else
+#define HAL_CAMERA_TRACE(a, ...)
+#endif
+// ============================================================================
+// GLOBAL VARIABLES
+// ============================================================================
+
+PRIVATE UINT8  g_halCameraIfcChan  = 0xff;
+
+PRIVATE HAL_CAMERA_CFG_T g_halCameraConfig = {
+	.rstActiveH = FALSE,
+	.pdnActiveH = TRUE,
+	.dropFrame  = FALSE,
+	.camClkDiv  = 12,
+	.endianess  = BYTE_SWAP,
+	.camId	  = 0,
+	.colRatio   = COL_RATIO_1_1,
+	.rowRatio   = ROW_RATIO_1_1,
+	.camPdnRemap.gpioId=HAL_GPIO_NONE,
+	.camRstRemap.gpioId=HAL_GPIO_NONE,
+};
+
+
+// =============================================================================
+// g_halCameraIrqHandler
+// -----------------------------------------------------------------------------
+/// Variable to store the user irq handler for the camera
+/// interruption.
+// =============================================================================
+PRIVATE HAL_CAMERA_IRQ_HANDLER_T g_halCameraIrqHandler;
+
+PUBLIC VOID hal_CameraSetVsyncInvert(BOOL polarity)
+{
+	if (polarity){
+		// VSYNC low effective
+		hwp_camera->CTRL |= CAMERA_VSYNC_POL_INVERT;
+#if (CHIP_HAS_ASYNC_TCU)
+		hwp_camera->CAM_SPI_REG_0 |= CAM_SPI_REG_VSYNC_INV_EN;
+#endif // defined (CHIP_HAS_ASYNC_TCU)
+	} else{
+		// VSYNC high effective
+		hwp_camera->CTRL &= ~CAMERA_VSYNC_POL_INVERT;
+#if (CHIP_HAS_ASYNC_TCU)
+		hwp_camera->CAM_SPI_REG_0 &= ~CAM_SPI_REG_VSYNC_INV_EN;
+#endif // defined (CHIP_HAS_ASYNC_TCU)
+	}
+}
+PUBLIC UINT32 hal_CameraIrqstatus(void)
+{
+	return hwp_camera->STATUS;
+}
+
+// ============================================================================
+// FUNCTIONS
+// ============================================================================
+
+// =============================================================================
+// hal_CameraReset(BOOL InReset)
+// -----------------------------------------------------------------------------
+/// Puts the Camera sensor in Reset or out of Reset.
+///
+/// @param InReset if true, put the external camera sensor in reset
+// =============================================================================
+PUBLIC VOID hal_CameraReset(BOOL InReset)
+{
+	if (InReset)
+		hwp_camera->CMD_SET = CAMERA_RESET;
+	else
+		hwp_camera->CMD_CLR = CAMERA_RESET;
+}
+
+#if (CHIP_HAS_ASYNC_TCU)
+PRIVATE VOID hal_camera_spi_reg_init()
+{
+	// clear all SPI camera related regs
+	hwp_camera->CAM_SPI_REG_0 = 0;
+	hwp_camera->CAM_SPI_REG_1 = 0;
+	hwp_camera->CAM_SPI_REG_2 = 0;
+	hwp_camera->CAM_SPI_REG_3 = 0;
+	hwp_camera->CAM_SPI_REG_4 = 0;
+	hwp_camera->CAM_SPI_REG_5 = 0;
+	hwp_camera->CAM_SPI_REG_6 = 0;
+
+	// set all SPI camera related regs to default
+	hwp_camera->CAM_SPI_REG_5 = 0x00ffffff; // sync code 0xffffff by default
+	// by default, frame start id 0x01,frame end id 0x00,line start id 0x02,packet id 0x40
+	hwp_camera->CAM_SPI_REG_6 = 0x01000240;
+}
+#endif
+
+
+void hal_config_pinmux_for_camera(void)
+{
+	hwp_configRegs->AP_GPIO_B_Mode=(hwp_configRegs->AP_GPIO_B_Mode)&(~0x00fffc00);
+}
+
+void hal_config_pinmux_for_camera_csi2(void)
+{
+	hwp_configRegs->Alt_mux_select=((hwp_configRegs->Alt_mux_select)&(~0x00000030))|(1<<4);
+}
+
+PUBLIC VOID hal_CameraOpen(HAL_CAMERA_CFG_T* camConfig)
+{
+	UINT32 decimDiv = 0;
+
+	if (HAL_UNKNOWN_CHANNEL != g_halCameraIfcChan){
+		printf("hal_CameraOpen: Camera already open\n");
+		return;
+	}
+
+	g_halCameraConfig = *camConfig;
+	hal_config_pinmux_for_camera();
+
+	if(camConfig->csi_cs == 1){
+		hal_config_pinmux_for_camera_csi2();
+	}
+
+#if (CHIP_HAS_ASYNC_TCU)
+	HAL_ASSERT(((camConfig->spi_mode == SPI_MODE_MASTER2_1) ||((camConfig->spi_mode == SPI_MODE_MASTER1))
+						|| (camConfig->spi_mode == SPI_MODE_MASTER2_2)
+						|| (camConfig->spi_mode == SPI_MODE_MASTER2_4)
+						|| (camConfig->spi_mode == SPI_MODE_NO)),
+			   "hal_CameraOpen: unsupported spi mode");
+#endif
+
+	switch (camConfig->rowRatio){
+		case ROW_RATIO_1_1:
+			decimDiv |= CAMERA_DECIMROW_ORIGINAL;
+			break;
+		case ROW_RATIO_1_2:
+			decimDiv |= CAMERA_DECIMROW_DIV_2;
+			break;
+		case ROW_RATIO_1_3:
+			decimDiv |= CAMERA_DECIMROW_DIV_3;
+			break;
+		case ROW_RATIO_1_4:
+			decimDiv |= CAMERA_DECIMROW_DIV_4;
+			break;
+		default:
+			HAL_ASSERT(FALSE, "Camera: Wrong row ratio: %d", camConfig->rowRatio);
+			break;
+	}
+
+	switch (camConfig->colRatio){
+		case COL_RATIO_1_1:
+			decimDiv |= CAMERA_DECIMCOL_ORIGINAL;
+			break;
+		case COL_RATIO_1_2:
+			decimDiv |= CAMERA_DECIMCOL_DIV_2;
+			break;
+		case COL_RATIO_1_3:
+			decimDiv |= CAMERA_DECIMCOL_DIV_3;
+			break;
+		case COL_RATIO_1_4:
+			decimDiv |= CAMERA_DECIMCOL_DIV_4;
+			break;
+		default:
+			HAL_ASSERT(FALSE, "Camera: Wrong column ratio: %d", camConfig->colRatio);
+			break;
+	}
+	hwp_camera->CTRL  = CAM_TEST_MODE;
+	hwp_camera->CTRL |= CAMERA_DATAFORMAT_YUV422;
+	hwp_camera->CTRL |= decimDiv;
+
+	if (camConfig->cropEnable)
+	{
+		hwp_camera->CTRL |= CAMERA_CROPEN_ENABLE;
+		hwp_camera->DSTWINCOL =
+			CAMERA_DSTWINCOLSTART(camConfig->dstWinColStart) |CAMERA_DSTWINCOLEND(camConfig->dstWinColEnd);
+		hwp_camera->DSTWINROW =
+			CAMERA_DSTWINROWSTART(camConfig->dstWinRowStart) |CAMERA_DSTWINROWEND(camConfig->dstWinRowEnd);
+	}
+
+	if(!g_halCameraConfig.rstActiveH)
+		hwp_camera->CTRL |= CAMERA_RESET_POL;
+	if(!g_halCameraConfig.pdnActiveH)
+		hwp_camera->CTRL |= CAMERA_PWDN_POL;
+	if (g_halCameraConfig.dropFrame)
+		hwp_camera->CTRL |= CAMERA_DECIMFRM_DIV_2;
+
+	hwp_camera->CTRL |= CAMERA_REORDER(camConfig->reOrder);
+
+#if (CHIP_HAS_ASYNC_TCU)
+	hal_camera_spi_reg_init();
+	if ((camConfig->spi_mode != SPI_MODE_NO)&&((camConfig->csi_mode == FALSE))){
+		// CAM_SPI_REG_0
+		hwp_camera->CAM_SPI_REG_0
+					|= CAM_SPI_REG_LINE_PER_FRM(camConfig->spi_pixels_per_column);
+		hwp_camera->CAM_SPI_REG_0
+					|= CAM_SPI_REG_BLK_PER_LINE((camConfig->spi_pixels_per_line) >> 1);
+		hwp_camera->CAM_SPI_REG_0
+					|= CAM_SPI_REG_YUV_OUT_FMT(camConfig->spi_yuv_out);
+		hwp_camera->CAM_SPI_REG_0
+					|= (camConfig->spi_href_inv) ? CAM_SPI_REG_HREF_INV_EN : 0;
+		hwp_camera->CAM_SPI_REG_0
+					|= (camConfig->spi_little_endian_en) ? CAM_SPI_REG_LITTLE_END_EN : 0;
+		// CAM_SPI_REG_1
+		hwp_camera->CAM_SPI_REG_1 |= CAM_SPI_REG_CLK_DIV(camConfig->spi_ctrl_clk_div);
+		// Other REGs according to the spi mode
+		switch (camConfig->spi_mode){
+		case SPI_MODE_MASTER2_1:
+			hwp_camera->CAM_SPI_REG_4 |=
+						CAM_SPI_REG_BLK_PER_PACK((camConfig->spi_pixels_per_line) >> 1) |
+						CAM_SPI_REG_LINE(0) |
+						CAM_SPI_REG_PACK_SIZE_FROM_REG |
+						CAM_SPI_REG_IMG_WIDTH_FROM_REG |
+						CAM_SPI_REG_IMG_HEIGHT_FROM_REG |
+						CAM_SPI_REG_MASTER2_EN;
+			break;
+		case SPI_MODE_MASTER2_2:
+			hwp_camera->CAM_SPI_REG_4 |=
+						CAM_SPI_REG_BLK_PER_PACK((camConfig->spi_pixels_per_line) >> 1) |
+						CAM_SPI_REG_LINE(1) |
+						CAM_SPI_REG_PACK_SIZE_FROM_REG |
+						CAM_SPI_REG_IMG_WIDTH_FROM_REG |
+						CAM_SPI_REG_IMG_HEIGHT_FROM_REG |
+						CAM_SPI_REG_MASTER2_EN;
+			break;
+		case SPI_MODE_MASTER2_4:
+			hwp_camera->CAM_SPI_REG_4 |=
+						CAM_SPI_REG_BLK_PER_PACK((camConfig->spi_pixels_per_line) >> 1) |
+						CAM_SPI_REG_LINE(2) |
+						CAM_SPI_REG_PACK_SIZE_FROM_REG |
+						CAM_SPI_REG_IMG_WIDTH_FROM_REG |
+						CAM_SPI_REG_IMG_HEIGHT_FROM_REG |
+						CAM_SPI_REG_MASTER2_EN;
+			break;
+	   case SPI_MODE_MASTER1:
+			hwp_camera->CAM_SPI_REG_0 |= CAM_SPI_REG_MASTER_EN;
+			if (camConfig->spi_ssn_high_en)
+				hwp_camera->CAM_SPI_REG_1 |=  CAM_SPI_REG_SSN_HIGH_EN;
+			break;
+		default:
+			break;
+		}
+	}
+#endif // defined (CHIP_HAS_ASYNC_TCU)
+
+	if (camConfig->csi_mode == TRUE){
+		hwp_camera->CAM_SPI_REG_0 = 0x200;
+
+		//hwp_mipi_csi->CSI_OBSERVE_CLK = 0x1;
+		serial_puts("set csi reg  \r\n");
+		hwp_camera->CSI_CONFIG_REG0 =0xA0000000|(camConfig->num_d_term_en&0xff)|((camConfig->frame_line_number&0x3ff)<<8);
+		hwp_camera->CSI_CONFIG_REG1 = 0x00020000|(camConfig->num_hs_settle&0xff);
+		hwp_camera->CSI_CONFIG_REG2= (camConfig->num_c_term_en<<16)|camConfig->num_c_hs_settle;//; //;//;/
+		hwp_camera->CSI_CONFIG_REG3= 0x9C0A0000|((camConfig->csi_cs&1)<<20)|(camConfig->csi_lane_2v8<<11);//0x9c0a0800; for csi1  0x9c1a***  for csi2
+		hwp_camera->CSI_CONFIG_REG4= 0xffffffff;
+		hwp_camera->CSI_CONFIG_REG5= 0x40dc4000;
+		hwp_camera->CSI_CONFIG_REG6= 0x800420ea;
+		hwp_camera->CSI_ENABLE_PHY = 1;
+
+		hal_HstSendEvent(0x12346666);
+	}
+
+	// Configure Camera Clock Divider
+	hal_CameraSetupClockDivider(g_halCameraConfig.camClkDiv);
+	// set vsync pole
+	hal_CameraSetVsyncInvert(camConfig->vsync_inv);
+
+	//  hwp_camera->CTRL |= (1<<31);  //  rda test mode
+
+	hal_CameraReset(FALSE);
+	hal_CameraPowerDown(FALSE);
+}
+
+
+// =============================================================================
+// hal_CameraClose
+// -----------------------------------------------------------------------------
+/// Power off the camera sensor by setting the PowerDown bit.
+/// Resets the camera sensor by enabling the Camera Reset bit.
+/// This function can only be called after the camera transfer has been stopped
+/// by a call to #hal_CameraStopXfer().
+// =============================================================================
+PUBLIC VOID hal_CameraClose(VOID)
+{
+	hal_CameraControllerEnable(FALSE);
+	hal_CameraReset(TRUE);
+	hal_CameraPowerDown(TRUE);
+}
+
+PUBLIC VOID hal_CameraPowerDownBoth(BOOL PowerDown)
+{
+
+}
+
+PUBLIC VOID hal_CameraClkOut(BOOL out)
+{
+	if (out)
+		hwp_camera->CLK_OUT = 0x11;
+	else
+		hwp_camera->CLK_OUT = 0x3f00;
+
+	return;
+}
+
+// // 0x11 = 13M   0x1 = 30M
+PUBLIC VOID hal_SetCameraClkOut(u16 value)
+{
+	hwp_camera->CLK_OUT = value;
+}
+
+PUBLIC VOID hal_CameraPowerDown(BOOL PowerDown)
+{
+	if(PowerDown){
+		hwp_camera->CMD_SET = CAMERA_PWDN;
+	}else{
+		hwp_camera->CMD_CLR = CAMERA_PWDN;
+	}
+
+	return;
+}
+
+
+// =============================================================================
+// hal_CameraControllerEnable(BOOL enable)
+// -----------------------------------------------------------------------------
+// =============================================================================
+PUBLIC VOID hal_CameraControllerEnable(BOOL enable)
+{
+	if(enable){
+		// Turn on controller and apbi
+		hwp_camera->CMD_SET  =  CAMERA_FIFO_RESET;
+		hwp_camera->CTRL	|=  CAMERA_DATAFORMAT_YUV422;
+		hwp_camera->CTRL	|=  CAMERA_ENABLE;
+	} else{
+		// Turn off controller and apbi
+		hwp_camera->CTRL	&= ~CAMERA_ENABLE;
+	}
+}
+
+PUBLIC VOID hal_CameraIrqSetHandler(HAL_CAMERA_IRQ_HANDLER_T handler)
+{
+	g_halCameraIrqHandler = handler;
+}
+
+
+
+// =============================================================================
+// hal_CameraIrqConfig()
+// -----------------------------------------------------------------------------
+/// Configure the desired interrupts
+///
+/// @param mask Mask to enable specific interrupts.  Valid interrupts are
+/// liste in HAL_CAMERA_IRQ_CAUSE_T.
+// =============================================================================
+PUBLIC VOID hal_CameraIrqSetMask(HAL_CAMERA_IRQ_CAUSE_T mask)
+{
+	UINT32 realMask = 0;
+
+	if (mask.overflow)
+		realMask |= CAMERA_OVFL;
+
+	if (mask.fstart)
+		realMask |= CAMERA_VSYNC_R;
+
+	if (mask.fend)
+		realMask |= CAMERA_VSYNC_F;
+
+	if (mask.dma)
+		realMask |= CAMERA_DMA_DONE;
+
+	hwp_camera->IRQ_CLEAR = realMask;
+	hwp_camera->IRQ_MASK  = realMask;
+}
+
+PROTECTED VOID hal_CameraIrqHandler(UINT8 interruptId)
+{
+	HAL_CAMERA_IRQ_CAUSE_T cause = {0, };
+	UINT32				 realCause;
+
+	realCause = hwp_camera->IRQ_CAUSE;
+
+	// Clear IRQ
+	hwp_camera->IRQ_CLEAR = realCause;
+
+	if(realCause & CAMERA_OVFL)
+		cause.overflow = 1;
+
+	if(realCause & CAMERA_VSYNC_R)
+		cause.fstart = 1;
+
+	if(realCause & CAMERA_VSYNC_F)
+		cause.fend= 1;
+
+	if(realCause & CAMERA_DMA_DONE)
+		cause.dma = 1;
+
+	// Call User handler
+	if (g_halCameraIrqHandler)
+		g_halCameraIrqHandler(cause);
+}
+
+PUBLIC UINT32 hal_getCameraStatus(HAL_CAMERA_IRQ_CAUSE_T *cause)
+{
+  //  HAL_CAMERA_IRQ_CAUSE_T cause = {0, };
+	UINT32				 realCause;
+
+	realCause = hwp_camera->IRQ_CAUSE;
+	// Clear IRQ
+	hwp_camera->IRQ_CLEAR = realCause;
+
+
+	if(realCause & CAMERA_OVFL)
+		cause->overflow = 1;
+
+	if(realCause & CAMERA_VSYNC_R)
+	  cause->fstart = 1;
+
+	if(realCause & CAMERA_VSYNC_F)
+		cause->fend= 1;
+
+	if(realCause & CAMERA_DMA_DONE)
+		cause->dma = 1;
+
+  	return realCause;
+}
+
+  UINT32 hal_AxiGetTc(void)
+  {
+	   return hwp_camera->CAM_TC_COUNT;
+  }
+
+// =============================================================================
+// hal_CameraStopXfer
+// -----------------------------------------------------------------------------
+/// Must be called at the end of the Frame Capture
+/// If an underflow occured and the IFC tranfer is not complete,
+/// this function will handle the channel release
+///
+/// @param stop If \c TRUE, stops the camera controller.
+/// @return 0 when the IC transfer was complete
+///		 1 when the IFC transfer was not complete and the channel had to be released
+// =============================================================================
+PUBLIC HAL_CAMERA_XFER_STATUS_T hal_CameraStopXfer(BOOL stop)
+{
+	UINT32 tc = 0;
+
+	printf(" stop xfer ");
+	// Disable the Camera controller in any case to avoid toggling
+	if(stop)
+		hal_CameraControllerEnable(FALSE);
+
+	tc = hal_AxiGetTc();
+
+	printf("\r\n ytt   loss  tc =0x ");
+	hal_HstSendEvent(tc);
+
+	if(tc != 0)
+		printf("\r\n---------------- --------------------------------------- \n");
+
+	printf("\r\n receive line = ");
+	hal_HstSendEvent((  640*480*2 - tc )/(640*2));
+	printf("\r\n");
+
+	if(tc != 0){
+
+		if(!stop){
+			hal_CameraControllerEnable(FALSE);
+			hal_CameraControllerEnable(TRUE);
+		}
+
+		// Try to determine why we missed data
+		if(hwp_camera->IRQ_CAUSE & CAMERA_OVFL)
+			printf("Overflow during transfer between camera module and IFC");
+		else
+			printf("Missing data between external camera and camera module");
+
+		return XFER_NOT_FINISHED;
+	}
+
+	if(!(hwp_camera->IRQ_CAUSE & CAMERA_OVFL))
+		return XFER_SUCCESS;
+
+	return(XFER_FINISHED_WITH_OVERFLOW);
+}
+
+
+// =============================================================================
+// hal_CameraStartXfer
+// -----------------------------------------------------------------------------
+/// This function begins the IFC transfer of the camera data.  The camera
+/// itself is reset and the camera module internal fifo is cleared.  The IFC
+/// transfer is then started.
+/// @param BufSize This is the size of the buffer in _bytes_
+/// @param Buffer Pointer to the video buffer where the IFC will store the data.
+/// @return IFC channel number.
+// =============================================================================
+PUBLIC UINT8 hal_CameraStartXfer(UINT32 bufSize, UINT8* buffer)
+{
+	REG32 value ;
+
+	hwp_camera->CMD_SET   =  CAMERA_FIFO_RESET;
+	hwp_camera->IRQ_CLEAR = CAMERA_OVFL;	   // Clear the Overflow bit for checking later
+	//  g_halCameraIfcChan	= hal_IfcTransferStart(HAL_IFC_CAMERA_RX, buffer, bufSize, HAL_IFC_SIZE_32_MODE_AUTO);
+	//   HAL_CAMERA_TRACE("hal_CameraStartXfer: channel %i", g_halCameraIfcChan);
+	hwp_camera->CAM_FRAME_START_ADDR   =(UINT32)  buffer;
+	hwp_camera->CAM_FRAME_SIZE   =  bufSize;
+	hwp_camera->CAM_AXI_CONFIG =( hwp_camera->CAM_AXI_CONFIG)|0x20;
+	value = hwp_camera->CAM_AXI_CONFIG;
+	printf("cam: 2013 hal_CameraStartXfer	  \r\n");
+	hal_HstSendEvent((UINT32)bufSize);
+	hal_HstSendEvent((UINT32)value);
+	printf("\n");
+
+	return 1;
+}
+
+// =============================================================================
+// hal_CameraWaitXferFinish
+// -----------------------------------------------------------------------------
+///if IFC transfer not finish, do nothg.
+/// @return 0 when the IC transfer was complete
+///		 1 when the IFC transfer was not complete
+// =============================================================================
+
+PUBLIC HAL_CAMERA_XFER_STATUS_T hal_CameraWaitXferFinish(void)
+{
+	return XFER_SUCCESS;
+}
+
+// =============================================================================
+// hal_CameraSetupClockDivider
+// -----------------------------------------------------------------------------
+// =============================================================================
+PUBLIC VOID hal_CameraSetupClockDivider(UINT8 divider)
+{
+
+
+#if 0 // ytt-temp
+	UINT32 newClkScale;
+	UINT32 ctrlReg;
+
+	// Save enable bit
+	ctrlReg = hwp_sysCtrl->Cfg_Clk_Camera_Out & SYS_CTRL_CLK_CAMERA_OUT_EN_ENABLE;
+
+	// Saturate the divider to the maximum value supported
+	// by the hardware.
+	if(divider-2 > (SYS_CTRL_CLK_CAMERA_OUT_DIV_MASK>>SYS_CTRL_CLK_CAMERA_OUT_DIV_SHIFT))
+	{
+		newClkScale = (SYS_CTRL_CLK_CAMERA_OUT_DIV_MASK>>SYS_CTRL_CLK_CAMERA_OUT_DIV_SHIFT) + 2;
+	}
+	else if(divider < 2)
+	{
+		newClkScale = 2;
+	}
+	else
+	{
+		newClkScale = divider;
+	}
+
+	// Divider is register value+2, so we take off 2 here.
+	ctrlReg |=  SYS_CTRL_CLK_CAMERA_DIV_SRC_SEL_156_MHZ	  |
+				SYS_CTRL_CLK_CAMERA_OUT_SRC_SEL_FROM_DIVIDER |
+				SYS_CTRL_CLK_CAMERA_OUT_DIV(newClkScale-2)
+#if (CHIP_HAS_ASYNC_TCU)
+				| SYS_CTRL_CLK_SPI_CAMERA_DIV(0)
+#endif
+				;
+
+	// Restore initial config with new clock scal.
+	hwp_sysCtrl->Cfg_Clk_Camera_Out = ctrlReg;
+#endif
+}
+
+PUBLIC VOID hal_CameraSetLane(UINT8 lane)
+{
+	hwp_camera->CSI_CONFIG_REG3 &= 0x3fffffff;
+
+	if (lane == 1)
+		hwp_camera->CSI_CONFIG_REG3 |= (0x2 << 30);
+	else
+		hwp_camera->CSI_CONFIG_REG3 |= (0x1 << 30);
+}
+
+
diff --git a/board/rda/common/i2c_test.c b/board/rda/common/i2c_test.c
new file mode 100644
index 0000000000..eb0d287ba6
--- /dev/null
+++ b/board/rda/common/i2c_test.c
@@ -0,0 +1,1546 @@
+#include <common.h>
+#include <asm/arch/cs_types.h>
+#include <asm/arch/global_macros.h>
+#include <asm/arch/reg_sysctrl.h>
+#include <asm/arch/reg_spi.h>
+#include <asm/arch/reg_gpio.h>
+#include <asm/arch/reg_cfg_regs.h>
+#include <asm/arch/reg_timer.h>
+#include <asm/arch/reg_i2c.h>
+#include <asm/arch/ispi.h>
+
+#ifdef CONFIG_IRQ
+#include "irq.h"
+#endif
+
+/* I2C debug enable or disable */
+#define rprintf printf
+#define TEST_I2C_DEBUG
+
+#ifdef TEST_I2C_DEBUG
+#define d_printf rprintf
+#else
+#define d_printf(...) do{}while(0)
+#endif
+
+/* TX FIFO size and timeout count */
+#define I2C_TX_FIFO_SIZE (0x1F)
+#define I2C_WAIT_SLOT	 (20)
+#define I2C_WAIT_JITTER	 (10)
+#define I2C_WAIT_COUNT	 (I2C_TX_FIFO_SIZE + I2C_WAIT_JITTER)
+#define I2C_WAIT_TIME	 (I2C_WAIT_SLOT * (I2C_TX_FIFO_SIZE + I2C_WAIT_JITTER))
+
+/* APB2 bus frequency value 200MHz */
+#define APB2_BUS_FREQ_VALUE (200000000)
+
+/* Device address */
+#define I2C_SLAVE_ADDR_TS_MSG2133	(0x60)
+
+//#define I2C_TX_BUF_SIZE	 (0x100)
+//#define I2C_RX_BUF_SIZE	 (0x100)
+
+/* I2C3 and Touch Sensor GPIO PINs */
+#define GPIO_A1	1
+#define GPIO_B2	2
+#define GPIO_B6	6
+#define GPIO_B7	7
+
+#define GPIO_TOUCH_IRQ		GPIO_A1
+#define GPIO_TOUCH_RESET	GPIO_B2
+#define GPIO_TOUCH_SCL		GPIO_B6
+#define GPIO_TOUCH_SDA		GPIO_B7
+
+#define BANK_TOUCH_IRQ		hwp_apGpioA
+#define BANK_TOUCH_RESET	hwp_apGpioB
+#define BANK_TOUCH_SCL		hwp_apGpioB
+#define BANK_TOUCH_SDA		hwp_apGpioB
+#define BANK_PIN_CFG		hwp_configRegs
+
+static int g_i2c_speed = 200;
+#ifdef CONFIG_IRQ
+static int g_i2c_flag_tx_msg_ok = 0;
+static int g_i2c_flag_rx_msg_ok = 0;
+static int g_i2c_flag_tx_msg_err = 0;
+#endif /* CONFIG_IRQ */
+static HWP_I2C_MASTER_T *g_hwp_i2c = hwp_i2cMaster;
+static HWP_I2C_MASTER_T *g_i2c_tab[] = {hwp_i2cMaster,hwp_i2cMaster2,hwp_i2cMaster3};
+
+static void touch_sensor_init(void);
+static void i2c_test_init(void);
+static void i2c_buffer_init(void);
+static void dump_i2c_reg(void);
+static unsigned int get_ticks_x(unsigned int *ptr_high,unsigned int *ptr_low);
+static unsigned int get_ticks_x_x(void);
+
+#ifdef CONFIG_IRQ
+static void i2c_tx_callback(void);
+static void i2c_rx_callback(void);
+#endif /* CONFIG_IRQ */
+
+#if 0
+static HWP_SPI_T *hwp_ispi = hwp_spi3;
+static void ispi_open(int modemSpi);
+static UINT32 ispi_reg_read(UINT32 regIdx);
+static void ispi_reg_write(UINT32 regIdx, UINT32 value);
+#endif
+
+static void i2c_config_clock(int speed_khz)
+{
+	unsigned int clock,clk_div,mclk = APB2_BUS_FREQ_VALUE;
+	unsigned int ctrl_reg;
+
+	clock = speed_khz * 1000;
+	clk_div = mclk / (5 * clock);
+	if(mclk % (5 * clock))
+		clk_div += 1;
+	if(clk_div >= 1)
+		clk_div -= 1;
+	if(clk_div > 0xFFFF)
+		clk_div = 0xFFFF;
+
+	ctrl_reg = g_hwp_i2c->CTRL;
+	ctrl_reg &= (~I2C_MASTER_CLOCK_PRESCALE_MASK);
+	ctrl_reg |= I2C_MASTER_CLOCK_PRESCALE(clk_div);
+
+	g_hwp_i2c->CTRL = 0;
+	g_hwp_i2c->CTRL = ctrl_reg;
+
+	d_printf("ctrl = %x,clk_div = %d,speed = %d Kbps\n"
+			,g_hwp_i2c->CTRL,clk_div,speed_khz);
+}
+
+static void i2c_enable(int enabled)
+{
+	if(enabled){
+		g_hwp_i2c->CTRL |= (I2C_MASTER_EN | (0x3 << 14));
+		g_hwp_i2c->CTRL1 = 0;
+	} else {
+		g_hwp_i2c->CTRL &= (~I2C_MASTER_EN);
+	}
+}
+
+static void i2c_test_init(void)
+{
+	i2c_config_clock(g_i2c_speed);
+	i2c_enable(1);
+}
+
+static void i2c_buffer_init(void)
+{
+#if 0
+	int i;
+	for(i = 0;i < I2C_TX_BUF_SIZE;i++)
+		g_i2c_tx_buf[i] = (unsigned char)i;
+	for(i = 0;i < I2C_RX_BUF_SIZE;i++)
+		g_i2c_rx_buf[i] = (unsigned char)0x5a;
+#endif
+}
+
+static int i2c_tx_byte(unsigned char dat,int start,int stop)
+{
+	unsigned int cmd = I2C_MASTER_WR;
+
+	if(start)
+		cmd |= I2C_MASTER_STA;
+	if(stop)
+		cmd |= I2C_MASTER_STO;
+
+	g_hwp_i2c->TXRX_BUFFER = dat;
+	g_hwp_i2c->CMD = cmd;
+	d_printf("i2c tx data:%2x,cmd:%x\n",dat,cmd);
+	return 0;
+}
+
+static int i2c_rx_byte(unsigned char *buf,int start,int stop)
+{
+	unsigned int cmd = I2C_MASTER_RD;
+
+	if(start)
+		cmd |= I2C_MASTER_STA;
+	if(stop)
+		cmd |= (I2C_MASTER_ACK | I2C_MASTER_STO);
+	g_hwp_i2c->CMD = cmd;
+//	d_printf("i2c_rx_byte, cmd = %x\n",cmd);
+	return 0;
+}
+
+#ifdef CONFIG_IRQ
+static void i2c_enable_irq(int enabled)
+{
+	if(enabled) {
+		g_hwp_i2c->CTRL |= I2C_MASTER_IRQ_MASK;
+	} else {
+		g_hwp_i2c->CTRL &= (~I2C_MASTER_IRQ_MASK);
+	}
+}
+
+static void i2c_enable_irq_tx_fifo_empty(int enabled)
+{
+	if(enabled) {
+		g_hwp_i2c->CTRL1 |= I2C_MASTER_TXFIFO_UNDER_IRQ_MASK;
+		g_hwp_i2c->IRQ_CLR = I2C_MASTER_IRQ_CLR;
+	} else {
+		g_hwp_i2c->CTRL1 &= (~I2C_MASTER_TXFIFO_UNDER_IRQ_MASK);
+	}
+}
+#endif /* CONFIG_IRQ */
+
+static inline void i2c_set_rx_number(unsigned int n)
+{
+	unsigned int reg = g_hwp_i2c->CTRL;
+
+	reg &= (~I2C_MASTER_RX_READ_NUM_MASK);
+	reg |= I2C_MASTER_RX_READ_NUM(n);
+	g_hwp_i2c->CTRL = reg;
+}
+
+static inline int i2c_get_rx_number(void)
+{
+	return (((g_hwp_i2c->STATUS & I2C_MASTER_RX_FIFO_DATA_NUM_MASK) >> 21) & 0x1F);
+}
+
+static inline void i2c_clear_fifo(void)
+{
+	g_hwp_i2c->CTRL |= I2C_MASTER_CLEAR_FIFO;
+	g_hwp_i2c->CTRL &= ~I2C_MASTER_CLEAR_FIFO;
+}
+
+static inline int i2c_get_free_space(void)
+{
+	return (((g_hwp_i2c->STATUS & I2C_MASTER_TX_FIFO_FREE_NUM_MASK) >> 26) & 0x1F);
+}
+
+#if 0
+//#ifdef TEST_I2C_DEBUG
+static int i2c_bus_is_busy(void)
+{
+	unsigned int status;
+	status = (g_hwp_i2c->STATUS &
+			(I2C_MASTER_TIP | I2C_MASTER_BUSY));
+	d_printf("i2c_bus_is_busy, status: %x\n",g_hwp_i2c->STATUS);
+	return status;
+}
+#else
+static inline int i2c_bus_is_busy(void)
+{
+	return (g_hwp_i2c->STATUS & (I2C_MASTER_TIP | I2C_MASTER_BUSY));
+}
+#endif
+
+#if 0
+static inline int i2c_is_tx_fifo_empty(void)
+{
+	return (g_hwp_i2c->STATUS & I2C_MASTER_IRQ_TX_UDF);
+}
+
+static void i2c_stop(void)
+{
+	d_printf("ctrl  : %x\n",g_hwp_i2c->CTRL);
+	d_printf("status: %x\n",g_hwp_i2c->STATUS);
+
+	g_hwp_i2c->CMD = I2C_MASTER_STO | I2C_MASTER_FORCE_STO;
+
+	g_hwp_i2c->CTRL |= I2C_MASTER_CLEAR_FIFO;
+	g_hwp_i2c->CTRL &= ~I2C_MASTER_CLEAR_FIFO;
+
+	d_printf("ctrl  : %x\n",g_hwp_i2c->CTRL);
+	d_printf("status: %x\n",g_hwp_i2c->STATUS);
+	d_printf("i2c stoped\n");
+}
+#endif
+static void dump_i2c_reg(void)
+{
+	rprintf("\n");
+	rprintf("ctrl   :  %x\n",g_hwp_i2c->CTRL);
+	rprintf("ctrl1  :  %x\n",g_hwp_i2c->CTRL1);
+	rprintf("status :  %x\n",g_hwp_i2c->STATUS);
+	rprintf("cmd    :  %x\n",g_hwp_i2c->CMD);
+	rprintf("\n");
+}
+
+void i2c_case_check_register_default_value(void)
+{
+	rprintf("\ncheck register default value ...\n");
+	//TODO: reset i2c
+	rprintf("base addr:   %x\n",(unsigned int)g_hwp_i2c);
+	dump_i2c_reg();
+}
+
+int i2c_test_tx_data_pol(unsigned char addr,const unsigned char *dat,int len)
+{
+	int i;
+	unsigned char temp;
+	static volatile unsigned int timeout = 0;
+
+	rprintf("\ni2c tx data polling test,addr = %x, len = %d\n",
+			(unsigned int)dat,len);
+
+	/* wait until bus is idle */
+	rprintf("clear fifo ...\n");
+	i2c_clear_fifo();
+	rprintf("wait i2c busy until it is idle ...\n");
+	timeout = I2C_WAIT_COUNT;
+	while(g_hwp_i2c->STATUS & (I2C_MASTER_TIP | I2C_MASTER_BUSY)) {
+		if(timeout == 0) {
+			dump_i2c_reg();
+			g_hwp_i2c->CMD = I2C_MASTER_STO | I2C_MASTER_FORCE_STO;
+			rprintf("i2c bus is busy,exit\n");
+			return -1;
+		}
+		udelay(I2C_WAIT_SLOT);
+		timeout--;
+	}
+	/* send first byte: device address,RW = 0 */
+	temp = (addr << 1) & 0xFE;
+	i2c_tx_byte(temp,1,0);
+	/* send data byte array */
+	for(i = 0;i < len - 1;i++) {
+		while(i2c_get_free_space() == 0);
+		i2c_tx_byte(dat[i],0,0);
+	}
+	/* send last byte */
+	i2c_tx_byte(dat[len-1],0,1);
+	/* wait sending finish */
+	rprintf("wait for tx finish ...\n");
+	if(1) {
+		timeout = I2C_WAIT_COUNT;
+		while(!(g_hwp_i2c->STATUS & (I2C_MASTER_IRQ_TX_UDF))) {
+			if(timeout == 0) {
+				rprintf("dump i2c register ...\n");
+				dump_i2c_reg();
+				g_hwp_i2c->CMD = I2C_MASTER_STO | I2C_MASTER_FORCE_STO;
+				rprintf("i2c send data timeout %d\n",
+						I2C_WAIT_TIME);
+				return -2;
+			}
+			udelay(I2C_WAIT_SLOT);
+			timeout--;
+			dump_i2c_reg();
+		}
+		g_hwp_i2c->CMD = 0;
+		g_hwp_i2c->CTRL1 = 0;
+		g_hwp_i2c->CTRL |= I2C_MASTER_CLEAR_FIFO;
+		g_hwp_i2c->CTRL	&= ~I2C_MASTER_CLEAR_FIFO;
+	}
+	rprintf("test done !!!\n");
+	return 0;
+}
+#ifdef CONFIG_IRQ
+static void i2c_tx_callback(void)
+{
+	if(g_hwp_i2c->STATUS & I2C_MASTER_IRQ_TX_UDF) {
+		g_i2c_flag_tx_msg_ok = 1;
+	} else {
+		g_i2c_flag_tx_msg_err++;
+	}
+	rprintf("i2c_tx_callback\n");
+	/* clear irq status */
+	g_hwp_i2c->IRQ_CLR = 0x01;
+}
+
+static inline void wr_i2c_bus(unsigned char dat,unsigned int cmd)
+{
+	g_hwp_i2c->TXRX_BUFFER = dat;
+	g_hwp_i2c->CMD	= cmd;
+}
+
+static inline void rd_i2c_bus(unsigned char dat,unsigned int cmd)
+{
+	g_hwp_i2c->CMD = cmd;
+}
+
+int i2c_test_tx_data_int(unsigned char addr,const unsigned char *dat,int len)
+{
+	int i,err = 0;
+	unsigned int sta_cmd,sto_cmd,dat_cmd,busy;
+	volatile unsigned int timeout;
+
+	rprintf("\ni2c tx data interrupt test,addr = %x, len = %d\n",
+			(unsigned int)dat,len);
+
+	dat_cmd = I2C_MASTER_WR;
+	sta_cmd = I2C_MASTER_STA | I2C_MASTER_WR;
+	sto_cmd = I2C_MASTER_STO | I2C_MASTER_WR;
+	busy	= I2C_MASTER_TIP | I2C_MASTER_BUSY;
+	timeout = I2C_WAIT_COUNT;
+	addr	= (addr << 1) & 0xFE;
+
+	/* waitting for bus idle */
+	while(g_hwp_i2c->STATUS & busy) {
+		if(timeout == 0) {
+			rprintf("dump i2c register ...\n");
+			dump_i2c_reg();
+			g_hwp_i2c->CMD = I2C_MASTER_STO | I2C_MASTER_FORCE_STO;
+			rprintf("i2c bus is busy,exit\n");
+			return -1;
+		}
+		udelay(I2C_WAIT_SLOT);
+		timeout--;
+	}
+	/* ready data */
+	timeout = I2C_WAIT_COUNT;
+	g_i2c_flag_tx_msg_ok = 0;
+	g_i2c_flag_tx_msg_err = 0;
+	/*
+	 * register a interrupt handler
+	 * When the first byte is moved to shift register from tx fifo and the
+	 * tx fifo is empty,the TX_UDF will be set 1. A interrupt should be
+	 * triggered by TX_UDF and MCU begin to run a interrupt service funtion
+	 * named callback().
+	 */
+	i2c_enable_irq(0);
+	/* clear tx fifo and flag */
+	i2c_clear_fifo();
+	/* register a interrupt handler */
+	irq_request(RDA_IRQ_I2C,i2c_tx_callback);
+	/* enable gic interrupt */
+	irq_unmask(RDA_IRQ_I2C);
+	/* enable TX_UDF inerrupt */
+	i2c_enable_irq(1);
+	/* enable tx fifo under flow interrupt */
+	g_hwp_i2c->CTRL1 |= I2C_MASTER_TXFIFO_UNDER_IRQ_MASK;
+	/* begin to send data */
+	wr_i2c_bus(addr,sta_cmd);
+	for(i = 0;i < len - 1;i++) {
+		while(i2c_get_free_space() == 0);
+		wr_i2c_bus(dat[i],dat_cmd);
+	}
+	wr_i2c_bus(dat[i],sto_cmd);
+	/* wait sending finish */
+	while(1) {
+		if(g_i2c_flag_tx_msg_ok) {
+			err = 0;
+			rprintf("transmit data ok !\n");
+			break;
+		}
+		if(!timeout) {
+			err = -2;
+			rprintf("dump i2c register ...\n");
+			dump_i2c_reg();
+			g_hwp_i2c->CMD = I2C_MASTER_STO | I2C_MASTER_FORCE_STO;
+			rprintf("transmit data timeout %d !\n",
+					I2C_WAIT_TIME);
+			break;
+		}
+		udelay(I2C_WAIT_SLOT);
+		timeout--;
+	}
+	/* disable GIC ieterrupt */
+	irq_mask(RDA_IRQ_I2C);
+	irq_free(RDA_IRQ_I2C);
+	i2c_enable_irq(0);
+	g_hwp_i2c->CMD = 0;
+	g_hwp_i2c->CTRL1 = 0;
+	i2c_clear_fifo();
+#if 0
+	rprintf("dump i2c register ...\n");
+	dump_i2c_reg();
+#endif
+	if(g_i2c_flag_tx_msg_err) {
+		/*
+		 * if g_i2c_flag_msg_err is not 0, this means
+		 * a interrupt is triggered while there is no
+		 * anyone IRQ source is enabled of I2C.
+		 */
+		rprintf("IRQ error occur ###,error is %d\n",
+				g_i2c_flag_tx_msg_err);
+		while(1);//halt
+	}
+	if(err)
+		rprintf("test error ###\n",err);
+	else
+		rprintf("test done !!!\n");
+	return err;
+}
+#else
+int i2c_test_tx_data_int(unsigned char addr,const unsigned char *dat,int len){return 0;}
+#endif /* CONFIG_IRQ */
+
+int i2c_case_test_tx_busy_state(unsigned char addr)
+{
+	unsigned char i = 0;
+	unsigned int sta_cmd,sto_cmd,dat_cmd;
+	unsigned int status;
+
+	rprintf("\ni2c tx busy state test,addr is %x\n",addr);
+	sta_cmd = I2C_MASTER_STA | I2C_MASTER_WR;
+	sto_cmd = I2C_MASTER_STO | I2C_MASTER_WR;
+	dat_cmd  = I2C_MASTER_WR;
+	addr = (addr << 1) & 0xFE;
+
+	/* wait until bus is idle */
+	rprintf("dump i2c register\n");
+	dump_i2c_reg();
+	rprintf("check busy state\n");
+	if(!(g_hwp_i2c->STATUS & I2C_MASTER_BUSY)) {
+		rprintf("i2c bus is idle,send some bytes\n");
+		/* send address byte */
+		g_hwp_i2c->TXRX_BUFFER = addr;
+		g_hwp_i2c->CMD = sta_cmd;
+		/* load data into tx fifo */
+		for(i = 0;i < I2C_TX_FIFO_SIZE - 2;i++) {
+			g_hwp_i2c->TXRX_BUFFER = i;
+			g_hwp_i2c->CMD = dat_cmd;
+		}
+		g_hwp_i2c->TXRX_BUFFER = 0xED;
+		g_hwp_i2c->CMD = sto_cmd;
+
+		status = g_hwp_i2c->STATUS;
+		rprintf("status is %x\n",status);
+		if(!(status & I2C_MASTER_BUSY)) {
+			rprintf("i2c bus is still idle after fill tx fifo\n"
+					"test error ###\n");
+			return -1;
+		}
+		dump_i2c_reg();
+		rprintf("delay ...\n");
+		mdelay(10);
+		dump_i2c_reg();
+	}
+	if(g_hwp_i2c->STATUS & (I2C_MASTER_BUSY)) {
+		rprintf("i2c bus is busy,delay ...\n");
+		mdelay(100);
+	} else {
+		rprintf("i2c bus is idle after sending some bytes\n"
+				"test done !!!\n");
+		return 0;
+	}
+	rprintf("check busy flag again\n");
+	dump_i2c_reg();
+	if(g_hwp_i2c->STATUS & (I2C_MASTER_BUSY)) {
+		rprintf("i2c bus is still busy, send stop cmd ...\n");
+		i2c_clear_fifo();
+		g_hwp_i2c->CMD = I2C_MASTER_STO | I2C_MASTER_FORCE_STO;
+		rprintf("delay ...\n");
+		mdelay(100);
+	}
+	dump_i2c_reg();
+	if(g_hwp_i2c->STATUS & I2C_MASTER_BUSY) {
+		rprintf("i2c bus is busy after sending stop cmd\n"
+				"test error ###\n");
+		return -1;
+	} else {
+		rprintf("i2c bus is idle after sending stop cmd\n"
+				"test done !!!\n");
+		return 0;
+	}
+}
+
+int i2c_case_test_tx_speed(unsigned char addr,unsigned int speed)
+{
+	unsigned char i = 0x55;
+	unsigned int sta_cmd,sto_cmd,dat_cmd;
+	unsigned int emp_num,busy;
+	unsigned int tick_a,tick_b;
+	unsigned int dur_time,real_speed,sum_bit;
+
+	rprintf("\ni2c tx speed test,addr is %x\n",addr);
+
+	busy = I2C_MASTER_BUSY | I2C_MASTER_TIP;
+	sta_cmd = I2C_MASTER_STA | I2C_MASTER_WR;
+	sto_cmd = I2C_MASTER_STO | I2C_MASTER_WR;
+	dat_cmd  = I2C_MASTER_WR;
+	addr = (addr << 1) & 0xFE;
+
+	/* wait until bus is idle */
+	rprintf("clear fifo\n");
+	i2c_clear_fifo();
+
+	rprintf("check busy\n");
+	if(g_hwp_i2c->STATUS & busy) {
+		rprintf("i2c bus is busy,delay ...\n");
+		mdelay(100);
+	}
+	if(g_hwp_i2c->STATUS & busy) {
+		rprintf("dump i2c register\n");
+		dump_i2c_reg();
+		rprintf("i2c bus is busy,exit\n");
+		return -1;
+	}
+
+	rprintf("i2c bus is idle,send some bytes\n");
+	/* mark current ticks value */
+	tick_a = get_ticks_x(NULL,NULL);
+	/* send address byte */
+	g_hwp_i2c->TXRX_BUFFER = addr;
+	g_hwp_i2c->CMD = sta_cmd;
+	/* load data into tx fifo */
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = sto_cmd;
+
+	do {
+		emp_num = (g_hwp_i2c->STATUS >> 26) & I2C_TX_FIFO_SIZE;
+	}while(emp_num != I2C_TX_FIFO_SIZE);
+
+	/* mark current ticks value */
+	tick_b = get_ticks_x(NULL,NULL);
+	rprintf("tick_a: %d, tick_b: %d,b-a: %d\n"
+			,tick_a,tick_b,tick_b-tick_a);
+
+	// assume HWTIMER clock frequency is 2MHz,1 tick is 0.5 us
+	dur_time = ((tick_b - tick_a) * 10) / 2;
+	sum_bit = 20 * (8 + 1) + 2 - 10;
+	real_speed = ((sum_bit * 1000) * 10) / dur_time;
+
+	//the real speed is 184.846 kbps
+	rprintf("real speed is %d kbps,the expected speed is %d kbps\n"
+			,real_speed,speed);
+	rprintf("test done !!!\n");
+	return 0;
+}
+
+int i2c_case_test_tx_speed_with_busy(unsigned char addr,unsigned int speed)
+{
+	unsigned char i = 0x55;
+	unsigned int sta_cmd,sto_cmd,dat_cmd;
+	unsigned int emp_num,busy,status;
+	unsigned int tick_a,tick_b,tick_c;
+	unsigned int dur_time,real_speed,sum_bit;
+
+	rprintf("\ni2c tx speed test,addr is %x\n",addr);
+
+	busy = I2C_MASTER_BUSY | I2C_MASTER_TIP;
+	sta_cmd = I2C_MASTER_STA | I2C_MASTER_WR;
+	sto_cmd = I2C_MASTER_STO | I2C_MASTER_WR;
+	dat_cmd  = I2C_MASTER_WR;
+	addr = (addr << 1) & 0xFE;
+
+	/* wait until bus is idle */
+	rprintf("clear fifo\n");
+	i2c_clear_fifo();
+
+	rprintf("check busy\n");
+	if(g_hwp_i2c->STATUS & busy) {
+		rprintf("i2c bus is busy,delay ...\n");
+		mdelay(100);
+	}
+	if(g_hwp_i2c->STATUS & busy) {
+		rprintf("dump i2c register\n");
+		dump_i2c_reg();
+		rprintf("i2c bus is busy,exit\n");
+		return -1;
+	}
+
+	rprintf("i2c bus is idle,send some bytes\n");
+	/* mark time before start to write data to buffer */
+	tick_a = get_ticks_x_x();
+	/* send address byte */
+	g_hwp_i2c->TXRX_BUFFER = addr;
+	g_hwp_i2c->CMD = sta_cmd;
+	/* load data into tx fifo */
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = dat_cmd;
+
+	g_hwp_i2c->TXRX_BUFFER = i;
+	g_hwp_i2c->CMD = sto_cmd;
+
+	/* wait until tx fifo is empty */
+	do {
+		emp_num = (g_hwp_i2c->STATUS >> 26) & I2C_TX_FIFO_SIZE;
+	}while(emp_num != I2C_TX_FIFO_SIZE);
+
+	/* mack time when tx fifo is empty */
+	tick_b = get_ticks_x_x();
+
+	/* wait until busy flag is cleared */
+	do {
+		status = (g_hwp_i2c->STATUS & busy);
+	}while(status);
+
+	/* mark time when busy state is cleared */
+	tick_c = get_ticks_x_x();
+
+	rprintf("tick_a: %d, tick_b: %d,tick_c: %d,"
+		"b - a: %d, c - a: %d, c - b: %d\n"
+		,tick_a,tick_b,tick_c,
+		tick_b - tick_a,tick_c - tick_a,tick_c - tick_b);
+
+	// assume HWTIMER clock frequency is 2MHz,1 tick is 0.5 us
+	dur_time = ((tick_b - tick_a) * 10) / 2;
+	sum_bit = 20 * (8 + 1) + 2 - 10;
+	real_speed = ((sum_bit * 1000) * 10) / dur_time;
+
+	//the real speed is 184.846 kbps when I2C is  configured 200 kbps
+	rprintf("real speed is %d Kbps,the expected speed is %d Kbps\n"
+			,real_speed,speed);
+	rprintf("test done !!!\n");
+	return 0;
+}
+
+int i2c_test_rx_data_pol(unsigned char addr,unsigned char *buf,int len)
+{
+	int i = 0;
+	unsigned char temp;
+	int rx_len;
+	static volatile unsigned int timeout = 0;
+
+	rprintf("\ni2c rx data polling test,addr = %x,len = %d\n",
+			(unsigned int)buf,len);
+	len = (len > I2C_TX_FIFO_SIZE) ? I2C_TX_FIFO_SIZE : len;
+
+//	rprintf("clear fifo ...\n");
+//	i2c_clear_fifo();
+
+	rprintf("waiting for bus idle ...\n");
+	timeout = I2C_WAIT_COUNT;
+	while(g_hwp_i2c->STATUS & (I2C_MASTER_TIP | I2C_MASTER_BUSY)) {
+		if(timeout == 0) {
+			g_hwp_i2c->CMD = I2C_MASTER_STO | I2C_MASTER_FORCE_STO;
+			rprintf("dump register ...\n");
+			dump_i2c_reg();
+			rprintf("i2c bus is busy,exit\n");
+			return -1;
+		}
+		udelay(I2C_WAIT_SLOT);
+		timeout--;
+	}
+	/* send address,RW = 1 */
+	temp = (addr << 1) | 0x01;
+	i2c_tx_byte(temp,1,0);
+#if 1
+	/* wait tx fifo empty,maybe the data walking on the bus */
+	timeout = I2C_WAIT_COUNT;
+	while(!(g_hwp_i2c->STATUS & I2C_MASTER_IRQ_TX_UDF)) {
+		if(timeout == 0) {
+			g_hwp_i2c->CMD = I2C_MASTER_STO;
+			rprintf("i2c send address timeout %d\n",
+					I2C_WAIT_TIME);
+			rprintf("dump register ...\n");
+			dump_i2c_reg();
+			return -2;
+		}
+		udelay(I2C_WAIT_SLOT);
+		timeout--;
+	}
+#endif
+	/* set rx data number */
+	i2c_set_rx_number(len);
+	/* set rx data command */
+	i2c_rx_byte(NULL,0,1);
+	/* wait until rx data finished */
+	timeout = I2C_WAIT_COUNT;
+	while(1) {
+		rx_len = i2c_get_rx_number();
+		if(rx_len >= len) {
+			rprintf("received %d bytes: ",rx_len);
+			break;
+		}
+		if(timeout == 0) {
+			g_hwp_i2c->CMD = I2C_MASTER_STO | I2C_MASTER_FORCE_STO;
+			rprintf("i2c receive data timeout %d\n",
+					I2C_WAIT_TIME);
+			rprintf("dump register ...\n");
+			dump_i2c_reg();
+			return -3;
+		}
+		udelay(I2C_WAIT_SLOT);
+		timeout--;
+	}
+	/* store data */
+	rprintf("received data:\n");
+	for(i = 0;i < rx_len;i++) {
+		buf[i] = g_hwp_i2c->TXRX_BUFFER;
+		rprintf("%2x ",buf[i]);
+	}
+	rprintf("\n");
+
+	if(rx_len != len) {
+		rprintf("test error ###\n");
+		i2c_set_rx_number(0);
+		i2c_clear_fifo();
+		return -3;
+	}
+	/* clear buffer */
+	i2c_set_rx_number(0);
+	i2c_clear_fifo();
+	rprintf("test done !!!\n");
+	return 0;
+}
+
+#ifdef CONFIG_IRQ
+static void i2c_rx_callback(void)
+{
+	g_i2c_flag_rx_msg_ok = 1;
+	rprintf("i2c_rx_callback\n");
+	/* clear irq status */
+	g_hwp_i2c->IRQ_CLR = 0x01;
+}
+
+int i2c_test_rx_data_int(unsigned char addr,unsigned char *buf,int len)
+{
+	int i,err = 0;
+	int rx_len = 0;
+	volatile unsigned int timeout = I2C_WAIT_COUNT;
+	unsigned int busy = I2C_MASTER_TIP | I2C_MASTER_BUSY;
+	unsigned int sta_cmd = I2C_MASTER_WR|I2C_MASTER_STA;
+	unsigned int dat_cmd = I2C_MASTER_RD|I2C_MASTER_STO|I2C_MASTER_ACK;
+	unsigned char temp = 0;
+	unsigned int tick_a = 0,tick_b = 0;
+
+	rprintf("\ni2c rx data interrupts test,addr = %x,len = %d\n",
+			(unsigned int)buf,len);
+	while(g_hwp_i2c->STATUS & busy) {
+		if(timeout == 0) {
+			dump_i2c_reg();
+			g_hwp_i2c->CMD = I2C_MASTER_STO | I2C_MASTER_FORCE_STO;
+			rprintf("i2c bus is busy,exit\n");
+			return -1;
+		}
+		udelay(I2C_WAIT_SLOT);
+		timeout--;
+	}
+	/* disable I2C IRQs */
+	i2c_enable_irq(0);
+	g_hwp_i2c->CTRL1 = 0;
+	g_hwp_i2c->IRQ_CLR = 0x01;
+	/* clear TX FIFO */
+	i2c_clear_fifo();
+	/* ready data */
+	timeout = I2C_WAIT_COUNT;
+	addr = (addr << 1) | 0x01;
+	len = (len > I2C_TX_FIFO_SIZE) ? I2C_TX_FIFO_SIZE : len;
+	/* enable GIC IRQs */
+	irq_request(RDA_IRQ_I2C,i2c_rx_callback);
+	irq_unmask(RDA_IRQ_I2C);
+	/* enable I2C IRQs */
+	i2c_enable_irq(1);
+	/* send address,RW = 1 */
+	wr_i2c_bus(addr,sta_cmd);
+#if 1
+	/* wait tx fifo empty,maybe the data walking on the bus */
+	while(!(g_hwp_i2c->STATUS & I2C_MASTER_IRQ_TX_UDF)) {
+		if(timeout == 0) {
+			g_hwp_i2c->CMD = I2C_MASTER_STO;
+			rprintf("i2c send address timeout %d\n",
+					I2C_WAIT_TIME);
+			dump_i2c_reg();
+			return -1;
+		}
+		udelay(I2C_WAIT_SLOT);
+		timeout--;
+	}
+#endif
+	/* set rx data number */
+	i2c_set_rx_number(len);
+	/* set rx data command */
+	rd_i2c_bus(0,dat_cmd);
+	/* clear ok flag */
+	timeout = I2C_WAIT_COUNT;
+	g_i2c_flag_rx_msg_ok = 0;
+	/* enable rx fifo interrupts */
+	g_hwp_i2c->CTRL1 |= I2C_MASTER_RXFIFO_NUM_IRQ_MASK;
+	/* wait until rx data finished */
+	tick_a = get_ticks_x_x();
+	while(1) {
+		if(!i2c_bus_is_busy()){
+			if(g_i2c_flag_rx_msg_ok) {
+				err = 0;
+				tick_b = get_ticks_x_x();
+				rx_len = i2c_get_rx_number();
+			//	rprintf("%x\n",g_hwp_i2c->STATUS); // for TIP
+				rprintf("received %d bytes: ",rx_len);
+				break;
+			}
+		}
+		if(timeout == 0) {
+			err = -2;
+			g_hwp_i2c->CMD = I2C_MASTER_STO | I2C_MASTER_FORCE_STO;
+			rprintf("i2c receive data timeout %d us\n",
+					I2C_WAIT_TIME);
+			dump_i2c_reg();
+			break;
+		}
+		udelay(I2C_WAIT_SLOT);
+		timeout--;
+	}
+	/* disable I2C rx fifo interrupts */
+	g_hwp_i2c->CTRL1 &= (~I2C_MASTER_RXFIFO_NUM_IRQ_MASK);
+	/* store data */
+	if(buf != NULL) {
+		for(i = 0;i < rx_len;i++)
+			buf[i] = g_hwp_i2c->TXRX_BUFFER;
+	} else {
+		temp = temp;
+		for(i = 0;i < rx_len;i++)
+			temp = g_hwp_i2c->TXRX_BUFFER;
+	}
+	/*
+	 * there is a very strange issue:
+	 * if we do disable irq before clear fifo
+	 * the TIP status will not be reset to 0
+	 * so we should set rx number to 0 and
+	 * clear the RX fifo before disable I2C
+	 * IRQs
+	 */
+//	i2c_enable_irq(0); // for TIP
+	/* clear buffer */
+	i2c_set_rx_number(0);
+	i2c_clear_fifo();
+	/* disable I2C IRQs */
+	i2c_enable_irq(0);// for TIP
+	/* disable GIC IRQs */
+	irq_mask(RDA_IRQ_I2C);
+	irq_free(RDA_IRQ_I2C);
+	if(buf != NULL) {
+		rprintf("i2c receive data: \n");
+		for(i = 0;i < rx_len;i++)
+			rprintf(" %2x",buf[i]);
+		rprintf("\n");
+	}
+	rprintf("tick_b: %d, tick_a: %d,b-a: %d\n"
+			,tick_b,tick_a,tick_b-tick_a);
+	dump_i2c_reg();
+	/* check received data length */
+	if((!err) && (rx_len >= len)) {
+		rprintf("test done !!!\n");
+	} else {
+		rprintf("test error ###\n");
+	}
+	return err;
+}
+#else
+int i2c_test_rx_data_int(unsigned char addr,unsigned char *buf,int len){return 0;}
+#endif /* CONFIG_IRQ */
+
+int i2c_case_test_receiving_msg_pol(unsigned char addr,
+					unsigned char *buf,
+					int len,
+					int times)
+{
+	int ret = 0;
+
+	rprintf("\ni2c receiving messsage polling test.\n"
+		"please touch you phone's screen.\n");
+
+	mdelay(1000);
+	while(times--) {
+		ret += i2c_test_rx_data_pol(addr,buf,len);
+		mdelay(1000);
+	}
+	if(ret !=0)
+		rprintf("test error,ret is %d ###\n",ret);
+	else
+		rprintf("test done !!!\n");
+	return ret;
+}
+
+int i2c_case_test_transmitting_msg_pol(unsigned char addr,
+					const unsigned char *dat,
+					int len,
+					int times)
+{
+	int ret = 0;
+	rprintf("\ni2c transmitting message polling test ...\n");
+	while(times--) {
+		ret += i2c_test_tx_data_pol(addr,dat,len);
+	}
+	if(ret != 0)
+		rprintf("test error,ret is %d ###\n",ret);
+	else
+		rprintf("test done !!!\n");
+	return ret;
+}
+
+int i2c_case_test_transmitting_speed(unsigned char addr)
+{
+	unsigned int spd_tab[7] = {100,150,200,250,300,350,400};
+	unsigned int old_speed = g_i2c_speed;
+	int i,ret = 0;
+
+	rprintf("\ni2c transmitting speed test ...\n");
+	for(i = 0;i < 7;i++) {
+		g_i2c_speed = spd_tab[i];
+		i2c_test_init();
+		mdelay(100);
+		ret += i2c_case_test_tx_speed(addr,g_i2c_speed);
+		mdelay(100);
+	}
+	/* recovery old speed configuration */
+	g_i2c_speed = old_speed;
+	i2c_test_init();
+	mdelay(100);
+
+	if(ret != 0)
+		rprintf("test error,ret is %d ###\n",ret);
+	else
+		rprintf("test done !!!\n");
+	return ret;
+}
+
+int i2c_case_test_transmitting_msg_irq(unsigned char addr,
+					const unsigned char *dat,
+					int len,
+					int times)
+{
+	int ret = 0;
+
+	rprintf("\ni2c transmit interrupts test\n");
+	while(times--) {
+		ret += i2c_test_tx_data_int(addr,dat,len);
+	}
+	if(ret != 0)
+		rprintf("test error,ret is %d\n",ret);
+	else
+		rprintf("test done !!!\n");
+	return ret;
+}
+
+int i2c_case_test_receiving_msg_irq(unsigned char addr,
+					unsigned char *rx_buf,
+					int len,
+					int times)
+{
+	int ret = 0;
+
+	rprintf("\n i2c receiving interrputs test\n");
+	while(times--) {
+		ret += i2c_test_rx_data_int(addr,rx_buf,len);
+	}
+	if(ret != 0)
+		rprintf("test error,ret is %d\n",ret);
+	else
+		rprintf("test done !!!\n");
+	return  ret;
+}
+
+int i2c_check_result(int val,const char *name_str)
+{
+	if(val != 0) {
+		rprintf("\n%s failed ###,error is %d\n"
+			,name_str,val);
+		//rprintf("test stoped\n");
+		//while(1);
+		return -1;
+	}
+	return 0;
+}
+
+#if 0
+int test_i2c(int id,int times)
+{
+	unsigned char tx_buf[10] = {0x11,0x22,0x33,0x44,0x55,0x66,0x77,0x88,0x99,0xAA};
+	unsigned char rx_buf[10] = {0x5A};
+	int rx_len;
+	int tx_len;
+	int ret;
+	unsigned char addr;
+	volatile unsigned char cmd;
+
+	rprintf("\n");
+	if((id > 2) || (id < 0)) {
+		rprintf("i2c id %d is invalid,must be 0 ~ 2.exit\n",id);
+		return -1;
+	}
+	if(times <= 0) {
+		rprintf("i2c times %d is invalid,exit\n"
+				,times);
+		return -2;
+	}
+	rprintf("\nstart to test i2c %d,test %d times\n",id,times);
+
+	g_hwp_i2c 	= g_i2c_tab[id];
+	g_i2c_speed 	= 200;
+	g_hwp_i2c 	= hwp_i2cMaster3;
+	rx_len 	= 4;
+	tx_len 	= 10;
+	ret 	= 0;
+	addr 	=I2C_SLAVE_ADDR_TS_MSG2133;
+
+	touch_sensor_init();
+	i2c_test_init();
+	i2c_buffer_init();
+
+	while(1) {
+		rprintf("> ");
+		cmd = serial_getc();
+		rprintf("%c\n",cmd);
+
+		switch(cmd) {
+		case '0':
+			i2c_case_check_register_default_value();
+			break;
+		case '1':
+			ret = i2c_test_tx_data_pol(addr,tx_buf,tx_len);
+			i2c_check_result(ret,"tx data pol test");
+			break;
+		case '2':
+			ret = i2c_test_tx_data_int(addr,tx_buf,tx_len);
+			i2c_check_result(ret,"tx data int test");
+			break;
+		case '3':
+			ret = i2c_test_rx_data_pol(addr,rx_buf,rx_len);
+			i2c_check_result(ret,"rx data pol test");
+			break;
+		case '4':
+			ret = i2c_test_rx_data_int(addr,rx_buf,rx_len);
+			i2c_check_result(ret,"rx data int test");
+			break;
+		case '5':
+			ret = i2c_case_test_tx_speed(addr,g_i2c_speed);
+			i2c_check_result(ret,"tx speed test");
+			break;
+		case '6':
+			ret = i2c_case_test_tx_speed_with_busy(addr,g_i2c_speed);
+			i2c_check_result(ret,"tx speed with busy test");
+			break;
+
+		case 'a':
+			ret = i2c_case_test_tx_busy_state(addr);
+			i2c_check_result(ret,"tx busy state test");
+			break;
+		case 'b':
+			ret = i2c_case_test_transmitting_speed(addr);
+			i2c_check_result(ret,"transmitting speed test");
+			break;
+		case 'c':
+			ret = i2c_case_test_receiving_msg_pol(addr,
+								rx_buf,
+								rx_len,
+								10);
+			i2c_check_result(ret,"receiving msg pol test");
+			break;
+		case 'd':
+			ret = i2c_case_test_transmitting_msg_pol(addr,
+								tx_buf,
+								tx_len,
+								times);
+			i2c_check_result(ret,"transmitting msg pol test");
+			break;
+		case 'e':
+			ret = i2c_case_test_transmitting_msg_irq(addr,
+								tx_buf,
+								tx_len,
+								times);
+			i2c_check_result(ret,"transmitting msg irq test");
+			break;
+		case 'f':
+			ret = i2c_case_test_receiving_msg_irq(addr,
+								tx_buf,
+								rx_len,
+								times);
+			i2c_check_result(ret,"receiving msg irq test");
+			break;
+		case 'q':
+			rprintf("i2c test quit\n");
+			return 0;
+		case 'r':
+			rprintf("reset i2c");
+			i2c_test_init();
+			i2c_buffer_init();
+			break;
+		default:
+			break;
+		}
+		rprintf("\n");
+	}
+}
+
+#else
+int test_i2c(int id,int times)
+{
+	unsigned char tx_buf[10] = {0x11,0x22,0x33,0x44,0x55,0x66,0x77,0x88,0x99,0xAA};
+	unsigned char rx_buf[10] = {0x5A};
+	int rx_len;
+	int tx_len;
+	int ret;
+	unsigned char addr;
+
+	rprintf("\n");
+	if((id > 2) || (id < 0)) {
+		rprintf("i2c id %d is invalid,must be 0 ~ 2.exit\n",id);
+		return -1;
+	}
+	if(times <= 0) {
+		rprintf("i2c times %d is invalid,exit\n"
+				,times);
+		return -2;
+	}
+	rprintf("\nstart to test i2c %d,test %d times\n",id,times);
+
+	g_hwp_i2c 	= g_i2c_tab[id];
+	g_i2c_speed 	= 200;
+	rx_len 	= 4;
+	tx_len 	= 10;
+	ret 	= 0;
+	addr 	=I2C_SLAVE_ADDR_TS_MSG2133;
+
+	touch_sensor_init();
+	i2c_test_init();
+	i2c_buffer_init();
+
+	ret = i2c_case_test_tx_speed(addr,g_i2c_speed);
+	if(i2c_check_result(ret,"tx speed test"))
+		return ret;
+
+	ret = i2c_case_test_tx_speed_with_busy(addr,g_i2c_speed);
+	if(i2c_check_result(ret,"tx speed with busy test"))
+		return ret;
+
+	ret = i2c_case_test_tx_busy_state(addr);
+	if(i2c_check_result(ret,"tx busy state test"))
+		return ret;
+
+	ret = i2c_case_test_transmitting_speed(addr);
+	if(i2c_check_result(ret,"transmit speed test"))
+		return ret;
+
+	ret = i2c_case_test_receiving_msg_pol(addr,rx_buf,rx_len,10);
+	if(i2c_check_result(ret,"receiving msg pol test"))
+		return ret;
+
+	ret = i2c_case_test_transmitting_msg_pol(addr,tx_buf,tx_len,times);
+	if(i2c_check_result(ret,"transmitting msg pol test"))
+		return ret;
+
+	ret = i2c_case_test_transmitting_msg_irq(addr,tx_buf,tx_len,times);
+	if(i2c_check_result(ret,"transmitting msg irq test"))
+		return ret;
+
+	ret = i2c_case_test_receiving_msg_irq(addr,tx_buf,rx_len,times);
+	if(i2c_check_result(ret,"receiving msg irq test"))
+		return ret;
+
+	rprintf("\n\nall i2c test cases are OK !!!\n");
+	rprintf("\n\ni2c test done !!!\n");
+	return 0;
+}
+#endif
+
+#if 0
+static void ispi_open(int modemSpi)
+{
+	UINT32 cfgReg = 0;
+	UINT32 ctrlReg = 0;
+
+	/* hard code for now */
+	cfgReg = 0x100003;
+	ctrlReg = 0x2019d821;
+
+	if (modemSpi)
+		hwp_ispi = hwp_mspi2;
+	else
+		hwp_ispi = hwp_spi3;
+
+	/* Activate the ISPI. */
+	hwp_ispi->cfg = cfgReg;
+	hwp_ispi->ctrl = ctrlReg;
+
+	/* No IRQ. */
+	hwp_ispi->irq = 0;
+}
+
+static UINT8 ispi_tx_fifo_avail(void)
+{
+	UINT8 freeRoom;
+
+	/* Get avail level. */
+	freeRoom = GET_BITFIELD(hwp_ispi->status, SPI_TX_SPACE);
+
+	return freeRoom;
+}
+
+static BOOL ispi_tx_finished(void)
+{
+	UINT32 spiStatus;
+	spiStatus = hwp_ispi->status;
+
+	/* If ISPI FSM is active and the TX Fifo is empty */
+	/* (ie available space == Fifo size), the tf is not done */
+	if ((!(hwp_ispi->status & SPI_ACTIVE_STATUS))
+		&& (SPI_TX_FIFO_SIZE == GET_BITFIELD(spiStatus, SPI_TX_SPACE))) {
+		return TRUE;
+	} else {
+		return FALSE;
+	}
+}
+
+static UINT32 ispi_send_data(UINT32 csId, UINT32 data, BOOL read)
+{
+	UINT32 freeRoom;
+
+	/* Clear data upper bit to only keep the data frame. */
+	UINT32 reg = data & ~(SPI_CS_MASK | SPI_READ_ENA_MASK);
+
+	/* Add CS and read mode bit */
+	reg |= SPI_CS(csId) | (read ? SPI_READ_ENA : 0);
+
+	/* Enter critical section. */
+	//UINT32 status = hwp_sysIrq->SC;
+
+	/* Check FIFO availability. */
+	freeRoom = GET_BITFIELD(hwp_ispi->status, SPI_TX_SPACE);
+
+	if (freeRoom > 0) {
+		hwp_ispi->rxtx_buffer = reg;
+
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+static UINT32 ispi_get_data(UINT32 * recData)
+{
+	UINT32 nbAvailable;
+
+	nbAvailable = GET_BITFIELD(hwp_ispi->status, SPI_RX_LEVEL);
+
+	if (nbAvailable > 0) {
+		*recData = hwp_ispi->rxtx_buffer;
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+static void ispi_reg_write(UINT32 regIdx, UINT32 value)
+{
+	UINT32 wrData;
+
+	wrData = (0 << 25) | ((regIdx & 0x1ff) << 16) | (value & 0xffff);
+
+	while (ispi_tx_fifo_avail() < 1 ||
+		   ispi_send_data(0, wrData, FALSE) == 0) ;
+
+	/* wait until any previous transfers have ended */
+	while (!ispi_tx_finished()) ;
+}
+
+static UINT32 ispi_reg_read(UINT32 regIdx)
+{
+	UINT32 wrData, rdData = 0;
+	UINT32 count;
+
+	wrData = (1 << 25) | ((regIdx & 0x1ff) << 16) | 0;
+
+	while (ispi_tx_fifo_avail() < 1 ||
+		   ispi_send_data(0, wrData, TRUE) == 0) ;
+
+	/* wait until any previous transfers have ended */
+	while (!ispi_tx_finished()) ;
+
+	count = ispi_get_data(&rdData);
+	if (1 != count)
+		rprintf("ABB ISPI count err!");
+
+	rdData &= 0xffff;
+
+	return rdData;
+}
+#endif
+
+static void touch_sensor_power_init(void)
+{
+	unsigned int addr,val;
+
+	ispi_open(1);
+	/* select vol > 2V */
+	addr = 0x07;
+	val = ispi_reg_read(addr);
+	val &= (~(1<<13));
+//	val |= (1<<13);// select vol < 2V
+	ispi_reg_write(addr,val);
+	/*
+	 * enable power in normal mode
+	 * set max value
+	 */
+	addr = 0x28;
+	val = ispi_reg_read(addr);
+	val |= (1<<13);
+	val |= (7 << 3);
+	ispi_reg_write(addr,val);
+	/* enable power in LP mode */
+	addr = 0x29;
+	val = ispi_reg_read(addr);
+	val |= (1<<13);
+	ispi_reg_write(addr,val);
+
+	d_printf("pmu reg %x = %x\n",0x07,(unsigned int)ispi_reg_read(0x07));
+	d_printf("pmu reg %x = %x\n",0x28,(unsigned int)ispi_reg_read(0x28));
+	d_printf("pmu reg %x = %x\n",0x29,(unsigned int)ispi_reg_read(0x29));
+
+	ispi_open(0);
+}
+
+static void touch_sensor_gpio_init(void)
+{
+	/* touch sensor reset pin direction: output,0 */
+	BANK_TOUCH_RESET->gpio_oen_set_out = (1 << GPIO_TOUCH_RESET);
+	BANK_TOUCH_RESET->gpio_clr = (1 << GPIO_TOUCH_RESET);
+	/* touch sensor irq pin direction: input */
+	BANK_TOUCH_IRQ->gpio_oen_set_in = (1 << GPIO_TOUCH_IRQ);
+	/* touch sensor i2c 3 pin scl,sda: alt */
+	d_printf("BANK_PIN_CFG : %x, BANK_PIN_CFG->AP_GPIO_B_Mode: %x\n"
+			,(unsigned int)(BANK_PIN_CFG),BANK_PIN_CFG->AP_GPIO_B_Mode);
+	BANK_PIN_CFG->AP_GPIO_B_Mode &= (~(1 << GPIO_TOUCH_SCL));
+	BANK_PIN_CFG->AP_GPIO_B_Mode &= (~(1 << GPIO_TOUCH_SDA));
+	d_printf("BANK_PIN_CFG : %x, BANK_PIN_CFG->AP_GPIO_B_Mode: %x\n"
+			,(unsigned int)(BANK_PIN_CFG),BANK_PIN_CFG->AP_GPIO_B_Mode);
+}
+
+static void gpio_set_val(HWP_GPIO_T *ptr_gpio,int pin,int val)
+{
+	unsigned int mask = 1 << (pin % 32);
+	if(val)
+		ptr_gpio->gpio_set = mask;
+	else
+		ptr_gpio->gpio_clr = mask;
+	d_printf("ptr_gpio: %x, pin: %x, mask: %x, val: %x\n",
+			(unsigned int)ptr_gpio,pin,mask,val);
+}
+
+static void touch_sensor_reset(void)
+{
+	gpio_set_val(BANK_TOUCH_RESET,GPIO_TOUCH_RESET,1);
+	mdelay(5);
+	gpio_set_val(BANK_TOUCH_RESET,GPIO_TOUCH_RESET,0);
+	mdelay(80);
+	gpio_set_val(BANK_TOUCH_RESET,GPIO_TOUCH_RESET,1);
+	mdelay(80);
+}
+#if 0
+static void touch_sensor_suspend(void)
+{
+	gpio_set_val(BANK_TOUCH_RESET,GPIO_TOUCH_RESET,0);
+	mdelay(10);
+}
+
+static void touch_sensor_resume(void)
+{
+	gpio_set_val(BANK_TOUCH_RESET,GPIO_TOUCH_RESET,1);
+	mdelay(1);
+	touch_sensor_reset();
+}
+#endif
+static void touch_sensor_init(void)
+{
+	touch_sensor_power_init();
+	touch_sensor_gpio_init();
+	touch_sensor_reset();
+}
+
+static unsigned int get_ticks_x(unsigned int *ptr_high,unsigned int *ptr_low)
+{
+	unsigned int val_h,val_l;
+	val_h = (unsigned int)hwp_apTimer->HWTimer_LockVal_H;
+	val_l = (unsigned int)hwp_apTimer->HWTimer_LockVal_L;
+	if(val_h != hwp_apTimer->HWTimer_LockVal_H) {
+		val_h = (unsigned int)hwp_apTimer->HWTimer_LockVal_H;
+		val_l = (unsigned int)hwp_apTimer->HWTimer_LockVal_L;
+	}
+	if(ptr_high != NULL)
+		*ptr_high = val_h;
+	if(ptr_low != NULL)
+		*ptr_low = val_l;
+	return val_l;
+}
+
+static unsigned int get_ticks_x_x(void)
+{
+	return ((unsigned int)hwp_apTimer->HWTimer_LockVal_L);
+}
diff --git a/board/rda/common/include/a7_cp15_reg.h b/board/rda/common/include/a7_cp15_reg.h
new file mode 100644
index 0000000000..64389ab992
--- /dev/null
+++ b/board/rda/common/include/a7_cp15_reg.h
@@ -0,0 +1,46 @@
+#ifndef __A7_CP15_REG_H__
+#define __A7_CP15_REG_H__
+
+unsigned int read_cp15_midr(void);
+unsigned int read_cp15_mpidr(void);
+unsigned int read_cp15_revidr(void);
+unsigned int read_cp15_ccsidr(void);
+unsigned int read_cp15_clidr(void);
+unsigned int read_cp15_l2ctlr(void);
+
+unsigned int read_cp15_csselr(void);
+void write_cp15_csselr(unsigned int val);
+
+unsigned int read_cp15_sctlr(void);
+void write_cp15_sctlr(unsigned int val);
+
+unsigned int read_cp15_scr(void);
+void write_cp15_scr(unsigned int val);
+
+unsigned int read_cp15_ttbr0(void);
+void write_cp15_ttbr0(unsigned int val);
+
+unsigned int read_cp15_ttbr1(void);
+void write_cp15_ttbr1(unsigned int val);
+
+unsigned int read_cp15_ttbcr(void);
+void write_cp15_ttbcr(unsigned int val);
+
+unsigned int read_cp15_htcr(void);
+void write_cp15_htcr(unsigned int val);
+void write_cp15_dacr(unsigned int val);
+
+void __copy_bytes(unsigned char *des,unsigned char *src,unsigned int size);
+void __nop_dly(void);
+
+unsigned int read_cpu_cpsr(void);
+void write_cpu_cpsr(unsigned int val);
+
+void cp15_disable_all_cache(void);
+void cp15_enable_dcache(void);
+void cp15_enable_icache(void);
+void cp15_enable_mmu(void);
+void cp15_disable_dcache(void);
+void cp15_disable_icache(void);
+void cp15_disable_mmu(void);
+#endif
diff --git a/board/rda/common/include/bootp_mode.h b/board/rda/common/include/bootp_mode.h
new file mode 100644
index 0000000000..16013bcde0
--- /dev/null
+++ b/board/rda/common/include/bootp_mode.h
@@ -0,0 +1,68 @@
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//            Copyright (C) 2003-2007, Coolsand Technologies, Inc.            //
+//                            All Rights Reserved                             //
+//                                                                            //
+//      This source code is the property of Coolsand Technologies and is      //
+//      confidential.  Any  modification, distribution,  reproduction or      //
+//      exploitation  of  any content of this file is totally forbidden,      //
+//      except  with the  written permission  of  Coolsand Technologies.      //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//  $HeadURL: http://svn.rdamicro.com/svn/developing1/Sources/chip/branches/gallite441/boot/8809/src/bootp_mode.h $ //
+//    $Author: huazeng $                                                        // 
+//    $Date: 2011-11-30 18:24:46 +0800 (Wed, 30 Nov 2011) $                     //   
+//    $Revision: 12233 $                                                          //   
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+/// @file halp_boot_asm.h                                                     //
+/// That file provides defines used by the assembly boot code.                //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+
+#ifndef _HALP_BOOT_MODE_H_
+#define _HALP_BOOT_MODE_H_
+
+
+#define BOOT_MODE_STD                       (0)
+
+// O: SLC
+#define BOOT_MODE_NAND_MLC                  (1<<0)
+// 0: 16 bits
+#define BOOT_MODE_NAND_8BIT                 (1<<1)
+// 0: boot from nand
+#define BOOT_MODE_BOOT_EMMC                 (1<<2)
+// 0: boot from emmc or nand
+#define BOOT_MODE_BOOT_SPI                  (1<<3)
+// 0: boot from nor spi
+#define BOOT_MODE_BOOT_SPI_NAND             (1<<4)
+// 0: spi flash from camera pins
+#define BOOT_MODE_SPI_PIN_NAND              (1<<5)
+// 0: nand flash high 8 bits from lcd pins
+#define BOOT_MODE_NAND_HIGH_PIN_CAM         (1<<6)
+// 0: nand page size small, 2K-SLC/4K-MLC; 1: 4K-SLC/8K-MLC
+#define BOOT_MODE_NAND_PAGE_SIZE_L          (1<<7)
+
+#define BOOT_MODE_JTAG_ENABLE               (1<<8)
+
+#define BOOT_MODE_AP_MEM_CHECK_DISABLE      (1<<9)
+
+#define BOOT_MODE_DRIVER_TEST               (1<<10)
+
+#define BOOT_MODE_FORCE_DOWNLOAD            (1<<11)
+
+#define BOOT_MODE_KEY_ON                    (1<<12)
+// If with KeyOn, driver test;
+// If with long KeyOn, hardware reset
+#define BOOT_MODE_VOL_DN                    (1<<13)
+// If with KeyOn, force download
+#define BOOT_MODE_VOL_UP                    (1<<14)
+// Force download
+#define BOOT_MODE_PLUG_IN                   (1<<15)
+
+
+#endif // _HALP_BOOT_MODE_H_
+
+
diff --git a/board/rda/common/include/bs_h264_5f_720x480.md5 b/board/rda/common/include/bs_h264_5f_720x480.md5
new file mode 100644
index 0000000000..da58c77115
--- /dev/null
+++ b/board/rda/common/include/bs_h264_5f_720x480.md5
@@ -0,0 +1,14 @@
+0xCE,	0x8E,	0xFE,	0x91,	0xF2,	0xE9,	0xBB,	0x21,
+0xB6,	0x68,	0xF5,	0x83,	0x08,	0x65,	0xC4,	0x46,
+
+0x77,	0xF8,	0x62,	0x51,	0x62,	0x0E,	0xEE,	0x5B,
+0x80,	0xF8,	0x69,	0x1C,	0xB7,	0xEA,	0xCD,	0xBF,
+
+0xEC,	0x50,	0x46,	0xC1,	0x0C,	0xE6,	0x38,	0x37,
+0xB5,	0x01,	0xB8,	0x43,	0xCC,	0xF5,	0x30,	0x23,
+
+0xE0,	0x47,	0xA2,	0xE2,	0xB4,	0x03,	0xE5,	0x11,
+0x34,	0xC3,	0xAC,	0xB1,	0xB7,	0x61,	0x2E,	0x9F,
+
+0x83,	0x1F,	0x8F,	0x82,	0xFF,	0x59,	0x6E,	0x51,
+0xB4,	0xF7,	0x30,	0x1B,	0xB2,	0x4F,	0xC4,	0x58,
diff --git a/board/rda/common/include/bs_h264_5f_720x480.txt b/board/rda/common/include/bs_h264_5f_720x480.txt
new file mode 100644
index 0000000000..2d52fc6460
--- /dev/null
+++ b/board/rda/common/include/bs_h264_5f_720x480.txt
@@ -0,0 +1,9435 @@
+0x01000000,	0x1F404D27,	0x5A408D8D,	0x0000903D,	0xEE280100,	0x00C81508,	0x25010000,	0x000200B8,
+0xB4CC7F00,	0x1A917434,	0x778F4F3E,	0x94966C10,	0x036EB76C,	0xE3D1E21C,	0x7842BB5F,	0x1C857462,
+0x65111D33,	0xA363E24F,	0xDACFE14B,	0x21CE79E2,	0xB953854A,	0x75AC19AB,	0xC17FE329,	0xAF3F84BC,
+0xD8B7E21F,	0x1FCFF248,	0x5187EDB8,	0x6253B4AC,	0xE71F2548,	0x5BAE0113,	0xF6A98FBD,	0xFE997DFE,
+0x4DB8D2CD,	0xBB1D42E6,	0xDC771AD8,	0xBBA84A47,	0xE394F269,	0xB1865720,	0xF36CE7CF,	0x292917BC,
+0xE0E43EEB,	0xF9F3BF0B,	0x24924B12,	0x7583492D,	0xB71F5655,	0x0F5FAECD,	0xEF9036B6,	0xDDDC2581,
+0x3A10C8E2,	0x2F0354D7,	0x1702D9FA,	0xDDA471E6,	0x1FF5279D,	0x8FB6335D,	0x4FC973BE,	0x00ABB163,
+0x66976F24,	0xCE5DC065,	0x81BD5CD0,	0x1A36046B,	0xC6662FDE,	0xE81B47C1,	0xBFC15FB7,	0xB29507EE,
+0x2CA2CBBA,	0xA41ECCC1,	0x2FC88D3C,	0xF793B9E8,	0x7C46E6E1,	0xB193B580,	0xCEFE0BC8,	0xB72CA7AD,
+0x10ED37F8,	0x5BB9C37B,	0x24D26758,	0x791A472C,	0x3FC6CE0B,	0xF976A6A6,	0xF40DCD94,	0x04877935,
+0x49E010F1,	0x8638A128,	0x0584AEF1,	0x27A70AEF,	0x356FB08E,	0x5648D135,	0xB4A38A5B,	0xE51E6C69,
+0xC02E9621,	0x4AE0D7CE,	0xBD8FE74B,	0x3C7DF817,	0xB465142E,	0x104B2371,	0x5E7B61D5,	0xCF697BFA,
+0xBAD206D2,	0x3D5470B0,	0x9DB5FA0A,	0xAA94FBE1,	0xFEC6683E,	0x55C4C532,	0x31BB4BB6,	0xCDF9DC97,
+0x2263D167,	0x294F913A,	0x06D405E0,	0xCB11E6AB,	0xD7E6A708,	0x1E01542A,	0xBDBFAD22,	0xBED866F9,
+0xD99F0443,	0xD204DC7D,	0xD57E3C3D,	0xFB542E4E,	0x70562917,	0xB6EA34D2,	0x7953B0E6,	0xAD649B2E,
+0x6E03B5F2,	0x32D09FCB,	0xB7E19873,	0xC6546843,	0x3059A8B0,	0x5F6A65FF,	0x383F4531,	0x72DB461D,
+0x6C4CD85F,	0xF3138808,	0x5FB5982C,	0x8AD199C1,	0x67DB38D4,	0x607DBF5D,	0x1D4ACDD1,	0xB142488B,
+0xFD42458F,	0xA99A8A01,	0x6708D4F2,	0x8BBB782A,	0xD51FA650,	0xCC255367,	0x628FBB6D,	0x34060CFE,
+0x0CD22EDB,	0x9285AA7D,	0x086F0589,	0xADE23CC4,	0x5B64EDDB,	0x72DCFC71,	0x30842B8A,	0x855A5D76,
+0x2F858613,	0x809B07BC,	0xF26295DB,	0xF72797D5,	0x608C8662,	0x207AEA1E,	0x74150B7F,	0x48919CCD,
+0xC5D2DB54,	0x4B68880A,	0x167DCA39,	0xC2EBF403,	0xC2379C97,	0x81E739AE,	0x1675D97D,	0x5CEE9592,
+0xA3839961,	0xE5E97F95,	0x98938117,	0x4C59A62B,	0xF9B7642F,	0x27ED2194,	0xA5B48FE9,	0x9DBE245F,
+0x44C01ECA,	0x21587121,	0xEE047B89,	0xDD22B3CD,	0x60D35F67,	0x23D61382,	0x9B5BC1B6,	0xB32CDB1F,
+0x893165C3,	0x52717FB8,	0x36834659,	0x01BC42DE,	0xE59794D0,	0x3E694FD3,	0xA4CC8667,	0x07BFD9F2,
+0x8035EA1E,	0x519C0B99,	0x79EE2888,	0xF6D67FC5,	0xFC196B6B,	0xFF0F810F,	0xE76D6CFE,	0x73D9114A,
+0x55DC5D9B,	0xA5FAE39D,	0x669A88BA,	0x2ABA3EF7,	0x28B41E00,	0x77455A7F,	0x5ED23953,	0x7E627F7E,
+0xAC6DDB01,	0x16479748,	0x57636FD0,	0x24EC1FC0,	0xA94CFC71,	0x1332CFE4,	0x9A049B05,	0x1F17AD9A,
+0xE69D6C81,	0xDD125C45,	0x476E7CEE,	0x7E70F050,	0x685C421B,	0x6461779A,	0x065EB196,	0xD486EEB9,
+0xA0079090,	0xF8963C08,	0x9A48CE81,	0xFD6BB425,	0x9EFA89E1,	0x5B7F5394,	0x6EAA5D11,	0x4AEE12B7,
+0xED82AF74,	0x13DB9668,	0xE389D188,	0x1A6740F3,	0xDD97291D,	0x84E3F294,	0x82444DD1,	0xEA841497,
+0x684F55BE,	0x870572FB,	0xD0081B00,	0xD2E46E60,	0x5AFFE4E6,	0xBB584138,	0xB20AB467,	0x22EDB941,
+0xEBC98524,	0x2F1A6434,	0x54578E11,	0x04E1F2CA,	0x5E897233,	0x57F9950E,	0x990DA8F8,	0x3A9CBB07,
+0xF92B9E9C,	0x1EE2B205,	0xADDE8043,	0x7C33E7DF,	0xC0E12E54,	0xEA0F571C,	0xEB26302A,	0xCFC906F9,
+0x4DA2074B,	0xAF74A68F,	0x00201E9E,	0x089E05E4,	0xA6AE02A1,	0x309FB5C0,	0xB1CDD680,	0x39DA0328,
+0x66AD8CDF,	0x5D9CE75E,	0xFA215794,	0x4417EC3A,	0x6D90CB21,	0xFCC6390B,	0xB423B4F2,	0xD1CE41E0,
+0x0419C01B,	0x53A1BBBF,	0x78A01250,	0x6E57058A,	0x5ADDDDA1,	0xAF636191,	0xB2B68CFC,	0x67648C29,
+0xE9C8703F,	0x4CDCA944,	0x406D7026,	0x2BBA3EB5,	0x382963EC,	0x0ABBA19B,	0xE2BAA3BC,	0x45E7F715,
+0x28F91065,	0x77C02B68,	0x3B87A7C4,	0xF03B7259,	0xDB2CADDF,	0x26593C6B,	0x8AF1814A,	0x8F96B6FB,
+0xBCC3A90A,	0xF99A80DA,	0xDE110C49,	0xBED673D9,	0x130EE126,	0x0B93B69E,	0x7D7737C3,	0xE66BCBDB,
+0xD218C88C,	0x59BF6AC3,	0xDD06CD32,	0x4733644E,	0x6514D1BE,	0x0D5D3D84,	0x23FCFC26,	0x424CF9FD,
+0x538B6400,	0xC3ACBEEE,	0x83469CDF,	0x627D8A69,	0x3C120BDF,	0xD0D48639,	0x2CEC0A12,	0x218338EB,
+0x0BDD176F,	0x3C891030,	0xC5431FC9,	0x651A7B62,	0x60E8E5AB,	0x9F45983F,	0x33D9BACA,	0x6CB63448,
+0x86D85E5E,	0xC28E7397,	0xB954FCB3,	0x0385E1EA,	0xB7E3FC29,	0x52054F36,	0x873E9C0B,	0xFF61EECC,
+0x326A3E06,	0x35C6871E,	0x43EEA7BA,	0xCB97494B,	0x03358D9E,	0x32C1CEB6,	0xC9BF6F51,	0xD5C311F2,
+0x889FC519,	0xD573BE09,	0xDFF9585D,	0x7AE23F2F,	0xBF90825D,	0x64E32A3B,	0x8972EC9B,	0x006FE3D8,
+0x05C46F2A,	0xF37FF7B2,	0xCAC80273,	0xD79F2784,	0x2476D000,	0xD8A7752F,	0xF6A679E7,	0x3CB4C80F,
+0x7A3C01D7,	0x4EA105A4,	0x32029165,	0x39F63AE1,	0xF81147CA,	0x43230048,	0xA53080A1,	0x3EC01BA3,
+0x44A10A6C,	0xF79F603A,	0xBEAB2F4F,	0xEDDCFE14,	0xE1C51172,	0x30DFF361,	0xA46E90F7,	0x73AF0A0A,
+0x0903E05B,	0x96B0B552,	0x79E024E9,	0x88A7DBD4,	0x00AB633A,	0x72CA0DDC,	0xD0BF266D,	0x7BBF62B3,
+0x175377EF,	0x7B70283D,	0x85E78587,	0x5EFF9A7C,	0x2AAC9724,	0x512E8998,	0x53D106E5,	0x60AA3620,
+0xF881155E,	0x8A83A58C,	0x9E248734,	0x12473BC1,	0xCD8E485F,	0x7F3EF67A,	0xDEB71265,	0xF68FBB5F,
+0x87A7DFEB,	0x46F2BFA5,	0xEE2A213B,	0xB3B6F3F8,	0x724DA9AA,	0xBC19314F,	0x35EEEAB6,	0x38C6811B,
+0x6113E099,	0x9C11E04F,	0x3016D827,	0x7FA8E2DB,	0x4DB0302D,	0x2B9DFB6C,	0x2FA14FEE,	0x3F2D1E1F,
+0x7000B0ED,	0xBC6B4B1F,	0xAB02C6BD,	0x189B6F6F,	0x1AC167F8,	0x4BCAC0F0,	0x84BDB593,	0x34F20634,
+0x6C4063FC,	0x5B69D619,	0x5E329343,	0x9A1C6D66,	0x1985ADBE,	0x734B262B,	0x978CB2B5,	0x59AE9AD4,
+0x8F4BD91C,	0x1735A843,	0x98A1B996,	0x9AC8576E,	0xC36E239C,	0x10354985,	0xDD3D6D2C,	0x69994D30,
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+0x55DC0AD2,	0x0371EF63,	0xCE0EB43C,	0x141EC101,	0x8F6C05A6,	0x0D1DF470,	0xA42DCF3A,	0x2DEBA57B,
+0x82BD31A2,	0x3A243D6D,	0x567F7515,	0xBEC1533F,	0xD0AC62C3,	0xFA470B40,	0x5D2A3BE6,	0x646670DF,
+0xFE5F1200,	0x9EC09A2B,	0x47F11DD3,	0xF7590403,	0xE47B252C,	0x23D199A2,	0x4D896673,	0x4BC41B23,
+0x4278021F,	0x90E82996,	0x007C3C5A,	0xDB6C4854,	0x2FAE59D4,	0x04164760,	0xAFEAA058,	0x86BFC02C,
+0x6082C555,	0xB9B2EB5B,	0x7CB8F105,	0x7AA38B7C,	0xB8FD1B5B,	0x0EB4DCA0,	0xB516AE4A,	0x61061288,
+0x13CF4E2C,	0xE0D2D218,	0x641C2EA8,	0x0810D9B9,	0xE9A51A54,	0xA3E41E40,	0xFE702981,	0xA1B8F354,
+0x128C4E44,	0x062659EB,	0x873A928A,	0xBA1C46EF,	0x26C34637,	0x78B2D337,	0x614078B0,	0xC2F79E70,
+0x6C2DAAB5,	0xD3EFAF99,	0x6E83591F,	0x14BC5C80,	0xD96BCB5D,	0xBC0D1588,	0x9994D4FF,	0xABEA5A5F,
+0x37DC0547,	0x56A71307,	0x8E4D4A65,	0x0767D446,	0x94990CEF,	0x7DBE8230,	0xC063E3AE,	0x057726DA,
+0xE4D8CCEE,	0xA714D42F,	0x1140BF42,	0x409D0987,	0xC84722B8,	0x1F2FB59B,	0xB9CD9BF0,	0x29A33DFA,
+0xF8AC31AE,	0x05457C68,	0xEE3EB76E,	0xD163A9DA,	0xBE6BF0D4,	0x5A8616F9,	0x545B68C9,	0x120E9972,
+0xCCC19BED,	0x255EFD86,	0xC60FDF6F,	0x044EEDBA,	0x5F17A10A,	0x7EB6A3B7,	0x62135187,	0x71CDB472,
+0x9CE4C789,	0x714453F3,	0xCE593514,	0x9B527E5E,	0x5D3E21CE,	0x3D4FDB90,	0x4576C774,	0x67ED805D,
+0x61D5847F,	0xDBCFB12E,	0x4E0CC524,	0xB3D92BF4,	0x9E37A38F,	0x32412F0B,	0x3B9D1043,	0x45C85C10,
+0x3BD1A515,	0x19FD9668,	0xDC56254C,	0x411978F2,	0x2EA0560C,	0xFD04A4FE,	0x1F9E8474,	0x4544A2D2,
+0xEEFDA116,	0x6DD2BCE1,	0x6690D499,	0xEA8A0669,	0xA7271868,	0x4626A9D9,	0xE741923F,	0xB68F2ADF,
+0x1F234011,	0xFF29768E,	0xFCF5D15D,	0xEB4E8253,	0x33B5F3E0,	0xE80728DE,	0x6B261BA7,	0x005BA67D,
+0x11EECC54,	0x03FDA702,	0x13F53F65,	0x20F1401D,	0x286D4059,	0xBA6B8A7D,	0x4A6411DA,	0x0A20F086,
+0xBF471544,	0xAD32D9D6,	0xFACF6642,	0x8920FC6C,	0x29039AF7,	0x1E7B95CC,	0xAFFC82B8,	0x9F8F2B7B,
+0x575D5C7C,	0x540F3B73,	0x41101C3F,	0x63984069,	0x0F165A68,	0x1A944AE5,	0x1FBC7092,	0x8444DACE,
+0xFBA7388E,	0xF6DB0446,	0x067DF1E5,	0x94232D00,	0x5FD1940E,	0x3F3407FC,	0x709E2FC2,	0x97056DA8,
+0xF7AD2367,	0xE28A66FC,	0x2BB2A05D,	0xAA7331B2,	0x9B377EA7,	0x8B261806,	0x4729210E,	0x707855AE,
+0xCB3305D5,	0xA5BA8A25,	0xB102B865,	0xF6ACC915,	0xCFBBBB1D,	0xF7A3D1AB,	0x9C0A2AEC,	0x9AAB192A,
+0x567EF3B7,	0xC94ED2CF,	0x6D66067E,	0xF47983B7,	0x3C440BD6,	0xFF5DA5B8,	0xFB577C5A,	0x5BE08925,
+0x11A02141,	0x4D725EA0,	0xD68ADB69,	0xA2EB6B60,	0x568D2AA1,	0x981BE08B,	0xB2B33D13,	0x546B44C5,
+0xE76BF4F6,	0xCB5018C9,	0x506645CE,	0x231A95C7,	0x500FF67E,	0xFC652ABC,	0xDEB37B2C,	0xFB5FEAB7,
+0xBBDC28C4,	0x4EF10EA4,	0x674FFA04,	0x41A2E9B7,	0x06ADE38D,	0x2E9CD55D,	0x2312B550,	0x86EE49B5,
+0xA339C9F2,	0x7309C7B7,	0xD0BE4ED0,	0xD3D882B1,	0xED0C2E1D,	0x30E5DA36,	0x5E500A54,	0x70773D2F,
+0x51AC33D8,	0xA6CCCB21,	0x38C7B329,	0xB72F3DF4,	0x4FD2A223,	0x7D54A3E4,	0xC1A0405A,	0x278C4E5E,
+0x147527AD,	0xB3D23DD5,	0x28C1153B,	0xCF046310,	0xB8824B43,	0xD6B99F2F,	0x11716863,	0xF52244F5,
+0xA2D2892A,	0x3898E03A,	0x4E8AAEF4,	0x1F35150B,	0xC40C85C7,	0x278E4CDE,	0xABA76BB5,	0x1ED8CD03,
+0xAE50C0BD,	0xC1F6B5C0,	0x612BF29B,	0xAF04116D,	0x0A0BDBBD,	0x13DD7603,	0xFA520AB8,	0xAF366247,
+0x59518452,	0x787FAAA9,	0xE6B26149,	0xE584C0E3,	0x5142AFE7,	0x06340D06,	0xC3394302,	0x755D1D66,
+0x81A3DA4D,	0xCA9A01CE,	0x7D808FB6,	0x9B521E91,	0x050AF792,	0x5EB03721,	0xF71C9310,	0x1588F196,
+0x68CA25D6,	0x5EC2BF29,	0x0216A510,	0x071D0ED8,	0x14AD0E0B,	0xCA229A85,	0x4F13119B,	0xAA572358,
+0xF602E1C1,	0xF4131626,	0x747F4DD6,	0x68BC1D8A,	0xF859A58B,	0x89215DB6,	0x6DBCBD21,	0xD380D013,
+0x32DF7DAD,	0x4D0E7C91,	0xCD8A4D60,	0x5D96610A,	0x2F0D0960,	0x316ABFF7,	0x3BC5FA4C,	0x14A3CF2C,
+0x8A153A1A,	0x2870CF55,	0x0E9FA8EC,	0x3756E2F8,	0xADA02437,	0xD0676072,	0xCE8AAD88,	0xD0378108,
+0xB6DECFBB,	0x4B416368,	0x81D5FE74,	0x2F204FF9,	0x2B2B520E,	0x7C26385A,	0x549E057C,	0xBCDCC81B,
+0xAD1D8630,	0x95BFD88C,	0xDA4F1086,	0xEAFC162A,	0x2D130AB5,	0x34663942,	0xEC553367,	0x6916CC61,
+0xAE36D16F,	0x98FDBFD8,	0x34961045,	0x9AB0F7B1,	0x01E7DBA2,	0xD2EA4862,	0x22F1F602,	0xC06849B9,
+0x2B32985A,	0x7D6DBDD5,	0x4B069666,	0x7AB33A9D,	0x6C65F10B,	0x2DC8D145,	0xBC803BFD,	0xBBA97E95,
+0xBA78A360,	0x700D784D,	0xB2829C9D,	0x3D3A862C,	0x70B3AD89,	0xC687C83D,	0xA3C41719,	0x007219B0,
+0x5DB76593,	0xB02804D0,	0x1DB48EF2,	0xAD213485,	0xF6ED5385,	0xFFA5E961,	0xBF034957,	0xF1A629D7,
+0xF3E6D3A2,	0xB2077771,	0x6600CAA0,	0x08014A62,	0x26E16FAC,	0xF455176A,	0xA26E4B8C,	0x1C60D8D7,
+0xA1DB4B95,	0xD0EDF137,	0x85150791,	0x9A88BFE4,	0x6FF50DE1,	0xCC7F8D5C,	0xEBBD7552,	0x2FC83CD2,
+0xC524687B,	0x0BFCA5EB,	0xB2A60EBC,	0xC08EF816,	0x68B96617,	0xA7FFF8E1,	0xA85D57C7,	0xBBADDFF0,
+0x52519496,	0x5251FC13,	0xC4CEA0FF,	0x27E06771,	0xBF1A9964,	0x2618F9A8,	0x54CFE977,	0xF325CCDD,
+0x5F1F4017,	0xC16F50FF,	0x1CA4D98F,	0x1DA107D7,	0x1F7EF04E,	0xBDA4D86A,	0xCF748C69,	0x0BE8B6C7,
+0x7FBF325A,	0xA5EE15CD,	0xF3FAF33F,	0x19B90B23,	0x0CE4FD63,	0x882009B3,	0x6C781DF4,	0xB02B86CA,
+0xA272B039,	0x62CD9C74,	0x9B2C2CE3,	0xB1EB9CC6,	0x25C8C3E8,	0xED01FCF0,	0xEC31DE19,	0x1CC88913,
+0x5DF560D5,	0x91749BDD,	0x10CC46BB,	0xF46BD60A,	0x078B76B5,	0xAAB5C3E9,	0x60CA8EF9,	0xC6D3EEE8,
+0x9D074245,	0x2C3D5D1C,	0x714345B0,	0xC4FC7D5E,	0x41AD6820,	0x567B7382,	0x5665DE0B,	0xDC030FB7,
+0x978AA503,	0x3A42A120,	0x98C84797,	0x478461CB,	0xE5A44B0E,	0x1B19283D,	0x8F6FF924,	0x3CC9C5A5,
+0x0066FDC5,	0x533E6B43,	0x98821864,	0xE0E59E98,	0xDE121AE1,	0x9FEADBD2,	0xA9EEE36B,	0xA4B36B2A,
+0x2F45AFDA,	0x950D3FF2,	0x0E867090,	0x3024FA4D,	0x78C2C934,	0xC1600CD3,	0x5415DD7B,	0x67A44995,
+0x8A8A53E1,	0xCE95BB4D,	0x9B66BA28,	0x3D8C9876,	0x7299D3F9,	0xAF50FD77,	0x0EB94542,	0xC4001006,
+0x05C8E75B,	0x5355BC54,	0x2DB73C63,	0x9D923898,	0x92BC7511,	0x86CC56AC,	0xED93574D,	0x36CC4CC4,
+0xE8362989,	0xB7C92660,	0x7F854BE9,	0xC3214180,	0x1BBDEB13,	0x58F33CCD,	0x2F83CBF7,	0x732A0EDD,
+0x63BC358F,	0xA66D6AE2,	0x82BF9F19,	0x4B096252,	0x036D66ED,	0x6C98EE11,	0x687CCDD2,	0x7495C374,
+0xB90C489C,	0x1688D94B,	0xECFF0BCE,	0xA3185401,	0xCB6FAEEE,	0xFBCECE2F,	0xB2A3B461,	0x8C739F4A,
+0xEFDD98B6,	0x89075340,	0xC31C7226,	0xD269DD8E,	0x53FCB36F,	0x796E1C3D,	0xD33E0D30,	0xD4D941B0,
+0xBE033E0E,	0x4636FF78,	0x34A9BE67,	0x842FE639,	0xC71CCC14,	0xC17276FB,	0xFD74422D,	0x4C1DCAAD,
+0x814B0E6E,	0x1C0E0A0F,	0x04A0ACAE,	0xBED3D8B1,	0x84DF92B8,	0x519D9670,	0x7157E2CA,	0xA3BA65AA,
+0x9ED809FF,	0xFDD88464,	0xC4FFECE7,	0x06332FD2,	0xC8807C6D,	0xA41AA69A,	0xFC66E534,	0x139FA663,
+0x3662C32A,	0xA669A93E,	0xFAB2C6A5,	0xCDB799F9,	0x03105F03,	0x49ABDCCA,	0x97BDB5B4,	0x6B91E34E,
+0xEFE63394,	0xED76E2EA,	0x9A5523D1,	0x12384C0B,	0x05112E66,	0x8B6B2605,	0xFD4CEFFA,	0x00000080,
diff --git a/board/rda/common/include/coda7l_fw.h b/board/rda/common/include/coda7l_fw.h
new file mode 100644
index 0000000000..51f3efc7f8
--- /dev/null
+++ b/board/rda/common/include/coda7l_fw.h
@@ -0,0 +1,11789 @@
+#ifndef __CODA7L_FW_H__
+#define __CODA7L_FW_H__
+
+//==============================================================================
+//    BIT ASSEMBLY CODE TABLE
+//      generated with <Falcon.out>
+//      generated at Tue Jun 17 14:30:19 2014
+//==============================================================================
+static const unsigned short bit_code[94208] = {
+    0xe40e, 0x0020, 0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x0131,
+    0xe470, 0xe190, 0xe40e, 0x0113, 0xe470, 0xe190, 0xe470, 0xe190,
+    0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+    0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x012f, 0xe40e, 0x0131,
+    0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058,
+    0xa200, 0xe0c2, 0x005a, 0x3cf0, 0x3cf1, 0xa2fe, 0x3cee, 0x3cef,
+    0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d, 0xce00, 0xf11e, 0xe0c0,
+    0x005c, 0xe0c1, 0x0059, 0x3eed, 0xa203, 0x5aed, 0xe052, 0xf08a,
+    0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00, 0xe41e,
+    0x008c, 0xe41e, 0x00ab, 0xe0c0, 0x005a, 0x18ee, 0xe0c1, 0x0059,
+    0xa115, 0xb636, 0x2aee, 0xb60a, 0xe418, 0x00fb, 0xe0c0, 0x005b,
+    0xe0c1, 0x005e, 0xae11, 0xe056, 0x18ef, 0xe0c1, 0x0059, 0xa117,
+    0xb636, 0xe418, 0x00b0, 0xe0c0, 0x005a, 0x18ee, 0x2aee, 0xb60a,
+    0xe0c1, 0x0059, 0xa117, 0xb636, 0xe418, 0x00f3, 0xd071, 0x802a,
+    0xe181, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100, 0xe0c0, 0x0059,
+    0xae02, 0xe000, 0x0113, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a,
+    0x3cee, 0xe41e, 0x0100, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11,
+    0xe056, 0x3cef, 0xe40e, 0x0037, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+    0x0058, 0xe0c2, 0x0008, 0xe0c0, 0x0059, 0xf7ea, 0xa11e, 0xf0e8,
+    0xa202, 0xe0c2, 0x0058, 0xe004, 0x093d, 0xe0c2, 0x0070, 0xa200,
+    0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xf6fe, 0xa202, 0xe0c2, 0x0008,
+    0xe0c2, 0x0058, 0xe42e, 0xd101, 0x0001, 0xc70f, 0xa000, 0xe42e,
+    0xa200, 0xe0c1, 0x005b, 0xf27b, 0xa220, 0xa103, 0xf2eb, 0xa230,
+    0xa103, 0xf2bb, 0xa23c, 0xa103, 0xf24b, 0xa258, 0xa103, 0xf25b,
+    0xa260, 0xa103, 0xf22b, 0xa200, 0xa103, 0xf1fb, 0xa26c, 0xa103,
+    0xf1cb, 0xe004, 0x003e, 0xa103, 0xf18b, 0xe004, 0x0044, 0xa105,
+    0xf14b, 0xe004, 0x0046, 0xa103, 0xf10b, 0xe004, 0x0000, 0xa107,
+    0xf0cb, 0xa200, 0xe0c1, 0x005e, 0xf08b, 0xe004, 0x004c, 0xf05e,
+    0xe0c1, 0x005e, 0xf02b, 0xa010, 0xae16, 0xe0c1, 0x0040, 0xe041,
+    0xca28, 0xf7f8, 0xce21, 0xd111, 0x0000, 0xd112, 0x2000, 0xd113,
+    0x000b, 0xe1e1, 0xe42e, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100,
+    0xe004, 0x0133, 0xe67c, 0xe41e, 0x0100, 0xe004, 0x0135, 0xe67c,
+    0x28ee, 0xe008, 0x03ff, 0xcca4, 0xe182, 0x0029, 0xe018, 0x2eee,
+    0xaf15, 0xcca5, 0xe182, 0x0029, 0xe019, 0xae15, 0xe042, 0xae14,
+    0x34f0, 0x3cf1, 0xe42e, 0xe40e, 0x072a, 0xe40e, 0x0137, 0xe40e,
+    0x013b, 0xe40e, 0x013f, 0xe40e, 0x0147, 0xe40e, 0x007e, 0xe40e,
+    0x0153, 0xe40e, 0x014f, 0xe40e, 0x015b, 0xe40e, 0x007e, 0xe40e,
+    0x007e, 0xe40e, 0x007e, 0xe40e, 0x007e, 0xe40e, 0x007e, 0xe40e,
+    0x007e, 0xe40e, 0x007e, 0xe40e, 0x0449, 0xe40e, 0x045c, 0xe41e,
+    0x018a, 0xe40e, 0x007e, 0xe41e, 0x020b, 0xe40e, 0x007e, 0x284d,
+    0xa184, 0xe41e, 0x015f, 0xe41e, 0x020c, 0xe40e, 0x007e, 0x284d,
+    0xa184, 0xe41e, 0x015f, 0xe41e, 0x03a1, 0xe40e, 0x007e, 0xe41e,
+    0x03d2, 0xe40e, 0x007e, 0x284d, 0xa184, 0xe41e, 0x015f, 0xe41e,
+    0x0580, 0xe40e, 0x007e, 0xe41e, 0x0405, 0xe40e, 0x007e, 0xe428,
+    0xe0c0, 0x0040, 0xa211, 0xae17, 0xe042, 0xca29, 0xf7f9, 0xce20,
+    0xd111, 0x0000, 0xd112, 0x2000, 0xd113, 0x000b, 0xe1e1, 0xe42e,
+    0xe167, 0x05d2, 0xe166, 0x0064, 0xd022, 0x0003, 0xe184, 0x017a,
+    0x9e16, 0x3517, 0x3d17, 0xe0c0, 0x0069, 0xe167, 0x0ba0, 0x3d17,
+    0x3517, 0xe0c0, 0x006a, 0x3d17, 0x3517, 0xe0c0, 0x006b, 0x3d17,
+    0x3517, 0xe42e, 0xd152, 0x0000, 0xd130, 0x0000, 0x22f0, 0x4ef1,
+    0xa200, 0xc401, 0xe188, 0x07ff, 0x3d11, 0x36f0, 0x3ef1, 0xe41e,
+    0x03f0, 0xa2fe, 0x3c10, 0x3c20, 0x3c48, 0xe0c2, 0x0079, 0xe0c2,
+    0x007a, 0xa206, 0x3cbe, 0xa200, 0xcc44, 0x3cd6, 0x3c4e, 0x3c4b,
+    0xe0c2, 0x0072, 0xe0c2, 0x006c, 0xa202, 0xe0c2, 0x0078, 0xe0c0,
+    0x0062, 0xaf02, 0x301e, 0xaf02, 0xa806, 0x3c75, 0xe41e, 0x06a5,
+    0xe41e, 0x1318, 0xe41e, 0x1787, 0xe41e, 0x059d, 0x286d, 0xe408,
+    0x0206, 0x28a4, 0xa10e, 0xf798, 0xe41e, 0x132b, 0xe41e, 0x06d7,
+    0xe128, 0xe41e, 0x0c52, 0xf71a, 0xa2fe, 0x3c10, 0x2050, 0x4c51,
+    0xae08, 0xe0c2, 0x0071, 0xe0c2, 0x004f, 0x2850, 0xe002, 0x0080,
+    0xf2e0, 0x2851, 0xe002, 0x0080, 0xf2a0, 0x281e, 0xf0da, 0x2813,
+    0xa104, 0xf0aa, 0x28df, 0xe0c2, 0x0074, 0xa004, 0xe0c2, 0x0073,
+    0x28de, 0x3cdc, 0xf09e, 0x2816, 0xa004, 0xe0c2, 0x0073, 0xa200,
+    0xe0c2, 0x0074, 0x3cdc, 0xa200, 0x3c6d, 0x285d, 0xae04, 0x4c1a,
+    0xae02, 0x4c18, 0xae10, 0x4c1c, 0xae10, 0x4c4d, 0xe0c2, 0x007b,
+    0xe41e, 0x065c, 0xa202, 0xe0c2, 0x0070, 0xe42e, 0xa200, 0x3c6d,
+    0xe0c2, 0x0070, 0xe42e, 0xe42e, 0xa2fe, 0xe0c2, 0x004c, 0xe0c2,
+    0x004d, 0xe0c2, 0x004e, 0xe0c2, 0x007b, 0xa200, 0xcc44, 0xcc4a,
+    0xcc4c, 0x3c4c, 0x3c55, 0xe0c2, 0x007a, 0x3c5c, 0xd14b, 0x0200,
+    0xa2fc, 0xe0c2, 0x0077, 0xa202, 0xe0c2, 0x0076, 0x286e, 0xf07a,
+    0xe41e, 0x0754, 0xe41e, 0x0586, 0xa200, 0x3c6e, 0xe41e, 0x0f0a,
+    0xf05a, 0xa202, 0x3c6c, 0xe40e, 0x0332, 0x2875, 0xa802, 0xf06a,
+    0xa200, 0x3c69, 0x3c6b, 0xe41e, 0x067d, 0xe41e, 0x12e3, 0xd152,
+    0x0000, 0xd130, 0x0000, 0xd1e0, 0x0003, 0xd1ff, 0x03b0, 0xd1fd,
+    0x03d0, 0xd199, 0x0224, 0xd1fc, 0x0700, 0xd03a, 0x0000, 0xd04c,
+    0x0000, 0xd008, 0x0000, 0x288e, 0xf10a, 0x288f, 0xf1c2, 0x28db,
+    0xe41a, 0x129b, 0xe41e, 0x17cd, 0x28c1, 0x3c8f, 0x3c39, 0x2848,
+    0xe412, 0x17ed, 0xe40e, 0x0332, 0xe41e, 0x17c1, 0xf048, 0xa2ff,
+    0xe0c3, 0x0077, 0xf03a, 0x286c, 0xf06a, 0x2848, 0xe412, 0x17ed,
+    0xe40e, 0x0332, 0xa2fc, 0xe0c2, 0x0077, 0xa200, 0x3caa, 0x3cab,
+    0x288e, 0xf038, 0x28c1, 0x3cbf, 0xa202, 0x3c49, 0x288e, 0xf0da,
+    0x288a, 0x3ca3, 0x288b, 0x3ca5, 0x288f, 0x3cc1, 0xe41e, 0x04d1,
+    0xe41e, 0x0bb2, 0xe40e, 0x02dc, 0xe41e, 0x059d, 0x28a4, 0xf7da,
+    0xa102, 0xe40a, 0x02dc, 0xa108, 0xf784, 0xe40a, 0x02dc, 0xa102,
+    0xf17a, 0xa102, 0xf0fa, 0xa102, 0xf10a, 0xa102, 0xf14a, 0xa102,
+    0xf16a, 0xa102, 0xf14a, 0xa102, 0xf2aa, 0xa10e, 0xf662, 0xe40e,
+    0x02da, 0xe41e, 0x132b, 0xf2fe, 0xe41e, 0x1356, 0xf2ce, 0xe41e,
+    0x0f12, 0xf29e, 0xba44, 0xe41e, 0x0862, 0xf25e, 0x2875, 0xa802,
+    0xe408, 0x0398, 0x286b, 0xf0ca, 0x2875, 0xa802, 0xe016, 0x3c6c,
+    0xe41e, 0x051d, 0x2848, 0xe412, 0x17ed, 0xe40e, 0x0332, 0x287f,
+    0xf038, 0x287d, 0xf03a, 0xa202, 0x3ca9, 0xf0de, 0xba0e, 0xe002,
+    0x00ff, 0xf058, 0xba4e, 0xe41e, 0x05e9, 0xf798, 0xe41e, 0x0862,
+    0xe40e, 0x028c, 0xe40e, 0x028c, 0xe165, 0x07c8, 0x28a5, 0x3d15,
+    0x28a3, 0x3d15, 0x2830, 0x3d15, 0x28d3, 0x3d15, 0x288e, 0xf098,
+    0xa2fe, 0x3cc1, 0xe41e, 0x08f5, 0x2a57, 0xa003, 0xe40b, 0x0398,
+    0x2a7e, 0xa103, 0xe40b, 0x0332, 0xe40a, 0x028c, 0x28a3, 0x3c84,
+    0x28a5, 0x3c85, 0x2a3b, 0x28bf, 0x18c1, 0xf0ca, 0x28be, 0xa106,
+    0xf0aa, 0xe41e, 0x04e6, 0xe41e, 0x04fb, 0x2848, 0xe412, 0x17ed,
+    0xf2ae, 0x4ebe, 0x3ebe, 0xa200, 0x3c49, 0x3c8e, 0xe41e, 0x186e,
+    0x282f, 0xa002, 0x3c2f, 0x28a3, 0x4c34, 0xf048, 0x28c1, 0xe41e,
+    0x178d, 0x28a3, 0xe418, 0x1461, 0x2834, 0xe41a, 0x1143, 0x2834,
+    0xaa02, 0x4432, 0xe41a, 0x1176, 0x28d3, 0x3cd7, 0xe41e, 0x065c,
+    0x2832, 0xf09a, 0x2a75, 0xf04b, 0x2834, 0xe41a, 0x0549, 0x2834,
+    0xe40a, 0x0278, 0x286c, 0xf04a, 0xe41e, 0x1296, 0x3cdc, 0xe41e,
+    0x119f, 0xf032, 0x2a6c, 0xb7b6, 0xe049, 0x1ad4, 0xf045, 0xa2fa,
+    0x2a6b, 0xb7f2, 0xe0c2, 0x0071, 0xe0c0, 0x0071, 0x3c48, 0xa200,
+    0x2a48, 0xf0f4, 0x3e0a, 0xaf09, 0x2072, 0x4c73, 0xf06b, 0x2070,
+    0x4c71, 0x2a0a, 0xa81f, 0x3e0a, 0x5c0a, 0x5c0a, 0xa806, 0xae20,
+    0x2a5c, 0xae13, 0x4e33, 0xae05, 0x4e19, 0xae03, 0x4e32, 0xae21,
+    0x4e55, 0xae05, 0xe056, 0x4c30, 0xe0c2, 0x0073, 0x2a48, 0xf1b5,
+    0xaf09, 0xf0fb, 0x2070, 0x4c71, 0x2a48, 0xa81f, 0x3e0a, 0xa207,
+    0x5a0a, 0x5a0a, 0xe013, 0xa103, 0xe052, 0x3470, 0x3c71, 0xf0be,
+    0x2072, 0x4c73, 0xa207, 0x5a48, 0x5a48, 0xe013, 0xa103, 0xe052,
+    0x3472, 0x3c73, 0x284c, 0xe0c2, 0x0072, 0x2c4b, 0xa002, 0x3c4b,
+    0xe0c2, 0x0070, 0xa200, 0x3c7e, 0xc84a, 0xc84d, 0xae20, 0xe056,
+    0xe0c2, 0x0053, 0xe41e, 0x1301, 0xe41e, 0x0563, 0xa202, 0xe42e,
+    0xe41e, 0x1301, 0xa2fe, 0xe0c2, 0x0072, 0xa200, 0xe0c2, 0x0076,
+    0xe42e, 0xd152, 0x0000, 0xd130, 0x0000, 0xe41e, 0x0170, 0xca28,
+    0xf7f8, 0xe0c0, 0x0060, 0xe42a, 0xe0c0, 0x0042, 0xce20, 0xd111,
+    0x0620, 0xd112, 0x0100, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe0c0,
+    0x0042, 0xe000, 0x1000, 0xce20, 0xd111, 0x0ba8, 0xd112, 0x004c,
+    0xd113, 0x0003, 0xca28, 0xf7f8, 0xa200, 0xe41e, 0x0c0a, 0xe004,
+    0x0040, 0xe41e, 0x0c0a, 0xe0c0, 0x0060, 0x3cd4, 0xe0c0, 0x0061,
+    0x3c67, 0xe42e, 0xca28, 0xf7f8, 0xe0c0, 0x0042, 0xce20, 0xd111,
+    0x0000, 0xd112, 0x0080, 0xd113, 0x0013, 0xca28, 0xf7f8, 0xe0c0,
+    0x0061, 0x3ca7, 0xa202, 0x3ca6, 0xe41e, 0x06d7, 0xe128, 0xe0c0,
+    0x0060, 0xf048, 0xe41e, 0x132b, 0xf03e, 0xe41e, 0x1356, 0xe42e,
+    0xe0c0, 0x0040, 0xa201, 0xae17, 0xe042, 0xe005, 0x3f00, 0xae03,
+    0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0450, 0xd112, 0x00c8,
+    0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0060, 0xf08a,
+    0xe0c0, 0x0061, 0x2298, 0x4e99, 0xe046, 0xaf12, 0xae02, 0x3c9b,
+    0xe180, 0xe41e, 0x06d7, 0xe41e, 0x0799, 0xe41e, 0x1318, 0xe41e,
+    0x1787, 0xe41e, 0x0539, 0x28de, 0x2a1e, 0xb616, 0x3cdc, 0xa200,
+    0x3cd6, 0x3cda, 0x3cd9, 0x3cdb, 0x3cd8, 0xe166, 0x05ab, 0xc710,
+    0x3d16, 0xe166, 0x0054, 0x9e06, 0xf16a, 0x28d4, 0xa102, 0xcc44,
+    0xa200, 0x3c68, 0xe184, 0x0440, 0x9e06, 0x5c68, 0xa802, 0xf07a,
+    0x2868, 0xe000, 0x0518, 0xe09e, 0xa208, 0x3d07, 0x2868, 0xa002,
+    0x3c68, 0xe190, 0xa200, 0x3c63, 0xe41e, 0x06e8, 0xa202, 0x3c6e,
+    0xe42e, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100, 0xa206, 0xe41e,
+    0x0465, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100, 0xa236, 0xe41e,
+    0x047b, 0xe41e, 0x0491, 0xe42e, 0xa234, 0xe41e, 0x047b, 0xe41e,
+    0x04b1, 0xa204, 0xe41e, 0x0465, 0xe42e, 0x3ced, 0xe0c0, 0x0041,
+    0xe005, 0x0280, 0xae11, 0xe042, 0x22f0, 0x4ef1, 0xe042, 0xca29,
+    0xf7f9, 0xce20, 0xd111, 0x0000, 0xd112, 0x0c00, 0x88ed, 0x0113,
+    0xca28, 0xf7f8, 0xe42e, 0x3ced, 0xe0c0, 0x0041, 0xe005, 0x0298,
+    0xae11, 0xe042, 0x22f0, 0x4ef1, 0xe042, 0xca29, 0xf7f9, 0xce20,
+    0xd111, 0x00c0, 0xd112, 0x0040, 0x88ed, 0x0113, 0xca28, 0xf7f8,
+    0xe42e, 0xe161, 0x07e0, 0x8911, 0x0145, 0x8911, 0x0144, 0x8911,
+    0x0146, 0x8911, 0x0147, 0x8911, 0x0148, 0x8911, 0x0152, 0x8911,
+    0x0153, 0x2111, 0x4d11, 0xce80, 0x2111, 0x4d11, 0xce82, 0x2111,
+    0x4d11, 0xce84, 0x2111, 0x4d11, 0xce86, 0x2111, 0x4d11, 0xcc72,
+    0xe42e, 0xe161, 0x07e0, 0x8b11, 0x0145, 0x8b11, 0x0144, 0x8b11,
+    0x0146, 0x8b11, 0x0147, 0x8b11, 0x0148, 0x8b11, 0x0152, 0x8b11,
+    0x0153, 0xca80, 0x3511, 0x3d11, 0xca82, 0x3511, 0x3d11, 0xca84,
+    0x3511, 0x3d11, 0xca86, 0x3511, 0x3d11, 0xc872, 0x3511, 0x3d11,
+    0xe42e, 0xe165, 0x07cc, 0x2915, 0x3c30, 0x2915, 0x3c32, 0x2915,
+    0x3c3b, 0x2915, 0x3c33, 0x2915, 0x3c34, 0x2915, 0x3c3a, 0x2915,
+    0x2915, 0x2915, 0x3c3c, 0x2915, 0x3cd3, 0xe42e, 0xe165, 0x07cc,
+    0x2830, 0x3d15, 0x2832, 0x3d15, 0x283b, 0x3d15, 0x2833, 0x3d15,
+    0x2834, 0x3d15, 0x283a, 0x3d15, 0x3d15, 0x3d15, 0x283c, 0x3d15,
+    0x28d3, 0x3d15, 0xe42e, 0xa202, 0x3c8e, 0x28a3, 0x3c8a, 0x28a5,
+    0x3c8b, 0x28c1, 0x3c8f, 0xe165, 0x07c8, 0x2915, 0x3ca5, 0x2915,
+    0x3ca3, 0x2915, 0x3c30, 0x2915, 0x3cd3, 0xa202, 0x3c32, 0x3c34,
+    0x3ca5, 0x28be, 0xa802, 0x3c33, 0xa200, 0x3c3a, 0x3c52, 0xe41e,
+    0x051d, 0x28be, 0x4c3b, 0x3cbe, 0xe42e, 0x28be, 0xaa06, 0x3c3b,
+    0x2abf, 0x3ec1, 0x3e0a, 0xaf09, 0x2072, 0x4c73, 0xf06b, 0x2070,
+    0x4c71, 0x2a0a, 0xa81f, 0x3e0a, 0x2a3b, 0x5a0a, 0x5a0a, 0xe056,
+    0x2ac1, 0xaf09, 0xf04b, 0x3470, 0x3c71, 0xe42e, 0x3472, 0x3c73,
+    0xe42e, 0xe161, 0x0100, 0xa200, 0xc73f, 0x3d11, 0x3c68, 0xd022,
+    0x000f, 0xe184, 0x0547, 0xe41e, 0x178d, 0x2868, 0xa002, 0x3c68,
+    0xe42e, 0xe0c0, 0x005c, 0xe008, 0x0400, 0xe42a, 0xe004, 0x0400,
+    0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00, 0xe0c0,
+    0x005d, 0xe008, 0x0400, 0xe190, 0xf7b8, 0xa200, 0x3c69, 0x3c6b,
+    0xe41e, 0x067d, 0xe42e, 0xe167, 0x0518, 0xa200, 0x3c68, 0xd022,
+    0x0007, 0xe184, 0x0571, 0x2b17, 0xa81f, 0x5a68, 0xe056, 0x2a68,
+    0xa009, 0x3e68, 0xa200, 0x3c68, 0xd022, 0x0007, 0xe184, 0x057e,
+    0x2b17, 0xa81f, 0x5a68, 0xe056, 0x2a68, 0xa009, 0x3e68, 0xe42e,
+    0xa200, 0x3c69, 0x3c6b, 0x3c6c, 0x3c4b, 0xe42e, 0xd146, 0x00c0,
+    0xd147, 0x00ff, 0xd148, 0x00c0, 0xd144, 0x00c0, 0xd145, 0x0000,
+    0xd14b, 0x0200, 0xe004, 0x0180, 0xce30, 0xca32, 0xca32, 0xce84,
+    0xca32, 0xce86, 0xd144, 0x00c1, 0xe42e, 0xcaa2, 0xaf10, 0xa102,
+    0xf09a, 0xcaa0, 0xe190, 0x286d, 0xe428, 0xca9c, 0xe418, 0x0754,
+    0xf75e, 0xcaa0, 0xe190, 0xcaa0, 0xe190, 0xcaa0, 0xe190, 0xcaa0,
+    0x3c00, 0xca9c, 0xe418, 0x0754, 0x2800, 0xaf0e, 0xf6b8, 0x2800,
+    0xaf0a, 0x3ca3, 0x2800, 0xa83e, 0x3ca4, 0x2a49, 0xf04b, 0xa10a,
+    0xe016, 0x3ca5, 0xa200, 0x3ca8, 0x3ca7, 0x3ca0, 0xe41e, 0x05cc,
+    0xe41e, 0x06d7, 0xe128, 0xe42e, 0x28a0, 0x44a1, 0xf048, 0xd149,
+    0x0000, 0xf03e, 0xd149, 0x0080, 0xd14a, 0x0000, 0xd14c, 0x0001,
+    0xca9c, 0xe418, 0x0754, 0xca9a, 0xf7c8, 0xca9c, 0xf7a8, 0xca9e,
+    0x3ca6, 0xcc92, 0xca94, 0x00a8, 0x0ca7, 0x34a8, 0x3ca7, 0xcc90,
+    0xe42e, 0x28a6, 0xe016, 0xc871, 0xa011, 0xe428, 0xaf07, 0xe009,
+    0x07ff, 0x28a7, 0xe008, 0x07ff, 0xe046, 0xf15a, 0xf0de, 0xe161,
+    0x05e1, 0x2901, 0xc871, 0xa011, 0xaf07, 0xe009, 0x07ff, 0xe008,
+    0x07ff, 0xe046, 0xf08a, 0xe049, 0xe011, 0xaf15, 0xe421, 0xe420,
+    0xa200, 0xe42e, 0xc868, 0xa80e, 0xf028, 0xa210, 0x3c95, 0x7895,
+    0xa203, 0x5a95, 0xaf03, 0xe046, 0xe42e, 0x28a3, 0x2aa5, 0x3c8a,
+    0x3e8b, 0x28a7, 0x2aa6, 0x3c8c, 0x3e8d, 0xa202, 0x3c86, 0xe0c0,
+    0x0041, 0x22f0, 0x4ef1, 0xe042, 0xe005, 0x029c, 0xae11, 0xe042,
+    0xca29, 0xf7f9, 0xce20, 0xd111, 0x0000, 0xd112, 0x0080, 0xd113,
+    0x0012, 0xca28, 0xf7f8, 0xca2c, 0xf7fa, 0xe42e, 0x288a, 0x2a8b,
+    0x3ca3, 0x3ea5, 0x288c, 0x2a8d, 0x3ca7, 0x3ea6, 0xcc90, 0xcc93,
+    0xa200, 0x3c86, 0x3ca8, 0x3ca0, 0xe0c0, 0x0041, 0x22f0, 0x4ef1,
+    0xe042, 0xe005, 0x029c, 0xae11, 0xe042, 0xca29, 0xf7f9, 0xce20,
+    0xd111, 0x0000, 0xd112, 0x0080, 0xd113, 0x0013, 0xca28, 0xf7f8,
+    0xe41e, 0x06d7, 0xe128, 0xe42e, 0xe0c0, 0x0048, 0xe002, 0x0200,
+    0xca89, 0xe003, 0x00c0, 0xa105, 0xae07, 0xe042, 0xca8b, 0xe015,
+    0xa80f, 0xe042, 0xa002, 0x2298, 0x4e99, 0xe045, 0xf047, 0x2e9a,
+    0xae11, 0xe042, 0xe0c1, 0x0048, 0xe045, 0xe003, 0x0200, 0xf037,
+    0xe000, 0x0200, 0xe0c2, 0x0046, 0xe42e, 0xa200, 0x3c9b, 0x2875,
+    0xaf02, 0xa802, 0xf05a, 0xe0c0, 0x0068, 0x3498, 0x3c99, 0x2098,
+    0x4c99, 0xe0c1, 0x0067, 0xe042, 0xe0c1, 0x0069, 0xa80f, 0xf02b,
+    0xe042, 0xe005, 0x0049, 0xe093, 0x9f01, 0xe004, 0xffff, 0x3c9a,
+    0xe41e, 0x06d7, 0xe41e, 0x0799, 0xa200, 0x3c63, 0xe41e, 0x06e8,
+    0xe41e, 0x0754, 0xe41e, 0x0586, 0xe42e, 0xa200, 0x3c9b, 0xe0c0,
+    0x0062, 0xaf0c, 0xa802, 0xf10a, 0xe0c1, 0x0048, 0xe0c0, 0x0060,
+    0xe045, 0xaf13, 0xae03, 0xa109, 0x3e9b, 0xf063, 0xe0c0, 0x0061,
+    0xae04, 0xe042, 0x3c9b, 0xe0c0, 0x0060, 0x3498, 0x3c99, 0xe0c0,
+    0x0061, 0xae04, 0x3c9a, 0xe41e, 0x06d7, 0xe41e, 0x0799, 0xa200,
+    0x3c69, 0x3c6a, 0x3c6b, 0x3c6c, 0x3c63, 0xe41e, 0x06e8, 0xd071,
+    0x802a, 0xe181, 0xe41e, 0x0754, 0xe41e, 0x0586, 0xe42e, 0xd030,
+    0x0000, 0xd034, 0x0000, 0xd033, 0x0000, 0xd035, 0x0000, 0xd036,
+    0x007f, 0xd037, 0x0000, 0xd038, 0x0000, 0xd04b, 0x0001, 0xe42e,
+    0x3c64, 0xe08e, 0x3c65, 0xe41e, 0x06f4, 0xe41e, 0x070f, 0x2865,
+    0xe09e, 0x2864, 0x3c63, 0xe42e, 0x2863, 0xae08, 0xe000, 0x0538,
+    0xe09e, 0x8b17, 0x0033, 0x8b17, 0x0034, 0x8b17, 0x0035, 0x8b17,
+    0x0036, 0x8b17, 0x0037, 0x8b17, 0x0038, 0xc860, 0x3517, 0x3d17,
+    0xc862, 0x3517, 0x3d17, 0xc864, 0x3517, 0x3d17, 0xe42e, 0x2864,
+    0xae08, 0xe000, 0x0538, 0xe09e, 0x8917, 0x0033, 0x8917, 0x0034,
+    0x8917, 0x0035, 0x8917, 0x0036, 0x8917, 0x0037, 0x8917, 0x0038,
+    0x2117, 0x4d17, 0xcc60, 0x2117, 0x4d17, 0xcc62, 0x2117, 0x4d17,
+    0xcc64, 0xe42e, 0xc000, 0x2863, 0xe408, 0x1380, 0x28a6, 0xf188,
+    0x28a0, 0xf068, 0xe41e, 0x05cc, 0xd04c, 0x0000, 0xe470, 0xc896,
+    0xf05a, 0xe41e, 0x074a, 0xd04c, 0x0000, 0xe004, 0x0080, 0x2aa1,
+    0xb616, 0xcc6e, 0xd04b, 0x0001, 0xa202, 0x3ca2, 0xe470, 0xd04c,
+    0x0000, 0xe470, 0xa200, 0x3ca2, 0xe41e, 0x05cc, 0x28a6, 0xcc96,
+    0x28a1, 0xe016, 0x3ca1, 0xe42e, 0x286b, 0xf0ba, 0xe004, 0x0180,
+    0xce30, 0xe41e, 0x07e6, 0xe41e, 0x0809, 0xd14e, 0x0000, 0xe42e,
+    0xe082, 0x3c9c, 0xe004, 0x0048, 0xe092, 0xd027, 0x0000, 0x2869,
+    0xe41a, 0x07a3, 0xd027, 0x0001, 0x286d, 0xf278, 0xca28, 0xf7f8,
+    0x2098, 0x4c99, 0x2e9b, 0xae11, 0xe042, 0xce20, 0xd111, 0x00c0,
+    0xd112, 0x0040, 0xe0c0, 0x0043, 0xa806, 0xae02, 0xa032, 0xce26,
+    0xca28, 0xf7f8, 0x2c9b, 0xe000, 0x0002, 0x3c9b, 0x1c9a, 0xf024,
+    0x3c9b, 0xf052, 0x2869, 0x3c6b, 0xe418, 0x07eb, 0x2098, 0x4c99,
+    0x2e9b, 0xae11, 0xe042, 0x9f01, 0x289c, 0xe092, 0xd14e, 0x0000,
+    0xe42e, 0x2098, 0x4c99, 0x2e9b, 0xae11, 0xe042, 0xe005, 0x0048,
+    0xe093, 0x9f01, 0xe42e, 0xe0c1, 0x0043, 0xa809, 0xe429, 0xa200,
+    0x3c9d, 0x2098, 0x4c99, 0x2e9b, 0xae11, 0xe042, 0x8111, 0x9e89,
+    0xe045, 0xf043, 0x2c9a, 0xae10, 0xe041, 0xe003, 0x0200, 0x2869,
+    0xb606, 0x3c69, 0xe423, 0xe001, 0x0200, 0x3e6a, 0x2869, 0xe428,
+    0xe0c0, 0x0045, 0xaf04, 0xa802, 0x3c69, 0xf648, 0x2875, 0xa802,
+    0xf03a, 0x3c69, 0xe42e, 0xe0c0, 0x0059, 0xa102, 0xf068, 0xe0c0,
+    0x0045, 0x306d, 0x286d, 0xe428, 0x289d, 0xf548, 0xe0c0, 0x005c,
+    0xe008, 0x4000, 0xf4fa, 0xe0c0, 0x005d, 0xe00a, 0x4000, 0xe0c2,
+    0x005d, 0xa202, 0xce00, 0x3c9d, 0xe40e, 0x07a9, 0xcbe1, 0xf7f9,
+    0xcba1, 0xf7f9, 0xe42e, 0x286a, 0xe42a, 0xe41e, 0x07e6, 0xaf04,
+    0xe000, 0x0180, 0xce30, 0x286a, 0xa806, 0xf10a, 0xa209, 0xe045,
+    0xae07, 0x3e0a, 0xa2ff, 0x5a0a, 0xca32, 0xca32, 0xe051, 0xca30,
+    0xa104, 0xe008, 0x01ff, 0xce30, 0xce33, 0xe005, 0x01f0, 0x1a6a,
+    0xf095, 0xe004, 0x010b, 0xce32, 0xa200, 0xce32, 0xce32, 0xce32,
+    0xe42e, 0xa021, 0xaf05, 0xe42b, 0xa200, 0xce32, 0xa103, 0xf7e1,
+    0xe42e, 0xba0c, 0xf03a, 0xbcfc, 0xe42e, 0xba4c, 0xa20c, 0x3c96,
+    0x2896, 0xa002, 0x3c96, 0xa140, 0xf0d2, 0xba40, 0xf7aa, 0x5896,
+    0xa102, 0x349e, 0x3c9f, 0x2896, 0xe41e, 0x0856, 0x009e, 0x0c9f,
+    0xe42e, 0xe16b, 0xe42e, 0xba0c, 0xf03a, 0xbe7e, 0xe42e, 0xba4c,
+    0xa20c, 0x3c96, 0x2896, 0xa002, 0x3c96, 0xa140, 0xf162, 0xba40,
+    0xf7aa, 0x5896, 0xa102, 0x349e, 0x3c9f, 0x2896, 0xe41e, 0x0856,
+    0x009e, 0x0c9f, 0x3c9f, 0x8c9f, 0x0000, 0xa002, 0xaf02, 0xe012,
+    0xe42c, 0xe012, 0xe16a, 0xe42e, 0xe16b, 0xe42e, 0xa120, 0xf050,
+    0xa020, 0x3c97, 0x7497, 0xe42e, 0x3c97, 0xba5e, 0x5897, 0x7697,
+    0xe056, 0xe42e, 0xba40, 0xe42a, 0xc868, 0xa80e, 0x3c00, 0xe016,
+    0xe428, 0x7400, 0xe016, 0xe42e, 0x2a30, 0xa103, 0x2826, 0xe425,
+    0xf02b, 0x2827, 0xb7f4, 0xa002, 0x3c46, 0xa104, 0xe424, 0xf04a,
+    0xa25a, 0x3c47, 0xe42e, 0xbc0e, 0x3c00, 0xe42d, 0x281f, 0xf02a,
+    0xbc0e, 0x3c01, 0xe42d, 0x2801, 0xae06, 0x4c00, 0x3c47, 0xe161,
+    0x0708, 0xe164, 0x0700, 0x8840, 0x0022, 0xe41e, 0x089d, 0xe42d,
+    0x2830, 0xa104, 0xe428, 0x2841, 0xe161, 0x0768, 0xe164, 0x0704,
+    0x8841, 0x0022, 0xe41e, 0x089d, 0xe42e, 0xe082, 0xa040, 0xe094,
+    0xa040, 0xe096, 0xe004, 0x00ff, 0x3c03, 0xa200, 0x3c05, 0x3c06,
+    0x3c07, 0x3c08, 0x3c09, 0xe184, 0x08e9, 0xba40, 0xf0ba, 0xe0c6,
+    0x0080, 0x4403, 0xae10, 0xe0c7, 0x0080, 0x4603, 0xe056, 0x3d11,
+    0xf0ce, 0xa202, 0x5800, 0xae10, 0x3d11, 0x2206, 0x4e07, 0xa202,
+    0x5805, 0xe056, 0x3406, 0x3c07, 0x281f, 0xf22a, 0xba40, 0xf14a,
+    0xe0c6, 0x0080, 0x4403, 0xae10, 0xe0c7, 0x0080, 0x4603, 0xe056,
+    0x3d12, 0xe0c6, 0x0080, 0x4403, 0xae10, 0xe0c7, 0x0080, 0x4603,
+    0xe056, 0x3d13, 0xf0de, 0xa202, 0x5801, 0xae10, 0x3d12, 0x3d13,
+    0x2208, 0x4e09, 0xa202, 0x5805, 0xe056, 0x3408, 0x3c09, 0x2805,
+    0xa002, 0x3c05, 0x2006, 0x4c07, 0xe014, 0x3514, 0x3d14, 0x2208,
+    0x4e09, 0xe015, 0x3714, 0x3f14, 0xe42e, 0xe0c4, 0x3fff, 0xe40d,
+    0x0aa7, 0x3c4a, 0x284a, 0xe01a, 0x4488, 0xe408, 0x0aa7, 0x2a7f,
+    0xf039, 0x2a89, 0xf03b, 0xe408, 0x0aa7, 0xa200, 0x3c89, 0xbc12,
+    0xe40d, 0x0aa7, 0xa10a, 0xb4a8, 0xa104, 0xe400, 0x0aa7, 0xb7b4,
+    0xa006, 0x3c30, 0x2849, 0xf0da, 0xbdfe, 0xe40d, 0x0aa7, 0x1820,
+    0xf0ea, 0x0820, 0x3c20, 0xe41e, 0x136a, 0xe40a, 0x0aa7, 0xf07e,
+    0xbdfe, 0xe40d, 0x0aa7, 0x1820, 0xe408, 0x0aa3, 0x2849, 0xf04a,
+    0x7411, 0x3c31, 0xf05e, 0x7411, 0x1831, 0xe408, 0x0aa3, 0x2849,
+    0xf0ca, 0xa200, 0x3c32, 0x3c33, 0x2818, 0xf138, 0xba40, 0x3c32,
+    0xf10a, 0xba40, 0x3c33, 0xf0de, 0x2818, 0xf0b8, 0xba40, 0x1832,
+    0xe408, 0x0aa3, 0x2832, 0xf05a, 0xba40, 0x1833, 0xe408, 0x0aa3,
+    0x2849, 0xf2aa, 0x281b, 0x5c32, 0x3c3c, 0xa200, 0x3c34, 0x2832,
+    0xf10a, 0xe41e, 0x0ab4, 0x3c34, 0xe016, 0x3c35, 0xf0aa, 0xa202,
+    0x3c35, 0x28a3, 0xe01a, 0x3c36, 0x2831, 0x3c37, 0x2833, 0x3c38,
+    0x2832, 0xe016, 0x4419, 0x3c3a, 0x2832, 0x0833, 0xb674, 0x3c3b,
+    0xa106, 0xf0aa, 0xa202, 0x5830, 0x2a3b, 0xa105, 0xf029, 0xae06,
+    0x2a55, 0xe055, 0x3e55, 0x2849, 0xe40a, 0x09ce, 0x287e, 0xa104,
+    0xe40a, 0x09cc, 0x2875, 0xa802, 0xf26a, 0xe0c0, 0x0065, 0xa808,
+    0xf108, 0x3c7f, 0xe0c0, 0x0065, 0xaf06, 0xa806, 0xe40a, 0x09cc,
+    0xa102, 0xf07a, 0xa102, 0xf02a, 0xf09e, 0x28a3, 0xf07a, 0xf3de,
+    0xa202, 0x3c7f, 0x28a5, 0xf02a, 0xf38e, 0xa2fa, 0xe0c2, 0x0071,
+    0x2855, 0xae04, 0x4c30, 0x2a5c, 0xae3d, 0xe056, 0xe0c2, 0x0073,
+    0xa200, 0xe42e, 0x287f, 0xf0fa, 0x28a5, 0xf21a, 0x284a, 0xf1f8,
+    0x287c, 0xf23a, 0x2a32, 0xf04b, 0x2a34, 0xe409, 0x09b0, 0xa102,
+    0x3c7c, 0xf15e, 0x287d, 0xf19a, 0xa102, 0xf06a, 0xa102, 0xf060,
+    0x28a3, 0xf04a, 0xf12e, 0x28a5, 0xf108, 0x287c, 0x2a32, 0xf04b,
+    0x2a34, 0xe409, 0x09c4, 0xa102, 0xf04a, 0x3c7c, 0xa200, 0xe42e,
+    0xa202, 0x3c89, 0x3c7e, 0xe42e, 0xa204, 0x3c7e, 0x2849, 0xf09a,
+    0x28a5, 0xf10a, 0xe41e, 0x0819, 0xe40d, 0x0aa7, 0x3c3d, 0xf0ae,
+    0x28a5, 0xf08a, 0xe41e, 0x0819, 0xe40d, 0x0aa7, 0x1c3d, 0xe408,
+    0x0aa3, 0x2849, 0xf10a, 0xe41e, 0x1100, 0x28c8, 0xe008, 0x03ff,
+    0x2a3b, 0xa105, 0xf029, 0xae14, 0xe0c1, 0x007a, 0xe055, 0xe0c3,
+    0x007a, 0xf2de, 0x2813, 0xa102, 0xf034, 0xf13a, 0xf28e, 0x7414,
+    0x1ce3, 0xe408, 0x0aa3, 0x2832, 0xe016, 0x4422, 0xf20a, 0xe41e,
+    0x0833, 0xe40d, 0x0aa7, 0x10e4, 0x1ce5, 0xe408, 0x0aa3, 0xf17e,
+    0x2815, 0xf158, 0xe41e, 0x0833, 0xe40d, 0x0aa7, 0x10e3, 0x1ce4,
+    0xe408, 0x0aa3, 0x2832, 0xe016, 0x4422, 0xf09a, 0xe41e, 0x0833,
+    0xe40d, 0x0aa7, 0x10e5, 0x1ce6, 0xe408, 0x0aa3, 0x2830, 0xa104,
+    0xf038, 0xba40, 0x3c3e, 0x2824, 0x3c40, 0x2825, 0x3c41, 0x2830,
+    0xf0ea, 0xba40, 0xf0ca, 0xbc3e, 0x3c40, 0xe40d, 0x0aa7, 0x2830,
+    0xa104, 0xf058, 0xbc3e, 0x3c41, 0xe40d, 0x0aa7, 0x2849, 0xf0ba,
+    0x2834, 0xf078, 0xe41e, 0x17cd, 0x28c1, 0xf054, 0x3c39, 0xf03e,
+    0x2839, 0x3cc1, 0x2849, 0xf05a, 0xe41e, 0x1451, 0xe41e, 0x0ace,
+    0x2830, 0xe016, 0xe41a, 0x0ad7, 0xe40a, 0x0aa7, 0xe41e, 0x086c,
+    0xe40d, 0x0aa7, 0x2849, 0xf06a, 0xe41e, 0x0ffb, 0xe40a, 0x0aa7,
+    0xf1fe, 0x28a3, 0xf1da, 0x28a5, 0xf04a, 0xba40, 0xba40, 0xf18e,
+    0xba40, 0xf16a, 0xbc0c, 0xe40d, 0x0aa7, 0xf12a, 0xa106, 0xf08a,
+    0xa104, 0xf79a, 0xe41e, 0x0819, 0xe40d, 0x0aa7, 0xf74e, 0xe41e,
+    0x0819, 0xe40d, 0x0aa7, 0xbc40, 0xe40d, 0x0aa7, 0xf6ce, 0x2830,
+    0xe01a, 0x4421, 0xf03a, 0xbc04, 0xf2bd, 0x3c3f, 0xe0c6, 0x0033,
+    0xf27d, 0x0828, 0xa400, 0xa566, 0x3c42, 0xa200, 0x3c43, 0x3c44,
+    0x3c45, 0x282a, 0xf10a, 0xbc04, 0xf1bd, 0x3c43, 0xa102, 0xf0ba,
+    0xbe0c, 0xf16d, 0xae02, 0xa83e, 0x3c44, 0xbe0c, 0xf11d, 0xae02,
+    0xa83e, 0x3c45, 0x2a3a, 0x284a, 0xe419, 0x0ac7, 0x3c4a, 0x183c,
+    0xf072, 0xa202, 0xe42e, 0x283c, 0x3c4a, 0xa202, 0xe42e, 0xe16a,
+    0x28c1, 0xf094, 0xe41e, 0x178d, 0x28c1, 0xe41e, 0x1794, 0x28c1,
+    0xe41e, 0x179b, 0xa200, 0xe42e, 0x28a5, 0xe016, 0xe42a, 0x2835,
+    0xe42a, 0x2838, 0x1833, 0xe42a, 0x28a3, 0xf048, 0x2836, 0xe016,
+    0xe42e, 0x2836, 0xe42a, 0x2837, 0x1831, 0xe016, 0xe42e, 0xe049,
+    0xc70f, 0x7e50, 0xaf21, 0xae02, 0xe046, 0xe42e, 0xe41e, 0x0bb2,
+    0xd1f3, 0x0000, 0xe162, 0x0270, 0x2912, 0xcfe4, 0xe42e, 0xe161,
+    0x0270, 0x2830, 0xa102, 0xf03a, 0xe161, 0x0290, 0x2840, 0x3c04,
+    0xe162, 0x01b0, 0xe41e, 0x0b4f, 0xe42a, 0xd1f3, 0x0000, 0xe162,
+    0x01b0, 0x8840, 0x0022, 0xe184, 0x0aee, 0x2912, 0xcfe4, 0x2830,
+    0xa104, 0xe428, 0x2841, 0x3c04, 0xe161, 0x02b0, 0xe162, 0x01d0,
+    0xe41e, 0x0b4f, 0xe42a, 0xd1f3, 0x0020, 0xe162, 0x01d0, 0x8841,
+    0x0022, 0xe184, 0x0b04, 0x2912, 0xcfe4, 0xe161, 0x05e0, 0xa23e,
+    0xc71f, 0x3d11, 0x2840, 0xe000, 0x01b0, 0xe094, 0x2a40, 0x8840,
+    0x0022, 0xe184, 0x0b18, 0x290a, 0xe000, 0x05e0, 0xe092, 0x3f01,
+    0xa103, 0xd1f9, 0x0000, 0xe162, 0x05e0, 0xd022, 0x001f, 0xe184,
+    0x0b22, 0x2912, 0xcff0, 0xe162, 0x01d0, 0x2902, 0x3cc2, 0xe41e,
+    0x0c03, 0xe41e, 0x0c2f, 0x34c5, 0x3cc6, 0x2902, 0xae02, 0xe000,
+    0x0160, 0xe09e, 0x2117, 0x4d17, 0x2317, 0x4f17, 0x10c7, 0x1cc8,
+    0x12c7, 0x1ec8, 0xe010, 0xe011, 0xe046, 0xb624, 0xb608, 0x3ccf,
+    0x2902, 0xe41e, 0x0bfc, 0xa102, 0xb628, 0x3ccd, 0x2902, 0xaf02,
+    0xe000, 0x01a0, 0xe09e, 0x2907, 0x3cce, 0xa202, 0xe42e, 0xba40,
+    0xf098, 0x8804, 0x0022, 0xe184, 0x0b56, 0x2911, 0x3d12, 0xa202,
+    0xe42e, 0x28c0, 0xe42a, 0xe082, 0x3c08, 0x2c12, 0x5832, 0x3400,
+    0x3c01, 0x2c31, 0x5832, 0x0832, 0x3402, 0x3c03, 0x2804, 0x3c05,
+    0xe163, 0x05e0, 0xa200, 0xc71f, 0x3d13, 0xbc06, 0xe40d, 0x0baf,
+    0xf06a, 0xa102, 0xf13a, 0xa102, 0xf1ba, 0xf28e, 0xe41e, 0x0819,
+    0xe40d, 0x0baf, 0xa002, 0x1002, 0x1c03, 0xe012, 0xf032, 0x0000,
+    0x0c01, 0x3402, 0x3c03, 0xa203, 0xf0de, 0xe41e, 0x0819, 0xe40d,
+    0x0baf, 0xa002, 0x0002, 0x0c03, 0x1000, 0x1c01, 0xf70e, 0xbc40,
+    0xa2ff, 0xe41e, 0x0bcc, 0xf1c4, 0x3d12, 0xe41e, 0x0be7, 0x2805,
+    0xa102, 0x3c05, 0xa004, 0xe42a, 0xf51e, 0x2808, 0xa102, 0xe092,
+    0xe163, 0x05e0, 0x2805, 0xf0a4, 0x2913, 0x8111, 0xf7e8, 0x2901,
+    0x3d12, 0x2805, 0xa102, 0x3c05, 0xf76e, 0xa202, 0xe42e, 0xe16a,
+    0xa200, 0xe42e, 0x28c1, 0xe424, 0xae04, 0x08c1, 0x08c1, 0xe000,
+    0x0620, 0xe09e, 0xe166, 0x020d, 0xe165, 0x0214, 0xd022, 0x0002,
+    0xe184, 0x0bc5, 0x2117, 0x4d17, 0x9f16, 0x9f15, 0x28c1, 0xe41e,
+    0x0c2f, 0x34c3, 0x3cc4, 0xe42e, 0x3c06, 0x3e07, 0xe163, 0x0230,
+    0x2816, 0xa102, 0xe424, 0xae02, 0xa002, 0xcc44, 0xe184, 0x0be4,
+    0x2d13, 0x2b0b, 0x1c06, 0x1a07, 0xf078, 0xf069, 0xe086, 0xe002,
+    0x0230, 0xaf02, 0xe42e, 0x8113, 0x8113, 0xa2fe, 0xe42e, 0x3c09,
+    0x2808, 0xe092, 0x28c0, 0xa102, 0xcc44, 0xe184, 0x0bf2, 0x2901,
+    0x1809, 0xf03a, 0x8111, 0xe42e, 0xe082, 0x1808, 0xe000, 0x05e0,
+    0xe096, 0xa202, 0x3d03, 0xe42e, 0xaf02, 0xae04, 0xe000, 0x0101,
+    0xe09e, 0x2907, 0xe42e, 0xaf02, 0xae04, 0xe000, 0x0103, 0xe09e,
+    0x2907, 0xe42e, 0x3c0a, 0xca28, 0xf7f8, 0xe0c0, 0x0042, 0xe000,
+    0x0180, 0x080a, 0xce20, 0xd111, 0x05e0, 0xd112, 0x0020, 0xd113,
+    0x0003, 0xca28, 0xf7f8, 0xe0c0, 0x0041, 0x22f0, 0x4ef1, 0xe042,
+    0xe005, 0x055a, 0xae0f, 0x0a0a, 0xe042, 0xce20, 0xd111, 0x05e0,
+    0xd112, 0x0020, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0x3c0a,
+    0xaf02, 0xae06, 0xe0c1, 0x0041, 0xe042, 0x22f0, 0x4ef1, 0xe042,
+    0xe005, 0x055a, 0xae0f, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111,
+    0x05e0, 0xd112, 0x0004, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe004,
+    0x05e0, 0xe09e, 0x2117, 0x4d17, 0x2a0a, 0xa803, 0xe42b, 0x2117,
+    0x4d17, 0xe42e, 0xba4e, 0x3c4d, 0xa184, 0xe404, 0x0d5b, 0xa170,
+    0xe400, 0x0d5b, 0xba46, 0x3c5d, 0xba46, 0xe408, 0x0d5b, 0xba4e,
+    0x3c1c, 0xa112, 0xe404, 0x0d5b, 0xa154, 0xe400, 0x0d5b, 0xbc3e,
+    0x3c10, 0xa202, 0x3c1f, 0x284d, 0xa1c8, 0xf2f8, 0xbc06, 0x3c1f,
+    0xbc08, 0xe408, 0x0d5b, 0xbc08, 0xe408, 0x0d5b, 0xba40, 0xba40,
+    0x3cb0, 0xf23a, 0xa201, 0x3eb2, 0x3eb4, 0xe160, 0x0000, 0xba40,
+    0xf11a, 0x2ab2, 0xae03, 0xe056, 0x3cb2, 0xe080, 0xe41e, 0x0eb0,
+    0x2ab4, 0xae03, 0xe056, 0x3cb4, 0xe080, 0xa201, 0xe41e, 0x0ee3,
+    0xf07e, 0x2ab2, 0xae03, 0x3eb2, 0x2ab4, 0xae03, 0x3eb4, 0xe080,
+    0xa002, 0xe090, 0xa110, 0xf648, 0xbc18, 0xe40d, 0x0d5b, 0xa008,
+    0x3c11, 0xa202, 0x5811, 0x3c12, 0xbc04, 0x3c13, 0xe40d, 0x0d5b,
+    0xa102, 0xf034, 0xf06a, 0xf21e, 0xbc18, 0xa008, 0x3c14, 0xf1de,
+    0xba40, 0x3c15, 0xe41e, 0x0833, 0x34e7, 0x3ce8, 0xe41e, 0x0833,
+    0x34e9, 0x3cea, 0xbdfe, 0xe40d, 0x0d5b, 0x3ceb, 0xf0ea, 0xa102,
+    0xcc44, 0xe162, 0x0250, 0xe184, 0x0cc8, 0xe41e, 0x0833, 0x3512,
+    0x3d12, 0xe41e, 0x0e2a, 0xf01e, 0xe40d, 0x0d5b, 0xbc20, 0xe40d,
+    0x0d5b, 0x3c16, 0xba40, 0x3c17, 0x2250, 0x4e51, 0xe0c4, 0x007f,
+    0xe40d, 0x0d5b, 0xa002, 0x3c50, 0xe0c4, 0x007f, 0xe40d, 0x0d5b,
+    0xa002, 0x3c51, 0x8450, 0x8251, 0xe018, 0x3c1b, 0x2c57, 0xf1ba,
+    0x2050, 0x4c51, 0xe046, 0xf20a, 0x2c57, 0xaf10, 0xe008, 0x00ff,
+    0x1850, 0xf064, 0x2c57, 0xe008, 0x00ff, 0x1851, 0xf152, 0x2050,
+    0x4c51, 0xae08, 0xe0c2, 0x006f, 0xe0c2, 0x004f, 0xa2fe, 0x3c57,
+    0xe40e, 0x0d5b, 0x2850, 0xe008, 0x00ff, 0xae10, 0x2a51, 0xe009,
+    0x00ff, 0xe056, 0x3c57, 0xa200, 0x3c19, 0xba40, 0x3c18, 0xf098,
+    0xba40, 0x3c19, 0x2851, 0xae02, 0x3c51, 0x281b, 0xae02, 0x3c1b,
+    0xe0c0, 0x0059, 0xa102, 0xf038, 0xe41e, 0x0de7, 0xba40, 0x3c1a,
+    0x4c18, 0xf3aa, 0xba40, 0x3c58, 0x3c59, 0x3c5a, 0x3c5b, 0xf14a,
+    0xe41e, 0x0819, 0x3c58, 0xe41e, 0x0819, 0x3c59, 0xe41e, 0x0819,
+    0x2a18, 0xf029, 0xae02, 0x3c5a, 0xe41e, 0x0819, 0x2a18, 0xf029,
+    0xae02, 0x3c5b, 0xf21d, 0xe0c0, 0x0059, 0xa102, 0xf0e8, 0x2a1f,
+    0x2058, 0x4c59, 0xf02b, 0xae02, 0xe0c2, 0x0076, 0x205a, 0x4c5b,
+    0xf02b, 0xae02, 0xe0c2, 0x0077, 0xa200, 0x3c82, 0x3c83, 0x281d,
+    0x3cde, 0x3cdf, 0xba40, 0xe016, 0xe41a, 0x0e3f, 0xf05a, 0xe41e,
+    0x0862, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0xe41e, 0x0819,
+    0x3c20, 0xbc3e, 0xe40d, 0x0de4, 0x1810, 0xf0ea, 0x0810, 0x3c10,
+    0xe41e, 0x1343, 0x3c66, 0xa202, 0xe41e, 0x06e8, 0xa203, 0x3e94,
+    0x2866, 0xe40a, 0x0de4, 0xba40, 0x3c21, 0xba40, 0x3c22, 0xbc0e,
+    0xe40d, 0x0de4, 0x3c23, 0xe408, 0x0de4, 0xbc3e, 0xe40d, 0x0de4,
+    0x3c24, 0xbc3e, 0x3c25, 0xe40d, 0x0de4, 0xba40, 0x3c26, 0xba42,
+    0x3c27, 0xbe34, 0xe40d, 0x0de4, 0xa034, 0x3c28, 0xe404, 0x0de4,
+    0xa168, 0xe402, 0x0de4, 0xbe34, 0xe40d, 0x0de4, 0xa034, 0xe404,
+    0x0de4, 0xa168, 0xe402, 0x0de4, 0xbe18, 0xe40d, 0x0de4, 0x3c29,
+    0x3c2d, 0xba40, 0x3c2a, 0xba40, 0x3c2b, 0xba40, 0x3c2c, 0xa200,
+    0x3c2e, 0x3cb1, 0x2820, 0x3c02, 0xe41e, 0x1409, 0xe41e, 0x05f7,
+    0xf30a, 0xba40, 0x3c2e, 0xba40, 0x3cb1, 0xf28a, 0xa201, 0x3eb3,
+    0x3eb5, 0xe160, 0x0000, 0xe080, 0xa10c, 0x182e, 0x182e, 0xf132,
+    0xba40, 0xf11a, 0x2ab3, 0xae03, 0xe056, 0x3cb3, 0xe080, 0xe41e,
+    0x0eb0, 0x2ab5, 0xae03, 0xe056, 0x3cb5, 0xe080, 0xa203, 0xe41e,
+    0x0ee3, 0xf07e, 0x2ab3, 0xae03, 0x3eb3, 0x2ab5, 0xae03, 0x3eb5,
+    0xe080, 0xa002, 0xe090, 0xa110, 0xf5f8, 0xbe18, 0xf06d, 0x3c2d,
+    0xe41e, 0x0862, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0x2a1c,
+    0xa115, 0xe004, 0x0129, 0xf2d7, 0xa103, 0xe004, 0x02a3, 0xf297,
+    0xa113, 0xe004, 0x06f6, 0xf257, 0xa103, 0xe004, 0x0dec, 0xf217,
+    0xa113, 0xe004, 0x17bb, 0xf1d7, 0xa103, 0xe004, 0x34bc, 0xf197,
+    0xa103, 0xe004, 0x3c00, 0xf157, 0xa113, 0xe004, 0x6000, 0xf117,
+    0xa103, 0xe004, 0x6600, 0xf0d7, 0xa111, 0xe004, 0x1437, 0xae08,
+    0xf087, 0xa103, 0xe004, 0x21c0, 0xae08, 0xf037, 0xe004, 0x17bb,
+    0xae12, 0x841b, 0xe182, 0x0180, 0xe019, 0xc407, 0xd022, 0x000f,
+    0xe184, 0x0e24, 0xe046, 0xf034, 0x8117, 0xe190, 0xe08e, 0xa520,
+    0x3c1d, 0xe42e, 0xe0c0, 0x0041, 0x22f0, 0x4ef1, 0xe042, 0xe005,
+    0x029e, 0xae11, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0250,
+    0xd112, 0x0200, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0xba40,
+    0xf15a, 0xba4e, 0xe0c1, 0x0059, 0xa103, 0xf039, 0xe0c2, 0x006c,
+    0xe002, 0x00ff, 0xf0b8, 0xba5e, 0xba5f, 0xae20, 0xe056, 0xe0c1,
+    0x0059, 0xa103, 0xf039, 0xe0c2, 0x006c, 0xba40, 0xf02a, 0xba40,
+    0xba40, 0xf08a, 0xba44, 0xba40, 0xba40, 0xf04a, 0xba4e, 0xba4e,
+    0xba4e, 0xba40, 0xf03a, 0xbc0a, 0xbc0a, 0xba40, 0xf08a, 0xba7e,
+    0xe0c2, 0x0079, 0xba7e, 0xe0c2, 0x007a, 0xba40, 0xba40, 0x3c82,
+    0xe016, 0xe161, 0x05bc, 0xe41a, 0x0e95, 0xf1da, 0xba40, 0x3c83,
+    0xe016, 0xe161, 0x05c1, 0xe41a, 0x0e95, 0xf15a, 0x2882, 0x4c83,
+    0xf02a, 0xba40, 0xba40, 0x3c4f, 0xba40, 0xf0aa, 0xba40, 0xbc20,
+    0xbc20, 0xbc20, 0xbc20, 0xbc20, 0x3cde, 0xbc20, 0x3cdf, 0xe16a,
+    0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0xe41e, 0x0819, 0xcc44,
+    0xa002, 0x3d11, 0xba46, 0xba46, 0xe184, 0x0ea2, 0xe41e, 0x0819,
+    0xe41e, 0x0819, 0xba40, 0xba48, 0xa002, 0x3d11, 0xba48, 0xa002,
+    0x3d11, 0xba48, 0xa002, 0x3d11, 0xba48, 0x3d11, 0xa202, 0xe42e,
+    0xd022, 0x000f, 0xa10c, 0xf034, 0xd022, 0x003f, 0xe161, 0x05e0,
+    0xa210, 0x3c06, 0x3c07, 0xa200, 0x3c08, 0x3c09, 0xe09c, 0xe09e,
+    0xe184, 0x0ee0, 0x2807, 0xf10a, 0xe41e, 0x0833, 0xe42d, 0x0806,
+    0xe000, 0x0100, 0xe008, 0x00ff, 0x3c07, 0x4c09, 0xe01a, 0xe016,
+    0xe09e, 0xa202, 0x3c09, 0x2807, 0xf028, 0x2806, 0x3c06, 0xe08d,
+    0xa003, 0xe09d, 0xa803, 0xf059, 0xe085, 0xae11, 0xe056, 0x3d11,
+    0xe094, 0xe08e, 0xe42e, 0x3e08, 0x3c06, 0xa211, 0x3e07, 0xa10c,
+    0xf064, 0xb690, 0xa00c, 0x3c06, 0xa240, 0x3c07, 0x2806, 0x2a08,
+    0xf02b, 0xa01c, 0xae08, 0x3c06, 0xe0c0, 0x0041, 0x22f0, 0x4ef1,
+    0xe042, 0xe005, 0x02ab, 0xae11, 0xe042, 0x0806, 0xca29, 0xf7f9,
+    0xce20, 0xd111, 0x05e0, 0x2807, 0xce24, 0xd113, 0x0002, 0xca28,
+    0xf7f8, 0xe42e, 0x2875, 0xa802, 0xe42a, 0xe0c0, 0x0045, 0xaf04,
+    0xa802, 0xe42e, 0xa200, 0xba4f, 0xe042, 0xe003, 0x00ff, 0xf7cb,
+    0x3c00, 0xa200, 0xba4f, 0xe042, 0xe003, 0x00ff, 0xf7cb, 0x3c01,
+    0xe41e, 0x0f29, 0xe42a, 0xe41e, 0x05e9, 0xf6d8, 0xe41e, 0x0862,
+    0xe42e, 0x2800, 0xf10a, 0xa102, 0xf11a, 0xa104, 0xf12a, 0xa102,
+    0xf13a, 0xa102, 0xf14a, 0x2a01, 0xf04b, 0xba4e, 0xa103, 0xf7e9,
+    0xa202, 0xe42e, 0xe41e, 0x0f51, 0xf0de, 0xe41e, 0x0f78, 0xf0ae,
+    0xe41e, 0x0fd3, 0xf07e, 0xe41e, 0x0fe3, 0xf04e, 0xe41e, 0x0ff1,
+    0xf01e, 0xe42a, 0xc868, 0xa80e, 0xe016, 0xe428, 0xe41e, 0x0862,
+    0xe42e, 0xbc3e, 0x1810, 0xf0da, 0x0810, 0x3c10, 0xe41e, 0x1343,
+    0x3c66, 0xa200, 0xe41e, 0x06e8, 0xa201, 0x3e94, 0x2866, 0xe42a,
+    0x2882, 0xe161, 0x05bc, 0xe418, 0x0f6c, 0x2883, 0xe161, 0x05c1,
+    0xe418, 0x0f6c, 0xa202, 0xe42e, 0x2911, 0xa102, 0xcc44, 0xe184,
+    0x0f76, 0x2901, 0xe41e, 0x0856, 0x2901, 0xe41e, 0x0856, 0xe42e,
+    0xe166, 0x004c, 0x2882, 0xe161, 0x05be, 0xf038, 0xe161, 0x05c3,
+    0x4c83, 0xf09a, 0x2911, 0xe41e, 0x0856, 0x2911, 0xe41e, 0x0856,
+    0x2911, 0xf02e, 0xa230, 0x3c02, 0x284f, 0xe016, 0xe428, 0xba46,
+    0xe0c2, 0x007b, 0xa112, 0xb604, 0xe42a, 0xa012, 0xe049, 0xa200,
+    0xa107, 0xb426, 0xa105, 0xb426, 0xa105, 0xb5f6, 0xcc44, 0xe184,
+    0x0fd0, 0xa201, 0xba40, 0xf038, 0x9f96, 0xf2be, 0xba42, 0xba40,
+    0xba48, 0xba40, 0x3c03, 0xba40, 0xba40, 0xae32, 0xe055, 0xba4e,
+    0xe055, 0x2803, 0xf0ba, 0xba4a, 0xae10, 0xe055, 0xba4a, 0xae1c,
+    0xe055, 0xba48, 0xae28, 0xe055, 0xf10e, 0xba40, 0xf0ea, 0xba4a,
+    0xae10, 0xe055, 0xba40, 0xf09a, 0xba4a, 0xae1c, 0xe055, 0xba40,
+    0xf04a, 0xba48, 0xae28, 0xe055, 0x9f96, 0x2802, 0xe41e, 0x0856,
+    0xe190, 0xa202, 0xe42e, 0x2801, 0xf0da, 0xa102, 0xcc44, 0xe004,
+    0x00ff, 0xe184, 0x0fdc, 0xba4f, 0xe052, 0xe002, 0x00ff, 0xe016,
+    0xe42a, 0xa202, 0xe42e, 0xa202, 0xba4f, 0xe003, 0x00ff, 0xf039,
+    0xba4f, 0xa204, 0xba4f, 0xa002, 0x2a01, 0xe045, 0xf7c1, 0xa202,
+    0xe42e, 0x2801, 0xa420, 0xa102, 0xcc44, 0xe184, 0x0ff8, 0xba4e,
+    0xe190, 0xa202, 0xe42e, 0x2c31, 0x3cd0, 0xa202, 0x3cd1, 0xa200,
+    0x3cd2, 0x3cd3, 0x28a3, 0xe016, 0xe428, 0x28a5, 0xf0ca, 0xe41e,
+    0x1098, 0xba40, 0xba40, 0xb7f0, 0xb634, 0x3cd1, 0xa200, 0x3cd0,
+    0xa202, 0xe42e, 0xba40, 0xf048, 0xa202, 0x3cd2, 0xe42e, 0x2816,
+    0xe42a, 0xae02, 0x3c09, 0x2812, 0x5832, 0x3400, 0x3c01, 0x2c31,
+    0x5832, 0x0832, 0x3402, 0x3c03, 0xbc0c, 0xe40d, 0x1095, 0xe40a,
+    0x1093, 0xa102, 0xf0ca, 0xa102, 0xf1da, 0xa102, 0xf24a, 0xa102,
+    0xf3aa, 0xa102, 0xe40a, 0x1073, 0xe40e, 0x107b, 0xe41e, 0x0819,
+    0xe40d, 0x1095, 0xa002, 0x1002, 0x1c03, 0xe012, 0xf032, 0x0000,
+    0x0c01, 0xa203, 0xe41e, 0x109f, 0xe408, 0x1048, 0xa203, 0x3ed2,
+    0xf5ce, 0xbc40, 0xe40d, 0x1095, 0xa2ff, 0xe41e, 0x109f, 0xe40a,
+    0x1095, 0xf53e, 0xe41e, 0x0819, 0xe40d, 0x1095, 0xa002, 0x1002,
+    0x1c03, 0xe012, 0xf032, 0x0000, 0x0c01, 0x3c06, 0xa802, 0x4432,
+    0xbc21, 0xf34d, 0x5a32, 0xe041, 0x3e07, 0xe41e, 0x10b7, 0xf2ea,
+    0xe40e, 0x1024, 0xbc20, 0xf2ad, 0xa102, 0x5832, 0x0832, 0xe41e,
+    0x10d2, 0xe40e, 0x1024, 0xe41e, 0x1098, 0xa202, 0x3cd3, 0xa200,
+    0x3cd0, 0xe40e, 0x1024, 0xbc20, 0xf19d, 0x3cd0, 0x28d0, 0x5832,
+    0x0832, 0xa2ff, 0xe41e, 0x109f, 0xf7a8, 0x2832, 0xf09a, 0x2834,
+    0xf078, 0x28d0, 0xae02, 0xa2ff, 0xe41e, 0x109f, 0xf7b8, 0xa2fe,
+    0x3cd1, 0xe40e, 0x1024, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e,
+    0xc410, 0xe161, 0x01f1, 0xa200, 0xc71f, 0x3d31, 0xe42e, 0x3c04,
+    0x3e05, 0xe161, 0x01f0, 0x8809, 0x0022, 0xe184, 0x10b2, 0x2d11,
+    0x2b09, 0x1c04, 0x1a05, 0xf068, 0xf059, 0x8111, 0xa200, 0x3d09,
+    0xf05e, 0x8111, 0x8111, 0xa200, 0xe42e, 0xa202, 0xe42e, 0x2807,
+    0xa2ff, 0xe41e, 0x109f, 0xf7c8, 0xe161, 0x01f0, 0x8809, 0x0022,
+    0xe184, 0x10cd, 0x2d11, 0x2b09, 0x1c06, 0xf078, 0xf067, 0x2807,
+    0x3d11, 0xa2fe, 0x3d09, 0xf05e, 0x8111, 0x8111, 0xa200, 0xe42e,
+    0xa202, 0xe42e, 0x3c08, 0xe161, 0x01f0, 0x8809, 0x0022, 0xe184,
+    0x10e2, 0x2d11, 0x2b09, 0x1808, 0xf056, 0xf043, 0x8111, 0xa200,
+    0x3d09, 0x8111, 0x8111, 0xe42e, 0x2816, 0x184e, 0xf112, 0x884e,
+    0x0022, 0xe161, 0x0102, 0xe184, 0x10f6, 0x2911, 0xf06a, 0x2909,
+    0xe412, 0x178d, 0xa200, 0x3d11, 0xe082, 0xa006, 0xe092, 0x2816,
+    0xb62c, 0x3c4e, 0x2813, 0xa104, 0xe428, 0xe41e, 0x1296, 0xe42e,
+    0x2813, 0xa102, 0xf034, 0xf0fa, 0xf2be, 0x7414, 0x3ce3, 0x2832,
+    0xe016, 0x4422, 0xe418, 0x0833, 0xe42d, 0x34e4, 0x3ce5, 0xe41e,
+    0x11d7, 0xf20e, 0xa200, 0x34e3, 0x3ce4, 0x34e5, 0x3ce6, 0x2815,
+    0xf0f8, 0xe41e, 0x0833, 0xe42d, 0x34e3, 0x3ce4, 0x2822, 0xf08a,
+    0x2832, 0xf068, 0xe41e, 0x0833, 0xe42d, 0x34e5, 0x3ce6, 0xe41e,
+    0x1213, 0xf08e, 0x34e3, 0x3ce4, 0x34e5, 0x3ce6, 0xf03e, 0xe41e,
+    0x1256, 0x2832, 0x2a33, 0xf0b9, 0xf078, 0x20c9, 0x4cca, 0x22cb,
+    0x4ecc, 0xe066, 0xf06e, 0x20c9, 0x4cca, 0xf03e, 0x20cb, 0x4ccc,
+    0x34c7, 0x3cc8, 0xe42e, 0x281e, 0xf04a, 0x2813, 0xa104, 0xf088,
+    0x28c1, 0x3c01, 0xe41e, 0x1794, 0xe41e, 0x12d3, 0xe42e, 0x28a5,
+    0x4cd3, 0xe418, 0x1296, 0x28d8, 0xae02, 0xe000, 0x0578, 0xe092,
+    0x20c7, 0x4cc8, 0x3511, 0x3d11, 0x28d8, 0xe000, 0x059a, 0xe092,
+    0x28c1, 0x3d11, 0x28d8, 0xa002, 0x3cd8, 0xa200, 0x3c0c, 0xe41e,
+    0x17b1, 0xf098, 0xe41e, 0x129b, 0x280c, 0xa180, 0xf052, 0xa082,
+    0x3c0c, 0xf76e, 0xe42e, 0xe41e, 0x1787, 0xe42e, 0x28c1, 0xe424,
+    0xe000, 0x06e0, 0xe092, 0x20aa, 0x4cab, 0x8450, 0x8251, 0xe019,
+    0xe41e, 0x1188, 0xe049, 0xa141, 0xf027, 0xa240, 0x3d01, 0xe42e,
+    0x3e0a, 0xa201, 0xf032, 0xe012, 0xa203, 0x3e0e, 0x3c0b, 0xaf20,
+    0xc70f, 0x7c0a, 0x3c0c, 0xaf20, 0xae20, 0x4c0b, 0xc70f, 0x7c0a,
+    0x3c0d, 0x200c, 0x4c0d, 0x2a0e, 0xe42b, 0xe012, 0xe42e, 0xe41e,
+    0x0f0a, 0xf04a, 0xe41e, 0x1296, 0xf0be, 0x287f, 0xf04a, 0xe41e,
+    0x1296, 0xf06e, 0x28dc, 0xf04a, 0xa102, 0x3cdc, 0xf1ee, 0x28db,
+    0xf1ca, 0x28da, 0xe000, 0x05ab, 0xe092, 0x28da, 0xa002, 0x3cda,
+    0xa122, 0xf028, 0x3cda, 0x28db, 0xa102, 0x3cdb, 0x287f, 0xf0ba,
+    0x28db, 0xf05a, 0x2901, 0xe41e, 0x179b, 0xf6ae, 0x281e, 0xf03a,
+    0x28de, 0x3cdc, 0x2901, 0xe42e, 0xe41e, 0x0f0a, 0xf078, 0x286c,
+    0xf058, 0x287d, 0xf03a, 0xa2fc, 0xe42e, 0xa2fe, 0xe42e, 0xa202,
+    0x5814, 0xaf02, 0x3c06, 0x28a5, 0x2ad7, 0xf078, 0xf099, 0x20e6,
+    0x4ce7, 0x22e8, 0x4ee9, 0xf07e, 0xa200, 0xa201, 0xf04e, 0xa200,
+    0x22ea, 0x4eeb, 0x3400, 0x3c01, 0x3602, 0x3e03, 0x2ee3, 0x1202,
+    0x1e03, 0xf071, 0xe013, 0x1e06, 0xf085, 0x0c06, 0x0c06, 0xf05e,
+    0x1e06, 0xf037, 0x1c06, 0x1c06, 0x3404, 0x3c05, 0x0ce3, 0x34c9,
+    0x3cca, 0x00e4, 0x0ce5, 0x34cb, 0x3ccc, 0x28a3, 0xf0ca, 0x20c9,
+    0x4cca, 0x34ea, 0x3ceb, 0x2004, 0x4c05, 0x34e6, 0x3ce7, 0x2ce3,
+    0x34e8, 0x3ce9, 0xe42e, 0xe41e, 0x1267, 0x28eb, 0xf30a, 0x2000,
+    0x4c01, 0x0c31, 0xf2c6, 0x2aa3, 0xe017, 0xe046, 0xa102, 0xf274,
+    0xe188, 0x000f, 0x7ceb, 0x3402, 0x3c03, 0xe41e, 0x1281, 0x28eb,
+    0xa102, 0xcc44, 0xe161, 0x0250, 0xa200, 0xe184, 0x1230, 0x0111,
+    0x0d11, 0xae02, 0x3404, 0xe008, 0xffff, 0xaf02, 0x3c05, 0x8403,
+    0x8204, 0xe018, 0xae1e, 0x8205, 0xe01c, 0xe161, 0x0250, 0x8802,
+    0x0022, 0xe184, 0x1244, 0x0111, 0x0d11, 0xf02e, 0xa200, 0x2aa3,
+    0xf039, 0x00e7, 0x0ce8, 0x00e3, 0x0ce4, 0x34c9, 0x3cca, 0x00e9,
+    0x0cea, 0x00e5, 0x0ce6, 0x34cb, 0x3ccc, 0xe42e, 0xe41e, 0x1267,
+    0x28a5, 0xe016, 0xf08a, 0x2000, 0x4c01, 0x0c31, 0xae02, 0x2aa3,
+    0xe017, 0xe046, 0x34c9, 0x3cca, 0x34cb, 0x3ccc, 0xe42e, 0x28d7,
+    0xf05a, 0xa200, 0x34e1, 0x3ce2, 0x3ce0, 0x28a5, 0xe016, 0xf09a,
+    0x20e1, 0x4ce2, 0x2ee0, 0x1e31, 0xf047, 0xa203, 0x5a11, 0xe042,
+    0x3400, 0x3c01, 0x2831, 0x3ce0, 0x2000, 0x4c01, 0x34e1, 0x3ce2,
+    0xe42e, 0xe0c0, 0x0041, 0x22f0, 0x4ef1, 0xe042, 0xe005, 0x029e,
+    0xae11, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0250, 0xd112,
+    0x0200, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e, 0x28d8, 0xe426,
+    0xe41e, 0x129b, 0xf7ce, 0x28d8, 0xe426, 0xe161, 0x0578, 0xe162,
+    0x0578, 0x2111, 0x4d11, 0xa201, 0x3e00, 0xa203, 0x28d8, 0xa104,
+    0xf0e4, 0xcc44, 0xe184, 0x12b5, 0x2112, 0x4d0a, 0x1111, 0x1d11,
+    0xf054, 0xe082, 0xa104, 0xe094, 0x3e00, 0xa003, 0xe084, 0xa004,
+    0xe092, 0x2800, 0xe000, 0x059a, 0xe098, 0xa002, 0xe096, 0x2904,
+    0x3c01, 0xe41e, 0x1794, 0x28d8, 0x1800, 0xa104, 0xf0a4, 0xcc44,
+    0xe184, 0x12cf, 0x2911, 0x3d12, 0x2911, 0x3d12, 0x2913, 0x3d14,
+    0x28d8, 0xa102, 0x3cd8, 0x28d9, 0xe000, 0x05ab, 0xe092, 0x2801,
+    0x3d01, 0x28d9, 0xa002, 0x3cd9, 0xa122, 0xf028, 0x3cd9, 0x28db,
+    0xa002, 0x3cdb, 0xe42e, 0xa200, 0x3c68, 0x28d4, 0xa102, 0xcc44,
+    0xe184, 0x12ff, 0xe0c0, 0x0054, 0x5c68, 0xa802, 0xf0b8, 0x2868,
+    0xe049, 0xe001, 0x0518, 0xe09f, 0x2b07, 0xa809, 0xe419, 0x179b,
+    0xf05e, 0x2868, 0xa209, 0xe41e, 0x17aa, 0x2a68, 0xa003, 0x3e68,
+    0xe42e, 0xe004, 0x0518, 0xe09e, 0xe004, 0x0054, 0xe09c, 0x28d4,
+    0xa102, 0xcc44, 0xa200, 0x3c68, 0xe184, 0x1315, 0x2b17, 0xaf05,
+    0xa803, 0x5a68, 0xe056, 0x2a68, 0xa003, 0x3e68, 0x9f06, 0xe42e,
+    0xe161, 0x05e0, 0xa200, 0x3d11, 0x3c02, 0xd022, 0x011f, 0xe184,
+    0x1325, 0xe41e, 0x1407, 0x2802, 0xa002, 0x3c02, 0xa200, 0x3c94,
+    0x3c90, 0x3c91, 0xe42e, 0xba4e, 0xba40, 0xba40, 0xba40, 0xba40,
+    0xba46, 0xba4e, 0xbc3e, 0xf0dd, 0x3c00, 0x1810, 0xf038, 0xa2fe,
+    0x3c10, 0x2800, 0xe000, 0x0100, 0xe41e, 0x138d, 0xa202, 0xe42e,
+    0xe16a, 0xa200, 0xe42e, 0xa204, 0x3c94, 0x2810, 0xe000, 0x0100,
+    0xe41e, 0x13d9, 0xe42a, 0xe41e, 0x0c52, 0xf05a, 0xe41e, 0x10e4,
+    0xa202, 0xe42e, 0xa2fe, 0x3c10, 0xa200, 0xe42e, 0xe41e, 0x0819,
+    0xf0fd, 0x3c01, 0xe002, 0x00ff, 0xf0b0, 0x2801, 0x1820, 0xf038,
+    0xa2fe, 0x3c20, 0x2801, 0xe41e, 0x138d, 0xa202, 0xe42e, 0xe16a,
+    0xa200, 0xe42e, 0xa202, 0x3c94, 0x2820, 0xe41e, 0x13d9, 0xe42a,
+    0xe41e, 0x0d5e, 0x3c66, 0xa200, 0xe41e, 0x06e8, 0xa201, 0x3e94,
+    0x2866, 0xf03a, 0xa202, 0xe42e, 0xa2fe, 0x3c20, 0xa200, 0xe42e,
+    0x2863, 0xa102, 0xf06a, 0x2092, 0x4c93, 0xe41e, 0x1433, 0xe470,
+    0x2080, 0x4c81, 0xe41e, 0x1442, 0xe470, 0x3c02, 0xe41e, 0x1409,
+    0xa200, 0x3c03, 0xe161, 0x05e0, 0x2901, 0xa203, 0x3f11, 0xf10a,
+    0x28a7, 0x1901, 0xf0d0, 0x28a7, 0xe002, 0x0200, 0xf092, 0x8111,
+    0x2111, 0x4d11, 0x3404, 0x3c05, 0xa202, 0x3c03, 0xf08e, 0x2090,
+    0x4c91, 0x3404, 0x3c05, 0x8111, 0x3511, 0x3d11, 0xe41e, 0x1426,
+    0xca29, 0xf7f9, 0xce20, 0xd111, 0x0000, 0x28a7, 0xa00e, 0xaf06,
+    0xae02, 0xce24, 0xd113, 0x0012, 0xca28, 0xf7f8, 0x28a6, 0xf0a8,
+    0xe41e, 0x05cc, 0x2004, 0x4c05, 0xe000, 0x0200, 0x3404, 0x3c05,
+    0xf66e, 0xe161, 0x05e1, 0x28a7, 0x3d01, 0x2a03, 0xf089, 0xa00e,
+    0xaf06, 0xae06, 0x0090, 0x0c91, 0x3490, 0x3c91, 0xe41e, 0x1407,
+    0xe42e, 0x3c02, 0xe41e, 0x1409, 0xe161, 0x05e0, 0x2911, 0xe42a,
+    0x8111, 0x2111, 0x4d11, 0x3404, 0x3c05, 0x2894, 0xa102, 0xf0ba,
+    0xe41e, 0x1426, 0xe41e, 0x1433, 0xa204, 0xe41e, 0x06e8, 0xe004,
+    0x0090, 0xf0ae, 0xe41e, 0x1426, 0xe41e, 0x1442, 0xa202, 0xe41e,
+    0x06e8, 0xe004, 0x0080, 0xcc66, 0xcc6a, 0xcc6e, 0xa01e, 0xcc6c,
+    0xa200, 0xcc60, 0xcc68, 0xcc70, 0xe128, 0xa202, 0xe42e, 0xa204,
+    0xf02e, 0xa206, 0x3c0a, 0xe41e, 0x1419, 0xca29, 0xf7f9, 0xce20,
+    0xd111, 0x05e0, 0xd112, 0x0004, 0x880a, 0x0113, 0xca28, 0xf7f8,
+    0xe42e, 0xe0c0, 0x0041, 0x22f0, 0x4ef1, 0xe042, 0xe005, 0x02a2,
+    0xae11, 0xe042, 0x2a02, 0xae07, 0xe042, 0xe42e, 0xe0c0, 0x0041,
+    0x22f0, 0x4ef1, 0xe042, 0xe005, 0x02ae, 0xae11, 0xe042, 0x2204,
+    0x4e05, 0xe042, 0xe42e, 0xca29, 0xf7f9, 0xce20, 0xa080, 0x3492,
+    0x3c93, 0xd111, 0x0090, 0xd112, 0x0010, 0xd113, 0x0013, 0xca28,
+    0xf7f8, 0xe42e, 0xca29, 0xf7f9, 0xce20, 0xa080, 0x3480, 0x3c81,
+    0xd111, 0x0080, 0xd112, 0x0010, 0xd113, 0x0013, 0xca28, 0xf7f8,
+    0xe42e, 0x2816, 0xe42a, 0xa102, 0x3c00, 0x28a3, 0xe01a, 0x4417,
+    0xe418, 0x1580, 0xe41e, 0x1593, 0xe41e, 0x15c7, 0xe41e, 0x15ec,
+    0xe42e, 0x28d3, 0xf11a, 0x20c9, 0x4cca, 0x10c7, 0x1cc8, 0x34c9,
+    0x3cca, 0x20cb, 0x4ccc, 0x10c7, 0x1cc8, 0x34cb, 0x3ccc, 0xa200,
+    0x34c7, 0x3cc8, 0x3c37, 0x2c31, 0x2aa5, 0x4ed3, 0xb612, 0x3cd5,
+    0x2816, 0xe42a, 0xa102, 0x3c00, 0x2831, 0x3c01, 0x2834, 0xe016,
+    0x44d2, 0xe418, 0x1516, 0x28d2, 0xe41a, 0x1544, 0x2834, 0xe408,
+    0x14da, 0xe41e, 0x149a, 0xe42e, 0xaf02, 0xae04, 0xe000, 0x0101,
+    0xe09e, 0x2907, 0xe42e, 0xaf02, 0xae04, 0xe000, 0x0103, 0xe09e,
+    0x2907, 0xe42e, 0xc420, 0xe161, 0x0102, 0x8800, 0x0022, 0xe184,
+    0x14a3, 0x2901, 0xf03a, 0x8131, 0xe42e, 0xe082, 0xe002, 0x0102,
+    0xaf04, 0x3c0a, 0x283b, 0x3d09, 0x28d1, 0x3d09, 0x28d0, 0x3d31,
+    0x8109, 0x28c1, 0x3d11, 0xe082, 0xe000, 0x005c, 0xe094, 0xe002,
+    0x0160, 0xaf02, 0xe000, 0x0140, 0xe092, 0x20c7, 0x4cc8, 0x3511,
+    0x3d11, 0x2a3b, 0xa105, 0x2112, 0x4d0a, 0xf03b, 0x20c9, 0x4cca,
+    0x3512, 0x3d12, 0x2112, 0x4d0a, 0xf035, 0x20cb, 0x4ccc, 0x3512,
+    0x3d12, 0x280a, 0xe000, 0x01a0, 0xe092, 0xa206, 0x183b, 0xe01a,
+    0x3d01, 0xe42e, 0xe161, 0x0100, 0x8800, 0x0022, 0xe184, 0x14e7,
+    0x2d11, 0x2b11, 0x1cd0, 0x1ad1, 0xf028, 0xf04b, 0x8111, 0x8111,
+    0xe42e, 0xa206, 0x3d01, 0xe082, 0xe000, 0x005e, 0xe094, 0xe002,
+    0x0160, 0xaf02, 0xe000, 0x0140, 0xe092, 0xe002, 0x0140, 0xaf02,
+    0x3c0a, 0x20c7, 0x4cc8, 0x2311, 0x4f09, 0xe066, 0x3511, 0x3d11,
+    0xf41e, 0xc420, 0xe161, 0x0102, 0x8800, 0x0022, 0xe184, 0x150a,
+    0x2901, 0xf03a, 0x8131, 0xe42e, 0xa206, 0x3d09, 0xa202, 0x3d09,
+    0x2801, 0x3d31, 0x8109, 0xa2fe, 0x3d11, 0xe42e, 0xa200, 0xc420,
+    0xe161, 0x0102, 0x8800, 0x0022, 0xe184, 0x1520, 0x2b31, 0xe01b,
+    0xe042, 0x1816, 0xe424, 0xa203, 0xae21, 0xe161, 0x0102, 0x8800,
+    0x0022, 0xe184, 0x153d, 0x2909, 0xf10a, 0x2909, 0xf0d6, 0x2901,
+    0x1c01, 0xf026, 0x1c12, 0x0c01, 0xe046, 0xf062, 0xe042, 0xe049,
+    0xe082, 0xa004, 0xe094, 0x8111, 0x8111, 0x8131, 0xa200, 0x3d12,
+    0x2912, 0xe412, 0x178d, 0xe42e, 0xe161, 0x0100, 0xe162, 0x01f0,
+    0x8800, 0x0022, 0xe184, 0x157e, 0x2832, 0xf098, 0x2912, 0x3c02,
+    0x2912, 0x3c03, 0xe01a, 0xb670, 0x3c04, 0xf15e, 0x2912, 0xaf02,
+    0x3c02, 0x2912, 0x3c03, 0xe01a, 0x3c04, 0x8112, 0x290a, 0xe01a,
+    0xae02, 0x4c04, 0x3c04, 0xa802, 0xf068, 0x2912, 0xaf02, 0x3c02,
+    0x290a, 0x3c03, 0x2804, 0x8112, 0x8112, 0xf08a, 0x2802, 0x3d11,
+    0x2803, 0x3d11, 0x2804, 0x3d11, 0xf0ae, 0x8111, 0x8111, 0x2901,
+    0xa201, 0x3f11, 0xf04a, 0x2901, 0xe412, 0x178d, 0x8111, 0xe42e,
+    0x28a5, 0xe428, 0x2834, 0xe428, 0x2cd5, 0x3c01, 0x2801, 0xa002,
+    0xc70f, 0x7c12, 0xaf20, 0x3c01, 0x1c31, 0xe42a, 0xe41e, 0x1516,
+    0xe41e, 0x1501, 0xf74e, 0xe161, 0x0100, 0xe162, 0x01f0, 0x8800,
+    0x0022, 0xe184, 0x15bb, 0x2832, 0xf0c8, 0x2911, 0x3d12, 0x2911,
+    0x2b11, 0xa807, 0xb616, 0x3d12, 0xa200, 0x3d12, 0x3d12, 0xf14e,
+    0x2911, 0xae02, 0xa002, 0x1833, 0x3d12, 0x2911, 0x2b09, 0xa803,
+    0xb616, 0x3d0a, 0x2912, 0x8112, 0xaa02, 0x3d12, 0x2911, 0x2b11,
+    0xa805, 0xb616, 0x3d12, 0x8111, 0xe161, 0x0230, 0xe162, 0x01f0,
+    0xd022, 0x003f, 0xe184, 0x15c5, 0x2912, 0x3d11, 0xe42e, 0x2832,
+    0xf0d8, 0xe41e, 0x162e, 0x2808, 0xe000, 0x0270, 0xe096, 0xe41e,
+    0x166f, 0x2808, 0x0809, 0x3cc0, 0xe42e, 0xe41e, 0x162e, 0xe163,
+    0x0270, 0x2808, 0xe41e, 0x172d, 0x3c08, 0xe000, 0x0270, 0xe096,
+    0xe41e, 0x166f, 0x2808, 0xe000, 0x0270, 0xe096, 0x2809, 0xe41e,
+    0x172d, 0x0808, 0x3cc0, 0xe42e, 0x2832, 0xf158, 0xe41e, 0x16a8,
+    0x2808, 0xe000, 0x0290, 0xe096, 0xe41e, 0x166f, 0x2808, 0xe000,
+    0x02b0, 0xe096, 0xe41e, 0x166f, 0x2808, 0x0809, 0x3cc0, 0xe41e,
+    0x1770, 0xe42e, 0xe41e, 0x16a8, 0xe163, 0x0290, 0x2808, 0xe41e,
+    0x172d, 0xe163, 0x02b0, 0x2808, 0xe41e, 0x172d, 0x3c08, 0x2808,
+    0xe000, 0x0290, 0xe096, 0xe41e, 0x166f, 0x2808, 0xe000, 0x0290,
+    0xe096, 0x2809, 0xe41e, 0x172d, 0x2808, 0xe000, 0x02b0, 0xe096,
+    0xe41e, 0x166f, 0x2808, 0xe000, 0x02b0, 0xe096, 0x2809, 0xe41e,
+    0x172d, 0x0808, 0x3cc0, 0xe41e, 0x1770, 0xe42e, 0xe161, 0x05e0,
+    0xa200, 0xc70f, 0x3d11, 0x2832, 0xb674, 0x3c05, 0xa200, 0x3c08,
+    0xc420, 0xe163, 0x0270, 0xa2fe, 0x3c06, 0xa203, 0xae21, 0xe013,
+    0xe161, 0x0102, 0xe162, 0x05e0, 0x8800, 0x0022, 0xe184, 0x165e,
+    0x2912, 0xf158, 0x2909, 0x1805, 0xf114, 0x2909, 0xf0e6, 0x2901,
+    0x1c31, 0xf026, 0x1c12, 0x0c31, 0xe046, 0xf076, 0xe042, 0xe049,
+    0xe084, 0xe002, 0x05e1, 0x3c06, 0x8111, 0x8111, 0x8131, 0x2806,
+    0xe424, 0xe000, 0x05e0, 0xe094, 0xa202, 0x3d02, 0x2806, 0xae02,
+    0x3d13, 0x2808, 0xa002, 0x3c08, 0x1816, 0xf4e8, 0xe42e, 0xe161,
+    0x05e0, 0xa200, 0xc70f, 0x3d11, 0x2832, 0xb674, 0x3c05, 0xa200,
+    0x3c09, 0xc420, 0xa2fe, 0x3c07, 0xa221, 0xe161, 0x0102, 0xe162,
+    0x05e0, 0x8800, 0x0022, 0xe184, 0x1697, 0x2912, 0xf118, 0x2909,
+    0x1805, 0xf0d4, 0x2909, 0xf0a2, 0x2901, 0xe046, 0xf072, 0xe042,
+    0xe049, 0xe084, 0xe002, 0x05e1, 0x3c07, 0x8111, 0x8111, 0x8131,
+    0x2807, 0xe424, 0xe000, 0x05e0, 0xe094, 0xa202, 0x3d02, 0x2807,
+    0xae02, 0x3d13, 0x2809, 0xa002, 0x3c09, 0x1816, 0xf548, 0xe42e,
+    0xe161, 0x05e0, 0xa200, 0xc70f, 0x3d11, 0x2832, 0xb674, 0x3c05,
+    0xa200, 0x3c0a, 0xc420, 0xe163, 0x0290, 0xe164, 0x02b0, 0xa2fe,
+    0x3c06, 0x3c07, 0xe161, 0x0102, 0xe162, 0x05e0, 0xe165, 0x0140,
+    0x8800, 0x0022, 0xe184, 0x16f3, 0x2912, 0xf2c8, 0x2909, 0x1805,
+    0xf284, 0x2909, 0xf256, 0x2115, 0x4d0d, 0x10c7, 0x1cc8, 0xf110,
+    0x2806, 0xf064, 0x2115, 0x4d0d, 0x100c, 0x1c0d, 0xf196, 0x2115,
+    0x4d0d, 0x340c, 0x3c0d, 0xe084, 0xe002, 0x05e1, 0x3c06, 0xf10e,
+    0x2807, 0xf064, 0x2115, 0x4d0d, 0x100e, 0x1c0f, 0xf092, 0x2115,
+    0x4d0d, 0x340e, 0x3c0f, 0xe084, 0xe002, 0x05e1, 0x3c07, 0x8111,
+    0x8111, 0x8131, 0x8115, 0x8115, 0x2806, 0xf094, 0xe000, 0x05e0,
+    0xe094, 0xa202, 0x3d02, 0x2806, 0xae02, 0x3d13, 0x2807, 0xf094,
+    0xe000, 0x05e0, 0xe094, 0xa202, 0x3d02, 0x2807, 0xae02, 0x3d14,
+    0x280a, 0xa002, 0x3c0a, 0x1816, 0xe408, 0x16b7, 0xe086, 0xe002,
+    0x0290, 0x3c0c, 0xe088, 0xe002, 0x02b0, 0x3c0d, 0xf09a, 0xa102,
+    0xcc44, 0xe164, 0x02b0, 0xe184, 0x171e, 0x2914, 0x3d13, 0x280c,
+    0xf09a, 0xa102, 0xcc44, 0xe163, 0x0290, 0xe184, 0x1728, 0x2913,
+    0x3d14, 0x280c, 0x080d, 0x3c08, 0xe42e, 0xe42a, 0xa102, 0x3c0c,
+    0xe086, 0xe098, 0xe161, 0x05e0, 0x880c, 0x0022, 0xe184, 0x1748,
+    0x2903, 0xae02, 0xe000, 0x0102, 0xe094, 0x2902, 0xa802, 0xf03a,
+    0x2903, 0x3d11, 0x2902, 0xa804, 0xf04a, 0x2903, 0xa002, 0x3d11,
+    0x8113, 0xe082, 0xe002, 0x05e0, 0xe42a, 0xa102, 0x3c0c, 0x3c0d,
+    0x2833, 0x3c0e, 0xe161, 0x05e0, 0x880c, 0x0022, 0xe184, 0x175d,
+    0x2901, 0xf044, 0xa802, 0x180e, 0xf06a, 0x8111, 0x280e, 0xe016,
+    0x3c0e, 0xf71e, 0x2901, 0x3d14, 0xa2fe, 0x3d01, 0x280e, 0xe016,
+    0x3c0e, 0x280d, 0xa102, 0x3c0d, 0xf662, 0x280c, 0xa002, 0xe42e,
+    0x28c0, 0xa102, 0xe426, 0xcc44, 0xe163, 0x0290, 0xe164, 0x02b0,
+    0xe184, 0x177d, 0x2913, 0x1914, 0xe428, 0xe190, 0xe163, 0x0291,
+    0xe164, 0x02b0, 0x290b, 0x3d14, 0x2903, 0x3d14, 0xe42e, 0xe161,
+    0x0518, 0xa200, 0xc71f, 0x3d11, 0xe42e, 0xe000, 0x0518, 0xe09e,
+    0x2907, 0xa80c, 0x3d07, 0xe42e, 0xe000, 0x0518, 0xe09e, 0x2907,
+    0xa80a, 0x3d07, 0xe42e, 0x3cd6, 0xe000, 0x0518, 0xe09e, 0x2907,
+    0xa806, 0x3d07, 0x28d6, 0xa002, 0x3cd6, 0x18d4, 0xe428, 0xa200,
+    0x3cd6, 0xe42e, 0xe000, 0x0518, 0xe09e, 0x2907, 0xe056, 0x3d07,
+    0xe42e, 0xe161, 0x0518, 0x28d4, 0xa102, 0xcc44, 0xa200, 0xe184,
+    0x17bc, 0x2b11, 0xa807, 0xe01b, 0xe042, 0x18df, 0xa102, 0xe01a,
+    0xe42e, 0xe161, 0x0518, 0x28d4, 0xa102, 0xcc44, 0xe184, 0x17cb,
+    0x2911, 0xe016, 0xf028, 0xe190, 0xe42e, 0x28d6, 0x3c00, 0x2800,
+    0xe000, 0x0518, 0xe092, 0x2901, 0xf12a, 0x2800, 0xa002, 0x3c00,
+    0x18d4, 0xf038, 0xa200, 0x3c00, 0x2800, 0x18d6, 0xf718, 0xa200,
+    0x3cd6, 0xa2fe, 0x3cc1, 0xe0c2, 0x0077, 0xe42e, 0xa20e, 0x3d01,
+    0x2800, 0x3cc1, 0xe0c2, 0x0077, 0xe42e, 0xe0c0, 0x0060, 0xe049,
+    0xa861, 0xe42b, 0xe0c1, 0x0044, 0xae1b, 0xe0c3, 0x0102, 0xe049,
+    0xa83e, 0x3caf, 0xaf0b, 0x3eae, 0x2848, 0xae04, 0x0848, 0x0848,
+    0xe000, 0x0620, 0xe09e, 0x2117, 0x4d17, 0xe0c2, 0x0143, 0x2117,
+    0x4d17, 0xe0c2, 0x0144, 0x2117, 0x4d17, 0xe0c2, 0x0145, 0xa200,
+    0xe0c2, 0x0140, 0xe0c2, 0x0149, 0x2867, 0xe0c2, 0x0141, 0xe0c0,
+    0x0064, 0xe0c2, 0x014c, 0x2850, 0xa102, 0xae20, 0x4c51, 0xa102,
+    0xe0c2, 0x0142, 0x28ae, 0xae08, 0x2aaf, 0xa81f, 0xe056, 0xe0c2,
+    0x014e, 0xe0c0, 0x0061, 0xe0c2, 0x0146, 0xe0c0, 0x0062, 0xe0c2,
+    0x0147, 0xe0c0, 0x0063, 0xe0c2, 0x0148, 0xa200, 0x3cad, 0xe41e,
+    0x184b, 0xe41e, 0x1862, 0x28ad, 0xa8fe, 0x1851, 0xf798, 0xa204,
+    0xae1c, 0xe0c2, 0x014d, 0xa202, 0xe0c2, 0x014a, 0xe190, 0xe0c1,
+    0x014b, 0xf7e9, 0xe42e, 0xa205, 0x28ad, 0xb615, 0xa903, 0x3e0d,
+    0x2848, 0xe000, 0x06e0, 0xe092, 0x2901, 0xae04, 0x4c0d, 0xae1c,
+    0x4cad, 0xe0c2, 0x014d, 0xa202, 0xe0c2, 0x014a, 0xe0c1, 0x014b,
+    0xf7e9, 0xe42e, 0x28ad, 0xe000, 0x0080, 0x3cad, 0xaf0e, 0x1850,
+    0xe428, 0x28ad, 0xa8fe, 0xa002, 0x3cad, 0xe42e, 0xe41e, 0x1939,
+    0xe41e, 0x19d7, 0xe41e, 0x18e8, 0xe41e, 0x1bc6, 0x285c, 0x4ca3,
+    0xe01a, 0x3c5c, 0xa200, 0x3c52, 0x3c4a, 0xa202, 0x3c88, 0xe41e,
+    0x1ac7, 0x2852, 0xf048, 0xcba2, 0xe40a, 0x18e3, 0x183c, 0xe402,
+    0x18e3, 0xe41e, 0x059d, 0x28a4, 0xf7da, 0xa102, 0xf11a, 0xa108,
+    0xf794, 0xf0ea, 0xa10a, 0xe40a, 0x18e3, 0xa102, 0xe40a, 0x18e3,
+    0xa102, 0xf32a, 0xa10e, 0xf6e2, 0xf3be, 0x283c, 0x3c4a, 0x28a3,
+    0xe01a, 0x2a84, 0xe01b, 0xe05a, 0xf338, 0x28a5, 0x1885, 0xf308,
+    0xe41e, 0x0615, 0xe41e, 0x1a5c, 0xf5da, 0x2888, 0xf06a, 0x283c,
+    0x3c0d, 0xe41e, 0x1aff, 0xf24e, 0xe41e, 0x0636, 0x28a3, 0x3c84,
+    0x28a5, 0x3c85, 0xe41e, 0x08f5, 0xf4da, 0xa201, 0x3e88, 0x284a,
+    0x3c0d, 0x1852, 0xf474, 0xe410, 0x1aff, 0x284a, 0x183c, 0xe402,
+    0x18e3, 0xe40e, 0x187f, 0xba0e, 0xe002, 0x00ff, 0xf058, 0xba4e,
+    0xe41e, 0x05e9, 0xf798, 0xe41e, 0x0862, 0xe40e, 0x1889, 0x2852,
+    0x183c, 0xe402, 0x18df, 0x283c, 0x3c0d, 0xe41e, 0x1aff, 0x2884,
+    0x3ca3, 0x2885, 0x3ca5, 0xe41e, 0x1cdf, 0xcbcc, 0xf7f8, 0xe42e,
+    0x281f, 0xae02, 0x4c2e, 0xae0a, 0x2a2d, 0xa83f, 0xe056, 0xae0a,
+    0x2a29, 0xa83f, 0xe056, 0xae02, 0x4c1a, 0xae02, 0x4c21, 0xae02,
+    0x4c3a, 0xcf80, 0x28a3, 0xe01a, 0xae02, 0x4c18, 0xae02, 0x4c1a,
+    0xae02, 0x4c3a, 0xcfc2, 0x2850, 0xa102, 0xae02, 0x4c2b, 0xae02,
+    0x4c32, 0xae02, 0x4c33, 0xae02, 0x4c3a, 0xcf00, 0xd1d3, 0x000b,
+    0xd185, 0x0001, 0x20c3, 0x4cc4, 0xcfc6, 0xd1e5, 0x0001, 0xc420,
+    0xe161, 0x0101, 0xa200, 0xd022, 0x000f, 0xe184, 0x1921, 0x2b31,
+    0xae02, 0xb42a, 0xcfe8, 0x20c7, 0x4cc8, 0xcfea, 0x20c9, 0x4cca,
+    0xcfec, 0x20cb, 0x4ccc, 0xcfee, 0xe004, 0x0060, 0xce30, 0xe161,
+    0x0160, 0xd022, 0x001f, 0xe184, 0x1937, 0x2111, 0x4d11, 0xce32,
+    0xe42e, 0xa200, 0xe161, 0x00b6, 0xc707, 0x3d11, 0x28b0, 0x4cb1,
+    0xf028, 0xe42e, 0xe161, 0x00b6, 0xa20e, 0x3c00, 0x28b0, 0xf39a,
+    0x28b2, 0x5c00, 0xa802, 0xf108, 0x2a00, 0xa10f, 0xf049, 0xa202,
+    0x3d11, 0xf17e, 0x2a00, 0xa109, 0xf049, 0xa204, 0x3d11, 0xf11e,
+    0xa20a, 0x3d11, 0xf0ee, 0x28b4, 0x5c00, 0xa802, 0xf08a, 0x2800,
+    0xa10a, 0xa205, 0xf024, 0xa203, 0x3f11, 0xf03e, 0xa206, 0x3d11,
+    0x2800, 0xa102, 0x3c00, 0xa102, 0xf5c8, 0x28b2, 0xe00c, 0x00ff,
+    0x2ab4, 0xe056, 0x5c00, 0xa802, 0xf06a, 0xa203, 0x2800, 0xb655,
+    0x3f11, 0xf03e, 0xa206, 0x3d11, 0x2800, 0xa102, 0x3c00, 0xf6ea,
+    0xe161, 0x00b6, 0xa20e, 0x3c00, 0x28b1, 0xe42a, 0x28b3, 0x5c00,
+    0xa802, 0xf188, 0x2800, 0xa10e, 0xf088, 0x2ab0, 0xf03b, 0x8111,
+    0xf1e9, 0xa202, 0x3d11, 0xf1be, 0x2a00, 0xa109, 0xf089, 0x2ab0,
+    0xf03b, 0x8111, 0xf149, 0xa204, 0x3d11, 0xf11e, 0xa20a, 0x3d11,
+    0xf0ee, 0x28b5, 0x5c00, 0xa802, 0xf08a, 0x2800, 0xa10a, 0xa205,
+    0xf024, 0xa203, 0x3f11, 0xf03e, 0xa208, 0x3d11, 0x2800, 0xa102,
+    0x3c00, 0xa102, 0xf548, 0x28b3, 0x5c00, 0x4cb0, 0xa802, 0xf068,
+    0xa203, 0x2800, 0xb655, 0x3f11, 0xf16e, 0x28b5, 0xe00c, 0x00ff,
+    0x2ab3, 0xe052, 0x5c00, 0xa802, 0xf0c8, 0x28b3, 0x5c00, 0xa802,
+    0xf06a, 0xa203, 0x2800, 0xb655, 0x3f11, 0xf05e, 0x8111, 0xf03e,
+    0xa208, 0x3d11, 0x2800, 0xa102, 0x3c00, 0xf5ea, 0xe42e, 0xa202,
+    0xe0c2, 0x013c, 0xa200, 0x3c00, 0x3c01, 0xe161, 0x00b6, 0xe162,
+    0x04c8, 0x2911, 0xa104, 0xf066, 0xa106, 0xe40a, 0x1a26, 0xa004,
+    0xf112, 0xa004, 0xae06, 0x3c04, 0x2800, 0xa10c, 0xf064, 0x2804,
+    0xae04, 0xe000, 0x0018, 0x3c04, 0xe004, 0x0450, 0x0804, 0x3c04,
+    0xf2ee, 0xa201, 0x3e02, 0xa211, 0x3e03, 0xf04a, 0xe005, 0x00e0,
+    0x3e02, 0x2800, 0x2a00, 0xae09, 0xa10c, 0xf05a, 0xa102, 0xf058,
+    0xe005, 0x00a0, 0xa240, 0x3c03, 0x0a02, 0x3e02, 0xe0c0, 0x0041,
+    0x22f0, 0x4ef1, 0xe042, 0xe005, 0x02ab, 0xae11, 0xe042, 0x0802,
+    0xca29, 0xf7f9, 0xce20, 0xd111, 0x05e0, 0x2803, 0xce24, 0xd113,
+    0x0003, 0xca28, 0xf7f8, 0xe004, 0x05e0, 0x3c04, 0x2800, 0xa10c,
+    0xa20f, 0xf024, 0xa23f, 0xcc45, 0x2804, 0xe096, 0xe184, 0x1a40,
+    0x2912, 0x0801, 0xe0c2, 0x013e, 0x2b03, 0xaf11, 0xe0c3, 0x013f,
+    0x2912, 0x0801, 0xe0c2, 0x013e, 0x2b13, 0xe009, 0x00ff, 0xe0c3,
+    0x013f, 0xe162, 0x04c8, 0x2a01, 0xe001, 0x0010, 0x3e01, 0x2800,
+    0xa002, 0x3c00, 0xa10c, 0xe404, 0x19e1, 0xe162, 0x04d8, 0xe40a,
+    0x19e1, 0xe001, 0x0030, 0x3e01, 0xa104, 0xe408, 0x19e1, 0xe16a,
+    0xa200, 0xe0c2, 0x013c, 0xe42e, 0xa200, 0x3c88, 0xe41e, 0x0819,
+    0xe40d, 0x1ac3, 0x2a3a, 0xe419, 0x0ac7, 0x183c, 0xe402, 0x1ac3,
+    0xbc12, 0xe40d, 0x1ac3, 0xa10a, 0xb4a8, 0xa104, 0xe400, 0x1ac3,
+    0xbdfe, 0xe40d, 0x1ac3, 0x1820, 0xf03a, 0xa202, 0x3c88, 0x7411,
+    0x1831, 0xf03a, 0xa202, 0x3c88, 0x2818, 0xf0d8, 0xba40, 0x1832,
+    0xf03a, 0xa202, 0x3c88, 0x2832, 0xf06a, 0xba40, 0x1833, 0xf03a,
+    0xa202, 0x3c88, 0x28a5, 0xf09a, 0xe41e, 0x0819, 0xe40d, 0x1ac3,
+    0x1c3d, 0xf03a, 0xa202, 0x3c88, 0x2813, 0xa102, 0xf034, 0xf14a,
+    0xf29e, 0x7414, 0x1ce3, 0xf03a, 0xa202, 0x3c88, 0x2832, 0xe016,
+    0x4422, 0xf20a, 0xe41e, 0x0833, 0xf1fd, 0x10e4, 0x1ce5, 0xf03a,
+    0xa202, 0x3c88, 0xf17e, 0x2815, 0xf158, 0xe41e, 0x0833, 0xf14d,
+    0x10e3, 0x1ce4, 0xf03a, 0xa202, 0x3c88, 0x2832, 0xe016, 0x4422,
+    0xf09a, 0xe41e, 0x0833, 0xf08d, 0x10e5, 0x1ce6, 0xf03a, 0xa202,
+    0x3c88, 0xa202, 0xe42e, 0xe16a, 0xa200, 0x3c86, 0xe42e, 0xa200,
+    0x3ca2, 0x28a6, 0xf098, 0xa202, 0x3ca0, 0x3ca2, 0x3ca1, 0xd036,
+    0x00ff, 0xd037, 0x0080, 0xe16a, 0x284a, 0x3c52, 0xe41e, 0x1b12,
+    0x2821, 0xf138, 0x2852, 0x183c, 0xf0d2, 0xe41e, 0x1b55, 0xf1ed,
+    0x283a, 0xe418, 0x1b55, 0xf1ad, 0xcb86, 0xa102, 0xf740, 0xc894,
+    0xf728, 0xe41e, 0x0862, 0xe42e, 0xe41e, 0x1b41, 0x2852, 0x183c,
+    0xf0a2, 0xe41e, 0x1b55, 0xf0ad, 0x283a, 0xe418, 0x1b55, 0xf06d,
+    0xbb60, 0xf75a, 0xe41e, 0x0864, 0xe42e, 0xe16a, 0xe42e, 0x28a5,
+    0xe016, 0x3c30, 0xe41e, 0x1b12, 0x2852, 0x180d, 0xf0b2, 0xe41e,
+    0x1b92, 0x283a, 0xe418, 0x1b92, 0x284c, 0xa002, 0x083a, 0x3c4c,
+    0xf74e, 0xe42e, 0x2829, 0x182d, 0xe01a, 0xae04, 0x4c43, 0xae0a,
+    0x4c44, 0xae0a, 0x4c45, 0xcf30, 0x2841, 0xae0a, 0x4c40, 0xae04,
+    0x4c30, 0xcf82, 0xd1c3, 0x0000, 0x2842, 0xcf96, 0x2841, 0xae08,
+    0x4c40, 0xae02, 0x4ccf, 0xae02, 0x4cce, 0xae02, 0x4ccd, 0xae02,
+    0x4c3e, 0xae04, 0x4c30, 0xcfc4, 0x8846, 0x01fa, 0x20c5, 0x4cc6,
+    0xcfc8, 0xd188, 0x0001, 0x2830, 0xa104, 0xe428, 0xd1e5, 0x0002,
+    0xe42e, 0xc868, 0xa80e, 0x3c97, 0x7497, 0xe004, 0x01fe, 0xcc86,
+    0xba50, 0xcc88, 0x2830, 0xe01a, 0x083f, 0xae0c, 0x4c42, 0xcc82,
+    0xd040, 0x0003, 0xc884, 0xf7f8, 0xe42e, 0x2852, 0xe0c2, 0x003f,
+    0xd185, 0x0002, 0xd1d0, 0x003f, 0xe190, 0xe180, 0x28a2, 0xe418,
+    0x074a, 0xe181, 0xcba0, 0xa810, 0xcba3, 0xf239, 0xf7c8, 0xe41e,
+    0x1c91, 0xcbe0, 0xf7f8, 0x2856, 0xe41a, 0x1cba, 0xcba0, 0xcba3,
+    0xf189, 0xf7d8, 0xd186, 0x0001, 0xd185, 0x0004, 0xe41e, 0x1cd1,
+    0xe41e, 0x1862, 0xcb06, 0x3c52, 0xcb8a, 0xaf04, 0x4421, 0xe42a,
+    0xe004, 0x01fe, 0xcc86, 0xba50, 0xcc88, 0xd040, 0x0001, 0xe42e,
+    0xd1d0, 0x0000, 0xd1d1, 0x0000, 0xcb1c, 0xf7f8, 0xcbe0, 0xf7f8,
+    0xe16b, 0xe42e, 0x2852, 0xe0c2, 0x003f, 0xd185, 0x0002, 0xd186,
+    0x0000, 0xd1c2, 0x0001, 0xd1c5, 0x0000, 0xd1c4, 0x0000, 0xd1d0,
+    0x000e, 0xcba0, 0xf7f8, 0x284b, 0xf098, 0xd1c2, 0x0000, 0xd1c5,
+    0x0003, 0xd1c4, 0x0003, 0xd1c8, 0x0000, 0xd1d0, 0x0020, 0xe41e,
+    0x1c91, 0xa200, 0xe0c2, 0x012a, 0xcbe0, 0xf7f8, 0x2856, 0xe41a,
+    0x1cba, 0xcba0, 0xf7f8, 0xd186, 0x0001, 0xd185, 0x0004, 0xe41e,
+    0x1cd1, 0xe41e, 0x1862, 0xcb06, 0x3c52, 0xe42e, 0xa200, 0xe0c2,
+    0x0100, 0xe0c2, 0x013d, 0xcc8e, 0xe004, 0x00ce, 0xe0c2, 0x017c,
+    0xa218, 0xe0c2, 0x017d, 0xe0c0, 0x0050, 0x3008, 0xaf02, 0x3009,
+    0xaf02, 0x300a, 0xaf02, 0x300b, 0xaf0a, 0x300c, 0xaf02, 0x300d,
+    0xaf02, 0x300e, 0xaf02, 0x300f, 0xaf06, 0xa802, 0xe005, 0x0ba6,
+    0xe09f, 0x3d17, 0x280c, 0x4408, 0x3c08, 0x280d, 0x4409, 0x3c09,
+    0x280e, 0x440a, 0x3c0a, 0x280f, 0x440b, 0x3c0b, 0xa200, 0xe0c2,
+    0x0168, 0x2a08, 0xf02b, 0xa904, 0x2a09, 0xf02b, 0xa912, 0x2a0a,
+    0xf02b, 0xa940, 0x2a0b, 0xf02b, 0xa980, 0xe005, 0x0ba6, 0xe09f,
+    0x2b17, 0xae05, 0xe056, 0xe0c2, 0x0169, 0xe0c1, 0x0041, 0xe004,
+    0x0010, 0xae10, 0xe042, 0x2a0c, 0xf06b, 0xe004, 0x05d2, 0xe09e,
+    0x2117, 0x4d17, 0xcf0e, 0xe0c1, 0x0041, 0xe004, 0x0050, 0xae10,
+    0xe042, 0x2a0d, 0xf06b, 0xe004, 0x05d4, 0xe09e, 0x2117, 0x4d17,
+    0xe0c2, 0x0103, 0xa202, 0xe0c2, 0x0210, 0xe0c1, 0x0041, 0xe004,
+    0x007c, 0xae10, 0xe042, 0x2a0e, 0xf06b, 0xe004, 0x05d6, 0xe09e,
+    0x2117, 0x4d17, 0xe0c2, 0x0211, 0xe0c1, 0x0041, 0xe004, 0x00bc,
+    0xae10, 0xe042, 0x2a0f, 0xf06b, 0xe004, 0x05d8, 0xe09e, 0x2117,
+    0x4d17, 0xe0c2, 0x0212, 0x2050, 0x4c51, 0xae08, 0xe0c2, 0x0101,
+    0xe0c2, 0x0283, 0xe0c2, 0x006f, 0xe0c2, 0x004f, 0x2a1f, 0x2058,
+    0x4c59, 0xf02b, 0xae02, 0xe0c2, 0x0078, 0x205a, 0x4c5b, 0xf02b,
+    0xae02, 0xe0c2, 0x0079, 0x281f, 0xe016, 0xae08, 0xe0c1, 0x0044,
+    0xa80f, 0xe056, 0xae1a, 0x4c67, 0xe0c2, 0x0102, 0x283a, 0xae02,
+    0x4c32, 0xae02, 0x4c33, 0xe0c2, 0x0104, 0xe0c1, 0x0065, 0xaf19,
+    0xa803, 0xae17, 0xe056, 0xe0c2, 0x0204, 0xa200, 0xe0c2, 0x0208,
+    0xe41e, 0x1d53, 0xe41e, 0x1d04, 0xe41e, 0x1d27, 0xa202, 0xe0c2,
+    0x0106, 0x2a3a, 0xae07, 0xe167, 0x0ba7, 0x3f17, 0xe41e, 0x1dc5,
+    0xe42e, 0xcb02, 0xaf02, 0xe0c2, 0x0113, 0xe0c2, 0x030d, 0xcb15,
+    0xae03, 0xe056, 0xe0c2, 0x022b, 0xcb94, 0xe0c2, 0x0115, 0xe41e,
+    0x1da4, 0xcba4, 0xe0c2, 0x012a, 0xcb8a, 0xe0c2, 0x0114, 0xa802,
+    0x3c56, 0xe42a, 0xcb14, 0xae0a, 0xcb19, 0xe056, 0xe0c2, 0x0120,
+    0xcb8c, 0xe0c2, 0x0121, 0xcb8e, 0xe0c2, 0x0122, 0xcb90, 0xe0c2,
+    0x0123, 0xe42e, 0xcbd0, 0xe0c2, 0x030c, 0xcbd2, 0xe0c2, 0x0309,
+    0xcbd8, 0xe0c2, 0x030a, 0xcbda, 0xe0c2, 0x030b, 0x2846, 0xe0c2,
+    0x0320, 0xe42a, 0x2847, 0xe0c2, 0x0321, 0xcbf6, 0xe0c2, 0x0322,
+    0xe42e, 0xe0c0, 0x0111, 0xf7e8, 0xa202, 0xe0c2, 0x0110, 0x28af,
+    0xaf08, 0x4cae, 0xe42a, 0xa202, 0xe0c2, 0x014a, 0xe42e, 0xe0c0,
+    0x0111, 0xf7e8, 0xe0c0, 0x0065, 0xaf18, 0xa802, 0xf09a, 0x283c,
+    0x1852, 0xf068, 0xcba2, 0xf048, 0xe0c0, 0x0281, 0xf7ea, 0x28af,
+    0x4cae, 0xe42a, 0x2832, 0x5434, 0xe428, 0xe0c0, 0x014b, 0xf7e8,
+    0xa204, 0xae1c, 0xe0c2, 0x014d, 0xa202, 0xe0c2, 0x014a, 0xe190,
+    0xe0c0, 0x014b, 0xf7e8, 0xe42e, 0xa202, 0xe0c2, 0x0302, 0x2816,
+    0xe42a, 0xa102, 0xcc44, 0xe160, 0x0004, 0xe161, 0x0103, 0xe163,
+    0x0380, 0xe184, 0x1d22, 0x8531, 0xc786, 0xe018, 0xb608, 0xe000,
+    0x0620, 0xe094, 0x2112, 0x4d12, 0x9f13, 0x2112, 0x4d12, 0x9f13,
+    0x2112, 0x4d12, 0x9f13, 0xa200, 0xe0c2, 0x0302, 0xe42e, 0xa202,
+    0xae02, 0xa902, 0xe0c2, 0x0312, 0xa802, 0xe42a, 0xe162, 0x01b0,
+    0x2912, 0xaf02, 0x3c0a, 0x2912, 0xaf02, 0x3c0b, 0x2830, 0xa104,
+    0xf068, 0xe162, 0x01d0, 0x2912, 0xaf02, 0x3c0b, 0x280a, 0x180b,
+    0xf0d8, 0xe162, 0x01b0, 0xd022, 0x001f, 0xe184, 0x1d4c, 0x2912,
+    0xaf02, 0x3c0b, 0x180a, 0xf028, 0xe190, 0x280b, 0xae08, 0x4c0a,
+    0xe0c2, 0x0313, 0xe42e, 0xa200, 0x3caf, 0x3cae, 0x3cad, 0x2848,
+    0xe404, 0x1da3, 0xe0c0, 0x0060, 0xe049, 0xa861, 0xe40b, 0x1da3,
+    0xe049, 0xa83e, 0x3caf, 0xaf0b, 0x3eae, 0x2848, 0xae04, 0x0848,
+    0x0848, 0xe000, 0x0620, 0xe09e, 0x2117, 0x4d17, 0xe0c2, 0x0143,
+    0x2117, 0x4d17, 0xe0c2, 0x0144, 0x2117, 0x4d17, 0xe0c2, 0x0145,
+    0xa200, 0xe0c2, 0x0140, 0xe0c2, 0x0149, 0x2867, 0xe0c2, 0x0141,
+    0xe0c0, 0x0064, 0xe0c2, 0x014c, 0x2850, 0xa102, 0xae20, 0x4c51,
+    0xa102, 0xe0c2, 0x0142, 0x28ae, 0xae08, 0x2aaf, 0xa81f, 0xe056,
+    0xe0c2, 0x014e, 0xe0c0, 0x0061, 0xe0c2, 0x0146, 0xe0c0, 0x0062,
+    0xe0c2, 0x0147, 0xe0c0, 0x0063, 0xe0c2, 0x0148, 0x2834, 0xf04a,
+    0x2851, 0xaf02, 0x3cad, 0xe42e, 0xcb94, 0xa87e, 0x22aa, 0x4eab,
+    0xe042, 0x34aa, 0x3cab, 0x28af, 0x4cae, 0xf17a, 0xa203, 0x28ad,
+    0xb615, 0x3e0d, 0xa203, 0x3e0e, 0x2848, 0xe000, 0x06e0, 0xe092,
+    0x2901, 0xae02, 0x4c0d, 0xae02, 0x4c0e, 0xae1c, 0x4cad, 0xe0c1,
+    0x014b, 0xf7e9, 0xe0c2, 0x014d, 0xe42e, 0xe0c0, 0x0065, 0xaf18,
+    0xa802, 0xe40a, 0x1e47, 0xae0a, 0xe0c1, 0x0060, 0xaf0d, 0xa80f,
+    0xe056, 0xe0c1, 0x0044, 0xa811, 0xe056, 0xae0c, 0xe0c1, 0x0044,
+    0xa80f, 0xe056, 0xe167, 0x0ba7, 0x2f17, 0xe056, 0xe0c2, 0x0282,
+    0xe0c0, 0x006e, 0xe0c2, 0x0284, 0xaf20, 0xe0c1, 0x0282, 0xa809,
+    0xf04b, 0xe049, 0xae1f, 0xf06e, 0xe049, 0xa011, 0xaf09, 0xae07,
+    0xae21, 0xe056, 0xe0c2, 0x028c, 0xe167, 0x0ba8, 0x2d17, 0x4917,
+    0xe0c2, 0x0285, 0xe167, 0x0baa, 0x2d17, 0x4917, 0xe0c2, 0x0286,
+    0xe41e, 0x1e48, 0xe0c0, 0x004a, 0xe0c2, 0x0289, 0xe0c0, 0x004b,
+    0xe0c2, 0x028a, 0xe0c0, 0x0055, 0xe0c2, 0x028b, 0xe0c1, 0x0041,
+    0xe004, 0x0100, 0xae10, 0xe042, 0xe167, 0x0ba6, 0x2b17, 0xf05b,
+    0xe167, 0x0ba0, 0x2d17, 0x4917, 0xe0c2, 0x0287, 0xe0c1, 0x0041,
+    0xe004, 0x0118, 0xae10, 0xe042, 0xe167, 0x0ba6, 0x2b17, 0xf05b,
+    0xe167, 0x0ba2, 0x2d17, 0x4917, 0xe0c2, 0x0288, 0xe0c1, 0x0041,
+    0xe004, 0x0120, 0xae10, 0xe042, 0xe167, 0x0ba6, 0x2b17, 0xf05b,
+    0xe167, 0x0ba4, 0x2d17, 0x4917, 0xe0c2, 0x028d, 0xe0c0, 0x0065,
+    0xaf18, 0xa802, 0xe0c2, 0x0280, 0xa210, 0xe0c2, 0x0168, 0xe42e,
+    0xe167, 0x0bac, 0xe165, 0x028e, 0xe166, 0x02c0, 0xd022, 0x0008,
+    0xe184, 0x1e5b, 0x2d17, 0x9f16, 0x9e85, 0xf7fb, 0x2517, 0x4d17,
+    0x9f16, 0x9e85, 0xf7fb, 0xe190, 0xe166, 0x02d2, 0xd022, 0x0008,
+    0xe184, 0x1e67, 0x2517, 0x4d17, 0x9f16, 0x9e85, 0xf7fb, 0xe190,
+    0xe166, 0x02db, 0xd022, 0x0008, 0xe184, 0x1e73, 0x2517, 0x4d17,
+    0x9f16, 0x9e85, 0xf7fb, 0xe190, 0xe166, 0x02e4, 0xd022, 0x0008,
+    0xe184, 0x1e7e, 0x2d17, 0x9f16, 0x9e85, 0xf7fb, 0xe190, 0xe42e,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
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+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe40e, 0x0020, 0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x0131,
+    0xe470, 0xe190, 0xe40e, 0x0113, 0xe470, 0xe190, 0xe470, 0xe190,
+    0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+    0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x012f, 0xe40e, 0x0131,
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+    0xa200, 0xe0c2, 0x005a, 0x3cf0, 0x3cf1, 0xa2fe, 0x3cee, 0x3cef,
+    0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d, 0xce00, 0xf11e, 0xe0c0,
+    0x005c, 0xe0c1, 0x0059, 0x3eed, 0xa203, 0x5aed, 0xe052, 0xf08a,
+    0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00, 0xe41e,
+    0x008c, 0xe41e, 0x00ab, 0xe0c0, 0x005a, 0x18ee, 0xe0c1, 0x0059,
+    0xa115, 0xb636, 0x2aee, 0xb60a, 0xe418, 0x00fb, 0xe0c0, 0x005b,
+    0xe0c1, 0x005e, 0xae11, 0xe056, 0x18ef, 0xe0c1, 0x0059, 0xa117,
+    0xb636, 0xe418, 0x00b0, 0xe0c0, 0x005a, 0x18ee, 0x2aee, 0xb60a,
+    0xe0c1, 0x0059, 0xa117, 0xb636, 0xe418, 0x00f3, 0xd071, 0x802a,
+    0xe181, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100, 0xe0c0, 0x0059,
+    0xae02, 0xe000, 0x0113, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a,
+    0x3cee, 0xe41e, 0x0100, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11,
+    0xe056, 0x3cef, 0xe40e, 0x0037, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+    0x0058, 0xe0c2, 0x0008, 0xe0c0, 0x0059, 0xf7ea, 0xa11e, 0xf0e8,
+    0xa202, 0xe0c2, 0x0058, 0xe004, 0x093d, 0xe0c2, 0x0070, 0xa200,
+    0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xf6fe, 0xa202, 0xe0c2, 0x0008,
+    0xe0c2, 0x0058, 0xe42e, 0xd101, 0x0001, 0xc70f, 0xa000, 0xe42e,
+    0xa200, 0xe0c1, 0x005b, 0xf27b, 0xa220, 0xa103, 0xf2eb, 0xa230,
+    0xa103, 0xf2bb, 0xa23c, 0xa103, 0xf24b, 0xa258, 0xa103, 0xf25b,
+    0xa260, 0xa103, 0xf22b, 0xa200, 0xa103, 0xf1fb, 0xa26c, 0xa103,
+    0xf1cb, 0xe004, 0x003e, 0xa103, 0xf18b, 0xe004, 0x0044, 0xa105,
+    0xf14b, 0xe004, 0x0046, 0xa103, 0xf10b, 0xe004, 0x0000, 0xa107,
+    0xf0cb, 0xa200, 0xe0c1, 0x005e, 0xf08b, 0xe004, 0x004c, 0xf05e,
+    0xe0c1, 0x005e, 0xf02b, 0xa010, 0xae16, 0xe0c1, 0x0040, 0xe041,
+    0xca28, 0xf7f8, 0xce21, 0xd111, 0x0000, 0xd112, 0x2000, 0xd113,
+    0x000b, 0xe1e1, 0xe42e, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100,
+    0xe004, 0x0133, 0xe67c, 0xe41e, 0x0100, 0xe004, 0x0135, 0xe67c,
+    0x28ee, 0xe008, 0x03ff, 0xcca4, 0xe182, 0x0029, 0xe018, 0x2eee,
+    0xaf15, 0xcca5, 0xe182, 0x0029, 0xe019, 0xae15, 0xe042, 0xae14,
+    0x34f0, 0x3cf1, 0xe42e, 0xe40e, 0x068c, 0xe40e, 0x0137, 0xe40e,
+    0x013b, 0xe40e, 0x013f, 0xe40e, 0x0147, 0xe40e, 0x007e, 0xe40e,
+    0x0153, 0xe40e, 0x014f, 0xe40e, 0x015b, 0xe40e, 0x007e, 0xe40e,
+    0x007e, 0xe40e, 0x007e, 0xe40e, 0x007e, 0xe40e, 0x007e, 0xe40e,
+    0x007e, 0xe40e, 0x007e, 0xe40e, 0x0442, 0xe40e, 0x0455, 0xe41e,
+    0x018a, 0xe40e, 0x007e, 0xe41e, 0x0207, 0xe40e, 0x007e, 0x284d,
+    0xa184, 0xe41e, 0x015f, 0xe41e, 0x0208, 0xe40e, 0x007e, 0x284d,
+    0xa184, 0xe41e, 0x015f, 0xe41e, 0x038c, 0xe40e, 0x007e, 0xe41e,
+    0x03bd, 0xe40e, 0x007e, 0x284d, 0xa184, 0xe41e, 0x015f, 0xe41e,
+    0x04f3, 0xe40e, 0x007e, 0xe41e, 0x03f0, 0xe40e, 0x007e, 0xe42a,
+    0xe0c0, 0x0040, 0xa201, 0xae17, 0xe042, 0xca29, 0xf7f9, 0xce20,
+    0xd111, 0x0000, 0xd112, 0x2000, 0xd113, 0x000b, 0xe1e1, 0xe42e,
+    0xe167, 0x05d2, 0xe166, 0x0064, 0xd022, 0x0003, 0xe184, 0x017a,
+    0x9e16, 0x3517, 0x3d17, 0xe0c0, 0x0069, 0xe167, 0x0ba0, 0x3d17,
+    0x3517, 0xe0c0, 0x006a, 0x3d17, 0x3517, 0xe0c0, 0x006b, 0x3d17,
+    0x3517, 0xe42e, 0xd152, 0x0000, 0xd130, 0x0000, 0x22f0, 0x4ef1,
+    0xa200, 0xc401, 0xe188, 0x07ff, 0x3d11, 0x36f0, 0x3ef1, 0xe41e,
+    0x03db, 0xa2fe, 0x3c10, 0x3c20, 0x3c48, 0xe0c2, 0x0079, 0xe0c2,
+    0x007a, 0xa200, 0xcc44, 0x3cd6, 0x3c4e, 0x3c4b, 0xe0c2, 0x0072,
+    0xe0c2, 0x006c, 0xa202, 0xe0c2, 0x0078, 0xe0c0, 0x0062, 0xaf02,
+    0x301e, 0xaf02, 0xa806, 0x3c75, 0xe41e, 0x0607, 0xe41e, 0x1619,
+    0xe41e, 0x18ae, 0xe41e, 0x0512, 0x286d, 0xe408, 0x0202, 0x28a4,
+    0xa10e, 0xf798, 0xe41e, 0x162c, 0xe41e, 0x0639, 0xe128, 0xe41e,
+    0x0ec3, 0xf71a, 0xa2fe, 0x3c10, 0x2050, 0x4c51, 0xae08, 0xe0c2,
+    0x0071, 0xe0c2, 0x004f, 0x2850, 0xa1f0, 0xf2d0, 0x2851, 0xa188,
+    0xf2a0, 0x281e, 0xf0da, 0x2813, 0xa104, 0xf0aa, 0x28df, 0xe0c2,
+    0x0074, 0xa004, 0xe0c2, 0x0073, 0x28de, 0x3cdc, 0xf09e, 0x2816,
+    0xa004, 0xe0c2, 0x0073, 0xa200, 0xe0c2, 0x0074, 0x3cdc, 0xa200,
+    0x3c6d, 0x285d, 0xae04, 0x4c1a, 0xae02, 0x4c18, 0xae10, 0x4c1c,
+    0xae10, 0x4c4d, 0xe0c2, 0x007b, 0xe41e, 0x05c7, 0xa202, 0xe0c2,
+    0x0070, 0xe42e, 0xa200, 0x3c6d, 0xe0c2, 0x0070, 0xe42e, 0xe42e,
+    0xe167, 0x0620, 0x2117, 0x4d17, 0xe0c2, 0x007d, 0x2117, 0x4d17,
+    0xe0c2, 0x007e, 0x2117, 0x4d17, 0xe0c2, 0x007f, 0xa2fe, 0xe0c2,
+    0x004c, 0xe0c2, 0x004d, 0xe0c2, 0x004e, 0xe0c2, 0x007b, 0xa200,
+    0xcc44, 0xcc4a, 0xcc4c, 0x3c4c, 0x3c62, 0x3c55, 0xe0c2, 0x007a,
+    0x3c5c, 0xd14b, 0x0200, 0xe41e, 0x1137, 0xe0c1, 0x0065, 0xa841,
+    0xf0ab, 0xe167, 0x05e0, 0xc703, 0x3d17, 0xe41e, 0x0434, 0xe004,
+    0x0088, 0x3c46, 0xa2fc, 0xe0c2, 0x0077, 0xa2fa, 0xe0c2, 0x0071,
+    0xa202, 0xe0c2, 0x0076, 0x286e, 0xf07a, 0xe41e, 0x06c8, 0xe41e,
+    0x04f9, 0xa200, 0x3c6e, 0xe41e, 0x117d, 0xf05a, 0xa202, 0x3c6c,
+    0xe40e, 0x0325, 0x2875, 0xa802, 0xf06a, 0xa200, 0x3c69, 0x3c6b,
+    0xe41e, 0x05df, 0xe41e, 0x15e4, 0xd152, 0x0000, 0xd130, 0x0000,
+    0xd1e0, 0x0003, 0xd1ff, 0x03b0, 0xd199, 0x0224, 0xd03a, 0x0000,
+    0xd04c, 0x0000, 0xd008, 0x0000, 0xe41e, 0x18e8, 0xf048, 0xa2ff,
+    0xe0c3, 0x0077, 0xf05a, 0x2886, 0xf088, 0x286c, 0xf06a, 0x2848,
+    0xe412, 0x1915, 0xe40e, 0x0325, 0xa2fc, 0xe0c2, 0x0077, 0xa200,
+    0x3caa, 0x3cab, 0xa202, 0x3c63, 0xe41e, 0x09da, 0xe41e, 0x0512,
+    0x28a4, 0xf7da, 0xa102, 0xe40a, 0x02d6, 0xa108, 0xf784, 0xe40a,
+    0x02d6, 0xa102, 0xf17a, 0xa102, 0xf0fa, 0xa102, 0xf10a, 0xa102,
+    0xf14a, 0xa102, 0xf16a, 0xa102, 0xf14a, 0xa102, 0xf27a, 0xa10e,
+    0xf662, 0xe40e, 0x02d1, 0xe41e, 0x162c, 0xf2ce, 0xe41e, 0x1653,
+    0xf29e, 0xe41e, 0x1185, 0xf26e, 0xba44, 0xe41e, 0x07da, 0xf22e,
+    0x286b, 0xf05a, 0x2875, 0xa802, 0xe016, 0x3c6c, 0x287f, 0xf038,
+    0x287d, 0xf01a, 0x2875, 0xa802, 0xf08a, 0x2849, 0xf06a, 0xa2fa,
+    0xe0c2, 0x0071, 0xe40e, 0x0359, 0xf0de, 0xba0e, 0xe002, 0x00ff,
+    0xf058, 0xba4e, 0xe41e, 0x0561, 0xf798, 0xe41e, 0x07da, 0xe40e,
+    0x0286, 0x2863, 0xe40a, 0x0302, 0xe40e, 0x0286, 0x2863, 0xf12a,
+    0xa202, 0x3c62, 0xe41e, 0x07e4, 0x2a57, 0xa003, 0xe40b, 0x0359,
+    0xe40a, 0x0286, 0x28a3, 0x3c84, 0x28a5, 0x3c85, 0xa200, 0x3c63,
+    0xf13e, 0x28a3, 0xe01a, 0x2a84, 0xe01b, 0xe05a, 0xf118, 0x28a5,
+    0x1885, 0xf0e8, 0xe41e, 0x08b2, 0xe40a, 0x0286, 0x2801, 0xe408,
+    0x0286, 0x2888, 0xf058, 0xe41e, 0x09f4, 0xe40e, 0x0286, 0xe41e,
+    0x0580, 0xf01e, 0x2875, 0xa802, 0xf04a, 0x287e, 0xf34a, 0xf07e,
+    0x287e, 0xe40a, 0x027f, 0xa102, 0xf028, 0xf18e, 0x2884, 0x3ca3,
+    0x2885, 0x3ca5, 0xe41e, 0x1996, 0x282f, 0xa002, 0x3c2f, 0x28a3,
+    0xf048, 0x28c1, 0xe41e, 0x18b4, 0x28a3, 0xe418, 0x1754, 0xe41e,
+    0x1446, 0xe41e, 0x1479, 0x28d3, 0x3cd7, 0x286c, 0xf04a, 0xe41e,
+    0x1599, 0x3cdc, 0xe41e, 0x14a2, 0xf032, 0x2a6c, 0xb7b6, 0xe049,
+    0x1ad4, 0xf045, 0xa2fa, 0x2a6b, 0xb7f2, 0xe0c2, 0x0071, 0xe0c0,
+    0x0071, 0x3c48, 0x2830, 0x2a5c, 0xae3d, 0xe056, 0x2a55, 0xae05,
+    0xe056, 0xe0c2, 0x0073, 0x284c, 0xe0c2, 0x0072, 0x2c4b, 0xa002,
+    0x3c4b, 0xe0c2, 0x0070, 0xc84a, 0xc84d, 0xae20, 0xe056, 0xe0c2,
+    0x0053, 0xe41e, 0x1137, 0xe41e, 0x1602, 0xe41e, 0x04d2, 0xa202,
+    0xe42e, 0xe41e, 0x1137, 0xe41e, 0x0366, 0xe41e, 0x1602, 0xa2fe,
+    0xe0c2, 0x0072, 0xa200, 0xe0c2, 0x0076, 0xe42e, 0xe0c0, 0x0065,
+    0xe008, 0x0100, 0xe42a, 0xe167, 0x0518, 0xe166, 0x05e0, 0xd022,
+    0x0007, 0xe184, 0x037a, 0x2917, 0xae08, 0x4d17, 0xae08, 0x4d17,
+    0xae08, 0x4d17, 0x3d16, 0xe190, 0xca28, 0xf7f8, 0xe167, 0x05c8,
+    0x2117, 0x4d17, 0xce20, 0xd111, 0x05e0, 0xd112, 0x0008, 0xd113,
+    0x0002, 0xca28, 0xf7f8, 0xe42e, 0xd152, 0x0000, 0xd130, 0x0000,
+    0xe41e, 0x0170, 0xca28, 0xf7f8, 0xe0c0, 0x0060, 0xe42a, 0xe0c0,
+    0x0042, 0xce20, 0xd111, 0x0620, 0xd112, 0x00c0, 0xd113, 0x0003,
+    0xca28, 0xf7f8, 0xe0c0, 0x0042, 0xe000, 0x1000, 0xce20, 0xd111,
+    0x0ba8, 0xd112, 0x004c, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe0c0,
+    0x0060, 0x3cd4, 0xe0c0, 0x0061, 0x3c67, 0xe0c0, 0x0062, 0x3472,
+    0x3c73, 0xe0c0, 0x0063, 0x3c74, 0xe42e, 0xca28, 0xf7f8, 0xe0c0,
+    0x0042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0080, 0xd113, 0x0013,
+    0xca28, 0xf7f8, 0xe0c0, 0x0061, 0x3ca7, 0xa202, 0x3ca6, 0xe41e,
+    0x0639, 0xe128, 0xe0c0, 0x0060, 0xf048, 0xe41e, 0x162c, 0xf03e,
+    0xe41e, 0x1653, 0xe42e, 0xe0c0, 0x0040, 0xa201, 0xae17, 0xe042,
+    0xe005, 0x3f00, 0xae03, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111,
+    0x0450, 0xd112, 0x00c8, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e,
+    0xe0c0, 0x0060, 0xf08a, 0xe0c0, 0x0061, 0x2298, 0x4e99, 0xe046,
+    0xaf12, 0xae02, 0x3c9b, 0xe180, 0xe41e, 0x0639, 0xe41e, 0x070d,
+    0xe41e, 0x1619, 0xe41e, 0x18ae, 0xe41e, 0x04c2, 0x28de, 0x2a1e,
+    0xb616, 0x3cdc, 0xa200, 0x3cd6, 0x3cda, 0x3cd9, 0x3cdb, 0x3cd8,
+    0xe166, 0x05ab, 0xc710, 0x3d16, 0xe166, 0x0054, 0x9e06, 0xf16a,
+    0x28d4, 0xa102, 0xcc44, 0xa200, 0x3c68, 0xe184, 0x042b, 0x9e06,
+    0x5c68, 0xa802, 0xf07a, 0x2868, 0xe000, 0x0518, 0xe09e, 0xa208,
+    0x3d07, 0x2868, 0xa002, 0x3c68, 0xe190, 0xa200, 0x3c35, 0xe41e,
+    0x064a, 0xa202, 0x3c6e, 0xe42e, 0xca28, 0xf7f8, 0xe0c0, 0x006b,
+    0xce20, 0xd111, 0x05e0, 0xd112, 0x0004, 0xd113, 0x0002, 0xca28,
+    0xf7f8, 0xe42e, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100, 0xa206,
+    0xe41e, 0x045e, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100, 0xa236,
+    0xe41e, 0x0474, 0xe41e, 0x048a, 0xe42e, 0xa234, 0xe41e, 0x0474,
+    0xe41e, 0x04a6, 0xa204, 0xe41e, 0x045e, 0xe42e, 0x3ced, 0xe0c0,
+    0x0041, 0xe005, 0x0280, 0xae11, 0xe042, 0x22f0, 0x4ef1, 0xe042,
+    0xca29, 0xf7f9, 0xce20, 0xd111, 0x0000, 0xd112, 0x0c00, 0x88ed,
+    0x0113, 0xca28, 0xf7f8, 0xe42e, 0x3ced, 0xe0c0, 0x0041, 0xe005,
+    0x0298, 0xae11, 0xe042, 0x22f0, 0x4ef1, 0xe042, 0xca29, 0xf7f9,
+    0xce20, 0xd111, 0x00c0, 0xd112, 0x0040, 0x88ed, 0x0113, 0xca28,
+    0xf7f8, 0xe42e, 0xe161, 0x07e0, 0x8911, 0x0145, 0x8911, 0x0144,
+    0x8911, 0x0146, 0x8911, 0x0147, 0x8911, 0x0148, 0x2111, 0x4d11,
+    0xce80, 0x2111, 0x4d11, 0xce82, 0x2111, 0x4d11, 0xce84, 0x2111,
+    0x4d11, 0xce86, 0x2111, 0x4d11, 0xcc72, 0xe42e, 0xe161, 0x07e0,
+    0x8b11, 0x0145, 0x8b11, 0x0144, 0x8b11, 0x0146, 0x8b11, 0x0147,
+    0x8b11, 0x0148, 0xca80, 0x3511, 0x3d11, 0xca82, 0x3511, 0x3d11,
+    0xca84, 0x3511, 0x3d11, 0xca86, 0x3511, 0x3d11, 0xc872, 0x3511,
+    0x3d11, 0xe42e, 0xe161, 0x0100, 0xa200, 0xc73f, 0x3d11, 0x3c68,
+    0xd022, 0x000f, 0xe184, 0x04d0, 0xe41e, 0x18b4, 0x2868, 0xa002,
+    0x3c68, 0xe42e, 0xe167, 0x0518, 0xa200, 0x3c68, 0xd022, 0x0007,
+    0xe184, 0x04e0, 0x2b17, 0xa81f, 0x5a68, 0xe056, 0x2a68, 0xa009,
+    0x3e68, 0xe0c2, 0x007d, 0xa200, 0x3c68, 0xd022, 0x0007, 0xe184,
+    0x04ef, 0x2b17, 0xa81f, 0x5a68, 0xe056, 0x2a68, 0xa009, 0x3e68,
+    0xe0c2, 0x007e, 0xe42e, 0xa200, 0x3c69, 0x3c6b, 0x3c6c, 0x3c4b,
+    0xe42e, 0xd146, 0x00c0, 0xd147, 0x00ff, 0xd148, 0x00c0, 0xd144,
+    0x00c0, 0xd145, 0x0000, 0xd14b, 0x0200, 0xa200, 0x3c86, 0xe004,
+    0x0180, 0xce30, 0xca32, 0xca32, 0xce84, 0xca32, 0xce86, 0xd144,
+    0x00c1, 0xe42e, 0x2886, 0xe408, 0x05a1, 0xcaa2, 0xaf10, 0xa102,
+    0xf09a, 0xcaa0, 0xe190, 0x286d, 0xe428, 0xca9c, 0xe418, 0x06c8,
+    0xf75e, 0xcaa0, 0xe190, 0xcaa0, 0xe190, 0xcaa0, 0xe190, 0xcaa0,
+    0x3c00, 0xca9c, 0xe418, 0x06c8, 0x2800, 0xaf0e, 0xf6b8, 0x2800,
+    0xaf0a, 0x3ca3, 0x2800, 0xa83e, 0x3ca4, 0xa10a, 0xe016, 0x3ca5,
+    0xa200, 0x3ca8, 0x3ca7, 0x3ca0, 0xe41e, 0x0544, 0xe41e, 0x0639,
+    0xe128, 0xa200, 0x3c3a, 0xe42e, 0x28a0, 0x44a1, 0xf048, 0xd149,
+    0x0000, 0xf03e, 0xd149, 0x0080, 0xd14a, 0x0000, 0xd14c, 0x0001,
+    0xca9c, 0xe418, 0x06c8, 0xca9a, 0xf7c8, 0xca9c, 0xf7a8, 0xca9e,
+    0x3ca6, 0xcc92, 0xca94, 0x00a8, 0x0ca7, 0x34a8, 0x3ca7, 0xcc90,
+    0xe42e, 0x28a6, 0xe016, 0xc871, 0xa011, 0xe428, 0xaf07, 0xe009,
+    0x07ff, 0x28a7, 0xe008, 0x07ff, 0xe046, 0xf08a, 0xe049, 0xe011,
+    0xaf15, 0xe421, 0xe420, 0xa200, 0xe42e, 0xc868, 0xa80e, 0xf028,
+    0xa210, 0x3c95, 0x7895, 0xa203, 0x5a95, 0xaf03, 0xe046, 0xe42e,
+    0x28a3, 0x2aa5, 0x3c8a, 0x3e8b, 0x28a7, 0x2aa6, 0x3c8c, 0x3e8d,
+    0xa202, 0x3c86, 0xe0c0, 0x0041, 0x22f0, 0x4ef1, 0xe042, 0xe005,
+    0x029c, 0xae11, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0000,
+    0xd112, 0x0080, 0xd113, 0x0012, 0xca28, 0xf7f8, 0xca2c, 0xf7fa,
+    0xe42e, 0x288a, 0x2a8b, 0x3ca3, 0x3ea5, 0x288c, 0x2a8d, 0x3ca7,
+    0x3ea6, 0xcc90, 0xcc93, 0xa200, 0x3c86, 0x3ca8, 0x3ca0, 0xe0c0,
+    0x0041, 0x22f0, 0x4ef1, 0xe042, 0xe005, 0x029c, 0xae11, 0xe042,
+    0xca29, 0xf7f9, 0xce20, 0xd111, 0x0000, 0xd112, 0x0080, 0xd113,
+    0x0013, 0xca28, 0xf7f8, 0xe41e, 0x0639, 0xe128, 0xe42e, 0xe0c0,
+    0x0048, 0xe002, 0x0200, 0xca89, 0xe003, 0x00c0, 0xa105, 0xae07,
+    0xe042, 0xca8b, 0xe015, 0xa80f, 0xe042, 0x2298, 0x4e99, 0xe045,
+    0xf047, 0x2e9a, 0xae11, 0xe042, 0xe0c2, 0x0046, 0xe42e, 0xa200,
+    0x3c9b, 0x2875, 0xaf02, 0xa802, 0xf05a, 0xe0c0, 0x0068, 0x3498,
+    0x3c99, 0x2098, 0x4c99, 0xe0c1, 0x0067, 0xe042, 0xe0c1, 0x0069,
+    0xa80f, 0xf02b, 0xe042, 0xe005, 0x0049, 0xe093, 0x9f01, 0xe004,
+    0xffff, 0x3c9a, 0xe41e, 0x0639, 0xe41e, 0x070d, 0xa200, 0x3c35,
+    0xe41e, 0x064a, 0xe41e, 0x06c8, 0xe41e, 0x04f9, 0xe42e, 0xa200,
+    0x3c9b, 0xe0c0, 0x0062, 0xaf0c, 0xa802, 0xf10a, 0xe0c1, 0x0048,
+    0xe0c0, 0x0060, 0xe045, 0xaf13, 0xae03, 0xa109, 0x3e9b, 0xf063,
+    0xe0c0, 0x0061, 0xae04, 0xe042, 0x3c9b, 0xe0c0, 0x0060, 0x3498,
+    0x3c99, 0xe0c0, 0x0061, 0xae04, 0x3c9a, 0xe41e, 0x0639, 0xe41e,
+    0x070d, 0xa200, 0x3c69, 0x3c6a, 0x3c6b, 0x3c6c, 0x3c35, 0xe41e,
+    0x064a, 0xd071, 0x802a, 0xe181, 0xe41e, 0x06c8, 0xe41e, 0x04f9,
+    0xe42e, 0xd030, 0x0000, 0xd034, 0x0000, 0xd033, 0x0000, 0xd035,
+    0x0000, 0xd036, 0x007f, 0xd037, 0x0000, 0xd038, 0x0000, 0xd04b,
+    0x0001, 0xe42e, 0x3c64, 0xe08e, 0x3c65, 0xe41e, 0x0656, 0xe41e,
+    0x0671, 0x2865, 0xe09e, 0x2864, 0x3c35, 0xe42e, 0x2835, 0xae08,
+    0xe000, 0x0538, 0xe09e, 0x8b17, 0x0033, 0x8b17, 0x0034, 0x8b17,
+    0x0035, 0x8b17, 0x0036, 0x8b17, 0x0037, 0x8b17, 0x0038, 0xc860,
+    0x3517, 0x3d17, 0xc862, 0x3517, 0x3d17, 0xc864, 0x3517, 0x3d17,
+    0xe42e, 0x2864, 0xae08, 0xe000, 0x0538, 0xe09e, 0x8917, 0x0033,
+    0x8917, 0x0034, 0x8917, 0x0035, 0x8917, 0x0036, 0x8917, 0x0037,
+    0x8917, 0x0038, 0x2117, 0x4d17, 0xcc60, 0x2117, 0x4d17, 0xcc62,
+    0x2117, 0x4d17, 0xcc64, 0xe42e, 0xc000, 0x2835, 0xf0ca, 0xa102,
+    0xe40a, 0x1679, 0xa102, 0xe40a, 0x1679, 0xe41e, 0x0b08, 0xd04c,
+    0x0000, 0xe470, 0x28a6, 0xf078, 0x283a, 0xf088, 0xe41e, 0x09df,
+    0xe41e, 0x0544, 0xd04c, 0x0000, 0xe470, 0xe41e, 0x0aec, 0x28a1,
+    0xf088, 0xa202, 0x3ca1, 0xd037, 0x0000, 0xd04c, 0x0000, 0xe470,
+    0xa200, 0x3ca1, 0xd037, 0x0080, 0xd04c, 0x0000, 0xe470, 0xe40e,
+    0x1679, 0xe41e, 0x0b08, 0xd04c, 0x0000, 0xe470, 0xa200, 0x3ca2,
+    0xe41e, 0x0aec, 0x28a6, 0xcc96, 0x28a1, 0xe016, 0x3ca1, 0xe42e,
+    0x286b, 0xf0ba, 0xe004, 0x0180, 0xce30, 0xe41e, 0x075e, 0xe41e,
+    0x0781, 0xd14e, 0x0000, 0xe42e, 0xe082, 0x3c9c, 0xe004, 0x0048,
+    0xe092, 0xd027, 0x0000, 0x2869, 0xe41a, 0x0717, 0xd027, 0x0001,
+    0x286d, 0xf278, 0xca28, 0xf7f8, 0x2098, 0x4c99, 0x2e9b, 0xae11,
+    0xe042, 0xce20, 0xd111, 0x00c0, 0xd112, 0x0040, 0xe0c0, 0x0043,
+    0xa806, 0xae02, 0xa032, 0xce26, 0xca28, 0xf7f8, 0x2c9b, 0xe000,
+    0x0002, 0x3c9b, 0x1c9a, 0xf024, 0x3c9b, 0xf052, 0x2869, 0x3c6b,
+    0xe418, 0x0763, 0x2098, 0x4c99, 0x2e9b, 0xae11, 0xe042, 0x9f01,
+    0x289c, 0xe092, 0xd14e, 0x0000, 0xe42e, 0x2098, 0x4c99, 0x2e9b,
+    0xae11, 0xe042, 0xe005, 0x0048, 0xe093, 0x9f01, 0xe42e, 0xe0c1,
+    0x0043, 0xa809, 0xe429, 0xa200, 0x3c9d, 0x2098, 0x4c99, 0x2e9b,
+    0xae11, 0xe042, 0x8111, 0x9e89, 0xe045, 0xf043, 0x2c9a, 0xae10,
+    0xe041, 0xe003, 0x0200, 0x2869, 0xb606, 0x3c69, 0xe423, 0xe001,
+    0x0200, 0x3e6a, 0x2869, 0xe428, 0xe0c0, 0x0045, 0xaf04, 0xa802,
+    0x3c69, 0xf648, 0x2875, 0xa802, 0xf07a, 0xe0c1, 0x0059, 0xa103,
+    0xb616, 0x3c69, 0xe42e, 0xe0c0, 0x0059, 0xa102, 0xf068, 0xe0c0,
+    0x0045, 0x306d, 0x286d, 0xe428, 0x289d, 0xf508, 0xe0c0, 0x005c,
+    0xe008, 0x4000, 0xf4ba, 0xe0c0, 0x005d, 0xe00a, 0x4000, 0xe0c2,
+    0x005d, 0xa202, 0xce00, 0x3c9d, 0xe40e, 0x071d, 0xcbe1, 0xf7f9,
+    0xcba1, 0xf7f9, 0xe42e, 0x286a, 0xe42a, 0xe41e, 0x075e, 0xaf04,
+    0xe000, 0x0180, 0xce30, 0x286a, 0xa806, 0xf10a, 0xa209, 0xe045,
+    0xae07, 0x3e0a, 0xa2ff, 0x5a0a, 0xca32, 0xca32, 0xe051, 0xca30,
+    0xa104, 0xe008, 0x01ff, 0xce30, 0xce33, 0xe005, 0x01f0, 0x1a6a,
+    0xf095, 0xe004, 0x010b, 0xce32, 0xa200, 0xce32, 0xce32, 0xce32,
+    0xe42e, 0xa021, 0xaf05, 0xe42b, 0xa200, 0xce32, 0xa103, 0xf7e1,
+    0xe42e, 0xba0c, 0xf03a, 0xbcfc, 0xe42e, 0xba4c, 0xa20c, 0x3c96,
+    0x2896, 0xa002, 0x3c96, 0xa140, 0xf0d2, 0xba40, 0xf7aa, 0x5896,
+    0xa102, 0x349e, 0x3c9f, 0x2896, 0xe41e, 0x07ce, 0x009e, 0x0c9f,
+    0xe42e, 0xe16b, 0xe42e, 0xba0c, 0xf03a, 0xbe7e, 0xe42e, 0xba4c,
+    0xa20c, 0x3c96, 0x2896, 0xa002, 0x3c96, 0xa140, 0xf162, 0xba40,
+    0xf7aa, 0x5896, 0xa102, 0x349e, 0x3c9f, 0x2896, 0xe41e, 0x07ce,
+    0x009e, 0x0c9f, 0x3c9f, 0x8c9f, 0x0000, 0xa002, 0xaf02, 0xe012,
+    0xe42c, 0xe012, 0xe16a, 0xe42e, 0xe16b, 0xe42e, 0xa120, 0xf050,
+    0xa020, 0x3c97, 0x7497, 0xe42e, 0x3c97, 0xba5e, 0x5897, 0x7697,
+    0xe056, 0xe42e, 0xba40, 0xe42a, 0xc868, 0xa80e, 0x3c00, 0xe016,
+    0xe428, 0x7400, 0xe016, 0xe42e, 0xa2fe, 0x3cc1, 0xe0c4, 0x3fff,
+    0xe40d, 0x08a5, 0x3c4a, 0x2a7f, 0xf03b, 0xe408, 0x08a5, 0xbc12,
+    0xe40d, 0x08a5, 0xa10a, 0xb4a8, 0xa104, 0xe400, 0x08a5, 0xb7b4,
+    0xa006, 0x3c30, 0xbdfe, 0xe40d, 0x08a5, 0x1820, 0xf0da, 0x0820,
+    0x3c20, 0xe41e, 0x1667, 0xf088, 0xe0c0, 0x0076, 0xa904, 0xe0c2,
+    0x0076, 0xe40e, 0x08a5, 0x7411, 0x3c31, 0x281b, 0x3c3c, 0x284a,
+    0x183c, 0xe402, 0x08a5, 0x28a5, 0xf06a, 0xe41e, 0x0791, 0xe40d,
+    0x08a5, 0x3c3d, 0xe41e, 0x1411, 0x28c8, 0xe008, 0x03ff, 0xe0c2,
+    0x007a, 0xe40d, 0x08a5, 0x282c, 0xf07a, 0xe41e, 0x0791, 0xe40d,
+    0x08a5, 0xe408, 0x08a5, 0x2875, 0xa802, 0xf24a, 0xe0c0, 0x0065,
+    0xa808, 0xf0f8, 0x3c7f, 0xe0c0, 0x0065, 0xaf06, 0xa806, 0xf3da,
+    0xa102, 0xf07a, 0xa102, 0xf02a, 0xf08e, 0x28a3, 0xf06a, 0xf35e,
+    0xa202, 0x3c7f, 0x28a5, 0xf318, 0xa2fa, 0xe0c2, 0x0071, 0x2830,
+    0x2a5c, 0xae3d, 0xe056, 0xe0c2, 0x0073, 0xa200, 0x3c7e, 0xe40e,
+    0x08a3, 0x287f, 0xf08a, 0x28a5, 0xf18a, 0x287c, 0xf1ea, 0xa102,
+    0x3c7c, 0xf13e, 0xe0c0, 0x0066, 0xf18a, 0x287d, 0xf16a, 0xa102,
+    0xf06a, 0xa102, 0xf068, 0x28a3, 0xf04a, 0xf0fe, 0x28a5, 0xf0d8,
+    0x287c, 0xa102, 0xf06a, 0x3c7c, 0xa200, 0x3c7e, 0xe40e, 0x08a3,
+    0xa202, 0x3c7e, 0xe40e, 0x08a3, 0xa204, 0x3c7e, 0x2824, 0x3c40,
+    0x2830, 0xf07a, 0xba40, 0xf05a, 0xbc3e, 0x3c40, 0xe40d, 0x08a5,
+    0xe41e, 0x18f5, 0xe41e, 0x1746, 0x2830, 0xf0ba, 0xba40, 0xf09a,
+    0xbc06, 0xf1cd, 0xa106, 0xf05a, 0xe41e, 0x0791, 0xf17d, 0xf79e,
+    0xe41e, 0x131b, 0xf13a, 0xe0c6, 0x0033, 0xf10d, 0x282a, 0xf09a,
+    0xbc04, 0xf0cd, 0xa102, 0xf05a, 0xbe0c, 0xf08d, 0xbe0c, 0xf06d,
+    0x2823, 0xe418, 0x0d13, 0xa202, 0xe42e, 0xe16a, 0x28c1, 0xf094,
+    0xe41e, 0x18b4, 0x28c1, 0xe41e, 0x18bb, 0x28c1, 0xe41e, 0x18c2,
+    0xa200, 0xe42e, 0xa200, 0x3c88, 0xe0c4, 0x3fff, 0xe40d, 0x090d,
+    0x3c4a, 0x183c, 0xe402, 0x090d, 0xbc12, 0xe40d, 0x090d, 0xa10a,
+    0xb4a8, 0xa104, 0xe400, 0x090d, 0xbdfe, 0xe40d, 0x090d, 0x1820,
+    0xf03a, 0xa202, 0x3c88, 0x7411, 0x1831, 0xf03a, 0xa202, 0x3c88,
+    0x28a5, 0xf09a, 0xe41e, 0x0791, 0xe40d, 0x090d, 0x1c3d, 0xf03a,
+    0xa202, 0x3c88, 0x2813, 0xa102, 0xf034, 0xf12a, 0xf25e, 0x7414,
+    0x1ce3, 0xf03a, 0xa202, 0x3c88, 0x2822, 0xf1ea, 0xe41e, 0x07ab,
+    0xf25d, 0x10e4, 0x1ce5, 0xf03a, 0xa202, 0x3c88, 0xf15e, 0x2815,
+    0xf138, 0xe41e, 0x07ab, 0xf1ad, 0x10e3, 0x1ce4, 0xf03a, 0xa202,
+    0x3c88, 0x2822, 0xf09a, 0xe41e, 0x07ab, 0xf10d, 0x10e5, 0x1ce6,
+    0xf03a, 0xa202, 0x3c88, 0x282c, 0xf06a, 0xbcfe, 0xf07d, 0xf03a,
+    0xa201, 0x3e88, 0x3c01, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e,
+    0xe41e, 0x098e, 0xd1f3, 0x0000, 0xe162, 0x0270, 0x2912, 0xcfe4,
+    0xe42e, 0x2840, 0x3c04, 0xe161, 0x0270, 0xe162, 0x01b0, 0xe41e,
+    0x092e, 0xe42a, 0xd1f3, 0x0000, 0xe162, 0x01b0, 0x8840, 0x0022,
+    0xe184, 0x092b, 0x2912, 0xcfe4, 0xa202, 0xe42e, 0xba40, 0xf098,
+    0x8804, 0x0022, 0xe184, 0x0935, 0x2911, 0x3d12, 0xa202, 0xe42e,
+    0x28c0, 0xe42a, 0xe082, 0x3c08, 0x2c12, 0x3400, 0x3c01, 0x2c31,
+    0x3402, 0x3c03, 0x2804, 0x3c05, 0xe163, 0x05e0, 0xa200, 0xc71f,
+    0x3d13, 0xbc06, 0xe40d, 0x098b, 0xf06a, 0xa102, 0xf13a, 0xa102,
+    0xf1ba, 0xf28e, 0xe41e, 0x0791, 0xe40d, 0x098b, 0xa002, 0x1002,
+    0x1c03, 0xe012, 0xf032, 0x0000, 0x0c01, 0x3402, 0x3c03, 0xa203,
+    0xf0de, 0xe41e, 0x0791, 0xe40d, 0x098b, 0xa002, 0x0002, 0x0c03,
+    0x1000, 0x1c01, 0xf70e, 0xbc40, 0xa2ff, 0xe41e, 0x09aa, 0xf1c4,
+    0x3d12, 0xe41e, 0x09c5, 0x2805, 0xa102, 0x3c05, 0xa004, 0xe42a,
+    0xf51e, 0x2808, 0xa102, 0xe092, 0xe163, 0x05e0, 0x2805, 0xf0a4,
+    0x2913, 0x8111, 0xf7e8, 0x2901, 0x3d12, 0x2805, 0xa102, 0x3c05,
+    0xf76e, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0x28c1, 0xe424,
+    0x28c1, 0xae04, 0x08c1, 0x08c1, 0xe000, 0x0620, 0xe09e, 0x2117,
+    0x4d17, 0xe0c2, 0x020d, 0xe0c2, 0x0214, 0x2117, 0x4d17, 0xe0c2,
+    0x020e, 0xe0c2, 0x0215, 0x2117, 0x4d17, 0xe0c2, 0x020f, 0xe0c2,
+    0x0216, 0xe42e, 0x3c06, 0x3e07, 0xe163, 0x0230, 0x2816, 0xa102,
+    0xe424, 0xae02, 0xa002, 0xcc44, 0xe184, 0x09c2, 0x2d13, 0x2b0b,
+    0x1c06, 0x1a07, 0xf078, 0xf069, 0xe086, 0xe002, 0x0230, 0xaf02,
+    0xe42e, 0x8113, 0x8113, 0xa2fe, 0xe42e, 0x3c09, 0x2808, 0xe092,
+    0x28c0, 0xa102, 0xcc44, 0xe184, 0x09d0, 0x2901, 0x1809, 0xf03a,
+    0x8111, 0xe42e, 0xe082, 0x1808, 0xe000, 0x05e0, 0xe096, 0xa202,
+    0x3d03, 0xe42e, 0xa200, 0x3c34, 0x3c32, 0x3c33, 0xe42e, 0x2862,
+    0xe42a, 0x2032, 0x4c33, 0x2272, 0x4e73, 0xe042, 0xca29, 0xf7f9,
+    0xce20, 0xd111, 0x0000, 0xd112, 0x0080, 0xd113, 0x0012, 0xca28,
+    0xf7f8, 0xa204, 0x3c62, 0xe42e, 0xe161, 0x05e0, 0x284a, 0x3d11,
+    0x2032, 0x4c33, 0xae10, 0x3511, 0x3d11, 0x2a74, 0xae15, 0xaf10,
+    0xe045, 0xe003, 0x0200, 0xf287, 0x2862, 0xa104, 0xf098, 0x2032,
+    0x4c33, 0xe000, 0x0200, 0x3432, 0x3c33, 0xa200, 0x3c62, 0x2032,
+    0x4c33, 0x2272, 0x4e73, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111,
+    0x0000, 0xd112, 0x0080, 0xd113, 0x0012, 0xca28, 0xf7f8, 0x2032,
+    0x4c33, 0xe000, 0x0200, 0x3432, 0x3c33, 0x2a74, 0xae15, 0xe045,
+    0x28a6, 0xf0b8, 0xf071, 0xe0c0, 0x0076, 0xa908, 0xe0c2, 0x0076,
+    0xf04e, 0xe41e, 0x0544, 0xf5ce, 0xe161, 0x05e2, 0x28a8, 0xe008,
+    0x00ff, 0x4d01, 0x3d11, 0x28a7, 0x3d01, 0x2834, 0xe41e, 0x0b29,
+    0x2834, 0xa002, 0x3c34, 0xe42e, 0x3c00, 0x2834, 0xe40a, 0x0aa2,
+    0xa102, 0x3c04, 0xe161, 0x05e0, 0xe004, 0x270f, 0x3c02, 0xa2fe,
+    0x3c03, 0xe41e, 0x0b3d, 0x2901, 0x1800, 0xf12a, 0x2901, 0x1802,
+    0xf052, 0x2901, 0x3c02, 0x2804, 0x3c03, 0x2804, 0xa102, 0x3c04,
+    0xf712, 0x2803, 0xe404, 0x0aa2, 0x3c04, 0xe41e, 0x0b3d, 0xa200,
+    0x3ca1, 0x2901, 0x3c4a, 0xe004, 0x270f, 0x3d11, 0x2111, 0x4d09,
+    0xaf10, 0xe41e, 0x0b5d, 0x2804, 0xe41e, 0x0b29, 0xe004, 0x0000,
+    0xe005, 0x007f, 0xe41e, 0x0b52, 0x2111, 0x4d01, 0xaf10, 0xe000,
+    0x0200, 0x3436, 0x3c37, 0x2911, 0xe008, 0x00ff, 0xae20, 0x4d01,
+    0x34a8, 0x3ca7, 0xcc90, 0xe002, 0x0200, 0x3438, 0x3c39, 0xb604,
+    0xb628, 0x3ca6, 0xcc92, 0xa202, 0x3c3a, 0x28a6, 0xe428, 0xa202,
+    0x3ca1, 0xe41e, 0x0aec, 0xa200, 0x3ca1, 0xd036, 0x00ff, 0xd037,
+    0x0080, 0xe42e, 0x283c, 0x3c4a, 0xe42e, 0x3c00, 0x3e01, 0x3e39,
+    0x2834, 0xf0ea, 0xa102, 0x3c04, 0xe161, 0x05e0, 0xe41e, 0x0b3d,
+    0x2901, 0x1800, 0xf07a, 0x2804, 0xa102, 0x3c04, 0xf782, 0xa200,
+    0xe42e, 0xca28, 0xf7f8, 0xe004, 0x270f, 0x3d11, 0x2111, 0x4d09,
+    0xaf10, 0x2a01, 0xe41e, 0x0b6f, 0x2804, 0xe41e, 0x0b29, 0x2801,
+    0xae0a, 0xe000, 0x0000, 0xa23f, 0xe41e, 0x0b52, 0x2801, 0xae04,
+    0xe000, 0x0310, 0xe094, 0x2111, 0x4d01, 0xaf10, 0xe000, 0x0080,
+    0x3512, 0x3d12, 0x2911, 0xe008, 0x00ff, 0xae20, 0x4d01, 0x34a8,
+    0x3ca7, 0xcc90, 0xe002, 0x0080, 0x3512, 0x3d12, 0xb604, 0xb628,
+    0x3ca6, 0xcc92, 0xa202, 0xe42e, 0xd115, 0x0001, 0xe190, 0xca28,
+    0xf7f8, 0x2036, 0x4c37, 0xe41e, 0x0b5d, 0xd115, 0x0000, 0x2036,
+    0x4c37, 0xe000, 0x0200, 0x3436, 0x3c37, 0x2038, 0x4c39, 0xe002,
+    0x0200, 0x3438, 0x3c39, 0xb604, 0xb628, 0x3ca6, 0xcc92, 0xe42e,
+    0xe082, 0x3c9c, 0xca28, 0xf7f8, 0x2839, 0xae04, 0xe000, 0x0310,
+    0xe092, 0x2111, 0x4d09, 0x2a39, 0xe41e, 0x0b6f, 0x2111, 0x4d09,
+    0xe000, 0x0080, 0x3511, 0x3d11, 0x2111, 0x4d09, 0xe002, 0x0080,
+    0x3511, 0x3d11, 0xb604, 0xb628, 0x3ca6, 0xcc92, 0x289c, 0xe092,
+    0xe42e, 0xae06, 0xe005, 0x0144, 0xae11, 0xe042, 0xe0c1, 0x0041,
+    0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x05e0, 0xd112, 0x0004,
+    0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0x2804, 0xae06, 0xe005,
+    0x0144, 0xae11, 0xe042, 0xe0c1, 0x0041, 0xe042, 0xca29, 0xf7f9,
+    0xce20, 0xd111, 0x05e0, 0xd112, 0x0004, 0xd113, 0x0003, 0xca28,
+    0xf7f8, 0xe42e, 0xcc66, 0xcc6a, 0xcc6e, 0xe042, 0xcc6c, 0xa200,
+    0xcc60, 0xcc68, 0xcc70, 0xe128, 0xe42e, 0x2272, 0x4e73, 0xe042,
+    0xca29, 0xf7f9, 0xce20, 0xe004, 0x0080, 0x2aa1, 0xb616, 0xce22,
+    0xd112, 0x0080, 0xd113, 0x0013, 0xca28, 0xf7f8, 0xe42e, 0xae0b,
+    0xe001, 0x0000, 0xce23, 0x2272, 0x4e73, 0xe042, 0xce20, 0xd112,
+    0x0020, 0xd113, 0x0013, 0xca28, 0xf7f8, 0xe42e, 0xa206, 0xe41e,
+    0x064a, 0xe004, 0x004e, 0xe0c2, 0x017c, 0xa218, 0xe0c2, 0x017d,
+    0xa200, 0x3cb9, 0x3cba, 0xe41e, 0x0bda, 0x28ba, 0xa002, 0x3cba,
+    0x18b1, 0xf7a4, 0xa200, 0x3c52, 0x3c53, 0x3c54, 0xe41e, 0x0bd1,
+    0x3cba, 0x2852, 0x183c, 0xe402, 0x0bcd, 0xe41e, 0x0bd1, 0x3cb3,
+    0x18ba, 0xe418, 0x0c82, 0x28b3, 0x3cba, 0x28b9, 0xe41a, 0x0c87,
+    0xe41e, 0x0caf, 0x28b9, 0xf07a, 0xe41e, 0x1ac8, 0xf0cc, 0xe16a,
+    0xa200, 0x3cb9, 0x28a5, 0xe016, 0x3c30, 0xe41e, 0x1af4, 0x284c,
+    0xa002, 0x3c4c, 0xe41e, 0x0cd0, 0xcb04, 0x3453, 0x3c54, 0x28b9,
+    0xe40a, 0x0b99, 0xcb86, 0xa102, 0xf550, 0xc894, 0xf538, 0xe41e,
+    0x07da, 0xa200, 0x3cb9, 0xe40e, 0x0b99, 0xa200, 0xe41e, 0x064a,
+    0xe42e, 0x2853, 0xe41a, 0x0cdb, 0xe004, 0x0290, 0x0853, 0xe094,
+    0x2902, 0xe42e, 0xe161, 0x03b0, 0x2830, 0x3d11, 0x2840, 0x3d11,
+    0x2842, 0x3d11, 0x2843, 0x3d11, 0x2844, 0x3d11, 0x2845, 0x3d11,
+    0xcb86, 0x3d11, 0xcb96, 0x3d11, 0x28b9, 0x3d11, 0x28a8, 0x3d11,
+    0x28a7, 0x3d11, 0x28a6, 0x3d11, 0xe162, 0x01b0, 0xd022, 0x000f,
+    0xe184, 0x0bfb, 0x2912, 0x3d11, 0x8b11, 0x0034, 0x8b11, 0x0033,
+    0xc860, 0x3511, 0x3d11, 0xc862, 0x3511, 0x3d11, 0xc864, 0x3511,
+    0x3d11, 0x8b11, 0x0035, 0x8b11, 0x0036, 0x8b11, 0x0037, 0x8b11,
+    0x0038, 0x28ba, 0xae0e, 0xe005, 0x00fc, 0xae11, 0xe042, 0xe0c1,
+    0x0041, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x03b0, 0xd112,
+    0x0028, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0x28b3, 0xae0e,
+    0xe005, 0x00fc, 0xae11, 0xe042, 0xe0c1, 0x0041, 0xe042, 0xca29,
+    0xf7f9, 0xce20, 0xd111, 0x03b0, 0xd112, 0x0028, 0xd113, 0x0003,
+    0xca28, 0xf7f8, 0xe161, 0x03b0, 0x2911, 0x3c30, 0x2911, 0x3c40,
+    0x2911, 0x3c42, 0x2911, 0x3c43, 0x2911, 0x3c44, 0x2911, 0x3c45,
+    0xe41e, 0x1ab3, 0x2911, 0xcf86, 0x2911, 0xcf96, 0x2911, 0x3cb9,
+    0x2911, 0x3ca8, 0x2911, 0x3ca7, 0xcc90, 0x2911, 0x3ca6, 0xcc92,
+    0xe162, 0x01b0, 0xd022, 0x000f, 0xe184, 0x0c5f, 0x2911, 0x3d12,
+    0xd1f3, 0x0000, 0xe162, 0x01b0, 0x8840, 0x0022, 0xe184, 0x0c69,
+    0x2912, 0xcfe4, 0x28b3, 0x3c39, 0x8911, 0x0034, 0x8911, 0x0033,
+    0x2111, 0x4d11, 0xcc60, 0x2111, 0x4d11, 0xcc62, 0x2111, 0x4d11,
+    0xcc64, 0x8911, 0x0035, 0x8911, 0x0036, 0x8911, 0x0037, 0x8911,
+    0x0038, 0xe42e, 0xe41e, 0x0bda, 0xe41e, 0x0c26, 0xe42e, 0x2852,
+    0x2ab3, 0xe41e, 0x0aa5, 0xe42a, 0xe41e, 0x1a01, 0xe16a, 0xe42a,
+    0xe41e, 0x1ab3, 0xe41e, 0x0c97, 0xa202, 0x3cb9, 0xe42e, 0xa203,
+    0x5ab3, 0xe00d, 0x00ff, 0xe161, 0x0330, 0x8850, 0x0022, 0xe184,
+    0x0ca3, 0x2901, 0xe052, 0x3d11, 0x28bb, 0xe052, 0x3cbb, 0x28bc,
+    0xe052, 0x3cbc, 0xe42e, 0xa200, 0x3cbb, 0x3cbc, 0xe42e, 0x2853,
+    0xe41a, 0x0cab, 0x2853, 0xe000, 0x0330, 0xe092, 0x28bb, 0x5cb3,
+    0xa802, 0x3cbd, 0x2911, 0x5cb3, 0xa802, 0xae02, 0x4cbd, 0x3cbd,
+    0x2911, 0x5cb3, 0xa802, 0xae04, 0x4cbd, 0x3cbd, 0x28bc, 0x5cb3,
+    0xa802, 0xae06, 0x4cbd, 0x3cbd, 0xcf12, 0xd18a, 0x0000, 0xe42e,
+    0x2853, 0xe000, 0x0330, 0xe092, 0x2901, 0x3cbc, 0xa202, 0x58b3,
+    0x3d01, 0x3cbb, 0xe42e, 0x2854, 0xae10, 0xe005, 0x0100, 0xae11,
+    0xe042, 0xe0c1, 0x0041, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111,
+    0x0290, 0x2850, 0xa006, 0xe008, 0x007c, 0xce24, 0xd113, 0x0003,
+    0xca28, 0xf7f8, 0xe42e, 0x3cb2, 0xa002, 0x3cb1, 0x281b, 0x3c3c,
+    0xbc0c, 0x3cb0, 0xe42d, 0xe40a, 0x0d33, 0xa102, 0xe40a, 0x0d6b,
+    0xa102, 0xe40a, 0x0d88, 0xa106, 0xe406, 0x0d0b, 0xa102, 0xe40a,
+    0x0e72, 0xe16b, 0xe42e, 0xba40, 0x3cb4, 0xe41e, 0x0791, 0xe42d,
+    0xa002, 0x3cb5, 0xe42e, 0xa200, 0x3cb8, 0x28b0, 0xa106, 0xe424,
+    0xa104, 0xe420, 0x283c, 0x08b5, 0xa102, 0xc70f, 0x7cb5, 0xe008,
+    0xffff, 0xe41e, 0x0eac, 0x3cb8, 0x74b8, 0x3cb6, 0x84b6, 0x82b5,
+    0xe018, 0x643c, 0x3cb6, 0x28b0, 0xa108, 0xe404, 0x0dda, 0xe40a,
+    0x0e48, 0xe40e, 0x0e48, 0xe161, 0x05e0, 0x88b2, 0x0022, 0xe184,
+    0x0d3d, 0xe41e, 0x0791, 0xe42d, 0xa002, 0x3d11, 0xe161, 0x05e0,
+    0xe162, 0x0290, 0xa200, 0x3cb3, 0x3c00, 0x3c53, 0x3c54, 0x2800,
+    0xa002, 0x3c00, 0x1901, 0xf0e6, 0xa200, 0x3c00, 0x28b3, 0xa002,
+    0x3cb3, 0x8111, 0x18b2, 0xf746, 0xa200, 0x3cb3, 0xe161, 0x05e0,
+    0xf6fe, 0x28b3, 0x3d12, 0x2853, 0xa002, 0x3c53, 0x1850, 0xf684,
+    0x3c53, 0xe41e, 0x0e90, 0x2854, 0xa002, 0x3c54, 0x1851, 0xe162,
+    0x0290, 0xf5e4, 0xe42e, 0xa200, 0x3c54, 0xe162, 0x0290, 0x8454,
+    0x82b1, 0xe018, 0xaf02, 0xc70f, 0x7cb1, 0xaf20, 0x2a50, 0xa103,
+    0xcc45, 0xe184, 0x0d7f, 0x3d12, 0xa002, 0xe049, 0x1ab1, 0xb616,
+    0xe41e, 0x0e90, 0x2854, 0xa002, 0x3c54, 0x1851, 0xf674, 0xe42e,
+    0xe167, 0x05e0, 0x28b2, 0xa102, 0xcc44, 0xe184, 0x0d96, 0xe41e,
+    0x0791, 0xe42d, 0x3d17, 0xe41e, 0x0791, 0xe42d, 0x3d17, 0xe162,
+    0x0290, 0x2850, 0xa102, 0x3c04, 0x28b1, 0xa102, 0x8604, 0x3d12,
+    0xa200, 0x3c54, 0xe41e, 0x0e90, 0x2854, 0xa002, 0x3c54, 0x1851,
+    0xf7a4, 0x28b1, 0xa104, 0x3cb3, 0x28b3, 0xae02, 0xe000, 0x05e0,
+    0xe092, 0x2911, 0xc70f, 0x7c50, 0x3400, 0x3c02, 0x2911, 0xc70f,
+    0x7c50, 0x3401, 0x3c03, 0x2802, 0x3c54, 0x1803, 0xf170, 0xca2c,
+    0xf7fa, 0xe41e, 0x0e92, 0x2800, 0xe000, 0x0290, 0xe094, 0x2801,
+    0x1800, 0xf054, 0x3c04, 0x28b3, 0x8604, 0x3d12, 0xe41e, 0x0e90,
+    0x2854, 0xa002, 0x3c54, 0x1803, 0xf6d6, 0x28b3, 0xa102, 0x3cb3,
+    0xf542, 0xe42e, 0xe162, 0x0310, 0xa2fe, 0x2a1b, 0xa01f, 0xaf09,
+    0x3e00, 0x8600, 0x3d12, 0x8450, 0x28b6, 0xe40a, 0x0e31, 0x2850,
+    0x18b4, 0xaf02, 0x3c53, 0x2851, 0x18b4, 0xaf02, 0x3c54, 0x2850,
+    0xa102, 0x3c07, 0x2851, 0xa102, 0x3c08, 0xa2fe, 0x08b4, 0x3c04,
+    0xa200, 0x08b4, 0x3c05, 0xa200, 0x3c00, 0x3c01, 0x3c02, 0xa202,
+    0x3c03, 0xe41e, 0x0eb3, 0xf0aa, 0x2901, 0xe05a, 0x3d01, 0x2800,
+    0xa002, 0x3c00, 0x2800, 0x18b6, 0xf25a, 0x2853, 0x0804, 0xa400,
+    0x6407, 0x3c53, 0x2854, 0x0805, 0xa400, 0x6408, 0x3c54, 0x2802,
+    0xa002, 0x3c02, 0x1803, 0xf668, 0x3c02, 0x2803, 0x0801, 0x3c03,
+    0xa202, 0x1801, 0x3c01, 0x28b4, 0xf078, 0x2804, 0x2a05, 0xe013,
+    0x3e04, 0x3c05, 0xf57e, 0x2804, 0x2a05, 0xe012, 0x3e04, 0x3c05,
+    0xf51e, 0xa200, 0x3c54, 0xe162, 0x0290, 0xa200, 0x3c53, 0xe41e,
+    0x0eb3, 0xe01a, 0x3d12, 0x2853, 0xa002, 0x3c53, 0x1850, 0xf784,
+    0xe41e, 0x0e90, 0x2854, 0xa002, 0x3c54, 0x1851, 0xf6d4, 0xe42e,
+    0x28b4, 0xf038, 0x28b6, 0xf03e, 0x283c, 0x18b6, 0x3c00, 0xa200,
+    0x3c54, 0xe162, 0x0290, 0xa200, 0x3c53, 0x8450, 0x8254, 0xe018,
+    0x0853, 0x2ab0, 0xa109, 0xf05b, 0x8451, 0x8253, 0xe018, 0x0854,
+    0x1800, 0x2ab4, 0xf024, 0xe017, 0x3f12, 0x2853, 0xa002, 0x3c53,
+    0x1850, 0xf6c4, 0xe41e, 0x0e90, 0x2854, 0xa002, 0x3c54, 0x1851,
+    0xf614, 0xe42e, 0xe41e, 0x0791, 0xe42d, 0xa002, 0x183c, 0xe408,
+    0x0d09, 0x28b2, 0xe41e, 0x0eac, 0x3c00, 0xa200, 0x3c54, 0xe162,
+    0x0290, 0x2850, 0xa102, 0xcc44, 0xe184, 0x0e87, 0x7400, 0x3d12,
+    0xe41e, 0x0e90, 0x2854, 0xa002, 0x3c54, 0x1851, 0xf714, 0xe42e,
+    0xa204, 0xf02e, 0xa206, 0x3c09, 0x2854, 0xae10, 0xe005, 0x0100,
+    0xae11, 0xe042, 0xe0c1, 0x0041, 0xe042, 0xca29, 0xf7f9, 0xce20,
+    0xd111, 0x0290, 0x2850, 0xa006, 0xe008, 0x007c, 0xce24, 0x8809,
+    0x0113, 0xca28, 0xf7f8, 0xe42e, 0xa201, 0xf04a, 0xaf02, 0xa003,
+    0xf7e8, 0xe04a, 0xe42e, 0x8254, 0xe018, 0x0853, 0x3c52, 0xaf08,
+    0xe000, 0x0310, 0xe092, 0x2852, 0xa81e, 0x3c06, 0xa203, 0x5a06,
+    0x2901, 0xe052, 0xe42e, 0xba4e, 0x3c4d, 0xba46, 0x3c5d, 0xa810,
+    0xf04a, 0xe004, 0x0042, 0x3c4d, 0xba46, 0xe408, 0x0fc3, 0xba4e,
+    0x3c1c, 0xbc3e, 0x3c10, 0xa202, 0x3c1f, 0x284d, 0xa1c8, 0xf2f8,
+    0xbc06, 0x3c1f, 0xbc08, 0xe408, 0x0fc3, 0xbc08, 0xe408, 0x0fc3,
+    0xba40, 0xba40, 0x3cb0, 0xf23a, 0xa201, 0x3eb2, 0x3eb4, 0xe160,
+    0x0000, 0xba40, 0xf11a, 0x2ab2, 0xae03, 0xe056, 0x3cb2, 0xe080,
+    0xe41e, 0x10dd, 0x2ab4, 0xae03, 0xe056, 0x3cb4, 0xe080, 0xa201,
+    0xe41e, 0x1110, 0xf07e, 0x2ab2, 0xae03, 0x3eb2, 0x2ab4, 0xae03,
+    0x3eb4, 0xe080, 0xa002, 0xe090, 0xa110, 0xf648, 0xbc18, 0xe40d,
+    0x0fc3, 0xa008, 0x3c11, 0xa202, 0x5811, 0x3c12, 0xbc04, 0x3c13,
+    0xe40d, 0x0fc3, 0xa102, 0xf034, 0xf06a, 0xf21e, 0xbc18, 0xa008,
+    0x3c14, 0xf1de, 0xba40, 0x3c15, 0xe41e, 0x07ab, 0x34e7, 0x3ce8,
+    0xe41e, 0x07ab, 0x34e9, 0x3cea, 0xbdfe, 0xe40d, 0x0fc3, 0x3ceb,
+    0xf0ea, 0xa102, 0xcc44, 0xe162, 0x0250, 0xe184, 0x0f32, 0xe41e,
+    0x07ab, 0x3512, 0x3d12, 0xe41e, 0x1057, 0xf01e, 0xe40d, 0x0fc3,
+    0xbc20, 0xe40d, 0x0fc3, 0x3c16, 0xba40, 0x3c17, 0x2250, 0x4e51,
+    0xbcfe, 0xe40d, 0x0fc3, 0xa002, 0x3c50, 0xbcfe, 0xe40d, 0x0fc3,
+    0xa002, 0x3c51, 0x8450, 0x8251, 0xe018, 0x3c1b, 0x2c57, 0xf1ba,
+    0x2050, 0x4c51, 0xe046, 0xf20a, 0x2c57, 0xaf10, 0xe008, 0x00ff,
+    0x1850, 0xf064, 0x2c57, 0xe008, 0x00ff, 0x1851, 0xf152, 0x2050,
+    0x4c51, 0xae08, 0xe0c2, 0x006f, 0xe0c2, 0x004f, 0xa2fe, 0x3c57,
+    0xe40e, 0x0fc3, 0x2850, 0xe008, 0x00ff, 0xae10, 0x2a51, 0xe009,
+    0x00ff, 0xe056, 0x3c57, 0xa200, 0x3c19, 0xba40, 0x3c18, 0xf098,
+    0xba40, 0x3c19, 0x2851, 0xae02, 0x3c51, 0x281b, 0xae02, 0x3c1b,
+    0xe0c0, 0x0059, 0xa102, 0xf038, 0xe41e, 0x1014, 0xba40, 0x3c1a,
+    0x4c18, 0xf3aa, 0xba40, 0x3c58, 0x3c59, 0x3c5a, 0x3c5b, 0xf14a,
+    0xe41e, 0x0791, 0x3c58, 0xe41e, 0x0791, 0x3c59, 0xe41e, 0x0791,
+    0x2a18, 0xf029, 0xae02, 0x3c5a, 0xe41e, 0x0791, 0x2a18, 0xf029,
+    0xae02, 0x3c5b, 0xf21d, 0xe0c0, 0x0059, 0xa102, 0xf0e8, 0x2a1f,
+    0x2058, 0x4c59, 0xf02b, 0xae02, 0xe0c2, 0x0076, 0x205a, 0x4c5b,
+    0xf02b, 0xae02, 0xe0c2, 0x0077, 0xa200, 0x3c82, 0x3c83, 0x281d,
+    0x3cde, 0x3cdf, 0xba40, 0xe016, 0xe41a, 0x106c, 0xf05a, 0xe41e,
+    0x07da, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0xe41e, 0x0791,
+    0x3c20, 0xbc3e, 0xe40d, 0x1011, 0x1810, 0xf0ea, 0x0810, 0x3c10,
+    0xe41e, 0x1644, 0x3c66, 0xa202, 0xe41e, 0x064a, 0xa203, 0x3e94,
+    0x2866, 0xe40a, 0x1011, 0xba40, 0xe408, 0x1011, 0xba40, 0x3c22,
+    0xbc0e, 0xf30d, 0x3c23, 0xf04a, 0xe41e, 0x0cf3, 0xf2bd, 0xbc3e,
+    0xe40d, 0x1011, 0x3c24, 0xbc3e, 0xe40d, 0x1011, 0xba40, 0xba42,
+    0xbe34, 0xe40d, 0x1011, 0xa034, 0x3c28, 0xe404, 0x1011, 0xa168,
+    0xe402, 0x1011, 0xbe34, 0xe40d, 0x1011, 0xa034, 0xe404, 0x1011,
+    0xa168, 0xe402, 0x1011, 0xbe18, 0xe40d, 0x1011, 0x3c29, 0xba40,
+    0x3c2a, 0xba40, 0x3c2b, 0xba40, 0x3c2c, 0xe41e, 0x07da, 0xa202,
+    0xe42e, 0xe16a, 0xa200, 0xe42e, 0x2a1c, 0xa115, 0xe004, 0x0129,
+    0xf2d7, 0xa103, 0xe004, 0x02a3, 0xf297, 0xa113, 0xe004, 0x06f6,
+    0xf257, 0xa103, 0xe004, 0x0dec, 0xf217, 0xa113, 0xe004, 0x17bb,
+    0xf1d7, 0xa103, 0xe004, 0x34bc, 0xf197, 0xa103, 0xe004, 0x3c00,
+    0xf157, 0xa113, 0xe004, 0x6000, 0xf117, 0xa103, 0xe004, 0x6600,
+    0xf0d7, 0xa111, 0xe004, 0x1437, 0xae08, 0xf087, 0xa103, 0xe004,
+    0x21c0, 0xae08, 0xf037, 0xe004, 0x17bb, 0xae12, 0x841b, 0xe182,
+    0x0180, 0xe019, 0xc407, 0xd022, 0x000f, 0xe184, 0x1051, 0xe046,
+    0xf034, 0x8117, 0xe190, 0xe08e, 0xa520, 0x3c1d, 0xe42e, 0xe0c0,
+    0x0041, 0x22f0, 0x4ef1, 0xe042, 0xe005, 0x029e, 0xae11, 0xe042,
+    0xca29, 0xf7f9, 0xce20, 0xd111, 0x0250, 0xd112, 0x0200, 0xd113,
+    0x0002, 0xca28, 0xf7f8, 0xe42e, 0xba40, 0xf15a, 0xba4e, 0xe0c1,
+    0x0059, 0xa103, 0xf039, 0xe0c2, 0x006c, 0xe002, 0x00ff, 0xf0b8,
+    0xba5e, 0xba5f, 0xae20, 0xe056, 0xe0c1, 0x0059, 0xa103, 0xf039,
+    0xe0c2, 0x006c, 0xba40, 0xf02a, 0xba40, 0xba40, 0xf08a, 0xba44,
+    0xba40, 0xba40, 0xf04a, 0xba4e, 0xba4e, 0xba4e, 0xba40, 0xf03a,
+    0xbc0a, 0xbc0a, 0xba40, 0xf08a, 0xba7e, 0xe0c2, 0x0079, 0xba7e,
+    0xe0c2, 0x007a, 0xba40, 0xba40, 0x3c82, 0xe016, 0xe161, 0x05bc,
+    0xe41a, 0x10c2, 0xf1da, 0xba40, 0x3c83, 0xe016, 0xe161, 0x05c1,
+    0xe41a, 0x10c2, 0xf15a, 0x2882, 0x4c83, 0xf02a, 0xba40, 0xba40,
+    0x3c4f, 0xba40, 0xf0aa, 0xba40, 0xbc20, 0xbc20, 0xbc20, 0xbc20,
+    0xbc20, 0x3cde, 0xbc20, 0x3cdf, 0xe16a, 0xa202, 0xe42e, 0xe16a,
+    0xa200, 0xe42e, 0xe41e, 0x0791, 0xcc44, 0xa002, 0x3d11, 0xba46,
+    0xba46, 0xe184, 0x10cf, 0xe41e, 0x0791, 0xe41e, 0x0791, 0xba40,
+    0xba48, 0xa002, 0x3d11, 0xba48, 0xa002, 0x3d11, 0xba48, 0xa002,
+    0x3d11, 0xba48, 0x3d11, 0xa202, 0xe42e, 0xd022, 0x000f, 0xa10c,
+    0xf034, 0xd022, 0x003f, 0xe161, 0x05e0, 0xa210, 0x3c06, 0x3c07,
+    0xa200, 0x3c08, 0x3c09, 0xe09c, 0xe09e, 0xe184, 0x110d, 0x2807,
+    0xf10a, 0xe41e, 0x07ab, 0xe42d, 0x0806, 0xe000, 0x0100, 0xe008,
+    0x00ff, 0x3c07, 0x4c09, 0xe01a, 0xe016, 0xe09e, 0xa202, 0x3c09,
+    0x2807, 0xf028, 0x2806, 0x3c06, 0xe08d, 0xa003, 0xe09d, 0xa803,
+    0xf059, 0xe085, 0xae11, 0xe056, 0x3d11, 0xe094, 0xe08e, 0xe42e,
+    0x3e08, 0x3c06, 0xa211, 0x3e07, 0xa10c, 0xf064, 0xb690, 0xa00c,
+    0x3c06, 0xa240, 0x3c07, 0x2806, 0x2a08, 0xf02b, 0xa01c, 0xae08,
+    0x3c06, 0xe0c0, 0x0041, 0x22f0, 0x4ef1, 0xe042, 0xe005, 0x02ab,
+    0xae11, 0xe042, 0x0806, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x05e0,
+    0x2807, 0xce24, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0xe0c0,
+    0x0065, 0xaf0c, 0xa80e, 0xe42a, 0xca28, 0xf7f8, 0xe0c0, 0x006a,
+    0xce20, 0xd111, 0x05c6, 0xd112, 0x000c, 0xd113, 0x0003, 0xca28,
+    0xf7f8, 0xc410, 0xe167, 0x05c6, 0xe0c0, 0x0065, 0xe008, 0x0100,
+    0x3d17, 0xa220, 0x3d17, 0x8137, 0xe0c0, 0x0065, 0xe008, 0x0080,
+    0xae04, 0x3d17, 0x281b, 0x3d17, 0x8137, 0xe0c0, 0x0065, 0xa880,
+    0xae08, 0x2aa5, 0xf069, 0x2a4d, 0xa185, 0xf02b, 0xa002, 0xa002,
+    0x3d17, 0x281b, 0x3d17, 0x8137, 0xe0c0, 0x0065, 0xaf0c, 0xa80e,
+    0xe42a, 0xe0c0, 0x006a, 0xce20, 0xd111, 0x05c6, 0xd112, 0x000c,
+    0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0x2875, 0xa802, 0xe42a,
+    0xe0c0, 0x0045, 0xaf04, 0xa802, 0xe42e, 0xa200, 0xba4f, 0xe042,
+    0xe003, 0x00ff, 0xf7cb, 0x3c00, 0xa200, 0xba4f, 0xe042, 0xe003,
+    0x00ff, 0xf7cb, 0x3c01, 0xe41e, 0x119c, 0xe42a, 0xe41e, 0x0561,
+    0xf6d8, 0xe41e, 0x07da, 0xe42e, 0x2800, 0xf10a, 0xa102, 0xf11a,
+    0xa104, 0xf12a, 0xa102, 0xf13a, 0xa102, 0xf14a, 0x2a01, 0xf04b,
+    0xba4e, 0xa103, 0xf7e9, 0xa202, 0xe42e, 0xe41e, 0x11c4, 0xf0de,
+    0xe41e, 0x11eb, 0xf0ae, 0xe41e, 0x1246, 0xf07e, 0xe41e, 0x1256,
+    0xf04e, 0xe41e, 0x1259, 0xf01e, 0xe42a, 0xc868, 0xa80e, 0xe016,
+    0xe428, 0xe41e, 0x07da, 0xe42e, 0xbc3e, 0x1810, 0xf0da, 0x0810,
+    0x3c10, 0xe41e, 0x1644, 0x3c66, 0xa200, 0xe41e, 0x064a, 0xa201,
+    0x3e94, 0x2866, 0xe42a, 0x2882, 0xe161, 0x05bc, 0xe418, 0x11df,
+    0x2883, 0xe161, 0x05c1, 0xe418, 0x11df, 0xa202, 0xe42e, 0x2911,
+    0xa102, 0xcc44, 0xe184, 0x11e9, 0x2901, 0xe41e, 0x07ce, 0x2901,
+    0xe41e, 0x07ce, 0xe42e, 0xe166, 0x004c, 0x2882, 0xe161, 0x05be,
+    0xf038, 0xe161, 0x05c3, 0x4c83, 0xf09a, 0x2911, 0xe41e, 0x07ce,
+    0x2911, 0xe41e, 0x07ce, 0x2911, 0xf02e, 0xa230, 0x3c02, 0x284f,
+    0xe016, 0xe428, 0xba46, 0xe0c2, 0x007b, 0xa112, 0xb604, 0xe42a,
+    0xa012, 0xe049, 0xa200, 0xa107, 0xb426, 0xa105, 0xb426, 0xa105,
+    0xb5f6, 0xcc44, 0xe184, 0x1243, 0xa201, 0xba40, 0xf038, 0x9f96,
+    0xf2be, 0xba42, 0xba40, 0xba48, 0xba40, 0x3c03, 0xba40, 0xba40,
+    0xae32, 0xe055, 0xba4e, 0xe055, 0x2803, 0xf0ba, 0xba4a, 0xae10,
+    0xe055, 0xba4a, 0xae1c, 0xe055, 0xba48, 0xae28, 0xe055, 0xf10e,
+    0xba40, 0xf0ea, 0xba4a, 0xae10, 0xe055, 0xba40, 0xf09a, 0xba4a,
+    0xae1c, 0xe055, 0xba40, 0xf04a, 0xba48, 0xae28, 0xe055, 0x9f96,
+    0x2802, 0xe41e, 0x07ce, 0xe190, 0xa202, 0xe42e, 0x2801, 0xf0da,
+    0xa102, 0xcc44, 0xe004, 0x00ff, 0xe184, 0x124f, 0xba4f, 0xe052,
+    0xe002, 0x00ff, 0xe016, 0xe42a, 0xa202, 0xe42e, 0xe41e, 0x125d,
+    0xe42e, 0xe41e, 0x125d, 0xa202, 0xe42e, 0xe0c0, 0x0065, 0xa878,
+    0xa140, 0xf0aa, 0x2801, 0xa102, 0xcc44, 0xe184, 0x1268, 0xba4e,
+    0xe190, 0xe40e, 0x12c3, 0xa201, 0xe41e, 0x1307, 0x2907, 0xa002,
+    0x3c0c, 0x3d17, 0xa120, 0xf6f0, 0x2907, 0x0801, 0xa00e, 0xaf06,
+    0xae06, 0xe049, 0xaf1f, 0xf0db, 0xa201, 0xe41e, 0x1307, 0x8117,
+    0x8117, 0x2907, 0xa202, 0x3d07, 0xa201, 0xe41e, 0x1305, 0xf5be,
+    0x3d17, 0xa201, 0xe41e, 0x1305, 0xe167, 0x05e0, 0x2800, 0x3d17,
+    0x2801, 0x3d17, 0x2a0c, 0xe41e, 0x1305, 0xa200, 0x3c0b, 0xa200,
+    0xe167, 0x05e0, 0xc703, 0x3d17, 0xe167, 0x05e0, 0x280b, 0xa002,
+    0x3c0b, 0xba4f, 0x2846, 0xa002, 0x3c46, 0xa802, 0xf058, 0x280a,
+    0xae10, 0xe056, 0x3d17, 0x3e0a, 0x2846, 0xa80e, 0xe41a, 0x12c5,
+    0x2801, 0x180b, 0xf6c0, 0x2846, 0xa80e, 0xf0ea, 0x2a46, 0xa803,
+    0xf04b, 0x280a, 0xae10, 0x3d17, 0x2a46, 0xa00f, 0xaf07, 0xae07,
+    0x3e46, 0xe418, 0x12c5, 0xa202, 0xe42e, 0xe0c0, 0x006c, 0xe000,
+    0x0088, 0x1846, 0xf242, 0xe0c0, 0x0065, 0xaf12, 0xa802, 0xf0da,
+    0xa201, 0xe41e, 0x1307, 0x8117, 0x8117, 0x2907, 0xa202, 0x3d07,
+    0xa201, 0xe41e, 0x1305, 0xe42e, 0xe004, 0x0200, 0xe0c1, 0x005d,
+    0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00, 0xe0c0, 0x005d, 0xe008,
+    0x0200, 0xe190, 0xf7b8, 0xe004, 0x0090, 0x3c46, 0xca28, 0xf7f8,
+    0xe0c0, 0x006b, 0x0846, 0xa110, 0xce20, 0xd111, 0x05e0, 0xd112,
+    0x0004, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xa200, 0xe167, 0x05e0,
+    0xc703, 0x3d17, 0xe167, 0x05e0, 0xe42e, 0xa204, 0xf02e, 0xa206,
+    0x3c0d, 0xca28, 0xf7f8, 0xe0c0, 0x006b, 0xae07, 0xe042, 0xce20,
+    0xd111, 0x05e0, 0xd112, 0x0004, 0x880d, 0x0113, 0xca28, 0xf7f8,
+    0xe167, 0x05e0, 0xe42e, 0x2c31, 0x3cd0, 0xa202, 0x3cd1, 0xa200,
+    0x3cd2, 0x3cd3, 0x28a3, 0xe016, 0xe428, 0x28a5, 0xf0ca, 0xe41e,
+    0x13a9, 0xba40, 0xba40, 0xb7f0, 0xb634, 0x3cd1, 0xa200, 0x3cd0,
+    0xa202, 0xe42e, 0xba40, 0xf048, 0xa202, 0x3cd2, 0xe42e, 0x2816,
+    0xe42a, 0xae02, 0x3c09, 0x2812, 0x3400, 0x3c01, 0x2c31, 0x3402,
+    0x3c03, 0xbc0c, 0xe40d, 0x13a6, 0xe40a, 0x13a4, 0xa102, 0xf0ba,
+    0xa102, 0xf1ca, 0xa102, 0xf23a, 0xa102, 0xf35a, 0xa102, 0xf3aa,
+    0xe40e, 0x1391, 0xe41e, 0x0791, 0xe40d, 0x13a6, 0xa002, 0x1002,
+    0x1c03, 0xe012, 0xf032, 0x0000, 0x0c01, 0xa203, 0xe41e, 0x13b0,
+    0xe408, 0x1364, 0xa203, 0x3ed2, 0xf5de, 0xbc40, 0xe40d, 0x13a6,
+    0xa2ff, 0xe41e, 0x13b0, 0xe40a, 0x13a6, 0xf54e, 0xe41e, 0x0791,
+    0xe40d, 0x13a6, 0xa002, 0x1002, 0x1c03, 0xe012, 0xf032, 0x0000,
+    0x0c01, 0x3c06, 0xbc20, 0xf2bd, 0x3c07, 0xe41e, 0x13c8, 0xf27a,
+    0xe40e, 0x1341, 0xbc20, 0xf23d, 0xa102, 0xe41e, 0x13e3, 0xe40e,
+    0x1341, 0xe41e, 0x13a9, 0xa202, 0x3cd3, 0xa200, 0x3cd0, 0xe40e,
+    0x1341, 0xbc20, 0xf14d, 0x3cd0, 0x28d0, 0xa2ff, 0xe41e, 0x13b0,
+    0xf7c8, 0xf07e, 0x28d0, 0xae02, 0xa2ff, 0xe41e, 0x13b0, 0xf7b8,
+    0xa2fe, 0x3cd1, 0xe40e, 0x1341, 0xa202, 0xe42e, 0xe16a, 0xa200,
+    0xe42e, 0xc410, 0xe161, 0x01f1, 0xa200, 0xc71f, 0x3d31, 0xe42e,
+    0x3c04, 0x3e05, 0xe161, 0x01f0, 0x8809, 0x0022, 0xe184, 0x13c3,
+    0x2d11, 0x2b09, 0x1c04, 0x1a05, 0xf068, 0xf059, 0x8111, 0xa200,
+    0x3d09, 0xf05e, 0x8111, 0x8111, 0xa200, 0xe42e, 0xa202, 0xe42e,
+    0x2807, 0xa2ff, 0xe41e, 0x13b0, 0xf7c8, 0xe161, 0x01f0, 0x8809,
+    0x0022, 0xe184, 0x13de, 0x2d11, 0x2b09, 0x1c06, 0xf078, 0xf067,
+    0x2807, 0x3d11, 0xa2fe, 0x3d09, 0xf05e, 0x8111, 0x8111, 0xa200,
+    0xe42e, 0xa202, 0xe42e, 0x3c08, 0xe161, 0x01f0, 0x8809, 0x0022,
+    0xe184, 0x13f3, 0x2d11, 0x2b09, 0x1808, 0xf056, 0xf043, 0x8111,
+    0xa200, 0x3d09, 0x8111, 0x8111, 0xe42e, 0x2816, 0x184e, 0xf112,
+    0x884e, 0x0022, 0xe161, 0x0102, 0xe184, 0x1407, 0x2911, 0xf06a,
+    0x2909, 0xe412, 0x18b4, 0xa200, 0x3d11, 0xe082, 0xa006, 0xe092,
+    0x2816, 0xb62c, 0x3c4e, 0x2813, 0xa104, 0xe428, 0xe41e, 0x1599,
+    0xe42e, 0x2813, 0xa102, 0xf034, 0xf0da, 0xf27e, 0x7414, 0x3ce3,
+    0x2822, 0xe418, 0x07ab, 0xe42d, 0x34e4, 0x3ce5, 0xe41e, 0x14da,
+    0xf1ee, 0xa200, 0x34e3, 0x3ce4, 0x34e5, 0x3ce6, 0x2815, 0xf0d8,
+    0xe41e, 0x07ab, 0xe42d, 0x34e3, 0x3ce4, 0x2822, 0xf06a, 0xe41e,
+    0x07ab, 0xe42d, 0x34e5, 0x3ce6, 0xe41e, 0x1516, 0xf08e, 0x34e3,
+    0x3ce4, 0x34e5, 0x3ce6, 0xf03e, 0xe41e, 0x1559, 0x20c9, 0x4cca,
+    0x22cb, 0x4ecc, 0xe066, 0x34c7, 0x3cc8, 0xe42e, 0x281e, 0xf04a,
+    0x2813, 0xa104, 0xf088, 0x28c1, 0x3c01, 0xe41e, 0x18bb, 0xe41e,
+    0x15d4, 0xe42e, 0x28a5, 0x4cd3, 0xe418, 0x1599, 0x28d8, 0xae02,
+    0xe000, 0x0578, 0xe092, 0x20c7, 0x4cc8, 0x3511, 0x3d11, 0x28d8,
+    0xe000, 0x059a, 0xe092, 0x28c1, 0x3d11, 0x28d8, 0xa002, 0x3cd8,
+    0xa200, 0x3c0c, 0xe41e, 0x18d8, 0xf098, 0xe41e, 0x159e, 0x280c,
+    0xa180, 0xf052, 0xa082, 0x3c0c, 0xf76e, 0xe42e, 0xe41e, 0x18ae,
+    0xe42e, 0x28c1, 0xe424, 0xe000, 0x0700, 0xe092, 0x20aa, 0x4cab,
+    0x8450, 0x8251, 0xe019, 0xe41e, 0x148b, 0xe049, 0xa141, 0xf027,
+    0xa240, 0x3d01, 0xe42e, 0x3e0a, 0xa201, 0xf032, 0xe012, 0xa203,
+    0x3e0e, 0x3c0b, 0xaf20, 0xc70f, 0x7c0a, 0x3c0c, 0xaf20, 0xae20,
+    0x4c0b, 0xc70f, 0x7c0a, 0x3c0d, 0x200c, 0x4c0d, 0x2a0e, 0xe42b,
+    0xe012, 0xe42e, 0xe41e, 0x117d, 0xf04a, 0xe41e, 0x1599, 0xf0be,
+    0x287f, 0xf04a, 0xe41e, 0x1599, 0xf06e, 0x28dc, 0xf04a, 0xa102,
+    0x3cdc, 0xf1ee, 0x28db, 0xf1ca, 0x28da, 0xe000, 0x05ab, 0xe092,
+    0x28da, 0xa002, 0x3cda, 0xa122, 0xf028, 0x3cda, 0x28db, 0xa102,
+    0x3cdb, 0x287f, 0xf0ba, 0x28db, 0xf05a, 0x2901, 0xe41e, 0x18c2,
+    0xf6ae, 0x281e, 0xf03a, 0x28de, 0x3cdc, 0x2901, 0xe42e, 0xe41e,
+    0x117d, 0xf078, 0x286c, 0xf058, 0x287d, 0xf03a, 0xa2fc, 0xe42e,
+    0xa2fe, 0xe42e, 0xa202, 0x5814, 0xaf02, 0x3c06, 0x28a5, 0x2ad7,
+    0xf078, 0xf099, 0x20e6, 0x4ce7, 0x22e8, 0x4ee9, 0xf07e, 0xa200,
+    0xa201, 0xf04e, 0xa200, 0x22ea, 0x4eeb, 0x3400, 0x3c01, 0x3602,
+    0x3e03, 0x2ee3, 0x1202, 0x1e03, 0xf071, 0xe013, 0x1e06, 0xf085,
+    0x0c06, 0x0c06, 0xf05e, 0x1e06, 0xf037, 0x1c06, 0x1c06, 0x3404,
+    0x3c05, 0x0ce3, 0x34c9, 0x3cca, 0x00e4, 0x0ce5, 0x34cb, 0x3ccc,
+    0x28a3, 0xf0ca, 0x20c9, 0x4cca, 0x34ea, 0x3ceb, 0x2004, 0x4c05,
+    0x34e6, 0x3ce7, 0x2ce3, 0x34e8, 0x3ce9, 0xe42e, 0xe41e, 0x156a,
+    0x28eb, 0xf30a, 0x2000, 0x4c01, 0x0c31, 0xf2c6, 0x2aa3, 0xe017,
+    0xe046, 0xa102, 0xf274, 0xe188, 0x000f, 0x7ceb, 0x3402, 0x3c03,
+    0xe41e, 0x1584, 0x28eb, 0xa102, 0xcc44, 0xe161, 0x0250, 0xa200,
+    0xe184, 0x1533, 0x0111, 0x0d11, 0xae02, 0x3404, 0xe008, 0xffff,
+    0xaf02, 0x3c05, 0x8403, 0x8204, 0xe018, 0xae1e, 0x8205, 0xe01c,
+    0xe161, 0x0250, 0x8802, 0x0022, 0xe184, 0x1547, 0x0111, 0x0d11,
+    0xf02e, 0xa200, 0x2aa3, 0xf039, 0x00e7, 0x0ce8, 0x00e3, 0x0ce4,
+    0x34c9, 0x3cca, 0x00e9, 0x0cea, 0x00e5, 0x0ce6, 0x34cb, 0x3ccc,
+    0xe42e, 0xe41e, 0x156a, 0x28a5, 0xe016, 0xf08a, 0x2000, 0x4c01,
+    0x0c31, 0xae02, 0x2aa3, 0xe017, 0xe046, 0x34c9, 0x3cca, 0x34cb,
+    0x3ccc, 0xe42e, 0x28d7, 0xf05a, 0xa200, 0x34e1, 0x3ce2, 0x3ce0,
+    0x28a5, 0xe016, 0xf09a, 0x20e1, 0x4ce2, 0x2ee0, 0x1e31, 0xf047,
+    0xa203, 0x5a11, 0xe042, 0x3400, 0x3c01, 0x2831, 0x3ce0, 0x2000,
+    0x4c01, 0x34e1, 0x3ce2, 0xe42e, 0xe0c0, 0x0041, 0x22f0, 0x4ef1,
+    0xe042, 0xe005, 0x029e, 0xae11, 0xe042, 0xca29, 0xf7f9, 0xce20,
+    0xd111, 0x0250, 0xd112, 0x0200, 0xd113, 0x0003, 0xca28, 0xf7f8,
+    0xe42e, 0x28d8, 0xe426, 0xe41e, 0x159e, 0xf7ce, 0xe161, 0x0578,
+    0xe162, 0x0578, 0x2111, 0x4d11, 0xa201, 0x3e00, 0xa203, 0x28d8,
+    0xa104, 0xf0e4, 0xcc44, 0xe184, 0x15b6, 0x2112, 0x4d0a, 0x1111,
+    0x1d11, 0xf054, 0xe082, 0xa104, 0xe094, 0x3e00, 0xa003, 0xe084,
+    0xa004, 0xe092, 0x2800, 0xe000, 0x059a, 0xe098, 0xa002, 0xe096,
+    0x2904, 0x3c01, 0xe41e, 0x18bb, 0x28d8, 0x1800, 0xa104, 0xf0a4,
+    0xcc44, 0xe184, 0x15d0, 0x2911, 0x3d12, 0x2911, 0x3d12, 0x2913,
+    0x3d14, 0x28d8, 0xa102, 0x3cd8, 0x28d9, 0xe000, 0x05ab, 0xe092,
+    0x2801, 0x3d01, 0x28d9, 0xa002, 0x3cd9, 0xa122, 0xf028, 0x3cd9,
+    0x28db, 0xa002, 0x3cdb, 0xe42e, 0xa200, 0x3c68, 0x28d4, 0xa102,
+    0xcc44, 0xe184, 0x1600, 0xe0c0, 0x0054, 0x5c68, 0xa802, 0xf0b8,
+    0x2868, 0xe049, 0xe001, 0x0518, 0xe09f, 0x2b07, 0xa809, 0xe419,
+    0x18c2, 0xf05e, 0x2868, 0xa209, 0xe41e, 0x18d1, 0x2a68, 0xa003,
+    0x3e68, 0xe42e, 0xe004, 0x0518, 0xe09e, 0xe004, 0x0054, 0xe09c,
+    0x28d4, 0xa102, 0xcc44, 0xa200, 0x3c68, 0xe184, 0x1616, 0x2b17,
+    0xaf05, 0xa803, 0x5a68, 0xe056, 0x2a68, 0xa003, 0x3e68, 0x9f06,
+    0xe42e, 0xe161, 0x05e0, 0xa200, 0x3d11, 0x3c02, 0xd022, 0x011f,
+    0xe184, 0x1626, 0xe41e, 0x16fc, 0x2802, 0xa002, 0x3c02, 0xa200,
+    0x3c94, 0x3c90, 0x3c91, 0xe42e, 0xba4e, 0xba40, 0xba40, 0xba40,
+    0xba40, 0xba46, 0xba4e, 0xbc3e, 0xf0dd, 0x3c00, 0x1810, 0xf038,
+    0xa2fe, 0x3c10, 0x2800, 0xe000, 0x0100, 0xe41e, 0x1686, 0xa202,
+    0xe42e, 0xe16a, 0xa200, 0xe42e, 0xa204, 0x3c94, 0x2810, 0xe000,
+    0x0100, 0xe41e, 0x16ce, 0xe42a, 0xe41e, 0x0ec3, 0xe42a, 0xe41e,
+    0x13f5, 0xa202, 0xe42e, 0xe41e, 0x0791, 0xf0fd, 0x3c01, 0xe002,
+    0x00ff, 0xf0b0, 0x2801, 0x1820, 0xf038, 0xa2fe, 0x3c20, 0x2801,
+    0xe41e, 0x1686, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0xa202,
+    0x3c94, 0x2820, 0xe41e, 0x16ce, 0xe42a, 0xe41e, 0x0fc6, 0x3c66,
+    0xa200, 0xe41e, 0x064a, 0xa201, 0x3e94, 0x2866, 0xe42a, 0xa202,
+    0xe42e, 0x2835, 0xa102, 0xf06a, 0x2092, 0x4c93, 0xe41e, 0x1728,
+    0xe470, 0x2080, 0x4c81, 0xe41e, 0x1737, 0xe470, 0x3c02, 0xe41e,
+    0x16fe, 0xa200, 0x3c03, 0xe161, 0x05e0, 0x2901, 0xa203, 0x3f11,
+    0xf0ca, 0x28a7, 0x1901, 0xf090, 0x8111, 0x2111, 0x4d11, 0x3404,
+    0x3c05, 0xa202, 0x3c03, 0xf08e, 0x2090, 0x4c91, 0x3404, 0x3c05,
+    0x8111, 0x3511, 0x3d11, 0xe41e, 0x171b, 0xca29, 0xf7f9, 0xce20,
+    0xd111, 0x0000, 0x28a7, 0xa00e, 0xaf06, 0xae02, 0xce24, 0xd113,
+    0x0012, 0xca28, 0xf7f8, 0x28a6, 0xf0a8, 0xe41e, 0x0544, 0x2004,
+    0x4c05, 0xe000, 0x0200, 0x3404, 0x3c05, 0xf66e, 0xe161, 0x05e1,
+    0x28a7, 0x3d01, 0x2a03, 0xf089, 0xa00e, 0xaf06, 0xae06, 0x0090,
+    0x0c91, 0x3490, 0x3c91, 0xe41e, 0x16fc, 0xe42e, 0x3c02, 0xe41e,
+    0x16fe, 0xe161, 0x05e0, 0x2911, 0xe42a, 0x8111, 0x2111, 0x4d11,
+    0x3404, 0x3c05, 0x2894, 0xa102, 0xf0ba, 0xe41e, 0x171b, 0xe41e,
+    0x1728, 0xa204, 0xe41e, 0x064a, 0xe004, 0x0090, 0xf0ae, 0xe41e,
+    0x171b, 0xe41e, 0x1737, 0xa202, 0xe41e, 0x064a, 0xe004, 0x0080,
+    0xcc66, 0xcc6a, 0xcc6e, 0xa01e, 0xcc6c, 0xa200, 0xcc60, 0xcc68,
+    0xcc70, 0xe128, 0xa202, 0xe42e, 0xa204, 0xf02e, 0xa206, 0x3c0a,
+    0xe41e, 0x170e, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x05e0, 0xd112,
+    0x0004, 0x880a, 0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0041,
+    0x22f0, 0x4ef1, 0xe042, 0xe005, 0x02a2, 0xae11, 0xe042, 0x2a02,
+    0xae07, 0xe042, 0xe42e, 0xe0c0, 0x0041, 0x22f0, 0x4ef1, 0xe042,
+    0xe005, 0x02ae, 0xae11, 0xe042, 0x2204, 0x4e05, 0xe042, 0xe42e,
+    0xca29, 0xf7f9, 0xce20, 0xa080, 0x3492, 0x3c93, 0xd111, 0x0090,
+    0xd112, 0x0010, 0xd113, 0x0013, 0xca28, 0xf7f8, 0xe42e, 0xca29,
+    0xf7f9, 0xce20, 0xa080, 0x3480, 0x3c81, 0xd111, 0x0080, 0xd112,
+    0x0010, 0xd113, 0x0013, 0xca28, 0xf7f8, 0xe42e, 0x2816, 0xe42a,
+    0xa102, 0x3c00, 0x28a3, 0xe01a, 0x4417, 0xe418, 0x17fb, 0xe41e,
+    0x180c, 0xe41e, 0x182a, 0xe42e, 0x28d3, 0xf10a, 0x20c9, 0x4cca,
+    0x10c7, 0x1cc8, 0x34c9, 0x3cca, 0x20cb, 0x4ccc, 0x10c7, 0x1cc8,
+    0x34cb, 0x3ccc, 0xa200, 0x34c7, 0x3cc8, 0x2c31, 0x2aa5, 0x4ed3,
+    0xb612, 0x3cd5, 0x2816, 0xe42a, 0xa102, 0x3c00, 0x2831, 0x3c01,
+    0x28d2, 0xe418, 0x17a8, 0x28d2, 0xe41a, 0x17d6, 0xe41e, 0x1779,
+    0xe42e, 0xc420, 0xe161, 0x0102, 0x8800, 0x0022, 0xe184, 0x1782,
+    0x2901, 0xf03a, 0x8131, 0xe42e, 0xe082, 0xe002, 0x0102, 0xaf04,
+    0x3c0a, 0xa206, 0x3d09, 0x28d1, 0x3d09, 0x28d0, 0x3d31, 0x8109,
+    0x28c1, 0x3d11, 0xe42e, 0xc420, 0xe161, 0x0102, 0x8800, 0x0022,
+    0xe184, 0x179c, 0x2901, 0xf03a, 0x8131, 0xe42e, 0xa206, 0x3d09,
+    0xa202, 0x3d09, 0x2801, 0x3d31, 0x8109, 0xa2fe, 0x3d11, 0xe42e,
+    0xa200, 0xc420, 0xe161, 0x0102, 0x8800, 0x0022, 0xe184, 0x17b2,
+    0x2b31, 0xe01b, 0xe042, 0x1816, 0xe424, 0xa203, 0xae21, 0xe161,
+    0x0102, 0x8800, 0x0022, 0xe184, 0x17cf, 0x2909, 0xf10a, 0x2909,
+    0xf0d6, 0x2901, 0x1c01, 0xf026, 0x1c12, 0x0c01, 0xe046, 0xf062,
+    0xe042, 0xe049, 0xe082, 0xa004, 0xe094, 0x8111, 0x8111, 0x8131,
+    0xa200, 0x3d12, 0x2912, 0xe412, 0x18b4, 0xe42e, 0xe161, 0x0100,
+    0xe162, 0x01f0, 0x8800, 0x0022, 0xe184, 0x17f9, 0x2912, 0x3c02,
+    0x2912, 0x3c03, 0xe01a, 0xb670, 0x3c04, 0x2804, 0x8112, 0x8112,
+    0xf08a, 0x2802, 0x3d11, 0x2803, 0x3d11, 0x2804, 0x3d11, 0xf0ae,
+    0x8111, 0x8111, 0x2901, 0xa201, 0x3f11, 0xf04a, 0x2901, 0xe412,
+    0x18b4, 0x8111, 0xe42e, 0x28a5, 0xe428, 0x2cd5, 0x3c01, 0x2801,
+    0xa002, 0xc70f, 0x7c12, 0xaf20, 0x3c01, 0x1c31, 0xe42a, 0xe41e,
+    0x17a8, 0xe41e, 0x1793, 0xf74e, 0xe161, 0x0100, 0xe162, 0x01f0,
+    0x8800, 0x0022, 0xe184, 0x181e, 0x2911, 0x3d12, 0x2911, 0x2b11,
+    0xa807, 0xb616, 0x3d12, 0xa200, 0x3d12, 0x3d12, 0x8111, 0xe161,
+    0x0230, 0xe162, 0x01f0, 0xd022, 0x003f, 0xe184, 0x1828, 0x2912,
+    0x3d11, 0xe42e, 0xe41e, 0x1836, 0x2808, 0xe000, 0x0270, 0xe096,
+    0xe41e, 0x1876, 0x2808, 0x0809, 0x3cc0, 0xe42e, 0xe161, 0x05e0,
+    0xa200, 0xc70f, 0x3d11, 0xa206, 0x3c05, 0xa200, 0x3c08, 0xc420,
+    0xe163, 0x0270, 0xa2fe, 0x3c06, 0xa203, 0xae21, 0xe013, 0xe161,
+    0x0102, 0xe162, 0x05e0, 0x8800, 0x0022, 0xe184, 0x1865, 0x2912,
+    0xf158, 0x2909, 0x1805, 0xf114, 0x2909, 0xf0e6, 0x2901, 0x1c31,
+    0xf026, 0x1c12, 0x0c31, 0xe046, 0xf076, 0xe042, 0xe049, 0xe084,
+    0xe002, 0x05e1, 0x3c06, 0x8111, 0x8111, 0x8131, 0x2806, 0xe424,
+    0xe000, 0x05e0, 0xe094, 0xa202, 0x3d02, 0x2806, 0xae02, 0x3d13,
+    0x2808, 0xa002, 0x3c08, 0x1816, 0xf4e8, 0xe42e, 0xe161, 0x05e0,
+    0xa200, 0xc70f, 0x3d11, 0xa206, 0x3c05, 0xa200, 0x3c09, 0xc420,
+    0xa2fe, 0x3c07, 0xa221, 0xe161, 0x0102, 0xe162, 0x05e0, 0x8800,
+    0x0022, 0xe184, 0x189d, 0x2912, 0xf118, 0x2909, 0x1805, 0xf0d4,
+    0x2909, 0xf0a2, 0x2901, 0xe046, 0xf072, 0xe042, 0xe049, 0xe084,
+    0xe002, 0x05e1, 0x3c07, 0x8111, 0x8111, 0x8131, 0x2807, 0xe424,
+    0xe000, 0x05e0, 0xe094, 0xa202, 0x3d02, 0x2807, 0xae02, 0x3d13,
+    0x2809, 0xa002, 0x3c09, 0x1816, 0xf548, 0xe42e, 0xe161, 0x0518,
+    0xa200, 0xc713, 0x3d11, 0xe42e, 0xe000, 0x0518, 0xe09e, 0x2907,
+    0xa80c, 0x3d07, 0xe42e, 0xe000, 0x0518, 0xe09e, 0x2907, 0xa80a,
+    0x3d07, 0xe42e, 0x3cd6, 0xe000, 0x0518, 0xe09e, 0x2907, 0xa806,
+    0x3d07, 0x28d6, 0xa002, 0x3cd6, 0x18d4, 0xf038, 0xa200, 0x3cd6,
+    0xe42e, 0xe000, 0x0518, 0xe09e, 0x2907, 0xe056, 0x3d07, 0xe42e,
+    0xe161, 0x0518, 0x28d4, 0xa102, 0xcc44, 0xa200, 0xe184, 0x18e3,
+    0x2b11, 0xa807, 0xe01b, 0xe042, 0x18df, 0xa102, 0xe01a, 0xe42e,
+    0xe161, 0x0518, 0x28d4, 0xa102, 0xcc44, 0xe184, 0x18f2, 0x2911,
+    0xe016, 0xf038, 0xe190, 0xe42e, 0xe42e, 0x28d6, 0x3c00, 0x2800,
+    0xe000, 0x0518, 0xe092, 0x2901, 0xf12a, 0x2800, 0xa002, 0x3c00,
+    0x18d4, 0xf038, 0xa200, 0x3c00, 0x2800, 0x18d6, 0xf718, 0xa200,
+    0x3cd6, 0xa2fe, 0x3cc1, 0xe0c2, 0x0077, 0xe42e, 0xa20e, 0x3d01,
+    0x2800, 0x3cc1, 0xe0c2, 0x0077, 0xe42e, 0xe0c0, 0x0060, 0xe049,
+    0xa861, 0xe42b, 0xe0c1, 0x0044, 0xae1b, 0xe0c3, 0x0102, 0xe049,
+    0xa83e, 0x3caf, 0xaf0b, 0x3eae, 0x2848, 0xae04, 0x0848, 0x0848,
+    0xe000, 0x0620, 0xe09e, 0x2117, 0x4d17, 0xe0c2, 0x0143, 0x2117,
+    0x4d17, 0xe0c2, 0x0144, 0x2117, 0x4d17, 0xe0c2, 0x0145, 0xa200,
+    0xe0c2, 0x0140, 0xe0c2, 0x0149, 0x2867, 0xe0c2, 0x0141, 0xe0c0,
+    0x0064, 0xe0c2, 0x014c, 0x2850, 0xa102, 0xae20, 0x4c51, 0xa102,
+    0xe0c2, 0x0142, 0x28ae, 0xae08, 0x2aaf, 0xa81f, 0xe056, 0xe0c2,
+    0x014e, 0xe0c0, 0x0061, 0xe0c2, 0x0146, 0xe0c0, 0x0062, 0xe0c2,
+    0x0147, 0xe0c0, 0x0063, 0xe0c2, 0x0148, 0xa200, 0x3cad, 0xe41e,
+    0x1973, 0xe41e, 0x198a, 0x28ad, 0xa8fe, 0x1851, 0xf798, 0xa204,
+    0xae1c, 0xe0c2, 0x014d, 0xa202, 0xe0c2, 0x014a, 0xe190, 0xe0c1,
+    0x014b, 0xf7e9, 0xe42e, 0xa205, 0x28ad, 0xb615, 0xa903, 0x3e0d,
+    0x2848, 0xe000, 0x0700, 0xe092, 0x2901, 0xae04, 0x4c0d, 0xae1c,
+    0x4cad, 0xe0c2, 0x014d, 0xa202, 0xe0c2, 0x014a, 0xe0c1, 0x014b,
+    0xf7e9, 0xe42e, 0x28ad, 0xe000, 0x0080, 0x3cad, 0xaf0e, 0x1850,
+    0xe428, 0x28ad, 0xa8fe, 0xa002, 0x3cad, 0xe42e, 0xe41e, 0x1a71,
+    0xe41e, 0x19c2, 0xe41e, 0x1b28, 0xe41e, 0x0910, 0x285c, 0x4ca3,
+    0xe01a, 0x3c5c, 0x2823, 0xf04a, 0xe41e, 0x0b7e, 0xf19e, 0xa200,
+    0x3c52, 0x2852, 0x183c, 0xf142, 0x2852, 0xa201, 0xe41e, 0x0a44,
+    0x284a, 0x1852, 0xf774, 0xf06a, 0xe41e, 0x1aa4, 0x284a, 0x183c,
+    0xf072, 0xe41e, 0x1a01, 0xf6ea, 0xe41e, 0x1a83, 0xf6be, 0xe41e,
+    0x1c91, 0xe42e, 0xa202, 0xae0c, 0x2a29, 0xa83f, 0xe056, 0xae0a,
+    0x2a29, 0xa83f, 0xe056, 0xae06, 0xcf80, 0xa200, 0xae02, 0xa902,
+    0xae04, 0xcfc2, 0x2823, 0xe01a, 0xae0e, 0x4c50, 0xa102, 0xae02,
+    0x4c2b, 0xae06, 0xcf00, 0xd1d3, 0x000b, 0xd185, 0x0001, 0xc420,
+    0xe161, 0x0101, 0xa200, 0xd022, 0x000f, 0xe184, 0x19e9, 0x2b31,
+    0xae02, 0xb42a, 0xcfe8, 0x20c7, 0x4cc8, 0xcfea, 0x20c9, 0x4cca,
+    0xcfec, 0x20cb, 0x4ccc, 0xcfee, 0xe004, 0x0060, 0xce30, 0xe161,
+    0x0160, 0xd022, 0x001f, 0xe184, 0x19ff, 0x2111, 0x4d11, 0xce32,
+    0xe42e, 0xe0c4, 0x3fff, 0xbc12, 0xa10a, 0xb4a8, 0xa104, 0xb7b4,
+    0xa006, 0x3c30, 0xbdfe, 0x7411, 0x28a5, 0xf03a, 0xe0c4, 0xffff,
+    0x2813, 0xa102, 0xf034, 0xf07a, 0xf0de, 0x7414, 0x2822, 0xe418,
+    0x07ab, 0xf08e, 0x2815, 0xf068, 0xe41e, 0x07ab, 0x2822, 0xe418,
+    0x07ab, 0x282c, 0xe418, 0x0791, 0x2824, 0x3c40, 0x2830, 0xf05a,
+    0xba40, 0xf03a, 0xbc3e, 0x3c40, 0x2830, 0xe016, 0xe41a, 0x0919,
+    0xe40a, 0x1a6e, 0x28a3, 0xf1aa, 0x28a5, 0xf04a, 0xba40, 0xba40,
+    0xf15e, 0xba40, 0xf13a, 0xbc0c, 0xe40d, 0x1a6e, 0xf0fa, 0xa106,
+    0xf07a, 0xa104, 0xf79a, 0xe41e, 0x0791, 0xf29d, 0xf75e, 0xe41e,
+    0x0791, 0xf25d, 0xbc40, 0xf23d, 0xf6fe, 0xe0c6, 0x0033, 0xf1fd,
+    0x0828, 0xa400, 0xa566, 0x3c42, 0xa200, 0x3c43, 0x3c44, 0x3c45,
+    0x282a, 0xf10a, 0xbc04, 0xf13d, 0x3c43, 0xa102, 0xf0ba, 0xbe0c,
+    0xf0ed, 0xae02, 0xa83e, 0x3c44, 0xbe0c, 0xf09d, 0xae02, 0xa83e,
+    0x3c45, 0x2823, 0xf02a, 0x74b8, 0xa202, 0xe42e, 0xe16a, 0xa200,
+    0xe42e, 0xa202, 0xe0c2, 0x013c, 0xa200, 0xa221, 0xd022, 0x00df,
+    0xe184, 0x1a7e, 0xe0c2, 0x013e, 0xe0c3, 0x013f, 0xa002, 0xa200,
+    0xe0c2, 0x013c, 0xe42e, 0xa200, 0x3ca2, 0x28a6, 0xf048, 0xa202,
+    0x3ca0, 0x3ca2, 0xe16a, 0x284a, 0x3c52, 0xe41e, 0x1ab3, 0x2852,
+    0x183c, 0xf092, 0xe41e, 0x1ac8, 0xf09d, 0xcb86, 0xa102, 0xf780,
+    0xc894, 0xf768, 0xe41e, 0x07da, 0xe42e, 0xe41e, 0x1af4, 0x284c,
+    0xa002, 0x3c4c, 0xe16a, 0xe42e, 0x28a5, 0xe016, 0x3c30, 0xe41e,
+    0x1ab3, 0x2852, 0x184a, 0xf072, 0xe41e, 0x1af4, 0x284c, 0xa002,
+    0x3c4c, 0xf78e, 0xe42e, 0x2843, 0xae0a, 0x4c44, 0xae0a, 0x4c45,
+    0xcf30, 0x2840, 0xae04, 0x4c30, 0xcf82, 0xd1c3, 0x0000, 0x2842,
+    0xcf96, 0x2840, 0xae0c, 0x4c30, 0xcfc4, 0xd188, 0x0001, 0xe42e,
+    0x2852, 0xe0c2, 0x003f, 0xd185, 0x0002, 0xd1d0, 0x003f, 0xcba0,
+    0xa810, 0xcba3, 0xf189, 0xf7c8, 0xe41e, 0x1c31, 0xe41e, 0x198a,
+    0xcbe0, 0xf7f8, 0x2856, 0xe41a, 0x1c73, 0xcba0, 0xcba3, 0xf0b9,
+    0xf7d8, 0xd186, 0x0001, 0xd185, 0x0004, 0xe41e, 0x1c83, 0xcb06,
+    0x3c52, 0xe42e, 0xd1d0, 0x0000, 0xd1d1, 0x0000, 0xcb1c, 0xf7f8,
+    0xcbe0, 0xf7f8, 0xe16b, 0xe42e, 0x2852, 0xe0c2, 0x003f, 0xd185,
+    0x0002, 0xd186, 0x0000, 0xd1c2, 0x0001, 0xd1c5, 0x0000, 0xd1c4,
+    0x0000, 0xd1d0, 0x000e, 0xcba0, 0xf7f8, 0x284b, 0xf098, 0xd1c2,
+    0x0000, 0xd1c5, 0x0003, 0xd1c4, 0x0003, 0xd1c8, 0x0000, 0xd1d0,
+    0x0020, 0xe41e, 0x1c31, 0xe41e, 0x198a, 0xa200, 0xe0c2, 0x012a,
+    0xcbe0, 0xf7f8, 0x2856, 0xe41a, 0x1c73, 0xcba0, 0xf7f8, 0xd186,
+    0x0001, 0xd185, 0x0004, 0xe41e, 0x1c83, 0xcb06, 0x3c52, 0xe42e,
+    0xa200, 0xe0c2, 0x0100, 0xe0c2, 0x013d, 0xcc8e, 0xe004, 0x00ce,
+    0xe0c2, 0x017c, 0xa218, 0xe0c2, 0x017d, 0xe0c0, 0x0050, 0x3008,
+    0xaf02, 0x3009, 0xaf02, 0x300a, 0xaf02, 0x300b, 0xaf0a, 0x300c,
+    0xaf02, 0x300d, 0xaf02, 0x300e, 0xaf02, 0x300f, 0xaf06, 0xa802,
+    0xe005, 0x0ba6, 0xe09f, 0x3d17, 0x280c, 0x4408, 0x3c08, 0x280d,
+    0x4409, 0x3c09, 0x280e, 0x440a, 0x3c0a, 0x280f, 0x440b, 0x3c0b,
+    0xa200, 0xe0c2, 0x0168, 0x2a08, 0xf02b, 0xa904, 0x2a09, 0xf02b,
+    0xa912, 0x2a0a, 0xf02b, 0xa940, 0x2a0b, 0xf02b, 0xa980, 0xe005,
+    0x0ba6, 0xe09f, 0x2b17, 0xae05, 0xe056, 0xe0c2, 0x0169, 0xe0c1,
+    0x0041, 0xe004, 0x000c, 0xae10, 0xe042, 0x2a0c, 0xf06b, 0xe004,
+    0x05d2, 0xe09e, 0x2117, 0x4d17, 0xcf0e, 0xe0c1, 0x0041, 0xe004,
+    0x004c, 0xae10, 0xe042, 0x2a0d, 0xf06b, 0xe004, 0x05d4, 0xe09e,
+    0x2117, 0x4d17, 0xe0c2, 0x0103, 0xa202, 0xe0c2, 0x0210, 0xe0c1,
+    0x0041, 0xe004, 0x007c, 0xae10, 0xe042, 0x2a0e, 0xf06b, 0xe004,
+    0x05d6, 0xe09e, 0x2117, 0x4d17, 0xe0c2, 0x0211, 0xe0c1, 0x0041,
+    0xe004, 0x00bc, 0xae10, 0xe042, 0x2a0f, 0xf06b, 0xe004, 0x05d8,
+    0xe09e, 0x2117, 0x4d17, 0xe0c2, 0x0212, 0x2050, 0x4c51, 0xae08,
+    0xe0c2, 0x0101, 0xe0c2, 0x0283, 0xe0c2, 0x006f, 0xe0c2, 0x004f,
+    0x2a1f, 0x2058, 0x4c59, 0xf02b, 0xae02, 0xe0c2, 0x0078, 0x205a,
+    0x4c5b, 0xf02b, 0xae02, 0xe0c2, 0x0079, 0xe0c0, 0x0044, 0xa80e,
+    0xae1a, 0x4c67, 0xe0c2, 0x0102, 0xa200, 0xe0c2, 0x0104, 0xe0c2,
+    0x0208, 0xe0c0, 0x0065, 0xaf18, 0xa802, 0xae16, 0xe0c2, 0x0204,
+    0xa200, 0x3caf, 0x3cae, 0x3cad, 0x2848, 0xe404, 0x1c23, 0xe0c0,
+    0x0060, 0xe049, 0xa861, 0xe40b, 0x1c23, 0xe049, 0xa83e, 0x3caf,
+    0xaf0b, 0x3eae, 0x2848, 0xae04, 0x0848, 0x0848, 0xe000, 0x0620,
+    0xe09e, 0x2117, 0x4d17, 0xe0c2, 0x0143, 0x2117, 0x4d17, 0xe0c2,
+    0x0144, 0x2117, 0x4d17, 0xe0c2, 0x0145, 0xa200, 0xe0c2, 0x0140,
+    0xe0c2, 0x0149, 0x2867, 0xe0c2, 0x0141, 0xe0c0, 0x0064, 0xe0c2,
+    0x014c, 0x2850, 0xa102, 0xae20, 0x4c51, 0xa102, 0xe0c2, 0x0142,
+    0x28ae, 0xae08, 0x2aaf, 0xa81f, 0xe056, 0xe0c2, 0x014e, 0xe0c0,
+    0x0061, 0xe0c2, 0x0146, 0xe0c0, 0x0062, 0xe0c2, 0x0147, 0xe0c0,
+    0x0063, 0xe0c2, 0x0148, 0xe41e, 0x1cae, 0xe41e, 0x1cd1, 0xa202,
+    0xe0c2, 0x0106, 0xa201, 0xe167, 0x0ba7, 0x3f17, 0xe41e, 0x1cf5,
+    0xe42e, 0xa200, 0xe0c2, 0x0113, 0xe0c2, 0x030d, 0xe0c2, 0x022b,
+    0xcb94, 0xe0c2, 0x0115, 0xa87e, 0x22aa, 0x4eab, 0xe042, 0x34aa,
+    0x3cab, 0x28af, 0x4cae, 0xf17a, 0xa203, 0x28ad, 0xb615, 0x3e0d,
+    0xa203, 0x3e0e, 0x2848, 0xe000, 0x0700, 0xe092, 0x2901, 0xae02,
+    0x4c0d, 0xae02, 0x4c0e, 0xae1c, 0x4cad, 0xe0c1, 0x014b, 0xf7e9,
+    0xe0c2, 0x014d, 0xcba4, 0xe0c2, 0x012a, 0xcb8a, 0xe0c2, 0x0114,
+    0xa802, 0x3c56, 0xe42a, 0xcb14, 0xae0a, 0xcb19, 0xe056, 0xe0c2,
+    0x0120, 0xcb8c, 0xe0c2, 0x0121, 0xcb8e, 0xe0c2, 0x0122, 0xcb90,
+    0xe0c2, 0x0123, 0xe42e, 0xcbd0, 0xe0c2, 0x030c, 0xcbd2, 0xe0c2,
+    0x0309, 0xcbd8, 0xe0c2, 0x030a, 0xcbda, 0xe0c2, 0x030b, 0xa200,
+    0xe0c2, 0x0320, 0xe42e, 0xe0c0, 0x0111, 0xf7e8, 0xa202, 0xe0c2,
+    0x0110, 0x28af, 0xaf08, 0x4cae, 0xe42a, 0xa202, 0xe0c2, 0x014a,
+    0xe42e, 0xe0c0, 0x0111, 0xf7e8, 0xe0c0, 0x0065, 0xaf18, 0xa802,
+    0xf04a, 0xe0c0, 0x0281, 0xf7ea, 0x28af, 0x4cae, 0xe42a, 0xe0c0,
+    0x014b, 0xf7e8, 0xa204, 0xae1c, 0xe0c2, 0x014d, 0xa202, 0xe0c2,
+    0x014a, 0xe190, 0xe0c0, 0x014b, 0xf7e8, 0xe42e, 0xa202, 0xe0c2,
+    0x0302, 0x2816, 0xe42a, 0xa102, 0xcc44, 0xe160, 0x0004, 0xe161,
+    0x0103, 0xe163, 0x0380, 0xe184, 0x1ccc, 0x8531, 0xc786, 0xe018,
+    0xb608, 0xe000, 0x0620, 0xe094, 0x2112, 0x4d12, 0x9f13, 0x2112,
+    0x4d12, 0x9f13, 0x2112, 0x4d12, 0x9f13, 0xa200, 0xe0c2, 0x0302,
+    0xe42e, 0xa202, 0xae02, 0xa902, 0xe0c2, 0x0312, 0xa802, 0xe42a,
+    0xe162, 0x01b0, 0x2912, 0xaf02, 0x3c0a, 0x2912, 0xaf02, 0x3c0b,
+    0x280a, 0x180b, 0xf0d8, 0xe162, 0x01b0, 0xd022, 0x001f, 0xe184,
+    0x1cee, 0x2912, 0xaf02, 0x3c0b, 0x180a, 0xf028, 0xe190, 0x280b,
+    0xae08, 0x4c0a, 0xe0c2, 0x0313, 0xe42e, 0xe0c0, 0x0065, 0xaf18,
+    0xa802, 0xe40a, 0x1d77, 0xae0a, 0xe0c1, 0x0060, 0xaf0d, 0xa80f,
+    0xe056, 0xe0c1, 0x0044, 0xa811, 0xe056, 0xae0c, 0xe0c1, 0x0044,
+    0xa80f, 0xe056, 0xe167, 0x0ba7, 0x2f17, 0xe056, 0xe0c2, 0x0282,
+    0xe0c0, 0x006e, 0xe0c2, 0x0284, 0xaf20, 0xe0c1, 0x0282, 0xa809,
+    0xf04b, 0xe049, 0xae1f, 0xf06e, 0xe049, 0xa011, 0xaf09, 0xae07,
+    0xae21, 0xe056, 0xe0c2, 0x028c, 0xe167, 0x0ba8, 0x2d17, 0x4917,
+    0xe0c2, 0x0285, 0xe167, 0x0baa, 0x2d17, 0x4917, 0xe0c2, 0x0286,
+    0xe41e, 0x1d78, 0xe0c0, 0x004a, 0xe0c2, 0x0289, 0xe0c0, 0x004b,
+    0xe0c2, 0x028a, 0xe0c0, 0x0055, 0xe0c2, 0x028b, 0xe0c1, 0x0041,
+    0xe004, 0x033c, 0xae10, 0xe042, 0xe167, 0x0ba6, 0x2b17, 0xf05b,
+    0xe167, 0x0ba0, 0x2d17, 0x4917, 0xe0c2, 0x0287, 0xe0c1, 0x0041,
+    0xe004, 0x0354, 0xae10, 0xe042, 0xe167, 0x0ba6, 0x2b17, 0xf05b,
+    0xe167, 0x0ba2, 0x2d17, 0x4917, 0xe0c2, 0x0288, 0xe0c1, 0x0041,
+    0xe004, 0x035c, 0xae10, 0xe042, 0xe167, 0x0ba6, 0x2b17, 0xf05b,
+    0xe167, 0x0ba4, 0x2d17, 0x4917, 0xe0c2, 0x028d, 0xe0c0, 0x0065,
+    0xaf18, 0xa802, 0xe0c2, 0x0280, 0xa210, 0xe0c2, 0x0168, 0xe42e,
+    0xe167, 0x0bac, 0xe165, 0x028e, 0xe166, 0x02c0, 0xd022, 0x0008,
+    0xe184, 0x1d8b, 0x2d17, 0x9f16, 0x9e85, 0xf7fb, 0x2517, 0x4d17,
+    0x9f16, 0x9e85, 0xf7fb, 0xe190, 0xe166, 0x02d2, 0xd022, 0x0008,
+    0xe184, 0x1d97, 0x2517, 0x4d17, 0x9f16, 0x9e85, 0xf7fb, 0xe190,
+    0xe166, 0x02db, 0xd022, 0x0008, 0xe184, 0x1da3, 0x2517, 0x4d17,
+    0x9f16, 0x9e85, 0xf7fb, 0xe190, 0xe166, 0x02e4, 0xd022, 0x0008,
+    0xe184, 0x1dae, 0x2d17, 0x9f16, 0x9e85, 0xf7fb, 0xe190, 0xe42e,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010,
+    0x060d, 0x0d14, 0x1414, 0x1c1c, 0x1c1c, 0x2020, 0x2025, 0x252a,
+    0x0a0e, 0x0e14, 0x1414, 0x1818, 0x1818, 0x1b1b, 0x1b1e, 0x1e22,
+    0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010,
+    0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010,
+    0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010,
+    0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010,
+    0x060a, 0x0a0d, 0x0b0d, 0x1010, 0x1010, 0x1212, 0x1212, 0x1217,
+    0x1717, 0x1717, 0x1719, 0x1919, 0x1919, 0x1919, 0x1b1b, 0x1b1b,
+    0x1b1b, 0x1b1b, 0x1d1d, 0x1d1d, 0x1d1d, 0x1d1f, 0x1f1f, 0x1f1f,
+    0x1f21, 0x2121, 0x2121, 0x2424, 0x2424, 0x2626, 0x2628, 0x282a,
+    0x090d, 0x0d0f, 0x0d0f, 0x1111, 0x1111, 0x1313, 0x1313, 0x1315,
+    0x1515, 0x1515, 0x1516, 0x1616, 0x1616, 0x1616, 0x1818, 0x1818,
+    0x1818, 0x1818, 0x1919, 0x1919, 0x1919, 0x191b, 0x1b1b, 0x1b1b,
+    0x1b1c, 0x1c1c, 0x1c1c, 0x1e1e, 0x1e1e, 0x2020, 0x2021, 0x2123,
+    0x0000, 0x0001, 0x0004, 0x0008, 0x0005, 0x0002, 0x0003, 0x0006,
+    0x0009, 0x000c, 0x000d, 0x000a, 0x0007, 0x000b, 0x000e, 0x000f,
+    0x0000, 0x0001, 0x0008, 0x0010, 0x0009, 0x0002, 0x0003, 0x000a,
+    0x0011, 0x0018, 0x0020, 0x0019, 0x0012, 0x000b, 0x0004, 0x0005,
+    0x000c, 0x0013, 0x001a, 0x0021, 0x0028, 0x0030, 0x0029, 0x0022,
+    0x001b, 0x0014, 0x000d, 0x0006, 0x0007, 0x000e, 0x0015, 0x001c,
+    0x0023, 0x002a, 0x0031, 0x0038, 0x0039, 0x0032, 0x002b, 0x0024,
+    0x001d, 0x0016, 0x000f, 0x0017, 0x001e, 0x0025, 0x002c, 0x0033,
+    0x003a, 0x003b, 0x0034, 0x002d, 0x0026, 0x001f, 0x0027, 0x002e,
+    0x0035, 0x003c, 0x003d, 0x0036, 0x002f, 0x0037, 0x003e, 0x003f,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0xe40e, 0x0020, 0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x0131,
+    0xe470, 0xe190, 0xe40e, 0x0113, 0xe470, 0xe190, 0xe470, 0xe190,
+    0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+    0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x012f, 0xe40e, 0x0131,
+    0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058,
+    0xa200, 0xe0c2, 0x005a, 0x3cf0, 0x3cf1, 0xa2fe, 0x3cee, 0x3cef,
+    0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d, 0xce00, 0xf11e, 0xe0c0,
+    0x005c, 0xe0c1, 0x0059, 0x3eed, 0xa203, 0x5aed, 0xe052, 0xf08a,
+    0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00, 0xe41e,
+    0x008c, 0xe41e, 0x00ab, 0xe0c0, 0x005a, 0x18ee, 0xe0c1, 0x0059,
+    0xa115, 0xb636, 0x2aee, 0xb60a, 0xe418, 0x00fb, 0xe0c0, 0x005b,
+    0xe0c1, 0x005e, 0xae11, 0xe056, 0x18ef, 0xe0c1, 0x0059, 0xa117,
+    0xb636, 0xe418, 0x00b0, 0xe0c0, 0x005a, 0x18ee, 0x2aee, 0xb60a,
+    0xe0c1, 0x0059, 0xa117, 0xb636, 0xe418, 0x00f3, 0xd071, 0x802a,
+    0xe181, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100, 0xe0c0, 0x0059,
+    0xae02, 0xe000, 0x0113, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a,
+    0x3cee, 0xe41e, 0x0100, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11,
+    0xe056, 0x3cef, 0xe40e, 0x0037, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+    0x0058, 0xe0c2, 0x0008, 0xe0c0, 0x0059, 0xf7ea, 0xa11e, 0xf0e8,
+    0xa202, 0xe0c2, 0x0058, 0xe004, 0x093d, 0xe0c2, 0x0070, 0xa200,
+    0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xf6fe, 0xa202, 0xe0c2, 0x0008,
+    0xe0c2, 0x0058, 0xe42e, 0xd101, 0x0001, 0xc70f, 0xa000, 0xe42e,
+    0xa200, 0xe0c1, 0x005b, 0xf27b, 0xa220, 0xa103, 0xf2eb, 0xa230,
+    0xa103, 0xf2bb, 0xa23c, 0xa103, 0xf24b, 0xa258, 0xa103, 0xf25b,
+    0xa260, 0xa103, 0xf22b, 0xa200, 0xa103, 0xf1fb, 0xa26c, 0xa103,
+    0xf1cb, 0xe004, 0x003e, 0xa103, 0xf18b, 0xe004, 0x0044, 0xa105,
+    0xf14b, 0xe004, 0x0046, 0xa103, 0xf10b, 0xe004, 0x0000, 0xa107,
+    0xf0cb, 0xa200, 0xe0c1, 0x005e, 0xf08b, 0xe004, 0x004c, 0xf05e,
+    0xe0c1, 0x005e, 0xf02b, 0xa010, 0xae16, 0xe0c1, 0x0040, 0xe041,
+    0xca28, 0xf7f8, 0xce21, 0xd111, 0x0000, 0xd112, 0x2000, 0xd113,
+    0x000b, 0xe1e1, 0xe42e, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100,
+    0xe004, 0x0133, 0xe67c, 0xe41e, 0x0100, 0xe004, 0x0135, 0xe67c,
+    0x28ee, 0xe008, 0x03ff, 0xcca4, 0xe182, 0x0029, 0xe018, 0x2eee,
+    0xaf15, 0xcca5, 0xe182, 0x0029, 0xe019, 0xae15, 0xe042, 0xae14,
+    0x34f0, 0x3cf1, 0xe42e, 0xe40e, 0x059a, 0xe40e, 0x0137, 0xe40e,
+    0x013b, 0xe40e, 0x013f, 0xe40e, 0x0143, 0xe40e, 0x007e, 0xe40e,
+    0x0147, 0xe40e, 0x007e, 0xe40e, 0x014b, 0xe40e, 0x007e, 0xe40e,
+    0x007e, 0xe40e, 0x007e, 0xe40e, 0x007e, 0xe40e, 0x007e, 0xe40e,
+    0x007e, 0xe40e, 0x007e, 0xe40e, 0x0316, 0xe40e, 0x0332, 0xe41e,
+    0x014f, 0xe40e, 0x007e, 0xe41e, 0x015a, 0xe40e, 0x007e, 0xe41e,
+    0x01ab, 0xe40e, 0x007e, 0xe41e, 0x015c, 0xe40e, 0x007e, 0xe41e,
+    0x0429, 0xe40e, 0x007e, 0xe41e, 0x018b, 0xe40e, 0x007e, 0xe41e,
+    0x01c1, 0xe41e, 0x0216, 0xe41e, 0x072b, 0xe41e, 0x0afa, 0xe41e,
+    0x01e6, 0xe42e, 0xa202, 0xe42e, 0xd130, 0x0001, 0xe41e, 0x0404,
+    0xca29, 0xf7f9, 0xe0c0, 0x0060, 0xe42a, 0xe0c0, 0x0042, 0xce20,
+    0xd111, 0x0700, 0xd112, 0x00c4, 0xd113, 0x0003, 0xca28, 0xf7f8,
+    0xe0c0, 0x0042, 0xe000, 0x1000, 0xce20, 0xd111, 0x0ba8, 0xd112,
+    0x004c, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe0c0, 0x0060, 0x3c98,
+    0xe0c0, 0x0061, 0x3cb4, 0xe41e, 0x0b35, 0xe41e, 0x0dea, 0xa200,
+    0xe0c2, 0x0054, 0xe42e, 0xe0c0, 0x0060, 0xf08a, 0xe0c0, 0x0061,
+    0x22b9, 0x4eba, 0xe046, 0xaf12, 0xae02, 0x3cbc, 0xa200, 0x3cc8,
+    0x3cc9, 0x3cca, 0x3ccb, 0x3ccc, 0xcc92, 0xcc8e, 0xa202, 0x3cde,
+    0xe41e, 0x054b, 0xe41e, 0x0b35, 0xe161, 0x07c5, 0xe0c0, 0x0054,
+    0x3511, 0x3d01, 0xe42e, 0xe41e, 0x022b, 0x28cd, 0xe418, 0x052b,
+    0x28cd, 0xe016, 0x44de, 0xe418, 0x0573, 0xa200, 0x3cde, 0xe41e,
+    0x0786, 0xe41e, 0x05b4, 0x28d6, 0xa104, 0xf7aa, 0xe41e, 0x029c,
+    0xe42e, 0xd130, 0x0001, 0xd03a, 0x0001, 0xd008, 0x0000, 0xd039,
+    0x0000, 0xd049, 0x0000, 0xd047, 0x0000, 0xa200, 0xe0c2, 0x0168,
+    0x22f0, 0x4ef1, 0xa200, 0xc401, 0xe188, 0x07ff, 0x3d11, 0x36f0,
+    0x3ef1, 0xe0c0, 0x0062, 0xaf02, 0x3089, 0xaf02, 0x30cd, 0xaf02,
+    0x30ce, 0xaf02, 0x3096, 0xaf02, 0x308a, 0xe42e, 0xd049, 0x0000,
+    0xd047, 0x0000, 0x2016, 0x4c17, 0xe0c2, 0x0071, 0xe0c2, 0x004f,
+    0x2822, 0xa102, 0xb608, 0xae20, 0x4c21, 0xe0c2, 0x0072, 0x2897,
+    0xe0c2, 0x0073, 0x2899, 0xe0c2, 0x0074, 0x2a19, 0xe017, 0x281c,
+    0xae02, 0x4c18, 0xae02, 0xe056, 0xae10, 0x4c11, 0xae10, 0x4c10,
+    0xe0c2, 0x007b, 0x281f, 0xae10, 0x4c20, 0xe0c2, 0x006c, 0xe41e,
+    0x04f1, 0x2893, 0xe016, 0xe0c2, 0x0070, 0xe42e, 0xe0c0, 0x0040,
+    0xa221, 0xae17, 0xe042, 0xe005, 0x1f00, 0xae03, 0xe042, 0xca29,
+    0xf7f9, 0xce20, 0xd111, 0x05f0, 0xd112, 0x0100, 0xd113, 0x0003,
+    0xca28, 0xf7f8, 0xe42e, 0xa200, 0xcc4a, 0xcc4c, 0xd130, 0x0001,
+    0xd03a, 0x0001, 0xd008, 0x0000, 0xd049, 0x0000, 0xd047, 0x0000,
+    0xa200, 0xe0c2, 0x0168, 0xe0c0, 0x0050, 0xe049, 0xe008, 0x001f,
+    0x3cb7, 0xaf11, 0xe009, 0x001f, 0x3eb8, 0x46b7, 0x3eb7, 0xe0c0,
+    0x0050, 0xaf1c, 0xa802, 0xe005, 0x0ba6, 0xe09f, 0x3d17, 0xa200,
+    0x2ab7, 0xa803, 0xf03b, 0xe00a, 0x0002, 0x2ab7, 0xa805, 0xf03b,
+    0xe00a, 0x0009, 0x2ab7, 0xa809, 0xf03b, 0xe00a, 0x0020, 0x2ab7,
+    0xa811, 0xf03b, 0xe00a, 0x0040, 0x2ab7, 0xa821, 0xf03b, 0xe00a,
+    0x0010, 0xe005, 0x0ba6, 0xe09f, 0x2b17, 0xae05, 0xe056, 0xe0c2,
+    0x0169, 0xa200, 0x3ca4, 0x3ca5, 0x3ca6, 0xe0c0, 0x0060, 0xe049,
+    0xa81f, 0x3ea6, 0xaf08, 0x30a5, 0xaf02, 0x30a4, 0xe0c0, 0x0066,
+    0x3cd4, 0xe0c0, 0x0065, 0xaf04, 0xa80e, 0x3cd5, 0xa200, 0x3cd6,
+    0xe41e, 0x0308, 0xa200, 0x3cd7, 0x3cd8, 0x3cd9, 0x3cda, 0xe41e,
+    0x19a2, 0x2833, 0x3c53, 0xa01e, 0xaf08, 0x3c55, 0x2834, 0x3c54,
+    0xa01e, 0xaf08, 0x3c56, 0xe42e, 0xd049, 0x0000, 0xd047, 0x0000,
+    0x20a0, 0x4ca1, 0xe0c2, 0x0070, 0x289c, 0xe000, 0x07ca, 0xe094,
+    0x2902, 0x2ad6, 0xb7b2, 0xe0c2, 0x0071, 0x2895, 0xe0c2, 0x0072,
+    0x2a4b, 0xa805, 0xe01b, 0x284c, 0xa804, 0xe01a, 0xe052, 0xe016,
+    0xae0e, 0x4c50, 0xae02, 0x4c4f, 0xae02, 0x4c4e, 0xae04, 0x4c4a,
+    0xae20, 0x4c4b, 0xae06, 0x2a4a, 0xf02b, 0x4c4c, 0xe0c2, 0x0073,
+    0x2053, 0x4c54, 0xe0c2, 0x006f, 0xe0c2, 0x004f, 0xa200, 0xe162,
+    0x07ce, 0x2902, 0xa83e, 0xe162, 0x07e8, 0x2b02, 0xaf05, 0xa807,
+    0xb616, 0x2a9c, 0xa103, 0xb612, 0xae06, 0x2a9c, 0xae05, 0xe001,
+    0x07e4, 0xe095, 0x2b02, 0xaf07, 0xa80f, 0xe056, 0x2ad6, 0xb612,
+    0xe0c2, 0x0074, 0xa200, 0x28d6, 0xae04, 0xe0c2, 0x0075, 0x2894,
+    0xe016, 0xe0c2, 0x0076, 0xe162, 0x07c7, 0x2902, 0xb7e8, 0x2a94,
+    0xb7d2, 0x2ad6, 0xb7d2, 0xe0c2, 0x0077, 0xc84a, 0xc84d, 0xae20,
+    0xe056, 0xe0c2, 0x0053, 0xe41e, 0x030f, 0xe41e, 0x195d, 0xe42e,
+    0xe0c0, 0x0054, 0xe165, 0x07c5, 0x3515, 0x3d0d, 0xe42e, 0xe165,
+    0x07c5, 0x2115, 0x4d0d, 0xe0c2, 0x0054, 0xe42e, 0xe0c0, 0x005a,
+    0x3cee, 0xe41e, 0x0100, 0xa206, 0xe41e, 0x0344, 0xe0c0, 0x005a,
+    0x3cee, 0xe41e, 0x0100, 0x283c, 0xa104, 0xf07a, 0xa226, 0xe41e,
+    0x035a, 0xe41e, 0x0386, 0xe42e, 0xa236, 0xe41e, 0x0370, 0xe41e,
+    0x03c4, 0xe42e, 0x283c, 0xa104, 0xf07a, 0xa224, 0xe41e, 0x035a,
+    0xe41e, 0x03a5, 0xf06e, 0xa234, 0xe41e, 0x0370, 0xe41e, 0x03e4,
+    0xa204, 0xe41e, 0x0344, 0xe42e, 0x3ced, 0xe0c0, 0x0041, 0xe005,
+    0x0280, 0xae11, 0xe042, 0x22f0, 0x4ef1, 0xe042, 0xca29, 0xf7f9,
+    0xce20, 0xd111, 0x0000, 0xd112, 0x0c00, 0x88ed, 0x0113, 0xca28,
+    0xf7f8, 0xe42e, 0x3ced, 0xe0c0, 0x0041, 0xe005, 0x0298, 0xae11,
+    0xe042, 0x22f0, 0x4ef1, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111,
+    0x0000, 0xd112, 0x0100, 0x88ed, 0x0113, 0xca28, 0xf7f8, 0xe42e,
+    0x3ced, 0xe0c0, 0x0041, 0xe005, 0x0298, 0xae11, 0xe042, 0x22f0,
+    0x4ef1, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x00c0, 0xd112,
+    0x0040, 0x88ed, 0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe161, 0x07e0,
+    0x8911, 0x0034, 0x8911, 0x0033, 0x8911, 0x0035, 0x8911, 0x0036,
+    0x8911, 0x0037, 0x8911, 0x0038, 0x8911, 0x004b, 0x8911, 0x004c,
+    0x2111, 0x4d11, 0xcc60, 0x2111, 0x4d11, 0xcc62, 0x2111, 0x4d11,
+    0xcc64, 0x2111, 0x4d11, 0xcc72, 0xe42e, 0xe161, 0x07e0, 0x8b11,
+    0x0034, 0x8b11, 0x0033, 0x8b11, 0x0035, 0x8b11, 0x0036, 0x8b11,
+    0x0037, 0x8b11, 0x0038, 0x8b11, 0x004b, 0x8b11, 0x004c, 0xc860,
+    0x3511, 0x3d11, 0xc862, 0x3511, 0x3d11, 0xc864, 0x3511, 0x3d11,
+    0xc872, 0x3511, 0x3d11, 0xe42e, 0xe161, 0x07e0, 0x8911, 0x0145,
+    0x8911, 0x0144, 0x8911, 0x0146, 0x8911, 0x0147, 0x8911, 0x0148,
+    0x8911, 0x0152, 0x8911, 0x0153, 0x2111, 0x4d11, 0xce80, 0x2111,
+    0x4d11, 0xce82, 0x2111, 0x4d11, 0xce84, 0x2111, 0x4d11, 0xce86,
+    0x2111, 0x4d11, 0xcc72, 0xe42e, 0xe161, 0x07e0, 0x8b11, 0x0145,
+    0x8b11, 0x0144, 0x8b11, 0x0146, 0x8b11, 0x0147, 0x8b11, 0x0148,
+    0x8b11, 0x0152, 0x8b11, 0x0153, 0xca80, 0x3511, 0x3d11, 0xca82,
+    0x3511, 0x3d11, 0xca84, 0x3511, 0x3d11, 0xca86, 0x3511, 0x3d11,
+    0xc872, 0x3511, 0x3d11, 0xe42e, 0xe161, 0x0550, 0xe0c0, 0x0064,
+    0x3511, 0x3d11, 0xe0c0, 0x0065, 0x3511, 0x3d11, 0xe0c0, 0x0066,
+    0x3511, 0x3d11, 0xe0c0, 0x0067, 0x3511, 0x3d11, 0xe0c0, 0x0068,
+    0x3511, 0x3d11, 0xe0c0, 0x0069, 0xe167, 0x0ba0, 0x3d17, 0x3517,
+    0xe0c0, 0x006a, 0x3d17, 0x3517, 0xe0c0, 0x006b, 0x3d17, 0x3517,
+    0xe42e, 0xa200, 0x3cbf, 0x3cc8, 0x3cc9, 0x3cca, 0x3ccb, 0x3ccc,
+    0x3c91, 0xcc92, 0xcc8e, 0xe42e, 0xd146, 0x00c0, 0xd147, 0x00ff,
+    0xd144, 0x00c0, 0xd145, 0x0000, 0xd14b, 0x0200, 0xe004, 0x0180,
+    0xce30, 0xca32, 0xca32, 0xce84, 0xca32, 0xce86, 0xd144, 0x00c1,
+    0xe42e, 0xa200, 0xf02e, 0xa202, 0x3ce3, 0xa200, 0x3cc4, 0x3cc3,
+    0x3cc1, 0x3ccc, 0xe41e, 0x06fb, 0xf05a, 0xa214, 0x3cc0, 0xa200,
+    0xe42e, 0xcaa2, 0xaf10, 0xa102, 0xf07a, 0xcaa0, 0xe190, 0xca9c,
+    0xe418, 0x04af, 0xf70e, 0x28e3, 0xf07a, 0xcaa2, 0x3c03, 0xa83e,
+    0x3cc0, 0xa202, 0xe42e, 0xcaa0, 0xe190, 0xcaa0, 0xe190, 0xcaa0,
+    0xe190, 0xcaa0, 0x3c03, 0xca9c, 0xe418, 0x04af, 0xe41e, 0x06fb,
+    0xf05a, 0xa214, 0x3cc0, 0xa200, 0xe42e, 0x2803, 0xaf0e, 0xf5e8,
+    0x2803, 0xa83e, 0x3cc0, 0xe41e, 0x0581, 0xe41e, 0x05bd, 0xa202,
+    0xe42e, 0x28c1, 0xe428, 0xe004, 0x0080, 0x2ac5, 0xb616, 0xce92,
+    0xd14a, 0x0000, 0xd14c, 0x0001, 0xca9c, 0xe418, 0x04c6, 0xf098,
+    0xca9a, 0xf7b8, 0xca9c, 0xf798, 0xca94, 0x3cc2, 0xca9e, 0x3cc1,
+    0x28c2, 0x00c4, 0x0cc3, 0x34c4, 0x3cc3, 0xcc90, 0xcc8c, 0x28c1,
+    0xcc92, 0xcc8e, 0xe428, 0x28c5, 0xe016, 0x3cc5, 0xe42e, 0x28c8,
+    0xf048, 0xe41e, 0x0623, 0xe42e, 0x28ca, 0xf0e8, 0xa202, 0x3cca,
+    0xca90, 0xe002, 0x00c0, 0xa004, 0xa87e, 0xe000, 0x00c0, 0xce90,
+    0xd14e, 0x0000, 0xe42e, 0xa202, 0x3ccb, 0xe42e, 0x28c8, 0xf058,
+    0xe41e, 0x0623, 0xa200, 0xe42e, 0x28ca, 0xf0f8, 0xa202, 0x3cca,
+    0xca90, 0xe002, 0x00c0, 0xa004, 0xa87e, 0xe000, 0x00c0, 0xce90,
+    0xd14e, 0x0000, 0xa200, 0xe42e, 0x28cb, 0xe428, 0xca94, 0x3cc2,
+    0xa202, 0x3cc1, 0x3ccb, 0xd148, 0x00c0, 0xd14e, 0x0000, 0xca9c,
+    0xf03a, 0xd14e, 0x0000, 0xca9a, 0xf7b8, 0xca9c, 0xf798, 0xa202,
+    0xe42e, 0xa201, 0x283c, 0xa104, 0xb635, 0xe0c0, 0x0048, 0xe002,
+    0x0200, 0xf099, 0xe002, 0x0200, 0xe0c1, 0x0059, 0xa103, 0xf039,
+    0xe000, 0x0200, 0xf0c9, 0xc867, 0xe009, 0x007f, 0xa107, 0xae05,
+    0xe042, 0xc869, 0xaf07, 0xe015, 0xa807, 0xf0ae, 0xca89, 0xe003,
+    0x00c0, 0xa105, 0xae07, 0xe042, 0xca8b, 0xe015, 0xa80f, 0xe042,
+    0x2a3c, 0xa105, 0xf0eb, 0x22b9, 0x4eba, 0xe045, 0xf0a7, 0xe0c2,
+    0x007d, 0x2abb, 0xae11, 0xe0c3, 0x007e, 0xe042, 0xe0c2, 0x007f,
+    0xe0c2, 0x0046, 0xe42e, 0x28ce, 0xf05a, 0xe0c0, 0x0068, 0x34b9,
+    0x3cba, 0xe0c0, 0x0067, 0x34cf, 0x3cd0, 0xa2fe, 0x3cbb, 0xf0ce,
+    0xe0c0, 0x0060, 0x34b9, 0x3cba, 0xe0c0, 0x0061, 0xae14, 0x34cf,
+    0x3cd0, 0xaf10, 0x3cbb, 0x28cd, 0xe418, 0x06fe, 0x28cd, 0xe418,
+    0x0708, 0xa200, 0x3cbc, 0xe0c0, 0x0062, 0xaf0c, 0xa802, 0xf10a,
+    0xe0c1, 0x0048, 0xe0c0, 0x0060, 0xe045, 0xaf13, 0xae03, 0xa109,
+    0x3ebc, 0xf063, 0xe0c0, 0x0061, 0xae04, 0xe042, 0x3cbc, 0xa200,
+    0x3cc8, 0x3cc9, 0x3cca, 0x3ccb, 0x3ccc, 0xcc92, 0xcc8e, 0xe41e,
+    0x0662, 0x28de, 0xf02a, 0xe180, 0xe41e, 0x0581, 0xd071, 0x802a,
+    0x28de, 0xe428, 0xe181, 0x283c, 0xa104, 0xf04a, 0xe41e, 0x05bd,
+    0xf05e, 0xe41e, 0x0623, 0xe41e, 0x0434, 0x28cd, 0xe418, 0x0716,
+    0xe42e, 0xd030, 0x0000, 0xd031, 0x0000, 0xd032, 0x0000, 0xd034,
+    0x0000, 0xd033, 0x0000, 0xd035, 0x0000, 0xd036, 0x00ff, 0xd037,
+    0x0000, 0xd038, 0x0000, 0xd039, 0x0000, 0xd04b, 0x0001, 0xd04c,
+    0x0000, 0xe42e, 0xca29, 0xf7f9, 0xc896, 0xf05a, 0xe41e, 0x05d2,
+    0x3cc7, 0xf058, 0xd04b, 0x0001, 0xa200, 0x3cc7, 0x28c6, 0xcc6e,
+    0xd04c, 0x0000, 0xe470, 0xa202, 0x3cc7, 0xe41e, 0x05d2, 0xcc96,
+    0xe42a, 0x28c6, 0xcc6e, 0xe42e, 0xc896, 0xe428, 0xd04b, 0x0001,
+    0x28c6, 0xcc6e, 0xd04c, 0x0000, 0xe42e, 0xa200, 0x3cc5, 0x3cc6,
+    0xe41e, 0x05d2, 0x3cc7, 0xd04b, 0x0001, 0x28c6, 0xcc6e, 0xe190,
+    0xe128, 0x28c6, 0xa104, 0xe420, 0xe41e, 0x06b0, 0xe42a, 0x28c6,
+    0xcc6e, 0xe42e, 0xe41e, 0x06b0, 0xe428, 0x283c, 0xa104, 0xf04a,
+    0xe41e, 0x05e7, 0xf03e, 0xe41e, 0x0489, 0xe41e, 0x06d1, 0xe428,
+    0xe004, 0x0080, 0x2ac5, 0xb616, 0x3cc6, 0xa200, 0xe42e, 0xe082,
+    0x3cbd, 0xe004, 0x0048, 0xe092, 0xd027, 0x0000, 0xe41e, 0x0670,
+    0xd027, 0x0001, 0xca28, 0xf7f8, 0x28c8, 0x2ac9, 0xb602, 0xf248,
+    0x20b9, 0x4cba, 0x2ebc, 0xae11, 0xe042, 0xce20, 0x9f01, 0xe004,
+    0x0080, 0x2ac5, 0xb616, 0xce22, 0xd112, 0x0080, 0xe0c0, 0x0043,
+    0xa806, 0xae02, 0xa022, 0xce26, 0xca28, 0xf7f8, 0x2cbc, 0xe000,
+    0x0002, 0x3cbc, 0x1cbb, 0xf024, 0x3cbc, 0x20b9, 0x4cba, 0x2ebc,
+    0xae11, 0xe042, 0x9f01, 0x28bd, 0xe092, 0x28c8, 0xe428, 0x28c5,
+    0xe016, 0x3cc5, 0xe42e, 0xe082, 0x3cbd, 0xe004, 0x0048, 0xe092,
+    0xd027, 0x0000, 0xe41e, 0x0670, 0xd027, 0x0001, 0xca28, 0xf7f8,
+    0x28c8, 0x2ac9, 0xb602, 0xf2c8, 0x20b9, 0x4cba, 0x2ebc, 0xae11,
+    0xe042, 0xce20, 0xd111, 0x00c0, 0xd112, 0x0040, 0xe0c0, 0x0043,
+    0xa806, 0xae02, 0xa032, 0xce26, 0xca28, 0xf7f8, 0x2cbc, 0xe000,
+    0x0002, 0x3cbc, 0x1cbb, 0xf024, 0x3cbc, 0x20b9, 0x4cba, 0x2ebc,
+    0xae11, 0xe042, 0x9f01, 0xe004, 0x00c0, 0x2ac8, 0xf06b, 0x2ac9,
+    0xa00f, 0xaf07, 0xa87f, 0xe042, 0xce90, 0xd14e, 0x0000, 0x28bd,
+    0xe092, 0xe42e, 0xe082, 0x3cbd, 0x20b9, 0x4cba, 0x2ebc, 0xae11,
+    0xe042, 0xe005, 0x0048, 0xe093, 0x9f01, 0x28bd, 0xe092, 0xe42e,
+    0xe0c0, 0x0043, 0xa808, 0xe428, 0xa200, 0x3cbe, 0xe0c0, 0x0045,
+    0xaf04, 0x4ccd, 0x30bf, 0x20b9, 0x4cba, 0x2ebc, 0xae11, 0xe041,
+    0x8111, 0x9e09, 0xe046, 0xf042, 0x2ebb, 0xae11, 0xe042, 0xe002,
+    0x0200, 0xe422, 0xe000, 0x0200, 0x3cc9, 0x28bf, 0x3cc8, 0xe428,
+    0xe0c0, 0x0059, 0xa102, 0xf078, 0xe0c0, 0x0045, 0xa802, 0xf03a,
+    0xe16b, 0xe42e, 0x28be, 0xf5b8, 0xe0c0, 0x005c, 0xe008, 0x4000,
+    0xf56a, 0xe0c0, 0x005d, 0xe00a, 0x4000, 0xe0c2, 0x005d, 0xa202,
+    0xce00, 0x3cbe, 0xf4ce, 0xc868, 0xa80e, 0x3c00, 0x7400, 0xe42e,
+    0x283c, 0xa104, 0xf0aa, 0x28c8, 0xe42a, 0x28cc, 0xf0ca, 0xa102,
+    0xf160, 0xa202, 0x3ccb, 0xf0de, 0x28c1, 0xe42a, 0x28cc, 0xf03a,
+    0xa102, 0xf0d0, 0x28c6, 0xa004, 0x3cc6, 0xa202, 0x3ccc, 0xe42e,
+    0x28c6, 0xa002, 0x3cc6, 0xa204, 0x3ccc, 0xe42e, 0xe16b, 0xa202,
+    0xe42e, 0x283c, 0xa104, 0xf19a, 0x28c8, 0xe42a, 0x28c9, 0xf0ca,
+    0xe004, 0x0080, 0x2ac5, 0xb616, 0x2ac9, 0xa007, 0xaf05, 0xe042,
+    0x3cc6, 0xa202, 0xe42e, 0xe004, 0x0080, 0x2ac5, 0xb616, 0xa004,
+    0x3cc6, 0xa202, 0x3ccc, 0xe42e, 0x28c1, 0xe42a, 0x28c2, 0xf74a,
+    0xe004, 0x0080, 0x2ac5, 0xb616, 0x2ac2, 0xa007, 0xaf05, 0xe042,
+    0x3cc6, 0xa202, 0xe42e, 0x28c8, 0x44cb, 0xe42e, 0xa200, 0xe0c0,
+    0x0045, 0xaf04, 0x30bf, 0xe42a, 0xa200, 0x34cf, 0x3cd0, 0xe42e,
+    0xe082, 0x3cbd, 0x20b9, 0x4cba, 0x22cf, 0x4ed0, 0xe042, 0xe005,
+    0x0049, 0xe093, 0x9f01, 0x28bd, 0xe092, 0xe42e, 0xe0c1, 0x0059,
+    0xa103, 0xf049, 0xe0c0, 0x0064, 0xf03e, 0xe0c0, 0x0069, 0xa80e,
+    0x2a3c, 0xa105, 0xf05b, 0xa102, 0xe424, 0xba4f, 0xf7de, 0xa102,
+    0xe424, 0xcaa1, 0xf7de, 0xe0c0, 0x0067, 0xe049, 0xa806, 0x3c3c,
+    0xa809, 0xe41b, 0x09b3, 0xe41e, 0x0538, 0xa200, 0x3c90, 0x3c91,
+    0x3c93, 0xe16a, 0x283c, 0xa104, 0xf0c8, 0xe41e, 0x09f1, 0xf1ca,
+    0xe41e, 0x1057, 0xd1ff, 0x0000, 0xf17d, 0xe41e, 0x0760, 0xf06e,
+    0xe41e, 0x0f73, 0xd1ff, 0x0000, 0xf0fd, 0x2816, 0xf0d6, 0xe002,
+    0x0800, 0xf0a0, 0x2817, 0xf086, 0xe002, 0x0800, 0xf050, 0xa200,
+    0x3c93, 0xa202, 0xe42e, 0xa202, 0x3c93, 0xe16a, 0xa200, 0xe42e,
+    0xe41e, 0x044b, 0xe42a, 0xa200, 0x3c90, 0x28c0, 0xa118, 0xf0ca,
+    0x28c0, 0xa11a, 0xf09a, 0x28c0, 0xa11c, 0xf08a, 0x28c0, 0xa11e,
+    0xf0ba, 0xa200, 0xe42e, 0xa202, 0xe42e, 0xe41e, 0x0449, 0xe41e,
+    0x10f2, 0xe40e, 0x0760, 0xe41e, 0x0449, 0xe41e, 0x1057, 0xf03d,
+    0xe40e, 0x0760, 0xa202, 0x3c93, 0xa200, 0xe42e, 0xe41e, 0x0b58,
+    0xf068, 0xe41e, 0x08d5, 0xe41e, 0x08da, 0xe42e, 0x2810, 0xa104,
+    0xe408, 0x0795, 0xe40e, 0x07dd, 0xe42e, 0xa200, 0x3c94, 0x3c95,
+    0xe162, 0x0570, 0xc73f, 0x3d12, 0xe16a, 0xe41e, 0x06fb, 0xf03a,
+    0xa202, 0x3c91, 0xe41e, 0x09e6, 0xf0da, 0xa202, 0x3c91, 0x2891,
+    0xf09a, 0xa208, 0x3c4b, 0x3c4c, 0xe41e, 0x08ca, 0xe41e, 0x08da,
+    0xe42e, 0xe41e, 0x113d, 0xd1ff, 0x0001, 0xf06c, 0xa208, 0x3c4b,
+    0x3c4c, 0xa202, 0x3c94, 0x28d5, 0xe418, 0x0ab5, 0xf078, 0xe41e,
+    0x08ca, 0xe41e, 0x0935, 0xe41e, 0x08da, 0x2041, 0x4c42, 0xe005,
+    0x0030, 0xae21, 0xe046, 0xe422, 0x2041, 0x4c42, 0xae06, 0xc873,
+    0xe046, 0xe426, 0xe049, 0xa83f, 0xf05b, 0x3e00, 0xe046, 0x7600,
+    0xe426, 0xba7f, 0xa140, 0xf7e0, 0xe42e, 0xa200, 0x3c90, 0x3c92,
+    0xa200, 0x3c51, 0x3c52, 0x3c57, 0x2892, 0xe428, 0x2890, 0xf108,
+    0x283c, 0xa104, 0xf058, 0xe41e, 0x0449, 0xf2ea, 0xf09e, 0xe41e,
+    0x06fb, 0xf2a8, 0xba4e, 0xba4e, 0xba4e, 0xba4e, 0x3cc0, 0xa200,
+    0x3c90, 0x28c0, 0xa114, 0xf20a, 0x28c0, 0xa116, 0xf27a, 0x28c0,
+    0xa118, 0xf26a, 0x28c0, 0xa11a, 0xf27a, 0x28c0, 0xa11c, 0xf28a,
+    0x28c0, 0xa11e, 0xf2da, 0x28c0, 0xa136, 0xf37a, 0x28c0, 0xa138,
+    0xf34a, 0x28c0, 0xa13a, 0xf31a, 0x28c0, 0xa13c, 0xf2ea, 0x28c0,
+    0xa13e, 0xf2ba, 0xf4ae, 0xa202, 0x3c91, 0xa208, 0x3c4b, 0x3c4c,
+    0xe41e, 0x08ca, 0xe41e, 0x08da, 0xe42e, 0xe40e, 0x07e4, 0xe41e,
+    0x08a3, 0xe40e, 0x07e4, 0xe41e, 0x0848, 0xe40e, 0x07e4, 0xe41e,
+    0x10f2, 0xe41e, 0x112e, 0xd1ff, 0x0000, 0xe40e, 0x07e4, 0xe41e,
+    0x1057, 0xe41e, 0x10c5, 0xe41e, 0x0b55, 0xa200, 0x3c91, 0xd1ff,
+    0x0000, 0xe42d, 0xe40e, 0x07e4, 0xe41e, 0x19bf, 0xe40e, 0x07e4,
+    0xa200, 0x3c94, 0x3c95, 0xe162, 0x0570, 0xc73f, 0x3d12, 0xe16a,
+    0xe41e, 0x1154, 0x28df, 0xf098, 0x2855, 0xae10, 0x2a54, 0xa01f,
+    0xaf09, 0xe056, 0x3cdf, 0xf15e, 0x28df, 0xa002, 0xf0da, 0x2cdf,
+    0xaf10, 0x1855, 0xf094, 0x28df, 0xe008, 0x00ff, 0x2a54, 0xa01f,
+    0xaf09, 0xe046, 0xf062, 0xa2fe, 0x3cdf, 0xa202, 0x3c92, 0xe16b,
+    0xd1ff, 0x0001, 0xf06c, 0xa208, 0x3c4b, 0x3c4c, 0xa202, 0x3c94,
+    0x28d5, 0xe418, 0x0ab5, 0xf058, 0xe41e, 0x08ca, 0xe41e, 0x0935,
+    0x284a, 0xa106, 0x2a4b, 0xa109, 0xb636, 0xf05a, 0xe41e, 0x08da,
+    0xa202, 0x3c92, 0x2892, 0xe428, 0x2851, 0xa002, 0x3c51, 0xe41e,
+    0x0a31, 0xe428, 0x28d6, 0xe428, 0xa202, 0x3c94, 0x284e, 0x3c52,
+    0xa200, 0x3c57, 0xe41e, 0x0bb3, 0xe41e, 0x0935, 0xe41e, 0x08da,
+    0xa202, 0x3c92, 0xe42e, 0x284a, 0xa106, 0xe428, 0x2851, 0xa102,
+    0xe428, 0x28d6, 0xf118, 0xe41e, 0x116b, 0xd1ff, 0x0001, 0xf03c,
+    0xa202, 0x3c94, 0x28d7, 0xe016, 0x3cd7, 0xe41e, 0x0bb3, 0xe41e,
+    0x0935, 0xe41e, 0x08da, 0xa202, 0x3c92, 0xe42e, 0x28d6, 0xe428,
+    0xe41e, 0x1177, 0xd1ff, 0x0001, 0xf03c, 0xa202, 0x3c94, 0xe41e,
+    0x0935, 0xe42e, 0xe41e, 0x0b5d, 0xe41e, 0x0bb3, 0xe41e, 0x0dfa,
+    0xe41e, 0x18b3, 0xe41e, 0x17e7, 0xe42e, 0xe41e, 0x0b75, 0xe41e,
+    0x17e7, 0xe42e, 0xe41e, 0x186d, 0xe42e, 0xa200, 0x3c87, 0x3c88,
+    0x3c86, 0x2886, 0xe0c2, 0x003f, 0xa200, 0xe0c2, 0x0113, 0xe0c2,
+    0x030d, 0xa200, 0xe0c2, 0x0114, 0xe0c2, 0x0115, 0xe0c2, 0x0116,
+    0xe0c2, 0x0130, 0x2888, 0x1857, 0x4c87, 0xe016, 0xe0c2, 0x0131,
+    0xa200, 0xe0c2, 0x012a, 0xa23e, 0xe0c2, 0x030f, 0xa200, 0xe0c2,
+    0x0309, 0xe004, 0x0055, 0xe0c2, 0x030c, 0xa200, 0xe0c2, 0x030a,
+    0xe0c2, 0x030b, 0xe162, 0x03b0, 0xa200, 0xd022, 0x001f, 0xe184,
+    0x0912, 0x9f12, 0xe190, 0xe0c0, 0x0111, 0xf7e8, 0xa202, 0xe0c2,
+    0x0110, 0x28a7, 0xe418, 0x1886, 0xe41e, 0x1b49, 0xd1ff, 0x0002,
+    0x2886, 0xa002, 0x3c86, 0x2887, 0xa002, 0x3c87, 0x1855, 0xe404,
+    0x08e1, 0xa200, 0x3c87, 0x2888, 0xa002, 0x3c88, 0x1856, 0xe404,
+    0x08e1, 0xe0c0, 0x0111, 0xf7e8, 0xe42e, 0xe166, 0x07c7, 0x2906,
+    0xe424, 0xe41e, 0x151f, 0xe41e, 0x1638, 0x2894, 0xf038, 0xe16a,
+    0xf02e, 0xe16b, 0x284b, 0xa108, 0xe40a, 0x08dd, 0xe42a, 0xa2fe,
+    0xcf08, 0xd18c, 0x0001, 0xcb18, 0xf7f8, 0xa200, 0x3c87, 0x3c88,
+    0x3c86, 0x2886, 0xe0c2, 0x003f, 0xe41e, 0x1ab9, 0xe41e, 0x1ad3,
+    0xe41e, 0x1b31, 0x28a7, 0xe418, 0x1886, 0xe41e, 0x1b49, 0xd1ff,
+    0x0002, 0x2886, 0xa002, 0x3c86, 0x2887, 0xa002, 0x3c87, 0x1855,
+    0xf694, 0xa200, 0x3c87, 0x2888, 0xa002, 0x3c88, 0x1856, 0xf322,
+    0xa202, 0x2a3e, 0xe419, 0x11a6, 0xe40a, 0x099e, 0x2810, 0xa104,
+    0xf598, 0xc894, 0x4c6b, 0xf568, 0x2894, 0xf218, 0xe41e, 0x0a73,
+    0xf1ea, 0xe41e, 0x1177, 0xd1ff, 0x0001, 0xf19d, 0x2888, 0x1857,
+    0xf168, 0x2856, 0x1857, 0xf136, 0xe41e, 0x151f, 0xe41e, 0x1638,
+    0xa200, 0x3c87, 0x2857, 0x3c88, 0x8488, 0x8255, 0xe018, 0x3c86,
+    0x28d7, 0xe016, 0x3cd7, 0xe16a, 0xe40e, 0x0951, 0xe16b, 0xe40e,
+    0x0951, 0x2856, 0xcf08, 0xd18c, 0x0001, 0xcb18, 0xf7f8, 0xe0c0,
+    0x0111, 0xf7e8, 0xe0c0, 0x0065, 0xaf18, 0xa802, 0xf04a, 0xe0c0,
+    0x0281, 0xf7ea, 0xe42e, 0xd030, 0x0000, 0xd034, 0x0000, 0xd033,
+    0x0000, 0xd035, 0x0000, 0xd036, 0x007f, 0xd037, 0x0000, 0xd038,
+    0x0000, 0xe181, 0xca28, 0xf7f8, 0xe0c0, 0x0060, 0xce20, 0xd111,
+    0x0000, 0xd112, 0x0020, 0xe0c0, 0x0043, 0xa806, 0xae02, 0xa022,
+    0xce26, 0xca28, 0xf7f8, 0xe128, 0x28cd, 0xf08a, 0xe0c0, 0x0064,
+    0xa80e, 0xa102, 0xf034, 0xba4f, 0xf7de, 0xba3f, 0xe009, 0x0085,
+    0xe003, 0x0085, 0xa204, 0xb636, 0x3c3c, 0xe42e, 0x203a, 0x4c3b,
+    0xf074, 0x229e, 0x4e9f, 0xe046, 0xf030, 0xa202, 0xe42e, 0xa200,
+    0xe42e, 0x2890, 0xf108, 0x283c, 0xa104, 0xf058, 0xe41e, 0x0449,
+    0xf2ca, 0xf09e, 0xe41e, 0x06fb, 0xf288, 0xba4e, 0xba4e, 0xba4e,
+    0xba4e, 0x3cc0, 0x28c0, 0xa114, 0xf20a, 0x28c0, 0xa116, 0xf25a,
+    0x28c0, 0xa118, 0xf22a, 0x28c0, 0xa11a, 0xf1fa, 0x28c0, 0xa11c,
+    0xf1ca, 0x28c0, 0xa11e, 0xf15a, 0x28c0, 0xa136, 0xf16a, 0x28c0,
+    0xa138, 0xf13a, 0x28c0, 0xa13a, 0xf10a, 0x28c0, 0xa13c, 0xf0da,
+    0x28c0, 0xa13e, 0xf0aa, 0xf4ee, 0xa202, 0x3c90, 0xa200, 0xe42e,
+    0xa202, 0x3c90, 0xa202, 0xe42e, 0xa200, 0x3c90, 0xe40e, 0x09f1,
+    0xe42e, 0x2890, 0xf108, 0x283c, 0xa104, 0xf058, 0xe41e, 0x0449,
+    0xf2ca, 0xf09e, 0xe41e, 0x06fb, 0xf288, 0xba4e, 0xba4e, 0xba4e,
+    0xba4e, 0x3cc0, 0x28c0, 0xa114, 0xf20a, 0x28c0, 0xa116, 0xf1da,
+    0x28c0, 0xa118, 0xf1ea, 0x28c0, 0xa11a, 0xf17a, 0x28c0, 0xa11c,
+    0xf14a, 0x28c0, 0xa11e, 0xf11a, 0x28c0, 0xa136, 0xf16a, 0x28c0,
+    0xa138, 0xf13a, 0x28c0, 0xa13a, 0xf10a, 0x28c0, 0xa13c, 0xf0da,
+    0x28c0, 0xa13e, 0xf0aa, 0xf4ee, 0xa202, 0x3c90, 0xa200, 0xe42e,
+    0xa202, 0x3c90, 0xa202, 0xe42e, 0xe41e, 0x19bf, 0xa200, 0x3c90,
+    0xe40e, 0x0a31, 0xe42e, 0x2890, 0xf108, 0x283c, 0xa104, 0xf058,
+    0xe41e, 0x0449, 0xf2ca, 0xf09e, 0xe41e, 0x06fb, 0xf288, 0xba4e,
+    0xba4e, 0xba4e, 0xba4e, 0x3cc0, 0x28c0, 0xa114, 0xf20a, 0x28c0,
+    0xa116, 0xf21a, 0x28c0, 0xa118, 0xf1aa, 0x28c0, 0xa11a, 0xf17a,
+    0x28c0, 0xa11c, 0xf14a, 0x28c0, 0xa11e, 0xf11a, 0x28c0, 0xa136,
+    0xf16a, 0x28c0, 0xa138, 0xf13a, 0x28c0, 0xa13a, 0xf10a, 0x28c0,
+    0xa13c, 0xf0da, 0x28c0, 0xa13e, 0xf0aa, 0xf4ee, 0xa202, 0x3c90,
+    0xa200, 0xe42e, 0xa200, 0x3c90, 0xa202, 0xe42e, 0xe41e, 0x19bf,
+    0xa200, 0x3c90, 0xe40e, 0x0a73, 0xe42e, 0x28cd, 0xf17a, 0x28d5,
+    0xf3ea, 0xa102, 0xf06a, 0xa102, 0xf08a, 0xa104, 0xf0aa, 0xf33e,
+    0x284b, 0x4c4c, 0xf308, 0xf33e, 0x284b, 0x4c4c, 0xf30a, 0xf2be,
+    0x284b, 0x4c4c, 0xa804, 0xf2b8, 0xf26e, 0x28d5, 0xf28a, 0xa102,
+    0xf06a, 0xa102, 0xf0ca, 0xa104, 0xf12a, 0xf1de, 0x284b, 0x4c4c,
+    0xf168, 0x28d4, 0xf1c6, 0xa102, 0x3cd4, 0xf11e, 0x284b, 0x4c4c,
+    0xf16a, 0x28d4, 0xa102, 0x3cd4, 0xf0e6, 0xf09e, 0x284b, 0x4c4c,
+    0xa804, 0xf0d8, 0x28d4, 0xa102, 0x3cd4, 0xf056, 0xa204, 0x3cd6,
+    0xa202, 0xe42e, 0xa202, 0x3cd6, 0xa202, 0xe42e, 0xa200, 0x3cd6,
+    0xa200, 0xe42e, 0xa202, 0x3c8d, 0xa202, 0x3c8e, 0x283f, 0x2a10,
+    0xa105, 0xb636, 0x3c8b, 0xa200, 0x3c8c, 0x2840, 0xb630, 0x2a10,
+    0xa105, 0xb636, 0x3c8f, 0xa204, 0x2a8f, 0xb452, 0xa004, 0x3c97,
+    0xa104, 0xf030, 0xa206, 0x3c97, 0xa200, 0x2a8f, 0xb432, 0xa002,
+    0x2a89, 0xb616, 0x3c99, 0x288d, 0x4c8e, 0xb630, 0x3c9a, 0xa200,
+    0x289a, 0x2a89, 0xb612, 0x3c9a, 0x288f, 0x3c9b, 0x2a89, 0xb616,
+    0x3c9b, 0xa200, 0x3c9c, 0xa002, 0x2a89, 0xb616, 0x3c9c, 0xa202,
+    0x3c9d, 0xa200, 0x3c9e, 0x3ca0, 0xe42e, 0xe165, 0x06e0, 0xa200,
+    0xd022, 0x001f, 0xe184, 0x0b3d, 0x3d15, 0xa002, 0xe165, 0x07c3,
+    0xa200, 0x3515, 0x3d15, 0x3515, 0x3d15, 0xe165, 0x07c7, 0xa2fa,
+    0xc708, 0x3d15, 0x2816, 0xa01e, 0xaf08, 0xae08, 0x3ca2, 0x2817,
+    0xa01e, 0xaf08, 0xae08, 0x3ca3, 0xe42e, 0xa202, 0x3c9d, 0xe42e,
+    0xe41e, 0x0dcd, 0xb60c, 0xb620, 0xe42e, 0xe41e, 0x0c3c, 0xe41e,
+    0x0c73, 0xe41e, 0x0cf7, 0xe41e, 0x0d20, 0xe41e, 0x0d2a, 0xa200,
+    0x3c9d, 0x209e, 0x4c9f, 0x2a91, 0xb436, 0x349e, 0x3c9f, 0x20a0,
+    0x4ca1, 0xa002, 0x34a0, 0x3ca1, 0xe42e, 0xa2fa, 0xe162, 0x07c7,
+    0x3d02, 0xe162, 0x07db, 0xe163, 0x07eb, 0xe164, 0x07ef, 0xd022,
+    0x0003, 0xe184, 0x0b84, 0x290b, 0x3d0c, 0xd022, 0x0003, 0xe184,
+    0x0b8a, 0x290b, 0x3d0c, 0xd022, 0x0003, 0xe184, 0x0b90, 0x290a,
+    0x3d0c, 0xe162, 0x07c7, 0xe163, 0x07cb, 0xe164, 0x07cc, 0x290b,
+    0x3d0c, 0x290b, 0x3d0c, 0x290a, 0x3d0c, 0xe162, 0x07e8, 0x28a4,
+    0x4ca5, 0xae02, 0x4d02, 0x3d12, 0x28a4, 0xae02, 0x4ca5, 0xae08,
+    0x4ca6, 0xae14, 0x4d02, 0x3d02, 0xe41e, 0x0d20, 0xe41e, 0x0d2a,
+    0xa200, 0x3c9d, 0xe42e, 0xe004, 0x004b, 0x0851, 0xe094, 0x2902,
+    0xa80c, 0xe428, 0x2851, 0xe408, 0x0bff, 0x2852, 0xae02, 0xe000,
+    0x07d5, 0xe094, 0xa10a, 0xe096, 0x2902, 0x3d03, 0x2852, 0xe016,
+    0xae02, 0xe000, 0x07d5, 0xe094, 0xa10a, 0xe096, 0x2902, 0x3d03,
+    0xa206, 0x2a52, 0xb616, 0x2a4a, 0xa107, 0xb612, 0xe000, 0x0067,
+    0xe094, 0x2852, 0xae02, 0xe000, 0x07d1, 0xe096, 0x290a, 0xae0c,
+    0x4d0a, 0xae02, 0x4d0a, 0x3d03, 0xa206, 0x2a52, 0xb612, 0x2a4a,
+    0xa107, 0xb612, 0xe000, 0x0067, 0xe094, 0x2852, 0xe016, 0xae02,
+    0xe000, 0x07d1, 0xe096, 0x290a, 0xae0c, 0x4d0a, 0xae02, 0x4d0a,
+    0x3d03, 0xe162, 0x07d4, 0xa200, 0xc703, 0x3d12, 0xe42e, 0x2852,
+    0xae02, 0xe000, 0x07d1, 0xe094, 0xa102, 0xe096, 0x2902, 0x3d03,
+    0x2852, 0xe016, 0xae02, 0xe000, 0x07d5, 0xe094, 0xa102, 0xe096,
+    0x2902, 0x3d03, 0xa206, 0x2a52, 0xb616, 0x2a4a, 0xa107, 0xb612,
+    0xe000, 0x0067, 0xe094, 0x2852, 0xae02, 0xe000, 0x07d1, 0xe096,
+    0x290a, 0xae0c, 0x4d0a, 0xae02, 0x4d0a, 0x3d03, 0xa206, 0x2a52,
+    0xb612, 0x2a4a, 0xa107, 0xb612, 0xe000, 0x0067, 0xe094, 0x2852,
+    0xe016, 0xae02, 0xe000, 0x07d5, 0xe096, 0x290a, 0xae0c, 0x4d0a,
+    0xae02, 0x4d0a, 0x3d03, 0xe42e, 0xe162, 0x07d8, 0x2836, 0xae02,
+    0x4c38, 0xae06, 0x4c37, 0xae06, 0x4c39, 0xae02, 0x4c5c, 0xae02,
+    0x4c8c, 0xae04, 0x4c5b, 0xae02, 0xe0c1, 0x0065, 0xaf19, 0xa803,
+    0xf069, 0x2a36, 0x4e38, 0x4e5c, 0x468b, 0xb432, 0xae02, 0x2a5b,
+    0xb633, 0x468c, 0xb432, 0xae02, 0xa900, 0xae02, 0xa900, 0x3d12,
+    0xa200, 0xae02, 0xa900, 0xae08, 0xa900, 0xae04, 0x4c10, 0xae04,
+    0x4c4a, 0xae06, 0x4c4b, 0xae06, 0x4c4c, 0x3d12, 0x2853, 0x3d12,
+    0x2854, 0x3d12, 0xe42e, 0x284b, 0xa804, 0xe408, 0x0ccd, 0xe162,
+    0x07c7, 0xe163, 0x07c8, 0xa203, 0x2913, 0xe419, 0x0d8a, 0x2903,
+    0x2a91, 0xb7f2, 0xe41b, 0x0d35, 0x3d02, 0xe162, 0x07d8, 0xe163,
+    0x07dc, 0xe164, 0x07e0, 0xd022, 0x0003, 0xe184, 0x0c90, 0x2914,
+    0x3d13, 0xd022, 0x0003, 0xe184, 0x0c96, 0x2912, 0x3d13, 0xe162,
+    0x07c7, 0xe163, 0x07c8, 0xe164, 0x07c9, 0x2914, 0x3d13, 0x2912,
+    0x3d13, 0x289b, 0xe016, 0xae04, 0xe000, 0x07df, 0xe094, 0xe163,
+    0x07eb, 0xe164, 0x07ef, 0xd022, 0x0003, 0xe184, 0x0cb0, 0x290b,
+    0x3d0c, 0xd022, 0x0003, 0xe184, 0x0cb6, 0x290b, 0x3d0c, 0xd022,
+    0x0003, 0xe184, 0x0cbc, 0x290a, 0x3d0c, 0x289b, 0xe016, 0xe000,
+    0x07c8, 0xe094, 0xe163, 0x07cb, 0xe164, 0x07cc, 0x290b, 0x3d0c,
+    0x290b, 0x3d0c, 0x290a, 0x3d0c, 0xe42e, 0xe41e, 0x0d57, 0xe162,
+    0x07c7, 0x3d02, 0xe162, 0x07db, 0xe163, 0x07eb, 0xe164, 0x07ef,
+    0xd022, 0x0003, 0xe184, 0x0cdd, 0x290b, 0x3d0c, 0xd022, 0x0003,
+    0xe184, 0x0ce3, 0x290b, 0x3d0c, 0xd022, 0x0003, 0xe184, 0x0ce9,
+    0x290a, 0x3d0c, 0xe162, 0x07c7, 0xe163, 0x07cb, 0xe164, 0x07cc,
+    0x290b, 0x3d0c, 0x290b, 0x3d0c, 0x290a, 0x3d0c, 0xe42e, 0xe162,
+    0x07e8, 0x28a4, 0x4ca5, 0xae02, 0x4d02, 0x3d12, 0x28a4, 0xae02,
+    0x4ca5, 0xae08, 0x4ca6, 0xae14, 0x4d02, 0x3d02, 0x289c, 0xe42a,
+    0xe163, 0x07cb, 0x2903, 0xe424, 0xe162, 0x07e8, 0x2902, 0xa81c,
+    0xe42a, 0xe162, 0x07ce, 0xe163, 0x07cb, 0x2903, 0x3d02, 0xe41e,
+    0x0d57, 0x3d0b, 0x2902, 0x2b02, 0x1b03, 0xe419, 0x0d9c, 0xe42e,
+    0x289c, 0xa002, 0xe000, 0x07ca, 0xe094, 0x2902, 0xe424, 0xe41e,
+    0x0dae, 0xe42e, 0xe162, 0x07ca, 0x2912, 0xe412, 0x0d79, 0x289c,
+    0xe426, 0x2912, 0xe412, 0x0d79, 0xe42e, 0xe165, 0x07c3, 0x2115,
+    0x4d15, 0x2315, 0x4f15, 0xe056, 0xe165, 0x06e0, 0x2a98, 0xf0b7,
+    0xa103, 0xcc45, 0xe184, 0x0d49, 0x2b15, 0x3e01, 0xe049, 0x5e01,
+    0xa803, 0xf03b, 0xa2fa, 0xe42e, 0xe165, 0x07c3, 0x2115, 0x4d0d,
+    0xa203, 0x5a01, 0xe056, 0x3515, 0x3d0d, 0x2801, 0xe42e, 0xe165,
+    0x07c3, 0x2115, 0x4d15, 0x2315, 0x4f15, 0xe056, 0xe165, 0x06e0,
+    0x2a98, 0xf0b7, 0xa103, 0xcc45, 0xe184, 0x0d6b, 0x2b15, 0x3e01,
+    0xe049, 0x5e01, 0xa803, 0xf03b, 0xa2fa, 0xe42e, 0xe165, 0x07c5,
+    0x2115, 0x4d0d, 0xa203, 0x5a01, 0xe056, 0x3515, 0x3d0d, 0x2801,
+    0xe42e, 0xe424, 0x3c01, 0x2898, 0xa102, 0x1801, 0xe424, 0xe165,
+    0x07c5, 0x2115, 0x4d0d, 0xa203, 0x5a01, 0xe056, 0x3515, 0x3d0d,
+    0x2801, 0xe42e, 0xe424, 0x3c01, 0x2898, 0xa102, 0x1801, 0xe424,
+    0xe165, 0x07c3, 0x2115, 0x4d0d, 0xa203, 0x5a01, 0xe015, 0xe052,
+    0x3515, 0x3d0d, 0x2801, 0xe42e, 0xe424, 0x3c01, 0x2898, 0xa102,
+    0x1801, 0xe424, 0xe165, 0x07c5, 0x2115, 0x4d0d, 0xa203, 0x5a01,
+    0xe015, 0xe052, 0x3515, 0x3d0d, 0x2801, 0xe42e, 0xe424, 0x3c01,
+    0x2898, 0xa102, 0x1801, 0xe424, 0xe165, 0x06e0, 0x2a98, 0xf087,
+    0xa103, 0xcc45, 0xe184, 0x0dbe, 0x2b15, 0x1a01, 0xf03b, 0xa2fa,
+    0xe42e, 0xc845, 0xf067, 0xe184, 0x0dc7, 0x290d, 0x3d15, 0x8115,
+    0x2801, 0x810d, 0x3d15, 0x2801, 0xe42e, 0xa200, 0x3c02, 0xe165,
+    0x07c3, 0x2115, 0x4d15, 0x2315, 0x4f15, 0xe056, 0xe165, 0x06e0,
+    0x2a98, 0xf0f7, 0xa103, 0xcc45, 0xe184, 0x0de7, 0x2b15, 0x3e01,
+    0xe049, 0x5e01, 0xa803, 0xf049, 0x2a02, 0xa003, 0x3e02, 0xe190,
+    0x2802, 0xe42e, 0xe165, 0x0505, 0xa2fa, 0x3d15, 0x3d15, 0x3d15,
+    0xe165, 0x0500, 0xa200, 0xd022, 0x0002, 0xe184, 0x0df8, 0x3d15,
+    0xa002, 0xe42e, 0xa200, 0x3cb1, 0x3cb2, 0xe162, 0x0500, 0xe163,
+    0x0501, 0xe164, 0x0502, 0xe165, 0x0504, 0xe166, 0x0503, 0xe167,
+    0x0505, 0x284b, 0xa808, 0xf2c8, 0x284b, 0xa804, 0xf188, 0x2904,
+    0x2b02, 0x3d02, 0x2903, 0x3f03, 0x3d04, 0x2902, 0xa806, 0x2a4a,
+    0xae11, 0xe056, 0x3d02, 0x289b, 0xe000, 0x0500, 0xe098, 0x2906,
+    0x3d05, 0x2904, 0x3d06, 0x2902, 0x3d07, 0xe42e, 0x2904, 0x2b03,
+    0x3d03, 0x3f04, 0x2903, 0xa806, 0x2a4a, 0xae11, 0xe056, 0x3d03,
+    0x2906, 0x3d05, 0x2903, 0x3d06, 0x2903, 0x3d07, 0xe42e, 0x2906,
+    0x3d05, 0x2902, 0x3d06, 0x2902, 0x3d07, 0xe42e, 0xe162, 0x0505,
+    0x2b02, 0xaf11, 0xa807, 0xa107, 0xe40b, 0x0e87, 0x2eb1, 0xaf03,
+    0xa8ff, 0xe001, 0x0380, 0xe095, 0x2eb1, 0xa803, 0xa83e, 0xf03b,
+    0xae10, 0x4d02, 0x3d02, 0x2cb1, 0xa002, 0x3cb1, 0xe008, 0x00ff,
+    0xf09a, 0x2887, 0x1855, 0xa002, 0xe424, 0x2888, 0x1856, 0xa002,
+    0xe424, 0xe162, 0x0505, 0x2b02, 0xa807, 0xa103, 0xa200, 0xb4a6,
+    0xb4a2, 0xae16, 0x2eb1, 0xaf03, 0xa103, 0xb60b, 0xaf0f, 0xae11,
+    0xe042, 0xe005, 0x029c, 0xae11, 0xe042, 0xe0c1, 0x0041, 0xe042,
+    0x22f0, 0x4ef1, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0380,
+    0xd112, 0x0080, 0xd113, 0x0002, 0xca29, 0xf7f9, 0xe42e, 0x2a87,
+    0xaf03, 0xe001, 0x0380, 0xe095, 0x2a87, 0xa803, 0xa83e, 0xf03b,
+    0xae10, 0x4d02, 0x3d02, 0x2887, 0x1855, 0xa002, 0xe424, 0x2855,
+    0xa00e, 0xaf06, 0xae04, 0x3cae, 0x84ae, 0x8288, 0xe018, 0xae02,
+    0x3cb0, 0xe162, 0x0505, 0x2b02, 0xa807, 0xa103, 0xa200, 0xb4a6,
+    0xb4a2, 0xae02, 0x2a51, 0xb4b2, 0xae14, 0x08b0, 0xe005, 0x029c,
+    0xae11, 0xe042, 0xe0c1, 0x0041, 0xe042, 0x22f0, 0x4ef1, 0xe042,
+    0xca29, 0xf7f9, 0xce20, 0xd111, 0x0380, 0x28ae, 0xce24, 0xd113,
+    0x0002, 0xca29, 0xf7f9, 0xe42e, 0xe162, 0x0504, 0x2b02, 0xaf11,
+    0xa807, 0xa107, 0xe40b, 0x0eff, 0x2cb2, 0xe008, 0x00ff, 0xf208,
+    0xe162, 0x0504, 0x2b02, 0xa807, 0xa103, 0xa200, 0xb4a6, 0xb4a2,
+    0xae16, 0x0cb2, 0xe005, 0x029c, 0xae11, 0xe042, 0xe0c1, 0x0041,
+    0xe042, 0x22f0, 0x4ef1, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111,
+    0x0400, 0xd112, 0x0080, 0xd113, 0x0003, 0xca29, 0xf7f9, 0x2cb2,
+    0xaf02, 0xa8fe, 0xe000, 0x0400, 0xe094, 0x2902, 0x2eb2, 0xa803,
+    0xf02b, 0xaf10, 0xa83e, 0x2eb2, 0xa003, 0x3eb2, 0xe42e, 0x28aa,
+    0xe408, 0x0f67, 0x28ab, 0xa802, 0xe408, 0x0f67, 0x28a8, 0xa00e,
+    0xaf06, 0xae04, 0x3cae, 0x28ab, 0xaf02, 0x3caf, 0x84ae, 0x82af,
+    0xe018, 0xae02, 0x3cb0, 0xe162, 0x0504, 0x2b02, 0xa807, 0xa103,
+    0xa200, 0xb4a6, 0xb4a2, 0xae16, 0x08b0, 0xe005, 0x029c, 0xae11,
+    0xe042, 0xe0c1, 0x0041, 0xe042, 0x22f0, 0x4ef1, 0xe042, 0xca29,
+    0xf7f9, 0xce20, 0xd111, 0x0400, 0x28ae, 0xce24, 0xd113, 0x0003,
+    0xca29, 0xf7f9, 0xe162, 0x0504, 0x2b02, 0xa807, 0xa103, 0xa200,
+    0xb4a6, 0xb4a2, 0xae02, 0xa00a, 0xae14, 0x08b0, 0xe005, 0x029c,
+    0xae11, 0xe042, 0xe0c1, 0x0041, 0xe042, 0x22f0, 0x4ef1, 0xe042,
+    0xca29, 0xf7f9, 0xce20, 0xd111, 0x0480, 0x28ae, 0xce24, 0xd113,
+    0x0003, 0xca29, 0xf7f9, 0xe164, 0x0400, 0xe165, 0x0480, 0x28ae,
+    0xf0f6, 0xa102, 0xcc44, 0xe184, 0x0f66, 0x2904, 0x0915, 0xaf02,
+    0xe049, 0xaf10, 0xa83e, 0xae10, 0xa83f, 0xe056, 0x3d14, 0x28aa,
+    0xaf02, 0xe000, 0x0400, 0xe094, 0x2902, 0x2aaa, 0xa803, 0xf02b,
+    0xaf10, 0xa83e, 0xe42e, 0xe41e, 0x06ab, 0xba4e, 0xba4f, 0xae11,
+    0xe056, 0xba4f, 0xae21, 0xe056, 0xb7f4, 0xe005, 0x00ff, 0xae21,
+    0xe00b, 0xffff, 0xe045, 0xb7f6, 0x343a, 0x3c3b, 0xba4e, 0x3c3c,
+    0xe008, 0x0085, 0xe002, 0x0085, 0xe408, 0x1039, 0xba4e, 0xba4f,
+    0xae11, 0xe056, 0xba4f, 0xae21, 0xe056, 0xba4f, 0xae31, 0xe055,
+    0xa109, 0xe405, 0x1039, 0xba42, 0x3c10, 0xba40, 0x3c48, 0xba40,
+    0x3c49, 0xba44, 0x3c13, 0xba48, 0x3c14, 0xba40, 0x3c2c, 0xba40,
+    0x3c43, 0xba40, 0x3c3d, 0xba40, 0x3c44, 0xba40, 0x3c2d, 0xba40,
+    0x3c2e, 0xba42, 0x3c2f, 0xba40, 0x3c30, 0xba40, 0x3c45, 0xba40,
+    0x3c31, 0xba40, 0x3c3e, 0xba40, 0x3c3f, 0xba44, 0x3c40, 0xba42,
+    0x3c32, 0xba40, 0x3c1b, 0xba40, 0x3c46, 0x2813, 0xae04, 0xa004,
+    0x3c21, 0xa202, 0x3c22, 0x2848, 0xe408, 0x1039, 0x2849, 0xe408,
+    0x1039, 0x2810, 0xa104, 0xe40a, 0x1039, 0x2844, 0xe40a, 0x1039,
+    0x2843, 0xe408, 0x1039, 0x2810, 0xa104, 0xb7f4, 0xa004, 0x3c10,
+    0xf047, 0xba4e, 0xa103, 0xf7e1, 0xba4e, 0xba4f, 0xae11, 0xe056,
+    0xba4f, 0xae21, 0xe056, 0xba4f, 0xae31, 0xe056, 0x3c17, 0x3c34,
+    0xba4e, 0xba4f, 0xae11, 0xe056, 0xba4f, 0xae21, 0xe056, 0xba4f,
+    0xae31, 0xe056, 0x3c16, 0x3c33, 0xa200, 0x2a3c, 0xe003, 0x00c5,
+    0xb636, 0x3c3c, 0xa100, 0xe40a, 0x103a, 0xba4e, 0xba4f, 0xae11,
+    0xe056, 0xba4f, 0xae21, 0xe056, 0xba4f, 0xae31, 0xe056, 0xe049,
+    0xa118, 0xf06a, 0xf287, 0xba4e, 0xa103, 0xf7e1, 0xf24e, 0xba44,
+    0x3c11, 0xba40, 0xba46, 0xba4e, 0xba4f, 0xae11, 0xe056, 0xba4f,
+    0xae21, 0xe056, 0xe161, 0x0658, 0x3511, 0x3d11, 0xba4e, 0xba4f,
+    0xae11, 0xe056, 0xba4f, 0xae21, 0xe056, 0xba4f, 0xae31, 0xe056,
+    0xe161, 0x0618, 0x3511, 0x3d11, 0xba4e, 0xba4e, 0xba4e, 0xba4e,
+    0xf02e, 0xe16b, 0xe42e, 0xe161, 0x0618, 0xe162, 0x0658, 0xba48,
+    0x3c27, 0xf156, 0xa102, 0xcc44, 0xba46, 0xa00c, 0x3c00, 0xba46,
+    0xa008, 0x3c01, 0xe184, 0x1055, 0xba5e, 0xa002, 0x5800, 0x3511,
+    0x3d11, 0xba5e, 0xa002, 0x5801, 0x3512, 0x3d12, 0xe42e, 0xba42,
+    0xa102, 0x3c10, 0xba44, 0x3c11, 0xba42, 0x3c12, 0xba44, 0x3c13,
+    0xba48, 0x3c14, 0xba40, 0x3c15, 0xba56, 0xa002, 0xae02, 0x3c16,
+    0x3c53, 0xba56, 0xa002, 0xae02, 0x3c17, 0x3c54, 0xba40, 0x3c18,
+    0xba40, 0x3c19, 0xba40, 0x3c1a, 0xba40, 0x3c1b, 0xba40, 0xba40,
+    0x3c1c, 0xa200, 0x3c43, 0x3c45, 0xa202, 0x3c44, 0x3c46, 0xa200,
+    0x3c21, 0x3c22, 0xba40, 0xe40a, 0x10c0, 0xba5a, 0xa002, 0x3c1d,
+    0xba5a, 0xa002, 0x3c1e, 0xba40, 0xf15a, 0xba46, 0xe049, 0xa11f,
+    0xf069, 0xba4e, 0x3c1f, 0xba4e, 0x3c20, 0xf0ce, 0xe049, 0xe000,
+    0x05f0, 0xe098, 0xe001, 0x0600, 0xe09b, 0x2904, 0x3c1f, 0x2905,
+    0x3c20, 0xba40, 0xf16a, 0xba40, 0xf0f8, 0xba4e, 0xa80e, 0xe000,
+    0x0610, 0xe098, 0x2904, 0x3c21, 0xe004, 0x03e8, 0xba47, 0xa103,
+    0xb422, 0x3c22, 0xf06e, 0xba5e, 0xa002, 0x3c21, 0xa240, 0x3c22,
+    0xba40, 0xf07a, 0xba4e, 0x3c23, 0xba4e, 0x3c24, 0xba4e, 0x3c25,
+    0xba40, 0x3c26, 0xe418, 0x103b, 0xe42e, 0x2810, 0xf0c4, 0xa104,
+    0xf0a0, 0x2816, 0xf086, 0x18a2, 0xf060, 0x2817, 0xf046, 0x18a3,
+    0xf020, 0xf08e, 0xa204, 0x3c10, 0x28a2, 0x3c16, 0x28a3, 0x3c17,
+    0xe16b, 0xe42e, 0xe161, 0x0658, 0xe162, 0x0698, 0x2827, 0xf126,
+    0xa102, 0xcc44, 0xe184, 0x10f0, 0xba4e, 0xa002, 0x3c00, 0x8400,
+    0x8311, 0xe018, 0xae20, 0x8400, 0x8311, 0xe019, 0xe042, 0xaf10,
+    0x3d12, 0xe42e, 0xba40, 0x3c28, 0xba40, 0x3c29, 0xba40, 0x3c2a,
+    0xba40, 0x3c2b, 0xba40, 0x3c2c, 0xba40, 0x3c2d, 0xba40, 0x3c2e,
+    0xba42, 0x3c2f, 0xba40, 0x3c30, 0xba40, 0x3c31, 0xba42, 0x3c32,
+    0x2826, 0xe418, 0x10da, 0x2816, 0x3c33, 0x2817, 0x3c34, 0xba40,
+    0xf09a, 0xba56, 0xa002, 0xae02, 0x3c33, 0xba56, 0xa002, 0xae02,
+    0x3c34, 0xa200, 0x3c35, 0x282e, 0xf03a, 0xba40, 0x3c35, 0xa200,
+    0x3c37, 0xba40, 0x3c36, 0xf03a, 0xba44, 0x3c37, 0xa200, 0x3c39,
+    0xba40, 0x3c38, 0xe42a, 0xba44, 0x3c39, 0xe42e, 0x2833, 0xf086,
+    0x1816, 0xf060, 0x2834, 0xf046, 0x1817, 0xf020, 0xf06e, 0x2816,
+    0x3c33, 0x2817, 0x3c34, 0xe16b, 0xe42e, 0xa200, 0x3c51, 0x3c52,
+    0x3c57, 0x3c6b, 0xe41e, 0x11c7, 0xd039, 0x0000, 0xa208, 0x3c4b,
+    0x3c4c, 0x2041, 0x4c42, 0xa102, 0xe426, 0xe16a, 0xe41e, 0x11e1,
+    0xe42d, 0xe41e, 0x1326, 0xe42e, 0xa200, 0x3c51, 0x3c52, 0x3c57,
+    0x3c6b, 0xe16a, 0xe41e, 0x123e, 0xe42d, 0x284b, 0xa108, 0xe418,
+    0x12e1, 0xe42d, 0x284a, 0xa106, 0xf048, 0x284e, 0xe016, 0x3c52,
+    0xe41e, 0x1326, 0xe42e, 0x284e, 0x3c52, 0xa200, 0x3c57, 0x3c6b,
+    0xe16a, 0xe41e, 0x12e1, 0xe42d, 0xe41e, 0x1326, 0xe42e, 0x2851,
+    0x2a56, 0xb615, 0xba50, 0xe046, 0x3c57, 0xba40, 0xe42a, 0xa200,
+    0x3c6b, 0xe162, 0x004a, 0xe163, 0x0510, 0xd022, 0x0038, 0xe184,
+    0x118a, 0x2912, 0x3d13, 0xe16a, 0xe41e, 0x123e, 0xf0dd, 0x284b,
+    0xa108, 0xe418, 0x12e1, 0xf08d, 0xe41e, 0x133b, 0xf05d, 0xe41e,
+    0x1326, 0xf02d, 0xe42e, 0xe162, 0x0510, 0xe163, 0x004a, 0xd022,
+    0x0038, 0xe184, 0x11a4, 0x2912, 0x3d13, 0xe42e, 0x283e, 0xf1ea,
+    0xba40, 0xf1c8, 0xe41e, 0x06ab, 0xa200, 0xba4f, 0xae10, 0xe056,
+    0xba4f, 0xae10, 0xe056, 0xe002, 0x00aa, 0xf0ba, 0xa102, 0xf03a,
+    0xa200, 0xe42e, 0xba4e, 0xba4e, 0xba4e, 0xba4e, 0xba4e, 0xba4e,
+    0xba4e, 0xba4e, 0xba4e, 0xba4e, 0xba4e, 0xa202, 0xe42e, 0xe41e,
+    0x06ab, 0xba4e, 0xba4f, 0xae11, 0xe056, 0xba4f, 0xae21, 0xe056,
+    0x3441, 0x3c42, 0xba4e, 0x283c, 0xa102, 0xe428, 0xba4e, 0xba4f,
+    0xae11, 0xe056, 0xba4f, 0xae21, 0xe056, 0xba4f, 0xae31, 0xe056,
+    0xe42e, 0x281b, 0xf02a, 0xba40, 0xba42, 0xa200, 0x2a3f, 0xf03b,
+    0xba40, 0x3c5c, 0x2a40, 0xf039, 0xba40, 0xf02e, 0xb800, 0x3c4b,
+    0x3c4c, 0xa106, 0xf088, 0xb808, 0x3c5d, 0xa12c, 0xf048, 0xa204,
+    0x3c4b, 0x3c4c, 0xe004, 0x004b, 0x0851, 0xe092, 0x2901, 0x3c85,
+    0x2861, 0x2a85, 0xa803, 0xb636, 0x2a85, 0xa103, 0xb436, 0xa802,
+    0x3c61, 0x2885, 0xa802, 0xf028, 0xba4c, 0xe41e, 0x1351, 0xa200,
+    0x2a2e, 0xf02b, 0xb804, 0x3c62, 0x2885, 0xa804, 0xf068, 0xa200,
+    0x2a3d, 0xf02b, 0xba42, 0x3c5b, 0x2833, 0x2a5b, 0xa803, 0xf03b,
+    0xa002, 0xaf02, 0x3c53, 0xa01e, 0xaf08, 0x3c55, 0x2834, 0x2a5b,
+    0xa805, 0xf03b, 0xa002, 0xaf02, 0x3c54, 0xa01e, 0xaf08, 0x3c56,
+    0xe41e, 0x13b8, 0xe41e, 0x1416, 0xe41e, 0x1460, 0xe41e, 0x14b7,
+    0xa202, 0x3c4e, 0xa200, 0x3c5f, 0x3c60, 0xe42e, 0xa200, 0x2a19,
+    0xf02b, 0xb80a, 0x3c4a, 0xa106, 0xf05a, 0xb802, 0x3c4b, 0x3c4c,
+    0xf0ee, 0xba44, 0xae02, 0x3c4c, 0xe004, 0xaf50, 0x5c4c, 0xa806,
+    0x3c4b, 0xe004, 0xbb44, 0x5c4c, 0xa806, 0x3c4c, 0x284b, 0xa108,
+    0xf05a, 0x281a, 0xf03a, 0xba4e, 0x3c4d, 0xa200, 0x3c50, 0x3c4f,
+    0xa202, 0x3c4e, 0x2818, 0xf0ca, 0x2819, 0xf08a, 0x281c, 0xf068,
+    0xba40, 0x3c4e, 0xba40, 0x3c4f, 0xf03e, 0xba42, 0x3c50, 0x282a,
+    0xf28a, 0xa202, 0x2a19, 0xb616, 0x2a1c, 0xb612, 0xa002, 0x3c47,
+    0x2850, 0x084f, 0x2a18, 0xb616, 0x0847, 0x3c47, 0xba40, 0xf19a,
+    0xe161, 0x06b8, 0xe162, 0x06c4, 0xe163, 0x06d0, 0xe164, 0x06d6,
+    0x2847, 0xf0f6, 0xa102, 0xcc44, 0xe184, 0x1297, 0xba62, 0x3511,
+    0x3d11, 0xba62, 0x3512, 0x3d12, 0xba5a, 0x3d13, 0xba5a, 0x3d14,
+    0x284b, 0xa108, 0xe42a, 0xe004, 0x004b, 0x0851, 0xe092, 0x2901,
+    0x3c85, 0xba40, 0x3c61, 0xa200, 0x2a19, 0xf02b, 0xba40, 0x3c58,
+    0x2a1b, 0x284a, 0xa100, 0xb611, 0xa200, 0xf02b, 0xba40, 0x3c59,
+    0x284a, 0xa100, 0x2a85, 0xa107, 0xb632, 0xf07a, 0x284a, 0xa106,
+    0x2a85, 0xa805, 0xb636, 0xf038, 0xb808, 0x3c5d, 0x282b, 0x2a4a,
+    0xa107, 0xb612, 0x2a85, 0xa805, 0xb612, 0xf0ca, 0xba42, 0xe049,
+    0xa107, 0xf079, 0xba41, 0xf05b, 0xa002, 0xe049, 0xa121, 0xf7b7,
+    0x3c5e, 0x2833, 0x3c53, 0xa01e, 0xaf08, 0x3c55, 0x2834, 0x3c54,
+    0xa01e, 0xaf08, 0x2a4a, 0xa107, 0xf039, 0xa002, 0xaf02, 0x3c56,
+    0xe42e, 0xe004, 0x004b, 0x0851, 0xe092, 0x2901, 0x3c85, 0xe41e,
+    0x1351, 0xa200, 0x2a15, 0xf02b, 0xba42, 0x3c5a, 0x284a, 0xa104,
+    0x2a85, 0xa107, 0xb632, 0xf038, 0xb808, 0x3c5d, 0xa200, 0x3c5f,
+    0x3c60, 0x284a, 0xa106, 0xf118, 0x2885, 0xa102, 0xf09a, 0x2885,
+    0xa106, 0xf0b8, 0xa202, 0x3c5f, 0xa200, 0x3c60, 0xf06e, 0xba40,
+    0x3c5f, 0xf038, 0xba40, 0x3c60, 0x2885, 0xa802, 0xf0ea, 0xa200,
+    0x2a2e, 0xf02b, 0xb804, 0x3c62, 0x2a35, 0x284a, 0xa100, 0xb615,
+    0xa200, 0xf02b, 0xb804, 0x3c63, 0xe41e, 0x13b8, 0xe41e, 0x1416,
+    0xe42d, 0xe41e, 0x1460, 0xe41e, 0x14b7, 0xe42e, 0x287b, 0xf026,
+    0xf05e, 0xa202, 0x3c7b, 0x3c7c, 0xe16b, 0xf0cd, 0x283c, 0xa104,
+    0xf08a, 0x2041, 0x4c42, 0xe005, 0x0030, 0xae21, 0xe046, 0xf022,
+    0xf02e, 0xe16b, 0xe42e, 0xe162, 0x0510, 0x284a, 0x1912, 0xf108,
+    0xe162, 0x0519, 0x2853, 0x1912, 0xf0b8, 0x2854, 0x1912, 0xf088,
+    0x2855, 0x1912, 0xf058, 0x2856, 0x1912, 0xf028, 0xf02e, 0xe16b,
+    0xe42e, 0xba49, 0x3e7a, 0xa111, 0xa200, 0xf021, 0xba40, 0x3c7d,
+    0x287a, 0x2a32, 0xa101, 0xf0a9, 0x2a7a, 0xa111, 0xf077, 0x2a7a,
+    0xa139, 0xb5ae, 0xf037, 0xae02, 0xa13e, 0x3c7b, 0x3c7c, 0x2a32,
+    0xa105, 0xf0c3, 0xa003, 0xf073, 0xa200, 0x2a7a, 0xa111, 0xb62e,
+    0x3c7e, 0xe42e, 0xba40, 0x3c7e, 0xe42e, 0x2832, 0xa802, 0x3c7e,
+    0xe42e, 0xa200, 0x3c7f, 0xa206, 0x3c80, 0xa202, 0x3c82, 0x2a2f,
+    0xa803, 0xf059, 0x2a2f, 0xa805, 0xf259, 0xe42e, 0xba40, 0xe42a,
+    0x3c7f, 0xba42, 0x3c80, 0xf09a, 0xa102, 0xf0aa, 0xa102, 0xf11a,
+    0xba40, 0x3c82, 0xe42a, 0xf1ce, 0xa21e, 0x3c81, 0xf19e, 0xba42,
+    0xae04, 0x3c81, 0xe004, 0x936c, 0x5c81, 0xa81e, 0x3c81, 0xf10e,
+    0xba42, 0xae04, 0x3c81, 0xe004, 0x1248, 0x5c81, 0xa81e, 0x3c81,
+    0xf07e, 0xa202, 0x3c7f, 0xa200, 0x3c80, 0xa21e, 0x3c81, 0xba44,
+    0xe049, 0xa10f, 0x087b, 0xa002, 0xf029, 0xba48, 0x3c7c, 0xe42e,
+    0xa200, 0xe162, 0x0065, 0xc705, 0x3d12, 0xa202, 0x2a85, 0xa103,
+    0xf05b, 0x2a85, 0xa107, 0xf1cb, 0xf33e, 0x2a4a, 0xa105, 0xf059,
+    0xba41, 0xa202, 0xb672, 0xf2ce, 0xa208, 0x2a7b, 0xa119, 0xb60e,
+    0x3c64, 0xb80e, 0xe049, 0xaf05, 0x3e65, 0xf02b, 0xb810, 0x0864,
+    0xae02, 0x3c64, 0xe004, 0xe42d, 0x5c64, 0xa806, 0xf19e, 0x2a4a,
+    0xa101, 0xf05b, 0x2a4a, 0xa107, 0xf06b, 0xf12e, 0xba41, 0xa200,
+    0xb632, 0xf0ee, 0xa208, 0x2a7b, 0xa119, 0xb60e, 0x3c64, 0xb810,
+    0x0864, 0xae02, 0x3c64, 0xe004, 0xe42d, 0x5c64, 0xa806, 0x3c64,
+    0x284a, 0xa104, 0x2a85, 0xa803, 0xb636, 0xf038, 0xba40, 0x3c65,
+    0x2865, 0xe42a, 0x284a, 0xa106, 0xf058, 0xb836, 0x3068, 0xaf02,
+    0x3065, 0x2865, 0xf05a, 0xba4a, 0x3c66, 0xba4a, 0x3c67, 0x2868,
+    0xf05a, 0xba4a, 0x3c69, 0xba4a, 0x3c6a, 0xe42e, 0xa200, 0x3c6d,
+    0x3c6e, 0x3c6f, 0xc411, 0xe162, 0x006f, 0x2a4a, 0xa101, 0x2885,
+    0xa102, 0xb631, 0x2864, 0xa106, 0xb631, 0xe41b, 0x15f3, 0xe42d,
+    0xc411, 0xe162, 0x006f, 0x2a4a, 0xa107, 0x2885, 0xa106, 0xb631,
+    0xe41b, 0x15f3, 0xe42d, 0xc411, 0xe162, 0x006f, 0x2a4a, 0xa107,
+    0x2885, 0xa106, 0xb611, 0xe419, 0x15f3, 0xe42d, 0xc409, 0xe162,
+    0x006e, 0x2a4a, 0xa107, 0x2885, 0xa802, 0xb615, 0xe419, 0x15f3,
+    0xe42d, 0xc411, 0xe162, 0x006f, 0x2a4a, 0xa105, 0x2885, 0xa802,
+    0xb631, 0xe41b, 0x15f3, 0xe42d, 0xc409, 0xe162, 0x006e, 0x2a10,
+    0xa105, 0x2885, 0xa802, 0xb631, 0xe41b, 0x15f3, 0xe42d, 0xe42e,
+    0xe004, 0x0024, 0x3c74, 0x2885, 0xa802, 0xe42a, 0x284a, 0xa104,
+    0xf05a, 0x284a, 0xa106, 0xf0aa, 0xf11e, 0xba42, 0xe000, 0x0051,
+    0x2a64, 0xa107, 0xb492, 0x3c70, 0xf09e, 0xba44, 0xe000, 0x0041,
+    0x2a64, 0xa107, 0xb492, 0xb492, 0x3c70, 0xa202, 0x2a4a, 0xa101,
+    0xf07b, 0x2a5f, 0xf091, 0xba42, 0xe000, 0x003d, 0xf08e, 0xba42,
+    0xe000, 0x0031, 0xf04e, 0xba44, 0xe000, 0x0035, 0x3c73, 0x2a4a,
+    0xa101, 0xf05b, 0xba44, 0xe000, 0x0029, 0xf04e, 0xba42, 0xe000,
+    0x0025, 0x3c74, 0x2a4a, 0xa105, 0x2885, 0xa802, 0xb635, 0xa200,
+    0xf049, 0xba42, 0xe000, 0x0020, 0x3c71, 0x284a, 0xa104, 0x2a85,
+    0xa107, 0xb632, 0xf08a, 0x2a4a, 0xa101, 0x2864, 0xa106, 0xb611,
+    0xa200, 0xf04b, 0xba42, 0xe000, 0x001c, 0x3c72, 0xe42e, 0xa200,
+    0x3c7f, 0x2885, 0xa802, 0xf0fa, 0x282f, 0xe418, 0x1379, 0xa202,
+    0x3c75, 0xa200, 0x3c76, 0x2830, 0xf06a, 0xba40, 0x3c75, 0xf03a,
+    0xba42, 0x3c76, 0xa200, 0x3c6c, 0x2831, 0xf17a, 0x2885, 0xa106,
+    0xf14a, 0xa204, 0x2a7b, 0xa113, 0xf083, 0x2810, 0xa104, 0x2a85,
+    0xa803, 0xb632, 0xf0a8, 0xb80c, 0x3c6c, 0xc401, 0xe162, 0x006d,
+    0xa106, 0xe41a, 0x15f3, 0xe42d, 0x2843, 0x2a85, 0xa803, 0xb612,
+    0xf02a, 0xba40, 0x3c83, 0x2a83, 0x2885, 0xa802, 0xb636, 0x4445,
+    0xf02a, 0xba40, 0x3c84, 0xe004, 0x005d, 0x3c78, 0x3c79, 0x2884,
+    0xf198, 0x287a, 0xa110, 0xa203, 0xb601, 0xb806, 0xb611, 0xb472,
+    0xe000, 0x005d, 0x3c78, 0x3c79, 0x2885, 0xa802, 0xf0b8, 0x287a,
+    0xa110, 0xa203, 0xb601, 0xb806, 0xb611, 0xb472, 0xe000, 0x005d,
+    0x3c79, 0xba40, 0xe000, 0x0059, 0x3c77, 0x2810, 0xa104, 0x2a85,
+    0xa803, 0xb632, 0x2a2f, 0xb636, 0xe41a, 0x1379, 0xe42e, 0x2857,
+    0xae10, 0x4c55, 0xae10, 0x4c56, 0xcf24, 0xcf44, 0xcfc6, 0xcf04,
+    0xa200, 0x4c46, 0xae02, 0x4c84, 0xae04, 0x4c10, 0xae02, 0x4c2d,
+    0xae04, 0x4c4a, 0xae04, 0xe005, 0x004b, 0x0a51, 0xe093, 0x4d01,
+    0xae02, 0x4c51, 0xae02, 0x4c52, 0xae04, 0x4c6c, 0xae02, 0x4c75,
+    0xae02, 0x4c5f, 0xae02, 0x4c60, 0xae04, 0x4c64, 0xae04, 0x4c62,
+    0xae04, 0x4c63, 0xae0a, 0x4c5d, 0xae0a, 0x4c5e, 0xcf46, 0xcfc8,
+    0xcf06, 0xa200, 0x4c46, 0xae02, 0x4c84, 0xae02, 0x2a7a, 0xa111,
+    0xb42e, 0xae04, 0x4c7f, 0xae04, 0x4c80, 0xae08, 0x4c81, 0xae02,
+    0x4c82, 0xae02, 0x4c75, 0xae04, 0x4c76, 0xae0a, 0x4c7b, 0xae0a,
+    0x4c7c, 0xae02, 0x4c7d, 0xae02, 0x4c7e, 0xae02, 0x2a77, 0xe003,
+    0x0059, 0xe056, 0xae04, 0x2a78, 0xe003, 0x005d, 0xe056, 0xae04,
+    0x2a79, 0xe003, 0x005d, 0xe056, 0xcf48, 0xcf64, 0xa200, 0x2a70,
+    0xe003, 0x0041, 0xa83f, 0xe056, 0xae08, 0x2a74, 0xe003, 0x0024,
+    0xa81f, 0xe056, 0xae04, 0x2a72, 0xe003, 0x001c, 0xa807, 0xe056,
+    0xae04, 0x2a71, 0xe003, 0x0020, 0xa807, 0xe056, 0xae08, 0x2a73,
+    0xe003, 0x0031, 0xa81f, 0xe056, 0xcf4a, 0xe0c1, 0x0041, 0xe004,
+    0x0000, 0xae10, 0xe042, 0x2ab8, 0xa803, 0xf05b, 0xe161, 0x0550,
+    0x2111, 0x4d11, 0x4c6d, 0xcf4c, 0xcf1a, 0xe0c1, 0x0041, 0xe004,
+    0x0010, 0xae10, 0xe042, 0x2ab8, 0xa803, 0xf07b, 0xe161, 0x0550,
+    0x2111, 0x4d11, 0x2ae2, 0xe042, 0x4c6e, 0xcf4e, 0xcf1c, 0xe0c1,
+    0x0041, 0xe004, 0x0020, 0xae10, 0xe042, 0x2ab8, 0xa803, 0xf08b,
+    0xe161, 0x0550, 0x2111, 0x4d11, 0x2ae2, 0xe042, 0xe042, 0x4c6f,
+    0xcf50, 0xcf1e, 0xe0c1, 0x0041, 0xe004, 0x0030, 0xae10, 0xe042,
+    0x2ab8, 0xa803, 0xf09b, 0xe161, 0x0550, 0x2111, 0x4d11, 0x2ae2,
+    0xe042, 0xe042, 0xe042, 0xcf00, 0xe165, 0x07c0, 0x2115, 0x4d15,
+    0xcf02, 0xe004, 0x0033, 0x2ab7, 0xa803, 0xb616, 0xcf14, 0x2053,
+    0x4c54, 0xcfc4, 0xe42e, 0xe082, 0xa104, 0xe400, 0x1634, 0x2855,
+    0xae10, 0x4c56, 0xcf24, 0xd190, 0x0100, 0xcb20, 0xcb23, 0xe409,
+    0x1634, 0xf7c8, 0xcb26, 0x3d02, 0xa100, 0xe42a, 0xa202, 0x3c6b,
+    0xe41e, 0x1a80, 0xca28, 0xf7f8, 0xe083, 0xa103, 0xa200, 0xb486,
+    0xb482, 0xae04, 0xe000, 0x0000, 0xae10, 0xe0c1, 0x0041, 0xe042,
+    0x2ab8, 0xa803, 0xf0db, 0xe083, 0xa103, 0xa200, 0xf045, 0x08e2,
+    0xf027, 0x08e2, 0xe163, 0x0550, 0x2313, 0x4f13, 0xe042, 0xce20,
+    0xd111, 0x0100, 0x28e1, 0xce24, 0x28b7, 0xa802, 0xae0a, 0xa904,
+    0xce26, 0xca28, 0xf7f8, 0xe42e, 0xd191, 0x0000, 0xe16b, 0xe42e,
+    0xe41e, 0x165a, 0xe41e, 0x16ad, 0xe41e, 0x175d, 0x2857, 0xe428,
+    0xa202, 0xe0c2, 0x0106, 0x2a4a, 0xa105, 0xe017, 0xae15, 0xa921,
+    0xe167, 0x0ba7, 0x3f17, 0xe41e, 0x1c1b, 0xe42e, 0xe0c0, 0x0111,
+    0xf7e8, 0xe0c0, 0x0065, 0xaf18, 0xa802, 0xf04a, 0xe0c0, 0x0281,
+    0xf7ea, 0xe42e, 0x2810, 0xae08, 0xa902, 0xe0c2, 0x0100, 0xe004,
+    0x00d6, 0xe0c2, 0x017c, 0xe004, 0x0014, 0xe0c2, 0x017d, 0x2055,
+    0x4c56, 0xae08, 0x2a4b, 0xa109, 0xf06b, 0x2a10, 0xa105, 0xf039,
+    0x2053, 0x4c54, 0xe0c2, 0x0101, 0x2a53, 0xa01f, 0xaf09, 0xae29,
+    0x2854, 0xa01e, 0xaf08, 0xae08, 0xe056, 0xe0c2, 0x0283, 0xe0c0,
+    0x0044, 0xa80e, 0xae1a, 0x4cb4, 0xe0c2, 0x0102, 0xe0c1, 0x0041,
+    0xe004, 0x0050, 0xae10, 0xe042, 0x2ab8, 0xa805, 0xf05b, 0xe161,
+    0x0552, 0x2111, 0x4d11, 0xe0c2, 0x0103, 0xe004, 0x004b, 0x0851,
+    0xe092, 0x2901, 0x2b01, 0xa809, 0xb632, 0xae04, 0x4c4a, 0xae02,
+    0x4c52, 0xe0c2, 0x0104, 0xa200, 0x2a6c, 0xa101, 0xb432, 0x2a4b,
+    0xa109, 0xb616, 0xe0c2, 0x0105, 0xe42e, 0xa200, 0xe0c2, 0x0320,
+    0x2a4b, 0xa109, 0xf2bb, 0xe165, 0x07d0, 0x2b15, 0xa803, 0xb452,
+    0x2b15, 0xa803, 0xb432, 0xae04, 0x2b15, 0xa803, 0xb452, 0x2b15,
+    0xa803, 0xb432, 0xae04, 0x2b15, 0xa803, 0xb452, 0x2b15, 0xa803,
+    0xb432, 0xae04, 0x2b15, 0xa803, 0xb452, 0x2b15, 0xa803, 0xb432,
+    0xae04, 0xc420, 0xe165, 0x07dc, 0x2b35, 0xaf0f, 0xa803, 0xb452,
+    0x2b35, 0xaf0f, 0xa803, 0xb432, 0xae04, 0x2a64, 0xb456, 0xa803,
+    0xb432, 0xae02, 0x4c61, 0xe0c2, 0x0303, 0xe165, 0x07d0, 0xe166,
+    0x0304, 0xd022, 0x0003, 0xe184, 0x16f3, 0x2915, 0xaf02, 0xae18,
+    0x2b15, 0xaf03, 0xe042, 0x9f16, 0xc420, 0xe165, 0x07dd, 0xa200,
+    0x2b35, 0xaf0d, 0xa807, 0xa101, 0xb673, 0xe042, 0x2b35, 0xaf0d,
+    0xa807, 0xa101, 0xb673, 0xae05, 0xe042, 0xe0c2, 0x0308, 0x2857,
+    0xe428, 0xa202, 0xe0c2, 0x0302, 0xe162, 0x0380, 0xe165, 0x07c8,
+    0x8505, 0x2905, 0xf042, 0xe165, 0x07c7, 0x8505, 0xc786, 0xe018,
+    0xe000, 0x0700, 0xe092, 0xd022, 0x0002, 0xe184, 0x1721, 0x2111,
+    0x4d11, 0x9f12, 0xe162, 0x0383, 0xe165, 0x07c9, 0x8505, 0x2905,
+    0xf042, 0xe165, 0x07c8, 0x8505, 0xf042, 0xe165, 0x07c7, 0x8505,
+    0xc786, 0xe018, 0xe000, 0x0700, 0xe092, 0xd022, 0x0002, 0xe184,
+    0x173b, 0x2111, 0x4d11, 0x9f12, 0xe162, 0x0386, 0xe165, 0x07c7,
+    0x8505, 0xc786, 0xe018, 0xe000, 0x0700, 0xe092, 0xd022, 0x0002,
+    0xe184, 0x174c, 0x2111, 0x4d11, 0x9f12, 0xa200, 0xe0c2, 0x0302,
+    0xa202, 0xae02, 0xa902, 0xe0c2, 0x0312, 0xa802, 0xe42a, 0x2851,
+    0xa002, 0xae08, 0xe0c2, 0x0313, 0xe42e, 0xa202, 0xae04, 0x2a10,
+    0xa807, 0xe056, 0xae04, 0xe005, 0x004b, 0x0a51, 0xe093, 0x2b01,
+    0xa807, 0xe056, 0xae04, 0x2a4a, 0xa807, 0xe056, 0xae02, 0x2a52,
+    0xa803, 0xe056, 0xe0c1, 0x0065, 0xaf19, 0xa803, 0xae17, 0xe056,
+    0xe0c2, 0x0204, 0xa204, 0x2a6c, 0xa101, 0xb612, 0x2a2c, 0xb612,
+    0x2a6c, 0xa101, 0xb492, 0x2a4b, 0xa109, 0xf029, 0xa204, 0xe0c2,
+    0x0208, 0xe0c1, 0x0041, 0xe004, 0x0090, 0xae10, 0xe042, 0x2ab8,
+    0xa821, 0xf05b, 0xe161, 0x0558, 0x2111, 0x4d11, 0xe0c2, 0x0209,
+    0xa204, 0x2a6c, 0xa101, 0xb612, 0x2a2c, 0xb612, 0x4c2c, 0x2a4b,
+    0xa109, 0xf029, 0xa204, 0xe0c2, 0x0210, 0xe0c1, 0x0041, 0xe004,
+    0x00e0, 0xae10, 0xe042, 0x2ab8, 0xa809, 0xf05b, 0xe161, 0x0554,
+    0x2111, 0x4d11, 0xe0c2, 0x0211, 0xe0c1, 0x0041, 0xe004, 0x00e0,
+    0xe000, 0x0080, 0xae10, 0xe042, 0x2ab8, 0xa811, 0xf05b, 0xe161,
+    0x0556, 0x2111, 0x4d11, 0xe0c2, 0x0212, 0xa200, 0xe0c2, 0x020a,
+    0xe0c2, 0x020b, 0xe0c2, 0x020c, 0xe165, 0x07c7, 0x8505, 0xc786,
+    0xe018, 0xe000, 0x0700, 0xe092, 0x2111, 0x4d11, 0xe0c2, 0x020d,
+    0xe0c2, 0x0214, 0x2111, 0x4d11, 0xe0c2, 0x020e, 0xe0c2, 0x0215,
+    0x2111, 0x4d11, 0xe0c2, 0x020f, 0xe0c2, 0x0216, 0xe42e, 0xe162,
+    0x07cb, 0xe163, 0x07e8, 0xe164, 0x07e9, 0xe165, 0x07ea, 0xa200,
+    0xa202, 0x2a9c, 0xb616, 0x2b03, 0xa819, 0xb616, 0x2b03, 0xa805,
+    0xb632, 0x2b02, 0xb60a, 0x3ca7, 0xe42a, 0xe004, 0x012c, 0xe0c2,
+    0x0140, 0x28b4, 0xe0c2, 0x0141, 0x2b03, 0xa805, 0xf03b, 0xe0c0,
+    0x0064, 0xe0c2, 0x014c, 0x2915, 0xe008, 0x7fff, 0xa01e, 0xaf08,
+    0x3ca8, 0x2915, 0xe008, 0x7fff, 0xa01e, 0xaf08, 0x3ca9, 0x84a8,
+    0x82a9, 0xe018, 0x3cad, 0xa200, 0x3caa, 0x3cab, 0x3cac, 0x28a8,
+    0xa102, 0xae20, 0x4ca9, 0xa102, 0xe0c2, 0x0142, 0x2903, 0xaf0e,
+    0xe0c2, 0x0149, 0x2904, 0xaf1e, 0xa802, 0xae08, 0x2b04, 0xaf15,
+    0xa81f, 0xe056, 0xe0c2, 0x014e, 0xe165, 0x07ce, 0x8505, 0xc786,
+    0xe018, 0xe000, 0x0700, 0xe092, 0x2111, 0x4d11, 0xe0c2, 0x0143,
+    0x2111, 0x4d11, 0xe0c2, 0x0144, 0x2111, 0x4d11, 0xe0c2, 0x0145,
+    0x2b03, 0xa805, 0xf169, 0xe165, 0x07cb, 0x8505, 0xc786, 0xe018,
+    0xe000, 0x0700, 0xe092, 0x2111, 0x4d11, 0xe0c2, 0x0146, 0x2111,
+    0x4d11, 0xe0c2, 0x0147, 0x2111, 0x4d11, 0xe0c2, 0x0148, 0xf0de,
+    0xe0c0, 0x0061, 0xe0c2, 0x0146, 0xe0c0, 0x0062, 0xe0c2, 0x0147,
+    0xe0c0, 0x0063, 0xe0c2, 0x0148, 0xe42e, 0x28a7, 0xe42a, 0xe41e,
+    0x1886, 0xf7e8, 0xe0c0, 0x014b, 0xf7e8, 0xa200, 0x28b3, 0xae04,
+    0xa904, 0xae0e, 0x4caa, 0xae0e, 0x4cab, 0xe0c2, 0x014d, 0xa202,
+    0xe0c2, 0x014a, 0xe0c0, 0x014b, 0xf7e8, 0xe42e, 0xa200, 0x2aac,
+    0x1aad, 0xe423, 0xe0c0, 0x014b, 0xf7e8, 0xa200, 0xe41e, 0x0ec4,
+    0x3cb3, 0xae02, 0x2aac, 0xb422, 0xae02, 0x2aac, 0x1aad, 0xb42a,
+    0xae0e, 0x4caa, 0xae0e, 0x4cab, 0xe0c2, 0x014d, 0xa202, 0xe0c2,
+    0x014a, 0xa202, 0x2aac, 0xa003, 0x3eac, 0x2aaa, 0xa003, 0x3eaa,
+    0x1aa8, 0xe425, 0xa201, 0x3eaa, 0x2aab, 0xa003, 0x3eab, 0x1aa9,
+    0xe425, 0xa200, 0xe42e, 0xe0c0, 0x0065, 0xaf10, 0xa802, 0xe418,
+    0x18c6, 0xe0c0, 0x0065, 0xaf0e, 0xa802, 0xe418, 0x18ee, 0xe0c0,
+    0x0065, 0xaf0c, 0xa802, 0xe418, 0x191e, 0xe42e, 0xca28, 0xf7f8,
+    0xe0c0, 0x006a, 0xce20, 0xd111, 0x0200, 0xd112, 0x0004, 0xd113,
+    0x0003, 0xca28, 0xf7f8, 0xe161, 0x0200, 0xe162, 0x055a, 0xa202,
+    0xae30, 0xa920, 0x3511, 0x3d11, 0x2111, 0x4d11, 0x3512, 0x3d12,
+    0xca28, 0xf7f8, 0xe0c0, 0x006a, 0xce20, 0xd111, 0x0200, 0xd112,
+    0x0004, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0xca28, 0xf7f8,
+    0xe0c0, 0x006a, 0xa010, 0xce20, 0xd111, 0x0200, 0xd112, 0x0004,
+    0xd113, 0x0003, 0xca28, 0xf7f8, 0xe161, 0x0200, 0xe162, 0x055c,
+    0xa204, 0xae10, 0x3d11, 0x8455, 0x8256, 0xe018, 0x2a4a, 0xa107,
+    0xf029, 0xae02, 0x3d11, 0x2111, 0x4d11, 0x3512, 0x3d12, 0xca28,
+    0xf7f8, 0xe0c0, 0x006a, 0xa010, 0xce20, 0xd111, 0x0200, 0xd112,
+    0x0004, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0xca28, 0xf7f8,
+    0xe0c0, 0x006a, 0xa020, 0xce20, 0xd111, 0x0200, 0xd112, 0x0004,
+    0xd113, 0x0003, 0xca28, 0xf7f8, 0xa200, 0x2a4b, 0x4e4c, 0xa803,
+    0xf09b, 0xa204, 0x2a4b, 0xa107, 0xf05b, 0x2a4c, 0xa107, 0xf02b,
+    0xa202, 0x3cda, 0xe161, 0x0200, 0xe162, 0x055e, 0xa208, 0xae10,
+    0x4cda, 0x3d11, 0x8455, 0x8256, 0xe018, 0x2a4a, 0xa107, 0xf029,
+    0xae02, 0x3d11, 0x2111, 0x4d11, 0x3512, 0x3d12, 0xca28, 0xf7f8,
+    0xe0c0, 0x006a, 0xa020, 0xce20, 0xd111, 0x0200, 0xd112, 0x0004,
+    0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0065, 0xaf10,
+    0xa802, 0xe42a, 0xe161, 0x0200, 0xe163, 0x07c3, 0xe164, 0x07c5,
+    0xa200, 0x3c01, 0xd022, 0x0007, 0xe184, 0x197f, 0xa200, 0xae08,
+    0x2313, 0x4f0b, 0x5e01, 0xa803, 0xb452, 0x2314, 0x4f0c, 0x5e01,
+    0xa803, 0xb492, 0x2a01, 0xa003, 0x3e01, 0xa807, 0xf719, 0x3d11,
+    0xe162, 0x07c7, 0x2902, 0xf0f4, 0xaf04, 0xe000, 0x0200, 0xe092,
+    0xa218, 0x2b02, 0xa807, 0xae05, 0xe046, 0x3c01, 0xa202, 0x5801,
+    0x4d01, 0x3d01, 0xca28, 0xf7f8, 0xe162, 0x055a, 0x2112, 0x4d12,
+    0xce20, 0xd111, 0x0200, 0xd112, 0x0008, 0xd113, 0x0002, 0xca28,
+    0xf7f8, 0xe42e, 0xe0c0, 0x0065, 0xaf0a, 0xa802, 0xe42a, 0xa200,
+    0x3cdb, 0x3cdc, 0x3cdd, 0xe162, 0x0200, 0x3d12, 0x3d12, 0x3d12,
+    0x3d12, 0xca28, 0xf7f8, 0xe0c0, 0x006b, 0xce20, 0xd111, 0x0200,
+    0xd112, 0x0004, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0xe0c0,
+    0x0065, 0xaf0a, 0xa802, 0xe42a, 0x2cdb, 0xa87e, 0xa120, 0xe422,
+    0xa200, 0xe41e, 0x1a19, 0x28c1, 0xf7ca, 0x20c4, 0x4cc3, 0xc871,
+    0xaf07, 0xe046, 0xf760, 0xa202, 0xe41e, 0x1a19, 0x2cdb, 0xa002,
+    0x3cdb, 0xe161, 0x0200, 0x28c0, 0x3d11, 0xc870, 0xaf06, 0x3d11,
+    0xa200, 0x3d11, 0x3d11, 0xc870, 0xaf16, 0xf09a, 0xa220, 0x3cdb,
+    0xe161, 0x0201, 0xa200, 0x3d11, 0x3d11, 0x3d11, 0xca28, 0xf7f8,
+    0xe0c0, 0x006b, 0x2edb, 0xa87f, 0xae07, 0xe042, 0xce20, 0xd111,
+    0x0200, 0xd112, 0x0004, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe161,
+    0x0200, 0x2cdb, 0xa87e, 0x3d11, 0x2cdc, 0x3d11, 0x2cdb, 0xaf10,
+    0x3d11, 0xa200, 0x3d11, 0xca28, 0xf7f8, 0xe0c0, 0x006b, 0xce20,
+    0xd111, 0x0200, 0xd112, 0x0004, 0xd113, 0x0002, 0xca28, 0xf7f8,
+    0xe42e, 0xf278, 0xe0c0, 0x006c, 0x1cdd, 0xf2c0, 0xe0c0, 0x0065,
+    0xaf14, 0xa802, 0xf068, 0xe0c0, 0x005c, 0xe008, 0x0200, 0xf098,
+    0xba4e, 0x2cdb, 0xa87e, 0xa203, 0xae11, 0xe042, 0x3cdb, 0xe42e,
+    0xe0c0, 0x005d, 0xe00a, 0x0200, 0xe0c2, 0x005d, 0xa202, 0xce00,
+    0xe0c0, 0x005d, 0xe008, 0x0200, 0xf7c8, 0xa200, 0x3cdd, 0xf0ae,
+    0x2cdd, 0xa80e, 0xe42a, 0x2cdd, 0xa00e, 0xaf06, 0xae06, 0x3cdd,
+    0xf20e, 0x2cdd, 0xa80e, 0xf088, 0xe161, 0x0200, 0xa200, 0x3d11,
+    0x3d11, 0x3d11, 0x3d11, 0x2cdd, 0xa80e, 0xaf02, 0xe000, 0x0200,
+    0xe092, 0x2cdd, 0xa802, 0xf058, 0xba4e, 0xae10, 0x3d11, 0xf04e,
+    0xba4e, 0x4d01, 0x3d11, 0x2cdd, 0xa002, 0x3cdd, 0xa80e, 0xe428,
+    0xca28, 0xf7f8, 0xe0c0, 0x006b, 0xe000, 0x0088, 0x2edd, 0xa103,
+    0xaf07, 0xae07, 0xe042, 0xce20, 0xd111, 0x0200, 0xd112, 0x0004,
+    0xd113, 0x0002, 0xca28, 0xf7f8, 0x2cdc, 0xa010, 0x3cdc, 0xe42e,
+    0x2855, 0xa01e, 0xaf08, 0x3c02, 0x8402, 0x8256, 0xe018, 0xa008,
+    0xaf04, 0xae04, 0x3ce1, 0xae02, 0xe049, 0xe003, 0x0100, 0xf063,
+    0xe005, 0x0100, 0xe004, 0x0200, 0xf06e, 0xe009, 0x00ff, 0xf03b,
+    0xe003, 0x0100, 0xe046, 0x3ce2, 0xe42e, 0x2887, 0xae10, 0x4c88,
+    0xcf52, 0xcfca, 0xcf08, 0xd18c, 0x0001, 0xd18b, 0x0000, 0xcb16,
+    0xf7f8, 0xd1e1, 0x0000, 0xcbc2, 0xf7f8, 0xe42e, 0xcb18, 0xf7f8,
+    0xd18b, 0x0001, 0xd1e1, 0x0001, 0xcb16, 0xcbc3, 0xf7e8, 0xf7d9,
+    0xe42e, 0xe41e, 0x1a9d, 0xf12d, 0xd1a0, 0x0001, 0xcb40, 0xcb43,
+    0xf0a9, 0xf7d8, 0xf08d, 0xcb54, 0xcf66, 0xcf0a, 0xcfd0, 0xcb56,
+    0xcf6c, 0xe42e, 0xd1a1, 0x0000, 0xe16b, 0xd1a0, 0x0000, 0xcb40,
+    0xf7f8, 0xf72e, 0xe42e, 0xf1dd, 0xd1b0, 0x0001, 0xe180, 0x28c7,
+    0xe41a, 0x05ab, 0xe181, 0xe41e, 0x1afd, 0xcb8a, 0xe41e, 0x0e3e,
+    0xe41e, 0x1b7e, 0xe41e, 0x1bbd, 0xcb60, 0xcb63, 0xf089, 0xf7d8,
+    0xf06d, 0xcb68, 0xcf0e, 0xcb6a, 0xcf10, 0xe42e, 0xd1e0, 0x0000,
+    0xe41e, 0x1afd, 0xd1b1, 0x0000, 0xa200, 0xcf0e, 0xcf10, 0xe0c0,
+    0x0124, 0xe0c2, 0x0124, 0xe16b, 0xe42e, 0xa200, 0xe0c2, 0x0113,
+    0xcb90, 0xe0c2, 0x030d, 0xcb88, 0xe0c2, 0x0114, 0xcb8a, 0xe0c2,
+    0x0115, 0xcb8c, 0xe0c2, 0x0130, 0x2888, 0x1857, 0x4c87, 0xe016,
+    0xe0c2, 0x0131, 0xcb8e, 0xe0c2, 0x012a, 0xcb82, 0xe0c2, 0x0221,
+    0xcb84, 0xe0c2, 0x0220, 0x287b, 0xe0c2, 0x022c, 0xcbd0, 0xf7f8,
+    0xcb92, 0xe0c2, 0x030f, 0xf0da, 0xcbd2, 0xe0c2, 0x0309, 0xcbd4,
+    0xe0c2, 0x030c, 0xcbd6, 0xe0c2, 0x030a, 0xcbd8, 0xe0c2, 0x030b,
+    0xe42e, 0xcb80, 0xe0c2, 0x0116, 0xcbda, 0xcf12, 0xe161, 0x0224,
+    0xd022, 0x0007, 0xd186, 0x0000, 0xe184, 0x1b3f, 0xcb86, 0x9f11,
+    0xe41e, 0x1aae, 0xe0c0, 0x0111, 0xf7e8, 0xa202, 0xe0c2, 0x0110,
+    0xe42e, 0x2895, 0xb43a, 0x3c95, 0x2896, 0xe42a, 0xf0fc, 0x2888,
+    0xae0e, 0x0887, 0xaf08, 0xe000, 0x0570, 0xe098, 0x2887, 0xa81e,
+    0x3c00, 0xa202, 0x5800, 0x4d04, 0x3d04, 0x2887, 0xa1aa, 0xe424,
+    0x2888, 0xa1ac, 0x2a88, 0xa80f, 0xa10f, 0xb636, 0xe424, 0xe0c0,
+    0x0042, 0x2a88, 0xaf07, 0xae0f, 0xe042, 0xca29, 0xf7f9, 0xce20,
+    0xd111, 0x0570, 0xd112, 0x0040, 0xd113, 0x0002, 0xca29, 0xf7f9,
+    0xe164, 0x0570, 0xa200, 0xc73f, 0x3d14, 0xe42e, 0xe0c0, 0x0065,
+    0xaf0e, 0xa802, 0xe42a, 0xa200, 0xf02c, 0xa204, 0x4cd7, 0xae0c,
+    0xcb8b, 0xa83f, 0xe056, 0x2ed8, 0xaf03, 0xa8ff, 0xe001, 0x0280,
+    0xe095, 0x2ed8, 0xa803, 0xf03b, 0x4d02, 0xf02e, 0xae10, 0x3d02,
+    0x2cd8, 0xa002, 0x3cd8, 0xe008, 0x00ff, 0xf09a, 0x2887, 0x1855,
+    0xa002, 0xe424, 0x2888, 0x1856, 0xa002, 0xe424, 0xe162, 0x055c,
+    0x2112, 0x4d12, 0x2ed8, 0xaf03, 0xa103, 0xb60b, 0xaf0f, 0xae11,
+    0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0280, 0xd112, 0x0080,
+    0xd113, 0x0002, 0xca29, 0xf7f9, 0xe42e, 0xe0c0, 0x0065, 0xaf0c,
+    0xa802, 0xe42a, 0x28da, 0xe42a, 0xa200, 0xcb55, 0xaf3d, 0xa803,
+    0xf0a9, 0xcbd5, 0xaf0d, 0xa803, 0xf06b, 0xe0c1, 0x03b0, 0xa202,
+    0xae3e, 0xe056, 0x2ed9, 0xaf03, 0xa8ff, 0xe001, 0x0300, 0xe095,
+    0x3512, 0x3d12, 0x2cd9, 0xa008, 0x3cd9, 0x2ada, 0xa103, 0xf1ab,
+    0xa200, 0xcb55, 0xaf3d, 0xa803, 0xf0a9, 0xcbd5, 0xaf0f, 0xa803,
+    0xf06b, 0xe0c1, 0x03c0, 0xa202, 0xae3e, 0xe056, 0x2ed9, 0xaf03,
+    0xa8ff, 0xe001, 0x0300, 0xe095, 0x3512, 0x3d12, 0x2cd9, 0xa008,
+    0x3cd9, 0xe008, 0x00ff, 0xf09a, 0x2887, 0x1855, 0xa002, 0xe424,
+    0x2888, 0x1856, 0xa002, 0xe424, 0xe162, 0x055e, 0x2112, 0x4d12,
+    0x2ed9, 0xaf03, 0xa103, 0xb60b, 0xaf0f, 0xae11, 0xe042, 0xca29,
+    0xf7f9, 0xce20, 0xd111, 0x0300, 0xd112, 0x0080, 0xd113, 0x0002,
+    0xca29, 0xf7f9, 0xe42e, 0xe0c0, 0x0065, 0xaf18, 0xa802, 0xe40a,
+    0x1c9d, 0xae0a, 0xe0c1, 0x0060, 0xaf0d, 0xa80f, 0xe056, 0xe0c1,
+    0x0044, 0xa811, 0xe056, 0xae0c, 0xe0c1, 0x0044, 0xa80f, 0xe056,
+    0xe167, 0x0ba7, 0x2f17, 0xe056, 0xe0c2, 0x0282, 0xe0c0, 0x006e,
+    0xe0c2, 0x0284, 0xaf20, 0xe0c1, 0x0282, 0xa809, 0xf04b, 0xe049,
+    0xae1f, 0xf06e, 0xe049, 0xa011, 0xaf09, 0xae07, 0xae21, 0xe056,
+    0xe0c2, 0x028c, 0xe167, 0x0ba8, 0x2d17, 0x4917, 0xe0c2, 0x0285,
+    0xe167, 0x0baa, 0x2d17, 0x4917, 0xe0c2, 0x0286, 0xe41e, 0x1c9e,
+    0xe0c0, 0x004a, 0xe0c2, 0x0289, 0xe0c0, 0x004b, 0xe0c2, 0x028a,
+    0xe0c0, 0x0055, 0xe0c2, 0x028b, 0xe0c1, 0x0041, 0xe004, 0x01e0,
+    0xae10, 0xe042, 0xe167, 0x0ba6, 0x2b17, 0xf05b, 0xe167, 0x0ba0,
+    0x2d17, 0x4917, 0xe0c2, 0x0287, 0xe0c1, 0x0041, 0xe004, 0x01f8,
+    0xae10, 0xe042, 0xe167, 0x0ba6, 0x2b17, 0xf05b, 0xe167, 0x0ba2,
+    0x2d17, 0x4917, 0xe0c2, 0x0288, 0xe0c1, 0x0041, 0xe004, 0x0200,
+    0xae10, 0xe042, 0xe167, 0x0ba6, 0x2b17, 0xf05b, 0xe167, 0x0ba4,
+    0x2d17, 0x4917, 0xe0c2, 0x028d, 0xe0c0, 0x0065, 0xaf18, 0xa802,
+    0xe0c2, 0x0280, 0xa210, 0xe0c2, 0x0168, 0xe42e, 0xe167, 0x0bac,
+    0xe165, 0x028e, 0xe166, 0x02c0, 0xd022, 0x0008, 0xe184, 0x1cb1,
+    0x2d17, 0x9f16, 0x9e85, 0xf7fb, 0x2517, 0x4d17, 0x9f16, 0x9e85,
+    0xf7fb, 0xe190, 0xe166, 0x02d2, 0xd022, 0x0008, 0xe184, 0x1cbd,
+    0x2517, 0x4d17, 0x9f16, 0x9e85, 0xf7fb, 0xe190, 0xe166, 0x02db,
+    0xd022, 0x0008, 0xe184, 0x1cc9, 0x2517, 0x4d17, 0x9f16, 0x9e85,
+    0xf7fb, 0xe190, 0xe166, 0x02e4, 0xd022, 0x0008, 0xe184, 0x1cd4,
+    0x2d17, 0x9f16, 0x9e85, 0xf7fb, 0xe190, 0xe42e, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0x0000, 0x0001, 0x000c, 0x000a, 0x0010, 0x0028, 0x0018, 0x0014,
+    0x0020, 0x0050, 0x0012, 0x000f, 0x0040, 0x00a0, 0x0000, 0x0000,
+    0x0000, 0x0001, 0x000b, 0x000b, 0x000b, 0x0021, 0x000b, 0x000b,
+    0x000b, 0x0021, 0x000b, 0x000b, 0x0021, 0x0063, 0x0000, 0x0000,
+    0x0000, 0x0018, 0x0019, 0x001e, 0x0032, 0x003c, 0x0030, 0x0048,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0xe40e, 0x0020, 0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x0131,
+    0xe470, 0xe190, 0xe40e, 0x0113, 0xe470, 0xe190, 0xe470, 0xe190,
+    0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+    0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x012f, 0xe40e, 0x0131,
+    0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058,
+    0xa200, 0xe0c2, 0x005a, 0x3cf0, 0x3cf1, 0xa2fe, 0x3cee, 0x3cef,
+    0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d, 0xce00, 0xf11e, 0xe0c0,
+    0x005c, 0xe0c1, 0x0059, 0x3eed, 0xa203, 0x5aed, 0xe052, 0xf08a,
+    0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00, 0xe41e,
+    0x008c, 0xe41e, 0x00ab, 0xe0c0, 0x005a, 0x18ee, 0xe0c1, 0x0059,
+    0xa115, 0xb636, 0x2aee, 0xb60a, 0xe418, 0x00fb, 0xe0c0, 0x005b,
+    0xe0c1, 0x005e, 0xae11, 0xe056, 0x18ef, 0xe0c1, 0x0059, 0xa117,
+    0xb636, 0xe418, 0x00b0, 0xe0c0, 0x005a, 0x18ee, 0x2aee, 0xb60a,
+    0xe0c1, 0x0059, 0xa117, 0xb636, 0xe418, 0x00f3, 0xd071, 0x802a,
+    0xe181, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100, 0xe0c0, 0x0059,
+    0xae02, 0xe000, 0x0113, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a,
+    0x3cee, 0xe41e, 0x0100, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11,
+    0xe056, 0x3cef, 0xe40e, 0x0037, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+    0x0058, 0xe0c2, 0x0008, 0xe0c0, 0x0059, 0xf7ea, 0xa11e, 0xf0e8,
+    0xa202, 0xe0c2, 0x0058, 0xe004, 0x093d, 0xe0c2, 0x0070, 0xa200,
+    0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xf6fe, 0xa202, 0xe0c2, 0x0008,
+    0xe0c2, 0x0058, 0xe42e, 0xd101, 0x0001, 0xc70f, 0xa000, 0xe42e,
+    0xa200, 0xe0c1, 0x005b, 0xf27b, 0xa220, 0xa103, 0xf2eb, 0xa230,
+    0xa103, 0xf2bb, 0xa23c, 0xa103, 0xf24b, 0xa258, 0xa103, 0xf25b,
+    0xa260, 0xa103, 0xf22b, 0xa200, 0xa103, 0xf1fb, 0xa26c, 0xa103,
+    0xf1cb, 0xe004, 0x003e, 0xa103, 0xf18b, 0xe004, 0x0044, 0xa105,
+    0xf14b, 0xe004, 0x0046, 0xa103, 0xf10b, 0xe004, 0x0000, 0xa107,
+    0xf0cb, 0xa200, 0xe0c1, 0x005e, 0xf08b, 0xe004, 0x004c, 0xf05e,
+    0xe0c1, 0x005e, 0xf02b, 0xa010, 0xae16, 0xe0c1, 0x0040, 0xe041,
+    0xca28, 0xf7f8, 0xce21, 0xd111, 0x0000, 0xd112, 0x2000, 0xd113,
+    0x000b, 0xe1e1, 0xe42e, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100,
+    0xe004, 0x0133, 0xe67c, 0xe41e, 0x0100, 0xe004, 0x0135, 0xe67c,
+    0x28ee, 0xe008, 0x03ff, 0xcca4, 0xe182, 0x0029, 0xe018, 0x2eee,
+    0xaf15, 0xcca5, 0xe182, 0x0029, 0xe019, 0xae15, 0xe042, 0xae14,
+    0x34f0, 0x3cf1, 0xe42e, 0xe40e, 0x0a5e, 0xe40e, 0x0137, 0xe40e,
+    0x013b, 0xe40e, 0x013f, 0xe40e, 0x0143, 0xe40e, 0x007e, 0xe40e,
+    0x0147, 0xe40e, 0x007e, 0xe40e, 0x014b, 0xe40e, 0x007e, 0xe40e,
+    0x007e, 0xe40e, 0x007e, 0xe40e, 0x007e, 0xe40e, 0x007e, 0xe40e,
+    0x007e, 0xe40e, 0x007e, 0xe40e, 0x042e, 0xe40e, 0x0444, 0xe41e,
+    0x014f, 0xe40e, 0x007e, 0xe41e, 0x01b7, 0xe40e, 0x007e, 0xe41e,
+    0x01b8, 0xe40e, 0x007e, 0xe41e, 0x0351, 0xe40e, 0x007e, 0xe41e,
+    0x04b3, 0xe40e, 0x007e, 0xe41e, 0x0387, 0xe40e, 0x007e, 0xd130,
+    0x0002, 0xa200, 0xe0c2, 0x0169, 0xe41e, 0x037d, 0xe41e, 0x04be,
+    0xe0c0, 0x0062, 0x3003, 0xaf04, 0x30b4, 0xaf02, 0x30b5, 0xe41e,
+    0x0a11, 0xe41e, 0x05b9, 0xf24a, 0x2852, 0xae20, 0x4c53, 0xe0c2,
+    0x0071, 0xe0c2, 0x004f, 0xe41e, 0x018c, 0xe0c2, 0x0072, 0x2825,
+    0xae10, 0x4c2e, 0xae10, 0x4c2d, 0xe0c2, 0x007b, 0x282f, 0xe0c2,
+    0x006c, 0xa208, 0x0803, 0xe0c2, 0x0073, 0xa202, 0x3caf, 0xe0c2,
+    0x0074, 0xe41e, 0x0b47, 0xa202, 0xe0c2, 0x0070, 0xe42e, 0xa200,
+    0x3ca0, 0xe0c2, 0x0070, 0xe42e, 0x2827, 0xe42a, 0xa231, 0xa102,
+    0xf21a, 0xa102, 0xf12a, 0xa102, 0xa003, 0xf0fa, 0xa102, 0xa00b,
+    0xf19a, 0xa102, 0xf0aa, 0xa102, 0xa029, 0xf07a, 0xa102, 0xa015,
+    0xf11a, 0xa102, 0xb7f0, 0xe428, 0x3e51, 0x2a29, 0xae21, 0x2828,
+    0xa002, 0x3c50, 0x8450, 0x8251, 0xe018, 0xe008, 0xffff, 0xe056,
+    0xe42e, 0xe004, 0x03e7, 0x3c28, 0xa002, 0x3c29, 0xf6ee, 0xe42e,
+    0xa2fe, 0xe0c2, 0x004c, 0xe0c2, 0x004d, 0xe0c2, 0x004e, 0xa200,
+    0xcc4a, 0xcc4c, 0x3c3b, 0x3cea, 0x3c85, 0x3ce4, 0xcc72, 0xe0c2,
+    0x007d, 0xe0c2, 0x007e, 0xe0c2, 0x007f, 0x3c4b, 0xe0c2, 0x007a,
+    0xa2fc, 0xe0c2, 0x0077, 0x3c12, 0xa2fa, 0xe0c2, 0x0071, 0xa202,
+    0xe0c2, 0x0076, 0xe0c0, 0x0065, 0xaf0a, 0xa81e, 0xf1ea, 0x30d9,
+    0xaf02, 0x30d8, 0xaf02, 0x30d7, 0xaf02, 0x30d6, 0xe0c0, 0x006c,
+    0xe002, 0x0088, 0x3ce6, 0xe0c0, 0x0065, 0xaf0c, 0xa80e, 0xf0da,
+    0xe0c0, 0x006a, 0xca29, 0xf7f9, 0xce20, 0xd112, 0x000c, 0xd111,
+    0x02f0, 0xd113, 0x0003, 0xe1e1, 0x28aa, 0xf10a, 0xa200, 0x3c0e,
+    0xe41e, 0x0a70, 0xa202, 0x3c0e, 0xe41e, 0x0a70, 0xa200, 0x3c0e,
+    0xd037, 0x0080, 0xe128, 0xa200, 0x3caa, 0x28b4, 0xf068, 0xe41e,
+    0x0b28, 0xe40a, 0x0258, 0xf07e, 0xe0c0, 0x0045, 0xaf04, 0xa802,
+    0xe40a, 0x0258, 0x28af, 0xf296, 0x2817, 0xf074, 0x2a15, 0x282a,
+    0xa104, 0xf02a, 0x2a16, 0x3e17, 0x28af, 0xa102, 0x3caf, 0x2221,
+    0x4e22, 0xa003, 0x3621, 0x3e22, 0xa202, 0x3c1c, 0x2817, 0xf074,
+    0xe0c0, 0x0060, 0xaf08, 0xa806, 0xe418, 0x03db, 0x28af, 0xf194,
+    0x2a03, 0x2814, 0xf02b, 0x2816, 0xe0c2, 0x0071, 0x3c17, 0xa200,
+    0xe0c2, 0x0072, 0xe40e, 0x0328, 0x28af, 0xf0b4, 0x2814, 0x2a03,
+    0xf02b, 0x2816, 0x3c17, 0xe0c1, 0x0060, 0xaf09, 0xa807, 0xf559,
+    0xa2fe, 0xe0c2, 0x0071, 0xa200, 0xe0c2, 0x0072, 0xe40e, 0x0328,
+    0x28b4, 0xf05a, 0xe41e, 0x09e8, 0xe40e, 0x025e, 0xa2fe, 0xe0c2,
+    0x0077, 0xe41e, 0x03ff, 0xe41e, 0x1090, 0xe42a, 0xa2fc, 0xe0c2,
+    0x0077, 0xd130, 0x0002, 0xd03a, 0x0002, 0xd04b, 0x0001, 0xd04c,
+    0x0000, 0xd008, 0x0000, 0x28a4, 0xe016, 0x4ca1, 0xe41a, 0x1058,
+    0x28a4, 0x3ca1, 0xe41e, 0x05eb, 0x2ab4, 0xf04b, 0x2a3b, 0xe409,
+    0x031f, 0xe40a, 0x0337, 0xe404, 0x021a, 0x28b4, 0xf26a, 0xe0c0,
+    0x0065, 0xa808, 0xe40a, 0x0295, 0x2840, 0xe408, 0x02fd, 0xa2fa,
+    0x3c15, 0xa200, 0x3c42, 0xe40e, 0x031f, 0xe0c0, 0x0065, 0xaf06,
+    0xa806, 0x3ca3, 0xe40a, 0x02fd, 0xa102, 0xf068, 0x2840, 0x4c49,
+    0xe408, 0x02fd, 0xf06e, 0xa102, 0xf048, 0x2842, 0xe40a, 0x02fd,
+    0xa2fa, 0x3c15, 0xe40e, 0x031f, 0x28a4, 0xf11a, 0x2848, 0xa102,
+    0xe016, 0x443b, 0x4c40, 0xf47a, 0x28a2, 0xe40a, 0x02fd, 0x2a32,
+    0x563b, 0x3e3b, 0xb5f6, 0x3ca2, 0xe40e, 0x027a, 0x28a3, 0xe40a,
+    0x02fd, 0xa102, 0xf04a, 0xa102, 0xf09a, 0xf0ae, 0x2848, 0xa102,
+    0xe016, 0x443b, 0x4c40, 0xf328, 0xf03e, 0x2842, 0xf2fa, 0x28a2,
+    0x2a32, 0x563b, 0x3e3b, 0xb5f6, 0xf04a, 0x3ca2, 0xe40e, 0x027a,
+    0xe41e, 0x03b7, 0x2834, 0xa106, 0xe01a, 0xae02, 0x4c25, 0xae02,
+    0x4c3c, 0xae06, 0x28d5, 0x2a34, 0xa103, 0xae04, 0x4c3e, 0xae02,
+    0x4c3a, 0xae02, 0x4c39, 0xae04, 0x4c3d, 0xae02, 0x4c32, 0xae24,
+    0xe056, 0xe0c2, 0x0073, 0xa204, 0xe0c2, 0x0075, 0x2800, 0xe0c2,
+    0x0072, 0xa2fa, 0xe0c2, 0x0071, 0xe42e, 0xe41e, 0x0ba6, 0xe40a,
+    0x0337, 0xe41e, 0x04d3, 0xd182, 0x0007, 0x2804, 0x4c05, 0xe418,
+    0x1015, 0xe0c0, 0x0111, 0xf7e8, 0xe0c0, 0x0065, 0xaf18, 0xa802,
+    0xf04a, 0xe0c0, 0x0281, 0xf7ea, 0x2832, 0x543b, 0x3c3b, 0x2ab4,
+    0xf05b, 0x283b, 0xe418, 0x03c4, 0x283b, 0xe408, 0x027a, 0xa200,
+    0xe41e, 0x0d8a, 0x2817, 0xf052, 0xa2fa, 0x3c17, 0xe0c2, 0x0071,
+    0x2852, 0xae20, 0x4c53, 0xe0c2, 0x006f, 0xe0c2, 0x004f, 0xe41e,
+    0x0417, 0x2817, 0x3c4e, 0xa202, 0xe0c2, 0x0076, 0xe42e, 0x2852,
+    0xae20, 0x4c53, 0xe0c2, 0x006f, 0xe0c2, 0x004f, 0x28a9, 0xf06a,
+    0xa2fa, 0xe0c2, 0x0071, 0xa200, 0x3ca9, 0xa2fa, 0x3c17, 0xe0c2,
+    0x0071, 0xe41e, 0x0d8a, 0xe41e, 0x0417, 0xa200, 0xe0c2, 0x0076,
+    0xe42e, 0xd130, 0x0002, 0xe41e, 0x0b8f, 0xe0c0, 0x0060, 0xe42a,
+    0xe0c0, 0x0060, 0x3c23, 0xca28, 0xf7f8, 0xe0c0, 0x0042, 0xce20,
+    0xd111, 0x0100, 0xd112, 0x00c4, 0xd113, 0x0003, 0xca28, 0xf7f8,
+    0xe0c0, 0x0042, 0xe000, 0x1000, 0xce20, 0xd111, 0x0ba8, 0xd112,
+    0x004c, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe0c0, 0x0061, 0x3c06,
+    0xaf02, 0x3c07, 0xe41e, 0x1058, 0xe42e, 0xa200, 0xc401, 0xe188,
+    0x07ff, 0x3d11, 0xcc72, 0xa2fe, 0x3421, 0x3c22, 0xe42e, 0xe0c0,
+    0x0060, 0xf08a, 0xe0c0, 0x0061, 0x2208, 0x4e09, 0xe046, 0xaf12,
+    0xae02, 0x3c0b, 0xa200, 0x3cae, 0xe180, 0xe41e, 0x0a51, 0xe41e,
+    0x0ac4, 0xe41e, 0x1058, 0xe166, 0x0054, 0x9e06, 0xf16a, 0x2823,
+    0xa102, 0xcc44, 0xa200, 0x3cb3, 0xe184, 0x03b2, 0x9e06, 0x5cb3,
+    0xa802, 0xf07a, 0x28b3, 0xe000, 0x02b0, 0xe09e, 0xa208, 0x3d07,
+    0x28b3, 0xa002, 0x3cb3, 0xe190, 0xa202, 0x3caa, 0xe42e, 0xe41e,
+    0x089c, 0xba2e, 0xa102, 0xe40a, 0x03bf, 0xba4e, 0xf7be, 0x2832,
+    0x543b, 0x3c3b, 0xf778, 0xe42e, 0xe0c0, 0x005c, 0xe008, 0x0400,
+    0xe42a, 0xe004, 0x0400, 0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d,
+    0xa202, 0xce00, 0xe0c0, 0x005d, 0xe008, 0x0400, 0xe190, 0xf7b8,
+    0xe41e, 0x09e8, 0xe42e, 0xa200, 0x3c3b, 0x3c58, 0x3c59, 0xe0c2,
+    0x0140, 0xe0c2, 0x0149, 0xe41e, 0x0fb3, 0xe41e, 0x0ec5, 0xa202,
+    0x3c95, 0xa203, 0xe41e, 0x0fef, 0xe41e, 0x100a, 0xf798, 0xa200,
+    0x3c95, 0xa201, 0xe41e, 0x0fef, 0xe0c1, 0x014b, 0xf7e9, 0x2818,
+    0xe000, 0x02d0, 0xe094, 0x2902, 0xa81c, 0x3d02, 0xe42e, 0xa200,
+    0x3cb1, 0x2823, 0xa102, 0xcc44, 0xe184, 0x0415, 0xe0c0, 0x0054,
+    0x5cb1, 0xa802, 0xf058, 0x28b1, 0xe41e, 0x10ad, 0xf05e, 0x28b1,
+    0xa209, 0xe41e, 0x10a6, 0x2ab1, 0xa003, 0x3eb1, 0xe42e, 0xe004,
+    0x02b0, 0xe09e, 0xe004, 0x0054, 0xe09c, 0x2823, 0xa102, 0xcc44,
+    0xa200, 0x3cb1, 0xe184, 0x042b, 0x2b17, 0xaf05, 0xa803, 0x5ab1,
+    0xe056, 0x2ab1, 0xa003, 0x3eb1, 0x9f06, 0xe42e, 0xe0c0, 0x005a,
+    0x3cee, 0xe41e, 0x0100, 0xa206, 0xe41e, 0x044d, 0xe0c0, 0x005a,
+    0x3cee, 0xe41e, 0x0100, 0xe0c0, 0x005b, 0x3cef, 0xa226, 0xe41e,
+    0x0463, 0xe41e, 0x047d, 0xe42e, 0xa224, 0xe41e, 0x0463, 0xe41e,
+    0x0498, 0xa204, 0xe41e, 0x044d, 0xe42e, 0x3ced, 0xe0c0, 0x0041,
+    0xe005, 0x0280, 0xae11, 0xe042, 0x22f0, 0x4ef1, 0xe042, 0xca29,
+    0xf7f9, 0xce20, 0xd111, 0x0000, 0xd112, 0x0c00, 0x88ed, 0x0113,
+    0xca28, 0xf7f8, 0xe42e, 0x2aef, 0xa80f, 0xa10d, 0xe42b, 0x3ced,
+    0xe0c0, 0x0041, 0xe005, 0x0298, 0xae11, 0xe042, 0x22f0, 0x4ef1,
+    0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0000, 0xd112, 0x0100,
+    0x88ed, 0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe161, 0x07e0, 0x8911,
+    0x0034, 0x8911, 0x0033, 0x8911, 0x0035, 0x8911, 0x0036, 0x8911,
+    0x0037, 0x8911, 0x0038, 0x2111, 0x4d11, 0xcc60, 0x2111, 0x4d11,
+    0xcc62, 0x2111, 0x4d11, 0xcc64, 0x2111, 0x4d11, 0xcc72, 0xe42e,
+    0xe161, 0x07e0, 0x8b11, 0x0034, 0x8b11, 0x0033, 0x8b11, 0x0035,
+    0x8b11, 0x0036, 0x8b11, 0x0037, 0x8b11, 0x0038, 0xc860, 0x3511,
+    0x3d11, 0xc862, 0x3511, 0x3d11, 0xc864, 0x3511, 0x3d11, 0xc872,
+    0x3511, 0x3d11, 0xe42e, 0xa200, 0x3cae, 0x3cab, 0x3cbe, 0x3c1c,
+    0x3c21, 0x3c22, 0x3c2a, 0xa202, 0x3caf, 0xe42e, 0xe0c0, 0x0040,
+    0xa231, 0xae17, 0xe042, 0xe005, 0x1500, 0xae03, 0xe042, 0xca29,
+    0xf7f9, 0xce20, 0xd111, 0x0400, 0xd112, 0x0210, 0xd113, 0x0003,
+    0xca28, 0xf7f8, 0xe42e, 0xd1b3, 0x0001, 0xa200, 0x3c57, 0x3c58,
+    0x3c59, 0x3c47, 0x3c84, 0x3c82, 0x3c81, 0xcf64, 0xcf62, 0xe16a,
+    0x28b4, 0xf11a, 0xc872, 0x26b8, 0x4eb9, 0xae07, 0xe045, 0xf0b3,
+    0xa202, 0x3c82, 0x2857, 0x3c83, 0x3c81, 0x3c47, 0x2a54, 0x1a83,
+    0x3e84, 0xf26e, 0xba2c, 0xf068, 0xe41e, 0x0524, 0x2882, 0xf208,
+    0xf0ce, 0x2a47, 0xe41b, 0x09db, 0xf0bd, 0x2a47, 0xa103, 0xe01b,
+    0x2840, 0xe016, 0xe051, 0xf079, 0xe41e, 0x0934, 0xf08c, 0xe41e,
+    0x0524, 0xf0ee, 0xa200, 0xe41e, 0x09b5, 0xf7ad, 0xa201, 0xe41e,
+    0x0583, 0x2258, 0x4e59, 0xcf63, 0xf4c8, 0xa200, 0xe42e, 0xa200,
+    0x3c82, 0x2885, 0x0884, 0x3c85, 0x2881, 0xe408, 0x05ae, 0xe41e,
+    0x0598, 0xf638, 0xa202, 0xe42e, 0xf06c, 0xe16a, 0xa202, 0x3c82,
+    0x2857, 0x3c83, 0xe41e, 0x055d, 0x2ada, 0xe017, 0x3eda, 0xf17a,
+    0xe41e, 0x09db, 0xf29d, 0x8455, 0x8245, 0xe018, 0x2a47, 0xa103,
+    0xe042, 0x3c46, 0x2882, 0xf058, 0x2857, 0x1846, 0xf1d8, 0xf07e,
+    0x2846, 0x1854, 0xf192, 0x2883, 0x1846, 0xf160, 0x2882, 0xf11a,
+    0x2a57, 0x3e83, 0x2a54, 0x2881, 0xf028, 0x2a46, 0x1a83, 0xf073,
+    0xa202, 0x3c81, 0x2a57, 0x3e83, 0x2a54, 0x1a83, 0x3e84, 0xe16a,
+    0xa202, 0x3c47, 0xe42e, 0xe16b, 0xf48e, 0xe41e, 0x0894, 0xba3e,
+    0xe008, 0x00ff, 0xa102, 0x3c45, 0xf1a4, 0xe002, 0x00ae, 0xf170,
+    0xba7e, 0xe190, 0xba48, 0x3c64, 0xae02, 0x4c65, 0xae04, 0xcb23,
+    0xa807, 0xe056, 0xcf22, 0xba40, 0xf06a, 0xba4e, 0xba40, 0xf03a,
+    0xba4e, 0xf7de, 0xd182, 0x0007, 0xa202, 0xe42e, 0xa202, 0x3c81,
+    0x3c82, 0xa200, 0xe42e, 0xf049, 0x2847, 0xa102, 0x3c47, 0x2857,
+    0xa002, 0x3c57, 0xcf64, 0x2858, 0xa002, 0x3c58, 0x1855, 0xe428,
+    0xd1b3, 0x0004, 0x3c58, 0x2859, 0xa002, 0x3c59, 0x1844, 0xe42e,
+    0x2884, 0xe42a, 0xd186, 0x0008, 0xa102, 0xcc44, 0xe184, 0x05ac,
+    0xa202, 0x2a40, 0xe41b, 0x09b5, 0x2840, 0xe418, 0x0e03, 0xa203,
+    0xe41e, 0x0583, 0x2258, 0x4e59, 0xcf63, 0xe42e, 0xa202, 0xe41e,
+    0x09b5, 0xa203, 0xe41e, 0x0583, 0x2258, 0x4e59, 0xcf63, 0xe42a,
+    0xf76e, 0xe41e, 0x0894, 0xba3e, 0xe008, 0x00ff, 0xf058, 0x8c4f,
+    0x0000, 0xf23d, 0xe16a, 0xba6e, 0xe41e, 0x0b28, 0xa201, 0x8c4f,
+    0x0000, 0xb63b, 0xe0c3, 0x0070, 0xe16a, 0xe428, 0x28a0, 0xf188,
+    0xba4e, 0xe002, 0x00b3, 0xf09a, 0xa108, 0xf64a, 0xa102, 0xf02a,
+    0xf61e, 0xe41e, 0x0673, 0xf5ee, 0xa203, 0xe41e, 0x0637, 0xa202,
+    0x3c4f, 0xf06b, 0x28b4, 0xf568, 0xe16a, 0xa202, 0xe42e, 0xa200,
+    0xe0c2, 0x0070, 0xe42e, 0xa203, 0xe41e, 0x0894, 0xba6e, 0x28b4,
+    0xf058, 0xe41e, 0x0b28, 0xb7f0, 0xe428, 0x28b4, 0xf09a, 0xc872,
+    0x26b8, 0x4eb9, 0xae07, 0xe045, 0xf031, 0xa200, 0xe42e, 0xba4e,
+    0xf2da, 0xe002, 0x00b3, 0xf06a, 0xa108, 0xf67a, 0xa102, 0xf22a,
+    0xf64e, 0xa201, 0xe41e, 0x0637, 0xf29b, 0x284a, 0xf0b8, 0x2855,
+    0xe008, 0x00ff, 0xae10, 0x2a56, 0xe009, 0x00ff, 0xe056, 0x3c4a,
+    0xf0fe, 0x284a, 0xaf10, 0xe008, 0x00ff, 0x1855, 0xf064, 0x284a,
+    0xe008, 0x00ff, 0x1856, 0xf042, 0xa2fe, 0x3c4a, 0xf0fe, 0xe40e,
+    0x05ec, 0xe41e, 0x0673, 0xe40e, 0x05ec, 0x2a4a, 0xe405, 0x0635,
+    0xe41e, 0x068d, 0xa202, 0xb616, 0xe42e, 0xa200, 0xe42e, 0xa200,
+    0x3c24, 0x3c26, 0x3c28, 0x3c29, 0x3ce3, 0xba56, 0xe40a, 0x0671,
+    0x3c52, 0xe002, 0x0780, 0xf026, 0xf2de, 0x2852, 0xa01e, 0xaf08,
+    0x3c55, 0xba56, 0xf27a, 0x3c53, 0xe002, 0x0480, 0xf026, 0xf22e,
+    0x2853, 0xa01e, 0xaf08, 0x3c56, 0x3c44, 0x8455, 0x8256, 0xe018,
+    0x3c54, 0xba46, 0x3c2f, 0xf16a, 0xba46, 0x3c27, 0xf13a, 0xba62,
+    0xba40, 0xf10a, 0xba52, 0xba40, 0xe41e, 0x0849, 0xf0b8, 0xa200,
+    0xe41e, 0x0719, 0xe049, 0x2824, 0xe41a, 0x0704, 0xf03b, 0xa203,
+    0xe42e, 0xa201, 0xe42e, 0xa202, 0x3ce3, 0xa201, 0xba40, 0xae32,
+    0xe055, 0xba48, 0xae28, 0xe055, 0xba4a, 0xae1c, 0xe055, 0xba40,
+    0xba4a, 0xae10, 0xe055, 0xba4a, 0xe055, 0xe0c3, 0x004c, 0xba40,
+    0xba40, 0xa202, 0xe41e, 0x0719, 0xe42e, 0xa204, 0x3ce3, 0xba52,
+    0x2a3b, 0xf02b, 0xae14, 0xe0c1, 0x007a, 0xe055, 0xe0c3, 0x007a,
+    0xba44, 0xe40a, 0x0702, 0x2a34, 0x3e48, 0x3c34, 0xa102, 0xa201,
+    0xb635, 0x3e40, 0xa102, 0xa201, 0xb635, 0x3e41, 0xa102, 0xa201,
+    0xb635, 0x3e42, 0xa102, 0xe400, 0x0702, 0xf048, 0x4c24, 0xe016,
+    0x3c49, 0x2834, 0x2a3b, 0xa102, 0xf02b, 0x64ea, 0x3cea, 0xa201,
+    0xa104, 0xb635, 0x3eeb, 0xba5f, 0x2824, 0xf08a, 0x2840, 0xf298,
+    0xba46, 0x2841, 0xf268, 0xba46, 0xf24e, 0x2840, 0x4c49, 0xe162,
+    0x0200, 0xe163, 0x0204, 0xf1d8, 0xba40, 0x3c7d, 0x4424, 0xf338,
+    0xba44, 0xf31a, 0xa102, 0x3d12, 0x3d02, 0xa221, 0x5b12, 0x3f13,
+    0x3f13, 0x2841, 0xf0e8, 0xba40, 0x3c7e, 0x4424, 0xf248, 0xba44,
+    0xf22a, 0xa102, 0x3d12, 0x3d02, 0xa221, 0x5b02, 0x3f13, 0x3f03,
+    0xba40, 0xf03a, 0xba4e, 0xf7de, 0xa202, 0xe41e, 0x0719, 0xf13a,
+    0x2834, 0xa108, 0xf0ba, 0xa202, 0x5834, 0xaf02, 0x2a3d, 0xa107,
+    0xf08b, 0x2a3d, 0xa105, 0xf029, 0xae06, 0x2a4b, 0xe055, 0x3e4b,
+    0xa203, 0xe42e, 0xa201, 0xe42e, 0xa200, 0x3c36, 0x3c35, 0x3c37,
+    0x3c33, 0x3c3a, 0x3c38, 0x3c30, 0xa202, 0x3c3c, 0x3c31, 0x3c3e,
+    0x3c25, 0xa206, 0x3c3d, 0x2853, 0xa01e, 0xaf08, 0x3c56, 0x3c44,
+    0xe42e, 0x3c51, 0xe41e, 0x088f, 0xba3e, 0xe008, 0x00ff, 0xe002,
+    0x00b2, 0xf18a, 0xa106, 0xe428, 0xba7e, 0xe190, 0xba46, 0xa102,
+    0xf3ca, 0xa102, 0xe40a, 0x076b, 0xa102, 0xe40a, 0x0773, 0xa102,
+    0xe40a, 0x077b, 0xa106, 0xe40a, 0x0783, 0xa102, 0xe40a, 0x078b,
+    0xf62e, 0x28d9, 0xf268, 0xba7e, 0xe190, 0xe0c0, 0x0065, 0xaf0a,
+    0xa802, 0xf59a, 0xe162, 0x0800, 0x28e3, 0x3d12, 0xa200, 0x3d12,
+    0xa202, 0x3d12, 0xa200, 0x3d12, 0xe0c1, 0x006b, 0x28e4, 0xa002,
+    0xae06, 0xe041, 0xaf06, 0x3ce4, 0xca28, 0xf7f8, 0xce21, 0xd111,
+    0x0800, 0xd112, 0x0004, 0xd113, 0x0002, 0xe1e1, 0xe40e, 0x071a,
+    0xe41e, 0x08a1, 0xe40e, 0x071a, 0xa202, 0x3c24, 0xe41e, 0x0796,
+    0xf2cb, 0xe40e, 0x071a, 0xa202, 0x3c24, 0xe41e, 0x07bc, 0x4e51,
+    0xf24b, 0xe40e, 0x071a, 0xa202, 0x3c24, 0xe41e, 0x07cc, 0x4e51,
+    0xf1cb, 0xe40e, 0x071a, 0xa202, 0x3c24, 0xe41e, 0x0838, 0x4e51,
+    0xf14b, 0xe40e, 0x071a, 0xa202, 0x3c24, 0xe41e, 0x0824, 0x4e51,
+    0xf0cb, 0xe40e, 0x071a, 0xa202, 0x3c24, 0xe41e, 0x07e0, 0xf05b,
+    0xe40e, 0x071a, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xba40, 0xba44,
+    0x3c2d, 0xba46, 0x3c2e, 0xba40, 0x3c25, 0x2a53, 0xf04a, 0xa01f,
+    0xaf09, 0xf04e, 0xa03f, 0xaf0b, 0xae03, 0x3e56, 0xba42, 0xa102,
+    0xf128, 0xba42, 0xf108, 0xba42, 0xf0e8, 0xba56, 0xf0c8, 0xba40,
+    0xf0aa, 0xba4e, 0xf088, 0xba40, 0xba42, 0x3c28, 0xba48, 0x3c29,
+    0xa203, 0xe42e, 0xa201, 0xe42e, 0xba44, 0xba40, 0xf07a, 0xba4e,
+    0xf0aa, 0xba4e, 0xf08a, 0xba4e, 0xf06a, 0xba5a, 0xba40, 0xba5a,
+    0xa203, 0xe42e, 0xa201, 0xe42e, 0xe41e, 0x0849, 0xf108, 0xa200,
+    0x3c50, 0xd022, 0x0001, 0xe184, 0x07da, 0xba41, 0xf03b, 0xc73f,
+    0xba4e, 0x4e50, 0x3e50, 0xf039, 0xa203, 0xe42e, 0xa201, 0xe42e,
+    0xe162, 0x0200, 0xe163, 0x0204, 0xd022, 0x0003, 0xe184, 0x07ed,
+    0xba46, 0xa102, 0x3d02, 0xa221, 0x5b12, 0x3f13, 0xba43, 0x3e30,
+    0xba43, 0x3e3d, 0xf30b, 0xa103, 0x3233, 0xaf03, 0x3e31, 0xe017,
+    0x3e32, 0x283b, 0xf03a, 0x2831, 0xf268, 0x2a31, 0x8455, 0x8256,
+    0xe018, 0xf029, 0xaf02, 0x3c54, 0x2856, 0xf029, 0xaf02, 0x3c44,
+    0xba40, 0x3c39, 0xba40, 0x3c3c, 0xba40, 0x3c38, 0xba40, 0x3c36,
+    0xba40, 0x3c37, 0xba40, 0x3c35, 0xba40, 0x3c3a, 0xba40, 0xba40,
+    0x3c3e, 0xa203, 0xba40, 0xe42a, 0xba40, 0xba44, 0x3cd5, 0xba5e,
+    0xa203, 0xe42e, 0xa201, 0xe42e, 0xa202, 0x2a25, 0xf04b, 0x083a,
+    0x0839, 0xf03e, 0x0831, 0x083a, 0xae02, 0xa102, 0xcc44, 0xe184,
+    0x0833, 0xba5e, 0xba40, 0xf03a, 0xa203, 0xe42e, 0xa201, 0xe42e,
+    0xba40, 0xba4e, 0xba40, 0xba4c, 0xba40, 0xf0aa, 0xba66, 0xba40,
+    0xf07a, 0xba6a, 0xba40, 0xf04a, 0xba6a, 0xa203, 0xe42e, 0xa201,
+    0xe42e, 0xba41, 0xf21b, 0xe0c3, 0x013c, 0xa200, 0x3c7c, 0xe161,
+    0x0220, 0x287c, 0xe0c2, 0x013e, 0xa002, 0x3c7c, 0xba4e, 0x3d11,
+    0xe0c2, 0x013f, 0xa110, 0xf328, 0xd022, 0x003e, 0xe184, 0x0869,
+    0x287c, 0xe0c2, 0x013e, 0xa002, 0x3c7c, 0xba4e, 0xf27a, 0x3d11,
+    0xe0c2, 0x013f, 0xe190, 0xba40, 0xf19a, 0xe0c2, 0x013c, 0xae02,
+    0xe055, 0xe004, 0x0040, 0x3c7c, 0xe162, 0x0260, 0xd022, 0x003f,
+    0xe184, 0x0883, 0x287c, 0xe0c2, 0x013e, 0xa002, 0x3c7c, 0xba4e,
+    0xf0da, 0x3d12, 0xe0c2, 0x013f, 0xe190, 0x4e26, 0x3e26, 0xe0c3,
+    0x013d, 0xa200, 0xe0c2, 0x013c, 0xe42e, 0xa202, 0xe42e, 0xd180,
+    0x0004, 0xcb00, 0xf7f8, 0xe42e, 0xd180, 0x0004, 0x28be, 0x4ca0,
+    0xcf0a, 0xcb00, 0xf7c8, 0xe42e, 0xc868, 0xa80e, 0x3c7a, 0x747a,
+    0xe42e, 0xba7e, 0x2ad9, 0x28e4, 0xa120, 0xb615, 0x3ed9, 0xe42b,
+    0xa200, 0x3ce2, 0xe162, 0x0800, 0xba4e, 0x2ae2, 0xa803, 0xf049,
+    0xae10, 0x3ce1, 0xf03e, 0x4ce1, 0x3d12, 0x2ae2, 0xa003, 0x3ee2,
+    0xa80f, 0xe41b, 0x0917, 0x28d9, 0xf0aa, 0xba2e, 0xa102, 0xf02a,
+    0xf6ce, 0x28e2, 0xa802, 0xf03a, 0x28e1, 0x3d12, 0xa211, 0x28e2,
+    0xa80e, 0xf0ba, 0xe045, 0xaf03, 0xf06b, 0xa103, 0x3e50, 0xa201,
+    0x8650, 0x3f12, 0xe41e, 0x0917, 0xa201, 0xba2e, 0xa102, 0xb631,
+    0xe162, 0x0800, 0x28e3, 0x3d12, 0x28e2, 0x3d12, 0x3f12, 0xa200,
+    0x3d12, 0xe0c1, 0x006b, 0x28e4, 0xa002, 0xae06, 0xe041, 0xaf06,
+    0x3ce4, 0xca28, 0xf7f8, 0xce21, 0xd111, 0x0800, 0xd112, 0x0004,
+    0xd113, 0x0002, 0xe1e1, 0x28d9, 0xe41a, 0x088f, 0xe42e, 0xa200,
+    0x3ce7, 0xe0c0, 0x005c, 0xe0c1, 0x0065, 0xaf12, 0xa802, 0xaf15,
+    0xa803, 0xe016, 0xe056, 0xf04a, 0xa200, 0x3cd9, 0xe42e, 0x28e8,
+    0xf05a, 0xe0c0, 0x005d, 0xe42a, 0xf7be, 0xe0c0, 0x005d, 0xe00a,
+    0x0200, 0xe0c2, 0x005d, 0xa202, 0xce00, 0x3ce8, 0xf71e, 0xd112,
+    0x0004, 0xe0c0, 0x006b, 0xe000, 0x0088, 0x08e7, 0xca29, 0xf7f9,
+    0xce20, 0xd111, 0x0800, 0xd113, 0x0002, 0xe1e1, 0xe162, 0x0800,
+    0x28e5, 0x2ae7, 0xa010, 0xa011, 0x3ce5, 0x3ee7, 0x1ae6, 0xe41b,
+    0x08f7, 0xa200, 0x3ce8, 0xe42e, 0x2857, 0xe0c2, 0x003f, 0xd180,
+    0x0002, 0xcb00, 0xcb03, 0xe409, 0x0999, 0xf7c8, 0xcb0c, 0x3060,
+    0xaf02, 0x3061, 0xaf02, 0x306f, 0xaf02, 0x3070, 0xaf02, 0x306a,
+    0xaf02, 0x3065, 0xaf02, 0xf03a, 0xcb16, 0x3c64, 0xa200, 0x2a70,
+    0x4e60, 0xe017, 0x4641, 0xb632, 0x3c6e, 0xcf24, 0xcb22, 0xaf08,
+    0xa802, 0x4c6f, 0xae02, 0x4c70, 0x2a60, 0xe055, 0xb636, 0x3c79,
+    0x286a, 0x4c70, 0x4c6f, 0xf08a, 0xd190, 0x0001, 0xcb20, 0xcb03,
+    0xe409, 0x0999, 0xf7c8, 0x746a, 0xa200, 0x1860, 0x2a61, 0xf03b,
+    0xb808, 0xf28d, 0xcf08, 0xe0c2, 0x012a, 0xa200, 0x2a60, 0xe017,
+    0x4e6e, 0x4e6a, 0xb652, 0xcf20, 0xd180, 0x0001, 0xcb00, 0xcb03,
+    0xf199, 0xf7d8, 0xcb20, 0xcb03, 0xf159, 0xf7d8, 0x7449, 0xa200,
+    0x2a60, 0xb636, 0xcf04, 0xa200, 0x2a6a, 0xe017, 0x4660, 0xb6d2,
+    0xcf04, 0xa200, 0x2a6e, 0xb652, 0xcf04, 0xa200, 0xe41e, 0x0e03,
+    0xe42e, 0xe16b, 0xa200, 0xcf02, 0xe42e, 0xe167, 0x02a0, 0xe166,
+    0x02a8, 0xcb26, 0xd022, 0x0003, 0xe184, 0x09a7, 0x3116, 0xaf02,
+    0xcb2a, 0x3517, 0x3d17, 0xcb2c, 0x3517, 0x3d17, 0xcb2e, 0x3517,
+    0x3d17, 0xcb30, 0x3517, 0x3d17, 0xe42e, 0x3c50, 0x2857, 0xe0c2,
+    0x003f, 0xd192, 0x0002, 0xd182, 0x0001, 0xcb0c, 0xaf04, 0xa806,
+    0xf038, 0xa210, 0xcf0c, 0xa200, 0x3c60, 0x2a41, 0xb652, 0xcf04,
+    0xd190, 0x0002, 0xcb20, 0xcb03, 0xf0b9, 0xf7d8, 0x286f, 0xae02,
+    0x4c70, 0xb634, 0x3c79, 0x2850, 0xe41e, 0x0e03, 0xe42e, 0xe16b,
+    0xa200, 0xcf02, 0xe42e, 0xa201, 0xb800, 0xe42d, 0xf08a, 0xa17e,
+    0xf7ca, 0xa102, 0xa87e, 0xe041, 0x3e47, 0xe42e, 0xa043, 0xf75e,
+    0xa200, 0x3c0b, 0x2208, 0x4e09, 0x28b5, 0xf05a, 0xe0c1, 0x0068,
+    0x3608, 0x3e09, 0xe0c0, 0x0069, 0xe042, 0xe41e, 0x0b89, 0xe41e,
+    0x0b68, 0xe004, 0xffff, 0x3c0a, 0xe41e, 0x0a51, 0xe41e, 0x0ac4,
+    0xd071, 0x802a, 0xe181, 0xa200, 0x3c0e, 0xe41e, 0x0a70, 0xa202,
+    0x3c0e, 0xe41e, 0x0a70, 0xa200, 0x3c0e, 0xd037, 0x0080, 0xe128,
+    0xe42e, 0xa200, 0x3c0b, 0xe41e, 0x0b60, 0xe0c0, 0x0062, 0xaf0c,
+    0xa802, 0xf10a, 0xe0c1, 0x0048, 0xe0c0, 0x0060, 0xe045, 0xaf13,
+    0xae03, 0xa109, 0x3e0b, 0xf063, 0xe0c0, 0x0061, 0xae04, 0xe042,
+    0x3c0b, 0xe0c0, 0x0060, 0x3408, 0x3c09, 0xe0c0, 0x0061, 0xae04,
+    0x3c0a, 0x28b4, 0xf0aa, 0xe0c1, 0x0060, 0xe0c0, 0x0064, 0xe042,
+    0xe41e, 0x0b89, 0xe41e, 0x0b68, 0xe41e, 0x0a51, 0xe41e, 0x0ac4,
+    0xd071, 0x802a, 0xe181, 0xa200, 0x3c0e, 0xe41e, 0x0a70, 0xa202,
+    0x3c0e, 0xe41e, 0x0a70, 0xa200, 0x3c0e, 0xd037, 0x0080, 0xe128,
+    0xe42e, 0xd030, 0x0000, 0xd034, 0x0000, 0xd033, 0x0000, 0xd035,
+    0x0000, 0xd036, 0x00ff, 0xd038, 0x0000, 0xe42e, 0xcb21, 0xa80d,
+    0xf7e9, 0xd04c, 0x0001, 0xe41e, 0x0a70, 0xd04c, 0x0000, 0xe004,
+    0x0080, 0x2a0e, 0xb616, 0xcc6e, 0x280e, 0xe016, 0x3c0e, 0xe470,
+    0xca28, 0xf7f8, 0x28ab, 0xf0da, 0xa802, 0xf06a, 0x3cbe, 0x28a6,
+    0xe01a, 0x3ca5, 0xe42e, 0xe41e, 0x0b12, 0xa202, 0x3cab, 0xe42e,
+    0xe082, 0x3c0c, 0xe004, 0x0048, 0xe092, 0xd027, 0x0000, 0xe41e,
+    0x0ace, 0xd027, 0x0001, 0x28a0, 0x4ca5, 0xf348, 0xe004, 0x0000,
+    0x2a0e, 0xf03b, 0xe000, 0x0080, 0xce22, 0x2008, 0x4c09, 0x2e0b,
+    0xae11, 0xe042, 0xce20, 0xd112, 0x0080, 0xe0c0, 0x0043, 0xa806,
+    0xae02, 0xa022, 0xce26, 0x2c0b, 0xe000, 0x0002, 0x3c0b, 0x1c0a,
+    0xf024, 0x3c0b, 0x28a6, 0xf168, 0x2008, 0x4c09, 0x2e0b, 0xae11,
+    0xe042, 0x9f01, 0x28ae, 0xf0ea, 0xa201, 0x20ac, 0x4cad, 0xe002,
+    0x0200, 0x34ac, 0x3cad, 0xb64d, 0x3eab, 0xf04b, 0xe000, 0x0200,
+    0x3cad, 0x280c, 0xe092, 0xe42e, 0x2008, 0x4c09, 0x2e0b, 0xae11,
+    0xe042, 0xe005, 0x0048, 0xe093, 0x9f01, 0xe42e, 0xe0c1, 0x0043,
+    0xa809, 0xe429, 0x28b4, 0x4cae, 0xe428, 0xa200, 0x3c0d, 0xe0c0,
+    0x0045, 0xaf04, 0x305d, 0x2008, 0x4c09, 0x2e0b, 0xae11, 0xe042,
+    0x8111, 0x9e89, 0xe045, 0xf043, 0x2c0a, 0xae10, 0xe041, 0xe003,
+    0x0200, 0xe423, 0x285d, 0xf08a, 0xe001, 0x0200, 0x36ac, 0x3ead,
+    0xa202, 0x3cae, 0xe42e, 0xe0c0, 0x0059, 0xa102, 0xf068, 0xe0c0,
+    0x0045, 0x30a0, 0x28a0, 0xe428, 0x28a6, 0xe01a, 0x3ca5, 0xe428,
+    0x280d, 0xf568, 0xe0c0, 0x005c, 0xe008, 0x4000, 0xf51a, 0xe0c0,
+    0x005d, 0xe00a, 0x4000, 0xe0c2, 0x005d, 0xa202, 0xce00, 0x3c0d,
+    0xf47e, 0xe42e, 0xe004, 0x0000, 0x2a0e, 0xf039, 0xe000, 0x0200,
+    0x08ad, 0xe049, 0xa807, 0x3ead, 0xaf04, 0xb432, 0x3cb0, 0xe008,
+    0x00ff, 0xcc78, 0xa200, 0xcc7a, 0xe004, 0x01b7, 0xcc7a, 0xe42e,
+    0x28b4, 0xf1b8, 0x28ab, 0xa802, 0xe42a, 0xc867, 0x1ab0, 0xa105,
+    0xe04a, 0xe000, 0x00fe, 0xf030, 0xe001, 0x0100, 0xa202, 0xb60a,
+    0xe429, 0xc869, 0xb636, 0xe42b, 0xa208, 0x18ad, 0xaf07, 0xe046,
+    0xe049, 0xa200, 0xb62e, 0xe42e, 0xe41e, 0x0b7d, 0xe42e, 0xe0c0,
+    0x0048, 0xe002, 0x0400, 0xc867, 0xe009, 0x007f, 0xa107, 0xae05,
+    0xe042, 0xc869, 0xaf07, 0xe015, 0xa807, 0xe042, 0x2208, 0x4e09,
+    0xe045, 0xf047, 0x2e0a, 0xae11, 0xe042, 0xe0c2, 0x0046, 0xe42e,
+    0xe161, 0x0800, 0xa200, 0x3d11, 0xe004, 0x01b7, 0x3d11, 0xe42e,
+    0xca29, 0xf7f9, 0xe0c0, 0x0049, 0xe049, 0xaf06, 0xae06, 0xa80f,
+    0xe01b, 0xae07, 0xe042, 0xce20, 0xd111, 0x0800, 0xd112, 0x0004,
+    0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0xc872, 0xe049, 0xa80f,
+    0xe01b, 0xaf06, 0xe042, 0x22b8, 0x4eb9, 0xe045, 0xa200, 0xb62e,
+    0xe42e, 0xe0c1, 0x0049, 0xe045, 0x36b8, 0x3eb9, 0xe42e, 0xe0c0,
+    0x0066, 0x3cba, 0x34bb, 0xe0c0, 0x0067, 0x3cbc, 0x34bd, 0xe0c0,
+    0x0069, 0xe167, 0x0ba0, 0x3d17, 0x3517, 0xe0c0, 0x006a, 0x3d17,
+    0x3517, 0xe0c0, 0x006b, 0x3d17, 0x3517, 0xe42e, 0xa200, 0xe0c2,
+    0x0320, 0xcc8e, 0x283b, 0xe408, 0x0cd5, 0xa200, 0x3c04, 0x3c05,
+    0xa200, 0x3cdb, 0x3ce9, 0x3cda, 0xe004, 0x00c6, 0xe0c2, 0x017c,
+    0xe004, 0x0004, 0xe0c2, 0x017d, 0xe0c0, 0x0050, 0xaf04, 0x3002,
+    0xaf02, 0x305e, 0xaf06, 0x3071, 0xaf08, 0x3010, 0xaf02, 0x305f,
+    0xaf06, 0x3072, 0xe0c0, 0x0050, 0xaf1c, 0xa802, 0xe005, 0x0ba6,
+    0xe09f, 0x3d17, 0x2810, 0x4402, 0x3002, 0x285f, 0x445e, 0x305e,
+    0x2872, 0x4471, 0x3071, 0x285e, 0xae02, 0x4c02, 0xae06, 0x4c71,
+    0xae04, 0xe0c2, 0x0169, 0xe0c0, 0x0044, 0xa80e, 0xae1a, 0x4c06,
+    0xe0c2, 0x0102, 0x2824, 0xe016, 0xae08, 0xa904, 0xe0c2, 0x0100,
+    0x2855, 0xae20, 0x4c56, 0xae08, 0xe0c2, 0x0101, 0xe0c2, 0x0283,
+    0xcf60, 0xa200, 0xe0c2, 0x0103, 0xe0c2, 0x0113, 0xe0c2, 0x0120,
+    0xe0c2, 0x0121, 0xe0c2, 0x0122, 0xe0c2, 0x0123, 0xe0c2, 0x0303,
+    0xe0c2, 0x0168, 0xa27e, 0xe0c2, 0x012a, 0x2826, 0xe0c2, 0x013d,
+    0xe418, 0x1028, 0x2842, 0xf078, 0x2a2a, 0xa105, 0xe017, 0x2813,
+    0xe419, 0x10b5, 0x2803, 0x4442, 0xf218, 0x2a03, 0xe41e, 0x1070,
+    0xe404, 0x0d7f, 0x3c12, 0x3c15, 0xe0c2, 0x0077, 0xa204, 0xe0c2,
+    0x0208, 0xe0c2, 0x0210, 0x8412, 0xc786, 0xe018, 0xe000, 0x0100,
+    0xe09e, 0x2117, 0x4d17, 0xe0c2, 0x020d, 0x2117, 0x4d17, 0xe0c2,
+    0x020e, 0x2117, 0x4d17, 0xe0c2, 0x020f, 0x2803, 0xf0ca, 0xa201,
+    0xe41e, 0x1070, 0xe404, 0x0d7f, 0x3c11, 0x3c15, 0x2a42, 0xf03b,
+    0xe0c2, 0x0077, 0x2842, 0x3c43, 0xf128, 0x2816, 0x3c15, 0x2812,
+    0x2a03, 0xf05b, 0x2812, 0xe41e, 0x10ad, 0x2811, 0x3c16, 0x2814,
+    0x3c13, 0x2812, 0x3c14, 0xa205, 0xe412, 0x10a6, 0x284e, 0xf074,
+    0xe0c0, 0x0060, 0xaf08, 0xa806, 0xe418, 0x0fb3, 0xe41e, 0x0e63,
+    0x2815, 0xe0c2, 0x0071, 0xf024, 0x3c17, 0xa202, 0xe0c2, 0x0302,
+    0xa202, 0xae02, 0xa902, 0xe0c2, 0x0312, 0xa220, 0xe0c2, 0x0313,
+    0x8413, 0xc786, 0xe018, 0xe000, 0x0100, 0xe09e, 0x2117, 0x4d17,
+    0xe0c2, 0x0380, 0x2117, 0x4d17, 0xe0c2, 0x0381, 0x2117, 0x4d17,
+    0xe0c2, 0x0382, 0x8414, 0xc786, 0xe018, 0xe000, 0x0100, 0xe09e,
+    0x2117, 0x4d17, 0xe0c2, 0x0383, 0x2117, 0x4d17, 0xe0c2, 0x0384,
+    0x2117, 0x4d17, 0xe0c2, 0x0385, 0xa200, 0xe0c2, 0x0302, 0x2803,
+    0xf35a, 0xe0c1, 0x0041, 0xe004, 0x0000, 0xae10, 0xe042, 0x2a10,
+    0xf03b, 0x20bb, 0x4cba, 0xe0c2, 0x0211, 0xe0c1, 0x0041, 0xe004,
+    0x003c, 0xae10, 0xe042, 0x2a5f, 0xf03b, 0x20bd, 0x4cbc, 0xe0c2,
+    0x0212, 0x8411, 0xc786, 0xe018, 0xe000, 0x0100, 0xe09e, 0x2117,
+    0x4d17, 0xe0c2, 0x0214, 0x2117, 0x4d17, 0xe0c2, 0x0215, 0x2117,
+    0x4d17, 0xe0c2, 0x0216, 0xa202, 0xe0c2, 0x0210, 0xa200, 0xcf68,
+    0x2842, 0xf04a, 0xa200, 0xe0c2, 0x0208, 0xe0c0, 0x0065, 0xaf18,
+    0xa802, 0xae10, 0xa960, 0x4c34, 0xa102, 0x2a42, 0xb432, 0xae04,
+    0x4c32, 0xae02, 0x4c33, 0xe0c2, 0x0204, 0x2a24, 0xe017, 0x2849,
+    0xae02, 0x4c40, 0xae02, 0x4c41, 0xae02, 0x4c3b, 0xae02, 0x4c39,
+    0xae02, 0x4c7e, 0xae02, 0x4c7d, 0xae02, 0x4c38, 0xae04, 0x4c30,
+    0xae02, 0x4c3c, 0xae04, 0x4c3d, 0xae04, 0x4c34, 0xae02, 0x4c37,
+    0xae02, 0xe056, 0xcf06, 0xe162, 0x0200, 0xd022, 0x0003, 0xe184,
+    0x0d0a, 0xae08, 0x4d12, 0xcf28, 0xa202, 0xae02, 0x4c35, 0xae0a,
+    0x4c32, 0xae02, 0x4c33, 0xe0c2, 0x0104, 0xa202, 0xe0c2, 0x0106,
+    0xa201, 0xe167, 0x0ba7, 0x3f17, 0xe41e, 0x117c, 0xe0c0, 0x0065,
+    0xaf0a, 0xa81e, 0xe40a, 0x0d6e, 0x28d6, 0xf27a, 0xa210, 0x3c50,
+    0xe162, 0x02b0, 0xe163, 0x02e8, 0xa201, 0xd022, 0x0002, 0xe184,
+    0x0d34, 0x2912, 0xa81e, 0xe055, 0xae09, 0x2912, 0xa81e, 0xe055,
+    0x3f13, 0x2850, 0xa102, 0xf03a, 0x3c50, 0xf6fe, 0xe162, 0x02f2,
+    0x2112, 0x4d02, 0xca29, 0xf7f9, 0xce20, 0xd112, 0x0008, 0xd111,
+    0x02e8, 0xd113, 0x0002, 0xe1e1, 0xe162, 0x02f0, 0xc410, 0xa200,
+    0x2ad6, 0xb632, 0xae10, 0x3d12, 0xa220, 0x3d12, 0x8132, 0xa200,
+    0x2ad7, 0xb652, 0xae10, 0x3d12, 0x2854, 0x5832, 0x3d12, 0x8132,
+    0x2ad8, 0x28ea, 0xe01a, 0xe051, 0xa200, 0xb692, 0xae10, 0x4cea,
+    0x3d12, 0x2854, 0x5832, 0xb616, 0x3d12, 0x8132, 0xa200, 0xe0c2,
+    0x0103, 0xe0c2, 0x0113, 0xe0c2, 0x0120, 0xe0c2, 0x0121, 0xe0c2,
+    0x0122, 0xe0c2, 0x0123, 0xe0c2, 0x0303, 0xa202, 0xe42e, 0xe16a,
+    0x2812, 0xe412, 0x109f, 0x2803, 0xe42a, 0x2811, 0xe412, 0x109f,
+    0xa200, 0xe42e, 0xf04a, 0x3c15, 0xe0c2, 0x0071, 0x2a2a, 0x2842,
+    0xb435, 0x3e2a, 0xa107, 0xf039, 0xa204, 0x3c2a, 0x2842, 0x3c43,
+    0x2021, 0x4c22, 0xa002, 0x3421, 0x3c22, 0xe0c2, 0x0070, 0x2885,
+    0xe0c2, 0x0072, 0x2834, 0xa106, 0xe01a, 0xae02, 0x4c25, 0xae02,
+    0x4c3c, 0xae06, 0x4cd5, 0xae04, 0x4c3e, 0xae02, 0x4c3a, 0xae02,
+    0x4c39, 0xae04, 0x4c3d, 0xae02, 0x4c32, 0xae24, 0x2a34, 0xa103,
+    0xe056, 0x2a4b, 0xae05, 0xe056, 0xe0c2, 0x0073, 0xe41e, 0x018c,
+    0xe0c2, 0x0057, 0x282f, 0xe0c2, 0x0056, 0xc84a, 0xc84d, 0xae20,
+    0xe056, 0xe0c2, 0x0053, 0xe0c0, 0x0065, 0xaf0a, 0xa802, 0xf13a,
+    0xe162, 0x0800, 0x28e4, 0x3d12, 0x28e5, 0x3d12, 0xe0c0, 0x006b,
+    0xca29, 0xf7f9, 0xce20, 0xd111, 0x0800, 0xd112, 0x0004, 0xd113,
+    0x0002, 0xe1e1, 0xe0c0, 0x0065, 0xaf0c, 0xa80e, 0xf0da, 0xe0c0,
+    0x006a, 0xca29, 0xf7f9, 0xce20, 0xd112, 0x000c, 0xd111, 0x02f0,
+    0xd113, 0x0002, 0xe1e1, 0xa200, 0x3ce5, 0x3ce4, 0x3cd9, 0x3ce7,
+    0x3ce8, 0x284e, 0xe424, 0x2818, 0xe000, 0x02d0, 0xe094, 0x2902,
+    0xa81c, 0x3d02, 0xe42e, 0x2ad7, 0xf07b, 0xae02, 0x4cda, 0xae0c,
+    0x4c64, 0xe41e, 0x10bd, 0x2803, 0xe40a, 0x0e14, 0xd1b6, 0x0001,
+    0xd1b5, 0x0001, 0xcb6a, 0xf7f8, 0x2865, 0xae08, 0x4c60, 0xe0c2,
+    0x0114, 0x2836, 0xae0a, 0x4c64, 0xe0c2, 0x0115, 0xe0c0, 0x012a,
+    0xe0c2, 0x0116, 0x2ad8, 0x28ea, 0xe01a, 0xe051, 0xf28b, 0xe004,
+    0x0780, 0x08e9, 0xe094, 0x2860, 0xf208, 0x2a79, 0xa803, 0xae1f,
+    0xe0c0, 0x03b0, 0xb616, 0x3512, 0x3d0a, 0x2902, 0xe008, 0x7fff,
+    0xe056, 0x3d12, 0x8112, 0x28ea, 0xa102, 0xf0fa, 0x2a79, 0xa805,
+    0xae1d, 0xe0c0, 0x03c0, 0xb616, 0x3512, 0x3d0a, 0x2902, 0xe008,
+    0x7fff, 0xe056, 0x3d12, 0x8112, 0xe41e, 0x1103, 0xe0c0, 0x0111,
+    0xf7e8, 0xa202, 0xe0c2, 0x0110, 0xe41e, 0x0f2e, 0xe0c0, 0x0060,
+    0xaf08, 0xa806, 0xe42a, 0x284e, 0xf064, 0xa202, 0x3c95, 0xa203,
+    0xe41e, 0x0fef, 0xe42e, 0x284e, 0xf1d4, 0x280f, 0xf1ba, 0xa210,
+    0x3c50, 0xa201, 0xe161, 0x02d0, 0xa200, 0x3c1e, 0xd022, 0x0003,
+    0xe184, 0x0e80, 0x2911, 0xa80e, 0xf0aa, 0x1850, 0xf082, 0x0850,
+    0xe049, 0xa803, 0xf04b, 0x3c50, 0x281e, 0x3c18, 0x281e, 0xa002,
+    0x3c1e, 0x281c, 0xe428, 0xa2fe, 0x3c1a, 0x3c1b, 0xa200, 0x3c1e,
+    0x3c1d, 0xe161, 0x02d0, 0xd022, 0x0003, 0xe184, 0x0ea4, 0x2901,
+    0x3c50, 0x4c1d, 0xf058, 0x281e, 0x3c19, 0xa202, 0x3c1d, 0x2850,
+    0xe049, 0xa804, 0xf03a, 0x281e, 0x3c1a, 0xa809, 0xf03b, 0x281e,
+    0x3c1b, 0x281e, 0xa002, 0x3c1e, 0x8111, 0x2819, 0xe000, 0x02d0,
+    0xe094, 0x2842, 0xe016, 0xae04, 0xa902, 0x3d02, 0x2842, 0xe428,
+    0x281b, 0xf084, 0xe000, 0x02d0, 0xe094, 0x2902, 0xa904, 0xa816,
+    0x3d02, 0x282a, 0xa104, 0xe428, 0x281a, 0xe424, 0xe000, 0x02d0,
+    0xe094, 0x2902, 0xa81a, 0x3d02, 0xe42e, 0x284e, 0xf1b4, 0xa210,
+    0x3c50, 0xa201, 0xe161, 0x02d0, 0xa200, 0x3c1e, 0xd022, 0x0003,
+    0xe184, 0x0ee0, 0x2911, 0xa80e, 0xf0aa, 0x1850, 0xf082, 0x0850,
+    0xe049, 0xa803, 0xf04b, 0x3c50, 0x281e, 0x3c18, 0x281e, 0xa002,
+    0x3c1e, 0xa200, 0x3c1e, 0x3c1d, 0x2812, 0xf144, 0xe161, 0x02d0,
+    0xd022, 0x0003, 0xe184, 0x0ef8, 0x2901, 0x3c50, 0xa81e, 0x4c1d,
+    0xf058, 0x281e, 0x3c19, 0xa202, 0x3c1d, 0x281e, 0xa002, 0x3c1e,
+    0x8111, 0x281a, 0xf154, 0xe161, 0x02d0, 0xd022, 0x0003, 0xe184,
+    0x0f07, 0x2901, 0xe049, 0xa810, 0xf03a, 0xa86f, 0x3f01, 0x8111,
+    0x281a, 0xe000, 0x02d0, 0xe094, 0x2902, 0xa910, 0x3d02, 0x281a,
+    0xf084, 0x281a, 0xe000, 0x02d0, 0xe094, 0x2902, 0xa87a, 0x3d02,
+    0x2819, 0xe000, 0x02d0, 0xe094, 0xa22a, 0xa201, 0xb632, 0x3d02,
+    0x281b, 0xf0a4, 0xe000, 0x02d0, 0xe094, 0x2902, 0xa904, 0xa876,
+    0x3d02, 0x281b, 0x3c1a, 0x2819, 0x3c1b, 0xe42e, 0x2a64, 0x2858,
+    0xa802, 0xf0e8, 0xae11, 0x3e96, 0x2858, 0xa002, 0x1855, 0xe428,
+    0x2858, 0xaf02, 0xe000, 0x0300, 0xe09e, 0x3f07, 0xf20e, 0x2a96,
+    0x2858, 0xaf02, 0xe000, 0x0300, 0xe09e, 0x4e64, 0x3f07, 0x2858,
+    0xa002, 0x1855, 0xe428, 0xf13e, 0x2a58, 0x2897, 0xa803, 0xe429,
+    0x2858, 0xe41a, 0x0f89, 0x2858, 0xaf02, 0xe000, 0x0340, 0xe09e,
+    0x2907, 0xe049, 0xaf10, 0xa83f, 0x3e97, 0xe42e, 0x2855, 0xa002,
+    0xaf02, 0xa006, 0xa2f9, 0xe052, 0xae02, 0x3c50, 0x2859, 0x2a32,
+    0xf03b, 0xae02, 0x0833, 0x3c51, 0xe0c1, 0x0041, 0x20f0, 0x4cf1,
+    0xe041, 0xe004, 0x029c, 0xae10, 0xe042, 0x2a19, 0xae1b, 0xe042,
+    0x8451, 0x8250, 0xe019, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111,
+    0x0300, 0x2850, 0xaf02, 0xce24, 0xd113, 0x0002, 0xca28, 0xf7f8,
+    0xe42e, 0x2855, 0xa002, 0xaf02, 0xa006, 0xa2f9, 0xe052, 0xae02,
+    0x3c50, 0x2859, 0x2a3b, 0xf02b, 0x0844, 0x3c51, 0xe0c1, 0x0041,
+    0x20f0, 0x4cf1, 0xe041, 0xe004, 0x029c, 0xae10, 0xe042, 0x2a18,
+    0xae1b, 0xe042, 0x8451, 0x8250, 0xe019, 0xe042, 0xca29, 0xf7f9,
+    0xce20, 0xd111, 0x0340, 0x2850, 0xaf02, 0xce24, 0xd113, 0x0003,
+    0xca28, 0xf7f8, 0xe42e, 0xa202, 0x3c0f, 0xe0c0, 0x0060, 0xaf08,
+    0x3004, 0xaf02, 0x3005, 0xe0c1, 0x0060, 0xa81f, 0xae08, 0xe055,
+    0xe0c3, 0x014e, 0x2855, 0xa102, 0xae20, 0x4c56, 0xa102, 0xe0c2,
+    0x0142, 0x2806, 0xe0c2, 0x0141, 0xe0c0, 0x0064, 0xe0c2, 0x014c,
+    0x8417, 0xc786, 0xe018, 0xe000, 0x0100, 0xe09e, 0x2117, 0x4d17,
+    0xe0c2, 0x0143, 0x2117, 0x4d17, 0xe0c2, 0x0144, 0x2117, 0x4d17,
+    0xe0c2, 0x0145, 0xe0c0, 0x0061, 0xe0c2, 0x0146, 0xe0c0, 0x0062,
+    0xe0c2, 0x0147, 0xe0c0, 0x0063, 0xe0c2, 0x0148, 0xe42e, 0x2858,
+    0x4c59, 0xe01a, 0x3c94, 0x4605, 0xe419, 0x0f4c, 0xae02, 0x4c94,
+    0xae02, 0x4c95, 0xae0e, 0x4c58, 0xae0e, 0x2a3b, 0xf02b, 0x0844,
+    0x0859, 0xe0c1, 0x014b, 0xf7e9, 0xe0c2, 0x014d, 0xa202, 0xe0c2,
+    0x014a, 0xe42e, 0x2858, 0xa002, 0x3c58, 0x1855, 0xe428, 0x3c58,
+    0x2859, 0xa002, 0x3c59, 0x1856, 0xe42e, 0xa204, 0xae0e, 0x4c55,
+    0xa102, 0xae0e, 0x4c56, 0xa102, 0xe0c1, 0x014b, 0xf7e9, 0xe0c2,
+    0x014d, 0xa202, 0xe0c2, 0x014a, 0xe0c1, 0x014b, 0xf7e9, 0xe42e,
+    0xa802, 0xf14a, 0xe0c2, 0x013c, 0xa200, 0x3c7c, 0xe161, 0x0220,
+    0xd022, 0x003f, 0xe184, 0x103b, 0x287c, 0xe0c2, 0x013e, 0xa002,
+    0x3c7c, 0x2911, 0xe0c2, 0x013f, 0xe190, 0x2826, 0xaf02, 0xf15a,
+    0xe0c2, 0x013c, 0xe004, 0x0040, 0x3c7c, 0xe162, 0x0260, 0xd022,
+    0x003f, 0xe184, 0x1052, 0x287c, 0xe0c2, 0x013e, 0xa002, 0x3c7c,
+    0x2912, 0xe0c2, 0x013f, 0xe190, 0xa200, 0xe0c2, 0x013c, 0xe42e,
+    0xa2fa, 0x3c15, 0x3c12, 0x3c17, 0x3c4e, 0x3c16, 0x3c11, 0x3c13,
+    0x3c14, 0xa200, 0x3cb2, 0x3c43, 0xe161, 0x02b0, 0x2a23, 0xa103,
+    0x3e50, 0x8650, 0x3d11, 0xe161, 0x02d0, 0xc703, 0x3d11, 0xe42e,
+    0x28b2, 0x3cb3, 0x28b3, 0xe000, 0x02b0, 0xe092, 0x2901, 0xf0da,
+    0x28b3, 0xa002, 0x3cb3, 0x1823, 0xf038, 0xa200, 0x3cb3, 0x28b3,
+    0x18b2, 0xf718, 0xa2fe, 0xe42e, 0xa208, 0xb652, 0x3d01, 0x28b3,
+    0xa002, 0x3cb2, 0x1823, 0xf038, 0xa200, 0x3cb2, 0x28b3, 0xe42e,
+    0xe161, 0x02b0, 0x2823, 0xa102, 0xcc44, 0xa200, 0xe184, 0x109b,
+    0x2b11, 0xa80d, 0xe01b, 0xe042, 0x1823, 0xe01a, 0xe42e, 0xe424,
+    0xe000, 0x02b0, 0xe092, 0xa200, 0x3d01, 0xe42e, 0xe000, 0x02b0,
+    0xe092, 0x2901, 0xe056, 0x3d01, 0xe42e, 0xe424, 0xe000, 0x02b0,
+    0xe092, 0x2901, 0xa806, 0x3d01, 0xe42e, 0xe424, 0xe000, 0x02b0,
+    0xe092, 0x2901, 0xa80a, 0x3d01, 0xe42e, 0x2a57, 0xa803, 0xf139,
+    0xae10, 0x3cdc, 0x2a3b, 0xe017, 0x4632, 0xe429, 0x2a54, 0xa103,
+    0x1a57, 0xe429, 0xe005, 0x0700, 0x0adb, 0xe095, 0x3d02, 0xe41e,
+    0x10ed, 0xe42e, 0x4cdc, 0xe005, 0x0700, 0x0adb, 0xe095, 0x3d02,
+    0x28db, 0xa002, 0x3cdb, 0xe002, 0x0080, 0xf068, 0xe41e, 0x10ed,
+    0xa200, 0x3cdb, 0xe42e, 0x2a3b, 0xe017, 0x4632, 0xe429, 0x2854,
+    0xa102, 0x1857, 0xe41a, 0x10ed, 0xe42e, 0x2a57, 0x283b, 0xf02a,
+    0x0a54, 0xaf11, 0xae11, 0xe162, 0x02f6, 0x2112, 0x4d02, 0xe042,
+    0xca29, 0xf7f9, 0xce20, 0xd112, 0x0080, 0xd111, 0x0700, 0xd113,
+    0x0002, 0xe1e1, 0xe42e, 0x2860, 0xf08a, 0xa201, 0xa204, 0x58eb,
+    0xa102, 0x3c50, 0x8650, 0x3f12, 0x28e9, 0x2aeb, 0xa004, 0xb452,
+    0x3ce9, 0xe002, 0x0080, 0xf068, 0xe41e, 0x1123, 0xa200, 0x3ce9,
+    0xe42e, 0x2a3b, 0xe017, 0x4632, 0xe429, 0x2854, 0xa102, 0x1857,
+    0xe41a, 0x1123, 0xe42e, 0x28eb, 0xe016, 0x3c50, 0x2a57, 0x283b,
+    0xf02a, 0x0a54, 0xaf0b, 0x5e50, 0xae11, 0xe162, 0x02fa, 0x2112,
+    0x4d02, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd112, 0x0080, 0xd111,
+    0x0780, 0xd113, 0x0002, 0xe1e1, 0xe42e, 0x3e88, 0xa201, 0xf032,
+    0xe012, 0xa203, 0x3e8c, 0x3c89, 0xaf20, 0xc70f, 0x7c88, 0x3c8a,
+    0xaf20, 0xae20, 0x4c89, 0xc70f, 0x7c88, 0x3c8b, 0x208a, 0x4c8b,
+    0x2a8c, 0xe42b, 0xe012, 0xe42e, 0xe167, 0x0bac, 0xe166, 0x02c0,
+    0xd022, 0x0008, 0xe184, 0x1160, 0x2d17, 0x9f16, 0x2517, 0x4d17,
+    0x9f16, 0xe166, 0x02d2, 0xd022, 0x0008, 0xe184, 0x1169, 0x2517,
+    0x4d17, 0x9f16, 0xe166, 0x02db, 0xd022, 0x0008, 0xe184, 0x1172,
+    0x2517, 0x4d17, 0x9f16, 0xe166, 0x02e4, 0xd022, 0x0008, 0xe184,
+    0x117a, 0x2d17, 0x9f16, 0xe42e, 0xe0c0, 0x0065, 0xaf18, 0xa802,
+    0xe40a, 0x11fe, 0xae0a, 0xe0c1, 0x0060, 0xaf0d, 0xa80f, 0xe056,
+    0xe0c1, 0x0044, 0xa811, 0xe056, 0xae0c, 0xe0c1, 0x0044, 0xa80f,
+    0xe056, 0xe167, 0x0ba7, 0x2f17, 0xe056, 0xe0c2, 0x0282, 0xe0c0,
+    0x006e, 0xe0c2, 0x0284, 0xaf20, 0xe0c1, 0x0282, 0xa809, 0xf04b,
+    0xe049, 0xae1f, 0xf06e, 0xe049, 0xa011, 0xaf09, 0xae07, 0xae21,
+    0xe056, 0xe0c2, 0x028c, 0xe167, 0x0ba8, 0x2d17, 0x4917, 0xe0c2,
+    0x0285, 0xe167, 0x0baa, 0x2d17, 0x4917, 0xe0c2, 0x0286, 0xe41e,
+    0x11ff, 0xe0c0, 0x004a, 0xe0c2, 0x0289, 0xe0c0, 0x004b, 0xe0c2,
+    0x028a, 0xe0c0, 0x0055, 0xe0c2, 0x028b, 0xe0c1, 0x0041, 0xe004,
+    0x005c, 0xae10, 0xe042, 0xe167, 0x0ba6, 0x2b17, 0xf05b, 0xe167,
+    0x0ba0, 0x2d17, 0x4917, 0xe0c2, 0x0287, 0xe0c1, 0x0041, 0xe004,
+    0x0074, 0xae10, 0xe042, 0xe167, 0x0ba6, 0x2b17, 0xf05b, 0xe167,
+    0x0ba2, 0x2d17, 0x4917, 0xe0c2, 0x0288, 0xe0c1, 0x0041, 0xe004,
+    0x007c, 0xae10, 0xe042, 0xe167, 0x0ba6, 0x2b17, 0xf05b, 0xe167,
+    0x0ba4, 0x2d17, 0x4917, 0xe0c2, 0x028d, 0xe0c0, 0x0065, 0xaf18,
+    0xa802, 0xe0c2, 0x0280, 0xa210, 0xe0c2, 0x0168, 0xe42e, 0xe167,
+    0x0bac, 0xe165, 0x028e, 0xe166, 0x02c0, 0xd022, 0x0008, 0xe184,
+    0x1212, 0x2d17, 0x9f16, 0x9e85, 0xf7fb, 0x2517, 0x4d17, 0x9f16,
+    0x9e85, 0xf7fb, 0xe190, 0xe166, 0x02d2, 0xd022, 0x0008, 0xe184,
+    0x121e, 0x2517, 0x4d17, 0x9f16, 0x9e85, 0xf7fb, 0xe190, 0xe166,
+    0x02db, 0xd022, 0x0008, 0xe184, 0x122a, 0x2517, 0x4d17, 0x9f16,
+    0x9e85, 0xf7fb, 0xe190, 0xe166, 0x02e4, 0xd022, 0x0008, 0xe184,
+    0x1235, 0x2d17, 0x9f16, 0x9e85, 0xf7fb, 0xe190, 0xe42e, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0x0005, 0x5555, 0x0004, 0x0000, 0x0003, 0x3333, 0x0002, 0xaaaa,
+    0x0002, 0x4924, 0x0002, 0x0000, 0x0001, 0xc71c, 0x0001, 0x9999,
+    0x0001, 0x745d, 0x0001, 0x0000, 0x0f1e, 0x261e, 0x0f00, 0x0b1d,
+    0x2820, 0x0d03, 0x0a1c, 0x2821, 0x0e03, 0x091b, 0x2822, 0x0f03,
+    0x081a, 0x2623, 0x1104, 0x0719, 0x2723, 0x1204, 0x0618, 0x2724,
+    0x1304, 0x0616, 0x2625, 0x1405, 0x0515, 0x2626, 0x1505, 0x0c1f,
+    0x2920, 0x0c00, 0x0a1e, 0x2820, 0x0d03, 0x091c, 0x2921, 0x0e03,
+    0x081b, 0x2922, 0x0f03, 0x081a, 0x2823, 0x1003, 0x0719, 0x2724,
+    0x1104, 0x0617, 0x2726, 0x1204, 0x0516, 0x2726, 0x1404, 0x0515,
+    0x2626, 0x1505, 0x0b1f, 0x2b20, 0x0b00, 0x0817, 0x211a, 0x091d,
+    0x0819, 0x251d, 0x0b12, 0x0719, 0x2721, 0x0d0b, 0x0719, 0x2822,
+    0x0e08, 0x0618, 0x2824, 0x1006, 0x0617, 0x2825, 0x1105, 0x0515,
+    0x2826, 0x1305, 0x0514, 0x2727, 0x1405, 0x0c1e, 0x2b1f, 0x0c00,
+    0x0b1b, 0x281e, 0x0c08, 0x0a1a, 0x281f, 0x0d08, 0x0a19, 0x2721,
+    0x0e07, 0x0918, 0x2722, 0x0f07, 0x0917, 0x2722, 0x1007, 0x0816,
+    0x2624, 0x1107, 0x0814, 0x2625, 0x1207, 0x0813, 0x2525, 0x1308,
+    0x0b1f, 0x2c1f, 0x0b00, 0x091d, 0x2b20, 0x0b04, 0x091c, 0x2a21,
+    0x0c04, 0x081a, 0x2b22, 0x0d04, 0x0719, 0x2a24, 0x0e04, 0x0717,
+    0x2a25, 0x0f04, 0x0616, 0x2926, 0x1104, 0x0615, 0x2826, 0x1205,
+    0x0513, 0x2828, 0x1305, 0x0820, 0x3020, 0x0800, 0x071d, 0x3021,
+    0x0902, 0x061c, 0x2f23, 0x0a02, 0x061a, 0x2f24, 0x0b02, 0x0518,
+    0x2f26, 0x0c02, 0x0417, 0x2e27, 0x0e02, 0x0415, 0x2d29, 0x0f02,
+    0x0313, 0x2c2b, 0x1003, 0x0312, 0x2b2b, 0x1203, 0x0520, 0x3620,
+    0x0500, 0x041e, 0x3622, 0x0600, 0x031b, 0x3625, 0x0700, 0x0319,
+    0x3527, 0x0800, 0x0217, 0x3529, 0x0900, 0x0215, 0x332a, 0x0b01,
+    0x0213, 0x322c, 0x0c01, 0x0111, 0x312e, 0x0e01, 0x010f, 0x3030,
+    0x0f01, 0x001c, 0x481c, 0x0000, 0x0018, 0x491f, 0x0000, 0x0015,
+    0x4723, 0x0100, 0x0012, 0x4627, 0x0100, 0x000f, 0x442b, 0x0200,
+    0x000c, 0x422f, 0x0300, 0x000a, 0x3f33, 0x0400, 0x0008, 0x3d36,
+    0x0500, 0x0006, 0x3a3a, 0x0600, 0xff1a, 0x4e1a, 0xff00, 0xff16,
+    0x4e1e, 0xff00, 0xff12, 0x4d23, 0xff00, 0xff0f, 0x4b27, 0x0000,
+    0xff0c, 0x492c, 0x0000, 0xff0a, 0x472f, 0x0100, 0x0008, 0x4333,
+    0x0200, 0x0006, 0x3f38, 0x0300, 0x0004, 0x3c3c, 0x0400, 0xff17,
+    0x5417, 0xff00, 0xff13, 0x541c, 0xfe00, 0xff10, 0x5221, 0xfe00,
+    0xff0c, 0x5125, 0xff00, 0xff09, 0x4e2b, 0xff00, 0xff07, 0x4b30,
+    0xff00, 0xff05, 0x4735, 0x0000, 0x0003, 0x423a, 0x0100, 0x0002,
+    0x3e3e, 0x0200, 0xfe15, 0x5a15, 0xfe00, 0xfe10, 0x5a1a, 0xfe00,
+    0xff0c, 0x581f, 0xfe00, 0xff09, 0x5624, 0xfe00, 0xff06, 0x532b,
+    0xfd00, 0xff04, 0x4f30, 0xfe00, 0x0002, 0x4a36, 0xfe00, 0x0000,
+    0x463c, 0xfe00, 0x00ff, 0x4141, 0xff00, 0x2a2c, 0x2a00, 0x1d3b,
+    0x2305, 0x1a3b, 0x2605, 0x173b, 0x2806, 0x153a, 0x2b06, 0x1239,
+    0x2d08, 0x1037, 0x3009, 0x0e36, 0x320a, 0x0c34, 0x340c, 0x233a,
+    0x2300, 0x1d3b, 0x2305, 0x1a3c, 0x2505, 0x173c, 0x2805, 0x153b,
+    0x2a06, 0x123a, 0x2d07, 0x1038, 0x2f09, 0x0e36, 0x320a, 0x0c34,
+    0x340c, 0x213e, 0x2100, 0x1d3d, 0x2204, 0x1a3d, 0x2504, 0x173d,
+    0x2705, 0x143c, 0x2a06, 0x123a, 0x2d07, 0x1038, 0x3008, 0x0e36,
+    0x320a, 0x0c34, 0x340c, 0x2040, 0x2000, 0x1c3e, 0x2204, 0x193e,
+    0x2504, 0x163d, 0x2805, 0x143c, 0x2b05, 0x113b, 0x2d07, 0x0f39,
+    0x3008, 0x0d37, 0x3309, 0x0b35, 0x350b, 0x1f42, 0x1f00, 0x1634,
+    0x1b1b, 0x1537, 0x2014, 0x1438, 0x2410, 0x1238, 0x280e, 0x1038,
+    0x2c0c, 0x0f37, 0x2e0c, 0x0e35, 0x310c, 0x0d33, 0x330d, 0x2040,
+    0x2000, 0x1a3a, 0x1f0d, 0x183a, 0x220c, 0x163a, 0x240c, 0x1438,
+    0x280c, 0x1237, 0x2b0c, 0x1135, 0x2d0d, 0x1034, 0x2f0d, 0x0e32,
+    0x320e, 0x1f41, 0x2000, 0x1b3d, 0x2008, 0x183d, 0x2308, 0x163c,
+    0x2608, 0x143a, 0x2909, 0x1239, 0x2c09, 0x1038, 0x2e0a, 0x0e36,
+    0x310b, 0x0d33, 0x330d, 0x115d, 0x1200, 0x0e5c, 0x1600, 0x0a5b,
+    0x1b00, 0x0858, 0x2000, 0x0655, 0x2500, 0x0450, 0x2c00, 0x034a,
+    0x3201, 0x0245, 0x3801, 0x013f, 0x3f01, 0x1060, 0x1000, 0x0c60,
+    0x1400, 0x095e, 0x1900, 0x075b, 0x1e00, 0x0557, 0x2400, 0x0352,
+    0x2b00, 0x024c, 0x3200, 0x0146, 0x3900, 0x013f, 0x3f01, 0x0e64,
+    0x0e00, 0x0a64, 0x1200, 0x0762, 0x1700, 0x055e, 0x1d00, 0x035a,
+    0x2300, 0x0254, 0x2a00, 0x014e, 0x3100, 0x0147, 0x3800, 0x0040,
+    0x4000, 0x0c68, 0x0c00, 0x0868, 0x1000, 0x0665, 0x1500, 0x0461,
+    0x1b00, 0x025d, 0x2100, 0x0157, 0x2800, 0x0050, 0x3000, 0x0048,
+    0x3800, 0x0040, 0x4000, 0x7f01, 0x7808, 0x7010, 0x6818, 0x6020,
+    0x5828, 0x5030, 0x4838, 0x4040, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe40e, 0x0020, 0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x0131,
+    0xe470, 0xe190, 0xe40e, 0x0113, 0xe470, 0xe190, 0xe470, 0xe190,
+    0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+    0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x012f, 0xe40e, 0x0131,
+    0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058,
+    0xa200, 0xe0c2, 0x005a, 0x3cf0, 0x3cf1, 0xa2fe, 0x3cee, 0x3cef,
+    0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d, 0xce00, 0xf11e, 0xe0c0,
+    0x005c, 0xe0c1, 0x0059, 0x3eed, 0xa203, 0x5aed, 0xe052, 0xf08a,
+    0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00, 0xe41e,
+    0x008c, 0xe41e, 0x00ab, 0xe0c0, 0x005a, 0x18ee, 0xe0c1, 0x0059,
+    0xa115, 0xb636, 0x2aee, 0xb60a, 0xe418, 0x00fb, 0xe0c0, 0x005b,
+    0xe0c1, 0x005e, 0xae11, 0xe056, 0x18ef, 0xe0c1, 0x0059, 0xa117,
+    0xb636, 0xe418, 0x00b0, 0xe0c0, 0x005a, 0x18ee, 0x2aee, 0xb60a,
+    0xe0c1, 0x0059, 0xa117, 0xb636, 0xe418, 0x00f3, 0xd071, 0x802a,
+    0xe181, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100, 0xe0c0, 0x0059,
+    0xae02, 0xe000, 0x0113, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a,
+    0x3cee, 0xe41e, 0x0100, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11,
+    0xe056, 0x3cef, 0xe40e, 0x0037, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+    0x0058, 0xe0c2, 0x0008, 0xe0c0, 0x0059, 0xf7ea, 0xa11e, 0xf0e8,
+    0xa202, 0xe0c2, 0x0058, 0xe004, 0x093d, 0xe0c2, 0x0070, 0xa200,
+    0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xf6fe, 0xa202, 0xe0c2, 0x0008,
+    0xe0c2, 0x0058, 0xe42e, 0xd101, 0x0001, 0xc70f, 0xa000, 0xe42e,
+    0xa200, 0xe0c1, 0x005b, 0xf27b, 0xa220, 0xa103, 0xf2eb, 0xa230,
+    0xa103, 0xf2bb, 0xa23c, 0xa103, 0xf24b, 0xa258, 0xa103, 0xf25b,
+    0xa260, 0xa103, 0xf22b, 0xa200, 0xa103, 0xf1fb, 0xa26c, 0xa103,
+    0xf1cb, 0xe004, 0x003e, 0xa103, 0xf18b, 0xe004, 0x0044, 0xa105,
+    0xf14b, 0xe004, 0x0046, 0xa103, 0xf10b, 0xe004, 0x0000, 0xa107,
+    0xf0cb, 0xa200, 0xe0c1, 0x005e, 0xf08b, 0xe004, 0x004c, 0xf05e,
+    0xe0c1, 0x005e, 0xf02b, 0xa010, 0xae16, 0xe0c1, 0x0040, 0xe041,
+    0xca28, 0xf7f8, 0xce21, 0xd111, 0x0000, 0xd112, 0x2000, 0xd113,
+    0x000b, 0xe1e1, 0xe42e, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100,
+    0xe004, 0x0133, 0xe67c, 0xe41e, 0x0100, 0xe004, 0x0135, 0xe67c,
+    0x28ee, 0xe008, 0x03ff, 0xcca4, 0xe182, 0x0029, 0xe018, 0x2eee,
+    0xaf15, 0xcca5, 0xe182, 0x0029, 0xe019, 0xae15, 0xe042, 0xae14,
+    0x34f0, 0x3cf1, 0xe42e, 0xe40e, 0x10bf, 0xe40e, 0x0137, 0xe40e,
+    0x013b, 0xe40e, 0x014b, 0xe40e, 0x013f, 0xe40e, 0x007e, 0xe40e,
+    0x0143, 0xe40e, 0x007e, 0xe40e, 0x0147, 0xe40e, 0x007e, 0xe40e,
+    0x007e, 0xe40e, 0x007e, 0xe40e, 0x007e, 0xe40e, 0x007e, 0xe40e,
+    0x007e, 0xe40e, 0x007e, 0xe40e, 0x0155, 0xe40e, 0x0168, 0xe41e,
+    0x1800, 0xe40e, 0x007e, 0xe41e, 0x18ae, 0xe40e, 0x007e, 0xe41e,
+    0x18af, 0xe40e, 0x007e, 0xe41e, 0x01f4, 0xe40e, 0x007e, 0xe41e,
+    0x18cc, 0xe40e, 0x007e, 0x2885, 0xf058, 0xe41e, 0x01fe, 0xe40e,
+    0x007e, 0xe41e, 0x197f, 0xe40e, 0x007e, 0xe0c0, 0x005a, 0x3cee,
+    0xe41e, 0x0100, 0xa206, 0xe41e, 0x0171, 0xe0c0, 0x005a, 0x3cee,
+    0xe41e, 0x0100, 0xa226, 0xe41e, 0x0187, 0xe41e, 0x019d, 0xe42e,
+    0xa224, 0xe41e, 0x0187, 0xe41e, 0x01b8, 0xa204, 0xe41e, 0x0171,
+    0xe42e, 0x3ced, 0xe0c0, 0x0041, 0xe005, 0x0280, 0xae11, 0xe042,
+    0x22f0, 0x4ef1, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0000,
+    0xd112, 0x0c00, 0x88ed, 0x0113, 0xca28, 0xf7f8, 0xe42e, 0x3ced,
+    0xe0c0, 0x0041, 0xe005, 0x0298, 0xae11, 0xe042, 0x22f0, 0x4ef1,
+    0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0000, 0xd112, 0x0100,
+    0x88ed, 0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe161, 0x07e0, 0x8911,
+    0x0034, 0x8911, 0x0033, 0x8911, 0x0035, 0x8911, 0x0036, 0x8911,
+    0x0037, 0x8911, 0x0038, 0x2111, 0x4d11, 0xcc60, 0x2111, 0x4d11,
+    0xcc62, 0x2111, 0x4d11, 0xcc64, 0x2111, 0x4d11, 0xcc72, 0xe42e,
+    0xe161, 0x07e0, 0x8b11, 0x0034, 0x8b11, 0x0033, 0x8b11, 0x0035,
+    0x8b11, 0x0036, 0x8b11, 0x0037, 0x8b11, 0x0038, 0xc860, 0x3511,
+    0x3d11, 0xc862, 0x3511, 0x3d11, 0xc864, 0x3511, 0x3d11, 0xc872,
+    0x3511, 0x3d11, 0xe42e, 0xe167, 0x0212, 0xa200, 0x3c06, 0xd022,
+    0x0007, 0xe184, 0x01e1, 0x2b17, 0xa81f, 0x5a06, 0xe056, 0x2a06,
+    0xa009, 0x3e06, 0xe0c2, 0x007d, 0xa200, 0x3c06, 0xd022, 0x0007,
+    0xe184, 0x01f0, 0x2b17, 0xa81f, 0x5a06, 0xe056, 0x2a06, 0xa009,
+    0x3e06, 0xe0c2, 0x007e, 0xe42e, 0xa200, 0x3c9a, 0x3c99, 0x3c4a,
+    0x3c4b, 0x3c6e, 0x3c6f, 0xa202, 0x3c9c, 0xe42e, 0x288b, 0xe418,
+    0x10cf, 0xa200, 0xcc4a, 0xcc4c, 0xcc72, 0x3c8b, 0x3ce7, 0x3cd9,
+    0x3c3f, 0x3c9d, 0x3c9e, 0x3c9f, 0xe0c2, 0x0074, 0xa2fc, 0xe0c2,
+    0x0077, 0xa2fa, 0xe0c2, 0x0071, 0xa202, 0xe0c2, 0x0076, 0xe0c0,
+    0x006c, 0xe002, 0x0088, 0x3cdd, 0xe0c0, 0x0065, 0xaf0a, 0x30e3,
+    0xe41e, 0x11a4, 0xe408, 0x039a, 0x2890, 0xf24a, 0x2892, 0xa108,
+    0xf218, 0x28a4, 0xf064, 0xe000, 0x02b2, 0xe09e, 0x2907, 0x3c74,
+    0xe41e, 0x0fa9, 0xe419, 0x0f6e, 0x28a2, 0x2a63, 0xf02b, 0x28a6,
+    0x3ca5, 0xe0c2, 0x0071, 0x3ca4, 0xa200, 0x3c92, 0xa202, 0x3c76,
+    0x244a, 0x4c4b, 0xa002, 0x344a, 0x3c4b, 0xe41e, 0x0547, 0xe40e,
+    0x038a, 0xe41e, 0x03eb, 0xe42a, 0x2883, 0xe428, 0xe0c0, 0x0065,
+    0xa802, 0xe0c2, 0x0075, 0xa2fe, 0xe0c2, 0x0077, 0xe41e, 0x0547,
+    0xe41e, 0x0538, 0xe42a, 0xa2fc, 0xe0c2, 0x0077, 0xd130, 0x0003,
+    0xd03a, 0x0003, 0xd04b, 0x0001, 0xd04c, 0x0000, 0xd008, 0x0000,
+    0xa200, 0xe0c2, 0x030a, 0x3c46, 0x2830, 0xe418, 0x05b2, 0xe404,
+    0x039a, 0x2830, 0xe41a, 0x055e, 0xe404, 0x039a, 0xe40d, 0x03d1,
+    0x288f, 0xf08a, 0x2825, 0xf718, 0x288d, 0xf36a, 0xa102, 0x3c8d,
+    0xf6ce, 0xe0c0, 0x0066, 0xf30a, 0x288e, 0xf2ea, 0xa102, 0xf04a,
+    0xa102, 0xf05a, 0xf07e, 0x2825, 0xf27a, 0xf04e, 0x2825, 0xa104,
+    0xf238, 0x288d, 0xa102, 0xf04a, 0x3c8d, 0xe40e, 0x026c, 0xe0c0,
+    0x0066, 0xa102, 0xf196, 0xe41e, 0x0480, 0x2825, 0xa104, 0xe01a,
+    0xae12, 0x4cae, 0xae2a, 0x4c25, 0xe0c2, 0x0073, 0xa204, 0xe0c2,
+    0x0075, 0xa200, 0xe0c2, 0x0072, 0xa2fc, 0x3ca5, 0xe0c2, 0x0071,
+    0x3ca4, 0xe40e, 0x039a, 0x2890, 0xf22a, 0x282e, 0xf208, 0x287d,
+    0xf1ea, 0x28a4, 0xf064, 0xe000, 0x02b2, 0xe09e, 0x2907, 0x3c74,
+    0xe41e, 0x0fa9, 0xe419, 0x0f6e, 0xa200, 0x3c7d, 0x28a3, 0x3ca5,
+    0xe0c2, 0x0071, 0x3ca4, 0xa206, 0x3c92, 0xa202, 0x3c76, 0x244a,
+    0x4c4b, 0xa002, 0x344a, 0x3c4b, 0xe40e, 0x038a, 0x2825, 0xa802,
+    0x447d, 0xf06a, 0x28a3, 0xe41e, 0x04fb, 0xa200, 0x3c7d, 0x2890,
+    0xf19a, 0x2825, 0xf178, 0x2892, 0xa106, 0xf14a, 0x2892, 0xa806,
+    0xe01a, 0xf10a, 0x287f, 0xf0ea, 0x28a3, 0xe000, 0x0212, 0xe092,
+    0x2901, 0xe049, 0xa809, 0xf06b, 0xa806, 0x3d01, 0xa200, 0x3c92,
+    0x3c7d, 0xe41e, 0x0b4f, 0x286d, 0xa80c, 0xe016, 0x4466, 0xe408,
+    0x03d1, 0x282e, 0x2a3f, 0xe017, 0x3e70, 0x2ac3, 0xa103, 0xe017,
+    0x4e70, 0xe052, 0xf218, 0xe162, 0x0200, 0xa200, 0xc711, 0x3d12,
+    0x3c44, 0x3c3e, 0x3c0d, 0x3c0c, 0x3cb5, 0x3cb6, 0x3c6c, 0x3c0b,
+    0x282e, 0xf068, 0x2825, 0xa104, 0xf038, 0xa200, 0x3c66, 0x2852,
+    0x3c43, 0xa202, 0x3c42, 0xe004, 0x1000, 0xcf02, 0xe41e, 0x1382,
+    0xa200, 0x3c46, 0xf0fe, 0x2836, 0xe016, 0x4430, 0xf078, 0xe41e,
+    0x1251, 0xe40a, 0x03d1, 0xe40e, 0x0339, 0xe41e, 0x12ab, 0xe40a,
+    0x03d1, 0xe41e, 0x0d8f, 0x264a, 0x4e4b, 0xa003, 0x364a, 0x3e4b,
+    0xa103, 0x2890, 0xe40a, 0x0383, 0x2825, 0xf0ea, 0xa102, 0xf15a,
+    0xa102, 0xf138, 0x2892, 0xa102, 0xf038, 0xa202, 0x3c7d, 0xa204,
+    0x3c92, 0xe40e, 0x0383, 0x28a2, 0x2a63, 0xf02b, 0x28a6, 0xe0c2,
+    0x0071, 0x3ca5, 0x3ca4, 0xf2fe, 0xe41e, 0x0a5f, 0xba3e, 0xe002,
+    0x01b6, 0xf10a, 0x2892, 0xa102, 0xf048, 0xa208, 0x3c92, 0xf23e,
+    0x28a2, 0x2a63, 0xf02b, 0x28a6, 0xe0c2, 0x0071, 0x3ca5, 0x3ca4,
+    0xf1ae, 0x2892, 0xa102, 0xf028, 0xf16e, 0xa2fe, 0x3ca5, 0x3ca4,
+    0xa202, 0x3c92, 0x244a, 0x4c4b, 0xa102, 0x344a, 0x3c4b, 0xa2fa,
+    0xe0c2, 0x0071, 0xf08e, 0xf079, 0xa2fe, 0x3ca5, 0x3ca4, 0xa2fa,
+    0xe0c2, 0x0071, 0x244a, 0x4c4b, 0xe0c2, 0x0070, 0x2825, 0xa104,
+    0xe01a, 0xae12, 0x4cae, 0xae2a, 0x4c25, 0xe0c2, 0x0073, 0x2846,
+    0xe0c2, 0x0072, 0x286d, 0xa808, 0xf09a, 0xe41e, 0x0494, 0x287f,
+    0xf138, 0xa2fe, 0xe0c2, 0x0071, 0xf0fe, 0x287f, 0xf0d8, 0xe0c0,
+    0x0077, 0x2a63, 0xf06b, 0x2a2e, 0xe017, 0x4690, 0x28a6, 0xb7d2,
+    0xe0c2, 0x0071, 0x3ca4, 0x2889, 0xae20, 0x4c8a, 0xe0c2, 0x006f,
+    0xe0c2, 0x004f, 0xc84a, 0xc84d, 0xae20, 0xe056, 0xe0c2, 0x0053,
+    0xe41e, 0x0521, 0x2825, 0xa104, 0xe01a, 0xae12, 0x4cae, 0xae2a,
+    0x4c25, 0xe0c2, 0x0073, 0xe41e, 0x01d3, 0xe41e, 0x11de, 0xa202,
+    0xe42e, 0x2889, 0xae20, 0x4c8a, 0xe0c2, 0x006f, 0xe0c2, 0x004f,
+    0x2825, 0xa104, 0xe01a, 0xae12, 0x4cae, 0xae2a, 0x4c25, 0xe0c2,
+    0x0073, 0xa2fc, 0xe0c2, 0x0077, 0xe41e, 0x0521, 0xe16a, 0xa200,
+    0xe0c2, 0x0076, 0xe42e, 0xe0c0, 0x0065, 0x3082, 0xaf02, 0x3083,
+    0xaf02, 0x308f, 0xaf02, 0xa806, 0x3c8e, 0xe0c0, 0x0066, 0x3c8d,
+    0x288f, 0xf06a, 0xa200, 0x3082, 0x3083, 0xe40e, 0x047b, 0x288d,
+    0xf028, 0x3c8e, 0x288e, 0xf09a, 0x288d, 0xa102, 0xf04a, 0xa200,
+    0x3c82, 0xf03e, 0xa202, 0x3c82, 0x2882, 0xe40a, 0x047b, 0x28ee,
+    0x3c84, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100, 0xa224, 0xe41e,
+    0x0187, 0xe41e, 0x01b8, 0xa204, 0xe41e, 0x0171, 0x2830, 0xf048,
+    0xe41e, 0x055e, 0xf03e, 0xe41e, 0x05b2, 0xf11d, 0x2881, 0xf0f8,
+    0xa206, 0x3c82, 0xa200, 0x3c81, 0x2830, 0xf048, 0xe41e, 0x055e,
+    0xf03e, 0xe41e, 0x05b2, 0xf03d, 0x2881, 0xf0aa, 0xa200, 0x3c81,
+    0xe41e, 0x00f3, 0xa200, 0x3c82, 0xe0c2, 0x0075, 0xe42e, 0x288d,
+    0xf33a, 0x288e, 0xf31a, 0xa102, 0xf04a, 0xa102, 0xf05a, 0xf07e,
+    0x2825, 0xf2aa, 0xf04e, 0x2825, 0xa104, 0xf268, 0xe082, 0x3c14,
+    0xe004, 0x0048, 0xe092, 0x2010, 0x4c11, 0x2e13, 0xae11, 0xe042,
+    0x9f01, 0x2814, 0xe092, 0xa200, 0x3c82, 0x2825, 0xa104, 0xe01a,
+    0xae12, 0x4cae, 0xae2a, 0x4c25, 0xe0c2, 0x0073, 0xa202, 0xe0c2,
+    0x0075, 0xa200, 0xe0c2, 0x0072, 0xa2fa, 0xe0c2, 0x0071, 0x3ca5,
+    0x3ca4, 0xa200, 0xe42e, 0xe41e, 0x00f3, 0xa200, 0x3c82, 0xa202,
+    0xe0c2, 0x0075, 0xf04e, 0xa204, 0xe0c2, 0x0075, 0xa202, 0xe42e,
+    0x2830, 0xf0a8, 0xe41e, 0x0a5f, 0xe41e, 0x0a5f, 0xba2e, 0xa102,
+    0xe42a, 0xba4e, 0xf7ae, 0xe41e, 0x0a5f, 0xba2a, 0xa140, 0xe42a,
+    0xa13e, 0xe42a, 0xba4e, 0xf78e, 0xa200, 0xe0c2, 0x0072, 0x289c,
+    0xf0e6, 0x289c, 0xa102, 0x3c9c, 0xe41e, 0x04b7, 0x2a63, 0x28a1,
+    0xf02b, 0x28a3, 0xe0c2, 0x0071, 0x3ca4, 0xe42e, 0x289c, 0xe424,
+    0x28a1, 0x2a63, 0xf02b, 0x28a3, 0x3ca3, 0xe0c1, 0x0060, 0xaf09,
+    0xa807, 0xe419, 0x04b7, 0xa2fe, 0xe0c2, 0x0071, 0xe42e, 0x28a4,
+    0xe424, 0xe000, 0x02b2, 0xe09e, 0x2907, 0x3c74, 0xe41e, 0x0fa9,
+    0xe419, 0x0f6e, 0xe42e, 0xa200, 0x3c4a, 0x3c4b, 0x3c74, 0x3c75,
+    0xa2fe, 0x3ca2, 0x3ca3, 0x3ca4, 0x3ca5, 0x3ca0, 0x3ca1, 0xa200,
+    0x3c6d, 0x3ca7, 0x3c76, 0xe161, 0x0212, 0x2a4d, 0xa103, 0x3e70,
+    0x8670, 0x3d11, 0xe42e, 0x28a7, 0x3c06, 0x2806, 0xe000, 0x0212,
+    0xe092, 0x2901, 0xf0da, 0x2806, 0xa002, 0x3c06, 0x184d, 0xf038,
+    0xa200, 0x3c06, 0x2806, 0x18a7, 0xf718, 0xa2fe, 0xe42e, 0xa208,
+    0xb652, 0x3d01, 0x2806, 0xa002, 0x3ca7, 0x184d, 0xf038, 0xa200,
+    0x3ca7, 0x2806, 0xe42e, 0xe424, 0xe000, 0x0212, 0xe092, 0xa200,
+    0x3d01, 0xe42e, 0xe000, 0x0212, 0xe092, 0x2901, 0xe056, 0x3d01,
+    0xe42e, 0xe424, 0xe000, 0x0212, 0xe092, 0x2901, 0xa806, 0x3d01,
+    0xe42e, 0xe424, 0xe000, 0x0212, 0xe092, 0x2901, 0xa908, 0x3d01,
+    0xe42e, 0xe424, 0xe000, 0x0212, 0xe092, 0x2901, 0xa80a, 0x3d01,
+    0xe42e, 0xe004, 0x0212, 0xe09e, 0xe004, 0x0054, 0xe09c, 0x284d,
+    0xa102, 0xcc44, 0xa200, 0x3c06, 0xe184, 0x0535, 0x2b17, 0xaf05,
+    0xa803, 0x5a06, 0xe056, 0x2a06, 0xa003, 0x3e06, 0x9f06, 0xe42e,
+    0xe161, 0x0212, 0x284d, 0xa102, 0xcc44, 0xa200, 0xe184, 0x0543,
+    0x2b11, 0xa80d, 0xe01b, 0xe042, 0x184d, 0xe01a, 0xe42e, 0xa200,
+    0x3c06, 0x284d, 0xa102, 0xcc44, 0xe184, 0x055c, 0xe0c0, 0x0054,
+    0x5c06, 0xa802, 0xf058, 0x2806, 0xe41e, 0x0509, 0xf04e, 0x2806,
+    0xe41e, 0x0511, 0x2a06, 0xa003, 0x3e06, 0xe42e, 0xa200, 0x3cae,
+    0xd198, 0x0000, 0xd180, 0x0000, 0xd190, 0x0004, 0x8881, 0x0198,
+    0xcb20, 0xf7d8, 0xe41e, 0x11a4, 0xe428, 0x2885, 0xf08a, 0xc872,
+    0x2687, 0x4e88, 0xae07, 0xe045, 0xa200, 0xe427, 0xba7e, 0xe002,
+    0x0100, 0xf374, 0xa13e, 0xf030, 0xe40e, 0x0564, 0xa102, 0xf314,
+    0xe002, 0x000f, 0xf060, 0xe41e, 0x066c, 0xf2ba, 0xe40e, 0x0564,
+    0xe002, 0x0081, 0xf058, 0xe41e, 0x0644, 0xe40e, 0x0564, 0xa104,
+    0xf058, 0xe41e, 0x090f, 0xe40e, 0x0564, 0xa102, 0xf058, 0xe41e,
+    0x0737, 0xe40e, 0x0564, 0xa104, 0xf058, 0xe41e, 0x064b, 0xe40e,
+    0x0564, 0xa102, 0xf058, 0xe41e, 0x0742, 0xf0ba, 0xe42e, 0x2a76,
+    0xe40b, 0x0564, 0xa11a, 0xe408, 0x0564, 0xba7e, 0xe40e, 0x0564,
+    0xe16b, 0xe42e, 0x282f, 0xe01a, 0xae0c, 0xa920, 0xcf00, 0xd198,
+    0x0000, 0xd190, 0x0004, 0x8881, 0x0198, 0xcb20, 0xf7d8, 0xe41e,
+    0x11a4, 0xe428, 0x2885, 0xf08a, 0xc872, 0x2687, 0x4e88, 0xae07,
+    0xe045, 0xa200, 0xe427, 0x282f, 0xf06a, 0xba60, 0xe41e, 0x0a8c,
+    0xf07a, 0xe42e, 0xba6a, 0xe41e, 0x0805, 0xf02a, 0xe42e, 0xe16b,
+    0xe42e, 0xba5e, 0x2860, 0xa120, 0x3c48, 0x7448, 0x2852, 0xe41e,
+    0x0a3a, 0x3c48, 0x7448, 0x3c01, 0x1852, 0xf034, 0x2852, 0x3c01,
+    0xba48, 0x3c28, 0xba40, 0xe40a, 0x0625, 0xa201, 0xba40, 0xb431,
+    0xf7e8, 0xba40, 0xe40a, 0x0625, 0x2c21, 0xe41e, 0x0a3a, 0x3c48,
+    0x7448, 0x3c2c, 0xba40, 0xe40a, 0x0625, 0xba42, 0x3c25, 0xa106,
+    0xe016, 0x3c3f, 0xba44, 0xe000, 0x0120, 0xe09e, 0x2907, 0x3c27,
+    0x2825, 0xf1ca, 0xba44, 0x3c29, 0x3c0c, 0xa102, 0x3c2a, 0x3c1d,
+    0xa202, 0x582a, 0xa102, 0x3c2b, 0x3c1e, 0x2825, 0xa104, 0xf0e8,
+    0xba44, 0x3c0d, 0xa102, 0x3c1f, 0xa202, 0x581f, 0xa102, 0x3c20,
+    0xe004, 0x0040, 0x4c0d, 0xae0c, 0x4c0c, 0x2801, 0xe42e, 0x3c05,
+    0xf028, 0xba60, 0xba40, 0xf17a, 0x2852, 0xe41e, 0x0a44, 0x3c48,
+    0x7648, 0x3e01, 0xa116, 0xf046, 0xf037, 0xba40, 0xf0ca, 0x2805,
+    0xf038, 0xba48, 0x3c28, 0xba40, 0xf06a, 0x2805, 0xf028, 0xba42,
+    0x2801, 0xe42e, 0xa2fe, 0xe42e, 0xba4e, 0x3ce0, 0xa200, 0x3cd8,
+    0xe41e, 0x090a, 0xe42e, 0xba40, 0xf08a, 0xba46, 0xa102, 0xe424,
+    0xa108, 0xe420, 0xba44, 0xe42a, 0xba46, 0xa102, 0xe428, 0xba40,
+    0xf08a, 0xba44, 0xba40, 0xba40, 0xf04a, 0xba4e, 0xba4e, 0xba4e,
+    0xe41e, 0x0a14, 0xe42a, 0xa202, 0x3cd8, 0xe41e, 0x090a, 0xe41e,
+    0x0a14, 0xe42a, 0xba7e, 0xe42e, 0xa202, 0x3c00, 0xba40, 0xba4e,
+    0x3ce1, 0xba40, 0xf0ba, 0xba46, 0xa102, 0xe404, 0x0735, 0xa108,
+    0xe400, 0x0735, 0xa00a, 0x3c00, 0xba44, 0xba46, 0x3c7e, 0xa11e,
+    0xf0a8, 0xba4e, 0xe40a, 0x0735, 0xba4f, 0xe40b, 0x0735, 0xae11,
+    0xe056, 0x3ce2, 0xba40, 0xf1da, 0xba42, 0xa102, 0xe408, 0x0735,
+    0xba40, 0xba40, 0xf16a, 0xba5c, 0xba40, 0xe40a, 0x0735, 0xba5c,
+    0xba40, 0xe40a, 0x0735, 0xba5c, 0xba40, 0xe40a, 0x0735, 0xba44,
+    0xba54, 0xba40, 0xe40a, 0x0735, 0xba5c, 0xba40, 0xe40a, 0x0735,
+    0xba42, 0xe408, 0x0735, 0xba40, 0xe40a, 0x0735, 0xa202, 0x3c22,
+    0xba5e, 0xe40a, 0x0735, 0x3c21, 0xba40, 0xe40a, 0x0735, 0xba40,
+    0x3ceb, 0xe40a, 0x06c3, 0x2c21, 0xe41e, 0x0a3a, 0x3c48, 0x7448,
+    0xe40a, 0x0735, 0x3c22, 0xba40, 0xe40a, 0x0735, 0xba58, 0x3c89,
+    0xa01e, 0xaf08, 0x3c50, 0xba41, 0xba58, 0x3c8a, 0xa01e, 0xaf08,
+    0x3c51, 0xe40a, 0x0735, 0xe002, 0x0080, 0xe400, 0x0735, 0x2850,
+    0xe40a, 0x0735, 0xe002, 0x0080, 0xe400, 0x0735, 0xe40b, 0x0735,
+    0xba40, 0xe40a, 0x0735, 0xba40, 0x3cad, 0xba40, 0xe40a, 0x0735,
+    0x2a00, 0xa103, 0xb636, 0xb652, 0x3c48, 0x7648, 0xf11b, 0xa103,
+    0xe40b, 0x0735, 0xa103, 0xe04a, 0xe016, 0x3cc2, 0xa103, 0xe40b,
+    0x0735, 0xba4a, 0x3cc3, 0xba42, 0x3cc5, 0xba40, 0x3cc4, 0xba40,
+    0xe408, 0x0735, 0xba40, 0x3c0e, 0xf07a, 0xba40, 0xe418, 0x0a64,
+    0xba40, 0xe418, 0x0a78, 0x2800, 0xa102, 0xe40a, 0x0711, 0xba40,
+    0x3c94, 0xba40, 0xe40a, 0x0735, 0xba40, 0xba40, 0x3c23, 0xe40a,
+    0x071a, 0xba40, 0x3c24, 0x2800, 0xa102, 0xe40a, 0x0724, 0xba40,
+    0xf03a, 0xba42, 0xba40, 0xba40, 0x3c2d, 0xba40, 0xe408, 0x0735,
+    0xe41e, 0x0a14, 0xf0ba, 0xa204, 0x3cd8, 0xe41e, 0x090a, 0x8450,
+    0x8251, 0xe018, 0x3c52, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xba62,
+    0xba40, 0xba40, 0xe41e, 0x0a14, 0xe42a, 0xa206, 0x3cd8, 0xe41e,
+    0x090a, 0xe42e, 0xa200, 0x3cae, 0x3cac, 0xba42, 0x3c25, 0xa106,
+    0xe016, 0x3c3f, 0xa201, 0xba40, 0xb431, 0xf7e8, 0x3e70, 0xba40,
+    0xe40a, 0x0803, 0x2c21, 0xe41e, 0x0a3a, 0xa102, 0xf022, 0xa200,
+    0xa002, 0x3c48, 0x7448, 0x3c2c, 0x2aeb, 0xae3f, 0xe056, 0xe0c2,
+    0x004e, 0x2825, 0xa104, 0xf0fa, 0x28a9, 0x3ca8, 0x0870, 0x3ca9,
+    0x84a9, 0x8221, 0xe018, 0x082c, 0x3c4e, 0x28b0, 0x3caf, 0x284e,
+    0x3cb0, 0xf1ee, 0x28a8, 0x0870, 0x3c70, 0x8470, 0x8221, 0xe018,
+    0x082c, 0x3c4e, 0x28b2, 0xf048, 0x284e, 0x18af, 0x3cb2, 0x28af,
+    0xc70f, 0x7cb2, 0x3c70, 0x28b0, 0xc70f, 0x7cb2, 0x1870, 0xae02,
+    0x3cb3, 0x284e, 0xc70f, 0x7cb2, 0x1870, 0xae02, 0x3cb4, 0xba40,
+    0xe40a, 0x0803, 0xba40, 0x3c2e, 0xe40a, 0x0801, 0xa200, 0x3c26,
+    0x2825, 0xa102, 0xf05a, 0xa104, 0xf058, 0x28c2, 0xf03a, 0xba40,
+    0x3c26, 0x282d, 0xf07a, 0x2825, 0xa104, 0xf042, 0xba40, 0xe408,
+    0x0803, 0xba44, 0xe000, 0x0120, 0xe09e, 0x2907, 0x3c27, 0x28ad,
+    0xf05a, 0xba40, 0x3cae, 0xba40, 0x3cac, 0x283f, 0x44c2, 0x2ac3,
+    0xe01b, 0xe052, 0xf23a, 0xe162, 0x02f0, 0xd022, 0x0001, 0xe184,
+    0x07d5, 0xb83c, 0xe40d, 0x0803, 0xf0ea, 0xa102, 0x3c70, 0xba40,
+    0xf078, 0xa205, 0x5a70, 0xa103, 0x7470, 0xe046, 0xf04e, 0x5870,
+    0x7670, 0xe056, 0x3d12, 0xba40, 0xe40a, 0x0803, 0x28c4, 0xf06a,
+    0xb83e, 0xe40d, 0x0803, 0x3c70, 0x7470, 0xba48, 0x3c28, 0x2825,
+    0xe40a, 0x0801, 0xba44, 0x3c29, 0x3c0c, 0xe40a, 0x0803, 0xa102,
+    0x3c2a, 0x3c1d, 0xa202, 0x582a, 0xa102, 0x3c2b, 0x3c1e, 0x2825,
+    0xa104, 0xf108, 0xba44, 0x3c0d, 0xe40a, 0x0803, 0xa102, 0x3c1f,
+    0xa202, 0x581f, 0xa102, 0x3c20, 0xe004, 0x0040, 0x4c0d, 0xae0c,
+    0x4c0c, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xa200, 0x3c7e, 0xba4e,
+    0x3c2c, 0xba40, 0xe40a, 0x0908, 0xba40, 0xe408, 0x0908, 0xba40,
+    0xba40, 0xba40, 0xba44, 0x3c02, 0xa10e, 0xe40a, 0x0831, 0xba40,
+    0x3c25, 0xba40, 0x3c39, 0xba44, 0xe408, 0x0908, 0xba48, 0x3c28,
+    0xba40, 0xe408, 0x0908, 0xe41e, 0x0a27, 0xe40a, 0x0908, 0xa200,
+    0x3c34, 0x3c35, 0x3c36, 0x3c37, 0x3c3a, 0x3c26, 0x3c38, 0xe40e,
+    0x08c6, 0xa202, 0x3c3a, 0xa200, 0x3c02, 0xba44, 0x3c03, 0xa102,
+    0xe400, 0x0908, 0xe404, 0x0859, 0xba44, 0x3c02, 0xa10c, 0xe418,
+    0x0a27, 0xba40, 0x3c38, 0xba40, 0x3c39, 0xba42, 0xe408, 0x0908,
+    0xba40, 0x3c34, 0xba40, 0x3c35, 0xba40, 0x3c36, 0xba44, 0xe408,
+    0x0908, 0xba40, 0x3c37, 0xba40, 0xe40a, 0x0908, 0xba44, 0xe408,
+    0x0908, 0xba44, 0xa102, 0xe400, 0x0908, 0xa002, 0x3c25, 0xba42,
+    0xe408, 0x0908, 0xba40, 0x3c26, 0xba44, 0xa102, 0xe408, 0x0908,
+    0xba40, 0xe408, 0x0908, 0x2802, 0xa10c, 0xf228, 0x2803, 0xf20a,
+    0xba46, 0x3c7e, 0xe40a, 0x0908, 0xba50, 0xa002, 0xae04, 0x3c89,
+    0xa01e, 0xaf08, 0x3c50, 0x3c32, 0xba40, 0xe40a, 0x0908, 0xba50,
+    0xae04, 0x3c8a, 0xa01e, 0xaf08, 0x3c51, 0x3c31, 0xa132, 0xe406,
+    0x088f, 0x2832, 0xae02, 0x3c32, 0x2831, 0xaf02, 0x3c31, 0x287e,
+    0xf0ca, 0xa11e, 0xf0a8, 0xba4e, 0xe40a, 0x0908, 0xba4f, 0xe40b,
+    0x0908, 0xae11, 0xe056, 0x3ce2, 0x2838, 0x4403, 0xf11a, 0xba40,
+    0xe000, 0x03e8, 0xba4d, 0xe40b, 0x0908, 0x3c22, 0x3e21, 0xe004,
+    0x1b77, 0xae10, 0xe00a, 0x0040, 0xc70f, 0x7c21, 0x3c21, 0x2838,
+    0xf05a, 0xba42, 0xae10, 0x4c2c, 0x3c2c, 0x2839, 0x4403, 0xf07a,
+    0xba40, 0x3c3b, 0xf048, 0xba40, 0xe40a, 0x0908, 0x2836, 0x4403,
+    0xf04a, 0xba42, 0xe408, 0x0908, 0xba48, 0x3c28, 0xba40, 0xf03a,
+    0xba4e, 0xf7de, 0x8450, 0x8251, 0xe018, 0x3c52, 0x2836, 0xf05a,
+    0xa202, 0xe41e, 0x0627, 0xf358, 0x2838, 0xf078, 0xe004, 0x03e9,
+    0x3c22, 0xe004, 0x7530, 0x3c21, 0xa200, 0x3c23, 0x3c24, 0xa202,
+    0x3c29, 0x3c0c, 0x3c2e, 0xa200, 0x3c2a, 0x3c2b, 0xe167, 0x0120,
+    0x2907, 0x3c27, 0x2839, 0xf1ba, 0x283a, 0xf038, 0xa200, 0xf17e,
+    0x283b, 0xf15a, 0xa204, 0x2a50, 0xa12d, 0xf057, 0xa002, 0xa12d,
+    0xf027, 0xa002, 0x3c70, 0xa204, 0x2a51, 0xa125, 0xf057, 0xa002,
+    0xa125, 0xf027, 0xa002, 0xae06, 0x4c70, 0xf01e, 0xa202, 0xe42e,
+    0xa200, 0xe42e, 0xba3e, 0xe002, 0x01b2, 0xe428, 0xba7e, 0xa200,
+    0x3cdf, 0x2ae3, 0xe0c0, 0x0065, 0xaf0a, 0xa802, 0xe017, 0xe052,
+    0x3ce7, 0xe41e, 0x0b07, 0xf1aa, 0x28e3, 0xf3a8, 0x2891, 0xf098,
+    0xba2e, 0xa102, 0xe42a, 0xe41e, 0x0a0a, 0xe428, 0xba4e, 0xf79e,
+    0xba2e, 0xa102, 0xe42a, 0xe41e, 0x0a0a, 0xe428, 0xba4e, 0xe002,
+    0x0070, 0xf778, 0xa202, 0x3c0f, 0xf74e, 0x28e3, 0xf218, 0xe42e,
+    0xe164, 0x0530, 0xe163, 0x052c, 0xe162, 0x0528, 0xd022, 0x0003,
+    0xe184, 0x0954, 0xba2e, 0xa102, 0xe42a, 0xba4e, 0x3d03, 0x2adf,
+    0xa803, 0xf049, 0xae10, 0x3cde, 0xf03e, 0x4cde, 0x3d14, 0x2913,
+    0x1912, 0x2adf, 0xa003, 0x3edf, 0xe428, 0xa202, 0xe42e, 0x2ae3,
+    0x28d9, 0xa120, 0xb615, 0x3ee3, 0xf42b, 0x2891, 0xf168, 0xba2e,
+    0xa102, 0xf2fa, 0xba4e, 0x2adf, 0xa803, 0xf049, 0xae10, 0x3cde,
+    0xf03e, 0x4cde, 0x3d14, 0x2adf, 0xa003, 0x3edf, 0xa80f, 0xe41b,
+    0x09eb, 0x28e3, 0xf31a, 0xf6ce, 0xba2e, 0xa102, 0xf1aa, 0xba4e,
+    0xe002, 0x0070, 0xf038, 0xa203, 0x3e0f, 0xe000, 0x0070, 0x2adf,
+    0xa803, 0xf049, 0xae10, 0x3cde, 0xf03e, 0x4cde, 0x3d14, 0x2adf,
+    0xa003, 0x3edf, 0xa80f, 0xe41b, 0x09eb, 0x28e3, 0xf15a, 0xf65e,
+    0x2adf, 0xa803, 0xf03b, 0x28de, 0x3d14, 0xa211, 0x28df, 0xa80e,
+    0xf0ba, 0xe045, 0xaf03, 0xf06b, 0xa103, 0x3e70, 0xa201, 0x8670,
+    0x3f14, 0xe41e, 0x09eb, 0xa201, 0xba2e, 0xa102, 0xf04a, 0xba4e,
+    0xa203, 0xf7be, 0x3ee7, 0xe162, 0x0530, 0x28d8, 0x3d12, 0x28df,
+    0x3d12, 0x28e7, 0x3d12, 0xa200, 0x3d12, 0xe0c1, 0x006b, 0x28d9,
+    0xa002, 0xae06, 0xe041, 0xaf06, 0x3cd9, 0xca28, 0xf7f8, 0xe180,
+    0xce21, 0xd111, 0x0530, 0xd112, 0x0004, 0xd113, 0x0002, 0xe1e1,
+    0xe181, 0x28e3, 0xe428, 0xa200, 0x3cdb, 0xe0c0, 0x005c, 0xe0c1,
+    0x0065, 0xaf12, 0xa802, 0xaf15, 0xa803, 0xe016, 0xe056, 0xf04a,
+    0xa200, 0x3ce3, 0xe42e, 0x28dc, 0xf05a, 0xe0c0, 0x005d, 0xe42a,
+    0xf7be, 0xe0c0, 0x005d, 0xe00a, 0x0200, 0xe0c2, 0x005d, 0xa202,
+    0xce00, 0x3cdc, 0xf71e, 0xe0c0, 0x006b, 0xe000, 0x0088, 0x08db,
+    0xca29, 0xf7f9, 0xe180, 0xce20, 0xd111, 0x0530, 0xd112, 0x0004,
+    0xd113, 0x0002, 0xe1e1, 0xe181, 0xe164, 0x0530, 0x28da, 0x2adb,
+    0xa010, 0xa011, 0x3cda, 0x3edb, 0x1add, 0xe41b, 0x09cb, 0xa200,
+    0x3cdc, 0xe42e, 0x2885, 0xe42a, 0xc872, 0x2687, 0x4e88, 0xae07,
+    0xe045, 0xa200, 0xb62e, 0xe42e, 0xe41e, 0x0a5f, 0xba2e, 0xa102,
+    0xe016, 0x4c80, 0xe428, 0xba4e, 0x2885, 0xf08a, 0xc872, 0x2687,
+    0x4e88, 0xae07, 0xe045, 0xa202, 0xe427, 0xf71e, 0xe42e, 0x2802,
+    0xae04, 0xe000, 0x0100, 0xe09e, 0x2917, 0x3c89, 0xaf08, 0x3c50,
+    0x2917, 0x3c8a, 0xaf08, 0x3c51, 0x2917, 0x3c32, 0x2907, 0x3c31,
+    0xe01a, 0xe42e, 0xa102, 0xa201, 0xf04a, 0xaf02, 0xa003, 0xf7e8,
+    0xe04a, 0xe428, 0xa202, 0xe42e, 0xa102, 0xa15e, 0xf0d6, 0xa166,
+    0xf0d6, 0xe002, 0x0129, 0xf0c6, 0xe002, 0x04a4, 0xf0b6, 0xe002,
+    0x1290, 0xf0a6, 0xf0be, 0xa20c, 0xe42e, 0xa20e, 0xe42e, 0xa212,
+    0xe42e, 0xa216, 0xe42e, 0xa21a, 0xe42e, 0xa21c, 0xe42e, 0xc868,
+    0xa80e, 0x3c49, 0x7449, 0xe42e, 0xe004, 0x0040, 0xe165, 0x0232,
+    0xba4f, 0xf05b, 0x3e70, 0x3f15, 0xa102, 0xf7b0, 0xf06a, 0xa102,
+    0x3c71, 0x2a70, 0x8671, 0x3f15, 0x28aa, 0xa902, 0x3caa, 0xe42e,
+    0xe004, 0x0040, 0xe165, 0x0272, 0xba4f, 0xf05b, 0x3e70, 0x3f15,
+    0xa102, 0xf7b0, 0xf06a, 0xa102, 0x3c71, 0x2a70, 0x8671, 0x3f15,
+    0x28aa, 0xa904, 0x3caa, 0xe42e, 0xba48, 0xa002, 0x3c2f, 0xe406,
+    0x0ad4, 0xa104, 0xe400, 0x0ad4, 0xba4e, 0x3c2c, 0xba44, 0xe404,
+    0x0ad4, 0xa10c, 0xe400, 0x0ad4, 0xa008, 0xe41e, 0x0ad6, 0xba42,
+    0x3c25, 0xa102, 0xe400, 0x0ad4, 0xba40, 0xba48, 0x3c28, 0xba40,
+    0xf03a, 0xba4e, 0xf7de, 0xa200, 0x3c39, 0x3c34, 0x3c35, 0x3c36,
+    0x3c37, 0x3c3a, 0x3c26, 0x3c38, 0x3c23, 0x3c24, 0xa202, 0x3c29,
+    0x3c0c, 0x3c2e, 0xe167, 0x0120, 0x2907, 0x3c27, 0x2851, 0xa132,
+    0xe406, 0x0ac8, 0x2832, 0xae02, 0x3c32, 0x2831, 0xaf02, 0x3c31,
+    0x8450, 0x8251, 0xe018, 0x3c52, 0xe004, 0x03e9, 0x3c22, 0xe004,
+    0x7530, 0x3c21, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xf092, 0xa002,
+    0xf04a, 0xba4e, 0xba4f, 0xf21e, 0xba5e, 0xba5f, 0xf1ee, 0xa207,
+    0xe045, 0xf107, 0xae05, 0xe001, 0x0100, 0xe09f, 0x2917, 0x3c89,
+    0x2917, 0x3c8a, 0x2917, 0x3c32, 0x3c50, 0x2907, 0x3c31, 0x3c51,
+    0xe42e, 0xf07b, 0xe004, 0x00a0, 0xe005, 0x0078, 0xe40e, 0x0afc,
+    0xe004, 0x0140, 0xe005, 0x00f0, 0x3c89, 0x3e8a, 0xa01e, 0xa01f,
+    0xaf08, 0xaf09, 0x3c32, 0x3c50, 0x3e31, 0x3e51, 0xe42e, 0xe164,
+    0x0530, 0xba3f, 0xe004, 0x4469, 0xae20, 0xe00a, 0x7658, 0xe046,
+    0xf0ba, 0xe004, 0x5876, 0xae20, 0xe00a, 0x6944, 0xe046, 0xf1ca,
+    0xa200, 0x3cdf, 0xe42e, 0xa20a, 0x3cdf, 0xba4e, 0x3d14, 0xba4e,
+    0x3d14, 0xba4e, 0x3d14, 0xba4e, 0x3d14, 0xa202, 0x3c91, 0xba4e,
+    0x3d14, 0xa16a, 0xf02a, 0xe42e, 0x28d1, 0xf058, 0xa200, 0x3cd2,
+    0xa202, 0x3cd0, 0xe42e, 0xa208, 0x3cdf, 0xe004, 0x0058, 0x3d14,
+    0xe004, 0x0076, 0x3d14, 0xe004, 0x0069, 0x3d14, 0xe004, 0x0044,
+    0x3d14, 0xa202, 0x3cd1, 0xa200, 0x3cd0, 0xba1e, 0xa118, 0xf056,
+    0xa200, 0x3cd2, 0xa202, 0xe42e, 0xa202, 0x3cd2, 0xe42e, 0xa200,
+    0xcc8e, 0xe0c2, 0x0320, 0x3cd7, 0x3cd6, 0x3cd4, 0x2837, 0xae02,
+    0x4c36, 0xae02, 0x4c35, 0xae02, 0x4c34, 0xae04, 0x4c30, 0xae08,
+    0xa906, 0xe0c2, 0x0100, 0xe004, 0x00d6, 0xe0c2, 0x017c, 0xe004,
+    0x0014, 0xe0c2, 0x017d, 0xe0c0, 0x0050, 0x30bd, 0xaf02, 0x30be,
+    0xaf02, 0x30bc, 0xaf02, 0x30ec, 0xaf0a, 0x30bf, 0xaf02, 0x30c0,
+    0xaf02, 0x30c1, 0xaf02, 0x30ed, 0xe0c0, 0x0050, 0xaf1c, 0xa802,
+    0xe005, 0x0ba6, 0xe09f, 0x3d17, 0x28bf, 0x44bd, 0x3cbd, 0x28c0,
+    0x44be, 0x3cbe, 0x28c1, 0x44bc, 0x3cbc, 0x28ed, 0x44ec, 0x3cec,
+    0xa200, 0x2abd, 0xf03b, 0xe00a, 0x0002, 0x2abe, 0xf03b, 0xe00a,
+    0x0009, 0x2abc, 0xf03b, 0xe00a, 0x0020, 0x2aec, 0xf03b, 0xe00a,
+    0x0040, 0xe005, 0x0ba6, 0xe09f, 0x2b17, 0xae05, 0xe056, 0xe0c2,
+    0x0169, 0x2835, 0x4c63, 0xf19a, 0xe0c1, 0x0041, 0xe004, 0x0148,
+    0xae10, 0xe042, 0x2ac1, 0xf03b, 0x20cc, 0x4ccd, 0xe0c2, 0x0211,
+    0xe0c1, 0x0041, 0xe004, 0x0188, 0xae10, 0xe042, 0x2aed, 0xf03b,
+    0x20ce, 0x4ccf, 0xe0c2, 0x0212, 0xe0c0, 0x0041, 0xe005, 0x0011,
+    0xae11, 0xe042, 0x2ac0, 0xf03b, 0x20ca, 0x4ccb, 0xe0c2, 0x0103,
+    0xe161, 0x0460, 0x2111, 0x4d11, 0xcf42, 0xe0c1, 0x0041, 0xe004,
+    0x0140, 0xae10, 0xe042, 0x2abf, 0xf03b, 0x20c8, 0x4cc9, 0xcf44,
+    0x2aaa, 0xe0c3, 0x013d, 0xa803, 0xa200, 0xe419, 0x0de4, 0x2aaa,
+    0xa805, 0xa202, 0xe419, 0x0de4, 0x2ad2, 0xf05b, 0x2889, 0xae20,
+    0x4c8a, 0xf05e, 0x2850, 0xae20, 0x4c51, 0xae08, 0xe0c2, 0x0101,
+    0x2850, 0xae20, 0x4c51, 0xae08, 0xe0c2, 0x0283, 0xcf60, 0x2837,
+    0xcf68, 0x2a25, 0xa105, 0xe017, 0x462e, 0x3e66, 0x2830, 0xae04,
+    0x4c3e, 0xae02, 0x4c94, 0xae06, 0x4c0d, 0xae06, 0x4c0c, 0xcf46,
+    0x28d1, 0xae02, 0x4cd0, 0xae04, 0xa904, 0x4cad, 0xae04, 0x4c2f,
+    0xaf02, 0xae04, 0x4c30, 0xae02, 0xa902, 0xae04, 0x4c25, 0xae02,
+    0x4cae, 0xcf00, 0x2834, 0xae02, 0x4c35, 0xae02, 0x4c23, 0xae02,
+    0x4c24, 0xae02, 0x4c37, 0xcf24, 0xe0c0, 0x0044, 0xa80e, 0xae1a,
+    0x4c62, 0xe0c2, 0x0102, 0x2863, 0x4466, 0xf088, 0x2a63, 0xe41e,
+    0x04db, 0xe0c2, 0x0077, 0x3ca2, 0x3ca5, 0x28a0, 0x2a66, 0xe41b,
+    0x0519, 0x2a63, 0xf08b, 0xa201, 0xe41e, 0x04db, 0x3ca6, 0x3ca5,
+    0xe0c2, 0x0077, 0x2876, 0xf048, 0x2875, 0xaa02, 0x3c75, 0x28a4,
+    0xf064, 0xe000, 0x02b2, 0xe09e, 0x2907, 0x3c74, 0x28a5, 0xe000,
+    0x02b2, 0xe09e, 0x2875, 0x3d07, 0x2866, 0x3c76, 0xf188, 0x2825,
+    0xe016, 0x303e, 0x28a2, 0xa205, 0xe412, 0x0502, 0x28a3, 0x3ca5,
+    0x28a2, 0x2a63, 0xf07b, 0x287f, 0xf05a, 0x28a2, 0xe41e, 0x0509,
+    0x28a6, 0x3ca3, 0x28a1, 0x3ca0, 0x28a2, 0x3ca1, 0xa206, 0xae08,
+    0x4c25, 0xae06, 0xe0c1, 0x0065, 0xaf19, 0xa803, 0xae17, 0xe056,
+    0xe0c2, 0x0204, 0xa204, 0x2a35, 0x4e63, 0xb632, 0xe0c2, 0x0210,
+    0xa204, 0x2a63, 0x4666, 0x4e35, 0xb612, 0xe0c2, 0x0208, 0xf139,
+    0x84a2, 0xc786, 0xe018, 0xe000, 0x03a0, 0xe09e, 0x2117, 0x4d17,
+    0xe0c2, 0x020d, 0x2117, 0x4d17, 0xe0c2, 0x020e, 0x2117, 0x4d17,
+    0xe0c2, 0x020f, 0x2835, 0x4c63, 0xf16a, 0x84a6, 0x2a35, 0xf02b,
+    0x84a2, 0xc786, 0xe018, 0xe000, 0x03a0, 0xe09e, 0x2117, 0x4d17,
+    0xe0c2, 0x0214, 0x2117, 0x4d17, 0xe0c2, 0x0215, 0x2117, 0x4d17,
+    0xe0c2, 0x0216, 0x28a1, 0xf344, 0xa202, 0xe0c2, 0x0302, 0x28a0,
+    0xf062, 0x28a1, 0xae04, 0x08a1, 0x08a1, 0xf05e, 0x28a0, 0xae04,
+    0x08a0, 0x08a0, 0xe000, 0x03a0, 0xe09e, 0x2117, 0x4d17, 0xe0c2,
+    0x0380, 0x2117, 0x4d17, 0xe0c2, 0x0381, 0x2117, 0x4d17, 0xe0c2,
+    0x0382, 0x28a1, 0xae04, 0x08a1, 0x08a1, 0xe000, 0x03a0, 0xe09e,
+    0x2117, 0x4d17, 0xe0c2, 0x0383, 0x2117, 0x4d17, 0xe0c2, 0x0384,
+    0x2117, 0x4d17, 0xe0c2, 0x0385, 0xa200, 0xe0c2, 0x0302, 0xa204,
+    0x4c94, 0xae02, 0x4c26, 0xe0c2, 0x0303, 0xa202, 0xae02, 0xa902,
+    0xe0c2, 0x0312, 0xa220, 0xe0c2, 0x0313, 0xa200, 0xe0c2, 0x0308,
+    0xe0c2, 0x0168, 0xa200, 0x3c77, 0x3c78, 0x3c73, 0xa202, 0x3c7a,
+    0x28a4, 0xe412, 0x0fa9, 0x28a5, 0xe0c2, 0x0071, 0xf024, 0x3ca4,
+    0xa202, 0x3c6b, 0xa201, 0x28ac, 0xb6d1, 0xae0b, 0xe0c3, 0x0104,
+    0x286d, 0xa80c, 0xf058, 0x286d, 0x2a66, 0xb436, 0x3c6d, 0xa202,
+    0xe0c2, 0x0106, 0xa201, 0xe167, 0x0ba7, 0x3f17, 0xe41e, 0x1dfd,
+    0xe0c0, 0x0065, 0xaf0c, 0xa80e, 0xe40a, 0x0d6e, 0xca29, 0xf7f9,
+    0xe180, 0xe0c1, 0x006a, 0xce21, 0xd111, 0x0518, 0xd112, 0x000c,
+    0xd113, 0x0003, 0xca29, 0xf7f9, 0xe181, 0x30e4, 0xaf02, 0x30e5,
+    0xaf02, 0x30e6, 0x28e6, 0xe40a, 0x0d6e, 0xa210, 0x3c70, 0xe162,
+    0x0212, 0xe163, 0x0510, 0xa201, 0xd022, 0x0002, 0xe184, 0x0d53,
+    0x2912, 0xa81e, 0xe055, 0xae09, 0x2912, 0xa81e, 0xe055, 0x3f13,
+    0x2870, 0xa102, 0xf03a, 0x3c70, 0xf6fe, 0xe162, 0x051a, 0x2112,
+    0x4d12, 0xca29, 0xf7f9, 0xe180, 0xce20, 0xd111, 0x0510, 0xd112,
+    0x0008, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe181, 0xe162, 0x0518,
+    0xc410, 0xa200, 0x2ae6, 0xb632, 0xae10, 0x3d12, 0xa220, 0x3d12,
+    0x8132, 0xa200, 0x2ae5, 0xb652, 0xae10, 0x3d12, 0x2852, 0x3d12,
+    0x8132, 0x2ae4, 0x2825, 0xe01a, 0xe051, 0xa200, 0xb692, 0xae10,
+    0x4c25, 0x3d12, 0x2852, 0xb616, 0x3d12, 0x8132, 0xe42e, 0xe0c0,
+    0x0065, 0xaf0a, 0xa802, 0xf16a, 0xe162, 0x0530, 0x28d9, 0x3d12,
+    0x28da, 0x3d12, 0xe0c0, 0x006b, 0xca29, 0xf7f9, 0xe180, 0xce20,
+    0xd111, 0x0530, 0xd112, 0x0004, 0xd113, 0x0002, 0xca28, 0xf7f8,
+    0xe181, 0xe0c0, 0x0065, 0xaf0c, 0xa80e, 0xf10a, 0xe0c0, 0x006a,
+    0xca29, 0xf7f9, 0xe180, 0xce20, 0xd112, 0x000c, 0xd111, 0x0518,
+    0xd113, 0x0002, 0xca28, 0xf7f8, 0xe181, 0xa200, 0x3cda, 0x3cd9,
+    0x3ce3, 0x3cdb, 0x3cdc, 0xe0c0, 0x0111, 0xf7e8, 0xe0c0, 0x0065,
+    0xaf18, 0xa802, 0xf04a, 0xe0c0, 0x0281, 0xf7ea, 0x2877, 0x4c73,
+    0xe42a, 0xa204, 0xae0e, 0x4c50, 0xa102, 0xae0e, 0x4c51, 0xa102,
+    0xe0c1, 0x014b, 0xf7e9, 0xe0c2, 0x014d, 0xa202, 0xe0c2, 0x014a,
+    0xe0c1, 0x014b, 0xf7e9, 0xe42e, 0xe161, 0x0232, 0xa201, 0xf05a,
+    0xe161, 0x0272, 0xe005, 0x0040, 0xa202, 0xe0c2, 0x013c, 0xd022,
+    0x003f, 0xe184, 0x0df8, 0x2911, 0xe0c3, 0x013e, 0xe0c2, 0x013f,
+    0xa003, 0xa200, 0xe0c2, 0x013c, 0xe42e, 0xe0c0, 0x0064, 0x3cc9,
+    0x34c8, 0xe0c0, 0x0065, 0x3ccb, 0x34ca, 0xe0c0, 0x0066, 0x3ccd,
+    0x34cc, 0xe0c0, 0x0067, 0x3ccf, 0x34ce, 0xe0c0, 0x0069, 0xe167,
+    0x0ba0, 0x3d17, 0x3517, 0xe0c0, 0x006a, 0x3d17, 0x3517, 0xe0c0,
+    0x006b, 0x3d17, 0x3517, 0xe0c0, 0x0042, 0xe000, 0x1000, 0xce20,
+    0xd111, 0x0ba8, 0xd112, 0x004c, 0xd113, 0x0003, 0xca28, 0xf7f8,
+    0xe42e, 0xa201, 0x3ee8, 0x2ae5, 0xf07b, 0xae02, 0x4cd7, 0xae0c,
+    0x4c5d, 0xe41e, 0x103b, 0x280e, 0xae0a, 0x4c5d, 0xe0c2, 0x0115,
+    0xa27f, 0x2858, 0xf028, 0x2a5e, 0xe0c3, 0x012a, 0xa27e, 0xe0c2,
+    0x0116, 0x28ab, 0xae08, 0x4c58, 0xe0c2, 0x0114, 0x2835, 0x4c63,
+    0xf07a, 0x2859, 0x4435, 0xe016, 0xae0a, 0x4c5d, 0xcf6a, 0x2858,
+    0xe41a, 0x0e9b, 0x2ae4, 0x2825, 0xe01a, 0xe051, 0xf2eb, 0xe004,
+    0x0680, 0x08d4, 0xe094, 0x2858, 0xf268, 0x2ae8, 0xa803, 0xae1f,
+    0xe0c0, 0x03b0, 0xb616, 0x3512, 0x3d0a, 0x280b, 0xe418, 0x10af,
+    0x2902, 0xe008, 0x7fff, 0xe056, 0x3d12, 0x8112, 0x2825, 0xa102,
+    0xf12a, 0x2ae8, 0xa805, 0xae1d, 0xe0c0, 0x03c0, 0xb616, 0x3512,
+    0x3d0a, 0x280b, 0xe418, 0x10af, 0x2902, 0xe008, 0x7fff, 0xe056,
+    0x3d12, 0x8112, 0xe41e, 0x1079, 0x2823, 0xf078, 0x2858, 0xe016,
+    0x4c66, 0xf038, 0xe41e, 0x15c5, 0xe41e, 0x0eec, 0xe0c0, 0x0111,
+    0xf7e8, 0xa202, 0xe0c2, 0x0110, 0xe41e, 0x0fed, 0x2877, 0x4c73,
+    0xe418, 0x0f81, 0xe42e, 0x2a0b, 0xe0c3, 0x030d, 0xa200, 0x2a66,
+    0xf03b, 0x2a6c, 0xb676, 0x2a5b, 0xb672, 0x2a0b, 0xb632, 0x3c70,
+    0xae06, 0x4c70, 0x3c70, 0xae0c, 0x4c70, 0xe0c2, 0x0309, 0x2866,
+    0x2a6c, 0xa105, 0xe017, 0xe052, 0xe016, 0x3c64, 0xa200, 0x2a6c,
+    0xa107, 0xb62a, 0x4466, 0x3c65, 0xae02, 0x4c64, 0x3ce8, 0xae04,
+    0x4ce8, 0x3ce8, 0xae08, 0x4ce8, 0xe0c2, 0x030c, 0xa200, 0x2a0b,
+    0x4664, 0xf08b, 0x28b5, 0xae0a, 0x4cb5, 0xae0a, 0x4cb6, 0xae0a,
+    0x4cb6, 0xe0c2, 0x030a, 0xa202, 0xae20, 0xe00a, 0x0842, 0x2a0b,
+    0x4665, 0xf09b, 0x2ab7, 0xae0b, 0x4eb7, 0xae0b, 0x4eb8, 0xae0b,
+    0x4eb8, 0xe056, 0xe0c2, 0x030b, 0x2825, 0xa104, 0xe42a, 0x2823,
+    0xe428, 0xe41e, 0x15c5, 0xe42e, 0x286b, 0xe0c2, 0x0131, 0xa200,
+    0x3c6b, 0x285c, 0xe0c2, 0x0130, 0xe42e, 0x2069, 0x4c6a, 0xcf48,
+    0x2856, 0x4c58, 0x4c59, 0xf09a, 0xd1b3, 0x0008, 0xd1b3, 0x0010,
+    0x283f, 0xf058, 0xe40e, 0x0f2e, 0x283f, 0xf11a, 0x2859, 0x2ac6,
+    0xe016, 0xe017, 0xe052, 0xf0b8, 0xe162, 0x02f0, 0x2112, 0x4d0a,
+    0xcf4c, 0x2112, 0x4d0a, 0xcf54, 0xe40e, 0x0f2e, 0xe162, 0x0201,
+    0x2112, 0x4d12, 0xcf4c, 0x2112, 0x4d12, 0xcf4e, 0x2112, 0x4d12,
+    0xcf50, 0x2112, 0x4d12, 0xcf52, 0x2866, 0xf09a, 0x8112, 0xc418,
+    0x2112, 0x4d32, 0xcf54, 0x2112, 0x4d32, 0xcf58, 0x286c, 0xe016,
+    0x4466, 0x443e, 0xe40a, 0x0f5f, 0xca28, 0xf7f8, 0xa202, 0xcf62,
+    0xcf64, 0xe0c0, 0x0041, 0xe005, 0x01a8, 0xae11, 0xe042, 0xca29,
+    0xf7f9, 0xe180, 0xce20, 0xd111, 0x04d0, 0xd112, 0x0008, 0xd113,
+    0x0002, 0xca28, 0xf7f8, 0xe181, 0xe0c0, 0x0041, 0xe005, 0x01a8,
+    0xae11, 0xe042, 0xca29, 0xf7f9, 0xe180, 0xce20, 0xd111, 0x0048,
+    0xd112, 0x0002, 0xd113, 0x001b, 0xca28, 0xf7f8, 0xe181, 0xd1a0,
+    0x0001, 0xcb40, 0xf7f8, 0x286c, 0xe016, 0x4466, 0x443e, 0xe42a,
+    0x2853, 0xcf64, 0x2054, 0x4c55, 0xcf62, 0xe42e, 0xa200, 0x3c54,
+    0x3c55, 0xa202, 0x3c7a, 0xe41e, 0x0f81, 0xe41e, 0x1030, 0xf7c8,
+    0xa200, 0x3c7a, 0xe41e, 0x0f81, 0xe190, 0xe0c1, 0x014b, 0xf7e9,
+    0xe42e, 0x2854, 0x4c55, 0xe01a, 0x3c79, 0x2873, 0xf11a, 0x2854,
+    0xe41a, 0x1003, 0x2854, 0xaf02, 0xe000, 0x0360, 0xe09e, 0x2907,
+    0x2a54, 0xa803, 0xf029, 0xaf10, 0xe008, 0x001f, 0x3c7b, 0x287b,
+    0xae02, 0x4c79, 0xae02, 0x4c7a, 0xae0e, 0x4c54, 0xae0e, 0x4c55,
+    0xe0c1, 0x014b, 0xf7e9, 0xe0c2, 0x014d, 0xa202, 0xe0c2, 0x014a,
+    0xe42e, 0xe0c0, 0x0060, 0xe049, 0xa861, 0xe42b, 0xe049, 0xa81e,
+    0x3c78, 0xaf09, 0x3277, 0xaf03, 0x3273, 0x84a4, 0xc786, 0xe018,
+    0xe000, 0x03a0, 0xe09e, 0x2117, 0x4d17, 0xe0c2, 0x0143, 0x2117,
+    0x4d17, 0xe0c2, 0x0144, 0x2117, 0x4d17, 0xe0c2, 0x0145, 0xa200,
+    0xe0c2, 0x0140, 0xe0c2, 0x0149, 0x2862, 0xe0c2, 0x0141, 0xe0c0,
+    0x0064, 0xe0c2, 0x014c, 0x2850, 0xa102, 0xae20, 0x4c51, 0xa102,
+    0xe0c2, 0x0142, 0x2873, 0xae08, 0x4c78, 0xe0c2, 0x014e, 0xe0c0,
+    0x0061, 0xe0c2, 0x0146, 0xe0c0, 0x0062, 0xe0c2, 0x0147, 0xe0c0,
+    0x0063, 0xe0c2, 0x0148, 0xa203, 0xe42e, 0x2854, 0xaf02, 0xe000,
+    0x0320, 0xe09e, 0x2907, 0x2a54, 0xa803, 0x4c5d, 0xf039, 0x285d,
+    0xae10, 0x3d07, 0x2854, 0xa002, 0x1850, 0xe41a, 0x1000, 0xe42e,
+    0x2a75, 0xa204, 0xf03e, 0x2a74, 0xa206, 0x3c06, 0x3e07, 0xe0c0,
+    0x0041, 0x22f0, 0x4ef1, 0xe042, 0xe005, 0x029c, 0xae11, 0xe042,
+    0x2a07, 0xae09, 0x4e07, 0xae13, 0xe042, 0x2a55, 0xae0f, 0xe042,
+    0xca29, 0xf7f9, 0xe180, 0xce20, 0xd111, 0x0320, 0x2806, 0xa802,
+    0xf03a, 0xd111, 0x0360, 0x2850, 0xa002, 0xaf02, 0xa006, 0xa2f9,
+    0xe052, 0xce24, 0x8806, 0x0113, 0xca28, 0xf7f8, 0xe181, 0xe42e,
+    0x2854, 0xa002, 0x3c54, 0x1850, 0xe428, 0x3c54, 0x2855, 0xa002,
+    0x3c55, 0x1851, 0xe42e, 0x2a53, 0xa803, 0xf0f9, 0xae10, 0x3cd5,
+    0x2a52, 0xa103, 0x1a53, 0xe429, 0xe005, 0x0600, 0x0ad6, 0xe095,
+    0x3d02, 0xe41e, 0x1063, 0xe42e, 0x4cd5, 0xe005, 0x0600, 0x0ad6,
+    0xe095, 0x3d02, 0x28d6, 0xa002, 0x3cd6, 0xe002, 0x0080, 0xf068,
+    0xe41e, 0x1063, 0xa200, 0x3cd6, 0xe42e, 0x2852, 0xa102, 0x1853,
+    0xe41a, 0x1063, 0xe42e, 0x2a53, 0xaf11, 0xae11, 0xe162, 0x051e,
+    0x2112, 0x4d12, 0xe042, 0xca29, 0xf7f9, 0xe180, 0xce20, 0xd111,
+    0x0600, 0xd112, 0x0080, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe181,
+    0xe42e, 0x2858, 0xf08a, 0xa201, 0xa204, 0x5866, 0xa102, 0x3c70,
+    0x8670, 0x3f12, 0x28d4, 0x2a66, 0xa004, 0xb452, 0x3cd4, 0xe002,
+    0x0080, 0xf068, 0xe41e, 0x1095, 0xa200, 0x3cd4, 0xe42e, 0x2852,
+    0xa102, 0x1853, 0xe41a, 0x1095, 0xe42e, 0x2866, 0xe016, 0x3c70,
+    0x2a53, 0xaf0b, 0x5e70, 0xae11, 0xe162, 0x0522, 0x2112, 0x4d12,
+    0xe042, 0xca29, 0xf7f9, 0xe180, 0xce20, 0xd111, 0x0680, 0xd112,
+    0x0080, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe181, 0xe42e, 0x8112,
+    0xa204, 0x5894, 0xa102, 0x3ce9, 0x2902, 0x44e9, 0x3cea, 0x2902,
+    0xaf02, 0x5c94, 0x5894, 0xae04, 0x4cea, 0x3d0a, 0xe42e, 0xcb41,
+    0xf7f9, 0xd04c, 0x0001, 0xe41e, 0x10dd, 0xd04c, 0x0000, 0xe004,
+    0x0080, 0x2a16, 0xb616, 0xcc6e, 0xe017, 0x3e16, 0xe470, 0xa200,
+    0x3c16, 0xe41e, 0x10dd, 0xa202, 0x3c16, 0xe41e, 0x10dd, 0xa200,
+    0x3c16, 0xd037, 0x0080, 0xe128, 0xe42e, 0xca28, 0xf7f8, 0x2899,
+    0xf08a, 0xa802, 0xe428, 0xe41e, 0x1186, 0xa202, 0x3c99, 0xe42e,
+    0xe082, 0x3c14, 0xe004, 0x0048, 0xe092, 0xd027, 0x0000, 0xe41e,
+    0x112f, 0xd027, 0x0001, 0x2880, 0x4c81, 0xf378, 0xe004, 0x0000,
+    0x2a16, 0xf03b, 0xe000, 0x0080, 0xce22, 0x2010, 0x4c11, 0x2e13,
+    0xae11, 0xe042, 0xce20, 0xd112, 0x0080, 0xa226, 0xe0c0, 0x0043,
+    0xa806, 0xae02, 0xa022, 0xce26, 0x2c13, 0xe000, 0x0002, 0x3c13,
+    0x1c12, 0xf024, 0x3c13, 0x2882, 0xf078, 0x2010, 0x4c11, 0x2e13,
+    0xae11, 0xe042, 0x9f01, 0x2885, 0xe016, 0x449a, 0xf0ea, 0xa201,
+    0x2097, 0x4c98, 0xe002, 0x0200, 0x3497, 0x3c98, 0xb64d, 0x3e99,
+    0xf04b, 0xe000, 0x0200, 0x3c98, 0x2814, 0xe092, 0xe42e, 0xe0c1,
+    0x0043, 0xa809, 0xe429, 0x2885, 0xe428, 0x2885, 0xe016, 0x449a,
+    0xe428, 0xa200, 0x3c15, 0x2885, 0xf08a, 0xe0c0, 0x0059, 0xa102,
+    0xf048, 0x2886, 0xf02a, 0xf23e, 0x2010, 0x4c11, 0x2e13, 0xae11,
+    0xe042, 0x8111, 0x9e89, 0xe045, 0xf043, 0x2c12, 0xae10, 0xe041,
+    0xe003, 0x0200, 0xe423, 0xe0c0, 0x0045, 0xaf04, 0xa802, 0xf08a,
+    0xe001, 0x0200, 0x3697, 0x3e98, 0xa202, 0x3c9a, 0xe42e, 0x2885,
+    0xf06a, 0x2886, 0xf048, 0xa202, 0x3c86, 0xe42e, 0xe0c0, 0x0059,
+    0xa102, 0xf068, 0xe0c0, 0x0045, 0x3080, 0x2880, 0xe428, 0x2882,
+    0xe01a, 0x3c81, 0xe428, 0x2815, 0xf508, 0xe0c0, 0x005c, 0xe008,
+    0x4000, 0xf4ba, 0xe0c0, 0x005d, 0xe00a, 0x4000, 0xe0c2, 0x005d,
+    0xa202, 0xce00, 0x3c15, 0xe40e, 0x1144, 0xe42e, 0xe004, 0x0000,
+    0x2a16, 0xf039, 0xe000, 0x0200, 0x0898, 0xe049, 0xa807, 0x3e98,
+    0xaf04, 0xb432, 0x3c9b, 0xe008, 0x00ff, 0xcc78, 0xa201, 0xcc7b,
+    0xa002, 0xe008, 0x00ff, 0xcc78, 0xe004, 0x01b1, 0x2a30, 0xf03b,
+    0xe004, 0x0080, 0xcc7a, 0xe42e, 0x2885, 0xf1f8, 0x2899, 0xa802,
+    0xe42a, 0xc867, 0x1a9b, 0xa105, 0xe04a, 0xe000, 0x00fe, 0xf030,
+    0xe001, 0x0100, 0xa202, 0xb60a, 0xf0b9, 0xc869, 0xb636, 0xf08b,
+    0xa208, 0x1898, 0xaf07, 0xe046, 0xe049, 0xa200, 0xb62e, 0xb7f0,
+    0x2a6d, 0xb691, 0x3e6d, 0xe42e, 0xe41e, 0x1218, 0xe42e, 0xd030,
+    0x0000, 0xd034, 0x0000, 0xd033, 0x0000, 0xd035, 0x0000, 0xd036,
+    0x00ff, 0xd038, 0x0000, 0xe42e, 0x2010, 0x4c11, 0x2e13, 0xae11,
+    0xe042, 0xe005, 0x0048, 0xe093, 0x9f01, 0xe42e, 0xe0c0, 0x0048,
+    0xe002, 0x0400, 0xc867, 0xe009, 0x007f, 0xa107, 0xae05, 0xe042,
+    0xc869, 0xaf07, 0xe015, 0xa807, 0xe042, 0x2210, 0x4e11, 0xe045,
+    0xf047, 0x2e12, 0xae11, 0xe042, 0xe0c2, 0x0046, 0xe42e, 0xe161,
+    0x0800, 0xa200, 0x3d11, 0xe004, 0x01b1, 0x2a30, 0xf03b, 0xe004,
+    0x0080, 0x3d11, 0xe42e, 0xca29, 0xf7f9, 0xe0c0, 0x0049, 0xe049,
+    0xaf06, 0xae06, 0xa80f, 0xe01b, 0xae07, 0xe042, 0xce20, 0xd111,
+    0x0800, 0xd112, 0x0004, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e,
+    0xc872, 0xe049, 0xa80f, 0xe01b, 0xaf06, 0xe042, 0x2287, 0x4e88,
+    0xe045, 0xa200, 0xb7ee, 0xe42e, 0xe0c1, 0x0049, 0xe045, 0x3687,
+    0x3e88, 0xe42e, 0x283c, 0xf1ba, 0xf0c4, 0x283c, 0xaf10, 0xe008,
+    0x00ff, 0x1850, 0xf064, 0x283c, 0xe008, 0x00ff, 0x1851, 0xf182,
+    0x2050, 0x4c51, 0xae08, 0xe0c2, 0x006f, 0x2889, 0xae20, 0x4c8a,
+    0xe0c2, 0x004f, 0xa2fe, 0x3c3c, 0xa200, 0xe42e, 0x2850, 0xe008,
+    0x00ff, 0xae10, 0x2a51, 0xe009, 0x00ff, 0xe056, 0x3c3c, 0xa202,
+    0xe42e, 0xe41e, 0x122a, 0xe42a, 0xd1b3, 0x0001, 0xa223, 0x2825,
+    0xf0ca, 0x2a0c, 0xa021, 0xa102, 0xf08a, 0x283f, 0xf068, 0x280c,
+    0x2a0d, 0xe061, 0xa021, 0xa425, 0x3e60, 0x2825, 0xf068, 0xe161,
+    0x0200, 0xa200, 0xc711, 0x3d11, 0x2828, 0x3c42, 0xa200, 0x3c72,
+    0x3c43, 0x3c44, 0xcf64, 0xcf62, 0x2844, 0x4c72, 0xf14a, 0x2836,
+    0xf088, 0xe41e, 0x13f5, 0xf0da, 0xe41e, 0x05d9, 0x3c43, 0xf0be,
+    0xe41e, 0x1433, 0xf06a, 0xa200, 0xe41e, 0x0627, 0x3c43, 0xf03e,
+    0x2852, 0x3c43, 0x2844, 0x1843, 0xf680, 0xf07a, 0xe41e, 0x1382,
+    0x2843, 0x3c44, 0x1852, 0xf16a, 0xa202, 0x3c72, 0x2823, 0xf068,
+    0xe41e, 0x12ff, 0xd1b3, 0x0002, 0xf06e, 0xe41e, 0x1428, 0xd1b3,
+    0x0002, 0xe428, 0x286b, 0xa002, 0x3c6b, 0x2844, 0x1852, 0xe404,
+    0x1274, 0xa202, 0xe42e, 0xe41e, 0x122a, 0xe42a, 0xd1b3, 0x0001,
+    0x2828, 0x3c42, 0xa200, 0x3c43, 0x3c44, 0x3c33, 0xcf64, 0xcf62,
+    0xa2fe, 0x3c40, 0x2844, 0x1843, 0xf072, 0xe41e, 0x1382, 0x2843,
+    0x3c44, 0x1852, 0xf31a, 0xe41e, 0x12ff, 0x2843, 0x0832, 0x3c43,
+    0x2833, 0xa002, 0x3c33, 0x2844, 0x1852, 0xf26a, 0x282f, 0xf6b8,
+    0x2844, 0x1843, 0xf094, 0xba20, 0xa102, 0xf658, 0xd1b3, 0x0002,
+    0x286b, 0xa002, 0x3c6b, 0xe41e, 0x140a, 0x3c41, 0xf12a, 0xba60,
+    0xba48, 0x3c41, 0x2840, 0xba43, 0xf038, 0xe046, 0xf758, 0xba48,
+    0x3c28, 0x2841, 0x3c33, 0x8433, 0x8232, 0xe018, 0x3c43, 0xf4be,
+    0x2852, 0x3c43, 0xf48e, 0xa22c, 0xe41e, 0x13ad, 0xa17e, 0xf048,
+    0xe41e, 0x0a5f, 0xba6a, 0xe41e, 0x0a5f, 0xa202, 0xe42e, 0x2ad7,
+    0xe017, 0x3ed7, 0x2828, 0x3c61, 0x2832, 0x0843, 0x3c45, 0x2843,
+    0x3c53, 0xc70f, 0x7c50, 0x3454, 0x3c55, 0x2853, 0x1852, 0xe40a,
+    0x137d, 0xe41e, 0x1508, 0xe40a, 0x1380, 0x285d, 0x3c61, 0x2853,
+    0xa002, 0x3c53, 0xcf64, 0x2885, 0xf0ba, 0x2853, 0x1852, 0xf08a,
+    0xc872, 0x2687, 0x4e88, 0xae07, 0xe045, 0xe405, 0x1380, 0xe41e,
+    0x1458, 0xe01a, 0x3c7a, 0x2054, 0x4c55, 0xcf62, 0x2825, 0xa104,
+    0xf05a, 0x2836, 0xf348, 0x2830, 0xf398, 0x2825, 0xa104, 0xf1c8,
+    0xe41e, 0x13d0, 0xf0ca, 0x2854, 0xf06a, 0xe41e, 0x15eb, 0xa802,
+    0xe408, 0x130d, 0xba40, 0xe41e, 0x0a5f, 0xf38e, 0xe41e, 0x13b8,
+    0xe40a, 0x130d, 0xe41e, 0x15eb, 0xa802, 0xe408, 0x130d, 0xba40,
+    0xe41e, 0x0a5f, 0xf2be, 0xd190, 0x0008, 0xcb20, 0xf7f8, 0xe41e,
+    0x13d0, 0xf05a, 0xba40, 0xe41e, 0x0a5f, 0xf20e, 0xe41e, 0x13b8,
+    0xe40a, 0x130d, 0xba40, 0xe41e, 0x0a5f, 0xf18e, 0xe41e, 0x13e9,
+    0xe40a, 0x130d, 0xe41e, 0x0a5f, 0xf11e, 0x2853, 0x1845, 0xe408,
+    0x130d, 0x2861, 0x3c28, 0xba20, 0xa102, 0xf08a, 0xa222, 0xe41e,
+    0x13ad, 0xa102, 0xf038, 0xe41e, 0x0a5f, 0x2853, 0x3c44, 0xe42e,
+    0xe16a, 0xf7ce, 0x244a, 0x4c4b, 0xe016, 0x3c58, 0xe016, 0x3c59,
+    0x2842, 0x3c5d, 0xa200, 0x3c5b, 0x3c5f, 0x3c5c, 0x2844, 0x3c53,
+    0xc70f, 0x7c50, 0x3454, 0x3c55, 0x2853, 0x1843, 0xf122, 0xe41e,
+    0x0ef5, 0xa202, 0xe41e, 0x0e29, 0x2853, 0xa002, 0x3c53, 0xcf64,
+    0xe41e, 0x1458, 0xe01a, 0x3c7a, 0x2054, 0x4c55, 0xcf62, 0xf6de,
+    0x2843, 0x1844, 0x0846, 0x3c46, 0xe42e, 0x3c48, 0xc869, 0xa80f,
+    0xe042, 0x3c49, 0x7849, 0xa203, 0x5a48, 0xa103, 0xe052, 0xe42e,
+    0xc868, 0xa80e, 0xa102, 0xb6e8, 0xa002, 0x3c48, 0x7848, 0xa203,
+    0x5a48, 0xaf03, 0xa103, 0xe046, 0xe016, 0xe42a, 0xa22e, 0x0848,
+    0x3c48, 0x7848, 0xa203, 0xae2f, 0xa103, 0xe052, 0xe016, 0xe42e,
+    0xc868, 0xa80e, 0xa102, 0xb6e8, 0xa002, 0x3c48, 0x7848, 0xa203,
+    0x5a48, 0xaf03, 0xa103, 0xe046, 0xe016, 0xe42a, 0x2860, 0x0848,
+    0x3c48, 0x7848, 0xa203, 0x5a60, 0xa103, 0xe052, 0xa102, 0xe016,
+    0xe42e, 0xc869, 0xa80f, 0x3e48, 0x7848, 0xe016, 0xa023, 0x3e48,
+    0xe42a, 0x7848, 0xa102, 0xe016, 0xe42e, 0xe41e, 0x0a5f, 0x7860,
+    0xa102, 0xe016, 0xe428, 0xba2c, 0xe42a, 0xba4e, 0x2885, 0xf0aa,
+    0xc872, 0x2687, 0x4e88, 0xae07, 0xe045, 0xe403, 0x1409, 0xa200,
+    0xe42e, 0xf6ee, 0xba20, 0xa102, 0xf0ea, 0x2885, 0xf0aa, 0xc872,
+    0x2687, 0x4e88, 0xae07, 0xe045, 0xe403, 0x1418, 0xa200, 0xe42e,
+    0xba40, 0xf71e, 0xba2a, 0xa83e, 0x3c41, 0xe42a, 0xa13e, 0xe42a,
+    0x2841, 0x1833, 0xf6b4, 0x2841, 0x1832, 0xf682, 0x2841, 0xe42e,
+    0x2825, 0xa104, 0xf058, 0xe41e, 0x1382, 0xa202, 0xe42e, 0xe41e,
+    0x1bb3, 0xa200, 0xe42e, 0xe41e, 0x0a5f, 0xba20, 0xa102, 0xf0ea,
+    0xba4e, 0x2885, 0xf0aa, 0xc872, 0x2687, 0x4e88, 0xae07, 0xe045,
+    0xe403, 0x1444, 0xa200, 0xe42e, 0xf71e, 0xba2a, 0xa83e, 0xe42a,
+    0xa13e, 0xe42a, 0xa03e, 0xaf08, 0xf6ca, 0xe42e, 0xa200, 0x3c58,
+    0x3c5f, 0x2825, 0xe418, 0x0ef5, 0xa200, 0xe41e, 0x0e29, 0xe42e,
+    0xd188, 0x0001, 0x2854, 0xa002, 0x3c54, 0x1850, 0xe428, 0xd1b3,
+    0x0004, 0x3c54, 0x2855, 0xa002, 0x3c55, 0x1851, 0xe42e, 0xba42,
+    0xe000, 0x0128, 0xe09e, 0x2907, 0x0861, 0xa402, 0xa53e, 0x3c5d,
+    0xe42e, 0x2837, 0xf75a, 0xba40, 0xf0da, 0xba40, 0xae0a, 0x0861,
+    0xe000, 0x012c, 0xe09e, 0x2907, 0x0861, 0xa402, 0xa53e, 0x3c5d,
+    0xe42e, 0xba48, 0x3c5d, 0xe42e, 0xe161, 0x0200, 0x280b, 0xf03a,
+    0xa203, 0xf03e, 0x2a5b, 0xb673, 0x3f11, 0xcc45, 0xe184, 0x149c,
+    0xe41e, 0x149e, 0xe42d, 0x3d11, 0xe41e, 0x149e, 0xe42d, 0x3d11,
+    0x280b, 0xf03a, 0x8111, 0x8111, 0xe190, 0xe42e, 0xb80c, 0xa140,
+    0xe42d, 0xe42a, 0x582a, 0x762a, 0x1a2b, 0xf030, 0xe046, 0xe046,
+    0xe042, 0xe42e, 0x286c, 0xa802, 0xe40a, 0x14c8, 0x280c, 0x3c29,
+    0x281d, 0x3c2a, 0x281e, 0x3c2b, 0xe161, 0x0200, 0x2a0b, 0x3f11,
+    0xcc45, 0xe184, 0x14c7, 0xe41e, 0x149e, 0xe42d, 0x3d11, 0xe41e,
+    0x149e, 0xe42d, 0x3d11, 0x280b, 0xf03a, 0x8111, 0x8111, 0xe190,
+    0x286c, 0xf20a, 0xa106, 0xf1ea, 0x280d, 0x3c29, 0x281f, 0x3c2a,
+    0x2820, 0x3c2b, 0xe161, 0x0200, 0x2a0b, 0x3f01, 0xe161, 0x0209,
+    0x3f11, 0xcc45, 0xe184, 0x14e8, 0xe41e, 0x149e, 0xe42d, 0x3d11,
+    0xe41e, 0x149e, 0xe42d, 0x3d11, 0x280b, 0xf03a, 0x8111, 0x8111,
+    0xe190, 0xe42e, 0x28b0, 0x18af, 0xf02a, 0x3c69, 0x284e, 0x18af,
+    0x3c6a, 0xe42e, 0xe161, 0x0200, 0xe162, 0x0209, 0xa206, 0x3d11,
+    0x3d12, 0xe41e, 0x1505, 0x3d11, 0x3d12, 0xe42d, 0xe41e, 0x1505,
+    0x3d11, 0x3d12, 0xe41e, 0x14ea, 0xe42e, 0xb80c, 0xa140, 0xe42e,
+    0x2861, 0xcf34, 0x2830, 0xe408, 0x1580, 0x2866, 0xf0da, 0xe41e,
+    0x15eb, 0xcf36, 0xa802, 0x2ac2, 0xe017, 0xe052, 0xf05a, 0xe004,
+    0x1000, 0xcf02, 0xf08e, 0xd190, 0x0002, 0xcb20, 0xf7f8, 0xcb22,
+    0xe408, 0x157b, 0xcb02, 0x30b8, 0xaf02, 0x30b7, 0xaf02, 0x30b6,
+    0xaf02, 0x30b5, 0xaf02, 0x30c6, 0xaf02, 0x300b, 0xaf02, 0x30ab,
+    0xaf02, 0x305c, 0xaf06, 0x305b, 0xaf02, 0x3058, 0xaf02, 0x3059,
+    0xaf02, 0x3056, 0xaf02, 0xe049, 0xa807, 0x3e6c, 0xaf04, 0xe049,
+    0xa83f, 0x3e5d, 0xaf0a, 0x3c5e, 0x2859, 0xf308, 0x2856, 0x2a56,
+    0xe418, 0x14ea, 0xf1d9, 0x2866, 0xf0aa, 0x286c, 0xe41a, 0x14f2,
+    0x286c, 0xe418, 0x14aa, 0xe40d, 0x157b, 0xf07e, 0x2858, 0x4cc6,
+    0xe41a, 0x1484, 0xe40d, 0x157b, 0x2858, 0x2a61, 0x1a27, 0xb606,
+    0x2a66, 0xb612, 0x3c5f, 0xcf26, 0xd190, 0x0001, 0x2a25, 0xe419,
+    0x0ef5, 0xcb20, 0xf7f8, 0xa202, 0x3cbb, 0xcb22, 0xe408, 0x157b,
+    0xa200, 0xe41e, 0x0e29, 0xa202, 0xe42e, 0xa208, 0x3c6c, 0xe41e,
+    0x144e, 0xa202, 0xe42e, 0xd191, 0x0000, 0xe16a, 0xa200, 0xe42e,
+    0xd190, 0x0002, 0xcb20, 0xf7f8, 0xcb22, 0xe408, 0x15c0, 0xcb02,
+    0xaf0e, 0xe049, 0xa807, 0x3e5c, 0xaf06, 0x305b, 0xaf02, 0x3058,
+    0xaf02, 0x3059, 0xaf08, 0xe049, 0xa83e, 0x3c5d, 0xaf0b, 0x3e5e,
+    0x2859, 0xf238, 0x2858, 0xf078, 0x2839, 0x443a, 0xf02a, 0xf03e,
+    0xe41e, 0x1484, 0xe40d, 0x15c0, 0x2834, 0xe016, 0x4458, 0x3c5f,
+    0x2858, 0x4434, 0xae02, 0x4c5f, 0xcf26, 0xd190, 0x0001, 0x2825,
+    0xe418, 0x0ef5, 0xcb21, 0xf7f9, 0xcb22, 0xe408, 0x15c0, 0xa200,
+    0xe41e, 0x0e29, 0xa202, 0xe42e, 0xe41e, 0x144e, 0xa202, 0xe42e,
+    0xd191, 0x0000, 0xe16a, 0xa200, 0xe42e, 0x2854, 0xaf04, 0xe000,
+    0x0300, 0xe09e, 0x2a54, 0xa807, 0xa107, 0xe013, 0xae05, 0x3e70,
+    0xa21f, 0x5a70, 0xa2fe, 0xe059, 0x2907, 0xe052, 0x2a59, 0xf05b,
+    0x5a70, 0xe056, 0x3d07, 0xf0ae, 0x2ab5, 0xae03, 0x4eb6, 0xae03,
+    0x4e0b, 0xae03, 0x5a70, 0xe056, 0x3d07, 0x2854, 0xa002, 0x1850,
+    0xe41a, 0x15fd, 0xe42e, 0x2854, 0xe41a, 0x15ff, 0x2854, 0xaf04,
+    0xe000, 0x0300, 0xe092, 0x2a54, 0xa807, 0xa107, 0xe013, 0xae05,
+    0x3e70, 0x2901, 0x5c70, 0xa81e, 0xe42e, 0xa204, 0xf02e, 0xa206,
+    0x3c06, 0xe0c0, 0x0041, 0x22f0, 0x4ef1, 0xe042, 0xe005, 0x02e0,
+    0xae11, 0xe042, 0x2a55, 0xae0d, 0xe042, 0xca29, 0xf7f9, 0xe180,
+    0xce20, 0xd111, 0x0300, 0xd112, 0x0020, 0x8806, 0x0113, 0xca28,
+    0xf7f8, 0xe181, 0xe42e, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0080, 0x0060, 0x0008, 0x0006,
+    0x00b0, 0x0090, 0x000b, 0x0009, 0x0160, 0x0120, 0x0016, 0x0012,
+    0x02c0, 0x0240, 0x0058, 0x0012, 0x0580, 0x0480, 0x0160, 0x0012,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0063, 0x000d, 0x000f, 0x0011, 0x0013, 0x0015, 0x0017, 0x0000,
+    0xffff, 0xfffe, 0x0001, 0x0002, 0x0000, 0x0002, 0xffff, 0xffff,
+    0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xfffe,
+    0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe,
+    0xfffe, 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0xfffd,
+    0xfffd, 0xfffd, 0xfffd, 0xfffd, 0x0000, 0x0001, 0x0001, 0x0001,
+    0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0002,
+    0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002,
+    0x0002, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+    0x0003, 0x0002, 0x0001, 0xfffb, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x22f0, 0x4ef1, 0xd130, 0x0003, 0xa200, 0xc401, 0xe188, 0x07ff,
+    0x3d11, 0x36f0, 0x3ef1, 0xe41e, 0x1899, 0xe41e, 0x18fc, 0xe162,
+    0x0528, 0xe004, 0x0044, 0x3d12, 0xe004, 0x0069, 0x3d12, 0xe004,
+    0x0076, 0x3d12, 0xe004, 0x0058, 0x3d12, 0xa202, 0xe0c2, 0x0078,
+    0xe0c0, 0x0067, 0xa211, 0xe045, 0xf07b, 0x30d0, 0xaf02, 0x30d1,
+    0xaf02, 0x30d2, 0xf06e, 0xa200, 0x3cd1, 0xa202, 0x3cd2, 0x3cd0,
+    0xe0c0, 0x0062, 0x3063, 0xaf02, 0x307f, 0xaf02, 0x3085, 0xaf02,
+    0x3093, 0xe41e, 0x1940, 0xe41e, 0x1901, 0xe40a, 0x1894, 0xe41e,
+    0x11de, 0x2830, 0xf08a, 0xe41e, 0x11c7, 0xe128, 0xe0c0, 0x0060,
+    0xe0c2, 0x0046, 0x280f, 0x3c90, 0x2089, 0x4c8a, 0xe0c2, 0x0071,
+    0xe0c2, 0x004f, 0x2c22, 0xa102, 0xae20, 0x4c21, 0xe0c2, 0x0072,
+    0x28c3, 0xa80e, 0xae02, 0x4c35, 0xae02, 0x4c30, 0xae02, 0x4c24,
+    0xae02, 0x4c23, 0xe0c2, 0x0075, 0x28ad, 0xe016, 0x2ae0, 0xae02,
+    0xe01b, 0xe056, 0xae0e, 0xf09b, 0x2ae0, 0xa81f, 0xe056, 0xae10,
+    0x2ae0, 0xaf09, 0xe056, 0xf03e, 0xae10, 0x4ce1, 0xe0c2, 0x007b,
+    0x28e2, 0xae08, 0x4c7e, 0xe0c2, 0x006c, 0x2863, 0x2a35, 0xb612,
+    0x3c63, 0xa208, 0x0863, 0xe0c2, 0x0073, 0xa200, 0x3c80, 0x2a90,
+    0xf029, 0xa202, 0x3c9c, 0xe0c2, 0x0074, 0x2823, 0xe016, 0x3c09,
+    0xa202, 0xe0c2, 0x0070, 0xe42e, 0xa200, 0x3c80, 0xe0c2, 0x0070,
+    0xe42e, 0xe0c0, 0x0040, 0xa23d, 0xae17, 0xe042, 0xe005, 0x1700,
+    0xae03, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0100, 0xd112,
+    0x0100, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e, 0xe42e, 0xd130,
+    0x0003, 0xe41e, 0x0dfd, 0xe0c0, 0x0060, 0xe42a, 0xca28, 0xf7f8,
+    0xe0c0, 0x0042, 0xce20, 0xd111, 0x03a0, 0xd112, 0x00c4, 0xd113,
+    0x0003, 0xca28, 0xf7f8, 0xe0c0, 0x0060, 0x3c4d, 0xe0c0, 0x0061,
+    0x3c62, 0xe41e, 0x04c3, 0xe42e, 0xe0c0, 0x0060, 0xf08a, 0xe0c0,
+    0x0061, 0x2210, 0x4e11, 0xe046, 0xaf12, 0xae02, 0x3c13, 0xa200,
+    0x3c9a, 0xe180, 0xe41e, 0x11c7, 0xe41e, 0x11d4, 0xe41e, 0x04c3,
+    0xe166, 0x0054, 0x9e06, 0xf16a, 0x284d, 0xa102, 0xcc44, 0xa200,
+    0x3c06, 0xe184, 0x18f7, 0x9e06, 0x5c06, 0xa802, 0xf07a, 0x2806,
+    0xe000, 0x0212, 0xe09e, 0xa208, 0x3d07, 0x2806, 0xa002, 0x3c06,
+    0xe190, 0xa202, 0x3c8b, 0xe42e, 0xa200, 0xcc72, 0xe0c2, 0x006c,
+    0xe42e, 0xd198, 0x0004, 0xd190, 0x0004, 0x2880, 0xa908, 0xcf30,
+    0xcb20, 0xf7c8, 0xe41e, 0x11a4, 0xf328, 0x2880, 0xf308, 0xcb30,
+    0xaf08, 0xa102, 0xf1ea, 0xa102, 0xf23a, 0xba3e, 0xe002, 0x01b0,
+    0xf058, 0xba7e, 0xe41e, 0x0644, 0xf67e, 0xba7e, 0xe002, 0x012f,
+    0xf630, 0xe000, 0x000f, 0xf604, 0xe41e, 0x066c, 0xf5da, 0xa200,
+    0x3c30, 0x3c34, 0x3c35, 0x3c36, 0x3c37, 0x3c2f, 0xa202, 0xe42e,
+    0xba6a, 0xe41e, 0x0805, 0xf50a, 0xa202, 0x3c30, 0xe42e, 0xba60,
+    0xe41e, 0x0a8c, 0xf49a, 0xa202, 0x3c30, 0xe42e, 0xa200, 0xe42e,
+    0xa200, 0x3c13, 0x3c16, 0xe41e, 0x11f7, 0xe0c0, 0x0062, 0xaf0c,
+    0xa802, 0xf10a, 0xe0c1, 0x0048, 0xe0c0, 0x0060, 0xe045, 0xaf13,
+    0xae03, 0xa109, 0x3e13, 0xf063, 0xe0c0, 0x0061, 0xae04, 0xe042,
+    0x3c13, 0xe0c0, 0x0060, 0x3410, 0x3c11, 0xe0c0, 0x0061, 0xae04,
+    0x3c12, 0xe41e, 0x11c7, 0xe41e, 0x11d4, 0xd071, 0x802a, 0xe181,
+    0x2885, 0xf0aa, 0xe0c1, 0x0060, 0xe0c0, 0x0064, 0xe042, 0xe41e,
+    0x1224, 0xe41e, 0x1203, 0xe41e, 0x10dd, 0xa202, 0x3c16, 0xe41e,
+    0x10dd, 0xa200, 0x3c16, 0xd037, 0x0080, 0xe128, 0xe42e, 0x288b,
+    0xe418, 0x10cf, 0xa200, 0xcc4a, 0xcc4c, 0x3c8b, 0x3ce7, 0x3cd9,
+    0x3c3f, 0x3c9e, 0x3c9f, 0xe0c2, 0x0074, 0xa2fc, 0xe0c2, 0x0077,
+    0xa2fa, 0xe0c2, 0x0071, 0xa202, 0xe0c2, 0x0076, 0xe0c0, 0x006c,
+    0xe002, 0x0088, 0x3cdd, 0xe0c0, 0x0065, 0xaf0a, 0x30e3, 0xe0c0,
+    0x0045, 0xaf04, 0xa802, 0xf22a, 0x289c, 0xa102, 0x3c9c, 0xf194,
+    0x28a4, 0xf0a4, 0xe000, 0x02b2, 0xe09e, 0x2907, 0x3c74, 0xe41e,
+    0x0fa9, 0xe419, 0x0f6e, 0x28a3, 0x3ca5, 0xe0c2, 0x0071, 0x3ca4,
+    0x287f, 0xe408, 0x1b53, 0xa2fe, 0xe0c2, 0x0071, 0xe40e, 0x1b53,
+    0xa2fe, 0xe0c2, 0x0071, 0xe40e, 0x1b53, 0xe41e, 0x1b81, 0xa204,
+    0xe0c2, 0x0075, 0xa2fe, 0xe0c2, 0x0077, 0xe41e, 0x0547, 0xe41e,
+    0x0538, 0xe42a, 0xa2fc, 0xe0c2, 0x0077, 0xd130, 0x0003, 0xd03a,
+    0x0003, 0xd04b, 0x0001, 0xd04c, 0x0000, 0xd008, 0x0000, 0xa200,
+    0xe0c2, 0x030a, 0x3c46, 0x2830, 0xe418, 0x05b2, 0xe404, 0x19f7,
+    0xe40d, 0x1b6d, 0x2830, 0xe41a, 0x055e, 0xe404, 0x19f7, 0xe40d,
+    0x1b6d, 0xe0c0, 0x0065, 0xa808, 0xf0fa, 0x2825, 0xf0da, 0xa2fa,
+    0xe0c2, 0x0071, 0x3ca5, 0x3ca4, 0x28ae, 0xae2a, 0x4c25, 0xe0c2,
+    0x0073, 0xe40e, 0x1b45, 0xe0c0, 0x0065, 0xaf06, 0xa806, 0x3c8e,
+    0xf17a, 0xa102, 0xf048, 0x2825, 0xf13a, 0xf06e, 0xa102, 0xf048,
+    0x2825, 0xa104, 0xf0d8, 0xa2fa, 0xe0c2, 0x0071, 0x3ca5, 0x3ca4,
+    0x28ae, 0xae2a, 0x4c25, 0xe0c2, 0x0073, 0xe40e, 0x1b45, 0x2890,
+    0xe016, 0x4c2e, 0xf218, 0x287d, 0xf1fa, 0x28a4, 0xf064, 0xe000,
+    0x02b2, 0xe09e, 0x2907, 0x3c74, 0xe41e, 0x0fa9, 0xe419, 0x0f6e,
+    0xa200, 0x3c7d, 0x28a3, 0x3ca5, 0xe0c2, 0x0071, 0x3ca4, 0xa206,
+    0x3c92, 0x3c9c, 0xa202, 0x3c76, 0x246e, 0x4c6f, 0xa002, 0x346e,
+    0x3c6f, 0xe40e, 0x1b39, 0x2825, 0xa802, 0x447d, 0xf06a, 0x28a3,
+    0xe41e, 0x04fb, 0xa200, 0x3c7d, 0x2890, 0xf14a, 0x2825, 0xf128,
+    0x287d, 0xf10a, 0x287f, 0xf0ea, 0x28a3, 0xe000, 0x0212, 0xe092,
+    0x2901, 0xe049, 0xa809, 0xf06b, 0xa806, 0x3d01, 0xa200, 0x3c92,
+    0x3c7d, 0xe41e, 0x0b4f, 0x286d, 0xa80c, 0xe016, 0x4466, 0xe408,
+    0x1b6d, 0x282e, 0x2a3f, 0xe017, 0x3e70, 0x2ac3, 0xa103, 0xe017,
+    0x4e70, 0xe052, 0xf218, 0xe162, 0x0200, 0xa200, 0xc711, 0x3d12,
+    0x3c44, 0x3c3e, 0x3c0d, 0x3c0c, 0x3cb5, 0x3cb6, 0x3c6c, 0x3c0b,
+    0x282e, 0xf068, 0x2825, 0xa104, 0xf038, 0xa200, 0x3c66, 0x2852,
+    0x3c43, 0xa202, 0x3c42, 0xe004, 0x1000, 0xcf02, 0xe41e, 0x1382,
+    0xa200, 0x3c46, 0xf0fe, 0x2836, 0xe016, 0x4430, 0xf078, 0xe41e,
+    0x1251, 0xe40a, 0x1b6d, 0xe40e, 0x1aa1, 0xe41e, 0x12ab, 0xe40a,
+    0x1b6d, 0xe41e, 0x0d8f, 0x244a, 0x4c4b, 0xa002, 0x344a, 0x3c4b,
+    0xa102, 0xe0c1, 0x0062, 0xa811, 0xa201, 0xe055, 0x2890, 0xf3ca,
+    0x2825, 0xf06a, 0xa102, 0xf0ea, 0xa102, 0xf36a, 0xf0be, 0x28a2,
+    0x2a63, 0xf02b, 0x28a6, 0x3ca5, 0xe0c2, 0x0071, 0x3ca4, 0xe40e,
+    0x1b39, 0xa202, 0x3c92, 0xc872, 0x2687, 0x4e88, 0xae07, 0xe045,
+    0xaf07, 0xa10b, 0xe403, 0x1ad6, 0x28a2, 0x2a63, 0xf02b, 0x28a6,
+    0x3ca5, 0xe0c2, 0x0071, 0x3ca4, 0xe40e, 0x1b39, 0xa2fa, 0xe0c2,
+    0x0071, 0x3ca5, 0x3ca4, 0xa202, 0x3c9d, 0x3c7d, 0x3c9c, 0x246e,
+    0x4c6f, 0xa102, 0x346e, 0x3c6f, 0xa202, 0xae20, 0xa902, 0xe0c2,
+    0x0076, 0xe40e, 0x1b39, 0x244a, 0x4c4b, 0xa102, 0xf088, 0xa2fa,
+    0xe0c2, 0x0071, 0x3ca5, 0x3ca4, 0xe40e, 0x1b39, 0x2890, 0xf3ba,
+    0x2825, 0xf09a, 0xa102, 0xf10a, 0xa102, 0xf02a, 0xf0de, 0xa204,
+    0x3c92, 0xf31e, 0x28a2, 0x2a63, 0xf02b, 0x28a6, 0xe0c2, 0x0071,
+    0x3ca5, 0x3ca4, 0xf2fe, 0xe41e, 0x0a5f, 0xba3e, 0xe002, 0x01b6,
+    0xf10a, 0x2892, 0xa102, 0xf048, 0xa208, 0x3c92, 0xf23e, 0x28a2,
+    0x2a63, 0xf02b, 0x28a6, 0xe0c2, 0x0071, 0x3ca5, 0x3ca4, 0xf1ae,
+    0x2892, 0xa102, 0xf028, 0xf16e, 0xa2fe, 0x3ca5, 0x3ca4, 0xa202,
+    0x3c92, 0x244a, 0x4c4b, 0xa102, 0x344a, 0x3c4b, 0xa2fa, 0xe0c2,
+    0x0071, 0xf08e, 0xf079, 0xa2fe, 0x3ca5, 0x3ca4, 0xa2fa, 0xe0c2,
+    0x0071, 0x244a, 0x4c4b, 0xe0c2, 0x0070, 0x28ae, 0xae2a, 0x4c25,
+    0xe0c2, 0x0073, 0x2846, 0xe0c2, 0x0072, 0x287f, 0xf0d8, 0xe0c0,
+    0x0077, 0x2a63, 0xf06b, 0x2a2e, 0xe017, 0x4690, 0x28a6, 0xb7d2,
+    0xe0c2, 0x0071, 0x3ca4, 0x2889, 0xae20, 0x4c8a, 0xe0c2, 0x006f,
+    0xe0c2, 0x004f, 0xc84a, 0xc84d, 0xae20, 0xe056, 0xe0c2, 0x0053,
+    0xe41e, 0x0521, 0x28ae, 0xae2a, 0x4c25, 0xe0c2, 0x0073, 0xe41e,
+    0x01d3, 0xe41e, 0x11de, 0xa202, 0xe42e, 0x2889, 0xae20, 0x4c8a,
+    0xe0c2, 0x006f, 0xe0c2, 0x004f, 0x2825, 0xe0c2, 0x0073, 0xa2fc,
+    0xe0c2, 0x0077, 0xe41e, 0x0521, 0xe16a, 0xa200, 0xe0c2, 0x0076,
+    0xe42e, 0x289d, 0xf04a, 0xa200, 0x3c9d, 0xe42e, 0xa200, 0x3c86,
+    0x3c16, 0x3c13, 0x2210, 0x4e11, 0x2893, 0xf05a, 0xe0c1, 0x0068,
+    0x3610, 0x3e11, 0xe0c0, 0x0069, 0xe042, 0xe41e, 0x1224, 0x2010,
+    0x4c11, 0xe042, 0xe005, 0x0049, 0xe093, 0x9f01, 0xe004, 0xffff,
+    0x3c12, 0xe41e, 0x11c7, 0xe41e, 0x11d4, 0xe41e, 0x1203, 0xe41e,
+    0x10dd, 0xa202, 0x3c16, 0xe41e, 0x10dd, 0xa200, 0x3c16, 0xd037,
+    0x0080, 0xe128, 0xe42e, 0x2ad7, 0xe017, 0x3ed7, 0x2828, 0x3c61,
+    0x2832, 0x0843, 0x3c45, 0xe160, 0x0006, 0x2825, 0xf0a8, 0xe41e,
+    0x1c08, 0xe40a, 0x1c06, 0xe41e, 0x1c66, 0xe40a, 0x1c06, 0xf09e,
+    0xe41e, 0x1c9d, 0xe40a, 0x1c06, 0xe41e, 0x1cfd, 0xe40a, 0x1c06,
+    0xa200, 0x3c4f, 0x2843, 0x3c53, 0xc70f, 0x7c50, 0x3454, 0x3c55,
+    0x2828, 0x3c61, 0x3c5d, 0x2853, 0x1852, 0xe40a, 0x1c03, 0xe41e,
+    0x1d7f, 0xe40a, 0x1c06, 0x285d, 0x3c61, 0x2853, 0xa002, 0x3c53,
+    0xcf64, 0x2885, 0xf0ba, 0x2853, 0x1852, 0xf08a, 0xc872, 0x2687,
+    0x4e88, 0xae07, 0xe045, 0xe405, 0x1c06, 0xe41e, 0x1458, 0xe01a,
+    0x3c7a, 0x2054, 0x4c55, 0xcf62, 0x2853, 0x1845, 0xe408, 0x1bdb,
+    0xba40, 0xe41e, 0x0a5f, 0x2853, 0x3c44, 0xe42e, 0xe16a, 0xf7ce,
+    0xd1b3, 0x0020, 0xa200, 0x3c67, 0xe161, 0x0700, 0xe004, 0x0700,
+    0x3c68, 0x2843, 0x3c53, 0x2853, 0x1852, 0xe402, 0x1c5b, 0x2861,
+    0xcf34, 0xd198, 0x0000, 0xa203, 0x2861, 0x1827, 0xb605, 0x3e5f,
+    0xa909, 0xcf27, 0xd190, 0x0002, 0xcb20, 0xf7f8, 0xcb22, 0xe408,
+    0x1c60, 0xcb02, 0xaf20, 0xe049, 0xa8fe, 0xae02, 0x4c5f, 0xae06,
+    0xa908, 0x3d11, 0xa83f, 0x3e5d, 0x2a5f, 0xf0bb, 0xcb2a, 0x3511,
+    0x3d11, 0xcb2c, 0x3511, 0x3d11, 0xcb2e, 0x3511, 0x3d11, 0xf02e,
+    0x8131, 0xe082, 0xe002, 0x07f0, 0xf084, 0xe41e, 0x1de5, 0x2867,
+    0xa002, 0x3c67, 0xe161, 0x0700, 0x285f, 0xf058, 0xd190, 0x0008,
+    0xcb20, 0xf7f8, 0x285d, 0x3c61, 0x2853, 0xa002, 0x3c53, 0xcb30,
+    0xa808, 0xe40a, 0x1c13, 0xba64, 0x2a53, 0x3e45, 0xa202, 0xe42e,
+    0xd191, 0x0000, 0x2843, 0x3c53, 0xa200, 0xe42e, 0x1a43, 0xa103,
+    0xcc45, 0x2867, 0xf07a, 0xe41e, 0x1de5, 0xa200, 0x3c67, 0xe41e,
+    0x1de7, 0xe161, 0x0700, 0xe184, 0x1c8c, 0xba40, 0xb809, 0xf22d,
+    0xae08, 0xe056, 0xae16, 0x2b01, 0xe056, 0x3d11, 0x8131, 0xe082,
+    0xe002, 0x07f0, 0xf0a4, 0xe41e, 0x1de5, 0x2867, 0xa002, 0x3c67,
+    0xe41e, 0x1de7, 0xe161, 0x0700, 0xe190, 0x2867, 0xf09a, 0xe41e,
+    0x1de5, 0xa200, 0x3c67, 0xe41e, 0x1de7, 0xa202, 0x3c67, 0xa202,
+    0xe42e, 0x2843, 0x3c53, 0xa200, 0xe42e, 0xd1b3, 0x0020, 0xa200,
+    0x3c67, 0xe161, 0x0700, 0x2843, 0xe005, 0x0700, 0x3c53, 0x3e68,
+    0x2853, 0x1852, 0xe402, 0x1cf4, 0xba40, 0xe40a, 0x1cb1, 0x3d11,
+    0xf2ce, 0xb802, 0xa10e, 0xe40d, 0x1cf9, 0xf77a, 0xa00e, 0x3058,
+    0xaf02, 0x305a, 0xaf02, 0x305b, 0xaf02, 0x3c01, 0x285a, 0xae04,
+    0x4c01, 0xae0e, 0x4c58, 0xae02, 0x4c5b, 0xae02, 0x3d11, 0x2858,
+    0xf118, 0x285b, 0xb670, 0xcc44, 0xe184, 0x1cd7, 0xe41e, 0x149e,
+    0xe40d, 0x1cf9, 0x3d11, 0xe41e, 0x149e, 0xe40d, 0x1cf9, 0x3d11,
+    0xf04e, 0x2858, 0xf02a, 0x8131, 0xe082, 0xe002, 0x07f0, 0xf084,
+    0xe41e, 0x1de5, 0x2867, 0xa002, 0x3c67, 0xe161, 0x0700, 0x2853,
+    0xa002, 0x3c53, 0xd198, 0x0002, 0xd190, 0x0008, 0xcb20, 0xf7f8,
+    0xcb30, 0xa808, 0xe40a, 0x1ca8, 0xba60, 0x2a53, 0x3e45, 0xa202,
+    0xe42e, 0x2843, 0x3c53, 0xa200, 0xe42e, 0x1a43, 0xa103, 0xcc45,
+    0x2867, 0xf07a, 0xe41e, 0x1de5, 0xa200, 0x3c67, 0xe41e, 0x1de7,
+    0xe161, 0x0700, 0xe184, 0x1d6c, 0x2901, 0x3c70, 0xe049, 0xa803,
+    0xe40b, 0x1d17, 0x2861, 0x3c5d, 0x3f11, 0xe40e, 0x1d5e, 0xaf02,
+    0x305b, 0xaf02, 0x3058, 0xaf12, 0x305a, 0x2858, 0xae04, 0x4c5a,
+    0xae12, 0xcf02, 0x2861, 0xcf34, 0x2858, 0x2a61, 0x1a27, 0xb606,
+    0x3c5f, 0xa908, 0xcf26, 0xd190, 0x0002, 0x2870, 0xe008, 0x07ff,
+    0x3c70, 0xcb20, 0xf7f8, 0xcb22, 0xe408, 0x1d79, 0xcb02, 0xaf0e,
+    0x305c, 0xaf12, 0xa23f, 0xe051, 0x3e5d, 0xaf0e, 0x3c5e, 0x285c,
+    0xae08, 0x4c5e, 0xae0e, 0x4c5d, 0xae02, 0x4c5f, 0xae06, 0x4c70,
+    0x3d11, 0x2858, 0xf0fa, 0x285f, 0xf0ba, 0xcb2a, 0x3511, 0x3d11,
+    0xcb2c, 0x3511, 0x3d11, 0xcb2e, 0x3511, 0x3d11, 0xf08e, 0x8131,
+    0xf06e, 0x8111, 0x8111, 0x285b, 0xf02a, 0x8131, 0xe082, 0xe002,
+    0x07f0, 0xf0a4, 0xe41e, 0x1de5, 0x2867, 0xa002, 0x3c67, 0xe41e,
+    0x1de7, 0xe161, 0x0700, 0x285d, 0x3c61, 0x2867, 0xf09a, 0xe41e,
+    0x1de5, 0xa200, 0x3c67, 0xe41e, 0x1de7, 0xa202, 0x3c67, 0xa202,
+    0xe42e, 0xd191, 0x0000, 0x2843, 0x3c53, 0xa200, 0xe42e, 0x2861,
+    0xcf34, 0x2868, 0xe092, 0x2911, 0x3059, 0x2a59, 0xe409, 0x1dd8,
+    0xaf02, 0x305b, 0xaf02, 0x3058, 0xaf02, 0x305f, 0xaf02, 0xa23f,
+    0xe051, 0x3e5d, 0xaf0a, 0xa27f, 0xe051, 0x3e5e, 0xaf0c, 0x3c5c,
+    0x2858, 0xf0c8, 0xe162, 0x0201, 0xa20e, 0x2a5b, 0xb636, 0xcc44,
+    0xe184, 0x1da3, 0x2911, 0x3d12, 0xf0ee, 0x285f, 0xf0ba, 0x2111,
+    0x4d11, 0xcf2a, 0x2111, 0x4d11, 0xcf2c, 0x2111, 0x4d11, 0xcf2e,
+    0xf02e, 0x8131, 0x285e, 0xae08, 0x4c59, 0xae02, 0x4c58, 0xae02,
+    0x4c5b, 0xae14, 0xcf02, 0x285f, 0xcf26, 0xd190, 0x0001, 0x2825,
+    0xe418, 0x0ef5, 0xcb20, 0xf7f8, 0xcb22, 0xf188, 0xa200, 0xe41e,
+    0x0e29, 0xe082, 0x3c68, 0xe002, 0x07f0, 0xf094, 0xe41e, 0x1de7,
+    0x2867, 0xa002, 0x3c67, 0xe004, 0x0700, 0x3c68, 0xa202, 0xe42e,
+    0xd181, 0x1000, 0xe41e, 0x144e, 0xf6de, 0xd191, 0x0000, 0xe16a,
+    0x2846, 0xa002, 0x3c46, 0xa200, 0xe42e, 0xa204, 0xf02e, 0xa206,
+    0x3c06, 0xe0c0, 0x0041, 0xe005, 0x0050, 0x0a67, 0x0a67, 0xae11,
+    0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0700, 0xd112, 0x0100,
+    0x2806, 0xce26, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0065, 0xaf18,
+    0xa802, 0xe40a, 0x1e7f, 0xae0a, 0xe0c1, 0x0060, 0xaf0d, 0xa80f,
+    0xe056, 0xe0c1, 0x0044, 0xa811, 0xe056, 0xae0c, 0xe0c1, 0x0044,
+    0xa80f, 0xe056, 0xe167, 0x0ba7, 0x2f17, 0xe056, 0xe0c2, 0x0282,
+    0xe0c0, 0x006e, 0xe0c2, 0x0284, 0xaf20, 0xe0c1, 0x0282, 0xa809,
+    0xf04b, 0xe049, 0xae1f, 0xf06e, 0xe049, 0xa011, 0xaf09, 0xae07,
+    0xae21, 0xe056, 0xe0c2, 0x028c, 0xe167, 0x0ba8, 0x2d17, 0x4917,
+    0xe0c2, 0x0285, 0xe167, 0x0baa, 0x2d17, 0x4917, 0xe0c2, 0x0286,
+    0xe41e, 0x1e80, 0xe0c0, 0x004a, 0xe0c2, 0x0289, 0xe0c0, 0x004b,
+    0xe0c2, 0x028a, 0xe0c0, 0x0055, 0xe0c2, 0x028b, 0xe0c1, 0x0041,
+    0xe004, 0x0240, 0xae10, 0xe042, 0xe167, 0x0ba6, 0x2b17, 0xf05b,
+    0xe167, 0x0ba0, 0x2d17, 0x4917, 0xe0c2, 0x0287, 0xe0c1, 0x0041,
+    0xe004, 0x0258, 0xae10, 0xe042, 0xe167, 0x0ba6, 0x2b17, 0xf05b,
+    0xe167, 0x0ba2, 0x2d17, 0x4917, 0xe0c2, 0x0288, 0xe0c1, 0x0041,
+    0xe004, 0x0260, 0xae10, 0xe042, 0xe167, 0x0ba6, 0x2b17, 0xf05b,
+    0xe167, 0x0ba4, 0x2d17, 0x4917, 0xe0c2, 0x028d, 0xe0c0, 0x0065,
+    0xaf18, 0xa802, 0xe0c2, 0x0280, 0xa210, 0xe0c2, 0x0168, 0xe42e,
+    0xe167, 0x0bac, 0xe165, 0x028e, 0xe166, 0x02c0, 0xd022, 0x0008,
+    0xe184, 0x1e93, 0x2d17, 0x9f16, 0x9e85, 0xf7fb, 0x2517, 0x4d17,
+    0x9f16, 0x9e85, 0xf7fb, 0xe190, 0xe166, 0x02d2, 0xd022, 0x0008,
+    0xe184, 0x1e9f, 0x2517, 0x4d17, 0x9f16, 0x9e85, 0xf7fb, 0xe190,
+    0xe166, 0x02db, 0xd022, 0x0008, 0xe184, 0x1eab, 0x2517, 0x4d17,
+    0x9f16, 0x9e85, 0xf7fb, 0xe190, 0xe166, 0x02e4, 0xd022, 0x0008,
+    0xe184, 0x1eb6, 0x2d17, 0x9f16, 0x9e85, 0xf7fb, 0xe190, 0xe42e,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe40e, 0x0020, 0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x0131,
+    0xe470, 0xe190, 0xe40e, 0x0113, 0xe470, 0xe190, 0xe470, 0xe190,
+    0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+    0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x012f, 0xe40e, 0x0131,
+    0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058,
+    0xa200, 0xe0c2, 0x005a, 0x3cf0, 0x3cf1, 0xa2fe, 0x3cee, 0x3cef,
+    0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d, 0xce00, 0xf11e, 0xe0c0,
+    0x005c, 0xe0c1, 0x0059, 0x3eed, 0xa203, 0x5aed, 0xe052, 0xf08a,
+    0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00, 0xe41e,
+    0x008c, 0xe41e, 0x00ab, 0xe0c0, 0x005a, 0x18ee, 0xe0c1, 0x0059,
+    0xa115, 0xb636, 0x2aee, 0xb60a, 0xe418, 0x00fb, 0xe0c0, 0x005b,
+    0xe0c1, 0x005e, 0xae11, 0xe056, 0x18ef, 0xe0c1, 0x0059, 0xa117,
+    0xb636, 0xe418, 0x00b0, 0xe0c0, 0x005a, 0x18ee, 0x2aee, 0xb60a,
+    0xe0c1, 0x0059, 0xa117, 0xb636, 0xe418, 0x00f3, 0xd071, 0x802a,
+    0xe181, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100, 0xe0c0, 0x0059,
+    0xae02, 0xe000, 0x0113, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a,
+    0x3cee, 0xe41e, 0x0100, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11,
+    0xe056, 0x3cef, 0xe40e, 0x0037, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+    0x0058, 0xe0c2, 0x0008, 0xe0c0, 0x0059, 0xf7ea, 0xa11e, 0xf0e8,
+    0xa202, 0xe0c2, 0x0058, 0xe004, 0x093d, 0xe0c2, 0x0070, 0xa200,
+    0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xf6fe, 0xa202, 0xe0c2, 0x0008,
+    0xe0c2, 0x0058, 0xe42e, 0xd101, 0x0001, 0xc70f, 0xa000, 0xe42e,
+    0xa200, 0xe0c1, 0x005b, 0xf27b, 0xa220, 0xa103, 0xf2eb, 0xa230,
+    0xa103, 0xf2bb, 0xa23c, 0xa103, 0xf24b, 0xa258, 0xa103, 0xf25b,
+    0xa260, 0xa103, 0xf22b, 0xa200, 0xa103, 0xf1fb, 0xa26c, 0xa103,
+    0xf1cb, 0xe004, 0x003e, 0xa103, 0xf18b, 0xe004, 0x0044, 0xa105,
+    0xf14b, 0xe004, 0x0046, 0xa103, 0xf10b, 0xe004, 0x0000, 0xa107,
+    0xf0cb, 0xa200, 0xe0c1, 0x005e, 0xf08b, 0xe004, 0x004c, 0xf05e,
+    0xe0c1, 0x005e, 0xf02b, 0xa010, 0xae16, 0xe0c1, 0x0040, 0xe041,
+    0xca28, 0xf7f8, 0xce21, 0xd111, 0x0000, 0xd112, 0x2000, 0xd113,
+    0x000b, 0xe1e1, 0xe42e, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100,
+    0xe004, 0x0133, 0xe67c, 0xe41e, 0x0100, 0xe004, 0x0135, 0xe67c,
+    0x28ee, 0xe008, 0x03ff, 0xcca4, 0xe182, 0x0029, 0xe018, 0x2eee,
+    0xaf15, 0xcca5, 0xe182, 0x0029, 0xe019, 0xae15, 0xe042, 0xae14,
+    0x34f0, 0x3cf1, 0xe42e, 0xe40e, 0x0b3a, 0xe40e, 0x0137, 0xe40e,
+    0x013b, 0xe40e, 0x013f, 0xe40e, 0x0143, 0xe40e, 0x007e, 0xe40e,
+    0x0147, 0xe40e, 0x007e, 0xe40e, 0x014b, 0xe40e, 0x007e, 0xe40e,
+    0x007e, 0xe40e, 0x007e, 0xe40e, 0x007e, 0xe40e, 0x007e, 0xe40e,
+    0x007e, 0xe40e, 0x007e, 0xe40e, 0x03d4, 0xe40e, 0x03e7, 0xe41e,
+    0x014f, 0xe40e, 0x007e, 0xe41e, 0x01c1, 0xe40e, 0x007e, 0xe41e,
+    0x01c2, 0xe40e, 0x007e, 0xe41e, 0x02a1, 0xe40e, 0x007e, 0xe41e,
+    0x0452, 0xe40e, 0x007e, 0xe41e, 0x02d5, 0xe40e, 0x007e, 0xd130,
+    0x0003, 0xa200, 0xc401, 0xe188, 0x07ff, 0x3d11, 0xa200, 0x3c63,
+    0x3c64, 0x3c65, 0x3c62, 0x3c61, 0x3c60, 0xa200, 0x3c72, 0x3c77,
+    0x3c8d, 0x3c8e, 0x3c68, 0x3c69, 0x3c6a, 0x3c2b, 0xa202, 0xe0c2,
+    0x0078, 0xe0c0, 0x0062, 0xaf04, 0x3073, 0xaf02, 0x3078, 0x2873,
+    0xf17a, 0xe0c0, 0x0063, 0xe049, 0xe009, 0xffff, 0x3e71, 0xa01f,
+    0xaf09, 0x3e31, 0xe049, 0xaf21, 0xe009, 0xffff, 0x3e70, 0xa01f,
+    0xaf09, 0x3e30, 0x8430, 0x8231, 0xe018, 0x3c32, 0xf0ae, 0xe41e,
+    0x0b0e, 0xe0c0, 0x0062, 0x3041, 0xe41e, 0x0532, 0xe40a, 0x01bc,
+    0x2873, 0xe40a, 0x019c, 0xa200, 0x3c2b, 0x3c74, 0xe41e, 0x0afc,
+    0xa202, 0x3c52, 0x3c23, 0x3c59, 0x2070, 0x4c71, 0xe0c2, 0x0071,
+    0x2c21, 0xa102, 0xae20, 0x4c20, 0xe0c2, 0x0072, 0xa200, 0xe0c2,
+    0x0075, 0x2841, 0xae02, 0xa006, 0xe0c2, 0x0073, 0xa200, 0x3c72,
+    0xe0c2, 0x0074, 0xa202, 0xae20, 0xe0c2, 0x007b, 0xe41e, 0x0c4d,
+    0xa202, 0xe0c2, 0x0070, 0xe42e, 0xa200, 0x3c72, 0xe0c2, 0x0070,
+    0xe42e, 0xe42e, 0xa200, 0xcc4a, 0xcc4c, 0xcc72, 0xa2fc, 0xe0c2,
+    0x0077, 0xa2fa, 0xe0c2, 0x0071, 0xa202, 0xe0c2, 0x0076, 0x2877,
+    0xf06a, 0xe41e, 0x0b4b, 0xe128, 0xa200, 0x3c77, 0xe0c0, 0x0045,
+    0xaf04, 0xa802, 0x4473, 0xb7f0, 0xf04a, 0xe0c2, 0x0071, 0xe42e,
+    0xa2fe, 0xe0c2, 0x0077, 0xe41e, 0x0305, 0xe41e, 0x0333, 0xf058,
+    0xa2fc, 0xe0c2, 0x0071, 0xe42e, 0xa2fc, 0xe0c2, 0x0077, 0xd130,
+    0x0003, 0xd03a, 0x0003, 0xd04b, 0x0001, 0xd04c, 0x0000, 0xd008,
+    0x0000, 0xa200, 0xe0c2, 0x030a, 0x3c29, 0x288e, 0xf228, 0xa200,
+    0x3c74, 0x2873, 0xf04a, 0xe41e, 0x0ad1, 0xf05e, 0xe41e, 0x069a,
+    0x288e, 0xf178, 0xe41e, 0x06bc, 0x2a73, 0xf0eb, 0xe0c1, 0x0065,
+    0xa809, 0xf0ab, 0x2a22, 0xf08b, 0xa2fa, 0xe0c2, 0x0071, 0x2822,
+    0xe0c2, 0x0073, 0xe42e, 0xe40a, 0x0266, 0xe41e, 0x0c33, 0xf19a,
+    0x2a44, 0x4e42, 0xf03b, 0x288d, 0xf06a, 0xa2fe, 0xe0c2, 0x0071,
+    0xa202, 0xe42e, 0xa202, 0x3c8d, 0x2a79, 0x3e7b, 0x287a, 0x3c7d,
+    0xe0c2, 0x0071, 0xe41e, 0x093c, 0xe41e, 0x0342, 0xa202, 0xe42e,
+    0xe41e, 0x0750, 0x2825, 0xf0a8, 0xa200, 0x3c28, 0x2832, 0x3c27,
+    0xe41e, 0x04af, 0xa200, 0x3c29, 0xf05e, 0xe41e, 0x0458, 0xe40a,
+    0x0266, 0xe41e, 0x097d, 0x2c2b, 0xa002, 0x3c2b, 0xe0c2, 0x0070,
+    0x2822, 0xe0c2, 0x0073, 0x2070, 0x4c71, 0xe0c2, 0x006f, 0x2829,
+    0xe0c2, 0x0072, 0xc84a, 0xc84d, 0xae20, 0xe056, 0xe0c2, 0x0053,
+    0xe41e, 0x031c, 0xa202, 0xe0c2, 0x0076, 0xe42e, 0xe41e, 0x097d,
+    0xe41e, 0x031c, 0xa200, 0xe0c2, 0x0076, 0xe42e, 0x2834, 0x4c35,
+    0xe01a, 0x3c46, 0x2842, 0xf11a, 0x2834, 0xe41a, 0x039a, 0x2834,
+    0xaf02, 0xe000, 0x0640, 0xe09e, 0x2907, 0x2a34, 0xa803, 0xf029,
+    0xaf10, 0xe008, 0x001f, 0x3c43, 0x2843, 0xae02, 0x4c46, 0xae02,
+    0x4c47, 0xae0e, 0x4c34, 0xae0e, 0x4c35, 0xe0c1, 0x014b, 0xf7e9,
+    0xe0c2, 0x014d, 0xa202, 0xe0c2, 0x014a, 0xe42e, 0x2834, 0xa002,
+    0x3c34, 0x1830, 0xe428, 0x3c34, 0x2835, 0xa002, 0x3c35, 0x1831,
+    0xe42e, 0xd130, 0x0003, 0xca28, 0xf7f8, 0xe41e, 0x0724, 0xe0c0,
+    0x0060, 0xe42a, 0xca29, 0xf7f9, 0xe0c0, 0x0042, 0xce20, 0xd111,
+    0x0300, 0xd112, 0x00c0, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe0c0,
+    0x0060, 0x3c2c, 0xe0c0, 0x0061, 0x3c40, 0xe41e, 0x0a03, 0xe42e,
+    0xe0c0, 0x0040, 0xa24d, 0xae17, 0xe042, 0xe005, 0x1700, 0xae03,
+    0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0100, 0xd112, 0x0100,
+    0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0060, 0xf08a,
+    0xe0c0, 0x0061, 0x2210, 0x4e11, 0xe046, 0xaf12, 0xae02, 0x3c13,
+    0xa200, 0x3c6a, 0xe180, 0xe41e, 0x0b2d, 0xe41e, 0x0b99, 0xe41e,
+    0x0a03, 0xe166, 0x0054, 0x9e06, 0xf16a, 0x282c, 0xa102, 0xcc44,
+    0xa200, 0x3c3c, 0xe184, 0x0300, 0x9e06, 0x5c3c, 0xa802, 0xf07a,
+    0x283c, 0xe000, 0x03c0, 0xe09e, 0xa208, 0x3d07, 0x283c, 0xa002,
+    0x3c3c, 0xe190, 0xa202, 0x3c77, 0xe42e, 0x282c, 0xa102, 0xcc44,
+    0xa200, 0x3c3c, 0xe184, 0x031a, 0xe0c0, 0x0054, 0x5c3c, 0xa802,
+    0xf058, 0x283c, 0xe41e, 0x0a43, 0xf04e, 0x283c, 0xe41e, 0x0a4a,
+    0x2a3c, 0xa003, 0x3e3c, 0xe42e, 0xe004, 0x03c0, 0xe09e, 0xe004,
+    0x0054, 0xe09c, 0x282c, 0xa102, 0xcc44, 0xa200, 0x3c3c, 0xe184,
+    0x0330, 0x2b17, 0xaf05, 0xa803, 0x5a3c, 0xe056, 0x2a3c, 0xa003,
+    0x3e3c, 0x9f06, 0xe42e, 0xe161, 0x03c0, 0x282c, 0xa102, 0xcc44,
+    0xa200, 0xe184, 0x033e, 0x2b11, 0xa80d, 0xe01b, 0xe042, 0x182c,
+    0xe01a, 0xe42e, 0xa200, 0x3c34, 0x3c35, 0xa202, 0x3c47, 0xe41e,
+    0x026e, 0xe41e, 0x0296, 0xf7c8, 0xa200, 0x3c47, 0xe41e, 0x026e,
+    0xe190, 0xe0c1, 0x014b, 0xf7e9, 0xe42e, 0x2a24, 0x2834, 0xa802,
+    0xf0e8, 0xae11, 0x3e8a, 0x2834, 0xa002, 0x1830, 0xe428, 0x2834,
+    0xaf02, 0xe000, 0x0600, 0xe09e, 0x3f07, 0xf0ee, 0x2a8a, 0x2834,
+    0xaf02, 0xe000, 0x0600, 0xe09e, 0x4e24, 0x3f07, 0x2834, 0xa002,
+    0x1830, 0xe428, 0xf01e, 0x2830, 0xa002, 0xaf02, 0xa006, 0xa2f9,
+    0xe052, 0xae02, 0x3c3b, 0x2879, 0xa806, 0x3c3d, 0xe0c1, 0x0041,
+    0xe004, 0x029c, 0xae10, 0xe042, 0x843d, 0xe182, 0x2000, 0xe019,
+    0xe042, 0x8435, 0x823b, 0xe019, 0xe042, 0xca29, 0xf7f9, 0xce20,
+    0xd111, 0x0600, 0x283b, 0xaf02, 0xce24, 0xa204, 0xce26, 0xca28,
+    0xf7f8, 0xe42e, 0x2a34, 0x288b, 0xa803, 0xf02b, 0xe42e, 0x2834,
+    0xe41a, 0x03ad, 0x2834, 0xaf02, 0xe000, 0x0640, 0xe09e, 0x2907,
+    0xe049, 0xaf10, 0xa83f, 0x3e8b, 0xe42e, 0x2830, 0xa002, 0xaf02,
+    0xa006, 0xa2f9, 0xe052, 0xae02, 0x3c3b, 0x287b, 0xa806, 0x3c3d,
+    0xe0c1, 0x0041, 0xe004, 0x029c, 0xae10, 0xe042, 0x843d, 0xe182,
+    0x2000, 0xe019, 0xe042, 0x8435, 0x823b, 0xe019, 0xe042, 0xca29,
+    0xf7f9, 0xce20, 0xd111, 0x0640, 0x283b, 0xaf02, 0xce24, 0xa206,
+    0xce26, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x005a, 0x3cee, 0xe41e,
+    0x0100, 0xa206, 0xe41e, 0x03f0, 0xe0c0, 0x005a, 0x3cee, 0xe41e,
+    0x0100, 0xa226, 0xe41e, 0x0406, 0xe41e, 0x041c, 0xe42e, 0xa224,
+    0xe41e, 0x0406, 0xe41e, 0x0437, 0xa204, 0xe41e, 0x03f0, 0xe42e,
+    0x3ced, 0xe0c0, 0x0041, 0xe005, 0x0280, 0xae11, 0xe042, 0x22f0,
+    0x4ef1, 0xe042, 0xce20, 0xca29, 0xf7f9, 0xd111, 0x0000, 0xd112,
+    0x0c00, 0x88ed, 0x0113, 0xca28, 0xf7f8, 0xe42e, 0x3ced, 0xe0c0,
+    0x0041, 0xe005, 0x0298, 0xae11, 0xe042, 0x22f0, 0x4ef1, 0xe042,
+    0xca29, 0xf7f9, 0xce20, 0xd111, 0x0000, 0xd112, 0x0100, 0x88ed,
+    0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe161, 0x07e0, 0x8911, 0x0034,
+    0x8911, 0x0033, 0x8911, 0x0035, 0x8911, 0x0036, 0x8911, 0x0037,
+    0x8911, 0x0038, 0x2111, 0x4d11, 0xcc60, 0x2111, 0x4d11, 0xcc62,
+    0x2111, 0x4d11, 0xcc64, 0x2111, 0x4d11, 0xcc72, 0xe42e, 0xe161,
+    0x07e0, 0x8b11, 0x0034, 0x8b11, 0x0033, 0x8b11, 0x0035, 0x8b11,
+    0x0036, 0x8b11, 0x0037, 0x8b11, 0x0038, 0xc860, 0x3511, 0x3d11,
+    0xc862, 0x3511, 0x3d11, 0xc864, 0x3511, 0x3d11, 0xc872, 0x3511,
+    0x3d11, 0xe42e, 0xa200, 0x3c6a, 0x3c69, 0x3c2b, 0x3c8d, 0xe42e,
+    0x2824, 0xe0c2, 0x0115, 0xa202, 0xcf66, 0xa200, 0x3c33, 0x3c28,
+    0xcf64, 0xcf62, 0xa200, 0x3c51, 0x2833, 0x0850, 0x3c51, 0x2a51,
+    0x1a32, 0xf037, 0x2a32, 0x3e51, 0xe41e, 0x047a, 0x2a3a, 0xa003,
+    0x3e3a, 0x1851, 0xf064, 0x2851, 0x1832, 0xf6f4, 0xa202, 0xe42e,
+    0xa200, 0xe42e, 0x2866, 0x5401, 0x3c66, 0x2833, 0xc70f, 0x7c30,
+    0x3434, 0x3c35, 0x2833, 0xe002, 0x0094, 0xf028, 0xe190, 0xe41e,
+    0x04d0, 0xe40a, 0x04a6, 0x2873, 0xf08a, 0xc872, 0x2676, 0x4e75,
+    0xae07, 0xe045, 0xe405, 0x04a6, 0xe41e, 0x0518, 0x2034, 0x4c35,
+    0xcf62, 0x2833, 0xe002, 0x00c8, 0xf028, 0xe190, 0x2833, 0x1851,
+    0xf628, 0xa204, 0xcf66, 0x2833, 0x3c28, 0xe42e, 0x2833, 0x3c28,
+    0x2851, 0x3c27, 0xe41e, 0x04af, 0x2833, 0xe16a, 0xf73e, 0x2c2b,
+    0xe016, 0x3c36, 0xe016, 0x3c37, 0xa200, 0x3c38, 0x2828, 0x3c33,
+    0xc70f, 0x7c30, 0x3434, 0x3c35, 0x2833, 0x1827, 0xf0d2, 0x2822,
+    0xe418, 0x0c7b, 0xa202, 0xe41e, 0x09b4, 0xe41e, 0x0518, 0x2034,
+    0x4c35, 0xcf62, 0xf72e, 0x2827, 0x1828, 0x0829, 0x3c29, 0xe42e,
+    0x2853, 0xae06, 0xcf26, 0xd190, 0x0002, 0xcb20, 0xf7f8, 0xcb22,
+    0xe408, 0x0513, 0xcb02, 0xaf0e, 0x3038, 0xaf08, 0x3036, 0xaf02,
+    0x3037, 0xaf12, 0x3c39, 0x2836, 0x4c37, 0xe41a, 0x0c66, 0x2836,
+    0x4c37, 0xe418, 0x052c, 0x2822, 0xf068, 0x8839, 0x0182, 0xe190,
+    0xcb04, 0x3c39, 0x2837, 0x4422, 0xe418, 0x0c7b, 0xe40d, 0x0513,
+    0x2837, 0xf158, 0x2836, 0xcf26, 0x2839, 0xae08, 0x4c37, 0xae02,
+    0x4c36, 0xae16, 0xcf02, 0xd190, 0x0001, 0x2822, 0xe418, 0x0c7b,
+    0xf0bd, 0xcb20, 0xf7f8, 0xcb22, 0xe408, 0x0513, 0xa200, 0xe41e,
+    0x09b4, 0xa202, 0xe42e, 0xd191, 0x0000, 0xe16a, 0xa200, 0xe42e,
+    0xa202, 0xcf10, 0x2833, 0xa002, 0x3c33, 0xcf64, 0x2834, 0xa002,
+    0x3c34, 0x1830, 0xe428, 0xa208, 0xcf66, 0xa200, 0x3c34, 0x2835,
+    0xa002, 0x3c35, 0x1831, 0xe42e, 0xa201, 0xe161, 0x03e0, 0x3f11,
+    0x3f11, 0xe42e, 0xe41e, 0x071f, 0x2872, 0xf138, 0xba3e, 0x3c00,
+    0x3401, 0xe004, 0x4646, 0x1800, 0xf088, 0xe004, 0x5249, 0x1801,
+    0xf048, 0xe41e, 0x0572, 0xf038, 0xba4e, 0xf6fe, 0xa202, 0xe42e,
+    0xa200, 0xe42e, 0xba3e, 0x3c00, 0x3401, 0xe080, 0x1800, 0xf068,
+    0xe082, 0x1801, 0xf038, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xba7e,
+    0x3402, 0x3c03, 0x2c02, 0x2e02, 0xaf10, 0xe008, 0x00ff, 0xae11,
+    0xe009, 0xff00, 0xe056, 0x3c02, 0x2c03, 0x2e03, 0xaf10, 0xe008,
+    0x00ff, 0xae11, 0xe009, 0xff00, 0xe056, 0x3c03, 0x2c03, 0x0c02,
+    0xe01a, 0xe42e, 0xa200, 0x3c05, 0xe160, 0x4646, 0xe161, 0x5249,
+    0xe41e, 0x054a, 0xba7e, 0xba7e, 0xe160, 0x4920, 0xe161, 0x4156,
+    0xe41e, 0x054a, 0xe408, 0x058c, 0xe160, 0x4958, 0xe161, 0x4156,
+    0xe41e, 0x054a, 0xe40a, 0x068d, 0xba7e, 0xa200, 0xe160, 0x5354,
+    0xe161, 0x4c49, 0xe41e, 0x054a, 0xf0fa, 0xba7e, 0xe41e, 0x0557,
+    0xe160, 0x7669, 0xe161, 0x6d6f, 0xe41e, 0x054a, 0xba7f, 0xe408,
+    0x0688, 0xe40e, 0x0686, 0xe160, 0x6968, 0xe161, 0x6176, 0xe41e,
+    0x054a, 0xf29a, 0xba7e, 0xe41e, 0x0557, 0x2802, 0xaf04, 0xa114,
+    0x3c04, 0xba7e, 0xba7e, 0xba7e, 0xba7e, 0xba7e, 0xba7e, 0xba7e,
+    0xba7e, 0xe41e, 0x0557, 0x2802, 0x3c70, 0xa01e, 0xaf08, 0x3c30,
+    0xe41e, 0x0557, 0x2802, 0x3c71, 0xa01e, 0xaf08, 0x3c31, 0x8430,
+    0x8231, 0xe018, 0x3c32, 0x2804, 0xf04a, 0xba7f, 0xa102, 0xf7de,
+    0xe40e, 0x0686, 0xe160, 0x7268, 0xe161, 0x7374, 0xe41e, 0x054a,
+    0xe40a, 0x063c, 0xba7e, 0xe41e, 0x0557, 0x2802, 0xaf04, 0xa114,
+    0x3c04, 0xe160, 0x6473, 0xe161, 0x7669, 0xe41e, 0x054a, 0xba7f,
+    0xf32a, 0xa202, 0x3c05, 0xe160, 0x7633, 0xe161, 0x6469, 0xe41e,
+    0x054a, 0xf238, 0xe160, 0x5633, 0xe161, 0x4449, 0xe41e, 0x054a,
+    0xf1c8, 0xe160, 0x7634, 0xe161, 0x6469, 0xe41e, 0x054a, 0xf158,
+    0xe160, 0x5634, 0xe161, 0x4449, 0xe41e, 0x054a, 0xf0e8, 0xe160,
+    0x3433, 0xe161, 0x6d70, 0xe41e, 0x054a, 0xf078, 0xe160, 0x3433,
+    0xe161, 0x4d50, 0xe41e, 0x054a, 0x3c52, 0xba7f, 0x2804, 0xa102,
+    0x3c04, 0xf0ae, 0xe160, 0x6473, 0xe161, 0x6175, 0xe41e, 0x054a,
+    0xba7f, 0xa200, 0x3c05, 0xba7e, 0xba7e, 0xba7e, 0x2805, 0xf048,
+    0xba7e, 0xba7e, 0xf07e, 0xe41e, 0x068f, 0x3c21, 0xe41e, 0x068f,
+    0x3c20, 0xba7e, 0xba7e, 0xba7e, 0xba7e, 0x2804, 0xf04a, 0xba7f,
+    0xa102, 0xf7de, 0xe40e, 0x0686, 0xe160, 0x7266, 0xe161, 0x7374,
+    0xe41e, 0x054a, 0xe40a, 0x0685, 0xba7e, 0xe41e, 0x0557, 0x2802,
+    0xaf04, 0x3c04, 0x2805, 0xf33a, 0x2804, 0xa10a, 0x3c04, 0xba7e,
+    0xe41e, 0x0557, 0x2802, 0xa01e, 0xaf08, 0x3c30, 0xe41e, 0x0557,
+    0x2802, 0xa01e, 0xaf08, 0x3c31, 0x8430, 0x8231, 0xe018, 0x3c32,
+    0xba7e, 0xe160, 0x7633, 0xe161, 0x6469, 0xe41e, 0x054a, 0xf158,
+    0xe160, 0x5633, 0xe161, 0x4449, 0xe41e, 0x054a, 0xf0e8, 0xe160,
+    0x7634, 0xe161, 0x6469, 0xe41e, 0x054a, 0xf078, 0xe160, 0x5634,
+    0xe161, 0x4449, 0xe41e, 0x054a, 0x3c52, 0xba7f, 0x2804, 0xf04a,
+    0xba7f, 0xa102, 0xf7de, 0xe40e, 0x0686, 0xba7e, 0xe40e, 0x058d,
+    0xa202, 0x3c23, 0x3c59, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xba4e,
+    0xba4f, 0xae11, 0xe056, 0xba4f, 0xae21, 0xe056, 0xba4f, 0xae31,
+    0xe056, 0xe42e, 0xe41e, 0x071f, 0xe160, 0x7831, 0xe161, 0x6964,
+    0xe41e, 0x054a, 0xe408, 0x06b5, 0xe160, 0x6462, 0xe161, 0x3030,
+    0xe41e, 0x054a, 0xe408, 0x06b7, 0xe160, 0x6463, 0xe161, 0x3030,
+    0xe41e, 0x054a, 0xf058, 0xba4e, 0xf68e, 0xa202, 0x3c8e, 0xba7e,
+    0xe41e, 0x0557, 0xf62a, 0xe42e, 0x2873, 0xf04a, 0x2076, 0x4c75,
+    0xe42a, 0xba42, 0x3c22, 0x3c26, 0xba48, 0x3c24, 0x2822, 0xf2b8,
+    0xa224, 0x3c56, 0xa228, 0x3c57, 0xa22c, 0x3c55, 0xa232, 0x3c54,
+    0xa202, 0x3c23, 0xba48, 0xa12c, 0xe406, 0x071d, 0x3c50, 0x2831,
+    0xc70f, 0x7c50, 0x3c50, 0x8430, 0x8250, 0xe018, 0x3c50, 0xba40,
+    0xf05a, 0xba40, 0xa235, 0xe042, 0x3c54, 0xba40, 0xf05a, 0xba40,
+    0xa22f, 0xe042, 0x3c55, 0xba40, 0xa225, 0xe042, 0x3c56, 0xa004,
+    0x3c57, 0xf27e, 0xa224, 0x3c56, 0xa228, 0x3c57, 0xa22c, 0x3c55,
+    0xa232, 0x3c54, 0xa238, 0x3c58, 0x2859, 0xf04a, 0x2823, 0xe016,
+    0xf02e, 0xa202, 0x3c23, 0xba40, 0x3c53, 0xba40, 0xf08a, 0xba41,
+    0xa22e, 0xe042, 0x3c55, 0xa234, 0xe042, 0x3c54, 0xba40, 0xa225,
+    0xe042, 0x3c56, 0xa004, 0x3c57, 0xba40, 0xa239, 0xe042, 0x3c58,
+    0xa202, 0x3c25, 0xa202, 0xe42e, 0xba7e, 0xa200, 0xe42e, 0xc868,
+    0xa80e, 0x3c2a, 0x742a, 0xe42e, 0xe0c0, 0x0064, 0x3c81, 0x3480,
+    0xe0c0, 0x0065, 0x3c83, 0x3482, 0xe0c0, 0x0066, 0x3c85, 0x3484,
+    0xe0c0, 0x0067, 0x3c87, 0x3486, 0xe0c0, 0x0069, 0xe167, 0x0ba0,
+    0x3d17, 0x3517, 0xe0c0, 0x006a, 0x3d17, 0x3517, 0xe0c0, 0x006b,
+    0x3d17, 0x3517, 0xe0c0, 0x0042, 0xe000, 0x1000, 0xce20, 0xd111,
+    0x0ba8, 0xd112, 0x004c, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e,
+    0xa200, 0xcf24, 0xcf46, 0xcf68, 0xe0c2, 0x0104, 0xe0c2, 0x0140,
+    0xe0c2, 0x0149, 0xe0c2, 0x0308, 0xe0c2, 0x030d, 0xe0c2, 0x0309,
+    0xe0c2, 0x030a, 0xe0c2, 0x030b, 0xe0c2, 0x0168, 0xcc8e, 0xe0c2,
+    0x0320, 0xa200, 0x3c66, 0x3c62, 0x3c60, 0xa246, 0xe0c2, 0x0100,
+    0xe004, 0x00d6, 0xe0c2, 0x017c, 0xe004, 0x0014, 0xe0c2, 0x017d,
+    0xe0c0, 0x0050, 0x3048, 0xaf02, 0x3049, 0xaf02, 0x304a, 0xaf02,
+    0x304b, 0xaf0a, 0x304c, 0xaf02, 0x304d, 0xaf02, 0x304e, 0xaf02,
+    0x304f, 0xe0c0, 0x0050, 0xaf1c, 0xa802, 0xe005, 0x0ba6, 0xe09f,
+    0x3d17, 0x284c, 0x4448, 0x3c48, 0x284d, 0x4449, 0x3c49, 0x284e,
+    0x444a, 0x3c4a, 0x284f, 0x444b, 0x3c4b, 0xa200, 0x2a48, 0xf03b,
+    0xe00a, 0x0002, 0x2a49, 0xf03b, 0xe00a, 0x0009, 0x2a4a, 0xf03b,
+    0xe00a, 0x0020, 0x2a4b, 0xf03b, 0xe00a, 0x0040, 0xe005, 0x0ba6,
+    0xe09f, 0x2b17, 0xae05, 0xe056, 0xe0c2, 0x0169, 0xe0c1, 0x0041,
+    0xe004, 0x0044, 0xae10, 0xe042, 0x2a4e, 0xf03b, 0x2084, 0x4c85,
+    0xe0c2, 0x0211, 0xe0c1, 0x0041, 0xe004, 0x0080, 0xae10, 0xe042,
+    0x2a4f, 0xf03b, 0x2086, 0x4c87, 0xe0c2, 0x0212, 0x2854, 0xa132,
+    0xae04, 0xe049, 0x2855, 0xa12c, 0xe055, 0xae03, 0x2856, 0xa124,
+    0xe055, 0xcf33, 0xe0c1, 0x0041, 0xe004, 0x003c, 0xae10, 0xe042,
+    0x2a4c, 0xf03b, 0x2080, 0x4c81, 0xcf44, 0xa220, 0x4c22, 0xae02,
+    0xcf00, 0xa200, 0xcf46, 0x2830, 0xae20, 0x4c31, 0xae08, 0xe0c2,
+    0x0101, 0xe0c2, 0x0283, 0xcf60, 0xe0c0, 0x0041, 0xe005, 0x0000,
+    0xae11, 0xe042, 0x2a4d, 0xf03b, 0x2082, 0x4c83, 0xe0c2, 0x0103,
+    0xe0c0, 0x0044, 0xa80e, 0xae1a, 0x4c40, 0xe0c2, 0x0102, 0x287b,
+    0xe412, 0x0a35, 0x2879, 0x3c7b, 0xe412, 0x0a3c, 0x2841, 0x3c3e,
+    0xe41e, 0x0a12, 0xe0c2, 0x0077, 0x3c79, 0x3c7a, 0x2a41, 0xf07b,
+    0xa200, 0x3c3e, 0xe41e, 0x0a12, 0x3c7c, 0x3c7a, 0xa206, 0xae08,
+    0x4c22, 0xae06, 0xe0c1, 0x0065, 0xaf19, 0xa803, 0xae17, 0xe056,
+    0xe0c2, 0x0204, 0xa204, 0x1841, 0xe0c2, 0x0210, 0xa204, 0xe0c2,
+    0x0208, 0x8479, 0xc786, 0xe018, 0xe000, 0x0300, 0xe09e, 0x2117,
+    0x4d17, 0xe0c2, 0x020d, 0x2117, 0x4d17, 0xe0c2, 0x020e, 0x2117,
+    0x4d17, 0xe0c2, 0x020f, 0x2841, 0xf13a, 0x847c, 0xc786, 0xe018,
+    0xe000, 0x0300, 0xe09e, 0x2117, 0x4d17, 0xe0c2, 0x0214, 0x2117,
+    0x4d17, 0xe0c2, 0x0215, 0x2117, 0x4d17, 0xe0c2, 0x0216, 0x287b,
+    0xf2d4, 0xa202, 0xe0c2, 0x0302, 0x287b, 0xae04, 0x087b, 0x087b,
+    0xe000, 0x0300, 0xe09e, 0x2117, 0x4d17, 0xe0c2, 0x0380, 0x2117,
+    0x4d17, 0xe0c2, 0x0381, 0x2117, 0x4d17, 0xe0c2, 0x0382, 0xe004,
+    0x0055, 0xe0c2, 0x030c, 0xa208, 0x4c23, 0xe0c2, 0x0303, 0xa202,
+    0xae02, 0xa902, 0xe0c2, 0x0312, 0xa220, 0xe0c2, 0x0313, 0xa200,
+    0xe0c2, 0x0308, 0xa200, 0xe0c2, 0x0302, 0xa200, 0x3c44, 0x3c45,
+    0x3c42, 0xa202, 0x3c47, 0x287d, 0xf3d4, 0xe0c0, 0x0060, 0xa87e,
+    0xe049, 0xaf08, 0xf37a, 0x3044, 0xaf02, 0x3042, 0xa81f, 0x3e45,
+    0x847d, 0xc786, 0xe018, 0xe000, 0x0300, 0xe09e, 0x2117, 0x4d17,
+    0xe0c2, 0x0143, 0x2117, 0x4d17, 0xe0c2, 0x0144, 0x2117, 0x4d17,
+    0xe0c2, 0x0145, 0x2840, 0xe0c2, 0x0141, 0xe0c0, 0x0064, 0xe0c2,
+    0x014c, 0x2830, 0xa102, 0xae20, 0x4c31, 0xa102, 0xe0c2, 0x0142,
+    0x2842, 0xae08, 0x4c45, 0xe0c2, 0x014e, 0xe0c0, 0x0061, 0xe0c2,
+    0x0146, 0xe0c0, 0x0062, 0xe0c2, 0x0147, 0xe0c0, 0x0063, 0xe0c2,
+    0x0148, 0x287a, 0x3c7d, 0xe0c2, 0x0071, 0xa202, 0x3c3a, 0xa202,
+    0xe0c2, 0x0106, 0xa201, 0xe167, 0x0ba7, 0x3f17, 0xe41e, 0x0c87,
+    0xe0c0, 0x0065, 0xaf0c, 0xa80e, 0xe42a, 0xca29, 0xf7f9, 0xe180,
+    0xe0c1, 0x006a, 0xce21, 0xd112, 0x000c, 0xd111, 0x0508, 0xd113,
+    0x0003, 0xca29, 0xf7f9, 0xe181, 0x3063, 0xaf02, 0x3064, 0xaf02,
+    0x3065, 0x2865, 0xf2aa, 0xa210, 0x3c3b, 0xe162, 0x03c0, 0xe163,
+    0x0500, 0xa201, 0xd022, 0x0002, 0xe184, 0x0901, 0x2912, 0xa81e,
+    0xe055, 0xae09, 0x2912, 0xa81e, 0xe055, 0x3f13, 0x283b, 0xa102,
+    0xf03a, 0x3c3b, 0xf6fe, 0xe162, 0x050a, 0x2112, 0x4d12, 0xca29,
+    0xf7f9, 0xe180, 0xce20, 0xd112, 0x0008, 0xd111, 0x0500, 0xd113,
+    0x0002, 0xca28, 0xf7f8, 0xe181, 0xe162, 0x0508, 0xe160, 0x0002,
+    0xa200, 0x2a65, 0xb632, 0xae10, 0x3d12, 0xa220, 0x3d12, 0x8132,
+    0xa200, 0x2a64, 0xb652, 0xae10, 0x3d12, 0x2832, 0x3d12, 0x8132,
+    0x2a63, 0x2822, 0xe01a, 0xe051, 0xa200, 0xb692, 0xae10, 0x4c22,
+    0x3d12, 0x2832, 0x3d12, 0xe42e, 0xe0c0, 0x0060, 0xe049, 0xa81e,
+    0x3c45, 0xaf09, 0x3244, 0xaf03, 0x3242, 0x847d, 0xc786, 0xe018,
+    0xe000, 0x0300, 0xe09e, 0x2117, 0x4d17, 0xe0c2, 0x0143, 0x2117,
+    0x4d17, 0xe0c2, 0x0144, 0x2117, 0x4d17, 0xe0c2, 0x0145, 0xa200,
+    0xe0c2, 0x0140, 0xe0c2, 0x0149, 0x2840, 0xe0c2, 0x0141, 0xe0c0,
+    0x0064, 0xe0c2, 0x014c, 0x2830, 0xa102, 0xae20, 0x4c31, 0xa102,
+    0xe0c2, 0x0142, 0x2842, 0xae08, 0x4c45, 0xe0c2, 0x014e, 0xe0c0,
+    0x0061, 0xe0c2, 0x0146, 0xe0c0, 0x0062, 0xe0c2, 0x0147, 0xe0c0,
+    0x0063, 0xe0c2, 0x0148, 0xa203, 0xe42e, 0x2824, 0x3c43, 0xe0c0,
+    0x0065, 0xaf0c, 0xa80e, 0xf10a, 0xca29, 0xf7f9, 0xe180, 0xe0c0,
+    0x006a, 0xce20, 0xd112, 0x000c, 0xd111, 0x0508, 0xd113, 0x0002,
+    0xca28, 0xf7f8, 0xe181, 0xe0c0, 0x0111, 0xf7e8, 0xe0c0, 0x0065,
+    0xaf18, 0xa802, 0xf04a, 0xe0c0, 0x0281, 0xf7ea, 0x2844, 0x4c42,
+    0xe42a, 0xa204, 0xae0e, 0x4c30, 0xa102, 0xae0e, 0x4c31, 0xa102,
+    0xe0c1, 0x014b, 0xf7e9, 0xe0c2, 0x014d, 0xa202, 0xe0c2, 0x014a,
+    0xe0c1, 0x014b, 0xf7e9, 0xe42e, 0x2a64, 0xf0cb, 0xa802, 0xae02,
+    0x2a66, 0xa803, 0xe056, 0xae0c, 0x2a24, 0xa87f, 0xe056, 0xe41e,
+    0x0a67, 0xa27f, 0x2836, 0xf028, 0x2a39, 0xe0c3, 0x012a, 0x2836,
+    0xe0c2, 0x0114, 0x2841, 0xf06a, 0x2837, 0xe016, 0xae0a, 0x4c24,
+    0xcf6a, 0x2a63, 0x2822, 0xe01a, 0xe051, 0xf16b, 0xe004, 0x0480,
+    0x0860, 0xe094, 0x2836, 0xf0e8, 0xa202, 0xae1f, 0xe0c0, 0x03b0,
+    0xb616, 0x3512, 0x3d0a, 0x2902, 0xe008, 0x7fff, 0xe056, 0x3d12,
+    0x8112, 0xe41e, 0x0aa5, 0xe41e, 0x09fa, 0xe0c0, 0x0111, 0xf7e8,
+    0xa202, 0xe0c2, 0x0110, 0xe41e, 0x0355, 0x2844, 0x4c42, 0xe418,
+    0x026e, 0xe42e, 0x283a, 0xe0c2, 0x0131, 0xa200, 0x3c3a, 0x4c38,
+    0xe0c2, 0x0130, 0xe42e, 0xa2fe, 0x3c7b, 0x3c79, 0x3c7a, 0x3c7d,
+    0xa200, 0x3c7e, 0xe161, 0x03c0, 0x2a2c, 0xa103, 0x3e3b, 0x863b,
+    0x3d11, 0xe42e, 0x287e, 0x3c3c, 0x283c, 0xe000, 0x03c0, 0xe092,
+    0x2901, 0xf10a, 0x283c, 0xa002, 0x3c3c, 0x182c, 0xf038, 0xa200,
+    0x3c3c, 0x283c, 0x187e, 0xf718, 0x283c, 0xe0c2, 0x007f, 0xa2fe,
+    0xe42e, 0xa208, 0x5c3e, 0x3d01, 0x283c, 0xa002, 0x3c7e, 0x182c,
+    0xf038, 0xa200, 0x3c7e, 0x283c, 0xe42e, 0xe000, 0x03c0, 0xe092,
+    0x2901, 0xa808, 0x3d01, 0xe42e, 0xe000, 0x03c0, 0xe092, 0x2901,
+    0xa904, 0x3d01, 0xe42e, 0xe000, 0x03c0, 0xe092, 0x2901, 0xa804,
+    0x3d01, 0xe42e, 0xe000, 0x03c0, 0xe092, 0x2901, 0xa908, 0x3d01,
+    0xe42e, 0x2834, 0x4c35, 0xe01a, 0x3c46, 0x2843, 0xae02, 0x4c46,
+    0xae02, 0x4c47, 0xae0e, 0x4c34, 0xae0e, 0x4c35, 0xe0c1, 0x014b,
+    0xf7e9, 0xe0c2, 0x014d, 0xa202, 0xe0c2, 0x014a, 0xe42e, 0x2a33,
+    0xa803, 0xf0f9, 0xae10, 0x3c61, 0x2a32, 0xa103, 0x1a33, 0xe429,
+    0xe005, 0x0400, 0x0a62, 0xe095, 0x3d02, 0xe41e, 0x0a8f, 0xe42e,
+    0x4c61, 0xe005, 0x0400, 0x0a62, 0xe095, 0x3d02, 0x2862, 0xa002,
+    0x3c62, 0xe002, 0x0080, 0xf068, 0xe41e, 0x0a8f, 0xa200, 0x3c62,
+    0xe42e, 0x2832, 0xa102, 0x1833, 0xe41a, 0x0a8f, 0xe42e, 0x2a33,
+    0xaf11, 0xae11, 0xe162, 0x050e, 0x2112, 0x4d12, 0xe042, 0xca29,
+    0xf7f9, 0xe180, 0xce20, 0xd112, 0x0080, 0xd111, 0x0400, 0xd113,
+    0x0002, 0xca28, 0xf7f8, 0xe181, 0xe42e, 0x2836, 0xf04a, 0xa201,
+    0x3f12, 0x3f12, 0x2860, 0xa004, 0x3c60, 0xe002, 0x0080, 0xf068,
+    0xe41e, 0x0abb, 0xa200, 0x3c60, 0xe42e, 0x2832, 0xa102, 0x1833,
+    0xe41a, 0x0abb, 0xe42e, 0x2a33, 0xaf0d, 0xae11, 0xe162, 0x0512,
+    0x2112, 0x4d12, 0xe042, 0xca29, 0xf7f9, 0xe180, 0xce20, 0xd112,
+    0x0080, 0xd111, 0x0480, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe181,
+    0xe42e, 0xa200, 0x3c13, 0x3c16, 0xe0c1, 0x0067, 0xe0c0, 0x0069,
+    0xa80e, 0xe041, 0x3676, 0x3e75, 0x2878, 0xf05a, 0xe0c0, 0x0068,
+    0x3410, 0x3c11, 0x2010, 0x4c11, 0xe042, 0xe005, 0x0049, 0xe093,
+    0x9f01, 0xe004, 0xffff, 0x3c12, 0xe41e, 0x0b2d, 0xe41e, 0x0b99,
+    0xe41e, 0x0b4b, 0xa202, 0x3c16, 0xe41e, 0x0b4b, 0xa200, 0x3c16,
+    0xd037, 0x0080, 0xe128, 0xe42e, 0xa200, 0x3c13, 0xe0c0, 0x0060,
+    0x3410, 0x3c11, 0xe0c0, 0x0061, 0xae04, 0x3c12, 0xe41e, 0x0b2d,
+    0xe41e, 0x0b99, 0xd071, 0x802a, 0xe181, 0xe42e, 0xa200, 0x3c13,
+    0xe0c0, 0x0060, 0x3410, 0x3c11, 0xe0c0, 0x0061, 0xae04, 0x3c12,
+    0xe41e, 0x0b2d, 0xe41e, 0x0b99, 0xd071, 0x802a, 0xe181, 0xa200,
+    0x3c16, 0xe41e, 0x0b4b, 0xa202, 0x3c16, 0xe41e, 0x0b4b, 0xa200,
+    0x3c16, 0xd037, 0x0080, 0xe128, 0xe42e, 0xd030, 0x0000, 0xd034,
+    0x0000, 0xd033, 0x0000, 0xd035, 0x0000, 0xd036, 0x00ff, 0xd038,
+    0x0000, 0xe42e, 0xcb41, 0xf7f9, 0xd04c, 0x0001, 0xe41e, 0x0b4b,
+    0xd04c, 0x0000, 0xe004, 0x0080, 0x2a16, 0xb616, 0xcc6e, 0x2816,
+    0xe016, 0x3c16, 0xe470, 0xca28, 0xf7f8, 0x2869, 0xf08a, 0xa802,
+    0xe428, 0xe41e, 0x0c18, 0xa202, 0x3c69, 0xe42e, 0x2816, 0xf048,
+    0xd111, 0x0000, 0xf03e, 0xd111, 0x0080, 0xe082, 0x3c14, 0xe004,
+    0x0048, 0xe092, 0xd027, 0x0000, 0xe41e, 0x0ba3, 0xd027, 0x0001,
+    0x2872, 0xf2d8, 0x2010, 0x4c11, 0x2e13, 0xae11, 0xe042, 0xce20,
+    0xd112, 0x0080, 0xe0c0, 0x0043, 0xa806, 0xae02, 0xa022, 0xce26,
+    0x2c13, 0xe000, 0x0002, 0x3c13, 0x1c12, 0xf024, 0x3c13, 0x2010,
+    0x4c11, 0x2e13, 0xae11, 0xe042, 0x9f01, 0x2873, 0xe016, 0x446a,
+    0xf0ea, 0xa201, 0x2067, 0x4c8f, 0xe002, 0x0200, 0x3467, 0x3c8f,
+    0xb64d, 0x3e69, 0xf04b, 0xe000, 0x0200, 0x3c8f, 0x2814, 0xe092,
+    0xe42e, 0x2010, 0x4c11, 0x2e13, 0xae11, 0xe042, 0xe005, 0x0048,
+    0xe093, 0x9f01, 0xe42e, 0xe0c1, 0x0043, 0xa809, 0xe429, 0x2873,
+    0xe428, 0x2873, 0xe016, 0x446a, 0xe428, 0xa200, 0x3c15, 0x2010,
+    0x4c11, 0x2e13, 0xae11, 0xe042, 0x8111, 0x9e89, 0xe045, 0xf043,
+    0x2c12, 0xae10, 0xe041, 0xe003, 0x0200, 0xe423, 0xe0c0, 0x0045,
+    0xaf04, 0xa802, 0xf08a, 0xe001, 0x0200, 0x3667, 0x3e8f, 0xa202,
+    0x3c6a, 0xe42e, 0x2873, 0xf06a, 0x2874, 0xf048, 0xa202, 0x3c74,
+    0xe42e, 0xe0c0, 0x0059, 0xa102, 0xf068, 0xe0c0, 0x0045, 0x3072,
+    0x2872, 0xf128, 0x2815, 0xf548, 0xe0c0, 0x005c, 0xe008, 0x4000,
+    0xf4fa, 0xe0c0, 0x005d, 0xe00a, 0x4000, 0xe0c2, 0x005d, 0xa202,
+    0xce00, 0x3c15, 0xf45e, 0xe42e, 0xa806, 0xe42a, 0xa102, 0xf11a,
+    0xa102, 0xf1ba, 0xe084, 0xcc76, 0xcc78, 0xc87a, 0xe005, 0xffff,
+    0xae21, 0xe00b, 0xff00, 0xe052, 0xcc7a, 0x8112, 0xa202, 0xe42e,
+    0xe084, 0xcc76, 0xcc78, 0xc87a, 0xe005, 0xff00, 0xae21, 0xe052,
+    0xcc7a, 0x8112, 0xa206, 0xe42e, 0xe084, 0xcc76, 0xcc78, 0xc87a,
+    0xe005, 0xffff, 0xae21, 0xe052, 0xcc7a, 0x8112, 0xa204, 0xe42e,
+    0xe004, 0x0000, 0x2a16, 0xf039, 0xe000, 0x0200, 0x088f, 0xe049,
+    0xa807, 0x3e8f, 0xaf04, 0xb432, 0x3c68, 0xe008, 0x00ff, 0xcc78,
+    0xe005, 0x6964, 0xcc7b, 0xa002, 0xe008, 0x00ff, 0xcc78, 0xe004,
+    0x7831, 0xcc7a, 0xe42e, 0x2869, 0xa802, 0xe42a, 0xc867, 0x1a68,
+    0xa105, 0xe04a, 0xe000, 0x00fe, 0xf030, 0xe001, 0x0100, 0xa202,
+    0xb60a, 0xe429, 0xc869, 0xb636, 0xe42b, 0xa208, 0x188f, 0xaf07,
+    0xe046, 0xe049, 0xa200, 0xb62e, 0xe42e, 0xe0c0, 0x0048, 0xe002,
+    0x0400, 0xc867, 0xe009, 0x007f, 0xa107, 0xae05, 0xe042, 0xc869,
+    0xaf07, 0xe015, 0xa807, 0xe042, 0x2210, 0x4e11, 0xe045, 0xf047,
+    0x2e12, 0xae11, 0xe042, 0xe0c2, 0x0046, 0xe42e, 0x6858, 0xe42d,
+    0xe161, 0x03e0, 0xf088, 0xba4a, 0xa140, 0x3d11, 0xba4a, 0xa140,
+    0x3d11, 0xe42e, 0xe049, 0xa87e, 0xa140, 0x3d11, 0xaf0d, 0xa87f,
+    0xa141, 0x3f11, 0xe42e, 0xd1a5, 0x0000, 0xe161, 0x03e0, 0x2111,
+    0x4d11, 0xcf4c, 0xd1a0, 0x0001, 0xcb41, 0xf7f9, 0xe42e, 0xe0c0,
+    0x0065, 0xaf18, 0xa802, 0xe40a, 0x0d09, 0xae0a, 0xe0c1, 0x0060,
+    0xaf0d, 0xa80f, 0xe056, 0xe0c1, 0x0044, 0xa811, 0xe056, 0xae0c,
+    0xe0c1, 0x0044, 0xa80f, 0xe056, 0xe167, 0x0ba7, 0x2f17, 0xe056,
+    0xe0c2, 0x0282, 0xe0c0, 0x006e, 0xe0c2, 0x0284, 0xaf20, 0xe0c1,
+    0x0282, 0xa809, 0xf04b, 0xe049, 0xae1f, 0xf06e, 0xe049, 0xa011,
+    0xaf09, 0xae07, 0xae21, 0xe056, 0xe0c2, 0x028c, 0xe167, 0x0ba8,
+    0x2d17, 0x4917, 0xe0c2, 0x0285, 0xe167, 0x0baa, 0x2d17, 0x4917,
+    0xe0c2, 0x0286, 0xe41e, 0x0d0a, 0xe0c0, 0x004a, 0xe0c2, 0x0289,
+    0xe0c0, 0x004b, 0xe0c2, 0x028a, 0xe0c0, 0x0055, 0xe0c2, 0x028b,
+    0xe0c1, 0x0041, 0xe004, 0x0100, 0xae10, 0xe042, 0xe167, 0x0ba6,
+    0x2b17, 0xf05b, 0xe167, 0x0ba0, 0x2d17, 0x4917, 0xe0c2, 0x0287,
+    0xe0c1, 0x0041, 0xe004, 0x0118, 0xae10, 0xe042, 0xe167, 0x0ba6,
+    0x2b17, 0xf05b, 0xe167, 0x0ba2, 0x2d17, 0x4917, 0xe0c2, 0x0288,
+    0xe0c1, 0x0041, 0xe004, 0x0120, 0xae10, 0xe042, 0xe167, 0x0ba6,
+    0x2b17, 0xf05b, 0xe167, 0x0ba4, 0x2d17, 0x4917, 0xe0c2, 0x028d,
+    0xe0c0, 0x0065, 0xaf18, 0xa802, 0xe0c2, 0x0280, 0xa210, 0xe0c2,
+    0x0168, 0xe42e, 0xe167, 0x0bac, 0xe165, 0x028e, 0xe166, 0x02c0,
+    0xd022, 0x0008, 0xe184, 0x0d1d, 0x2d17, 0x9f16, 0x9e85, 0xf7fb,
+    0x2517, 0x4d17, 0x9f16, 0x9e85, 0xf7fb, 0xe190, 0xe166, 0x02d2,
+    0xd022, 0x0008, 0xe184, 0x0d29, 0x2517, 0x4d17, 0x9f16, 0x9e85,
+    0xf7fb, 0xe190, 0xe166, 0x02db, 0xd022, 0x0008, 0xe184, 0x0d35,
+    0x2517, 0x4d17, 0x9f16, 0x9e85, 0xf7fb, 0xe190, 0xe166, 0x02e4,
+    0xd022, 0x0008, 0xe184, 0x0d40, 0x2d17, 0x9f16, 0x9e85, 0xf7fb,
+    0xe190, 0xe42e, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
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+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
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+    0x007e, 0xe40e, 0x007e, 0xe40e, 0x03d5, 0xe40e, 0x03e8, 0xe41e,
+    0x0153, 0xe40e, 0x007e, 0xe41e, 0x01a9, 0xe40e, 0x007e, 0xe41e,
+    0x01aa, 0xe41e, 0x0a4b, 0xe40e, 0x007e, 0xe41e, 0x02bd, 0xe40e,
+    0x007e, 0xe41e, 0x04db, 0xe40e, 0x007e, 0xe41e, 0x0369, 0xe41e,
+    0x0a48, 0xe40e, 0x007e, 0xd130, 0x0004, 0xa200, 0xc401, 0xe188,
+    0x07ff, 0x3d11, 0xa200, 0x3c51, 0x3c52, 0x3c85, 0x3c89, 0x3c81,
+    0x3c93, 0x3c94, 0xe0c0, 0x0062, 0xaf02, 0x3054, 0xaf02, 0x3080,
+    0xaf02, 0x307f, 0x2880, 0xf0da, 0xe0c0, 0x0064, 0xa80e, 0xe049,
+    0xa809, 0xf03b, 0xba7f, 0xa806, 0xae06, 0xf03a, 0xe092, 0x9201,
+    0xe41e, 0x0ab4, 0xe41e, 0x0a2a, 0xe41e, 0x0a91, 0xa2fa, 0x3c45,
+    0xe41e, 0x07b2, 0xf23a, 0xe41e, 0x0ab4, 0xe41e, 0x0ae7, 0xe128,
+    0x2810, 0xf06a, 0xba7e, 0xa108, 0xba4f, 0xa102, 0xf7e0, 0x2016,
+    0x4c17, 0xe0c2, 0x0071, 0xe0c2, 0x004f, 0x2012, 0x4c13, 0xe0c2,
+    0x0072, 0x2856, 0xe0c2, 0x006c, 0xa208, 0xe0c2, 0x0073, 0xa202,
+    0xe0c2, 0x0074, 0xe0c2, 0x0070, 0xe42e, 0xa200, 0xe0c2, 0x0070,
+    0xe42e, 0xe42e, 0xa200, 0xcc4a, 0xcc4c, 0x3c50, 0x3cba, 0x3cbb,
+    0x3cbc, 0xa2fa, 0xe0c2, 0x0071, 0xa2fc, 0xe0c2, 0x0077, 0xa2fe,
+    0xe0c2, 0x0073, 0x3c44, 0x3c21, 0xa202, 0xe0c2, 0x0076, 0x288a,
+    0xf0fa, 0xa200, 0x3c7e, 0xe41e, 0x0b39, 0xa202, 0x3c7e, 0xe41e,
+    0x0b39, 0xa200, 0x3c7e, 0xd037, 0x0080, 0xa200, 0x3c8a, 0xa2fe,
+    0xe0c2, 0x0077, 0xe41e, 0x039b, 0xe41e, 0x03c9, 0xe40a, 0x028d,
+    0xa2fc, 0xe0c2, 0x0077, 0xd130, 0x0004, 0xd1e0, 0x0001, 0xd1e1,
+    0x03b0, 0xd03a, 0x0004, 0xd04b, 0x0001, 0xd04c, 0x0000, 0xd008,
+    0x0000, 0xd1f3, 0x0040, 0xd022, 0x00bf, 0xe184, 0x01f0, 0xa200,
+    0xcfe8, 0xe0c0, 0x0045, 0xaf04, 0xa802, 0x4480, 0xf20a, 0x2845,
+    0x3c90, 0xf0c4, 0x2a8c, 0xe045, 0xf039, 0xa200, 0xf07e, 0x2a8d,
+    0xe045, 0xf039, 0xa202, 0xf02e, 0xa204, 0x3c91, 0x2843, 0x3c45,
+    0xe0c2, 0x0071, 0xe41e, 0x02ec, 0x3c46, 0xa2ff, 0x3e43, 0xe40e,
+    0x028d, 0xa2fe, 0xe0c2, 0x0071, 0xe40e, 0x028d, 0x2880, 0xf08a,
+    0x2051, 0x4c52, 0xf03a, 0xe41e, 0x0b06, 0xe40e, 0x0259, 0x2880,
+    0xf398, 0xe41e, 0x0c35, 0xf36a, 0xa2fe, 0xe0c2, 0x0071, 0x2854,
+    0xf158, 0x2845, 0x3c90, 0xe404, 0x028d, 0x2a8c, 0xe045, 0xf039,
+    0xa200, 0xf07e, 0x2a8d, 0xe045, 0xf039, 0xa202, 0xf02e, 0xa204,
+    0x3c91, 0xe41e, 0x02ec, 0xe40e, 0x028d, 0x2845, 0x3c90, 0xe404,
+    0x028d, 0x2a8c, 0xe045, 0xf039, 0xa200, 0xf07e, 0x2a8d, 0xe045,
+    0xf039, 0xa202, 0xf02e, 0xa204, 0x3c91, 0xe41e, 0x02ec, 0x2843,
+    0x3c45, 0xe404, 0x028d, 0xe0c2, 0x0071, 0x3c46, 0xa2fa, 0x3c43,
+    0xf35e, 0xe41e, 0x04e2, 0x2880, 0xf26a, 0x28c0, 0xf24a, 0xa2fc,
+    0xe0c2, 0x0077, 0xa2fa, 0xe0c2, 0x0071, 0x2051, 0x4c52, 0xe0c2,
+    0x0070, 0xe41e, 0x03b2, 0x2821, 0xa104, 0xe01a, 0xae3c, 0x4c21,
+    0xe0c2, 0x0073, 0x2016, 0x4c17, 0xe0c2, 0x006f, 0xe0c2, 0x004f,
+    0xa200, 0xe0c2, 0x0072, 0xc84a, 0xc84d, 0xae20, 0xe056, 0xe0c2,
+    0x0053, 0xe42e, 0x2893, 0x4c94, 0xe418, 0x0ebd, 0x2a54, 0x2845,
+    0xf029, 0x2844, 0xe0c2, 0x0071, 0x3c46, 0xe41e, 0x03b2, 0x2821,
+    0xa104, 0xe01a, 0xae3c, 0x4c21, 0xe0c2, 0x0073, 0x2016, 0x4c17,
+    0xe0c2, 0x006f, 0xe0c2, 0x004f, 0x2850, 0xe0c2, 0x0072, 0x2844,
+    0xe0c2, 0x0077, 0x2051, 0x4c52, 0xa002, 0x3451, 0x3c52, 0xe0c2,
+    0x0070, 0xc84a, 0xc84d, 0xae20, 0xe056, 0xe0c2, 0x0053, 0xa2fb,
+    0x2891, 0xf0a4, 0xa102, 0xf032, 0x3e8c, 0xf06e, 0xa102, 0xf032,
+    0x3e8d, 0xf02e, 0x3e8e, 0xa202, 0xe42e, 0xd130, 0x0004, 0xe41e,
+    0x0c76, 0xe0c0, 0x0060, 0xe42a, 0xca28, 0xf7f8, 0xe0c0, 0x0042,
+    0xce20, 0xd111, 0x0100, 0xd112, 0x0060, 0xd113, 0x0003, 0xca28,
+    0xf7f8, 0xe0c0, 0x0042, 0xe000, 0x0180, 0xce20, 0xd111, 0x0160,
+    0xd112, 0x0004, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe004, 0x0160,
+    0xe09e, 0x2117, 0x4d17, 0x3440, 0x3c41, 0xe0c0, 0x0060, 0x3c53,
+    0xe0c0, 0x0061, 0x3c55, 0xe42e, 0x2891, 0xe424, 0xe0c0, 0x0060,
+    0xe049, 0xa861, 0xe42b, 0xe049, 0xa81e, 0x3c95, 0xaf0b, 0x3294,
+    0x2890, 0xae04, 0x0890, 0x0890, 0xe000, 0x0100, 0xe09e, 0x2117,
+    0x4d17, 0xe0c2, 0x0143, 0x2117, 0x4d17, 0xe0c2, 0x0144, 0x2117,
+    0x4d17, 0xe0c2, 0x0145, 0xa200, 0xe0c2, 0x0140, 0xe0c2, 0x0149,
+    0x2855, 0xe0c2, 0x0141, 0xe0c0, 0x0064, 0xe0c2, 0x014c, 0x2818,
+    0xa102, 0xae20, 0x4c19, 0xa102, 0xe0c2, 0x0142, 0x2894, 0xae08,
+    0x4c95, 0xe0c2, 0x014e, 0xe0c0, 0x0061, 0xe0c2, 0x0146, 0xe0c0,
+    0x0062, 0xe0c2, 0x0147, 0xe0c0, 0x0063, 0xe0c2, 0x0148, 0xa200,
+    0x3c96, 0x3c97, 0x3c98, 0x3c61, 0xe41e, 0x034b, 0x2861, 0xa002,
+    0x3c61, 0x2897, 0xa002, 0x3c97, 0x1818, 0xf068, 0x3c97, 0x2898,
+    0xa002, 0x3c98, 0x1819, 0xf718, 0xe41e, 0x034b, 0xe190, 0xe0c1,
+    0x014b, 0xf7e9, 0xe42e, 0xa203, 0x2861, 0xb615, 0x3e99, 0xa203,
+    0x2898, 0x1819, 0xb615, 0x3e9a, 0x2894, 0xf03a, 0xe41e, 0x0e84,
+    0xae02, 0x4c99, 0xae02, 0x4c9a, 0xae0e, 0x4c97, 0xae0e, 0x4c98,
+    0xe0c1, 0x014b, 0xf7e9, 0xe0c2, 0x014d, 0xa202, 0xe0c2, 0x014a,
+    0xe42e, 0xe0c0, 0x0060, 0xf08a, 0xe0c0, 0x0061, 0x2278, 0x4e79,
+    0xe046, 0xaf12, 0xae02, 0x3c7b, 0xa200, 0x3c85, 0xe180, 0xe41e,
+    0x0ae7, 0xe41e, 0x0b74, 0xe41e, 0x0a2a, 0xe41e, 0x0a91, 0xe166,
+    0x0071, 0x9e06, 0xf16a, 0x2853, 0xa102, 0xcc44, 0xa200, 0x3c9f,
+    0xe184, 0x0396, 0x9e06, 0x5c9f, 0xa802, 0xf07a, 0x289f, 0xe000,
+    0x0170, 0xe09e, 0xa204, 0x3d07, 0x289f, 0xa002, 0x3c9f, 0xe190,
+    0xa202, 0x3c8a, 0xe42e, 0xa200, 0x3c9f, 0x2853, 0xa102, 0xcc44,
+    0xe184, 0x03b0, 0xe0c0, 0x0054, 0x5c9f, 0xa802, 0xf058, 0x289f,
+    0xe41e, 0x0a39, 0xf04e, 0x289f, 0xe41e, 0x0a41, 0x2a9f, 0xa003,
+    0x3e9f, 0xe42e, 0xe004, 0x0170, 0xe09e, 0xe004, 0x0054, 0xe09c,
+    0x2853, 0xa102, 0xcc44, 0xa200, 0x3c9f, 0xe184, 0x03c6, 0x2b17,
+    0xaf03, 0xa803, 0x5a9f, 0xe056, 0x2a9f, 0xa003, 0x3e9f, 0x9f06,
+    0xe42e, 0xe161, 0x0170, 0x2853, 0xa102, 0xcc44, 0xe184, 0x03d3,
+    0x2911, 0xe016, 0xe428, 0xe190, 0xe42e, 0xe0c0, 0x005a, 0x3cee,
+    0xe41e, 0x0100, 0xa206, 0xe41e, 0x03f1, 0xe0c0, 0x005a, 0x3cee,
+    0xe41e, 0x0100, 0xa226, 0xe41e, 0x0407, 0xe41e, 0x041d, 0xe42e,
+    0xa224, 0xe41e, 0x0407, 0xe41e, 0x0438, 0xa204, 0xe41e, 0x03f1,
+    0xe42e, 0x3ced, 0xe0c0, 0x0041, 0xe005, 0x0280, 0xae11, 0xe042,
+    0x22f0, 0x4ef1, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0000,
+    0xd112, 0x0c00, 0x88ed, 0x0113, 0xca28, 0xf7f8, 0xe42e, 0x3ced,
+    0xe0c0, 0x0041, 0xe005, 0x0298, 0xae11, 0xe042, 0x22f0, 0x4ef1,
+    0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0000, 0xd112, 0x0100,
+    0x88ed, 0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe161, 0x07e0, 0x8911,
+    0x0034, 0x8911, 0x0033, 0x8911, 0x0035, 0x8911, 0x0036, 0x8911,
+    0x0037, 0x8911, 0x0038, 0x2111, 0x4d11, 0xcc60, 0x2111, 0x4d11,
+    0xcc62, 0x2111, 0x4d11, 0xcc64, 0x2111, 0x4d11, 0xcc72, 0xe42e,
+    0xe161, 0x07e0, 0x8b11, 0x0034, 0x8b11, 0x0033, 0x8b11, 0x0035,
+    0x8b11, 0x0036, 0x8b11, 0x0037, 0x8b11, 0x0038, 0xc860, 0x3511,
+    0x3d11, 0xc862, 0x3511, 0x3d11, 0xc864, 0x3511, 0x3d11, 0xc872,
+    0x3511, 0x3d11, 0xe42e, 0xe0c0, 0x0065, 0xaf0c, 0xa80e, 0xe42a,
+    0xca28, 0xf7f8, 0xe0c0, 0x006a, 0xce20, 0xd111, 0x05a0, 0xd112,
+    0x000c, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe160, 0x0003, 0xe161,
+    0x05a2, 0xe162, 0x0500, 0x2911, 0x3d12, 0x2931, 0x3d12, 0x2911,
+    0x3d12, 0x2931, 0x3d12, 0x2911, 0x3d12, 0x2931, 0x3d12, 0xe0c0,
+    0x0065, 0xaf10, 0xa802, 0xf19a, 0xe161, 0x05a0, 0xa202, 0xae10,
+    0x3d11, 0xa220, 0x3d11, 0xe162, 0x0500, 0x2112, 0x4d12, 0x3511,
+    0x3d11, 0xe0c0, 0x006a, 0xce20, 0xd111, 0x05a0, 0xd112, 0x0004,
+    0xd113, 0x0002, 0xca28, 0xf7f8, 0xe0c0, 0x0065, 0xaf0e, 0xa802,
+    0xf1da, 0xe161, 0x05a0, 0xa204, 0xae10, 0x3d11, 0x281a, 0x3d11,
+    0xe0c0, 0x0041, 0xe162, 0x0502, 0x2312, 0x4f12, 0xe042, 0x3511,
+    0x3d11, 0xe0c0, 0x006a, 0xa010, 0xce20, 0xd111, 0x05a0, 0xd112,
+    0x0004, 0xd113, 0x0002, 0xca28, 0xf7f8, 0x2821, 0x3cbd, 0xe0c0,
+    0x0065, 0xaf0c, 0xa802, 0xf1fa, 0xe161, 0x05a0, 0xa208, 0xae10,
+    0x2abd, 0xe056, 0x3d11, 0x281a, 0x3d11, 0xe0c0, 0x0041, 0xe162,
+    0x0504, 0x2312, 0x4f12, 0xe042, 0x3511, 0x3d11, 0xe0c0, 0x006a,
+    0xa020, 0xce20, 0xd111, 0x05a0, 0xd112, 0x0004, 0xd113, 0x0002,
+    0xca28, 0xf7f8, 0xe42e, 0xa200, 0x3c65, 0x3c85, 0x3c51, 0x3c52,
+    0x3c89, 0xe42e, 0xa200, 0x3ca0, 0x2810, 0xf058, 0xe41e, 0x084a,
+    0xe40e, 0x0520, 0xe41e, 0x080b, 0xe016, 0x3ca0, 0xe41e, 0x0453,
+    0x2880, 0xf1ea, 0xe0c0, 0x0065, 0xa808, 0xf06a, 0x2821, 0xf18a,
+    0xa202, 0x3cc0, 0xe42e, 0xe0c0, 0x0065, 0xaf06, 0xa806, 0xf10a,
+    0xa102, 0xf04a, 0xa102, 0xf05a, 0xf08e, 0x2821, 0xf068, 0xf08e,
+    0x2821, 0xa104, 0xf02a, 0xf04e, 0xa202, 0x3cc0, 0xe42e, 0xa200,
+    0x3cc0, 0x2821, 0xf062, 0x2051, 0x4c52, 0xa200, 0xb620, 0x3c21,
+    0xf03e, 0x3ca0, 0x3ca3, 0x28a3, 0xf04a, 0x2821, 0x3ca3, 0x3ca0,
+    0x2823, 0x3c25, 0x2821, 0xa104, 0xf05a, 0x2823, 0x3c24, 0x3c25,
+    0xf04e, 0x2824, 0x6423, 0x3c25, 0xe41e, 0x063c, 0x2845, 0x3c90,
+    0xf0c4, 0x2a8c, 0xe045, 0xf039, 0xa200, 0xf07e, 0x2a8d, 0xe045,
+    0xf039, 0xa202, 0xf02e, 0xa204, 0x3c91, 0xe41e, 0x0a9c, 0x2844,
+    0xf0d4, 0x2a8c, 0xf043, 0x3c8c, 0xa201, 0xf08e, 0x2a8d, 0xf043,
+    0x3c8d, 0xa203, 0xf03e, 0x3c8e, 0xa205, 0x3e92, 0xe41e, 0x0ca6,
+    0x2821, 0xae02, 0x4c11, 0xcf80, 0xcfc6, 0xd1d3, 0x000b, 0x2818,
+    0xa102, 0xae04, 0x4c21, 0xae02, 0x4c11, 0xcf00, 0x2826, 0xa200,
+    0xcf02, 0xd184, 0x0001, 0x2818, 0xae20, 0x4c19, 0xae08, 0xcfc4,
+    0x2040, 0x4c41, 0xcfca, 0x2835, 0xcfce, 0xd1e6, 0x0000, 0xa200,
+    0x3c61, 0x3c97, 0x3c98, 0x28a0, 0xf110, 0xe41e, 0x059a, 0x2aba,
+    0xe017, 0x3eba, 0xf0ba, 0x2861, 0x181a, 0xf132, 0xe41e, 0x0890,
+    0xf05a, 0x2860, 0x1861, 0xf7b4, 0xf71a, 0x2821, 0xf088, 0x2051,
+    0x4c52, 0xf05a, 0xa204, 0x4c11, 0xcf80, 0xcfc6, 0xe41e, 0x05bc,
+    0x2810, 0xe418, 0x0629, 0xd1e6, 0x0001, 0xe41e, 0x0da0, 0xcbe2,
+    0xf7f8, 0xe42e, 0xe41e, 0x05c9, 0x2861, 0x181a, 0xf162, 0xe41e,
+    0x0664, 0xf15d, 0x2897, 0xa002, 0x3c97, 0x1818, 0xf058, 0x3c97,
+    0x2898, 0xa002, 0x3c98, 0xcb86, 0xa102, 0xf6f0, 0x2861, 0x181a,
+    0xf042, 0xe41e, 0x05e3, 0xf698, 0xa202, 0xe42e, 0x28ba, 0xe016,
+    0x3cba, 0xe16a, 0xa200, 0xe42e, 0x2861, 0xe41a, 0x05c9, 0x2861,
+    0x181a, 0xf072, 0xe41e, 0x06b3, 0x2850, 0xa002, 0x3c50, 0xf78e,
+    0xe42e, 0x2822, 0xcf82, 0xd1c3, 0x0000, 0x2823, 0xcf96, 0xd188,
+    0x0001, 0x281c, 0xa102, 0x181d, 0xe016, 0x3c1e, 0x281d, 0xa002,
+    0x3c1d, 0xae02, 0xe000, 0x0200, 0xe092, 0x2111, 0x4d11, 0xae06,
+    0x341f, 0x3c20, 0xe42e, 0x2810, 0xf358, 0x2811, 0xf298, 0xba04,
+    0xa23b, 0xae21, 0xe428, 0xe00b, 0x1c10, 0xba2e, 0xe046, 0xf1da,
+    0xba30, 0xe046, 0xf19a, 0xba32, 0xe046, 0xf15a, 0xba34, 0xe046,
+    0xf11a, 0xba36, 0xe046, 0xf0da, 0xba38, 0xe046, 0xf09a, 0xba3a,
+    0xe046, 0xf05a, 0xba3c, 0xe046, 0xe428, 0xba40, 0xba40, 0xba40,
+    0xba40, 0xba40, 0xba40, 0xba40, 0xba6e, 0xa200, 0xe42e, 0xba1e,
+    0xba2f, 0xe428, 0xb636, 0xe428, 0xba5e, 0xba40, 0xf7fa, 0xa200,
+    0xe42e, 0x281e, 0xe428, 0xc872, 0x101f, 0x1c20, 0xa00e, 0xe424,
+    0xa10e, 0xe012, 0x3c63, 0xb60c, 0xe42a, 0x7863, 0xe428, 0x7463,
+    0xe42e, 0xe41e, 0x08dd, 0x281a, 0xae10, 0x1014, 0x1c15, 0xf0c4,
+    0xc872, 0xaf06, 0x1014, 0x1c15, 0xe012, 0xf064, 0xe426, 0xba4f,
+    0xa102, 0xf7e0, 0xe42e, 0xe42e, 0x2821, 0xa104, 0xf09a, 0x2830,
+    0x1831, 0xf022, 0x0834, 0x3c32, 0x2830, 0x3c31, 0xe42e, 0x2831,
+    0x1830, 0xf022, 0x0834, 0x3c33, 0x2832, 0x1833, 0xa400, 0x3c33,
+    0x2833, 0xae1c, 0xc70f, 0x7c32, 0x3c35, 0x2832, 0x1833, 0xae1c,
+    0xc70f, 0x7c32, 0x3c36, 0xe005, 0x3fff, 0x2835, 0xe066, 0x3c35,
+    0x2836, 0xe066, 0x3c36, 0xe42e, 0x2861, 0xe0c2, 0x003f, 0xd184,
+    0x0002, 0xd185, 0x0000, 0xe190, 0xd1d0, 0x003f, 0xcba0, 0xa810,
+    0xcba3, 0xf389, 0xf7c8, 0xe41e, 0x0dac, 0xcbe0, 0xf7f8, 0x2862,
+    0xe41a, 0x0dc2, 0xe41e, 0x0dc6, 0xcba0, 0xcba3, 0xf2b9, 0xf7d8,
+    0xd185, 0x0001, 0xd184, 0x0004, 0xa200, 0xe41e, 0x0703, 0xe41e,
+    0x073d, 0xe41e, 0x0dd3, 0xe41e, 0x0e36, 0x2893, 0x4c94, 0xf17a,
+    0x2890, 0xf154, 0xe0c0, 0x014b, 0xf7e8, 0x2894, 0xe418, 0x0e84,
+    0x3c9d, 0x2a61, 0xae04, 0xa902, 0xb442, 0xae0e, 0x4c97, 0xae0e,
+    0x0898, 0xe0c2, 0x014d, 0xa202, 0xe0c2, 0x014a, 0xcb06, 0x3c61,
+    0xe42e, 0xd1d0, 0x0000, 0xd1d1, 0x0000, 0xcb0c, 0xf7f8, 0xcbe0,
+    0xf7f8, 0xe16b, 0xe42e, 0x2861, 0xe0c2, 0x003f, 0xd184, 0x0002,
+    0xd185, 0x0000, 0x8823, 0x01ca, 0xd1c4, 0x0000, 0xd1c2, 0x0001,
+    0xd1c5, 0x0000, 0xd1d0, 0x000e, 0xcba0, 0xf7f8, 0x2051, 0x4c52,
+    0xf058, 0xd1c2, 0x0000, 0xd1c5, 0x0003, 0xd1d0, 0x0030, 0xe41e,
+    0x0dac, 0xa200, 0xe0c2, 0x012a, 0xcbe0, 0xf7f8, 0x2862, 0xe41a,
+    0x0dc2, 0xe41e, 0x0dc6, 0xcba0, 0xf7f8, 0xd185, 0x0001, 0xd184,
+    0x0004, 0xa202, 0xe41e, 0x0703, 0xe41e, 0x073d, 0xe41e, 0x0dd3,
+    0xe41e, 0x0e36, 0x2893, 0x4c94, 0xf14a, 0xe0c0, 0x014b, 0xf7e8,
+    0x2894, 0xe418, 0x0e84, 0x2a61, 0xae04, 0xa902, 0xb442, 0xae0e,
+    0x4c97, 0xae0e, 0x0898, 0xe0c2, 0x014d, 0xa202, 0xe0c2, 0x014a,
+    0xcb06, 0x3c61, 0xe42e, 0xe0c1, 0x0065, 0xaf0f, 0xa803, 0xe42b,
+    0xa802, 0xae0e, 0x2aba, 0xa803, 0xae0d, 0xe055, 0xcb94, 0xa83e,
+    0xe056, 0x2abb, 0xa83f, 0xaf03, 0xe001, 0x0510, 0xe093, 0x2abb,
+    0xa803, 0xf05b, 0x2b01, 0xe056, 0x3d01, 0xf03e, 0xae10, 0x3d01,
+    0x28bb, 0xa002, 0x3cbb, 0xa83e, 0xf04a, 0x28bb, 0x181a, 0xe428,
+    0xca28, 0xf7f8, 0xe166, 0x0502, 0x2116, 0x4d16, 0x2abb, 0xa103,
+    0xaf0b, 0xae0b, 0xe042, 0xce20, 0xd111, 0x0510, 0xd112, 0x0010,
+    0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0065, 0xaf0c,
+    0xa802, 0xe42a, 0x28bd, 0xe42a, 0xca28, 0xf7f8, 0x28bd, 0xa102,
+    0xf1b8, 0xa201, 0xcb8a, 0xa802, 0xf068, 0xa202, 0xae3e, 0xe0c1,
+    0x03b0, 0xe055, 0x28bc, 0xa87e, 0xae02, 0xe000, 0x0520, 0xe092,
+    0x3711, 0x3f11, 0x28bc, 0xa002, 0x3cbc, 0x181a, 0xf392, 0x28bc,
+    0xa87e, 0xf36a, 0xe42e, 0xa201, 0xcb8a, 0xa802, 0xf0da, 0x28bc,
+    0xa83e, 0xae04, 0xe000, 0x0520, 0xe092, 0xa201, 0x3f11, 0x3f11,
+    0x3f11, 0x3f11, 0xf1ce, 0xcb88, 0xa112, 0xf06a, 0xa202, 0xae3e,
+    0xe0c1, 0x03b0, 0xe055, 0x28bc, 0xa83e, 0xae04, 0xe000, 0x0520,
+    0xe092, 0x3711, 0x3f11, 0xcb88, 0xa112, 0xb609, 0xf064, 0xa202,
+    0xae3e, 0xe0c1, 0x03c0, 0xe055, 0x3711, 0x3f11, 0x28bc, 0xa002,
+    0x3cbc, 0x181a, 0xf052, 0x28bc, 0xa83e, 0xf02a, 0xe42e, 0xe166,
+    0x0504, 0x2116, 0x4d16, 0x2abd, 0xa103, 0xf069, 0x2abc, 0xa103,
+    0xaf0d, 0xae11, 0xf05e, 0x2abc, 0xa103, 0xaf0b, 0xae11, 0xe042,
+    0xce20, 0xd111, 0x0520, 0xd112, 0x0080, 0xd113, 0x0002, 0xca28,
+    0xf7f8, 0xe42e, 0xa200, 0x3c10, 0x3c11, 0x3c00, 0x3c01, 0x3ca3,
+    0x3c16, 0x3c17, 0xe41e, 0x08dd, 0xe004, 0x5555, 0x3c03, 0xe005,
+    0x5649, 0xae21, 0xe00b, 0x444f, 0x288b, 0xe408, 0x0808, 0xba3e,
+    0xe046, 0xf11a, 0xe042, 0x1403, 0x1803, 0xf28a, 0xba2e, 0xa102,
+    0xf29a, 0xba4e, 0x3c02, 0x2000, 0x4c01, 0xae10, 0x4c02, 0x3400,
+    0x3c01, 0xf6be, 0xba7e, 0xa202, 0x3c10, 0xe004, 0x2000, 0x3c34,
+    0xe41e, 0x08e2, 0xe41e, 0x0c5d, 0xf24a, 0xe41e, 0x080b, 0xf21a,
+    0x2816, 0x3ca1, 0x2817, 0x3ca2, 0x2816, 0xa01e, 0xaf08, 0x3c18,
+    0x2817, 0xa01e, 0xaf08, 0x3c19, 0xe42e, 0xba7e, 0xa200, 0x3c11,
+    0xf04e, 0xba6e, 0xa202, 0x3c11, 0xa200, 0x3c12, 0xa21e, 0x3c13,
+    0xe004, 0x0100, 0x3c34, 0xe41e, 0x0947, 0xf03a, 0xa202, 0xe42e,
+    0xe16a, 0xa200, 0xe42e, 0xe41e, 0x08dd, 0xa209, 0xba7e, 0xe045,
+    0xf055, 0xa208, 0x3414, 0x3c15, 0xf32e, 0x3414, 0x3c15, 0xba7e,
+    0xe190, 0xba5e, 0xe190, 0xba5e, 0xe190, 0xba7e, 0xe190, 0xba7e,
+    0xf266, 0xe002, 0x0100, 0xf230, 0xe000, 0x0100, 0x3c1c, 0xe161,
+    0x0200, 0x281c, 0xa102, 0xcc44, 0xe184, 0x083b, 0xba7e, 0xe190,
+    0xe016, 0xf02a, 0x3ca0, 0xba7e, 0x2214, 0x4e15, 0xe045, 0xf031,
+    0xa203, 0x3ea0, 0x3511, 0x3d11, 0xd039, 0x0000, 0xa200, 0x3c1d,
+    0x28a0, 0xf058, 0xe41e, 0x0862, 0xf02a, 0xe42e, 0xd039, 0x0000,
+    0xa200, 0xe42e, 0xe41e, 0x08dd, 0x2811, 0xf0e8, 0xba1e, 0xe002,
+    0x5555, 0xf03a, 0xba4e, 0xf7be, 0xba5e, 0xba1e, 0xe002, 0x5555,
+    0xf768, 0xba5e, 0xf02e, 0xba6e, 0xe41e, 0x0947, 0xe42e, 0xe16a,
+    0xa200, 0xe42e, 0xba40, 0xf2b8, 0x7411, 0xf298, 0x7411, 0xf278,
+    0xba42, 0xa102, 0xb608, 0x3c21, 0x7411, 0xba48, 0x3c23, 0xa13e,
+    0xf1ea, 0x2811, 0xe016, 0xf06a, 0xba40, 0xf198, 0xba40, 0xf178,
+    0xba42, 0x3c22, 0xba40, 0x3c26, 0xba58, 0x3c30, 0xe41e, 0x09c7,
+    0x2805, 0x3c16, 0x2806, 0x3c17, 0xe41e, 0x0999, 0x741b, 0x3c60,
+    0xf068, 0x181a, 0xf040, 0x7411, 0xa202, 0xe42e, 0xa200, 0xe42e,
+    0x2810, 0xf1c8, 0xba40, 0xe40a, 0x08db, 0x741b, 0x3c60, 0x181a,
+    0xe402, 0x08db, 0x281b, 0xa116, 0xf036, 0xba40, 0xf3da, 0xba48,
+    0x3c23, 0xa13e, 0xf39a, 0x2811, 0xe016, 0xf02a, 0xba42, 0x3c22,
+    0xba40, 0xf32a, 0xba42, 0xa202, 0xe42e, 0xba40, 0xf2d8, 0x7411,
+    0xf2b8, 0x7411, 0xf298, 0xba42, 0xa102, 0xb608, 0x1821, 0xf248,
+    0x7411, 0xba48, 0x3c23, 0xa13e, 0xf1fa, 0x2811, 0xe016, 0xf06a,
+    0xba40, 0xf1a8, 0xba40, 0xf188, 0xba42, 0x3c22, 0xba40, 0x1826,
+    0xf138, 0xba58, 0x1830, 0xf108, 0xe41e, 0x09c7, 0x2805, 0x1816,
+    0xf0b8, 0x2806, 0x1817, 0xf088, 0x741b, 0x3c60, 0x181a, 0xf042,
+    0x7411, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xc868, 0xa80e, 0x3c64,
+    0x7464, 0xe42e, 0xba1e, 0xe002, 0x5256, 0xe016, 0xe42a, 0xba5e,
+    0xba1e, 0xe002, 0x3430, 0xf07a, 0xba1e, 0xe002, 0x3330, 0xe016,
+    0xe42a, 0xa202, 0x3c11, 0xba5e, 0xba5e, 0x3c28, 0x3c16, 0xba5e,
+    0x3c29, 0x3c17, 0xe41e, 0x0999, 0xba5e, 0xba5e, 0xba5e, 0xba4e,
+    0xba5e, 0x3c13, 0xba4e, 0xe004, 0x00ff, 0x3c12, 0xba7e, 0xe190,
+    0xba7e, 0xaf18, 0xa81e, 0xa10a, 0xa203, 0xae21, 0xa913, 0xf026,
+    0xa003, 0xe0c3, 0x007b, 0x2811, 0xf098, 0x2000, 0x4c01, 0xa144,
+    0xf2b6, 0xba4f, 0xa102, 0xf28a, 0xf7de, 0xa203, 0xae21, 0xa911,
+    0xe0c3, 0x007b, 0xa200, 0x3c27, 0xe161, 0x01d0, 0x2816, 0x3d11,
+    0x2817, 0x3d11, 0x2000, 0x4c01, 0xa144, 0xf166, 0xba4f, 0xae05,
+    0x3f11, 0xba4f, 0xae05, 0x3f11, 0x2a27, 0xa003, 0x3e27, 0xa111,
+    0xf0d3, 0xa104, 0xf740, 0x2827, 0xa002, 0x3c27, 0x2827, 0xa002,
+    0xaf02, 0xa506, 0x3c27, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xe0c8,
+    0xfffe, 0xe40d, 0x0989, 0xe002, 0x7fff, 0x3c04, 0x2804, 0xa802,
+    0xf398, 0xe004, 0x00b0, 0x3c16, 0xe004, 0x0090, 0x3c17, 0x2804,
+    0xaf02, 0xa802, 0xf03a, 0xa200, 0x3c16, 0x2804, 0xaf04, 0xa83e,
+    0x3c23, 0x2804, 0xaf0e, 0xe008, 0x00ff, 0x3c30, 0xd20c, 0xf22d,
+    0xf0aa, 0xa104, 0xf05a, 0xa102, 0xf09a, 0xe40e, 0x0989, 0xa200,
+    0x3c21, 0xf06e, 0xa202, 0x3c21, 0xf03e, 0xa204, 0x3c21, 0x2816,
+    0xe41a, 0x098c, 0x2816, 0x3ca1, 0x2817, 0x3ca2, 0xe41e, 0x0999,
+    0xa200, 0x3c60, 0x2811, 0xe016, 0xf02a, 0xba42, 0x3c22, 0xa202,
+    0xe42e, 0xe16a, 0xa200, 0xe42e, 0xba46, 0x3c56, 0xba50, 0xa002,
+    0xae04, 0x3c16, 0xba40, 0xe42a, 0xba50, 0xae04, 0x3c17, 0xa202,
+    0xe42e, 0x2816, 0xa01e, 0xaf08, 0x3c18, 0x2817, 0xa01e, 0xaf08,
+    0x3c19, 0x8418, 0x8219, 0xe018, 0x3c1a, 0xf0de, 0x2816, 0xa01e,
+    0xaf08, 0x3ca4, 0x2817, 0xa01e, 0xaf08, 0x3ca5, 0x84a4, 0x82a5,
+    0xe018, 0x3ca6, 0xa160, 0xa20d, 0xf116, 0xa166, 0xf0e6, 0xe002,
+    0x0129, 0xf0a6, 0xe002, 0x04a4, 0xf066, 0xe002, 0x1290, 0xf026,
+    0xa003, 0xa005, 0xa005, 0xa005, 0xa003, 0x3e1b, 0xe42e, 0x2811,
+    0xf0da, 0x2827, 0xf0fa, 0x7427, 0xae02, 0xe000, 0x01d0, 0xe092,
+    0x2911, 0x3c05, 0x2911, 0x3c06, 0xe42e, 0x2821, 0xf08a, 0xba40,
+    0xf06a, 0x2816, 0x3c05, 0x2817, 0x3c06, 0xe42e, 0xe005, 0x00a0,
+    0xba44, 0xf1ca, 0xa102, 0xf19a, 0xa102, 0xf16a, 0xa102, 0xf13a,
+    0xa102, 0xf10a, 0xa102, 0xf0ca, 0xa102, 0xf09a, 0xa201, 0xba4e,
+    0xe041, 0xe002, 0x00ff, 0xf7ca, 0xae05, 0xf08e, 0xa081, 0xe001,
+    0x0120, 0xa041, 0xa0a1, 0xa081, 0xa021, 0x3e05, 0xe005, 0x0078,
+    0xba44, 0xf27a, 0xa102, 0xf24a, 0xa102, 0xf21a, 0xa102, 0xf1ea,
+    0xa102, 0xf1ba, 0xa102, 0xf17a, 0xa102, 0xba41, 0xf088, 0xf049,
+    0xe005, 0x00b4, 0xf16e, 0xe005, 0x0168, 0xf13e, 0xf049, 0xe005,
+    0x0240, 0xf0fe, 0xa201, 0xba4e, 0xe041, 0xe002, 0x00ff, 0xf7ca,
+    0xae05, 0xf07e, 0xe001, 0x00c0, 0xa061, 0xa0c1, 0xa019, 0xa019,
+    0x3e06, 0xe42e, 0xe167, 0x0170, 0xa200, 0xc70f, 0x3d17, 0xa200,
+    0x3c47, 0xe42e, 0xe000, 0x0170, 0xe09e, 0x2907, 0xa804, 0x3d07,
+    0xe42e, 0xe424, 0xe000, 0x0170, 0xe09e, 0x2907, 0xa802, 0x3d07,
+    0xe42e, 0xe000, 0x0170, 0xe09e, 0x2907, 0xa904, 0x3d07, 0xe42e,
+    0xe41e, 0x0a2a, 0xe42e, 0xe0c1, 0x0065, 0xaf11, 0xa803, 0xe42b,
+    0xe167, 0x0170, 0xe166, 0x05a0, 0xd022, 0x0007, 0xe184, 0x0a5f,
+    0x2917, 0xae08, 0x4d17, 0xae08, 0x4d17, 0xae08, 0x4d17, 0x3d16,
+    0xe190, 0xca28, 0xf7f8, 0xe166, 0x0500, 0x2116, 0x4d16, 0xce20,
+    0xd111, 0x05a0, 0xd112, 0x0008, 0xd113, 0x0002, 0xca28, 0xf7f8,
+    0xe42e, 0x2847, 0x3c00, 0x2800, 0xe000, 0x0170, 0xe09e, 0x2907,
+    0xf0ea, 0x2800, 0xa002, 0x3c00, 0x1853, 0xf028, 0x3c00, 0x2800,
+    0x1847, 0xf728, 0xa200, 0x3c47, 0xa2fe, 0xe42e, 0xa206, 0x3d07,
+    0x2800, 0xa002, 0x3c47, 0x1853, 0xf038, 0xa200, 0x3c47, 0x2800,
+    0xe42e, 0xa2fa, 0x3c42, 0x3c43, 0x3c46, 0x3c90, 0x3c91, 0x3c92,
+    0x3c8c, 0x3c8d, 0x3c8e, 0xe42e, 0xe41e, 0x0a71, 0x3c44, 0x2821,
+    0xa104, 0xf0ea, 0x2844, 0x2a54, 0xf02b, 0x2843, 0x3c45, 0x2842,
+    0xe412, 0x0a32, 0x2843, 0x3c42, 0x2844, 0x3c43, 0xe42e, 0x2844,
+    0x3c45, 0xe41e, 0x0a32, 0xe42e, 0xa200, 0x3c7b, 0xe0c0, 0x0062,
+    0xaf0c, 0xa802, 0xf10a, 0xe0c1, 0x0048, 0xe0c0, 0x0060, 0xe045,
+    0xaf13, 0xae03, 0xa109, 0x3e7b, 0xf063, 0xe0c0, 0x0061, 0xae04,
+    0xe042, 0x3c7b, 0xe0c0, 0x0060, 0x3478, 0x3c79, 0xe0c0, 0x0061,
+    0xae04, 0x3c7a, 0xe41e, 0x0ae7, 0xe41e, 0x0b74, 0xd071, 0x802a,
+    0xe181, 0xa200, 0x3c7e, 0xe41e, 0x0b39, 0xa202, 0x3c7e, 0xe41e,
+    0x0b39, 0xa200, 0x3c7e, 0xd037, 0x0080, 0xe128, 0xe42e, 0xd030,
+    0x0000, 0xd034, 0x0000, 0xd033, 0x0000, 0xd035, 0x0000, 0xd036,
+    0x00ff, 0xd038, 0x0000, 0xe42e, 0xe41e, 0x0b39, 0x287e, 0xf088,
+    0xa202, 0x3c7e, 0xd037, 0x0000, 0xd04c, 0x0000, 0xe470, 0xa200,
+    0x3c7e, 0xd037, 0x0080, 0xd04c, 0x0000, 0xe470, 0xa200, 0x3c81,
+    0x3c7b, 0xe0c1, 0x0067, 0x287f, 0xf05a, 0xe0c0, 0x0068, 0x3478,
+    0x3c79, 0x2078, 0x4c79, 0xe042, 0xe005, 0x0049, 0xe093, 0x9f01,
+    0xe004, 0xffff, 0x3c7a, 0xe41e, 0x0ae7, 0xe41e, 0x0b74, 0xa200,
+    0x3c7e, 0xe41e, 0x0b39, 0xa202, 0x3c7e, 0xe41e, 0x0b39, 0xa200,
+    0x3c7e, 0xd037, 0x0080, 0xe128, 0xe0c0, 0x0069, 0xa80e, 0xe049,
+    0xa809, 0xf03b, 0xba7f, 0xa806, 0xae06, 0xf03a, 0xe092, 0x9201,
+    0xe42e, 0xca28, 0xf7f8, 0x287e, 0xf048, 0xd111, 0x0000, 0xf03e,
+    0xd111, 0x0080, 0xe082, 0x3c7c, 0xe004, 0x0048, 0xe092, 0xd027,
+    0x0000, 0xe41e, 0x0b7e, 0xd027, 0x0001, 0x288b, 0xf238, 0x2078,
+    0x4c79, 0x2e7b, 0xae11, 0xe042, 0xce20, 0x9f01, 0xd112, 0x0080,
+    0xe0c0, 0x0043, 0xa806, 0xae02, 0xa022, 0xce26, 0x2880, 0xf058,
+    0x2889, 0xf038, 0xe41e, 0x0bc8, 0x2c7b, 0xe000, 0x0002, 0x3c7b,
+    0x1c7a, 0xf024, 0x3c7b, 0x2078, 0x4c79, 0x2e7b, 0xae11, 0xe042,
+    0x9f01, 0x287c, 0xe092, 0xe42e, 0x2078, 0x4c79, 0x2e7b, 0xae11,
+    0xe042, 0xe005, 0x0048, 0xe093, 0x9f01, 0xe42e, 0xe0c1, 0x0043,
+    0xa809, 0xe429, 0xa200, 0x3c7d, 0x2880, 0xf038, 0x2885, 0xf228,
+    0xe0c0, 0x0045, 0xaf04, 0xe0c1, 0x0059, 0xa107, 0xb612, 0x3065,
+    0x2078, 0x4c79, 0x2e7b, 0xae11, 0xe042, 0x8111, 0x9e89, 0xe045,
+    0xf043, 0x2c7a, 0xae10, 0xe041, 0xe003, 0x0200, 0xe423, 0x2880,
+    0xf03a, 0x2881, 0xe42e, 0x2880, 0xf088, 0x2865, 0xa802, 0xf05a,
+    0x2885, 0xa002, 0x3c85, 0xe42e, 0xe0c0, 0x0059, 0xa102, 0xf068,
+    0xe0c0, 0x0045, 0x308b, 0x288b, 0xf138, 0x287d, 0xf528, 0xe0c0,
+    0x005c, 0xe008, 0x4000, 0xf4da, 0xe0c0, 0x005d, 0xe00a, 0x4000,
+    0xe0c2, 0x005d, 0xa202, 0xce00, 0x3c7d, 0xe40e, 0x0b88, 0xe42e,
+    0x2885, 0xe42a, 0xa102, 0xe40a, 0x0c06, 0xa102, 0xf288, 0x8111,
+    0x9e09, 0x2278, 0x4e79, 0xe046, 0xe008, 0x03ff, 0x3c88, 0xe008,
+    0x01ff, 0x3c86, 0x2888, 0xaf04, 0xe001, 0x0000, 0xe042, 0xe094,
+    0x2886, 0xe005, 0x0200, 0xe045, 0xa109, 0xf0e3, 0xe41e, 0x0c09,
+    0xe005, 0x0200, 0x1a86, 0xe045, 0xe084, 0xcc78, 0xa200, 0xf17b,
+    0xcc7a, 0xa109, 0xf7de, 0xe41e, 0x0c09, 0xf01e, 0xe084, 0xcc78,
+    0xe004, 0x5555, 0xae20, 0xe005, 0x5555, 0xe056, 0x2811, 0xf03a,
+    0xe004, 0x0100, 0xcc7a, 0xa202, 0x3c89, 0xe42e, 0xa200, 0x3c89,
+    0xe42e, 0xa806, 0xe42a, 0xa102, 0xf11a, 0xa102, 0xf1ba, 0xe084,
+    0xcc76, 0xcc78, 0xc87a, 0xe005, 0xffff, 0xae21, 0xe00b, 0xff00,
+    0xe052, 0xcc7a, 0x8112, 0xa202, 0xe42e, 0xe084, 0xcc76, 0xcc78,
+    0xc87a, 0xe005, 0xff00, 0xae21, 0xe052, 0xcc7a, 0x8112, 0xa206,
+    0xe42e, 0xe084, 0xcc76, 0xcc78, 0xc87a, 0xe005, 0xffff, 0xae21,
+    0xe052, 0xcc7a, 0x8112, 0xa204, 0xe42e, 0x2885, 0xa104, 0xf032,
+    0xa200, 0xe42e, 0xf0b0, 0xc866, 0x2a85, 0xaf0e, 0x2a88, 0xaf13,
+    0xe05a, 0xf04a, 0xa200, 0xf00e, 0xe42e, 0xa241, 0xc868, 0xe045,
+    0xa00f, 0xaf07, 0xc866, 0xae04, 0xa118, 0xe042, 0x2a85, 0xa105,
+    0xf07b, 0x2a88, 0xaf13, 0xf02b, 0xa205, 0xae13, 0xe042, 0xa008,
+    0x2a88, 0xe045, 0xa200, 0xb62e, 0xe42e, 0xe0c0, 0x0048, 0xe002,
+    0x0400, 0xc867, 0xe009, 0x007f, 0xa107, 0xae05, 0xe042, 0xc869,
+    0xaf07, 0xe015, 0xa807, 0xe042, 0x2278, 0x4e79, 0xe045, 0xf047,
+    0x2e7a, 0xae11, 0xe042, 0xe0c2, 0x0046, 0xe42e, 0xe0c0, 0x0064,
+    0x3cb1, 0x34b0, 0xe0c0, 0x0065, 0x3cb3, 0x34b2, 0xe0c0, 0x0066,
+    0x3cb5, 0x34b4, 0xe0c0, 0x0067, 0x3cb7, 0x34b6, 0xe0c0, 0x0068,
+    0x3cb9, 0x34b8, 0xe0c0, 0x0069, 0xe167, 0x0ba0, 0x3d17, 0x3517,
+    0xe0c0, 0x006a, 0x3d17, 0x3517, 0xe0c0, 0x006b, 0x3d17, 0x3517,
+    0xe0c0, 0x0042, 0xe000, 0x1000, 0xce20, 0xd111, 0x0ba8, 0xd112,
+    0x004c, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e, 0xa200, 0xcc8e,
+    0xe0c0, 0x0060, 0xaf08, 0x3093, 0xaf02, 0x3094, 0xe0c0, 0x0060,
+    0xa81e, 0x2a94, 0xae09, 0xe056, 0xe0c2, 0x014e, 0x2855, 0x2a93,
+    0x4e94, 0xf2cb, 0xe0c2, 0x0141, 0xe0c0, 0x0064, 0xe0c2, 0x014c,
+    0x2818, 0xa102, 0xae20, 0x4c19, 0xa102, 0xe0c2, 0x0142, 0x8490,
+    0xc786, 0xe018, 0xe000, 0x0100, 0xe09e, 0x2117, 0x4d17, 0xe0c2,
+    0x0143, 0x2117, 0x4d17, 0xe0c2, 0x0144, 0x2117, 0x4d17, 0xe0c2,
+    0x0145, 0xe0c0, 0x0061, 0xe0c2, 0x0146, 0xe0c0, 0x0062, 0xe0c2,
+    0x0147, 0xe0c0, 0x0063, 0xe0c2, 0x0148, 0x2811, 0xae08, 0xa908,
+    0xe0c2, 0x0100, 0xe004, 0x00ce, 0xe0c2, 0x017c, 0xe004, 0x000c,
+    0xe0c2, 0x017d, 0xa208, 0xae04, 0x4c11, 0xae04, 0x4c21, 0xae06,
+    0xe0c1, 0x0065, 0xaf19, 0xa803, 0xae17, 0xe056, 0xe0c2, 0x0204,
+    0xa200, 0xe0c2, 0x0208, 0x2821, 0xae06, 0xe0c2, 0x0104, 0xe0c0,
+    0x0050, 0x3000, 0xaf02, 0x3001, 0xaf02, 0x3002, 0xaf02, 0x3003,
+    0xaf0a, 0x3004, 0xaf02, 0x3005, 0xaf02, 0x3006, 0xaf02, 0x3007,
+    0xe0c0, 0x0050, 0xaf1c, 0xa802, 0xe005, 0x0ba6, 0xe09f, 0x3d17,
+    0x2804, 0x4400, 0x3c00, 0x2805, 0x4401, 0x3c01, 0x2806, 0x4402,
+    0x3c02, 0x2807, 0x4403, 0x3c03, 0xa200, 0x2a00, 0xf03b, 0xe00a,
+    0x0002, 0x2a01, 0xf03b, 0xe00a, 0x0009, 0x2a02, 0xf03b, 0xe00a,
+    0x0020, 0x2a03, 0xf03b, 0xe00a, 0x0040, 0xe005, 0x0ba6, 0xe09f,
+    0x2b17, 0xae05, 0xe056, 0xe0c2, 0x0169, 0xe0c1, 0x0041, 0xe004,
+    0x0000, 0xae10, 0xe042, 0x2a04, 0xf03b, 0x20b0, 0x4cb1, 0xcfc8,
+    0xe0c1, 0x0041, 0xe004, 0x0040, 0xae10, 0xe042, 0x2a05, 0xf03b,
+    0x20b2, 0x4cb3, 0xe0c2, 0x0103, 0x2826, 0xe016, 0xe0c2, 0x0210,
+    0xe0c1, 0x0041, 0xe004, 0x0070, 0xae10, 0xe042, 0x2a06, 0xf03b,
+    0x20b4, 0x4cb5, 0xe0c2, 0x0211, 0xe000, 0x4000, 0x2a07, 0xf03b,
+    0x20b6, 0x4cb7, 0xe0c2, 0x0212, 0x2818, 0xae20, 0x4c19, 0xae08,
+    0xe0c2, 0x0101, 0xe0c2, 0x0283, 0xe0c0, 0x0044, 0xa80e, 0xae1a,
+    0x4c55, 0xe0c2, 0x0102, 0xa200, 0xae0a, 0x4c25, 0xe0c2, 0x0217,
+    0xe41e, 0x0dda, 0xe41e, 0x0df4, 0xe41e, 0x0e2c, 0xa200, 0xe0c2,
+    0x030d, 0x2036, 0x4c35, 0xe0c2, 0x0310, 0xa202, 0xe0c2, 0x0106,
+    0x2a11, 0xae19, 0xe167, 0x0ba7, 0x3f17, 0xe41e, 0x0ed2, 0xe42e,
+    0xe0c0, 0x0111, 0xf7e8, 0xe0c0, 0x0065, 0xaf18, 0xa802, 0xf04a,
+    0xe0c0, 0x0281, 0xf7ea, 0xe42e, 0xcb94, 0xe0c2, 0x0115, 0xcba4,
+    0xe0c2, 0x012a, 0xcb8a, 0xe0c2, 0x0114, 0xa802, 0x3c62, 0xe42a,
+    0xcb12, 0xe0c2, 0x0120, 0xcb8c, 0xe0c2, 0x0121, 0xcb8e, 0xe0c2,
+    0x0122, 0xe42e, 0xcbd0, 0xe0c2, 0x0311, 0xe42e, 0xcb40, 0xe0c2,
+    0x0224, 0xcb42, 0xe0c2, 0x0225, 0xcb44, 0xe0c2, 0x0226, 0xcb46,
+    0xe0c2, 0x0227, 0xe42e, 0xe0c0, 0x0111, 0xf7e8, 0xa202, 0xe0c2,
+    0x0110, 0xe42e, 0x2844, 0xae04, 0x0844, 0x0844, 0xe000, 0x0100,
+    0xe09e, 0x2117, 0x4d17, 0xe0c2, 0x020d, 0xe0c2, 0x0214, 0x2117,
+    0x4d17, 0xe0c2, 0x020e, 0xe0c2, 0x0215, 0x2117, 0x4d17, 0xe0c2,
+    0x020f, 0xe0c2, 0x0216, 0xe42e, 0xa200, 0xe0c2, 0x030a, 0xe004,
+    0x0082, 0xa202, 0xae20, 0xe00a, 0x0842, 0xe0c2, 0x030b, 0xa202,
+    0xe0c2, 0x0302, 0x8442, 0xc786, 0xe018, 0xb608, 0xe000, 0x0100,
+    0xe094, 0x2112, 0x4d12, 0xe0c2, 0x0380, 0x2112, 0x4d12, 0xe0c2,
+    0x0381, 0x2112, 0x4d12, 0xe0c2, 0x0382, 0x8443, 0xc786, 0xe018,
+    0xb608, 0xe000, 0x0100, 0xe094, 0x2112, 0x4d12, 0xe0c2, 0x0383,
+    0x2112, 0x4d12, 0xe0c2, 0x0384, 0x2112, 0x4d12, 0xe0c2, 0x0385,
+    0xa200, 0xe0c2, 0x0302, 0xe42e, 0xa202, 0xae02, 0xa902, 0xe0c2,
+    0x0312, 0xa220, 0xe0c2, 0x0313, 0xe42e, 0xe42e, 0x2892, 0xe424,
+    0x2861, 0xa802, 0xf06a, 0xcb95, 0xa83f, 0x289b, 0xe056, 0xf09e,
+    0xcb94, 0xa83e, 0xae10, 0x3c9b, 0x2a61, 0xa003, 0x1a1a, 0xe429,
+    0x2a61, 0xe009, 0x00ff, 0xaf03, 0xe001, 0x0400, 0xe09f, 0x3d07,
+    0x2861, 0xa002, 0x181a, 0xf06a, 0x2861, 0xa002, 0xe008, 0x00ff,
+    0xe428, 0x2861, 0xe008, 0xff00, 0xe005, 0x029c, 0xae11, 0xe042,
+    0x2a92, 0x8492, 0xe182, 0x1fe0, 0xe019, 0xe042, 0xe0c1, 0x0041,
+    0xe042, 0xe0c1, 0x005a, 0xae1f, 0xe042, 0xca29, 0xf7f9, 0xce20,
+    0xe004, 0x0080, 0x2a61, 0xa003, 0x1a1a, 0xf078, 0x2861, 0xe008,
+    0x00ff, 0xa006, 0xe008, 0x00fc, 0xce24, 0xd111, 0x0400, 0xd113,
+    0x0002, 0xca28, 0xf7f8, 0xe42e, 0x2890, 0xe424, 0x2861, 0xe008,
+    0x00ff, 0xf208, 0x2861, 0xe008, 0xff00, 0xe005, 0x029c, 0xae11,
+    0xe042, 0x8491, 0xe182, 0x1fe0, 0xe019, 0xe042, 0xe0c1, 0x0041,
+    0xe042, 0xe0c1, 0x005a, 0xae1f, 0xe042, 0xca29, 0xf7f9, 0xce20,
+    0xe004, 0x0080, 0xce24, 0xd111, 0x0480, 0xd113, 0x0003, 0xca28,
+    0xf7f8, 0x2861, 0xa802, 0xf0a8, 0x2861, 0xe008, 0x00ff, 0xaf02,
+    0xe000, 0x0480, 0xe09e, 0x2907, 0x3c9c, 0x289c, 0x2a61, 0xa803,
+    0xf029, 0xaf10, 0xe008, 0x001f, 0xe42e, 0x2890, 0xe424, 0xe0c0,
+    0x014b, 0xf7e8, 0x289d, 0xae04, 0xa004, 0xae0e, 0x4c97, 0xae0e,
+    0x0898, 0xe0c2, 0x014d, 0xa202, 0xe0c2, 0x014a, 0xe0c0, 0x014b,
+    0xf7e8, 0xe42e, 0xe0c0, 0x0065, 0xaf18, 0xa802, 0xe40a, 0x0f54,
+    0xae0a, 0xe0c1, 0x0060, 0xaf0d, 0xa80f, 0xe056, 0xe0c1, 0x0044,
+    0xa811, 0xe056, 0xae0c, 0xe0c1, 0x0044, 0xa80f, 0xe056, 0xe167,
+    0x0ba7, 0x2f17, 0xe056, 0xe0c2, 0x0282, 0xe0c0, 0x006e, 0xe0c2,
+    0x0284, 0xaf20, 0xe0c1, 0x0282, 0xa809, 0xf04b, 0xe049, 0xae1f,
+    0xf06e, 0xe049, 0xa011, 0xaf09, 0xae07, 0xae21, 0xe056, 0xe0c2,
+    0x028c, 0xe167, 0x0ba8, 0x2d17, 0x4917, 0xe0c2, 0x0285, 0xe167,
+    0x0baa, 0x2d17, 0x4917, 0xe0c2, 0x0286, 0xe41e, 0x0f55, 0xe0c0,
+    0x004a, 0xe0c2, 0x0289, 0xe0c0, 0x004b, 0xe0c2, 0x028a, 0xe0c0,
+    0x0055, 0xe0c2, 0x028b, 0xe0c1, 0x0041, 0xe004, 0x0220, 0xae10,
+    0xe042, 0xe167, 0x0ba6, 0x2b17, 0xf05b, 0xe167, 0x0ba0, 0x2d17,
+    0x4917, 0xe0c2, 0x0287, 0xe0c1, 0x0041, 0xe004, 0x0238, 0xae10,
+    0xe042, 0xe167, 0x0ba6, 0x2b17, 0xf05b, 0xe167, 0x0ba2, 0x2d17,
+    0x4917, 0xe0c2, 0x0288, 0xe0c1, 0x0041, 0xe004, 0x0240, 0xae10,
+    0xe042, 0xe167, 0x0ba6, 0x2b17, 0xf05b, 0xe167, 0x0ba4, 0x2d17,
+    0x4917, 0xe0c2, 0x028d, 0xe0c0, 0x0065, 0xaf18, 0xa802, 0xe0c2,
+    0x0280, 0xa210, 0xe0c2, 0x0168, 0xe42e, 0xe167, 0x0bac, 0xe165,
+    0x028e, 0xe166, 0x02c0, 0xd022, 0x0008, 0xe184, 0x0f68, 0x2d17,
+    0x9f16, 0x9e85, 0xf7fb, 0x2517, 0x4d17, 0x9f16, 0x9e85, 0xf7fb,
+    0xe190, 0xe166, 0x02d2, 0xd022, 0x0008, 0xe184, 0x0f74, 0x2517,
+    0x4d17, 0x9f16, 0x9e85, 0xf7fb, 0xe190, 0xe166, 0x02db, 0xd022,
+    0x0008, 0xe184, 0x0f80, 0x2517, 0x4d17, 0x9f16, 0x9e85, 0xf7fb,
+    0xe190, 0xe166, 0x02e4, 0xd022, 0x0008, 0xe184, 0x0f8b, 0x2d17,
+    0x9f16, 0x9e85, 0xf7fb, 0xe190, 0xe42e, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe40e, 0x0020, 0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x0131,
+    0xe470, 0xe190, 0xe40e, 0x0113, 0xe470, 0xe190, 0xe470, 0xe190,
+    0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+    0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x012f, 0xe40e, 0x0131,
+    0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058,
+    0xa200, 0xe0c2, 0x005a, 0x3cf0, 0x3cf1, 0xa2fe, 0x3cee, 0x3cef,
+    0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d, 0xce00, 0xf11e, 0xe0c0,
+    0x005c, 0xe0c1, 0x0059, 0x3eed, 0xa203, 0x5aed, 0xe052, 0xf08a,
+    0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00, 0xe41e,
+    0x008c, 0xe41e, 0x00ab, 0xe0c0, 0x005a, 0x18ee, 0xe0c1, 0x0059,
+    0xa115, 0xb636, 0x2aee, 0xb60a, 0xe418, 0x00fb, 0xe0c0, 0x005b,
+    0xe0c1, 0x005e, 0xae11, 0xe056, 0x18ef, 0xe0c1, 0x0059, 0xa117,
+    0xb636, 0xe418, 0x00b0, 0xe0c0, 0x005a, 0x18ee, 0x2aee, 0xb60a,
+    0xe0c1, 0x0059, 0xa117, 0xb636, 0xe418, 0x00f3, 0xd071, 0x802a,
+    0xe181, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100, 0xe0c0, 0x0059,
+    0xae02, 0xe000, 0x0113, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a,
+    0x3cee, 0xe41e, 0x0100, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11,
+    0xe056, 0x3cef, 0xe40e, 0x0037, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+    0x0058, 0xe0c2, 0x0008, 0xe0c0, 0x0059, 0xf7ea, 0xa11e, 0xf0e8,
+    0xa202, 0xe0c2, 0x0058, 0xe004, 0x093d, 0xe0c2, 0x0070, 0xa200,
+    0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xf6fe, 0xa202, 0xe0c2, 0x0008,
+    0xe0c2, 0x0058, 0xe42e, 0xd101, 0x0001, 0xc70f, 0xa000, 0xe42e,
+    0xa200, 0xe0c1, 0x005b, 0xf27b, 0xa220, 0xa103, 0xf2eb, 0xa230,
+    0xa103, 0xf2bb, 0xa23c, 0xa103, 0xf24b, 0xa258, 0xa103, 0xf25b,
+    0xa260, 0xa103, 0xf22b, 0xa200, 0xa103, 0xf1fb, 0xa26c, 0xa103,
+    0xf1cb, 0xe004, 0x003e, 0xa103, 0xf18b, 0xe004, 0x0044, 0xa105,
+    0xf14b, 0xe004, 0x0046, 0xa103, 0xf10b, 0xe004, 0x0000, 0xa107,
+    0xf0cb, 0xa200, 0xe0c1, 0x005e, 0xf08b, 0xe004, 0x004c, 0xf05e,
+    0xe0c1, 0x005e, 0xf02b, 0xa010, 0xae16, 0xe0c1, 0x0040, 0xe041,
+    0xca28, 0xf7f8, 0xce21, 0xd111, 0x0000, 0xd112, 0x2000, 0xd113,
+    0x000b, 0xe1e1, 0xe42e, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100,
+    0xe004, 0x0133, 0xe67c, 0xe41e, 0x0100, 0xe004, 0x0135, 0xe67c,
+    0x28ee, 0xe008, 0x03ff, 0xcca4, 0xe182, 0x0029, 0xe018, 0x2eee,
+    0xaf15, 0xcca5, 0xe182, 0x0029, 0xe019, 0xae15, 0xe042, 0xae14,
+    0x34f0, 0x3cf1, 0xe42e, 0xe40e, 0x0529, 0xe40e, 0x0137, 0xe40e,
+    0x013b, 0xe40e, 0x013f, 0xe40e, 0x0143, 0xe40e, 0x007e, 0xe40e,
+    0x0147, 0xe40e, 0x007e, 0xe40e, 0x014b, 0xe40e, 0x007e, 0xe40e,
+    0x007e, 0xe40e, 0x007e, 0xe40e, 0x007e, 0xe40e, 0x007e, 0xe40e,
+    0x007e, 0xe40e, 0x007e, 0xe40e, 0x03ff, 0xe40e, 0x0412, 0xe41e,
+    0x0221, 0xe40e, 0x007e, 0xe41e, 0x0264, 0xe40e, 0x007e, 0xe41e,
+    0x027d, 0xe40e, 0x007e, 0xe41e, 0x03b3, 0xe40e, 0x007e, 0xe41e,
+    0x04b2, 0xe40e, 0x007e, 0xe41e, 0x05cf, 0xe40e, 0x007e, 0xa2fa,
+    0x3c66, 0x3c67, 0x3c68, 0x3c6b, 0xa200, 0x3c6a, 0xe42e, 0xe167,
+    0x0300, 0xa200, 0xc71f, 0x3d17, 0xa200, 0x3c5e, 0xe42e, 0xe000,
+    0x0300, 0xe09e, 0x2907, 0xa80a, 0x3d07, 0xe42e, 0xe424, 0xe000,
+    0x0300, 0xe09e, 0x2907, 0xa804, 0x3d07, 0xe42e, 0xe000, 0x0300,
+    0xe09e, 0x2907, 0xa908, 0x3d07, 0xe42e, 0x285e, 0x3c49, 0x2849,
+    0xe000, 0x0300, 0xe09e, 0x2907, 0xf0fa, 0x2849, 0xa002, 0x3c49,
+    0x1835, 0xf034, 0xa200, 0x3c49, 0x2849, 0x185e, 0xf718, 0xa200,
+    0x3c5e, 0xa2fe, 0xe42e, 0xa20e, 0x3d07, 0x2849, 0xa002, 0x3c5e,
+    0x1835, 0xf038, 0xa200, 0x3c5e, 0x2849, 0xe42e, 0xa2fa, 0x3c59,
+    0x3c5a, 0x3c5c, 0x3c5b, 0xe42e, 0x285a, 0xe412, 0x015f, 0xe42e,
+    0x285b, 0x3c5c, 0x2819, 0xa104, 0xf0ea, 0x2a56, 0xa105, 0x2859,
+    0x3c5d, 0xa2fe, 0x3c5b, 0xe42b, 0x2859, 0x3c5a, 0x285c, 0x3c5d,
+    0x3c59, 0xe42e, 0x2a56, 0xa105, 0xe42b, 0x2859, 0x3c5a, 0x285c,
+    0x3c59, 0x2819, 0x3c56, 0xe42e, 0x285b, 0x3c5c, 0xe41e, 0x0175,
+    0x3c5b, 0x2819, 0xa104, 0xf0ea, 0x2a56, 0xa105, 0x2819, 0x3c56,
+    0x2859, 0x3c5d, 0xe42b, 0x2859, 0x3c5a, 0x285c, 0x3c5d, 0x3c59,
+    0xe42e, 0x285b, 0x3c5d, 0xe41e, 0x015f, 0x2a56, 0xa105, 0xe42b,
+    0x2859, 0x3c5a, 0x285c, 0x3c59, 0x2819, 0x3c56, 0xe42e, 0xa200,
+    0x3c70, 0x2835, 0xa102, 0xcc44, 0xe184, 0x01f4, 0xe0c0, 0x0054,
+    0x5c70, 0xa802, 0xf058, 0x2870, 0xe41e, 0x0166, 0xf04e, 0x2870,
+    0xe41e, 0x016e, 0x2a70, 0xa003, 0x3e70, 0xe42e, 0xe004, 0x0300,
+    0xe09e, 0xe004, 0x0054, 0xe09c, 0x2835, 0xa102, 0xcc44, 0xa200,
+    0x3c70, 0xe184, 0x020a, 0x2b17, 0xaf05, 0xa803, 0x5a70, 0xe056,
+    0x2a70, 0xa003, 0x3e70, 0x9f06, 0xe42e, 0x285b, 0xe000, 0x0300,
+    0xe09e, 0x2b07, 0xa80d, 0x3f07, 0xe42e, 0xe161, 0x0300, 0x2835,
+    0xa102, 0xcc44, 0xe184, 0x021f, 0x2911, 0xe016, 0xe428, 0xe190,
+    0xe42e, 0xd130, 0x0005, 0xe004, 0x004e, 0xe0c2, 0x017c, 0xe004,
+    0x004c, 0xe0c2, 0x017d, 0xa200, 0x3c3c, 0x3c3b, 0xc401, 0xe188,
+    0x07ff, 0x3d11, 0xe0c0, 0x0062, 0xaf02, 0x30b9, 0xaf02, 0x30b6,
+    0xaf02, 0x30b7, 0xe41e, 0x04bf, 0xe41e, 0x0157, 0xe41e, 0x0196,
+    0xe41e, 0x064c, 0x2010, 0x4c11, 0xe0c2, 0x0071, 0xe0c2, 0x004f,
+    0xe41e, 0x0487, 0xe0c2, 0x0072, 0xa208, 0xe0c2, 0x0073, 0xa202,
+    0xe0c2, 0x0074, 0x2813, 0xe0c2, 0x006c, 0x2815, 0xae10, 0x4c17,
+    0xae10, 0x4c16, 0xe0c2, 0x007b, 0xe41e, 0x0265, 0xe41e, 0x05ff,
+    0xa202, 0xe0c2, 0x0070, 0xe42e, 0xe42e, 0xa200, 0x3c50, 0x3c47,
+    0x3c38, 0x3cbb, 0x3cbc, 0x3cbd, 0x3cba, 0x3cbf, 0x3cc0, 0x3cbe,
+    0x3cc2, 0x3cc3, 0x3cc4, 0x3cc5, 0x3cc1, 0x3cc8, 0x3cc7, 0x3cc6,
+    0x3c64, 0xa2fa, 0x3c55, 0x3c5d, 0xe42e, 0xa200, 0xcc4a, 0xcc4c,
+    0x3c3a, 0x3ca3, 0x3c57, 0xe0c2, 0x007d, 0xe0c2, 0x007e, 0xe0c2,
+    0x007f, 0xe0c2, 0x0072, 0x285d, 0x3c55, 0xe0c2, 0x007a, 0xa2fa,
+    0xe0c2, 0x0071, 0xd152, 0x0005, 0xd130, 0x0005, 0xd03a, 0x0005,
+    0xd04b, 0x0001, 0xd04c, 0x0000, 0xd008, 0x0000, 0xe0c0, 0x0065,
+    0xaf0a, 0xa81e, 0xf18a, 0x30bd, 0xaf02, 0x30bc, 0xaf02, 0x30bb,
+    0xaf02, 0x30ba, 0xe0c0, 0x006c, 0xe002, 0x0088, 0x3cc6, 0xe0c0,
+    0x006a, 0xce20, 0xd112, 0x000c, 0xd111, 0x0436, 0xd113, 0x0003,
+    0xca28, 0xf7f8, 0xe41e, 0x0b63, 0x28b6, 0x2a47, 0xb616, 0xe418,
+    0x04ef, 0x2ab6, 0xf07b, 0xe0c0, 0x0045, 0xaf04, 0xa802, 0xe408,
+    0x0384, 0x2838, 0xe408, 0x0384, 0xe41e, 0x0f77, 0x28a8, 0xe408,
+    0x0384, 0xa2fa, 0xe0c2, 0x0077, 0xe41e, 0x01df, 0xe41e, 0x0215,
+    0xf098, 0xa2fe, 0xe0c2, 0x0077, 0xd152, 0x0000, 0xd153, 0x0000,
+    0xe42e, 0xe41e, 0x06b7, 0x28a8, 0xe408, 0x0384, 0x28b0, 0xe418,
+    0x0b1a, 0x28b1, 0xf24a, 0x2ab6, 0xf19b, 0xa2fa, 0xe0c2, 0x0071,
+    0xa2fc, 0xe0c2, 0x0077, 0x2819, 0xa104, 0xe01a, 0xae0e, 0x4c1c,
+    0xae02, 0x4c1f, 0xae02, 0x4c1e, 0xae06, 0x2a1d, 0xe017, 0xe056,
+    0xae24, 0x4c19, 0xe0c2, 0x0073, 0xe42e, 0xe41e, 0x0ece, 0x2819,
+    0xe0c2, 0x0073, 0x28b1, 0xa102, 0xe42a, 0xf54e, 0x28a8, 0xe408,
+    0x0384, 0xe41e, 0x01bc, 0xe41e, 0x0936, 0x2860, 0x4c61, 0xe418,
+    0x0e44, 0x2847, 0xa002, 0x3c47, 0x2a19, 0xa105, 0xe419, 0x019c,
+    0xe41e, 0x01f6, 0xe41e, 0x0d6d, 0xe41e, 0x020d, 0xd152, 0x0000,
+    0xd153, 0x0000, 0x2ab9, 0xf07b, 0x2847, 0xf058, 0xa2fa, 0xe0c2,
+    0x0071, 0xf07e, 0xf03b, 0x285d, 0xf02e, 0x285b, 0xe0c2, 0x0071,
+    0x2819, 0xa104, 0xe01a, 0xae0e, 0x4c1c, 0xae02, 0x4c1f, 0xae02,
+    0x4c1e, 0xae06, 0x2a1d, 0xe017, 0xe056, 0xae24, 0x4c1a, 0xe0c2,
+    0x0073, 0x2857, 0xe0c2, 0x0072, 0x2847, 0xe0c2, 0x0070, 0x285b,
+    0xe0c2, 0x0077, 0xc84a, 0xc84d, 0xae20, 0xe056, 0xe0c2, 0x0053,
+    0xa2fb, 0x286b, 0xf0a4, 0xa102, 0xf032, 0x3e66, 0xf06e, 0xa102,
+    0xf032, 0x3e67, 0xf02e, 0x3e68, 0xd152, 0x0000, 0xd153, 0x0000,
+    0x2847, 0xa102, 0xe426, 0xa202, 0x3c64, 0xd152, 0x0000, 0xd153,
+    0x0000, 0xe41e, 0x05ff, 0xe42e, 0x2860, 0x4c61, 0xe418, 0x0e5f,
+    0xa2fe, 0x3c5d, 0xe0c2, 0x0071, 0xa200, 0x3c60, 0x3c61, 0xd152,
+    0x0000, 0xd153, 0x0000, 0xe42e, 0xa2fc, 0xe0c2, 0x0077, 0xe41e,
+    0x01a0, 0x2859, 0x3c5d, 0xe0c2, 0x0071, 0x2855, 0xa002, 0xe424,
+    0xe41e, 0x0afb, 0x2838, 0xe408, 0x0374, 0xe0c0, 0x0060, 0xaf08,
+    0x3060, 0xaf02, 0x3061, 0x2847, 0xe0c2, 0x0070, 0xa202, 0x3c38,
+    0x2860, 0x4c61, 0xe418, 0x0e5f, 0xd152, 0x0000, 0xd153, 0x0000,
+    0xe42e, 0xe41e, 0x0ece, 0xa2fa, 0xe0c2, 0x0071, 0xd152, 0x0000,
+    0xd153, 0x0000, 0xe42e, 0xd130, 0x0005, 0xe41e, 0x03d0, 0xe0c0,
+    0x0060, 0xe42a, 0xe0c0, 0x0060, 0x3c35, 0xca28, 0xf7f8, 0xe0c0,
+    0x0042, 0xce20, 0xd111, 0x0110, 0xd112, 0x00c4, 0xd113, 0x0003,
+    0xca28, 0xf7f8, 0xe0c0, 0x0061, 0x3c36, 0xe41e, 0x014f, 0xe42e,
+    0xe004, 0x01d4, 0xe09e, 0xe0c0, 0x0064, 0x3517, 0x3d17, 0xe0c0,
+    0x0065, 0x3517, 0x3d17, 0xe0c0, 0x0066, 0x3517, 0x3d17, 0xe0c0,
+    0x0067, 0x3517, 0x3d17, 0xe0c0, 0x0069, 0xe167, 0x0ba0, 0x3d17,
+    0x3517, 0xe0c0, 0x006a, 0x3d17, 0x3517, 0xe0c0, 0x006b, 0x3d17,
+    0x3517, 0xe0c0, 0x0042, 0xe000, 0x1000, 0xce20, 0xd111, 0x0ba8,
+    0xd112, 0x004c, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e, 0xe0c0,
+    0x005a, 0x3cee, 0xe41e, 0x0100, 0xa206, 0xe41e, 0x041b, 0xe0c0,
+    0x005a, 0x3cee, 0xe41e, 0x0100, 0xa236, 0xe41e, 0x0431, 0xe41e,
+    0x0447, 0xe42e, 0xa234, 0xe41e, 0x0431, 0xe41e, 0x0467, 0xa204,
+    0xe41e, 0x041b, 0xe42e, 0x3ced, 0xe0c0, 0x0041, 0xe005, 0x0280,
+    0xae11, 0xe042, 0x22f0, 0x4ef1, 0xe042, 0xca29, 0xf7f9, 0xce20,
+    0xd111, 0x0000, 0xd112, 0x0c00, 0x88ed, 0x0113, 0xca28, 0xf7f8,
+    0xe42e, 0x3ced, 0xe0c0, 0x0041, 0xe005, 0x0298, 0xae11, 0xe042,
+    0x22f0, 0x4ef1, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x00c0,
+    0xd112, 0x0040, 0x88ed, 0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe161,
+    0x07e0, 0x8911, 0x0145, 0x8911, 0x0144, 0x8911, 0x0146, 0x8911,
+    0x0147, 0x8911, 0x0148, 0x8911, 0x0152, 0x8911, 0x0153, 0x2111,
+    0x4d11, 0xce80, 0x2111, 0x4d11, 0xce82, 0x2111, 0x4d11, 0xce84,
+    0x2111, 0x4d11, 0xce86, 0x2111, 0x4d11, 0xcc72, 0xe42e, 0xe161,
+    0x07e0, 0x8b11, 0x0145, 0x8b11, 0x0144, 0x8b11, 0x0146, 0x8b11,
+    0x0147, 0x8b11, 0x0148, 0x8b11, 0x0152, 0x8b11, 0x0153, 0xca80,
+    0x3511, 0x3d11, 0xca82, 0x3511, 0x3d11, 0xca84, 0x3511, 0x3d11,
+    0xca86, 0x3511, 0x3d11, 0xc872, 0x3511, 0x3d11, 0xe42e, 0x2814,
+    0xe42a, 0xa231, 0xa102, 0xf21a, 0xa102, 0xf12a, 0xa102, 0xa003,
+    0xf0fa, 0xa102, 0xa00b, 0xf19a, 0xa102, 0xf0aa, 0xa102, 0xa029,
+    0xf07a, 0xa102, 0xa015, 0xf11a, 0xa102, 0xb7f0, 0xe428, 0x3e71,
+    0x2a3b, 0xae21, 0x283c, 0xa002, 0x3c70, 0x8470, 0x8271, 0xe018,
+    0xe008, 0xffff, 0xe056, 0xe42e, 0xe004, 0x03e7, 0x3c3c, 0xa002,
+    0x3c3b, 0xf6ee, 0xa200, 0x3ca6, 0x3ca7, 0x3ca8, 0x3cab, 0x3ca0,
+    0x3c38, 0x3c3a, 0x3c47, 0x3ca2, 0x3ca1, 0xcc92, 0xe42e, 0xe41e,
+    0x0615, 0xa200, 0x3c9b, 0xe0c0, 0x0062, 0xaf0c, 0xa802, 0xf10a,
+    0xe0c1, 0x0048, 0xe0c0, 0x0060, 0xe045, 0xaf13, 0xae03, 0xa109,
+    0x3e9b, 0xf063, 0xe0c0, 0x0061, 0xae04, 0xe042, 0x3c9b, 0xe0c0,
+    0x0060, 0x3498, 0x3c99, 0xe0c0, 0x0061, 0xae04, 0x2ab6, 0xb7f2,
+    0x3c9a, 0x28b6, 0xf0aa, 0xe0c1, 0x0060, 0xe0c0, 0x0064, 0xe042,
+    0xe41e, 0x063e, 0xe41e, 0x061d, 0xe41e, 0x0503, 0xe42e, 0xa200,
+    0x3c9b, 0x2298, 0x4e99, 0x28b7, 0xf05a, 0xe0c1, 0x0068, 0x3698,
+    0x3e99, 0xe0c0, 0x0069, 0xe042, 0xe41e, 0x063e, 0xe41e, 0x061d,
+    0xe41e, 0x0503, 0xe42e, 0xe41e, 0x0518, 0xe41e, 0x0551, 0xd071,
+    0x802a, 0xe181, 0xa200, 0x3ca6, 0x3ca7, 0x3ca8, 0x3ca9, 0x3caa,
+    0x3cab, 0x3cac, 0xe41e, 0x055b, 0xe41e, 0x0f03, 0xe128, 0xe42e,
+    0xd030, 0x0000, 0xd034, 0x0000, 0xd033, 0x0000, 0xd035, 0x0000,
+    0xd036, 0x007f, 0xd037, 0x0000, 0xd038, 0x0000, 0xd04b, 0x0001,
+    0xe42e, 0x28a0, 0xf1a8, 0x28a3, 0xf088, 0xd04c, 0x0001, 0xe41e,
+    0x0f35, 0xd04c, 0x0000, 0xe470, 0xc896, 0xf05a, 0xe41e, 0x0547,
+    0xd04c, 0x0000, 0xe004, 0x0080, 0x2aa4, 0xb616, 0xcc6e, 0xd04b,
+    0x0001, 0xa202, 0x3c58, 0xe470, 0xd04c, 0x0000, 0xe470, 0xa200,
+    0x3c58, 0xe41e, 0x0f35, 0x28a0, 0xcc96, 0x28a4, 0xe016, 0x3ca4,
+    0xe42e, 0x2098, 0x4c99, 0x2e9b, 0xae11, 0xe042, 0xe005, 0x0048,
+    0xe093, 0x9f01, 0xe42e, 0x28a6, 0xf308, 0xa200, 0x3cad, 0xca28,
+    0xf7d8, 0xe082, 0x3c9c, 0xe004, 0x0048, 0xe092, 0xd027, 0x0000,
+    0xe41e, 0x0591, 0xd027, 0x0001, 0x28a6, 0x2aa7, 0xb602, 0xf1d8,
+    0xca28, 0xf7f8, 0x2098, 0x4c99, 0x2e9b, 0xae11, 0xe042, 0xce20,
+    0x9f01, 0xd111, 0x00c0, 0xd112, 0x0040, 0xe0c0, 0x0043, 0xa806,
+    0xae02, 0xa032, 0xce26, 0xca28, 0xf7f8, 0x2c9b, 0xe000, 0x0002,
+    0x3c9b, 0x1c9a, 0xf024, 0x3c9b, 0xd14e, 0x0000, 0x289c, 0xe092,
+    0xe42e, 0xe0c1, 0x0043, 0xa809, 0xe429, 0xa200, 0x3c9d, 0x28b6,
+    0xe418, 0x0b4b, 0xe0c0, 0x0045, 0xaf04, 0xa802, 0x3cab, 0x2098,
+    0x4c99, 0x2e9b, 0xae11, 0xe042, 0x8111, 0x9e89, 0xe045, 0xf043,
+    0x2c9a, 0xae10, 0xe041, 0xe003, 0x0200, 0xe421, 0xca8a, 0xe001,
+    0x0200, 0xa011, 0xe041, 0x3ea7, 0xca94, 0x3cac, 0x28ab, 0x3ca6,
+    0xe428, 0x28b6, 0xf03a, 0x3cab, 0xe42e, 0x289d, 0xf5c8, 0xe0c0,
+    0x005c, 0xe008, 0x4000, 0xf57a, 0xe0c0, 0x005d, 0xe00a, 0x4000,
+    0xe0c2, 0x005d, 0xa202, 0xce00, 0x3c9d, 0xe40e, 0x059a, 0xe0c0,
+    0x0060, 0xf08a, 0xe0c0, 0x0061, 0x2298, 0x4e99, 0xe046, 0xaf12,
+    0xae02, 0x3c9b, 0xe180, 0xe41e, 0x0518, 0xe41e, 0x0551, 0xe41e,
+    0x0157, 0xe41e, 0x0196, 0xe166, 0x0054, 0x9e06, 0xf16a, 0x2835,
+    0xa102, 0xcc44, 0xa200, 0x3c70, 0xe184, 0x05fa, 0x9e06, 0x5c70,
+    0xa802, 0xf07a, 0x2870, 0xe000, 0x0300, 0xe09e, 0xa208, 0x3d07,
+    0x2870, 0xa002, 0x3c70, 0xe190, 0xa202, 0x3cb8, 0xe42e, 0xe0c0,
+    0x0048, 0xca89, 0xe003, 0x00c0, 0xa105, 0xae07, 0xe042, 0xca8b,
+    0xe015, 0xa80f, 0xe042, 0x2298, 0x4e99, 0xe045, 0xf047, 0x2e9a,
+    0xae11, 0xe042, 0xe0c2, 0x0046, 0xe42e, 0xe161, 0x0800, 0xa200,
+    0x3d11, 0xe004, 0x01b1, 0x3d11, 0xe42e, 0xca29, 0xf7f9, 0xe0c0,
+    0x0049, 0xe049, 0xaf06, 0xae06, 0xa80f, 0xe01b, 0xae07, 0xe042,
+    0xce20, 0xd111, 0x0800, 0xd112, 0x0004, 0xd113, 0x0002, 0xca28,
+    0xf7f8, 0xe42e, 0xc872, 0xe049, 0xa80f, 0xe01b, 0xaf06, 0xe042,
+    0x224a, 0x4e4b, 0xe045, 0xa200, 0xb62e, 0xe42e, 0xe0c1, 0x0049,
+    0xe045, 0x364a, 0x3e4b, 0xe42e, 0xcaa0, 0xe190, 0x28ad, 0xa002,
+    0x3cad, 0xca9c, 0xe418, 0x055b, 0xa203, 0xae1f, 0xcea7, 0xcaa2,
+    0xaf10, 0xa102, 0xf728, 0xcaa0, 0xe190, 0x28ad, 0xa002, 0x3cad,
+    0xca9c, 0xe418, 0x055b, 0xcaa0, 0xe190, 0x28ad, 0xa002, 0x3cad,
+    0xca9c, 0xe418, 0x055b, 0xa200, 0x3ca2, 0x3ca1, 0x3ca3, 0xe41e,
+    0x0f28, 0xba4e, 0xba4e, 0xe002, 0x00b0, 0xf5f8, 0xba4e, 0x3c16,
+    0xa140, 0xf03a, 0xe16b, 0xe42e, 0xba4e, 0x3c17, 0xba40, 0x3c15,
+    0x2a10, 0xba5a, 0xf2ca, 0x3c10, 0xf04b, 0x2810, 0xe045, 0xf275,
+    0xa01e, 0xaf08, 0x3c43, 0x2a11, 0xba5a, 0xf21a, 0x3c11, 0xf04b,
+    0x2811, 0xe045, 0xf1c5, 0xa01e, 0xaf08, 0x3c44, 0x3c65, 0xba42,
+    0x3c12, 0xba44, 0xba46, 0x3c13, 0xba46, 0x3c14, 0xf038, 0xe16b,
+    0xe42e, 0xba7c, 0xba40, 0x3c18, 0xba6a, 0x2810, 0xae20, 0x4c11,
+    0xe0c2, 0x006f, 0xe0c2, 0x004f, 0xa202, 0xe42e, 0x2810, 0xae20,
+    0x4c11, 0xe0c2, 0x006f, 0xe0c2, 0x004f, 0xa200, 0xe16b, 0xe42e,
+    0xcaa0, 0x28ad, 0xa002, 0x3cad, 0xca9c, 0xe418, 0x055b, 0xa203,
+    0xae1f, 0xcea7, 0xe41e, 0x0f77, 0xe428, 0xcaa2, 0x3c70, 0xaf10,
+    0xa102, 0xf6f8, 0x2870, 0xe008, 0x00ff, 0xe049, 0xe003, 0x00b1,
+    0xf3bb, 0xe002, 0x00af, 0xf030, 0xa202, 0xe42e, 0xcaa0, 0xe190,
+    0x28ad, 0xa002, 0x3cad, 0xca9c, 0xe418, 0x055b, 0xcaa0, 0xe190,
+    0x28ad, 0xa002, 0x3cad, 0xca9c, 0xe418, 0x055b, 0xe41e, 0x0f28,
+    0x2870, 0xe008, 0x00ff, 0xe002, 0x00af, 0xf030, 0xa202, 0xe42e,
+    0xba4e, 0xba4e, 0xe002, 0x00b0, 0xf12a, 0xa102, 0xf15a, 0xa102,
+    0xf17a, 0xa102, 0xf22a, 0xa104, 0xe40a, 0x075d, 0xa102, 0xe40a,
+    0x0791, 0xa102, 0xe40a, 0x07f8, 0xe40e, 0x06b7, 0xe41e, 0x066e,
+    0xe42d, 0xe40e, 0x06b7, 0xa202, 0x3c3a, 0xe40e, 0x06b0, 0x28bd,
+    0xf088, 0xba4e, 0xe41e, 0x0f1c, 0xf7d8, 0xe190, 0xe40e, 0x06b7,
+    0xe41e, 0x0833, 0xe40e, 0x06b7, 0xa202, 0x3c3a, 0x3cae, 0xba5e,
+    0xba40, 0xa102, 0xf028, 0xba6e, 0xba40, 0xba4e, 0x3c1b, 0x2818,
+    0xa102, 0xf028, 0xbdfe, 0xba40, 0xe049, 0x3c1c, 0xa103, 0xf02b,
+    0xba40, 0x3c1d, 0xe016, 0x3c2a, 0xba40, 0x3c1e, 0xba40, 0x3c1f,
+    0xba40, 0x3c20, 0xba4a, 0x3c21, 0x281c, 0x4c1d, 0xf038, 0xba40,
+    0x3c22, 0xba46, 0xba40, 0x3c26, 0xf078, 0xba40, 0xf05a, 0xbe7e,
+    0x3c23, 0xbe7e, 0x3c24, 0x2a1d, 0xf089, 0x2844, 0xe049, 0xaf02,
+    0xae02, 0xe045, 0x0a44, 0x3e44, 0x2844, 0xaf02, 0x3c45, 0x2a1d,
+    0x8443, 0x8244, 0xe018, 0x3c6c, 0xcf9a, 0xf029, 0xaf02, 0x3c37,
+    0x2800, 0x3c19, 0xe40e, 0x06b7, 0xe190, 0xba46, 0xa104, 0xf0aa,
+    0xa104, 0xf0fa, 0xa106, 0xf14a, 0xa108, 0xf18a, 0xf11e, 0xe40e,
+    0x06b7, 0xba46, 0xba40, 0xf02a, 0xba6e, 0xba7c, 0xe40e, 0x06b7,
+    0xba62, 0xba68, 0xba6c, 0xba6a, 0xe40e, 0x06b7, 0xba4e, 0xe41e,
+    0x0f1c, 0xf7d8, 0xe190, 0xe40e, 0x06b7, 0xba7e, 0xba6c, 0xba6c,
+    0xba6c, 0xba60, 0xba60, 0xba60, 0xba60, 0xba60, 0xba60, 0xba6c,
+    0xba6c, 0xba6c, 0xba6c, 0xba6c, 0xba7e, 0xba40, 0xba7e, 0xe40e,
+    0x06b7, 0xa202, 0x3c3a, 0xba5e, 0xba42, 0x3c30, 0xa104, 0xf04a,
+    0xa204, 0x3cae, 0xf03e, 0xa206, 0x3cae, 0xba4e, 0x3c1b, 0x2818,
+    0xf02a, 0xbdfe, 0xba40, 0x3c1c, 0xf068, 0xba40, 0x3c1d, 0xf048,
+    0xba40, 0xf02e, 0x3c1d, 0xba40, 0x3c1e, 0xba40, 0x3c1f, 0xba40,
+    0x3c20, 0xba4a, 0x3c21, 0x2830, 0xa104, 0x2a1d, 0xa103, 0xe056,
+    0xf03a, 0xba40, 0x3c25, 0xba46, 0xba40, 0x3c22, 0xba40, 0x3c26,
+    0xf078, 0xba40, 0xf05a, 0xbe7e, 0x3c23, 0xbe7e, 0x3c24, 0x2830,
+    0xa104, 0xf18a, 0x2a1d, 0xf089, 0x2844, 0xe049, 0xaf02, 0xae02,
+    0xe045, 0x0a44, 0x3e44, 0x2a1d, 0x8443, 0x8244, 0xe018, 0x3c6c,
+    0xcf9a, 0xf029, 0xaf02, 0x3c37, 0xa202, 0x3c19, 0xe40e, 0x06b7,
+    0xe190, 0x2a1d, 0xf089, 0x2844, 0xe049, 0xaf02, 0xae02, 0xe045,
+    0x0a44, 0x3e44, 0x2a1d, 0x8443, 0x8244, 0xe018, 0x3c6c, 0xcf9a,
+    0xf029, 0xaf02, 0x3c37, 0xa204, 0x3c19, 0xe40e, 0x06b7, 0xe190,
+    0xe40e, 0x06b7, 0xe190, 0xba4e, 0x2810, 0xe002, 0x0af0, 0xf024,
+    0xba44, 0x2820, 0xf058, 0xba40, 0x3c27, 0xba4a, 0x3c28, 0x2819,
+    0xf27a, 0xba40, 0x3c2e, 0xf24a, 0x281d, 0xf03a, 0xa204, 0xf07e,
+    0x282b, 0xf04a, 0xa202, 0x2a1a, 0xf02b, 0xa208, 0x3c70, 0xe161,
+    0x0100, 0xe162, 0x0104, 0xe163, 0x0108, 0xe164, 0x010c, 0xa102,
+    0xcc44, 0xe184, 0x082c, 0xba4e, 0x3d11, 0xba4e, 0x3d12, 0xba40,
+    0xba4e, 0x3d13, 0xba4e, 0x3d14, 0xba40, 0xba40, 0x3c2d, 0x28be,
+    0xe016, 0x3cbe, 0xe42e, 0x2abd, 0x28c4, 0xa120, 0xb615, 0x3ebd,
+    0xe42b, 0xa200, 0x3cc2, 0xe162, 0x0420, 0xba4e, 0x2ac2, 0xa803,
+    0xf049, 0xae10, 0x3cc1, 0xf03e, 0x4cc1, 0x3d12, 0x2ac2, 0xa003,
+    0x3ec2, 0xa80f, 0xe41b, 0x08a0, 0x28bd, 0xf0aa, 0xe41e, 0x0f1c,
+    0xf6d8, 0x28c2, 0x28c2, 0xa802, 0xf03a, 0x28c1, 0x3d12, 0xa211,
+    0x28c2, 0xa80e, 0xf0ba, 0xe045, 0xaf03, 0xf06b, 0xa103, 0x3e70,
+    0xa201, 0x8670, 0x3f12, 0xe41e, 0x08a0, 0xe162, 0x0420, 0x28c3,
+    0x3d12, 0x28c2, 0x3d12, 0xa200, 0x3d12, 0x3d12, 0xe0c1, 0x006b,
+    0x28c4, 0xa002, 0xae06, 0xe041, 0xaf06, 0x3cc4, 0xce21, 0xd111,
+    0x0420, 0xd112, 0x0004, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e,
+    0xa200, 0x3cc7, 0xe0c0, 0x005c, 0xe0c1, 0x0065, 0xaf12, 0xa802,
+    0xaf15, 0xa803, 0xe016, 0xe056, 0xf04a, 0xa200, 0x3cbd, 0xe42e,
+    0x28c8, 0xf05a, 0xe0c0, 0x005d, 0xe42a, 0xf7be, 0xe0c0, 0x005d,
+    0xe00a, 0x0200, 0xe0c2, 0x005d, 0xa202, 0xce00, 0x3cc8, 0xf71e,
+    0xd112, 0x0004, 0xe0c0, 0x006b, 0xe000, 0x0088, 0x08c7, 0xce20,
+    0xd111, 0x0420, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe162, 0x0420,
+    0x28c5, 0x2ac7, 0xa010, 0xa011, 0x3cc5, 0x3ec7, 0x1ac6, 0xe41b,
+    0x0880, 0xa200, 0x3cc8, 0xe42e, 0x2a40, 0xa803, 0xf139, 0xae10,
+    0x3cc0, 0x2a2b, 0xe017, 0x462a, 0xe429, 0x2a6c, 0xa103, 0x1a40,
+    0xe429, 0xe005, 0x0320, 0x0abf, 0xe095, 0x3d02, 0xe41e, 0x08ec,
+    0xe42e, 0x4cc0, 0xe005, 0x0320, 0x0abf, 0xe095, 0x3d02, 0x28bf,
+    0xa002, 0x3cbf, 0xe002, 0x0080, 0xf068, 0xe41e, 0x08ec, 0xa200,
+    0x3cbf, 0xe42e, 0x2a2b, 0xe017, 0x462a, 0xe429, 0x286c, 0xa102,
+    0x1840, 0xe41a, 0x08ec, 0xe42e, 0x2a40, 0xaf11, 0xae11, 0xe162,
+    0x043c, 0x2112, 0x4d02, 0xe042, 0xce20, 0xd112, 0x0080, 0xd111,
+    0x0320, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0xcb86, 0xa802,
+    0xf08a, 0xa201, 0x2819, 0xae02, 0xa102, 0x3c70, 0x8670, 0x3f12,
+    0x282c, 0x2a19, 0xa103, 0xa004, 0xb452, 0x3c2c, 0xe002, 0x0080,
+    0xf068, 0xe41e, 0x0920, 0xa200, 0x3c2c, 0xe42e, 0x2a2b, 0xe017,
+    0x462a, 0xe429, 0x286c, 0xa102, 0x1840, 0xe41a, 0x0920, 0xe42e,
+    0x2819, 0xa802, 0x3c70, 0x2a40, 0xaf0b, 0x5e70, 0xae11, 0xe162,
+    0x0440, 0x2112, 0x4d02, 0xe042, 0xce20, 0xd112, 0x0080, 0xd111,
+    0x03a0, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0xa200, 0x3c40,
+    0x3cbf, 0x3c2c, 0x3c2b, 0x3cc0, 0xcea6, 0xe016, 0x3cbe, 0x2819,
+    0x3c1a, 0xe41e, 0x0afb, 0xe41e, 0x0b73, 0xe41e, 0x0971, 0x281b,
+    0x2a1d, 0xf029, 0xae02, 0xe0c2, 0x007a, 0x281d, 0xf178, 0xa202,
+    0x3c2b, 0x28b6, 0xf03a, 0xe41e, 0x0a13, 0x281b, 0xae02, 0xa002,
+    0xe0c1, 0x007a, 0xae14, 0xe055, 0xe0c3, 0x007a, 0x2819, 0xb634,
+    0x3c19, 0xe41e, 0x0b73, 0xe41e, 0x0971, 0x2819, 0xa104, 0xf02a,
+    0xcfca, 0xa202, 0xe0c2, 0x0076, 0xe42e, 0xa200, 0xe0c2, 0x0076,
+    0xe42e, 0xd1c6, 0x0001, 0xe16a, 0xa200, 0x3c3f, 0x3c41, 0x3c42,
+    0xa2fe, 0x3c33, 0x281b, 0xcfc8, 0x2833, 0xcf8a, 0x2842, 0xae0e,
+    0x4c41, 0xcf94, 0x2841, 0xf1c8, 0x2833, 0xf1a0, 0xe41c, 0x09fc,
+    0xe41d, 0x09e7, 0x3c70, 0x28a3, 0xf0d8, 0xa200, 0x3c58, 0x28a0,
+    0xf098, 0xa202, 0x3ca3, 0x3c58, 0x3ca4, 0xd036, 0x00ff, 0xd037,
+    0x0080, 0x2870, 0xf05a, 0xe41e, 0x07fb, 0xe41e, 0x0c3d, 0xe41e,
+    0x0a40, 0xe41c, 0x0a4d, 0xe41d, 0x0a2f, 0xe41e, 0x0d07, 0xe41d,
+    0x0ee5, 0xe41e, 0x09bc, 0xcb8a, 0x3c33, 0x2837, 0x183f, 0xf538,
+    0xe0c0, 0x0111, 0xf7e8, 0xe0c0, 0x0065, 0xaf18, 0xa802, 0xf04a,
+    0xe0c0, 0x0281, 0xf7ea, 0xe42e, 0xd1c8, 0x0001, 0x283f, 0xa002,
+    0x3c3f, 0x2840, 0xa002, 0x3c40, 0x2841, 0xa002, 0x3c41, 0x1843,
+    0xe428, 0xd1c6, 0x0004, 0x3c41, 0x2842, 0xa002, 0x3c42, 0xe42e,
+    0x2819, 0xa104, 0xf0ca, 0x2851, 0x3c70, 0x2850, 0x3c51, 0x2852,
+    0x3c50, 0x2870, 0x3c52, 0x2819, 0x3c56, 0xe42e, 0x2853, 0x3c70,
+    0x2852, 0x3c53, 0x2870, 0x3c52, 0x2819, 0x3c56, 0xe42e, 0xa200,
+    0x3ca3, 0x2a29, 0x1a42, 0xe429, 0xe16a, 0xd153, 0x0000, 0xcaa0,
+    0xe190, 0xcaa0, 0xe190, 0xcaa0, 0xe190, 0x28ad, 0xa006, 0x3cad,
+    0xe41e, 0x0f28, 0xa202, 0xe42e, 0xc894, 0xf05a, 0x283f, 0xf03a,
+    0xa200, 0xe42e, 0xe41e, 0x0a2a, 0xcaa0, 0xe190, 0xcaa0, 0xe190,
+    0xcaa0, 0xe190, 0x28ad, 0xa006, 0x3cad, 0xa200, 0x3ca3, 0xe41e,
+    0x0f28, 0xa202, 0xe42e, 0xe0c0, 0x005c, 0xe008, 0x0400, 0xe42a,
+    0xe004, 0x0400, 0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202,
+    0xce00, 0xe0c0, 0x005d, 0xe008, 0x0400, 0xe190, 0xf7b8, 0xe41e,
+    0x04ef, 0xe42e, 0xc868, 0xa80e, 0x3c70, 0x7470, 0xe42e, 0xa2fe,
+    0x3c33, 0xd1ce, 0x0000, 0xd1c3, 0x0000, 0xcbc0, 0xf7f8, 0xd1c0,
+    0x0020, 0xd1e0, 0x0010, 0xcbc0, 0xf7f8, 0xd1e0, 0x000a, 0xe42e,
+    0x2842, 0xae0e, 0x4c41, 0xcf94, 0x2840, 0xcf98, 0xd1c3, 0x0000,
+    0xcbc0, 0xf7f8, 0xd1e0, 0x0005, 0xe42e, 0xcbc0, 0xf7f8, 0xe190,
+    0xe180, 0x2858, 0xe418, 0x0547, 0xe181, 0xd1c0, 0x000f, 0xcb9d,
+    0xcb80, 0xf0c9, 0xf7d8, 0xd1e0, 0x000a, 0x2826, 0xf038, 0xd1c0,
+    0x0010, 0xcbc0, 0xf7f8, 0xe16a, 0xe42e, 0xd1c0, 0x0000, 0xd1ce,
+    0x0000, 0xe16b, 0xe42e, 0x286a, 0xe424, 0xcba9, 0xa87f, 0x3e6d,
+    0x2841, 0xa802, 0xf0e8, 0xae11, 0x3e6f, 0x2841, 0xa002, 0x1843,
+    0xe428, 0x2841, 0xaf02, 0xe000, 0x0200, 0xe09e, 0x3f07, 0xf0ee,
+    0x2a6f, 0x2841, 0xaf02, 0xe000, 0x0200, 0xe09e, 0x4e6d, 0x3f07,
+    0x2841, 0xa002, 0x1843, 0xe428, 0xf01e, 0x2843, 0xa002, 0xaf02,
+    0xa006, 0xa2f9, 0xe052, 0xae02, 0x3c70, 0x2842, 0x2a1d, 0xf039,
+    0xae02, 0x082b, 0x3c71, 0xe0c1, 0x0041, 0xe004, 0x029c, 0xae10,
+    0xe042, 0x846a, 0xe182, 0x2000, 0xe019, 0xe042, 0x8471, 0x8270,
+    0xe019, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0200, 0x2870,
+    0xaf02, 0xce24, 0xa204, 0xce26, 0xca28, 0xf7f8, 0xe42e, 0x2a41,
+    0x286e, 0xa803, 0xf06b, 0xe049, 0xa13f, 0xe427, 0xa23e, 0xe42e,
+    0x2841, 0xe41a, 0x0ad2, 0x2841, 0xaf02, 0xe000, 0x0280, 0xe09e,
+    0x2907, 0xe049, 0xaf10, 0xa87f, 0x3e6e, 0xe049, 0xa13f, 0xe427,
+    0xa23e, 0xe42e, 0x2843, 0xa002, 0xaf02, 0xa006, 0xa2f9, 0xe052,
+    0xae02, 0x3c70, 0x2842, 0x2a2b, 0xf02b, 0x0845, 0x3c71, 0xe0c1,
+    0x0041, 0xe004, 0x029c, 0xae10, 0xe042, 0x846b, 0xe182, 0x2000,
+    0xe019, 0xe042, 0x8471, 0x8270, 0xe019, 0xe042, 0xca29, 0xf7f9,
+    0xce20, 0xd111, 0x0280, 0x2870, 0xaf02, 0xce24, 0xa206, 0xce26,
+    0xca28, 0xf7f8, 0xe42e, 0x2855, 0xf0c4, 0x2a66, 0xe045, 0xf039,
+    0xa200, 0xf07e, 0x2a67, 0xe045, 0xf039, 0xa202, 0xf02e, 0xa204,
+    0x3c6b, 0xa2ff, 0x285b, 0xf0d4, 0x2a66, 0xf043, 0x3c66, 0xa201,
+    0xf08e, 0x2a67, 0xf043, 0x3c67, 0xa203, 0xf03e, 0x3c68, 0xa205,
+    0x3e6a, 0xe42e, 0x28b0, 0xf2da, 0xa102, 0xf06a, 0xa102, 0xf12a,
+    0xa104, 0xf0aa, 0xf12e, 0x28ae, 0xa102, 0xf138, 0x28af, 0xf216,
+    0xa102, 0x3caf, 0xf0ee, 0x28ae, 0xa102, 0xf1ba, 0xa102, 0xf19a,
+    0xf04e, 0x28ae, 0xa102, 0xf15a, 0x28af, 0xa102, 0x3caf, 0xf056,
+    0xa204, 0x3cb1, 0xa202, 0xe42e, 0x285d, 0xe0c2, 0x0071, 0xa2fc,
+    0xe0c2, 0x0077, 0xa200, 0xe0c2, 0x0074, 0xa202, 0x3cb1, 0xe42e,
+    0xa200, 0x3cb1, 0xe42e, 0x2098, 0x4c99, 0xe0c1, 0x0067, 0xe042,
+    0xe0c1, 0x0069, 0xa80f, 0xe042, 0x8111, 0x9f09, 0xe0c0, 0x0045,
+    0xaf04, 0xa802, 0x3cab, 0xe42e, 0xe0c0, 0x0069, 0xa80e, 0xa102,
+    0xe424, 0xcaa0, 0xf7de, 0xe0c0, 0x0066, 0x3caf, 0xe0c0, 0x0065,
+    0xaf04, 0xa80e, 0x3cb0, 0xa200, 0x3cb1, 0x28b8, 0xe418, 0x0503,
+    0xa200, 0x3cb8, 0xe42e, 0xa200, 0xcc8e, 0xa20a, 0xe0c2, 0x0100,
+    0xe004, 0x00ce, 0xe0c2, 0x017c, 0xe004, 0x004c, 0xe0c2, 0x017d,
+    0xe0c0, 0x0050, 0xe049, 0xe008, 0x000f, 0x3c0c, 0xaf11, 0xe009,
+    0x000f, 0x3e0d, 0x460c, 0x3e0c, 0xe0c0, 0x0050, 0xaf1c, 0xa802,
+    0xe005, 0x0ba6, 0xe09f, 0x3d17, 0xa200, 0x2a0c, 0xa803, 0xf03b,
+    0xe00a, 0x0002, 0x2a0c, 0xa805, 0xf03b, 0xe00a, 0x0009, 0x2a0c,
+    0xa809, 0xf03b, 0xe00a, 0x0020, 0x2a0c, 0xa811, 0xf03b, 0xe00a,
+    0x0040, 0xe005, 0x0ba6, 0xe09f, 0x2b17, 0xae05, 0xe056, 0xe0c2,
+    0x0169, 0xe0c1, 0x0041, 0xe004, 0x0010, 0xae10, 0xe042, 0x2a0d,
+    0xa805, 0xf05b, 0xe167, 0x01d6, 0x2117, 0x4d17, 0xe0c2, 0x0103,
+    0x2843, 0xae20, 0x4c44, 0xae08, 0xe0c2, 0x0101, 0xe0c2, 0x006f,
+    0x2a10, 0xa01f, 0xaf09, 0xae29, 0x2811, 0xa01e, 0xaf08, 0xae08,
+    0xe056, 0xe0c2, 0x0283, 0x2844, 0xae0e, 0x4c43, 0xcf96, 0x2823,
+    0xa87e, 0xae0c, 0x2a24, 0xa87f, 0xe056, 0xcf8e, 0x2826, 0xcfd6,
+    0xe0c0, 0x0060, 0xaf08, 0xa806, 0xe01a, 0x4464, 0xe418, 0x0e09,
+    0x2825, 0xae02, 0x4c1d, 0xae02, 0x4c2b, 0xcfc2, 0x282b, 0xf098,
+    0x2820, 0xae0c, 0x4c21, 0xae02, 0x4c22, 0xae04, 0x4c19, 0xcf82,
+    0x2819, 0xcf88, 0xe0c0, 0x0044, 0xa80e, 0xae1a, 0x4c36, 0xe0c2,
+    0x0102, 0x282a, 0xa908, 0xae04, 0x4c19, 0xae04, 0x4c2a, 0xae02,
+    0x4c2b, 0xe0c2, 0x0104, 0x2a2a, 0x28ef, 0xae08, 0x4c19, 0xae04,
+    0xe056, 0xae02, 0x4c2b, 0xe0c1, 0x0065, 0xaf19, 0xa803, 0xae17,
+    0xe056, 0xe0c2, 0x0204, 0x282b, 0xe41a, 0x0cc2, 0xe41e, 0x0c75,
+    0xe161, 0x01d0, 0x2111, 0x4d01, 0xcfc6, 0xe0c1, 0x0041, 0xe004,
+    0x0000, 0xae10, 0xe042, 0x2a0d, 0xa803, 0xf05b, 0xe167, 0x01d4,
+    0x2117, 0x4d17, 0xcfc4, 0xa202, 0xe0c2, 0x0106, 0xa201, 0xe167,
+    0x0ba7, 0x3f17, 0xe41e, 0x0f96, 0xe42e, 0xa200, 0x3c57, 0xa2fe,
+    0x3c33, 0xcf8a, 0x2827, 0xae0c, 0x4c28, 0xae02, 0x4c2e, 0xae02,
+    0x4c2d, 0xcf84, 0xd1c6, 0x0002, 0xe161, 0x0100, 0xe162, 0x0104,
+    0xe163, 0x0108, 0xe164, 0x010c, 0x2911, 0xae10, 0x4d11, 0xae10,
+    0x4d11, 0xae10, 0x4d01, 0xcfce, 0x2912, 0xae10, 0x4d12, 0xae10,
+    0x4d12, 0xae10, 0x4d02, 0xcfd0, 0x2913, 0xae10, 0x4d13, 0xae10,
+    0x4d13, 0xae10, 0x4d03, 0xcfd2, 0x2914, 0xae10, 0x4d14, 0xae10,
+    0x4d14, 0xae10, 0x4d04, 0xcfd4, 0xe42e, 0x2826, 0xf19a, 0xa204,
+    0xe0c2, 0x0208, 0xe0c2, 0x0210, 0x845b, 0xc786, 0xe018, 0xe000,
+    0x0110, 0xe09e, 0x2117, 0x4d17, 0xe0c2, 0x020d, 0x2117, 0x4d17,
+    0xe0c2, 0x020e, 0x2117, 0x4d17, 0xe0c2, 0x020f, 0xe42e, 0xa200,
+    0xe0c2, 0x0208, 0xa202, 0xe0c2, 0x0210, 0xe0c1, 0x0041, 0xe004,
+    0x0040, 0xae10, 0xe042, 0x2a0d, 0xa809, 0xf05b, 0xe167, 0x01d8,
+    0x2117, 0x4d17, 0xe0c2, 0x0211, 0xe000, 0x4000, 0x2a0d, 0xa811,
+    0xf05b, 0xe167, 0x01da, 0x2117, 0x4d17, 0xe0c2, 0x0212, 0x845b,
+    0xc786, 0xe018, 0xe000, 0x0110, 0xe09e, 0x2117, 0x4d17, 0xe0c2,
+    0x0214, 0x2117, 0x4d17, 0xe0c2, 0x0215, 0x2117, 0x4d17, 0xe0c2,
+    0x0216, 0xe42e, 0xa202, 0xe0c2, 0x0302, 0xa202, 0xae02, 0xa902,
+    0xe0c2, 0x0312, 0xa220, 0xe0c2, 0x0313, 0x845a, 0xc786, 0xe018,
+    0xe000, 0x0110, 0xe09e, 0x2117, 0x4d17, 0xe0c2, 0x0380, 0x2117,
+    0x4d17, 0xe0c2, 0x0381, 0x2117, 0x4d17, 0xe0c2, 0x0382, 0x8459,
+    0xc786, 0xe018, 0xe000, 0x0110, 0xe09e, 0x2117, 0x4d17, 0xe0c2,
+    0x0383, 0x2117, 0x4d17, 0xe0c2, 0x0384, 0x2117, 0x4d17, 0xe0c2,
+    0x0385, 0x845b, 0xc786, 0xe018, 0xe000, 0x0110, 0xe09e, 0x2117,
+    0x4d17, 0xe0c2, 0x0386, 0x2117, 0x4d17, 0xe0c2, 0x0387, 0x2117,
+    0x4d17, 0xe0c2, 0x0388, 0xa200, 0xe0c2, 0x0302, 0xe42e, 0xcba6,
+    0xe0c2, 0x0114, 0xcba8, 0xe0c2, 0x0115, 0xcbaa, 0xe0c2, 0x012a,
+    0xcbac, 0xe0c2, 0x0117, 0xcbae, 0xe0c2, 0x0120, 0xcbb0, 0xe0c2,
+    0x0121, 0xcbb2, 0xe0c2, 0x0123, 0xe0c0, 0x0111, 0xf7e8, 0xf08c,
+    0xe0c0, 0x0124, 0xe0c2, 0x0124, 0xa200, 0xe0c2, 0x0320, 0x2abc,
+    0x281a, 0xe01a, 0xe051, 0xf2db, 0xe004, 0x03a0, 0x082c, 0xe094,
+    0xcb86, 0xa802, 0xf248, 0xcbdf, 0xaf05, 0xa803, 0xe017, 0xae1f,
+    0xe0c0, 0x03b0, 0xb616, 0x3512, 0x3d0a, 0x2902, 0xe008, 0x7fff,
+    0xe056, 0x3d12, 0x8112, 0x281a, 0xa102, 0xf11a, 0xcbdf, 0xaf1d,
+    0xa803, 0xe017, 0xae1f, 0xe0c0, 0x03c0, 0xb616, 0x3512, 0x3d0a,
+    0x2902, 0xe008, 0x7fff, 0xe056, 0x3d12, 0x8112, 0xe41e, 0x08fe,
+    0xa202, 0xe0c2, 0x0110, 0xcbc0, 0xf7f8, 0xe41e, 0x0a6b, 0xa200,
+    0xb63a, 0x2abb, 0xf07b, 0xae02, 0x4cbe, 0xae0c, 0x4c6d, 0xe41e,
+    0x08bc, 0x2864, 0xe418, 0x0de2, 0xe42e, 0xe0c0, 0x0065, 0xaf0a,
+    0xa81e, 0xe40a, 0x0db5, 0x28ba, 0xf1fa, 0xe167, 0x0300, 0xe166,
+    0x0428, 0xd022, 0x0007, 0xe184, 0x0d84, 0x2917, 0xae08, 0x4d17,
+    0xae08, 0x4d17, 0xae08, 0x4d17, 0x3d16, 0xe190, 0xe167, 0x0438,
+    0x2117, 0x4d17, 0xce20, 0xd111, 0x0428, 0xd112, 0x0008, 0xd113,
+    0x0002, 0xca28, 0xf7f8, 0xe162, 0x0436, 0xc410, 0xa200, 0x2aba,
+    0xb632, 0xae10, 0x3d12, 0xa220, 0x3d12, 0x8132, 0xa200, 0x2abb,
+    0xb652, 0xae10, 0x3d12, 0x2837, 0x582a, 0x3d12, 0x8132, 0x2abc,
+    0x281a, 0xe01a, 0xe051, 0xa200, 0xb692, 0xae10, 0x4c1a, 0x3d12,
+    0x2837, 0x582a, 0xb616, 0x3d12, 0x8132, 0xe0c0, 0x0065, 0xaf0a,
+    0xa802, 0xf12a, 0xe162, 0x0420, 0x28c4, 0x3d12, 0x28c5, 0x3d12,
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+    0xe055, 0xcfa3, 0xa201, 0xe166, 0x0584, 0x2916, 0xe008, 0x00ff,
+    0xe055, 0x2916, 0xe008, 0x00ff, 0xae10, 0xe055, 0x2916, 0xe008,
+    0x00ff, 0xae20, 0xe055, 0x2916, 0xe008, 0x00ff, 0xae30, 0xe055,
+    0xcfa5, 0xa201, 0xe166, 0x058c, 0x2916, 0xe008, 0x00ff, 0xe055,
+    0x2916, 0xe008, 0x00ff, 0xae10, 0xe055, 0x2916, 0xe008, 0x00ff,
+    0xae20, 0xe055, 0x2916, 0xe008, 0x00ff, 0xae30, 0xe055, 0xcfa7,
+    0xa201, 0xe166, 0x0588, 0x2916, 0xe008, 0x00ff, 0xe055, 0x2916,
+    0xe008, 0x00ff, 0xae10, 0xe055, 0x2916, 0xe008, 0x00ff, 0xae20,
+    0xe055, 0x2916, 0xe008, 0x00ff, 0xae30, 0xe055, 0xcfa9, 0xe005,
+    0x0080, 0xae21, 0xe00b, 0x0100, 0xcfab, 0xe005, 0x011f, 0xae21,
+    0xe004, 0x013f, 0xe055, 0xcfad, 0xe005, 0x009f, 0xae21, 0xe004,
+    0x00bf, 0xe055, 0xcfb7, 0xa200, 0xcfb0, 0xe41e, 0x0337, 0xe42e,
+    0x2885, 0xae10, 0x4c86, 0xcf06, 0xe42e, 0xa200, 0x4c82, 0xae02,
+    0x4c84, 0xae02, 0x4c81, 0xae02, 0x4c83, 0xae08, 0x3c96, 0xe42e,
+    0xe004, 0x001f, 0xae20, 0xe00a, 0x0000, 0xcf40, 0xe004, 0x0100,
+    0xcf42, 0xe005, 0x011f, 0xae21, 0xe004, 0x013f, 0xe055, 0xcf45,
+    0xe42e, 0xe004, 0x00ff, 0xae20, 0xe00a, 0x0000, 0xcf60, 0xe004,
+    0x0100, 0xcf62, 0xe005, 0x011f, 0xae21, 0xe004, 0x013f, 0xe055,
+    0xcf65, 0x2838, 0xae02, 0x4c37, 0xae04, 0xcf68, 0xe42e, 0xe004,
+    0x001f, 0xae20, 0xe00a, 0x0000, 0xcfc0, 0xe42e, 0xe004, 0x0080,
+    0x3c00, 0xe166, 0x0130, 0xe160, 0x0002, 0x2800, 0xae10, 0x4d16,
+    0xcf38, 0x2a00, 0xae07, 0xd022, 0x0004, 0xe184, 0x0356, 0xe04a,
+    0xae10, 0x8116, 0x4d0e, 0xae10, 0x4d36, 0xcf3e, 0xa003, 0xa203,
+    0x2800, 0xa806, 0xa104, 0xb655, 0x2800, 0xe042, 0x3c00, 0xaf10,
+    0xf028, 0xf64e, 0xe42e, 0xa2fe, 0x3c42, 0x3c43, 0x3c44, 0x3c45,
+    0x3c4a, 0xa200, 0x3c46, 0x3c47, 0x3c4b, 0x3c4c, 0x3c49, 0x3c48,
+    0xe0c0, 0x0061, 0x3c40, 0xe0c0, 0x0060, 0x3c41, 0xe41e, 0x0a0e,
+    0xe0c0, 0x0042, 0xce20, 0xd111, 0x0620, 0xd112, 0x00c0, 0xd113,
+    0x0003, 0xe41e, 0x0a0e, 0xa202, 0xe42e, 0xa2fc, 0x3c42, 0xe0c0,
+    0x0054, 0x3c47, 0x3446, 0xa202, 0xe42e, 0x2843, 0x3c42, 0x2842,
+    0xa002, 0x2a41, 0xe045, 0xb616, 0x3c42, 0x2a43, 0xe045, 0xf099,
+    0xa2fe, 0xe0c2, 0x0077, 0xa2fa, 0xe0c2, 0x0071, 0xa200, 0xe42e,
+    0x2a44, 0xe045, 0xf6db, 0x2a45, 0xe045, 0xf6ab, 0x2446, 0x4c47,
+    0x5c42, 0xa802, 0xf658, 0xa202, 0xe42e, 0x2843, 0x3c42, 0x2842,
+    0xa002, 0x2a41, 0xe045, 0xb616, 0x3c42, 0x2a43, 0xe045, 0xf059,
+    0xa2fe, 0x3c42, 0xa200, 0xe42e, 0x2a44, 0xe045, 0xf71b, 0x2a45,
+    0xe045, 0xf6eb, 0x2446, 0x4c47, 0x5c42, 0xa802, 0xf698, 0x2824,
+    0xf08a, 0xa202, 0x5842, 0x2646, 0x4e47, 0xe056, 0x3c47, 0x3446,
+    0xa202, 0xe42e, 0xa200, 0x3ca8, 0x3ca9, 0x2a43, 0x283a, 0xf028,
+    0x2a42, 0x3ea9, 0x2836, 0xf0fa, 0xa102, 0xf048, 0x28a9, 0x3c45,
+    0xf0ae, 0xa102, 0xf048, 0x2844, 0x3c45, 0xf05e, 0xa2fe, 0x3ca8,
+    0xa200, 0x3c45, 0x2835, 0xf0fa, 0xa102, 0xf048, 0x28a9, 0x3c44,
+    0xf0ae, 0xa102, 0xf048, 0x2845, 0x3c44, 0xf05e, 0xa2fe, 0x3ca8,
+    0xa200, 0x3c44, 0x2833, 0xf03a, 0x2842, 0x3c44, 0x2834, 0xf03a,
+    0x2842, 0x3c45, 0x283a, 0xf048, 0x2842, 0x3c4a, 0xf04e, 0x2842,
+    0x3c43, 0x3c4a, 0x2448, 0x4c49, 0xa002, 0x3c49, 0x3448, 0xa200,
+    0x2a43, 0xf045, 0xa203, 0x5a43, 0xe056, 0x2a44, 0xf045, 0xa203,
+    0x5a44, 0xe056, 0x2a45, 0xf045, 0xa203, 0x5a45, 0xe056, 0x2a42,
+    0xf045, 0xa203, 0x5a42, 0xe056, 0x344b, 0x3c4c, 0x28a8, 0xf038,
+    0xa202, 0xe42e, 0xa200, 0xe42e, 0xe0c0, 0x0041, 0xe005, 0x029c,
+    0xae11, 0xe042, 0xe41e, 0x0493, 0x3452, 0x3c53, 0xe000, 0x08a0,
+    0xe41e, 0x0493, 0x3459, 0x3c5a, 0xe000, 0x0ac0, 0xe0c0, 0x0041,
+    0xe005, 0x002c, 0xae15, 0xe042, 0xe41e, 0x0493, 0x345c, 0x3c5d,
+    0xe42e, 0xe167, 0x05b5, 0xe166, 0x0064, 0xd022, 0x0003, 0xe184,
+    0x0453, 0x9e16, 0x3517, 0x3d17, 0xe0c0, 0x006c, 0xf098, 0xe0c0,
+    0x0041, 0xe005, 0x0034, 0xae15, 0xe042, 0xe41e, 0x0493, 0x3454,
+    0x3c55, 0xe0c0, 0x0069, 0xe167, 0x0ba0, 0x3d17, 0x3517, 0xe0c0,
+    0x006a, 0x3d17, 0x3517, 0xe0c0, 0x006b, 0x3d17, 0x3517, 0xe0c0,
+    0x0042, 0xe000, 0x1000, 0xce20, 0xd111, 0x0ba8, 0xd112, 0x004c,
+    0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0050, 0xe049,
+    0xe008, 0x000f, 0x3c51, 0xaf11, 0xe009, 0x000f, 0x3e50, 0x4651,
+    0x3e51, 0xe0c0, 0x0050, 0xaf1c, 0xa802, 0xe005, 0x0ba6, 0xe09f,
+    0x3d17, 0xa202, 0xe42e, 0xa00e, 0xaf06, 0xae06, 0xe42e, 0xe41e,
+    0x04a7, 0xe40a, 0x04a5, 0xe41e, 0x04cf, 0xe40a, 0x04a5, 0xe41e,
+    0x0502, 0xe40a, 0x04a5, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xba4e,
+    0xa188, 0xf198, 0xba4e, 0xa196, 0xf168, 0xba4e, 0xa192, 0xf138,
+    0xba4e, 0xa18c, 0xf108, 0xba5e, 0xba5e, 0xba7e, 0xba5e, 0xba5e,
+    0xe41e, 0x04c4, 0x3c1a, 0xe41e, 0x04c4, 0x3c19, 0xba7e, 0xba7e,
+    0xa202, 0xe42e, 0xa200, 0xe42e, 0xba4e, 0xba4f, 0xae11, 0xe056,
+    0xba4f, 0xae21, 0xe056, 0xba4f, 0xae31, 0xe056, 0xe42e, 0xba4e,
+    0x3c00, 0xba4e, 0x3c01, 0xba4e, 0x3c02, 0xba4e, 0x3c03, 0x2803,
+    0xae10, 0x4c02, 0xae10, 0x4c01, 0xae10, 0x4c00, 0x3420, 0x3c21,
+    0xd022, 0x0007, 0xe184, 0x04e5, 0xba4e, 0xe190, 0xe190, 0xa200,
+    0xcc72, 0x3c79, 0xa202, 0xe42e, 0xe41e, 0x04cf, 0xf09a, 0xe41e,
+    0x0502, 0xf06a, 0xe41e, 0x0706, 0xf03a, 0xa202, 0xe42e, 0xa200,
+    0xe42e, 0xa202, 0x3c80, 0xe41e, 0x05b9, 0xf03a, 0xa202, 0xe42e,
+    0xa200, 0xe42e, 0xa200, 0x3c94, 0xba4e, 0xba4f, 0xae11, 0xe056,
+    0xba4f, 0xae21, 0xe055, 0xe04a, 0xa802, 0x3c22, 0xe04a, 0xaf02,
+    0xa80e, 0x3c23, 0xe04a, 0xaf08, 0xa802, 0x3c24, 0xe04a, 0xaf0a,
+    0x3425, 0x3c26, 0x2879, 0xa006, 0x3c79, 0xe41e, 0x06e2, 0x2822,
+    0xf3d8, 0x2810, 0x3ca4, 0x2811, 0x3ca5, 0xba4e, 0xe005, 0x009d,
+    0xe046, 0xe408, 0x056c, 0xba4e, 0xe005, 0x0001, 0xe046, 0xe408,
+    0x056c, 0xba4e, 0xe005, 0x002a, 0xe046, 0xe408, 0x056c, 0xba4e,
+    0xe049, 0xba4e, 0xae10, 0xe055, 0xe04a, 0xe008, 0x3fff, 0x3c10,
+    0xe04a, 0xaf1c, 0xa806, 0x3c12, 0xba4e, 0xe049, 0xba4e, 0xae10,
+    0xe055, 0xe04a, 0xe008, 0x3fff, 0x3c11, 0xe04a, 0xaf1c, 0xa806,
+    0x3c13, 0x2879, 0xa00e, 0x3c79, 0x2810, 0x18a4, 0xf07a, 0xf04e,
+    0x2811, 0x18a5, 0xf03a, 0xa202, 0x3c94, 0x2810, 0xa01e, 0xaf08,
+    0x3c14, 0x2811, 0xa01e, 0xaf08, 0x3c15, 0xcca4, 0x8214, 0xe018,
+    0x3c16, 0xf03a, 0xa202, 0xe42e, 0xa200, 0xe42e, 0x2812, 0x4c13,
+    0xf068, 0x2810, 0x3c17, 0x2811, 0x3c18, 0xe42e, 0xa202, 0x2a12,
+    0xa103, 0xb6b6, 0xa103, 0xb6b6, 0xa103, 0xb656, 0x3c00, 0xa202,
+    0x2a12, 0xa103, 0xb696, 0xa103, 0xb676, 0xa103, 0xb636, 0x3c01,
+    0xa202, 0x2a13, 0xa103, 0xb6b6, 0xa103, 0xb6b6, 0xa103, 0xb656,
+    0x3c02, 0xa202, 0x2a13, 0xa103, 0xb696, 0xa103, 0xb676, 0xa103,
+    0xb636, 0x3c03, 0x2810, 0xcca4, 0x8200, 0xe018, 0xc70f, 0x7c01,
+    0xe190, 0x3c17, 0x2811, 0xcca4, 0x8202, 0xe018, 0xc70f, 0x7c03,
+    0xe190, 0x3c18, 0xe42e, 0x2817, 0xa01e, 0xaf08, 0x1814, 0x2a18,
+    0xa01f, 0xaf09, 0x1a15, 0xf044, 0xf035, 0xa202, 0xe42e, 0xa200,
+    0xe42e, 0xe41e, 0x0147, 0x2822, 0xf068, 0xe41e, 0x0159, 0x3c27,
+    0xe41e, 0x0159, 0xe41e, 0x0159, 0x3c28, 0xf2fa, 0xe41e, 0x0159,
+    0x3c29, 0xe41e, 0x0159, 0x3c2a, 0xf1ca, 0xe41e, 0x0159, 0x3c2b,
+    0xe166, 0x0580, 0xa20e, 0x3ca6, 0xe41e, 0x072f, 0xe41e, 0x072f,
+    0xe41e, 0x072f, 0xe41e, 0x072f, 0xe166, 0x0584, 0xa20c, 0x3ca6,
+    0xe41e, 0x072f, 0xe41e, 0x072f, 0xe41e, 0x072f, 0xe41e, 0x072f,
+    0x2829, 0xf0ba, 0xe166, 0x0100, 0xa210, 0x3ca6, 0xe41e, 0x0740,
+    0xe41e, 0x0740, 0xe41e, 0x0740, 0xe41e, 0x0159, 0x3c2c, 0xa20c,
+    0xe41e, 0x0163, 0x3c2d, 0xa206, 0xe41e, 0x0163, 0x3c2e, 0xa200,
+    0x3c30, 0xe41e, 0x0159, 0x3c2f, 0xf1da, 0xe41e, 0x0159, 0x3c30,
+    0xf19a, 0xe166, 0x0588, 0xa20c, 0x3ca6, 0xe41e, 0x074c, 0xe41e,
+    0x074c, 0xe41e, 0x074c, 0xe41e, 0x074c, 0xe166, 0x058c, 0xa20c,
+    0x3ca6, 0xe41e, 0x074c, 0xe41e, 0x074c, 0xe41e, 0x074c, 0xe41e,
+    0x074c, 0xa204, 0xe41e, 0x0163, 0x3c31, 0xa202, 0x5831, 0x3c31,
+    0xe406, 0x06e0, 0xa110, 0xe400, 0x06e0, 0xa20e, 0xe41e, 0x0163,
+    0x3c32, 0xe166, 0x05b0, 0xa208, 0x3ca6, 0xe41e, 0x075c, 0xe41e,
+    0x075c, 0xe41e, 0x075c, 0xe41e, 0x075c, 0xe41e, 0x075c, 0x2822,
+    0xf1da, 0xe41e, 0x0159, 0x3c33, 0xe41e, 0x0159, 0x3c34, 0xa200,
+    0x3c35, 0x2833, 0xf058, 0xa204, 0xe41e, 0x0163, 0x3c35, 0xa200,
+    0x3c36, 0x2834, 0xf058, 0xa204, 0xe41e, 0x0163, 0x3c36, 0xe41e,
+    0x0159, 0x3c37, 0xe41e, 0x0159, 0x3c38, 0xe41e, 0x0159, 0x3c39,
+    0xf058, 0xe004, 0x0002, 0xe41e, 0x0c4a, 0x2822, 0xf048, 0xa202,
+    0x3c3a, 0xf04e, 0xe41e, 0x0159, 0x3c3a, 0xe167, 0x0130, 0xa200,
+    0x3c00, 0x2800, 0xa108, 0xf1ba, 0x2800, 0xe41e, 0x0c59, 0xe165,
+    0x0900, 0xe004, 0x0108, 0x3c01, 0x2915, 0xe41e, 0x014f, 0x2b07,
+    0xf04a, 0xe41e, 0x0189, 0xe049, 0x3f17, 0x2801, 0xa102, 0x3c01,
+    0xf748, 0xe190, 0x2800, 0xa002, 0x3c00, 0xf64e, 0xa200, 0x3c3f,
+    0xe41e, 0x0159, 0x3c3b, 0xf04a, 0xe41e, 0x0189, 0x3c3f, 0x2822,
+    0xe40a, 0x06de, 0xe41e, 0x0189, 0x3c3c, 0xe41e, 0x0189, 0x3c3d,
+    0xe41e, 0x0189, 0x3c3e, 0xe166, 0x0103, 0xe41e, 0x0159, 0xf0da,
+    0xe41e, 0x0189, 0x3d16, 0xe41e, 0x0189, 0x3d16, 0xe41e, 0x0189,
+    0x3d16, 0xe41e, 0x0189, 0x3d16, 0xe166, 0x0107, 0xe41e, 0x0159,
+    0xf0aa, 0xe41e, 0x0189, 0x3d16, 0xe41e, 0x0189, 0x3d16, 0xe41e,
+    0x0189, 0x3d16, 0xe41e, 0x0c75, 0xe165, 0x0550, 0xe166, 0x010a,
+    0xa200, 0x3c00, 0xa126, 0xf08a, 0x2915, 0xe41e, 0x076c, 0x2800,
+    0xa002, 0x3c00, 0xf78e, 0xa200, 0x3c00, 0xa126, 0xf08a, 0x2915,
+    0xe41e, 0x076c, 0x2800, 0xa002, 0x3c00, 0xf78e, 0xa202, 0xe42e,
+    0xa200, 0xe42e, 0x2823, 0xf078, 0xa201, 0x3e8e, 0x3e8f, 0x3e90,
+    0x3e91, 0xf1ce, 0xa102, 0xf088, 0xa201, 0x3e8e, 0x3e91, 0xa203,
+    0x3e8f, 0x3e90, 0xf13e, 0xa102, 0xf088, 0xa201, 0x3e8f, 0x3e91,
+    0xa203, 0x3e8e, 0x3e90, 0xf0ae, 0xa102, 0xf078, 0xa203, 0x3e8e,
+    0x3e8f, 0x3e90, 0x3e91, 0xf02e, 0xf60e, 0xe42e, 0x2822, 0xf228,
+    0xe41e, 0x0c32, 0xa200, 0x3c2b, 0xe166, 0x0580, 0xd022, 0x0007,
+    0xe184, 0x0713, 0x3d16, 0xe190, 0xe190, 0xa200, 0xe166, 0x0588,
+    0xd022, 0x0007, 0xe184, 0x071d, 0x3d16, 0xe190, 0xe190, 0xa202,
+    0x3c33, 0x3c34, 0xa200, 0x3c35, 0x3c36, 0xa200, 0x3c37, 0x3c38,
+    0xf05e, 0xa203, 0x2890, 0xb611, 0x3e8c, 0xa202, 0xe42e, 0xe41e,
+    0x0159, 0xf0ca, 0x28a6, 0xe41e, 0x0163, 0x3d06, 0xe41e, 0x0159,
+    0x2b06, 0xf02a, 0xe013, 0x3f16, 0xf03e, 0xa200, 0x3d16, 0xe42e,
+    0xe41e, 0x0159, 0xf06a, 0x28a6, 0xe41e, 0x0163, 0x3d16, 0xf04e,
+    0xe004, 0x00ff, 0x3d16, 0xe42e, 0xe41e, 0x0159, 0xf0ca, 0x28a6,
+    0xe41e, 0x0163, 0x3d06, 0xe41e, 0x0159, 0x2b06, 0xf02a, 0xe013,
+    0x3f16, 0xf02e, 0x8116, 0xe42e, 0xe41e, 0x0159, 0xf0ca, 0x28a6,
+    0xe41e, 0x0163, 0x3d06, 0xe41e, 0x0159, 0x2b06, 0xf02a, 0xe013,
+    0x3f16, 0xf02e, 0x3d16, 0xe42e, 0xe41e, 0x014f, 0x2b06, 0xf04a,
+    0xe41e, 0x0175, 0xe049, 0x3f16, 0xe42e, 0xa200, 0x3cb9, 0xa2fe,
+    0x3cba, 0xa202, 0x3c80, 0x2822, 0x3c81, 0xe016, 0x3c83, 0xa200,
+    0x3c82, 0x3c84, 0xe41e, 0x0305, 0xe41e, 0x01aa, 0xe41e, 0x0fed,
+    0xe41e, 0x01a5, 0xe41e, 0x0fe3, 0x2861, 0x4c62, 0xf03a, 0xe41e,
+    0x0bd5, 0xe41e, 0x07d5, 0xe41e, 0x0888, 0xe166, 0x0590, 0x2831,
+    0xa102, 0xf0fa, 0xa102, 0xcc44, 0xe184, 0x07a7, 0xba4e, 0xe049,
+    0xba4e, 0xae10, 0xe055, 0xba4e, 0xae20, 0xe055, 0x3716, 0x3f16,
+    0xe190, 0xa200, 0x3c80, 0x3c83, 0x3c81, 0xa202, 0x3c82, 0x3c84,
+    0xe41e, 0x0305, 0xe41e, 0x0278, 0x2831, 0xf15a, 0xa102, 0xf098,
+    0xe41e, 0x08ac, 0xe41e, 0x01a5, 0xe41e, 0x07f9, 0xa202, 0xe42e,
+    0xe41e, 0x08c4, 0xe41e, 0x08ac, 0xe41e, 0x01a5, 0xe41e, 0x0800,
+    0xa202, 0xe42e, 0xa200, 0xe42e, 0x2822, 0xe016, 0x4c33, 0x4c34,
+    0xf03a, 0x2832, 0x3c8d, 0xa202, 0xe42e, 0xa2fe, 0x3c87, 0xa200,
+    0x3c86, 0x3cbb, 0xe16a, 0xa200, 0x3c85, 0x2a87, 0xa003, 0x3e87,
+    0xe41e, 0x0aa7, 0xf0fd, 0x2885, 0xa002, 0x3c85, 0x1814, 0xf764,
+    0x2886, 0xa002, 0x3c86, 0x1815, 0xf6f4, 0xe41e, 0x0ad4, 0xa202,
+    0xe42e, 0x2887, 0x3cba, 0x2a16, 0xe045, 0x3ebb, 0xe16a, 0xa200,
+    0xe42e, 0xe41e, 0x0147, 0xe41e, 0x084d, 0xe41a, 0x0870, 0xe42e,
+    0xa2fe, 0x3c87, 0xa200, 0x3c86, 0x3c85, 0x3c9e, 0xe16a, 0x2886,
+    0x2a31, 0xa103, 0xe052, 0x3c9e, 0x2886, 0x1831, 0xf072, 0x2886,
+    0xe418, 0x0dfb, 0xe41e, 0x0147, 0xf09e, 0xe41e, 0x0e2e, 0xe41e,
+    0x014b, 0xe004, 0x0011, 0xe41e, 0x0e41, 0xe41e, 0x0834, 0xf10d,
+    0xe41e, 0x0e1d, 0xe004, 0x0010, 0xe41e, 0x0e41, 0x2886, 0xa002,
+    0x3c86, 0x1815, 0xf5d4, 0xe41e, 0x0ad4, 0xa202, 0xe42e, 0xe41e,
+    0x0870, 0xe16a, 0xa200, 0xe42e, 0x2880, 0xf158, 0xa200, 0x3c85,
+    0x28ba, 0x2a87, 0xa003, 0x3e87, 0xf044, 0x2887, 0x18ba, 0xf0b2,
+    0xe41e, 0x0aa7, 0xf08d, 0x2885, 0xa002, 0x3c85, 0x1814, 0xf714,
+    0xa202, 0xe42e, 0xe16b, 0xa200, 0xe42e, 0xa2fe, 0x3c87, 0xa200,
+    0x3c86, 0xe16a, 0xa200, 0x3c85, 0x28ba, 0x2a87, 0xa003, 0x3e87,
+    0xf044, 0x2887, 0x18ba, 0xf122, 0xe41e, 0x0aa7, 0xf0fd, 0x2885,
+    0xa002, 0x3c85, 0x1814, 0xf714, 0x2886, 0xa002, 0x3c86, 0x1815,
+    0xf6a4, 0xe41e, 0x0ad4, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e,
+    0xe16a, 0xe41e, 0x0ae9, 0xf12d, 0x2885, 0xa002, 0x3c85, 0x1814,
+    0x2a87, 0xa003, 0x3e87, 0xf764, 0xa200, 0x3c85, 0x2886, 0xa002,
+    0x3c86, 0x1815, 0xf6f4, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e,
+    0xa200, 0x2625, 0x4e26, 0xe042, 0x2e79, 0xe042, 0xae06, 0xc873,
+    0xe045, 0xf191, 0xc873, 0xe046, 0xe049, 0xf13a, 0xaf0a, 0xa102,
+    0xf0b4, 0xcc44, 0xe184, 0x08a1, 0xba4e, 0xba4e, 0xe190, 0xba4e,
+    0xba4e, 0xe190, 0xe190, 0xe04a, 0xa83e, 0xf03a, 0xe09c, 0x9206,
+    0xa202, 0xe42e, 0xa200, 0xe42e, 0xa200, 0x2625, 0x4e26, 0xe042,
+    0x2e79, 0xe042, 0x2a31, 0xa103, 0xf0e5, 0xf04b, 0xcca5, 0xc783,
+    0xe01c, 0xae06, 0xc873, 0xe045, 0xf061, 0xc873, 0xe046, 0xe40e,
+    0x0894, 0xe190, 0xa200, 0xe42e, 0xe166, 0x0590, 0xe167, 0x05a0,
+    0xa200, 0x2625, 0x4e26, 0xe042, 0x2e79, 0xe042, 0x2a31, 0xa111,
+    0xf151, 0x2a31, 0xa103, 0xf127, 0xcca5, 0xc783, 0xe01c, 0x3517,
+    0x3d17, 0x2a31, 0xa103, 0xa103, 0xcc45, 0xe184, 0x08e3, 0x2716,
+    0x4f16, 0xe042, 0x3517, 0x3d17, 0xe190, 0xa202, 0xe42e, 0xa200,
+    0xe0c2, 0x0074, 0xe0c2, 0x0076, 0xe0c2, 0x0077, 0x2819, 0xa102,
+    0xb608, 0xae20, 0x4c1a, 0xe0c2, 0x0072, 0xa2fe, 0xe0c2, 0x006c,
+    0xa20a, 0xe0c2, 0x0073, 0x2010, 0x4c11, 0xe0c2, 0x0071, 0x2823,
+    0xe0c2, 0x007b, 0xe41e, 0x095e, 0xe0c2, 0x0075, 0x2895, 0xe0c2,
+    0x0070, 0xa202, 0xe42e, 0xa200, 0xe0c2, 0x0075, 0xe0c2, 0x0078,
+    0xe0c2, 0x0079, 0xe0c2, 0x0072, 0x2842, 0x2a70, 0xb7d2, 0xe0c2,
+    0x0077, 0x2842, 0xe049, 0xa003, 0xb7b6, 0x2a24, 0xb7b6, 0x2a70,
+    0xb7f2, 0x2a61, 0x4e62, 0x4670, 0xb7f2, 0xe0c2, 0x0071, 0x2446,
+    0x4c47, 0xe0c2, 0x0054, 0x2014, 0x4c15, 0xae08, 0xe0c2, 0x006f,
+    0x2448, 0x4c49, 0xe0c2, 0x0070, 0x28bb, 0xe0c2, 0x0072, 0x2822,
+    0xa802, 0xe0c2, 0x0073, 0xe41e, 0x095e, 0xe0c2, 0x007c, 0xa200,
+    0x2a44, 0xe009, 0x00ff, 0xe056, 0xae10, 0x2a45, 0xe009, 0x00ff,
+    0xe056, 0xae10, 0x2a43, 0xe009, 0x00ff, 0xe056, 0xae0e, 0x4c23,
+    0xae02, 0x4c24, 0xe0c2, 0x007a, 0x2888, 0xae02, 0x2a42, 0xb626,
+    0x2a70, 0xb632, 0xe0c2, 0x0076, 0xa202, 0xe42e, 0x2812, 0xae04,
+    0x4c13, 0xae1c, 0x4c10, 0xae1c, 0x4c11, 0xe42e, 0x22f0, 0x4ef1,
+    0xa200, 0xc401, 0xe188, 0x07ff, 0x3d11, 0x36f0, 0x3ef1, 0xcc4a,
+    0xcc4c, 0xd130, 0x0007, 0xd04b, 0x0001, 0xd04c, 0x0000, 0xd008,
+    0x0000, 0xd03a, 0x0000, 0xe41e, 0x0a11, 0xe41e, 0x042c, 0xe41e,
+    0x0d39, 0xa100, 0xf0fa, 0xe41e, 0x0497, 0xa100, 0xf0ba, 0xe41e,
+    0x056e, 0x2822, 0xf078, 0xa202, 0x3c95, 0xe41e, 0x0d39, 0xe41e,
+    0x04a7, 0xe41e, 0x08e7, 0xe41e, 0x0ea1, 0xe41e, 0x0fc8, 0xe42e,
+    0xe42e, 0xd130, 0x0007, 0xe41e, 0x0363, 0xe41e, 0x0449, 0xe41e,
+    0x0b8e, 0xe42e, 0xa200, 0xcc44, 0xcc4a, 0xcc4c, 0x3c20, 0x3c21,
+    0x3c88, 0xd130, 0x0007, 0xd008, 0x0000, 0xd03a, 0x0000, 0xe0c0,
+    0x0065, 0xa808, 0xe01a, 0xe0c1, 0x0065, 0xa831, 0xa111, 0xe017,
+    0xe056, 0x3c6e, 0xe41e, 0x0385, 0xe41e, 0x038d, 0xe42a, 0x2870,
+    0xe41a, 0x0d57, 0xe41e, 0x047d, 0xe41e, 0x0c8d, 0xe41e, 0x0fcd,
+    0xe41e, 0x0b95, 0xe41e, 0x118e, 0xe41e, 0x0dc7, 0x3c70, 0x2870,
+    0xf298, 0xe41e, 0x0a1e, 0xe41e, 0x04ec, 0xf24a, 0xe41e, 0x0a1e,
+    0x2870, 0xf208, 0xe41e, 0x05ab, 0xf1da, 0xe41e, 0x0a1e, 0xe41e,
+    0x04f9, 0xf18a, 0xe41e, 0x0a1e, 0x2839, 0xe418, 0x0a16, 0x286e,
+    0x4422, 0xf02a, 0xf0fe, 0xf0e8, 0xe41e, 0x0a1e, 0xe41e, 0x03ad,
+    0xf09a, 0xe41e, 0x0a1e, 0xe41e, 0x0775, 0xe41e, 0x03d2, 0xe41e,
+    0x0a1a, 0xe41e, 0x07cc, 0xe41e, 0x0ca2, 0xe41e, 0x1083, 0xe41e,
+    0x0bb2, 0xe41e, 0x090b, 0x2842, 0xa002, 0xe418, 0x0ea7, 0xc84a,
+    0xc84d, 0xae20, 0xe056, 0xe0c2, 0x0053, 0xe42e, 0xca28, 0xf7f8,
+    0xe42e, 0xe41e, 0x0c32, 0xe41e, 0x115e, 0xe42e, 0xa204, 0xe41e,
+    0x0c4a, 0xe42e, 0xa206, 0xe41e, 0x0c4a, 0xe42e, 0x2888, 0xa002,
+    0x3c88, 0xe42e, 0xa224, 0xe41e, 0x0a57, 0xe41e, 0x0a8c, 0xa204,
+    0xe41e, 0x0a41, 0xe42e, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100,
+    0xa206, 0xe41e, 0x0a41, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100,
+    0xe0c0, 0x005b, 0x3cef, 0xa226, 0xe41e, 0x0a57, 0xe41e, 0x0a71,
+    0xe42e, 0x3ced, 0xe0c0, 0x0041, 0xe005, 0x0280, 0xae11, 0xe042,
+    0x22f0, 0x4ef1, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0000,
+    0xd112, 0x0c00, 0x88ed, 0x0113, 0xca28, 0xf7f8, 0xe42e, 0x2aef,
+    0xa80f, 0xa10d, 0xe42b, 0x3ced, 0xe0c0, 0x0041, 0xe005, 0x0298,
+    0xae11, 0xe042, 0x22f0, 0x4ef1, 0xe042, 0xca29, 0xf7f9, 0xce20,
+    0xd111, 0x0000, 0xd112, 0x0100, 0x88ed, 0x0113, 0xca28, 0xf7f8,
+    0xe42e, 0xe161, 0x07e0, 0x8911, 0x0034, 0x8911, 0x0033, 0x8911,
+    0x0035, 0x8911, 0x0036, 0x8911, 0x0037, 0x8911, 0x0038, 0x2111,
+    0x4d11, 0xcc60, 0x2111, 0x4d11, 0xcc62, 0x2111, 0x4d11, 0xcc64,
+    0x2111, 0x4d11, 0xcc72, 0xe42e, 0xe161, 0x07e0, 0x8b11, 0x0034,
+    0x8b11, 0x0033, 0x8b11, 0x0035, 0x8b11, 0x0036, 0x8b11, 0x0037,
+    0x8b11, 0x0038, 0xc860, 0x3511, 0x3d11, 0xc862, 0x3511, 0x3d11,
+    0xc864, 0x3511, 0x3d11, 0xc872, 0x3511, 0x3d11, 0xe42e, 0xcb05,
+    0xe009, 0x2222, 0x2885, 0xae10, 0x4c86, 0xcf06, 0xf058, 0xe16a,
+    0xe41e, 0x0afb, 0xf0ae, 0xf03b, 0xe41e, 0x0b0d, 0xcb05, 0xaf21,
+    0xa803, 0xf03b, 0xe41e, 0x0b50, 0x2896, 0xa908, 0xcf02, 0x2896,
+    0xa902, 0xcf02, 0x2a80, 0xcb02, 0xa802, 0xf7e8, 0xe429, 0xcb04,
+    0xaf14, 0xa802, 0xf7da, 0xe41e, 0x108f, 0xe41e, 0x10e5, 0x2a6a,
+    0x4e6b, 0xe419, 0x0ce1, 0xe42e, 0x2880, 0xcb05, 0xe009, 0x2222,
+    0xf07a, 0xf03b, 0xe41e, 0x0b0d, 0xe41e, 0x0b36, 0xe42e, 0xcb05,
+    0xaf21, 0xa803, 0xf03b, 0xe41e, 0x0b50, 0x2892, 0xe418, 0x0b74,
+    0xe42e, 0x2885, 0xae10, 0x4c86, 0xcf06, 0x2896, 0xa908, 0xcf02,
+    0x2896, 0xa906, 0xcf02, 0xcb02, 0xa802, 0xf7e8, 0xe41e, 0x108f,
+    0xe41e, 0x10e5, 0xe42e, 0x2a80, 0xa200, 0x3c56, 0x3c97, 0x3c5b,
+    0x3c98, 0xf0b9, 0xe41e, 0x0b1c, 0xe41e, 0x0b1c, 0x2892, 0xf058,
+    0xe41e, 0x0b5a, 0xe41e, 0x0b5a, 0xe42e, 0x3eaa, 0x2880, 0xa845,
+    0xf05a, 0xf03b, 0xe41e, 0x0b36, 0xe42e, 0x2aaa, 0xe009, 0x0200,
+    0xf03b, 0xe41e, 0x0b1c, 0xe42e, 0x2054, 0x4c55, 0x2e56, 0xae11,
+    0xe042, 0xca29, 0xf7f9, 0xce20, 0x2a97, 0xe004, 0x0100, 0xf03b,
+    0xe004, 0x0120, 0xce22, 0xd112, 0x0020, 0xd113, 0x0019, 0x2897,
+    0xaa02, 0x3c97, 0x2c56, 0xa002, 0x3c56, 0xe42e, 0x2054, 0x4c55,
+    0x2e56, 0xae11, 0xe042, 0xca29, 0xf7f9, 0xce20, 0x2a97, 0xe004,
+    0x0100, 0xf03b, 0xe004, 0x0120, 0xce22, 0xd112, 0x0020, 0xd113,
+    0x0018, 0x2897, 0xaa02, 0x3c97, 0x2c56, 0xa002, 0x3c56, 0xe42e,
+    0x2880, 0xf088, 0x2892, 0xf04a, 0xe41e, 0x0b74, 0xe42e, 0xe41e,
+    0x0b5a, 0xe42e, 0x2059, 0x4c5a, 0x2e5b, 0xae11, 0xe042, 0xca29,
+    0xf7f9, 0xce20, 0x2a98, 0xe004, 0x0080, 0xf03b, 0xe004, 0x00a0,
+    0xce22, 0xd112, 0x0020, 0xd113, 0x0019, 0x2898, 0xaa02, 0x3c98,
+    0x2c5b, 0xa002, 0x3c5b, 0xe42e, 0x2059, 0x4c5a, 0x2e5b, 0xae11,
+    0xe042, 0xca29, 0xf7f9, 0xce20, 0x2a98, 0xe004, 0x0080, 0xf03b,
+    0xe004, 0x00a0, 0xce22, 0xd112, 0x0020, 0xd113, 0x0018, 0x2898,
+    0xaa02, 0x3c98, 0x2c5b, 0xa002, 0x3c5b, 0xe42e, 0xa2fe, 0x3c63,
+    0xa200, 0x3c61, 0x3c62, 0xa202, 0xe42e, 0xe0c0, 0x0060, 0xa81e,
+    0x3c60, 0x2863, 0xf084, 0xe0c0, 0x0060, 0xaf08, 0x3061, 0xaf02,
+    0x3062, 0xf04e, 0xa200, 0x3c61, 0x3c62, 0xa200, 0x3c67, 0x3c68,
+    0x2814, 0xe008, 0x007f, 0x3c65, 0x2815, 0xe008, 0x007f, 0x3c66,
+    0xa202, 0xe42e, 0x2861, 0x4c62, 0xf1ba, 0x2867, 0x4c68, 0xe41e,
+    0x0bd5, 0x2868, 0x1866, 0xf062, 0xe41e, 0x0c0e, 0xe41e, 0x0c24,
+    0xf79e, 0xe0c0, 0x014b, 0xf7e8, 0xa204, 0xae1c, 0xe0c2, 0x014d,
+    0xa202, 0xe0c2, 0x014a, 0xe190, 0xe0c0, 0x014b, 0xf7e8, 0x2824,
+    0x2a42, 0xb7f5, 0x3e63, 0xa202, 0xe42e, 0x8463, 0xc786, 0xe018,
+    0xe000, 0x0620, 0xe09e, 0x2117, 0x4d17, 0xe0c2, 0x0143, 0x2117,
+    0x4d17, 0xe0c2, 0x0144, 0x2117, 0x4d17, 0xe0c2, 0x0145, 0xe0c0,
+    0x0061, 0xe0c2, 0x0146, 0xe0c0, 0x0062, 0xe0c2, 0x0147, 0xe0c0,
+    0x0063, 0xe0c2, 0x0148, 0xa200, 0x3c64, 0xe0c2, 0x0140, 0xe0c2,
+    0x0149, 0x2840, 0xe0c2, 0x0141, 0xe0c0, 0x0064, 0xe0c2, 0x014c,
+    0x2865, 0xa102, 0xae20, 0x4c66, 0xa102, 0xe0c2, 0x0142, 0xa200,
+    0xae08, 0x4c60, 0xe0c2, 0x014e, 0xa202, 0xe42e, 0x2a68, 0x1a66,
+    0x2867, 0xae0e, 0x4c68, 0xe423, 0xa203, 0xb615, 0x3eab, 0x2a64,
+    0xae03, 0x4eab, 0xae03, 0xa903, 0xae1d, 0xe056, 0xe0c1, 0x014b,
+    0xf7e9, 0xe0c2, 0x014d, 0xe42e, 0xa202, 0xe0c2, 0x014a, 0x2a67,
+    0xa003, 0x3e67, 0x1a65, 0xf065, 0x2a68, 0xa003, 0x3e68, 0xa201,
+    0x3e67, 0xe42e, 0xa200, 0xe0c1, 0x0040, 0xe042, 0xe005, 0x0036,
+    0xae17, 0xe042, 0xe005, 0x1500, 0xae03, 0xe042, 0xca29, 0xf7f9,
+    0xce20, 0xd111, 0x0100, 0xd112, 0x0450, 0xd113, 0x0003, 0xca28,
+    0xf7f8, 0xe42e, 0x3ca0, 0x2052, 0x4c53, 0xca29, 0xf7f9, 0xce20,
+    0xd111, 0x0100, 0xd112, 0x0450, 0x28a0, 0xce26, 0xca28, 0xf7f8,
+    0xe42e, 0xcca4, 0xe182, 0x0108, 0xe018, 0xae02, 0xe0c1, 0x0040,
+    0xe042, 0xe005, 0x0036, 0xae17, 0xe042, 0xe005, 0x1950, 0xae03,
+    0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0900, 0xd112, 0x0108,
+    0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e, 0xa200, 0xe0c1, 0x0040,
+    0xe042, 0xe005, 0x0036, 0xae17, 0xe042, 0xe005, 0x1e50, 0xae03,
+    0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0550, 0xd112, 0x0028,
+    0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0065, 0xaf0c,
+    0x306b, 0xaf02, 0x306a, 0xaf02, 0x3069, 0xe0c0, 0x006a, 0x346c,
+    0x3c6d, 0x2869, 0x4c6a, 0x4c6b, 0xf04a, 0xa206, 0xe41e, 0x0ce9,
+    0xa202, 0xe42e, 0x2869, 0x4c6a, 0x4c6b, 0xf3aa, 0x2869, 0xe166,
+    0x07c8, 0xa201, 0x3f06, 0xf0aa, 0xe166, 0x07c8, 0xa202, 0xae10,
+    0x3d16, 0xa220, 0x3d16, 0xe41e, 0x0cf8, 0x286a, 0xe166, 0x07cc,
+    0xa201, 0x3f06, 0xf0ca, 0xe166, 0x07cc, 0xa200, 0x2a42, 0xb646,
+    0xae10, 0x3d16, 0x8414, 0x8215, 0xe018, 0x3d16, 0x286b, 0xe166,
+    0x07d0, 0xa201, 0x3f06, 0xf11a, 0xe166, 0x07d0, 0xa200, 0x2a42,
+    0xb686, 0x2a22, 0xb616, 0xae10, 0xa002, 0x3d16, 0x8414, 0x8215,
+    0xe018, 0x2a22, 0xb616, 0x3d16, 0xa204, 0xe41e, 0x0ce9, 0xa202,
+    0xe42e, 0x286a, 0xe418, 0x0d37, 0x2822, 0x446b, 0xe418, 0x0d38,
+    0xe42e, 0x3ca0, 0xe41e, 0x0a0e, 0x246c, 0x4c6d, 0xce20, 0xd111,
+    0x07c8, 0xa218, 0xce24, 0x28a0, 0xce26, 0xe41e, 0x0a0e, 0xe42e,
+    0xe166, 0x07c0, 0xa200, 0xc707, 0x3d16, 0xe166, 0x07c0, 0xa200,
+    0x3ca7, 0x2841, 0xf256, 0xa006, 0xaf04, 0xa102, 0xcc44, 0xe184,
+    0x0d26, 0xa200, 0xae08, 0x2646, 0x4e47, 0x5ea7, 0xa803, 0xb492,
+    0x2a43, 0x1aa7, 0xe017, 0x3e00, 0x2a44, 0x1aa7, 0xe017, 0x4e00,
+    0x3e00, 0x2a45, 0x1aa7, 0xe017, 0x4e00, 0xb452, 0x2a42, 0x1aa7,
+    0xb436, 0x2aa7, 0xa003, 0x3ea7, 0xa807, 0xf659, 0x3d16, 0xe41e,
+    0x0a0e, 0xe166, 0x07ca, 0x2516, 0x4d16, 0xce20, 0xd111, 0x07c0,
+    0xd112, 0x0008, 0xd113, 0x0002, 0xe41e, 0x0a0e, 0xe42e, 0xe42e,
+    0xe42e, 0xe0c0, 0x0060, 0x3457, 0x3c58, 0xe0c1, 0x0061, 0xae15,
+    0x3677, 0x3e78, 0xe042, 0x347e, 0x3c7f, 0xe0c0, 0x0048, 0x347c,
+    0x3c7d, 0xe41e, 0x0ef8, 0x247c, 0x4c7d, 0xe41e, 0x0f61, 0xe41e,
+    0x0dde, 0xe41e, 0x0dc9, 0xa200, 0x3c79, 0xa202, 0xe42e, 0xe0c0,
+    0x0048, 0x347c, 0x3c7d, 0xe41e, 0x0ebf, 0xf0d8, 0x247c, 0x4c7d,
+    0xe41e, 0x0f61, 0xe41e, 0x0dde, 0xe41e, 0x0dc9, 0xa200, 0x3c79,
+    0xa202, 0xe42e, 0xe16a, 0xa202, 0xe42e, 0xe41e, 0x0d70, 0xe470,
+    0xca28, 0xf7f8, 0xe004, 0x0200, 0x3c7a, 0xaf04, 0xce24, 0x2871,
+    0xae0e, 0xce22, 0x2672, 0x4e73, 0xce21, 0x247e, 0x4c7f, 0xe046,
+    0xe002, 0x0200, 0xf062, 0xe000, 0x0200, 0x3c7a, 0xaf04, 0xce24,
+    0xe0c0, 0x0043, 0xa806, 0xae02, 0xa022, 0xce26, 0x2472, 0x4c73,
+    0x087a, 0x3472, 0x3c73, 0x147e, 0x1c7f, 0xf054, 0x2457, 0x4c58,
+    0x3472, 0x3c73, 0xca28, 0xf7f8, 0x287a, 0xe002, 0x0200, 0xf212,
+    0x287a, 0xaf04, 0x2a71, 0xae0f, 0xe042, 0xce22, 0x287a, 0xe005,
+    0x0200, 0xe045, 0x3e7a, 0x2472, 0x4c73, 0xce20, 0x287a, 0xaf04,
+    0xce24, 0xe0c0, 0x0043, 0xa806, 0xae02, 0xa022, 0xce26, 0x2472,
+    0x4c73, 0x087a, 0x3472, 0x3c73, 0xca28, 0xf7f8, 0xd04c, 0x0000,
+    0x2871, 0xae0e, 0xcc6e, 0x2871, 0xe016, 0x3c71, 0xe42e, 0x28c1,
+    0xe42e, 0xa200, 0x3c71, 0xe41e, 0x0d70, 0xe41e, 0x0d70, 0xe128,
+    0x2876, 0xa80e, 0xa102, 0xf074, 0xcc44, 0xe184, 0x0dd8, 0xba4e,
+    0xe190, 0xe190, 0xd071, 0x2020, 0xe181, 0xe42e, 0xd030, 0x0000,
+    0xd031, 0x0000, 0xd032, 0x0000, 0xd034, 0x0000, 0xd033, 0x0000,
+    0xd035, 0x0000, 0xd036, 0x00ff, 0xd037, 0x0000, 0xd038, 0x0000,
+    0xd039, 0x0000, 0xd04b, 0x0001, 0xd04c, 0x0000, 0xd046, 0x0000,
+    0xd047, 0x0000, 0xe42e, 0xe004, 0x05a0, 0x2a9e, 0xae03, 0xe042,
+    0xe09c, 0x2516, 0x4d16, 0x267c, 0x4e7d, 0xa019, 0xe042, 0xe049,
+    0xa80e, 0xe045, 0x3672, 0x3e73, 0x3c76, 0x2472, 0x4c73, 0x267e,
+    0x4e7f, 0xe045, 0xf061, 0x2677, 0x4e78, 0xe046, 0x3472, 0x3c73,
+    0xe41e, 0x0dde, 0xe41e, 0x0dc9, 0xe42e, 0xe004, 0x08c0, 0x2a9e,
+    0xae05, 0xe042, 0xe09c, 0x2072, 0x4c73, 0x3516, 0x3d16, 0x2876,
+    0x3d16, 0x2871, 0x3d16, 0xe41e, 0x0e53, 0xe42e, 0xe41e, 0x0dde,
+    0xe004, 0x08c0, 0x2a9e, 0xae05, 0xe042, 0xe09c, 0x2116, 0x4d16,
+    0x3472, 0x3c73, 0x2916, 0x3c76, 0x2916, 0x3c71, 0xe41e, 0x0e79,
+    0xe42e, 0x3ca0, 0xca29, 0xf7f9, 0xd111, 0x0000, 0x289e, 0xae14,
+    0x265c, 0x4e5d, 0xe042, 0xce20, 0xd112, 0x0100, 0x28a0, 0xce26,
+    0xca29, 0xf7f9, 0xe42e, 0xe004, 0x0800, 0x2a9e, 0xcca5, 0xc798,
+    0xe01c, 0xe09c, 0xc860, 0x3516, 0x3d16, 0xc862, 0x3516, 0x3d16,
+    0xc864, 0x3516, 0x3d16, 0xc866, 0x3d16, 0xc868, 0x3d16, 0xc86a,
+    0x3d16, 0xc86c, 0x3d16, 0xc86e, 0x3d16, 0xc870, 0x3d16, 0xc872,
+    0x3516, 0x3d16, 0xc88c, 0x3516, 0x3d16, 0xcb20, 0x3516, 0x3d16,
+    0xe42e, 0xe004, 0x0800, 0x2a9e, 0xcca5, 0xc798, 0xe01c, 0xe09c,
+    0x2116, 0x4d16, 0xcc60, 0x2116, 0x4d16, 0xcc62, 0x2116, 0x4d16,
+    0xcc64, 0x2916, 0xcc66, 0x2916, 0xcc68, 0x2916, 0xcc6a, 0x2916,
+    0xcc6c, 0x2916, 0xcc6e, 0x2916, 0xcc70, 0x2116, 0x4d16, 0xcc72,
+    0x2116, 0x4d16, 0xcc8c, 0x2116, 0x4d16, 0xaf08, 0xae08, 0xcf20,
+    0xe42e, 0x247c, 0x4c7d, 0x08c2, 0x347c, 0x3c7d, 0xf09e, 0x247c,
+    0x4c7d, 0xa018, 0x2620, 0x4e21, 0xe042, 0x347c, 0x3c7d, 0x267e,
+    0x4e7f, 0xe045, 0xf081, 0x247c, 0x4c7d, 0x2677, 0x4e78, 0xe046,
+    0x347c, 0x3c7d, 0x247c, 0x4c7d, 0xe0c2, 0x0048, 0xe42e, 0x247c,
+    0x4c7d, 0x3472, 0x3c73, 0xa219, 0x36c3, 0x3ec4, 0xd027, 0x0000,
+    0xe41e, 0x0f92, 0xd027, 0x0001, 0xf2a8, 0x247c, 0x4c7d, 0xe41e,
+    0x0f61, 0xe41e, 0x0f68, 0x2876, 0xaf02, 0xe000, 0x0700, 0xe092,
+    0x2876, 0xa802, 0xe41e, 0x0f30, 0x3420, 0x3c21, 0xf186, 0x2677,
+    0x4e78, 0xe046, 0xf142, 0x247c, 0x4c7d, 0x3472, 0x3c73, 0x2620,
+    0x4e21, 0xa019, 0x36c3, 0x3ec4, 0xd027, 0x0000, 0xe41e, 0x0f92,
+    0xd027, 0x0001, 0xf048, 0xa200, 0xe42e, 0xe16b, 0xa202, 0xe42e,
+    0x247c, 0x4c7d, 0x3472, 0x3c73, 0xa241, 0x36c3, 0x3ec4, 0xd027,
+    0x0000, 0xe41e, 0x0f92, 0xd027, 0x0001, 0xe408, 0x0f2e, 0x247c,
+    0x4c7d, 0xe41e, 0x0f61, 0xe41e, 0x0f68, 0x2876, 0xa00c, 0xaf02,
+    0xe000, 0x0700, 0xe092, 0x2876, 0xa802, 0xe41e, 0x0f30, 0xe008,
+    0xffff, 0x3cc2, 0xa140, 0xf124, 0x247c, 0x4c7d, 0x3472, 0x3c73,
+    0x2ac2, 0xa02d, 0x36c3, 0x3ec4, 0xd027, 0x0000, 0xe41e, 0x0f92,
+    0xd027, 0x0001, 0xf048, 0xa200, 0xe42e, 0xe16b, 0xa202, 0xe42e,
+    0xf0a8, 0x2911, 0xe008, 0xffff, 0xae20, 0x2b11, 0xe009, 0xffff,
+    0xe042, 0xf0fe, 0x2911, 0xe008, 0x00ff, 0xae20, 0x2b11, 0xe009,
+    0xffff, 0xe042, 0xae10, 0x2b11, 0xe009, 0xff00, 0xaf11, 0xe042,
+    0xe049, 0xaf31, 0xe009, 0x00ff, 0xe093, 0xe049, 0xaf21, 0xe009,
+    0x00ff, 0xe095, 0xe049, 0xaf11, 0xe009, 0x00ff, 0xe008, 0x00ff,
+    0xae10, 0xe056, 0xae10, 0xe085, 0xe056, 0xae10, 0xe083, 0xe056,
+    0xe42e, 0xe049, 0xa80e, 0xe045, 0x3672, 0x3e73, 0x3c76, 0xe42e,
+    0xca28, 0xf7f8, 0xd111, 0x0700, 0x2472, 0x4c73, 0xce20, 0x267e,
+    0x4e7f, 0xe045, 0xe004, 0x0040, 0xe065, 0xaf03, 0xce25, 0xe41e,
+    0x0f89, 0xa240, 0xca25, 0xe046, 0xe426, 0xca28, 0xf7f8, 0xce24,
+    0xe000, 0x0700, 0xce22, 0x2657, 0x4e58, 0xce20, 0xe41e, 0x0f89,
+    0xe42e, 0xe0c0, 0x0043, 0xa806, 0xae02, 0xa002, 0xce26, 0xca28,
+    0xf7f8, 0xe42e, 0xa200, 0x3cc0, 0xe0c0, 0x0045, 0xaf04, 0x307b,
+    0x28c0, 0xf09a, 0xe0c0, 0x0049, 0x2674, 0x4e75, 0xe046, 0xf75a,
+    0xa200, 0x3cc0, 0xe0c0, 0x0049, 0x3474, 0x3c75, 0x2474, 0x4c75,
+    0x2672, 0x4e73, 0xe046, 0xf032, 0x0077, 0x0c78, 0x26c3, 0x4ec4,
+    0xe045, 0xa200, 0xe427, 0x287b, 0x3cc1, 0xe428, 0x28c0, 0xf5d8,
+    0xe0c0, 0x005c, 0xe008, 0x4000, 0xf58a, 0xe0c0, 0x005d, 0xe00a,
+    0x4000, 0xe0c2, 0x005d, 0xa202, 0xce00, 0x3cc0, 0xf4ee, 0xe42e,
+    0xe0c0, 0x0048, 0xe0c2, 0x0046, 0xe42e, 0xa20e, 0xa940, 0xe0c2,
+    0x0100, 0xa200, 0xe0c2, 0x013d, 0xe004, 0x00ce, 0xe0c2, 0x017c,
+    0xa218, 0xe0c2, 0x017d, 0xe0c0, 0x0044, 0xa80e, 0xae1a, 0x4c40,
+    0xe0c2, 0x0102, 0xe42e, 0xa202, 0xe0c2, 0x0106, 0xa201, 0xe167,
+    0x0ba7, 0x3f17, 0xe41e, 0x11a9, 0xe42e, 0xa20e, 0xa940, 0xe0c2,
+    0x0100, 0xa200, 0xe0c2, 0x013d, 0xe004, 0x00ce, 0xe0c2, 0x017c,
+    0xa218, 0xe0c2, 0x017d, 0xe0c1, 0x0041, 0xe004, 0x0000, 0xae10,
+    0xe042, 0x2a50, 0xa805, 0xf05b, 0xe161, 0x05b7, 0x2111, 0x4d11,
+    0xe0c2, 0x0103, 0xa202, 0xe0c2, 0x0210, 0xe0c1, 0x0041, 0xe004,
+    0x0030, 0xae10, 0xe042, 0x2a50, 0xa809, 0xf05b, 0xe161, 0x05b9,
+    0x2111, 0x4d11, 0xe0c2, 0x0211, 0xe0c1, 0x0041, 0xe004, 0x0030,
+    0xe000, 0x0040, 0xae10, 0xe042, 0x2a50, 0xa811, 0xf05b, 0xe161,
+    0x05bb, 0x2111, 0x4d11, 0xe0c2, 0x0212, 0x2014, 0x4c15, 0xae08,
+    0xe0c2, 0x0101, 0xe0c2, 0x0283, 0xe0c0, 0x0044, 0xa80e, 0xae1a,
+    0x4c40, 0xe0c2, 0x0102, 0x2822, 0xa802, 0xae06, 0xe0c2, 0x0104,
+    0xa20e, 0xae04, 0xa904, 0xae04, 0x4c22, 0xae06, 0xa900, 0xe0c1,
+    0x0065, 0xaf19, 0xa803, 0xae17, 0xe056, 0xe0c2, 0x0204, 0xa200,
+    0xe0c2, 0x0208, 0x8442, 0xc786, 0xe018, 0xe000, 0x0620, 0xe09e,
+    0xe166, 0x020d, 0xe165, 0x0214, 0xd022, 0x0002, 0xe184, 0x1063,
+    0x2117, 0x4d17, 0x9f16, 0x9f15, 0x282c, 0xe0c2, 0x0217, 0xe166,
+    0x05b0, 0x2916, 0xe0c2, 0x0154, 0x2116, 0x4d16, 0xe0c2, 0x0155,
+    0x2116, 0x4d16, 0xe0c2, 0x0156, 0xe41e, 0x1176, 0xe41e, 0x1149,
+    0xe41e, 0x10f3, 0xa200, 0xe0c2, 0x0113, 0xe0c2, 0x030d, 0xe0c2,
+    0x022b, 0xa202, 0xe42e, 0xe0c0, 0x0111, 0xf7e8, 0xe0c0, 0x0065,
+    0xaf18, 0xa802, 0xf04a, 0xe0c0, 0x0281, 0xf7ea, 0xe42e, 0x2a61,
+    0x4e62, 0xcbb2, 0xaf10, 0xa8fe, 0x3c99, 0xae30, 0xe0c2, 0x0115,
+    0xe419, 0x0c0e, 0xcbb2, 0xa820, 0xa27f, 0xb611, 0xe0c3, 0x012a,
+    0xcbb2, 0x309a, 0xe049, 0xa803, 0xae03, 0xe05a, 0xa814, 0xe01a,
+    0xae14, 0xcbb3, 0xa81f, 0xe056, 0xe0c2, 0x0114, 0x289a, 0xcbb5,
+    0xf178, 0xa105, 0x209c, 0x4c9d, 0xf039, 0xae02, 0xf06e, 0xa103,
+    0xf049, 0xe049, 0xae02, 0xe056, 0xe0c2, 0x030a, 0xe004, 0x0055,
+    0xe0c2, 0x030c, 0xe0c0, 0x03b0, 0x34ac, 0x3cad, 0xe42e, 0x2885,
+    0xa002, 0x1814, 0xe01a, 0x2a86, 0xe01b, 0xe052, 0xa201, 0xb691,
+    0x2885, 0xb431, 0x2886, 0xb451, 0xe04a, 0xa806, 0xa106, 0xb495,
+    0xb495, 0xe0c3, 0x0120, 0xcbb8, 0xe0c2, 0x0121, 0xcbba, 0xe0c2,
+    0x0122, 0xcbbc, 0xe0c2, 0x0123, 0xe42e, 0x2a61, 0x4e62, 0xe0c0,
+    0x0111, 0xf7e8, 0xa202, 0xe0c2, 0x0110, 0xe42b, 0x2868, 0x1866,
+    0xe414, 0x0c24, 0xe42e, 0xa200, 0xe0c2, 0x030b, 0xa202, 0xe0c2,
+    0x0302, 0xe163, 0x06e0, 0x2843, 0x3d13, 0x2843, 0x3d13, 0x2844,
+    0x3d13, 0x2845, 0x3d13, 0xe161, 0x06e0, 0xe163, 0x0380, 0xd022,
+    0x0003, 0xe184, 0x111a, 0x8511, 0xc786, 0xe018, 0xb608, 0xe000,
+    0x0620, 0xe094, 0x2112, 0x4d12, 0x9f13, 0x2112, 0x4d12, 0x9f13,
+    0x2112, 0x4d12, 0x9f13, 0xa200, 0xe0c2, 0x0302, 0xe004, 0x0421,
+    0x3c9c, 0xe004, 0x0842, 0x3c9d, 0xa200, 0xe0c2, 0x0303, 0x288c,
+    0xae0c, 0xe0c2, 0x0330, 0xa200, 0xe0c2, 0x0308, 0x288c, 0xe166,
+    0x05e0, 0xe167, 0x0331, 0xf038, 0xe166, 0x05c0, 0xd022, 0x0007,
+    0xe184, 0x1141, 0x2916, 0xae10, 0x4d16, 0xae10, 0x4d16, 0xae10,
+    0x4d16, 0x9f17, 0xe190, 0xa202, 0xae02, 0xa902, 0xe0c2, 0x0312,
+    0xe42e, 0xa202, 0xe0c2, 0x013c, 0xa201, 0xe166, 0x0100, 0xd022,
+    0x00ff, 0xe184, 0x1158, 0x2916, 0xe0c3, 0x013e, 0xe0c2, 0x013f,
+    0xa003, 0xe190, 0xa200, 0xe0c2, 0x013c, 0xe42e, 0xa200, 0xe0c1,
+    0x0040, 0xe042, 0xe005, 0x0036, 0xae17, 0xe042, 0xe005, 0x1e80,
+    0xae03, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x05c0, 0xd112,
+    0x0040, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e, 0xa200, 0xe0c1,
+    0x0040, 0xe042, 0xe005, 0x0036, 0xae17, 0xe042, 0xe005, 0x1ec0,
+    0xae03, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0100, 0xd112,
+    0x0100, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e, 0xa200, 0x2a51,
+    0xa803, 0xf03b, 0xe00a, 0x0002, 0x2a51, 0xa805, 0xf02b, 0xa912,
+    0x2a51, 0xa809, 0xf02b, 0xa940, 0x2a51, 0xa811, 0xf02b, 0xa980,
+    0xe005, 0x0ba6, 0xe09f, 0x2b17, 0xae05, 0xe056, 0xe0c2, 0x0169,
+    0xe42e, 0xe0c0, 0x0065, 0xaf18, 0xa802, 0xe40a, 0x122b, 0xae0a,
+    0xe0c1, 0x0060, 0xaf0d, 0xa80f, 0xe056, 0xe0c1, 0x0044, 0xa811,
+    0xe056, 0xae0c, 0xe0c1, 0x0044, 0xa80f, 0xe056, 0xe167, 0x0ba7,
+    0x2f17, 0xe056, 0xe0c2, 0x0282, 0xe0c0, 0x006e, 0xe0c2, 0x0284,
+    0xaf20, 0xe0c1, 0x0282, 0xa809, 0xf04b, 0xe049, 0xae1f, 0xf06e,
+    0xe049, 0xa011, 0xaf09, 0xae07, 0xae21, 0xe056, 0xe0c2, 0x028c,
+    0xe167, 0x0ba8, 0x2d17, 0x4917, 0xe0c2, 0x0285, 0xe167, 0x0baa,
+    0x2d17, 0x4917, 0xe0c2, 0x0286, 0xe41e, 0x122c, 0xe0c0, 0x004a,
+    0xe0c2, 0x0289, 0xe0c0, 0x004b, 0xe0c2, 0x028a, 0xe0c0, 0x0055,
+    0xe0c2, 0x028b, 0xe0c1, 0x0041, 0xe004, 0x08c8, 0xae10, 0xe042,
+    0xe167, 0x0ba6, 0x2b17, 0xf05b, 0xe167, 0x0ba0, 0x2d17, 0x4917,
+    0xe0c2, 0x0287, 0xe0c1, 0x0041, 0xe004, 0x08e0, 0xae10, 0xe042,
+    0xe167, 0x0ba6, 0x2b17, 0xf05b, 0xe167, 0x0ba2, 0x2d17, 0x4917,
+    0xe0c2, 0x0288, 0xe0c1, 0x0041, 0xe004, 0x08e8, 0xae10, 0xe042,
+    0xe167, 0x0ba6, 0x2b17, 0xf05b, 0xe167, 0x0ba4, 0x2d17, 0x4917,
+    0xe0c2, 0x028d, 0xe0c0, 0x0065, 0xaf18, 0xa802, 0xe0c2, 0x0280,
+    0xa210, 0xe0c2, 0x0168, 0xe42e, 0xe167, 0x0bac, 0xe165, 0x028e,
+    0xe166, 0x02c0, 0xd022, 0x0008, 0xe184, 0x123f, 0x2d17, 0x9f16,
+    0x9e85, 0xf7fb, 0x2517, 0x4d17, 0x9f16, 0x9e85, 0xf7fb, 0xe190,
+    0xe166, 0x02d2, 0xd022, 0x0008, 0xe184, 0x124b, 0x2517, 0x4d17,
+    0x9f16, 0x9e85, 0xf7fb, 0xe190, 0xe166, 0x02db, 0xd022, 0x0008,
+    0xe184, 0x1257, 0x2517, 0x4d17, 0x9f16, 0x9e85, 0xf7fb, 0xe190,
+    0xe166, 0x02e4, 0xd022, 0x0008, 0xe184, 0x1262, 0x2d17, 0x9f16,
+    0x9e85, 0xf7fb, 0xe190, 0xe42e, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
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+    0x00ff, 0x00ff, 0x00ff, 0x00e1, 0x00fc, 0x00f1, 0x00fd, 0x00ff,
+    0x00ff, 0x00fe, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ea, 0x00fa,
+    0x00f1, 0x00fa, 0x00fd, 0x00ff, 0x00fd, 0x00fe, 0x00ff, 0x00ff,
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+    0x00fd, 0x00fe, 0x00fe, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00f8, 0x00fe, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00f9, 0x00fe, 0x00ff,
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+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fd, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00f7, 0x00fe,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
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+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fe,
+    0x00fd, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00fa, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fe, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ba, 0x00fb, 0x00fa, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ea, 0x00fb, 0x00f4, 0x00fe, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fb, 0x00fb,
+    0x00f3, 0x00fd, 0x00fe, 0x00ff, 0x00fe, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00fd, 0x00fe, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ec, 0x00fd, 0x00fe, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fb,
+    0x00fd, 0x00fd, 0x00fe, 0x00fe, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00fe, 0x00fe, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fe, 0x00fe, 0x00fe,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fe, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fe, 0x00fe,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00fe, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fe,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00f8, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00fa, 0x00fe, 0x00fc, 0x00fe, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00f8, 0x00fe,
+    0x00f9, 0x00fd, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00fd, 0x00fd, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00f6, 0x00fd, 0x00fd, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fc,
+    0x00fe, 0x00fb, 0x00fe, 0x00fe, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00fe, 0x00fc, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00f8, 0x00fe, 0x00fd,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00fd, 0x00ff, 0x00fe, 0x00fe, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fb, 0x00fe, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00f5, 0x00fb,
+    0x00fe, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00fd, 0x00fd, 0x00fe, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fb, 0x00fd, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fc,
+    0x00fd, 0x00fe, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00fe, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fc, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00f9, 0x00ff, 0x00fe, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fe, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00fd, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00fa, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00fe, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x00ed, 0x00f6, 0x00fd, 0x00fd, 0x00fe, 0x00fe, 0x00fe, 0x00fe,
+    0x00fe, 0x00fe, 0x00fe, 0x00fe, 0x00fe, 0x00fe, 0x00fa, 0x00fa,
+    0x00fc, 0x00fe, 0x00fe, 0x00e7, 0x00f3, 0x00f5, 0x00fd, 0x00fe,
+    0x00fe, 0x00fe, 0x00fe, 0x00fe, 0x00fe, 0x00fe, 0x00fe, 0x00fe,
+    0x00fe, 0x00fb, 0x00fb, 0x00fe, 0x00fe, 0x00fe, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0080, 0x0000, 0x0000, 0x0000, 0x0070, 0x0010, 0x0000,
+    0x0000, 0x0060, 0x0020, 0x0000, 0x0000, 0x0050, 0x0030, 0x0000,
+    0x0000, 0x0040, 0x0040, 0x0000, 0x0000, 0x0030, 0x0050, 0x0000,
+    0x0000, 0x0020, 0x0060, 0x0000, 0x0000, 0x0010, 0x0070, 0x0000,
+    0x0000, 0x0080, 0x0000, 0x0000, 0x0006, 0x007b, 0x000c, 0x0004,
+    0x008b, 0x006c, 0x0024, 0x0021, 0x0009, 0x005d, 0x0032, 0x0018,
+    0x00d0, 0x004d, 0x004d, 0x0043, 0x0006, 0x0032, 0x005d, 0x0024,
+    0x0048, 0x0024, 0x006c, 0x002e, 0x0001, 0x000c, 0x007b, 0x0018,
+    0x0004, 0x0005, 0x0006, 0x0007, 0x0008, 0x0009, 0x000a, 0x000a,
+    0x000b, 0x000c, 0x000d, 0x000e, 0x000f, 0x0010, 0x0011, 0x0011,
+    0x0012, 0x0013, 0x0014, 0x0014, 0x0015, 0x0015, 0x0016, 0x0016,
+    0x0017, 0x0017, 0x0018, 0x0019, 0x0019, 0x001a, 0x001b, 0x001c,
+    0x001d, 0x001e, 0x001f, 0x0020, 0x0021, 0x0022, 0x0023, 0x0024,
+    0x0025, 0x0025, 0x0026, 0x0027, 0x0028, 0x0029, 0x002a, 0x002b,
+    0x002c, 0x002d, 0x002e, 0x002e, 0x002f, 0x0030, 0x0031, 0x0032,
+    0x0033, 0x0034, 0x0035, 0x0036, 0x0037, 0x0038, 0x0039, 0x003a,
+    0x003b, 0x003c, 0x003d, 0x003e, 0x003f, 0x0040, 0x0041, 0x0042,
+    0x0043, 0x0044, 0x0045, 0x0046, 0x0047, 0x0048, 0x0049, 0x004a,
+    0x004b, 0x004c, 0x004c, 0x004d, 0x004e, 0x004f, 0x0050, 0x0051,
+    0x0052, 0x0053, 0x0054, 0x0055, 0x0056, 0x0057, 0x0058, 0x0059,
+    0x005b, 0x005d, 0x005f, 0x0060, 0x0062, 0x0064, 0x0065, 0x0066,
+    0x0068, 0x006a, 0x006c, 0x006e, 0x0070, 0x0072, 0x0074, 0x0076,
+    0x007a, 0x007c, 0x007e, 0x0080, 0x0082, 0x0084, 0x0086, 0x0088,
+    0x008a, 0x008c, 0x008f, 0x0091, 0x0094, 0x0097, 0x009a, 0x009d,
+    0x0004, 0x0005, 0x0006, 0x0007, 0x0008, 0x0009, 0x000a, 0x000b,
+    0x000c, 0x000d, 0x000e, 0x000f, 0x0010, 0x0011, 0x0012, 0x0013,
+    0x0014, 0x0015, 0x0016, 0x0017, 0x0018, 0x0019, 0x001a, 0x001b,
+    0x001c, 0x001d, 0x001e, 0x001f, 0x0020, 0x0021, 0x0022, 0x0023,
+    0x0024, 0x0025, 0x0026, 0x0027, 0x0028, 0x0029, 0x002a, 0x002b,
+    0x002c, 0x002d, 0x002e, 0x002f, 0x0030, 0x0031, 0x0032, 0x0033,
+    0x0034, 0x0035, 0x0036, 0x0037, 0x0038, 0x0039, 0x003a, 0x003c,
+    0x003e, 0x0040, 0x0042, 0x0044, 0x0046, 0x0048, 0x004a, 0x004c,
+    0x004e, 0x0050, 0x0052, 0x0054, 0x0056, 0x0058, 0x005a, 0x005c,
+    0x005e, 0x0060, 0x0062, 0x0064, 0x0066, 0x0068, 0x006a, 0x006c,
+    0x006e, 0x0070, 0x0072, 0x0074, 0x0077, 0x007a, 0x007d, 0x0080,
+    0x0083, 0x0086, 0x0089, 0x008c, 0x008f, 0x0092, 0x0095, 0x0098,
+    0x009b, 0x009e, 0x00a1, 0x00a4, 0x00a7, 0x00aa, 0x00ad, 0x00b1,
+    0x00b5, 0x00b9, 0x00bd, 0x00c1, 0x00c5, 0x00c9, 0x00cd, 0x00d1,
+    0x00d5, 0x00d9, 0x00dd, 0x00e1, 0x00e5, 0x00ea, 0x00ef, 0x00f5,
+    0x00f9, 0x00fe, 0x0103, 0x0108, 0x010d, 0x0112, 0x0117, 0x011c,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe40e, 0x0020, 0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x0131,
+    0xe470, 0xe190, 0xe40e, 0x0113, 0xe470, 0xe190, 0xe470, 0xe190,
+    0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+    0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x012f, 0xe40e, 0x0131,
+    0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058,
+    0xa200, 0xe0c2, 0x005a, 0x3cf0, 0x3cf1, 0xa2fe, 0x3cee, 0x3cef,
+    0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d, 0xce00, 0xf11e, 0xe0c0,
+    0x005c, 0xe0c1, 0x0059, 0x3eed, 0xa203, 0x5aed, 0xe052, 0xf08a,
+    0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00, 0xe41e,
+    0x008c, 0xe41e, 0x00ab, 0xe0c0, 0x005a, 0x18ee, 0xe0c1, 0x0059,
+    0xa115, 0xb636, 0x2aee, 0xb60a, 0xe418, 0x00fb, 0xe0c0, 0x005b,
+    0xe0c1, 0x005e, 0xae11, 0xe056, 0x18ef, 0xe0c1, 0x0059, 0xa117,
+    0xb636, 0xe418, 0x00b0, 0xe0c0, 0x005a, 0x18ee, 0x2aee, 0xb60a,
+    0xe0c1, 0x0059, 0xa117, 0xb636, 0xe418, 0x00f3, 0xd071, 0x802a,
+    0xe181, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100, 0xe0c0, 0x0059,
+    0xae02, 0xe000, 0x0113, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a,
+    0x3cee, 0xe41e, 0x0100, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11,
+    0xe056, 0x3cef, 0xe40e, 0x0037, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+    0x0058, 0xe0c2, 0x0008, 0xe0c0, 0x0059, 0xf7ea, 0xa11e, 0xf0e8,
+    0xa202, 0xe0c2, 0x0058, 0xe004, 0x093d, 0xe0c2, 0x0070, 0xa200,
+    0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xf6fe, 0xa202, 0xe0c2, 0x0008,
+    0xe0c2, 0x0058, 0xe42e, 0xd101, 0x0001, 0xc70f, 0xa000, 0xe42e,
+    0xa200, 0xe0c1, 0x005b, 0xf27b, 0xa220, 0xa103, 0xf2eb, 0xa230,
+    0xa103, 0xf2bb, 0xa23c, 0xa103, 0xf24b, 0xa258, 0xa103, 0xf25b,
+    0xa260, 0xa103, 0xf22b, 0xa200, 0xa103, 0xf1fb, 0xa26c, 0xa103,
+    0xf1cb, 0xe004, 0x003e, 0xa103, 0xf18b, 0xe004, 0x0044, 0xa105,
+    0xf14b, 0xe004, 0x0046, 0xa103, 0xf10b, 0xe004, 0x0000, 0xa107,
+    0xf0cb, 0xa200, 0xe0c1, 0x005e, 0xf08b, 0xe004, 0x004c, 0xf05e,
+    0xe0c1, 0x005e, 0xf02b, 0xa010, 0xae16, 0xe0c1, 0x0040, 0xe041,
+    0xca28, 0xf7f8, 0xce21, 0xd111, 0x0000, 0xd112, 0x2000, 0xd113,
+    0x000b, 0xe1e1, 0xe42e, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100,
+    0xe004, 0x0133, 0xe67c, 0xe41e, 0x0100, 0xe004, 0x0135, 0xe67c,
+    0x28ee, 0xe008, 0x03ff, 0xcca4, 0xe182, 0x0029, 0xe018, 0x2eee,
+    0xaf15, 0xcca5, 0xe182, 0x0029, 0xe019, 0xae15, 0xe042, 0xae14,
+    0x34f0, 0x3cf1, 0xe42e, 0xe40e, 0x0d3d, 0xe40e, 0x0137, 0xe40e,
+    0x013b, 0xe40e, 0x013f, 0xe40e, 0x0143, 0xe40e, 0x0147, 0xe40e,
+    0x014b, 0xe40e, 0x007e, 0xe40e, 0x007e, 0xe40e, 0x014f, 0xe40e,
+    0x007e, 0xe40e, 0x007e, 0xe40e, 0x007e, 0xe40e, 0x007e, 0xe40e,
+    0x007e, 0xe40e, 0x007e, 0xe40e, 0x03e8, 0xe40e, 0x0427, 0xe41e,
+    0x0153, 0xe40e, 0x007e, 0xe41e, 0x0177, 0xe40e, 0x007e, 0xe41e,
+    0x0183, 0xe40e, 0x007e, 0xe41e, 0x01cc, 0xe40e, 0x007e, 0xe41e,
+    0x01fa, 0xe40e, 0x007e, 0xe41e, 0x0244, 0xe40e, 0x007e, 0xe41e,
+    0x0c94, 0xe40e, 0x007e, 0xd130, 0x0008, 0xa200, 0xc401, 0xe188,
+    0x07ff, 0x3d11, 0xe41e, 0x038f, 0xa200, 0x3c2a, 0x3c33, 0xcc72,
+    0xcc44, 0x3ccb, 0x3ccc, 0xe41e, 0x0275, 0xf0ea, 0xe41e, 0x06f9,
+    0xe41e, 0x0d18, 0x2815, 0xe418, 0x09ea, 0xe41e, 0x0d10, 0xa202,
+    0xe0c2, 0x0070, 0xe42e, 0xa200, 0xe0c2, 0x0070, 0xe42e, 0x28be,
+    0xe428, 0x28bf, 0xf06a, 0xa200, 0x3c4d, 0xe41e, 0x0db3, 0xe42e,
+    0xe41e, 0x0d8b, 0xe42e, 0xa200, 0xcc44, 0xcc4a, 0xcc4c, 0x28bf,
+    0xf0fa, 0x28c0, 0xf09a, 0xe0c0, 0x0066, 0x344a, 0x3c4b, 0xe0c0,
+    0x0067, 0xae04, 0x3c4c, 0xa200, 0x3c4d, 0xe41e, 0x0db3, 0xd130,
+    0x0008, 0xd1e0, 0x0000, 0xd1ff, 0x03b0, 0xd199, 0x0224, 0xd03a,
+    0x0000, 0xd04b, 0x0001, 0xd04c, 0x0000, 0xd008, 0x0000, 0xe41e,
+    0x048b, 0x28bf, 0xf06a, 0xe41e, 0x0d8b, 0xe41e, 0x0658, 0xf05e,
+    0x28be, 0xf03a, 0xe41e, 0x0d96, 0x2c2a, 0xa002, 0x3c2a, 0x2c33,
+    0xa002, 0x3c33, 0xe0c2, 0x0070, 0x2829, 0xe0c2, 0x0071, 0x281f,
+    0xe0c2, 0x0073, 0xd039, 0x0000, 0xc84a, 0xc84d, 0xae20, 0xe056,
+    0xe0c2, 0x0053, 0xa202, 0xe42e, 0xd130, 0x0008, 0xe41e, 0x01e5,
+    0xe0c0, 0x0060, 0xe42a, 0xe0c0, 0x0042, 0xce20, 0xd111, 0x0570,
+    0xd112, 0x0030, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe0c0, 0x0060,
+    0x3c32, 0xe0c0, 0x0061, 0x3c70, 0xe42e, 0xe0c0, 0x0064, 0x3cd1,
+    0x34d0, 0xe0c0, 0x0065, 0x3cd3, 0x34d2, 0xe0c0, 0x0066, 0x3cd5,
+    0x34d4, 0xe0c0, 0x0067, 0x3cd7, 0x34d6, 0xe0c0, 0x0069, 0x3cd9,
+    0x34d8, 0xe42e, 0xd130, 0x0008, 0x28bf, 0xf0fa, 0x28c0, 0xf09a,
+    0xe0c0, 0x0061, 0x344a, 0x3c4b, 0xe0c0, 0x0062, 0xae04, 0x3c4c,
+    0xa200, 0x3c4d, 0xe41e, 0x0db3, 0xe0c0, 0x0060, 0xa806, 0xf08a,
+    0xa102, 0xf1aa, 0xa102, 0xf1ba, 0xa102, 0xf1ba, 0xe42e, 0xe0c0,
+    0x0060, 0xaf06, 0xa802, 0x3078, 0xf0ca, 0xe0c0, 0x0063, 0x3479,
+    0x3c7a, 0xe0c1, 0x0064, 0x367b, 0x3e7c, 0xe056, 0xe01a, 0x3c78,
+    0xe41e, 0x036c, 0xf0ee, 0xe41e, 0x0377, 0xf0be, 0xa214, 0xf02e,
+    0xa216, 0x3c30, 0xa200, 0x3c2f, 0xe41e, 0x0661, 0xe41e, 0x0688,
+    0x28bf, 0xf06a, 0xe41e, 0x0d8b, 0xe41e, 0x0658, 0xf05e, 0x28be,
+    0xf03a, 0xe41e, 0x0d96, 0xe42e, 0xe41e, 0x0d2c, 0xe0c0, 0x0060,
+    0xa802, 0xf158, 0xe0c0, 0x0060, 0xaf04, 0xa802, 0x3078, 0xf0ca,
+    0xe0c0, 0x0063, 0x3479, 0x3c7a, 0xe0c1, 0x0064, 0x367b, 0x3e7c,
+    0xe056, 0xe01a, 0x3c78, 0xe41e, 0x05c1, 0xf03e, 0xe41e, 0x05f6,
+    0xc870, 0xaf06, 0x3c45, 0xe0c2, 0x0070, 0xe004, 0x0080, 0xcc6e,
+    0xbadf, 0xe0c0, 0x0042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0100,
+    0xd113, 0x0012, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0074, 0xa806,
+    0x3cc9, 0xe0c0, 0x0074, 0xaf04, 0x3cca, 0xe0c0, 0x0064, 0x3450,
+    0x3c51, 0x3c71, 0x2850, 0xaf08, 0x3c50, 0x2851, 0xaf08, 0x3c51,
+    0xe0c0, 0x0065, 0x3418, 0x3c17, 0x2818, 0xa002, 0x3c18, 0xe0c0,
+    0x0062, 0x3019, 0xaf02, 0x301a, 0xaf02, 0x301b, 0xaf06, 0x30b8,
+    0xe0c1, 0x0071, 0x3eb9, 0xaf02, 0x30c8, 0xaf02, 0x30c7, 0xaf02,
+    0x30ce, 0xe0c0, 0x0068, 0xe049, 0xa83f, 0xae3f, 0xaf3f, 0x3e24,
+    0xe049, 0xaf0b, 0x3226, 0xe049, 0xaf0d, 0xa807, 0x3e2c, 0xe049,
+    0xaf11, 0xa81f, 0xaf41, 0xae41, 0xae03, 0x3e2d, 0xe049, 0xaf19,
+    0xa81f, 0xaf41, 0xae41, 0xae03, 0x3e2e, 0xe049, 0xaf21, 0xa803,
+    0x3e6b, 0x282c, 0x4c2d, 0x4c2e, 0xe01a, 0x3c25, 0xe0c0, 0x0069,
+    0x3037, 0xaf02, 0x3038, 0xaf02, 0x3c39, 0xe0c0, 0x006a, 0x3c14,
+    0xe0c0, 0x006b, 0x3015, 0x3481, 0xaf02, 0xe008, 0x7fff, 0x3c80,
+    0xe0c0, 0x006b, 0x2881, 0xaf1e, 0x30ac, 0x2881, 0xe008, 0x7fff,
+    0x3c81, 0xe0c0, 0x006c, 0x3482, 0x3c83, 0xe0c0, 0x006d, 0x3c1c,
+    0xa20a, 0x3c10, 0xa002, 0x3c12, 0xa202, 0x3c13, 0xa102, 0x3c22,
+    0xa200, 0x3c21, 0x3c20, 0x3c27, 0xa204, 0x3c11, 0xa234, 0x3c23,
+    0x8450, 0x8251, 0xe018, 0x3c52, 0xa201, 0xe002, 0x00c8, 0xb425,
+    0xe002, 0x0190, 0xb425, 0x3e36, 0xe0c0, 0x006e, 0x3472, 0x3c73,
+    0xe0c0, 0x006f, 0x3474, 0x3c75, 0x2850, 0x2a51, 0xaf06, 0xaf07,
+    0x3c07, 0x3e08, 0x8407, 0x8208, 0xe018, 0x3cc1, 0xa104, 0xf032,
+    0xa204, 0x3cc1, 0x2851, 0xaf02, 0x3c07, 0x8407, 0x8250, 0xe018,
+    0x3cc3, 0x3cc6, 0xa202, 0x3c1e, 0xe0c0, 0x0043, 0xaf06, 0x30be,
+    0xaf02, 0x30bf, 0xaf02, 0x30c0, 0xa202, 0xe42e, 0xcb04, 0xaf20,
+    0xe000, 0x0540, 0xe09e, 0xc872, 0x3d07, 0xcb04, 0xaf20, 0xa002,
+    0x1850, 0xe428, 0xcb04, 0xe008, 0xffff, 0xae0e, 0xe005, 0x0000,
+    0xae11, 0xe042, 0xe0c1, 0x0042, 0xe042, 0xce20, 0xd111, 0x0540,
+    0xd112, 0x002e, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0x204a,
+    0x4c4b, 0x2e4d, 0xae11, 0xe042, 0x0840, 0xe161, 0x04e4, 0x3511,
+    0x3d11, 0x281f, 0xae04, 0xe005, 0x0012, 0xae11, 0xe042, 0xe0c1,
+    0x0042, 0xe042, 0xce20, 0xd111, 0x04e4, 0xd112, 0x0004, 0xd113,
+    0x0002, 0xca28, 0xf7f8, 0xe42e, 0xa206, 0x3c2f, 0xa20e, 0x3c30,
+    0xe41e, 0x0661, 0xe41e, 0x05c1, 0xe41e, 0x0688, 0xe42e, 0xa206,
+    0x3c2f, 0xa210, 0x3c30, 0xe41e, 0x0661, 0xe41e, 0x05f6, 0xe41e,
+    0x0688, 0xe42e, 0xa200, 0x3c2f, 0xa212, 0x3c30, 0xe41e, 0x0661,
+    0xa204, 0xba84, 0xe41e, 0x064e, 0xe41e, 0x0688, 0xe42e, 0xe0c0,
+    0x0040, 0xe005, 0x003e, 0xae17, 0xe042, 0xe005, 0x1000, 0xae03,
+    0xe042, 0xce20, 0xd111, 0x03b0, 0xd112, 0x0100, 0xd113, 0x0003,
+    0xca28, 0xf7f8, 0xe42e, 0x281e, 0xf208, 0x281d, 0x181c, 0xf3f2,
+    0x2853, 0xa008, 0x18c2, 0xf3b4, 0x28c2, 0x08c1, 0x18c6, 0xf0b4,
+    0x28c4, 0xa002, 0xc70f, 0x7cc1, 0xaf20, 0x3cc4, 0x3cc2, 0x281c,
+    0x3c1d, 0xf2be, 0x281d, 0xa002, 0x3c1d, 0x28c2, 0x08c1, 0xc70f,
+    0x7cc6, 0xaf20, 0x3cc2, 0xf21e, 0x281d, 0x181c, 0xf202, 0x2853,
+    0xa008, 0x18c3, 0xf1c4, 0x28c3, 0x08c1, 0x1852, 0xf0c4, 0x28c5,
+    0xa002, 0xc70f, 0x7cc1, 0xaf20, 0x3cc5, 0x08c6, 0x3cc3, 0x281c,
+    0x3c1d, 0xf0be, 0x281d, 0xa002, 0x3c1d, 0x28c3, 0x08c1, 0xc70f,
+    0x7c52, 0xaf20, 0x3cc3, 0xf01e, 0xa202, 0xe42e, 0xa200, 0xe42e,
+    0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100, 0xa206, 0xe41e, 0x045f,
+    0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100, 0xe0c0, 0x005b, 0x3cef,
+    0xa226, 0xe41e, 0x0473, 0xe161, 0x07e0, 0x8911, 0x0034, 0x8911,
+    0x0033, 0x8911, 0x0035, 0x8911, 0x0036, 0x8911, 0x0037, 0x8911,
+    0x0038, 0x2111, 0x4d11, 0xcc60, 0xe0c2, 0x007d, 0x2111, 0x4d11,
+    0xcc62, 0x2111, 0x4d11, 0xcc64, 0x2111, 0x4d11, 0xcc72, 0xe0c2,
+    0x007e, 0xe161, 0x00f9, 0x2111, 0x4d11, 0xce88, 0xe0c2, 0x007f,
+    0x2111, 0x4d11, 0xce84, 0x2111, 0x4d11, 0xce80, 0xe42e, 0xe161,
+    0x07e0, 0x8b11, 0x0034, 0x8b11, 0x0033, 0x8b11, 0x0035, 0x8b11,
+    0x0036, 0x8b11, 0x0037, 0x8b11, 0x0038, 0xc860, 0x3511, 0x3d11,
+    0xe0c2, 0x007d, 0xc862, 0x3511, 0x3d11, 0xc864, 0x3511, 0x3d11,
+    0xc872, 0x3511, 0x3d11, 0xe0c2, 0x007e, 0xe161, 0x00f9, 0xca88,
+    0x3511, 0x3d11, 0xe0c2, 0x007f, 0xca84, 0x3511, 0x3d11, 0xca80,
+    0x3511, 0x3d11, 0xf06e, 0xe161, 0x07e0, 0xa200, 0xc70f, 0x3d11,
+    0xa224, 0xe41e, 0x0473, 0xa204, 0xe41e, 0x045f, 0xe42e, 0x3ced,
+    0xd112, 0x0800, 0xe0c0, 0x0041, 0xe005, 0x0280, 0xae11, 0xe042,
+    0x22f0, 0x4ef1, 0xe042, 0xce20, 0xd111, 0x0000, 0x88ed, 0x0113,
+    0xca28, 0xf7f8, 0xe42e, 0x2aef, 0xa80f, 0xa10b, 0xe42b, 0x3ced,
+    0xd112, 0x0100, 0xe0c0, 0x0041, 0xe005, 0x0298, 0xae11, 0xe042,
+    0x22f0, 0x4ef1, 0xe042, 0xce20, 0xd111, 0x0000, 0x88ed, 0x0113,
+    0xca28, 0xf7f8, 0xe42e, 0x2824, 0xa83e, 0xae06, 0xcf80, 0xd1f3,
+    0x0000, 0x2835, 0xcfe4, 0xa200, 0xcfc2, 0xd1e8, 0x0055, 0x2850,
+    0xa102, 0xae02, 0x4c26, 0xae06, 0xcf00, 0xd1d3, 0x000d, 0xd185,
+    0x0001, 0xe41e, 0x0cc7, 0xe41e, 0x0cca, 0x281b, 0xe418, 0x0382,
+    0xe41e, 0x04cc, 0x283c, 0x3c2b, 0xe41e, 0x0d15, 0x2829, 0xf05a,
+    0x281e, 0xa002, 0xa802, 0x3c1e, 0xe41e, 0x06fc, 0xe41e, 0x05bb,
+    0xa200, 0x3c53, 0x3c1f, 0x2831, 0xf028, 0x3ccf, 0xe41e, 0x0517,
+    0x2853, 0x1852, 0xf7c4, 0x28cf, 0xa002, 0x3ccf, 0xe41e, 0x087c,
+    0x2815, 0xe418, 0x0a8e, 0xe42e, 0xe0c0, 0x0065, 0xa804, 0xf06a,
+    0xa200, 0x3c2a, 0x3cb6, 0xe016, 0x3c8d, 0x2814, 0xf048, 0x2c2a,
+    0xf07a, 0xf0ae, 0x28b6, 0xf04a, 0x2a14, 0xe046, 0xf058, 0x3c29,
+    0xa202, 0x3cb6, 0xf05e, 0xa202, 0x3c29, 0x08b6, 0x3cb6, 0xa200,
+    0x3c77, 0xe0c0, 0x0065, 0xa802, 0xe418, 0x0501, 0xe0c0, 0x0063,
+    0x3c3c, 0x2815, 0xf09a, 0x2829, 0xe418, 0x0a49, 0xe41e, 0x0a4a,
+    0x3c3c, 0xe419, 0x0501, 0x2c2a, 0xe016, 0x3c31, 0xa004, 0x3c2f,
+    0xe42e, 0xa202, 0x3c29, 0x3c77, 0x8435, 0xc786, 0xe018, 0xe000,
+    0x0570, 0xe09e, 0x2117, 0x4d17, 0xe0c2, 0x0060, 0x2117, 0x4d17,
+    0xe0c2, 0x0061, 0x2117, 0x4d17, 0xe0c2, 0x0062, 0xe42e, 0x2a31,
+    0xa20a, 0xb636, 0x3c30, 0xe41e, 0x0661, 0xe41e, 0x061b, 0xa202,
+    0x3ccb, 0xe41e, 0x052e, 0xe41e, 0x064e, 0xe41e, 0x0688, 0x281a,
+    0xe418, 0x034f, 0x281f, 0xa002, 0x3c1f, 0xe42e, 0x282b, 0xcf96,
+    0x282c, 0xae0a, 0x2a2d, 0xa83f, 0xe056, 0xae0a, 0x2a2e, 0xa83f,
+    0xe056, 0xcf30, 0x2829, 0xcfc4, 0xcf82, 0xd188, 0x0001, 0xa200,
+    0xcf86, 0x3c3a, 0xa202, 0x3c3b, 0x2853, 0xe002, 0x000f, 0xe408,
+    0x054a, 0xe190, 0xe41e, 0x056d, 0xe41e, 0x05be, 0x8a5e, 0x0039,
+    0x2819, 0xe418, 0x032e, 0xe41e, 0x0582, 0xc872, 0x1c5e, 0xe008,
+    0xffff, 0x3c5f, 0x2a15, 0xcb96, 0xe419, 0x0b17, 0x2853, 0x1852,
+    0xf042, 0x283a, 0xe40a, 0x0544, 0xcb86, 0xf02a, 0xbbfc, 0x2a15,
+    0xcb96, 0xf02b, 0x3c2b, 0xa202, 0xe42e, 0x2837, 0x2a38, 0xe42a,
+    0xe409, 0x0577, 0xc870, 0x1c39, 0xe424, 0xe40e, 0x057f, 0x283b,
+    0x1839, 0x2a3b, 0xa003, 0x3e3b, 0xe428, 0xa202, 0x3c3b, 0xa202,
+    0x3c3a, 0xe42e, 0xd185, 0x0002, 0xd186, 0x0000, 0x2855, 0xae02,
+    0x4c54, 0xcf8a, 0x2859, 0xcf94, 0xa200, 0xcfdc, 0xcf84, 0x2858,
+    0xcfd2, 0xd1d0, 0x00c0, 0xcba0, 0xf7f8, 0x2854, 0xf16a, 0xcb18,
+    0x3c00, 0x2855, 0xf088, 0xe0c0, 0x0121, 0xcf8c, 0xe0c0, 0x0122,
+    0xcf8e, 0xf07e, 0x2856, 0x4400, 0xa104, 0xe012, 0xae38, 0xcf8c,
+    0x2857, 0x4400, 0xcf90, 0xf03e, 0xcbd2, 0xcf9a, 0xd1d0, 0x003f,
+    0xcba0, 0xf7f8, 0xe41e, 0x0d04, 0xd186, 0x0001, 0xd185, 0x0004,
+    0xcb06, 0x3c53, 0xe42e, 0xe41e, 0x081a, 0xe42e, 0xe41e, 0x0847,
+    0xe42e, 0xe004, 0x0042, 0xba8e, 0xbac0, 0xbac0, 0xbac0, 0xbac4,
+    0xa23d, 0xba8f, 0xa200, 0xbbfc, 0x2810, 0xa108, 0xbbfc, 0x2811,
+    0xbbfc, 0x2813, 0xbbfc, 0xbac0, 0x2850, 0xa102, 0xbbfc, 0x2851,
+    0xa102, 0xbbfc, 0xbae0, 0xbae0, 0x2878, 0xf038, 0xbac0, 0xf0fe,
+    0xbae0, 0x2879, 0xaf02, 0xbbfc, 0x287a, 0xaf02, 0xbbfc, 0x287b,
+    0xaf02, 0xbbfc, 0x287c, 0xaf02, 0xbbfc, 0xe190, 0xbac0, 0xe41e,
+    0x064e, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0xa200, 0xbbfc,
+    0xa200, 0xbbfc, 0xbac0, 0x2820, 0xba80, 0x2821, 0xbbfc, 0xe408,
+    0x0618, 0x2822, 0xbbfc, 0xa200, 0xbbfc, 0xbac0, 0xbac1, 0x2823,
+    0xa134, 0xbbfe, 0xa200, 0xbbfe, 0x2824, 0xbbfe, 0x2825, 0xba80,
+    0x2826, 0xba80, 0x2827, 0xba80, 0xe41e, 0x064e, 0xa202, 0xe42e,
+    0xe16a, 0xa200, 0xe42e, 0x2853, 0xbbfc, 0x2829, 0xe016, 0xae02,
+    0xa00a, 0xbbfc, 0xa200, 0xbbfc, 0x2c2a, 0x7010, 0x2831, 0xf03a,
+    0x28cf, 0xbbfc, 0x2829, 0xf03a, 0xbac0, 0xbac0, 0x282f, 0xe40a,
+    0x0639, 0x2831, 0xe40a, 0x0638, 0xbac0, 0xbac0, 0xe40e, 0x0639,
+    0xbac0, 0x282b, 0x1823, 0xbbfe, 0x2825, 0xe40a, 0x064a, 0x282c,
+    0xbbfc, 0xa102, 0xe40a, 0x064a, 0x282d, 0xaf02, 0xbbfe, 0x282e,
+    0xaf02, 0xbbfe, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xbae0, 0xc868,
+    0xa80e, 0xe42a, 0xa110, 0xe012, 0x3c48, 0xa200, 0x7048, 0xe42e,
+    0xa200, 0x3c40, 0xd142, 0x01ff, 0xd140, 0x0680, 0xd141, 0x0000,
+    0xe42e, 0xc872, 0xa050, 0xcc72, 0x2840, 0xaf02, 0xe000, 0x0680,
+    0xe098, 0x2840, 0xa802, 0x3c41, 0xa200, 0xe41e, 0x06e4, 0xa200,
+    0xe41e, 0x06e4, 0xa200, 0xe41e, 0x06e4, 0xa202, 0xe41e, 0x06e4,
+    0x282f, 0xae0a, 0x4c30, 0xe41e, 0x06e4, 0xe088, 0xe002, 0x0680,
+    0xae02, 0x0841, 0x3c40, 0xe41e, 0x0d2c, 0xa2fe, 0x3c43, 0xe42e,
+    0xc866, 0xe008, 0x007f, 0xe002, 0x0000, 0xae04, 0x3c45, 0xc868,
+    0xaf06, 0x0845, 0x3c45, 0xe42a, 0xc86e, 0xe000, 0x0080, 0xcc6e,
+    0xbadf, 0xc870, 0xa140, 0xcc70, 0xc872, 0xa140, 0xcc72, 0xe41e,
+    0x06b5, 0xe42e, 0xc000, 0xc86e, 0xf06a, 0xd141, 0x0000, 0xe41e,
+    0x06b5, 0xe42e, 0xd141, 0x0100, 0xe41e, 0x06b5, 0xe42e, 0xe004,
+    0x0200, 0x3c45, 0xe41e, 0x06b5, 0xe42e, 0x2849, 0xf048, 0xd141,
+    0x0000, 0xf03e, 0xd141, 0x0100, 0xd147, 0x0000, 0x8840, 0x0146,
+    0x8843, 0x0145, 0x2845, 0xa102, 0xce86, 0xd149, 0x0000, 0xd148,
+    0x0001, 0xca94, 0xf7fa, 0xa106, 0xf0b4, 0xe41e, 0x0d59, 0xd146,
+    0x0000, 0xd148, 0x0001, 0xca94, 0xf7fa, 0xa106, 0xf77a, 0x8a40,
+    0x0146, 0x8a43, 0x0145, 0x2840, 0xe002, 0x0200, 0xe428, 0xe41e,
+    0x0d59, 0xa200, 0x3c40, 0xe42e, 0x2a41, 0xe409, 0x06ec, 0xae10,
+    0x3d04, 0xe017, 0x3e41, 0xe42e, 0x4d04, 0x3d14, 0xe017, 0x3e41,
+    0xe089, 0xe003, 0x0780, 0xe429, 0xe41e, 0x0d59, 0xe164, 0x0680,
+    0xe42e, 0xa200, 0x3c34, 0xe42e, 0xe41e, 0x09ba, 0xa210, 0xe0c2,
+    0x0100, 0x2a29, 0xa25e, 0xf029, 0xa250, 0xe0c2, 0x017c, 0xa200,
+    0xe0c2, 0x017d, 0xe0c2, 0x013d, 0xe0c0, 0x0050, 0x3000, 0xaf02,
+    0x3001, 0xaf02, 0x3002, 0xaf02, 0x3003, 0xaf04, 0x3005, 0xaf06,
+    0x3006, 0xaf02, 0x3007, 0xaf02, 0x3008, 0xaf02, 0x3009, 0xaf04,
+    0x300a, 0x2806, 0x4400, 0x3c00, 0x2807, 0x4401, 0x3c01, 0x2808,
+    0x4402, 0x3c02, 0x2809, 0x4403, 0x3c03, 0x280a, 0x4405, 0x3c05,
+    0xa200, 0xe0c2, 0x0168, 0x2a00, 0xf03b, 0xe00a, 0x0002, 0x2a01,
+    0xf03b, 0xe00a, 0x0009, 0x2a02, 0xf03b, 0xe00a, 0x0020, 0x2a03,
+    0xf03b, 0xe00a, 0x0040, 0x2a05, 0xf03b, 0xe00a, 0x0004, 0xe0c2,
+    0x0169, 0xe0c1, 0x0041, 0xe004, 0x0000, 0xae10, 0xe042, 0x2a06,
+    0xf03b, 0x20d0, 0x4cd1, 0xcf0e, 0xe0c1, 0x0041, 0xe004, 0x0040,
+    0xae10, 0xe042, 0x2a07, 0xf03b, 0x20d2, 0x4cd3, 0xe0c2, 0x0103,
+    0xa200, 0xe0c2, 0x0208, 0xa202, 0xe0c2, 0x0210, 0xe0c1, 0x0041,
+    0xe004, 0x0070, 0xae10, 0xe042, 0x2a08, 0xf03b, 0x20d4, 0x4cd5,
+    0xe0c2, 0x0211, 0xe000, 0x4000, 0x2a09, 0xf03b, 0x20d6, 0x4cd7,
+    0xe0c2, 0x0212, 0xa202, 0xae02, 0xa902, 0xe0c2, 0x0312, 0xe0c0,
+    0x0064, 0x3c76, 0x2a77, 0xf02b, 0xa200, 0xe0c2, 0x0138, 0x2850,
+    0xae20, 0x4c51, 0xae08, 0xe0c2, 0x0101, 0x2a77, 0xaa03, 0x4676,
+    0xa803, 0xf05b, 0x2851, 0xae20, 0x4c50, 0xae08, 0xe0c2, 0x0142,
+    0xe0c0, 0x0044, 0xa81e, 0xae1a, 0x4c70, 0xe0c2, 0x0102, 0x2829,
+    0xae06, 0xe0c2, 0x0104, 0xa210, 0xae0e, 0xe0c2, 0x0204, 0xe0c0,
+    0x0060, 0xe0c2, 0x0143, 0xe0c0, 0x0061, 0xe0c2, 0x0144, 0xe0c0,
+    0x0062, 0xe0c2, 0x0145, 0x2870, 0x2a77, 0xaa03, 0x4676, 0xa803,
+    0xf02b, 0x2871, 0xe0c2, 0x0141, 0x8434, 0xc786, 0xe018, 0xe000,
+    0x0570, 0xe09e, 0x2117, 0x4d17, 0xe0c2, 0x020d, 0xe0c2, 0x0214,
+    0x2117, 0x4d17, 0xe0c2, 0x020e, 0xe0c2, 0x0215, 0x2117, 0x4d17,
+    0xe0c2, 0x020f, 0xe0c2, 0x0216, 0xa202, 0xe0c2, 0x0302, 0x8435,
+    0xc786, 0xe018, 0xe000, 0x0570, 0xe09e, 0x2117, 0x4d17, 0xe0c2,
+    0x0380, 0xe0c2, 0x0183, 0x2117, 0x4d17, 0xe0c2, 0x0381, 0x2117,
+    0x4d17, 0xe0c2, 0x0382, 0xa200, 0xe0c2, 0x0302, 0x2834, 0xe0c2,
+    0x0072, 0x3c35, 0xa002, 0x3c34, 0x1832, 0xf028, 0x3c34, 0xa228,
+    0xae20, 0xe00a, 0x1111, 0xe0c2, 0x0119, 0xa200, 0xe0c2, 0x0113,
+    0xe0c2, 0x022b, 0xe0c2, 0x030d, 0xe0c2, 0x0320, 0xe0c2, 0x030a,
+    0xe0c2, 0x030b, 0xe004, 0x0055, 0xe0c2, 0x030c, 0xe004, 0x003f,
+    0xe0c2, 0x012a, 0xa202, 0xe0c2, 0x0106, 0xe0c2, 0x0139, 0xe41e,
+    0x0957, 0xe42e, 0xa2f6, 0x3c53, 0xe0c2, 0x003f, 0xa202, 0xe0c2,
+    0x0110, 0xa2f8, 0x3c53, 0x2853, 0xe0c2, 0x003f, 0xa002, 0xf094,
+    0xe41e, 0x0940, 0xa200, 0x3ccc, 0xe41e, 0x0cd3, 0xe41e, 0x0927,
+    0xe41e, 0x09db, 0x2829, 0xe418, 0x09df, 0xa202, 0xe0c2, 0x0110,
+    0x2829, 0xe0c2, 0x018b, 0x2829, 0xe418, 0x08f5, 0xe41e, 0x0890,
+    0xe41e, 0x08d3, 0x2853, 0xa002, 0x3c53, 0xf5e4, 0xe42e, 0x2853,
+    0xe0c2, 0x003f, 0xe002, 0x0062, 0xf028, 0xe190, 0x2852, 0x1853,
+    0xa108, 0xa201, 0xb62d, 0x3e5a, 0xe41e, 0x0940, 0xe41e, 0x0ceb,
+    0x283a, 0xe418, 0x0cca, 0xe41e, 0x0cd3, 0xe41e, 0x0927, 0xe41e,
+    0x09db, 0x285a, 0xe016, 0x4429, 0xe418, 0x09df, 0xa202, 0xe0c2,
+    0x0110, 0x285a, 0xe016, 0x4429, 0xe0c2, 0x018b, 0xe41e, 0x0915,
+    0xe41e, 0x08e4, 0x285a, 0xf088, 0x2829, 0xe418, 0x08f5, 0xe41e,
+    0x0890, 0xe41e, 0x08d3, 0xe42e, 0xe41e, 0x09db, 0x2852, 0xe0c2,
+    0x003f, 0xa202, 0xe0c2, 0x0110, 0xe41e, 0x09db, 0xa202, 0xe0c2,
+    0x0110, 0xe41e, 0x09db, 0xe0c0, 0x0118, 0xa802, 0xf7da, 0xe42e,
+    0xe0c0, 0x015d, 0xe049, 0xaf20, 0xe009, 0xffff, 0xe066, 0xe0c1,
+    0x015c, 0xe065, 0x283c, 0xaf04, 0xe000, 0x0430, 0xe09e, 0x1b07,
+    0x28ce, 0xb62a, 0x3c01, 0xe0c0, 0x0197, 0x3c06, 0x2829, 0xe016,
+    0x0b07, 0xf0c8, 0xe001, 0x0280, 0x1e06, 0xb62a, 0x2a1c, 0xf068,
+    0xe419, 0x03a3, 0x2a01, 0xb615, 0x3e01, 0x3c00, 0x2877, 0xe016,
+    0xf048, 0xa200, 0x3c00, 0x3c01, 0x2801, 0x2a3c, 0xa109, 0xb60e,
+    0x3c01, 0x2801, 0xae02, 0x4c00, 0xe0c2, 0x0114, 0x2800, 0xe42a,
+    0xe0c0, 0x0161, 0xaf20, 0x3c03, 0x2801, 0xe42a, 0xe0c0, 0x015e,
+    0xaf20, 0x3c02, 0xe42e, 0x2853, 0xa806, 0xae04, 0xe000, 0x0200,
+    0xe092, 0x2801, 0xae02, 0x4c00, 0x3d11, 0x2802, 0x3d11, 0x2803,
+    0x3d11, 0x2804, 0x3d11, 0xe42e, 0x2853, 0xa806, 0xae04, 0xe000,
+    0x0200, 0xe092, 0x2911, 0x3054, 0xaf02, 0x3055, 0x2911, 0x3c56,
+    0x2911, 0x3c57, 0x2911, 0x3c58, 0xe42e, 0xe0c0, 0x0195, 0x3c04,
+    0xae06, 0x4c04, 0xae06, 0x4c04, 0xae06, 0x4c04, 0x3c04, 0xe0c2,
+    0x0309, 0x2853, 0xa806, 0xae06, 0xe000, 0x0210, 0xe092, 0xe162,
+    0x0191, 0xe163, 0x03b0, 0xc420, 0xd022, 0x0003, 0xe184, 0x0913,
+    0x9e12, 0x3511, 0x3d11, 0x9f33, 0xe42e, 0x2853, 0xa806, 0xae06,
+    0xe000, 0x0210, 0xe092, 0xe005, 0x0080, 0xd022, 0x0003, 0xe184,
+    0x0925, 0xcfd5, 0xa011, 0x2111, 0x4d11, 0xcfd6, 0xe42e, 0x2864,
+    0xe0c2, 0x0120, 0x2862, 0xe0c2, 0x011b, 0x2853, 0xa002, 0xa806,
+    0xae04, 0xe000, 0x0201, 0xe092, 0x2911, 0x4464, 0xa104, 0xe012,
+    0xae38, 0xe0c2, 0x0121, 0x2901, 0x4464, 0xe0c2, 0x0123, 0xe42e,
+    0x2805, 0x3c59, 0x2a15, 0x4629, 0x282b, 0xe419, 0x0ac2, 0x3c05,
+    0x2805, 0x0824, 0xa400, 0xa566, 0xe000, 0x0450, 0xe09c, 0x2906,
+    0xae0c, 0x4d06, 0xae0c, 0x4c05, 0xe0c2, 0x0115, 0xe42e, 0x2072,
+    0x4c73, 0x2a0a, 0xf03b, 0x20d8, 0x4cd9, 0xe0c2, 0x0187, 0x2074,
+    0x4c75, 0xe0c2, 0x0188, 0x2851, 0xae08, 0xa102, 0xae20, 0x2a50,
+    0xae09, 0xa103, 0xe056, 0xe0c2, 0x0181, 0x2870, 0xe0c2, 0x0189,
+    0xe0c2, 0x018a, 0xe0c0, 0x0060, 0xe0c2, 0x0182, 0xe0c0, 0x0044,
+    0xe0c2, 0x0199, 0xa201, 0x282b, 0xa154, 0xf0c4, 0xa27f, 0xae03,
+    0xa106, 0xf084, 0xae05, 0xa106, 0xf054, 0xae03, 0xa104, 0xf024,
+    0xae03, 0x283c, 0xa558, 0xa41c, 0xaf02, 0xa10e, 0x0836, 0xa51e,
+    0x3c04, 0xae04, 0xe000, 0x03f0, 0xe09e, 0x2117, 0x4d17, 0xe042,
+    0xe0c2, 0x0184, 0x2107, 0x4d17, 0xe0c2, 0x0185, 0x2917, 0xe0c2,
+    0x019a, 0x2804, 0xae04, 0xe000, 0x03b0, 0xe09e, 0x2117, 0x4d17,
+    0xe0c2, 0x019f, 0x2117, 0x4d17, 0xe0c2, 0x019e, 0x2829, 0x2a6b,
+    0xae05, 0xe056, 0xe0c2, 0x0186, 0xe004, 0x01a6, 0x4c29, 0xe0c2,
+    0x0180, 0xe42e, 0xe004, 0x3211, 0xae20, 0xe00a, 0x2100, 0xe0c2,
+    0x0155, 0xe004, 0x9211, 0xae20, 0xe00a, 0x2100, 0xe0c2, 0x0158,
+    0xe004, 0x1000, 0xae20, 0xe00a, 0x0000, 0xe0c2, 0x0156, 0xe0c2,
+    0x0159, 0xe004, 0x0104, 0xe0c2, 0x0154, 0xe0c2, 0x0157, 0xa202,
+    0xe0c2, 0x015a, 0xe42e, 0xe0c0, 0x0111, 0xf7e8, 0xe42e, 0xe0c0,
+    0x018c, 0xf7e8, 0xe42e, 0xe0c0, 0x0198, 0xf7ea, 0xa200, 0xe0c2,
+    0x0198, 0xe42e, 0xa254, 0x3ccd, 0xa268, 0x3c84, 0xa218, 0x3c86,
+    0xa266, 0x2ac8, 0xf03b, 0xe0c0, 0x0072, 0x3c85, 0xa210, 0x3c87,
+    0xe004, 0x0440, 0x3c88, 0x2814, 0x2a52, 0x3c89, 0x3e8f, 0x2c17,
+    0xc710, 0x7c18, 0xe008, 0xffff, 0xa002, 0xaf02, 0x3c8b, 0x3cbb,
+    0xe004, 0x6000, 0x2ac7, 0xf03b, 0xe0c0, 0x0073, 0x3c8c, 0x2889,
+    0xe016, 0x3c8a, 0xf06a, 0x288b, 0x3c89, 0xe004, 0x1000, 0x3c8c,
+    0x8418, 0xe182, 0x7530, 0xe018, 0xae02, 0x2e17, 0xe41e, 0x0bb2,
+    0x3c98, 0x8498, 0x8280, 0xe018, 0xa279, 0xe41e, 0x0b9b, 0x3498,
+    0x3c99, 0xae06, 0x2a84, 0xe41e, 0x0b9b, 0x349e, 0x3c9f, 0xa202,
+    0x3c8d, 0xa205, 0x1a36, 0xae03, 0xa011, 0x3e94, 0x2a8f, 0x5a94,
+    0xe013, 0x36ae, 0x3eaf, 0x28b9, 0x2ab8, 0xf049, 0xe41e, 0x0b40,
+    0x64cd, 0x3c90, 0xa004, 0x6086, 0x6485, 0x3c91, 0xe41e, 0x0b64,
+    0xe42e, 0xe42e, 0x2829, 0x3c8e, 0xa201, 0x3ead, 0x3ecc, 0xe418,
+    0x0b22, 0xa200, 0x3ca0, 0x3ca1, 0x288e, 0xf238, 0x288d, 0xf05a,
+    0xa200, 0x3c8d, 0x2890, 0xf31e, 0x2889, 0xa102, 0xf7ca, 0x2ab8,
+    0xf03b, 0x2890, 0xf2ae, 0x848f, 0x82b5, 0xe019, 0xe04a, 0xaf02,
+    0x00a2, 0x0ca3, 0xe41e, 0x0bb2, 0xa21f, 0x3e94, 0x2a89, 0xc70f,
+    0x7e94, 0xe009, 0xffff, 0xa405, 0xe046, 0x6086, 0x64cd, 0xf15e,
+    0xa200, 0x3c9c, 0x3c9d, 0x28c9, 0x3094, 0xaf02, 0x5494, 0xf08a,
+    0x2891, 0xa104, 0x6093, 0x2a91, 0xa005, 0xe066, 0xf02e, 0x2891,
+    0x2aad, 0xf02b, 0x2885, 0x3c93, 0x2aad, 0xe42e, 0xc872, 0xe41e,
+    0x0b6d, 0x288e, 0xf0ea, 0x20a0, 0x4ca1, 0xc710, 0x7c8f, 0xe008,
+    0xffff, 0xa002, 0xaf02, 0x3c91, 0x20a0, 0x4ca1, 0x00a2, 0x0ca3,
+    0x34a2, 0x3ca3, 0x28b5, 0xa002, 0x3cb5, 0x288e, 0xf028, 0x3cb5,
+    0x288e, 0xf0f8, 0x2a89, 0xa103, 0x20a6, 0x4ca7, 0xe41e, 0x0b9b,
+    0x34aa, 0x3cab, 0x10a6, 0x1ca7, 0xe012, 0x34a8, 0x3ca9, 0xf0ae,
+    0x22a8, 0x4ea9, 0x12aa, 0x1eab, 0x288a, 0xb606, 0xb611, 0x36a8,
+    0x3ea9, 0xe42e, 0x28c9, 0xf07a, 0x2852, 0x1853, 0xa102, 0xf038,
+    0x2805, 0xe42e, 0x229c, 0x4e9d, 0x209e, 0x4c9f, 0xe041, 0xf0c7,
+    0xe045, 0xe045, 0x2893, 0xf0f5, 0x369c, 0x3e9d, 0xa002, 0x6086,
+    0x6485, 0x3c93, 0xf08e, 0x369c, 0x3e9d, 0x2893, 0xa102, 0x6086,
+    0x6485, 0x3c93, 0x2893, 0x6086, 0x6485, 0x3c93, 0x28cc, 0xa002,
+    0x3ccc, 0x2ac9, 0xf08b, 0xa103, 0xf22b, 0xa103, 0xf07b, 0xa103,
+    0xf0ab, 0xf24e, 0x2893, 0x3c94, 0xf21e, 0x28cb, 0xf18a, 0xa200,
+    0x3ccb, 0xf06e, 0x28cc, 0x18ca, 0xf124, 0xa200, 0x3ccc, 0x2853,
+    0xa002, 0xf04a, 0xcb97, 0xcb96, 0xf03e, 0x2a2b, 0x282b, 0xa105,
+    0x6293, 0xa004, 0xe066, 0x3c93, 0x3c94, 0xf08e, 0xcb96, 0x3c94,
+    0x2853, 0xa002, 0xf038, 0x282b, 0x3c94, 0x2894, 0xe42e, 0x00a0,
+    0x0ca1, 0x34a0, 0x3ca1, 0x285f, 0x1892, 0x009c, 0x0c9d, 0x349c,
+    0x3c9d, 0xe42e, 0x20a8, 0x4ca9, 0x10a6, 0x1ca7, 0x848c, 0xe41e,
+    0x0be9, 0x0098, 0x0c99, 0xf052, 0x2aac, 0xf039, 0xa203, 0x3ead,
+    0xe41e, 0x0b81, 0x2298, 0x4e99, 0xaf07, 0xe062, 0x349a, 0x3c9b,
+    0xc710, 0x7c8f, 0xe008, 0xffff, 0xa002, 0xaf02, 0x3c92, 0xe42e,
+    0x8489, 0x2098, 0x4c99, 0xe41e, 0x0bdd, 0x8487, 0xe41e, 0x0bdd,
+    0x2a89, 0xa103, 0x0a87, 0xe41e, 0x0b9b, 0x349a, 0x3c9b, 0x288f,
+    0x3cb0, 0x209a, 0x4c9b, 0xae04, 0x009a, 0x0c9b, 0xae02, 0xc70f,
+    0x7cb0, 0xe008, 0xffff, 0xaf08, 0xa010, 0xaf08, 0x0836, 0xa51e,
+    0x0888, 0xe09e, 0x2907, 0xe42e, 0x8480, 0x8281, 0xe018, 0x34a4,
+    0x3ca5, 0xa200, 0x34a6, 0x3ca7, 0xe42e, 0xe0c2, 0x007d, 0x1098,
+    0x1c99, 0x00a6, 0x0ca7, 0xa27f, 0xae31, 0xe066, 0x34a6, 0x3ca7,
+    0x22ae, 0x4eaf, 0xe046, 0xf032, 0x36a6, 0x3ea7, 0x20a6, 0x28a7,
+    0xe42e, 0x2a81, 0xe42b, 0x22a4, 0x4ea5, 0x12a6, 0x1ea7, 0xe066,
+    0xf051, 0x2aac, 0xf039, 0xa203, 0x3ead, 0x2282, 0x4e83, 0xe42b,
+    0x22a4, 0x4ea5, 0x12a6, 0x1ea7, 0x0298, 0x0e99, 0x1282, 0x1e83,
+    0xa401, 0xe062, 0xe42e, 0x3eb0, 0xa201, 0xf032, 0xe012, 0xa203,
+    0x3eb4, 0x3cb1, 0xaf20, 0xc70f, 0x7cb0, 0x3cb2, 0xaf20, 0xae20,
+    0x4cb1, 0xc70f, 0x7cb0, 0x3cb3, 0x20b2, 0x4cb3, 0x2ab4, 0xe42b,
+    0xe012, 0xe42e, 0x36b0, 0x3eb1, 0xa201, 0x3eb2, 0x22b0, 0x4eb1,
+    0x5ab2, 0xe045, 0xf061, 0x2ab2, 0xa003, 0x3eb2, 0xa121, 0xf775,
+    0x2ab2, 0xf039, 0xa200, 0xe42e, 0xa103, 0x3eb2, 0xcc45, 0xa201,
+    0x3eb3, 0xe184, 0x0bda, 0x2ab3, 0xae03, 0x3eb3, 0x22b0, 0x4eb1,
+    0x5ab2, 0xe045, 0xf061, 0xe013, 0xe04a, 0x2ab3, 0xa003, 0x3eb3,
+    0x2ab2, 0xa103, 0x3eb2, 0x28b3, 0xe42e, 0xae02, 0x34b1, 0xe008,
+    0xffff, 0xaf02, 0x3cb0, 0x82b1, 0xe018, 0xae1e, 0x82b0, 0xe01c,
+    0xe42e, 0xae02, 0x34b1, 0xe008, 0xffff, 0xaf02, 0x3cb0, 0x82b0,
+    0xe018, 0xaf1e, 0x82b1, 0xe01c, 0xe42e, 0xae02, 0x34b1, 0xe008,
+    0xffff, 0xaf02, 0x3cb0, 0x82b1, 0xe018, 0xa103, 0x3eb2, 0x58b2,
+    0x82b0, 0xa11f, 0xe013, 0x3eb2, 0xe019, 0x5eb2, 0xe042, 0xe42e,
+    0x34bd, 0x3cbc, 0x28bd, 0xa002, 0x3cbd, 0x2cbc, 0xc710, 0x7cbd,
+    0xe008, 0xffff, 0xa002, 0xaf02, 0x3c8b, 0x18bb, 0xe42a, 0x288b,
+    0x3cbb, 0x28bc, 0x2abd, 0x3c17, 0x3e18, 0x8418, 0xe182, 0x7530,
+    0xe018, 0xae02, 0x2e17, 0xe41e, 0x0bb2, 0x3c98, 0x8498, 0x8280,
+    0xe018, 0xa279, 0xe41e, 0x0b9b, 0x3498, 0x3c99, 0xae06, 0x2a84,
+    0xe41e, 0x0b9b, 0x349e, 0x3c9f, 0xa200, 0x3cb5, 0x34a2, 0x3ca3,
+    0x2889, 0xe428, 0xe016, 0x3c8a, 0x288b, 0x3c89, 0xe42e, 0x3cb7,
+    0x2a89, 0xe046, 0xf028, 0xe42e, 0x28b6, 0x2ab7, 0xe046, 0xf034,
+    0xa200, 0x3cb6, 0x28b7, 0x3c89, 0x3c14, 0x2815, 0xe42a, 0x2889,
+    0xe016, 0x3c8a, 0xf03a, 0x2a8b, 0x3e89, 0x2a89, 0x28b6, 0xe045,
+    0xf0c6, 0x20a6, 0x4ca7, 0xe41e, 0x0b9b, 0x34aa, 0x3cab, 0x10a6,
+    0x1ca7, 0xe012, 0x34a8, 0x3ca9, 0xe42e, 0x3cba, 0x2815, 0xe42a,
+    0x2880, 0x2aba, 0xe046, 0xe42a, 0x3e80, 0x8418, 0xe182, 0x7530,
+    0xe018, 0xae02, 0x2e17, 0xe41e, 0x0bb2, 0x3c98, 0x8498, 0x8280,
+    0xe018, 0xa279, 0xe41e, 0x0b9b, 0x3498, 0x3c99, 0xae06, 0x2a84,
+    0xe41e, 0x0b9b, 0x349e, 0x3c9f, 0xa200, 0x3cb5, 0x34a2, 0x3ca3,
+    0xe42e, 0x2a15, 0xe42b, 0xf042, 0xa201, 0x3eb8, 0xe42e, 0x3cb9,
+    0x3c90, 0xa203, 0x3eb8, 0xe42e, 0xe0c1, 0x0060, 0xa803, 0xf05b,
+    0xe0c0, 0x0061, 0xe41e, 0x0c3f, 0xe0c1, 0x0060, 0xa805, 0xf05b,
+    0xe0c0, 0x0062, 0xe41e, 0x0c89, 0xe0c1, 0x0060, 0xa809, 0xf05b,
+    0xe0c0, 0x0063, 0xe41e, 0x0c65, 0xe0c1, 0x0060, 0xa811, 0xf05b,
+    0xe0c0, 0x0064, 0xe41e, 0x0c08, 0xe0c1, 0x0060, 0xa821, 0xf04b,
+    0xe0c0, 0x0065, 0x3c1c, 0xe0c1, 0x0060, 0xa841, 0xf08b, 0xe0c0,
+    0x0066, 0x3037, 0xaf02, 0x3038, 0xaf02, 0x3c39, 0xe42e, 0xa200,
+    0x3c63, 0xe42e, 0xe161, 0x0100, 0xa200, 0xe188, 0x007f, 0x3d11,
+    0xe41e, 0x0d0c, 0xe42e, 0x2863, 0xe41a, 0x0d0c, 0x2863, 0xe000,
+    0x0101, 0xe09c, 0x2860, 0xae02, 0x4c61, 0xae02, 0x4d0e, 0xae02,
+    0x4d06, 0xae02, 0x4c60, 0x3c64, 0x2863, 0xe000, 0x0180, 0xe09c,
+    0x2906, 0x3c62, 0xe42e, 0x2853, 0xa806, 0xae04, 0xe000, 0x0200,
+    0xe092, 0x2863, 0xe000, 0x0100, 0xe09c, 0x2906, 0x3c61, 0x2826,
+    0xe016, 0x4d01, 0xa802, 0x3d06, 0x3c60, 0x2863, 0xa002, 0x3c63,
+    0x1850, 0xe428, 0x3c63, 0xe42e, 0xcb04, 0xaf20, 0xe000, 0x0180,
+    0xe09c, 0xcb54, 0x3d06, 0xe42e, 0xa200, 0x3c60, 0x3c61, 0xe42e,
+    0xa200, 0x3cc2, 0x3cc4, 0x3cc5, 0xe42e, 0xa200, 0x3c1d, 0xe42e,
+    0xa200, 0x3c4d, 0xe0c0, 0x0060, 0x344a, 0x3c4b, 0xe0c0, 0x0061,
+    0xae04, 0x3c4c, 0xe41e, 0x0d2c, 0xe41e, 0x0db3, 0xd071, 0x802a,
+    0xe181, 0xe41e, 0x0658, 0xe42e, 0xd030, 0x0000, 0xd034, 0x0000,
+    0xd033, 0x0000, 0xd035, 0x0000, 0xd036, 0x00ff, 0xd037, 0x0080,
+    0xd038, 0x0000, 0xa200, 0x3c49, 0xe42e, 0xe41e, 0x06af, 0x2849,
+    0xf068, 0xa202, 0x3c49, 0xd037, 0x0000, 0xe470, 0xa200, 0x3c49,
+    0xd037, 0x0080, 0xe470, 0xd141, 0x0000, 0xe41e, 0x06af, 0xd037,
+    0x0000, 0xe470, 0xd141, 0x0100, 0xe41e, 0x06af, 0xd037, 0x0080,
+    0xe470, 0xd111, 0x0680, 0xe082, 0x3c4e, 0xe004, 0x0048, 0xe092,
+    0xe41e, 0x0dbd, 0x204a, 0x4c4b, 0x2e4d, 0xae11, 0xe042, 0xce20,
+    0x8111, 0x9f01, 0xd112, 0x0100, 0xe0c0, 0x0043, 0xa806, 0xae02,
+    0xa000, 0xce26, 0xca28, 0xf7f8, 0xa200, 0xe0c2, 0x0074, 0x2c4d,
+    0xe000, 0x0002, 0x3c4d, 0x1c4c, 0xf064, 0x2abf, 0xe01b, 0xe0c3,
+    0x0074, 0x3c4d, 0x204a, 0x4c4b, 0x2e4d, 0xae11, 0xe042, 0x9f01,
+    0x284e, 0xe092, 0xe42e, 0xe41e, 0x0d59, 0xe004, 0x0049, 0xe092,
+    0x9e01, 0x0840, 0xe002, 0x0200, 0x9f01, 0xe42e, 0xd111, 0x0680,
+    0xe004, 0x0048, 0xe092, 0xe41e, 0x0dbd, 0x204a, 0x4c4b, 0x2e4d,
+    0xae11, 0xe042, 0xce20, 0x8111, 0x9f01, 0xd112, 0x0100, 0xe0c0,
+    0x0043, 0xa806, 0xae02, 0xa000, 0xce26, 0xca28, 0xf7f8, 0x9e01,
+    0x0840, 0x9f01, 0xe42e, 0x204a, 0x4c4b, 0x2e4d, 0xae11, 0xe042,
+    0xe005, 0x0049, 0xe093, 0x9f01, 0xe42e, 0xe0c1, 0x0043, 0xa809,
+    0xe429, 0x2abf, 0xe429, 0xa200, 0x3c4f, 0x204a, 0x4c4b, 0x2e4d,
+    0xae11, 0xe042, 0x9e81, 0xe045, 0xf041, 0x2c4c, 0xae10, 0xe041,
+    0xe003, 0x0200, 0xe421, 0x284f, 0xf718, 0xe0c0, 0x005c, 0xe008,
+    0x8000, 0xf6ca, 0xe0c0, 0x005d, 0xe00a, 0x8000, 0xe0c2, 0x005d,
+    0xa202, 0xce00, 0x3c4f, 0xf62e, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0x000f, 0x0d0b, 0x0907, 0x0501, 0x000f, 0x0d0b, 0x0907, 0x0501,
+    0x001e, 0x1a16, 0x120e, 0x0a02, 0x001e, 0x1a16, 0x120e, 0x0a02,
+    0x002d, 0x2721, 0x1b15, 0x0f03, 0x003c, 0x342c, 0x241c, 0x1404,
+    0x004b, 0x4137, 0x2d23, 0x1905, 0x005a, 0x4e42, 0x362a, 0x1e06,
+    0x0069, 0x5b4d, 0x3f31, 0x2307, 0x0078, 0x6858, 0x4838, 0x2808,
+    0x0087, 0x7563, 0x513f, 0x2d09, 0x00a5, 0x8f79, 0x634d, 0x370b,
+    0x00c3, 0xa98f, 0x755b, 0x410d, 0x00e1, 0xc3a5, 0x8769, 0x4b0f,
+    0x00e1, 0xc3a5, 0x8769, 0x4b0f, 0x00e1, 0xc3a5, 0x8769, 0x4b0f,
+    0x0020, 0x0008, 0x0008, 0x0008, 0x0030, 0x0008, 0x0010, 0x0008,
+    0x0030, 0x0008, 0x0010, 0x0008, 0x0040, 0x0008, 0x0018, 0x0008,
+    0x0050, 0x0010, 0x0018, 0x0010, 0x0060, 0x0018, 0x0020, 0x0018,
+    0x0080, 0x0018, 0x0040, 0x0018, 0x00a0, 0x0020, 0x0060, 0x0020,
+    0x00c0, 0x0030, 0x0080, 0x0030, 0x0100, 0x0040, 0x00c0, 0x0040,
+    0x0140, 0x0060, 0x0100, 0x0060, 0x0180, 0x0070, 0x0140, 0x0070,
+    0x01c0, 0x0080, 0x0180, 0x0080, 0x0200, 0x00a0, 0x01c0, 0x00a0,
+    0x0300, 0x0180, 0x0200, 0x0180, 0x0400, 0x0200, 0x0240, 0x0200,
+    0x0080, 0x00a0, 0x00c0, 0x0100, 0x0180, 0x0200, 0x0300, 0x0400,
+    0x0500, 0x0600, 0x0800, 0x0a00, 0x0c00, 0x0000, 0x0000, 0x0000,
+    0x0028, 0x0027, 0x0027, 0x0026, 0x0026, 0x0025, 0x0024, 0x0023,
+    0x0022, 0x0021, 0x0020, 0x001f, 0x001e, 0x001d, 0x001c, 0x001b,
+    0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
+    0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f,
+    0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017,
+    0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001d, 0x001e,
+    0x001f, 0x0020, 0x0020, 0x0021, 0x0022, 0x0022, 0x0023, 0x0023,
+    0x0024, 0x0024, 0x0025, 0x0025, 0x0025, 0x0026, 0x0026, 0x0026,
+    0x0027, 0x0027, 0x0027, 0x0027, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
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+    0xd111, 0x0000, 0xd112, 0x0800, 0xd113, 0x0001, 0xca28, 0xf7f8,
+    0xe0c0, 0x0041, 0xe005, 0x0040, 0xae11, 0xe042, 0xe0c1, 0x005a,
+    0xae15, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0100, 0xd113,
+    0x0009, 0xca28, 0xf7f8, 0xe161, 0x00f0, 0x8911, 0x0034, 0x8911,
+    0x0033, 0x8911, 0x0035, 0x8911, 0x0036, 0x8911, 0x0037, 0x8911,
+    0x0038, 0x2111, 0x4d11, 0xcc60, 0x2111, 0x4d11, 0xcc62, 0x2111,
+    0x4d11, 0xcc64, 0x2111, 0x4d11, 0xcc72, 0x2111, 0x4d11, 0xce88,
+    0xe42e, 0xe161, 0x00f0, 0x8b11, 0x0034, 0x8b11, 0x0033, 0x8b11,
+    0x0035, 0x8b11, 0x0036, 0x8b11, 0x0037, 0x8b11, 0x0038, 0xc860,
+    0x3511, 0x3d11, 0xc862, 0x3511, 0x3d11, 0xc864, 0x3511, 0x3d11,
+    0xc872, 0x3511, 0x3d11, 0xca88, 0x3511, 0x3d11, 0xe0c0, 0x0041,
+    0xe005, 0x0000, 0xae11, 0xe042, 0x2aee, 0xae19, 0xe042, 0xce20,
+    0xd111, 0x0000, 0xd112, 0x0800, 0xd113, 0x0000, 0xca28, 0xf7f8,
+    0xe0c0, 0x0041, 0xe005, 0x0040, 0xae11, 0xe042, 0x2aee, 0xae15,
+    0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0100, 0xd113, 0x0008,
+    0xca28, 0xf7f8, 0xe42e, 0xe40e, 0x03e5, 0xe40e, 0x014b, 0xe40e,
+    0x014f, 0xe40e, 0x0153, 0xe40e, 0x015b, 0xe40e, 0x0059, 0xe40e,
+    0x0059, 0xe40e, 0x015f, 0xe40e, 0x0059, 0xe40e, 0x0059, 0xe40e,
+    0x0059, 0xe40e, 0x0059, 0xe40e, 0x0059, 0xe40e, 0x0059, 0xe40e,
+    0x0059, 0xe40e, 0x0059, 0xe41e, 0x0171, 0xe40e, 0x0059, 0xe41e,
+    0x01bc, 0xe40e, 0x0059, 0x2806, 0xa184, 0xe41a, 0x0163, 0xe41e,
+    0x01bd, 0xe40e, 0x0059, 0xe41e, 0x024f, 0xe40e, 0x0059, 0xe41e,
+    0x0261, 0xe40e, 0x0059, 0xe0c0, 0x0040, 0xa219, 0xae15, 0xe042,
+    0xce20, 0xd111, 0x0000, 0xd112, 0x1800, 0xd113, 0x0005, 0xe1e1,
+    0xe42e, 0xd130, 0x0000, 0xa200, 0xc401, 0xe188, 0x07ff, 0x3d11,
+    0xe41e, 0x027d, 0xa2fe, 0x3c10, 0x3c20, 0x3c48, 0xa200, 0x3cd6,
+    0xa200, 0x3c4d, 0xe41e, 0x037a, 0xe41e, 0x0aaf, 0xe41e, 0x106b,
+    0xe41e, 0x029b, 0x28ad, 0xa10e, 0xf7c8, 0xe41e, 0x0ac2, 0xe41e,
+    0x0394, 0xe128, 0xe41e, 0x0580, 0xf74a, 0xa2fe, 0x3c10, 0x2050,
+    0x4c51, 0xae08, 0xe0c2, 0x0071, 0xa200, 0xe0c2, 0x0072, 0xe0c0,
+    0x0062, 0xaf02, 0x301e, 0xf0da, 0x2813, 0xa104, 0xf0aa, 0x28df,
+    0xa004, 0xe0c2, 0x0073, 0x28de, 0x3cdc, 0xe0c2, 0x0074, 0xf09e,
+    0x2816, 0xa004, 0xe0c2, 0x0073, 0xa200, 0xe0c2, 0x0074, 0x3cdc,
+    0xa202, 0xe0c2, 0x0070, 0xe42e, 0xe42e, 0xa200, 0xcc4a, 0xcc4c,
+    0x3c4e, 0xe41e, 0x109e, 0xe40a, 0x0230, 0xd130, 0x0000, 0xd1e0,
+    0x0003, 0xd1ff, 0x03b0, 0xd199, 0x0224, 0xd03a, 0x0000, 0xd04b,
+    0x0001, 0xd04c, 0x0000, 0xd008, 0x0000, 0xa202, 0x3c49, 0x282f,
+    0xe002, 0x00a8, 0xf028, 0xe190, 0xe41e, 0x029b, 0x28ad, 0xf7da,
+    0xa102, 0xf30a, 0xa108, 0xf794, 0xf2da, 0xa102, 0xf17a, 0xa102,
+    0xf0fa, 0xa102, 0xf10a, 0xa102, 0xf14a, 0xa102, 0xf16a, 0xa102,
+    0xf14a, 0xa102, 0xf13a, 0xa10e, 0xf682, 0xe40e, 0x0210, 0xe41e,
+    0x0ac2, 0xf17e, 0xe41e, 0x0ae9, 0xf14e, 0xe41e, 0x07ce, 0xf11e,
+    0xba44, 0xe41e, 0x04ab, 0xf0de, 0xf0ce, 0xba0e, 0xe002, 0x00ff,
+    0xf058, 0xba4e, 0xe41e, 0x033d, 0xf798, 0xe41e, 0x04ab, 0xf4de,
+    0xf4ce, 0xa2fe, 0x3cc1, 0xe41e, 0x0bdc, 0xf47a, 0xa200, 0x3c49,
+    0xe41e, 0x10c6, 0x282f, 0xa002, 0x3c2f, 0x28ac, 0x4c34, 0xf048,
+    0x28c1, 0xe41e, 0x1071, 0x28ac, 0xe418, 0x0d45, 0x2834, 0xe41a,
+    0x0965, 0x28d3, 0x3cd7, 0x2832, 0xf04a, 0x2834, 0xe40a, 0x01d5,
+    0xe41e, 0x098e, 0xe404, 0x01d5, 0xe0c2, 0x0071, 0x2848, 0xe412,
+    0x107f, 0xe0c0, 0x0071, 0x3c48, 0x2830, 0xe0c2, 0x0073, 0x284e,
+    0xe0c2, 0x0072, 0x2c4d, 0xa002, 0x3c4d, 0xe0c2, 0x0070, 0xc84a,
+    0xc84d, 0xae20, 0xe056, 0xe0c2, 0x0053, 0xa202, 0xe42e, 0xe0c0,
+    0x0042, 0xce20, 0xd111, 0x0600, 0xd112, 0x0100, 0xd113, 0x0001,
+    0xca28, 0xf7f8, 0xe0c0, 0x0060, 0x3cd4, 0xe0c0, 0x0061, 0x3c70,
+    0xe42e, 0xe0c0, 0x0042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0080,
+    0xd113, 0x0009, 0xca28, 0xf7f8, 0xe0c0, 0x0061, 0x3ca5, 0xa202,
+    0x3ca2, 0xe41e, 0x0394, 0xe128, 0xe0c0, 0x0060, 0xf048, 0xe41e,
+    0x0ac2, 0xf03e, 0xe41e, 0x0ae9, 0xe42e, 0xe0c0, 0x0040, 0xe000,
+    0x2e00, 0xce20, 0xd111, 0x0500, 0xd112, 0x0100, 0xd113, 0x0001,
+    0xca28, 0xf7f8, 0xe42e, 0xe164, 0x0700, 0x2514, 0x4d14, 0xce88,
+    0xa208, 0x3ca0, 0xd142, 0x01ff, 0xd143, 0x01ff, 0xd140, 0x0700,
+    0xd141, 0x0000, 0xe42e, 0x28a0, 0xaf02, 0xe000, 0x0700, 0xe098,
+    0x28a0, 0xa802, 0x3ca1, 0xca88, 0xaf10, 0xa102, 0xf04a, 0xe41e,
+    0x0320, 0xf7ae, 0xca88, 0xe008, 0x00ff, 0x3c00, 0xaf0e, 0xf788,
+    0x2800, 0xaf0a, 0x3cac, 0x2800, 0xa83e, 0x3cad, 0xa10a, 0xe016,
+    0x3cae, 0xe088, 0xe002, 0x0700, 0xae02, 0x08a1, 0x3ca0, 0xa200,
+    0x3ca6, 0x3ca5, 0x3ca7, 0xd149, 0x0000, 0x88a0, 0x0146, 0xe41e,
+    0x02d2, 0xe41e, 0x0394, 0xe128, 0xe42e, 0x88a4, 0x0149, 0xe41e,
+    0x02d2, 0xe42e, 0x28a7, 0x44a8, 0xf048, 0xd141, 0x0000, 0xf03e,
+    0xd141, 0x0100, 0xd140, 0x0700, 0x88a0, 0x0146, 0xd143, 0x01ff,
+    0xd147, 0x0000, 0xd148, 0x0000, 0xca94, 0xf7fa, 0xa106, 0xf0b4,
+    0xe41e, 0x0407, 0xd146, 0x0000, 0xd148, 0x0000, 0xca94, 0xf7fa,
+    0xa106, 0xf77a, 0xca94, 0xa802, 0xca8f, 0xa803, 0xf0f8, 0xf0eb,
+    0xca8c, 0xe002, 0x0200, 0xf068, 0xe41e, 0x0407, 0xa200, 0x3ca0,
+    0xce8c, 0xd148, 0x0000, 0xca94, 0xf7fa, 0xca94, 0xa802, 0x3ca2,
+    0xcc92, 0xca8c, 0x3ca0, 0xca8e, 0x00a6, 0x0ca5, 0x34a6, 0x3ca5,
+    0xcc90, 0x8aa4, 0x0149, 0xca8e, 0xe41a, 0x0320, 0x28a0, 0xe002,
+    0x0200, 0xe428, 0xe41e, 0x0407, 0xa200, 0x3ca0, 0xce8c, 0xe42e,
+    0x2aa1, 0x2904, 0xf099, 0xaf10, 0xca89, 0xae11, 0xe055, 0xce89,
+    0xa203, 0x3ea1, 0xe42e, 0xe008, 0x00ff, 0xca89, 0xae11, 0xe055,
+    0xce89, 0xa201, 0x3ea1, 0x8114, 0xe089, 0xe003, 0x0800, 0xe429,
+    0xe41e, 0x0407, 0xe164, 0x0700, 0xe42e, 0x28a2, 0xe016, 0xc871,
+    0xa011, 0xe428, 0xaf07, 0xe009, 0x07ff, 0x28a5, 0xe008, 0x07ff,
+    0xe046, 0xf08a, 0xe049, 0xe011, 0xaf15, 0xe421, 0xe420, 0xa200,
+    0xe42e, 0xc868, 0xa80e, 0xf028, 0xa210, 0x3c95, 0x7895, 0xa203,
+    0x5a95, 0xaf03, 0xe046, 0xe42e, 0xe161, 0x05d1, 0x2901, 0xc871,
+    0xa011, 0xaf07, 0xe009, 0x07ff, 0xe008, 0x07ff, 0xe046, 0xf08a,
+    0xe049, 0xe011, 0xaf15, 0xe421, 0xe420, 0xa200, 0xe42e, 0xc868,
+    0xa80e, 0xf028, 0xa210, 0x3c95, 0x7895, 0xa203, 0x5a95, 0xaf03,
+    0xe046, 0xe42e, 0xa200, 0x3c9b, 0xe0c0, 0x0060, 0x3498, 0x3c99,
+    0xe0c0, 0x0061, 0xae04, 0x3c9a, 0xe41e, 0x0394, 0xe41e, 0x042f,
+    0xa200, 0x3c6b, 0xe41e, 0x03a3, 0xd071, 0x002a, 0xe181, 0xe41e,
+    0x0407, 0xe41e, 0x028b, 0xe42e, 0xd030, 0x0000, 0xd034, 0x0000,
+    0xd033, 0x0000, 0xd035, 0x0000, 0xd036, 0x007f, 0xd037, 0x0000,
+    0xd038, 0x0000, 0xe42e, 0x3c6c, 0xe08e, 0x3c6d, 0xe41e, 0x03af,
+    0xe41e, 0x03ca, 0x286d, 0xe09e, 0x286c, 0x3c6b, 0xe42e, 0x286b,
+    0xae08, 0xe000, 0x0470, 0xe09e, 0x8b17, 0x0033, 0x8b17, 0x0034,
+    0x8b17, 0x0035, 0x8b17, 0x0036, 0x8b17, 0x0037, 0x8b17, 0x0038,
+    0xc860, 0x3517, 0x3d17, 0xc862, 0x3517, 0x3d17, 0xc864, 0x3517,
+    0x3d17, 0xe42e, 0x286c, 0xae08, 0xe000, 0x0470, 0xe09e, 0x8917,
+    0x0033, 0x8917, 0x0034, 0x8917, 0x0035, 0x8917, 0x0036, 0x8917,
+    0x0037, 0x8917, 0x0038, 0x2117, 0x4d17, 0xcc60, 0x2117, 0x4d17,
+    0xcc62, 0x2117, 0x4d17, 0xcc64, 0xe42e, 0xc000, 0x286b, 0xf05a,
+    0xa102, 0xf1ca, 0xa102, 0xf1aa, 0x28a2, 0xf158, 0xe41e, 0x02cd,
+    0x28a7, 0xf11a, 0x28a8, 0xf088, 0xa202, 0x3ca8, 0xd037, 0x0000,
+    0xd04c, 0x0000, 0xe470, 0xa200, 0x3ca8, 0xd037, 0x0080, 0xd04c,
+    0x0000, 0xe470, 0xd04c, 0x0000, 0xe470, 0xe40e, 0x0b0f, 0xd111,
+    0x0700, 0xe082, 0x3c9c, 0xe0c0, 0x005a, 0xae02, 0xe000, 0x0048,
+    0xe092, 0xe41e, 0x043c, 0x2098, 0x4c99, 0x2e9b, 0xae11, 0xe042,
+    0xce20, 0x9f01, 0xd112, 0x0100, 0xa202, 0xe0c1, 0x0043, 0xa803,
+    0xb676, 0xce26, 0xca28, 0xe408, 0x0422, 0x2c9b, 0xe000, 0x0002,
+    0x3c9b, 0x1c9a, 0xf024, 0x3c9b, 0x289c, 0xe092, 0xe42e, 0x2098,
+    0x4c99, 0x2e9b, 0xae11, 0xe042, 0xe0c1, 0x005a, 0xae03, 0xe001,
+    0x0048, 0xe093, 0x9f01, 0xe42e, 0xe0c1, 0x0043, 0xa805, 0xe429,
+    0xa200, 0x3c9d, 0x2098, 0x4c99, 0x2e9b, 0xae11, 0xe042, 0x8111,
+    0x9e89, 0xe045, 0xf043, 0x2c9a, 0xae10, 0xe041, 0xe003, 0x0200,
+    0xe421, 0x289d, 0xf708, 0xe0c0, 0x005c, 0xe008, 0x4000, 0xf6ba,
+    0xe0c0, 0x005d, 0xe00a, 0x4000, 0xe0c2, 0x005d, 0xa202, 0xce00,
+    0x3c9d, 0xf61e, 0xba0c, 0xf03a, 0xbcfc, 0xe42e, 0xba4c, 0xa20c,
+    0x3c96, 0x2896, 0xa002, 0x3c96, 0xa140, 0xf0d2, 0xba40, 0xf7aa,
+    0x5896, 0xa102, 0x349e, 0x3c9f, 0x2896, 0xe41e, 0x049f, 0x009e,
+    0x0c9f, 0xe42e, 0xe16b, 0xe42e, 0xba0c, 0xf03a, 0xbe7e, 0xe42e,
+    0xba4c, 0xa20c, 0x3c96, 0x2896, 0xa002, 0x3c96, 0xa140, 0xf162,
+    0xba40, 0xf7aa, 0x5896, 0xa102, 0x349e, 0x3c9f, 0x2896, 0xe41e,
+    0x049f, 0x009e, 0x0c9f, 0x3c9f, 0x8c9f, 0x0000, 0xa002, 0xaf02,
+    0xe012, 0xe42c, 0xe012, 0xe16a, 0xe42e, 0xe16b, 0xe42e, 0xa120,
+    0xf050, 0xa020, 0x3c97, 0x7497, 0xe42e, 0x3c97, 0xba5e, 0x5897,
+    0x7697, 0xe056, 0xe42e, 0xba40, 0xe42a, 0xc868, 0xa80e, 0x3c00,
+    0xe016, 0xe428, 0x7400, 0xe016, 0xe42e, 0x2a30, 0xa103, 0x2826,
+    0xe425, 0xf02b, 0x2827, 0xb7f4, 0xa002, 0x3c46, 0xa104, 0xe424,
+    0xf04a, 0xa25a, 0x3c47, 0xe42e, 0xbc0e, 0x3c00, 0xe42d, 0x281f,
+    0xf02a, 0xbc0e, 0x3c01, 0xe42d, 0x2801, 0xae06, 0x4c00, 0x3c47,
+    0xe161, 0x02d0, 0x8840, 0x0022, 0xe41e, 0x0547, 0xe42d, 0x2830,
+    0xa104, 0xe428, 0x2841, 0xe161, 0x0390, 0x8841, 0x0022, 0xe41e,
+    0x0547, 0xe42e, 0xcb02, 0x3067, 0xaf02, 0x3065, 0xe004, 0x007f,
+    0x3c00, 0xa002, 0xe012, 0x3c01, 0xe004, 0x03ff, 0x3c02, 0xa002,
+    0xe012, 0x3c03, 0xa21e, 0x3c0c, 0xc440, 0xe161, 0x02d0, 0xcbd8,
+    0x5c0c, 0xa83e, 0x3c0d, 0xcbda, 0x5c0c, 0xa83e, 0x3c0e, 0x280d,
+    0xe41e, 0x1433, 0xf374, 0x280e, 0xe41e, 0x1433, 0xf334, 0x280d,
+    0x2a65, 0xf059, 0xa83c, 0xe000, 0x0140, 0xf04e, 0xae02, 0xe000,
+    0x0160, 0xe096, 0x280e, 0x2a65, 0xf059, 0xa83c, 0xe000, 0x0140,
+    0xf04e, 0xae02, 0xe000, 0x0160, 0xe098, 0x2113, 0x4d0b, 0x1114,
+    0x1d0c, 0xf18a, 0x2a3a, 0x4665, 0x20c7, 0x4cc8, 0xf07b, 0x2a67,
+    0x20c9, 0x4cca, 0xf03b, 0x20cb, 0x4ccc, 0xe41e, 0x1410, 0xaf04,
+    0xe000, 0x0040, 0xf074, 0xe002, 0x00c0, 0xf040, 0xe000, 0x0080,
+    0xf02e, 0xa240, 0x3c08, 0xe004, 0x0040, 0x1808, 0x3d11, 0x2808,
+    0x3d11, 0x280c, 0xa10a, 0x3c0c, 0xe402, 0x04f7, 0xe42e, 0xe004,
+    0x01ff, 0x3c02, 0xaf02, 0x3c03, 0xe184, 0x057e, 0xba40, 0xf0aa,
+    0xe41e, 0x047c, 0x4402, 0x3d11, 0xe41e, 0x047c, 0x4403, 0x3d11,
+    0xf06e, 0xa202, 0x5800, 0x3d11, 0xa200, 0x3d11, 0x281f, 0xf058,
+    0xe082, 0xa008, 0xe092, 0xf1be, 0xba40, 0xf12a, 0xe41e, 0x047c,
+    0x4402, 0x3d11, 0xe41e, 0x047c, 0x4403, 0x3d11, 0xe41e, 0x047c,
+    0x4402, 0x3d11, 0xe41e, 0x047c, 0x4403, 0x3d11, 0xf08e, 0xa202,
+    0x5801, 0x3d11, 0xa201, 0x3f11, 0x3d11, 0x3f11, 0xe190, 0xe42e,
+    0xba4e, 0x3c06, 0xa1c8, 0xba41, 0xba41, 0xba41, 0xf01a, 0xba40,
+    0xba46, 0xe408, 0x0634, 0xba4e, 0x3c1c, 0xbc3e, 0x3c10, 0xa202,
+    0x3c1f, 0x2806, 0xa1c8, 0xf2f8, 0xbc06, 0x3c1f, 0xbc08, 0xe408,
+    0x0634, 0xbc08, 0xe408, 0x0634, 0xba40, 0xba40, 0x3cb8, 0xf23a,
+    0xa201, 0x3eba, 0x3ebc, 0xe160, 0x0000, 0xba40, 0xf11a, 0x2aba,
+    0xae03, 0xe056, 0x3cba, 0xe080, 0xe41e, 0x0775, 0x2abc, 0xae03,
+    0xe056, 0x3cbc, 0xe080, 0xa201, 0xe41e, 0x07a8, 0xf07e, 0x2aba,
+    0xae03, 0x3eba, 0x2abc, 0xae03, 0x3ebc, 0xe080, 0xa002, 0xe090,
+    0xa110, 0xf648, 0xbc18, 0xe40d, 0x0634, 0xa008, 0x3c11, 0xa202,
+    0x5811, 0x3c12, 0xbc04, 0x3c13, 0xe40d, 0x0634, 0xa102, 0xf034,
+    0xf06a, 0xf21e, 0xbc18, 0xa008, 0x3c14, 0xf1de, 0xba40, 0x3c15,
+    0xe41e, 0x047c, 0x34e8, 0x3ce9, 0xe41e, 0x047c, 0x34ea, 0x3ceb,
+    0xbdfe, 0xe40d, 0x0634, 0x3cec, 0xf0ea, 0xa102, 0xcc44, 0xe162,
+    0x0250, 0xe184, 0x05ee, 0xe41e, 0x047c, 0x3512, 0x3d12, 0xe41e,
+    0x0703, 0xf01e, 0xe40d, 0x0634, 0xbc20, 0xe40d, 0x0634, 0x3c16,
+    0xba40, 0x3c17, 0xbcee, 0xf39d, 0xa002, 0x3c50, 0xbc86, 0xf35d,
+    0xa002, 0x3c51, 0x8450, 0x8251, 0xe018, 0x3c1b, 0xa200, 0x3c19,
+    0xba40, 0x3c18, 0xf098, 0xba40, 0x3c19, 0x2851, 0xae02, 0x3c51,
+    0x281b, 0xae02, 0x3c1b, 0xe41e, 0x06c0, 0xba40, 0x3c1a, 0x4c18,
+    0xf1ca, 0xba40, 0xf0aa, 0xe41e, 0x0462, 0xe41e, 0x0462, 0xe41e,
+    0x0462, 0xe41e, 0x0462, 0xf11d, 0xa200, 0x3c8b, 0x3c8c, 0x281d,
+    0x3cde, 0x3cdf, 0xba40, 0xe016, 0xe41a, 0x0717, 0xf06a, 0xe41e,
+    0x04ab, 0xf03a, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0xe41e,
+    0x0462, 0x3c20, 0xbc3e, 0xe40d, 0x06bd, 0x1810, 0xf0ea, 0x0810,
+    0x3c10, 0xe41e, 0x0ada, 0x3c6e, 0xa202, 0xe41e, 0x03a3, 0xa203,
+    0x3e94, 0x286e, 0xe40a, 0x06bd, 0xba40, 0x3c21, 0xba40, 0x3c22,
+    0xbc0e, 0xe40d, 0x06bd, 0x3c23, 0xe408, 0x06bd, 0xbc3e, 0xe40d,
+    0x06bd, 0x3c24, 0xbc3e, 0x3c25, 0xe40d, 0x06bd, 0xba40, 0x3c26,
+    0xba42, 0x3c27, 0xbe34, 0xe40d, 0x06bd, 0xa034, 0x3c28, 0xe404,
+    0x06bd, 0xa168, 0xe402, 0x06bd, 0xbe34, 0xe40d, 0x06bd, 0xa034,
+    0xe404, 0x06bd, 0xa168, 0xe402, 0x06bd, 0xbe18, 0xe40d, 0x06bd,
+    0x3c29, 0x3c2d, 0xba40, 0x3c2a, 0xba40, 0x3c2b, 0xba40, 0x3c2c,
+    0xa200, 0x3c2e, 0x3cb9, 0x2820, 0x3c02, 0xe41e, 0x0b8e, 0xe41e,
+    0x035c, 0xf2fa, 0xba40, 0x3c2e, 0xba40, 0x3cb9, 0xf28a, 0xa201,
+    0x3ebb, 0x3ebd, 0xe160, 0x0000, 0xe080, 0xa10c, 0x182e, 0x182e,
+    0xf132, 0xba40, 0xf11a, 0x2abb, 0xae03, 0xe056, 0x3cbb, 0xe080,
+    0xe41e, 0x0775, 0x2abd, 0xae03, 0xe056, 0x3cbd, 0xe080, 0xa203,
+    0xe41e, 0x07a8, 0xf07e, 0x2abb, 0xae03, 0x3ebb, 0x2abd, 0xae03,
+    0x3ebd, 0xe080, 0xa002, 0xe090, 0xa110, 0xf5f8, 0xbe18, 0x3c2d,
+    0xe41e, 0x04ab, 0xf03a, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e,
+    0x281c, 0xa114, 0xf146, 0xa102, 0xf156, 0xa112, 0xf166, 0xa102,
+    0xf176, 0xa112, 0xf186, 0xa102, 0xf196, 0xa102, 0xf1a6, 0xa112,
+    0xf1b6, 0xa102, 0xf1c6, 0xe004, 0x17bb, 0xf1ce, 0xe004, 0x0129,
+    0xf19e, 0xe004, 0x02a3, 0xf16e, 0xe004, 0x06f6, 0xf13e, 0xe004,
+    0x0dec, 0xf10e, 0xe004, 0x17bb, 0xf0de, 0xe004, 0x17bb, 0xf0ae,
+    0xe004, 0x3c00, 0xf07e, 0xe004, 0x5e70, 0xf04e, 0xe004, 0x6600,
+    0xf01e, 0xae12, 0x841b, 0xe182, 0x0180, 0xe019, 0xc407, 0xd022,
+    0x000f, 0xe184, 0x06fd, 0xe046, 0xf034, 0x8117, 0xe190, 0xe08e,
+    0xa520, 0x3c1d, 0xe42e, 0xe0c0, 0x0041, 0xe0c1, 0x005a, 0xae1b,
+    0xe042, 0xe005, 0x0052, 0xae11, 0xe042, 0xce20, 0xd111, 0x0250,
+    0xd112, 0x0200, 0xd113, 0x0000, 0xca28, 0xf7f8, 0xe42e, 0xba40,
+    0xf07a, 0xba4e, 0xe002, 0x00ff, 0xf038, 0xba5e, 0xba5e, 0xba40,
+    0xf02a, 0xba40, 0xba40, 0xf08a, 0xba44, 0xba40, 0xba40, 0xf04a,
+    0xba4e, 0xba4e, 0xba4e, 0xba40, 0xf03a, 0xbc0a, 0xbc0a, 0xba40,
+    0xf05a, 0xba7e, 0xe190, 0xba7e, 0xba40, 0xba40, 0x3c8b, 0xe016,
+    0xe161, 0x04f4, 0xe41a, 0x075a, 0xf1ca, 0xba40, 0x3c8c, 0xe016,
+    0xe161, 0x04f9, 0xe41a, 0x075a, 0xf14a, 0x288b, 0x4c8c, 0xf02a,
+    0xba40, 0xba40, 0x3c8d, 0xba40, 0xf0aa, 0xba40, 0xbc20, 0xbc20,
+    0xbc20, 0xbc20, 0xbc20, 0x3cde, 0xbc20, 0x3cdf, 0xa202, 0xe42e,
+    0xa200, 0xe42e, 0xe41e, 0x0462, 0xcc44, 0xa002, 0x3d11, 0xba46,
+    0xba46, 0xe184, 0x0767, 0xe41e, 0x0462, 0xe41e, 0x0462, 0xba40,
+    0xba48, 0xa002, 0x3d11, 0xba48, 0xa002, 0x3d11, 0xba48, 0xa002,
+    0x3d11, 0xba48, 0x3d11, 0xa202, 0xe42e, 0xd022, 0x000f, 0xa10c,
+    0xf034, 0xd022, 0x003f, 0xe161, 0x05d0, 0xa210, 0x3c06, 0x3c07,
+    0xa200, 0x3c08, 0x3c09, 0xe09c, 0xe09e, 0xe184, 0x07a5, 0x2807,
+    0xf10a, 0xe41e, 0x047c, 0xe42d, 0x0806, 0xe000, 0x0100, 0xe008,
+    0x00ff, 0x3c07, 0x4c09, 0xe01a, 0xe016, 0xe09e, 0xa202, 0x3c09,
+    0x2807, 0xf028, 0x2806, 0x3c06, 0xe08d, 0xa003, 0xe09d, 0xa803,
+    0xf059, 0xe085, 0xae11, 0xe056, 0x3d11, 0xe094, 0xe08e, 0xe42e,
+    0x3e08, 0x3c06, 0xa211, 0x3e07, 0xa10c, 0xf064, 0xb690, 0xa00c,
+    0x3c06, 0xa240, 0x3c07, 0x2806, 0x2a08, 0xf02b, 0xa01c, 0xae08,
+    0x3c06, 0xe0c0, 0x0041, 0xe0c1, 0x005a, 0xae1b, 0xe042, 0xe005,
+    0x005f, 0xae11, 0xe042, 0x0806, 0xce20, 0xd111, 0x05d0, 0x2807,
+    0xce24, 0xd113, 0x0000, 0xca28, 0xf7f8, 0xe42e, 0xa200, 0xba4f,
+    0xe042, 0xe003, 0x00ff, 0xf7cb, 0x3c00, 0xa200, 0xba4f, 0xe042,
+    0xe003, 0x00ff, 0xf7cb, 0x3c01, 0xe41e, 0x07e5, 0xe42a, 0xe41e,
+    0x033d, 0xf6d8, 0xe41e, 0x04ab, 0xe42e, 0x2800, 0xf0ba, 0xa102,
+    0xf0ca, 0xa104, 0xf0da, 0xa102, 0xf0ea, 0xa102, 0xf0fa, 0xa200,
+    0xe42e, 0xe41e, 0x0808, 0xf0de, 0xe41e, 0x082f, 0xf0ae, 0xe41e,
+    0x0831, 0xf07e, 0xe41e, 0x0832, 0xf04e, 0xe41e, 0x0834, 0xf01e,
+    0xe40e, 0x0020, 0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x0131,
+    0xe470, 0xe190, 0xe40e, 0x0113, 0xe470, 0xe190, 0xe470, 0xe190,
+    0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+    0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x012f, 0xe40e, 0x0131,
+    0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058,
+    0xa200, 0xe0c2, 0x005a, 0x3cf0, 0x3cf1, 0xa2fe, 0x3cee, 0x3cef,
+    0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d, 0xce00, 0xf11e, 0xe0c0,
+    0x005c, 0xe0c1, 0x0059, 0x3eed, 0xa203, 0x5aed, 0xe052, 0xf08a,
+    0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00, 0xe41e,
+    0x008c, 0xe41e, 0x00ab, 0xe0c0, 0x005a, 0x18ee, 0xe0c1, 0x0059,
+    0xa115, 0xb636, 0x2aee, 0xb60a, 0xe418, 0x00fb, 0xe0c0, 0x005b,
+    0xe0c1, 0x005e, 0xae11, 0xe056, 0x18ef, 0xe0c1, 0x0059, 0xa117,
+    0xb636, 0xe418, 0x00b0, 0xe0c0, 0x005a, 0x18ee, 0x2aee, 0xb60a,
+    0xe0c1, 0x0059, 0xa117, 0xb636, 0xe418, 0x00f3, 0xd071, 0x802a,
+    0xe181, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100, 0xe0c0, 0x0059,
+    0xae02, 0xe000, 0x0113, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a,
+    0x3cee, 0xe41e, 0x0100, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11,
+    0xe056, 0x3cef, 0xe40e, 0x0037, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+    0x0058, 0xe0c2, 0x0008, 0xe0c0, 0x0059, 0xf7ea, 0xa11e, 0xf0e8,
+    0xa202, 0xe0c2, 0x0058, 0xe004, 0x093d, 0xe0c2, 0x0070, 0xa200,
+    0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xf6fe, 0xa202, 0xe0c2, 0x0008,
+    0xe0c2, 0x0058, 0xe42e, 0xd101, 0x0001, 0xc70f, 0xa000, 0xe42e,
+    0xa200, 0xe0c1, 0x005b, 0xf27b, 0xa220, 0xa103, 0xf2eb, 0xa230,
+    0xa103, 0xf2bb, 0xa23c, 0xa103, 0xf24b, 0xa258, 0xa103, 0xf25b,
+    0xa260, 0xa103, 0xf22b, 0xa200, 0xa103, 0xf1fb, 0xa26c, 0xa103,
+    0xf1cb, 0xe004, 0x003e, 0xa103, 0xf18b, 0xe004, 0x0044, 0xa105,
+    0xf14b, 0xe004, 0x0046, 0xa103, 0xf10b, 0xe004, 0x0000, 0xa107,
+    0xf0cb, 0xa200, 0xe0c1, 0x005e, 0xf08b, 0xe004, 0x004c, 0xf05e,
+    0xe0c1, 0x005e, 0xf02b, 0xa010, 0xae16, 0xe0c1, 0x0040, 0xe041,
+    0xca28, 0xf7f8, 0xce21, 0xd111, 0x0000, 0xd112, 0x2000, 0xd113,
+    0x000b, 0xe1e1, 0xe42e, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100,
+    0xe004, 0x0133, 0xe67c, 0xe41e, 0x0100, 0xe004, 0x0135, 0xe67c,
+    0x28ee, 0xe008, 0x03ff, 0xcca4, 0xe182, 0x0029, 0xe018, 0x2eee,
+    0xaf15, 0xcca5, 0xe182, 0x0029, 0xe019, 0xae15, 0xe042, 0xae14,
+    0x34f0, 0x3cf1, 0xe42e, 0xe40e, 0x11b1, 0xe40e, 0x0137, 0xe40e,
+    0x013b, 0xe40e, 0x013f, 0xe40e, 0x0143, 0xe40e, 0x0147, 0xe40e,
+    0x014b, 0xe40e, 0x007e, 0xe40e, 0x007e, 0xe40e, 0x014f, 0xe40e,
+    0x007e, 0xe40e, 0x007e, 0xe40e, 0x007e, 0xe40e, 0x007e, 0xe40e,
+    0x007e, 0xe40e, 0x007e, 0xe40e, 0x0510, 0xe40e, 0x0547, 0xe41e,
+    0x0153, 0xe40e, 0x007e, 0xe41e, 0x016d, 0xe40e, 0x007e, 0xe41e,
+    0x0179, 0xe40e, 0x007e, 0xe41e, 0x0216, 0xe40e, 0x007e, 0xe41e,
+    0x0230, 0xe40e, 0x007e, 0xe41e, 0x04a9, 0xe40e, 0x007e, 0xe41e,
+    0x04d6, 0xe40e, 0x007e, 0xd130, 0x000b, 0xe41e, 0x0264, 0xe41e,
+    0x0496, 0xe41e, 0x027d, 0xf0ea, 0xe41e, 0x0c11, 0xe41e, 0x1164,
+    0x283f, 0xe418, 0x0e37, 0xe41e, 0x10dc, 0xa202, 0xe0c2, 0x0070,
+    0xe42e, 0xa200, 0xe0c2, 0x0070, 0xe42e, 0x28b5, 0xe428, 0x28b6,
+    0xf06a, 0xa200, 0x3c13, 0xe41e, 0x129d, 0xe42e, 0xe41e, 0x124f,
+    0xe42e, 0xa202, 0xe0c2, 0x0106, 0xa200, 0xcc4a, 0xcc4c, 0x3cdf,
+    0x3c45, 0xe0c2, 0x003f, 0xe0c2, 0x0074, 0x28b6, 0xf0fa, 0x28b7,
+    0xf09a, 0xe0c0, 0x0066, 0x3410, 0x3c11, 0xe0c0, 0x0067, 0xae04,
+    0x3c12, 0xa200, 0x3c13, 0xe41e, 0x129d, 0xd130, 0x000b, 0xd1b3,
+    0x0001, 0xd03a, 0x0003, 0xd04b, 0x0001, 0xd04c, 0x0000, 0xd008,
+    0x0000, 0xa200, 0xe0c2, 0x030a, 0xe0c2, 0x030b, 0xe41e, 0x03aa,
+    0xe41e, 0x10e1, 0x282c, 0xf05a, 0x28c5, 0xa002, 0xa802, 0x3cc5,
+    0xe41e, 0x0c2c, 0x2830, 0xe41a, 0x0a15, 0x2830, 0xe418, 0x0a7c,
+    0xe41e, 0x05ab, 0x283f, 0xe418, 0x0f66, 0x2e20, 0x2c2b, 0x0821,
+    0xe045, 0xb60e, 0x3c2b, 0x28b6, 0xf06a, 0xe41e, 0x124f, 0xe41e,
+    0x1176, 0xf05e, 0x28b5, 0xf03a, 0xe41e, 0x1270, 0x2c3b, 0xa002,
+    0x3c3b, 0xe0c2, 0x0070, 0xe002, 0x00f3, 0xf028, 0x283b, 0x2824,
+    0xe0c2, 0x0071, 0x282f, 0xe0c2, 0x0073, 0xd039, 0x0000, 0xa200,
+    0x3cd9, 0x3cda, 0xc84a, 0xc84d, 0xae20, 0xe056, 0xe0c2, 0x0053,
+    0xe0c0, 0x0065, 0xaf06, 0xa80e, 0xe418, 0x01f0, 0xa202, 0xe42e,
+    0xe162, 0x0510, 0xc410, 0x280d, 0xae10, 0x3d12, 0x2852, 0x3d12,
+    0x8132, 0x280e, 0xae12, 0x4c2c, 0x3d12, 0x2852, 0xae04, 0x3d12,
+    0x8132, 0x280f, 0xae14, 0x4c2f, 0x3d12, 0x282f, 0xae06, 0x3d12,
+    0xe180, 0xe0c0, 0x0068, 0xce20, 0xd112, 0x000c, 0xd111, 0x0510,
+    0xd113, 0x0002, 0xca28, 0xf7f8, 0xe181, 0xe42e, 0xd130, 0x000b,
+    0xe41e, 0x0c14, 0xe0c0, 0x0060, 0xe42a, 0xe0c0, 0x0042, 0xce20,
+    0xd111, 0x03a0, 0xe0c0, 0x0060, 0x3c3c, 0x843c, 0xc786, 0xe018,
+    0xce24, 0xd113, 0x0003, 0xe1e1, 0xe0c0, 0x0061, 0x3c70, 0xe42e,
+    0xd130, 0x0008, 0x2830, 0xe428, 0x28b6, 0xf0fa, 0x28b7, 0xf09a,
+    0xe0c0, 0x0061, 0x3410, 0x3c11, 0xe0c0, 0x0062, 0xae04, 0x3c12,
+    0xa200, 0x3c13, 0xe41e, 0x129d, 0xe0c0, 0x0060, 0xa806, 0xf06a,
+    0xa102, 0xf09a, 0xa102, 0xf0aa, 0xe42e, 0xe41e, 0x099f, 0xe41e,
+    0x09a4, 0xf07e, 0xe41e, 0x09e6, 0xf04e, 0xe41e, 0x0a07, 0xf01e,
+    0x28b6, 0xf06a, 0xe41e, 0x124f, 0xe41e, 0x1176, 0xe42e, 0x28b5,
+    0xe42a, 0xe41e, 0x1270, 0xe42e, 0x22f0, 0x4ef1, 0xa200, 0xc401,
+    0xe188, 0x07ff, 0x3d11, 0x36f0, 0x3ef1, 0x3cd9, 0x3cda, 0x3c2b,
+    0x3c3b, 0x3c48, 0x3c0d, 0x3cdc, 0x3cdd, 0x3cde, 0x3c33, 0x3c72,
+    0x3c74, 0x3c57, 0x3c93, 0xcc72, 0xe42e, 0xe0c0, 0x0074, 0xa806,
+    0x3c65, 0xe0c0, 0x0074, 0xaf04, 0x3c67, 0xe0c0, 0x0064, 0x347a,
+    0x3c7b, 0x3c71, 0xe0c0, 0x0065, 0x3421, 0x3c20, 0x2821, 0xa002,
+    0x3c21, 0x2c20, 0xc710, 0x7c21, 0xe008, 0xffff, 0xa002, 0xaf02,
+    0x3c3d, 0xe0c0, 0x0062, 0x302d, 0xaf02, 0x302e, 0xaf04, 0xaf04,
+    0x30bb, 0xe0c1, 0x0071, 0x3ebc, 0xaf02, 0x30ca, 0xaf02, 0x30cb,
+    0x287a, 0xa01e, 0xaf08, 0x3c50, 0x287b, 0xa01e, 0xaf08, 0x3c51,
+    0xe0c0, 0x0063, 0xaf06, 0x3030, 0xf1d8, 0xa200, 0x3c34, 0x3c35,
+    0x3c36, 0x3c37, 0x3c6b, 0xe0c0, 0x0066, 0x3022, 0xaf02, 0x3023,
+    0x2a23, 0x4622, 0x3e23, 0xaf02, 0xa80e, 0x3c46, 0xe0c0, 0x0066,
+    0xaf0a, 0x3048, 0xaf02, 0x30c9, 0x2823, 0x4422, 0x3c23, 0xe40e,
+    0x034c, 0xe0c0, 0x0067, 0x3c56, 0x3037, 0xaf02, 0x3036, 0xaf02,
+    0x3035, 0xaf02, 0x3034, 0xaf02, 0x306b, 0x2834, 0xe408, 0x03a6,
+    0x283d, 0xa11e, 0xe404, 0x03a6, 0xe167, 0x0204, 0xc420, 0xa202,
+    0x3c47, 0x2850, 0xae08, 0x1937, 0xe40a, 0x0324, 0x2847, 0xa002,
+    0x3c47, 0xa10a, 0xe408, 0x02e9, 0xa202, 0x3c56, 0xa20c, 0x3c47,
+    0x287b, 0xe002, 0x0190, 0xf086, 0xe002, 0x0190, 0xf0b6, 0xe002,
+    0x0160, 0xf116, 0xf19e, 0x2850, 0x3c32, 0x2851, 0x3c31, 0xe40e,
+    0x033a, 0x2850, 0xae02, 0x3c32, 0x2851, 0xa002, 0xaf02, 0x3c31,
+    0xe40e, 0x033a, 0x2850, 0xae04, 0x3c32, 0x2851, 0xa006, 0xaf04,
+    0x3c31, 0xe40e, 0x033a, 0x2850, 0xae06, 0x3c32, 0x2851, 0xa00e,
+    0xaf06, 0x3c31, 0xe40e, 0x033a, 0x812f, 0x8117, 0x2851, 0xae08,
+    0x1907, 0xe408, 0x02ee, 0x2847, 0xae04, 0xe000, 0x0200, 0xe09e,
+    0x2917, 0xaf08, 0x3c50, 0x2917, 0xaf08, 0x3c51, 0x2917, 0x3c32,
+    0x2907, 0x3c31, 0xa200, 0x2a20, 0xe003, 0x7530, 0xb632, 0x2a21,
+    0xe003, 0x03e9, 0xb632, 0x3c38, 0xf08a, 0x2856, 0xf068, 0x2821,
+    0xa102, 0xe408, 0x03a6, 0x3c38, 0xe0c0, 0x0069, 0x3008, 0xaf02,
+    0x3009, 0xaf02, 0x3c0a, 0xe0c0, 0x006a, 0x3c40, 0xe0c0, 0x006b,
+    0x303f, 0x3481, 0xaf02, 0xe008, 0x7fff, 0x3c80, 0xf028, 0x3c3f,
+    0x2881, 0xaf1e, 0x30ac, 0x2881, 0xe008, 0x7fff, 0x3c81, 0xe0c0,
+    0x006c, 0x3482, 0x3c83, 0xe0c0, 0x006d, 0x3c41, 0x8450, 0x8251,
+    0xe018, 0x3c52, 0xa201, 0xe002, 0x00c8, 0xb425, 0xe002, 0x0190,
+    0xb425, 0x3e44, 0xe0c0, 0x0043, 0xaf06, 0x30b5, 0xaf02, 0x30b6,
+    0xaf02, 0x30b7, 0x2850, 0x2a51, 0xaf06, 0xaf07, 0x3cea, 0x3eeb,
+    0x84ea, 0x82eb, 0xe018, 0x3cc6, 0xa104, 0xf032, 0xa204, 0x3cc6,
+    0x2851, 0xaf02, 0x3cea, 0x84ea, 0x8250, 0xe018, 0x3cc2, 0x3cc7,
+    0xa202, 0x3cc5, 0xe0c0, 0x006e, 0x347c, 0x3c7d, 0xe0c0, 0x006f,
+    0x347e, 0x3c7f, 0xa202, 0xe0c2, 0x0070, 0xe42e, 0xa200, 0xe0c2,
+    0x0070, 0xe42e, 0xa200, 0x3c1f, 0xe0c0, 0x0065, 0xa804, 0xf03a,
+    0xa200, 0x3c3b, 0x2840, 0x4c3b, 0xe016, 0x3c4b, 0x28b9, 0x1840,
+    0xe01a, 0x2ab9, 0xe01b, 0xe052, 0xe016, 0x2a40, 0xe01b, 0xe052,
+    0x4c4b, 0xa203, 0xb611, 0x3e24, 0x3e2c, 0xa202, 0xf02b, 0x08b9,
+    0x3cb9, 0xe0c0, 0x0065, 0xa802, 0xe418, 0x03df, 0xe0c0, 0x0063,
+    0x3c27, 0xa204, 0x1830, 0x3c28, 0x283f, 0xe42a, 0x282c, 0xe41a,
+    0x0f20, 0xe41e, 0x0f21, 0x3c27, 0xe419, 0x03df, 0xe42e, 0xa202,
+    0x3c24, 0x3c2c, 0x3c1f, 0x843a, 0xc786, 0xe018, 0xe000, 0x03a0,
+    0xe09e, 0x2117, 0x4d17, 0xe0c2, 0x0060, 0x2117, 0x4d17, 0xe0c2,
+    0x0061, 0x2117, 0x4d17, 0xe0c2, 0x0062, 0xe42e, 0x2833, 0xae0c,
+    0x4c5d, 0x2ae8, 0xa803, 0xf0f9, 0xae10, 0x3cdc, 0x2a52, 0xa103,
+    0x1ae8, 0xe429, 0xe005, 0x0600, 0x0add, 0xe095, 0x3d02, 0xe41e,
+    0x0421, 0xe42e, 0x4cdc, 0xe005, 0x0600, 0x0add, 0xe095, 0x3d02,
+    0x28dd, 0xa002, 0x3cdd, 0xe002, 0x0080, 0xf068, 0xe41e, 0x0421,
+    0xa200, 0x3cdd, 0xe42e, 0x2852, 0xa102, 0x18e8, 0xe41a, 0x0421,
+    0xe42e, 0x2ae8, 0xaf11, 0xae11, 0xe162, 0x0512, 0x2112, 0x4d12,
+    0xe042, 0xe180, 0xce20, 0xd112, 0x0080, 0xd111, 0x0600, 0xd113,
+    0x0002, 0xca28, 0xf7f8, 0xe181, 0xe42e, 0xe004, 0x0680, 0x08de,
+    0xe094, 0x2858, 0xf07a, 0xae3e, 0x3512, 0x3d0a, 0xe41e, 0x0450,
+    0xe42e, 0xe0c0, 0x03b0, 0x3512, 0x3d0a, 0x2b02, 0xe009, 0x8000,
+    0xf05b, 0x2b02, 0xe009, 0x7fff, 0x3f02, 0xe41e, 0x0450, 0xe42e,
+    0x28de, 0xa004, 0x3cde, 0xe002, 0x0080, 0xf068, 0xe41e, 0x0461,
+    0xa200, 0x3cde, 0xe42e, 0x2852, 0xa102, 0x1853, 0xe41a, 0x0461,
+    0xe42e, 0x2ae8, 0xaf0d, 0xae11, 0xe162, 0x0516, 0x2112, 0x4d12,
+    0xe042, 0xe180, 0xce20, 0xd112, 0x0080, 0xd111, 0x0680, 0xd113,
+    0x0002, 0xca28, 0xf7f8, 0xe181, 0xe42e, 0xe167, 0x0520, 0xa201,
+    0x3f17, 0x2ae8, 0xe045, 0x3f17, 0xc872, 0x22df, 0x4e45, 0xe046,
+    0x3517, 0x3d17, 0xc872, 0x34df, 0x3c45, 0x282f, 0xae06, 0xe167,
+    0x051a, 0x2317, 0x4f17, 0xe042, 0xce20, 0xd111, 0x0520, 0xd112,
+    0x0004, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0040,
+    0xe005, 0x0046, 0xae17, 0xe042, 0xe005, 0x1600, 0xae03, 0xe042,
+    0xce20, 0xd111, 0x0200, 0xd112, 0x016c, 0xd113, 0x0003, 0xe1e1,
+    0xe42e, 0xe0c0, 0x0060, 0xa806, 0xf06a, 0xa102, 0xf09a, 0xa102,
+    0xf0aa, 0xe42e, 0xe41e, 0x099f, 0xe41e, 0x09a4, 0xf06e, 0xe41e,
+    0x09e6, 0xf03e, 0xe41e, 0x0a07, 0xc868, 0xaf06, 0xc867, 0xe003,
+    0x0080, 0xae05, 0xe042, 0x3c4b, 0xe0c2, 0x0070, 0xc86e, 0xd037,
+    0x00c0, 0xbad7, 0xcc6e, 0xe0c0, 0x0042, 0xce20, 0xd111, 0x0100,
+    0xd112, 0x0080, 0xd113, 0x0012, 0xe1e1, 0xe42e, 0xe0c1, 0x0060,
+    0xa803, 0xf05b, 0xe0c0, 0x0061, 0xe41e, 0x0ec9, 0xe0c1, 0x0060,
+    0xa805, 0xf05b, 0xe0c0, 0x0062, 0xe41e, 0x0f15, 0xe0c1, 0x0060,
+    0xa809, 0xf05b, 0xe0c0, 0x0063, 0xe41e, 0x0eef, 0xe0c1, 0x0060,
+    0xa811, 0xf05b, 0xe0c0, 0x0064, 0xe41e, 0x0e90, 0xe0c1, 0x0060,
+    0xa821, 0xf04b, 0xe0c0, 0x0065, 0x3c41, 0xe0c1, 0x0060, 0xa841,
+    0xf08b, 0xe0c0, 0x0066, 0x3008, 0xaf02, 0x3009, 0xaf02, 0x3c0a,
+    0xe0c1, 0x0060, 0xa881, 0xf04b, 0xe0c0, 0x0067, 0x3c48, 0xe42e,
+    0xe0c0, 0x005a, 0x3cee, 0xa206, 0xe41e, 0x057f, 0xe0c0, 0x005a,
+    0x3cee, 0xe41e, 0x0100, 0xe0c0, 0x005b, 0x3cef, 0xa226, 0xe41e,
+    0x0593, 0xe161, 0x07e0, 0x8911, 0x0034, 0x8911, 0x0033, 0x8911,
+    0x0035, 0x8911, 0x0036, 0x8911, 0x0037, 0x8911, 0x0038, 0x2111,
+    0x4d11, 0xcc60, 0x2111, 0x4d11, 0xcc62, 0x2111, 0x4d11, 0xcc64,
+    0x2111, 0x4d11, 0xcc72, 0xe161, 0x00f9, 0x2111, 0x4d11, 0xce88,
+    0x2111, 0x4d11, 0xce84, 0x2111, 0x4d11, 0xce80, 0xe42e, 0xe0c0,
+    0x00ed, 0xa106, 0xf29a, 0xa102, 0xf2fa, 0xe161, 0x07e0, 0x8b11,
+    0x0034, 0x8b11, 0x0033, 0x8b11, 0x0035, 0x8b11, 0x0036, 0x8b11,
+    0x0037, 0x8b11, 0x0038, 0xc860, 0x3511, 0x3d11, 0xc862, 0x3511,
+    0x3d11, 0xc864, 0x3511, 0x3d11, 0xc872, 0x3511, 0x3d11, 0xe161,
+    0x00f9, 0xca88, 0x3511, 0x3d11, 0xca84, 0x3511, 0x3d11, 0xca80,
+    0x3511, 0x3d11, 0xf06e, 0xe161, 0x07e0, 0xa200, 0xc70f, 0x3d11,
+    0xa224, 0xe41e, 0x0593, 0xa204, 0xe41e, 0x057f, 0xe42e, 0x3ced,
+    0xd112, 0x0800, 0xe0c0, 0x0041, 0xe005, 0x0280, 0xae11, 0xe042,
+    0x22f0, 0x4ef1, 0xe042, 0xce20, 0xd111, 0x0000, 0x88ed, 0x0113,
+    0xca28, 0xf7f8, 0xe42e, 0x2aef, 0xa80f, 0xa10b, 0xe42b, 0x3ced,
+    0xd112, 0x0100, 0xe0c0, 0x0041, 0xe005, 0x0298, 0xae11, 0xe042,
+    0x22f0, 0x4ef1, 0xe042, 0xce20, 0xd111, 0x0000, 0x88ed, 0x0113,
+    0xca28, 0xf7f8, 0xe42e, 0x2827, 0x3c62, 0xa200, 0x3cd8, 0x3ce0,
+    0x3ce1, 0x3ce2, 0x3ce3, 0x3ce4, 0x3ce5, 0x3c53, 0x3c54, 0x3c55,
+    0x3cdd, 0x3cde, 0x3c33, 0x3ce8, 0x3ce6, 0x3ce7, 0x3c04, 0x3c05,
+    0x3c06, 0x3c2f, 0xcf64, 0xcf62, 0xe0c2, 0x0113, 0xe0c2, 0x030d,
+    0xa202, 0xe0c2, 0x0130, 0xa2fe, 0x2a22, 0xb616, 0x3c16, 0xe004,
+    0x0055, 0xe0c2, 0x030c, 0x2836, 0xe016, 0x4430, 0xe408, 0x0651,
+    0xa223, 0x2824, 0xe40a, 0x05de, 0x2a28, 0xa021, 0x3e61, 0xa200,
+    0x3c0b, 0xcc70, 0xa202, 0x3c0c, 0x2822, 0xe418, 0x0b6e, 0xa202,
+    0xe0c2, 0x0110, 0x280b, 0xa802, 0xf03a, 0xa202, 0x3c72, 0xe41e,
+    0x08c7, 0xe408, 0x0643, 0x2805, 0xf1fa, 0x280b, 0xa802, 0xe418,
+    0x06e9, 0x2858, 0x2a62, 0x1a26, 0xb606, 0x3c5f, 0xcf26, 0xe41e,
+    0x0716, 0x2824, 0xe418, 0x095e, 0x280d, 0xe418, 0x03f6, 0x2858,
+    0xae04, 0x4c59, 0xcf02, 0x2835, 0xf06a, 0x2859, 0xe016, 0xae0a,
+    0x4c5d, 0xcf6a, 0xe190, 0xe41e, 0x06b1, 0x283f, 0xe016, 0x4c22,
+    0xf038, 0x8a6e, 0x0039, 0x2805, 0xe418, 0x071e, 0x285d, 0x2ad4,
+    0x3c62, 0x3e63, 0x283f, 0x2a22, 0xf18a, 0xc872, 0xf0ab, 0xc870,
+    0xc440, 0xa217, 0xe001, 0x046a, 0xe095, 0x0932, 0x0902, 0x3c4b,
+    0x1c6e, 0xe008, 0xffff, 0x3c6f, 0x2a22, 0x284b, 0xf02b, 0x3c6e,
+    0x285d, 0x2a05, 0xe419, 0x1000, 0xe41e, 0x1127, 0x20e6, 0x4ce7,
+    0xcf62, 0xe40e, 0x05ea, 0x2822, 0xe418, 0x0b81, 0xa202, 0xe41e,
+    0x070e, 0x2836, 0xf048, 0xe41e, 0x0b05, 0xe42e, 0xe41e, 0x0b0f,
+    0xe42e, 0xa202, 0xe0c2, 0x0110, 0xa200, 0x3c4a, 0xf0fe, 0xa202,
+    0x3c72, 0x2808, 0xf0ba, 0xbacf, 0xbae0, 0x284a, 0xba88, 0xbac1,
+    0x285d, 0x3c27, 0xba88, 0xd1b3, 0x0002, 0xa200, 0x3c49, 0xe41e,
+    0x08c7, 0xe408, 0x06ae, 0x8a6e, 0x0039, 0x2805, 0xf1ca, 0x2858,
+    0x2a62, 0x1a26, 0xb606, 0x3c5f, 0xcf26, 0xe41e, 0x0716, 0x2824,
+    0xe418, 0x095e, 0x280d, 0xe418, 0x03f6, 0x2858, 0xae04, 0x4c59,
+    0xcf02, 0x2835, 0xf06a, 0x2859, 0xe016, 0xae0a, 0x4c5d, 0xcf6a,
+    0xe41e, 0x0753, 0x285d, 0x2ad4, 0x3c62, 0x3e63, 0xc872, 0x1c6e,
+    0xe008, 0xffff, 0x3c6f, 0x2a3f, 0x4605, 0x285d, 0xe419, 0x1000,
+    0xe41e, 0x1127, 0x20e6, 0x4ce7, 0xcf62, 0x2805, 0xe40a, 0x0667,
+    0x2849, 0xa002, 0x3c49, 0x1832, 0xe408, 0x0667, 0x284a, 0xa002,
+    0x3c4a, 0x1831, 0xe408, 0x0657, 0xe40e, 0x0667, 0xe41e, 0x0b0f,
+    0xe42e, 0x2808, 0x2a09, 0xe42a, 0x2822, 0xf239, 0x2a05, 0xe42b,
+    0xf0d8, 0x2a0b, 0xaf03, 0x3e0b, 0xe429, 0xc870, 0x1c0a, 0xe424,
+    0xa210, 0x3c0b, 0xa202, 0x3c66, 0xe42e, 0x2a0b, 0xaf03, 0x3e0b,
+    0xe429, 0xc870, 0xc440, 0xa217, 0xe001, 0x046a, 0xe095, 0x0932,
+    0x0902, 0x1c0a, 0xe424, 0xa210, 0x3c0b, 0xa202, 0x3c66, 0xe42e,
+    0x280c, 0x180a, 0x2a0c, 0xa003, 0x3e0c, 0x2a0b, 0xaf03, 0x3e0b,
+    0xe428, 0xa202, 0x3c0c, 0xe004, 0x0020, 0x3c0b, 0xa208, 0x3c66,
+    0xe42e, 0x2833, 0xe016, 0x3c33, 0xa200, 0xe41e, 0x070e, 0x2822,
+    0xf05a, 0xe41e, 0x0b81, 0xe41e, 0x0b6e, 0x2809, 0xf038, 0xd038,
+    0x0000, 0x2862, 0x3c27, 0xe41e, 0x0a49, 0x283f, 0x4422, 0xf0aa,
+    0xc870, 0xc440, 0xa217, 0xe001, 0x046a, 0xe095, 0x0932, 0x0902,
+    0x3c6e, 0xd1b3, 0x0002, 0xa200, 0x3c0b, 0xe42e, 0x2a2e, 0x4e0f,
+    0xe419, 0x0475, 0x282f, 0xa002, 0x3c2f, 0xe42e, 0xd190, 0x0002,
+    0xcb20, 0xa804, 0xf7e8, 0xcb04, 0x3c5e, 0xe42e, 0x28e8, 0xe0c2,
+    0x003f, 0x2a36, 0x2822, 0xe409, 0x0753, 0x2a24, 0xe40a, 0x072c,
+    0xe40b, 0x080c, 0xe40e, 0x0837, 0x2859, 0x7024, 0xe428, 0x285b,
+    0xae02, 0x4c5a, 0xae02, 0x4c58, 0x3c4f, 0xa200, 0x0824, 0x3c00,
+    0x285e, 0xa806, 0xae06, 0x4c4f, 0x6c00, 0x285c, 0x7058, 0xa20a,
+    0x1858, 0x3c00, 0x285e, 0xaf04, 0x6c00, 0x285a, 0xe418, 0x0869,
+    0x2858, 0xe41a, 0x0888, 0x8877, 0x0194, 0xd190, 0x0001, 0xcb20,
+    0xa802, 0xf7e8, 0xe42e, 0x2859, 0x7024, 0xe428, 0x285b, 0xae02,
+    0x4c5a, 0xae02, 0x4c58, 0x3c4f, 0xa200, 0x0824, 0x0824, 0x0824,
+    0x3c00, 0x285e, 0xa806, 0xae06, 0x4c4f, 0x6c00, 0xa20a, 0x1858,
+    0x3c00, 0x285e, 0xaf04, 0x6c00, 0x285a, 0xe418, 0x086e, 0x2858,
+    0xe41a, 0x087a, 0xcb3e, 0xe016, 0xa802, 0x4437, 0xe418, 0x08b2,
+    0xa201, 0xe0c3, 0x0134, 0xf098, 0x8877, 0x0194, 0xd190, 0x0001,
+    0xcb20, 0xa802, 0xf7e8, 0xe42e, 0xa20c, 0x3c4d, 0x2a4d, 0xe427,
+    0xa103, 0x3e4d, 0x285f, 0xe418, 0x0793, 0x285e, 0x5c4d, 0xa802,
+    0xe418, 0x07a2, 0xf74e, 0xa20a, 0xe046, 0xae0c, 0xcf3a, 0xcf3c,
+    0xcb38, 0xe005, 0x00fe, 0xe066, 0xe049, 0xe003, 0x0080, 0xb7f6,
+    0xba8e, 0xe42e, 0xe41e, 0x07a7, 0xe41e, 0x07d7, 0xe42e, 0x2877,
+    0x5c4d, 0x5c4d, 0xa806, 0xe005, 0x02ac, 0xf07a, 0xe005, 0x02fc,
+    0xa106, 0xf03a, 0xe005, 0x033c, 0xe09f, 0x8117, 0xe165, 0x0482,
+    0xe166, 0x04c2, 0xa27c, 0xcc44, 0xa20a, 0x2a4d, 0xe046, 0xae0c,
+    0x3c4b, 0xa200, 0xa201, 0x3cdb, 0xe184, 0x07d5, 0x284b, 0x4d17,
+    0xcf3a, 0xcf3c, 0xcb38, 0xe008, 0x0fff, 0xb435, 0xf07a, 0x3f15,
+    0x3d16, 0xa201, 0x28db, 0xa002, 0x3cdb, 0xe190, 0xe42e, 0xe165,
+    0x0482, 0xe166, 0x04c2, 0x28db, 0xa104, 0xcc44, 0xe184, 0x07e5,
+    0x2915, 0xae18, 0x4d16, 0xb914, 0xe41d, 0x07ef, 0xa202, 0xae0c,
+    0x4d15, 0xae18, 0x4d16, 0xb914, 0xe41d, 0x07ef, 0xe42e, 0xe16a,
+    0x810e, 0xa207, 0xba8d, 0xaf18, 0xba8c, 0x2906, 0xae30, 0xaf30,
+    0xe049, 0xe002, 0x007f, 0xe001, 0x007f, 0xf050, 0xf045, 0x2916,
+    0xba8e, 0xe42e, 0xe004, 0x0080, 0xba8e, 0x2906, 0xa83e, 0xba88,
+    0x2916, 0xaf0a, 0xba8a, 0xe42e, 0x285b, 0xae02, 0x4c5a, 0xae02,
+    0x4c58, 0x3c4f, 0x285e, 0xa806, 0xae06, 0x4c4f, 0xb900, 0x285a,
+    0xe418, 0x0869, 0x285f, 0xf06a, 0xd190, 0x0001, 0xcb20, 0xa802,
+    0xf7e8, 0xa203, 0xe41e, 0x0b3c, 0x285c, 0xba80, 0x285e, 0xaf04,
+    0xb908, 0xa205, 0xe41e, 0x0b3c, 0x8877, 0x0194, 0xd190, 0x0004,
+    0xcb20, 0xa808, 0xf7e8, 0xa201, 0xe41e, 0x0b3c, 0xe42e, 0x2859,
+    0xba80, 0xe428, 0x285b, 0xae02, 0x4c5a, 0xae02, 0x4c58, 0x3c4f,
+    0x285e, 0xa806, 0xae06, 0x4c4f, 0xb902, 0x2858, 0xe41a, 0x0888,
+    0xa203, 0xe41e, 0x0b3c, 0x285c, 0x7058, 0xa20a, 0x1858, 0x3c00,
+    0x285e, 0xaf04, 0x6c00, 0x285a, 0xe418, 0x0869, 0xd190, 0x0001,
+    0xcb20, 0xa802, 0xf7e8, 0xa205, 0xe41e, 0x0b3c, 0x8877, 0x0194,
+    0xd190, 0x0004, 0xcb20, 0xa808, 0xf7e8, 0xa201, 0xe41e, 0x0b3c,
+    0xe42e, 0x286c, 0xa002, 0xb628, 0xba82, 0xe42e, 0x2837, 0xe40a,
+    0x0869, 0x286c, 0xa140, 0xe404, 0x0877, 0xba82, 0xe42e, 0x286c,
+    0xba8a, 0xe42e, 0x285b, 0xb670, 0xcc44, 0xe161, 0x0100, 0xe184,
+    0x0886, 0x2911, 0xa040, 0xb90c, 0x2911, 0xa040, 0xb90c, 0xe42e,
+    0xe162, 0x0100, 0x285b, 0xb670, 0xcc44, 0xe184, 0x0895, 0x2912,
+    0xe41e, 0x0897, 0x2912, 0xe41e, 0x0897, 0xe190, 0xe42e, 0xe40a,
+    0x08af, 0xe404, 0x08a4, 0xa102, 0xe049, 0x5c29, 0xa002, 0xa040,
+    0xb90c, 0x462a, 0x7229, 0xe42e, 0xa002, 0xe012, 0xe049, 0x5c29,
+    0xa002, 0xe012, 0xa040, 0xb90c, 0x462a, 0x7229, 0xe42e, 0xa040,
+    0xb90c, 0xe42e, 0xe004, 0x017f, 0xcc44, 0xa202, 0xe0c2, 0x0134,
+    0xa200, 0xe184, 0x08c2, 0xe0c2, 0x0135, 0xa002, 0xe0c1, 0x0136,
+    0xe003, 0xff80, 0xf03b, 0xa200, 0xe42e, 0xa202, 0xe42e, 0xe41e,
+    0x0e25, 0x2824, 0x4406, 0xe418, 0x0e30, 0x2804, 0xe428, 0xa202,
+    0xe0c2, 0x0110, 0x2824, 0x4406, 0xe0c2, 0x018b, 0xa200, 0x3c5b,
+    0x3c5c, 0x3c77, 0x3c59, 0xe41e, 0x08f2, 0xe41e, 0x0de5, 0xe41e,
+    0x1147, 0x2a05, 0x2858, 0xe017, 0xe016, 0x4e30, 0xe055, 0xf099,
+    0xe0c0, 0x0130, 0xaf06, 0x305c, 0xe0c1, 0x0132, 0xb615, 0x3e77,
+    0xa200, 0xe42e, 0x2806, 0xf23a, 0x2824, 0xf08a, 0xe0c0, 0x0195,
+    0xe01a, 0x3c5b, 0xe0c0, 0x0197, 0x3c6a, 0x2824, 0xe016, 0xf0b8,
+    0xe0c1, 0x015c, 0xe001, 0x0200, 0x1e6a, 0xb62a, 0x2a41, 0xf038,
+    0xe419, 0x10e4, 0x3c58, 0x2a1f, 0xf03b, 0xa201, 0x3e58, 0x2a5b,
+    0xb611, 0x3e5b, 0xf04b, 0x28d8, 0xa940, 0x3cd8, 0x2a3f, 0x462c,
+    0x4605, 0x2827, 0xf0eb, 0xe41e, 0x0f9a, 0x2a65, 0xf02b, 0x28e9,
+    0x2ad8, 0xa803, 0xf02b, 0x2862, 0x1862, 0xa504, 0xa4fc, 0x0862,
+    0x3c5d, 0x2a3f, 0x462c, 0x4605, 0x2827, 0xf0db, 0x2893, 0x2a65,
+    0xf02b, 0x28c8, 0x2ad8, 0xa811, 0xf02b, 0x2863, 0x1863, 0xa504,
+    0xa4fc, 0x0863, 0x3cd4, 0x285d, 0x1862, 0x3c6c, 0x2a37, 0xf18a,
+    0xf17b, 0x2862, 0xe000, 0x022c, 0xe09e, 0xe160, 0x0020, 0x286c,
+    0x1937, 0xe40a, 0x0952, 0x286c, 0x1907, 0xe40a, 0x0955, 0x285d,
+    0xe40e, 0x0956, 0xa244, 0xe40e, 0x0956, 0xa246, 0x3c6c, 0x286c,
+    0xe01a, 0x3c5a, 0x28d8, 0xaf02, 0x3cd8, 0xe42e, 0xe162, 0x0100,
+    0x2869, 0xe09a, 0x2b15, 0x3e5b, 0x2915, 0x4d0d, 0x4c5a, 0x4c58,
+    0x4c5b, 0x4c5e, 0xe01a, 0xe016, 0x3c59, 0x2858, 0xae04, 0x4c59,
+    0xcf02, 0x2858, 0xf258, 0x2a5b, 0xcf4b, 0x2115, 0x4d15, 0xcf4c,
+    0xf0ab, 0x2115, 0x4d15, 0xcf4e, 0x2115, 0x4d15, 0xcf50, 0x2115,
+    0x4d15, 0xcf52, 0xd1a0, 0x0001, 0xcb40, 0xa802, 0xf7e8, 0xcb4c,
+    0x3512, 0x3d12, 0xf0ab, 0xcb4e, 0x3512, 0x3d12, 0xcb50, 0x3512,
+    0x3d12, 0xcb52, 0x3512, 0x3d12, 0xe08a, 0x3c69, 0xe42e, 0xd1a0,
+    0x0001, 0xcb40, 0xa802, 0xf7e8, 0xa200, 0x3c5b, 0xe42e, 0xbacf,
+    0xe004, 0x0100, 0xba9e, 0xe42e, 0xa204, 0x2ac9, 0xb632, 0x3c00,
+    0xbacf, 0xe004, 0x0120, 0xba9e, 0xbac0, 0xbae7, 0xbae0, 0x2800,
+    0xba86, 0xbae2, 0xbae3, 0xbac0, 0xbac1, 0xbae0, 0x2c20, 0xba9e,
+    0xbae0, 0x2821, 0xa102, 0xe01a, 0xba80, 0xf07a, 0x2c20, 0xe41e,
+    0x0b18, 0x3c4e, 0x2821, 0x704e, 0xbae0, 0x287a, 0x2a7b, 0xba98,
+    0xbae0, 0xba99, 0xbae0, 0xbac0, 0xbae0, 0xa200, 0x7000, 0xbac0,
+    0xbac0, 0x2800, 0xa102, 0xf02a, 0xbac0, 0xbae0, 0xbac0, 0x2822,
+    0xba80, 0xf03a, 0x2823, 0xba80, 0x2800, 0xa102, 0xe40a, 0x09e2,
+    0xbac0, 0xbac0, 0xbac0, 0xe41e, 0x0b05, 0xe42e, 0xbacf, 0xe004,
+    0x01b0, 0xba9e, 0x2850, 0xa116, 0xf090, 0x2851, 0xa112, 0xf060,
+    0x283d, 0xa11e, 0xf030, 0xa202, 0xf11e, 0x2850, 0xa12c, 0xf0d0,
+    0x2851, 0xa124, 0xf0a0, 0x283d, 0xa13c, 0xf070, 0xa01e, 0xf030,
+    0xa204, 0xf04e, 0xa206, 0xf02e, 0xa208, 0xba8e, 0xe42e, 0xbacf,
+    0xe004, 0x01b5, 0xba9e, 0xbae0, 0xa202, 0xba86, 0xa202, 0xba84,
+    0xbae3, 0xbac0, 0xe41e, 0x0b05, 0xe42e, 0xbacf, 0xe004, 0x01b6,
+    0xba9e, 0x2824, 0xba82, 0x2c3b, 0xf0aa, 0x2c2b, 0xf038, 0xbae0,
+    0xf06e, 0x1c20, 0xf046, 0x1821, 0xf022, 0xbae0, 0xbac0, 0xbae0,
+    0x2c20, 0xe41e, 0x0b18, 0x3c4e, 0x2c2b, 0x704e, 0xbae0, 0xbae0,
+    0x2824, 0xa102, 0xf038, 0x2825, 0xba80, 0x2846, 0xba84, 0xe000,
+    0x0220, 0xe09e, 0x2907, 0x3c26, 0x2827, 0xba88, 0x2824, 0xe42a,
+    0x2828, 0xba84, 0xa102, 0x3c29, 0xa202, 0x5829, 0xa102, 0x3c2a,
+    0xe42e, 0x2836, 0xe408, 0x0ae4, 0xe41e, 0x0b05, 0xbacf, 0x2861,
+    0xa120, 0x3c4e, 0xa202, 0x704e, 0x2852, 0xe41e, 0x0b18, 0x3c4e,
+    0x28e8, 0x704e, 0x2827, 0xba88, 0x2848, 0xba80, 0xe42a, 0x2c3b,
+    0xf0aa, 0x2c2b, 0xf038, 0xbae0, 0xf06e, 0x1c20, 0xf046, 0x1821,
+    0xf022, 0xbae0, 0xbac0, 0xbae0, 0x2c20, 0xe41e, 0x0b18, 0x3c4e,
+    0x2c2b, 0x704e, 0xbae0, 0x2824, 0xba82, 0x2846, 0xba84, 0x2824,
+    0xe42a, 0x2828, 0xba84, 0xe42e, 0xe41e, 0x0b0f, 0xbacf, 0xa240,
+    0xba8a, 0x2c3b, 0xe008, 0x00ff, 0xba8e, 0xbae0, 0xbac0, 0xbac0,
+    0xbac0, 0xbac0, 0x2856, 0xf0a8, 0x2847, 0xba84, 0x2824, 0xba80,
+    0xbac3, 0x2827, 0xba88, 0xbac0, 0xf3ee, 0xa20e, 0xba84, 0xbae2,
+    0x2847, 0xba84, 0x2838, 0xba80, 0xbac2, 0x2834, 0xba80, 0x2835,
+    0xba80, 0x2836, 0xba80, 0xbac2, 0x2837, 0xba80, 0xbae0, 0xbac2,
+    0x2824, 0xba84, 0xbac1, 0x2825, 0xba80, 0xbae2, 0xbac0, 0x2847,
+    0xa10c, 0xf0b8, 0xa204, 0xba86, 0x287a, 0xaf04, 0xa102, 0xba90,
+    0xbae0, 0x287b, 0xaf04, 0xba90, 0x2838, 0xf10a, 0x2821, 0xe002,
+    0x03e9, 0xe016, 0xba80, 0x8421, 0xe182, 0x0708, 0xe018, 0xc70f,
+    0x7c20, 0xba8c, 0x2c3b, 0xaf10, 0xba82, 0xa200, 0x7036, 0x7036,
+    0x2827, 0xba88, 0xbac0, 0xa200, 0x3ce8, 0x2836, 0xe418, 0x0ae4,
+    0x2846, 0xe000, 0x0220, 0xe09e, 0x2907, 0x3c26, 0xa202, 0x3c28,
+    0xa200, 0x3c29, 0x3c2a, 0xe42e, 0x28e8, 0xf0ba, 0xc868, 0xa80e,
+    0xf06a, 0xa110, 0xe012, 0x3c4e, 0xa200, 0x704e, 0xba9e, 0xbae0,
+    0xbae0, 0x2852, 0xe41e, 0x0b21, 0x3c4e, 0x2ae8, 0x724e, 0xa116,
+    0xf046, 0x2ae8, 0xf02b, 0xbae0, 0x28e8, 0xf03a, 0x2827, 0xba88,
+    0xbae0, 0x28e8, 0xf02a, 0xbac1, 0xe42e, 0xbac0, 0xc868, 0xa80e,
+    0xe42a, 0xa110, 0xe012, 0x3c4e, 0xa2fe, 0x704e, 0xe42e, 0xc868,
+    0xa80e, 0xe42a, 0xa110, 0xe012, 0x3c4e, 0xa200, 0x704e, 0xe42e,
+    0xa102, 0xa201, 0xf05a, 0xaf02, 0xa003, 0xe408, 0x0b1b, 0xe04a,
+    0xe42e, 0xa102, 0xa15e, 0xf0d6, 0xa166, 0xf0d6, 0xe002, 0x0129,
+    0xf0c6, 0xe002, 0x04a4, 0xf0b6, 0xe002, 0x1290, 0xf0a6, 0xf0be,
+    0xa20c, 0xe42e, 0xa20e, 0xe42e, 0xa212, 0xe42e, 0xa216, 0xe42e,
+    0xa21a, 0xe42e, 0xa21c, 0xe42e, 0xf049, 0x20d9, 0x4cda, 0xcc72,
+    0x2816, 0xf048, 0xc872, 0x34d9, 0x3cda, 0x2816, 0xae06, 0xe000,
+    0x046a, 0xe092, 0xc860, 0x3511, 0x3d11, 0x8b11, 0x0034, 0x8b11,
+    0x0038, 0x8b11, 0x0033, 0x8b11, 0x0035, 0x8b11, 0x0037, 0x8b11,
+    0x0036, 0x3e16, 0xae07, 0xe001, 0x046a, 0xe093, 0x2111, 0x4d11,
+    0xcc60, 0x8911, 0x0034, 0x8911, 0x0038, 0x8911, 0x0033, 0x8911,
+    0x0035, 0x8911, 0x0037, 0x8911, 0x0036, 0xe42e, 0xe41e, 0x1198,
+    0xe004, 0x00a4, 0x3c18, 0xe004, 0x0164, 0x3c19, 0xa200, 0x3c1a,
+    0x3c1b, 0x2816, 0xa201, 0x3e16, 0xe424, 0xa201, 0xe41e, 0x0b3c,
+    0xe42e, 0x2824, 0xe408, 0x0b8a, 0xe004, 0x006b, 0xba8c, 0xbaeb,
+    0xe40e, 0x0b8d, 0xa23e, 0xba88, 0xbaeb, 0xe41e, 0x0b92, 0xe41e,
+    0x0bc5, 0xe42e, 0xc872, 0x34d9, 0x3cda, 0x281a, 0xe40a, 0x0bb5,
+    0x2818, 0xe002, 0x00a4, 0x3c1c, 0xe41e, 0x1225, 0xd04c, 0x0000,
+    0xe004, 0x00a4, 0x3c18, 0xe41e, 0x11ff, 0xe004, 0x0800, 0x3c1e,
+    0xe161, 0x0080, 0xe41e, 0x0bf6, 0xc872, 0x34d9, 0x3cda, 0x281c,
+    0xa102, 0x3c1c, 0xf718, 0xe41e, 0x11ff, 0xa203, 0xe41e, 0x0b3c,
+    0xc870, 0xe008, 0x07ff, 0x3c1e, 0xe161, 0x0080, 0xbadf, 0xe41e,
+    0x0bf6, 0xc872, 0x34d9, 0x3cda, 0xe42e, 0x281b, 0xe40a, 0x0be6,
+    0x2819, 0xe002, 0x0164, 0x3c1c, 0xe41e, 0x123a, 0xd04c, 0x0000,
+    0xe004, 0x0164, 0x3c19, 0xe41e, 0x1212, 0xe004, 0x0800, 0x3c1e,
+    0xe161, 0x00c0, 0xe41e, 0x0bf6, 0xc872, 0x34d9, 0x3cda, 0x281c,
+    0xa102, 0x3c1c, 0xe408, 0x0bd3, 0xe41e, 0x1212, 0xa205, 0xe41e,
+    0x0b3c, 0xc870, 0xe008, 0x07ff, 0x3c1e, 0xe161, 0x00c0, 0xbadf,
+    0xe41e, 0x0bf6, 0xc872, 0x34d9, 0x3cda, 0xe42e, 0xe082, 0xcc76,
+    0xa201, 0xe41e, 0x0b3c, 0xa201, 0x281e, 0xaf0a, 0xe40a, 0x0c06,
+    0xa102, 0xcc44, 0xe184, 0x0c05, 0xc87a, 0xbabe, 0x281e, 0xa83e,
+    0xe42a, 0x3c1e, 0xa140, 0xe012, 0x3c1d, 0xc87a, 0x5c1d, 0x701e,
+    0xe42e, 0xa200, 0x3c39, 0xe42e, 0xe004, 0x0502, 0xe09e, 0xe0c0,
+    0x0064, 0x3517, 0x3d17, 0xe0c0, 0x0065, 0x3517, 0x3d17, 0xe0c0,
+    0x0066, 0x3517, 0x3d17, 0xe0c0, 0x0067, 0x3517, 0x3d17, 0xe0c0,
+    0x0069, 0x3517, 0x3d17, 0xe42e, 0x2837, 0xae02, 0x4c36, 0xae02,
+    0x4c35, 0xae06, 0x4c30, 0xae08, 0xa916, 0xe0c2, 0x0100, 0xe004,
+    0x003f, 0xe0c2, 0x012a, 0xe0c0, 0x0050, 0xe049, 0xe008, 0x003f,
+    0x3ccc, 0xaf11, 0xe009, 0x003f, 0x3ecd, 0x46cc, 0x3ecc, 0xa200,
+    0xe0c2, 0x0168, 0x2acc, 0xa803, 0xf03b, 0xe00a, 0x0002, 0x2acc,
+    0xa805, 0xf03b, 0xe00a, 0x0009, 0x2acc, 0xa809, 0xf03b, 0xe00a,
+    0x0020, 0x2acc, 0xa811, 0xf03b, 0xe00a, 0x0040, 0x2acc, 0xa841,
+    0xf03b, 0xe00a, 0x0004, 0xe0c2, 0x0169, 0xe004, 0x0037, 0xe0c2,
+    0x017c, 0xe004, 0x0014, 0xe0c2, 0x017d, 0xe0c0, 0x0041, 0xe005,
+    0x0000, 0xae11, 0xe042, 0x2acd, 0xa805, 0xf09b, 0xe004, 0x0502,
+    0xe09e, 0xe160, 0x0002, 0x0937, 0x2117, 0x4d17, 0xe0c2, 0x0103,
+    0xa202, 0xae02, 0xa902, 0xe0c2, 0x0312, 0xe0c0, 0x0064, 0x2a1f,
+    0xf02b, 0xa200, 0xe0c2, 0x0138, 0xe008, 0x000f, 0x3c75, 0x287a,
+    0xae20, 0x4c7b, 0xe0c2, 0x0142, 0x2870, 0xe0c2, 0x0141, 0x2850,
+    0xae20, 0x4c51, 0xae08, 0xe0c2, 0x0101, 0xcf60, 0x2a1f, 0xaa03,
+    0x4675, 0xa803, 0xf05b, 0x2851, 0xae20, 0x4c50, 0xae08, 0xe0c2,
+    0x0142, 0xe0c0, 0x0044, 0xa81e, 0xae1a, 0x4c70, 0xe0c2, 0x0102,
+    0x282c, 0xae06, 0xe0c2, 0x0104, 0xe0c0, 0x0060, 0xe0c2, 0x0143,
+    0xe0c0, 0x0061, 0xe0c2, 0x0144, 0xe0c0, 0x0062, 0xe0c2, 0x0145,
+    0x2870, 0x2a1f, 0xaa03, 0x4675, 0xa803, 0xf02b, 0x2871, 0xe0c2,
+    0x0141, 0x2835, 0xf27a, 0xe0c1, 0x0041, 0xe004, 0x0040, 0xae10,
+    0xe042, 0x2acd, 0xa809, 0xf09b, 0xe004, 0x0502, 0xe09e, 0xe160,
+    0x0004, 0x0937, 0x2117, 0x4d17, 0xe0c2, 0x0211, 0xe0c1, 0x0041,
+    0xe004, 0x0080, 0xae10, 0xe042, 0x2acd, 0xa811, 0xf09b, 0xe004,
+    0x0502, 0xe09e, 0xe160, 0x0006, 0x0937, 0x2117, 0x4d17, 0xe0c2,
+    0x0212, 0x2837, 0xcf68, 0xa204, 0x2a35, 0xb632, 0xe0c2, 0x0210,
+    0xb612, 0xe0c2, 0x0208, 0xa216, 0xae08, 0x4c24, 0xae06, 0xe0c2,
+    0x0204, 0x8439, 0xc786, 0xe018, 0xe000, 0x03a0, 0xe09e, 0x2117,
+    0x4d17, 0xe0c2, 0x020d, 0xe0c2, 0x0214, 0x2117, 0x4d17, 0xe0c2,
+    0x020e, 0xe0c2, 0x0215, 0x2117, 0x4d17, 0xe0c2, 0x020f, 0xe0c2,
+    0x0216, 0x2824, 0xf3aa, 0xa202, 0xe0c2, 0x0302, 0x843a, 0xc786,
+    0xe018, 0xe000, 0x03a0, 0xe09e, 0x2117, 0x4d17, 0xe0c2, 0x0380,
+    0x2117, 0x4d17, 0xe0c2, 0x0381, 0x2117, 0x4d17, 0xe0c2, 0x0382,
+    0xa200, 0xe0c2, 0x0302, 0xe0c0, 0x0380, 0xe0c2, 0x0183, 0xa204,
+    0xae02, 0x4c25, 0xe0c2, 0x0303, 0xa200, 0xe0c2, 0x0308, 0xe41e,
+    0x0d85, 0x2830, 0xae12, 0x4c28, 0xcf46, 0xe0c1, 0x0041, 0xe004,
+    0x00a0, 0xae10, 0xe042, 0x2acd, 0xa803, 0xf06b, 0xe004, 0x0502,
+    0xe09e, 0x2117, 0x4d17, 0xcf44, 0x2822, 0xae02, 0x4c23, 0xae02,
+    0x4c37, 0xcf24, 0x2830, 0xae06, 0x4c24, 0xae02, 0xcf00, 0x2839,
+    0xe0c2, 0x0072, 0x3c3a, 0xa002, 0x3c39, 0x183c, 0xf028, 0x3c39,
+    0xa202, 0x3c66, 0xe0c2, 0x0139, 0xe0c0, 0x0065, 0xaf06, 0xe049,
+    0x300d, 0xaf02, 0x300e, 0xaf02, 0x300f, 0xa80f, 0xe42b, 0xe180,
+    0xe0c1, 0x0068, 0xce21, 0xd112, 0x000c, 0xd111, 0x0510, 0xd113,
+    0x0003, 0xca29, 0xf7f9, 0xe181, 0xe42e, 0x207c, 0x4c7d, 0x2acd,
+    0xa841, 0xf07b, 0xe004, 0x0502, 0xa010, 0xe09e, 0x2117, 0x4d17,
+    0xe0c2, 0x0187, 0x207e, 0x4c7f, 0xe0c2, 0x0188, 0xa200, 0xe0c2,
+    0x019e, 0xe0c2, 0x019f, 0xe0c0, 0x0044, 0xe0c2, 0x0199, 0x2870,
+    0xe0c2, 0x018a, 0xe0c2, 0x0189, 0x2851, 0xae08, 0xa102, 0xae20,
+    0x2a50, 0xae09, 0xa103, 0xe056, 0xe0c2, 0x0181, 0xe0c0, 0x0060,
+    0xe0c2, 0x0182, 0x282c, 0xe0c2, 0x0186, 0x2827, 0xaf02, 0x0844,
+    0xa51e, 0xe049, 0xae02, 0xe042, 0xe000, 0x026c, 0xe09e, 0x8117,
+    0x8117, 0x210f, 0x4d07, 0xe0c2, 0x0184, 0xa200, 0xe0c2, 0x0185,
+    0x2917, 0xe0c2, 0x019a, 0x2830, 0xf09a, 0x2835, 0xf048, 0xe004,
+    0x0140, 0xf06e, 0xe004, 0x0152, 0xf03e, 0xe004, 0x0192, 0x4c2c,
+    0xe0c2, 0x0180, 0xe004, 0x0400, 0x3c68, 0x3c69, 0xd008, 0x000d,
+    0xd009, 0x0400, 0xd00a, 0x0436, 0xe42e, 0x28d4, 0xae0c, 0x4cd4,
+    0xae0c, 0x4cd4, 0xe0c2, 0x0115, 0x2866, 0xa802, 0xe0c2, 0x0131,
+    0x2866, 0xaf02, 0x3c66, 0x2858, 0xe0c2, 0x0114, 0xf038, 0xe41e,
+    0x0dfe, 0x280e, 0x442c, 0xe418, 0x0435, 0xe42e, 0x2868, 0xe09a,
+    0x2a5b, 0x3f15, 0xe162, 0x0191, 0x9e12, 0x3515, 0x3d15, 0xcf4c,
+    0xf0db, 0x9e12, 0x3515, 0x3d15, 0xcf4e, 0x9e12, 0x3515, 0x3d15,
+    0xcf50, 0x9e12, 0x3515, 0x3d15, 0xcf52, 0x285b, 0xcf4a, 0xd1a0,
+    0x0002, 0xcb41, 0xa805, 0xf7e9, 0xe08a, 0x3c68, 0xe004, 0x06db,
+    0x2a5b, 0xb616, 0xe0c2, 0x0309, 0xe42e, 0xe0c0, 0x0111, 0xf7e8,
+    0xe0c0, 0x0118, 0x3004, 0xaf02, 0x3005, 0xaf02, 0x3006, 0xe42e,
+    0xe0c0, 0x0198, 0xf7ea, 0xa200, 0xe0c2, 0x0198, 0xe42e, 0xa232,
+    0x3c07, 0xa240, 0x3c84, 0xa204, 0x3c86, 0xa23e, 0x2aca, 0xf03b,
+    0xe0c0, 0x0072, 0x3c85, 0xa20c, 0x3c87, 0xe004, 0x029c, 0x3c88,
+    0x2840, 0x2a52, 0x3c89, 0x3e8f, 0x283d, 0x3c8b, 0x3cbe, 0xe004,
+    0x6000, 0x2acb, 0xf03b, 0xe0c0, 0x0073, 0x3c8c, 0x2889, 0xe016,
+    0x3c8a, 0xf06a, 0x288b, 0x3c89, 0xe004, 0x1000, 0x3c8c, 0x8421,
+    0xe182, 0x7530, 0xe018, 0xae02, 0x2e20, 0xe41e, 0x1099, 0x3c98,
+    0x8498, 0x8280, 0xe018, 0xa279, 0xe41e, 0x1082, 0x3498, 0x3c99,
+    0xae06, 0x2a84, 0xe41e, 0x1082, 0x349e, 0x3c9f, 0xa202, 0x3c8d,
+    0xa205, 0x1a44, 0xae03, 0xa011, 0x3e94, 0x2a8f, 0x5a94, 0xe013,
+    0x36ae, 0x3eaf, 0x28bc, 0x2abb, 0xf049, 0xe41e, 0x1029, 0x6407,
+    0x3c90, 0xa004, 0x6086, 0x6485, 0x3c91, 0xe41e, 0x104d, 0xe42e,
+    0x34c0, 0x3cbf, 0x28c0, 0xa002, 0x3cc0, 0x2cbf, 0xc710, 0x7cc0,
+    0xe008, 0xffff, 0xa002, 0xaf02, 0x3c8b, 0x18be, 0xe42a, 0x288b,
+    0x3cbe, 0x28bf, 0x2ac0, 0x3c20, 0x3e21, 0xa200, 0x3c2b, 0x8421,
+    0xe182, 0x7530, 0xe018, 0xae02, 0x2e20, 0xe41e, 0x1099, 0x3c98,
+    0x8498, 0x8280, 0xe018, 0xa279, 0xe41e, 0x1082, 0x3498, 0x3c99,
+    0xae06, 0x2a84, 0xe41e, 0x1082, 0x349e, 0x3c9f, 0xa200, 0x3cb8,
+    0x34a2, 0x3ca3, 0x2889, 0xe428, 0xe016, 0x3c8a, 0x288b, 0x3c89,
+    0xe42e, 0x3cba, 0x2a89, 0xe046, 0xf028, 0xe42e, 0x28b9, 0x2aba,
+    0xe046, 0xf034, 0xa200, 0x3cb9, 0x28ba, 0x3c89, 0x3c40, 0x283f,
+    0xe42a, 0x2889, 0xe016, 0x3c8a, 0xf03a, 0x2a8b, 0x3e89, 0x2a89,
+    0x28b9, 0xe045, 0xf0c6, 0x20a6, 0x4ca7, 0xe41e, 0x1082, 0x34aa,
+    0x3cab, 0x10a6, 0x1ca7, 0xe012, 0x34a8, 0x3ca9, 0xe42e, 0x3cbd,
+    0xf028, 0x3c3f, 0x283f, 0xe42a, 0x2880, 0x2abd, 0xe046, 0xe42a,
+    0x3e80, 0x8421, 0xe182, 0x7530, 0xe018, 0xae02, 0x2e20, 0xe41e,
+    0x1099, 0x3c98, 0x8498, 0x8280, 0xe018, 0xa279, 0xe41e, 0x1082,
+    0x3498, 0x3c99, 0xae06, 0x2a84, 0xe41e, 0x1082, 0x349e, 0x3c9f,
+    0xa200, 0x3cb8, 0x34a2, 0x3ca3, 0xe42e, 0x2a3f, 0xe42b, 0xf042,
+    0xa201, 0x3ebb, 0xe42e, 0x3cbc, 0x3c90, 0xa203, 0x3ebb, 0xe42e,
+    0xe42e, 0x282c, 0x3c8e, 0xa201, 0x3ead, 0xe418, 0x100b, 0xa200,
+    0x3ca0, 0x3ca1, 0x3c74, 0x288e, 0xf238, 0x288d, 0xf05a, 0xa200,
+    0x3c8d, 0x2890, 0xf31e, 0x2889, 0xa102, 0xf7ca, 0x2abb, 0xf03b,
+    0x2890, 0xf2ae, 0x848f, 0x82b8, 0xe019, 0xe04a, 0xaf02, 0x00a2,
+    0x0ca3, 0xe41e, 0x1099, 0xa21f, 0x3e94, 0x2a89, 0xc70f, 0x7e94,
+    0xe009, 0xffff, 0xa405, 0xe046, 0x6086, 0x6407, 0xf15e, 0xa200,
+    0x3c9c, 0x3c9d, 0x2865, 0x30eb, 0xaf02, 0x54eb, 0xf08a, 0x2891,
+    0xa104, 0x6093, 0x2a91, 0xa005, 0xe066, 0xf02e, 0x2891, 0x2aad,
+    0xf02b, 0x2885, 0x3c93, 0x3c27, 0x2aad, 0xe42e, 0xc872, 0xe41e,
+    0x1056, 0x288e, 0xf0ea, 0x20a0, 0x4ca1, 0xc710, 0x7c8f, 0xe008,
+    0xffff, 0xa002, 0xaf02, 0x3c91, 0x20a0, 0x4ca1, 0x00a2, 0x0ca3,
+    0x34a2, 0x3ca3, 0x28b8, 0xa002, 0x3cb8, 0x288e, 0xf028, 0x3cb8,
+    0x288e, 0xf0f8, 0x2a89, 0xa103, 0x20a6, 0x4ca7, 0xe41e, 0x1082,
+    0x34aa, 0x3cab, 0x10a6, 0x1ca7, 0xe012, 0x34a8, 0x3ca9, 0xf0ae,
+    0x22a8, 0x4ea9, 0x12aa, 0x1eab, 0x288a, 0xb606, 0xb611, 0x36a8,
+    0x3ea9, 0xe42e, 0x28e8, 0xf038, 0x2893, 0x3c57, 0x2ae8, 0x1a52,
+    0xa007, 0xf0b5, 0x28d7, 0x3ce9, 0xe42b, 0xa103, 0x28d6, 0x3ce9,
+    0xe42b, 0x28d5, 0x3ce9, 0xe42e, 0x229c, 0x4e9d, 0x209e, 0x4c9f,
+    0xe041, 0xf0c7, 0xe045, 0xe045, 0x2893, 0xf0f5, 0x369c, 0x3e9d,
+    0xa002, 0x6086, 0x6485, 0x3c93, 0xf08e, 0x369c, 0x3e9d, 0x2893,
+    0xa102, 0x6086, 0x6485, 0x3c93, 0x2874, 0xa002, 0x3c74, 0x2a65,
+    0xf08b, 0xa103, 0xf1cb, 0xa103, 0xf07b, 0xa103, 0xf0ab, 0xf19e,
+    0x2893, 0x3cc8, 0xf16e, 0x2872, 0xf12a, 0xa200, 0x3c72, 0xf06e,
+    0x2874, 0x1867, 0xf0c4, 0xa200, 0x3c74, 0x2a57, 0xa105, 0x6293,
+    0x2857, 0xa004, 0xe066, 0x3c93, 0x3cc8, 0xf03e, 0x2857, 0x3cc8,
+    0x28c8, 0x3c57, 0x28e8, 0xf078, 0x28c8, 0x3cd5, 0x3cd6, 0x3cd7,
+    0x3ce9, 0xe42e, 0x28d7, 0x2a65, 0xa805, 0xf029, 0x3cc8, 0x3ce9,
+    0x28d6, 0x3cd7, 0x28d5, 0x3cd6, 0x2857, 0x3cd5, 0x28c8, 0xe42e,
+    0x00a0, 0x0ca1, 0x34a0, 0x3ca1, 0x286f, 0x1892, 0x009c, 0x0c9d,
+    0x349c, 0x3c9d, 0xe42e, 0x20a8, 0x4ca9, 0x10a6, 0x1ca7, 0x848c,
+    0xe41e, 0x10d0, 0x0098, 0x0c99, 0xf052, 0x2aac, 0xf039, 0xa203,
+    0x3ead, 0xe41e, 0x1068, 0x2298, 0x4e99, 0xaf07, 0xe062, 0x349a,
+    0x3c9b, 0xc710, 0x7c8f, 0xe008, 0xffff, 0xa002, 0xaf02, 0x3c92,
+    0xe42e, 0x8489, 0x2098, 0x4c99, 0xe41e, 0x10c4, 0x8487, 0xe41e,
+    0x10c4, 0x2a89, 0xa103, 0x0a87, 0xe41e, 0x1082, 0x349a, 0x3c9b,
+    0x288f, 0x3cb0, 0x209a, 0x4c9b, 0xae04, 0x009a, 0x0c9b, 0xae02,
+    0xc70f, 0x7cb0, 0xe008, 0xffff, 0xaf08, 0xa010, 0xaf08, 0x0844,
+    0xa51e, 0x0888, 0xe09e, 0x2907, 0xe42e, 0x8480, 0x8281, 0xe018,
+    0x34a4, 0x3ca5, 0xa200, 0x34a6, 0x3ca7, 0xe42e, 0x1098, 0x1c99,
+    0x00a6, 0x0ca7, 0xa27f, 0xae31, 0xe066, 0x34a6, 0x3ca7, 0x22ae,
+    0x4eaf, 0xe046, 0xf032, 0x36a6, 0x3ea7, 0x20a6, 0x28a7, 0xe42e,
+    0x2a81, 0xe42b, 0x22a4, 0x4ea5, 0x12a6, 0x1ea7, 0xe066, 0xf051,
+    0x2aac, 0xf039, 0xa203, 0x3ead, 0x2282, 0x4e83, 0xe42b, 0x22a4,
+    0x4ea5, 0x12a6, 0x1ea7, 0x0298, 0x0e99, 0x1282, 0x1e83, 0xa401,
+    0xe062, 0xe42e, 0x3eb0, 0xa201, 0xf032, 0xe012, 0xa203, 0x3eb4,
+    0x3cb1, 0xaf20, 0xc70f, 0x7cb0, 0x3cb2, 0xaf20, 0xae20, 0x4cb1,
+    0xc70f, 0x7cb0, 0x3cb3, 0x20b2, 0x4cb3, 0x2ab4, 0xe42b, 0xe012,
+    0xe42e, 0x36b0, 0x3eb1, 0xa201, 0x3eb2, 0x22b0, 0x4eb1, 0x5ab2,
+    0xe045, 0xf061, 0x2ab2, 0xa003, 0x3eb2, 0xa121, 0xf775, 0x2ab2,
+    0xf039, 0xa200, 0xe42e, 0xa103, 0x3eb2, 0xcc45, 0xa201, 0x3eb3,
+    0xe184, 0x10c1, 0x2ab3, 0xae03, 0x3eb3, 0x22b0, 0x4eb1, 0x5ab2,
+    0xe045, 0xf061, 0xe013, 0xe04a, 0x2ab3, 0xa003, 0x3eb3, 0x2ab2,
+    0xa103, 0x3eb2, 0x28b3, 0xe42e, 0xae02, 0x34b1, 0xe008, 0xffff,
+    0xaf02, 0x3cb0, 0x82b1, 0xe018, 0xae1e, 0x82b0, 0xe01c, 0xe42e,
+    0xae02, 0x34b1, 0xe008, 0xffff, 0xaf02, 0x3cb0, 0x82b0, 0xe018,
+    0xaf1e, 0x82b1, 0xe01c, 0xe42e, 0xa200, 0x3cc1, 0x3cc3, 0x3cc4,
+    0xe42e, 0xa200, 0x3c42, 0xe42e, 0x28c5, 0xf1f8, 0x2842, 0x1841,
+    0xf3d2, 0x2853, 0x18c1, 0xf3a4, 0x28c1, 0x08c6, 0x18c7, 0xf0b4,
+    0x28c3, 0xa002, 0xc70f, 0x7cc6, 0xaf20, 0x3cc3, 0x3cc1, 0x2841,
+    0x3c42, 0xf2ae, 0x2842, 0xa002, 0x3c42, 0x28c1, 0x08c6, 0xc70f,
+    0x7cc7, 0xaf20, 0x3cc1, 0xf20e, 0x2842, 0x1841, 0xf1f2, 0x2853,
+    0x18c2, 0xf1c4, 0x28c2, 0x08c6, 0x1852, 0xf0c4, 0x28c4, 0xa002,
+    0xc70f, 0x7cc6, 0xaf20, 0x3cc4, 0x08c7, 0x3cc2, 0x2841, 0x3c42,
+    0xf0be, 0x2842, 0xa002, 0x3c42, 0x28c2, 0x08c6, 0xc70f, 0x7c52,
+    0xaf20, 0x3cc2, 0xf01e, 0xa202, 0xe42e, 0xa200, 0xe42e, 0x2805,
+    0xf12a, 0xd188, 0x0001, 0x28e8, 0xa002, 0x3ce8, 0xcf64, 0x28e6,
+    0xa002, 0x3ce6, 0x1850, 0xf078, 0xd1b3, 0x0004, 0x3ce6, 0x28e7,
+    0xa002, 0x3ce7, 0x2853, 0xa002, 0x3c53, 0x2854, 0xa002, 0x3c54,
+    0x1850, 0xe428, 0x3c54, 0x2855, 0xa002, 0x3c55, 0xe42e, 0x28e4,
+    0x3ce5, 0x28e3, 0x3ce4, 0x28e2, 0x3ce3, 0x28e1, 0x3ce2, 0x28e0,
+    0x3ce1, 0x286c, 0xa83e, 0xae02, 0x4c5a, 0xae02, 0x4c58, 0x3ce0,
+    0x2a3f, 0x462c, 0x28e5, 0x3058, 0xe429, 0xaf02, 0x305a, 0xaf02,
+    0xae3e, 0xaf3e, 0x3c6c, 0xe42e, 0xa200, 0x3c13, 0xe0c0, 0x0060,
+    0x3410, 0x3c11, 0xe0c0, 0x0061, 0xae04, 0x3c12, 0xe41e, 0x1189,
+    0xe41e, 0x129d, 0xd071, 0x802a, 0xe181, 0xe42e, 0xd030, 0x0000,
+    0xd034, 0x0000, 0xd033, 0x0000, 0xd035, 0x0000, 0xd036, 0x007f,
+    0xd037, 0x0000, 0xc872, 0xa130, 0xcc72, 0xc870, 0xa130, 0xcc70,
+    0xe42e, 0xd030, 0x0000, 0xd034, 0x0000, 0xd033, 0x0000, 0xd035,
+    0x0000, 0xd036, 0x007f, 0xd037, 0x0000, 0xd038, 0x0000, 0xe42e,
+    0xa210, 0xe000, 0x046a, 0xe094, 0xa200, 0xc703, 0x3d12, 0xe004,
+    0x0080, 0xc702, 0x3d12, 0xe000, 0x003f, 0x3d12, 0xa200, 0xc703,
+    0x3d12, 0xe004, 0x00c0, 0xc702, 0x3d12, 0xe000, 0x003f, 0x3d12,
+    0xe42e, 0x2816, 0xf06a, 0xa102, 0xf0ba, 0xa102, 0xf0ea, 0xe470,
+    0xe004, 0x0080, 0xe41e, 0x11c9, 0xd04c, 0x0000, 0xe470, 0xe41e,
+    0x1225, 0xd04c, 0x0000, 0xe470, 0xe41e, 0x123a, 0xd04c, 0x0000,
+    0xe470, 0xce24, 0xd111, 0x0000, 0xe082, 0x3c14, 0xe004, 0x0048,
+    0xe092, 0x2010, 0x4c11, 0x2e13, 0xae11, 0xe042, 0x34e9, 0x3c4b,
+    0xe41e, 0x12a7, 0x2010, 0x4c11, 0x2e13, 0xae11, 0xe042, 0xce20,
+    0x8111, 0x9f01, 0xe0c0, 0x0043, 0xa806, 0xae02, 0xa020, 0xce26,
+    0xca28, 0xf7f8, 0x2c13, 0xe000, 0x0002, 0x3c13, 0x1c12, 0xf074,
+    0x2ab6, 0xf04b, 0xa203, 0xe0c3, 0x0074, 0x3c13, 0x2010, 0x4c11,
+    0x2e13, 0xae11, 0xe042, 0x9f01, 0x2814, 0xe092, 0xe42e, 0xe0c0,
+    0x0041, 0x2a18, 0xae11, 0xe042, 0xce20, 0xd111, 0x0080, 0xd112,
+    0x0040, 0xd113, 0x0013, 0xca28, 0xf7f8, 0x2818, 0xe000, 0x0001,
+    0x3c18, 0xe42e, 0xe0c0, 0x0041, 0x2a19, 0xae11, 0xe042, 0xce20,
+    0xd111, 0x00c0, 0xd112, 0x0040, 0xd113, 0x0013, 0xca28, 0xf7f8,
+    0x2819, 0xe000, 0x0001, 0x3c19, 0xe42e, 0xe0c0, 0x0041, 0x2a18,
+    0xae11, 0xe042, 0xce20, 0xd111, 0x0080, 0xd112, 0x0040, 0xd113,
+    0x0012, 0xca28, 0xf7f8, 0x2818, 0xe000, 0x0001, 0x3c18, 0xa202,
+    0x3c1a, 0xe42e, 0xe0c0, 0x0041, 0x2a19, 0xae11, 0xe042, 0xce20,
+    0xd111, 0x00c0, 0xd112, 0x0040, 0xd113, 0x0012, 0xca28, 0xf7f8,
+    0x2819, 0xe000, 0x0001, 0x3c19, 0xa202, 0x3c1b, 0xe42e, 0xc868,
+    0xaf06, 0xc867, 0xe003, 0x0000, 0xae05, 0xe042, 0x3c4c, 0xc86e,
+    0xd037, 0x0080, 0xbad7, 0xcc6e, 0xe004, 0x0080, 0xe41e, 0x11c9,
+    0xe004, 0x0049, 0xe092, 0x9e01, 0x2210, 0x4e11, 0xe045, 0xf049,
+    0x2210, 0x4e11, 0xe042, 0x084c, 0xe002, 0x0200, 0x9f01, 0xe42e,
+    0xc866, 0xcc78, 0xc860, 0xcc7a, 0xd111, 0x0000, 0xe004, 0x0048,
+    0xe092, 0x2010, 0x4c11, 0x2e13, 0xae11, 0xe042, 0x34e9, 0x3c4b,
+    0x2ab6, 0xe41b, 0x12a7, 0x20e9, 0x4c4b, 0xce20, 0x8111, 0x9f01,
+    0xd112, 0x0100, 0xe0c0, 0x0043, 0xa806, 0xae02, 0xa020, 0xce26,
+    0xca28, 0xf7f8, 0xc868, 0xaf06, 0xc867, 0xe003, 0x0000, 0xae05,
+    0xe042, 0x9e81, 0xe042, 0x9f01, 0xe42e, 0x2010, 0x4c11, 0x2e13,
+    0xae11, 0xe042, 0xe005, 0x0049, 0xe093, 0x9f01, 0xe42e, 0xe0c1,
+    0x0043, 0xa809, 0xe429, 0xe0c1, 0x0043, 0xa821, 0xe429, 0xa200,
+    0x3c15, 0x20e9, 0x4c4b, 0x9e81, 0xe045, 0xf041, 0x2c12, 0xae10,
+    0xe041, 0xe003, 0x0200, 0xe421, 0x2815, 0xf748, 0xe0c0, 0x005c,
+    0xe008, 0x8000, 0xf6fa, 0xe0c0, 0x005d, 0xe00a, 0x8000, 0xe0c2,
+    0x005d, 0xa202, 0xce00, 0x3c15, 0xf65e, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0080, 0x0060, 0x0008, 0x0006,
+    0x00b0, 0x0090, 0x000b, 0x0009, 0x0160, 0x0120, 0x0016, 0x0012,
+    0x02c0, 0x0240, 0x0058, 0x0012, 0x0580, 0x0480, 0x0160, 0x0012,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0063, 0x000d, 0x000f, 0x0011, 0x0013, 0x0015, 0x0017, 0x0000,
+    0xffff, 0xfffe, 0x0001, 0x0002, 0x0000, 0x0002, 0xffff, 0xffff,
+    0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xfffe,
+    0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe,
+    0xfffe, 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0xfffd,
+    0xfffd, 0xfffd, 0xfffd, 0xfffd, 0x0000, 0x0001, 0x0001, 0x0001,
+    0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0002,
+    0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002,
+    0x0002, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+    0x0003, 0x0002, 0x0001, 0xfffb, 0x0200, 0x0000, 0x0008, 0x0200,
+    0x0000, 0x0010, 0x0200, 0x0008, 0x0020, 0x0200, 0x0010, 0x0040,
+    0x0200, 0x0020, 0x0080, 0x0200, 0x0040, 0x00c0, 0x0200, 0x0060,
+    0x0100, 0x0200, 0x0080, 0x0140, 0x0200, 0x00c0, 0x0180, 0x0200,
+    0x0100, 0x01c0, 0x0200, 0x0140, 0x0200, 0x0200, 0x0180, 0x0280,
+    0x0200, 0x0200, 0x0300, 0x0200, 0x0200, 0x0300, 0x0200, 0x0200,
+    0x0300, 0x0200, 0x0200, 0x0300, 0x001a, 0x0019, 0x0018, 0x0017,
+    0x0016, 0x0015, 0x0014, 0x0013, 0x0012, 0x0011, 0x0010, 0x000f,
+    0x000e, 0x000d, 0x000c, 0x000a, 0x0000, 0x0001, 0x0008, 0x0010,
+    0x0009, 0x0002, 0x0003, 0x000a, 0x0011, 0x0018, 0x0020, 0x0019,
+    0x0012, 0x000b, 0x0004, 0x0005, 0x000c, 0x0013, 0x001a, 0x0021,
+    0x0028, 0x0030, 0x0029, 0x0022, 0x001b, 0x0014, 0x000d, 0x0006,
+    0x0007, 0x000e, 0x0015, 0x001c, 0x0023, 0x002a, 0x0031, 0x0038,
+    0x0039, 0x0032, 0x002b, 0x0024, 0x001d, 0x0016, 0x000f, 0x0017,
+    0x001e, 0x0025, 0x002c, 0x0033, 0x003a, 0x003b, 0x0034, 0x002d,
+    0x0026, 0x001f, 0x0027, 0x002e, 0x0035, 0x003c, 0x003d, 0x0036,
+    0x002f, 0x0037, 0x003e, 0x003f, 0x0000, 0x0008, 0x0010, 0x0018,
+    0x0001, 0x0009, 0x0002, 0x000a, 0x0011, 0x0019, 0x0020, 0x0028,
+    0x0030, 0x0038, 0x0039, 0x0031, 0x0029, 0x0021, 0x001a, 0x0012,
+    0x0003, 0x000b, 0x0004, 0x000c, 0x0013, 0x001b, 0x0022, 0x002a,
+    0x0032, 0x003a, 0x0023, 0x002b, 0x0033, 0x003b, 0x0014, 0x001c,
+    0x0005, 0x000d, 0x0006, 0x000e, 0x0015, 0x001d, 0x0024, 0x002c,
+    0x0034, 0x003c, 0x0025, 0x002d, 0x0035, 0x003d, 0x0016, 0x001e,
+    0x0007, 0x000f, 0x0017, 0x001f, 0x0026, 0x002e, 0x0036, 0x003e,
+    0x0027, 0x002f, 0x0037, 0x003f, 0x0000, 0x0001, 0x0002, 0x0003,
+    0x0008, 0x0009, 0x0010, 0x0011, 0x000a, 0x000b, 0x0004, 0x0005,
+    0x0006, 0x0007, 0x000f, 0x000e, 0x000d, 0x000c, 0x0013, 0x0012,
+    0x0018, 0x0019, 0x0020, 0x0021, 0x001a, 0x001b, 0x0014, 0x0015,
+    0x0016, 0x0017, 0x001c, 0x001d, 0x001e, 0x001f, 0x0022, 0x0023,
+    0x0028, 0x0029, 0x0030, 0x0031, 0x002a, 0x002b, 0x0024, 0x0025,
+    0x0026, 0x0027, 0x002c, 0x002d, 0x002e, 0x002f, 0x0032, 0x0033,
+    0x0038, 0x0039, 0x003a, 0x003b, 0x0034, 0x0035, 0x0036, 0x0037,
+    0x003c, 0x003d, 0x003e, 0x003f, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe40e, 0x0020, 0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x0131,
+    0xe470, 0xe190, 0xe40e, 0x0113, 0xe470, 0xe190, 0xe470, 0xe190,
+    0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+    0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x012f, 0xe40e, 0x0131,
+    0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058,
+    0xa200, 0xe0c2, 0x005a, 0x3cf0, 0x3cf1, 0xa2fe, 0x3cee, 0x3cef,
+    0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d, 0xce00, 0xf11e, 0xe0c0,
+    0x005c, 0xe0c1, 0x0059, 0x3eed, 0xa203, 0x5aed, 0xe052, 0xf08a,
+    0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00, 0xe41e,
+    0x008c, 0xe41e, 0x00ab, 0xe0c0, 0x005a, 0x18ee, 0xe0c1, 0x0059,
+    0xa115, 0xb636, 0x2aee, 0xb60a, 0xe418, 0x00fb, 0xe0c0, 0x005b,
+    0xe0c1, 0x005e, 0xae11, 0xe056, 0x18ef, 0xe0c1, 0x0059, 0xa117,
+    0xb636, 0xe418, 0x00b0, 0xe0c0, 0x005a, 0x18ee, 0x2aee, 0xb60a,
+    0xe0c1, 0x0059, 0xa117, 0xb636, 0xe418, 0x00f3, 0xd071, 0x802a,
+    0xe181, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100, 0xe0c0, 0x0059,
+    0xae02, 0xe000, 0x0113, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a,
+    0x3cee, 0xe41e, 0x0100, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11,
+    0xe056, 0x3cef, 0xe40e, 0x0037, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+    0x0058, 0xe0c2, 0x0008, 0xe0c0, 0x0059, 0xf7ea, 0xa11e, 0xf0e8,
+    0xa202, 0xe0c2, 0x0058, 0xe004, 0x093d, 0xe0c2, 0x0070, 0xa200,
+    0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xf6fe, 0xa202, 0xe0c2, 0x0008,
+    0xe0c2, 0x0058, 0xe42e, 0xd101, 0x0001, 0xc70f, 0xa000, 0xe42e,
+    0xa200, 0xe0c1, 0x005b, 0xf27b, 0xa220, 0xa103, 0xf2eb, 0xa230,
+    0xa103, 0xf2bb, 0xa23c, 0xa103, 0xf24b, 0xa258, 0xa103, 0xf25b,
+    0xa260, 0xa103, 0xf22b, 0xa200, 0xa103, 0xf1fb, 0xa26c, 0xa103,
+    0xf1cb, 0xe004, 0x003e, 0xa103, 0xf18b, 0xe004, 0x0044, 0xa105,
+    0xf14b, 0xe004, 0x0046, 0xa103, 0xf10b, 0xe004, 0x0000, 0xa107,
+    0xf0cb, 0xa200, 0xe0c1, 0x005e, 0xf08b, 0xe004, 0x004c, 0xf05e,
+    0xe0c1, 0x005e, 0xf02b, 0xa010, 0xae16, 0xe0c1, 0x0040, 0xe041,
+    0xca28, 0xf7f8, 0xce21, 0xd111, 0x0000, 0xd112, 0x2000, 0xd113,
+    0x000b, 0xe1e1, 0xe42e, 0xe0c0, 0x005a, 0x3cee, 0xe41e, 0x0100,
+    0xe004, 0x0133, 0xe67c, 0xe41e, 0x0100, 0xe004, 0x0135, 0xe67c,
+    0x28ee, 0xe008, 0x03ff, 0xcca4, 0xe182, 0x0029, 0xe018, 0x2eee,
+    0xaf15, 0xcca5, 0xe182, 0x0029, 0xe019, 0xae15, 0xe042, 0xae14,
+    0x34f0, 0x3cf1, 0xe42e, 0xe40e, 0x0764, 0xe40e, 0x0137, 0xe40e,
+    0x013b, 0xe40e, 0x013f, 0xe40e, 0x0147, 0xe40e, 0x007e, 0xe40e,
+    0x0153, 0xe40e, 0x014f, 0xe40e, 0x015b, 0xe40e, 0x007e, 0xe40e,
+    0x007e, 0xe40e, 0x007e, 0xe40e, 0x007e, 0xe40e, 0x007e, 0xe40e,
+    0x007e, 0xe40e, 0x007e, 0xe40e, 0x0464, 0xe40e, 0x0477, 0xe41e,
+    0x018a, 0xe40e, 0x007e, 0xe41e, 0x020d, 0xe40e, 0x007e, 0x284d,
+    0xa184, 0xe41e, 0x015f, 0xe41e, 0x020e, 0xe40e, 0x007e, 0x284d,
+    0xa184, 0xe41e, 0x015f, 0xe41e, 0x03bc, 0xe40e, 0x007e, 0xe41e,
+    0x03ed, 0xe40e, 0x007e, 0x284d, 0xa184, 0xe41e, 0x015f, 0xe41e,
+    0x059e, 0xe40e, 0x007e, 0xe41e, 0x0420, 0xe40e, 0x007e, 0xe428,
+    0xe0c0, 0x0040, 0xa211, 0xae17, 0xe042, 0xca29, 0xf7f9, 0xce20,
+    0xd111, 0x0000, 0xd112, 0x2000, 0xd113, 0x000b, 0xe1e1, 0xe42e,
+    0xe167, 0x05d3, 0xe166, 0x0064, 0xd022, 0x0003, 0xe184, 0x017a,
+    0x9e16, 0x3517, 0x3d17, 0xe0c0, 0x0069, 0xe167, 0x0ba0, 0x3d17,
+    0x3517, 0xe0c0, 0x006a, 0x3d17, 0x3517, 0xe0c0, 0x006b, 0x3d17,
+    0x3517, 0xe42e, 0xd152, 0x0000, 0xd130, 0x0000, 0x22f0, 0x4ef1,
+    0xa200, 0xc401, 0xe188, 0x07ff, 0x3d11, 0x36f0, 0x3ef1, 0xe41e,
+    0x040b, 0xa2fe, 0x3c10, 0x3c20, 0x3c48, 0x3cbf, 0x3c5f, 0xa206,
+    0x3cbe, 0xa200, 0xcc44, 0x3cd6, 0x3c4e, 0x3c4b, 0xe0c2, 0x0072,
+    0xe0c2, 0x006c, 0xa202, 0xe0c2, 0x0078, 0xe0c0, 0x0062, 0xaf02,
+    0x301e, 0xaf02, 0xa806, 0x3c75, 0xe41e, 0x06df, 0xe41e, 0x137d,
+    0xe41e, 0x1865, 0xe41e, 0x1f2e, 0xa200, 0x3c60, 0xe41e, 0x05bb,
+    0x286d, 0xe408, 0x0208, 0x28a4, 0xa10e, 0xf798, 0xe41e, 0x1390,
+    0xe41e, 0x0711, 0xe128, 0xe41e, 0x0ca0, 0xf71a, 0xa2fe, 0x3c10,
+    0x2050, 0x4c51, 0xae08, 0xe0c2, 0x0071, 0xe0c2, 0x004f, 0x2850,
+    0xe002, 0x0080, 0xf2e0, 0x2851, 0xe002, 0x0080, 0xf2a0, 0x281e,
+    0xf0da, 0x2813, 0xa104, 0xf0aa, 0x28df, 0xe0c2, 0x0074, 0xa006,
+    0xe0c2, 0x0073, 0x28de, 0x3cdc, 0xf09e, 0x28df, 0xa006, 0xe0c2,
+    0x0073, 0xa200, 0xe0c2, 0x0074, 0x3cdc, 0xa200, 0x3c6d, 0x285d,
+    0xae04, 0x4c1a, 0xae02, 0x4c18, 0xae10, 0x4c1c, 0xae10, 0x4c4d,
+    0xe0c2, 0x007b, 0xe41e, 0x0696, 0xa202, 0xe0c2, 0x0070, 0xe42e,
+    0xa200, 0x3c6d, 0xe0c2, 0x0070, 0xe42e, 0xe42e, 0xa2fe, 0xe0c2,
+    0x004c, 0xe0c2, 0x004d, 0xe0c2, 0x004e, 0xe0c2, 0x007b, 0xa200,
+    0xcc44, 0xcc4a, 0xcc4c, 0x3c4c, 0x3c55, 0x3ced, 0xe0c2, 0x006d,
+    0xe0c2, 0x007a, 0x3c5c, 0xd14b, 0x0200, 0xa2fc, 0xe0c2, 0x0077,
+    0xa202, 0xe0c2, 0x0076, 0x286e, 0xf07a, 0xe41e, 0x078e, 0xe41e,
+    0x05a4, 0xa200, 0x3c6e, 0xe41e, 0x0f5b, 0xf05a, 0xa202, 0x3c6c,
+    0xe40e, 0x034a, 0x2875, 0xa802, 0xf06a, 0xa200, 0x3c69, 0x3c6b,
+    0xe41e, 0x06b7, 0xe41e, 0x1348, 0xd152, 0x0000, 0xd130, 0x0000,
+    0xd1e0, 0x0003, 0xd1ff, 0x03b0, 0xd1fd, 0x03d0, 0xd199, 0x0224,
+    0xd1fc, 0x0700, 0xd03a, 0x0000, 0xd04c, 0x0000, 0xd008, 0x0000,
+    0xe41e, 0x1df4, 0x288e, 0xf0da, 0x288f, 0xf162, 0x28db, 0xe41a,
+    0x1300, 0xe41e, 0x18ae, 0x28c1, 0x3c8f, 0x3c39, 0xe40e, 0x034a,
+    0xe41e, 0x18a1, 0xf048, 0xa2ff, 0xe0c3, 0x0077, 0xf03a, 0x286c,
+    0xf03a, 0xe40e, 0x034a, 0xa2fc, 0xe0c2, 0x0077, 0xa200, 0x3caa,
+    0x3cab, 0x288e, 0xf038, 0x28c1, 0x3cbf, 0xa202, 0x3c49, 0x288e,
+    0xf0da, 0x288a, 0x3ca3, 0x288b, 0x3ca5, 0x288f, 0x3cc1, 0xe41e,
+    0x04ef, 0xe41e, 0x0bff, 0xe40e, 0x02e9, 0xe41e, 0x05bb, 0x28a4,
+    0xf7da, 0xa102, 0xe40a, 0x02e9, 0xa108, 0xf784, 0xe40a, 0x02e9,
+    0xa102, 0xf23a, 0xa102, 0xf1ba, 0xa102, 0xf1ca, 0xa102, 0xf20a,
+    0xa102, 0xf22a, 0xa102, 0xf20a, 0xa102, 0xf33a, 0xa106, 0xf08a,
+    0xa10a, 0xe40a, 0x02e6, 0xa002, 0xf612, 0xe40e, 0x02e4, 0xa203,
+    0x3e5e, 0xe41e, 0x1390, 0xa201, 0x3e5e, 0xf2fe, 0xe41e, 0x1390,
+    0xf2ce, 0xe41e, 0x13c1, 0xf29e, 0xe41e, 0x0f63, 0xf26e, 0xba44,
+    0xe41e, 0x089c, 0xf22e, 0x2875, 0xa802, 0xe408, 0x03b3, 0x286b,
+    0xf09a, 0x2875, 0xa802, 0xe016, 0x3c6c, 0xe41e, 0x053b, 0xe40e,
+    0x034a, 0x287f, 0xf038, 0x287d, 0xf03a, 0xa202, 0x3ca9, 0xf0de,
+    0xba0e, 0xe002, 0x00ff, 0xf058, 0xba4e, 0xe41e, 0x0623, 0xf798,
+    0xe41e, 0x089c, 0xe40e, 0x028d, 0xe40e, 0x028d, 0xa202, 0xe41e,
+    0x1f36, 0xe165, 0x07c8, 0x28a5, 0x3d15, 0x28a3, 0x3d15, 0x2830,
+    0x3d15, 0x28d3, 0x3d15, 0x288e, 0xf0d8, 0xa2fe, 0x3cc1, 0xe41e,
+    0x092f, 0xf0e8, 0xe41e, 0x1f36, 0xa200, 0x2a57, 0xa003, 0xe40b,
+    0x03b3, 0x2a7e, 0xa103, 0xe40b, 0x034a, 0xe40a, 0x028d, 0x28a3,
+    0x3c84, 0x28a5, 0x3c85, 0x2a3b, 0x28bf, 0x18c1, 0xf09a, 0x28be,
+    0xa106, 0xf07a, 0xe41e, 0x0504, 0xe41e, 0x0519, 0xf34e, 0x4ebe,
+    0x3ebe, 0xa200, 0x3c49, 0x3c8e, 0xe41e, 0x191a, 0x282f, 0xa002,
+    0x3c2f, 0x28a3, 0x4c34, 0xf048, 0x28c1, 0xe41e, 0x186b, 0x28a3,
+    0xe418, 0x1508, 0x2ac1, 0x285e, 0xb7f1, 0x3e5f, 0x2834, 0xf058,
+    0xe41e, 0x1f20, 0xe418, 0x1194, 0x2834, 0xaa02, 0x4432, 0xe41a,
+    0x11d0, 0x28d3, 0x3cd7, 0xa200, 0xe41e, 0x1f36, 0xe41e, 0x0696,
+    0x2832, 0xf09a, 0x2a75, 0xf04b, 0x2834, 0xe41a, 0x0567, 0x2834,
+    0xe40a, 0x0279, 0x2848, 0xe412, 0x18d5, 0x286c, 0xf04a, 0xe41e,
+    0x12fb, 0x3cdc, 0xe41e, 0x11f9, 0xf032, 0x2a6c, 0xb7b6, 0xe049,
+    0x1ad4, 0xf045, 0xa2fa, 0x2a6b, 0xb7f2, 0xe0c2, 0x0071, 0xe0c0,
+    0x0071, 0x3c48, 0xa200, 0x2a48, 0xf0f4, 0x3e0a, 0xaf09, 0x2072,
+    0x4c73, 0xf06b, 0x2070, 0x4c71, 0x2a0a, 0xa81f, 0x3e0a, 0x5c0a,
+    0x5c0a, 0xa806, 0xae20, 0x2a5c, 0xae13, 0x4e33, 0xae05, 0x4e19,
+    0xae03, 0x4e32, 0xae21, 0x4e55, 0xae05, 0xe056, 0x4c30, 0xe0c2,
+    0x0073, 0x2a48, 0xf1b5, 0xaf09, 0xf0fb, 0x2070, 0x4c71, 0x2a48,
+    0xa81f, 0x3e0a, 0xa207, 0x5a0a, 0x5a0a, 0xe013, 0xa103, 0xe052,
+    0x3470, 0x3c71, 0xf0be, 0x2072, 0x4c73, 0xa207, 0x5a48, 0x5a48,
+    0xe013, 0xa103, 0xe052, 0x3472, 0x3c73, 0x284c, 0xe0c2, 0x0072,
+    0x2c4b, 0xa002, 0x3c4b, 0xe0c2, 0x0070, 0xa200, 0x3c7e, 0xc84a,
+    0xc84d, 0xae20, 0xe056, 0xe0c2, 0x0053, 0xe41e, 0x1366, 0xe41e,
+    0x0581, 0xa202, 0xe42e, 0xe41e, 0x1366, 0xa2fe, 0xe0c2, 0x0072,
+    0xa200, 0xe0c2, 0x0076, 0xe42e, 0xd152, 0x0000, 0xd130, 0x0000,
+    0xe41e, 0x0170, 0xca28, 0xf7f8, 0xe0c0, 0x0060, 0xe42a, 0xe0c0,
+    0x0042, 0xce20, 0xd111, 0x0620, 0xd112, 0x0100, 0xd113, 0x0003,
+    0xca28, 0xf7f8, 0xe0c0, 0x0042, 0xe000, 0x1000, 0xce20, 0xd111,
+    0x0ba8, 0xd112, 0x004c, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xa200,
+    0xe41e, 0x0c58, 0xe004, 0x0040, 0xe41e, 0x0c58, 0xe0c0, 0x0060,
+    0x3cd4, 0xe0c0, 0x0061, 0x3c67, 0xe42e, 0xca28, 0xf7f8, 0xe0c0,
+    0x0042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0080, 0xd113, 0x0013,
+    0xca28, 0xf7f8, 0xe0c0, 0x0061, 0x3ca7, 0xa202, 0x3ca6, 0xe41e,
+    0x0711, 0xe128, 0xe0c0, 0x0060, 0xf048, 0xe41e, 0x1390, 0xf03e,
+    0xe41e, 0x13c1, 0xe42e, 0xe0c0, 0x0040, 0xa201, 0xae17, 0xe042,
+    0xe005, 0x3f00, 0xae03, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111,
+    0x0450, 0xd112, 0x00c8, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e,
+    0xe0c0, 0x0060, 0xf08a, 0xe0c0, 0x0061, 0x2298, 0x4e99, 0xe046,
+    0xaf12, 0xae02, 0x3c9b, 0xe180, 0xe41e, 0x0711, 0xe41e, 0x07d3,
+    0xe41e, 0x137d, 0xe41e, 0x1865, 0xe41e, 0x0557, 0x28de, 0x2a1e,
+    0xb616, 0x3cdc, 0xa200, 0x3cd6, 0x3cda, 0x3cd9, 0x3cdb, 0x3cd8,
+    0xe166, 0x05ab, 0xc710, 0x3d16, 0xe166, 0x0054, 0x9e06, 0xf16a,
+    0x28d4, 0xa102, 0xcc44, 0xa200, 0x3c68, 0xe184, 0x045b, 0x9e06,
+    0x5c68, 0xa802, 0xf07a, 0x2868, 0xe000, 0x0518, 0xe09e, 0xa208,
+    0x3d07, 0x2868, 0xa002, 0x3c68, 0xe190, 0xa200, 0x3c63, 0xe41e,
+    0x0722, 0xa202, 0x3c6e, 0xe42e, 0xe0c0, 0x005a, 0x3cee, 0xe41e,
+    0x0100, 0xa206, 0xe41e, 0x0480, 0xe0c0, 0x005a, 0x3cee, 0xe41e,
+    0x0100, 0xa236, 0xe41e, 0x0499, 0xe41e, 0x04af, 0xe42e, 0xa234,
+    0xe41e, 0x0499, 0xe41e, 0x04cf, 0xa204, 0xe41e, 0x0480, 0xe42e,
+    0x3ced, 0xe0c0, 0x0041, 0xe005, 0x0280, 0xae11, 0xe042, 0x22f0,
+    0x4ef1, 0xe042, 0x2a60, 0xae19, 0xe042, 0xca29, 0xf7f9, 0xce20,
+    0xd111, 0x0000, 0xd112, 0x0c00, 0x88ed, 0x0113, 0xca28, 0xf7f8,
+    0xe42e, 0x3ced, 0xe0c0, 0x0041, 0xe005, 0x0298, 0xae11, 0xe042,
+    0x22f0, 0x4ef1, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x00c0,
+    0xd112, 0x0040, 0x88ed, 0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe161,
+    0x07e0, 0x8911, 0x0145, 0x8911, 0x0144, 0x8911, 0x0146, 0x8911,
+    0x0147, 0x8911, 0x0148, 0x8911, 0x0152, 0x8911, 0x0153, 0x2111,
+    0x4d11, 0xce80, 0x2111, 0x4d11, 0xce82, 0x2111, 0x4d11, 0xce84,
+    0x2111, 0x4d11, 0xce86, 0x2111, 0x4d11, 0xcc72, 0xe42e, 0xe161,
+    0x07e0, 0x8b11, 0x0145, 0x8b11, 0x0144, 0x8b11, 0x0146, 0x8b11,
+    0x0147, 0x8b11, 0x0148, 0x8b11, 0x0152, 0x8b11, 0x0153, 0xca80,
+    0x3511, 0x3d11, 0xca82, 0x3511, 0x3d11, 0xca84, 0x3511, 0x3d11,
+    0xca86, 0x3511, 0x3d11, 0xc872, 0x3511, 0x3d11, 0xe42e, 0xe165,
+    0x07cc, 0x2915, 0x3c30, 0x2915, 0x3c32, 0x2915, 0x3c3b, 0x2915,
+    0x3c33, 0x2915, 0x3c34, 0x2915, 0x3c3a, 0x2915, 0x2915, 0x2915,
+    0x3c3c, 0x2915, 0x3cd3, 0xe42e, 0xe165, 0x07cc, 0x2830, 0x3d15,
+    0x2832, 0x3d15, 0x283b, 0x3d15, 0x2833, 0x3d15, 0x2834, 0x3d15,
+    0x283a, 0x3d15, 0x3d15, 0x3d15, 0x283c, 0x3d15, 0x28d3, 0x3d15,
+    0xe42e, 0xa202, 0x3c8e, 0x28a3, 0x3c8a, 0x28a5, 0x3c8b, 0x28c1,
+    0x3c8f, 0xe165, 0x07c8, 0x2915, 0x3ca5, 0x2915, 0x3ca3, 0x2915,
+    0x3c30, 0x2915, 0x3cd3, 0xa202, 0x3c32, 0x3c34, 0x3ca5, 0x28be,
+    0xa802, 0x3c33, 0xa200, 0x3c3a, 0x3c52, 0xe41e, 0x053b, 0x28be,
+    0x4c3b, 0x3cbe, 0xe42e, 0x28be, 0xaa06, 0x3c3b, 0x2abf, 0x3ec1,
+    0x3e0a, 0xaf09, 0x2072, 0x4c73, 0xf06b, 0x2070, 0x4c71, 0x2a0a,
+    0xa81f, 0x3e0a, 0x2a3b, 0x5a0a, 0x5a0a, 0xe056, 0x2ac1, 0xaf09,
+    0xf04b, 0x3470, 0x3c71, 0xe42e, 0x3472, 0x3c73, 0xe42e, 0xe161,
+    0x0100, 0xa200, 0xc73f, 0x3d11, 0x3c68, 0xd022, 0x000f, 0xe184,
+    0x0565, 0xe41e, 0x186b, 0x2868, 0xa002, 0x3c68, 0xe42e, 0xe0c0,
+    0x005c, 0xe008, 0x0400, 0xe42a, 0xe004, 0x0400, 0xe0c1, 0x005d,
+    0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00, 0xe0c0, 0x005d, 0xe008,
+    0x0400, 0xe190, 0xf7b8, 0xa200, 0x3c69, 0x3c6b, 0xe41e, 0x06b7,
+    0xe42e, 0xe167, 0x0518, 0xa200, 0x3c68, 0xd022, 0x0007, 0xe184,
+    0x058f, 0x2b17, 0xa81f, 0x5a68, 0xe056, 0x2a68, 0xa009, 0x3e68,
+    0xa200, 0x3c68, 0xd022, 0x0007, 0xe184, 0x059c, 0x2b17, 0xa81f,
+    0x5a68, 0xe056, 0x2a68, 0xa009, 0x3e68, 0xe42e, 0xa200, 0x3c69,
+    0x3c6b, 0x3c6c, 0x3c4b, 0xe42e, 0xd146, 0x00c0, 0xd147, 0x00ff,
+    0xd148, 0x00c0, 0xd144, 0x00c0, 0xd145, 0x0000, 0xd14b, 0x0200,
+    0xe004, 0x0180, 0xce30, 0xca32, 0xca32, 0xce84, 0xca32, 0xce86,
+    0xd144, 0x00c1, 0xe42e, 0xcaa2, 0xaf10, 0xa102, 0xf09a, 0xcaa0,
+    0xe190, 0x286d, 0xe428, 0xca9c, 0xe418, 0x078e, 0xf75e, 0xcaa0,
+    0xe190, 0xcaa0, 0xe190, 0xcaa0, 0xe190, 0xcaa0, 0x3c00, 0xca9c,
+    0xe418, 0x078e, 0x2800, 0xaf0e, 0xf6b8, 0xa200, 0x3cec, 0x2800,
+    0xaf0a, 0x3ca3, 0x2800, 0xa83e, 0x3ca4, 0x2a49, 0xf04b, 0xa10a,
+    0xe016, 0x3ca5, 0x28a4, 0xa128, 0xe016, 0x3c5e, 0xf13a, 0xcaa0,
+    0x3c00, 0xaf0e, 0xf0f8, 0xca9c, 0xe418, 0x078e, 0x2800, 0xaf0c,
+    0xa802, 0xe016, 0x3ca5, 0xcaa0, 0xe190, 0xcaa0, 0xe190, 0xaf04,
+    0x30ec, 0xca9c, 0xe418, 0x078e, 0xa200, 0x3ca8, 0x3ca7, 0x3ca0,
+    0xe41e, 0x0606, 0xe41e, 0x0711, 0xe128, 0xe42e, 0x28a0, 0x44a1,
+    0xf048, 0xd149, 0x0000, 0xf03e, 0xd149, 0x0080, 0xd14a, 0x0000,
+    0xd14c, 0x0001, 0xca9c, 0xe418, 0x078e, 0xca9a, 0xf7c8, 0xca9c,
+    0xf7a8, 0xca9e, 0x3ca6, 0xcc92, 0xca94, 0x00a8, 0x0ca7, 0x34a8,
+    0x3ca7, 0xcc90, 0xe42e, 0x28a6, 0xe016, 0xc871, 0xa011, 0xe428,
+    0xaf07, 0xe009, 0x07ff, 0x28a7, 0xe008, 0x07ff, 0xe046, 0xf15a,
+    0xf0de, 0xe161, 0x05e1, 0x2901, 0xc871, 0xa011, 0xaf07, 0xe009,
+    0x07ff, 0xe008, 0x07ff, 0xe046, 0xf08a, 0xe049, 0xe011, 0xaf15,
+    0xe421, 0xe420, 0xa200, 0xe42e, 0xc868, 0xa80e, 0xf028, 0xa210,
+    0x3c95, 0x7895, 0xa203, 0x5a95, 0xaf03, 0xe046, 0xe42e, 0x28a3,
+    0x2aa5, 0x3c8a, 0x3e8b, 0x28a7, 0x2aa6, 0x3c8c, 0x3e8d, 0xa202,
+    0x3c86, 0xe0c0, 0x0041, 0x22f0, 0x4ef1, 0xe042, 0xe005, 0x029c,
+    0xae11, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0000, 0xd112,
+    0x0080, 0xd113, 0x0012, 0xca28, 0xf7f8, 0xca2c, 0xf7fa, 0xe42e,
+    0x288a, 0x2a8b, 0x3ca3, 0x3ea5, 0x288c, 0x2a8d, 0x3ca7, 0x3ea6,
+    0xcc90, 0xcc93, 0xa200, 0x3c86, 0x3ca8, 0x3ca0, 0xe0c0, 0x0041,
+    0x22f0, 0x4ef1, 0xe042, 0xe005, 0x029c, 0xae11, 0xe042, 0xca29,
+    0xf7f9, 0xce20, 0xd111, 0x0000, 0xd112, 0x0080, 0xd113, 0x0013,
+    0xca28, 0xf7f8, 0xe41e, 0x0711, 0xe128, 0xe42e, 0xe0c0, 0x0048,
+    0xe002, 0x0200, 0xca89, 0xe003, 0x00c0, 0xa105, 0xae07, 0xe042,
+    0xca8b, 0xe015, 0xa80f, 0xe042, 0xa002, 0x2298, 0x4e99, 0xe045,
+    0xf047, 0x2e9a, 0xae11, 0xe042, 0xe0c1, 0x0048, 0xe045, 0xe003,
+    0x0200, 0xf037, 0xe000, 0x0200, 0xe0c2, 0x0046, 0xe42e, 0xa200,
+    0x3c9b, 0x2875, 0xaf02, 0xa802, 0xf05a, 0xe0c0, 0x0068, 0x3498,
+    0x3c99, 0x2098, 0x4c99, 0xe0c1, 0x0067, 0xe042, 0xe0c1, 0x0069,
+    0xa80f, 0xf02b, 0xe042, 0xe005, 0x0049, 0xe093, 0x9f01, 0xe004,
+    0xffff, 0x3c9a, 0xe41e, 0x0711, 0xe41e, 0x07d3, 0xa200, 0x3c63,
+    0xe41e, 0x0722, 0xe41e, 0x078e, 0xe41e, 0x05a4, 0xe42e, 0xa200,
+    0x3c9b, 0xe0c0, 0x0062, 0xaf0c, 0xa802, 0xf10a, 0xe0c1, 0x0048,
+    0xe0c0, 0x0060, 0xe045, 0xaf13, 0xae03, 0xa109, 0x3e9b, 0xf063,
+    0xe0c0, 0x0061, 0xae04, 0xe042, 0x3c9b, 0xe0c0, 0x0060, 0x3498,
+    0x3c99, 0xe0c0, 0x0061, 0xae04, 0x3c9a, 0xe41e, 0x0711, 0xe41e,
+    0x07d3, 0xa200, 0x3c69, 0x3c6a, 0x3c6b, 0x3c6c, 0x3c63, 0xe41e,
+    0x0722, 0xd071, 0x802a, 0xe181, 0xe41e, 0x078e, 0xe41e, 0x05a4,
+    0xe42e, 0xd030, 0x0000, 0xd034, 0x0000, 0xd033, 0x0000, 0xd035,
+    0x0000, 0xd036, 0x007f, 0xd037, 0x0000, 0xd038, 0x0000, 0xd04b,
+    0x0001, 0xe42e, 0x3c64, 0xe08e, 0x3c65, 0xe41e, 0x072e, 0xe41e,
+    0x0749, 0x2865, 0xe09e, 0x2864, 0x3c63, 0xe42e, 0x2863, 0xae08,
+    0xe000, 0x0538, 0xe09e, 0x8b17, 0x0033, 0x8b17, 0x0034, 0x8b17,
+    0x0035, 0x8b17, 0x0036, 0x8b17, 0x0037, 0x8b17, 0x0038, 0xc860,
+    0x3517, 0x3d17, 0xc862, 0x3517, 0x3d17, 0xc864, 0x3517, 0x3d17,
+    0xe42e, 0x2864, 0xae08, 0xe000, 0x0538, 0xe09e, 0x8917, 0x0033,
+    0x8917, 0x0034, 0x8917, 0x0035, 0x8917, 0x0036, 0x8917, 0x0037,
+    0x8917, 0x0038, 0x2117, 0x4d17, 0xcc60, 0x2117, 0x4d17, 0xcc62,
+    0x2117, 0x4d17, 0xcc64, 0xe42e, 0xc000, 0x2863, 0xe408, 0x13eb,
+    0x28a6, 0xf188, 0x28a0, 0xf068, 0xe41e, 0x0606, 0xd04c, 0x0000,
+    0xe470, 0xc896, 0xf05a, 0xe41e, 0x0784, 0xd04c, 0x0000, 0xe004,
+    0x0080, 0x2aa1, 0xb616, 0xcc6e, 0xd04b, 0x0001, 0xa202, 0x3ca2,
+    0xe470, 0xd04c, 0x0000, 0xe470, 0xa200, 0x3ca2, 0xe41e, 0x0606,
+    0x28a6, 0xcc96, 0x28a1, 0xe016, 0x3ca1, 0xe42e, 0x286b, 0xf0ba,
+    0xe004, 0x0180, 0xce30, 0xe41e, 0x0820, 0xe41e, 0x0843, 0xd14e,
+    0x0000, 0xe42e, 0xe082, 0x3c9c, 0xe004, 0x0048, 0xe092, 0xd027,
+    0x0000, 0x2869, 0xe41a, 0x07dd, 0xd027, 0x0001, 0x286d, 0xf278,
+    0xca28, 0xf7f8, 0x2098, 0x4c99, 0x2e9b, 0xae11, 0xe042, 0xce20,
+    0xd111, 0x00c0, 0xd112, 0x0040, 0xe0c0, 0x0043, 0xa806, 0xae02,
+    0xa032, 0xce26, 0xca28, 0xf7f8, 0x2c9b, 0xe000, 0x0002, 0x3c9b,
+    0x1c9a, 0xf024, 0x3c9b, 0xf052, 0x2869, 0x3c6b, 0xe418, 0x0825,
+    0x2098, 0x4c99, 0x2e9b, 0xae11, 0xe042, 0x9f01, 0x289c, 0xe092,
+    0xd14e, 0x0000, 0xe42e, 0x2098, 0x4c99, 0x2e9b, 0xae11, 0xe042,
+    0xe005, 0x0048, 0xe093, 0x9f01, 0xe42e, 0xe0c1, 0x0043, 0xa809,
+    0xe429, 0xa200, 0x3c9d, 0x2098, 0x4c99, 0x2e9b, 0xae11, 0xe042,
+    0x8111, 0x9e89, 0xe045, 0xf043, 0x2c9a, 0xae10, 0xe041, 0xe003,
+    0x0200, 0x2869, 0xb606, 0x3c69, 0xe423, 0xe001, 0x0200, 0x3e6a,
+    0x2869, 0xe428, 0xe0c0, 0x0045, 0xaf04, 0xa802, 0x3c69, 0xf648,
+    0x2875, 0xa802, 0xf03a, 0x3c69, 0xe42e, 0xe0c0, 0x0059, 0xa102,
+    0xf068, 0xe0c0, 0x0045, 0x306d, 0x286d, 0xe428, 0x289d, 0xf548,
+    0xe0c0, 0x005c, 0xe008, 0x4000, 0xf4fa, 0xe0c0, 0x005d, 0xe00a,
+    0x4000, 0xe0c2, 0x005d, 0xa202, 0xce00, 0x3c9d, 0xe40e, 0x07e3,
+    0xcbe1, 0xf7f9, 0xcba1, 0xf7f9, 0xe42e, 0x286a, 0xe42a, 0xe41e,
+    0x0820, 0xaf04, 0xe000, 0x0180, 0xce30, 0x286a, 0xa806, 0xf10a,
+    0xa209, 0xe045, 0xae07, 0x3e0a, 0xa2ff, 0x5a0a, 0xca32, 0xca32,
+    0xe051, 0xca30, 0xa104, 0xe008, 0x01ff, 0xce30, 0xce33, 0xe005,
+    0x01f0, 0x1a6a, 0xf095, 0xe004, 0x010b, 0xce32, 0xa200, 0xce32,
+    0xce32, 0xce32, 0xe42e, 0xa021, 0xaf05, 0xe42b, 0xa200, 0xce32,
+    0xa103, 0xf7e1, 0xe42e, 0xba0c, 0xf03a, 0xbcfc, 0xe42e, 0xba4c,
+    0xa20c, 0x3c96, 0x2896, 0xa002, 0x3c96, 0xa140, 0xf0d2, 0xba40,
+    0xf7aa, 0x5896, 0xa102, 0x349e, 0x3c9f, 0x2896, 0xe41e, 0x0890,
+    0x009e, 0x0c9f, 0xe42e, 0xe16b, 0xe42e, 0xba0c, 0xf03a, 0xbe7e,
+    0xe42e, 0xba4c, 0xa20c, 0x3c96, 0x2896, 0xa002, 0x3c96, 0xa140,
+    0xf162, 0xba40, 0xf7aa, 0x5896, 0xa102, 0x349e, 0x3c9f, 0x2896,
+    0xe41e, 0x0890, 0x009e, 0x0c9f, 0x3c9f, 0x8c9f, 0x0000, 0xa002,
+    0xaf02, 0xe012, 0xe42c, 0xe012, 0xe16a, 0xe42e, 0xe16b, 0xe42e,
+    0xa120, 0xf050, 0xa020, 0x3c97, 0x7497, 0xe42e, 0x3c97, 0xba5e,
+    0x5897, 0x7697, 0xe056, 0xe42e, 0xba40, 0xe42a, 0xc868, 0xa80e,
+    0x3c00, 0xe016, 0xe428, 0x7400, 0xe016, 0xe42e, 0x2a30, 0xa103,
+    0x2826, 0xe425, 0xf02b, 0x2827, 0xb7f4, 0xa002, 0x3c46, 0xa104,
+    0xe424, 0xf04a, 0xa25a, 0x3c47, 0xe42e, 0xbc0e, 0x3c00, 0xe42d,
+    0x281f, 0xf02a, 0xbc0e, 0x3c01, 0xe42d, 0x2801, 0xae06, 0x4c00,
+    0x3c47, 0xe161, 0x0708, 0xe164, 0x0700, 0x8840, 0x0022, 0xe41e,
+    0x08d7, 0xe42d, 0x2830, 0xa104, 0xe428, 0x2841, 0xe161, 0x0768,
+    0xe164, 0x0704, 0x8841, 0x0022, 0xe41e, 0x08d7, 0xe42e, 0xe082,
+    0xa040, 0xe094, 0xa040, 0xe096, 0xe004, 0x00ff, 0x3c03, 0xa200,
+    0x3c05, 0x3c06, 0x3c07, 0x3c08, 0x3c09, 0xe184, 0x0923, 0xba40,
+    0xf0ba, 0xe0c6, 0x0080, 0x4403, 0xae10, 0xe0c7, 0x0080, 0x4603,
+    0xe056, 0x3d11, 0xf0ce, 0xa202, 0x5800, 0xae10, 0x3d11, 0x2206,
+    0x4e07, 0xa202, 0x5805, 0xe056, 0x3406, 0x3c07, 0x281f, 0xf22a,
+    0xba40, 0xf14a, 0xe0c6, 0x0080, 0x4403, 0xae10, 0xe0c7, 0x0080,
+    0x4603, 0xe056, 0x3d12, 0xe0c6, 0x0080, 0x4403, 0xae10, 0xe0c7,
+    0x0080, 0x4603, 0xe056, 0x3d13, 0xf0de, 0xa202, 0x5801, 0xae10,
+    0x3d12, 0x3d13, 0x2208, 0x4e09, 0xa202, 0x5805, 0xe056, 0x3408,
+    0x3c09, 0x2805, 0xa002, 0x3c05, 0x2006, 0x4c07, 0xe014, 0x3514,
+    0x3d14, 0x2208, 0x4e09, 0xe015, 0x3714, 0x3f14, 0xe42e, 0xe0c4,
+    0x3fff, 0xe40d, 0x0ae9, 0x3c4a, 0x284a, 0xe01a, 0x4488, 0xe408,
+    0x0ae9, 0x2a7f, 0xf039, 0x2a89, 0xf03b, 0xe408, 0x0ae9, 0xa200,
+    0x3c89, 0xbc12, 0xe40d, 0x0ae9, 0xa10a, 0xb4a8, 0xa104, 0xe400,
+    0x0ae9, 0xb7b4, 0xa006, 0x3c30, 0x2849, 0xf0da, 0xbdfe, 0xe40d,
+    0x0ae9, 0x1820, 0xf0ea, 0x0820, 0x3c20, 0xe41e, 0x13d5, 0xe40a,
+    0x0ae9, 0xf07e, 0xbdfe, 0xe40d, 0x0ae9, 0x1820, 0xe408, 0x0ae5,
+    0x2849, 0xf04a, 0x7411, 0x3c31, 0xf05e, 0x7411, 0x1831, 0xe408,
+    0x0ae5, 0x2849, 0xf0ca, 0xa200, 0x3c32, 0x3c33, 0x2818, 0xf138,
+    0xba40, 0x3c32, 0xf10a, 0xba40, 0x3c33, 0xf0de, 0x2818, 0xf0b8,
+    0xba40, 0x1832, 0xe408, 0x0ae5, 0x2832, 0xf05a, 0xba40, 0x1833,
+    0xe408, 0x0ae5, 0x2849, 0xf2aa, 0x281b, 0x5c32, 0x3c3c, 0xa200,
+    0x3c34, 0x2832, 0xf10a, 0xe41e, 0x0af6, 0x3c34, 0xe016, 0x3c35,
+    0xf0aa, 0xa202, 0x3c35, 0x28a3, 0xe01a, 0x3c36, 0x2831, 0x3c37,
+    0x2833, 0x3c38, 0x2832, 0xe016, 0x4419, 0x3c3a, 0x2832, 0x0833,
+    0xb674, 0x3c3b, 0xa106, 0xf0aa, 0xa202, 0x5830, 0x2a3b, 0xa105,
+    0xf029, 0xae06, 0x2a55, 0xe055, 0x3e55, 0x2849, 0xe40a, 0x0a08,
+    0x287e, 0xa104, 0xe40a, 0x0a06, 0x2875, 0xa802, 0xf26a, 0xe0c0,
+    0x0065, 0xa808, 0xf108, 0x3c7f, 0xe0c0, 0x0065, 0xaf06, 0xa806,
+    0xe40a, 0x0a06, 0xa102, 0xf07a, 0xa102, 0xf02a, 0xf09e, 0x28a3,
+    0xf07a, 0xf3de, 0xa202, 0x3c7f, 0x28a5, 0xf02a, 0xf38e, 0xa2fa,
+    0xe0c2, 0x0071, 0x2855, 0xae04, 0x4c30, 0x2a5c, 0xae3d, 0xe056,
+    0xe0c2, 0x0073, 0xa200, 0xe42e, 0x287f, 0xf0fa, 0x28a5, 0xf21a,
+    0x284a, 0xf1f8, 0x287c, 0xf23a, 0x2a32, 0xf04b, 0x2a34, 0xe409,
+    0x09ea, 0xa102, 0x3c7c, 0xf15e, 0x287d, 0xf19a, 0xa102, 0xf06a,
+    0xa102, 0xf060, 0x28a3, 0xf04a, 0xf12e, 0x28a5, 0xf108, 0x287c,
+    0x2a32, 0xf04b, 0x2a34, 0xe409, 0x09fe, 0xa102, 0xf04a, 0x3c7c,
+    0xa200, 0xe42e, 0xa202, 0x3c89, 0x3c7e, 0xe42e, 0xa204, 0x3c7e,
+    0x2849, 0xf09a, 0x28a5, 0xf10a, 0xe41e, 0x0853, 0xe40d, 0x0ae9,
+    0x3c3d, 0xf0ae, 0x28a5, 0xf08a, 0xe41e, 0x0853, 0xe40d, 0x0ae9,
+    0x1c3d, 0xe408, 0x0ae5, 0x2849, 0xf10a, 0xe41e, 0x1151, 0x28c8,
+    0xe008, 0x03ff, 0x2a3b, 0xa105, 0xf029, 0xae14, 0xe0c1, 0x007a,
+    0xe055, 0xe0c3, 0x007a, 0xf2de, 0x2813, 0xa102, 0xf034, 0xf13a,
+    0xf28e, 0x7414, 0x1ce3, 0xe408, 0x0ae5, 0x2832, 0xe016, 0x4422,
+    0xf20a, 0xe41e, 0x086d, 0xe40d, 0x0ae9, 0x10e4, 0x1ce5, 0xe408,
+    0x0ae5, 0xf17e, 0x2815, 0xf158, 0xe41e, 0x086d, 0xe40d, 0x0ae9,
+    0x10e3, 0x1ce4, 0xe408, 0x0ae5, 0x2832, 0xe016, 0x4422, 0xf09a,
+    0xe41e, 0x086d, 0xe40d, 0x0ae9, 0x10e5, 0x1ce6, 0xe408, 0x0ae5,
+    0x2830, 0xa104, 0xf038, 0xba40, 0x3c3e, 0x2824, 0x3c40, 0x2825,
+    0x3c41, 0x2830, 0xf0ea, 0xba40, 0xf0ca, 0xbc3e, 0x3c40, 0xe40d,
+    0x0ae9, 0x2830, 0xa104, 0xf058, 0xbc3e, 0x3c41, 0xe40d, 0x0ae9,
+    0x2849, 0xf0da, 0x2834, 0xf078, 0xe41e, 0x18ae, 0x28c1, 0xf074,
+    0x3c39, 0xf05e, 0x2839, 0x3cc1, 0xe0c2, 0x0077, 0x2849, 0xf0ba,
+    0x285e, 0xf05a, 0x28a5, 0xf03a, 0xe41e, 0x14f6, 0xe41e, 0x14bc,
+    0xe41e, 0x0b10, 0x2830, 0xe016, 0xe41a, 0x0b19, 0xe40a, 0x0ae9,
+    0xe41e, 0x08a6, 0xe40d, 0x0ae9, 0x2849, 0xf06a, 0xe41e, 0x104c,
+    0xe40a, 0x0ae9, 0xf1fe, 0x28a3, 0xf1da, 0x28a5, 0xf04a, 0xba40,
+    0xba40, 0xf18e, 0xba40, 0xf16a, 0xbc0c, 0xe40d, 0x0ae9, 0xf12a,
+    0xa106, 0xf08a, 0xa104, 0xf79a, 0xe41e, 0x0853, 0xe40d, 0x0ae9,
+    0xf74e, 0xe41e, 0x0853, 0xe40d, 0x0ae9, 0xbc40, 0xe40d, 0x0ae9,
+    0xf6ce, 0x2830, 0xe01a, 0x4421, 0xf03a, 0xbc04, 0xf2bd, 0x3c3f,
+    0xe0c6, 0x0033, 0xf27d, 0x0828, 0xa400, 0xa566, 0x3c42, 0xa200,
+    0x3c43, 0x3c44, 0x3c45, 0x282a, 0xf10a, 0xbc04, 0xf1bd, 0x3c43,
+    0xa102, 0xf0ba, 0xbe0c, 0xf16d, 0xae02, 0xa83e, 0x3c44, 0xbe0c,
+    0xf11d, 0xae02, 0xa83e, 0x3c45, 0x2a3a, 0x284a, 0xe419, 0x0b09,
+    0x3c4a, 0x183c, 0xf072, 0xa202, 0xe42e, 0x283c, 0x3c4a, 0xa202,
+    0xe42e, 0xe16a, 0x28c1, 0xf094, 0xe41e, 0x186b, 0x28c1, 0xe41e,
+    0x1872, 0x28c1, 0xe41e, 0x187b, 0xa200, 0xe42e, 0x28a5, 0xe016,
+    0xe42a, 0x2835, 0xe42a, 0x2838, 0x1833, 0xe42a, 0x28a3, 0xf048,
+    0x2836, 0xe016, 0xe42e, 0x2836, 0xe42a, 0x2837, 0x1831, 0xe016,
+    0xe42e, 0xe049, 0xc70f, 0x7e50, 0xaf21, 0xae02, 0xe046, 0xe42e,
+    0xe41e, 0x0bff, 0xd1f3, 0x0000, 0xe162, 0x0270, 0x2912, 0xcfe4,
+    0xe42e, 0xe161, 0x0270, 0x2830, 0xa102, 0xf03a, 0xe161, 0x0290,
+    0x2840, 0x3c04, 0xe162, 0x01b0, 0xe41e, 0x0b91, 0xe42a, 0xd1f3,
+    0x0000, 0xe162, 0x01b0, 0x8840, 0x0022, 0xe184, 0x0b30, 0x2912,
+    0xcfe4, 0x2830, 0xa104, 0xe428, 0x2841, 0x3c04, 0xe161, 0x02b0,
+    0xe162, 0x01d0, 0xe41e, 0x0b91, 0xe42a, 0xd1f3, 0x0020, 0xe162,
+    0x01d0, 0x8841, 0x0022, 0xe184, 0x0b46, 0x2912, 0xcfe4, 0xe161,
+    0x05e0, 0xa23e, 0xc71f, 0x3d11, 0x2840, 0xe000, 0x01b0, 0xe094,
+    0x2a40, 0x8840, 0x0022, 0xe184, 0x0b5a, 0x290a, 0xe000, 0x05e0,
+    0xe092, 0x3f01, 0xa103, 0xd1f9, 0x0000, 0xe162, 0x05e0, 0xd022,
+    0x001f, 0xe184, 0x0b64, 0x2912, 0xcff0, 0xe162, 0x01d0, 0x2902,
+    0x3cc2, 0xe41e, 0x0c51, 0xe41e, 0x0c7d, 0x34c5, 0x3cc6, 0x2902,
+    0xae02, 0xe000, 0x0160, 0xe09e, 0x2117, 0x4d17, 0x2317, 0x4f17,
+    0x10c7, 0x1cc8, 0x12c7, 0x1ec8, 0xe010, 0xe011, 0xe046, 0xb624,
+    0xb608, 0x3ccf, 0x2902, 0xe41e, 0x0c4a, 0xa102, 0xb628, 0x3ccd,
+    0x2902, 0xaf02, 0xe000, 0x01a0, 0xe09e, 0x2907, 0x3cce, 0xa202,
+    0xe42e, 0xba40, 0xf098, 0x8804, 0x0022, 0xe184, 0x0b98, 0x2911,
+    0x3d12, 0xa202, 0xe42e, 0x28c0, 0xe42a, 0xe082, 0x3c08, 0x2c12,
+    0x5832, 0x3400, 0x3c01, 0x2c31, 0x5832, 0x0832, 0x3402, 0x3c03,
+    0x2804, 0x3c05, 0xe163, 0x05e0, 0xa200, 0xc71f, 0x3d13, 0xbc0a,
+    0xe40d, 0x0bfc, 0xf0aa, 0xa102, 0xf17a, 0xa102, 0xf26a, 0xa104,
+    0xf1da, 0xa102, 0xf1ba, 0xf2fe, 0xe41e, 0x0853, 0xe40d, 0x0bfc,
+    0xa002, 0x1002, 0x1c03, 0xe012, 0xf032, 0x0000, 0x0c01, 0x3402,
+    0x3c03, 0xa203, 0xf14e, 0xe41e, 0x0853, 0xe40d, 0x0bfc, 0xa002,
+    0x0002, 0x0c03, 0x1000, 0x1c01, 0xf70e, 0xe41e, 0x0853, 0xe40d,
+    0x0bfc, 0x2832, 0xa2fd, 0xf03e, 0xbc40, 0xa2ff, 0xe41e, 0x0c19,
+    0xf1c4, 0x3d12, 0xe41e, 0x0c35, 0x2805, 0xa102, 0x3c05, 0xa004,
+    0xe42a, 0xf46e, 0x2808, 0xa102, 0xe092, 0xe163, 0x05e0, 0x2805,
+    0xf0a4, 0x2913, 0x8111, 0xf7e8, 0x2901, 0x3d12, 0x2805, 0xa102,
+    0x3c05, 0xf76e, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0x28c1,
+    0xe424, 0xae04, 0x08c1, 0x08c1, 0xe000, 0x0620, 0xe09e, 0xe166,
+    0x020d, 0xe165, 0x0214, 0xd022, 0x0002, 0xe184, 0x0c12, 0x2117,
+    0x4d17, 0x9f16, 0x9f15, 0x28c1, 0xe41e, 0x0c7d, 0x34c3, 0x3cc4,
+    0xe42e, 0x3c06, 0x3e07, 0xe163, 0x0230, 0x2816, 0x2a5e, 0xb5f6,
+    0xe424, 0xae02, 0xa002, 0xcc44, 0xe184, 0x0c32, 0x2d13, 0x2b0b,
+    0x1c06, 0x1a07, 0xf078, 0xf069, 0xe086, 0xe002, 0x0230, 0xaf02,
+    0xe42e, 0x8113, 0x8113, 0xa2fe, 0xe42e, 0x3c09, 0x2808, 0xe092,
+    0x28c0, 0xa102, 0xcc44, 0xe184, 0x0c40, 0x2901, 0x1809, 0xf03a,
+    0x8111, 0xe42e, 0xe082, 0x1808, 0xe000, 0x05e0, 0xe096, 0xa202,
+    0x3d03, 0xe42e, 0xaf02, 0xae04, 0xe000, 0x0101, 0xe09e, 0x2907,
+    0xe42e, 0xaf02, 0xae04, 0xe000, 0x0103, 0xe09e, 0x2907, 0xe42e,
+    0x3c0a, 0xca28, 0xf7f8, 0xe0c0, 0x0042, 0xe000, 0x0180, 0x080a,
+    0xce20, 0xd111, 0x05e0, 0xd112, 0x0020, 0xd113, 0x0003, 0xca28,
+    0xf7f8, 0xe0c0, 0x0041, 0x22f0, 0x4ef1, 0xe042, 0xe005, 0x055c,
+    0xae0f, 0x0a0a, 0xe042, 0xce20, 0xd111, 0x05e0, 0xd112, 0x0020,
+    0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0x3c0a, 0xaf02, 0xae06,
+    0xe0c1, 0x0041, 0xe042, 0x22f0, 0x4ef1, 0xe042, 0xe005, 0x055c,
+    0xae0f, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x05e0, 0xd112,
+    0x0004, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe004, 0x05e0, 0xe09e,
+    0x2117, 0x4d17, 0x2a0a, 0xa803, 0xe42b, 0x2117, 0x4d17, 0xe42e,
+    0xba4e, 0x3c4d, 0xa184, 0xe404, 0x0dae, 0xa17c, 0xe400, 0x0dae,
+    0xba4a, 0x3c5d, 0xba42, 0xe408, 0x0dae, 0xba4e, 0x3c1c, 0xa112,
+    0xe404, 0x0dae, 0xa154, 0xe400, 0x0dae, 0xbc3e, 0x3c10, 0xa202,
+    0x3c1f, 0x284d, 0xa1c8, 0xf06a, 0xa124, 0xf04a, 0xa114, 0xf02a,
+    0xf2fe, 0xbc06, 0x3c1f, 0xbc08, 0xe408, 0x0dae, 0xbc08, 0xe408,
+    0x0dae, 0xba40, 0xba40, 0x3cb0, 0xf23a, 0xa201, 0x3eb2, 0x3eb4,
+    0xe160, 0x0000, 0xba40, 0xf11a, 0x2ab2, 0xae03, 0xe056, 0x3cb2,
+    0xe080, 0xe41e, 0x0f01, 0x2ab4, 0xae03, 0xe056, 0x3cb4, 0xe080,
+    0xa201, 0xe41e, 0x0f34, 0xf07e, 0x2ab2, 0xae03, 0x3eb2, 0x2ab4,
+    0xae03, 0x3eb4, 0xe080, 0xa002, 0xe090, 0xa110, 0xf648, 0xbc18,
+    0xe40d, 0x0dae, 0xa008, 0x3c11, 0xa202, 0x5811, 0x3c12, 0xbc04,
+    0x3c13, 0xe40d, 0x0dae, 0xa102, 0xf034, 0xf06a, 0xf21e, 0xbc18,
+    0xa008, 0x3c14, 0xf1de, 0xba40, 0x3c15, 0xe41e, 0x086d, 0x34e7,
+    0x3ce8, 0xe41e, 0x086d, 0x34e9, 0x3cea, 0xbdfe, 0xe40d, 0x0dae,
+    0x3ceb, 0xf0ea, 0xa102, 0xcc44, 0xe162, 0x0250, 0xe184, 0x0d1b,
+    0xe41e, 0x086d, 0x3512, 0x3d12, 0xe41e, 0x0e7e, 0xf01e, 0xe40d,
+    0x0dae, 0xbc20, 0xe40d, 0x0dae, 0x3c16, 0xba40, 0x3c17, 0x2250,
+    0x4e51, 0xe0c4, 0x007f, 0xe40d, 0x0dae, 0xa002, 0x3c50, 0xe0c4,
+    0x007f, 0xe40d, 0x0dae, 0xa002, 0x3c51, 0x8450, 0x8251, 0xe018,
+    0x3c1b, 0x2c57, 0xf1ba, 0x2050, 0x4c51, 0xe046, 0xf20a, 0x2c57,
+    0xaf10, 0xe008, 0x00ff, 0x1850, 0xf064, 0x2c57, 0xe008, 0x00ff,
+    0x1851, 0xf152, 0x2050, 0x4c51, 0xae08, 0xe0c2, 0x006f, 0xe0c2,
+    0x004f, 0xa2fe, 0x3c57, 0xe40e, 0x0dae, 0x2850, 0xe008, 0x00ff,
+    0xae10, 0x2a51, 0xe009, 0x00ff, 0xe056, 0x3c57, 0xa200, 0x3c19,
+    0xba40, 0x3c18, 0xf098, 0xba40, 0x3c19, 0x2851, 0xae02, 0x3c51,
+    0x281b, 0xae02, 0x3c1b, 0xe0c0, 0x0059, 0xa102, 0xf038, 0xe41e,
+    0x0e3a, 0xba40, 0x3c1a, 0x4c18, 0xf3aa, 0xba40, 0x3c58, 0x3c59,
+    0x3c5a, 0x3c5b, 0xf14a, 0xe41e, 0x0853, 0x3c58, 0xe41e, 0x0853,
+    0x3c59, 0xe41e, 0x0853, 0x2a18, 0xf029, 0xae02, 0x3c5a, 0xe41e,
+    0x0853, 0x2a18, 0xf029, 0xae02, 0x3c5b, 0xf21d, 0xe0c0, 0x0059,
+    0xa102, 0xf0e8, 0x2a1f, 0x2058, 0x4c59, 0xf02b, 0xae02, 0xe0c2,
+    0x0076, 0x205a, 0x4c5b, 0xf02b, 0xae02, 0xe0c2, 0x0077, 0xa200,
+    0x3c82, 0x3c83, 0x281d, 0x3cde, 0x3cdf, 0xba40, 0xe016, 0xe41a,
+    0x0e93, 0xf05a, 0xe41e, 0x089c, 0xa202, 0xe42e, 0xe16a, 0xa200,
+    0xe42e, 0xe41e, 0x0853, 0x3c20, 0xbc3e, 0xe40d, 0x0e37, 0x1810,
+    0xf0ea, 0x0810, 0x3c10, 0xe41e, 0x13ab, 0x3c66, 0xa202, 0xe41e,
+    0x0722, 0xa203, 0x3e94, 0x2866, 0xe40a, 0x0e37, 0xba40, 0x3c21,
+    0xba40, 0x3c22, 0xbc0e, 0xe40d, 0x0e37, 0x3c23, 0xe408, 0x0e37,
+    0xbc3e, 0xe40d, 0x0e37, 0x3c24, 0xbc3e, 0x3c25, 0xe40d, 0x0e37,
+    0xba40, 0x3c26, 0xba42, 0x3c27, 0xbe34, 0xe40d, 0x0e37, 0xa034,
+    0x3c28, 0xe404, 0x0e37, 0xa168, 0xe402, 0x0e37, 0xbe34, 0xe40d,
+    0x0e37, 0xa034, 0xe404, 0x0e37, 0xa168, 0xe402, 0x0e37, 0xbe18,
+    0xe40d, 0x0e37, 0x3c29, 0x3c2d, 0xba40, 0x3c2a, 0xba40, 0x3c2b,
+    0xba40, 0x3c2c, 0xa200, 0x3c2e, 0x3cb1, 0x2820, 0x3c02, 0xe41e,
+    0x1474, 0xe41e, 0x0631, 0xf30a, 0xba40, 0x3c2e, 0xba40, 0x3cb1,
+    0xf28a, 0xa201, 0x3eb3, 0x3eb5, 0xe160, 0x0000, 0xe080, 0xa10c,
+    0x182e, 0x182e, 0xf132, 0xba40, 0xf11a, 0x2ab3, 0xae03, 0xe056,
+    0x3cb3, 0xe080, 0xe41e, 0x0f01, 0x2ab5, 0xae03, 0xe056, 0x3cb5,
+    0xe080, 0xa203, 0xe41e, 0x0f34, 0xf07e, 0x2ab3, 0xae03, 0x3eb3,
+    0x2ab5, 0xae03, 0x3eb5, 0xe080, 0xa002, 0xe090, 0xa110, 0xf5f8,
+    0xbe18, 0xf06d, 0x3c2d, 0xe41e, 0x089c, 0xa202, 0xe42e, 0xe16a,
+    0xa200, 0xe42e, 0x2a1c, 0xa115, 0xe004, 0x0129, 0xf2d7, 0xa103,
+    0xe004, 0x02a3, 0xf297, 0xa113, 0xe004, 0x06f6, 0xf257, 0xa103,
+    0xe004, 0x0dec, 0xf217, 0xa113, 0xe004, 0x17bb, 0xf1d7, 0xa103,
+    0xe004, 0x34bc, 0xf197, 0xa103, 0xe004, 0x3c00, 0xf157, 0xa113,
+    0xe004, 0x6000, 0xf117, 0xa103, 0xe004, 0x6600, 0xf0d7, 0xa111,
+    0xe004, 0x1437, 0xae08, 0xf087, 0xa103, 0xe004, 0x21c0, 0xae08,
+    0xf037, 0xe004, 0x17bb, 0xae12, 0x841b, 0xe182, 0x0180, 0xe019,
+    0xc407, 0xd022, 0x000f, 0xe184, 0x0e77, 0xe046, 0xf034, 0x8117,
+    0xe190, 0xe08e, 0xae02, 0xa520, 0x3c1d, 0xe42e, 0xe0c0, 0x0041,
+    0x22f0, 0x4ef1, 0xe042, 0xe005, 0x029e, 0xae11, 0xe042, 0xca29,
+    0xf7f9, 0xce20, 0xd111, 0x0250, 0xd112, 0x0200, 0xd113, 0x0002,
+    0xca28, 0xf7f8, 0xe42e, 0xba40, 0xf15a, 0xba4e, 0xe0c1, 0x0059,
+    0xa103, 0xf039, 0xe0c2, 0x006c, 0xe002, 0x00ff, 0xf0b8, 0xba5e,
+    0xba5f, 0xae20, 0xe056, 0xe0c1, 0x0059, 0xa103, 0xf039, 0xe0c2,
+    0x006c, 0xba40, 0xf02a, 0xba40, 0xba40, 0xf08a, 0xba44, 0xba40,
+    0xba40, 0xf04a, 0xba4e, 0xba4e, 0xba4e, 0xba40, 0xf03a, 0xbc0a,
+    0xbc0a, 0xba40, 0xf06a, 0xba7e, 0xe190, 0xba7e, 0xe190, 0xba40,
+    0xba40, 0x3c82, 0xe016, 0xe161, 0x05bd, 0xe41a, 0x0ee6, 0xf1ca,
+    0xba40, 0x3c83, 0xe016, 0xe161, 0x05c2, 0xe41a, 0x0ee6, 0xf14a,
+    0x2882, 0x4c83, 0xf02a, 0xba40, 0xba40, 0x3c4f, 0xba40, 0xf09a,
+    0xba40, 0xbc20, 0xbc20, 0xbc20, 0xbc20, 0xbc20, 0xbc20, 0x3cdf,
+    0xe16a, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0xe41e, 0x0853,
+    0xcc44, 0xa002, 0x3d11, 0xba46, 0xba46, 0xe184, 0x0ef3, 0xe41e,
+    0x0853, 0xe41e, 0x0853, 0xba40, 0xba48, 0xa002, 0x3d11, 0xba48,
+    0xa002, 0x3d11, 0xba48, 0xa002, 0x3d11, 0xba48, 0x3d11, 0xa202,
+    0xe42e, 0xd022, 0x000f, 0xa10c, 0xf034, 0xd022, 0x003f, 0xe161,
+    0x05e0, 0xa210, 0x3c06, 0x3c07, 0xa200, 0x3c08, 0x3c09, 0xe09c,
+    0xe09e, 0xe184, 0x0f31, 0x2807, 0xf10a, 0xe41e, 0x086d, 0xe42d,
+    0x0806, 0xe000, 0x0100, 0xe008, 0x00ff, 0x3c07, 0x4c09, 0xe01a,
+    0xe016, 0xe09e, 0xa202, 0x3c09, 0x2807, 0xf028, 0x2806, 0x3c06,
+    0xe08d, 0xa003, 0xe09d, 0xa803, 0xf059, 0xe085, 0xae11, 0xe056,
+    0x3d11, 0xe094, 0xe08e, 0xe42e, 0x3e08, 0x3c06, 0xa211, 0x3e07,
+    0xa10c, 0xf064, 0xb690, 0xa00c, 0x3c06, 0xa240, 0x3c07, 0x2806,
+    0x2a08, 0xf02b, 0xa01c, 0xae08, 0x3c06, 0xe0c0, 0x0041, 0x22f0,
+    0x4ef1, 0xe042, 0xe005, 0x02ac, 0xae11, 0xe042, 0x0806, 0xca29,
+    0xf7f9, 0xce20, 0xd111, 0x05e0, 0x2807, 0xce24, 0xd113, 0x0002,
+    0xca28, 0xf7f8, 0xe42e, 0x2875, 0xa802, 0xe42a, 0xe0c0, 0x0045,
+    0xaf04, 0xa802, 0xe42e, 0xa200, 0xba4f, 0xe042, 0xe003, 0x00ff,
+    0xf7cb, 0x3c00, 0xa200, 0xba4f, 0xe042, 0xe003, 0x00ff, 0xf7cb,
+    0x3c01, 0xe41e, 0x0f7a, 0xe42a, 0xe41e, 0x0623, 0xf6d8, 0xe41e,
+    0x089c, 0xe42e, 0x2800, 0xf10a, 0xa102, 0xf11a, 0xa104, 0xf12a,
+    0xa102, 0xf13a, 0xa102, 0xf14a, 0x2a01, 0xf04b, 0xba4e, 0xa103,
+    0xf7e9, 0xa202, 0xe42e, 0xe41e, 0x0fa2, 0xf0de, 0xe41e, 0x0fc9,
+    0xf0ae, 0xe41e, 0x1024, 0xf07e, 0xe41e, 0x1034, 0xf04e, 0xe41e,
+    0x1042, 0xf01e, 0xe42a, 0xc868, 0xa80e, 0xe016, 0xe428, 0xe41e,
+    0x089c, 0xe42e, 0xbc3e, 0x1810, 0xf0da, 0x0810, 0x3c10, 0xe41e,
+    0x13ab, 0x3c66, 0xa200, 0xe41e, 0x0722, 0xa201, 0x3e94, 0x2866,
+    0xe42a, 0x2882, 0xe161, 0x05bd, 0xe418, 0x0fbd, 0x2883, 0xe161,
+    0x05c2, 0xe418, 0x0fbd, 0xa202, 0xe42e, 0x2911, 0xa102, 0xcc44,
+    0xe184, 0x0fc7, 0x2901, 0xe41e, 0x0890, 0x2901, 0xe41e, 0x0890,
+    0xe42e, 0xe166, 0x004c, 0x2882, 0xe161, 0x05bf, 0xf038, 0xe161,
+    0x05c4, 0x4c83, 0xf09a, 0x2911, 0xe41e, 0x0890, 0x2911, 0xe41e,
+    0x0890, 0x2911, 0xf02e, 0xa230, 0x3c02, 0x284f, 0xe016, 0xe428,
+    0xba46, 0xe0c2, 0x007b, 0xa112, 0xb604, 0xe42a, 0xa012, 0xe049,
+    0xa200, 0xa107, 0xb426, 0xa105, 0xb426, 0xa105, 0xb5f6, 0xcc44,
+    0xe184, 0x1021, 0xa201, 0xba40, 0xf038, 0x9f96, 0xf2be, 0xba42,
+    0xba40, 0xba48, 0xba40, 0x3c03, 0xba40, 0xba40, 0xae32, 0xe055,
+    0xba4e, 0xe055, 0x2803, 0xf0ba, 0xba4a, 0xae10, 0xe055, 0xba4a,
+    0xae1c, 0xe055, 0xba48, 0xae28, 0xe055, 0xf10e, 0xba40, 0xf0ea,
+    0xba4a, 0xae10, 0xe055, 0xba40, 0xf09a, 0xba4a, 0xae1c, 0xe055,
+    0xba40, 0xf04a, 0xba48, 0xae28, 0xe055, 0x9f96, 0x2802, 0xe41e,
+    0x0890, 0xe190, 0xa202, 0xe42e, 0x2801, 0xf0da, 0xa102, 0xcc44,
+    0xe004, 0x00ff, 0xe184, 0x102d, 0xba4f, 0xe052, 0xe002, 0x00ff,
+    0xe016, 0xe42a, 0xa202, 0xe42e, 0xa202, 0xba4f, 0xe003, 0x00ff,
+    0xf039, 0xba4f, 0xa204, 0xba4f, 0xa002, 0x2a01, 0xe045, 0xf7c1,
+    0xa202, 0xe42e, 0x2801, 0xa420, 0xa102, 0xcc44, 0xe184, 0x1049,
+    0xba4e, 0xe190, 0xa202, 0xe42e, 0x2c31, 0x3cd0, 0xa202, 0x3cd1,
+    0xa200, 0x3cd2, 0x3cd3, 0x28a3, 0xe016, 0xe428, 0x28a5, 0xf0ca,
+    0xe41e, 0x10e9, 0xba40, 0xba40, 0xb7f0, 0xb634, 0x3cd1, 0xa200,
+    0x3cd0, 0xa202, 0xe42e, 0xba40, 0xf048, 0xa202, 0x3cd2, 0xe42e,
+    0x2816, 0xe42a, 0xae02, 0x3c09, 0x2812, 0x5832, 0x3400, 0x3c01,
+    0x2c31, 0x5832, 0x0832, 0x3402, 0x3c03, 0xbc0c, 0xe40d, 0x10e6,
+    0xe40a, 0x10e4, 0xa102, 0xf0ca, 0xa102, 0xf1da, 0xa102, 0xf24a,
+    0xa102, 0xf3aa, 0xa102, 0xe40a, 0x10c4, 0xe40e, 0x10cc, 0xe41e,
+    0x0853, 0xe40d, 0x10e6, 0xa002, 0x1002, 0x1c03, 0xe012, 0xf032,
+    0x0000, 0x0c01, 0xa203, 0xe41e, 0x10f0, 0xe408, 0x1099, 0xa203,
+    0x3ed2, 0xf5ce, 0xbc40, 0xe40d, 0x10e6, 0xa2ff, 0xe41e, 0x10f0,
+    0xe40a, 0x10e6, 0xf53e, 0xe41e, 0x0853, 0xe40d, 0x10e6, 0xa002,
+    0x1002, 0x1c03, 0xe012, 0xf032, 0x0000, 0x0c01, 0x3c06, 0xa802,
+    0x4432, 0xbc21, 0xf34d, 0x5a32, 0xe041, 0x3e07, 0xe41e, 0x1108,
+    0xf2ea, 0xe40e, 0x1075, 0xbc20, 0xf2ad, 0xa102, 0x5832, 0x0832,
+    0xe41e, 0x1123, 0xe40e, 0x1075, 0xe41e, 0x10e9, 0xa202, 0x3cd3,
+    0xa200, 0x3cd0, 0xe40e, 0x1075, 0xbc20, 0xf19d, 0x3cd0, 0x28d0,
+    0x5832, 0x0832, 0xa2ff, 0xe41e, 0x10f0, 0xf7a8, 0x2832, 0xf09a,
+    0x2834, 0xf078, 0x28d0, 0xae02, 0xa2ff, 0xe41e, 0x10f0, 0xf7b8,
+    0xa2fe, 0x3cd1, 0xe40e, 0x1075, 0xa202, 0xe42e, 0xe16a, 0xa200,
+    0xe42e, 0xc410, 0xe161, 0x01f1, 0xa200, 0xc71f, 0x3d31, 0xe42e,
+    0x3c04, 0x3e05, 0xe161, 0x01f0, 0x8809, 0x0022, 0xe184, 0x1103,
+    0x2d11, 0x2b09, 0x1c04, 0x1a05, 0xf068, 0xf059, 0x8111, 0xa200,
+    0x3d09, 0xf05e, 0x8111, 0x8111, 0xa200, 0xe42e, 0xa202, 0xe42e,
+    0x2807, 0xa2ff, 0xe41e, 0x10f0, 0xf7c8, 0xe161, 0x01f0, 0x8809,
+    0x0022, 0xe184, 0x111e, 0x2d11, 0x2b09, 0x1c06, 0xf078, 0xf067,
+    0x2807, 0x3d11, 0xa2fe, 0x3d09, 0xf05e, 0x8111, 0x8111, 0xa200,
+    0xe42e, 0xa202, 0xe42e, 0x3c08, 0xe161, 0x01f0, 0x8809, 0x0022,
+    0xe184, 0x1133, 0x2d11, 0x2b09, 0x1808, 0xf056, 0xf043, 0x8111,
+    0xa200, 0x3d09, 0x8111, 0x8111, 0xe42e, 0x2816, 0x184e, 0xf112,
+    0x884e, 0x0022, 0xe161, 0x0102, 0xe184, 0x1147, 0x2911, 0xf06a,
+    0x2909, 0xe412, 0x186b, 0xa200, 0x3d11, 0xe082, 0xa006, 0xe092,
+    0x2816, 0xb62c, 0x3c4e, 0x2813, 0xa104, 0xe428, 0xe41e, 0x12fb,
+    0xe42e, 0x2813, 0xa102, 0xf034, 0xf0fa, 0xf2be, 0x7414, 0x3ce3,
+    0x2832, 0xe016, 0x4422, 0xe418, 0x086d, 0xe42d, 0x34e4, 0x3ce5,
+    0xe41e, 0x123c, 0xf20e, 0xa200, 0x34e3, 0x3ce4, 0x34e5, 0x3ce6,
+    0x2815, 0xf0f8, 0xe41e, 0x086d, 0xe42d, 0x34e3, 0x3ce4, 0x2822,
+    0xf08a, 0x2832, 0xf068, 0xe41e, 0x086d, 0xe42d, 0x34e5, 0x3ce6,
+    0xe41e, 0x1278, 0xf08e, 0x34e3, 0x3ce4, 0x34e5, 0x3ce6, 0xf03e,
+    0xe41e, 0x12bb, 0x2832, 0x2a33, 0xf0b9, 0xf078, 0x20c9, 0x4cca,
+    0x22cb, 0x4ecc, 0xe066, 0xf06e, 0x20c9, 0x4cca, 0xf03e, 0x20cb,
+    0x4ccc, 0x34c7, 0x3cc8, 0xe42e, 0x281e, 0xf04a, 0x2813, 0xa104,
+    0xf0b8, 0x28c1, 0x2a60, 0xae1f, 0xe056, 0x3c01, 0xe41e, 0x1872,
+    0xe41e, 0x1338, 0xe42e, 0x28a5, 0x4cd3, 0x2a5e, 0xe017, 0xe052,
+    0xe418, 0x12fb, 0x28d8, 0xae02, 0xe000, 0x0578, 0xe092, 0x20c7,
+    0x4cc8, 0x3511, 0x3d11, 0x28d8, 0xe000, 0x059a, 0xe092, 0x28c1,
+    0x2a60, 0xae1f, 0xe056, 0x3d11, 0x28d8, 0xa002, 0x3cd8, 0xa200,
+    0x3c0c, 0xe41e, 0x1891, 0xf098, 0xe41e, 0x1300, 0x280c, 0xa180,
+    0xf052, 0xa082, 0x3c0c, 0xf76e, 0xe42e, 0xe41e, 0x1865, 0xe42e,
+    0x28c1, 0xe424, 0xe000, 0x06e0, 0xe092, 0x20aa, 0x4cab, 0x8450,
+    0x8251, 0xe019, 0xe41e, 0x11e2, 0xe049, 0xa141, 0xf027, 0xa240,
+    0x3d01, 0xe42e, 0x3e0a, 0xa201, 0xf032, 0xe012, 0xa203, 0x3e0e,
+    0x3c0b, 0xaf20, 0xc70f, 0x7c0a, 0x3c0c, 0xaf20, 0xae20, 0x4c0b,
+    0xc70f, 0x7c0a, 0x3c0d, 0x200c, 0x4c0d, 0x2a0e, 0xe42b, 0xe012,
+    0xe42e, 0xe41e, 0x0f5b, 0xf04a, 0xe41e, 0x12fb, 0xf0be, 0x287f,
+    0xf04a, 0xe41e, 0x12fb, 0xf06e, 0x28dc, 0xf04a, 0xa102, 0x3cdc,
+    0xf29e, 0x28db, 0xf27a, 0x28da, 0xe000, 0x05ab, 0xe092, 0x28da,
+    0xa002, 0x3cda, 0xa124, 0xf028, 0x3cda, 0x28db, 0xa102, 0x3cdb,
+    0x287f, 0xf0ba, 0x28db, 0xf05a, 0x2901, 0xe41e, 0x187b, 0xf6ae,
+    0x281e, 0xf03a, 0x28de, 0x3cdc, 0x2901, 0xe049, 0xe009, 0x8000,
+    0xf08b, 0xe0c1, 0x006d, 0xa903, 0xe0c3, 0x006d, 0xe008, 0x7fff,
+    0xe42e, 0xe41e, 0x0f5b, 0xf078, 0x286c, 0xf058, 0x287d, 0xf03a,
+    0xa2fc, 0xe42e, 0xa2fe, 0xe42e, 0xa202, 0x5814, 0xaf02, 0x3c06,
+    0x28a5, 0x2ad7, 0xf078, 0xf099, 0x20e6, 0x4ce7, 0x22e8, 0x4ee9,
+    0xf07e, 0xa200, 0xa201, 0xf04e, 0xa200, 0x22ea, 0x4eeb, 0x3400,
+    0x3c01, 0x3602, 0x3e03, 0x2ee3, 0x1202, 0x1e03, 0xf071, 0xe013,
+    0x1e06, 0xf085, 0x0c06, 0x0c06, 0xf05e, 0x1e06, 0xf037, 0x1c06,
+    0x1c06, 0x3404, 0x3c05, 0x0ce3, 0x34c9, 0x3cca, 0x00e4, 0x0ce5,
+    0x34cb, 0x3ccc, 0x28a3, 0xf0ca, 0x20c9, 0x4cca, 0x34ea, 0x3ceb,
+    0x2004, 0x4c05, 0x34e6, 0x3ce7, 0x2ce3, 0x34e8, 0x3ce9, 0xe42e,
+    0xe41e, 0x12cc, 0x28eb, 0xf30a, 0x2000, 0x4c01, 0x0c31, 0xf2c6,
+    0x2aa3, 0xe017, 0xe046, 0xa102, 0xf274, 0xe188, 0x000f, 0x7ceb,
+    0x3402, 0x3c03, 0xe41e, 0x12e6, 0x28eb, 0xa102, 0xcc44, 0xe161,
+    0x0250, 0xa200, 0xe184, 0x1295, 0x0111, 0x0d11, 0xae02, 0x3404,
+    0xe008, 0xffff, 0xaf02, 0x3c05, 0x8403, 0x8204, 0xe018, 0xae1e,
+    0x8205, 0xe01c, 0xe161, 0x0250, 0x8802, 0x0022, 0xe184, 0x12a9,
+    0x0111, 0x0d11, 0xf02e, 0xa200, 0x2aa3, 0xf039, 0x00e7, 0x0ce8,
+    0x00e3, 0x0ce4, 0x34c9, 0x3cca, 0x00e9, 0x0cea, 0x00e5, 0x0ce6,
+    0x34cb, 0x3ccc, 0xe42e, 0xe41e, 0x12cc, 0x28a5, 0xe016, 0xf08a,
+    0x2000, 0x4c01, 0x0c31, 0xae02, 0x2aa3, 0xe017, 0xe046, 0x34c9,
+    0x3cca, 0x34cb, 0x3ccc, 0xe42e, 0x28d7, 0xf05a, 0xa200, 0x34e1,
+    0x3ce2, 0x3ce0, 0x28a5, 0xe016, 0xf09a, 0x20e1, 0x4ce2, 0x2ee0,
+    0x1e31, 0xf047, 0xa203, 0x5a11, 0xe042, 0x3400, 0x3c01, 0x2831,
+    0x3ce0, 0x2000, 0x4c01, 0x34e1, 0x3ce2, 0xe42e, 0xe0c0, 0x0041,
+    0x22f0, 0x4ef1, 0xe042, 0xe005, 0x029e, 0xae11, 0xe042, 0xca29,
+    0xf7f9, 0xce20, 0xd111, 0x0250, 0xd112, 0x0200, 0xd113, 0x0003,
+    0xca28, 0xf7f8, 0xe42e, 0x28d8, 0xe426, 0xe41e, 0x1300, 0xf7ce,
+    0x28d8, 0xe426, 0xe161, 0x0578, 0xe162, 0x0578, 0x2111, 0x4d11,
+    0xa201, 0x3e00, 0xa203, 0x28d8, 0xa104, 0xf0e4, 0xcc44, 0xe184,
+    0x131a, 0x2112, 0x4d0a, 0x1111, 0x1d11, 0xf056, 0xe082, 0xa104,
+    0xe094, 0x3e00, 0xa003, 0xe084, 0xa004, 0xe092, 0x2800, 0xe000,
+    0x059a, 0xe098, 0xa002, 0xe096, 0x2904, 0x3c01, 0xe41e, 0x1872,
+    0x28d8, 0x1800, 0xa104, 0xf0a4, 0xcc44, 0xe184, 0x1334, 0x2911,
+    0x3d12, 0x2911, 0x3d12, 0x2913, 0x3d14, 0x28d8, 0xa102, 0x3cd8,
+    0x28d9, 0xe000, 0x05ab, 0xe092, 0x2801, 0x3d01, 0x28d9, 0xa002,
+    0x3cd9, 0xa124, 0xf028, 0x3cd9, 0x28db, 0xa002, 0x3cdb, 0xe42e,
+    0xa200, 0x3c68, 0x28d4, 0xa102, 0xcc44, 0xe184, 0x1364, 0xe0c0,
+    0x0054, 0x5c68, 0xa802, 0xf0b8, 0x2868, 0xe049, 0xe001, 0x0518,
+    0xe09f, 0x2b07, 0xa809, 0xe419, 0x187b, 0xf05e, 0x2868, 0xa209,
+    0xe41e, 0x188a, 0x2a68, 0xa003, 0x3e68, 0xe42e, 0xe004, 0x0518,
+    0xe09e, 0xe004, 0x0054, 0xe09c, 0x28d4, 0xa102, 0xcc44, 0xa200,
+    0x3c68, 0xe184, 0x137a, 0x2b17, 0xaf05, 0xa803, 0x5a68, 0xe056,
+    0x2a68, 0xa003, 0x3e68, 0x9f06, 0xe42e, 0xe161, 0x05e0, 0xa200,
+    0x3d11, 0x3c02, 0xd022, 0x013f, 0xe184, 0x138a, 0xe41e, 0x1472,
+    0x2802, 0xa002, 0x3c02, 0xa200, 0x3c94, 0x3c90, 0x3c91, 0xe42e,
+    0xba4e, 0xba40, 0xba40, 0xba40, 0xba40, 0xba46, 0xba4e, 0xbc3e,
+    0xf10d, 0x3c00, 0x1810, 0xf038, 0xa2fe, 0x3c10, 0x2800, 0xe000,
+    0x0100, 0x2a5e, 0xf02b, 0xa040, 0xe41e, 0x13f8, 0xa202, 0xe42e,
+    0xe16a, 0xa200, 0xe42e, 0xa204, 0x3c94, 0x2810, 0xe000, 0x0100,
+    0x2a5e, 0xf02b, 0xa040, 0xe41e, 0x1444, 0xe42a, 0xe41e, 0x0ca0,
+    0xf05a, 0xe41e, 0x1135, 0xa202, 0xe42e, 0xa2fe, 0x3c10, 0xa200,
+    0xe42e, 0xe41e, 0x0853, 0xf0fd, 0x3c01, 0xe002, 0x00ff, 0xf0b0,
+    0x2801, 0x1820, 0xf038, 0xa2fe, 0x3c20, 0x2801, 0xe41e, 0x13f8,
+    0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0xa202, 0x3c94, 0x2820,
+    0xe41e, 0x1444, 0xe42a, 0xe41e, 0x0db1, 0x3c66, 0xa200, 0xe41e,
+    0x0722, 0xa201, 0x3e94, 0x2866, 0xf03a, 0xa202, 0xe42e, 0xa2fe,
+    0x3c20, 0xa200, 0xe42e, 0x2863, 0xa102, 0xf06a, 0x2092, 0x4c93,
+    0xe41e, 0x149e, 0xe470, 0x2080, 0x4c81, 0xe41e, 0x14ad, 0xe470,
+    0x3c02, 0xe41e, 0x1474, 0xa200, 0x3c03, 0xe161, 0x05e0, 0x2901,
+    0xa203, 0x3f11, 0xf10a, 0x28a7, 0x1901, 0xf0d0, 0x28a7, 0xe002,
+    0x0200, 0xf092, 0x8111, 0x2111, 0x4d11, 0x3404, 0x3c05, 0xa202,
+    0x3c03, 0xf08e, 0x2090, 0x4c91, 0x3404, 0x3c05, 0x8111, 0x3511,
+    0x3d11, 0xe41e, 0x1491, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0000,
+    0x28a7, 0xa00e, 0xaf06, 0xae02, 0xce24, 0xd113, 0x0012, 0xca28,
+    0xf7f8, 0x28a6, 0xf0a8, 0xe41e, 0x0606, 0x2004, 0x4c05, 0xe000,
+    0x0200, 0x3404, 0x3c05, 0xf66e, 0xe161, 0x05e1, 0x28a7, 0x3d01,
+    0x2a03, 0xf089, 0xa00e, 0xaf06, 0xae06, 0x0090, 0x0c91, 0x3490,
+    0x3c91, 0xe41e, 0x1472, 0xe42e, 0x3c02, 0xe41e, 0x1474, 0xe161,
+    0x05e0, 0x2911, 0xe42a, 0x8111, 0x2111, 0x4d11, 0x3404, 0x3c05,
+    0x2894, 0xa102, 0xf0ba, 0xe41e, 0x1491, 0xe41e, 0x149e, 0xa204,
+    0xe41e, 0x0722, 0xe004, 0x0090, 0xf0ae, 0xe41e, 0x1491, 0xe41e,
+    0x14ad, 0xa202, 0xe41e, 0x0722, 0xe004, 0x0080, 0xcc66, 0xcc6a,
+    0xcc6e, 0xa01e, 0xcc6c, 0xa200, 0xcc60, 0xcc68, 0xcc70, 0xe128,
+    0xa202, 0xe42e, 0xa204, 0xf02e, 0xa206, 0x3c0a, 0xe41e, 0x1484,
+    0xca29, 0xf7f9, 0xce20, 0xd111, 0x05e0, 0xd112, 0x0004, 0x880a,
+    0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0041, 0x22f0, 0x4ef1,
+    0xe042, 0xe005, 0x02a2, 0xae11, 0xe042, 0x2a02, 0xae07, 0xe042,
+    0xe42e, 0xe0c0, 0x0041, 0x22f0, 0x4ef1, 0xe042, 0xe005, 0x02af,
+    0xae11, 0xe042, 0x2204, 0x4e05, 0xe042, 0xe42e, 0xca29, 0xf7f9,
+    0xce20, 0xa080, 0x3492, 0x3c93, 0xd111, 0x0090, 0xd112, 0x0010,
+    0xd113, 0x0013, 0xca28, 0xf7f8, 0xe42e, 0xca29, 0xf7f9, 0xce20,
+    0xa080, 0x3480, 0x3c81, 0xd111, 0x0080, 0xd112, 0x0010, 0xd113,
+    0x0013, 0xca28, 0xf7f8, 0xe42e, 0xe41e, 0x14ce, 0x2816, 0xe42a,
+    0xa102, 0x3c00, 0x28a3, 0xe01a, 0x4417, 0xe418, 0x1627, 0xe41e,
+    0x163a, 0xe41e, 0x1672, 0xe41e, 0x16a5, 0xe42e, 0x285e, 0xe42a,
+    0x2a16, 0xae05, 0xe001, 0x0100, 0xe093, 0xa200, 0x3d11, 0xa2fc,
+    0x3d11, 0xa206, 0x3d11, 0x285f, 0x3d11, 0x2a16, 0xae03, 0xe001,
+    0x0140, 0xe09b, 0x2a16, 0xae05, 0xe001, 0x0160, 0xe09d, 0x2a16,
+    0xe001, 0x01a0, 0xe09f, 0x20c7, 0x4cc8, 0x3515, 0x3d15, 0x3516,
+    0x3d16, 0x3516, 0x3d16, 0xa200, 0x3d07, 0xe42e, 0xc418, 0xe161,
+    0x0102, 0xa201, 0x2816, 0xe426, 0xa102, 0xcc44, 0xe184, 0x1506,
+    0x2911, 0xf05a, 0x2909, 0xe41e, 0x186b, 0x3f11, 0x8131, 0xe42e,
+    0x28d3, 0xf11a, 0x20c9, 0x4cca, 0x10c7, 0x1cc8, 0x34c9, 0x3cca,
+    0x20cb, 0x4ccc, 0x10c7, 0x1cc8, 0x34cb, 0x3ccc, 0xa200, 0x34c7,
+    0x3cc8, 0x3c37, 0x2c31, 0x2aa5, 0x4ed3, 0xb612, 0x3cd5, 0x2816,
+    0xe42a, 0xa102, 0x3c00, 0x2831, 0x3c01, 0x2834, 0xe016, 0x44d2,
+    0xe418, 0x15bd, 0x28d2, 0xe41a, 0x15eb, 0x2834, 0xe408, 0x1581,
+    0xe41e, 0x1541, 0xe42e, 0xaf02, 0xae04, 0xe000, 0x0101, 0xe09e,
+    0x2907, 0xe42e, 0xaf02, 0xae04, 0xe000, 0x0103, 0xe09e, 0x2907,
+    0xe42e, 0xc420, 0xe161, 0x0102, 0x8800, 0x0022, 0xe184, 0x154a,
+    0x2901, 0xf03a, 0x8131, 0xe42e, 0xe082, 0xe002, 0x0102, 0xaf04,
+    0x3c0a, 0x283b, 0x3d09, 0x28d1, 0x3d09, 0x28d0, 0x3d31, 0x8109,
+    0x28c1, 0x3d11, 0xe082, 0xe000, 0x005c, 0xe094, 0xe002, 0x0160,
+    0xaf02, 0xe000, 0x0140, 0xe092, 0x20c7, 0x4cc8, 0x3511, 0x3d11,
+    0x2a3b, 0xa105, 0x2112, 0x4d0a, 0xf03b, 0x20c9, 0x4cca, 0x3512,
+    0x3d12, 0x2112, 0x4d0a, 0xf035, 0x20cb, 0x4ccc, 0x3512, 0x3d12,
+    0x280a, 0xe000, 0x01a0, 0xe092, 0xa206, 0x183b, 0xe01a, 0x3d01,
+    0xe42e, 0xe161, 0x0100, 0x8800, 0x0022, 0xe184, 0x158e, 0x2d11,
+    0x2b11, 0x1cd0, 0x1ad1, 0xf028, 0xf04b, 0x8111, 0x8111, 0xe42e,
+    0xa206, 0x3d01, 0xe082, 0xe000, 0x005e, 0xe094, 0xe002, 0x0160,
+    0xaf02, 0xe000, 0x0140, 0xe092, 0xe002, 0x0140, 0xaf02, 0x3c0a,
+    0x20c7, 0x4cc8, 0x2311, 0x4f09, 0xe066, 0x3511, 0x3d11, 0xf41e,
+    0xc420, 0xe161, 0x0102, 0x8800, 0x0022, 0xe184, 0x15b1, 0x2901,
+    0xf03a, 0x8131, 0xe42e, 0xa206, 0x3d09, 0xa202, 0x3d09, 0x2801,
+    0x3d31, 0x8109, 0xa2fe, 0x3d11, 0xe42e, 0xa200, 0xc420, 0xe161,
+    0x0102, 0x8800, 0x0022, 0xe184, 0x15c7, 0x2b31, 0xe01b, 0xe042,
+    0x1816, 0xe424, 0xa203, 0xae21, 0xe161, 0x0102, 0x8800, 0x0022,
+    0xe184, 0x15e4, 0x2909, 0xf10a, 0x2909, 0xf0d6, 0x2901, 0x1c01,
+    0xf026, 0x1c12, 0x0c01, 0xe046, 0xf062, 0xe042, 0xe049, 0xe082,
+    0xa004, 0xe094, 0x8111, 0x8111, 0x8131, 0xa200, 0x3d12, 0x2912,
+    0xe412, 0x186b, 0xe42e, 0xe161, 0x0100, 0xe162, 0x01f0, 0x8800,
+    0x0022, 0xe184, 0x1625, 0x2832, 0xf098, 0x2912, 0x3c02, 0x2912,
+    0x3c03, 0xe01a, 0xb670, 0x3c04, 0xf15e, 0x2912, 0xaf02, 0x3c02,
+    0x2912, 0x3c03, 0xe01a, 0x3c04, 0x8112, 0x290a, 0xe01a, 0xae02,
+    0x4c04, 0x3c04, 0xa802, 0xf068, 0x2912, 0xaf02, 0x3c02, 0x290a,
+    0x3c03, 0x2804, 0x8112, 0x8112, 0xf08a, 0x2802, 0x3d11, 0x2803,
+    0x3d11, 0x2804, 0x3d11, 0xf0ae, 0x8111, 0x8111, 0x2901, 0xa201,
+    0x3f11, 0xf04a, 0x2901, 0xe412, 0x186b, 0x8111, 0xe42e, 0x28a5,
+    0xe428, 0x2834, 0xe428, 0x2cd5, 0x3c01, 0x2801, 0xa002, 0xc70f,
+    0x7c12, 0xaf20, 0x3c01, 0x1c31, 0xe42a, 0xe41e, 0x15bd, 0xe41e,
+    0x15a8, 0xf74e, 0xe161, 0x0100, 0xe162, 0x01f0, 0x8800, 0x0022,
+    0x285e, 0xf03a, 0x8816, 0x0022, 0xe184, 0x1666, 0x2832, 0xf0c8,
+    0x2911, 0x3d12, 0x2911, 0x2b11, 0xa807, 0xb616, 0x3d12, 0xa200,
+    0x3d12, 0x3d12, 0xf14e, 0x2911, 0xae02, 0xa002, 0x1833, 0x3d12,
+    0x2911, 0x2b09, 0xa803, 0xb616, 0x3d0a, 0x2912, 0x8112, 0xaa02,
+    0x3d12, 0x2911, 0x2b11, 0xa805, 0xb616, 0x3d12, 0x8111, 0xe161,
+    0x0230, 0xe162, 0x01f0, 0xd022, 0x003f, 0xe184, 0x1670, 0x2912,
+    0x3d11, 0xe42e, 0x2832, 0xf148, 0xe41e, 0x1703, 0x2808, 0xe000,
+    0x0270, 0xe096, 0xe41e, 0x1744, 0x2808, 0x0809, 0x3cc0, 0xe000,
+    0x0270, 0xe096, 0xe41e, 0x1803, 0x08c0, 0x3cc0, 0xe42e, 0xe41e,
+    0x1703, 0xe163, 0x0270, 0x2808, 0xe41e, 0x180b, 0x3c08, 0xe000,
+    0x0270, 0xe096, 0xe41e, 0x1744, 0x2808, 0xe000, 0x0270, 0xe096,
+    0x2809, 0xe41e, 0x180b, 0x0808, 0x3cc0, 0xe000, 0x0270, 0xe096,
+    0xe41e, 0x1803, 0x08c0, 0x3cc0, 0xe42e, 0x2832, 0xf238, 0xe41e,
+    0x177e, 0x2808, 0xe000, 0x0290, 0xe096, 0xe41e, 0x1744, 0x2808,
+    0xe000, 0x02b0, 0xe096, 0xe41e, 0x1744, 0x2808, 0x0809, 0x3cc0,
+    0xe41e, 0x184e, 0x28c0, 0xe000, 0x0290, 0xe096, 0xe41e, 0x1803,
+    0x28c0, 0xe000, 0x02b0, 0xe096, 0xe41e, 0x1803, 0x08c0, 0x3cc0,
+    0xe42e, 0xe41e, 0x177e, 0xe163, 0x0290, 0x2808, 0xe41e, 0x180b,
+    0xe163, 0x02b0, 0x2808, 0xe41e, 0x180b, 0x3c08, 0x2808, 0xe000,
+    0x0290, 0xe096, 0xe41e, 0x1744, 0x2808, 0xe000, 0x0290, 0xe096,
+    0x2809, 0xe41e, 0x180b, 0x2808, 0xe000, 0x02b0, 0xe096, 0xe41e,
+    0x1744, 0x2808, 0xe000, 0x02b0, 0xe096, 0x2809, 0xe41e, 0x180b,
+    0x0808, 0x3cc0, 0xe41e, 0x184e, 0x28c0, 0xe000, 0x0290, 0xe096,
+    0xe41e, 0x1803, 0x28c0, 0xe000, 0x02b0, 0xe096, 0xe41e, 0x1803,
+    0x08c0, 0x3cc0, 0xe42e, 0xe161, 0x05e0, 0xa200, 0xc70f, 0x3d11,
+    0x2832, 0xb674, 0x3c05, 0xa200, 0x3c08, 0xc420, 0xe163, 0x0270,
+    0xa2fe, 0x3c06, 0xa203, 0xae21, 0xe013, 0xe161, 0x0102, 0xe162,
+    0x05e0, 0x8800, 0x0022, 0xe184, 0x1733, 0x2912, 0xf158, 0x2909,
+    0x1805, 0xf114, 0x2909, 0xf0e6, 0x2901, 0x1c31, 0xf026, 0x1c12,
+    0x0c31, 0xe046, 0xf076, 0xe042, 0xe049, 0xe084, 0xe002, 0x05e1,
+    0x3c06, 0x8111, 0x8111, 0x8131, 0x2806, 0xe424, 0xe000, 0x05e0,
+    0xe094, 0xa202, 0x3d02, 0x2806, 0xae02, 0x3d13, 0x2808, 0xa002,
+    0x3c08, 0x1816, 0xf4e8, 0xe42e, 0xe161, 0x05e0, 0xa200, 0xc70f,
+    0x3d11, 0x2832, 0xb674, 0x3c05, 0xa200, 0x3c09, 0xc420, 0xa2fe,
+    0x3c07, 0xa221, 0xe161, 0x0102, 0xe162, 0x05e0, 0x8800, 0x0022,
+    0xe184, 0x176d, 0x2912, 0xf128, 0x2909, 0x1805, 0xf0e4, 0x2909,
+    0xa002, 0xf0a8, 0x2901, 0xe046, 0xf072, 0xe042, 0xe049, 0xe084,
+    0xe002, 0x05e1, 0x3c07, 0x8111, 0x8111, 0x8131, 0x2807, 0xe424,
+    0xe000, 0x05e0, 0xe094, 0xa202, 0x3d02, 0x2807, 0xae02, 0x3d13,
+    0x2809, 0xa002, 0x3c09, 0x1816, 0xf538, 0xe42e, 0xe161, 0x05e0,
+    0xa200, 0xc70f, 0x3d11, 0x2832, 0xb674, 0x3c05, 0xa200, 0x3c0a,
+    0xc420, 0xe163, 0x0290, 0xe164, 0x02b0, 0xa2fe, 0x3c06, 0x3c07,
+    0xe161, 0x0102, 0xe162, 0x05e0, 0xe165, 0x0140, 0x8800, 0x0022,
+    0xe184, 0x17c9, 0x2912, 0xf2c8, 0x2909, 0x1805, 0xf284, 0x2909,
+    0xf256, 0x2115, 0x4d0d, 0x10c7, 0x1cc8, 0xf110, 0x2806, 0xf064,
+    0x2115, 0x4d0d, 0x100c, 0x1c0d, 0xf196, 0x2115, 0x4d0d, 0x340c,
+    0x3c0d, 0xe084, 0xe002, 0x05e1, 0x3c06, 0xf10e, 0x2807, 0xf064,
+    0x2115, 0x4d0d, 0x100e, 0x1c0f, 0xf092, 0x2115, 0x4d0d, 0x340e,
+    0x3c0f, 0xe084, 0xe002, 0x05e1, 0x3c07, 0x8111, 0x8111, 0x8131,
+    0x8115, 0x8115, 0x2806, 0xf094, 0xe000, 0x05e0, 0xe094, 0xa202,
+    0x3d02, 0x2806, 0xae02, 0x3d13, 0x2807, 0xf094, 0xe000, 0x05e0,
+    0xe094, 0xa202, 0x3d02, 0x2807, 0xae02, 0x3d14, 0x280a, 0xa002,
+    0x3c0a, 0x1816, 0xe408, 0x178d, 0xe086, 0xe002, 0x0290, 0x3c0c,
+    0xe088, 0xe002, 0x02b0, 0x3c0d, 0xf09a, 0xa102, 0xcc44, 0xe164,
+    0x02b0, 0xe184, 0x17f4, 0x2914, 0x3d13, 0x280c, 0xf09a, 0xa102,
+    0xcc44, 0xe163, 0x0290, 0xe184, 0x17fe, 0x2913, 0x3d14, 0x280c,
+    0x080d, 0x3c08, 0xe42e, 0x285e, 0xe42a, 0x2816, 0xae02, 0x0833,
+    0x3d03, 0xa202, 0xe42e, 0xe42a, 0xa102, 0x3c0c, 0xe086, 0xe098,
+    0xe161, 0x05e0, 0x880c, 0x0022, 0xe184, 0x1826, 0x2903, 0xae02,
+    0xe000, 0x0102, 0xe094, 0x2902, 0xa802, 0xf03a, 0x2903, 0x3d11,
+    0x2902, 0xa804, 0xf04a, 0x2903, 0xa002, 0x3d11, 0x8113, 0xe082,
+    0xe002, 0x05e0, 0xe42a, 0xa102, 0x3c0c, 0x3c0d, 0x2833, 0x3c0e,
+    0xe161, 0x05e0, 0x880c, 0x0022, 0xe184, 0x183b, 0x2901, 0xf044,
+    0xa802, 0x180e, 0xf06a, 0x8111, 0x280e, 0xe016, 0x3c0e, 0xf71e,
+    0x2901, 0x3d14, 0xa2fe, 0x3d01, 0x280e, 0xe016, 0x3c0e, 0x280d,
+    0xa102, 0x3c0d, 0xf662, 0x280c, 0xa002, 0xe42e, 0x28c0, 0xa102,
+    0xe426, 0xcc44, 0xe163, 0x0290, 0xe164, 0x02b0, 0xe184, 0x185b,
+    0x2913, 0x1914, 0xe428, 0xe190, 0xe163, 0x0291, 0xe164, 0x02b0,
+    0x290b, 0x3d14, 0x2903, 0x3d14, 0xe42e, 0xe161, 0x0518, 0xa200,
+    0xc71f, 0x3d11, 0xe42e, 0xe000, 0x0518, 0xe09e, 0x2907, 0xa80c,
+    0x3d07, 0xe42e, 0xe008, 0x7fff, 0xe000, 0x0518, 0xe09e, 0x2907,
+    0xa80a, 0x3d07, 0xe42e, 0x3cd6, 0xe000, 0x0518, 0xe09e, 0x2907,
+    0xa806, 0x3d07, 0x28d6, 0xa002, 0x3cd6, 0x18d4, 0xe428, 0xa200,
+    0x3cd6, 0xe42e, 0xe000, 0x0518, 0xe09e, 0x2907, 0xe056, 0x3d07,
+    0xe42e, 0xe161, 0x0518, 0x28d4, 0xa102, 0xcc44, 0xa200, 0xe184,
+    0x189c, 0x2b11, 0xa807, 0xe01b, 0xe042, 0x18df, 0xa102, 0xe01a,
+    0xe42e, 0xe161, 0x0518, 0x28d4, 0xa102, 0xe049, 0xcc44, 0xe184,
+    0x18aa, 0x2911, 0xb5f1, 0xa202, 0xb60e, 0xe42e, 0x28d6, 0x3c00,
+    0x2800, 0xe000, 0x0518, 0xe092, 0x2901, 0xf12a, 0x2800, 0xa002,
+    0x3c00, 0x18d4, 0xf038, 0xa200, 0x3c00, 0x2800, 0x18d6, 0xf718,
+    0xa200, 0x3cd6, 0xa2fe, 0x3cc1, 0xe0c2, 0x0077, 0xe42e, 0x2a60,
+    0xae03, 0xe0c0, 0x006d, 0xe056, 0xe0c2, 0x006d, 0xa20e, 0x3d01,
+    0x2800, 0x3cc1, 0xe0c2, 0x0077, 0xe42e, 0xe0c0, 0x0060, 0xe049,
+    0xa861, 0xe42b, 0xe0c1, 0x0044, 0xae1b, 0xe0c3, 0x0102, 0x28ad,
+    0xa8fe, 0x1851, 0xf092, 0xe41e, 0x18f7, 0xe41e, 0x190e, 0x28ad,
+    0xa8fe, 0x1851, 0xf798, 0xa204, 0xae1c, 0xe0c2, 0x014d, 0xa202,
+    0xe0c2, 0x014a, 0xe190, 0xe0c1, 0x014b, 0xf7e9, 0xe42e, 0xa205,
+    0x28ad, 0xb615, 0xa903, 0x3e0d, 0x2848, 0xe000, 0x06e0, 0xe092,
+    0x2901, 0xae04, 0x4c0d, 0xae1c, 0x4cad, 0xe0c2, 0x014d, 0xa202,
+    0xe0c2, 0x014a, 0xe0c1, 0x014b, 0xf7e9, 0xe42e, 0x28ad, 0xe000,
+    0x0080, 0x3cad, 0xaf0e, 0x1850, 0xe428, 0x28ad, 0xa8fe, 0xa002,
+    0x3cad, 0xe42e, 0xe41e, 0x19eb, 0xe41e, 0x1a89, 0xe41e, 0x199a,
+    0xe41e, 0x1c78, 0x285c, 0x4ca3, 0xe01a, 0x3c5c, 0xa200, 0x3c52,
+    0x3c4a, 0xa202, 0x3c88, 0xe41e, 0x1b79, 0x2852, 0xf048, 0xcba2,
+    0xe40a, 0x1995, 0x183c, 0xe402, 0x1995, 0xe41e, 0x05bb, 0x28a4,
+    0xf7da, 0xa102, 0xf17a, 0xa108, 0xf794, 0xf14a, 0xa10a, 0xe40a,
+    0x1995, 0xa102, 0xe40a, 0x1995, 0xa102, 0xf38a, 0xa104, 0xf6ea,
+    0xa102, 0xa10a, 0xe40a, 0x1951, 0xa002, 0xf682, 0xf3be, 0x283c,
+    0x3c4a, 0x28a3, 0xe01a, 0x2a84, 0xe01b, 0xe05a, 0xf338, 0x28a5,
+    0x1885, 0xf308, 0xe41e, 0x064f, 0xe41e, 0x1b0e, 0xf57a, 0x2888,
+    0xf06a, 0x283c, 0x3c0d, 0xe41e, 0x1bb1, 0xf24e, 0xe41e, 0x0670,
+    0x28a3, 0x3c84, 0x28a5, 0x3c85, 0xe41e, 0x092f, 0xf47a, 0xa201,
+    0x3e88, 0x284a, 0x3c0d, 0x1852, 0xf414, 0xe410, 0x1bb1, 0x284a,
+    0x183c, 0xe402, 0x1995, 0xe40e, 0x192b, 0xba0e, 0xe002, 0x00ff,
+    0xf058, 0xba4e, 0xe41e, 0x0623, 0xf798, 0xe41e, 0x089c, 0xe40e,
+    0x1935, 0x2852, 0x183c, 0xe402, 0x1991, 0x283c, 0x3c0d, 0xe41e,
+    0x1bb1, 0x2884, 0x3ca3, 0x2885, 0x3ca5, 0xe41e, 0x1d93, 0xcbcc,
+    0xf7f8, 0xe42e, 0x281f, 0xae02, 0x4c2e, 0xae0a, 0x2a2d, 0xa83f,
+    0xe056, 0xae0a, 0x2a29, 0xa83f, 0xe056, 0xae02, 0x4c1a, 0xae02,
+    0x4c21, 0xae02, 0x4c3a, 0xcf80, 0x28a3, 0xe01a, 0xae02, 0x4c18,
+    0xae02, 0x4c1a, 0xae02, 0x4c3a, 0xcfc2, 0x2850, 0xa102, 0xae02,
+    0x4c2b, 0xae02, 0x4c32, 0xae02, 0x4c33, 0xae02, 0x4c3a, 0xcf00,
+    0xd1d3, 0x000b, 0xd185, 0x0001, 0x20c3, 0x4cc4, 0xcfc6, 0xd1e5,
+    0x0001, 0xc420, 0xe161, 0x0101, 0xa200, 0xd022, 0x000f, 0xe184,
+    0x19d3, 0x2b31, 0xae02, 0xb42a, 0xcfe8, 0x20c7, 0x4cc8, 0xcfea,
+    0x20c9, 0x4cca, 0xcfec, 0x20cb, 0x4ccc, 0xcfee, 0xe004, 0x0060,
+    0xce30, 0xe161, 0x0160, 0xd022, 0x001f, 0xe184, 0x19e9, 0x2111,
+    0x4d11, 0xce32, 0xe42e, 0xa200, 0xe161, 0x00b6, 0xc707, 0x3d11,
+    0x28b0, 0x4cb1, 0xf028, 0xe42e, 0xe161, 0x00b6, 0xa20e, 0x3c00,
+    0x28b0, 0xf39a, 0x28b2, 0x5c00, 0xa802, 0xf108, 0x2a00, 0xa10f,
+    0xf049, 0xa202, 0x3d11, 0xf17e, 0x2a00, 0xa109, 0xf049, 0xa204,
+    0x3d11, 0xf11e, 0xa20a, 0x3d11, 0xf0ee, 0x28b4, 0x5c00, 0xa802,
+    0xf08a, 0x2800, 0xa10a, 0xa205, 0xf024, 0xa203, 0x3f11, 0xf03e,
+    0xa206, 0x3d11, 0x2800, 0xa102, 0x3c00, 0xa102, 0xf5c8, 0x28b2,
+    0xe00c, 0x00ff, 0x2ab4, 0xe056, 0x5c00, 0xa802, 0xf06a, 0xa203,
+    0x2800, 0xb655, 0x3f11, 0xf03e, 0xa206, 0x3d11, 0x2800, 0xa102,
+    0x3c00, 0xf6ea, 0xe161, 0x00b6, 0xa20e, 0x3c00, 0x28b1, 0xe42a,
+    0x28b3, 0x5c00, 0xa802, 0xf188, 0x2800, 0xa10e, 0xf088, 0x2ab0,
+    0xf03b, 0x8111, 0xf1e9, 0xa202, 0x3d11, 0xf1be, 0x2a00, 0xa109,
+    0xf089, 0x2ab0, 0xf03b, 0x8111, 0xf149, 0xa204, 0x3d11, 0xf11e,
+    0xa20a, 0x3d11, 0xf0ee, 0x28b5, 0x5c00, 0xa802, 0xf08a, 0x2800,
+    0xa10a, 0xa205, 0xf024, 0xa203, 0x3f11, 0xf03e, 0xa208, 0x3d11,
+    0x2800, 0xa102, 0x3c00, 0xa102, 0xf548, 0x28b3, 0x5c00, 0x4cb0,
+    0xa802, 0xf068, 0xa203, 0x2800, 0xb655, 0x3f11, 0xf16e, 0x28b5,
+    0xe00c, 0x00ff, 0x2ab3, 0xe052, 0x5c00, 0xa802, 0xf0c8, 0x28b3,
+    0x5c00, 0xa802, 0xf06a, 0xa203, 0x2800, 0xb655, 0x3f11, 0xf05e,
+    0x8111, 0xf03e, 0xa208, 0x3d11, 0x2800, 0xa102, 0x3c00, 0xf5ea,
+    0xe42e, 0xa202, 0xe0c2, 0x013c, 0xa200, 0x3c00, 0x3c01, 0xe161,
+    0x00b6, 0xe162, 0x04c8, 0x2911, 0xa104, 0xf066, 0xa106, 0xe40a,
+    0x1ad8, 0xa004, 0xf112, 0xa004, 0xae06, 0x3c04, 0x2800, 0xa10c,
+    0xf064, 0x2804, 0xae04, 0xe000, 0x0018, 0x3c04, 0xe004, 0x0450,
+    0x0804, 0x3c04, 0xf2ee, 0xa201, 0x3e02, 0xa211, 0x3e03, 0xf04a,
+    0xe005, 0x00e0, 0x3e02, 0x2800, 0x2a00, 0xae09, 0xa10c, 0xf05a,
+    0xa102, 0xf058, 0xe005, 0x00a0, 0xa240, 0x3c03, 0x0a02, 0x3e02,
+    0xe0c0, 0x0041, 0x22f0, 0x4ef1, 0xe042, 0xe005, 0x02ac, 0xae11,
+    0xe042, 0x0802, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x05e0, 0x2803,
+    0xce24, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe004, 0x05e0, 0x3c04,
+    0x2800, 0xa10c, 0xa20f, 0xf024, 0xa23f, 0xcc45, 0x2804, 0xe096,
+    0xe184, 0x1af2, 0x2912, 0x0801, 0xe0c2, 0x013e, 0x2b03, 0xaf11,
+    0xe0c3, 0x013f, 0x2912, 0x0801, 0xe0c2, 0x013e, 0x2b13, 0xe009,
+    0x00ff, 0xe0c3, 0x013f, 0xe162, 0x04c8, 0x2a01, 0xe001, 0x0010,
+    0x3e01, 0x2800, 0xa002, 0x3c00, 0xa10c, 0xe404, 0x1a93, 0xe162,
+    0x04d8, 0xe40a, 0x1a93, 0xe001, 0x0030, 0x3e01, 0xa104, 0xe408,
+    0x1a93, 0xe16a, 0xa200, 0xe0c2, 0x013c, 0xe42e, 0xa200, 0x3c88,
+    0xe41e, 0x0853, 0xe40d, 0x1b75, 0x2a3a, 0xe419, 0x0b09, 0x183c,
+    0xe402, 0x1b75, 0xbc12, 0xe40d, 0x1b75, 0xa10a, 0xb4a8, 0xa104,
+    0xe400, 0x1b75, 0xbdfe, 0xe40d, 0x1b75, 0x1820, 0xf03a, 0xa202,
+    0x3c88, 0x7411, 0x1831, 0xf03a, 0xa202, 0x3c88, 0x2818, 0xf0d8,
+    0xba40, 0x1832, 0xf03a, 0xa202, 0x3c88, 0x2832, 0xf06a, 0xba40,
+    0x1833, 0xf03a, 0xa202, 0x3c88, 0x28a5, 0xf09a, 0xe41e, 0x0853,
+    0xe40d, 0x1b75, 0x1c3d, 0xf03a, 0xa202, 0x3c88, 0x2813, 0xa102,
+    0xf034, 0xf14a, 0xf29e, 0x7414, 0x1ce3, 0xf03a, 0xa202, 0x3c88,
+    0x2832, 0xe016, 0x4422, 0xf20a, 0xe41e, 0x086d, 0xf1fd, 0x10e4,
+    0x1ce5, 0xf03a, 0xa202, 0x3c88, 0xf17e, 0x2815, 0xf158, 0xe41e,
+    0x086d, 0xf14d, 0x10e3, 0x1ce4, 0xf03a, 0xa202, 0x3c88, 0x2832,
+    0xe016, 0x4422, 0xf09a, 0xe41e, 0x086d, 0xf08d, 0x10e5, 0x1ce6,
+    0xf03a, 0xa202, 0x3c88, 0xa202, 0xe42e, 0xe16a, 0xa200, 0x3c86,
+    0xe42e, 0xa200, 0x3ca2, 0x28a6, 0xf098, 0xa202, 0x3ca0, 0x3ca2,
+    0x3ca1, 0xd036, 0x00ff, 0xd037, 0x0080, 0xe16a, 0x284a, 0x3c52,
+    0xe41e, 0x1bc4, 0x2821, 0xf138, 0x2852, 0x183c, 0xf0d2, 0xe41e,
+    0x1c07, 0xf1ed, 0x283a, 0xe418, 0x1c07, 0xf1ad, 0xcb86, 0xa102,
+    0xf740, 0xc894, 0xf728, 0xe41e, 0x089c, 0xe42e, 0xe41e, 0x1bf3,
+    0x2852, 0x183c, 0xf0a2, 0xe41e, 0x1c07, 0xf0ad, 0x283a, 0xe418,
+    0x1c07, 0xf06d, 0xbb60, 0xf75a, 0xe41e, 0x089e, 0xe42e, 0xe16a,
+    0xe42e, 0x28a5, 0xe016, 0x3c30, 0xe41e, 0x1bc4, 0x2852, 0x180d,
+    0xf0b2, 0xe41e, 0x1c44, 0x283a, 0xe418, 0x1c44, 0x284c, 0xa002,
+    0x083a, 0x3c4c, 0xf74e, 0xe42e, 0x2829, 0x182d, 0xe01a, 0xae04,
+    0x4c43, 0xae0a, 0x4c44, 0xae0a, 0x4c45, 0xcf30, 0x2841, 0xae0a,
+    0x4c40, 0xae04, 0x4c30, 0xcf82, 0xd1c3, 0x0000, 0x2842, 0xcf96,
+    0x2841, 0xae08, 0x4c40, 0xae02, 0x4ccf, 0xae02, 0x4cce, 0xae02,
+    0x4ccd, 0xae02, 0x4c3e, 0xae04, 0x4c30, 0xcfc4, 0x8846, 0x01fa,
+    0x20c5, 0x4cc6, 0xcfc8, 0xd188, 0x0001, 0x2830, 0xa104, 0xe428,
+    0xd1e5, 0x0002, 0xe42e, 0xc868, 0xa80e, 0x3c97, 0x7497, 0xe004,
+    0x01fe, 0xcc86, 0xba50, 0xcc88, 0x2830, 0xe01a, 0x083f, 0xae0c,
+    0x4c42, 0xcc82, 0xd040, 0x0003, 0xc884, 0xf7f8, 0xe42e, 0x2852,
+    0xe0c2, 0x003f, 0xd185, 0x0002, 0xd1d0, 0x003f, 0xe190, 0xe180,
+    0x28a2, 0xe418, 0x0784, 0xe181, 0xcba0, 0xa810, 0xcba3, 0xf239,
+    0xf7c8, 0xe41e, 0x1d41, 0xcbe0, 0xf7f8, 0x2856, 0xe41a, 0x1d6a,
+    0xcba0, 0xcba3, 0xf189, 0xf7d8, 0xd186, 0x0001, 0xd185, 0x0004,
+    0xe41e, 0x1d81, 0xe41e, 0x190e, 0xcb06, 0x3c52, 0xcb8a, 0xaf04,
+    0x4421, 0xe42a, 0xe004, 0x01fe, 0xcc86, 0xba50, 0xcc88, 0xd040,
+    0x0001, 0xe42e, 0xd1d0, 0x0000, 0xd1d1, 0x0000, 0xcb1c, 0xf7f8,
+    0xcbe0, 0xf7f8, 0xe16b, 0xe42e, 0x2852, 0xe0c2, 0x003f, 0xd185,
+    0x0002, 0xd186, 0x0000, 0xd1c2, 0x0001, 0xd1c5, 0x0000, 0xd1c4,
+    0x0000, 0xd1d0, 0x000e, 0xcba0, 0xf7f8, 0x284b, 0xf098, 0xd1c2,
+    0x0000, 0xd1c5, 0x0003, 0xd1c4, 0x0003, 0xd1c8, 0x0000, 0xd1d0,
+    0x0020, 0xe41e, 0x1d41, 0xa200, 0xe0c2, 0x012a, 0xcbe0, 0xf7f8,
+    0x2856, 0xe41a, 0x1d6a, 0xcba0, 0xf7f8, 0xd186, 0x0001, 0xd185,
+    0x0004, 0xe41e, 0x1d81, 0xe41e, 0x190e, 0xcb06, 0x3c52, 0xe42e,
+    0xa200, 0xe0c2, 0x0100, 0xe0c2, 0x013d, 0xcc8e, 0xe004, 0x00ce,
+    0xe0c2, 0x017c, 0xa218, 0xe0c2, 0x017d, 0xe0c0, 0x0050, 0x3008,
+    0xaf02, 0x3009, 0xaf02, 0x300a, 0xaf02, 0x300b, 0xaf0a, 0x300c,
+    0xaf02, 0x300d, 0xaf02, 0x300e, 0xaf02, 0x300f, 0xaf06, 0xa802,
+    0xe005, 0x0ba6, 0xe09f, 0x3d17, 0x280c, 0x4408, 0x3c08, 0x280d,
+    0x4409, 0x3c09, 0x280e, 0x440a, 0x3c0a, 0x280f, 0x440b, 0x3c0b,
+    0xa200, 0xe0c2, 0x0168, 0x2a08, 0xf02b, 0xa904, 0x2a09, 0xf02b,
+    0xa912, 0x2a0a, 0xf02b, 0xa940, 0x2a0b, 0xf02b, 0xa980, 0xe005,
+    0x0ba6, 0xe09f, 0x2b17, 0xae05, 0xe056, 0xe0c2, 0x0169, 0xe0c1,
+    0x0041, 0xe004, 0x0010, 0xae10, 0xe042, 0x2a0c, 0xf06b, 0xe004,
+    0x05d3, 0xe09e, 0x2117, 0x4d17, 0xcf0e, 0xe0c1, 0x0041, 0xe004,
+    0x0050, 0xae10, 0xe042, 0x2a0d, 0xf06b, 0xe004, 0x05d5, 0xe09e,
+    0x2117, 0x4d17, 0xe0c2, 0x0103, 0xa202, 0xe0c2, 0x0210, 0xe0c1,
+    0x0041, 0xe004, 0x007c, 0xae10, 0xe042, 0x2a0e, 0xf06b, 0xe004,
+    0x05d7, 0xe09e, 0x2117, 0x4d17, 0xe0c2, 0x0211, 0xe0c1, 0x0041,
+    0xe004, 0x00bc, 0xae10, 0xe042, 0x2a0f, 0xf06b, 0xe004, 0x05d9,
+    0xe09e, 0x2117, 0x4d17, 0xe0c2, 0x0212, 0x2050, 0x4c51, 0xae08,
+    0xe0c2, 0x0101, 0xe0c2, 0x0283, 0xe0c2, 0x006f, 0xe0c2, 0x004f,
+    0x2a1f, 0x2058, 0x4c59, 0xf02b, 0xae02, 0xe0c2, 0x0078, 0x205a,
+    0x4c5b, 0xf02b, 0xae02, 0xe0c2, 0x0079, 0x281f, 0xe016, 0xae08,
+    0xe0c1, 0x0044, 0xa80f, 0xe056, 0xae1a, 0x4c67, 0xe0c2, 0x0102,
+    0x283a, 0xae02, 0x4c32, 0xae02, 0x4c33, 0xe0c2, 0x0104, 0xe0c1,
+    0x0065, 0xaf19, 0xa803, 0xae17, 0xe056, 0xe0c2, 0x0204, 0xa200,
+    0xe0c2, 0x0208, 0xe41e, 0x1da4, 0xe41e, 0x1dc8, 0xa202, 0xe0c2,
+    0x0106, 0x2a3a, 0xae07, 0xe167, 0x0ba7, 0x3f17, 0xe41e, 0x1e65,
+    0xe42e, 0xcb02, 0xaf02, 0xe0c2, 0x0113, 0xe0c2, 0x030d, 0xcb15,
+    0xae03, 0xe056, 0xe0c2, 0x022b, 0xcb94, 0xe0c2, 0x0115, 0xe41e,
+    0x1e40, 0xcba4, 0xe0c2, 0x012a, 0xcb8a, 0xe0c2, 0x0114, 0xa802,
+    0x3c56, 0xe42a, 0xcb14, 0xae0a, 0xcb19, 0xe056, 0xe0c2, 0x0120,
+    0xcb8c, 0xe0c2, 0x0121, 0xcb8e, 0xe0c2, 0x0122, 0xcb90, 0xe0c2,
+    0x0123, 0xe42e, 0xcbd0, 0xe0c2, 0x030c, 0xcbd2, 0xe0c2, 0x0309,
+    0xcbd8, 0xe0c2, 0x030a, 0xcbda, 0xe0c2, 0x030b, 0x2846, 0xe0c2,
+    0x0320, 0xe42a, 0x2847, 0xe0c2, 0x0321, 0xcbf6, 0xe0c2, 0x0322,
+    0xe42e, 0xe0c0, 0x0111, 0xf7e8, 0xa202, 0xe0c2, 0x0110, 0x28af,
+    0xaf08, 0x4cae, 0xe42a, 0x28ad, 0xa8fe, 0x1851, 0xe422, 0xa202,
+    0xe0c2, 0x014a, 0xe42e, 0xe0c0, 0x0111, 0xf7e8, 0xe0c0, 0x0065,
+    0xaf18, 0xa802, 0xf09a, 0x283c, 0x1852, 0xf068, 0xcba2, 0xf048,
+    0xe0c0, 0x0281, 0xf7ea, 0xe42e, 0xa202, 0xe0c2, 0x0302, 0x2816,
+    0xe42a, 0x2a5e, 0xb5f6, 0xcc44, 0xe160, 0x0004, 0xe161, 0x0103,
+    0xe163, 0x0380, 0xe184, 0x1dc3, 0x8531, 0xc786, 0xe018, 0xb608,
+    0xe000, 0x0620, 0xe094, 0x2112, 0x4d12, 0x9f13, 0x2112, 0x4d12,
+    0x9f13, 0x2112, 0x4d12, 0x9f13, 0xa200, 0xe0c2, 0x0302, 0xe42e,
+    0xa202, 0xae02, 0xa902, 0xe0c2, 0x0312, 0xa802, 0xe42a, 0xe162,
+    0x01b0, 0x2912, 0xaf02, 0x3c0a, 0x2912, 0xaf02, 0x3c0b, 0x2830,
+    0xa104, 0xf068, 0xe162, 0x01d0, 0x2912, 0xaf02, 0x3c0b, 0x280a,
+    0x180b, 0xf0d8, 0xe162, 0x01b0, 0xd022, 0x001f, 0xe184, 0x1ded,
+    0x2912, 0xaf02, 0x3c0b, 0x180a, 0xf028, 0xe190, 0x280b, 0xae08,
+    0x4c0a, 0xe0c2, 0x0313, 0xe42e, 0xa200, 0x3caf, 0x3cae, 0x3cad,
+    0x2848, 0xe404, 0x1e64, 0xe0c0, 0x0060, 0xe049, 0xa861, 0xe40b,
+    0x1e64, 0xe049, 0xa83e, 0x3caf, 0xaf0b, 0x3eae, 0x2848, 0xae04,
+    0x0848, 0x0848, 0xe000, 0x0620, 0xe09e, 0x2117, 0x4d17, 0xe0c2,
+    0x0143, 0x2117, 0x4d17, 0xe0c2, 0x0144, 0x2117, 0x4d17, 0xe0c2,
+    0x0145, 0xa200, 0xe0c2, 0x0140, 0xe0c2, 0x0149, 0x2867, 0xe0c2,
+    0x0141, 0xe0c0, 0x0064, 0xe0c2, 0x014c, 0x2850, 0xa102, 0xae20,
+    0x4c51, 0xa102, 0xe0c2, 0x0142, 0x28ae, 0xae08, 0x2aaf, 0xa81f,
+    0xe056, 0xe0c2, 0x014e, 0xe0c0, 0x0061, 0xe0c2, 0x0146, 0xe0c0,
+    0x0062, 0xe0c2, 0x0147, 0xe0c0, 0x0063, 0xe0c2, 0x0148, 0xe42e,
+    0xcb94, 0xa87e, 0x22aa, 0x4eab, 0xe042, 0x34aa, 0x3cab, 0x28af,
+    0x4cae, 0xf1ba, 0x28ad, 0xa8fe, 0x1851, 0xf172, 0xa203, 0x28ad,
+    0xb615, 0x3e0d, 0xa203, 0x3e0e, 0x2848, 0xe000, 0x06e0, 0xe092,
+    0x2901, 0xae02, 0x4c0d, 0xae02, 0x4c0e, 0xae1c, 0x4cad, 0xe0c1,
+    0x014b, 0xf7e9, 0xe0c2, 0x014d, 0xe42e, 0xe0c0, 0x0065, 0xaf18,
+    0xa802, 0xe40a, 0x1ee7, 0xae0a, 0xe0c1, 0x0060, 0xaf0d, 0xa80f,
+    0xe056, 0xe0c1, 0x0044, 0xa811, 0xe056, 0xae0c, 0xe0c1, 0x0044,
+    0xa80f, 0xe056, 0xe167, 0x0ba7, 0x2f17, 0xe056, 0xe0c2, 0x0282,
+    0xe0c0, 0x006e, 0xe0c2, 0x0284, 0xaf20, 0xe0c1, 0x0282, 0xa809,
+    0xf04b, 0xe049, 0xae1f, 0xf06e, 0xe049, 0xa011, 0xaf09, 0xae07,
+    0xae21, 0xe056, 0xe0c2, 0x028c, 0xe167, 0x0ba8, 0x2d17, 0x4917,
+    0xe0c2, 0x0285, 0xe167, 0x0baa, 0x2d17, 0x4917, 0xe0c2, 0x0286,
+    0xe41e, 0x1ee8, 0xe0c0, 0x004a, 0xe0c2, 0x0289, 0xe0c0, 0x004b,
+    0xe0c2, 0x028a, 0xe0c0, 0x0055, 0xe0c2, 0x028b, 0xe0c1, 0x0041,
+    0xe004, 0x0100, 0xae10, 0xe042, 0xe167, 0x0ba6, 0x2b17, 0xf05b,
+    0xe167, 0x0ba0, 0x2d17, 0x4917, 0xe0c2, 0x0287, 0xe0c1, 0x0041,
+    0xe004, 0x0118, 0xae10, 0xe042, 0xe167, 0x0ba6, 0x2b17, 0xf05b,
+    0xe167, 0x0ba2, 0x2d17, 0x4917, 0xe0c2, 0x0288, 0xe0c1, 0x0041,
+    0xe004, 0x0120, 0xae10, 0xe042, 0xe167, 0x0ba6, 0x2b17, 0xf05b,
+    0xe167, 0x0ba4, 0x2d17, 0x4917, 0xe0c2, 0x028d, 0xe0c0, 0x0065,
+    0xaf18, 0xa802, 0xe0c2, 0x0280, 0xa210, 0xe0c2, 0x0168, 0xe42e,
+    0xe167, 0x0bac, 0xe165, 0x028e, 0xe166, 0x02c0, 0xd022, 0x0008,
+    0xe184, 0x1efb, 0x2d17, 0x9f16, 0x9e85, 0xf7fb, 0x2517, 0x4d17,
+    0x9f16, 0x9e85, 0xf7fb, 0xe190, 0xe166, 0x02d2, 0xd022, 0x0008,
+    0xe184, 0x1f07, 0x2517, 0x4d17, 0x9f16, 0x9e85, 0xf7fb, 0xe190,
+    0xe166, 0x02db, 0xd022, 0x0008, 0xe184, 0x1f13, 0x2517, 0x4d17,
+    0x9f16, 0x9e85, 0xf7fb, 0xe190, 0xe166, 0x02e4, 0xd022, 0x0008,
+    0xe184, 0x1f1e, 0x2d17, 0x9f16, 0x9e85, 0xf7fb, 0xe190, 0xe42e,
+    0x287d, 0xe016, 0x4c62, 0xe01a, 0xe428, 0x28c1, 0xf064, 0xe41e,
+    0x1872, 0x28c1, 0xe41e, 0x187b, 0xa200, 0xe42e, 0xa202, 0x3c60,
+    0xa204, 0xe41e, 0x0480, 0xa200, 0x3c60, 0xe42e, 0x3c05, 0x2860,
+    0x1805, 0xe42a, 0x2805, 0xf03a, 0x2820, 0x3c61, 0xa204, 0xe41e,
+    0x0480, 0x2805, 0x3c60, 0xe0c0, 0x0041, 0xe005, 0x0280, 0xae11,
+    0xe042, 0xe0c1, 0x005a, 0x0a60, 0xae19, 0xe042, 0x3400, 0x3c01,
+    0xe004, 0x0100, 0x3c02, 0xe004, 0x01b0, 0x3c04, 0xe41e, 0x1f93,
+    0xe004, 0x00d5, 0xe41e, 0x1f90, 0xe004, 0x00d7, 0xe41e, 0x1f90,
+    0xe004, 0x004e, 0xe41e, 0x1f90, 0xe004, 0x0035, 0x3c02, 0xe004,
+    0x003a, 0x3c04, 0xe41e, 0x1f93, 0xe004, 0x00c1, 0xe41e, 0x1f90,
+    0x28c1, 0x3cbf, 0xe004, 0x00be, 0xe41e, 0x1f90, 0xe004, 0x00e0,
+    0x3c02, 0xe004, 0x00ec, 0x3c04, 0xe41e, 0x1f93, 0xa2fe, 0x3c20,
+    0x3c10, 0x2805, 0xe428, 0x3c5e, 0x2861, 0x3c20, 0xe41e, 0x13d5,
+    0xe42e, 0xe41e, 0x1fe4, 0xae02, 0x2600, 0x4e01, 0xe042, 0xe42e,
+    0x3c02, 0xa002, 0x3c04, 0xca28, 0xf7f8, 0x2802, 0xa806, 0xf20a,
+    0xd111, 0x05e0, 0x2802, 0xe41e, 0x1f89, 0xce20, 0xd112, 0x0004,
+    0xd113, 0x0003, 0xca28, 0xf7f8, 0xe004, 0x05e0, 0x2a02, 0xa807,
+    0xe042, 0xe09c, 0x2802, 0xe09e, 0x2916, 0x3d17, 0xe08e, 0xa806,
+    0xf05a, 0xe08e, 0x1804, 0xf02a, 0xf78e, 0xe08e, 0x3c02, 0x2802,
+    0xce22, 0xe41e, 0x1f89, 0xce20, 0x2804, 0x1802, 0xe41e, 0x1fe4,
+    0xf08a, 0xce24, 0x0802, 0x3c02, 0xd113, 0x0003, 0xca28, 0xf7f8,
+    0x2804, 0x1802, 0xf19a, 0xd111, 0x05e0, 0x2802, 0xe41e, 0x1f89,
+    0xce20, 0xd112, 0x0004, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe166,
+    0x05e0, 0x2802, 0xe09e, 0x2804, 0x1802, 0xa102, 0xcc44, 0xe184,
+    0x1fe2, 0x2916, 0x3d17, 0xe42e, 0xaf04, 0xae04, 0xe42e, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
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+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+    0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010,
+    0x060d, 0x0d14, 0x1414, 0x1c1c, 0x1c1c, 0x2020, 0x2025, 0x252a,
+    0x0a0e, 0x0e14, 0x1414, 0x1818, 0x1818, 0x1b1b, 0x1b1e, 0x1e22,
+    0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010,
+    0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010,
+    0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010,
+    0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010,
+    0x060a, 0x0a0d, 0x0b0d, 0x1010, 0x1010, 0x1212, 0x1212, 0x1217,
+    0x1717, 0x1717, 0x1719, 0x1919, 0x1919, 0x1919, 0x1b1b, 0x1b1b,
+    0x1b1b, 0x1b1b, 0x1d1d, 0x1d1d, 0x1d1d, 0x1d1f, 0x1f1f, 0x1f1f,
+    0x1f21, 0x2121, 0x2121, 0x2424, 0x2424, 0x2626, 0x2628, 0x282a,
+    0x090d, 0x0d0f, 0x0d0f, 0x1111, 0x1111, 0x1313, 0x1313, 0x1315,
+    0x1515, 0x1515, 0x1516, 0x1616, 0x1616, 0x1616, 0x1818, 0x1818,
+    0x1818, 0x1818, 0x1919, 0x1919, 0x1919, 0x191b, 0x1b1b, 0x1b1b,
+    0x1b1c, 0x1c1c, 0x1c1c, 0x1e1e, 0x1e1e, 0x2020, 0x2021, 0x2123,
+    0x0000, 0x0001, 0x0004, 0x0008, 0x0005, 0x0002, 0x0003, 0x0006,
+    0x0009, 0x000c, 0x000d, 0x000a, 0x0007, 0x000b, 0x000e, 0x000f,
+    0x0000, 0x0001, 0x0008, 0x0010, 0x0009, 0x0002, 0x0003, 0x000a,
+    0x0011, 0x0018, 0x0020, 0x0019, 0x0012, 0x000b, 0x0004, 0x0005,
+    0x000c, 0x0013, 0x001a, 0x0021, 0x0028, 0x0030, 0x0029, 0x0022,
+    0x001b, 0x0014, 0x000d, 0x0006, 0x0007, 0x000e, 0x0015, 0x001c,
+    0x0023, 0x002a, 0x0031, 0x0038, 0x0039, 0x0032, 0x002b, 0x0024,
+    0x001d, 0x0016, 0x000f, 0x0017, 0x001e, 0x0025, 0x002c, 0x0033,
+    0x003a, 0x003b, 0x0034, 0x002d, 0x0026, 0x001f, 0x0027, 0x002e,
+    0x0035, 0x003c, 0x003d, 0x0036, 0x002f, 0x0037, 0x003e, 0x003f,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+    0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+};
+
+#endif //__CODA7L_FW_H__
+
diff --git a/board/rda/common/include/coda7l_regs.h b/board/rda/common/include/coda7l_regs.h
new file mode 100644
index 0000000000..4b2d1b36fa
--- /dev/null
+++ b/board/rda/common/include/coda7l_regs.h
@@ -0,0 +1,587 @@
+//--=========================================================================--
+//  This file is a part of VPU Reference API project
+//-----------------------------------------------------------------------------
+//
+//       This confidential and proprietary software may be used only
+//     as authorized by a licensing agreement from Chips&Media Inc.
+//     In the event of publication, the following notice is applicable:
+//
+//            (C) COPYRIGHT 2006 - 2011  CHIPS&MEDIA INC.
+//                      ALL RIGHTS RESERVED
+//
+//       The entire notice above must be reproduced on all authorized
+//       copies.
+//
+//--=========================================================================--
+//#include "../config.h"
+
+#ifndef __CODA7L_REGS_H__
+#define __CODA7L_REGS_H__
+
+//------------------------------------------------------------------------------
+// REGISTER BASE
+//------------------------------------------------------------------------------
+#define BIT_BASE            0x0000
+#define GDMA_BASE          	0x1000
+#define MBC_BASE            0x0400
+#define ME_BASE				0x0600
+#define DBK_BASE            0x0800
+#define MC_BASE				0x0C00
+#define DMAC_BASE			0x2000
+
+#define BW_BASE             0x03000000
+//------------------------------------------------------------------------------
+// HARDWARE REGISTER
+//------------------------------------------------------------------------------
+#define BIT_CODE_RUN                (BIT_BASE + 0x000)
+#define BIT_CODE_DOWN               (BIT_BASE + 0x004)
+#define BIT_INT_REQ                 (BIT_BASE + 0x008)
+#define BIT_INT_CLEAR               (BIT_BASE + 0x00C)
+#define BIT_INT_STS					(BIT_BASE + 0x010)
+#define BIT_CODE_RESET				(BIT_BASE + 0x014)
+#define BIT_CUR_PC                  (BIT_BASE + 0x018)
+#define BIT_SW_RESET				(BIT_BASE + 0x024)
+#define BIT_SW_RESET_STATUS			(BIT_BASE + 0x034)
+
+//------------------------------------------------------------------------------
+// GLOBAL REGISTER
+//------------------------------------------------------------------------------
+#define BIT_CODE_BUF_ADDR           (BIT_BASE + 0x100)
+#define BIT_WORK_BUF_ADDR           (BIT_BASE + 0x104)
+#define BIT_PARA_BUF_ADDR           (BIT_BASE + 0x108)
+#define BIT_BIT_STREAM_CTRL         (BIT_BASE + 0x10C)
+#define BIT_FRAME_MEM_CTRL          (BIT_BASE + 0x110)
+#define	BIT_BIT_STREAM_PARAM		(BIT_BASE + 0x114)
+
+#define BIT_RD_PTR					(BIT_BASE + 0x120)
+#define BIT_WR_PTR					(BIT_BASE + 0x124)
+
+
+#define BIT_AXI_SRAM_USE            (BIT_BASE + 0x140)
+#define BIT_BYTE_POS_FRAME_START    (BIT_BASE + 0x144)
+#define BIT_BYTE_POS_FRAME_END		(BIT_BASE + 0x148)
+#define BIT_FRAME_CYCLE             (BIT_BASE + 0x14C)
+
+#define	BIT_FRM_DIS_FLG				(BIT_BASE + 0x150)
+
+#define BIT_BUSY_FLAG               (BIT_BASE + 0x160)
+#define BIT_RUN_COMMAND             (BIT_BASE + 0x164)
+#define BIT_RUN_INDEX               (BIT_BASE + 0x168)
+#define BIT_RUN_COD_STD             (BIT_BASE + 0x16C)
+#define BIT_INT_ENABLE              (BIT_BASE + 0x170)
+#define BIT_INT_REASON              (BIT_BASE + 0x174)
+#define BIT_RUN_AUX_STD             (BIT_BASE + 0x178)
+
+// MSG REGISTER ADDRESS changed
+#ifdef CNM_FPGA_PLATFORM
+#define BIT_MSG_0                   	(BIT_BASE + 0x1F4)
+#define BIT_MSG_1                   	(BIT_BASE + 0x1F8)
+#define BIT_MSG_2                   	(BIT_BASE + 0x1FC)
+#define BIT_MSG_3                   	(BIT_BASE + 0x1FC)	// only 3 MSG registers in coda7l
+
+#define MBC_BUSY                	(MBC_BASE + 0x044)
+#define MC_BUSY                 	(MC_BASE + 0x004)
+#endif
+
+
+#define CMD_SET_FRAME_AXI_SCLY_ADDR			 (BIT_BASE + 0x1A4)
+#define CMD_SET_FRAME_AXI_SCLC_ADDR			 (BIT_BASE + 0x1A8)
+#define CMD_SET_FRAME_AXI_SCL_PACKED_SYNC_ADDR (BIT_BASE + 0x1AC)
+
+//------------------------------------------------------------------------------
+// [ENC SEQ INIT] COMMAND
+//------------------------------------------------------------------------------
+#define CMD_ENC_SEQ_BB_START        (BIT_BASE + 0x180)
+#define CMD_ENC_SEQ_BB_SIZE         (BIT_BASE + 0x184)
+#define CMD_ENC_SEQ_OPTION          (BIT_BASE + 0x188)          // HecEnable,ConstIntraQp, FMO, QPREP, AUD, SLICE, MB BIT
+#define CMD_ENC_SEQ_COD_STD         (BIT_BASE + 0x18C)
+#define CMD_ENC_SEQ_SRC_SIZE        (BIT_BASE + 0x190)
+#define CMD_ENC_SEQ_SRC_F_RATE      (BIT_BASE + 0x194)
+#define CMD_ENC_SEQ_MP4_PARA        (BIT_BASE + 0x198)
+#define CMD_ENC_SEQ_263_PARA        (BIT_BASE + 0x19C)
+#define CMD_ENC_SEQ_264_PARA        (BIT_BASE + 0x1A0)
+#define CMD_ENC_SEQ_SLICE_MODE      (BIT_BASE + 0x1A4)
+#define CMD_ENC_SEQ_GOP_NUM         (BIT_BASE + 0x1A8)
+#define CMD_ENC_SEQ_RC_PARA         (BIT_BASE + 0x1AC)
+#define CMD_ENC_SEQ_RC_BUF_SIZE     (BIT_BASE + 0x1B0)
+#define CMD_ENC_SEQ_INTRA_REFRESH   (BIT_BASE + 0x1B4)
+#define CMD_ENC_SEARCH_BASE			(BIT_BASE + 0x1B8)
+#define CMD_ENC_SEARCH_SIZE			(BIT_BASE + 0x1BC)
+#define CMD_ENC_SEQ_INTRA_QP		(BIT_BASE + 0x1C4)
+#define CMD_ENC_SEQ_RC_QP_MAX			(BIT_BASE + 0x1C8)
+#define CMD_ENC_SEQ_RC_GAMMA			(BIT_BASE + 0x1CC)
+#define CMD_ENC_SEQ_RC_INTERVAL_MODE	(BIT_BASE + 0x1D0)		// mbInterval[32:2], rcIntervalMode[1:0]
+#define CMD_ENC_SEQ_INTRA_WEIGHT		(BIT_BASE + 0x1D4)
+#define CMD_ENC_SEQ_ME_OPTION			(BIT_BASE + 0x1D8)
+#define CMD_ENC_SEQ_RC_PARA2			(BIT_BASE + 0x1DC)
+#define CMD_ENC_SEQ_QP_RANGE_SET		(BIT_BASE + 0x1E0)
+#define CMD_ENC_SEQ_RC_MAX_INTRA_SIZE   (BIT_BASE + 0x1F0)
+
+#define CMD_ENC_SEQ_FIRST_MBA           (BIT_BASE + 0x1E4)
+#define CMD_ENC_SEQ_HEIGHT_IN_MAP_UNITS (BIT_BASE + 0x1E8)
+#define CMD_ENC_SEQ_OVERLAP_CLIP_SIZE   (BIT_BASE + 0x1EC)
+
+//------------------------------------------------------------------------------
+// [ENC SEQ END] COMMAND
+//------------------------------------------------------------------------------
+#define RET_ENC_SEQ_END_SUCCESS         (BIT_BASE + 0x1C0)
+
+//------------------------------------------------------------------------------
+// [DEC][MINI-PIPPEN] COMMAND
+//------------------------------------------------------------------------------
+#define	CMD_DEC_PIC_SCL_TGT_SIZE		(BIT_BASE + 0x1B8)
+#define	CMD_DEC_PIC_SCL_ADDR_Y  		(BIT_BASE + 0x128)
+#define	CMD_DEC_PIC_SCL_ADDR_CB 		(BIT_BASE + 0x12C)
+#define	CMD_DEC_PIC_SCL_ADDR_CR 		(BIT_BASE + 0x154)
+
+//------------------------------------------------------------------------------
+// [ENC PIC RUN] COMMAND
+//------------------------------------------------------------------------------
+
+#define CMD_ENC_PIC_SRC_INDEX       (BIT_BASE + 0x180)
+#define CMD_ENC_PIC_SRC_STRIDE      (BIT_BASE + 0x184)
+#define CMD_ENC_PIC_SRC_ADDR_Y		(BIT_BASE + 0x180)
+#define CMD_ENC_PIC_SRC_ADDR_CB		(BIT_BASE + 0x184)
+#define CMD_ENC_PIC_SRC_ADDR_CR		(BIT_BASE + 0x188)
+#define CMD_ENC_PIC_QS              (BIT_BASE + 0x18C)
+#define CMD_ENC_PIC_ROT_MODE        (BIT_BASE + 0x190)
+#define CMD_ENC_PIC_OPTION          (BIT_BASE + 0x194)
+#define CMD_ENC_PIC_BB_START        (BIT_BASE + 0x198)
+#define CMD_ENC_PIC_BB_SIZE        	(BIT_BASE + 0x19C)
+#define CMD_ENC_PIC_PARA_BASE_ADDR	(BIT_BASE + 0x1A0)
+#define CMD_ENC_PIC_SUB_FRAME_SYNC  (BIT_BASE + 0x1A4)
+
+
+
+#define RET_ENC_PIC_FRAME_NUM       (BIT_BASE + 0x1C0)
+#define RET_ENC_PIC_TYPE            (BIT_BASE + 0x1C4)
+#define RET_ENC_PIC_FRAME_IDX       (BIT_BASE + 0x1C8)
+#define RET_ENC_PIC_SLICE_NUM       (BIT_BASE + 0x1CC)
+#define RET_ENC_PIC_FLAG			(BIT_BASE + 0x1D0)
+#define RET_ENC_PIC_SUCCESS         (BIT_BASE + 0x1D8)
+
+//------------------------------------------------------------------------------
+// [ENC ROI INIT] COMMAND
+//------------------------------------------------------------------------------
+#define CMD_ENC_ROI_MODE            (BIT_BASE + 0x180)      // [1]: RoiType, [0]: RoiEn
+#define CMD_ENC_ROI_NUM             (BIT_BASE + 0x184)      // [3:0] RoiNum
+
+#define CMD_ENC_ROI_POS_0           (BIT_BASE + 0x188)      // [31:24]: MbyEnd, [23:16]: MbyStart, [15:8]: MbxEnd, [7:0]: MbxStart
+#define CMD_ENC_ROI_QP_0            (BIT_BASE + 0x18C)      // [05:04]: RoiQp
+#define CMD_ENC_ROI_POS_1           (BIT_BASE + 0x190)
+#define CMD_ENC_ROI_QP_1            (BIT_BASE + 0x194)
+#define CMD_ENC_ROI_POS_2           (BIT_BASE + 0x198)
+#define CMD_ENC_ROI_QP_2            (BIT_BASE + 0x19C)
+#define CMD_ENC_ROI_POS_3           (BIT_BASE + 0x1A0)
+#define CMD_ENC_ROI_QP_3            (BIT_BASE + 0x1A4)
+#define CMD_ENC_ROI_POS_4           (BIT_BASE + 0x1A8)
+#define CMD_ENC_ROI_QP_4            (BIT_BASE + 0x1AC)
+#define CMD_ENC_ROI_POS_5           (BIT_BASE + 0x1B0)
+#define CMD_ENC_ROI_QP_5            (BIT_BASE + 0x1B4)
+#define CMD_ENC_ROI_POS_6           (BIT_BASE + 0x1B8)
+#define CMD_ENC_ROI_QP_6            (BIT_BASE + 0x1BC)
+#define CMD_ENC_ROI_POS_7           (BIT_BASE + 0x1C0)
+#define CMD_ENC_ROI_QP_7            (BIT_BASE + 0x1C4)
+#define CMD_ENC_ROI_POS_8           (BIT_BASE + 0x1C8)
+#define CMD_ENC_ROI_QP_8            (BIT_BASE + 0x1CC)
+#define CMD_ENC_ROI_POS_9           (BIT_BASE + 0x1D0)
+#define CMD_ENC_ROI_QP_9            (BIT_BASE + 0x1D4)
+
+#define RET_ENC_ROI_SUCCESS         (BIT_BASE + 0x1D8)
+
+
+//------------------------------------------------------------------------------
+// [ENC SET FRAME BUF] COMMAND
+//------------------------------------------------------------------------------
+#define CMD_SET_FRAME_SUBSAMP_A    (BIT_BASE + 0x188)
+#define CMD_SET_FRAME_SUBSAMP_B    (BIT_BASE + 0x18C)
+
+#define CMD_SET_FRAME_DP_BUF_BASE  (BIT_BASE + 0x1B0)
+#define CMD_SET_FRAME_DP_BUF_SIZE  (BIT_BASE + 0x1B4)
+
+//------------------------------------------------------------------------------
+// [ENC HEADER] COMMAND
+//------------------------------------------------------------------------------
+#define CMD_ENC_HEADER_CODE         (BIT_BASE + 0x180)
+#define CMD_ENC_HEADER_BB_START     (BIT_BASE + 0x184)
+#define CMD_ENC_HEADER_BB_SIZE      (BIT_BASE + 0x188)
+#define CMD_ENC_HEADER_FRAME_CROP_H (BIT_BASE + 0x18C)
+#define CMD_ENC_HEADER_FRAME_CROP_V (BIT_BASE + 0x190)
+
+
+#define RET_ENC_HEADER_SUCCESS      (BIT_BASE + 0x1C0)
+
+//------------------------------------------------------------------------------
+// [ENC_PARA_SET] COMMAND
+//------------------------------------------------------------------------------
+#define CMD_ENC_PARA_SET_TYPE       (BIT_BASE + 0x180)
+#define RET_ENC_PARA_SET_SIZE       (BIT_BASE + 0x1c0)
+#define RET_ENC_PARA_SET_SUCCESS    (BIT_BASE + 0x1C4)
+
+//------------------------------------------------------------------------------
+// [ENC PARA CHANGE] COMMAND :
+//------------------------------------------------------------------------------
+#define CMD_ENC_PARAM_CHANGE_ENABLE		(BIT_BASE + 0x180)		// FrameRateEn[3], BitRateEn[2], IntraQpEn[1], GopEn[0]
+#define CMD_ENC_PARAM_CHANGE_GOP_NUM	(BIT_BASE + 0x184)
+#define CMD_ENC_PARAM_CHANGE_INTRA_QP	(BIT_BASE + 0x188)
+#define CMD_ENC_PARAM_CHANGE_BITRATE    (BIT_BASE + 0x18C)
+#define CMD_ENC_PARAM_CHANGE_F_RATE		(BIT_BASE + 0x190)
+#define	CMD_ENC_PARAM_CHANGE_INTRA_REFRESH	(BIT_BASE + 0x194)		// update param
+#define CMD_ENC_PARAM_CHANGE_SLICE_MODE		(BIT_BASE + 0x198)		// update param
+#define CMD_ENC_PARAM_CHANGE_HEC_MODE		(BIT_BASE + 0x19C)		// update param
+#define CMD_ENC_SEQ_PARA_CABAC_MODE		(BIT_BASE + 0x1A0)		// entropyCodingMode==2
+#define CMD_ENC_SEQ_PARA_PPS_ID  		(BIT_BASE + 0x1B4)		// entropyCodingMode==2
+
+#define RET_ENC_SEQ_PARA_CHANGE_SECCESS	(BIT_BASE + 0x1C0)
+
+//------------------------------------------------------------------------------
+// [DEC SEQ INIT] COMMAND
+//------------------------------------------------------------------------------
+#define CMD_DEC_SEQ_BB_START        (BIT_BASE + 0x180)
+#define CMD_DEC_SEQ_BB_SIZE         (BIT_BASE + 0x184)
+#define CMD_DEC_SEQ_OPTION          (BIT_BASE + 0x188)
+#define CMD_DEC_SEQ_SRC_SIZE        (BIT_BASE + 0x18C)
+#define CMD_DEC_SEQ_START_BYTE		(BIT_BASE + 0x190)
+
+#define CMD_DEC_SEQ_PS_BB_START     (BIT_BASE + 0x194)
+#define CMD_DEC_SEQ_PS_BB_SIZE      (BIT_BASE + 0x198)
+
+#define CMD_DEC_SEQ_MP4_ASP_CLASS   (BIT_BASE + 0x19C)
+#define CMD_DEC_SEQ_VC1_STREAM_FMT  (BIT_BASE + 0x19C)
+#define CMD_DEC_SEQ_X264_MV_EN		(BIT_BASE + 0x19C)
+
+// For MPEG2 only
+#define CMD_DEC_SEQ_USER_DATA_OPTION		(BIT_BASE + 0x194)
+#define CMD_DEC_SEQ_USER_DATA_BASE_ADDR		(BIT_BASE + 0x1AC)
+#define CMD_DEC_SEQ_USER_DATA_BUF_SIZE		(BIT_BASE + 0x1B0)
+
+
+#define CMD_DEC_SEQ_INIT_ESCAPE		(BIT_BASE + 0x114)
+
+
+#define RET_DEC_SEQ_BIT_RATE		(BIT_BASE + 0x1B4)
+#define RET_DEC_SEQ_EXT_INFO        (BIT_BASE + 0x1B8)
+#define RET_DEC_SEQ_SUCCESS         (BIT_BASE + 0x1C0)
+#define RET_DEC_SEQ_SRC_SIZE        (BIT_BASE + 0x1C4)
+#define RET_DEC_SEQ_ASPECT			(BIT_BASE + 0x1B0)
+#define RET_DEC_SEQ_FRAME_NEED      (BIT_BASE + 0x1CC)
+#define RET_DEC_SEQ_FRAME_DELAY     (BIT_BASE + 0x1D0)
+#define RET_DEC_SEQ_INFO            (BIT_BASE + 0x1D4)
+#define RET_DEC_SEQ_VP8_SCALE_INFO  (BIT_BASE + 0x1D4)
+
+#define RET_DEC_SEQ_CROP_LEFT_RIGHT (BIT_BASE + 0x1D8)
+#define RET_DEC_SEQ_CROP_TOP_BOTTOM (BIT_BASE + 0x1DC)
+#define RET_DEC_SEQ_SEQ_ERR_REASON  (BIT_BASE + 0x1E0)
+
+#define RET_DEC_SEQ_SRC_F_RATE		(BIT_BASE + 0x1C8)
+#define RET_DEC_SEQ_FRATE_NR        (BIT_BASE + 0x1E8)
+#define RET_DEC_SEQ_FRATE_DR        (BIT_BASE + 0x1E4)
+
+#define RET_DEC_SEQ_HEADER_REPORT   (BIT_BASE + 0x1EC)
+#define RET_DEC_SEQ_VUI_INFO		(BIT_BASE + 0x18C)
+#define RET_DEC_SEQ_VUI_PIC_STRUCT		(BIT_BASE + 0x1A8)
+
+#define RET_DEC_SEQ_MP2_BAR_LEFT_RIGHT (BIT_BASE + 0x1D8)
+#define RET_DEC_SEQ_MP2_BAR_TOP_BOTTOM (BIT_BASE + 0x1DC)
+
+
+
+
+//------------------------------------------------------------------------------
+// [DEC SEQ END] COMMAND
+//------------------------------------------------------------------------------
+#define RET_DEC_SEQ_END_SUCCESS     (BIT_BASE + 0x1C0)
+
+//------------------------------------------------------------------------------
+// [DEC PIC RUN] COMMAND
+//----------------------------------------------------
+#define CMD_DEC_PIC_ROT_MODE        (BIT_BASE + 0x180)
+#define CMD_DEC_BUF_FLUSH_TYPE		(BIT_BASE + 0x180)
+#define CMD_DEC_BUF_FLUSH_RDPTR		(BIT_BASE + 0x184)
+#define CMD_DEC_PIC_ROT_INDEX       (BIT_BASE + 0x184)
+#define CMD_DEC_PIC_ROT_ADDR_Y      (BIT_BASE + 0x184)
+#define CMD_DEC_PIC_ROT_ADDR_CB     (BIT_BASE + 0x188)
+#define CMD_DEC_PIC_ROT_ADDR_CR     (BIT_BASE + 0x18C)
+#define CMD_DEC_PIC_ROT_STRIDE      (BIT_BASE + 0x190)
+
+
+#define CMD_DEC_PIC_OPTION			(BIT_BASE + 0x194)
+
+#define	CMD_DEC_PIC_CHUNK_SIZE		(BIT_BASE + 0x19C)
+#define	CMD_DEC_PIC_BB_START		(BIT_BASE + 0x1A0)
+#define CMD_DEC_PIC_START_BYTE		(BIT_BASE + 0x1A4)
+
+#define CMD_DEC_PIC_USER_DATA_BASE_ADDR		(BIT_BASE + 0x1AC)
+#define CMD_DEC_PIC_USER_DATA_BUF_SIZE		(BIT_BASE + 0x1B0)
+#define CMD_DEC_PIC_THO_PIC_PARA            (BIT_BASE + 0x198)
+#define CMD_DEC_PIC_THO_QMAT_ADDR           (BIT_BASE + 0x1A0)
+#define CMD_DEC_PIC_THO_MB_PARA_ADDR        (BIT_BASE + 0x1A4)
+#define RET_DEC_PIC_VUI_PIC_STRUCT			(BIT_BASE + 0x1A8)
+#define RET_DEC_PIC_AVC_FPA_SEI0			(BIT_BASE + 0x19C)
+#define RET_DEC_PIC_AVC_FPA_SEI1			(BIT_BASE + 0x1A0)
+#define RET_DEC_PIC_AVC_FPA_SEI2			(BIT_BASE + 0x1A4)
+#define RET_DEC_PIC_HRD_INFO				(BIT_BASE + 0x1B8)
+#define RET_DEC_PIC_SIZE					(BIT_BASE + 0x1BC)
+#define RET_DEC_PIC_FRAME_NUM				(BIT_BASE + 0x1C0)
+#define RET_DEC_PIC_FRAME_IDX				(BIT_BASE + 0x1C4)
+#define RET_DEC_PIC_DISPLAY_IDX				(BIT_BASE + 0x1C4)
+#define RET_DEC_PIC_ERR_MB					(BIT_BASE + 0x1C8)
+#define RET_DEC_PIC_TYPE					(BIT_BASE + 0x1CC)
+#define RET_DEC_PIC_POST					(BIT_BASE + 0x1D0) // for VC1
+#define RET_DEC_PIC_MVC_REPORT				(BIT_BASE + 0x1D0) // for MVC
+#define RET_DEC_PIC_OPTION					(BIT_BASE + 0x1D4)
+#define RET_DEC_PIC_SUCCESS					(BIT_BASE + 0x1D8)
+#define RET_DEC_PIC_CUR_IDX					(BIT_BASE + 0x1DC)
+#define RET_DEC_PIC_DECODED_IDX				(BIT_BASE + 0x1DC)
+#define	RET_DEC_PIC_CROP_LEFT_RIGHT			(BIT_BASE + 0x1E0) // for AVC, MPEG-2
+#define RET_DEC_PIC_CROP_TOP_BOTTOM			(BIT_BASE + 0x1E4) // for AVC, MPEG-2
+#define	RET_DEC_PIC_MODULO_TIME_BASE		(BIT_BASE + 0x1E0) // for MP4
+#define RET_DEC_PIC_VOP_TIME_INCREMENT		(BIT_BASE + 0x1E4) // for MP4
+#define RET_DEC_PIC_RV_TR					(BIT_BASE + 0x1E8)
+#define RET_DEC_PIC_VP8_PIC_REPORT			(BIT_BASE + 0x1E8)
+#define RET_DEC_PIC_ATSC_USER_DATA_INFO		(BIT_BASE + 0x1E8) // H.264, MEPEG2
+#define RET_DEC_PIC_VUI_INFO				(BIT_BASE + 0x1EC)
+#define RET_DEC_PIC_ASPECT					(BIT_BASE + 0x1F0)
+#define RET_DEC_PIC_VP8_SCALE_INFO			(BIT_BASE + 0x1F0)
+#define RET_DEC_PIC_FRATE_NR				(BIT_BASE + 0x1F4)
+#define RET_DEC_PIC_FRATE_DR				(BIT_BASE + 0x1F8)
+#define RET_DEC_PIC_POC_TOP					(BIT_BASE + 0x1AC)
+#define RET_DEC_PIC_POC_BOT					(BIT_BASE + 0x1B0)
+#define RET_DEC_PIC_POC  					(BIT_BASE + 0x1B0)
+#define RET_DEC_PIC_SEQ_EXT_INFO			(BIT_BASE + 0x1D0) // for MP2
+
+#define RET_DEC_PIC_MP2_BAR_LEFT_RIGHT      (BIT_BASE + 0x180)
+#define RET_DEC_PIC_MP2_BAR_TOP_BOTTOM		(BIT_BASE + 0x184)
+
+#define RET_DEC_PIC_MP2_OFFSET1				(BIT_BASE + 0x19C) // for MP2
+#define RET_DEC_PIC_MP2_OFFSET2				(BIT_BASE + 0x1A0) // for MP2
+#define RET_DEC_PIC_MP2_OFFSET3				(BIT_BASE + 0x1A4) // for MP2
+#define RET_DEC_PIC_MP2_OFFSET_NUM			(BIT_BASE + 0x1A8) // for MP2
+
+
+//------------------------------------------------------------------------------
+// [DEC SET FRAME BUF] COMMAND
+//------------------------------------------------------------------------------
+#define CMD_SET_FRAME_BUF_NUM       (BIT_BASE + 0x180)
+#define CMD_SET_FRAME_BUF_STRIDE    (BIT_BASE + 0x184)
+
+#define CMD_SET_FRAME_SLICE_BB_START	(BIT_BASE + 0x188)
+#define CMD_SET_FRAME_SLICE_BB_SIZE		(BIT_BASE + 0x18C)
+#define CMD_SET_FRAME_AXI_BIT_ADDR		(BIT_BASE + 0x190)
+#define CMD_SET_FRAME_AXI_IPACDC_ADDR	(BIT_BASE + 0x194)
+#define CMD_SET_FRAME_AXI_DBKY_ADDR		(BIT_BASE + 0x198)
+#define CMD_SET_FRAME_AXI_DBKC_ADDR		(BIT_BASE + 0x19C)
+#define CMD_SET_FRAME_AXI_OVL_ADDR		(BIT_BASE + 0x1A0)
+#define CMD_SET_FRAME_AXI_ME_ADDR		(BIT_BASE + 0x1A4)	//for coda7L ME_SRAM
+
+#define CMD_SET_FRM_AXI_SCLY_ADDR			 (BIT_BASE + 0x1A4)
+#define CMD_SET_FRM_AXI_SCLC_ADDR			 (BIT_BASE + 0x1A8)
+#define CMD_SET_FRM_AXI_SCL_PACKED_SYNC_ADDR (BIT_BASE + 0x1AC)
+
+
+#define CMD_SET_FRAME_MB_BUF_BASE       (BIT_BASE + 0x1B0)
+
+#define CMD_SET_FRAME_MAX_DEC_SIZE		(BIT_BASE + 0x1B8)
+#define CMD_SET_FRAME_DELAY     		(BIT_BASE + 0x1BC)
+
+#define RET_SET_FRAME_SUCCESS           (BIT_BASE + 0x1C0)
+
+
+//------------------------------------------------------------------------------
+// [DEC_PARA_SET] COMMAND
+//------------------------------------------------------------------------------
+#define CMD_DEC_PARA_SET_TYPE       (BIT_BASE + 0x180)
+#define CMD_DEC_PARA_SET_SIZE       (BIT_BASE + 0x184)
+
+#define RET_DEC_PARA_SET_SUCCESS        (BIT_BASE + 0x1C0)
+
+//------------------------------------------------------------------------------
+// [DEC_BUF_FLUSH] COMMAND
+//------------------------------------------------------------------------------
+#define RET_DEC_BUF_FLUSH_SUCCESS       (BIT_BASE + 0x1C0)
+
+//------------------------------------------------------------------------------
+// [SLEEP/WAKE] COMMAND
+//------------------------------------------------------------------------------
+#define RET_SLEEP_WAKE_SUCCESS          (BIT_BASE + 0x1C0)
+
+
+//------------------------------------------------------------------------------
+// [SET PIC INFO] COMMAND
+//------------------------------------------------------------------------------
+#define GDI_PRI_RD_PRIO_L   		(GDMA_BASE + 0x000)
+#define GDI_PRI_RD_PRIO_H   		(GDMA_BASE + 0x004)
+#define GDI_PRI_WR_PRIO_L   		(GDMA_BASE + 0x008)
+#define GDI_PRI_WR_PRIO_H   		(GDMA_BASE + 0x00c)
+#define GDI_PRI_RD_LOCK_CNT 		(GDMA_BASE + 0x010)
+#define GDI_PRI_WR_LOCK_CNT 		(GDMA_BASE + 0x014)
+#define GDI_SEC_RD_PRIO_L   		(GDMA_BASE + 0x018)
+#define GDI_SEC_RD_PRIO_H   		(GDMA_BASE + 0x01c)
+#define GDI_SEC_WR_PRIO_L   		(GDMA_BASE + 0x020)
+#define GDI_SEC_WR_PRIO_H   		(GDMA_BASE + 0x024)
+#define GDI_SEC_RD_LOCK_CNT 		(GDMA_BASE + 0x028)
+#define GDI_SEC_WR_LOCK_CNT 		(GDMA_BASE + 0x02c)
+#define GDI_SEC_CLIENT_EN   		(GDMA_BASE + 0x030)
+#define GDI_CONTROL                 (GDMA_BASE + 0x034)
+#define GDI_PIC_INIT_HOST           (GDMA_BASE + 0x038)
+
+#define GDI_HW_VERINFO            	(GDMA_BASE + 0x050)
+#define GDI_PINFO_REQ               (GDMA_BASE + 0x060)
+#define GDI_PINFO_ACK               (GDMA_BASE + 0x064)
+#define GDI_PINFO_ADDR              (GDMA_BASE + 0x068)
+#define GDI_PINFO_DATA              (GDMA_BASE + 0x06c)
+#define GDI_BWB_ENABLE              (GDMA_BASE + 0x070)
+#define GDI_BWB_SIZE                (GDMA_BASE + 0x074)
+#define GDI_BWB_STD_STRUCT          (GDMA_BASE + 0x078)
+#define GDI_BWB_STATUS              (GDMA_BASE + 0x07c)
+
+#define GDI_STATUS					(GDMA_BASE + 0x080)
+
+#define GDI_DEBUG_0                 (GDMA_BASE + 0x084)
+#define GDI_DEBUG_1                 (GDMA_BASE + 0x088)
+#define GDI_DEBUG_2                 (GDMA_BASE + 0x08c)
+#define GDI_DEBUG_3                 (GDMA_BASE + 0x090)
+#define GDI_DEBUG_PROBE_ADDR        (GDMA_BASE + 0x094)
+#define GDI_DEBUG_PROBE_DATA        (GDMA_BASE + 0x098)
+
+
+
+// write protect
+#define GDI_WPROT_ERR_CLR			(GDMA_BASE + 0x0A0)
+#define GDI_WPROT_ERR_RSN			(GDMA_BASE + 0x0A4)
+#define GDI_WPROT_ERR_ADR			(GDMA_BASE + 0x0A8)
+#define GDI_WPROT_RGN_EN			(GDMA_BASE + 0x0AC)
+#define GDI_WPROT_RGN0_STA			(GDMA_BASE + 0x0B0)
+#define GDI_WPROT_RGN0_END			(GDMA_BASE + 0x0B4)
+#define GDI_WPROT_RGN1_STA			(GDMA_BASE + 0x0B8)
+#define GDI_WPROT_RGN1_END			(GDMA_BASE + 0x0BC)
+#define GDI_WPROT_RGN2_STA			(GDMA_BASE + 0x0C0)
+#define GDI_WPROT_RGN2_END			(GDMA_BASE + 0x0C4)
+#define GDI_WPROT_RGN3_STA			(GDMA_BASE + 0x0C8)
+#define GDI_WPROT_RGN3_END			(GDMA_BASE + 0x0CC)
+#define GDI_WPROT_RGN4_STA			(GDMA_BASE + 0x0D0)
+#define GDI_WPROT_RGN4_END			(GDMA_BASE + 0x0D4)
+#define GDI_WPROT_RGN5_STA			(GDMA_BASE + 0x0D8)
+#define GDI_WPROT_RGN5_END			(GDMA_BASE + 0x0DC)
+
+#define GDI_BUS_CTRL				(GDMA_BASE + 0x0F0)
+#define GDI_BUS_STATUS				(GDMA_BASE + 0x0F4)
+
+
+
+#define GDI_SIZE_ERR_FLAG           (GDMA_BASE + 0x0e0)
+#define GDI_ADR_RQ_SIZE_ERR_PRI0	(GDMA_BASE + 0x100)
+#define GDI_ADR_RQ_SIZE_ERR_PRI1	(GDMA_BASE + 0x104)
+#define GDI_ADR_RQ_SIZE_ERR_PRI1	(GDMA_BASE + 0x104)
+#define GDI_ADR_RQ_SIZE_ERR_PRI2	(GDMA_BASE + 0x108)
+#define GDI_ADR_WQ_SIZE_ERR_PRI0	(GDMA_BASE + 0x10c)
+#define GDI_ADR_WQ_SIZE_ERR_PRI1	(GDMA_BASE + 0x110)
+#define GDI_ADR_WQ_SIZE_ERR_PRI2	(GDMA_BASE + 0x114)
+
+#define GDI_ADR_RQ_SIZE_ERR_SEC0	(GDMA_BASE + 0x118)
+#define GDI_ADR_RQ_SIZE_ERR_SEC1	(GDMA_BASE + 0x11c)
+#define GDI_ADR_RQ_SIZE_ERR_SEC2	(GDMA_BASE + 0x120)
+
+#define GDI_ADR_WQ_SIZE_ERR_SEC0	(GDMA_BASE + 0x124)
+#define GDI_ADR_WQ_SIZE_ERR_SEC1	(GDMA_BASE + 0x128)
+#define GDI_ADR_WQ_SIZE_ERR_SEC2	(GDMA_BASE + 0x12c)
+
+#define GDI_INFO_CONTROL			(GDMA_BASE + 0x400)
+#define GDI_INFO_PIC_SIZE			(GDMA_BASE + 0x404)
+#define GDI_INFO_BASE_Y				(GDMA_BASE + 0x408)
+#define GDI_INFO_BASE_CB			(GDMA_BASE + 0x40C)
+#define GDI_INFO_BASE_CR			(GDMA_BASE + 0x410)
+
+#define GDI_XY2_CAS_0				(GDMA_BASE + 0x800)
+#define GDI_XY2_CAS_F				(GDMA_BASE + 0x83C)
+
+#define GDI_XY2_BA_0				(GDMA_BASE + 0x840)
+#define GDI_XY2_BA_1				(GDMA_BASE + 0x844)
+#define GDI_XY2_BA_2				(GDMA_BASE + 0x848)
+#define GDI_XY2_BA_3				(GDMA_BASE + 0x84C)
+
+#define GDI_XY2_RAS_0				(GDMA_BASE + 0x850)
+#define GDI_XY2_RAS_F				(GDMA_BASE + 0x88C)
+
+#define GDI_XY2_RBC_CONFIG			(GDMA_BASE + 0x890)
+#define GDI_RBC2_AXI_0				(GDMA_BASE + 0x8A0)
+#define GDI_RBC2_AXI_1F				(GDMA_BASE + 0x91C)
+#define GDI_TILEDBUF_BASE			(GDMA_BASE + 0x920)
+
+//------------------------------------------------------------------------------
+// Product, Reconfiguration Information
+//------------------------------------------------------------------------------
+#define DBG_CONFIG_REPORT_0         (GDMA_BASE + 0x040)    //product name and version
+#define DBG_CONFIG_REPORT_1         (GDMA_BASE + 0x044)    //interface configuration, hardware definition
+#define DBG_CONFIG_REPORT_2         (GDMA_BASE + 0x048)    //standard definition
+#define DBG_CONFIG_REPORT_3         (GDMA_BASE + 0x04C)    //standard detail definition
+#define DBG_CONFIG_REPORT_4         (GDMA_BASE + 0x050)    //definition in cnm_define
+#define DBG_CONFIG_REPORT_5         (GDMA_BASE + 0x054)
+#define DBG_CONFIG_REPORT_6         (GDMA_BASE + 0x058)
+#define DBG_CONFIG_REPORT_7         (GDMA_BASE + 0x05C)
+
+//------------------------------------------------------------------------------
+// MEMORY COPY MODULE REGISTER
+//------------------------------------------------------------------------------
+#define	ADDR_DMAC_PIC_RUN			(DMAC_BASE+0x000)
+#define	ADDR_DMAC_PIC_STATUS		(DMAC_BASE+0x004)
+#define	ADDR_DMAC_PIC_OP_MODE		(DMAC_BASE+0x008)
+#define	ADDR_DMAC_ID				(DMAC_BASE+0x00c)	//the result muse be 0x4d435059
+
+#define	ADDR_DMAC_SRC_BASE_Y		(DMAC_BASE+0x010)
+#define	ADDR_DMAC_SRC_BASE_CB		(DMAC_BASE+0x014)
+#define	ADDR_DMAC_SRC_BASE_CR		(DMAC_BASE+0x018)
+#define	ADDR_DMAC_SRC_STRIDE		(DMAC_BASE+0x01c)
+
+#define	ADDR_DMAC_DST_BASE_Y		(DMAC_BASE+0x020)
+#define	ADDR_DMAC_DST_BASE_CB		(DMAC_BASE+0x024)
+#define	ADDR_DMAC_DST_BASE_CR		(DMAC_BASE+0x028)
+#define	ADDR_DMAC_DST_STRIDE		(DMAC_BASE+0x02c)
+
+#define	ADDR_DMAC_SRC_MB_POS_X		(DMAC_BASE+0x030)
+#define	ADDR_DMAC_SRC_MB_POS_Y		(DMAC_BASE+0x034)
+#define	ADDR_DMAC_SRC_MB_BLK_X		(DMAC_BASE+0x038)
+#define	ADDR_DMAC_SRC_MB_BLK_Y		(DMAC_BASE+0x03c)
+
+#define	ADDR_DMAC_DST_MB_POS_X		(DMAC_BASE+0x040)
+#define	ADDR_DMAC_DST_MB_POS_Y		(DMAC_BASE+0x044)
+#define	ADDR_DMAC_DST_MB_BLK_X		(DMAC_BASE+0x048)
+#define	ADDR_DMAC_DST_MB_BLK_Y		(DMAC_BASE+0x04c)
+
+#define	ADDR_DMAC_SET_COLOR_Y		(DMAC_BASE+0x050)
+#define	ADDR_DMAC_SET_COLOR_CB		(DMAC_BASE+0x054)
+#define	ADDR_DMAC_SET_COLOR_CR		(DMAC_BASE+0x058)
+
+#define	ADDR_DMAC_SUB_SAMPLE_X		(DMAC_BASE+0x060)
+#define	ADDR_DMAC_SUB_SAMPLE_Y		(DMAC_BASE+0x064)
+
+
+
+//------------------------------------------------------------------------------
+// DMAC
+//------------------------------------------------------------------------------
+#define DMAC_DMAC_RUN		    (DMAC_BASE + 0x00)
+#define DMAC_SOFT_RESET		    (DMAC_BASE + 0x04)
+#define DMAC_DMAC_MODE		    (DMAC_BASE + 0x08)
+#define DMAC_DESC_ADDR		    (DMAC_BASE + 0x0c)
+#define DMAC_DESC0				(DMAC_BASE + 0x10)
+#define DMAC_DESC1				(DMAC_BASE + 0x14)
+#define DMAC_DESC2				(DMAC_BASE + 0x18)
+#define DMAC_DESC3				(DMAC_BASE + 0x1c)
+#define DMAC_DESC4				(DMAC_BASE + 0x20)
+#define DMAC_DESC5				(DMAC_BASE + 0x24)
+#define DMAC_DESC6				(DMAC_BASE + 0x28)
+#define DMAC_DESC7				(DMAC_BASE + 0x2c)
+
+
+//------------------------------------------------------------------------------
+// [FIRMWARE VERSION] COMMAND
+// [32:16] project number =>
+// [16:0]  version => xxxx.xxxx.xxxxxxxx
+//------------------------------------------------------------------------------
+#define RET_FW_VER_NUM					(BIT_BASE + 0x1c0)
+#define RET_FW_CODE_REV             (BIT_BASE + 0x1c4)
+
+
+#endif //__CODA7L_REGS_H__
+
diff --git a/board/rda/common/include/coda7l_test_video.txt b/board/rda/common/include/coda7l_test_video.txt
new file mode 100644
index 0000000000..2d52fc6460
--- /dev/null
+++ b/board/rda/common/include/coda7l_test_video.txt
@@ -0,0 +1,9435 @@
+0x01000000,	0x1F404D27,	0x5A408D8D,	0x0000903D,	0xEE280100,	0x00C81508,	0x25010000,	0x000200B8,
+0xB4CC7F00,	0x1A917434,	0x778F4F3E,	0x94966C10,	0x036EB76C,	0xE3D1E21C,	0x7842BB5F,	0x1C857462,
+0x65111D33,	0xA363E24F,	0xDACFE14B,	0x21CE79E2,	0xB953854A,	0x75AC19AB,	0xC17FE329,	0xAF3F84BC,
+0xD8B7E21F,	0x1FCFF248,	0x5187EDB8,	0x6253B4AC,	0xE71F2548,	0x5BAE0113,	0xF6A98FBD,	0xFE997DFE,
+0x4DB8D2CD,	0xBB1D42E6,	0xDC771AD8,	0xBBA84A47,	0xE394F269,	0xB1865720,	0xF36CE7CF,	0x292917BC,
+0xE0E43EEB,	0xF9F3BF0B,	0x24924B12,	0x7583492D,	0xB71F5655,	0x0F5FAECD,	0xEF9036B6,	0xDDDC2581,
+0x3A10C8E2,	0x2F0354D7,	0x1702D9FA,	0xDDA471E6,	0x1FF5279D,	0x8FB6335D,	0x4FC973BE,	0x00ABB163,
+0x66976F24,	0xCE5DC065,	0x81BD5CD0,	0x1A36046B,	0xC6662FDE,	0xE81B47C1,	0xBFC15FB7,	0xB29507EE,
+0x2CA2CBBA,	0xA41ECCC1,	0x2FC88D3C,	0xF793B9E8,	0x7C46E6E1,	0xB193B580,	0xCEFE0BC8,	0xB72CA7AD,
+0x10ED37F8,	0x5BB9C37B,	0x24D26758,	0x791A472C,	0x3FC6CE0B,	0xF976A6A6,	0xF40DCD94,	0x04877935,
+0x49E010F1,	0x8638A128,	0x0584AEF1,	0x27A70AEF,	0x356FB08E,	0x5648D135,	0xB4A38A5B,	0xE51E6C69,
+0xC02E9621,	0x4AE0D7CE,	0xBD8FE74B,	0x3C7DF817,	0xB465142E,	0x104B2371,	0x5E7B61D5,	0xCF697BFA,
+0xBAD206D2,	0x3D5470B0,	0x9DB5FA0A,	0xAA94FBE1,	0xFEC6683E,	0x55C4C532,	0x31BB4BB6,	0xCDF9DC97,
+0x2263D167,	0x294F913A,	0x06D405E0,	0xCB11E6AB,	0xD7E6A708,	0x1E01542A,	0xBDBFAD22,	0xBED866F9,
+0xD99F0443,	0xD204DC7D,	0xD57E3C3D,	0xFB542E4E,	0x70562917,	0xB6EA34D2,	0x7953B0E6,	0xAD649B2E,
+0x6E03B5F2,	0x32D09FCB,	0xB7E19873,	0xC6546843,	0x3059A8B0,	0x5F6A65FF,	0x383F4531,	0x72DB461D,
+0x6C4CD85F,	0xF3138808,	0x5FB5982C,	0x8AD199C1,	0x67DB38D4,	0x607DBF5D,	0x1D4ACDD1,	0xB142488B,
+0xFD42458F,	0xA99A8A01,	0x6708D4F2,	0x8BBB782A,	0xD51FA650,	0xCC255367,	0x628FBB6D,	0x34060CFE,
+0x0CD22EDB,	0x9285AA7D,	0x086F0589,	0xADE23CC4,	0x5B64EDDB,	0x72DCFC71,	0x30842B8A,	0x855A5D76,
+0x2F858613,	0x809B07BC,	0xF26295DB,	0xF72797D5,	0x608C8662,	0x207AEA1E,	0x74150B7F,	0x48919CCD,
+0xC5D2DB54,	0x4B68880A,	0x167DCA39,	0xC2EBF403,	0xC2379C97,	0x81E739AE,	0x1675D97D,	0x5CEE9592,
+0xA3839961,	0xE5E97F95,	0x98938117,	0x4C59A62B,	0xF9B7642F,	0x27ED2194,	0xA5B48FE9,	0x9DBE245F,
+0x44C01ECA,	0x21587121,	0xEE047B89,	0xDD22B3CD,	0x60D35F67,	0x23D61382,	0x9B5BC1B6,	0xB32CDB1F,
+0x893165C3,	0x52717FB8,	0x36834659,	0x01BC42DE,	0xE59794D0,	0x3E694FD3,	0xA4CC8667,	0x07BFD9F2,
+0x8035EA1E,	0x519C0B99,	0x79EE2888,	0xF6D67FC5,	0xFC196B6B,	0xFF0F810F,	0xE76D6CFE,	0x73D9114A,
+0x55DC5D9B,	0xA5FAE39D,	0x669A88BA,	0x2ABA3EF7,	0x28B41E00,	0x77455A7F,	0x5ED23953,	0x7E627F7E,
+0xAC6DDB01,	0x16479748,	0x57636FD0,	0x24EC1FC0,	0xA94CFC71,	0x1332CFE4,	0x9A049B05,	0x1F17AD9A,
+0xE69D6C81,	0xDD125C45,	0x476E7CEE,	0x7E70F050,	0x685C421B,	0x6461779A,	0x065EB196,	0xD486EEB9,
+0xA0079090,	0xF8963C08,	0x9A48CE81,	0xFD6BB425,	0x9EFA89E1,	0x5B7F5394,	0x6EAA5D11,	0x4AEE12B7,
+0xED82AF74,	0x13DB9668,	0xE389D188,	0x1A6740F3,	0xDD97291D,	0x84E3F294,	0x82444DD1,	0xEA841497,
+0x684F55BE,	0x870572FB,	0xD0081B00,	0xD2E46E60,	0x5AFFE4E6,	0xBB584138,	0xB20AB467,	0x22EDB941,
+0xEBC98524,	0x2F1A6434,	0x54578E11,	0x04E1F2CA,	0x5E897233,	0x57F9950E,	0x990DA8F8,	0x3A9CBB07,
+0xF92B9E9C,	0x1EE2B205,	0xADDE8043,	0x7C33E7DF,	0xC0E12E54,	0xEA0F571C,	0xEB26302A,	0xCFC906F9,
+0x4DA2074B,	0xAF74A68F,	0x00201E9E,	0x089E05E4,	0xA6AE02A1,	0x309FB5C0,	0xB1CDD680,	0x39DA0328,
+0x66AD8CDF,	0x5D9CE75E,	0xFA215794,	0x4417EC3A,	0x6D90CB21,	0xFCC6390B,	0xB423B4F2,	0xD1CE41E0,
+0x0419C01B,	0x53A1BBBF,	0x78A01250,	0x6E57058A,	0x5ADDDDA1,	0xAF636191,	0xB2B68CFC,	0x67648C29,
+0xE9C8703F,	0x4CDCA944,	0x406D7026,	0x2BBA3EB5,	0x382963EC,	0x0ABBA19B,	0xE2BAA3BC,	0x45E7F715,
+0x28F91065,	0x77C02B68,	0x3B87A7C4,	0xF03B7259,	0xDB2CADDF,	0x26593C6B,	0x8AF1814A,	0x8F96B6FB,
+0xBCC3A90A,	0xF99A80DA,	0xDE110C49,	0xBED673D9,	0x130EE126,	0x0B93B69E,	0x7D7737C3,	0xE66BCBDB,
+0xD218C88C,	0x59BF6AC3,	0xDD06CD32,	0x4733644E,	0x6514D1BE,	0x0D5D3D84,	0x23FCFC26,	0x424CF9FD,
+0x538B6400,	0xC3ACBEEE,	0x83469CDF,	0x627D8A69,	0x3C120BDF,	0xD0D48639,	0x2CEC0A12,	0x218338EB,
+0x0BDD176F,	0x3C891030,	0xC5431FC9,	0x651A7B62,	0x60E8E5AB,	0x9F45983F,	0x33D9BACA,	0x6CB63448,
+0x86D85E5E,	0xC28E7397,	0xB954FCB3,	0x0385E1EA,	0xB7E3FC29,	0x52054F36,	0x873E9C0B,	0xFF61EECC,
+0x326A3E06,	0x35C6871E,	0x43EEA7BA,	0xCB97494B,	0x03358D9E,	0x32C1CEB6,	0xC9BF6F51,	0xD5C311F2,
+0x889FC519,	0xD573BE09,	0xDFF9585D,	0x7AE23F2F,	0xBF90825D,	0x64E32A3B,	0x8972EC9B,	0x006FE3D8,
+0x05C46F2A,	0xF37FF7B2,	0xCAC80273,	0xD79F2784,	0x2476D000,	0xD8A7752F,	0xF6A679E7,	0x3CB4C80F,
+0x7A3C01D7,	0x4EA105A4,	0x32029165,	0x39F63AE1,	0xF81147CA,	0x43230048,	0xA53080A1,	0x3EC01BA3,
+0x44A10A6C,	0xF79F603A,	0xBEAB2F4F,	0xEDDCFE14,	0xE1C51172,	0x30DFF361,	0xA46E90F7,	0x73AF0A0A,
+0x0903E05B,	0x96B0B552,	0x79E024E9,	0x88A7DBD4,	0x00AB633A,	0x72CA0DDC,	0xD0BF266D,	0x7BBF62B3,
+0x175377EF,	0x7B70283D,	0x85E78587,	0x5EFF9A7C,	0x2AAC9724,	0x512E8998,	0x53D106E5,	0x60AA3620,
+0xF881155E,	0x8A83A58C,	0x9E248734,	0x12473BC1,	0xCD8E485F,	0x7F3EF67A,	0xDEB71265,	0xF68FBB5F,
+0x87A7DFEB,	0x46F2BFA5,	0xEE2A213B,	0xB3B6F3F8,	0x724DA9AA,	0xBC19314F,	0x35EEEAB6,	0x38C6811B,
+0x6113E099,	0x9C11E04F,	0x3016D827,	0x7FA8E2DB,	0x4DB0302D,	0x2B9DFB6C,	0x2FA14FEE,	0x3F2D1E1F,
+0x7000B0ED,	0xBC6B4B1F,	0xAB02C6BD,	0x189B6F6F,	0x1AC167F8,	0x4BCAC0F0,	0x84BDB593,	0x34F20634,
+0x6C4063FC,	0x5B69D619,	0x5E329343,	0x9A1C6D66,	0x1985ADBE,	0x734B262B,	0x978CB2B5,	0x59AE9AD4,
+0x8F4BD91C,	0x1735A843,	0x98A1B996,	0x9AC8576E,	0xC36E239C,	0x10354985,	0xDD3D6D2C,	0x69994D30,
+0xA7F7593C,	0xFA540656,	0x978A8CFA,	0xF9015E9D,	0x7CB50E22,	0x40329D6D,	0x73092A94,	0xD5D886D2,
+0x00ACE8BD,	0xD223AEE4,	0xB614B52C,	0x39B1701B,	0xC2D65C39,	0x84CBB065,	0x5B05C8DC,	0x36FE57DA,
+0x4754B784,	0x0BF154F4,	0xDB3390ED,	0x22FCC82C,	0x415A4479,	0x3E3A4600,	0xB2D49E95,	0x19199A55,
+0xF8E56AFD,	0xCA195645,	0x9238E80A,	0x6F64E1CE,	0x9AB851E2,	0x990E8106,	0xF6120060,	0x3EC5E06A,
+0xD5764449,	0xB1832144,	0x89C3231D,	0x1C14E6AE,	0x67D952F1,	0xAEEFD026,	0xFDF020EA,	0x5453F648,
+0x5A8513F2,	0xDEAA9199,	0x84869341,	0xFB41A696,	0x76EFFA54,	0xED6627D9,	0x0AE8D001,	0x04D5DC05,
+0xD0299147,	0xF1E7D634,	0x6AAF9021,	0x27A79A46,	0x7849C572,	0x03EC69BB,	0x19EBF068,	0x37787183,
+0x3339450A,	0xA7C84CB8,	0x848959EF,	0x072E4637,	0x29833214,	0x02A5AFD0,	0x7562EE8F,	0xDAF15F9F,
+0x01C38819,	0x2541A47C,	0x1D9D1582,	0xB434F16A,	0x8EDA91FD,	0x9D8ACC85,	0x12117953,	0xC4BD73BF,
+0x66E22182,	0x4ECC4305,	0x597AF136,	0xB8D50A41,	0x4498AAE6,	0x2A1003CC,	0x5B17A853,	0x9676898B,
+0xD5E320DD,	0xF6072ECF,	0x7865DBA0,	0xD01C61ED,	0xD09029E5,	0xA65B6B55,	0x67B1FE47,	0xF60CE961,
+0xC64F12FB,	0x0E0869A0,	0xC9AC33F9,	0xA9FC3751,	0x70499745,	0xC3DB37F3,	0x321FE32D,	0xE90317D6,
+0x560A8159,	0xD855F789,	0x8DF8907F,	0x47DA9450,	0x4447B407,	0x0E5661FC,	0xD56A1A98,	0xDD6A1376,
+0xB431B72C,	0xF1A7FD41,	0xE827CABF,	0x858090C1,	0xEEEFE633,	0x1342DFD1,	0xA9D86010,	0x2A676096,
+0xE8CB23E4,	0xDA9D607E,	0x877CFD78,	0xBB60C7BE,	0x2EF63637,	0x8E8F5664,	0xF2568EF6,	0xCF72BE29,
+0x44B4D7DB,	0x45C944EB,	0xF58A3303,	0x132892E1,	0x534F4471,	0xEF2BDDAB,	0xD3E213FD,	0xB8CFEC86,
+0x449E6CDD,	0x8709837D,	0xF15DEB2F,	0xCDA1688E,	0xE6365419,	0x7AAFC431,	0x61AB843F,	0x6BB98522,
+0xF51337BA,	0x7994DE1F,	0x9127E5BA,	0x66BA5218,	0xDA748A6E,	0xFABCBB41,	0xEC5A6C26,	0xA130B02E,
+0xF593176F,	0x092F137D,	0xE180C586,	0x88F302CB,	0xD547CA5E,	0xAA2405EA,	0x4748D00F,	0xD9F1BB55,
+0x9CB165DC,	0x8EFFFF49,	0x09C50DAF,	0x424D2362,	0x9FCE3586,	0x8B77E5A2,	0x6748A122,	0x936A9323,
+0xDCAAC792,	0xD55D7F4A,	0xE2B7DEF9,	0xD4DAB540,	0x1FBF280D,	0x3097239A,	0xB8161ECB,	0xA99CB83D,
+0xEC736F56,	0x98482FA8,	0x6F59722D,	0x28CD3D73,	0xA60D7B9B,	0xF75792A4,	0x23090991,	0x3FFBD218,
+0xF2613771,	0xD96106C3,	0x6C006966,	0x3B3E773D,	0x5AD50907,	0x1C23119E,	0x262BC867,	0x4B9725C4,
+0x6563BE30,	0x0BCFA5C9,	0x699E742E,	0xB1A2D413,	0xC54A75CA,	0x425A6960,	0xB3E9B9CA,	0x56BE16C7,
+0x509D0EFA,	0x711BACAF,	0x1FA533C6,	0xDEB3E840,	0x96BBCAF9,	0xDA1B91FD,	0x737824A5,	0x245EA66E,
+0x0A3AC030,	0x01B0567C,	0x2EB29709,	0xCD80BE54,	0x1594BC69,	0xFE5A259E,	0xF7B80C9A,	0xE19DEE42,
+0x6618912C,	0xF785BFF0,	0x1568100D,	0x3955FCF6,	0xAC20E9B7,	0x93E6051A,	0x47B2B4D3,	0x2E167443,
+0xAE2D9E53,	0x5CAF111A,	0xE75380AC,	0xD57874AC,	0xD8CD3A4E,	0xE63CA533,	0xBB63C2FB,	0x80894BC6,
+0xC29A79AE,	0x5027A02F,	0x6C8A9F7F,	0xA59756F0,	0x5B123878,	0xC9DEDA6D,	0x77E1BDC0,	0x46D1449B,
+0x0A15ADDD,	0xAD9409F4,	0xCFD7BD38,	0xE97BB9A6,	0x6AED2A6F,	0xF8F8BDE1,	0x71A796D1,	0xDBDB169D,
+0x32CF0AFF,	0x3C606182,	0x2736E085,	0x1970C282,	0x46B58A9E,	0x79B61D4A,	0x74905075,	0x0C87BBBB,
+0x5E4E8C8B,	0xAA8E22C2,	0xAB4C450A,	0x0008CCFA,	0xAD62BA5F,	0x5A18143A,	0xDFF5BCDA,	0x22F82703,
+0xF5097260,	0x530C4C05,	0x7025F44B,	0x49CA1071,	0xA4CC6E3E,	0xD58275D4,	0xA9154295,	0x25675EFB,
+0xFF684E8D,	0x47725301,	0x3A1547D6,	0x3E46C884,	0x9F119E3A,	0x6BB83C78,	0xD6FB8970,	0xBD5925C9,
+0x1D58DC0C,	0xFAC6E06C,	0x80D91C92,	0x11356574,	0x8C99CCB8,	0x83773943,	0x427441F7,	0xCAA489C6,
+0xA5C39422,	0x10FD56B3,	0xC1A8E13E,	0x6229C0D9,	0x4723EF29,	0x79393AA7,	0xC8BB915B,	0xB6C6B49F,
+0x22F82630,	0x160E9F7F,	0x47A3C803,	0xE4882D8C,	0xA3AB2B1A,	0xE037857A,	0xC382EF6A,	0x412CD54B,
+0x41C458FC,	0xC4727B80,	0x5F1C3CE7,	0xAAEAD12B,	0x708944D3,	0x8E382DD9,	0x8A34E39D,	0x6E8A18B1,
+0x00F11D4C,	0x2F3988BD,	0x48425CC4,	0xECC81390,	0x0E4CAF45,	0x5A55FBC1,	0x830B4563,	0x5220A656,
+0x9941DE92,	0x7E91FDEC,	0x0F5069FA,	0x793D3275,	0xF6F3E65F,	0xBB0685F9,	0xA32FD9CB,	0x54DDB520,
+0x5A40783E,	0x3F8B810D,	0x2312716D,	0x3B99C1B8,	0x43A9B70D,	0x374A41B6,	0x8F3E6E55,	0x9201BAC4,
+0x827E8D38,	0x6F10265B,	0x3BB2140D,	0x4994CFE5,	0x42E99637,	0x2A815ADB,	0xA891980C,	0xD81EE1BC,
+0x579EB4BF,	0x5F790C8C,	0x1C72777B,	0x9AC4AFBE,	0xB1888D24,	0xA0EE1141,	0x7C5B03C6,	0x3262BDC9,
+0x715B019D,	0x9BDD420E,	0x829C837E,	0xFE004623,	0xBA32A3E7,	0x95E6CA65,	0x0BFD959A,	0xB36AFEF5,
+0x5E1E0D60,	0x3D72EFC2,	0xC0884171,	0x1D323552,	0x671A8D28,	0x996EA039,	0xF0D36479,	0xAE697A68,
+0x374DF2DC,	0xBBE2D052,	0xA8C1E2E7,	0xD554975E,	0xADD912CA,	0x7B4184FB,	0xB0571035,	0xD5062473,
+0xBA731F9B,	0x4F6840AE,	0x72E58EA8,	0xAAE7C93B,	0x73B7D4B8,	0xF21E7740,	0xAE5899D2,	0x1FDBC933,
+0x03D770F5,	0x0E5D8C5D,	0x608201C9,	0xA789AC0F,	0x3FBF5156,	0xFE8E9773,	0xC8DB8478,	0x78F6979B,
+0xB9318291,	0x46F92879,	0xA48CDF60,	0xEA93954B,	0x4B0830A0,	0xA2B8E5DC,	0x9FEB7A64,	0x4A605414,
+0xE6537FEB,	0xF2AF57CC,	0x2CFA60AB,	0xC3AC37D2,	0x947C555A,	0x2577864B,	0x994BB97D,	0x7F4B586D,
+0x828F6C9B,	0x83024746,	0x2E233069,	0x666EE7E8,	0xC8103A7B,	0xFD3B0D7A,	0x7EE8830D,	0xA469D2FE,
+0x5D7E1AAE,	0xE41F61EF,	0x871D68DE,	0xB9C67CDD,	0x869B5F5F,	0xB33CD68D,	0x4B60EDA9,	0xAD80518D,
+0xB3158411,	0x9DD39A3C,	0x5A936D57,	0x318989B4,	0xC916BCC6,	0x9217B199,	0x0ED06DEF,	0x497EB6B5,
+0x03EF9E42,	0x4EA9446B,	0x2BCA9B02,	0x93C52283,	0xF897384A,	0x1EA3DCDB,	0x0B416E4E,	0xE36959AD,
+0xC5830660,	0x64DBBEF8,	0xF5BB114C,	0x780A591B,	0x7D732E23,	0xDFB989CE,	0x16C94402,	0x876F6B87,
+0x5058A414,	0x346FF0C6,	0x05B9B0EA,	0xFEE50A07,	0x6BA6292E,	0x7034444F,	0x7E7DA797,	0xF04E12FD,
+0x5192CA94,	0xF6B5C008,	0x4F37FEAC,	0x3073B0DC,	0xC567E987,	0x5B280E71,	0x78FAA6C1,	0xB860A3D3,
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+0x0066FDC5,	0x533E6B43,	0x98821864,	0xE0E59E98,	0xDE121AE1,	0x9FEADBD2,	0xA9EEE36B,	0xA4B36B2A,
+0x2F45AFDA,	0x950D3FF2,	0x0E867090,	0x3024FA4D,	0x78C2C934,	0xC1600CD3,	0x5415DD7B,	0x67A44995,
+0x8A8A53E1,	0xCE95BB4D,	0x9B66BA28,	0x3D8C9876,	0x7299D3F9,	0xAF50FD77,	0x0EB94542,	0xC4001006,
+0x05C8E75B,	0x5355BC54,	0x2DB73C63,	0x9D923898,	0x92BC7511,	0x86CC56AC,	0xED93574D,	0x36CC4CC4,
+0xE8362989,	0xB7C92660,	0x7F854BE9,	0xC3214180,	0x1BBDEB13,	0x58F33CCD,	0x2F83CBF7,	0x732A0EDD,
+0x63BC358F,	0xA66D6AE2,	0x82BF9F19,	0x4B096252,	0x036D66ED,	0x6C98EE11,	0x687CCDD2,	0x7495C374,
+0xB90C489C,	0x1688D94B,	0xECFF0BCE,	0xA3185401,	0xCB6FAEEE,	0xFBCECE2F,	0xB2A3B461,	0x8C739F4A,
+0xEFDD98B6,	0x89075340,	0xC31C7226,	0xD269DD8E,	0x53FCB36F,	0x796E1C3D,	0xD33E0D30,	0xD4D941B0,
+0xBE033E0E,	0x4636FF78,	0x34A9BE67,	0x842FE639,	0xC71CCC14,	0xC17276FB,	0xFD74422D,	0x4C1DCAAD,
+0x814B0E6E,	0x1C0E0A0F,	0x04A0ACAE,	0xBED3D8B1,	0x84DF92B8,	0x519D9670,	0x7157E2CA,	0xA3BA65AA,
+0x9ED809FF,	0xFDD88464,	0xC4FFECE7,	0x06332FD2,	0xC8807C6D,	0xA41AA69A,	0xFC66E534,	0x139FA663,
+0x3662C32A,	0xA669A93E,	0xFAB2C6A5,	0xCDB799F9,	0x03105F03,	0x49ABDCCA,	0x97BDB5B4,	0x6B91E34E,
+0xEFE63394,	0xED76E2EA,	0x9A5523D1,	0x12384C0B,	0x05112E66,	0x8B6B2605,	0xFD4CEFFA,	0x00000080,
diff --git a/board/rda/common/include/coda960_fw.h b/board/rda/common/include/coda960_fw.h
new file mode 100644
index 0000000000..2f9c868bf6
--- /dev/null
+++ b/board/rda/common/include/coda960_fw.h
@@ -0,0 +1,15880 @@
+#ifndef __CODA960_FW_H__
+#define __CODA960_FW_H__
+
+static const unsigned short bit_code[] = {
+	0xe40e, 0x0020, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x0330, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x034a, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x003a, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058,
+	0xa200, 0xe0c2, 0x005a, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xa2fe,
+	0x3cee, 0x3cef, 0x3cec, 0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d,
+	0xce00, 0xf33e, 0xe41e, 0x0164, 0xe09e, 0xa202, 0xae3e, 0x9f07,
+	0xe0c0, 0x005c, 0xe0c1, 0x0059, 0x3eed, 0xa203, 0x5aed, 0xe052,
+	0xf08a, 0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00,
+	0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2, 0x0008, 0xf00e,
+	0x28ee, 0xe412, 0x013d, 0xe190, 0xe0c0, 0x005c, 0xe0c1, 0x0059,
+	0x3eed, 0xa203, 0x5aed, 0xe052, 0xf08a, 0xe0c1, 0x005d, 0xe055,
+	0xe0c3, 0x005d, 0xa202, 0xce00, 0xe0c0, 0x004a, 0xf08a, 0xe41e,
+	0x019c, 0xe408, 0x005c, 0xe40e, 0x0058, 0xe190, 0xe0c0, 0x043d,
+	0xa1ee, 0xf7d8, 0xe004, 0x0060, 0xe0c2, 0x0009, 0xa200, 0xe0c2,
+	0x0009, 0xe0c0, 0x000d, 0xf7e8, 0xe41e, 0x00b2, 0xe41e, 0x00e2,
+	0xe41e, 0x012c, 0xd071, 0x242a, 0xe181, 0xe41e, 0x0164, 0xe09e,
+	0xa202, 0x9f07, 0xe0c0, 0x0049, 0xe0c1, 0x005b, 0xa111, 0xf033,
+	0xe0c0, 0x0048, 0xe0c2, 0x0047, 0xe0c0, 0x0059, 0xae02, 0xe000,
+	0x0330, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a, 0xe008, 0xffff,
+	0x3cee, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11, 0xe056, 0x3cef,
+	0xe40e, 0x0058, 0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2,
+	0x0008, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xe0c0, 0x0059, 0xf7ea,
+	0xa11e, 0xf198, 0xa202, 0xe0c2, 0x0058, 0xe004, 0xca20, 0xae20,
+	0xe005, 0x210a, 0xe056, 0xe0c2, 0x0070, 0xe004, 0x0000, 0xae20,
+	0xe00a, 0x9cea, 0xe0c2, 0x0071, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+	0x0058, 0xf64e, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058, 0xd027,
+	0x0001, 0xe42e, 0xa200, 0xe0c1, 0x005b, 0xf21b, 0xa23c, 0xa103,
+	0xf37b, 0xa24c, 0xa103, 0xf34b, 0xa258, 0xa103, 0xf1db, 0xe004,
+	0x003a, 0xa103, 0xf2db, 0xe004, 0x003f, 0xa103, 0xf29b, 0xe004,
+	0x0045, 0xa103, 0xf25b, 0xa103, 0xf14b, 0xe004, 0x0063, 0xa103,
+	0xf1ab, 0xe004, 0x006a, 0xa107, 0xf1bb, 0xa200, 0xe0c1, 0x005e,
+	0xf17b, 0xa028, 0xf15e, 0xe0c1, 0x005e, 0xf12b, 0xa010, 0xf10e,
+	0xe004, 0x0049, 0xe0c1, 0x005e, 0xf0bb, 0xa010, 0xa103, 0xf08b,
+	0xa010, 0xf06e, 0xe0c1, 0x005e, 0xf03b, 0xe004, 0x0074, 0xae16,
+	0xe0c1, 0x0040, 0xe041, 0xce21, 0xd111, 0x0000, 0xd112, 0x2800,
+	0xd113, 0x000b, 0xe1e1, 0xe42e, 0xe41e, 0x023a, 0xe0c0, 0x0059,
+	0xa102, 0xe42a, 0xe0c0, 0x005b, 0xa810, 0xf058, 0xa206, 0xe41e,
+	0x0153, 0xe42e, 0xe004, 0x0350, 0xe67c, 0xe0c0, 0x005b, 0xa810,
+	0xf058, 0xa204, 0xe41e, 0x0153, 0xe42e, 0xe004, 0x0352, 0xe67c,
+	0xa200, 0xc401, 0xe188, 0x00eb, 0x3d11, 0xe161, 0x00f2, 0xe188,
+	0x0b0d, 0x3d11, 0xe42e, 0x3cec, 0xe0c0, 0x0041, 0xe005, 0x0000,
+	0xae11, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0c00, 0x88ec,
+	0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0059, 0xa106, 0xf048,
+	0xe004, 0x0076, 0xe42e, 0xe0c0, 0x0059, 0xa10c, 0xf038, 0xe004,
+	0x0071, 0xe004, 0x0070, 0xe42e, 0xe0c0, 0x006b, 0xe167, 0x01a0,
+	0x3d07, 0xe0c0, 0x0414, 0xe428, 0xe0c1, 0x0044, 0xa809, 0xae33,
+	0xe0c0, 0x006a, 0xe167, 0x01a0, 0x3517, 0x3d17, 0xe0c0, 0x006b,
+	0xe056, 0x3517, 0x3d07, 0xe42e, 0xe167, 0x01a0, 0x2907, 0xe0c2,
+	0x0151, 0xa204, 0xe0c2, 0x0150, 0xe0c0, 0x0150, 0xa804, 0xf7da,
+	0xa208, 0xe0c2, 0x0150, 0xe42e, 0xe0c0, 0x004a, 0xe42a, 0xe0c0,
+	0x005b, 0xa110, 0xf142, 0xe0c0, 0x0059, 0xa102, 0xe41a, 0x01be,
+	0xe0c0, 0x0059, 0xa106, 0xe41a, 0x01cb, 0xe0c0, 0x0047, 0xe0c2,
+	0x0048, 0xa200, 0xe0c2, 0x004a, 0xa202, 0xe42e, 0xe0c0, 0x0047,
+	0xe0c2, 0x0049, 0xa200, 0xe0c2, 0x004a, 0xe42e, 0xe0c0, 0x004a,
+	0xa802, 0xa23e, 0x3cf0, 0xa202, 0x58f0, 0xe0c2, 0x0078, 0xa220,
+	0xe0c2, 0x0070, 0xe42e, 0xe0c0, 0x004a, 0xa802, 0xa220, 0xe0c2,
+	0x0076, 0xa200, 0xe0c2, 0x0072, 0xa2fc, 0xe0c2, 0x0077, 0xa2fa,
+	0xe0c2, 0x0071, 0xe42e, 0xe0c0, 0x0045, 0xaf04, 0xa80e, 0xa104,
+	0xe428, 0xa202, 0xe0c2, 0x004a, 0xe0c0, 0x0111, 0xf7e8, 0xca28,
+	0xf7f8, 0xca48, 0xa802, 0xf7e8, 0xa208, 0xae14, 0xa102, 0xe190,
+	0xf7e2, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xe0c0, 0x041f, 0xf7e8,
+	0xa200, 0xe0c2, 0x041c, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xe004,
+	0x0078, 0xe0c2, 0x0009, 0xa200, 0xe0c2, 0x0009, 0xe0c0, 0x000d,
+	0xf7e8, 0xe42e, 0xc001, 0x3443, 0x3c42, 0xc000, 0xe42e, 0xc001,
+	0x2c43, 0x2e42, 0xc000, 0xe42a, 0x1c1e, 0xf0b4, 0xe04a, 0xaf10,
+	0x1857, 0xf074, 0xe009, 0x00ff, 0x1a58, 0xf034, 0xa202, 0xe42e,
+	0xa2fe, 0xe42e, 0xe41e, 0x023a, 0xd160, 0x0620, 0xe004, 0x0019,
+	0xae18, 0xcec0, 0xe42e, 0xe41e, 0x024f, 0xe000, 0x0040, 0xce50,
+	0xa200, 0xd022, 0x00ff, 0xe184, 0x0236, 0xce52, 0xe190, 0xe41e,
+	0x0257, 0xe42e, 0xa204, 0xae22, 0xcc9e, 0xa200, 0xcc72, 0xcc8c,
+	0xcc8e, 0xe004, 0xa810, 0xae20, 0xe00a, 0x9322, 0xce4a, 0xd16f,
+	0x0003, 0xe190, 0xe190, 0xe190, 0xd16f, 0x0000, 0xe42e, 0xe004,
+	0x0030, 0xce50, 0xca50, 0xa802, 0xf7ea, 0xc000, 0xe42e, 0xe004,
+	0x0020, 0xce50, 0xe42e, 0xa200, 0xe0c2, 0x041c, 0xe42e, 0xe41e,
+	0x02bb, 0xe42a, 0xe0c0, 0x0061, 0xe008, 0x001f, 0xe00a, 0x0100,
+	0xe0c2, 0x041c, 0xe41e, 0x02f1, 0xe41e, 0x032b, 0xae12, 0xe0c2,
+	0x041e, 0xe41e, 0x031b, 0xe42e, 0xe41e, 0x02df, 0xe42a, 0xe0c0,
+	0x041f, 0xf7e8, 0xe0c0, 0x0210, 0xa804, 0xf118, 0xe0c0, 0x0215,
+	0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0216, 0xf0be, 0xe0c0, 0x0213,
+	0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0214, 0xf03e, 0xe0c0, 0x020b,
+	0xe00a, 0x0100, 0xe0c2, 0x041c, 0xe41e, 0x02f1, 0xe41e, 0x032b,
+	0xae12, 0xe0c1, 0x0210, 0xa803, 0xae15, 0xe056, 0xe0c1, 0x0204,
+	0xaf0b, 0xa87f, 0xae07, 0xe056, 0xe0c1, 0x0204, 0xa80f, 0xe056,
+	0xe0c2, 0x041e, 0xe41e, 0x031b, 0xe42e, 0xe0c0, 0x041f, 0xf7e8,
+	0xe0c0, 0x041f, 0xf7e8, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xa200,
+	0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xa203, 0xae19, 0xe052,
+	0xf1da, 0xe0c0, 0x0060, 0xaf08, 0xa806, 0xf18a, 0xe0c0, 0x0060,
+	0xa81e, 0xe016, 0xe0c1, 0x0060, 0xa821, 0xe017, 0xe056, 0xf0ea,
+	0xe0c0, 0x0044, 0xaf12, 0xa806, 0xe016, 0xe0c1, 0x0044, 0xaf17,
+	0xa803, 0xe056, 0xf03a, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xe0c0,
+	0x0044, 0xa203, 0xae19, 0xe052, 0xf0ba, 0xe41e, 0x02bb, 0xf088,
+	0xe0c0, 0x0044, 0xaf12, 0xa806, 0xf038, 0xa202, 0xe42e, 0xa200,
+	0xe42e, 0xe0c0, 0x041c, 0xe008, 0x00ff, 0xcca4, 0xc785, 0xe018,
+	0xe000, 0x0500, 0xa002, 0xae04, 0xe0c2, 0x041a, 0xa202, 0xe0c2,
+	0x0418, 0xe0c0, 0x0419, 0xf7ea, 0xa202, 0xe0c2, 0x0418, 0xe0c0,
+	0x0419, 0xf7ea, 0xe0c0, 0x041b, 0xaf20, 0xa01e, 0xaf08, 0xae28,
+	0xe0c1, 0x041b, 0xe009, 0xffff, 0xa01f, 0xaf09, 0xae09, 0xe056,
+	0xe0c2, 0x041d, 0xe42e, 0xe0c0, 0x041c, 0xe00a, 0x0200, 0xe0c2,
+	0x041c, 0xa228, 0xa102, 0xf7f0, 0xe0c0, 0x041c, 0xe00c, 0x0200,
+	0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xaf04, 0xa802, 0xe42e,
+	0xe40e, 0x0c5c, 0xe40e, 0x0354, 0xe40e, 0x0358, 0xe40e, 0x035c,
+	0xe40e, 0x036a, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x0370,
+	0xe40e, 0x0374, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe41e, 0x0398, 0xe40e, 0x00a4,
+	0xe41e, 0x03b9, 0xe40e, 0x00a4, 0xe41e, 0x025b, 0xe41e, 0x0378,
+	0xe41e, 0x0fee, 0xe41e, 0x0458, 0xe41e, 0x0feb, 0xe41e, 0x02ad,
+	0xe40e, 0x00a4, 0xe41e, 0x0378, 0xe41e, 0x0543, 0xe40e, 0x00a4,
+	0xe41e, 0x0548, 0xe40e, 0x00a4, 0xe41e, 0x0579, 0xe40e, 0x00a4,
+	0x2811, 0xa184, 0x2a24, 0xa805, 0xe056, 0xe428, 0xe0c0, 0x0040,
+	0xa215, 0xae17, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x2800,
+	0xd113, 0x000b, 0xe1e1, 0xe42e, 0xe167, 0x05cb, 0xe166, 0x0064,
+	0xd022, 0x0003, 0xe184, 0x0396, 0x9e16, 0x3517, 0x3d17, 0xe42e,
+	0xa200, 0x3c86, 0x3cad, 0x3cbe, 0xe41e, 0x0429, 0xe41e, 0x0566,
+	0xe41e, 0x0686, 0xe41e, 0x0904, 0xe41e, 0x03ba, 0xf0dd, 0xe41e,
+	0x08bd, 0xe41a, 0x03f9, 0xa2fe, 0x3c10, 0x3c83, 0xe41e, 0x052f,
+	0xf03a, 0xa202, 0x3c86, 0xe41e, 0x0b38, 0xe41e, 0x06f6, 0xe16a,
+	0xe42e, 0xe42e, 0xa23e, 0x3cf0, 0xe41e, 0x08bd, 0xe408, 0x03d3,
+	0xe41e, 0x0b72, 0xa10e, 0xf13a, 0xa104, 0xf2ba, 0xa102, 0xf05a,
+	0xf04a, 0xe41e, 0x0951, 0xf6fe, 0xe41e, 0x08bd, 0xe408, 0x03d3,
+	0xe41e, 0x098a, 0xf68e, 0xe41e, 0x01db, 0xf22e, 0xe41e, 0x1459,
+	0xe41e, 0x098a, 0xa2fe, 0x3c10, 0xe41e, 0x1a99, 0xf5ca, 0x2800,
+	0x3c10, 0xe41e, 0x1ab1, 0xe092, 0xa200, 0xe41e, 0x0c40, 0xa200,
+	0x3c9b, 0xe41e, 0x141e, 0xa2fe, 0x3c10, 0xe082, 0xf096, 0xe42e,
+	0xe41e, 0x1460, 0xe41e, 0x1459, 0xe41e, 0x0951, 0xf44e, 0xe16b,
+	0xe42e, 0xe41e, 0x0b72, 0xf0da, 0xa102, 0xe40a, 0x0412, 0xa108,
+	0xf084, 0xf11a, 0xa108, 0xf0f6, 0xa102, 0xf06a, 0xa102, 0xf04a,
+	0xe41e, 0x0951, 0xf6fe, 0xe41e, 0x08bd, 0xe408, 0x0412, 0xe41e,
+	0x098a, 0xf68e, 0xe42e, 0xa200, 0xe161, 0x0100, 0xe188, 0x0aff,
+	0x3d11, 0xe0c0, 0x0041, 0xe005, 0x0034, 0xae11, 0xe042, 0xce20,
+	0xd111, 0x0100, 0xd112, 0x0180, 0xd113, 0x0002, 0xca28, 0xf7f8,
+	0xe42e, 0xe41e, 0x0413, 0xe41e, 0x0222, 0xe41e, 0x0148, 0xa204,
+	0x3cae, 0xe16a, 0xd130, 0x0000, 0xd03a, 0x0000, 0xd04c, 0x0000,
+	0xd008, 0x0000, 0xd022, 0x0000, 0xa200, 0xe0c2, 0x0100, 0xe0c2,
+	0x0128, 0xa2fe, 0x3c25, 0x3c26, 0x3c27, 0x3c28, 0x3c10, 0x3c29,
+	0x3c56, 0xe161, 0x05c7, 0x3511, 0x3d11, 0x3511, 0x3d11, 0xe41e,
+	0x0c2b, 0xe41e, 0x1a88, 0xe41e, 0x1f23, 0xe41e, 0x1607, 0xe42e,
+	0xa200, 0x3c86, 0xe41e, 0x0686, 0xe41e, 0x1a4b, 0xe41e, 0x04df,
+	0xe41e, 0x090e, 0xe41e, 0x067b, 0xe41e, 0x052f, 0xe40a, 0x04dc,
+	0xe41e, 0x1382, 0xe408, 0x0472, 0xe41e, 0x08bd, 0xe408, 0x04dc,
+	0xe40e, 0x04c3, 0xe41e, 0x020f, 0xe404, 0x04c3, 0xe41e, 0x067b,
+	0xa202, 0x3c86, 0x28bd, 0xf09a, 0xe41e, 0x0672, 0xa2fe, 0x3c84,
+	0xa202, 0x3cb4, 0xe40e, 0x04c3, 0x28a4, 0xf0b4, 0xa202, 0x3cb4,
+	0xe41e, 0x1460, 0xe41e, 0x0672, 0xa200, 0x3c3a, 0xe40e, 0x04c3,
+	0xe41e, 0x05d4, 0xf05a, 0xe41e, 0x05f3, 0xe40e, 0x04b5, 0xe41e,
+	0x1a7d, 0x2884, 0xe414, 0x0672, 0x2884, 0xe404, 0x04c3, 0x2884,
+	0xe41e, 0x1f8e, 0xe41e, 0x20e9, 0xe41e, 0x05c7, 0x28a5, 0xf0e8,
+	0x2a4e, 0x4e40, 0x2884, 0xe41b, 0x1f29, 0x284e, 0xe418, 0x1bc2,
+	0x2840, 0xe41a, 0x18cf, 0x287e, 0x3c82, 0x2840, 0xf058, 0xe41e,
+	0x0655, 0xe41e, 0x065a, 0xe41e, 0x065f, 0x2840, 0xaa02, 0x443f,
+	0xf03a, 0xe40e, 0x0468, 0xe41e, 0x20d0, 0xe41e, 0x1460, 0xe41e,
+	0x08d7, 0xf04a, 0xe41e, 0x19fe, 0x3ce9, 0xe41e, 0x18f8, 0x3c85,
+	0x2885, 0x3c56, 0x2884, 0xf024, 0x3c83, 0xe41e, 0x06f6, 0xe41e,
+	0x1a66, 0xe41e, 0x0b38, 0xe42e, 0xa202, 0x3c86, 0xf65e, 0xa200,
+	0xcc4a, 0xcc4c, 0x3c53, 0x3c62, 0x3cbd, 0x3cae, 0x3cb4, 0x3ca5,
+	0x3c97, 0x28ad, 0xe41a, 0x064c, 0xe41e, 0x0655, 0xe41e, 0x065a,
+	0xe41e, 0x065f, 0xa2fe, 0x3cba, 0x3cbb, 0x3cb9, 0xa200, 0x3cbc,
+	0xa2fe, 0x3ca4, 0xa204, 0x3cf0, 0xa2fc, 0x3c84, 0xa2fa, 0x3c85,
+	0xa2fe, 0xc009, 0x3c3f, 0x3c40, 0x3c41, 0x3c42, 0xc000, 0xe42e,
+	0x2811, 0xa184, 0xf068, 0x2824, 0xa804, 0xf038, 0xa202, 0xe42e,
+	0xa200, 0xe42e, 0xa200, 0xcc44, 0xd152, 0x0000, 0xd130, 0x0000,
+	0xd1e0, 0x0003, 0xd1ff, 0x03b0, 0xd1fd, 0x03d0, 0xd199, 0x0224,
+	0xd1fc, 0x0720, 0xd03a, 0x0000, 0xd04c, 0x0000, 0xd008, 0x0000,
+	0xd14b, 0x0200, 0x28b1, 0xcfce, 0xe41e, 0x025f, 0xe42e, 0xe0c0,
+	0x0059, 0xa102, 0xf0da, 0xe41e, 0x08bd, 0xf04a, 0xe41e, 0x01db,
+	0xf09e, 0xe41e, 0x1f66, 0x2a84, 0xb7f5, 0x3e84, 0xf03a, 0xa202,
+	0xe42e, 0xa200, 0xe42e, 0xe41e, 0x0686, 0xe41e, 0x207b, 0xe42e,
+	0xe0c0, 0x0042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0080, 0xd113,
+	0x0013, 0xca28, 0xf7f8, 0xe0c0, 0x0061, 0xe41e, 0x0c09, 0xa202,
+	0xe41e, 0x0c13, 0xe41e, 0x0a10, 0xe128, 0xe0c0, 0x0060, 0xf048,
+	0xe41e, 0x1a99, 0xf03e, 0xe41e, 0x1ac4, 0xe42e, 0xe0c0, 0x0040,
+	0xa201, 0xae17, 0xe042, 0xe005, 0x4f00, 0xae03, 0xe042, 0xce20,
+	0xd111, 0x0450, 0xd112, 0x00c8, 0xd113, 0x0003, 0xca28, 0xf7f8,
+	0xe42e, 0xe180, 0xa2fe, 0x3c29, 0x3c10, 0xe41e, 0x1f23, 0xe41e,
+	0x05b7, 0x2821, 0xf05a, 0x2816, 0xa104, 0xf02a, 0x28ea, 0x3ce9,
+	0xa200, 0x3c81, 0x3ce7, 0x3ce6, 0x3ce8, 0x3ce5, 0xe166, 0x05ab,
+	0xc710, 0x3d16, 0xe167, 0x0518, 0xe166, 0x0054, 0xa200, 0x3cb2,
+	0x287f, 0xa102, 0xcc44, 0xe184, 0x05a4, 0x9e06, 0x5cb2, 0xa802,
+	0xb690, 0x3d17, 0x28b2, 0xa002, 0x3cb2, 0xe190, 0xa200, 0x3c60,
+	0xe41e, 0x0c40, 0xe42e, 0x24b5, 0x4cb6, 0xce20, 0xd111, 0x0600,
+	0xd112, 0x0004, 0xd113, 0x0000, 0xca28, 0xf7f8, 0xe42e, 0xe161,
+	0x0200, 0xa200, 0xc73f, 0x3d11, 0x3cb2, 0xd022, 0x001f, 0xe184,
+	0x05c5, 0xe41e, 0x1f29, 0x28b2, 0xa002, 0x3cb2, 0xe42e, 0x2abc,
+	0x4e4f, 0x3ebc, 0x28a1, 0x3cb9, 0x2a3f, 0xf06b, 0x2a42, 0xf039,
+	0x3cba, 0xf02e, 0x3cbb, 0xe42e, 0x28a5, 0xf1c8, 0x28a5, 0xe016,
+	0x4440, 0xf168, 0xe41e, 0x0634, 0xf07a, 0xe41e, 0x0639, 0xf07a,
+	0x284f, 0xf0e8, 0xf0fe, 0xe41e, 0x063e, 0xf04a, 0x2838, 0xf0a8,
+	0xf07e, 0xe41e, 0x0645, 0xf04a, 0x284e, 0xf04a, 0xf01e, 0xa200,
+	0xe42e, 0xa202, 0xe42e, 0xa202, 0x3ca5, 0x2884, 0xe412, 0x1f29,
+	0x2884, 0xe412, 0x1f30, 0x2884, 0xe412, 0x1f37, 0xa2fc, 0x3c84,
+	0x3c3e, 0xe41e, 0x0608, 0xe41e, 0x0b21, 0xe41e, 0x090e, 0xe42e,
+	0xe41e, 0x0b72, 0xf15a, 0xa102, 0xf17a, 0xa108, 0xf114, 0xf14a,
+	0xa102, 0xf0da, 0xa102, 0xf0ba, 0xa102, 0xf09a, 0xa102, 0xf07a,
+	0xa104, 0xf056, 0xa102, 0xf04a, 0xa10e, 0xf022, 0xe42e, 0xe41e,
+	0x0951, 0xe40e, 0x0608, 0xcaa2, 0xaf0a, 0xa806, 0x184e, 0xf0a8,
+	0xe41e, 0x098a, 0xe41e, 0x22e7, 0xf5ca, 0x2894, 0xf5aa, 0xe41e,
+	0x0b69, 0xe41e, 0x0b21, 0xe42e, 0xe0c0, 0x0065, 0xaf04, 0xa802,
+	0xe42e, 0xe0c0, 0x0065, 0xaf16, 0xa802, 0xe42e, 0xe0c0, 0x0065,
+	0xaf06, 0xa806, 0xa102, 0xe016, 0xe42e, 0xe0c0, 0x0065, 0xaf06,
+	0xa806, 0xa104, 0xe016, 0xe42e, 0xe41e, 0x0b21, 0xe0c0, 0x0048,
+	0xc009, 0x3433, 0x3c34, 0xc000, 0xe42e, 0xc009, 0x2433, 0x4c34,
+	0xc000, 0xe42e, 0xc009, 0x3435, 0x3c36, 0xc000, 0xe42e, 0xe41e,
+	0x0b21, 0xe0c0, 0x0048, 0xc009, 0x3437, 0x3c38, 0xc000, 0xe42e,
+	0xc009, 0x2435, 0x4c36, 0xc000, 0xe42e, 0xc009, 0x2437, 0x4c38,
+	0xc000, 0xe42e, 0xe41e, 0x0b69, 0x28ad, 0xe42a, 0xe41e, 0x0655,
+	0xe0c2, 0x0048, 0xe42e, 0xe41e, 0x1fed, 0xe41e, 0x2020, 0xe41e,
+	0x0512, 0xe41e, 0x247d, 0xe41e, 0x2080, 0xe42e, 0xe0c0, 0x0059,
+	0xa102, 0xf2ca, 0xa102, 0xe42a, 0xa102, 0xf05a, 0xa102, 0xe40a,
+	0x06cc, 0xe42e, 0xe0c0, 0x006b, 0x34b5, 0x3cb6, 0xe0c0, 0x006c,
+	0x34b7, 0x3cb8, 0xe0c0, 0x0060, 0xaf08, 0x3088, 0xe0c0, 0x0060,
+	0xa81e, 0x3c87, 0xe0c0, 0x0061, 0xa83e, 0x3c8a, 0xe0c0, 0x0065,
+	0xa840, 0xf0ba, 0xa200, 0xe167, 0x0600, 0xc703, 0x3d17, 0xe41e,
+	0x05ab, 0xe004, 0x0088, 0x3ca7, 0xe42e, 0xc001, 0xe0c0, 0x0060,
+	0x3400, 0x3c01, 0xe0c0, 0x0061, 0xae14, 0x3406, 0x3c07, 0xc000,
+	0xe0c0, 0x0062, 0xaf02, 0x3021, 0xaf02, 0x30aa, 0xa200, 0xe0c0,
+	0x0067, 0xa802, 0x3cb1, 0xe42e, 0xe41e, 0x038c, 0xe41e, 0x0174,
+	0xe0c0, 0x0042, 0xce20, 0xd111, 0x0640, 0xd112, 0x00c0, 0xd113,
+	0x0003, 0xca29, 0xf7f9, 0xa200, 0xe41e, 0x0f91, 0xe004, 0x0040,
+	0xe41e, 0x0f91, 0xe0c0, 0x0060, 0x3c7f, 0xe0c0, 0x0061, 0x3c66,
+	0xe0c0, 0x006e, 0xe41e, 0x020a, 0xe167, 0x05fd, 0xe0c0, 0x0062,
+	0x3517, 0x3d17, 0xe0c0, 0x0063, 0x3d17, 0xe42e, 0xe0c0, 0x0059,
+	0xa102, 0xe40a, 0x0797, 0xa102, 0xe42a, 0xa102, 0xf05a, 0xa102,
+	0xe40a, 0x0804, 0xe42e, 0x2861, 0xae04, 0x4c91, 0xae02, 0x4c90,
+	0xe0c2, 0x0060, 0xc009, 0x203f, 0x4c40, 0xe0c2, 0x0061, 0x2041,
+	0x4c42, 0xc000, 0xe0c2, 0x0062, 0xe41e, 0x1612, 0xe0c2, 0x0067,
+	0xe41e, 0x1617, 0xe0c2, 0x0068, 0xe41e, 0x161c, 0xe0c2, 0x0069,
+	0xe41e, 0x1607, 0x2a23, 0xe41b, 0x0846, 0x2a3f, 0xe419, 0x0846,
+	0xae02, 0x4c23, 0xe0c2, 0x006a, 0x283f, 0xf0ba, 0xc009, 0x203b,
+	0x4c3c, 0xe0c2, 0x006b, 0x203d, 0x4c3e, 0xe0c2, 0x006c, 0xc000,
+	0x2072, 0x4c73, 0xe0c2, 0x006c, 0xe41e, 0x1463, 0xe0c2, 0x007b,
+	0x2057, 0x4c58, 0xae08, 0xe0c2, 0x006f, 0x28b0, 0xe0c2, 0x007a,
+	0x2054, 0x4c55, 0xa002, 0x3454, 0x3c55, 0xe0c2, 0x0070, 0x2885,
+	0xe0c2, 0x0071, 0x2c53, 0xe0c2, 0x0072, 0xe41e, 0x0805, 0xe0c2,
+	0x0073, 0xa200, 0xe0c2, 0x0074, 0x2886, 0x2ab4, 0xae21, 0xe056,
+	0x2aae, 0xae23, 0xe056, 0x2abd, 0xae29, 0xe056, 0xe0c2, 0x0076,
+	0xe41e, 0x0668, 0xe0c2, 0x0051, 0xe41e, 0x066d, 0xe0c2, 0x0052,
+	0x2884, 0xe0c2, 0x0077, 0x2a22, 0xe161, 0x05e4, 0x2111, 0x4d11,
+	0xf02b, 0xae02, 0xe0c2, 0x0078, 0x2111, 0x4d11, 0xf02b, 0xae02,
+	0xe0c2, 0x0079, 0x2025, 0x4c26, 0xe0c2, 0x007c, 0xe167, 0x05c7,
+	0x2117, 0x4d17, 0xe0c2, 0x007e, 0x2117, 0x4d17, 0xe0c2, 0x007d,
+	0xc84a, 0xc84d, 0xae20, 0xe056, 0xe0c2, 0x0053, 0xe42e, 0xe41e,
+	0x1463, 0xe0c2, 0x0063, 0x2a23, 0xe41b, 0x0846, 0x2a3f, 0xe419,
+	0x0846, 0xae02, 0x4c23, 0xe0c2, 0x0064, 0x2027, 0x4c28, 0xe0c2,
+	0x006d, 0x2886, 0xe0c2, 0x0070, 0x2057, 0x4c58, 0xae08, 0xe0c2,
+	0x0071, 0x2025, 0x4c26, 0xe0c2, 0x0072, 0x2821, 0xf0ca, 0x2816,
+	0xa104, 0xf09a, 0x28eb, 0x3cb3, 0xa004, 0xe0c2, 0x0073, 0x28ea,
+	0x3ce9, 0xf07e, 0x2819, 0xa004, 0xe0c2, 0x0073, 0xa200, 0x3ce9,
+	0x28e9, 0xe0c2, 0x0074, 0xa200, 0xe0c2, 0x0075, 0x2a22, 0xe161,
+	0x05e4, 0x2111, 0x4d11, 0xf02b, 0xae02, 0xe0c2, 0x0076, 0x2111,
+	0x4d11, 0xf02b, 0xae02, 0xe0c2, 0x0077, 0x2886, 0xe016, 0x58f0,
+	0xe0c2, 0x0078, 0xe161, 0x05c7, 0x2111, 0x4d11, 0xe0c2, 0x007a,
+	0x2111, 0x4d11, 0xe0c2, 0x0079, 0xe41e, 0x1463, 0xaf32, 0xa802,
+	0xae0c, 0x2a24, 0xae05, 0xe056, 0x4c1d, 0xae02, 0x2a1b, 0xe017,
+	0xe056, 0xae10, 0x4c1f, 0xae10, 0x4c11, 0x2a19, 0xe01b, 0xae3f,
+	0xe056, 0xe0c2, 0x007b, 0xe42e, 0xe42e, 0x2885, 0xe41e, 0x25f3,
+	0xe092, 0x2842, 0xe016, 0x5440, 0x443f, 0x3c00, 0xa200, 0x2a40,
+	0xf079, 0x2aa4, 0xf053, 0x2ab9, 0xa80f, 0xe056, 0xf12e, 0x2a00,
+	0xf09b, 0x2aba, 0xa80f, 0xae07, 0xe056, 0x2abb, 0xa80f, 0xe056,
+	0xf08e, 0x2abb, 0xa80f, 0xae07, 0xe056, 0x2aba, 0xa80f, 0xe056,
+	0x3c01, 0x28a3, 0x2a23, 0xe41b, 0x0846, 0x2a3f, 0xe419, 0x0846,
+	0xae02, 0x4c23, 0xae0c, 0x4c00, 0xae04, 0x4c43, 0xae02, 0x4c3f,
+	0xae24, 0x2a3f, 0xe017, 0x4e40, 0xae1f, 0xe056, 0xe083, 0xae21,
+	0xe056, 0x2abc, 0xae0d, 0xe056, 0x4c01, 0xe42e, 0x283f, 0xe42a,
+	0x28a4, 0xf0c2, 0xc009, 0x203b, 0x4c3c, 0x103d, 0x1c3e, 0xc000,
+	0xf030, 0xa206, 0xe42e, 0xa208, 0xe42e, 0x2823, 0xf048, 0xa202,
+	0x0842, 0xe42e, 0x28a3, 0xe42e, 0x3cec, 0xe0c0, 0x0041, 0xe005,
+	0x0018, 0xae11, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0100,
+	0x88ec, 0x0113, 0xca28, 0xf7f8, 0xe42e, 0x8917, 0x0034, 0x8917,
+	0x0033, 0x8917, 0x0035, 0x8917, 0x0036, 0x8917, 0x0037, 0x8917,
+	0x0038, 0x8117, 0x8117, 0x2117, 0x4d17, 0xcc60, 0x2117, 0x4d17,
+	0xcc62, 0x2117, 0x4d17, 0xcc64, 0x2117, 0x4d17, 0xcc72, 0xe42e,
+	0x8b17, 0x0034, 0x8b17, 0x0033, 0x8b17, 0x0035, 0x8b17, 0x0036,
+	0x8b17, 0x0037, 0x8b17, 0x0038, 0x8117, 0x8117, 0xc860, 0x3517,
+	0x3d17, 0xc862, 0x3517, 0x3d17, 0xc864, 0x3517, 0x3d17, 0xc872,
+	0x3517, 0x3d17, 0xe42e, 0xc001, 0x3c13, 0xc000, 0xe42e, 0xc001,
+	0x2813, 0xc000, 0xe42e, 0xc001, 0x3c14, 0xc000, 0xe42e, 0xc001,
+	0x2814, 0xc000, 0xe42e, 0xc001, 0x2430, 0x4c31, 0xc000, 0xae06,
+	0xc873, 0xe046, 0xe422, 0xe16b, 0xe42e, 0xc001, 0x280c, 0xf16a,
+	0xe41e, 0x0b21, 0xc001, 0xe0c0, 0x0049, 0x340e, 0x3c0f, 0x240e,
+	0x4c0f, 0xe0c1, 0x0048, 0x360e, 0x3e0f, 0x260e, 0x4e0f, 0xe045,
+	0xa200, 0xb626, 0xe003, 0x0200, 0xb606, 0xc000, 0xe42e, 0xe41e,
+	0x08bd, 0xe42a, 0xe0c0, 0x0045, 0xaf04, 0xa802, 0xe42e, 0xc001,
+	0x3c33, 0xc000, 0xe42e, 0xc001, 0x2833, 0xc000, 0xe42e, 0xc001,
+	0x3c11, 0xc000, 0xe42e, 0xc001, 0x2811, 0xc000, 0xe42e, 0xd148,
+	0x0040, 0xd144, 0x0000, 0xd145, 0x0000, 0xd168, 0x0000, 0xd16b,
+	0x0000, 0xd14b, 0x0200, 0xe004, 0x0019, 0xae18, 0xcec0, 0xd14c,
+	0x000c, 0xca9a, 0xf7f8, 0xe42e, 0xc001, 0x2400, 0x4c01, 0x0406,
+	0x0c07, 0x3408, 0x3c09, 0xd071, 0x202a, 0xe181, 0xc001, 0xe0c0,
+	0x0048, 0x3415, 0x3c16, 0x280c, 0xf13a, 0xe0c0, 0x0048, 0x340e,
+	0x3c0f, 0x240e, 0x4c0f, 0xe0c1, 0x0049, 0x3604, 0x3e05, 0x1404,
+	0x1c05, 0xe0c1, 0x0045, 0xaf05, 0xa803, 0xb611, 0x320c, 0xe0c0,
+	0x0048, 0x3402, 0xe008, 0xfe00, 0x3c03, 0xe0c0, 0x0048, 0xe008,
+	0x01ff, 0x3c0b, 0xa200, 0xcc78, 0xd022, 0x00ff, 0xe184, 0x0939,
+	0xcc7a, 0xe190, 0xe41e, 0x0a10, 0xe41e, 0x0a2f, 0xe41e, 0x08ef,
+	0xc001, 0xa200, 0x3c1a, 0x280b, 0xa102, 0xe412, 0x0959, 0xc001,
+	0xa202, 0x3c1a, 0xa200, 0xceaa, 0xc000, 0xa200, 0xe41e, 0x0c40,
+	0xe42e, 0xcaa0, 0xe190, 0xca9a, 0xf7f8, 0xca9c, 0xe418, 0x0a2f,
+	0xe42e, 0xcc44, 0xe184, 0x0962, 0xca9c, 0xe418, 0x0a2f, 0xcaa0,
+	0xca9b, 0xf7f9, 0xe190, 0xe42e, 0xe004, 0x0100, 0xceb0, 0xe004,
+	0x00ff, 0xe014, 0xceb8, 0xd15d, 0x0000, 0xd15e, 0x0000, 0xd15f,
+	0x0000, 0xe004, 0x0019, 0xae18, 0xe00a, 0x0620, 0xcec0, 0xd157,
+	0x0000, 0xd14a, 0x0000, 0xd14c, 0x0003, 0xca9c, 0xe418, 0x0a2f,
+	0xca9a, 0xf7c8, 0xcaae, 0xa802, 0xf73a, 0xca9c, 0xe418, 0x0a2f,
+	0xa200, 0xe42e, 0xe41e, 0x0964, 0xe41e, 0x08bd, 0xf128, 0xe41e,
+	0x0b60, 0xcaa2, 0xe008, 0x00ff, 0xe41e, 0x08a3, 0xaf0e, 0xe418,
+	0x0951, 0xe41e, 0x08a7, 0xaf0e, 0xf6e8, 0xe41e, 0x08bd, 0xf0ea,
+	0xe004, 0x010b, 0xe008, 0x00ff, 0xe41e, 0x08a3, 0xe004, 0x010b,
+	0xa83e, 0xe41e, 0x08ab, 0xa200, 0xe42e, 0xe41e, 0x08a7, 0xf058,
+	0xa204, 0xe41e, 0x0959, 0xf57e, 0xa206, 0xe41e, 0x0959, 0xe41e,
+	0x08a7, 0xaf0a, 0x3c4e, 0xe41e, 0x08a7, 0xa83e, 0xe41e, 0x08ab,
+	0xe41e, 0x08a7, 0xa116, 0xe42a, 0xca9c, 0xe418, 0x0a2f, 0x2a51,
+	0xf06b, 0xe41e, 0x08af, 0xa10a, 0xe016, 0x3c4f, 0xe41e, 0x09d1,
+	0xe42e, 0xc001, 0xa200, 0x3c30, 0x3c31, 0x3c33, 0xe41e, 0x09df,
+	0xc001, 0xe41e, 0x0a10, 0xc001, 0xe128, 0xc000, 0xe42e, 0xc001,
+	0x2833, 0x4411, 0xc000, 0xae0e, 0xce92, 0xd14a, 0x0000, 0xd158,
+	0x0000, 0xe004, 0x01ff, 0xe014, 0xceb8, 0xd15d, 0x0000, 0xd15e,
+	0x0000, 0xd15f, 0x0000, 0xd161, 0x0003, 0xe004, 0x0019, 0xae18,
+	0xe00a, 0x0638, 0xcec0, 0xd14c, 0x0003, 0xca9c, 0xe418, 0x0a2f,
+	0xca9a, 0xf7c8, 0xca9c, 0xf7a8, 0xca9e, 0xc001, 0x3c32, 0xcc92,
+	0xca94, 0x0030, 0x0c31, 0x3430, 0x3c31, 0xcc90, 0xc000, 0xe42e,
+	0xe004, 0x1495, 0xae20, 0xcc9e, 0xd030, 0x0000, 0xd034, 0x0000,
+	0xd033, 0x0000, 0xd035, 0x0000, 0xd036, 0x007f, 0xd037, 0x0000,
+	0xd038, 0x0000, 0xd039, 0x0000, 0xd04b, 0x0001, 0xd04c, 0x0000,
+	0xd046, 0x0000, 0xd047, 0x0000, 0xd149, 0x0000, 0xe42e, 0xc001,
+	0x280c, 0xf20a, 0xe41e, 0x024f, 0xc001, 0xe004, 0x0440, 0xce50,
+	0x280d, 0xa806, 0xa108, 0xe012, 0xa806, 0xae06, 0x3c40, 0xe004,
+	0x010b, 0x5840, 0xce52, 0xe41e, 0x0257, 0xc001, 0xd14e, 0x0000,
+	0xd144, 0x0000, 0x2402, 0x4c03, 0xe000, 0x0200, 0x3402, 0x3c03,
+	0xf3ae, 0xd027, 0x0000, 0x280c, 0xe41a, 0x0a98, 0xc001, 0xd027,
+	0x0001, 0x280d, 0xf25a, 0xca48, 0xa802, 0xf7e8, 0x2402, 0x4c03,
+	0xce40, 0xd121, 0x0000, 0xd122, 0x0040, 0xe0c0, 0x0043, 0xa806,
+	0xae02, 0xa032, 0xce46, 0xe190, 0xe190, 0xe190, 0xe190, 0xca48,
+	0xa802, 0xf7e8, 0xe004, 0x0200, 0x0402, 0x0c03, 0x3402, 0x3c03,
+	0x1408, 0x1c09, 0xf054, 0x2400, 0x4c01, 0x3402, 0x3c03, 0x280c,
+	0xe418, 0x0adc, 0xc001, 0xe41e, 0x0b21, 0xc001, 0xd14e, 0x0000,
+	0xd144, 0x0000, 0xc000, 0xe42e, 0xe0c1, 0x0059, 0xa103, 0xa200,
+	0xb636, 0xe000, 0x001c, 0xe0c1, 0x0045, 0xe052, 0xe01a, 0xe42e,
+	0xc001, 0xa200, 0x3c0a, 0xe004, 0x0200, 0x3c0d, 0xe0c0, 0x0043,
+	0xa808, 0xf338, 0xe41e, 0x0a8c, 0xc001, 0x3c0c, 0x2402, 0x4c03,
+	0xe0c1, 0x0049, 0x3604, 0x3e05, 0x2604, 0x4e05, 0xe045, 0xf033,
+	0x0606, 0x0e07, 0xe003, 0x0200, 0x280c, 0xb602, 0x3c0c, 0xf1d3,
+	0xe001, 0x0200, 0x3e0d, 0x280c, 0xf188, 0x280a, 0xe408, 0x0aa2,
+	0xe41e, 0x01db, 0xc001, 0xe0c0, 0x005c, 0xe008, 0x4000, 0xe40a,
+	0x0aa2, 0xe0c0, 0x005d, 0xe00a, 0x4000, 0xe0c2, 0x005d, 0xa202,
+	0xce00, 0x3c0a, 0xe40e, 0x0aa2, 0x280d, 0x2a0c, 0xf039, 0xe004,
+	0x0200, 0x3c0d, 0xc000, 0xe42e, 0xc001, 0xe41e, 0x024f, 0xc001,
+	0x280d, 0xe002, 0x0200, 0xe40a, 0x0b1e, 0x280d, 0xa806, 0xf1fa,
+	0xa108, 0xe012, 0xae06, 0x3c40, 0x280d, 0xaf04, 0xae20, 0xe000,
+	0x01c0, 0xce50, 0xe190, 0xca52, 0x5c40, 0x5840, 0x2a0d, 0xa807,
+	0xae07, 0x3e40, 0xe005, 0x010b, 0x5e40, 0xe056, 0x2a0d, 0xaf05,
+	0xae21, 0xe001, 0x0140, 0xce51, 0xe190, 0xce52, 0xe004, 0x01fc,
+	0x180d, 0xf022, 0xf14e, 0xc001, 0x280d, 0xa006, 0xaf04, 0xae20,
+	0xe000, 0x0440, 0xce50, 0x280d, 0xa806, 0xa108, 0xe012, 0xa806,
+	0xae06, 0x3c40, 0xe004, 0x010b, 0x5840, 0xce52, 0xc000, 0xe40e,
+	0x0257, 0xc001, 0xcaaa, 0x2a1a, 0xb616, 0xe0c1, 0x0048, 0x360e,
+	0x3e0f, 0x260e, 0x4e0f, 0xe042, 0xe049, 0x1608, 0x1e09, 0xf035,
+	0x1406, 0x1c07, 0xe0c2, 0x0048, 0xa200, 0xceaa, 0xc000, 0xe42e,
+	0xe41e, 0x0b21, 0xe0c0, 0x0045, 0xaf04, 0xa806, 0xa104, 0xe428,
+	0xa2fc, 0x2a84, 0xa003, 0xb616, 0xe418, 0x0b47, 0xe42e, 0xc001,
+	0x3c40, 0xe0c0, 0x0048, 0x340e, 0x3c0f, 0x240e, 0x4c0f, 0x0840,
+	0xe049, 0x1600, 0x1e01, 0xf033, 0x0406, 0x0c07, 0xe049, 0x1608,
+	0x1e09, 0xf035, 0x1406, 0x1c07, 0xe0c2, 0x0048, 0xc000, 0xe42e,
+	0xe41e, 0x0b21, 0xc001, 0xe0c0, 0x0048, 0x3417, 0x3c18, 0xc000,
+	0xe42e, 0xa200, 0xceaa, 0xc001, 0x2417, 0x4c18, 0xc000, 0xe0c2,
+	0x0048, 0xe42e, 0xe41e, 0x0964, 0xe41e, 0x08bd, 0xf0f8, 0xcaa2,
+	0xe049, 0xa83e, 0xe009, 0x00ff, 0xf03b, 0xaf0f, 0xf04b, 0xe41e,
+	0x0951, 0xf71e, 0xe41e, 0x08bd, 0xf0aa, 0xe004, 0x010b, 0xe008,
+	0x00ff, 0xe41e, 0x08a3, 0xe004, 0x010b, 0xf02e, 0xcaa2, 0xe008,
+	0x001f, 0xe41e, 0x08ab, 0xe41e, 0x08af, 0xe42e, 0xc001, 0x2832,
+	0xe016, 0xc871, 0xa011, 0xf288, 0xaf07, 0xe009, 0x07ff, 0x2831,
+	0xe008, 0x07ff, 0xe046, 0xf16a, 0xf0ee, 0xc001, 0xe161, 0x0601,
+	0x2901, 0xc871, 0xa011, 0xaf07, 0xe009, 0x07ff, 0xe008, 0x07ff,
+	0xe046, 0xf08a, 0xe049, 0xe011, 0xaf15, 0xf0e1, 0xf0d0, 0xa200,
+	0xf0be, 0xc868, 0xa80e, 0xf028, 0xa210, 0x3c35, 0x7835, 0xa203,
+	0x5a35, 0xaf03, 0xe046, 0xc000, 0xe42e, 0xc000, 0x284e, 0x2a4f,
+	0x3c95, 0x3e96, 0xc001, 0x2831, 0x2a32, 0x3c36, 0x3e37, 0xe0c0,
+	0x0046, 0xe005, 0x0000, 0xae11, 0xe042, 0xce20, 0xd111, 0x0000,
+	0xd112, 0x0080, 0xd113, 0x0012, 0xca28, 0xf7f8, 0xca2c, 0xf7fa,
+	0xc000, 0xe42e, 0xc000, 0x2895, 0x2a96, 0x3c4e, 0x3e4f, 0xc001,
+	0x2836, 0x2a37, 0x3c31, 0x3e32, 0xcc90, 0xcc93, 0xa200, 0x3c30,
+	0x3c33, 0xe0c0, 0x0046, 0xe005, 0x0000, 0xae11, 0xe042, 0xce20,
+	0xd111, 0x0000, 0xd112, 0x0080, 0xd113, 0x0013, 0xca28, 0xf7f8,
+	0xe41e, 0x0a10, 0xe128, 0xc000, 0xe42e, 0xc001, 0x2834, 0xc000,
+	0xe42e, 0xc001, 0x3430, 0x3c31, 0xc000, 0xe42e, 0xc001, 0x2430,
+	0x4c31, 0xc000, 0xe42e, 0xc001, 0x3c32, 0xc000, 0xe42e, 0xc001,
+	0x2832, 0xc000, 0xe42e, 0xc001, 0x3c10, 0xc000, 0xe42e, 0xc001,
+	0x2810, 0xc000, 0xe42e, 0xc001, 0x3c38, 0xc000, 0xe42e, 0xc001,
+	0x2838, 0xc000, 0xe42e, 0xc001, 0xe0c0, 0x0041, 0xe005, 0x0039,
+	0xae11, 0xe042, 0x3420, 0x3c21, 0xe004, 0x04e1, 0xae10, 0x3422,
+	0x3c23, 0xc000, 0xe42e, 0xc001, 0x2420, 0x4c21, 0xc000, 0xe42e,
+	0x3c63, 0xe08e, 0x3c64, 0xe41e, 0x0c4c, 0xe41e, 0x0c54, 0x2864,
+	0xe09e, 0x2863, 0x3c60, 0xe42e, 0x2860, 0xae08, 0xe000, 0x0538,
+	0xe09e, 0xe41e, 0x0888, 0xe42e, 0x2863, 0xae08, 0xe000, 0x0538,
+	0xe09e, 0xe41e, 0x086d, 0xe42e, 0x2860, 0xe408, 0x1afb, 0xe41e,
+	0x0c17, 0xf1b8, 0xe41e, 0x08e3, 0xf068, 0xe41e, 0x09df, 0xd04c,
+	0x0000, 0xe470, 0xc896, 0xf05a, 0xe41e, 0x0c7f, 0xd04c, 0x0000,
+	0xe41e, 0x08eb, 0xe005, 0x0080, 0xb615, 0xcc6f, 0xd04b, 0x0001,
+	0xa202, 0xe41e, 0x0c1b, 0xe470, 0xd04c, 0x0000, 0xe470, 0xc001,
+	0xa200, 0x3c10, 0xe41e, 0x09df, 0xc001, 0x2832, 0xcc96, 0x2811,
+	0xe016, 0x3c11, 0xc000, 0xe42e, 0xba0c, 0xf03a, 0xbcfc, 0xe42e,
+	0xba4c, 0xa20c, 0x3c9d, 0x289d, 0xa002, 0x3c9d, 0xa140, 0xf0d2,
+	0xba40, 0xf7aa, 0x589d, 0xa102, 0x34ab, 0x3cac, 0x289d, 0xe41e,
+	0x0cc9, 0x00ab, 0x0cac, 0xe42e, 0xe16b, 0xe42e, 0xba0c, 0xf03a,
+	0xbe7e, 0xe42e, 0xba4c, 0xa20c, 0x3c9d, 0x289d, 0xa002, 0x3c9d,
+	0xa140, 0xf162, 0xba40, 0xf7aa, 0x589d, 0xa102, 0x34ab, 0x3cac,
+	0x289d, 0xe41e, 0x0cc9, 0x00ab, 0x0cac, 0x3cac, 0x8cac, 0x0000,
+	0xa002, 0xaf02, 0xe012, 0xe42c, 0xe012, 0xe16a, 0xe42e, 0xe16b,
+	0xe42e, 0xa120, 0xf050, 0xa020, 0x3c9e, 0x749e, 0xe42e, 0x3c9e,
+	0xba5e, 0x589e, 0x769e, 0xe056, 0xe42e, 0xba40, 0xe42a, 0xc868,
+	0xa80e, 0x3c00, 0xe016, 0xe428, 0x7400, 0xe016, 0xe42e, 0x2a38,
+	0xa103, 0x282f, 0xe425, 0xf02b, 0x2830, 0xb7f4, 0xa002, 0x3c5e,
+	0xa104, 0xe424, 0xf04a, 0xa25a, 0x3c5f, 0xe42e, 0xbc0e, 0x3c00,
+	0xe42d, 0x2822, 0xf02a, 0xbc0e, 0x3c01, 0xe42d, 0x2801, 0xae06,
+	0x4c00, 0x3c5f, 0xe161, 0x0728, 0xe164, 0x0720, 0x8848, 0x0022,
+	0xe41e, 0x0d10, 0xe42d, 0x2838, 0xa104, 0xe428, 0x2849, 0xe161,
+	0x0788, 0xe164, 0x0724, 0x8849, 0x0022, 0xe41e, 0x0d10, 0xe42e,
+	0xe082, 0xa040, 0xe094, 0xa040, 0xe096, 0xe004, 0x00ff, 0x3c03,
+	0xa200, 0x3c05, 0x3c06, 0x3c07, 0x3c08, 0x3c09, 0xe184, 0x0d5c,
+	0xba40, 0xf0ba, 0xe0c6, 0x0080, 0x4403, 0xae10, 0xe0c7, 0x0080,
+	0x4603, 0xe056, 0x3d11, 0xf0ce, 0xa202, 0x5800, 0xae10, 0x3d11,
+	0x2206, 0x4e07, 0xa202, 0x5805, 0xe056, 0x3406, 0x3c07, 0x2822,
+	0xf22a, 0xba40, 0xf14a, 0xe0c6, 0x0080, 0x4403, 0xae10, 0xe0c7,
+	0x0080, 0x4603, 0xe056, 0x3d12, 0xe0c6, 0x0080, 0x4403, 0xae10,
+	0xe0c7, 0x0080, 0x4603, 0xe056, 0x3d13, 0xf0de, 0xa202, 0x5801,
+	0xae10, 0x3d12, 0x3d13, 0x2208, 0x4e09, 0xa202, 0x5805, 0xe056,
+	0x3408, 0x3c09, 0x2805, 0xa002, 0x3c05, 0x2006, 0x4c07, 0xe014,
+	0x3514, 0x3d14, 0x2208, 0x4e09, 0xe015, 0x3714, 0x3f14, 0xe42e,
+	0xe0c4, 0x3fff, 0xe40d, 0x0e58, 0x3c52, 0xf048, 0xa200, 0xa2fe,
+	0x3ca1, 0x2c52, 0xe01a, 0x4451, 0xe408, 0x0e58, 0xbc12, 0xe40d,
+	0x0e58, 0xa10a, 0xb4a8, 0xa104, 0xe400, 0x0e58, 0xb7b4, 0xa006,
+	0x3c38, 0x60a1, 0x3ca1, 0xbdfe, 0xe40d, 0x0e58, 0x2a51, 0xf09b,
+	0xe049, 0x1829, 0xf06a, 0x3e29, 0xe41e, 0x1adb, 0xe40a, 0x0e58,
+	0x7413, 0x3c39, 0xa200, 0x3c3f, 0x3c42, 0x281b, 0xf068, 0xba40,
+	0x3c3f, 0xf03a, 0xba40, 0x3c42, 0x2851, 0xf2fa, 0x2c1e, 0x5c3f,
+	0x3c44, 0xa200, 0x3c40, 0x283a, 0xf07a, 0xe41e, 0x0e5b, 0x3c40,
+	0xf168, 0x283e, 0x3ca4, 0x283f, 0x3c3a, 0x284e, 0xe01a, 0x3c3b,
+	0x2839, 0x3c3c, 0x2842, 0x3c3d, 0xa2fc, 0x3c3e, 0x284e, 0xf098,
+	0x2850, 0x1c39, 0xf06a, 0xa202, 0x3cbe, 0xf03e, 0xa200, 0x3c3a,
+	0x2c52, 0xf038, 0x2840, 0xf018, 0x283f, 0xe016, 0x441c, 0x3c43,
+	0x283f, 0x0842, 0xb674, 0x3c41, 0x284f, 0xf06a, 0xe41e, 0x0c8c,
+	0xe40d, 0x0e58, 0x3c45, 0xe41e, 0x1865, 0x2835, 0xf07a, 0xe41e,
+	0x0c8c, 0xe40d, 0x0e58, 0xe408, 0x0e58, 0x2838, 0xa104, 0xf038,
+	0xba40, 0x3c46, 0x282c, 0x3c48, 0x282e, 0x3c49, 0x2838, 0xf0ea,
+	0xba40, 0xf0ca, 0xbc3e, 0x3c48, 0xe40d, 0x0e58, 0x2838, 0xa104,
+	0xf058, 0xbc3e, 0x3c49, 0xe40d, 0x0e58, 0x2851, 0xf05a, 0xe41e,
+	0x1baf, 0xe41e, 0x0e77, 0x2838, 0xe016, 0xe41a, 0x0e7e, 0xe40a,
+	0x0e58, 0xe41e, 0x0cdf, 0xe40d, 0x0e58, 0x2851, 0xf06a, 0xe41e,
+	0x172e, 0xe40a, 0x0e58, 0xf1fe, 0x284e, 0xf1da, 0x284f, 0xf04a,
+	0xba40, 0xba40, 0xf18e, 0xba40, 0xf16a, 0xbc0c, 0xe40d, 0x0e58,
+	0xf12a, 0xa106, 0xf08a, 0xa104, 0xf79a, 0xe41e, 0x0c8c, 0xe40d,
+	0x0e58, 0xf74e, 0xe41e, 0x0c8c, 0xe40d, 0x0e58, 0xbc40, 0xe40d,
+	0x0e58, 0xf6ce, 0x2838, 0xe01a, 0x442d, 0xf03a, 0xbc04, 0xf29d,
+	0x3c47, 0xe0c6, 0x0033, 0xf25d, 0x0831, 0xa400, 0xa566, 0x3c4a,
+	0xa200, 0x3c4b, 0x3c4c, 0x3c4d, 0x2833, 0xf10a, 0xbc04, 0xf19d,
+	0x3c4b, 0xa102, 0xf0ba, 0xbe0c, 0xf14d, 0xae02, 0xa83e, 0x3c4c,
+	0xbe0c, 0xf0fd, 0xae02, 0xa83e, 0x3c4d, 0x282b, 0xf01a, 0x2a43,
+	0x2c52, 0xe419, 0x0e70, 0x3c52, 0x1c44, 0xf032, 0xa202, 0xe42e,
+	0xe16a, 0xa200, 0xe42e, 0x284f, 0xe016, 0xe42a, 0x283f, 0xe42a,
+	0x283a, 0xe42a, 0x283d, 0x1842, 0xe42a, 0x284e, 0xf048, 0x283b,
+	0xe016, 0xe42e, 0x283b, 0xe42a, 0x283c, 0x1839, 0xe016, 0xe42e,
+	0xe049, 0xc70f, 0x7e57, 0xaf21, 0xae02, 0xe046, 0xe42e, 0xd1f3,
+	0x0000, 0xe162, 0x0370, 0x2912, 0xcfe4, 0xe42e, 0xe161, 0x0370,
+	0x2838, 0xa102, 0xf03a, 0xe161, 0x0390, 0x2848, 0x3c04, 0xe162,
+	0x02b0, 0xe41e, 0x0ed9, 0xe42a, 0xd1f3, 0x0000, 0xe162, 0x02b0,
+	0x8848, 0x0022, 0xe184, 0x0e95, 0x2912, 0xcfe4, 0x2838, 0xa104,
+	0xe428, 0x2849, 0x3c04, 0xe161, 0x03b0, 0xe162, 0x02d0, 0xe41e,
+	0x0ed9, 0xe42a, 0xd1f3, 0x0020, 0xe162, 0x02d0, 0x8849, 0x0022,
+	0xe184, 0x0eab, 0x2912, 0xcfe4, 0xe41e, 0x0fcc, 0xe162, 0x02d0,
+	0x2902, 0xe41e, 0x0f8a, 0xe41e, 0x0fae, 0x3470, 0x3c71, 0x2902,
+	0xae02, 0xe000, 0x0260, 0xe09e, 0x2117, 0x4d17, 0x2317, 0x4f17,
+	0x1072, 0x1c73, 0x1272, 0x1e73, 0xe010, 0xe011, 0xe046, 0xb624,
+	0xb608, 0x3c7a, 0x2902, 0xe41e, 0x0f83, 0xa102, 0xb628, 0x3c78,
+	0x2902, 0xaf02, 0xe000, 0x02a0, 0xe09e, 0x2907, 0x3c79, 0xa202,
+	0xe42e, 0xe082, 0xe098, 0xba40, 0xf098, 0x8804, 0x0022, 0xe184,
+	0x0ee2, 0x2911, 0x3d12, 0xa202, 0xe42e, 0x286d, 0xe082, 0x3c08,
+	0x2014, 0x4c15, 0x583f, 0x3400, 0x3c01, 0x2c39, 0x583f, 0x083f,
+	0x3402, 0x3c03, 0x2804, 0x3c05, 0xe163, 0x0600, 0xa200, 0xc71f,
+	0x3d13, 0xbc06, 0xe40d, 0x0f44, 0xf06a, 0xa102, 0xf13a, 0xa102,
+	0xf1ba, 0xf31e, 0xe41e, 0x0c8c, 0xe40d, 0x0f44, 0xa002, 0x1002,
+	0x1c03, 0xe012, 0xf032, 0x0000, 0x0c01, 0x3402, 0x3c03, 0xa203,
+	0xf0de, 0xe41e, 0x0c8c, 0xe40d, 0x0f44, 0xa002, 0x0002, 0x0c03,
+	0x1000, 0x1c01, 0xf70e, 0xbc40, 0xa2ff, 0x3c0f, 0xe41e, 0x0f53,
+	0xf082, 0xa203, 0x283f, 0xf03a, 0x2a0f, 0xa803, 0x2904, 0xe046,
+	0x3d12, 0xe41e, 0x0f6e, 0x2805, 0xa102, 0x3c05, 0xa004, 0xe42a,
+	0xe40e, 0x0ef9, 0x2808, 0xa102, 0xe092, 0xe163, 0x0600, 0x2805,
+	0xf0a4, 0x2913, 0x8111, 0xf7e8, 0x2901, 0x3d12, 0x2805, 0xa102,
+	0x3c05, 0xf76e, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0x2884,
+	0xe424, 0xe0c2, 0x020b, 0xe0c2, 0x0214, 0x2884, 0xe41e, 0x0fae,
+	0x346e, 0x3c6f, 0xe42e, 0x3c06, 0x3e07, 0xe163, 0x0330, 0x2819,
+	0xa102, 0xe424, 0xae02, 0xa002, 0xcc44, 0xe184, 0x0f6b, 0x2d13,
+	0x2b0b, 0x1c06, 0x1a07, 0xf078, 0xf069, 0xe086, 0xe002, 0x0330,
+	0xaf02, 0xe42e, 0x8113, 0x8113, 0xa2fe, 0xe42e, 0x3c09, 0x2808,
+	0xe092, 0x286d, 0xa102, 0xcc44, 0xe184, 0x0f79, 0x2901, 0x1809,
+	0xf03a, 0x8111, 0xe42e, 0xe082, 0x1808, 0xe000, 0x0600, 0xe096,
+	0xa202, 0x3d03, 0xe42e, 0xaf02, 0xae04, 0xe000, 0x0201, 0xe09e,
+	0x2907, 0xe42e, 0xaf02, 0xae04, 0xe000, 0x0203, 0xe09e, 0x2907,
+	0xe42e, 0x3c0a, 0xe0c0, 0x0042, 0xe000, 0x0180, 0x080a, 0xa207,
+	0xe41e, 0x0fa5, 0xe0c0, 0x0041, 0xe005, 0x006c, 0xae0f, 0x0a0a,
+	0xe042, 0xa205, 0xe41e, 0x0fa5, 0xe42e, 0xce20, 0xd111, 0x0600,
+	0xd112, 0x0020, 0xce27, 0xca28, 0xf7f8, 0xe42e, 0x3c0a, 0xaf02,
+	0xae06, 0xe0c1, 0x0041, 0xe042, 0xe005, 0x006c, 0xae0f, 0xe042,
+	0xce20, 0xd111, 0x0600, 0xd112, 0x0004, 0xd113, 0x0003, 0xca28,
+	0xf7f8, 0xe004, 0x0600, 0xe09e, 0x2117, 0x4d17, 0x2a0a, 0xa803,
+	0xe42b, 0x2117, 0x4d17, 0xe42e, 0xe161, 0x0600, 0xa23e, 0xc71f,
+	0x3d11, 0x2848, 0xe000, 0x02b0, 0xe094, 0x2a48, 0x8848, 0x0022,
+	0xe184, 0x0fdf, 0x290a, 0xe000, 0x0600, 0xe092, 0x3f01, 0xa103,
+	0xd1f9, 0x0000, 0xe162, 0x0600, 0xd022, 0x001f, 0xe184, 0x0fe9,
+	0x2912, 0xcff0, 0xe42e, 0xe41e, 0x0fcc, 0xe42e, 0xd1f3, 0x0000,
+	0xe167, 0x02b0, 0xd022, 0x003f, 0xe184, 0x0ff7, 0x2917, 0xcfe4,
+	0xd1f9, 0x0000, 0xe167, 0x0600, 0xd022, 0x001f, 0xe184, 0x1001,
+	0x2917, 0xcff0, 0xe42e, 0xba4e, 0x3c11, 0xa200, 0x3c24, 0xd022,
+	0x0007, 0xe184, 0x1010, 0xba41, 0x5a24, 0xe056, 0x2a24, 0xa003,
+	0x3e24, 0x3c24, 0xa208, 0x3cf0, 0x2824, 0xaf0c, 0xe408, 0x111a,
+	0xa224, 0x3cf0, 0xe41e, 0x1373, 0xe40a, 0x111d, 0xa226, 0x3cf0,
+	0xba4e, 0x3c1f, 0xa112, 0xe404, 0x111a, 0xa154, 0xe400, 0x111a,
+	0xbc3e, 0x3c10, 0xa202, 0x3c22, 0xa200, 0x3c67, 0x2811, 0xa1c8,
+	0xf338, 0xbc06, 0x3c22, 0xa20a, 0x3cf0, 0xbc08, 0xe408, 0x111a,
+	0xa20c, 0x3cf0, 0xbc08, 0xe408, 0x111a, 0xba40, 0xba40, 0x3c67,
+	0xf23a, 0xa201, 0x3e69, 0x3e6b, 0xe160, 0x0000, 0xba40, 0xf11a,
+	0x2a69, 0xae03, 0xe056, 0x3c69, 0xe080, 0xe41e, 0x131e, 0x2a6b,
+	0xae03, 0xe056, 0x3c6b, 0xe080, 0xa201, 0xe41e, 0x1351, 0xf07e,
+	0x2a69, 0xae03, 0x3e69, 0x2a6b, 0xae03, 0x3e6b, 0xe080, 0xa002,
+	0xe090, 0xa110, 0xf648, 0xa20e, 0x3cf0, 0xbc18, 0xe40d, 0x111a,
+	0xa008, 0x3c13, 0xa202, 0x5813, 0x3414, 0x3c15, 0xa210, 0x3cf0,
+	0xbc04, 0x3c16, 0xe40d, 0x111a, 0xa102, 0xf034, 0xf0aa, 0xf33e,
+	0xa212, 0x3cf0, 0xbc18, 0xe40d, 0x111a, 0xa008, 0x3c17, 0xf2be,
+	0xba40, 0x3c18, 0xe41e, 0x0ca6, 0xe160, 0x0907, 0xe161, 0x0908,
+	0x3500, 0x3d01, 0xe41e, 0x0ca6, 0xe162, 0x0909, 0xe163, 0x090a,
+	0x3502, 0x3d03, 0xa214, 0x3cf0, 0xbdfe, 0xe40d, 0x111a, 0xe164,
+	0x090b, 0x3d04, 0xf10a, 0xa102, 0xcc44, 0xe162, 0x09e0, 0xe184,
+	0x10a4, 0xe41e, 0x0ca6, 0x3512, 0x3d12, 0xa216, 0x3cf0, 0xe41e,
+	0x124a, 0xf01e, 0xe40d, 0x111a, 0xa218, 0x3cf0, 0xbc20, 0xe40d,
+	0x111a, 0x3c19, 0xba40, 0x3c1a, 0xa21a, 0x3cf0, 0xbdfe, 0xe40d,
+	0x111a, 0xa002, 0x3c57, 0xa21c, 0x3cf0, 0xbdfe, 0xe40d, 0x111a,
+	0xa002, 0x3c58, 0x8457, 0x8258, 0xe018, 0x3c1e, 0xa222, 0x3cf0,
+	0x2c57, 0xe002, 0x0080, 0xe400, 0x111a, 0x2c58, 0xe002, 0x0080,
+	0xe400, 0x111a, 0x2c1e, 0xe002, 0x4000, 0xe400, 0x111a, 0xa200,
+	0x3c1c, 0xba40, 0x3c1b, 0xf098, 0xba40, 0x3c1c, 0x2858, 0xae02,
+	0x3c58, 0x2c1e, 0xae02, 0x3c1e, 0xe41e, 0x11ca, 0xa21e, 0x3cf0,
+	0x2a1b, 0xba40, 0xb636, 0x3c1d, 0xa220, 0x3cf0, 0xba40, 0xe161,
+	0x05e4, 0xc703, 0x3d11, 0xf16a, 0xe161, 0x05e4, 0xe41e, 0x0c8c,
+	0x3d11, 0xe41e, 0x0c8c, 0x3d11, 0xe41e, 0x0c8c, 0x2a1b, 0xf029,
+	0xae02, 0x3d11, 0xe41e, 0x0c8c, 0x2a1b, 0xf029, 0xae02, 0x3d11,
+	0xf12d, 0xa200, 0x3c90, 0x3c91, 0x2820, 0x3cea, 0x3ceb, 0xe41e,
+	0x1468, 0xba40, 0xe016, 0xe41a, 0x125a, 0xf05a, 0xe41e, 0x0cd5,
+	0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0xa2fe, 0xe42e, 0xe41e,
+	0x0c8c, 0x3c29, 0xbc3e, 0xe40d, 0x11c0, 0x1810, 0xf11a, 0x0810,
+	0x3c10, 0xe41e, 0x1ab1, 0x3c65, 0xa205, 0xae23, 0xcc9f, 0xa202,
+	0xe41e, 0x0c40, 0xa203, 0x3e9b, 0x2865, 0xe40a, 0x11c0, 0xba40,
+	0x3c2d, 0xba40, 0x3c2a, 0xbc0e, 0xe40d, 0x11c0, 0x3c2b, 0xf03a,
+	0xe40d, 0x11c0, 0x282d, 0x2a2b, 0xe01b, 0xe052, 0xe408, 0x11c0,
+	0x2811, 0xa184, 0xf078, 0x282d, 0xf0aa, 0xe004, 0x0064, 0x3c11,
+	0xf06e, 0x282b, 0xf04a, 0xe004, 0x0042, 0x3c11, 0xbc3e, 0xe40d,
+	0x11c0, 0x3c2c, 0xbc3e, 0x3c2e, 0xe40d, 0x11c0, 0xba40, 0x3c2f,
+	0xba42, 0x3c30, 0xbe34, 0xe40d, 0x11c0, 0xa034, 0x3c31, 0xe404,
+	0x11c0, 0xa168, 0xe402, 0x11c0, 0xbe34, 0xe40d, 0x11c0, 0xa034,
+	0xe404, 0x11c0, 0xa168, 0xe402, 0x11c0, 0xbe18, 0xe40d, 0x11c0,
+	0x3c32, 0x3c36, 0xba40, 0x3c33, 0xba40, 0x3c34, 0xba40, 0x3c35,
+	0xa200, 0x3c37, 0x3c68, 0x2811, 0xa184, 0xf37a, 0x2829, 0x3c02,
+	0xe41e, 0x1b79, 0xe41e, 0x0ba5, 0xf30a, 0xba40, 0x3c37, 0xba40,
+	0x3c68, 0xf28a, 0xa201, 0x3e6a, 0x3e6c, 0xe160, 0x0000, 0xe080,
+	0xa10c, 0x1837, 0x1837, 0xf132, 0xba40, 0xf11a, 0x2a6a, 0xae03,
+	0xe056, 0x3c6a, 0xe080, 0xe41e, 0x131e, 0x2a6c, 0xae03, 0xe056,
+	0x3c6c, 0xe080, 0xa203, 0xe41e, 0x1351, 0xf07e, 0x2a6a, 0xae03,
+	0x3e6a, 0x2a6c, 0xae03, 0x3e6c, 0xe080, 0xa002, 0xe090, 0xa110,
+	0xf5f8, 0xbe18, 0xf06d, 0x3c36, 0xe41e, 0x0cd5, 0xa202, 0xe42e,
+	0xe0c1, 0x0059, 0xa107, 0xf049, 0x28ae, 0xa902, 0x3cae, 0xe16a,
+	0xa200, 0xe42e, 0xa214, 0x2e1e, 0xe003, 0x0063, 0xf2f7, 0xa216,
+	0x2e1e, 0xe003, 0x018c, 0xf2a7, 0xa22a, 0x2e1e, 0xe003, 0x0318,
+	0xf257, 0xa22c, 0x2e1e, 0xe003, 0x0654, 0xf207, 0xa23e, 0x2e1e,
+	0xe003, 0x0e10, 0xf1b7, 0xa240, 0x2e1e, 0xe003, 0x1400, 0xf167,
+	0xa250, 0x2e1e, 0xe003, 0x2000, 0xf117, 0xa254, 0x2e1e, 0xe003,
+	0x2200, 0xf0c7, 0xa264, 0x2e1e, 0xe003, 0x5640, 0xf077, 0xa266,
+	0x2e1e, 0xe003, 0x9000, 0xf027, 0xa268, 0x2a1f, 0xe045, 0xf023,
+	0x3c1f, 0x2a1f, 0xa115, 0xe004, 0x0129, 0xf2d7, 0xa103, 0xe004,
+	0x02a3, 0xf297, 0xa113, 0xe004, 0x06f6, 0xf257, 0xa103, 0xe004,
+	0x0dec, 0xf217, 0xa113, 0xe004, 0x17bb, 0xf1d7, 0xa103, 0xe004,
+	0x34bc, 0xf197, 0xa103, 0xe004, 0x3c00, 0xf157, 0xa113, 0xe004,
+	0x6000, 0xf117, 0xa103, 0xe004, 0x6600, 0xf0d7, 0xa111, 0xe004,
+	0x1437, 0xae08, 0xf087, 0xa103, 0xe004, 0x21c0, 0xae08, 0xf037,
+	0xe004, 0x17bb, 0xae12, 0x3409, 0x3c0a, 0x841e, 0xe182, 0x0180,
+	0xe019, 0x2009, 0x4c0a, 0xc407, 0xd022, 0x000f, 0xe184, 0x1242,
+	0xe046, 0xf034, 0x8117, 0xe190, 0xe08e, 0x2a19, 0xe062, 0xa520,
+	0x3c20, 0xe42e, 0xe0c0, 0x0041, 0xe005, 0x0026, 0xae11, 0xe042,
+	0xce20, 0xd111, 0x09e0, 0xd112, 0x0200, 0xd113, 0x0002, 0xca28,
+	0xf7f8, 0xe42e, 0xa200, 0x3c00, 0x3c01, 0x3c02, 0x3c03, 0x3c04,
+	0x3c05, 0x3c06, 0x3c07, 0x3c08, 0x3c09, 0x3c0a, 0xba40, 0xa2ff,
+	0x3e25, 0x3e26, 0xf16a, 0xba4e, 0xa201, 0x3e25, 0x3c26, 0xe002,
+	0x00ff, 0xf0f8, 0xa202, 0x3c07, 0xba5e, 0xba5f, 0x3c25, 0x3e26,
+	0xe016, 0xe017, 0xe056, 0xf028, 0xf04e, 0xa200, 0x3c26, 0x3c25,
+	0xba40, 0xf02a, 0xba40, 0xba40, 0x3c0a, 0xf0ca, 0xba44, 0x3c09,
+	0xba40, 0x3c08, 0xba40, 0x3c06, 0xf05a, 0xba4e, 0x3c05, 0xba4e,
+	0xba4e, 0xba40, 0x3c04, 0xf05a, 0xbc0a, 0x3c03, 0xbc0a, 0x3c02,
+	0xba40, 0x3c01, 0xf0ba, 0xba7e, 0xe161, 0x05c7, 0x3511, 0x3d11,
+	0xba7e, 0x3511, 0x3d11, 0xba40, 0x3c00, 0xba40, 0x3c90, 0xe016,
+	0xe161, 0x05bd, 0xe41a, 0x1302, 0xe40a, 0x12ff, 0xba40, 0x3c91,
+	0xe016, 0xe161, 0x05c2, 0xe41a, 0x1302, 0xe40a, 0x12ff, 0x2890,
+	0x4c91, 0xf02a, 0xba40, 0xba40, 0x3c23, 0xba40, 0xf0aa, 0xba40,
+	0xbc20, 0xbc20, 0xbc20, 0xbc20, 0xbc20, 0x3cea, 0xbc20, 0x3ceb,
+	0x28eb, 0xa120, 0xf0a0, 0x2819, 0x18eb, 0xf070, 0x28b3, 0xf09a,
+	0x287f, 0xa104, 0x18eb, 0xf052, 0x2ab3, 0xf029, 0x2a20, 0x3eeb,
+	0xa202, 0xae3e, 0x2a0a, 0xae3d, 0xe056, 0x2a09, 0xae37, 0xe056,
+	0x2a08, 0xae35, 0xe056, 0x2a07, 0xae33, 0xe056, 0x2a06, 0xae31,
+	0xe056, 0x2a05, 0xae21, 0xe056, 0x2a04, 0xae11, 0xe056, 0x2a03,
+	0xae0b, 0xe056, 0x2a02, 0xae05, 0xe056, 0x2a01, 0xae03, 0xe056,
+	0x2a00, 0xe056, 0xe41e, 0x1468, 0xe16a, 0xa202, 0xe42e, 0xe16a,
+	0xa200, 0xe42e, 0xe41e, 0x0c8c, 0xcc44, 0x3c61, 0xa002, 0x3d11,
+	0xba46, 0xba46, 0xe184, 0x1310, 0xe41e, 0x0c8c, 0xe41e, 0x0c8c,
+	0xba40, 0xba48, 0xa002, 0x3d11, 0xba48, 0xa002, 0x3d11, 0xba48,
+	0xa002, 0x3d11, 0xba48, 0x3d11, 0xa202, 0xe42e, 0xd022, 0x000f,
+	0xa10c, 0xf034, 0xd022, 0x003f, 0xe161, 0x0600, 0xa210, 0x3c06,
+	0x3c07, 0xa200, 0x3c08, 0x3c09, 0xe09c, 0xe09e, 0xe184, 0x134e,
+	0x2807, 0xf10a, 0xe41e, 0x0ca6, 0xe42d, 0x0806, 0xe000, 0x0100,
+	0xe008, 0x00ff, 0x3c07, 0x4c09, 0xe01a, 0xe016, 0xe09e, 0xa202,
+	0x3c09, 0x2807, 0xf028, 0x2806, 0x3c06, 0xe08d, 0xa003, 0xe09d,
+	0xa803, 0xf059, 0xe085, 0xae11, 0xe056, 0x3d11, 0xe094, 0xe08e,
+	0xe42e, 0x3e08, 0x3c06, 0xa211, 0x3e07, 0xa10c, 0xf064, 0xb690,
+	0xa00c, 0x3c06, 0xa240, 0x3c07, 0x2806, 0x2a08, 0xf02b, 0xa01c,
+	0xae08, 0x3c06, 0xe0c0, 0x0041, 0xe005, 0x0034, 0xae11, 0xe042,
+	0x0806, 0xce20, 0xd111, 0x0600, 0x2807, 0xce24, 0xd113, 0x0002,
+	0xca28, 0xf7f8, 0xe42e, 0x2811, 0xa184, 0xf0ba, 0xa116, 0xf09a,
+	0xa12e, 0xf07a, 0x2824, 0xe008, 0x0003, 0xf038, 0xa200, 0xe42e,
+	0xa202, 0xe42e, 0xa202, 0x3c51, 0xe41e, 0x08bd, 0xe408, 0x13e2,
+	0xe41e, 0x0b72, 0xf26a, 0xa102, 0xe40a, 0x13fe, 0xa108, 0xe404,
+	0x13b0, 0xe40a, 0x13fe, 0xa102, 0xe40a, 0x13c8, 0xa102, 0xe40a,
+	0x13b3, 0xa102, 0xe40a, 0x13be, 0xa102, 0xe40a, 0x13d2, 0xa102,
+	0xe40a, 0x13df, 0xa102, 0xe40a, 0x13df, 0xa102, 0xe40a, 0x13e9,
+	0xf082, 0x2851, 0xe40a, 0x140c, 0xe41e, 0x098a, 0xe40e, 0x13f9,
+	0xe41e, 0x0951, 0xf52e, 0x2851, 0xe40a, 0x140c, 0xe41e, 0x1459,
+	0xe41e, 0x098a, 0xe41e, 0x1a99, 0xe40e, 0x13f9, 0x2851, 0xe40a,
+	0x140c, 0xe41e, 0x1459, 0xe41e, 0x098a, 0xe41e, 0x1ac4, 0xf32e,
+	0x2851, 0xe40a, 0x140c, 0xe41e, 0x1459, 0xe41e, 0x098a, 0xe41e,
+	0x146d, 0xf28e, 0x2851, 0xe40a, 0x140c, 0xe41e, 0x1460, 0xe41e,
+	0x1459, 0xe41e, 0x098a, 0xba44, 0xe41e, 0x0cd5, 0xf1be, 0xe41e,
+	0x08bd, 0xf16a, 0xe41e, 0x01db, 0x2851, 0xe408, 0x1413, 0xe40e,
+	0x140c, 0xe41e, 0x098a, 0xba0e, 0xe002, 0x00ff, 0xf058, 0xba4e,
+	0xe41e, 0x0b96, 0xf798, 0xe41e, 0x0cd5, 0xe40e, 0x1384, 0xe41e,
+	0x0951, 0x2851, 0xe40a, 0x140c, 0xe40e, 0x1384, 0xe41e, 0x1459,
+	0xe41e, 0x098a, 0xe41e, 0x25f9, 0xe41e, 0x0d68, 0xe40a, 0x1384,
+	0x284e, 0x3c92, 0x284f, 0x3c93, 0xa200, 0x3c51, 0xe41e, 0x1435,
+	0xf078, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xa2fe, 0xe42e, 0xe41e,
+	0x141e, 0xe41e, 0x05b7, 0xe41e, 0x19fe, 0xf74e, 0xe165, 0x05e8,
+	0x2811, 0x3d15, 0x2857, 0x3d15, 0x2858, 0x3d15, 0x28eb, 0x3d15,
+	0x281b, 0x3d15, 0x2824, 0x3d15, 0x281f, 0x3d15, 0x2813, 0x3d15,
+	0x2816, 0x3d15, 0x2819, 0x3d15, 0xe42e, 0xe165, 0x05e8, 0x2811,
+	0x1915, 0xf1d8, 0x2857, 0x1915, 0xf1a8, 0x2858, 0x1915, 0xf178,
+	0x28eb, 0x1915, 0xf148, 0x281b, 0x1915, 0xf118, 0x2824, 0x1915,
+	0xe428, 0x281f, 0x1915, 0xe428, 0x2813, 0x1915, 0xe428, 0x2816,
+	0x1915, 0xe428, 0x2819, 0x1915, 0xe428, 0xe42e, 0xa202, 0x3cbd,
+	0xe42e, 0x28ad, 0xe428, 0xe41e, 0x064c, 0xa202, 0x3cad, 0xe42e,
+	0xa200, 0x3cad, 0xe42e, 0xc009, 0x2039, 0x4c3a, 0xc000, 0xe42e,
+	0xc009, 0x3439, 0x3c3a, 0xc000, 0xe42e, 0xa200, 0xba4f, 0xe042,
+	0xe003, 0x00ff, 0xf7cb, 0xe41e, 0x171e, 0xa200, 0xba4f, 0xe042,
+	0xe003, 0x00ff, 0xf7cb, 0xe41e, 0x1726, 0xf04a, 0xe41e, 0x1487,
+	0xe42a, 0xe41e, 0x0b96, 0xf6a8, 0xe41e, 0x0cd5, 0xe42e, 0xe41e,
+	0x1722, 0xf13a, 0xa102, 0xf14a, 0xa104, 0xf15a, 0xa102, 0xf16a,
+	0xa102, 0xf17a, 0xa150, 0xf18a, 0xe41e, 0x172a, 0xf04a, 0xba4f,
+	0xa102, 0xf7e8, 0xa202, 0xe42e, 0xe41e, 0x14b6, 0xf10e, 0xe41e,
+	0x14e5, 0xf0de, 0xe41e, 0x1533, 0xf0ae, 0xe41e, 0x1544, 0xf07e,
+	0xe41e, 0x158e, 0xf04e, 0xe41e, 0x1592, 0xf01e, 0xe42a, 0xc868,
+	0xa80e, 0xe016, 0xe428, 0xe41e, 0x0cd5, 0xe42e, 0xbc3e, 0xf1fd,
+	0x1810, 0xf11a, 0x0810, 0xf084, 0xa13e, 0xf060, 0xa03e, 0x3c10,
+	0xe41e, 0x1ab1, 0x3c65, 0xa200, 0xe41e, 0x0c40, 0xa201, 0x3e9b,
+	0x2865, 0xe42a, 0x2890, 0xe161, 0x05bd, 0xe418, 0x14d9, 0x2891,
+	0xe161, 0x05c2, 0xe418, 0x14d9, 0xa202, 0xe42e, 0xa200, 0xe16a,
+	0xe42e, 0x2911, 0xa102, 0xcc44, 0xe184, 0x14e3, 0x2901, 0xe41e,
+	0x0cc9, 0x2901, 0xe41e, 0x0cc9, 0xe42e, 0x2890, 0xe161, 0x05bf,
+	0xf038, 0xe161, 0x05c4, 0x4c91, 0xf11a, 0x2911, 0xe41e, 0x0cc9,
+	0xc009, 0x343f, 0x3c40, 0xc000, 0x2911, 0xe41e, 0x0cc9, 0xc009,
+	0x3441, 0x3c42, 0xc000, 0x2911, 0xf02e, 0xa230, 0x3c02, 0x2823,
+	0xe016, 0xe428, 0xba46, 0x3ca3, 0xa112, 0xb604, 0xe42a, 0xa012,
+	0xe049, 0xa200, 0xa107, 0xb426, 0xa105, 0xb426, 0xa105, 0xb5f6,
+	0xcc44, 0xe184, 0x1530, 0xba40, 0xf028, 0xf1be, 0xba42, 0xba40,
+	0xba48, 0xba40, 0x3c03, 0xba40, 0xba40, 0xba4e, 0x2803, 0xf05a,
+	0xba4a, 0xba4a, 0xba48, 0xf0ae, 0xba40, 0xf08a, 0xba4a, 0xba40,
+	0xf05a, 0xba4a, 0xba40, 0xf02a, 0xba48, 0x2802, 0xe41e, 0x0cc9,
+	0xe190, 0xa202, 0xe42e, 0xe41e, 0x172a, 0xf0da, 0xa102, 0xcc44,
+	0xe004, 0x00ff, 0xe184, 0x153d, 0xba4f, 0xe052, 0xe002, 0x00ff,
+	0xe016, 0xe42a, 0xa202, 0xe42e, 0xa202, 0xba4f, 0xe003, 0x00ff,
+	0xf039, 0xba4f, 0xa204, 0xba1f, 0xe003, 0x0031, 0xf049, 0xba5f,
+	0xa004, 0xe190, 0xba3f, 0x360e, 0x3e0f, 0xe005, 0x4454, 0x1a0e,
+	0xf069, 0xe005, 0x4731, 0x1a0f, 0xf029, 0xf24e, 0xe005, 0x4741,
+	0x1a0e, 0xf0b9, 0xe005, 0x3934, 0x1a0f, 0xf079, 0xba7f, 0xa008,
+	0xba0f, 0xa10d, 0xe40b, 0x1578, 0xc009, 0x2a2d, 0xc000, 0xe045,
+	0xa009, 0xc009, 0x3e2d, 0xc000, 0xe41e, 0x1621, 0xa202, 0xe42e,
+	0xba4f, 0xa002, 0xc009, 0x2a2d, 0xc000, 0xe045, 0xf4d1, 0xa202,
+	0xe42e, 0xba7e, 0xba40, 0xf098, 0xba41, 0xba4a, 0xf04b, 0xba46,
+	0xba46, 0x3cb0, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xe41e, 0x1621,
+	0xa202, 0xe42e, 0xc009, 0xa2fe, 0x3426, 0x3c27, 0xa201, 0x3628,
+	0x3e29, 0x362a, 0x3e2b, 0xc000, 0xe41e, 0x0c8c, 0xc009, 0xe40d,
+	0x1607, 0x3426, 0x3c27, 0xba40, 0xe40d, 0x1607, 0xae2a, 0xe055,
+	0x3628, 0x3e29, 0xe408, 0x15fd, 0xba4c, 0xe40d, 0x1607, 0xae0c,
+	0xe055, 0xba40, 0xe40d, 0x1607, 0xae28, 0xe055, 0xba4a, 0xe40d,
+	0x1607, 0xe055, 0xba40, 0xe40d, 0x1607, 0xae26, 0xe055, 0xba40,
+	0xe40d, 0x1607, 0xae24, 0xe055, 0xba40, 0xe40d, 0x1607, 0xae22,
+	0xe055, 0xba40, 0xe40d, 0x1607, 0xae20, 0xe055, 0xba40, 0xe40d,
+	0x1607, 0xae1e, 0xe055, 0xba40, 0xe40d, 0x1607, 0xae1c, 0xe055,
+	0x3628, 0x3e29, 0xe04a, 0xaf28, 0xa802, 0xe016, 0xaf0d, 0xa83f,
+	0xa10b, 0xe01b, 0xe052, 0xf12a, 0xa201, 0xba46, 0xf21d, 0xae38,
+	0xe055, 0xba46, 0xf1dd, 0xae30, 0xe055, 0xba46, 0xf19d, 0xae28,
+	0xe055, 0xba46, 0xf15d, 0xae20, 0xe055, 0xba4e, 0xf11d, 0xe0c4,
+	0x4064, 0xf0ed, 0xe055, 0x362a, 0x3e2b, 0x2228, 0x4e29, 0xba40,
+	0xae1a, 0xe055, 0x3628, 0x3e29, 0xa202, 0xc000, 0xe42e, 0xc009,
+	0xa2fe, 0x3426, 0x3c27, 0xa200, 0x3428, 0x3c29, 0x342a, 0x3c2b,
+	0xc000, 0xe42e, 0xc009, 0x2426, 0x4c27, 0xc000, 0xe42e, 0xc009,
+	0x2428, 0x4c29, 0xc000, 0xe42e, 0xc009, 0x242a, 0x4c2b, 0xc000,
+	0xe42e, 0xe0c0, 0x0065, 0xa878, 0xa140, 0xf0ba, 0xe41e, 0x172a,
+	0xa102, 0xcc44, 0xe184, 0x162d, 0xba4e, 0xe190, 0xe40e, 0x16b1,
+	0xa201, 0xe41e, 0x170c, 0x2907, 0xa002, 0x3c0c, 0x3d17, 0xa120,
+	0xf6e0, 0x2b07, 0xe41e, 0x1722, 0xf05a, 0xe41e, 0x172a, 0xe041,
+	0xf05e, 0x2861, 0xa002, 0xae06, 0xe041, 0xa00f, 0xaf07, 0xae07,
+	0xe04a, 0xaf1f, 0xf0db, 0xa201, 0xe41e, 0x170c, 0x8117, 0x8117,
+	0x2907, 0xa202, 0x3d07, 0xa201, 0xe41e, 0x170a, 0xf50e, 0x3d17,
+	0xa201, 0xe41e, 0x170a, 0xe167, 0x0600, 0xe41e, 0x1722, 0x3d17,
+	0xe41e, 0x1722, 0xf04a, 0xe41e, 0x172a, 0xf04e, 0x2861, 0xa002,
+	0xae06, 0x3d17, 0x2a0c, 0xe41e, 0x170a, 0xa200, 0x3c0b, 0xa200,
+	0xe167, 0x0600, 0xc703, 0x3d17, 0xe167, 0x0600, 0xe41e, 0x1722,
+	0xf3ba, 0xe41e, 0x1722, 0xa108, 0xf0f8, 0xe004, 0x4741, 0x3d17,
+	0xe004, 0x3934, 0x3d17, 0x28a7, 0xa008, 0x3ca7, 0xe41e, 0x172a,
+	0xa108, 0xe41e, 0x1726, 0x280b, 0xa002, 0x3c0b, 0xba4f, 0x28a7,
+	0xa002, 0x3ca7, 0xa802, 0xf058, 0x280a, 0xae10, 0xe056, 0x3d17,
+	0x3e0a, 0x28a7, 0xa80e, 0xe41a, 0x16cc, 0xe41e, 0x172a, 0x180b,
+	0xf6b0, 0x28a7, 0xa80e, 0xf0ea, 0x2aa7, 0xa803, 0xf04b, 0x280a,
+	0xae10, 0x3d17, 0x2aa7, 0xa00f, 0xaf07, 0xae07, 0x3ea7, 0xe418,
+	0x16cc, 0xe40e, 0x16ca, 0x280b, 0xa002, 0x3c0b, 0x2901, 0xe41e,
+	0x0cc9, 0x3517, 0x3d17, 0x2901, 0xe41e, 0x0cc9, 0x3517, 0x3d17,
+	0x28a7, 0xa010, 0x3ca7, 0xe41e, 0x16cc, 0x2861, 0xa002, 0x180b,
+	0xf6b0, 0xf01a, 0xa202, 0xe42e, 0x24b7, 0x4cb8, 0xe000, 0x0088,
+	0x18a7, 0xf242, 0xe0c0, 0x0065, 0xaf12, 0xa802, 0xf0da, 0xa201,
+	0xe41e, 0x170c, 0x8117, 0x8117, 0x2907, 0xa202, 0x3d07, 0xa201,
+	0xe41e, 0x170a, 0xe42e, 0xe004, 0x0200, 0xe0c1, 0x005d, 0xe055,
+	0xe0c3, 0x005d, 0xa202, 0xce00, 0xe0c0, 0x005d, 0xe008, 0x0200,
+	0xe190, 0xf7b8, 0xe004, 0x0090, 0x3ca7, 0x24b5, 0x4cb6, 0x08a7,
+	0xa110, 0xce20, 0xd111, 0x0600, 0xd112, 0x0004, 0xd113, 0x0000,
+	0xca28, 0xf7f8, 0xa200, 0xe167, 0x0600, 0xc703, 0x3d17, 0xe167,
+	0x0600, 0xe42e, 0xa200, 0xf02e, 0xa202, 0x3c0d, 0x24b5, 0x4cb6,
+	0xae07, 0xe042, 0xce20, 0xd111, 0x0600, 0xd112, 0x0004, 0x880d,
+	0x0113, 0xca28, 0xf7f8, 0xe167, 0x0600, 0xe42e, 0xc009, 0x3c2c,
+	0xc000, 0xe42e, 0xc009, 0x282c, 0xc000, 0xe42e, 0xc009, 0x3c2d,
+	0xc000, 0xe42e, 0xc009, 0x282d, 0xc000, 0xe42e, 0x2c39, 0x3c7b,
+	0xa202, 0x3c7c, 0xa200, 0x3c7d, 0x3c7e, 0x284e, 0xe016, 0xe428,
+	0x284f, 0xf0ca, 0xe41e, 0x17cd, 0xba40, 0xba40, 0xb7f0, 0xb634,
+	0x3c7c, 0xa200, 0x3c7b, 0xa202, 0xe42e, 0xba40, 0xf11a, 0x2819,
+	0xe42a, 0xae02, 0x3c09, 0x2014, 0x4c15, 0x583f, 0x3400, 0x3c01,
+	0x2c39, 0x583f, 0x083f, 0x3402, 0x3c03, 0xbc0c, 0xf058, 0xa202,
+	0x3c7d, 0xe42e, 0xbc0c, 0xe40d, 0x17ca, 0xe40a, 0x17c8, 0xa102,
+	0xf0ca, 0xa102, 0xf1fa, 0xa102, 0xf24a, 0xa102, 0xf39a, 0xa102,
+	0xe40a, 0x17a8, 0xe40e, 0x17b0, 0xe41e, 0x0c8c, 0xe40d, 0x17ca,
+	0xa002, 0x1002, 0x1c03, 0xe012, 0x3c0a, 0xf032, 0x0000, 0x0c01,
+	0xa203, 0xe41e, 0x17d4, 0x2a0a, 0x3e04, 0x4c4f, 0xe41a, 0x17ec,
+	0xf5ae, 0xbc40, 0xe40d, 0x17ca, 0xa2ff, 0xe41e, 0x17d4, 0xf53e,
+	0xe41e, 0x0c8c, 0xe40d, 0x17ca, 0xa002, 0x1002, 0x1c03, 0xe012,
+	0xf032, 0x0000, 0x0c01, 0x3c06, 0xa802, 0x443f, 0xbc21, 0xf33d,
+	0x5a3f, 0xe041, 0x3e07, 0xe41e, 0x181b, 0xe40e, 0x175a, 0xbc20,
+	0xf2ad, 0xa102, 0x583f, 0x083f, 0xe41e, 0x1836, 0xe40e, 0x175a,
+	0xe41e, 0x17cd, 0xa202, 0x3c7e, 0xa200, 0x3c7b, 0xe40e, 0x175a,
+	0xbc20, 0xf19d, 0x3c7b, 0x287b, 0x583f, 0x083f, 0xa2ff, 0xe41e,
+	0x17d4, 0xf7a8, 0x283f, 0xf09a, 0x2840, 0xf078, 0x287b, 0xae02,
+	0xa2ff, 0xe41e, 0x17d4, 0xf7b8, 0xa2fe, 0x3c7c, 0xe40e, 0x175a,
+	0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0xc410, 0xe161, 0x02f1,
+	0xa200, 0xc71f, 0x3d31, 0xe42e, 0x3c04, 0x3e05, 0xe161, 0x02f0,
+	0x8809, 0x0022, 0xe184, 0x17e7, 0x2d11, 0x2b09, 0x1c04, 0x1a05,
+	0xf068, 0xf059, 0x8111, 0xa200, 0x3d09, 0xf05e, 0x8111, 0x8111,
+	0xa200, 0xe42e, 0xa202, 0xe42e, 0xe161, 0x02f0, 0x8809, 0x0022,
+	0xe184, 0x17fc, 0x2d11, 0x2b09, 0x1804, 0x1a05, 0xf050, 0xf049,
+	0x8111, 0xa200, 0x3d09, 0x8111, 0x8111, 0xe160, 0x0003, 0xe161,
+	0x02f1, 0x8809, 0x0022, 0xe184, 0x1818, 0x2909, 0xf11a, 0x2d01,
+	0x2e39, 0x5a3f, 0xe045, 0xf053, 0x2214, 0x4e15, 0x5a3f, 0xe046,
+	0xae02, 0x1804, 0xf052, 0xa200, 0x8111, 0x3d01, 0xe42e, 0x8131,
+	0xe190, 0xa202, 0xe42e, 0x2807, 0xa2ff, 0xe41e, 0x17d4, 0xf7c8,
+	0xe161, 0x02f0, 0x8809, 0x0022, 0xe184, 0x1831, 0x2d11, 0x2b09,
+	0x1c06, 0xf078, 0xf067, 0x2807, 0x3d11, 0xa2fe, 0x3d09, 0xf05e,
+	0x8111, 0x8111, 0xa200, 0xe42e, 0xa202, 0xe42e, 0x3c08, 0xe161,
+	0x02f0, 0x8809, 0x0022, 0xe184, 0x1846, 0x2d11, 0x2b09, 0x1808,
+	0xf056, 0xf043, 0x8111, 0xa200, 0x3d09, 0x8111, 0x8111, 0xe42e,
+	0x2819, 0x1812, 0xf122, 0x2812, 0xa102, 0xcc44, 0xe161, 0x0202,
+	0xe184, 0x185b, 0x2911, 0xf06a, 0x2909, 0xe412, 0x1f29, 0xa200,
+	0x3d11, 0xe082, 0xa006, 0xe092, 0x2819, 0xb62c, 0x3c12, 0x2816,
+	0xa104, 0xe428, 0xe41e, 0x19fe, 0xe42e, 0x2816, 0xa102, 0xf044,
+	0xf16a, 0xe40e, 0x18b3, 0x7417, 0xe160, 0x0903, 0x3d00, 0x283f,
+	0xe016, 0x442a, 0xe418, 0x0ca6, 0xe42d, 0xe161, 0x0904, 0xe162,
+	0x0905, 0x3501, 0x3d02, 0xe41e, 0x1916, 0xf38e, 0xa200, 0xe160,
+	0x0903, 0xe161, 0x0904, 0xe162, 0x0905, 0xe163, 0x0906, 0x3500,
+	0x3d01, 0x3502, 0x3d03, 0x2818, 0xf178, 0xe41e, 0x0ca6, 0xe42d,
+	0xe164, 0x0903, 0xe165, 0x0904, 0x3504, 0x3d05, 0x282a, 0xf0ca,
+	0x283f, 0xf0a8, 0xe41e, 0x0ca6, 0xe42d, 0xe166, 0x0905, 0xe167,
+	0x0906, 0x3506, 0x3d07, 0xe41e, 0x1966, 0xf10e, 0xe164, 0x0903,
+	0xe165, 0x0904, 0xe166, 0x0905, 0xe167, 0x0906, 0x3504, 0x3d05,
+	0x3506, 0x3d07, 0xf03e, 0xe41e, 0x19b7, 0x283f, 0x2a42, 0xf0f9,
+	0xf078, 0x2074, 0x4c75, 0x2276, 0x4e77, 0xe066, 0xf0ee, 0x2074,
+	0x4c75, 0xc009, 0x343b, 0x3c3c, 0xc000, 0xf07e, 0x2076, 0x4c77,
+	0xc009, 0x343d, 0x3c3e, 0xc000, 0x3472, 0x3c73, 0xe42e, 0x284f,
+	0x4c7e, 0xe418, 0x19fe, 0x28e5, 0xae02, 0xe000, 0x0578, 0xe092,
+	0x2072, 0x4c73, 0x3511, 0x3d11, 0x28e5, 0xe000, 0x059a, 0xe092,
+	0x2884, 0x3d11, 0x28e5, 0xa002, 0x3ce5, 0x28eb, 0x2a16, 0xa105,
+	0xb616, 0x2a21, 0xb616, 0x3c07, 0xe41e, 0x1f46, 0xf048, 0xe41e,
+	0x1a03, 0xf7be, 0xe41e, 0x1f56, 0xe428, 0xe41e, 0x1a03, 0xf7be,
+	0x28e9, 0xf04a, 0xa102, 0x3ce9, 0xf14e, 0x28e8, 0xf12a, 0x28e7,
+	0xe000, 0x05ab, 0xe092, 0x28e7, 0xa002, 0x3ce7, 0xa122, 0xf028,
+	0x3ce7, 0x28e8, 0xa102, 0x3ce8, 0x2901, 0xe049, 0x1a7f, 0xe425,
+	0xe41e, 0x08d7, 0xe049, 0xa2fa, 0xb7f2, 0xe42e, 0xa202, 0x5817,
+	0xaf02, 0x3c06, 0x284f, 0x2a82, 0xf0b8, 0xf0d9, 0xe164, 0x0906,
+	0x2114, 0x4d14, 0xe166, 0x0908, 0x2316, 0x4f16, 0xf09e, 0xa200,
+	0xa201, 0xf06e, 0xa200, 0xe161, 0x090a, 0x2311, 0x4f11, 0x3400,
+	0x3c01, 0x3602, 0x3e03, 0xe161, 0x0903, 0x2f01, 0x1202, 0x1e03,
+	0xf071, 0xe013, 0x1e06, 0xf085, 0x0c06, 0x0c06, 0xf05e, 0x1e06,
+	0xf037, 0x1c06, 0x1c06, 0x3404, 0x3c05, 0xe161, 0x0903, 0x0d01,
+	0x3474, 0x3c75, 0xe162, 0x0904, 0x0112, 0x0d12, 0x3476, 0x3c77,
+	0x284e, 0xf14a, 0x2074, 0x4c75, 0xe161, 0x090a, 0x3511, 0x3d11,
+	0x2004, 0x4c05, 0xe164, 0x0906, 0x3514, 0x3d14, 0xe161, 0x0903,
+	0xe166, 0x0908, 0x2d01, 0x3516, 0x3d16, 0xe42e, 0xe41e, 0x19c8,
+	0xe160, 0x090b, 0x2900, 0xf34a, 0x2000, 0x4c01, 0x0c39, 0xf306,
+	0x2a4e, 0xe017, 0xe046, 0xa102, 0xf2b4, 0xe160, 0x090b, 0xe188,
+	0x000f, 0x7d00, 0x3402, 0x3c03, 0xe41e, 0x19ee, 0xe163, 0x090b,
+	0x2903, 0xa102, 0xcc44, 0xe161, 0x09e0, 0xa200, 0xe184, 0x1989,
+	0x0111, 0x0d11, 0xae02, 0x3404, 0xe008, 0xffff, 0xaf02, 0x3c05,
+	0x8403, 0x8204, 0xe018, 0xae1e, 0x8205, 0xe01c, 0xe161, 0x09e0,
+	0x8802, 0x0022, 0xe184, 0x199d, 0x0111, 0x0d11, 0xf02e, 0xa200,
+	0x2a4e, 0xf059, 0xe161, 0x0907, 0x0111, 0x0d11, 0xe164, 0x0903,
+	0x0114, 0x0d14, 0x3474, 0x3c75, 0xe162, 0x0909, 0x0112, 0x0d12,
+	0xe166, 0x0905, 0x0116, 0x0d16, 0x3476, 0x3c77, 0xe42e, 0xe41e,
+	0x19c8, 0x284f, 0xe016, 0xf08a, 0x2000, 0x4c01, 0x0c39, 0xae02,
+	0x2a4e, 0xe017, 0xe046, 0x3474, 0x3c75, 0x3476, 0x3c77, 0xe42e,
+	0x2882, 0xf09a, 0xa200, 0xe162, 0x0901, 0x3512, 0x3d12, 0xe161,
+	0x0900, 0x3d01, 0x284f, 0xe016, 0xf0da, 0xe162, 0x0901, 0x2112,
+	0x4d12, 0xe161, 0x0900, 0x2f01, 0x1e39, 0xf047, 0xa203, 0x5a13,
+	0xe042, 0x3400, 0x3c01, 0x2839, 0xe161, 0x0900, 0x3d01, 0x2000,
+	0x4c01, 0xe162, 0x0901, 0x3512, 0x3d12, 0xe42e, 0xe0c0, 0x0041,
+	0xe005, 0x0026, 0xae11, 0xe042, 0xce20, 0xd111, 0x09e0, 0xd112,
+	0x0200, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e, 0x28e5, 0xe426,
+	0xe41e, 0x1a03, 0xf7ce, 0x28e5, 0xe426, 0xe161, 0x0578, 0xe162,
+	0x0578, 0x2111, 0x4d11, 0xa201, 0x3e00, 0xa203, 0x28e5, 0xa104,
+	0xf0e4, 0xcc44, 0xe184, 0x1a1d, 0x2112, 0x4d0a, 0x1111, 0x1d11,
+	0xf056, 0xe082, 0xa104, 0xe094, 0x3e00, 0xa003, 0xe084, 0xa004,
+	0xe092, 0x2800, 0xe000, 0x059a, 0xe098, 0xa002, 0xe096, 0x2904,
+	0x3c01, 0xe41e, 0x1f30, 0x28e5, 0x1800, 0xa104, 0xf0a4, 0xcc44,
+	0xe184, 0x1a37, 0x2911, 0x3d12, 0x2911, 0x3d12, 0x2913, 0x3d14,
+	0x28e5, 0xb5f0, 0x3ce5, 0x28e6, 0xe000, 0x05ab, 0xe092, 0x2801,
+	0x3d01, 0x28e6, 0xa002, 0x3ce6, 0xa122, 0xf028, 0x3ce6, 0x28e8,
+	0xa002, 0x3ce8, 0xe42e, 0xa200, 0x3cb2, 0xe004, 0x0054, 0xe09c,
+	0x287f, 0xa102, 0xcc44, 0xe184, 0x1a64, 0x9e06, 0x5cb2, 0xa802,
+	0xf0a8, 0x28b2, 0xe049, 0xe001, 0x0518, 0xe09f, 0x2b07, 0xa809,
+	0xe419, 0x1f37, 0x2ab2, 0xa003, 0x3eb2, 0xe42e, 0xe004, 0x0518,
+	0xe09e, 0xe004, 0x0054, 0xe09c, 0x287f, 0xa102, 0xcc44, 0xa200,
+	0x3cb2, 0xe184, 0x1a7a, 0x2b17, 0xaf05, 0xa803, 0x5ab2, 0xe056,
+	0x2ab2, 0xa003, 0x3eb2, 0x9f06, 0xe42e, 0x2840, 0xf078, 0xe41e,
+	0x1f72, 0x3c3e, 0xe41e, 0x1fbc, 0xf03e, 0x283e, 0x3c84, 0xe42e,
+	0xe161, 0x0600, 0xa200, 0x3d11, 0x3c02, 0xd022, 0x011f, 0xe184,
+	0x1a95, 0xe41e, 0x1b77, 0x2802, 0xa002, 0x3c02, 0xa200, 0x3c9b,
+	0xe42e, 0xba4e, 0xba40, 0xba40, 0xba40, 0xba40, 0xba46, 0xba4e,
+	0xbc3e, 0xf0dd, 0x3c00, 0x1810, 0xf038, 0xa2fe, 0x3c10, 0x2800,
+	0xe000, 0x0100, 0xe41e, 0x1b08, 0xa202, 0xe42e, 0xe16a, 0xa200,
+	0xe42e, 0xa204, 0x3c9b, 0x2810, 0xe000, 0x0100, 0xe41e, 0x1b43,
+	0xe42a, 0xe41e, 0x1003, 0xf056, 0xe41e, 0x1848, 0xa202, 0xe42e,
+	0xa2fe, 0x3c10, 0xa200, 0xe42e, 0xe41e, 0x0c8c, 0xf12d, 0x3c01,
+	0xe002, 0x00ff, 0xf0e0, 0x2801, 0x1829, 0xf038, 0xa2fe, 0x3c29,
+	0x28ae, 0xa802, 0x3cae, 0x2801, 0xe41e, 0x1b08, 0xa202, 0xe42e,
+	0xe16a, 0xa200, 0xe42e, 0xa202, 0x3c9b, 0x2829, 0xe41e, 0x1b43,
+	0xf0da, 0xe41e, 0x111f, 0x3c65, 0xa200, 0xe41e, 0x0c40, 0xa201,
+	0x3e9b, 0x2865, 0xf03a, 0xa202, 0xe42e, 0xe0c1, 0x0059, 0xa107,
+	0xf079, 0x28ae, 0xa104, 0xf04a, 0x28ae, 0xa902, 0x3cae, 0xa2fe,
+	0x3c29, 0xa200, 0xe42e, 0x2860, 0xa102, 0xf06a, 0x2499, 0x4c9a,
+	0xe41e, 0x1b91, 0xe470, 0xe41e, 0x1baa, 0xe41e, 0x1b98, 0xe470,
+	0x3c02, 0xe41e, 0x1b79, 0xa200, 0x3c06, 0x2802, 0xae14, 0x3404,
+	0x3c05, 0xe41e, 0x0c3b, 0x0404, 0x0c05, 0xce20, 0xd111, 0x0000,
+	0xe41e, 0x0c0e, 0x1806, 0xa00e, 0xaf06, 0xae02, 0xce24, 0xd113,
+	0x0012, 0xca28, 0xf7f8, 0xca2c, 0xf7fa, 0xe41e, 0x0c17, 0xf128,
+	0x2004, 0x4c05, 0xe000, 0x0200, 0x3404, 0x3c05, 0xe41e, 0x0c0e,
+	0x3c06, 0xe41e, 0x09df, 0xe41e, 0x0c0e, 0xe002, 0x0400, 0xf020,
+	0xf59e, 0xe161, 0x0600, 0xa202, 0x3d11, 0xe41e, 0x0c0e, 0x3d01,
+	0xe41e, 0x1b77, 0xe42e, 0x3c02, 0xe41e, 0x1b79, 0xe161, 0x0600,
+	0x2911, 0xe42a, 0x8111, 0x2111, 0x4d11, 0x2802, 0xae14, 0x3404,
+	0x3c05, 0x289b, 0xa102, 0xf0da, 0xe41e, 0x0c3b, 0x0404, 0x0c05,
+	0xe41e, 0x1b91, 0xa204, 0xe41e, 0x0c40, 0xe004, 0x0090, 0xf0ce,
+	0xe41e, 0x0c3b, 0x0404, 0x0c05, 0xe41e, 0x1b98, 0xa202, 0xe41e,
+	0x0c40, 0xe004, 0x0080, 0xcc66, 0xcc6a, 0xcc6e, 0xa01e, 0xcc6c,
+	0xa200, 0xcc60, 0xcc68, 0xcc70, 0xe128, 0xa202, 0xe42e, 0xa204,
+	0xf02e, 0xa206, 0x3c0a, 0xe41e, 0x1b87, 0xce20, 0xd111, 0x0600,
+	0xd112, 0x0004, 0x880a, 0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe0c0,
+	0x0041, 0xe005, 0x002a, 0xae11, 0xe042, 0x2a02, 0xae07, 0xe042,
+	0xe42e, 0xce20, 0xa080, 0x3499, 0x3c9a, 0xd111, 0x0090, 0xf07e,
+	0xce20, 0xa080, 0xe41e, 0x1ba5, 0xd111, 0x0080, 0xd112, 0x0010,
+	0xd113, 0x0013, 0xca28, 0xf7f8, 0xe42e, 0xc009, 0x3410, 0x3c11,
+	0xc000, 0xe42e, 0xc009, 0x2410, 0x4c11, 0xc000, 0xe42e, 0x2819,
+	0xe42a, 0xa102, 0x3c00, 0x284e, 0xe01a, 0x2abe, 0xa003, 0xa803,
+	0xe052, 0xe418, 0x1cd9, 0xe41e, 0x1d0e, 0xe41e, 0x1d42, 0xe41e,
+	0x1d7a, 0xe42e, 0x287e, 0xf11a, 0x2074, 0x4c75, 0x1072, 0x1c73,
+	0x3474, 0x3c75, 0x2076, 0x4c77, 0x1072, 0x1c73, 0x3476, 0x3c77,
+	0xa200, 0x3472, 0x3c73, 0x3c3c, 0xa200, 0x3cbe, 0x2c39, 0x2a4f,
+	0x4e7e, 0xb612, 0x3c80, 0x2819, 0xf12a, 0xa102, 0x3c00, 0x2839,
+	0x3c50, 0x287d, 0xe41a, 0x1c9d, 0x2840, 0xe016, 0xe418, 0x1c6e,
+	0x2840, 0xe408, 0x1c32, 0xe41e, 0x1bf2, 0xe42e, 0x2884, 0xe41e,
+	0x1f29, 0xe42e, 0xc420, 0xe161, 0x0202, 0x8800, 0x0022, 0xe184,
+	0x1bfb, 0x2901, 0xf03a, 0x8131, 0xe42e, 0xe082, 0xe002, 0x0202,
+	0xaf04, 0x3c0a, 0x2841, 0x3d09, 0x287c, 0x3d09, 0x287b, 0x3d31,
+	0x8109, 0x2884, 0x3d11, 0xe082, 0xe000, 0x005c, 0xe094, 0xe002,
+	0x0260, 0xaf02, 0xe000, 0x0240, 0xe092, 0x2072, 0x4c73, 0x3511,
+	0x3d11, 0x2a41, 0xa105, 0x2112, 0x4d0a, 0xf03b, 0x2074, 0x4c75,
+	0x3512, 0x3d12, 0x2112, 0x4d0a, 0xf035, 0x2076, 0x4c77, 0x3512,
+	0x3d12, 0x280a, 0xe000, 0x02a0, 0xe092, 0xa206, 0x1841, 0xe01a,
+	0x3d01, 0xe42e, 0xe161, 0x0200, 0x8800, 0x0022, 0xe184, 0x1c3f,
+	0x2d11, 0x2b11, 0x1c7b, 0x1a7c, 0xf028, 0xf04b, 0x8111, 0x8111,
+	0xe42e, 0xa206, 0x3d01, 0xe082, 0xe000, 0x005e, 0xe094, 0xe002,
+	0x0260, 0xaf02, 0xe000, 0x0240, 0xe092, 0xe002, 0x0240, 0xaf02,
+	0x3c0a, 0x2072, 0x4c73, 0x2311, 0x4f09, 0xe066, 0x3511, 0x3d11,
+	0xf41e, 0xc420, 0xe161, 0x0202, 0x8800, 0x0022, 0xe184, 0x1c62,
+	0x2901, 0xf03a, 0x8131, 0xe42e, 0xa206, 0x3d09, 0xa202, 0x3d09,
+	0x2850, 0x3d31, 0x8109, 0xa2fe, 0x3d11, 0xe42e, 0xa200, 0xc420,
+	0xe161, 0x0202, 0x8800, 0x0022, 0xe184, 0x1c78, 0x2b31, 0xe01b,
+	0xe042, 0x1819, 0xe424, 0xa203, 0xae21, 0xe161, 0x0202, 0x8800,
+	0x0022, 0xe184, 0x1c96, 0x2909, 0xf11a, 0x2909, 0xf0e6, 0x2901,
+	0x1c50, 0xf036, 0x1014, 0x1c15, 0x0c50, 0xe046, 0xf062, 0xe042,
+	0xe049, 0xe082, 0xa004, 0xe094, 0x8111, 0x8111, 0x8131, 0xa200,
+	0x3d12, 0x2912, 0xe412, 0x1f29, 0xe42e, 0xe161, 0x0200, 0xe162,
+	0x02f0, 0x8800, 0x0022, 0xe184, 0x1cd7, 0x283f, 0xf098, 0x2912,
+	0x3c02, 0x2912, 0x3c03, 0xe01a, 0xb670, 0x3c04, 0xf15e, 0x2912,
+	0xaf02, 0x3c02, 0x2912, 0x3c03, 0xe01a, 0x3c04, 0x8112, 0x290a,
+	0xe01a, 0xae02, 0x4c04, 0x3c04, 0xa802, 0xf068, 0x2912, 0xaf02,
+	0x3c02, 0x290a, 0x3c03, 0x2804, 0x8112, 0x8112, 0xf08a, 0x2802,
+	0x3d11, 0x2803, 0x3d11, 0x2804, 0x3d11, 0xf0ae, 0x8111, 0x8111,
+	0x2901, 0xa201, 0x3f11, 0xf04a, 0x2901, 0xe412, 0x1f29, 0x8111,
+	0xe42e, 0x284f, 0xe428, 0x2819, 0xe42a, 0x2840, 0xe428, 0xe41e,
+	0x1f16, 0x4c1a, 0xe42a, 0x2c80, 0x3c50, 0xa200, 0x3c0f, 0x2850,
+	0xa002, 0x2214, 0x4e15, 0xa103, 0xe052, 0x3c50, 0x1c39, 0xe42a,
+	0x281a, 0x4caa, 0xf05a, 0xe41e, 0x1c6e, 0xe41e, 0x1c59, 0x281a,
+	0xf6f8, 0x28ae, 0xa920, 0x3cae, 0x280f, 0xa002, 0x3c0f, 0xa120,
+	0xf062, 0xe41e, 0x05b7, 0xe41e, 0x17cd, 0xf62e, 0xe41e, 0x05b7,
+	0xe41e, 0x19fe, 0x28ae, 0xa908, 0x3cae, 0xe42e, 0xe161, 0x0200,
+	0xe162, 0x02f0, 0x8800, 0x0022, 0xe184, 0x1d36, 0x283f, 0xf0c8,
+	0x2911, 0x3d12, 0x2911, 0x2b11, 0xa107, 0xb612, 0x3d12, 0xa200,
+	0x3d12, 0x3d12, 0xf14e, 0x2911, 0xae02, 0xa002, 0x1842, 0x3d12,
+	0x2911, 0x2b09, 0xa803, 0xb616, 0x3d0a, 0x2912, 0x8112, 0xaa02,
+	0x3d12, 0x2911, 0x2b11, 0xa805, 0xb616, 0x3d12, 0x8111, 0xe161,
+	0x0330, 0xe162, 0x02f0, 0xd022, 0x003f, 0xe184, 0x1d40, 0x2912,
+	0x3d11, 0xe42e, 0x283f, 0xf0d8, 0xe41e, 0x1dbc, 0x2808, 0xe000,
+	0x0370, 0xe096, 0xe41e, 0x1dfe, 0x2808, 0x0809, 0x3c6d, 0xe42e,
+	0xe41e, 0x1dbc, 0xe163, 0x0370, 0x2808, 0xe41e, 0x1ebc, 0x3c08,
+	0xe000, 0x0370, 0xe096, 0xe41e, 0x1dfe, 0x2808, 0xe000, 0x0370,
+	0xe096, 0x2809, 0xe41e, 0x1ebc, 0x0808, 0x3c6d, 0x1842, 0xe400,
+	0x1d79, 0x28ae, 0xa820, 0xe40a, 0x1d79, 0xe163, 0x0370, 0x2842,
+	0xf05a, 0xa23e, 0x3d13, 0xa200, 0x3d13, 0xa23e, 0x3d13, 0xa23c,
+	0x3d13, 0xe42e, 0x283f, 0xf158, 0xe41e, 0x1e37, 0x2808, 0xe000,
+	0x0390, 0xe096, 0xe41e, 0x1dfe, 0x2808, 0xe000, 0x03b0, 0xe096,
+	0xe41e, 0x1dfe, 0x2808, 0x0809, 0x3c6d, 0xe41e, 0x1eff, 0xe42e,
+	0xe41e, 0x1e37, 0xe163, 0x0390, 0x2808, 0xe41e, 0x1ebc, 0xe163,
+	0x03b0, 0x2808, 0xe41e, 0x1ebc, 0x3c08, 0x2808, 0xe000, 0x0390,
+	0xe096, 0xe41e, 0x1dfe, 0x2808, 0xe000, 0x0390, 0xe096, 0x2809,
+	0xe41e, 0x1ebc, 0x2808, 0xe000, 0x03b0, 0xe096, 0xe41e, 0x1dfe,
+	0x2808, 0xe000, 0x03b0, 0xe096, 0x2809, 0xe41e, 0x1ebc, 0x0808,
+	0x3c6d, 0xe41e, 0x1eff, 0xe42e, 0xe161, 0x0600, 0xa200, 0xc70f,
+	0x3d11, 0x283f, 0xb674, 0x3c05, 0xa200, 0x3c08, 0xc420, 0xe163,
+	0x0370, 0xa2fe, 0x3c06, 0xa203, 0xae21, 0xe013, 0xe161, 0x0202,
+	0xe162, 0x0600, 0x8800, 0x0022, 0xe184, 0x1ded, 0x2912, 0xf168,
+	0x2909, 0x1805, 0xf124, 0x2909, 0xf0f6, 0x2901, 0x1c39, 0xf036,
+	0x1014, 0x1c15, 0x0c39, 0xe046, 0xf076, 0xe042, 0xe049, 0xe084,
+	0xe002, 0x0601, 0x3c06, 0x8111, 0x8111, 0x8131, 0x2806, 0xe424,
+	0xe000, 0x0600, 0xe094, 0xa202, 0x3d02, 0x2806, 0xae02, 0x3d13,
+	0x2808, 0xa002, 0x3c08, 0x1819, 0xf4d8, 0xe42e, 0xe161, 0x0600,
+	0xa200, 0xc70f, 0x3d11, 0x283f, 0xb674, 0x3c05, 0xa200, 0x3c09,
+	0xc420, 0xa2fe, 0x3c07, 0xa221, 0xe161, 0x0202, 0xe162, 0x0600,
+	0x8800, 0x0022, 0xe184, 0x1e26, 0x2912, 0xf118, 0x2909, 0x1805,
+	0xf0d4, 0x2909, 0xf0a2, 0x2901, 0xe046, 0xf072, 0xe042, 0xe049,
+	0xe084, 0xe002, 0x0601, 0x3c07, 0x8111, 0x8111, 0x8131, 0x2807,
+	0xe424, 0xe000, 0x0600, 0xe094, 0xa202, 0x3d02, 0x2807, 0xae02,
+	0x3d13, 0x2809, 0xa002, 0x3c09, 0x1819, 0xf548, 0xe42e, 0xe161,
+	0x0600, 0xa200, 0xc70f, 0x3d11, 0x283f, 0xb674, 0x3c05, 0xa200,
+	0x3c0a, 0xc420, 0xe163, 0x0390, 0xe164, 0x03b0, 0xa2fe, 0x3c06,
+	0x3c07, 0xe161, 0x0202, 0xe162, 0x0600, 0xe165, 0x0240, 0x8800,
+	0x0022, 0xe184, 0x1e82, 0x2912, 0xf2c8, 0x2909, 0x1805, 0xf284,
+	0x2909, 0xf256, 0x2115, 0x4d0d, 0x1072, 0x1c73, 0xf110, 0x2806,
+	0xf064, 0x2115, 0x4d0d, 0x100c, 0x1c0d, 0xf196, 0x2115, 0x4d0d,
+	0x340c, 0x3c0d, 0xe084, 0xe002, 0x0601, 0x3c06, 0xf10e, 0x2807,
+	0xf064, 0x2115, 0x4d0d, 0x100e, 0x1c0f, 0xf092, 0x2115, 0x4d0d,
+	0x340e, 0x3c0f, 0xe084, 0xe002, 0x0601, 0x3c07, 0x8111, 0x8111,
+	0x8131, 0x8115, 0x8115, 0x2806, 0xf094, 0xe000, 0x0600, 0xe094,
+	0xa202, 0x3d02, 0x2806, 0xae02, 0x3d13, 0x2807, 0xf094, 0xe000,
+	0x0600, 0xe094, 0xa202, 0x3d02, 0x2807, 0xae02, 0x3d14, 0x280a,
+	0xa002, 0x3c0a, 0x1819, 0xe408, 0x1e46, 0xe086, 0xe002, 0x0390,
+	0x3c0c, 0xe088, 0xe002, 0x03b0, 0x3c0d, 0xf09a, 0xa102, 0xcc44,
+	0xe164, 0x03b0, 0xe184, 0x1ead, 0x2914, 0x3d13, 0x280c, 0xf09a,
+	0xa102, 0xcc44, 0xe163, 0x0390, 0xe184, 0x1eb7, 0x2913, 0x3d14,
+	0x280c, 0x080d, 0x3c08, 0xe42e, 0xe42a, 0xa102, 0x3c0c, 0xe086,
+	0xe098, 0xe161, 0x0600, 0x880c, 0x0022, 0xe184, 0x1ed7, 0x2903,
+	0xae02, 0xe000, 0x0202, 0xe094, 0x2902, 0xa802, 0xf03a, 0x2903,
+	0x3d11, 0x2902, 0xa804, 0xf04a, 0x2903, 0xa002, 0x3d11, 0x8113,
+	0xe082, 0xe002, 0x0600, 0xe42a, 0xa102, 0x3c0c, 0x3c0d, 0x2842,
+	0x3c0e, 0xe161, 0x0600, 0x880c, 0x0022, 0xe184, 0x1eec, 0x2901,
+	0xf044, 0xa802, 0x180e, 0xf06a, 0x8111, 0x280e, 0xe016, 0x3c0e,
+	0xf71e, 0x2901, 0x3d14, 0xa2fe, 0x3d01, 0x280e, 0xe016, 0x3c0e,
+	0x280d, 0xa102, 0x3c0d, 0xf662, 0x280c, 0xa002, 0xe42e, 0x286d,
+	0xa102, 0xe426, 0xcc44, 0xe163, 0x0390, 0xe164, 0x03b0, 0xe184,
+	0x1f0c, 0x2913, 0x1914, 0xe428, 0xe190, 0xe163, 0x0391, 0xe164,
+	0x03b0, 0x290b, 0x3d14, 0x2903, 0x3d14, 0xe42e, 0x2819, 0xe426,
+	0xa102, 0xcc44, 0xc420, 0xe161, 0x0202, 0xe184, 0x1f21, 0x2901,
+	0xe428, 0x8131, 0xe42e, 0xe161, 0x0518, 0xa200, 0xc71f, 0x3d11,
+	0xe42e, 0xe000, 0x0518, 0xe09e, 0x2907, 0xa80c, 0x3d07, 0xe42e,
+	0xe000, 0x0518, 0xe09e, 0x2907, 0xa80a, 0x3d07, 0xe42e, 0x3c81,
+	0xe000, 0x0518, 0xe09e, 0x2907, 0xa806, 0x3d07, 0x2881, 0xa002,
+	0x3c81, 0x187f, 0xe428, 0xa200, 0x3c81, 0xe42e, 0xe161, 0x0518,
+	0x287f, 0xa102, 0xcc44, 0xa201, 0xe184, 0x1f51, 0x2911, 0xa804,
+	0xe01a, 0xe041, 0x1a07, 0xa202, 0xb602, 0xe42e, 0xe161, 0x0518,
+	0x287f, 0xa102, 0xcc44, 0xa200, 0xe184, 0x1f61, 0x2b11, 0xa807,
+	0xe01b, 0xe042, 0x18eb, 0xa102, 0xe01a, 0xe42e, 0xe161, 0x0518,
+	0x287f, 0xa102, 0xcc44, 0xe184, 0x1f70, 0x2911, 0xe016, 0xe428,
+	0xe190, 0xe42e, 0x2881, 0x3c00, 0x2800, 0xe000, 0x0518, 0xe092,
+	0x2901, 0xf10a, 0x2800, 0xa002, 0x3c00, 0x187f, 0xf038, 0xa200,
+	0x3c00, 0x2800, 0x1881, 0xf718, 0xa200, 0x3c81, 0xa2fe, 0x3c84,
+	0xe42e, 0xa20e, 0x3d01, 0x2800, 0x3c84, 0xe42e, 0xe424, 0xc009,
+	0x3c32, 0xc000, 0x2841, 0xc009, 0xa804, 0xe01a, 0x5832, 0xe014,
+	0x2230, 0x4e31, 0xe051, 0x3630, 0x3e31, 0xc000, 0x2841, 0xc009,
+	0xa802, 0x5832, 0xe014, 0x222e, 0x4e2f, 0xe051, 0x362e, 0x3e2f,
+	0xc000, 0xe42e, 0xc009, 0x3c32, 0xa200, 0x2a32, 0xf0c5, 0x222e,
+	0x4e2f, 0x5e32, 0xa803, 0xe056, 0x2230, 0x4e31, 0x5e32, 0xa803,
+	0xae03, 0xe056, 0xc000, 0xe42e, 0xe424, 0xc009, 0x3c32, 0xa202,
+	0x5832, 0x2230, 0x4e31, 0xe055, 0x3630, 0x3e31, 0x222e, 0x4e2f,
+	0xe055, 0x362e, 0x3e2f, 0xc000, 0xe42e, 0xe0c1, 0x0044, 0xa80f,
+	0xe056, 0xe42e, 0xa200, 0xe41e, 0x1fcd, 0xe42e, 0xe0c1, 0x0044,
+	0xaf0d, 0xae03, 0xe056, 0xe008, 0x003f, 0xe42e, 0xe0c1, 0x0044,
+	0xaf17, 0xa803, 0xe42e, 0xe0c1, 0x0044, 0xaf17, 0xa803, 0xa105,
+	0xf039, 0xa213, 0xe42e, 0xa201, 0xe42e, 0xa203, 0xe0c3, 0x040d,
+	0xe0c1, 0x0420, 0xa803, 0xf7db, 0xe160, 0x0003, 0xe166, 0x0640,
+	0xe167, 0x0500, 0x287f, 0xf166, 0xa102, 0xcc44, 0xe184, 0x2010,
+	0xa200, 0xe41e, 0x1fcd, 0xaf04, 0xe41e, 0x1fd6, 0xae20, 0x2e66,
+	0xe056, 0x9f17, 0x2057, 0x4c58, 0xae08, 0x9f17, 0xe41e, 0x2016,
+	0xe190, 0xe190, 0xa201, 0xe0c3, 0x040d, 0xe42e, 0x2116, 0x4d16,
+	0x9f17, 0x2116, 0x4d16, 0x9f17, 0x2116, 0x4d16, 0x9f17, 0xe42e,
+	0xe0c0, 0x0044, 0xaf20, 0xa802, 0xe428, 0xe0c0, 0x0060, 0xa860,
+	0xe42a, 0xe0c0, 0x0061, 0xa83e, 0xa203, 0xe0c3, 0x040d, 0xcca4,
+	0xc785, 0xe018, 0xe000, 0x0500, 0xe09e, 0xe0c1, 0x0420, 0xa803,
+	0xf7db, 0xa200, 0xe41e, 0x1fd2, 0xa80e, 0xaf04, 0xe41e, 0x1fd6,
+	0xe41e, 0x1fde, 0xe40b, 0x2049, 0xa81e, 0xe41e, 0x1fe3, 0xae09,
+	0xe056, 0xae20, 0xe0c1, 0x006e, 0xe009, 0x1fff, 0xe056, 0x9f17,
+	0xe0c0, 0x0060, 0xa822, 0xa122, 0xf04a, 0x2057, 0x4c58, 0xf03e,
+	0x2058, 0x4c57, 0xae08, 0x9f17, 0xe0c0, 0x0062, 0x9f17, 0xe0c0,
+	0x0063, 0x9f17, 0xe0c0, 0x0064, 0x9f17, 0xa201, 0xe0c3, 0x040d,
+	0xe42e, 0x3cec, 0xe0c0, 0x0041, 0xe005, 0x0020, 0xae11, 0xe042,
+	0xce20, 0xd111, 0x0640, 0xd112, 0x00c0, 0x88ec, 0x0113, 0xca29,
+	0xf7f9, 0xe190, 0xe42e, 0xa2fe, 0x3c89, 0xa200, 0x3c88, 0xe42e,
+	0x2856, 0x3c89, 0x2889, 0xf032, 0xa200, 0x3c88, 0xa200, 0x3c8d,
+	0x3c8e, 0x2857, 0x3c8b, 0x2858, 0x3c8c, 0x2888, 0xe42a, 0x2889,
+	0xe424, 0x2889, 0xe0c2, 0x0143, 0x288a, 0xe0c2, 0x0144, 0xa200,
+	0xe0c2, 0x017f, 0xe0c2, 0x0149, 0xe41e, 0x1fcd, 0xe0c2, 0x017f,
+	0x288b, 0xa102, 0xae20, 0x4c8c, 0xa102, 0xe0c2, 0x0142, 0xa200,
+	0xae20, 0x2a87, 0xe042, 0xe0c2, 0x014e, 0xe42e, 0x2889, 0x2a8e,
+	0x1a8c, 0xe423, 0x288d, 0xae0e, 0x4c8e, 0xa203, 0xb615, 0x3e8f,
+	0x2a8f, 0xae03, 0xa903, 0xae1d, 0xe056, 0xe0c1, 0x014b, 0xf7e9,
+	0xe0c2, 0x014d, 0xa202, 0xe0c2, 0x014a, 0x2a8d, 0xa003, 0x3e8d,
+	0x1a8b, 0xf065, 0x2a8e, 0xa003, 0x3e8e, 0xa201, 0x3e8d, 0xe42e,
+	0x2888, 0xf15a, 0x288e, 0x188c, 0xf042, 0xe41e, 0x20ae, 0xf7be,
+	0xe0c0, 0x014b, 0xf7e8, 0xa204, 0xae1c, 0xe0c2, 0x014d, 0xa202,
+	0xe0c2, 0x014a, 0xe190, 0xe0c0, 0x014b, 0xf7e8, 0x2885, 0x3c89,
+	0xe42e, 0xe41e, 0x21c9, 0xe41e, 0x2267, 0xe41e, 0x0f47, 0xe41e,
+	0x2173, 0xe41e, 0x24b1, 0xa200, 0x3c59, 0x3c52, 0xe41e, 0x2368,
+	0x2c59, 0x1c44, 0xe402, 0x216e, 0xe41e, 0x0b72, 0xf12a, 0xa102,
+	0xf15a, 0xa108, 0xf0e4, 0xf12a, 0xa10a, 0xe40a, 0x215d, 0xa102,
+	0xe40a, 0x215d, 0xa102, 0xe40a, 0x214f, 0xa10e, 0xe404, 0x2162,
+	0xe41e, 0x0951, 0xf6ae, 0x2c44, 0x3c52, 0xe41e, 0x098a, 0x284e,
+	0xe01a, 0x2a92, 0xe01b, 0xe05a, 0xe408, 0x2162, 0x284f, 0x1893,
+	0xe408, 0x2162, 0xe41e, 0x0bc5, 0xe41e, 0x22e7, 0xf56a, 0x2894,
+	0xf07a, 0x2c44, 0x3c0d, 0xe41e, 0x23af, 0xe40e, 0x216a, 0xe41e,
+	0x0be2, 0x284e, 0x3c92, 0x284f, 0x3c93, 0xe41e, 0x0d68, 0xe40a,
+	0x20fc, 0xa201, 0x3e94, 0x2c52, 0x3c0d, 0x1c59, 0xe404, 0x20fc,
+	0xe410, 0x23af, 0x2c52, 0x1c44, 0xe402, 0x216e, 0xe41e, 0x05d4,
+	0xf05a, 0xe41e, 0x05f3, 0xe40e, 0x216e, 0xe40e, 0x20f6, 0xe41e,
+	0x098a, 0xba0e, 0xe002, 0x00ff, 0xf058, 0xba4e, 0xe41e, 0x0b96,
+	0xf798, 0xe41e, 0x0cd5, 0xe40e, 0x20fc, 0xe41e, 0x08bd, 0xf03a,
+	0xe41e, 0x01db, 0x2c59, 0x1c44, 0xe402, 0x216a, 0x2c44, 0x3c0d,
+	0xe41e, 0x23af, 0x2892, 0x3c4e, 0x2893, 0x3c4f, 0xe41e, 0x2575,
+	0xcbcc, 0xf7f8, 0xe42e, 0x2822, 0xae02, 0x4c37, 0xae0a, 0x2a36,
+	0xa83f, 0xe056, 0xae0a, 0x2a32, 0xa83f, 0xe056, 0xae02, 0x4c1d,
+	0xae02, 0x4c2d, 0xae02, 0x4c43, 0xcf80, 0x284e, 0xe01a, 0xae02,
+	0x4c1b, 0xae02, 0x4c1d, 0xae02, 0x4c43, 0xcfc2, 0x2857, 0xa102,
+	0xae02, 0x4c34, 0xae02, 0x4c3f, 0xae02, 0x4c42, 0xae02, 0x4c43,
+	0xcf00, 0xd1d3, 0x000b, 0xd185, 0x0001, 0x246e, 0x4c6f, 0xcfc6,
+	0xd1e5, 0x0001, 0xc420, 0xe161, 0x0201, 0xa200, 0xd022, 0x000f,
+	0xe184, 0x21ac, 0x2b31, 0xae02, 0xb42a, 0xcfe8, 0x2072, 0x4c73,
+	0xcfea, 0x2074, 0x4c75, 0xcfec, 0x2076, 0x4c77, 0xcfee, 0xe004,
+	0x0060, 0xcbcf, 0xa803, 0xf03b, 0xe004, 0x0070, 0xce30, 0xe161,
+	0x0260, 0xd022, 0x001f, 0xe184, 0x21c7, 0x2111, 0x4d11, 0xce32,
+	0xe42e, 0xa200, 0xe161, 0x07f6, 0xc707, 0x3d11, 0x2867, 0x4c68,
+	0xf028, 0xe42e, 0xe161, 0x07f6, 0xa20e, 0x3c00, 0x2867, 0xf39a,
+	0x2869, 0x5c00, 0xa802, 0xf108, 0x2a00, 0xa10f, 0xf049, 0xa202,
+	0x3d11, 0xf17e, 0x2a00, 0xa109, 0xf049, 0xa204, 0x3d11, 0xf11e,
+	0xa20a, 0x3d11, 0xf0ee, 0x286b, 0x5c00, 0xa802, 0xf08a, 0x2800,
+	0xa10a, 0xa205, 0xf024, 0xa203, 0x3f11, 0xf03e, 0xa206, 0x3d11,
+	0x2800, 0xa102, 0x3c00, 0xa102, 0xf5c8, 0x2869, 0xe00c, 0x00ff,
+	0x2a6b, 0xe056, 0x5c00, 0xa802, 0xf06a, 0xa203, 0x2800, 0xb655,
+	0x3f11, 0xf03e, 0xa206, 0x3d11, 0x2800, 0xa102, 0x3c00, 0xf6ea,
+	0xe161, 0x07f6, 0xa20e, 0x3c00, 0x2868, 0xe42a, 0x286a, 0x5c00,
+	0xa802, 0xf188, 0x2800, 0xa10e, 0xf088, 0x2a67, 0xf03b, 0x8111,
+	0xf1e9, 0xa202, 0x3d11, 0xf1be, 0x2a00, 0xa109, 0xf089, 0x2a67,
+	0xf03b, 0x8111, 0xf149, 0xa204, 0x3d11, 0xf11e, 0xa20a, 0x3d11,
+	0xf0ee, 0x286c, 0x5c00, 0xa802, 0xf08a, 0x2800, 0xa10a, 0xa205,
+	0xf024, 0xa203, 0x3f11, 0xf03e, 0xa208, 0x3d11, 0x2800, 0xa102,
+	0x3c00, 0xa102, 0xf548, 0x286a, 0x5c00, 0x4c67, 0xa802, 0xf068,
+	0xa203, 0x2800, 0xb655, 0x3f11, 0xf16e, 0x286c, 0xe00c, 0x00ff,
+	0x2a6a, 0xe052, 0x5c00, 0xa802, 0xf0c8, 0x286a, 0x5c00, 0xa802,
+	0xf06a, 0xa203, 0x2800, 0xb655, 0x3f11, 0xf05e, 0x8111, 0xf03e,
+	0xa208, 0x3d11, 0x2800, 0xa102, 0x3c00, 0xf5ea, 0xe42e, 0xa202,
+	0xe0c2, 0x013c, 0xa200, 0x3c00, 0x3c01, 0xe161, 0x07f6, 0xe162,
+	0x04c8, 0x2911, 0xa104, 0xf066, 0xa106, 0xe40a, 0x22b1, 0xa004,
+	0xf112, 0xa004, 0xae06, 0x3c04, 0x2800, 0xa10c, 0xf064, 0x2804,
+	0xae04, 0xe000, 0x0018, 0x3c04, 0xe004, 0x0450, 0x0804, 0x3c04,
+	0xf29e, 0xa201, 0x3e02, 0xa211, 0x3e03, 0xf04a, 0xe005, 0x00e0,
+	0x3e02, 0x2800, 0x2a00, 0xae09, 0xa10c, 0xf05a, 0xa102, 0xf058,
+	0xe005, 0x00a0, 0xa240, 0x3c03, 0x0a02, 0x3e02, 0xe0c0, 0x0041,
+	0xe005, 0x0034, 0xae11, 0xe042, 0x0802, 0xce20, 0xd111, 0x0600,
+	0x2803, 0xce24, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe004, 0x0600,
+	0x3c04, 0x2800, 0xa10c, 0xa20f, 0xf024, 0xa23f, 0xcc45, 0x2804,
+	0xe096, 0xe184, 0x22cb, 0x2912, 0x0801, 0xe0c2, 0x013e, 0x2b03,
+	0xaf11, 0xe0c3, 0x013f, 0x2912, 0x0801, 0xe0c2, 0x013e, 0x2b13,
+	0xe009, 0x00ff, 0xe0c3, 0x013f, 0xe162, 0x04c8, 0x2a01, 0xe001,
+	0x0010, 0x3e01, 0x2800, 0xa002, 0x3c00, 0xa10c, 0xe404, 0x2271,
+	0xe162, 0x04d8, 0xe40a, 0x2271, 0xe001, 0x0030, 0x3e01, 0xa104,
+	0xe408, 0x2271, 0xe16a, 0xa200, 0xe0c2, 0x013c, 0xe42e, 0xa200,
+	0x3c94, 0xe41e, 0x0c8c, 0xe40d, 0x2365, 0x2a43, 0xe419, 0x0e70,
+	0x1c44, 0xe402, 0x2365, 0xbc12, 0xe40d, 0x2365, 0xa10a, 0xb4a8,
+	0xa104, 0xe400, 0x2365, 0xbdfe, 0xe40d, 0x2365, 0x1829, 0xf03a,
+	0xa202, 0x3c94, 0x7413, 0x1839, 0xf03a, 0xa202, 0x3c94, 0x281b,
+	0xf0d8, 0xba40, 0x183f, 0xf03a, 0xa202, 0x3c94, 0x283f, 0xf06a,
+	0xba40, 0x1842, 0xf03a, 0xa202, 0x3c94, 0x284f, 0xf09a, 0xe41e,
+	0x0c8c, 0xe40d, 0x2365, 0x1c45, 0xf03a, 0xa202, 0x3c94, 0x2816,
+	0xa102, 0xf034, 0xf1da, 0xf3ae, 0x7417, 0xe160, 0x0903, 0x1d00,
+	0xf03a, 0xa202, 0x3c94, 0x283f, 0xe016, 0x442a, 0xf2fa, 0xe41e,
+	0x0ca6, 0xf34d, 0xe161, 0x0904, 0xe162, 0x0905, 0x1101, 0x1d02,
+	0xf03a, 0xa202, 0x3c94, 0xf22e, 0xe418, 0x0ca6, 0xf1fe, 0x2818,
+	0xf1d8, 0xe41e, 0x0ca6, 0xf22d, 0xe163, 0x0903, 0xe164, 0x0904,
+	0x1103, 0x1d04, 0xf03a, 0xa202, 0x3c94, 0x283f, 0xe016, 0x442a,
+	0xf0da, 0xe41e, 0x0ca6, 0xf12d, 0xe165, 0x0905, 0xe166, 0x0906,
+	0x1105, 0x1d06, 0xf03a, 0xa202, 0x3c94, 0xe41e, 0x0c0e, 0xae06,
+	0xc873, 0xe046, 0xf034, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e,
+	0xa200, 0xe41e, 0x0c1b, 0xe41e, 0x0c17, 0xf0c8, 0xa202, 0xe41e,
+	0x08df, 0xe41e, 0x0c1b, 0xe41e, 0x08e7, 0xd036, 0x00ff, 0xd037,
+	0x0080, 0xe16a, 0x2c52, 0x3c59, 0xa200, 0x3c0c, 0xe41e, 0x23c6,
+	0x282d, 0xf138, 0x2c59, 0x1c44, 0xf0d2, 0xe41e, 0x240d, 0xf1ed,
+	0x2843, 0xe418, 0x240d, 0xf1ad, 0xcb86, 0xa102, 0xf740, 0xc894,
+	0xf728, 0xe41e, 0x0cd5, 0xe42e, 0xe41e, 0x23f9, 0x2c59, 0x1c44,
+	0xf0a2, 0xe41e, 0x240d, 0xf0ad, 0x2843, 0xe418, 0x240d, 0xf06d,
+	0xbb60, 0xf75a, 0xe41e, 0x0cd7, 0xe42e, 0xe16a, 0xe41e, 0x0b72,
+	0xa116, 0xe428, 0xe41e, 0x08bd, 0xe418, 0x01db, 0xe42e, 0x284f,
+	0xe016, 0x3c38, 0xa202, 0x3c0c, 0xe41e, 0x23c6, 0xa200, 0x3c0c,
+	0x2c59, 0x180d, 0xf0b2, 0xe41e, 0x244d, 0x2843, 0xe418, 0x244d,
+	0x2c53, 0xa002, 0x0843, 0x3c53, 0xf74e, 0xe42e, 0x2832, 0x1836,
+	0xe01a, 0xae04, 0x4c4b, 0xae0a, 0x4c4c, 0xae0a, 0x4c4d, 0xcf30,
+	0x2849, 0xae0a, 0x4c48, 0xae04, 0x4c38, 0xcf82, 0xd1c3, 0x0000,
+	0x284a, 0xcf96, 0x2849, 0xae08, 0x4c48, 0xae02, 0x4c7a, 0xae02,
+	0x4c79, 0xae02, 0x4c78, 0xae02, 0x4c46, 0xae04, 0x4c38, 0xcfc4,
+	0x885e, 0x01fa, 0x2470, 0x4c71, 0xcfc8, 0x280c, 0xf03a, 0x2838,
+	0xf03a, 0xd188, 0x0001, 0x2838, 0xa104, 0xe428, 0xd1e5, 0x0002,
+	0xe42e, 0xc868, 0xa80e, 0x3c9e, 0x749e, 0xe004, 0x01fe, 0xcc86,
+	0xba50, 0xcc88, 0x2838, 0xe01a, 0x0847, 0xae0c, 0x4c4a, 0xcc82,
+	0xd040, 0x0003, 0xc884, 0xf7f8, 0xe42e, 0xd185, 0x0002, 0xd1d0,
+	0x003f, 0xe190, 0xe180, 0xe41e, 0x0c1f, 0xe418, 0x0c7f, 0xe181,
+	0xcba0, 0xa810, 0xcba3, 0xe409, 0x2443, 0xf7b8, 0xe41e, 0x252d,
+	0xcbe0, 0xf7f8, 0x285a, 0xe41a, 0x2554, 0xcba0, 0xcba3, 0xe409,
+	0x2443, 0xf7c8, 0xd186, 0x0001, 0xd185, 0x0004, 0xe41e, 0x256b,
+	0xcb06, 0x3c59, 0xcb8a, 0xaf04, 0x442d, 0xf08a, 0xe004, 0x01fe,
+	0xcc86, 0xba50, 0xcc88, 0xd040, 0x0001, 0xe41e, 0x0c0e, 0xae06,
+	0xc873, 0xe046, 0xe422, 0xd1d0, 0x0000, 0xd1d1, 0x0000, 0xcb1c,
+	0xf7f8, 0xcbe0, 0xf7f8, 0xe16b, 0xe42e, 0xd185, 0x0002, 0xd186,
+	0x0000, 0xd1c2, 0x0001, 0xd1c5, 0x0000, 0xd1c4, 0x0000, 0xd1d0,
+	0x000e, 0xcba0, 0xf7f8, 0x2054, 0x4c55, 0xf098, 0xd1c2, 0x0000,
+	0xd1c5, 0x0003, 0xd1c4, 0x0003, 0xd1c8, 0x0000, 0xd1d0, 0x0020,
+	0xe41e, 0x252d, 0xa200, 0xe0c2, 0x012a, 0xcbe0, 0xf7f8, 0x285a,
+	0xe41a, 0x2554, 0xcba0, 0xf7f8, 0xd186, 0x0001, 0xd185, 0x0004,
+	0xe41e, 0x256b, 0xcb06, 0x3c59, 0xe42e, 0xa200, 0xe0c2, 0x0100,
+	0xe0c2, 0x013d, 0xe0c2, 0x0128, 0xcc8e, 0x2a88, 0xb692, 0xae08,
+	0xa91c, 0xe0c2, 0x017c, 0xa218, 0xe0c2, 0x017d, 0xa200, 0xe41e,
+	0x1fcd, 0x2a22, 0xe017, 0xae09, 0xe056, 0xa203, 0xae11, 0xe056,
+	0xe0c2, 0x0213, 0xa200, 0xe0c2, 0x0215, 0xa202, 0xe0c2, 0x0210,
+	0x2057, 0x4c58, 0xae08, 0xe0c2, 0x0101, 0xe0c2, 0x0205, 0xa200,
+	0xe41e, 0x1fcd, 0x2a22, 0xe017, 0xae07, 0xe056, 0xe0c2, 0x0102,
+	0xe42e, 0xe0c0, 0x0050, 0xe049, 0xe008, 0x007f, 0x3c08, 0xaf11,
+	0xe009, 0x007f, 0x3e09, 0x4608, 0x3e08, 0xa200, 0x2a08, 0xa803,
+	0xf03b, 0xe00a, 0x0002, 0x2a08, 0xa805, 0xf02b, 0xa912, 0x2a08,
+	0xa809, 0xf02b, 0xa940, 0x2a08, 0xa811, 0xf02b, 0xa980, 0xe0c2,
+	0x040c, 0xe0c1, 0x0046, 0xe004, 0x0002, 0xae10, 0xe042, 0x2a09,
+	0xa803, 0xf05b, 0xe161, 0x05cb, 0x2111, 0x4d11, 0xcf0e, 0xe0c1,
+	0x0046, 0xe004, 0x004a, 0xae10, 0xe042, 0x2a09, 0xa805, 0xf05b,
+	0xe161, 0x05cd, 0x2111, 0x4d11, 0xe0c2, 0x0103, 0xe0c1, 0x0046,
+	0xe004, 0x007a, 0xae10, 0xe042, 0x2a09, 0xa809, 0xf05b, 0xe161,
+	0x05cf, 0x2111, 0x4d11, 0xe0c2, 0x0211, 0xe0c1, 0x0046, 0xe004,
+	0x007a, 0xe000, 0x0040, 0xae10, 0xe042, 0x2a09, 0xa811, 0xf05b,
+	0xe161, 0x05d1, 0x2111, 0x4d11, 0xe0c2, 0x0212, 0x2843, 0xae02,
+	0x4c3f, 0xae02, 0x4c42, 0xe0c2, 0x0104, 0xe0c2, 0x0204, 0xa200,
+	0xe0c2, 0x0208, 0xe41e, 0x2579, 0xa20e, 0xe0c2, 0x0312, 0xe0c0,
+	0x0414, 0xe418, 0x018c, 0xe0c0, 0x0414, 0xe41a, 0x25a1, 0xe41e,
+	0x0274, 0xa202, 0xe0c2, 0x0106, 0xe42e, 0xcb02, 0xaf02, 0xe0c2,
+	0x0113, 0xe0c2, 0x030d, 0xcb15, 0xae03, 0xe056, 0xe0c2, 0x022b,
+	0xcb94, 0xe0c2, 0x0115, 0xcba4, 0xe0c2, 0x012a, 0xcb8a, 0xe0c2,
+	0x0114, 0xa802, 0x3c5a, 0xe42a, 0xcb14, 0xae0a, 0xcb19, 0xe056,
+	0xe0c2, 0x0120, 0xcb8c, 0xe0c2, 0x0121, 0xcb8e, 0xe0c2, 0x0122,
+	0xcb90, 0xe0c2, 0x0123, 0xe42e, 0xcbd0, 0xe0c2, 0x030c, 0xcbd2,
+	0xe0c2, 0x0309, 0xcbd8, 0xe0c2, 0x030a, 0xcbda, 0xe0c2, 0x030b,
+	0x285e, 0xe0c2, 0x0320, 0xe42a, 0x285f, 0xe0c2, 0x0321, 0xcbf6,
+	0xe0c2, 0x0322, 0xe42e, 0xe0c0, 0x0111, 0xf7e8, 0xa202, 0xe0c2,
+	0x0110, 0x2888, 0xe418, 0x20ae, 0xe42e, 0xe0c0, 0x0111, 0xf7e8,
+	0xe42e, 0xa202, 0xe0c2, 0x0302, 0xd022, 0x000f, 0xe163, 0x0380,
+	0x2883, 0xb608, 0xe184, 0x2587, 0x9f03, 0x8113, 0x8113, 0x8113,
+	0x2819, 0xf14a, 0xa102, 0xcc44, 0xe160, 0x0004, 0xe161, 0x0203,
+	0xe163, 0x0380, 0xe184, 0x259b, 0x2931, 0xf022, 0x2883, 0xb608,
+	0x9f03, 0x8113, 0x8113, 0x8113, 0xe190, 0xa200, 0xe0c2, 0x0302,
+	0xe42e, 0xe167, 0x01a0, 0x2317, 0x4f17, 0xe0c3, 0x0152, 0x2b17,
+	0xe009, 0x00ff, 0xae21, 0x4f07, 0xe0c3, 0x0153, 0xe0c1, 0x0101,
+	0xe0c3, 0x015d, 0xe162, 0x02b0, 0x2912, 0xaf02, 0x3c0a, 0x2912,
+	0xaf02, 0x3c0b, 0x2838, 0xa104, 0xf068, 0xe162, 0x02d0, 0x2912,
+	0xaf02, 0x3c0b, 0x280a, 0x180b, 0xf0d8, 0xe162, 0x02b0, 0xd022,
+	0x001f, 0xe184, 0x25d0, 0x2912, 0xaf02, 0x3c0b, 0x180a, 0xf028,
+	0xe190, 0x280b, 0xae02, 0xe41e, 0x0f8a, 0xe049, 0xae11, 0x280a,
+	0xae02, 0xe41e, 0x0f8a, 0xe055, 0xae21, 0xe167, 0x01a2, 0x2907,
+	0xaf10, 0xe008, 0x001f, 0xe055, 0xe0c3, 0x015c, 0xa202, 0xe0c2,
+	0x0150, 0xe0c0, 0x0150, 0xf7ea, 0xa200, 0xe0c2, 0x0150, 0xe0c0,
+	0x0151, 0xf7e8, 0xe42e, 0xf044, 0xe41e, 0x1faa, 0xe42e, 0xa200,
+	0xe42e, 0xe165, 0x07e8, 0x284f, 0x3d15, 0x284e, 0x3d15, 0x2838,
+	0x3d15, 0x287e, 0x3d15, 0xe42e, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe40e, 0x0020, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x0330, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x034a, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x003a, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058,
+	0xa200, 0xe0c2, 0x005a, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xa2fe,
+	0x3cee, 0x3cef, 0x3cec, 0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d,
+	0xce00, 0xf33e, 0xe41e, 0x0164, 0xe09e, 0xa202, 0xae3e, 0x9f07,
+	0xe0c0, 0x005c, 0xe0c1, 0x0059, 0x3eed, 0xa203, 0x5aed, 0xe052,
+	0xf08a, 0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00,
+	0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2, 0x0008, 0xf00e,
+	0x28ee, 0xe412, 0x013d, 0xe190, 0xe0c0, 0x005c, 0xe0c1, 0x0059,
+	0x3eed, 0xa203, 0x5aed, 0xe052, 0xf08a, 0xe0c1, 0x005d, 0xe055,
+	0xe0c3, 0x005d, 0xa202, 0xce00, 0xe0c0, 0x004a, 0xf08a, 0xe41e,
+	0x019c, 0xe408, 0x005c, 0xe40e, 0x0058, 0xe190, 0xe0c0, 0x043d,
+	0xa1ee, 0xf7d8, 0xe004, 0x0060, 0xe0c2, 0x0009, 0xa200, 0xe0c2,
+	0x0009, 0xe0c0, 0x000d, 0xf7e8, 0xe41e, 0x00b2, 0xe41e, 0x00e2,
+	0xe41e, 0x012c, 0xd071, 0x242a, 0xe181, 0xe41e, 0x0164, 0xe09e,
+	0xa202, 0x9f07, 0xe0c0, 0x0049, 0xe0c1, 0x005b, 0xa111, 0xf033,
+	0xe0c0, 0x0048, 0xe0c2, 0x0047, 0xe0c0, 0x0059, 0xae02, 0xe000,
+	0x0330, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a, 0xe008, 0xffff,
+	0x3cee, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11, 0xe056, 0x3cef,
+	0xe40e, 0x0058, 0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2,
+	0x0008, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xe0c0, 0x0059, 0xf7ea,
+	0xa11e, 0xf198, 0xa202, 0xe0c2, 0x0058, 0xe004, 0xca20, 0xae20,
+	0xe005, 0x210a, 0xe056, 0xe0c2, 0x0070, 0xe004, 0x0000, 0xae20,
+	0xe00a, 0x9cea, 0xe0c2, 0x0071, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+	0x0058, 0xf64e, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058, 0xd027,
+	0x0001, 0xe42e, 0xa200, 0xe0c1, 0x005b, 0xf21b, 0xa23c, 0xa103,
+	0xf37b, 0xa24c, 0xa103, 0xf34b, 0xa258, 0xa103, 0xf1db, 0xe004,
+	0x003a, 0xa103, 0xf2db, 0xe004, 0x003f, 0xa103, 0xf29b, 0xe004,
+	0x0045, 0xa103, 0xf25b, 0xa103, 0xf14b, 0xe004, 0x0063, 0xa103,
+	0xf1ab, 0xe004, 0x006a, 0xa107, 0xf1bb, 0xa200, 0xe0c1, 0x005e,
+	0xf17b, 0xa028, 0xf15e, 0xe0c1, 0x005e, 0xf12b, 0xa010, 0xf10e,
+	0xe004, 0x0049, 0xe0c1, 0x005e, 0xf0bb, 0xa010, 0xa103, 0xf08b,
+	0xa010, 0xf06e, 0xe0c1, 0x005e, 0xf03b, 0xe004, 0x0074, 0xae16,
+	0xe0c1, 0x0040, 0xe041, 0xce21, 0xd111, 0x0000, 0xd112, 0x2800,
+	0xd113, 0x000b, 0xe1e1, 0xe42e, 0xe41e, 0x023a, 0xe0c0, 0x0059,
+	0xa102, 0xe42a, 0xe0c0, 0x005b, 0xa810, 0xf058, 0xa206, 0xe41e,
+	0x0153, 0xe42e, 0xe004, 0x0350, 0xe67c, 0xe0c0, 0x005b, 0xa810,
+	0xf058, 0xa204, 0xe41e, 0x0153, 0xe42e, 0xe004, 0x0352, 0xe67c,
+	0xa200, 0xc401, 0xe188, 0x00eb, 0x3d11, 0xe161, 0x00f2, 0xe188,
+	0x0b0d, 0x3d11, 0xe42e, 0x3cec, 0xe0c0, 0x0041, 0xe005, 0x0000,
+	0xae11, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0c00, 0x88ec,
+	0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0059, 0xa106, 0xf048,
+	0xe004, 0x0076, 0xe42e, 0xe0c0, 0x0059, 0xa10c, 0xf038, 0xe004,
+	0x0071, 0xe004, 0x0070, 0xe42e, 0xe0c0, 0x006b, 0xe167, 0x01a0,
+	0x3d07, 0xe0c0, 0x0414, 0xe428, 0xe0c1, 0x0044, 0xa809, 0xae33,
+	0xe0c0, 0x006a, 0xe167, 0x01a0, 0x3517, 0x3d17, 0xe0c0, 0x006b,
+	0xe056, 0x3517, 0x3d07, 0xe42e, 0xe167, 0x01a0, 0x2907, 0xe0c2,
+	0x0151, 0xa204, 0xe0c2, 0x0150, 0xe0c0, 0x0150, 0xa804, 0xf7da,
+	0xa208, 0xe0c2, 0x0150, 0xe42e, 0xe0c0, 0x004a, 0xe42a, 0xe0c0,
+	0x005b, 0xa110, 0xf142, 0xe0c0, 0x0059, 0xa102, 0xe41a, 0x01be,
+	0xe0c0, 0x0059, 0xa106, 0xe41a, 0x01cb, 0xe0c0, 0x0047, 0xe0c2,
+	0x0048, 0xa200, 0xe0c2, 0x004a, 0xa202, 0xe42e, 0xe0c0, 0x0047,
+	0xe0c2, 0x0049, 0xa200, 0xe0c2, 0x004a, 0xe42e, 0xe0c0, 0x004a,
+	0xa802, 0xa23e, 0x3cf0, 0xa202, 0x58f0, 0xe0c2, 0x0078, 0xa220,
+	0xe0c2, 0x0070, 0xe42e, 0xe0c0, 0x004a, 0xa802, 0xa220, 0xe0c2,
+	0x0076, 0xa200, 0xe0c2, 0x0072, 0xa2fc, 0xe0c2, 0x0077, 0xa2fa,
+	0xe0c2, 0x0071, 0xe42e, 0xe0c0, 0x0045, 0xaf04, 0xa80e, 0xa104,
+	0xe428, 0xa202, 0xe0c2, 0x004a, 0xe0c0, 0x0111, 0xf7e8, 0xca28,
+	0xf7f8, 0xca48, 0xa802, 0xf7e8, 0xa208, 0xae14, 0xa102, 0xe190,
+	0xf7e2, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xe0c0, 0x041f, 0xf7e8,
+	0xa200, 0xe0c2, 0x041c, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xe004,
+	0x0078, 0xe0c2, 0x0009, 0xa200, 0xe0c2, 0x0009, 0xe0c0, 0x000d,
+	0xf7e8, 0xe42e, 0xc001, 0x3443, 0x3c42, 0xc000, 0xe42e, 0xc001,
+	0x2c43, 0x2e42, 0xc000, 0xe42a, 0x1c1e, 0xf0b4, 0xe04a, 0xaf10,
+	0x1857, 0xf074, 0xe009, 0x00ff, 0x1a58, 0xf034, 0xa202, 0xe42e,
+	0xa2fe, 0xe42e, 0xe41e, 0x023a, 0xd160, 0x0620, 0xe004, 0x0019,
+	0xae18, 0xcec0, 0xe42e, 0xe41e, 0x024f, 0xe000, 0x0040, 0xce50,
+	0xa200, 0xd022, 0x00ff, 0xe184, 0x0236, 0xce52, 0xe190, 0xe41e,
+	0x0257, 0xe42e, 0xa204, 0xae22, 0xcc9e, 0xa200, 0xcc72, 0xcc8c,
+	0xcc8e, 0xe004, 0xa810, 0xae20, 0xe00a, 0x9322, 0xce4a, 0xd16f,
+	0x0003, 0xe190, 0xe190, 0xe190, 0xd16f, 0x0000, 0xe42e, 0xe004,
+	0x0030, 0xce50, 0xca50, 0xa802, 0xf7ea, 0xc000, 0xe42e, 0xe004,
+	0x0020, 0xce50, 0xe42e, 0xa200, 0xe0c2, 0x041c, 0xe42e, 0xe41e,
+	0x02bb, 0xe42a, 0xe0c0, 0x0061, 0xe008, 0x001f, 0xe00a, 0x0100,
+	0xe0c2, 0x041c, 0xe41e, 0x02f1, 0xe41e, 0x032b, 0xae12, 0xe0c2,
+	0x041e, 0xe41e, 0x031b, 0xe42e, 0xe41e, 0x02df, 0xe42a, 0xe0c0,
+	0x041f, 0xf7e8, 0xe0c0, 0x0210, 0xa804, 0xf118, 0xe0c0, 0x0215,
+	0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0216, 0xf0be, 0xe0c0, 0x0213,
+	0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0214, 0xf03e, 0xe0c0, 0x020b,
+	0xe00a, 0x0100, 0xe0c2, 0x041c, 0xe41e, 0x02f1, 0xe41e, 0x032b,
+	0xae12, 0xe0c1, 0x0210, 0xa803, 0xae15, 0xe056, 0xe0c1, 0x0204,
+	0xaf0b, 0xa87f, 0xae07, 0xe056, 0xe0c1, 0x0204, 0xa80f, 0xe056,
+	0xe0c2, 0x041e, 0xe41e, 0x031b, 0xe42e, 0xe0c0, 0x041f, 0xf7e8,
+	0xe0c0, 0x041f, 0xf7e8, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xa200,
+	0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xa203, 0xae19, 0xe052,
+	0xf1da, 0xe0c0, 0x0060, 0xaf08, 0xa806, 0xf18a, 0xe0c0, 0x0060,
+	0xa81e, 0xe016, 0xe0c1, 0x0060, 0xa821, 0xe017, 0xe056, 0xf0ea,
+	0xe0c0, 0x0044, 0xaf12, 0xa806, 0xe016, 0xe0c1, 0x0044, 0xaf17,
+	0xa803, 0xe056, 0xf03a, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xe0c0,
+	0x0044, 0xa203, 0xae19, 0xe052, 0xf0ba, 0xe41e, 0x02bb, 0xf088,
+	0xe0c0, 0x0044, 0xaf12, 0xa806, 0xf038, 0xa202, 0xe42e, 0xa200,
+	0xe42e, 0xe0c0, 0x041c, 0xe008, 0x00ff, 0xcca4, 0xc785, 0xe018,
+	0xe000, 0x0500, 0xa002, 0xae04, 0xe0c2, 0x041a, 0xa202, 0xe0c2,
+	0x0418, 0xe0c0, 0x0419, 0xf7ea, 0xa202, 0xe0c2, 0x0418, 0xe0c0,
+	0x0419, 0xf7ea, 0xe0c0, 0x041b, 0xaf20, 0xa01e, 0xaf08, 0xae28,
+	0xe0c1, 0x041b, 0xe009, 0xffff, 0xa01f, 0xaf09, 0xae09, 0xe056,
+	0xe0c2, 0x041d, 0xe42e, 0xe0c0, 0x041c, 0xe00a, 0x0200, 0xe0c2,
+	0x041c, 0xa228, 0xa102, 0xf7f0, 0xe0c0, 0x041c, 0xe00c, 0x0200,
+	0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xaf04, 0xa802, 0xe42e,
+	0xe40e, 0x0c35, 0xe40e, 0x0354, 0xe40e, 0x0358, 0xe40e, 0x035c,
+	0xe40e, 0x036a, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x0370,
+	0xe40e, 0x0374, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe41e, 0x0398, 0xe40e, 0x00a4,
+	0xe41e, 0x03b9, 0xe40e, 0x00a4, 0xe41e, 0x025b, 0xe41e, 0x0378,
+	0xe41e, 0x0eb9, 0xe41e, 0x045c, 0xe41e, 0x0eb8, 0xe41e, 0x02ad,
+	0xe40e, 0x00a4, 0xe41e, 0x0378, 0xe41e, 0x0535, 0xe40e, 0x00a4,
+	0xe41e, 0x053a, 0xe40e, 0x00a4, 0xe41e, 0x056b, 0xe40e, 0x00a4,
+	0x2811, 0xa184, 0x2a24, 0xa805, 0xe056, 0xe42a, 0xe0c0, 0x0040,
+	0xa201, 0xae17, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x2800,
+	0xd113, 0x000b, 0xe1e1, 0xe42e, 0xe167, 0x05cb, 0xe166, 0x0064,
+	0xd022, 0x0003, 0xe184, 0x0396, 0x9e16, 0x3517, 0x3d17, 0xe42e,
+	0xa200, 0x3c86, 0x3cad, 0x3cbe, 0xe41e, 0x042d, 0xe41e, 0x0558,
+	0xe41e, 0x0672, 0xe41e, 0x08d6, 0xe41e, 0x03ba, 0xf0dd, 0xe41e,
+	0x088b, 0xe41a, 0x03f9, 0xa2fe, 0x3c10, 0x3c83, 0xe41e, 0x0521,
+	0xf03a, 0xa202, 0x3c86, 0xe41e, 0x0b0e, 0xe41e, 0x06e2, 0xe16a,
+	0xe42e, 0xe42e, 0xa23e, 0x3cf0, 0xe41e, 0x088b, 0xe408, 0x03d3,
+	0xe41e, 0x0b48, 0xa10e, 0xf13a, 0xa104, 0xf2ba, 0xa102, 0xf05a,
+	0xf04a, 0xe41e, 0x0923, 0xf6fe, 0xe41e, 0x088b, 0xe408, 0x03d3,
+	0xe41e, 0x095c, 0xf68e, 0xe41e, 0x01db, 0xf22e, 0xe41e, 0x18ab,
+	0xe41e, 0x095c, 0xa2fe, 0x3c10, 0xe41e, 0x1ec1, 0xf5ca, 0x2800,
+	0x3c10, 0xe41e, 0x1ed9, 0xe092, 0xa200, 0xe41e, 0x0c19, 0xa200,
+	0x3c9b, 0xe41e, 0x1870, 0xa2fe, 0x3c10, 0xe082, 0xf096, 0xe42e,
+	0xe41e, 0x18b2, 0xe41e, 0x18ab, 0xe41e, 0x0923, 0xf44e, 0xe16b,
+	0xe42e, 0xe41e, 0x0b48, 0xf0da, 0xa102, 0xe40a, 0x0412, 0xa108,
+	0xf084, 0xf11a, 0xa108, 0xf0f6, 0xa102, 0xf06a, 0xa102, 0xf04a,
+	0xe41e, 0x0923, 0xf6fe, 0xe41e, 0x088b, 0xe408, 0x0412, 0xe41e,
+	0x095c, 0xf68e, 0xe41e, 0x0b3f, 0xe41e, 0x0b36, 0xe42e, 0xa200,
+	0xe161, 0x0100, 0xe188, 0x0aff, 0x3d11, 0xe0c0, 0x0041, 0xe005,
+	0x0034, 0xae11, 0xe042, 0xce20, 0xd111, 0x0100, 0xd112, 0x0180,
+	0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0xe41e, 0x0417, 0xe41e,
+	0x0222, 0xe41e, 0x0148, 0xa204, 0x3cae, 0xe16a, 0xd130, 0x0000,
+	0xd03a, 0x0000, 0xd04c, 0x0000, 0xd008, 0x0000, 0xd022, 0x0000,
+	0xa200, 0xe0c2, 0x0100, 0xe0c2, 0x0128, 0xa2fe, 0x3c25, 0x3c26,
+	0x3c27, 0x3c28, 0x3c10, 0x3c29, 0x3c56, 0xe161, 0x05c7, 0x3511,
+	0x3d11, 0x3511, 0x3d11, 0xe41e, 0x0c04, 0xe41e, 0x1eb0, 0xe41e,
+	0x2179, 0xe41e, 0x1a59, 0xe42e, 0xa200, 0x3c86, 0xe41e, 0x0672,
+	0xe41e, 0x1e75, 0xe41e, 0x04d4, 0xe41e, 0x08e0, 0xe41e, 0x0667,
+	0xe41e, 0x0521, 0xe40a, 0x04d1, 0xe41e, 0x17aa, 0xe408, 0x0476,
+	0xe41e, 0x088b, 0xe408, 0x04d1, 0xe40e, 0x04b8, 0xe41e, 0x020f,
+	0xe404, 0x04b8, 0xe41e, 0x0667, 0xa202, 0x3c86, 0x28bd, 0xf09a,
+	0xe41e, 0x065e, 0xa2fe, 0x3c84, 0xa202, 0x3cb4, 0xe40e, 0x04b8,
+	0xe41e, 0x05c6, 0xf05a, 0xe41e, 0x05e5, 0xe40e, 0x04aa, 0xe41e,
+	0x1ea7, 0x2884, 0xe414, 0x065e, 0x2884, 0xe404, 0x04b8, 0xe41e,
+	0x2300, 0xe41e, 0x05b9, 0x28a5, 0xf0e8, 0x2a4e, 0x4e40, 0x2884,
+	0xe41b, 0x217f, 0x284e, 0xe418, 0x1fe8, 0x2840, 0xe41a, 0x1cfb,
+	0x287e, 0x3c82, 0x2840, 0xf058, 0xe41e, 0x0641, 0xe41e, 0x0646,
+	0xe41e, 0x064b, 0x2840, 0xaa02, 0x443f, 0xf03a, 0xe40e, 0x046c,
+	0xe41e, 0x22e7, 0xe41e, 0x18b2, 0xe41e, 0x08a5, 0xf04a, 0xe41e,
+	0x1e2a, 0x3ce9, 0xe41e, 0x1d24, 0x3c85, 0x2885, 0x3c56, 0x2884,
+	0xf024, 0x3c83, 0xe41e, 0x06e2, 0xe41e, 0x1e90, 0xe41e, 0x0b0e,
+	0xe42e, 0xa202, 0x3c86, 0xf65e, 0xa200, 0xcc4a, 0xcc4c, 0x3c53,
+	0x3c62, 0x3cbd, 0x3cae, 0x3cb4, 0x3ca5, 0x3c97, 0x28ad, 0xe41a,
+	0x0638, 0xe41e, 0x0641, 0xe41e, 0x0646, 0xe41e, 0x064b, 0xe41e,
+	0x0ec4, 0xa2fe, 0x3cba, 0x3cbb, 0x3cb9, 0xa200, 0x3cbc, 0xa204,
+	0x3cf0, 0xa2fc, 0x3c84, 0xa2fa, 0x3c85, 0xa2fe, 0xc009, 0x3c3f,
+	0x3c40, 0x3c41, 0x3c42, 0xc000, 0xe42e, 0x2811, 0xa184, 0xf03a,
+	0xa202, 0xe42e, 0xa200, 0xe42e, 0xa200, 0xcc44, 0xd152, 0x0000,
+	0xd130, 0x0000, 0xd1e0, 0x0003, 0xd1ff, 0x03b0, 0xd1fd, 0x03d0,
+	0xd199, 0x0224, 0xd1fc, 0x0720, 0xd03a, 0x0000, 0xd04c, 0x0000,
+	0xd008, 0x0000, 0xd14b, 0x0200, 0x28b1, 0xcfce, 0xe41e, 0x025f,
+	0xe42e, 0xe0c0, 0x0059, 0xa102, 0xf0da, 0xe41e, 0x088b, 0xf04a,
+	0xe41e, 0x01db, 0xf09e, 0xe41e, 0x21bc, 0x2a84, 0xb7f5, 0x3e84,
+	0xf03a, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xe41e, 0x0672, 0xe41e,
+	0x2292, 0xe42e, 0xe0c0, 0x0042, 0xce20, 0xd111, 0x0000, 0xd112,
+	0x0080, 0xd113, 0x0013, 0xca28, 0xf7f8, 0xe0c0, 0x0061, 0xe41e,
+	0x0be2, 0xa202, 0xe41e, 0x0bec, 0xe41e, 0x09e6, 0xe128, 0xe0c0,
+	0x0060, 0xf048, 0xe41e, 0x1ec1, 0xf03e, 0xe41e, 0x1eec, 0xe42e,
+	0xe0c0, 0x0040, 0xa201, 0xae17, 0xe042, 0xe005, 0x4f00, 0xae03,
+	0xe042, 0xce20, 0xd111, 0x0450, 0xd112, 0x00c8, 0xd113, 0x0003,
+	0xca28, 0xf7f8, 0xe42e, 0xe180, 0xa2fe, 0x3c29, 0x3c10, 0xe41e,
+	0x2179, 0xe41e, 0x05a9, 0x2821, 0xf05a, 0x2816, 0xa104, 0xf02a,
+	0x28ea, 0x3ce9, 0xa200, 0x3c81, 0x3ce7, 0x3ce6, 0x3ce8, 0x3ce5,
+	0xe166, 0x05ab, 0xc710, 0x3d16, 0xe167, 0x0518, 0xe166, 0x0054,
+	0xa200, 0x3cb2, 0x287f, 0xa102, 0xcc44, 0xe184, 0x0596, 0x9e06,
+	0x5cb2, 0xa802, 0xb690, 0x3d17, 0x28b2, 0xa002, 0x3cb2, 0xe190,
+	0xa200, 0x3c60, 0xe41e, 0x0c19, 0xe42e, 0x24b5, 0x4cb6, 0xce20,
+	0xd111, 0x0600, 0xd112, 0x0004, 0xd113, 0x0000, 0xca28, 0xf7f8,
+	0xe42e, 0xe161, 0x0200, 0xa200, 0xc73f, 0x3d11, 0x3cb2, 0xd022,
+	0x001f, 0xe184, 0x05b7, 0xe41e, 0x217f, 0x28b2, 0xa002, 0x3cb2,
+	0xe42e, 0x2abc, 0x4e4f, 0x3ebc, 0x28a1, 0x3cb9, 0x2a3f, 0xf06b,
+	0x2a42, 0xf039, 0x3cba, 0xf02e, 0x3cbb, 0xe42e, 0x28a5, 0xf1c8,
+	0x28a5, 0xe016, 0x4440, 0xf168, 0xe41e, 0x0620, 0xf07a, 0xe41e,
+	0x0625, 0xf07a, 0x284f, 0xf0e8, 0xf0fe, 0xe41e, 0x062a, 0xf04a,
+	0x2838, 0xf0a8, 0xf07e, 0xe41e, 0x0631, 0xf04a, 0x284e, 0xf04a,
+	0xf01e, 0xa200, 0xe42e, 0xa202, 0xe42e, 0xa202, 0x3ca5, 0x2884,
+	0xe412, 0x217f, 0x2884, 0xe412, 0x2186, 0x2884, 0xe412, 0x218d,
+	0xa2fc, 0x3c84, 0x3c3e, 0xe42e, 0xe41e, 0x0b48, 0xf15a, 0xa102,
+	0xf17a, 0xa108, 0xf114, 0xf14a, 0xa102, 0xf0da, 0xa102, 0xf0ba,
+	0xa102, 0xf09a, 0xa102, 0xf07a, 0xa104, 0xf056, 0xa102, 0xf04a,
+	0xa10e, 0xf022, 0xe42e, 0xe41e, 0x0923, 0xe40e, 0x05f4, 0xcaa2,
+	0xaf0a, 0xa806, 0x184e, 0xf0a8, 0xe41e, 0x095c, 0xe41e, 0x2387,
+	0xf5ca, 0x2894, 0xf5aa, 0xe41e, 0x0b3f, 0xe41e, 0x0af7, 0xe42e,
+	0xe0c0, 0x0065, 0xaf04, 0xa802, 0xe42e, 0xe0c0, 0x0065, 0xaf16,
+	0xa802, 0xe42e, 0xe0c0, 0x0065, 0xaf06, 0xa806, 0xa102, 0xe016,
+	0xe42e, 0xe0c0, 0x0065, 0xaf06, 0xa806, 0xa104, 0xe016, 0xe42e,
+	0xe41e, 0x0af7, 0xe0c0, 0x0048, 0xc009, 0x3433, 0x3c34, 0xc000,
+	0xe42e, 0xc009, 0x2433, 0x4c34, 0xc000, 0xe42e, 0xc009, 0x3435,
+	0x3c36, 0xc000, 0xe42e, 0xe41e, 0x0af7, 0xe0c0, 0x0048, 0xc009,
+	0x3437, 0x3c38, 0xc000, 0xe42e, 0xc009, 0x2435, 0x4c36, 0xc000,
+	0xe42e, 0xc009, 0x2437, 0x4c38, 0xc000, 0xe42e, 0xe41e, 0x0b3f,
+	0x28ad, 0xe42a, 0xe41e, 0x0641, 0xe0c2, 0x0048, 0xe42e, 0xe41e,
+	0x2204, 0xe41e, 0x2237, 0xe41e, 0x0504, 0xe41e, 0x24a9, 0xe41e,
+	0x2297, 0xe42e, 0xe0c0, 0x0059, 0xa102, 0xf2ca, 0xa102, 0xe42a,
+	0xa102, 0xf05a, 0xa102, 0xe40a, 0x06b8, 0xe42e, 0xe0c0, 0x006b,
+	0x34b5, 0x3cb6, 0xe0c0, 0x006c, 0x34b7, 0x3cb8, 0xe0c0, 0x0060,
+	0xaf08, 0x3088, 0xe0c0, 0x0060, 0xa81e, 0x3c87, 0xe0c0, 0x0061,
+	0xa83e, 0x3c8a, 0xe0c0, 0x0065, 0xa840, 0xf0ba, 0xa200, 0xe167,
+	0x0600, 0xc703, 0x3d17, 0xe41e, 0x059d, 0xe004, 0x0088, 0x3ca7,
+	0xe42e, 0xc001, 0xe0c0, 0x0060, 0x3400, 0x3c01, 0xe0c0, 0x0061,
+	0xae14, 0x3406, 0x3c07, 0xc000, 0xe0c0, 0x0062, 0xaf02, 0x3021,
+	0xaf02, 0x30aa, 0xa200, 0xe0c0, 0x0067, 0xa802, 0x3cb1, 0xe42e,
+	0xe41e, 0x038c, 0xe41e, 0x0174, 0xe0c0, 0x0042, 0xce20, 0xd111,
+	0x0640, 0xd112, 0x00c0, 0xd113, 0x0003, 0xca29, 0xf7f9, 0xa200,
+	0xe41e, 0x0e9b, 0xe004, 0x0040, 0xe41e, 0x0e9b, 0xe0c0, 0x0060,
+	0x3c7f, 0xe0c0, 0x0061, 0x3c66, 0xe0c0, 0x006e, 0xe41e, 0x020a,
+	0xe167, 0x05fd, 0xe0c0, 0x0062, 0x3517, 0x3d17, 0xe0c0, 0x0063,
+	0x3d17, 0xe42e, 0xe0c0, 0x0059, 0xa102, 0xe40a, 0x077a, 0xa102,
+	0xe42a, 0xa102, 0xf05a, 0xa102, 0xe40a, 0x07e7, 0xe42e, 0x2861,
+	0xae04, 0x4c91, 0xae02, 0x4c90, 0xe0c2, 0x0060, 0xc009, 0x203f,
+	0x4c40, 0xe0c2, 0x0061, 0x2041, 0x4c42, 0xc000, 0xe0c2, 0x0062,
+	0xe41e, 0x1a64, 0xe0c2, 0x0067, 0xe41e, 0x1a69, 0xe0c2, 0x0068,
+	0xe41e, 0x1a6e, 0xe0c2, 0x0069, 0xe41e, 0x1a59, 0x2a23, 0xe41b,
+	0x081d, 0x2a3f, 0xe419, 0x081d, 0xae02, 0x4c23, 0xe0c2, 0x006a,
+	0x2072, 0x4c73, 0xe0c2, 0x006c, 0xe41e, 0x18b5, 0xe0c2, 0x007b,
+	0x2057, 0x4c58, 0xae08, 0xe0c2, 0x006f, 0x28b0, 0xe0c2, 0x007a,
+	0x2054, 0x4c55, 0xa002, 0x3454, 0x3c55, 0xe0c2, 0x0070, 0x2885,
+	0xe0c2, 0x0071, 0x2c53, 0xe0c2, 0x0072, 0xe41e, 0x07e8, 0xe0c2,
+	0x0073, 0xa200, 0xe0c2, 0x0074, 0x2886, 0x2a97, 0xae05, 0xe056,
+	0x2ab4, 0xae21, 0xe056, 0x2aae, 0xae23, 0xe056, 0x2abd, 0xae29,
+	0xe056, 0xe0c2, 0x0076, 0xe41e, 0x0654, 0xe0c2, 0x0051, 0xe41e,
+	0x0659, 0xe0c2, 0x0052, 0x2884, 0xe0c2, 0x0077, 0x2a22, 0xe161,
+	0x05e4, 0x2111, 0x4d11, 0xf02b, 0xae02, 0xe0c2, 0x0078, 0x2111,
+	0x4d11, 0xf02b, 0xae02, 0xe0c2, 0x0079, 0x2025, 0x4c26, 0xe0c2,
+	0x007c, 0xe167, 0x05c7, 0x2117, 0x4d17, 0xe0c2, 0x007e, 0x2117,
+	0x4d17, 0xe0c2, 0x007d, 0xc84a, 0xc84d, 0xae20, 0xe056, 0xe0c2,
+	0x0053, 0xe42e, 0xe41e, 0x18b5, 0xe0c2, 0x0063, 0x2a23, 0xe41b,
+	0x081d, 0x2a3f, 0xe419, 0x081d, 0xae02, 0x4c23, 0xe0c2, 0x0064,
+	0x2027, 0x4c28, 0xe0c2, 0x006d, 0x2886, 0xe0c2, 0x0070, 0x2057,
+	0x4c58, 0xae08, 0xe0c2, 0x0071, 0x2025, 0x4c26, 0xe0c2, 0x0072,
+	0x2821, 0xf0ca, 0x2816, 0xa104, 0xf09a, 0x28eb, 0x3cb3, 0xa004,
+	0xe0c2, 0x0073, 0x28ea, 0x3ce9, 0xf07e, 0x2819, 0xa004, 0xe0c2,
+	0x0073, 0xa200, 0x3ce9, 0x28e9, 0xe0c2, 0x0074, 0xa200, 0xe0c2,
+	0x0075, 0x2a22, 0xe161, 0x05e4, 0x2111, 0x4d11, 0xf02b, 0xae02,
+	0xe0c2, 0x0076, 0x2111, 0x4d11, 0xf02b, 0xae02, 0xe0c2, 0x0077,
+	0x2886, 0xe016, 0x58f0, 0xe0c2, 0x0078, 0xe161, 0x05c7, 0x2111,
+	0x4d11, 0xe0c2, 0x007a, 0x2111, 0x4d11, 0xe0c2, 0x0079, 0xe41e,
+	0x18b5, 0xaf32, 0xa802, 0xae0c, 0x2a24, 0xae05, 0xe056, 0x4c1d,
+	0xae02, 0x2a1b, 0xe017, 0xe056, 0xae10, 0x4c1f, 0xae10, 0x4c11,
+	0x2a19, 0xe01b, 0xae3f, 0xe056, 0xe0c2, 0x007b, 0xe42e, 0xe42e,
+	0x2842, 0x3c00, 0xa200, 0x2a40, 0xf059, 0x2ab9, 0xa80f, 0xe056,
+	0xf12e, 0x2a00, 0xf09b, 0x2aba, 0xa80f, 0xae07, 0xe056, 0x2abb,
+	0xa80f, 0xe056, 0xf08e, 0x2abb, 0xa80f, 0xae07, 0xe056, 0x2aba,
+	0xa80f, 0xe056, 0x3c01, 0x28a3, 0x2a23, 0xe41b, 0x081d, 0x2a3f,
+	0xe419, 0x081d, 0xae02, 0x4c23, 0xae0c, 0x4c00, 0xae04, 0x4c43,
+	0xae02, 0x4c3f, 0xae24, 0x2a3f, 0xe017, 0x4e40, 0xae1f, 0xe056,
+	0x2abc, 0xae0d, 0xe056, 0x4c01, 0xe42e, 0x283f, 0xe42a, 0xc009,
+	0x203b, 0x4c3c, 0x103d, 0x1c3e, 0xc000, 0xf030, 0xa206, 0xe42e,
+	0xa208, 0xe42e, 0x3cec, 0xe0c0, 0x0041, 0xe005, 0x0018, 0xae11,
+	0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0100, 0x88ec, 0x0113,
+	0xca28, 0xf7f8, 0xe42e, 0x8917, 0x0034, 0x8917, 0x0033, 0x8917,
+	0x0035, 0x8917, 0x0036, 0x8917, 0x0037, 0x8917, 0x0038, 0x8117,
+	0x8117, 0x2117, 0x4d17, 0xcc60, 0x2117, 0x4d17, 0xcc62, 0x2117,
+	0x4d17, 0xcc64, 0x2117, 0x4d17, 0xcc72, 0xe42e, 0x8b17, 0x0034,
+	0x8b17, 0x0033, 0x8b17, 0x0035, 0x8b17, 0x0036, 0x8b17, 0x0037,
+	0x8b17, 0x0038, 0x8117, 0x8117, 0xc860, 0x3517, 0x3d17, 0xc862,
+	0x3517, 0x3d17, 0xc864, 0x3517, 0x3d17, 0xc872, 0x3517, 0x3d17,
+	0xe42e, 0xc001, 0x3c13, 0xc000, 0xe42e, 0xc001, 0x2813, 0xc000,
+	0xe42e, 0xc001, 0x3c14, 0xc000, 0xe42e, 0xc001, 0x2814, 0xc000,
+	0xe42e, 0xc001, 0x2430, 0x4c31, 0xc000, 0xae06, 0xc873, 0xe046,
+	0xe422, 0xe16b, 0xe42e, 0xc001, 0x280c, 0xf16a, 0xe41e, 0x0af7,
+	0xc001, 0xe0c0, 0x0049, 0x340e, 0x3c0f, 0x240e, 0x4c0f, 0xe0c1,
+	0x0048, 0x360e, 0x3e0f, 0x260e, 0x4e0f, 0xe045, 0xa200, 0xb626,
+	0xe003, 0x0200, 0xb606, 0xc000, 0xe42e, 0xe41e, 0x088b, 0xe42a,
+	0xe0c0, 0x0045, 0xaf04, 0xa802, 0xe42e, 0xc001, 0x3c33, 0xc000,
+	0xe42e, 0xc001, 0x2833, 0xc000, 0xe42e, 0xc001, 0x3c11, 0xc000,
+	0xe42e, 0xc001, 0x2811, 0xc000, 0xe42e, 0xd148, 0x0040, 0xd144,
+	0x0000, 0xd145, 0x0000, 0xd168, 0x0000, 0xd16b, 0x0000, 0xd14b,
+	0x0200, 0xc001, 0xa200, 0x3c34, 0xc000, 0xe004, 0x0019, 0xae18,
+	0xcec0, 0xd14c, 0x000c, 0xca9a, 0xf7f8, 0xe42e, 0xc001, 0x2400,
+	0x4c01, 0x0406, 0x0c07, 0x3408, 0x3c09, 0xd071, 0x202a, 0xe181,
+	0xc001, 0xe0c0, 0x0048, 0x3415, 0x3c16, 0x280c, 0xf13a, 0xe0c0,
+	0x0048, 0x340e, 0x3c0f, 0x240e, 0x4c0f, 0xe0c1, 0x0049, 0x3604,
+	0x3e05, 0x1404, 0x1c05, 0xe0c1, 0x0045, 0xaf05, 0xa803, 0xb611,
+	0x320c, 0xe0c0, 0x0048, 0x3402, 0xe008, 0xfe00, 0x3c03, 0xe0c0,
+	0x0048, 0xe008, 0x01ff, 0x3c0b, 0xa200, 0xcc78, 0xd022, 0x00ff,
+	0xe184, 0x090b, 0xcc7a, 0xe190, 0xe41e, 0x09e6, 0xe41e, 0x0a05,
+	0xe41e, 0x08bd, 0xc001, 0xa200, 0x3c1a, 0x280b, 0xa102, 0xe412,
+	0x092b, 0xc001, 0xa202, 0x3c1a, 0xa200, 0xceaa, 0xc000, 0xa200,
+	0xe41e, 0x0c19, 0xe42e, 0xcaa0, 0xe190, 0xca9a, 0xf7f8, 0xca9c,
+	0xe418, 0x0a05, 0xe42e, 0xcc44, 0xe184, 0x0934, 0xca9c, 0xe418,
+	0x0a05, 0xcaa0, 0xca9b, 0xf7f9, 0xe190, 0xe42e, 0xe004, 0x0100,
+	0xceb0, 0xe004, 0x00ff, 0xe014, 0xceb8, 0xd15d, 0x0000, 0xd15e,
+	0x0000, 0xd15f, 0x0000, 0xe004, 0x0019, 0xae18, 0xe00a, 0x0620,
+	0xcec0, 0xd157, 0x0000, 0xd14a, 0x0000, 0xd14c, 0x0003, 0xca9c,
+	0xe418, 0x0a05, 0xca9a, 0xf7c8, 0xcaae, 0xa802, 0xf73a, 0xca9c,
+	0xe418, 0x0a05, 0xa200, 0xe42e, 0xe41e, 0x0bde, 0xe408, 0x0bba,
+	0xe41e, 0x0936, 0xe41e, 0x088b, 0xf128, 0xe41e, 0x0b36, 0xcaa2,
+	0xe008, 0x00ff, 0xe41e, 0x0871, 0xaf0e, 0xe418, 0x0923, 0xe41e,
+	0x0875, 0xaf0e, 0xf6e8, 0xe41e, 0x088b, 0xf0ea, 0xe004, 0x010b,
+	0xe008, 0x00ff, 0xe41e, 0x0871, 0xe004, 0x010b, 0xa83e, 0xe41e,
+	0x0879, 0xa200, 0xe42e, 0xe41e, 0x0875, 0xf058, 0xa204, 0xe41e,
+	0x092b, 0xf57e, 0xa206, 0xe41e, 0x092b, 0xe41e, 0x0875, 0xaf0a,
+	0x3c4e, 0xe41e, 0x0875, 0xa83e, 0xe41e, 0x0879, 0xe41e, 0x0875,
+	0xa116, 0xe42a, 0xca9c, 0xe418, 0x0a05, 0xe41e, 0x087d, 0xa10a,
+	0xe016, 0x3c4f, 0xe41e, 0x09a5, 0xe42e, 0xc001, 0xa200, 0x3c30,
+	0x3c31, 0x3c33, 0xe41e, 0x09b5, 0xc001, 0xe41e, 0x09e6, 0xc001,
+	0xe128, 0xa200, 0x3c38, 0xc000, 0xe42e, 0xc001, 0x2833, 0x4411,
+	0xc000, 0xae0e, 0xce92, 0xd14a, 0x0000, 0xd158, 0x0000, 0xe004,
+	0x01ff, 0xe014, 0xceb8, 0xd15d, 0x0000, 0xd15e, 0x0000, 0xd15f,
+	0x0000, 0xd161, 0x0003, 0xe004, 0x0019, 0xae18, 0xe00a, 0x0638,
+	0xcec0, 0xd14c, 0x0003, 0xca9c, 0xe418, 0x0a05, 0xca9a, 0xf7c8,
+	0xca9c, 0xf7a8, 0xca9e, 0xc001, 0x3c32, 0xcc92, 0xca94, 0x0030,
+	0x0c31, 0x3430, 0x3c31, 0xcc90, 0xc000, 0xe42e, 0xe004, 0x1495,
+	0xae20, 0xcc9e, 0xd030, 0x0000, 0xd034, 0x0000, 0xd033, 0x0000,
+	0xd035, 0x0000, 0xd036, 0x007f, 0xd037, 0x0000, 0xd038, 0x0000,
+	0xd039, 0x0000, 0xd04b, 0x0001, 0xd04c, 0x0000, 0xd046, 0x0000,
+	0xd047, 0x0000, 0xd149, 0x0000, 0xe42e, 0xc001, 0x280c, 0xf20a,
+	0xe41e, 0x024f, 0xc001, 0xe004, 0x0440, 0xce50, 0x280d, 0xa806,
+	0xa108, 0xe012, 0xa806, 0xae06, 0x3c40, 0xe004, 0x010b, 0x5840,
+	0xce52, 0xe41e, 0x0257, 0xc001, 0xd14e, 0x0000, 0xd144, 0x0000,
+	0x2402, 0x4c03, 0xe000, 0x0200, 0x3402, 0x3c03, 0xf3ae, 0xd027,
+	0x0000, 0x280c, 0xe41a, 0x0a6e, 0xc001, 0xd027, 0x0001, 0x280d,
+	0xf25a, 0xca48, 0xa802, 0xf7e8, 0x2402, 0x4c03, 0xce40, 0xd121,
+	0x0000, 0xd122, 0x0040, 0xe0c0, 0x0043, 0xa806, 0xae02, 0xa032,
+	0xce46, 0xe190, 0xe190, 0xe190, 0xe190, 0xca48, 0xa802, 0xf7e8,
+	0xe004, 0x0200, 0x0402, 0x0c03, 0x3402, 0x3c03, 0x1408, 0x1c09,
+	0xf054, 0x2400, 0x4c01, 0x3402, 0x3c03, 0x280c, 0xe418, 0x0ab2,
+	0xc001, 0xe41e, 0x0af7, 0xc001, 0xd14e, 0x0000, 0xd144, 0x0000,
+	0xc000, 0xe42e, 0xe0c1, 0x0059, 0xa103, 0xa200, 0xb636, 0xe000,
+	0x001c, 0xe0c1, 0x0045, 0xe052, 0xe01a, 0xe42e, 0xc001, 0xa200,
+	0x3c0a, 0xe004, 0x0200, 0x3c0d, 0xe0c0, 0x0043, 0xa808, 0xf338,
+	0xe41e, 0x0a62, 0xc001, 0x3c0c, 0x2402, 0x4c03, 0xe0c1, 0x0049,
+	0x3604, 0x3e05, 0x2604, 0x4e05, 0xe045, 0xf033, 0x0606, 0x0e07,
+	0xe003, 0x0200, 0x280c, 0xb602, 0x3c0c, 0xf1d3, 0xe001, 0x0200,
+	0x3e0d, 0x280c, 0xf188, 0x280a, 0xe408, 0x0a78, 0xe41e, 0x01db,
+	0xc001, 0xe0c0, 0x005c, 0xe008, 0x4000, 0xe40a, 0x0a78, 0xe0c0,
+	0x005d, 0xe00a, 0x4000, 0xe0c2, 0x005d, 0xa202, 0xce00, 0x3c0a,
+	0xe40e, 0x0a78, 0x280d, 0x2a0c, 0xf039, 0xe004, 0x0200, 0x3c0d,
+	0xc000, 0xe42e, 0xc001, 0xe41e, 0x024f, 0xc001, 0x280d, 0xe002,
+	0x0200, 0xe40a, 0x0af4, 0x280d, 0xa806, 0xf1fa, 0xa108, 0xe012,
+	0xae06, 0x3c40, 0x280d, 0xaf04, 0xae20, 0xe000, 0x01c0, 0xce50,
+	0xe190, 0xca52, 0x5c40, 0x5840, 0x2a0d, 0xa807, 0xae07, 0x3e40,
+	0xe005, 0x010b, 0x5e40, 0xe056, 0x2a0d, 0xaf05, 0xae21, 0xe001,
+	0x0140, 0xce51, 0xe190, 0xce52, 0xe004, 0x01fc, 0x180d, 0xf022,
+	0xf14e, 0xc001, 0x280d, 0xa006, 0xaf04, 0xae20, 0xe000, 0x0440,
+	0xce50, 0x280d, 0xa806, 0xa108, 0xe012, 0xa806, 0xae06, 0x3c40,
+	0xe004, 0x010b, 0x5840, 0xce52, 0xc000, 0xe40e, 0x0257, 0xc001,
+	0xcaaa, 0x2a1a, 0xb616, 0xe0c1, 0x0048, 0x360e, 0x3e0f, 0x260e,
+	0x4e0f, 0xe042, 0xe049, 0x1608, 0x1e09, 0xf035, 0x1406, 0x1c07,
+	0xe0c2, 0x0048, 0xa200, 0xceaa, 0xc000, 0xe42e, 0xe41e, 0x0af7,
+	0xe0c0, 0x0045, 0xaf04, 0xa806, 0xa104, 0xe428, 0xa2fc, 0x2a84,
+	0xa003, 0xb616, 0xe418, 0x0b1d, 0xe42e, 0xc001, 0x3c40, 0xe0c0,
+	0x0048, 0x340e, 0x3c0f, 0x240e, 0x4c0f, 0x0840, 0xe049, 0x1600,
+	0x1e01, 0xf033, 0x0406, 0x0c07, 0xe049, 0x1608, 0x1e09, 0xf035,
+	0x1406, 0x1c07, 0xe0c2, 0x0048, 0xc000, 0xe42e, 0xe41e, 0x0af7,
+	0xc001, 0xe0c0, 0x0048, 0x3417, 0x3c18, 0xc000, 0xe42e, 0xa200,
+	0xceaa, 0xc001, 0x2417, 0x4c18, 0xc000, 0xe0c2, 0x0048, 0xe42e,
+	0xe41e, 0x0936, 0xe41e, 0x088b, 0xf0f8, 0xcaa2, 0xe049, 0xa83e,
+	0xe009, 0x00ff, 0xf03b, 0xaf0f, 0xf04b, 0xe41e, 0x0923, 0xf71e,
+	0xe41e, 0x088b, 0xf0aa, 0xe004, 0x010b, 0xe008, 0x00ff, 0xe41e,
+	0x0871, 0xe004, 0x010b, 0xf02e, 0xcaa2, 0xe008, 0x001f, 0xe41e,
+	0x0879, 0xe41e, 0x087d, 0xe42e, 0xc001, 0x2832, 0xe016, 0xc871,
+	0xa011, 0xf288, 0xaf07, 0xe009, 0x07ff, 0x2831, 0xe008, 0x07ff,
+	0xe046, 0xf16a, 0xf0ee, 0xc001, 0xe161, 0x0601, 0x2901, 0xc871,
+	0xa011, 0xaf07, 0xe009, 0x07ff, 0xe008, 0x07ff, 0xe046, 0xf08a,
+	0xe049, 0xe011, 0xaf15, 0xf0e1, 0xf0d0, 0xa200, 0xf0be, 0xc868,
+	0xa80e, 0xf028, 0xa210, 0x3c35, 0x7835, 0xa203, 0x5a35, 0xaf03,
+	0xe046, 0xc000, 0xe42e, 0xc000, 0x284e, 0x2a4f, 0x3c95, 0x3e96,
+	0xc001, 0x2831, 0x2a32, 0x3c36, 0x3e37, 0xa202, 0x3c34, 0xe0c0,
+	0x0046, 0xe005, 0x0000, 0xae11, 0xe042, 0xce20, 0xd111, 0x0000,
+	0xd112, 0x0080, 0xd113, 0x0012, 0xca28, 0xf7f8, 0xca2c, 0xf7fa,
+	0xc000, 0xe42e, 0xc000, 0x2895, 0x2a96, 0x3c4e, 0x3e4f, 0xc001,
+	0x2836, 0x2a37, 0x3c31, 0x3e32, 0xcc90, 0xcc93, 0xa200, 0x3c34,
+	0x3c30, 0x3c33, 0xe0c0, 0x0046, 0xe005, 0x0000, 0xae11, 0xe042,
+	0xce20, 0xd111, 0x0000, 0xd112, 0x0080, 0xd113, 0x0013, 0xca28,
+	0xf7f8, 0xe41e, 0x09e6, 0xe128, 0xc000, 0xe42e, 0xc001, 0x2834,
+	0xc000, 0xe42e, 0xc001, 0x3430, 0x3c31, 0xc000, 0xe42e, 0xc001,
+	0x2430, 0x4c31, 0xc000, 0xe42e, 0xc001, 0x3c32, 0xc000, 0xe42e,
+	0xc001, 0x2832, 0xc000, 0xe42e, 0xc001, 0x3c10, 0xc000, 0xe42e,
+	0xc001, 0x2810, 0xc000, 0xe42e, 0xc001, 0x3c38, 0xc000, 0xe42e,
+	0xc001, 0x2838, 0xc000, 0xe42e, 0xc001, 0xe0c0, 0x0041, 0xe005,
+	0x0039, 0xae11, 0xe042, 0x3420, 0x3c21, 0xe004, 0x04e1, 0xae10,
+	0x3422, 0x3c23, 0xc000, 0xe42e, 0xc001, 0x2420, 0x4c21, 0xc000,
+	0xe42e, 0x3c63, 0xe08e, 0x3c64, 0xe41e, 0x0c25, 0xe41e, 0x0c2d,
+	0x2864, 0xe09e, 0x2863, 0x3c60, 0xe42e, 0x2860, 0xae08, 0xe000,
+	0x0538, 0xe09e, 0xe41e, 0x0856, 0xe42e, 0x2863, 0xae08, 0xe000,
+	0x0538, 0xe09e, 0xe41e, 0x083b, 0xe42e, 0x2860, 0xf0ca, 0xa102,
+	0xe40a, 0x1f23, 0xa102, 0xe40a, 0x1f23, 0xe41e, 0x1020, 0xd04c,
+	0x0000, 0xe470, 0xe41e, 0x0bf0, 0xf088, 0xe41e, 0x0c00, 0xf088,
+	0xe41e, 0x0eca, 0xe41e, 0x09b5, 0xd04c, 0x0000, 0xe470, 0xe41e,
+	0x1003, 0xe41e, 0x08b9, 0xf098, 0xa202, 0xe41e, 0x08b5, 0xd037,
+	0x0000, 0xd04c, 0x0000, 0xe470, 0xa200, 0xe41e, 0x08b5, 0xd037,
+	0x0080, 0xd04c, 0x0000, 0xe470, 0xe40e, 0x1f23, 0xe41e, 0x1020,
+	0xd04c, 0x0000, 0xe470, 0xc001, 0xa200, 0x3c10, 0xe41e, 0x1003,
+	0xc001, 0x2832, 0xcc96, 0x2811, 0xe016, 0x3c11, 0xc000, 0xe42e,
+	0xba0c, 0xf03a, 0xbcfc, 0xe42e, 0xba4c, 0xa20c, 0x3c9d, 0x289d,
+	0xa002, 0x3c9d, 0xa140, 0xf0d2, 0xba40, 0xf7aa, 0x589d, 0xa102,
+	0x34ab, 0x3cac, 0x289d, 0xe41e, 0x0cb5, 0x00ab, 0x0cac, 0xe42e,
+	0xe16b, 0xe42e, 0xba0c, 0xf03a, 0xbe7e, 0xe42e, 0xba4c, 0xa20c,
+	0x3c9d, 0x289d, 0xa002, 0x3c9d, 0xa140, 0xf162, 0xba40, 0xf7aa,
+	0x589d, 0xa102, 0x34ab, 0x3cac, 0x289d, 0xe41e, 0x0cb5, 0x00ab,
+	0x0cac, 0x3cac, 0x8cac, 0x0000, 0xa002, 0xaf02, 0xe012, 0xe42c,
+	0xe012, 0xe16a, 0xe42e, 0xe16b, 0xe42e, 0xa120, 0xf050, 0xa020,
+	0x3c9e, 0x749e, 0xe42e, 0x3c9e, 0xba5e, 0x589e, 0x769e, 0xe056,
+	0xe42e, 0xba40, 0xe42a, 0xc868, 0xa80e, 0x3c00, 0xe016, 0xe428,
+	0x7400, 0xe016, 0xe42e, 0xe0c4, 0x3fff, 0xe40d, 0x0db6, 0x3c52,
+	0xf048, 0xa200, 0xa2fe, 0x3ca1, 0xbc12, 0xe40d, 0x0db6, 0xa10a,
+	0xb4a8, 0xa104, 0xe400, 0x0db6, 0xb7b4, 0xa006, 0x3c38, 0x60a1,
+	0x3ca1, 0xbdfe, 0xe40d, 0x0db6, 0x2a51, 0xf09b, 0xe049, 0x1829,
+	0xf06a, 0x3e29, 0xe41e, 0x1f03, 0xe40a, 0x0db6, 0x7413, 0x3c39,
+	0xa200, 0x3c3f, 0x3c42, 0x281b, 0xf068, 0xba40, 0x3c3f, 0xf03a,
+	0xba40, 0x3c42, 0x2851, 0xf2da, 0x2c1e, 0x5c3f, 0x3c44, 0xa200,
+	0x3c40, 0x283a, 0xf05a, 0xe41e, 0x0db9, 0x3c40, 0xf148, 0x283f,
+	0x3c3a, 0x284e, 0xe01a, 0x3c3b, 0x2839, 0x3c3c, 0x2842, 0x3c3d,
+	0xa2fc, 0x3c3e, 0x284e, 0xf098, 0x2850, 0x1c39, 0xf06a, 0xa202,
+	0x3cbe, 0xf03e, 0xa200, 0x3c3a, 0x2c52, 0xf038, 0x2840, 0xf018,
+	0x283f, 0xe016, 0x441c, 0x3c43, 0x283f, 0x0842, 0xb674, 0x3c41,
+	0x284f, 0xf06a, 0xe41e, 0x0c78, 0xe40d, 0x0db6, 0x3c45, 0xe41e,
+	0x1ca7, 0x2835, 0xf07a, 0xe41e, 0x0c78, 0xe40d, 0x0db6, 0xe408,
+	0x0db6, 0x2838, 0xa104, 0xf038, 0xba40, 0x3c46, 0x282c, 0x3c48,
+	0x282e, 0x3c49, 0x2838, 0xf0ea, 0xba40, 0xf0ca, 0xbc3e, 0x3c48,
+	0xe40d, 0x0db6, 0x2838, 0xa104, 0xf058, 0xbc3e, 0x3c49, 0xe40d,
+	0x0db6, 0x2851, 0xf05a, 0xe41e, 0x1fd7, 0xe41e, 0x0dd5, 0x2838,
+	0xe016, 0xe41a, 0x0ddc, 0xe40a, 0x0db6, 0x2851, 0xf06a, 0xe41e,
+	0x1b80, 0xe40a, 0x0db6, 0xf1fe, 0x284e, 0xf1da, 0x284f, 0xf04a,
+	0xba40, 0xba40, 0xf18e, 0xba40, 0xf16a, 0xbc0c, 0xe40d, 0x0db6,
+	0xf12a, 0xa106, 0xf08a, 0xa104, 0xf79a, 0xe41e, 0x0c78, 0xe40d,
+	0x0db6, 0xf74e, 0xe41e, 0x0c78, 0xe40d, 0x0db6, 0xbc40, 0xe40d,
+	0x0db6, 0xf6ce, 0x2838, 0xe01a, 0x442d, 0xf03a, 0xbc04, 0xf2fd,
+	0x3c47, 0xe0c6, 0x0033, 0xf2bd, 0x0831, 0xa400, 0xa566, 0x3c4a,
+	0xa200, 0x3c4b, 0x3c4c, 0x3c4d, 0x2833, 0xf10a, 0xbc04, 0xf1fd,
+	0x3c4b, 0xa102, 0xf0ba, 0xbe0c, 0xf1ad, 0xae02, 0xa83e, 0x3c4c,
+	0xbe0c, 0xf15d, 0xae02, 0xa83e, 0x3c4d, 0x282b, 0xf07a, 0x2851,
+	0xf038, 0x74de, 0xf03e, 0xe41e, 0x1278, 0x2a43, 0x2c52, 0xe419,
+	0x0dce, 0x3c52, 0x1c44, 0xf032, 0xa202, 0xe42e, 0xe16a, 0xa200,
+	0xe42e, 0x284f, 0xe016, 0xe42a, 0x283f, 0xe42a, 0x283a, 0xe42a,
+	0x283d, 0x1842, 0xe42a, 0x284e, 0xf048, 0x283b, 0xe016, 0xe42e,
+	0x283b, 0xe42a, 0x283c, 0x1839, 0xe016, 0xe42e, 0xe049, 0xc70f,
+	0x7e57, 0xaf21, 0xae02, 0xe046, 0xe42e, 0xd1f3, 0x0000, 0xe162,
+	0x0370, 0x2912, 0xcfe4, 0xe42e, 0x2848, 0x3c04, 0xe161, 0x0370,
+	0xe162, 0x02b0, 0xe41e, 0x0df1, 0xe42a, 0xd1f3, 0x0000, 0xe162,
+	0x02b0, 0x8848, 0x0022, 0xe184, 0x0dee, 0x2912, 0xcfe4, 0xa202,
+	0xe42e, 0xe082, 0xe098, 0xba40, 0xf098, 0x8804, 0x0022, 0xe184,
+	0x0dfa, 0x2911, 0x3d12, 0xa202, 0xe42e, 0x286d, 0xe082, 0x3c08,
+	0x2014, 0x4c15, 0x3400, 0x3c01, 0x2c39, 0x3402, 0x3c03, 0x2804,
+	0x3c05, 0xe163, 0x0600, 0xa200, 0xc71f, 0x3d13, 0xbc06, 0xe40d,
+	0x0e5a, 0xf06a, 0xa102, 0xf13a, 0xa102, 0xf1ba, 0xf32e, 0xe41e,
+	0x0c78, 0xe40d, 0x0e5a, 0xa002, 0x1002, 0x1c03, 0xe012, 0xf032,
+	0x0000, 0x0c01, 0x3402, 0x3c03, 0xa203, 0xf0de, 0xe41e, 0x0c78,
+	0xe40d, 0x0e5a, 0xa002, 0x0002, 0x0c03, 0x1000, 0x1c01, 0xf70e,
+	0xbc40, 0xa2ff, 0x3c0f, 0xe41e, 0x0e64, 0xf082, 0xa203, 0x283f,
+	0xf03a, 0x2a0f, 0xa803, 0x2904, 0xe046, 0xf1d4, 0x3d12, 0xe41e,
+	0x0e7f, 0x2805, 0xa102, 0x3c05, 0xa004, 0xe42a, 0xe40e, 0x0e0e,
+	0x2808, 0xa102, 0xe092, 0xe163, 0x0600, 0x2805, 0xf0a4, 0x2913,
+	0x8111, 0xf7e8, 0x2901, 0x3d12, 0x2805, 0xa102, 0x3c05, 0xf76e,
+	0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0x2884, 0xe424, 0xe0c2,
+	0x020b, 0xe0c2, 0x0214, 0xe42e, 0x3c06, 0x3e07, 0xe163, 0x0330,
+	0x2819, 0xa102, 0xe424, 0xae02, 0xa002, 0xcc44, 0xe184, 0x0e7c,
+	0x2d13, 0x2b0b, 0x1c06, 0x1a07, 0xf078, 0xf069, 0xe086, 0xe002,
+	0x0330, 0xaf02, 0xe42e, 0x8113, 0x8113, 0xa2fe, 0xe42e, 0x3c09,
+	0x2808, 0xe092, 0x286d, 0xa102, 0xcc44, 0xe184, 0x0e8a, 0x2901,
+	0x1809, 0xf03a, 0x8111, 0xe42e, 0xe082, 0x1808, 0xe000, 0x0600,
+	0xe096, 0xa202, 0x3d03, 0xe42e, 0xaf02, 0xae04, 0xe000, 0x0203,
+	0xe09e, 0x2907, 0xe42e, 0x3c0a, 0xe0c0, 0x0042, 0xe000, 0x0180,
+	0x080a, 0xa207, 0xe41e, 0x0eaf, 0xe0c0, 0x0041, 0xe005, 0x006c,
+	0xae0f, 0x0a0a, 0xe042, 0xa205, 0xe41e, 0x0eaf, 0xe42e, 0xce20,
+	0xd111, 0x0600, 0xd112, 0x0020, 0xce27, 0xca28, 0xf7f8, 0xe42e,
+	0xe42e, 0xd1f3, 0x0000, 0xe167, 0x02b0, 0xd022, 0x001f, 0xe184,
+	0x0ec2, 0x2917, 0xcfe4, 0xe42e, 0xa200, 0xe41e, 0x109d, 0xe41e,
+	0x10a5, 0xe42e, 0x2862, 0xe42a, 0xe41e, 0x10aa, 0xe167, 0x05fd,
+	0x2717, 0x4f17, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0000,
+	0xd112, 0x0080, 0xd113, 0x0012, 0xca28, 0xf7f8, 0xca2c, 0xf7fa,
+	0xa204, 0x3c62, 0xe42e, 0xe161, 0x0600, 0x2c52, 0x3d11, 0xe41e,
+	0x10aa, 0xae10, 0x3511, 0x3d11, 0xe161, 0x05ff, 0x2f01, 0xae15,
+	0xaf10, 0xe045, 0xe003, 0x0200, 0xa200, 0xb62e, 0x3c97, 0xf357,
+	0x2862, 0xa104, 0xf098, 0xe41e, 0x10aa, 0xe000, 0x0200, 0xe41e,
+	0x10a5, 0xa200, 0x3c62, 0xe41e, 0x10aa, 0xe161, 0x05fd, 0x2711,
+	0x4f11, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0000, 0xd112,
+	0x0080, 0xd113, 0x0012, 0xca28, 0xf7f8, 0xca2c, 0xf7fa, 0xe41e,
+	0x10aa, 0xe000, 0x0200, 0xe41e, 0x10a5, 0xe161, 0x05ff, 0x2f01,
+	0xae15, 0xe045, 0xe41e, 0x0bf0, 0xf088, 0xa200, 0xb62e, 0x3c97,
+	0xf047, 0xe41e, 0x09b5, 0xf58e, 0xe161, 0x0602, 0xe41e, 0x0be7,
+	0xaf20, 0xe008, 0x00ff, 0x4d01, 0x3d11, 0xe41e, 0x0be7, 0x3d01,
+	0xe161, 0x0601, 0x2711, 0x4f11, 0xaf11, 0xe41e, 0x0be7, 0xe042,
+	0xa00e, 0xa20f, 0xe015, 0xe052, 0xe41e, 0x10a5, 0xe41e, 0x10a1,
+	0xe41e, 0x1043, 0xe41e, 0x10a1, 0xa002, 0xe41e, 0x109d, 0xe42e,
+	0x3c00, 0xe41e, 0x10a1, 0xe40a, 0x0fb5, 0xa102, 0x3c04, 0xe161,
+	0x0600, 0xe004, 0x270f, 0x3c02, 0xa2fe, 0x3c03, 0xe41e, 0x1057,
+	0x2901, 0x1800, 0xf12a, 0x2901, 0x1802, 0xf052, 0x2901, 0x3c02,
+	0x2804, 0x3c03, 0x2804, 0xa102, 0x3c04, 0xf712, 0x2803, 0xe404,
+	0x0fb5, 0x3c04, 0xe41e, 0x1057, 0xa200, 0xe41e, 0x08b5, 0x2901,
+	0x3c52, 0xe004, 0x270f, 0x3d11, 0x2111, 0x4d09, 0xaf10, 0xe41e,
+	0x1077, 0x2804, 0xe41e, 0x1043, 0xe004, 0x0000, 0xe005, 0x007f,
+	0xe41e, 0x106c, 0x2111, 0x4d01, 0xaf10, 0xe000, 0x0200, 0xe41e,
+	0x10af, 0x2911, 0xe008, 0x00ff, 0xae20, 0x4d01, 0xe41e, 0x0be2,
+	0xcc90, 0xe002, 0x0200, 0xe41e, 0x10b9, 0xb604, 0xb628, 0xe41e,
+	0x0bec, 0xcc92, 0xa202, 0xe41e, 0x0bfc, 0xe41e, 0x0bf0, 0xe428,
+	0xa202, 0xe41e, 0x08b5, 0xe41e, 0x1003, 0xa200, 0xe41e, 0x08b5,
+	0xd036, 0x00ff, 0xd037, 0x0080, 0xe42e, 0x2c44, 0x3c52, 0xe42e,
+	0x3c00, 0x3e01, 0xe04a, 0xe41e, 0x10c3, 0xe41e, 0x10a1, 0xf0ea,
+	0xa102, 0x3c04, 0xe161, 0x0600, 0xe41e, 0x1057, 0x2901, 0x1800,
+	0xf07a, 0x2804, 0xa102, 0x3c04, 0xf782, 0xa200, 0xe42e, 0xca28,
+	0xf7f8, 0xe004, 0x270f, 0x3d11, 0x2111, 0x4d09, 0xaf10, 0x2a01,
+	0xe41e, 0x108c, 0x2804, 0xe41e, 0x1043, 0x2801, 0xae0a, 0xe000,
+	0x0000, 0xa23f, 0xe41e, 0x106c, 0x2801, 0xae04, 0xe000, 0x0410,
+	0xe094, 0x2111, 0x4d01, 0xaf10, 0xe000, 0x0080, 0x3512, 0x3d12,
+	0x2911, 0xe008, 0x00ff, 0xae20, 0x4d01, 0xe41e, 0x0be2, 0xcc90,
+	0xe002, 0x0080, 0x3512, 0x3d12, 0xb604, 0xb628, 0xe41e, 0x0bec,
+	0xcc92, 0xa202, 0xe42e, 0xd115, 0x0001, 0xe190, 0xca28, 0xf7f8,
+	0xe41e, 0x10b4, 0xe41e, 0x1077, 0xd115, 0x0000, 0xe41e, 0x10b4,
+	0xe000, 0x0200, 0xe41e, 0x10af, 0xe41e, 0x10be, 0xe002, 0x0200,
+	0xe41e, 0x10b9, 0xb604, 0xb628, 0xe41e, 0x0bec, 0xcc92, 0xe42e,
+	0xe082, 0x3ce4, 0xca28, 0xf7f8, 0xe41e, 0x10c7, 0xe049, 0xae04,
+	0xe000, 0x0410, 0xe092, 0x2111, 0x4d09, 0xe41e, 0x108c, 0x2111,
+	0x4d09, 0xe000, 0x0080, 0x3511, 0x3d11, 0x2111, 0x4d09, 0xe002,
+	0x0080, 0x3511, 0x3d11, 0xb604, 0xb628, 0xe41e, 0x0bec, 0xcc92,
+	0x28e4, 0xe092, 0xe42e, 0xae06, 0xe005, 0x0142, 0xae11, 0xe042,
+	0xe0c1, 0x0046, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0600,
+	0xd112, 0x0004, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0x2804,
+	0xae06, 0xe005, 0x0142, 0xae11, 0xe042, 0xe0c1, 0x0046, 0xe042,
+	0xca29, 0xf7f9, 0xce20, 0xd111, 0x0600, 0xd112, 0x0004, 0xd113,
+	0x0003, 0xca28, 0xf7f8, 0xe42e, 0xcc66, 0xcc6a, 0xcc6e, 0xe042,
+	0xcc6c, 0xa200, 0xcc60, 0xcc68, 0xcc70, 0xe128, 0xe42e, 0xe167,
+	0x05fd, 0x2717, 0x4f17, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xe41e,
+	0x08b9, 0xe005, 0x0080, 0xb615, 0xce23, 0xd112, 0x0080, 0xd113,
+	0x0013, 0xca28, 0xf7f8, 0xe42e, 0xae0b, 0xe001, 0x0000, 0xce23,
+	0xe167, 0x05fd, 0x2717, 0x4f17, 0xe042, 0xce20, 0xd112, 0x0020,
+	0xd113, 0x0013, 0xca28, 0xf7f8, 0xe42e, 0xc009, 0x3c20, 0xc000,
+	0xe42e, 0xc009, 0x2820, 0xc000, 0xe42e, 0xc009, 0x341e, 0x3c1f,
+	0xc000, 0xe42e, 0xc009, 0x241e, 0x4c1f, 0xc000, 0xe42e, 0xc009,
+	0x3422, 0x3c23, 0xc000, 0xe42e, 0xc009, 0x2422, 0x4c23, 0xc000,
+	0xe42e, 0xc009, 0x3424, 0x3c25, 0xc000, 0xe42e, 0xc009, 0x2424,
+	0x4c25, 0xc000, 0xe42e, 0xc009, 0x3c21, 0xc000, 0xe42e, 0xc009,
+	0x2821, 0xc000, 0xe42e, 0xe41e, 0x10a1, 0xe40a, 0x10dc, 0xa102,
+	0x3c04, 0xe161, 0x0600, 0xe41e, 0x1057, 0x2901, 0x1852, 0xf07a,
+	0x2804, 0xa102, 0x3c04, 0xf782, 0xa200, 0xe42e, 0xa202, 0xe42e,
+	0xa206, 0xe41e, 0x0c19, 0xe004, 0x004e, 0xe0c2, 0x017c, 0xa218,
+	0xe0c2, 0x017d, 0xa200, 0x3cdf, 0x3ce0, 0xe41e, 0x113c, 0x28e0,
+	0xa002, 0x3ce0, 0x18d7, 0xf7a4, 0xa200, 0x3c59, 0x3c5b, 0x3c5c,
+	0xe41e, 0x1133, 0x3ce0, 0x2c59, 0x1c44, 0xe402, 0x112f, 0xe41e,
+	0x1133, 0x3cd9, 0x18e0, 0xe418, 0x11e7, 0x28d9, 0x3ce0, 0x28df,
+	0xe41a, 0x11ec, 0xe41e, 0x1214, 0x28df, 0xf07a, 0xe41e, 0x2450,
+	0xf0cc, 0xe16a, 0xa200, 0x3cdf, 0x284f, 0xe016, 0x3c38, 0xe41e,
+	0x2479, 0x2c53, 0xa002, 0x3c53, 0xe41e, 0x1235, 0xcb04, 0x345b,
+	0x3c5c, 0x28df, 0xe40a, 0x10fb, 0xcb86, 0xa102, 0xf550, 0xc894,
+	0xf538, 0xe41e, 0x0cc1, 0xa200, 0x3cdf, 0xe40e, 0x10fb, 0xa200,
+	0xe41e, 0x0c19, 0xe42e, 0x285b, 0xe41a, 0x1240, 0xe004, 0x0390,
+	0x085b, 0xe094, 0x2902, 0xe42e, 0xe161, 0x04b0, 0x2838, 0x3d11,
+	0x2848, 0x3d11, 0x284a, 0x3d11, 0x284b, 0x3d11, 0x284c, 0x3d11,
+	0x284d, 0x3d11, 0xcb86, 0x3d11, 0xcb96, 0x3d11, 0x28df, 0x3d11,
+	0xe41e, 0x0be7, 0x3511, 0x3d11, 0xe41e, 0x0bf0, 0x3d11, 0xe162,
+	0x02b0, 0xd022, 0x000f, 0xe184, 0x115e, 0x2912, 0x3d11, 0x8b11,
+	0x0034, 0x8b11, 0x0033, 0xc860, 0x3511, 0x3d11, 0xc862, 0x3511,
+	0x3d11, 0xc864, 0x3511, 0x3d11, 0x8b11, 0x0035, 0x8b11, 0x0036,
+	0x8b11, 0x0037, 0x8b11, 0x0038, 0x28e0, 0xae0e, 0xe005, 0x00fa,
+	0xae11, 0xe042, 0xe0c1, 0x0046, 0xe042, 0xca29, 0xf7f9, 0xce20,
+	0xd111, 0x04b0, 0xd112, 0x0028, 0xd113, 0x0002, 0xca28, 0xf7f8,
+	0xe42e, 0x28d9, 0xae0e, 0xe005, 0x00fa, 0xae11, 0xe042, 0xe0c1,
+	0x0046, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x04b0, 0xd112,
+	0x0028, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe161, 0x04b0, 0x2911,
+	0x3c38, 0x2911, 0x3c48, 0x2911, 0x3c4a, 0x2911, 0x3c4b, 0x2911,
+	0x3c4c, 0x2911, 0x3c4d, 0xe41e, 0x2435, 0x2911, 0xcf86, 0x2911,
+	0xcf96, 0x2911, 0x3cdf, 0x2511, 0x4d11, 0xe41e, 0x0be2, 0xcc90,
+	0x2911, 0xe41e, 0x0bec, 0xcc92, 0xe162, 0x02b0, 0xd022, 0x000f,
+	0xe184, 0x11c3, 0x2911, 0x3d12, 0xd1f3, 0x0000, 0xe162, 0x02b0,
+	0x8848, 0x0022, 0xe184, 0x11cd, 0x2912, 0xcfe4, 0x28d9, 0xe41e,
+	0x10c3, 0x8911, 0x0034, 0x8911, 0x0033, 0x2111, 0x4d11, 0xcc60,
+	0x2111, 0x4d11, 0xcc62, 0x2111, 0x4d11, 0xcc64, 0x8911, 0x0035,
+	0x8911, 0x0036, 0x8911, 0x0037, 0x8911, 0x0038, 0xe42e, 0xe41e,
+	0x113c, 0xe41e, 0x1189, 0xe42e, 0x2c59, 0x2ad9, 0xe41e, 0x0fb8,
+	0xe42a, 0xe41e, 0x0ccb, 0xe16a, 0xe42a, 0xe41e, 0x2435, 0xe41e,
+	0x11fc, 0xa202, 0x3cdf, 0xe42e, 0xa203, 0x5ad9, 0xe00d, 0x00ff,
+	0xe161, 0x0430, 0x8857, 0x0022, 0xe184, 0x1208, 0x2901, 0xe052,
+	0x3d11, 0x28e1, 0xe052, 0x3ce1, 0x28e2, 0xe052, 0x3ce2, 0xe42e,
+	0xa200, 0x3ce1, 0x3ce2, 0xe42e, 0x285b, 0xe41a, 0x1210, 0x285b,
+	0xe000, 0x0430, 0xe092, 0x28e1, 0x5cd9, 0xa802, 0x3ce3, 0x2911,
+	0x5cd9, 0xa802, 0xae02, 0x4ce3, 0x3ce3, 0x2911, 0x5cd9, 0xa802,
+	0xae04, 0x4ce3, 0x3ce3, 0x28e2, 0x5cd9, 0xa802, 0xae06, 0x4ce3,
+	0x3ce3, 0xcf12, 0xd18a, 0x0000, 0xe42e, 0x285b, 0xe000, 0x0430,
+	0xe092, 0x2901, 0x3ce2, 0xa202, 0x58d9, 0x3d01, 0x3ce1, 0xe42e,
+	0x285c, 0xae10, 0xe005, 0x00fe, 0xae11, 0xe042, 0xe0c1, 0x0046,
+	0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0390, 0x2857, 0xa006,
+	0xe008, 0x00fc, 0xce24, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e,
+	0x3cd8, 0xa002, 0x3cd7, 0x2c1e, 0x3c44, 0xbc0c, 0x3cd6, 0xe42d,
+	0xe40a, 0x1299, 0xa102, 0xe40a, 0x12d1, 0xa102, 0xe40a, 0x12ee,
+	0xa106, 0xe406, 0x1270, 0xa102, 0xe40a, 0x13d8, 0xe16b, 0xe42e,
+	0xba40, 0x3cda, 0xe41e, 0x0c78, 0xe42d, 0xa002, 0x3cdb, 0xe42e,
+	0xa200, 0x3cde, 0x28d6, 0xa106, 0xe424, 0xa104, 0xe420, 0x2c44,
+	0x08db, 0xa102, 0xc70f, 0x7cdb, 0xe008, 0xffff, 0xe41e, 0x1412,
+	0x3cde, 0x74de, 0x3cdc, 0x84dc, 0x82db, 0xe018, 0x2e44, 0xe066,
+	0x3cdc, 0x28d6, 0xa108, 0xe404, 0x1340, 0xe40a, 0x13ae, 0xe40e,
+	0x13ae, 0xe161, 0x0600, 0x88d8, 0x0022, 0xe184, 0x12a3, 0xe41e,
+	0x0c78, 0xe42d, 0xa002, 0x3d11, 0xe161, 0x0600, 0xe162, 0x0390,
+	0xa200, 0x3cd9, 0x3c00, 0x3c5b, 0x3c5c, 0x2800, 0xa002, 0x3c00,
+	0x1901, 0xf0e6, 0xa200, 0x3c00, 0x28d9, 0xa002, 0x3cd9, 0x8111,
+	0x18d8, 0xf746, 0xa200, 0x3cd9, 0xe161, 0x0600, 0xf6fe, 0x28d9,
+	0x3d12, 0x285b, 0xa002, 0x3c5b, 0x1857, 0xf684, 0x3c5b, 0xe41e,
+	0x13f6, 0x285c, 0xa002, 0x3c5c, 0x1858, 0xe162, 0x0390, 0xf5e4,
+	0xe42e, 0xa200, 0x3c5c, 0xe162, 0x0390, 0x845c, 0x82d7, 0xe018,
+	0xaf02, 0xc70f, 0x7cd7, 0xaf20, 0x2a57, 0xa103, 0xcc45, 0xe184,
+	0x12e5, 0x3d12, 0xa002, 0xe049, 0x1ad7, 0xb616, 0xe41e, 0x13f6,
+	0x285c, 0xa002, 0x3c5c, 0x1858, 0xf674, 0xe42e, 0xe167, 0x0600,
+	0x28d8, 0xa102, 0xcc44, 0xe184, 0x12fc, 0xe41e, 0x0c78, 0xe42d,
+	0x3d17, 0xe41e, 0x0c78, 0xe42d, 0x3d17, 0xe162, 0x0390, 0x2857,
+	0xa102, 0x3c04, 0x28d7, 0xa102, 0x8604, 0x3d12, 0xa200, 0x3c5c,
+	0xe41e, 0x13f6, 0x285c, 0xa002, 0x3c5c, 0x1858, 0xf7a4, 0x28d7,
+	0xa104, 0x3cd9, 0x28d9, 0xae02, 0xe000, 0x0600, 0xe092, 0x2911,
+	0xc70f, 0x7c57, 0x3400, 0x3c02, 0x2911, 0xc70f, 0x7c57, 0x3401,
+	0x3c03, 0x2802, 0x3c5c, 0x1803, 0xf170, 0xca2c, 0xf7fa, 0xe41e,
+	0x13f8, 0x2800, 0xe000, 0x0390, 0xe094, 0x2801, 0x1800, 0xf054,
+	0x3c04, 0x28d9, 0x8604, 0x3d12, 0xe41e, 0x13f6, 0x285c, 0xa002,
+	0x3c5c, 0x1803, 0xf6d6, 0x28d9, 0xa102, 0x3cd9, 0xf542, 0xe42e,
+	0xe162, 0x09e0, 0xa2fe, 0x2e1e, 0xa01f, 0xaf09, 0x3e00, 0x8600,
+	0x3d12, 0x8457, 0x28dc, 0xe40a, 0x1397, 0x2857, 0x18da, 0xaf02,
+	0x3c5b, 0x2858, 0x18da, 0xaf02, 0x3c5c, 0x2857, 0xa102, 0x3c07,
+	0x2858, 0xa102, 0x3c08, 0xa2fe, 0x08da, 0x3c04, 0xa200, 0x08da,
+	0x3c05, 0xa200, 0x3c00, 0x3c01, 0x3c02, 0xa202, 0x3c03, 0xe41e,
+	0x1419, 0xf0aa, 0x2901, 0xe05a, 0x3d01, 0x2800, 0xa002, 0x3c00,
+	0x2800, 0x18dc, 0xf25a, 0x285b, 0x0804, 0xa400, 0x6407, 0x3c5b,
+	0x285c, 0x0805, 0xa400, 0x6408, 0x3c5c, 0x2802, 0xa002, 0x3c02,
+	0x1803, 0xf668, 0x3c02, 0x2803, 0x0801, 0x3c03, 0xa202, 0x1801,
+	0x3c01, 0x28da, 0xf078, 0x2804, 0x2a05, 0xe013, 0x3e04, 0x3c05,
+	0xf57e, 0x2804, 0x2a05, 0xe012, 0x3e04, 0x3c05, 0xf51e, 0xa200,
+	0x3c5c, 0xe162, 0x0390, 0xa200, 0x3c5b, 0xe41e, 0x1419, 0xe01a,
+	0x3d12, 0x285b, 0xa002, 0x3c5b, 0x1857, 0xf784, 0xe41e, 0x13f6,
+	0x285c, 0xa002, 0x3c5c, 0x1858, 0xf6d4, 0xe42e, 0x28da, 0xf038,
+	0x28dc, 0xf03e, 0x2c44, 0x18dc, 0x3c00, 0xa200, 0x3c5c, 0xe162,
+	0x0390, 0xa200, 0x3c5b, 0x8457, 0x825c, 0xe018, 0x085b, 0x2ad6,
+	0xa109, 0xf05b, 0x8458, 0x825b, 0xe018, 0x085c, 0x1800, 0x2ada,
+	0xf024, 0xe017, 0x3f12, 0x285b, 0xa002, 0x3c5b, 0x1857, 0xf6c4,
+	0xe41e, 0x13f6, 0x285c, 0xa002, 0x3c5c, 0x1858, 0xf614, 0xe42e,
+	0xe41e, 0x0c78, 0xe42d, 0xa002, 0x1c44, 0xe408, 0x126e, 0x28d8,
+	0xe41e, 0x1412, 0x3c00, 0xa200, 0x3c5c, 0xe162, 0x0390, 0x2857,
+	0xa102, 0xcc44, 0xe184, 0x13ed, 0x7400, 0x3d12, 0xe41e, 0x13f6,
+	0x285c, 0xa002, 0x3c5c, 0x1858, 0xf714, 0xe42e, 0xa204, 0xf02e,
+	0xa206, 0x3c09, 0x285c, 0xae10, 0xe005, 0x00fe, 0xae11, 0xe042,
+	0xe0c1, 0x0046, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0390,
+	0x2857, 0xa006, 0xe008, 0x00fc, 0xce24, 0x8809, 0x0113, 0xca28,
+	0xf7f8, 0xe42e, 0xa201, 0xf04a, 0xaf02, 0xa003, 0xf7e8, 0xe04a,
+	0xe42e, 0x825c, 0xe018, 0x085b, 0x3c59, 0xaf08, 0xe000, 0x09e0,
+	0xe092, 0x2c59, 0xa81e, 0x3c06, 0xa203, 0x5a06, 0x2901, 0xe052,
+	0xe42e, 0xba4e, 0x3c11, 0xa200, 0x3c24, 0xd022, 0x0007, 0xe184,
+	0x1436, 0xba41, 0x5a24, 0xe056, 0x2a24, 0xa003, 0x3e24, 0x3c24,
+	0xa208, 0x3cf0, 0x2824, 0xaf0c, 0xe408, 0x1540, 0xa224, 0x3cf0,
+	0xe41e, 0x179b, 0xe40a, 0x1543, 0xa226, 0x3cf0, 0xba4e, 0x3c1f,
+	0xa112, 0xe404, 0x1540, 0xa154, 0xe400, 0x1540, 0xbc3e, 0x3c10,
+	0xa202, 0x3c22, 0xa200, 0x3c67, 0x2811, 0xa1c8, 0xf338, 0xbc06,
+	0x3c22, 0xa20a, 0x3cf0, 0xbc08, 0xe408, 0x1540, 0xa20c, 0x3cf0,
+	0xbc08, 0xe408, 0x1540, 0xba40, 0xba40, 0x3c67, 0xf23a, 0xa201,
+	0x3e69, 0x3e6b, 0xe160, 0x0000, 0xba40, 0xf11a, 0x2a69, 0xae03,
+	0xe056, 0x3c69, 0xe080, 0xe41e, 0x1746, 0x2a6b, 0xae03, 0xe056,
+	0x3c6b, 0xe080, 0xa201, 0xe41e, 0x1779, 0xf07e, 0x2a69, 0xae03,
+	0x3e69, 0x2a6b, 0xae03, 0x3e6b, 0xe080, 0xa002, 0xe090, 0xa110,
+	0xf648, 0xa20e, 0x3cf0, 0xbc18, 0xe40d, 0x1540, 0xa008, 0x3c13,
+	0xa202, 0x5813, 0x3414, 0x3c15, 0xa210, 0x3cf0, 0xbc04, 0x3c16,
+	0xe40d, 0x1540, 0xa102, 0xf034, 0xf0aa, 0xf33e, 0xa212, 0x3cf0,
+	0xbc18, 0xe40d, 0x1540, 0xa008, 0x3c17, 0xf2be, 0xba40, 0x3c18,
+	0xe41e, 0x0c92, 0xe160, 0x0907, 0xe161, 0x0908, 0x3500, 0x3d01,
+	0xe41e, 0x0c92, 0xe162, 0x0909, 0xe163, 0x090a, 0x3502, 0x3d03,
+	0xa214, 0x3cf0, 0xbdfe, 0xe40d, 0x1540, 0xe164, 0x090b, 0x3d04,
+	0xf10a, 0xa102, 0xcc44, 0xe162, 0x09e0, 0xe184, 0x14ca, 0xe41e,
+	0x0c92, 0x3512, 0x3d12, 0xa216, 0x3cf0, 0xe41e, 0x1672, 0xf01e,
+	0xe40d, 0x1540, 0xa218, 0x3cf0, 0xbc20, 0xe40d, 0x1540, 0x3c19,
+	0xba40, 0x3c1a, 0xa21a, 0x3cf0, 0xbdfe, 0xe40d, 0x1540, 0xa002,
+	0x3c57, 0xa21c, 0x3cf0, 0xbdfe, 0xe40d, 0x1540, 0xa002, 0x3c58,
+	0x8457, 0x8258, 0xe018, 0x3c1e, 0xa222, 0x3cf0, 0x2c57, 0xe002,
+	0x0080, 0xe400, 0x1540, 0x2c58, 0xe002, 0x0080, 0xe400, 0x1540,
+	0x2c1e, 0xe002, 0x4000, 0xe400, 0x1540, 0xa200, 0x3c1c, 0xba40,
+	0x3c1b, 0xf098, 0xba40, 0x3c1c, 0x2858, 0xae02, 0x3c58, 0x2c1e,
+	0xae02, 0x3c1e, 0xe41e, 0x15f2, 0xa21e, 0x3cf0, 0x2a1b, 0xba40,
+	0xb636, 0x3c1d, 0xa220, 0x3cf0, 0xba40, 0xe161, 0x05e4, 0xc703,
+	0x3d11, 0xf16a, 0xe161, 0x05e4, 0xe41e, 0x0c78, 0x3d11, 0xe41e,
+	0x0c78, 0x3d11, 0xe41e, 0x0c78, 0x2a1b, 0xf029, 0xae02, 0x3d11,
+	0xe41e, 0x0c78, 0x2a1b, 0xf029, 0xae02, 0x3d11, 0xf12d, 0xa200,
+	0x3c90, 0x3c91, 0x2820, 0x3cea, 0x3ceb, 0xe41e, 0x18ba, 0xba40,
+	0xe016, 0xe41a, 0x1682, 0xf05a, 0xe41e, 0x0cc1, 0xa202, 0xe42e,
+	0xe16a, 0xa200, 0xe42e, 0xa2fe, 0xe42e, 0xe41e, 0x0c78, 0x3c29,
+	0xbc3e, 0xe40d, 0x15e8, 0x1810, 0xf11a, 0x0810, 0x3c10, 0xe41e,
+	0x1ed9, 0x3c65, 0xa205, 0xae23, 0xcc9f, 0xa202, 0xe41e, 0x0c19,
+	0xa203, 0x3e9b, 0x2865, 0xe40a, 0x15e8, 0xba40, 0x3c2d, 0xba40,
+	0x3c2a, 0xbc0e, 0xe40d, 0x15e8, 0x3c2b, 0xf05a, 0xe41e, 0x1258,
+	0xe40d, 0x15e8, 0x282d, 0x2a2b, 0xe01b, 0xe052, 0xe408, 0x15e8,
+	0x2811, 0xa184, 0xf078, 0x282d, 0xf0aa, 0xe004, 0x0064, 0x3c11,
+	0xf06e, 0x282b, 0xf04a, 0xe004, 0x0042, 0x3c11, 0xbc3e, 0xe40d,
+	0x15e8, 0x3c2c, 0xbc3e, 0x3c2e, 0xe40d, 0x15e8, 0xba40, 0x3c2f,
+	0xba42, 0x3c30, 0xbe34, 0xe40d, 0x15e8, 0xa034, 0x3c31, 0xe404,
+	0x15e8, 0xa168, 0xe402, 0x15e8, 0xbe34, 0xe40d, 0x15e8, 0xa034,
+	0xe404, 0x15e8, 0xa168, 0xe402, 0x15e8, 0xbe18, 0xe40d, 0x15e8,
+	0x3c32, 0x3c36, 0xba40, 0x3c33, 0xba40, 0x3c34, 0xba40, 0x3c35,
+	0xa200, 0x3c37, 0x3c68, 0x2811, 0xa184, 0xf37a, 0x2829, 0x3c02,
+	0xe41e, 0x1fa1, 0xe41e, 0x0b7b, 0xf30a, 0xba40, 0x3c37, 0xba40,
+	0x3c68, 0xf28a, 0xa201, 0x3e6a, 0x3e6c, 0xe160, 0x0000, 0xe080,
+	0xa10c, 0x1837, 0x1837, 0xf132, 0xba40, 0xf11a, 0x2a6a, 0xae03,
+	0xe056, 0x3c6a, 0xe080, 0xe41e, 0x1746, 0x2a6c, 0xae03, 0xe056,
+	0x3c6c, 0xe080, 0xa203, 0xe41e, 0x1779, 0xf07e, 0x2a6a, 0xae03,
+	0x3e6a, 0x2a6c, 0xae03, 0x3e6c, 0xe080, 0xa002, 0xe090, 0xa110,
+	0xf5f8, 0xbe18, 0xf06d, 0x3c36, 0xe41e, 0x0cc1, 0xa202, 0xe42e,
+	0xe0c1, 0x0059, 0xa107, 0xf049, 0x28ae, 0xa902, 0x3cae, 0xe16a,
+	0xa200, 0xe42e, 0xa214, 0x2e1e, 0xe003, 0x0063, 0xf2f7, 0xa216,
+	0x2e1e, 0xe003, 0x018c, 0xf2a7, 0xa22a, 0x2e1e, 0xe003, 0x0318,
+	0xf257, 0xa22c, 0x2e1e, 0xe003, 0x0654, 0xf207, 0xa23e, 0x2e1e,
+	0xe003, 0x0e10, 0xf1b7, 0xa240, 0x2e1e, 0xe003, 0x1400, 0xf167,
+	0xa250, 0x2e1e, 0xe003, 0x2000, 0xf117, 0xa254, 0x2e1e, 0xe003,
+	0x2200, 0xf0c7, 0xa264, 0x2e1e, 0xe003, 0x5640, 0xf077, 0xa266,
+	0x2e1e, 0xe003, 0x9000, 0xf027, 0xa268, 0x2a1f, 0xe045, 0xf023,
+	0x3c1f, 0x2a1f, 0xa115, 0xe004, 0x0129, 0xf2d7, 0xa103, 0xe004,
+	0x02a3, 0xf297, 0xa113, 0xe004, 0x06f6, 0xf257, 0xa103, 0xe004,
+	0x0dec, 0xf217, 0xa113, 0xe004, 0x17bb, 0xf1d7, 0xa103, 0xe004,
+	0x34bc, 0xf197, 0xa103, 0xe004, 0x3c00, 0xf157, 0xa113, 0xe004,
+	0x6000, 0xf117, 0xa103, 0xe004, 0x6600, 0xf0d7, 0xa111, 0xe004,
+	0x1437, 0xae08, 0xf087, 0xa103, 0xe004, 0x21c0, 0xae08, 0xf037,
+	0xe004, 0x17bb, 0xae12, 0x3409, 0x3c0a, 0x841e, 0xe182, 0x0180,
+	0xe019, 0x2009, 0x4c0a, 0xc407, 0xd022, 0x000f, 0xe184, 0x166a,
+	0xe046, 0xf034, 0x8117, 0xe190, 0xe08e, 0x2a19, 0xe062, 0xa520,
+	0x3c20, 0xe42e, 0xe0c0, 0x0041, 0xe005, 0x0026, 0xae11, 0xe042,
+	0xce20, 0xd111, 0x09e0, 0xd112, 0x0200, 0xd113, 0x0002, 0xca28,
+	0xf7f8, 0xe42e, 0xa200, 0x3c00, 0x3c01, 0x3c02, 0x3c03, 0x3c04,
+	0x3c05, 0x3c06, 0x3c07, 0x3c08, 0x3c09, 0x3c0a, 0xba40, 0xa2ff,
+	0x3e25, 0x3e26, 0xf16a, 0xba4e, 0xa201, 0x3e25, 0x3c26, 0xe002,
+	0x00ff, 0xf0f8, 0xa202, 0x3c07, 0xba5e, 0xba5f, 0x3c25, 0x3e26,
+	0xe016, 0xe017, 0xe056, 0xf028, 0xf04e, 0xa200, 0x3c26, 0x3c25,
+	0xba40, 0xf02a, 0xba40, 0xba40, 0x3c0a, 0xf0ca, 0xba44, 0x3c09,
+	0xba40, 0x3c08, 0xba40, 0x3c06, 0xf05a, 0xba4e, 0x3c05, 0xba4e,
+	0xba4e, 0xba40, 0x3c04, 0xf05a, 0xbc0a, 0x3c03, 0xbc0a, 0x3c02,
+	0xba40, 0x3c01, 0xf0ba, 0xba7e, 0xe161, 0x05c7, 0x3511, 0x3d11,
+	0xba7e, 0x3511, 0x3d11, 0xba40, 0x3c00, 0xba40, 0x3c90, 0xe016,
+	0xe161, 0x05bd, 0xe41a, 0x172a, 0xe40a, 0x1727, 0xba40, 0x3c91,
+	0xe016, 0xe161, 0x05c2, 0xe41a, 0x172a, 0xe40a, 0x1727, 0x2890,
+	0x4c91, 0xf02a, 0xba40, 0xba40, 0x3c23, 0xba40, 0xf0aa, 0xba40,
+	0xbc20, 0xbc20, 0xbc20, 0xbc20, 0xbc20, 0x3cea, 0xbc20, 0x3ceb,
+	0x28eb, 0xa120, 0xf0a0, 0x2819, 0x18eb, 0xf070, 0x28b3, 0xf09a,
+	0x287f, 0xa104, 0x18eb, 0xf052, 0x2ab3, 0xf029, 0x2a20, 0x3eeb,
+	0xa202, 0xae3e, 0x2a0a, 0xae3d, 0xe056, 0x2a09, 0xae37, 0xe056,
+	0x2a08, 0xae35, 0xe056, 0x2a07, 0xae33, 0xe056, 0x2a06, 0xae31,
+	0xe056, 0x2a05, 0xae21, 0xe056, 0x2a04, 0xae11, 0xe056, 0x2a03,
+	0xae0b, 0xe056, 0x2a02, 0xae05, 0xe056, 0x2a01, 0xae03, 0xe056,
+	0x2a00, 0xe056, 0xe41e, 0x18ba, 0xe16a, 0xa202, 0xe42e, 0xe16a,
+	0xa200, 0xe42e, 0xe41e, 0x0c78, 0xcc44, 0x3c61, 0xa002, 0x3d11,
+	0xba46, 0xba46, 0xe184, 0x1738, 0xe41e, 0x0c78, 0xe41e, 0x0c78,
+	0xba40, 0xba48, 0xa002, 0x3d11, 0xba48, 0xa002, 0x3d11, 0xba48,
+	0xa002, 0x3d11, 0xba48, 0x3d11, 0xa202, 0xe42e, 0xd022, 0x000f,
+	0xa10c, 0xf034, 0xd022, 0x003f, 0xe161, 0x0600, 0xa210, 0x3c06,
+	0x3c07, 0xa200, 0x3c08, 0x3c09, 0xe09c, 0xe09e, 0xe184, 0x1776,
+	0x2807, 0xf10a, 0xe41e, 0x0c92, 0xe42d, 0x0806, 0xe000, 0x0100,
+	0xe008, 0x00ff, 0x3c07, 0x4c09, 0xe01a, 0xe016, 0xe09e, 0xa202,
+	0x3c09, 0x2807, 0xf028, 0x2806, 0x3c06, 0xe08d, 0xa003, 0xe09d,
+	0xa803, 0xf059, 0xe085, 0xae11, 0xe056, 0x3d11, 0xe094, 0xe08e,
+	0xe42e, 0x3e08, 0x3c06, 0xa211, 0x3e07, 0xa10c, 0xf064, 0xb690,
+	0xa00c, 0x3c06, 0xa240, 0x3c07, 0x2806, 0x2a08, 0xf02b, 0xa01c,
+	0xae08, 0x3c06, 0xe0c0, 0x0041, 0xe005, 0x0034, 0xae11, 0xe042,
+	0x0806, 0xce20, 0xd111, 0x0600, 0x2807, 0xce24, 0xd113, 0x0002,
+	0xca28, 0xf7f8, 0xe42e, 0x2811, 0xa184, 0xf0ba, 0xa116, 0xf09a,
+	0xa12e, 0xf07a, 0x2824, 0xe008, 0x0003, 0xf038, 0xa200, 0xe42e,
+	0xa202, 0xe42e, 0xa202, 0x3c51, 0xe41e, 0x088b, 0xe408, 0x180a,
+	0xe41e, 0x0b48, 0xf26a, 0xa102, 0xe40a, 0x1826, 0xa108, 0xe404,
+	0x17d8, 0xe40a, 0x1826, 0xa102, 0xe40a, 0x17f0, 0xa102, 0xe40a,
+	0x17db, 0xa102, 0xe40a, 0x17e6, 0xa102, 0xe40a, 0x17fa, 0xa102,
+	0xe40a, 0x1807, 0xa102, 0xe40a, 0x1807, 0xa102, 0xe40a, 0x1811,
+	0xf082, 0x2851, 0xe40a, 0x185a, 0xe41e, 0x095c, 0xe40e, 0x1821,
+	0xe41e, 0x0923, 0xf52e, 0x2851, 0xe40a, 0x185a, 0xe41e, 0x18ab,
+	0xe41e, 0x095c, 0xe41e, 0x1ec1, 0xe40e, 0x1821, 0x2851, 0xe40a,
+	0x185a, 0xe41e, 0x18ab, 0xe41e, 0x095c, 0xe41e, 0x1eec, 0xf32e,
+	0x2851, 0xe40a, 0x185a, 0xe41e, 0x18ab, 0xe41e, 0x095c, 0xe41e,
+	0x18bf, 0xf28e, 0x2851, 0xe40a, 0x185a, 0xe41e, 0x18b2, 0xe41e,
+	0x18ab, 0xe41e, 0x095c, 0xba44, 0xe41e, 0x0cc1, 0xf1be, 0xe41e,
+	0x088b, 0xf16a, 0xe41e, 0x01db, 0x2851, 0xe408, 0x1865, 0xe40e,
+	0x185a, 0xe41e, 0x095c, 0xba0e, 0xe002, 0x00ff, 0xf058, 0xba4e,
+	0xe41e, 0x0b6c, 0xf798, 0xe41e, 0x0cc1, 0xe40e, 0x17ac, 0xe41e,
+	0x0923, 0x2851, 0xe40a, 0x185a, 0xe40e, 0x17ac, 0xe41e, 0x18ab,
+	0xe41e, 0x095c, 0x2851, 0xf10a, 0xa202, 0x3c62, 0xe41e, 0x0ccb,
+	0xe41a, 0x18b2, 0xe40a, 0x17ac, 0x284e, 0x3c92, 0x284f, 0x3c93,
+	0xa200, 0x3c51, 0xf13e, 0x284e, 0xe01a, 0x2a92, 0xe01b, 0xe05a,
+	0xf118, 0x284f, 0x1893, 0xf0e8, 0xe41e, 0x2387, 0xe40a, 0x17ac,
+	0x2801, 0xe408, 0x17ac, 0x2894, 0xf058, 0xe41e, 0x0ee3, 0xe40e,
+	0x17ac, 0xe41e, 0x0b3f, 0xa200, 0x3c51, 0xf05e, 0x284e, 0x3c92,
+	0x284f, 0x3c93, 0x2892, 0x3c4e, 0x2893, 0x3c4f, 0xa200, 0x3c51,
+	0xe41e, 0x1887, 0xf078, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xa2fe,
+	0xe42e, 0xe41e, 0x1870, 0xe41e, 0x05a9, 0xe41e, 0x1e2a, 0xf74e,
+	0xe165, 0x05e8, 0x2811, 0x3d15, 0x2857, 0x3d15, 0x2858, 0x3d15,
+	0x28eb, 0x3d15, 0x281b, 0x3d15, 0x2824, 0x3d15, 0x281f, 0x3d15,
+	0x2813, 0x3d15, 0x2816, 0x3d15, 0x2819, 0x3d15, 0xe42e, 0xe165,
+	0x05e8, 0x2811, 0x1915, 0xf1d8, 0x2857, 0x1915, 0xf1a8, 0x2858,
+	0x1915, 0xf178, 0x28eb, 0x1915, 0xf148, 0x281b, 0x1915, 0xf118,
+	0x2824, 0x1915, 0xe428, 0x281f, 0x1915, 0xe428, 0x2813, 0x1915,
+	0xe428, 0x2816, 0x1915, 0xe428, 0x2819, 0x1915, 0xe428, 0xe42e,
+	0xa202, 0x3cbd, 0xe42e, 0x28ad, 0xe428, 0xe41e, 0x0638, 0xa202,
+	0x3cad, 0xe42e, 0xa200, 0x3cad, 0xe42e, 0xc009, 0x2039, 0x4c3a,
+	0xc000, 0xe42e, 0xc009, 0x3439, 0x3c3a, 0xc000, 0xe42e, 0xa200,
+	0xba4f, 0xe042, 0xe003, 0x00ff, 0xf7cb, 0xe41e, 0x1b70, 0xa200,
+	0xba4f, 0xe042, 0xe003, 0x00ff, 0xf7cb, 0xe41e, 0x1b78, 0xf04a,
+	0xe41e, 0x18d9, 0xe42a, 0xe41e, 0x0b6c, 0xf6a8, 0xe41e, 0x0cc1,
+	0xe42e, 0xe41e, 0x1b74, 0xf13a, 0xa102, 0xf14a, 0xa104, 0xf15a,
+	0xa102, 0xf16a, 0xa102, 0xf17a, 0xa150, 0xf18a, 0xe41e, 0x1b7c,
+	0xf04a, 0xba4f, 0xa102, 0xf7e8, 0xa202, 0xe42e, 0xe41e, 0x1908,
+	0xf10e, 0xe41e, 0x1937, 0xf0de, 0xe41e, 0x1985, 0xf0ae, 0xe41e,
+	0x1996, 0xf07e, 0xe41e, 0x19e0, 0xf04e, 0xe41e, 0x19e4, 0xf01e,
+	0xe42a, 0xc868, 0xa80e, 0xe016, 0xe428, 0xe41e, 0x0cc1, 0xe42e,
+	0xbc3e, 0xf1fd, 0x1810, 0xf11a, 0x0810, 0xf084, 0xa13e, 0xf060,
+	0xa03e, 0x3c10, 0xe41e, 0x1ed9, 0x3c65, 0xa200, 0xe41e, 0x0c19,
+	0xa201, 0x3e9b, 0x2865, 0xe42a, 0x2890, 0xe161, 0x05bd, 0xe418,
+	0x192b, 0x2891, 0xe161, 0x05c2, 0xe418, 0x192b, 0xa202, 0xe42e,
+	0xa200, 0xe16a, 0xe42e, 0x2911, 0xa102, 0xcc44, 0xe184, 0x1935,
+	0x2901, 0xe41e, 0x0cb5, 0x2901, 0xe41e, 0x0cb5, 0xe42e, 0x2890,
+	0xe161, 0x05bf, 0xf038, 0xe161, 0x05c4, 0x4c91, 0xf11a, 0x2911,
+	0xe41e, 0x0cb5, 0xc009, 0x343f, 0x3c40, 0xc000, 0x2911, 0xe41e,
+	0x0cb5, 0xc009, 0x3441, 0x3c42, 0xc000, 0x2911, 0xf02e, 0xa230,
+	0x3c02, 0x2823, 0xe016, 0xe428, 0xba46, 0x3ca3, 0xa112, 0xb604,
+	0xe42a, 0xa012, 0xe049, 0xa200, 0xa107, 0xb426, 0xa105, 0xb426,
+	0xa105, 0xb5f6, 0xcc44, 0xe184, 0x1982, 0xba40, 0xf028, 0xf1be,
+	0xba42, 0xba40, 0xba48, 0xba40, 0x3c03, 0xba40, 0xba40, 0xba4e,
+	0x2803, 0xf05a, 0xba4a, 0xba4a, 0xba48, 0xf0ae, 0xba40, 0xf08a,
+	0xba4a, 0xba40, 0xf05a, 0xba4a, 0xba40, 0xf02a, 0xba48, 0x2802,
+	0xe41e, 0x0cb5, 0xe190, 0xa202, 0xe42e, 0xe41e, 0x1b7c, 0xf0da,
+	0xa102, 0xcc44, 0xe004, 0x00ff, 0xe184, 0x198f, 0xba4f, 0xe052,
+	0xe002, 0x00ff, 0xe016, 0xe42a, 0xa202, 0xe42e, 0xa202, 0xba4f,
+	0xe003, 0x00ff, 0xf039, 0xba4f, 0xa204, 0xba1f, 0xe003, 0x0031,
+	0xf049, 0xba5f, 0xa004, 0xe190, 0xba3f, 0x360e, 0x3e0f, 0xe005,
+	0x4454, 0x1a0e, 0xf069, 0xe005, 0x4731, 0x1a0f, 0xf029, 0xf24e,
+	0xe005, 0x4741, 0x1a0e, 0xf0b9, 0xe005, 0x3934, 0x1a0f, 0xf079,
+	0xba7f, 0xa008, 0xba0f, 0xa10d, 0xe40b, 0x19ca, 0xc009, 0x2a2d,
+	0xc000, 0xe045, 0xa009, 0xc009, 0x3e2d, 0xc000, 0xe41e, 0x1a73,
+	0xa202, 0xe42e, 0xba4f, 0xa002, 0xc009, 0x2a2d, 0xc000, 0xe045,
+	0xf4d1, 0xa202, 0xe42e, 0xba7e, 0xba40, 0xf098, 0xba41, 0xba4a,
+	0xf04b, 0xba46, 0xba46, 0x3cb0, 0xa202, 0xe42e, 0xa200, 0xe42e,
+	0xe41e, 0x1a73, 0xa202, 0xe42e, 0xc009, 0xa2fe, 0x3426, 0x3c27,
+	0xa201, 0x3628, 0x3e29, 0x362a, 0x3e2b, 0xc000, 0xe41e, 0x0c78,
+	0xc009, 0xe40d, 0x1a59, 0x3426, 0x3c27, 0xba40, 0xe40d, 0x1a59,
+	0xae2a, 0xe055, 0x3628, 0x3e29, 0xe408, 0x1a4f, 0xba4c, 0xe40d,
+	0x1a59, 0xae0c, 0xe055, 0xba40, 0xe40d, 0x1a59, 0xae28, 0xe055,
+	0xba4a, 0xe40d, 0x1a59, 0xe055, 0xba40, 0xe40d, 0x1a59, 0xae26,
+	0xe055, 0xba40, 0xe40d, 0x1a59, 0xae24, 0xe055, 0xba40, 0xe40d,
+	0x1a59, 0xae22, 0xe055, 0xba40, 0xe40d, 0x1a59, 0xae20, 0xe055,
+	0xba40, 0xe40d, 0x1a59, 0xae1e, 0xe055, 0xba40, 0xe40d, 0x1a59,
+	0xae1c, 0xe055, 0x3628, 0x3e29, 0xe04a, 0xaf28, 0xa802, 0xe016,
+	0xaf0d, 0xa83f, 0xa10b, 0xe01b, 0xe052, 0xf12a, 0xa201, 0xba46,
+	0xf21d, 0xae38, 0xe055, 0xba46, 0xf1dd, 0xae30, 0xe055, 0xba46,
+	0xf19d, 0xae28, 0xe055, 0xba46, 0xf15d, 0xae20, 0xe055, 0xba4e,
+	0xf11d, 0xe0c4, 0x4064, 0xf0ed, 0xe055, 0x362a, 0x3e2b, 0x2228,
+	0x4e29, 0xba40, 0xae1a, 0xe055, 0x3628, 0x3e29, 0xa202, 0xc000,
+	0xe42e, 0xc009, 0xa2fe, 0x3426, 0x3c27, 0xa200, 0x3428, 0x3c29,
+	0x342a, 0x3c2b, 0xc000, 0xe42e, 0xc009, 0x2426, 0x4c27, 0xc000,
+	0xe42e, 0xc009, 0x2428, 0x4c29, 0xc000, 0xe42e, 0xc009, 0x242a,
+	0x4c2b, 0xc000, 0xe42e, 0xe0c0, 0x0065, 0xa878, 0xa140, 0xf0ba,
+	0xe41e, 0x1b7c, 0xa102, 0xcc44, 0xe184, 0x1a7f, 0xba4e, 0xe190,
+	0xe40e, 0x1b03, 0xa201, 0xe41e, 0x1b5e, 0x2907, 0xa002, 0x3c0c,
+	0x3d17, 0xa120, 0xf6e0, 0x2b07, 0xe41e, 0x1b74, 0xf05a, 0xe41e,
+	0x1b7c, 0xe041, 0xf05e, 0x2861, 0xa002, 0xae06, 0xe041, 0xa00f,
+	0xaf07, 0xae07, 0xe04a, 0xaf1f, 0xf0db, 0xa201, 0xe41e, 0x1b5e,
+	0x8117, 0x8117, 0x2907, 0xa202, 0x3d07, 0xa201, 0xe41e, 0x1b5c,
+	0xf50e, 0x3d17, 0xa201, 0xe41e, 0x1b5c, 0xe167, 0x0600, 0xe41e,
+	0x1b74, 0x3d17, 0xe41e, 0x1b74, 0xf04a, 0xe41e, 0x1b7c, 0xf04e,
+	0x2861, 0xa002, 0xae06, 0x3d17, 0x2a0c, 0xe41e, 0x1b5c, 0xa200,
+	0x3c0b, 0xa200, 0xe167, 0x0600, 0xc703, 0x3d17, 0xe167, 0x0600,
+	0xe41e, 0x1b74, 0xf3ba, 0xe41e, 0x1b74, 0xa108, 0xf0f8, 0xe004,
+	0x4741, 0x3d17, 0xe004, 0x3934, 0x3d17, 0x28a7, 0xa008, 0x3ca7,
+	0xe41e, 0x1b7c, 0xa108, 0xe41e, 0x1b78, 0x280b, 0xa002, 0x3c0b,
+	0xba4f, 0x28a7, 0xa002, 0x3ca7, 0xa802, 0xf058, 0x280a, 0xae10,
+	0xe056, 0x3d17, 0x3e0a, 0x28a7, 0xa80e, 0xe41a, 0x1b1e, 0xe41e,
+	0x1b7c, 0x180b, 0xf6b0, 0x28a7, 0xa80e, 0xf0ea, 0x2aa7, 0xa803,
+	0xf04b, 0x280a, 0xae10, 0x3d17, 0x2aa7, 0xa00f, 0xaf07, 0xae07,
+	0x3ea7, 0xe418, 0x1b1e, 0xe40e, 0x1b1c, 0x280b, 0xa002, 0x3c0b,
+	0x2901, 0xe41e, 0x0cb5, 0x3517, 0x3d17, 0x2901, 0xe41e, 0x0cb5,
+	0x3517, 0x3d17, 0x28a7, 0xa010, 0x3ca7, 0xe41e, 0x1b1e, 0x2861,
+	0xa002, 0x180b, 0xf6b0, 0xf01a, 0xa202, 0xe42e, 0x24b7, 0x4cb8,
+	0xe000, 0x0088, 0x18a7, 0xf242, 0xe0c0, 0x0065, 0xaf12, 0xa802,
+	0xf0da, 0xa201, 0xe41e, 0x1b5e, 0x8117, 0x8117, 0x2907, 0xa202,
+	0x3d07, 0xa201, 0xe41e, 0x1b5c, 0xe42e, 0xe004, 0x0200, 0xe0c1,
+	0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00, 0xe0c0, 0x005d,
+	0xe008, 0x0200, 0xe190, 0xf7b8, 0xe004, 0x0090, 0x3ca7, 0x24b5,
+	0x4cb6, 0x08a7, 0xa110, 0xce20, 0xd111, 0x0600, 0xd112, 0x0004,
+	0xd113, 0x0000, 0xca28, 0xf7f8, 0xa200, 0xe167, 0x0600, 0xc703,
+	0x3d17, 0xe167, 0x0600, 0xe42e, 0xa200, 0xf02e, 0xa202, 0x3c0d,
+	0x24b5, 0x4cb6, 0xae07, 0xe042, 0xce20, 0xd111, 0x0600, 0xd112,
+	0x0004, 0x880d, 0x0113, 0xca28, 0xf7f8, 0xe167, 0x0600, 0xe42e,
+	0xc009, 0x3c2c, 0xc000, 0xe42e, 0xc009, 0x282c, 0xc000, 0xe42e,
+	0xc009, 0x3c2d, 0xc000, 0xe42e, 0xc009, 0x282d, 0xc000, 0xe42e,
+	0x2c39, 0x3c7b, 0xa202, 0x3c7c, 0xa200, 0x3c7d, 0x3c7e, 0x284e,
+	0xe016, 0xe428, 0x284f, 0xf0ca, 0xe41e, 0x1c11, 0xba40, 0xba40,
+	0xb7f0, 0xb634, 0x3c7c, 0xa200, 0x3c7b, 0xa202, 0xe42e, 0xba40,
+	0xf0ea, 0x2819, 0xe42a, 0xae02, 0x3c09, 0x2014, 0x4c15, 0x3400,
+	0x3c01, 0x2c39, 0x3402, 0x3c03, 0xbc0c, 0xf058, 0xa202, 0x3c7d,
+	0xe42e, 0xbc0c, 0xe40d, 0x1c0e, 0xe40a, 0x1c0c, 0xa102, 0xf0ca,
+	0xa102, 0xf1fa, 0xa102, 0xf24a, 0xa102, 0xf35a, 0xa102, 0xe40a,
+	0x1bf1, 0xe40e, 0x1bf9, 0xe41e, 0x0c78, 0xe40d, 0x1c0e, 0xa002,
+	0x1002, 0x1c03, 0xe012, 0x3c0a, 0xf032, 0x0000, 0x0c01, 0xa203,
+	0xe41e, 0x1c18, 0x2a0a, 0x3e04, 0x4c4f, 0xe41a, 0x1c30, 0xf5ae,
+	0xbc40, 0xe40d, 0x1c0e, 0xa2ff, 0xe41e, 0x1c18, 0xf53e, 0xe41e,
+	0x0c78, 0xe40d, 0x1c0e, 0xa002, 0x1002, 0x1c03, 0xe012, 0xf032,
+	0x0000, 0x0c01, 0x3c06, 0xbc20, 0xf2ad, 0x3c07, 0xe41e, 0x1c5d,
+	0xe40e, 0x1ba9, 0xbc20, 0xf23d, 0xa102, 0xe41e, 0x1c78, 0xe40e,
+	0x1ba9, 0xe41e, 0x1c11, 0xa202, 0x3c7e, 0xa200, 0x3c7b, 0xe40e,
+	0x1ba9, 0xbc20, 0xf14d, 0x3c7b, 0x287b, 0xa2ff, 0xe41e, 0x1c18,
+	0xf7c8, 0xf07e, 0x287b, 0xae02, 0xa2ff, 0xe41e, 0x1c18, 0xf7b8,
+	0xa2fe, 0x3c7c, 0xe40e, 0x1ba9, 0xa202, 0xe42e, 0xe16a, 0xa200,
+	0xe42e, 0xc410, 0xe161, 0x02f1, 0xa200, 0xc71f, 0x3d31, 0xe42e,
+	0x3c04, 0x3e05, 0xe161, 0x02f0, 0x8809, 0x0022, 0xe184, 0x1c2b,
+	0x2d11, 0x2b09, 0x1c04, 0x1a05, 0xf068, 0xf059, 0x8111, 0xa200,
+	0x3d09, 0xf05e, 0x8111, 0x8111, 0xa200, 0xe42e, 0xa202, 0xe42e,
+	0xe161, 0x02f0, 0x8809, 0x0022, 0xe184, 0x1c40, 0x2d11, 0x2b09,
+	0x1804, 0x1a05, 0xf050, 0xf049, 0x8111, 0xa200, 0x3d09, 0x8111,
+	0x8111, 0xe160, 0x0003, 0xe161, 0x02f1, 0x8809, 0x0022, 0xe184,
+	0x1c5a, 0x2909, 0xf0fa, 0x2d01, 0x2e39, 0xe045, 0xf043, 0x2214,
+	0x4e15, 0xe046, 0xae02, 0x1804, 0xf052, 0xa200, 0x8111, 0x3d01,
+	0xe42e, 0x8131, 0xe190, 0xa202, 0xe42e, 0x2807, 0xa2ff, 0xe41e,
+	0x1c18, 0xf7c8, 0xe161, 0x02f0, 0x8809, 0x0022, 0xe184, 0x1c73,
+	0x2d11, 0x2b09, 0x1c06, 0xf078, 0xf067, 0x2807, 0x3d11, 0xa2fe,
+	0x3d09, 0xf05e, 0x8111, 0x8111, 0xa200, 0xe42e, 0xa202, 0xe42e,
+	0x3c08, 0xe161, 0x02f0, 0x8809, 0x0022, 0xe184, 0x1c88, 0x2d11,
+	0x2b09, 0x1808, 0xf056, 0xf043, 0x8111, 0xa200, 0x3d09, 0x8111,
+	0x8111, 0xe42e, 0x2819, 0x1812, 0xf122, 0x2812, 0xa102, 0xcc44,
+	0xe161, 0x0202, 0xe184, 0x1c9d, 0x2911, 0xf06a, 0x2909, 0xe412,
+	0x217f, 0xa200, 0x3d11, 0xe082, 0xa006, 0xe092, 0x2819, 0xb62c,
+	0x3c12, 0x2816, 0xa104, 0xe428, 0xe41e, 0x1e2a, 0xe42e, 0x2816,
+	0xa102, 0xf044, 0xf14a, 0xe40e, 0x1cf1, 0x7417, 0xe160, 0x0903,
+	0x3d00, 0x282a, 0xe418, 0x0c92, 0xe42d, 0xe161, 0x0904, 0xe162,
+	0x0905, 0x3501, 0x3d02, 0xe41e, 0x1d42, 0xf36e, 0xa200, 0xe160,
+	0x0903, 0xe161, 0x0904, 0xe162, 0x0905, 0xe163, 0x0906, 0x3500,
+	0x3d01, 0x3502, 0x3d03, 0x2818, 0xf158, 0xe41e, 0x0c92, 0xe42d,
+	0xe164, 0x0903, 0xe165, 0x0904, 0x3504, 0x3d05, 0x282a, 0xf0aa,
+	0xe41e, 0x0c92, 0xe42d, 0xe166, 0x0905, 0xe167, 0x0906, 0x3506,
+	0x3d07, 0xe41e, 0x1d92, 0xf10e, 0xe164, 0x0903, 0xe165, 0x0904,
+	0xe166, 0x0905, 0xe167, 0x0906, 0x3504, 0x3d05, 0x3506, 0x3d07,
+	0xf03e, 0xe41e, 0x1de3, 0x2074, 0x4c75, 0x2276, 0x4e77, 0xe066,
+	0x3472, 0x3c73, 0xe42e, 0x284f, 0x4c7e, 0xe418, 0x1e2a, 0x28e5,
+	0xae02, 0xe000, 0x0578, 0xe092, 0x2072, 0x4c73, 0x3511, 0x3d11,
+	0x28e5, 0xe000, 0x059a, 0xe092, 0x2884, 0x3d11, 0x28e5, 0xa002,
+	0x3ce5, 0x28eb, 0x2a16, 0xa105, 0xb616, 0x2a21, 0xb616, 0x3c07,
+	0xe41e, 0x219c, 0xf048, 0xe41e, 0x1e2f, 0xf7be, 0xe41e, 0x21ac,
+	0xe428, 0xe41e, 0x1e2f, 0xf7be, 0x28e9, 0xf04a, 0xa102, 0x3ce9,
+	0xf14e, 0x28e8, 0xf12a, 0x28e7, 0xe000, 0x05ab, 0xe092, 0x28e7,
+	0xa002, 0x3ce7, 0xa122, 0xf028, 0x3ce7, 0x28e8, 0xa102, 0x3ce8,
+	0x2901, 0xe049, 0x1a7f, 0xe425, 0xe41e, 0x08a5, 0xe049, 0xa2fa,
+	0xb7f2, 0xe42e, 0xa202, 0x5817, 0xaf02, 0x3c06, 0x284f, 0x2a82,
+	0xf0b8, 0xf0d9, 0xe164, 0x0906, 0x2114, 0x4d14, 0xe166, 0x0908,
+	0x2316, 0x4f16, 0xf09e, 0xa200, 0xa201, 0xf06e, 0xa200, 0xe161,
+	0x090a, 0x2311, 0x4f11, 0x3400, 0x3c01, 0x3602, 0x3e03, 0xe161,
+	0x0903, 0x2f01, 0x1202, 0x1e03, 0xf071, 0xe013, 0x1e06, 0xf085,
+	0x0c06, 0x0c06, 0xf05e, 0x1e06, 0xf037, 0x1c06, 0x1c06, 0x3404,
+	0x3c05, 0xe161, 0x0903, 0x0d01, 0x3474, 0x3c75, 0xe162, 0x0904,
+	0x0112, 0x0d12, 0x3476, 0x3c77, 0x284e, 0xf14a, 0x2074, 0x4c75,
+	0xe161, 0x090a, 0x3511, 0x3d11, 0x2004, 0x4c05, 0xe164, 0x0906,
+	0x3514, 0x3d14, 0xe161, 0x0903, 0xe166, 0x0908, 0x2d01, 0x3516,
+	0x3d16, 0xe42e, 0xe41e, 0x1df4, 0xe160, 0x090b, 0x2900, 0xf34a,
+	0x2000, 0x4c01, 0x0c39, 0xf306, 0x2a4e, 0xe017, 0xe046, 0xa102,
+	0xf2b4, 0xe160, 0x090b, 0xe188, 0x000f, 0x7d00, 0x3402, 0x3c03,
+	0xe41e, 0x1e1a, 0xe163, 0x090b, 0x2903, 0xa102, 0xcc44, 0xe161,
+	0x09e0, 0xa200, 0xe184, 0x1db5, 0x0111, 0x0d11, 0xae02, 0x3404,
+	0xe008, 0xffff, 0xaf02, 0x3c05, 0x8403, 0x8204, 0xe018, 0xae1e,
+	0x8205, 0xe01c, 0xe161, 0x09e0, 0x8802, 0x0022, 0xe184, 0x1dc9,
+	0x0111, 0x0d11, 0xf02e, 0xa200, 0x2a4e, 0xf059, 0xe161, 0x0907,
+	0x0111, 0x0d11, 0xe164, 0x0903, 0x0114, 0x0d14, 0x3474, 0x3c75,
+	0xe162, 0x0909, 0x0112, 0x0d12, 0xe166, 0x0905, 0x0116, 0x0d16,
+	0x3476, 0x3c77, 0xe42e, 0xe41e, 0x1df4, 0x284f, 0xe016, 0xf08a,
+	0x2000, 0x4c01, 0x0c39, 0xae02, 0x2a4e, 0xe017, 0xe046, 0x3474,
+	0x3c75, 0x3476, 0x3c77, 0xe42e, 0x2882, 0xf09a, 0xa200, 0xe162,
+	0x0901, 0x3512, 0x3d12, 0xe161, 0x0900, 0x3d01, 0x284f, 0xe016,
+	0xf0da, 0xe162, 0x0901, 0x2112, 0x4d12, 0xe161, 0x0900, 0x2f01,
+	0x1e39, 0xf047, 0xa203, 0x5a13, 0xe042, 0x3400, 0x3c01, 0x2839,
+	0xe161, 0x0900, 0x3d01, 0x2000, 0x4c01, 0xe162, 0x0901, 0x3512,
+	0x3d12, 0xe42e, 0xe0c0, 0x0041, 0xe005, 0x0026, 0xae11, 0xe042,
+	0xce20, 0xd111, 0x09e0, 0xd112, 0x0200, 0xd113, 0x0003, 0xca28,
+	0xf7f8, 0xe42e, 0x28e5, 0xe426, 0xe41e, 0x1e2f, 0xf7ce, 0xe161,
+	0x0578, 0xe162, 0x0578, 0x2111, 0x4d11, 0xa201, 0x3e00, 0xa203,
+	0x28e5, 0xa104, 0xf0e4, 0xcc44, 0xe184, 0x1e47, 0x2112, 0x4d0a,
+	0x1111, 0x1d11, 0xf056, 0xe082, 0xa104, 0xe094, 0x3e00, 0xa003,
+	0xe084, 0xa004, 0xe092, 0x2800, 0xe000, 0x059a, 0xe098, 0xa002,
+	0xe096, 0x2904, 0x3c01, 0xe41e, 0x2186, 0x28e5, 0x1800, 0xa104,
+	0xf0a4, 0xcc44, 0xe184, 0x1e61, 0x2911, 0x3d12, 0x2911, 0x3d12,
+	0x2913, 0x3d14, 0x28e5, 0xb5f0, 0x3ce5, 0x28e6, 0xe000, 0x05ab,
+	0xe092, 0x2801, 0x3d01, 0x28e6, 0xa002, 0x3ce6, 0xa122, 0xf028,
+	0x3ce6, 0x28e8, 0xa002, 0x3ce8, 0xe42e, 0xa200, 0x3cb2, 0xe004,
+	0x0054, 0xe09c, 0x287f, 0xa102, 0xcc44, 0xe184, 0x1e8e, 0x9e06,
+	0x5cb2, 0xa802, 0xf0a8, 0x28b2, 0xe049, 0xe001, 0x0518, 0xe09f,
+	0x2b07, 0xa809, 0xe419, 0x218d, 0x2ab2, 0xa003, 0x3eb2, 0xe42e,
+	0xe004, 0x0518, 0xe09e, 0xe004, 0x0054, 0xe09c, 0x287f, 0xa102,
+	0xcc44, 0xa200, 0x3cb2, 0xe184, 0x1ea4, 0x2b17, 0xaf05, 0xa803,
+	0x5ab2, 0xe056, 0x2ab2, 0xa003, 0x3eb2, 0x9f06, 0xe42e, 0x2840,
+	0xf058, 0xe41e, 0x21c8, 0x3c3e, 0xf03e, 0x283e, 0x3c84, 0xe42e,
+	0xe161, 0x0600, 0xa200, 0x3d11, 0x3c02, 0xd022, 0x011f, 0xe184,
+	0x1ebd, 0xe41e, 0x1f9f, 0x2802, 0xa002, 0x3c02, 0xa200, 0x3c9b,
+	0xe42e, 0xba4e, 0xba40, 0xba40, 0xba40, 0xba40, 0xba46, 0xba4e,
+	0xbc3e, 0xf0dd, 0x3c00, 0x1810, 0xf038, 0xa2fe, 0x3c10, 0x2800,
+	0xe000, 0x0100, 0xe41e, 0x1f30, 0xa202, 0xe42e, 0xe16a, 0xa200,
+	0xe42e, 0xa204, 0x3c9b, 0x2810, 0xe000, 0x0100, 0xe41e, 0x1f6b,
+	0xe42a, 0xe41e, 0x1429, 0xf056, 0xe41e, 0x1c8a, 0xa202, 0xe42e,
+	0xa2fe, 0x3c10, 0xa200, 0xe42e, 0xe41e, 0x0c78, 0xf12d, 0x3c01,
+	0xe002, 0x00ff, 0xf0e0, 0x2801, 0x1829, 0xf038, 0xa2fe, 0x3c29,
+	0x28ae, 0xa802, 0x3cae, 0x2801, 0xe41e, 0x1f30, 0xa202, 0xe42e,
+	0xe16a, 0xa200, 0xe42e, 0xa202, 0x3c9b, 0x2829, 0xe41e, 0x1f6b,
+	0xf0da, 0xe41e, 0x1545, 0x3c65, 0xa200, 0xe41e, 0x0c19, 0xa201,
+	0x3e9b, 0x2865, 0xf03a, 0xa202, 0xe42e, 0xe0c1, 0x0059, 0xa107,
+	0xf079, 0x28ae, 0xa104, 0xf04a, 0x28ae, 0xa902, 0x3cae, 0xa2fe,
+	0x3c29, 0xa200, 0xe42e, 0x2860, 0xa102, 0xf06a, 0x2499, 0x4c9a,
+	0xe41e, 0x1fb9, 0xe470, 0xe41e, 0x1fd2, 0xe41e, 0x1fc0, 0xe470,
+	0x3c02, 0xe41e, 0x1fa1, 0xa200, 0x3c06, 0x2802, 0xae14, 0x3404,
+	0x3c05, 0xe41e, 0x0c14, 0x0404, 0x0c05, 0xce20, 0xd111, 0x0000,
+	0xe41e, 0x0be7, 0x1806, 0xa00e, 0xaf06, 0xae02, 0xce24, 0xd113,
+	0x0012, 0xca28, 0xf7f8, 0xca2c, 0xf7fa, 0xe41e, 0x0bf0, 0xf128,
+	0x2004, 0x4c05, 0xe000, 0x0200, 0x3404, 0x3c05, 0xe41e, 0x0be7,
+	0x3c06, 0xe41e, 0x09b5, 0xe41e, 0x0be7, 0xe002, 0x0400, 0xf020,
+	0xf59e, 0xe161, 0x0600, 0xa202, 0x3d11, 0xe41e, 0x0be7, 0x3d01,
+	0xe41e, 0x1f9f, 0xe42e, 0x3c02, 0xe41e, 0x1fa1, 0xe161, 0x0600,
+	0x2911, 0xe42a, 0x8111, 0x2111, 0x4d11, 0x2802, 0xae14, 0x3404,
+	0x3c05, 0x289b, 0xa102, 0xf0da, 0xe41e, 0x0c14, 0x0404, 0x0c05,
+	0xe41e, 0x1fb9, 0xa204, 0xe41e, 0x0c19, 0xe004, 0x0090, 0xf0ce,
+	0xe41e, 0x0c14, 0x0404, 0x0c05, 0xe41e, 0x1fc0, 0xa202, 0xe41e,
+	0x0c19, 0xe004, 0x0080, 0xcc66, 0xcc6a, 0xcc6e, 0xa01e, 0xcc6c,
+	0xa200, 0xcc60, 0xcc68, 0xcc70, 0xe128, 0xa202, 0xe42e, 0xa204,
+	0xf02e, 0xa206, 0x3c0a, 0xe41e, 0x1faf, 0xce20, 0xd111, 0x0600,
+	0xd112, 0x0004, 0x880a, 0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe0c0,
+	0x0041, 0xe005, 0x002a, 0xae11, 0xe042, 0x2a02, 0xae07, 0xe042,
+	0xe42e, 0xce20, 0xa080, 0x3499, 0x3c9a, 0xd111, 0x0090, 0xf07e,
+	0xce20, 0xa080, 0xe41e, 0x1fcd, 0xd111, 0x0080, 0xd112, 0x0010,
+	0xd113, 0x0013, 0xca28, 0xf7f8, 0xe42e, 0xc009, 0x3410, 0x3c11,
+	0xc000, 0xe42e, 0xc009, 0x2410, 0x4c11, 0xc000, 0xe42e, 0x2819,
+	0xe42a, 0xa102, 0x3c00, 0x284e, 0xe01a, 0x2abe, 0xa003, 0xa803,
+	0xe052, 0xe418, 0x2096, 0xe41e, 0x20c9, 0xe41e, 0x20e7, 0xe42e,
+	0x287e, 0xf10a, 0x2074, 0x4c75, 0x1072, 0x1c73, 0x3474, 0x3c75,
+	0x2076, 0x4c77, 0x1072, 0x1c73, 0x3476, 0x3c77, 0xa200, 0x3472,
+	0x3c73, 0xa200, 0x3cbe, 0x2c39, 0x2a4f, 0x4e7e, 0xb612, 0x3c80,
+	0x2819, 0xf0ea, 0xa102, 0x3c00, 0x2839, 0x3c50, 0x287d, 0xe41a,
+	0x2071, 0xa202, 0xe418, 0x2042, 0xe41e, 0x2013, 0xe42e, 0x2884,
+	0xe41e, 0x217f, 0xe42e, 0xc420, 0xe161, 0x0202, 0x8800, 0x0022,
+	0xe184, 0x201c, 0x2901, 0xf03a, 0x8131, 0xe42e, 0xe082, 0xe002,
+	0x0202, 0xaf04, 0x3c0a, 0xa206, 0x3d09, 0x287c, 0x3d09, 0x287b,
+	0x3d31, 0x8109, 0x2884, 0x3d11, 0xe42e, 0xc420, 0xe161, 0x0202,
+	0x8800, 0x0022, 0xe184, 0x2036, 0x2901, 0xf03a, 0x8131, 0xe42e,
+	0xa206, 0x3d09, 0xa202, 0x3d09, 0x2850, 0x3d31, 0x8109, 0xa2fe,
+	0x3d11, 0xe42e, 0xa200, 0xc420, 0xe161, 0x0202, 0x8800, 0x0022,
+	0xe184, 0x204c, 0x2b31, 0xe01b, 0xe042, 0x1819, 0xe424, 0xa203,
+	0xae21, 0xe161, 0x0202, 0x8800, 0x0022, 0xe184, 0x206a, 0x2909,
+	0xf11a, 0x2909, 0xf0e6, 0x2901, 0x1c50, 0xf036, 0x1014, 0x1c15,
+	0x0c50, 0xe046, 0xf062, 0xe042, 0xe049, 0xe082, 0xa004, 0xe094,
+	0x8111, 0x8111, 0x8131, 0xa200, 0x3d12, 0x2912, 0xe412, 0x217f,
+	0xe42e, 0xe161, 0x0200, 0xe162, 0x02f0, 0x8800, 0x0022, 0xe184,
+	0x2094, 0x2912, 0x3c02, 0x2912, 0x3c03, 0xe01a, 0xb670, 0x3c04,
+	0x2804, 0x8112, 0x8112, 0xf08a, 0x2802, 0x3d11, 0x2803, 0x3d11,
+	0x2804, 0x3d11, 0xf0ae, 0x8111, 0x8111, 0x2901, 0xa201, 0x3f11,
+	0xf04a, 0x2901, 0xe412, 0x217f, 0x8111, 0xe42e, 0x284f, 0xe428,
+	0x2819, 0xe42a, 0xe41e, 0x216c, 0x4c1a, 0xe42a, 0x2c80, 0x3c50,
+	0xa200, 0x3c0f, 0x2850, 0xa002, 0x2214, 0x4e15, 0xa103, 0xe052,
+	0x3c50, 0x1c39, 0xe42a, 0x281a, 0x4caa, 0xf05a, 0xe41e, 0x2042,
+	0xe41e, 0x202d, 0x281a, 0xf6f8, 0x28ae, 0xa920, 0x3cae, 0x280f,
+	0xa002, 0x3c0f, 0xa120, 0xf062, 0xe41e, 0x05a9, 0xe41e, 0x1c11,
+	0xf62e, 0xe41e, 0x05a9, 0xe41e, 0x1e2a, 0x28ae, 0xa908, 0x3cae,
+	0xe42e, 0xe161, 0x0200, 0xe162, 0x02f0, 0x8800, 0x0022, 0xe184,
+	0x20db, 0x2911, 0x3d12, 0x2911, 0x2b11, 0xa107, 0xb612, 0x3d12,
+	0xa200, 0x3d12, 0x3d12, 0x8111, 0xe161, 0x0330, 0xe162, 0x02f0,
+	0xd022, 0x003f, 0xe184, 0x20e5, 0x2912, 0x3d11, 0xe42e, 0xe41e,
+	0x20f3, 0x2808, 0xe000, 0x0370, 0xe096, 0xe41e, 0x2134, 0x2808,
+	0x0809, 0x3c6d, 0xe42e, 0xe161, 0x0600, 0xa200, 0xc70f, 0x3d11,
+	0xa206, 0x3c05, 0xa200, 0x3c08, 0xc420, 0xe163, 0x0370, 0xa2fe,
+	0x3c06, 0xa203, 0xae21, 0xe013, 0xe161, 0x0202, 0xe162, 0x0600,
+	0x8800, 0x0022, 0xe184, 0x2123, 0x2912, 0xf168, 0x2909, 0x1805,
+	0xf124, 0x2909, 0xf0f6, 0x2901, 0x1c39, 0xf036, 0x1014, 0x1c15,
+	0x0c39, 0xe046, 0xf076, 0xe042, 0xe049, 0xe084, 0xe002, 0x0601,
+	0x3c06, 0x8111, 0x8111, 0x8131, 0x2806, 0xe424, 0xe000, 0x0600,
+	0xe094, 0xa202, 0x3d02, 0x2806, 0xae02, 0x3d13, 0x2808, 0xa002,
+	0x3c08, 0x1819, 0xf4d8, 0xe42e, 0xe161, 0x0600, 0xa200, 0xc70f,
+	0x3d11, 0xa206, 0x3c05, 0xa200, 0x3c09, 0xc420, 0xa2fe, 0x3c07,
+	0xa221, 0xe161, 0x0202, 0xe162, 0x0600, 0x8800, 0x0022, 0xe184,
+	0x215b, 0x2912, 0xf118, 0x2909, 0x1805, 0xf0d4, 0x2909, 0xf0a2,
+	0x2901, 0xe046, 0xf072, 0xe042, 0xe049, 0xe084, 0xe002, 0x0601,
+	0x3c07, 0x8111, 0x8111, 0x8131, 0x2807, 0xe424, 0xe000, 0x0600,
+	0xe094, 0xa202, 0x3d02, 0x2807, 0xae02, 0x3d13, 0x2809, 0xa002,
+	0x3c09, 0x1819, 0xf548, 0xe42e, 0x2819, 0xe426, 0xa102, 0xcc44,
+	0xc420, 0xe161, 0x0202, 0xe184, 0x2177, 0x2901, 0xe428, 0x8131,
+	0xe42e, 0xe161, 0x0518, 0xa200, 0xc71f, 0x3d11, 0xe42e, 0xe000,
+	0x0518, 0xe09e, 0x2907, 0xa80c, 0x3d07, 0xe42e, 0xe000, 0x0518,
+	0xe09e, 0x2907, 0xa80a, 0x3d07, 0xe42e, 0x3c81, 0xe000, 0x0518,
+	0xe09e, 0x2907, 0xa806, 0x3d07, 0x2881, 0xa002, 0x3c81, 0x187f,
+	0xe428, 0xa200, 0x3c81, 0xe42e, 0xe161, 0x0518, 0x287f, 0xa102,
+	0xcc44, 0xa201, 0xe184, 0x21a7, 0x2911, 0xa804, 0xe01a, 0xe041,
+	0x1a07, 0xa202, 0xb602, 0xe42e, 0xe161, 0x0518, 0x287f, 0xa102,
+	0xcc44, 0xa200, 0xe184, 0x21b7, 0x2b11, 0xa807, 0xe01b, 0xe042,
+	0x18eb, 0xa102, 0xe01a, 0xe42e, 0xe161, 0x0518, 0x287f, 0xa102,
+	0xcc44, 0xe184, 0x21c6, 0x2911, 0xe016, 0xe428, 0xe190, 0xe42e,
+	0x2881, 0x3c00, 0x2800, 0xe000, 0x0518, 0xe092, 0x2901, 0xf10a,
+	0x2800, 0xa002, 0x3c00, 0x187f, 0xf038, 0xa200, 0x3c00, 0x2800,
+	0x1881, 0xf718, 0xa200, 0x3c81, 0xa2fe, 0x3c84, 0xe42e, 0xa20e,
+	0x3d01, 0x2800, 0x3c84, 0xe42e, 0xe0c1, 0x0044, 0xa80f, 0xe056,
+	0xe42e, 0xa200, 0xe41e, 0x21e4, 0xe42e, 0xe0c1, 0x0044, 0xaf0d,
+	0xae03, 0xe056, 0xe008, 0x003f, 0xe42e, 0xe0c1, 0x0044, 0xaf17,
+	0xa803, 0xe42e, 0xe0c1, 0x0044, 0xaf17, 0xa803, 0xa105, 0xf039,
+	0xa213, 0xe42e, 0xa201, 0xe42e, 0xa203, 0xe0c3, 0x040d, 0xe0c1,
+	0x0420, 0xa803, 0xf7db, 0xe160, 0x0003, 0xe166, 0x0640, 0xe167,
+	0x0500, 0x287f, 0xf166, 0xa102, 0xcc44, 0xe184, 0x2227, 0xa200,
+	0xe41e, 0x21e4, 0xaf04, 0xe41e, 0x21ed, 0xae20, 0x2e66, 0xe056,
+	0x9f17, 0x2057, 0x4c58, 0xae08, 0x9f17, 0xe41e, 0x222d, 0xe190,
+	0xe190, 0xa201, 0xe0c3, 0x040d, 0xe42e, 0x2116, 0x4d16, 0x9f17,
+	0x2116, 0x4d16, 0x9f17, 0x2116, 0x4d16, 0x9f17, 0xe42e, 0xe0c0,
+	0x0044, 0xaf20, 0xa802, 0xe428, 0xe0c0, 0x0060, 0xa860, 0xe42a,
+	0xe0c0, 0x0061, 0xa83e, 0xa203, 0xe0c3, 0x040d, 0xcca4, 0xc785,
+	0xe018, 0xe000, 0x0500, 0xe09e, 0xe0c1, 0x0420, 0xa803, 0xf7db,
+	0xa200, 0xe41e, 0x21e9, 0xa80e, 0xaf04, 0xe41e, 0x21ed, 0xe41e,
+	0x21f5, 0xe40b, 0x2260, 0xa81e, 0xe41e, 0x21fa, 0xae09, 0xe056,
+	0xae20, 0xe0c1, 0x006e, 0xe009, 0x1fff, 0xe056, 0x9f17, 0xe0c0,
+	0x0060, 0xa822, 0xa122, 0xf04a, 0x2057, 0x4c58, 0xf03e, 0x2058,
+	0x4c57, 0xae08, 0x9f17, 0xe0c0, 0x0062, 0x9f17, 0xe0c0, 0x0063,
+	0x9f17, 0xe0c0, 0x0064, 0x9f17, 0xa201, 0xe0c3, 0x040d, 0xe42e,
+	0x3cec, 0xe0c0, 0x0041, 0xe005, 0x0020, 0xae11, 0xe042, 0xce20,
+	0xd111, 0x0640, 0xd112, 0x00c0, 0x88ec, 0x0113, 0xca29, 0xf7f9,
+	0xe190, 0xe42e, 0xa2fe, 0x3c89, 0xa200, 0x3c88, 0xe42e, 0x2856,
+	0x3c89, 0x2889, 0xf032, 0xa200, 0x3c88, 0xa200, 0x3c8d, 0x3c8e,
+	0x2857, 0x3c8b, 0x2858, 0x3c8c, 0x2888, 0xe42a, 0x2889, 0xe424,
+	0x2889, 0xe0c2, 0x0143, 0x288a, 0xe0c2, 0x0144, 0xa200, 0xe0c2,
+	0x017f, 0xe0c2, 0x0149, 0xe41e, 0x21e4, 0xe0c2, 0x017f, 0x288b,
+	0xa102, 0xae20, 0x4c8c, 0xa102, 0xe0c2, 0x0142, 0xa200, 0xae20,
+	0x2a87, 0xe042, 0xe0c2, 0x014e, 0xe42e, 0x2889, 0x2a8e, 0x1a8c,
+	0xe423, 0x288d, 0xae0e, 0x4c8e, 0xa203, 0xb615, 0x3e8f, 0x2a8f,
+	0xae03, 0xa903, 0xae1d, 0xe056, 0xe0c1, 0x014b, 0xf7e9, 0xe0c2,
+	0x014d, 0xa202, 0xe0c2, 0x014a, 0x2a8d, 0xa003, 0x3e8d, 0x1a8b,
+	0xf065, 0x2a8e, 0xa003, 0x3e8e, 0xa201, 0x3e8d, 0xe42e, 0x2888,
+	0xf15a, 0x288e, 0x188c, 0xf042, 0xe41e, 0x22c5, 0xf7be, 0xe0c0,
+	0x014b, 0xf7e8, 0xa204, 0xae1c, 0xe0c2, 0x014d, 0xa202, 0xe0c2,
+	0x014a, 0xe190, 0xe0c0, 0x014b, 0xf7e8, 0x2885, 0x3c89, 0xe42e,
+	0xe41e, 0x2375, 0xe41e, 0x0e5d, 0xe41e, 0x2331, 0xe41e, 0x24dd,
+	0xe41e, 0x0dd5, 0x282b, 0xf04a, 0xe41e, 0x10e0, 0xf20e, 0xa200,
+	0x3c59, 0x2c59, 0x1c44, 0xf1b2, 0x2c59, 0xa201, 0xe41e, 0x0f50,
+	0x2c52, 0x1c59, 0xf774, 0xf06a, 0xe41e, 0x2422, 0x2c52, 0x1c44,
+	0xf0e2, 0xe41e, 0x0ccb, 0xf6ea, 0xe41e, 0x05c6, 0xf05a, 0xe41e,
+	0x05e5, 0xe40e, 0x232e, 0xe41e, 0x2400, 0xf64e, 0xe41e, 0x2592,
+	0xe42e, 0xa202, 0xae0c, 0x2a32, 0xa83f, 0xe056, 0xae0a, 0x2a32,
+	0xa83f, 0xe056, 0xae06, 0xcf80, 0xa200, 0xae02, 0xa902, 0xae04,
+	0xcfc2, 0x282b, 0xe01a, 0xae0e, 0x4c57, 0xa102, 0xae02, 0x4c34,
+	0xae06, 0xcf00, 0xd1d3, 0x000b, 0xd185, 0x0001, 0xc420, 0xe161,
+	0x0201, 0xa200, 0xd022, 0x000f, 0xe184, 0x2358, 0x2b31, 0xae02,
+	0xb42a, 0xcfe8, 0x2072, 0x4c73, 0xcfea, 0x2074, 0x4c75, 0xcfec,
+	0x2076, 0x4c77, 0xcfee, 0xe004, 0x0060, 0xcbcf, 0xa803, 0xf03b,
+	0xe004, 0x0070, 0xce30, 0xe161, 0x0260, 0xd022, 0x001f, 0xe184,
+	0x2373, 0x2111, 0x4d11, 0xce32, 0xe42e, 0xa202, 0xe0c2, 0x013c,
+	0xa200, 0xa221, 0xd022, 0x00df, 0xe184, 0x2382, 0xe0c2, 0x013e,
+	0xe0c3, 0x013f, 0xa002, 0xa200, 0xe0c2, 0x013c, 0xe42e, 0xa200,
+	0x3c94, 0xe41e, 0x0c78, 0xe40d, 0x23fd, 0x3c52, 0x1c44, 0xe402,
+	0x23fd, 0xbc12, 0xe40d, 0x23fd, 0xa10a, 0xb4a8, 0xa104, 0xe400,
+	0x23fd, 0xbdfe, 0xe40d, 0x23fd, 0x1829, 0xf03a, 0xa202, 0x3c94,
+	0x7413, 0x1839, 0xf03a, 0xa202, 0x3c94, 0x284f, 0xf09a, 0xe41e,
+	0x0c78, 0xe40d, 0x23fd, 0x1c45, 0xf03a, 0xa202, 0x3c94, 0x2816,
+	0xa102, 0xf034, 0xf18a, 0xf33e, 0x7417, 0xe160, 0x0903, 0x1d00,
+	0xf03a, 0xa202, 0x3c94, 0x282a, 0xf2aa, 0xe41e, 0x0c92, 0xf3ed,
+	0xe161, 0x0904, 0xe162, 0x0905, 0x1101, 0x1d02, 0xf03a, 0xa202,
+	0x3c94, 0xf1de, 0x2818, 0xf1b8, 0xe41e, 0x0c92, 0xf2fd, 0xe163,
+	0x0903, 0xe164, 0x0904, 0x1103, 0x1d04, 0xf03a, 0xa202, 0x3c94,
+	0x282a, 0xf0da, 0xe41e, 0x0c92, 0xf21d, 0xe165, 0x0905, 0xe166,
+	0x0906, 0x1105, 0x1d06, 0xf03a, 0xa202, 0x3c94, 0x2835, 0xf06a,
+	0xbcfe, 0xf14d, 0xf03a, 0xa201, 0x3e94, 0x3c01, 0x2894, 0xf068,
+	0x2801, 0xf048, 0xe41e, 0x10cb, 0x3c94, 0xe41e, 0x0be7, 0xae06,
+	0xc873, 0xe046, 0xf034, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e,
+	0xa200, 0xe41e, 0x0bf4, 0xe41e, 0x0bf0, 0xf068, 0xa202, 0xe41e,
+	0x08ad, 0xe41e, 0x0bf4, 0xe16a, 0x2c52, 0x3c59, 0xa200, 0x3c0c,
+	0xe41e, 0x2435, 0x2c59, 0x1c44, 0xf092, 0xe41e, 0x2450, 0xf09d,
+	0xcb86, 0xa102, 0xf780, 0xc894, 0xf768, 0xe41e, 0x0cc1, 0xe42e,
+	0xe16a, 0xe42e, 0x284f, 0xe016, 0x3c38, 0xa202, 0x3c0c, 0xe41e,
+	0x2435, 0xa200, 0x3c0c, 0x2c59, 0x180d, 0xf072, 0xe41e, 0x2479,
+	0x2c53, 0xa002, 0x3c53, 0xf78e, 0xe42e, 0xd1fa, 0x0000, 0x284b,
+	0xae0a, 0x4c4c, 0xae0a, 0x4c4d, 0xcf30, 0x2848, 0xae04, 0x4c38,
+	0xcf82, 0xd1c3, 0x0000, 0x284a, 0xcf96, 0x2848, 0xae0c, 0x4c38,
+	0xcfc4, 0x280c, 0xf03a, 0x2838, 0xf03a, 0xd188, 0x0001, 0xe42e,
+	0xd185, 0x0002, 0xd1d0, 0x003f, 0xcba0, 0xa810, 0xcba3, 0xe409,
+	0x246f, 0xf7b8, 0xe41e, 0x2555, 0xcbe0, 0xf7f8, 0x285a, 0xe41a,
+	0x2578, 0xcba0, 0xcba3, 0xe409, 0x246f, 0xf7c8, 0xd186, 0x0001,
+	0xd185, 0x0004, 0xe41e, 0x2588, 0xcb06, 0x3c59, 0xe42e, 0xd1d0,
+	0x0000, 0xd1d1, 0x0000, 0xcb1c, 0xf7f8, 0xcbe0, 0xf7f8, 0xe16b,
+	0xe42e, 0xd185, 0x0002, 0xd186, 0x0000, 0xd1c2, 0x0001, 0xd1c5,
+	0x0000, 0xd1c4, 0x0000, 0xd1d0, 0x000e, 0xcba0, 0xf7f8, 0x2054,
+	0x4c55, 0xf098, 0xd1c2, 0x0000, 0xd1c5, 0x0003, 0xd1c4, 0x0003,
+	0xd1c8, 0x0000, 0xd1d0, 0x0020, 0xe41e, 0x2555, 0xa200, 0xe0c2,
+	0x012a, 0xcbe0, 0xf7f8, 0x285a, 0xe41a, 0x2578, 0xcba0, 0xf7f8,
+	0xd186, 0x0001, 0xd185, 0x0004, 0xe41e, 0x2588, 0xcb06, 0x3c59,
+	0xe42e, 0xa200, 0xe0c2, 0x0100, 0xe0c2, 0x013d, 0xe0c2, 0x0128,
+	0xcc8e, 0x2a88, 0xb692, 0xae08, 0xa91c, 0xe0c2, 0x017c, 0xa218,
+	0xe0c2, 0x017d, 0xa200, 0xe41e, 0x21e4, 0x2a22, 0xe017, 0xae09,
+	0xe056, 0xa203, 0xae11, 0xe056, 0xe0c2, 0x0213, 0xa200, 0xe0c2,
+	0x0215, 0xa202, 0xe0c2, 0x0210, 0x2057, 0x4c58, 0xae08, 0xe0c2,
+	0x0101, 0xe0c2, 0x0205, 0xa200, 0xe41e, 0x21e4, 0x2a22, 0xe017,
+	0xae07, 0xe056, 0xe0c2, 0x0102, 0xe42e, 0xe0c0, 0x0050, 0xe049,
+	0xe008, 0x007f, 0x3c08, 0xaf11, 0xe009, 0x007f, 0x3e09, 0x4608,
+	0x3e08, 0xa200, 0x2a08, 0xa803, 0xf03b, 0xe00a, 0x0002, 0x2a08,
+	0xa805, 0xf02b, 0xa912, 0x2a08, 0xa809, 0xf02b, 0xa940, 0x2a08,
+	0xa811, 0xf02b, 0xa980, 0xe0c2, 0x040c, 0xe0c1, 0x0046, 0xe004,
+	0x0002, 0xae10, 0xe042, 0x2a09, 0xa803, 0xf05b, 0xe161, 0x05cb,
+	0x2111, 0x4d11, 0xcf0e, 0xe0c1, 0x0046, 0xe004, 0x004a, 0xae10,
+	0xe042, 0x2a09, 0xa805, 0xf05b, 0xe161, 0x05cd, 0x2111, 0x4d11,
+	0xe0c2, 0x0103, 0xe0c1, 0x0046, 0xe004, 0x007a, 0xae10, 0xe042,
+	0x2a09, 0xa809, 0xf05b, 0xe161, 0x05cf, 0x2111, 0x4d11, 0xe0c2,
+	0x0211, 0xe0c1, 0x0046, 0xe004, 0x007a, 0xe000, 0x0040, 0xae10,
+	0xe042, 0x2a09, 0xa811, 0xf05b, 0xe161, 0x05d1, 0x2111, 0x4d11,
+	0xe0c2, 0x0212, 0xa200, 0xe0c2, 0x0104, 0xe0c2, 0x0204, 0xa200,
+	0xe0c2, 0x0208, 0xe41e, 0x2596, 0xa20e, 0xe0c2, 0x0312, 0xe0c0,
+	0x0414, 0xe418, 0x018c, 0xe0c0, 0x0414, 0xe41a, 0x25be, 0xe41e,
+	0x0274, 0xa202, 0xe0c2, 0x0106, 0xe42e, 0xa200, 0xe0c2, 0x0113,
+	0xe0c2, 0x030d, 0xe0c2, 0x022b, 0xcb94, 0xe0c2, 0x0115, 0xcba4,
+	0xe0c2, 0x012a, 0xcb8a, 0xe0c2, 0x0114, 0xa802, 0x3c5a, 0xe42a,
+	0xcb14, 0xae0a, 0xcb19, 0xe056, 0xe0c2, 0x0120, 0xcb8c, 0xe0c2,
+	0x0121, 0xcb8e, 0xe0c2, 0x0122, 0xcb90, 0xe0c2, 0x0123, 0xe42e,
+	0xcbd0, 0xe0c2, 0x030c, 0xcbd2, 0xe0c2, 0x0309, 0xcbd8, 0xe0c2,
+	0x030a, 0xcbda, 0xe0c2, 0x030b, 0xa200, 0xe0c2, 0x0320, 0xe42e,
+	0xe0c0, 0x0111, 0xf7e8, 0xa202, 0xe0c2, 0x0110, 0x2888, 0xe418,
+	0x22c5, 0xe42e, 0xe0c0, 0x0111, 0xf7e8, 0xe42e, 0xa202, 0xe0c2,
+	0x0302, 0xd022, 0x000f, 0xe163, 0x0380, 0x2883, 0xb608, 0xe184,
+	0x25a4, 0x9f03, 0x8113, 0x8113, 0x8113, 0x2819, 0xf14a, 0xa102,
+	0xcc44, 0xe160, 0x0004, 0xe161, 0x0203, 0xe163, 0x0380, 0xe184,
+	0x25b8, 0x2931, 0xf022, 0x2883, 0xb608, 0x9f03, 0x8113, 0x8113,
+	0x8113, 0xe190, 0xa200, 0xe0c2, 0x0302, 0xe42e, 0xe167, 0x01a0,
+	0x2317, 0x4f17, 0xe0c3, 0x0152, 0x2b17, 0xe009, 0x00ff, 0xae21,
+	0x4f07, 0xe0c3, 0x0153, 0xe0c1, 0x0101, 0xe0c3, 0x015d, 0xe162,
+	0x02b0, 0x2912, 0xaf02, 0x3c0a, 0x2912, 0xaf02, 0x3c0b, 0x280a,
+	0x180b, 0xf0d8, 0xe162, 0x02b0, 0xd022, 0x001f, 0xe184, 0x25e5,
+	0x2912, 0xaf02, 0x3c0b, 0x180a, 0xf028, 0xe190, 0x280b, 0xae02,
+	0xe41e, 0x0e94, 0xe049, 0xae11, 0x280a, 0xae02, 0xe41e, 0x0e94,
+	0xe055, 0xae21, 0xe167, 0x01a2, 0x2907, 0xaf10, 0xe008, 0x001f,
+	0xe055, 0xe0c3, 0x015c, 0xa202, 0xe0c2, 0x0150, 0xe0c0, 0x0150,
+	0xf7ea, 0xa200, 0xe0c2, 0x0150, 0xe0c0, 0x0151, 0xf7e8, 0xe42e,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010,
+	0x060d, 0x0d14, 0x1414, 0x1c1c, 0x1c1c, 0x2020, 0x2025, 0x252a,
+	0x0a0e, 0x0e14, 0x1414, 0x1818, 0x1818, 0x1b1b, 0x1b1e, 0x1e22,
+	0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010,
+	0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010,
+	0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010,
+	0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010, 0x1010,
+	0x060a, 0x0a0d, 0x0b0d, 0x1010, 0x1010, 0x1212, 0x1212, 0x1217,
+	0x1717, 0x1717, 0x1719, 0x1919, 0x1919, 0x1919, 0x1b1b, 0x1b1b,
+	0x1b1b, 0x1b1b, 0x1d1d, 0x1d1d, 0x1d1d, 0x1d1f, 0x1f1f, 0x1f1f,
+	0x1f21, 0x2121, 0x2121, 0x2424, 0x2424, 0x2626, 0x2628, 0x282a,
+	0x090d, 0x0d0f, 0x0d0f, 0x1111, 0x1111, 0x1313, 0x1313, 0x1315,
+	0x1515, 0x1515, 0x1516, 0x1616, 0x1616, 0x1616, 0x1818, 0x1818,
+	0x1818, 0x1818, 0x1919, 0x1919, 0x1919, 0x191b, 0x1b1b, 0x1b1b,
+	0x1b1c, 0x1c1c, 0x1c1c, 0x1e1e, 0x1e1e, 0x2020, 0x2021, 0x2123,
+	0x0000, 0x0001, 0x0004, 0x0008, 0x0005, 0x0002, 0x0003, 0x0006,
+	0x0009, 0x000c, 0x000d, 0x000a, 0x0007, 0x000b, 0x000e, 0x000f,
+	0x0000, 0x0001, 0x0008, 0x0010, 0x0009, 0x0002, 0x0003, 0x000a,
+	0x0011, 0x0018, 0x0020, 0x0019, 0x0012, 0x000b, 0x0004, 0x0005,
+	0x000c, 0x0013, 0x001a, 0x0021, 0x0028, 0x0030, 0x0029, 0x0022,
+	0x001b, 0x0014, 0x000d, 0x0006, 0x0007, 0x000e, 0x0015, 0x001c,
+	0x0023, 0x002a, 0x0031, 0x0038, 0x0039, 0x0032, 0x002b, 0x0024,
+	0x001d, 0x0016, 0x000f, 0x0017, 0x001e, 0x0025, 0x002c, 0x0033,
+	0x003a, 0x003b, 0x0034, 0x002d, 0x0026, 0x001f, 0x0027, 0x002e,
+	0x0035, 0x003c, 0x003d, 0x0036, 0x002f, 0x0037, 0x003e, 0x003f,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0xe40e, 0x0020, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x0330, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x034a, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x003a, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058,
+	0xa200, 0xe0c2, 0x005a, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xa2fe,
+	0x3cee, 0x3cef, 0x3cec, 0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d,
+	0xce00, 0xf33e, 0xe41e, 0x0164, 0xe09e, 0xa202, 0xae3e, 0x9f07,
+	0xe0c0, 0x005c, 0xe0c1, 0x0059, 0x3eed, 0xa203, 0x5aed, 0xe052,
+	0xf08a, 0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00,
+	0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2, 0x0008, 0xf00e,
+	0x28ee, 0xe412, 0x013d, 0xe190, 0xe0c0, 0x005c, 0xe0c1, 0x0059,
+	0x3eed, 0xa203, 0x5aed, 0xe052, 0xf08a, 0xe0c1, 0x005d, 0xe055,
+	0xe0c3, 0x005d, 0xa202, 0xce00, 0xe0c0, 0x004a, 0xf08a, 0xe41e,
+	0x019c, 0xe408, 0x005c, 0xe40e, 0x0058, 0xe190, 0xe0c0, 0x043d,
+	0xa1ee, 0xf7d8, 0xe004, 0x0060, 0xe0c2, 0x0009, 0xa200, 0xe0c2,
+	0x0009, 0xe0c0, 0x000d, 0xf7e8, 0xe41e, 0x00b2, 0xe41e, 0x00e2,
+	0xe41e, 0x012c, 0xd071, 0x242a, 0xe181, 0xe41e, 0x0164, 0xe09e,
+	0xa202, 0x9f07, 0xe0c0, 0x0049, 0xe0c1, 0x005b, 0xa111, 0xf033,
+	0xe0c0, 0x0048, 0xe0c2, 0x0047, 0xe0c0, 0x0059, 0xae02, 0xe000,
+	0x0330, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a, 0xe008, 0xffff,
+	0x3cee, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11, 0xe056, 0x3cef,
+	0xe40e, 0x0058, 0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2,
+	0x0008, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xe0c0, 0x0059, 0xf7ea,
+	0xa11e, 0xf198, 0xa202, 0xe0c2, 0x0058, 0xe004, 0xca20, 0xae20,
+	0xe005, 0x210a, 0xe056, 0xe0c2, 0x0070, 0xe004, 0x0000, 0xae20,
+	0xe00a, 0x9cea, 0xe0c2, 0x0071, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+	0x0058, 0xf64e, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058, 0xd027,
+	0x0001, 0xe42e, 0xa200, 0xe0c1, 0x005b, 0xf21b, 0xa23c, 0xa103,
+	0xf37b, 0xa24c, 0xa103, 0xf34b, 0xa258, 0xa103, 0xf1db, 0xe004,
+	0x003a, 0xa103, 0xf2db, 0xe004, 0x003f, 0xa103, 0xf29b, 0xe004,
+	0x0045, 0xa103, 0xf25b, 0xa103, 0xf14b, 0xe004, 0x0063, 0xa103,
+	0xf1ab, 0xe004, 0x006a, 0xa107, 0xf1bb, 0xa200, 0xe0c1, 0x005e,
+	0xf17b, 0xa028, 0xf15e, 0xe0c1, 0x005e, 0xf12b, 0xa010, 0xf10e,
+	0xe004, 0x0049, 0xe0c1, 0x005e, 0xf0bb, 0xa010, 0xa103, 0xf08b,
+	0xa010, 0xf06e, 0xe0c1, 0x005e, 0xf03b, 0xe004, 0x0074, 0xae16,
+	0xe0c1, 0x0040, 0xe041, 0xce21, 0xd111, 0x0000, 0xd112, 0x2800,
+	0xd113, 0x000b, 0xe1e1, 0xe42e, 0xe41e, 0x023a, 0xe0c0, 0x0059,
+	0xa102, 0xe42a, 0xe0c0, 0x005b, 0xa810, 0xf058, 0xa206, 0xe41e,
+	0x0153, 0xe42e, 0xe004, 0x0350, 0xe67c, 0xe0c0, 0x005b, 0xa810,
+	0xf058, 0xa204, 0xe41e, 0x0153, 0xe42e, 0xe004, 0x0352, 0xe67c,
+	0xa200, 0xc401, 0xe188, 0x00eb, 0x3d11, 0xe161, 0x00f2, 0xe188,
+	0x0b0d, 0x3d11, 0xe42e, 0x3cec, 0xe0c0, 0x0041, 0xe005, 0x0000,
+	0xae11, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0c00, 0x88ec,
+	0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0059, 0xa106, 0xf048,
+	0xe004, 0x0076, 0xe42e, 0xe0c0, 0x0059, 0xa10c, 0xf038, 0xe004,
+	0x0071, 0xe004, 0x0070, 0xe42e, 0xe0c0, 0x006b, 0xe167, 0x01a0,
+	0x3d07, 0xe0c0, 0x0414, 0xe428, 0xe0c1, 0x0044, 0xa809, 0xae33,
+	0xe0c0, 0x006a, 0xe167, 0x01a0, 0x3517, 0x3d17, 0xe0c0, 0x006b,
+	0xe056, 0x3517, 0x3d07, 0xe42e, 0xe167, 0x01a0, 0x2907, 0xe0c2,
+	0x0151, 0xa204, 0xe0c2, 0x0150, 0xe0c0, 0x0150, 0xa804, 0xf7da,
+	0xa208, 0xe0c2, 0x0150, 0xe42e, 0xe0c0, 0x004a, 0xe42a, 0xe0c0,
+	0x005b, 0xa110, 0xf142, 0xe0c0, 0x0059, 0xa102, 0xe41a, 0x01be,
+	0xe0c0, 0x0059, 0xa106, 0xe41a, 0x01cb, 0xe0c0, 0x0047, 0xe0c2,
+	0x0048, 0xa200, 0xe0c2, 0x004a, 0xa202, 0xe42e, 0xe0c0, 0x0047,
+	0xe0c2, 0x0049, 0xa200, 0xe0c2, 0x004a, 0xe42e, 0xe0c0, 0x004a,
+	0xa802, 0xa23e, 0x3cf0, 0xa202, 0x58f0, 0xe0c2, 0x0078, 0xa220,
+	0xe0c2, 0x0070, 0xe42e, 0xe0c0, 0x004a, 0xa802, 0xa220, 0xe0c2,
+	0x0076, 0xa200, 0xe0c2, 0x0072, 0xa2fc, 0xe0c2, 0x0077, 0xa2fa,
+	0xe0c2, 0x0071, 0xe42e, 0xe0c0, 0x0045, 0xaf04, 0xa80e, 0xa104,
+	0xe428, 0xa202, 0xe0c2, 0x004a, 0xe0c0, 0x0111, 0xf7e8, 0xca28,
+	0xf7f8, 0xca48, 0xa802, 0xf7e8, 0xa208, 0xae14, 0xa102, 0xe190,
+	0xf7e2, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xe0c0, 0x041f, 0xf7e8,
+	0xa200, 0xe0c2, 0x041c, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xe004,
+	0x0078, 0xe0c2, 0x0009, 0xa200, 0xe0c2, 0x0009, 0xe0c0, 0x000d,
+	0xf7e8, 0xe42e, 0xc001, 0x3443, 0x3c42, 0xc000, 0xe42e, 0xc001,
+	0x2c43, 0x2e42, 0xc000, 0xe42a, 0x1c1e, 0xf0b4, 0xe04a, 0xaf10,
+	0x1857, 0xf074, 0xe009, 0x00ff, 0x1a58, 0xf034, 0xa202, 0xe42e,
+	0xa2fe, 0xe42e, 0xe41e, 0x023a, 0xd160, 0x0620, 0xe004, 0x0019,
+	0xae18, 0xcec0, 0xe42e, 0xe41e, 0x024f, 0xe000, 0x0040, 0xce50,
+	0xa200, 0xd022, 0x00ff, 0xe184, 0x0236, 0xce52, 0xe190, 0xe41e,
+	0x0257, 0xe42e, 0xa204, 0xae22, 0xcc9e, 0xa200, 0xcc72, 0xcc8c,
+	0xcc8e, 0xe004, 0xa810, 0xae20, 0xe00a, 0x9322, 0xce4a, 0xd16f,
+	0x0003, 0xe190, 0xe190, 0xe190, 0xd16f, 0x0000, 0xe42e, 0xe004,
+	0x0030, 0xce50, 0xca50, 0xa802, 0xf7ea, 0xc000, 0xe42e, 0xe004,
+	0x0020, 0xce50, 0xe42e, 0xa200, 0xe0c2, 0x041c, 0xe42e, 0xe41e,
+	0x02bb, 0xe42a, 0xe0c0, 0x0061, 0xe008, 0x001f, 0xe00a, 0x0100,
+	0xe0c2, 0x041c, 0xe41e, 0x02f1, 0xe41e, 0x032b, 0xae12, 0xe0c2,
+	0x041e, 0xe41e, 0x031b, 0xe42e, 0xe41e, 0x02df, 0xe42a, 0xe0c0,
+	0x041f, 0xf7e8, 0xe0c0, 0x0210, 0xa804, 0xf118, 0xe0c0, 0x0215,
+	0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0216, 0xf0be, 0xe0c0, 0x0213,
+	0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0214, 0xf03e, 0xe0c0, 0x020b,
+	0xe00a, 0x0100, 0xe0c2, 0x041c, 0xe41e, 0x02f1, 0xe41e, 0x032b,
+	0xae12, 0xe0c1, 0x0210, 0xa803, 0xae15, 0xe056, 0xe0c1, 0x0204,
+	0xaf0b, 0xa87f, 0xae07, 0xe056, 0xe0c1, 0x0204, 0xa80f, 0xe056,
+	0xe0c2, 0x041e, 0xe41e, 0x031b, 0xe42e, 0xe0c0, 0x041f, 0xf7e8,
+	0xe0c0, 0x041f, 0xf7e8, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xa200,
+	0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xa203, 0xae19, 0xe052,
+	0xf1da, 0xe0c0, 0x0060, 0xaf08, 0xa806, 0xf18a, 0xe0c0, 0x0060,
+	0xa81e, 0xe016, 0xe0c1, 0x0060, 0xa821, 0xe017, 0xe056, 0xf0ea,
+	0xe0c0, 0x0044, 0xaf12, 0xa806, 0xe016, 0xe0c1, 0x0044, 0xaf17,
+	0xa803, 0xe056, 0xf03a, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xe0c0,
+	0x0044, 0xa203, 0xae19, 0xe052, 0xf0ba, 0xe41e, 0x02bb, 0xf088,
+	0xe0c0, 0x0044, 0xaf12, 0xa806, 0xf038, 0xa202, 0xe42e, 0xa200,
+	0xe42e, 0xe0c0, 0x041c, 0xe008, 0x00ff, 0xcca4, 0xc785, 0xe018,
+	0xe000, 0x0500, 0xa002, 0xae04, 0xe0c2, 0x041a, 0xa202, 0xe0c2,
+	0x0418, 0xe0c0, 0x0419, 0xf7ea, 0xa202, 0xe0c2, 0x0418, 0xe0c0,
+	0x0419, 0xf7ea, 0xe0c0, 0x041b, 0xaf20, 0xa01e, 0xaf08, 0xae28,
+	0xe0c1, 0x041b, 0xe009, 0xffff, 0xa01f, 0xaf09, 0xae09, 0xe056,
+	0xe0c2, 0x041d, 0xe42e, 0xe0c0, 0x041c, 0xe00a, 0x0200, 0xe0c2,
+	0x041c, 0xa228, 0xa102, 0xf7f0, 0xe0c0, 0x041c, 0xe00c, 0x0200,
+	0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xaf04, 0xa802, 0xe42e,
+	0xe40e, 0x0c6b, 0xe40e, 0x0354, 0xe40e, 0x0358, 0xe40e, 0x035c,
+	0xe40e, 0x0368, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x036c,
+	0xe40e, 0x0370, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe41e, 0x0380, 0xe40e, 0x00a4,
+	0xe41e, 0x03a1, 0xe40e, 0x00a4, 0xe41e, 0x025b, 0xe41e, 0x100e,
+	0xe41e, 0x044b, 0xe41e, 0x100b, 0xe41e, 0x02ad, 0xe40e, 0x00a4,
+	0xe41e, 0x0537, 0xe40e, 0x00a4, 0xe41e, 0x053c, 0xe40e, 0x00a4,
+	0xe41e, 0x056d, 0xe40e, 0x00a4, 0xe167, 0x05cb, 0xe166, 0x0064,
+	0xd022, 0x0003, 0xe184, 0x037e, 0x9e16, 0x3517, 0x3d17, 0xe42e,
+	0xa200, 0x3c86, 0x3cad, 0x3cbe, 0xe41e, 0x0416, 0xe41e, 0x055a,
+	0xe41e, 0x0680, 0xe41e, 0x08ff, 0xe41e, 0x03a2, 0xf0dd, 0xe41e,
+	0x08b8, 0xe41a, 0x03e2, 0xa2fe, 0x3c10, 0x3c83, 0xe41e, 0x0523,
+	0xf03a, 0xa202, 0x3c86, 0xe41e, 0x0b47, 0xe41e, 0x06f0, 0xe16a,
+	0xe42e, 0xe42e, 0xa23e, 0x3cf0, 0xe41e, 0x08b8, 0xe408, 0x03bb,
+	0xe41e, 0x0b81, 0xa10e, 0xf13a, 0xa104, 0xf2ca, 0xa102, 0xf05a,
+	0xf04a, 0xe41e, 0x094c, 0xf6fe, 0xe41e, 0x08b8, 0xe408, 0x03bb,
+	0xe41e, 0x0985, 0xf68e, 0xe41e, 0x01db, 0xf23e, 0xe41e, 0x14a6,
+	0xe41e, 0x0985, 0xa2fe, 0x3c10, 0xe41e, 0x1af7, 0xf5ca, 0x2800,
+	0x3c10, 0xe41e, 0x1b12, 0xe092, 0xa200, 0xe41e, 0x0c4f, 0xa200,
+	0x3c9b, 0x28d6, 0xe41a, 0x146b, 0xa2fe, 0x3c10, 0xe082, 0xf096,
+	0xe42e, 0xe41e, 0x14ad, 0xe41e, 0x14a6, 0xe41e, 0x094c, 0xf43e,
+	0xe16b, 0xe42e, 0xe41e, 0x0b81, 0xf11a, 0xa102, 0xe40a, 0x03ff,
+	0xa108, 0xf0c4, 0xf15a, 0xa108, 0xf136, 0xa102, 0xf0aa, 0xa102,
+	0xf08a, 0xa106, 0xf0da, 0xa102, 0xf0ba, 0xe41e, 0x094c, 0xf6be,
+	0xe41e, 0x08b8, 0xe408, 0x03ff, 0xe41e, 0x0985, 0xf64e, 0xe42e,
+	0xa200, 0xe161, 0x0100, 0xe188, 0x0aff, 0x3d11, 0xe0c0, 0x0041,
+	0xe005, 0x0034, 0xae11, 0xe042, 0xce20, 0xd111, 0x0100, 0xd112,
+	0x0180, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0xe41e, 0x0400,
+	0xe41e, 0x0222, 0xe41e, 0x0148, 0xa204, 0x3cae, 0xe16a, 0xd130,
+	0x0000, 0xd03a, 0x0000, 0xd04c, 0x0000, 0xd008, 0x0000, 0xd022,
+	0x0000, 0xa200, 0xe0c2, 0x0100, 0xe0c2, 0x0128, 0xa2fe, 0x3c25,
+	0x3c26, 0x3c27, 0x3c28, 0x3c10, 0x3c29, 0x3c56, 0x3cda, 0x3cd7,
+	0xe161, 0x05c7, 0x3511, 0x3d11, 0x3511, 0x3d11, 0xe41e, 0x0c3a,
+	0xe41e, 0x1ae6, 0xe41e, 0x1fef, 0xe41e, 0x1654, 0xe41e, 0x26e2,
+	0xa200, 0x3cd8, 0xe42e, 0xa200, 0x3c86, 0xe41e, 0x0680, 0xe41e,
+	0x1aa9, 0xe41e, 0x04d9, 0xe41e, 0x0909, 0xe41e, 0x0675, 0xe41e,
+	0x0523, 0xe40a, 0x04d6, 0xe41e, 0x13a7, 0xe408, 0x0465, 0xe41e,
+	0x08b8, 0xe408, 0x04d6, 0xe40e, 0x04bd, 0xe41e, 0x020f, 0xe404,
+	0x04bd, 0xe41e, 0x0675, 0xa202, 0x3c86, 0x28bd, 0xf09a, 0xe41e,
+	0x066c, 0xa2fe, 0x3c84, 0xa202, 0x3cb4, 0xe40e, 0x04bd, 0x28a4,
+	0xf0b4, 0xa202, 0x3cb4, 0xe41e, 0x14ad, 0xe41e, 0x066c, 0xa200,
+	0x3c3a, 0xe40e, 0x04bd, 0xe41e, 0x05c8, 0xf05a, 0xe41e, 0x05ed,
+	0xe40e, 0x04ac, 0xe41e, 0x1adb, 0x2884, 0xe414, 0x066c, 0x2884,
+	0xe404, 0x04bd, 0x2884, 0xe41e, 0x2064, 0xe41e, 0x21bf, 0xe41e,
+	0x05bb, 0x28a5, 0xf128, 0x2a4e, 0x4e40, 0x2884, 0xe41b, 0x1ff5,
+	0x284e, 0xe418, 0x1c69, 0x28d6, 0xf038, 0x2a84, 0x3ed7, 0x2840,
+	0xe41a, 0x191c, 0x287e, 0x3c82, 0x2840, 0xf058, 0xe41e, 0x064f,
+	0xe41e, 0x0654, 0xe41e, 0x0659, 0xa200, 0xe41e, 0x26fc, 0x2840,
+	0xaa02, 0x443f, 0xf03a, 0xe40e, 0x045b, 0xe41e, 0x21a6, 0xe41e,
+	0x14ad, 0xe41e, 0x08d2, 0xf04a, 0xe41e, 0x1a5c, 0x3ce9, 0xe41e,
+	0x194b, 0x3c85, 0x2885, 0x3c56, 0x2884, 0xf024, 0x3c83, 0xe41e,
+	0x06f0, 0xe41e, 0x1ac4, 0xe41e, 0x0b47, 0xe42e, 0xa202, 0x3c86,
+	0xf65e, 0xa200, 0xcc4a, 0xcc4c, 0x3c53, 0x3c62, 0x3cbd, 0x3cae,
+	0x3cb4, 0x3ca5, 0x3c97, 0x3ca8, 0x3ca9, 0x28ad, 0xe41a, 0x0646,
+	0xe41e, 0x064f, 0xe41e, 0x0654, 0xe41e, 0x0659, 0xa2fe, 0x3cba,
+	0x3cbb, 0x3cb9, 0xa200, 0x3cbc, 0xa2fe, 0x3ca4, 0xa204, 0x3cf0,
+	0xa2fc, 0x3c84, 0xa2fa, 0x3c85, 0xa2fe, 0xc009, 0x3c3f, 0x3c40,
+	0x3c41, 0x3c42, 0xc000, 0xe42e, 0xa200, 0xe42e, 0xa200, 0xcc44,
+	0xd152, 0x0000, 0xd130, 0x0000, 0xd1e0, 0x0003, 0xd1ff, 0x03b0,
+	0xd1fd, 0x03d0, 0xd199, 0x0224, 0xd1fc, 0x0720, 0xd03a, 0x0000,
+	0xd04c, 0x0000, 0xd008, 0x0000, 0xd14b, 0x0200, 0x28b1, 0xcfce,
+	0xe41e, 0x025f, 0xe42e, 0xe0c0, 0x0059, 0xa102, 0xf0da, 0xe41e,
+	0x08b8, 0xf04a, 0xe41e, 0x01db, 0xf09e, 0xe41e, 0x2034, 0x2a84,
+	0xb7f5, 0x3e84, 0xf03a, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xe41e,
+	0x0680, 0xe41e, 0x2151, 0xe42e, 0xe0c0, 0x0042, 0xce20, 0xd111,
+	0x0000, 0xd112, 0x0080, 0xd113, 0x0013, 0xca28, 0xf7f8, 0xe0c0,
+	0x0061, 0xe41e, 0x0c18, 0xa202, 0xe41e, 0x0c22, 0xe41e, 0x0a1f,
+	0xe128, 0xe0c0, 0x0060, 0xf048, 0xe41e, 0x1af7, 0xf03e, 0xe41e,
+	0x1b28, 0xe42e, 0xe0c0, 0x0040, 0xa201, 0xae17, 0xe042, 0xe005,
+	0x4f00, 0xae03, 0xe042, 0xce20, 0xd111, 0x0450, 0xd112, 0x00c8,
+	0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e, 0xe180, 0xa2fe, 0x3c29,
+	0x3c10, 0xe41e, 0x1fef, 0xe41e, 0x05ab, 0x2821, 0xf05a, 0x2816,
+	0xa104, 0xf02a, 0x28ea, 0x3ce9, 0xa200, 0x3c81, 0x3ce7, 0x3ce6,
+	0x3ce8, 0x3ce5, 0xe166, 0x05ab, 0xc710, 0x3d16, 0xe167, 0x0518,
+	0xe166, 0x0054, 0xa200, 0x3cb2, 0x287f, 0xa102, 0xcc44, 0xe184,
+	0x0598, 0x9e06, 0x5cb2, 0xa802, 0xb690, 0x3d17, 0x28b2, 0xa002,
+	0x3cb2, 0xe190, 0xa200, 0x3c60, 0xe41e, 0x0c4f, 0xe42e, 0x24b5,
+	0x4cb6, 0xce20, 0xd111, 0x0600, 0xd112, 0x0004, 0xd113, 0x0000,
+	0xca28, 0xf7f8, 0xe42e, 0xe161, 0x0200, 0xa200, 0xc73f, 0x3d11,
+	0x3cb2, 0xd022, 0x001f, 0xe184, 0x05b9, 0xe41e, 0x1ff5, 0x28b2,
+	0xa002, 0x3cb2, 0xe42e, 0x2abc, 0x4e4f, 0x3ebc, 0x28a1, 0x3cb9,
+	0x2a3f, 0xf06b, 0x2a42, 0xf039, 0x3cba, 0xf02e, 0x3cbb, 0xe42e,
+	0x28a5, 0xf228, 0x28a5, 0xe016, 0x4440, 0xf1c8, 0x28a5, 0xe016,
+	0x44d6, 0xf188, 0xe41e, 0x062e, 0xf07a, 0xe41e, 0x0633, 0xf07a,
+	0x284f, 0xf108, 0xf11e, 0xe41e, 0x0638, 0xf06a, 0x28d6, 0xf0c8,
+	0x2838, 0xf0a8, 0xf07e, 0xe41e, 0x063f, 0xf04a, 0x284e, 0xf04a,
+	0xf01e, 0xa200, 0xe42e, 0xa202, 0xe42e, 0xa202, 0x3ca5, 0x2884,
+	0xe412, 0x1ff5, 0x2884, 0xe412, 0x1ffc, 0x2884, 0xe412, 0x2005,
+	0xa2fc, 0x3c84, 0x3c3e, 0xe41e, 0x0602, 0xe41e, 0x0b30, 0xe41e,
+	0x0909, 0xe42e, 0xe41e, 0x0b81, 0xf15a, 0xa102, 0xf17a, 0xa108,
+	0xf114, 0xf14a, 0xa102, 0xf0da, 0xa102, 0xf0ba, 0xa102, 0xf09a,
+	0xa102, 0xf07a, 0xa104, 0xf056, 0xa102, 0xf04a, 0xa10e, 0xf022,
+	0xe42e, 0xe41e, 0x094c, 0xe40e, 0x0602, 0xcaa2, 0xaf0a, 0xa806,
+	0x184e, 0xf0a8, 0xe41e, 0x0985, 0xe41e, 0x23c4, 0xf5ca, 0x2894,
+	0xf5aa, 0xe41e, 0x0b78, 0xe41e, 0x0b30, 0xe42e, 0xe0c0, 0x0065,
+	0xaf04, 0xa802, 0xe42e, 0xe0c0, 0x0065, 0xaf16, 0xa802, 0xe42e,
+	0xe0c0, 0x0065, 0xaf06, 0xa806, 0xa102, 0xe016, 0xe42e, 0xe0c0,
+	0x0065, 0xaf06, 0xa806, 0xa104, 0xe016, 0xe42e, 0xe41e, 0x0b30,
+	0xe0c0, 0x0048, 0xc009, 0x3433, 0x3c34, 0xc000, 0xe42e, 0xc009,
+	0x2433, 0x4c34, 0xc000, 0xe42e, 0xc009, 0x3435, 0x3c36, 0xc000,
+	0xe42e, 0xe41e, 0x0b30, 0xe0c0, 0x0048, 0xc009, 0x3437, 0x3c38,
+	0xc000, 0xe42e, 0xc009, 0x2435, 0x4c36, 0xc000, 0xe42e, 0xc009,
+	0x2437, 0x4c38, 0xc000, 0xe42e, 0xe41e, 0x0b78, 0x28ad, 0xe42a,
+	0xe41e, 0x064f, 0xe0c2, 0x0048, 0xe42e, 0xe41e, 0x20c3, 0xe41e,
+	0x20f6, 0xe41e, 0x0506, 0xe41e, 0x255a, 0xe41e, 0x2156, 0xe42e,
+	0xe0c0, 0x0059, 0xa102, 0xf2ca, 0xa102, 0xe42a, 0xa102, 0xf05a,
+	0xa102, 0xe40a, 0x06c6, 0xe42e, 0xe0c0, 0x006b, 0x34b5, 0x3cb6,
+	0xe0c0, 0x006c, 0x34b7, 0x3cb8, 0xe0c0, 0x0060, 0xaf08, 0x3088,
+	0xe0c0, 0x0060, 0xa81e, 0x3c87, 0xe0c0, 0x0061, 0xa83e, 0x3c8a,
+	0xe0c0, 0x0065, 0xa840, 0xf0ba, 0xa200, 0xe167, 0x0600, 0xc703,
+	0x3d17, 0xe41e, 0x059f, 0xe004, 0x0088, 0x3ca7, 0xe42e, 0xc001,
+	0xe0c0, 0x0060, 0x3400, 0x3c01, 0xe0c0, 0x0061, 0xae14, 0x3406,
+	0x3c07, 0xc000, 0xe0c0, 0x0062, 0xaf02, 0x3021, 0xaf02, 0x30aa,
+	0xa200, 0xe0c0, 0x0067, 0xa802, 0x3cb1, 0xe42e, 0xe41e, 0x0374,
+	0xe41e, 0x0174, 0xe0c0, 0x0042, 0xce20, 0xd111, 0x0640, 0xd112,
+	0x00c0, 0xd113, 0x0003, 0xca29, 0xf7f9, 0xa200, 0xe41e, 0x0fb1,
+	0xe004, 0x0040, 0xe41e, 0x0fb1, 0xe0c0, 0x0060, 0x3c7f, 0xe0c0,
+	0x0061, 0x3c66, 0xe0c0, 0x006e, 0xe41e, 0x020a, 0xe167, 0x05fd,
+	0xe0c0, 0x0062, 0x3517, 0x3d17, 0xe0c0, 0x0063, 0x3d17, 0xe42e,
+	0xe0c0, 0x0059, 0xa102, 0xe40a, 0x0792, 0xa102, 0xe42a, 0xa102,
+	0xf05a, 0xa102, 0xe40a, 0x07ff, 0xe42e, 0x2861, 0xae04, 0x4c91,
+	0xae02, 0x4c90, 0xe0c2, 0x0060, 0xc009, 0x203f, 0x4c40, 0xe0c2,
+	0x0061, 0x2041, 0x4c42, 0xc000, 0xe0c2, 0x0062, 0xe41e, 0x165f,
+	0xe0c2, 0x0067, 0xe41e, 0x1664, 0xe0c2, 0x0068, 0xe41e, 0x1669,
+	0xe0c2, 0x0069, 0xe41e, 0x1654, 0x2a23, 0xe41b, 0x0841, 0x2a3f,
+	0xe419, 0x0841, 0xae02, 0x4c23, 0xe0c2, 0x006a, 0x283f, 0xf0ba,
+	0xc009, 0x203b, 0x4c3c, 0xe0c2, 0x006b, 0x203d, 0x4c3e, 0xe0c2,
+	0x006c, 0xc000, 0x2072, 0x4c73, 0xe0c2, 0x006c, 0xe41e, 0x14b0,
+	0xe0c2, 0x007b, 0x2057, 0x4c58, 0xae08, 0xe0c2, 0x006f, 0x28b0,
+	0xe0c2, 0x007a, 0x2054, 0x4c55, 0xa002, 0x3454, 0x3c55, 0xe0c2,
+	0x0070, 0x2885, 0xe0c2, 0x0071, 0x2c53, 0xe0c2, 0x0072, 0xe41e,
+	0x0800, 0xe0c2, 0x0073, 0x24a8, 0x4ca9, 0xe0c2, 0x0074, 0x2886,
+	0x2ab4, 0xae21, 0xe056, 0x2aae, 0xae23, 0xe056, 0x2abd, 0xae29,
+	0xe056, 0xe0c2, 0x0076, 0xe41e, 0x0662, 0xe0c2, 0x0051, 0xe41e,
+	0x0667, 0xe0c2, 0x0052, 0x2884, 0xe0c2, 0x0077, 0x2a22, 0xe161,
+	0x05e4, 0x2111, 0x4d11, 0xf02b, 0xae02, 0xe0c2, 0x0078, 0x2111,
+	0x4d11, 0xf02b, 0xae02, 0xe0c2, 0x0079, 0x2025, 0x4c26, 0xe0c2,
+	0x007c, 0xe167, 0x05c7, 0x2117, 0x4d17, 0xe0c2, 0x007e, 0x2117,
+	0x4d17, 0xe0c2, 0x007d, 0xc84a, 0xc84d, 0xae20, 0xe056, 0xe0c2,
+	0x0053, 0xe42e, 0xe41e, 0x14b0, 0xe0c2, 0x0063, 0x2a23, 0xe41b,
+	0x0841, 0x2a3f, 0xe419, 0x0841, 0xae02, 0x4c23, 0xe0c2, 0x0064,
+	0x2027, 0x4c28, 0xe0c2, 0x006d, 0x2886, 0xe0c2, 0x0070, 0x2057,
+	0x4c58, 0xae08, 0xe0c2, 0x0071, 0x2025, 0x4c26, 0xe0c2, 0x0072,
+	0x2821, 0xf0ca, 0x2816, 0xa104, 0xf09a, 0x28eb, 0x3cb3, 0xa006,
+	0xe0c2, 0x0073, 0x28ea, 0x3ce9, 0xf07e, 0x28eb, 0xa006, 0xe0c2,
+	0x0073, 0xa200, 0x3ce9, 0x28e9, 0xe0c2, 0x0074, 0xa200, 0xe0c2,
+	0x0075, 0x2a22, 0xe161, 0x05e4, 0x2111, 0x4d11, 0xf02b, 0xae02,
+	0xe0c2, 0x0076, 0x2111, 0x4d11, 0xf02b, 0xae02, 0xe0c2, 0x0077,
+	0x2886, 0xe016, 0x58f0, 0xe0c2, 0x0078, 0xe161, 0x05c7, 0x2111,
+	0x4d11, 0xe0c2, 0x007a, 0x2111, 0x4d11, 0xe0c2, 0x0079, 0xe41e,
+	0x14b0, 0xaf32, 0xa802, 0xae0c, 0x2a24, 0xae05, 0xe056, 0x4c1d,
+	0xae02, 0x2a1b, 0xe017, 0xe056, 0xae10, 0x4c1f, 0xae10, 0x4c11,
+	0x2a19, 0xe01b, 0xae3f, 0xe056, 0xe0c2, 0x007b, 0xe42e, 0xe42e,
+	0x2885, 0xe41e, 0x26d1, 0xe092, 0x2842, 0xe016, 0x5440, 0x443f,
+	0x3c00, 0xa200, 0x2a40, 0xf079, 0x2aa4, 0xf053, 0x2ab9, 0xa80f,
+	0xe056, 0xf12e, 0x2a00, 0xf09b, 0x2aba, 0xa80f, 0xae07, 0xe056,
+	0x2abb, 0xa80f, 0xe056, 0xf08e, 0x2abb, 0xa80f, 0xae07, 0xe056,
+	0x2aba, 0xa80f, 0xe056, 0x3c01, 0x28a3, 0x2a23, 0xe41b, 0x0841,
+	0x2a3f, 0xe419, 0x0841, 0xae02, 0x4c23, 0xae0c, 0x4c00, 0xae04,
+	0x4c43, 0xae02, 0x4c3f, 0xae24, 0x2a3f, 0xe017, 0x4e40, 0xae1f,
+	0xe056, 0xe083, 0xae21, 0xe056, 0x2abc, 0xae0d, 0xe056, 0x4c01,
+	0xe42e, 0x283f, 0xe42a, 0x28a4, 0xf0c2, 0xc009, 0x203b, 0x4c3c,
+	0x103d, 0x1c3e, 0xc000, 0xf030, 0xa206, 0xe42e, 0xa208, 0xe42e,
+	0x2823, 0xf048, 0xa202, 0x0842, 0xe42e, 0x28a3, 0xe42e, 0x3cec,
+	0xe0c0, 0x0041, 0xe005, 0x0018, 0xae11, 0xe042, 0xce20, 0xd111,
+	0x0000, 0xd112, 0x0100, 0x88ec, 0x0113, 0xca28, 0xf7f8, 0xe42e,
+	0x8917, 0x0034, 0x8917, 0x0033, 0x8917, 0x0035, 0x8917, 0x0036,
+	0x8917, 0x0037, 0x8917, 0x0038, 0x8117, 0x8117, 0x2117, 0x4d17,
+	0xcc60, 0x2117, 0x4d17, 0xcc62, 0x2117, 0x4d17, 0xcc64, 0x2117,
+	0x4d17, 0xcc72, 0xe42e, 0x8b17, 0x0034, 0x8b17, 0x0033, 0x8b17,
+	0x0035, 0x8b17, 0x0036, 0x8b17, 0x0037, 0x8b17, 0x0038, 0x8117,
+	0x8117, 0xc860, 0x3517, 0x3d17, 0xc862, 0x3517, 0x3d17, 0xc864,
+	0x3517, 0x3d17, 0xc872, 0x3517, 0x3d17, 0xe42e, 0xc001, 0x3c13,
+	0xc000, 0xe42e, 0xc001, 0x2813, 0xc000, 0xe42e, 0xc001, 0x3c14,
+	0xc000, 0xe42e, 0xc001, 0x2814, 0xc000, 0xe42e, 0xc001, 0x2430,
+	0x4c31, 0xc000, 0xae06, 0xc873, 0xe046, 0xe422, 0xe16b, 0xe42e,
+	0xc001, 0x280c, 0xf16a, 0xe41e, 0x0b30, 0xc001, 0xe0c0, 0x0049,
+	0x340e, 0x3c0f, 0x240e, 0x4c0f, 0xe0c1, 0x0048, 0x360e, 0x3e0f,
+	0x260e, 0x4e0f, 0xe045, 0xa200, 0xb626, 0xe003, 0x0200, 0xb606,
+	0xc000, 0xe42e, 0xe41e, 0x08b8, 0xe42a, 0xe0c0, 0x0045, 0xaf04,
+	0xa802, 0xe42e, 0xc001, 0x3c33, 0xc000, 0xe42e, 0xc001, 0x2833,
+	0xc000, 0xe42e, 0xc001, 0x3c11, 0xc000, 0xe42e, 0xc001, 0x2811,
+	0xc000, 0xe42e, 0xd148, 0x0040, 0xd144, 0x0000, 0xd145, 0x0000,
+	0xd168, 0x0000, 0xd16b, 0x0000, 0xd14b, 0x0200, 0xe004, 0x0019,
+	0xae18, 0xcec0, 0xd14c, 0x000c, 0xca9a, 0xf7f8, 0xe42e, 0xc001,
+	0x2400, 0x4c01, 0x0406, 0x0c07, 0x3408, 0x3c09, 0xd071, 0x202a,
+	0xe181, 0xc001, 0xe0c0, 0x0048, 0x3415, 0x3c16, 0x280c, 0xf13a,
+	0xe0c0, 0x0048, 0x340e, 0x3c0f, 0x240e, 0x4c0f, 0xe0c1, 0x0049,
+	0x3604, 0x3e05, 0x1404, 0x1c05, 0xe0c1, 0x0045, 0xaf05, 0xa803,
+	0xb611, 0x320c, 0xe0c0, 0x0048, 0x3402, 0xe008, 0xfe00, 0x3c03,
+	0xe0c0, 0x0048, 0xe008, 0x01ff, 0x3c0b, 0xa200, 0xcc78, 0xd022,
+	0x00ff, 0xe184, 0x0934, 0xcc7a, 0xe190, 0xe41e, 0x0a1f, 0xe41e,
+	0x0a3e, 0xe41e, 0x08ea, 0xc001, 0xa200, 0x3c1a, 0x280b, 0xa102,
+	0xe412, 0x0954, 0xc001, 0xa202, 0x3c1a, 0xa200, 0xceaa, 0xc000,
+	0xa200, 0xe41e, 0x0c4f, 0xe42e, 0xcaa0, 0xe190, 0xca9a, 0xf7f8,
+	0xca9c, 0xe418, 0x0a3e, 0xe42e, 0xcc44, 0xe184, 0x095d, 0xca9c,
+	0xe418, 0x0a3e, 0xcaa0, 0xca9b, 0xf7f9, 0xe190, 0xe42e, 0xe004,
+	0x0100, 0xceb0, 0xe004, 0x00ff, 0xe014, 0xceb8, 0xd15d, 0x0000,
+	0xd15e, 0x0000, 0xd15f, 0x0000, 0xe004, 0x0019, 0xae18, 0xe00a,
+	0x0620, 0xcec0, 0xd157, 0x0000, 0xd14a, 0x0000, 0xd14c, 0x0003,
+	0xca9c, 0xe418, 0x0a3e, 0xca9a, 0xf7c8, 0xcaae, 0xa802, 0xf73a,
+	0xca9c, 0xe418, 0x0a3e, 0xa200, 0xe42e, 0xe41e, 0x095f, 0xe41e,
+	0x08b8, 0xf128, 0xe41e, 0x0b6f, 0xcaa2, 0xe008, 0x00ff, 0xe41e,
+	0x089e, 0xaf0e, 0xe418, 0x094c, 0xe41e, 0x08a2, 0xaf0e, 0xf6e8,
+	0xe41e, 0x08b8, 0xf0ea, 0xe004, 0x010b, 0xe008, 0x00ff, 0xe41e,
+	0x089e, 0xe004, 0x010b, 0xa83e, 0xe41e, 0x08a6, 0xa200, 0xe42e,
+	0xe41e, 0x08a2, 0xf058, 0xa204, 0xe41e, 0x0954, 0xf57e, 0xa206,
+	0xe41e, 0x0954, 0xe41e, 0x08a2, 0xaf0a, 0x3c4e, 0xe41e, 0x08a2,
+	0xa83e, 0xe41e, 0x08a6, 0xe41e, 0x08a2, 0xa116, 0xe42a, 0xca9c,
+	0xe418, 0x0a3e, 0xe41e, 0x08aa, 0xa10a, 0xe016, 0x3c4f, 0xe41e,
+	0x08aa, 0xa128, 0xe016, 0x3cd6, 0xf11a, 0xa200, 0xe41e, 0x0954,
+	0xe41e, 0x089e, 0xaf0e, 0xf0a8, 0xe41e, 0x08a2, 0xaf0c, 0xa802,
+	0xe016, 0x3c4f, 0xa202, 0xe41e, 0x0954, 0xe41e, 0x09e0, 0xe42e,
+	0xc001, 0xa200, 0x3c30, 0x3c31, 0x3c33, 0xe41e, 0x09ee, 0xc001,
+	0xe41e, 0x0a1f, 0xc001, 0xe128, 0xc000, 0xe42e, 0xc001, 0x2833,
+	0x4411, 0xc000, 0xae0e, 0xce92, 0xd14a, 0x0000, 0xd158, 0x0000,
+	0xe004, 0x01ff, 0xe014, 0xceb8, 0xd15d, 0x0000, 0xd15e, 0x0000,
+	0xd15f, 0x0000, 0xd161, 0x0003, 0xe004, 0x0019, 0xae18, 0xe00a,
+	0x0638, 0xcec0, 0xd14c, 0x0003, 0xca9c, 0xe418, 0x0a3e, 0xca9a,
+	0xf7c8, 0xca9c, 0xf7a8, 0xca9e, 0xc001, 0x3c32, 0xcc92, 0xca94,
+	0x0030, 0x0c31, 0x3430, 0x3c31, 0xcc90, 0xc000, 0xe42e, 0xe004,
+	0x1495, 0xae20, 0xcc9e, 0xd030, 0x0000, 0xd034, 0x0000, 0xd033,
+	0x0000, 0xd035, 0x0000, 0xd036, 0x007f, 0xd037, 0x0000, 0xd038,
+	0x0000, 0xd039, 0x0000, 0xd04b, 0x0001, 0xd04c, 0x0000, 0xd046,
+	0x0000, 0xd047, 0x0000, 0xd149, 0x0000, 0xe42e, 0xc001, 0x280c,
+	0xf20a, 0xe41e, 0x024f, 0xc001, 0xe004, 0x0440, 0xce50, 0x280d,
+	0xa806, 0xa108, 0xe012, 0xa806, 0xae06, 0x3c40, 0xe004, 0x010b,
+	0x5840, 0xce52, 0xe41e, 0x0257, 0xc001, 0xd14e, 0x0000, 0xd144,
+	0x0000, 0x2402, 0x4c03, 0xe000, 0x0200, 0x3402, 0x3c03, 0xf3ae,
+	0xd027, 0x0000, 0x280c, 0xe41a, 0x0aa7, 0xc001, 0xd027, 0x0001,
+	0x280d, 0xf25a, 0xca48, 0xa802, 0xf7e8, 0x2402, 0x4c03, 0xce40,
+	0xd121, 0x0000, 0xd122, 0x0040, 0xe0c0, 0x0043, 0xa806, 0xae02,
+	0xa032, 0xce46, 0xe190, 0xe190, 0xe190, 0xe190, 0xca48, 0xa802,
+	0xf7e8, 0xe004, 0x0200, 0x0402, 0x0c03, 0x3402, 0x3c03, 0x1408,
+	0x1c09, 0xf054, 0x2400, 0x4c01, 0x3402, 0x3c03, 0x280c, 0xe418,
+	0x0aeb, 0xc001, 0xe41e, 0x0b30, 0xc001, 0xd14e, 0x0000, 0xd144,
+	0x0000, 0xc000, 0xe42e, 0xe0c1, 0x0059, 0xa103, 0xa200, 0xb636,
+	0xe000, 0x001c, 0xe0c1, 0x0045, 0xe052, 0xe01a, 0xe42e, 0xc001,
+	0xa200, 0x3c0a, 0xe004, 0x0200, 0x3c0d, 0xe0c0, 0x0043, 0xa808,
+	0xf338, 0xe41e, 0x0a9b, 0xc001, 0x3c0c, 0x2402, 0x4c03, 0xe0c1,
+	0x0049, 0x3604, 0x3e05, 0x2604, 0x4e05, 0xe045, 0xf033, 0x0606,
+	0x0e07, 0xe003, 0x0200, 0x280c, 0xb602, 0x3c0c, 0xf1d3, 0xe001,
+	0x0200, 0x3e0d, 0x280c, 0xf188, 0x280a, 0xe408, 0x0ab1, 0xe41e,
+	0x01db, 0xc001, 0xe0c0, 0x005c, 0xe008, 0x4000, 0xe40a, 0x0ab1,
+	0xe0c0, 0x005d, 0xe00a, 0x4000, 0xe0c2, 0x005d, 0xa202, 0xce00,
+	0x3c0a, 0xe40e, 0x0ab1, 0x280d, 0x2a0c, 0xf039, 0xe004, 0x0200,
+	0x3c0d, 0xc000, 0xe42e, 0xc001, 0xe41e, 0x024f, 0xc001, 0x280d,
+	0xe002, 0x0200, 0xe40a, 0x0b2d, 0x280d, 0xa806, 0xf1fa, 0xa108,
+	0xe012, 0xae06, 0x3c40, 0x280d, 0xaf04, 0xae20, 0xe000, 0x01c0,
+	0xce50, 0xe190, 0xca52, 0x5c40, 0x5840, 0x2a0d, 0xa807, 0xae07,
+	0x3e40, 0xe005, 0x010b, 0x5e40, 0xe056, 0x2a0d, 0xaf05, 0xae21,
+	0xe001, 0x0140, 0xce51, 0xe190, 0xce52, 0xe004, 0x01fc, 0x180d,
+	0xf022, 0xf14e, 0xc001, 0x280d, 0xa006, 0xaf04, 0xae20, 0xe000,
+	0x0440, 0xce50, 0x280d, 0xa806, 0xa108, 0xe012, 0xa806, 0xae06,
+	0x3c40, 0xe004, 0x010b, 0x5840, 0xce52, 0xc000, 0xe40e, 0x0257,
+	0xc001, 0xcaaa, 0x2a1a, 0xb616, 0xe0c1, 0x0048, 0x360e, 0x3e0f,
+	0x260e, 0x4e0f, 0xe042, 0xe049, 0x1608, 0x1e09, 0xf035, 0x1406,
+	0x1c07, 0xe0c2, 0x0048, 0xa200, 0xceaa, 0xc000, 0xe42e, 0xe41e,
+	0x0b30, 0xe0c0, 0x0045, 0xaf04, 0xa806, 0xa104, 0xe428, 0xa2fc,
+	0x2a84, 0xa003, 0xb616, 0xe418, 0x0b56, 0xe42e, 0xc001, 0x3c40,
+	0xe0c0, 0x0048, 0x340e, 0x3c0f, 0x240e, 0x4c0f, 0x0840, 0xe049,
+	0x1600, 0x1e01, 0xf033, 0x0406, 0x0c07, 0xe049, 0x1608, 0x1e09,
+	0xf035, 0x1406, 0x1c07, 0xe0c2, 0x0048, 0xc000, 0xe42e, 0xe41e,
+	0x0b30, 0xc001, 0xe0c0, 0x0048, 0x3417, 0x3c18, 0xc000, 0xe42e,
+	0xa200, 0xceaa, 0xc001, 0x2417, 0x4c18, 0xc000, 0xe0c2, 0x0048,
+	0xe42e, 0xe41e, 0x095f, 0xe41e, 0x08b8, 0xf0f8, 0xcaa2, 0xe049,
+	0xa83e, 0xe009, 0x00ff, 0xf03b, 0xaf0f, 0xf04b, 0xe41e, 0x094c,
+	0xf71e, 0xe41e, 0x08b8, 0xf0aa, 0xe004, 0x010b, 0xe008, 0x00ff,
+	0xe41e, 0x089e, 0xe004, 0x010b, 0xf02e, 0xcaa2, 0xe008, 0x001f,
+	0xe41e, 0x08a6, 0xe41e, 0x08aa, 0xe42e, 0xc001, 0x2832, 0xe016,
+	0xc871, 0xa011, 0xf288, 0xaf07, 0xe009, 0x07ff, 0x2831, 0xe008,
+	0x07ff, 0xe046, 0xf16a, 0xf0ee, 0xc001, 0xe161, 0x0601, 0x2901,
+	0xc871, 0xa011, 0xaf07, 0xe009, 0x07ff, 0xe008, 0x07ff, 0xe046,
+	0xf08a, 0xe049, 0xe011, 0xaf15, 0xf0e1, 0xf0d0, 0xa200, 0xf0be,
+	0xc868, 0xa80e, 0xf028, 0xa210, 0x3c35, 0x7835, 0xa203, 0x5a35,
+	0xaf03, 0xe046, 0xc000, 0xe42e, 0xc000, 0x284e, 0x2a4f, 0x3c95,
+	0x3e96, 0xc001, 0x2831, 0x2a32, 0x3c36, 0x3e37, 0xe0c0, 0x0046,
+	0xe005, 0x0000, 0xae11, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112,
+	0x0080, 0xd113, 0x0012, 0xca28, 0xf7f8, 0xca2c, 0xf7fa, 0xc000,
+	0xe42e, 0xc000, 0x2895, 0x2a96, 0x3c4e, 0x3e4f, 0xc001, 0x2836,
+	0x2a37, 0x3c31, 0x3e32, 0xcc90, 0xcc93, 0xa200, 0x3c30, 0x3c33,
+	0xe0c0, 0x0046, 0xe005, 0x0000, 0xae11, 0xe042, 0xce20, 0xd111,
+	0x0000, 0xd112, 0x0080, 0xd113, 0x0013, 0xca28, 0xf7f8, 0xe41e,
+	0x0a1f, 0xe128, 0xc000, 0xe42e, 0xc001, 0x2834, 0xc000, 0xe42e,
+	0xc001, 0x3430, 0x3c31, 0xc000, 0xe42e, 0xc001, 0x2430, 0x4c31,
+	0xc000, 0xe42e, 0xc001, 0x3c32, 0xc000, 0xe42e, 0xc001, 0x2832,
+	0xc000, 0xe42e, 0xc001, 0x3c10, 0xc000, 0xe42e, 0xc001, 0x2810,
+	0xc000, 0xe42e, 0xc001, 0x3c38, 0xc000, 0xe42e, 0xc001, 0x2838,
+	0xc000, 0xe42e, 0xc001, 0xe0c0, 0x0041, 0xe005, 0x0039, 0xae11,
+	0xe042, 0x3420, 0x3c21, 0xe004, 0x04e1, 0xae10, 0x3422, 0x3c23,
+	0xc000, 0xe42e, 0xc001, 0x2420, 0x4c21, 0xc000, 0xe42e, 0x3c63,
+	0xe08e, 0x3c64, 0xe41e, 0x0c5b, 0xe41e, 0x0c63, 0x2864, 0xe09e,
+	0x2863, 0x3c60, 0xe42e, 0x2860, 0xae08, 0xe000, 0x0538, 0xe09e,
+	0xe41e, 0x0883, 0xe42e, 0x2863, 0xae08, 0xe000, 0x0538, 0xe09e,
+	0xe41e, 0x0868, 0xe42e, 0x2860, 0xe408, 0x1b5f, 0xe41e, 0x0c26,
+	0xf1b8, 0xe41e, 0x08de, 0xf068, 0xe41e, 0x09ee, 0xd04c, 0x0000,
+	0xe470, 0xc896, 0xf05a, 0xe41e, 0x0c8e, 0xd04c, 0x0000, 0xe41e,
+	0x08e6, 0xe005, 0x0080, 0xb615, 0xcc6f, 0xd04b, 0x0001, 0xa202,
+	0xe41e, 0x0c2a, 0xe470, 0xd04c, 0x0000, 0xe470, 0xc001, 0xa200,
+	0x3c10, 0xe41e, 0x09ee, 0xc001, 0x2832, 0xcc96, 0x2811, 0xe016,
+	0x3c11, 0xc000, 0xe42e, 0xba0c, 0xf03a, 0xbcfc, 0xe42e, 0xba4c,
+	0xa20c, 0x3c9d, 0x289d, 0xa002, 0x3c9d, 0xa140, 0xf0d2, 0xba40,
+	0xf7aa, 0x589d, 0xa102, 0x34ab, 0x3cac, 0x289d, 0xe41e, 0x0cd8,
+	0x00ab, 0x0cac, 0xe42e, 0xe16b, 0xe42e, 0xba0c, 0xf03a, 0xbe7e,
+	0xe42e, 0xba4c, 0xa20c, 0x3c9d, 0x289d, 0xa002, 0x3c9d, 0xa140,
+	0xf162, 0xba40, 0xf7aa, 0x589d, 0xa102, 0x34ab, 0x3cac, 0x289d,
+	0xe41e, 0x0cd8, 0x00ab, 0x0cac, 0x3cac, 0x8cac, 0x0000, 0xa002,
+	0xaf02, 0xe012, 0xe42c, 0xe012, 0xe16a, 0xe42e, 0xe16b, 0xe42e,
+	0xa120, 0xf050, 0xa020, 0x3c9e, 0x749e, 0xe42e, 0x3c9e, 0xba5e,
+	0x589e, 0x769e, 0xe056, 0xe42e, 0xba40, 0xe42a, 0xc868, 0xa80e,
+	0x3c00, 0xe016, 0xe428, 0x7400, 0xe016, 0xe42e, 0x2a38, 0xa103,
+	0x282f, 0xe425, 0xf02b, 0x2830, 0xb7f4, 0xa002, 0x3c5e, 0xa104,
+	0xe424, 0xf04a, 0xa25a, 0x3c5f, 0xe42e, 0xbc0e, 0x3c00, 0xe42d,
+	0x2822, 0xf02a, 0xbc0e, 0x3c01, 0xe42d, 0x2801, 0xae06, 0x4c00,
+	0x3c5f, 0xe161, 0x0728, 0xe164, 0x0720, 0x8848, 0x0022, 0xe41e,
+	0x0d1f, 0xe42d, 0x2838, 0xa104, 0xe428, 0x2849, 0xe161, 0x0788,
+	0xe164, 0x0724, 0x8849, 0x0022, 0xe41e, 0x0d1f, 0xe42e, 0xe082,
+	0xa040, 0xe094, 0xa040, 0xe096, 0xe004, 0x00ff, 0x3c03, 0xa200,
+	0x3c05, 0x3c06, 0x3c07, 0x3c08, 0x3c09, 0xe184, 0x0d6b, 0xba40,
+	0xf0ba, 0xe0c6, 0x0080, 0x4403, 0xae10, 0xe0c7, 0x0080, 0x4603,
+	0xe056, 0x3d11, 0xf0ce, 0xa202, 0x5800, 0xae10, 0x3d11, 0x2206,
+	0x4e07, 0xa202, 0x5805, 0xe056, 0x3406, 0x3c07, 0x2822, 0xf22a,
+	0xba40, 0xf14a, 0xe0c6, 0x0080, 0x4403, 0xae10, 0xe0c7, 0x0080,
+	0x4603, 0xe056, 0x3d12, 0xe0c6, 0x0080, 0x4403, 0xae10, 0xe0c7,
+	0x0080, 0x4603, 0xe056, 0x3d13, 0xf0de, 0xa202, 0x5801, 0xae10,
+	0x3d12, 0x3d13, 0x2208, 0x4e09, 0xa202, 0x5805, 0xe056, 0x3408,
+	0x3c09, 0x2805, 0xa002, 0x3c05, 0x2006, 0x4c07, 0xe014, 0x3514,
+	0x3d14, 0x2208, 0x4e09, 0xe015, 0x3714, 0x3f14, 0xe42e, 0xe0c4,
+	0x3fff, 0xe40d, 0x0e6c, 0x3c52, 0xf048, 0xa200, 0xa2fe, 0x3ca1,
+	0x2c52, 0xe01a, 0x4451, 0xe408, 0x0e6c, 0xbc12, 0xe40d, 0x0e6c,
+	0xa10a, 0xb4a8, 0xa104, 0xe400, 0x0e6c, 0xb7b4, 0xa006, 0x3c38,
+	0x60a1, 0x3ca1, 0xbdfe, 0xe40d, 0x0e6c, 0x2a51, 0xf09b, 0xe049,
+	0x1829, 0xf06a, 0x3e29, 0xe41e, 0x1b3f, 0xe40a, 0x0e6c, 0x7413,
+	0x3c39, 0xa200, 0x3c3f, 0x3c42, 0x281b, 0xf068, 0xba40, 0x3c3f,
+	0xf03a, 0xba40, 0x3c42, 0x2851, 0xf2fa, 0x2c1e, 0x5c3f, 0x3c44,
+	0xa200, 0x3c40, 0x283a, 0xf07a, 0xe41e, 0x0e6f, 0x3c40, 0xf168,
+	0x283e, 0x3ca4, 0x283f, 0x3c3a, 0x284e, 0xe01a, 0x3c3b, 0x2839,
+	0x3c3c, 0x2842, 0x3c3d, 0xa2fc, 0x3c3e, 0x284e, 0xf098, 0x2850,
+	0x1c39, 0xf06a, 0xa202, 0x3cbe, 0xf03e, 0xa200, 0x3c3a, 0x2c52,
+	0xf038, 0x2840, 0xf018, 0x283f, 0xe016, 0x441c, 0x3c43, 0x283f,
+	0x0842, 0xb674, 0x3c41, 0x284f, 0xf06a, 0xe41e, 0x0c9b, 0xe40d,
+	0x0e6c, 0x3c45, 0xe41e, 0x18b2, 0x2835, 0xf07a, 0xe41e, 0x0c9b,
+	0xe40d, 0x0e6c, 0xe408, 0x0e6c, 0x2838, 0xa104, 0xf038, 0xba40,
+	0x3c46, 0x282c, 0x3c48, 0x282e, 0x3c49, 0x2838, 0xf0ea, 0xba40,
+	0xf0ca, 0xbc3e, 0x3c48, 0xe40d, 0x0e6c, 0x2838, 0xa104, 0xf058,
+	0xbc3e, 0x3c49, 0xe40d, 0x0e6c, 0x2851, 0xf0aa, 0x28d6, 0x444f,
+	0xf03a, 0xe41e, 0x1c57, 0xe41e, 0x1c13, 0xe41e, 0x0e8b, 0x2838,
+	0xe016, 0xe41a, 0x0e92, 0xe40a, 0x0e6c, 0xe41e, 0x0cee, 0xe40d,
+	0x0e6c, 0x2851, 0xf06a, 0xe41e, 0x177b, 0xe40a, 0x0e6c, 0xf1fe,
+	0x284e, 0xf1da, 0x284f, 0xf04a, 0xba40, 0xba40, 0xf18e, 0xba40,
+	0xf16a, 0xbc0c, 0xe40d, 0x0e6c, 0xf12a, 0xa106, 0xf08a, 0xa104,
+	0xf79a, 0xe41e, 0x0c9b, 0xe40d, 0x0e6c, 0xf74e, 0xe41e, 0x0c9b,
+	0xe40d, 0x0e6c, 0xbc40, 0xe40d, 0x0e6c, 0xf6ce, 0x2838, 0xe01a,
+	0x442d, 0xf03a, 0xbc04, 0xf29d, 0x3c47, 0xe0c6, 0x0033, 0xf25d,
+	0x0831, 0xa400, 0xa566, 0x3c4a, 0xa200, 0x3c4b, 0x3c4c, 0x3c4d,
+	0x2833, 0xf10a, 0xbc04, 0xf19d, 0x3c4b, 0xa102, 0xf0ba, 0xbe0c,
+	0xf14d, 0xae02, 0xa83e, 0x3c4c, 0xbe0c, 0xf0fd, 0xae02, 0xa83e,
+	0x3c4d, 0x282b, 0xf01a, 0x2a43, 0x2c52, 0xe419, 0x0e84, 0x3c52,
+	0x1c44, 0xf032, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0x284f,
+	0xe016, 0xe42a, 0x283f, 0xe42a, 0x283a, 0xe42a, 0x283d, 0x1842,
+	0xe42a, 0x284e, 0xf048, 0x283b, 0xe016, 0xe42e, 0x283b, 0xe42a,
+	0x283c, 0x1839, 0xe016, 0xe42e, 0xe049, 0xc70f, 0x7e57, 0xaf21,
+	0xae02, 0xe046, 0xe42e, 0xd1f3, 0x0000, 0xe162, 0x0370, 0x2912,
+	0xcfe4, 0xe42e, 0xe161, 0x0370, 0x2838, 0xa102, 0xf03a, 0xe161,
+	0x0390, 0x2848, 0x3c04, 0xe162, 0x02b0, 0xe41e, 0x0eed, 0xe42a,
+	0xd1f3, 0x0000, 0xe162, 0x02b0, 0x8848, 0x0022, 0xe184, 0x0ea9,
+	0x2912, 0xcfe4, 0x2838, 0xa104, 0xe428, 0x2849, 0x3c04, 0xe161,
+	0x03b0, 0xe162, 0x02d0, 0xe41e, 0x0eed, 0xe42a, 0xd1f3, 0x0020,
+	0xe162, 0x02d0, 0x8849, 0x0022, 0xe184, 0x0ebf, 0x2912, 0xcfe4,
+	0xe41e, 0x0fec, 0xe162, 0x02d0, 0x2902, 0xe41e, 0x0faa, 0xe41e,
+	0x0fce, 0x3470, 0x3c71, 0x2902, 0xae02, 0xe000, 0x0260, 0xe09e,
+	0x2117, 0x4d17, 0x2317, 0x4f17, 0x1072, 0x1c73, 0x1272, 0x1e73,
+	0xe010, 0xe011, 0xe046, 0xb624, 0xb608, 0x3c7a, 0x2902, 0xe41e,
+	0x0fa3, 0xa102, 0xb628, 0x3c78, 0x2902, 0xaf02, 0xe000, 0x02a0,
+	0xe09e, 0x2907, 0x3c79, 0xa202, 0xe42e, 0xe082, 0xe098, 0xba40,
+	0xf098, 0x8804, 0x0022, 0xe184, 0x0ef6, 0x2911, 0x3d12, 0xa202,
+	0xe42e, 0x286d, 0xe082, 0x3c08, 0x2014, 0x4c15, 0x583f, 0x3400,
+	0x3c01, 0x2c39, 0x583f, 0x083f, 0x3402, 0x3c03, 0x2804, 0x3c05,
+	0xe163, 0x0600, 0xa200, 0xc71f, 0x3d13, 0xbc0a, 0xe40d, 0x0f63,
+	0xf0aa, 0xa102, 0xf17a, 0xa102, 0xf26a, 0xa104, 0xf1da, 0xa102,
+	0xf1ba, 0xf38e, 0xe41e, 0x0c9b, 0xe40d, 0x0f63, 0xa002, 0x1002,
+	0x1c03, 0xe012, 0xf032, 0x0000, 0x0c01, 0x3402, 0x3c03, 0xa203,
+	0xf14e, 0xe41e, 0x0c9b, 0xe40d, 0x0f63, 0xa002, 0x0002, 0x0c03,
+	0x1000, 0x1c01, 0xf70e, 0xe41e, 0x0c9b, 0xe40d, 0x0f63, 0x283f,
+	0xa2fd, 0xf03e, 0xbc40, 0xa2ff, 0x3c0f, 0xe41e, 0x0f72, 0xf082,
+	0xa203, 0x283f, 0xf03a, 0x2a0f, 0xa803, 0x2904, 0xe046, 0x3d12,
+	0xe41e, 0x0f8e, 0x2805, 0xa102, 0x3c05, 0xa004, 0xe42a, 0xe40e,
+	0x0f0d, 0x2808, 0xa102, 0xe092, 0xe163, 0x0600, 0x2805, 0xf0a4,
+	0x2913, 0x8111, 0xf7e8, 0x2901, 0x3d12, 0x2805, 0xa102, 0x3c05,
+	0xf76e, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0x2884, 0xe424,
+	0xe0c2, 0x020b, 0xe0c2, 0x0214, 0x2884, 0xe41e, 0x0fce, 0x346e,
+	0x3c6f, 0xe42e, 0x3c06, 0x3e07, 0xe163, 0x0330, 0x2819, 0x2ad6,
+	0xb5f6, 0xe424, 0xae02, 0xa002, 0xcc44, 0xe184, 0x0f8b, 0x2d13,
+	0x2b0b, 0x1c06, 0x1a07, 0xf078, 0xf069, 0xe086, 0xe002, 0x0330,
+	0xaf02, 0xe42e, 0x8113, 0x8113, 0xa2fe, 0xe42e, 0x3c09, 0x2808,
+	0xe092, 0x286d, 0xa102, 0xcc44, 0xe184, 0x0f99, 0x2901, 0x1809,
+	0xf03a, 0x8111, 0xe42e, 0xe082, 0x1808, 0xe000, 0x0600, 0xe096,
+	0xa202, 0x3d03, 0xe42e, 0xaf02, 0xae04, 0xe000, 0x0201, 0xe09e,
+	0x2907, 0xe42e, 0xaf02, 0xae04, 0xe000, 0x0203, 0xe09e, 0x2907,
+	0xe42e, 0x3c0a, 0xe0c0, 0x0042, 0xe000, 0x0180, 0x080a, 0xa207,
+	0xe41e, 0x0fc5, 0xe0c0, 0x0041, 0xe005, 0x006c, 0xae0f, 0x0a0a,
+	0xe042, 0xa205, 0xe41e, 0x0fc5, 0xe42e, 0xce20, 0xd111, 0x0600,
+	0xd112, 0x0020, 0xce27, 0xca28, 0xf7f8, 0xe42e, 0x3c0a, 0xaf02,
+	0xae06, 0xe0c1, 0x0041, 0xe042, 0xe005, 0x006c, 0xae0f, 0xe042,
+	0xce20, 0xd111, 0x0600, 0xd112, 0x0004, 0xd113, 0x0003, 0xca28,
+	0xf7f8, 0xe004, 0x0600, 0xe09e, 0x2117, 0x4d17, 0x2a0a, 0xa803,
+	0xe42b, 0x2117, 0x4d17, 0xe42e, 0xe161, 0x0600, 0xa23e, 0xc71f,
+	0x3d11, 0x2848, 0xe000, 0x02b0, 0xe094, 0x2a48, 0x8848, 0x0022,
+	0xe184, 0x0fff, 0x290a, 0xe000, 0x0600, 0xe092, 0x3f01, 0xa103,
+	0xd1f9, 0x0000, 0xe162, 0x0600, 0xd022, 0x001f, 0xe184, 0x1009,
+	0x2912, 0xcff0, 0xe42e, 0xe41e, 0x0fec, 0xe42e, 0xd1f3, 0x0000,
+	0xe167, 0x02b0, 0xd022, 0x003f, 0xe184, 0x1017, 0x2917, 0xcfe4,
+	0xd1f9, 0x0000, 0xe167, 0x0600, 0xd022, 0x001f, 0xe184, 0x1021,
+	0x2917, 0xcff0, 0xe42e, 0xba4e, 0x3c11, 0xa200, 0x3c24, 0xd022,
+	0x0007, 0xe184, 0x1030, 0xba41, 0x5a24, 0xe056, 0x2a24, 0xa003,
+	0x3e24, 0x3c24, 0xa208, 0x3cf0, 0x2824, 0xaf0c, 0xe408, 0x113d,
+	0xa224, 0x3cf0, 0xe41e, 0x1396, 0xe40a, 0x1140, 0xa226, 0x3cf0,
+	0xba4e, 0x3c1f, 0xa112, 0xe404, 0x113d, 0xa154, 0xe400, 0x113d,
+	0xbc3e, 0x3c10, 0xa202, 0x3c22, 0xa200, 0x3c67, 0x2811, 0xa1c8,
+	0xf06a, 0xa124, 0xf04a, 0xa114, 0xf02a, 0xf33e, 0xbc06, 0x3c22,
+	0xa20a, 0x3cf0, 0xbc08, 0xe408, 0x113d, 0xa20c, 0x3cf0, 0xbc08,
+	0xe408, 0x113d, 0xba40, 0xba40, 0x3c67, 0xf23a, 0xa201, 0x3e69,
+	0x3e6b, 0xe160, 0x0000, 0xba40, 0xf11a, 0x2a69, 0xae03, 0xe056,
+	0x3c69, 0xe080, 0xe41e, 0x1341, 0x2a6b, 0xae03, 0xe056, 0x3c6b,
+	0xe080, 0xa201, 0xe41e, 0x1374, 0xf07e, 0x2a69, 0xae03, 0x3e69,
+	0x2a6b, 0xae03, 0x3e6b, 0xe080, 0xa002, 0xe090, 0xa110, 0xf648,
+	0xa20e, 0x3cf0, 0xbc18, 0xe40d, 0x113d, 0xa008, 0x3c13, 0xa202,
+	0x5813, 0x3414, 0x3c15, 0xa210, 0x3cf0, 0xbc04, 0x3c16, 0xe40d,
+	0x113d, 0xa102, 0xf034, 0xf0aa, 0xf33e, 0xa212, 0x3cf0, 0xbc18,
+	0xe40d, 0x113d, 0xa008, 0x3c17, 0xf2be, 0xba40, 0x3c18, 0xe41e,
+	0x0cb5, 0xe160, 0x0907, 0xe161, 0x0908, 0x3500, 0x3d01, 0xe41e,
+	0x0cb5, 0xe162, 0x0909, 0xe163, 0x090a, 0x3502, 0x3d03, 0xa214,
+	0x3cf0, 0xbdfe, 0xe40d, 0x113d, 0xe164, 0x090b, 0x3d04, 0xf10a,
+	0xa102, 0xcc44, 0xe162, 0x09e0, 0xe184, 0x10c9, 0xe41e, 0x0cb5,
+	0x3512, 0x3d12, 0xa216, 0x3cf0, 0xe41e, 0x126f, 0xf01e, 0xe40d,
+	0x113d, 0xa218, 0x3cf0, 0xbc20, 0xe40d, 0x113d, 0x3c19, 0xba40,
+	0x3c1a, 0xa21a, 0x3cf0, 0xbdfe, 0xe40d, 0x113d, 0xa002, 0x3c57,
+	0xa21c, 0x3cf0, 0xbdfe, 0xe40d, 0x113d, 0xa002, 0x3c58, 0x8457,
+	0x8258, 0xe018, 0x3c1e, 0xa222, 0x3cf0, 0x2c57, 0xe002, 0x0080,
+	0xe400, 0x113d, 0x2c58, 0xe002, 0x0080, 0xe400, 0x113d, 0x2c1e,
+	0xe002, 0x4000, 0xe400, 0x113d, 0xa200, 0x3c1c, 0xba40, 0x3c1b,
+	0xf098, 0xba40, 0x3c1c, 0x2858, 0xae02, 0x3c58, 0x2c1e, 0xae02,
+	0x3c1e, 0xe41e, 0x11ed, 0xa21e, 0x3cf0, 0x2a1b, 0xba40, 0xb636,
+	0x3c1d, 0xa220, 0x3cf0, 0xba40, 0xe161, 0x05e4, 0xc703, 0x3d11,
+	0xf16a, 0xe161, 0x05e4, 0xe41e, 0x0c9b, 0x3d11, 0xe41e, 0x0c9b,
+	0x3d11, 0xe41e, 0x0c9b, 0x2a1b, 0xf029, 0xae02, 0x3d11, 0xe41e,
+	0x0c9b, 0x2a1b, 0xf029, 0xae02, 0x3d11, 0xf10d, 0xa200, 0x3c90,
+	0x3c91, 0x2820, 0x3cea, 0x3ceb, 0xe41e, 0x14b5, 0xba40, 0xe016,
+	0xe41a, 0x127f, 0xf03a, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e,
+	0xa2fe, 0xe42e, 0xe41e, 0x0c9b, 0x3c29, 0xbc3e, 0xe40d, 0x11e3,
+	0x1810, 0xf11a, 0x0810, 0x3c10, 0xe41e, 0x1b12, 0x3c65, 0xa205,
+	0xae23, 0xcc9f, 0xa202, 0xe41e, 0x0c4f, 0xa203, 0x3e9b, 0x2865,
+	0xe40a, 0x11e3, 0xba40, 0x3c2d, 0xba40, 0x3c2a, 0xbc0e, 0xe40d,
+	0x11e3, 0x3c2b, 0xf03a, 0xe40d, 0x11e3, 0x282d, 0x2a2b, 0xe01b,
+	0xe052, 0xe408, 0x11e3, 0x2811, 0xa184, 0xf078, 0x282d, 0xf0aa,
+	0xe004, 0x0064, 0x3c11, 0xf06e, 0x282b, 0xf04a, 0xe004, 0x0042,
+	0x3c11, 0xbc3e, 0xe40d, 0x11e3, 0x3c2c, 0xbc3e, 0x3c2e, 0xe40d,
+	0x11e3, 0xba40, 0x3c2f, 0xba42, 0x3c30, 0xbe34, 0xe40d, 0x11e3,
+	0xa034, 0x3c31, 0xe404, 0x11e3, 0xa168, 0xe402, 0x11e3, 0xbe34,
+	0xe40d, 0x11e3, 0xa034, 0xe404, 0x11e3, 0xa168, 0xe402, 0x11e3,
+	0xbe18, 0xe40d, 0x11e3, 0x3c32, 0x3c36, 0xba40, 0x3c33, 0xba40,
+	0x3c34, 0xba40, 0x3c35, 0xa200, 0x3c37, 0x3c68, 0x2811, 0xa184,
+	0xf37a, 0x2829, 0x3c02, 0xe41e, 0x1bdd, 0xe41e, 0x0bb4, 0xf30a,
+	0xba40, 0x3c37, 0xba40, 0x3c68, 0xf28a, 0xa201, 0x3e6a, 0x3e6c,
+	0xe160, 0x0000, 0xe080, 0xa10c, 0x1837, 0x1837, 0xf132, 0xba40,
+	0xf11a, 0x2a6a, 0xae03, 0xe056, 0x3c6a, 0xe080, 0xe41e, 0x1341,
+	0x2a6c, 0xae03, 0xe056, 0x3c6c, 0xe080, 0xa203, 0xe41e, 0x1374,
+	0xf07e, 0x2a6a, 0xae03, 0x3e6a, 0x2a6c, 0xae03, 0x3e6c, 0xe080,
+	0xa002, 0xe090, 0xa110, 0xf5f8, 0xbe18, 0xf06d, 0x3c36, 0xe41e,
+	0x0ce4, 0xa202, 0xe42e, 0xe0c1, 0x0059, 0xa107, 0xf049, 0x28ae,
+	0xa902, 0x3cae, 0xe16a, 0xa200, 0xe42e, 0xa214, 0x2e1e, 0xe003,
+	0x0063, 0xf2f7, 0xa216, 0x2e1e, 0xe003, 0x018c, 0xf2a7, 0xa22a,
+	0x2e1e, 0xe003, 0x0318, 0xf257, 0xa22c, 0x2e1e, 0xe003, 0x0654,
+	0xf207, 0xa23e, 0x2e1e, 0xe003, 0x0e10, 0xf1b7, 0xa240, 0x2e1e,
+	0xe003, 0x1400, 0xf167, 0xa250, 0x2e1e, 0xe003, 0x2000, 0xf117,
+	0xa254, 0x2e1e, 0xe003, 0x2200, 0xf0c7, 0xa264, 0x2e1e, 0xe003,
+	0x5640, 0xf077, 0xa266, 0x2e1e, 0xe003, 0x9000, 0xf027, 0xa268,
+	0x2a1f, 0xe045, 0xf023, 0x3c1f, 0x2a1f, 0xa115, 0xe004, 0x0129,
+	0xf2d7, 0xa103, 0xe004, 0x02a3, 0xf297, 0xa113, 0xe004, 0x06f6,
+	0xf257, 0xa103, 0xe004, 0x0dec, 0xf217, 0xa113, 0xe004, 0x17bb,
+	0xf1d7, 0xa103, 0xe004, 0x34bc, 0xf197, 0xa103, 0xe004, 0x3c00,
+	0xf157, 0xa113, 0xe004, 0x6000, 0xf117, 0xa103, 0xe004, 0x6600,
+	0xf0d7, 0xa111, 0xe004, 0x1437, 0xae08, 0xf087, 0xa103, 0xe004,
+	0x21c0, 0xae08, 0xf037, 0xe004, 0x17bb, 0xae12, 0x3409, 0x3c0a,
+	0x841e, 0xe182, 0x0180, 0xe019, 0x2009, 0x4c0a, 0xc407, 0xd022,
+	0x000f, 0xe184, 0x1265, 0xe046, 0xf034, 0x8117, 0xe190, 0xe08e,
+	0xae02, 0x2a19, 0xae03, 0xe062, 0xa520, 0x3c20, 0xe42e, 0xe0c0,
+	0x0041, 0xe005, 0x0026, 0xae11, 0xe042, 0xce20, 0xd111, 0x09e0,
+	0xd112, 0x0200, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0xa200,
+	0x3c00, 0x3c01, 0x3c02, 0x3c03, 0x3c04, 0x3c05, 0x3c06, 0x3c07,
+	0x3c08, 0x3c09, 0x3c0a, 0xba40, 0xa2ff, 0x3e25, 0x3e26, 0xf16a,
+	0xba4e, 0xa201, 0x3e25, 0x3c26, 0xe002, 0x00ff, 0xf0f8, 0xa202,
+	0x3c07, 0xba5e, 0xba5f, 0x3c25, 0x3e26, 0xe016, 0xe017, 0xe056,
+	0xf028, 0xf04e, 0xa200, 0x3c26, 0x3c25, 0xba40, 0xf02a, 0xba40,
+	0xba40, 0x3c0a, 0xf0ca, 0xba44, 0x3c09, 0xba40, 0x3c08, 0xba40,
+	0x3c06, 0xf05a, 0xba4e, 0x3c05, 0xba4e, 0xba4e, 0xba40, 0x3c04,
+	0xf05a, 0xbc0a, 0x3c03, 0xbc0a, 0x3c02, 0xba40, 0x3c01, 0xf0ba,
+	0xba7e, 0xe161, 0x05c7, 0x3511, 0x3d11, 0xba7e, 0x3511, 0x3d11,
+	0xba40, 0x3c00, 0xba40, 0x3c90, 0xe016, 0xe161, 0x05bd, 0xe41a,
+	0x1325, 0xe40a, 0x1322, 0xba40, 0x3c91, 0xe016, 0xe161, 0x05c2,
+	0xe41a, 0x1325, 0xe40a, 0x1322, 0x2890, 0x4c91, 0xf02a, 0xba40,
+	0xba40, 0x3c23, 0xba40, 0xf08a, 0xba40, 0xbc20, 0xbc20, 0xbc20,
+	0xbc20, 0xbc20, 0xbc20, 0x28eb, 0xa120, 0xf0a0, 0x2819, 0x18eb,
+	0xf070, 0x28b3, 0xf09a, 0x287f, 0xa104, 0x18eb, 0xf052, 0x2ab3,
+	0xf029, 0x2a20, 0x3eeb, 0xa202, 0xae3e, 0x2a0a, 0xae3d, 0xe056,
+	0x2a09, 0xae37, 0xe056, 0x2a08, 0xae35, 0xe056, 0x2a07, 0xae33,
+	0xe056, 0x2a06, 0xae31, 0xe056, 0x2a05, 0xae21, 0xe056, 0x2a04,
+	0xae11, 0xe056, 0x2a03, 0xae0b, 0xe056, 0x2a02, 0xae05, 0xe056,
+	0x2a01, 0xae03, 0xe056, 0x2a00, 0xe056, 0xe41e, 0x14b5, 0xe16a,
+	0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0xe41e, 0x0c9b, 0xcc44,
+	0x3c61, 0xa002, 0x3d11, 0xba46, 0xba46, 0xe184, 0x1333, 0xe41e,
+	0x0c9b, 0xe41e, 0x0c9b, 0xba40, 0xba48, 0xa002, 0x3d11, 0xba48,
+	0xa002, 0x3d11, 0xba48, 0xa002, 0x3d11, 0xba48, 0x3d11, 0xa202,
+	0xe42e, 0xd022, 0x000f, 0xa10c, 0xf034, 0xd022, 0x003f, 0xe161,
+	0x0600, 0xa210, 0x3c06, 0x3c07, 0xa200, 0x3c08, 0x3c09, 0xe09c,
+	0xe09e, 0xe184, 0x1371, 0x2807, 0xf10a, 0xe41e, 0x0cb5, 0xe42d,
+	0x0806, 0xe000, 0x0100, 0xe008, 0x00ff, 0x3c07, 0x4c09, 0xe01a,
+	0xe016, 0xe09e, 0xa202, 0x3c09, 0x2807, 0xf028, 0x2806, 0x3c06,
+	0xe08d, 0xa003, 0xe09d, 0xa803, 0xf059, 0xe085, 0xae11, 0xe056,
+	0x3d11, 0xe094, 0xe08e, 0xe42e, 0x3e08, 0x3c06, 0xa211, 0x3e07,
+	0xa10c, 0xf064, 0xb690, 0xa00c, 0x3c06, 0xa240, 0x3c07, 0x2806,
+	0x2a08, 0xf02b, 0xa01c, 0xae08, 0x3c06, 0xe0c0, 0x0041, 0xe005,
+	0x0034, 0xae11, 0xe042, 0x0806, 0xce20, 0xd111, 0x0600, 0x2807,
+	0xce24, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0x2811, 0xa184,
+	0xf0da, 0xa116, 0xf0ba, 0xa12e, 0xf09a, 0xa138, 0xf07a, 0x2824,
+	0xe008, 0x0023, 0xf038, 0xa200, 0xe42e, 0xa202, 0xe42e, 0xa202,
+	0x3c51, 0xe41e, 0x08b8, 0xe408, 0x141c, 0xe41e, 0x0b81, 0xf2ea,
+	0xa102, 0xe40a, 0x143b, 0xa108, 0xe404, 0x13dd, 0xe40a, 0x143b,
+	0xa102, 0xe40a, 0x1402, 0xa102, 0xe40a, 0x13ed, 0xa102, 0xe40a,
+	0x13f8, 0xa102, 0xe40a, 0x140c, 0xa102, 0xe40a, 0x1419, 0xa102,
+	0xe40a, 0x1419, 0xa102, 0xe40a, 0x1423, 0xa106, 0xe40a, 0x13e0,
+	0xa10a, 0xe40a, 0x1438, 0xa002, 0xa10e, 0xf082, 0x2851, 0xe40a,
+	0x144d, 0xe41e, 0x0985, 0xe40e, 0x1433, 0xe41e, 0x094c, 0xf4ae,
+	0x2851, 0xe40a, 0x144d, 0xe41e, 0x14a6, 0xe41e, 0x0985, 0xa202,
+	0x3cd6, 0xe41e, 0x1af7, 0xe40e, 0x1433, 0x2851, 0xe40a, 0x144d,
+	0xe41e, 0x14a6, 0xe41e, 0x0985, 0xe41e, 0x1af7, 0xe40e, 0x1433,
+	0x2851, 0xe40a, 0x144d, 0xe41e, 0x14a6, 0xe41e, 0x0985, 0xe41e,
+	0x1b28, 0xf32e, 0x2851, 0xe40a, 0x144d, 0xe41e, 0x14a6, 0xe41e,
+	0x0985, 0xe41e, 0x14ba, 0xf28e, 0x2851, 0xe40a, 0x144d, 0xe41e,
+	0x14ad, 0xe41e, 0x14a6, 0xe41e, 0x0985, 0xba44, 0xe41e, 0x0ce4,
+	0xf1be, 0xe41e, 0x08b8, 0xf16a, 0xe41e, 0x01db, 0x2851, 0xe408,
+	0x1456, 0xe40e, 0x144d, 0xe41e, 0x0985, 0xba0e, 0xe002, 0x00ff,
+	0xf058, 0xba4e, 0xe41e, 0x0ba5, 0xf798, 0xe41e, 0x0ce4, 0xe40e,
+	0x13a9, 0xe41e, 0x094c, 0x2851, 0xe40a, 0x144d, 0xe40e, 0x13a9,
+	0xa202, 0xe41e, 0x26fc, 0xe41e, 0x14a6, 0xe41e, 0x0985, 0xe41e,
+	0x26d7, 0xe41e, 0x0d77, 0xf048, 0xe41e, 0x26fc, 0xa200, 0xe40a,
+	0x13a9, 0x284e, 0x3c92, 0x284f, 0x3c93, 0xa200, 0x3c51, 0x28d6,
+	0xf048, 0xe41e, 0x1482, 0xf078, 0xa202, 0xe42e, 0xa200, 0xe42e,
+	0xa2fe, 0xe42e, 0xe41e, 0x146b, 0xe41e, 0x05ab, 0x28d6, 0xf098,
+	0xa202, 0xe41e, 0x26fc, 0xe41e, 0x05ab, 0xa200, 0xe41e, 0x26fc,
+	0xe41e, 0x1a5c, 0xf6ae, 0xe165, 0x05e8, 0x2811, 0x3d15, 0x2857,
+	0x3d15, 0x2858, 0x3d15, 0x28eb, 0x3d15, 0x281b, 0x3d15, 0x2824,
+	0x3d15, 0x281f, 0x3d15, 0x2813, 0x3d15, 0x2816, 0x3d15, 0x2819,
+	0x3d15, 0xe42e, 0xe165, 0x05e8, 0x2811, 0x1915, 0xf1d8, 0x2857,
+	0x1915, 0xf1a8, 0x2858, 0x1915, 0xf178, 0x28eb, 0x1915, 0xf148,
+	0x281b, 0x1915, 0xf118, 0x2824, 0x1915, 0xe428, 0x281f, 0x1915,
+	0xe428, 0x2813, 0x1915, 0xe428, 0x2816, 0x1915, 0xe428, 0x2819,
+	0x1915, 0xe428, 0xe42e, 0xa202, 0x3cbd, 0xe42e, 0x28ad, 0xe428,
+	0xe41e, 0x0646, 0xa202, 0x3cad, 0xe42e, 0xa200, 0x3cad, 0xe42e,
+	0xc009, 0x2039, 0x4c3a, 0xc000, 0xe42e, 0xc009, 0x3439, 0x3c3a,
+	0xc000, 0xe42e, 0xa200, 0xba4f, 0xe042, 0xe003, 0x00ff, 0xf7cb,
+	0xe41e, 0x176b, 0xa200, 0xba4f, 0xe042, 0xe003, 0x00ff, 0xf7cb,
+	0xe41e, 0x1773, 0xf04a, 0xe41e, 0x14d4, 0xe42a, 0xe41e, 0x0ba5,
+	0xf6a8, 0xe41e, 0x0ce4, 0xe42e, 0xe41e, 0x176f, 0xf13a, 0xa102,
+	0xf14a, 0xa104, 0xf15a, 0xa102, 0xf16a, 0xa102, 0xf17a, 0xa150,
+	0xf18a, 0xe41e, 0x1777, 0xf04a, 0xba4f, 0xa102, 0xf7e8, 0xa202,
+	0xe42e, 0xe41e, 0x1503, 0xf10e, 0xe41e, 0x1532, 0xf0de, 0xe41e,
+	0x1580, 0xf0ae, 0xe41e, 0x1591, 0xf07e, 0xe41e, 0x15db, 0xf04e,
+	0xe41e, 0x15df, 0xf01e, 0xe42a, 0xc868, 0xa80e, 0xe016, 0xe428,
+	0xe41e, 0x0ce4, 0xe42e, 0xbc3e, 0xf1fd, 0x1810, 0xf11a, 0x0810,
+	0xf084, 0xa13e, 0xf060, 0xa03e, 0x3c10, 0xe41e, 0x1b12, 0x3c65,
+	0xa200, 0xe41e, 0x0c4f, 0xa201, 0x3e9b, 0x2865, 0xe42a, 0x2890,
+	0xe161, 0x05bd, 0xe418, 0x1526, 0x2891, 0xe161, 0x05c2, 0xe418,
+	0x1526, 0xa202, 0xe42e, 0xa200, 0xe16a, 0xe42e, 0x2911, 0xa102,
+	0xcc44, 0xe184, 0x1530, 0x2901, 0xe41e, 0x0cd8, 0x2901, 0xe41e,
+	0x0cd8, 0xe42e, 0x2890, 0xe161, 0x05bf, 0xf038, 0xe161, 0x05c4,
+	0x4c91, 0xf11a, 0x2911, 0xe41e, 0x0cd8, 0xc009, 0x343f, 0x3c40,
+	0xc000, 0x2911, 0xe41e, 0x0cd8, 0xc009, 0x3441, 0x3c42, 0xc000,
+	0x2911, 0xf02e, 0xa230, 0x3c02, 0x2823, 0xe016, 0xe428, 0xba46,
+	0x3ca3, 0xa112, 0xb604, 0xe42a, 0xa012, 0xe049, 0xa200, 0xa107,
+	0xb426, 0xa105, 0xb426, 0xa105, 0xb5f6, 0xcc44, 0xe184, 0x157d,
+	0xba40, 0xf028, 0xf1be, 0xba42, 0xba40, 0xba48, 0xba40, 0x3c03,
+	0xba40, 0xba40, 0xba4e, 0x2803, 0xf05a, 0xba4a, 0xba4a, 0xba48,
+	0xf0ae, 0xba40, 0xf08a, 0xba4a, 0xba40, 0xf05a, 0xba4a, 0xba40,
+	0xf02a, 0xba48, 0x2802, 0xe41e, 0x0cd8, 0xe190, 0xa202, 0xe42e,
+	0xe41e, 0x1777, 0xf0da, 0xa102, 0xcc44, 0xe004, 0x00ff, 0xe184,
+	0x158a, 0xba4f, 0xe052, 0xe002, 0x00ff, 0xe016, 0xe42a, 0xa202,
+	0xe42e, 0xa202, 0xba4f, 0xe003, 0x00ff, 0xf039, 0xba4f, 0xa204,
+	0xba1f, 0xe003, 0x0031, 0xf049, 0xba5f, 0xa004, 0xe190, 0xba3f,
+	0x360e, 0x3e0f, 0xe005, 0x4454, 0x1a0e, 0xf069, 0xe005, 0x4731,
+	0x1a0f, 0xf029, 0xf24e, 0xe005, 0x4741, 0x1a0e, 0xf0b9, 0xe005,
+	0x3934, 0x1a0f, 0xf079, 0xba7f, 0xa008, 0xba0f, 0xa10d, 0xe40b,
+	0x15c5, 0xc009, 0x2a2d, 0xc000, 0xe045, 0xa009, 0xc009, 0x3e2d,
+	0xc000, 0xe41e, 0x166e, 0xa202, 0xe42e, 0xba4f, 0xa002, 0xc009,
+	0x2a2d, 0xc000, 0xe045, 0xf4d1, 0xa202, 0xe42e, 0xba7e, 0xba40,
+	0xf098, 0xba41, 0xba4a, 0xf04b, 0xba46, 0xba46, 0x3cb0, 0xa202,
+	0xe42e, 0xa200, 0xe42e, 0xe41e, 0x166e, 0xa202, 0xe42e, 0xc009,
+	0xa2fe, 0x3426, 0x3c27, 0xa201, 0x3628, 0x3e29, 0x362a, 0x3e2b,
+	0xc000, 0xe41e, 0x0c9b, 0xc009, 0xe40d, 0x1654, 0x3426, 0x3c27,
+	0xba40, 0xe40d, 0x1654, 0xae2a, 0xe055, 0x3628, 0x3e29, 0xe408,
+	0x164a, 0xba4c, 0xe40d, 0x1654, 0xae0c, 0xe055, 0xba40, 0xe40d,
+	0x1654, 0xae28, 0xe055, 0xba4a, 0xe40d, 0x1654, 0xe055, 0xba40,
+	0xe40d, 0x1654, 0xae26, 0xe055, 0xba40, 0xe40d, 0x1654, 0xae24,
+	0xe055, 0xba40, 0xe40d, 0x1654, 0xae22, 0xe055, 0xba40, 0xe40d,
+	0x1654, 0xae20, 0xe055, 0xba40, 0xe40d, 0x1654, 0xae1e, 0xe055,
+	0xba40, 0xe40d, 0x1654, 0xae1c, 0xe055, 0x3628, 0x3e29, 0xe04a,
+	0xaf28, 0xa802, 0xe016, 0xaf0d, 0xa83f, 0xa10b, 0xe01b, 0xe052,
+	0xf12a, 0xa201, 0xba46, 0xf21d, 0xae38, 0xe055, 0xba46, 0xf1dd,
+	0xae30, 0xe055, 0xba46, 0xf19d, 0xae28, 0xe055, 0xba46, 0xf15d,
+	0xae20, 0xe055, 0xba4e, 0xf11d, 0xe0c4, 0x4064, 0xf0ed, 0xe055,
+	0x362a, 0x3e2b, 0x2228, 0x4e29, 0xba40, 0xae1a, 0xe055, 0x3628,
+	0x3e29, 0xa202, 0xc000, 0xe42e, 0xc009, 0xa2fe, 0x3426, 0x3c27,
+	0xa200, 0x3428, 0x3c29, 0x342a, 0x3c2b, 0xc000, 0xe42e, 0xc009,
+	0x2426, 0x4c27, 0xc000, 0xe42e, 0xc009, 0x2428, 0x4c29, 0xc000,
+	0xe42e, 0xc009, 0x242a, 0x4c2b, 0xc000, 0xe42e, 0xe0c0, 0x0065,
+	0xa878, 0xa140, 0xf0ba, 0xe41e, 0x1777, 0xa102, 0xcc44, 0xe184,
+	0x167a, 0xba4e, 0xe190, 0xe40e, 0x16fe, 0xa201, 0xe41e, 0x1759,
+	0x2907, 0xa002, 0x3c0c, 0x3d17, 0xa120, 0xf6e0, 0x2b07, 0xe41e,
+	0x176f, 0xf05a, 0xe41e, 0x1777, 0xe041, 0xf05e, 0x2861, 0xa002,
+	0xae06, 0xe041, 0xa00f, 0xaf07, 0xae07, 0xe04a, 0xaf1f, 0xf0db,
+	0xa201, 0xe41e, 0x1759, 0x8117, 0x8117, 0x2907, 0xa202, 0x3d07,
+	0xa201, 0xe41e, 0x1757, 0xf50e, 0x3d17, 0xa201, 0xe41e, 0x1757,
+	0xe167, 0x0600, 0xe41e, 0x176f, 0x3d17, 0xe41e, 0x176f, 0xf04a,
+	0xe41e, 0x1777, 0xf04e, 0x2861, 0xa002, 0xae06, 0x3d17, 0x2a0c,
+	0xe41e, 0x1757, 0xa200, 0x3c0b, 0xa200, 0xe167, 0x0600, 0xc703,
+	0x3d17, 0xe167, 0x0600, 0xe41e, 0x176f, 0xf3ba, 0xe41e, 0x176f,
+	0xa108, 0xf0f8, 0xe004, 0x4741, 0x3d17, 0xe004, 0x3934, 0x3d17,
+	0x28a7, 0xa008, 0x3ca7, 0xe41e, 0x1777, 0xa108, 0xe41e, 0x1773,
+	0x280b, 0xa002, 0x3c0b, 0xba4f, 0x28a7, 0xa002, 0x3ca7, 0xa802,
+	0xf058, 0x280a, 0xae10, 0xe056, 0x3d17, 0x3e0a, 0x28a7, 0xa80e,
+	0xe41a, 0x1719, 0xe41e, 0x1777, 0x180b, 0xf6b0, 0x28a7, 0xa80e,
+	0xf0ea, 0x2aa7, 0xa803, 0xf04b, 0x280a, 0xae10, 0x3d17, 0x2aa7,
+	0xa00f, 0xaf07, 0xae07, 0x3ea7, 0xe418, 0x1719, 0xe40e, 0x1717,
+	0x280b, 0xa002, 0x3c0b, 0x2901, 0xe41e, 0x0cd8, 0x3517, 0x3d17,
+	0x2901, 0xe41e, 0x0cd8, 0x3517, 0x3d17, 0x28a7, 0xa010, 0x3ca7,
+	0xe41e, 0x1719, 0x2861, 0xa002, 0x180b, 0xf6b0, 0xf01a, 0xa202,
+	0xe42e, 0x24b7, 0x4cb8, 0xe000, 0x0088, 0x18a7, 0xf242, 0xe0c0,
+	0x0065, 0xaf12, 0xa802, 0xf0da, 0xa201, 0xe41e, 0x1759, 0x8117,
+	0x8117, 0x2907, 0xa202, 0x3d07, 0xa201, 0xe41e, 0x1757, 0xe42e,
+	0xe004, 0x0200, 0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202,
+	0xce00, 0xe0c0, 0x005d, 0xe008, 0x0200, 0xe190, 0xf7b8, 0xe004,
+	0x0090, 0x3ca7, 0x24b5, 0x4cb6, 0x08a7, 0xa110, 0xce20, 0xd111,
+	0x0600, 0xd112, 0x0004, 0xd113, 0x0000, 0xca28, 0xf7f8, 0xa200,
+	0xe167, 0x0600, 0xc703, 0x3d17, 0xe167, 0x0600, 0xe42e, 0xa200,
+	0xf02e, 0xa202, 0x3c0d, 0x24b5, 0x4cb6, 0xae07, 0xe042, 0xce20,
+	0xd111, 0x0600, 0xd112, 0x0004, 0x880d, 0x0113, 0xca28, 0xf7f8,
+	0xe167, 0x0600, 0xe42e, 0xc009, 0x3c2c, 0xc000, 0xe42e, 0xc009,
+	0x282c, 0xc000, 0xe42e, 0xc009, 0x3c2d, 0xc000, 0xe42e, 0xc009,
+	0x282d, 0xc000, 0xe42e, 0x2c39, 0x3c7b, 0xa202, 0x3c7c, 0xa200,
+	0x3c7d, 0x3c7e, 0x284e, 0xe016, 0xe428, 0x284f, 0xf0ca, 0xe41e,
+	0x181a, 0xba40, 0xba40, 0xb7f0, 0xb634, 0x3c7c, 0xa200, 0x3c7b,
+	0xa202, 0xe42e, 0xba40, 0xf11a, 0x2819, 0xe42a, 0xae02, 0x3c09,
+	0x2014, 0x4c15, 0x583f, 0x3400, 0x3c01, 0x2c39, 0x583f, 0x083f,
+	0x3402, 0x3c03, 0xbc0c, 0xf058, 0xa202, 0x3c7d, 0xe42e, 0xbc0c,
+	0xe40d, 0x1817, 0xe40a, 0x1815, 0xa102, 0xf0ca, 0xa102, 0xf1fa,
+	0xa102, 0xf24a, 0xa102, 0xf39a, 0xa102, 0xe40a, 0x17f5, 0xe40e,
+	0x17fd, 0xe41e, 0x0c9b, 0xe40d, 0x1817, 0xa002, 0x1002, 0x1c03,
+	0xe012, 0x3c0a, 0xf032, 0x0000, 0x0c01, 0xa203, 0xe41e, 0x1821,
+	0x2a0a, 0x3e04, 0x4c4f, 0xe41a, 0x1839, 0xf5ae, 0xbc40, 0xe40d,
+	0x1817, 0xa2ff, 0xe41e, 0x1821, 0xf53e, 0xe41e, 0x0c9b, 0xe40d,
+	0x1817, 0xa002, 0x1002, 0x1c03, 0xe012, 0xf032, 0x0000, 0x0c01,
+	0x3c06, 0xa802, 0x443f, 0xbc21, 0xf33d, 0x5a3f, 0xe041, 0x3e07,
+	0xe41e, 0x1868, 0xe40e, 0x17a7, 0xbc20, 0xf2ad, 0xa102, 0x583f,
+	0x083f, 0xe41e, 0x1883, 0xe40e, 0x17a7, 0xe41e, 0x181a, 0xa202,
+	0x3c7e, 0xa200, 0x3c7b, 0xe40e, 0x17a7, 0xbc20, 0xf19d, 0x3c7b,
+	0x287b, 0x583f, 0x083f, 0xa2ff, 0xe41e, 0x1821, 0xf7a8, 0x283f,
+	0xf09a, 0x2840, 0xf078, 0x287b, 0xae02, 0xa2ff, 0xe41e, 0x1821,
+	0xf7b8, 0xa2fe, 0x3c7c, 0xe40e, 0x17a7, 0xa202, 0xe42e, 0xe16a,
+	0xa200, 0xe42e, 0xc410, 0xe161, 0x02f1, 0xa200, 0xc71f, 0x3d31,
+	0xe42e, 0x3c04, 0x3e05, 0xe161, 0x02f0, 0x8809, 0x0022, 0xe184,
+	0x1834, 0x2d11, 0x2b09, 0x1c04, 0x1a05, 0xf068, 0xf059, 0x8111,
+	0xa200, 0x3d09, 0xf05e, 0x8111, 0x8111, 0xa200, 0xe42e, 0xa202,
+	0xe42e, 0xe161, 0x02f0, 0x8809, 0x0022, 0xe184, 0x1849, 0x2d11,
+	0x2b09, 0x1804, 0x1a05, 0xf050, 0xf049, 0x8111, 0xa200, 0x3d09,
+	0x8111, 0x8111, 0xe160, 0x0003, 0xe161, 0x02f1, 0x8809, 0x0022,
+	0xe184, 0x1865, 0x2909, 0xf11a, 0x2d01, 0x2e39, 0x5a3f, 0xe045,
+	0xf053, 0x2214, 0x4e15, 0x5a3f, 0xe046, 0xae02, 0x1804, 0xf052,
+	0xa200, 0x8111, 0x3d01, 0xe42e, 0x8131, 0xe190, 0xa202, 0xe42e,
+	0x2807, 0xa2ff, 0xe41e, 0x1821, 0xf7c8, 0xe161, 0x02f0, 0x8809,
+	0x0022, 0xe184, 0x187e, 0x2d11, 0x2b09, 0x1c06, 0xf078, 0xf067,
+	0x2807, 0x3d11, 0xa2fe, 0x3d09, 0xf05e, 0x8111, 0x8111, 0xa200,
+	0xe42e, 0xa202, 0xe42e, 0x3c08, 0xe161, 0x02f0, 0x8809, 0x0022,
+	0xe184, 0x1893, 0x2d11, 0x2b09, 0x1808, 0xf056, 0xf043, 0x8111,
+	0xa200, 0x3d09, 0x8111, 0x8111, 0xe42e, 0x2819, 0x1812, 0xf122,
+	0x2812, 0xa102, 0xcc44, 0xe161, 0x0202, 0xe184, 0x18a8, 0x2911,
+	0xf06a, 0x2909, 0xe412, 0x1ff5, 0xa200, 0x3d11, 0xe082, 0xa006,
+	0xe092, 0x2819, 0xb62c, 0x3c12, 0x2816, 0xa104, 0xe428, 0xe41e,
+	0x1a5c, 0xe42e, 0x2816, 0xa102, 0xf044, 0xf16a, 0xe40e, 0x1900,
+	0x7417, 0xe160, 0x0903, 0x3d00, 0x283f, 0xe016, 0x442a, 0xe418,
+	0x0cb5, 0xe42d, 0xe161, 0x0904, 0xe162, 0x0905, 0x3501, 0x3d02,
+	0xe41e, 0x1974, 0xf38e, 0xa200, 0xe160, 0x0903, 0xe161, 0x0904,
+	0xe162, 0x0905, 0xe163, 0x0906, 0x3500, 0x3d01, 0x3502, 0x3d03,
+	0x2818, 0xf178, 0xe41e, 0x0cb5, 0xe42d, 0xe164, 0x0903, 0xe165,
+	0x0904, 0x3504, 0x3d05, 0x282a, 0xf0ca, 0x283f, 0xf0a8, 0xe41e,
+	0x0cb5, 0xe42d, 0xe166, 0x0905, 0xe167, 0x0906, 0x3506, 0x3d07,
+	0xe41e, 0x19c4, 0xf10e, 0xe164, 0x0903, 0xe165, 0x0904, 0xe166,
+	0x0905, 0xe167, 0x0906, 0x3504, 0x3d05, 0x3506, 0x3d07, 0xf03e,
+	0xe41e, 0x1a15, 0x283f, 0x2a42, 0xf0f9, 0xf078, 0x2074, 0x4c75,
+	0x2276, 0x4e77, 0xe066, 0xf0ee, 0x2074, 0x4c75, 0xc009, 0x343b,
+	0x3c3c, 0xc000, 0xf07e, 0x2076, 0x4c77, 0xc009, 0x343d, 0x3c3e,
+	0xc000, 0x3472, 0x3c73, 0xe42e, 0x284f, 0x4c7e, 0xf03a, 0x28d6,
+	0xe016, 0xe418, 0x1a5c, 0x28e5, 0xae02, 0xe000, 0x0578, 0xe092,
+	0x2072, 0x4c73, 0x3511, 0x3d11, 0x28e5, 0xe000, 0x059a, 0xe092,
+	0x2884, 0x2ad8, 0xae1f, 0xe056, 0x3d11, 0x28e5, 0xa002, 0x3ce5,
+	0x28eb, 0x2a16, 0xa105, 0xb616, 0x2a21, 0xb616, 0x3c07, 0xe41e,
+	0x2014, 0xf048, 0xe41e, 0x1a61, 0xf7be, 0xe41e, 0x2024, 0xe428,
+	0xe41e, 0x1a61, 0xf7be, 0x28e9, 0xf04a, 0xa102, 0x3ce9, 0xf1fe,
+	0x28e8, 0xf1da, 0x28e7, 0xe000, 0x05ab, 0xe092, 0x28e7, 0xa002,
+	0x3ce7, 0xa124, 0xf028, 0x3ce7, 0x28e8, 0xa102, 0x3ce8, 0x2901,
+	0xe049, 0xe009, 0x8000, 0xf08b, 0x26a8, 0x4ea9, 0xa903, 0x36a8,
+	0x3ea9, 0xe008, 0x7fff, 0xe049, 0x1a7f, 0xe425, 0xe41e, 0x08d2,
+	0xe049, 0xa2fa, 0xb7f2, 0xe42e, 0xa202, 0x5817, 0xaf02, 0x3c06,
+	0x284f, 0x2a82, 0xf0b8, 0xf0d9, 0xe164, 0x0906, 0x2114, 0x4d14,
+	0xe166, 0x0908, 0x2316, 0x4f16, 0xf09e, 0xa200, 0xa201, 0xf06e,
+	0xa200, 0xe161, 0x090a, 0x2311, 0x4f11, 0x3400, 0x3c01, 0x3602,
+	0x3e03, 0xe161, 0x0903, 0x2f01, 0x1202, 0x1e03, 0xf071, 0xe013,
+	0x1e06, 0xf085, 0x0c06, 0x0c06, 0xf05e, 0x1e06, 0xf037, 0x1c06,
+	0x1c06, 0x3404, 0x3c05, 0xe161, 0x0903, 0x0d01, 0x3474, 0x3c75,
+	0xe162, 0x0904, 0x0112, 0x0d12, 0x3476, 0x3c77, 0x284e, 0xf14a,
+	0x2074, 0x4c75, 0xe161, 0x090a, 0x3511, 0x3d11, 0x2004, 0x4c05,
+	0xe164, 0x0906, 0x3514, 0x3d14, 0xe161, 0x0903, 0xe166, 0x0908,
+	0x2d01, 0x3516, 0x3d16, 0xe42e, 0xe41e, 0x1a26, 0xe160, 0x090b,
+	0x2900, 0xf34a, 0x2000, 0x4c01, 0x0c39, 0xf306, 0x2a4e, 0xe017,
+	0xe046, 0xa102, 0xf2b4, 0xe160, 0x090b, 0xe188, 0x000f, 0x7d00,
+	0x3402, 0x3c03, 0xe41e, 0x1a4c, 0xe163, 0x090b, 0x2903, 0xa102,
+	0xcc44, 0xe161, 0x09e0, 0xa200, 0xe184, 0x19e7, 0x0111, 0x0d11,
+	0xae02, 0x3404, 0xe008, 0xffff, 0xaf02, 0x3c05, 0x8403, 0x8204,
+	0xe018, 0xae1e, 0x8205, 0xe01c, 0xe161, 0x09e0, 0x8802, 0x0022,
+	0xe184, 0x19fb, 0x0111, 0x0d11, 0xf02e, 0xa200, 0x2a4e, 0xf059,
+	0xe161, 0x0907, 0x0111, 0x0d11, 0xe164, 0x0903, 0x0114, 0x0d14,
+	0x3474, 0x3c75, 0xe162, 0x0909, 0x0112, 0x0d12, 0xe166, 0x0905,
+	0x0116, 0x0d16, 0x3476, 0x3c77, 0xe42e, 0xe41e, 0x1a26, 0x284f,
+	0xe016, 0xf08a, 0x2000, 0x4c01, 0x0c39, 0xae02, 0x2a4e, 0xe017,
+	0xe046, 0x3474, 0x3c75, 0x3476, 0x3c77, 0xe42e, 0x2882, 0xf09a,
+	0xa200, 0xe162, 0x0901, 0x3512, 0x3d12, 0xe161, 0x0900, 0x3d01,
+	0x284f, 0xe016, 0xf0da, 0xe162, 0x0901, 0x2112, 0x4d12, 0xe161,
+	0x0900, 0x2f01, 0x1e39, 0xf047, 0xa203, 0x5a13, 0xe042, 0x3400,
+	0x3c01, 0x2839, 0xe161, 0x0900, 0x3d01, 0x2000, 0x4c01, 0xe162,
+	0x0901, 0x3512, 0x3d12, 0xe42e, 0xe0c0, 0x0041, 0xe005, 0x0026,
+	0xae11, 0xe042, 0xce20, 0xd111, 0x09e0, 0xd112, 0x0200, 0xd113,
+	0x0003, 0xca28, 0xf7f8, 0xe42e, 0x28e5, 0xe426, 0xe41e, 0x1a61,
+	0xf7ce, 0x28e5, 0xe426, 0xe161, 0x0578, 0xe162, 0x0578, 0x2111,
+	0x4d11, 0xa201, 0x3e00, 0xa203, 0x28e5, 0xa104, 0xf0e4, 0xcc44,
+	0xe184, 0x1a7b, 0x2112, 0x4d0a, 0x1111, 0x1d11, 0xf056, 0xe082,
+	0xa104, 0xe094, 0x3e00, 0xa003, 0xe084, 0xa004, 0xe092, 0x2800,
+	0xe000, 0x059a, 0xe098, 0xa002, 0xe096, 0x2904, 0x3c01, 0xe41e,
+	0x1ffc, 0x28e5, 0x1800, 0xa104, 0xf0a4, 0xcc44, 0xe184, 0x1a95,
+	0x2911, 0x3d12, 0x2911, 0x3d12, 0x2913, 0x3d14, 0x28e5, 0xb5f0,
+	0x3ce5, 0x28e6, 0xe000, 0x05ab, 0xe092, 0x2801, 0x3d01, 0x28e6,
+	0xa002, 0x3ce6, 0xa124, 0xf028, 0x3ce6, 0x28e8, 0xa002, 0x3ce8,
+	0xe42e, 0xa200, 0x3cb2, 0xe004, 0x0054, 0xe09c, 0x287f, 0xa102,
+	0xcc44, 0xe184, 0x1ac2, 0x9e06, 0x5cb2, 0xa802, 0xf0a8, 0x28b2,
+	0xe049, 0xe001, 0x0518, 0xe09f, 0x2b07, 0xa809, 0xe419, 0x2005,
+	0x2ab2, 0xa003, 0x3eb2, 0xe42e, 0xe004, 0x0518, 0xe09e, 0xe004,
+	0x0054, 0xe09c, 0x287f, 0xa102, 0xcc44, 0xa200, 0x3cb2, 0xe184,
+	0x1ad8, 0x2b17, 0xaf05, 0xa803, 0x5ab2, 0xe056, 0x2ab2, 0xa003,
+	0x3eb2, 0x9f06, 0xe42e, 0x2840, 0xf078, 0xe41e, 0x2041, 0x3c3e,
+	0xe41e, 0x2092, 0xf03e, 0x283e, 0x3c84, 0xe42e, 0xe161, 0x0600,
+	0xa200, 0x3d11, 0x3c02, 0xd022, 0x013f, 0xe184, 0x1af3, 0xe41e,
+	0x1bdb, 0x2802, 0xa002, 0x3c02, 0xa200, 0x3c9b, 0xe42e, 0xba4e,
+	0xba40, 0xba40, 0xba40, 0xba40, 0xba46, 0xba4e, 0xbc3e, 0xf10d,
+	0x3c00, 0x1810, 0xf038, 0xa2fe, 0x3c10, 0x2800, 0xe000, 0x0100,
+	0x2ad6, 0xf02b, 0xa040, 0xe41e, 0x1b6c, 0xa202, 0xe42e, 0xe16a,
+	0xa200, 0xe42e, 0xa204, 0x3c9b, 0x2810, 0xe000, 0x0100, 0x2ad6,
+	0xf02b, 0xa040, 0xe41e, 0x1ba7, 0xe42a, 0xe41e, 0x1023, 0xf056,
+	0xe41e, 0x1895, 0xa202, 0xe42e, 0xa2fe, 0x3c10, 0xa200, 0xe42e,
+	0xe41e, 0x0c9b, 0xf12d, 0x3c01, 0xe002, 0x00ff, 0xf0e0, 0x2801,
+	0x1829, 0xf038, 0xa2fe, 0x3c29, 0x28ae, 0xa802, 0x3cae, 0x2801,
+	0xe41e, 0x1b6c, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0xa202,
+	0x3c9b, 0x2829, 0xe41e, 0x1ba7, 0xf0da, 0xe41e, 0x1142, 0x3c65,
+	0xa200, 0xe41e, 0x0c4f, 0xa201, 0x3e9b, 0x2865, 0xf03a, 0xa202,
+	0xe42e, 0xe0c1, 0x0059, 0xa107, 0xf079, 0x28ae, 0xa104, 0xf04a,
+	0x28ae, 0xa902, 0x3cae, 0xa2fe, 0x3c29, 0xa200, 0xe42e, 0x2860,
+	0xa102, 0xf06a, 0x2499, 0x4c9a, 0xe41e, 0x1bf5, 0xe470, 0xe41e,
+	0x1c0e, 0xe41e, 0x1bfc, 0xe470, 0x3c02, 0xe41e, 0x1bdd, 0xa200,
+	0x3c06, 0x2802, 0xae14, 0x3404, 0x3c05, 0xe41e, 0x0c4a, 0x0404,
+	0x0c05, 0xce20, 0xd111, 0x0000, 0xe41e, 0x0c1d, 0x1806, 0xa00e,
+	0xaf06, 0xae02, 0xce24, 0xd113, 0x0012, 0xca28, 0xf7f8, 0xca2c,
+	0xf7fa, 0xe41e, 0x0c26, 0xf128, 0x2004, 0x4c05, 0xe000, 0x0200,
+	0x3404, 0x3c05, 0xe41e, 0x0c1d, 0x3c06, 0xe41e, 0x09ee, 0xe41e,
+	0x0c1d, 0xe002, 0x0400, 0xf020, 0xf59e, 0xe161, 0x0600, 0xa202,
+	0x3d11, 0xe41e, 0x0c1d, 0x3d01, 0xe41e, 0x1bdb, 0xe42e, 0x3c02,
+	0xe41e, 0x1bdd, 0xe161, 0x0600, 0x2911, 0xe42a, 0x8111, 0x2111,
+	0x4d11, 0x2802, 0xae14, 0x3404, 0x3c05, 0x289b, 0xa102, 0xf0da,
+	0xe41e, 0x0c4a, 0x0404, 0x0c05, 0xe41e, 0x1bf5, 0xa204, 0xe41e,
+	0x0c4f, 0xe004, 0x0090, 0xf0ce, 0xe41e, 0x0c4a, 0x0404, 0x0c05,
+	0xe41e, 0x1bfc, 0xa202, 0xe41e, 0x0c4f, 0xe004, 0x0080, 0xcc66,
+	0xcc6a, 0xcc6e, 0xa01e, 0xcc6c, 0xa200, 0xcc60, 0xcc68, 0xcc70,
+	0xe128, 0xa202, 0xe42e, 0xa204, 0xf02e, 0xa206, 0x3c0a, 0xe41e,
+	0x1beb, 0xce20, 0xd111, 0x0600, 0xd112, 0x0004, 0x880a, 0x0113,
+	0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0041, 0xe005, 0x002a, 0xae11,
+	0xe042, 0x2a02, 0xae07, 0xe042, 0xe42e, 0xce20, 0xa080, 0x3499,
+	0x3c9a, 0xd111, 0x0090, 0xf07e, 0xce20, 0xa080, 0xe41e, 0x1c09,
+	0xd111, 0x0080, 0xd112, 0x0010, 0xd113, 0x0013, 0xca28, 0xf7f8,
+	0xe42e, 0xc009, 0x3410, 0x3c11, 0xc000, 0xe42e, 0xc009, 0x2410,
+	0x4c11, 0xc000, 0xe42e, 0xe41e, 0x1c28, 0x2819, 0xe42a, 0xa102,
+	0x3c00, 0x284e, 0xe01a, 0x2abe, 0xa003, 0xa803, 0xe052, 0xe418,
+	0x1d80, 0xe41e, 0x1db5, 0xe41e, 0x1ded, 0xe41e, 0x1e20, 0xe42e,
+	0x28d6, 0xe42a, 0x2a19, 0xae05, 0xe001, 0x0200, 0x28d7, 0xf234,
+	0xe093, 0xa200, 0x3d11, 0xa2fc, 0x3d11, 0xa206, 0x3d11, 0x28d7,
+	0x3d11, 0x2a19, 0xae03, 0xe001, 0x0240, 0xe09b, 0x2a19, 0xae05,
+	0xe001, 0x0260, 0xe09d, 0x2a19, 0xe001, 0x02a0, 0xe09f, 0x2072,
+	0x4c73, 0x3515, 0x3d15, 0x3516, 0x3d16, 0x3516, 0x3d16, 0xa200,
+	0x3d07, 0xf05e, 0xa005, 0xe093, 0xa200, 0x3d01, 0xe42e, 0xc418,
+	0xe161, 0x0202, 0xa201, 0x2819, 0xf0c6, 0xa102, 0xcc44, 0xe184,
+	0x1c67, 0x2911, 0xf05a, 0x2909, 0xe41e, 0x1ff5, 0x3f11, 0x8131,
+	0xe42e, 0x287e, 0xf11a, 0x2074, 0x4c75, 0x1072, 0x1c73, 0x3474,
+	0x3c75, 0x2076, 0x4c77, 0x1072, 0x1c73, 0x3476, 0x3c77, 0xa200,
+	0x3472, 0x3c73, 0x3c3c, 0xa200, 0x3cbe, 0x2c39, 0x2a4f, 0x4e7e,
+	0xb612, 0x3c80, 0x2819, 0xf12a, 0xa102, 0x3c00, 0x2839, 0x3c50,
+	0x287d, 0xe41a, 0x1d44, 0x2840, 0xe016, 0xe418, 0x1d15, 0x2840,
+	0xe408, 0x1cd9, 0xe41e, 0x1c99, 0xe42e, 0x2884, 0xe41e, 0x1ff5,
+	0xe42e, 0xc420, 0xe161, 0x0202, 0x8800, 0x0022, 0xe184, 0x1ca2,
+	0x2901, 0xf03a, 0x8131, 0xe42e, 0xe082, 0xe002, 0x0202, 0xaf04,
+	0x3c0a, 0x2841, 0x3d09, 0x287c, 0x3d09, 0x287b, 0x3d31, 0x8109,
+	0x2884, 0x3d11, 0xe082, 0xe000, 0x005c, 0xe094, 0xe002, 0x0260,
+	0xaf02, 0xe000, 0x0240, 0xe092, 0x2072, 0x4c73, 0x3511, 0x3d11,
+	0x2a41, 0xa105, 0x2112, 0x4d0a, 0xf03b, 0x2074, 0x4c75, 0x3512,
+	0x3d12, 0x2112, 0x4d0a, 0xf035, 0x2076, 0x4c77, 0x3512, 0x3d12,
+	0x280a, 0xe000, 0x02a0, 0xe092, 0xa206, 0x1841, 0xe01a, 0x3d01,
+	0xe42e, 0xe161, 0x0200, 0x8800, 0x0022, 0xe184, 0x1ce6, 0x2d11,
+	0x2b11, 0x1c7b, 0x1a7c, 0xf028, 0xf04b, 0x8111, 0x8111, 0xe42e,
+	0xa206, 0x3d01, 0xe082, 0xe000, 0x005e, 0xe094, 0xe002, 0x0260,
+	0xaf02, 0xe000, 0x0240, 0xe092, 0xe002, 0x0240, 0xaf02, 0x3c0a,
+	0x2072, 0x4c73, 0x2311, 0x4f09, 0xe066, 0x3511, 0x3d11, 0xf41e,
+	0xc420, 0xe161, 0x0202, 0x8800, 0x0022, 0xe184, 0x1d09, 0x2901,
+	0xf03a, 0x8131, 0xe42e, 0xa206, 0x3d09, 0xa202, 0x3d09, 0x2850,
+	0x3d31, 0x8109, 0xa2fe, 0x3d11, 0xe42e, 0xa200, 0xc420, 0xe161,
+	0x0202, 0x8800, 0x0022, 0xe184, 0x1d1f, 0x2b31, 0xe01b, 0xe042,
+	0x1819, 0xe424, 0xa203, 0xae21, 0xe161, 0x0202, 0x8800, 0x0022,
+	0xe184, 0x1d3d, 0x2909, 0xf11a, 0x2909, 0xf0e6, 0x2901, 0x1c50,
+	0xf036, 0x1014, 0x1c15, 0x0c50, 0xe046, 0xf062, 0xe042, 0xe049,
+	0xe082, 0xa004, 0xe094, 0x8111, 0x8111, 0x8131, 0xa200, 0x3d12,
+	0x2912, 0xe412, 0x1ff5, 0xe42e, 0xe161, 0x0200, 0xe162, 0x02f0,
+	0x8800, 0x0022, 0xe184, 0x1d7e, 0x283f, 0xf098, 0x2912, 0x3c02,
+	0x2912, 0x3c03, 0xe01a, 0xb670, 0x3c04, 0xf15e, 0x2912, 0xaf02,
+	0x3c02, 0x2912, 0x3c03, 0xe01a, 0x3c04, 0x8112, 0x290a, 0xe01a,
+	0xae02, 0x4c04, 0x3c04, 0xa802, 0xf068, 0x2912, 0xaf02, 0x3c02,
+	0x290a, 0x3c03, 0x2804, 0x8112, 0x8112, 0xf08a, 0x2802, 0x3d11,
+	0x2803, 0x3d11, 0x2804, 0x3d11, 0xf0ae, 0x8111, 0x8111, 0x2901,
+	0xa201, 0x3f11, 0xf04a, 0x2901, 0xe412, 0x1ff5, 0x8111, 0xe42e,
+	0x284f, 0xe428, 0x2819, 0xe42a, 0x2840, 0xe428, 0xe41e, 0x1fe2,
+	0x4c1a, 0xe42a, 0x2c80, 0x3c50, 0xa200, 0x3c0f, 0x2850, 0xa002,
+	0x2214, 0x4e15, 0xa103, 0xe052, 0x3c50, 0x1c39, 0xe42a, 0x281a,
+	0x4caa, 0xf05a, 0xe41e, 0x1d15, 0xe41e, 0x1d00, 0x281a, 0xf6f8,
+	0x28ae, 0xa920, 0x3cae, 0x280f, 0xa002, 0x3c0f, 0xa120, 0xf062,
+	0xe41e, 0x05ab, 0xe41e, 0x181a, 0xf62e, 0xe41e, 0x05ab, 0xe41e,
+	0x1a5c, 0x28ae, 0xa908, 0x3cae, 0xe42e, 0xe161, 0x0200, 0xe162,
+	0x02f0, 0x8800, 0x0022, 0x28d6, 0xf03a, 0x8819, 0x0022, 0xe184,
+	0x1de1, 0x283f, 0xf0c8, 0x2911, 0x3d12, 0x2911, 0x2b11, 0xa107,
+	0xb612, 0x3d12, 0xa200, 0x3d12, 0x3d12, 0xf14e, 0x2911, 0xae02,
+	0xa002, 0x1842, 0x3d12, 0x2911, 0x2b09, 0xa803, 0xb616, 0x3d0a,
+	0x2912, 0x8112, 0xaa02, 0x3d12, 0x2911, 0x2b11, 0xa805, 0xb616,
+	0x3d12, 0x8111, 0xe161, 0x0330, 0xe162, 0x02f0, 0xd022, 0x003f,
+	0xe184, 0x1deb, 0x2912, 0x3d11, 0xe42e, 0x283f, 0xf148, 0xe41e,
+	0x1e7e, 0x2808, 0xe000, 0x0370, 0xe096, 0xe41e, 0x1ec0, 0x2808,
+	0x0809, 0x3c6d, 0xe000, 0x0370, 0xe096, 0xe41e, 0x1f7e, 0x086d,
+	0x3c6d, 0xe42e, 0xe41e, 0x1e7e, 0xe163, 0x0370, 0x2808, 0xe41e,
+	0x1f88, 0x3c08, 0xe000, 0x0370, 0xe096, 0xe41e, 0x1ec0, 0x2808,
+	0xe000, 0x0370, 0xe096, 0x2809, 0xe41e, 0x1f88, 0x0808, 0x3c6d,
+	0xe000, 0x0370, 0xe096, 0xe41e, 0x1f7e, 0x086d, 0x3c6d, 0xe42e,
+	0x283f, 0xf238, 0xe41e, 0x1ef9, 0x2808, 0xe000, 0x0390, 0xe096,
+	0xe41e, 0x1ec0, 0x2808, 0xe000, 0x03b0, 0xe096, 0xe41e, 0x1ec0,
+	0x2808, 0x0809, 0x3c6d, 0xe41e, 0x1fcb, 0x286d, 0xe000, 0x0390,
+	0xe096, 0xe41e, 0x1f7e, 0x286d, 0xe000, 0x03b0, 0xe096, 0xe41e,
+	0x1f7e, 0x086d, 0x3c6d, 0xe42e, 0xe41e, 0x1ef9, 0xe163, 0x0390,
+	0x2808, 0xe41e, 0x1f88, 0xe163, 0x03b0, 0x2808, 0xe41e, 0x1f88,
+	0x3c08, 0x2808, 0xe000, 0x0390, 0xe096, 0xe41e, 0x1ec0, 0x2808,
+	0xe000, 0x0390, 0xe096, 0x2809, 0xe41e, 0x1f88, 0x2808, 0xe000,
+	0x03b0, 0xe096, 0xe41e, 0x1ec0, 0x2808, 0xe000, 0x03b0, 0xe096,
+	0x2809, 0xe41e, 0x1f88, 0x0808, 0x3c6d, 0xe41e, 0x1fcb, 0x286d,
+	0xe000, 0x0390, 0xe096, 0xe41e, 0x1f7e, 0x286d, 0xe000, 0x03b0,
+	0xe096, 0xe41e, 0x1f7e, 0x086d, 0x3c6d, 0xe42e, 0xe161, 0x0600,
+	0xa200, 0xc70f, 0x3d11, 0x283f, 0xb674, 0x3c05, 0xa200, 0x3c08,
+	0xc420, 0xe163, 0x0370, 0xa2fe, 0x3c06, 0xa203, 0xae21, 0xe013,
+	0xe161, 0x0202, 0xe162, 0x0600, 0x8800, 0x0022, 0xe184, 0x1eaf,
+	0x2912, 0xf168, 0x2909, 0x1805, 0xf124, 0x2909, 0xf0f6, 0x2901,
+	0x1c39, 0xf036, 0x1014, 0x1c15, 0x0c39, 0xe046, 0xf076, 0xe042,
+	0xe049, 0xe084, 0xe002, 0x0601, 0x3c06, 0x8111, 0x8111, 0x8131,
+	0x2806, 0xe424, 0xe000, 0x0600, 0xe094, 0xa202, 0x3d02, 0x2806,
+	0xae02, 0x3d13, 0x2808, 0xa002, 0x3c08, 0x1819, 0xf4d8, 0xe42e,
+	0xe161, 0x0600, 0xa200, 0xc70f, 0x3d11, 0x283f, 0xb674, 0x3c05,
+	0xa200, 0x3c09, 0xc420, 0xa2fe, 0x3c07, 0xa221, 0xe161, 0x0202,
+	0xe162, 0x0600, 0x8800, 0x0022, 0xe184, 0x1ee8, 0x2912, 0xf118,
+	0x2909, 0x1805, 0xf0d4, 0x2909, 0xf0a2, 0x2901, 0xe046, 0xf072,
+	0xe042, 0xe049, 0xe084, 0xe002, 0x0601, 0x3c07, 0x8111, 0x8111,
+	0x8131, 0x2807, 0xe424, 0xe000, 0x0600, 0xe094, 0xa202, 0x3d02,
+	0x2807, 0xae02, 0x3d13, 0x2809, 0xa002, 0x3c09, 0x1819, 0xf548,
+	0xe42e, 0xe161, 0x0600, 0xa200, 0xc70f, 0x3d11, 0x283f, 0xb674,
+	0x3c05, 0xa200, 0x3c0a, 0xc420, 0xe163, 0x0390, 0xe164, 0x03b0,
+	0xa2fe, 0x3c06, 0x3c07, 0xe161, 0x0202, 0xe162, 0x0600, 0xe165,
+	0x0240, 0x8800, 0x0022, 0xe184, 0x1f44, 0x2912, 0xf2c8, 0x2909,
+	0x1805, 0xf284, 0x2909, 0xf256, 0x2115, 0x4d0d, 0x1072, 0x1c73,
+	0xf110, 0x2806, 0xf064, 0x2115, 0x4d0d, 0x100c, 0x1c0d, 0xf196,
+	0x2115, 0x4d0d, 0x340c, 0x3c0d, 0xe084, 0xe002, 0x0601, 0x3c06,
+	0xf10e, 0x2807, 0xf064, 0x2115, 0x4d0d, 0x100e, 0x1c0f, 0xf092,
+	0x2115, 0x4d0d, 0x340e, 0x3c0f, 0xe084, 0xe002, 0x0601, 0x3c07,
+	0x8111, 0x8111, 0x8131, 0x8115, 0x8115, 0x2806, 0xf094, 0xe000,
+	0x0600, 0xe094, 0xa202, 0x3d02, 0x2806, 0xae02, 0x3d13, 0x2807,
+	0xf094, 0xe000, 0x0600, 0xe094, 0xa202, 0x3d02, 0x2807, 0xae02,
+	0x3d14, 0x280a, 0xa002, 0x3c0a, 0x1819, 0xe408, 0x1f08, 0xe086,
+	0xe002, 0x0390, 0x3c0c, 0xe088, 0xe002, 0x03b0, 0x3c0d, 0xf09a,
+	0xa102, 0xcc44, 0xe164, 0x03b0, 0xe184, 0x1f6f, 0x2914, 0x3d13,
+	0x280c, 0xf09a, 0xa102, 0xcc44, 0xe163, 0x0390, 0xe184, 0x1f79,
+	0x2913, 0x3d14, 0x280c, 0x080d, 0x3c08, 0xe42e, 0x28d6, 0xf07a,
+	0x2819, 0xae02, 0x0842, 0x3d03, 0xa202, 0xe42e, 0xa200, 0xe42e,
+	0xe42a, 0xa102, 0x3c0c, 0xe086, 0xe098, 0xe161, 0x0600, 0x880c,
+	0x0022, 0xe184, 0x1fa3, 0x2903, 0xae02, 0xe000, 0x0202, 0xe094,
+	0x2902, 0xa802, 0xf03a, 0x2903, 0x3d11, 0x2902, 0xa804, 0xf04a,
+	0x2903, 0xa002, 0x3d11, 0x8113, 0xe082, 0xe002, 0x0600, 0xe42a,
+	0xa102, 0x3c0c, 0x3c0d, 0x2842, 0x3c0e, 0xe161, 0x0600, 0x880c,
+	0x0022, 0xe184, 0x1fb8, 0x2901, 0xf044, 0xa802, 0x180e, 0xf06a,
+	0x8111, 0x280e, 0xe016, 0x3c0e, 0xf71e, 0x2901, 0x3d14, 0xa2fe,
+	0x3d01, 0x280e, 0xe016, 0x3c0e, 0x280d, 0xa102, 0x3c0d, 0xf662,
+	0x280c, 0xa002, 0xe42e, 0x286d, 0xa102, 0xe426, 0xcc44, 0xe163,
+	0x0390, 0xe164, 0x03b0, 0xe184, 0x1fd8, 0x2913, 0x1914, 0xe428,
+	0xe190, 0xe163, 0x0391, 0xe164, 0x03b0, 0x290b, 0x3d14, 0x2903,
+	0x3d14, 0xe42e, 0x2819, 0xe426, 0xa102, 0xcc44, 0xc420, 0xe161,
+	0x0202, 0xe184, 0x1fed, 0x2901, 0xe428, 0x8131, 0xe42e, 0xe161,
+	0x0518, 0xa200, 0xc71f, 0x3d11, 0xe42e, 0xe000, 0x0518, 0xe09e,
+	0x2907, 0xa80c, 0x3d07, 0xe42e, 0xe008, 0x7fff, 0xe000, 0x0518,
+	0xe09e, 0x2907, 0xa80a, 0x3d07, 0xe42e, 0x3c81, 0xe000, 0x0518,
+	0xe09e, 0x2907, 0xa806, 0x3d07, 0x2881, 0xa002, 0x3c81, 0x187f,
+	0xe428, 0xa200, 0x3c81, 0xe42e, 0xe161, 0x0518, 0x287f, 0xa102,
+	0xcc44, 0xa201, 0xe184, 0x201f, 0x2911, 0xa804, 0xe01a, 0xe041,
+	0x1a07, 0xa202, 0xb602, 0xe42e, 0xe161, 0x0518, 0x287f, 0xa102,
+	0xcc44, 0xa200, 0xe184, 0x202f, 0x2b11, 0xa807, 0xe01b, 0xe042,
+	0x18eb, 0xa102, 0xe01a, 0xe42e, 0xe161, 0x0518, 0x287f, 0xa102,
+	0xcc44, 0xe049, 0xe184, 0x203d, 0x2911, 0xb5f1, 0xa202, 0xb60e,
+	0xe42e, 0x2881, 0x3c00, 0x2800, 0xe000, 0x0518, 0xe092, 0x2901,
+	0xf10a, 0x2800, 0xa002, 0x3c00, 0x187f, 0xf038, 0xa200, 0x3c00,
+	0x2800, 0x1881, 0xf718, 0xa200, 0x3c81, 0xa2fe, 0x3c84, 0xe42e,
+	0x2ad8, 0xae03, 0x24a8, 0x4ca9, 0xe056, 0x34a8, 0x3ca9, 0xa20e,
+	0x3d01, 0x2800, 0x3c84, 0xe42e, 0xe424, 0xc009, 0x3c32, 0xc000,
+	0x2841, 0xc009, 0xa804, 0xe01a, 0x5832, 0xe014, 0x2230, 0x4e31,
+	0xe051, 0x3630, 0x3e31, 0xc000, 0x2841, 0xc009, 0xa802, 0x5832,
+	0xe014, 0x222e, 0x4e2f, 0xe051, 0x362e, 0x3e2f, 0xc000, 0xe42e,
+	0xc009, 0x3c32, 0xa200, 0x2a32, 0xf0c5, 0x222e, 0x4e2f, 0x5e32,
+	0xa803, 0xe056, 0x2230, 0x4e31, 0x5e32, 0xa803, 0xae03, 0xe056,
+	0xc000, 0xe42e, 0xe424, 0xc009, 0x3c32, 0xa202, 0x5832, 0x2230,
+	0x4e31, 0xe055, 0x3630, 0x3e31, 0x222e, 0x4e2f, 0xe055, 0x362e,
+	0x3e2f, 0xc000, 0xe42e, 0xe0c1, 0x0044, 0xa80f, 0xe056, 0xe42e,
+	0xa200, 0xe41e, 0x20a3, 0xe42e, 0xe0c1, 0x0044, 0xaf0d, 0xae03,
+	0xe056, 0xe008, 0x003f, 0xe42e, 0xe0c1, 0x0044, 0xaf17, 0xa803,
+	0xe42e, 0xe0c1, 0x0044, 0xaf17, 0xa803, 0xa105, 0xf039, 0xa213,
+	0xe42e, 0xa201, 0xe42e, 0xa203, 0xe0c3, 0x040d, 0xe0c1, 0x0420,
+	0xa803, 0xf7db, 0xe160, 0x0003, 0xe166, 0x0640, 0xe167, 0x0500,
+	0x287f, 0xf166, 0xa102, 0xcc44, 0xe184, 0x20e6, 0xa200, 0xe41e,
+	0x20a3, 0xaf04, 0xe41e, 0x20ac, 0xae20, 0x2e66, 0xe056, 0x9f17,
+	0x2057, 0x4c58, 0xae08, 0x9f17, 0xe41e, 0x20ec, 0xe190, 0xe190,
+	0xa201, 0xe0c3, 0x040d, 0xe42e, 0x2116, 0x4d16, 0x9f17, 0x2116,
+	0x4d16, 0x9f17, 0x2116, 0x4d16, 0x9f17, 0xe42e, 0xe0c0, 0x0044,
+	0xaf20, 0xa802, 0xe428, 0xe0c0, 0x0060, 0xa860, 0xe42a, 0xe0c0,
+	0x0061, 0xa83e, 0xa203, 0xe0c3, 0x040d, 0xcca4, 0xc785, 0xe018,
+	0xe000, 0x0500, 0xe09e, 0xe0c1, 0x0420, 0xa803, 0xf7db, 0xa200,
+	0xe41e, 0x20a8, 0xa80e, 0xaf04, 0xe41e, 0x20ac, 0xe41e, 0x20b4,
+	0xe40b, 0x211f, 0xa81e, 0xe41e, 0x20b9, 0xae09, 0xe056, 0xae20,
+	0xe0c1, 0x006e, 0xe009, 0x1fff, 0xe056, 0x9f17, 0xe0c0, 0x0060,
+	0xa822, 0xa122, 0xf04a, 0x2057, 0x4c58, 0xf03e, 0x2058, 0x4c57,
+	0xae08, 0x9f17, 0xe0c0, 0x0062, 0x9f17, 0xe0c0, 0x0063, 0x9f17,
+	0xe0c0, 0x0064, 0x9f17, 0xa201, 0xe0c3, 0x040d, 0xe42e, 0x3cec,
+	0xe0c0, 0x0041, 0xe005, 0x0020, 0xae11, 0xe042, 0xce20, 0xd111,
+	0x0640, 0xd112, 0x00c0, 0x88ec, 0x0113, 0xca29, 0xf7f9, 0xe190,
+	0xe42e, 0xa2fe, 0x3c89, 0xa200, 0x3c88, 0xe42e, 0x2856, 0x3c89,
+	0x2889, 0xf032, 0xa200, 0x3c88, 0xa200, 0x3c8d, 0x3c8e, 0x2857,
+	0x3c8b, 0x2858, 0x3c8c, 0x2888, 0xe42a, 0x2889, 0xe424, 0x2889,
+	0xe0c2, 0x0143, 0x288a, 0xe0c2, 0x0144, 0xa200, 0xe0c2, 0x017f,
+	0xe0c2, 0x0149, 0xe41e, 0x20a3, 0xe0c2, 0x017f, 0x288b, 0xa102,
+	0xae20, 0x4c8c, 0xa102, 0xe0c2, 0x0142, 0xa200, 0xae20, 0x2a87,
+	0xe042, 0xe0c2, 0x014e, 0xe42e, 0x2889, 0x2a8e, 0x1a8c, 0xe423,
+	0x288d, 0xae0e, 0x4c8e, 0xa203, 0xb615, 0x3e8f, 0x2a8f, 0xae03,
+	0xa903, 0xae1d, 0xe056, 0xe0c1, 0x014b, 0xf7e9, 0xe0c2, 0x014d,
+	0xa202, 0xe0c2, 0x014a, 0x2a8d, 0xa003, 0x3e8d, 0x1a8b, 0xf065,
+	0x2a8e, 0xa003, 0x3e8e, 0xa201, 0x3e8d, 0xe42e, 0x2888, 0xf15a,
+	0x288e, 0x188c, 0xf042, 0xe41e, 0x2184, 0xf7be, 0xe0c0, 0x014b,
+	0xf7e8, 0xa204, 0xae1c, 0xe0c2, 0x014d, 0xa202, 0xe0c2, 0x014a,
+	0xe190, 0xe0c0, 0x014b, 0xf7e8, 0x2885, 0x3c89, 0xe42e, 0xe41e,
+	0x22a6, 0xe41e, 0x2344, 0xe41e, 0x0f66, 0xe41e, 0x2250, 0xe41e,
+	0x258e, 0xa200, 0x3c59, 0x3c52, 0xe41e, 0x2445, 0x2c59, 0x1c44,
+	0xe402, 0x224b, 0xe41e, 0x0b81, 0xf19a, 0xa102, 0xf1ca, 0xa108,
+	0xf154, 0xf19a, 0xa10a, 0xe40a, 0x223a, 0xa102, 0xe40a, 0x223a,
+	0xa102, 0xe40a, 0x222c, 0xa104, 0xe40a, 0x21ed, 0xa102, 0xa10a,
+	0xe40a, 0x21f2, 0xa002, 0xe404, 0x223f, 0xe41e, 0x094c, 0xf63e,
+	0x2c44, 0x3c52, 0xe41e, 0x0985, 0x284e, 0xe01a, 0x2a92, 0xe01b,
+	0xe05a, 0xe408, 0x223f, 0x284f, 0x1893, 0xe408, 0x223f, 0xe41e,
+	0x0bd4, 0xe41e, 0x23c4, 0xf4fa, 0x2894, 0xf07a, 0x2c44, 0x3c0d,
+	0xe41e, 0x248c, 0xe40e, 0x2247, 0xe41e, 0x0bf1, 0x284e, 0x3c92,
+	0x284f, 0x3c93, 0xe41e, 0x0d77, 0xe40a, 0x21d2, 0xa201, 0x3e94,
+	0x2c52, 0x3c0d, 0x1c59, 0xe404, 0x21d2, 0xe410, 0x248c, 0x2c52,
+	0x1c44, 0xe402, 0x224b, 0xe41e, 0x05c8, 0xf05a, 0xe41e, 0x05ed,
+	0xe40e, 0x224b, 0xe40e, 0x21cc, 0xe41e, 0x0985, 0xba0e, 0xe002,
+	0x00ff, 0xf058, 0xba4e, 0xe41e, 0x0ba5, 0xf798, 0xe41e, 0x0ce4,
+	0xe40e, 0x21d2, 0xe41e, 0x08b8, 0xf03a, 0xe41e, 0x01db, 0x2c59,
+	0x1c44, 0xe402, 0x2247, 0x2c44, 0x3c0d, 0xe41e, 0x248c, 0x2892,
+	0x3c4e, 0x2893, 0x3c4f, 0xe41e, 0x2652, 0xcbcc, 0xf7f8, 0xe42e,
+	0x2822, 0xae02, 0x4c37, 0xae0a, 0x2a36, 0xa83f, 0xe056, 0xae0a,
+	0x2a32, 0xa83f, 0xe056, 0xae02, 0x4c1d, 0xae02, 0x4c2d, 0xae02,
+	0x4c43, 0xcf80, 0x284e, 0xe01a, 0xae02, 0x4c1b, 0xae02, 0x4c1d,
+	0xae02, 0x4c43, 0xcfc2, 0x2857, 0xa102, 0xae02, 0x4c34, 0xae02,
+	0x4c3f, 0xae02, 0x4c42, 0xae02, 0x4c43, 0xcf00, 0xd1d3, 0x000b,
+	0xd185, 0x0001, 0x246e, 0x4c6f, 0xcfc6, 0xd1e5, 0x0001, 0xc420,
+	0xe161, 0x0201, 0xa200, 0xd022, 0x000f, 0xe184, 0x2289, 0x2b31,
+	0xae02, 0xb42a, 0xcfe8, 0x2072, 0x4c73, 0xcfea, 0x2074, 0x4c75,
+	0xcfec, 0x2076, 0x4c77, 0xcfee, 0xe004, 0x0060, 0xcbcf, 0xa803,
+	0xf03b, 0xe004, 0x0070, 0xce30, 0xe161, 0x0260, 0xd022, 0x001f,
+	0xe184, 0x22a4, 0x2111, 0x4d11, 0xce32, 0xe42e, 0xa200, 0xe161,
+	0x07f6, 0xc707, 0x3d11, 0x2867, 0x4c68, 0xf028, 0xe42e, 0xe161,
+	0x07f6, 0xa20e, 0x3c00, 0x2867, 0xf39a, 0x2869, 0x5c00, 0xa802,
+	0xf108, 0x2a00, 0xa10f, 0xf049, 0xa202, 0x3d11, 0xf17e, 0x2a00,
+	0xa109, 0xf049, 0xa204, 0x3d11, 0xf11e, 0xa20a, 0x3d11, 0xf0ee,
+	0x286b, 0x5c00, 0xa802, 0xf08a, 0x2800, 0xa10a, 0xa205, 0xf024,
+	0xa203, 0x3f11, 0xf03e, 0xa206, 0x3d11, 0x2800, 0xa102, 0x3c00,
+	0xa102, 0xf5c8, 0x2869, 0xe00c, 0x00ff, 0x2a6b, 0xe056, 0x5c00,
+	0xa802, 0xf06a, 0xa203, 0x2800, 0xb655, 0x3f11, 0xf03e, 0xa206,
+	0x3d11, 0x2800, 0xa102, 0x3c00, 0xf6ea, 0xe161, 0x07f6, 0xa20e,
+	0x3c00, 0x2868, 0xe42a, 0x286a, 0x5c00, 0xa802, 0xf188, 0x2800,
+	0xa10e, 0xf088, 0x2a67, 0xf03b, 0x8111, 0xf1e9, 0xa202, 0x3d11,
+	0xf1be, 0x2a00, 0xa109, 0xf089, 0x2a67, 0xf03b, 0x8111, 0xf149,
+	0xa204, 0x3d11, 0xf11e, 0xa20a, 0x3d11, 0xf0ee, 0x286c, 0x5c00,
+	0xa802, 0xf08a, 0x2800, 0xa10a, 0xa205, 0xf024, 0xa203, 0x3f11,
+	0xf03e, 0xa208, 0x3d11, 0x2800, 0xa102, 0x3c00, 0xa102, 0xf548,
+	0x286a, 0x5c00, 0x4c67, 0xa802, 0xf068, 0xa203, 0x2800, 0xb655,
+	0x3f11, 0xf16e, 0x286c, 0xe00c, 0x00ff, 0x2a6a, 0xe052, 0x5c00,
+	0xa802, 0xf0c8, 0x286a, 0x5c00, 0xa802, 0xf06a, 0xa203, 0x2800,
+	0xb655, 0x3f11, 0xf05e, 0x8111, 0xf03e, 0xa208, 0x3d11, 0x2800,
+	0xa102, 0x3c00, 0xf5ea, 0xe42e, 0xa202, 0xe0c2, 0x013c, 0xa200,
+	0x3c00, 0x3c01, 0xe161, 0x07f6, 0xe162, 0x04c8, 0x2911, 0xa104,
+	0xf066, 0xa106, 0xe40a, 0x238e, 0xa004, 0xf112, 0xa004, 0xae06,
+	0x3c04, 0x2800, 0xa10c, 0xf064, 0x2804, 0xae04, 0xe000, 0x0018,
+	0x3c04, 0xe004, 0x0450, 0x0804, 0x3c04, 0xf29e, 0xa201, 0x3e02,
+	0xa211, 0x3e03, 0xf04a, 0xe005, 0x00e0, 0x3e02, 0x2800, 0x2a00,
+	0xae09, 0xa10c, 0xf05a, 0xa102, 0xf058, 0xe005, 0x00a0, 0xa240,
+	0x3c03, 0x0a02, 0x3e02, 0xe0c0, 0x0041, 0xe005, 0x0034, 0xae11,
+	0xe042, 0x0802, 0xce20, 0xd111, 0x0600, 0x2803, 0xce24, 0xd113,
+	0x0003, 0xca28, 0xf7f8, 0xe004, 0x0600, 0x3c04, 0x2800, 0xa10c,
+	0xa20f, 0xf024, 0xa23f, 0xcc45, 0x2804, 0xe096, 0xe184, 0x23a8,
+	0x2912, 0x0801, 0xe0c2, 0x013e, 0x2b03, 0xaf11, 0xe0c3, 0x013f,
+	0x2912, 0x0801, 0xe0c2, 0x013e, 0x2b13, 0xe009, 0x00ff, 0xe0c3,
+	0x013f, 0xe162, 0x04c8, 0x2a01, 0xe001, 0x0010, 0x3e01, 0x2800,
+	0xa002, 0x3c00, 0xa10c, 0xe404, 0x234e, 0xe162, 0x04d8, 0xe40a,
+	0x234e, 0xe001, 0x0030, 0x3e01, 0xa104, 0xe408, 0x234e, 0xe16a,
+	0xa200, 0xe0c2, 0x013c, 0xe42e, 0xa200, 0x3c94, 0xe41e, 0x0c9b,
+	0xe40d, 0x2442, 0x2a43, 0xe419, 0x0e84, 0x1c44, 0xe402, 0x2442,
+	0xbc12, 0xe40d, 0x2442, 0xa10a, 0xb4a8, 0xa104, 0xe400, 0x2442,
+	0xbdfe, 0xe40d, 0x2442, 0x1829, 0xf03a, 0xa202, 0x3c94, 0x7413,
+	0x1839, 0xf03a, 0xa202, 0x3c94, 0x281b, 0xf0d8, 0xba40, 0x183f,
+	0xf03a, 0xa202, 0x3c94, 0x283f, 0xf06a, 0xba40, 0x1842, 0xf03a,
+	0xa202, 0x3c94, 0x284f, 0xf09a, 0xe41e, 0x0c9b, 0xe40d, 0x2442,
+	0x1c45, 0xf03a, 0xa202, 0x3c94, 0x2816, 0xa102, 0xf034, 0xf1da,
+	0xf3ae, 0x7417, 0xe160, 0x0903, 0x1d00, 0xf03a, 0xa202, 0x3c94,
+	0x283f, 0xe016, 0x442a, 0xf2fa, 0xe41e, 0x0cb5, 0xf34d, 0xe161,
+	0x0904, 0xe162, 0x0905, 0x1101, 0x1d02, 0xf03a, 0xa202, 0x3c94,
+	0xf22e, 0xe418, 0x0cb5, 0xf1fe, 0x2818, 0xf1d8, 0xe41e, 0x0cb5,
+	0xf22d, 0xe163, 0x0903, 0xe164, 0x0904, 0x1103, 0x1d04, 0xf03a,
+	0xa202, 0x3c94, 0x283f, 0xe016, 0x442a, 0xf0da, 0xe41e, 0x0cb5,
+	0xf12d, 0xe165, 0x0905, 0xe166, 0x0906, 0x1105, 0x1d06, 0xf03a,
+	0xa202, 0x3c94, 0xe41e, 0x0c1d, 0xae06, 0xc873, 0xe046, 0xf034,
+	0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0xa200, 0xe41e, 0x0c2a,
+	0xe41e, 0x0c26, 0xf0c8, 0xa202, 0xe41e, 0x08da, 0xe41e, 0x0c2a,
+	0xe41e, 0x08e2, 0xd036, 0x00ff, 0xd037, 0x0080, 0xe16a, 0x2c52,
+	0x3c59, 0xa200, 0x3c0c, 0xe41e, 0x24a3, 0x282d, 0xf138, 0x2c59,
+	0x1c44, 0xf0d2, 0xe41e, 0x24ea, 0xf1ed, 0x2843, 0xe418, 0x24ea,
+	0xf1ad, 0xcb86, 0xa102, 0xf740, 0xc894, 0xf728, 0xe41e, 0x0ce4,
+	0xe42e, 0xe41e, 0x24d6, 0x2c59, 0x1c44, 0xf0a2, 0xe41e, 0x24ea,
+	0xf0ad, 0x2843, 0xe418, 0x24ea, 0xf06d, 0xbb60, 0xf75a, 0xe41e,
+	0x0ce6, 0xe42e, 0xe16a, 0xe41e, 0x0b81, 0xa116, 0xe428, 0xe41e,
+	0x08b8, 0xe418, 0x01db, 0xe42e, 0x284f, 0xe016, 0x3c38, 0xa202,
+	0x3c0c, 0xe41e, 0x24a3, 0xa200, 0x3c0c, 0x2c59, 0x180d, 0xf0b2,
+	0xe41e, 0x252a, 0x2843, 0xe418, 0x252a, 0x2c53, 0xa002, 0x0843,
+	0x3c53, 0xf74e, 0xe42e, 0x2832, 0x1836, 0xe01a, 0xae04, 0x4c4b,
+	0xae0a, 0x4c4c, 0xae0a, 0x4c4d, 0xcf30, 0x2849, 0xae0a, 0x4c48,
+	0xae04, 0x4c38, 0xcf82, 0xd1c3, 0x0000, 0x284a, 0xcf96, 0x2849,
+	0xae08, 0x4c48, 0xae02, 0x4c7a, 0xae02, 0x4c79, 0xae02, 0x4c78,
+	0xae02, 0x4c46, 0xae04, 0x4c38, 0xcfc4, 0x885e, 0x01fa, 0x2470,
+	0x4c71, 0xcfc8, 0x280c, 0xf03a, 0x2838, 0xf03a, 0xd188, 0x0001,
+	0x2838, 0xa104, 0xe428, 0xd1e5, 0x0002, 0xe42e, 0xc868, 0xa80e,
+	0x3c9e, 0x749e, 0xe004, 0x01fe, 0xcc86, 0xba50, 0xcc88, 0x2838,
+	0xe01a, 0x0847, 0xae0c, 0x4c4a, 0xcc82, 0xd040, 0x0003, 0xc884,
+	0xf7f8, 0xe42e, 0xd185, 0x0002, 0xd1d0, 0x003f, 0xe190, 0xe180,
+	0xe41e, 0x0c2e, 0xe418, 0x0c8e, 0xe181, 0xcba0, 0xa810, 0xcba3,
+	0xe409, 0x2520, 0xf7b8, 0xe41e, 0x260a, 0xcbe0, 0xf7f8, 0x285a,
+	0xe41a, 0x2631, 0xcba0, 0xcba3, 0xe409, 0x2520, 0xf7c8, 0xd186,
+	0x0001, 0xd185, 0x0004, 0xe41e, 0x2648, 0xcb06, 0x3c59, 0xcb8a,
+	0xaf04, 0x442d, 0xf08a, 0xe004, 0x01fe, 0xcc86, 0xba50, 0xcc88,
+	0xd040, 0x0001, 0xe41e, 0x0c1d, 0xae06, 0xc873, 0xe046, 0xe422,
+	0xd1d0, 0x0000, 0xd1d1, 0x0000, 0xcb1c, 0xf7f8, 0xcbe0, 0xf7f8,
+	0xe16b, 0xe42e, 0xd185, 0x0002, 0xd186, 0x0000, 0xd1c2, 0x0001,
+	0xd1c5, 0x0000, 0xd1c4, 0x0000, 0xd1d0, 0x000e, 0xcba0, 0xf7f8,
+	0x2054, 0x4c55, 0xf098, 0xd1c2, 0x0000, 0xd1c5, 0x0003, 0xd1c4,
+	0x0003, 0xd1c8, 0x0000, 0xd1d0, 0x0020, 0xe41e, 0x260a, 0xa200,
+	0xe0c2, 0x012a, 0xcbe0, 0xf7f8, 0x285a, 0xe41a, 0x2631, 0xcba0,
+	0xf7f8, 0xd186, 0x0001, 0xd185, 0x0004, 0xe41e, 0x2648, 0xcb06,
+	0x3c59, 0xe42e, 0xa200, 0xe0c2, 0x0100, 0xe0c2, 0x013d, 0xe0c2,
+	0x0128, 0xcc8e, 0x2a88, 0xb692, 0xae08, 0xa91c, 0xe0c2, 0x017c,
+	0xa218, 0xe0c2, 0x017d, 0xa200, 0xe41e, 0x20a3, 0x2a22, 0xe017,
+	0xae09, 0xe056, 0xa203, 0xae11, 0xe056, 0xe0c2, 0x0213, 0xa200,
+	0xe0c2, 0x0215, 0xa202, 0xe0c2, 0x0210, 0x2057, 0x4c58, 0xae08,
+	0xe0c2, 0x0101, 0xe0c2, 0x0205, 0xa200, 0xe41e, 0x20a3, 0x2a22,
+	0xe017, 0xae07, 0xe056, 0xe0c2, 0x0102, 0xe42e, 0xe0c0, 0x0050,
+	0xe049, 0xe008, 0x007f, 0x3c08, 0xaf11, 0xe009, 0x007f, 0x3e09,
+	0x4608, 0x3e08, 0xa200, 0x2a08, 0xa803, 0xf03b, 0xe00a, 0x0002,
+	0x2a08, 0xa805, 0xf02b, 0xa912, 0x2a08, 0xa809, 0xf02b, 0xa940,
+	0x2a08, 0xa811, 0xf02b, 0xa980, 0xe0c2, 0x040c, 0xe0c1, 0x0046,
+	0xe004, 0x0002, 0xae10, 0xe042, 0x2a09, 0xa803, 0xf05b, 0xe161,
+	0x05cb, 0x2111, 0x4d11, 0xcf0e, 0xe0c1, 0x0046, 0xe004, 0x004a,
+	0xae10, 0xe042, 0x2a09, 0xa805, 0xf05b, 0xe161, 0x05cd, 0x2111,
+	0x4d11, 0xe0c2, 0x0103, 0xe0c1, 0x0046, 0xe004, 0x007a, 0xae10,
+	0xe042, 0x2a09, 0xa809, 0xf05b, 0xe161, 0x05cf, 0x2111, 0x4d11,
+	0xe0c2, 0x0211, 0xe0c1, 0x0046, 0xe004, 0x007a, 0xe000, 0x0040,
+	0xae10, 0xe042, 0x2a09, 0xa811, 0xf05b, 0xe161, 0x05d1, 0x2111,
+	0x4d11, 0xe0c2, 0x0212, 0x2843, 0xae02, 0x4c3f, 0xae02, 0x4c42,
+	0xe0c2, 0x0104, 0xe0c2, 0x0204, 0xa200, 0xe0c2, 0x0208, 0xe41e,
+	0x2656, 0xa20e, 0xe0c2, 0x0312, 0xe0c0, 0x0414, 0xe418, 0x018c,
+	0xe0c0, 0x0414, 0xe41a, 0x267f, 0xe41e, 0x0274, 0xa202, 0xe0c2,
+	0x0106, 0xe42e, 0xcb02, 0xaf02, 0xe0c2, 0x0113, 0xe0c2, 0x030d,
+	0xcb15, 0xae03, 0xe056, 0xe0c2, 0x022b, 0xcb94, 0xe0c2, 0x0115,
+	0xcba4, 0xe0c2, 0x012a, 0xcb8a, 0xe0c2, 0x0114, 0xa802, 0x3c5a,
+	0xe42a, 0xcb14, 0xae0a, 0xcb19, 0xe056, 0xe0c2, 0x0120, 0xcb8c,
+	0xe0c2, 0x0121, 0xcb8e, 0xe0c2, 0x0122, 0xcb90, 0xe0c2, 0x0123,
+	0xe42e, 0xcbd0, 0xe0c2, 0x030c, 0xcbd2, 0xe0c2, 0x0309, 0xcbd8,
+	0xe0c2, 0x030a, 0xcbda, 0xe0c2, 0x030b, 0x285e, 0xe0c2, 0x0320,
+	0xe42a, 0x285f, 0xe0c2, 0x0321, 0xcbf6, 0xe0c2, 0x0322, 0xe42e,
+	0xe0c0, 0x0111, 0xf7e8, 0xa202, 0xe0c2, 0x0110, 0x2888, 0xe418,
+	0x2184, 0xe42e, 0xe0c0, 0x0111, 0xf7e8, 0xe42e, 0xa202, 0xe0c2,
+	0x0302, 0xd022, 0x000f, 0xe163, 0x0380, 0x2883, 0xb608, 0xe184,
+	0x2664, 0x9f03, 0x8113, 0x8113, 0x8113, 0x2819, 0xf15a, 0x2ad6,
+	0xb5f6, 0xcc44, 0xe160, 0x0004, 0xe161, 0x0203, 0xe163, 0x0380,
+	0xe184, 0x2679, 0x2931, 0xf022, 0x2883, 0xb608, 0x9f03, 0x8113,
+	0x8113, 0x8113, 0xe190, 0xa200, 0xe0c2, 0x0302, 0xe42e, 0xe167,
+	0x01a0, 0x2317, 0x4f17, 0xe0c3, 0x0152, 0x2b17, 0xe009, 0x00ff,
+	0xae21, 0x4f07, 0xe0c3, 0x0153, 0xe0c1, 0x0101, 0xe0c3, 0x015d,
+	0xe162, 0x02b0, 0x2912, 0xaf02, 0x3c0a, 0x2912, 0xaf02, 0x3c0b,
+	0x2838, 0xa104, 0xf068, 0xe162, 0x02d0, 0x2912, 0xaf02, 0x3c0b,
+	0x280a, 0x180b, 0xf0d8, 0xe162, 0x02b0, 0xd022, 0x001f, 0xe184,
+	0x26ae, 0x2912, 0xaf02, 0x3c0b, 0x180a, 0xf028, 0xe190, 0x280b,
+	0xae02, 0xe41e, 0x0faa, 0xe049, 0xae11, 0x280a, 0xae02, 0xe41e,
+	0x0faa, 0xe055, 0xae21, 0xe167, 0x01a2, 0x2907, 0xaf10, 0xe008,
+	0x001f, 0xe055, 0xe0c3, 0x015c, 0xa202, 0xe0c2, 0x0150, 0xe0c0,
+	0x0150, 0xf7ea, 0xa200, 0xe0c2, 0x0150, 0xe0c0, 0x0151, 0xf7e8,
+	0xe42e, 0xf044, 0xe41e, 0x2080, 0xe42e, 0xa200, 0xe42e, 0xe165,
+	0x07e8, 0x284f, 0x3d15, 0x284e, 0x3d15, 0x2838, 0x3d15, 0x287e,
+	0x3d15, 0xe42e, 0xe165, 0x0620, 0xa200, 0xe188, 0x001f, 0x3d15,
+	0xe41e, 0x277b, 0xd022, 0x0007, 0xe184, 0x26f0, 0xe41e, 0x275e,
+	0xe190, 0xe41e, 0x277b, 0xe165, 0x0620, 0xa2fe, 0x3d15, 0xa206,
+	0x3d15, 0xe41e, 0x275e, 0xe42e, 0x3c03, 0x18d8, 0xe42a, 0x2803,
+	0xf03a, 0x2829, 0x3cd9, 0x2803, 0x3cd8, 0xe41e, 0x2732, 0xe164,
+	0x0200, 0xe004, 0x00b0, 0xe41e, 0x2742, 0xe164, 0x0080, 0xe41e,
+	0x274a, 0xe164, 0x0082, 0xe41e, 0x274a, 0xe164, 0x0012, 0xe41e,
+	0x274a, 0xe164, 0x003a, 0xe004, 0x0005, 0xe41e, 0x2742, 0xe164,
+	0x0900, 0xe004, 0x000c, 0xe41e, 0x2742, 0xe41e, 0x273d, 0xa2fe,
+	0x3c29, 0x3c10, 0x2803, 0xe428, 0x3cd6, 0x28d9, 0x3c29, 0xe41e,
+	0x1b3f, 0xe42e, 0xe41e, 0x277b, 0xa200, 0x3c02, 0xe41e, 0x276f,
+	0xe165, 0x0620, 0xe166, 0x0600, 0xe42e, 0x2802, 0xe42a, 0xe41e,
+	0x275e, 0xe42e, 0xa102, 0xcc44, 0xe184, 0x2748, 0xe41e, 0x274a,
+	0xe190, 0xe42e, 0x2904, 0x3d15, 0x2916, 0x3d14, 0x2802, 0xa002,
+	0x3c02, 0xa140, 0xe424, 0xe41e, 0x275e, 0xe41e, 0x276f, 0xe165,
+	0x0620, 0xe166, 0x0600, 0xa200, 0x3c02, 0xe42e, 0x2400, 0x4c01,
+	0xce20, 0xd111, 0x0620, 0xd112, 0x0020, 0xd113, 0x0002, 0xca28,
+	0xf7f8, 0x2400, 0x4c01, 0xa080, 0x3400, 0x3c01, 0xe42e, 0x2400,
+	0x4c01, 0xce20, 0xd111, 0x0600, 0xd112, 0x0020, 0xd113, 0x0003,
+	0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0041, 0xe005, 0x0037, 0xae11,
+	0xe042, 0x3400, 0x3c01, 0xe42e, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe40e, 0x0020, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x0330, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x034a, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x003a, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058,
+	0xa200, 0xe0c2, 0x005a, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xa2fe,
+	0x3cee, 0x3cef, 0x3cec, 0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d,
+	0xce00, 0xf33e, 0xe41e, 0x0164, 0xe09e, 0xa202, 0xae3e, 0x9f07,
+	0xe0c0, 0x005c, 0xe0c1, 0x0059, 0x3eed, 0xa203, 0x5aed, 0xe052,
+	0xf08a, 0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00,
+	0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2, 0x0008, 0xf00e,
+	0x28ee, 0xe412, 0x013d, 0xe190, 0xe0c0, 0x005c, 0xe0c1, 0x0059,
+	0x3eed, 0xa203, 0x5aed, 0xe052, 0xf08a, 0xe0c1, 0x005d, 0xe055,
+	0xe0c3, 0x005d, 0xa202, 0xce00, 0xe0c0, 0x004a, 0xf08a, 0xe41e,
+	0x019c, 0xe408, 0x005c, 0xe40e, 0x0058, 0xe190, 0xe0c0, 0x043d,
+	0xa1ee, 0xf7d8, 0xe004, 0x0060, 0xe0c2, 0x0009, 0xa200, 0xe0c2,
+	0x0009, 0xe0c0, 0x000d, 0xf7e8, 0xe41e, 0x00b2, 0xe41e, 0x00e2,
+	0xe41e, 0x012c, 0xd071, 0x242a, 0xe181, 0xe41e, 0x0164, 0xe09e,
+	0xa202, 0x9f07, 0xe0c0, 0x0049, 0xe0c1, 0x005b, 0xa111, 0xf033,
+	0xe0c0, 0x0048, 0xe0c2, 0x0047, 0xe0c0, 0x0059, 0xae02, 0xe000,
+	0x0330, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a, 0xe008, 0xffff,
+	0x3cee, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11, 0xe056, 0x3cef,
+	0xe40e, 0x0058, 0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2,
+	0x0008, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xe0c0, 0x0059, 0xf7ea,
+	0xa11e, 0xf198, 0xa202, 0xe0c2, 0x0058, 0xe004, 0xca20, 0xae20,
+	0xe005, 0x210a, 0xe056, 0xe0c2, 0x0070, 0xe004, 0x0000, 0xae20,
+	0xe00a, 0x9cea, 0xe0c2, 0x0071, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+	0x0058, 0xf64e, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058, 0xd027,
+	0x0001, 0xe42e, 0xa200, 0xe0c1, 0x005b, 0xf21b, 0xa23c, 0xa103,
+	0xf37b, 0xa24c, 0xa103, 0xf34b, 0xa258, 0xa103, 0xf1db, 0xe004,
+	0x003a, 0xa103, 0xf2db, 0xe004, 0x003f, 0xa103, 0xf29b, 0xe004,
+	0x0045, 0xa103, 0xf25b, 0xa103, 0xf14b, 0xe004, 0x0063, 0xa103,
+	0xf1ab, 0xe004, 0x006a, 0xa107, 0xf1bb, 0xa200, 0xe0c1, 0x005e,
+	0xf17b, 0xa028, 0xf15e, 0xe0c1, 0x005e, 0xf12b, 0xa010, 0xf10e,
+	0xe004, 0x0049, 0xe0c1, 0x005e, 0xf0bb, 0xa010, 0xa103, 0xf08b,
+	0xa010, 0xf06e, 0xe0c1, 0x005e, 0xf03b, 0xe004, 0x0074, 0xae16,
+	0xe0c1, 0x0040, 0xe041, 0xce21, 0xd111, 0x0000, 0xd112, 0x2800,
+	0xd113, 0x000b, 0xe1e1, 0xe42e, 0xe41e, 0x023a, 0xe0c0, 0x0059,
+	0xa102, 0xe42a, 0xe0c0, 0x005b, 0xa810, 0xf058, 0xa206, 0xe41e,
+	0x0153, 0xe42e, 0xe004, 0x0350, 0xe67c, 0xe0c0, 0x005b, 0xa810,
+	0xf058, 0xa204, 0xe41e, 0x0153, 0xe42e, 0xe004, 0x0352, 0xe67c,
+	0xa200, 0xc401, 0xe188, 0x00eb, 0x3d11, 0xe161, 0x00f2, 0xe188,
+	0x0b0d, 0x3d11, 0xe42e, 0x3cec, 0xe0c0, 0x0041, 0xe005, 0x0000,
+	0xae11, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0c00, 0x88ec,
+	0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0059, 0xa106, 0xf048,
+	0xe004, 0x0076, 0xe42e, 0xe0c0, 0x0059, 0xa10c, 0xf038, 0xe004,
+	0x0071, 0xe004, 0x0070, 0xe42e, 0xe0c0, 0x006b, 0xe167, 0x01a0,
+	0x3d07, 0xe0c0, 0x0414, 0xe428, 0xe0c1, 0x0044, 0xa809, 0xae33,
+	0xe0c0, 0x006a, 0xe167, 0x01a0, 0x3517, 0x3d17, 0xe0c0, 0x006b,
+	0xe056, 0x3517, 0x3d07, 0xe42e, 0xe167, 0x01a0, 0x2907, 0xe0c2,
+	0x0151, 0xa204, 0xe0c2, 0x0150, 0xe0c0, 0x0150, 0xa804, 0xf7da,
+	0xa208, 0xe0c2, 0x0150, 0xe42e, 0xe0c0, 0x004a, 0xe42a, 0xe0c0,
+	0x005b, 0xa110, 0xf142, 0xe0c0, 0x0059, 0xa102, 0xe41a, 0x01be,
+	0xe0c0, 0x0059, 0xa106, 0xe41a, 0x01cb, 0xe0c0, 0x0047, 0xe0c2,
+	0x0048, 0xa200, 0xe0c2, 0x004a, 0xa202, 0xe42e, 0xe0c0, 0x0047,
+	0xe0c2, 0x0049, 0xa200, 0xe0c2, 0x004a, 0xe42e, 0xe0c0, 0x004a,
+	0xa802, 0xa23e, 0x3cf0, 0xa202, 0x58f0, 0xe0c2, 0x0078, 0xa220,
+	0xe0c2, 0x0070, 0xe42e, 0xe0c0, 0x004a, 0xa802, 0xa220, 0xe0c2,
+	0x0076, 0xa200, 0xe0c2, 0x0072, 0xa2fc, 0xe0c2, 0x0077, 0xa2fa,
+	0xe0c2, 0x0071, 0xe42e, 0xe0c0, 0x0045, 0xaf04, 0xa80e, 0xa104,
+	0xe428, 0xa202, 0xe0c2, 0x004a, 0xe0c0, 0x0111, 0xf7e8, 0xca28,
+	0xf7f8, 0xca48, 0xa802, 0xf7e8, 0xa208, 0xae14, 0xa102, 0xe190,
+	0xf7e2, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xe0c0, 0x041f, 0xf7e8,
+	0xa200, 0xe0c2, 0x041c, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xe004,
+	0x0078, 0xe0c2, 0x0009, 0xa200, 0xe0c2, 0x0009, 0xe0c0, 0x000d,
+	0xf7e8, 0xe42e, 0xc001, 0x3443, 0x3c42, 0xc000, 0xe42e, 0xc001,
+	0x2c43, 0x2e42, 0xc000, 0xe42a, 0x1ceb, 0xf0b4, 0xe04a, 0xaf10,
+	0x1855, 0xf074, 0xe009, 0x00ff, 0x1a56, 0xf034, 0xa202, 0xe42e,
+	0xa2fe, 0xe42e, 0xe41e, 0x023a, 0xd160, 0x0620, 0xe004, 0x0019,
+	0xae18, 0xcec0, 0xe42e, 0xe41e, 0x024f, 0xe000, 0x0040, 0xce50,
+	0xa200, 0xd022, 0x00ff, 0xe184, 0x0236, 0xce52, 0xe190, 0xe41e,
+	0x0257, 0xe42e, 0xa204, 0xae22, 0xcc9e, 0xa200, 0xcc72, 0xcc8c,
+	0xcc8e, 0xe004, 0xa810, 0xae20, 0xe00a, 0x9322, 0xce4a, 0xd16f,
+	0x0003, 0xe190, 0xe190, 0xe190, 0xd16f, 0x0000, 0xe42e, 0xe004,
+	0x0030, 0xce50, 0xca50, 0xa802, 0xf7ea, 0xc000, 0xe42e, 0xe004,
+	0x0020, 0xce50, 0xe42e, 0xa200, 0xe0c2, 0x041c, 0xe42e, 0xe41e,
+	0x02bb, 0xe42a, 0xe0c0, 0x0061, 0xe008, 0x001f, 0xe00a, 0x0100,
+	0xe0c2, 0x041c, 0xe41e, 0x02f1, 0xe41e, 0x032b, 0xae12, 0xe0c2,
+	0x041e, 0xe41e, 0x031b, 0xe42e, 0xe41e, 0x02df, 0xe42a, 0xe0c0,
+	0x041f, 0xf7e8, 0xe0c0, 0x0210, 0xa804, 0xf118, 0xe0c0, 0x0215,
+	0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0216, 0xf0be, 0xe0c0, 0x0213,
+	0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0214, 0xf03e, 0xe0c0, 0x020b,
+	0xe00a, 0x0100, 0xe0c2, 0x041c, 0xe41e, 0x02f1, 0xe41e, 0x032b,
+	0xae12, 0xe0c1, 0x0210, 0xa803, 0xae15, 0xe056, 0xe0c1, 0x0204,
+	0xaf0b, 0xa87f, 0xae07, 0xe056, 0xe0c1, 0x0204, 0xa80f, 0xe056,
+	0xe0c2, 0x041e, 0xe41e, 0x031b, 0xe42e, 0xe0c0, 0x041f, 0xf7e8,
+	0xe0c0, 0x041f, 0xf7e8, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xa200,
+	0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xa203, 0xae19, 0xe052,
+	0xf1da, 0xe0c0, 0x0060, 0xaf08, 0xa806, 0xf18a, 0xe0c0, 0x0060,
+	0xa81e, 0xe016, 0xe0c1, 0x0060, 0xa821, 0xe017, 0xe056, 0xf0ea,
+	0xe0c0, 0x0044, 0xaf12, 0xa806, 0xe016, 0xe0c1, 0x0044, 0xaf17,
+	0xa803, 0xe056, 0xf03a, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xe0c0,
+	0x0044, 0xa203, 0xae19, 0xe052, 0xf0ba, 0xe41e, 0x02bb, 0xf088,
+	0xe0c0, 0x0044, 0xaf12, 0xa806, 0xf038, 0xa202, 0xe42e, 0xa200,
+	0xe42e, 0xe0c0, 0x041c, 0xe008, 0x00ff, 0xcca4, 0xc785, 0xe018,
+	0xe000, 0x0500, 0xa002, 0xae04, 0xe0c2, 0x041a, 0xa202, 0xe0c2,
+	0x0418, 0xe0c0, 0x0419, 0xf7ea, 0xa202, 0xe0c2, 0x0418, 0xe0c0,
+	0x0419, 0xf7ea, 0xe0c0, 0x041b, 0xaf20, 0xa01e, 0xaf08, 0xae28,
+	0xe0c1, 0x041b, 0xe009, 0xffff, 0xa01f, 0xaf09, 0xae09, 0xe056,
+	0xe0c2, 0x041d, 0xe42e, 0xe0c0, 0x041c, 0xe00a, 0x0200, 0xe0c2,
+	0x041c, 0xa228, 0xa102, 0xf7f0, 0xe0c0, 0x041c, 0xe00c, 0x0200,
+	0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xaf04, 0xa802, 0xe42e,
+	0xe40e, 0x0691, 0xe40e, 0x0354, 0xe40e, 0x0358, 0xe40e, 0x035c,
+	0xe40e, 0x0364, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x0368, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe41e, 0x036c, 0xe40e, 0x00a4,
+	0xe41e, 0x0379, 0xe40e, 0x00a4, 0xe41e, 0x025b, 0xe41e, 0x03c6,
+	0xe41e, 0x02ad, 0xe40e, 0x00a4, 0xe41e, 0x037b, 0xe40e, 0x00a4,
+	0xe41e, 0x0398, 0xe40e, 0x00a4, 0xe41e, 0x03e2, 0xe41e, 0x042c,
+	0xe41e, 0x086b, 0xe41e, 0x14ec, 0xe41e, 0x0bd4, 0xe41e, 0x03ff,
+	0xe42e, 0xa202, 0xe42e, 0xe41e, 0x0523, 0xe41e, 0x0174, 0xca28,
+	0xf7f8, 0xe0c0, 0x0042, 0xce20, 0xd111, 0x0800, 0xd112, 0x00c4,
+	0xd113, 0x0003, 0xca28, 0xf7f8, 0xe0c0, 0x0060, 0x3c98, 0xe0c0,
+	0x0061, 0x3cb4, 0xe41e, 0x0c09, 0xa200, 0xe0c2, 0x0054, 0xe42e,
+	0xe41e, 0x03b0, 0xe41e, 0x0c09, 0xa200, 0x3c91, 0x3c9e, 0x3c9f,
+	0x3ca0, 0x3ca1, 0xe161, 0x08c5, 0xe163, 0x08fc, 0x2513, 0x4d0b,
+	0xe0c1, 0x0054, 0xe052, 0xe0c2, 0x0054, 0x3511, 0x3d01, 0xe42e,
+	0xe162, 0x08d8, 0x2b02, 0xa811, 0xe163, 0x08fc, 0xa2fe, 0x3513,
+	0x3d0b, 0xf0cb, 0xe164, 0x08ce, 0xa203, 0x5b04, 0xe165, 0x08c5,
+	0x2115, 0x4d05, 0xe056, 0x3513, 0x3d0b, 0xe42e, 0xe41e, 0x0441,
+	0xd14b, 0x0200, 0xe41e, 0x0608, 0xe41e, 0x08ac, 0x28db, 0xe408,
+	0x03dd, 0xe41e, 0x06a9, 0x28e0, 0xa104, 0xe41a, 0x0bad, 0xe41e,
+	0x07a0, 0xf048, 0x28e0, 0xa104, 0xf70a, 0xe41e, 0x049a, 0xe41e,
+	0x07f8, 0xe42e, 0xe41e, 0x023a, 0xe41e, 0x0148, 0xd130, 0x0001,
+	0xd03a, 0x0001, 0xd008, 0x0000, 0xd039, 0x0000, 0xd049, 0x0000,
+	0xd047, 0x0000, 0xe0c0, 0x0062, 0xaf02, 0x3089, 0xaf06, 0x3096,
+	0xaf02, 0x308a, 0xa2fe, 0x3c22, 0xe0c2, 0x0079, 0xe42e, 0xd049,
+	0x0000, 0xd047, 0x0000, 0x2016, 0x4c17, 0xe0c2, 0x0071, 0x2822,
+	0xe0c2, 0x007a, 0x2821, 0xe0c2, 0x0079, 0x2897, 0xe0c2, 0x0073,
+	0x2899, 0xe0c2, 0x0074, 0x281c, 0xae02, 0x4c18, 0xae02, 0x4c19,
+	0xae10, 0x4c11, 0xae10, 0x4c10, 0xe0c2, 0x007b, 0x281f, 0xae10,
+	0x4c20, 0xe0c2, 0x0072, 0x2893, 0xe016, 0xe0c2, 0x0070, 0x2893,
+	0x58f0, 0xe0c2, 0x0078, 0xe42e, 0xe0c0, 0x0040, 0xa23d, 0xae17,
+	0xe042, 0xe005, 0x1f00, 0xae03, 0xe042, 0xca29, 0xf7f9, 0xce20,
+	0xd111, 0x06f0, 0xd112, 0x0100, 0xd113, 0x0003, 0xca28, 0xf7f8,
+	0xe42e, 0xa200, 0x3cdc, 0xcc4a, 0xcc4c, 0x3cdb, 0xd130, 0x0001,
+	0xd03a, 0x0001, 0xd008, 0x0000, 0xe41e, 0x1a2c, 0xe41e, 0x1a64,
+	0x283d, 0xe41a, 0x025f, 0xe0c0, 0x0050, 0xe049, 0xe008, 0x007f,
+	0x3cb7, 0xaf11, 0xe009, 0x007f, 0x3eb8, 0x46b7, 0x3eb7, 0xa200,
+	0x2ab7, 0xa803, 0xf03b, 0xe00a, 0x0002, 0x2ab7, 0xa805, 0xf03b,
+	0xe00a, 0x0009, 0x2ab7, 0xa809, 0xf03b, 0xe00a, 0x0020, 0x2ab7,
+	0xa811, 0xf03b, 0xe00a, 0x0040, 0x2ab7, 0xa821, 0xf03b, 0xe00a,
+	0x0010, 0x2ab7, 0xa841, 0xf03b, 0xe00a, 0x0002, 0xe0c2, 0x040c,
+	0xa200, 0x3ca4, 0x3ca5, 0x3ca6, 0xe0c0, 0x0060, 0xe049, 0xa81f,
+	0x3ea6, 0xaf08, 0x30a5, 0xaf02, 0xa202, 0x3cde, 0xe0c0, 0x0065,
+	0xaf04, 0xa80e, 0x3cdf, 0xa200, 0x3ce0, 0xe41e, 0x050f, 0xe41e,
+	0x192e, 0xe42e, 0xd049, 0x0000, 0xd047, 0x0000, 0x20a0, 0x4ca1,
+	0xe0c2, 0x0070, 0x28e0, 0xe418, 0x0bad, 0x289c, 0xe000, 0x08ca,
+	0xe094, 0x2902, 0xe0c2, 0x0071, 0x2895, 0xe0c2, 0x0072, 0x2850,
+	0xae02, 0x4c4f, 0xae02, 0x4c4e, 0xae04, 0x4c4a, 0xae02, 0x4c19,
+	0xae1e, 0x4c4b, 0xae06, 0x4c4c, 0xe0c2, 0x0073, 0x2053, 0x4c54,
+	0xe0c2, 0x006f, 0x281f, 0xae10, 0x4c20, 0xe0c2, 0x007c, 0x2822,
+	0xe0c2, 0x007e, 0x2821, 0xe0c2, 0x007d, 0xa200, 0x2a9c, 0xae05,
+	0xe001, 0x08e4, 0xe095, 0x2b02, 0xaf07, 0xa80f, 0xe056, 0x2ae0,
+	0xb612, 0xe0c2, 0x0074, 0xa200, 0x28e0, 0xae04, 0xe0c2, 0x0075,
+	0x2894, 0xe016, 0x2adb, 0xae29, 0xe056, 0x2adb, 0xae21, 0xe056,
+	0xe0c2, 0x0076, 0xe162, 0x08c7, 0x2902, 0xb7e8, 0x2a4b, 0xa109,
+	0xb7d6, 0x2a94, 0xb7d2, 0xf0c4, 0xe162, 0x08d8, 0xe164, 0x08cf,
+	0x2b02, 0xaf05, 0xa807, 0xf04b, 0x2b04, 0xf025, 0x2904, 0x2ae0,
+	0xb7d2, 0xe0c2, 0x0077, 0xc84a, 0xc84d, 0xae20, 0xe056, 0xe0c2,
+	0x0053, 0xe41e, 0x0519, 0xe41e, 0x18e6, 0xe42e, 0xe42e, 0xe0c1,
+	0x0054, 0xe165, 0x08c5, 0x2115, 0x4d0d, 0xe052, 0x3515, 0x3d0d,
+	0xe42e, 0xe165, 0x08c3, 0x2115, 0x4d15, 0x2315, 0x4f15, 0xe056,
+	0xe0c2, 0x0054, 0xe42e, 0xe166, 0x0064, 0xe167, 0x08f0, 0xd022,
+	0x0003, 0xe184, 0x052d, 0x9e16, 0x3517, 0x3d17, 0xe167, 0x07dc,
+	0xd022, 0x0001, 0xe184, 0x0536, 0x9e16, 0x3517, 0x3d17, 0xe42e,
+	0xd148, 0x0040, 0xd144, 0x0000, 0xd145, 0x0000, 0xd168, 0x0000,
+	0xd14b, 0x0200, 0xe004, 0x0019, 0xae18, 0xcec0, 0xd14c, 0x000c,
+	0xca9a, 0xf7f8, 0xe42e, 0xcc44, 0xe184, 0x0554, 0xca9c, 0xe418,
+	0x0703, 0xcaa0, 0xca9b, 0xf7f9, 0xe190, 0xe42e, 0xa200, 0x3cd7,
+	0x3cd6, 0x3cd4, 0xe41e, 0x07a0, 0xf138, 0xe41e, 0x05aa, 0xe41e,
+	0x07a0, 0xf0e8, 0xe41e, 0x083e, 0xa206, 0xcaa3, 0xe009, 0x00ff,
+	0xb656, 0xe41e, 0x054b, 0x3c03, 0xe41e, 0x07a0, 0xf05a, 0xa214,
+	0x3cd3, 0xa200, 0xe42e, 0x2803, 0xaf0e, 0xf688, 0x2803, 0xa83e,
+	0x3cd3, 0xe41e, 0x0676, 0xe41e, 0x06b2, 0xa202, 0xe42e, 0xa200,
+	0x3cd7, 0x3cd6, 0x3cd4, 0xe41e, 0x07a0, 0xf198, 0xe41e, 0x05aa,
+	0xe41e, 0x07a0, 0xf148, 0xe41e, 0x083e, 0xcaa2, 0xe008, 0x00ff,
+	0x3c03, 0xe008, 0x007f, 0xa114, 0xf034, 0xa12a, 0xf056, 0xa202,
+	0xe41e, 0x054b, 0xf6ce, 0xe41e, 0x07a0, 0xf05a, 0xa214, 0x3cd3,
+	0xa200, 0xe42e, 0x2803, 0xaf0e, 0xf628, 0x2803, 0xa83e, 0x3cd3,
+	0xa202, 0xe42e, 0xd158, 0x0100, 0xe004, 0x00ff, 0xe014, 0xceb8,
+	0xd15d, 0x0000, 0xd15e, 0x0000, 0xd15f, 0x0000, 0xe004, 0x0019,
+	0xae18, 0xe00a, 0x0620, 0xcec0, 0xd157, 0x0000, 0xd14a, 0x0000,
+	0xd14c, 0x0003, 0xca9c, 0xe418, 0x0703, 0xca9a, 0xf7c8, 0xcaae,
+	0xa802, 0xf73a, 0xca9c, 0xe418, 0x0703, 0xa200, 0xe42e, 0x28d4,
+	0xe428, 0xe004, 0x0080, 0x2ac8, 0xb616, 0xce92, 0xd158, 0x0000,
+	0xe004, 0x01ff, 0xe014, 0xceb8, 0xd15d, 0x0000, 0xd15e, 0x0000,
+	0xd15f, 0x0000, 0xe004, 0x0019, 0xae18, 0xe00a, 0x0638, 0xcec0,
+	0xd161, 0x0003, 0xd14a, 0x0000, 0xd14c, 0x0003, 0xca9c, 0xe418,
+	0x0703, 0xca9a, 0xf7c8, 0xca9c, 0xf7a8, 0xca94, 0x3cd5, 0xca9e,
+	0x3cd4, 0x28d5, 0x00d7, 0x0cd6, 0x34d7, 0x3cd6, 0xcc90, 0xcc8c,
+	0x28d4, 0xcc92, 0xcc8e, 0xe428, 0x28c8, 0xe016, 0x3cc8, 0xe42e,
+	0xe0c0, 0x0059, 0xa102, 0xe40a, 0x0615, 0xa102, 0xe40a, 0x0670,
+	0xa102, 0xe40a, 0x0624, 0xe40e, 0x0670, 0xe0c0, 0x0060, 0x34b9,
+	0x3cba, 0x34bf, 0x3cc0, 0xe0c0, 0x0061, 0xae14, 0x34bb, 0x3cbc,
+	0x04b9, 0x0cba, 0x34bd, 0x3cbe, 0x28c7, 0xf13a, 0xe0c0, 0x0048,
+	0x34d1, 0x3cd2, 0x24d1, 0x4cd2, 0xe0c1, 0x0049, 0x36c1, 0x3ec2,
+	0x14c1, 0x1cc2, 0xe0c1, 0x0045, 0xaf05, 0xa803, 0xb611, 0x3ec7,
+	0xe0c0, 0x0048, 0xe008, 0x01ff, 0x3cc5, 0xe0c0, 0x0048, 0x34bf,
+	0xe008, 0xfe00, 0x3cc0, 0xe0c0, 0x0048, 0x34c3, 0x3cc4, 0xa200,
+	0xcc92, 0xcc8e, 0xe180, 0xe41e, 0x0676, 0xe41e, 0x0222, 0xd071,
+	0x202a, 0xe181, 0xa200, 0x3cc9, 0x283c, 0xa104, 0xf10a, 0xa200,
+	0x34d7, 0x3cd6, 0xcc72, 0xe41e, 0x06b2, 0x2cc5, 0xa102, 0xf034,
+	0xba4f, 0xf7de, 0xc872, 0xe41e, 0x0838, 0xf0be, 0xe41e, 0x0703,
+	0xe41e, 0x0538, 0x28c5, 0xa102, 0xe412, 0x054b, 0xa200, 0xceaa,
+	0xa202, 0x3cc9, 0xa202, 0xb61a, 0xe16a, 0xe42e, 0xd030, 0x0000,
+	0xd031, 0x0000, 0xd032, 0x0000, 0xd034, 0x0000, 0xd033, 0x0000,
+	0xd035, 0x0000, 0xd036, 0x00ff, 0xd037, 0x0000, 0xd038, 0x0000,
+	0xd039, 0x0000, 0xd04b, 0x0001, 0xd04c, 0x0000, 0xd149, 0x0000,
+	0xe42e, 0xc896, 0xf05a, 0xe41e, 0x06bf, 0x3cd9, 0xf058, 0xd04b,
+	0x0001, 0xa200, 0x3cd9, 0x28d8, 0xcc6e, 0xd04c, 0x0000, 0xe470,
+	0xa202, 0x3cd9, 0xe41e, 0x06bf, 0xcc96, 0xe42a, 0x28d8, 0xcc6e,
+	0xe42e, 0xc896, 0xe428, 0xd04b, 0x0001, 0x28d8, 0xcc6e, 0xd04c,
+	0x0000, 0xe42e, 0xa200, 0x3cc8, 0x3cd8, 0xe41e, 0x06bf, 0x3cd9,
+	0xd04b, 0x0001, 0x28d8, 0xcc6e, 0xe190, 0xe128, 0xe42e, 0x283c,
+	0xa104, 0xf04a, 0xe41e, 0x06ce, 0xf03e, 0xe41e, 0x05cf, 0xe004,
+	0x0080, 0x2ac8, 0xb616, 0x3cd8, 0xa200, 0xe42e, 0x28c7, 0xe428,
+	0xd027, 0x0000, 0xe41e, 0x0760, 0xd027, 0x0001, 0xca28, 0xf7f8,
+	0x24bf, 0x4cc0, 0xce20, 0x28c8, 0xae0e, 0xce22, 0xd112, 0x0080,
+	0xe0c0, 0x0043, 0xa806, 0xae02, 0xa022, 0xce26, 0xca28, 0xf7f8,
+	0x24bf, 0x4cc0, 0xe000, 0x0200, 0x34bf, 0x3cc0, 0x14bd, 0x1cbe,
+	0xf054, 0x24b9, 0x4cba, 0x34bf, 0x3cc0, 0xe41e, 0x07fa, 0x28c8,
+	0xe016, 0x3cc8, 0x28da, 0x00d7, 0x0cd6, 0x34d7, 0x3cd6, 0xcc8c,
+	0x28c7, 0xcc8e, 0xe42e, 0x28c7, 0xf1aa, 0xe41e, 0x024f, 0xe000,
+	0x0440, 0xce50, 0xe005, 0x010a, 0x28da, 0xa806, 0xa108, 0xe012,
+	0xa806, 0xae06, 0x3cfe, 0xe004, 0x010a, 0x58fe, 0xce52, 0xe41e,
+	0x0257, 0xd14e, 0x0000, 0xd144, 0x0000, 0xe42e, 0xd027, 0x0000,
+	0xe41e, 0x0760, 0xd027, 0x0001, 0x28da, 0xf25a, 0xca48, 0xa802,
+	0xf7e8, 0x24bf, 0x4cc0, 0xce40, 0xd121, 0x0000, 0xd122, 0x0040,
+	0xe0c0, 0x0043, 0xa806, 0xae02, 0xa032, 0xce46, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xca48, 0xa802, 0xf7e8, 0x24bf, 0x4cc0, 0xe000,
+	0x0200, 0x34bf, 0x3cc0, 0x14bd, 0x1cbe, 0xf054, 0x24b9, 0x4cba,
+	0x34bf, 0x3cc0, 0x28c7, 0xe418, 0x07b7, 0xe41e, 0x07fa, 0xd14e,
+	0x0000, 0xd144, 0x0000, 0xe42e, 0xe0c1, 0x0059, 0xa103, 0xa200,
+	0xb636, 0xe000, 0x001c, 0xe0c1, 0x0045, 0xe052, 0xe01a, 0xe42e,
+	0xe0c0, 0x0043, 0xa808, 0xf318, 0xa200, 0x3cc6, 0xe004, 0x0200,
+	0x3cda, 0xe41e, 0x0754, 0x3cc7, 0x24bf, 0x4cc0, 0xe0c1, 0x0049,
+	0x36d1, 0x3ed2, 0x26d1, 0x4ed2, 0xe045, 0xf033, 0x06bb, 0x0ebc,
+	0xe003, 0x0200, 0x28c7, 0xb602, 0x3cc7, 0xf173, 0xe001, 0x0200,
+	0x3eda, 0x28c7, 0xf128, 0x28c6, 0xf658, 0xe0c0, 0x005c, 0xe008,
+	0x4000, 0xf60a, 0xe0c0, 0x005d, 0xe00a, 0x4000, 0xe0c2, 0x005d,
+	0xa202, 0xce00, 0x3cc6, 0xf56e, 0x28da, 0x2ac7, 0xf039, 0xe004,
+	0x0200, 0x3cda, 0xe42e, 0xc868, 0xa80e, 0x3c00, 0x7400, 0xe42e,
+	0x28c7, 0xe42a, 0xe41e, 0x07fa, 0xe0c0, 0x0049, 0x34d1, 0x3cd2,
+	0x24d1, 0x4cd2, 0xe0c1, 0x0048, 0x36d1, 0x3ed2, 0x26d1, 0x4ed2,
+	0xe045, 0xa200, 0xb626, 0xe003, 0x0200, 0xb606, 0xe42e, 0xe41e,
+	0x024f, 0x28da, 0xe002, 0x0200, 0xe40a, 0x07f6, 0x28da, 0xa806,
+	0xf1fa, 0xa108, 0xe012, 0xae06, 0x3cfe, 0x28da, 0xaf04, 0xae20,
+	0xe000, 0x01c0, 0xce50, 0xe190, 0xca52, 0x5cfe, 0x58fe, 0x2ada,
+	0xa807, 0xae07, 0x3efe, 0xe005, 0x010a, 0x5efe, 0xe056, 0x2ada,
+	0xaf05, 0xae21, 0xe001, 0x0140, 0xce51, 0xe190, 0xce52, 0xe004,
+	0x01fc, 0x18da, 0xf022, 0xf13e, 0x28da, 0xa006, 0xaf04, 0xae20,
+	0xe000, 0x0440, 0xce50, 0x28da, 0xa806, 0xa108, 0xe012, 0xae06,
+	0xa83e, 0x3cfe, 0xe004, 0x010a, 0x58fe, 0xce52, 0xe40e, 0x0257,
+	0xe41e, 0x079b, 0x283c, 0xa104, 0xf1aa, 0xc872, 0xc001, 0x343b,
+	0x3c3c, 0xc000, 0x26d7, 0x4ed6, 0xae07, 0xe045, 0xf053, 0x26d7,
+	0x4ed6, 0xae07, 0xcc73, 0xe41e, 0x0833, 0xe049, 0xc001, 0x243b,
+	0x4c3c, 0xc000, 0xaf06, 0xe046, 0xb608, 0xf02e, 0xcaaa, 0x2ac9,
+	0xb616, 0xe0c1, 0x0048, 0x36d1, 0x3ed2, 0x26d1, 0x4ed2, 0xe042,
+	0xe049, 0x16bd, 0x1ebe, 0xf035, 0x14bb, 0x1cbc, 0xe0c2, 0x0048,
+	0xe0c2, 0x0052, 0xa200, 0xceaa, 0xc001, 0x243b, 0x4c3c, 0xc000,
+	0xe41e, 0x0838, 0xe42e, 0xc001, 0x2439, 0x4c3a, 0xc000, 0xe42e,
+	0xc001, 0xaf06, 0x3439, 0x3c3a, 0xc000, 0xe42e, 0xe41e, 0x07fa,
+	0xc001, 0xe0c0, 0x0048, 0x3417, 0x3c18, 0xc000, 0xe42e, 0xe0c0,
+	0x0045, 0xaf04, 0xa80e, 0xa104, 0xe428, 0x283c, 0xa104, 0xf06a,
+	0xe41e, 0x07a0, 0xe418, 0x01db, 0xe42e, 0xe41e, 0x05aa, 0xcaa2,
+	0xe008, 0x00ff, 0xe002, 0x000a, 0xe428, 0xe41e, 0x07a0, 0xe418,
+	0x01db, 0xe42e, 0xa200, 0xceaa, 0xc001, 0x2417, 0x4c18, 0xc000,
+	0xe0c2, 0x0048, 0xe42e, 0xe0c0, 0x0067, 0xe049, 0xa806, 0x3c3c,
+	0xe04a, 0xa810, 0xe01a, 0x3ce6, 0xa809, 0xe41b, 0x0a8f, 0xe41e,
+	0x0608, 0xf2ca, 0xa200, 0x3c91, 0x3c93, 0xe16a, 0x283c, 0xa104,
+	0xf108, 0xa23e, 0x3cf0, 0xe41e, 0x0af1, 0xe40a, 0x08a5, 0xe41e,
+	0x0556, 0xe41e, 0x1004, 0xe40d, 0x08a5, 0xe41d, 0x0847, 0xf06e,
+	0xe41e, 0x0f0b, 0xd1ff, 0x0000, 0xf11d, 0xa214, 0x3cf0, 0x2816,
+	0xf0d6, 0xe002, 0x0800, 0xf0a0, 0x2817, 0xf086, 0xe002, 0x0800,
+	0xf050, 0xa200, 0x3c93, 0xa202, 0xf05e, 0xa202, 0x3c93, 0xe16a,
+	0xa200, 0xe41e, 0x07f8, 0xe42e, 0xe41e, 0x0c2c, 0xf068, 0xe41e,
+	0x0a15, 0xe41e, 0x0a1a, 0xe42e, 0x2810, 0xa104, 0xe408, 0x08bb,
+	0xe40e, 0x090f, 0xe42e, 0xa200, 0x3c94, 0x3c95, 0xe162, 0x0670,
+	0xc73f, 0x3d12, 0xe16a, 0xe41e, 0x07a0, 0x3c91, 0x2891, 0xf10a,
+	0xe41e, 0x0847, 0xe0c0, 0x0045, 0xa808, 0xe01a, 0x3c91, 0xa208,
+	0x3c4b, 0x3c4c, 0xe41e, 0x0a0a, 0xe41e, 0x0a1a, 0xe42e, 0xe41e,
+	0x10ec, 0xd1ff, 0x0001, 0xf06c, 0xa208, 0x3c4b, 0x3c4c, 0xa202,
+	0x3c94, 0x28df, 0xf0da, 0xe41e, 0x0b8b, 0xf0aa, 0xe41e, 0x0c33,
+	0x209e, 0x4c9f, 0x2a91, 0xb436, 0x349e, 0x3c9f, 0xf07e, 0xe41e,
+	0x0a0a, 0xe41e, 0x0a1d, 0xe41e, 0x0a1a, 0x2041, 0x4c42, 0xe005,
+	0x0030, 0xae21, 0xe046, 0xf112, 0x2041, 0x4c42, 0xae06, 0xc873,
+	0xe046, 0xf0b6, 0xe049, 0xa83f, 0xf05b, 0x3e00, 0xe046, 0x7600,
+	0xf046, 0xba7f, 0xa140, 0xf7e0, 0xe41d, 0x0847, 0xe42e, 0xa200,
+	0x3c92, 0xa200, 0x3c51, 0x3c52, 0x3c57, 0x2892, 0xb63a, 0xe418,
+	0x0847, 0x2892, 0xe428, 0x28dd, 0xf0ba, 0xa200, 0x3cdd, 0x28d4,
+	0xcc92, 0x28d3, 0xa118, 0xe40a, 0x0964, 0xe40e, 0x096a, 0xe41e,
+	0x057f, 0xf2aa, 0x28d3, 0xa114, 0xf27a, 0x28d3, 0xa116, 0xf30a,
+	0x28d3, 0xa118, 0xf32a, 0x28d3, 0xa11a, 0xf35a, 0x28d3, 0xa11c,
+	0xf3aa, 0x28d3, 0xa11e, 0xe40a, 0x097c, 0x28d3, 0xa136, 0xe40a,
+	0x098f, 0x28d3, 0xa138, 0xe40a, 0x098f, 0x28d3, 0xa13a, 0xe40a,
+	0x098f, 0x28d3, 0xa13c, 0xe40a, 0x098f, 0x28d3, 0xa13e, 0xe40a,
+	0x098f, 0xe40e, 0x0915, 0xe41e, 0x0847, 0xa202, 0x3c91, 0xa208,
+	0x3c4b, 0x3c4c, 0xe41e, 0x0a0a, 0xe41e, 0x0a1a, 0xe42e, 0xa202,
+	0xe41e, 0x054b, 0xe40e, 0x0915, 0xe41e, 0x0556, 0xe41e, 0x09e6,
+	0xe40e, 0x0915, 0xe41e, 0x0bbe, 0xe41e, 0x0556, 0xe41e, 0x09a7,
+	0xe40e, 0x0915, 0xe41e, 0x0556, 0xe41e, 0x10a1, 0xe41e, 0x10dd,
+	0xd1ff, 0x0000, 0xe40e, 0x0915, 0xe41e, 0x0556, 0xe41e, 0x1004,
+	0xe41e, 0x14f5, 0xe41e, 0x107a, 0xe41e, 0x0c29, 0xa200, 0x3c91,
+	0xd1ff, 0x0000, 0x28db, 0xe408, 0x0995, 0xe40e, 0x0915, 0xe41e,
+	0x0556, 0xe41e, 0x194b, 0xe40e, 0x0915, 0xe41e, 0x14ec, 0xe41e,
+	0x0862, 0xa202, 0x3c92, 0xe161, 0x08c7, 0x289c, 0xe000, 0x08ca,
+	0xe094, 0xa2fe, 0x3d01, 0xa2fa, 0x3d02, 0xe40e, 0x0915, 0xa200,
+	0x3c94, 0x3c95, 0xe162, 0x0670, 0xc73f, 0x3d12, 0xe16a, 0xe41e,
+	0x1119, 0xd1ff, 0x0001, 0xf06c, 0xa208, 0x3c4b, 0x3c4c, 0xa202,
+	0x3c94, 0x28df, 0xe418, 0x0b8b, 0xe418, 0x0c33, 0xf058, 0xe41e,
+	0x0a0a, 0xe41e, 0x0a1d, 0x284a, 0xa106, 0x2a4b, 0xa109, 0xb636,
+	0xf05a, 0xe41e, 0x0a1a, 0xa202, 0x3c92, 0x2892, 0xe428, 0x2851,
+	0xa002, 0x3c51, 0xe41e, 0x0b21, 0xe428, 0x28e0, 0xe428, 0xa202,
+	0x3c94, 0x284e, 0x3c52, 0xa200, 0x3c57, 0xe41e, 0x0c8c, 0xe41e,
+	0x0a1d, 0xe41e, 0x0a1a, 0xa202, 0x3c92, 0xe42e, 0x284a, 0xa106,
+	0xe428, 0x2851, 0xa102, 0xe428, 0x28e0, 0xf0e8, 0xe41e, 0x1130,
+	0xd1ff, 0x0001, 0xf03c, 0xa202, 0x3c94, 0xe41e, 0x0c8c, 0xe41e,
+	0x0a1d, 0xe41e, 0x0a1a, 0xa202, 0x3c92, 0xe42e, 0x28e0, 0xe428,
+	0xe41e, 0x113c, 0xd1ff, 0x0001, 0xf03c, 0xa202, 0x3c94, 0xe41e,
+	0x0a1d, 0xe42e, 0xe41e, 0x1691, 0xe41e, 0x0c33, 0xe41e, 0x0c8c,
+	0xe41e, 0x18b9, 0xe41e, 0x181e, 0xe42e, 0xe41e, 0x0c4e, 0xe41e,
+	0x181e, 0xe42e, 0xe41e, 0x1879, 0xe42e, 0xe166, 0x08c7, 0x2906,
+	0xe424, 0xe41e, 0x1506, 0xe41e, 0x163c, 0x2894, 0xf038, 0xe16a,
+	0xf02e, 0xe16b, 0x284b, 0xa108, 0xe42a, 0xa2fe, 0xcf08, 0xd18c,
+	0x0001, 0xcb18, 0xf7f8, 0xa200, 0x3c87, 0x3c88, 0x3c86, 0xe41d,
+	0x0847, 0xe41e, 0x1b18, 0xe41e, 0x1b32, 0xe41e, 0x1b8a, 0x28a7,
+	0xe418, 0x1890, 0xe41e, 0x1ba2, 0xd1ff, 0x0002, 0x2886, 0xa002,
+	0x3c86, 0x2887, 0xa002, 0x3c87, 0x1855, 0xf6a4, 0xa200, 0x3c87,
+	0x2888, 0xa002, 0x3c88, 0x1856, 0xf312, 0xa202, 0x2a3e, 0xe419,
+	0x116b, 0xe40a, 0x0a82, 0x2810, 0xa104, 0xf5a8, 0xc894, 0x4c6b,
+	0xf578, 0x2894, 0xf208, 0xe41e, 0x0b57, 0xf1da, 0xe41e, 0x0556,
+	0xe41e, 0x113c, 0xd1ff, 0x0001, 0xf16d, 0x2888, 0x1857, 0xf138,
+	0x2856, 0x1857, 0xf106, 0xe41e, 0x1506, 0xe41e, 0x163c, 0xa200,
+	0x3c87, 0x2857, 0x3c88, 0x8488, 0x8255, 0xe018, 0x3c86, 0xe16a,
+	0xe40e, 0x0a37, 0xe16b, 0xe40e, 0x0a37, 0x2856, 0xcf08, 0xd18c,
+	0x0001, 0xcb18, 0xf7f8, 0xe0c0, 0x0111, 0xf7e8, 0xe42e, 0xd030,
+	0x0000, 0xd034, 0x0000, 0xd033, 0x0000, 0xd035, 0x0000, 0xd036,
+	0x007f, 0xd037, 0x0000, 0xd038, 0x0000, 0xe181, 0xe0c0, 0x0060,
+	0x34b9, 0x3cba, 0xe0c0, 0x0061, 0xae14, 0x34bb, 0x3cbc, 0x04b9,
+	0x0cba, 0x34bd, 0x3cbe, 0xe0c0, 0x0048, 0xe008, 0x01ff, 0x3cc5,
+	0xe0c0, 0x0048, 0x34bf, 0xe008, 0xfe00, 0x3cc0, 0xca28, 0xf7f8,
+	0x24bf, 0x4cc0, 0xce20, 0xd111, 0x0000, 0xd112, 0x0080, 0xe0c0,
+	0x0043, 0xa806, 0xae02, 0xa022, 0xce26, 0xca28, 0xf7f8, 0x24bf,
+	0x4cc0, 0xe000, 0x0200, 0x34bf, 0x3cc0, 0xe049, 0x16bd, 0x1ebe,
+	0xf055, 0x24b9, 0x4cba, 0x34bf, 0x3cc0, 0xce20, 0xd111, 0x0080,
+	0xd112, 0x0080, 0xe0c0, 0x0043, 0xa806, 0xae02, 0xa022, 0xce26,
+	0xca28, 0xf7f8, 0xe128, 0x28c5, 0xa102, 0xf034, 0xba4f, 0xf7de,
+	0xba3f, 0xe009, 0x0085, 0xe003, 0x0085, 0xa204, 0xb636, 0x3c3c,
+	0xe42e, 0xe41e, 0x057f, 0xf23a, 0x28d3, 0xa114, 0xf20a, 0x28d3,
+	0xa116, 0xf23a, 0x28d3, 0xa118, 0xf20a, 0x28d3, 0xa11a, 0xf1da,
+	0x28d3, 0xa11c, 0xf1aa, 0x28d3, 0xa11e, 0xf15a, 0x28d3, 0xa136,
+	0xf14a, 0x28d3, 0xa138, 0xf11a, 0x28d3, 0xa13a, 0xf0ea, 0x28d3,
+	0xa13c, 0xf0ba, 0x28d3, 0xa13e, 0xf08a, 0xf07e, 0xe41e, 0x0847,
+	0xa200, 0xe42e, 0xa202, 0xe42e, 0xa202, 0xe41e, 0x054b, 0xe40e,
+	0x0af1, 0xe41e, 0x057f, 0xf25a, 0x28d3, 0xa114, 0xf22a, 0x28d3,
+	0xa116, 0xf1fa, 0x28d3, 0xa118, 0xf1ea, 0x28d3, 0xa11a, 0xf19a,
+	0x28d3, 0xa11c, 0xf16a, 0x28d3, 0xa11e, 0xf13a, 0x28d3, 0xa136,
+	0xf14a, 0x28d3, 0xa138, 0xf11a, 0x28d3, 0xa13a, 0xf0ea, 0x28d3,
+	0xa13c, 0xe40a, 0x0b4c, 0x28d3, 0xa13e, 0xe40a, 0x0b4c, 0xf0be,
+	0xa200, 0xe42e, 0xa202, 0xe42e, 0xe41e, 0x0556, 0xe41e, 0x194b,
+	0xe40e, 0x0b21, 0xa202, 0xe41e, 0x054b, 0xe40e, 0x0b21, 0xe41e,
+	0x057f, 0xf23a, 0x28d3, 0xa114, 0xf20a, 0x28d3, 0xa116, 0xf1fa,
+	0x28d3, 0xa118, 0xf1aa, 0x28d3, 0xa11a, 0xf17a, 0x28d3, 0xa11c,
+	0xf14a, 0x28d3, 0xa11e, 0xf11a, 0x28d3, 0xa136, 0xf12a, 0x28d3,
+	0xa138, 0xf0fa, 0x28d3, 0xa13a, 0xf0ca, 0x28d3, 0xa13c, 0xf09a,
+	0x28d3, 0xa13e, 0xf06a, 0xf0be, 0xa200, 0xe42e, 0xa202, 0xe42e,
+	0xe41e, 0x0556, 0xe41e, 0x194b, 0xe40e, 0x0b57, 0xa202, 0xe41e,
+	0x054b, 0xe40e, 0x0b57, 0x28df, 0xf1da, 0xa102, 0xf06a, 0xa102,
+	0xf0ba, 0xa104, 0xf0ea, 0xf12e, 0x284b, 0x444c, 0xf13a, 0xa204,
+	0x3ce0, 0xa202, 0xe42e, 0x284b, 0x084c, 0xa102, 0xf0b6, 0xf06e,
+	0x284b, 0x4c4c, 0xa804, 0xf06a, 0xf01e, 0xa202, 0x3ce0, 0xa202,
+	0xe42e, 0xa200, 0x3ce0, 0xa200, 0xe42e, 0x283c, 0xa104, 0xf02a,
+	0xe42e, 0xe41e, 0x07a0, 0xe428, 0xe41e, 0x057f, 0x28d3, 0xa116,
+	0xe428, 0xa202, 0xe41e, 0x054b, 0xf75e, 0xe42e, 0x28dc, 0xe428,
+	0xc001, 0x2417, 0x4c18, 0xc000, 0xe0c2, 0x0051, 0xa202, 0x3cdc,
+	0xe42e, 0x28dc, 0xe428, 0xe41e, 0x07fa, 0xe0c0, 0x0048, 0xe0c2,
+	0x0051, 0xa202, 0x3cdc, 0xe42e, 0xa202, 0x3c8e, 0x283f, 0x2a10,
+	0xa105, 0xb636, 0x3c8b, 0xa200, 0x3c8c, 0xa202, 0x3c8f, 0xa204,
+	0x2a8f, 0xb452, 0x3c97, 0xa204, 0x2a10, 0xa105, 0xb633, 0x468f,
+	0xb632, 0x2a8b, 0x4e8c, 0xb616, 0x0897, 0x3c97, 0xa104, 0xf030,
+	0xa206, 0x3c97, 0xa200, 0x2a8f, 0xb432, 0x2a89, 0xb616, 0x3c99,
+	0x288d, 0x4c8e, 0xb630, 0x3c9a, 0x288f, 0x3c9b, 0x2a89, 0xb616,
+	0x3c9b, 0xa200, 0x3c9c, 0xa202, 0x3c9d, 0xa200, 0x3c9e, 0x3ca0,
+	0xe42e, 0xe165, 0x07e0, 0xa200, 0xd022, 0x001f, 0xe184, 0x0c11,
+	0x3d15, 0xa002, 0xe165, 0x08c3, 0xa200, 0x3515, 0x3d15, 0x3515,
+	0x3d15, 0xe165, 0x08c7, 0xa2fa, 0xc708, 0x3d15, 0x2816, 0xa01e,
+	0xaf08, 0xae08, 0x3ca2, 0x2817, 0xa01e, 0xaf08, 0xae08, 0x3ca3,
+	0xe42e, 0xa202, 0x3c9d, 0xe42e, 0xe41e, 0x0d15, 0xe41e, 0x0eee,
+	0xb60c, 0xb620, 0xe42e, 0xe41e, 0x0d15, 0x28e0, 0xe41a, 0x0d1d,
+	0xe41e, 0x0d4f, 0xe41e, 0x0ddd, 0xe41e, 0x0e42, 0x28e0, 0xf0e8,
+	0xa200, 0x3c9d, 0x209e, 0x4c9f, 0x2a91, 0xb436, 0x349e, 0x3c9f,
+	0x20a0, 0x4ca1, 0xa002, 0x34a0, 0x3ca1, 0xe42e, 0xe41e, 0x0d15,
+	0xa2fa, 0xe162, 0x08c7, 0x3d02, 0xe162, 0x08db, 0xe163, 0x08eb,
+	0xe164, 0x08ef, 0xd022, 0x0003, 0xe184, 0x0c5f, 0x290b, 0x3d0c,
+	0xd022, 0x0003, 0xe184, 0x0c65, 0x290b, 0x3d0c, 0xd022, 0x0003,
+	0xe184, 0x0c6b, 0x290a, 0x3d0c, 0xe162, 0x08c7, 0xe163, 0x08cb,
+	0xe164, 0x08cc, 0x290b, 0x3d0c, 0x290b, 0x3d0c, 0x290a, 0x3d0c,
+	0xe162, 0x08e8, 0x28a4, 0x4ca5, 0xae02, 0x4d02, 0x3d12, 0x28a4,
+	0xae02, 0x4ca5, 0xae08, 0x4ca6, 0xae14, 0x4d02, 0x3d02, 0xe41e,
+	0x0e42, 0xa200, 0x3c9d, 0xe42e, 0xe004, 0x004b, 0x0851, 0xe094,
+	0x2902, 0xa80c, 0xe428, 0x2851, 0xe408, 0x0cd8, 0x2852, 0xae02,
+	0xe000, 0x08d5, 0xe094, 0xa10a, 0xe096, 0x2902, 0x3d03, 0x2852,
+	0xe016, 0xae02, 0xe000, 0x08d5, 0xe094, 0xa10a, 0xe096, 0x2902,
+	0x3d03, 0xa206, 0x2a52, 0xb616, 0x2a4a, 0xa107, 0xb612, 0xe000,
+	0x0067, 0xe094, 0x2852, 0xae02, 0xe000, 0x08d1, 0xe096, 0x290a,
+	0xae0c, 0x4d0a, 0xae02, 0x4d0a, 0x3d03, 0xa206, 0x2a52, 0xb612,
+	0x2a4a, 0xa107, 0xb612, 0xe000, 0x0067, 0xe094, 0x2852, 0xe016,
+	0xae02, 0xe000, 0x08d1, 0xe096, 0x290a, 0xae0c, 0x4d0a, 0xae02,
+	0x4d0a, 0x3d03, 0xe162, 0x08d4, 0xa200, 0xc703, 0x3d12, 0xe42e,
+	0x2852, 0xae02, 0xe000, 0x08d1, 0xe094, 0xa102, 0xe096, 0x2902,
+	0x3d03, 0x2852, 0xe016, 0xae02, 0xe000, 0x08d5, 0xe094, 0xa102,
+	0xe096, 0x2902, 0x3d03, 0xa206, 0x2a52, 0xb616, 0x2a4a, 0xa107,
+	0xb612, 0xe000, 0x0067, 0xe094, 0x2852, 0xae02, 0xe000, 0x08d1,
+	0xe096, 0x290a, 0xae0c, 0x4d0a, 0xae02, 0x4d0a, 0x3d03, 0xa206,
+	0x2a52, 0xb612, 0x2a4a, 0xa107, 0xb612, 0xe000, 0x0067, 0xe094,
+	0x2852, 0xe016, 0xae02, 0xe000, 0x08d5, 0xe096, 0x290a, 0xae0c,
+	0x4d0a, 0xae02, 0x4d0a, 0x3d03, 0xe42e, 0x289c, 0xe426, 0xe162,
+	0x08ca, 0x2902, 0xe41e, 0x0e9a, 0xe42e, 0xe162, 0x08d8, 0x2836,
+	0xae02, 0x4c38, 0xae06, 0x4c37, 0xae06, 0x4c39, 0xae02, 0x4c5c,
+	0xae02, 0x4c8c, 0xae04, 0x4c5b, 0xae02, 0x2a36, 0x4e38, 0x4e5c,
+	0x468b, 0xb432, 0xae02, 0x2a5b, 0xb633, 0x468c, 0xb432, 0xae02,
+	0xa900, 0xae02, 0xa900, 0x3d12, 0xa200, 0xae02, 0xa900, 0xae08,
+	0xa900, 0xae04, 0x4c10, 0xae04, 0x4c4a, 0xae06, 0x4c4b, 0xae06,
+	0x4c4c, 0x3d12, 0x2853, 0x3d12, 0x2854, 0x3d12, 0xe42e, 0x284b,
+	0xa804, 0xe408, 0x0db1, 0xe162, 0x08c7, 0xe163, 0x08c8, 0xa203,
+	0x2b13, 0x1b0b, 0x2913, 0xe419, 0x0eab, 0x2903, 0x2ae0, 0xb7d2,
+	0x2a91, 0xb7f2, 0x2a4b, 0xa809, 0x4e91, 0x4ee0, 0xe41b, 0x0e56,
+	0x3d02, 0xe162, 0x08d8, 0xe163, 0x08dc, 0xe164, 0x08e0, 0xd022,
+	0x0003, 0xe184, 0x0d74, 0x2914, 0x3d13, 0xd022, 0x0003, 0xe184,
+	0x0d7a, 0x2912, 0x3d13, 0xe162, 0x08c7, 0xe163, 0x08c8, 0xe164,
+	0x08c9, 0x2914, 0x3d13, 0x2912, 0x3d13, 0x289b, 0xe016, 0xae04,
+	0xe000, 0x08df, 0xe094, 0xe163, 0x08eb, 0xe164, 0x08ef, 0xd022,
+	0x0003, 0xe184, 0x0d94, 0x290b, 0x3d0c, 0xd022, 0x0003, 0xe184,
+	0x0d9a, 0x290b, 0x3d0c, 0xd022, 0x0003, 0xe184, 0x0da0, 0x290a,
+	0x3d0c, 0x289b, 0xe016, 0xe000, 0x08c8, 0xe094, 0xe163, 0x08cb,
+	0xe164, 0x08cc, 0x290b, 0x3d0c, 0x290b, 0x3d0c, 0x290a, 0x3d0c,
+	0xe42e, 0x2ae0, 0xb7d2, 0xe41b, 0x0e78, 0xe162, 0x08c7, 0x3d02,
+	0xe162, 0x08db, 0xe163, 0x08eb, 0xe164, 0x08ef, 0xd022, 0x0003,
+	0xe184, 0x0dc3, 0x290b, 0x3d0c, 0xd022, 0x0003, 0xe184, 0x0dc9,
+	0x290b, 0x3d0c, 0xd022, 0x0003, 0xe184, 0x0dcf, 0x290a, 0x3d0c,
+	0xe162, 0x08c7, 0xe163, 0x08cb, 0xe164, 0x08cc, 0x290b, 0x3d0c,
+	0x290b, 0x3d0c, 0x290a, 0x3d0c, 0xe42e, 0xe162, 0x08e8, 0x28a4,
+	0x4ca5, 0xae02, 0x4d02, 0x3d12, 0x28a4, 0xae02, 0x4ca5, 0xae08,
+	0x4ca6, 0xae14, 0x4d02, 0x3d02, 0x284b, 0xa804, 0xe408, 0x0e23,
+	0xe162, 0x08cd, 0xe163, 0x08ce, 0xe164, 0x08cf, 0xa2fa, 0x3d04,
+	0xe161, 0x08c7, 0x2b01, 0xf0d5, 0xe161, 0x08d8, 0x2b01, 0xa819,
+	0xf08b, 0xa201, 0x2903, 0x2a4b, 0xa809, 0xe41b, 0x0e56, 0x3d04,
+	0x2903, 0x3d02, 0x2904, 0x3d03, 0xa203, 0x2b02, 0x1b03, 0x2902,
+	0xe419, 0x0eab, 0xe163, 0x08ca, 0x2903, 0xe424, 0xe162, 0x08e4,
+	0x2902, 0xa818, 0xe42a, 0x289b, 0xe016, 0xe000, 0x08cd, 0xe098,
+	0x2904, 0x3d03, 0xe42e, 0xe161, 0x08d8, 0xe162, 0x08c7, 0xe163,
+	0x08ca, 0xe164, 0x08cf, 0xa2fa, 0x3d04, 0x2902, 0xe424, 0x2911,
+	0xa818, 0xe42a, 0x2902, 0x3d04, 0x2911, 0xaf0c, 0xa806, 0xa106,
+	0xf078, 0xe41e, 0x0e78, 0x3d04, 0x2902, 0xe41e, 0x0ebd, 0x2904,
+	0x3d03, 0xe42e, 0x289c, 0xa002, 0xe000, 0x08ca, 0xe094, 0x2902,
+	0xf034, 0xe41e, 0x0ecf, 0xe162, 0x08ca, 0x2912, 0xe412, 0x0e9a,
+	0x289c, 0xe426, 0x2912, 0xe412, 0x0e9a, 0xe42e, 0xe165, 0x08c3,
+	0x2115, 0x4d15, 0x2315, 0x4f15, 0xe056, 0xe165, 0x07e0, 0x2a98,
+	0xf0b7, 0xa103, 0xcc45, 0xe184, 0x0e6a, 0x2b15, 0x3e01, 0xe049,
+	0x5e01, 0xa803, 0xf03b, 0xa2fa, 0xe42e, 0xe165, 0x08c3, 0x2115,
+	0x4d0d, 0xa203, 0x5a01, 0xe056, 0x3515, 0x3d0d, 0x2801, 0xe42e,
+	0xe165, 0x08c3, 0x2115, 0x4d15, 0x2315, 0x4f15, 0xe056, 0xe165,
+	0x07e0, 0x2a98, 0xf0b7, 0xa103, 0xcc45, 0xe184, 0x0e8c, 0x2b15,
+	0x3e01, 0xe049, 0x5e01, 0xa803, 0xf03b, 0xa2fa, 0xe42e, 0xe165,
+	0x08c5, 0x2115, 0x4d0d, 0xa203, 0x5a01, 0xe056, 0x3515, 0x3d0d,
+	0x2801, 0xe42e, 0xe424, 0x3c01, 0x2898, 0xa102, 0x1801, 0xe424,
+	0xe165, 0x08c5, 0x2115, 0x4d0d, 0xa203, 0x5a01, 0xe056, 0x3515,
+	0x3d0d, 0x2801, 0xe42e, 0xe424, 0x3c01, 0x2898, 0xa102, 0x1801,
+	0xe424, 0xe165, 0x08c3, 0x2115, 0x4d0d, 0xa203, 0x5a01, 0xe015,
+	0xe052, 0x3515, 0x3d0d, 0x2801, 0xe42e, 0xe424, 0x3c01, 0x2898,
+	0xa102, 0x1801, 0xe424, 0xe165, 0x08c5, 0x2115, 0x4d0d, 0xa203,
+	0x5a01, 0xe015, 0xe052, 0x3515, 0x3d0d, 0x2801, 0xe42e, 0xe424,
+	0x3c01, 0x2898, 0xa102, 0x1801, 0xe424, 0xe165, 0x07e0, 0x2a98,
+	0xf087, 0xa103, 0xcc45, 0xe184, 0x0edf, 0x2b15, 0x1a01, 0xf03b,
+	0xa2fa, 0xe42e, 0xc845, 0xf067, 0xe184, 0x0ee8, 0x290d, 0x3d15,
+	0x8115, 0x2801, 0x810d, 0x3d15, 0x2801, 0xe42e, 0xa200, 0x3c02,
+	0xe165, 0x08c3, 0x2115, 0x4d15, 0x2315, 0x4f15, 0xe056, 0xe165,
+	0x07e0, 0x2a98, 0xf0f7, 0xa103, 0xcc45, 0xe184, 0x0f08, 0x2b15,
+	0x3e01, 0xe049, 0x5e01, 0xa803, 0xf049, 0x2a02, 0xa003, 0x3e02,
+	0xe190, 0x2802, 0xe42e, 0xe41e, 0x079b, 0xba4e, 0xba4f, 0xae11,
+	0xe056, 0xba4f, 0xae21, 0xe056, 0xb7f4, 0xe005, 0x00ff, 0xae21,
+	0xe00b, 0xffff, 0xe045, 0xb7f6, 0x343a, 0x3c3b, 0xba4e, 0x3c3c,
+	0xe008, 0x0085, 0xe002, 0x0085, 0xa203, 0x3ef0, 0xe408, 0x0fe4,
+	0xba4e, 0xba4f, 0xae11, 0xe056, 0xba4f, 0xae21, 0xe056, 0xba4f,
+	0xae31, 0xe055, 0xa109, 0xa204, 0x3cf0, 0xe405, 0x0fe4, 0xa206,
+	0x3cf0, 0xba42, 0x3c10, 0xba40, 0x3c48, 0xba40, 0x3c49, 0xba44,
+	0x3c13, 0xba48, 0x3c14, 0xba40, 0x3c2c, 0xba40, 0x3c43, 0xba40,
+	0x3c3d, 0xba40, 0x3c44, 0xba40, 0x3c2d, 0xba40, 0x3c2e, 0xba42,
+	0x3c2f, 0xba40, 0x3c30, 0xba40, 0x3c45, 0xba40, 0x3c31, 0xba40,
+	0x3c3e, 0xba40, 0x3c3f, 0xba44, 0x3c40, 0xba42, 0x3c32, 0xba40,
+	0x3c1b, 0xba40, 0x3c46, 0x2813, 0xae04, 0xa004, 0xe0c2, 0x007d,
+	0xe0c2, 0x0079, 0xa202, 0x3c22, 0xa208, 0x3cf0, 0x2848, 0xe408,
+	0x0fe4, 0xa20a, 0x3cf0, 0x2849, 0xe408, 0x0fe4, 0xa206, 0x3cf0,
+	0x2810, 0xa104, 0xe40a, 0x0fe4, 0xa20e, 0x3cf0, 0x2844, 0xe40a,
+	0x0fe4, 0xa20c, 0x3cf0, 0x2843, 0xe408, 0x0fe4, 0x2810, 0xa104,
+	0xb7f4, 0xa004, 0x3c10, 0xf047, 0xba4e, 0xa103, 0xf7e1, 0xba4e,
+	0xba4f, 0xae11, 0xe056, 0xba4f, 0xae21, 0xe056, 0xba4f, 0xae31,
+	0xe056, 0x3c17, 0x3c34, 0xba4e, 0xba4f, 0xae11, 0xe056, 0xba4f,
+	0xae21, 0xe056, 0xba4f, 0xae31, 0xe056, 0x3c16, 0x3c33, 0xa200,
+	0x2a3c, 0xe003, 0x00c5, 0xb636, 0x3c3c, 0xa100, 0xe40a, 0x0fe5,
+	0xba4e, 0xba4f, 0xae11, 0xe056, 0xba4f, 0xae21, 0xe056, 0xba4f,
+	0xae31, 0xe056, 0xe049, 0xa118, 0xf06a, 0xf287, 0xba4e, 0xa103,
+	0xf7e1, 0xf24e, 0xba44, 0x3c11, 0xba40, 0xba46, 0xba4e, 0xba4f,
+	0xae11, 0xe056, 0xba4f, 0xae21, 0xe056, 0xe161, 0x0758, 0x3511,
+	0x3d11, 0xba4e, 0xba4f, 0xae11, 0xe056, 0xba4f, 0xae21, 0xe056,
+	0xba4f, 0xae31, 0xe056, 0xe161, 0x0718, 0x3511, 0x3d11, 0xba4e,
+	0xba4e, 0xba4e, 0xba4e, 0xf02e, 0xe16b, 0xe41d, 0x0847, 0xe42e,
+	0xe161, 0x0718, 0xe162, 0x0758, 0xba48, 0x3c27, 0xf156, 0xa102,
+	0xcc44, 0xba46, 0xa00c, 0x3c00, 0xba46, 0xa008, 0x3c01, 0xe184,
+	0x1002, 0xba5e, 0xa002, 0x5800, 0x3511, 0x3d11, 0xba5e, 0xa002,
+	0x5801, 0x3512, 0x3d12, 0xe42e, 0xba42, 0xa102, 0x3c10, 0xba44,
+	0x3c11, 0xba42, 0x3c12, 0xba44, 0x3c13, 0xba48, 0x3c14, 0xba40,
+	0x3c15, 0xba56, 0xa002, 0xae02, 0x3c16, 0xba56, 0xa002, 0xae02,
+	0x3c17, 0xba40, 0x3c18, 0xba40, 0x3c19, 0xba40, 0x3c1a, 0xba40,
+	0x3c1b, 0xba40, 0xba40, 0x3c1c, 0xa200, 0x3c43, 0x3c45, 0xa202,
+	0x3c44, 0x3c46, 0xba40, 0xe40a, 0x1075, 0xba5a, 0xa002, 0x3c1d,
+	0xba5a, 0xa002, 0x3c1e, 0xba40, 0xf17a, 0xba46, 0xe049, 0xa11f,
+	0xf089, 0xba4e, 0xa002, 0x3c1f, 0xba4e, 0xa002, 0x3c20, 0xf0ce,
+	0xe049, 0xe000, 0x06f0, 0xe098, 0xe001, 0x0700, 0xe09b, 0x2904,
+	0x3c1f, 0x2905, 0x3c20, 0xba40, 0xf21a, 0xba40, 0xf178, 0xba4e,
+	0xa80e, 0xe000, 0x0710, 0xe098, 0x2904, 0x3c21, 0x8421, 0xe182,
+	0x03e8, 0xe018, 0xe0c2, 0x007d, 0xe0c2, 0x0079, 0xe004, 0x03e8,
+	0xba47, 0xa103, 0xb422, 0x3c22, 0xf09e, 0xba5e, 0xa002, 0xe0c2,
+	0x007d, 0xe0c2, 0x0079, 0xa240, 0x3c22, 0xba40, 0xf07a, 0xba4e,
+	0x3c23, 0xba4e, 0x3c24, 0xba4e, 0x3c25, 0xba40, 0x3c26, 0xe418,
+	0x0fe8, 0xe42e, 0x2810, 0xf064, 0xa104, 0xf040, 0xe41e, 0x020f,
+	0xf082, 0xa204, 0x3c10, 0x28a2, 0x3c16, 0x28a3, 0x3c17, 0xe16b,
+	0xe42e, 0xe161, 0x0758, 0xe162, 0x0798, 0x2827, 0xf126, 0xa102,
+	0xcc44, 0xe184, 0x109f, 0xba4e, 0xa002, 0x3c00, 0x8400, 0x8311,
+	0xe018, 0xae20, 0x8400, 0x8311, 0xe019, 0xe042, 0xaf10, 0x3d12,
+	0xe42e, 0xba40, 0x3c28, 0xba40, 0x3c29, 0xba40, 0x3c2a, 0xba40,
+	0x3c2b, 0xba40, 0x3c2c, 0xba40, 0x3c2d, 0xba40, 0x3c2e, 0xba42,
+	0x3c2f, 0xba40, 0x3c30, 0xba40, 0x3c31, 0xba42, 0x3c32, 0x2826,
+	0xe418, 0x1089, 0x2816, 0x3c33, 0x2817, 0x3c34, 0xba40, 0xf09a,
+	0xba56, 0xa002, 0xae02, 0x3c33, 0xba56, 0xa002, 0xae02, 0x3c34,
+	0xa200, 0x3c35, 0x282e, 0xf03a, 0xba40, 0x3c35, 0xa200, 0x3c37,
+	0xba40, 0x3c36, 0xf03a, 0xba44, 0x3c37, 0xa200, 0x3c39, 0xba40,
+	0x3c38, 0xe42a, 0xba44, 0x3c39, 0xe42e, 0x2833, 0xf086, 0x1816,
+	0xf060, 0x2834, 0xf046, 0x1817, 0xf020, 0xf06e, 0x2816, 0x3c33,
+	0x2817, 0x3c34, 0xe16b, 0xe42e, 0xa200, 0x3c51, 0x3c52, 0x3c57,
+	0x3c6b, 0xba3e, 0xe008, 0x0085, 0xe002, 0x0085, 0xe41a, 0x0f0b,
+	0xe41e, 0x0bc9, 0xe41e, 0x118c, 0xe41e, 0x07fa, 0x24d7, 0x4cd6,
+	0xc873, 0xaf07, 0xe046, 0x34d7, 0x3cd6, 0xcc8c, 0xd039, 0x0000,
+	0xa200, 0xe41e, 0x0838, 0xa208, 0x3c4b, 0x3c4c, 0x2041, 0x4c42,
+	0xa102, 0xe426, 0xe16a, 0xe41e, 0x11a6, 0xe42d, 0xe41e, 0x12eb,
+	0xe42e, 0xa200, 0x3c51, 0x3c52, 0x3c57, 0x3c6b, 0xe16a, 0xe41e,
+	0x1203, 0xe42d, 0x284b, 0xa108, 0xe418, 0x12a6, 0xe42d, 0x284a,
+	0xa106, 0xf048, 0x284e, 0xe016, 0x3c52, 0xe41e, 0x12eb, 0xe42e,
+	0x284e, 0x3c52, 0xa200, 0x3c57, 0x3c6b, 0xe16a, 0xe41e, 0x12a6,
+	0xe42d, 0xe41e, 0x12eb, 0xe42e, 0x2851, 0x2a56, 0xb615, 0xba50,
+	0xe046, 0x3c57, 0xba40, 0xe42a, 0xa200, 0x3c6b, 0xe162, 0x004a,
+	0xe163, 0x0610, 0xd022, 0x0038, 0xe184, 0x114f, 0x2912, 0x3d13,
+	0xe16a, 0xe41e, 0x1203, 0xf0dd, 0x284b, 0xa108, 0xe418, 0x12a6,
+	0xf08d, 0xe41e, 0x1308, 0xf05d, 0xe41e, 0x12eb, 0xf02d, 0xe42e,
+	0xe162, 0x0610, 0xe163, 0x004a, 0xd022, 0x0038, 0xe184, 0x1169,
+	0x2912, 0x3d13, 0xe42e, 0x283e, 0xf1ea, 0xba40, 0xf1c8, 0xe41e,
+	0x079b, 0xa200, 0xba4f, 0xae10, 0xe056, 0xba4f, 0xae10, 0xe056,
+	0xe002, 0x00aa, 0xf0ba, 0xa102, 0xf03a, 0xa200, 0xe42e, 0xba4e,
+	0xba4e, 0xba4e, 0xba4e, 0xba4e, 0xba4e, 0xba4e, 0xba4e, 0xba4e,
+	0xba4e, 0xba4e, 0xa202, 0xe42e, 0xe41e, 0x079b, 0xba4e, 0xba4f,
+	0xae11, 0xe056, 0xba4f, 0xae21, 0xe056, 0x3441, 0x3c42, 0xba4e,
+	0x283c, 0xa102, 0xe428, 0xba4e, 0xba4f, 0xae11, 0xe056, 0xba4f,
+	0xae21, 0xe056, 0xba4f, 0xae31, 0xe056, 0xe42e, 0x281b, 0xf02a,
+	0xba40, 0xba42, 0xa200, 0x2a3f, 0xf03b, 0xba40, 0x3c5c, 0x2a40,
+	0xf039, 0xba40, 0xf02e, 0xb800, 0x3c4b, 0x3c4c, 0xa106, 0xf088,
+	0xb808, 0x3c5d, 0xa12c, 0xf048, 0xa204, 0x3c4b, 0x3c4c, 0xe004,
+	0x004b, 0x0851, 0xe092, 0x2901, 0x3c85, 0x2861, 0x2a85, 0xa803,
+	0xb636, 0x2a85, 0xa103, 0xb436, 0xa802, 0x3c61, 0x2885, 0xa802,
+	0xf028, 0xba4c, 0xe41e, 0x131e, 0xa200, 0x2a2e, 0xf02b, 0xb804,
+	0x3c62, 0x2885, 0xa804, 0xf068, 0xa200, 0x2a3d, 0xf02b, 0xba42,
+	0x3c5b, 0x2833, 0x2a5b, 0xa803, 0xf03b, 0xa002, 0xaf02, 0x3c53,
+	0xa01e, 0xaf08, 0x3c55, 0x2834, 0x2a5b, 0xa805, 0xf03b, 0xa002,
+	0xaf02, 0x3c54, 0xa01e, 0xaf08, 0x3c56, 0xe41e, 0x1385, 0xe41e,
+	0x13e3, 0xe41e, 0x142d, 0xe41e, 0x1484, 0xa202, 0x3c4e, 0xa200,
+	0x3c5f, 0x3c60, 0xe42e, 0xa200, 0x2a19, 0xf02b, 0xb80a, 0x3c4a,
+	0xa106, 0xf05a, 0xb802, 0x3c4b, 0x3c4c, 0xf0ee, 0xba44, 0xae02,
+	0x3c4c, 0xe004, 0xaf50, 0x5c4c, 0xa806, 0x3c4b, 0xe004, 0xbb44,
+	0x5c4c, 0xa806, 0x3c4c, 0x284b, 0xa108, 0xf05a, 0x281a, 0xf03a,
+	0xba4e, 0x3c4d, 0xa200, 0x3c50, 0x3c4f, 0xa202, 0x3c4e, 0x2818,
+	0xf0ca, 0x2819, 0xf08a, 0x281c, 0xf068, 0xba40, 0x3c4e, 0xba40,
+	0x3c4f, 0xf03e, 0xba42, 0x3c50, 0x282a, 0xf28a, 0xa202, 0x2a19,
+	0xb616, 0x2a1c, 0xb612, 0xa002, 0x3c47, 0x2850, 0x084f, 0x2a18,
+	0xb616, 0x0847, 0x3c47, 0xba40, 0xf19a, 0xe161, 0x07b8, 0xe162,
+	0x07c4, 0xe163, 0x07d0, 0xe164, 0x07d6, 0x2847, 0xf0f6, 0xa102,
+	0xcc44, 0xe184, 0x125c, 0xba62, 0x3511, 0x3d11, 0xba62, 0x3512,
+	0x3d12, 0xba5a, 0x3d13, 0xba5a, 0x3d14, 0x284b, 0xa108, 0xe42a,
+	0xe004, 0x004b, 0x0851, 0xe092, 0x2901, 0x3c85, 0xba40, 0x3c61,
+	0xa200, 0x2a19, 0xf02b, 0xba40, 0x3c58, 0x2a1b, 0x284a, 0xa100,
+	0xb611, 0xa200, 0xf02b, 0xba40, 0x3c59, 0x284a, 0xa100, 0x2a85,
+	0xa107, 0xb632, 0xf07a, 0x284a, 0xa106, 0x2a85, 0xa805, 0xb636,
+	0xf038, 0xb808, 0x3c5d, 0x282b, 0x2a4a, 0xa107, 0xb612, 0x2a85,
+	0xa805, 0xb612, 0xf0ca, 0xba42, 0xe049, 0xa107, 0xf079, 0xba41,
+	0xf05b, 0xa002, 0xe049, 0xa121, 0xf7b7, 0x3c5e, 0x2833, 0x3c53,
+	0xa01e, 0xaf08, 0x3c55, 0x2834, 0x3c54, 0xa01e, 0xaf08, 0x2a4a,
+	0xa107, 0xf039, 0xa002, 0xaf02, 0x3c56, 0xe42e, 0xe004, 0x004b,
+	0x0851, 0xe092, 0x2901, 0x3c85, 0xe41e, 0x131e, 0xa200, 0x2a15,
+	0xf02b, 0xba42, 0x3c5a, 0x284a, 0xa104, 0x2a85, 0xa107, 0xb632,
+	0xf038, 0xb808, 0x3c5d, 0xa200, 0x3c5f, 0x3c60, 0x284a, 0xa106,
+	0xf118, 0x2885, 0xa102, 0xf09a, 0x2885, 0xa106, 0xf0b8, 0xa202,
+	0x3c5f, 0xa200, 0x3c60, 0xf06e, 0xba40, 0x3c5f, 0xf038, 0xba40,
+	0x3c60, 0x2885, 0xa802, 0xf0ea, 0xa200, 0x2a2e, 0xf02b, 0xb804,
+	0x3c62, 0x2a35, 0x284a, 0xa100, 0xb615, 0xa200, 0xf02b, 0xb804,
+	0x3c63, 0xe41e, 0x1385, 0xe41e, 0x13e3, 0xe42d, 0xe41e, 0x142d,
+	0xe41e, 0x1484, 0xe42e, 0xe41e, 0x020f, 0xf062, 0x2833, 0x3c53,
+	0x2834, 0x3c54, 0xe16b, 0x287b, 0xf026, 0xf05e, 0xa202, 0x3c7b,
+	0x3c7c, 0xe16b, 0xf0cd, 0x283c, 0xa104, 0xf08a, 0x2041, 0x4c42,
+	0xe005, 0x0030, 0xae21, 0xe046, 0xf022, 0xf02e, 0xe16b, 0xe42e,
+	0xe162, 0x0610, 0x284a, 0x1912, 0xf108, 0xe162, 0x0619, 0x2853,
+	0x1912, 0xf0b8, 0x2854, 0x1912, 0xf088, 0x2855, 0x1912, 0xf058,
+	0x2856, 0x1912, 0xf028, 0xf02e, 0xe16b, 0xe42e, 0xba49, 0x3e7a,
+	0xa111, 0xa200, 0xf021, 0xba40, 0x3c7d, 0x287a, 0x2a32, 0xa101,
+	0xf0a9, 0x2a7a, 0xa111, 0xf077, 0x2a7a, 0xa139, 0xb5ae, 0xf037,
+	0xae02, 0xa13e, 0x3c7b, 0x3c7c, 0x2a32, 0xa105, 0xf0c3, 0xa003,
+	0xf073, 0xa200, 0x2a7a, 0xa111, 0xb62e, 0x3c7e, 0xe42e, 0xba40,
+	0x3c7e, 0xe42e, 0x2832, 0xa802, 0x3c7e, 0xe42e, 0xa200, 0x3c7f,
+	0xa206, 0x3c80, 0xa202, 0x3c82, 0x2a2f, 0xa803, 0xf059, 0x2a2f,
+	0xa805, 0xf259, 0xe42e, 0xba40, 0xe42a, 0x3c7f, 0xba42, 0x3c80,
+	0xf09a, 0xa102, 0xf0aa, 0xa102, 0xf11a, 0xba40, 0x3c82, 0xe42a,
+	0xf1ce, 0xa21e, 0x3c81, 0xf19e, 0xba42, 0xae04, 0x3c81, 0xe004,
+	0x936c, 0x5c81, 0xa81e, 0x3c81, 0xf10e, 0xba42, 0xae04, 0x3c81,
+	0xe004, 0x1248, 0x5c81, 0xa81e, 0x3c81, 0xf07e, 0xa202, 0x3c7f,
+	0xa200, 0x3c80, 0xa21e, 0x3c81, 0xba44, 0xe049, 0xa10f, 0x087b,
+	0xa002, 0xf029, 0xba48, 0x3c7c, 0xe42e, 0xa200, 0xe162, 0x0065,
+	0xc705, 0x3d12, 0xa202, 0x2a85, 0xa103, 0xf05b, 0x2a85, 0xa107,
+	0xf1cb, 0xf33e, 0x2a4a, 0xa105, 0xf059, 0xba41, 0xa202, 0xb672,
+	0xf2ce, 0xa208, 0x2a7b, 0xa119, 0xb60e, 0x3c64, 0xb80e, 0xe049,
+	0xaf05, 0x3e65, 0xf02b, 0xb810, 0x0864, 0xae02, 0x3c64, 0xe004,
+	0xe42d, 0x5c64, 0xa806, 0xf19e, 0x2a4a, 0xa101, 0xf05b, 0x2a4a,
+	0xa107, 0xf06b, 0xf12e, 0xba41, 0xa200, 0xb632, 0xf0ee, 0xa208,
+	0x2a7b, 0xa119, 0xb60e, 0x3c64, 0xb810, 0x0864, 0xae02, 0x3c64,
+	0xe004, 0xe42d, 0x5c64, 0xa806, 0x3c64, 0x284a, 0xa104, 0x2a85,
+	0xa803, 0xb636, 0xf038, 0xba40, 0x3c65, 0x2865, 0xe42a, 0x284a,
+	0xa106, 0xf058, 0xb836, 0x3068, 0xaf02, 0x3065, 0x2865, 0xf05a,
+	0xba4a, 0x3c66, 0xba4a, 0x3c67, 0x2868, 0xf05a, 0xba4a, 0x3c69,
+	0xba4a, 0x3c6a, 0xe42e, 0xa200, 0x3c6d, 0x3c6e, 0x3c6f, 0xc411,
+	0xe162, 0x006f, 0x2a4a, 0xa101, 0x2885, 0xa102, 0xb631, 0x2864,
+	0xa106, 0xb631, 0xe41b, 0x15db, 0xe42d, 0xc411, 0xe162, 0x006f,
+	0x2a4a, 0xa107, 0x2885, 0xa106, 0xb631, 0xe41b, 0x15db, 0xe42d,
+	0xc411, 0xe162, 0x006f, 0x2a4a, 0xa107, 0x2885, 0xa106, 0xb611,
+	0xe419, 0x15db, 0xe42d, 0xc409, 0xe162, 0x006e, 0x2a4a, 0xa107,
+	0x2885, 0xa802, 0xb615, 0xe419, 0x15db, 0xe42d, 0xc411, 0xe162,
+	0x006f, 0x2a4a, 0xa105, 0x2885, 0xa802, 0xb631, 0xe41b, 0x15db,
+	0xe42d, 0xc409, 0xe162, 0x006e, 0x2a10, 0xa105, 0x2885, 0xa802,
+	0xb631, 0xe41b, 0x15db, 0xe42d, 0xe42e, 0xe004, 0x0024, 0x3c74,
+	0x2885, 0xa802, 0xe42a, 0x284a, 0xa104, 0xf05a, 0x284a, 0xa106,
+	0xf0aa, 0xf11e, 0xba42, 0xe000, 0x0051, 0x2a64, 0xa107, 0xb492,
+	0x3c70, 0xf09e, 0xba44, 0xe000, 0x0041, 0x2a64, 0xa107, 0xb492,
+	0xb492, 0x3c70, 0xa202, 0x2a4a, 0xa101, 0xf07b, 0x2a5f, 0xf091,
+	0xba42, 0xe000, 0x003d, 0xf08e, 0xba42, 0xe000, 0x0031, 0xf04e,
+	0xba44, 0xe000, 0x0035, 0x3c73, 0x2a4a, 0xa101, 0xf05b, 0xba44,
+	0xe000, 0x0029, 0xf04e, 0xba42, 0xe000, 0x0025, 0x3c74, 0x2a4a,
+	0xa105, 0x2885, 0xa802, 0xb635, 0xa200, 0xf049, 0xba42, 0xe000,
+	0x0020, 0x3c71, 0x284a, 0xa104, 0x2a85, 0xa107, 0xb632, 0xf08a,
+	0x2a4a, 0xa101, 0x2864, 0xa106, 0xb611, 0xa200, 0xf04b, 0xba42,
+	0xe000, 0x001c, 0x3c72, 0xe42e, 0xa200, 0x3c7f, 0x2885, 0xa802,
+	0xf0fa, 0x282f, 0xe418, 0x1346, 0xa202, 0x3c75, 0xa200, 0x3c76,
+	0x2830, 0xf06a, 0xba40, 0x3c75, 0xf03a, 0xba42, 0x3c76, 0xa200,
+	0x3c6c, 0x2831, 0xf17a, 0x2885, 0xa106, 0xf14a, 0xa204, 0x2a7b,
+	0xa113, 0xf083, 0x2810, 0xa104, 0x2a85, 0xa803, 0xb632, 0xf0a8,
+	0xb80c, 0x3c6c, 0xc401, 0xe162, 0x006d, 0xa106, 0xe41a, 0x15db,
+	0xe42d, 0x2843, 0x2a85, 0xa803, 0xb612, 0xf02a, 0xba40, 0x3c83,
+	0x2a83, 0x2885, 0xa802, 0xb636, 0x4445, 0xf02a, 0xba40, 0x3c84,
+	0xe004, 0x005d, 0x3c78, 0x3c79, 0x2884, 0xf198, 0x287a, 0xa110,
+	0xa203, 0xb601, 0xb806, 0xb611, 0xb472, 0xe000, 0x005d, 0x3c78,
+	0x3c79, 0x2885, 0xa802, 0xf0b8, 0x287a, 0xa110, 0xa203, 0xb601,
+	0xb806, 0xb611, 0xb472, 0xe000, 0x005d, 0x3c79, 0xba40, 0xe000,
+	0x0059, 0x3c77, 0x2810, 0xa104, 0x2a85, 0xa803, 0xb632, 0x2a2f,
+	0xb636, 0xe41a, 0x1346, 0xe42e, 0xe161, 0x0380, 0x2816, 0x3d11,
+	0x2817, 0x3d11, 0x2819, 0x3d11, 0xe42e, 0xe161, 0x0380, 0x2816,
+	0x1911, 0xf0a8, 0x2817, 0x1911, 0xf078, 0x2819, 0x1911, 0xf048,
+	0xa200, 0x3cdb, 0xe42e, 0xa202, 0x3cdb, 0xe42e, 0x2857, 0xae10,
+	0x4c55, 0xae10, 0x4c56, 0xcf24, 0xcf44, 0xcfc6, 0xcf04, 0xa200,
+	0x4c46, 0xae02, 0x4c84, 0xae04, 0x4c10, 0xae02, 0x4c2d, 0xae04,
+	0x4c4a, 0xae04, 0xe005, 0x004b, 0x0a51, 0xe093, 0x4d01, 0xae02,
+	0x4c51, 0xae02, 0x4c52, 0xae04, 0x4c6c, 0xae02, 0x4c75, 0xae02,
+	0x4c5f, 0xae02, 0x4c60, 0xae04, 0x4c64, 0xae04, 0x4c62, 0xae04,
+	0x4c63, 0xae0a, 0x4c5d, 0xae0a, 0x4c5e, 0xcf46, 0xcfc8, 0xcf06,
+	0xa200, 0x4c46, 0xae02, 0x4c84, 0xae02, 0x2a7a, 0xa111, 0xb42e,
+	0xae04, 0x4c7f, 0xae04, 0x4c80, 0xae08, 0x4c81, 0xae02, 0x4c82,
+	0xae02, 0x4c75, 0xae04, 0x4c76, 0xae0a, 0x4c7b, 0xae0a, 0x4c7c,
+	0xae02, 0x4c7d, 0xae02, 0x4c7e, 0xae02, 0x2a77, 0xe003, 0x0059,
+	0xe056, 0xae04, 0x2a78, 0xe003, 0x005d, 0xe056, 0xae04, 0x2a79,
+	0xe003, 0x005d, 0xe056, 0xcf48, 0xcf64, 0xa200, 0x2a70, 0xe003,
+	0x0041, 0xa83f, 0xe056, 0xae08, 0x2a74, 0xe003, 0x0024, 0xa81f,
+	0xe056, 0xae04, 0x2a72, 0xe003, 0x001c, 0xa807, 0xe056, 0xae04,
+	0x2a71, 0xe003, 0x0020, 0xa807, 0xe056, 0xae08, 0x2a73, 0xe003,
+	0x0031, 0xa81f, 0xe056, 0xcf4a, 0xe0c1, 0x0046, 0xe004, 0x0000,
+	0xae10, 0xe042, 0x2ab8, 0xa841, 0xf05b, 0xe161, 0x07de, 0x2111,
+	0x4d11, 0x4c6d, 0xcf4c, 0xcf1a, 0xe0c1, 0x0046, 0xe004, 0x0010,
+	0xae10, 0xe042, 0x2ab8, 0xa841, 0xf07b, 0xe161, 0x07de, 0x2111,
+	0x4d11, 0x2ae5, 0xe042, 0x4c6e, 0xcf4e, 0xcf1c, 0xe0c1, 0x0046,
+	0xe004, 0x0020, 0xae10, 0xe042, 0x2ab8, 0xa841, 0xf08b, 0xe161,
+	0x07de, 0x2111, 0x4d11, 0x2ae5, 0xae03, 0xe042, 0x4c6f, 0xcf50,
+	0xcf1e, 0xe0c1, 0x0046, 0xe004, 0x0030, 0xae10, 0xe042, 0x2ab8,
+	0xa803, 0xf05b, 0xe161, 0x08f0, 0x2111, 0x4d11, 0xcf00, 0xe165,
+	0x08c0, 0x2115, 0x4d15, 0xcf02, 0xe004, 0x0022, 0x2ab7, 0xa803,
+	0xb616, 0x2ab7, 0xa841, 0xf03b, 0xe00a, 0x0011, 0xcf14, 0x2053,
+	0x4c54, 0xcfc4, 0xe42e, 0xe082, 0xa104, 0xe400, 0x1638, 0x2855,
+	0xae10, 0x4c56, 0xcf24, 0xd190, 0x0200, 0xcb20, 0xcb23, 0xe409,
+	0x1638, 0xf7c8, 0xcb26, 0x3d02, 0xa100, 0xe42a, 0xa202, 0x3c6b,
+	0xe180, 0xe180, 0x2855, 0xa01e, 0xaf08, 0x3c02, 0x8402, 0x8256,
+	0xe018, 0xa008, 0xaf04, 0xae04, 0x3ce4, 0xae02, 0xe049, 0xe003,
+	0x0100, 0xf063, 0xe005, 0x0100, 0xe004, 0x0200, 0xf06e, 0xe009,
+	0x00ff, 0xf03b, 0xe003, 0x0100, 0xe046, 0x3ce5, 0xca28, 0xf7f8,
+	0xe083, 0xa103, 0xa200, 0xb486, 0xb482, 0xae04, 0xe000, 0x0000,
+	0xae10, 0xe0c1, 0x0046, 0xe042, 0x2ab8, 0xa841, 0xf0db, 0xe083,
+	0xa103, 0xa200, 0xf045, 0x08e5, 0xf027, 0x08e5, 0xe163, 0x07de,
+	0x2313, 0x4f13, 0xe042, 0xce20, 0xd111, 0x0200, 0x28e4, 0xce24,
+	0x28b7, 0xa840, 0xa904, 0xce26, 0xca28, 0xf7f8, 0xe181, 0xe42e,
+	0xd191, 0x0000, 0xe16b, 0xe42e, 0xe41e, 0x164e, 0xe41e, 0x16a7,
+	0xe41e, 0x1770, 0x2857, 0xe428, 0xe41e, 0x0274, 0xa202, 0xe0c2,
+	0x0106, 0xe42e, 0xe0c0, 0x0111, 0xf7e8, 0xe42e, 0x2810, 0xae08,
+	0xa902, 0xe0c2, 0x0100, 0xa200, 0xe0c2, 0x0128, 0x2aa5, 0x4ea4,
+	0xb692, 0xae08, 0xa92c, 0xe0c2, 0x017c, 0xe004, 0x0014, 0xe0c2,
+	0x017d, 0x2055, 0x4c56, 0xae08, 0x2a10, 0xa105, 0xf039, 0x2053,
+	0x4c54, 0xe0c2, 0x0101, 0xa200, 0xe41e, 0x1a0c, 0xe0c2, 0x0102,
+	0xe0c1, 0x0046, 0xe004, 0x0050, 0xae10, 0xe042, 0x2ab8, 0xa805,
+	0xf05b, 0xe161, 0x08f2, 0x2111, 0x4d11, 0xe0c2, 0x0103, 0xe004,
+	0x004b, 0x0851, 0xe092, 0x2901, 0xae04, 0x4c4a, 0xae02, 0x4c52,
+	0xe0c2, 0x0104, 0xa200, 0x2a6c, 0xa101, 0xb432, 0xe0c2, 0x0105,
+	0xe42e, 0x2810, 0xae08, 0xa902, 0xe0c2, 0x0100, 0x2aa5, 0x4ea4,
+	0xb692, 0xae08, 0xa92c, 0xe0c2, 0x017c, 0xe004, 0x0014, 0xe0c2,
+	0x017d, 0xa200, 0xe41e, 0x1a0c, 0xe0c2, 0x0102, 0xe42e, 0xa200,
+	0xe0c2, 0x0320, 0xe165, 0x08d0, 0x2b15, 0xa803, 0xb452, 0x2b15,
+	0xa803, 0xb432, 0xae04, 0x2b15, 0xa803, 0xb452, 0x2b15, 0xa803,
+	0xb432, 0xae04, 0x2b15, 0xa803, 0xb452, 0x2b15, 0xa803, 0xb432,
+	0xae04, 0x2b15, 0xa803, 0xb452, 0x2b15, 0xa803, 0xb432, 0xae04,
+	0xc420, 0xe165, 0x08dc, 0x2b35, 0xaf0f, 0xa803, 0xb452, 0x2b35,
+	0xaf0f, 0xa803, 0xb432, 0xae04, 0x2a64, 0xb456, 0xa803, 0xb432,
+	0xae02, 0x4c61, 0xe0c2, 0x0303, 0xe165, 0x08d0, 0xe166, 0x0304,
+	0xd022, 0x0003, 0xe184, 0x16ea, 0x2915, 0xaf02, 0xae18, 0x2b15,
+	0xaf03, 0xe042, 0x9f16, 0xc420, 0xe165, 0x08dd, 0xa200, 0x2b35,
+	0xaf0d, 0xa807, 0xa101, 0xb673, 0xe042, 0x2b35, 0xaf0d, 0xa807,
+	0xa101, 0xb673, 0xae05, 0xe042, 0xe0c2, 0x0308, 0x2857, 0xe428,
+	0xa202, 0xe0c2, 0x0302, 0xe165, 0x08c8, 0x2905, 0xf082, 0xe165,
+	0x08c9, 0x2905, 0xf042, 0xe165, 0x08c7, 0x2905, 0xe0c2, 0x0380,
+	0x3ce7, 0xe165, 0x08c9, 0x2905, 0xf082, 0xe165, 0x08c8, 0x2905,
+	0xf042, 0xe165, 0x08c7, 0x2905, 0xe0c2, 0x0383, 0x3ce8, 0xe165,
+	0x08c7, 0x2905, 0xe0c2, 0x0386, 0x2a51, 0xf02b, 0x3ce8, 0xa200,
+	0xe0c2, 0x0302, 0xa20e, 0xe0c2, 0x0312, 0xe0c0, 0x0414, 0xe418,
+	0x018c, 0xe0c0, 0x0414, 0xe41a, 0x1736, 0xe42e, 0xe167, 0x01a0,
+	0x2317, 0x4f17, 0xe0c3, 0x0152, 0x2b17, 0xe009, 0x00ff, 0xae21,
+	0x4f07, 0xe0c3, 0x0153, 0xe0c1, 0x0101, 0xe0c3, 0x015d, 0x2a4b,
+	0x2852, 0xf02a, 0x2a4c, 0xa107, 0xe004, 0x001b, 0xf039, 0xe004,
+	0x001f, 0x3c00, 0x28e7, 0xa53e, 0xa400, 0x2ae8, 0xa53f, 0xa401,
+	0xae11, 0xe055, 0xae21, 0xe167, 0x01a2, 0x2907, 0xaf10, 0x4400,
+	0xe055, 0xe0c3, 0x015c, 0xa202, 0xe0c2, 0x0150, 0xe0c0, 0x0150,
+	0xf7ea, 0xa200, 0xe0c2, 0x0150, 0xe0c0, 0x0151, 0xf7e8, 0xe42e,
+	0xa202, 0xae04, 0x2a10, 0xa807, 0xe056, 0xae04, 0xe005, 0x004b,
+	0x0a51, 0xe093, 0x2b01, 0xa807, 0xe056, 0xae04, 0x2a4a, 0xa807,
+	0xe056, 0xae02, 0x2a52, 0xa803, 0xe056, 0xe0c2, 0x0204, 0xa204,
+	0x2a6c, 0xa101, 0xb612, 0x2a2c, 0xb612, 0xe162, 0x08d8, 0x2b02,
+	0xa811, 0xb612, 0x2a6c, 0xa101, 0xb492, 0xe0c2, 0x0208, 0xe0c1,
+	0x0046, 0xe004, 0x0090, 0xae10, 0xe042, 0x2ab8, 0xa821, 0xf05b,
+	0xe161, 0x07dc, 0x2111, 0x4d11, 0xe0c2, 0x0209, 0xa204, 0x2a6c,
+	0xa101, 0xb612, 0x2a2c, 0xb612, 0xe162, 0x08d8, 0x2b02, 0xa811,
+	0xb612, 0x4c2c, 0xe0c2, 0x0210, 0xe0c1, 0x0046, 0xe004, 0x00e0,
+	0xae10, 0xe042, 0x2ab8, 0xa809, 0xf05b, 0xe161, 0x08f4, 0x2111,
+	0x4d11, 0xe0c2, 0x0211, 0xe0c1, 0x0046, 0xe004, 0x00e0, 0xe000,
+	0x0080, 0xae10, 0xe042, 0x2ab8, 0xa811, 0xf05b, 0xe161, 0x08f6,
+	0x2111, 0x4d11, 0xe0c2, 0x0212, 0x2053, 0x4c54, 0xe0c2, 0x0205,
+	0xa204, 0xe163, 0x08c7, 0xe164, 0x08cf, 0x2b03, 0x1b04, 0xb616,
+	0x2b04, 0xb64a, 0xae0e, 0xe41e, 0x1a0c, 0xe0c2, 0x0213, 0xa200,
+	0xe162, 0x08d8, 0xe164, 0x08cf, 0x2b02, 0xaf07, 0xa803, 0xb672,
+	0x2b04, 0xb60a, 0xae0e, 0xe41e, 0x1a0c, 0xe0c2, 0x0215, 0xe165,
+	0x08c7, 0x2905, 0xe0c2, 0x020b, 0xe0c2, 0x0214, 0xe41e, 0x1aac,
+	0xe162, 0x08d8, 0xe163, 0x08c7, 0xe164, 0x08cf, 0xa200, 0x2b02,
+	0xaf0f, 0xa803, 0xb432, 0xae10, 0x2b02, 0xaf11, 0xe009, 0x00ff,
+	0xe056, 0x2b04, 0xb60a, 0xe0c2, 0x0218, 0xe425, 0xe165, 0x08cf,
+	0x2905, 0xe0c2, 0x0216, 0xe41e, 0x1aac, 0xe42e, 0xe162, 0x08cb,
+	0xe163, 0x08e8, 0xe164, 0x08e9, 0xe165, 0x08ea, 0xa200, 0x2b03,
+	0xa805, 0xb632, 0x2b02, 0xb60a, 0x3ca7, 0xe42a, 0xe004, 0x012c,
+	0xe0c2, 0x017f, 0xa200, 0xe41e, 0x1a0c, 0xe0c2, 0x017f, 0x2915,
+	0xe008, 0x7fff, 0xa01e, 0xaf08, 0x3ca8, 0x2915, 0xe008, 0x7fff,
+	0xa01e, 0xaf08, 0x3ca9, 0x84a8, 0x82a9, 0xe018, 0x3cad, 0xa200,
+	0x3caa, 0x3cab, 0x3cac, 0x28a8, 0xa102, 0xae20, 0x4ca9, 0xa102,
+	0xe0c2, 0x0142, 0x2903, 0xaf0e, 0xa200, 0xe0c2, 0x0149, 0x2904,
+	0xaf1e, 0xa802, 0xae08, 0x2b04, 0xaf15, 0xa81f, 0xe056, 0xe0c2,
+	0x014e, 0x289c, 0xe000, 0x08cb, 0xe09a, 0x2905, 0xe0c2, 0x0143,
+	0xe41e, 0x1ac7, 0x2b03, 0xa805, 0xf079, 0xe165, 0x08cb, 0x2905,
+	0xe0c2, 0x0144, 0xf06e, 0xe0c0, 0x0061, 0xa87e, 0xe0c2, 0x0144,
+	0xe42e, 0x28a7, 0xe42a, 0xe41e, 0x1890, 0xf7e8, 0xe0c0, 0x014b,
+	0xf7e8, 0xa200, 0xa904, 0xae0e, 0x4caa, 0xae0e, 0x4cab, 0xe0c2,
+	0x014d, 0xa202, 0xe0c2, 0x014a, 0xe0c0, 0x014b, 0xf7e8, 0xe42e,
+	0xa200, 0x2aac, 0x1aad, 0xe423, 0xe0c0, 0x014b, 0xf7e8, 0xa200,
+	0x2aac, 0xb422, 0xae02, 0x2aac, 0x1aad, 0xb42a, 0xae0e, 0x4caa,
+	0xae0e, 0x4cab, 0xe0c2, 0x014d, 0xa202, 0xe0c2, 0x014a, 0xa202,
+	0x2aac, 0xa003, 0x3eac, 0x2aaa, 0xa003, 0x3eaa, 0x1aa8, 0xe425,
+	0xa201, 0x3eaa, 0x2aab, 0xa003, 0x3eab, 0x1aa9, 0xe425, 0xa200,
+	0xe42e, 0xe0c0, 0x0065, 0xe008, 0x0100, 0xe42a, 0xca28, 0xf7f8,
+	0xe0c0, 0x006a, 0xce20, 0xd111, 0x0300, 0xd112, 0x0004, 0xd113,
+	0x0003, 0xca28, 0xf7f8, 0xe161, 0x0300, 0xe162, 0x08fa, 0xa202,
+	0xae30, 0xa920, 0x3511, 0x3d11, 0x2111, 0x4d11, 0x3512, 0x3d12,
+	0xca28, 0xf7f8, 0xe0c0, 0x006a, 0xce20, 0xd111, 0x0300, 0xd112,
+	0x0004, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0065,
+	0xaf10, 0xa802, 0xe42a, 0xe161, 0x0300, 0xe163, 0x08c3, 0xe164,
+	0x08c5, 0xa200, 0x3c01, 0xd022, 0x0007, 0xe184, 0x1908, 0xa200,
+	0xae08, 0x2313, 0x4f0b, 0x5e01, 0xa803, 0xb452, 0x2314, 0x4f0c,
+	0x5e01, 0xa803, 0xb492, 0x2a01, 0xa003, 0x3e01, 0xa807, 0xf719,
+	0x3d11, 0xe162, 0x08c7, 0x2902, 0xf0f4, 0xaf04, 0xe000, 0x0300,
+	0xe092, 0xa218, 0x2b02, 0xa807, 0xae05, 0xe046, 0x3c01, 0xa202,
+	0x5801, 0x4d01, 0x3d01, 0xe180, 0xe180, 0xca28, 0xf7f8, 0xe162,
+	0x08fa, 0x2112, 0x4d12, 0xce20, 0xd111, 0x0300, 0xd112, 0x0008,
+	0xd113, 0x0002, 0xca28, 0xf7f8, 0xe181, 0xe42e, 0xe0c0, 0x0065,
+	0xaf0a, 0xa802, 0xe42a, 0xa200, 0x3ce1, 0x3ce2, 0x3ce3, 0xe162,
+	0x0300, 0x3d12, 0x3d12, 0x3d12, 0x3d12, 0xca28, 0xf7f8, 0xe0c0,
+	0x006b, 0xce20, 0xd111, 0x0300, 0xd112, 0x0004, 0xd113, 0x0000,
+	0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0065, 0xaf0a, 0xa802, 0xe42a,
+	0x2ce1, 0xa87e, 0xa120, 0xe422, 0xa200, 0xe41e, 0x19a5, 0x28d4,
+	0xf7ca, 0x20d7, 0x4cd6, 0xc871, 0xaf07, 0xe046, 0xf760, 0xa202,
+	0xe41e, 0x19a5, 0x2ce1, 0xa002, 0x3ce1, 0xe161, 0x0300, 0x28d3,
+	0x3d11, 0xc870, 0xaf06, 0x3d11, 0xa200, 0x3d11, 0x3d11, 0xc870,
+	0xaf16, 0xf09a, 0xa220, 0x3ce1, 0xe161, 0x0301, 0xa200, 0x3d11,
+	0x3d11, 0x3d11, 0xca28, 0xf7f8, 0xe0c0, 0x006b, 0x2ee1, 0xa87f,
+	0xae07, 0xe042, 0xce20, 0xd111, 0x0300, 0xd112, 0x0004, 0xd113,
+	0x0000, 0xca28, 0xf7f8, 0xe161, 0x0300, 0x2ce1, 0xa87e, 0x3d11,
+	0x2ce2, 0x3d11, 0x2ce1, 0xaf10, 0x3d11, 0xa200, 0x3d11, 0xca28,
+	0xf7f8, 0xe0c0, 0x006b, 0xce20, 0xd111, 0x0300, 0xd112, 0x0004,
+	0xd113, 0x0000, 0xca28, 0xf7f8, 0xe42e, 0xf278, 0xe0c0, 0x006c,
+	0x1ce3, 0xf2c0, 0xe0c0, 0x0065, 0xaf14, 0xa802, 0xf068, 0xe0c0,
+	0x005c, 0xe008, 0x0200, 0xf098, 0xba4e, 0x2ce1, 0xa87e, 0xa203,
+	0xae11, 0xe042, 0x3ce1, 0xe42e, 0xe0c0, 0x005d, 0xe00a, 0x0200,
+	0xe0c2, 0x005d, 0xa202, 0xce00, 0xe0c0, 0x005d, 0xe008, 0x0200,
+	0xf7c8, 0xa200, 0x3ce3, 0xf0ae, 0x2ce3, 0xa80e, 0xe42a, 0x2ce3,
+	0xa00e, 0xaf06, 0xae06, 0x3ce3, 0xf20e, 0x2ce3, 0xa80e, 0xf088,
+	0xe161, 0x0300, 0xa200, 0x3d11, 0x3d11, 0x3d11, 0x3d11, 0x2ce3,
+	0xa80e, 0xaf02, 0xe000, 0x0300, 0xe092, 0x2ce3, 0xa802, 0xf058,
+	0xba4e, 0xae10, 0x3d11, 0xf04e, 0xba4e, 0x4d01, 0x3d11, 0x2ce3,
+	0xa002, 0x3ce3, 0xa80e, 0xe428, 0xca28, 0xf7f8, 0xe0c0, 0x006b,
+	0xe000, 0x0088, 0x2ee3, 0xa103, 0xaf07, 0xae07, 0xe042, 0xce20,
+	0xd111, 0x0300, 0xd112, 0x0004, 0xd113, 0x0000, 0xca28, 0xf7f8,
+	0x2ce2, 0xa010, 0x3ce2, 0xe42e, 0xe0c1, 0x0044, 0xa80f, 0xe056,
+	0xe42e, 0xa200, 0xe41e, 0x1a0c, 0xe42e, 0xe0c1, 0x0044, 0xaf0d,
+	0xae03, 0xe056, 0xe008, 0x003f, 0xe42e, 0xe0c1, 0x0044, 0xaf17,
+	0xa803, 0xe42e, 0xe0c1, 0x0044, 0xaf17, 0xa803, 0xa105, 0xf039,
+	0xa213, 0xe42e, 0xa201, 0xe42e, 0xa203, 0xe0c3, 0x040d, 0xe0c1,
+	0x0420, 0xa803, 0xf7db, 0xe160, 0x0003, 0xe166, 0x0800, 0xe167,
+	0x0500, 0x2898, 0xf1b6, 0xa102, 0xcc44, 0xe184, 0x1a54, 0xa200,
+	0xe41e, 0x1a0c, 0xaf04, 0xe41e, 0x1a15, 0xae20, 0x2eb4, 0xe056,
+	0x9f17, 0x2055, 0x4c56, 0xae08, 0x2a10, 0xa105, 0xf039, 0x2053,
+	0x4c54, 0x9f17, 0xe41e, 0x1a5a, 0xe190, 0xe190, 0xa201, 0xe0c3,
+	0x040d, 0xe42e, 0x2116, 0x4d16, 0x9f17, 0x2116, 0x4d16, 0x9f17,
+	0x2116, 0x4d16, 0x9f17, 0xe42e, 0xe0c0, 0x0044, 0xaf20, 0xa802,
+	0xe428, 0xe0c0, 0x0060, 0xa860, 0xe42a, 0xe0c0, 0x0061, 0xa83e,
+	0xa203, 0xe0c3, 0x040d, 0xcca4, 0xc785, 0xe018, 0xe000, 0x0500,
+	0xe09e, 0xe0c1, 0x0420, 0xa803, 0xf7db, 0xa200, 0xe41e, 0x1a11,
+	0xa80e, 0xaf04, 0xe41e, 0x1a15, 0xe41e, 0x1a1d, 0xe40b, 0x1a8d,
+	0xa81e, 0xe41e, 0x1a22, 0xae09, 0xe056, 0xae20, 0xe0c1, 0x006e,
+	0xe009, 0x1fff, 0xe056, 0x9f17, 0xe0c0, 0x0060, 0xa822, 0xa122,
+	0xf04a, 0x20a2, 0x4ca3, 0xf03e, 0x20a3, 0x4ca2, 0x9f17, 0xe0c0,
+	0x0062, 0x9f17, 0xe0c0, 0x0063, 0x9f17, 0xe0c0, 0x0064, 0x9f17,
+	0xa201, 0xe0c3, 0x040d, 0xe42e, 0x3c00, 0xa202, 0xe0c2, 0x040d,
+	0xe0c0, 0x0420, 0xa802, 0xf7da, 0x8400, 0xc785, 0xe018, 0xe000,
+	0x0501, 0xe09e, 0x2055, 0x4c56, 0xae08, 0x2a10, 0xa105, 0xf039,
+	0x2053, 0x4c54, 0x9f07, 0xa200, 0xe0c2, 0x040d, 0xe42e, 0x3c00,
+	0xa202, 0xe0c2, 0x040d, 0xe0c0, 0x0420, 0xa802, 0xf7da, 0x8400,
+	0xc785, 0xe018, 0xe000, 0x0501, 0xe09e, 0x20a8, 0x4ca9, 0xae08,
+	0x2a10, 0xa105, 0xf0b9, 0xe165, 0x08ea, 0x2915, 0xe008, 0x7fff,
+	0xae20, 0x2b15, 0xe009, 0x7fff, 0xe056, 0x9f07, 0xa200, 0xe0c2,
+	0x040d, 0xe42e, 0x3cec, 0xe0c0, 0x0041, 0xe005, 0x0020, 0xae11,
+	0xe042, 0xce20, 0xd111, 0x0800, 0xd112, 0x00c0, 0x88ec, 0x0113,
+	0xca29, 0xf7f9, 0xe190, 0xe42e, 0x2887, 0xae10, 0x4c88, 0xcf52,
+	0xcfca, 0xcf08, 0xd18c, 0x0001, 0xd18b, 0x0000, 0xcb16, 0xf7f8,
+	0xd1e1, 0x0000, 0xcbc2, 0xf7f8, 0xe42e, 0xcb18, 0xf7f8, 0xd18b,
+	0x0001, 0xd1e1, 0x0001, 0xcb16, 0xcbc3, 0xf7e8, 0xf7d9, 0xe42e,
+	0xe41e, 0x1afc, 0xf12d, 0xd1a0, 0x0001, 0xcb40, 0xcb43, 0xf0a9,
+	0xf7d8, 0xf08d, 0xcb54, 0xcf66, 0xcf0a, 0xcfd0, 0xcb56, 0xcf6c,
+	0xe42e, 0xd1a1, 0x0000, 0xe16b, 0xd1a0, 0x0000, 0xcb40, 0xf7f8,
+	0xf72e, 0xe42e, 0xf17d, 0xd1b0, 0x0001, 0xe180, 0xe180, 0x28d9,
+	0xe41a, 0x06a0, 0xe181, 0xe41e, 0x1b56, 0xcb60, 0xcb63, 0xf089,
+	0xf7d8, 0xf06d, 0xcb68, 0xcf0e, 0xcb6a, 0xcf10, 0xe42e, 0xd1e0,
+	0x0000, 0xe41e, 0x1b56, 0xd1b1, 0x0000, 0xa200, 0xcf0e, 0xcf10,
+	0xe0c0, 0x0124, 0xe0c2, 0x0124, 0xe16b, 0xe42e, 0xa200, 0xe0c2,
+	0x0113, 0xcb90, 0xe0c2, 0x030d, 0xcb88, 0xe0c2, 0x0114, 0xcb8a,
+	0xe0c2, 0x0115, 0xcb8c, 0xe0c2, 0x0130, 0x2888, 0x1857, 0x4c87,
+	0xe016, 0xe0c2, 0x0131, 0xcb8e, 0xe0c2, 0x012a, 0xcb82, 0xe0c2,
+	0x0221, 0xcb84, 0xe0c2, 0x0220, 0x287b, 0xe0c2, 0x022c, 0xcbd0,
+	0xf7f8, 0xcb92, 0xe0c2, 0x030f, 0xf0da, 0xcbd2, 0xe0c2, 0x0309,
+	0xcbd4, 0xe0c2, 0x030c, 0xcbd6, 0xe0c2, 0x030a, 0xcbd8, 0xe0c2,
+	0x030b, 0xe42e, 0xcb80, 0xe0c2, 0x0116, 0xcbda, 0xcf12, 0xe161,
+	0x0224, 0xd022, 0x0007, 0xd186, 0x0000, 0xe184, 0x1b98, 0xcb86,
+	0x9f11, 0xe41e, 0x1b0d, 0xe0c0, 0x0111, 0xf7e8, 0xa202, 0xe0c2,
+	0x0110, 0xe42e, 0x2895, 0xb43a, 0x3c95, 0x2896, 0xe42a, 0xf0fc,
+	0x2888, 0xae0e, 0x0887, 0xaf08, 0xe000, 0x0670, 0xe098, 0x2887,
+	0xa81e, 0x3c00, 0xa202, 0x5800, 0x4d04, 0x3d04, 0x2887, 0xa1aa,
+	0xe424, 0x2888, 0xa1ac, 0x2a88, 0xa80f, 0xa10f, 0xb636, 0xe424,
+	0xe0c0, 0x0042, 0x2a88, 0xaf07, 0xae0f, 0xe042, 0xe180, 0xe180,
+	0xca29, 0xf7f9, 0xce20, 0xd111, 0x0670, 0xd112, 0x0040, 0xd113,
+	0x0002, 0xca29, 0xf7f9, 0xe181, 0xe164, 0x0670, 0xa200, 0xc73f,
+	0x3d14, 0xe42e, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0x0000, 0x0001, 0x000c, 0x000a, 0x0010, 0x0028, 0x0018, 0x0014,
+	0x0020, 0x0050, 0x0012, 0x000f, 0x0040, 0x00a0, 0x0000, 0x0000,
+	0x0000, 0x0001, 0x000b, 0x000b, 0x000b, 0x0021, 0x000b, 0x000b,
+	0x000b, 0x0021, 0x000b, 0x000b, 0x0021, 0x0063, 0x0000, 0x0000,
+	0x0000, 0x0018, 0x0019, 0x001e, 0x0032, 0x003c, 0x0030, 0x0048,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0xe40e, 0x0020, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x0330, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x034a, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x003a, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058,
+	0xa200, 0xe0c2, 0x005a, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xa2fe,
+	0x3cee, 0x3cef, 0x3cec, 0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d,
+	0xce00, 0xf33e, 0xe41e, 0x0164, 0xe09e, 0xa202, 0xae3e, 0x9f07,
+	0xe0c0, 0x005c, 0xe0c1, 0x0059, 0x3eed, 0xa203, 0x5aed, 0xe052,
+	0xf08a, 0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00,
+	0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2, 0x0008, 0xf00e,
+	0x28ee, 0xe412, 0x013d, 0xe190, 0xe0c0, 0x005c, 0xe0c1, 0x0059,
+	0x3eed, 0xa203, 0x5aed, 0xe052, 0xf08a, 0xe0c1, 0x005d, 0xe055,
+	0xe0c3, 0x005d, 0xa202, 0xce00, 0xe0c0, 0x004a, 0xf08a, 0xe41e,
+	0x019c, 0xe408, 0x005c, 0xe40e, 0x0058, 0xe190, 0xe0c0, 0x043d,
+	0xa1ee, 0xf7d8, 0xe004, 0x0060, 0xe0c2, 0x0009, 0xa200, 0xe0c2,
+	0x0009, 0xe0c0, 0x000d, 0xf7e8, 0xe41e, 0x00b2, 0xe41e, 0x00e2,
+	0xe41e, 0x012c, 0xd071, 0x242a, 0xe181, 0xe41e, 0x0164, 0xe09e,
+	0xa202, 0x9f07, 0xe0c0, 0x0049, 0xe0c1, 0x005b, 0xa111, 0xf033,
+	0xe0c0, 0x0048, 0xe0c2, 0x0047, 0xe0c0, 0x0059, 0xae02, 0xe000,
+	0x0330, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a, 0xe008, 0xffff,
+	0x3cee, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11, 0xe056, 0x3cef,
+	0xe40e, 0x0058, 0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2,
+	0x0008, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xe0c0, 0x0059, 0xf7ea,
+	0xa11e, 0xf198, 0xa202, 0xe0c2, 0x0058, 0xe004, 0xca20, 0xae20,
+	0xe005, 0x210a, 0xe056, 0xe0c2, 0x0070, 0xe004, 0x0000, 0xae20,
+	0xe00a, 0x9cea, 0xe0c2, 0x0071, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+	0x0058, 0xf64e, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058, 0xd027,
+	0x0001, 0xe42e, 0xa200, 0xe0c1, 0x005b, 0xf21b, 0xa23c, 0xa103,
+	0xf37b, 0xa24c, 0xa103, 0xf34b, 0xa258, 0xa103, 0xf1db, 0xe004,
+	0x003a, 0xa103, 0xf2db, 0xe004, 0x003f, 0xa103, 0xf29b, 0xe004,
+	0x0045, 0xa103, 0xf25b, 0xa103, 0xf14b, 0xe004, 0x0063, 0xa103,
+	0xf1ab, 0xe004, 0x006a, 0xa107, 0xf1bb, 0xa200, 0xe0c1, 0x005e,
+	0xf17b, 0xa028, 0xf15e, 0xe0c1, 0x005e, 0xf12b, 0xa010, 0xf10e,
+	0xe004, 0x0049, 0xe0c1, 0x005e, 0xf0bb, 0xa010, 0xa103, 0xf08b,
+	0xa010, 0xf06e, 0xe0c1, 0x005e, 0xf03b, 0xe004, 0x0074, 0xae16,
+	0xe0c1, 0x0040, 0xe041, 0xce21, 0xd111, 0x0000, 0xd112, 0x2800,
+	0xd113, 0x000b, 0xe1e1, 0xe42e, 0xe41e, 0x023a, 0xe0c0, 0x0059,
+	0xa102, 0xe42a, 0xe0c0, 0x005b, 0xa810, 0xf058, 0xa206, 0xe41e,
+	0x0153, 0xe42e, 0xe004, 0x0350, 0xe67c, 0xe0c0, 0x005b, 0xa810,
+	0xf058, 0xa204, 0xe41e, 0x0153, 0xe42e, 0xe004, 0x0352, 0xe67c,
+	0xa200, 0xc401, 0xe188, 0x00eb, 0x3d11, 0xe161, 0x00f2, 0xe188,
+	0x0b0d, 0x3d11, 0xe42e, 0x3cec, 0xe0c0, 0x0041, 0xe005, 0x0000,
+	0xae11, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0c00, 0x88ec,
+	0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0059, 0xa106, 0xf048,
+	0xe004, 0x0076, 0xe42e, 0xe0c0, 0x0059, 0xa10c, 0xf038, 0xe004,
+	0x0071, 0xe004, 0x0070, 0xe42e, 0xe0c0, 0x006b, 0xe167, 0x01a0,
+	0x3d07, 0xe0c0, 0x0414, 0xe428, 0xe0c1, 0x0044, 0xa809, 0xae33,
+	0xe0c0, 0x006a, 0xe167, 0x01a0, 0x3517, 0x3d17, 0xe0c0, 0x006b,
+	0xe056, 0x3517, 0x3d07, 0xe42e, 0xe167, 0x01a0, 0x2907, 0xe0c2,
+	0x0151, 0xa204, 0xe0c2, 0x0150, 0xe0c0, 0x0150, 0xa804, 0xf7da,
+	0xa208, 0xe0c2, 0x0150, 0xe42e, 0xe0c0, 0x004a, 0xe42a, 0xe0c0,
+	0x005b, 0xa110, 0xf142, 0xe0c0, 0x0059, 0xa102, 0xe41a, 0x01be,
+	0xe0c0, 0x0059, 0xa106, 0xe41a, 0x01cb, 0xe0c0, 0x0047, 0xe0c2,
+	0x0048, 0xa200, 0xe0c2, 0x004a, 0xa202, 0xe42e, 0xe0c0, 0x0047,
+	0xe0c2, 0x0049, 0xa200, 0xe0c2, 0x004a, 0xe42e, 0xe0c0, 0x004a,
+	0xa802, 0xa23e, 0x3cf0, 0xa202, 0x58f0, 0xe0c2, 0x0078, 0xa220,
+	0xe0c2, 0x0070, 0xe42e, 0xe0c0, 0x004a, 0xa802, 0xa220, 0xe0c2,
+	0x0076, 0xa200, 0xe0c2, 0x0072, 0xa2fc, 0xe0c2, 0x0077, 0xa2fa,
+	0xe0c2, 0x0071, 0xe42e, 0xe0c0, 0x0045, 0xaf04, 0xa80e, 0xa104,
+	0xe428, 0xa202, 0xe0c2, 0x004a, 0xe0c0, 0x0111, 0xf7e8, 0xca28,
+	0xf7f8, 0xca48, 0xa802, 0xf7e8, 0xa208, 0xae14, 0xa102, 0xe190,
+	0xf7e2, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xe0c0, 0x041f, 0xf7e8,
+	0xa200, 0xe0c2, 0x041c, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xe004,
+	0x0078, 0xe0c2, 0x0009, 0xa200, 0xe0c2, 0x0009, 0xe0c0, 0x000d,
+	0xf7e8, 0xe42e, 0xc001, 0x3443, 0x3c42, 0xc000, 0xe42e, 0xc001,
+	0x2c43, 0x2e42, 0xc000, 0xe42a, 0x1c54, 0xf0b4, 0xe04a, 0xaf10,
+	0x1855, 0xf074, 0xe009, 0x00ff, 0x1a56, 0xf034, 0xa202, 0xe42e,
+	0xa2fe, 0xe42e, 0xe41e, 0x023a, 0xd160, 0x0620, 0xe004, 0x0019,
+	0xae18, 0xcec0, 0xe42e, 0xe41e, 0x024f, 0xe000, 0x0040, 0xce50,
+	0xa200, 0xd022, 0x00ff, 0xe184, 0x0236, 0xce52, 0xe190, 0xe41e,
+	0x0257, 0xe42e, 0xa204, 0xae22, 0xcc9e, 0xa200, 0xcc72, 0xcc8c,
+	0xcc8e, 0xe004, 0xa810, 0xae20, 0xe00a, 0x9322, 0xce4a, 0xd16f,
+	0x0003, 0xe190, 0xe190, 0xe190, 0xd16f, 0x0000, 0xe42e, 0xe004,
+	0x0030, 0xce50, 0xca50, 0xa802, 0xf7ea, 0xc000, 0xe42e, 0xe004,
+	0x0020, 0xce50, 0xe42e, 0xa200, 0xe0c2, 0x041c, 0xe42e, 0xe41e,
+	0x02bb, 0xe42a, 0xe0c0, 0x0061, 0xe008, 0x001f, 0xe00a, 0x0100,
+	0xe0c2, 0x041c, 0xe41e, 0x02f1, 0xe41e, 0x032b, 0xae12, 0xe0c2,
+	0x041e, 0xe41e, 0x031b, 0xe42e, 0xe41e, 0x02df, 0xe42a, 0xe0c0,
+	0x041f, 0xf7e8, 0xe0c0, 0x0210, 0xa804, 0xf118, 0xe0c0, 0x0215,
+	0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0216, 0xf0be, 0xe0c0, 0x0213,
+	0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0214, 0xf03e, 0xe0c0, 0x020b,
+	0xe00a, 0x0100, 0xe0c2, 0x041c, 0xe41e, 0x02f1, 0xe41e, 0x032b,
+	0xae12, 0xe0c1, 0x0210, 0xa803, 0xae15, 0xe056, 0xe0c1, 0x0204,
+	0xaf0b, 0xa87f, 0xae07, 0xe056, 0xe0c1, 0x0204, 0xa80f, 0xe056,
+	0xe0c2, 0x041e, 0xe41e, 0x031b, 0xe42e, 0xe0c0, 0x041f, 0xf7e8,
+	0xe0c0, 0x041f, 0xf7e8, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xa200,
+	0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xa203, 0xae19, 0xe052,
+	0xf1da, 0xe0c0, 0x0060, 0xaf08, 0xa806, 0xf18a, 0xe0c0, 0x0060,
+	0xa81e, 0xe016, 0xe0c1, 0x0060, 0xa821, 0xe017, 0xe056, 0xf0ea,
+	0xe0c0, 0x0044, 0xaf12, 0xa806, 0xe016, 0xe0c1, 0x0044, 0xaf17,
+	0xa803, 0xe056, 0xf03a, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xe0c0,
+	0x0044, 0xa203, 0xae19, 0xe052, 0xf0ba, 0xe41e, 0x02bb, 0xf088,
+	0xe0c0, 0x0044, 0xaf12, 0xa806, 0xf038, 0xa202, 0xe42e, 0xa200,
+	0xe42e, 0xe0c0, 0x041c, 0xe008, 0x00ff, 0xcca4, 0xc785, 0xe018,
+	0xe000, 0x0500, 0xa002, 0xae04, 0xe0c2, 0x041a, 0xa202, 0xe0c2,
+	0x0418, 0xe0c0, 0x0419, 0xf7ea, 0xa202, 0xe0c2, 0x0418, 0xe0c0,
+	0x0419, 0xf7ea, 0xe0c0, 0x041b, 0xaf20, 0xa01e, 0xaf08, 0xae28,
+	0xe0c1, 0x041b, 0xe009, 0xffff, 0xa01f, 0xaf09, 0xae09, 0xe056,
+	0xe0c2, 0x041d, 0xe42e, 0xe0c0, 0x041c, 0xe00a, 0x0200, 0xe0c2,
+	0x041c, 0xa228, 0xa102, 0xf7f0, 0xe0c0, 0x041c, 0xe00c, 0x0200,
+	0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xaf04, 0xa802, 0xe42e,
+	0xe40e, 0x11ed, 0xe40e, 0x0354, 0xe40e, 0x0358, 0xe40e, 0x035c,
+	0xe40e, 0x0364, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x0368,
+	0xe40e, 0x036a, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe41e, 0x04b3, 0xe40e, 0x00a4,
+	0xe41e, 0x04d9, 0xe40e, 0x00a4, 0xe41e, 0x025b, 0xe41e, 0x04da,
+	0xe41e, 0x02ad, 0xe40e, 0x00a4, 0xe41e, 0x0557, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe41e, 0x05f4, 0xe40e, 0x00a4, 0xe0c0, 0x0059,
+	0xa102, 0xf28a, 0xa102, 0xe42a, 0xa102, 0xf05a, 0xa102, 0xe40a,
+	0x03ac, 0xe42e, 0xe0c0, 0x0060, 0xaf08, 0x30c1, 0xaf02, 0x30c2,
+	0xe0c0, 0x0060, 0xa81e, 0x3cc0, 0xe0c0, 0x0061, 0xa83e, 0x3cc4,
+	0xe0c0, 0x0065, 0xaf04, 0x30a5, 0xe0c0, 0x0065, 0xaf06, 0xa806,
+	0x3ca3, 0xe0c0, 0x0065, 0xaf0a, 0x30d8, 0xe0c0, 0x0066, 0x3ca4,
+	0xe42e, 0xc001, 0xe0c0, 0x0060, 0x3400, 0x3c01, 0xe0c0, 0x0061,
+	0xae14, 0x3406, 0x3c07, 0xc000, 0xe0c0, 0x0062, 0x3009, 0xe0c0,
+	0x0065, 0xaf0a, 0x30d8, 0xe42e, 0xe41e, 0x05d2, 0xe41e, 0x0174,
+	0xca28, 0xf7f8, 0xe0c0, 0x0042, 0xce20, 0xd111, 0x0200, 0xd112,
+	0x00c0, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe0c0, 0x0060, 0x3ca8,
+	0xe0c0, 0x0061, 0x3ca9, 0xe0c0, 0x006e, 0xe41e, 0x020a, 0xe42e,
+	0xe0c0, 0x0059, 0xa102, 0xe40a, 0x043b, 0xa102, 0xe42a, 0xa102,
+	0xf05a, 0xa102, 0xe40a, 0x047e, 0xe42e, 0x245d, 0x4c5e, 0xe0c2,
+	0x006f, 0x285b, 0xe0c2, 0x007a, 0x20a6, 0x4ca7, 0xa002, 0x34a6,
+	0x3ca7, 0xe0c2, 0x0070, 0x28a2, 0xe0c2, 0x0071, 0x28a0, 0xe0c2,
+	0x0072, 0xe41e, 0x0497, 0xe0c2, 0x0073, 0xa200, 0xe0c2, 0x0074,
+	0x280c, 0x2ad9, 0xae21, 0xe056, 0x2a4f, 0xae23, 0xe056, 0x2ada,
+	0xae29, 0xe056, 0xe0c2, 0x0076, 0xe41e, 0x0634, 0xe0c2, 0x0051,
+	0xe41e, 0x0637, 0xe0c2, 0x0052, 0x28a1, 0xe0c2, 0x0077, 0x2aaa,
+	0xe161, 0x02d8, 0x2111, 0x4d11, 0xf02b, 0xae02, 0xe0c2, 0x0078,
+	0x2111, 0x4d11, 0xf02b, 0xae02, 0xe0c2, 0x0079, 0x20ab, 0x4cac,
+	0xe0c2, 0x007c, 0xe167, 0x02dc, 0x2117, 0x4d17, 0xe0c2, 0x007e,
+	0x2117, 0x4d17, 0xe0c2, 0x007d, 0x28d4, 0xae20, 0x4cd5, 0x2ad1,
+	0xa807, 0xb7f6, 0xe0c2, 0x0078, 0x28d2, 0xae20, 0x4cd3, 0x2ad1,
+	0xa819, 0xb7f6, 0xe0c2, 0x0079, 0xc84a, 0xc84d, 0xae20, 0xe056,
+	0xe0c2, 0x0053, 0xe42e, 0xa200, 0xe0c2, 0x006d, 0x280c, 0xe0c2,
+	0x0070, 0x245d, 0x4c5e, 0xe0c2, 0x0071, 0x20ab, 0x4cac, 0xe0c2,
+	0x0072, 0xa208, 0x0809, 0xe0c2, 0x0073, 0xa202, 0x3cb3, 0x28b3,
+	0xe0c2, 0x0074, 0xa200, 0xe0c2, 0x0075, 0xa200, 0xe0c2, 0x0076,
+	0xa200, 0xe0c2, 0x0077, 0x280c, 0xe016, 0x58f0, 0xe0c2, 0x0078,
+	0xe161, 0x02dc, 0x2111, 0x4d11, 0xe0c2, 0x007a, 0x2111, 0x4d11,
+	0xe0c2, 0x0079, 0x2881, 0xae1c, 0x2a82, 0xe056, 0xae02, 0x2a80,
+	0xe056, 0xe0c2, 0x006e, 0x2826, 0xe016, 0xae10, 0x4c2d, 0xae10,
+	0x4c2c, 0xe0c2, 0x007b, 0xe41e, 0x047f, 0xe42e, 0xe42e, 0xe0c0,
+	0x0065, 0xaf0a, 0xa802, 0xf13a, 0xe162, 0x04c8, 0x2ce4, 0x3d12,
+	0x2ce5, 0x3d12, 0xe0c0, 0x006b, 0xca29, 0xf7f9, 0xce20, 0xd111,
+	0x04c8, 0xd112, 0x0004, 0xd113, 0x0000, 0xe1e1, 0xe42e, 0x2826,
+	0xae02, 0x4c3c, 0xae06, 0x4cd7, 0x2a43, 0xae07, 0x4e34, 0xae04,
+	0x4c3e, 0xae02, 0x4c3a, 0xae02, 0x4c39, 0xae04, 0x4c3d, 0xae02,
+	0x4c32, 0xae24, 0xe056, 0x2a73, 0xe40b, 0x04b2, 0xa205, 0x1a33,
+	0xae21, 0xe056, 0xe42e, 0xa200, 0x3c0c, 0xa200, 0xcc4a, 0xcc4c,
+	0xe41e, 0x05de, 0xe41e, 0x061f, 0xe41e, 0x036e, 0xa200, 0x3c0c,
+	0xe41e, 0x0f17, 0xe41e, 0x0900, 0xf0dd, 0xe41e, 0x0914, 0xe41e,
+	0x0bd4, 0xe41e, 0x0aab, 0xf06d, 0xe41e, 0x0580, 0xf03a, 0xa202,
+	0x3c0c, 0xe41e, 0x0a4b, 0xe41e, 0x1138, 0xe41e, 0x03c8, 0xe16a,
+	0xe42e, 0xe42e, 0xa202, 0x3c0c, 0xe41e, 0x036e, 0xe41e, 0x06a0,
+	0xe41e, 0x055e, 0xe41e, 0x1435, 0xe41e, 0x1468, 0xe41e, 0x060d,
+	0xe41e, 0x1236, 0xe41e, 0x14c9, 0xe41e, 0x0f21, 0xe41e, 0x0580,
+	0xe40a, 0x0530, 0xe41e, 0x0986, 0xe40a, 0x0530, 0xf0a0, 0x283b,
+	0xe016, 0x4432, 0x2a32, 0x563b, 0x3e3b, 0xf758, 0xe40e, 0x0530,
+	0xe41e, 0x020f, 0xe404, 0x0530, 0xe41e, 0x0a54, 0xf0da, 0xe41e,
+	0x0a4b, 0xe41e, 0x0680, 0xe41e, 0x0643, 0xa2fe, 0x3ca1, 0xa202,
+	0x3cd9, 0xe40e, 0x0530, 0xe41e, 0x0620, 0xe408, 0x0530, 0xe41e,
+	0x0625, 0x283b, 0xe41a, 0x070e, 0xe404, 0x054e, 0x283b, 0xe41a,
+	0x0749, 0xe41e, 0x078b, 0x283b, 0xe41a, 0x064d, 0x2832, 0x543b,
+	0x3c3b, 0xf07a, 0x2834, 0x3c43, 0x2840, 0x3c44, 0xe40e, 0x04f2,
+	0xe41e, 0x1522, 0x2a90, 0xf0c5, 0x2891, 0xe046, 0xf024, 0xf05e,
+	0x2a91, 0x2890, 0x3c91, 0x3e90, 0x2891, 0xe41e, 0x0813, 0xe41e,
+	0x062d, 0xa200, 0xe41e, 0x1385, 0xe41e, 0x0eea, 0xf05a, 0xe41e,
+	0x0680, 0xa200, 0x3cb3, 0xe41e, 0x0662, 0x3ca2, 0x28a2, 0x3cb4,
+	0xe41e, 0x03c8, 0xe41e, 0x06b5, 0xe41e, 0x1138, 0xe42e, 0xe41e,
+	0x036e, 0xe41e, 0x14c3, 0xe41e, 0x076d, 0xe42e, 0xa2fe, 0x3c46,
+	0x3c5c, 0xa200, 0x3ca0, 0x3c3b, 0x3c43, 0x3c44, 0x3ce4, 0x3cd1,
+	0x3cd2, 0x3cd3, 0x3cd4, 0x3cd5, 0x3cd6, 0xa200, 0x3cb9, 0x3cd9,
+	0x3cda, 0xe41e, 0x0626, 0xe41e, 0x062d, 0xa2fc, 0x3ca1, 0xa2fa,
+	0x3ca2, 0x2872, 0x2a73, 0xb616, 0x3c72, 0xa2fe, 0x3c90, 0xe42e,
+	0xa202, 0x3cf0, 0x2855, 0xe406, 0x05d0, 0xe002, 0x0078, 0xe400,
+	0x05d0, 0xa204, 0x3cf0, 0x2856, 0xe406, 0x05d0, 0xe002, 0x0078,
+	0xe400, 0x05d0, 0x2854, 0xe002, 0x1fe0, 0xf3b0, 0xe0c0, 0x0059,
+	0xa106, 0xf358, 0xe41e, 0x0ed0, 0xf04a, 0xe41e, 0x01db, 0xf31e,
+	0x28b7, 0x3cb8, 0x2809, 0xf0ba, 0xe41e, 0x06cb, 0x3c11, 0xe41e,
+	0x06cb, 0x3c14, 0x2811, 0x2a14, 0xb7ea, 0xf07e, 0xa2fa, 0x3c11,
+	0xe41e, 0x06cb, 0x3c14, 0x2814, 0x2aa1, 0xb7e9, 0x3ea1, 0x2811,
+	0xe41e, 0x06f6, 0x2811, 0xe41e, 0x06fe, 0x2811, 0xe41e, 0x0706,
+	0x2814, 0xe41e, 0x06f6, 0x2814, 0xe41e, 0x06fe, 0x2814, 0xe41e,
+	0x0706, 0x28b8, 0x3cb7, 0x28a1, 0xa002, 0xf03a, 0xa202, 0xe42e,
+	0xa200, 0xe42e, 0xe167, 0x02d0, 0xe166, 0x0064, 0xd022, 0x0003,
+	0xe184, 0x05dc, 0x9e16, 0x3517, 0x3d17, 0xe42e, 0xe41e, 0x0148,
+	0xe16a, 0xd130, 0x0002, 0xa2fe, 0x34a6, 0x3ca7, 0x3c28, 0xa200,
+	0x3caa, 0xe161, 0x02d8, 0xc703, 0x3d11, 0x3cab, 0x3cac, 0xe161,
+	0x02dc, 0xc703, 0x3d11, 0xe42e, 0xe41e, 0x076d, 0xa200, 0x3e0c,
+	0xe167, 0x0310, 0xe166, 0x0054, 0xa200, 0x3c00, 0x28a8, 0xa102,
+	0xcc44, 0xe184, 0x060a, 0x9e06, 0x5c00, 0xa802, 0xb690, 0x3d17,
+	0x2800, 0xa002, 0x3c00, 0xe190, 0xe42e, 0xa200, 0xcc44, 0xcc4a,
+	0xcc4c, 0xcc72, 0xd130, 0x0002, 0xd03a, 0x0002, 0xd04b, 0x0001,
+	0xd04c, 0x0000, 0xd008, 0x0000, 0xe41e, 0x025f, 0xe42e, 0xe42e,
+	0x2a3b, 0x2873, 0xb611, 0x3e3b, 0xe42e, 0xe42e, 0xe41e, 0x1121,
+	0xe0c0, 0x0048, 0x34ba, 0x3cbb, 0xe42e, 0xe41e, 0x1121, 0xe0c0,
+	0x0048, 0x34bc, 0x3cbd, 0xe42e, 0x24ba, 0x4cbb, 0xe42e, 0x24bc,
+	0x4cbd, 0xe42e, 0xe41e, 0x1121, 0xc001, 0xe0c0, 0x0048, 0x341b,
+	0x3c1c, 0xc000, 0xe42e, 0xa200, 0xceaa, 0xc001, 0x241b, 0x4c1c,
+	0xc000, 0xe0c2, 0x0048, 0xe42e, 0xe42e, 0x2809, 0xf088, 0x2a42,
+	0x28a1, 0xf0b9, 0xe166, 0x0301, 0x2916, 0xf07e, 0x2a42, 0x28a1,
+	0xf049, 0x28d0, 0x2aa1, 0x3ed0, 0x3cb6, 0xe41e, 0x06fe, 0xe41e,
+	0x068e, 0xe42e, 0x28b3, 0xf04a, 0xa102, 0x3cb3, 0xf14e, 0x28b2,
+	0xf12a, 0x28b1, 0xe000, 0x02e0, 0xe092, 0x28b1, 0xa002, 0x3cb1,
+	0xa122, 0xf028, 0x3cb1, 0x28b2, 0xa102, 0x3cb2, 0x2901, 0xe049,
+	0x1aa8, 0xe425, 0xe41e, 0x0eea, 0xe049, 0xa2fa, 0xb7f2, 0xe42e,
+	0xa200, 0x3c42, 0xa202, 0x3c41, 0xa2fc, 0x3c14, 0x3ca1, 0xe41e,
+	0x0749, 0xe41e, 0x064d, 0x28b6, 0xe424, 0xf73e, 0x28b6, 0xe424,
+	0x28b0, 0xe000, 0x02e0, 0xe092, 0x28b6, 0x3d01, 0x28b0, 0xa002,
+	0x3cb0, 0xa122, 0xf028, 0x3cb0, 0x28b2, 0xa002, 0x3cb2, 0xe42e,
+	0xa200, 0x3c00, 0xe004, 0x0054, 0xe09c, 0x28a8, 0xa102, 0xcc44,
+	0xe184, 0x06b3, 0x9e06, 0x5c00, 0xa802, 0xf048, 0x2800, 0xe41e,
+	0x0706, 0x2a00, 0xa003, 0x3e00, 0xe42e, 0xe167, 0x0310, 0xe004,
+	0x0054, 0xe09c, 0x28a8, 0xa102, 0xcc44, 0xa200, 0x3c00, 0xe184,
+	0x06c8, 0x2b17, 0xaf05, 0xa803, 0x5a00, 0xe056, 0x2a00, 0xa003,
+	0x3e00, 0x9f06, 0xe42e, 0x28b7, 0x3c00, 0x2800, 0xe000, 0x0310,
+	0xe092, 0x2901, 0xf0da, 0x2800, 0xa002, 0x3c00, 0x18a8, 0xf038,
+	0xa200, 0x3c00, 0x2800, 0x18b7, 0xf718, 0xa2fe, 0xe42e, 0xa20e,
+	0x3d01, 0x2800, 0xa002, 0x3cb7, 0x18a8, 0xf038, 0xa200, 0x3cb7,
+	0x2800, 0xe42e, 0xe161, 0x0310, 0x28a8, 0xa102, 0xcc44, 0xe184,
+	0x06f4, 0x2911, 0xe016, 0xe428, 0xe190, 0xe42e, 0xe424, 0xe000,
+	0x0310, 0xe092, 0x2901, 0xa80c, 0x3d01, 0xe42e, 0xe424, 0xe000,
+	0x0310, 0xe092, 0x2901, 0xa80a, 0x3d01, 0xe42e, 0xe424, 0xe000,
+	0x0310, 0xe092, 0x2901, 0xa806, 0x3d01, 0xe42e, 0x28a2, 0x3cb4,
+	0xa2fa, 0x3c11, 0x3c14, 0x2809, 0xf0d8, 0xe41e, 0x06cb, 0xf1e4,
+	0x3ca1, 0x3c14, 0xa2fa, 0x3c11, 0x2a42, 0x28a1, 0xe419, 0x06f6,
+	0xf13e, 0x2842, 0xf0a8, 0xe41e, 0x06cb, 0xf104, 0x3c14, 0xe41e,
+	0x06fe, 0x2814, 0xe41e, 0x0706, 0xe41e, 0x06cb, 0xf074, 0x3ca1,
+	0x3c11, 0xe41e, 0x06f6, 0xa200, 0xe42e, 0x2814, 0xe41e, 0x06f6,
+	0x2814, 0xe41e, 0x06fe, 0x2814, 0xe41e, 0x0706, 0x2811, 0xe41e,
+	0x06f6, 0x2811, 0xe41e, 0x06fe, 0x2811, 0xe41e, 0x0706, 0xa2fe,
+	0xe42e, 0x2842, 0xf148, 0xe166, 0x0300, 0x2916, 0xb608, 0x3c12,
+	0x2814, 0x3c13, 0xe166, 0x0301, 0x290e, 0xe41e, 0x06f6, 0xe166,
+	0x0300, 0x2916, 0x3d0e, 0x2814, 0x3d06, 0xe42e, 0xe166, 0x0300,
+	0x2916, 0xb608, 0x3c13, 0x2916, 0xb608, 0x3c12, 0xe42e, 0xa2fa,
+	0xe166, 0x0300, 0xc701, 0x3d16, 0xe42e, 0xa2fa, 0x3c12, 0x3c13,
+	0x3cb4, 0x3c11, 0x3cd0, 0xa202, 0x3cb3, 0xa200, 0x3cb1, 0x3cb0,
+	0x3cb2, 0x3cb5, 0xe166, 0x02e0, 0xc710, 0x3d16, 0xe41e, 0x0767,
+	0xa200, 0x3cb7, 0xe161, 0x0310, 0x2aa8, 0xe42b, 0xa103, 0x3e50,
+	0x8650, 0x3d11, 0xe42e, 0xe16a, 0x2a3b, 0xf089, 0x2814, 0x2a09,
+	0xf02b, 0x28a1, 0xa2ff, 0xe41e, 0x1542, 0xe41e, 0x1435, 0xe41e,
+	0x1468, 0x283b, 0xe41a, 0x025f, 0xe41e, 0x1252, 0xe41e, 0x08df,
+	0xe41e, 0x0a63, 0xf164, 0x283b, 0xf03a, 0xa2fe, 0x3c5c, 0x2846,
+	0x2a5c, 0xe046, 0xe402, 0x07b1, 0x2c54, 0x3c47, 0xe41e, 0x07ef,
+	0xf0ee, 0xe41e, 0x11de, 0xe41e, 0x07c5, 0xe41e, 0x08fb, 0xf69a,
+	0x2c54, 0x3c47, 0x1c57, 0xe410, 0x07ef, 0xf01e, 0xe16a, 0xd182,
+	0x0007, 0xe0c0, 0x0111, 0xf7e8, 0xe42e, 0xe41e, 0x089a, 0xf26d,
+	0xe41e, 0x08a7, 0xf23d, 0xa202, 0x3c48, 0x2c47, 0x1c57, 0xe410,
+	0x07ef, 0xe41e, 0x08b6, 0xf1ad, 0x2848, 0xa102, 0xe418, 0x0e87,
+	0x2848, 0xa102, 0xe41a, 0x0e1c, 0xf11d, 0x2c48, 0xa102, 0x3c48,
+	0xe41e, 0x08e8, 0xe41e, 0x08fb, 0xe428, 0xe41e, 0x11c2, 0xe428,
+	0x2848, 0xe41a, 0x089a, 0xf02d, 0xf65e, 0xe16a, 0xe42e, 0x2890,
+	0xf152, 0x2826, 0xf0d8, 0x283d, 0xa106, 0xf0a8, 0x2856, 0x2a53,
+	0xa01f, 0xaf09, 0xe046, 0xf04a, 0xa2fe, 0x3c90, 0xf07e, 0x2859,
+	0xe40a, 0x0804, 0xe002, 0x0001, 0x3c90, 0xe41e, 0x0eaa, 0xe41e,
+	0x08e8, 0xe41e, 0x08fb, 0xf058, 0x2c47, 0x1c57, 0xf02a, 0xf76e,
+	0x2859, 0x3c91, 0xe42e, 0xe41e, 0x02ad, 0x2812, 0xf032, 0x2814,
+	0xb608, 0x3c95, 0x2814, 0x3c9c, 0xa200, 0x3c92, 0xe41e, 0x0835,
+	0xe41e, 0x0863, 0xa204, 0x3c92, 0xe41e, 0x0835, 0xe41e, 0x0863,
+	0xe41e, 0x032b, 0xf078, 0xa206, 0x3c92, 0xe41e, 0x0835, 0xe41e,
+	0x0863, 0xe0c0, 0x0800, 0xf7e8, 0xe42e, 0xa200, 0x3c93, 0x3c9a,
+	0x2892, 0x3c94, 0x3c9b, 0x2890, 0xae08, 0x5832, 0x3c96, 0x3c9d,
+	0xa200, 0x3c97, 0x3c9e, 0x2891, 0xa002, 0x1890, 0xae08, 0x5832,
+	0x2a92, 0xa101, 0xf02b, 0xaf02, 0x3c98, 0x2855, 0xae08, 0x3c99,
+	0x2892, 0xa100, 0xf07a, 0xe41e, 0x032b, 0xf048, 0x2899, 0xaf02,
+	0x3c99, 0x2892, 0xa100, 0xf07a, 0x2896, 0xaf02, 0x3c96, 0x289d,
+	0xaf02, 0x3c9d, 0xe42e, 0xe0c0, 0x0800, 0xf7e8, 0xa202, 0xe0c2,
+	0x0802, 0xe41e, 0x032b, 0xae20, 0xe0c2, 0x0804, 0xa220, 0xae20,
+	0xe005, 0x1010, 0xe056, 0xe0c2, 0x0805, 0xa200, 0xe0c2, 0x0806,
+	0xa202, 0xae04, 0x4c93, 0xae04, 0x4c94, 0xae10, 0x4c95, 0xe0c2,
+	0x0807, 0x2096, 0x4c97, 0xe0c2, 0x0808, 0x2098, 0x4c99, 0xe0c2,
+	0x0809, 0xa202, 0xae04, 0x4c9a, 0xae04, 0x4c9b, 0xae10, 0x4c9c,
+	0xe0c2, 0x080a, 0x209d, 0x4c9e, 0xe0c2, 0x080b, 0xa202, 0xe0c2,
+	0x0800, 0xe42e, 0xa201, 0xb800, 0xe42d, 0xf08a, 0xa17e, 0xf7ca,
+	0xa102, 0xa87e, 0xe041, 0x3e48, 0xe42e, 0xa043, 0xf75e, 0x8455,
+	0x8246, 0xe018, 0x2e48, 0xa103, 0xe042, 0x3c47, 0x2c47, 0x1c54,
+	0xf042, 0x2c47, 0x1c57, 0xe422, 0xe16b, 0xe42e, 0x2840, 0xf04a,
+	0x2c48, 0xa102, 0xf028, 0xe42e, 0xe16b, 0xe42e, 0xba48, 0x3c64,
+	0x2814, 0x3c01, 0x2809, 0xf03a, 0x28a1, 0x3c01, 0x2801, 0xe41e,
+	0x153c, 0xf052, 0x2801, 0x2a64, 0xe41e, 0x1542, 0xae02, 0x4c65,
+	0xae04, 0xcb23, 0xa807, 0xe056, 0xcf22, 0xba40, 0xf06a, 0xba4e,
+	0xba40, 0xf03a, 0xba4e, 0xf7de, 0xd182, 0x0007, 0xe42e, 0xa200,
+	0x3c57, 0x3c58, 0x3c59, 0xcf64, 0xcf62, 0xd1b3, 0x0001, 0xe42e,
+	0x2c57, 0xa002, 0x3c57, 0xcf64, 0x2c58, 0xa002, 0x3c58, 0x1c55,
+	0xf078, 0xd1b3, 0x0004, 0x3c58, 0x2c59, 0xa002, 0x3c59, 0x2458,
+	0x4c59, 0xcf62, 0xe42e, 0x2c59, 0x1c45, 0xe01a, 0xe016, 0xe42e,
+	0xa23e, 0x3cf0, 0xe41e, 0x0ed0, 0xf0c8, 0xe41e, 0x0f9a, 0xe41e,
+	0x0ec2, 0xe002, 0x00b3, 0xf778, 0xe41e, 0x0b06, 0xf04a, 0xe42e,
+	0xe41e, 0x01db, 0xe16b, 0xe42e, 0xe41e, 0x1172, 0xe41e, 0x0ec2,
+	0xe002, 0x00b3, 0xf28a, 0xe41e, 0x0ec2, 0xe002, 0x00b8, 0xf28a,
+	0xe41e, 0x0ec2, 0xe002, 0x00b2, 0xf2aa, 0xe41e, 0x0ec2, 0xe002,
+	0x00b5, 0xe40a, 0x097b, 0xe41e, 0x0ec2, 0xe002, 0x0000, 0xf11a,
+	0xe41e, 0x0ec2, 0xe002, 0x00b7, 0xf04a, 0xe41e, 0x0f61, 0xf5de,
+	0xe41e, 0x0ed0, 0xe408, 0x093f, 0xe41e, 0x0f9a, 0xf56e, 0xf01e,
+	0xe40e, 0x0983, 0xe41e, 0x0f9a, 0xe41e, 0x0b06, 0xf4ee, 0xe41e,
+	0x0f9a, 0xa200, 0x3c3b, 0xe41e, 0x0b60, 0xf47e, 0xe41e, 0x0f9a,
+	0xba3e, 0x340a, 0x3c0b, 0xe004, 0x4454, 0x180a, 0xf078, 0xe004,
+	0x4731, 0x180b, 0xf038, 0xe40e, 0x0973, 0xe004, 0x4741, 0x180a,
+	0xf0c8, 0xe004, 0x3934, 0x180b, 0xf088, 0xba7e, 0xba0e, 0xa10c,
+	0xe40a, 0x0977, 0xa202, 0x3cd6, 0x28d8, 0xe40a, 0x0914, 0xe41e,
+	0x0d26, 0xe40e, 0x0914, 0xe41e, 0x0e05, 0xe40e, 0x0914, 0xe41e,
+	0x0dd4, 0xe40e, 0x0914, 0xe41e, 0x0f9a, 0xe41e, 0x0beb, 0xf06d,
+	0xe16a, 0xe40e, 0x0914, 0xe16a, 0xe42e, 0xe42e, 0xa204, 0x3c4f,
+	0xa200, 0x3c5f, 0xe41e, 0x0ed0, 0xe408, 0x09ca, 0xe41e, 0x1172,
+	0xe41e, 0x0ec2, 0xe002, 0x00b3, 0xe40a, 0x09e8, 0xe41e, 0x0ec2,
+	0xe002, 0x00b8, 0xe40a, 0x09f2, 0xe41e, 0x0ec2, 0xe002, 0x00b2,
+	0xe40a, 0x09f8, 0xe41e, 0x0ec2, 0xe002, 0x00b5, 0xe40a, 0x0a25,
+	0xe41e, 0x0ec2, 0xe002, 0x0000, 0xe40a, 0x09ce, 0xe41e, 0x0ec2,
+	0xe002, 0x0001, 0xe404, 0x09bf, 0xe41e, 0x0ec2, 0xe002, 0x00af,
+	0xe404, 0x0a2c, 0xe41e, 0x0ec2, 0xe002, 0x00b7, 0xf05a, 0xe41e,
+	0x0f61, 0xe40e, 0x098a, 0xe41e, 0x0ed0, 0xe408, 0x09ca, 0xe41e,
+	0x0f9a, 0xf41e, 0xe41e, 0x01db, 0xe40e, 0x0a43, 0xe41e, 0x0e12,
+	0xe41e, 0x0f9a, 0xe41e, 0x0b6b, 0xa202, 0xb61a, 0x3c5f, 0xe41d,
+	0x0e19, 0x2873, 0xe418, 0x1169, 0x28a3, 0x4ca5, 0xe01a, 0x4473,
+	0xe408, 0x0a47, 0x2873, 0xe408, 0x0a41, 0xe16a, 0xe40e, 0x098a,
+	0xa200, 0x3c3b, 0xe41e, 0x063a, 0xe41e, 0x0f9a, 0xe41e, 0x0b06,
+	0xe40e, 0x098a, 0xe41e, 0x0f9a, 0xe41e, 0x0b60, 0xe40e, 0x098a,
+	0xe41e, 0x0f9a, 0xba3e, 0x340a, 0x3c0b, 0xe004, 0x4454, 0x180a,
+	0xf078, 0xe004, 0x4731, 0x180b, 0xf038, 0xe40e, 0x0a1d, 0xe004,
+	0x4741, 0x180a, 0xf0c8, 0xe004, 0x3934, 0x180b, 0xf088, 0xba7e,
+	0xba0e, 0xa10c, 0xe40a, 0x0a21, 0xa202, 0x3cd6, 0x28d8, 0xe40a,
+	0x098a, 0xe41e, 0x0d26, 0xe40e, 0x098a, 0xe41e, 0x0e05, 0xe40e,
+	0x098a, 0xe41e, 0x0dd4, 0xe40e, 0x098a, 0xe41e, 0x0f9a, 0xe41e,
+	0x0beb, 0xe16a, 0xe40e, 0x098a, 0x285f, 0xe408, 0x0a33, 0xe41e,
+	0x0f9a, 0xe40e, 0x098a, 0xe41e, 0x0bd4, 0xe41e, 0x0aab, 0xe41e,
+	0x0ae2, 0xf08a, 0xf0d4, 0xe41e, 0x0f9a, 0xa202, 0x3c5f, 0xe40e,
+	0x098a, 0xa202, 0xe42e, 0xe41e, 0x0aab, 0xa200, 0xe42e, 0xa2fd,
+	0x3ea1, 0xa2fe, 0xe42e, 0xe165, 0x0350, 0x2855, 0x3d15, 0x2856,
+	0x3d15, 0x2826, 0x3d15, 0xe42e, 0xe165, 0x0350, 0x2855, 0x1915,
+	0xf088, 0x2856, 0x1915, 0xf058, 0x2826, 0x1915, 0xf028, 0xe42e,
+	0xa202, 0x3cda, 0xe42e, 0xe41e, 0x1172, 0xe41e, 0x0ec2, 0xe002,
+	0x00b3, 0xe40a, 0x0a9b, 0xe41e, 0x0ec2, 0xe002, 0x00b8, 0xe40a,
+	0x0a9b, 0xe41e, 0x0ec2, 0xe002, 0x00b2, 0xe40a, 0x0a9b, 0xe41e,
+	0x0ec2, 0xe002, 0x00b5, 0xe40a, 0x0a9b, 0xe41e, 0x0ec2, 0xe002,
+	0x0000, 0xe40a, 0x0a9b, 0xe41e, 0x0ec2, 0xe002, 0x0001, 0xe404,
+	0x0a9b, 0xe41e, 0x0ec2, 0xe002, 0x00af, 0xe404, 0x0a9d, 0xe41e,
+	0x0ec2, 0xe002, 0x00b7, 0xe408, 0x0a9b, 0xe41e, 0x0ed0, 0xe40a,
+	0x0aa9, 0xe41e, 0x01db, 0xe40e, 0x0aa9, 0x2846, 0x3c5c, 0xe41e,
+	0x0f9a, 0xe41e, 0x0ec2, 0xa102, 0x3c46, 0xe41e, 0x08be, 0xa200,
+	0xe42e, 0xa2fe, 0xe42e, 0xe166, 0x02dc, 0xe167, 0x02de, 0xa2fe,
+	0x3516, 0x3d0e, 0x3517, 0x3d0f, 0x2828, 0xe424, 0xa231, 0xa104,
+	0xf0e6, 0xa102, 0xb435, 0xf0ba, 0xa104, 0xb4cd, 0xf086, 0xa102,
+	0xf05a, 0xa104, 0xf026, 0xe42e, 0xa015, 0xa035, 0x3e50, 0x8450,
+	0x8229, 0xe018, 0x3c50, 0x8450, 0xe182, 0x03e8, 0xe018, 0x3517,
+	0x3d17, 0xe005, 0x03e9, 0x2828, 0xa102, 0xf06a, 0xa106, 0xf04a,
+	0xa106, 0xf02a, 0xa103, 0x3e50, 0x8450, 0x822a, 0xe018, 0x3516,
+	0x3d16, 0xe42e, 0x28a5, 0xf0aa, 0x2844, 0x443b, 0x4c40, 0xe40a,
+	0x0aeb, 0xe40e, 0x0b00, 0xe40e, 0x0b02, 0x28a3, 0xe40a, 0x0b00,
+	0xa102, 0xf05a, 0xa102, 0xf09a, 0xa102, 0xf0aa, 0x2844, 0x443b,
+	0x4c40, 0xe408, 0x0b00, 0xf04e, 0x2842, 0xe40a, 0x0b00, 0xf05e,
+	0xa200, 0xe42e, 0xa202, 0xe42e, 0xa2fe, 0xe42e, 0xa200, 0x3c25,
+	0x3c27, 0x3ce3, 0xa202, 0x3c29, 0x3c2a, 0x2825, 0x3c0d, 0x285d,
+	0x3c0e, 0x285e, 0x3c0f, 0x2a5d, 0xba56, 0xe40a, 0x0b4d, 0x3c5d,
+	0xe002, 0x0780, 0xf046, 0x3e5d, 0xf31e, 0xe190, 0x285d, 0x3c52,
+	0xa01e, 0xaf08, 0x3c55, 0x2a5e, 0xba56, 0xf28a, 0x3c5e, 0xe002,
+	0x0480, 0xf036, 0x3e5e, 0xf22e, 0x285e, 0x3c53, 0xa01e, 0xaf08,
+	0x3c56, 0x3c45, 0x8455, 0x8256, 0xe018, 0x3c54, 0xa206, 0x3cf0,
+	0xba46, 0xf14a, 0x34ab, 0x3cac, 0xa208, 0x3cf0, 0xba46, 0xf0ea,
+	0x3c28, 0xa20a, 0x3cf0, 0xba62, 0xba40, 0xf08a, 0xba52, 0xba40,
+	0xe41e, 0x0cdf, 0xf038, 0xa202, 0xe42e, 0x280d, 0x3c25, 0x280e,
+	0x3c5d, 0xa01e, 0xaf08, 0x3c55, 0x280f, 0x3c5e, 0xa01e, 0xaf08,
+	0x3c56, 0x3c45, 0x8455, 0x8256, 0xe018, 0x3c54, 0xa200, 0xe42e,
+	0xa202, 0x3ce3, 0xba40, 0xba48, 0xba4a, 0xba40, 0xba4a, 0xba4a,
+	0xba40, 0xba40, 0xe42e, 0xe0c1, 0x0059, 0xa107, 0xf049, 0x284f,
+	0xa802, 0x3c4f, 0xa204, 0x3ce3, 0x283b, 0xf0a8, 0xa200, 0x3c73,
+	0xba18, 0xa80e, 0xe40a, 0x0bcf, 0xba52, 0x3c72, 0xf08e, 0xba12,
+	0x1872, 0xf04a, 0x3c73, 0xe40e, 0x0bcf, 0xba52, 0xba44, 0xe40a,
+	0x0bcf, 0x2a34, 0x3e2f, 0xa102, 0xe049, 0xaf05, 0xe409, 0x0bcf,
+	0x3c34, 0xa202, 0x5834, 0x3040, 0xaf02, 0x3041, 0xaf02, 0x3042,
+	0xaf02, 0x3049, 0x2849, 0x4425, 0xf338, 0xba5f, 0x2825, 0xf08a,
+	0x2840, 0xf298, 0xba46, 0x2841, 0xf268, 0xba46, 0xf24e, 0x2840,
+	0x4c49, 0xe162, 0x0400, 0xe163, 0x0404, 0xf1d8, 0xba40, 0x3c7d,
+	0x4425, 0xf1e8, 0xba44, 0xf1ca, 0xa102, 0x3d12, 0x3d02, 0xa221,
+	0x5b12, 0x3f13, 0x3f13, 0x2841, 0xf0e8, 0xba40, 0x3c7e, 0x4425,
+	0xf0f8, 0xba44, 0xf0da, 0xa102, 0x3d12, 0x3d02, 0xa221, 0x5b02,
+	0x3f13, 0x3f03, 0xba40, 0xf03a, 0xba4e, 0xf7de, 0xe42e, 0x284f,
+	0xa902, 0x3c4f, 0xe16b, 0xe42e, 0x2825, 0xe428, 0xa200, 0x3c36,
+	0x3c35, 0x3c37, 0x3c33, 0x3c3a, 0x3c38, 0x3c30, 0xa202, 0x3c3c,
+	0x3c31, 0x3c3e, 0x3c26, 0xa206, 0x3c3d, 0x2853, 0xa01e, 0xaf08,
+	0x3c56, 0x3c45, 0xe42e, 0xba46, 0xa102, 0xf0ca, 0xa102, 0xf0fa,
+	0xa102, 0xf13a, 0xa102, 0xf17a, 0xa106, 0xf1ba, 0xa102, 0xf1fa,
+	0xe42e, 0xa202, 0x3c25, 0xe41e, 0x0c1c, 0xe42e, 0xa202, 0x3c25,
+	0xe41e, 0x0c4d, 0xe16a, 0xe42e, 0xa202, 0x3c25, 0xe41e, 0x0c5e,
+	0xe16a, 0xe42e, 0xa202, 0x3c25, 0xe41e, 0x0ccd, 0xe16a, 0xe42e,
+	0xa202, 0x3c25, 0xe41e, 0x0cb8, 0xe16a, 0xe42e, 0xa202, 0x3c25,
+	0xe41e, 0x0c71, 0xe16a, 0xe42e, 0xba46, 0x3c2c, 0xba46, 0x3c2d,
+	0xba40, 0x3c26, 0x2a53, 0xf04a, 0xa01f, 0xaf09, 0xf04e, 0xa03f,
+	0xaf0b, 0xae03, 0x3e56, 0xa210, 0x3cf0, 0xba42, 0xa102, 0xf1c8,
+	0xa212, 0x3cf0, 0xba42, 0xf188, 0xa214, 0x3cf0, 0xba42, 0xf148,
+	0xa216, 0x3cf0, 0xba56, 0xa218, 0x3cf0, 0xba40, 0xf0da, 0xa21a,
+	0x3cf0, 0xba4e, 0xba40, 0x3c80, 0xba42, 0xa002, 0x3c29, 0xba48,
+	0xa002, 0x3c2a, 0xe42e, 0xe16b, 0xe42e, 0xba44, 0xba40, 0xf04a,
+	0xba4e, 0xba4e, 0xba4e, 0xba5a, 0x3c81, 0xa20a, 0x3cf0, 0xba40,
+	0xf04a, 0xba5a, 0x3c82, 0xe42e, 0xe16b, 0xe42e, 0xe41e, 0x0cdf,
+	0xf0f8, 0xa200, 0x3c50, 0xd022, 0x0001, 0xe184, 0x0c6c, 0xba41,
+	0xf03b, 0xc73f, 0xba4e, 0x4e50, 0x3e50, 0xf029, 0xe42e, 0xe16b,
+	0xe42e, 0xe162, 0x0400, 0xe163, 0x0404, 0xa21c, 0x3cf0, 0xd022,
+	0x0003, 0xe184, 0x0c80, 0xba46, 0xa102, 0x3d02, 0xa221, 0x5b12,
+	0x3f13, 0xba43, 0x3e30, 0xa21e, 0x3cf0, 0xba43, 0x3e3d, 0xf2fb,
+	0xa103, 0x3233, 0xaf03, 0x3e31, 0xe017, 0x3e32, 0x283b, 0xf03a,
+	0x2831, 0xf258, 0x2a31, 0x8455, 0x8256, 0xe018, 0xf029, 0xaf02,
+	0x3c54, 0x2856, 0xf029, 0xaf02, 0x3c45, 0xba40, 0x3c39, 0xba40,
+	0x3c3c, 0xba40, 0x3c38, 0xba40, 0x3c36, 0xba40, 0x3c37, 0xba40,
+	0x3c35, 0xba40, 0x3c3a, 0xba40, 0xba40, 0x3c3e, 0xa203, 0xba40,
+	0xe42a, 0xba40, 0xba44, 0x3cd7, 0xba5e, 0xe42e, 0xe16b, 0xe42e,
+	0xa202, 0x2a26, 0xf04b, 0x083a, 0x0839, 0xf03e, 0x0831, 0x083a,
+	0xae02, 0xa102, 0xcc44, 0xe184, 0x0cc7, 0xba5e, 0xba40, 0xf02a,
+	0xe42e, 0xa20a, 0x3cf0, 0xe16b, 0xe42e, 0xba40, 0xba4e, 0xba40,
+	0xba4c, 0xba40, 0xf09a, 0xba66, 0xba40, 0xf06a, 0xba6a, 0xba40,
+	0xf03a, 0xba6a, 0xe42e, 0xa20a, 0x3cf0, 0xe16b, 0xe42e, 0xba41,
+	0xf21b, 0xe0c3, 0x013c, 0xa200, 0x3c7c, 0xe161, 0x0420, 0x287c,
+	0xe0c2, 0x013e, 0xa002, 0x3c7c, 0xa20c, 0x3cf0, 0xba4e, 0x3d11,
+	0xe0c2, 0x013f, 0xd022, 0x003e, 0xe184, 0x0cff, 0x287c, 0xe0c2,
+	0x013e, 0xa002, 0x3c7c, 0xba4e, 0xf28a, 0x3d11, 0xe0c2, 0x013f,
+	0xe190, 0xba40, 0xf1aa, 0xe0c2, 0x013c, 0xae02, 0xe055, 0xe004,
+	0x0040, 0x3c7c, 0xe162, 0x0460, 0xa20e, 0x3cf0, 0xd022, 0x003f,
+	0xe184, 0x0d1a, 0x287c, 0xe0c2, 0x013e, 0xa002, 0x3c7c, 0xba4e,
+	0x3d12, 0xe0c2, 0x013f, 0xe190, 0x4e27, 0x3e27, 0xe0c3, 0x013d,
+	0xa200, 0xe0c2, 0x013c, 0xe42e, 0xa202, 0xe42e, 0x2ad8, 0x28e4,
+	0xa120, 0xb615, 0x3ed8, 0xe42b, 0xa200, 0x3ce2, 0xe162, 0x04c8,
+	0x28d6, 0xf09a, 0xe004, 0x4741, 0x3d12, 0xe004, 0x3934, 0x3d12,
+	0xa208, 0x3ce2, 0xe41e, 0x0d83, 0xf168, 0xba4e, 0x2ae2, 0xa803,
+	0xf049, 0xae10, 0x3ce1, 0xf03e, 0x4ce1, 0x3d12, 0x2ae2, 0xa003,
+	0x3ee2, 0xa80f, 0xe41b, 0x0db3, 0x28d8, 0xf0aa, 0xe41e, 0x0d83,
+	0xf028, 0xf69e, 0x28e2, 0xa802, 0xf03a, 0x28e1, 0x3d12, 0xa211,
+	0x28e2, 0xa80e, 0xf0ba, 0xe045, 0xaf03, 0xf06b, 0xa103, 0x3e50,
+	0xa201, 0x8650, 0x3f12, 0xe41e, 0x0db3, 0xa201, 0xe162, 0x04c8,
+	0x28e3, 0x3d12, 0x28e2, 0x3d12, 0x3f12, 0xa200, 0x3d12, 0xe0c1,
+	0x006b, 0x28e4, 0xa002, 0xae06, 0xe041, 0xaf06, 0x3ce4, 0xca28,
+	0xf7f8, 0xce21, 0xd111, 0x04c8, 0xd112, 0x0004, 0xd113, 0x0000,
+	0xca28, 0xf7f8, 0xe42e, 0xc001, 0x2832, 0xf028, 0xf07e, 0x2430,
+	0x4c31, 0xae06, 0xc873, 0xe046, 0xf046, 0xa200, 0xc000, 0xe42e,
+	0xa202, 0xc000, 0xe42e, 0xa200, 0x3ce7, 0xe0c0, 0x005c, 0xe0c1,
+	0x0065, 0xaf12, 0xa802, 0xaf15, 0xa803, 0xe016, 0xe056, 0xf04a,
+	0xa200, 0x3cd8, 0xe42e, 0x28e8, 0xf05a, 0xe0c0, 0x005d, 0xe42a,
+	0xf7be, 0xe0c0, 0x005d, 0xe00a, 0x0200, 0xe0c2, 0x005d, 0xa202,
+	0xce00, 0x3ce8, 0xf71e, 0xd112, 0x0004, 0xe0c0, 0x006b, 0xe000,
+	0x0088, 0x0ce7, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x04c8, 0xd113,
+	0x0000, 0xe1e1, 0xe162, 0x04c8, 0x2ce5, 0x2ee7, 0xa010, 0xa011,
+	0x3ce5, 0x3ee7, 0xe0c0, 0x006c, 0xe002, 0x0088, 0xe046, 0xe416,
+	0x0d93, 0xa200, 0x3ce8, 0xe42e, 0xba4e, 0xba40, 0xae02, 0xba41,
+	0xe056, 0xae02, 0xba41, 0xe056, 0xae02, 0xba41, 0xe056, 0x3cd1,
+	0xba46, 0x28d1, 0xa810, 0xf06a, 0xba42, 0xa106, 0xf1d8, 0xba5a,
+	0x3cd2, 0x28d1, 0xa808, 0xf06a, 0xba42, 0xa106, 0xf158, 0xba5a,
+	0x3cd3, 0x28d1, 0xa804, 0xf06a, 0xba42, 0xa106, 0xf0d8, 0xba5a,
+	0x3cd4, 0x28d1, 0xa802, 0xf06a, 0xba42, 0xa106, 0xf058, 0xba5a,
+	0x3cd5, 0xa203, 0xe42e, 0xa201, 0xe42e, 0xba7e, 0xba40, 0xf098,
+	0xba41, 0xba4a, 0xf04b, 0xba46, 0xba46, 0x3c5b, 0xa203, 0xe42e,
+	0xa201, 0xe42e, 0x28b9, 0xe428, 0xe41e, 0x0626, 0xa202, 0x3cb9,
+	0xe42e, 0xa200, 0x3cb9, 0xe42e, 0xd180, 0x0002, 0xe41e, 0x122f,
+	0xcb00, 0xcb03, 0xe409, 0x0e83, 0xf7c8, 0xcb0c, 0x3060, 0xaf02,
+	0x3061, 0xaf02, 0x306f, 0xaf02, 0x3070, 0xaf02, 0x306a, 0xaf02,
+	0x3065, 0xaf02, 0xf03a, 0xcb16, 0x3c64, 0xa200, 0x2a70, 0x4e60,
+	0xe017, 0x4641, 0xb632, 0x3c6e, 0xcf24, 0xcb22, 0xaf08, 0xa802,
+	0x4c6f, 0xae02, 0x4c70, 0x2a60, 0xe055, 0xb636, 0x3c71, 0x286a,
+	0x4c70, 0x4c6f, 0xf08a, 0xd190, 0x0001, 0xcb20, 0xcb03, 0xe409,
+	0x0e83, 0xf7c8, 0x746a, 0xa200, 0x1860, 0x2a61, 0xf03b, 0xb808,
+	0xf2bd, 0xcf08, 0xe0c2, 0x012a, 0xa200, 0x2a60, 0xe017, 0x4e6e,
+	0x4e6a, 0xb652, 0xcf20, 0xd180, 0x0001, 0xcb00, 0xcb03, 0xf1c9,
+	0xf7d8, 0xcb20, 0xcb03, 0xf189, 0xf7d8, 0x7449, 0xe41e, 0x0ec6,
+	0xf13d, 0xa200, 0x2a60, 0xb636, 0xcf04, 0xa200, 0x2a6a, 0xe017,
+	0x4660, 0xb6d2, 0xcf04, 0xa200, 0x2a6e, 0xb652, 0xcf04, 0xa200,
+	0xe41e, 0x13bd, 0xe42e, 0xe16b, 0xa200, 0xcf02, 0xe42e, 0x3c50,
+	0xd192, 0x0002, 0xd182, 0x0001, 0xcb0c, 0xaf04, 0xa806, 0xf038,
+	0xa210, 0xcf0c, 0xa200, 0x3c60, 0x2a41, 0xb652, 0xcf04, 0xd190,
+	0x0002, 0xcb20, 0xcb03, 0xf0b9, 0xf7d8, 0x286f, 0xae02, 0x4c70,
+	0xb634, 0x3c71, 0x2850, 0xe41e, 0x13bd, 0xe42e, 0xe16b, 0xa200,
+	0xcf02, 0xe42e, 0x20a6, 0x4ca7, 0xe414, 0x13bd, 0x20a6, 0x4ca7,
+	0xe412, 0x0e87, 0x2ca0, 0xa002, 0x3ca0, 0xe42e, 0xc001, 0x3c13,
+	0xc000, 0xe42e, 0xc001, 0x2813, 0xc000, 0xe42e, 0xc001, 0x3c14,
+	0xc000, 0xe42e, 0xc001, 0x2814, 0xc000, 0xe42e, 0xc001, 0x2430,
+	0x4c31, 0xc000, 0xae06, 0xc873, 0xe046, 0xe422, 0xe16b, 0xe42e,
+	0xc001, 0x280c, 0xf16a, 0xe41e, 0x1121, 0xc001, 0xe0c0, 0x0049,
+	0x340e, 0x3c0f, 0x240e, 0x4c0f, 0xe0c1, 0x0048, 0x360e, 0x3e0f,
+	0x260e, 0x4e0f, 0xe045, 0xa200, 0xb626, 0xe003, 0x0200, 0xb606,
+	0xc000, 0xe42e, 0xe41e, 0x0ed0, 0xe42a, 0xe0c0, 0x0045, 0xaf04,
+	0xa802, 0xe42e, 0xc001, 0x3c33, 0xc000, 0xe42e, 0xc001, 0x2833,
+	0xc000, 0xe42e, 0xc001, 0x3c11, 0xc000, 0xe42e, 0xc001, 0x2811,
+	0xc000, 0xe42e, 0xd148, 0x0040, 0xd144, 0x0000, 0xd145, 0x0000,
+	0xd168, 0x0000, 0xd16b, 0x0000, 0xd14b, 0x0200, 0xe004, 0x0019,
+	0xae18, 0xcec0, 0xd14c, 0x000c, 0xca9a, 0xf7f8, 0xe42e, 0xc001,
+	0x2400, 0x4c01, 0x0406, 0x0c07, 0x3408, 0x3c09, 0xd071, 0x202a,
+	0xe181, 0xc001, 0xe0c0, 0x0048, 0x3415, 0x3c16, 0x280c, 0xf13a,
+	0xe0c0, 0x0048, 0x340e, 0x3c0f, 0x240e, 0x4c0f, 0xe0c1, 0x0049,
+	0x3604, 0x3e05, 0x1404, 0x1c05, 0xe0c1, 0x0045, 0xaf05, 0xa803,
+	0xb611, 0x320c, 0xe0c0, 0x0048, 0x3402, 0xe008, 0xfe00, 0x3c03,
+	0xe0c0, 0x0048, 0xe008, 0x01ff, 0x3c0b, 0xa200, 0xcc78, 0xd022,
+	0x00ff, 0xe184, 0x0f4c, 0xcc7a, 0xe190, 0xe41e, 0x1010, 0xe41e,
+	0x102f, 0xe41e, 0x0f02, 0xc001, 0xa200, 0x3c1a, 0x280b, 0xa102,
+	0xe412, 0x0f69, 0xc001, 0xa202, 0x3c1a, 0xa200, 0xceaa, 0xc000,
+	0xe42e, 0xcaa0, 0xe190, 0xca9a, 0xf7f8, 0xca9c, 0xe418, 0x102f,
+	0xe42e, 0xcc44, 0xe184, 0x0f72, 0xca9c, 0xe418, 0x102f, 0xcaa0,
+	0xca9b, 0xf7f9, 0xe190, 0xe42e, 0xe004, 0x0100, 0xceb0, 0xe004,
+	0x00ff, 0xe014, 0xceb8, 0xd15d, 0x0000, 0xd15e, 0x0000, 0xd15f,
+	0x0000, 0xe004, 0x0019, 0xae18, 0xe00a, 0x0620, 0xcec0, 0xd157,
+	0x0000, 0xd14a, 0x0000, 0xd14c, 0x0003, 0xca9c, 0xe418, 0x102f,
+	0xca9a, 0xf7c8, 0xcaae, 0xa802, 0xf73a, 0xca9c, 0xe418, 0x102f,
+	0xa200, 0xe42e, 0xe41e, 0x0f74, 0xe41e, 0x0ed0, 0xf188, 0xe41e,
+	0x1160, 0xcaa2, 0xe008, 0x00ff, 0xf0a8, 0xe41e, 0x1198, 0xaf20,
+	0xa102, 0xf058, 0xa204, 0xe41e, 0x0f69, 0xf6de, 0xcaa2, 0xe008,
+	0x00ff, 0xe41e, 0x0eb6, 0xe41e, 0x0ed0, 0xf0fa, 0xe004, 0x01b7,
+	0xe008, 0x00ff, 0xe41e, 0x0eb6, 0xe004, 0x01b7, 0xe008, 0x00ff,
+	0xe41e, 0x0ebe, 0xa200, 0xe42e, 0xa206, 0xe41e, 0x0f69, 0xe41e,
+	0x0eba, 0xe41e, 0x0ebe, 0xca9c, 0xe418, 0x102f, 0xe41e, 0x0fd1,
+	0xe42e, 0xc001, 0xa200, 0x3c30, 0x3c31, 0x3c33, 0xe41e, 0x0fdf,
+	0xc001, 0xe41e, 0x1010, 0xc001, 0xe128, 0xc000, 0xe42e, 0xc001,
+	0x2833, 0x4411, 0xc000, 0xae0e, 0xce92, 0xd14a, 0x0000, 0xd158,
+	0x0100, 0xe004, 0x00ff, 0xe014, 0xceb8, 0xd15d, 0x0000, 0xd15e,
+	0x0000, 0xd15f, 0x0000, 0xd161, 0x0003, 0xe004, 0x0019, 0xae18,
+	0xe00a, 0x0620, 0xcec0, 0xd14c, 0x0003, 0xca9c, 0xe418, 0x102f,
+	0xca9a, 0xf7c8, 0xca9c, 0xf7a8, 0xca9e, 0xc001, 0x3c32, 0xcc92,
+	0xca94, 0x0030, 0x0c31, 0x3430, 0x3c31, 0xcc90, 0xc000, 0xe42e,
+	0xe004, 0x1495, 0xae20, 0xcc9e, 0xd030, 0x0000, 0xd034, 0x0000,
+	0xd033, 0x0000, 0xd035, 0x0000, 0xd036, 0x007f, 0xd037, 0x0000,
+	0xd038, 0x0000, 0xd039, 0x0000, 0xd04b, 0x0001, 0xd04c, 0x0000,
+	0xd046, 0x0000, 0xd047, 0x0000, 0xd149, 0x0000, 0xe42e, 0xc001,
+	0x280c, 0xf20a, 0xe41e, 0x024f, 0xc001, 0xe004, 0x0440, 0xce50,
+	0x280d, 0xa806, 0xa108, 0xe012, 0xa806, 0xae06, 0x3c40, 0xe004,
+	0x01b7, 0x5840, 0xce52, 0xe41e, 0x0257, 0xc001, 0xd14e, 0x0000,
+	0xd144, 0x0000, 0x2402, 0x4c03, 0xe000, 0x0200, 0x3402, 0x3c03,
+	0xf3ae, 0xd027, 0x0000, 0x280c, 0xe41a, 0x1098, 0xc001, 0xd027,
+	0x0001, 0x280d, 0xf25a, 0xca48, 0xa802, 0xf7e8, 0x2402, 0x4c03,
+	0xce40, 0xd121, 0x0000, 0xd122, 0x0040, 0xe0c0, 0x0043, 0xa806,
+	0xae02, 0xa032, 0xce46, 0xe190, 0xe190, 0xe190, 0xe190, 0xca48,
+	0xa802, 0xf7e8, 0xe004, 0x0200, 0x0402, 0x0c03, 0x3402, 0x3c03,
+	0x1408, 0x1c09, 0xf054, 0x2400, 0x4c01, 0x3402, 0x3c03, 0x280c,
+	0xe418, 0x10dc, 0xc001, 0xe41e, 0x1121, 0xc001, 0xd14e, 0x0000,
+	0xd144, 0x0000, 0xc000, 0xe42e, 0xe0c1, 0x0059, 0xa103, 0xa200,
+	0xb636, 0xe000, 0x001c, 0xe0c1, 0x0045, 0xe052, 0xe01a, 0xe42e,
+	0xc001, 0xa200, 0x3c0a, 0xe004, 0x0200, 0x3c0d, 0xe0c0, 0x0043,
+	0xa808, 0xf338, 0xe41e, 0x108c, 0xc001, 0x3c0c, 0x2402, 0x4c03,
+	0xe0c1, 0x0049, 0x3604, 0x3e05, 0x2604, 0x4e05, 0xe045, 0xf033,
+	0x0606, 0x0e07, 0xe003, 0x0200, 0x280c, 0xb602, 0x3c0c, 0xf1d3,
+	0xe001, 0x0200, 0x3e0d, 0x280c, 0xf188, 0x280a, 0xe408, 0x10a2,
+	0xe41e, 0x01db, 0xc001, 0xe0c0, 0x005c, 0xe008, 0x4000, 0xe40a,
+	0x10a2, 0xe0c0, 0x005d, 0xe00a, 0x4000, 0xe0c2, 0x005d, 0xa202,
+	0xce00, 0x3c0a, 0xe40e, 0x10a2, 0x280d, 0x2a0c, 0xf039, 0xe004,
+	0x0200, 0x3c0d, 0xc000, 0xe42e, 0xc001, 0xe41e, 0x024f, 0xc001,
+	0x280d, 0xe002, 0x0200, 0xe40a, 0x111e, 0x280d, 0xa806, 0xf1fa,
+	0xa108, 0xe012, 0xae06, 0x3c40, 0x280d, 0xaf04, 0xae20, 0xe000,
+	0x01c0, 0xce50, 0xe190, 0xca52, 0x5c40, 0x5840, 0x2a0d, 0xa807,
+	0xae07, 0x3e40, 0xe005, 0x01b7, 0x5e40, 0xe056, 0x2a0d, 0xaf05,
+	0xae21, 0xe001, 0x0140, 0xce51, 0xe190, 0xce52, 0xe004, 0x01fc,
+	0x180d, 0xf022, 0xf14e, 0xc001, 0x280d, 0xa006, 0xaf04, 0xae20,
+	0xe000, 0x0440, 0xce50, 0x280d, 0xa806, 0xa108, 0xe012, 0xa806,
+	0xae06, 0x3c40, 0xe004, 0x01b7, 0x5840, 0xce52, 0xc000, 0xe40e,
+	0x0257, 0xc001, 0xcaaa, 0x2a1a, 0xb616, 0xe0c1, 0x0048, 0x360e,
+	0x3e0f, 0x260e, 0x4e0f, 0xe042, 0xe049, 0x1608, 0x1e09, 0xf035,
+	0x1406, 0x1c07, 0xe0c2, 0x0048, 0xa200, 0xceaa, 0xc000, 0xe42e,
+	0xe41e, 0x1121, 0xe0c0, 0x0045, 0xaf04, 0xa806, 0xa104, 0xe428,
+	0xa2fc, 0x2aa1, 0xa003, 0xb616, 0xe418, 0x1147, 0xe42e, 0xc001,
+	0x3c40, 0xe0c0, 0x0048, 0x340e, 0x3c0f, 0x240e, 0x4c0f, 0x0840,
+	0xe049, 0x1600, 0x1e01, 0xf033, 0x0406, 0x0c07, 0xe049, 0x1608,
+	0x1e09, 0xf035, 0x1406, 0x1c07, 0xe0c2, 0x0048, 0xc000, 0xe42e,
+	0xe41e, 0x1121, 0xc001, 0xe0c0, 0x0048, 0x3417, 0x3c18, 0xc000,
+	0xe42e, 0xa200, 0xceaa, 0xc001, 0x2417, 0x4c18, 0xc000, 0xe0c2,
+	0x0048, 0xe42e, 0xe41e, 0x0f74, 0xe41e, 0x0ed0, 0xf118, 0xcaa2,
+	0xe008, 0x00ff, 0xf0a8, 0xe41e, 0x1198, 0xaf20, 0xa102, 0xf058,
+	0xa204, 0xe41e, 0x0f69, 0xf6fe, 0xe41e, 0x0ed0, 0xf0aa, 0xe004,
+	0x01b7, 0xe008, 0x00ff, 0xe41e, 0x0eb6, 0xe004, 0x01b7, 0xf02e,
+	0xcaa2, 0xe008, 0x00ff, 0xe41e, 0x0ebe, 0xe41e, 0x0ec2, 0xe42e,
+	0xe162, 0x0190, 0xca80, 0x3512, 0x3d12, 0xca82, 0x3512, 0x3d12,
+	0xca84, 0x3512, 0x3d12, 0xca86, 0x3512, 0x3d12, 0xca8b, 0xa208,
+	0xca8b, 0xa003, 0xaf03, 0xe046, 0xe000, 0x0192, 0xe094, 0xca8a,
+	0xa802, 0xf048, 0x2512, 0x4d12, 0xe42e, 0x2d12, 0xe008, 0x00ff,
+	0xae20, 0x4d12, 0xae10, 0x2712, 0x4f12, 0xaf31, 0xe009, 0x00ff,
+	0xe056, 0xe42e, 0xc001, 0x2832, 0xf068, 0xba2c, 0xf158, 0xa202,
+	0x3c32, 0xf0fe, 0x2430, 0x4c31, 0xae06, 0xc873, 0xe046, 0xf096,
+	0xa12e, 0xb600, 0xa02e, 0x3c32, 0x7832, 0xa203, 0x3e32, 0xf048,
+	0xa202, 0xc000, 0xe42e, 0xa200, 0xc000, 0xe42e, 0xc001, 0xa200,
+	0x3c10, 0x2832, 0xf098, 0xa202, 0x3c33, 0x3c10, 0x3c11, 0xd036,
+	0x00ff, 0xd037, 0x0080, 0xc000, 0xe42e, 0xc001, 0xcb20, 0xa80c,
+	0xf7e8, 0x2832, 0xf1b8, 0x2833, 0xf078, 0xe41e, 0x0fdf, 0xc001,
+	0xd04c, 0x0000, 0xf13e, 0xc896, 0xf05a, 0xe41e, 0x1211, 0xd04c,
+	0x0000, 0xe41e, 0x0efe, 0xe005, 0x0080, 0xb615, 0xcc6f, 0xd04b,
+	0x0001, 0xa202, 0xe41e, 0x1227, 0xe470, 0xd04c, 0x0000, 0xc000,
+	0xe470, 0xa200, 0xe41e, 0x1227, 0xe41e, 0x0fdf, 0xe41e, 0x1223,
+	0xcc96, 0xe41e, 0x0efe, 0xe016, 0xe41e, 0x0efa, 0xe42e, 0xc001,
+	0x3c32, 0xc000, 0xe42e, 0xc001, 0x2832, 0xc000, 0xe42e, 0xc001,
+	0x3c10, 0xc000, 0xe42e, 0xc001, 0x2810, 0xc000, 0xe42e, 0xe180,
+	0xe41e, 0x122b, 0xe418, 0x1211, 0xe181, 0xe42e, 0x2825, 0xe016,
+	0xae08, 0xa904, 0xe0c2, 0x0100, 0xa200, 0xe0c2, 0x013d, 0xa200,
+	0xe0c2, 0x0128, 0x2ac1, 0x4ec2, 0xb692, 0xae08, 0xa90c, 0xe0c2,
+	0x017c, 0xa208, 0xe0c2, 0x017d, 0xa200, 0xe41e, 0x1415, 0xe0c2,
+	0x0102, 0xe42e, 0xa200, 0xe0c2, 0x0320, 0xcc8e, 0x283b, 0xe408,
+	0x12fb, 0xe41e, 0x1236, 0xe0c0, 0x0050, 0xe049, 0xe008, 0x007f,
+	0x3c08, 0xaf11, 0xe009, 0x007f, 0x3e10, 0x4608, 0x3e08, 0xa200,
+	0x2a08, 0xa809, 0xf03b, 0xe00a, 0x0020, 0x2a08, 0xa811, 0xf03b,
+	0xe00a, 0x0040, 0xe0c2, 0x040c, 0x2855, 0xae20, 0x4c56, 0xae08,
+	0xe0c2, 0x0101, 0xe0c2, 0x0205, 0xcf60, 0xa200, 0xe0c2, 0x0103,
+	0xe0c2, 0x0113, 0xe0c2, 0x0120, 0xe0c2, 0x0121, 0xe0c2, 0x0122,
+	0xe0c2, 0x0123, 0xe0c2, 0x0303, 0xa27e, 0xe0c2, 0x012a, 0x2827,
+	0xe0c2, 0x013d, 0xe418, 0x13e5, 0x2814, 0xf104, 0xa204, 0xe0c2,
+	0x0208, 0xe0c2, 0x0210, 0xa200, 0xe41e, 0x1415, 0xe0c2, 0x0213,
+	0xe0c2, 0x0215, 0x2814, 0xe0c2, 0x020b, 0xa202, 0xe0c2, 0x0302,
+	0xa20e, 0xe0c2, 0x0312, 0xe0c0, 0x0414, 0xe418, 0x018c, 0xe0c0,
+	0x0414, 0xe41a, 0x1350, 0x2812, 0xf052, 0x2813, 0xf032, 0x28a1,
+	0xb608, 0xe0c2, 0x0380, 0x2813, 0xf042, 0x2812, 0x28a1, 0xb608,
+	0xe0c2, 0x0383, 0xa200, 0xe0c2, 0x0302, 0x2809, 0xf35a, 0xe0c1,
+	0x0046, 0xe004, 0x0000, 0xae10, 0xe042, 0x2a10, 0xa809, 0xf05b,
+	0xe167, 0x02d4, 0x2117, 0x4d17, 0xe0c2, 0x0211, 0xe0c1, 0x0046,
+	0xe004, 0x0080, 0xae10, 0xe042, 0x2a10, 0xa811, 0xf05b, 0xe167,
+	0x02d6, 0x2117, 0x4d17, 0xe0c2, 0x0212, 0xa200, 0xe0c2, 0x0215,
+	0xe41e, 0x1415, 0xe00a, 0x0100, 0xe0c2, 0x0213, 0x2811, 0xe0c2,
+	0x0214, 0xa202, 0xe0c2, 0x0210, 0xa200, 0xcf68, 0x2842, 0xf04a,
+	0xa200, 0xe0c2, 0x0208, 0x2834, 0xa104, 0xb5a0, 0xb434, 0xa004,
+	0xa960, 0xae04, 0x4c32, 0xae02, 0x4c33, 0xe0c2, 0x0204, 0x2849,
+	0xae02, 0x4c40, 0xae02, 0x4c41, 0xae02, 0x4c3b, 0xae02, 0x4c39,
+	0xae02, 0x4c7e, 0xae02, 0x4c7d, 0xae02, 0x4c38, 0xae04, 0x4c30,
+	0xae02, 0x4c3c, 0xae04, 0x4c3d, 0xae04, 0x2a34, 0xa003, 0xa807,
+	0xe056, 0xae02, 0x4c37, 0xae02, 0x2a25, 0xe017, 0xe056, 0xcf06,
+	0xe162, 0x0400, 0xd022, 0x0003, 0xe184, 0x132f, 0xae08, 0x4d12,
+	0xcf28, 0xa202, 0xae02, 0x4c35, 0xae0a, 0x4c32, 0xae02, 0x4c33,
+	0xe0c2, 0x0104, 0xe41e, 0x0274, 0xa202, 0xe0c2, 0x0106, 0xa200,
+	0xe0c2, 0x0103, 0xe0c2, 0x0113, 0xe0c2, 0x0120, 0xe0c2, 0x0121,
+	0xe0c2, 0x0122, 0xe0c2, 0x0123, 0xe0c2, 0x0303, 0xa202, 0xe42e,
+	0xe167, 0x01a0, 0x2317, 0x4f17, 0xe0c3, 0x0152, 0x2b17, 0xe009,
+	0x00ff, 0xae21, 0x4f07, 0xe0c3, 0x0153, 0xe0c1, 0x0101, 0xe0c3,
+	0x015d, 0x2834, 0xa106, 0xe005, 0x001b, 0xf038, 0xe005, 0x001f,
+	0x3e50, 0x2812, 0xb608, 0x2a13, 0xb60b, 0xae11, 0xe055, 0xae21,
+	0xe167, 0x01a2, 0x2907, 0xaf10, 0x4450, 0xe055, 0xe0c3, 0x015c,
+	0xa202, 0xe0c2, 0x0150, 0xe0c0, 0x0150, 0xf7ea, 0xa200, 0xe0c2,
+	0x0150, 0xe0c0, 0x0151, 0xf7e8, 0xe42e, 0x2a2b, 0x2842, 0xb435,
+	0x3e2b, 0xa107, 0xf039, 0xa204, 0x3c2b, 0xe0c0, 0x0065, 0xaf0a,
+	0xa802, 0xf13a, 0xe162, 0x04c8, 0x2ce4, 0x3d12, 0x2ce5, 0x3d12,
+	0xe0c0, 0x006b, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x04c8, 0xd112,
+	0x0004, 0xd113, 0x0000, 0xe1e1, 0xe0c0, 0x0065, 0xe008, 0x0100,
+	0xf0ea, 0xca28, 0xf7f8, 0xe0c0, 0x006a, 0xce20, 0xd112, 0x0004,
+	0xd111, 0x04c0, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xa200, 0x3ce5,
+	0x3ce4, 0x3cd8, 0x3ce7, 0x3ce8, 0xe42e, 0x2809, 0xe40a, 0x13cc,
+	0x2864, 0xae06, 0xcb23, 0xa80f, 0xe055, 0xcf23, 0xd1b6, 0x0001,
+	0xd1b5, 0x0001, 0xcb6a, 0xf7f8, 0x2865, 0xae08, 0x4c60, 0xe0c2,
+	0x0114, 0x2836, 0xae0a, 0x4c64, 0xe0c2, 0x0115, 0xe0c0, 0x012a,
+	0xe0c2, 0x0116, 0xe0c0, 0x0111, 0xf7e8, 0xa202, 0xe0c2, 0x0110,
+	0x28c1, 0x4cc2, 0xe418, 0x14fb, 0xe42e, 0xa802, 0xf14a, 0xe0c2,
+	0x013c, 0xa200, 0x3c7c, 0xe161, 0x0420, 0xd022, 0x003f, 0xe184,
+	0x13f8, 0x287c, 0xe0c2, 0x013e, 0xa002, 0x3c7c, 0x2911, 0xe0c2,
+	0x013f, 0xe190, 0x2827, 0xaf02, 0xf15a, 0xe0c2, 0x013c, 0xe004,
+	0x0040, 0x3c7c, 0xe162, 0x0460, 0xd022, 0x003f, 0xe184, 0x140f,
+	0x287c, 0xe0c2, 0x013e, 0xa002, 0x3c7c, 0x2912, 0xe0c2, 0x013f,
+	0xe190, 0xa200, 0xe0c2, 0x013c, 0xe42e, 0xe0c1, 0x0044, 0xa80f,
+	0xe056, 0xe42e, 0xa200, 0xe41e, 0x1415, 0xe42e, 0xe0c1, 0x0044,
+	0xaf0d, 0xae03, 0xe056, 0xe008, 0x003f, 0xe42e, 0xe0c1, 0x0044,
+	0xaf17, 0xa803, 0xe42e, 0xe0c1, 0x0044, 0xaf17, 0xa803, 0xa105,
+	0xf039, 0xa213, 0xe42e, 0xa201, 0xe42e, 0xa203, 0xe0c3, 0x040d,
+	0xe0c1, 0x0420, 0xa803, 0xf7db, 0xe160, 0x0003, 0xe166, 0x0200,
+	0xe167, 0x0500, 0x28a8, 0xf166, 0xa102, 0xcc44, 0xe184, 0x1458,
+	0xa200, 0xe41e, 0x1415, 0xaf04, 0xe41e, 0x141e, 0xae20, 0x2ea9,
+	0xe056, 0x9f17, 0x2055, 0x4c56, 0xae08, 0x9f17, 0xe41e, 0x145e,
+	0xe190, 0xe190, 0xa201, 0xe0c3, 0x040d, 0xe42e, 0x2116, 0x4d16,
+	0x9f17, 0x2116, 0x4d16, 0x9f17, 0x2116, 0x4d16, 0x9f17, 0xe42e,
+	0xe0c0, 0x0044, 0xaf20, 0xa802, 0xe428, 0xe0c0, 0x0060, 0xa860,
+	0xe42a, 0xe0c0, 0x0061, 0xa83e, 0xa203, 0xe0c3, 0x040d, 0xcca4,
+	0xc785, 0xe018, 0xe000, 0x0500, 0xe09e, 0xe0c1, 0x0420, 0xa803,
+	0xf7db, 0xa200, 0xe41e, 0x141a, 0xa80e, 0xaf04, 0xe41e, 0x141e,
+	0xe41e, 0x1426, 0xe40b, 0x1491, 0xa81e, 0xe41e, 0x142b, 0xae09,
+	0xe056, 0xae20, 0xe0c1, 0x006e, 0xe009, 0x1fff, 0xe056, 0x9f17,
+	0xe0c0, 0x0060, 0xa822, 0xa122, 0xf04a, 0x2055, 0x4c56, 0xf03e,
+	0x2056, 0x4c55, 0xae08, 0x9f17, 0xe0c0, 0x0062, 0x9f17, 0xe0c0,
+	0x0063, 0x9f17, 0xe0c0, 0x0064, 0x9f17, 0xa201, 0xe0c3, 0x040d,
+	0xe42e, 0x3cec, 0xe0c0, 0x0041, 0xe005, 0x0020, 0xae11, 0xe042,
+	0xce20, 0xd111, 0x0200, 0xd112, 0x00c0, 0x88ec, 0x0113, 0xca29,
+	0xf7f9, 0xe190, 0xe42e, 0xa2fe, 0x3cc3, 0xa200, 0x3cc1, 0x3cc2,
+	0xe42e, 0x28b4, 0x3cc3, 0x28c3, 0xf042, 0xa200, 0x3cc1, 0x3cc2,
+	0xa200, 0x3cc8, 0x3cc9, 0x2855, 0x3cc6, 0x2856, 0x3cc7, 0x28c1,
+	0x4cc2, 0xe42a, 0x28c3, 0xe424, 0x28c3, 0xe0c2, 0x0143, 0x28c4,
+	0xe0c2, 0x0144, 0xa200, 0xe0c2, 0x017f, 0xe0c2, 0x0149, 0xe41e,
+	0x1415, 0xe0c2, 0x017f, 0x28c6, 0xa102, 0xae20, 0x4cc7, 0xa102,
+	0xe0c2, 0x0142, 0xa200, 0xae20, 0x2ac2, 0xae09, 0x4ec0, 0xe042,
+	0xe0c2, 0x014e, 0xe42e, 0x28c3, 0xe41e, 0x153c, 0x3cc5, 0x2ac9,
+	0x1ac7, 0xe423, 0x28c8, 0xae0e, 0x4cc9, 0xa203, 0xb615, 0x3eca,
+	0x2ac5, 0xae03, 0x4eca, 0xae03, 0xa903, 0xae1d, 0xe056, 0xe0c1,
+	0x014b, 0xf7e9, 0xe0c2, 0x014d, 0xa202, 0xe0c2, 0x014a, 0x2ac8,
+	0xa003, 0x3ec8, 0x1ac6, 0xf065, 0x2ac9, 0xa003, 0x3ec9, 0xa201,
+	0x3ec8, 0xe42e, 0x28c1, 0x4cc2, 0xf15a, 0x28c9, 0x18c7, 0xf042,
+	0xe41e, 0x14fb, 0xf7be, 0xe0c0, 0x014b, 0xf7e8, 0xa204, 0xae1c,
+	0xe0c2, 0x014d, 0xa202, 0xe0c2, 0x014a, 0xe190, 0xe0c0, 0x014b,
+	0xf7e8, 0x28a2, 0x3cc3, 0xe42e, 0xe424, 0xe000, 0x0330, 0xe09c,
+	0x2906, 0xe42e, 0xe424, 0xe000, 0x0330, 0xe09c, 0x3f06, 0xe42e,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0080, 0x0060, 0x0008, 0x0006,
+	0x00b0, 0x0090, 0x000b, 0x0009, 0x0160, 0x0120, 0x0016, 0x0012,
+	0x02c0, 0x0240, 0x0058, 0x0012, 0x0580, 0x0480, 0x0160, 0x0012,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0063, 0x000d, 0x000f, 0x0011, 0x0013, 0x0015, 0x0017, 0x0000,
+	0xffff, 0xfffe, 0x0001, 0x0002, 0x0000, 0x0002, 0xffff, 0xffff,
+	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xfffe,
+	0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe,
+	0xfffe, 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0xfffd,
+	0xfffd, 0xfffd, 0xfffd, 0xfffd, 0x0000, 0x0001, 0x0001, 0x0001,
+	0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0002,
+	0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002,
+	0x0002, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0002, 0x0001, 0xfffb, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0xe40e, 0x0020, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x0330, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x034a, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x003a, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058,
+	0xa200, 0xe0c2, 0x005a, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xa2fe,
+	0x3cee, 0x3cef, 0x3cec, 0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d,
+	0xce00, 0xf33e, 0xe41e, 0x0164, 0xe09e, 0xa202, 0xae3e, 0x9f07,
+	0xe0c0, 0x005c, 0xe0c1, 0x0059, 0x3eed, 0xa203, 0x5aed, 0xe052,
+	0xf08a, 0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00,
+	0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2, 0x0008, 0xf00e,
+	0x28ee, 0xe412, 0x013d, 0xe190, 0xe0c0, 0x005c, 0xe0c1, 0x0059,
+	0x3eed, 0xa203, 0x5aed, 0xe052, 0xf08a, 0xe0c1, 0x005d, 0xe055,
+	0xe0c3, 0x005d, 0xa202, 0xce00, 0xe0c0, 0x004a, 0xf08a, 0xe41e,
+	0x019c, 0xe408, 0x005c, 0xe40e, 0x0058, 0xe190, 0xe0c0, 0x043d,
+	0xa1ee, 0xf7d8, 0xe004, 0x0060, 0xe0c2, 0x0009, 0xa200, 0xe0c2,
+	0x0009, 0xe0c0, 0x000d, 0xf7e8, 0xe41e, 0x00b2, 0xe41e, 0x00e2,
+	0xe41e, 0x012c, 0xd071, 0x242a, 0xe181, 0xe41e, 0x0164, 0xe09e,
+	0xa202, 0x9f07, 0xe0c0, 0x0049, 0xe0c1, 0x005b, 0xa111, 0xf033,
+	0xe0c0, 0x0048, 0xe0c2, 0x0047, 0xe0c0, 0x0059, 0xae02, 0xe000,
+	0x0330, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a, 0xe008, 0xffff,
+	0x3cee, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11, 0xe056, 0x3cef,
+	0xe40e, 0x0058, 0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2,
+	0x0008, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xe0c0, 0x0059, 0xf7ea,
+	0xa11e, 0xf198, 0xa202, 0xe0c2, 0x0058, 0xe004, 0xca20, 0xae20,
+	0xe005, 0x210a, 0xe056, 0xe0c2, 0x0070, 0xe004, 0x0000, 0xae20,
+	0xe00a, 0x9cea, 0xe0c2, 0x0071, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+	0x0058, 0xf64e, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058, 0xd027,
+	0x0001, 0xe42e, 0xa200, 0xe0c1, 0x005b, 0xf21b, 0xa23c, 0xa103,
+	0xf37b, 0xa24c, 0xa103, 0xf34b, 0xa258, 0xa103, 0xf1db, 0xe004,
+	0x003a, 0xa103, 0xf2db, 0xe004, 0x003f, 0xa103, 0xf29b, 0xe004,
+	0x0045, 0xa103, 0xf25b, 0xa103, 0xf14b, 0xe004, 0x0063, 0xa103,
+	0xf1ab, 0xe004, 0x006a, 0xa107, 0xf1bb, 0xa200, 0xe0c1, 0x005e,
+	0xf17b, 0xa028, 0xf15e, 0xe0c1, 0x005e, 0xf12b, 0xa010, 0xf10e,
+	0xe004, 0x0049, 0xe0c1, 0x005e, 0xf0bb, 0xa010, 0xa103, 0xf08b,
+	0xa010, 0xf06e, 0xe0c1, 0x005e, 0xf03b, 0xe004, 0x0074, 0xae16,
+	0xe0c1, 0x0040, 0xe041, 0xce21, 0xd111, 0x0000, 0xd112, 0x2800,
+	0xd113, 0x000b, 0xe1e1, 0xe42e, 0xe41e, 0x023a, 0xe0c0, 0x0059,
+	0xa102, 0xe42a, 0xe0c0, 0x005b, 0xa810, 0xf058, 0xa206, 0xe41e,
+	0x0153, 0xe42e, 0xe004, 0x0350, 0xe67c, 0xe0c0, 0x005b, 0xa810,
+	0xf058, 0xa204, 0xe41e, 0x0153, 0xe42e, 0xe004, 0x0352, 0xe67c,
+	0xa200, 0xc401, 0xe188, 0x00eb, 0x3d11, 0xe161, 0x00f2, 0xe188,
+	0x0b0d, 0x3d11, 0xe42e, 0x3cec, 0xe0c0, 0x0041, 0xe005, 0x0000,
+	0xae11, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0c00, 0x88ec,
+	0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0059, 0xa106, 0xf048,
+	0xe004, 0x0076, 0xe42e, 0xe0c0, 0x0059, 0xa10c, 0xf038, 0xe004,
+	0x0071, 0xe004, 0x0070, 0xe42e, 0xe0c0, 0x006b, 0xe167, 0x01a0,
+	0x3d07, 0xe0c0, 0x0414, 0xe428, 0xe0c1, 0x0044, 0xa809, 0xae33,
+	0xe0c0, 0x006a, 0xe167, 0x01a0, 0x3517, 0x3d17, 0xe0c0, 0x006b,
+	0xe056, 0x3517, 0x3d07, 0xe42e, 0xe167, 0x01a0, 0x2907, 0xe0c2,
+	0x0151, 0xa204, 0xe0c2, 0x0150, 0xe0c0, 0x0150, 0xa804, 0xf7da,
+	0xa208, 0xe0c2, 0x0150, 0xe42e, 0xe0c0, 0x004a, 0xe42a, 0xe0c0,
+	0x005b, 0xa110, 0xf142, 0xe0c0, 0x0059, 0xa102, 0xe41a, 0x01be,
+	0xe0c0, 0x0059, 0xa106, 0xe41a, 0x01cb, 0xe0c0, 0x0047, 0xe0c2,
+	0x0048, 0xa200, 0xe0c2, 0x004a, 0xa202, 0xe42e, 0xe0c0, 0x0047,
+	0xe0c2, 0x0049, 0xa200, 0xe0c2, 0x004a, 0xe42e, 0xe0c0, 0x004a,
+	0xa802, 0xa23e, 0x3cf0, 0xa202, 0x58f0, 0xe0c2, 0x0078, 0xa220,
+	0xe0c2, 0x0070, 0xe42e, 0xe0c0, 0x004a, 0xa802, 0xa220, 0xe0c2,
+	0x0076, 0xa200, 0xe0c2, 0x0072, 0xa2fc, 0xe0c2, 0x0077, 0xa2fa,
+	0xe0c2, 0x0071, 0xe42e, 0xe0c0, 0x0045, 0xaf04, 0xa80e, 0xa104,
+	0xe428, 0xa202, 0xe0c2, 0x004a, 0xe0c0, 0x0111, 0xf7e8, 0xca28,
+	0xf7f8, 0xca48, 0xa802, 0xf7e8, 0xa208, 0xae14, 0xa102, 0xe190,
+	0xf7e2, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xe0c0, 0x041f, 0xf7e8,
+	0xa200, 0xe0c2, 0x041c, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xe004,
+	0x0078, 0xe0c2, 0x0009, 0xa200, 0xe0c2, 0x0009, 0xe0c0, 0x000d,
+	0xf7e8, 0xe42e, 0xc001, 0x3443, 0x3c42, 0xc000, 0xe42e, 0xc001,
+	0x2c43, 0x2e42, 0xc000, 0xe42a, 0x1c52, 0xf0b4, 0xe04a, 0xaf10,
+	0x1850, 0xf074, 0xe009, 0x00ff, 0x1a51, 0xf034, 0xa202, 0xe42e,
+	0xa2fe, 0xe42e, 0xe41e, 0x023a, 0xd160, 0x0620, 0xe004, 0x0019,
+	0xae18, 0xcec0, 0xe42e, 0xe41e, 0x024f, 0xe000, 0x0040, 0xce50,
+	0xa200, 0xd022, 0x00ff, 0xe184, 0x0236, 0xce52, 0xe190, 0xe41e,
+	0x0257, 0xe42e, 0xa204, 0xae22, 0xcc9e, 0xa200, 0xcc72, 0xcc8c,
+	0xcc8e, 0xe004, 0xa810, 0xae20, 0xe00a, 0x9322, 0xce4a, 0xd16f,
+	0x0003, 0xe190, 0xe190, 0xe190, 0xd16f, 0x0000, 0xe42e, 0xe004,
+	0x0030, 0xce50, 0xca50, 0xa802, 0xf7ea, 0xc000, 0xe42e, 0xe004,
+	0x0020, 0xce50, 0xe42e, 0xa200, 0xe0c2, 0x041c, 0xe42e, 0xe41e,
+	0x02bb, 0xe42a, 0xe0c0, 0x0061, 0xe008, 0x001f, 0xe00a, 0x0100,
+	0xe0c2, 0x041c, 0xe41e, 0x02f1, 0xe41e, 0x032b, 0xae12, 0xe0c2,
+	0x041e, 0xe41e, 0x031b, 0xe42e, 0xe41e, 0x02df, 0xe42a, 0xe0c0,
+	0x041f, 0xf7e8, 0xe0c0, 0x0210, 0xa804, 0xf118, 0xe0c0, 0x0215,
+	0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0216, 0xf0be, 0xe0c0, 0x0213,
+	0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0214, 0xf03e, 0xe0c0, 0x020b,
+	0xe00a, 0x0100, 0xe0c2, 0x041c, 0xe41e, 0x02f1, 0xe41e, 0x032b,
+	0xae12, 0xe0c1, 0x0210, 0xa803, 0xae15, 0xe056, 0xe0c1, 0x0204,
+	0xaf0b, 0xa87f, 0xae07, 0xe056, 0xe0c1, 0x0204, 0xa80f, 0xe056,
+	0xe0c2, 0x041e, 0xe41e, 0x031b, 0xe42e, 0xe0c0, 0x041f, 0xf7e8,
+	0xe0c0, 0x041f, 0xf7e8, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xa200,
+	0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xa203, 0xae19, 0xe052,
+	0xf1da, 0xe0c0, 0x0060, 0xaf08, 0xa806, 0xf18a, 0xe0c0, 0x0060,
+	0xa81e, 0xe016, 0xe0c1, 0x0060, 0xa821, 0xe017, 0xe056, 0xf0ea,
+	0xe0c0, 0x0044, 0xaf12, 0xa806, 0xe016, 0xe0c1, 0x0044, 0xaf17,
+	0xa803, 0xe056, 0xf03a, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xe0c0,
+	0x0044, 0xa203, 0xae19, 0xe052, 0xf0ba, 0xe41e, 0x02bb, 0xf088,
+	0xe0c0, 0x0044, 0xaf12, 0xa806, 0xf038, 0xa202, 0xe42e, 0xa200,
+	0xe42e, 0xe0c0, 0x041c, 0xe008, 0x00ff, 0xcca4, 0xc785, 0xe018,
+	0xe000, 0x0500, 0xa002, 0xae04, 0xe0c2, 0x041a, 0xa202, 0xe0c2,
+	0x0418, 0xe0c0, 0x0419, 0xf7ea, 0xa202, 0xe0c2, 0x0418, 0xe0c0,
+	0x0419, 0xf7ea, 0xe0c0, 0x041b, 0xaf20, 0xa01e, 0xaf08, 0xae28,
+	0xe0c1, 0x041b, 0xe009, 0xffff, 0xa01f, 0xaf09, 0xae09, 0xe056,
+	0xe0c2, 0x041d, 0xe42e, 0xe0c0, 0x041c, 0xe00a, 0x0200, 0xe0c2,
+	0x041c, 0xa228, 0xa102, 0xf7f0, 0xe0c0, 0x041c, 0xe00c, 0x0200,
+	0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xaf04, 0xa802, 0xe42e,
+	0xe40e, 0x1343, 0xe40e, 0x0354, 0xe40e, 0x0358, 0xe40e, 0x035c,
+	0xe40e, 0x0364, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x0368, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe41e, 0x0491, 0xe40e, 0x00a4,
+	0xe41e, 0x04e1, 0xe40e, 0x00a4, 0xe41e, 0x025b, 0xe41e, 0x04e2,
+	0xe41e, 0x02ad, 0xe40e, 0x00a4, 0xe41e, 0x06e2, 0xe40e, 0x00a4,
+	0xe41e, 0x0705, 0xe40e, 0x00a4, 0xe0c1, 0x0044, 0xa80f, 0xe056,
+	0xe42e, 0xa200, 0xe41e, 0x036c, 0xe42e, 0xe0c1, 0x0044, 0xaf0d,
+	0xae03, 0xe056, 0xe008, 0x003f, 0xe42e, 0xe0c1, 0x0044, 0xaf17,
+	0xa803, 0xe42e, 0xe0c1, 0x0044, 0xaf17, 0xa803, 0xa105, 0xf039,
+	0xa213, 0xe42e, 0xa201, 0xe42e, 0xa203, 0xe0c3, 0x040d, 0xe0c1,
+	0x0420, 0xa803, 0xf7db, 0xe160, 0x0003, 0xe166, 0x0500, 0xe167,
+	0x0500, 0x284d, 0xf1b6, 0xa102, 0xcc44, 0xe184, 0x03b4, 0xa200,
+	0xe41e, 0x036c, 0xaf04, 0xe41e, 0x0375, 0xae20, 0x2e62, 0xe056,
+	0x9f17, 0x2ad3, 0xf04b, 0x2009, 0x4c0a, 0xf04e, 0x2050, 0x4c51,
+	0xae08, 0x9f17, 0xe41e, 0x03ba, 0xe190, 0xe190, 0xa201, 0xe0c3,
+	0x040d, 0xe42e, 0x2116, 0x4d16, 0x9f17, 0x2116, 0x4d16, 0x9f17,
+	0x2116, 0x4d16, 0x9f17, 0xe42e, 0xe0c0, 0x0044, 0xaf20, 0xa802,
+	0xe428, 0xe0c0, 0x0060, 0xa860, 0xe42a, 0xe0c0, 0x0061, 0xa83e,
+	0xa203, 0xe0c3, 0x040d, 0xcca4, 0xc785, 0xe018, 0xe000, 0x0500,
+	0xe09e, 0xe0c1, 0x0420, 0xa803, 0xf7db, 0xa200, 0xe41e, 0x0371,
+	0xa80e, 0xaf04, 0xe41e, 0x0375, 0xe41e, 0x037d, 0xe40b, 0x03ed,
+	0xa81e, 0xe41e, 0x0382, 0xae09, 0xe056, 0xae20, 0xe0c1, 0x006e,
+	0xe009, 0x1fff, 0xe056, 0x9f17, 0xe0c0, 0x0060, 0xa822, 0xa122,
+	0xf04a, 0x2050, 0x4c51, 0xf03e, 0x2051, 0x4c50, 0xae08, 0x9f17,
+	0xe0c0, 0x0062, 0x9f17, 0xe0c0, 0x0063, 0x9f17, 0xe0c0, 0x0064,
+	0x9f17, 0xa201, 0xe0c3, 0x040d, 0xe42e, 0x3cec, 0xe0c0, 0x0041,
+	0xe005, 0x0020, 0xae11, 0xe042, 0xce20, 0xd111, 0x0500, 0xd112,
+	0x00c0, 0x88ec, 0x0113, 0xca29, 0xf7f9, 0xe190, 0xe42e, 0xe0c0,
+	0x0067, 0x30d1, 0xaf02, 0x30d2, 0xaf02, 0x30d3, 0xaf02, 0x30c0,
+	0xe0c0, 0x0062, 0x3063, 0xaf10, 0x3010, 0xe42e, 0x2009, 0x4c0a,
+	0xe0c2, 0x0071, 0x2821, 0xe0c2, 0x007a, 0x2c20, 0xe0c2, 0x0079,
+	0x2a39, 0xae0f, 0x28c2, 0xa80e, 0xae02, 0x4c35, 0xae02, 0x4c30,
+	0xae02, 0x4c23, 0xae02, 0x4c22, 0xe056, 0xe0c2, 0x0075, 0x28ad,
+	0x2ae0, 0xae02, 0xe01b, 0xe056, 0xae0e, 0xf09b, 0x2ae0, 0xa81f,
+	0xe056, 0xae10, 0x2ae0, 0xaf09, 0xe056, 0xf03e, 0xae10, 0x4ce1,
+	0xe0c2, 0x007b, 0x2a7a, 0xb60b, 0xae09, 0x28e2, 0xe056, 0xe0c2,
+	0x0072, 0xa208, 0x0863, 0xe0c2, 0x0073, 0x2819, 0xe0c2, 0x0074,
+	0x281f, 0xe0c2, 0x0070, 0x281f, 0xe016, 0x58f0, 0xe0c2, 0x0078,
+	0xe42e, 0xe0c0, 0x0045, 0xaf08, 0x3091, 0xe0c0, 0x0060, 0xe049,
+	0xa81f, 0x3e76, 0xaf08, 0x3075, 0xaf02, 0x3071, 0xe0c0, 0x0065,
+	0xaf04, 0x301e, 0xaf02, 0xa806, 0x3c1d, 0xa200, 0x3ce3, 0xe0c0,
+	0x006c, 0xe002, 0x0088, 0x3cda, 0xe0c0, 0x0065, 0xaf0a, 0x30e3,
+	0xe42e, 0xa200, 0xcc4a, 0xcc4c, 0xd130, 0x0003, 0xd03a, 0x0003,
+	0xd008, 0x0000, 0xa200, 0xe0c2, 0x0128, 0xe41e, 0x0148, 0xe41e,
+	0x023a, 0xe41e, 0x04cc, 0xe41e, 0x0720, 0xe41e, 0x128c, 0xa200,
+	0x3c1f, 0xe41e, 0x041f, 0xa204, 0x3cdd, 0xe41e, 0x12f2, 0xe41e,
+	0x07d3, 0xf15d, 0x2830, 0xf04a, 0xe41e, 0x13cc, 0xe128, 0x2810,
+	0xf038, 0x280f, 0x3c15, 0x2863, 0x2a35, 0xb612, 0x3c63, 0xe41e,
+	0x0728, 0xf05a, 0xa202, 0x3c1f, 0xa202, 0x3c19, 0xe41e, 0x146e,
+	0xe41e, 0x042e, 0xe16a, 0xe42e, 0xe0c0, 0x0040, 0xa259, 0xae17,
+	0xe042, 0xe005, 0x1e00, 0xae03, 0xe042, 0xca29, 0xf7f9, 0xce20,
+	0xd111, 0x0200, 0xd112, 0x0100, 0xd113, 0x0003, 0xca28, 0xf7f8,
+	0xe42e, 0xe42e, 0xa200, 0xcc4a, 0xcc4c, 0xd130, 0x0003, 0xd03a,
+	0x0003, 0xd008, 0x0000, 0xe41e, 0x06da, 0xe41e, 0x0471, 0xe41e,
+	0x07be, 0xe41e, 0x1305, 0xa2fc, 0x3c1b, 0xa2fa, 0x3c1c, 0xa200,
+	0x3c1f, 0xa206, 0xe41e, 0x040d, 0xe41e, 0x038c, 0xe41e, 0x03c4,
+	0xe41e, 0x025f, 0xe41e, 0x1433, 0xf0b8, 0x2830, 0xe418, 0x067b,
+	0x2830, 0xe41a, 0x068a, 0xe41e, 0x1433, 0xe40a, 0x0544, 0xa202,
+	0x3c1f, 0xe0c0, 0x0045, 0xaf04, 0xa802, 0xe40a, 0x062c, 0x2819,
+	0xf1a6, 0x2819, 0xa102, 0x3c19, 0x28a4, 0xf0a4, 0xe41e, 0x12a6,
+	0x3c72, 0xe41e, 0x12b4, 0xe41e, 0x11ff, 0xe419, 0x11c2, 0x2a63,
+	0x28a1, 0xf02b, 0x28a3, 0x3c1c, 0x3ca4, 0xa2fe, 0x3ca1, 0x3ca3,
+	0xe40e, 0x062c, 0x2819, 0xf0a4, 0x28a1, 0x2a63, 0xf02b, 0x28a3,
+	0x3ca3, 0xe0c0, 0x0060, 0xaf08, 0xf5d8, 0xa2fe, 0x3ca1, 0x3c1c,
+	0xa2fc, 0x3c1b, 0xe40e, 0x062c, 0x2815, 0xf1ca, 0x2817, 0xa108,
+	0xf198, 0x28a4, 0xf064, 0xe41e, 0x12a6, 0x3c72, 0xe41e, 0x12b4,
+	0xe41e, 0x11ff, 0xe419, 0x11c2, 0x28a2, 0x2a63, 0xf02b, 0x28a6,
+	0x3ca5, 0x3c1c, 0x3ca4, 0xa200, 0x3c17, 0xa202, 0x3c74, 0xe40e,
+	0x062c, 0xa2fe, 0x3c1b, 0xa202, 0x3c1f, 0xe41e, 0x07af, 0xe40a,
+	0x062c, 0xa200, 0x3c1a, 0xa2fc, 0x3c1b, 0xa202, 0x3c1f, 0x2830,
+	0xe418, 0x0869, 0xe404, 0x050f, 0x2830, 0xe41a, 0x0819, 0xe404,
+	0x050f, 0x281f, 0xb61a, 0x3c1f, 0xe40d, 0x062c, 0x281e, 0xf0ea,
+	0x2824, 0xf0aa, 0x2891, 0xf05a, 0xa202, 0x3c1f, 0xe40e, 0x062c,
+	0xe41e, 0x067b, 0xf63e, 0xe40e, 0x05a8, 0x281d, 0xf1aa, 0xa102,
+	0xf04a, 0xa102, 0xf05a, 0xf0be, 0x2824, 0xf13a, 0xf08e, 0x2824,
+	0xa104, 0xf0f8, 0x2815, 0xf03a, 0xa204, 0x3c17, 0xe41e, 0x067b,
+	0xa200, 0x3c46, 0xa2fc, 0x3ca5, 0x3c1c, 0x3ca4, 0xe40e, 0x062c,
+	0x2815, 0xf19a, 0x282d, 0xf178, 0x28a4, 0xf064, 0xe41e, 0x12a6,
+	0x3c72, 0xe41e, 0x12b4, 0xe41e, 0x11ff, 0xe419, 0x11c2, 0xa2fa,
+	0x3c1c, 0xa2fc, 0x3c1b, 0x3ca4, 0xa206, 0x3c17, 0xa202, 0x3c74,
+	0xe40e, 0x062c, 0xe41e, 0x0e41, 0x286d, 0xe016, 0x4466, 0xf0ba,
+	0x28a5, 0xe000, 0x0312, 0xe092, 0xa201, 0x3f01, 0xa200, 0x3c1f,
+	0xe40e, 0x062c, 0x282d, 0x2a3f, 0xe017, 0x3e00, 0x2ac2, 0xa103,
+	0xe017, 0x4e00, 0xe052, 0xf1c8, 0xe162, 0x0300, 0xa200, 0xc711,
+	0x3d12, 0x3c44, 0x3c3e, 0x3c0d, 0x3c0c, 0x3cb5, 0x3cb6, 0x3c6c,
+	0x3c0b, 0x2852, 0x3c43, 0xa202, 0x3c42, 0xe004, 0x1000, 0xcf02,
+	0xd1b3, 0x0001, 0xe41e, 0x15dd, 0xa200, 0x3c46, 0xf1ce, 0xe41e,
+	0x020f, 0xa203, 0xb609, 0x3e1f, 0xe404, 0x062c, 0x2836, 0xe016,
+	0x4430, 0xf0a8, 0xe41e, 0x14c6, 0xa203, 0xb615, 0x3e1f, 0xe40a,
+	0x062c, 0xe40e, 0x0612, 0xe41e, 0x152a, 0xa203, 0xb615, 0x3e1f,
+	0xe40a, 0x062c, 0xe41e, 0x1049, 0x2891, 0xf0fa, 0x2815, 0xf0da,
+	0x2824, 0xa102, 0xf0a8, 0xe41e, 0x142e, 0xba3e, 0xe002, 0x01b6,
+	0xf048, 0xa202, 0x3c1a, 0x3c1f, 0x244a, 0x4c4b, 0xf068, 0xa2fe,
+	0x3ca5, 0x3ca4, 0xa2fa, 0x3c1c, 0x281b, 0xe0c2, 0x0077, 0x281c,
+	0xe0c2, 0x0071, 0xa202, 0x2a1b, 0xb60a, 0x044a, 0x0c4b, 0x344a,
+	0x3c4b, 0xe0c2, 0x0070, 0x2846, 0xe0c2, 0x0072, 0x2409, 0x4c0a,
+	0xe0c2, 0x006f, 0x282d, 0xf058, 0x2815, 0xf03a, 0xa208, 0x3c24,
+	0x28ae, 0xae2a, 0x4c24, 0x2aad, 0xae25, 0xe056, 0x2a2d, 0xae0d,
+	0xe056, 0xe0c2, 0x0073, 0x2a7a, 0xb60b, 0xae09, 0x28e2, 0xe056,
+	0xe0c2, 0x007c, 0x2821, 0xe0c2, 0x007e, 0x2c20, 0xe0c2, 0x007d,
+	0xe41e, 0x0798, 0x281a, 0xae20, 0x4c1f, 0xe0c2, 0x0076, 0xe0c0,
+	0x0076, 0x2add, 0xae23, 0xe056, 0xe0c2, 0x0076, 0xc84a, 0xc84d,
+	0xae20, 0xe056, 0xe0c2, 0x0053, 0xa200, 0xe0c2, 0x0074, 0xe41e,
+	0x146e, 0xe16a, 0xe42e, 0xa200, 0x2a30, 0xf05b, 0x282e, 0xe01a,
+	0xae0c, 0xa920, 0xcf00, 0xd199, 0x0000, 0xd190, 0x0004, 0xcb20,
+	0xf7f8, 0xe42e, 0xa200, 0x3cae, 0xd199, 0x0000, 0xd180, 0x0000,
+	0xd190, 0x0004, 0xcb20, 0xf7f8, 0xe41e, 0x1433, 0xb7f0, 0xe428,
+	0xba3e, 0xe002, 0x0100, 0xe404, 0x06d6, 0xa13e, 0xf030, 0xe40e,
+	0x06d6, 0xa102, 0xe404, 0x06d6, 0xe002, 0x000f, 0xf060, 0xba7e,
+	0xe41e, 0x0933, 0xe40e, 0x0690, 0xe002, 0x0081, 0xf068, 0xba7e,
+	0xe41e, 0x090b, 0xe40e, 0x0690, 0xa104, 0xf068, 0xba7e, 0xe41e,
+	0x0c1e, 0xe40e, 0x0690, 0xa102, 0xf068, 0xba7e, 0xe41e, 0x0a21,
+	0xe40e, 0x0690, 0xa104, 0xf068, 0xba7e, 0xe41e, 0x0912, 0xe40e,
+	0x0690, 0xa102, 0xf028, 0xe42e, 0xba7e, 0x2a74, 0xe40b, 0x0690,
+	0xa11a, 0xe408, 0x0690, 0xba7e, 0xe40e, 0x0690, 0xba7e, 0xe40e,
+	0x0690, 0xe42e, 0xa200, 0x3ce9, 0x3ce5, 0x3cd6, 0x3c3f, 0x3c46,
+	0x3cbe, 0xe42e, 0xe41e, 0x10af, 0xe41e, 0x0174, 0xca28, 0xf7f8,
+	0xe0c0, 0x0042, 0xce20, 0xd111, 0x0500, 0xd112, 0x00c4, 0xd113,
+	0x0003, 0xca29, 0xf7f9, 0xa204, 0xe41e, 0x040d, 0xe0c0, 0x0060,
+	0x3c4d, 0xe0c0, 0x0061, 0x3c62, 0xe0c0, 0x006e, 0xe41e, 0x020a,
+	0xe41e, 0x0743, 0xe41e, 0x038c, 0xe42e, 0xe41e, 0x0743, 0xe41e,
+	0x128c, 0xa202, 0x3c19, 0xe167, 0x0312, 0xe166, 0x0054, 0xa200,
+	0x3c06, 0x284d, 0xa102, 0xcc44, 0xe184, 0x071d, 0x9e06, 0x5c06,
+	0xa802, 0xb690, 0x3d17, 0x2806, 0xa002, 0x3c06, 0xe190, 0xe42e,
+	0xa2fe, 0x3c21, 0x3c7a, 0xe0c2, 0x0079, 0xe0c2, 0x007a, 0xe42e,
+	0xa23c, 0x3cf0, 0x2850, 0xf166, 0xe002, 0x0078, 0xf130, 0x2851,
+	0xf116, 0xe002, 0x0078, 0xf0e0, 0x2852, 0xe002, 0x1fe0, 0xf0a0,
+	0xe0c0, 0x0059, 0xa106, 0xf048, 0xe41e, 0x1433, 0xf038, 0xa202,
+	0xe42e, 0xa200, 0xe42e, 0xa200, 0x3c4a, 0x3c4b, 0x3c72, 0x3c73,
+	0xa2fe, 0x3ca2, 0x3ca3, 0x3ca4, 0x3ca5, 0x3ca0, 0x3ca1, 0xa200,
+	0x3c6d, 0x3ca7, 0x3c74, 0xe161, 0x0312, 0x2a4d, 0xa103, 0x3e00,
+	0x8600, 0x3d11, 0xe42e, 0x28a7, 0x3c06, 0x2806, 0xe000, 0x0312,
+	0xe092, 0x2901, 0xf0da, 0x2806, 0xa002, 0x3c06, 0x184d, 0xf038,
+	0xa200, 0x3c06, 0x2806, 0x18a7, 0xf718, 0xa2fe, 0xe42e, 0xa208,
+	0xb652, 0x3d01, 0x2806, 0xa002, 0x3ca7, 0x184d, 0xf038, 0xa200,
+	0x3ca7, 0x2806, 0xe42e, 0xe424, 0xe000, 0x0312, 0xe092, 0xa200,
+	0x3d01, 0xe42e, 0xe000, 0x0312, 0xe092, 0x2901, 0xe056, 0x3d01,
+	0xe42e, 0xe000, 0x0312, 0xe092, 0x2901, 0xa806, 0x3d01, 0xe42e,
+	0xe424, 0xe000, 0x0312, 0xe092, 0x2901, 0xa80a, 0x3d01, 0xe42e,
+	0xe004, 0x0312, 0xe09e, 0xe004, 0x0054, 0xe09c, 0x284d, 0xa102,
+	0xcc44, 0xa200, 0x3c06, 0xe184, 0x07ac, 0x2b17, 0xaf05, 0xa803,
+	0x5a06, 0xe056, 0x2a06, 0xa003, 0x3e06, 0x9f06, 0xe42e, 0xe161,
+	0x0312, 0x284d, 0xa102, 0xcc44, 0xa200, 0xe184, 0x07ba, 0x2b11,
+	0xa80d, 0xe01b, 0xe042, 0x184d, 0xe01a, 0xe42e, 0xa200, 0x3c06,
+	0xe004, 0x0054, 0xe09c, 0x284d, 0xa102, 0xcc44, 0xe184, 0x07d1,
+	0x9e06, 0x5c06, 0xa802, 0xf048, 0x2806, 0xe412, 0x0789, 0x2a06,
+	0xa003, 0x3e06, 0xe42e, 0xa23e, 0x3cf0, 0xd130, 0x0003, 0xd199,
+	0x0004, 0xd190, 0x0004, 0xe41e, 0x1433, 0xa908, 0xcf32, 0xcb20,
+	0xf7b8, 0xe41e, 0x1433, 0xf348, 0xcb32, 0xaf08, 0xa102, 0xf1da,
+	0xa102, 0xf27a, 0xba3e, 0xe002, 0x01b0, 0xf058, 0xba7e, 0xe41e,
+	0x090b, 0xf68e, 0xba7e, 0xe002, 0x012f, 0xf640, 0xe000, 0x000f,
+	0xf614, 0xe41e, 0x0933, 0xf1cd, 0xa200, 0x3c30, 0x3c34, 0x3c35,
+	0x3c36, 0x3c37, 0x3c2e, 0xe42e, 0xe0c0, 0x0067, 0xaf10, 0xa802,
+	0xf088, 0xba6a, 0xe41e, 0x0af8, 0xf0bd, 0xa202, 0x3c30, 0xe42e,
+	0xba60, 0xe41e, 0x0d7f, 0xf46a, 0xa202, 0x3c30, 0xe42e, 0xe16b,
+	0xe42e, 0xa200, 0x3cae, 0xd199, 0x0000, 0xd180, 0x0000, 0xd190,
+	0x0004, 0xcb20, 0xf7f8, 0xe41e, 0x1433, 0xb7f0, 0xe428, 0xe41e,
+	0x149a, 0xba7e, 0xe002, 0x0100, 0xf394, 0xa13e, 0xf030, 0xe40e,
+	0x081f, 0xa102, 0xf334, 0xe002, 0x000f, 0xf060, 0xe41e, 0x0933,
+	0xf2dd, 0xe40e, 0x081f, 0xe002, 0x0081, 0xf058, 0xe41e, 0x090b,
+	0xe40e, 0x081f, 0xa104, 0xf058, 0xe41e, 0x0c1e, 0xe40e, 0x081f,
+	0xa102, 0xf058, 0xe41e, 0x0a21, 0xe40e, 0x081f, 0xa104, 0xf058,
+	0xe41e, 0x0912, 0xe40e, 0x081f, 0xa102, 0xf078, 0xe41e, 0x0e33,
+	0xe41e, 0x0a2c, 0xf0ba, 0xe42e, 0x2a74, 0xe40b, 0x081f, 0xa11a,
+	0xe408, 0x081f, 0xba7e, 0xe40e, 0x081f, 0xe41e, 0x0e3e, 0xe16b,
+	0xe42e, 0x28dd, 0xa802, 0x3cdd, 0x282e, 0xe01a, 0xae0c, 0xa920,
+	0xcf00, 0xd199, 0x0000, 0xd190, 0x0004, 0xcb20, 0xf7f8, 0xe41e,
+	0x1433, 0xb7f0, 0xe428, 0xe41e, 0x149a, 0x282e, 0xf08a, 0xba60,
+	0xe41e, 0x0e33, 0xe41e, 0x0d7f, 0xf09a, 0xe42e, 0xba6a, 0xe41e,
+	0x0e33, 0xe41e, 0x0af8, 0xf02d, 0xe42e, 0xe16a, 0xe41e, 0x142e,
+	0xf59e, 0xe41e, 0x0e3e, 0xe16b, 0xe42e, 0xba5e, 0x2860, 0xa120,
+	0x3c48, 0x7448, 0x2852, 0xe41e, 0x0d4d, 0x3c48, 0x7448, 0x3c01,
+	0x1852, 0xf034, 0x2852, 0x3c01, 0xba48, 0x3c27, 0xba40, 0xe40a,
+	0x08e5, 0xa201, 0xba40, 0xb431, 0xf7e8, 0xe0c3, 0x0078, 0xba40,
+	0xe40a, 0x08e5, 0x2c20, 0xe41e, 0x0d4d, 0x3c48, 0x7448, 0x3c2b,
+	0xe0c2, 0x0079, 0xba40, 0xe40a, 0x08e5, 0xba42, 0x3c24, 0xa106,
+	0xe016, 0x3c3f, 0xba44, 0xe000, 0x0220, 0xe09e, 0x2907, 0x3c26,
+	0x2824, 0xf1ca, 0xba44, 0x3c28, 0x3c0c, 0xa102, 0x3c29, 0x3c11,
+	0xa202, 0x5829, 0xa102, 0x3c2a, 0x3c12, 0x2824, 0xa104, 0xf0e8,
+	0xba44, 0x3c0d, 0xa102, 0x3c13, 0xa202, 0x5813, 0xa102, 0x3c14,
+	0xe004, 0x0040, 0x4c0d, 0xae0c, 0x4c0c, 0x2801, 0xe42e, 0x3c05,
+	0xf028, 0xba60, 0xa224, 0x3cf0, 0xba40, 0xf1ca, 0x2852, 0xe41e,
+	0x0e1d, 0x3c48, 0x7648, 0x3e01, 0xa116, 0xf076, 0x2805, 0xf058,
+	0xa224, 0x3cf0, 0xba40, 0xf0ea, 0x2805, 0xf038, 0xba48, 0x3c27,
+	0xa224, 0x3cf0, 0xba40, 0xf06a, 0x2805, 0xf028, 0xba42, 0x2801,
+	0xe42e, 0xa2fe, 0xe42e, 0xba4e, 0x3ce0, 0xa200, 0x3cd5, 0xe41e,
+	0x0c19, 0xe42e, 0xba40, 0xf08a, 0xba46, 0xa102, 0xe424, 0xa108,
+	0xe420, 0xba44, 0xe42a, 0xba46, 0xa102, 0xe428, 0xba40, 0xf08a,
+	0xba44, 0xba40, 0xba40, 0xf04a, 0xba4e, 0xba4e, 0xba4e, 0xe41e,
+	0x0d31, 0xe42a, 0xa202, 0x3cd5, 0xe41e, 0x0c19, 0xe41e, 0x0d31,
+	0xe42a, 0xba7e, 0xe42e, 0xa202, 0x3c02, 0xba40, 0xba4e, 0x3ce1,
+	0xba40, 0xf0da, 0xa202, 0x3cf0, 0xba46, 0xa102, 0xe404, 0x0a1f,
+	0xa108, 0xe400, 0x0a1f, 0xa00a, 0x3c02, 0xba44, 0xba46, 0x3ce2,
+	0xa11e, 0xf0f8, 0xa204, 0x3cf0, 0xba4e, 0x3c7a, 0xe40a, 0x0a1f,
+	0xa206, 0x3cf0, 0xba4f, 0xe40b, 0x0a1f, 0xae11, 0x4e7a, 0x3e7a,
+	0xba40, 0xf25a, 0xa208, 0x3cf0, 0xba42, 0xa102, 0xe408, 0x0a1f,
+	0xba40, 0xba40, 0xf1ca, 0xba5c, 0xa20a, 0x3cf0, 0xba40, 0xe40a,
+	0x0a1f, 0xba5c, 0xba40, 0xe40a, 0x0a1f, 0xba5c, 0xba40, 0xe40a,
+	0x0a1f, 0xba44, 0xba54, 0xa20a, 0x3cf0, 0xba40, 0xe40a, 0x0a1f,
+	0xba5c, 0xa20a, 0x3cf0, 0xba40, 0xe40a, 0x0a1f, 0xa20c, 0x3cf0,
+	0xba42, 0xe408, 0x0a1f, 0xa20a, 0x3cf0, 0xba40, 0xe40a, 0x0a1f,
+	0xa2fe, 0x3c21, 0xa20e, 0x3cf0, 0xba5e, 0xe40a, 0x0a1f, 0x3c20,
+	0xa20a, 0x3cf0, 0xba40, 0xba40, 0xe40a, 0x09a0, 0x2c20, 0xe41e,
+	0x0d4d, 0x3c48, 0xa210, 0x3cf0, 0x7448, 0xe40a, 0x0a1f, 0x3c21,
+	0xa20a, 0x3cf0, 0xba40, 0xe40a, 0x0a1f, 0xba58, 0x3c09, 0xa01e,
+	0xaf08, 0x3c50, 0xa20a, 0x3cf0, 0xba41, 0xba58, 0x3c0a, 0xa01e,
+	0xaf08, 0x3c51, 0xa20a, 0x3cf0, 0xba40, 0xe40a, 0x0a1f, 0xba40,
+	0x3cad, 0xa212, 0x3cf0, 0xba40, 0xe40a, 0x0a1f, 0x2a02, 0xa103,
+	0xb636, 0xb652, 0x3c48, 0xa215, 0x3ef0, 0x7648, 0x28c0, 0xf05a,
+	0xa214, 0x3cf0, 0xe409, 0x0a1f, 0xf18b, 0xa103, 0xe40b, 0x0a1f,
+	0xa103, 0xe04a, 0xe016, 0x3cc1, 0xa103, 0xe40b, 0x0a1f, 0xba4a,
+	0x3cc2, 0xba42, 0x3cc4, 0xba40, 0x3cc3, 0x28c2, 0xa104, 0xf054,
+	0xa214, 0x3cf0, 0xe40e, 0x0a1f, 0xa216, 0x3cf0, 0xba40, 0xe408,
+	0x0a1f, 0xba40, 0x3c0e, 0xf07a, 0xba40, 0xe418, 0x0d57, 0xba40,
+	0xe418, 0x0d6b, 0x2802, 0xa102, 0xe40a, 0x09f8, 0xba40, 0x3c18,
+	0xa218, 0x3cf0, 0xba40, 0xe40a, 0x0a1f, 0xba40, 0xba40, 0x3c22,
+	0xe40a, 0x0a03, 0xba40, 0x3c23, 0x2802, 0xa102, 0xe40a, 0x0a0d,
+	0xba40, 0xf03a, 0xba42, 0xba40, 0xba40, 0x3c2c, 0xa21a, 0x3cf0,
+	0xba40, 0xe408, 0x0a1f, 0xe41e, 0x0d31, 0xf0aa, 0xa204, 0x3cd5,
+	0xe41e, 0x0c19, 0x8450, 0x8251, 0xe018, 0x3c52, 0xe42e, 0xe16b,
+	0xe42e, 0xba62, 0xba40, 0xba40, 0xe41e, 0x0d31, 0xe42a, 0xa206,
+	0x3cd5, 0xe41e, 0x0c19, 0xe42e, 0xa200, 0x3cae, 0x3cac, 0xe0c0,
+	0x0059, 0xa106, 0xf048, 0x28dd, 0xa802, 0x3cdd, 0xba42, 0x3c24,
+	0xa106, 0xe016, 0x3c3f, 0xa201, 0xba40, 0xb431, 0xf7e8, 0x3e00,
+	0xe0c3, 0x0078, 0xba40, 0xe40a, 0x0af3, 0x2c20, 0xe41e, 0x0d4d,
+	0xa102, 0xf022, 0xa200, 0xa002, 0x3c48, 0x7448, 0x3c2b, 0xe0c2,
+	0x0079, 0x2824, 0xa104, 0xf0fa, 0x28a9, 0x3ca8, 0x0800, 0x3ca9,
+	0x84a9, 0x8220, 0xe018, 0x082b, 0x3c4e, 0x28b0, 0x3caf, 0x284e,
+	0x3cb0, 0xf1ee, 0x28a8, 0x0800, 0x3c00, 0x8400, 0x8220, 0xe018,
+	0x082b, 0x3c4e, 0x28b2, 0xf048, 0x284e, 0x18af, 0x3cb2, 0x28af,
+	0xc70f, 0x7cb2, 0x3c00, 0x28b0, 0xc70f, 0x7cb2, 0x1800, 0xae02,
+	0x3cb3, 0x284e, 0xc70f, 0x7cb2, 0x1800, 0xae02, 0x3cb4, 0xba40,
+	0xe40a, 0x0af3, 0xba40, 0x3c2d, 0xe40a, 0x0af1, 0xa200, 0x3c25,
+	0x2824, 0xa102, 0xf05a, 0xa104, 0xf058, 0x28c1, 0xf03a, 0xba40,
+	0x3c25, 0x282c, 0xf07a, 0x2824, 0xa104, 0xf042, 0xba40, 0xe408,
+	0x0af3, 0xba44, 0xe000, 0x0220, 0xe09e, 0x2907, 0x3c26, 0x28ad,
+	0xf05a, 0xba40, 0x3cae, 0xba40, 0x3cac, 0x283f, 0x44c1, 0x2ac2,
+	0xe01b, 0xe052, 0xf23a, 0xe162, 0x03b2, 0xd022, 0x0001, 0xe184,
+	0x0ac5, 0xb83c, 0xe40d, 0x0af3, 0xf0ea, 0xa102, 0x3c00, 0xba40,
+	0xf078, 0xa205, 0x5a00, 0xa103, 0x7400, 0xe046, 0xf04e, 0x5800,
+	0x7600, 0xe056, 0x3d12, 0xba40, 0xe40a, 0x0af3, 0x28c3, 0xf06a,
+	0xb83e, 0xe40d, 0x0af3, 0x3c00, 0x7400, 0xba48, 0x3c27, 0x2824,
+	0xe40a, 0x0af1, 0xba44, 0x3c28, 0x3c0c, 0xe40a, 0x0af3, 0xa102,
+	0x3c29, 0x3c11, 0xa202, 0x5829, 0xa102, 0x3c2a, 0x3c12, 0x2824,
+	0xa104, 0xf108, 0xba44, 0x3c0d, 0xe40a, 0x0af3, 0xa102, 0x3c13,
+	0xa202, 0x5813, 0xa102, 0x3c14, 0xe004, 0x0040, 0x4c0d, 0xae0c,
+	0x4c0c, 0xa202, 0xe42e, 0x28dd, 0xa902, 0x3cdd, 0xa200, 0xe42e,
+	0xba4e, 0x3c2b, 0xa202, 0x3cf0, 0xba40, 0xe40a, 0x0c17, 0xa204,
+	0x3cf0, 0xba40, 0xe408, 0x0c17, 0xba40, 0xba40, 0xba40, 0xba44,
+	0x3c02, 0xa10e, 0xe40a, 0x0b2c, 0xba40, 0x3c24, 0xba40, 0x3c39,
+	0xa208, 0x3cf0, 0xba44, 0xe408, 0x0c17, 0xba48, 0x3c27, 0xa204,
+	0x3cf0, 0xba40, 0xe408, 0x0c17, 0xa20a, 0x3cf0, 0xe41e, 0x0d3a,
+	0xe40a, 0x0c17, 0xa200, 0x3c34, 0x3c35, 0x3c36, 0x3c37, 0x3c3a,
+	0x3c25, 0x3c38, 0xe40e, 0x0bd6, 0xa202, 0x3c3a, 0xa200, 0x3c02,
+	0xa20c, 0x3cf0, 0xba44, 0x3c03, 0xa102, 0xe400, 0x0c17, 0xe404,
+	0x0b5e, 0xba44, 0x3c02, 0xa10c, 0xe418, 0x0d3a, 0xba40, 0x3c38,
+	0xba40, 0x3c39, 0xa210, 0x3cf0, 0xba42, 0xe408, 0x0c17, 0xba40,
+	0x3c34, 0xba40, 0x3c35, 0xba40, 0x3c36, 0xa212, 0x3cf0, 0xba44,
+	0xe408, 0x0c17, 0xba40, 0x3c37, 0xa202, 0x3cf0, 0xba40, 0xe40a,
+	0x0c17, 0xa204, 0x3cf0, 0xba44, 0xe408, 0x0c17, 0xa214, 0x3cf0,
+	0xba44, 0xa102, 0xe400, 0x0c17, 0xa002, 0x3c24, 0xa216, 0x3cf0,
+	0xba42, 0xe408, 0x0c17, 0xba40, 0x3c25, 0xa218, 0x3cf0, 0xba44,
+	0xa102, 0xe408, 0x0c17, 0xa21a, 0x3cf0, 0xba40, 0xe408, 0x0c17,
+	0x2802, 0xa10c, 0xf1e8, 0x2803, 0xf1ca, 0xa21c, 0x3cf0, 0xba46,
+	0x3c7a, 0x3ce2, 0xe40a, 0x0c17, 0xba50, 0xa002, 0xae04, 0x3c09,
+	0xba40, 0xe40a, 0x0c17, 0xba50, 0xae04, 0x3c0a, 0x2809, 0xa01e,
+	0xaf08, 0x3c50, 0x280a, 0xa01e, 0xaf08, 0x3c51, 0xe41e, 0x0df5,
+	0x287a, 0xf0da, 0xa11e, 0xf0b8, 0xba4e, 0x3c7a, 0xe40a, 0x0c17,
+	0xba4e, 0xe40a, 0x0c17, 0xae10, 0x4c7a, 0x3c7a, 0x2838, 0x4403,
+	0xf13a, 0xa21e, 0x3cf0, 0xba40, 0xe000, 0x03e8, 0xba4d, 0xe40b,
+	0x0c17, 0x3c21, 0x3e20, 0xe004, 0x1b77, 0xae10, 0xe00a, 0x0040,
+	0xc70f, 0x7c20, 0x3c20, 0x2838, 0xf05a, 0xba42, 0xae10, 0x4c2b,
+	0x3c2b, 0x2839, 0x4403, 0xf09a, 0xba40, 0x3c3b, 0xf068, 0xa220,
+	0x3cf0, 0xba40, 0xe40a, 0x0c17, 0x2836, 0x4403, 0xf06a, 0xa222,
+	0x3cf0, 0xba42, 0xe408, 0x0c17, 0xba48, 0x3c27, 0xba40, 0xf03a,
+	0xba4e, 0xf7de, 0x8450, 0x8251, 0xe018, 0x3c52, 0x2836, 0xf05a,
+	0xa202, 0xe41e, 0x08e7, 0xf344, 0x2838, 0xf078, 0xe004, 0x03e9,
+	0x3c21, 0xe004, 0x7530, 0x3c20, 0xa200, 0x3c22, 0x3c23, 0xa202,
+	0x3c28, 0x3c0c, 0x3c2d, 0xa200, 0x3c29, 0x3c2a, 0xe167, 0x0220,
+	0x2907, 0x3c26, 0x2839, 0xf1ba, 0x283a, 0xf038, 0xa200, 0xf17e,
+	0x283b, 0xf15a, 0xa204, 0x2a50, 0xa12d, 0xf057, 0xa002, 0xa12d,
+	0xf027, 0xa002, 0x3c00, 0xa204, 0x2a51, 0xa125, 0xf057, 0xa002,
+	0xa125, 0xf027, 0xa002, 0xae06, 0x4c00, 0xf01e, 0xe42e, 0xe16b,
+	0xe42e, 0xba3e, 0xe002, 0x01b2, 0xe428, 0xba7e, 0xa200, 0x3cdc,
+	0x2ae3, 0xe0c0, 0x0065, 0xaf0a, 0xa802, 0xe017, 0xe052, 0x3ce5,
+	0xe41e, 0x0c4b, 0xf1ea, 0x2adc, 0xa109, 0xf039, 0xa202, 0x3c16,
+	0x28e3, 0xe408, 0x0c78, 0x2816, 0xf068, 0xba2e, 0xa102, 0xe42a,
+	0xba4e, 0xf7ce, 0xba2e, 0xa102, 0xe42a, 0xba4e, 0xe002, 0x0070,
+	0xf7a8, 0xa202, 0x2a10, 0xf039, 0x3c0f, 0xf02e, 0x3c15, 0xf73e,
+	0x28e3, 0xf2f8, 0xe42e, 0xe164, 0x0630, 0xe163, 0x062c, 0xe162,
+	0x0628, 0xe004, 0x0044, 0x3d12, 0xe004, 0x0069, 0x3d12, 0xe004,
+	0x0076, 0x3d12, 0xe004, 0x0058, 0x3d12, 0xe162, 0x0628, 0xd022,
+	0x0003, 0xe184, 0x0c75, 0xba2e, 0xa102, 0xe42a, 0xba4e, 0x3d03,
+	0x2adc, 0xa803, 0xf049, 0xae10, 0x3cdb, 0xf03e, 0x4cdb, 0x3d14,
+	0x2913, 0x1912, 0x2adc, 0xa003, 0x3edc, 0xe428, 0xa202, 0xe42e,
+	0x2ae3, 0x28d6, 0xa120, 0xb615, 0x3ee3, 0xe40b, 0x0c33, 0x2816,
+	0xf168, 0xba2e, 0xa102, 0xf34a, 0xba4e, 0x2adc, 0xa803, 0xf049,
+	0xae10, 0x3cdb, 0xf03e, 0x4cdb, 0x3d14, 0x2adc, 0xa003, 0x3edc,
+	0xa80f, 0xe41b, 0x0d12, 0x28e3, 0xf36a, 0xf6ce, 0xba2e, 0xa102,
+	0xf1fa, 0xba4e, 0xe002, 0x0070, 0xf088, 0x2a10, 0xf049, 0xa203,
+	0x3e0f, 0xf03e, 0xa203, 0x3e15, 0xe000, 0x0070, 0x2adc, 0xa803,
+	0xf049, 0xae10, 0x3cdb, 0xf03e, 0x4cdb, 0x3d14, 0x2adc, 0xa003,
+	0x3edc, 0xa80f, 0xe41b, 0x0d12, 0x28e3, 0xf15a, 0xf60e, 0x2adc,
+	0xa803, 0xf03b, 0x28db, 0x3d14, 0xa211, 0x28dc, 0xa80e, 0xf0ba,
+	0xe045, 0xaf03, 0xf06b, 0xa103, 0x3e00, 0xa201, 0x8600, 0x3f14,
+	0xe41e, 0x0d12, 0xa201, 0xba2e, 0xa102, 0xf04a, 0xba4e, 0xa203,
+	0xf7be, 0x3ee5, 0xe162, 0x0630, 0x28d5, 0x3d12, 0x28dc, 0x3d12,
+	0x28e5, 0x3d12, 0xa200, 0x3d12, 0xe0c1, 0x006b, 0x28d6, 0xa002,
+	0xae06, 0xe041, 0xaf06, 0x3cd6, 0xca28, 0xf7f8, 0xe180, 0xce21,
+	0xd111, 0x0630, 0xd112, 0x0004, 0xd113, 0x0000, 0xe1e1, 0xe181,
+	0x28e3, 0xe428, 0xa200, 0x3cd8, 0xe0c0, 0x005c, 0xe0c1, 0x0065,
+	0xaf12, 0xa802, 0xaf15, 0xa803, 0xe016, 0xe056, 0xf04a, 0xa200,
+	0x3ce3, 0xe42e, 0x28d9, 0xf05a, 0xe0c0, 0x005d, 0xe42a, 0xf7be,
+	0xe0c0, 0x005d, 0xe00a, 0x0200, 0xe0c2, 0x005d, 0xa202, 0xce00,
+	0x3cd9, 0xf71e, 0xe0c0, 0x006b, 0xe000, 0x0088, 0x08d8, 0xca29,
+	0xf7f9, 0xe180, 0xce20, 0xd111, 0x0630, 0xd112, 0x0004, 0xd113,
+	0x0000, 0xe1e1, 0xe181, 0xe164, 0x0630, 0x28d7, 0x2ad8, 0xa010,
+	0xa011, 0x3cd7, 0x3ed8, 0x1ada, 0xe41b, 0x0cf2, 0xa200, 0x3cd9,
+	0xe42e, 0xe41e, 0x142e, 0xba2e, 0xa102, 0xe016, 0xe428, 0xba4e,
+	0xf7be, 0xe42e, 0x2802, 0xae04, 0xe000, 0x0200, 0xe09e, 0x2917,
+	0x3c09, 0xaf08, 0x3c50, 0x2917, 0x3c0a, 0xaf08, 0x3c51, 0x2917,
+	0x3c32, 0x2907, 0x3c31, 0xe01a, 0xe42e, 0xa102, 0xa201, 0xf04a,
+	0xaf02, 0xa003, 0xf7e8, 0xe04a, 0xe428, 0xa202, 0xe42e, 0xe004,
+	0x0040, 0xe165, 0x0332, 0xba4f, 0xf05b, 0x3e00, 0x3f15, 0xa102,
+	0xf7b0, 0xf06a, 0xa102, 0x3c01, 0x2a00, 0x8601, 0x3f15, 0x28aa,
+	0xa902, 0x3caa, 0xe42e, 0xe004, 0x0040, 0xe165, 0x0372, 0xba4f,
+	0xf05b, 0x3e00, 0x3f15, 0xa102, 0xf7b0, 0xf06a, 0xa102, 0x3c01,
+	0x2a00, 0x8601, 0x3f15, 0x28aa, 0xa904, 0x3caa, 0xe42e, 0xba48,
+	0x3c2f, 0xa104, 0xe402, 0x0dc2, 0xa202, 0x3c2e, 0xba4e, 0x3c2b,
+	0xba44, 0xe404, 0x0dc2, 0xa10c, 0xe400, 0x0dc2, 0xa008, 0xe41e,
+	0x0dc4, 0xba42, 0x3c24, 0xa102, 0xa201, 0x3ebe, 0xf046, 0xa203,
+	0x3e24, 0x3ebe, 0xba40, 0xba48, 0x3c27, 0xba40, 0xf03a, 0xba4e,
+	0xf7de, 0xa200, 0x3c39, 0x3c34, 0x3c35, 0x3c36, 0x3c37, 0x3c3a,
+	0x3c25, 0x3c38, 0x3c22, 0x3c23, 0xa202, 0x3c28, 0x3c0c, 0x3c2d,
+	0xe167, 0x0220, 0x2907, 0x3c26, 0x8450, 0x8251, 0xe018, 0x3c52,
+	0xa2fe, 0x3ce2, 0xe004, 0x03e9, 0x3c21, 0xe004, 0x7530, 0x3c20,
+	0xa202, 0xe42e, 0xa200, 0xe42e, 0xf092, 0xa002, 0xf04a, 0xba4e,
+	0xba4f, 0xf21e, 0xba5e, 0xba5f, 0xf1ee, 0xa207, 0xe045, 0xf107,
+	0xae05, 0xe001, 0x0200, 0xe09f, 0x2917, 0x3c09, 0x2917, 0x3c0a,
+	0x2917, 0x3c32, 0x3c50, 0x2907, 0x3c31, 0x3c51, 0xe42e, 0xf07b,
+	0xe004, 0x00a0, 0xe005, 0x0078, 0xe40e, 0x0dea, 0xe004, 0x0140,
+	0xe005, 0x00f0, 0x3c09, 0x3e0a, 0xa01e, 0xa01f, 0xaf08, 0xaf09,
+	0x3c50, 0x3e51, 0xe41e, 0x0df5, 0xe42e, 0x280a, 0xe002, 0x0190,
+	0xf086, 0xe002, 0x0190, 0xf0a6, 0xe002, 0x0160, 0xf0f6, 0xf16e,
+	0x2850, 0x3c32, 0x2851, 0x3c31, 0xe42e, 0x2850, 0xae02, 0x3c32,
+	0x2851, 0xa002, 0xaf02, 0x3c31, 0xe42e, 0x2850, 0xae04, 0x3c32,
+	0x2851, 0xa006, 0xaf04, 0x3c31, 0xe42e, 0x2850, 0xae06, 0x3c32,
+	0x2851, 0xa00e, 0xaf06, 0x3c31, 0xe42e, 0xe049, 0xa103, 0xa15f,
+	0xa20c, 0xe427, 0xa167, 0xa20e, 0xe427, 0xe003, 0x0129, 0xa212,
+	0xe427, 0xe003, 0x04a4, 0xa216, 0xe427, 0xe003, 0x1290, 0xa21a,
+	0xe427, 0xa21c, 0xe42e, 0x28e9, 0xe428, 0xc001, 0x2417, 0x4c18,
+	0xc000, 0xe0c2, 0x0051, 0xa202, 0x3ce9, 0xe42e, 0xa200, 0x3ce9,
+	0xe42e, 0xa200, 0xcc8e, 0xe0c2, 0x030a, 0xe0c2, 0x0320, 0x2837,
+	0xae02, 0x4c36, 0xae02, 0x4c35, 0xae02, 0x4c34, 0xae04, 0x2ad1,
+	0xb472, 0x4c30, 0xae08, 0xa906, 0xe0c2, 0x0100, 0xa200, 0xe0c2,
+	0x0128, 0x2a75, 0x4e71, 0xb692, 0xae08, 0xa92c, 0xe0c2, 0x017c,
+	0xe004, 0x0014, 0xe0c2, 0x017d, 0xe0c0, 0x0050, 0xe049, 0xe008,
+	0x007f, 0x3cbc, 0xaf11, 0xe009, 0x007f, 0x3ebd, 0x46bc, 0x3ebc,
+	0xa200, 0x2abc, 0xa803, 0xf03b, 0xe00a, 0x0002, 0x2abc, 0xa805,
+	0xf03b, 0xe00a, 0x0009, 0x2abc, 0xa809, 0xf03b, 0xe00a, 0x0020,
+	0x2abc, 0xa811, 0xf03b, 0xe00a, 0x0040, 0xe0c2, 0x040c, 0x2835,
+	0x4c63, 0xf1fa, 0xe0c1, 0x0046, 0xe004, 0x0048, 0xae10, 0xe042,
+	0x2abd, 0xa809, 0xf05b, 0xe161, 0x05e4, 0x2111, 0x4d11, 0xe0c2,
+	0x0211, 0xe0c1, 0x0046, 0xe004, 0x0088, 0xae10, 0xe042, 0x2abd,
+	0xa811, 0xf05b, 0xe161, 0x05e6, 0x2111, 0x4d11, 0xe0c2, 0x0212,
+	0xe0c0, 0x0046, 0xe005, 0x0000, 0xae11, 0xe042, 0x2abd, 0xa805,
+	0xf05b, 0xe161, 0x05e2, 0x2111, 0x4d11, 0xe0c2, 0x0103, 0xe161,
+	0x05c0, 0x2111, 0x4d11, 0xcf42, 0xe0c1, 0x0046, 0xe004, 0x0040,
+	0xae10, 0xe042, 0x2abd, 0xa803, 0xf05b, 0xe161, 0x05e0, 0x2111,
+	0x4d11, 0xcf44, 0x2aaa, 0xe0c3, 0x013d, 0xa803, 0xa200, 0xe419,
+	0x1096, 0x2aaa, 0xa805, 0xa202, 0xe419, 0x1096, 0x2ad3, 0xf04b,
+	0x2009, 0x4c0a, 0xf04e, 0x2050, 0x4c51, 0xae08, 0xe0c2, 0x0101,
+	0xe0c2, 0x0205, 0x2850, 0xae20, 0x4c51, 0xae08, 0xcf60, 0x2837,
+	0xcf68, 0x2a24, 0xa105, 0xe017, 0x3e66, 0x283e, 0xae02, 0x4c18,
+	0xae06, 0x4c0d, 0xae06, 0x4c0c, 0xcf46, 0x282f, 0xae02, 0x4cd2,
+	0xae02, 0x4cd1, 0xae04, 0xa904, 0x4cad, 0xae02, 0x4c2e, 0xae04,
+	0x4c30, 0xae02, 0x2a30, 0xf029, 0xa902, 0xae04, 0x4c24, 0xae02,
+	0x4cae, 0xcf00, 0x2834, 0xae02, 0x4c35, 0xae02, 0x2a24, 0xa105,
+	0xf05b, 0x4c22, 0xae02, 0x4c23, 0xf02e, 0xae02, 0xae02, 0x4c37,
+	0xcf24, 0xa200, 0xe41e, 0x036c, 0xe0c2, 0x0102, 0x2863, 0x4466,
+	0xf078, 0x2a63, 0xe41e, 0x075b, 0x3c1b, 0x3ca2, 0x3ca5, 0x28a0,
+	0x2a66, 0xe41b, 0x0790, 0x2a63, 0xf07b, 0xa201, 0xe41e, 0x075b,
+	0x3ca6, 0x3ca5, 0x3c1b, 0x28a4, 0xe412, 0x12a6, 0x3c72, 0x28a5,
+	0xe41e, 0x1292, 0x3c73, 0x2872, 0xe41e, 0x12b4, 0x2866, 0x3c74,
+	0xf1a8, 0x2824, 0xe016, 0x303e, 0x28be, 0xf058, 0x28a2, 0xa205,
+	0xe412, 0x0782, 0x28a3, 0x3ca5, 0x28a2, 0x2a63, 0xf05b, 0x28a2,
+	0xe412, 0x0789, 0x28a6, 0x3ca3, 0x28bf, 0xf038, 0x28a1, 0x3ca0,
+	0x28a2, 0x3ca1, 0x28be, 0x3cbf, 0xa206, 0xae08, 0x4c24, 0xae06,
+	0xe0c2, 0x0204, 0xa204, 0x2a35, 0x4e63, 0xb632, 0xe0c2, 0x0210,
+	0x3c01, 0xa200, 0xe41e, 0x036c, 0x2a01, 0xae11, 0xe056, 0xe0c2,
+	0x0213, 0xa200, 0xe0c2, 0x0215, 0xa204, 0x2a63, 0x4666, 0x4e35,
+	0xb612, 0xe0c2, 0x0208, 0xf049, 0x2aa2, 0xe0c3, 0x020b, 0x2835,
+	0x4c63, 0xf07a, 0x28a6, 0x2a35, 0xf02b, 0x28a2, 0xe0c2, 0x0214,
+	0x28a1, 0xf174, 0xa202, 0xe0c2, 0x0302, 0x28a0, 0xf052, 0x28a1,
+	0xf032, 0x28a2, 0xb608, 0xe0c2, 0x0380, 0x28a1, 0xf052, 0x28a0,
+	0xf032, 0x28a2, 0xb608, 0xe0c2, 0x0383, 0xa200, 0xe0c2, 0x0302,
+	0xa204, 0x4c18, 0xae02, 0x4c25, 0xe0c2, 0x0303, 0xa20e, 0xe0c2,
+	0x0312, 0xe0c0, 0x0414, 0xe418, 0x018c, 0xe0c0, 0x0414, 0xe41a,
+	0x12bb, 0xa200, 0xe0c2, 0x0308, 0xa200, 0x3c75, 0x3c76, 0x3c71,
+	0xa202, 0x3c78, 0x28a4, 0xe412, 0x11ff, 0x28a5, 0x3c1c, 0xf024,
+	0x3ca4, 0xa202, 0x3c6b, 0xa201, 0x28ac, 0xb6d1, 0xae0b, 0xe0c3,
+	0x0104, 0x2a6d, 0xa105, 0xf05b, 0xa005, 0x2866, 0xb435, 0x3e6d,
+	0xe41e, 0x0274, 0xa202, 0xe0c2, 0x0106, 0xe0c0, 0x0065, 0xaf0c,
+	0xa80e, 0xe40a, 0x1018, 0xca29, 0xf7f9, 0xe180, 0xe0c1, 0x006a,
+	0xce21, 0xd111, 0x0618, 0xd112, 0x000c, 0xd113, 0x0003, 0xca29,
+	0xf7f9, 0xe181, 0xaf04, 0x30e4, 0x28e4, 0xe40a, 0x1018, 0xa210,
+	0x3c00, 0xe162, 0x0312, 0xe163, 0x0610, 0xa201, 0xd022, 0x0002,
+	0xe184, 0x0ffd, 0x2912, 0xa81e, 0xe055, 0xae09, 0x2912, 0xa81e,
+	0xe055, 0x3f13, 0x2800, 0xa102, 0xf03a, 0x3c00, 0xf6fe, 0xca29,
+	0xf7f9, 0xe162, 0x061a, 0x2112, 0x4d12, 0xe180, 0xce20, 0xd111,
+	0x0610, 0xd112, 0x0008, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe181,
+	0xe162, 0x0618, 0xc410, 0xa200, 0x2ae4, 0xb632, 0xae10, 0x3d12,
+	0xa220, 0x3d12, 0xe42e, 0xa200, 0xcc8e, 0xe0c2, 0x0320, 0xe0c2,
+	0x030a, 0x2837, 0xae02, 0x4c36, 0xae02, 0x4c35, 0xae02, 0x4c34,
+	0xae04, 0x2ad1, 0xb472, 0x4c30, 0xae08, 0xa906, 0xe0c2, 0x0100,
+	0x2a75, 0x4e71, 0xb692, 0xae08, 0xa92c, 0xe0c2, 0x017c, 0xe004,
+	0x0014, 0xe0c2, 0x017d, 0xa200, 0xe41e, 0x036c, 0xe0c2, 0x0102,
+	0xe42e, 0xe0c0, 0x0065, 0xaf0a, 0xa802, 0xf16a, 0xe162, 0x0630,
+	0x28d6, 0x3d12, 0x28d7, 0x3d12, 0xe0c0, 0x006b, 0xca29, 0xf7f9,
+	0xe180, 0xce20, 0xd111, 0x0630, 0xd112, 0x0004, 0xd113, 0x0000,
+	0xca28, 0xf7f8, 0xe181, 0xe0c0, 0x0065, 0xe008, 0x0100, 0xf10a,
+	0xca29, 0xf7f9, 0xe0c0, 0x006a, 0xe180, 0xce20, 0xd112, 0x0004,
+	0xd111, 0x0618, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe181, 0xa200,
+	0x3cd7, 0x3cd6, 0x3ce3, 0x3cd8, 0x3cd9, 0xe0c0, 0x0111, 0xf7e8,
+	0x2875, 0x4c71, 0xe42a, 0xa204, 0xae0e, 0x4c50, 0xa102, 0xae0e,
+	0x4c51, 0xa102, 0xe0c1, 0x014b, 0xf7e9, 0xe0c2, 0x014d, 0xa202,
+	0xe0c2, 0x014a, 0xe0c1, 0x014b, 0xf7e9, 0xe42e, 0xe161, 0x0332,
+	0xa201, 0xf05a, 0xe161, 0x0372, 0xe005, 0x0040, 0xa202, 0xe0c2,
+	0x013c, 0xd022, 0x003f, 0xe184, 0x10aa, 0x2911, 0xe0c3, 0x013e,
+	0xe0c2, 0x013f, 0xa003, 0xa200, 0xe0c2, 0x013c, 0xe42e, 0xe167,
+	0x05e0, 0xe166, 0x0064, 0xd022, 0x0003, 0xe184, 0x10b9, 0x9e16,
+	0x3517, 0x3d17, 0xe42e, 0xa201, 0x3ee6, 0x280e, 0xae0a, 0x4c5d,
+	0xe0c2, 0x0115, 0xa27f, 0x2858, 0xf028, 0x2a5e, 0xe0c3, 0x012a,
+	0xa27e, 0xe0c2, 0x0116, 0x28ab, 0xae08, 0x4c58, 0xe0c2, 0x0114,
+	0x2835, 0x4c63, 0xf07a, 0x2859, 0x4435, 0xe016, 0xae0a, 0x4c5d,
+	0xcf6a, 0x2858, 0xe41a, 0x10f1, 0x2858, 0xe016, 0x4c66, 0xf038,
+	0xe41e, 0x1810, 0xe41e, 0x1140, 0xe0c0, 0x0111, 0xf7e8, 0xa202,
+	0xe0c2, 0x0110, 0xe41e, 0x1231, 0x2875, 0x4c71, 0xe418, 0x11d7,
+	0xe42e, 0x2a0b, 0xe0c3, 0x030d, 0xa200, 0x2a66, 0xf03b, 0x2a6c,
+	0xb676, 0x2a5b, 0xb672, 0x2a0b, 0xb632, 0x3c00, 0xae06, 0x4c00,
+	0x3c00, 0xae0c, 0x4c00, 0xe0c2, 0x0309, 0x2866, 0x2a6c, 0xa105,
+	0xe017, 0xe052, 0xe016, 0x3c64, 0xa200, 0x2a6c, 0xa107, 0xb62a,
+	0x4466, 0x3c65, 0xae02, 0x4c64, 0x3ce6, 0xae04, 0x4ce6, 0x3ce6,
+	0xae08, 0x4ce6, 0xe0c2, 0x030c, 0xa200, 0x2a0b, 0x4664, 0xf08b,
+	0x28b5, 0xae0a, 0x4cb5, 0xae0a, 0x4cb6, 0xae0a, 0x4cb6, 0xe0c2,
+	0x030a, 0xa202, 0xae20, 0xe00a, 0x0842, 0x2a0b, 0x4665, 0xf09b,
+	0x2ab7, 0xae0b, 0x4eb7, 0xae0b, 0x4eb8, 0xae0b, 0x4eb8, 0xe056,
+	0xe0c2, 0x030b, 0x2824, 0xa104, 0xe42a, 0xe41e, 0x1810, 0xe42e,
+	0x286b, 0xe0c2, 0x0131, 0xa200, 0x3c6b, 0x285c, 0xe0c2, 0x0130,
+	0xe42e, 0x2069, 0x4c6a, 0xcf48, 0x2856, 0x4c58, 0x4c59, 0xf09a,
+	0xd1b3, 0x0008, 0xd1b3, 0x0010, 0x283f, 0xf058, 0xe40e, 0x1182,
+	0x283f, 0xf11a, 0x2859, 0x2ac5, 0xe016, 0xe017, 0xe052, 0xf0b8,
+	0xe162, 0x03b2, 0x2112, 0x4d0a, 0xcf4c, 0x2112, 0x4d0a, 0xcf54,
+	0xe40e, 0x1182, 0xe162, 0x0301, 0x2112, 0x4d12, 0xcf4c, 0x2112,
+	0x4d12, 0xcf4e, 0x2112, 0x4d12, 0xcf50, 0x2112, 0x4d12, 0xcf52,
+	0x2866, 0xf09a, 0x8112, 0xc418, 0x2112, 0x4d32, 0xcf54, 0x2112,
+	0x4d32, 0xcf58, 0x286c, 0xe016, 0x4466, 0x443e, 0xe40a, 0x11b3,
+	0xca28, 0xf7f8, 0xa202, 0xcf62, 0xcf64, 0xe0c0, 0x0046, 0xe005,
+	0x00a8, 0xae11, 0xe042, 0xca29, 0xf7f9, 0xe180, 0xce20, 0xd111,
+	0x05d0, 0xd112, 0x0008, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe181,
+	0xe0c0, 0x0046, 0xe005, 0x00a8, 0xae11, 0xe042, 0xca29, 0xf7f9,
+	0xe180, 0xce20, 0xd111, 0x0048, 0xd112, 0x0002, 0xd113, 0x001b,
+	0xca28, 0xf7f8, 0xe181, 0xd1a0, 0x0001, 0xcb40, 0xf7f8, 0x286c,
+	0xe016, 0x4466, 0x443e, 0xe42a, 0x2853, 0xcf64, 0x2054, 0x4c55,
+	0xcf62, 0xe42e, 0xe41e, 0x1023, 0xa200, 0x3c54, 0x3c55, 0xa202,
+	0x3c78, 0xe41e, 0x11d7, 0xe41e, 0x1271, 0xf7c8, 0xa200, 0x3c78,
+	0xe41e, 0x11d7, 0xe190, 0xe0c1, 0x014b, 0xf7e9, 0xe42e, 0x2854,
+	0x4c55, 0xe01a, 0x3c77, 0x2871, 0xf11a, 0x2854, 0xe41a, 0x124e,
+	0x2854, 0xaf02, 0xe000, 0x0460, 0xe09e, 0x2907, 0x2a54, 0xa803,
+	0xf029, 0xaf10, 0xe008, 0x001f, 0x3c79, 0x2879, 0xae02, 0x4c77,
+	0xae02, 0x4c78, 0xae0e, 0x4c54, 0xae0e, 0x4c55, 0xe0c1, 0x014b,
+	0xf7e9, 0xe0c2, 0x014d, 0xa202, 0xe0c2, 0x014a, 0xe42e, 0xe0c0,
+	0x0060, 0xe049, 0xa861, 0xe42b, 0xe049, 0xa81e, 0x3c76, 0xaf09,
+	0x3275, 0xaf03, 0x3271, 0x28a4, 0xe0c2, 0x0143, 0xa200, 0xe0c2,
+	0x017f, 0xe0c2, 0x0149, 0xa200, 0xe41e, 0x036c, 0xe0c2, 0x017f,
+	0x2850, 0xa102, 0xae20, 0x4c51, 0xa102, 0xe0c2, 0x0142, 0xe41e,
+	0x0371, 0xae20, 0x2a71, 0xae09, 0xe056, 0x2a75, 0xf02b, 0x4c76,
+	0xe0c2, 0x014e, 0xe0c0, 0x0061, 0xa87e, 0xe0c2, 0x0144, 0xa203,
+	0xe42e, 0x2854, 0xaf02, 0xe000, 0x0420, 0xe09e, 0x2907, 0x2a54,
+	0xa803, 0x4c5d, 0xf039, 0x285d, 0xae10, 0x3d07, 0x2854, 0xa002,
+	0x1850, 0xe41a, 0x1244, 0xe42e, 0xe180, 0xca28, 0xf7f8, 0x2873,
+	0x3c07, 0xa204, 0x3c06, 0xd111, 0x0420, 0xf0ae, 0xe180, 0xca28,
+	0xf7f8, 0x2872, 0x3c07, 0xa206, 0x3c06, 0xd111, 0x0460, 0xe0c0,
+	0x0041, 0xe005, 0x0037, 0xae11, 0xe042, 0x2a07, 0xae1d, 0xe042,
+	0x2a55, 0xae0f, 0xe042, 0xce20, 0x2850, 0xa002, 0xaf02, 0xa006,
+	0xa2f9, 0xe052, 0xce24, 0x8806, 0x0113, 0xca28, 0xf7f8, 0xe181,
+	0xe42e, 0x2854, 0xa002, 0x3c54, 0x1850, 0xe428, 0x3c54, 0x2855,
+	0xa002, 0x3c55, 0x1851, 0xe42e, 0x8112, 0xa204, 0x5818, 0xa102,
+	0x3ce7, 0x2902, 0x44e7, 0x3ce8, 0x2902, 0xaf02, 0x5c18, 0x5818,
+	0xae04, 0x4ce8, 0x3d0a, 0xe42e, 0xe161, 0x04a0, 0xa2fe, 0xc703,
+	0x3d11, 0xe42e, 0x3c06, 0xe004, 0x04a0, 0xe092, 0xa200, 0x2b11,
+	0xf075, 0xa002, 0xe049, 0xa109, 0xf7b9, 0xa200, 0xe42e, 0xe049,
+	0xe001, 0x04a0, 0xe093, 0x2a06, 0x3f11, 0xe42e, 0x3c06, 0xe004,
+	0x04a0, 0xe092, 0xa200, 0x2b11, 0x1a06, 0xf06b, 0xa002, 0xe049,
+	0xa109, 0xf7a9, 0xa200, 0xe42e, 0xe424, 0xe000, 0x04a0, 0xe092,
+	0xa2fe, 0x3d01, 0xe42e, 0xe167, 0x01a0, 0x2317, 0x4f17, 0xe0c3,
+	0x0152, 0x2b17, 0xe009, 0x00ff, 0xae21, 0x4f07, 0xe0c3, 0x0153,
+	0xe0c1, 0x0101, 0xe0c3, 0x015d, 0x2824, 0xa104, 0xe005, 0x001b,
+	0xf038, 0xe005, 0x001f, 0x3e00, 0x28a0, 0xa53e, 0xa400, 0x2aa1,
+	0xa53f, 0xa401, 0xae11, 0xe055, 0xae21, 0xe167, 0x01a2, 0x2907,
+	0xaf10, 0x4400, 0xe055, 0xe0c3, 0x015c, 0xa202, 0xe0c2, 0x0150,
+	0xe0c0, 0x0150, 0xf7ea, 0xa200, 0xe0c2, 0x0150, 0xe0c0, 0x0151,
+	0xf7e8, 0xe42e, 0xe0c0, 0x0045, 0xaf08, 0x3091, 0xe0c0, 0x0060,
+	0x3480, 0x3c81, 0x3486, 0x3c87, 0xe0c0, 0x0061, 0xae14, 0x3482,
+	0x3c83, 0x0480, 0x0c81, 0x3484, 0x3c85, 0x288c, 0xf13a, 0xe0c0,
+	0x0048, 0x3492, 0x3c93, 0x2492, 0x4c93, 0xe0c1, 0x0049, 0x3688,
+	0x3e89, 0x1488, 0x1c89, 0xe0c1, 0x0045, 0xaf05, 0xa803, 0xb611,
+	0x3e8c, 0xe0c0, 0x0048, 0xe008, 0x01ff, 0x3c8a, 0xe0c0, 0x0048,
+	0x3486, 0xe008, 0xfe00, 0x3c87, 0xa200, 0xcc92, 0xcc8e, 0xe180,
+	0xe41e, 0x13cc, 0xd071, 0x202a, 0xe181, 0xa200, 0x3c8e, 0xa200,
+	0x3498, 0x3c97, 0xcc72, 0xe41e, 0x1377, 0x2c8a, 0xa102, 0xf034,
+	0xba4f, 0xf7de, 0xc872, 0xe41e, 0x1496, 0xa202, 0x3c8e, 0xa202,
+	0xb61a, 0xe16a, 0xe42e, 0xcb40, 0xf7f8, 0xc896, 0xf11a, 0x288c,
+	0xf0a8, 0xe41e, 0x1390, 0x288c, 0xf08a, 0xa200, 0x2a9b, 0xe003,
+	0x01fc, 0xb62e, 0xe418, 0x138d, 0xa200, 0x3c9a, 0xf05e, 0xd04b,
+	0x0001, 0xa200, 0x3c9a, 0xe41e, 0x14a3, 0x2899, 0xcc6e, 0xd04c,
+	0x0000, 0xa214, 0xa102, 0xf7f0, 0xe470, 0x288c, 0xe428, 0xa202,
+	0x3c9a, 0xe41e, 0x1390, 0x288c, 0xcc96, 0xe42e, 0xc896, 0xe428,
+	0xd04b, 0x0001, 0x2899, 0xcc6e, 0xd04c, 0x0000, 0xe42e, 0xa200,
+	0x3c8d, 0x3c99, 0xe41e, 0x1390, 0xa200, 0x3c9a, 0x288c, 0xf07a,
+	0x289b, 0xa118, 0xf042, 0xe41e, 0x138d, 0xf79e, 0xd04b, 0x0001,
+	0x2899, 0xcc6e, 0xe190, 0xe128, 0xe42e, 0xe41e, 0x144a, 0xf04e,
+	0x288c, 0xe41a, 0x13a2, 0x289b, 0xaf12, 0x088d, 0xa802, 0x3c8d,
+	0x289b, 0xe008, 0x01ff, 0x3c9b, 0x288d, 0xae12, 0x089b, 0xaf04,
+	0x3c99, 0xe42e, 0xd027, 0x0000, 0xe41e, 0x13f3, 0xd027, 0x0001,
+	0x289b, 0xe42a, 0xca28, 0xf7f8, 0x2486, 0x4c87, 0xce20, 0x288d,
+	0xae0e, 0xce22, 0xd112, 0x0080, 0xe0c0, 0x0043, 0xa806, 0xae02,
+	0xa022, 0xce26, 0xca28, 0xf7f8, 0x2486, 0x4c87, 0xe000, 0x0200,
+	0x3486, 0x3c87, 0x1484, 0x1c85, 0xf054, 0x2480, 0x4c81, 0x3486,
+	0x3c87, 0xe41e, 0x1470, 0xe42e, 0xd030, 0x0000, 0xd031, 0x0000,
+	0xd032, 0x0000, 0xd034, 0x0000, 0xd033, 0x0000, 0xd035, 0x0000,
+	0xd036, 0x00ff, 0xd037, 0x0000, 0xd038, 0x0000, 0xd039, 0x0000,
+	0xd04b, 0x0001, 0xd04c, 0x0000, 0xd149, 0x0000, 0xe42e, 0xe0c1,
+	0x0059, 0xa103, 0xa200, 0xb636, 0xe000, 0x001c, 0xe0c1, 0x0045,
+	0xe052, 0xe01a, 0xe42e, 0xe0c0, 0x0043, 0xa808, 0xf318, 0xa200,
+	0x3c8b, 0xe004, 0x0200, 0x3c9b, 0xe41e, 0x13e7, 0x3c8c, 0x2486,
+	0x4c87, 0xe0c1, 0x0049, 0x3692, 0x3e93, 0x2692, 0x4e93, 0xe045,
+	0xf033, 0x0682, 0x0e83, 0xe003, 0x0200, 0x288c, 0xb606, 0x3c8c,
+	0xf173, 0xe001, 0x0200, 0x3e9b, 0x288c, 0xf128, 0x288b, 0xf658,
+	0xe0c0, 0x005c, 0xe008, 0x4000, 0xf60a, 0xe0c0, 0x005d, 0xe00a,
+	0x4000, 0xe0c2, 0x005d, 0xa202, 0xce00, 0x3c8b, 0xf56e, 0x289b,
+	0x2a8c, 0xf039, 0xe004, 0x0200, 0x3c9b, 0xe42e, 0xc868, 0xa80e,
+	0x3c00, 0x7400, 0xe42e, 0x288c, 0xe42a, 0xe41e, 0x1470, 0xe0c0,
+	0x0049, 0x3492, 0x3c93, 0x2492, 0x4c93, 0xe0c1, 0x0048, 0x3692,
+	0x3e93, 0x2692, 0x4e93, 0xe045, 0xa200, 0xb626, 0xe003, 0x0200,
+	0xb606, 0xe42e, 0xe004, 0x01b1, 0x2a30, 0xf03b, 0xe004, 0x8000,
+	0x3c7b, 0x288d, 0xae12, 0x089b, 0xaf04, 0xcc78, 0xcc76, 0x289b,
+	0xa806, 0x3c7d, 0xf0da, 0xae06, 0x3c7c, 0xa240, 0x187c, 0x3c7d,
+	0xc87a, 0x5c7d, 0x587d, 0x2e7b, 0x5e7c, 0xe042, 0xcc7a, 0x2c7b,
+	0x587d, 0xcc7a, 0x289b, 0xa008, 0x3c9b, 0xe42e, 0xe41e, 0x142e,
+	0xc872, 0x349c, 0x3c9d, 0xe41e, 0x1493, 0xe049, 0x249c, 0x4c9d,
+	0xaf06, 0xe046, 0xb608, 0x2a8e, 0xb616, 0xe0c1, 0x0048, 0x3692,
+	0x3e93, 0x2692, 0x4e93, 0xe042, 0xe049, 0x1684, 0x1e85, 0xf035,
+	0x1482, 0x1c83, 0xe0c2, 0x0048, 0xe0c2, 0x0052, 0x249c, 0x4c9d,
+	0xe41e, 0x1496, 0xe42e, 0x249e, 0x4c9f, 0xe42e, 0xaf06, 0x349e,
+	0x3c9f, 0xe42e, 0xe41e, 0x1470, 0xc001, 0xe0c0, 0x0048, 0x3417,
+	0x3c18, 0xc000, 0xe42e, 0xe0c0, 0x0045, 0xaf04, 0xa80e, 0xa104,
+	0xe428, 0xe41e, 0x14ae, 0xe418, 0x01db, 0xe42e, 0x288c, 0xe42a,
+	0xe41e, 0x1470, 0xe0c0, 0x0048, 0x3492, 0x3c93, 0x2492, 0x4c93,
+	0xe0c1, 0x0049, 0x3692, 0x3e93, 0x2692, 0x4e93, 0xe045, 0xf033,
+	0x0682, 0x0e83, 0xa109, 0xa200, 0xb62e, 0xe42e, 0xd1b3, 0x0001,
+	0xa223, 0x2824, 0xf0ca, 0x2a0c, 0xa021, 0xa102, 0xf08a, 0x283f,
+	0xf068, 0x280c, 0x2a0d, 0xe061, 0xa021, 0xa425, 0x3e60, 0x2824,
+	0xf068, 0xe161, 0x0300, 0xa200, 0xc711, 0x3d11, 0x2827, 0x3c42,
+	0xa200, 0x3c70, 0x3c43, 0x3c44, 0xcf64, 0xcf62, 0x2866, 0xf09a,
+	0x2851, 0xa102, 0xf068, 0xa202, 0xcf62, 0xcb60, 0xa020, 0xcf60,
+	0x2844, 0x4c70, 0xf14a, 0x2836, 0xf088, 0xe41e, 0x164f, 0xf0da,
+	0xe41e, 0x0895, 0x3c43, 0xf0be, 0xe41e, 0x1677, 0xf06a, 0xa200,
+	0xe41e, 0x08e7, 0x3c43, 0xf03e, 0x2852, 0x3c43, 0x2844, 0x1843,
+	0xf680, 0xf07a, 0xe41e, 0x15dd, 0x2843, 0x3c44, 0x1852, 0xf19a,
+	0xa202, 0x3c70, 0x2824, 0xa104, 0xe01a, 0x4422, 0xf068, 0xe41e,
+	0x157f, 0xd1b3, 0x0006, 0xf06e, 0xe41e, 0x166c, 0xd1b3, 0x0002,
+	0xe428, 0x286b, 0xa002, 0x3c6b, 0x2844, 0x1852, 0xe404, 0x14f0,
+	0xa202, 0xe42e, 0xd1b3, 0x0001, 0x2827, 0x3c42, 0xa200, 0x3c43,
+	0x3c44, 0x3c33, 0xcf64, 0xcf62, 0xa2fe, 0x3c40, 0x2844, 0x1843,
+	0xf072, 0xe41e, 0x15dd, 0x2843, 0x3c44, 0x1852, 0xf35a, 0xe41e,
+	0x157f, 0x2843, 0x0832, 0x3c43, 0x1852, 0xf034, 0x2852, 0x3c43,
+	0x2833, 0xa002, 0x3c33, 0x2844, 0x1852, 0xf26a, 0x282e, 0xf678,
+	0x2844, 0x1843, 0xf094, 0xba20, 0xa102, 0xf618, 0xd1b3, 0x0002,
+	0x286b, 0xa002, 0x3c6b, 0xe41e, 0x1659, 0x3c41, 0xf12a, 0xba60,
+	0xba48, 0x3c41, 0x2840, 0xba43, 0xf038, 0xe046, 0xf758, 0xba48,
+	0x3c27, 0x2841, 0x3c33, 0x8433, 0x8232, 0xe018, 0x3c43, 0xf47e,
+	0x2852, 0x3c43, 0xf44e, 0xa22c, 0xe41e, 0x1607, 0xa17e, 0xf048,
+	0xe41e, 0x142e, 0xba6a, 0xe41e, 0x142e, 0xa202, 0xe42e, 0x2827,
+	0x3c61, 0x2832, 0x0843, 0x3c45, 0x2843, 0x3c53, 0xc70f, 0x7c50,
+	0x3454, 0x3c55, 0x2853, 0x1852, 0xe40a, 0x15d8, 0xe41e, 0x1741,
+	0xe40a, 0x15db, 0x285d, 0x3c61, 0x2853, 0xa002, 0x3c53, 0xcf64,
+	0xe41e, 0x1691, 0xe01a, 0x3c78, 0x2054, 0x4c55, 0xcf62, 0x2830,
+	0xe40a, 0x15bd, 0x2836, 0xe408, 0x15b6, 0x2853, 0x1845, 0xe408,
+	0x158a, 0x2861, 0x3c27, 0xba20, 0xa102, 0xf2ba, 0xa222, 0xe41e,
+	0x1607, 0xa102, 0xf268, 0xe41e, 0x142e, 0xf23e, 0xe41e, 0x1643,
+	0xe40a, 0x158a, 0xe41e, 0x142e, 0xf1ce, 0xd190, 0x0008, 0xcb20,
+	0xf7f8, 0xe41e, 0x162a, 0xf05a, 0xba40, 0xe41e, 0x142e, 0xf11e,
+	0xe41e, 0x1612, 0xe40a, 0x158a, 0x2855, 0x1851, 0xf06a, 0xe41e,
+	0x1836, 0xa802, 0xe408, 0x158a, 0xba40, 0xe41e, 0x142e, 0xf01e,
+	0x2853, 0x3c44, 0xe42e, 0xe16a, 0xf7ce, 0x244a, 0x4c4b, 0xe016,
+	0x3c58, 0xe016, 0x3c59, 0x2842, 0x3c5d, 0xa200, 0x3c5b, 0x3c5f,
+	0x3c5c, 0x2844, 0x3c53, 0xc70f, 0x7c50, 0x3454, 0x3c55, 0x2853,
+	0x1843, 0xf112, 0xe41e, 0x1149, 0xe41e, 0x10bb, 0x2853, 0xa002,
+	0x3c53, 0xcf64, 0xe41e, 0x1691, 0xe01a, 0x3c78, 0x2054, 0x4c55,
+	0xcf62, 0xf6ee, 0x2843, 0x1844, 0x0846, 0x3c46, 0xe42e, 0x3c48,
+	0xc869, 0xa80f, 0xe042, 0x3c49, 0x7849, 0xa203, 0x5a48, 0xa103,
+	0xe052, 0xe42e, 0xc868, 0xa80e, 0xa102, 0xb6e8, 0xa002, 0x3c48,
+	0x7848, 0xa203, 0x5a48, 0xaf03, 0xa103, 0xe046, 0xe016, 0xe42a,
+	0xa22e, 0x0848, 0x3c48, 0x7848, 0xa203, 0xae2f, 0xa103, 0xe052,
+	0xe016, 0xe42e, 0xc868, 0xa80e, 0xa102, 0xb6e8, 0xa002, 0x3c48,
+	0x7848, 0xa203, 0x5a48, 0xaf03, 0xa103, 0xe046, 0xe016, 0xe42a,
+	0x2860, 0x0848, 0x3c48, 0x7848, 0xa203, 0x5a60, 0xa103, 0xe052,
+	0xa102, 0xe016, 0xe42e, 0xc869, 0xa80f, 0x3e48, 0x7848, 0xe016,
+	0xa023, 0x3e48, 0xe42a, 0x7848, 0xa102, 0xe016, 0xe42e, 0xe41e,
+	0x142e, 0x7860, 0xa102, 0xe016, 0xe428, 0xba2c, 0xe42a, 0xba4e,
+	0xf79e, 0xba20, 0xa102, 0xf03a, 0xba40, 0xf7ce, 0xba2a, 0xa83e,
+	0x3c41, 0xe42a, 0xa13e, 0xe42a, 0x2841, 0x1833, 0xf764, 0x2841,
+	0x1832, 0xf732, 0x2841, 0xe42e, 0x2824, 0xa104, 0xf058, 0xe41e,
+	0x15dd, 0xa202, 0xe42e, 0xe41e, 0x1863, 0xa200, 0xe42e, 0xe41e,
+	0x142e, 0xba20, 0xa102, 0xf03a, 0xba4e, 0xf7ce, 0xba2a, 0xa83e,
+	0xe42a, 0xa13e, 0xe42a, 0xa03e, 0xaf08, 0xf77a, 0xe42e, 0xa200,
+	0x3c58, 0x3c5f, 0x2824, 0xe418, 0x1149, 0xa200, 0xe41e, 0x10bb,
+	0xe42e, 0xd188, 0x0001, 0x2854, 0xa002, 0x3c54, 0x1850, 0xe428,
+	0xd1b3, 0x0004, 0x3c54, 0x2855, 0xa002, 0x3c55, 0x1851, 0xe42e,
+	0xba42, 0xe000, 0x0228, 0xe09e, 0x2907, 0x0861, 0xa402, 0xa53e,
+	0x3c5d, 0xe42e, 0x2837, 0xf75a, 0xba40, 0xf0da, 0xba40, 0xae0a,
+	0x0861, 0xe000, 0x022c, 0xe09e, 0x2907, 0x0861, 0xa402, 0xa53e,
+	0x3c5d, 0xe42e, 0xba48, 0x3c5d, 0xe42e, 0xe161, 0x0300, 0x280b,
+	0xf03a, 0xa203, 0xf03e, 0x2a5b, 0xb673, 0x3f11, 0xcc45, 0xe184,
+	0x16d5, 0xe41e, 0x16d7, 0xe42d, 0x3d11, 0xe41e, 0x16d7, 0xe42d,
+	0x3d11, 0x280b, 0xf03a, 0x8111, 0x8111, 0xe190, 0xe42e, 0xb80c,
+	0xa140, 0xe42d, 0xe42a, 0x5829, 0x7629, 0x1a2a, 0xf030, 0xe046,
+	0xe046, 0xe042, 0xe42e, 0x286c, 0xa802, 0xe40a, 0x1701, 0x280c,
+	0x3c28, 0x2811, 0x3c29, 0x2812, 0x3c2a, 0xe161, 0x0300, 0x2a0b,
+	0x3f11, 0xcc45, 0xe184, 0x1700, 0xe41e, 0x16d7, 0xe42d, 0x3d11,
+	0xe41e, 0x16d7, 0xe42d, 0x3d11, 0x280b, 0xf03a, 0x8111, 0x8111,
+	0xe190, 0x286c, 0xf20a, 0xa106, 0xf1ea, 0x280d, 0x3c28, 0x2813,
+	0x3c29, 0x2814, 0x3c2a, 0xe161, 0x0300, 0x2a0b, 0x3f01, 0xe161,
+	0x0309, 0x3f11, 0xcc45, 0xe184, 0x1721, 0xe41e, 0x16d7, 0xe42d,
+	0x3d11, 0xe41e, 0x16d7, 0xe42d, 0x3d11, 0x280b, 0xf03a, 0x8111,
+	0x8111, 0xe190, 0xe42e, 0x28b0, 0x18af, 0xf02a, 0x3c69, 0x284e,
+	0x18af, 0x3c6a, 0xe42e, 0xe161, 0x0300, 0xe162, 0x0309, 0xa206,
+	0x3d11, 0x3d12, 0xe41e, 0x173e, 0x3d11, 0x3d12, 0xe42d, 0xe41e,
+	0x173e, 0x3d11, 0x3d12, 0xe41e, 0x1723, 0xe42e, 0xb80c, 0xa140,
+	0xe42e, 0x2861, 0xcf36, 0x2830, 0xe408, 0x17c5, 0x2866, 0xf0da,
+	0xe41e, 0x1836, 0xcf38, 0xa802, 0x2ac1, 0xe017, 0xe052, 0xf05a,
+	0xe004, 0x1000, 0xcf02, 0xf0ee, 0xd190, 0x0002, 0xe180, 0xe180,
+	0x289a, 0xe41a, 0x1365, 0xe181, 0xcb20, 0xf7f8, 0xcb22, 0xe408,
+	0x17c0, 0xcb02, 0x30b8, 0xaf02, 0x30b7, 0xaf02, 0x30b6, 0xaf02,
+	0x30b5, 0xaf02, 0x30c5, 0xaf02, 0x300b, 0xaf02, 0x30ab, 0xaf02,
+	0x305c, 0xaf06, 0x305b, 0xaf02, 0x3058, 0xaf02, 0x3059, 0xaf02,
+	0x3056, 0xaf02, 0xe049, 0xa807, 0x3e6c, 0xaf04, 0xe049, 0xa83f,
+	0x3e5d, 0xaf0a, 0x3c5e, 0x2859, 0xf368, 0x2856, 0x2a56, 0xe418,
+	0x1723, 0xf1d9, 0x2866, 0xf0aa, 0x286c, 0xe41a, 0x172b, 0x286c,
+	0xe418, 0x16e3, 0xe40d, 0x17c0, 0xf07e, 0x2858, 0x4cc5, 0xe41a,
+	0x16bd, 0xe40d, 0x17c0, 0x2858, 0x2a61, 0x1a26, 0xb606, 0x2a66,
+	0xb612, 0x3c5f, 0xcf26, 0xd190, 0x0001, 0x2a24, 0xe419, 0x1149,
+	0xe180, 0xe180, 0x289a, 0xe41a, 0x1365, 0xe181, 0xcb20, 0xf7f8,
+	0xa202, 0x3cbb, 0xcb22, 0xe408, 0x17c0, 0xa200, 0xe41e, 0x10bb,
+	0xa202, 0xe42e, 0xa208, 0x3c6c, 0xe41e, 0x1687, 0xa202, 0xe42e,
+	0xd191, 0x0000, 0xe16a, 0xa200, 0xe42e, 0xd190, 0x0002, 0xcb20,
+	0xf7f8, 0xcb22, 0xe408, 0x180b, 0xcb02, 0xaf0e, 0xe049, 0xa807,
+	0x3e5c, 0xaf06, 0x305b, 0xaf02, 0x3058, 0xaf02, 0x3059, 0xaf08,
+	0xe049, 0xa83e, 0x3c5d, 0xaf0b, 0x3e5e, 0x2859, 0xf298, 0x2858,
+	0xf078, 0x2839, 0x443a, 0xf02a, 0xf03e, 0xe41e, 0x16bd, 0xe40d,
+	0x180b, 0x2834, 0xe016, 0x4458, 0x3c5f, 0x2858, 0x4434, 0xae02,
+	0x4c5f, 0xcf26, 0xd190, 0x0001, 0x2824, 0xe418, 0x1149, 0xe180,
+	0xe180, 0x289a, 0xe41a, 0x1365, 0xe181, 0xcb21, 0xf7f9, 0xcb22,
+	0xe408, 0x180b, 0xa200, 0xe41e, 0x10bb, 0xa202, 0xe42e, 0xe41e,
+	0x1687, 0xa202, 0xe42e, 0xd191, 0x0000, 0xe16a, 0xa200, 0xe42e,
+	0x2854, 0xaf04, 0xe000, 0x0400, 0xe09e, 0x2a54, 0xa807, 0xa107,
+	0xe013, 0xae05, 0x3e00, 0xa21f, 0x5a00, 0xa2fe, 0xe059, 0x2907,
+	0xe052, 0x2a59, 0xf05b, 0x5a00, 0xe056, 0x3d07, 0xf0ae, 0x2ab5,
+	0xae03, 0x4eb6, 0xae03, 0x4e0b, 0xae03, 0x5a00, 0xe056, 0x3d07,
+	0x2854, 0xa002, 0x1850, 0xe41a, 0x1848, 0xe42e, 0x2854, 0xe41a,
+	0x184a, 0x2854, 0xaf04, 0xe000, 0x0400, 0xe092, 0x2a54, 0xa807,
+	0xa107, 0xe013, 0xae05, 0x3e00, 0x2901, 0x5c00, 0xa81e, 0xe42e,
+	0xa204, 0xf02e, 0xa206, 0x3c06, 0xe0c0, 0x0041, 0xe005, 0x0026,
+	0xae11, 0xe042, 0x2a55, 0xae0d, 0xe042, 0xca29, 0xf7f9, 0xe180,
+	0xce20, 0xd111, 0x0400, 0xd112, 0x0020, 0x8806, 0x0113, 0xca28,
+	0xf7f8, 0xe181, 0xe42e, 0x2827, 0x3c61, 0x2832, 0x0843, 0x3c45,
+	0xe160, 0x0006, 0x2824, 0xf0a8, 0xe41e, 0x18a9, 0xe40a, 0x18a7,
+	0xe41e, 0x1910, 0xe40a, 0x18a7, 0xf09e, 0xe41e, 0x1947, 0xe40a,
+	0x18a7, 0xe41e, 0x19b1, 0xe40a, 0x18a7, 0xa200, 0x3c4f, 0x2843,
+	0x3c53, 0xc70f, 0x7c50, 0x3454, 0x3c55, 0x2827, 0x3c61, 0x3c5d,
+	0x2853, 0x1852, 0xe40a, 0x18a4, 0xe41e, 0x1a33, 0xe40a, 0x18a7,
+	0x285d, 0x3c61, 0x2853, 0xa002, 0x3c53, 0xcf64, 0xe41e, 0x1691,
+	0xe01a, 0x3c78, 0x2054, 0x4c55, 0xcf62, 0x2853, 0x1845, 0xe408,
+	0x1888, 0xba40, 0xe41e, 0x142e, 0x2853, 0x3c44, 0xe42e, 0xe16a,
+	0xf7ce, 0xd1b3, 0x0020, 0xa200, 0x3c67, 0xe161, 0x0800, 0xe004,
+	0x0800, 0x3c68, 0x2843, 0x3c53, 0x2853, 0x1852, 0xe402, 0x1905,
+	0x2861, 0xcf36, 0xd199, 0x0000, 0xa203, 0x2861, 0x1826, 0xb605,
+	0x3e5f, 0xa909, 0xcf27, 0xd190, 0x0002, 0xcb20, 0xf7f8, 0xcb22,
+	0xe408, 0x190a, 0xcb02, 0xaf04, 0x30b6, 0xaf02, 0x30b5, 0xaf04,
+	0x300b, 0xa200, 0x3c59, 0xcb02, 0xaf20, 0xe049, 0xa8fe, 0xae02,
+	0x4c5f, 0xae06, 0xa908, 0x3d11, 0xa83f, 0x3e5d, 0x2a5f, 0xf0bb,
+	0xcb2c, 0x3511, 0x3d11, 0xcb2e, 0x3511, 0x3d11, 0xcb30, 0x3511,
+	0x3d11, 0xf02e, 0x8131, 0xe082, 0xe002, 0x08f0, 0xf084, 0xe41e,
+	0x1a9f, 0x2867, 0xa002, 0x3c67, 0xe161, 0x0800, 0x285f, 0xf058,
+	0xd190, 0x0008, 0xcb20, 0xf7f8, 0x285d, 0x3c61, 0x2853, 0xa002,
+	0x3c53, 0xcb32, 0xa808, 0xe40a, 0x18b4, 0xba64, 0x2a53, 0x3e45,
+	0xa202, 0xe42e, 0xd191, 0x0000, 0x2843, 0x3c53, 0xa200, 0xe42e,
+	0x1a43, 0xa103, 0xcc45, 0x2867, 0xf07a, 0xe41e, 0x1a9f, 0xa200,
+	0x3c67, 0xe41e, 0x1aa1, 0xe161, 0x0800, 0xe184, 0x1936, 0xba40,
+	0xb809, 0xf22d, 0xae08, 0xe056, 0xae16, 0x2b01, 0xe056, 0x3d11,
+	0x8131, 0xe082, 0xe002, 0x08f0, 0xf0a4, 0xe41e, 0x1a9f, 0x2867,
+	0xa002, 0x3c67, 0xe41e, 0x1aa1, 0xe161, 0x0800, 0xe190, 0x2867,
+	0xf09a, 0xe41e, 0x1a9f, 0xa200, 0x3c67, 0xe41e, 0x1aa1, 0xa202,
+	0x3c67, 0xa202, 0xe42e, 0x2843, 0x3c53, 0xa200, 0xe42e, 0xd1b3,
+	0x0020, 0xa200, 0x3c67, 0xe161, 0x0800, 0x2843, 0xe005, 0x0800,
+	0x3c53, 0x3e68, 0x2853, 0x1852, 0xe402, 0x19a8, 0xba40, 0xe40a,
+	0x195c, 0x3d11, 0xe40e, 0x1987, 0xb802, 0xa10e, 0xe40d, 0x19ad,
+	0xf76a, 0xa00e, 0x3058, 0xaf02, 0x305a, 0xaf02, 0x305b, 0xaf02,
+	0x3c01, 0x285a, 0xae04, 0x4c01, 0xae0e, 0x4c58, 0xae02, 0x4c5b,
+	0xae02, 0x3d11, 0x2858, 0xf118, 0x285b, 0xb670, 0xcc44, 0xe184,
+	0x1982, 0xe41e, 0x16d7, 0xe40d, 0x19ad, 0x3d11, 0xe41e, 0x16d7,
+	0xe40d, 0x19ad, 0x3d11, 0xf04e, 0x2858, 0xf02a, 0x8131, 0xe082,
+	0xe002, 0x08f0, 0xf084, 0xe41e, 0x1a9f, 0x2867, 0xa002, 0x3c67,
+	0xe161, 0x0800, 0x2853, 0xa002, 0x3c53, 0xd199, 0x0002, 0xd190,
+	0x0008, 0xcb20, 0xf7f8, 0xcb32, 0xa808, 0xe40a, 0x1952, 0xcb02,
+	0xaf04, 0x30b6, 0xaf02, 0x30b5, 0xaf04, 0x300b, 0xaf0e, 0x3059,
+	0xba60, 0x2a53, 0x3e45, 0xa202, 0xe42e, 0x2843, 0x3c53, 0xa200,
+	0xe42e, 0x1a43, 0xa103, 0xcc45, 0x2867, 0xf07a, 0xe41e, 0x1a9f,
+	0xa200, 0x3c67, 0xe41e, 0x1aa1, 0xe161, 0x0800, 0xe184, 0x1a20,
+	0x2901, 0x3c00, 0xe049, 0xa803, 0xe40b, 0x19cb, 0x2861, 0x3c5d,
+	0x3f11, 0xe40e, 0x1a12, 0xaf02, 0x305b, 0xaf02, 0x3058, 0xaf12,
+	0x305a, 0x2858, 0xae04, 0x4c5a, 0xae12, 0xcf02, 0x2861, 0xcf36,
+	0x2858, 0x2a61, 0x1a26, 0xb606, 0x3c5f, 0xa908, 0xcf26, 0xd190,
+	0x0002, 0x2800, 0xe008, 0x07ff, 0x3c00, 0xcb20, 0xf7f8, 0xcb22,
+	0xe408, 0x1a2d, 0xcb02, 0xaf0e, 0x305c, 0xaf12, 0xa23f, 0xe051,
+	0x3e5d, 0xaf0e, 0x3c5e, 0x285c, 0xae08, 0x4c5e, 0xae0e, 0x4c5d,
+	0xae02, 0x4c5f, 0xae06, 0x4c00, 0x3d11, 0x2858, 0xf0fa, 0x285f,
+	0xf0ba, 0xcb2c, 0x3511, 0x3d11, 0xcb2e, 0x3511, 0x3d11, 0xcb30,
+	0x3511, 0x3d11, 0xf08e, 0x8131, 0xf06e, 0x8111, 0x8111, 0x285b,
+	0xf02a, 0x8131, 0xe082, 0xe002, 0x08f0, 0xf0a4, 0xe41e, 0x1a9f,
+	0x2867, 0xa002, 0x3c67, 0xe41e, 0x1aa1, 0xe161, 0x0800, 0x285d,
+	0x3c61, 0x2867, 0xf09a, 0xe41e, 0x1a9f, 0xa200, 0x3c67, 0xe41e,
+	0x1aa1, 0xa202, 0x3c67, 0xa202, 0xe42e, 0xd191, 0x0000, 0x2843,
+	0x3c53, 0xa200, 0xe42e, 0x2861, 0xcf36, 0x2868, 0xe092, 0x2911,
+	0x3059, 0x2a59, 0xe409, 0x1a92, 0xaf02, 0x305b, 0xaf02, 0x3058,
+	0xaf02, 0x305f, 0xaf02, 0xa23f, 0xe051, 0x3e5d, 0xaf0a, 0xa27f,
+	0xe051, 0x3e5e, 0xaf0c, 0x3c5c, 0x2858, 0xf0c8, 0xe162, 0x0301,
+	0xa20e, 0x2a5b, 0xb636, 0xcc44, 0xe184, 0x1a57, 0x2911, 0x3d12,
+	0xf0ee, 0x285f, 0xf0ba, 0x2111, 0x4d11, 0xcf2c, 0x2111, 0x4d11,
+	0xcf2e, 0x2111, 0x4d11, 0xcf30, 0xf02e, 0x8131, 0x285e, 0xae08,
+	0x4c59, 0xae02, 0x4c58, 0xae02, 0x4c5b, 0xae14, 0xcf02, 0x285f,
+	0xcf26, 0xd190, 0x0001, 0x2824, 0xe418, 0x1149, 0xe180, 0xe180,
+	0x289a, 0xe41a, 0x1365, 0xe181, 0xcb20, 0xf7f8, 0xcb22, 0xf188,
+	0xa200, 0xe41e, 0x10bb, 0xe082, 0x3c68, 0xe002, 0x08f0, 0xf094,
+	0xe41e, 0x1aa1, 0x2867, 0xa002, 0x3c67, 0xe004, 0x0800, 0x3c68,
+	0xa202, 0xe42e, 0xd181, 0x1000, 0xe41e, 0x1687, 0xf6de, 0xd191,
+	0x0000, 0xe16a, 0x2846, 0xa002, 0x3c46, 0xa200, 0xe42e, 0xa204,
+	0xf02e, 0xa206, 0x3c06, 0xe0c0, 0x0046, 0xe005, 0x00a9, 0x0a67,
+	0x0a67, 0xae11, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0800,
+	0xd112, 0x0100, 0x2806, 0xce26, 0xca28, 0xf7f8, 0xe42e, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0080, 0x0060, 0x0008, 0x0006,
+	0x00b0, 0x0090, 0x000b, 0x0009, 0x0160, 0x0120, 0x0016, 0x0012,
+	0x02c0, 0x0240, 0x0058, 0x0012, 0x0580, 0x0480, 0x0160, 0x0012,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0063, 0x000d, 0x000f, 0x0011, 0x0013, 0x0015, 0x0017, 0x0000,
+	0xffff, 0xfffe, 0x0001, 0x0002, 0x0000, 0x0002, 0xffff, 0xffff,
+	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xfffe,
+	0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe,
+	0xfffe, 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0xfffd,
+	0xfffd, 0xfffd, 0xfffd, 0xfffd, 0x0000, 0x0001, 0x0001, 0x0001,
+	0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0002,
+	0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002,
+	0x0002, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0002, 0x0001, 0xfffb, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe40e, 0x0020, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x0330, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x034a, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x003a, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058,
+	0xa200, 0xe0c2, 0x005a, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xa2fe,
+	0x3cee, 0x3cef, 0x3cec, 0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d,
+	0xce00, 0xf33e, 0xe41e, 0x0164, 0xe09e, 0xa202, 0xae3e, 0x9f07,
+	0xe0c0, 0x005c, 0xe0c1, 0x0059, 0x3eed, 0xa203, 0x5aed, 0xe052,
+	0xf08a, 0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00,
+	0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2, 0x0008, 0xf00e,
+	0x28ee, 0xe412, 0x013d, 0xe190, 0xe0c0, 0x005c, 0xe0c1, 0x0059,
+	0x3eed, 0xa203, 0x5aed, 0xe052, 0xf08a, 0xe0c1, 0x005d, 0xe055,
+	0xe0c3, 0x005d, 0xa202, 0xce00, 0xe0c0, 0x004a, 0xf08a, 0xe41e,
+	0x019c, 0xe408, 0x005c, 0xe40e, 0x0058, 0xe190, 0xe0c0, 0x043d,
+	0xa1ee, 0xf7d8, 0xe004, 0x0060, 0xe0c2, 0x0009, 0xa200, 0xe0c2,
+	0x0009, 0xe0c0, 0x000d, 0xf7e8, 0xe41e, 0x00b2, 0xe41e, 0x00e2,
+	0xe41e, 0x012c, 0xd071, 0x242a, 0xe181, 0xe41e, 0x0164, 0xe09e,
+	0xa202, 0x9f07, 0xe0c0, 0x0049, 0xe0c1, 0x005b, 0xa111, 0xf033,
+	0xe0c0, 0x0048, 0xe0c2, 0x0047, 0xe0c0, 0x0059, 0xae02, 0xe000,
+	0x0330, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a, 0xe008, 0xffff,
+	0x3cee, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11, 0xe056, 0x3cef,
+	0xe40e, 0x0058, 0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2,
+	0x0008, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xe0c0, 0x0059, 0xf7ea,
+	0xa11e, 0xf198, 0xa202, 0xe0c2, 0x0058, 0xe004, 0xca20, 0xae20,
+	0xe005, 0x210a, 0xe056, 0xe0c2, 0x0070, 0xe004, 0x0000, 0xae20,
+	0xe00a, 0x9cea, 0xe0c2, 0x0071, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+	0x0058, 0xf64e, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058, 0xd027,
+	0x0001, 0xe42e, 0xa200, 0xe0c1, 0x005b, 0xf21b, 0xa23c, 0xa103,
+	0xf37b, 0xa24c, 0xa103, 0xf34b, 0xa258, 0xa103, 0xf1db, 0xe004,
+	0x003a, 0xa103, 0xf2db, 0xe004, 0x003f, 0xa103, 0xf29b, 0xe004,
+	0x0045, 0xa103, 0xf25b, 0xa103, 0xf14b, 0xe004, 0x0063, 0xa103,
+	0xf1ab, 0xe004, 0x006a, 0xa107, 0xf1bb, 0xa200, 0xe0c1, 0x005e,
+	0xf17b, 0xa028, 0xf15e, 0xe0c1, 0x005e, 0xf12b, 0xa010, 0xf10e,
+	0xe004, 0x0049, 0xe0c1, 0x005e, 0xf0bb, 0xa010, 0xa103, 0xf08b,
+	0xa010, 0xf06e, 0xe0c1, 0x005e, 0xf03b, 0xe004, 0x0074, 0xae16,
+	0xe0c1, 0x0040, 0xe041, 0xce21, 0xd111, 0x0000, 0xd112, 0x2800,
+	0xd113, 0x000b, 0xe1e1, 0xe42e, 0xe41e, 0x023a, 0xe0c0, 0x0059,
+	0xa102, 0xe42a, 0xe0c0, 0x005b, 0xa810, 0xf058, 0xa206, 0xe41e,
+	0x0153, 0xe42e, 0xe004, 0x0350, 0xe67c, 0xe0c0, 0x005b, 0xa810,
+	0xf058, 0xa204, 0xe41e, 0x0153, 0xe42e, 0xe004, 0x0352, 0xe67c,
+	0xa200, 0xc401, 0xe188, 0x00eb, 0x3d11, 0xe161, 0x00f2, 0xe188,
+	0x0b0d, 0x3d11, 0xe42e, 0x3cec, 0xe0c0, 0x0041, 0xe005, 0x0000,
+	0xae11, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0c00, 0x88ec,
+	0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0059, 0xa106, 0xf048,
+	0xe004, 0x0076, 0xe42e, 0xe0c0, 0x0059, 0xa10c, 0xf038, 0xe004,
+	0x0071, 0xe004, 0x0070, 0xe42e, 0xe0c0, 0x006b, 0xe167, 0x01a0,
+	0x3d07, 0xe0c0, 0x0414, 0xe428, 0xe0c1, 0x0044, 0xa809, 0xae33,
+	0xe0c0, 0x006a, 0xe167, 0x01a0, 0x3517, 0x3d17, 0xe0c0, 0x006b,
+	0xe056, 0x3517, 0x3d07, 0xe42e, 0xe167, 0x01a0, 0x2907, 0xe0c2,
+	0x0151, 0xa204, 0xe0c2, 0x0150, 0xe0c0, 0x0150, 0xa804, 0xf7da,
+	0xa208, 0xe0c2, 0x0150, 0xe42e, 0xe0c0, 0x004a, 0xe42a, 0xe0c0,
+	0x005b, 0xa110, 0xf142, 0xe0c0, 0x0059, 0xa102, 0xe41a, 0x01be,
+	0xe0c0, 0x0059, 0xa106, 0xe41a, 0x01cb, 0xe0c0, 0x0047, 0xe0c2,
+	0x0048, 0xa200, 0xe0c2, 0x004a, 0xa202, 0xe42e, 0xe0c0, 0x0047,
+	0xe0c2, 0x0049, 0xa200, 0xe0c2, 0x004a, 0xe42e, 0xe0c0, 0x004a,
+	0xa802, 0xa23e, 0x3cf0, 0xa202, 0x58f0, 0xe0c2, 0x0078, 0xa220,
+	0xe0c2, 0x0070, 0xe42e, 0xe0c0, 0x004a, 0xa802, 0xa220, 0xe0c2,
+	0x0076, 0xa200, 0xe0c2, 0x0072, 0xa2fc, 0xe0c2, 0x0077, 0xa2fa,
+	0xe0c2, 0x0071, 0xe42e, 0xe0c0, 0x0045, 0xaf04, 0xa80e, 0xa104,
+	0xe428, 0xa202, 0xe0c2, 0x004a, 0xe0c0, 0x0111, 0xf7e8, 0xca28,
+	0xf7f8, 0xca48, 0xa802, 0xf7e8, 0xa208, 0xae14, 0xa102, 0xe190,
+	0xf7e2, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xe0c0, 0x041f, 0xf7e8,
+	0xa200, 0xe0c2, 0x041c, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xe004,
+	0x0078, 0xe0c2, 0x0009, 0xa200, 0xe0c2, 0x0009, 0xe0c0, 0x000d,
+	0xf7e8, 0xe42e, 0xc001, 0x3443, 0x3c42, 0xc000, 0xe42e, 0xc001,
+	0x2c43, 0x2e42, 0xc000, 0xe42a, 0x1c32, 0xf0b4, 0xe04a, 0xaf10,
+	0x1830, 0xf074, 0xe009, 0x00ff, 0x1a31, 0xf034, 0xa202, 0xe42e,
+	0xa2fe, 0xe42e, 0xe41e, 0x023a, 0xd160, 0x0620, 0xe004, 0x0019,
+	0xae18, 0xcec0, 0xe42e, 0xe41e, 0x024f, 0xe000, 0x0040, 0xce50,
+	0xa200, 0xd022, 0x00ff, 0xe184, 0x0236, 0xce52, 0xe190, 0xe41e,
+	0x0257, 0xe42e, 0xa204, 0xae22, 0xcc9e, 0xa200, 0xcc72, 0xcc8c,
+	0xcc8e, 0xe004, 0xa810, 0xae20, 0xe00a, 0x9322, 0xce4a, 0xd16f,
+	0x0003, 0xe190, 0xe190, 0xe190, 0xd16f, 0x0000, 0xe42e, 0xe004,
+	0x0030, 0xce50, 0xca50, 0xa802, 0xf7ea, 0xc000, 0xe42e, 0xe004,
+	0x0020, 0xce50, 0xe42e, 0xa200, 0xe0c2, 0x041c, 0xe42e, 0xe41e,
+	0x02bb, 0xe42a, 0xe0c0, 0x0061, 0xe008, 0x001f, 0xe00a, 0x0100,
+	0xe0c2, 0x041c, 0xe41e, 0x02f1, 0xe41e, 0x032b, 0xae12, 0xe0c2,
+	0x041e, 0xe41e, 0x031b, 0xe42e, 0xe41e, 0x02df, 0xe42a, 0xe0c0,
+	0x041f, 0xf7e8, 0xe0c0, 0x0210, 0xa804, 0xf118, 0xe0c0, 0x0215,
+	0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0216, 0xf0be, 0xe0c0, 0x0213,
+	0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0214, 0xf03e, 0xe0c0, 0x020b,
+	0xe00a, 0x0100, 0xe0c2, 0x041c, 0xe41e, 0x02f1, 0xe41e, 0x032b,
+	0xae12, 0xe0c1, 0x0210, 0xa803, 0xae15, 0xe056, 0xe0c1, 0x0204,
+	0xaf0b, 0xa87f, 0xae07, 0xe056, 0xe0c1, 0x0204, 0xa80f, 0xe056,
+	0xe0c2, 0x041e, 0xe41e, 0x031b, 0xe42e, 0xe0c0, 0x041f, 0xf7e8,
+	0xe0c0, 0x041f, 0xf7e8, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xa200,
+	0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xa203, 0xae19, 0xe052,
+	0xf1da, 0xe0c0, 0x0060, 0xaf08, 0xa806, 0xf18a, 0xe0c0, 0x0060,
+	0xa81e, 0xe016, 0xe0c1, 0x0060, 0xa821, 0xe017, 0xe056, 0xf0ea,
+	0xe0c0, 0x0044, 0xaf12, 0xa806, 0xe016, 0xe0c1, 0x0044, 0xaf17,
+	0xa803, 0xe056, 0xf03a, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xe0c0,
+	0x0044, 0xa203, 0xae19, 0xe052, 0xf0ba, 0xe41e, 0x02bb, 0xf088,
+	0xe0c0, 0x0044, 0xaf12, 0xa806, 0xf038, 0xa202, 0xe42e, 0xa200,
+	0xe42e, 0xe0c0, 0x041c, 0xe008, 0x00ff, 0xcca4, 0xc785, 0xe018,
+	0xe000, 0x0500, 0xa002, 0xae04, 0xe0c2, 0x041a, 0xa202, 0xe0c2,
+	0x0418, 0xe0c0, 0x0419, 0xf7ea, 0xa202, 0xe0c2, 0x0418, 0xe0c0,
+	0x0419, 0xf7ea, 0xe0c0, 0x041b, 0xaf20, 0xa01e, 0xaf08, 0xae28,
+	0xe0c1, 0x041b, 0xe009, 0xffff, 0xa01f, 0xaf09, 0xae09, 0xe056,
+	0xe0c2, 0x041d, 0xe42e, 0xe0c0, 0x041c, 0xe00a, 0x0200, 0xe0c2,
+	0x041c, 0xa228, 0xa102, 0xf7f0, 0xe0c0, 0x041c, 0xe00c, 0x0200,
+	0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xaf04, 0xa802, 0xe42e,
+	0xe40e, 0x0b17, 0xe40e, 0x0354, 0xe40e, 0x0358, 0xe40e, 0x035c,
+	0xe40e, 0x0364, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x0368, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe41e, 0x0429, 0xe40e, 0x00a4,
+	0xe41e, 0x0473, 0xe40e, 0x00a4, 0xe41e, 0x025b, 0xe41e, 0x0474,
+	0xe41e, 0x02ad, 0xe40e, 0x00a4, 0xe41e, 0x055c, 0xe40e, 0x00a4,
+	0xe41e, 0x058d, 0xe40e, 0x00a4, 0xe0c1, 0x0044, 0xa80f, 0xe056,
+	0xe42e, 0xa200, 0xe41e, 0x036c, 0xe42e, 0xe0c1, 0x0044, 0xaf0d,
+	0xae03, 0xe056, 0xe008, 0x003f, 0xe42e, 0xe0c1, 0x0044, 0xaf17,
+	0xa803, 0xe42e, 0xe0c1, 0x0044, 0xaf17, 0xa803, 0xa105, 0xf039,
+	0xa213, 0xe42e, 0xa201, 0xe42e, 0xa203, 0xe0c3, 0x040d, 0xe0c1,
+	0x0420, 0xa803, 0xf7db, 0xe160, 0x0003, 0xe166, 0x0400, 0xe167,
+	0x0500, 0x282c, 0xf166, 0xa102, 0xcc44, 0xe184, 0x03af, 0xa200,
+	0xe41e, 0x036c, 0xaf04, 0xe41e, 0x0375, 0xae20, 0x2e40, 0xe056,
+	0x9f17, 0x2030, 0x4c31, 0xae08, 0x9f17, 0xe41e, 0x03b5, 0xe190,
+	0xe190, 0xa201, 0xe0c3, 0x040d, 0xe42e, 0x2116, 0x4d16, 0x9f17,
+	0x2116, 0x4d16, 0x9f17, 0x2116, 0x4d16, 0x9f17, 0xe42e, 0xe0c0,
+	0x0044, 0xaf20, 0xa802, 0xe428, 0xe0c0, 0x0060, 0xa860, 0xe42a,
+	0xe0c0, 0x0061, 0xa83e, 0xa203, 0xe0c3, 0x040d, 0xcca4, 0xc785,
+	0xe018, 0xe000, 0x0500, 0xe09e, 0xe0c1, 0x0420, 0xa803, 0xf7db,
+	0xa200, 0xe41e, 0x0371, 0xa80e, 0xaf04, 0xe41e, 0x0375, 0xe41e,
+	0x037d, 0xe40b, 0x03e8, 0xa81e, 0xe41e, 0x0382, 0xae09, 0xe056,
+	0xae20, 0xe0c1, 0x006e, 0xe009, 0x1fff, 0xe056, 0x9f17, 0xe0c0,
+	0x0060, 0xa822, 0xa122, 0xf04a, 0x2030, 0x4c31, 0xf03e, 0x2031,
+	0x4c30, 0xae08, 0x9f17, 0xe0c0, 0x0062, 0x9f17, 0xe0c0, 0x0063,
+	0x9f17, 0xe0c0, 0x0064, 0x9f17, 0xa201, 0xe0c3, 0x040d, 0xe42e,
+	0x3cec, 0xe0c0, 0x0041, 0xe005, 0x0020, 0xae11, 0xe042, 0xce20,
+	0xd111, 0x0400, 0xd112, 0x00c0, 0x88ec, 0x0113, 0xca29, 0xf7f9,
+	0xe190, 0xe42e, 0xe42e, 0xe42e, 0xe0c0, 0x0060, 0xe049, 0xa81f,
+	0x3e45, 0xaf08, 0x3044, 0xe0c0, 0x0065, 0xaf04, 0xa80e, 0x3c5a,
+	0xe42e, 0xe41e, 0x0148, 0xe41e, 0x023a, 0xa200, 0xcc4a, 0xcc4c,
+	0xd130, 0x0003, 0xd04b, 0x0001, 0xd04c, 0x0000, 0xd008, 0x0000,
+	0xd03a, 0x0000, 0xa200, 0x3c7f, 0xe41e, 0x0acd, 0xa100, 0xf07a,
+	0xe41e, 0x074f, 0xa100, 0xf03a, 0xa202, 0x3c7f, 0xa23e, 0x3cf0,
+	0xe41e, 0x044d, 0xe41e, 0x0b7b, 0xe42e, 0xa200, 0xe0c2, 0x0074,
+	0xe0c2, 0x0076, 0xe0c2, 0x0077, 0xe0c2, 0x0079, 0xe0c2, 0x007a,
+	0x287f, 0xe016, 0x58f0, 0xe0c2, 0x0078, 0xa2fe, 0xe0c2, 0x0072,
+	0xe0c2, 0x006d, 0xe0c0, 0x0062, 0x3041, 0x2841, 0xae02, 0xa004,
+	0xe0c2, 0x0073, 0x20b5, 0x4cb6, 0xe0c2, 0x0071, 0x287f, 0xe0c2,
+	0x0070, 0xa202, 0xe42e, 0xe42e, 0xa200, 0xcc44, 0xcc4a, 0xcc4c,
+	0x3cb0, 0x3cb1, 0x3c33, 0x3c29, 0x3c28, 0x28b7, 0xf0b8, 0xa202,
+	0x3c50, 0x2831, 0xc70f, 0x7c50, 0x3c50, 0x8430, 0x8250, 0xe018,
+	0x3c50, 0xe41e, 0x041c, 0xe41e, 0x05a8, 0xd130, 0x0003, 0xd008,
+	0x0000, 0xd03a, 0x0000, 0xe41e, 0x0af8, 0xe41e, 0x038c, 0xe41e,
+	0x03bf, 0xe41e, 0x025f, 0xa2fe, 0xe0c2, 0x0077, 0xa2fa, 0xe0c2,
+	0x0071, 0xa202, 0xe0c2, 0x0076, 0xe41e, 0x0b45, 0xe408, 0x04f3,
+	0x2a2e, 0xe419, 0x074f, 0xe41e, 0x0790, 0xe40a, 0x04f8, 0xe41e,
+	0x05d9, 0xe42a, 0xa2fc, 0xe0c2, 0x0077, 0xd130, 0x0003, 0xd03a,
+	0x0003, 0xd04b, 0x0001, 0xd04c, 0x0000, 0xd008, 0x0000, 0xa200,
+	0xe0c2, 0x030a, 0x3c29, 0xe41e, 0x06e7, 0xe40a, 0x04f8, 0xe0c0,
+	0x0065, 0xaf04, 0xa80e, 0x3c3b, 0xf0fa, 0x283b, 0xa104, 0xf0c0,
+	0x2822, 0xf0aa, 0xa2fa, 0xe0c2, 0x0071, 0x2822, 0xe0c2, 0x0073,
+	0xe41e, 0x0b81, 0xe42e, 0xe41e, 0x038c, 0xe41e, 0x03bf, 0xe41e,
+	0x025f, 0xe41e, 0x07b0, 0xe424, 0x2825, 0xf0a8, 0xa200, 0x3c28,
+	0x2832, 0x3c27, 0xe41e, 0x065e, 0xa200, 0x3c29, 0xf05e, 0xe41e,
+	0x05fd, 0xe40a, 0x04f8, 0xe41e, 0x04fc, 0xe41e, 0x0b81, 0xe42e,
+	0xa200, 0xe0c2, 0x0076, 0xf78e, 0xa200, 0xe0c2, 0x0075, 0xe0c2,
+	0x0078, 0xe0c2, 0x0079, 0xe0c2, 0x007d, 0xe0c2, 0x007e, 0x2890,
+	0xf038, 0xe41e, 0x0960, 0x2c2b, 0xa002, 0x3c2b, 0xe0c2, 0x0070,
+	0x2822, 0xe0c2, 0x0073, 0x20b5, 0x4cb6, 0xe0c2, 0x006f, 0xa2fe,
+	0xe0c2, 0x007c, 0xe167, 0x0005, 0x2117, 0x4d17, 0xe0c2, 0x007e,
+	0x2117, 0x4d07, 0xe0c2, 0x007d, 0x2829, 0xe0c2, 0x0072, 0xc84a,
+	0xc84d, 0xae20, 0xe056, 0xe0c2, 0x0053, 0xe41e, 0x05c2, 0x2890,
+	0xf20a, 0xe0c0, 0x0077, 0x2a90, 0xb7d2, 0xe0c2, 0x0077, 0x2a44,
+	0xf03b, 0x288d, 0xf06a, 0xa2fe, 0xe0c2, 0x0071, 0xa202, 0xe42e,
+	0xa202, 0x3c8d, 0x2a79, 0x3e7b, 0x287a, 0x3c7d, 0xa2fe, 0xe0c2,
+	0x0071, 0xa2fc, 0xe0c2, 0x0077, 0xe41e, 0x0936, 0xe41e, 0x05e8,
+	0xe42e, 0x2834, 0xa002, 0x3c34, 0x1830, 0xe428, 0x3c34, 0x2835,
+	0xa002, 0x3c35, 0x1831, 0xe42e, 0xe41e, 0x079d, 0xe41e, 0x0174,
+	0xca29, 0xf7f9, 0xe0c0, 0x0042, 0xce20, 0xd111, 0x0400, 0xd112,
+	0x00c0, 0xd113, 0x0003, 0xca29, 0xf7f9, 0xe0c0, 0x0060, 0x3c2c,
+	0xe0c0, 0x0061, 0x3c40, 0xe41e, 0x099f, 0xe41e, 0x038c, 0xe42e,
+	0xe0c0, 0x0040, 0xa269, 0xae17, 0xe042, 0xe005, 0x0f00, 0xae03,
+	0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0300, 0xd112, 0x0100,
+	0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e, 0xe180, 0xe41e, 0x099f,
+	0xa200, 0x3c1d, 0x3c90, 0xe167, 0x04c0, 0xe166, 0x0054, 0xa200,
+	0x3c2d, 0x282c, 0xa102, 0xcc44, 0xe184, 0x05a5, 0x9e06, 0x5c2d,
+	0xa802, 0xb690, 0x3d17, 0x282d, 0xa002, 0x3c2d, 0xe190, 0xe42e,
+	0xa200, 0x3c3c, 0xe004, 0x0054, 0xe09c, 0x282c, 0xa102, 0xcc44,
+	0xe184, 0x05c0, 0x9e06, 0x5c3c, 0xa802, 0xf058, 0x283c, 0xe41e,
+	0x09da, 0xf05e, 0x283c, 0xa209, 0xe41e, 0x09d3, 0x2a3c, 0xa003,
+	0x3e3c, 0xe42e, 0xe004, 0x04c0, 0xe09e, 0xe004, 0x0054, 0xe09c,
+	0x282c, 0xa102, 0xcc44, 0xa200, 0x3c3c, 0xe184, 0x05d6, 0x2b17,
+	0xaf05, 0xa803, 0x5a3c, 0xe056, 0x2a3c, 0xa003, 0x3e3c, 0x9f06,
+	0xe42e, 0xe161, 0x04c0, 0x282c, 0xa102, 0xcc44, 0xa200, 0xe184,
+	0x05e4, 0x2b11, 0xa80d, 0xe01b, 0xe042, 0x182c, 0xe01a, 0xe42e,
+	0xe41e, 0x0923, 0xa200, 0x3c34, 0x3c35, 0xa202, 0x3c47, 0xe41e,
+	0x09f7, 0xe41e, 0x0551, 0xf7c8, 0xa200, 0x3c47, 0xe41e, 0x09f7,
+	0xe190, 0xe0c1, 0x014b, 0xf7e9, 0xe42e, 0x2824, 0xe0c2, 0x0115,
+	0xa202, 0xcf66, 0xa200, 0x3c33, 0x3c28, 0xcf64, 0xcf62, 0xa200,
+	0x3c51, 0x2833, 0x0850, 0x3c51, 0x2a51, 0x1a32, 0xf037, 0x2a32,
+	0x3e51, 0xe41e, 0x0635, 0x2a3a, 0xa003, 0x3e3a, 0x1851, 0xf0b4,
+	0x2851, 0x1832, 0xf6f4, 0x2822, 0xe41a, 0x0624, 0xe41e, 0x074a,
+	0xa202, 0xe42e, 0xa200, 0xe42e, 0xa200, 0x3c59, 0xc873, 0x2089,
+	0x4c88, 0xe045, 0x2403, 0x4c02, 0xae06, 0xe046, 0xa122, 0xe424,
+	0xba48, 0xba54, 0xba40, 0x3c59, 0xe42e, 0x2833, 0xc70f, 0x7c30,
+	0x3434, 0x3c35, 0x2833, 0xe002, 0x0094, 0xf028, 0xe190, 0xe41e,
+	0x067e, 0xe40a, 0x0655, 0xe41e, 0x06cd, 0x2034, 0x4c35, 0xcf62,
+	0x2833, 0xe002, 0x00c8, 0xf028, 0xe190, 0x2833, 0x1851, 0xf6b8,
+	0xa204, 0xcf66, 0x2833, 0x3c28, 0xe42e, 0x2833, 0x3c28, 0x2851,
+	0x3c27, 0xe41e, 0x065e, 0x2833, 0xe16a, 0xf73e, 0x2c2b, 0xe016,
+	0x3c36, 0xe016, 0x3c37, 0xa200, 0x3c38, 0x2828, 0x3c33, 0xc70f,
+	0x7c30, 0x3434, 0x3c35, 0x2833, 0x1827, 0xf0c2, 0x2822, 0xe418,
+	0x0ac1, 0xe41e, 0x097a, 0xe41e, 0x06cd, 0x2034, 0x4c35, 0xcf62,
+	0xf73e, 0x2827, 0x1828, 0x0829, 0x3c29, 0xe42e, 0x2853, 0xae06,
+	0xcf26, 0xd190, 0x0002, 0xcb20, 0xf7f8, 0xcb22, 0xe408, 0x06c0,
+	0xcb02, 0xaf0e, 0x3038, 0xaf08, 0x3036, 0xaf02, 0x3037, 0xaf12,
+	0x3c39, 0x2836, 0x4c37, 0xe41a, 0x0aac, 0x2836, 0x4c37, 0xe418,
+	0x06e1, 0x2822, 0xf068, 0x8839, 0x0182, 0xe190, 0xcb04, 0x3c39,
+	0x2837, 0x4422, 0xe418, 0x0ac1, 0xe40d, 0x06c0, 0x2837, 0xf158,
+	0x2836, 0xcf26, 0x2839, 0xae08, 0x4c37, 0xae02, 0x4c36, 0xae16,
+	0xcf02, 0xd190, 0x0001, 0x2822, 0xe418, 0x0ac1, 0xf0ad, 0xcb20,
+	0xf7f8, 0xcb22, 0xe408, 0x06c0, 0xe41e, 0x097a, 0xa202, 0xe42e,
+	0xd191, 0x0000, 0xe16a, 0xe41e, 0x06cd, 0x2034, 0x4c35, 0xcf62,
+	0x2829, 0xa002, 0x3c29, 0xa200, 0xe42e, 0xa202, 0xcf10, 0x2833,
+	0xa002, 0x3c33, 0xcf64, 0x2834, 0xa002, 0x3c34, 0x1830, 0xe428,
+	0xa208, 0xcf66, 0xa200, 0x3c34, 0x2835, 0xa002, 0x3c35, 0x1831,
+	0xe42e, 0xa201, 0xe161, 0x04e0, 0x3f11, 0x3f11, 0xe42e, 0xc872,
+	0x3c88, 0x3489, 0xba42, 0x3c22, 0x3c26, 0xba48, 0x3c24, 0x2822,
+	0xf2d8, 0xa202, 0x3cb7, 0xa224, 0x3c56, 0xa228, 0x3c57, 0xa22c,
+	0x3c55, 0xa232, 0x3c54, 0xa202, 0x3c23, 0xba48, 0xa12c, 0xe406,
+	0x0748, 0x3c50, 0x2831, 0xc70f, 0x7c50, 0x3c50, 0x8430, 0x8250,
+	0xe018, 0x3c50, 0xba40, 0xf05a, 0xba40, 0xa235, 0xe042, 0x3c54,
+	0xba40, 0xf05a, 0xba40, 0xa22f, 0xe042, 0x3c55, 0xba40, 0xa225,
+	0xe042, 0x3c56, 0xa004, 0x3c57, 0xf27e, 0xa224, 0x3c56, 0xa228,
+	0x3c57, 0xa22c, 0x3c55, 0xa232, 0x3c54, 0xa238, 0x3c58, 0x2859,
+	0xf04a, 0x2823, 0xe016, 0xf02e, 0xa200, 0x3c23, 0xba40, 0x3c53,
+	0xba40, 0xf08a, 0xba41, 0xa22e, 0xe042, 0x3c55, 0xa234, 0xe042,
+	0x3c54, 0xba40, 0xa225, 0xe042, 0x3c56, 0xa004, 0x3c57, 0xba40,
+	0xa239, 0xe042, 0x3c58, 0xa202, 0x3c25, 0xa202, 0xe42e, 0xba7e,
+	0xa200, 0xe42e, 0xc868, 0xa80e, 0x3c2a, 0x742a, 0xe42e, 0xba7e,
+	0xe005, 0x0043, 0xae11, 0xa99d, 0xae11, 0xa99b, 0xae11, 0xa9ad,
+	0xe046, 0xe408, 0x078e, 0xe41e, 0x0a9c, 0x3c00, 0xe41e, 0x0a9c,
+	0x3c01, 0xba7e, 0x3402, 0x3c03, 0xe41e, 0x0a9c, 0x3cb5, 0xe41e,
+	0x0a9c, 0x3cb6, 0xe41e, 0x0aa1, 0x3404, 0x3c05, 0xe41e, 0x0aa1,
+	0x3406, 0x3c07, 0xe41e, 0x0aa1, 0x3408, 0x3c09, 0xba7e, 0x28b5,
+	0xa01e, 0xaf08, 0xae08, 0x3c70, 0x28b6, 0xa01e, 0xaf08, 0xae08,
+	0x3c71, 0x2870, 0xa01e, 0xaf08, 0x3c30, 0x2871, 0xa01e, 0xaf08,
+	0x3c31, 0x8430, 0x8231, 0xe018, 0x3c32, 0xe42e, 0x2800, 0xe42e,
+	0xe41e, 0x0aa1, 0xf09a, 0xd022, 0x0007, 0xe184, 0x0798, 0xba4e,
+	0xe190, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xe167, 0x0080, 0xe0c0,
+	0x0064, 0x3517, 0x3d17, 0xe0c0, 0x0065, 0x3517, 0x3d17, 0xe0c0,
+	0x0066, 0x3517, 0x3d17, 0xe0c0, 0x0067, 0x3517, 0x3d17, 0xe42e,
+	0xa200, 0xcf24, 0xcf46, 0xcf68, 0xe0c2, 0x0104, 0xe0c2, 0x017f,
+	0xe0c2, 0x0149, 0xe0c2, 0x0308, 0xe0c2, 0x030d, 0xe0c2, 0x0309,
+	0xe0c2, 0x030a, 0xe0c2, 0x030b, 0xcc8e, 0xe0c2, 0x0320, 0xa246,
+	0xe0c2, 0x0100, 0xa200, 0xe0c2, 0x0128, 0x2a44, 0xb692, 0xae08,
+	0xa92c, 0xe0c2, 0x017c, 0xe004, 0x0014, 0xe0c2, 0x017d, 0xe0c0,
+	0x0050, 0xe049, 0xe008, 0x007f, 0x3c48, 0xaf11, 0xe009, 0x007f,
+	0x3e49, 0x4648, 0x3e48, 0xa200, 0x2a48, 0xa803, 0xf03b, 0xe00a,
+	0x0002, 0x2a48, 0xa805, 0xf03b, 0xe00a, 0x0009, 0x2a48, 0xa809,
+	0xf03b, 0xe00a, 0x0020, 0x2a48, 0xa811, 0xf03b, 0xe00a, 0x0040,
+	0xe0c2, 0x040c, 0xe0c1, 0x0046, 0xe004, 0x0044, 0xae10, 0xe042,
+	0x2a49, 0xa809, 0xf05b, 0xe161, 0x0084, 0x2111, 0x4d11, 0xe0c2,
+	0x0211, 0xe0c1, 0x0046, 0xe004, 0x0080, 0xae10, 0xe042, 0x2a49,
+	0xa811, 0xf05b, 0xe161, 0x0086, 0x2111, 0x4d11, 0xe0c2, 0x0212,
+	0x2854, 0xa132, 0xae04, 0xe049, 0x2855, 0xa12c, 0xe055, 0xae03,
+	0x2856, 0xa124, 0xe055, 0xcf2b, 0xe0c1, 0x0046, 0xe004, 0x003c,
+	0xae10, 0xe042, 0x2a49, 0xa803, 0xf05b, 0xe161, 0x0080, 0x2111,
+	0x4d11, 0xcf44, 0xa220, 0x4c22, 0xae02, 0xcf00, 0xa200, 0xcf46,
+	0x2830, 0xae20, 0x4c31, 0xae08, 0xe0c2, 0x0101, 0xe0c2, 0x0205,
+	0xcf60, 0xe0c0, 0x0046, 0xe005, 0x0000, 0xae11, 0xe042, 0x2a49,
+	0xa805, 0xf05b, 0xe161, 0x0082, 0x2111, 0x4d11, 0xe0c2, 0x0103,
+	0xa200, 0xe41e, 0x036c, 0xe0c2, 0x0102, 0x2841, 0xb6d5, 0xb611,
+	0x287b, 0xe412, 0x09cc, 0x2879, 0x3c7b, 0xa205, 0xe412, 0x09d3,
+	0xe41e, 0x09af, 0xe0c2, 0x0077, 0x3c79, 0xb7a8, 0x3c7a, 0x2a41,
+	0xf15b, 0x2879, 0xa203, 0xe412, 0x09cc, 0xe41e, 0x09af, 0x3c7c,
+	0x3c7a, 0xa209, 0xe412, 0x09cc, 0x287a, 0xf082, 0xa2fa, 0xe0c2,
+	0x0071, 0xa2fe, 0xe0c2, 0x0077, 0xe42e, 0xa206, 0xae08, 0x4c22,
+	0xae06, 0xe0c2, 0x0204, 0xa204, 0x1841, 0xe0c2, 0x0210, 0xa200,
+	0xe0c2, 0x0215, 0xe41e, 0x036c, 0xe0c1, 0x0210, 0xa803, 0xae11,
+	0xe056, 0xe0c2, 0x0213, 0xa204, 0xe0c2, 0x0208, 0x2a79, 0xe0c3,
+	0x020b, 0x2841, 0xf04a, 0x287c, 0xe0c2, 0x0214, 0x287b, 0xe404,
+	0x08c3, 0xa202, 0xe0c2, 0x0302, 0x287b, 0xf032, 0x2879, 0xb608,
+	0xe0c2, 0x0380, 0xe004, 0x0055, 0xe0c2, 0x030c, 0xa208, 0x4c23,
+	0xe0c2, 0x0303, 0xa20e, 0xe0c2, 0x0312, 0xe0c0, 0x0414, 0xe418,
+	0x018c, 0xe0c0, 0x0414, 0xe41a, 0x08fa, 0xa200, 0xe0c2, 0x0308,
+	0xa200, 0xe0c2, 0x0302, 0xa200, 0x3c44, 0x3c45, 0xa202, 0x3c47,
+	0x287d, 0xf254, 0xe0c0, 0x0060, 0xe049, 0xaf08, 0xf20a, 0x3044,
+	0xa81f, 0x3e45, 0x287d, 0xe0c2, 0x0143, 0xa200, 0xe41e, 0x036c,
+	0xe0c2, 0x017f, 0x2830, 0xa102, 0xae20, 0x4c31, 0xa102, 0xe0c2,
+	0x0142, 0xe41e, 0x0371, 0xae20, 0x2a44, 0xf02b, 0x4c45, 0xe0c2,
+	0x014e, 0xe0c0, 0x0061, 0xa87e, 0xe0c2, 0x0144, 0x287a, 0x3c7d,
+	0xe0c2, 0x0071, 0xa202, 0x3c3a, 0xe41e, 0x0274, 0xa202, 0xe0c2,
+	0x0106, 0xe42e, 0xe167, 0x01a0, 0x2317, 0x4f17, 0xe0c3, 0x0152,
+	0x2b17, 0xe009, 0x00ff, 0xae21, 0x4f07, 0xe0c3, 0x0153, 0xe0c1,
+	0x0101, 0xe0c3, 0x015d, 0x2a7b, 0xae21, 0xe167, 0x01a2, 0x2907,
+	0xaf10, 0xe008, 0x001b, 0xe055, 0xe0c3, 0x015c, 0xa202, 0xe0c2,
+	0x0150, 0xe0c0, 0x0150, 0xf7ea, 0xa200, 0xe0c2, 0x0150, 0xe0c0,
+	0x0151, 0xf7e8, 0xe42e, 0xa246, 0xe0c2, 0x0100, 0x2a44, 0xb692,
+	0xae08, 0xa92c, 0xe0c2, 0x017c, 0xe004, 0x0014, 0xe0c2, 0x017d,
+	0xa200, 0xe41e, 0x036c, 0xe0c2, 0x0102, 0xe42e, 0xe0c0, 0x0060,
+	0xe049, 0xa81e, 0x3c45, 0xaf09, 0x3244, 0x287d, 0xe0c2, 0x0143,
+	0xa200, 0xe0c2, 0x017f, 0xe0c2, 0x0149, 0xa200, 0xe41e, 0x036c,
+	0xe0c2, 0x017f, 0x2830, 0xa102, 0xae20, 0x4c31, 0xa102, 0xe0c2,
+	0x0142, 0xe41e, 0x0371, 0xae20, 0x2a44, 0xf02b, 0x4c45, 0xe0c2,
+	0x014e, 0xe0c0, 0x0061, 0xa87e, 0xe0c2, 0x0144, 0xa203, 0xe42e,
+	0x2824, 0x3c43, 0xe0c0, 0x0111, 0xf7e8, 0x2844, 0xe42a, 0xa204,
+	0xae0e, 0x4c30, 0xa102, 0xae0e, 0x4c31, 0xa102, 0xe0c1, 0x014b,
+	0xf7e9, 0xe0c2, 0x014d, 0xa202, 0xe0c2, 0x014a, 0xe0c1, 0x014b,
+	0xf7e9, 0xe42e, 0xa27f, 0x2836, 0xf028, 0x2a39, 0xe0c3, 0x012a,
+	0x2836, 0xe0c2, 0x0114, 0x2841, 0xf06a, 0x2837, 0xe016, 0xae0a,
+	0x4c24, 0xcf6a, 0xe41e, 0x0996, 0xe0c0, 0x0111, 0xf7e8, 0xa202,
+	0xe0c2, 0x0110, 0x2844, 0xe418, 0x09f7, 0xe42e, 0x283a, 0xe0c2,
+	0x0131, 0xa200, 0x3c3a, 0x4c38, 0xe0c2, 0x0130, 0xe42e, 0xa2fe,
+	0x3c7b, 0x3c79, 0x3c7a, 0x3c7d, 0xa200, 0x3c7e, 0x2a2c, 0xa103,
+	0xcc45, 0xe161, 0x04c0, 0xe184, 0x09ad, 0x3d11, 0xe42e, 0x287e,
+	0x3c3c, 0x283c, 0xe000, 0x04c0, 0xe092, 0x2901, 0xf0ca, 0x283c,
+	0xa002, 0x3c3c, 0x182c, 0xf028, 0x3c3c, 0x283c, 0x187e, 0xf728,
+	0xa2fe, 0xe42e, 0xa20a, 0x3d01, 0xa202, 0x083c, 0x3c7e, 0x182c,
+	0xf028, 0x3c7e, 0x283c, 0xe42e, 0xe000, 0x04c0, 0xe092, 0x2901,
+	0xe052, 0x3d01, 0xe42e, 0xe000, 0x04c0, 0xe092, 0x2901, 0xe056,
+	0x3d01, 0xe42e, 0xe000, 0x04c0, 0xe092, 0x2901, 0xa802, 0x3d01,
+	0xe42e, 0x2834, 0x4c35, 0xe01a, 0x3c46, 0x2843, 0xae02, 0x4c46,
+	0xae02, 0x4c47, 0xae0e, 0x4c34, 0xae0e, 0x4c35, 0xe0c1, 0x014b,
+	0xf7e9, 0xe0c2, 0x014d, 0xa202, 0xe0c2, 0x014a, 0xe42e, 0x2834,
+	0x4c35, 0xe01a, 0x3c46, 0x2843, 0xae02, 0x4c46, 0xae02, 0x4c47,
+	0xae0e, 0x4c34, 0xae0e, 0x4c35, 0xe0c1, 0x014b, 0xf7e9, 0xe0c2,
+	0x014d, 0xa202, 0xe0c2, 0x014a, 0xe42e, 0xa218, 0x34b3, 0x3cb4,
+	0x249c, 0x4c9d, 0xd027, 0x0000, 0xe41e, 0x0bf9, 0xd027, 0x0001,
+	0xf2f8, 0x249c, 0x4c9d, 0xe41e, 0x0bce, 0xe095, 0xe41e, 0x0bd2,
+	0xe084, 0xaf02, 0xe000, 0x0500, 0xe092, 0xe41e, 0x0a82, 0xe084,
+	0xa802, 0xe41e, 0x0b9b, 0x00b0, 0x0cb1, 0x34b0, 0x3cb1, 0xf186,
+	0x2693, 0x4e94, 0xe046, 0xf142, 0x24b0, 0x4cb1, 0xa018, 0x34b0,
+	0x3cb1, 0x34b3, 0x3cb4, 0x249c, 0x4c9d, 0xd027, 0x0000, 0xe41e,
+	0x0bf9, 0xd027, 0x0001, 0xf048, 0xa200, 0xe42e, 0xe16b, 0xa200,
+	0x34b0, 0x3cb1, 0xa202, 0xe42e, 0xa202, 0x3ca2, 0xa240, 0x34b3,
+	0x3cb4, 0x249c, 0x4c9d, 0xd027, 0x0000, 0xe41e, 0x0bf9, 0xd027,
+	0x0001, 0xe408, 0x0a80, 0x249c, 0x4c9d, 0xe41e, 0x0bce, 0xe095,
+	0xe41e, 0x0bd2, 0xe084, 0xa00c, 0xaf02, 0xe000, 0x0500, 0xe092,
+	0xe084, 0xa802, 0xe41e, 0x0b9b, 0xe008, 0xffff, 0x3cb2, 0xa140,
+	0xf0f4, 0x28b2, 0x34b3, 0x3cb4, 0x249c, 0x4c9d, 0xd027, 0x0000,
+	0xe41e, 0x0bf9, 0xd027, 0x0001, 0xf048, 0xa200, 0xe42e, 0xe16b,
+	0xa202, 0xe42e, 0x2111, 0x4d09, 0xe005, 0x0043, 0xae11, 0xa99d,
+	0xae11, 0xa99b, 0xae11, 0xa9ad, 0xae11, 0xe046, 0xf05a, 0xa200,
+	0x3cb1, 0x3c2e, 0xe42e, 0xa241, 0x3eb1, 0xaf03, 0xe082, 0xe042,
+	0xe092, 0xa202, 0x3c2e, 0xe42e, 0xba4e, 0xba4f, 0xae11, 0xe056,
+	0xe42e, 0xba4e, 0xba4f, 0xae11, 0xe056, 0xba4f, 0xae21, 0xe056,
+	0xba4f, 0xae31, 0xe056, 0xe42e, 0x6858, 0xe42d, 0xe161, 0x04e0,
+	0xf088, 0xba4a, 0xa140, 0x3d11, 0xba4a, 0xa140, 0x3d11, 0xe42e,
+	0xe049, 0xa87e, 0xa140, 0x3d11, 0xaf0d, 0xa87f, 0xa141, 0x3f11,
+	0xe42e, 0xd1a5, 0x0000, 0xe161, 0x04e0, 0x2111, 0x4d11, 0xcf4c,
+	0xd1a0, 0x0001, 0xcb41, 0xf7f9, 0xe42e, 0xe41e, 0x023a, 0xa206,
+	0xae1e, 0xcec0, 0xd160, 0x0600, 0xe0c0, 0x0060, 0x3491, 0x3c92,
+	0xe0c1, 0x0061, 0xae15, 0x3693, 0x3e94, 0xe042, 0x3495, 0x3c96,
+	0xe0c0, 0x0048, 0x349c, 0x3c9d, 0x3497, 0xe008, 0xfe00, 0x3c98,
+	0x2c9d, 0xe008, 0x01ff, 0x3ca0, 0xe41e, 0x0a4c, 0xf07d, 0xe41e,
+	0x0b5c, 0xe41e, 0x0b47, 0xa202, 0xe42e, 0xa200, 0xe16a, 0xe42e,
+	0xa206, 0xae1e, 0xcec0, 0xd160, 0x0600, 0xe0c0, 0x0048, 0xe0c2,
+	0x0051, 0x349c, 0x3c9d, 0x3497, 0xe008, 0xfe00, 0x3c98, 0x2c9d,
+	0xe008, 0x01ff, 0x3ca0, 0xe41e, 0x0a0d, 0xf078, 0xe41e, 0x0b5c,
+	0xe41e, 0x0b47, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0xcb40,
+	0xf7f8, 0xe41e, 0x0b1c, 0xe470, 0xca28, 0xf7f8, 0xe004, 0x0080,
+	0xce24, 0x28a1, 0xae0e, 0xce22, 0x2497, 0x4c98, 0xce20, 0xe0c0,
+	0x0043, 0xa806, 0xae02, 0xa022, 0xce26, 0xca28, 0xf7f8, 0x2497,
+	0x4c98, 0xe000, 0x0200, 0x3497, 0x3c98, 0x1495, 0x1c96, 0xf054,
+	0x2491, 0x4c92, 0x3497, 0x3c98, 0xd04c, 0x0000, 0x28a1, 0xae0e,
+	0xcc6e, 0x28a1, 0xe016, 0x3ca1, 0xe42e, 0x2890, 0xe42e, 0xa200,
+	0x3ca1, 0xce92, 0xe41e, 0x0b1c, 0xe41e, 0x0b1c, 0xe128, 0xd071,
+	0x2020, 0xe181, 0x2ca0, 0xa102, 0xf074, 0xcc44, 0xe184, 0x0b59,
+	0xba4e, 0xe190, 0xe190, 0xe42e, 0xe004, 0x1495, 0xae20, 0xcc9e,
+	0xd030, 0x0000, 0xd034, 0x0000, 0xd033, 0x0000, 0xd035, 0x0000,
+	0xd036, 0x00ff, 0xd037, 0x0000, 0xd038, 0x0000, 0xd039, 0x0000,
+	0xd04b, 0x0001, 0xd04c, 0x0000, 0xd046, 0x0000, 0xd047, 0x0000,
+	0xd149, 0x0000, 0xe42e, 0x249c, 0x4c9d, 0x08b2, 0x349c, 0x3c9d,
+	0xf07e, 0x249c, 0x4c9d, 0x04b0, 0x0cb1, 0x349c, 0x3c9d, 0x1495,
+	0x1c96, 0xf074, 0x249c, 0x4c9d, 0x1493, 0x1c94, 0x349c, 0x3c9d,
+	0x249c, 0x4c9d, 0xe0c2, 0x0048, 0xe0c2, 0x0052, 0xe42e, 0xa200,
+	0x34b0, 0x3cb1, 0xe42e, 0xf0a8, 0x2911, 0xe008, 0xffff, 0xae20,
+	0x2b11, 0xe009, 0xffff, 0xe042, 0xf0fe, 0x2911, 0xe008, 0x00ff,
+	0xae20, 0x2b11, 0xe009, 0xffff, 0xe042, 0xae10, 0x2b11, 0xe009,
+	0xff00, 0xaf11, 0xe042, 0x2aa2, 0xe42b, 0xe049, 0xaf31, 0xe009,
+	0x00ff, 0xe093, 0xe049, 0xaf21, 0xe009, 0x00ff, 0xe095, 0xe049,
+	0xaf11, 0xe009, 0x00ff, 0xe008, 0x00ff, 0xae10, 0xe056, 0xae10,
+	0xe085, 0xe056, 0xae10, 0xe083, 0xe056, 0xe42e, 0xe049, 0xa80f,
+	0xe046, 0xe42e, 0xca29, 0xf7f9, 0xd111, 0x0500, 0xce20, 0x2695,
+	0x4e96, 0xe045, 0xe004, 0x0040, 0xe065, 0xaf03, 0xce25, 0x3ea3,
+	0xe41e, 0x0bf0, 0xa240, 0x18a3, 0xe426, 0xce24, 0x28a3, 0xe000,
+	0x0500, 0xce22, 0x2491, 0x4c92, 0xce20, 0xe41e, 0x0bf0, 0xe42e,
+	0xe0c0, 0x0043, 0xa806, 0xae02, 0xa002, 0xce26, 0xca28, 0xf7f8,
+	0xe42e, 0x34c9, 0x3cca, 0xa200, 0x3c15, 0xe0c0, 0x0049, 0x34cb,
+	0x3ccc, 0xe0c0, 0x0045, 0xaf04, 0x301d, 0xe0c0, 0x0049, 0x3499,
+	0x3c9a, 0x10cb, 0x1ccc, 0x2a15, 0xb611, 0x3e15, 0x2699, 0x4e9a,
+	0x16c9, 0x1eca, 0xf033, 0x0693, 0x0e94, 0x16b3, 0x1eb4, 0xa200,
+	0xe423, 0x281d, 0x3c90, 0xe428, 0x2815, 0xf648, 0xe41e, 0x01db,
+	0xe0c0, 0x005c, 0xe008, 0x4000, 0xf5da, 0xe0c0, 0x005d, 0xe00a,
+	0x4000, 0xe0c2, 0x005d, 0xa202, 0xce00, 0x3c15, 0xf53e, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0080, 0x0060, 0x0008, 0x0006,
+	0x00b0, 0x0090, 0x000b, 0x0009, 0x0160, 0x0120, 0x0016, 0x0012,
+	0x02c0, 0x0240, 0x0058, 0x0012, 0x0580, 0x0480, 0x0160, 0x0012,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0063, 0x000d, 0x000f, 0x0011, 0x0013, 0x0015, 0x0017, 0x0000,
+	0xffff, 0xfffe, 0x0001, 0x0002, 0x0000, 0x0002, 0xffff, 0xffff,
+	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xfffe,
+	0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe,
+	0xfffe, 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0xfffd,
+	0xfffd, 0xfffd, 0xfffd, 0xfffd, 0x0000, 0x0001, 0x0001, 0x0001,
+	0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0002,
+	0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002,
+	0x0002, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0002, 0x0001, 0xfffb, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
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+	0x0330, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a, 0xe008, 0xffff,
+	0x3cee, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11, 0xe056, 0x3cef,
+	0xe40e, 0x0058, 0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2,
+	0x0008, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xe0c0, 0x0059, 0xf7ea,
+	0xa11e, 0xf198, 0xa202, 0xe0c2, 0x0058, 0xe004, 0xca20, 0xae20,
+	0xe005, 0x210a, 0xe056, 0xe0c2, 0x0070, 0xe004, 0x0000, 0xae20,
+	0xe00a, 0x9cea, 0xe0c2, 0x0071, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+	0x0058, 0xf64e, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058, 0xd027,
+	0x0001, 0xe42e, 0xa200, 0xe0c1, 0x005b, 0xf21b, 0xa23c, 0xa103,
+	0xf37b, 0xa24c, 0xa103, 0xf34b, 0xa258, 0xa103, 0xf1db, 0xe004,
+	0x003a, 0xa103, 0xf2db, 0xe004, 0x003f, 0xa103, 0xf29b, 0xe004,
+	0x0045, 0xa103, 0xf25b, 0xa103, 0xf14b, 0xe004, 0x0063, 0xa103,
+	0xf1ab, 0xe004, 0x006a, 0xa107, 0xf1bb, 0xa200, 0xe0c1, 0x005e,
+	0xf17b, 0xa028, 0xf15e, 0xe0c1, 0x005e, 0xf12b, 0xa010, 0xf10e,
+	0xe004, 0x0049, 0xe0c1, 0x005e, 0xf0bb, 0xa010, 0xa103, 0xf08b,
+	0xa010, 0xf06e, 0xe0c1, 0x005e, 0xf03b, 0xe004, 0x0074, 0xae16,
+	0xe0c1, 0x0040, 0xe041, 0xce21, 0xd111, 0x0000, 0xd112, 0x2800,
+	0xd113, 0x000b, 0xe1e1, 0xe42e, 0xe41e, 0x023a, 0xe0c0, 0x0059,
+	0xa102, 0xe42a, 0xe0c0, 0x005b, 0xa810, 0xf058, 0xa206, 0xe41e,
+	0x0153, 0xe42e, 0xe004, 0x0350, 0xe67c, 0xe0c0, 0x005b, 0xa810,
+	0xf058, 0xa204, 0xe41e, 0x0153, 0xe42e, 0xe004, 0x0352, 0xe67c,
+	0xa200, 0xc401, 0xe188, 0x00eb, 0x3d11, 0xe161, 0x00f2, 0xe188,
+	0x0b0d, 0x3d11, 0xe42e, 0x3cec, 0xe0c0, 0x0041, 0xe005, 0x0000,
+	0xae11, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0c00, 0x88ec,
+	0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0059, 0xa106, 0xf048,
+	0xe004, 0x0076, 0xe42e, 0xe0c0, 0x0059, 0xa10c, 0xf038, 0xe004,
+	0x0071, 0xe004, 0x0070, 0xe42e, 0xe0c0, 0x006b, 0xe167, 0x01a0,
+	0x3d07, 0xe0c0, 0x0414, 0xe428, 0xe0c1, 0x0044, 0xa809, 0xae33,
+	0xe0c0, 0x006a, 0xe167, 0x01a0, 0x3517, 0x3d17, 0xe0c0, 0x006b,
+	0xe056, 0x3517, 0x3d07, 0xe42e, 0xe167, 0x01a0, 0x2907, 0xe0c2,
+	0x0151, 0xa204, 0xe0c2, 0x0150, 0xe0c0, 0x0150, 0xa804, 0xf7da,
+	0xa208, 0xe0c2, 0x0150, 0xe42e, 0xe0c0, 0x004a, 0xe42a, 0xe0c0,
+	0x005b, 0xa110, 0xf142, 0xe0c0, 0x0059, 0xa102, 0xe41a, 0x01be,
+	0xe0c0, 0x0059, 0xa106, 0xe41a, 0x01cb, 0xe0c0, 0x0047, 0xe0c2,
+	0x0048, 0xa200, 0xe0c2, 0x004a, 0xa202, 0xe42e, 0xe0c0, 0x0047,
+	0xe0c2, 0x0049, 0xa200, 0xe0c2, 0x004a, 0xe42e, 0xe0c0, 0x004a,
+	0xa802, 0xa23e, 0x3cf0, 0xa202, 0x58f0, 0xe0c2, 0x0078, 0xa220,
+	0xe0c2, 0x0070, 0xe42e, 0xe0c0, 0x004a, 0xa802, 0xa220, 0xe0c2,
+	0x0076, 0xa200, 0xe0c2, 0x0072, 0xa2fc, 0xe0c2, 0x0077, 0xa2fa,
+	0xe0c2, 0x0071, 0xe42e, 0xe0c0, 0x0045, 0xaf04, 0xa80e, 0xa104,
+	0xe428, 0xa202, 0xe0c2, 0x004a, 0xe0c0, 0x0111, 0xf7e8, 0xca28,
+	0xf7f8, 0xca48, 0xa802, 0xf7e8, 0xa208, 0xae14, 0xa102, 0xe190,
+	0xf7e2, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xe0c0, 0x041f, 0xf7e8,
+	0xa200, 0xe0c2, 0x041c, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xe004,
+	0x0078, 0xe0c2, 0x0009, 0xa200, 0xe0c2, 0x0009, 0xe0c0, 0x000d,
+	0xf7e8, 0xe42e, 0xc001, 0x3443, 0x3c42, 0xc000, 0xe42e, 0xc001,
+	0x2c43, 0x2e42, 0xc000, 0xe42a, 0x1c42, 0xf0b4, 0xe04a, 0xaf10,
+	0x1840, 0xf074, 0xe009, 0x00ff, 0x1a41, 0xf034, 0xa202, 0xe42e,
+	0xa2fe, 0xe42e, 0xe41e, 0x023a, 0xd160, 0x0620, 0xe004, 0x0019,
+	0xae18, 0xcec0, 0xe42e, 0xe41e, 0x024f, 0xe000, 0x0040, 0xce50,
+	0xa200, 0xd022, 0x00ff, 0xe184, 0x0236, 0xce52, 0xe190, 0xe41e,
+	0x0257, 0xe42e, 0xa204, 0xae22, 0xcc9e, 0xa200, 0xcc72, 0xcc8c,
+	0xcc8e, 0xe004, 0xa810, 0xae20, 0xe00a, 0x9322, 0xce4a, 0xd16f,
+	0x0003, 0xe190, 0xe190, 0xe190, 0xd16f, 0x0000, 0xe42e, 0xe004,
+	0x0030, 0xce50, 0xca50, 0xa802, 0xf7ea, 0xc000, 0xe42e, 0xe004,
+	0x0020, 0xce50, 0xe42e, 0xa200, 0xe0c2, 0x041c, 0xe42e, 0xe41e,
+	0x02bb, 0xe42a, 0xe0c0, 0x0061, 0xe008, 0x001f, 0xe00a, 0x0100,
+	0xe0c2, 0x041c, 0xe41e, 0x02f1, 0xe41e, 0x032b, 0xae12, 0xe0c2,
+	0x041e, 0xe41e, 0x031b, 0xe42e, 0xe41e, 0x02df, 0xe42a, 0xe0c0,
+	0x041f, 0xf7e8, 0xe0c0, 0x0210, 0xa804, 0xf118, 0xe0c0, 0x0215,
+	0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0216, 0xf0be, 0xe0c0, 0x0213,
+	0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0214, 0xf03e, 0xe0c0, 0x020b,
+	0xe00a, 0x0100, 0xe0c2, 0x041c, 0xe41e, 0x02f1, 0xe41e, 0x032b,
+	0xae12, 0xe0c1, 0x0210, 0xa803, 0xae15, 0xe056, 0xe0c1, 0x0204,
+	0xaf0b, 0xa87f, 0xae07, 0xe056, 0xe0c1, 0x0204, 0xa80f, 0xe056,
+	0xe0c2, 0x041e, 0xe41e, 0x031b, 0xe42e, 0xe0c0, 0x041f, 0xf7e8,
+	0xe0c0, 0x041f, 0xf7e8, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xa200,
+	0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xa203, 0xae19, 0xe052,
+	0xf1da, 0xe0c0, 0x0060, 0xaf08, 0xa806, 0xf18a, 0xe0c0, 0x0060,
+	0xa81e, 0xe016, 0xe0c1, 0x0060, 0xa821, 0xe017, 0xe056, 0xf0ea,
+	0xe0c0, 0x0044, 0xaf12, 0xa806, 0xe016, 0xe0c1, 0x0044, 0xaf17,
+	0xa803, 0xe056, 0xf03a, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xe0c0,
+	0x0044, 0xa203, 0xae19, 0xe052, 0xf0ba, 0xe41e, 0x02bb, 0xf088,
+	0xe0c0, 0x0044, 0xaf12, 0xa806, 0xf038, 0xa202, 0xe42e, 0xa200,
+	0xe42e, 0xe0c0, 0x041c, 0xe008, 0x00ff, 0xcca4, 0xc785, 0xe018,
+	0xe000, 0x0500, 0xa002, 0xae04, 0xe0c2, 0x041a, 0xa202, 0xe0c2,
+	0x0418, 0xe0c0, 0x0419, 0xf7ea, 0xa202, 0xe0c2, 0x0418, 0xe0c0,
+	0x0419, 0xf7ea, 0xe0c0, 0x041b, 0xaf20, 0xa01e, 0xaf08, 0xae28,
+	0xe0c1, 0x041b, 0xe009, 0xffff, 0xa01f, 0xaf09, 0xae09, 0xe056,
+	0xe0c2, 0x041d, 0xe42e, 0xe0c0, 0x041c, 0xe00a, 0x0200, 0xe0c2,
+	0x041c, 0xa228, 0xa102, 0xf7f0, 0xe0c0, 0x041c, 0xe00c, 0x0200,
+	0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xaf04, 0xa802, 0xe42e,
+	0xe40e, 0x0bb5, 0xe40e, 0x0354, 0xe40e, 0x0358, 0xe40e, 0x035c,
+	0xe40e, 0x0364, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x0368,
+	0xe40e, 0x036a, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe41e, 0x036e, 0xe40e, 0x00a4,
+	0xe41e, 0x038d, 0xe40e, 0x00a4, 0xe41e, 0x025b, 0xe41e, 0x038e,
+	0xe41e, 0x02ad, 0xe40e, 0x00a4, 0xe41e, 0x03e0, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe41e, 0x03e9, 0xe40e, 0x00a4, 0xe41e, 0x0148,
+	0xe41e, 0x093e, 0xe41e, 0x0417, 0xe41e, 0x09fd, 0xa200, 0xcc4a,
+	0xcc4c, 0xa200, 0x3c1f, 0xe41e, 0x095f, 0xe41e, 0x0b81, 0xf08a,
+	0xe41e, 0x070e, 0xe41e, 0x0561, 0xf03d, 0xa202, 0x3c1f, 0xe41e,
+	0x098d, 0xe41e, 0x0c17, 0xe16a, 0xe42e, 0xe42e, 0xa200, 0xcc44,
+	0xcc4a, 0xcc4c, 0x3c4a, 0x3c4b, 0xe41e, 0x095f, 0xe41e, 0x0b81,
+	0xf2ea, 0xe41e, 0x070e, 0xe41e, 0x08bc, 0xe41e, 0x0a14, 0xe41e,
+	0x0b7a, 0xe41e, 0x0746, 0xe41e, 0x0b11, 0xe41e, 0x0a1e, 0x28c1,
+	0xf1e8, 0xe41e, 0x0418, 0x281a, 0xe418, 0x0561, 0xe41e, 0x0582,
+	0xa202, 0xb61a, 0x3c1f, 0xf13d, 0xe41e, 0x0418, 0x28c1, 0xf0f8,
+	0xe41e, 0x041c, 0xf0f8, 0xe41e, 0x0418, 0xe41e, 0x08f8, 0xf07a,
+	0xe41e, 0x0418, 0xe41e, 0x0a28, 0xe41e, 0x042d, 0x2852, 0xe414,
+	0x0c38, 0x28c1, 0xe41e, 0x0927, 0xe41e, 0x0914, 0xe41e, 0x0461,
+	0xe41e, 0x0b7b, 0xe41e, 0x07ff, 0xe41e, 0x0b61, 0x285c, 0x3c5f,
+	0xe41e, 0x08e3, 0xe41e, 0x098d, 0xe41e, 0x0c17, 0xe16a, 0xe42e,
+	0xe41e, 0x0899, 0xe41e, 0x0a06, 0xe41e, 0x0b0c, 0xe41e, 0x0a7e,
+	0xe42e, 0xe180, 0xe41e, 0x093e, 0xa200, 0x3cbe, 0x3cc1, 0xa2fa,
+	0x3c5a, 0x3c5b, 0x3c5c, 0xa2fc, 0x3c52, 0xa2fe, 0x3c53, 0xa200,
+	0x3c57, 0x3c56, 0xe166, 0x0054, 0x9e06, 0xf16a, 0x2851, 0xa102,
+	0xcc44, 0xa200, 0x3c5e, 0xe184, 0x0411, 0x9e06, 0x5c5e, 0xa802,
+	0xf07a, 0x285e, 0xe000, 0x02d0, 0xe09e, 0xa208, 0x3d07, 0x285e,
+	0xa002, 0x3c5e, 0xe190, 0xe42e, 0xca28, 0xf7f8, 0xe42e, 0xe42e,
+	0x2861, 0xa002, 0x3c61, 0xe42e, 0x2860, 0xe42a, 0xa102, 0xf04a,
+	0xa102, 0xf05a, 0xf09e, 0x2829, 0xf078, 0xf04e, 0x2829, 0xa104,
+	0xf03a, 0xa200, 0xe42e, 0xa202, 0xe42e, 0x282b, 0x3c2d, 0x2829,
+	0xa104, 0xf05a, 0x282b, 0x3c2c, 0x3c2d, 0xf04e, 0x282c, 0x642b,
+	0x3c2d, 0xe41e, 0x04cd, 0xe41e, 0x0723, 0xe41e, 0x0a7e, 0xe41e,
+	0x0ab1, 0xe41e, 0x025f, 0xe41e, 0x0767, 0xe41e, 0x0761, 0xa200,
+	0x3446, 0x3c47, 0xe41e, 0x0462, 0xf0dd, 0x2046, 0x4c47, 0x1842,
+	0xf0c2, 0xe41e, 0x05f2, 0xf06d, 0x2c45, 0x1046, 0x1c47, 0xf7a4,
+	0xf72a, 0xe41e, 0x048a, 0xe16a, 0xd1e6, 0x0001, 0xcbe2, 0xf7f8,
+	0xe42e, 0xe42e, 0xe41e, 0x04a3, 0x2822, 0x1836, 0xf058, 0x2823,
+	0x1837, 0xf028, 0xf12e, 0x2829, 0xe01a, 0xa802, 0xf088, 0x2822,
+	0x3c36, 0x2823, 0x3c37, 0xa200, 0x3c38, 0xf03e, 0xa202, 0x3c38,
+	0x2838, 0xf03a, 0xe16b, 0xe42e, 0xe41e, 0x04f5, 0xe42d, 0x2046,
+	0x4c47, 0x1842, 0xe422, 0xcb86, 0xa102, 0xf770, 0xe41e, 0x04bd,
+	0xf748, 0xe42e, 0x2829, 0xf088, 0x2456, 0x4c57, 0xf05a, 0xa204,
+	0x4c10, 0xcf80, 0xcfc6, 0x2046, 0x4c47, 0xe41a, 0x04a3, 0x2046,
+	0x4c47, 0x1842, 0xe422, 0xe41e, 0x0529, 0x244a, 0x4c4b, 0xa002,
+	0x344a, 0x3c4b, 0xf75e, 0x282a, 0xcf82, 0xd1c3, 0x0000, 0x282b,
+	0xcf96, 0xd188, 0x0001, 0x2824, 0xa102, 0x1825, 0xe016, 0x3c26,
+	0x2825, 0xa002, 0x3c25, 0xae02, 0xe000, 0x0360, 0xe092, 0x2111,
+	0x4d11, 0xae06, 0x3427, 0x3c28, 0xe42e, 0x2826, 0xe428, 0xc872,
+	0x1027, 0x1c28, 0xa00e, 0xe424, 0xa10e, 0xe012, 0x3c49, 0xb60c,
+	0xe42a, 0x7849, 0xe428, 0x7449, 0xe42e, 0x2829, 0xa104, 0xf09a,
+	0x282f, 0x1830, 0xf022, 0x0833, 0x3c31, 0x282f, 0x3c30, 0xe42e,
+	0x2830, 0x182f, 0xf022, 0x0833, 0x3c32, 0x2831, 0x1832, 0xa400,
+	0x3c32, 0x2832, 0xae1c, 0xc70f, 0x7c31, 0x3c34, 0x2831, 0x1832,
+	0xae1c, 0xc70f, 0x7c31, 0x3c35, 0xe005, 0x3fff, 0x2834, 0xe066,
+	0x3c34, 0x2835, 0xe066, 0x3c35, 0xe42e, 0xd184, 0x0002, 0xd185,
+	0x0000, 0xe190, 0xd1d0, 0x003f, 0xcba0, 0xa810, 0xcba3, 0xf209,
+	0xf7c8, 0xe41e, 0x0803, 0xcbe0, 0xf7f8, 0x2848, 0xe41a, 0x0819,
+	0xe41e, 0x081d, 0xcba0, 0xcba3, 0xf139, 0xf7d8, 0xd185, 0x0001,
+	0xd184, 0x0004, 0xe41e, 0x082a, 0xcb06, 0x3446, 0x3c47, 0x2871,
+	0x4c72, 0xe42a, 0x2879, 0x1877, 0xe414, 0x0b3f, 0xe42e, 0xd1d0,
+	0x0000, 0xd1d1, 0x0000, 0xcb0c, 0xf7f8, 0xcbe0, 0xf7f8, 0xe16b,
+	0xe42e, 0xd184, 0x0002, 0xd185, 0x0000, 0x882b, 0x01ca, 0xd1c4,
+	0x0000, 0xd1c2, 0x0001, 0xd1c5, 0x0000, 0xd1d0, 0x000e, 0xcba0,
+	0xf7f8, 0x2456, 0x4c57, 0xf058, 0xd1c2, 0x0000, 0xd1c5, 0x0003,
+	0xd1d0, 0x0030, 0xe41e, 0x0803, 0xa200, 0xe0c2, 0x012a, 0xcbe0,
+	0xf7f8, 0x2848, 0xe41a, 0x0819, 0xe41e, 0x081d, 0xcba0, 0xf7f8,
+	0xd185, 0x0001, 0xd184, 0x0004, 0xe41e, 0x082a, 0xcb06, 0x3446,
+	0x3c47, 0x2871, 0x4c72, 0xe42a, 0x2879, 0x1877, 0xe414, 0x0b3f,
+	0xe42e, 0xa200, 0x3c10, 0xe16a, 0xba7e, 0x3418, 0x3c19, 0xe004,
+	0x5649, 0xae20, 0xe00a, 0x444f, 0xa201, 0x3ef0, 0xba7f, 0xe046,
+	0xf108, 0xe004, 0x2000, 0x3c33, 0xe41e, 0x0620, 0xf0ad, 0xe41e,
+	0x068a, 0x2822, 0x3c13, 0x3c36, 0x2823, 0x3c14, 0x3c37, 0xe42e,
+	0xe16b, 0xe42e, 0xba7e, 0x3420, 0x3c21, 0xa108, 0xa209, 0x3ef0,
+	0xf326, 0xba7e, 0xe190, 0xba5e, 0xe190, 0xba5e, 0xe190, 0xba7e,
+	0xe190, 0xba7e, 0xa20b, 0x3ef0, 0xf266, 0xe002, 0x0100, 0xa20d,
+	0x3ef0, 0xf210, 0xe000, 0x0100, 0x3c24, 0xe161, 0x0360, 0x2824,
+	0xa102, 0xcc44, 0xe184, 0x05ad, 0xba7e, 0xe190, 0xf14a, 0xba7e,
+	0x3511, 0x3d11, 0x1420, 0x1c21, 0xf0e0, 0xe190, 0xd039, 0x0000,
+	0xa200, 0x3c25, 0xa20f, 0x3ef0, 0xe41e, 0x05be, 0xf04d, 0xa200,
+	0x3cf0, 0xe42e, 0xd039, 0x0000, 0xe16b, 0xe42e, 0xa211, 0x3ef0,
+	0xba40, 0xf2f8, 0x7410, 0xf2d8, 0x7410, 0xf2b8, 0xba42, 0xa102,
+	0xb608, 0x3c29, 0x7410, 0xe190, 0xba48, 0x3c2b, 0x2810, 0xe016,
+	0xf0aa, 0xba40, 0xa215, 0x3ef0, 0xf1c8, 0xa217, 0x3ef0, 0xba40,
+	0xf188, 0xba42, 0x3c2a, 0xba40, 0x3c2e, 0xba58, 0x3c2f, 0xe41e,
+	0x06ab, 0xe086, 0x3c22, 0xe088, 0x3c23, 0xe41e, 0x068a, 0xa219,
+	0x3ef0, 0x7444, 0x3c45, 0xf058, 0x1842, 0xf030, 0x7410, 0xe42e,
+	0xe16b, 0xe42e, 0xba40, 0xf2b8, 0x7410, 0xf298, 0x7410, 0xf278,
+	0xba42, 0xa102, 0xb608, 0x1829, 0xf228, 0x7410, 0xe190, 0xba48,
+	0x3c2b, 0x2810, 0xe016, 0xf06a, 0xba40, 0xf198, 0xba40, 0xf178,
+	0xba42, 0x3c2a, 0xba40, 0x182e, 0xf128, 0xba58, 0x182f, 0xf0f8,
+	0xe41e, 0x06ab, 0xe086, 0x1822, 0xf0a8, 0xe088, 0x1823, 0xf078,
+	0x7444, 0x3c45, 0x1842, 0xf032, 0x7410, 0xe42e, 0xe16b, 0xe42e,
+	0xba1e, 0xe002, 0x5256, 0xe016, 0xa203, 0x3ef0, 0xe40a, 0x0688,
+	0xba5e, 0xba1e, 0xe002, 0x3430, 0xf0aa, 0xba1e, 0xe002, 0x3330,
+	0xe016, 0xa205, 0x3ef0, 0xe40a, 0x0688, 0xa202, 0x3c10, 0xba5e,
+	0xe190, 0xba5e, 0x3c22, 0xba5e, 0x3c23, 0xba5e, 0xe190, 0xba5e,
+	0xe190, 0xba5e, 0xe190, 0xba4e, 0xe190, 0xba5e, 0x3c12, 0xba4e,
+	0xe004, 0x0100, 0x3c11, 0xba7e, 0xe190, 0xba7e, 0xaf18, 0xa81e,
+	0xa10a, 0xa213, 0xf026, 0xa003, 0x3615, 0x3e16, 0x2810, 0xf098,
+	0x2018, 0x4c19, 0xa144, 0xf2b6, 0xba4f, 0xa102, 0xf28a, 0xf7de,
+	0xa211, 0x3615, 0x3e16, 0xa207, 0x3ef0, 0xa200, 0x3c17, 0xe161,
+	0x0330, 0x2822, 0x3d11, 0x2823, 0x3d11, 0x2018, 0x4c19, 0xa144,
+	0xf166, 0xba4f, 0xae05, 0x3f11, 0xba4f, 0xae05, 0x3f11, 0x2a17,
+	0xa003, 0x3e17, 0xa111, 0xf0d3, 0xa104, 0xf740, 0x2817, 0xa002,
+	0x3c17, 0x2817, 0xa002, 0xaf02, 0xa506, 0x3c17, 0xe16a, 0xe42e,
+	0xe16b, 0xe42e, 0x2822, 0xa01e, 0xaf08, 0x3c40, 0x2823, 0xa01e,
+	0xaf08, 0x3c41, 0x8440, 0x8241, 0xe018, 0x3c42, 0xa160, 0xa20d,
+	0xf116, 0xa166, 0xf0e6, 0xe002, 0x0129, 0xf0a6, 0xe002, 0x04a4,
+	0xf066, 0xe002, 0x1290, 0xf026, 0xa003, 0xa005, 0xa005, 0xa005,
+	0xa003, 0x3e44, 0xe42e, 0x2810, 0xf0da, 0x2817, 0xf0fa, 0x7417,
+	0xae02, 0xe000, 0x0330, 0xe092, 0x2911, 0xe096, 0x2911, 0xe098,
+	0xe42e, 0x2829, 0xf08a, 0xba40, 0xf06a, 0x2822, 0xe096, 0x2823,
+	0xe098, 0xe42e, 0xe005, 0x00a0, 0xba44, 0xf1ca, 0xa102, 0xf19a,
+	0xa102, 0xf16a, 0xa102, 0xf13a, 0xa102, 0xf10a, 0xa102, 0xf0ca,
+	0xa102, 0xf09a, 0xa201, 0xba4e, 0xe041, 0xe002, 0x00ff, 0xf7ca,
+	0xae05, 0xf08e, 0xa081, 0xe001, 0x0120, 0xa041, 0xa0a1, 0xa081,
+	0xa021, 0xe097, 0xe005, 0x0078, 0xba44, 0xf27a, 0xa102, 0xf24a,
+	0xa102, 0xf21a, 0xa102, 0xf1ea, 0xa102, 0xf1ba, 0xa102, 0xf17a,
+	0xa102, 0xba41, 0xf088, 0xf049, 0xe005, 0x00b4, 0xf16e, 0xe005,
+	0x0168, 0xf13e, 0xf049, 0xe005, 0x0240, 0xf0fe, 0xa201, 0xba4e,
+	0xe041, 0xe002, 0x00ff, 0xf7ca, 0xae05, 0xf07e, 0xe001, 0x00c0,
+	0xa061, 0xa0c1, 0xa019, 0xa019, 0xe099, 0xe42e, 0xd130, 0x0004,
+	0xd131, 0x0000, 0xd008, 0x0000, 0xd03a, 0x0004, 0xd1e0, 0x0001,
+	0xd1e1, 0x03b0, 0xd1f3, 0x0040, 0xd022, 0x00bf, 0xe184, 0x0721,
+	0xa200, 0xcfe8, 0xe42e, 0x2829, 0xae02, 0x4c10, 0xcf80, 0xcfc6,
+	0xd1d3, 0x000b, 0x2840, 0xa102, 0xae04, 0x4c29, 0xae02, 0x4c10,
+	0xcf00, 0x282e, 0xa200, 0xcf02, 0xd184, 0x0001, 0x2840, 0xae20,
+	0x4c41, 0xae08, 0xcfc4, 0xe167, 0x02c0, 0x2117, 0x4d17, 0xcfca,
+	0x2834, 0xcfce, 0xd1e6, 0x0000, 0xe42e, 0xe42e, 0x2810, 0xae08,
+	0xa908, 0xe0c2, 0x0100, 0xa200, 0xe0c2, 0x0128, 0xa200, 0xe0c2,
+	0x013d, 0x2a71, 0x4e72, 0xb692, 0xae08, 0xa91c, 0xe0c2, 0x017c,
+	0xa218, 0xe0c2, 0x017d, 0xa200, 0xe41e, 0x0a5e, 0xe0c2, 0x0102,
+	0xe42e, 0xe41e, 0x0274, 0xa202, 0xe0c2, 0x0106, 0xe42e, 0xa200,
+	0xcc8e, 0xe0c2, 0x0128, 0x2810, 0xae08, 0xa908, 0xe0c2, 0x0100,
+	0x2a71, 0x4e72, 0xb692, 0xae08, 0xa91c, 0xe0c2, 0x017c, 0xe004,
+	0x000c, 0xe0c2, 0x017d, 0xa208, 0xae04, 0x4c10, 0xae04, 0x4c29,
+	0xae06, 0xe0c2, 0x0204, 0xa200, 0xe0c2, 0x0208, 0x2829, 0xae06,
+	0xe0c2, 0x0104, 0xe0c1, 0x0046, 0xe004, 0x0000, 0xae10, 0xe042,
+	0x2ac8, 0xa803, 0xf05b, 0xe161, 0x0700, 0x2111, 0x4d11, 0xcfc8,
+	0xe0c1, 0x0046, 0xe004, 0x0040, 0xae10, 0xe042, 0x2ac8, 0xa805,
+	0xf05b, 0xe161, 0x0702, 0x2111, 0x4d11, 0xe0c2, 0x0103, 0x282e,
+	0xe016, 0xe0c2, 0x0210, 0xa200, 0xe41e, 0x0a5e, 0xa203, 0xae11,
+	0xe056, 0xe0c2, 0x0213, 0xa200, 0xe0c2, 0x0215, 0xe0c1, 0x0046,
+	0xe004, 0x0070, 0xae10, 0xe042, 0x2ac8, 0xa809, 0xf05b, 0xe161,
+	0x0704, 0x2111, 0x4d11, 0xe0c2, 0x0211, 0xe0c1, 0x0046, 0xe004,
+	0x0070, 0xe000, 0x0040, 0xae10, 0xe042, 0x2ac8, 0xa811, 0xf05b,
+	0xe161, 0x0706, 0x2111, 0x4d11, 0xe0c2, 0x0212, 0x2840, 0xae20,
+	0x4c41, 0xae08, 0xe0c2, 0x0101, 0xe0c2, 0x0205, 0xa200, 0xe41e,
+	0x0a5e, 0xe0c2, 0x0102, 0xa200, 0xae0a, 0x4c2d, 0xe0c2, 0x0217,
+	0xe41e, 0x0831, 0xe41e, 0x0836, 0xa20e, 0xe0c2, 0x0312, 0xe0c0,
+	0x0414, 0xe418, 0x018c, 0xe0c0, 0x0414, 0xe41a, 0x0862, 0xa200,
+	0xe0c2, 0x030d, 0x2035, 0x4c34, 0xe0c2, 0x0310, 0xe42e, 0xe0c0,
+	0x0111, 0xf7e8, 0xe42e, 0xcb94, 0xe0c2, 0x0115, 0xcba4, 0xe0c2,
+	0x012a, 0xcb8a, 0xe0c2, 0x0114, 0xa802, 0x3c48, 0xe42a, 0xcb12,
+	0xe0c2, 0x0120, 0xcb8c, 0xe0c2, 0x0121, 0xcb8e, 0xe0c2, 0x0122,
+	0xe42e, 0xcbd0, 0xe0c2, 0x0311, 0xe42e, 0xcb40, 0xe0c2, 0x0224,
+	0xcb42, 0xe0c2, 0x0225, 0xcb44, 0xe0c2, 0x0226, 0xcb46, 0xe0c2,
+	0x0227, 0xe42e, 0xe0c0, 0x0111, 0xf7e8, 0xa202, 0xe0c2, 0x0110,
+	0xe42e, 0x2852, 0xe0c2, 0x020b, 0xe0c2, 0x0214, 0xa200, 0xe0c2,
+	0x030a, 0xe004, 0x0082, 0xa202, 0xae20, 0xe00a, 0x0842, 0xe0c2,
+	0x030b, 0xa202, 0xe0c2, 0x0302, 0x2829, 0xa104, 0xf082, 0x285b,
+	0xf032, 0x2852, 0xb608, 0xe0c2, 0x0380, 0xf09e, 0x285a, 0xf052,
+	0x285b, 0xf032, 0x2852, 0xb608, 0xe0c2, 0x0380, 0x285b, 0xf052,
+	0x285a, 0xf032, 0x2852, 0xb608, 0xe0c2, 0x0383, 0xa200, 0xe0c2,
+	0x0302, 0xe42e, 0xe167, 0x01a0, 0x2317, 0x4f17, 0xe0c3, 0x0152,
+	0x2b17, 0xe009, 0x00ff, 0xae21, 0x4f07, 0xe0c3, 0x0153, 0xe0c1,
+	0x0101, 0xe0c3, 0x015d, 0x2829, 0xa104, 0xe005, 0x001b, 0xf038,
+	0xe005, 0x001f, 0x3e00, 0x285a, 0xa53e, 0xa400, 0x2a5b, 0xa53f,
+	0xa401, 0xae11, 0xe055, 0xae21, 0xe167, 0x01a2, 0x2907, 0xaf10,
+	0x4400, 0xe055, 0xe0c3, 0x015c, 0xa202, 0xe0c2, 0x0150, 0xe0c0,
+	0x0150, 0xf7ea, 0xa200, 0xe0c2, 0x0150, 0xe0c0, 0x0151, 0xf7e8,
+	0xe42e, 0xa2fa, 0x3c5a, 0x3c5b, 0xa2fe, 0x3c53, 0xa200, 0x3c54,
+	0x3c55, 0x3c58, 0x3c59, 0x3c57, 0x3c56, 0xa202, 0x285d, 0xe0c0,
+	0x0061, 0x3c50, 0xe41e, 0x0414, 0xe0c0, 0x0042, 0xce20, 0xd111,
+	0x0200, 0xd112, 0x00c4, 0xd113, 0x0003, 0xe41e, 0x0414, 0xe0c0,
+	0x0060, 0x3c51, 0xa202, 0xe42e, 0xa2fc, 0x3c52, 0xa2fa, 0x3c5c,
+	0xe0c0, 0x0054, 0x2654, 0x4e55, 0xe052, 0x3c55, 0x3454, 0xe41e,
+	0x08ca, 0xe42e, 0xa200, 0x3c5e, 0x2851, 0xa102, 0xcc44, 0xe184,
+	0x08e1, 0x2454, 0x4c55, 0x5c5e, 0xa802, 0xf0a8, 0x285e, 0xe049,
+	0xe001, 0x02d0, 0xe09f, 0x2b07, 0xa809, 0xe419, 0x0951, 0x285e,
+	0xa002, 0x3c5e, 0xe42e, 0xe004, 0x02d0, 0xe09e, 0x2851, 0xa102,
+	0xcc44, 0xa200, 0x3c5e, 0xe184, 0x08f4, 0x2b17, 0xaf05, 0xa803,
+	0x5a5e, 0xe056, 0x2a5e, 0xa003, 0x3e5e, 0x3454, 0x3c55, 0xe42e,
+	0x2853, 0xb7e8, 0xe094, 0xe092, 0xe084, 0xa002, 0x2a51, 0xe045,
+	0xb616, 0x3c52, 0xe094, 0xe083, 0xe045, 0xf059, 0xa2fe, 0x3c52,
+	0xa200, 0xe42e, 0x3c53, 0xe000, 0x02d0, 0xe09e, 0x2907, 0xf6d8,
+	0xa20a, 0x3d07, 0xa202, 0xe42e, 0x2852, 0xf114, 0x2829, 0xf0f4,
+	0xa104, 0xf0d2, 0x285a, 0xe41e, 0x0946, 0x285b, 0x3c5a, 0x2852,
+	0x3c5b, 0x2456, 0x4c57, 0xa002, 0x3c57, 0x3456, 0xe42e, 0x2a5d,
+	0xb630, 0xe045, 0x3e5d, 0xf098, 0xa2fa, 0x3c5c, 0x2852, 0xe424,
+	0x2829, 0xe424, 0xa104, 0xf062, 0x2a5d, 0x285b, 0xb7ea, 0x3c5c,
+	0xe42e, 0x2852, 0x3c5c, 0xe41e, 0x0946, 0xe42e, 0xe167, 0x02d0,
+	0xa200, 0xc71f, 0x3d17, 0xa202, 0x3c5d, 0xe42e, 0xe424, 0xe049,
+	0x1a51, 0xe423, 0xe000, 0x02d0, 0xe09e, 0x2907, 0xa808, 0x3d07,
+	0xe42e, 0xe000, 0x02d0, 0xe09e, 0x2907, 0xa802, 0x3d07, 0xe42e,
+	0xe000, 0x02d0, 0xe09e, 0xa208, 0x4d07, 0x3d07, 0xe42e, 0xe0c0,
+	0x0059, 0xa102, 0xf20a, 0xa102, 0xe42a, 0xa102, 0xf04a, 0xa102,
+	0xf24a, 0xe42e, 0xe0c0, 0x0060, 0xaf08, 0x3071, 0xaf02, 0x3072,
+	0xe0c0, 0x0060, 0xa81e, 0x3c70, 0xe0c0, 0x0061, 0xa83e, 0x3c74,
+	0xe0c1, 0x0065, 0xa809, 0xe0c0, 0x0065, 0xaf06, 0xa806, 0xb632,
+	0x3c60, 0xe42e, 0xe0c0, 0x0060, 0x34b0, 0x3cb1, 0xe0c0, 0x0061,
+	0xae14, 0x34b2, 0x3cb3, 0xe42e, 0xe42e, 0xe0c0, 0x0059, 0xa102,
+	0xe40a, 0x09d4, 0xa102, 0xe42a, 0xa102, 0xf05a, 0xa102, 0xe40a,
+	0x09fc, 0xe42e, 0x2022, 0x4c23, 0xe0c2, 0x006f, 0x2456, 0x4c57,
+	0xe0c2, 0x0070, 0x285c, 0xe0c2, 0x0071, 0x244a, 0x4c4b, 0xe0c2,
+	0x0072, 0x2829, 0xe0c2, 0x0073, 0xa200, 0xe0c2, 0x0074, 0x281f,
+	0xe0c2, 0x0076, 0x2852, 0x2ac1, 0xb7d2, 0xe0c2, 0x0077, 0xa200,
+	0xe0c2, 0x0078, 0xe0c2, 0x0079, 0x282f, 0xe0c2, 0x007a, 0xa2fe,
+	0xe0c2, 0x007c, 0x2811, 0xe0c2, 0x007e, 0x2812, 0xe0c2, 0x007d,
+	0x2454, 0x4c55, 0xe0c2, 0x0054, 0xc84a, 0xc84d, 0xae20, 0xe056,
+	0xe0c2, 0x0053, 0xa202, 0xe42e, 0xa202, 0xe0c2, 0x0074, 0xa200,
+	0xe0c2, 0x0076, 0xe0c2, 0x0077, 0xa202, 0x2af0, 0xb616, 0x58f0,
+	0xe0c2, 0x0078, 0x2811, 0xe0c2, 0x007a, 0x2812, 0xe0c2, 0x0079,
+	0xa2fe, 0xe0c2, 0x0072, 0xe0c2, 0x006d, 0xa208, 0xe0c2, 0x0073,
+	0x2013, 0x4c14, 0xe0c2, 0x0071, 0x2015, 0x4c16, 0xe0c2, 0x007b,
+	0x281f, 0xe0c2, 0x0070, 0xe42e, 0xe42e, 0xe0c0, 0x0041, 0xe005,
+	0x0020, 0xae11, 0xe042, 0xe41e, 0x0a1a, 0xe42e, 0xe41e, 0x0174,
+	0xe167, 0x0700, 0xe166, 0x0064, 0xd022, 0x0003, 0xe184, 0x0a12,
+	0x9e16, 0x3517, 0x3d17, 0xe42e, 0xe0c0, 0x0050, 0xe008, 0x007f,
+	0x3cc8, 0xe42e, 0xa00e, 0xaf06, 0xae06, 0xe42e, 0xe41e, 0x0a7e,
+	0xe41e, 0x0ab1, 0xe41e, 0x025f, 0xe41e, 0x0a49, 0xa202, 0xe42e,
+	0x2852, 0xf1f4, 0xa203, 0xe0c3, 0x040d, 0xcca4, 0xc785, 0xe019,
+	0xe001, 0x0500, 0xe09f, 0xe0c1, 0x0420, 0xa803, 0xf7db, 0xa200,
+	0xe41e, 0x0a5e, 0xaf04, 0xe41e, 0x0a67, 0xae20, 0x2e50, 0xe056,
+	0x9f17, 0x2040, 0x4c41, 0xae08, 0x9f17, 0xa201, 0xe0c3, 0x040d,
+	0xe42e, 0xa200, 0x2ac8, 0xa803, 0xf03b, 0xe00a, 0x0002, 0x2ac8,
+	0xa805, 0xf02b, 0xa912, 0x2ac8, 0xa809, 0xf02b, 0xa940, 0x2ac8,
+	0xa811, 0xf02b, 0xa980, 0xe0c2, 0x040c, 0xe42e, 0xe0c1, 0x0044,
+	0xa80f, 0xe056, 0xe42e, 0xa200, 0xe41e, 0x0a5e, 0xe42e, 0xe0c1,
+	0x0044, 0xaf0d, 0xae03, 0xe056, 0xe008, 0x003f, 0xe42e, 0xe0c1,
+	0x0044, 0xaf17, 0xa803, 0xe42e, 0xe0c1, 0x0044, 0xaf17, 0xa803,
+	0xa105, 0xf039, 0xa213, 0xe42e, 0xa201, 0xe42e, 0xa203, 0xe0c3,
+	0x040d, 0xe0c1, 0x0420, 0xa803, 0xf7db, 0xe160, 0x0003, 0xe166,
+	0x0200, 0xe167, 0x0500, 0x2851, 0xf166, 0xa102, 0xcc44, 0xe184,
+	0x0aa1, 0xa200, 0xe41e, 0x0a5e, 0xaf04, 0xe41e, 0x0a67, 0xae20,
+	0x2e50, 0xe056, 0x9f17, 0x2040, 0x4c41, 0xae08, 0x9f17, 0xe41e,
+	0x0aa7, 0xe190, 0xe190, 0xa201, 0xe0c3, 0x040d, 0xe42e, 0x2116,
+	0x4d16, 0x9f17, 0x2116, 0x4d16, 0x9f17, 0x2116, 0x4d16, 0x9f17,
+	0xe42e, 0xe0c0, 0x0044, 0xaf20, 0xa802, 0xe428, 0xe0c0, 0x0060,
+	0xa860, 0xe42a, 0xe0c0, 0x0061, 0xa83e, 0xa203, 0xe0c3, 0x040d,
+	0xcca4, 0xc785, 0xe018, 0xe000, 0x0500, 0xe09e, 0xe0c1, 0x0420,
+	0xa803, 0xf7db, 0xa200, 0xe41e, 0x0a63, 0xa80e, 0xaf04, 0xe41e,
+	0x0a67, 0xe41e, 0x0a6f, 0xe40b, 0x0ada, 0xa81e, 0xe41e, 0x0a74,
+	0xae09, 0xe056, 0xae20, 0xe0c1, 0x006e, 0xe009, 0x1fff, 0xe056,
+	0x9f17, 0xe0c0, 0x0060, 0xa822, 0xa122, 0xf04a, 0x2040, 0x4c41,
+	0xf03e, 0x2041, 0x4c40, 0xae08, 0x9f17, 0xe0c0, 0x0062, 0x9f17,
+	0xe0c0, 0x0063, 0x9f17, 0xe0c0, 0x0064, 0x9f17, 0xa201, 0xe0c3,
+	0x040d, 0xe42e, 0x3cec, 0xe0c0, 0x0041, 0xe005, 0x0020, 0xae11,
+	0xe042, 0xce20, 0xd111, 0x0200, 0xd112, 0x00c0, 0x88ec, 0x0113,
+	0xca29, 0xf7f9, 0xe190, 0xe42e, 0xa2fe, 0x3c73, 0xa200, 0x3c71,
+	0xe42e, 0x285f, 0x3c73, 0x2873, 0xf032, 0xa200, 0x3c71, 0xa200,
+	0x3c78, 0x3c79, 0x2840, 0x3c76, 0x2841, 0x3c77, 0x2871, 0xe42a,
+	0x2873, 0xe424, 0x2873, 0xe0c2, 0x0143, 0x2874, 0xe0c2, 0x0144,
+	0xa200, 0xe0c2, 0x017f, 0xe0c2, 0x0149, 0xe41e, 0x0a5e, 0xe0c2,
+	0x017f, 0x2876, 0xa102, 0xae20, 0x4c77, 0xa102, 0xe0c2, 0x0142,
+	0xa200, 0xae20, 0x2a70, 0xe042, 0xe0c2, 0x014e, 0xe42e, 0x2873,
+	0x2a79, 0x1a77, 0xe423, 0x2878, 0xae0e, 0x4c79, 0xa203, 0xb615,
+	0x3e7a, 0x2a7a, 0xae03, 0xa903, 0xae1d, 0xe056, 0xe0c1, 0x014b,
+	0xf7e9, 0xe0c2, 0x014d, 0xa202, 0xe0c2, 0x014a, 0x2a78, 0xa003,
+	0x3e78, 0x1a76, 0xf065, 0x2a79, 0xa003, 0x3e79, 0xa201, 0x3e78,
+	0xe42e, 0x2871, 0xf15a, 0x2879, 0x1877, 0xf042, 0xe41e, 0x0b3f,
+	0xf7be, 0xe0c0, 0x014b, 0xf7e8, 0xa204, 0xae1c, 0xe0c2, 0x014d,
+	0xa202, 0xe0c2, 0x014a, 0xe190, 0xe0c0, 0x014b, 0xf7e8, 0x285c,
+	0x3c73, 0xe42e, 0xe42e, 0xe42e, 0xe42e, 0xe42e, 0xe42e, 0xe42e,
+	0xe42e, 0xe0c0, 0x0059, 0xa102, 0xe40a, 0x0b8e, 0xa102, 0xe40a,
+	0x0bb0, 0xa102, 0xe40a, 0x0b96, 0xe40e, 0x0bb0, 0xe41e, 0x023a,
+	0x24b0, 0x4cb1, 0x04b2, 0x0cb3, 0x34b4, 0x3cb5, 0xa206, 0xae1e,
+	0xcec0, 0xd160, 0x0600, 0xe0c0, 0x0048, 0xe0c2, 0x0051, 0x34ba,
+	0x3cbb, 0x34b6, 0xe008, 0xfe00, 0x3cb7, 0x2cbb, 0xe008, 0x01ff,
+	0x3cbc, 0xe41e, 0x0cd0, 0xf07d, 0xe41e, 0x0bf8, 0xe41e, 0x0be3,
+	0xa202, 0xe42e, 0xa200, 0xe16a, 0xe42e, 0xe41e, 0x0bb8, 0xe470,
+	0xca28, 0xf7f8, 0xe004, 0x0080, 0xce24, 0x28bf, 0xae0e, 0xce22,
+	0x24b6, 0x4cb7, 0xce20, 0xe0c0, 0x0043, 0xa806, 0xae02, 0xa022,
+	0xce26, 0xca28, 0xf7f8, 0x24b6, 0x4cb7, 0xe000, 0x0200, 0x34b6,
+	0x3cb7, 0x14b4, 0x1cb5, 0xf054, 0x24b0, 0x4cb1, 0x34b6, 0x3cb7,
+	0xd04c, 0x0000, 0x28bf, 0xae0e, 0xcc6e, 0x28bf, 0xe016, 0x3cbf,
+	0xe42e, 0x28c1, 0xe42e, 0xa200, 0x3cbf, 0xce92, 0xe41e, 0x0bb8,
+	0xe41e, 0x0bb8, 0xe128, 0xd071, 0x2020, 0xe181, 0x2cbc, 0xa102,
+	0xf074, 0xcc44, 0xe184, 0x0bf5, 0xba4e, 0xe190, 0xe190, 0xe42e,
+	0xe004, 0x1495, 0xae20, 0xcc9e, 0xd030, 0x0000, 0xd034, 0x0000,
+	0xd033, 0x0000, 0xd035, 0x0000, 0xd036, 0x00ff, 0xd037, 0x0000,
+	0xd038, 0x0000, 0xd039, 0x0000, 0xd04b, 0x0001, 0xd04c, 0x0000,
+	0xd046, 0x0000, 0xd047, 0x0000, 0xd149, 0x0000, 0xe42e, 0xe0c0,
+	0x0059, 0xa102, 0xe40a, 0x0c22, 0xa102, 0xe42a, 0xa102, 0xe40a,
+	0x0c22, 0xe42a, 0x24c5, 0x4cc6, 0x04ba, 0x0cbb, 0x34ba, 0x3cbb,
+	0x14b4, 0x1cb5, 0xf074, 0x24ba, 0x4cbb, 0x14b2, 0x1cb3, 0x34ba,
+	0x3cbb, 0x24ba, 0x4cbb, 0xe0c2, 0x0048, 0xe0c2, 0x0052, 0xe42e,
+	0xa200, 0x34c5, 0x3cc6, 0xe42e, 0xf0a8, 0x2911, 0xe008, 0xffff,
+	0xae20, 0x2b11, 0xe009, 0xffff, 0xe042, 0xf0fe, 0x2911, 0xe008,
+	0x00ff, 0xae20, 0x2b11, 0xe009, 0xffff, 0xe042, 0xae10, 0x2b11,
+	0xe009, 0xff00, 0xaf11, 0xe042, 0x2ac7, 0xe42b, 0xe049, 0xaf31,
+	0xe009, 0x00ff, 0xe093, 0xe049, 0xaf21, 0xe009, 0x00ff, 0xe095,
+	0xe049, 0xaf11, 0xe009, 0x00ff, 0xe008, 0x00ff, 0xae10, 0xe056,
+	0xae10, 0xe085, 0xe056, 0xae10, 0xe083, 0xe056, 0xe42e, 0xe049,
+	0xa80f, 0xe046, 0xe42e, 0xca29, 0xf7f9, 0xd111, 0x0600, 0xce20,
+	0x26b4, 0x4eb5, 0xe045, 0xe004, 0x0040, 0xe065, 0xaf03, 0xce25,
+	0x3ec0, 0xe41e, 0x0c91, 0xa240, 0x18c0, 0xe426, 0xce24, 0x28c0,
+	0xe000, 0x0600, 0xce22, 0x24b0, 0x4cb1, 0xce20, 0xe41e, 0x0c91,
+	0xe42e, 0xe0c0, 0x0043, 0xa806, 0xae02, 0xa002, 0xce26, 0xca28,
+	0xf7f8, 0xe42e, 0x34c9, 0x3cca, 0xa200, 0x3cbd, 0xe0c0, 0x0049,
+	0x34cb, 0x3ccc, 0xe0c0, 0x0045, 0xaf04, 0x30be, 0xe0c0, 0x0049,
+	0x34b8, 0x3cb9, 0x10cb, 0x1ccc, 0x2abd, 0xb611, 0x3ebd, 0x26b8,
+	0x4eb9, 0x16c9, 0x1eca, 0xf033, 0x06b2, 0x0eb3, 0x16c3, 0x1ec4,
+	0xa200, 0xe423, 0x28be, 0x3cc1, 0xe428, 0x28bd, 0xf648, 0xe41e,
+	0x01db, 0xe0c0, 0x005c, 0xe008, 0x4000, 0xf5da, 0xe0c0, 0x005d,
+	0xe00a, 0x4000, 0xe0c2, 0x005d, 0xa202, 0xce00, 0x3cbd, 0xf53e,
+	0xe0c0, 0x0059, 0xa102, 0xe40a, 0x0cdb, 0xa102, 0xe42a, 0xa102,
+	0xe40a, 0x0d05, 0xe42e, 0xa200, 0x3cc7, 0xa244, 0x34c3, 0x3cc4,
+	0x24ba, 0x4cbb, 0xd027, 0x0000, 0xe41e, 0x0c9a, 0xd027, 0x0001,
+	0xe408, 0x0d03, 0x24ba, 0x4cbb, 0xe41e, 0x0c6f, 0xe095, 0xe41e,
+	0x0c73, 0xe084, 0xaf02, 0xe000, 0x0600, 0xe092, 0xe084, 0xa802,
+	0xe41e, 0x0c3c, 0xe008, 0xffff, 0x34c5, 0x3cc6, 0xa144, 0xf034,
+	0xa200, 0xe42e, 0xe16b, 0xa202, 0xe42e, 0xa228, 0x34c3, 0x3cc4,
+	0x24ba, 0x4cbb, 0xd027, 0x0000, 0xe41e, 0x0c9a, 0xd027, 0x0001,
+	0xe408, 0x0d50, 0x24ba, 0x4cbb, 0xe41e, 0x0c6f, 0xe095, 0xe41e,
+	0x0c73, 0xe084, 0xaf02, 0xe000, 0x0600, 0xe092, 0xe41e, 0x0d55,
+	0xe084, 0xa802, 0xe41e, 0x0c3c, 0x00c5, 0x0cc6, 0x34c5, 0x3cc6,
+	0xf286, 0x26b2, 0x4eb3, 0xe046, 0xf242, 0xe084, 0xa020, 0x001b,
+	0x0c1c, 0xaf02, 0xe000, 0x0600, 0xe092, 0xe084, 0xa802, 0xe41e,
+	0x0c3c, 0x3c24, 0xf154, 0x2824, 0xae06, 0xa028, 0x04c5, 0x0cc6,
+	0x34c5, 0x3cc6, 0x34c3, 0x3cc4, 0x24ba, 0x4cbb, 0xd027, 0x0000,
+	0xe41e, 0x0c9a, 0xd027, 0x0001, 0xf048, 0xa200, 0xe42e, 0xe16b,
+	0xa200, 0x34c5, 0x3cc6, 0xa202, 0xe42e, 0x2111, 0x4d11, 0x341b,
+	0x3c1c, 0x2111, 0x4d11, 0xe160, 0x0004, 0x8129, 0xe005, 0x5649,
+	0xae21, 0xe00b, 0x444f, 0xe046, 0xf08a, 0xa200, 0x3c1a, 0x341b,
+	0x3c1c, 0x34c5, 0x3cc6, 0xe42e, 0x221b, 0x4e1c, 0x36c5, 0x3ec6,
+	0xaf03, 0xe082, 0xe042, 0xe092, 0xa202, 0x3c1a, 0xe42e, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
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+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe40e, 0x0020, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x0330, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x034a, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x003a, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058,
+	0xa200, 0xe0c2, 0x005a, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xa2fe,
+	0x3cee, 0x3cef, 0x3cec, 0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d,
+	0xce00, 0xf33e, 0xe41e, 0x0164, 0xe09e, 0xa202, 0xae3e, 0x9f07,
+	0xe0c0, 0x005c, 0xe0c1, 0x0059, 0x3eed, 0xa203, 0x5aed, 0xe052,
+	0xf08a, 0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00,
+	0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2, 0x0008, 0xf00e,
+	0x28ee, 0xe412, 0x013d, 0xe190, 0xe0c0, 0x005c, 0xe0c1, 0x0059,
+	0x3eed, 0xa203, 0x5aed, 0xe052, 0xf08a, 0xe0c1, 0x005d, 0xe055,
+	0xe0c3, 0x005d, 0xa202, 0xce00, 0xe0c0, 0x004a, 0xf08a, 0xe41e,
+	0x019c, 0xe408, 0x005c, 0xe40e, 0x0058, 0xe190, 0xe0c0, 0x043d,
+	0xa1ee, 0xf7d8, 0xe004, 0x0060, 0xe0c2, 0x0009, 0xa200, 0xe0c2,
+	0x0009, 0xe0c0, 0x000d, 0xf7e8, 0xe41e, 0x00b2, 0xe41e, 0x00e2,
+	0xe41e, 0x012c, 0xd071, 0x242a, 0xe181, 0xe41e, 0x0164, 0xe09e,
+	0xa202, 0x9f07, 0xe0c0, 0x0049, 0xe0c1, 0x005b, 0xa111, 0xf033,
+	0xe0c0, 0x0048, 0xe0c2, 0x0047, 0xe0c0, 0x0059, 0xae02, 0xe000,
+	0x0330, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a, 0xe008, 0xffff,
+	0x3cee, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11, 0xe056, 0x3cef,
+	0xe40e, 0x0058, 0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2,
+	0x0008, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xe0c0, 0x0059, 0xf7ea,
+	0xa11e, 0xf198, 0xa202, 0xe0c2, 0x0058, 0xe004, 0xca20, 0xae20,
+	0xe005, 0x210a, 0xe056, 0xe0c2, 0x0070, 0xe004, 0x0000, 0xae20,
+	0xe00a, 0x9cea, 0xe0c2, 0x0071, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+	0x0058, 0xf64e, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058, 0xd027,
+	0x0001, 0xe42e, 0xa200, 0xe0c1, 0x005b, 0xf21b, 0xa23c, 0xa103,
+	0xf37b, 0xa24c, 0xa103, 0xf34b, 0xa258, 0xa103, 0xf1db, 0xe004,
+	0x003a, 0xa103, 0xf2db, 0xe004, 0x003f, 0xa103, 0xf29b, 0xe004,
+	0x0045, 0xa103, 0xf25b, 0xa103, 0xf14b, 0xe004, 0x0063, 0xa103,
+	0xf1ab, 0xe004, 0x006a, 0xa107, 0xf1bb, 0xa200, 0xe0c1, 0x005e,
+	0xf17b, 0xa028, 0xf15e, 0xe0c1, 0x005e, 0xf12b, 0xa010, 0xf10e,
+	0xe004, 0x0049, 0xe0c1, 0x005e, 0xf0bb, 0xa010, 0xa103, 0xf08b,
+	0xa010, 0xf06e, 0xe0c1, 0x005e, 0xf03b, 0xe004, 0x0074, 0xae16,
+	0xe0c1, 0x0040, 0xe041, 0xce21, 0xd111, 0x0000, 0xd112, 0x2800,
+	0xd113, 0x000b, 0xe1e1, 0xe42e, 0xe41e, 0x023a, 0xe0c0, 0x0059,
+	0xa102, 0xe42a, 0xe0c0, 0x005b, 0xa810, 0xf058, 0xa206, 0xe41e,
+	0x0153, 0xe42e, 0xe004, 0x0350, 0xe67c, 0xe0c0, 0x005b, 0xa810,
+	0xf058, 0xa204, 0xe41e, 0x0153, 0xe42e, 0xe004, 0x0352, 0xe67c,
+	0xa200, 0xc401, 0xe188, 0x00eb, 0x3d11, 0xe161, 0x00f2, 0xe188,
+	0x0b0d, 0x3d11, 0xe42e, 0x3cec, 0xe0c0, 0x0041, 0xe005, 0x0000,
+	0xae11, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0c00, 0x88ec,
+	0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0059, 0xa106, 0xf048,
+	0xe004, 0x0076, 0xe42e, 0xe0c0, 0x0059, 0xa10c, 0xf038, 0xe004,
+	0x0071, 0xe004, 0x0070, 0xe42e, 0xe0c0, 0x006b, 0xe167, 0x01a0,
+	0x3d07, 0xe0c0, 0x0414, 0xe428, 0xe0c1, 0x0044, 0xa809, 0xae33,
+	0xe0c0, 0x006a, 0xe167, 0x01a0, 0x3517, 0x3d17, 0xe0c0, 0x006b,
+	0xe056, 0x3517, 0x3d07, 0xe42e, 0xe167, 0x01a0, 0x2907, 0xe0c2,
+	0x0151, 0xa204, 0xe0c2, 0x0150, 0xe0c0, 0x0150, 0xa804, 0xf7da,
+	0xa208, 0xe0c2, 0x0150, 0xe42e, 0xe0c0, 0x004a, 0xe42a, 0xe0c0,
+	0x005b, 0xa110, 0xf142, 0xe0c0, 0x0059, 0xa102, 0xe41a, 0x01be,
+	0xe0c0, 0x0059, 0xa106, 0xe41a, 0x01cb, 0xe0c0, 0x0047, 0xe0c2,
+	0x0048, 0xa200, 0xe0c2, 0x004a, 0xa202, 0xe42e, 0xe0c0, 0x0047,
+	0xe0c2, 0x0049, 0xa200, 0xe0c2, 0x004a, 0xe42e, 0xe0c0, 0x004a,
+	0xa802, 0xa23e, 0x3cf0, 0xa202, 0x58f0, 0xe0c2, 0x0078, 0xa220,
+	0xe0c2, 0x0070, 0xe42e, 0xe0c0, 0x004a, 0xa802, 0xa220, 0xe0c2,
+	0x0076, 0xa200, 0xe0c2, 0x0072, 0xa2fc, 0xe0c2, 0x0077, 0xa2fa,
+	0xe0c2, 0x0071, 0xe42e, 0xe0c0, 0x0045, 0xaf04, 0xa80e, 0xa104,
+	0xe428, 0xa202, 0xe0c2, 0x004a, 0xe0c0, 0x0111, 0xf7e8, 0xca28,
+	0xf7f8, 0xca48, 0xa802, 0xf7e8, 0xa208, 0xae14, 0xa102, 0xe190,
+	0xf7e2, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xe0c0, 0x041f, 0xf7e8,
+	0xa200, 0xe0c2, 0x041c, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xe004,
+	0x0078, 0xe0c2, 0x0009, 0xa200, 0xe0c2, 0x0009, 0xe0c0, 0x000d,
+	0xf7e8, 0xe42e, 0xc001, 0x3443, 0x3c42, 0xc000, 0xe42e, 0xc001,
+	0x2c43, 0x2e42, 0xc000, 0xe42a, 0x1c47, 0xf0b4, 0xe04a, 0xaf10,
+	0x1844, 0xf074, 0xe009, 0x00ff, 0x1a45, 0xf034, 0xa202, 0xe42e,
+	0xa2fe, 0xe42e, 0xe41e, 0x023a, 0xd160, 0x0620, 0xe004, 0x0019,
+	0xae18, 0xcec0, 0xe42e, 0xe41e, 0x024f, 0xe000, 0x0040, 0xce50,
+	0xa200, 0xd022, 0x00ff, 0xe184, 0x0236, 0xce52, 0xe190, 0xe41e,
+	0x0257, 0xe42e, 0xa204, 0xae22, 0xcc9e, 0xa200, 0xcc72, 0xcc8c,
+	0xcc8e, 0xe004, 0xa810, 0xae20, 0xe00a, 0x9322, 0xce4a, 0xd16f,
+	0x0003, 0xe190, 0xe190, 0xe190, 0xd16f, 0x0000, 0xe42e, 0xe004,
+	0x0030, 0xce50, 0xca50, 0xa802, 0xf7ea, 0xc000, 0xe42e, 0xe004,
+	0x0020, 0xce50, 0xe42e, 0xa200, 0xe0c2, 0x041c, 0xe42e, 0xe41e,
+	0x02bb, 0xe42a, 0xe0c0, 0x0061, 0xe008, 0x001f, 0xe00a, 0x0100,
+	0xe0c2, 0x041c, 0xe41e, 0x02f1, 0xe41e, 0x032b, 0xae12, 0xe0c2,
+	0x041e, 0xe41e, 0x031b, 0xe42e, 0xe41e, 0x02df, 0xe42a, 0xe0c0,
+	0x041f, 0xf7e8, 0xe0c0, 0x0210, 0xa804, 0xf118, 0xe0c0, 0x0215,
+	0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0216, 0xf0be, 0xe0c0, 0x0213,
+	0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0214, 0xf03e, 0xe0c0, 0x020b,
+	0xe00a, 0x0100, 0xe0c2, 0x041c, 0xe41e, 0x02f1, 0xe41e, 0x032b,
+	0xae12, 0xe0c1, 0x0210, 0xa803, 0xae15, 0xe056, 0xe0c1, 0x0204,
+	0xaf0b, 0xa87f, 0xae07, 0xe056, 0xe0c1, 0x0204, 0xa80f, 0xe056,
+	0xe0c2, 0x041e, 0xe41e, 0x031b, 0xe42e, 0xe0c0, 0x041f, 0xf7e8,
+	0xe0c0, 0x041f, 0xf7e8, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xa200,
+	0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xa203, 0xae19, 0xe052,
+	0xf1da, 0xe0c0, 0x0060, 0xaf08, 0xa806, 0xf18a, 0xe0c0, 0x0060,
+	0xa81e, 0xe016, 0xe0c1, 0x0060, 0xa821, 0xe017, 0xe056, 0xf0ea,
+	0xe0c0, 0x0044, 0xaf12, 0xa806, 0xe016, 0xe0c1, 0x0044, 0xaf17,
+	0xa803, 0xe056, 0xf03a, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xe0c0,
+	0x0044, 0xa203, 0xae19, 0xe052, 0xf0ba, 0xe41e, 0x02bb, 0xf088,
+	0xe0c0, 0x0044, 0xaf12, 0xa806, 0xf038, 0xa202, 0xe42e, 0xa200,
+	0xe42e, 0xe0c0, 0x041c, 0xe008, 0x00ff, 0xcca4, 0xc785, 0xe018,
+	0xe000, 0x0500, 0xa002, 0xae04, 0xe0c2, 0x041a, 0xa202, 0xe0c2,
+	0x0418, 0xe0c0, 0x0419, 0xf7ea, 0xa202, 0xe0c2, 0x0418, 0xe0c0,
+	0x0419, 0xf7ea, 0xe0c0, 0x041b, 0xaf20, 0xa01e, 0xaf08, 0xae28,
+	0xe0c1, 0x041b, 0xe009, 0xffff, 0xa01f, 0xaf09, 0xae09, 0xe056,
+	0xe0c2, 0x041d, 0xe42e, 0xe0c0, 0x041c, 0xe00a, 0x0200, 0xe0c2,
+	0x041c, 0xa228, 0xa102, 0xf7f0, 0xe0c0, 0x041c, 0xe00c, 0x0200,
+	0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xaf04, 0xa802, 0xe42e,
+	0xe40e, 0x06d4, 0xe40e, 0x0354, 0xe40e, 0x0358, 0xe40e, 0x035c,
+	0xe40e, 0x0364, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x0368, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe41e, 0x036c, 0xe40e, 0x00a4,
+	0xe41e, 0x038b, 0xe40e, 0x00a4, 0xe41e, 0x025b, 0xe41e, 0x038c,
+	0xe41e, 0x02ad, 0xe40e, 0x00a4, 0xe41e, 0x040f, 0xe40e, 0x00a4,
+	0xe41e, 0x0526, 0xe40e, 0x00a4, 0xa200, 0x3cb6, 0xa200, 0xcc4a,
+	0xcc4c, 0xe41e, 0x0459, 0xe41e, 0x0485, 0xe41e, 0x0870, 0xe41e,
+	0x0669, 0xe41e, 0x0975, 0xf0ad, 0xe41e, 0x095b, 0xe41e, 0x04bf,
+	0xe41e, 0x0492, 0xf03a, 0xa202, 0x3cb6, 0xe41e, 0x0813, 0xe41e,
+	0x08d1, 0xe16a, 0xe42e, 0xe42e, 0xa202, 0x3cb6, 0xe41e, 0x0870,
+	0xe41e, 0x05aa, 0xe41e, 0x0486, 0xe41e, 0x0f72, 0xe41e, 0x0fa5,
+	0xe41e, 0x0473, 0xe41e, 0x0d3a, 0x2813, 0xe016, 0x3c33, 0xe41e,
+	0x0ae4, 0xe41e, 0x1135, 0xe41e, 0x0669, 0xe41e, 0x0492, 0xe40a,
+	0x03e2, 0x2833, 0x4434, 0xe408, 0x03cc, 0xe41e, 0x0a28, 0xe40d,
+	0x03e2, 0xe41e, 0x0964, 0x2817, 0xe408, 0x03fc, 0xe41e, 0x0cef,
+	0xf714, 0xf05a, 0xe41e, 0x04bf, 0xe40e, 0x03e2, 0xe41e, 0x020f,
+	0xe404, 0x03e2, 0xe41e, 0x0d08, 0x2834, 0xe41a, 0x0620, 0xe404,
+	0x03f3, 0x2834, 0xe41a, 0x062f, 0xe41e, 0x0c36, 0x2833, 0x4434,
+	0xe41a, 0x054a, 0x2833, 0x5434, 0xe41a, 0x0638, 0x2833, 0x5434,
+	0xe41a, 0x0d2d, 0x2833, 0x5434, 0x3c34, 0xf05a, 0x281a, 0x3cab,
+	0xe40e, 0x03a9, 0xe41e, 0x1185, 0xe41e, 0x0ef4, 0xe41e, 0x07a4,
+	0xf08a, 0xe41e, 0x07bb, 0xf05a, 0xe41e, 0x057b, 0xa200, 0x3ca7,
+	0xe41e, 0x055e, 0x3ca3, 0x28a3, 0x3ca8, 0xe41e, 0x08d1, 0xe41e,
+	0x05bf, 0xe41e, 0x0813, 0xe42e, 0xa200, 0x3ca7, 0xe41e, 0x095b,
+	0xe41e, 0x055e, 0x3ca3, 0x3ca8, 0xa2fe, 0x3ca2, 0xe41e, 0x1129,
+	0xe41e, 0x08d1, 0xe41e, 0x05bf, 0xe41e, 0x0813, 0xe42e, 0xe41e,
+	0x0870, 0xe42e, 0xe167, 0x02d4, 0xe166, 0x0064, 0xd022, 0x0003,
+	0xe184, 0x041c, 0x9e16, 0x3517, 0x3d17, 0xe42e, 0xe42e, 0xe161,
+	0x0550, 0xa200, 0x3d11, 0x2844, 0xae08, 0x1810, 0x3d11, 0xa200,
+	0x3d11, 0x2845, 0xae08, 0x1811, 0x3d11, 0xe42e, 0x3c03, 0xf028,
+	0xe42e, 0xa231, 0xa104, 0xf0e6, 0xa102, 0xb435, 0xf0ba, 0xa104,
+	0xb4cd, 0xf086, 0xa102, 0xf05a, 0xa104, 0xf026, 0xe42e, 0xa015,
+	0xa029, 0x3e01, 0x8401, 0xe182, 0x03e8, 0xe018, 0xe161, 0x0556,
+	0x3511, 0x3d11, 0xe005, 0x03e9, 0x2803, 0xa102, 0xf06a, 0xa106,
+	0xf04a, 0xa106, 0xf02a, 0xa103, 0xe161, 0x0554, 0x3711, 0x3f11,
+	0xe42e, 0xe41e, 0x0148, 0xe16a, 0xd130, 0x0005, 0xa2fe, 0x34b4,
+	0x3cb5, 0xe161, 0x0554, 0xc703, 0x3d11, 0xa202, 0x3cb7, 0xe161,
+	0x0550, 0xc703, 0x3d11, 0xa200, 0x3cb0, 0x3cb1, 0xe41e, 0x064d,
+	0xe41e, 0x1130, 0xe42e, 0xa200, 0xcc44, 0xcc4a, 0xcc4c, 0xcc72,
+	0xd130, 0x0005, 0xd03a, 0x0005, 0xd04b, 0x0001, 0xd04c, 0x0000,
+	0xd008, 0x0000, 0xe41e, 0x025f, 0xe42e, 0xe42e, 0xa200, 0x3c60,
+	0xa200, 0x3cb8, 0x3c34, 0x3c33, 0x3c17, 0xa2fc, 0x3ca2, 0xa2fa,
+	0x3ca3, 0xe42e, 0xa202, 0x3cf0, 0x2814, 0xa140, 0xf278, 0xa204,
+	0x3cf0, 0x2c10, 0xf23a, 0x2c11, 0xf21a, 0x2c10, 0xe002, 0x0780,
+	0xf1d0, 0x2c11, 0xe002, 0x0780, 0xf190, 0x8444, 0x8245, 0xe018,
+	0xe002, 0x1fe0, 0xf130, 0xe0c0, 0x0059, 0xa106, 0xf0d8, 0xe41e,
+	0x07a4, 0xf04a, 0xe41e, 0x01db, 0xf09e, 0xe41e, 0x05f4, 0x2aa2,
+	0xb7f5, 0x3ea2, 0xf03a, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xe16a,
+	0xa200, 0xcea6, 0xe41e, 0x07a4, 0xe408, 0x0508, 0xe41e, 0x1076,
+	0x28d3, 0xe002, 0x00af, 0xe406, 0x04fe, 0x28d3, 0xe002, 0x00b0,
+	0xf28a, 0x28d3, 0xe002, 0x00b1, 0xf2aa, 0x28d3, 0xe002, 0x00b2,
+	0xf26a, 0x28d3, 0xe002, 0x00b3, 0xf21a, 0x28d3, 0xe002, 0x00b4,
+	0xf1ea, 0x28d3, 0xe002, 0x00b5, 0xf1ea, 0x28d3, 0xe002, 0x00b6,
+	0xe40a, 0x04fd, 0x28d3, 0xe002, 0x00b7, 0xe40a, 0x04fe, 0x28d3,
+	0xe002, 0x00b8, 0xf0ca, 0x28d3, 0xe002, 0x00b9, 0xf082, 0xf07e,
+	0xe41e, 0x104a, 0xe41e, 0x09d5, 0xf43e, 0xf0de, 0xe41e, 0x104a,
+	0xe40e, 0x04bf, 0xe41e, 0x104a, 0xe41e, 0x09fb, 0xe40e, 0x04bf,
+	0xe41e, 0x01db, 0xe16a, 0xe42e, 0xa200, 0xcea6, 0xe41e, 0x07a4,
+	0xe408, 0x0519, 0xe41e, 0x1076, 0xe41e, 0x07a4, 0xe408, 0x0519,
+	0xe42e, 0xe41e, 0x01db, 0xe42e, 0x281d, 0xae02, 0x4c20, 0xae02,
+	0x4c1f, 0xae06, 0x4c1e, 0xae24, 0x4c1b, 0xe42e, 0xe41e, 0x064d,
+	0xe166, 0x0054, 0x9e06, 0xf16a, 0x28ad, 0xa102, 0xcc44, 0xa200,
+	0x3c01, 0xe184, 0x053f, 0x9e06, 0x5c01, 0xa802, 0xf07a, 0x2801,
+	0xe000, 0x0400, 0xe09e, 0xa208, 0x3d07, 0x2801, 0xa002, 0x3c01,
+	0xe190, 0xe42e, 0xe41e, 0x0815, 0xe0c0, 0x0048, 0xe0c2, 0x0051,
+	0xe42e, 0xe42e, 0x28a2, 0x2a54, 0xf07b, 0x2a1a, 0xa105, 0xf04b,
+	0xe166, 0x0598, 0x2916, 0x3ca9, 0xe41e, 0x0618, 0xa804, 0xe42a,
+	0x28a9, 0xe41e, 0x0608, 0xe41e, 0x0598, 0xe42e, 0x28a7, 0xa102,
+	0xb608, 0x3ca7, 0x28a6, 0xf12a, 0x28a5, 0xe000, 0x0578, 0xe092,
+	0x28a5, 0xa002, 0x3ca5, 0xa122, 0xf028, 0x3ca5, 0x28a6, 0xa102,
+	0x3ca6, 0x2901, 0xe049, 0x1aad, 0xe425, 0xe41e, 0x07bf, 0xe049,
+	0xa2fa, 0xb7f2, 0xe42e, 0xe166, 0x0599, 0x2906, 0xe41e, 0x0618,
+	0xa804, 0xf07a, 0x2906, 0x3ca9, 0xe41e, 0x0608, 0xe41e, 0x0598,
+	0xe166, 0x0598, 0x2906, 0xe41e, 0x0618, 0xa804, 0xf07a, 0x2906,
+	0x3ca9, 0xe41e, 0x0608, 0xe41e, 0x0598, 0xe41e, 0x0647, 0xe42e,
+	0x28a9, 0xe424, 0x28a4, 0xe000, 0x0578, 0xe092, 0x28a9, 0x3d01,
+	0x28a4, 0xa002, 0x3ca4, 0xa122, 0xf028, 0x3ca4, 0x28a6, 0xa002,
+	0x3ca6, 0xe42e, 0xa200, 0x3c06, 0xe004, 0x0054, 0xe09c, 0x28ad,
+	0xa102, 0xcc44, 0xe184, 0x05bd, 0x9e06, 0x5c06, 0xa802, 0xf048,
+	0x2806, 0xe41e, 0x0610, 0x2a06, 0xa003, 0x3e06, 0xe42e, 0xe167,
+	0x0400, 0xe004, 0x0054, 0xe09c, 0x28ad, 0xa102, 0xcc44, 0xa200,
+	0x3c06, 0xe184, 0x05d2, 0x2b17, 0xaf05, 0xa803, 0x5a06, 0xe056,
+	0x2a06, 0xa003, 0x3e06, 0x9f06, 0xe42e, 0x28aa, 0x3c06, 0x2806,
+	0xe000, 0x0400, 0xe092, 0x2901, 0xf0da, 0x2806, 0xa002, 0x3c06,
+	0x18ad, 0xf038, 0xa200, 0x3c06, 0x2806, 0x18aa, 0xf718, 0xa2fe,
+	0xe42e, 0xa20e, 0x3d01, 0x2806, 0xa002, 0x3caa, 0x18ad, 0xf038,
+	0xa200, 0x3caa, 0x2806, 0xe42e, 0xe161, 0x0400, 0x28ad, 0xa102,
+	0xcc44, 0xe184, 0x05fe, 0x2911, 0xe016, 0xe428, 0xe190, 0xe42e,
+	0xe424, 0xe000, 0x0400, 0xe092, 0x2901, 0xa80c, 0x3d01, 0xe42e,
+	0xe424, 0xe000, 0x0400, 0xe092, 0x2901, 0xa80a, 0x3d01, 0xe42e,
+	0xe424, 0xe000, 0x0400, 0xe092, 0x2901, 0xa806, 0x3d01, 0xe42e,
+	0xe049, 0xa200, 0xe425, 0xe001, 0x0400, 0xe093, 0x2901, 0xe42e,
+	0x28a3, 0x3ca8, 0xe41e, 0x05d5, 0xf094, 0x3ca2, 0x2a1a, 0xa105,
+	0x28a2, 0xe41b, 0x0600, 0xa200, 0xe42e, 0xa2fe, 0xe42e, 0xe166,
+	0x0598, 0x2916, 0xb608, 0x3ca1, 0x2916, 0xb608, 0x3ca0, 0xe42e,
+	0x281a, 0xa104, 0xe42a, 0xe166, 0x0599, 0x290e, 0xe41e, 0x0600,
+	0xe166, 0x0598, 0x2916, 0x3d0e, 0x28a2, 0x3d06, 0xe42e, 0xa2fa,
+	0xe166, 0x0598, 0xc701, 0x3d16, 0xe42e, 0xa2fa, 0x3ca0, 0x3ca1,
+	0x3ca8, 0xa202, 0x3ca7, 0xa200, 0x3ca5, 0x3ca4, 0x3ca6, 0x3ca9,
+	0xe166, 0x0578, 0xc710, 0x3d16, 0xe41e, 0x0647, 0xa200, 0x3caa,
+	0xe161, 0x0400, 0x2aad, 0xe42b, 0xa103, 0x3e01, 0x8601, 0x3d11,
+	0xe42e, 0xe0c0, 0x0059, 0xa102, 0xe40a, 0x0676, 0xa102, 0xe40a,
+	0x06b2, 0xa102, 0xe40a, 0x067c, 0xe40e, 0x06b2, 0x24c0, 0x4cc1,
+	0x04c2, 0x0cc3, 0x34c4, 0x3cc5, 0x28cc, 0xf13a, 0xe0c0, 0x0048,
+	0x34cf, 0x3cd0, 0x24cf, 0x4cd0, 0xe0c1, 0x0049, 0x36c8, 0x3ec9,
+	0x14c8, 0x1cc9, 0xe0c1, 0x0045, 0xaf05, 0xa803, 0xb611, 0x3ecc,
+	0xe0c0, 0x0048, 0xe008, 0x01ff, 0x3cca, 0xe0c0, 0x0048, 0x34c6,
+	0xe008, 0xfe00, 0x3cc7, 0xa200, 0xcc92, 0xcc8e, 0xe180, 0xe41e,
+	0x06b9, 0xe41e, 0x0222, 0xd071, 0x202a, 0xe181, 0xa200, 0x3cce,
+	0xe41e, 0x070b, 0xe41e, 0x102c, 0x28ca, 0xa102, 0xe412, 0x103f,
+	0xa200, 0xceaa, 0xa202, 0x3cce, 0xa202, 0xb61a, 0xe16a, 0xe42e,
+	0xe42e, 0xd030, 0x0000, 0xd031, 0x0000, 0xd032, 0x0000, 0xd034,
+	0x0000, 0xd033, 0x0000, 0xd035, 0x0000, 0xd036, 0x00ff, 0xd037,
+	0x0000, 0xd038, 0x0000, 0xd039, 0x0000, 0xd04b, 0x0001, 0xd04c,
+	0x0000, 0xd149, 0x0000, 0xe42e, 0xc896, 0xf05a, 0xe41e, 0x0702,
+	0x3cdc, 0xf058, 0xd04b, 0x0001, 0xa200, 0x3cdc, 0x28d8, 0xcc6e,
+	0xd04c, 0x0000, 0xe470, 0xa202, 0x3cdc, 0xe41e, 0x0702, 0xcc96,
+	0xe42a, 0x28d8, 0xcc6e, 0xe42e, 0xc896, 0xe428, 0xd04b, 0x0001,
+	0x28d8, 0xcc6e, 0xd04c, 0x0000, 0xe42e, 0xa200, 0x3ccd, 0x3cd8,
+	0xe41e, 0x0702, 0x3cdc, 0xd04b, 0x0001, 0x28d8, 0xcc6e, 0xe190,
+	0xe128, 0xe42e, 0xe41e, 0x10e9, 0xe004, 0x0080, 0x2acd, 0xb616,
+	0x3cd8, 0xa200, 0xe42e, 0x28cc, 0xf1aa, 0xe41e, 0x024f, 0xe000,
+	0x0440, 0xce50, 0xe005, 0x01b1, 0x28d9, 0xa806, 0xa108, 0xe012,
+	0xa806, 0xae06, 0x3cfe, 0xe004, 0x01b1, 0x58fe, 0xce52, 0xe41e,
+	0x0257, 0xd14e, 0x0000, 0xd144, 0x0000, 0xe42e, 0xd027, 0x0000,
+	0xe41e, 0x0768, 0xd027, 0x0001, 0x28d9, 0xf25a, 0xca48, 0xa802,
+	0xf7e8, 0x24c6, 0x4cc7, 0xce40, 0xd121, 0x0000, 0xd122, 0x0040,
+	0xe0c0, 0x0043, 0xa806, 0xae02, 0xa032, 0xce46, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xca48, 0xa802, 0xf7e8, 0x24c6, 0x4cc7, 0xe000,
+	0x0200, 0x34c6, 0x3cc7, 0x14c4, 0x1cc5, 0xf054, 0x24c0, 0x4cc1,
+	0x34c6, 0x3cc7, 0x28cc, 0xe418, 0x07d2, 0xe41e, 0x0815, 0xd14e,
+	0x0000, 0xd144, 0x0000, 0xe42e, 0xe0c1, 0x0059, 0xa103, 0xa200,
+	0xb636, 0xe000, 0x001c, 0xe0c1, 0x0045, 0xe052, 0xe01a, 0xe42e,
+	0xa200, 0x3ccb, 0xe004, 0x0200, 0x3cd9, 0xe41e, 0x075c, 0x3ccc,
+	0x24c6, 0x4cc7, 0xe0c1, 0x0049, 0x36cf, 0x3ed0, 0x26cf, 0x4ed0,
+	0xe045, 0xf033, 0x06c2, 0x0ec3, 0xe003, 0x0200, 0x28cc, 0xb602,
+	0x3ccc, 0xf173, 0xe001, 0x0200, 0x3ed9, 0x28cc, 0xf128, 0x28cb,
+	0xf658, 0xe0c0, 0x005c, 0xe008, 0x4000, 0xf60a, 0xe0c0, 0x005d,
+	0xe00a, 0x4000, 0xe0c2, 0x005d, 0xa202, 0xce00, 0x3ccb, 0xf56e,
+	0x28d9, 0x2acc, 0xf039, 0xe004, 0x0200, 0x3cd9, 0xe42e, 0xc868,
+	0xa80e, 0x3c04, 0x7404, 0xe42e, 0x28cc, 0xe42a, 0xe41e, 0x0815,
+	0xe0c0, 0x0049, 0x34cf, 0x3cd0, 0x24cf, 0x4cd0, 0xe0c1, 0x0048,
+	0x36cf, 0x3ed0, 0x26cf, 0x4ed0, 0xe045, 0xa200, 0xb626, 0xe003,
+	0x0200, 0xb606, 0xe42e, 0xe0c0, 0x0045, 0xa808, 0xe42e, 0xe41e,
+	0x07a4, 0xe42a, 0xe0c0, 0x0045, 0xaf04, 0xa802, 0xe42e, 0xe0c1,
+	0x0045, 0xaf07, 0xa202, 0xa803, 0xe429, 0xa204, 0xa805, 0xe429,
+	0xa208, 0xe42e, 0xe41e, 0x024f, 0x28d9, 0xe002, 0x0200, 0xe40a,
+	0x0811, 0x28d9, 0xa806, 0xf1fa, 0xa108, 0xe012, 0xae06, 0x3cfe,
+	0x28d9, 0xaf04, 0xae20, 0xe000, 0x01c0, 0xce50, 0xe190, 0xca52,
+	0x5cfe, 0x58fe, 0x2ad9, 0xa807, 0xae07, 0x3efe, 0xe005, 0x01b1,
+	0x5efe, 0xe056, 0x2ad9, 0xaf05, 0xae21, 0xe001, 0x0140, 0xce51,
+	0xe190, 0xce52, 0xe004, 0x01fc, 0x18d9, 0xf022, 0xf13e, 0x28d9,
+	0xa006, 0xaf04, 0xae20, 0xe000, 0x0440, 0xce50, 0x28d9, 0xa806,
+	0xa108, 0xe012, 0xae06, 0xa83e, 0x3cfe, 0xe004, 0x01b1, 0x58fe,
+	0xce52, 0xe40e, 0x0257, 0xe41e, 0x079f, 0xf1ae, 0xc872, 0xc001,
+	0x343b, 0x3c3c, 0xc000, 0x26d7, 0x4ed6, 0xae07, 0xe045, 0xf053,
+	0x26d7, 0x4ed6, 0xae07, 0xcc73, 0xe41e, 0x084c, 0xe049, 0xc001,
+	0x243b, 0x4c3c, 0xc000, 0xaf06, 0xe046, 0xb608, 0xf02e, 0xcaaa,
+	0x2ace, 0xb616, 0xe0c1, 0x0048, 0x36cf, 0x3ed0, 0x26cf, 0x4ed0,
+	0xe042, 0xe049, 0x16c4, 0x1ec5, 0xf035, 0x14c2, 0x1cc3, 0xe0c2,
+	0x0048, 0xe0c2, 0x0052, 0xa200, 0xceaa, 0xc001, 0x243b, 0x4c3c,
+	0xc000, 0xe41e, 0x0851, 0xe42e, 0xc001, 0x2439, 0x4c3a, 0xc000,
+	0xe42e, 0xc001, 0xaf06, 0x3439, 0x3c3a, 0xc000, 0xe42e, 0xe0c0,
+	0x0045, 0xaf04, 0xa80e, 0xa104, 0xe428, 0xf06e, 0xe41e, 0x07a4,
+	0xe418, 0x01db, 0xe42e, 0xe41e, 0x10c2, 0xcaa2, 0xe008, 0x00ff,
+	0xe002, 0x00b1, 0xe428, 0xe41e, 0x07a4, 0xe418, 0x01db, 0xe42e,
+	0xe0c0, 0x0059, 0xa102, 0xf34a, 0xa102, 0xe42a, 0xa102, 0xf05a,
+	0xa102, 0xe40a, 0x08b5, 0xe42e, 0xe0c0, 0x0060, 0xaf08, 0x30e1,
+	0xaf02, 0x30e2, 0xe0c0, 0x0060, 0xa81e, 0x3ce0, 0xe0c0, 0x0061,
+	0xa83e, 0x3ce4, 0xe0c0, 0x0065, 0xaf04, 0xa80e, 0x3cba, 0xa200,
+	0x3c56, 0x3c55, 0xa202, 0x3cb9, 0x2856, 0xf11a, 0xe0c0, 0x006c,
+	0xe002, 0x0088, 0x3c5c, 0xe0c0, 0x006a, 0xce20, 0xd112, 0x000c,
+	0xd111, 0x0536, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e, 0xe0c0,
+	0x0060, 0x34c0, 0x3cc1, 0xe0c0, 0x0061, 0xae14, 0x34c2, 0x3cc3,
+	0xe0c0, 0x0062, 0xaf02, 0x3054, 0xe42e, 0xe41e, 0x0412, 0xe41e,
+	0x0174, 0xca28, 0xf7f8, 0xe0c0, 0x0042, 0xce20, 0xd111, 0x0210,
+	0xd112, 0x00c4, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe0c0, 0x0060,
+	0x3cad, 0xe0c0, 0x0061, 0x3cae, 0xe0c0, 0x006e, 0xe41e, 0x020a,
+	0xe42e, 0xe0c0, 0x0059, 0xa102, 0xe40a, 0x091f, 0xa102, 0xe42a,
+	0xa102, 0xf05a, 0xa102, 0xe40a, 0x095a, 0xe42e, 0x2444, 0x4c45,
+	0xae08, 0xe0c2, 0x006f, 0x20b4, 0x4cb5, 0xa002, 0x34b4, 0x3cb5,
+	0xe0c2, 0x0070, 0x28a3, 0xe0c2, 0x0071, 0x28b8, 0xe0c2, 0x0072,
+	0xe41e, 0x051c, 0xe0c2, 0x0073, 0xa200, 0xe0c2, 0x0074, 0x28b6,
+	0x2a17, 0xae29, 0xe056, 0xe0c2, 0x0076, 0x28a2, 0xe0c2, 0x0077,
+	0xe161, 0x0550, 0x2111, 0x4d11, 0xe0c2, 0x0078, 0x2111, 0x4d11,
+	0xe0c2, 0x0079, 0x20b0, 0x4cb1, 0xe0c2, 0x007c, 0xe167, 0x0554,
+	0x2117, 0x4d17, 0xe0c2, 0x007e, 0x2117, 0x4d17, 0xe0c2, 0x007d,
+	0xc84a, 0xc84d, 0xae20, 0xe056, 0xe0c2, 0x0053, 0xe42e, 0x24b3,
+	0x4cb2, 0xe0c2, 0x006d, 0x28b6, 0xe0c2, 0x0070, 0x2444, 0x4c45,
+	0xae08, 0xe0c2, 0x0071, 0x20b0, 0x4cb1, 0xe0c2, 0x0072, 0xa208,
+	0xe0c2, 0x0073, 0xa202, 0xe0c2, 0x0074, 0xa200, 0xe0c2, 0x0075,
+	0xe161, 0x0550, 0x2111, 0x4d11, 0xe0c2, 0x0076, 0x2111, 0x4d11,
+	0xe0c2, 0x0077, 0x28b6, 0xe016, 0x58f0, 0xe0c2, 0x0078, 0xe161,
+	0x0554, 0x2111, 0x4d11, 0xe0c2, 0x007a, 0x2111, 0x4d11, 0xe0c2,
+	0x0079, 0x2813, 0xe016, 0xae10, 0x4c15, 0xae10, 0x4c14, 0xe0c2,
+	0x007b, 0xe42e, 0xe42e, 0xe161, 0x05a8, 0x2810, 0x3d11, 0x2811,
+	0x3d11, 0x2813, 0x3d11, 0xe42e, 0xe161, 0x05a8, 0x2810, 0x1911,
+	0xf0a8, 0x2811, 0x1911, 0xf078, 0x2813, 0x1911, 0xf048, 0xa200,
+	0x3c17, 0xe42e, 0xa202, 0x3c17, 0xe42e, 0xa200, 0x3c28, 0xe16a,
+	0xa200, 0xcea6, 0xa23e, 0x3cf0, 0xe41e, 0x07a4, 0xe408, 0x09cf,
+	0xe41e, 0x1076, 0x28d3, 0xe002, 0x00af, 0xe406, 0x09c3, 0x28d3,
+	0xe002, 0x00b0, 0xf28a, 0x28d3, 0xe002, 0x00b1, 0xf35a, 0x28d3,
+	0xe002, 0x00b2, 0xf31a, 0x28d3, 0xe002, 0x00b3, 0xf27a, 0x28d3,
+	0xe002, 0x00b4, 0xf29a, 0x28d3, 0xe002, 0x00b5, 0xf2ba, 0x28d3,
+	0xe002, 0x00b6, 0xe40a, 0x09bd, 0x28d3, 0xe002, 0x00b7, 0xe40a,
+	0x09c3, 0x28d3, 0xe002, 0x00b8, 0xf17a, 0x28d3, 0xe002, 0x00b9,
+	0xf132, 0xf12e, 0xe41e, 0x1122, 0xe41e, 0x104a, 0xe41e, 0x09d5,
+	0xf1bd, 0xa202, 0x3c28, 0xe40e, 0x0977, 0x2828, 0xe428, 0xe41e,
+	0x104a, 0xe40e, 0x0977, 0x2828, 0xe428, 0xe41e, 0x104a, 0xe40e,
+	0x0977, 0xe41e, 0x104a, 0xe41e, 0x09fb, 0xe40e, 0x0977, 0x2828,
+	0xe428, 0xe41e, 0x0857, 0xe16b, 0xe42e, 0xba4e, 0x3c14, 0xba4e,
+	0x3c15, 0xba40, 0x3c13, 0xba5a, 0x3c10, 0xba5a, 0x3c11, 0x2813,
+	0xe016, 0x3c33, 0xe41e, 0x0ae4, 0xe41e, 0x041f, 0xba42, 0x3cb7,
+	0xba44, 0xa200, 0x3cb0, 0xba46, 0x3cb1, 0xba46, 0xe41e, 0x042e,
+	0xba62, 0xba41, 0xba57, 0xae25, 0xe056, 0x34b3, 0x3cb2, 0xba40,
+	0x3c16, 0xba6a, 0xe42e, 0xba46, 0xa104, 0xf08a, 0xa104, 0xf0fa,
+	0xa106, 0xf03a, 0xa108, 0xf10a, 0xe42e, 0xba46, 0xba40, 0xf02a,
+	0xba6e, 0xba5a, 0xba40, 0xba5a, 0xba42, 0xf19e, 0xba62, 0xba68,
+	0xba6c, 0xba6a, 0xf14e, 0xba7e, 0xba6c, 0xba6c, 0xba6c, 0xba60,
+	0xba60, 0xba60, 0xba60, 0xba60, 0xba60, 0xba6c, 0xba6c, 0xba6c,
+	0xba6c, 0xba6c, 0xba7e, 0xe190, 0xba40, 0xba7e, 0xa200, 0xe42e,
+	0xa200, 0x3c28, 0xe16a, 0xa200, 0xcea6, 0xe41e, 0x07a4, 0xe408,
+	0x0aa5, 0xe41e, 0x1076, 0x28d3, 0xe002, 0x00af, 0xe406, 0x0a9e,
+	0x28d3, 0xe002, 0x00b0, 0xf2ca, 0x28d3, 0xe002, 0x00b1, 0xf30a,
+	0x28d3, 0xe002, 0x00b2, 0xf30a, 0x28d3, 0xe002, 0x00b3, 0xf33a,
+	0x28d3, 0xe002, 0x00b4, 0xf18a, 0x28d3, 0xe002, 0x00b5, 0xf38a,
+	0x28d3, 0xe002, 0x00b6, 0xe40a, 0x0a8d, 0x28d3, 0xe002, 0x00b7,
+	0xe40a, 0x0a9a, 0x28d3, 0xe002, 0x00b8, 0xf06a, 0x28d3, 0xe002,
+	0x00b9, 0xf022, 0xe190, 0xe41e, 0x104a, 0xe40e, 0x0a2a, 0xe41e,
+	0x1122, 0xe41e, 0x104a, 0xe41e, 0x09d5, 0xe40e, 0x0a2a, 0xe41e,
+	0x104a, 0xe40e, 0x0a2a, 0xe41e, 0x104a, 0x2856, 0xe418, 0x0ba4,
+	0xe40e, 0x0a2a, 0xe41e, 0x0c2c, 0xe41e, 0x104a, 0xe41e, 0x0ab4,
+	0xa202, 0xb61a, 0x3c28, 0xe41d, 0x0c33, 0xe40e, 0x0a2a, 0xe41e,
+	0x104a, 0xe41e, 0x09fb, 0xe40e, 0x0a2a, 0xe41e, 0x0c2c, 0xe41e,
+	0x104a, 0xe41e, 0x0aff, 0xa202, 0xb61a, 0x3c28, 0xe41d, 0x0c33,
+	0xe40e, 0x0a2a, 0xe41e, 0x104a, 0xe40e, 0x0a2a, 0x2828, 0xe408,
+	0x0aa7, 0xe41e, 0x104a, 0xe40e, 0x0a2a, 0xe41e, 0x01db, 0x281a,
+	0x3c1b, 0x281e, 0xe016, 0x3c33, 0xe41e, 0x0ae4, 0xe41e, 0x041f,
+	0x2828, 0xe428, 0xe16b, 0xe42e, 0xba5e, 0xba40, 0xa102, 0xf028,
+	0xba6e, 0xba40, 0xba4e, 0x3c1c, 0x2816, 0xa102, 0xf038, 0xcfa0,
+	0xcba2, 0xba40, 0xe049, 0x3c1d, 0xa103, 0xf02b, 0xba40, 0x3c1e,
+	0xba40, 0x3c1f, 0xba40, 0x3c20, 0xba40, 0x3c21, 0xba4a, 0x3c22,
+	0x281d, 0x4c1e, 0xf038, 0xba40, 0x3c23, 0xba46, 0xba40, 0x3c27,
+	0xf098, 0xba40, 0xf07a, 0xcfa0, 0xcba4, 0x3c24, 0xcfa0, 0xcba4,
+	0x3c25, 0xa200, 0x3c1a, 0xe42e, 0x2810, 0xa01e, 0xaf08, 0x3c44,
+	0x2811, 0xa01e, 0xaf08, 0x3c45, 0x2833, 0xf06a, 0x2845, 0xa002,
+	0xaf02, 0xae02, 0x3c45, 0x8444, 0x8245, 0xe018, 0x3c47, 0x2c45,
+	0x3c48, 0x2833, 0xe42a, 0x2c45, 0xaf02, 0x3c48, 0xe42e, 0xba5e,
+	0xba42, 0x3c39, 0xba4e, 0x3c1c, 0x2816, 0xf03a, 0xcfa0, 0xcba2,
+	0xba40, 0x3c1d, 0xf068, 0xba40, 0x3c1e, 0xf048, 0xba40, 0xf02e,
+	0x3c1e, 0xba40, 0x3c1f, 0xba40, 0x3c20, 0xba40, 0x3c21, 0xba4a,
+	0x3c22, 0x2839, 0xa104, 0x2a1e, 0xa103, 0xe056, 0xf03a, 0xba40,
+	0x3c26, 0xba46, 0xba40, 0x3c23, 0xba40, 0x3c27, 0xf098, 0xba40,
+	0xf07a, 0xcfa0, 0xcba4, 0x3c24, 0xcfa0, 0xcba4, 0x3c25, 0xa202,
+	0x2a39, 0xa105, 0xb656, 0x3c1a, 0xe42e, 0xe41e, 0x07a4, 0xe408,
+	0x0b60, 0xe41e, 0x1076, 0x28d3, 0xe002, 0x00b0, 0xe40a, 0x0b62,
+	0x28d3, 0xe002, 0x00b2, 0xe40a, 0x0b62, 0x28d3, 0xe002, 0x00b5,
+	0xe40a, 0x0b62, 0x28d3, 0xe002, 0x00b3, 0xe40a, 0x0b62, 0x28d3,
+	0xe002, 0x00b6, 0xe40a, 0x0b62, 0x28d3, 0xe002, 0x00af, 0xe406,
+	0x0b64, 0x28d3, 0xe002, 0x00b1, 0xe40a, 0x0b60, 0xe40e, 0x0b62,
+	0xe41e, 0x01db, 0xe40e, 0x0b6e, 0xe41e, 0x104a, 0x8444, 0x82d3,
+	0xe018, 0x3c46, 0xe41e, 0x0b70, 0xa200, 0xe42e, 0xa2fe, 0xe42e,
+	0x2810, 0xe002, 0x0af0, 0xf024, 0xba44, 0x2821, 0xf058, 0xba40,
+	0x3c30, 0xba4a, 0x3c31, 0x281a, 0xf27a, 0xba40, 0x3c37, 0xf24a,
+	0x281e, 0xf03a, 0xa204, 0xf07e, 0x2834, 0xf04a, 0xa202, 0x2a1b,
+	0xf02b, 0xa208, 0x3c01, 0xe161, 0x0200, 0xe162, 0x0204, 0xe163,
+	0x0208, 0xe164, 0x020c, 0xa102, 0xcc44, 0xe184, 0x0ba0, 0xba4e,
+	0x3d11, 0xba4e, 0x3d12, 0xba40, 0xba4e, 0x3d13, 0xba4e, 0x3d14,
+	0xba40, 0xba40, 0x3c36, 0xe42e, 0x2a56, 0x285a, 0xa120, 0xb615,
+	0x3e56, 0xe42b, 0xa200, 0x3c58, 0xe162, 0x0520, 0xba4e, 0x2a58,
+	0xa803, 0xf049, 0xae10, 0x3c57, 0xf03e, 0x4c57, 0x3d12, 0x2a58,
+	0xa003, 0x3e58, 0xa80f, 0xe41b, 0x0c10, 0x2856, 0xf09a, 0xc894,
+	0xf6e8, 0x2858, 0x2858, 0xa802, 0xf03a, 0x2857, 0x3d12, 0xa211,
+	0x2858, 0xa80e, 0xf0ba, 0xe045, 0xaf03, 0xf06b, 0xa103, 0x3e01,
+	0xa201, 0x8601, 0x3f12, 0xe41e, 0x0c10, 0xe162, 0x0520, 0x2859,
+	0x3d12, 0x2858, 0x3d12, 0xa200, 0x3d12, 0x3d12, 0xe0c1, 0x006b,
+	0x285a, 0xa002, 0xae06, 0xe041, 0xaf06, 0x3c5a, 0xce21, 0xd111,
+	0x0520, 0xd112, 0x0004, 0xd113, 0x0000, 0xca28, 0xf7f8, 0xe42e,
+	0xa200, 0x3c5d, 0xe0c0, 0x005c, 0xe0c1, 0x0065, 0xaf12, 0xa802,
+	0xaf15, 0xa803, 0xe016, 0xe056, 0xf04a, 0xa200, 0x3c56, 0xe42e,
+	0x285e, 0xf05a, 0xe0c0, 0x005d, 0xe42a, 0xf7be, 0xe0c0, 0x005d,
+	0xe00a, 0x0200, 0xe0c2, 0x005d, 0xa202, 0xce00, 0x3c5e, 0xf71e,
+	0xd112, 0x0004, 0xe0c0, 0x006b, 0xe000, 0x0088, 0x085d, 0xce20,
+	0xd111, 0x0520, 0xd113, 0x0000, 0xca28, 0xf7f8, 0xe162, 0x0520,
+	0x285b, 0x2a5d, 0xa010, 0xa011, 0x3c5b, 0x3e5d, 0x1a5c, 0xe41b,
+	0x0bf0, 0xa200, 0x3c5e, 0xe42e, 0x2860, 0xe428, 0xe41e, 0x0542,
+	0xa202, 0x3c60, 0xe42e, 0xa200, 0x3c60, 0xe42e, 0xe16a, 0xa200,
+	0x3c42, 0x3c43, 0x2841, 0x2a34, 0xb616, 0x3c41, 0x2834, 0xf04a,
+	0x281a, 0xb634, 0x3c1a, 0xe41e, 0x0d54, 0x281c, 0xcfc8, 0xe16a,
+	0xe41e, 0x0b35, 0xf084, 0xe41e, 0x0dfa, 0xe41e, 0x0c5e, 0xe41e,
+	0x0c9a, 0xf76a, 0x8444, 0x8248, 0xe018, 0x3c46, 0x1841, 0xe410,
+	0x0c7a, 0xe16a, 0xe0c0, 0x0111, 0xf7e8, 0xe42e, 0xe16a, 0x2c46,
+	0x1c41, 0xe410, 0x0c7a, 0xe41e, 0x0cba, 0xe41e, 0x0cc7, 0xe42d,
+	0xe41e, 0x0ec1, 0xe41e, 0x0ca9, 0xe41e, 0x0c9a, 0xf048, 0xe41e,
+	0x0c9f, 0xf72a, 0x24d7, 0x4cd6, 0xae06, 0xc873, 0xe046, 0xe422,
+	0xe16b, 0xe42e, 0xe41e, 0x0cba, 0xe41e, 0x0c89, 0xe41e, 0x0ec1,
+	0xe41e, 0x0ca9, 0xe41e, 0x0c9a, 0xe428, 0x2c46, 0x1c41, 0xe42a,
+	0xf72e, 0xa2fe, 0x3c40, 0xd1ce, 0x0000, 0xd1c3, 0x0000, 0xcbc0,
+	0xf7f8, 0xd1c0, 0x0020, 0xd1e0, 0x0010, 0xcbc0, 0xf7f8, 0xd1e0,
+	0x000a, 0xe42e, 0x2c43, 0x1c48, 0xe01a, 0xe016, 0xe42e, 0xcb8a,
+	0xb60c, 0x3c40, 0xe016, 0xe42a, 0xc88e, 0xc895, 0xe017, 0xe042,
+	0xe42e, 0xd1c8, 0x0001, 0x2841, 0xa002, 0x3c41, 0x2842, 0xa002,
+	0x3c42, 0x1844, 0xe428, 0xd1c6, 0x0004, 0x3c42, 0x2843, 0xa002,
+	0x3c43, 0xe42e, 0x2843, 0xae0e, 0x4c42, 0xcf94, 0x2841, 0xcf98,
+	0xd1c3, 0x0000, 0xcbc0, 0xf7f8, 0xd1e0, 0x0005, 0xe42e, 0xcbc0,
+	0xf7f8, 0xe180, 0xe180, 0x28dc, 0xe41a, 0x06e3, 0xe181, 0xd1c0,
+	0x000f, 0xe005, 0x8000, 0xa103, 0xf155, 0xcb9c, 0xf138, 0xcb80,
+	0xf7b8, 0xd1e0, 0x000a, 0xd1c0, 0x0010, 0xcb8a, 0xb60c, 0x3c40,
+	0xf056, 0x2c47, 0x1841, 0x1840, 0xf054, 0xcbc0, 0xf7f8, 0xe16a,
+	0xe42e, 0xd1c0, 0x0000, 0xd1ce, 0x0000, 0xe16b, 0xe42e, 0x28ba,
+	0xf16a, 0xa102, 0xf06a, 0xa102, 0xf0ba, 0xa104, 0xf05a, 0xf0ae,
+	0x281b, 0xf098, 0xf0ce, 0x281b, 0xa102, 0xf096, 0xf03e, 0x281b,
+	0xf06a, 0xf03e, 0xa2fe, 0xe42e, 0xa202, 0xe42e, 0xa200, 0xe42e,
+	0xa200, 0xcfc2, 0x283b, 0xcfc8, 0xaf12, 0xe40a, 0x0d12, 0xcfc2,
+	0x283b, 0xcfc8, 0xa2fe, 0xcfca, 0xa200, 0xcfc2, 0x283a, 0xcfc8,
+	0xaf12, 0xe40a, 0x0d1e, 0xcfc2, 0x283a, 0xcfc8, 0xa2fe, 0xcfca,
+	0xa200, 0xcfc2, 0x283c, 0xcfc8, 0xaf12, 0xe40a, 0x0d2a, 0xcfc2,
+	0x283c, 0xcfc8, 0xa2fe, 0xcfca, 0xe42e, 0x281a, 0xa104, 0xe42a,
+	0x283a, 0x3c3b, 0x283c, 0x3c3a, 0x281c, 0x2a33, 0xae13, 0xe056,
+	0x3c3c, 0xe42e, 0xa20a, 0xe0c2, 0x0100, 0xa200, 0xe0c2, 0x013d,
+	0xa200, 0xe0c2, 0x0128, 0x2ae1, 0x4ee2, 0xb692, 0xae08, 0xa91c,
+	0xe0c2, 0x017c, 0xe004, 0x004c, 0xe0c2, 0x017d, 0xa200, 0xe41e,
+	0x0f52, 0xe0c2, 0x0102, 0xe42e, 0xe0c0, 0x0050, 0xe049, 0xe008,
+	0x007f, 0x3c0c, 0xaf11, 0xe009, 0x007f, 0x3e0d, 0x460c, 0x3e0c,
+	0xa200, 0x2a0c, 0xa803, 0xf03b, 0xe00a, 0x0002, 0x2a0c, 0xa805,
+	0xf03b, 0xe00a, 0x0009, 0x2a0c, 0xa809, 0xf03b, 0xe00a, 0x0020,
+	0x2a0c, 0xa811, 0xf03b, 0xe00a, 0x0040, 0xe0c2, 0x040c, 0xe0c1,
+	0x0046, 0xe004, 0x0010, 0xae10, 0xe042, 0x2a0d, 0xa805, 0xf05b,
+	0xe167, 0x02d6, 0x2117, 0x4d17, 0xe0c2, 0x0103, 0x2844, 0xae20,
+	0x4c45, 0xae08, 0xe0c2, 0x0101, 0xd1c6, 0x0001, 0x2845, 0xae0e,
+	0x4c44, 0xcf96, 0x8444, 0x8245, 0xe018, 0xcf9a, 0x2824, 0xa87e,
+	0xae0c, 0x2a25, 0xa87f, 0xe056, 0xcf8e, 0xa200, 0xcfd6, 0x2826,
+	0xae02, 0x4c1e, 0xae02, 0x4c34, 0xcfc2, 0x2834, 0xf098, 0x2821,
+	0xae0c, 0x4c22, 0xae02, 0x4c23, 0xae04, 0x4c1a, 0xcf82, 0x281a,
+	0xcf88, 0xa200, 0xe41e, 0x0f52, 0xe0c2, 0x0102, 0x2833, 0xa908,
+	0xae04, 0x4c1a, 0xae04, 0x4c33, 0xae02, 0x4c34, 0xe0c2, 0x0104,
+	0x2a33, 0xe0c0, 0x005b, 0xae08, 0x4c1a, 0xae04, 0xe056, 0xae02,
+	0x4c34, 0xe0c2, 0x0204, 0x2834, 0xe41a, 0x0e6f, 0xe41e, 0x0e32,
+	0xe161, 0x02d0, 0x2111, 0x4d01, 0xcfc6, 0xe0c1, 0x0046, 0xe004,
+	0x0000, 0xae10, 0xe042, 0x2a0d, 0xa803, 0xf05b, 0xe167, 0x02d4,
+	0x2117, 0x4d17, 0xcfc4, 0xe41e, 0x0274, 0xa202, 0xe0c2, 0x0106,
+	0xe42e, 0xa20a, 0xe0c2, 0x0100, 0xe004, 0x004e, 0xe0c2, 0x017c,
+	0xe004, 0x004c, 0xe0c2, 0x017d, 0xa200, 0xe41e, 0x0f52, 0xe0c2,
+	0x0102, 0xe42e, 0xa200, 0x3cb8, 0xa2fe, 0x3c40, 0xcf8a, 0x2830,
+	0xae0c, 0x4c31, 0xae02, 0x4c37, 0xae02, 0x4c36, 0xcf84, 0xd1c6,
+	0x0002, 0xe161, 0x0200, 0xe162, 0x0204, 0xe163, 0x0208, 0xe164,
+	0x020c, 0x2911, 0xae10, 0x4d11, 0xae10, 0x4d11, 0xae10, 0x4d01,
+	0xcfce, 0x2912, 0xae10, 0x4d12, 0xae10, 0x4d12, 0xae10, 0x4d02,
+	0xcfd0, 0x2913, 0xae10, 0x4d13, 0xae10, 0x4d13, 0xae10, 0x4d03,
+	0xcfd2, 0x2914, 0xae10, 0x4d14, 0xae10, 0x4d14, 0xae10, 0x4d04,
+	0xcfd4, 0xe42e, 0x2010, 0x4c11, 0xe0c2, 0x0205, 0xa200, 0xe0c2,
+	0x0215, 0xe41e, 0x0f52, 0xa203, 0xae11, 0xe056, 0xe0c2, 0x0213,
+	0xa200, 0xe0c2, 0x0215, 0xa200, 0xe0c2, 0x0208, 0xa202, 0xe0c2,
+	0x0210, 0xe0c1, 0x0046, 0xe004, 0x0040, 0xae10, 0xe042, 0x2a0d,
+	0xa809, 0xf05b, 0xe167, 0x02d8, 0x2117, 0x4d17, 0xe0c2, 0x0211,
+	0xe0c1, 0x0046, 0xe004, 0x0040, 0xe000, 0x0040, 0xae10, 0xe042,
+	0x2a0d, 0xa811, 0xf05b, 0xe167, 0x02da, 0x2117, 0x4d17, 0xe0c2,
+	0x0212, 0x28a2, 0xe0c2, 0x0214, 0xe41e, 0x0fee, 0xe42e, 0xa202,
+	0xe0c2, 0x0302, 0xa20e, 0xe0c2, 0x0312, 0x28a0, 0xf052, 0x28a1,
+	0xf032, 0x28a2, 0xb608, 0xe0c2, 0x0380, 0x28a1, 0xf032, 0x28a2,
+	0xb608, 0xe0c2, 0x0383, 0x28a2, 0xb608, 0xe0c2, 0x0386, 0xe0c0,
+	0x0414, 0xe418, 0x018c, 0xe0c0, 0x0414, 0xe41a, 0x0e93, 0xa200,
+	0xe0c2, 0x0302, 0xe42e, 0xe167, 0x01a0, 0x2117, 0x4d17, 0xe0c2,
+	0x0152, 0x2917, 0xe008, 0x00ff, 0xae20, 0x4d07, 0xe0c2, 0x0153,
+	0xe0c0, 0x0101, 0xe0c2, 0x015d, 0x28a0, 0xb608, 0x2aa1, 0xb60b,
+	0xae11, 0xe055, 0xae21, 0xe167, 0x01a2, 0x2907, 0xaf10, 0xe008,
+	0x001f, 0xe056, 0xe0c2, 0x015c, 0xa202, 0xe0c2, 0x0150, 0xe0c0,
+	0x0150, 0xf7ea, 0xa200, 0xe0c2, 0x0150, 0xe0c0, 0x0151, 0xf7e8,
+	0xe42e, 0xcba6, 0xe0c2, 0x0114, 0xcba8, 0xe0c2, 0x0115, 0xcbaa,
+	0xe0c2, 0x012a, 0xcbac, 0xe0c2, 0x0117, 0xcbae, 0xe0c2, 0x0120,
+	0xcbb0, 0xe0c2, 0x0121, 0xcbb2, 0xe0c2, 0x0123, 0xcbc0, 0xf7f8,
+	0xe0c0, 0x0111, 0xf7e8, 0xf08c, 0xe0c0, 0x0124, 0xe0c2, 0x0124,
+	0xa200, 0xe0c2, 0x0320, 0x2827, 0xe418, 0x0eee, 0xa202, 0xe0c2,
+	0x0110, 0x28e1, 0x4ce2, 0xe418, 0x1163, 0xe42e, 0xa200, 0xe0c2,
+	0x0224, 0xe0c2, 0x0225, 0xe42e, 0xe0c0, 0x0065, 0xaf0a, 0xa812,
+	0xe40a, 0x0f25, 0x2855, 0xf21a, 0xe167, 0x0400, 0xe166, 0x0528,
+	0xd022, 0x0007, 0xe184, 0x0f0b, 0x2917, 0xae08, 0x4d17, 0xae08,
+	0x4d17, 0xae08, 0x4d17, 0x3d16, 0xe190, 0xca28, 0xf7f8, 0xe167,
+	0x0538, 0x2117, 0x4d17, 0xce20, 0xd111, 0x0528, 0xd112, 0x0008,
+	0xd113, 0x0002, 0xca28, 0xf7f8, 0xe162, 0x0536, 0xa200, 0x2a55,
+	0xb632, 0xae10, 0x3d12, 0xa220, 0x3d12, 0xe0c0, 0x0065, 0xaf0a,
+	0xa802, 0xf12a, 0xe162, 0x0520, 0x285a, 0x3d12, 0x285b, 0x3d12,
+	0xe0c0, 0x006b, 0xce20, 0xd111, 0x0520, 0xd112, 0x0004, 0xd113,
+	0x0000, 0xca28, 0xf7f8, 0xe0c0, 0x0065, 0xaf0c, 0xa80e, 0xf0ca,
+	0xe0c0, 0x006a, 0xce20, 0xd112, 0x000c, 0xd111, 0x0536, 0xd113,
+	0x0002, 0xca28, 0xf7f8, 0xa200, 0x3c5b, 0x3c5a, 0x3c56, 0x3c5d,
+	0x3c5e, 0xe42e, 0xe0c1, 0x0044, 0xa80f, 0xe056, 0xe42e, 0xa200,
+	0xe41e, 0x0f52, 0xe42e, 0xe0c1, 0x0044, 0xaf0d, 0xae03, 0xe056,
+	0xe008, 0x003f, 0xe42e, 0xe0c1, 0x0044, 0xaf17, 0xa803, 0xe42e,
+	0xe0c1, 0x0044, 0xaf17, 0xa803, 0xa105, 0xf039, 0xa213, 0xe42e,
+	0xa201, 0xe42e, 0xa203, 0xe0c3, 0x040d, 0xe0c1, 0x0420, 0xa803,
+	0xf7db, 0xe160, 0x0003, 0xe166, 0x0210, 0xe167, 0x0500, 0x28ad,
+	0xf166, 0xa102, 0xcc44, 0xe184, 0x0f95, 0xa200, 0xe41e, 0x0f52,
+	0xaf04, 0xe41e, 0x0f5b, 0xae20, 0x2eae, 0xe056, 0x9f17, 0x2044,
+	0x4c45, 0xae08, 0x9f17, 0xe41e, 0x0f9b, 0xe190, 0xe190, 0xa201,
+	0xe0c3, 0x040d, 0xe42e, 0x2116, 0x4d16, 0x9f17, 0x2116, 0x4d16,
+	0x9f17, 0x2116, 0x4d16, 0x9f17, 0xe42e, 0xe0c0, 0x0044, 0xaf20,
+	0xa802, 0xe428, 0xe0c0, 0x0060, 0xa860, 0xe42a, 0xe0c0, 0x0061,
+	0xa83e, 0xa203, 0xe0c3, 0x040d, 0xcca4, 0xc785, 0xe018, 0xe000,
+	0x0500, 0xe09e, 0xe0c1, 0x0420, 0xa803, 0xf7db, 0xa200, 0xe41e,
+	0x0f57, 0xa80e, 0xaf04, 0xe41e, 0x0f5b, 0xe41e, 0x0f63, 0xe40b,
+	0x0fce, 0xa81e, 0xe41e, 0x0f68, 0xae09, 0xe056, 0xae20, 0xe0c1,
+	0x006e, 0xe009, 0x1fff, 0xe056, 0x9f17, 0xe0c0, 0x0060, 0xa822,
+	0xa122, 0xf04a, 0x2044, 0x4c45, 0xf03e, 0x2045, 0x4c44, 0xae08,
+	0x9f17, 0xe0c0, 0x0062, 0x9f17, 0xe0c0, 0x0063, 0x9f17, 0xe0c0,
+	0x0064, 0x9f17, 0xa201, 0xe0c3, 0x040d, 0xe42e, 0x3c01, 0xa202,
+	0xe0c2, 0x040d, 0xe0c0, 0x0420, 0xa802, 0xf7da, 0x8401, 0xc785,
+	0xe018, 0xe000, 0x0501, 0xe09e, 0x2044, 0x4c45, 0xae08, 0x9f07,
+	0xa200, 0xe0c2, 0x040d, 0xe42e, 0x3c01, 0xa202, 0xe0c2, 0x040d,
+	0xe0c0, 0x0420, 0xa802, 0xf7da, 0x8401, 0xc785, 0xe018, 0xe000,
+	0x0501, 0xe09e, 0x2044, 0x4c45, 0xae08, 0x9f07, 0xa200, 0xe0c2,
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+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe40e, 0x0020, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x0330, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x034a, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x003a, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058,
+	0xa200, 0xe0c2, 0x005a, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xa2fe,
+	0x3cee, 0x3cef, 0x3cec, 0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d,
+	0xce00, 0xf33e, 0xe41e, 0x0164, 0xe09e, 0xa202, 0xae3e, 0x9f07,
+	0xe0c0, 0x005c, 0xe0c1, 0x0059, 0x3eed, 0xa203, 0x5aed, 0xe052,
+	0xf08a, 0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00,
+	0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2, 0x0008, 0xf00e,
+	0x28ee, 0xe412, 0x013d, 0xe190, 0xe0c0, 0x005c, 0xe0c1, 0x0059,
+	0x3eed, 0xa203, 0x5aed, 0xe052, 0xf08a, 0xe0c1, 0x005d, 0xe055,
+	0xe0c3, 0x005d, 0xa202, 0xce00, 0xe0c0, 0x004a, 0xf08a, 0xe41e,
+	0x019c, 0xe408, 0x005c, 0xe40e, 0x0058, 0xe190, 0xe0c0, 0x043d,
+	0xa1ee, 0xf7d8, 0xe004, 0x0060, 0xe0c2, 0x0009, 0xa200, 0xe0c2,
+	0x0009, 0xe0c0, 0x000d, 0xf7e8, 0xe41e, 0x00b2, 0xe41e, 0x00e2,
+	0xe41e, 0x012c, 0xd071, 0x242a, 0xe181, 0xe41e, 0x0164, 0xe09e,
+	0xa202, 0x9f07, 0xe0c0, 0x0049, 0xe0c1, 0x005b, 0xa111, 0xf033,
+	0xe0c0, 0x0048, 0xe0c2, 0x0047, 0xe0c0, 0x0059, 0xae02, 0xe000,
+	0x0330, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a, 0xe008, 0xffff,
+	0x3cee, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11, 0xe056, 0x3cef,
+	0xe40e, 0x0058, 0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2,
+	0x0008, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xe0c0, 0x0059, 0xf7ea,
+	0xa11e, 0xf198, 0xa202, 0xe0c2, 0x0058, 0xe004, 0xca20, 0xae20,
+	0xe005, 0x210a, 0xe056, 0xe0c2, 0x0070, 0xe004, 0x0000, 0xae20,
+	0xe00a, 0x9cea, 0xe0c2, 0x0071, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+	0x0058, 0xf64e, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058, 0xd027,
+	0x0001, 0xe42e, 0xa200, 0xe0c1, 0x005b, 0xf21b, 0xa23c, 0xa103,
+	0xf37b, 0xa24c, 0xa103, 0xf34b, 0xa258, 0xa103, 0xf1db, 0xe004,
+	0x003a, 0xa103, 0xf2db, 0xe004, 0x003f, 0xa103, 0xf29b, 0xe004,
+	0x0045, 0xa103, 0xf25b, 0xa103, 0xf14b, 0xe004, 0x0063, 0xa103,
+	0xf1ab, 0xe004, 0x006a, 0xa107, 0xf1bb, 0xa200, 0xe0c1, 0x005e,
+	0xf17b, 0xa028, 0xf15e, 0xe0c1, 0x005e, 0xf12b, 0xa010, 0xf10e,
+	0xe004, 0x0049, 0xe0c1, 0x005e, 0xf0bb, 0xa010, 0xa103, 0xf08b,
+	0xa010, 0xf06e, 0xe0c1, 0x005e, 0xf03b, 0xe004, 0x0074, 0xae16,
+	0xe0c1, 0x0040, 0xe041, 0xce21, 0xd111, 0x0000, 0xd112, 0x2800,
+	0xd113, 0x000b, 0xe1e1, 0xe42e, 0xe41e, 0x023a, 0xe0c0, 0x0059,
+	0xa102, 0xe42a, 0xe0c0, 0x005b, 0xa810, 0xf058, 0xa206, 0xe41e,
+	0x0153, 0xe42e, 0xe004, 0x0350, 0xe67c, 0xe0c0, 0x005b, 0xa810,
+	0xf058, 0xa204, 0xe41e, 0x0153, 0xe42e, 0xe004, 0x0352, 0xe67c,
+	0xa200, 0xc401, 0xe188, 0x00eb, 0x3d11, 0xe161, 0x00f2, 0xe188,
+	0x0b0d, 0x3d11, 0xe42e, 0x3cec, 0xe0c0, 0x0041, 0xe005, 0x0000,
+	0xae11, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0c00, 0x88ec,
+	0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0059, 0xa106, 0xf048,
+	0xe004, 0x0076, 0xe42e, 0xe0c0, 0x0059, 0xa10c, 0xf038, 0xe004,
+	0x0071, 0xe004, 0x0070, 0xe42e, 0xe0c0, 0x006b, 0xe167, 0x01a0,
+	0x3d07, 0xe0c0, 0x0414, 0xe428, 0xe0c1, 0x0044, 0xa809, 0xae33,
+	0xe0c0, 0x006a, 0xe167, 0x01a0, 0x3517, 0x3d17, 0xe0c0, 0x006b,
+	0xe056, 0x3517, 0x3d07, 0xe42e, 0xe167, 0x01a0, 0x2907, 0xe0c2,
+	0x0151, 0xa204, 0xe0c2, 0x0150, 0xe0c0, 0x0150, 0xa804, 0xf7da,
+	0xa208, 0xe0c2, 0x0150, 0xe42e, 0xe0c0, 0x004a, 0xe42a, 0xe0c0,
+	0x005b, 0xa110, 0xf142, 0xe0c0, 0x0059, 0xa102, 0xe41a, 0x01be,
+	0xe0c0, 0x0059, 0xa106, 0xe41a, 0x01cb, 0xe0c0, 0x0047, 0xe0c2,
+	0x0048, 0xa200, 0xe0c2, 0x004a, 0xa202, 0xe42e, 0xe0c0, 0x0047,
+	0xe0c2, 0x0049, 0xa200, 0xe0c2, 0x004a, 0xe42e, 0xe0c0, 0x004a,
+	0xa802, 0xa23e, 0x3cf0, 0xa202, 0x58f0, 0xe0c2, 0x0078, 0xa220,
+	0xe0c2, 0x0070, 0xe42e, 0xe0c0, 0x004a, 0xa802, 0xa220, 0xe0c2,
+	0x0076, 0xa200, 0xe0c2, 0x0072, 0xa2fc, 0xe0c2, 0x0077, 0xa2fa,
+	0xe0c2, 0x0071, 0xe42e, 0xe0c0, 0x0045, 0xaf04, 0xa80e, 0xa104,
+	0xe428, 0xa202, 0xe0c2, 0x004a, 0xe0c0, 0x0111, 0xf7e8, 0xca28,
+	0xf7f8, 0xca48, 0xa802, 0xf7e8, 0xa208, 0xae14, 0xa102, 0xe190,
+	0xf7e2, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xe0c0, 0x041f, 0xf7e8,
+	0xa200, 0xe0c2, 0x041c, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xe004,
+	0x0078, 0xe0c2, 0x0009, 0xa200, 0xe0c2, 0x0009, 0xe0c0, 0x000d,
+	0xf7e8, 0xe42e, 0xc001, 0x3443, 0x3c42, 0xc000, 0xe42e, 0xc001,
+	0x2c43, 0x2e42, 0xc000, 0xe42a, 0x1c26, 0xf0b4, 0xe04a, 0xaf10,
+	0x1827, 0xf074, 0xe009, 0x00ff, 0x1a28, 0xf034, 0xa202, 0xe42e,
+	0xa2fe, 0xe42e, 0xe41e, 0x023a, 0xd160, 0x0620, 0xe004, 0x0019,
+	0xae18, 0xcec0, 0xe42e, 0xe41e, 0x024f, 0xe000, 0x0040, 0xce50,
+	0xa200, 0xd022, 0x00ff, 0xe184, 0x0236, 0xce52, 0xe190, 0xe41e,
+	0x0257, 0xe42e, 0xa204, 0xae22, 0xcc9e, 0xa200, 0xcc72, 0xcc8c,
+	0xcc8e, 0xe004, 0xa810, 0xae20, 0xe00a, 0x9322, 0xce4a, 0xd16f,
+	0x0003, 0xe190, 0xe190, 0xe190, 0xd16f, 0x0000, 0xe42e, 0xe004,
+	0x0030, 0xce50, 0xca50, 0xa802, 0xf7ea, 0xc000, 0xe42e, 0xe004,
+	0x0020, 0xce50, 0xe42e, 0xa200, 0xe0c2, 0x041c, 0xe42e, 0xe41e,
+	0x02bb, 0xe42a, 0xe0c0, 0x0061, 0xe008, 0x001f, 0xe00a, 0x0100,
+	0xe0c2, 0x041c, 0xe41e, 0x02f1, 0xe41e, 0x032b, 0xae12, 0xe0c2,
+	0x041e, 0xe41e, 0x031b, 0xe42e, 0xe41e, 0x02df, 0xe42a, 0xe0c0,
+	0x041f, 0xf7e8, 0xe0c0, 0x0210, 0xa804, 0xf118, 0xe0c0, 0x0215,
+	0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0216, 0xf0be, 0xe0c0, 0x0213,
+	0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0214, 0xf03e, 0xe0c0, 0x020b,
+	0xe00a, 0x0100, 0xe0c2, 0x041c, 0xe41e, 0x02f1, 0xe41e, 0x032b,
+	0xae12, 0xe0c1, 0x0210, 0xa803, 0xae15, 0xe056, 0xe0c1, 0x0204,
+	0xaf0b, 0xa87f, 0xae07, 0xe056, 0xe0c1, 0x0204, 0xa80f, 0xe056,
+	0xe0c2, 0x041e, 0xe41e, 0x031b, 0xe42e, 0xe0c0, 0x041f, 0xf7e8,
+	0xe0c0, 0x041f, 0xf7e8, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xa200,
+	0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xa203, 0xae19, 0xe052,
+	0xf1da, 0xe0c0, 0x0060, 0xaf08, 0xa806, 0xf18a, 0xe0c0, 0x0060,
+	0xa81e, 0xe016, 0xe0c1, 0x0060, 0xa821, 0xe017, 0xe056, 0xf0ea,
+	0xe0c0, 0x0044, 0xaf12, 0xa806, 0xe016, 0xe0c1, 0x0044, 0xaf17,
+	0xa803, 0xe056, 0xf03a, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xe0c0,
+	0x0044, 0xa203, 0xae19, 0xe052, 0xf0ba, 0xe41e, 0x02bb, 0xf088,
+	0xe0c0, 0x0044, 0xaf12, 0xa806, 0xf038, 0xa202, 0xe42e, 0xa200,
+	0xe42e, 0xe0c0, 0x041c, 0xe008, 0x00ff, 0xcca4, 0xc785, 0xe018,
+	0xe000, 0x0500, 0xa002, 0xae04, 0xe0c2, 0x041a, 0xa202, 0xe0c2,
+	0x0418, 0xe0c0, 0x0419, 0xf7ea, 0xa202, 0xe0c2, 0x0418, 0xe0c0,
+	0x0419, 0xf7ea, 0xe0c0, 0x041b, 0xaf20, 0xa01e, 0xaf08, 0xae28,
+	0xe0c1, 0x041b, 0xe009, 0xffff, 0xa01f, 0xaf09, 0xae09, 0xe056,
+	0xe0c2, 0x041d, 0xe42e, 0xe0c0, 0x041c, 0xe00a, 0x0200, 0xe0c2,
+	0x041c, 0xa228, 0xa102, 0xf7f0, 0xe0c0, 0x041c, 0xe00c, 0x0200,
+	0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xaf04, 0xa802, 0xe42e,
+	0xe40e, 0x04de, 0xe40e, 0x0354, 0xe40e, 0x0358, 0xe40e, 0x035c,
+	0xe40e, 0x0364, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe41e, 0x0368, 0xe40e, 0x00a4,
+	0xe41e, 0x0385, 0xe40e, 0x00a4, 0xe41e, 0x025b, 0xe41e, 0x0450,
+	0xe41e, 0x02ad, 0xe40e, 0x00a4, 0xe41e, 0x039d, 0xe40e, 0x00a4,
+	0xe41e, 0x0148, 0xa200, 0xcc4a, 0xcc4c, 0xd130, 0x0007, 0xd131,
+	0x0000, 0xe41e, 0x0387, 0xe41e, 0x0494, 0xf09a, 0xe41e, 0x03a2,
+	0xf06d, 0xe41e, 0x0669, 0xe41e, 0x0544, 0xe42e, 0xe41e, 0x0544,
+	0xe16a, 0xa200, 0xe0c2, 0x0070, 0xe42e, 0xa202, 0xe42e, 0xe41e,
+	0x0491, 0xe0c0, 0x0040, 0xe005, 0x0049, 0xae17, 0xe042, 0xe005,
+	0x1f00, 0xae03, 0xe042, 0xce20, 0xd111, 0x08a0, 0xd112, 0x0040,
+	0xd113, 0x0003, 0xe41e, 0x0491, 0xe42e, 0xe41e, 0x089e, 0xe41e,
+	0x08fe, 0xe42e, 0xba4e, 0xa186, 0xe408, 0x03fe, 0xba4e, 0xa19c,
+	0xe408, 0x03fe, 0xba4e, 0xa19a, 0xe408, 0x03fe, 0xba4e, 0xa1ac,
+	0xe408, 0x03fe, 0xba4e, 0xba4f, 0xae11, 0xe056, 0x3c00, 0xba4e,
+	0xba4f, 0xae11, 0xe056, 0x3c01, 0xba7e, 0x3402, 0x3c03, 0xba4e,
+	0xba4f, 0xae11, 0xe055, 0x3e12, 0xba4e, 0xba4f, 0xae11, 0xe055,
+	0x3e13, 0xba4e, 0xba4f, 0xae11, 0xe056, 0xba4f, 0xae21, 0xe056,
+	0xba4f, 0xae31, 0xe056, 0x3404, 0x3c05, 0xba4e, 0xba4f, 0xae11,
+	0xe056, 0xba4f, 0xae21, 0xe056, 0xba4f, 0xae31, 0xe056, 0x3406,
+	0x3c07, 0xba7e, 0x3408, 0x3c09, 0xba7e, 0x2812, 0xa01e, 0xaf08,
+	0xae08, 0x3c10, 0x2813, 0xa01e, 0xaf08, 0xae08, 0x3c11, 0x2810,
+	0x3c22, 0xa01e, 0xaf08, 0x3c27, 0x2811, 0x3c23, 0xa01e, 0xaf08,
+	0x3c28, 0x8427, 0x8228, 0xe018, 0x3c26, 0xe42e, 0xe16b, 0xe42e,
+	0xba4e, 0xba4f, 0xae11, 0xe056, 0xba4f, 0xae21, 0xe056, 0xba4f,
+	0xae31, 0xe056, 0xf1da, 0xd022, 0x0007, 0xe184, 0x0410, 0xba4e,
+	0xe190, 0xe190, 0xd039, 0x0000, 0xba4e, 0x3c2b, 0xf088, 0xba4e,
+	0x3c20, 0xba4e, 0x3c51, 0xba4e, 0x3c50, 0xe42e, 0xba4e, 0xba4e,
+	0xba4e, 0xa202, 0x3c20, 0x3c51, 0xa200, 0x3c50, 0xe42e, 0xe16b,
+	0xe42e, 0xba4e, 0xba4f, 0xae11, 0xe056, 0xba4f, 0xae21, 0xe056,
+	0xba4f, 0xae31, 0xe056, 0x3c0a, 0xba7e, 0xe161, 0x0300, 0x8451,
+	0xe182, 0x0180, 0xe018, 0xa102, 0xcc44, 0xe184, 0x0444, 0xba5e,
+	0x3d11, 0x280a, 0xa104, 0x3c0a, 0xf02a, 0xe190, 0x280a, 0xe426,
+	0xa102, 0xcc44, 0xe184, 0x044d, 0xba4e, 0xe190, 0xe190, 0xe42e,
+	0xe41e, 0x06a6, 0xa200, 0x3c82, 0xcc4a, 0xcc4c, 0xd130, 0x0007,
+	0xd131, 0x0000, 0xe0c0, 0x005a, 0xe008, 0xffff, 0x3cee, 0xe41e,
+	0x09c4, 0xe41e, 0x08bd, 0xe41e, 0x093f, 0x2860, 0xe418, 0x0a7c,
+	0xe41e, 0x092f, 0xe41e, 0x0931, 0xe41e, 0x04bf, 0xe41e, 0x050a,
+	0xf09a, 0xa2fe, 0x3c33, 0xa2fc, 0x3c30, 0x3c34, 0xe41e, 0x0985,
+	0xf05e, 0xe41e, 0x025f, 0xe41e, 0x06b5, 0xe41e, 0x0680, 0xe41e,
+	0x09d3, 0xe41e, 0x054a, 0xc84a, 0xc84d, 0xae20, 0xe056, 0xe0c2,
+	0x0053, 0xe42e, 0xe41e, 0x054a, 0xe16a, 0xa200, 0xe0c2, 0x0076,
+	0xe42e, 0xca28, 0xf7f8, 0xe42e, 0xe41e, 0x023a, 0xa206, 0xae1e,
+	0xcec0, 0xd160, 0x0600, 0xe0c0, 0x0060, 0x34b0, 0x3cb1, 0xe0c1,
+	0x0061, 0xae15, 0x36b2, 0x3eb3, 0xe042, 0x34b4, 0x3cb5, 0xe0c0,
+	0x0048, 0x34ba, 0x3cbb, 0x34b6, 0xe008, 0xfe00, 0x3cb7, 0x2cbb,
+	0xe008, 0x01ff, 0x3cbc, 0xe41e, 0x0633, 0xf07d, 0xe41e, 0x0525,
+	0xe41e, 0x050c, 0xa202, 0xe42e, 0xa200, 0xe16a, 0xe42e, 0xa206,
+	0xae1e, 0xcec0, 0xd160, 0x0600, 0xe0c0, 0x0048, 0xe0c2, 0x0051,
+	0x34ba, 0x3cbb, 0x34b6, 0xe008, 0xfe00, 0x3cb7, 0x28bb, 0xe008,
+	0x01ff, 0x3cbc, 0xe41e, 0x05f8, 0xf078, 0xe41e, 0x0525, 0xe41e,
+	0x050c, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0xe41e, 0x04e1,
+	0xe470, 0xca28, 0xf7f8, 0xe004, 0x0080, 0xce24, 0x28bf, 0xae0e,
+	0xce22, 0x24b6, 0x4cb7, 0xce20, 0x24cd, 0x4cce, 0xa806, 0xae02,
+	0xa022, 0xce26, 0xca28, 0xf7f8, 0x24b6, 0x4cb7, 0xe000, 0x0200,
+	0x34b6, 0x3cb7, 0x14b4, 0x1cb5, 0xf054, 0x24b0, 0x4cb1, 0x34b6,
+	0x3cb7, 0xd04c, 0x0000, 0x28bf, 0xae0e, 0xcc6e, 0x28bf, 0xe016,
+	0x3cbf, 0xe42e, 0x28c1, 0xe42e, 0xa200, 0x3cbf, 0xce92, 0xe0c0,
+	0x0043, 0x34cd, 0x3cce, 0xe41e, 0x04e1, 0xe41e, 0x04e1, 0xe128,
+	0xd071, 0x2020, 0xe181, 0x2cbc, 0xa102, 0xf074, 0xcc44, 0xe184,
+	0x0522, 0xba4e, 0xe190, 0xe190, 0xe42e, 0xe004, 0x1495, 0xae20,
+	0xcc9e, 0xd030, 0x0000, 0xd034, 0x0000, 0xd033, 0x0000, 0xd035,
+	0x0000, 0xd036, 0x00ff, 0xd037, 0x0000, 0xd038, 0x0000, 0xd039,
+	0x0000, 0xd04b, 0x0001, 0xd04c, 0x0000, 0xd046, 0x0000, 0xd047,
+	0x0000, 0xd149, 0x0000, 0xe42e, 0x24ba, 0x4cbb, 0x08c2, 0x34ba,
+	0x3cbb, 0xf07e, 0x24ba, 0x4cbb, 0x04c5, 0x0cc6, 0x34ba, 0x3cbb,
+	0x14b4, 0x1cb5, 0xf074, 0x24ba, 0x4cbb, 0x14b2, 0x1cb3, 0x34ba,
+	0x3cbb, 0x24ba, 0x4cbb, 0xe0c2, 0x0048, 0xe0c2, 0x0052, 0xe42e,
+	0xa200, 0x34c5, 0x3cc6, 0xe42e, 0xf0a8, 0x2911, 0xe008, 0xffff,
+	0xae20, 0x2b11, 0xe009, 0xffff, 0xe042, 0xf0fe, 0x2911, 0xe008,
+	0x00ff, 0xae20, 0x2b11, 0xe009, 0xffff, 0xe042, 0xae10, 0x2b11,
+	0xe009, 0xff00, 0xaf11, 0xe042, 0x2ac7, 0xe42b, 0xe049, 0xaf31,
+	0xe009, 0x00ff, 0xe093, 0xe049, 0xaf21, 0xe009, 0x00ff, 0xe095,
+	0xe049, 0xaf11, 0xe009, 0x00ff, 0xe008, 0x00ff, 0xae10, 0xe056,
+	0xae10, 0xe085, 0xe056, 0xae10, 0xe083, 0xe056, 0xe42e, 0xe049,
+	0xa80f, 0xe046, 0xe42e, 0xca29, 0xf7f9, 0xd111, 0x0830, 0xce20,
+	0x26b4, 0x4eb5, 0xe045, 0xe004, 0x0040, 0xe065, 0xaf03, 0xce25,
+	0x3ec0, 0xe41e, 0x05b9, 0xa240, 0x18c0, 0xe426, 0xce24, 0x28c0,
+	0xe000, 0x0830, 0xce22, 0x24b0, 0x4cb1, 0xce20, 0xe41e, 0x05b9,
+	0xe42e, 0xe0c0, 0x0043, 0xa806, 0xae02, 0xa002, 0xce26, 0xca28,
+	0xf7f8, 0xe42e, 0x34c9, 0x3cca, 0xa200, 0x3cbd, 0xe0c0, 0x0049,
+	0x34cb, 0x3ccc, 0xe0c0, 0x0045, 0xaf04, 0x30be, 0xe0c0, 0x0049,
+	0x34b8, 0x3cb9, 0x10cb, 0x1ccc, 0x2abd, 0xb611, 0x3ebd, 0x26b8,
+	0x4eb9, 0x16c9, 0x1eca, 0xf033, 0x06b2, 0x0eb3, 0x16c3, 0x1ec4,
+	0xa200, 0xe423, 0x28be, 0x3cc1, 0xe428, 0x28bd, 0xf648, 0xe41e,
+	0x01db, 0xe0c0, 0x005c, 0xe008, 0x4000, 0xf5da, 0xe0c0, 0x005d,
+	0xe00a, 0x4000, 0xe0c2, 0x005d, 0xa202, 0xce00, 0x3cbd, 0xf53e,
+	0xa218, 0x34c3, 0x3cc4, 0x24ba, 0x4cbb, 0xd027, 0x0000, 0xe41e,
+	0x05c2, 0xd027, 0x0001, 0xf2b8, 0x24ba, 0x4cbb, 0xe41e, 0x0597,
+	0xe095, 0xe41e, 0x059b, 0xe084, 0xaf02, 0xe000, 0x0830, 0xe092,
+	0xe084, 0xa802, 0xe41e, 0x0564, 0x34c5, 0x3cc6, 0xf186, 0x26b2,
+	0x4eb3, 0xe046, 0xf142, 0x24c5, 0x4cc6, 0xa018, 0x34c5, 0x3cc6,
+	0x34c3, 0x3cc4, 0x24ba, 0x4cbb, 0xd027, 0x0000, 0xe41e, 0x05c2,
+	0xd027, 0x0001, 0xf048, 0xa200, 0xe42e, 0xe16b, 0xa200, 0x34c5,
+	0x3cc6, 0xa202, 0xe42e, 0xa202, 0x3cc7, 0xa240, 0x34c3, 0x3cc4,
+	0x24ba, 0x4cbb, 0xd027, 0x0000, 0xe41e, 0x05c2, 0xd027, 0x0001,
+	0xe408, 0x0667, 0x24ba, 0x4cbb, 0xe41e, 0x0597, 0xe095, 0xe41e,
+	0x059b, 0xe084, 0xa00c, 0xaf02, 0xe000, 0x0830, 0xe092, 0xe084,
+	0xa802, 0xe41e, 0x0564, 0xe008, 0xffff, 0x3cc2, 0xa140, 0xf0f4,
+	0x28c2, 0x34c3, 0x3cc4, 0x24ba, 0x4cbb, 0xd027, 0x0000, 0xe41e,
+	0x05c2, 0xd027, 0x0001, 0xf048, 0xa200, 0xe42e, 0xe16b, 0xa202,
+	0xe42e, 0xa200, 0xe0c2, 0x0074, 0xe0c2, 0x0076, 0xe0c2, 0x0077,
+	0x2012, 0x4c13, 0xe0c2, 0x0071, 0xa2fe, 0xe0c2, 0x0072, 0xe0c2,
+	0x006d, 0xa206, 0xe0c2, 0x0073, 0xa202, 0xe0c2, 0x0070, 0xe42e,
+	0xa200, 0xe0c2, 0x0075, 0xe0c2, 0x0078, 0xe0c2, 0x0079, 0x2833,
+	0xe0c2, 0x0071, 0x2882, 0xe0c2, 0x0072, 0x2820, 0xe0c2, 0x0073,
+	0xa202, 0xe0c2, 0x0076, 0x2834, 0xe0c2, 0x0077, 0x2012, 0x4c13,
+	0xe0c2, 0x006f, 0xa200, 0xe0c2, 0x0075, 0x2436, 0x4c3a, 0xe0c2,
+	0x0070, 0xe42e, 0xa200, 0xe0c2, 0x0076, 0xe42e, 0xa200, 0xcc4a,
+	0xcc4c, 0x3c20, 0x3c50, 0x3c24, 0x3c25, 0x3c6a, 0x3c6b, 0x3c29,
+	0x3c80, 0x3c82, 0xa2fe, 0x3c51, 0xe42e, 0xe41e, 0x08c8, 0xe40a,
+	0x0726, 0xe41e, 0x0400, 0xe40d, 0x0726, 0x2a2b, 0xe41b, 0x050a,
+	0xe408, 0x0726, 0xa218, 0xcf02, 0x2860, 0xe418, 0x0956, 0xe41e,
+	0x078c, 0xe41e, 0x0799, 0x2828, 0xa102, 0x3c25, 0x282b, 0xf1c8,
+	0xe41e, 0x0429, 0xe41e, 0x0838, 0xba4e, 0xba4f, 0xae11, 0xe056,
+	0xba4f, 0xae21, 0xe056, 0xba4f, 0xae31, 0xe056, 0x2a2b, 0xb612,
+	0x340b, 0x3c0c, 0x340b, 0x3c0c, 0xba7e, 0xa200, 0xe41e, 0x076d,
+	0xa202, 0xe41e, 0x076d, 0xe41e, 0x0794, 0xcb04, 0xa802, 0xf7e8,
+	0x282b, 0xe418, 0x072a, 0xf128, 0xa212, 0xcf02, 0xcb04, 0xa808,
+	0xf7ea, 0xcb04, 0xa810, 0xf0aa, 0xcb04, 0xaf08, 0xa802, 0xe41e,
+	0x076d, 0xcb04, 0xa806, 0xe418, 0x074e, 0xe0c0, 0x0111, 0xf7e8,
+	0xa202, 0xe0c2, 0x0110, 0x2860, 0xf0ba, 0xa202, 0x3c66, 0x286a,
+	0x4c6b, 0xe01a, 0x3c65, 0xe41e, 0x096f, 0xe41e, 0x09b6, 0xe41e,
+	0x0735, 0xe40a, 0x071d, 0xe40e, 0x06eb, 0xe0c0, 0x0111, 0xf7e8,
+	0x2860, 0xf03a, 0xe41e, 0x09aa, 0xe41e, 0x08f3, 0xe41e, 0x09d3,
+	0xa202, 0xe42e, 0xa206, 0xcf42, 0xa200, 0xe0c2, 0x0224, 0xa214,
+	0xcf02, 0xcb04, 0xa802, 0xf7ea, 0xe42e, 0x2829, 0xa002, 0x3c29,
+	0x2a26, 0xa103, 0xe046, 0xe400, 0x074c, 0x2824, 0xa002, 0x3c24,
+	0x1827, 0xe404, 0x074a, 0x2825, 0xa102, 0x3c25, 0xa200, 0x3c24,
+	0xe404, 0x074c, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xa202, 0x3c80,
+	0x2882, 0xa002, 0x3c82, 0x2036, 0x4c3a, 0xe40a, 0x075e, 0x2820,
+	0xe408, 0x0762, 0xa206, 0xcf42, 0xe40e, 0x076a, 0xa202, 0xcf42,
+	0xe40e, 0x076a, 0xa204, 0xcf42, 0xe0c0, 0x03b0, 0xcf44, 0xe0c0,
+	0x03b1, 0xcf46, 0xa214, 0xcf02, 0xe42e, 0xae10, 0xce30, 0x200b,
+	0x4c0c, 0xe426, 0xe004, 0x00ff, 0xcc44, 0x200b, 0x4c0c, 0xe002,
+	0x0400, 0xaf04, 0xf062, 0x200b, 0x4c0c, 0xaf04, 0xa102, 0xcc44,
+	0xe184, 0x0783, 0xba7e, 0xce32, 0x200b, 0x4c0c, 0xe002, 0x0400,
+	0xb60c, 0x340b, 0x3c0c, 0xe42e, 0x2820, 0xae20, 0x2a28, 0xae11,
+	0xe056, 0x4c27, 0xcf00, 0xe42e, 0x2825, 0xae10, 0x4c24, 0xcf06,
+	0xe42e, 0xa200, 0x2a61, 0x4e64, 0xb692, 0xae08, 0xa90c, 0xe0c2,
+	0x017c, 0xe004, 0x0004, 0xe0c2, 0x017d, 0xa20e, 0xe0c2, 0x0100,
+	0xa200, 0xe0c2, 0x0128, 0x2022, 0x4c23, 0xe0c2, 0x0101, 0xa200,
+	0xe41e, 0x0a2a, 0xe0c2, 0x0102, 0x2820, 0xa802, 0xae06, 0xe0c2,
+	0x0104, 0xe0c0, 0x0414, 0xe418, 0x018c, 0xe0c0, 0x0414, 0xe41a,
+	0x0802, 0xa20e, 0xe0c2, 0x0312, 0xa202, 0xe0c2, 0x0302, 0x2832,
+	0xe0c2, 0x0380, 0x2831, 0xe0c2, 0x0383, 0xa200, 0xe0c2, 0x0302,
+	0xa20e, 0xae0e, 0x2a20, 0xa807, 0xae07, 0xe056, 0xe0c2, 0x0204,
+	0x2831, 0xe0c2, 0x0216, 0x2830, 0xe0c2, 0x0214, 0x2022, 0x4c23,
+	0xe0c2, 0x0205, 0xa200, 0xe0c2, 0x0208, 0xa202, 0xe0c2, 0x0210,
+	0x2040, 0x4c41, 0xe0c2, 0x0211, 0x2042, 0x4c43, 0xe0c2, 0x0212,
+	0xa200, 0xe41e, 0x0a2a, 0xa203, 0xae11, 0xe056, 0xe0c2, 0x0213,
+	0xa200, 0xe0c2, 0x0215, 0x2850, 0xe0c2, 0x0217, 0xa202, 0xe0c2,
+	0x0106, 0xe42e, 0xe167, 0x01a0, 0x2317, 0x4f17, 0xe0c3, 0x0152,
+	0x2b17, 0xe009, 0x00ff, 0xae21, 0x4f07, 0xe0c3, 0x0153, 0xe0c1,
+	0x0101, 0xe0c3, 0x015d, 0xe005, 0x001b, 0x3e91, 0x2831, 0xa53e,
+	0xa400, 0x2a32, 0xa53f, 0xa401, 0xae11, 0xe055, 0xae21, 0xe167,
+	0x01a2, 0x2907, 0xaf10, 0x4491, 0xe055, 0xe0c3, 0x015c, 0xa202,
+	0xe0c2, 0x0150, 0xe0c0, 0x0150, 0xf7ea, 0xa200, 0xe0c2, 0x0150,
+	0xe0c0, 0x0151, 0xf7e8, 0xe42e, 0xa202, 0xe42e, 0xa202, 0xe42e,
+	0xa202, 0xe0c2, 0x013c, 0xa200, 0x3c95, 0x3c93, 0x3c94, 0x3c52,
+	0x8451, 0xc783, 0xe018, 0x3c2a, 0x282a, 0xa102, 0xe404, 0x0898,
+	0x3c2a, 0xa200, 0x3c52, 0x2893, 0xa106, 0xf068, 0xa200, 0x3c93,
+	0x2894, 0xa002, 0x3c94, 0x8493, 0xc783, 0xe018, 0x2a94, 0xe042,
+	0x3c96, 0x2852, 0xa104, 0xe40a, 0x088f, 0xe160, 0x08a0, 0x2895,
+	0xae02, 0x2a52, 0xe042, 0x3c91, 0x8491, 0xe182, 0x0040, 0xe018,
+	0x3c91, 0xe161, 0x0300, 0xe082, 0x0c91, 0xe092, 0x2896, 0xae02,
+	0x2a52, 0xe042, 0x3c92, 0x8492, 0xe182, 0x0040, 0xe018, 0x3c92,
+	0xd022, 0x003f, 0xe184, 0x0888, 0x2a92, 0xe0c3, 0x013e, 0xa003,
+	0x3e92, 0x2910, 0xe083, 0xe042, 0xe094, 0x2902, 0xe0c2, 0x013f,
+	0xa200, 0xe190, 0x2852, 0xa002, 0x3c52, 0xe40e, 0x0859, 0xe190,
+	0x2895, 0xa002, 0x3c95, 0x2893, 0xa002, 0x3c93, 0xe40e, 0x0844,
+	0xe190, 0xa200, 0xe0c2, 0x013c, 0xa202, 0xe42e, 0xa200, 0x3c36,
+	0x3c3a, 0x3c3b, 0x3c3c, 0xa2fe, 0x3c63, 0x3c30, 0x3c31, 0x3c32,
+	0x3c33, 0xe0c0, 0x0061, 0x3c21, 0xe0c0, 0x0060, 0x3c35, 0xe41e,
+	0x0491, 0xe0c0, 0x0042, 0xce20, 0xd111, 0x0200, 0xd112, 0x00c0,
+	0xd113, 0x0003, 0xe41e, 0x0491, 0xe42e, 0xa2fe, 0x3c30, 0xe0c0,
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+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0x0003, 0x0002, 0x0001, 0x0000, 0x0007, 0x0006, 0x0005, 0x0004,
+	0x000b, 0x000a, 0x0009, 0x0008, 0x000f, 0x000e, 0x000d, 0x000c,
+	0x0013, 0x0012, 0x0011, 0x0010, 0x0017, 0x0016, 0x0015, 0x0014,
+	0x001b, 0x001a, 0x0019, 0x0018, 0x001f, 0x001e, 0x001d, 0x001c,
+	0x0023, 0x0022, 0x0021, 0x0020, 0x0027, 0x0026, 0x0025, 0x0024,
+	0x002b, 0x002a, 0x0029, 0x0028, 0x002f, 0x002e, 0x002d, 0x002c,
+	0x0033, 0x0032, 0x0031, 0x0030, 0x0037, 0x0036, 0x0035, 0x0034,
+	0x003b, 0x003a, 0x0039, 0x0038, 0x003f, 0x003e, 0x003d, 0x003c,
+	0xfffe, 0xfffd, 0xfffd, 0xfffd, 0xcccc, 0xcccc, 0xcccc, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0xe40e, 0x0020, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x0318, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x003a, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058,
+	0xa200, 0xe0c2, 0x005a, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xa2fe,
+	0x3cee, 0x3cef, 0x3cec, 0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d,
+	0xce00, 0xf33e, 0xe41e, 0x0164, 0xe09e, 0xa202, 0xae3e, 0x9f07,
+	0xe0c0, 0x005c, 0xe0c1, 0x0059, 0x3eed, 0xa203, 0x5aed, 0xe052,
+	0xf08a, 0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00,
+	0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2, 0x0008, 0xf00e,
+	0x28ee, 0xe412, 0x013d, 0xe190, 0xe0c0, 0x005c, 0xe0c1, 0x0059,
+	0x3eed, 0xa203, 0x5aed, 0xe052, 0xf08a, 0xe0c1, 0x005d, 0xe055,
+	0xe0c3, 0x005d, 0xa202, 0xce00, 0xe0c0, 0x004a, 0xf08a, 0xe41e,
+	0x019c, 0xe408, 0x005c, 0xe40e, 0x0058, 0xe190, 0xe0c0, 0x043d,
+	0xa1ee, 0xf7d8, 0xe004, 0x0060, 0xe0c2, 0x0009, 0xa200, 0xe0c2,
+	0x0009, 0xe0c0, 0x000d, 0xf7e8, 0xe41e, 0x00b2, 0xe41e, 0x00e2,
+	0xe41e, 0x012c, 0xd071, 0x242a, 0xe181, 0xe41e, 0x0164, 0xe09e,
+	0xa202, 0x9f07, 0xe0c0, 0x0049, 0xe0c1, 0x005b, 0xa111, 0xf033,
+	0xe0c0, 0x0048, 0xe0c2, 0x0047, 0xe0c0, 0x0059, 0xae02, 0xe000,
+	0x0318, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a, 0xe008, 0xffff,
+	0x3cee, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11, 0xe056, 0x3cef,
+	0xe40e, 0x0058, 0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2,
+	0x0008, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xe0c0, 0x0059, 0xf7ea,
+	0xa11e, 0xf198, 0xa202, 0xe0c2, 0x0058, 0xe004, 0xca20, 0xae20,
+	0xe005, 0x210a, 0xe056, 0xe0c2, 0x0070, 0xe004, 0x0000, 0xae20,
+	0xe00a, 0x9cea, 0xe0c2, 0x0071, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+	0x0058, 0xf64e, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058, 0xd027,
+	0x0001, 0xe42e, 0xa200, 0xe0c1, 0x005b, 0xf21b, 0xa23c, 0xa103,
+	0xf37b, 0xa24c, 0xa103, 0xf34b, 0xa258, 0xa103, 0xf1db, 0xe004,
+	0x003a, 0xa103, 0xf2db, 0xe004, 0x003f, 0xa103, 0xf29b, 0xe004,
+	0x0045, 0xa103, 0xf25b, 0xa103, 0xf14b, 0xe004, 0x0063, 0xa103,
+	0xf1ab, 0xe004, 0x006a, 0xa107, 0xf1bb, 0xa200, 0xe0c1, 0x005e,
+	0xf17b, 0xa028, 0xf15e, 0xe0c1, 0x005e, 0xf12b, 0xa010, 0xf10e,
+	0xe004, 0x0049, 0xe0c1, 0x005e, 0xf0bb, 0xa010, 0xa103, 0xf08b,
+	0xa010, 0xf06e, 0xe0c1, 0x005e, 0xf03b, 0xe004, 0x0074, 0xae16,
+	0xe0c1, 0x0040, 0xe041, 0xce21, 0xd111, 0x0000, 0xd112, 0x2800,
+	0xd113, 0x000b, 0xe1e1, 0xe42e, 0xe41e, 0x0222, 0xe0c0, 0x0059,
+	0xa102, 0xe42a, 0xe0c0, 0x005b, 0xa810, 0xf058, 0xa206, 0xe41e,
+	0x0153, 0xe42e, 0xe004, 0x0338, 0xe67c, 0xe0c0, 0x005b, 0xa810,
+	0xf058, 0xa204, 0xe41e, 0x0153, 0xe42e, 0xe004, 0x033a, 0xe67c,
+	0xa200, 0xc401, 0xe188, 0x00eb, 0x3d11, 0xe161, 0x00f2, 0xe188,
+	0x0b0d, 0x3d11, 0xe42e, 0x3cec, 0xe0c0, 0x0041, 0xe005, 0x0000,
+	0xae11, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0c00, 0x88ec,
+	0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0059, 0xa106, 0xf048,
+	0xe004, 0x0076, 0xe42e, 0xe0c0, 0x0059, 0xa10c, 0xf038, 0xe004,
+	0x0071, 0xe004, 0x0070, 0xe42e, 0xe0c0, 0x006b, 0xe167, 0x01a0,
+	0x3d07, 0xe0c0, 0x0414, 0xe428, 0xe0c1, 0x0044, 0xa809, 0xae33,
+	0xe0c0, 0x006a, 0xe167, 0x01a0, 0x3517, 0x3d17, 0xe0c0, 0x006b,
+	0xe056, 0x3517, 0x3d07, 0xe42e, 0xe167, 0x01a0, 0x2907, 0xe0c2,
+	0x0151, 0xa204, 0xe0c2, 0x0150, 0xe0c0, 0x0150, 0xa804, 0xf7da,
+	0xa208, 0xe0c2, 0x0150, 0xe42e, 0xe0c0, 0x004a, 0xe42a, 0xe0c0,
+	0x005b, 0xa110, 0xf142, 0xe0c0, 0x0059, 0xa102, 0xe41a, 0x01be,
+	0xe0c0, 0x0059, 0xa106, 0xe41a, 0x01cb, 0xe0c0, 0x0047, 0xe0c2,
+	0x0048, 0xa200, 0xe0c2, 0x004a, 0xa202, 0xe42e, 0xe0c0, 0x0047,
+	0xe0c2, 0x0049, 0xa200, 0xe0c2, 0x004a, 0xe42e, 0xe0c0, 0x004a,
+	0xa802, 0xa23e, 0x3cf0, 0xa202, 0x58f0, 0xe0c2, 0x0078, 0xa220,
+	0xe0c2, 0x0070, 0xe42e, 0xe0c0, 0x004a, 0xa802, 0xa220, 0xe0c2,
+	0x0076, 0xa200, 0xe0c2, 0x0072, 0xa2fc, 0xe0c2, 0x0077, 0xa2fa,
+	0xe0c2, 0x0071, 0xe42e, 0xe0c0, 0x0045, 0xaf04, 0xa80e, 0xa104,
+	0xe428, 0xa202, 0xe0c2, 0x004a, 0xe0c0, 0x0111, 0xf7e8, 0xca28,
+	0xf7f8, 0xca48, 0xa802, 0xf7e8, 0xa208, 0xae14, 0xa102, 0xe190,
+	0xf7e2, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xe0c0, 0x041f, 0xf7e8,
+	0xa200, 0xe0c2, 0x041c, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xe004,
+	0x0078, 0xe0c2, 0x0009, 0xa200, 0xe0c2, 0x0009, 0xe0c0, 0x000d,
+	0xf7e8, 0xe42e, 0xc001, 0x3443, 0x3c42, 0xc000, 0xe42e, 0xc001,
+	0x2c43, 0x2e42, 0xc000, 0xe42a, 0x1c2f, 0xf0b4, 0xe04a, 0xaf10,
+	0x182d, 0xf074, 0xe009, 0x00ff, 0x1a2e, 0xf034, 0xa202, 0xe42e,
+	0xa2fe, 0xe42e, 0xa204, 0xae22, 0xcc9e, 0xa200, 0xcc72, 0xcc8c,
+	0xcc8e, 0xe004, 0xa810, 0xae20, 0xe00a, 0x9322, 0xce4a, 0xd16f,
+	0x0003, 0xe190, 0xe190, 0xe190, 0xd16f, 0x0000, 0xe42e, 0xe004,
+	0x0030, 0xce50, 0xca50, 0xa802, 0xf7ea, 0xc000, 0xe42e, 0xe004,
+	0x0020, 0xce50, 0xe42e, 0xa200, 0xe0c2, 0x041c, 0xe42e, 0xe41e,
+	0x02a3, 0xe42a, 0xe0c0, 0x0061, 0xe008, 0x001f, 0xe00a, 0x0100,
+	0xe0c2, 0x041c, 0xe41e, 0x02d9, 0xe41e, 0x0313, 0xae12, 0xe0c2,
+	0x041e, 0xe41e, 0x0303, 0xe42e, 0xe41e, 0x02c7, 0xe42a, 0xe0c0,
+	0x041f, 0xf7e8, 0xe0c0, 0x0210, 0xa804, 0xf118, 0xe0c0, 0x0215,
+	0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0216, 0xf0be, 0xe0c0, 0x0213,
+	0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0214, 0xf03e, 0xe0c0, 0x020b,
+	0xe00a, 0x0100, 0xe0c2, 0x041c, 0xe41e, 0x02d9, 0xe41e, 0x0313,
+	0xae12, 0xe0c1, 0x0210, 0xa803, 0xae15, 0xe056, 0xe0c1, 0x0204,
+	0xaf0b, 0xa87f, 0xae07, 0xe056, 0xe0c1, 0x0204, 0xa80f, 0xe056,
+	0xe0c2, 0x041e, 0xe41e, 0x0303, 0xe42e, 0xe0c0, 0x041f, 0xf7e8,
+	0xe0c0, 0x041f, 0xf7e8, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xa200,
+	0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xa203, 0xae19, 0xe052,
+	0xf1da, 0xe0c0, 0x0060, 0xaf08, 0xa806, 0xf18a, 0xe0c0, 0x0060,
+	0xa81e, 0xe016, 0xe0c1, 0x0060, 0xa821, 0xe017, 0xe056, 0xf0ea,
+	0xe0c0, 0x0044, 0xaf12, 0xa806, 0xe016, 0xe0c1, 0x0044, 0xaf17,
+	0xa803, 0xe056, 0xf03a, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xe0c0,
+	0x0044, 0xa203, 0xae19, 0xe052, 0xf0ba, 0xe41e, 0x02a3, 0xf088,
+	0xe0c0, 0x0044, 0xaf12, 0xa806, 0xf038, 0xa202, 0xe42e, 0xa200,
+	0xe42e, 0xe0c0, 0x041c, 0xe008, 0x00ff, 0xcca4, 0xc785, 0xe018,
+	0xe000, 0x0500, 0xa002, 0xae04, 0xe0c2, 0x041a, 0xa202, 0xe0c2,
+	0x0418, 0xe0c0, 0x0419, 0xf7ea, 0xa202, 0xe0c2, 0x0418, 0xe0c0,
+	0x0419, 0xf7ea, 0xe0c0, 0x041b, 0xaf20, 0xa01e, 0xaf08, 0xae28,
+	0xe0c1, 0x041b, 0xe009, 0xffff, 0xa01f, 0xaf09, 0xae09, 0xe056,
+	0xe0c2, 0x041d, 0xe42e, 0xe0c0, 0x041c, 0xe00a, 0x0200, 0xe0c2,
+	0x041c, 0xa228, 0xa102, 0xf7f0, 0xe0c0, 0x041c, 0xe00c, 0x0200,
+	0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xaf04, 0xa802, 0xe42e,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
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+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe40e, 0x0020, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x0330, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x034a, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x003a, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058,
+	0xa200, 0xe0c2, 0x005a, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xa2fe,
+	0x3cee, 0x3cef, 0x3cec, 0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d,
+	0xce00, 0xf33e, 0xe41e, 0x0164, 0xe09e, 0xa202, 0xae3e, 0x9f07,
+	0xe0c0, 0x005c, 0xe0c1, 0x0059, 0x3eed, 0xa203, 0x5aed, 0xe052,
+	0xf08a, 0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00,
+	0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2, 0x0008, 0xf00e,
+	0x28ee, 0xe412, 0x013d, 0xe190, 0xe0c0, 0x005c, 0xe0c1, 0x0059,
+	0x3eed, 0xa203, 0x5aed, 0xe052, 0xf08a, 0xe0c1, 0x005d, 0xe055,
+	0xe0c3, 0x005d, 0xa202, 0xce00, 0xe0c0, 0x004a, 0xf08a, 0xe41e,
+	0x019c, 0xe408, 0x005c, 0xe40e, 0x0058, 0xe190, 0xe0c0, 0x043d,
+	0xa1ee, 0xf7d8, 0xe004, 0x0060, 0xe0c2, 0x0009, 0xa200, 0xe0c2,
+	0x0009, 0xe0c0, 0x000d, 0xf7e8, 0xe41e, 0x00b2, 0xe41e, 0x00e2,
+	0xe41e, 0x012c, 0xd071, 0x242a, 0xe181, 0xe41e, 0x0164, 0xe09e,
+	0xa202, 0x9f07, 0xe0c0, 0x0049, 0xe0c1, 0x005b, 0xa111, 0xf033,
+	0xe0c0, 0x0048, 0xe0c2, 0x0047, 0xe0c0, 0x0059, 0xae02, 0xe000,
+	0x0330, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a, 0xe008, 0xffff,
+	0x3cee, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11, 0xe056, 0x3cef,
+	0xe40e, 0x0058, 0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2,
+	0x0008, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xe0c0, 0x0059, 0xf7ea,
+	0xa11e, 0xf198, 0xa202, 0xe0c2, 0x0058, 0xe004, 0xca20, 0xae20,
+	0xe005, 0x210a, 0xe056, 0xe0c2, 0x0070, 0xe004, 0x0000, 0xae20,
+	0xe00a, 0x9cea, 0xe0c2, 0x0071, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+	0x0058, 0xf64e, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058, 0xd027,
+	0x0001, 0xe42e, 0xa200, 0xe0c1, 0x005b, 0xf21b, 0xa23c, 0xa103,
+	0xf37b, 0xa24c, 0xa103, 0xf34b, 0xa258, 0xa103, 0xf1db, 0xe004,
+	0x003a, 0xa103, 0xf2db, 0xe004, 0x003f, 0xa103, 0xf29b, 0xe004,
+	0x0045, 0xa103, 0xf25b, 0xa103, 0xf14b, 0xe004, 0x0063, 0xa103,
+	0xf1ab, 0xe004, 0x006a, 0xa107, 0xf1bb, 0xa200, 0xe0c1, 0x005e,
+	0xf17b, 0xa028, 0xf15e, 0xe0c1, 0x005e, 0xf12b, 0xa010, 0xf10e,
+	0xe004, 0x0049, 0xe0c1, 0x005e, 0xf0bb, 0xa010, 0xa103, 0xf08b,
+	0xa010, 0xf06e, 0xe0c1, 0x005e, 0xf03b, 0xe004, 0x0074, 0xae16,
+	0xe0c1, 0x0040, 0xe041, 0xce21, 0xd111, 0x0000, 0xd112, 0x2800,
+	0xd113, 0x000b, 0xe1e1, 0xe42e, 0xe41e, 0x023a, 0xe0c0, 0x0059,
+	0xa102, 0xe42a, 0xe0c0, 0x005b, 0xa810, 0xf058, 0xa206, 0xe41e,
+	0x0153, 0xe42e, 0xe004, 0x0350, 0xe67c, 0xe0c0, 0x005b, 0xa810,
+	0xf058, 0xa204, 0xe41e, 0x0153, 0xe42e, 0xe004, 0x0352, 0xe67c,
+	0xa200, 0xc401, 0xe188, 0x00eb, 0x3d11, 0xe161, 0x00f2, 0xe188,
+	0x0b0d, 0x3d11, 0xe42e, 0x3cec, 0xe0c0, 0x0041, 0xe005, 0x0000,
+	0xae11, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0c00, 0x88ec,
+	0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0059, 0xa106, 0xf048,
+	0xe004, 0x0076, 0xe42e, 0xe0c0, 0x0059, 0xa10c, 0xf038, 0xe004,
+	0x0071, 0xe004, 0x0070, 0xe42e, 0xe0c0, 0x006b, 0xe167, 0x01a0,
+	0x3d07, 0xe0c0, 0x0414, 0xe428, 0xe0c1, 0x0044, 0xa809, 0xae33,
+	0xe0c0, 0x006a, 0xe167, 0x01a0, 0x3517, 0x3d17, 0xe0c0, 0x006b,
+	0xe056, 0x3517, 0x3d07, 0xe42e, 0xe167, 0x01a0, 0x2907, 0xe0c2,
+	0x0151, 0xa204, 0xe0c2, 0x0150, 0xe0c0, 0x0150, 0xa804, 0xf7da,
+	0xa208, 0xe0c2, 0x0150, 0xe42e, 0xe0c0, 0x004a, 0xe42a, 0xe0c0,
+	0x005b, 0xa110, 0xf142, 0xe0c0, 0x0059, 0xa102, 0xe41a, 0x01be,
+	0xe0c0, 0x0059, 0xa106, 0xe41a, 0x01cb, 0xe0c0, 0x0047, 0xe0c2,
+	0x0048, 0xa200, 0xe0c2, 0x004a, 0xa202, 0xe42e, 0xe0c0, 0x0047,
+	0xe0c2, 0x0049, 0xa200, 0xe0c2, 0x004a, 0xe42e, 0xe0c0, 0x004a,
+	0xa802, 0xa23e, 0x3cf0, 0xa202, 0x58f0, 0xe0c2, 0x0078, 0xa220,
+	0xe0c2, 0x0070, 0xe42e, 0xe0c0, 0x004a, 0xa802, 0xa220, 0xe0c2,
+	0x0076, 0xa200, 0xe0c2, 0x0072, 0xa2fc, 0xe0c2, 0x0077, 0xa2fa,
+	0xe0c2, 0x0071, 0xe42e, 0xe0c0, 0x0045, 0xaf04, 0xa80e, 0xa104,
+	0xe428, 0xa202, 0xe0c2, 0x004a, 0xe0c0, 0x0111, 0xf7e8, 0xca28,
+	0xf7f8, 0xca48, 0xa802, 0xf7e8, 0xa208, 0xae14, 0xa102, 0xe190,
+	0xf7e2, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xe0c0, 0x041f, 0xf7e8,
+	0xa200, 0xe0c2, 0x041c, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xe004,
+	0x0078, 0xe0c2, 0x0009, 0xa200, 0xe0c2, 0x0009, 0xe0c0, 0x000d,
+	0xf7e8, 0xe42e, 0xc001, 0x3443, 0x3c42, 0xc000, 0xe42e, 0xc001,
+	0x2c43, 0x2e42, 0xc000, 0xe42a, 0x1c0e, 0xf0b4, 0xe04a, 0xaf10,
+	0x180c, 0xf074, 0xe009, 0x00ff, 0x1a0d, 0xf034, 0xa202, 0xe42e,
+	0xa2fe, 0xe42e, 0xe41e, 0x023a, 0xd160, 0x0620, 0xe004, 0x0019,
+	0xae18, 0xcec0, 0xe42e, 0xe41e, 0x024f, 0xe000, 0x0040, 0xce50,
+	0xa200, 0xd022, 0x00ff, 0xe184, 0x0236, 0xce52, 0xe190, 0xe41e,
+	0x0257, 0xe42e, 0xa204, 0xae22, 0xcc9e, 0xa200, 0xcc72, 0xcc8c,
+	0xcc8e, 0xe004, 0xa810, 0xae20, 0xe00a, 0x9322, 0xce4a, 0xd16f,
+	0x0003, 0xe190, 0xe190, 0xe190, 0xd16f, 0x0000, 0xe42e, 0xe004,
+	0x0030, 0xce50, 0xca50, 0xa802, 0xf7ea, 0xc000, 0xe42e, 0xe004,
+	0x0020, 0xce50, 0xe42e, 0xa200, 0xe0c2, 0x041c, 0xe42e, 0xe41e,
+	0x02bb, 0xe42a, 0xe0c0, 0x0061, 0xe008, 0x001f, 0xe00a, 0x0100,
+	0xe0c2, 0x041c, 0xe41e, 0x02f1, 0xe41e, 0x032b, 0xae12, 0xe0c2,
+	0x041e, 0xe41e, 0x031b, 0xe42e, 0xe41e, 0x02df, 0xe42a, 0xe0c0,
+	0x041f, 0xf7e8, 0xe0c0, 0x0210, 0xa804, 0xf118, 0xe0c0, 0x0215,
+	0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0216, 0xf0be, 0xe0c0, 0x0213,
+	0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0214, 0xf03e, 0xe0c0, 0x020b,
+	0xe00a, 0x0100, 0xe0c2, 0x041c, 0xe41e, 0x02f1, 0xe41e, 0x032b,
+	0xae12, 0xe0c1, 0x0210, 0xa803, 0xae15, 0xe056, 0xe0c1, 0x0204,
+	0xaf0b, 0xa87f, 0xae07, 0xe056, 0xe0c1, 0x0204, 0xa80f, 0xe056,
+	0xe0c2, 0x041e, 0xe41e, 0x031b, 0xe42e, 0xe0c0, 0x041f, 0xf7e8,
+	0xe0c0, 0x041f, 0xf7e8, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8, 0xa200,
+	0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xa203, 0xae19, 0xe052,
+	0xf1da, 0xe0c0, 0x0060, 0xaf08, 0xa806, 0xf18a, 0xe0c0, 0x0060,
+	0xa81e, 0xe016, 0xe0c1, 0x0060, 0xa821, 0xe017, 0xe056, 0xf0ea,
+	0xe0c0, 0x0044, 0xaf12, 0xa806, 0xe016, 0xe0c1, 0x0044, 0xaf17,
+	0xa803, 0xe056, 0xf03a, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xe0c0,
+	0x0044, 0xa203, 0xae19, 0xe052, 0xf0ba, 0xe41e, 0x02bb, 0xf088,
+	0xe0c0, 0x0044, 0xaf12, 0xa806, 0xf038, 0xa202, 0xe42e, 0xa200,
+	0xe42e, 0xe0c0, 0x041c, 0xe008, 0x00ff, 0xcca4, 0xc785, 0xe018,
+	0xe000, 0x0500, 0xa002, 0xae04, 0xe0c2, 0x041a, 0xa202, 0xe0c2,
+	0x0418, 0xe0c0, 0x0419, 0xf7ea, 0xa202, 0xe0c2, 0x0418, 0xe0c0,
+	0x0419, 0xf7ea, 0xe0c0, 0x041b, 0xaf20, 0xa01e, 0xaf08, 0xae28,
+	0xe0c1, 0x041b, 0xe009, 0xffff, 0xa01f, 0xaf09, 0xae09, 0xe056,
+	0xe0c2, 0x041d, 0xe42e, 0xe0c0, 0x041c, 0xe00a, 0x0200, 0xe0c2,
+	0x041c, 0xa228, 0xa102, 0xf7f0, 0xe0c0, 0x041c, 0xe00c, 0x0200,
+	0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xaf04, 0xa802, 0xe42e,
+	0xe40e, 0x0edd, 0xe40e, 0x0354, 0xe40e, 0x0358, 0xe40e, 0x035c,
+	0xe40e, 0x0364, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x0368,
+	0xe40e, 0x036a, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe41e, 0x0c24, 0xe40e, 0x00a4,
+	0xe41e, 0x0c54, 0xe40e, 0x00a4, 0xe41e, 0x025b, 0xe41e, 0x0c5e,
+	0xe41e, 0x02ad, 0xe40e, 0x00a4, 0xe41e, 0x0c55, 0xe40e, 0x00a4,
+	0xe40e, 0x00a4, 0xe41e, 0x0cba, 0xe40e, 0x00a4, 0xa202, 0xcf22,
+	0xa202, 0xe42e, 0xa204, 0xcf22, 0xa202, 0xe42e, 0xe008, 0x00ff,
+	0xae08, 0xa908, 0xcf22, 0xe190, 0xcb22, 0xaf18, 0xa802, 0xe42e,
+	0xe004, 0x0080, 0xae08, 0xa908, 0xcf22, 0xe190, 0xcb22, 0xaf18,
+	0xa802, 0xe42e, 0xa102, 0xcc44, 0xa201, 0xe184, 0x0399, 0xe004,
+	0x0080, 0xae08, 0xa908, 0xcf22, 0xe190, 0xcb22, 0xaf18, 0xa802,
+	0xae03, 0xe055, 0xe04a, 0xe42e, 0xd022, 0x0006, 0xa201, 0xe184,
+	0x03ab, 0xe004, 0x0080, 0xae08, 0xa908, 0xcf22, 0xe190, 0xcb22,
+	0xaf18, 0xa802, 0xae03, 0xe055, 0xe04a, 0xae02, 0xb634, 0xe42e,
+	0xd022, 0x0007, 0xa201, 0xe184, 0x03bf, 0xe004, 0x0080, 0xae08,
+	0xa908, 0xcf22, 0xe190, 0xcb22, 0xaf18, 0xa802, 0xae03, 0xe055,
+	0xe04a, 0xe42e, 0xe004, 0x0080, 0xae08, 0xa908, 0xcf22, 0xe190,
+	0xcb22, 0xaf18, 0xa802, 0xe42e, 0xe004, 0x00f0, 0xa908, 0xcf02,
+	0xe42e, 0xd130, 0x0007, 0xd131, 0x0002, 0xa203, 0xae03, 0x2812,
+	0xe016, 0xe055, 0xae03, 0x2819, 0xe055, 0xae03, 0x2818, 0xe055,
+	0xae03, 0x282b, 0xe055, 0xae11, 0x280c, 0xe055, 0xae11, 0x280d,
+	0xe055, 0xcf01, 0xa200, 0x3c80, 0x2a12, 0xe017, 0x2819, 0x4418,
+	0xe056, 0x3080, 0xe166, 0x0202, 0x290e, 0xae10, 0x4d0e, 0xae10,
+	0x4d06, 0xae10, 0x4c2f, 0xcf24, 0xe41e, 0x0567, 0x2870, 0xf08a,
+	0x2812, 0xf048, 0xe41e, 0x0539, 0xf03e, 0xe41e, 0x054a, 0x2812,
+	0xe42a, 0xe166, 0x0206, 0x290e, 0xae10, 0x4d0e, 0xae10, 0x4d0e,
+	0xae10, 0x4d06, 0xcf30, 0xe166, 0x0209, 0x290e, 0xae10, 0x4d0e,
+	0xae10, 0x4d06, 0xcf32, 0x282e, 0xae10, 0x4c2d, 0xae10, 0x4c2c,
+	0xcf34, 0xe166, 0x020a, 0x2916, 0x2b16, 0xae21, 0xe056, 0xe166,
+	0x021d, 0x2b16, 0xae11, 0xe056, 0x2b16, 0xae31, 0xe056, 0xcf26,
+	0xe166, 0x020f, 0x290e, 0xae10, 0x4d0e, 0xae10, 0x4d0e, 0xae10,
+	0x4d06, 0xcf28, 0xe166, 0x0212, 0x290e, 0xae10, 0x4d0e, 0xae10,
+	0x4d06, 0xcf2a, 0xe166, 0x0222, 0x290e, 0xae10, 0x4d0e, 0xae10,
+	0x4d0e, 0xae10, 0x4d06, 0xcf2c, 0xe166, 0x0225, 0x290e, 0xae10,
+	0x4d0e, 0xae10, 0x4d06, 0xcf2e, 0xe166, 0x0227, 0x290e, 0xae10,
+	0x4d06, 0xae10, 0xe166, 0x0214, 0x4d0e, 0xae10, 0x4d06, 0xcf36,
+	0xe166, 0x0218, 0x290e, 0xae10, 0x4d0e, 0xae10, 0x4d0e, 0xae10,
+	0x4d06, 0xe005, 0x00f8, 0xe00b, 0x8000, 0xcf3b, 0xcf3c, 0xe190,
+	0xe166, 0x021c, 0x290e, 0xae10, 0x4d0e, 0xae10, 0x4d0e, 0xae10,
+	0x4d06, 0xe005, 0x00f8, 0xe00b, 0x8001, 0xcf3b, 0xcf3c, 0xe190,
+	0xe166, 0x022b, 0x290e, 0xae10, 0x4d0e, 0xae10, 0x4d0e, 0xae10,
+	0x4d06, 0xe005, 0x00fc, 0xe00b, 0x8000, 0xcf3b, 0xcf3c, 0xe190,
+	0xe166, 0x022f, 0x290e, 0xae10, 0x4d0e, 0xae10, 0x4d0e, 0xae10,
+	0x4d06, 0xe005, 0x00fc, 0xe00b, 0x8001, 0xcf3b, 0xcf3c, 0xe190,
+	0xe42e, 0xa201, 0x281f, 0xe055, 0xae11, 0x2822, 0xe055, 0xae0d,
+	0x287f, 0xe055, 0xae07, 0x281e, 0xe055, 0xae0d, 0x281d, 0xe055,
+	0xae03, 0x281b, 0xe055, 0xcfa1, 0xa201, 0xe166, 0x0680, 0x2916,
+	0xe008, 0x00ff, 0xe055, 0x2916, 0xe008, 0x00ff, 0xae10, 0xe055,
+	0x2916, 0xe008, 0x00ff, 0xae20, 0xe055, 0x2916, 0xe008, 0x00ff,
+	0xae30, 0xe055, 0xcfa3, 0xa201, 0xe166, 0x0684, 0x2916, 0xe008,
+	0x00ff, 0xe055, 0x2916, 0xe008, 0x00ff, 0xae10, 0xe055, 0x2916,
+	0xe008, 0x00ff, 0xae20, 0xe055, 0x2916, 0xe008, 0x00ff, 0xae30,
+	0xe055, 0xcfa5, 0xa201, 0xe166, 0x068c, 0x2916, 0xe008, 0x00ff,
+	0xe055, 0x2916, 0xe008, 0x00ff, 0xae10, 0xe055, 0x2916, 0xe008,
+	0x00ff, 0xae20, 0xe055, 0x2916, 0xe008, 0x00ff, 0xae30, 0xe055,
+	0xcfa7, 0xa201, 0xe166, 0x0688, 0x2916, 0xe008, 0x00ff, 0xe055,
+	0x2916, 0xe008, 0x00ff, 0xae10, 0xe055, 0x2916, 0xe008, 0x00ff,
+	0xae20, 0xe055, 0x2916, 0xe008, 0x00ff, 0xae30, 0xe055, 0xcfa9,
+	0xe005, 0x0080, 0xae21, 0xe00b, 0x0100, 0xcfab, 0xe005, 0x011f,
+	0xae21, 0xe004, 0x013f, 0xe055, 0xcfad, 0xe005, 0x009f, 0xae21,
+	0xe004, 0x00bf, 0xe055, 0xcfb7, 0xa200, 0xcfb0, 0xe41e, 0x0560,
+	0xe42e, 0x2875, 0xae10, 0x4c76, 0xcf06, 0xe42e, 0xa200, 0x4c72,
+	0xae02, 0x4c74, 0xae02, 0x4c71, 0xae02, 0x4c73, 0xae08, 0x3c84,
+	0xe42e, 0xe004, 0x001f, 0xae20, 0xe00a, 0x0000, 0xcf40, 0xe004,
+	0x0100, 0xcf42, 0xe005, 0x011f, 0xae21, 0xe004, 0x013f, 0xe055,
+	0xcf45, 0xe42e, 0xe004, 0x00ff, 0xae20, 0xe00a, 0x0000, 0xcf60,
+	0xe004, 0x0100, 0xcf62, 0xe005, 0x011f, 0xae21, 0xe004, 0x013f,
+	0xe055, 0xcf65, 0x2828, 0xae02, 0x4c27, 0xae04, 0xcf68, 0xe42e,
+	0xe004, 0x001f, 0xae20, 0xe00a, 0x0000, 0xcfc0, 0xe42e, 0xe004,
+	0x0080, 0x3c00, 0xe166, 0x0230, 0xe160, 0x0002, 0x2800, 0xae10,
+	0x4d16, 0xcf38, 0x2a00, 0xae07, 0xd022, 0x0004, 0xe184, 0x057f,
+	0xe04a, 0xae10, 0x8116, 0x4d0e, 0xae10, 0x4d36, 0xcf3e, 0xa003,
+	0xa203, 0x2800, 0xa806, 0xa104, 0xb655, 0x2800, 0xe042, 0x3c00,
+	0xaf10, 0xf028, 0xf64e, 0xe42e, 0xa2fe, 0x3c34, 0x3c35, 0x3c36,
+	0x3c37, 0x3c3c, 0xa200, 0x3c38, 0x3c39, 0x3c3d, 0x3c3e, 0x3c3b,
+	0x3c3a, 0xe0c0, 0x0061, 0x3c32, 0xe0c0, 0x0060, 0x3c33, 0xe41e,
+	0x0ccc, 0xe0c0, 0x0042, 0xce20, 0xd111, 0x0700, 0xd112, 0x00c0,
+	0xd113, 0x0003, 0xca29, 0xf7f9, 0xa204, 0xe41e, 0x13cd, 0xa202,
+	0xe42e, 0xa2fc, 0x3c34, 0xe0c0, 0x0054, 0x2638, 0x4e39, 0xe052,
+	0x3c39, 0x3438, 0xa202, 0xe42e, 0x2835, 0x3c34, 0x2834, 0xa002,
+	0x2a33, 0xe045, 0xb616, 0x3c34, 0x2a35, 0xe045, 0xf059, 0xa2fe,
+	0x3c34, 0xa200, 0xe42e, 0x2a36, 0xe045, 0xf71b, 0x2a37, 0xe045,
+	0xf6eb, 0x2438, 0x4c39, 0x5c34, 0xa802, 0xf698, 0x2814, 0xf08a,
+	0xa202, 0x5834, 0x2638, 0x4e39, 0xe056, 0x3c39, 0x3438, 0xa202,
+	0xe42e, 0xa200, 0x3c98, 0x3c99, 0x2a35, 0x282a, 0xf028, 0x2a34,
+	0x3e99, 0x2826, 0xf0fa, 0xa102, 0xf048, 0x2899, 0x3c37, 0xf0ae,
+	0xa102, 0xf048, 0x2836, 0x3c37, 0xf05e, 0xa2fe, 0x3c98, 0xa200,
+	0x3c37, 0x2825, 0xf0fa, 0xa102, 0xf048, 0x2899, 0x3c36, 0xf0ae,
+	0xa102, 0xf048, 0x2837, 0x3c36, 0xf05e, 0xa2fe, 0x3c98, 0xa200,
+	0x3c36, 0x2823, 0xf03a, 0x2834, 0x3c36, 0x2824, 0xf03a, 0x2834,
+	0x3c37, 0x282a, 0xf048, 0x2834, 0x3c3c, 0xf04e, 0x2834, 0x3c35,
+	0x3c3c, 0x243a, 0x4c3b, 0xa002, 0x3c3b, 0x343a, 0xa200, 0x2a35,
+	0xf045, 0xa203, 0x5a35, 0xe056, 0x2a36, 0xf045, 0xa203, 0x5a36,
+	0xe056, 0x2a37, 0xf045, 0xa203, 0x5a37, 0xe056, 0x2a34, 0xf045,
+	0xa203, 0x5a34, 0xe056, 0x343d, 0x3c3e, 0x2898, 0xf038, 0xa202,
+	0xe42e, 0xa200, 0xe42e, 0xe0c0, 0x0041, 0xe005, 0x0026, 0xae11,
+	0xe042, 0xe41e, 0x0678, 0x3442, 0x3c43, 0xe000, 0x08a0, 0xe41e,
+	0x0678, 0x3447, 0x3c48, 0xe000, 0x0ac0, 0xe0c0, 0x0046, 0xe005,
+	0x002c, 0xae15, 0xe042, 0xe41e, 0x0678, 0x344a, 0x3c4b, 0xe42e,
+	0xe41e, 0x0174, 0xe167, 0x06b5, 0xe166, 0x0064, 0xd022, 0x0003,
+	0xe184, 0x0664, 0x9e16, 0x3517, 0x3d17, 0xe0c0, 0x006c, 0x3444,
+	0x3c45, 0xe42e, 0xe0c0, 0x0050, 0xe049, 0xe008, 0x007f, 0x3c41,
+	0xaf11, 0xe009, 0x007f, 0x3e40, 0x4641, 0x3e41, 0xa202, 0xe42e,
+	0xa00e, 0xaf06, 0xae06, 0xe42e, 0xe41e, 0x068c, 0xe40a, 0x068a,
+	0xe41e, 0x06a2, 0xe40a, 0x068a, 0xe41e, 0x06e4, 0xe40a, 0x068a,
+	0xa202, 0xe42e, 0xa200, 0xe42e, 0xba4e, 0xa188, 0xf128, 0xba4e,
+	0xa196, 0xf0f8, 0xba4e, 0xa192, 0xf0c8, 0xba4e, 0xa18c, 0xf098,
+	0xd022, 0x001b, 0xe184, 0x069d, 0xba4e, 0xe190, 0xa202, 0xe42e,
+	0xa200, 0xe42e, 0xba4e, 0x3c00, 0xba4e, 0x3c01, 0xba4e, 0x3c02,
+	0xba4e, 0x3c03, 0x2803, 0xae10, 0x4c02, 0xae10, 0x4c01, 0xae10,
+	0x4c00, 0x346a, 0x3c6b, 0xd022, 0x0007, 0xe184, 0x06b8, 0xba4e,
+	0xe190, 0xe190, 0xa200, 0xcc72, 0x3cb7, 0xa202, 0xe42e, 0xba3e,
+	0xe005, 0x0044, 0xae11, 0xa997, 0xae11, 0xa993, 0xae11, 0xa98d,
+	0xe046, 0xe41a, 0x068c, 0xe42e, 0xe41e, 0x06bf, 0xe41e, 0x06a2,
+	0xf09a, 0xe41e, 0x06e4, 0xf06a, 0xe41e, 0x08f0, 0xf03a, 0xa202,
+	0xe42e, 0xa200, 0xe42e, 0xa202, 0x3c70, 0xe41e, 0x07a3, 0xf03a,
+	0xa202, 0xe42e, 0xa200, 0xe42e, 0xa200, 0x3c82, 0xba4e, 0xba4f,
+	0xae11, 0xe056, 0xba4f, 0xae21, 0xe055, 0xe04a, 0xa802, 0x3c12,
+	0xe04a, 0xaf02, 0xa80e, 0x3c13, 0xe04a, 0xaf08, 0xa802, 0x3c14,
+	0xe04a, 0xaf0a, 0x3415, 0x3c16, 0x28b7, 0xa006, 0x3cb7, 0xe41e,
+	0x08cc, 0x2812, 0xf07a, 0xe0c0, 0x0059, 0xa102, 0xe40a, 0x0754,
+	0xf3de, 0x2808, 0x3c94, 0x2809, 0x3c95, 0xba4e, 0xe005, 0x009d,
+	0xe046, 0xe408, 0x0756, 0xba4e, 0xe005, 0x0001, 0xe046, 0xe408,
+	0x0756, 0xba4e, 0xe005, 0x002a, 0xe046, 0xe408, 0x0756, 0xba4e,
+	0xe049, 0xba4e, 0xae10, 0xe055, 0xe04a, 0xe008, 0x3fff, 0x3c08,
+	0xe04a, 0xaf1c, 0xa806, 0x3c0a, 0xba4e, 0xe049, 0xba4e, 0xae10,
+	0xe055, 0xe04a, 0xe008, 0x3fff, 0x3c09, 0xe04a, 0xaf1c, 0xa806,
+	0x3c0b, 0x28b7, 0xa00e, 0x3cb7, 0x2808, 0x1894, 0xf07a, 0xf04e,
+	0x2809, 0x1895, 0xf03a, 0xa202, 0x3c82, 0x2808, 0xa01e, 0xaf08,
+	0x3c0c, 0x2809, 0xa01e, 0xaf08, 0x3c0d, 0xcca4, 0x820c, 0xe018,
+	0x3c0e, 0xf05a, 0xa202, 0xe42e, 0xa202, 0x3cf0, 0xa200, 0xe42e,
+	0x280a, 0x4c0b, 0xf068, 0x2808, 0x3c0f, 0x2809, 0x3c10, 0xe42e,
+	0xa202, 0x2a0a, 0xa103, 0xb6b6, 0xa103, 0xb6b6, 0xa103, 0xb656,
+	0x3c00, 0xa202, 0x2a0a, 0xa103, 0xb696, 0xa103, 0xb676, 0xa103,
+	0xb636, 0x3c01, 0xa202, 0x2a0b, 0xa103, 0xb6b6, 0xa103, 0xb6b6,
+	0xa103, 0xb656, 0x3c02, 0xa202, 0x2a0b, 0xa103, 0xb696, 0xa103,
+	0xb676, 0xa103, 0xb636, 0x3c03, 0x2808, 0xcca4, 0x8200, 0xe018,
+	0xc70f, 0x7c01, 0xe190, 0x3c0f, 0x2809, 0xcca4, 0x8202, 0xe018,
+	0xc70f, 0x7c03, 0xe190, 0x3c10, 0xe42e, 0x280f, 0xa01e, 0xaf08,
+	0x180c, 0x2a10, 0xa01f, 0xaf09, 0x1a0d, 0xf044, 0xf035, 0xa202,
+	0xe42e, 0xa200, 0xe42e, 0xe41e, 0x036e, 0x2812, 0xf068, 0xe41e,
+	0x0380, 0x3c17, 0xe41e, 0x0380, 0xe41e, 0x0380, 0x3c18, 0xf2fa,
+	0xe41e, 0x0380, 0x3c19, 0xe41e, 0x0380, 0x3c1a, 0xf1ca, 0xe41e,
+	0x0380, 0x3c1b, 0xe166, 0x0680, 0xa20e, 0x3c96, 0xe41e, 0x0919,
+	0xe41e, 0x0919, 0xe41e, 0x0919, 0xe41e, 0x0919, 0xe166, 0x0684,
+	0xa20c, 0x3c96, 0xe41e, 0x0919, 0xe41e, 0x0919, 0xe41e, 0x0919,
+	0xe41e, 0x0919, 0x2819, 0xf0ba, 0xe166, 0x0200, 0xa210, 0x3c96,
+	0xe41e, 0x092a, 0xe41e, 0x092a, 0xe41e, 0x092a, 0xe41e, 0x0380,
+	0x3c1c, 0xa20c, 0xe41e, 0x038a, 0x3c1d, 0xa206, 0xe41e, 0x038a,
+	0x3c1e, 0xa200, 0x3c20, 0xe41e, 0x0380, 0x3c1f, 0xf1da, 0xe41e,
+	0x0380, 0x3c20, 0xf19a, 0xe166, 0x0688, 0xa20c, 0x3c96, 0xe41e,
+	0x0936, 0xe41e, 0x0936, 0xe41e, 0x0936, 0xe41e, 0x0936, 0xe166,
+	0x068c, 0xa20c, 0x3c96, 0xe41e, 0x0936, 0xe41e, 0x0936, 0xe41e,
+	0x0936, 0xe41e, 0x0936, 0xa204, 0xe41e, 0x038a, 0x3c21, 0xa202,
+	0x5821, 0x3c21, 0xe406, 0x08ca, 0xa110, 0xe400, 0x08ca, 0xa20e,
+	0xe41e, 0x038a, 0x3c22, 0xe166, 0x06b0, 0xa208, 0x3c96, 0xe41e,
+	0x0946, 0xe41e, 0x0946, 0xe41e, 0x0946, 0xe41e, 0x0946, 0xe41e,
+	0x0946, 0x2812, 0xf1da, 0xe41e, 0x0380, 0x3c23, 0xe41e, 0x0380,
+	0x3c24, 0xa200, 0x3c25, 0x2823, 0xf058, 0xa204, 0xe41e, 0x038a,
+	0x3c25, 0xa200, 0x3c26, 0x2824, 0xf058, 0xa204, 0xe41e, 0x038a,
+	0x3c26, 0xe41e, 0x0380, 0x3c27, 0xe41e, 0x0380, 0x3c28, 0xe41e,
+	0x0380, 0x3c29, 0xf058, 0xe004, 0x0002, 0xe41e, 0x0e5d, 0x2812,
+	0xf048, 0xa202, 0x3c2a, 0xf04e, 0xe41e, 0x0380, 0x3c2a, 0xe167,
+	0x0230, 0xa200, 0x3c00, 0x2800, 0xa108, 0xf1ba, 0x2800, 0xe41e,
+	0x0e6c, 0xe165, 0x0900, 0xe004, 0x0108, 0x3c01, 0x2915, 0xe41e,
+	0x0376, 0x2b07, 0xf04a, 0xe41e, 0x03b0, 0xe049, 0x3f17, 0x2801,
+	0xa102, 0x3c01, 0xf748, 0xe190, 0x2800, 0xa002, 0x3c00, 0xf64e,
+	0xa200, 0x3c2f, 0xe41e, 0x0380, 0x3c2b, 0xf21a, 0xe41e, 0x03b0,
+	0x3c2f, 0x2812, 0xe40a, 0x08c8, 0xe41e, 0x03b0, 0x3c2c, 0xe41e,
+	0x03b0, 0x3c2d, 0xe41e, 0x03b0, 0x3c2e, 0xe166, 0x0203, 0xe41e,
+	0x0380, 0xf0da, 0xe41e, 0x03b0, 0x3d16, 0xe41e, 0x03b0, 0x3d16,
+	0xe41e, 0x03b0, 0x3d16, 0xe41e, 0x03b0, 0x3d16, 0xe166, 0x0207,
+	0xe41e, 0x0380, 0xf0aa, 0xe41e, 0x03b0, 0x3d16, 0xe41e, 0x03b0,
+	0x3d16, 0xe41e, 0x03b0, 0x3d16, 0xe41e, 0x0e88, 0xe165, 0x0650,
+	0xe166, 0x020a, 0xa200, 0x3c00, 0xa126, 0xf08a, 0x2915, 0xe41e,
+	0x0956, 0x2800, 0xa002, 0x3c00, 0xf78e, 0xa200, 0x3c00, 0xa126,
+	0xf08a, 0x2915, 0xe41e, 0x0956, 0x2800, 0xa002, 0x3c00, 0xf78e,
+	0xa202, 0xe42e, 0xa200, 0xe42e, 0x2813, 0xf078, 0xa201, 0x3e7b,
+	0x3e7c, 0x3e7d, 0x3e7f, 0xf1ce, 0xa102, 0xf088, 0xa201, 0x3e7b,
+	0x3e7f, 0xa203, 0x3e7c, 0x3e7d, 0xf13e, 0xa102, 0xf088, 0xa201,
+	0x3e7c, 0x3e7f, 0xa203, 0x3e7b, 0x3e7d, 0xf0ae, 0xa102, 0xf078,
+	0xa203, 0x3e7b, 0x3e7c, 0x3e7d, 0x3e7f, 0xf02e, 0xf60e, 0xe42e,
+	0x2812, 0xf228, 0xe41e, 0x0e45, 0xa200, 0x3c1b, 0xe166, 0x0680,
+	0xd022, 0x0007, 0xe184, 0x08fd, 0x3d16, 0xe190, 0xe190, 0xa200,
+	0xe166, 0x0688, 0xd022, 0x0007, 0xe184, 0x0907, 0x3d16, 0xe190,
+	0xe190, 0xa202, 0x3c23, 0x3c24, 0xa200, 0x3c25, 0x3c26, 0xa200,
+	0x3c27, 0x3c28, 0xf05e, 0xa203, 0x287d, 0xb611, 0x3e79, 0xa202,
+	0xe42e, 0xe41e, 0x0380, 0xf0ca, 0x2896, 0xe41e, 0x038a, 0x3d06,
+	0xe41e, 0x0380, 0x2b06, 0xf02a, 0xe013, 0x3f16, 0xf03e, 0xa200,
+	0x3d16, 0xe42e, 0xe41e, 0x0380, 0xf06a, 0x2896, 0xe41e, 0x038a,
+	0x3d16, 0xf04e, 0xe004, 0x00ff, 0x3d16, 0xe42e, 0xe41e, 0x0380,
+	0xf0ca, 0x2896, 0xe41e, 0x038a, 0x3d06, 0xe41e, 0x0380, 0x2b06,
+	0xf02a, 0xe013, 0x3f16, 0xf02e, 0x8116, 0xe42e, 0xe41e, 0x0380,
+	0xf0ca, 0x2896, 0xe41e, 0x038a, 0x3d06, 0xe41e, 0x0380, 0x2b06,
+	0xf02a, 0xe013, 0x3f16, 0xf02e, 0x3d16, 0xe42e, 0xe41e, 0x0376,
+	0x2b06, 0xf04a, 0xe41e, 0x039c, 0xe049, 0x3f16, 0xe42e, 0xa200,
+	0x3c66, 0xa2fe, 0x3c67, 0xa202, 0x3c70, 0x2812, 0x3c71, 0xe016,
+	0x3c73, 0xa200, 0x3c72, 0x3c74, 0xe41e, 0x052e, 0xe41e, 0x03d1,
+	0xe41e, 0x1330, 0xe41e, 0x1363, 0xe41e, 0x025f, 0xe41e, 0x1158,
+	0xe41e, 0x03cc, 0xe41e, 0x1152, 0xe41e, 0x09cf, 0xe41e, 0x0ab0,
+	0xe016, 0x4c69, 0x3c69, 0xe166, 0x0690, 0x2821, 0xa102, 0xf0fa,
+	0xa102, 0xcc44, 0xe184, 0x0995, 0xba4e, 0xe049, 0xba4e, 0xae10,
+	0xe055, 0xba4e, 0xae20, 0xe055, 0x3716, 0x3f16, 0xe190, 0xa200,
+	0x3c70, 0x3c73, 0x3c71, 0xa202, 0x3c72, 0x3c74, 0xe41e, 0x052e,
+	0xe41e, 0x04a1, 0x2821, 0xf21a, 0xa102, 0xf138, 0xe41e, 0x0ad4,
+	0xe41e, 0x03cc, 0xe41e, 0x09f3, 0xa200, 0x246a, 0x4c6b, 0xae06,
+	0xc873, 0xe045, 0xf047, 0xa202, 0x4c69, 0x3c69, 0xa202, 0xe42e,
+	0xe41e, 0x0aec, 0xe41e, 0x0ad4, 0xe41e, 0x03cc, 0xa200, 0xcc72,
+	0xe41e, 0x09fa, 0xa202, 0xe42e, 0xa200, 0xe42e, 0x2812, 0xe016,
+	0x4c23, 0x4c24, 0xf03a, 0x2822, 0x3c7a, 0xa202, 0xe42e, 0xa2fe,
+	0x3c77, 0xa200, 0x3c76, 0x3c68, 0xe16a, 0xa200, 0x3c75, 0x2a77,
+	0xa003, 0x3e77, 0xe41e, 0x0cf1, 0xf0fd, 0x2875, 0xa002, 0x3c75,
+	0x180c, 0xf764, 0x2876, 0xa002, 0x3c76, 0x180d, 0xf6f4, 0xe41e,
+	0x0d1a, 0xa202, 0xe42e, 0x2877, 0x3c67, 0x2a0e, 0xe045, 0x3e68,
+	0xe16a, 0xa200, 0xe42e, 0xe41e, 0x036e, 0xe41e, 0x0a75, 0xe41a,
+	0x0a98, 0xe42e, 0xa2fe, 0x3c77, 0xa200, 0x3c76, 0x3c75, 0x3c8b,
+	0xe16a, 0x2876, 0x2a21, 0xa103, 0xe052, 0x3c8b, 0x2876, 0x1821,
+	0xf072, 0x2876, 0xe418, 0x0ff8, 0xe41e, 0x036e, 0xf09e, 0xe41e,
+	0x102c, 0xe41e, 0x0372, 0xe004, 0x0011, 0xe41e, 0x1041, 0xe41e,
+	0x0a5c, 0xf19d, 0xe41e, 0x101b, 0xe004, 0x0010, 0xe41e, 0x1041,
+	0x2876, 0xa002, 0x3c76, 0x180d, 0xf5d4, 0xe41e, 0x0d1a, 0xa200,
+	0x3c8b, 0xe41e, 0x0a37, 0x288b, 0xa002, 0x3c8b, 0x1821, 0xf7a4,
+	0xa202, 0xe42e, 0xe41e, 0x0a98, 0xe16a, 0xa200, 0xe42e, 0xe004,
+	0x0800, 0x2a8b, 0xcca5, 0xc798, 0xe01c, 0xe09c, 0xe004, 0x0690,
+	0x2a8b, 0xcca5, 0xc782, 0xe01c, 0xe09e, 0x8116, 0x8116, 0x8116,
+	0x8116, 0x8116, 0x8116, 0x8116, 0x8116, 0x8116, 0x8116, 0x8116,
+	0x8116, 0x2116, 0x4d16, 0x2717, 0x4f17, 0xae07, 0xe046, 0xf046,
+	0xa202, 0x4c69, 0x3c69, 0xe42e, 0x2870, 0xf158, 0xa200, 0x3c75,
+	0x2867, 0x2a77, 0xa003, 0x3e77, 0xf044, 0x2877, 0x1867, 0xf0b2,
+	0xe41e, 0x0cf1, 0xf08d, 0x2875, 0xa002, 0x3c75, 0x180c, 0xf714,
+	0xa202, 0xe42e, 0xe16b, 0xa200, 0xe42e, 0xa2fe, 0x3c77, 0xa200,
+	0x3c76, 0xe16a, 0xa200, 0x3c75, 0x2867, 0x2a77, 0xa003, 0x3e77,
+	0xf044, 0x2877, 0x1867, 0xf122, 0xe41e, 0x0cf1, 0xf0fd, 0x2875,
+	0xa002, 0x3c75, 0x180c, 0xf714, 0x2876, 0xa002, 0x3c76, 0x180d,
+	0xf6a4, 0xe41e, 0x0d1a, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e,
+	0xe16a, 0xe41e, 0x0d2f, 0xf12d, 0x2875, 0xa002, 0x3c75, 0x180c,
+	0x2a77, 0xa003, 0x3e77, 0xf764, 0xa200, 0x3c75, 0x2876, 0xa002,
+	0x3c76, 0x180d, 0xf6f4, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e,
+	0xa200, 0x2615, 0x4e16, 0xe042, 0x2eb7, 0xe042, 0xae06, 0xc873,
+	0xe045, 0xf191, 0xc873, 0xe046, 0xe049, 0xf13a, 0xaf0a, 0xa102,
+	0xf0b4, 0xcc44, 0xe184, 0x0ac9, 0xba4e, 0xba4e, 0xe190, 0xba4e,
+	0xba4e, 0xe190, 0xe190, 0xe04a, 0xa83e, 0xf03a, 0xe09c, 0x9206,
+	0xa202, 0xe42e, 0xa200, 0xe42e, 0xa200, 0x2615, 0x4e16, 0xe042,
+	0x2eb7, 0xe042, 0x2a21, 0xa103, 0xf0e5, 0xf04b, 0xcca5, 0xc783,
+	0xe01c, 0xae06, 0xc873, 0xe045, 0xf061, 0xc873, 0xe046, 0xe40e,
+	0x0abc, 0xe190, 0xa200, 0xe42e, 0xe166, 0x0690, 0xe167, 0x06a0,
+	0xa200, 0x2615, 0x4e16, 0xe042, 0x2eb7, 0xe042, 0x2a21, 0xa111,
+	0xf201, 0x2a21, 0xa103, 0xf1d7, 0xcca5, 0xc783, 0xe01c, 0x3517,
+	0x3d17, 0x2a21, 0xa103, 0xa103, 0xcc45, 0xe184, 0x0b0b, 0x2716,
+	0x4f16, 0xe042, 0x3517, 0x3d17, 0x266a, 0x4e6b, 0xe045, 0xa107,
+	0x2812, 0xf028, 0xa10f, 0x2cb7, 0xe041, 0x3716, 0x3f16, 0xe190,
+	0xa202, 0xe42e, 0xa206, 0xe41e, 0x13cd, 0xe41e, 0x1330, 0xe41e,
+	0x1363, 0xe41e, 0x025f, 0xe41e, 0x0b48, 0xa202, 0xe42e, 0x2834,
+	0xf1f4, 0xa203, 0xe0c3, 0x040d, 0xcca4, 0xc785, 0xe019, 0xe001,
+	0x0500, 0xe09f, 0xe0c1, 0x0420, 0xa803, 0xf7db, 0xa200, 0xe41e,
+	0x1310, 0xaf04, 0xe41e, 0x1319, 0xae20, 0x2e32, 0xe056, 0x9f17,
+	0x200c, 0x4c0d, 0xae08, 0x9f17, 0xa201, 0xe0c3, 0x040d, 0xe42e,
+	0xa200, 0x2a41, 0xa803, 0xf03b, 0xe00a, 0x0002, 0x2a41, 0xa805,
+	0xf02b, 0xa912, 0x2a41, 0xa809, 0xf02b, 0xa940, 0x2a41, 0xa811,
+	0xf02b, 0xa980, 0xe0c2, 0x040c, 0xe42e, 0xe0c0, 0x0059, 0xa102,
+	0xf20a, 0xa102, 0xe42a, 0xa102, 0xf04a, 0xa102, 0xf24a, 0xe42e,
+	0xe0c0, 0x0060, 0xaf08, 0x3051, 0xaf02, 0x3052, 0xe0c0, 0x0060,
+	0xa81e, 0x3c50, 0xe0c0, 0x0061, 0xa83e, 0x3c54, 0xe0c1, 0x0065,
+	0xa809, 0xe0c0, 0x0065, 0xaf06, 0xa806, 0xb632, 0x3c4c, 0xe42e,
+	0xe0c0, 0x0060, 0x34a0, 0x3ca1, 0xe0c0, 0x0061, 0xae14, 0x34a2,
+	0x3ca3, 0xe42e, 0xe42e, 0xe0c0, 0x0059, 0xa102, 0xe40a, 0x0bf5,
+	0xa102, 0xe42a, 0xa102, 0xf05a, 0xa102, 0xe40a, 0x0c1b, 0xe42e,
+	0xa200, 0xe0c2, 0x0075, 0xe0c2, 0x0078, 0xe0c2, 0x0079, 0xe0c2,
+	0x007d, 0xe0c2, 0x007e, 0x2834, 0x2ab1, 0xb7d2, 0xe0c2, 0x0077,
+	0x2834, 0xe049, 0xa003, 0xb7b6, 0x2a14, 0xb7b6, 0x2ab1, 0xb7f2,
+	0x2a51, 0x4e52, 0x46b1, 0xb7f2, 0xe0c2, 0x0071, 0x2438, 0x4c39,
+	0xe0c2, 0x0054, 0x200c, 0x4c0d, 0xae08, 0xe0c2, 0x006f, 0x243a,
+	0x4c3b, 0xe0c2, 0x0070, 0x2868, 0xe0c2, 0x0072, 0x2812, 0xa802,
+	0xe0c2, 0x0073, 0xe41e, 0x0c1c, 0xe0c2, 0x007c, 0xa200, 0x2a36,
+	0xe009, 0x00ff, 0xe056, 0xae10, 0x2a37, 0xe009, 0x00ff, 0xe056,
+	0xae10, 0x2a35, 0xe009, 0x00ff, 0xe056, 0xae0e, 0x4c13, 0xae02,
+	0x4c14, 0xe0c2, 0x007a, 0x2878, 0xae02, 0x2a78, 0xa103, 0xb632,
+	0x2a69, 0xae21, 0xe056, 0xe0c2, 0x0076, 0xc84a, 0xc84d, 0xae20,
+	0xe056, 0xe0c2, 0x0053, 0xa202, 0xe42e, 0xa200, 0xe0c2, 0x0074,
+	0xe0c2, 0x0076, 0xe0c2, 0x0077, 0xe0c2, 0x0079, 0xe0c2, 0x007a,
+	0xa2fe, 0xe0c2, 0x0072, 0xe0c2, 0x006d, 0xa208, 0xe0c2, 0x0073,
+	0x2008, 0x4c09, 0xe0c2, 0x0071, 0x2813, 0xe0c2, 0x007b, 0xe41e,
+	0x0c1c, 0xe0c2, 0x0075, 0x2883, 0xe0c2, 0x0070, 0x28f0, 0xe0c2,
+	0x0078, 0xa202, 0xe42e, 0xe42e, 0x280a, 0xae04, 0x4c0b, 0xae1c,
+	0x4c08, 0xae1c, 0x4c09, 0xe42e, 0xe41e, 0x0148, 0xe41e, 0x023a,
+	0xe41e, 0x0ccf, 0xe41e, 0x063b, 0xd130, 0x0007, 0xd131, 0x0002,
+	0xd04b, 0x0001, 0xd04c, 0x0000, 0xd008, 0x0000, 0xd03a, 0x0000,
+	0xa200, 0xcc4a, 0xcc4c, 0xa200, 0x3c83, 0xe41e, 0x0b5d, 0xe41e,
+	0x0ea9, 0xf0da, 0xa200, 0x3cb7, 0xe41e, 0x067c, 0xa100, 0xf07a,
+	0xe41e, 0x0758, 0x2812, 0xf038, 0xa202, 0x3c83, 0xe41e, 0x0b8b,
+	0xe41e, 0x0f3f, 0xe16a, 0xe42e, 0xe42e, 0xe41e, 0x058c, 0xe41e,
+	0x0658, 0xe41e, 0x0dd4, 0xe41e, 0x1330, 0xe42e, 0xa200, 0xcc44,
+	0xcc4a, 0xcc4c, 0x3c69, 0x3c78, 0xd130, 0x0007, 0xd131, 0x0002,
+	0xd008, 0x0000, 0xd03a, 0x0000, 0xe41e, 0x0b5d, 0xe41e, 0x0ea9,
+	0xe40a, 0x0caa, 0xa200, 0x3cb7, 0xe41e, 0x05b1, 0xe41e, 0x066a,
+	0xe41e, 0x0ea0, 0xe41e, 0x1138, 0xe41e, 0x0dd9, 0xe41e, 0x0b1a,
+	0x28b1, 0xf298, 0xe41e, 0x0cdc, 0xe41e, 0x06cc, 0xf24a, 0xe41e,
+	0x0cdc, 0x28b1, 0xf208, 0xe41e, 0x0795, 0xf1da, 0xe41e, 0x0cdc,
+	0xe41e, 0x06db, 0xf18a, 0xe41e, 0x0cdc, 0x2829, 0xe418, 0x0cd4,
+	0xe41e, 0x0ce0, 0xf108, 0xe41e, 0x0cdc, 0xe41e, 0x05bc, 0xf0ba,
+	0xe41e, 0x0cdc, 0xe41e, 0x0b27, 0xe41e, 0x095f, 0xe41e, 0x05e1,
+	0xe41e, 0x0cd8, 0xe41e, 0x09c6, 0xe41e, 0x0ea2, 0xe41e, 0x11eb,
+	0xe41e, 0x0e29, 0xe41e, 0x0b8b, 0x2834, 0xa002, 0xe016, 0xe41a,
+	0x0f3f, 0xe42e, 0xa2fe, 0x3c34, 0x3c35, 0x3c36, 0x3c37, 0x3c3c,
+	0xe0c0, 0x0054, 0x3438, 0x3c39, 0xa200, 0x3cae, 0x3cb1, 0x3c3d,
+	0x3c3e, 0x3c3b, 0x3c3a, 0xe42e, 0xca28, 0xf7f8, 0xe42e, 0xe41e,
+	0x0e45, 0xe41e, 0x12e0, 0xe42e, 0xa204, 0xe41e, 0x0e5d, 0xe42e,
+	0xa206, 0xe41e, 0x0e5d, 0xe42e, 0x2878, 0xa002, 0x3c78, 0xe42e,
+	0x284c, 0xe42a, 0xa102, 0xf04a, 0xa102, 0xf05a, 0xf09e, 0x2812,
+	0xf078, 0xf04e, 0x2812, 0xa104, 0xf03a, 0xa200, 0xe42e, 0xa202,
+	0xe42e, 0xcb05, 0xe009, 0x2222, 0x2875, 0xae10, 0x4c76, 0xcf06,
+	0xf058, 0xe16a, 0xe41e, 0x0d41, 0xf0ae, 0xf03b, 0xe41e, 0x0d53,
+	0xcb05, 0xaf21, 0xa803, 0xf03b, 0xe41e, 0x0d96, 0x2884, 0xa908,
+	0xcf02, 0x2884, 0xa902, 0xcf02, 0x2a70, 0xcb02, 0xa802, 0xf7e8,
+	0xe429, 0xcb04, 0xaf14, 0xa802, 0xf7da, 0xe41e, 0x11ef, 0xe41e,
+	0x1241, 0xe42e, 0x2870, 0xcb05, 0xe009, 0x2222, 0xf07a, 0xf03b,
+	0xe41e, 0x0d53, 0xe41e, 0x0d7c, 0xe42e, 0xcb05, 0xaf21, 0xa803,
+	0xf03b, 0xe41e, 0x0d96, 0x2880, 0xe418, 0x0dba, 0xe42e, 0x2875,
+	0xae10, 0x4c76, 0xcf06, 0x2884, 0xa908, 0xcf02, 0x2884, 0xa906,
+	0xcf02, 0xcb02, 0xa802, 0xf7e8, 0xe41e, 0x11ef, 0xe41e, 0x1241,
+	0xe42e, 0x2a70, 0xa200, 0x3c46, 0x3c85, 0x3c49, 0x3c86, 0xf0b9,
+	0xe41e, 0x0d62, 0xe41e, 0x0d62, 0x2880, 0xf058, 0xe41e, 0x0da0,
+	0xe41e, 0x0da0, 0xe42e, 0x3e9a, 0x2870, 0xa845, 0xf05a, 0xf03b,
+	0xe41e, 0x0d7c, 0xe42e, 0x2a9a, 0xe009, 0x0200, 0xf03b, 0xe41e,
+	0x0d62, 0xe42e, 0x2044, 0x4c45, 0x2e46, 0xae11, 0xe042, 0xca29,
+	0xf7f9, 0xce20, 0x2a85, 0xe004, 0x0100, 0xf03b, 0xe004, 0x0120,
+	0xce22, 0xd112, 0x0020, 0xd113, 0x0019, 0x2885, 0xaa02, 0x3c85,
+	0x2c46, 0xa002, 0x3c46, 0xe42e, 0x2044, 0x4c45, 0x2e46, 0xae11,
+	0xe042, 0xca29, 0xf7f9, 0xce20, 0x2a85, 0xe004, 0x0100, 0xf03b,
+	0xe004, 0x0120, 0xce22, 0xd112, 0x0020, 0xd113, 0x0018, 0x2885,
+	0xaa02, 0x3c85, 0x2c46, 0xa002, 0x3c46, 0xe42e, 0x2870, 0xf088,
+	0x2880, 0xf04a, 0xe41e, 0x0dba, 0xe42e, 0xe41e, 0x0da0, 0xe42e,
+	0x2047, 0x4c48, 0x2e49, 0xae11, 0xe042, 0xca29, 0xf7f9, 0xce20,
+	0x2a86, 0xe004, 0x0080, 0xf03b, 0xe004, 0x00a0, 0xce22, 0xd112,
+	0x0020, 0xd113, 0x0019, 0x2886, 0xaa02, 0x3c86, 0x2c49, 0xa002,
+	0x3c49, 0xe42e, 0x2047, 0x4c48, 0x2e49, 0xae11, 0xe042, 0xca29,
+	0xf7f9, 0xce20, 0x2a86, 0xe004, 0x0080, 0xf03b, 0xe004, 0x00a0,
+	0xce22, 0xd112, 0x0020, 0xd113, 0x0018, 0x2886, 0xaa02, 0x3c86,
+	0x2c49, 0xa002, 0x3c49, 0xe42e, 0xa2fe, 0x3c53, 0xa200, 0x3c51,
+	0xe42e, 0x283f, 0x3c53, 0x2853, 0xf032, 0xa200, 0x3c51, 0xa200,
+	0x3c58, 0x3c59, 0x280c, 0x3c56, 0x280d, 0x3c57, 0x2851, 0xe42a,
+	0x2853, 0xe424, 0x2853, 0xe0c2, 0x0143, 0x2854, 0xe0c2, 0x0144,
+	0xa200, 0xe0c2, 0x017f, 0xe0c2, 0x0149, 0xe41e, 0x1310, 0xe0c2,
+	0x017f, 0x2856, 0xa102, 0xae20, 0x4c57, 0xa102, 0xe0c2, 0x0142,
+	0xa200, 0xae20, 0x2a50, 0xe042, 0xe0c2, 0x014e, 0xe42e, 0x2853,
+	0x2a59, 0x1a57, 0xe423, 0x2858, 0xae0e, 0x4c59, 0xa203, 0xb615,
+	0x3e5a, 0x2a5a, 0xae03, 0xa903, 0xae1d, 0xe056, 0xe0c1, 0x014b,
+	0xf7e9, 0xe0c2, 0x014d, 0xa202, 0xe0c2, 0x014a, 0x2a58, 0xa003,
+	0x3e58, 0x1a56, 0xf065, 0x2a59, 0xa003, 0x3e59, 0xa201, 0x3e58,
+	0xe42e, 0x2851, 0xf15a, 0x2859, 0x1857, 0xf042, 0xe41e, 0x0e07,
+	0xf7be, 0xe0c0, 0x014b, 0xf7e8, 0xa204, 0xae1c, 0xe0c2, 0x014d,
+	0xa202, 0xe0c2, 0x014a, 0xe190, 0xe0c0, 0x014b, 0xf7e8, 0x2a14,
+	0x2834, 0xb7f6, 0x3c3f, 0x3c53, 0xe42e, 0xa200, 0xe0c1, 0x0040,
+	0xe042, 0xe005, 0x0059, 0xae17, 0xe042, 0xe005, 0x1600, 0xae03,
+	0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111, 0x0200, 0xd112, 0x0450,
+	0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e, 0x3c90, 0x2042, 0x4c43,
+	0xca29, 0xf7f9, 0xce20, 0xd111, 0x0200, 0xd112, 0x0450, 0x2890,
+	0xce26, 0xca28, 0xf7f8, 0xe42e, 0xcca4, 0xe182, 0x0108, 0xe018,
+	0xae02, 0xe0c1, 0x0040, 0xe042, 0xe005, 0x0059, 0xae17, 0xe042,
+	0xe005, 0x1a50, 0xae03, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111,
+	0x0900, 0xd112, 0x0108, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e,
+	0xa200, 0xe0c1, 0x0040, 0xe042, 0xe005, 0x0059, 0xae17, 0xe042,
+	0xe005, 0x1f50, 0xae03, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111,
+	0x0650, 0xd112, 0x0028, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e,
+	0xa202, 0xe42e, 0xa202, 0xe42e, 0xe42e, 0xe42e, 0xe42e, 0xe42e,
+	0xe42e, 0xe0c0, 0x0059, 0xa102, 0xe40a, 0x0eb6, 0xa102, 0xe40a,
+	0x0ed8, 0xa102, 0xe40a, 0x0ebe, 0xe40e, 0x0ed8, 0xe41e, 0x023a,
+	0x24a0, 0x4ca1, 0x04a2, 0x0ca3, 0x34a4, 0x3ca5, 0xa206, 0xae1e,
+	0xcec0, 0xd160, 0x0600, 0xe0c0, 0x0048, 0xe0c2, 0x0051, 0x34aa,
+	0x3cab, 0x34a6, 0xe008, 0xfe00, 0x3ca7, 0x2cab, 0xe008, 0x01ff,
+	0x3cac, 0xe41e, 0x10a1, 0xf07d, 0xe41e, 0x0f20, 0xe41e, 0x0f0b,
+	0xa202, 0xe42e, 0xa200, 0xe16a, 0xe42e, 0xe41e, 0x0ee0, 0xe470,
+	0xca28, 0xf7f8, 0xe004, 0x0080, 0xce24, 0x28af, 0xae0e, 0xce22,
+	0x24a6, 0x4ca7, 0xce20, 0xe0c0, 0x0043, 0xa806, 0xae02, 0xa022,
+	0xce26, 0xca28, 0xf7f8, 0x24a6, 0x4ca7, 0xe000, 0x0200, 0x34a6,
+	0x3ca7, 0x14a4, 0x1ca5, 0xf054, 0x24a0, 0x4ca1, 0x34a6, 0x3ca7,
+	0xd04c, 0x0000, 0x28af, 0xae0e, 0xcc6e, 0x28af, 0xe016, 0x3caf,
+	0xe42e, 0x28b1, 0xe42e, 0xa200, 0x3caf, 0xce92, 0xe41e, 0x0ee0,
+	0xe41e, 0x0ee0, 0xe128, 0xd071, 0x2020, 0xe181, 0x2cac, 0xa102,
+	0xf074, 0xcc44, 0xe184, 0x0f1d, 0xba4e, 0xe190, 0xe190, 0xe42e,
+	0xe004, 0x1495, 0xae20, 0xcc9e, 0xd030, 0x0000, 0xd034, 0x0000,
+	0xd033, 0x0000, 0xd035, 0x0000, 0xd036, 0x00ff, 0xd037, 0x0000,
+	0xd038, 0x0000, 0xd039, 0x0000, 0xd04b, 0x0001, 0xd04c, 0x0000,
+	0xd046, 0x0000, 0xd047, 0x0000, 0xd149, 0x0000, 0xe42e, 0xe0c0,
+	0x0059, 0xa102, 0xe40a, 0x0f4a, 0xa102, 0xe42a, 0xa102, 0xe40a,
+	0x0f4a, 0xe42a, 0x24b4, 0x4cb5, 0x04aa, 0x0cab, 0x34aa, 0x3cab,
+	0x14a4, 0x1ca5, 0xf074, 0x24aa, 0x4cab, 0x14a2, 0x1ca3, 0x34aa,
+	0x3cab, 0x24aa, 0x4cab, 0xe0c2, 0x0048, 0xe0c2, 0x0052, 0xe42e,
+	0xa200, 0x34b4, 0x3cb5, 0xe42e, 0xf0a8, 0x2911, 0xe008, 0xffff,
+	0xae20, 0x2b11, 0xe009, 0xffff, 0xe042, 0xf0fe, 0x2911, 0xe008,
+	0x00ff, 0xae20, 0x2b11, 0xe009, 0xffff, 0xe042, 0xae10, 0x2b11,
+	0xe009, 0xff00, 0xaf11, 0xe042, 0x2ab6, 0xe42b, 0xe049, 0xaf31,
+	0xe009, 0x00ff, 0xe093, 0xe049, 0xaf21, 0xe009, 0x00ff, 0xe095,
+	0xe049, 0xaf11, 0xe009, 0x00ff, 0xe008, 0x00ff, 0xae10, 0xe056,
+	0xae10, 0xe085, 0xe056, 0xae10, 0xe083, 0xe056, 0xe42e, 0xe049,
+	0xa80f, 0xe046, 0xe42e, 0xca29, 0xf7f9, 0xd111, 0x07c0, 0xce20,
+	0x26a4, 0x4ea5, 0xe045, 0xe004, 0x0040, 0xe065, 0xaf03, 0xce25,
+	0x3eb0, 0xe41e, 0x0fb9, 0xa240, 0x18b0, 0xe426, 0xce24, 0x28b0,
+	0xe000, 0x07c0, 0xce22, 0x24a0, 0x4ca1, 0xce20, 0xe41e, 0x0fb9,
+	0xe42e, 0xe0c0, 0x0043, 0xa806, 0xae02, 0xa002, 0xce26, 0xca28,
+	0xf7f8, 0xe42e, 0x34b8, 0x3cb9, 0xa200, 0x3cad, 0xe0c0, 0x0049,
+	0x34ba, 0x3cbb, 0xe0c0, 0x0045, 0xaf04, 0x30ae, 0xe0c0, 0x0049,
+	0x34a8, 0x3ca9, 0x10ba, 0x1cbb, 0x2aad, 0xb611, 0x3ead, 0x26a8,
+	0x4ea9, 0x16b8, 0x1eb9, 0xf033, 0x06a2, 0x0ea3, 0x16b2, 0x1eb3,
+	0xa200, 0xe423, 0x28ae, 0x3cb1, 0xe428, 0x28ad, 0xf648, 0xe41e,
+	0x01db, 0xe0c0, 0x005c, 0xe008, 0x4000, 0xf5da, 0xe0c0, 0x005d,
+	0xe00a, 0x4000, 0xe0c2, 0x005d, 0xa202, 0xce00, 0x3cad, 0xf53e,
+	0xe004, 0x06a0, 0x2a8b, 0xae03, 0xe042, 0xe09c, 0x2516, 0x4d16,
+	0x26aa, 0x4eab, 0xa019, 0xe042, 0xe049, 0xe008, 0x01ff, 0xe045,
+	0x36a6, 0x3ea7, 0x3cac, 0x24a6, 0x4ca7, 0x14a4, 0x1ca5, 0xf054,
+	0x04a0, 0x0ca1, 0x34a6, 0x3ca7, 0xe41e, 0x0f20, 0xe41e, 0x0f0b,
+	0xa200, 0xcc72, 0xe42e, 0xe004, 0x08c0, 0x2a8b, 0xae05, 0xe042,
+	0xe09c, 0x20a6, 0x4ca7, 0x3516, 0x3d16, 0x28ac, 0x3d16, 0x28af,
+	0x3d16, 0xe41e, 0x1053, 0xe42e, 0xe41e, 0x0f20, 0xe004, 0x08c0,
+	0x2a8b, 0xae05, 0xe042, 0xe09c, 0x2116, 0x4d16, 0x34a6, 0x3ca7,
+	0x2916, 0x3cac, 0x2916, 0x3caf, 0xae0e, 0xce92, 0xe41e, 0x1079,
+	0xe42e, 0x3c90, 0xca29, 0xf7f9, 0xd111, 0x0000, 0x288b, 0xae14,
+	0x264a, 0x4e4b, 0xe042, 0xce20, 0xd112, 0x0100, 0x2890, 0xce26,
+	0xca29, 0xf7f9, 0xe42e, 0xe004, 0x0800, 0x2a8b, 0xcca5, 0xc798,
+	0xe01c, 0xe09c, 0xc860, 0x3516, 0x3d16, 0xc862, 0x3516, 0x3d16,
+	0xc864, 0x3516, 0x3d16, 0xc866, 0x3d16, 0xc868, 0x3d16, 0xc86a,
+	0x3d16, 0xc86c, 0x3d16, 0xc86e, 0x3d16, 0xc870, 0x3d16, 0xc872,
+	0x3516, 0x3d16, 0xc88c, 0x3516, 0x3d16, 0xcb20, 0x3516, 0x3d16,
+	0xe42e, 0xe004, 0x0800, 0x2a8b, 0xcca5, 0xc798, 0xe01c, 0xe09c,
+	0x2116, 0x4d16, 0xcc60, 0x2116, 0x4d16, 0xcc62, 0x2116, 0x4d16,
+	0xcc64, 0x2916, 0xcc66, 0x2916, 0xcc68, 0x2916, 0xcc6a, 0x2916,
+	0xcc6c, 0x2916, 0xcc6e, 0x2916, 0xcc70, 0x2116, 0x4d16, 0xcc72,
+	0x2116, 0x4d16, 0xcc8c, 0x2116, 0x4d16, 0xaf08, 0xae08, 0xcf20,
+	0xe42e, 0xe0c0, 0x0059, 0xa102, 0xe40a, 0x10ac, 0xa102, 0xe42a,
+	0xa102, 0xe40a, 0x10e5, 0xe42e, 0xa202, 0x3cb6, 0xa240, 0x34b2,
+	0x3cb3, 0x24aa, 0x4cab, 0xd027, 0x0000, 0xe41e, 0x0fc2, 0xd027,
+	0x0001, 0xe408, 0x10e3, 0x24aa, 0x4cab, 0xe41e, 0x0f97, 0xe095,
+	0xe41e, 0x0f9b, 0xe084, 0xa00c, 0xaf02, 0xe000, 0x07c0, 0xe092,
+	0xe084, 0xa802, 0xe41e, 0x0f64, 0xe008, 0xffff, 0x34b4, 0x3cb5,
+	0xa140, 0xf114, 0x24b4, 0x4cb5, 0xa02c, 0x34b2, 0x3cb3, 0x24aa,
+	0x4cab, 0xd027, 0x0000, 0xe41e, 0x0fc2, 0xd027, 0x0001, 0xf048,
+	0xa200, 0xe42e, 0xe16b, 0xa202, 0xe42e, 0xa218, 0x34b2, 0x3cb3,
+	0x24aa, 0x4cab, 0xd027, 0x0000, 0xe41e, 0x0fc2, 0xd027, 0x0001,
+	0xf2f8, 0x24aa, 0x4cab, 0xe41e, 0x0f97, 0xe095, 0xe41e, 0x0f9b,
+	0xe084, 0xaf02, 0xe000, 0x07c0, 0xe092, 0xe41e, 0x1124, 0xe084,
+	0xa802, 0xe41e, 0x0f64, 0x00b4, 0x0cb5, 0x34b4, 0x3cb5, 0xf186,
+	0x26a2, 0x4ea3, 0xe046, 0xf142, 0x24b4, 0x4cb5, 0xa018, 0x34b4,
+	0x3cb5, 0x34b2, 0x3cb3, 0x24aa, 0x4cab, 0xd027, 0x0000, 0xe41e,
+	0x0fc2, 0xd027, 0x0001, 0xf048, 0xa200, 0xe42e, 0xe16b, 0xa200,
+	0x34b4, 0x3cb5, 0xa202, 0xe42e, 0x2111, 0x4d09, 0xe005, 0x0044,
+	0xae11, 0xa997, 0xae11, 0xa993, 0xae11, 0xa98d, 0xe046, 0xa241,
+	0xb611, 0x36b4, 0x3eb5, 0xaf03, 0xe082, 0xe042, 0xe092, 0xe42e,
+	0xa20e, 0xa940, 0xe0c2, 0x0100, 0xa200, 0xe0c2, 0x013d, 0xa200,
+	0xe0c2, 0x0128, 0x2a51, 0x4e52, 0xb692, 0xae08, 0xa91c, 0xe0c2,
+	0x017c, 0xa218, 0xe0c2, 0x017d, 0xa200, 0xe41e, 0x1310, 0xe0c2,
+	0x0102, 0xe42e, 0xe41e, 0x0274, 0xa202, 0xe0c2, 0x0106, 0xe42e,
+	0xa20e, 0xa940, 0xe0c2, 0x0100, 0xa200, 0xe0c2, 0x013d, 0x2a51,
+	0x4e52, 0xb692, 0xae08, 0xa91c, 0xe0c2, 0x017c, 0xa218, 0xe0c2,
+	0x017d, 0xe0c1, 0x0046, 0xe004, 0x0000, 0xae10, 0xe042, 0x2a40,
+	0xa805, 0xf05b, 0xe161, 0x06b7, 0x2111, 0x4d11, 0xe0c2, 0x0103,
+	0xa202, 0xe0c2, 0x0210, 0xe0c1, 0x0046, 0xe004, 0x0030, 0xae10,
+	0xe042, 0x2a40, 0xa809, 0xf05b, 0xe161, 0x06b9, 0x2111, 0x4d11,
+	0xe0c2, 0x0211, 0xe0c1, 0x0046, 0xe004, 0x0030, 0xe000, 0x0040,
+	0xae10, 0xe042, 0x2a40, 0xa811, 0xf05b, 0xe161, 0x06bb, 0x2111,
+	0x4d11, 0xe0c2, 0x0212, 0x200c, 0x4c0d, 0xae08, 0xe0c2, 0x0101,
+	0xe0c2, 0x0205, 0xa200, 0xe41e, 0x1310, 0xe0c2, 0x0102, 0x2812,
+	0xa802, 0xae06, 0xe0c2, 0x0104, 0xa20e, 0xae04, 0xa904, 0xae04,
+	0x4c12, 0xae06, 0xa900, 0xe0c2, 0x0204, 0xa200, 0xe0c2, 0x0208,
+	0xa200, 0xe41e, 0x1310, 0xa203, 0xae11, 0xe056, 0xe0c2, 0x0213,
+	0xa200, 0xe0c2, 0x0215, 0xe0c2, 0x0216, 0xe0c2, 0x0216, 0x2834,
+	0xe0c2, 0x020b, 0xe0c2, 0x0214, 0x281c, 0xe0c2, 0x0217, 0xe166,
+	0x06b0, 0x2916, 0xe0c2, 0x0154, 0x2116, 0x4d16, 0xe0c2, 0x0155,
+	0x2116, 0x4d16, 0xe0c2, 0x0156, 0xe41e, 0x12f8, 0xe41e, 0x12cb,
+	0xe41e, 0x124f, 0xa200, 0xe0c2, 0x0113, 0xe0c2, 0x030d, 0xe0c2,
+	0x022b, 0xa202, 0xe42e, 0xe0c0, 0x0111, 0xf7e8, 0xe42e, 0xcbb2,
+	0xaf10, 0xa8fe, 0x3c87, 0xae30, 0xe0c2, 0x0115, 0xcbb2, 0xa820,
+	0xa27f, 0xb611, 0xe0c3, 0x012a, 0xcbb2, 0x3088, 0xe049, 0xa803,
+	0xae03, 0xe05a, 0xa814, 0xe01a, 0xae14, 0xcbb3, 0xa81f, 0xe056,
+	0xe0c2, 0x0114, 0x2888, 0xcbb5, 0xf178, 0xa105, 0x2089, 0x4c8a,
+	0xf039, 0xae02, 0xf06e, 0xa103, 0xf049, 0xe049, 0xae02, 0xe056,
+	0xe0c2, 0x030a, 0xe004, 0x0055, 0xe0c2, 0x030c, 0xe0c0, 0x03b0,
+	0x349b, 0x3c9c, 0xe42e, 0x2875, 0xa002, 0x180c, 0xe01a, 0x2a76,
+	0xe01b, 0xe052, 0xa201, 0xb691, 0x2875, 0xb431, 0x2876, 0xb451,
+	0xe04a, 0xa806, 0xa106, 0xb495, 0xb495, 0xe0c3, 0x0120, 0xcbb8,
+	0xe0c2, 0x0121, 0xcbba, 0xe0c2, 0x0122, 0xcbbc, 0xe0c2, 0x0123,
+	0xe42e, 0xe0c0, 0x0111, 0xf7e8, 0xa202, 0xe0c2, 0x0110, 0x2851,
+	0x4c52, 0xe42a, 0x2859, 0x1857, 0xe414, 0x0e07, 0xe42e, 0xa200,
+	0xe0c2, 0x030b, 0xa202, 0xe0c2, 0x0302, 0x2835, 0xb608, 0xe0c2,
+	0x0380, 0x2835, 0xb608, 0xe0c2, 0x0383, 0x2836, 0xb608, 0xe0c2,
+	0x0386, 0x2837, 0xb608, 0xe0c2, 0x0389, 0xa200, 0xe0c2, 0x0302,
+	0xe004, 0x0421, 0x3c89, 0xe004, 0x0842, 0x3c8a, 0xa200, 0xe0c2,
+	0x0303, 0x2879, 0xae0c, 0xe0c2, 0x0330, 0xa200, 0xe0c2, 0x0308,
+	0x2879, 0xe166, 0x06e0, 0xe167, 0x0331, 0xf038, 0xe166, 0x06c0,
+	0xd022, 0x0007, 0xe184, 0x128b, 0x2916, 0xae10, 0x4d16, 0xae10,
+	0x4d16, 0xae10, 0x4d16, 0x9f17, 0xe190, 0xa20e, 0xe0c2, 0x0312,
+	0xe0c0, 0x0414, 0xe418, 0x018c, 0xe0c0, 0x0414, 0xe41a, 0x1299,
+	0xe42e, 0xe167, 0x01a0, 0x2317, 0x4f17, 0xe0c3, 0x0152, 0x2b17,
+	0xe009, 0x00ff, 0xae21, 0x4f07, 0xe0c3, 0x0153, 0xe0c1, 0x0101,
+	0xe0c3, 0x015d, 0xe005, 0x001b, 0x3e00, 0x2835, 0xa53e, 0xa400,
+	0x2a36, 0xa53f, 0xa401, 0xae11, 0xe055, 0xae21, 0xe167, 0x01a2,
+	0x2907, 0xaf10, 0x4400, 0xe055, 0xe0c3, 0x015c, 0xa202, 0xe0c2,
+	0x0150, 0xe0c0, 0x0150, 0xf7ea, 0xa200, 0xe0c2, 0x0150, 0xe0c0,
+	0x0151, 0xf7e8, 0xe42e, 0xa202, 0xe0c2, 0x013c, 0xa201, 0xe166,
+	0x0200, 0xd022, 0x00ff, 0xe184, 0x12da, 0x2916, 0xe0c3, 0x013e,
+	0xe0c2, 0x013f, 0xa003, 0xe190, 0xa200, 0xe0c2, 0x013c, 0xe42e,
+	0xa200, 0xe0c1, 0x0040, 0xe042, 0xe005, 0x0059, 0xae17, 0xe042,
+	0xe005, 0x1f80, 0xae03, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111,
+	0x06c0, 0xd112, 0x0040, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e,
+	0xa200, 0xe0c1, 0x0040, 0xe042, 0xe005, 0x0059, 0xae17, 0xe042,
+	0xe005, 0x1fc0, 0xae03, 0xe042, 0xca29, 0xf7f9, 0xce20, 0xd111,
+	0x0200, 0xd112, 0x0100, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e,
+	0xe0c1, 0x0044, 0xa80f, 0xe056, 0xe42e, 0xa200, 0xe41e, 0x1310,
+	0xe42e, 0xe0c1, 0x0044, 0xaf0d, 0xae03, 0xe056, 0xe008, 0x003f,
+	0xe42e, 0xe0c1, 0x0044, 0xaf17, 0xa803, 0xe42e, 0xe0c1, 0x0044,
+	0xaf17, 0xa803, 0xa105, 0xf039, 0xa213, 0xe42e, 0xa201, 0xe42e,
+	0xa203, 0xe0c3, 0x040d, 0xe0c1, 0x0420, 0xa803, 0xf7db, 0xe160,
+	0x0003, 0xe166, 0x0700, 0xe167, 0x0500, 0x2833, 0xf166, 0xa102,
+	0xcc44, 0xe184, 0x1353, 0xa200, 0xe41e, 0x1310, 0xaf04, 0xe41e,
+	0x1319, 0xae20, 0x2e32, 0xe056, 0x9f17, 0x200c, 0x4c0d, 0xae08,
+	0x9f17, 0xe41e, 0x1359, 0xe190, 0xe190, 0xa201, 0xe0c3, 0x040d,
+	0xe42e, 0x2116, 0x4d16, 0x9f17, 0x2116, 0x4d16, 0x9f17, 0x2116,
+	0x4d16, 0x9f17, 0xe42e, 0xe0c0, 0x0044, 0xaf20, 0xa802, 0xe428,
+	0xe0c0, 0x0060, 0xa860, 0xe42a, 0xe0c0, 0x0061, 0xa83e, 0xa203,
+	0xe0c3, 0x040d, 0xcca4, 0xc785, 0xe018, 0xe000, 0x0500, 0xe09e,
+	0xe0c1, 0x0420, 0xa803, 0xf7db, 0xa200, 0xe41e, 0x1315, 0xa80e,
+	0xaf04, 0xe41e, 0x1319, 0xe41e, 0x1321, 0xe40b, 0x138c, 0xa81e,
+	0xe41e, 0x1326, 0xae09, 0xe056, 0xae20, 0xe0c1, 0x006e, 0xe009,
+	0x1fff, 0xe056, 0x9f17, 0xe0c0, 0x0060, 0xa822, 0xa122, 0xf04a,
+	0x2056, 0x4c57, 0xf03e, 0x2057, 0x4c56, 0xae08, 0x9f17, 0xe0c0,
+	0x0062, 0x9f17, 0xe0c0, 0x0063, 0x9f17, 0xe0c0, 0x0064, 0x9f17,
+	0xa201, 0xe0c3, 0x040d, 0xe42e, 0x2834, 0xf1f4, 0xa203, 0xe0c3,
+	0x040d, 0xcca4, 0xc785, 0xe019, 0xe001, 0x0500, 0xe09f, 0xe0c1,
+	0x0420, 0xa803, 0xf7db, 0xa200, 0xe41e, 0x1310, 0xaf04, 0xe41e,
+	0x1319, 0xae20, 0x2e32, 0xe056, 0x9f17, 0x200c, 0x4c0d, 0xae08,
+	0x9f17, 0xa201, 0xe0c3, 0x040d, 0xe42e, 0x3cec, 0xe0c0, 0x0041,
+	0xe005, 0x0020, 0xae11, 0xe042, 0xce20, 0xd111, 0x0700, 0xd112,
+	0x00c0, 0x88ec, 0x0113, 0xca29, 0xf7f9, 0xe190, 0xe42e, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0x0000, 0x0000, 0x0000, 0x0070, 0x0056, 0x008c, 0x0025, 0x00a2,
+	0x0065, 0x00cc, 0x00a2, 0x0080, 0x00e1, 0x0092, 0x00ac, 0x0093,
+	0x00d6, 0x0027, 0x009c, 0x0080, 0x0081, 0x0084, 0x004b, 0x0091,
+	0x00b2, 0x00ce, 0x00ef, 0x00fe, 0x00fe, 0x00a4, 0x0080, 0x00cc,
+	0x00aa, 0x0077, 0x00eb, 0x008c, 0x00e6, 0x00e4, 0x0080, 0x0082,
+	0x0082, 0x004a, 0x0094, 0x00b4, 0x00cb, 0x00ec, 0x00fe, 0x00fe,
+	0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080,
+	0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080,
+	0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080,
+	0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080,
+	0x0080, 0x00fd, 0x0088, 0x00fe, 0x00ff, 0x00e4, 0x00db, 0x0080,
+	0x0080, 0x0080, 0x0080, 0x0080, 0x00bd, 0x0081, 0x00f2, 0x00ff,
+	0x00e3, 0x00d5, 0x00ff, 0x00db, 0x0080, 0x0080, 0x0080, 0x006a,
+	0x007e, 0x00e3, 0x00fc, 0x00d6, 0x00d1, 0x00ff, 0x00ff, 0x0080,
+	0x0080, 0x0080, 0x0001, 0x0062, 0x00f8, 0x00ff, 0x00ec, 0x00e2,
+	0x00ff, 0x00ff, 0x0080, 0x0080, 0x0080, 0x00b5, 0x0085, 0x00ee,
+	0x00fe, 0x00dd, 0x00ea, 0x00ff, 0x009a, 0x0080, 0x0080, 0x0080,
+	0x004e, 0x0086, 0x00ca, 0x00f7, 0x00c6, 0x00b4, 0x00ff, 0x00db,
+	0x0080, 0x0080, 0x0080, 0x0001, 0x00b9, 0x00f9, 0x00ff, 0x00f3,
+	0x00ff, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x00b8, 0x0096,
+	0x00f7, 0x00ff, 0x00ec, 0x00e0, 0x0080, 0x0080, 0x0080, 0x0080,
+	0x0080, 0x004d, 0x006e, 0x00d8, 0x00ff, 0x00ec, 0x00e6, 0x0080,
+	0x0080, 0x0080, 0x0080, 0x0080, 0x0001, 0x0065, 0x00fb, 0x00ff,
+	0x00f1, 0x00ff, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x00aa,
+	0x008b, 0x00f1, 0x00fc, 0x00ec, 0x00d1, 0x00ff, 0x00ff, 0x0080,
+	0x0080, 0x0080, 0x0025, 0x0074, 0x00c4, 0x00f3, 0x00e4, 0x00ff,
+	0x00ff, 0x00ff, 0x0080, 0x0080, 0x0080, 0x0001, 0x00cc, 0x00fe,
+	0x00ff, 0x00f5, 0x00ff, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080,
+	0x00cf, 0x00a0, 0x00fa, 0x00ff, 0x00ee, 0x0080, 0x0080, 0x0080,
+	0x0080, 0x0080, 0x0080, 0x0066, 0x0067, 0x00e7, 0x00ff, 0x00d3,
+	0x00ab, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0001, 0x0098,
+	0x00fc, 0x00ff, 0x00f0, 0x00ff, 0x0080, 0x0080, 0x0080, 0x0080,
+	0x0080, 0x00b1, 0x0087, 0x00f3, 0x00ff, 0x00ea, 0x00e1, 0x0080,
+	0x0080, 0x0080, 0x0080, 0x0080, 0x0050, 0x0081, 0x00d3, 0x00ff,
+	0x00c2, 0x00e0, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0001,
+	0x0001, 0x00ff, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080,
+	0x0080, 0x0080, 0x00f6, 0x0001, 0x00ff, 0x0080, 0x0080, 0x0080,
+	0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x00ff, 0x0080, 0x0080,
+	0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080,
+	0x00c6, 0x0023, 0x00ed, 0x00df, 0x00c1, 0x00bb, 0x00a2, 0x00a0,
+	0x0091, 0x009b, 0x003e, 0x0083, 0x002d, 0x00c6, 0x00dd, 0x00ac,
+	0x00b0, 0x00dc, 0x009d, 0x00fc, 0x00dd, 0x0001, 0x0044, 0x002f,
+	0x0092, 0x00d0, 0x0095, 0x00a7, 0x00dd, 0x00a2, 0x00ff, 0x00df,
+	0x0080, 0x0001, 0x0095, 0x00f1, 0x00ff, 0x00dd, 0x00e0, 0x00ff,
+	0x00ff, 0x0080, 0x0080, 0x0080, 0x00b8, 0x008d, 0x00ea, 0x00fd,
+	0x00de, 0x00dc, 0x00ff, 0x00c7, 0x0080, 0x0080, 0x0080, 0x0051,
+	0x0063, 0x00b5, 0x00f2, 0x00b0, 0x00be, 0x00f9, 0x00ca, 0x00ff,
+	0x00ff, 0x0080, 0x0001, 0x0081, 0x00e8, 0x00fd, 0x00d6, 0x00c5,
+	0x00f2, 0x00c4, 0x00ff, 0x00ff, 0x0080, 0x0063, 0x0079, 0x00d2,
+	0x00fa, 0x00c9, 0x00c6, 0x00ff, 0x00ca, 0x0080, 0x0080, 0x0080,
+	0x0017, 0x005b, 0x00a3, 0x00f2, 0x00aa, 0x00bb, 0x00f7, 0x00d2,
+	0x00ff, 0x00ff, 0x0080, 0x0001, 0x00c8, 0x00f6, 0x00ff, 0x00ea,
+	0x00ff, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x006d, 0x00b2,
+	0x00f1, 0x00ff, 0x00e7, 0x00f5, 0x00ff, 0x00ff, 0x0080, 0x0080,
+	0x0080, 0x002c, 0x0082, 0x00c9, 0x00fd, 0x00cd, 0x00c0, 0x00ff,
+	0x00ff, 0x0080, 0x0080, 0x0080, 0x0001, 0x0084, 0x00ef, 0x00fb,
+	0x00db, 0x00d1, 0x00ff, 0x00a5, 0x0080, 0x0080, 0x0080, 0x005e,
+	0x0088, 0x00e1, 0x00fb, 0x00da, 0x00be, 0x00ff, 0x00ff, 0x0080,
+	0x0080, 0x0080, 0x0016, 0x0064, 0x00ae, 0x00f5, 0x00ba, 0x00a1,
+	0x00ff, 0x00c7, 0x0080, 0x0080, 0x0080, 0x0001, 0x00b6, 0x00f9,
+	0x00ff, 0x00e8, 0x00eb, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080,
+	0x007c, 0x008f, 0x00f1, 0x00ff, 0x00e3, 0x00ea, 0x0080, 0x0080,
+	0x0080, 0x0080, 0x0080, 0x0023, 0x004d, 0x00b5, 0x00fb, 0x00c1,
+	0x00d3, 0x00ff, 0x00cd, 0x0080, 0x0080, 0x0080, 0x0001, 0x009d,
+	0x00f7, 0x00ff, 0x00ec, 0x00e7, 0x00ff, 0x00ff, 0x0080, 0x0080,
+	0x0080, 0x0079, 0x008d, 0x00eb, 0x00ff, 0x00e1, 0x00e3, 0x00ff,
+	0x00ff, 0x0080, 0x0080, 0x0080, 0x002d, 0x0063, 0x00bc, 0x00fb,
+	0x00c3, 0x00d9, 0x00ff, 0x00e0, 0x0080, 0x0080, 0x0080, 0x0001,
+	0x0001, 0x00fb, 0x00ff, 0x00d5, 0x00ff, 0x0080, 0x0080, 0x0080,
+	0x0080, 0x0080, 0x00cb, 0x0001, 0x00f8, 0x00ff, 0x00ff, 0x0080,
+	0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0089, 0x0001, 0x00b1,
+	0x00ff, 0x00e0, 0x00ff, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080,
+	0x00fd, 0x0009, 0x00f8, 0x00fb, 0x00cf, 0x00d0, 0x00ff, 0x00c0,
+	0x0080, 0x0080, 0x0080, 0x00af, 0x000d, 0x00e0, 0x00f3, 0x00c1,
+	0x00b9, 0x00f9, 0x00c6, 0x00ff, 0x00ff, 0x0080, 0x0049, 0x0011,
+	0x00ab, 0x00dd, 0x00a1, 0x00b3, 0x00ec, 0x00a7, 0x00ff, 0x00ea,
+	0x0080, 0x0001, 0x005f, 0x00f7, 0x00fd, 0x00d4, 0x00b7, 0x00ff,
+	0x00ff, 0x0080, 0x0080, 0x0080, 0x00ef, 0x005a, 0x00f4, 0x00fa,
+	0x00d3, 0x00d1, 0x00ff, 0x00ff, 0x0080, 0x0080, 0x0080, 0x009b,
+	0x004d, 0x00c3, 0x00f8, 0x00bc, 0x00c3, 0x00ff, 0x00ff, 0x0080,
+	0x0080, 0x0080, 0x0001, 0x0018, 0x00ef, 0x00fb, 0x00da, 0x00db,
+	0x00ff, 0x00cd, 0x0080, 0x0080, 0x0080, 0x00c9, 0x0033, 0x00db,
+	0x00ff, 0x00c4, 0x00ba, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080,
+	0x0045, 0x002e, 0x00be, 0x00ef, 0x00c9, 0x00da, 0x00ff, 0x00e4,
+	0x0080, 0x0080, 0x0080, 0x0001, 0x00bf, 0x00fb, 0x00ff, 0x00ff,
+	0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x00df, 0x00a5,
+	0x00f9, 0x00ff, 0x00d5, 0x00ff, 0x0080, 0x0080, 0x0080, 0x0080,
+	0x0080, 0x008d, 0x007c, 0x00f8, 0x00ff, 0x00ff, 0x0080, 0x0080,
+	0x0080, 0x0080, 0x0080, 0x0080, 0x0001, 0x0010, 0x00f8, 0x00ff,
+	0x00ff, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x00be,
+	0x0024, 0x00e6, 0x00ff, 0x00ec, 0x00ff, 0x0080, 0x0080, 0x0080,
+	0x0080, 0x0080, 0x0095, 0x0001, 0x00ff, 0x0080, 0x0080, 0x0080,
+	0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0001, 0x00e2, 0x00ff,
+	0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080,
+	0x00f7, 0x00c0, 0x00ff, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080,
+	0x0080, 0x0080, 0x0080, 0x00f0, 0x0080, 0x00ff, 0x0080, 0x0080,
+	0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0001, 0x0086,
+	0x00fc, 0x00ff, 0x00ff, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080,
+	0x0080, 0x00d5, 0x003e, 0x00fa, 0x00ff, 0x00ff, 0x0080, 0x0080,
+	0x0080, 0x0080, 0x0080, 0x0080, 0x0037, 0x005d, 0x00ff, 0x0080,
+	0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080,
+	0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080,
+	0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080,
+	0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080,
+	0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080,
+	0x00ca, 0x0018, 0x00d5, 0x00eb, 0x00ba, 0x00bf, 0x00dc, 0x00a0,
+	0x00f0, 0x00af, 0x00ff, 0x007e, 0x0026, 0x00b6, 0x00e8, 0x00a9,
+	0x00b8, 0x00e4, 0x00ae, 0x00ff, 0x00bb, 0x0080, 0x003d, 0x002e,
+	0x008a, 0x00db, 0x0097, 0x00b2, 0x00f0, 0x00aa, 0x00ff, 0x00d8,
+	0x0080, 0x0001, 0x0070, 0x00e6, 0x00fa, 0x00c7, 0x00bf, 0x00f7,
+	0x009f, 0x00ff, 0x00ff, 0x0080, 0x00a6, 0x006d, 0x00e4, 0x00fc,
+	0x00d3, 0x00d7, 0x00ff, 0x00ae, 0x0080, 0x0080, 0x0080, 0x0027,
+	0x004d, 0x00a2, 0x00e8, 0x00ac, 0x00b4, 0x00f5, 0x00b2, 0x00ff,
+	0x00ff, 0x0080, 0x0001, 0x0034, 0x00dc, 0x00f6, 0x00c6, 0x00c7,
+	0x00f9, 0x00dc, 0x00ff, 0x00ff, 0x0080, 0x007c, 0x004a, 0x00bf,
+	0x00f3, 0x00b7, 0x00c1, 0x00fa, 0x00dd, 0x00ff, 0x00ff, 0x0080,
+	0x0018, 0x0047, 0x0082, 0x00db, 0x009a, 0x00aa, 0x00f3, 0x00b6,
+	0x00ff, 0x00ff, 0x0080, 0x0001, 0x00b6, 0x00e1, 0x00f9, 0x00db,
+	0x00f0, 0x00ff, 0x00e0, 0x0080, 0x0080, 0x0080, 0x0095, 0x0096,
+	0x00e2, 0x00fc, 0x00d8, 0x00cd, 0x00ff, 0x00ab, 0x0080, 0x0080,
+	0x0080, 0x001c, 0x006c, 0x00aa, 0x00f2, 0x00b7, 0x00c2, 0x00fe,
+	0x00df, 0x00ff, 0x00ff, 0x0080, 0x0001, 0x0051, 0x00e6, 0x00fc,
+	0x00cc, 0x00cb, 0x00ff, 0x00c0, 0x0080, 0x0080, 0x0080, 0x007b,
+	0x0066, 0x00d1, 0x00f7, 0x00bc, 0x00c4, 0x00ff, 0x00e9, 0x0080,
+	0x0080, 0x0080, 0x0014, 0x005f, 0x0099, 0x00f3, 0x00a4, 0x00ad,
+	0x00ff, 0x00cb, 0x0080, 0x0080, 0x0080, 0x0001, 0x00de, 0x00f8,
+	0x00ff, 0x00d8, 0x00d5, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080,
+	0x00a8, 0x00af, 0x00f6, 0x00fc, 0x00eb, 0x00cd, 0x00ff, 0x00ff,
+	0x0080, 0x0080, 0x0080, 0x002f, 0x0074, 0x00d7, 0x00ff, 0x00d3,
+	0x00d4, 0x00ff, 0x00ff, 0x0080, 0x0080, 0x0080, 0x0001, 0x0079,
+	0x00ec, 0x00fd, 0x00d4, 0x00d6, 0x00ff, 0x00ff, 0x0080, 0x0080,
+	0x0080, 0x008d, 0x0054, 0x00d5, 0x00fc, 0x00c9, 0x00ca, 0x00ff,
+	0x00db, 0x0080, 0x0080, 0x0080, 0x002a, 0x0050, 0x00a0, 0x00f0,
+	0x00a2, 0x00b9, 0x00ff, 0x00cd, 0x0080, 0x0080, 0x0080, 0x0001,
+	0x0001, 0x00ff, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080,
+	0x0080, 0x0080, 0x00f4, 0x0001, 0x00ff, 0x0080, 0x0080, 0x0080,
+	0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x00ee, 0x0001, 0x00ff,
+	0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080, 0x0080,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00b0, 0x00f6, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00df, 0x00f1, 0x00fc, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00f9,
+	0x00fd, 0x00fd, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00f4, 0x00fc, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ea, 0x00fe, 0x00fe,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00fd, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00f6, 0x00fe, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ef, 0x00fd,
+	0x00fe, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00fe, 0x00ff, 0x00fe, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00f8, 0x00fe, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fb,
+	0x00ff, 0x00fe, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fd, 0x00fe,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00fb, 0x00fe, 0x00fe, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00fe, 0x00ff, 0x00fe, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fe,
+	0x00fd, 0x00ff, 0x00fe, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00fa, 0x00ff, 0x00fe, 0x00ff, 0x00fe, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fe, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00d9, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00e1, 0x00fc, 0x00f1, 0x00fd, 0x00ff,
+	0x00ff, 0x00fe, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ea, 0x00fa,
+	0x00f1, 0x00fa, 0x00fd, 0x00ff, 0x00fd, 0x00fe, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00fe, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00df, 0x00fe, 0x00fe, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ee,
+	0x00fd, 0x00fe, 0x00fe, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00f8, 0x00fe, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00f9, 0x00fe, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fd, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00f7, 0x00fe,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fd, 0x00fe, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fc,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fe, 0x00fe,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00fd, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fe,
+	0x00fd, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00fa, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fe, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ba, 0x00fb, 0x00fa, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ea, 0x00fb, 0x00f4, 0x00fe, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fb, 0x00fb,
+	0x00f3, 0x00fd, 0x00fe, 0x00ff, 0x00fe, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00fd, 0x00fe, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ec, 0x00fd, 0x00fe, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fb,
+	0x00fd, 0x00fd, 0x00fe, 0x00fe, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00fe, 0x00fe, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fe, 0x00fe, 0x00fe,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fe, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fe, 0x00fe,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00fe, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00fe,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
+	0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff,
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+	0x3cee, 0x3cef, 0x3cec, 0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d,
+	0xce00, 0xf33e, 0xe41e, 0x0164, 0xe09e, 0xa202, 0xae3e, 0x9f07,
+	0xe0c0, 0x005c, 0xe0c1, 0x0059, 0x3eed, 0xa203, 0x5aed, 0xe052,
+	0xf08a, 0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00,
+	0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2, 0x0008, 0xf00e,
+	0x28ee, 0xe412, 0x013d, 0xe190, 0xe0c0, 0x005c, 0xe0c1, 0x0059,
+	0x3eed, 0xa203, 0x5aed, 0xe052, 0xf08a, 0xe0c1, 0x005d, 0xe055,
+	0xe0c3, 0x005d, 0xa202, 0xce00, 0xe0c0, 0x004a, 0xf08a, 0xe41e,
+	0x019c, 0xe408, 0x005c, 0xe40e, 0x0058, 0xe190, 0xe0c0, 0x043d,
+	0xa1ee, 0xf7d8, 0xe004, 0x0060, 0xe0c2, 0x0009, 0xa200, 0xe0c2,
+	0x0009, 0xe0c0, 0x000d, 0xf7e8, 0xe41e, 0x00b2, 0xe41e, 0x00e2,
+	0xe41e, 0x012c, 0xd071, 0x242a, 0xe181, 0xe41e, 0x0164, 0xe09e,
+	0xa202, 0x9f07, 0xe0c0, 0x0049, 0xe0c1, 0x005b, 0xa111, 0xf033,
+	0xe0c0, 0x0048, 0xe0c2, 0x0047, 0xe0c0, 0x0059, 0xae02, 0xe000,
+	0x02f9, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a, 0xe008, 0xffff,
+	0x3cee, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11, 0xe056, 0x3cef,
+	0xe40e, 0x0058, 0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2,
+	0x0008, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xe0c0, 0x0059, 0xf7ea,
+	0xa11e, 0xf198, 0xa202, 0xe0c2, 0x0058, 0xe004, 0xca20, 0xae20,
+	0xe005, 0x210a, 0xe056, 0xe0c2, 0x0070, 0xe004, 0x0000, 0xae20,
+	0xe00a, 0x9cea, 0xe0c2, 0x0071, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+	0x0058, 0xf64e, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058, 0xd027,
+	0x0001, 0xe42e, 0xa200, 0xe0c1, 0x005b, 0xf21b, 0xa23c, 0xa103,
+	0xf37b, 0xa24c, 0xa103, 0xf34b, 0xa258, 0xa103, 0xf1db, 0xe004,
+	0x003a, 0xa103, 0xf2db, 0xe004, 0x003f, 0xa103, 0xf29b, 0xe004,
+	0x0045, 0xa103, 0xf25b, 0xa103, 0xf14b, 0xe004, 0x0063, 0xa103,
+	0xf1ab, 0xe004, 0x006a, 0xa107, 0xf1bb, 0xa200, 0xe0c1, 0x005e,
+	0xf17b, 0xa028, 0xf15e, 0xe0c1, 0x005e, 0xf12b, 0xa010, 0xf10e,
+	0xe004, 0x0049, 0xe0c1, 0x005e, 0xf0bb, 0xa010, 0xa103, 0xf08b,
+	0xa010, 0xf06e, 0xe0c1, 0x005e, 0xf03b, 0xe004, 0x0074, 0xae16,
+	0xe0c1, 0x0040, 0xe041, 0xce21, 0xd111, 0x0000, 0xd112, 0x2800,
+	0xd113, 0x000b, 0xe1e1, 0xe42e, 0xe41e, 0x0213, 0xe0c0, 0x0059,
+	0xa102, 0xe42a, 0xe0c0, 0x005b, 0xa810, 0xf058, 0xa206, 0xe41e,
+	0x0153, 0xe42e, 0xe004, 0x0319, 0xe67c, 0xe0c0, 0x005b, 0xa810,
+	0xf058, 0xa204, 0xe41e, 0x0153, 0xe42e, 0xe004, 0x031b, 0xe67c,
+	0xa200, 0xc401, 0xe188, 0x00eb, 0x3d11, 0xe161, 0x00f2, 0xe188,
+	0x0b0d, 0x3d11, 0xe42e, 0x3cec, 0xe0c0, 0x0041, 0xe005, 0x0000,
+	0xae11, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0c00, 0x88ec,
+	0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0059, 0xa106, 0xf048,
+	0xe004, 0x0076, 0xe42e, 0xe0c0, 0x0059, 0xa10c, 0xf038, 0xe004,
+	0x0071, 0xe004, 0x0070, 0xe42e, 0xe0c0, 0x006b, 0xe167, 0x01a0,
+	0x3d07, 0xe0c0, 0x0414, 0xe428, 0xe0c1, 0x0044, 0xa809, 0xae33,
+	0xe0c0, 0x006a, 0xe167, 0x01a0, 0x3517, 0x3d17, 0xe0c0, 0x006b,
+	0xe056, 0x3517, 0x3d07, 0xe42e, 0xe167, 0x01a0, 0x2907, 0xe0c2,
+	0x0151, 0xa204, 0xe0c2, 0x0150, 0xe0c0, 0x0150, 0xa804, 0xf7da,
+	0xa208, 0xe0c2, 0x0150, 0xe42e, 0xe0c0, 0x004a, 0xe42a, 0xe0c0,
+	0x005b, 0xa110, 0xf142, 0xe0c0, 0x0059, 0xa102, 0xe41a, 0x01be,
+	0xe0c0, 0x0059, 0xa106, 0xe41a, 0x01c5, 0xe0c0, 0x0047, 0xe0c2,
+	0x0048, 0xa200, 0xe0c2, 0x004a, 0xa202, 0xe42e, 0xe0c0, 0x0047,
+	0xe0c2, 0x0049, 0xa200, 0xe0c2, 0x004a, 0xe42e, 0xe0c0, 0x004a,
+	0xa802, 0xa220, 0xe0c2, 0x0070, 0xe42e, 0xe0c0, 0x004a, 0xa802,
+	0xa220, 0xe0c2, 0x0076, 0xa200, 0xe0c2, 0x0072, 0xa2fc, 0xe0c2,
+	0x0077, 0xa2fa, 0xe0c2, 0x0071, 0xe42e, 0xe428, 0xa202, 0xe0c2,
+	0x004a, 0xe0c0, 0x0111, 0xf7e8, 0xca28, 0xf7f8, 0xca48, 0xa802,
+	0xf7e8, 0xa208, 0xae14, 0xa102, 0xe190, 0xf7e2, 0xe0c0, 0x041f,
+	0xf7e8, 0xa200, 0xe0c2, 0x041c, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8,
+	0xe004, 0x0078, 0xe0c2, 0x0009, 0xa200, 0xe0c2, 0x0009, 0xe0c0,
+	0x000d, 0xf7e8, 0xe42e, 0xe41e, 0x0213, 0xd160, 0x0620, 0xe004,
+	0x0019, 0xae18, 0xcec0, 0xe42e, 0xe41e, 0x0228, 0xe000, 0x0040,
+	0xce50, 0xa200, 0xd022, 0x00ff, 0xe184, 0x020f, 0xce52, 0xe190,
+	0xe41e, 0x0230, 0xe42e, 0xa204, 0xae22, 0xcc9e, 0xa200, 0xcc72,
+	0xcc8c, 0xcc8e, 0xe004, 0xa810, 0xae20, 0xe00a, 0x9322, 0xce4a,
+	0xd16f, 0x0003, 0xe190, 0xe190, 0xe190, 0xd16f, 0x0000, 0xe42e,
+	0xe004, 0x0030, 0xce50, 0xca50, 0xa802, 0xf7ea, 0xc000, 0xe42e,
+	0xe004, 0x0020, 0xce50, 0xe42e, 0xa200, 0xe0c2, 0x041c, 0xe42e,
+	0xe41e, 0x028d, 0xe42a, 0xe0c0, 0x0061, 0xe008, 0x001f, 0xe00a,
+	0x0100, 0xe0c2, 0x041c, 0xe41e, 0x02c3, 0xe41e, 0x02f4, 0xae12,
+	0xe0c2, 0x041e, 0xe41e, 0x02e7, 0xe42e, 0xe41e, 0x02b1, 0xe42a,
+	0xe0c0, 0x041f, 0xf7e8, 0xe0c0, 0x0210, 0xa804, 0xf118, 0xe0c0,
+	0x0215, 0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0216, 0xf0be, 0xe0c0,
+	0x0213, 0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0214, 0xf03e, 0xe0c0,
+	0x020b, 0xe00a, 0x0100, 0xe0c2, 0x041c, 0xe41e, 0x02c3, 0xe41e,
+	0x02f4, 0xae12, 0xe0c1, 0x0210, 0xa803, 0xae15, 0xe056, 0xe0c1,
+	0x0204, 0xaf0b, 0xa87f, 0xae07, 0xe056, 0xe0c1, 0x0204, 0xa80f,
+	0xe056, 0xe0c2, 0x041e, 0xe41e, 0x02e7, 0xe42e, 0xe0c0, 0x041f,
+	0xf7e8, 0xa200, 0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xa203,
+	0xae19, 0xe052, 0xf1da, 0xe0c0, 0x0060, 0xaf08, 0xa806, 0xf18a,
+	0xe0c0, 0x0060, 0xa81e, 0xe016, 0xe0c1, 0x0060, 0xa821, 0xe017,
+	0xe056, 0xf0ea, 0xe0c0, 0x0044, 0xaf12, 0xa806, 0xe016, 0xe0c1,
+	0x0044, 0xaf17, 0xa803, 0xe056, 0xf03a, 0xa202, 0xe42e, 0xa200,
+	0xe42e, 0xe0c0, 0x0044, 0xa203, 0xae19, 0xe052, 0xf0ba, 0xe41e,
+	0x028d, 0xf088, 0xe0c0, 0x0044, 0xaf12, 0xa806, 0xf038, 0xa202,
+	0xe42e, 0xa200, 0xe42e, 0xe0c0, 0x041c, 0xe008, 0x00ff, 0xcca4,
+	0xc785, 0xe018, 0xe000, 0x0500, 0xa002, 0xae04, 0xe0c2, 0x041a,
+	0xa202, 0xe0c2, 0x0418, 0xe0c0, 0x0419, 0xf7ea, 0xe0c0, 0x041b,
+	0xaf20, 0xa01e, 0xaf08, 0xae28, 0xe0c1, 0x041b, 0xe009, 0xffff,
+	0xa01f, 0xaf09, 0xae09, 0xe056, 0xe0c2, 0x041d, 0xe42e, 0xe0c0,
+	0x041c, 0xe00a, 0x0200, 0xe0c2, 0x041c, 0xe0c0, 0x041c, 0xe00c,
+	0x0200, 0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xaf04, 0xa802,
+	0xe42e, 0xe40e, 0x1126, 0xe40e, 0x031d, 0xe40e, 0x0321, 0xe40e,
+	0x0325, 0xe40e, 0x032d, 0xe40e, 0x0331, 0xe40e, 0x0335, 0xe40e,
+	0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x0339, 0xe40e, 0x00a4, 0xe40e,
+	0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x1146, 0xe40e, 0x00a4, 0xe40e,
+	0x00a4, 0xe40e, 0x062b, 0xe40e, 0x0649, 0xe41e, 0x033d, 0xe40e,
+	0x00a4, 0xe41e, 0x036a, 0xe40e, 0x00a4, 0xe41e, 0x0234, 0xe41e,
+	0x0376, 0xe41e, 0x0286, 0xe40e, 0x00a4, 0xe41e, 0x03e6, 0xe40e,
+	0x00a4, 0xe41e, 0x0415, 0xe40e, 0x00a4, 0xe41e, 0x0476, 0xe40e,
+	0x00a4, 0xe41e, 0x105c, 0xe40e, 0x00a4, 0xa210, 0xe0c2, 0x0100,
+	0xa200, 0xe0c2, 0x0128, 0xd130, 0x0008, 0xe41e, 0x0148, 0xe41e,
+	0x0213, 0xe41e, 0x05dc, 0xa200, 0x3c2a, 0x3c33, 0xcc72, 0xcc44,
+	0x3ccb, 0x3ccc, 0xe41e, 0x04a9, 0xf12a, 0xe41e, 0x08ae, 0xe41e,
+	0x1106, 0xe41e, 0x1131, 0x2815, 0xe40a, 0x0360, 0xe418, 0x0d87,
+	0xe41e, 0x10b9, 0xa202, 0xe0c2, 0x0070, 0xe42e, 0xa200, 0xe0c2,
+	0x0070, 0xe42e, 0xd130, 0x0008, 0x28be, 0xe428, 0x28bf, 0xf06a,
+	0xa200, 0x3c4d, 0xe41e, 0x1127, 0xe42e, 0xe42e, 0xd130, 0x0008,
+	0xa200, 0xcc44, 0xcc4a, 0xcc4c, 0xcfce, 0xe0c2, 0x0074, 0x3c65,
+	0xe0c0, 0x0065, 0xaf06, 0x3066, 0xaf02, 0x3067, 0xaf02, 0x3068,
+	0xe41e, 0x061b, 0xe41e, 0x0d0b, 0xe41e, 0x0d36, 0x28bf, 0xf24a,
+	0xc872, 0x3c07, 0x28c0, 0xf09a, 0xe0c0, 0x0066, 0x344a, 0x3c4b,
+	0xe0c0, 0x0067, 0xae04, 0x3c4c, 0xa200, 0x3c4d, 0xe41e, 0x1127,
+	0xe41e, 0x0213, 0xa200, 0x3cdf, 0x3ce0, 0xe41e, 0x11ed, 0xe41e,
+	0x1209, 0xe41e, 0x1226, 0xe41e, 0x1160, 0xe41e, 0x124a, 0xe41e,
+	0x1255, 0x2807, 0xcc72, 0xd130, 0x0008, 0xd1e0, 0x0000, 0xd1ff,
+	0x03b0, 0xd199, 0x0224, 0xd03a, 0x0000, 0xd04b, 0x0001, 0xd04c,
+	0x0000, 0xd008, 0x0000, 0xe41e, 0x064f, 0x28bf, 0xf02a, 0xf03e,
+	0x28be, 0xf01a, 0x2c2a, 0xa002, 0x3c2a, 0x2c33, 0xa002, 0x3c33,
+	0xe0c2, 0x0070, 0x2829, 0xe0c2, 0x0071, 0x281f, 0xe0c2, 0x0073,
+	0xd039, 0x0000, 0xc84a, 0xc84d, 0xae20, 0xe056, 0xe0c2, 0x0053,
+	0xe41e, 0x05f0, 0xa202, 0xe0c2, 0x0076, 0xe42e, 0xe41e, 0x0409,
+	0xe41e, 0x0174, 0xe0c0, 0x0042, 0xce20, 0xd111, 0x04c0, 0xd112,
+	0x00c0, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe0c0, 0x0060, 0x3c32,
+	0xe0c0, 0x0061, 0x3c70, 0xe004, 0x0580, 0xe096, 0xe0c0, 0x0062,
+	0x3513, 0x3d13, 0xe0c0, 0x0063, 0x3513, 0x3d13, 0xe41e, 0x0d0b,
+	0xe42e, 0xe167, 0x0488, 0xe166, 0x0064, 0xd022, 0x0003, 0xe184,
+	0x0413, 0x9e16, 0x3517, 0x3d17, 0xe42e, 0xd130, 0x0008, 0x28bf,
+	0xf24a, 0xc872, 0x3c07, 0x28c0, 0xf09a, 0xe0c0, 0x0061, 0x344a,
+	0x3c4b, 0xe0c0, 0x0062, 0xae04, 0x3c4c, 0xa200, 0x3c4d, 0xe41e,
+	0x1127, 0xe41e, 0x0213, 0xa200, 0x3cdf, 0x3ce0, 0xe41e, 0x11ed,
+	0xe41e, 0x1209, 0xe41e, 0x1226, 0xe41e, 0x1160, 0xe41e, 0x124a,
+	0xe41e, 0x1255, 0x2807, 0xcc72, 0xe0c0, 0x0060, 0xa80e, 0xf0da,
+	0xa102, 0xf1fa, 0xa102, 0xf20a, 0xa102, 0xf20a, 0xa102, 0xa102,
+	0xa202, 0xe0c2, 0x0070, 0xe42e, 0xe0c0, 0x0060, 0xaf06, 0xa802,
+	0x3073, 0xf0ca, 0xe0c0, 0x0063, 0x3478, 0x3c79, 0xe0c1, 0x0064,
+	0x367a, 0x3e7b, 0xe056, 0xe01a, 0x3c73, 0xe41e, 0x05b9, 0xf0ee,
+	0xe41e, 0x05c4, 0xf0be, 0xa214, 0xf02e, 0xa216, 0x3c30, 0xa200,
+	0x3c2f, 0xe41e, 0x1267, 0xe41e, 0x1291, 0x28bf, 0xf02a, 0xf03e,
+	0x28be, 0xf01a, 0xa202, 0xe0c2, 0x0070, 0xe42e, 0xe41e, 0x1115,
+	0xa200, 0xce92, 0xe0c0, 0x0060, 0xa802, 0xf158, 0xe0c0, 0x0060,
+	0xaf04, 0xa802, 0x3073, 0xf0ca, 0xe0c0, 0x0063, 0x3478, 0x3c79,
+	0xe0c1, 0x0064, 0x367a, 0x3e7b, 0xe056, 0xe01a, 0x3c73, 0xe41e,
+	0x07ae, 0xf03e, 0xe41e, 0x0837, 0xc870, 0xaf06, 0x3c45, 0xe0c2,
+	0x0070, 0xe004, 0x0080, 0xcc6e, 0xbadf, 0xe0c0, 0x0042, 0xce20,
+	0xd111, 0x0000, 0xd112, 0x0100, 0xd113, 0x0012, 0xca28, 0xf7f8,
+	0xe42e, 0xe0c0, 0x0074, 0xa806, 0x3cc9, 0xe0c0, 0x0074, 0xaf04,
+	0x3cca, 0xe0c0, 0x0064, 0x3450, 0x3c51, 0x2850, 0xa01e, 0xaf08,
+	0x3c50, 0x2851, 0xa01e, 0xaf08, 0x3c51, 0xe0c0, 0x0065, 0x3418,
+	0x3c17, 0x2818, 0xa002, 0x3c18, 0x2c17, 0xc710, 0x7c18, 0xe008,
+	0xffff, 0xa002, 0xaf02, 0x3c88, 0xe0c0, 0x0062, 0xaf04, 0x301b,
+	0xaf06, 0x30b8, 0xe0c1, 0x0071, 0x3eb9, 0xaf02, 0x30c8, 0xaf02,
+	0x30c7, 0xaf04, 0xaf02, 0xe0c0, 0x0068, 0xe049, 0xa83f, 0xae3f,
+	0xaf3f, 0x3e24, 0xe049, 0xaf0b, 0x3226, 0xe049, 0xaf0d, 0xa807,
+	0x3e2c, 0xe049, 0xaf11, 0xa81f, 0xaf41, 0xae41, 0xae03, 0x3e2d,
+	0xe049, 0xaf19, 0xa81f, 0xaf41, 0xae41, 0xae03, 0x3e2e, 0x282c,
+	0x4c2d, 0x4c2e, 0xe01a, 0x3c25, 0xe0c0, 0x0069, 0x3038, 0xaf02,
+	0x3039, 0xaf02, 0x3c3a, 0xe0c0, 0x006a, 0x3c14, 0xe0c0, 0x006b,
+	0x3480, 0x3015, 0xaf02, 0xe008, 0x7fff, 0x3c7f, 0xf028, 0x3c15,
+	0x2880, 0xaf1e, 0x3091, 0x2880, 0xe008, 0x7fff, 0x3c80, 0xe0c0,
+	0x006c, 0x3481, 0x3c82, 0xe0c0, 0x006d, 0x3c1c, 0xa20a, 0x3c10,
+	0xa002, 0x3c12, 0xa202, 0x3c13, 0xa102, 0x3c22, 0xa200, 0x3c21,
+	0x3c20, 0x3c27, 0xa204, 0x3c11, 0xa234, 0x3c23, 0x8450, 0x8251,
+	0xe018, 0x3c52, 0xa201, 0xe002, 0x00c8, 0xb425, 0xe002, 0x0190,
+	0xb425, 0x3e36, 0xe0c0, 0x0075, 0xe166, 0x0600, 0x3516, 0x3d16,
+	0xe0c0, 0x0076, 0xe049, 0xa806, 0x3cd7, 0xe04a, 0xaf04, 0x30d9,
+	0xaf02, 0xa81e, 0x3cd8, 0x28d9, 0xe016, 0x3cd9, 0xae02, 0x4cd9,
+	0xae02, 0x4cd9, 0x3cd9, 0x28d8, 0xf028, 0xa21e, 0x3cd8, 0x2850,
+	0x2a51, 0xaf06, 0xaf07, 0x3c08, 0x3e09, 0x8408, 0x8209, 0xe018,
+	0x3cc1, 0xa104, 0xf032, 0xa204, 0x3cc1, 0x2851, 0xaf02, 0x3c08,
+	0x8408, 0x8250, 0xe018, 0x3cc3, 0x3cc6, 0xa202, 0x3c1e, 0xe0c0,
+	0x0043, 0xaf06, 0x30be, 0xaf02, 0x30bf, 0xaf02, 0x30c0, 0xaf02,
+	0x30ce, 0xa202, 0xe42e, 0xcb04, 0xaf20, 0xe000, 0x0490, 0xe09e,
+	0xc872, 0x3d07, 0xcb04, 0xaf20, 0xa002, 0x1850, 0xe428, 0xcb04,
+	0xe008, 0xffff, 0xae0e, 0xe005, 0x0000, 0xae11, 0xe042, 0xe0c1,
+	0x0042, 0xe042, 0xce20, 0xd111, 0x0490, 0xd112, 0x002e, 0xd113,
+	0x0002, 0xca28, 0xf7f8, 0xe42e, 0x204a, 0x4c4b, 0x2e4d, 0xae11,
+	0xe042, 0x0840, 0xe161, 0x0434, 0x3511, 0x3d11, 0x281f, 0xae04,
+	0xe005, 0x0012, 0xae11, 0xe042, 0xe0c1, 0x0042, 0xe042, 0xce20,
+	0xd111, 0x0434, 0xd112, 0x0004, 0xd113, 0x0002, 0xca28, 0xf7f8,
+	0xe42e, 0xa206, 0x3c2f, 0xa20e, 0x3c30, 0xe41e, 0x1267, 0xe41e,
+	0x07ae, 0xe41e, 0x1291, 0xe42e, 0xa206, 0x3c2f, 0xa210, 0x3c30,
+	0xe41e, 0x1267, 0xe41e, 0x0837, 0xe41e, 0x1291, 0xe42e, 0xa200,
+	0x3c2f, 0xa212, 0x3c30, 0xe41e, 0x1267, 0xa204, 0xba84, 0xe41e,
+	0x08a4, 0xe41e, 0x1291, 0xe42e, 0xe0c0, 0x0040, 0xe005, 0x0063,
+	0xae17, 0xe042, 0xe005, 0x1900, 0xae03, 0xe042, 0xce20, 0xd111,
+	0x0700, 0xd112, 0x0200, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e,
+	0x2866, 0x4c67, 0x4c68, 0xe42a, 0xe167, 0x05f0, 0xc410, 0x2866,
+	0xae10, 0x3d17, 0x2852, 0x3d17, 0x8137, 0x2867, 0xae12, 0x2a31,
+	0xe017, 0xe056, 0x3d17, 0x2852, 0xae04, 0x3d17, 0x8137, 0x2868,
+	0xae14, 0x2a1f, 0xe056, 0x3d17, 0x281f, 0xae06, 0x3d17, 0xe0c0,
+	0x0068, 0xce20, 0xd111, 0x05f0, 0xd112, 0x000c, 0xd113, 0x0002,
+	0xca28, 0xf7f8, 0xe42e, 0x2866, 0x4c67, 0x4c68, 0xe42a, 0xe0c0,
+	0x0068, 0xce20, 0xd111, 0x05f0, 0xd112, 0x000c, 0xd113, 0x0003,
+	0xca28, 0xf7f8, 0xe42e, 0xa206, 0xe41e, 0x0153, 0xe0c0, 0x005a,
+	0xe008, 0xffff, 0x3cee, 0xe41e, 0x0213, 0xa200, 0x3cdf, 0x3ce0,
+	0xe41e, 0x11ed, 0xe41e, 0x1209, 0xe41e, 0x1226, 0xe41e, 0x13d7,
+	0xe41e, 0x1160, 0xe41e, 0x124a, 0xe41e, 0x1255, 0xe41e, 0x13df,
+	0xe42e, 0xe41e, 0x13c3, 0xa204, 0xe41e, 0x0153, 0xe42e, 0x2824,
+	0xa83e, 0xae06, 0xcf80, 0xe41e, 0x1291, 0xd1f3, 0x0000, 0x2835,
+	0xcfe4, 0xa200, 0xcfc2, 0xd1e8, 0x0055, 0x2850, 0xa102, 0xae02,
+	0x4c26, 0xae06, 0xcf00, 0xd1d3, 0x000d, 0xd185, 0x0001, 0xe41e,
+	0x108f, 0xe41e, 0x1094, 0x281b, 0xe418, 0x05cf, 0xe41e, 0x0693,
+	0x283d, 0x3c2b, 0xe41e, 0x10be, 0x2829, 0xf05a, 0x281e, 0xa002,
+	0xa802, 0x3c1e, 0xe41e, 0x08e6, 0xe41e, 0x0cd8, 0xe41e, 0x07a8,
+	0xa200, 0x3c53, 0x3c1f, 0xe41e, 0x06d0, 0x2865, 0xaa02, 0x3c65,
+	0x2853, 0x1852, 0xf794, 0xe41e, 0x0cf4, 0xe41e, 0x0af0, 0x2815,
+	0xe418, 0x0d90, 0xe42e, 0xe0c0, 0x0065, 0xa804, 0xf06a, 0xa200,
+	0x3c2a, 0x3cb6, 0xe016, 0x3c89, 0x2814, 0xf048, 0x2c2a, 0xf07a,
+	0xf0ae, 0x28b6, 0xf04a, 0x2a14, 0xe046, 0xf058, 0x3c29, 0xa202,
+	0x3cb6, 0xf05e, 0xa202, 0x3c29, 0x08b6, 0x3cb6, 0xa200, 0x3c72,
+	0xe0c0, 0x0065, 0xa802, 0xe418, 0x06c9, 0xe0c0, 0x0063, 0xa408,
+	0x3c3d, 0x2815, 0xf09a, 0x2829, 0xe41a, 0x0d8a, 0xe41e, 0x0d8d,
+	0x3c3d, 0xe419, 0x06c9, 0x2c2a, 0xe016, 0x3c31, 0xa004, 0x3c2f,
+	0xe42e, 0xa202, 0x3c29, 0x3c72, 0x2835, 0xe0c2, 0x0060, 0xe42e,
+	0x2a31, 0xa20a, 0xb636, 0x3c30, 0xe41e, 0x1267, 0xe41e, 0x0860,
+	0xa202, 0x3ccb, 0xe41e, 0x0703, 0xe41e, 0x08a4, 0xe41e, 0x1291,
+	0x2868, 0xe418, 0x06e7, 0x281f, 0xa002, 0x3c1f, 0xe42e, 0xe167,
+	0x05ec, 0xa200, 0x3d17, 0x2853, 0xa102, 0x3d17, 0xcaaa, 0xae06,
+	0x3517, 0x3d17, 0x281f, 0xae06, 0xe167, 0x05fa, 0x2317, 0x4f17,
+	0xe042, 0xce20, 0xd111, 0x05ec, 0xd112, 0x0004, 0xd113, 0x0002,
+	0xca28, 0xf7f8, 0xe42e, 0x282b, 0xcf96, 0x282c, 0xae0a, 0x2a2d,
+	0xa83f, 0xe056, 0xae0a, 0x2a2e, 0xa83f, 0xe056, 0xcf30, 0x2829,
+	0xcfc4, 0xcf82, 0xd188, 0x0001, 0xa200, 0xcf86, 0x3c3b, 0xa202,
+	0x3c3c, 0xe41e, 0x0739, 0xe41e, 0x07ab, 0x8a5e, 0x0039, 0xe41e,
+	0x0780, 0xc872, 0x1c5e, 0xe008, 0xffff, 0x3c5f, 0x2a15, 0xcb96,
+	0xe419, 0x0d96, 0x2853, 0x1852, 0xf042, 0x283b, 0xe40a, 0x0719,
+	0xcb86, 0xf02a, 0xbbfc, 0x2a15, 0xcb96, 0xf02b, 0x3c2b, 0xa202,
+	0xe42e, 0x2838, 0x2a39, 0xe42a, 0xf0a9, 0x28dc, 0xe42a, 0xa102,
+	0x3cdc, 0xa102, 0xe428, 0xa202, 0x3c3b, 0xe42e, 0x283c, 0x183a,
+	0x2a3c, 0xa003, 0x3e3c, 0xe428, 0xa202, 0x3c3c, 0x3c3b, 0xe42e,
+	0x2a38, 0x2839, 0xe42b, 0xa201, 0xf0a8, 0x28dc, 0xe428, 0xc870,
+	0x1c3a, 0xe424, 0xa209, 0x3ed1, 0x3edc, 0xe42e, 0x28d0, 0xa002,
+	0x3cd0, 0xa102, 0x183a, 0xe428, 0xa203, 0x3ed1, 0x3ed0, 0xe42e,
+	0xa200, 0x3cd1, 0x3cdc, 0xa202, 0x3cd0, 0xe42e, 0xcb1c, 0xf7f8,
+	0xd185, 0x0002, 0xd186, 0x0000, 0x2855, 0xae02, 0x4c54, 0xcf8a,
+	0x2859, 0xcf94, 0xa200, 0xcfdc, 0xcf84, 0x2858, 0xcfd2, 0xe42e,
+	0x2876, 0xf05a, 0xe41e, 0x0b5a, 0xe41e, 0x0b33, 0xcba0, 0xf7f8,
+	0x2854, 0xf0ba, 0xcb18, 0x3c00, 0x2855, 0xf04a, 0x2856, 0xae38,
+	0xcf8c, 0x2857, 0xcf90, 0xf03e, 0xcbd2, 0xcf9a, 0xd1d0, 0x003f,
+	0xa202, 0x3c76, 0xe41e, 0x0a51, 0x2a66, 0xcba0, 0xf7f8, 0xe419,
+	0x0c8d, 0xd186, 0x0001, 0xd185, 0x0004, 0xcb06, 0x3c53, 0xe42e,
+	0xe41e, 0x0a0e, 0xe42e, 0xe41e, 0x0a46, 0xe42e, 0xe004, 0x0042,
+	0xba8e, 0xbac0, 0xbae0, 0xbac0, 0xbac4, 0x8452, 0x8288, 0xe019,
+	0x2852, 0xe002, 0x0063, 0xf070, 0xe04a, 0xe002, 0x05cd, 0xf030,
+	0xa214, 0xf37e, 0x2852, 0xe002, 0x018c, 0xf070, 0xe04a, 0xe002,
+	0x2e68, 0xf030, 0xa228, 0xf2de, 0x2852, 0xe002, 0x0654, 0xf070,
+	0xe04a, 0xe002, 0x9e34, 0xf030, 0xa23c, 0xf23e, 0x2852, 0xe002,
+	0x0e10, 0xf080, 0xe004, 0x0d2f, 0xae0a, 0xe046, 0xf034, 0xa23e,
+	0xf18e, 0x2852, 0xe002, 0x1400, 0xf080, 0xe004, 0x0d2f, 0xae0c,
+	0xe046, 0xf034, 0xa240, 0xf0de, 0x2852, 0xe002, 0x2000, 0xf080,
+	0xe004, 0x03c0, 0xae10, 0xe046, 0xf034, 0xa250, 0xf02e, 0xa254,
+	0xe0c1, 0x0060, 0xaf09, 0xa803, 0xf06b, 0xe0c0, 0x0060, 0xaf10,
+	0xe008, 0x00ff, 0xba8e, 0xa200, 0xbbfc, 0x2810, 0xa108, 0xbbfc,
+	0x2811, 0xbbfc, 0x2811, 0xf048, 0x2812, 0xa108, 0xbbfc, 0x2813,
+	0xbbfc, 0xe190, 0xbac0, 0x2850, 0xa102, 0xbbfc, 0x2851, 0xa102,
+	0xbbfc, 0xe190, 0xbae0, 0xe190, 0xbae0, 0x2873, 0xf038, 0xbac0,
+	0xf0fe, 0xbae0, 0x2878, 0xaf02, 0xbbfc, 0x2879, 0xaf02, 0xbbfc,
+	0x287a, 0xaf02, 0xbbfc, 0x287b, 0xaf02, 0xbbfc, 0xe190, 0xbac0,
+	0xe41e, 0x08a4, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0xa200,
+	0xbbfc, 0xa200, 0xbbfc, 0xbac0, 0x2820, 0xba80, 0x2821, 0xbbfc,
+	0xe408, 0x085d, 0x2822, 0xbbfc, 0xa200, 0xe190, 0xbbfc, 0xe190,
+	0xbac0, 0xe190, 0xbac1, 0xe190, 0x2823, 0xa134, 0xbbfe, 0xa200,
+	0xbbfe, 0x2824, 0xbbfe, 0x2825, 0xba80, 0x2826, 0xba80, 0x2827,
+	0xba80, 0xe41e, 0x08a4, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e,
+	0x2853, 0xbbfc, 0x2829, 0xe016, 0xae02, 0xa00a, 0xbbfc, 0xa200,
+	0xbbfc, 0x2c2a, 0x7010, 0x2831, 0xf03a, 0xa200, 0xbbfc, 0x2811,
+	0xf098, 0x2c33, 0xae02, 0x7012, 0x2820, 0xe40a, 0x0879, 0xa200,
+	0xbbfe, 0x2827, 0xe40a, 0x087e, 0xa200, 0xbbfc, 0x2829, 0xf04a,
+	0xbac0, 0xe190, 0xbac0, 0x282f, 0xe40a, 0x088f, 0x2831, 0xe40a,
+	0x088e, 0xbac0, 0xe190, 0xbac0, 0xe40e, 0x088f, 0xbac0, 0x282b,
+	0x1823, 0xbbfe, 0x2825, 0xe40a, 0x08a0, 0x282c, 0xbbfc, 0xa102,
+	0xe40a, 0x08a0, 0x282d, 0xaf02, 0xbbfe, 0x282e, 0xaf02, 0xbbfe,
+	0xa202, 0xe42e, 0xa200, 0xe42e, 0xbae0, 0xc868, 0xa80e, 0xe42a,
+	0xa110, 0xe012, 0x3c48, 0xa200, 0x7048, 0xe42e, 0xa200, 0x3c34,
+	0xe004, 0x0190, 0x3c75, 0xe0c0, 0x0414, 0xe428, 0xa200, 0xe0c2,
+	0x0150, 0xe0c0, 0x0151, 0xf7e8, 0xa201, 0xae09, 0xa907, 0xae09,
+	0xa907, 0xae09, 0xa907, 0xae09, 0xa901, 0xae09, 0xa907, 0xae09,
+	0xa905, 0xae09, 0xa905, 0xe0c3, 0x0152, 0xa241, 0xae11, 0xa911,
+	0xae11, 0xa911, 0xe0c3, 0x0153, 0xa201, 0xae21, 0xa902, 0xae02,
+	0xa902, 0xae04, 0xa900, 0x3cde, 0xe056, 0xe0c2, 0x015c, 0xa202,
+	0xe0c2, 0x0150, 0xe0c0, 0x0150, 0xf7ea, 0xe42e, 0xe41e, 0x0c23,
+	0xa210, 0xe0c2, 0x0100, 0xa200, 0xe0c2, 0x0128, 0x2a29, 0xe004,
+	0x016f, 0xf039, 0xe004, 0x0168, 0xe0c2, 0x017c, 0xa200, 0xe0c2,
+	0x017d, 0xe0c2, 0x013d, 0xe0c0, 0x0050, 0xe049, 0xe008, 0x007f,
+	0x3c00, 0xaf11, 0xe009, 0x007f, 0x3e01, 0x4600, 0x3e00, 0xa200,
+	0x2a00, 0xa803, 0xf03b, 0xe00a, 0x0002, 0x2a00, 0xa805, 0xf02b,
+	0xa912, 0x2a00, 0xa809, 0xf02b, 0xa940, 0x2a00, 0xa811, 0xf02b,
+	0xa980, 0xe0c2, 0x040c, 0xe0c1, 0x0046, 0xe004, 0x0000, 0xae10,
+	0xe042, 0x2a01, 0xa803, 0xf05b, 0xe161, 0x0488, 0x2111, 0x4d11,
+	0xcf0e, 0xe0c1, 0x0046, 0xe004, 0x0040, 0xae10, 0xe042, 0x2a01,
+	0xa805, 0xf05b, 0xe161, 0x048a, 0x2111, 0x4d11, 0xe0c2, 0x0103,
+	0xa200, 0xe0c2, 0x0208, 0xa200, 0xe0c2, 0x021c, 0xa202, 0xe0c2,
+	0x0210, 0xa200, 0xe0c2, 0x0215, 0xe41e, 0x0cff, 0xa203, 0xae09,
+	0xa901, 0xae09, 0xe056, 0xe0c2, 0x0213, 0xe0c1, 0x0046, 0xe004,
+	0x0070, 0xae10, 0xe042, 0x2a01, 0xa809, 0xf05b, 0xe161, 0x048c,
+	0x2111, 0x4d11, 0xe0c2, 0x0211, 0xe0c1, 0x0046, 0xe004, 0x0070,
+	0xe000, 0x0040, 0xae10, 0xe042, 0x2a01, 0xa811, 0xf05b, 0xe161,
+	0x048e, 0x2111, 0x4d11, 0xe0c2, 0x0212, 0xe0c0, 0x0064, 0x3c71,
+	0x2a72, 0xf02b, 0xa200, 0xe0c2, 0x0138, 0x2050, 0x4c51, 0xae08,
+	0xe0c2, 0x0101, 0xe0c2, 0x0205, 0x2a72, 0xaa03, 0x4671, 0xa803,
+	0xf04b, 0x2051, 0x4c50, 0xae08, 0xe0c2, 0x0142, 0xa200, 0xe41e,
+	0x0cff, 0xe0c2, 0x0102, 0x2829, 0xae06, 0xe0c2, 0x0104, 0xa210,
+	0xae08, 0x4c29, 0xae06, 0xe0c2, 0x0204, 0xe0c0, 0x0060, 0xa87e,
+	0xe0c2, 0x0143, 0xe0c0, 0x0069, 0xe0c2, 0x014f, 0xe004, 0x0580,
+	0xe096, 0x2113, 0x4d13, 0xe0c2, 0x021d, 0x2834, 0xe0c2, 0x020b,
+	0xe0c2, 0x0214, 0xa200, 0xe0c2, 0x0312, 0xa202, 0xe0c2, 0x0302,
+	0x2835, 0xe0c2, 0x0380, 0xe0c2, 0x018d, 0x3cdd, 0xa200, 0xe0c2,
+	0x0302, 0x2834, 0xe0c2, 0x0072, 0x3c35, 0xa002, 0x3c34, 0x1832,
+	0xf028, 0x3c34, 0xa200, 0xe0c2, 0x0113, 0xe0c2, 0x030d, 0xe0c2,
+	0x0320, 0xe0c2, 0x030a, 0xe0c2, 0x030b, 0xe004, 0x0055, 0xe0c2,
+	0x030c, 0xe004, 0x003f, 0xe0c2, 0x012a, 0xe166, 0x0600, 0x2116,
+	0x4d16, 0xe0c2, 0x011f, 0x2826, 0xe0c2, 0x0179, 0xe41e, 0x0bb0,
+	0xe004, 0x0582, 0xe096, 0x2313, 0x4f13, 0xe004, 0x0580, 0xe096,
+	0x2113, 0x4d13, 0x3513, 0x3d13, 0xe004, 0x0580, 0xe096, 0x3713,
+	0x3f13, 0xe41e, 0x0cbb, 0xe41e, 0x0ccd, 0xa202, 0xe0c2, 0x0106,
+	0xe0c2, 0x0139, 0xe41e, 0x024d, 0xa204, 0x2a3d, 0xa115, 0xb60a,
+	0x3cd5, 0x2a72, 0xa200, 0xf02b, 0xa208, 0xe0c2, 0x0140, 0x3cd6,
+	0x2a50, 0xa10f, 0xa200, 0xb62e, 0x3cd4, 0xe42e, 0xa2f0, 0x3c53,
+	0xe0c2, 0x003f, 0xe41e, 0x0c44, 0xe41e, 0x0768, 0xa200, 0x3c76,
+	0xa2f2, 0x3c53, 0x2853, 0xe0c2, 0x003f, 0xa00a, 0xf078, 0xe41e,
+	0x0c48, 0xa202, 0xe0c2, 0x021e, 0xf17e, 0xa102, 0xf0a8, 0xe41e,
+	0x0b99, 0xe41e, 0x0c48, 0xe41e, 0x0b92, 0xe41e, 0x0b88, 0xf0ce,
+	0xf094, 0x2839, 0xf048, 0xe41e, 0x0a51, 0xf0ae, 0xe41e, 0x0a49,
+	0xf07e, 0xe41e, 0x0c48, 0xe41e, 0x0c4c, 0xe41e, 0x0c44, 0xa200,
+	0x3ccc, 0x2853, 0xa002, 0x3c53, 0xf564, 0xe42e, 0x2853, 0xe0c2,
+	0x003f, 0xe41e, 0x0750, 0xe419, 0x1094, 0xe41e, 0x0b99, 0x2876,
+	0xf0c8, 0x2863, 0xa002, 0x3c63, 0x1850, 0xf028, 0x3c63, 0x2864,
+	0xe0c2, 0x0120, 0x2876, 0xe428, 0x2853, 0xf104, 0xa106, 0xa80e,
+	0xae06, 0x3cdb, 0xe41e, 0x0b78, 0x2a67, 0xe41e, 0x0b49, 0xe419,
+	0x0c50, 0xe41e, 0x076e, 0xd1f0, 0x000d, 0x2ad4, 0x2853, 0xa80e,
+	0xae06, 0x3cda, 0xf05b, 0x2863, 0xe016, 0x4cd1, 0x3cd1, 0x2a72,
+	0xe0c0, 0x011c, 0xf7ea, 0xf07b, 0xa200, 0x3c00, 0x3c01, 0xe0c2,
+	0x0114, 0xf10e, 0xe0c0, 0x011e, 0x3000, 0x44d5, 0x3c01, 0x4c00,
+	0xe0c2, 0x0114, 0xf07a, 0xe0c0, 0x0170, 0x3c02, 0xe0c0, 0x0174,
+	0x3c03, 0x2ad1, 0xe0c0, 0x0141, 0x3c64, 0xf09b, 0xe41e, 0x0b92,
+	0xa200, 0x3cd1, 0xa203, 0x4ed6, 0xe0c3, 0x0140, 0xe41e, 0x109d,
+	0x2a29, 0xf17b, 0xe0c0, 0x018f, 0x3c04, 0xe0c2, 0x0309, 0x28da,
+	0xe000, 0x02c0, 0xe092, 0xe162, 0x0190, 0xe163, 0x03b0, 0xc420,
+	0xd022, 0x0003, 0xe184, 0x0ab7, 0x9e12, 0x3511, 0x3d11, 0x9f33,
+	0x2a00, 0xe0c0, 0x0111, 0xf7e8, 0x2853, 0xe0c3, 0x0188, 0xf064,
+	0xa210, 0xe0c2, 0x0134, 0xd1d0, 0x0080, 0x2a29, 0x2864, 0xe0c2,
+	0x0119, 0x28d2, 0xe0c2, 0x011a, 0x2862, 0xe0c2, 0x011b, 0xa202,
+	0xe0c2, 0x0110, 0x2a76, 0xf1c9, 0x2115, 0x4d15, 0xcf8c, 0x2115,
+	0x4d15, 0xcf8e, 0x28da, 0xe000, 0x0280, 0xe092, 0x2801, 0x4c00,
+	0x3d11, 0x2802, 0xae10, 0x4c03, 0x3d11, 0x2804, 0x3d11, 0xe0c0,
+	0x0121, 0x3511, 0x3d11, 0xe0c0, 0x0122, 0x3511, 0x3d11, 0xe42e,
+	0xe41e, 0x0c48, 0x2866, 0xf10a, 0x2a52, 0xa80f, 0xf0db, 0xe167,
+	0x05f2, 0x2117, 0x4d17, 0x2a52, 0xa00f, 0xaf07, 0xae07, 0xa103,
+	0xe042, 0xe41e, 0x0cb1, 0x2867, 0xf0ba, 0x2852, 0xa806, 0xa106,
+	0x2a52, 0xa007, 0xaf05, 0xae05, 0xa103, 0xe418, 0x0c7b, 0x2852,
+	0xe0c2, 0x003f, 0xe41e, 0x0c44, 0xe41e, 0x0c48, 0xe190, 0xe0c0,
+	0x0118, 0xa802, 0xf78a, 0xe42e, 0xe0c0, 0x011c, 0xf7ea, 0xe0c0,
+	0x011e, 0xe0c2, 0x0114, 0x3000, 0xa804, 0x3c01, 0x2800, 0xe0c2,
+	0x0188, 0xf09a, 0xe0c0, 0x0170, 0x3c02, 0xe0c0, 0x0174, 0x3c03,
+	0xe0c2, 0x0123, 0xe42e, 0x28da, 0xe000, 0x0280, 0xe092, 0x2801,
+	0x4c00, 0x3d11, 0x2802, 0xae10, 0x4c03, 0x3d11, 0x2804, 0x3d11,
+	0xe0c0, 0x0121, 0x3511, 0x3d11, 0xe0c0, 0x0122, 0x3511, 0x3d11,
+	0xe42e, 0x28db, 0xe000, 0x0280, 0xe09a, 0x2915, 0x3054, 0xaf02,
+	0x3055, 0x2905, 0xaf10, 0x3c56, 0x2915, 0xa81e, 0x3c57, 0x2915,
+	0x3c58, 0xe42e, 0x2115, 0x4d15, 0xcf8c, 0x2115, 0x4d15, 0xcf8e,
+	0xe42e, 0xe0c0, 0x018f, 0x3c04, 0xe0c2, 0x0309, 0x28da, 0xe000,
+	0x02c0, 0xe092, 0xe162, 0x0190, 0xe163, 0x03b0, 0xc420, 0xd022,
+	0x0003, 0xe184, 0x0b76, 0x9e12, 0x3511, 0x3d11, 0x9f33, 0xe42e,
+	0x28db, 0xe000, 0x02c0, 0xe092, 0xe005, 0x0080, 0xd022, 0x0003,
+	0xe184, 0x0b86, 0xcfd5, 0xa011, 0x2111, 0x4d11, 0xcfd6, 0xe42e,
+	0x2864, 0xe0c2, 0x0119, 0x28d2, 0xe0c2, 0x011a, 0x2862, 0xe0c2,
+	0x011b, 0xe42e, 0xa200, 0x3c64, 0xe004, 0x2222, 0x3cd2, 0x3c62,
+	0xe42e, 0x2805, 0x3c59, 0x2a15, 0x4629, 0x282b, 0xe419, 0x0d93,
+	0x3c05, 0x2805, 0x0824, 0xa400, 0xa566, 0xe000, 0x07f0, 0xe09c,
+	0x2906, 0xae0c, 0x4d06, 0xae0c, 0x4c05, 0xe0c2, 0x0115, 0xe42e,
+	0x2829, 0xf09a, 0xe0c0, 0x0414, 0xe418, 0x018c, 0xe0c0, 0x0414,
+	0xe41a, 0x0bf8, 0x28d7, 0x2a50, 0xa113, 0xf071, 0x2a50, 0xa10d,
+	0xf037, 0xa402, 0xf02e, 0xa404, 0xe005, 0x0020, 0xe055, 0xe0c3,
+	0x0180, 0xe004, 0x0582, 0xe096, 0x2113, 0x4d13, 0xe0c2, 0x018c,
+	0x28d8, 0xe0c2, 0x018e, 0x28d9, 0xe0c2, 0x018a, 0xa201, 0x283d,
+	0xa11e, 0xa400, 0xa548, 0x3c03, 0xae04, 0xe000, 0x0740, 0xe09e,
+	0x2917, 0xe0c2, 0x0186, 0x2917, 0xe0c2, 0x0185, 0xe0c2, 0x0184,
+	0x2917, 0xe049, 0xae15, 0xe056, 0xae15, 0xe056, 0xe0c2, 0x0181,
+	0xe0c2, 0x0182, 0x2917, 0xae20, 0x4c75, 0xe0c2, 0x0183, 0xe42e,
+	0xa200, 0xe0c2, 0x0150, 0xe0c0, 0x0151, 0xf7e8, 0xe167, 0x01a0,
+	0x2317, 0x4f17, 0xe0c3, 0x0152, 0x2b17, 0xe009, 0x00ff, 0xae21,
+	0x4f07, 0xe0c3, 0x0153, 0xe0c1, 0x0101, 0xe0c3, 0x015d, 0x2add,
+	0xa53f, 0xa401, 0xae21, 0xe167, 0x01a2, 0x2907, 0xaf10, 0xe008,
+	0x001b, 0xe056, 0xe0c2, 0x015c, 0xa202, 0xe0c2, 0x0150, 0xe0c0,
+	0x0150, 0xf7ea, 0xe42e, 0xe004, 0x3211, 0xae20, 0xe00a, 0x2100,
+	0xe0c2, 0x0155, 0xe004, 0x9211, 0xae20, 0xe00a, 0x2100, 0xe0c2,
+	0x0158, 0xe004, 0x1000, 0xae20, 0xe00a, 0x0000, 0xe0c2, 0x0156,
+	0xe0c2, 0x0159, 0xe004, 0x0004, 0xe0c2, 0x0154, 0xe0c2, 0x0157,
+	0xa202, 0xe0c2, 0x015a, 0xe42e, 0xa202, 0xe0c2, 0x0110, 0xe42e,
+	0xe0c0, 0x0111, 0xf7e8, 0xe42e, 0xe0c0, 0x011c, 0xf7ea, 0xe42e,
+	0x2853, 0xa806, 0xae02, 0xe000, 0x05e0, 0xe09e, 0x28db, 0xe000,
+	0x0280, 0xe092, 0x2b11, 0xe01b, 0xae1f, 0xa200, 0xf0c9, 0x28db,
+	0xe000, 0x02c0, 0xe092, 0x2111, 0x4d11, 0xcfd6, 0xe049, 0xaf21,
+	0xe009, 0x7fff, 0x3f17, 0x3d17, 0x2853, 0xa806, 0xa106, 0x3c08,
+	0xe41a, 0x0c7b, 0x2808, 0xe42a, 0x2852, 0x1853, 0xa102, 0xe428,
+	0xe41e, 0x0c7b, 0xe42e, 0xe167, 0x05f6, 0x2117, 0x4d17, 0x2a53,
+	0xaf05, 0xae09, 0xe042, 0xce20, 0xd112, 0x0008, 0xd111, 0x05e0,
+	0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0x2853, 0xa80e, 0xaf02,
+	0xe000, 0x05e8, 0xe09e, 0xcb94, 0xe008, 0x003f, 0x2a65, 0xae0d,
+	0xe056, 0x2a53, 0xa803, 0xf049, 0xae10, 0x3d07, 0xf06e, 0x2b07,
+	0xe009, 0xff00, 0xe056, 0x3d07, 0x2853, 0xa80e, 0xa10e, 0xe41a,
+	0x0caa, 0xe42e, 0x2853, 0xa10e, 0xe167, 0x05f2, 0x2317, 0x4f17,
+	0xe042, 0xce20, 0xd111, 0x05e8, 0xd112, 0x0004, 0xd113, 0x0002,
+	0xca28, 0xf7f8, 0xe42e, 0x282b, 0xa118, 0xb608, 0xa54e, 0xe000,
+	0x0830, 0xe09c, 0x2906, 0xae04, 0xe0c2, 0x0176, 0xcca4, 0xc786,
+	0xe018, 0xa004, 0xe0c2, 0x0177, 0xe42e, 0x282b, 0xa11e, 0xa400,
+	0xa548, 0xe000, 0x0860, 0xe09c, 0x2906, 0xe0c2, 0x0189, 0xe42e,
+	0x2829, 0xe42a, 0xa202, 0x2a1c, 0xb616, 0xae02, 0x4c1e, 0xae20,
+	0x4c1c, 0xe0c2, 0x0108, 0x20c6, 0x4cc1, 0xe0c2, 0x0109, 0x2052,
+	0x4c1d, 0xe0c2, 0x010a, 0x20c2, 0x4cc3, 0xe0c2, 0x010b, 0x20c4,
+	0x4cc5, 0xe0c2, 0x010c, 0xe42e, 0x2829, 0xe42a, 0xe0c0, 0x010b,
+	0x34c2, 0x3cc3, 0xe0c0, 0x010c, 0x34c4, 0x3cc5, 0xe42e, 0xe0c1,
+	0x0044, 0xa80f, 0xe056, 0xe42e, 0xe0c1, 0x0044, 0xaf0d, 0xae03,
+	0xe056, 0xa87e, 0xe42e, 0xa203, 0xe0c3, 0x040d, 0xe0c1, 0x0420,
+	0xa803, 0xf7db, 0xe166, 0x04c0, 0xe167, 0x0500, 0x2832, 0xf1b6,
+	0xa102, 0xcc44, 0xe184, 0x0d31, 0xa200, 0xe41e, 0x0cff, 0xaf04,
+	0xe41e, 0x0d04, 0xae20, 0x4c70, 0x9f17, 0x2050, 0x4c51, 0xae08,
+	0x9f17, 0x2116, 0x4d16, 0x9f17, 0x2116, 0x4d16, 0x9f17, 0x2116,
+	0x4d16, 0x9f17, 0xa201, 0xe0c3, 0x040d, 0xe42e, 0xe0c0, 0x0044,
+	0xaf20, 0xa802, 0xe428, 0xe0c0, 0x0060, 0xa83e, 0xa203, 0xe0c3,
+	0x040d, 0xcca4, 0xc785, 0xe018, 0xe000, 0x0500, 0xe09e, 0xe0c1,
+	0x0420, 0xa803, 0xf7db, 0xa200, 0xe41e, 0x0cff, 0xaf04, 0xe0c1,
+	0x0061, 0xaf21, 0xa807, 0xa105, 0xf025, 0xe04a, 0xe41e, 0x0d04,
+	0xe0c1, 0x0044, 0xaf17, 0xa803, 0xe40b, 0x0d5f, 0xa81e, 0xae20,
+	0xe0c1, 0x0061, 0xe009, 0x1fff, 0xe056, 0x9f17, 0xe0c0, 0x0064,
+	0xa802, 0xf048, 0x2050, 0x4c51, 0xf03e, 0x2051, 0x4c50, 0xae08,
+	0x9f17, 0xe0c0, 0x006a, 0x9f17, 0xe0c0, 0x006b, 0x9f17, 0xe0c0,
+	0x006c, 0x9f17, 0xa201, 0xe0c3, 0x040d, 0xe42e, 0xcca4, 0xc786,
+	0xe018, 0xe000, 0x04c0, 0xe09c, 0x2116, 0x4d06, 0xe42e, 0xe41e,
+	0x0d9f, 0xe42e, 0xe41e, 0x0e00, 0xe42e, 0xe41e, 0x0e01, 0xe42e,
+	0xe41e, 0x0e4b, 0xe42e, 0xe41e, 0x0e81, 0xe42e, 0xe41e, 0x0ee1,
+	0xe42e, 0xe41e, 0x0fd0, 0xe42e, 0xe41e, 0x102d, 0xe42e, 0xa254,
+	0x3ccd, 0xa268, 0x3c83, 0xa218, 0x3c85, 0xa266, 0x2ac8, 0xf03b,
+	0xe0c0, 0x0072, 0x3c84, 0xa210, 0x3c97, 0xe004, 0x07e0, 0x3c98,
+	0x2814, 0x2a52, 0x3c86, 0x3e8b, 0x2c17, 0xc710, 0x7c18, 0xe008,
+	0xffff, 0xa002, 0xaf02, 0x3c88, 0x3cbb, 0xe004, 0x6000, 0x2ac7,
+	0xf03b, 0xe0c0, 0x0073, 0x3c99, 0x2886, 0xe016, 0x3c87, 0xf06a,
+	0x2888, 0x3c86, 0xe004, 0x1000, 0x3c99, 0x8418, 0xe182, 0x7530,
+	0xe018, 0xae02, 0x2e17, 0xe41e, 0x0f7a, 0x3c9e, 0x849e, 0x827f,
+	0xe018, 0xa279, 0xe41e, 0x0f63, 0x349e, 0x3c9f, 0xae06, 0x2a83,
+	0xe41e, 0x0f63, 0x34a4, 0x3ca5, 0xa202, 0x3c89, 0xa205, 0x1a36,
+	0xae03, 0xa011, 0x3e8e, 0x2a8b, 0x5a8e, 0xe013, 0x36ae, 0x3eaf,
+	0x28b9, 0x2ab8, 0xf049, 0xe41e, 0x0f0a, 0x64cd, 0x3c8c, 0xa004,
+	0x6085, 0x6484, 0x3c8d, 0xa200, 0x3ce7, 0xe41e, 0x0f2e, 0xe42e,
+	0xe42e, 0x2829, 0x3c8a, 0xa201, 0x3e92, 0x3ecc, 0xe418, 0x0eec,
+	0xa200, 0x3c93, 0x3c94, 0x288a, 0xf238, 0x2889, 0xf05a, 0xa200,
+	0x3c89, 0x288c, 0xf37e, 0x2886, 0xa102, 0xf7ca, 0x2ab8, 0xf03b,
+	0x288c, 0xf30e, 0x848b, 0x82b5, 0xe019, 0xe04a, 0xaf02, 0x00a6,
+	0x0ca7, 0xe41e, 0x0f7a, 0xa21f, 0x3e8e, 0x2a86, 0xc70f, 0x7e8e,
+	0xe009, 0xffff, 0xa405, 0xe046, 0x6085, 0x64cd, 0xf1be, 0xa200,
+	0x3ca2, 0x3ca3, 0x2a92, 0xf08b, 0x288d, 0x2ae7, 0xf129, 0xa006,
+	0x2a84, 0xe066, 0xf0ee, 0x28c9, 0x308e, 0xaf02, 0x548e, 0xf08a,
+	0x288d, 0xa104, 0x6090, 0x2a8d, 0xa005, 0xe066, 0xf02e, 0x288d,
+	0x3c90, 0x2a92, 0xe42e, 0xc872, 0xe41e, 0x0f37, 0x288a, 0xf0ea,
+	0x2093, 0x4c94, 0xc710, 0x7c8b, 0xe008, 0xffff, 0xa002, 0xaf02,
+	0x3c8d, 0x2093, 0x4c94, 0x00a6, 0x0ca7, 0x34a6, 0x3ca7, 0x28b5,
+	0xa002, 0x3cb5, 0x288a, 0xf028, 0x3cb5, 0x288a, 0xf0f8, 0x2a86,
+	0xa103, 0x2095, 0x4c96, 0xe41e, 0x0f63, 0x34ac, 0x3cad, 0x1095,
+	0x1c96, 0xe012, 0x34aa, 0x3cab, 0xf0ae, 0x22aa, 0x4eab, 0x12ac,
+	0x1ead, 0x2887, 0xb606, 0xb611, 0x36aa, 0x3eab, 0x2892, 0x3ce7,
+	0xe42e, 0x28c9, 0xf08a, 0x2852, 0x1853, 0xa102, 0xf048, 0x2805,
+	0xe40e, 0x0ed6, 0x22a2, 0x4ea3, 0x20a4, 0x4ca5, 0xe041, 0xf0c7,
+	0xe045, 0xe045, 0x2890, 0xf0f5, 0x36a2, 0x3ea3, 0xa002, 0x6085,
+	0x6484, 0x3c90, 0xf08e, 0x36a2, 0x3ea3, 0x2890, 0xa102, 0x6085,
+	0x6484, 0x3c90, 0x2890, 0x6085, 0x6484, 0x3c90, 0x2ac9, 0x28cc,
+	0xa002, 0x3ccc, 0xf08b, 0xa103, 0xf22b, 0xa103, 0xf07b, 0xa103,
+	0xf0ab, 0xf24e, 0x2890, 0xe40e, 0x0ed6, 0x28cb, 0xf18a, 0xa200,
+	0x3ccb, 0xf06e, 0x28cc, 0x18ca, 0xf124, 0xa200, 0x3ccc, 0x2853,
+	0xa002, 0xf046, 0xcb97, 0xcb96, 0xf03e, 0x2a2b, 0x282b, 0xa105,
+	0x6290, 0xa004, 0xe066, 0x3c90, 0x3c8e, 0xf08e, 0xcb96, 0x3c8e,
+	0x2853, 0xa002, 0xf030, 0x282b, 0x3c8e, 0x288e, 0x2a3d, 0xe045,
+	0xf053, 0x2a3d, 0xa007, 0xe066, 0xe42e, 0x2a3d, 0xa107, 0xe062,
+	0xe42e, 0x0093, 0x0c94, 0x3493, 0x3c94, 0x285f, 0x189a, 0x00a2,
+	0x0ca3, 0x34a2, 0x3ca3, 0xe42e, 0x20aa, 0x4cab, 0x1095, 0x1c96,
+	0x8499, 0xe41e, 0x0fb1, 0x009e, 0x0c9f, 0xf052, 0x2a91, 0xf039,
+	0xa203, 0x3e92, 0xe41e, 0x0f49, 0x229e, 0x4e9f, 0xaf07, 0xe062,
+	0x34a0, 0x3ca1, 0xc710, 0x7c8b, 0xe008, 0xffff, 0xa002, 0xaf02,
+	0x3c9a, 0xe42e, 0x8486, 0x209e, 0x4c9f, 0xe41e, 0x0fa5, 0x8497,
+	0xe41e, 0x0fa5, 0x2a86, 0xa103, 0x0a97, 0xe41e, 0x0f63, 0x34a0,
+	0x3ca1, 0x288b, 0x3cb0, 0x20a0, 0x4ca1, 0xae04, 0x00a0, 0x0ca1,
+	0xae02, 0xc70f, 0x7cb0, 0xe008, 0xffff, 0xaf08, 0xa010, 0xaf08,
+	0x0836, 0xa51e, 0x0898, 0xe09e, 0x2907, 0xe42e, 0x847f, 0x8280,
+	0xe018, 0x34a8, 0x3ca9, 0xa200, 0x3495, 0x3c96, 0xe42e, 0x109e,
+	0x1c9f, 0x0095, 0x0c96, 0xa27f, 0xae31, 0xe066, 0x3495, 0x3c96,
+	0x22ae, 0x4eaf, 0xe046, 0xf032, 0x3695, 0x3e96, 0x2095, 0x2896,
+	0xe42e, 0x2a80, 0xe42b, 0x22a8, 0x4ea9, 0x1295, 0x1e96, 0xe066,
+	0xf051, 0x2a91, 0xf039, 0xa203, 0x3e92, 0x2281, 0x4e82, 0xe42b,
+	0x22a8, 0x4ea9, 0x1295, 0x1e96, 0x029e, 0x0e9f, 0x1281, 0x1e82,
+	0xa401, 0xe062, 0xe42e, 0x3eb0, 0xa201, 0xf032, 0xe012, 0xa203,
+	0x3eb4, 0x3cb1, 0xaf20, 0xc70f, 0x7cb0, 0x3cb2, 0xaf20, 0xae20,
+	0x4cb1, 0xc70f, 0x7cb0, 0x3cb3, 0x20b2, 0x4cb3, 0x2ab4, 0xe42b,
+	0xe012, 0xe42e, 0x36b0, 0x3eb1, 0xa201, 0x3eb2, 0x22b0, 0x4eb1,
+	0x5ab2, 0xe045, 0xf061, 0x2ab2, 0xa003, 0x3eb2, 0xa121, 0xf775,
+	0x2ab2, 0xf039, 0xa200, 0xe42e, 0xa103, 0x3eb2, 0xcc45, 0xa201,
+	0x3eb3, 0xe184, 0x0fa2, 0x2ab3, 0xae03, 0x3eb3, 0x22b0, 0x4eb1,
+	0x5ab2, 0xe045, 0xf061, 0xe013, 0xe04a, 0x2ab3, 0xa003, 0x3eb3,
+	0x2ab2, 0xa103, 0x3eb2, 0x28b3, 0xe42e, 0xae02, 0x34b1, 0xe008,
+	0xffff, 0xaf02, 0x3cb0, 0x82b1, 0xe018, 0xae1e, 0x82b0, 0xe01c,
+	0xe42e, 0xae02, 0x34b1, 0xe008, 0xffff, 0xaf02, 0x3cb0, 0x82b0,
+	0xe018, 0xaf1e, 0x82b1, 0xe01c, 0xe42e, 0xae02, 0x34b1, 0xe008,
+	0xffff, 0xaf02, 0x3cb0, 0x82b1, 0xe018, 0xa103, 0x3eb2, 0x58b2,
+	0x82b0, 0xa11f, 0xe013, 0x3eb2, 0xe019, 0x5eb2, 0xe042, 0xe42e,
+	0x34bd, 0x3cbc, 0x28bd, 0xa002, 0x3cbd, 0x2cbc, 0xc710, 0x7cbd,
+	0xe008, 0xffff, 0xa002, 0xaf02, 0x3c88, 0x18bb, 0xe42a, 0x2888,
+	0x3cbb, 0x28bc, 0x2abd, 0x3c17, 0x3e18, 0x8418, 0xe182, 0x7530,
+	0xe018, 0xae02, 0x2e17, 0xe41e, 0x0f7a, 0x3c9e, 0x849e, 0x827f,
+	0xe018, 0xa279, 0xe41e, 0x0f63, 0x349e, 0x3c9f, 0xae06, 0x2a83,
+	0xe41e, 0x0f63, 0x34a4, 0x3ca5, 0xa200, 0x3cb5, 0x34a6, 0x3ca7,
+	0x2886, 0xe428, 0xe016, 0x3c87, 0x2888, 0x3c86, 0xe42e, 0x3cb7,
+	0x2a86, 0xe046, 0xf028, 0xe42e, 0x28b6, 0x2ab7, 0xe046, 0xf034,
+	0xa200, 0x3cb6, 0x28b7, 0x3c86, 0x3c14, 0x2815, 0xe42a, 0x2886,
+	0xe016, 0x3c87, 0xf03a, 0x2a88, 0x3e86, 0x2a86, 0x28b6, 0xe045,
+	0xf0c6, 0x2095, 0x4c96, 0xe41e, 0x0f63, 0x34ac, 0x3cad, 0x1095,
+	0x1c96, 0xe012, 0x34aa, 0x3cab, 0xe42e, 0x3cba, 0x2815, 0xe42a,
+	0x287f, 0x2aba, 0xe046, 0xe42a, 0x3e7f, 0x8418, 0xe182, 0x7530,
+	0xe018, 0xae02, 0x2e17, 0xe41e, 0x0f7a, 0x3c9e, 0x849e, 0x827f,
+	0xe018, 0xa279, 0xe41e, 0x0f63, 0x349e, 0x3c9f, 0xae06, 0x2a83,
+	0xe41e, 0x0f63, 0x34a4, 0x3ca5, 0xa200, 0x3cb5, 0x34a6, 0x3ca7,
+	0xe42e, 0x2a15, 0xe42b, 0xf042, 0xa201, 0x3eb8, 0xe42e, 0x3cb9,
+	0x3c8c, 0xa203, 0x3eb8, 0xe42e, 0xe0c1, 0x0060, 0xa803, 0xf05b,
+	0xe0c0, 0x0061, 0xe41e, 0x1007, 0xe0c1, 0x0060, 0xa805, 0xf05b,
+	0xe0c0, 0x0062, 0xe41e, 0x1051, 0xe0c1, 0x0060, 0xa809, 0xf05b,
+	0xe0c0, 0x0063, 0xe41e, 0x0d9c, 0xe0c1, 0x0060, 0xa811, 0xf05b,
+	0xe0c0, 0x0064, 0xe41e, 0x0d99, 0xe0c1, 0x0060, 0xa821, 0xf04b,
+	0xe0c0, 0x0065, 0x3c1c, 0xe0c1, 0x0060, 0xa841, 0xf08b, 0xe0c0,
+	0x0066, 0x3038, 0xaf02, 0x3039, 0xaf02, 0x3c3a, 0xe42e, 0xa200,
+	0x3c63, 0x3cd3, 0x3c64, 0xe42e, 0xe161, 0x0200, 0xe004, 0x2222,
+	0xe188, 0x007f, 0x3d11, 0xe190, 0xe42e, 0xf149, 0x2a63, 0x28d3,
+	0xe000, 0x0200, 0xe09c, 0x2906, 0x3c62, 0xf089, 0xe004, 0x2222,
+	0x3cd2, 0xe0c0, 0x0173, 0x3506, 0xf05e, 0xe0c0, 0x0173, 0x3506,
+	0x3cd2, 0x28d3, 0xa002, 0x3cd3, 0xa002, 0x1850, 0xe428, 0x3cd3,
+	0xe42e, 0xa200, 0x3cc2, 0x3cc4, 0x3cc5, 0xe42e, 0xa200, 0x3c1d,
+	0xe42e, 0x281e, 0xf208, 0x281d, 0x181c, 0xf3f2, 0x2853, 0xa006,
+	0x18c2, 0xf3b4, 0x28c2, 0x08c1, 0x18c6, 0xf0b4, 0x28c4, 0xa002,
+	0xc70f, 0x7cc1, 0xaf20, 0x3cc4, 0x3cc2, 0x281c, 0x3c1d, 0xf2be,
+	0x281d, 0xa002, 0x3c1d, 0x28c2, 0x08c1, 0xc70f, 0x7cc6, 0xaf20,
+	0x3cc2, 0xf21e, 0x281d, 0x181c, 0xf202, 0x2853, 0xa006, 0x18c3,
+	0xf1c4, 0x28c3, 0x08c1, 0x1852, 0xf0c4, 0x28c5, 0xa002, 0xc70f,
+	0x7cc1, 0xaf20, 0x3cc5, 0x08c6, 0x3cc3, 0x281c, 0x3c1d, 0xf0be,
+	0x281d, 0xa002, 0x3c1d, 0x28c3, 0x08c1, 0xc70f, 0x7c52, 0xaf20,
+	0x3cc3, 0xf01e, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xa200, 0x3c4d,
+	0xe0c0, 0x0060, 0x344a, 0x3c4b, 0x347c, 0x3c7d, 0xe0c0, 0x0061,
+	0xae04, 0x3c4c, 0xe41e, 0x1127, 0xe42e, 0xd030, 0x0000, 0xd034,
+	0x0000, 0xd033, 0x0000, 0xd035, 0x0000, 0xd036, 0x00ff, 0xd037,
+	0x0080, 0xd038, 0x0000, 0xa200, 0x3c49, 0xe42e, 0xe470, 0x204a,
+	0x4c4b, 0x2e4d, 0xae11, 0xe042, 0xe0c2, 0x0049, 0x347c, 0x3c7d,
+	0xe42e, 0xd071, 0x242a, 0xe181, 0xa200, 0x34df, 0x3ce0, 0xe004,
+	0x0200, 0x3cf3, 0x3cf6, 0xe41e, 0x11ed, 0xe41e, 0x1209, 0xe41e,
+	0x1226, 0xe41e, 0x124a, 0xe41e, 0x1255, 0xe42e, 0xe41e, 0x1171,
+	0xe41e, 0x118d, 0xca48, 0xaf3c, 0xa802, 0xf05a, 0xa202, 0x3cf4,
+	0xae3c, 0xce48, 0xca48, 0xaf38, 0xa802, 0xf0aa, 0xe41e, 0x1160,
+	0xe41e, 0x124a, 0xa202, 0xae38, 0xce48, 0xe41e, 0x1255, 0xe470,
+	0x247c, 0x4c7d, 0x264a, 0x4e4b, 0xe046, 0x2e4c, 0xae11, 0xe045,
+	0xe425, 0x28f3, 0xe045, 0xf043, 0xe041, 0x3ef6, 0xe42e, 0x3cf6,
+	0xe42e, 0xca55, 0x28f6, 0xf048, 0xa200, 0xceaa, 0xf04e, 0x20df,
+	0x4ce0, 0xe045, 0x247c, 0x4c7d, 0xe042, 0x347c, 0x3c7d, 0x28f6,
+	0xe42a, 0x24df, 0x4ce0, 0xe042, 0x34df, 0x3ce0, 0x2af6, 0xe046,
+	0xe428, 0xa200, 0x34df, 0x3ce0, 0xe42e, 0xa200, 0x3c4f, 0x247c,
+	0x4c7d, 0x264a, 0x4e4b, 0xe046, 0xe049, 0xaf10, 0x3c4d, 0x2c4c,
+	0xae10, 0xe045, 0xf275, 0x28bf, 0xf1fa, 0xa202, 0xe0c2, 0x0074,
+	0x247c, 0x4c7d, 0xe0c2, 0x0049, 0x2ace, 0xf16b, 0xe0c0, 0x005c,
+	0xe008, 0x8000, 0xf11a, 0xe0c0, 0x005d, 0xe00a, 0x8000, 0xe0c2,
+	0x005d, 0xa202, 0xce00, 0xe0c1, 0x005d, 0xe009, 0x8000, 0xf7c9,
+	0xe0c0, 0x0004, 0xf798, 0xa200, 0x3c4d, 0x264a, 0x4e4b, 0x367c,
+	0x3e7d, 0x267c, 0x4e7d, 0xe0c3, 0x0049, 0x28bf, 0xe428, 0xd027,
+	0x0000, 0xe41e, 0x11ce, 0xd027, 0x0001, 0xe42e, 0xe0c0, 0x0048,
+	0xe0c1, 0x0049, 0xe046, 0xf040, 0x2e4c, 0xae11, 0xe042, 0xe005,
+	0x0200, 0xe046, 0xe420, 0x284f, 0xf728, 0xe0c0, 0x005c, 0xe008,
+	0x8000, 0xf6da, 0xe0c0, 0x005d, 0xe00a, 0x8000, 0xe0c2, 0x005d,
+	0xa202, 0xce00, 0x3c4f, 0xf63e, 0xe42e, 0xa220, 0xa20d, 0xe056,
+	0xa203, 0xe056, 0xae20, 0xcc9e, 0xd030, 0x0000, 0xd033, 0x0000,
+	0xd034, 0x0000, 0xd035, 0x0000, 0xd036, 0x00ff, 0xd037, 0x0080,
+	0xd038, 0x0000, 0xd039, 0x0000, 0xd046, 0x0000, 0xd047, 0x0000,
+	0xe42e, 0xe0c0, 0x0043, 0xaf0c, 0x30ce, 0xa202, 0xae0e, 0xe0c1,
+	0x0043, 0xa807, 0xae09, 0xe056, 0xce4e, 0xa222, 0xae28, 0xa217,
+	0xae37, 0xe056, 0xce4c, 0xa200, 0xce54, 0xa206, 0xae38, 0xe005,
+	0x0003, 0xe056, 0xce4a, 0xa200, 0xce58, 0xe42e, 0xe0c0, 0x005b,
+	0xa110, 0xf04a, 0xa106, 0xf05a, 0xe42e, 0xe004, 0x0038, 0xf03e,
+	0xe004, 0x0020, 0xe005, 0x0080, 0xe056, 0xe005, 0x1800, 0xe056,
+	0xcec0, 0xa208, 0xcec8, 0xa200, 0xce92, 0xce9e, 0xce88, 0xce8a,
+	0xced0, 0xced6, 0xcea4, 0xcec6, 0xa202, 0xce9c, 0xe004, 0x0200,
+	0xce96, 0xe42e, 0xa206, 0x2af6, 0xae11, 0xe056, 0xce5a, 0x247c,
+	0x4c7d, 0xce5c, 0xa200, 0xce5e, 0xe42e, 0xe004, 0x0f00, 0xae20,
+	0xe005, 0x0003, 0xe056, 0xe005, 0x0030, 0xe056, 0xca49, 0xaf21,
+	0xa803, 0xf04b, 0xa203, 0xae2f, 0xe056, 0xce4a, 0xe42e, 0xc872,
+	0xa050, 0xcc72, 0xa200, 0xe41e, 0x1286, 0xa200, 0xe41e, 0x1286,
+	0xa200, 0xe41e, 0x1286, 0xa202, 0xe41e, 0x1286, 0xa200, 0xce96,
+	0xceaa, 0x282f, 0xae0a, 0x4c30, 0xe41e, 0x1286, 0xe41e, 0x1115,
+	0xa200, 0xce92, 0xe42e, 0xca9b, 0xf7f9, 0xe42e, 0xe41e, 0x1283,
+	0xcec4, 0xe42e, 0xca48, 0xa802, 0xf7e8, 0xca4c, 0xa802, 0xf7ea,
+	0xe42e, 0xe41e, 0x128a, 0xe41e, 0x1283, 0xa200, 0x3cf4, 0xe004,
+	0x0030, 0xce98, 0x28f4, 0xf7fa, 0xe42e, 0xe082, 0x3c4e, 0xe161,
+	0x0180, 0xca80, 0x3511, 0x3d11, 0xca82, 0x3511, 0x3d11, 0xca84,
+	0x3511, 0x3d11, 0xca86, 0x3511, 0x3d11, 0x8b11, 0x0144, 0x8b11,
+	0x0145, 0x8b11, 0x0148, 0x8b11, 0x0149, 0x8b11, 0x014a, 0x8b11,
+	0x014b, 0x8b11, 0x0160, 0x8b11, 0x014e, 0x8b11, 0x014f, 0x8b11,
+	0x0152, 0x8b11, 0x0153, 0x8b11, 0x0155, 0x8b11, 0x0157, 0x8b11,
+	0x0163, 0x8b11, 0x0164, 0x8b11, 0x0165, 0xcacc, 0x3511, 0x3d11,
+	0xcace, 0x3511, 0x3d11, 0x8b11, 0x0168, 0xcad2, 0x3511, 0x3d11,
+	0xcad4, 0x3511, 0x3d11, 0x8b11, 0x016b, 0x8b11, 0x016c, 0x8b11,
+	0x016d, 0x8b11, 0x016e, 0xc860, 0x3511, 0x3d11, 0xc862, 0x3511,
+	0x3d11, 0xc864, 0x3511, 0x3d11, 0x8b11, 0x0033, 0x8b11, 0x0034,
+	0x8b11, 0x0035, 0x8b11, 0x0036, 0x8b11, 0x0037, 0x8b11, 0x0038,
+	0xc872, 0x3511, 0x3d11, 0x8b11, 0x003a, 0xc87a, 0x3511, 0x3d11,
+	0xc87c, 0x3511, 0x3d11, 0xc880, 0x3511, 0x3d11, 0xc882, 0x3511,
+	0x3d11, 0xc884, 0x3511, 0x3d11, 0xc886, 0x3511, 0x3d11, 0xc888,
+	0x3511, 0x3d11, 0xc88a, 0x3511, 0x3d11, 0xc88c, 0x3511, 0x3d11,
+	0xc890, 0x3511, 0x3d11, 0xc892, 0x3511, 0x3d11, 0xc894, 0x3511,
+	0x3d11, 0xc896, 0x3511, 0x3d11, 0xc898, 0x3511, 0x3d11, 0xc89e,
+	0x3511, 0x3d11, 0x284e, 0xe092, 0xe42e, 0xe082, 0x3c4e, 0xe161,
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+	0x0400, 0x0240, 0x0200, 0x0440, 0x0400, 0x0240, 0x0200, 0x0688,
+	0x0400, 0x0240, 0x0200, 0x06d8, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0028, 0x0027, 0x0027, 0x0026, 0x0026, 0x0025, 0x0024, 0x0023,
+	0x0022, 0x0021, 0x0020, 0x001f, 0x001e, 0x001d, 0x001c, 0x001b,
+	0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
+	0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f,
+	0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017,
+	0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001d, 0x001e,
+	0x001f, 0x0020, 0x0020, 0x0021, 0x0022, 0x0022, 0x0023, 0x0023,
+	0x0024, 0x0024, 0x0025, 0x0025, 0x0025, 0x0026, 0x0026, 0x0026,
+	0x0027, 0x0027, 0x0027, 0x0027, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0001, 0x0001, 0x0001, 0x0001, 0x0002, 0x0002, 0x0002, 0x0002,
+	0x0003, 0x0003, 0x0003, 0x0004, 0x0006, 0x0006, 0x0007, 0x0008,
+	0x0009, 0x000c, 0x000f, 0x0011, 0x0014, 0x0017, 0x001c, 0x001f,
+	0x0022, 0x0025, 0x002a, 0x002e, 0x0030, 0x0037, 0x003a, 0x003e,
+	0x0043, 0x0049, 0x0050, 0x0057, 0x005f, 0x0068, 0x0072, 0x007d,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0001, 0x0002, 0x0002, 0x0002, 0x0002, 0x0003, 0x0003, 0x0003,
+	0x0004, 0x0004, 0x0004, 0x0005, 0x0006, 0x0006, 0x0007, 0x0008,
+	0x0009, 0x000a, 0x000b, 0x000d, 0x000e, 0x0010, 0x0012, 0x0014,
+	0x0017, 0x0019, 0x001d, 0x0020, 0x0024, 0x0028, 0x002d, 0x0033,
+	0x0039, 0x0040, 0x0048, 0x0051, 0x005b, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe40e, 0x0020, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x02f9, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe470, 0xe190, 0xe40e, 0x0313, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x003a, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058,
+	0xa200, 0xe0c2, 0x005a, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xa2fe,
+	0x3cee, 0x3cef, 0x3cec, 0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d,
+	0xce00, 0xf33e, 0xe41e, 0x0164, 0xe09e, 0xa202, 0xae3e, 0x9f07,
+	0xe0c0, 0x005c, 0xe0c1, 0x0059, 0x3eed, 0xa203, 0x5aed, 0xe052,
+	0xf08a, 0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00,
+	0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2, 0x0008, 0xf00e,
+	0x28ee, 0xe412, 0x013d, 0xe190, 0xe0c0, 0x005c, 0xe0c1, 0x0059,
+	0x3eed, 0xa203, 0x5aed, 0xe052, 0xf08a, 0xe0c1, 0x005d, 0xe055,
+	0xe0c3, 0x005d, 0xa202, 0xce00, 0xe0c0, 0x004a, 0xf08a, 0xe41e,
+	0x019c, 0xe408, 0x005c, 0xe40e, 0x0058, 0xe190, 0xe0c0, 0x043d,
+	0xa1ee, 0xf7d8, 0xe004, 0x0060, 0xe0c2, 0x0009, 0xa200, 0xe0c2,
+	0x0009, 0xe0c0, 0x000d, 0xf7e8, 0xe41e, 0x00b2, 0xe41e, 0x00e2,
+	0xe41e, 0x012c, 0xd071, 0x242a, 0xe181, 0xe41e, 0x0164, 0xe09e,
+	0xa202, 0x9f07, 0xe0c0, 0x0049, 0xe0c1, 0x005b, 0xa111, 0xf033,
+	0xe0c0, 0x0048, 0xe0c2, 0x0047, 0xe0c0, 0x0059, 0xae02, 0xe000,
+	0x02f9, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a, 0xe008, 0xffff,
+	0x3cee, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11, 0xe056, 0x3cef,
+	0xe40e, 0x0058, 0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2,
+	0x0008, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xe0c0, 0x0059, 0xf7ea,
+	0xa11e, 0xf198, 0xa202, 0xe0c2, 0x0058, 0xe004, 0xca20, 0xae20,
+	0xe005, 0x210a, 0xe056, 0xe0c2, 0x0070, 0xe004, 0x0000, 0xae20,
+	0xe00a, 0x9cea, 0xe0c2, 0x0071, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+	0x0058, 0xf64e, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058, 0xd027,
+	0x0001, 0xe42e, 0xa200, 0xe0c1, 0x005b, 0xf21b, 0xa23c, 0xa103,
+	0xf37b, 0xa24c, 0xa103, 0xf34b, 0xa258, 0xa103, 0xf1db, 0xe004,
+	0x003a, 0xa103, 0xf2db, 0xe004, 0x003f, 0xa103, 0xf29b, 0xe004,
+	0x0045, 0xa103, 0xf25b, 0xa103, 0xf14b, 0xe004, 0x0063, 0xa103,
+	0xf1ab, 0xe004, 0x006a, 0xa107, 0xf1bb, 0xa200, 0xe0c1, 0x005e,
+	0xf17b, 0xa028, 0xf15e, 0xe0c1, 0x005e, 0xf12b, 0xa010, 0xf10e,
+	0xe004, 0x0049, 0xe0c1, 0x005e, 0xf0bb, 0xa010, 0xa103, 0xf08b,
+	0xa010, 0xf06e, 0xe0c1, 0x005e, 0xf03b, 0xe004, 0x0074, 0xae16,
+	0xe0c1, 0x0040, 0xe041, 0xce21, 0xd111, 0x0000, 0xd112, 0x2800,
+	0xd113, 0x000b, 0xe1e1, 0xe42e, 0xe41e, 0x0213, 0xe0c0, 0x0059,
+	0xa102, 0xe42a, 0xe0c0, 0x005b, 0xa810, 0xf058, 0xa206, 0xe41e,
+	0x0153, 0xe42e, 0xe004, 0x0319, 0xe67c, 0xe0c0, 0x005b, 0xa810,
+	0xf058, 0xa204, 0xe41e, 0x0153, 0xe42e, 0xe004, 0x031b, 0xe67c,
+	0xa200, 0xc401, 0xe188, 0x00eb, 0x3d11, 0xe161, 0x00f2, 0xe188,
+	0x0b0d, 0x3d11, 0xe42e, 0x3cec, 0xe0c0, 0x0041, 0xe005, 0x0000,
+	0xae11, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0c00, 0x88ec,
+	0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0059, 0xa106, 0xf048,
+	0xe004, 0x0076, 0xe42e, 0xe0c0, 0x0059, 0xa10c, 0xf038, 0xe004,
+	0x0071, 0xe004, 0x0070, 0xe42e, 0xe0c0, 0x006b, 0xe167, 0x01a0,
+	0x3d07, 0xe0c0, 0x0414, 0xe428, 0xe0c1, 0x0044, 0xa809, 0xae33,
+	0xe0c0, 0x006a, 0xe167, 0x01a0, 0x3517, 0x3d17, 0xe0c0, 0x006b,
+	0xe056, 0x3517, 0x3d07, 0xe42e, 0xe167, 0x01a0, 0x2907, 0xe0c2,
+	0x0151, 0xa204, 0xe0c2, 0x0150, 0xe0c0, 0x0150, 0xa804, 0xf7da,
+	0xa208, 0xe0c2, 0x0150, 0xe42e, 0xe0c0, 0x004a, 0xe42a, 0xe0c0,
+	0x005b, 0xa110, 0xf142, 0xe0c0, 0x0059, 0xa102, 0xe41a, 0x01be,
+	0xe0c0, 0x0059, 0xa106, 0xe41a, 0x01c5, 0xe0c0, 0x0047, 0xe0c2,
+	0x0048, 0xa200, 0xe0c2, 0x004a, 0xa202, 0xe42e, 0xe0c0, 0x0047,
+	0xe0c2, 0x0049, 0xa200, 0xe0c2, 0x004a, 0xe42e, 0xe0c0, 0x004a,
+	0xa802, 0xa220, 0xe0c2, 0x0070, 0xe42e, 0xe0c0, 0x004a, 0xa802,
+	0xa220, 0xe0c2, 0x0076, 0xa200, 0xe0c2, 0x0072, 0xa2fc, 0xe0c2,
+	0x0077, 0xa2fa, 0xe0c2, 0x0071, 0xe42e, 0xe428, 0xa202, 0xe0c2,
+	0x004a, 0xe0c0, 0x0111, 0xf7e8, 0xca28, 0xf7f8, 0xca48, 0xa802,
+	0xf7e8, 0xa208, 0xae14, 0xa102, 0xe190, 0xf7e2, 0xe0c0, 0x041f,
+	0xf7e8, 0xa200, 0xe0c2, 0x041c, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8,
+	0xe004, 0x0078, 0xe0c2, 0x0009, 0xa200, 0xe0c2, 0x0009, 0xe0c0,
+	0x000d, 0xf7e8, 0xe42e, 0xe41e, 0x0213, 0xd160, 0x0620, 0xe004,
+	0x0019, 0xae18, 0xcec0, 0xe42e, 0xe41e, 0x0228, 0xe000, 0x0040,
+	0xce50, 0xa200, 0xd022, 0x00ff, 0xe184, 0x020f, 0xce52, 0xe190,
+	0xe41e, 0x0230, 0xe42e, 0xa204, 0xae22, 0xcc9e, 0xa200, 0xcc72,
+	0xcc8c, 0xcc8e, 0xe004, 0xa810, 0xae20, 0xe00a, 0x9322, 0xce4a,
+	0xd16f, 0x0003, 0xe190, 0xe190, 0xe190, 0xd16f, 0x0000, 0xe42e,
+	0xe004, 0x0030, 0xce50, 0xca50, 0xa802, 0xf7ea, 0xc000, 0xe42e,
+	0xe004, 0x0020, 0xce50, 0xe42e, 0xa200, 0xe0c2, 0x041c, 0xe42e,
+	0xe41e, 0x028d, 0xe42a, 0xe0c0, 0x0061, 0xe008, 0x001f, 0xe00a,
+	0x0100, 0xe0c2, 0x041c, 0xe41e, 0x02c3, 0xe41e, 0x02f4, 0xae12,
+	0xe0c2, 0x041e, 0xe41e, 0x02e7, 0xe42e, 0xe41e, 0x02b1, 0xe42a,
+	0xe0c0, 0x041f, 0xf7e8, 0xe0c0, 0x0210, 0xa804, 0xf118, 0xe0c0,
+	0x0215, 0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0216, 0xf0be, 0xe0c0,
+	0x0213, 0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0214, 0xf03e, 0xe0c0,
+	0x020b, 0xe00a, 0x0100, 0xe0c2, 0x041c, 0xe41e, 0x02c3, 0xe41e,
+	0x02f4, 0xae12, 0xe0c1, 0x0210, 0xa803, 0xae15, 0xe056, 0xe0c1,
+	0x0204, 0xaf0b, 0xa87f, 0xae07, 0xe056, 0xe0c1, 0x0204, 0xa80f,
+	0xe056, 0xe0c2, 0x041e, 0xe41e, 0x02e7, 0xe42e, 0xe0c0, 0x041f,
+	0xf7e8, 0xa200, 0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xa203,
+	0xae19, 0xe052, 0xf1da, 0xe0c0, 0x0060, 0xaf08, 0xa806, 0xf18a,
+	0xe0c0, 0x0060, 0xa81e, 0xe016, 0xe0c1, 0x0060, 0xa821, 0xe017,
+	0xe056, 0xf0ea, 0xe0c0, 0x0044, 0xaf12, 0xa806, 0xe016, 0xe0c1,
+	0x0044, 0xaf17, 0xa803, 0xe056, 0xf03a, 0xa202, 0xe42e, 0xa200,
+	0xe42e, 0xe0c0, 0x0044, 0xa203, 0xae19, 0xe052, 0xf0ba, 0xe41e,
+	0x028d, 0xf088, 0xe0c0, 0x0044, 0xaf12, 0xa806, 0xf038, 0xa202,
+	0xe42e, 0xa200, 0xe42e, 0xe0c0, 0x041c, 0xe008, 0x00ff, 0xcca4,
+	0xc785, 0xe018, 0xe000, 0x0500, 0xa002, 0xae04, 0xe0c2, 0x041a,
+	0xa202, 0xe0c2, 0x0418, 0xe0c0, 0x0419, 0xf7ea, 0xe0c0, 0x041b,
+	0xaf20, 0xa01e, 0xaf08, 0xae28, 0xe0c1, 0x041b, 0xe009, 0xffff,
+	0xa01f, 0xaf09, 0xae09, 0xe056, 0xe0c2, 0x041d, 0xe42e, 0xe0c0,
+	0x041c, 0xe00a, 0x0200, 0xe0c2, 0x041c, 0xe0c0, 0x041c, 0xe00c,
+	0x0200, 0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xaf04, 0xa802,
+	0xe42e, 0xe40e, 0x1424, 0xe40e, 0x031d, 0xe40e, 0x0321, 0xe40e,
+	0x0325, 0xe40e, 0x032d, 0xe40e, 0x0331, 0xe40e, 0x0335, 0xe40e,
+	0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x0339, 0xe40e, 0x00a4, 0xe40e,
+	0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x00a4, 0xe40e,
+	0x00a4, 0xe40e, 0x0704, 0xe40e, 0x0715, 0xe41e, 0x03b2, 0xe40e,
+	0x00a4, 0xe41e, 0x03d0, 0xe40e, 0x00a4, 0xe41e, 0x0234, 0xe41e,
+	0x03dc, 0xe41e, 0x0286, 0xe40e, 0x00a4, 0xe41e, 0x0488, 0xe40e,
+	0x00a4, 0xe41e, 0x04b5, 0xe40e, 0x00a4, 0xe41e, 0x069e, 0xe40e,
+	0x00a4, 0xe41e, 0x06ca, 0xe40e, 0x00a4, 0x3cec, 0xe0c0, 0x0041,
+	0xe005, 0x0018, 0xae11, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112,
+	0x0100, 0x88ec, 0x0113, 0xca28, 0xf7f8, 0xe42e, 0x8917, 0x0034,
+	0x8917, 0x0033, 0x8917, 0x0035, 0x8917, 0x0036, 0x8917, 0x0037,
+	0x8917, 0x0038, 0x8117, 0x8117, 0x2117, 0x4d17, 0xcc60, 0x2117,
+	0x4d17, 0xcc62, 0x2117, 0x4d17, 0xcc64, 0x2117, 0x4d17, 0xcc72,
+	0xe42e, 0x2117, 0x4d17, 0xcc72, 0x2117, 0x4d17, 0xcc8c, 0x2917,
+	0xcc90, 0x2917, 0x28f4, 0xcc8e, 0x2917, 0x28f5, 0xcc92, 0x2917,
+	0xcc96, 0x2917, 0xcc98, 0x2117, 0x4d17, 0xcc9e, 0xe42e, 0x8b17,
+	0x0034, 0x8b17, 0x0033, 0x8b17, 0x0035, 0x8b17, 0x0036, 0x8b17,
+	0x0037, 0x8b17, 0x0038, 0x8117, 0x8117, 0xc860, 0x3517, 0x3d17,
+	0xc862, 0x3517, 0x3d17, 0xc864, 0x3517, 0x3d17, 0xc872, 0x3517,
+	0x3d17, 0xe42e, 0xc872, 0x3517, 0x3d17, 0xc88c, 0x3517, 0x3d17,
+	0xc890, 0x3d17, 0xc88e, 0x3d17, 0xca9e, 0x3d17, 0xc896, 0x3d17,
+	0xc898, 0x3d17, 0xe005, 0x1415, 0xae21, 0xc89e, 0xe056, 0x3517,
+	0x3d17, 0xe42e, 0xd130, 0x000b, 0xe41e, 0x0148, 0xe41e, 0x0213,
+	0xe41e, 0x04e6, 0xe41e, 0x068b, 0xe41e, 0x04e9, 0xf0ea, 0xe41e,
+	0x0d78, 0xe41e, 0x13d5, 0x283f, 0xe418, 0x10b0, 0xe41e, 0x1354,
+	0xa202, 0xe0c2, 0x0070, 0xe42e, 0xa200, 0xe0c2, 0x0070, 0xe42e,
+	0x28b5, 0xe428, 0x28b6, 0xf06a, 0xa200, 0x3c13, 0xe41e, 0x1533,
+	0xe42e, 0xe41e, 0x14d6, 0xe42e, 0xa202, 0xce02, 0xa240, 0xa102,
+	0xf7f8, 0xa200, 0xcc4a, 0xcc4c, 0x3cf9, 0x3cfa, 0xe0c2, 0x003f,
+	0xe0c2, 0x0074, 0x3c7c, 0xe41e, 0x1034, 0xe41e, 0x105f, 0x28b6,
+	0xf0fa, 0x28b7, 0xf09a, 0xe0c0, 0x0066, 0x3410, 0x3c11, 0xe0c0,
+	0x0067, 0xae04, 0x3c12, 0xa200, 0x3c13, 0xe41e, 0x1533, 0xd130,
+	0x000b, 0xd1b3, 0x0001, 0xd03a, 0x0003, 0xd04b, 0x0001, 0xd04c,
+	0x0000, 0xd008, 0x0000, 0xe41e, 0x0628, 0xe41e, 0x1359, 0x282c,
+	0xf05a, 0x28c5, 0xa002, 0xa802, 0x3cc5, 0xe41e, 0x0dbc, 0x283b,
+	0xf038, 0x2854, 0xcc72, 0x2830, 0xe41a, 0x0b80, 0x2830, 0xe418,
+	0x0be7, 0xe41e, 0x0724, 0x283f, 0xe418, 0x11de, 0x2e20, 0x2c2b,
+	0x0821, 0xe045, 0xb60e, 0x3c2b, 0x28b6, 0xf06a, 0xe41e, 0x14d6,
+	0xe41e, 0x13e7, 0xf05e, 0x28b5, 0xf03a, 0xe41e, 0x1500, 0x2c3b,
+	0xa002, 0x3c3b, 0xe0c2, 0x0070, 0xe002, 0x00f3, 0xf028, 0x283b,
+	0x2824, 0xe0c2, 0x0071, 0x282f, 0xe0c2, 0x0073, 0xd039, 0x0000,
+	0xa200, 0x3cd4, 0x3cd5, 0xc84a, 0xc84d, 0xae20, 0xe056, 0xe0c2,
+	0x0053, 0xe0c0, 0x0065, 0xaf06, 0xa80e, 0xe418, 0x0462, 0x287c,
+	0xf058, 0xa202, 0xe0c2, 0x0076, 0xe42e, 0xa208, 0xe0c2, 0x0076,
+	0xe42e, 0xe42e, 0xe162, 0x05c0, 0xc410, 0x28f2, 0xae10, 0x3d12,
+	0x2852, 0x3d12, 0x8132, 0x28f3, 0xae12, 0x4c2c, 0x3d12, 0x2852,
+	0xae04, 0x3d12, 0x8132, 0x28f4, 0xae14, 0x4c2f, 0x3d12, 0x282f,
+	0xae06, 0x3d12, 0xe180, 0xe0c0, 0x0068, 0xce20, 0xd112, 0x000c,
+	0xd111, 0x05c0, 0xd113, 0x0002, 0xca28, 0xf7f8, 0xe181, 0xe42e,
+	0xe41e, 0x0db0, 0xe41e, 0x0174, 0xe0c0, 0x0042, 0xce20, 0xd111,
+	0x0600, 0xd112, 0x00c0, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe0c0,
+	0x0060, 0x3c3c, 0xe0c0, 0x0061, 0x3c70, 0xe004, 0x0700, 0xe096,
+	0xe0c0, 0x0062, 0x3513, 0x3d13, 0xe0c0, 0x0063, 0x3513, 0x3d13,
+	0xe167, 0x0704, 0xe0c0, 0x006c, 0x3517, 0x3d17, 0xe0c0, 0x006d,
+	0x3517, 0x3d17, 0xe41e, 0x1034, 0xe42e, 0x2830, 0xe428, 0x28b6,
+	0xf0fa, 0x28b7, 0xf09a, 0xe0c0, 0x0061, 0x3410, 0x3c11, 0xe0c0,
+	0x0062, 0xae04, 0x3c12, 0xa200, 0x3c13, 0xe41e, 0x1533, 0xe0c0,
+	0x0060, 0xf06a, 0xa102, 0xf09a, 0xa102, 0xf0aa, 0xe42e, 0xe41e,
+	0x0b08, 0xe41e, 0x0b0d, 0xf07e, 0xe41e, 0x0b51, 0xf04e, 0xe41e,
+	0x0b72, 0xf01e, 0x28b6, 0xf06a, 0xe41e, 0x14d6, 0xe41e, 0x13e7,
+	0xe42e, 0x28b5, 0xe42a, 0xe41e, 0x1500, 0xe42e, 0xa200, 0xcc72,
+	0xe42e, 0xe0c0, 0x0074, 0xa806, 0x3cd9, 0xe0c0, 0x0074, 0xaf04,
+	0x3cda, 0xe0c0, 0x0064, 0x347a, 0x3c7b, 0x3c71, 0xe0c0, 0x0065,
+	0x3421, 0x3c20, 0x2821, 0xa002, 0x3c21, 0x2c20, 0xc710, 0x7c21,
+	0xe008, 0xffff, 0xa002, 0xaf02, 0x3c3d, 0xe0c0, 0x0062, 0xaf06,
+	0x303e, 0xaf04, 0x30bb, 0xe0c1, 0x0071, 0x3ebc, 0xaf02, 0x30ca,
+	0xaf02, 0x30cb, 0xe0c0, 0x0075, 0xe166, 0x0510, 0x3516, 0x3d16,
+	0x287a, 0xa01e, 0xaf08, 0x3c50, 0x287b, 0xa01e, 0xaf08, 0x3c51,
+	0xe0c0, 0x0063, 0xaf06, 0x3030, 0xf1d8, 0xa200, 0x3c34, 0x3c35,
+	0x3c36, 0x3c37, 0x3c6b, 0xe0c0, 0x0066, 0x3022, 0xaf02, 0x3023,
+	0x2a23, 0x4622, 0x3e23, 0xaf02, 0xa80e, 0x3c46, 0xe0c0, 0x0066,
+	0xaf0a, 0x3048, 0xaf02, 0x30c9, 0x2823, 0x4422, 0x3c23, 0xe40e,
+	0x05bc, 0xe0c0, 0x0067, 0x3c55, 0x3037, 0xaf02, 0x3036, 0xaf02,
+	0x3035, 0xaf02, 0x3034, 0xaf02, 0x306b, 0x2834, 0xe408, 0x0624,
+	0x283d, 0xa11e, 0xe404, 0x0624, 0xe167, 0x0204, 0xc420, 0xa202,
+	0x3c47, 0x2850, 0xae08, 0x1937, 0xe40a, 0x0594, 0x2847, 0xa002,
+	0x3c47, 0xa10a, 0xe408, 0x0559, 0xa202, 0x3c55, 0xa20c, 0x3c47,
+	0x287b, 0xe002, 0x0190, 0xf086, 0xe002, 0x0190, 0xf0b6, 0xe002,
+	0x0160, 0xf116, 0xf19e, 0x2850, 0x3c32, 0x2851, 0x3c31, 0xe40e,
+	0x05aa, 0x2850, 0xae02, 0x3c32, 0x2851, 0xa002, 0xaf02, 0x3c31,
+	0xe40e, 0x05aa, 0x2850, 0xae04, 0x3c32, 0x2851, 0xa006, 0xaf04,
+	0x3c31, 0xe40e, 0x05aa, 0x2850, 0xae06, 0x3c32, 0x2851, 0xa00e,
+	0xaf06, 0x3c31, 0xe40e, 0x05aa, 0x812f, 0x8117, 0x2851, 0xae08,
+	0x1907, 0xe408, 0x055e, 0x2847, 0xae04, 0xe000, 0x0200, 0xe09e,
+	0x2917, 0xaf08, 0x3c50, 0x2917, 0xaf08, 0x3c51, 0x2917, 0x3c32,
+	0x2907, 0x3c31, 0xa200, 0x2a20, 0xe003, 0x7530, 0xb632, 0x2a21,
+	0xe003, 0x03e9, 0xb632, 0x3c38, 0xf08a, 0x2855, 0xf068, 0x2821,
+	0xa102, 0xe408, 0x0624, 0x3c38, 0xe0c0, 0x0069, 0x3008, 0xaf02,
+	0x3009, 0xaf02, 0x3c0a, 0xe0c0, 0x006a, 0x3c40, 0xe0c0, 0x006b,
+	0x303f, 0x3481, 0xaf02, 0xe008, 0x7fff, 0x3c80, 0xf028, 0x3c3f,
+	0x2881, 0xaf1e, 0x30ac, 0x2881, 0xe008, 0x7fff, 0x3c81, 0xe0c0,
+	0x006c, 0x3482, 0x3c83, 0xe0c0, 0x006d, 0x3c41, 0x8450, 0x8251,
+	0xe018, 0x3c52, 0xa201, 0xe002, 0x00c8, 0xb425, 0xe002, 0x0190,
+	0xb425, 0x3e44, 0xa202, 0x30b5, 0xe0c0, 0x0043, 0xaf06, 0xaf02,
+	0x30b6, 0xaf02, 0x30b7, 0xaf02, 0x30de, 0x2850, 0x2a51, 0xaf06,
+	0xaf07, 0x3c06, 0x3e07, 0x8406, 0x8207, 0xe018, 0x3cc6, 0xa104,
+	0xf032, 0xa204, 0x3cc6, 0x2851, 0xaf02, 0x3c06, 0x8406, 0x8250,
+	0xe018, 0x3cc2, 0x3cc7, 0xa202, 0x3cc5, 0xe0c0, 0x0076, 0xe049,
+	0xa807, 0x3e0d, 0xaf04, 0x300e, 0xaf02, 0xa81e, 0x3c0f, 0xa20e,
+	0x2a0e, 0xb612, 0xa200, 0x3c0e, 0x280f, 0xb7f4, 0xa81e, 0x3c0f,
+	0xa202, 0xe0c2, 0x0070, 0xe42e, 0xa200, 0xe0c2, 0x0070, 0xe42e,
+	0xa200, 0x3c1f, 0xe0c0, 0x0065, 0xa804, 0xf03a, 0xa200, 0x3c3b,
+	0x28b9, 0x1840, 0xe01a, 0x2ab9, 0xe01b, 0xe052, 0xe016, 0x2a40,
+	0xe01b, 0xe052, 0x2a40, 0x4e3b, 0xe017, 0xe056, 0xa203, 0xb611,
+	0x3e24, 0x3e2c, 0xa202, 0xf02b, 0x08b9, 0x3cb9, 0xe0c0, 0x0065,
+	0xa802, 0xe418, 0x065e, 0xe0c0, 0x0063, 0x3c27, 0xa208, 0x180d,
+	0x2a30, 0xb632, 0x3c28, 0x283f, 0xe42a, 0x282c, 0xe41a, 0x1199,
+	0xe41e, 0x119a, 0x3c27, 0xe419, 0x065e, 0xe42e, 0xa202, 0x3c24,
+	0x3c2c, 0x3c1f, 0xe0c0, 0x0060, 0xaf20, 0xae20, 0x4c3a, 0xe0c2,
+	0x0060, 0xe42e, 0xe167, 0x05d0, 0xa201, 0x3f17, 0x2aea, 0xe045,
+	0x3f17, 0xc872, 0x22f9, 0x4efa, 0xe046, 0x3517, 0x3d17, 0xc872,
+	0x34f9, 0x3cfa, 0x282f, 0xae06, 0xe167, 0x05ca, 0x2317, 0x4f17,
+	0xe042, 0xce20, 0xd111, 0x05d0, 0xd112, 0x0004, 0xd113, 0x0002,
+	0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0040, 0xe005, 0x006a, 0xae17,
+	0xe042, 0xe005, 0x1600, 0xae03, 0xe042, 0xce20, 0xd111, 0x0200,
+	0xd112, 0x018c, 0xd113, 0x0003, 0xe1e1, 0xe42e, 0xe0c0, 0x0060,
+	0xf06a, 0xa102, 0xf09a, 0xa102, 0xf0aa, 0xe42e, 0xe41e, 0x0b08,
+	0xe41e, 0x0b0d, 0xf06e, 0xe41e, 0x0b51, 0xf03e, 0xe41e, 0x0b72,
+	0xc868, 0xaf06, 0xc867, 0xe003, 0x0080, 0xae05, 0xe042, 0x3c06,
+	0xe0c2, 0x0070, 0xc86e, 0xd037, 0x00c0, 0xbad7, 0xcc6e, 0xe0c0,
+	0x0042, 0xce20, 0xd111, 0x0100, 0xd112, 0x0080, 0xd113, 0x0012,
+	0xe1e1, 0xe42e, 0xe0c1, 0x0060, 0xa803, 0xf05b, 0xe0c0, 0x0061,
+	0xe41e, 0x1142, 0xe0c1, 0x0060, 0xa805, 0xf05b, 0xe0c0, 0x0062,
+	0xe41e, 0x118e, 0xe0c1, 0x0060, 0xa809, 0xf05b, 0xe0c0, 0x0063,
+	0xe41e, 0x1168, 0xe0c1, 0x0060, 0xa811, 0xf05b, 0xe0c0, 0x0064,
+	0xe41e, 0x1109, 0xe0c1, 0x0060, 0xa821, 0xf04b, 0xe0c0, 0x0065,
+	0x3c41, 0xe0c1, 0x0060, 0xa841, 0xf08b, 0xe0c0, 0x0066, 0x3008,
+	0xaf02, 0x3009, 0xaf02, 0x3c0a, 0xe0c1, 0x0060, 0xa881, 0xf04b,
+	0xe0c0, 0x0067, 0x3c48, 0xe42e, 0xa206, 0xe41e, 0x0153, 0xe41e,
+	0x0213, 0xa226, 0xe41e, 0x033d, 0xe167, 0x0160, 0xe41e, 0x034e,
+	0xe167, 0x0170, 0xe41e, 0x0369, 0xe42e, 0xa224, 0xe41e, 0x033d,
+	0xe167, 0x0160, 0xe41e, 0x037f, 0xe167, 0x0170, 0xe41e, 0x039a,
+	0xa204, 0xe41e, 0x0153, 0xe42e, 0x2827, 0x3c62, 0xa200, 0x3cd3,
+	0x3ce2, 0x3ce3, 0x3ce4, 0x3ce5, 0x3ce6, 0x3ce7, 0x3c54, 0x3c53,
+	0x3cf7, 0x3cf8, 0x3cf5, 0x3cea, 0x3ce8, 0x3ce9, 0x3c01, 0x3c02,
+	0x3c03, 0x3c2f, 0xcf64, 0xcf62, 0xe0c2, 0x0113, 0xe0c2, 0x030d,
+	0xa202, 0xe0c2, 0x0130, 0xa2fe, 0x2a22, 0xb616, 0x3c16, 0xe004,
+	0x0055, 0xe0c2, 0x030c, 0x2836, 0xe016, 0x4430, 0xe408, 0x07c8,
+	0xa223, 0x2824, 0xe40a, 0x0756, 0x2a28, 0xa021, 0x3e61, 0xa200,
+	0x3c0b, 0xcc70, 0xa202, 0x3c0c, 0x2822, 0xe418, 0x0cd9, 0xa202,
+	0xe0c2, 0x0110, 0x280b, 0xa802, 0xf03a, 0xa202, 0x3cdb, 0xe41e,
+	0x0a3e, 0xe408, 0x07ba, 0x2802, 0xf1ea, 0x280b, 0xa802, 0xe418,
+	0x0863, 0x2858, 0x2a62, 0x1a26, 0xb606, 0x3c5f, 0xcf26, 0xe41e,
+	0x088d, 0x2824, 0xe418, 0x0ac7, 0x2858, 0xae04, 0x4c59, 0xcf02,
+	0x2835, 0xf06a, 0x2859, 0xe016, 0xae0a, 0x4c5d, 0xcf6a, 0xa202,
+	0xe0c2, 0x021e, 0xe41e, 0x0828, 0x283f, 0xe016, 0x4c22, 0xf038,
+	0x8a6e, 0x0039, 0x2802, 0xe418, 0x0895, 0x285d, 0x2ace, 0x3c62,
+	0x3e63, 0x283f, 0x2a22, 0xf18a, 0xc872, 0xf0ab, 0xc870, 0xc440,
+	0xa217, 0xe001, 0x046a, 0xe095, 0x0932, 0x0902, 0x3c06, 0x1c6e,
+	0xe008, 0xffff, 0x3c6f, 0x2a22, 0x2806, 0xf02b, 0x3c6e, 0x285d,
+	0x2a02, 0xe419, 0x1278, 0xe41e, 0x139f, 0x20e8, 0x4ce9, 0xcf62,
+	0xe40e, 0x0762, 0x2822, 0xe418, 0x0ceb, 0xa202, 0xe41e, 0x0886,
+	0x2836, 0xf048, 0xe41e, 0x0c70, 0xe42e, 0xe41e, 0x0c7a, 0xe42e,
+	0xa202, 0xe0c2, 0x0110, 0xa200, 0x3c4a, 0xf0fe, 0xa202, 0x3cdb,
+	0x2808, 0xf0ba, 0xbacf, 0xbae0, 0x284a, 0xba88, 0xbac1, 0x285d,
+	0x3c27, 0xba88, 0xd1b3, 0x0002, 0xa200, 0x3c49, 0xe41e, 0x0a3e,
+	0xe408, 0x0825, 0x8a6e, 0x0039, 0x2802, 0xf1ca, 0x2858, 0x2a62,
+	0x1a26, 0xb606, 0x3c5f, 0xcf26, 0xe41e, 0x088d, 0x2824, 0xe418,
+	0x0ac7, 0x2858, 0xae04, 0x4c59, 0xcf02, 0x2835, 0xf06a, 0x2859,
+	0xe016, 0xae0a, 0x4c5d, 0xcf6a, 0xa202, 0xe0c2, 0x021e, 0xe41e,
+	0x08ca, 0x285d, 0x2ace, 0x3c62, 0x3e63, 0xc872, 0x1c6e, 0xe008,
+	0xffff, 0x3c6f, 0x2a3f, 0x4602, 0x285d, 0xe419, 0x1278, 0xe41e,
+	0x139f, 0x20e8, 0x4ce9, 0xcf62, 0x2802, 0xe40a, 0x07de, 0x2849,
+	0xa002, 0x3c49, 0x1832, 0xe408, 0x07de, 0x284a, 0xa002, 0x3c4a,
+	0x1831, 0xe408, 0x07ce, 0xe40e, 0x07de, 0xe41e, 0x0c7a, 0xe42e,
+	0x2808, 0x2a09, 0xe42a, 0x2822, 0xf239, 0x2a02, 0xe42b, 0xf0d8,
+	0x2a0b, 0xaf03, 0x3e0b, 0xe429, 0xc870, 0x1c0a, 0xe424, 0xa210,
+	0x3c0b, 0xa202, 0x3c66, 0xe42e, 0x2a0b, 0xaf03, 0x3e0b, 0xe429,
+	0xc870, 0xc440, 0xa217, 0xe001, 0x046a, 0xe095, 0x0932, 0x0902,
+	0x1c0a, 0xe424, 0xa210, 0x3c0b, 0xa202, 0x3c66, 0xe42e, 0x2a54,
+	0xe42b, 0x280c, 0x180a, 0x2a0c, 0xa003, 0x3e0c, 0x2a0b, 0xaf03,
+	0x3e0b, 0xe428, 0xa202, 0x3c0c, 0x280b, 0xa940, 0x3c0b, 0x2866,
+	0xa908, 0x3c66, 0xe42e, 0x28f5, 0xe016, 0x3cf5, 0x2822, 0xe418,
+	0x0ceb, 0xa200, 0xe41e, 0x0886, 0x2822, 0xe418, 0x0cd9, 0x2809,
+	0xf038, 0xd038, 0x0000, 0x2862, 0x3c27, 0xe41e, 0x0bb4, 0x283f,
+	0x4422, 0xf0aa, 0xc870, 0xc440, 0xa217, 0xe001, 0x046a, 0xe095,
+	0x0932, 0x0902, 0x3c6e, 0xd1b3, 0x0002, 0xe42e, 0x2af4, 0xe419,
+	0x066a, 0x282f, 0xa002, 0x3c2f, 0xe42e, 0xd190, 0x0002, 0xcb20,
+	0xa804, 0xf7e8, 0xcb04, 0x3c5e, 0xe42e, 0x28ea, 0xe0c2, 0x003f,
+	0x2a36, 0x2822, 0xe409, 0x08ca, 0x2a24, 0xe40a, 0x08a3, 0xe40b,
+	0x0983, 0xe40e, 0x09ae, 0x2859, 0x7024, 0xe428, 0x285b, 0xae02,
+	0x4c5a, 0xae02, 0x4c58, 0x3c4f, 0xa200, 0x0824, 0x3c00, 0x285e,
+	0xa806, 0xae06, 0x4c4f, 0x6c00, 0x285c, 0x7058, 0xa20a, 0x1858,
+	0x3c00, 0x285e, 0xaf04, 0x6c00, 0x285a, 0xe418, 0x09e0, 0x2858,
+	0xe41a, 0x09ff, 0x8877, 0x0194, 0xd190, 0x0001, 0xcb20, 0xa802,
+	0xf7e8, 0xe42e, 0x2859, 0x7024, 0xe428, 0x285b, 0xae02, 0x4c5a,
+	0xae02, 0x4c58, 0x3c4f, 0xa200, 0x0824, 0x0824, 0x0824, 0x3c00,
+	0x285e, 0xa806, 0xae06, 0x4c4f, 0x6c00, 0xa20a, 0x1858, 0x3c00,
+	0x285e, 0xaf04, 0x6c00, 0x285a, 0xe418, 0x09e5, 0x2858, 0xe41a,
+	0x09f1, 0xcb3e, 0xe016, 0xa802, 0x4437, 0xe418, 0x0a29, 0xa201,
+	0xe0c3, 0x0134, 0xf098, 0x8877, 0x0194, 0xd190, 0x0001, 0xcb20,
+	0xa802, 0xf7e8, 0xe42e, 0xa20c, 0x3c4d, 0x2a4d, 0xe427, 0xa103,
+	0x3e4d, 0x285f, 0xe418, 0x090a, 0x285e, 0x5c4d, 0xa802, 0xe418,
+	0x0919, 0xf74e, 0xa20a, 0xe046, 0xae0c, 0xcf3a, 0xcf3c, 0xcb38,
+	0xe005, 0x00fe, 0xe066, 0xe049, 0xe003, 0x0080, 0xb7f6, 0xba8e,
+	0xe42e, 0xe41e, 0x091e, 0xe41e, 0x094e, 0xe42e, 0x2877, 0x5c4d,
+	0x5c4d, 0xa806, 0xe005, 0x02ac, 0xf07a, 0xe005, 0x02ec, 0xa106,
+	0xf03a, 0xe005, 0x032c, 0xe09f, 0x8117, 0xe165, 0x0482, 0xe166,
+	0x04c2, 0xa27c, 0xcc44, 0xa20a, 0x2a4d, 0xe046, 0xae0c, 0x3c06,
+	0xa200, 0xa201, 0x3cd6, 0xe184, 0x094c, 0x2806, 0x4d17, 0xcf3a,
+	0xcf3c, 0xcb38, 0xe008, 0x0fff, 0xb435, 0xf07a, 0x3f15, 0x3d16,
+	0xa201, 0x28d6, 0xa002, 0x3cd6, 0xe190, 0xe42e, 0xe165, 0x0482,
+	0xe166, 0x04c2, 0x28d6, 0xa104, 0xcc44, 0xe184, 0x095c, 0x2915,
+	0xae18, 0x4d16, 0xb914, 0xe41d, 0x0966, 0xa202, 0xae0c, 0x4d15,
+	0xae18, 0x4d16, 0xb914, 0xe41d, 0x0966, 0xe42e, 0xe16a, 0x810e,
+	0xa207, 0xba8d, 0xaf18, 0xba8c, 0x2906, 0xae30, 0xaf30, 0xe049,
+	0xe002, 0x007f, 0xe001, 0x007f, 0xf050, 0xf045, 0x2916, 0xba8e,
+	0xe42e, 0xe004, 0x0080, 0xba8e, 0x2906, 0xa83e, 0xba88, 0x2916,
+	0xaf0a, 0xba8a, 0xe42e, 0x285b, 0xae02, 0x4c5a, 0xae02, 0x4c58,
+	0x3c4f, 0x285e, 0xa806, 0xae06, 0x4c4f, 0xb900, 0x285a, 0xe418,
+	0x09e0, 0x285f, 0xf06a, 0xd190, 0x0001, 0xcb20, 0xa802, 0xf7e8,
+	0xa203, 0xe41e, 0x0ca7, 0x285c, 0xba80, 0x285e, 0xaf04, 0xb908,
+	0xa205, 0xe41e, 0x0ca7, 0x8877, 0x0194, 0xd190, 0x0004, 0xcb20,
+	0xa808, 0xf7e8, 0xa201, 0xe41e, 0x0ca7, 0xe42e, 0x2859, 0xba80,
+	0xe428, 0x285b, 0xae02, 0x4c5a, 0xae02, 0x4c58, 0x3c4f, 0x285e,
+	0xa806, 0xae06, 0x4c4f, 0xb902, 0x2858, 0xe41a, 0x09ff, 0xa203,
+	0xe41e, 0x0ca7, 0x285c, 0x7058, 0xa20a, 0x1858, 0x3c00, 0x285e,
+	0xaf04, 0x6c00, 0x285a, 0xe418, 0x09e0, 0xd190, 0x0001, 0xcb20,
+	0xa802, 0xf7e8, 0xa205, 0xe41e, 0x0ca7, 0x8877, 0x0194, 0xd190,
+	0x0004, 0xcb20, 0xa808, 0xf7e8, 0xa201, 0xe41e, 0x0ca7, 0xe42e,
+	0x286c, 0xa002, 0xb628, 0xba82, 0xe42e, 0x2837, 0xe40a, 0x09e0,
+	0x286c, 0xa140, 0xe404, 0x09ee, 0xba82, 0xe42e, 0x286c, 0xba8a,
+	0xe42e, 0x285b, 0xb670, 0xcc44, 0xe161, 0x06c0, 0xe184, 0x09fd,
+	0x2911, 0xa040, 0xb90c, 0x2911, 0xa040, 0xb90c, 0xe42e, 0xe162,
+	0x06c0, 0x285b, 0xb670, 0xcc44, 0xe184, 0x0a0c, 0x2912, 0xe41e,
+	0x0a0e, 0x2912, 0xe41e, 0x0a0e, 0xe190, 0xe42e, 0xe40a, 0x0a26,
+	0xe404, 0x0a1b, 0xa102, 0xe049, 0x5c29, 0xa002, 0xa040, 0xb90c,
+	0x462a, 0x7229, 0xe42e, 0xa002, 0xe012, 0xe049, 0x5c29, 0xa002,
+	0xe012, 0xa040, 0xb90c, 0x462a, 0x7229, 0xe42e, 0xa040, 0xb90c,
+	0xe42e, 0xe004, 0x017f, 0xcc44, 0xa202, 0xe0c2, 0x0134, 0xa200,
+	0xe184, 0x0a39, 0xe0c2, 0x0135, 0xa002, 0xe0c1, 0x0136, 0xe003,
+	0xff80, 0xf03b, 0xa200, 0xe42e, 0xa202, 0xe42e, 0xe41e, 0x101a,
+	0x2801, 0xe428, 0xa202, 0xe0c2, 0x0110, 0xa200, 0x3c5b, 0x3c5c,
+	0x3c77, 0x3c59, 0xe41e, 0x0a61, 0xe41e, 0x0fdd, 0xe41e, 0x13b8,
+	0x2a02, 0x2858, 0xe017, 0xe016, 0x4e30, 0xe055, 0xf099, 0xe0c0,
+	0x0130, 0xaf06, 0x305c, 0xe0c1, 0x0132, 0xb615, 0x3e77, 0xa200,
+	0xe42e, 0x2803, 0xf1da, 0x2824, 0xf05a, 0xe0c0, 0x018f, 0xe01a,
+	0x3c5b, 0x2824, 0xe016, 0xf088, 0xe0c0, 0x011e, 0xa802, 0x2a41,
+	0xf038, 0xe419, 0x135c, 0x3c58, 0x2a1f, 0xf03b, 0xa201, 0x3e58,
+	0x2a5b, 0xb611, 0x3e5b, 0xf04b, 0x28d3, 0xa940, 0x3cd3, 0x2a3f,
+	0x462c, 0x4602, 0x2827, 0xf0eb, 0xe41e, 0x1212, 0x2ad9, 0xf02b,
+	0x28d2, 0x2ad3, 0xa803, 0xf02b, 0x2862, 0x1862, 0xa504, 0xa4fc,
+	0x0862, 0x3c5d, 0x2a3f, 0x462c, 0x4602, 0x2827, 0xf0db, 0x2893,
+	0x2ad9, 0xf02b, 0x28c8, 0x2ad3, 0xa811, 0xf02b, 0x2863, 0x1863,
+	0xa504, 0xa4fc, 0x0863, 0x3cce, 0x285d, 0x1862, 0x3c6c, 0x2a37,
+	0xf18a, 0xf17b, 0x2862, 0xe000, 0x022c, 0xe09e, 0xe160, 0x0020,
+	0x286c, 0x1937, 0xe40a, 0x0abb, 0x286c, 0x1907, 0xe40a, 0x0abe,
+	0x285d, 0xe40e, 0x0abf, 0xa244, 0xe40e, 0x0abf, 0xa246, 0x3c6c,
+	0x286c, 0xe01a, 0x3c5a, 0x28d3, 0xaf02, 0x3cd3, 0xe42e, 0xe162,
+	0x06c0, 0x2869, 0xe09a, 0x2b15, 0x3e5b, 0x2915, 0x4d0d, 0x4c5a,
+	0x4c58, 0x4c5b, 0x4c5e, 0xe01a, 0xe016, 0x3c59, 0x2858, 0xae04,
+	0x4c59, 0xcf02, 0x2858, 0xf258, 0x2a5b, 0xcf4b, 0x2115, 0x4d15,
+	0xcf4c, 0xf0ab, 0x2115, 0x4d15, 0xcf4e, 0x2115, 0x4d15, 0xcf50,
+	0x2115, 0x4d15, 0xcf52, 0xd1a0, 0x0001, 0xcb40, 0xa802, 0xf7e8,
+	0xcb4c, 0x3512, 0x3d12, 0xf0ab, 0xcb4e, 0x3512, 0x3d12, 0xcb50,
+	0x3512, 0x3d12, 0xcb52, 0x3512, 0x3d12, 0xe08a, 0x3c69, 0xe42e,
+	0xd1a0, 0x0001, 0xcb40, 0xa802, 0xf7e8, 0xa200, 0x3c5b, 0xe42e,
+	0xbacf, 0xe004, 0x0100, 0xba9e, 0xe42e, 0xa204, 0x2ac9, 0xb632,
+	0x3c00, 0xbacf, 0xe004, 0x0120, 0xba9e, 0xbac0, 0xbae7, 0xbae0,
+	0x2800, 0xba86, 0xbae2, 0xbae3, 0xbac0, 0xbac1, 0xbae0, 0x2c20,
+	0xba9e, 0xbae0, 0x2821, 0xa102, 0xe01a, 0xba80, 0xf07a, 0x2c20,
+	0xe41e, 0x0c83, 0x3c4e, 0x2821, 0x704e, 0xbae0, 0x287a, 0x2a7b,
+	0xba98, 0xbae0, 0xba99, 0xbae0, 0xbac0, 0xbae0, 0xa200, 0x7000,
+	0xbac0, 0xbac0, 0x2800, 0xa102, 0xf02a, 0xbac0, 0xbae0, 0xbac0,
+	0x2822, 0xba80, 0xf03a, 0x2823, 0xba80, 0x2800, 0xa102, 0xe40a,
+	0x0b4b, 0xbac0, 0xbac0, 0xbac0, 0xe41e, 0x0c70, 0xc872, 0x3c54,
+	0xe42e, 0xbacf, 0xe004, 0x01b0, 0xba9e, 0x2850, 0xa116, 0xf090,
+	0x2851, 0xa112, 0xf060, 0x283d, 0xa11e, 0xf030, 0xa202, 0xf11e,
+	0x2850, 0xa12c, 0xf0d0, 0x2851, 0xa124, 0xf0a0, 0x283d, 0xa13c,
+	0xf070, 0xa01e, 0xf030, 0xa204, 0xf04e, 0xa206, 0xf02e, 0xa208,
+	0xba8e, 0xe42e, 0xbacf, 0xe004, 0x01b5, 0xba9e, 0xbae0, 0xa204,
+	0xba86, 0xa202, 0xba84, 0xbae3, 0xbac0, 0xe41e, 0x0c70, 0xe42e,
+	0xbacf, 0xe004, 0x01b6, 0xba9e, 0x2824, 0xba82, 0x2c3b, 0xf0aa,
+	0x2c2b, 0xf038, 0xbae0, 0xf06e, 0x1c20, 0xf046, 0x1821, 0xf022,
+	0xbae0, 0xbac0, 0xbae0, 0x2c20, 0xe41e, 0x0c83, 0x3c4e, 0x2c2b,
+	0x704e, 0xbae0, 0xbae0, 0x2824, 0xa102, 0xf038, 0x2825, 0xba80,
+	0x2846, 0xba84, 0xe000, 0x0220, 0xe09e, 0x2907, 0x3c26, 0x2827,
+	0xba88, 0x2824, 0xe42a, 0x2828, 0xba84, 0xa102, 0x3c29, 0xa202,
+	0x5829, 0xa102, 0x3c2a, 0xe42e, 0x2836, 0xe408, 0x0c4f, 0xe41e,
+	0x0c70, 0xbacf, 0x2861, 0xa120, 0x3c4e, 0xa202, 0x704e, 0x2852,
+	0xe41e, 0x0c83, 0x3c4e, 0x28ea, 0x704e, 0x2827, 0xba88, 0x2848,
+	0xba80, 0xe42a, 0x2c3b, 0xf0aa, 0x2c2b, 0xf038, 0xbae0, 0xf06e,
+	0x1c20, 0xf046, 0x1821, 0xf022, 0xbae0, 0xbac0, 0xbae0, 0x2c20,
+	0xe41e, 0x0c83, 0x3c4e, 0x2c2b, 0x704e, 0xbae0, 0x2824, 0xba82,
+	0x2846, 0xba84, 0x2824, 0xe42a, 0x2828, 0xba84, 0xe42e, 0xe41e,
+	0x0c7a, 0xbacf, 0xa240, 0xba8a, 0x2c3b, 0xe008, 0x00ff, 0xba8e,
+	0xbae0, 0xbac0, 0xbac0, 0xbac0, 0xbac0, 0x2855, 0xf0a8, 0x2847,
+	0xba84, 0x2824, 0xba80, 0xbac3, 0x2827, 0xba88, 0xbac0, 0xf3ee,
+	0xa20e, 0xba84, 0xbae2, 0x2847, 0xba84, 0x2838, 0xba80, 0xbac2,
+	0x2834, 0xba80, 0x2835, 0xba80, 0x2836, 0xba80, 0xbac2, 0x2837,
+	0xba80, 0xbae0, 0xbac2, 0x2824, 0xba84, 0xbac1, 0x2825, 0xba80,
+	0xbae2, 0xbac0, 0x2847, 0xa10c, 0xf0b8, 0xa204, 0xba86, 0x287a,
+	0xaf04, 0xa102, 0xba90, 0xbae0, 0x287b, 0xaf04, 0xba90, 0x2838,
+	0xf10a, 0x2821, 0xe002, 0x03e9, 0xe016, 0xba80, 0x8421, 0xe182,
+	0x0708, 0xe018, 0xc70f, 0x7c20, 0xba8c, 0x2c3b, 0xaf10, 0xba82,
+	0xa200, 0x7036, 0x7036, 0x2827, 0xba88, 0xbac0, 0xa200, 0x3cea,
+	0x2836, 0xe418, 0x0c4f, 0x2846, 0xe000, 0x0220, 0xe09e, 0x2907,
+	0x3c26, 0xa202, 0x3c28, 0xa200, 0x3c29, 0x3c2a, 0xe42e, 0x28ea,
+	0xf0ba, 0xc868, 0xa80e, 0xf06a, 0xa110, 0xe012, 0x3c4e, 0xa200,
+	0x704e, 0xba9e, 0xbae0, 0xbae0, 0x2852, 0xe41e, 0x0c8c, 0x3c4e,
+	0x2aea, 0x724e, 0xa116, 0xf046, 0x28ea, 0xf02a, 0xbae0, 0x28ea,
+	0xf03a, 0x2827, 0xba88, 0xbae0, 0x28ea, 0xf02a, 0xbac1, 0xe42e,
+	0xbac0, 0xc868, 0xa80e, 0xe42a, 0xa110, 0xe012, 0x3c4e, 0xa2fe,
+	0x704e, 0xe42e, 0xc868, 0xa80e, 0xe42a, 0xa110, 0xe012, 0x3c4e,
+	0xa200, 0x704e, 0xe42e, 0xa102, 0xa201, 0xf05a, 0xaf02, 0xa003,
+	0xe408, 0x0c86, 0xe04a, 0xe42e, 0xa102, 0xa15e, 0xf0d6, 0xa166,
+	0xf0d6, 0xe002, 0x0129, 0xf0c6, 0xe002, 0x04a4, 0xf0b6, 0xe002,
+	0x1290, 0xf0a6, 0xf0be, 0xa20c, 0xe42e, 0xa20e, 0xe42e, 0xa212,
+	0xe42e, 0xa216, 0xe42e, 0xa21a, 0xe42e, 0xa21c, 0xe42e, 0xf049,
+	0x20d4, 0x4cd5, 0xcc72, 0x2816, 0xf048, 0xc872, 0x34d4, 0x3cd5,
+	0x2816, 0xae06, 0xe000, 0x046a, 0xe092, 0xc860, 0x3511, 0x3d11,
+	0x8b11, 0x0034, 0x8b11, 0x0038, 0x8b11, 0x0033, 0x8b11, 0x0035,
+	0x8b11, 0x0037, 0x8b11, 0x0036, 0x3e16, 0xae07, 0xe001, 0x046a,
+	0xe093, 0x2111, 0x4d11, 0xcc60, 0x8911, 0x0034, 0x8911, 0x0038,
+	0x8911, 0x0033, 0x8911, 0x0035, 0x8911, 0x0037, 0x8911, 0x0036,
+	0xe42e, 0xe41e, 0x140b, 0xe004, 0x00a4, 0x3c18, 0xa200, 0x3c19,
+	0xa200, 0x3c1a, 0x3c1b, 0x2816, 0xa201, 0x3e16, 0xe424, 0xa201,
+	0xe41e, 0x0ca7, 0xe42e, 0x2824, 0xe408, 0x0cf4, 0xe004, 0x006b,
+	0xba8c, 0xbaeb, 0xe40e, 0x0cf7, 0xa23e, 0xba88, 0xbaeb, 0xe41e,
+	0x0cfc, 0xe41e, 0x0d2f, 0xe42e, 0xc872, 0x34d4, 0x3cd5, 0x281a,
+	0xe40a, 0x0d1f, 0x2818, 0xe002, 0x00a4, 0x3c1c, 0xe41e, 0x149c,
+	0xd04c, 0x0000, 0xe004, 0x00a4, 0x3c18, 0xe41e, 0x1474, 0xe004,
+	0x0800, 0x3c1e, 0xe161, 0x0080, 0xe41e, 0x0d5d, 0xc872, 0x34d4,
+	0x3cd5, 0x281c, 0xa102, 0x3c1c, 0xf718, 0xe41e, 0x1474, 0xa203,
+	0xe41e, 0x0ca7, 0xc870, 0xe008, 0x07ff, 0x3c1e, 0xe161, 0x0080,
+	0xbadf, 0xe41e, 0x0d5d, 0xc872, 0x34d4, 0x3cd5, 0xe42e, 0x281b,
+	0xe40a, 0x0d4d, 0x2819, 0x3c1c, 0xe41e, 0x14b1, 0xd04c, 0x0000,
+	0xa200, 0x3c19, 0xe41e, 0x1487, 0xe004, 0x0800, 0x3c1e, 0xe161,
+	0x00c0, 0xe41e, 0x0d5d, 0xc872, 0x34d4, 0x3cd5, 0x281c, 0xa102,
+	0x3c1c, 0xe408, 0x0d3a, 0xe41e, 0x1487, 0xa205, 0xe41e, 0x0ca7,
+	0xc870, 0xe008, 0x07ff, 0x3c1e, 0xe161, 0x00c0, 0xbadf, 0xe41e,
+	0x0d5d, 0xc872, 0x34d4, 0x3cd5, 0xe42e, 0xe082, 0xcc76, 0xa201,
+	0xe41e, 0x0ca7, 0xa201, 0x281e, 0xaf0a, 0xe40a, 0x0d6d, 0xa102,
+	0xcc44, 0xe184, 0x0d6c, 0xc87a, 0xbabe, 0x281e, 0xa83e, 0xe42a,
+	0x3c1e, 0xa140, 0xe012, 0x3c1d, 0xc87a, 0x5c1d, 0x701e, 0xe42e,
+	0xa200, 0xe0c2, 0x0128, 0xa200, 0x3c39, 0xe0c0, 0x0414, 0xf308,
+	0xa200, 0xe0c2, 0x0150, 0xe0c0, 0x0151, 0xf7e8, 0xa201, 0xae09,
+	0xa907, 0xae09, 0xa907, 0xae09, 0xa907, 0xae09, 0xa901, 0xae09,
+	0xa907, 0xae09, 0xa905, 0xae09, 0xa905, 0xe0c3, 0x0152, 0xa241,
+	0xae11, 0xa911, 0xae11, 0xa911, 0xe0c3, 0x0153, 0xa201, 0xae21,
+	0xa902, 0xae02, 0xa902, 0xae04, 0xa900, 0x3c4b, 0xe056, 0xe0c2,
+	0x015c, 0xa202, 0xe0c2, 0x0150, 0xe0c0, 0x0150, 0xf7ea, 0xe42e,
+	0xe167, 0x0502, 0xe166, 0x0064, 0xd022, 0x0003, 0xe184, 0x0dba,
+	0x9e16, 0x3517, 0x3d17, 0xe42e, 0xe41e, 0x0e05, 0xe41e, 0x0eb7,
+	0xe41e, 0x0f6e, 0xe41e, 0x0fbb, 0xe004, 0x0702, 0xe096, 0x2313,
+	0x4f13, 0xe004, 0x0700, 0xe096, 0x2113, 0x4d13, 0x3513, 0x3d13,
+	0xe004, 0x0700, 0xe096, 0x3713, 0x3f13, 0x2839, 0xe0c2, 0x0072,
+	0x3c3a, 0xa002, 0x3c39, 0x183c, 0xf028, 0x3c39, 0xe004, 0x0400,
+	0x3c68, 0x3c69, 0xd008, 0x000d, 0xd009, 0x0400, 0xd00a, 0x0436,
+	0xa202, 0x3c66, 0xe0c2, 0x0106, 0xe0c2, 0x0139, 0xe41e, 0x024d,
+	0xe0c0, 0x0065, 0xaf06, 0xa80e, 0xe42a, 0xaf04, 0x30f4, 0xe180,
+	0xe0c1, 0x0068, 0xce21, 0xd112, 0x000c, 0xd111, 0x05c0, 0xd113,
+	0x0003, 0xca29, 0xf7f9, 0xe181, 0xe42e, 0xa200, 0xe0c2, 0x0128,
+	0xe0c0, 0x0050, 0xe049, 0xe008, 0x00ff, 0x3ccc, 0xaf11, 0xe009,
+	0x00ff, 0x3ecd, 0x46cc, 0x3ecc, 0x2837, 0xae02, 0x4c36, 0xae02,
+	0x4c35, 0xae06, 0x4c30, 0xae08, 0xa916, 0xe0c2, 0x0100, 0x2050,
+	0x4c51, 0xae08, 0xe0c2, 0x0101, 0xa200, 0xe41e, 0x1028, 0xe0c2,
+	0x0102, 0xe0c0, 0x0046, 0xe005, 0x0000, 0xae11, 0xe042, 0x2acd,
+	0xa805, 0xf05b, 0xe167, 0x0504, 0x2117, 0x4d17, 0xe0c2, 0x0103,
+	0x282c, 0xae06, 0xe0c2, 0x0104, 0xa200, 0xe0c2, 0x0105, 0xe0c0,
+	0x0064, 0x3c75, 0x2a1f, 0xb612, 0xe0c2, 0x0138, 0x2050, 0x4c51,
+	0xae08, 0x2a1f, 0xaa03, 0x4675, 0xa803, 0xf04b, 0x2051, 0x4c50,
+	0xae08, 0xe0c2, 0x0142, 0xe0c0, 0x0060, 0xa87e, 0xe0c2, 0x0143,
+	0xe0c0, 0x0069, 0xe0c2, 0x014f, 0xe004, 0x3211, 0xae20, 0xe00a,
+	0x2100, 0xe0c2, 0x0155, 0xe004, 0x9211, 0xae20, 0xe00a, 0x2100,
+	0xe0c2, 0x0158, 0xe004, 0x1000, 0xae20, 0xe00a, 0x0000, 0xe0c2,
+	0x0156, 0xe0c2, 0x0159, 0xe004, 0x0104, 0xe0c2, 0x0154, 0xe0c2,
+	0x0157, 0xa202, 0xe0c2, 0x015a, 0x2827, 0xae04, 0xe0c2, 0x0176,
+	0xe049, 0xae02, 0xae05, 0xe042, 0xa004, 0xe0c2, 0x0177, 0xa200,
+	0x2acc, 0xa803, 0xf03b, 0xe00a, 0x0002, 0x2acc, 0xa805, 0xf03b,
+	0xe00a, 0x0009, 0x2acc, 0xa809, 0xf03b, 0xe00a, 0x0020, 0x2acc,
+	0xa811, 0xf03b, 0xe00a, 0x0040, 0xe0c2, 0x040c, 0x2a2c, 0xe004,
+	0x0077, 0xf039, 0xe004, 0x0070, 0xe0c2, 0x017c, 0xa200, 0xe0c2,
+	0x017d, 0xa200, 0xe0c2, 0x0113, 0xe166, 0x0510, 0x2116, 0x4d16,
+	0xe0c2, 0x011f, 0xe004, 0x003f, 0xe0c2, 0x012a, 0xe42e, 0xa200,
+	0xe0c2, 0x0312, 0xa200, 0xe0c2, 0x0320, 0xa204, 0xae02, 0x4c25,
+	0xe0c2, 0x0303, 0xa200, 0xe0c2, 0x0308, 0xa200, 0xe0c2, 0x030a,
+	0xe0c2, 0x030b, 0xe0c2, 0x030d, 0xe004, 0x0055, 0xe0c2, 0x030c,
+	0xa202, 0xe0c2, 0x0302, 0x283a, 0xe0c2, 0x0380, 0xa200, 0xe0c2,
+	0x0302, 0x282c, 0xf09a, 0xe0c0, 0x0414, 0xe418, 0x018c, 0xe0c0,
+	0x0414, 0xe41a, 0x0f43, 0xa200, 0x2a30, 0xb636, 0x2a35, 0xb632,
+	0xa904, 0xae0a, 0x4c0d, 0xe0c2, 0x0180, 0xa200, 0xe0c2, 0x0184,
+	0xe0c2, 0x0185, 0x2827, 0xaf02, 0x0844, 0xa51e, 0xe049, 0xae02,
+	0xe042, 0xe000, 0x026e, 0xe09e, 0x290f, 0xe0c2, 0x0186, 0xa206,
+	0x3c06, 0x2907, 0xae02, 0xc70f, 0x7c06, 0xe008, 0xffff, 0x2a0e,
+	0xf03b, 0xe049, 0xf02e, 0x2b07, 0xae14, 0xe056, 0xae14, 0xe056,
+	0xe0c2, 0x0181, 0xe0c2, 0x0182, 0x2827, 0xe000, 0x036c, 0xe09c,
+	0x2906, 0xae20, 0xe000, 0x1000, 0xaf1a, 0xae20, 0xe00a, 0x0190,
+	0xe0c2, 0x0183, 0x2827, 0xe000, 0x036c, 0xe09c, 0x2906, 0xe0c2,
+	0x0189, 0x280e, 0xe0c2, 0x018a, 0xa200, 0xe0c2, 0x018b, 0xe004,
+	0x0702, 0xe096, 0x2113, 0x4d13, 0xe0c2, 0x018c, 0x283a, 0xe0c2,
+	0x018d, 0xa200, 0x2a30, 0xb636, 0x2a35, 0xb632, 0xae06, 0xa902,
+	0xe0c2, 0x018e, 0xe42e, 0xa200, 0xe0c2, 0x0150, 0xe0c0, 0x0151,
+	0xf7e8, 0xe167, 0x01a0, 0x2317, 0x4f17, 0xe0c3, 0x0152, 0x2b17,
+	0xe009, 0x00ff, 0xae21, 0x4f07, 0xe0c3, 0x0153, 0xe0c1, 0x0101,
+	0xe0c3, 0x015d, 0x283a, 0xa53e, 0xa400, 0xae20, 0xe167, 0x01a2,
+	0x2b07, 0xaf11, 0xe009, 0x001b, 0xe056, 0xe0c2, 0x015c, 0xa202,
+	0xe0c2, 0x0150, 0xe0c0, 0x0150, 0xf7ea, 0xe42e, 0xa216, 0xae08,
+	0x4c24, 0xae06, 0xe0c2, 0x0204, 0x2050, 0x4c51, 0xae08, 0xe0c2,
+	0x0205, 0xa200, 0xe0c2, 0x0208, 0xa200, 0x2a35, 0xb632, 0xe0c2,
+	0x0210, 0xe0c1, 0x0046, 0xe004, 0x0040, 0xae10, 0xe042, 0x2acd,
+	0xa809, 0xf05b, 0xe167, 0x0506, 0x2117, 0x4d17, 0xe0c2, 0x0211,
+	0xe0c1, 0x0046, 0xe004, 0x0080, 0xae10, 0xe042, 0x2acd, 0xa811,
+	0xf05b, 0xe167, 0x0508, 0x2117, 0x4d17, 0xe0c2, 0x0212, 0xa200,
+	0xe0c2, 0x0215, 0xa202, 0xae10, 0xe41e, 0x1028, 0xe0c2, 0x0213,
+	0x2839, 0xe0c2, 0x020b, 0xe0c2, 0x0214, 0xa200, 0xe0c2, 0x021c,
+	0xe004, 0x0700, 0xe096, 0x2113, 0x4d13, 0xe0c2, 0x021d, 0xa200,
+	0xe0c2, 0x021e, 0xe42e, 0x2830, 0xae06, 0x4c24, 0xae02, 0xcf00,
+	0x2050, 0x4c51, 0xae08, 0xcf60, 0x2837, 0xcf68, 0x2822, 0xae02,
+	0x4c23, 0xae02, 0x4c37, 0xcf24, 0x2828, 0xcf46, 0xe0c1, 0x0046,
+	0xe004, 0x00a0, 0xae10, 0xe042, 0x2acd, 0xa803, 0xf05b, 0xe167,
+	0x0502, 0x2117, 0x4d17, 0xcf44, 0xe42e, 0x28ce, 0xae0c, 0x4cce,
+	0xae0c, 0x4cce, 0xe0c2, 0x0115, 0x2866, 0xa802, 0xe0c2, 0x0131,
+	0x2866, 0xaf02, 0x3c66, 0x2858, 0xe0c2, 0x0114, 0xe016, 0x4403,
+	0xe418, 0x0ff3, 0xe42e, 0x2868, 0xe09a, 0x2a5b, 0x3f15, 0xe162,
+	0x0190, 0x9e12, 0x3515, 0x3d15, 0xcf4c, 0xf0db, 0x9e12, 0x3515,
+	0x3d15, 0xcf4e, 0x9e12, 0x3515, 0x3d15, 0xcf50, 0x9e12, 0x3515,
+	0x3d15, 0xcf52, 0x285b, 0xcf4a, 0xd1a0, 0x0002, 0xcb41, 0xa805,
+	0xf7e9, 0xe08a, 0x3c68, 0xe004, 0x06db, 0x2a5b, 0xb616, 0xe0c2,
+	0x0309, 0xe42e, 0xe0c0, 0x0111, 0xf7e8, 0xe0c0, 0x0118, 0x3001,
+	0xaf02, 0x3002, 0xaf02, 0x3003, 0x2854, 0x4c03, 0x3c54, 0xe42e,
+	0xe0c1, 0x0044, 0xa80f, 0xe056, 0xe42e, 0xe0c1, 0x0044, 0xaf0d,
+	0xae03, 0xe056, 0xa87e, 0xe42e, 0xa203, 0xe0c3, 0x040d, 0xe0c1,
+	0x0420, 0xa803, 0xf7db, 0xe166, 0x0600, 0xe167, 0x0500, 0x283c,
+	0xf1b6, 0xa102, 0xcc44, 0xe184, 0x105a, 0xa200, 0xe41e, 0x1028,
+	0xaf04, 0xe41e, 0x102d, 0xae20, 0x4c70, 0x9f17, 0x2050, 0x4c51,
+	0xae08, 0x9f17, 0x2116, 0x4d16, 0x9f17, 0x2116, 0x4d16, 0x9f17,
+	0x2116, 0x4d16, 0x9f17, 0xa201, 0xe0c3, 0x040d, 0xe42e, 0xe0c0,
+	0x0044, 0xaf20, 0xa802, 0xe428, 0xe0c0, 0x0060, 0xa83e, 0xa203,
+	0xe0c3, 0x040d, 0xcca4, 0xc785, 0xe018, 0xe000, 0x0500, 0xe09e,
+	0xe0c1, 0x0420, 0xa803, 0xf7db, 0xa200, 0xe41e, 0x1028, 0xaf04,
+	0xe0c1, 0x0061, 0xaf21, 0xa807, 0xa105, 0xf025, 0xe04a, 0xe41e,
+	0x102d, 0xe0c1, 0x0044, 0xaf17, 0xa803, 0xe40b, 0x1088, 0xa81e,
+	0xae20, 0xe0c1, 0x0061, 0xe009, 0x1fff, 0xe056, 0x9f17, 0xe0c0,
+	0x0064, 0xa802, 0xf048, 0x2050, 0x4c51, 0xf03e, 0x2051, 0x4c50,
+	0xae08, 0x9f17, 0xe0c0, 0x006a, 0x9f17, 0xe0c0, 0x006b, 0x9f17,
+	0xe0c0, 0x006c, 0x9f17, 0xa201, 0xe0c3, 0x040d, 0xe42e, 0xcca4,
+	0xc786, 0xe018, 0xe000, 0x0600, 0xe09c, 0x2116, 0x4d06, 0xe42e,
+	0xa232, 0x3cdd, 0xa240, 0x3c84, 0xa204, 0x3c86, 0xa23e, 0x2aca,
+	0xf03b, 0xe0c0, 0x0072, 0x3c85, 0xa20c, 0x3c87, 0xe004, 0x029c,
+	0x3c88, 0x2840, 0x2a52, 0x3c89, 0x3e8f, 0x283d, 0x3c8b, 0x3cbe,
+	0xe004, 0x6000, 0x2acb, 0xf03b, 0xe0c0, 0x0073, 0x3c8c, 0x2889,
+	0xe016, 0x3c8a, 0xf06a, 0x288b, 0x3c89, 0xe004, 0x1000, 0x3c8c,
+	0x8421, 0xe182, 0x7530, 0xe018, 0xae02, 0x2e20, 0xe41e, 0x1311,
+	0x3c98, 0x8498, 0x8280, 0xe018, 0xa279, 0xe41e, 0x12fa, 0x3498,
+	0x3c99, 0xae06, 0x2a84, 0xe41e, 0x12fa, 0x349e, 0x3c9f, 0xa202,
+	0x3c8d, 0xa205, 0x1a44, 0xae03, 0xa011, 0x3e94, 0x2a8f, 0x5a94,
+	0xe013, 0x36ae, 0x3eaf, 0x28bc, 0x2abb, 0xf049, 0xe41e, 0x12a1,
+	0x64dd, 0x3c90, 0xa004, 0x6086, 0x6485, 0x3c91, 0xe41e, 0x12c5,
+	0xe42e, 0x34c0, 0x3cbf, 0x28c0, 0xa002, 0x3cc0, 0x2cbf, 0xc710,
+	0x7cc0, 0xe008, 0xffff, 0xa002, 0xaf02, 0x3c8b, 0x18be, 0xe42a,
+	0x288b, 0x3cbe, 0x28bf, 0x2ac0, 0x3c20, 0x3e21, 0xa200, 0x3c2b,
+	0x8421, 0xe182, 0x7530, 0xe018, 0xae02, 0x2e20, 0xe41e, 0x1311,
+	0x3c98, 0x8498, 0x8280, 0xe018, 0xa279, 0xe41e, 0x12fa, 0x3498,
+	0x3c99, 0xae06, 0x2a84, 0xe41e, 0x12fa, 0x349e, 0x3c9f, 0xa200,
+	0x3cb8, 0x34a2, 0x3ca3, 0x2889, 0xe428, 0xe016, 0x3c8a, 0x288b,
+	0x3c89, 0xe42e, 0x3cba, 0x2a89, 0xe046, 0xf028, 0xe42e, 0x28b9,
+	0x2aba, 0xe046, 0xf034, 0xa200, 0x3cb9, 0x28ba, 0x3c89, 0x3c40,
+	0x283f, 0xe42a, 0x2889, 0xe016, 0x3c8a, 0xf03a, 0x2a8b, 0x3e89,
+	0x2a89, 0x28b9, 0xe045, 0xf0c6, 0x20a6, 0x4ca7, 0xe41e, 0x12fa,
+	0x34aa, 0x3cab, 0x10a6, 0x1ca7, 0xe012, 0x34a8, 0x3ca9, 0xe42e,
+	0x3cbd, 0xf028, 0x3c3f, 0x283f, 0xe42a, 0x2880, 0x2abd, 0xe046,
+	0xe42a, 0x3e80, 0x8421, 0xe182, 0x7530, 0xe018, 0xae02, 0x2e20,
+	0xe41e, 0x1311, 0x3c98, 0x8498, 0x8280, 0xe018, 0xa279, 0xe41e,
+	0x12fa, 0x3498, 0x3c99, 0xae06, 0x2a84, 0xe41e, 0x12fa, 0x349e,
+	0x3c9f, 0xa200, 0x3cb8, 0x34a2, 0x3ca3, 0xe42e, 0x2a3f, 0xe42b,
+	0xf042, 0xa201, 0x3ebb, 0xe42e, 0x3cbc, 0x3c90, 0xa203, 0x3ebb,
+	0xe42e, 0xe42e, 0x282c, 0x3c8e, 0xa201, 0x3ead, 0xe418, 0x1283,
+	0xa200, 0x3ca0, 0x3ca1, 0x3cdc, 0x288e, 0xf238, 0x288d, 0xf05a,
+	0xa200, 0x3c8d, 0x2890, 0xf31e, 0x2889, 0xa102, 0xf7ca, 0x2abb,
+	0xf03b, 0x2890, 0xf2ae, 0x848f, 0x82b8, 0xe019, 0xe04a, 0xaf02,
+	0x00a2, 0x0ca3, 0xe41e, 0x1311, 0xa21f, 0x3e94, 0x2a89, 0xc70f,
+	0x7e94, 0xe009, 0xffff, 0xa405, 0xe046, 0x6086, 0x64dd, 0xf15e,
+	0xa200, 0x3c9c, 0x3c9d, 0x28d9, 0x3006, 0xaf02, 0x5406, 0xf08a,
+	0x2891, 0xa104, 0x6093, 0x2a91, 0xa005, 0xe066, 0xf02e, 0x2891,
+	0x2aad, 0xf02b, 0x2885, 0x3c93, 0x2aad, 0xe42e, 0xc872, 0xe41e,
+	0x12ce, 0x288e, 0xf0ea, 0x20a0, 0x4ca1, 0xc710, 0x7c8f, 0xe008,
+	0xffff, 0xa002, 0xaf02, 0x3c91, 0x20a0, 0x4ca1, 0x00a2, 0x0ca3,
+	0x34a2, 0x3ca3, 0x28b8, 0xa002, 0x3cb8, 0x288e, 0xf028, 0x3cb8,
+	0x288e, 0xf0f8, 0x2a89, 0xa103, 0x20a6, 0x4ca7, 0xe41e, 0x12fa,
+	0x34aa, 0x3cab, 0x10a6, 0x1ca7, 0xe012, 0x34a8, 0x3ca9, 0xf0ae,
+	0x22a8, 0x4ea9, 0x12aa, 0x1eab, 0x288a, 0xb606, 0xb611, 0x36a8,
+	0x3ea9, 0xe42e, 0x28ea, 0xf038, 0x2893, 0x3cd7, 0x2aea, 0x1a52,
+	0xa007, 0xf0b5, 0x28d1, 0x3cd2, 0xe42b, 0xa103, 0x28d0, 0x3cd2,
+	0xe42b, 0x28cf, 0x3cd2, 0xe42e, 0x229c, 0x4e9d, 0x209e, 0x4c9f,
+	0xe041, 0xf0c7, 0xe045, 0xe045, 0x2893, 0xf0f5, 0x369c, 0x3e9d,
+	0xa002, 0x6086, 0x6485, 0x3c93, 0xf08e, 0x369c, 0x3e9d, 0x2893,
+	0xa102, 0x6086, 0x6485, 0x3c93, 0x28dc, 0xa002, 0x3cdc, 0x2ad9,
+	0xf08b, 0xa103, 0xf1cb, 0xa103, 0xf07b, 0xa103, 0xf0ab, 0xf19e,
+	0x2893, 0x3cc8, 0xf16e, 0x28db, 0xf12a, 0xa200, 0x3cdb, 0xf06e,
+	0x28dc, 0x18da, 0xf0c4, 0xa200, 0x3cdc, 0x2ad7, 0xa105, 0x6293,
+	0x28d7, 0xa004, 0xe066, 0x3c93, 0x3cc8, 0xf03e, 0x28d7, 0x3cc8,
+	0x28c8, 0x3cd7, 0x28ea, 0xf078, 0x28c8, 0x3ccf, 0x3cd0, 0x3cd1,
+	0x3cd2, 0xe42e, 0x28d1, 0x2ad9, 0xa805, 0xf029, 0x3cc8, 0x3cd2,
+	0x28d0, 0x3cd1, 0x28cf, 0x3cd0, 0x28d7, 0x3ccf, 0x28c8, 0xe42e,
+	0x00a0, 0x0ca1, 0x34a0, 0x3ca1, 0x286f, 0x1892, 0x009c, 0x0c9d,
+	0x349c, 0x3c9d, 0xe42e, 0x20a8, 0x4ca9, 0x10a6, 0x1ca7, 0x848c,
+	0xe41e, 0x1348, 0x0098, 0x0c99, 0xf052, 0x2aac, 0xf039, 0xa203,
+	0x3ead, 0xe41e, 0x12e0, 0x2298, 0x4e99, 0xaf07, 0xe062, 0x349a,
+	0x3c9b, 0xc710, 0x7c8f, 0xe008, 0xffff, 0xa002, 0xaf02, 0x3c92,
+	0xe42e, 0x8489, 0x2098, 0x4c99, 0xe41e, 0x133c, 0x8487, 0xe41e,
+	0x133c, 0x2a89, 0xa103, 0x0a87, 0xe41e, 0x12fa, 0x349a, 0x3c9b,
+	0x288f, 0x3cb0, 0x209a, 0x4c9b, 0xae04, 0x009a, 0x0c9b, 0xae02,
+	0xc70f, 0x7cb0, 0xe008, 0xffff, 0xaf08, 0xa010, 0xaf08, 0x0844,
+	0xa51e, 0x0888, 0xe09e, 0x2907, 0xe42e, 0x8480, 0x8281, 0xe018,
+	0x34a4, 0x3ca5, 0xa200, 0x34a6, 0x3ca7, 0xe42e, 0x1098, 0x1c99,
+	0x00a6, 0x0ca7, 0xa27f, 0xae31, 0xe066, 0x34a6, 0x3ca7, 0x22ae,
+	0x4eaf, 0xe046, 0xf032, 0x36a6, 0x3ea7, 0x20a6, 0x28a7, 0xe42e,
+	0x2a81, 0xe42b, 0x22a4, 0x4ea5, 0x12a6, 0x1ea7, 0xe066, 0xf051,
+	0x2aac, 0xf039, 0xa203, 0x3ead, 0x2282, 0x4e83, 0xe42b, 0x22a4,
+	0x4ea5, 0x12a6, 0x1ea7, 0x0298, 0x0e99, 0x1282, 0x1e83, 0xa401,
+	0xe062, 0xe42e, 0x3eb0, 0xa201, 0xf032, 0xe012, 0xa203, 0x3eb4,
+	0x3cb1, 0xaf20, 0xc70f, 0x7cb0, 0x3cb2, 0xaf20, 0xae20, 0x4cb1,
+	0xc70f, 0x7cb0, 0x3cb3, 0x20b2, 0x4cb3, 0x2ab4, 0xe42b, 0xe012,
+	0xe42e, 0x36b0, 0x3eb1, 0xa201, 0x3eb2, 0x22b0, 0x4eb1, 0x5ab2,
+	0xe045, 0xf061, 0x2ab2, 0xa003, 0x3eb2, 0xa121, 0xf775, 0x2ab2,
+	0xf039, 0xa200, 0xe42e, 0xa103, 0x3eb2, 0xcc45, 0xa201, 0x3eb3,
+	0xe184, 0x1339, 0x2ab3, 0xae03, 0x3eb3, 0x22b0, 0x4eb1, 0x5ab2,
+	0xe045, 0xf061, 0xe013, 0xe04a, 0x2ab3, 0xa003, 0x3eb3, 0x2ab2,
+	0xa103, 0x3eb2, 0x28b3, 0xe42e, 0xae02, 0x34b1, 0xe008, 0xffff,
+	0xaf02, 0x3cb0, 0x82b1, 0xe018, 0xae1e, 0x82b0, 0xe01c, 0xe42e,
+	0xae02, 0x34b1, 0xe008, 0xffff, 0xaf02, 0x3cb0, 0x82b0, 0xe018,
+	0xaf1e, 0x82b1, 0xe01c, 0xe42e, 0xa200, 0x3cc1, 0x3cc3, 0x3cc4,
+	0xe42e, 0xa200, 0x3c42, 0xe42e, 0x28c5, 0xf1f8, 0x2842, 0x1841,
+	0xf3d2, 0x2853, 0x18c1, 0xf3a4, 0x28c1, 0x08c6, 0x18c7, 0xf0b4,
+	0x28c3, 0xa002, 0xc70f, 0x7cc6, 0xaf20, 0x3cc3, 0x3cc1, 0x2841,
+	0x3c42, 0xf2ae, 0x2842, 0xa002, 0x3c42, 0x28c1, 0x08c6, 0xc70f,
+	0x7cc7, 0xaf20, 0x3cc1, 0xf20e, 0x2842, 0x1841, 0xf1f2, 0x2853,
+	0x18c2, 0xf1c4, 0x28c2, 0x08c6, 0x1852, 0xf0c4, 0x28c4, 0xa002,
+	0xc70f, 0x7cc6, 0xaf20, 0x3cc4, 0x08c7, 0x3cc2, 0x2841, 0x3c42,
+	0xf0be, 0x2842, 0xa002, 0x3c42, 0x28c2, 0x08c6, 0xc70f, 0x7c52,
+	0xaf20, 0x3cc2, 0xf01e, 0xa202, 0xe42e, 0xa200, 0xe42e, 0x2802,
+	0xf12a, 0xd188, 0x0001, 0x28ea, 0xa002, 0x3cea, 0xcf64, 0x28e8,
+	0xa002, 0x3ce8, 0x1850, 0xf078, 0xd1b3, 0x0004, 0x3ce8, 0x28e9,
+	0xa002, 0x3ce9, 0x2803, 0xe42a, 0x2853, 0xa002, 0x3c53, 0xe42e,
+	0x28e6, 0x3ce7, 0x28e5, 0x3ce6, 0x28e4, 0x3ce5, 0x28e3, 0x3ce4,
+	0x28e2, 0x3ce3, 0x286c, 0xa83e, 0xae02, 0x4c5a, 0xae02, 0x4c58,
+	0x3ce2, 0x2a3f, 0x462c, 0x28e7, 0x3058, 0xe429, 0xaf02, 0x305a,
+	0xaf02, 0xae3e, 0xaf3e, 0x3c6c, 0xe42e, 0xa200, 0x3c13, 0xe0c0,
+	0x0060, 0x3410, 0x3c11, 0xe0c0, 0x0061, 0xae04, 0x3c12, 0xe41e,
+	0x13fa, 0xe41e, 0x1533, 0xd071, 0x202a, 0xe181, 0xe42e, 0xd030,
+	0x0000, 0xd034, 0x0000, 0xd033, 0x0000, 0xd035, 0x0000, 0xd036,
+	0x007f, 0xd037, 0x0000, 0xc872, 0xa130, 0xcc72, 0xc870, 0xa130,
+	0xcc70, 0xe42e, 0xd030, 0x0000, 0xd034, 0x0000, 0xd033, 0x0000,
+	0xd035, 0x0000, 0xd036, 0x007f, 0xd037, 0x0000, 0xd038, 0x0000,
+	0xa200, 0x3c72, 0xe42e, 0xa210, 0xe000, 0x046a, 0xe094, 0xa200,
+	0xc703, 0x3d12, 0xe004, 0x0080, 0xc702, 0x3d12, 0xe000, 0x003f,
+	0x3d12, 0xa200, 0xc703, 0x3d12, 0xe004, 0x00c0, 0xc702, 0x3d12,
+	0xe000, 0x003f, 0x3d12, 0xe42e, 0x2816, 0xf06a, 0xa102, 0xf0ba,
+	0xa102, 0xf0ea, 0xe470, 0xe004, 0x0080, 0xe41e, 0x143c, 0xd04c,
+	0x0000, 0xe470, 0xe41e, 0x149c, 0xd04c, 0x0000, 0xe470, 0xe41e,
+	0x14b1, 0xd04c, 0x0000, 0xe470, 0xce24, 0xd111, 0x0000, 0xe082,
+	0x3c14, 0xe004, 0x0048, 0xe092, 0xd027, 0x0000, 0xe41e, 0x153d,
+	0xd027, 0x0001, 0x2010, 0x4c11, 0x2e13, 0xae11, 0xe042, 0xce20,
+	0x2004, 0x4c05, 0x8111, 0x9f01, 0xe0c0, 0x0043, 0xa806, 0xae02,
+	0xa020, 0xce26, 0xca28, 0xf7f8, 0x2c13, 0xe000, 0x0002, 0x3c13,
+	0x1c12, 0xf084, 0x2ab6, 0xf05b, 0xa203, 0xe0c3, 0x0074, 0xf02e,
+	0x3c13, 0x2010, 0x4c11, 0x2e13, 0xae11, 0xe042, 0x9f01, 0x3404,
+	0x3c05, 0x2814, 0xe092, 0xe42e, 0xe0c0, 0x0046, 0x2a18, 0xae11,
+	0xe042, 0xce20, 0xd111, 0x0080, 0xd112, 0x0040, 0xd113, 0x0013,
+	0xca28, 0xf7f8, 0x2818, 0xe000, 0x0001, 0x3c18, 0xe42e, 0xe167,
+	0x0704, 0x2517, 0x4d17, 0x2e19, 0xae11, 0xe042, 0xce20, 0xd111,
+	0x00c0, 0xd112, 0x0040, 0xd113, 0x0013, 0xca28, 0xf7f8, 0x2819,
+	0xe000, 0x0001, 0x3c19, 0xe42e, 0xe0c0, 0x0046, 0x2a18, 0xae11,
+	0xe042, 0xce20, 0xd111, 0x0080, 0xd112, 0x0040, 0xd113, 0x0012,
+	0xca28, 0xf7f8, 0x2818, 0xe000, 0x0001, 0x3c18, 0xa202, 0x3c1a,
+	0xe42e, 0x287c, 0xf1f8, 0xe167, 0x0704, 0x2517, 0x4d17, 0x2e19,
+	0xae11, 0xe042, 0xce20, 0xd111, 0x00c0, 0xd112, 0x0040, 0xd113,
+	0x0012, 0xca28, 0xf7f8, 0x2819, 0xe000, 0x0001, 0x3c19, 0xe167,
+	0x0706, 0x2317, 0x4f17, 0xae05, 0x1e19, 0xf061, 0xa202, 0x3c1b,
+	0x3c7c, 0xa200, 0xe42e, 0xa202, 0x3c1b, 0xe42e, 0xc868, 0xaf06,
+	0xc867, 0xe003, 0x0000, 0xae05, 0xe042, 0x3c4c, 0xc86e, 0xd037,
+	0x0080, 0xbad7, 0xcc6e, 0xe004, 0x0080, 0xe41e, 0x143c, 0xe004,
+	0x0049, 0xe092, 0x9e01, 0x2210, 0x4e11, 0xe045, 0xf0b9, 0xe004,
+	0x0200, 0x184c, 0x2a12, 0xae11, 0xe045, 0x2010, 0x4c11, 0xe042,
+	0xf04e, 0x084c, 0xe002, 0x0200, 0x9f01, 0x3404, 0x3c05, 0xe42e,
+	0xc866, 0xcc78, 0xc860, 0xcc7a, 0xd111, 0x0000, 0xe004, 0x0048,
+	0xe092, 0xd027, 0x0000, 0xe41e, 0x153d, 0xd027, 0x0001, 0x2010,
+	0x4c11, 0x2e13, 0xae11, 0xe042, 0xce20, 0x2004, 0x4c05, 0x8111,
+	0xd112, 0x0080, 0xe0c0, 0x0043, 0xa806, 0xae02, 0xa020, 0xce26,
+	0xca28, 0xf7f8, 0xc868, 0xaf06, 0xc867, 0xe003, 0x0000, 0xae05,
+	0xe042, 0x2210, 0x4e11, 0xe042, 0x2e13, 0xae11, 0xe042, 0x9f01,
+	0x3404, 0x3c05, 0xe42e, 0x2010, 0x4c11, 0x2e13, 0xae11, 0xe042,
+	0xe0c2, 0x0049, 0x3404, 0x3c05, 0xe42e, 0xe0c1, 0x0043, 0xa809,
+	0xe429, 0xa200, 0x3c15, 0x2ab6, 0xf2eb, 0x2c13, 0xae10, 0x2e12,
+	0xae11, 0xe045, 0xe003, 0x0200, 0xe423, 0xa203, 0xe0c3, 0x0074,
+	0x2004, 0x4c05, 0xe0c2, 0x0049, 0xa200, 0x3c13, 0x2010, 0x4c11,
+	0x3404, 0x3c05, 0x2ade, 0xe42b, 0xe0c0, 0x005c, 0xe008, 0x8000,
+	0xe42a, 0xe0c0, 0x005d, 0xe00a, 0x8000, 0xe0c2, 0x005d, 0xa202,
+	0xce00, 0xe0c1, 0x005d, 0xe009, 0x8000, 0xf7c9, 0xe0c0, 0x0004,
+	0xf798, 0xe42e, 0x2004, 0x4c05, 0x9e81, 0xe045, 0xf041, 0x2c12,
+	0xae10, 0xe041, 0xe003, 0x0200, 0xe421, 0x2815, 0xf748, 0xe0c0,
+	0x005c, 0xe008, 0x8000, 0xf6fa, 0xe0c0, 0x005d, 0xe00a, 0x8000,
+	0xe0c2, 0x005d, 0xa202, 0xce00, 0x3c15, 0xf65e, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0080, 0x0060, 0x0008, 0x0006,
+	0x00b0, 0x0090, 0x000b, 0x0009, 0x0160, 0x0120, 0x0016, 0x0012,
+	0x02c0, 0x0240, 0x0058, 0x0012, 0x0580, 0x0480, 0x0160, 0x0012,
+	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	0x0063, 0x000d, 0x000f, 0x0011, 0x0013, 0x0015, 0x0017, 0x0000,
+	0xffff, 0xfffe, 0x0001, 0x0002, 0x0000, 0x0002, 0xffff, 0xffff,
+	0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xfffe,
+	0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe, 0xfffe,
+	0xfffe, 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0xfffd, 0xfffd,
+	0xfffd, 0xfffd, 0xfffd, 0xfffd, 0x0000, 0x0001, 0x0001, 0x0001,
+	0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0002,
+	0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002,
+	0x0002, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003,
+	0x0003, 0x0002, 0x0001, 0xfffb, 0x0200, 0x0000, 0x0008, 0x0200,
+	0x0000, 0x0010, 0x0200, 0x0008, 0x0020, 0x0200, 0x0010, 0x0040,
+	0x0200, 0x0020, 0x0080, 0x0200, 0x0040, 0x00c0, 0x0200, 0x0060,
+	0x0100, 0x0200, 0x0080, 0x0140, 0x0200, 0x00c0, 0x0180, 0x0200,
+	0x0100, 0x01c0, 0x0200, 0x0140, 0x0200, 0x0200, 0x0180, 0x0280,
+	0x0200, 0x0200, 0x0300, 0x0200, 0x0200, 0x0300, 0x0200, 0x0200,
+	0x0300, 0x0200, 0x0200, 0x0300, 0x001a, 0x0019, 0x0018, 0x0017,
+	0x0016, 0x0015, 0x0014, 0x0013, 0x0012, 0x0011, 0x0010, 0x000f,
+	0x000e, 0x000d, 0x000c, 0x000a, 0x0000, 0x0001, 0x0008, 0x0010,
+	0x0009, 0x0002, 0x0003, 0x000a, 0x0011, 0x0018, 0x0020, 0x0019,
+	0x0012, 0x000b, 0x0004, 0x0005, 0x000c, 0x0013, 0x001a, 0x0021,
+	0x0028, 0x0030, 0x0029, 0x0022, 0x001b, 0x0014, 0x000d, 0x0006,
+	0x0007, 0x000e, 0x0015, 0x001c, 0x0023, 0x002a, 0x0031, 0x0038,
+	0x0039, 0x0032, 0x002b, 0x0024, 0x001d, 0x0016, 0x000f, 0x0017,
+	0x001e, 0x0025, 0x002c, 0x0033, 0x003a, 0x003b, 0x0034, 0x002d,
+	0x0026, 0x001f, 0x0027, 0x002e, 0x0035, 0x003c, 0x003d, 0x0036,
+	0x002f, 0x0037, 0x003e, 0x003f, 0x0000, 0x0008, 0x0010, 0x0018,
+	0x0001, 0x0009, 0x0002, 0x000a, 0x0011, 0x0019, 0x0020, 0x0028,
+	0x0030, 0x0038, 0x0039, 0x0031, 0x0029, 0x0021, 0x001a, 0x0012,
+	0x0003, 0x000b, 0x0004, 0x000c, 0x0013, 0x001b, 0x0022, 0x002a,
+	0x0032, 0x003a, 0x0023, 0x002b, 0x0033, 0x003b, 0x0014, 0x001c,
+	0x0005, 0x000d, 0x0006, 0x000e, 0x0015, 0x001d, 0x0024, 0x002c,
+	0x0034, 0x003c, 0x0025, 0x002d, 0x0035, 0x003d, 0x0016, 0x001e,
+	0x0007, 0x000f, 0x0017, 0x001f, 0x0026, 0x002e, 0x0036, 0x003e,
+	0x0027, 0x002f, 0x0037, 0x003f, 0x0000, 0x0001, 0x0002, 0x0003,
+	0x0008, 0x0009, 0x0010, 0x0011, 0x000a, 0x000b, 0x0004, 0x0005,
+	0x0006, 0x0007, 0x000f, 0x000e, 0x000d, 0x000c, 0x0013, 0x0012,
+	0x0018, 0x0019, 0x0020, 0x0021, 0x001a, 0x001b, 0x0014, 0x0015,
+	0x0016, 0x0017, 0x001c, 0x001d, 0x001e, 0x001f, 0x0022, 0x0023,
+	0x0028, 0x0029, 0x0030, 0x0031, 0x002a, 0x002b, 0x0024, 0x0025,
+	0x0026, 0x0027, 0x002c, 0x002d, 0x002e, 0x002f, 0x0032, 0x0033,
+	0x0038, 0x0039, 0x003a, 0x003b, 0x0034, 0x0035, 0x0036, 0x0037,
+	0x003c, 0x003d, 0x003e, 0x003f, 0x0010, 0x0010, 0x0010, 0x0010,
+	0x0010, 0x0010, 0x0010, 0x0010, 0x0010, 0x0010, 0x0010, 0x0010,
+	0x000e, 0x000e, 0x000e, 0x000e, 0x000c, 0x000c, 0x000c, 0x000c,
+	0x000a, 0x000a, 0x000a, 0x000a, 0x0008, 0x0008, 0x0008, 0x0008,
+	0x0008, 0x0008, 0x0008, 0x0008, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe40e, 0x0020, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x021c, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe470, 0xe190, 0xe40e, 0x003a, 0xe470, 0xe190, 0xe470, 0xe190,
+	0xe168, 0xd027, 0x0001, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058,
+	0xa200, 0xe0c2, 0x005a, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xa2fe,
+	0x3cee, 0x3cef, 0x3cec, 0xe0c0, 0x005c, 0xa802, 0xe0c2, 0x005d,
+	0xce00, 0xf33e, 0xe41e, 0x0164, 0xe09e, 0xa202, 0xae3e, 0x9f07,
+	0xe0c0, 0x005c, 0xe0c1, 0x0059, 0x3eed, 0xa203, 0x5aed, 0xe052,
+	0xf08a, 0xe0c1, 0x005d, 0xe055, 0xe0c3, 0x005d, 0xa202, 0xce00,
+	0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2, 0x0008, 0xf00e,
+	0x28ee, 0xe412, 0x013d, 0xe190, 0xe0c0, 0x005c, 0xe0c1, 0x0059,
+	0x3eed, 0xa203, 0x5aed, 0xe052, 0xf08a, 0xe0c1, 0x005d, 0xe055,
+	0xe0c3, 0x005d, 0xa202, 0xce00, 0xe0c0, 0x004a, 0xf08a, 0xe41e,
+	0x019c, 0xe408, 0x005c, 0xe40e, 0x0058, 0xe190, 0xe0c0, 0x043d,
+	0xa1ee, 0xf7d8, 0xe004, 0x0060, 0xe0c2, 0x0009, 0xa200, 0xe0c2,
+	0x0009, 0xe0c0, 0x000d, 0xf7e8, 0xe41e, 0x00b2, 0xe41e, 0x00e2,
+	0xe41e, 0x012c, 0xd071, 0x242a, 0xe181, 0xe41e, 0x0164, 0xe09e,
+	0xa202, 0x9f07, 0xe0c0, 0x0049, 0xe0c1, 0x005b, 0xa111, 0xf033,
+	0xe0c0, 0x0048, 0xe0c2, 0x0047, 0xe0c0, 0x0059, 0xae02, 0xe000,
+	0x021c, 0xe16a, 0xc000, 0xe67c, 0xe0c0, 0x005a, 0xe008, 0xffff,
+	0x3cee, 0xe0c0, 0x005b, 0xe0c1, 0x005e, 0xae11, 0xe056, 0x3cef,
+	0xe40e, 0x0058, 0xa200, 0xe0c2, 0x0059, 0xe0c2, 0x0058, 0xe0c2,
+	0x0008, 0xe004, 0x0080, 0xe0c2, 0x017c, 0xe0c0, 0x0059, 0xf7ea,
+	0xa11e, 0xf198, 0xa202, 0xe0c2, 0x0058, 0xe004, 0xca20, 0xae20,
+	0xe005, 0x210a, 0xe056, 0xe0c2, 0x0070, 0xe004, 0x0000, 0xae20,
+	0xe00a, 0x9cea, 0xe0c2, 0x0071, 0xa200, 0xe0c2, 0x0059, 0xe0c2,
+	0x0058, 0xf64e, 0xa202, 0xe0c2, 0x0008, 0xe0c2, 0x0058, 0xd027,
+	0x0001, 0xe42e, 0xa200, 0xe0c1, 0x005b, 0xf21b, 0xa23c, 0xa103,
+	0xf37b, 0xa24c, 0xa103, 0xf34b, 0xa258, 0xa103, 0xf1db, 0xe004,
+	0x003a, 0xa103, 0xf2db, 0xe004, 0x003f, 0xa103, 0xf29b, 0xe004,
+	0x0045, 0xa103, 0xf25b, 0xa103, 0xf14b, 0xe004, 0x0063, 0xa103,
+	0xf1ab, 0xe004, 0x006a, 0xa107, 0xf1bb, 0xa200, 0xe0c1, 0x005e,
+	0xf17b, 0xa028, 0xf15e, 0xe0c1, 0x005e, 0xf12b, 0xa010, 0xf10e,
+	0xe004, 0x0049, 0xe0c1, 0x005e, 0xf0bb, 0xa010, 0xa103, 0xf08b,
+	0xa010, 0xf06e, 0xe0c1, 0x005e, 0xf03b, 0xe004, 0x0074, 0xae16,
+	0xe0c1, 0x0040, 0xe041, 0xce21, 0xd111, 0x0000, 0xd112, 0x2800,
+	0xd113, 0x000b, 0xe1e1, 0xe42e, 0xe41e, 0x01fb, 0xe0c0, 0x0059,
+	0xa102, 0xe42a, 0xe0c0, 0x005b, 0xa810, 0xf058, 0xa206, 0xe41e,
+	0x0153, 0xe42e, 0xe004, 0x023c, 0xe67c, 0xe0c0, 0x005b, 0xa810,
+	0xf058, 0xa204, 0xe41e, 0x0153, 0xe42e, 0xe004, 0x023e, 0xe67c,
+	0xa200, 0xc401, 0xe188, 0x00eb, 0x3d11, 0xe161, 0x00f2, 0xe188,
+	0x0b0d, 0x3d11, 0xe42e, 0x3cec, 0xe0c0, 0x0041, 0xe005, 0x0000,
+	0xae11, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0c00, 0x88ec,
+	0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0059, 0xa106, 0xf048,
+	0xe004, 0x0076, 0xe42e, 0xe0c0, 0x0059, 0xa10c, 0xf038, 0xe004,
+	0x0071, 0xe004, 0x0070, 0xe42e, 0xe0c0, 0x006b, 0xe167, 0x01a0,
+	0x3d07, 0xe0c0, 0x0414, 0xe428, 0xe0c1, 0x0044, 0xa809, 0xae33,
+	0xe0c0, 0x006a, 0xe167, 0x01a0, 0x3517, 0x3d17, 0xe0c0, 0x006b,
+	0xe056, 0x3517, 0x3d07, 0xe42e, 0xe167, 0x01a0, 0x2907, 0xe0c2,
+	0x0151, 0xa204, 0xe0c2, 0x0150, 0xe0c0, 0x0150, 0xa804, 0xf7da,
+	0xa208, 0xe0c2, 0x0150, 0xe42e, 0xe0c0, 0x004a, 0xe42a, 0xe0c0,
+	0x005b, 0xa110, 0xf142, 0xe0c0, 0x0059, 0xa102, 0xe41a, 0x01be,
+	0xe0c0, 0x0059, 0xa106, 0xe41a, 0x01c5, 0xe0c0, 0x0047, 0xe0c2,
+	0x0048, 0xa200, 0xe0c2, 0x004a, 0xa202, 0xe42e, 0xe0c0, 0x0047,
+	0xe0c2, 0x0049, 0xa200, 0xe0c2, 0x004a, 0xe42e, 0xe0c0, 0x004a,
+	0xa802, 0xa220, 0xe0c2, 0x0070, 0xe42e, 0xe0c0, 0x004a, 0xa802,
+	0xa220, 0xe0c2, 0x0076, 0xa200, 0xe0c2, 0x0072, 0xa2fc, 0xe0c2,
+	0x0077, 0xa2fa, 0xe0c2, 0x0071, 0xe42e, 0xe428, 0xa202, 0xe0c2,
+	0x004a, 0xe0c0, 0x0111, 0xf7e8, 0xca28, 0xf7f8, 0xca48, 0xa802,
+	0xf7e8, 0xa208, 0xae14, 0xa102, 0xe190, 0xf7e2, 0xe0c0, 0x041f,
+	0xf7e8, 0xa200, 0xe0c2, 0x041c, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8,
+	0xe004, 0x0078, 0xe0c2, 0x0009, 0xa200, 0xe0c2, 0x0009, 0xe0c0,
+	0x000d, 0xf7e8, 0xe42e, 0xa204, 0xae22, 0xcc9e, 0xa200, 0xcc72,
+	0xcc8c, 0xcc8e, 0xe004, 0xa810, 0xae20, 0xe00a, 0x9322, 0xce4a,
+	0xd16f, 0x0003, 0xe190, 0xe190, 0xe190, 0xd16f, 0x0000, 0xe42e,
+	0xe004, 0x0030, 0xce50, 0xca50, 0xa802, 0xf7ea, 0xc000, 0xe42e,
+	0xe004, 0x0020, 0xce50, 0xe42e, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
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+	0xf17b, 0xa028, 0xf15e, 0xe0c1, 0x005e, 0xf12b, 0xa010, 0xf10e,
+	0xe004, 0x0049, 0xe0c1, 0x005e, 0xf0bb, 0xa010, 0xa103, 0xf08b,
+	0xa010, 0xf06e, 0xe0c1, 0x005e, 0xf03b, 0xe004, 0x0074, 0xae16,
+	0xe0c1, 0x0040, 0xe041, 0xce21, 0xd111, 0x0000, 0xd112, 0x2800,
+	0xd113, 0x000b, 0xe1e1, 0xe42e, 0xe41e, 0x0213, 0xe0c0, 0x0059,
+	0xa102, 0xe42a, 0xe0c0, 0x005b, 0xa810, 0xf058, 0xa206, 0xe41e,
+	0x0153, 0xe42e, 0xe004, 0x0319, 0xe67c, 0xe0c0, 0x005b, 0xa810,
+	0xf058, 0xa204, 0xe41e, 0x0153, 0xe42e, 0xe004, 0x031b, 0xe67c,
+	0xa200, 0xc401, 0xe188, 0x00eb, 0x3d11, 0xe161, 0x00f2, 0xe188,
+	0x0b0d, 0x3d11, 0xe42e, 0x3cec, 0xe0c0, 0x0041, 0xe005, 0x0000,
+	0xae11, 0xe042, 0xce20, 0xd111, 0x0000, 0xd112, 0x0c00, 0x88ec,
+	0x0113, 0xca28, 0xf7f8, 0xe42e, 0xe0c0, 0x0059, 0xa106, 0xf048,
+	0xe004, 0x0076, 0xe42e, 0xe0c0, 0x0059, 0xa10c, 0xf038, 0xe004,
+	0x0071, 0xe004, 0x0070, 0xe42e, 0xe0c0, 0x006b, 0xe167, 0x01a0,
+	0x3d07, 0xe0c0, 0x0414, 0xe428, 0xe0c1, 0x0044, 0xa809, 0xae33,
+	0xe0c0, 0x006a, 0xe167, 0x01a0, 0x3517, 0x3d17, 0xe0c0, 0x006b,
+	0xe056, 0x3517, 0x3d07, 0xe42e, 0xe167, 0x01a0, 0x2907, 0xe0c2,
+	0x0151, 0xa204, 0xe0c2, 0x0150, 0xe0c0, 0x0150, 0xa804, 0xf7da,
+	0xa208, 0xe0c2, 0x0150, 0xe42e, 0xe0c0, 0x004a, 0xe42a, 0xe0c0,
+	0x005b, 0xa110, 0xf142, 0xe0c0, 0x0059, 0xa102, 0xe41a, 0x01be,
+	0xe0c0, 0x0059, 0xa106, 0xe41a, 0x01c5, 0xe0c0, 0x0047, 0xe0c2,
+	0x0048, 0xa200, 0xe0c2, 0x004a, 0xa202, 0xe42e, 0xe0c0, 0x0047,
+	0xe0c2, 0x0049, 0xa200, 0xe0c2, 0x004a, 0xe42e, 0xe0c0, 0x004a,
+	0xa802, 0xa220, 0xe0c2, 0x0070, 0xe42e, 0xe0c0, 0x004a, 0xa802,
+	0xa220, 0xe0c2, 0x0076, 0xa200, 0xe0c2, 0x0072, 0xa2fc, 0xe0c2,
+	0x0077, 0xa2fa, 0xe0c2, 0x0071, 0xe42e, 0xe428, 0xa202, 0xe0c2,
+	0x004a, 0xe0c0, 0x0111, 0xf7e8, 0xca28, 0xf7f8, 0xca48, 0xa802,
+	0xf7e8, 0xa208, 0xae14, 0xa102, 0xe190, 0xf7e2, 0xe0c0, 0x041f,
+	0xf7e8, 0xa200, 0xe0c2, 0x041c, 0xe0c0, 0x043d, 0xa1ee, 0xf7d8,
+	0xe004, 0x0078, 0xe0c2, 0x0009, 0xa200, 0xe0c2, 0x0009, 0xe0c0,
+	0x000d, 0xf7e8, 0xe42e, 0xe41e, 0x0213, 0xd160, 0x0620, 0xe004,
+	0x0019, 0xae18, 0xcec0, 0xe42e, 0xe41e, 0x0228, 0xe000, 0x0040,
+	0xce50, 0xa200, 0xd022, 0x00ff, 0xe184, 0x020f, 0xce52, 0xe190,
+	0xe41e, 0x0230, 0xe42e, 0xa204, 0xae22, 0xcc9e, 0xa200, 0xcc72,
+	0xcc8c, 0xcc8e, 0xe004, 0xa810, 0xae20, 0xe00a, 0x9322, 0xce4a,
+	0xd16f, 0x0003, 0xe190, 0xe190, 0xe190, 0xd16f, 0x0000, 0xe42e,
+	0xe004, 0x0030, 0xce50, 0xca50, 0xa802, 0xf7ea, 0xc000, 0xe42e,
+	0xe004, 0x0020, 0xce50, 0xe42e, 0xa200, 0xe0c2, 0x041c, 0xe42e,
+	0xe41e, 0x028d, 0xe42a, 0xe0c0, 0x0061, 0xe008, 0x001f, 0xe00a,
+	0x0100, 0xe0c2, 0x041c, 0xe41e, 0x02c3, 0xe41e, 0x02f4, 0xae12,
+	0xe0c2, 0x041e, 0xe41e, 0x02e7, 0xe42e, 0xe41e, 0x02b1, 0xe42a,
+	0xe0c0, 0x041f, 0xf7e8, 0xe0c0, 0x0210, 0xa804, 0xf118, 0xe0c0,
+	0x0215, 0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0216, 0xf0be, 0xe0c0,
+	0x0213, 0xe008, 0x0100, 0xf04a, 0xe0c0, 0x0214, 0xf03e, 0xe0c0,
+	0x020b, 0xe00a, 0x0100, 0xe0c2, 0x041c, 0xe41e, 0x02c3, 0xe41e,
+	0x02f4, 0xae12, 0xe0c1, 0x0210, 0xa803, 0xae15, 0xe056, 0xe0c1,
+	0x0204, 0xaf0b, 0xa87f, 0xae07, 0xe056, 0xe0c1, 0x0204, 0xa80f,
+	0xe056, 0xe0c2, 0x041e, 0xe41e, 0x02e7, 0xe42e, 0xe0c0, 0x041f,
+	0xf7e8, 0xa200, 0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xa203,
+	0xae19, 0xe052, 0xf1da, 0xe0c0, 0x0060, 0xaf08, 0xa806, 0xf18a,
+	0xe0c0, 0x0060, 0xa81e, 0xe016, 0xe0c1, 0x0060, 0xa821, 0xe017,
+	0xe056, 0xf0ea, 0xe0c0, 0x0044, 0xaf12, 0xa806, 0xe016, 0xe0c1,
+	0x0044, 0xaf17, 0xa803, 0xe056, 0xf03a, 0xa202, 0xe42e, 0xa200,
+	0xe42e, 0xe0c0, 0x0044, 0xa203, 0xae19, 0xe052, 0xf0ba, 0xe41e,
+	0x028d, 0xf088, 0xe0c0, 0x0044, 0xaf12, 0xa806, 0xf038, 0xa202,
+	0xe42e, 0xa200, 0xe42e, 0xe0c0, 0x041c, 0xe008, 0x00ff, 0xcca4,
+	0xc785, 0xe018, 0xe000, 0x0500, 0xa002, 0xae04, 0xe0c2, 0x041a,
+	0xa202, 0xe0c2, 0x0418, 0xe0c0, 0x0419, 0xf7ea, 0xe0c0, 0x041b,
+	0xaf20, 0xa01e, 0xaf08, 0xae28, 0xe0c1, 0x041b, 0xe009, 0xffff,
+	0xa01f, 0xaf09, 0xae09, 0xe056, 0xe0c2, 0x041d, 0xe42e, 0xe0c0,
+	0x041c, 0xe00a, 0x0200, 0xe0c2, 0x041c, 0xe0c0, 0x041c, 0xe00c,
+	0x0200, 0xe0c2, 0x041c, 0xe42e, 0xe0c0, 0x0044, 0xaf04, 0xa802,
+	0xe42e, 0xe40e, 0x11cc, 0xe40e, 0x031d, 0xe40e, 0x0321, 0xe40e,
+	0x0325, 0xe40e, 0x032d, 0xe40e, 0x0331, 0xe40e, 0x0335, 0xe40e,
+	0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x0339, 0xe40e, 0x00a4, 0xe40e,
+	0x00a4, 0xe40e, 0x00a4, 0xe40e, 0x11ec, 0xe40e, 0x00a4, 0xe40e,
+	0x00a4, 0xe40e, 0x066a, 0xe40e, 0x0688, 0xe41e, 0x033d, 0xe40e,
+	0x00a4, 0xe41e, 0x036b, 0xe40e, 0x00a4, 0xe41e, 0x0234, 0xe41e,
+	0x0377, 0xe41e, 0x0286, 0xe40e, 0x00a4, 0xe41e, 0x03ef, 0xe40e,
+	0x00a4, 0xe41e, 0x0429, 0xe40e, 0x00a4, 0xe41e, 0x0494, 0xe40e,
+	0x00a4, 0xe41e, 0x10f9, 0xe40e, 0x00a4, 0xa210, 0xe0c2, 0x0100,
+	0xa200, 0xe0c2, 0x0128, 0xd130, 0x0008, 0xe41e, 0x0148, 0xe41e,
+	0x0213, 0xe41e, 0x061b, 0xa200, 0x3c2a, 0x3c33, 0xcc72, 0xcc44,
+	0x3ccb, 0x3ccc, 0xf15e, 0xe41e, 0x04cf, 0xf12a, 0xe41e, 0x0937,
+	0xe41e, 0x11ac, 0xe41e, 0x11d7, 0x2815, 0xe40a, 0x0361, 0xe418,
+	0x0e1a, 0xe41e, 0x1156, 0xa202, 0xe0c2, 0x0070, 0xe42e, 0xa200,
+	0xe0c2, 0x0070, 0xe42e, 0xd130, 0x0008, 0x28be, 0xe428, 0x28bf,
+	0xf06a, 0xa200, 0x3c4d, 0xe41e, 0x11cd, 0xe42e, 0xe42e, 0xd130,
+	0x0008, 0xa200, 0xcc44, 0xcc4a, 0xcc4c, 0xcfce, 0xe0c2, 0x0074,
+	0x3c65, 0xe0c0, 0x0065, 0xaf06, 0x3066, 0xaf02, 0x3067, 0xaf02,
+	0x3068, 0xe41e, 0x065a, 0xe41e, 0x0d9e, 0xe41e, 0x0dc9, 0x28bf,
+	0xf24a, 0xc872, 0x3c07, 0x28c0, 0xf09a, 0xe0c0, 0x0066, 0x344a,
+	0x3c4b, 0xe0c0, 0x0067, 0xae04, 0x3c4c, 0xa200, 0x3c4d, 0xe41e,
+	0x11cd, 0xe41e, 0x0213, 0xa200, 0x3cdf, 0x3ce0, 0xe41e, 0x1293,
+	0xe41e, 0x12af, 0xe41e, 0x12cc, 0xe41e, 0x1206, 0xe41e, 0x12f0,
+	0xe41e, 0x12fb, 0x2807, 0xcc72, 0xd130, 0x0008, 0xd1e0, 0x0000,
+	0xd1ff, 0x03b0, 0xd199, 0x0224, 0xd03a, 0x0000, 0xd04b, 0x0001,
+	0xd04c, 0x0000, 0xd008, 0x0000, 0xe41e, 0x068e, 0x28bf, 0xf02a,
+	0xf03e, 0x28be, 0xf01a, 0x2c33, 0xae02, 0x083f, 0xa002, 0xe0c2,
+	0x0070, 0x283f, 0xf07a, 0x2c2a, 0xa002, 0x3c2a, 0x2c33, 0xa002,
+	0x3c33, 0x2829, 0xe0c2, 0x0071, 0x281f, 0xe0c2, 0x0073, 0xd039,
+	0x0000, 0xc84a, 0xc84d, 0xae20, 0xe056, 0xe0c2, 0x0053, 0xe41e,
+	0x062f, 0xe41e, 0x14d9, 0xa202, 0xe0c2, 0x0076, 0xe42e, 0xe41e,
+	0x041d, 0xe41e, 0x0174, 0xe0c0, 0x0042, 0xce20, 0xd111, 0x04c0,
+	0xd112, 0x00c0, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe0c0, 0x0060,
+	0x3c32, 0xe0c0, 0x0061, 0x3c70, 0xe004, 0x0580, 0xe096, 0xe0c0,
+	0x0062, 0x3513, 0x3d13, 0xe0c0, 0x0063, 0x3513, 0x3d13, 0xe004,
+	0x0901, 0xe096, 0xe0c0, 0x006c, 0x3513, 0x3d13, 0xe0c0, 0x006d,
+	0x3513, 0x3d13, 0xe41e, 0x0d9e, 0xe42e, 0xe167, 0x0488, 0xe166,
+	0x0064, 0xd022, 0x0003, 0xe184, 0x0427, 0x9e16, 0x3517, 0x3d17,
+	0xe42e, 0xd130, 0x0008, 0x28bf, 0xf24a, 0xc872, 0x3c07, 0x28c0,
+	0xf09a, 0xe0c0, 0x0061, 0x344a, 0x3c4b, 0xe0c0, 0x0062, 0xae04,
+	0x3c4c, 0xa200, 0x3c4d, 0xe41e, 0x11cd, 0xe41e, 0x0213, 0xa200,
+	0x3cdf, 0x3ce0, 0xe41e, 0x1293, 0xe41e, 0x12af, 0xe41e, 0x12cc,
+	0xe41e, 0x1206, 0xe41e, 0x12f0, 0xe41e, 0x12fb, 0x2807, 0xcc72,
+	0xe0c0, 0x0060, 0xa80e, 0xf0fa, 0xa102, 0xf25a, 0xa102, 0xf2aa,
+	0xa102, 0xf2aa, 0xa102, 0xf07a, 0xa102, 0xf1da, 0xa202, 0xe0c2,
+	0x0070, 0xe42e, 0xe0c0, 0x0060, 0xaf06, 0xa802, 0x3073, 0xf0ca,
+	0xe0c0, 0x0063, 0x3478, 0x3c79, 0xe0c1, 0x0064, 0x367a, 0x3e7b,
+	0xe056, 0xe01a, 0x3c73, 0xe0c0, 0x0060, 0xa808, 0xe01a, 0xe41e,
+	0x05ea, 0xf12e, 0xe0c0, 0x0060, 0xa808, 0xe01a, 0xe41e, 0x05fa,
+	0xf0be, 0xa214, 0xf02e, 0xa216, 0x3c30, 0xa200, 0x3c2f, 0xe41e,
+	0x130d, 0xe41e, 0x1368, 0x28bf, 0xf02a, 0xf03e, 0x28be, 0xf01a,
+	0xa202, 0xe0c2, 0x0070, 0xe42e, 0xe41e, 0x11bb, 0xa200, 0xce92,
+	0xe0c0, 0x0060, 0xa802, 0xf198, 0xe0c0, 0x0060, 0xaf04, 0xa802,
+	0x3073, 0xf0ca, 0xe0c0, 0x0063, 0x3478, 0x3c79, 0xe0c1, 0x0064,
+	0x367a, 0x3e7b, 0xe056, 0xe01a, 0x3c73, 0xe0c0, 0x0060, 0xa804,
+	0xe01a, 0xe41e, 0x0818, 0xf07e, 0xe0c0, 0x0060, 0xa804, 0xe01a,
+	0xe41e, 0x08b0, 0xc870, 0xaf06, 0x3c45, 0xe0c2, 0x0070, 0xe004,
+	0x0080, 0xcc6e, 0xbadf, 0xe0c0, 0x0042, 0xce20, 0xd111, 0x0000,
+	0xd112, 0x0100, 0xd113, 0x0012, 0xca28, 0xf7f8, 0xe42e, 0xe0c0,
+	0x0074, 0xa806, 0x3cc9, 0xe0c0, 0x0074, 0xaf04, 0x3cca, 0xe0c0,
+	0x0064, 0x3450, 0x3c51, 0x2850, 0xa01e, 0xaf08, 0x3c50, 0x2851,
+	0xa01e, 0xaf08, 0x3c51, 0xe0c0, 0x0065, 0x3418, 0x3c17, 0x2817,
+	0xae02, 0x3c17, 0x2818, 0xa002, 0x3c18, 0x2c17, 0xc710, 0x7c18,
+	0xe008, 0xffff, 0xa002, 0xaf02, 0x3c88, 0xe0c0, 0x0062, 0xaf04,
+	0x301b, 0xaf04, 0x30e1, 0xaf02, 0x30b8, 0xe0c1, 0x0071, 0x3eb9,
+	0xaf02, 0x30c8, 0xaf02, 0x30c7, 0xaf02, 0x30e6, 0xaf02, 0x30e5,
+	0xaf02, 0xe0c0, 0x0068, 0xe049, 0xa83f, 0xae3f, 0xaf3f, 0x3e24,
+	0xe049, 0xaf0b, 0x3226, 0xe049, 0xaf0d, 0xa807, 0x3e2c, 0xe049,
+	0xaf11, 0xa81f, 0xaf41, 0xae41, 0xae03, 0x3e2d, 0xe049, 0xaf19,
+	0xa81f, 0xaf41, 0xae41, 0xae03, 0x3e2e, 0x282c, 0x4c2d, 0x4c2e,
+	0xe01a, 0x3c25, 0xe0c0, 0x0069, 0x3038, 0xaf02, 0x3039, 0xaf02,
+	0x3c3a, 0xe0c0, 0x006a, 0x3c14, 0xe0c0, 0x006b, 0x3480, 0x3015,
+	0xaf02, 0xe008, 0x7fff, 0x3c7f, 0xf028, 0x3c15, 0x2880, 0xaf1e,
+	0x3091, 0x2880, 0xe008, 0x7fff, 0x3c80, 0xe0c0, 0x006c, 0x3481,
+	0x3c82, 0xe0c0, 0x006d, 0x3c1c, 0xa20a, 0x3c10, 0xa002, 0x3c12,
+	0xa202, 0x3c13, 0xa102, 0x3c22, 0xa200, 0x3c21, 0x3c20, 0x3c27,
+	0xa204, 0x3c11, 0xa234, 0x3c23, 0x8450, 0x8251, 0xe018, 0x3c52,
+	0xa201, 0xe002, 0x00c8, 0xb425, 0xe002, 0x0190, 0xb425, 0x3e36,
+	0xe0c0, 0x0075, 0xe166, 0x0600, 0x3516, 0x3d16, 0xe0c0, 0x0076,
+	0xe049, 0xa806, 0x3cd7, 0xe04a, 0xaf04, 0x30d9, 0xaf02, 0xa81e,
+	0x3cd8, 0x28d9, 0xe016, 0x3cd9, 0xae02, 0x4cd9, 0xae02, 0x4cd9,
+	0x3cd9, 0x28d8, 0xf028, 0xa21e, 0x3cd8, 0x2850, 0x2a51, 0xaf06,
+	0xaf07, 0x3c08, 0x3e09, 0x8408, 0x8209, 0xe018, 0x3cc1, 0xa104,
+	0xf032, 0xa204, 0x3cc1, 0x2851, 0xaf02, 0x3c08, 0x8408, 0x8250,
+	0xe018, 0x3cc3, 0xe161, 0x0906, 0x3d01, 0x3cc6, 0xa202, 0x3c1e,
+	0xe0c0, 0x0043, 0xaf06, 0x30be, 0xaf02, 0x30bf, 0xaf02, 0x30c0,
+	0xaf02, 0x30ce, 0xa202, 0xe42e, 0xcb04, 0xaf20, 0xe000, 0x0490,
+	0xe09e, 0xc872, 0x3d07, 0xcb04, 0xaf20, 0xa002, 0x1850, 0xe428,
+	0xcb04, 0xe008, 0xffff, 0xae0e, 0xe005, 0x0000, 0xae11, 0xe042,
+	0xe0c1, 0x0042, 0xe042, 0xce20, 0xd111, 0x0490, 0xd112, 0x002e,
+	0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0x204a, 0x4c4b, 0x2e4d,
+	0xae11, 0xe042, 0x0840, 0xe161, 0x0434, 0x3511, 0x3d11, 0x281f,
+	0xae04, 0xe005, 0x0012, 0xae11, 0xe042, 0xe0c1, 0x0042, 0xe042,
+	0xce20, 0xd111, 0x0434, 0xd112, 0x0004, 0xd113, 0x0002, 0xca28,
+	0xf7f8, 0xe42e, 0x3c07, 0xa206, 0x3c2f, 0xa20e, 0x2a07, 0xf02b,
+	0xa21e, 0x3c30, 0xe41e, 0x130d, 0x2807, 0xe41e, 0x0818, 0xe41e,
+	0x1368, 0xe42e, 0x3c07, 0xa206, 0x3c2f, 0xa210, 0x3c30, 0xe41e,
+	0x130d, 0x2807, 0xe41e, 0x08b0, 0xe41e, 0x1368, 0xe42e, 0xa200,
+	0x3c2f, 0x283f, 0xf06a, 0xa230, 0x3c30, 0xe41e, 0x130d, 0xf09e,
+	0xa212, 0x3c30, 0xe41e, 0x130d, 0xa204, 0xba84, 0xe41e, 0x092d,
+	0xe41e, 0x1368, 0xe42e, 0xe0c0, 0x0040, 0xe005, 0x0063, 0xae17,
+	0xe042, 0xe005, 0x1900, 0xae03, 0xe042, 0xce20, 0xd111, 0x0700,
+	0xd112, 0x0200, 0xd113, 0x0003, 0xca28, 0xf7f8, 0xe42e, 0x2866,
+	0x4c67, 0x4c68, 0xe42a, 0xe167, 0x05f0, 0xc410, 0x2866, 0xae10,
+	0x3d17, 0x2852, 0x3d17, 0x8137, 0x2867, 0xae12, 0x2a31, 0xe017,
+	0xe056, 0x3d17, 0x2852, 0xae04, 0x3d17, 0x8137, 0x2868, 0xae14,
+	0x2a1f, 0xe056, 0x3d17, 0x281f, 0xae06, 0x3d17, 0xe0c0, 0x0068,
+	0xce20, 0xd111, 0x05f0, 0xd112, 0x000c, 0xd113, 0x0002, 0xca28,
+	0xf7f8, 0xe42e, 0x2866, 0x4c67, 0x4c68, 0xe42a, 0xe0c0, 0x0068,
+	0xce20, 0xd111, 0x05f0, 0xd112, 0x000c, 0xd113, 0x0003, 0xca28,
+	0xf7f8, 0xe42e, 0xa206, 0xe41e, 0x0153, 0xe0c0, 0x005a, 0xe008,
+	0xffff, 0x3cee, 0xe41e, 0x0213, 0xa200, 0x3cdf, 0x3ce0, 0xe41e,
+	0x1293, 0xe41e, 0x12af, 0xe41e, 0x12cc, 0xe41e, 0x14ae, 0xe41e,
+	0x1206, 0xe41e, 0x12f0, 0xe41e, 0x12fb, 0xe41e, 0x14b6, 0xe42e,
+	0xe41e, 0x149a, 0xa204, 0xe41e, 0x0153, 0xe42e, 0x2824, 0xa83e,
+	0xae06, 0xcf80, 0xe41e, 0x1368, 0x283f, 0xf048, 0x2834, 0x3ce2,
+	0xf06e, 0x283e, 0x44e1, 0xf03a, 0x28e2, 0x3c35, 0xd1f3, 0x0000,
+	0x2835, 0xcfe4, 0xa200, 0xcfc2, 0xd1e8, 0x0055, 0x2850, 0xa102,
+	0xae02, 0x4c26, 0xae06, 0xcf00, 0xd1d3, 0x000d, 0xd185, 0x0001,
+	0xe41e, 0x112c, 0xe41e, 0x1131, 0x281b, 0xe418, 0x0607, 0xe41e,
+	0x06f0, 0x283f, 0x2ae6, 0x463e, 0xe419, 0x05ea, 0x283f, 0x2ae6,
+	0x463e, 0xe419, 0x05fa, 0x283d, 0x3c2b, 0xe41e, 0x1161, 0x283f,
+	0xf078, 0x2829, 0xf05a, 0x281e, 0xa002, 0xa802, 0x3c1e, 0xe41e,
+	0x096f, 0xe41e, 0x0d67, 0xe41e, 0x0812, 0xa200, 0x3c53, 0x3c1f,
+	0x2831, 0xa004, 0x3c2f, 0x283f, 0xe016, 0x44e5, 0xe418, 0x1513,
+	0xe41e, 0x0737, 0x2865, 0xaa02, 0x3c65, 0x2853, 0x1852, 0xf744,
+	0xe41e, 0x0d85, 0xe41e, 0x0b79, 0x2815, 0xe418, 0x0e23, 0xe42e,
+	0x283f, 0xf208, 0xe0c0, 0x0065, 0xa804, 0xf06a, 0xa200, 0x3c2a,
+	0x3cb6, 0xe016, 0x3c89, 0x2814, 0xf048, 0x2c2a, 0xf07a, 0xf0ae,
+	0x28b6, 0xf04a, 0x2a14, 0xe046, 0xf058, 0x3c29, 0xa202, 0x3cb6,
+	0xf05e, 0xa202, 0x3c29, 0x08b6, 0x3cb6, 0x2829, 0xe016, 0x3c3e,
+	0xf05e, 0x283e, 0x44e1, 0xf02a, 0x3c29, 0xa200, 0x3c72, 0xe0c0,
+	0x0065, 0xa802, 0xe418, 0x0730, 0xe0c0, 0x0063, 0xa408, 0x3c3d,
+	0x2815, 0xf09a, 0x2829, 0xe41a, 0x0e1d, 0xe41e, 0x0e20, 0x3c3d,
+	0xe419, 0x0730, 0x2c2a, 0xe016, 0x3c31, 0xa004, 0x3c2f, 0xe42e,
+	0xa202, 0x3c29, 0x3c72, 0x2835, 0xe0c2, 0x0060, 0xe42e, 0x2a31,
+	0xa20a, 0xb636, 0x2a3f, 0xf02b, 0xa228, 0x3c30, 0xe41e, 0x130d,
+	0xe41e, 0x08d7, 0xa202, 0x3ccb, 0xe41e, 0x076d, 0xe41e, 0x092d,
+	0xe41e, 0x1368, 0x2868, 0xe418, 0x0751, 0x281f, 0xa002, 0x3c1f,
+	0xe42e, 0xe167, 0x05ec, 0xa200, 0x3d17, 0x2853, 0xa102, 0x3d17,
+	0xcaaa, 0xae06, 0x3517, 0x3d17, 0x281f, 0xae06, 0xe167, 0x05fa,
+	0x2317, 0x4f17, 0xe042, 0xce20, 0xd111, 0x05ec, 0xd112, 0x0004,
+	0xd113, 0x0002, 0xca28, 0xf7f8, 0xe42e, 0x282b, 0xcf96, 0x282c,
+	0xae0a, 0x2a2d, 0xa83f, 0xe056, 0xae0a, 0x2a2e, 0xa83f, 0xe056,
+	0xcf30, 0x2829, 0xcfc4, 0xcf82, 0xd188, 0x0001, 0xa200, 0xcf86,
+	0x3c3b, 0xa202, 0x3c3c, 0xe41e, 0x07a3, 0xe41e, 0x0815, 0x8a5e,
+	0x0039, 0xe41e, 0x07ea, 0xc872, 0x1c5e, 0xe008, 0xffff, 0x3c5f,
+	0x2a15, 0xcb96, 0xe419, 0x0e29, 0x2853, 0x1852, 0xf042, 0x283b,
+	0xe40a, 0x0783, 0xcb86, 0xf02a, 0xbbfc, 0x2a15, 0xcb96, 0xf02b,
+	0x3c2b, 0xa202, 0xe42e, 0x2838, 0x2a39, 0xe42a, 0xf0a9, 0x28dc,
+	0xe42a, 0xa102, 0x3cdc, 0xa102, 0xe428, 0xa202, 0x3c3b, 0xe42e,
+	0x283c, 0x183a, 0x2a3c, 0xa003, 0x3e3c, 0xe428, 0xa202, 0x3c3c,
+	0x3c3b, 0xe42e, 0x2a38, 0x2839, 0xe42b, 0xa201, 0xf0a8, 0x28dc,
+	0xe428, 0xc870, 0x1c3a, 0xe424, 0xa209, 0x3ed1, 0x3edc, 0xe42e,
+	0x28d0, 0xa002, 0x3cd0, 0xa102, 0x183a, 0xe428, 0xa203, 0x3ed1,
+	0x3ed0, 0xe42e, 0xa200, 0x3cd1, 0x3cdc, 0xa202, 0x3cd0, 0xe42e,
+	0xcb1c, 0xf7f8, 0xd185, 0x0002, 0xd186, 0x0000, 0x2855, 0xae02,
+	0x4c54, 0xcf8a, 0x2859, 0xcf94, 0xa200, 0xcfdc, 0xcf84, 0x2858,
+	0xcfd2, 0xe42e, 0x2876, 0xf05a, 0xe41e, 0x0be3, 0xe41e, 0x0bbc,
+	0xcba0, 0xf7f8, 0x2854, 0xf0ba, 0xcb18, 0x3c00, 0x2855, 0xf04a,
+	0x2856, 0xae38, 0xcf8c, 0x2857, 0xcf90, 0xf03e, 0xcbd2, 0xcf9a,
+	0xd1d0, 0x003f, 0xa202, 0x3c76, 0xe41e, 0x0ada, 0x2a66, 0xcba0,
+	0xf7f8, 0xe419, 0x0d1c, 0xd186, 0x0001, 0xd185, 0x0004, 0xcb06,
+	0x3c53, 0xe42e, 0xe41e, 0x0a97, 0xe42e, 0xe41e, 0x0acf, 0xe42e,
+	0x3c07, 0xe005, 0x0064, 0xf03a, 0xe005, 0x0080, 0xba8f, 0xbac7,
+	0x8452, 0x8288, 0xe019, 0xaf03, 0x2852, 0xe002, 0x0063, 0xf070,
+	0xe04a, 0xe002, 0x05cd, 0xf030, 0xa214, 0xf37e, 0x2852, 0xe002,
+	0x018c, 0xf070, 0xe04a, 0xe002, 0x2e68, 0xf030, 0xa228, 0xf2de,
+	0x2852, 0xe002, 0x0654, 0xf070, 0xe04a, 0xe002, 0x9e34, 0xf030,
+	0xa23c, 0xf23e, 0x2852, 0xe002, 0x0e10, 0xf080, 0xe004, 0x0d2f,
+	0xae0a, 0xe046, 0xf034, 0xa23e, 0xf18e, 0x2852, 0xe002, 0x1400,
+	0xf080, 0xe004, 0x0d2f, 0xae0c, 0xe046, 0xf034, 0xa240, 0xf0de,
+	0x2852, 0xe002, 0x2000, 0xf080, 0xe004, 0x03c0, 0xae10, 0xe046,
+	0xf034, 0xa250, 0xf02e, 0xa254, 0xe0c1, 0x0060, 0xaf09, 0xa803,
+	0xf06b, 0xe0c0, 0x0060, 0xaf10, 0xe008, 0x00ff, 0x3ce3, 0xba8e,
+	0x2807, 0xbbfc, 0xa202, 0xbbfc, 0xa200, 0xbbfc, 0xbbfc, 0xbac1,
+	0x2810, 0xa108, 0xbbfc, 0x2811, 0xbbfc, 0x2811, 0xf048, 0x2812,
+	0xa108, 0xbbfc, 0x2813, 0xbbfc, 0xe190, 0xbac0, 0x2850, 0xa102,
+	0xbbfc, 0x2851, 0xa102, 0xbbfc, 0xe190, 0xbae0, 0xe190, 0xbae0,
+	0x2873, 0xf038, 0xbac0, 0xf0fe, 0xbae0, 0x2878, 0xaf02, 0xbbfc,
+	0x2879, 0xaf02, 0xbbfc, 0x287a, 0xaf02, 0xbbfc, 0x287b, 0xaf02,
+	0xbbfc, 0xe190, 0xbac0, 0x2807, 0xf05a, 0xbae0, 0xe41e, 0x14f2,
+	0xbac1, 0xe41e, 0x092d, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e,
+	0xbbfc, 0xbbfc, 0xbac0, 0x2820, 0xba80, 0x2821, 0xbbfc, 0xe408,
+	0x08d4, 0x2822, 0xbbfc, 0xa200, 0xe190, 0xbbfc, 0xe190, 0xbac0,
+	0xe190, 0xbac1, 0xe190, 0x2823, 0xa134, 0xbbfe, 0xa200, 0xbbfe,
+	0x2824, 0xbbfe, 0x2825, 0xba80, 0x2826, 0xba80, 0x2827, 0xba80,
+	0xe41e, 0x092d, 0xa202, 0xe42e, 0xe16a, 0xa200, 0xe42e, 0x2853,
+	0xbbfc, 0x2829, 0xe016, 0xae02, 0xe049, 0xe01b, 0x463f, 0xf029,
+	0xa00a, 0xbbfc, 0x283f, 0xbbfc, 0x2c2a, 0x7010, 0x2831, 0xf03a,
+	0xa200, 0xbbfc, 0x2811, 0xf098, 0x2c33, 0xae02, 0x7012, 0x2820,
+	0xe40a, 0x08f4, 0xa200, 0xbbfe, 0x2827, 0xe40a, 0x08f9, 0xa200,
+	0xbbfc, 0x2829, 0xf12a, 0xbac0, 0xe190, 0x2831, 0xe016, 0x443e,
+	0x44e1, 0x443f, 0xf09a, 0xbae0, 0xa20a, 0xbbfc, 0xa200, 0xbbfc,
+	0xa206, 0xbbfc, 0xf02e, 0xbac0, 0x282f, 0xe40a, 0x0918, 0x2831,
+	0xe40a, 0x0917, 0xbac0, 0xe190, 0xbac0, 0xe40e, 0x0918, 0xbac0,
+	0x282b, 0x1823, 0xbbfe, 0x2825, 0xe40a, 0x0929, 0x282c, 0xbbfc,
+	0xa102, 0xe40a, 0x0929, 0x282d, 0xaf02, 0xbbfe, 0x282e, 0xaf02,
+	0xbbfe, 0xa202, 0xe42e, 0xa200, 0xe42e, 0xbae0, 0xc868, 0xa80e,
+	0xe42a, 0xa110, 0xe012, 0x3c48, 0xa200, 0x7048, 0xe42e, 0xa200,
+	0x3c34, 0xe004, 0x0190, 0x3c75, 0xe0c0, 0x0414, 0xe428, 0xa200,
+	0xe0c2, 0x0150, 0xe0c0, 0x0151, 0xf7e8, 0xa201, 0xae09, 0xa907,
+	0xae09, 0xa907, 0xae09, 0xa907, 0xae09, 0xa901, 0xae09, 0xa907,
+	0xae09, 0xa905, 0xae09, 0xa905, 0xe0c3, 0x0152, 0xa241, 0xae11,
+	0xa911, 0xae11, 0xa911, 0xe0c3, 0x0153, 0xa201, 0xae21, 0xa902,
+	0xae02, 0xa902, 0xae04, 0xa900, 0x3cde, 0xe056, 0xe0c2, 0x015c,
+	0xa202, 0xe0c2, 0x0150, 0xe0c0, 0x0150, 0xf7ea, 0xe42e, 0xe41e,
+	0x0cb2, 0xa210, 0xe0c2, 0x0100, 0xa200, 0xe0c2, 0x0128, 0x2a29,
+	0xe004, 0x016f, 0xf039, 0xe004, 0x0168, 0xe0c2, 0x017c, 0xa200,
+	0xe0c2, 0x017d, 0xe0c2, 0x013d, 0xe0c0, 0x0050, 0xe049, 0xe008,
+	0x007f, 0x3c00, 0xaf11, 0xe009, 0x007f, 0x3e01, 0x4600, 0x3e00,
+	0xa200, 0x2a00, 0xa803, 0xf03b, 0xe00a, 0x0002, 0x2a00, 0xa805,
+	0xf02b, 0xa912, 0x2a00, 0xa809, 0xf02b, 0xa940, 0x2a00, 0xa811,
+	0xf02b, 0xa980, 0xe0c2, 0x040c, 0xe0c1, 0x0046, 0xe004, 0x0000,
+	0xae10, 0xe042, 0x2a01, 0xa803, 0xf05b, 0xe161, 0x0488, 0x2111,
+	0x4d11, 0xcf0e, 0xe0c1, 0x0046, 0xe004, 0x0040, 0xae10, 0xe042,
+	0x2a01, 0xa805, 0xf05b, 0xe161, 0x048a, 0x2111, 0x4d11, 0xe0c2,
+	0x0103, 0xa200, 0xe0c2, 0x0208, 0xa200, 0xe0c2, 0x021c, 0xa202,
+	0xe0c2, 0x0210, 0xa200, 0xe0c2, 0x0215, 0xe41e, 0x0d92, 0xa203,
+	0xae09, 0xa901, 0xae09, 0xe056, 0xe0c2, 0x0213, 0xe0c1, 0x0046,
+	0xe004, 0x0070, 0xae10, 0xe042, 0x2a01, 0xa809, 0xf05b, 0xe161,
+	0x048c, 0x2111, 0x4d11, 0xe0c2, 0x0211, 0xe0c1, 0x0046, 0xe004,
+	0x0070, 0xe000, 0x0040, 0xae10, 0xe042, 0x2a01, 0xa811, 0xf05b,
+	0xe161, 0x048e, 0x2111, 0x4d11, 0xe0c2, 0x0212, 0xe0c0, 0x0064,
+	0x3c71, 0x2a72, 0xf02b, 0xa200, 0xe0c2, 0x0138, 0x2050, 0x4c51,
+	0xae08, 0xe0c2, 0x0101, 0xe0c2, 0x0205, 0x2a72, 0xaa03, 0x4671,
+	0xa803, 0xf04b, 0x2051, 0x4c50, 0xae08, 0xe0c2, 0x0142, 0xa200,
+	0xe41e, 0x0d92, 0xe0c2, 0x0102, 0x2829, 0xae06, 0xe0c2, 0x0104,
+	0xa210, 0xae08, 0x4c29, 0xae06, 0xe0c2, 0x0204, 0xe0c0, 0x0060,
+	0xa87e, 0xe0c2, 0x0143, 0xe0c0, 0x0069, 0xe0c2, 0x014f, 0xe004,
+	0x0580, 0xe096, 0x2113, 0x4d13, 0xe0c2, 0x021d, 0x2834, 0xe0c2,
+	0x020b, 0xe0c2, 0x0214, 0xa200, 0xe0c2, 0x0312, 0xa202, 0xe0c2,
+	0x0302, 0x2835, 0xe0c2, 0x0380, 0xe0c2, 0x018d, 0x3cdd, 0xa200,
+	0xe0c2, 0x0302, 0x2834, 0xe0c2, 0x0072, 0x3c35, 0xa002, 0x3c34,
+	0x1832, 0xf028, 0x3c34, 0xa200, 0xe0c2, 0x0113, 0xe0c2, 0x030d,
+	0xe0c2, 0x0320, 0xe0c2, 0x030a, 0xe0c2, 0x030b, 0xe004, 0x0055,
+	0xe0c2, 0x030c, 0xe004, 0x003f, 0xe0c2, 0x012a, 0xe166, 0x0600,
+	0x2116, 0x4d16, 0xe0c2, 0x011f, 0x2826, 0xe0c2, 0x0179, 0xe41e,
+	0x0c39, 0xe004, 0x0582, 0xe096, 0x2313, 0x4f13, 0xe004, 0x0580,
+	0xe096, 0x2113, 0x4d13, 0x3513, 0x3d13, 0xe004, 0x0580, 0xe096,
+	0x3713, 0x3f13, 0xe41e, 0x0d4a, 0xe41e, 0x0d5c, 0xa202, 0xe0c2,
+	0x0106, 0xe0c2, 0x0139, 0xe41e, 0x024d, 0xa204, 0x2a3d, 0xa115,
+	0xb60a, 0x3cd5, 0x2a72, 0xa200, 0xf02b, 0xa208, 0xe0c2, 0x0140,
+	0x3cd6, 0x2a50, 0xa10f, 0xa200, 0xb62e, 0x3cd4, 0xe42e, 0xa2f0,
+	0x3c53, 0xe0c2, 0x003f, 0xe41e, 0x0cd3, 0xe41e, 0x07d2, 0xa200,
+	0x3c76, 0xa2f2, 0x3c53, 0x2853, 0xe0c2, 0x003f, 0xa00a, 0xf078,
+	0xe41e, 0x0cd7, 0xa202, 0xe0c2, 0x021e, 0xf17e, 0xa102, 0xf0a8,
+	0xe41e, 0x0c22, 0xe41e, 0x0cd7, 0xe41e, 0x0c1b, 0xe41e, 0x0c11,
+	0xf0ce, 0xf094, 0x2839, 0xf048, 0xe41e, 0x0ada, 0xf0ae, 0xe41e,
+	0x0ad2, 0xf07e, 0xe41e, 0x0cd7, 0xe41e, 0x0cdb, 0xe41e, 0x0cd3,
+	0xa200, 0x3ccc, 0x2853, 0xa002, 0x3c53, 0xf564, 0xe42e, 0x2853,
+	0xe0c2, 0x003f, 0xe41e, 0x07ba, 0xe419, 0x1131, 0xe41e, 0x0c22,
+	0x2876, 0xf0c8, 0x2863, 0xa002, 0x3c63, 0x1850, 0xf028, 0x3c63,
+	0x2864, 0xe0c2, 0x0120, 0x2876, 0xe428, 0x2853, 0xf104, 0xa106,
+	0xa80e, 0xae06, 0x3cdb, 0xe41e, 0x0c01, 0x2a67, 0xe41e, 0x0bd2,
+	0xe419, 0x0cdf, 0xe41e, 0x07d8, 0xd1f0, 0x000d, 0x2ad4, 0x2853,
+	0xa80e, 0xae06, 0x3cda, 0xf05b, 0x2863, 0xe016, 0x4cd1, 0x3cd1,
+	0x2a72, 0xe0c0, 0x011c, 0xf7ea, 0xf07b, 0xa200, 0x3c00, 0x3c01,
+	0xe0c2, 0x0114, 0xf10e, 0xe0c0, 0x011e, 0x3000, 0x44d5, 0x3c01,
+	0x4c00, 0xe0c2, 0x0114, 0xf07a, 0xe0c0, 0x0170, 0x3c02, 0xe0c0,
+	0x0174, 0x3c03, 0x2ad1, 0xe0c0, 0x0141, 0x3c64, 0xf09b, 0xe41e,
+	0x0c1b, 0xa200, 0x3cd1, 0xa203, 0x4ed6, 0xe0c3, 0x0140, 0xe41e,
+	0x113a, 0x2a29, 0xf17b, 0xe0c0, 0x018f, 0x3c04, 0xe0c2, 0x0309,
+	0x28da, 0xe000, 0x02c0, 0xe092, 0xe162, 0x0190, 0xe163, 0x03b0,
+	0xc420, 0xd022, 0x0003, 0xe184, 0x0b40, 0x9e12, 0x3511, 0x3d11,
+	0x9f33, 0x2a00, 0xe0c0, 0x0111, 0xf7e8, 0x2853, 0xe0c3, 0x0188,
+	0xf064, 0xa210, 0xe0c2, 0x0134, 0xd1d0, 0x0080, 0x2a29, 0x2864,
+	0xe0c2, 0x0119, 0x28d2, 0xe0c2, 0x011a, 0x2862, 0xe0c2, 0x011b,
+	0xa202, 0xe0c2, 0x0110, 0x2a76, 0xf1c9, 0x2115, 0x4d15, 0xcf8c,
+	0x2115, 0x4d15, 0xcf8e, 0x28da, 0xe000, 0x0280, 0xe092, 0x2801,
+	0x4c00, 0x3d11, 0x2802, 0xae10, 0x4c03, 0x3d11, 0x2804, 0x3d11,
+	0xe0c0, 0x0121, 0x3511, 0x3d11, 0xe0c0, 0x0122, 0x3511, 0x3d11,
+	0xe42e, 0xe41e, 0x0cd7, 0x2866, 0xf10a, 0x2a52, 0xa80f, 0xf0db,
+	0xe167, 0x05f2, 0x2117, 0x4d17, 0x2a52, 0xa00f, 0xaf07, 0xae07,
+	0xa103, 0xe042, 0xe41e, 0x0d40, 0x2867, 0xf0ba, 0x2852, 0xa806,
+	0xa106, 0x2a52, 0xa007, 0xaf05, 0xae05, 0xa103, 0xe418, 0x0d0a,
+	0x2852, 0xe0c2, 0x003f, 0xe41e, 0x0cd3, 0xe41e, 0x0cd7, 0xe190,
+	0xe0c0, 0x0118, 0xa802, 0xf78a, 0xe42e, 0xe0c0, 0x011c, 0xf7ea,
+	0xe0c0, 0x011e, 0xe0c2, 0x0114, 0x3000, 0xa804, 0x3c01, 0x2800,
+	0xe0c2, 0x0188, 0xf09a, 0xe0c0, 0x0170, 0x3c02, 0xe0c0, 0x0174,
+	0x3c03, 0xe0c2, 0x0123, 0xe42e, 0x28da, 0xe000, 0x0280, 0xe092,
+	0x2801, 0x4c00, 0x3d11, 0x2802, 0xae10, 0x4c03, 0x3d11, 0x2804,
+	0x3d11, 0xe0c0, 0x0121, 0x3511, 0x3d11, 0xe0c0, 0x0122, 0x3511,
+	0x3d11, 0xe42e, 0x28db, 0xe000, 0x0280, 0xe09a, 0x2915, 0x3054,
+	0xaf02, 0x3055, 0x2905, 0xaf10, 0x3c56, 0x2915, 0xa81e, 0x3c57,
+	0x2915, 0x3c58, 0xe42e, 0x2115, 0x4d15, 0xcf8c, 0x2115, 0x4d15,
+	0xcf8e, 0xe42e, 0xe0c0, 0x018f, 0x3c04, 0xe0c2, 0x0309, 0x28da,
+	0xe000, 0x02c0, 0xe092, 0xe162, 0x0190, 0xe163, 0x03b0, 0xc420,
+	0xd022, 0x0003, 0xe184, 0x0bff, 0x9e12, 0x3511, 0x3d11, 0x9f33,
+	0xe42e, 0x28db, 0xe000, 0x02c0, 0xe092, 0xe005, 0x0080, 0xd022,
+	0x0003, 0xe184, 0x0c0f, 0xcfd5, 0xa011, 0x2111, 0x4d11, 0xcfd6,
+	0xe42e, 0x2864, 0xe0c2, 0x0119, 0x28d2, 0xe0c2, 0x011a, 0x2862,
+	0xe0c2, 0x011b, 0xe42e, 0xa200, 0x3c64, 0xe004, 0x2222, 0x3cd2,
+	0x3c62, 0xe42e, 0x2805, 0x3c59, 0x2a15, 0x4629, 0x282b, 0xe419,
+	0x0e26, 0x3c05, 0x2805, 0x0824, 0xa400, 0xa566, 0xe000, 0x07f0,
+	0xe09c, 0x2906, 0xae0c, 0x4d06, 0xae0c, 0x4c05, 0xe0c2, 0x0115,
+	0xe42e, 0x2829, 0xf09a, 0xe0c0, 0x0414, 0xe418, 0x018c, 0xe0c0,
+	0x0414, 0xe41a, 0x0c87, 0x28d7, 0x2a50, 0xa113, 0xf071, 0x2a50,
+	0xa10d, 0xf037, 0xa402, 0xf02e, 0xa404, 0xe005, 0x0020, 0xe055,
+	0xe0c3, 0x0180, 0xe004, 0x0582, 0x2a3f, 0x46e1, 0x463e, 0xf03b,
+	0xe004, 0x0903, 0xe096, 0x2113, 0x4d13, 0xe0c2, 0x018c, 0x28d8,
+	0xe0c2, 0x018e, 0x28d9, 0xe0c2, 0x018a, 0xa201, 0x283d, 0xa11e,
+	0xa400, 0xa548, 0x3c03, 0xae04, 0xe000, 0x0740, 0xe09e, 0x2917,
+	0xe0c2, 0x0186, 0x2917, 0xe0c2, 0x0185, 0xe0c2, 0x0184, 0x2917,
+	0xe049, 0xae15, 0xe056, 0xae15, 0xe056, 0xe0c2, 0x0181, 0xe0c2,
+	0x0182, 0x2917, 0xae20, 0x4c75, 0xe0c2, 0x0183, 0xe42e, 0xa200,
+	0xe0c2, 0x0150, 0xe0c0, 0x0151, 0xf7e8, 0xe167, 0x01a0, 0x2317,
+	0x4f17, 0xe0c3, 0x0152, 0x2b17, 0xe009, 0x00ff, 0xae21, 0x4f07,
+	0xe0c3, 0x0153, 0xe0c1, 0x0101, 0xe0c3, 0x015d, 0x2add, 0xa53f,
+	0xa401, 0xae21, 0xe167, 0x01a2, 0x2907, 0xaf10, 0xe008, 0x001b,
+	0xe056, 0xe0c2, 0x015c, 0xa202, 0xe0c2, 0x0150, 0xe0c0, 0x0150,
+	0xf7ea, 0xe42e, 0xe004, 0x3211, 0xae20, 0xe00a, 0x2100, 0xe0c2,
+	0x0155, 0xe004, 0x9211, 0xae20, 0xe00a, 0x2100, 0xe0c2, 0x0158,
+	0xe004, 0x1000, 0xae20, 0xe00a, 0x0000, 0xe0c2, 0x0156, 0xe0c2,
+	0x0159, 0xe004, 0x0004, 0xe0c2, 0x0154, 0xe0c2, 0x0157, 0xa202,
+	0xe0c2, 0x015a, 0xe42e, 0xa202, 0xe0c2, 0x0110, 0xe42e, 0xe0c0,
+	0x0111, 0xf7e8, 0xe42e, 0xe0c0, 0x011c, 0xf7ea, 0xe42e, 0x2853,
+	0xa806, 0xae02, 0xe000, 0x05e0, 0xe09e, 0x28db, 0xe000, 0x0280,
+	0xe092, 0x2b11, 0xe01b, 0xae1f, 0xa200, 0xf0c9, 0x28db, 0xe000,
+	0x02c0, 0xe092, 0x2111, 0x4d11, 0xcfd6, 0xe049, 0xaf21, 0xe009,
+	0x7fff, 0x3f17, 0x3d17, 0x2853, 0xa806, 0xa106, 0x3c08, 0xe41a,
+	0x0d0a, 0x2808, 0xe42a, 0x2852, 0x1853, 0xa102, 0xe428, 0xe41e,
+	0x0d0a, 0xe42e, 0xe167, 0x05f6, 0x2117, 0x4d17, 0x2a53, 0xaf05,
+	0xae09, 0xe042, 0xce20, 0xd112, 0x0008, 0xd111, 0x05e0, 0xd113,
+	0x0002, 0xca28, 0xf7f8, 0xe42e, 0x2853, 0xa80e, 0xaf02, 0xe000,
+	0x05e8, 0xe09e, 0xcb94, 0xe008, 0x003f, 0x2a65, 0xae0d, 0xe056,
+	0x2a53, 0xa803, 0xf049, 0xae10, 0x3d07, 0xf06e, 0x2b07, 0xe009,
+	0xff00, 0xe056, 0x3d07, 0x2853, 0xa80e, 0xa10e, 0xe41a, 0x0d39,
+	0xe42e, 0x2853, 0xa10e, 0xe167, 0x05f2, 0x2317, 0x4f17, 0xe042,
+	0xce20, 0xd111, 0x05e8, 0xd112, 0x0004, 0xd113, 0x0002, 0xca28,
+	0xf7f8, 0xe42e, 0x282b, 0xa118, 0xb608, 0xa54e, 0xe000, 0x0830,
+	0xe09c, 0x2906, 0xae04, 0xe0c2, 0x0176, 0xcca4, 0xc786, 0xe018,
+	0xa004, 0xe0c2, 0x0177, 0xe42e, 0x282b, 0xa11e, 0xa400, 0xa548,
+	0xe000, 0x0860, 0xe09c, 0x2906, 0xe0c2, 0x0189, 0xe42e, 0x2829,
+	0xe42a, 0x283e, 0xe428, 0xa202, 0x2a1c, 0xb616, 0xae02, 0x4c1e,
+	0xae20, 0x4c1c, 0xe0c2, 0x0108, 0x20c6, 0x4cc1, 0xe0c2, 0x0109,
+	0x2052, 0x4c1d, 0xe0c2, 0x010a, 0x20c2, 0x4cc3, 0xe0c2, 0x010b,
+	0x20c4, 0x4cc5, 0xe0c2, 0x010c, 0xe42e, 0x2829, 0xe42a, 0x283e,
+	0xe428, 0xe0c0, 0x010b, 0x34c2, 0x3cc3, 0xe0c0, 0x010c, 0x34c4,
+	0x3cc5, 0xe42e, 0xe0c1, 0x0044, 0xa80f, 0xe056, 0xe42e, 0xe0c1,
+	0x0044, 0xaf0d, 0xae03, 0xe056, 0xa87e, 0xe42e, 0xa203, 0xe0c3,
+	0x040d, 0xe0c1, 0x0420, 0xa803, 0xf7db, 0xe166, 0x04c0, 0xe167,
+	0x0500, 0x2832, 0xf1b6, 0xa102, 0xcc44, 0xe184, 0x0dc4, 0xa200,
+	0xe41e, 0x0d92, 0xaf04, 0xe41e, 0x0d97, 0xae20, 0x4c70, 0x9f17,
+	0x2050, 0x4c51, 0xae08, 0x9f17, 0x2116, 0x4d16, 0x9f17, 0x2116,
+	0x4d16, 0x9f17, 0x2116, 0x4d16, 0x9f17, 0xa201, 0xe0c3, 0x040d,
+	0xe42e, 0xe0c0, 0x0044, 0xaf20, 0xa802, 0xe428, 0xe0c0, 0x0060,
+	0xa83e, 0xa203, 0xe0c3, 0x040d, 0xcca4, 0xc785, 0xe018, 0xe000,
+	0x0500, 0xe09e, 0xe0c1, 0x0420, 0xa803, 0xf7db, 0xa200, 0xe41e,
+	0x0d92, 0xaf04, 0xe0c1, 0x0061, 0xaf21, 0xa807, 0xa105, 0xf025,
+	0xe04a, 0xe41e, 0x0d97, 0xe0c1, 0x0044, 0xaf17, 0xa803, 0xe40b,
+	0x0df2, 0xa81e, 0xae20, 0xe0c1, 0x0061, 0xe009, 0x1fff, 0xe056,
+	0x9f17, 0xe0c0, 0x0064, 0xa802, 0xf048, 0x2050, 0x4c51, 0xf03e,
+	0x2051, 0x4c50, 0xae08, 0x9f17, 0xe0c0, 0x006a, 0x9f17, 0xe0c0,
+	0x006b, 0x9f17, 0xe0c0, 0x006c, 0x9f17, 0xa201, 0xe0c3, 0x040d,
+	0xe42e, 0xcca4, 0xc786, 0xe018, 0xe000, 0x04c0, 0xe09c, 0x2116,
+	0x4d06, 0xe42e, 0xe41e, 0x0e32, 0xe42e, 0xe41e, 0x0e93, 0xe42e,
+	0xe41e, 0x0e94, 0xe42e, 0xe41e, 0x0ee5, 0xe42e, 0xe41e, 0x0f1b,
+	0xe42e, 0xe41e, 0x0f7b, 0xe42e, 0xe41e, 0x106a, 0xe42e, 0xe41e,
+	0x10ca, 0xe42e, 0xa254, 0x3ccd, 0xa268, 0x3c83, 0xa218, 0x3c85,
+	0xa266, 0x2ac8, 0xf03b, 0xe0c0, 0x0072, 0x3c84, 0xa210, 0x3c97,
+	0xe004, 0x07e0, 0x3c98, 0x2814, 0x2a52, 0x3c86, 0x3e8b, 0x2c17,
+	0xc710, 0x7c18, 0xe008, 0xffff, 0xa002, 0xaf02, 0x3c88, 0x3cbb,
+	0xe004, 0x6000, 0x2ac7, 0xf03b, 0xe0c0, 0x0073, 0x3c99, 0x2886,
+	0xe016, 0x3c87, 0xf06a, 0x2888, 0x3c86, 0xe004, 0x1000, 0x3c99,
+	0x8418, 0xe182, 0x7530, 0xe018, 0xae02, 0x2e17, 0xe41e, 0x1014,
+	0x3c9e, 0x849e, 0x827f, 0xe018, 0xa279, 0xe41e, 0x0ffd, 0x349e,
+	0x3c9f, 0xae06, 0x2a83, 0xe41e, 0x0ffd, 0x34a4, 0x3ca5, 0xa202,
+	0x3c89, 0xa205, 0x1a36, 0xae03, 0xa011, 0x3e8e, 0x2a8b, 0x5a8e,
+	0xe013, 0x36ae, 0x3eaf, 0x28b9, 0x2ab8, 0xf049, 0xe41e, 0x0fa4,
+	0x64cd, 0x3c8c, 0xa004, 0x6085, 0x6484, 0x3c8d, 0xa200, 0x3ce7,
+	0xe41e, 0x0fc8, 0xe42e, 0xe42e, 0x2829, 0x3c8a, 0xa201, 0x3e92,
+	0x3ecc, 0xe418, 0x0f86, 0xa200, 0x3c93, 0x3c94, 0x288a, 0xf238,
+	0x2889, 0xf05a, 0xa200, 0x3c89, 0x288c, 0xf37e, 0x2886, 0xa102,
+	0xf7ca, 0x2ab8, 0xf03b, 0x288c, 0xf30e, 0x848b, 0x82b5, 0xe019,
+	0xe04a, 0xaf02, 0x00a6, 0x0ca7, 0xe41e, 0x1014, 0xa21f, 0x3e8e,
+	0x2a86, 0xc70f, 0x7e8e, 0xe009, 0xffff, 0xa405, 0xe046, 0x6085,
+	0x64cd, 0xf1be, 0xa200, 0x3ca2, 0x3ca3, 0x2a92, 0xf08b, 0x288d,
+	0x2ae7, 0xf129, 0xa006, 0x2a84, 0xe066, 0xf0ee, 0x28c9, 0x308e,
+	0xaf02, 0x548e, 0xf08a, 0x288d, 0xa104, 0x6090, 0x2a8d, 0xa005,
+	0xe066, 0xf02e, 0x288d, 0x3c90, 0x2a29, 0xf069, 0x2a3f, 0xf039,
+	0x3ce4, 0xf02e, 0x28e4, 0x2a92, 0xe42e, 0xc872, 0xe41e, 0x0fd1,
+	0x288a, 0xf0ea, 0x2093, 0x4c94, 0xc710, 0x7c8b, 0xe008, 0xffff,
+	0xa002, 0xaf02, 0x3c8d, 0x2093, 0x4c94, 0x00a6, 0x0ca7, 0x34a6,
+	0x3ca7, 0x28b5, 0xa002, 0x3cb5, 0x288a, 0xf028, 0x3cb5, 0x288a,
+	0xf0f8, 0x2a86, 0xa103, 0x2095, 0x4c96, 0xe41e, 0x0ffd, 0x34ac,
+	0x3cad, 0x1095, 0x1c96, 0xe012, 0x34aa, 0x3cab, 0xf0ae, 0x22aa,
+	0x4eab, 0x12ac, 0x1ead, 0x2887, 0xb606, 0xb611, 0x36aa, 0x3eab,
+	0x2892, 0x3ce7, 0xe42e, 0x28c9, 0xf08a, 0x2852, 0x1853, 0xa102,
+	0xf048, 0x2805, 0xe40e, 0x0f70, 0x22a2, 0x4ea3, 0x20a4, 0x4ca5,
+	0xe041, 0xf0c7, 0xe045, 0xe045, 0x2890, 0xf0f5, 0x36a2, 0x3ea3,
+	0xa002, 0x6085, 0x6484, 0x3c90, 0xf08e, 0x36a2, 0x3ea3, 0x2890,
+	0xa102, 0x6085, 0x6484, 0x3c90, 0x2890, 0x6085, 0x6484, 0x3c90,
+	0x2ac9, 0x28cc, 0xa002, 0x3ccc, 0xf08b, 0xa103, 0xf22b, 0xa103,
+	0xf07b, 0xa103, 0xf0ab, 0xf24e, 0x2890, 0xe40e, 0x0f70, 0x28cb,
+	0xf18a, 0xa200, 0x3ccb, 0xf06e, 0x28cc, 0x18ca, 0xf124, 0xa200,
+	0x3ccc, 0x2853, 0xa002, 0xf046, 0xcb97, 0xcb96, 0xf03e, 0x2a2b,
+	0x282b, 0xa105, 0x6290, 0xa004, 0xe066, 0x3c90, 0x3c8e, 0xf08e,
+	0xcb96, 0x3c8e, 0x2853, 0xa002, 0xf030, 0x282b, 0x3c8e, 0x288e,
+	0x2a3d, 0xe045, 0xf053, 0x2a3d, 0xa007, 0xe066, 0xe42e, 0x2a3d,
+	0xa107, 0xe062, 0xe42e, 0x0093, 0x0c94, 0x3493, 0x3c94, 0x285f,
+	0x189a, 0x00a2, 0x0ca3, 0x34a2, 0x3ca3, 0xe42e, 0x20aa, 0x4cab,
+	0x1095, 0x1c96, 0x8499, 0xe41e, 0x104b, 0x009e, 0x0c9f, 0xf052,
+	0x2a91, 0xf039, 0xa203, 0x3e92, 0xe41e, 0x0fe3, 0x229e, 0x4e9f,
+	0xaf07, 0xe062, 0x34a0, 0x3ca1, 0xc710, 0x7c8b, 0xe008, 0xffff,
+	0xa002, 0xaf02, 0x3c9a, 0xe42e, 0x8486, 0x209e, 0x4c9f, 0xe41e,
+	0x103f, 0x8497, 0xe41e, 0x103f, 0x2a86, 0xa103, 0x0a97, 0xe41e,
+	0x0ffd, 0x34a0, 0x3ca1, 0x288b, 0x3cb0, 0x20a0, 0x4ca1, 0xae04,
+	0x00a0, 0x0ca1, 0xae02, 0xc70f, 0x7cb0, 0xe008, 0xffff, 0xaf08,
+	0xa010, 0xaf08, 0x0836, 0xa51e, 0x0898, 0xe09e, 0x2907, 0xe42e,
+	0x847f, 0x8280, 0xe018, 0x34a8, 0x3ca9, 0xa200, 0x3495, 0x3c96,
+	0xe42e, 0x109e, 0x1c9f, 0x0095, 0x0c96, 0xa27f, 0xae31, 0xe066,
+	0x3495, 0x3c96, 0x22ae, 0x4eaf, 0xe046, 0xf032, 0x3695, 0x3e96,
+	0x2095, 0x2896, 0xe42e, 0x2a80, 0xe42b, 0x22a8, 0x4ea9, 0x1295,
+	0x1e96, 0xe066, 0xf051, 0x2a91, 0xf039, 0xa203, 0x3e92, 0x2281,
+	0x4e82, 0xe42b, 0x22a8, 0x4ea9, 0x1295, 0x1e96, 0x029e, 0x0e9f,
+	0x1281, 0x1e82, 0xa401, 0xe062, 0xe42e, 0x3eb0, 0xa201, 0xf032,
+	0xe012, 0xa203, 0x3eb4, 0x3cb1, 0xaf20, 0xc70f, 0x7cb0, 0x3cb2,
+	0xaf20, 0xae20, 0x4cb1, 0xc70f, 0x7cb0, 0x3cb3, 0x20b2, 0x4cb3,
+	0x2ab4, 0xe42b, 0xe012, 0xe42e, 0x36b0, 0x3eb1, 0xa201, 0x3eb2,
+	0x22b0, 0x4eb1, 0x5ab2, 0xe045, 0xf061, 0x2ab2, 0xa003, 0x3eb2,
+	0xa121, 0xf775, 0x2ab2, 0xf039, 0xa200, 0xe42e, 0xa103, 0x3eb2,
+	0xcc45, 0xa201, 0x3eb3, 0xe184, 0x103c, 0x2ab3, 0xae03, 0x3eb3,
+	0x22b0, 0x4eb1, 0x5ab2, 0xe045, 0xf061, 0xe013, 0xe04a, 0x2ab3,
+	0xa003, 0x3eb3, 0x2ab2, 0xa103, 0x3eb2, 0x28b3, 0xe42e, 0xae02,
+	0x34b1, 0xe008, 0xffff, 0xaf02, 0x3cb0, 0x82b1, 0xe018, 0xae1e,
+	0x82b0, 0xe01c, 0xe42e, 0xae02, 0x34b1, 0xe008, 0xffff, 0xaf02,
+	0x3cb0, 0x82b0, 0xe018, 0xaf1e, 0x82b1, 0xe01c, 0xe42e, 0xae02,
+	0x34b1, 0xe008, 0xffff, 0xaf02, 0x3cb0, 0x82b1, 0xe018, 0xa103,
+	0x3eb2, 0x58b2, 0x82b0, 0xa11f, 0xe013, 0x3eb2, 0xe019, 0x5eb2,
+	0xe042, 0xe42e, 0x34bd, 0x3cbc, 0x28bc, 0xae02, 0x3cbc, 0x28bd,
+	0xa002, 0x3cbd, 0x2cbc, 0xc710, 0x7cbd, 0xe008, 0xffff, 0xa002,
+	0xaf02, 0x3c88, 0x18bb, 0xe42a, 0x2888, 0x3cbb, 0x28bc, 0x2abd,
+	0x3c17, 0x3e18, 0x8418, 0xe182, 0x7530, 0xe018, 0xae02, 0x2e17,
+	0xe41e, 0x1014, 0x3c9e, 0x849e, 0x827f, 0xe018, 0xa279, 0xe41e,
+	0x0ffd, 0x349e, 0x3c9f, 0xae06, 0x2a83, 0xe41e, 0x0ffd, 0x34a4,
+	0x3ca5, 0xa200, 0x3cb5, 0x34a6, 0x3ca7, 0x2886, 0xe428, 0xe016,
+	0x3c87, 0x2888, 0x3c86, 0xe42e, 0x3cb7, 0x2a86, 0xe046, 0xf028,
+	0xe42e, 0x28b6, 0x2ab7, 0xe046, 0xf034, 0xa200, 0x3cb6, 0x28b7,
+	0x3c86, 0x3c14, 0x2815, 0xe42a, 0x2886, 0xe016, 0x3c87, 0xf03a,
+	0x2a88, 0x3e86, 0x2a86, 0x28b6, 0xe045, 0xf0c6, 0x2095, 0x4c96,
+	0xe41e, 0x0ffd, 0x34ac, 0x3cad, 0x1095, 0x1c96, 0xe012, 0x34aa,
+	0x3cab, 0xe42e, 0x3cba, 0x2815, 0xe42a, 0x287f, 0x2aba, 0xe046,
+	0xe42a, 0x3e7f, 0x8418, 0xe182, 0x7530, 0xe018, 0xae02, 0x2e17,
+	0xe41e, 0x1014, 0x3c9e, 0x849e, 0x827f, 0xe018, 0xa279, 0xe41e,
+	0x0ffd, 0x349e, 0x3c9f, 0xae06, 0x2a83, 0xe41e, 0x0ffd, 0x34a4,
+	0x3ca5, 0xa200, 0x3cb5, 0x34a6, 0x3ca7, 0xe42e, 0x2a15, 0xe42b,
+	0xf042, 0xa201, 0x3eb8, 0xe42e, 0x3cb9, 0x3c8c, 0xa203, 0x3eb8,
+	0xe42e, 0xe0c1, 0x0060, 0xa803, 0xf05b, 0xe0c0, 0x0061, 0xe41e,
+	0x10a4, 0xe0c1, 0x0060, 0xa805, 0xf05b, 0xe0c0, 0x0062, 0xe41e,
+	0x10ee, 0xe0c1, 0x0060, 0xa809, 0xf05b, 0xe0c0, 0x0063, 0xe41e,
+	0x0e2f, 0xe0c1, 0x0060, 0xa811, 0xf05b, 0xe0c0, 0x0064, 0xe41e,
+	0x0e2c, 0xe0c1, 0x0060, 0xa821, 0xf04b, 0xe0c0, 0x0065, 0x3c1c,
+	0xe0c1, 0x0060, 0xa841, 0xf08b, 0xe0c0, 0x0066, 0x3038, 0xaf02,
+	0x3039, 0xaf02, 0x3c3a, 0xe42e, 0xa200, 0x3c63, 0x3cd3, 0x3c64,
+	0xe42e, 0xe161, 0x0200, 0xe004, 0x2222, 0xe188, 0x007f, 0x3d11,
+	0xe190, 0xe42e, 0xf149, 0x2a63, 0x28d3, 0xe000, 0x0200, 0xe09c,
+	0x2906, 0x3c62, 0xf089, 0xe004, 0x2222, 0x3cd2, 0xe0c0, 0x0173,
+	0x3506, 0xf05e, 0xe0c0, 0x0173, 0x3506, 0x3cd2, 0x28d3, 0xa002,
+	0x3cd3, 0xa002, 0x1850, 0xe428, 0x3cd3, 0xe42e, 0xa200, 0x3cc2,
+	0x3cc4, 0x3cc5, 0xe161, 0x0905, 0x3d11, 0x8111, 0x3d11, 0x3d11,
+	0xe42e, 0xa200, 0x3c1d, 0xe42e, 0x2a3e, 0xa200, 0xe429, 0x281e,
+	0xf208, 0x281d, 0x181c, 0xf3f2, 0x2853, 0xa006, 0x18c2, 0xf3b4,
+	0x28c2, 0x08c1, 0x18c6, 0xf0b4, 0x28c4, 0xa002, 0xc70f, 0x7cc1,
+	0xaf20, 0x3cc4, 0x3cc2, 0x281c, 0x3c1d, 0xf2be, 0x281d, 0xa002,
+	0x3c1d, 0x28c2, 0x08c1, 0xc70f, 0x7cc6, 0xaf20, 0x3cc2, 0xf21e,
+	0x281d, 0x181c, 0xf202, 0x2853, 0xa006, 0x18c3, 0xf1c4, 0x28c3,
+	0x08c1, 0x1852, 0xf0c4, 0x28c5, 0xa002, 0xc70f, 0x7cc1, 0xaf20,
+	0x3cc5, 0x08c6, 0x3cc3, 0x281c, 0x3c1d, 0xf0be, 0x281d, 0xa002,
+	0x3c1d, 0x28c3, 0x08c1, 0xc70f, 0x7c52, 0xaf20, 0x3cc3, 0xf01e,
+	0xa202, 0xe42e, 0xa200, 0xe42e, 0xa200, 0x3c4d, 0xe0c0, 0x0060,
+	0x344a, 0x3c4b, 0x347c, 0x3c7d, 0xe0c0, 0x0061, 0xae04, 0x3c4c,
+	0xe41e, 0x11cd, 0xe42e, 0xd030, 0x0000, 0xd034, 0x0000, 0xd033,
+	0x0000, 0xd035, 0x0000, 0xd036, 0x00ff, 0xd037, 0x0080, 0xd038,
+	0x0000, 0xa200, 0x3c49, 0xe42e, 0xe470, 0x204a, 0x4c4b, 0x2e4d,
+	0xae11, 0xe042, 0xe0c2, 0x0049, 0x347c, 0x3c7d, 0xe42e, 0xd071,
+	0x242a, 0xe181, 0xa200, 0x34df, 0x3ce0, 0xe004, 0x0200, 0x3cf3,
+	0x3cf6, 0xe41e, 0x1293, 0xe41e, 0x12af, 0xe41e, 0x12cc, 0xe41e,
+	0x12f0, 0xe41e, 0x12fb, 0xe42e, 0xe41e, 0x1217, 0xe41e, 0x1233,
+	0xca48, 0xaf3c, 0xa802, 0xf05a, 0xa202, 0x3cf4, 0xae3c, 0xce48,
+	0xca48, 0xaf38, 0xa802, 0xf0aa, 0xe41e, 0x1206, 0xe41e, 0x12f0,
+	0xa202, 0xae38, 0xce48, 0xe41e, 0x12fb, 0xe470, 0x247c, 0x4c7d,
+	0x264a, 0x4e4b, 0xe046, 0x2e4c, 0xae11, 0xe045, 0xe425, 0x28f3,
+	0xe045, 0xf043, 0xe041, 0x3ef6, 0xe42e, 0x3cf6, 0xe42e, 0xca55,
+	0x28f6, 0xf048, 0xa200, 0xceaa, 0xf04e, 0x20df, 0x4ce0, 0xe045,
+	0x247c, 0x4c7d, 0xe042, 0x347c, 0x3c7d, 0x28f6, 0xe42a, 0x24df,
+	0x4ce0, 0xe042, 0x34df, 0x3ce0, 0x2af6, 0xe046, 0xe428, 0xa200,
+	0x34df, 0x3ce0, 0xe42e, 0xa200, 0x3c4f, 0x247c, 0x4c7d, 0x264a,
+	0x4e4b, 0xe046, 0xe049, 0xaf10, 0x3c4d, 0x2c4c, 0xae10, 0xe045,
+	0xf275, 0x28bf, 0xf1fa, 0xa202, 0xe0c2, 0x0074, 0x247c, 0x4c7d,
+	0xe0c2, 0x0049, 0x2ace, 0xf16b, 0xe0c0, 0x005c, 0xe008, 0x8000,
+	0xf11a, 0xe0c0, 0x005d, 0xe00a, 0x8000, 0xe0c2, 0x005d, 0xa202,
+	0xce00, 0xe0c1, 0x005d, 0xe009, 0x8000, 0xf7c9, 0xe0c0, 0x0004,
+	0xf798, 0xa200, 0x3c4d, 0x264a, 0x4e4b, 0x367c, 0x3e7d, 0x267c,
+	0x4e7d, 0xe0c3, 0x0049, 0x28bf, 0xe428, 0xd027, 0x0000, 0xe41e,
+	0x1274, 0xd027, 0x0001, 0xe42e, 0xe0c0, 0x0048, 0xe0c1, 0x0049,
+	0xe046, 0xf040, 0x2e4c, 0xae11, 0xe042, 0xe005, 0x0200, 0xe046,
+	0xe420, 0x284f, 0xf728, 0xe0c0, 0x005c, 0xe008, 0x8000, 0xf6da,
+	0xe0c0, 0x005d, 0xe00a, 0x8000, 0xe0c2, 0x005d, 0xa202, 0xce00,
+	0x3c4f, 0xf63e, 0xe42e, 0xa220, 0xa20d, 0xe056, 0xa203, 0xe056,
+	0xae20, 0xcc9e, 0xd030, 0x0000, 0xd033, 0x0000, 0xd034, 0x0000,
+	0xd035, 0x0000, 0xd036, 0x00ff, 0xd037, 0x0080, 0xd038, 0x0000,
+	0xd039, 0x0000, 0xd046, 0x0000, 0xd047, 0x0000, 0xe42e, 0xe0c0,
+	0x0043, 0xaf0c, 0x30ce, 0xa202, 0xae0e, 0xe0c1, 0x0043, 0xa807,
+	0xae09, 0xe056, 0xce4e, 0xa222, 0xae28, 0xa217, 0xae37, 0xe056,
+	0xce4c, 0xa200, 0xce54, 0xa206, 0xae38, 0xe005, 0x0003, 0xe056,
+	0xce4a, 0xa200, 0xce58, 0xe42e, 0xe0c0, 0x005b, 0xa110, 0xf04a,
+	0xa106, 0xf05a, 0xe42e, 0xe004, 0x0038, 0xf03e, 0xe004, 0x0020,
+	0xe005, 0x0080, 0xe056, 0xe005, 0x1800, 0xe056, 0xcec0, 0xa208,
+	0xcec8, 0xa200, 0xce92, 0xce9e, 0xce88, 0xce8a, 0xced0, 0xced6,
+	0xcea4, 0xcec6, 0xa202, 0xce9c, 0xe004, 0x0200, 0xce96, 0xe42e,
+	0xa206, 0x2af6, 0xae11, 0xe056, 0xce5a, 0x247c, 0x4c7d, 0xce5c,
+	0xa200, 0xce5e, 0xe42e, 0xe004, 0x0f00, 0xae20, 0xe005, 0x0003,
+	0xe056, 0xe005, 0x0030, 0xe056, 0xca49, 0xaf21, 0xa803, 0xf04b,
+	0xa203, 0xae2f, 0xe056, 0xce4a, 0xe42e, 0xc872, 0xa050, 0xcc72,
+	0xa200, 0xe41e, 0x135d, 0xa200, 0xe41e, 0x135d, 0xa200, 0xe41e,
+	0x135d, 0xa202, 0xe41e, 0x135d, 0xa200, 0xce96, 0xceaa, 0x282f,
+	0xae0a, 0x4c30, 0xe41e, 0x135d, 0x2830, 0xa11c, 0xf05a, 0x2830,
+	0xa128, 0xf02a, 0xf2be, 0xc872, 0xa030, 0xcc72, 0xa200, 0xae02,
+	0x2a31, 0xb436, 0xae0c, 0xa900, 0xae14, 0x2a30, 0xa11d, 0xb432,
+	0xae06, 0xa900, 0xae02, 0x4c3e, 0xae02, 0x2a3f, 0xe017, 0x463e,
+	0x46e1, 0xb432, 0xae02, 0xa902, 0x3c07, 0xaf20, 0xe008, 0x00ff,
+	0xe41e, 0x135d, 0x2807, 0xaf10, 0xe008, 0x00ff, 0xe41e, 0x135d,
+	0x2807, 0xe008, 0x00ff, 0xe41e, 0x135d, 0xe41e, 0x11bb, 0xa200,
+	0xce92, 0xe42e, 0xca9b, 0xf7f9, 0xe42e, 0xe41e, 0x135a, 0xcec4,
+	0xe42e, 0xca48, 0xa802, 0xf7e8, 0xca4c, 0xa802, 0xf7ea, 0xe42e,
+	0xe41e, 0x1361, 0xe41e, 0x135a, 0xa200, 0x3cf4, 0xe004, 0x0030,
+	0xce98, 0x28f4, 0xf7fa, 0xe42e, 0xe082, 0x3c4e, 0xe161, 0x0180,
+	0xca80, 0x3511, 0x3d11, 0xca82, 0x3511, 0x3d11, 0xca84, 0x3511,
+	0x3d11, 0xca86, 0x3511, 0x3d11, 0x8b11, 0x0144, 0x8b11, 0x0145,
+	0x8b11, 0x0148, 0x8b11, 0x0149, 0x8b11, 0x014a, 0x8b11, 0x014b,
+	0x8b11, 0x0160, 0x8b11, 0x014e, 0x8b11, 0x014f, 0x8b11, 0x0152,
+	0x8b11, 0x0153, 0x8b11, 0x0155, 0x8b11, 0x0157, 0x8b11, 0x0163,
+	0x8b11, 0x0164, 0x8b11, 0x0165, 0xcacc, 0x3511, 0x3d11, 0xcace,
+	0x3511, 0x3d11, 0x8b11, 0x0168, 0xcad2, 0x3511, 0x3d11, 0xcad4,
+	0x3511, 0x3d11, 0x8b11, 0x016b, 0x8b11, 0x016c, 0x8b11, 0x016d,
+	0x8b11, 0x016e, 0xc860, 0x3511, 0x3d11, 0xc862, 0x3511, 0x3d11,
+	0xc864, 0x3511, 0x3d11, 0x8b11, 0x0033, 0x8b11, 0x0034, 0x8b11,
+	0x0035, 0x8b11, 0x0036, 0x8b11, 0x0037, 0x8b11, 0x0038, 0xc872,
+	0x3511, 0x3d11, 0x8b11, 0x003a, 0xc87a, 0x3511, 0x3d11, 0xc87c,
+	0x3511, 0x3d11, 0xc880, 0x3511, 0x3d11, 0xc882, 0x3511, 0x3d11,
+	0xc884, 0x3511, 0x3d11, 0xc886, 0x3511, 0x3d11, 0xc888, 0x3511,
+	0x3d11, 0xc88a, 0x3511, 0x3d11, 0xc88c, 0x3511, 0x3d11, 0xc890,
+	0x3511, 0x3d11, 0xc892, 0x3511, 0x3d11, 0xc894, 0x3511, 0x3d11,
+	0xc896, 0x3511, 0x3d11, 0xc898, 0x3511, 0x3d11, 0xc89e, 0x3511,
+	0x3d11, 0x284e, 0xe092, 0xe42e, 0xe082, 0x3c4e, 0xe161, 0x0180,
+	0x2111, 0x4d11, 0xce80, 0x2111, 0x4d11, 0xce82, 0x2111, 0x4d11,
+	0xce84, 0x2111, 0x4d11, 0xce86, 0x8911, 0x0144, 0x8911, 0x0145,
+	0x8911, 0x0148, 0x8911, 0x0149, 0x8911, 0x014a, 0x8911, 0x014b,
+	0x8911, 0x0160, 0x8911, 0x014e, 0x8911, 0x014f, 0x8911, 0x0152,
+	0x8911, 0x0153, 0x8911, 0x0155, 0x8911, 0x0157, 0x8911, 0x0163,
+	0x8911, 0x0164, 0x8911, 0x0165, 0x2111, 0x4d11, 0xcecc, 0x2111,
+	0x4d11, 0xcece, 0x8911, 0x0168, 0x2111, 0x4d11, 0xced2, 0x2111,
+	0x4d11, 0xced4, 0x8911, 0x016b, 0x8911, 0x016c, 0x8911, 0x016d,
+	0x8911, 0x016e, 0x2111, 0x4d11, 0xcc60, 0x2111, 0x4d11, 0xcc62,
+	0x2111, 0x4d11, 0xcc64, 0x8911, 0x0033, 0x8911, 0x0034, 0x8911,
+	0x0035, 0x8911, 0x0036, 0x8911, 0x0037, 0x8911, 0x0038, 0x2111,
+	0x4d11, 0xcc72, 0x8911, 0x003a, 0x2111, 0x4d11, 0xcc7a, 0x2111,
+	0x4d11, 0xcc7c, 0x2111, 0x4d11, 0xcc80, 0x2111, 0x4d11, 0xcc82,
+	0x2111, 0x4d11, 0xcc84, 0x2111, 0x4d11, 0xcc86, 0x2111, 0x4d11,
+	0xcc88, 0x2111, 0x4d11, 0xcc8a, 0x2111, 0x4d11, 0xcc8c, 0x2111,
+	0x4d11, 0xcc90, 0x2111, 0x4d11, 0xcc92, 0x2111, 0x4d11, 0xcc94,
+	0x2111, 0x4d11, 0xcc96, 0x2111, 0x4d11, 0xcc98, 0x2111, 0x4d11,
+	0xe005, 0x1415, 0xae21, 0xe056, 0xcc9e, 0xd14c, 0x0002, 0x284e,
+	0xe092, 0xe42e, 0xe082, 0x3c4e, 0xe161, 0x0180, 0xc872, 0x3511,
+	0x3d11, 0xcac6, 0x3cfa, 0x3d11, 0xf07a, 0xcacc, 0x3511, 0x3d11,
+	0xcace, 0x3511, 0x3d11, 0x284e, 0xe092, 0xe42e, 0x2afa, 0xe42b,
+	0x247c, 0x4c7d, 0xe046, 0x347c, 0x3c7d, 0xe42e, 0xe082, 0x3c4e,
+	0xe161, 0x0180, 0x2111, 0x4d11, 0xcc72, 0x2b11, 0xf15b, 0x2901,
+	0xaf10, 0xe008, 0x00ff, 0xe41e, 0x135d, 0x28fa, 0xa102, 0xf0ca,
+	0x3cfa, 0x2911, 0xe008, 0x00ff, 0xe41e, 0x135d, 0x28fa, 0xa102,
+	0xf03a, 0x3cfa, 0xf6de, 0x284e, 0xe092, 0xe42e, 0xa200, 0x3c3f,
+	0xe42e, 0xe163, 0x0035, 0xe164, 0x0900, 0xa202, 0xe41e, 0x151c,
+	0xe163, 0x0580, 0xe164, 0x0901, 0xa208, 0xe41e, 0x151c, 0xe163,
+	0x00c2, 0xe164, 0x0905, 0xa208, 0xe41e, 0x151c, 0x283f, 0xaa02,
+	0x3c3f, 0xe42e, 0xa202, 0xbbfc, 0xa200, 0xbbfc, 0xa202, 0xbbfc,
+	0x28e1, 0xf06a, 0xa202, 0xbbfc, 0xa200, 0xbbfc, 0xf03e, 0xa200,
+	0xbbfc, 0xa200, 0xbbfc, 0xbbfc, 0xbbfc, 0xbbfc, 0x28e3, 0xba8e,
+	0xa200, 0xbbfc, 0xbac2, 0xa202, 0xbbfc, 0xa200, 0xbbfc, 0xa202,
+	0xbbfc, 0xbbfc, 0xe42e, 0x283f, 0xe428, 0xa21c, 0x3c30, 0xe41e,
+	0x130d, 0xe41e, 0x1368, 0xe42e, 0xa102, 0xcc44, 0xe184, 0x1523,
+	0x2d03, 0x2f04, 0x3d14, 0x3f13, 0xe42e, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
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+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
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+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+	0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190, 0xe190,
+};
+
+#endif //__CODA960_FW_H__
+
diff --git a/board/rda/common/include/coda960_regs.h b/board/rda/common/include/coda960_regs.h
new file mode 100644
index 0000000000..a52a983d9a
--- /dev/null
+++ b/board/rda/common/include/coda960_regs.h
@@ -0,0 +1,544 @@
+//--=========================================================================--
+//  This file is a part of VPU Reference API project
+//-----------------------------------------------------------------------------
+//
+//       This confidential and proprietary software may be used only
+//     as authorized by a licensing agreement from Chips&Media Inc.
+//     In the event of publication, the following notice is applicable:
+//
+//            (C) COPYRIGHT 2006 - 2011  CHIPS&MEDIA INC.
+//                      ALL RIGHTS RESERVED
+//
+//       The entire notice above must be reproduced on all authorized
+//       copies.
+//
+//--=========================================================================--
+
+#ifndef __CODA960_REGS_H__
+#define __CODA960_REGS_H__
+
+//------------------------------------------------------------------------------
+// REGISTER BASE
+//------------------------------------------------------------------------------
+#define BIT_BASE            0x0000
+#define GDMA_BASE          	0x1000
+#define MBC_BASE            0x0400
+#define ME_BASE				0x0600
+#define MC_BASE				0x0C00
+#define DMAC_BASE			0x2000
+
+#define BW_BASE             0x03000000
+//------------------------------------------------------------------------------
+// HARDWARE REGISTER
+//------------------------------------------------------------------------------
+#define BIT_CODE_RUN                (BIT_BASE + 0x000)
+#define BIT_CODE_DOWN               (BIT_BASE + 0x004)
+#define BIT_INT_REQ                 (BIT_BASE + 0x008)
+#define BIT_INT_CLEAR               (BIT_BASE + 0x00C)
+#define BIT_INT_STS					(BIT_BASE + 0x010)
+#define BIT_CODE_RESET				(BIT_BASE + 0x014)
+#define BIT_CUR_PC                  (BIT_BASE + 0x018)
+#define BIT_SW_RESET				(BIT_BASE + 0x024)
+#define BIT_SW_RESET_STATUS			(BIT_BASE + 0x034)
+
+//------------------------------------------------------------------------------
+// GLOBAL REGISTER
+//------------------------------------------------------------------------------
+#define BIT_CODE_BUF_ADDR           (BIT_BASE + 0x100)
+#define BIT_WORK_BUF_ADDR           (BIT_BASE + 0x104)
+#define BIT_PARA_BUF_ADDR           (BIT_BASE + 0x108)
+#define BIT_BIT_STREAM_CTRL         (BIT_BASE + 0x10C)
+#define BIT_FRAME_MEM_CTRL          (BIT_BASE + 0x110)
+#define	BIT_BIT_STREAM_PARAM		(BIT_BASE + 0x114)
+#define	BIT_TEMP_BUF_ADDR			(BIT_BASE + 0x118)
+
+#define BIT_RD_PTR					(BIT_BASE + 0x120)
+#define BIT_WR_PTR					(BIT_BASE + 0x124)
+
+#define BIT_ROLLBACK_STATUS			(BIT_BASE + 0x128)	// internal used in f/w.
+
+#define BIT_AXI_SRAM_USE            (BIT_BASE + 0x140)
+#define BIT_BYTE_POS_FRAME_START    (BIT_BASE + 0x144)
+#define BIT_BYTE_POS_FRAME_END		(BIT_BASE + 0x148)
+#define BIT_FRAME_CYCLE             (BIT_BASE + 0x14C)
+
+#define	BIT_FRM_DIS_FLG				(BIT_BASE + 0x150)
+
+#define BIT_BUSY_FLAG               (BIT_BASE + 0x160)
+#define BIT_RUN_COMMAND             (BIT_BASE + 0x164)
+#define BIT_RUN_INDEX               (BIT_BASE + 0x168)
+#define BIT_RUN_COD_STD             (BIT_BASE + 0x16C)
+#define BIT_INT_ENABLE              (BIT_BASE + 0x170)
+#define BIT_INT_REASON              (BIT_BASE + 0x174)
+#define BIT_RUN_AUX_STD             (BIT_BASE + 0x178)
+
+// MSG REGISTER ADDRESS changed
+#define BIT_MSG_0                   (BIT_BASE + 0x130)
+#define BIT_MSG_1                   (BIT_BASE + 0x134)
+#define BIT_MSG_2                   (BIT_BASE + 0x138)
+#define BIT_MSG_3                   (BIT_BASE + 0x13C)
+
+#define MBC_BUSY                	(MBC_BASE + 0x040)
+#define MC_BUSY                 	(MC_BASE + 0x004)
+
+//------------------------------------------------------------------------------
+// [ENC SEQ INIT] COMMAND
+//------------------------------------------------------------------------------
+#define CMD_ENC_SEQ_BB_START        (BIT_BASE + 0x180)
+#define CMD_ENC_SEQ_BB_SIZE         (BIT_BASE + 0x184)
+#define CMD_ENC_SEQ_OPTION          (BIT_BASE + 0x188)          // HecEnable,ConstIntraQp, FMO, QPREP, AUD, SLICE, MB BIT
+#define CMD_ENC_SEQ_COD_STD         (BIT_BASE + 0x18C)
+#define CMD_ENC_SEQ_SRC_SIZE        (BIT_BASE + 0x190)
+#define CMD_ENC_SEQ_SRC_F_RATE      (BIT_BASE + 0x194)
+#define CMD_ENC_SEQ_MP4_PARA        (BIT_BASE + 0x198)
+#define CMD_ENC_SEQ_263_PARA        (BIT_BASE + 0x19C)
+#define CMD_ENC_SEQ_264_PARA        (BIT_BASE + 0x1A0)
+#define CMD_ENC_SEQ_SLICE_MODE      (BIT_BASE + 0x1A4)
+#define CMD_ENC_SEQ_GOP_NUM         (BIT_BASE + 0x1A8)
+#define CMD_ENC_SEQ_RC_PARA         (BIT_BASE + 0x1AC)
+#define CMD_ENC_SEQ_RC_BUF_SIZE     (BIT_BASE + 0x1B0)
+#define CMD_ENC_SEQ_INTRA_REFRESH   (BIT_BASE + 0x1B4)
+#define CMD_ENC_SEQ_INTRA_QP		(BIT_BASE + 0x1C4)
+#define CMD_ENC_SEQ_RC_QP_MAX			(BIT_BASE + 0x1C8)
+#define CMD_ENC_SEQ_RC_GAMMA			(BIT_BASE + 0x1CC)
+#define CMD_ENC_SEQ_RC_INTERVAL_MODE	(BIT_BASE + 0x1D0)		// mbInterval[32:2], rcIntervalMode[1:0]
+#define CMD_ENC_SEQ_INTRA_WEIGHT		(BIT_BASE + 0x1D4)
+#define CMD_ENC_SEQ_ME_OPTION			(BIT_BASE + 0x1D8)
+#define CMD_ENC_SEQ_RC_PARA2			(BIT_BASE + 0x1DC)
+#define CMD_ENC_SEQ_QP_RANGE_SET		(BIT_BASE + 0x1E0)
+#define CMD_ENC_SEQ_RC_MAX_INTRA_SIZE   (BIT_BASE + 0x1F0)
+
+#define CMD_ENC_SEQ_FIRST_MBA           (BIT_BASE + 0x1E4)
+#define CMD_ENC_SEQ_HEIGHT_IN_MAP_UNITS (BIT_BASE + 0x1E8)
+#define CMD_ENC_SEQ_OVERLAP_CLIP_SIZE   (BIT_BASE + 0x1EC)
+
+//------------------------------------------------------------------------------
+// [ENC SEQ END] COMMAND
+//------------------------------------------------------------------------------
+#define RET_ENC_SEQ_END_SUCCESS         (BIT_BASE + 0x1C0)
+//------------------------------------------------------------------------------
+// [ENC PIC RUN] COMMAND
+//------------------------------------------------------------------------------
+
+#define CMD_ENC_PIC_SRC_INDEX       (BIT_BASE + 0x180)
+#define CMD_ENC_PIC_SRC_STRIDE      (BIT_BASE + 0x184)
+#define CMD_ENC_PIC_SRC_ADDR_Y		(BIT_BASE + 0x1A8)
+#define CMD_ENC_PIC_SRC_ADDR_CB		(BIT_BASE + 0x1AC)
+#define CMD_ENC_PIC_SRC_ADDR_CR		(BIT_BASE + 0x1B0)
+#define CMD_ENC_PIC_QS              (BIT_BASE + 0x18C)
+#define CMD_ENC_PIC_ROT_MODE        (BIT_BASE + 0x190)
+#define CMD_ENC_PIC_OPTION          (BIT_BASE + 0x194)
+#define CMD_ENC_PIC_BB_START        (BIT_BASE + 0x198)
+#define CMD_ENC_PIC_BB_SIZE        	(BIT_BASE + 0x19C)
+#define CMD_ENC_PIC_PARA_BASE_ADDR	(BIT_BASE + 0x1A0)
+#define CMD_ENC_PIC_SUB_FRAME_SYNC  (BIT_BASE + 0x1A4)
+
+
+
+#define RET_ENC_PIC_FRAME_NUM       (BIT_BASE + 0x1C0)
+#define RET_ENC_PIC_TYPE            (BIT_BASE + 0x1C4)
+#define RET_ENC_PIC_FRAME_IDX       (BIT_BASE + 0x1C8)
+#define RET_ENC_PIC_SLICE_NUM       (BIT_BASE + 0x1CC)
+#define RET_ENC_PIC_FLAG			(BIT_BASE + 0x1D0)
+#define RET_ENC_PIC_SUCCESS         (BIT_BASE + 0x1D8)
+
+//------------------------------------------------------------------------------
+// [ENC ROI INIT] COMMAND
+//------------------------------------------------------------------------------
+#define CMD_ENC_ROI_MODE            (BIT_BASE + 0x180)      // [1]: RoiType, [0]: RoiEn
+#define CMD_ENC_ROI_NUM             (BIT_BASE + 0x184)      // [3:0] RoiNum
+
+#define CMD_ENC_ROI_POS_0           (BIT_BASE + 0x188)      // [31:24]: MbyEnd, [23:16]: MbyStart, [15:8]: MbxEnd, [7:0]: MbxStart
+#define CMD_ENC_ROI_QP_0            (BIT_BASE + 0x18C)      // [05:04]: RoiQp
+#define CMD_ENC_ROI_POS_1           (BIT_BASE + 0x190)
+#define CMD_ENC_ROI_QP_1            (BIT_BASE + 0x194)
+#define CMD_ENC_ROI_POS_2           (BIT_BASE + 0x198)
+#define CMD_ENC_ROI_QP_2            (BIT_BASE + 0x19C)
+#define CMD_ENC_ROI_POS_3           (BIT_BASE + 0x1A0)
+#define CMD_ENC_ROI_QP_3            (BIT_BASE + 0x1A4)
+#define CMD_ENC_ROI_POS_4           (BIT_BASE + 0x1A8)
+#define CMD_ENC_ROI_QP_4            (BIT_BASE + 0x1AC)
+#define CMD_ENC_ROI_POS_5           (BIT_BASE + 0x1B0)
+#define CMD_ENC_ROI_QP_5            (BIT_BASE + 0x1B4)
+#define CMD_ENC_ROI_POS_6           (BIT_BASE + 0x1B8)
+#define CMD_ENC_ROI_QP_6            (BIT_BASE + 0x1BC)
+#define CMD_ENC_ROI_POS_7           (BIT_BASE + 0x1C0)
+#define CMD_ENC_ROI_QP_7            (BIT_BASE + 0x1C4)
+#define CMD_ENC_ROI_POS_8           (BIT_BASE + 0x1C8)
+#define CMD_ENC_ROI_QP_8            (BIT_BASE + 0x1CC)
+#define CMD_ENC_ROI_POS_9           (BIT_BASE + 0x1D0)
+#define CMD_ENC_ROI_QP_9            (BIT_BASE + 0x1D4)
+
+#define RET_ENC_ROI_SUCCESS         (BIT_BASE + 0x1D8)
+
+
+//------------------------------------------------------------------------------
+// [ENC SET FRAME BUF] COMMAND
+//------------------------------------------------------------------------------
+#define CMD_SET_FRAME_SUBSAMP_A    (BIT_BASE + 0x188)
+#define CMD_SET_FRAME_SUBSAMP_B    (BIT_BASE + 0x18C)
+
+#define CMD_SET_FRAME_DP_BUF_BASE  (BIT_BASE + 0x1B0)
+#define CMD_SET_FRAME_DP_BUF_SIZE  (BIT_BASE + 0x1B4)
+
+//------------------------------------------------------------------------------
+// [ENC HEADER] COMMAND
+//------------------------------------------------------------------------------
+#define CMD_ENC_HEADER_CODE         (BIT_BASE + 0x180)
+#define CMD_ENC_HEADER_BB_START     (BIT_BASE + 0x184)
+#define CMD_ENC_HEADER_BB_SIZE      (BIT_BASE + 0x188)
+#define CMD_ENC_HEADER_FRAME_CROP_H (BIT_BASE + 0x18C)
+#define CMD_ENC_HEADER_FRAME_CROP_V (BIT_BASE + 0x190)
+
+
+#define RET_ENC_HEADER_SUCCESS      (BIT_BASE + 0x1C0)
+
+//------------------------------------------------------------------------------
+// [ENC_PARA_SET] COMMAND
+//------------------------------------------------------------------------------
+#define CMD_ENC_PARA_SET_TYPE       (BIT_BASE + 0x180)
+#define RET_ENC_PARA_SET_SIZE       (BIT_BASE + 0x1c0)
+#define RET_ENC_PARA_SET_SUCCESS    (BIT_BASE + 0x1C4)
+
+//------------------------------------------------------------------------------
+// [ENC PARA CHANGE] COMMAND :
+//------------------------------------------------------------------------------
+#define CMD_ENC_SEQ_PARA_CHANGE_ENABLE	(BIT_BASE + 0x180)		// FrameRateEn[3], BitRateEn[2], IntraQpEn[1], GopEn[0]
+#define CMD_ENC_SEQ_PARA_RC_GOP			(BIT_BASE + 0x184)
+#define CMD_ENC_SEQ_PARA_RC_INTRA_QP	(BIT_BASE + 0x188)
+#define CMD_ENC_SEQ_PARA_RC_BITRATE     (BIT_BASE + 0x18C)
+#define CMD_ENC_SEQ_PARA_RC_FRAME_RATE  (BIT_BASE + 0x190)
+#define	CMD_ENC_SEQ_PARA_INTRA_MB_NUM	(BIT_BASE + 0x194)		// update param
+#define CMD_ENC_SEQ_PARA_SLICE_MODE		(BIT_BASE + 0x198)		// update param
+#define CMD_ENC_SEQ_PARA_HEC_MODE		(BIT_BASE + 0x19C)		// update param
+#define CMD_ENC_SEQ_PARA_CABAC_MODE		(BIT_BASE + 0x1A0)		// entropyCodingMode==2
+#define CMD_ENC_SEQ_PARA_PPS_ID  		(BIT_BASE + 0x1B4)		// entropyCodingMode==2
+
+#define RET_ENC_SEQ_PARA_CHANGE_SECCESS	(BIT_BASE + 0x1C0)
+
+//------------------------------------------------------------------------------
+// [DEC SEQ INIT] COMMAND
+//------------------------------------------------------------------------------
+#define CMD_DEC_SEQ_BB_START        (BIT_BASE + 0x180)
+#define CMD_DEC_SEQ_BB_SIZE         (BIT_BASE + 0x184)
+#define CMD_DEC_SEQ_OPTION          (BIT_BASE + 0x188)
+
+
+#define CMD_DEC_SEQ_MP4_ASP_CLASS   (BIT_BASE + 0x19C)
+#define CMD_DEC_SEQ_VC1_STREAM_FMT  (BIT_BASE + 0x19C)
+#define CMD_DEC_SEQ_X264_MV_EN		(BIT_BASE + 0x19C)
+#define CMD_DEC_SEQ_SPP_CHUNK_SIZE  (BIT_BASE + 0x1A0)
+
+// For MPEG2 only
+#define CMD_DEC_SEQ_USER_DATA_OPTION		(BIT_BASE + 0x194)
+#define CMD_DEC_SEQ_USER_DATA_BASE_ADDR		(BIT_BASE + 0x1AC)
+#define CMD_DEC_SEQ_USER_DATA_BUF_SIZE		(BIT_BASE + 0x1B0)
+
+
+#define CMD_DEC_SEQ_INIT_ESCAPE		(BIT_BASE + 0x114)
+
+
+#define RET_DEC_SEQ_BIT_RATE		(BIT_BASE + 0x1B4)
+#define RET_DEC_SEQ_EXT_INFO        (BIT_BASE + 0x1B8)
+#define RET_DEC_SEQ_SUCCESS         (BIT_BASE + 0x1C0)
+#define RET_DEC_SEQ_SRC_SIZE        (BIT_BASE + 0x1C4)
+#define RET_DEC_SEQ_ASPECT          (BIT_BASE + 0x1C8)
+#define RET_DEC_SEQ_FRAME_NEED      (BIT_BASE + 0x1CC)
+#define RET_DEC_SEQ_FRAME_DELAY     (BIT_BASE + 0x1D0)
+#define RET_DEC_SEQ_INFO            (BIT_BASE + 0x1D4)
+#define RET_DEC_SEQ_VP8_SCALE_INFO  (BIT_BASE + 0x1D4)
+
+#define RET_DEC_SEQ_CROP_LEFT_RIGHT (BIT_BASE + 0x1D8)
+#define RET_DEC_SEQ_CROP_TOP_BOTTOM (BIT_BASE + 0x1DC)
+#define RET_DEC_SEQ_SEQ_ERR_REASON  (BIT_BASE + 0x1E0)
+
+#define RET_DEC_SEQ_FRATE_NR        (BIT_BASE + 0x1E4)
+#define RET_DEC_SEQ_FRATE_DR        (BIT_BASE + 0x1E8)
+#define RET_DEC_SEQ_HEADER_REPORT   (BIT_BASE + 0x1EC)
+#define RET_DEC_SEQ_VUI_INFO		(BIT_BASE + 0x18C)
+#define RET_DEC_SEQ_VUI_PIC_STRUCT		(BIT_BASE + 0x1A8)
+
+
+
+
+//------------------------------------------------------------------------------
+// [DEC SEQ END] COMMAND
+//------------------------------------------------------------------------------
+#define RET_DEC_SEQ_END_SUCCESS     (BIT_BASE + 0x1C0)
+
+
+//------------------------------------------------------------------------------
+// [DEC PIC RUN] COMMAND
+//----------------------------------------------------
+#define CMD_DEC_PIC_ROT_MODE        (BIT_BASE + 0x180)
+#define CMD_DEC_PIC_ROT_INDEX       (BIT_BASE + 0x184)
+#define CMD_DEC_PIC_ROT_ADDR_Y      (BIT_BASE + 0x188)
+#define CMD_DEC_PIC_ROT_ADDR_CB     (BIT_BASE + 0x18C)
+#define CMD_DEC_PIC_ROT_ADDR_CR     (BIT_BASE + 0x190)
+#define CMD_DEC_PIC_ROT_STRIDE      (BIT_BASE + 0x1B8)
+
+
+#define CMD_DEC_PIC_OPTION			(BIT_BASE + 0x194)
+
+
+#define CMD_DEC_PIC_USER_DATA_BASE_ADDR		(BIT_BASE + 0x1AC)
+#define CMD_DEC_PIC_USER_DATA_BUF_SIZE		(BIT_BASE + 0x1B0)
+
+#define CMD_DEC_PIC_NUM_ROWS		        (BIT_BASE + 0x1B4)
+#define CMD_DEC_PIC_THO_PIC_PARA            (BIT_BASE + 0x198)
+#define CMD_DEC_PIC_THO_QMAT_ADDR           (BIT_BASE + 0x1A0)
+#define CMD_DEC_PIC_THO_MB_PARA_ADDR        (BIT_BASE + 0x1A4)
+#define RET_DEC_PIC_VUI_PIC_STRUCT			(BIT_BASE + 0x1A8)
+#define RET_DEC_PIC_AVC_FPA_SEI0			(BIT_BASE + 0x19C)
+#define RET_DEC_PIC_AVC_FPA_SEI1			(BIT_BASE + 0x1A0)
+#define RET_DEC_PIC_AVC_FPA_SEI2			(BIT_BASE + 0x1A4)
+#define RET_DEC_NUM_MB_ROWS					(BIT_BASE + 0x1B4) // it will be update
+#define RET_DEC_PIC_HRD_INFO				(BIT_BASE + 0x1B8)
+#define RET_DEC_PIC_SIZE					(BIT_BASE + 0x1BC)
+#define RET_DEC_PIC_FRAME_NUM				(BIT_BASE + 0x1C0)
+#define RET_DEC_PIC_FRAME_IDX				(BIT_BASE + 0x1C4)
+#define RET_DEC_PIC_DISPLAY_IDX				(BIT_BASE + 0x1C4)
+#define RET_DEC_PIC_ERR_MB					(BIT_BASE + 0x1C8)
+#define RET_DEC_PIC_TYPE					(BIT_BASE + 0x1CC)
+#define RET_DEC_PIC_POST					(BIT_BASE + 0x1D0) // for VC1
+#define RET_DEC_PIC_MVC_REPORT				(BIT_BASE + 0x1D0) // for MVC
+#define RET_DEC_PIC_OPTION					(BIT_BASE + 0x1D4)
+#define RET_DEC_PIC_SUCCESS					(BIT_BASE + 0x1D8)
+#define RET_DEC_PIC_CUR_IDX					(BIT_BASE + 0x1DC)
+#define RET_DEC_PIC_DECODED_IDX				(BIT_BASE + 0x1DC)
+#define	RET_DEC_PIC_CROP_LEFT_RIGHT			(BIT_BASE + 0x1E0) // for AVC, MPEG-2
+#define RET_DEC_PIC_CROP_TOP_BOTTOM			(BIT_BASE + 0x1E4) // for AVC, MPEG-2
+#define	RET_DEC_PIC_MODULO_TIME_BASE		(BIT_BASE + 0x1E0) // for MP4
+#define RET_DEC_PIC_VOP_TIME_INCREMENT		(BIT_BASE + 0x1E4) // for MP4
+#define RET_DEC_PIC_RV_TR					(BIT_BASE + 0x1E8)
+#define RET_DEC_PIC_VP8_PIC_REPORT			(BIT_BASE + 0x1E8)
+#define RET_DEC_PIC_ATSC_USER_DATA_INFO		(BIT_BASE + 0x1E8) // H.264, MEPEG2
+#define RET_DEC_PIC_VUI_INFO				(BIT_BASE + 0x1EC)
+#define RET_DEC_PIC_ASPECT					(BIT_BASE + 0x1F0)
+#define RET_DEC_PIC_VP8_SCALE_INFO			(BIT_BASE + 0x1F0)
+#define RET_DEC_PIC_FRATE_NR				(BIT_BASE + 0x1F4)
+#define RET_DEC_PIC_FRATE_DR				(BIT_BASE + 0x1F8)
+#define RET_DEC_PIC_POC_TOP					(BIT_BASE + 0x1AC)
+#define RET_DEC_PIC_POC_BOT					(BIT_BASE + 0x1B0)
+#define RET_DEC_PIC_POC  					(BIT_BASE + 0x1B0)
+
+//------------------------------------------------------------------------------
+// [DEC SET FRAME BUF] COMMAND
+//------------------------------------------------------------------------------
+#define CMD_SET_FRAME_BUF_NUM       (BIT_BASE + 0x180)
+#define CMD_SET_FRAME_BUF_STRIDE    (BIT_BASE + 0x184)
+
+#define CMD_SET_FRAME_SLICE_BB_START	(BIT_BASE + 0x188)
+#define CMD_SET_FRAME_SLICE_BB_SIZE		(BIT_BASE + 0x18C)
+#define CMD_SET_FRAME_AXI_BIT_ADDR		(BIT_BASE + 0x190)
+#define CMD_SET_FRAME_AXI_IPACDC_ADDR	(BIT_BASE + 0x194)
+#define CMD_SET_FRAME_AXI_DBKY_ADDR		(BIT_BASE + 0x198)
+#define CMD_SET_FRAME_AXI_DBKC_ADDR		(BIT_BASE + 0x19C)
+#define CMD_SET_FRAME_AXI_OVL_ADDR		(BIT_BASE + 0x1A0)
+#define CMD_SET_FRAME_AXI_BTP_ADDR		(BIT_BASE + 0x1A4)
+
+#define CMD_SET_FRAME_CACHE_SIZE        (BIT_BASE + 0x1A8)
+#define CMD_SET_FRAME_CACHE_CONFIG      (BIT_BASE + 0x1AC)
+#define CMD_SET_FRAME_MB_BUF_BASE       (BIT_BASE + 0x1B0)
+#define CMD_SET_FRAME_MAX_DEC_SIZE		(BIT_BASE + 0x1B8)
+#define CMD_SET_FRAME_DELAY     		(BIT_BASE + 0x1BC)
+
+#define RET_SET_FRAME_SUCCESS           (BIT_BASE + 0x1C0)
+
+//------------------------------------------------------------------------------
+// [DEC_PARA_SET] COMMAND
+//------------------------------------------------------------------------------
+#define CMD_DEC_PARA_SET_TYPE       (BIT_BASE + 0x180)
+#define CMD_DEC_PARA_SET_SIZE       (BIT_BASE + 0x184)
+
+#define RET_DEC_PARA_SET_SUCCESS        (BIT_BASE + 0x1C0)
+
+//------------------------------------------------------------------------------
+// [DEC_BUF_FLUSH] COMMAND
+//------------------------------------------------------------------------------
+#define RET_DEC_BUF_FLUSH_SUCCESS       (BIT_BASE + 0x1C0)
+
+//------------------------------------------------------------------------------
+// [SLEEP/WAKE] COMMAND
+//------------------------------------------------------------------------------
+#define RET_SLEEP_WAKE_SUCCESS          (BIT_BASE + 0x1C0)
+
+//------------------------------------------------------------------------------
+// [SET PIC INFO] COMMAND
+//------------------------------------------------------------------------------
+#define GDI_PRI_RD_PRIO_L   		(GDMA_BASE + 0x000)
+#define GDI_PRI_RD_PRIO_H   		(GDMA_BASE + 0x004)
+#define GDI_PRI_WR_PRIO_L   		(GDMA_BASE + 0x008)
+#define GDI_PRI_WR_PRIO_H   		(GDMA_BASE + 0x00c)
+#define GDI_PRI_RD_LOCK_CNT 		(GDMA_BASE + 0x010)
+#define GDI_PRI_WR_LOCK_CNT 		(GDMA_BASE + 0x014)
+#define GDI_SEC_RD_PRIO_L   		(GDMA_BASE + 0x018)
+#define GDI_SEC_RD_PRIO_H   		(GDMA_BASE + 0x01c)
+#define GDI_SEC_WR_PRIO_L   		(GDMA_BASE + 0x020)
+#define GDI_SEC_WR_PRIO_H   		(GDMA_BASE + 0x024)
+#define GDI_SEC_RD_LOCK_CNT 		(GDMA_BASE + 0x028)
+#define GDI_SEC_WR_LOCK_CNT 		(GDMA_BASE + 0x02c)
+#define GDI_SEC_CLIENT_EN   		(GDMA_BASE + 0x030)
+#define GDI_CONTROL                 (GDMA_BASE + 0x034)
+#define GDI_PIC_INIT_HOST           (GDMA_BASE + 0x038)
+
+#define GDI_HW_VERINFO            	(GDMA_BASE + 0x050)
+#define GDI_PINFO_REQ               (GDMA_BASE + 0x060)
+#define GDI_PINFO_ACK               (GDMA_BASE + 0x064)
+#define GDI_PINFO_ADDR              (GDMA_BASE + 0x068)
+#define GDI_PINFO_DATA              (GDMA_BASE + 0x06c)
+#define GDI_BWB_ENABLE              (GDMA_BASE + 0x070)
+#define GDI_BWB_SIZE                (GDMA_BASE + 0x074)
+#define GDI_BWB_STD_STRUCT          (GDMA_BASE + 0x078)
+#define GDI_BWB_STATUS              (GDMA_BASE + 0x07c)
+
+#define GDI_STATUS					(GDMA_BASE + 0x080)
+
+#define GDI_DEBUG_0                 (GDMA_BASE + 0x084)
+#define GDI_DEBUG_1                 (GDMA_BASE + 0x088)
+#define GDI_DEBUG_2                 (GDMA_BASE + 0x08c)
+#define GDI_DEBUG_3                 (GDMA_BASE + 0x090)
+#define GDI_DEBUG_PROBE_ADDR        (GDMA_BASE + 0x094)
+#define GDI_DEBUG_PROBE_DATA        (GDMA_BASE + 0x098)
+
+
+
+// write protect
+#define GDI_WPROT_ERR_CLR			(GDMA_BASE + 0x0A0)
+#define GDI_WPROT_ERR_RSN			(GDMA_BASE + 0x0A4)
+#define GDI_WPROT_ERR_ADR			(GDMA_BASE + 0x0A8)
+#define GDI_WPROT_RGN_EN			(GDMA_BASE + 0x0AC)
+#define GDI_WPROT_RGN0_STA			(GDMA_BASE + 0x0B0)
+#define GDI_WPROT_RGN0_END			(GDMA_BASE + 0x0B4)
+#define GDI_WPROT_RGN1_STA			(GDMA_BASE + 0x0B8)
+#define GDI_WPROT_RGN1_END			(GDMA_BASE + 0x0BC)
+#define GDI_WPROT_RGN2_STA			(GDMA_BASE + 0x0C0)
+#define GDI_WPROT_RGN2_END			(GDMA_BASE + 0x0C4)
+#define GDI_WPROT_RGN3_STA			(GDMA_BASE + 0x0C8)
+#define GDI_WPROT_RGN3_END			(GDMA_BASE + 0x0CC)
+#define GDI_WPROT_RGN4_STA			(GDMA_BASE + 0x0D0)
+#define GDI_WPROT_RGN4_END			(GDMA_BASE + 0x0D4)
+#define GDI_WPROT_RGN5_STA			(GDMA_BASE + 0x0D8)
+#define GDI_WPROT_RGN5_END			(GDMA_BASE + 0x0DC)
+
+#define GDI_BUS_CTRL				(GDMA_BASE + 0x0F0)
+#define GDI_BUS_STATUS				(GDMA_BASE + 0x0F4)
+
+
+
+#define GDI_SIZE_ERR_FLAG           (GDMA_BASE + 0x0e0)
+#define GDI_ADR_RQ_SIZE_ERR_PRI0	(GDMA_BASE + 0x100)
+#define GDI_ADR_RQ_SIZE_ERR_PRI1	(GDMA_BASE + 0x104)
+#define GDI_ADR_RQ_SIZE_ERR_PRI1	(GDMA_BASE + 0x104)
+#define GDI_ADR_RQ_SIZE_ERR_PRI2	(GDMA_BASE + 0x108)
+#define GDI_ADR_WQ_SIZE_ERR_PRI0	(GDMA_BASE + 0x10c)
+#define GDI_ADR_WQ_SIZE_ERR_PRI1	(GDMA_BASE + 0x110)
+#define GDI_ADR_WQ_SIZE_ERR_PRI2	(GDMA_BASE + 0x114)
+
+#define GDI_ADR_RQ_SIZE_ERR_SEC0	(GDMA_BASE + 0x118)
+#define GDI_ADR_RQ_SIZE_ERR_SEC1	(GDMA_BASE + 0x11c)
+#define GDI_ADR_RQ_SIZE_ERR_SEC2	(GDMA_BASE + 0x120)
+
+#define GDI_ADR_WQ_SIZE_ERR_SEC0	(GDMA_BASE + 0x124)
+#define GDI_ADR_WQ_SIZE_ERR_SEC1	(GDMA_BASE + 0x128)
+#define GDI_ADR_WQ_SIZE_ERR_SEC2	(GDMA_BASE + 0x12c)
+
+#define GDI_INFO_CONTROL			(GDMA_BASE + 0x400)
+#define GDI_INFO_PIC_SIZE			(GDMA_BASE + 0x404)
+#define GDI_INFO_BASE_Y				(GDMA_BASE + 0x408)
+#define GDI_INFO_BASE_CB			(GDMA_BASE + 0x40C)
+#define GDI_INFO_BASE_CR			(GDMA_BASE + 0x410)
+
+#define GDI_XY2_CAS_0				(GDMA_BASE + 0x800)
+#define GDI_XY2_CAS_F				(GDMA_BASE + 0x83C)
+
+#define GDI_XY2_BA_0				(GDMA_BASE + 0x840)
+#define GDI_XY2_BA_1				(GDMA_BASE + 0x844)
+#define GDI_XY2_BA_2				(GDMA_BASE + 0x848)
+#define GDI_XY2_BA_3				(GDMA_BASE + 0x84C)
+
+#define GDI_XY2_RAS_0				(GDMA_BASE + 0x850)
+#define GDI_XY2_RAS_F				(GDMA_BASE + 0x88C)
+
+#define GDI_XY2_RBC_CONFIG			(GDMA_BASE + 0x890)
+#define GDI_RBC2_AXI_0				(GDMA_BASE + 0x8A0)
+#define GDI_RBC2_AXI_1F				(GDMA_BASE + 0x91C)
+#define GDI_TILEDBUF_BASE			(GDMA_BASE + 0x920)
+
+//------------------------------------------------------------------------------
+// Product, Reconfiguration Information
+//------------------------------------------------------------------------------
+#define DBG_CONFIG_REPORT_0         (GDMA_BASE + 0x040)    //product name and version
+#define DBG_CONFIG_REPORT_1         (GDMA_BASE + 0x044)    //interface configuration, hardware definition
+#define DBG_CONFIG_REPORT_2         (GDMA_BASE + 0x048)    //standard definition
+#define DBG_CONFIG_REPORT_3         (GDMA_BASE + 0x04C)    //standard detail definition
+#define DBG_CONFIG_REPORT_4         (GDMA_BASE + 0x050)    //definition in cnm_define
+#define DBG_CONFIG_REPORT_5         (GDMA_BASE + 0x054)
+#define DBG_CONFIG_REPORT_6         (GDMA_BASE + 0x058)
+#define DBG_CONFIG_REPORT_7         (GDMA_BASE + 0x05C)
+
+//------------------------------------------------------------------------------
+// MEMORY COPY MODULE REGISTER
+//------------------------------------------------------------------------------
+#define	ADDR_DMAC_PIC_RUN			(DMAC_BASE+0x000)
+#define	ADDR_DMAC_PIC_STATUS		(DMAC_BASE+0x004)
+#define	ADDR_DMAC_PIC_OP_MODE		(DMAC_BASE+0x008)
+#define	ADDR_DMAC_ID				(DMAC_BASE+0x00c)	//the result muse be 0x4d435059
+
+#define	ADDR_DMAC_SRC_BASE_Y		(DMAC_BASE+0x010)
+#define	ADDR_DMAC_SRC_BASE_CB		(DMAC_BASE+0x014)
+#define	ADDR_DMAC_SRC_BASE_CR		(DMAC_BASE+0x018)
+#define	ADDR_DMAC_SRC_STRIDE		(DMAC_BASE+0x01c)
+
+#define	ADDR_DMAC_DST_BASE_Y		(DMAC_BASE+0x020)
+#define	ADDR_DMAC_DST_BASE_CB		(DMAC_BASE+0x024)
+#define	ADDR_DMAC_DST_BASE_CR		(DMAC_BASE+0x028)
+#define	ADDR_DMAC_DST_STRIDE		(DMAC_BASE+0x02c)
+
+#define	ADDR_DMAC_SRC_MB_POS_X		(DMAC_BASE+0x030)
+#define	ADDR_DMAC_SRC_MB_POS_Y		(DMAC_BASE+0x034)
+#define	ADDR_DMAC_SRC_MB_BLK_X		(DMAC_BASE+0x038)
+#define	ADDR_DMAC_SRC_MB_BLK_Y		(DMAC_BASE+0x03c)
+
+#define	ADDR_DMAC_DST_MB_POS_X		(DMAC_BASE+0x040)
+#define	ADDR_DMAC_DST_MB_POS_Y		(DMAC_BASE+0x044)
+#define	ADDR_DMAC_DST_MB_BLK_X		(DMAC_BASE+0x048)
+#define	ADDR_DMAC_DST_MB_BLK_Y		(DMAC_BASE+0x04c)
+
+#define	ADDR_DMAC_SET_COLOR_Y		(DMAC_BASE+0x050)
+#define	ADDR_DMAC_SET_COLOR_CB		(DMAC_BASE+0x054)
+#define	ADDR_DMAC_SET_COLOR_CR		(DMAC_BASE+0x058)
+
+#define	ADDR_DMAC_SUB_SAMPLE_X		(DMAC_BASE+0x060)
+#define	ADDR_DMAC_SUB_SAMPLE_Y		(DMAC_BASE+0x064)
+
+
+
+//------------------------------------------------------------------------------
+// DMAC
+//------------------------------------------------------------------------------
+#define DMAC_DMAC_RUN		    (DMAC_BASE + 0x00)
+#define DMAC_SOFT_RESET		    (DMAC_BASE + 0x04)
+#define DMAC_DMAC_MODE		    (DMAC_BASE + 0x08)
+#define DMAC_DESC_ADDR		    (DMAC_BASE + 0x0c)
+#define DMAC_DESC0				(DMAC_BASE + 0x10)
+#define DMAC_DESC1				(DMAC_BASE + 0x14)
+#define DMAC_DESC2				(DMAC_BASE + 0x18)
+#define DMAC_DESC3				(DMAC_BASE + 0x1c)
+#define DMAC_DESC4				(DMAC_BASE + 0x20)
+#define DMAC_DESC5				(DMAC_BASE + 0x24)
+#define DMAC_DESC6				(DMAC_BASE + 0x28)
+#define DMAC_DESC7				(DMAC_BASE + 0x2c)
+
+
+//------------------------------------------------------------------------------
+// [FIRMWARE VERSION] COMMAND
+// [32:16] project number =>
+// [16:0]  version => xxxx.xxxx.xxxxxxxx
+//------------------------------------------------------------------------------
+#define RET_FW_VER_NUM					(BIT_BASE + 0x1c0)
+#define RET_FW_CODE_REV             (BIT_BASE + 0x1c4)
+
+
+#endif //__CODA960_REGS_H__
+
diff --git a/board/rda/common/include/coda960_test_video.txt b/board/rda/common/include/coda960_test_video.txt
new file mode 100644
index 0000000000..e3c8c4d469
--- /dev/null
+++ b/board/rda/common/include/coda960_test_video.txt
@@ -0,0 +1,7015 @@
+0x01000000,	0x1E404D67,	0x1E5A80EC,	0x008008D8,	0x80000300,	0x47190000,	0x00CB168B,	0x68010000,
+0x00C8B2EF,	0x05060100,	0xDCE8FFFF,	0xE6BDE945,	0x96B748D9,	0xD920D82C,	0x78EFEE23,	0x20343632,
+0x6F63202D,	0x31206572,	0x72203932,	0x30333232,	0x66633120,	0x66396566,	0x48202D20,	0x3436322E,
+0x45504D2F,	0x20342D47,	0x20435641,	0x65646F63,	0x202D2063,	0x79706F43,	0x7466656C,	0x30303220,
+0x30322D33,	0x2D203231,	0x74746820,	0x2F2F3A70,	0x2E777777,	0x65646976,	0x6E616C6F,	0x67726F2E,
+0x3632782F,	0x74682E34,	0x2D206C6D,	0x74706F20,	0x736E6F69,	0x6163203A,	0x3D636162,	0x65722031,
+0x20313D66,	0x6C626564,	0x3D6B636F,	0x3A303A31,	0x6E612030,	0x73796C61,	0x78303D65,	0x78303A31,
+0x20313131,	0x683D656D,	0x73207865,	0x656D6275,	0x7020373D,	0x313D7973,	0x79737020,	0x3D64725F,
+0x30302E31,	0x302E303A,	0x696D2030,	0x5F646578,	0x3D666572,	0x656D2030,	0x6E61725F,	0x313D6567,
+0x68632036,	0x616D6F72,	0x3D656D5F,	0x72742031,	0x696C6C65,	0x20313D73,	0x64387838,	0x303D7463,
+0x6D716320,	0x6420303D,	0x7A646165,	0x3D656E6F,	0x312C3132,	0x61662031,	0x705F7473,	0x70696B73,
+0x6320313D,	0x6D6F7268,	0x70715F61,	0x66666F5F,	0x3D746573,	0x7420322D,	0x61657268,	0x313D7364,
+0x6F6F6C20,	0x6568616B,	0x745F6461,	0x61657268,	0x313D7364,	0x696C7320,	0x5F646563,	0x65726874,
+0x3D736461,	0x726E2030,	0x6420303D,	0x6D696365,	0x3D657461,	0x6E692031,	0x6C726574,	0x64656361,
+0x6220303D,	0x6172756C,	0x6F635F79,	0x7461706D,	0x6320303D,	0x74736E6F,	0x6E696172,	0x695F6465,
+0x6172746E,	0x6220303D,	0x6D617266,	0x323D7365,	0x705F6220,	0x6D617279,	0x313D6469,	0x615F6220,
+0x74706164,	0x6220313D,	0x6169625F,	0x20303D73,	0x65726964,	0x313D7463,	0x69657720,	0x62746867,
+0x6F20313D,	0x5F6E6570,	0x3D706F67,	0x65772030,	0x74686769,	0x20323D70,	0x6979656B,	0x323D746E,
+0x656B2035,	0x746E6979,	0x6E696D5F,	0x2030313D,	0x6E656373,	0x74756365,	0x2030343D,	0x72746E69,
+0x65725F61,	0x73657266,	0x20303D68,	0x6C5F6372,	0x616B6F6F,	0x64616568,	0x2035323D,	0x633D6372,
+0x6D207262,	0x65727462,	0x20313D65,	0x72746962,	0x3D657461,	0x30303032,	0x74617220,	0x6C6F7465,
+0x302E313D,	0x6F637120,	0x303D706D,	0x2030362E,	0x696D7071,	0x20303D6E,	0x616D7071,	0x39363D78,
+0x73707120,	0x3D706574,	0x62762034,	0x616D5F76,	0x74617278,	0x30323D65,	0x76203030,	0x625F7662,
+0x69736675,	0x313D657A,	0x20303030,	0x5F6C616E,	0x3D647268,	0x656E6F6E,	0x5F706920,	0x69746172,
+0x2E313D6F,	0x61203034,	0x3A313D71,	0x30302E31,	0x00008000,	0x84886501,	0x72FF2100,	0xDE93AF14,
+0x4708431B,	0x421F7010,	0x387A62D0,	0xCEDCA0E9,	0xC2AC549F,	0x0B95542A,	0xF8097915,	0x534E817D,
+0x08DDC69B,	0xFAD98D24,	0xDF539BFE,	0xDB4CD42F,	0x1605F13C,	0xC864D931,	0x1CE690E6,	0x6820FA6F,
+0xD3225B5A,	0x175C0BD3,	0xD211C734,	0x4152C276,	0xE44BFC74,	0x31DF457D,	0x35660825,	0x2259F533,
+0x61275E4A,	0xA87763B2,	0x8D447AF6,	0x5AC57358,	0xC4ACACFE,	0x3D32892D,	0xF1756CF5,	0x9E413164,
+0x200FC974,	0xBBC24807,	0xC4BA5CC5,	0xC5329A4E,	0x93C055B0,	0xD50AA203,	0xF0FCFD20,	0x437E08E9,
+0xFB200B8D,	0x14D394E7,	0x7FC46FD0,	0xAD1863AF,	0xDE02D2F3,	0x80016B76,	0x8F0382EE,	0x8CFB1F89,
+0xA643FAA3,	0x03346E90,	0x0D86E587,	0xFF20098E,	0x1B99AC53,	0x22B926A9,	0x267D4213,	0x27CF1555,
+0xDF60C844,	0x7EBC51BB,	0x1D67435F,	0x0A0B9ADD,	0xB523F3DF,	0x7ECB02F6,	0xBF75F1AD,	0x1B627B9D,
+0x62511DD8,	0x07919B39,	0x838E5889,	0xF02BD0F9,	0x3F68E2A6,	0x670A2AD1,	0x7C0B5B3A,	0x4329E82B,
+0x982E5AD5,	0x2F2384DA,	0x93BBE985,	0x903E00B8,	0xF5AC3E44,	0xEB9CAFF9,	0x35E0788A,	0x69E95BF8,
+0x720137E4,	0x7CC1C92E,	0x81A605E1,	0x742EAC8E,	0x9CF6747B,	0xE95A7ECF,	0x89595B54,	0xBC2B3DED,
+0xB891BBB2,	0xE44CDA67,	0x849E244E,	0x56FC9C0A,	0x8B488788,	0x6F6E0973,	0xC3444583,	0x9B612298,
+0x8C9F14CA,	0x4A3EDA93,	0x867289F6,	0x1EEFB81E,	0xC36846D9,	0x188E9074,	0x47437D40,	0x66776DDA,
+0x67C04DD3,	0xE2910C65,	0x5096CAE9,	0x6EA1C2EA,	0x17BDD43D,	0xEE93A86D,	0x34DD15EC,	0x4F2B591C,
+0xF79432B3,	0x65113CB2,	0x0F2935A1,	0xC3391A73,	0x2344523A,	0x6C4667BD,	0xDFE61D0A,	0x478EF4BA,
+0x50145FC9,	0x70BF3FE7,	0x902362DB,	0xB888707F,	0x067D3F5F,	0xE4947153,	0xFD2AF8B0,	0x1ED31942,
+0x934BBF78,	0xBA3702E4,	0x76BE526B,	0xE6576BF1,	0x2A8C9F84,	0x6F6E03BF,	0x3F8DC3BC,	0x719C842D,
+0xD1495E92,	0x1605A50E,	0xC9895528,	0x69595B63,	0xF225E6B7,	0x67E6F31F,	0x4E224202,	0x9744F345,
+0xD64329A1,	0x1C2E956F,	0xE55370FB,	0xA5A36E91,	0x992D5AF9,	0x793F9429,	0x5483F4E0,	0x75C8E778,
+0xDBCFA2C3,	0xF3CB3AD3,	0x33DD0290,	0xAF5C5D56,	0x73C3A64E,	0xF1A03C2A,	0xFE4EC93D,	0x2F8062A1,
+0x185E0E90,	0x3F598540,	0x1ED012DE,	0xB1D6A2C4,	0x46A68097,	0x0F2AFD0C,	0xF1FEA809,	0x07AE97CE,
+0xE570B0F0,	0x54FCA6BE,	0xBA1A08F6,	0x8B0FE28A,	0x63E3221A,	0x04F3A4A9,	0xC95F562B,	0x7056537B,
+0x632AF291,	0xD3A55E38,	0x97BD6F08,	0x6AC40E66,	0x6525562A,	0x2F751481,	0x0D4A6BD2,	0x160CD960,
+0x90C045F0,	0x85B23650,	0xC89AE055,	0x2DB2F098,	0xC3335AFE,	0x2D9FD68F,	0x95AE67AB,	0xA466872B,
+0x5C383621,	0x1AA5B0A6,	0xFFA83F45,	0x69E10FBA,	0xD4F48895,	0xD3EEB2FF,	0xFEAE3BE8,	0x2F62AEE5,
+0x1BF3C05B,	0xE66BE019,	0x463F049C,	0x7073D668,	0xD17DA291,	0xB1FF267F,	0xCA905CBC,	0xB4488289,
+0x8D850F96,	0xCD4935B8,	0x7A57A570,	0x8CD27C2B,	0x74F8B552,	0x6F76DFC0,	0x3FA50302,	0x00CCCF49,
+0xDB017DAE,	0x2B718257,	0xE443E347,	0x0B51B0E2,	0xF7D03B2E,	0x354196DA,	0xFC1FA725,	0xFE047C25,
+0xB3058BD6,	0xBF8DCB86,	0x89B77C44,	0xFF041AAC,	0xD3A00FF0,	0x35F86CD8,	0xD25D9472,	0xF4375A55,
+0x94B88C08,	0xCCA8E9C6,	0x5A2E7CFF,	0x15378BFD,	0x196ED026,	0x713EE774,	0x34246839,	0x686B0CBE,
+0x817793AA,	0xB0CCFA95,	0x0C528327,	0x1E1DCF30,	0x073265FB,	0x2B5777C7,	0x5215EA68,	0x1204404C,
+0x92B40E34,	0x39FB8950,	0x9211A7C9,	0xB7390D0E,	0xA217CF6C,	0xE3978FB0,	0x037FAC4B,	0x8C4D460E,
+0xE7D012F6,	0x4DCBCD03,	0x9B780DBF,	0x7D4A71AB,	0x981DC7E5,	0x87916FD8,	0xE33D98DA,	0xC9561280,
+0x351A4BC3,	0x470D2293,	0x9A3E5EBB,	0x9C01AEBF,	0x8F1CCE93,	0x34903D2F,	0xB90E045A,	0xBAF0144F,
+0x268FE655,	0xF0E17DD4,	0x42112AC3,	0x4A4645E2,	0xDEA58074,	0xD4BE4A5F,	0x60C048C4,	0x498F1DDD,
+0xB851991F,	0x0FBADB44,	0xE95B7E81,	0xFB9AC14E,	0x3E0E53BA,	0x6F4E477F,	0xAD045EB9,	0xEC724696,
+0xD7A81D0D,	0x37BBA2BC,	0xC6BDC7D4,	0xFD971B5F,	0x065F3CAC,	0x90C1D746,	0xB3B6FFC1,	0xAE48B3FC,
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+0x95857985,	0x436E5165,	0xABA01405,	0x16668A20,	0x52F9654F,	0x7C010D1B,	0x83AF9BA6,	0xFB3EF57E,
+0x338BF567,	0x5544D0CB,	0xC67299B2,	0x4D87BEDB,	0xA37A9D1D,	0xD66654C3,	0x1F0CC2D9,	0x08A08957,
+0x53F2119D,	0x07215109,	0x4D2B72AF,	0x099C646D,	0xD5F429A4,	0x06466B8E,	0xDB9864E7,	0x96DFFA6D,
+0x77AF81DC,	0xDF4DDFB7,	0x0285761C,	0x1CAD869B,	0x745AEFDE,	0x0667B350,	0xAFACE895,	0xDC5670CF,
+0xAE5F1D34,	0xA8DE1270,	0x611EF4F5,	0x8F3F661C,	0x5D6AC752,	0x3326830F,	0xE2A62DCE,	0x9EB5C771,
+0x439343A3,	0xF5E2C87E,	0xCED1C7D9,	0x4957C41E,	0xA7C58239,	0xCCFE5144,	0xCE0A54AA,	0x41B5724F,
+0x3F9C6567,	0xC14C12C4,	0x77AEC102,	0xC9417C89,	0x636E16CC,	0xA35728A8,	0xDD6390F7,	0x8D52D29D,
+0x94C89468,	0xD7AA2C5A,	0xAC40442A,	0x89100A75,	0xD74AC5C4,	0xF20E3A18,	0xA4331E57,	0x497FB441,
+0x375233B8,	0xD8A6B084,	0xF7F5242F,	0xB6534DCA,	0xAC019211,	0xDDDD594C,	0xCB04C044,	0xFFFA3079,
+0x691BFD6A,	0x76B39697,	0x15DF3CC5,	0xF08987D0,	0x6E29499E,	0x5A98E16A,	0x32724180,	0xF933A4E0,
+0x7F4F938F,	0xE7773840,	0x9BFB3425,	0x45EDA4CE,	0x8041BB7F,	0xBA4F8835,	0x5E065039,	0x5B457B7F,
+0x11293E90,	0xC7429671,	0xD07C9854,	0xB2201A50,	0x53A9927B,	0xEE75CD7F,	0x3E2D6AC8,	0x5D7F4DAE,
+0xE3283C08,	0x400BBBCB,	0xAB52B099,	0x7A0FA45A,	0x461CF37D,	0x3C196B52,	0x0DA90431,	0xD335AA0E,
+0xB7EA8605,	0x2ED6093D,	0x7E36C994,	0x134175B2,	0xE7165CCB,	0x9A6275C8,	0x3AC62BC2,	0xE92B708B,
+0x4B54A61D,	0xA36387AE,	0xAC32B431,	0x0895D5D3,	0x3EAA0FF2,	0x8AFC7CB6,	0x5B5C5898,	0x79D05134,
+0xDC8DD681,	0xEC4198E2,	0x4B57AA57,	0x9FDE3227,	0x765F46FD,	0x17B9BBFD,	0x9546318A,	0x520D5C5F,
+0xCD1F2641,	0x3F5A5040,	0xB789C7D7,	0x9AD26F05,	0x489373C8,	0x87A947B6,	0x658D6F8B,	0xB1BB913A,
+0xB1736CC0,	0xDA842C41,	0x8CEDB117,	0x55E96C0B,	0xF14ABAC7,	0x2A5754B2,	0xEA081BF4,	0x31802010,
+0x07FC041D,	0xEC1E2E7C,	0xA6A587B6,	0xE8544CF0,	0x963E7DBC,	0x91C5EAC9,	0xF9A30105,	0x1E3795C4,
+0x0EB4D7F4,	0x2ABBFC3B,	0xD912DB7A,	0xB59C1F70,	0xEE06F9E7,	0xE41003B9,	0x4B41D4B8,	0xFB06A6E3,
+0xFD9FC550,	0x585BA559,	0x126BDEA5,	0x8C884DC1,	0x31E188D1,	0xC91D2EDA,	0x165EC8EE,	0xBD97C7D3,
+0x41687217,	0x2DACD212,	0xAF2B0A71,	0xB50C8C08,	0x9755041A,	0xFFC0C7A9,	0x3944C7E1,	0x8A3D5888,
+0x6C7D109F,	0xC0C59704,	0x84912F52,	0xBC521D70,	0x25131484,	0x701DC346,	0x3962F9A3,	0xAC76064F,
+0x5D8D4ABF,	0x9AC7D2E6,	0x11B91637,	0x33477DA7,	0xDDFA8BA6,	0xAF0B05C4,	0x042B371A,	0xCB97A6F3,
+0xC00BE0DB,	0xA3B139CB,	0x42B6D698,	0xBB786404,	0x5771ABA4,	0x13F567CD,	0x3F5D0082,	0xC3976701,
+0x93376244,	0x5B30645E,	0x4E0F5455,	0x8E5EA337,	0xFB775E99,	0x6EDA25A4,	0x89158FED,	0xB30CEF06,
+0x33F46623,	0x424951BC,	0x4583E10D,	0x8012D33F,	0x74886E36,	0xA77E56D3,	0x5D8C8C9D,	0xF1EA6249,
+0x88F60548,	0xF6EB83E2,	0xF1026B3F,	0x29365DD4,	0x562D209A,	0x4F9C8037,	0xADF430D9,	0xE1B8996F,
+0xD5397762,	0x1A1C81E7,	0x835F8971,	0x3E757A0C,	0xEF7F9FE8,	0x58A0A860,	0xA47F520F,	0xDF1C2504,
+0x81550321,	0x5FDCE2BC,	0x08E19441,	0xCBE58F8B,	0x8CCBBB75,	0x5C1544E9,	0xCF8DC1E8,	0x7382CAE1,
+0x4BB7BDA2,	0x2EB05621,	0x34C58257,	0x7DCFB117,	0xE0AEBE32,	0x781C2D1C,	0x37442033,	0x1831BDAE,
+0x387ECB9E,	0xF4E4CA2A,	0x04DA9615,	0x4AF9C6D8,	0x732351C2,	0xF4289AF0,	0xF6D38C61,	0x85E7D33A,
+0x6D0D3860,	0x7A80E291,	0x701FB1CA,	0x3089B4E8,	0x598F71DE,	0x417F70E2,	0x065160B3,	0x55DEC560,
+0x44ED1945,	0xD043F54A,	0x2138C5B6,	0x3FF42DA6,	0xE2A7D634,	0xED6695D4,	0xFF17B97D,	0x6BB509BD,
+0xD9293177,	0x310B696A,	0x03912223,	0x6F8D6719,	0xF4BF0897,	0x2CF4061F,	0x1CC85CCB,	0xD6D5B90C,
+0x6BA527E4,	0x06005141,	0x79AB2E86,	0x02AC187B,	0x4E482E86,	0xA095FFC9,	0x5B735774,	0xF77F8693,
+0x56A20277,	0x48E9245A,	0x22B7E4C8,	0x219E63B1,	0x74459F42,	0x5296B965,	0x3CA63CA9,	0xF56B43D7,
+0x51B2DB04,	0xDAF5033D,	0x25BB1773,	0xAC6432B8,	0x37DD6F0C,	0x3CDC9520,	0xD5C42CFD,	0xF3D10240,
+0xE78A73FF,	0xFAC2B754,	0xEB864C3B,	0x90EB2C3B,	0xD6AAEEE0,	0x80042D96,	0x5D408AF7,	0xD64F981A,
+0x8F10A866,	0x8FD9B205,	0x4A118DF4,	0xBDE79790,	0x89639E41,	0x85917629,	0x6B8E2ABA,	0xD6D97448,
+0xE4179328,	0x57A72280,	0x7F4A5039,	0xB8A94547,	0x6AE5AF25,	0xBDDF5A39,	0xF02601F5,	0xFB20278D,
+0x64632A31,	0x4E236F08,	0x1B84D502,	0xB80500D9,	0x4CF2B584,	0x53080125,	0x6E25C255,	0xE9254CE4,
+0x0F3AD582,	0xE6B990A0,	0xEB980922,	0x266C2847,	0x73AA05D1,	0x60B3BA1F,	0xE13E4BD2,	0x2454FC6D,
+0x2FAF1A63,	0x743F5FF4,	0x5CDCFB99,	0x9BE28675,	0xC71AB112,	0xFBAF4573,	0xC2436FC0,	0xBE3E744B,
+0x43CE2C4D,	0x2DA0BAEA,	0xDF58B7ED,	0xA3DFE938,	0x816073A4,	0xEFD8F97C,	0xBC4BBDCE,	0x0518944D,
+0x4D056AAA,	0xCD3BB1A3,	0x9C52B8C6,	0xAAEFDCA4,	0x1BAA7524,	0xC2B7B039,	0x8B8A68DD,	0x06D8A4A2,
+0xD94AA28E,	0xBAD5FF68,	0x288F5EDD,	0x4BEC3312,	0x282AE897,	0xBB1FC67F,	0x0C1527FF,	0x5C1F9429,
+0xE0E0290C,	0x37AE165A,	0xE52DE406,	0x4A253206,	0xC6D1F2D9,	0x9362CFBB,	0x37F94252,	0x77DD7370,
+0xDB16A00E,	0x3CC7DB56,	0xD1618D1A,	0x8D097ACC,	0xC8EB75C5,	0x658C271C,	0xC05CEA4F,	0xC4F81BCD,
+0xA2F7256D,	0x55708301,	0xE4DD5885,	0xB3B0DC96,	0x6CABCAAC,	0xD1D14387,	0xC90C3A7F,	0x1DA3E066,
+0xC63647FD,	0xEFFA50FE,	0x2A4EA0F1,	0xC7BD1684,	0xFEA4CFB3,	0x216C7D17,	0x4AEEBA15,	0xD1A5F37F,
+0xC3178500,	0xEE1C29F7,	0x663262E1,	0x13AF0723,	0x4898625E,	0x3930F881,	0x6CEA995B,	0xEE67A958,
+0xD6F2A4D1,	0x7550C02D,	0xD19D8FE5,	0x318F423F,	0x226157ED,	0xB9AF4344,	0x29CABC8B,	0x454DE8D9,
+0xE1E1FB81,	0x17DF9067,	0x16D3E00E,	0xF59FDD11,	0xCD20CADF,	0x57ED85EF,	0xEA11FD9D,	0x6F93F7A0,
+0x3A5A241A,	0xAE481A7B,	0xAFB8DBAD,	0x9F518083,	0xFA8A72BF,	0xA1807FEB,	0x9EFA7C19,	0x33043279,
+0xFCD899ED,	0x0D39F5E5,	0xE19C1ACA,	0x93439729,	0x96C5E92E,	0xC54C291B,	0xB0031FDD,	0xD06F922F,
+0x8F81EDFF,	0xF1BEC66C,	0x50AA76D7,	0xF243350E,	0xE0684A82,	0x1530681D,	0x84996E51,	0xE3D12663,
+0x871530BF,	0x317D26C9,	0x3FCE6C74,	0x2D0952D2,	0x43135500,	0x25554C90,	0xF2CA3A67,	0x4D8407CB,
+0xE54D21E8,	0x73B63908,	0x20AD34BE,	0xEC9EC3F1,	0xA5753163,	0x04BF37E5,	0xFA35C705,	0x8F52FA57,
+0xD9309F23,	0x93BA63A2,	0xE1E7BE11,	0x61B3DE2A,	0xF12E47DF,	0x68ABE79D,	0x1404735C,	0xF99EBF90,
+0xAA2B844F,	0x1ACE10D5,	0x727756B2,	0x9A5BC570,	0xC156D617,	0xE148ACAE,	0x85644997,	0x663D1020,
+0xCE07C75D,	0x1B1E57D8,	0x5930B8F8,	0xCE937EE9,	0x53CE3255,	0x9A4FA07E,	0x5ED54F33,	0xF6C81F10,
+0xA30707EC,	0x973E4C10,	0x46EFDBB6,	0x71CBFCE7,	0x85EFA697,	0xA58F90D9,	0x2DA7F436,	0x74A96661,
+0xD9A41E53,	0x0B80B558,	0xFF85BE5A,	0xF2ECAABF,	0x00008195,	0x9F010100,	0xFF2944B7,	0xA1BD49FE,
+0xA23CFB2E,	0xC25601A9,	0x8721577F,	0x001B40CB,	0x327AC749,	0x1263A86A,	0x6F4ADF22,	0xB731AF0E,
+0x52F555A5,	0x58FB153E,	0xAA968A55,	0xAC6F92C2,	0x45EAAE7E,	0x72E2F253,	0xE1A6F55E,	0xC86FCF3D,
+0x12379C1E,	0x71166347,	0x1BC4E76C,	0xC44FBC97,	0xA258CE6B,	0xF1F8B483,	0x4CF480BC,	0xAADB7AFC,
+0x9942E9BC,	0x1D920350,	0x3869FC2B,	0xFAF51233,	0x0743BE5A,	0x2B4F6A1A,	0xC9BEE97F,	0xA3D5FE30,
+0xEED506E7,	0x54DF52AF,	0x54C1F23F,	0x13055123,	0x0F81129A,	0x11A67D71,	0xAF47F4AA,	0x446D0AC8,
+0x3DC4DF68,	0x97592A89,	0x8304F966,	0x0024D15B,	0xC54A8A11,	0xD9662D7F,	0x263DA27F,	0x9B789218,
+0xF7D9C965,	0x354AAF5F,	0x31A2EEA1,	0x451BE162,	0xDB6007E9,	0x6B0FC1E6,	0xCC0CD304,	0xE6ACD98F,
+0x9FA0237C,	0x1D506195,	0x31561C3C,	0xF209687D,	0x32E72322,	0x1AF935B6,	0xB0F38931,	0xB5437CBE,
+0x885D706A,	0x2A755B9A,	0x67C3874B,	0x2181CD96,	0x86157748,	0x86817166,	0x34A2DFF8,	0xC480509D,
+0x1126AF5D,	0x4CCAD3C2,	0xD533F4CB,	0x238BE8F8,	0x5B39BC98,	0x55585528,	0x149C31BA,	0x2E048CA9,
+0x7DF44543,	0x35879919,	0x56905C5D,	0x1AA1222E,	0xCFAC1E44,	0x4291E7E3,	0x00008D09,
diff --git a/board/rda/common/include/freh3_h264_30f_hp_cif_decOrder.md5 b/board/rda/common/include/freh3_h264_30f_hp_cif_decOrder.md5
new file mode 100644
index 0000000000..b8f516f930
--- /dev/null
+++ b/board/rda/common/include/freh3_h264_30f_hp_cif_decOrder.md5
@@ -0,0 +1,89 @@
+0x49,	0xC6,	0xCC,	0x44,	0x42,	0x89,	0xA8,	0x5A,
+0x65,	0x75,	0xC1,	0x29,	0xC3,	0x30,	0x4A,	0x84,
+
+0x33,	0xBD,	0xFA,	0xE5,	0x86,	0x69,	0x1C,	0xFF,
+0x38,	0xD4,	0xE8,	0x4C,	0x3A,	0xD3,	0x45,	0x24,
+
+0xEF,	0xFB,	0x09,	0x1E,	0x4F,	0x24,	0xF2,	0xEB,
+0xBD,	0x69,	0x18,	0x4A,	0xCE,	0x56,	0xA5,	0x90,
+
+0x99,	0x4F,	0xE7,	0x64,	0x59,	0x0A,	0xB9,	0x24,
+0x87,	0x2B,	0xDC,	0x37,	0xBF,	0x42,	0x6B,	0xD2,
+
+0x09,	0xFE,	0xE4,	0x18,	0xD8,	0xC1,	0x81,	0x35,
+0xCD,	0x0D,	0x09,	0x85,	0x83,	0xE4,	0x11,	0xA6,
+
+0x24,	0x32,	0x60,	0xBC,	0xC5,	0x12,	0xF1,	0xE5,
+0xEF,	0xF9,	0x05,	0xBC,	0xA7,	0x5B,	0xC8,	0xCD,
+
+0x25,	0x91,	0xB7,	0xDB,	0xBB,	0x4B,	0x22,	0x46,
+0x2B,	0x0F,	0x03,	0x1B,	0x75,	0xE1,	0xF1,	0x50,
+
+0x17,	0xE6,	0xAE,	0x90,	0x47,	0x5E,	0x2B,	0xA0,
+0xCA,	0xC1,	0xE7,	0x33,	0x8B,	0xE4,	0xFD,	0x46,
+
+0x17,	0x8D,	0xE3,	0xD0,	0xD1,	0xE1,	0x62,	0x17,
+0x70,	0x09,	0x0A,	0x19,	0x3B,	0x08,	0x99,	0xBC,
+
+0xC0,	0xE4,	0x9C,	0xF1,	0x0A,	0x7E,	0x8D,	0x1E,
+0x6F,	0x59,	0xDB,	0x02,	0x04,	0x6B,	0xCA,	0x84,
+
+0x2E,	0x7F,	0x31,	0x77,	0xD6,	0xD3,	0x7F,	0x7B,
+0xFC,	0xE7,	0x41,	0xFF,	0x66,	0x8E,	0xBF,	0x7E,
+
+0x86,	0x53,	0x2A,	0x3D,	0x81,	0x99,	0xA0,	0xA5,
+0xA7,	0x6F,	0x13,	0x32,	0x15,	0x59,	0xD9,	0x30,
+
+0xB9,	0x64,	0x7A,	0xD6,	0xE5,	0x38,	0x89,	0x99,
+0x9E,	0xC7,	0xB4,	0xDD,	0x53,	0xEE,	0xB6,	0x09,
+
+0xF5,	0xB4,	0x43,	0xA1,	0x88,	0xF0,	0x4C,	0x9F,
+0xC3,	0xDA,	0xB8,	0xF2,	0xB9,	0x87,	0x2E,	0x6A,
+
+0x8E,	0xEB,	0x97,	0x0B,	0x09,	0x25,	0x0C,	0xF1,
+0x09,	0x93,	0x92,	0x2A,	0x84,	0xB9,	0xAB,	0x9A,
+
+0x69,	0x95,	0xF2,	0xAF,	0x94,	0x81,	0x75,	0xB3,
+0x0D,	0x35,	0x75,	0x20,	0x4D,	0xF7,	0x88,	0xEA,
+
+0xB4,	0x58,	0xD7,	0xD1,	0x31,	0x43,	0xEB,	0x59,
+0x76,	0x26,	0xD6,	0xA0,	0x8A,	0x44,	0x3B,	0x9C,
+
+0x33,	0x0C,	0x29,	0xC3,	0xCA,	0xCD,	0x62,	0xE7,
+0x9F,	0x5E,	0x55,	0x9E,	0xFF,	0xCB,	0x84,	0xA9,
+
+0xA7,	0x46,	0x31,	0x34,	0x57,	0x18,	0x34,	0xD2,
+0x71,	0xC6,	0x26,	0xB4,	0x95,	0x5C,	0xE7,	0x87,
+
+0x69,	0x8F,	0x96,	0x4F,	0xB3,	0xDF,	0xD8,	0x1F,
+0x32,	0x6C,	0x90,	0xEF,	0x3A,	0xED,	0xB2,	0xBF,
+
+0x43,	0x9B,	0x47,	0x3B,	0xBE,	0x46,	0x3F,	0xE1,
+0xB1,	0xA8,	0x36,	0x2C,	0xEC,	0x4C,	0x03,	0xA5,
+
+0x94,	0xEE,	0x55,	0x35,	0xBF,	0x39,	0x1C,	0x2E,
+0xD6,	0xB4,	0xEA,	0x7E,	0x7B,	0xDB,	0x5A,	0x4E,
+
+0xA2,	0x85,	0x7D,	0x96,	0x11,	0x90,	0x9F,	0xE5,
+0x15,	0x4A,	0x36,	0x62,	0xCF,	0x89,	0x15,	0x30,
+
+0xC1,	0x01,	0x35,	0x27,	0xBE,	0xF6,	0x17,	0xEB,
+0x46,	0x02,	0x9D,	0xA5,	0x6C,	0x02,	0xA1,	0x98,
+
+0x75,	0x25,	0x55,	0xD5,	0x3C,	0x7E,	0x0D,	0xCB,
+0x20,	0x7B,	0x6D,	0xA2,	0x40,	0x72,	0xBF,	0xBC,
+
+0x40,	0x75,	0x0E,	0x47,	0x3C,	0x58,	0x7F,	0xAF,
+0x12,	0x0D,	0xFD,	0x4A,	0x7F,	0x07,	0xB2,	0x93,
+
+0x05,	0xE7,	0x44,	0x51,	0x82,	0x5C,	0x18,	0x14,
+0xD2,	0x9D,	0x9B,	0xD0,	0xA0,	0x20,	0x12,	0xBD,
+
+0x16,	0x86,	0x55,	0xBB,	0xA0,	0x0A,	0xDE,	0x40,
+0xF7,	0x43,	0x51,	0x93,	0xC8,	0x67,	0x24,	0xD0,
+
+0xF5,	0x17,	0xE5,	0xE8,	0x34,	0xF7,	0x20,	0x8B,
+0x85,	0x3D,	0x4C,	0x52,	0x0F,	0x2E,	0xA3,	0x79,
+
+0x11,	0xB0,	0x06,	0x48,	0xA3,	0x54,	0x43,	0x7A,
+0x29,	0x48,	0xE7,	0xD7,	0xBE,	0xE4,	0x5E,	0x25,
diff --git a/board/rda/common/include/freh3_h264_99f_hp_cif.txt b/board/rda/common/include/freh3_h264_99f_hp_cif.txt
new file mode 100644
index 0000000000..da02055e52
--- /dev/null
+++ b/board/rda/common/include/freh3_h264_99f_hp_cif.txt
@@ -0,0 +1,8666 @@
+0x01000000,	0x1E006427,	0x2B1B00AD,	0x00598205,	0x28010000,	0xC09840EA,	0x01000030,	0x00808825,
+0x31E20F40,	0x4F4E00E4,	0x1BFFCEC3,	0xA7BA6313,	0xA5C89A2D,	0xC81902F5,	0xF19C35EE,	0x3A6A0CB6,
+0x0C314132,	0xCE342C1D,	0x2EF191BA,	0x389FDE74,	0x3288AE24,	0x2D155A36,	0x2D0A6D2B,	0x84209A88,
+0x30A7AD41,	0xBC078AC0,	0x1231B638,	0xF45E131D,	0x1B6CC7A5,	0x290F9A7F,	0xF88224B7,	0x87BA7A3D,
+0x27C89540,	0xFFFFD75C,	0xBE0F9CFD,	0x1EE691D7,	0x10A11B7F,	0x6E9C5032,	0x85EB07F6,	0x0BFA82A2,
+0x3C3576DC,	0xF392A2EF,	0xBCD684EC,	0xBA3372C3,	0x30B4A325,	0x47F82D03,	0x4879D88C,	0x99CC0890,
+0xA908DA8A,	0x315AF8E1,	0xAA5CB184,	0x28864576,	0xF8E52938,	0x8EC32C8D,	0xA88F1390,	0x470BD15B,
+0xAEDFCE16,	0xD1FEEC95,	0x565FC61E,	0x06050EC8,	0x1D9F84B4,	0x56582F66,	0x254247FE,	0x48FB7D24,
+0xA4E83F38,	0x87021B8B,	0x5A2A7258,	0x2F6D645F,	0x113D4BA6,	0xD262284F,	0xF3A37BD6,	0x56FFFF30,
+0xEF3447AF,	0xF7F0178E,	0x1350E274,	0x2F4AE1DB,	0x2FABA33B,	0x02B4F8A7,	0x1A7061C4,	0x65C338CB,
+0x61DAA898,	0x61DA8D39,	0x4A836B34,	0x66ADC22F,	0x23ED184B,	0xE42F2AAF,	0x7BE26C7C,	0x833D838B,
+0xDFEDD532,	0x1DA3CB0B,	0x37071078,	0xB62F228B,	0xB8B7FBD2,	0x3CF37DA1,	0xD833B3C9,	0x742FBD1F,
+0x6DDBB63C,	0x0EEBA3E2,	0xD337929C,	0x50AAF2ED,	0x484B4E94,	0x980D7074,	0xBEECA612,	0xB60426AC,
+0x764BF27E,	0xD6569350,	0xF2BEB8FE,	0xC6E1A748,	0x97E0FFE7,	0xBBC10065,	0xD1F1E333,	0xCFE81FF6,
+0x1CE35EBE,	0x5CF04007,	0xE8EDAFF4,	0xF0D98996,	0x2CD1EF94,	0xA310ACF5,	0x88E9ED1D,	0x3726C256,
+0x1FAAE43A,	0x15EF9CCB,	0x115BB1C1,	0xEB5DC32D,	0xE2ED70E0,	0x33F69DB8,	0x9F2BEA50,	0xA51D7C2C,
+0xC5242BF7,	0x418D293A,	0x36A6805B,	0xC544A410,	0x9D7B2418,	0xD9307D1F,	0x6481B93C,	0xB86D197E,
+0x8DF75CA0,	0xC40440CA,	0x5B1A31F7,	0xC065527A,	0xE650428D,	0x4F2CEFD1,	0xFA444D5A,	0xA3AA944A,
+0xC2A9BDC7,	0x7E2C08E8,	0x5D7810D3,	0xCF292994,	0x9B551B55,	0x228CA047,	0xB06D2913,	0x407FA14F,
+0x040781EF,	0x1CC2B503,	0x8EF719B4,	0x06A5CC40,	0x241CA11C,	0xCE2F17A3,	0x1A5EC74F,	0x7978DCEB,
+0x43F2CE37,	0x5A165DB2,	0x1343CE8B,	0x3E3010DD,	0xB8FA69F1,	0x786932A1,	0x00C44AC9,	0xF60CD0C7,
+0xC754C41C,	0x4944172E,	0xFC096971,	0xC73312DC,	0x4ABFBB9E,	0x94F399CF,	0xEC4C01E2,	0xF738C1F1,
+0xBD42416A,	0x4919CF28,	0xA9953C2C,	0x88734FEF,	0x6CCDE521,	0x21266162,	0xC13DA4AC,	0x54B79EEA,
+0x83E08975,	0xEE32202D,	0x2BB646FB,	0x269D3336,	0x79420C71,	0x94E47412,	0xB2767B94,	0x1D4CAE27,
+0x37ADE265,	0x72C41F94,	0x0E9C402D,	0x845B8C22,	0x2553D26C,	0x91429DF1,	0x1B2E86F7,	0xD267D3EB,
+0x9576DD3B,	0x8124B19F,	0xE16696E4,	0x3C268B23,	0x673B4AF1,	0xA0A648DD,	0xDF6EB1D6,	0xAAA900FA,
+0x4D572697,	0x1CA1729F,	0x94D9D29F,	0x31CAFB37,	0x643E0F5F,	0xC88D93D0,	0x6C445E22,	0xB55AA0E0,
+0x8CFC6CEB,	0xA05E7EE7,	0xB1939498,	0x0C583C2B,	0xA3A6E757,	0xFB0F13F3,	0xC2D8C2B2,	0x83CC35C2,
+0x88C5FA61,	0x47E02C93,	0xBF31261E,	0x0B26DAD7,	0xFD92199C,	0xBF854821,	0x72D49FC5,	0x5AEF4517,
+0x28D2DD29,	0x6AB3B1E7,	0xA3691EB0,	0x3E2DEB60,	0x60B7D892,	0x1034F0A7,	0x1402BC4D,	0x02F3DCAE,
+0xCE4E1CD6,	0x2304A402,	0x277A80EF,	0x444C9DE8,	0x4FD7ECD6,	0xEDDCCD63,	0x17CE04E4,	0x23F0EAFC,
+0x18376F20,	0x7606B8E2,	0x6F59E7A1,	0xD907EA5C,	0xA244FF6B,	0x0BFCFF1E,	0x4FB3E6E1,	0x9EFF930F,
+0x30264EE0,	0x8505A7DE,	0xC5CCF604,	0xCF03D5F5,	0x1BEE36D4,	0xB6FAB188,	0x816379B1,	0x55FBA6ED,
+0x5F9E9C4A,	0xA792E346,	0xEC93A76C,	0x2010B786,	0xBBB4A034,	0xE43E7958,	0x3D946104,	0xBD21E249,
+0x0511E863,	0x634A7FC0,	0x444D3442,	0xA8C6B46F,	0xFC409759,	0x055E0860,	0xEEE460A2,	0x9FE606A7,
+0xBDA8DFBC,	0x9C1B4A48,	0x196C3499,	0x2410A7F3,	0x2F1D5693,	0x8B6C3DFF,	0x6ED22AF4,	0xF5821C32,
+0xD8CB7FF9,	0x113EA778,	0x50308886,	0x2883C8EC,	0x15707CE1,	0x3DD75CFA,	0x7E7819B9,	0xF74311D0,
+0xFCE4D010,	0xFDD4EF16,	0x09CEA3B4,	0x81528FF5,	0x5AE7A6DF,	0x78F4668C,	0x8329967D,	0x3F10178B,
+0x0D89396B,	0xFD790611,	0xD45FFB40,	0x18354587,	0xA4AEE262,	0x03BDCF11,	0x684205BC,	0x128E41B4,
+0xE4A75A92,	0x0515C78C,	0x56A15D0F,	0x085EA6BF,	0xF6196ACC,	0x8A61E69C,	0xAF6B5726,	0x583E2F3F,
+0xD125C197,	0xA0C7EFD6,	0xB1068E38,	0xA1A56DF2,	0x5F02D5E0,	0x054FA0EE,	0x1EF59693,	0x178FE67C,
+0xDE10422A,	0x86115CA5,	0x2F45604F,	0xCF5B949C,	0xF4289E00,	0x43457D6A,	0x71EA2054,	0x20C05D28,
+0xCF49A68D,	0x272D0F32,	0x579028BC,	0x56CCCBBF,	0x8D5006A9,	0x8F233248,	0xDD3656CE,	0x0F485DE9,
+0xC6B69592,	0x6F96400F,	0xA1E7CD2B,	0x21413520,	0x6F62B9C2,	0xD7E6A6BE,	0xDE810DE1,	0xF11E0429,
+0x9DDD46EC,	0x97C227FA,	0x9BEF5BB8,	0x191FA59A,	0xBD9A0349,	0x1BC526A6,	0x07CAEBB5,	0x889E9286,
+0xEFAB2825,	0x21CD8342,	0x7B2EC28A,	0xB8EBA30B,	0x88CA2F31,	0xDD46F111,	0xD0FF35EA,	0x5F0844D0,
+0x5F497819,	0x4BD870EC,	0xFDDA6753,	0x4233C155,	0x33A2A57E,	0x1A947E90,	0x454617B2,	0xC9983C0C,
+0x25426A31,	0x35801072,	0x83CABC3F,	0x4AD33E7C,	0x06C199BD,	0xA3A37531,	0x447979B0,	0xACC806C0,
+0x66558A7A,	0x95900805,	0xEE580A15,	0x5BD0C217,	0x466007BC,	0x0F1635BC,	0x7C6C79FA,	0x102F7846,
+0x10F6B355,	0x2253BB68,	0xF3078F8C,	0x73768642,	0x2F0FCD59,	0xAB016465,	0x0634465A,	0xB0F20D6E,
+0xDD6BEAEC,	0x26CFA7E1,	0x51636D00,	0x6D8DFB3E,	0x01ADE59C,	0xA264B022,	0xE9C725EC,	0x7566161D,
+0xB5FF7E2B,	0x3A594D3E,	0xCAA6FE0C,	0xAC1A70D3,	0x2C06A16B,	0x7A55CBA9,	0x17F70447,	0x32BB6C30,
+0x81A13D3F,	0x3F4ED12E,	0x2E8FE98B,	0x60522A94,	0xEB815F6E,	0xDC8BE133,	0x0768B45D,	0xEA62A02C,
+0x284771EC,	0xB7793AAC,	0x8C926F58,	0x18D69C0A,	0x128054F0,	0xBDD399BE,	0x46DF4ED8,	0xD671FB22,
+0x805F8EB5,	0xE42C2063,	0x84E2C1F5,	0xE3ABCB6A,	0xD32B5724,	0xD861B37F,	0x627604BD,	0x79B340F4,
+0x6F5E754B,	0xDE1E78DA,	0x017EF28B,	0x1E187DA4,	0xC2B090C0,	0x854F9B22,	0x649B4766,	0x95CCECFE,
+0x533CE82E,	0x02A55244,	0xCB038149,	0x7AD52824,	0x2970887B,	0xA5103309,	0xD03959BB,	0x8EBC221B,
+0x3F726A4F,	0xC3E896DF,	0x56968F7F,	0xAFD3DBD9,	0x42DE3CCB,	0xDAB59D65,	0x72D29135,	0xB76363DA,
+0x1B234056,	0xB079B25D,	0xE27D4B5F,	0x50400E4F,	0x8121B760,	0x1C3055A2,	0xCC024ED8,	0xB686861C,
+0xCEA91365,	0x74EC5159,	0x3713F3BC,	0xEAC0F7BF,	0xC2C9A6D1,	0xDA7A4C5E,	0x7775F81F,	0x1037B16A,
+0x6CF53B71,	0x6FA9005F,	0x58E085A2,	0xCD2D5E36,	0xC939C4D7,	0x13AB45FD,	0x33E732FE,	0x86E2E797,
+0xA5C39D12,	0x74627D64,	0x8B7345A4,	0xB15C98A9,	0x13CAF8AA,	0x64CC9FE8,	0x070078C0,	0x8A988CB0,
+0xE482EAAB,	0xAE30B180,	0xF7AFF2CD,	0xED180C4E,	0x20A8FE98,	0xD49AE3F3,	0x5648F45A,	0x8FB3254E,
+0x870E61EA,	0x788F20A7,	0x3C87BCE9,	0xB69E403E,	0x9CB4AC07,	0xA794ADC7,	0x6C7DAD89,	0xF74BB01D,
+0x7713E6FB,	0x986144C0,	0x1B648A53,	0x15EAB191,	0xB6B0B962,	0x3DB6A517,	0xAD1E28BE,	0xD6F66573,
+0x2861F99F,	0x2939B2BC,	0xBAFE3DA4,	0xA54AEC2C,	0x9EBBF163,	0x9611C2E9,	0xF6A35EC4,	0x74BB5650,
+0x1E7A98D1,	0x75169062,	0xDE6D8C44,	0xDBB39DA4,	0xCCD5D089,	0x97B7AD98,	0x6256DF3B,	0xD673424E,
+0x8596A880,	0x6F5F44B5,	0xB43D5C79,	0x9E51DAB9,	0xAF8103F3,	0x59C10D27,	0xF4FBB45D,	0x5362F2F2,
+0xDB9A97CE,	0x75A3FA0B,	0xD617CEFD,	0x2DE959A9,	0x66478238,	0xA2EFAA79,	0x8A1E6EE9,	0xA034EE4D,
+0x92FE767B,	0xB561FACA,	0x97028D78,	0x726C1B0F,	0x54867F2E,	0x15FC4B73,	0xE6002C5E,	0xB01F4AA6,
+0x1FA6D77C,	0x41C2A0AA,	0x98E19DD4,	0x83F083C1,	0x6A2F65EB,	0x047020D8,	0xB015A5DA,	0x7E514D4B,
+0x5F81671F,	0x13DB1CCC,	0xAC51859F,	0x807D56BD,	0x79C6CDAB,	0x5D94BEC1,	0x8DA15D21,	0x96D5A2B6,
+0x7F338C16,	0x579663CC,	0x627F53A7,	0xB826339E,	0x4CE0FDE5,	0x5333AD6B,	0x6FE8065F,	0x1637B655,
+0x00030AE1,	0x4A1B77AA,	0xA7F087E4,	0xE30A4D8D,	0xEC12C3EB,	0x38070BF9,	0x99FD28D7,	0xCECF48D1,
+0x6475399C,	0xE2283882,	0x221E8B5A,	0xACB362B7,	0x46F5D538,	0x5ABB453A,	0xBE39F0E4,	0xEB2B53FB,
+0x193A7E90,	0x7F63508D,	0xA488296C,	0x2D3E7DE2,	0x26FB9A49,	0xCF4EEC7F,	0x2B71978D,	0x0729B8DE,
+0x58C652E0,	0x00CF0FD7,	0x1534C2EF,	0xCA71F60D,	0xDD4FCABF,	0x1D3671FA,	0x351618CF,	0x8F7A8FD9,
+0xAB082627,	0x19B87D1F,	0xB613ED4C,	0x7D22D166,	0x1383F468,	0x8D6CD052,	0x01D096E1,	0xAD2B75BD,
+0xEFC54110,	0x0F79997B,	0x512D39AC,	0x8CDA74F5,	0x688B09BB,	0x008EC1D4,	0x62D4A213,	0xB8AEEA98,
+0x6E286F3A,	0xF0A2DD54,	0xD02A49CB,	0x2D5F0904,	0x4A4DB105,	0x20301E96,	0xDF1CC173,	0xD7FF009C,
+0x3FB0DA7B,	0x42557FE2,	0x402B31EE,	0xDB26EA56,	0xB28AF4EA,	0x60F68B38,	0xA2EE0434,	0x2C48B881,
+0x1B0A70EF,	0x2AC47B6C,	0xE679F668,	0xE64BA9CC,	0x60392858,	0xF0B7FD29,	0x37432859,	0x546271DB,
+0x1640E004,	0x7CB2DEED,	0xC94DAF98,	0x9E64B2FC,	0x3555EF4B,	0xDCB4F4F3,	0xF2CCCCFD,	0x1006C036,
+0xB0B698BB,	0x2E0D7F3C,	0xC51FF2F2,	0x545B34DF,	0xC0DFDB3D,	0xD305E1B9,	0x2963394D,	0x9C2846DA,
+0x6FFDBA01,	0x1D387AE1,	0x7FB43E29,	0x20593CB0,	0xF449167A,	0xCCDA54A8,	0xED5BFB02,	0x99454AF5,
+0x330C6504,	0x854EAD16,	0xEFE54576,	0x7EB47DB2,	0x0AA42AE8,	0x30D21F89,	0x229E3E3B,	0x19B05285,
+0x80C13533,	0x9CE6D736,	0xF20443F8,	0x703D71F0,	0xC9391224,	0x8B9DE398,	0x1CF05C08,	0x2C761E91,
+0x0E9D6CEF,	0xF9145995,	0x06A740AD,	0x2BA3EE22,	0x5CDC6D68,	0xF4DD9C1B,	0x1636309D,	0x198C339B,
+0x8C232A1F,	0x99A9E9F8,	0x3A403C81,	0xA06D98F2,	0x86E42D56,	0xC0A7BD4B,	0x7CAEBDD1,	0xE91F5CD1,
+0x18D6B0AA,	0x277047B4,	0xA201D256,	0xF7404D7B,	0x72BD4518,	0xD5D3B1CC,	0x5C1B7D92,	0x987822EC,
+0xAA2CA911,	0x7A2B8FD5,	0x8910C121,	0xB0F31769,	0x98D3A37C,	0x3BAD280B,	0x264CF4AE,	0x15333639,
+0x7D15549F,	0x57BDC92E,	0x08D1DDB6,	0x7B3CFAD5,	0xE8F6DB07,	0x8A8D4B89,	0xA90E2F39,	0xE5AB8358,
+0x9C3EAC59,	0xEB329B11,	0xFCA9263B,	0x24ED4E34,	0xD3AEC949,	0x09B2A94A,	0x5F5F19CC,	0x14DC1FB2,
+0x39A188BB,	0xCF0E532B,	0x0BE1BC2D,	0xFDB46738,	0xBA08C2C4,	0xFB206E0F,	0x7A4305E8,	0x0D1D0174,
+0x791C709A,	0x3B3E4B9D,	0x921AE27D,	0xF3ADD8C0,	0x13E65B14,	0xE2C96A9B,	0x944F4D3C,	0x410FCA86,
+0x9D4F7528,	0xD3E1F336,	0x41B3B573,	0x57638F1E,	0x47551EF9,	0x83F2EE23,	0xB385F8D5,	0xFC1133FB,
+0xAECDE7A0,	0x79580C01,	0x66202190,	0x9DBA214C,	0xF10872E6,	0xE6135574,	0x52593E42,	0x87EAE0C3,
+0x94BCD124,	0xBCC9302D,	0xE7A8F82C,	0xBFB263A9,	0x0D120F36,	0xEC156372,	0x33391D5A,	0xA3D3A35B,
+0x7D65F7E2,	0x81294D21,	0x23637ADA,	0xDCE1141E,	0x799D3D58,	0xF1A92431,	0xAC500A7C,	0x4ECB2D9E,
+0xD70E92D5,	0xF799BBD0,	0x07CE41C5,	0x8D3E2F29,	0x2DE1D5D6,	0xCEAB711B,	0x8D3DFEDA,	0x8908CE27,
+0xD4375F80,	0x5C549EFE,	0x82DE0972,	0x9043F0FA,	0x45A97BEC,	0xD9439BDC,	0x105A7020,	0x74005A54,
+0x29B7F089,	0xE809BB12,	0xB1E43538,	0xD99F915B,	0x670B1C93,	0x836502D3,	0x260FCFC9,	0x2E3904E5,
+0x0835D19E,	0xA5BFDB18,	0x84B3BE34,	0x34B80B9F,	0x59358E6B,	0xCD0D52A3,	0x343F8961,	0xD26C82C3,
+0x729A4083,	0xEF8B91C9,	0x6F038541,	0x5D0A446E,	0x47F24111,	0x5C8DE7C9,	0x80FE9E8D,	0x1A2FB2BF,
+0x301B905D,	0x840FA54A,	0xB2CC68EC,	0x2483ADDE,	0x794B4D22,	0x222C5342,	0x34A12D5E,	0x619F3485,
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+0x1EDA6602,	0x5AC7333E,	0xBF388F07,	0xAB215695,	0x0909C826,	0x30290873,	0xD77CE62D,	0xF3ED6D8C,
+0xF5AEB6DB,	0x97ECCFFC,	0x0ED3FA19,	0xA72E15B4,	0x6E5A8A4E,	0x0C723164,	0x971359A0,	0x841D2260,
+0x862D14C9,	0xA2DB52B6,	0x3A353DFC,	0xC4CA669B,	0x53B2DED7,	0x56C9D7F6,	0x9445548E,	0x98061A26,
+0xC7F629B5,	0xB7BFFAAD,	0xFD78EEF4,	0x50553006,	0xAB8E11A4,	0xE28FCDFF,	0x766EEEE4,	0x59CD27DF,
+0x8A18EDC4,	0x9EDA78D8,	0xDBE7878F,	0x3B247B97,	0xB20F9039,	0xCDE0F99F,	0x3B0A2220,	0x1EE895CB,
+0x99A8D3E7,	0xEE0F0E7E,	0x5F460462,	0xB947B2EB,	0xB444E57D,	0x06410519,	0x4E49B779,	0xC80801C4,
+0xA5D5A75E,	0x1E2B42C9,	0x5B74BF42,	0xC43B27DF,	0x462A90C0,	0xC9BAEAF9,	0x7A13EEFA,	0x356BD93E,
+0xC2D093E3,	0x27E82A2D,	0xC6D84066,	0x3AB85D92,	0xA980C82E,	0xD8DCD61A,	0xA349787E,	0x10D1CE49,
+0xB05C062D,	0x1E9A6FB1,	0xEA29A9DC,	0xF13E1ED5,	0xFC3CDDFA,	0xE53DB35C,	0xF5BF5040,	0xE9D21B26,
+0xEF4FD684,	0x7EAD03A5,	0xD57E1FB1,	0x22F31869,	0xDB84ACB8,	0x8CF50A44,	0x451FB297,	0xFCFA954B,
+0x52513109,	0x07ACAFF1,	0x281A3024,	0x5C82B3CD,	0x9455E05E,	0x91615912,	0x50D96A20,	0xA48B3A89,
+0x892E2AD7,	0x2CAE0F46,	0x9FBB73DE,	0x60C8129F,	0x6D522730,	0xB5B6D663,	0x6AC0AA06,	0x82C3F277,
+0xB9981F3C,	0x85B5FB0B,	0x184FBBA2,	0xDF55E4AF,	0x0304D708,	0xD0FDB30E,	0x0040EBAE,	0x000A0100,
diff --git a/board/rda/common/include/hal_ap_config.h b/board/rda/common/include/hal_ap_config.h
new file mode 100644
index 0000000000..8452471975
--- /dev/null
+++ b/board/rda/common/include/hal_ap_config.h
@@ -0,0 +1,178 @@
+/*
+* devices.c - RDA platform devices
+*
+* Copyright (C) 2013 RDA Microelectronics Inc.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; either version 2 of the License, or
+* (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*
+*/
+
+#ifndef _HAL_AP_AP_CONFIG_H_
+#define _HAL_AP_AP_CONFIG_H_
+
+#define CHIP_AP_STD_UART_QTY            3
+#define CHIP_AP_STD_SPI_QTY             3
+
+#define CHIP_AP_GOUDA_MAGIC_NUM         0x12345678
+#define CHIP_AP_LCD_MAGIC_NUM           0x81234567
+#define CHIP_AP_USB_MAGIC_NUM           0x78123456
+#define CHIP_AP_BT_MAGIC_NUM            0x67812345
+#define CHIP_AP_CAM_MAGIC_NUM           0x56781234
+#define CHIP_AP_LED_MAGIC_NUM           0x45678123
+#define CHIP_AP_MMC_MAGIC_NUM           0x34567812
+#define CHIP_AP_EARPHONE_MAGIC_NUM      0x23456781
+#define CHIP_AP_LOUDSPK_MAGIC_NUM       0x12345678
+
+/* Synced with iomap @ap side */
+#define CHIP_AP_SHARED_MEMORY_SIZE      0x00010000
+#define CHIP_AP_SHARED_MEMORY_BASE      0x00100000
+
+/* **********************************************************
+*   gouda cofig
+*
+*   bankId    GPIO_A ,GPIO_B,GPIO_D??
+*   goudaResetPin
+*
+*************************************************************/
+struct HAL_AP_GOUDA_T{
+    int magic;
+    enum gpio_id reset_pin;
+};
+
+/* **********************************************************
+*   lcd cofig
+*
+*   bankId    GPIO_A ,GPIO_B,GPIO_D??
+*   lcdResetPin
+*
+*************************************************************/
+struct HAL_AP_LCD_T{
+    int magic;
+    enum gpio_id reset_pin;
+};
+
+/* **********************************************************
+*   usb cofig
+*
+*   bankId    GPIO_A ,GPIO_B,GPIO_D??
+*   usbResetPin
+*
+*************************************************************/
+struct HAL_AP_USB_T
+{
+    int magic;
+    enum gpio_id reset_pin;
+};
+
+/* **********************************************************
+*   bt cofig
+*
+*   bankId    GPIO_A ,GPIO_B,GPIO_D??
+*   btResetPin
+*
+*************************************************************/
+struct HAL_AP_BT_T{
+    int magic;
+    enum gpio_id reset_pin;
+};
+
+/* **********************************************************
+*   cam cofig
+*
+*   bankId    GPIO_A ,GPIO_B,GPIO_D??
+*   camResetPin
+*
+*************************************************************/
+struct HAL_AP_CAM_T{
+    int magic;
+    enum gpio_id reset_pin;
+};
+
+/* **********************************************************
+*   led cofig
+*
+*   bankId    GPIO_A ,GPIO_B,GPIO_D??
+*   ledResetPin
+*
+*************************************************************/
+struct HAL_AP_LED_T{
+    int magic;
+    enum gpio_id reset_pin;
+};
+
+/* **********************************************************
+*   mmc cofig
+*
+*   bankId    GPIO_A ,GPIO_B,GPIO_D??
+*   mmcResetPin
+*
+*************************************************************/
+struct HAL_AP_MMC_T{
+    int magic;
+    enum gpio_id reset_pin;
+};
+
+/* **********************************************************
+*   earphone cofig
+*
+*   bankId    GPIO_A ,GPIO_B,GPIO_D??
+*   earphoneResetPin
+*
+*************************************************************/
+struct HAL_AP_EARPHONE_T{
+    int magic;
+    enum gpio_id reset_pin;
+};
+
+/* **********************************************************
+*   loudspk cofig
+*
+*   bankId    GPIO_A ,GPIO_B,GPIO_D??
+*   loudSpkResetPin
+*
+*************************************************************/
+struct HAL_AP_LOUDSPK_T{
+    int magic;
+    enum gpio_id reset_pin;
+};
+
+/* **********************************************************
+*   configure gpio used by ap
+*
+*
+*************************************************************/
+struct HAL_AP_CFG_CONFIG_T{
+    struct HAL_AP_GOUDA_T       gouda_cfg;
+    struct HAL_AP_LCD_T         lcd_cfg;
+    struct HAL_AP_USB_T         usb_cfg;
+    struct HAL_AP_BT_T          bt_cfg;
+    struct HAL_AP_CAM_T         cam_cfg;
+    struct HAL_AP_LED_T         led_cfg;
+    struct HAL_AP_MMC_T         mmc_cfg;
+    struct HAL_AP_LOUDSPK_T     loudspk_cfg;
+    struct HAL_AP_EARPHONE_T    earphone_cfg;
+
+    int noConnectGpio_A;
+    int usedGpio_A;
+    int usedGpo_A;
+    int noConnectGpio_B;
+    int usedGpio_B;
+    int noConnectGpio_D;
+    int usedGpio_D;
+};
+
+
+#endif // _HAL_AP_AP_CONFIG_H_
+
diff --git a/board/rda/common/include/hal_ap_gpio.h b/board/rda/common/include/hal_ap_gpio.h
new file mode 100644
index 0000000000..32e6317a9a
--- /dev/null
+++ b/board/rda/common/include/hal_ap_gpio.h
@@ -0,0 +1,111 @@
+#ifndef __MACH_GPIO_ID_H__
+#define __MACH_GPIO_ID_H__
+
+enum gpio_id {
+    GPIO_NONE = -1,
+    GPIO_A0 = 0,
+    GPIO_A1,
+    GPIO_A2,
+    GPIO_A3,
+    GPIO_A4,
+    GPIO_A5,
+    GPIO_A6,
+    GPIO_A7,
+    GPIO_A8,
+    GPIO_A9,
+    GPIO_A10,
+    GPIO_A11,
+    GPIO_A12,
+    GPIO_A13,
+    GPIO_A14,
+    GPIO_A15,
+    GPIO_A16,
+    GPIO_A17,
+    GPIO_A18,
+    GPIO_A19,
+    GPIO_A20,
+    GPIO_A21,
+    GPIO_A22,
+    GPIO_A23,
+    GPIO_A24,
+    GPIO_A25,
+    GPIO_A26,
+    GPIO_A27,
+    GPIO_A28,
+    GPIO_A29,
+    GPIO_A30,
+    GPIO_A31,
+    GPIO_B0 = 32,
+    GPIO_B1,
+    GPIO_B2,
+    GPIO_B3,
+    GPIO_B4,
+    GPIO_B5,
+    GPIO_B6,
+    GPIO_B7,
+    GPIO_B8,
+    GPIO_B9,
+    GPIO_B10,
+    GPIO_B11,
+    GPIO_B12,
+    GPIO_B13,
+    GPIO_B14,
+    GPIO_B15,
+    GPIO_B16,
+    GPIO_B17,
+    GPIO_B18,
+    GPIO_B19,
+    GPIO_B20,
+    GPIO_B21,
+    GPIO_B22,
+    GPIO_B23,
+    GPIO_B24,
+    GPIO_B25,
+    GPIO_B26,
+    GPIO_B27,
+    GPIO_B28,
+    GPIO_B29,
+    GPIO_B30,
+    GPIO_B31,
+    GPIO_D0 = 64,
+    GPIO_D1,
+    GPIO_D2,
+    GPIO_D3,
+    GPIO_D4,
+    GPIO_D5,
+    GPIO_D6,
+    GPIO_D7,
+    GPIO_D8,
+    GPIO_D9,
+    GPIO_D10,
+    GPIO_D11,
+    GPIO_D12,
+    GPIO_D13,
+    GPIO_D14,
+    GPIO_D15,
+    GPIO_D16,
+    GPIO_D17,
+    GPIO_D18,
+    GPIO_D19,
+    GPIO_D20,
+    GPIO_D21,
+    GPIO_D22,
+    GPIO_D23,
+    GPIO_D24,
+    GPIO_D25,
+    GPIO_D26,
+    GPIO_D27,
+    GPIO_D28,
+    GPIO_D29,
+    GPIO_D30,
+    GPIO_D31,
+    GPO_0 = 96,
+    GPO_1,
+    GPO_2,
+    GPO_3,
+    GPO_4,
+    GPIO_MAX_NUM
+};
+
+#endif
+
diff --git a/board/rda/common/include/hal_camera.h b/board/rda/common/include/hal_camera.h
new file mode 100644
index 0000000000..dd50c60092
--- /dev/null
+++ b/board/rda/common/include/hal_camera.h
@@ -0,0 +1,360 @@
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//            Copyright (C) 2012-2020,RDA, Inc.            //
+//                            All Rights Reserved                             //
+//                                                                            //
+//      This source code is the property of Coolsand Technologies and is      //
+//      confidential.  Any  modification, distribution,  reproduction or      //
+//      exploitation  of  any content of this file is totally forbidden,      //
+//      except  with the  written permission  of  RDA      //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+
+
+#ifndef _HAL_CAMERA_H_
+#define _HAL_CAMERA_H_
+
+#include "asm/arch/cs_types.h"
+#include "hal_gpio.h"
+// =============================================================================
+// HAL_CAMERA_IRQ_CAUSE_T
+// -----------------------------------------------------------------------------
+/// Describes the camera interrupt cause.
+// =============================================================================
+typedef struct
+{
+    /// An overflow occured.
+    UINT8 overflow:1;
+
+    /// Frame start interrupt cause.
+    UINT8 fstart:1;
+
+    /// Frame end interrupt cause.
+    UINT8 fend:1;
+
+    /// DMA done interrupt cause.
+    UINT8 dma:1;
+} HAL_CAMERA_IRQ_CAUSE_T;
+
+
+// =============================================================================
+// HAL_CAMERA_ENDIANESS_T
+// -----------------------------------------------------------------------------
+/// Camera endiannes. Defines the swapping operation done on any 32 bits of
+/// received data from the camera data flow, to get pixels in the proper order.
+// =============================================================================
+typedef enum
+{
+    /// No reordering.
+    NO_SWAP=0,
+
+    /// Bytes order is inverted.
+    BYTE_SWAP=1,
+
+    /// 16 bits data are swapped.
+    HALF_WORD_SWAP=2,
+
+    /// Bits are swapped.
+    BIT_SWAP=3
+} HAL_CAMERA_ENDIANESS_T;
+
+
+// =============================================================================
+// HAL_CAMERA_XFER_STATUS_T
+// -----------------------------------------------------------------------------
+/// Describes the status returned by the #hal_CameraStopXfer() function.
+// =============================================================================
+typedef enum
+{
+    /// The transfer finished properly, the whole image
+    /// has been received.
+    XFER_SUCCESS,
+
+    /// The transfer has not finished.
+    XFER_NOT_FINISHED,
+
+    /// The transfer finished, but an overflow occured.
+    /// There is probably a misconfiguration between
+    /// the number of pixels expected and the camera
+    /// resolution configuration.
+    XFER_FINISHED_WITH_OVERFLOW,
+
+    /// There was no IFC configured for a transfer.
+    /// #hal_CameraStopXfer() was called before
+    /// #hal_CameraStartXfer() ?
+    XFER_ERR_WRONG_PARAM
+} HAL_CAMERA_XFER_STATUS_T;
+
+// =============================================================================
+// HAL_CAMERA_ROW_RATIO_T
+// -----------------------------------------------------------------------------
+/// Describes the row pixel decimation ratio.
+// =============================================================================
+typedef enum
+{
+    /// Original size, decimation disabled, 1/1.
+    ROW_RATIO_1_1,
+
+    /// Row pixel decimation 1/2.
+    ROW_RATIO_1_2,
+
+    /// Row pixel decimation 1/3.
+    ROW_RATIO_1_3,
+
+    /// Row pixel decimation 1/4.
+    ROW_RATIO_1_4,
+} HAL_CAMERA_ROW_RATIO_T;
+
+
+// =============================================================================
+// HAL_CAMERA_COL_RATIO_T
+// -----------------------------------------------------------------------------
+/// Describes the column pixel decimation ratio.
+// =============================================================================
+typedef enum
+{
+    /// Original size, decimation disabled, 1/1.
+    COL_RATIO_1_1,
+
+    /// Column pixel decimation 1/2.
+    COL_RATIO_1_2,
+
+    /// Column pixel decimation 1/3.
+    COL_RATIO_1_3,
+
+    /// Column pixel decimation 1/4.
+    COL_RATIO_1_4,
+} HAL_CAMERA_COL_RATIO_T;
+
+#if (CHIP_HAS_ASYNC_TCU)
+
+typedef enum {
+    SPI_MODE_NO = 0,         // parallel sensor in use
+    SPI_MODE_SLAVE ,        // SPI sensor as SPI slave
+    SPI_MODE_MASTER1,     // SPI sensor as SPI master, 1 sdo output with SSN
+    SPI_MODE_MASTER2_1, // SPI sensor as SPI master, 1 sdo output without SSN
+    SPI_MODE_MASTER2_2, // SPI sensor as SPI master, 2 sdos output
+    SPI_MODE_MASTER2_4, // SPI sensor as SPI master, 4 sdos output
+    SPI_MODE_UNDEF,
+} HAL_CAMERA_SPI_MODE_E;
+
+typedef enum {
+    SPI_OUT_Y0_U0_Y1_V0 = 0,
+    SPI_OUT_Y0_V0_Y1_U0,
+    SPI_OUT_U0_Y0_V0_Y1,
+    SPI_OUT_U0_Y1_V0_Y0,
+    SPI_OUT_V0_Y1_U0_Y0,
+    SPI_OUT_V0_Y0_U0_Y1,
+    SPI_OUT_Y1_V0_Y0_U0,
+    SPI_OUT_Y1_U0_Y0_V0,
+} HAL_CAMERA_SPI_YUV_OUT_E;
+#endif // (CHIP_HAS_ASYNC_TCU)
+// =============================================================================
+// HAL_CAMERA_CFG_T
+// -----------------------------------------------------------------------------
+/// Camera configuration. This structure is used by #hal_CameraOpen() to
+/// configure how the chip and the camera sensors are connected, and which
+/// camera sensor to use in case there would be two.
+// =============================================================================
+typedef struct
+{
+	/// Reset line polarity. Active high if \c TRUE.
+	BOOL rstActiveH;
+	/// Power DOWN line polarity. Active high if \c TRUE.
+	BOOL pdnActiveH;
+	/// If \c TRUE, all even frame are skipped.
+	BOOL dropFrame;
+	// Enable window crop
+	BOOL cropEnable;
+	/// Clock divider to apply to produce the camera clock
+	/// from the 156 MHz clock.
+	UINT8 camClkDiv;
+	UINT8 reOrder;
+	BOOL  vsync_inv;
+	/// Describes the swapping operation to apply to data
+	/// received from the camera sensor.
+	HAL_CAMERA_ENDIANESS_T endianess;
+	/// Id (0 or 1) of the camera to use.
+	UINT32 camId;
+	/// Row pixel decimation ratio
+	HAL_CAMERA_ROW_RATIO_T rowRatio;
+	/// Column pixel decimation ratio
+	HAL_CAMERA_COL_RATIO_T colRatio;
+	// start pixel of cropped window
+	UINT16 dstWinColStart;
+	// end pixel of cropped window
+	UINT16 dstWinColEnd;
+	// start line of cropped window
+	UINT16 dstWinRowStart;
+	// end line of cropped window
+	UINT16 dstWinRowEnd;
+#if (CHIP_HAS_ASYNC_TCU)
+	UINT16 spi_pixels_per_line;
+	UINT16 spi_pixels_per_column;
+	BOOL  spi_href_inv;
+	BOOL  spi_little_endian_en;
+	// ssn high enable, only for spi master mode 1
+	BOOL  spi_ssn_high_en;
+	UINT16 spi_ctrl_clk_div;
+	HAL_CAMERA_SPI_MODE_E       spi_mode;
+	HAL_CAMERA_SPI_YUV_OUT_E  spi_yuv_out;
+#endif //CHIP_HAS_ASYNC_TCU
+
+	/// The remapped GPIO controlling PDN (HAL_GPIO_NONE if not remapped), for the rear sensor.
+	HAL_APO_ID_T    camPdnRemap;
+	/// The remapped GPIO controlling RST (HAL_GPIO_NONE if not remapped), for the rear sensor.
+	HAL_APO_ID_T    camRstRemap;
+	HAL_APO_ID_T    cam1PdnRemap;
+	/// The remapped GPIO controlling RST (HAL_GPIO_NONE if not remapped), for the rear sensor.
+	HAL_APO_ID_T    cam1RstRemap;
+	BOOL                csi_mode;
+	UINT16		num_d_term_en;
+	UINT16		num_hs_settle;
+	UINT16		num_c_term_en;
+	UINT16		num_c_hs_settle;
+	u8			csi_cs;// 0 use csi1 . 1 use csi2
+	UINT16		frame_line_number;
+	u8 			csi_lane_2v8;
+
+} HAL_CAMERA_CFG_T;
+
+
+
+// =============================================================================
+// HAL_CAMERA_IRQ_HANDLER_T
+// -----------------------------------------------------------------------------
+/// Type for the user function called when a camera interrupt occurs.
+// =============================================================================
+typedef VOID (*HAL_CAMERA_IRQ_HANDLER_T)(HAL_CAMERA_IRQ_CAUSE_T cause);
+
+// =============================================================================
+// hal_CameraOpen
+// -----------------------------------------------------------------------------
+/// Enable the Camera Control module and set the default configuration
+/// for the selected external camera module.  It is both held in reset
+/// AND kept in power down.
+///
+/// In case of dual-sensor platform, the #camId field of the #camConfig
+/// parameter is to be used to select which sensor is to be enabled.
+///
+/// @param camConfig Camera configuration. (cf #HAL_CAMERA_CFG_T).
+// =============================================================================
+PUBLIC VOID hal_CameraOpen(HAL_CAMERA_CFG_T* camConfig);
+PUBLIC VOID hal_CameraPowerDownBoth(BOOL PowerDown);
+PUBLIC VOID hal_CameraClkOut(BOOL out);
+
+// =============================================================================
+// hal_CameraClose
+// -----------------------------------------------------------------------------
+/// Power off the camera sensor by setting the PowerDown bit.
+/// Resets the camera sensor by enabling the Camera Reset bit.
+/// This function can only be called after the camera transfer has been stopped
+/// by a call to #hal_CameraStopXfer().
+// =============================================================================
+PUBLIC VOID hal_CameraClose(VOID);
+
+
+// =============================================================================
+// hal_CameraReset
+// -----------------------------------------------------------------------------
+/// Controls the Reset line going to the sensor
+/// Uses the rstActiveH field of the configuration structure to know the polarity
+/// Should not be called before the open
+/// @param reset \c TRUE, the sensor is in reset
+///              \c FALSE, the sensor is out of reset
+// =============================================================================
+PUBLIC VOID hal_CameraReset(BOOL reset);
+
+
+// =============================================================================
+// hal_CameraPowerOn
+// -----------------------------------------------------------------------------
+/// Controls the PDN line going to the sensor
+/// Uses the pdnActiveH field of the configuration structure to know the polarity
+/// Should not be called before the open
+/// @param powerDown \c TRUE, the sensor is in Power Down
+///              \c FALSE, the sensor is out of Power Down
+// =============================================================================
+PUBLIC VOID hal_CameraPowerDown(BOOL powerDown);
+
+
+// =============================================================================
+// hal_CameraControllerEnable
+// -----------------------------------------------------------------------------
+/// Turns the Camera controller module On and Off
+/// Should not be called before the open
+/// @param enable \cTRUE, the Controller is active
+///               FALSE, the Controller is turned off
+// =============================================================================
+PUBLIC VOID hal_CameraControllerEnable(BOOL enable);
+
+
+// ============================================================================
+// hal_CameraIrqSetHandler
+// ----------------------------------------------------------------------------
+/// This function configures which user function will be called by the
+/// camera driver when an interruption is generated.
+///
+/// @param handler Pointer to a user function called when an interruption
+/// is generated by the camera driver.
+// ============================================================================
+PUBLIC VOID hal_CameraIrqSetHandler(HAL_CAMERA_IRQ_HANDLER_T handler);
+
+
+// =============================================================================
+// hal_CameraIrqConfig()
+// -----------------------------------------------------------------------------
+/// Configure the desired interrupts
+///
+/// @param mask Mask to enable specific interrupts.  Valid interrupts are
+/// liste in HAL_CAMERA_IRQ_CAUSE_T.
+// =============================================================================
+PUBLIC VOID hal_CameraIrqSetMask(HAL_CAMERA_IRQ_CAUSE_T mask);
+
+
+// =============================================================================
+// hal_CameraStartXfer
+// -----------------------------------------------------------------------------
+/// This function begins the IFC transfer of the camera data.  The camera
+/// itself is reset and the camera module internal fifo is cleared.  The IFC
+/// transfer is then started.
+/// @param bufSize This is the size of the buffer in _bytes_
+/// @param buffer Pointer to the video buffer where the IFC will store the data.
+/// @return IFC channel number.
+// =============================================================================
+PUBLIC UINT8 hal_CameraStartXfer(UINT32 bufSize, UINT8* buffer);
+
+
+
+// =============================================================================
+// hal_CameraStopXfer()
+// -----------------------------------------------------------------------------
+/// Must be called at the end of the Frame Capture
+/// If an underflow occured and the IFC tranfer is not complete,
+/// this function will handle the channel release
+///
+/// @param stop If \c TRUE, stops the camera controller.
+/// @return 0 when the IC transfer was complete
+///         1 when the IFC transfer was not complete and the channel had to be released
+// =============================================================================
+PUBLIC HAL_CAMERA_XFER_STATUS_T hal_CameraStopXfer(BOOL stop);
+
+
+// =============================================================================
+// hal_CameraSetupClockDivider
+// -----------------------------------------------------------------------------
+/// setup the divider of the camera module to generate the required frequency
+/// @param divider : the generated clock will be 156MHz/divider
+/// divider must be between 2 and 18
+// =============================================================================
+PUBLIC VOID hal_CameraSetupClockDivider(UINT8 divider);
+
+PUBLIC VOID hal_CameraSetLane(UINT8 lane);
+
+PUBLIC UINT32 hal_getCameraStatus(HAL_CAMERA_IRQ_CAUSE_T *cause);
+
+PUBLIC VOID hal_SetCameraClkOut(U16 value);
+
+#endif // _HAL_CAMERA_H_
+
+
diff --git a/board/rda/common/include/hal_config.h b/board/rda/common/include/hal_config.h
new file mode 100644
index 0000000000..0922453279
--- /dev/null
+++ b/board/rda/common/include/hal_config.h
@@ -0,0 +1,422 @@
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//            Copyright (C) 2013, RDA Microeletronics.                        //
+//                            All Rights Reserved                             //
+//                                                                            //
+//      This source code is the property of RDA Microeletronics and is        //
+//      confidential.  Any  modification, distribution,  reproduction or      //
+//      exploitation  of  any content of this file is totally forbidden,      //
+//      except  with the  written permission  of  RDA Microeletronics.        //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//  $HeadURL: http://svn.rdamicro.com/svn/developing1/Sources/chip/branches/8810/hal/8810/include/hal_config.h $ //
+//    $Author: huazeng $                                                        // 
+//    $Date: 2013-07-30 19:19:13 +0800 (Tue, 30 Jul 2013) $                     //   
+//    $Revision: 20765 $                                                          //   
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+/// @file hal_config.h                                                        //
+/// That file describes the configuration structure used to set all
+/// configurable parameters in HAL.                                           //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+
+#ifndef _HAL_CONFIG_H_
+#define _HAL_CONFIG_H_
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+// =============================================================================
+// HAL_LCD_MODE_T
+// -----------------------------------------------------------------------------
+/// The LCD interface modes.
+// =============================================================================
+typedef enum
+{
+    HAL_LCD_MODE_SPI,
+    HAL_LCD_MODE_PARALLEL_16BIT,
+    HAL_LCD_MODE_DSI,
+    HAL_LCD_MODE_RGB_16BIT,
+#if defined(CONFIG_MACH_RDA8810E) || defined(CONFIG_MACH_RDA8810H) || defined(CONFIG_MACH_RDA8850E)
+    HAL_LCD_MODE_RGB_18BIT,
+#endif
+    HAL_LCD_MODE_RGB_24BIT,
+
+    HAL_LCD_MODE_QTY,
+} HAL_LCD_MODE_T;
+
+// =============================================================================
+// HAL_CAM_MODE_T
+// -----------------------------------------------------------------------------
+/// The camera interface modes.
+// =============================================================================
+typedef enum
+{
+    HAL_CAM_MODE_PARALLEL,
+    HAL_CAM_MODE_SPI,
+    HAL_CAM_MODE_CSI,
+
+    HAL_CAM_MODE_QTY,
+} HAL_CAM_MODE_T;
+
+// =============================================================================
+// HAL_CAM_CSI_ID_T
+// -----------------------------------------------------------------------------
+/// The camera CSI IDs.
+// =============================================================================
+typedef enum
+{
+    HAL_CAM_CSI_NONE,
+    HAL_CAM_CSI_1,
+    HAL_CAM_CSI_2,
+
+    HAL_CAM_CSI_ID_QTY,
+} HAL_CAM_CSI_ID_T;
+
+// =============================================================================
+// HAL_CFG_SDMMC_T
+// -----------------------------------------------------------------------------
+/// This structure describes the SDMMC configuration for a given target.
+// =============================================================================
+typedef struct
+{
+    /// The sdmmc is used.
+    BOOL sdmmcUsed :1;
+    /// The sdmmc2 is used.
+    BOOL sdmmc2Used :1;
+    /// The sdmmc3 is used.
+    BOOL sdmmc3Used :1;
+} HAL_CFG_SDMMC_T;
+
+// =============================================================================
+// HAL_CFG_CAM_T
+// -----------------------------------------------------------------------------
+/// This structure describes the camera configuration for a given target.
+/// The first field identify if camera is used.
+/// The second and third field is the RemapFlag which identify if camera PDN/RST
+/// need to be remapped to other GPIOs instead of default (GPIO_5 and GPIO_4),
+/// for the first camera sensor.
+/// The fourth and fifth field is the remapped pin when RemapFlag is set, for the
+/// first camera sensor.
+/// The sixth and seventh fields are used to describe which GPIOs are used for 
+/// the PDN/RST lines of the optional second camera sensor. This second camera
+/// sensor can only be used on with GPIOs to control its PDN and RST lines.
+// =============================================================================
+typedef struct
+{
+    /// \c TRUE if the rear camera is used
+    BOOL            camUsed :1;
+    /// The polarity of the Power DowN line, for the rear sensor.
+    BOOL            camPdnActiveH :1;
+    /// The polarity of the Reset line, for the rear sensor.
+    BOOL            camRstActiveH :1;
+    /// The remapped GPIO controlling PDN (-1 if not remapped), for the rear sensor.
+    INT32           camPdnRemap;
+    /// The remapped GPIO controlling RST (-1 if not remapped), for the rear sensor.
+    INT32           camRstRemap;
+    /// The CSI ID (valid only if camera mode is CSI)
+    HAL_CAM_CSI_ID_T camCsiId;
+    /// \c TRUE if the front camera is used
+    BOOL            cam1Used :1;
+    /// The polarity of the Power DowN line, for the front sensor.    
+    BOOL            cam1PdnActiveH :1;
+    /// The polarity of the Reset line, for the front sensor.
+    BOOL            cam1RstActiveH :1;
+    /// The remapped GPIO controlling PDN (-1 if not remapped), for the front sensor.
+    INT32           cam1PdnRemap;
+    /// The remapped GPIO controlling RST (-1 if not remapped), for the front sensor.
+    INT32           cam1RstRemap;
+    /// The CSI ID (valid only if camera mode is CSI)
+    HAL_CAM_CSI_ID_T cam1CsiId;
+    /// The camera interface mode
+    HAL_CAM_MODE_T  camMode;
+} HAL_CFG_CAM_T;
+
+// =============================================================================
+// HAL_CFG_PWM_T
+// -----------------------------------------------------------------------------
+/// This structure describes the PWM configuration for a given target. 
+/// The fields tell wether the pin corresponding to PWM output 
+/// is actually used as PWM output and not as something else (for 
+/// instance as a GPIO). 
+// =============================================================================
+typedef struct
+{
+    /// \c TRUE if the PWL0 is used
+    BOOL pwl0Used :1;
+    /// \c TRUE if the PWL1 is used
+    BOOL pwl1Used :1;
+    /// \c TRUE if the PWT is used
+    BOOL pwtUsed :1;
+    /// \c TRUE if the LPG is used
+    BOOL lpgUsed :1;
+} HAL_CFG_PWM_T;
+
+// =============================================================================
+// HAL_CFG_I2C_T
+// -----------------------------------------------------------------------------
+/// This structure describes the I2C configuration for a given target. The
+/// fields tell wether the corresponding I2C pins are actually used
+/// for I2C and not as something else (for instance as a GPIO). 
+// =============================================================================
+typedef struct
+{
+    /// \c TRUE if the I2C pins are used
+    BOOL i2cUsed :1;
+    /// \c TRUE if the I2C2 pins are used
+    BOOL i2c2Used :1;
+    /// \c TRUE if the I2C2 pins are used from cam pins
+    BOOL i2c2PinsCam :1;
+    /// \c TRUE if the I2C3 pins are used
+    BOOL i2c3Used :1;
+#if defined(CONFIG_MACH_RDA8810E) || defined(CONFIG_MACH_RDA8810H) || defined(CONFIG_MACH_RDA8850E)
+    /// \c TRUE if the I2CBB pins are used
+    BOOL modemI2cUsed :1;
+#endif
+} HAL_CFG_I2C_T;
+
+// =============================================================================
+// HAL_CFG_I2S_T
+// -----------------------------------------------------------------------------
+/// This structure describes the I2S configuration for a given target. The
+/// fields tell wether the corresponding I2S pin is actually used
+/// for I2S and not as something else (for instance as a GPIO). 
+// =============================================================================
+typedef struct
+{
+    /// \c TRUE if the data out pin is used
+    BOOL doUsed :1;
+    BOOL :3;
+    /// \c TRUE if corresponding input is used
+    BOOL di0Used :1;
+    BOOL di1Used :1;
+    BOOL di2Used :1;
+} HAL_CFG_I2S_T;
+
+// =============================================================================
+// HAL_UART_CONFIG_T
+// -----------------------------------------------------------------------------
+/// Used to describes a configuration for used pin by an UART for a given target.
+// =============================================================================
+typedef enum
+{
+    /// invalid
+    HAL_UART_CONFIG_INVALID = 0,
+
+    /// UART is not used
+    HAL_UART_CONFIG_NONE,
+
+    /// UART use only data lines (TXD & RXD)
+    HAL_UART_CONFIG_DATA,
+
+    /// UART use data and flow control lines (TXD, RXD, RTS & CTS)
+    HAL_UART_CONFIG_FLOWCONTROL,
+
+    /// UART use all lines (TXD, RXD, RTS, CTS, RI, DSR, DCD & DTR)
+    HAL_UART_CONFIG_MODEM,
+
+    HAL_UART_CONFIG_QTY
+} HAL_UART_CONFIG_T;
+
+// =============================================================================
+// HAL_CFG_SPI_T
+// -----------------------------------------------------------------------------
+/// This structure describes the SPI configuration for a given target. The first
+/// fields tell wether the pin corresponding to chip select is actually used
+/// as a chip select and not as something else (for instance as a GPIO). 
+/// Then, the polarity of the Chip Select is given. It is only relevant
+/// if the corresponding Chip Select is used as a Chip Select.
+/// Finally which pin is used as input, Can be none, one or the other.
+/// On most chip configuration the input 0 (di0) is on the output pin: SPI_DIO
+// =============================================================================
+typedef struct
+{
+    /// \c TRUE if the corresponding pin is used as a Chip Select.
+    BOOL cs0Used :1;
+    BOOL cs1Used :1;
+    BOOL cs2Used :1;
+    BOOL cs3Used :1;
+    /// \c TRUE if the first edge is falling
+    BOOL cs0ActiveLow :1;
+    BOOL cs1ActiveLow :1;
+    BOOL cs2ActiveLow :1;
+    BOOL cs3ActiveLow :1;
+    /// \c TRUE if corresponding input is used
+    BOOL di0Used :1;
+    BOOL di1Used :1;
+} HAL_CFG_SPI_T;
+
+// =============================================================================
+// HAL_CFG_GOUDA_T
+// -----------------------------------------------------------------------------
+/// This structure describes the GOUDA configuration for a given target. 
+/// The first fields tell wether the pin corresponding to chip select is 
+/// actually used as a chip select and not as something else (for instance
+/// as a GPIO). If none are used, the GOUDA is considered unused.
+// =============================================================================
+typedef struct
+{
+    /// \c TRUE if the corresponding pin is used as a Chip Select.
+    BOOL cs0Used :1;
+    BOOL cs1Used :1;
+    /// \c TRUE if LCD 16-23 bits are from camera, FALSE from NAND
+    BOOL lcd16_23Cam :1;
+#if defined(CONFIG_MACH_RDA8810E) || defined(CONFIG_MACH_RDA8810H) || defined(CONFIG_MACH_RDA8850E)
+    /// \c TRUE if LCD 8-23 (except for 16-17) bits are from camera2, FALSE from other
+    BOOL lcd8_23Cam2 :1;
+    /// \c TRUE if LCD 16-17 bits are from LCD CS, FALSE from other
+    BOOL lcd16_17Cs :1;
+#endif
+    /// \c LCD interface mode
+    HAL_LCD_MODE_T lcdMode;
+} HAL_CFG_GOUDA_T;
+
+// =============================================================================
+// HAL_CFG_IO_DRIVE_T
+// -----------------------------------------------------------------------------
+/// This structure describes the IO Drive configuration for a given target. 
+// =============================================================================
+typedef union
+{
+    struct
+    {
+        UINT32 vDdrDomain:3;    // 2:0
+        UINT32 vPsram1Domain:3; // 5:3
+        UINT32 vPsram2Domain:3; // 6:8
+        UINT32 vNFlashDomain:3; // 11:9
+        UINT32 vLcd1Domain:3;   // 14:12
+        UINT32 vLcd2Domain:3;   // 17:15
+        UINT32 vSDat1Domain:3;  // 20:18
+        UINT32 vSDat2Domain:3;  // 23 :21
+        UINT32 vCamDomain:2;    // 25:24
+        UINT32 vSim1Domain:2;   // 27:26
+        UINT32 vSim2Domain:2;   // 29:28
+        UINT32 vSim3Domain:2;   // 31:30
+        UINT32 vGpioDomain:2;   // 1:0
+        UINT32 :30;
+    };
+    struct
+    {
+        UINT32 select1;
+        UINT32 select2;
+    };
+} HAL_CFG_IO_DRIVE_T;
+
+// =============================================================================
+// HAL_CFG_CONFIG_T
+// -----------------------------------------------------------------------------
+/// HAL configuration structure. 
+/// This structure is used to setup HAL with regards to the specific 
+/// configuration of the board.
+/// Enabling a feature such as i2sCfg will set the corresponding pins which 
+/// could also be a GPIO to their alternative use, that is I2S for this 
+/// example.
+/// GPIO Pins not connected must be set in the noConnectPins bitfield, for
+/// power saving. They are configured as output and driven to '0'.
+/// Pins which are not not connected (ie are connected) but are not used in
+/// an alternative mode as I2S, are considered to be used as GPIOs.
+// =============================================================================
+typedef struct{
+    /// Chip version
+    UINT32  chipVersion;
+    /// RF Clock Frequency
+    UINT32  rfClkFreq;
+    /// \c TRUE if LPS_CO_1 is used as LPS
+    BOOL    useLpsCo1;
+    /// Bitfield with '1' for keypad pins used as input on the keypad
+    UINT8   keyInMask;
+    /// Bitfield with '1' for keypad pins used as output on the keypad
+    UINT8   keyOutMask;
+    /// PWM Configuration
+    HAL_CFG_PWM_T pwmCfg;
+    HAL_CFG_I2C_T i2cCfg;
+    /// I2S Configuration
+    HAL_CFG_I2S_T i2sCfg;
+#if defined(CONFIG_MACH_RDA8810E) || defined(CONFIG_MACH_RDA8810H) || defined(CONFIG_MACH_RDA8850E)
+    HAL_CFG_I2S_T i2s2Cfg;
+#endif
+    /// UART Configuration
+    HAL_UART_CONFIG_T uartCfg[3];
+    /// SPI Configuration
+    HAL_CFG_SPI_T modemSpiCfg[1];
+    HAL_CFG_SPI_T spiCfg[2];
+    /// SDMMC Configuration
+    HAL_CFG_SDMMC_T sdmmcCfg;
+    /// Camera Configuration
+    HAL_CFG_CAM_T   camCfg;
+#if defined(CONFIG_MACH_RDA8810E) || defined(CONFIG_MACH_RDA8810H) || defined(CONFIG_MACH_RDA8850E)
+    /// Camera2 Configuration
+    HAL_CFG_CAM_T   cam2Cfg;
+#endif
+    /// Gouda/LCD Configuration
+    HAL_CFG_GOUDA_T goudaCfg;
+    /// \c TRUE if parallel NAND interface is used
+    BOOL    parallelNandUsed;
+    /// \c TRUE if host UART is used
+    BOOL    hostUartUsed;
+    /// \c TRUE if host clock is used
+    BOOL    hostClkUsed;
+    /// \c TRUE if CLK_OUT pin is used
+    BOOL    clkOutUsed;
+    /// \c TRUE if CLK_32K pin is used
+    BOOL    useClk32k;
+#if defined(CONFIG_MACH_RDA8810E) || defined(CONFIG_MACH_RDA8810H) || defined(CONFIG_MACH_RDA8850E)
+    /// \c TRUE if SDIO2_UART1 pin is used for UART1, FALSE for SDIO2
+    BOOL    sdio2Uart1Used;
+    /// \c TRUE if EMAC pin is used
+    BOOL    emacUsed;
+#endif
+
+    /// Bitfield with '1' for physically not connected GPIO_C pins
+    UINT32  noConnectGpio_C;
+    /// Bitfield with '1' for GPIO really used as GPIO_C
+    UINT32  usedGpio_C;
+    /// Bitfield with '1' for TCO really used as TCO
+    UINT32  usedTco;
+    /// Bitfield with '1' for physically not connected GPIO_A pins
+    UINT32  noConnectGpio_A;
+    /// Bitfield with '1' for GPIO really used as GPIO_A
+    UINT32  usedGpio_A;
+    /// Bitfield with '1' for GPO really used as GPO_A
+    UINT32  usedGpo_A;
+    /// Bitfield with '1' for physically not connected GPIO_B pins
+    UINT32  noConnectGpio_B;
+    /// Bitfield with '1' for GPIO really used as GPIO_B
+    UINT32  usedGpio_B;
+    /// Bitfield with '1' for physically not connected GPIO_D pins
+    UINT32  noConnectGpio_D;
+    /// Bitfield with '1' for GPIO really used as GPIO_D
+    UINT32  usedGpio_D;
+#if defined(CONFIG_MACH_RDA8810E) || defined(CONFIG_MACH_RDA8810H) || defined(CONFIG_MACH_RDA8850E)
+    /// Bitfield with '1' for physically not connected GPIO_E pins
+    UINT32  noConnectGpio_E;
+    /// Bitfield with '1' for GPIO really used as GPIO_E
+    UINT32  usedGpio_E;
+#endif
+    /// IO Drive Value
+    HAL_CFG_IO_DRIVE_T ioDrive;
+
+} HAL_CFG_CONFIG_T;
+
+
+// =============================================================================
+//  GLOBAL VARIABLES
+// =============================================================================
+
+//  
+
+// =============================================================================
+//  FUNCTIONS
+// =============================================================================
+
+#endif // _HAL_CONFIG_H_
+
diff --git a/board/rda/common/include/hal_gpio.h b/board/rda/common/include/hal_gpio.h
new file mode 100644
index 0000000000..5f378a817f
--- /dev/null
+++ b/board/rda/common/include/hal_gpio.h
@@ -0,0 +1,553 @@
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//            Copyright (C) 2003-2007, Coolsand Technologies, Inc.            //
+//                            All Rights Reserved                             //
+//                                                                            //
+//      This source code is the property of Coolsand Technologies and is      //
+//      confidential.  Any  modification, distribution,  reproduction or      //
+//      exploitation  of  any content of this file is totally forbidden,      //
+//      except  with the  written permission  of  Coolsand Technologies.      //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//  $HeadURL: http://svn.rdamicro.com/svn/developing1/Sources/chip/branches/8810/hal/include/hal_gpio.h $ //
+//    $Author: huazeng $                                                        // 
+//    $Date: 2013-07-08 14:14:23 +0800 (Mon, 08 Jul 2013) $                     //   
+//    $Revision: 20589 $                                                         //   
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+/// @file hal_gpio.h                                                          //
+/// Describes the GPIO driver API                                             //
+//                                                                            //
+//////////////////////////////////////////////////////////////////////////////// 
+
+#ifndef _HAL_GPIO_H_
+#define _HAL_GPIO_H_
+
+/// @defgroup gpio HAL GPIO Driver
+/// This document describes the characteristics of the GPIO module 
+/// and how to use it via its Hardware Abstraction Layer API.
+///
+/// @par GPIO Operation
+/// GPIOs are used to control external chips, or to get external events. They 
+/// can be used as inputs or outputs. As input 8 of them can trigger an 
+/// interruption.
+///
+/// @par Interruption Handler
+/// For each one of the 8 interrupt capable GPIO, the user handler is set
+/// through a call to the #hal_GpioIrqSetHandler function. When an interrupt
+/// occurs on a GPIO, whether on a falling or rising edge, the registered
+/// user function is called. No information about the kind of edge is available,
+/// so these functions don't have a status.
+///
+/// @par Interruption Mask
+/// For each one of the 8 interrupt capable GPIO, the mask is set through 
+/// #hal_GpioIrqSetMask, using the #HAL_GPIO_IRQ_MASK_T structure to set on 
+/// which edge the GPIO are sensitive.
+///
+/// @par HAL GPIO Driver is designed for ease of use and configurability for
+/// edrv and svc, not for high speed toggling. If for some specific situation
+/// (mostly experimental projects) a Fast GPIO interface is needed, this 
+/// could be added to HAL.
+///
+/// @{
+///   
+
+
+// =============================================================================
+// TYPES
+// =============================================================================
+
+
+
+// =============================================================================
+// HAL_GPIO_TYPE_T
+// -----------------------------------------------------------------------------
+/// Used to give a type to a general purpose pin that can be either a GPIO pin
+/// or a GPO pin.
+// =============================================================================
+typedef enum
+{
+    /// invalid IO type
+    HAL_GPIO_TYPE_INVALID = 0,
+
+    /// no IO type
+    HAL_GPIO_TYPE_NONE,
+
+    /// GPIO type
+    HAL_GPIO_TYPE_IO,
+
+    /// GPO type
+    HAL_GPIO_TYPE_O,
+
+    /// TCO type
+    HAL_GPIO_TYPE_TCO,
+
+    HAL_GPIO_TYPE_QTY
+} HAL_GPIO_TYPE_T;
+
+
+
+// =============================================================================
+// HAL_GPIO_GPIO_ID_T
+// -----------------------------------------------------------------------------
+/// This type is used to name all the GPIO.
+/// Functions of the GPIO driver are called with a parameter of 
+/// this type to specify which GPIO is concerned by a the function call.
+// =============================================================================
+typedef enum
+{
+    /// To be used in configuration when the field for this GPIO is not used
+    HAL_GPIO_NONE = HAL_GPIO_TYPE_NONE << 16,
+    // Only the first eight ones can trig interrupts
+    /// Can cause an interrupt
+    HAL_GPIO_0 = HAL_GPIO_TYPE_IO << 16,
+    /// Can cause an interrupt
+    HAL_GPIO_1,
+    /// Can cause an interrupt
+    HAL_GPIO_2,
+    /// Can cause an interrupt
+    HAL_GPIO_3,
+    /// Can cause an interrupt
+    HAL_GPIO_4,
+    /// Can cause an interrupt
+    HAL_GPIO_5,
+    /// Can cause an interrupt
+    HAL_GPIO_6,
+    /// Can cause an interrupt
+    HAL_GPIO_7,
+    // Those following are not interruptible
+    HAL_GPIO_8,
+    HAL_GPIO_9,
+    HAL_GPIO_10,
+    HAL_GPIO_11,
+    HAL_GPIO_12,
+    HAL_GPIO_13,
+    HAL_GPIO_14,
+    HAL_GPIO_15,
+    HAL_GPIO_16,
+    HAL_GPIO_17,
+    HAL_GPIO_18,
+    HAL_GPIO_19,
+    HAL_GPIO_20,
+    HAL_GPIO_21,
+    HAL_GPIO_22,
+    HAL_GPIO_23,
+    HAL_GPIO_24,
+    HAL_GPIO_25,
+    HAL_GPIO_26,
+    HAL_GPIO_27,
+    HAL_GPIO_28,
+    HAL_GPIO_29,
+    HAL_GPIO_30,
+    HAL_GPIO_31,
+    HAL_GPIO_QTY = 32
+
+} HAL_GPIO_GPIO_ID_T;
+
+
+
+// =============================================================================
+// HAL_GPIO_GPO_ID_T
+// -----------------------------------------------------------------------------
+/// This type is used to name all the GPO.
+/// GPO functions of the GPIO driver are called with a parameter of 
+/// this type to specify which GPO is concerned by a the function call.
+// =============================================================================
+typedef enum
+{
+    /// To be used in configuration when the field for this GPO is not used
+    HAL_GPO_NONE = HAL_GPIO_TYPE_NONE << 16,
+    HAL_GPO_0 = HAL_GPIO_TYPE_O << 16,
+    HAL_GPO_1,
+    HAL_GPO_2,
+    HAL_GPO_3,
+    HAL_GPO_4,
+    HAL_GPO_5,
+    HAL_GPO_6,
+    HAL_GPO_7,
+    HAL_GPO_8,
+    HAL_GPO_9,
+    HAL_GPO_10,
+    HAL_GPO_11,
+
+    HAL_GPO_QTY = 12
+} HAL_GPIO_GPO_ID_T;
+
+
+
+// =============================================================================
+// HAL_GPIO_TCO_ID_T
+// -----------------------------------------------------------------------------
+/// This type is used to name all the TCO.
+/// TCO functions of the GPIO driver are called with a parameter of 
+/// this type to specify which TCO is concerned by a the function call.
+// =============================================================================
+typedef enum
+{
+    /// To be used in configuration when the field for this TCO is not used
+    HAL_TCO_NONE = HAL_GPIO_TYPE_NONE << 16,
+    HAL_TCO_0 = HAL_GPIO_TYPE_TCO << 16,
+    HAL_TCO_1,
+    HAL_TCO_2,
+    HAL_TCO_3,
+    HAL_TCO_4,
+    HAL_TCO_5,
+    HAL_TCO_6,
+    HAL_TCO_7,
+    HAL_TCO_8,
+    HAL_TCO_9,
+
+    HAL_TCO_QTY = 10
+} HAL_GPIO_TCO_ID_T;
+
+
+
+// =============================================================================
+// HAL_APO_ID_T
+// -----------------------------------------------------------------------------
+/// Any Programmable Output IDentifier
+/// Used to identify any general purpose output pin which can be either a GPIO 
+/// pin, a GPO pin or a TCO pin.
+// =============================================================================
+typedef union
+{
+    struct
+    {
+        // NOTE: THIS IS ENDIANNES DEPENDANT
+        UINT16 id:16;
+        /// Defines the kind of the pin: GPIO, GPO, TCO, none
+        HAL_GPIO_TYPE_T type:16;
+    };
+    /// id field is either a GPIO ID ...
+    HAL_GPIO_GPIO_ID_T gpioId;
+    /// or a GPO ID
+    HAL_GPIO_GPO_ID_T gpoId;
+    /// or a TCO ID depending on the type.
+    HAL_GPIO_TCO_ID_T tcoId;
+} HAL_APO_ID_T;
+
+
+
+// =============================================================================
+// HAL_GPIO_IRQ_MASK_T
+// -----------------------------------------------------------------------------
+/// This structure is used to define on which occasion an interrupt 
+/// will be triggered from an interruptible GPIO.
+/// In that sense, it is the interrupt mask, but the configuration is
+/// much more precise
+// =============================================================================
+typedef struct
+{
+    /// Defines whether an interruption will be triggered on a rising
+    /// edge on the GPIO
+    BOOL rising;
+
+    /// Defines whether an interruption will be triggered on a falling
+    /// edge on the GPIO
+    BOOL falling;
+
+    /// Defines if the GPIO's signal will be debounced before the interrupt
+    /// is triggered
+    BOOL debounce;
+
+    /// Defines if the interruption is on level (\c TRUE), or on edge (\c FALSE)
+    BOOL level;
+} HAL_GPIO_IRQ_MASK_T;
+
+
+
+// =============================================================================
+// HAL_GPIO_IRQ_HANDLER_T
+// -----------------------------------------------------------------------------
+/// Type for the user function called when an interrupt is triggered on 
+/// a GPIO.
+// =============================================================================
+typedef VOID (*HAL_GPIO_IRQ_HANDLER_T)(VOID);
+
+
+
+
+
+
+// =============================================================================
+// HAL_GPIO_DC_ON_INT_MODE_T
+// -----------------------------------------------------------------------------
+/// Type used to define the interruption mode of the DC_ON read.
+// =============================================================================
+typedef enum
+{
+    /// Send IRQ if last read DCON is '0' and now is '1'.
+    HAL_GPIO_DC_ON_INT_L2H,
+    /// Send IRQ if last read DCON is '1' and now is '0'.
+    HAL_GPIO_DC_ON_INT_H2L,
+    /// Send IRQ every time read is ready.
+    HAL_GPIO_DC_ON_INT_RR,
+    /// disable IRQ for DCON
+    HAL_GPIO_DC_ON_INT_NO
+} HAL_GPIO_DC_ON_INT_MODE_T;
+
+
+// =============================================================================
+// HAL_GPIO_DIRECTION_T
+// -----------------------------------------------------------------------------
+/// Direction of a GPIO
+// =============================================================================
+typedef enum
+{
+    HAL_GPIO_DIRECTION_INPUT,
+    HAL_GPIO_DIRECTION_OUTPUT,
+
+    HAL_GPIO_DIRECTION_QTY
+} HAL_GPIO_DIRECTION_T;
+
+
+
+// =============================================================================
+// HAL_GPIO_CFG_T
+// -----------------------------------------------------------------------------
+/// This structure is used to define the initial state of a GPIO when it is 
+/// opened by a call to #hal_GpioOpen.
+// =============================================================================
+typedef struct
+{
+    /// Direction of the GPIO
+    HAL_GPIO_DIRECTION_T direction;
+
+    /// Initial value (if this GPIO is an output)
+    BOOL value;
+
+    /// IRQ mask, only valid if applied to an interruptible GPIO
+    HAL_GPIO_IRQ_MASK_T irqMask;
+
+    /// IRQ handler, only valid if applied to an interruptible GPIO
+    HAL_GPIO_IRQ_HANDLER_T irqHandler;
+} HAL_GPIO_CFG_T;
+
+
+
+
+// =============================================================================
+// FUNCTIONS
+// =============================================================================
+
+// =============================================================================
+// hal_GpioOpen
+// -----------------------------------------------------------------------------
+/// Opens the a GPIO and sets its initial configuration. The GPIO's state can 
+/// then be changed by the others functions of this API.
+/// It also sets the corresponding pin in GPIO mode.
+///
+/// @param gpio Identifier of the GPIO to open
+/// @param cfg Initial configuration of this GPIO.
+// =============================================================================
+PUBLIC VOID hal_GpioOpen(HAL_GPIO_GPIO_ID_T gpio, CONST HAL_GPIO_CFG_T* cfg);
+
+
+
+// =============================================================================
+// hal_GpioClose
+// -----------------------------------------------------------------------------
+/// Closes a GPIO driver. The GPIO is returned to its reset state
+/// @param gpio GPIO to close.
+// =============================================================================
+PUBLIC VOID hal_GpioClose(HAL_GPIO_GPIO_ID_T gpio);
+
+
+
+// =============================================================================
+// hal_GpioSetOut
+// -----------------------------------------------------------------------------
+/// This function sets one GPIO to output and leaves the others'directions
+/// unchanged.
+// =============================================================================
+PUBLIC VOID hal_GpioSetOut(HAL_GPIO_GPIO_ID_T gpio);
+
+
+
+// =============================================================================
+// hal_GpioSetIn
+// -----------------------------------------------------------------------------
+/// This function sets one GPIO to input and leaves the others'directions
+/// unchanged.
+// =============================================================================
+PUBLIC VOID hal_GpioSetIn(HAL_GPIO_GPIO_ID_T gpio);
+
+
+
+// =============================================================================
+// hal_GpioGet
+// -----------------------------------------------------------------------------
+/// This function reads a GPIO, and returns its value. It 
+/// returns the input value of GPIO configured as input and the output value 
+/// for GPIO configured as output.
+///
+/// @return The input value for a GPIO configured as input and 
+/// the output value for a GPIO configured as output.
+// =============================================================================
+PUBLIC UINT32 hal_GpioGet(HAL_GPIO_GPIO_ID_T gpio);
+
+
+
+// =============================================================================
+// hal_GpioSet
+// -----------------------------------------------------------------------------
+/// This function sets to '1' the value of the given GPIO, GPO or TCO and leaves
+/// the others unchanged
+/// @param apo A GPIO, a GPO or a TCO set to '1', others being unchanged.
+// =============================================================================
+PUBLIC VOID hal_GpioSet(HAL_APO_ID_T apo);
+
+
+
+// =============================================================================
+// hal_GpioClr
+// -----------------------------------------------------------------------------
+/// This function sets to '0' the value of the given GPIO, GPO or TCO and leaves
+/// the others unchanged
+/// @param apo A GPIO, a GPO or a TCO set to '0', others being unchanged.
+// =============================================================================
+PUBLIC VOID hal_GpioClr(HAL_APO_ID_T apo);
+
+
+
+// =============================================================================
+// hal_GpioResetIrq
+// -----------------------------------------------------------------------------
+/// Clears the gpio IRQ, 
+/// This function should only be called to avoid unwanted IRQ. \n
+/// For regular usage, IRQ clearing is done automatically by the driver. \n
+/// Rise and fall cause are cleared simultaneously
+/// 
+/// @param gpio A GPIO whose interrupt cause is cleared.
+// ==========================================================================
+PUBLIC VOID hal_GpioResetIrq(HAL_GPIO_GPIO_ID_T gpio);
+
+
+
+// =============================================================================
+// hal_GpioIrqSetHandler
+// -----------------------------------------------------------------------------
+/// Sets the user IRQ handler called when an interruption is triggerd on a 
+/// given GPIO.
+///
+/// @param gpio The GPIO whose interrupt will trig the handler
+/// @param handler The user function called on an interruption on this GPIO.
+// =============================================================================
+PUBLIC VOID hal_GpioIrqSetHandler(HAL_GPIO_GPIO_ID_T gpio, HAL_GPIO_IRQ_HANDLER_T handler);
+
+
+
+
+// =============================================================================
+// hal_GpioIrqSetMask
+// -----------------------------------------------------------------------------
+/// Set the condition under which an interrupt is triggered on a GPIO
+/// @param gpio The GPIO
+/// @param cfg Pointer to the configuration defining the condition 
+/// under which the interrupts are triggered, ie the interrupt mask.
+// =============================================================================
+PUBLIC VOID hal_GpioIrqSetMask(HAL_GPIO_GPIO_ID_T gpio, CONST HAL_GPIO_IRQ_MASK_T* cfg);
+
+
+
+// =============================================================================
+// hal_GpioGetCfg
+// -----------------------------------------------------------------------------
+/// Return the configuration of a GPIO.
+/// @param gpio Identifier of the GPIO.
+/// @param cfg Current configuration of this GPIO.
+// =============================================================================
+PUBLIC VOID hal_GpioGetCfg(HAL_GPIO_GPIO_ID_T gpio, HAL_GPIO_CFG_T* cfg);
+
+
+
+// =============================================================================
+// hal_GpioGetIntStatus
+// -----------------------------------------------------------------------------
+/// Return the interrupt status of a GPIO.
+/// @param gpio Identifier of the GPIO.
+/// @return The interrupt status of this GPIO.
+// =============================================================================
+PUBLIC BOOL hal_GpioGetIntStatus(HAL_GPIO_GPIO_ID_T gpio);
+
+
+
+#if 0
+// =============================================================================
+// hal_GpioDcOnOpen
+// =============================================================================
+/// Configure the DC-ON command
+/// @param outTime Time for which GPIO0 is set to output mode, after a start 
+/// read DCON command is issued.
+/// @param waitTime Time for which GPIO0 should wait before reading DC_ON,
+/// after a start read DCON command is issued (Note: \p waitTime must be 
+/// strictly greater than \p outTime).
+/// @param intMode Interruption mode of GPIO0 in mode DC_ON detection.
+// =============================================================================
+PUBLIC VOID hal_GpioDcOnOpen(UINT32 outTime, UINT32 waitTime,
+                            HAL_GPIO_DC_ON_INT_MODE_T intMode);
+
+
+// =============================================================================
+// hal_GpioDcOnClose
+// =============================================================================
+/// Disable the DC-ON command: set back GPIO0 as regular GPIO
+// =============================================================================
+PUBLIC VOID hal_GpioDcOnClose(VOID);
+
+
+// =============================================================================
+// hal_GpioChgSetMode
+// -----------------------------------------------------------------------------
+/// Enable or disable the charger according to \p on.
+/// when enabled, #hal_GpioChgDown can be called to pulse down the charger.
+/// @param on charger state
+// =============================================================================
+PUBLIC VOID hal_GpioChgSetMode(BOOL on);
+
+
+// =============================================================================
+// hal_GpioChgDown
+// -----------------------------------------------------------------------------
+/// Sends the down signal to the charger to avoid a time-out. The user will 
+/// have to call that function at least every 5 seconds.
+// =============================================================================
+PUBLIC VOID hal_GpioChgDown(VOID);
+
+
+// =============================================================================
+// hal_GpioChgGet
+// -----------------------------------------------------------------------------
+/// This function reads the charger dedicated GPIO, and returns its value.
+///
+/// @return The input value of the charger dedicated GPIO.
+// =============================================================================
+PUBLIC UINT32 hal_GpioChgGet(VOID);
+
+
+// =============================================================================
+// hal_GpioChgIrqSetHandler
+// -----------------------------------------------------------------------------
+/// Sets the user IRQ handler called when an interruption is triggerd on the 
+/// charger dedicated GPIO.
+///
+/// @param gpio The GPIO whose interrupt will trig the handler
+/// @param handler The user function called on an interruption on the charger
+/// dedicated GPIO.
+// =============================================================================
+PUBLIC VOID hal_GpioChgIrqSetHandler(HAL_GPIO_IRQ_HANDLER_T handler);
+
+
+#endif
+
+
+
+///  @} <- End of the gpio group 
+
+
+#endif // _HAL_GPIO_H_
+
+
+
diff --git a/board/rda/common/include/hal_sys.h b/board/rda/common/include/hal_sys.h
new file mode 100644
index 0000000000..f7aad7231c
--- /dev/null
+++ b/board/rda/common/include/hal_sys.h
@@ -0,0 +1,831 @@
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//            Copyright (C) 2003-2007, Coolsand Technologies, Inc.            //
+//                            All Rights Reserved                             //
+//                                                                            //
+//      This source code is the property of Coolsand Technologies and is      //
+//      confidential.  Any  modification, distribution,  reproduction or      //
+//      exploitation  of  any content of this file is totally forbidden,      //
+//      except  with the  written permission  of  Coolsand Technologies.      //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//
+//  $HeadURL: http://svn.rdamicro.com/svn/developing1/Sources/chip/branches/8810/hal/include/hal_sys.h $
+//  $Author: huazeng $
+//  $Date: 2013-08-30 12:04:12 +0800 (Fri, 30 Aug 2013) $
+//  $Revision: 20989 $
+//
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+/// @file hal_sys.h
+/// That file describes the SYSTEM driver API.
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+
+#ifndef _HAL_SYS_H_
+#define _HAL_SYS_H_
+
+/// @defgroup system HAL Sytem Driver
+/// description
+/// ...
+/// @{
+
+
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+
+// Chip product IDs
+
+#define HAL_SYS_CHIP_PROD_ID_8808       0x8808
+
+#define HAL_SYS_CHIP_PROD_ID_8808S      0x880a
+
+#define HAL_SYS_CHIP_PROD_ID_8809       0x8809
+
+#define HAL_SYS_CHIP_PROD_ID_8810       0x8810
+
+
+#ifdef BIG_ENDIAN
+
+#define HAL_ENDIAN_LITTLE_32(X) (((((X) >> 24) & 0xFF) <<  0)           \
+                                |((((X) >> 16) & 0xFF) <<  8)           \
+                                |((((X) >>  8) & 0xFF) << 16)           \
+                                |((((X) >>  0) & 0xFF) << 24))
+
+#define HAL_ENDIAN_LITTLE_24(X) (((((X) >> 16) & 0xFF) <<  0)           \
+                                |((((X) >>  8) & 0xFF) <<  8)           \
+                                |((((X) >>  0) & 0xFF) << 16))
+
+#define HAL_ENDIAN_LITTLE_16(X) (((((X) >>  8) & 0xFF) <<  0)           \
+                                |((((X) >>  0) & 0xFF) <<  8))
+
+#define HAL_ENDIAN_BIG_32(X)    (X)
+
+#define HAL_ENDIAN_BIG_24(X)    (X)
+
+#define HAL_ENDIAN_BIG_16(X)    (X)
+
+#else
+
+#define HAL_ENDIAN_BIG_32(X)    (((((X) >> 24) & 0xFF) <<  0)           \
+                                |((((X) >> 16) & 0xFF) <<  8)           \
+                                |((((X) >>  8) & 0xFF) << 16)           \
+                                |((((X) >>  0) & 0xFF) << 24))
+
+#define HAL_ENDIAN_BIG_24(X)    (((((X) >> 16) & 0xFF) <<  0)           \
+                                |((((X) >>  8) & 0xFF) <<  8)           \
+                                |((((X) >>  0) & 0xFF) << 16))
+
+#define HAL_ENDIAN_BIG_16(X)    (((((X) >>  8) & 0xFF) <<  0)           \
+                                |((((X) >>  0) & 0xFF) <<  8))
+
+#define HAL_ENDIAN_LITTLE_32(X) (X)
+
+#define HAL_ENDIAN_LITTLE_24(X) (X)
+
+#define HAL_ENDIAN_LITTLE_16(X) (X)
+
+#endif /* BIG_ENDIAN */
+
+// =============================================================================
+// HAL_SYS_CRITICAL_SECTION_ADDRESS
+// -----------------------------------------------------------------------------
+/// Address of the interrupt enable semaphore, used to control the critical
+/// section.
+// =============================================================================
+#define HAL_SYS_CRITICAL_SECTION_ADDRESS  CHIP_SYS_CRITICAL_SECTION_REG
+
+
+// =============================================================================
+// HAL_SYS_GET_CACHED_ADDR
+// -----------------------------------------------------------------------------
+/// That macro is used to get the cached version of a given address
+// =============================================================================
+#define HAL_SYS_GET_CACHED_ADDR(addr)  (((UINT32)(addr))&0xdfffffff)
+
+
+// =============================================================================
+// HAL_SYS_GET_UNCACHED_ADDR
+// -----------------------------------------------------------------------------
+/// That macro is used to get the uncached version of a given address
+// =============================================================================
+#define HAL_SYS_GET_UNCACHED_ADDR(addr) (((UINT32)(addr))|0x20000000)
+
+#ifdef __mips16
+// =============================================================================
+// HAL_SYS_GET_RA
+// -----------------------------------------------------------------------------
+/// That macro puts in store the current value of the RA register. It should 
+/// be called at the beginning of the function (before any other function call)
+/// to ensure the correctness of the result.
+///
+/// This is the macro for mips16 code. It also exists for mips32 code, in
+/// which case its value would be:
+///
+/// <code>
+/// \#define HAL_SYS_GET_RA(store) asm volatile("sw $31, 0(%0)"::"r"((store)))
+/// </code>
+///
+/// @param store The return address of the current function
+// =============================================================================
+#define HAL_SYS_GET_RA(store) asm volatile("move $2, $31\n\tsw $2, 0(%0)"::"d"((store)):"$2")
+#else
+// =============================================================================
+// HAL_SYS_GET_RA
+// -----------------------------------------------------------------------------
+/// That macro puts in store the current value of the RA register. It should 
+/// be called at the beginning of the function (before any other function call)
+/// to ensure the correctness of the result.
+///
+/// This is the macro for mips32 code. It also exists for mips16 code, in
+/// which case its value would be:
+///
+/// <code>
+/// \#define HAL_SYS_GET_RA(store) asm volatile("move $2, $31\n\tsw $2, 0(%0)"::"r"((store)):"$2")
+/// </code>
+///
+/// @param store The return address of the current function
+// =============================================================================
+#define HAL_SYS_GET_RA(store) asm volatile("sw $31, 0(%0)"::"r"((store)))
+#endif
+
+
+
+
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+// =============================================================================
+// HAL_SYS_FREQ_USER_ID_T
+// -----------------------------------------------------------------------------
+/// Those are the different user recognized at the system scale.
+/// @todo fill
+// =============================================================================
+typedef enum
+{
+    // Resource ID to be used by the platform 
+    HAL_SYS_FREQ_PLATFORM_FIRST_USER = 25,
+    HAL_SYS_FREQ_PAL = HAL_SYS_FREQ_PLATFORM_FIRST_USER,
+    HAL_SYS_FREQ_BCPU,
+    HAL_SYS_FREQ_XCV,
+    HAL_SYS_FREQ_CAMS,
+    HAL_SYS_FREQ_VOIS,
+    HAL_SYS_FREQ_NONE_0,
+    HAL_SYS_FREQ_NONE_1,
+    HAL_SYS_FREQ_AVRS,
+    // !!! Add new platform users above !!!
+    HAL_SYS_FREQ_PLATFORM_USER_END,
+    HAL_SYS_FREQ_PLATFORM_LAST_USER = HAL_SYS_FREQ_PLATFORM_USER_END-1,
+
+    // Resource ID to be used by the application (MMI)
+    HAL_SYS_FREQ_APP_FIRST_USER = 40,
+    HAL_SYS_FREQ_APP_USER_0 = HAL_SYS_FREQ_APP_FIRST_USER,
+    HAL_SYS_FREQ_APP_USER_1,
+    HAL_SYS_FREQ_APP_USER_2,
+    HAL_SYS_FREQ_APP_USER_3,
+    HAL_SYS_FREQ_APP_USER_4,
+    HAL_SYS_FREQ_APP_USER_5,
+    HAL_SYS_FREQ_APP_USER_6,
+    HAL_SYS_FREQ_APP_USER_7,
+    // !!! Add new app users above !!!
+    HAL_SYS_FREQ_APP_USER_END,
+    HAL_SYS_FREQ_APP_LAST_USER = HAL_SYS_FREQ_APP_USER_END-1,
+
+    // Total number of resource IDs
+    HAL_SYS_FREQ_USER_QTY
+} HAL_SYS_FREQ_USER_ID_T;
+
+
+
+// =============================================================================
+// HAL_SYS_FREQ_T
+// -----------------------------------------------------------------------------
+/// That type defines all the possible frequencies for the system clock.
+/// This type is used to define the minimum system frequency required 
+/// by a user selected among #HAL_SYS_FREQ_USER_ID_T.
+/// Some frequencies might not be supported by some chips.
+// =============================================================================
+typedef enum
+{
+#if (!CHIP_HAS_ASYNC_TCU)
+    HAL_SYS_FREQ_32K     = 32768,
+    HAL_SYS_FREQ_13M     = 13000000,
+    HAL_SYS_FREQ_26M     = 26000000,
+    HAL_SYS_FREQ_39M     = 39000000,
+    HAL_SYS_FREQ_52M     = 52000000,
+    HAL_SYS_FREQ_78M     = 78000000,
+    HAL_SYS_FREQ_104M    = 104000000,
+    HAL_SYS_FREQ_156M    = 156000000,
+    HAL_SYS_FREQ_208M    = 208000000,
+    HAL_SYS_FREQ_UNKNOWN = 0,
+#else // CHIP_HAS_ASYNC_TCU
+    HAL_SYS_FREQ_32K     = 32768,
+    HAL_SYS_FREQ_13M     = 13000000,
+    HAL_SYS_FREQ_26M     = 26000000,
+    HAL_SYS_FREQ_39M     = 39000000,
+    HAL_SYS_FREQ_52M     = 52000000,
+    HAL_SYS_FREQ_78M     = 78000000,
+    HAL_SYS_FREQ_89M     = 89142857, //624M/7
+    HAL_SYS_FREQ_104M    = 104000000,
+    HAL_SYS_FREQ_113M    = 113454545, //624M/5.5
+    HAL_SYS_FREQ_125M    = 124800000,
+    HAL_SYS_FREQ_139M    = 138666667, //624M/4.5
+    HAL_SYS_FREQ_156M    = 156000000,
+    HAL_SYS_FREQ_178M    = 178285714, //624M/3.5
+    HAL_SYS_FREQ_208M    = 208000000,
+    HAL_SYS_FREQ_250M    = 249600000, //624M/2.5
+    HAL_SYS_FREQ_312M    = 312000000,
+    HAL_SYS_FREQ_UNKNOWN = 0,
+#endif // CHIP_HAS_ASYNC_TCU
+} HAL_SYS_FREQ_T;
+
+
+// =============================================================================
+// HAL_SYS_BB_FREQ_T
+// -----------------------------------------------------------------------------
+/// That type defines all the possible frequencies for the bb clock.
+/// Some frequencies might not be supported by some chips.
+// =============================================================================
+typedef enum
+{
+    HAL_SYS_BB_FREQ_26M     = 26000000,
+    HAL_SYS_BB_FREQ_39M     = 39000000,
+    HAL_SYS_BB_FREQ_52M     = 52000000,
+    HAL_SYS_BB_FREQ_78M     = 78000000,
+    HAL_SYS_BB_FREQ_104M    = 104000000,
+    HAL_SYS_BB_FREQ_156M    = 156000000,
+    HAL_SYS_BB_FREQ_208M    = 208000000,
+    HAL_SYS_BB_FREQ_312M    = 312000000,
+} HAL_SYS_BB_FREQ_T;
+
+
+
+// =============================================================================
+// HAL_SYS_FREQ_CHANGE_HANDLER_T
+// -----------------------------------------------------------------------------
+/// Type for Handler called when the system frequency changes
+/// as registered by function hal_SysRequestFreq()
+// =============================================================================
+typedef VOID (*HAL_SYS_FREQ_CHANGE_HANDLER_T)(HAL_SYS_FREQ_T);
+
+
+
+// =============================================================================
+// HAL_SYS_MEM_FREQ_T
+// -----------------------------------------------------------------------------
+/// That type defines all the possible frequencies for the memory clock.
+/// Some frequencies might not be supported by some chips.
+// =============================================================================
+typedef enum
+{
+    HAL_SYS_MEM_FREQ_13M     = 13000000,
+    HAL_SYS_MEM_FREQ_26M     = 26000000,
+    HAL_SYS_MEM_FREQ_39M     = 39000000,
+    HAL_SYS_MEM_FREQ_52M     = 52000000,
+    HAL_SYS_MEM_FREQ_78M     = 78000000,
+    HAL_SYS_MEM_FREQ_89M     = 89142857, //624M/7
+    HAL_SYS_MEM_FREQ_104M    = 104000000,
+    HAL_SYS_MEM_FREQ_113M    = 113454545, //624M/5.5
+    HAL_SYS_MEM_FREQ_125M    = 124800000,
+    HAL_SYS_MEM_FREQ_139M    = 138666667, //624M/4.5
+    HAL_SYS_MEM_FREQ_156M    = 156000000,
+    HAL_SYS_MEM_FREQ_178M    = 178285714, //624M/3.5
+    HAL_SYS_MEM_FREQ_208M    = 208000000,
+    HAL_SYS_MEM_FREQ_250M    = 249600000, //624M/2.5
+    HAL_SYS_MEM_FREQ_312M    = 312000000,
+} HAL_SYS_MEM_FREQ_T;
+
+
+// =============================================================================
+// HAL_SYS_VOC_FREQ_T
+// -----------------------------------------------------------------------------
+/// That type defines all the possible frequencies for the VoC clock.
+/// Some frequencies might not be supported by some chips.
+// =============================================================================
+typedef enum
+{
+    HAL_SYS_VOC_FREQ_13M     = 13000000,
+    HAL_SYS_VOC_FREQ_26M     = 26000000,
+    HAL_SYS_VOC_FREQ_39M     = 39000000,
+    HAL_SYS_VOC_FREQ_52M     = 52000000,
+    HAL_SYS_VOC_FREQ_78M     = 78000000,
+    HAL_SYS_VOC_FREQ_89M     = 89142857, //624M/7
+    HAL_SYS_VOC_FREQ_104M    = 104000000,
+    HAL_SYS_VOC_FREQ_113M    = 113454545, //624M/5.5
+    HAL_SYS_VOC_FREQ_125M    = 124800000,
+    HAL_SYS_VOC_FREQ_139M    = 138666667, //624M/4.5
+    HAL_SYS_VOC_FREQ_156M    = 156000000,
+    HAL_SYS_VOC_FREQ_178M    = 178285714, //624M/3.5
+    HAL_SYS_VOC_FREQ_208M    = 208000000,
+    HAL_SYS_VOC_FREQ_250M    = 249600000, //624M/2.5
+    HAL_SYS_VOC_FREQ_312M    = 312000000,
+} HAL_SYS_VOC_FREQ_T;
+
+
+// =============================================================================
+// HAL_SYS_CLOCK_OUT_ID_T
+// -----------------------------------------------------------------------------
+/// That type defines all the possible user Id for the clock Out Pin sharing.
+// =============================================================================
+typedef enum
+{
+    /// returned when no more IDs are availlable
+    HAL_SYS_CLOCK_OUT_ID_1 = 0,
+    HAL_SYS_CLOCK_OUT_ID_2,
+    HAL_SYS_CLOCK_OUT_ID_3,
+    HAL_SYS_CLOCK_OUT_ID_4,
+
+    HAL_SYS_CLOCK_OUT_ID_QTY,
+
+    HAL_SYS_CLOCK_OUT_RESOURCE_UNAVAILABLE = -1
+} HAL_SYS_CLOCK_OUT_ID_T;
+
+
+// =============================================================================
+// HAL_SYS_CLOCK_OUT_FREQ_T
+// -----------------------------------------------------------------------------
+/// That type defines all the possible frequencies for the clock Out Pin.
+// =============================================================================
+typedef enum
+{
+    HAL_SYS_CLOCK_OUT_FREQ_32K  = 1,
+    HAL_SYS_CLOCK_OUT_FREQ_26M
+} HAL_SYS_CLOCK_OUT_FREQ_T;
+
+
+// =============================================================================
+// HAL_SYS_RESET_CAUSE_T
+// -----------------------------------------------------------------------------
+/// Describes the cause of a system reset. This type is returned by the function
+/// #hal_SysGetResetCause.
+// =============================================================================
+typedef enum
+{
+    /// Normal cause, ie power up
+    HAL_SYS_RESET_CAUSE_NORMAL,
+
+    /// The reset was caused by a watchdog
+    HAL_SYS_RESET_CAUSE_WATCHDOG,
+
+    /// The reset was caused by a soft restart, triggered by the function
+    /// #hal_SysRestart.
+    HAL_SYS_RESET_CAUSE_RESTART,
+
+    /// The reset was initiated from the Host Interface.
+    HAL_SYS_RESET_CAUSE_HOST_DEBUG,
+
+    /// The reset was caused by alarm, from the calendar.
+    HAL_SYS_RESET_CAUSE_ALARM,
+
+    HAL_SYS_RESET_CAUSE_QTY
+
+} HAL_SYS_RESET_CAUSE_T;
+
+
+// =============================================================================
+// HAL_SYS_CHIP_ID_T
+// -----------------------------------------------------------------------------
+/// Describes the cause of a system reset. This type is returned by the function
+/// #hal_SysGetResetCause.
+// =============================================================================
+typedef enum
+{
+    /// Chip product ID
+    HAL_SYS_CHIP_PROD_ID,
+
+    /// Chip bond ID
+    HAL_SYS_CHIP_BOND_ID,
+
+    /// Chip metal ID
+    HAL_SYS_CHIP_METAL_ID,
+
+    /// Chip ID whole
+    HAL_SYS_CHIP_ID_WHOLE,
+
+} HAL_SYS_CHIP_ID_T;
+
+
+// =============================================================================
+// HAL_SYS_CHIP_METAL_ID_T
+// -----------------------------------------------------------------------------
+/// Those are the different metal IDs.
+/// @todo fill
+// =============================================================================
+typedef enum
+{
+    HAL_SYS_CHIP_METAL_ID_U00 = 0x00,
+    HAL_SYS_CHIP_METAL_ID_U01,
+    HAL_SYS_CHIP_METAL_ID_U02,
+    HAL_SYS_CHIP_METAL_ID_U03,
+    HAL_SYS_CHIP_METAL_ID_U04,
+    HAL_SYS_CHIP_METAL_ID_U05,
+    HAL_SYS_CHIP_METAL_ID_U06,
+    HAL_SYS_CHIP_METAL_ID_U07,
+    HAL_SYS_CHIP_METAL_ID_U08,
+    HAL_SYS_CHIP_METAL_ID_U09,
+    HAL_SYS_CHIP_METAL_ID_U0a,
+    HAL_SYS_CHIP_METAL_ID_U0b,
+    HAL_SYS_CHIP_METAL_ID_U0c,
+    HAL_SYS_CHIP_METAL_ID_U0d,
+    HAL_SYS_CHIP_METAL_ID_U0e,
+    HAL_SYS_CHIP_METAL_ID_U0f,
+    HAL_SYS_CHIP_METAL_ID_U10,
+}HAL_SYS_CHIP_METAL_ID_T;
+
+
+
+// =============================================================================
+//  FUNCTIONS
+// =============================================================================
+
+
+// ============================================================================
+// hal_SysSetupPLL
+// ----------------------------------------------------------------------------
+/// Setup PLL at early system boot time.
+// ============================================================================
+PUBLIC VOID hal_SysSetupPLL(VOID);
+
+
+// =============================================================================
+// hal_SysStartBcpu
+// -----------------------------------------------------------------------------
+/// Start the BCPU with a stack to at the given address.
+/// @param bcpuMain Main function to run on the BCPU.
+/// @param stackStartAddr Stack top for the program running on the BCPU
+// =============================================================================
+PUBLIC VOID hal_SysStartBcpu(VOID* bcpuMain, VOID* stackStartAddr);
+
+
+// =============================================================================
+// hal_SysStopBcpu
+// -----------------------------------------------------------------------------
+/// Stop the BCPU and leave it in reset
+/// Use it for debug only as it is prefereable to 
+/// not send any commands to it
+// =============================================================================
+PUBLIC VOID hal_SysStopBcpu(VOID);
+
+
+// =============================================================================
+// hal_SysSetRequestFreq
+// -----------------------------------------------------------------------------
+/// When a given users requires a minimum frequency to be able to execute a
+/// task, this function must be called.
+/// @param userId Identifier of the calling user.
+/// @param minFreq Minimum required frequency.
+/// @param handler User function registered for this userId 
+/// The function is called when the frequency is switched by any following call
+/// to hal_SysSetRequestFreq() including the current one.
+/// If \c NULL, no function is registered.
+// =============================================================================
+PUBLIC VOID hal_SysRequestFreq(HAL_SYS_FREQ_USER_ID_T userId, HAL_SYS_FREQ_T minFreq,
+                                HAL_SYS_FREQ_CHANGE_HANDLER_T handler);
+
+
+
+// =============================================================================
+// hal_SysGetRequestFreq
+// -----------------------------------------------------------------------------
+/// Get the minimum frequency required by a given user
+/// @param userId Identifier of the calling user.
+/// @return The minimum required frequency for this user.
+// =============================================================================
+PUBLIC HAL_SYS_FREQ_T hal_SysGetRequestFreq(HAL_SYS_FREQ_USER_ID_T userId);
+
+
+
+// =============================================================================
+// hal_SysGetFreq
+// -----------------------------------------------------------------------------
+/// Get the current system clock frequency.
+/// @return The current system clock frequency.
+// =============================================================================
+PUBLIC HAL_SYS_FREQ_T hal_SysGetFreq(VOID);
+
+
+
+// =============================================================================
+// hal_SysSetBBClock
+// -----------------------------------------------------------------------------
+/// Set the BB clock.
+/// @param newClock New BB clock.
+// =============================================================================
+PUBLIC VOID hal_SysSetBBClock(HAL_SYS_BB_FREQ_T newClock);
+
+
+
+// =============================================================================
+// hal_SysSetVocClock
+// -----------------------------------------------------------------------------
+/// Set the VOC clock.
+/// @param newClock New VOC clock.
+/// @return Old VOC clock.
+// =============================================================================
+PUBLIC HAL_SYS_VOC_FREQ_T hal_SysSetVocClock(HAL_SYS_VOC_FREQ_T newClock);
+
+
+
+// =============================================================================
+// hal_SysShutdown
+// -----------------------------------------------------------------------------
+/// A call to this function shuts the system down.
+// =============================================================================
+PUBLIC VOID hal_SysShutdown(VOID);
+
+
+
+// =============================================================================
+// hal_SysSoftReset
+// -----------------------------------------------------------------------------
+/// Does a soft reset on the chip.
+/// Generally, you should NOT use this function, use hal_SysRestart() instead.
+// =============================================================================
+PUBLIC VOID hal_SysSoftReset(VOID);
+
+
+
+// =============================================================================
+// hal_SysRestart
+// -----------------------------------------------------------------------------
+/// A call to this function reboots the system.
+/// First, this function does a power cycle on USB
+// =============================================================================
+PUBLIC VOID hal_SysRestart(VOID);
+
+
+
+// =============================================================================
+// hal_SysGetResetCause
+// -----------------------------------------------------------------------------
+/// Get the cause of the last reset.
+/// This function only returns the reset cause. It does not proceed to any test
+/// to now if the boot was due to a press on the Power On button or because
+/// the charger was plugged. Those tests are to be done by the user code, 
+/// when this function returns HAL_SYS_RESET_CAUSE_ALARM.
+/// @return The last reset cause
+// =============================================================================
+PUBLIC HAL_SYS_RESET_CAUSE_T hal_SysGetResetCause(VOID);
+
+
+
+// =============================================================================
+// hal_SysSleep 
+// -----------------------------------------------------------------------------
+/// Check if the system can sleep and, in that case, make it sleep.
+///
+/// This function is to be called by pal_Sleep, normally in
+/// the idle task. It switches the system on the 32khz clock if no user requires
+/// a higher clock and if it is ready to do it, ie: the LPS is operational
+// =============================================================================
+PUBLIC VOID hal_SysSleep(VOID);
+
+
+
+// =============================================================================
+// hal_SysResetOut
+// -----------------------------------------------------------------------------
+/// A call to this function resets an external device through the reset-out
+/// line, if the parameter is \c TRUE.
+/// @param resetOut If \c TRUE, rises the reset-out line.
+///                 If \c FALSE, pulls it down.
+// =============================================================================
+PUBLIC VOID hal_SysResetOut(BOOL resetOut);
+
+
+
+// =============================================================================
+// hal_SysInvalidateCache
+// -----------------------------------------------------------------------------
+/// This function invalidates in the cache the line corresponding to the given 
+/// memory area, referred by a pointer and a size.
+/// It must be called with the destination buffer after a DMA copy.
+/// @param buffer Pointer to the first address whose cache line must be 
+/// invalidated
+/// @param size Size of the buffer.
+// =============================================================================
+PUBLIC VOID hal_SysInvalidateCache(VOID* buffer, UINT32 size);
+
+
+
+// =============================================================================
+// hal_SysGetChipId
+// -----------------------------------------------------------------------------
+/// That function gives the chip ID the software is running on.
+/// @param part Which part of the chip ID
+/// @return The requested part of the chip ID.
+// =============================================================================
+PUBLIC UINT32 hal_SysGetChipId(HAL_SYS_CHIP_ID_T part);
+
+
+
+// =============================================================================
+// g_halSysCsAddress
+// -----------------------------------------------------------------------------
+/// This global variable stores the address of the chip critical section.
+///
+/// *ATTENTION* It is forbidden to use  global variables, but here we e
+/// exceptionally need to have one for critical performance reasons.
+/// This is not an exchange variable, it is forbidden to use it directly.
+///
+/// hal_SysEnterCriticalSection and hal_SysExitCriticalSection are inline 
+/// built using that variable and must be used to access the critical 
+/// section.
+// =============================================================================
+EXPORT VOLATILE UINT32* g_bootSysCsAddress;
+
+
+
+// =============================================================================
+// hal_SysEnterCriticalSection
+// -----------------------------------------------------------------------------
+/// This function enters in a critical section (relative to the hardware 
+/// interrupts) and return a status that should be given to the 
+/// #hal_SysExitCriticalSection function.
+/// 
+/// @return  The \c status that should be given to the #hal_SysExitCriticalSection 
+/// function.
+// =============================================================================
+INLINE UINT32 hal_SysEnterCriticalSection(VOID)
+{
+    UINT32  myLocalVar = *g_bootSysCsAddress;
+    // add this empty assembly line to avoid the compiler to re-order
+    // the code around the critical section call
+    asm volatile ("");
+    return myLocalVar;
+}
+
+
+
+
+// =============================================================================
+// hal_SysExitCriticalSection
+// -----------------------------------------------------------------------------
+/// This function leaves the critical section. The <CODE>status</CODE> 
+/// parameter is the return value of the #hal_SysEnterCriticalSection call
+/// that opened the critical section.
+/// 
+/// @param status The value returned by #hal_SysEnterCriticalSection.
+// =============================================================================
+INLINE VOID hal_SysExitCriticalSection(UINT32 status)
+{
+    // add this empty assembly line to avoid the compiler to re-order
+    // the code around the critical section call
+    asm volatile ("");
+   *g_bootSysCsAddress = status;
+}
+
+
+
+// =============================================================================
+// hal_SysGetSp
+// -----------------------------------------------------------------------------
+/// This function returns the current value of the stack register
+/// @return The current value of the stack pointer.
+// =============================================================================
+PUBLIC UINT32 hal_SysGetSp(VOID);
+
+
+
+// =============================================================================
+// hal_SysClkOutOpen
+// -----------------------------------------------------------------------------
+/// Manage the output of the clock-out, to an external device
+///
+/// This function requests a resource of #HAL_SYS_FREQ_26M or release it 
+/// to #HAL_SYS_FREQ_32K depending on the \p freq parameter value.
+///
+/// @param freq the required frequency
+/// @return the user id to be used for #hal_SysClkOutClose
+///         or #HAL_SYS_CLOCK_OUT_RESOURCE_UNAVAILABLE when the clock is already
+///         in use at a different frequency.
+// =============================================================================
+PUBLIC HAL_SYS_CLOCK_OUT_ID_T hal_SysClkOutOpen(HAL_SYS_CLOCK_OUT_FREQ_T freq);
+
+
+
+// =============================================================================
+// hal_SysClkOutClose
+// -----------------------------------------------------------------------------
+/// Manage the output of the clock-out, to an external device
+///
+/// This function release a resource to #HAL_SYS_FREQ_32K.
+///
+/// @param id the user id returned by #hal_SysClkOutOpen
+// =============================================================================
+PUBLIC VOID hal_SysClkOutClose(HAL_SYS_CLOCK_OUT_ID_T id);
+
+
+
+// ==========================================================================
+// hal_SysAuxClkOut
+// --------------------------------------------------------------------------
+/// Manage the output of the 26M AUX Clock, to an external device
+/// @param enable If \c TRUE, enable AuxClk output.
+///               If \c FALSE, disable AuxClk output.
+// ==========================================================================
+PUBLIC VOID hal_SysAuxClkOut(BOOL enable);
+
+
+
+// ==========================================================================
+// hal_Sys32kClkOut
+// --------------------------------------------------------------------------
+/// Manage the output of the 32K Clock, to an external device
+/// @param enable If \c TRUE, enable 32K clock output.
+///               If \c FALSE, disable 32K clock output.
+// ==========================================================================
+PUBLIC VOID hal_Sys32kClkOut(BOOL enable);
+
+
+
+#if (!CHIP_HAS_ASYNC_TCU)
+// =============================================================================
+// hal_SysQBitError
+// -----------------------------------------------------------------------------
+/// This function returns error on QBit due to clock switch mechanism.
+/// If the error has to be compensated the error is cleared.
+/// @param forceReset force to clear the error counter.
+/// @return -1, 0 or 1 QBit error to be compensated.
+// =============================================================================
+PUBLIC INT32 hal_SysQBitError(BOOL forceReset);
+#endif // (!CHIP_HAS_ASYNC_TCU)
+
+
+
+// =============================================================================
+// hal_SysIrqPending
+// -----------------------------------------------------------------------------
+/// This function checks the IRQ pending status. It should be called in critical
+/// section to know if some IRQ are pending and then decide to release the 
+/// critical section.
+/// @return \c TRUE if IRQ are pending.
+///         \c FALSE Otherwise.
+// =============================================================================
+PUBLIC BOOL hal_SysIrqPending(VOID);
+
+
+
+// =============================================================================
+// hal_SysProcessHostMonitor
+// -----------------------------------------------------------------------------
+/// This function is called in the idle task or in gdb loop.
+/// It is used to execute the function processing possible commands
+/// from the Host.
+// =============================================================================
+PUBLIC VOID hal_SysProcessHostMonitor(VOID);
+
+
+
+// =============================================================================
+// hal_SysProcessIdle
+// -----------------------------------------------------------------------------
+/// This function is called in the idle task. 
+/// It is used to execute in idle the function processing possible commands
+/// from the Host, and thus, for example, call the executor. etc ...
+// =============================================================================
+PUBLIC VOID hal_SysProcessIdle(VOID);
+
+
+
+// =============================================================================
+// hal_SysWaitMicrosecond
+// -----------------------------------------------------------------------------
+/// This function wait some time in microseconds.
+/// It calculates CPU instruction cycles needed, depending on current system frequency.
+/// Note that it does NOT have critical section operations.
+/// @param us Microseconds to wait.
+// =============================================================================
+PUBLIC VOID hal_SysWaitMicrosecond(UINT32 us);
+
+
+
+// =============================================================================
+// hal_BootEnterMonitor
+// -----------------------------------------------------------------------------
+/// Call this function to enter the boot monitor.
+// =============================================================================
+PUBLIC VOID hal_BootEnterMonitor(VOID);
+
+
+
+// =============================================================================
+// hal_BootRegisterBeforeMonCallback
+// -----------------------------------------------------------------------------
+/// Call this function to register a callback function which is run
+/// before entering the boot monitor.
+// =============================================================================
+PUBLIC VOID hal_BootRegisterBeforeMonCallback(VOID (*funcPtr)(VOID));
+
+
+
+/// @} // end of the system group
+
+
+
+#endif // _HAL_SYS_H_
+
diff --git a/board/rda/common/include/hal_tcu.h b/board/rda/common/include/hal_tcu.h
new file mode 100644
index 0000000000..242c249d84
--- /dev/null
+++ b/board/rda/common/include/hal_tcu.h
@@ -0,0 +1,330 @@
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//            Copyright (C) 2003-2007, Coolsand Technologies, Inc.            //
+//                            All Rights Reserved                             //
+//                                                                            //
+//      This source code is the property of Coolsand Technologies and is      //
+//      confidential.  Any  modification, distribution,  reproduction or      //
+//      exploitation  of  any content of this file is totally forbidden,      //
+//      except  with the  written permission  of  Coolsand Technologies.      //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//  $HeadURL: http://svn.rdamicro.com/svn/developing1/Sources/chip/branches/8810/hal/include/hal_tcu.h $ //
+//    $Author: huazeng $                                                        // 
+//    $Date: 2013-07-08 14:14:23 +0800 (Mon, 08 Jul 2013) $                     //   
+//    $Revision: 20589 $                                                          //   
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+/// @file hal_tcu.h                                                           //
+/// That file provides the TCU driver API                                     //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+
+
+
+#ifndef _HAL_TCU_H_
+#define _HAL_TCU_H_
+
+/// @defgroup tcu HAL TCU driver
+///
+/// @{
+// =============================================================================
+//  MACROS
+// =============================================================================
+
+typedef enum
+{
+    HAL_TCU_TCO_GMSK_ON                                 = 0x00000006,
+    HAL_TCU_TCO_TX_OEN                                  = 0x00000007,
+    HAL_TCU_TCO_TX_ON                                   = 0x00000008,
+    HAL_TCU_TCO_RX_ON                                   = 0x00000009,
+    HAL_TCU_TCO_RX_DEC_ON                           = 0x0000000a,
+    HAL_TCU_TCO_RX_PDN                                 = 0x0000000b,
+} HAL_TCU_TCO_MAPPING_T;
+
+
+// =============================================================================
+// SET_TCO
+// -----------------------------------------------------------------------------
+/// This define must be used to build the TCU events.
+/// It must NOT be used to pass a tcoNumber, for instance it
+/// must NOT be used for the parameters passed to the functions:
+/// hal_TcuSetTco(), hal_TcuClrTco() or hal_TcuPulseTco().
+// =============================================================================
+#define SET_TCO(n)           ((n<<1) | 0x1)
+
+// =============================================================================
+// CLR_TCO
+// -----------------------------------------------------------------------------
+/// This define must be used to build the TCU events.
+/// It must NOT be used to pass a tcoNumber, for instance it
+/// must NOT be used for the parameters passed to the functions:
+/// hal_TcuSetTco(), hal_TcuClrTco() or hal_TcuPulseTco().
+// =============================================================================
+#define CLR_TCO(n)           ((n<<1))
+
+// =============================================================================
+// MASK_TCO
+// -----------------------------------------------------------------------------
+/// This define must be used to build the TCU events.
+/// It must NOT be used to pass a tcoNumber, for instance it
+/// must NOT be used for the parameters passed to the functions:
+/// hal_TcuSetTco(), hal_TcuClrTco() or hal_TcuPulseTco().
+// =============================================================================
+#define MASK_TCO(n)          (1<<n)
+
+// =============================================================================
+// HAL_TCU_MASK_DTX
+// -----------------------------------------------------------------------------
+/// These defines are used to disable the different Tx signals in case of DTX.
+// =============================================================================
+#define HAL_TCU_MASK_TCO_GMSK_ON             MASK_TCO(HAL_TCU_TCO_GMSK_ON)
+#define HAL_TCU_MASK_TCO_TX_OEN              MASK_TCO(HAL_TCU_TCO_TX_OEN)
+#define HAL_TCU_MASK_TCO_TX_ON               MASK_TCO(HAL_TCU_TCO_TX_ON)
+
+// =============================================================================
+// HAL_TCU_MASK_RX
+// -----------------------------------------------------------------------------
+/// These defines are used to disable the different Rx signals in case of Rx on.
+// =============================================================================
+#define HAL_TCU_MASK_TCO_RX_PDN      MASK_TCO(HAL_TCU_TCO_RX_PDN)
+#define HAL_TCU_MASK_TCO_RX_DEC_ON      MASK_TCO(HAL_TCU_TCO_RX_DEC_ON)
+
+// Values copied by "tcu.h". If tcu.h changes these values need to be updated.
+#define HAL_TCU_MASK_RAMP                   (31<<19)
+#define HAL_TCU_MASK_DIGRF_STROBE            (1<<25)
+#define HAL_TCU_MASK_RF_SPI_MARKED_CMD       (1<<31)
+
+// =============================================================================
+// TCO
+// -----------------------------------------------------------------------------
+/// This define can be used for the parameters passed to the functions:
+/// hal_TcuSetTco(), hal_TcuClrTco() or hal_TcuPulseTco().
+// =============================================================================
+#define TCO(n)               (n)
+
+#define TCO_UNUSED           (-1)
+
+
+// =============================================================================
+//  Types
+// =============================================================================
+
+// =============================================================================
+// HAL_TCU_EVENT_ID_T
+// -----------------------------------------------------------------------------
+/// This type lists all the TCU events
+// =============================================================================
+typedef enum {
+    // TODO: should get rid of useless event
+    /// Clear TCO #0    
+    HAL_TCU_TCO_0_CLR, //0
+    /// Set TCO #0
+    HAL_TCU_TCO_0_SET,
+    HAL_TCU_TCO_1_CLR,
+    HAL_TCU_TCO_1_SET,
+    HAL_TCU_TCO_2_CLR,
+    HAL_TCU_TCO_2_SET,
+    HAL_TCU_TCO_3_CLR,
+    HAL_TCU_TCO_3_SET,
+    HAL_TCU_TCO_4_CLR,
+    HAL_TCU_TCO_4_SET,
+    HAL_TCU_TCO_5_CLR, // 10
+    HAL_TCU_TCO_5_SET,
+    /// stop modulation
+    HAL_TCU_STOP_GMSK,
+    /// starts modulation and output on IQ DAC
+    HAL_TCU_START_GMSK,
+    HAL_TCU_HIGHZ_IQ_DAC,
+    HAL_TCU_DRIVE_IQ_DAC,
+    HAL_TCU_DISABLE_IQ_DAC,
+    HAL_TCU_ENABLE_IQ_DAC,
+    /// disable IQ ADC
+    HAL_TCU_DISABLE_IQ_ADC,
+    /// enable IQ ADC
+    HAL_TCU_ENABLE_IQ_ADC,
+    /// stop recording IQ samples
+    HAL_TCU_STOP_RFIN_RECORD,
+    /// start recording IQ samples
+    HAL_TCU_START_RFIN_RECORD,
+    /// Clear RF_PDN
+    HAL_TCU_CLR_PDN,
+    /// Set RF_PDN
+    HAL_TCU_SET_PDN,
+    /// sends a sequence of commands to the RF chip through spi
+    HAL_TCU_SEND_SPI_CMD,
+    HAL_TCU_NEXT_GAIN,
+    HAL_TCU_FIRST_GAIN,
+    /// set the next value in fifo on frequency control DAC
+    HAL_TCU_SET_NEXT_FC,
+    /// send the pre-programmed ramp0 and stay at the final level
+    HAL_TCU_PA_USE_RAMP0,
+    HAL_TCU_PA_USE_RAMP1,
+    HAL_TCU_PA_USE_RAMP2,
+    HAL_TCU_PA_USE_RAMP3,
+    HAL_TCU_PA_USE_RAMP4,
+    HAL_TCU_RX_SOC,
+    HAL_TCU_DIGRF_STB,
+    /// trigger one irq on the BCPU
+    HAL_TCU_TRIGGER_BCPU_SOFTIRQ0,
+    HAL_TCU_TRIGGER_BCPU_SOFTIRQ1,
+    /// trigger one irq on the XCPU
+    HAL_TCU_TRIGGER_XCPU_SOFTIRQ0,
+    HAL_TCU_TRIGGER_XCPU_SOFTIRQ1,
+    /// End of the WakeUp mode
+    HAL_TCU_WAKEUP_DONE,
+    HAL_TCU_NO_EVENT = 0x3f
+} HAL_TCU_EVENT_ID_T;
+
+
+// =============================================================================
+// hal_TcuInit
+// -----------------------------------------------------------------------------
+/// Initialize the TCU
+/// This function opens the TCU and configures the TCO polarities.
+/// @param tcoPolarity Bitfield where '0' means the corresponding. Only the
+/// lowest 17 bits are relevant.
+/// TCO output is active high and '1' that it is active low
+// =============================================================================
+PUBLIC VOID hal_TcuOpen(UINT32 tcoPolarity);
+
+
+// =============================================================================
+// hal_TcuStart
+// -----------------------------------------------------------------------------
+/// Start the TCU with an initial Value
+/// @param value Value loaded in the TCU counter when it starts.
+// =============================================================================
+PUBLIC VOID hal_TcuStart (UINT16 value);
+
+
+
+// =============================================================================
+// hal_TcuStop
+// -----------------------------------------------------------------------------
+/// Stops the TCU
+// =============================================================================
+PUBLIC VOID hal_TcuStop(VOID);
+
+
+
+// =============================================================================
+// hal_TcuSetTco
+// -----------------------------------------------------------------------------
+/// This function sets the corresponding TCO line to its
+/// active level (which depends on TCO's polarity)
+/// @param tcoNumber: index of the TCO to be set,
+/// you can use the define TCO(n). No need to shift the number.
+// =============================================================================
+PUBLIC VOID hal_TcuSetTco(UINT8 tcoNumber);
+
+
+
+// =============================================================================
+// hal_TcuClrTco
+// -----------------------------------------------------------------------------
+/// This function sets the corresponding TCO line to its
+/// inactive level (which depends on TCO's polarity)
+/// @param tcoNumber: index of the TCO to be reset,
+/// you can use the define TCO(n). No need to shift the number.
+// =============================================================================
+PUBLIC VOID hal_TcuClrTco(UINT8 tcoNumber);
+
+
+
+// =============================================================================
+// hal_TcuPulseTco
+// -----------------------------------------------------------------------------
+/// This function  must only be called when the TCU timings are not available.
+/// Send a pulse on a TCO.
+/// @param tcoNumber: index of the TCO, you can use the define TCO(n). No need
+/// to shift the number.
+/// @param time Time in number of 16384Hz tick between the rise and the fall
+// =============================================================================
+PUBLIC VOID hal_TcuPulseTco(UINT8 tcoNumber, UINT16 time);
+
+
+
+// =============================================================================
+// hal_TcuGetCount
+// -----------------------------------------------------------------------------
+/// Get the TCU counter
+/// Only the less significant 14 bits are 
+/// relevant.
+/// @return The TCU counter
+// =============================================================================
+PUBLIC UINT32 hal_TcuGetCount(VOID);
+
+
+
+// =============================================================================
+// hal_TcuSetWrap
+// -----------------------------------------------------------------------------
+/// Set the wrap value
+/// It is the time when the programming table becomes
+/// the active table. The counter's next value is 0.
+/// Only the less significant 14 bits are 
+/// relevant to set the counter.
+/// @param value Wrap Value
+// =============================================================================
+PUBLIC VOID hal_TcuSetWrap(UINT32 value);
+
+
+// =============================================================================
+// hal_TcuSetEvent
+// -----------------------------------------------------------------------------
+/// Set a TCU event.
+/// This function handles the increment of TCU's event
+/// pointer.
+/// @param evId Event id, that is the event to set.
+/// @param time Time when the foresaid event is to be
+/// triggered.
+// =============================================================================
+PUBLIC VOID hal_TcuSetEvent( HAL_TCU_EVENT_ID_T evId, UINT16 time);
+
+
+// =============================================================================
+// hal_TcuClrEvtRange
+// -----------------------------------------------------------------------------
+/// Remove a range of events.
+///
+/// @param first first event to be removed.
+/// @param last last event to be removed.
+// =============================================================================
+PUBLIC VOID hal_TcuClrEvtRange(UINT8 first, UINT8 last);
+
+// =============================================================================
+// hal_TcuClrAllEvents
+// -----------------------------------------------------------------------------
+/// Remove all active and programmed events
+///
+// =============================================================================
+PUBLIC VOID hal_TcuClrAllEvents(VOID);
+
+
+// =============================================================================
+// hal_TcuSetEvtPtr
+// -----------------------------------------------------------------------------
+/// Set TCU's event pointer 
+/// @param tcuPtr new pointer position.
+// =============================================================================
+PUBLIC VOID hal_TcuSetEvtPtr(UINT8 tcuPtr);
+
+
+
+// =============================================================================
+// hal_TcuGetEvtPtr
+// -----------------------------------------------------------------------------
+/// Get current value of TCU's event pointer.
+/// @return The current value of the TCU's event pointer.
+// =============================================================================
+PUBLIC UINT8 hal_TcuGetEvtPtr(VOID);
+
+
+/// @} // <-- End of the TCU group
+#endif // _HAL_TCU_H_
+
+
+
diff --git a/board/rda/common/include/halp_gpio.h b/board/rda/common/include/halp_gpio.h
new file mode 100644
index 0000000000..d45bc43a90
--- /dev/null
+++ b/board/rda/common/include/halp_gpio.h
@@ -0,0 +1,64 @@
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//            Copyright (C) 2003-2007, Coolsand Technologies, Inc.            //
+//                            All Rights Reserved                             //
+//                                                                            //
+//      This source code is the property of Coolsand Technologies and is      //
+//      confidential.  Any  modification, distribution,  reproduction or      //
+//      exploitation  of  any content of this file is totally forbidden,      //
+//      except  with the  written permission  of  Coolsand Technologies.      //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//  $HeadURL: http://svn.rdamicro.com/svn/developing1/Sources/chip/branches/8810/hal/src/halp_gpio.h $ //
+//    $Author: admin $                                                        // 
+//    $Date: 2010-07-07 20:28:03 +0800 (Wed, 07 Jul 2010) $                     //   
+//    $Revision: 269 $                                                          //   
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+/// @file halp_gpio.h                                                         //
+/// This file contains Granite's GPIO driver implementation                   //
+//                                                                            //
+//////////////////////////////////////////////////////////////////////////////// 
+
+
+#ifndef  _HALP_GPIO_H_
+#define  _HALP_GPIO_H_
+
+// =============================================================================
+// MACROS
+// =============================================================================
+
+// =============================================================================
+// HAL_GPIO_BIT
+// -----------------------------------------------------------------------------
+/// This macro is used by internal code to convert gpio number to bit.
+/// It masks the upper bit so it can be used directly with #HAL_GPIO_GPIO_ID_T.
+// =============================================================================
+#define HAL_GPIO_BIT(n)    (1<<((n)&0x3f))
+
+// =============================================================================
+// HAL_GPO_BIT
+// -----------------------------------------------------------------------------
+/// This macro is used by internal code to convert gpio number to bit.
+/// It masks the upper bit so it can be used directly with #HAL_GPIO_GPO_ID_T.
+// =============================================================================
+#define HAL_GPO_BIT(n)    (1<<((n)&0x3f))
+
+
+
+
+// =============================================================================
+// hal_GpioIrqHandler
+// -----------------------------------------------------------------------------
+/// GPIO module IRQ handler
+/// 
+///     Clear the IRQ and call the IRQ handler
+///     user function
+///     @param interruptId The interruption ID
+// =============================================================================  
+PROTECTED VOID hal_GpioIrqHandler(UINT8 interruptId);
+
+
+#endif //HAL_GPIO_H
diff --git a/board/rda/common/include/halp_sys.h b/board/rda/common/include/halp_sys.h
new file mode 100644
index 0000000000..e962ac8aca
--- /dev/null
+++ b/board/rda/common/include/halp_sys.h
@@ -0,0 +1,404 @@
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//            Copyright (C) 2003-2007, Coolsand Technologies, Inc.            //
+//                            All Rights Reserved                             //
+//                                                                            //
+//      This source code is the property of Coolsand Technologies and is      //
+//      confidential.  Any  modification, distribution,  reproduction or      //
+//      exploitation  of  any content of this file is totally forbidden,      //
+//      except  with the  written permission  of  Coolsand Technologies.      //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//
+//  $HeadURL: http://svn.rdamicro.com/svn/developing1/Sources/chip/branches/8810/hal/src/halp_sys.h $
+//  $Author: huazeng $
+//  $Date: 2013-08-05 11:38:03 +0800 (Mon, 05 Aug 2013) $
+//  $Revision: 20799 $
+//
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+/// @file halp_sys.h                                                          //
+/// That file provides the private interface for the System Driver.           //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+
+#ifndef  _HALP_SYS_H_
+#define  _HALP_SYS_H_
+
+// =============================================================================
+// 
+// -----------------------------------------------------------------------------
+// =============================================================================
+
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+
+
+// =============================================================================
+// HAL_SYS_FREQ_MAX_RESOURCE_NB
+// -----------------------------------------------------------------------------
+/// Maximum number of resources
+// =============================================================================
+#define HAL_SYS_FREQ_MAX_RESOURCE_NB  64
+
+
+// =============================================================================
+// HAL_SYS_FREQ_WIDTH
+// -----------------------------------------------------------------------------
+/// Width of the bitfield holding a frequency value in bits.
+/// Not sure that scales pretty well...
+// =============================================================================
+#define HAL_SYS_FREQ_WIDTH  8
+
+
+
+// default clock generation params
+// PCM_CLOCKS_POLARITY : INVERT_PCM_BCK | INVERT_PCM_MCK
+#define PCM_CLOCKS_POLARITY 0
+// ANA_CLOCKS_POLARITY : INVERT_AU_ADC_CLK | INVERT_TX_FS_CLK 
+//  | INVERT_RX_FS_CLK | INVERT_PA_DAC_CLK | INVERT_AFC_DAC_CLK
+#define ANA_CLOCKS_POLARITY ANA_ACCO_GPADC_CLK_POL
+// RF_FS_SETTING : RX_FS_IS_13M, RX_FS_IS_6M5
+#define RF_FS_SETTING RX_FS_IS_6M5
+// AFC_DIVIDER_SETTING : n
+#define AFC_DIVIDER_SETTING 8
+#define GPADC_DIVIDER_SETTING   0x1F
+
+
+#define PLL_CONFIG (SYS_CTRL_PLL_R(4-2) | SYS_CTRL_PLL_F(48-2) | SYS_CTRL_PLL_OD_DIV_BY_1)
+
+// =============================================================================
+//  TYPES
+// =============================================================================
+
+// =============================================================================
+// HAL_SYS_FREQ_SCAL_USERS_T
+// -----------------------------------------------------------------------------
+/// That type lists all the possible entities (software / drivers / peripherals)
+/// that need a specific minimum clock.
+/// This is the internal type for HAL use only. Specific resource identifiers
+/// are exported through the interface for use in upper layer or by upper 
+/// layers.
+/// The list attempts to be exhaustive, but could contain useless fields
+/// and lack some others. Don't forget to adjust #HAL_SYS_TENS_QTY consequently.
+// =============================================================================
+typedef enum
+{
+    HAL_SYS_FREQ_PWM, // 0
+    HAL_SYS_FREQ_SIM,
+    HAL_SYS_FREQ_SPI,
+    HAL_SYS_FREQ_TRACE,
+    HAL_SYS_FREQ_UART,
+    HAL_SYS_FREQ_I2C, // 5
+    HAL_SYS_FREQ_RF_SPI,
+    HAL_SYS_FREQ_DEBUG_HOST,
+    HAL_SYS_FREQ_AIF,
+    HAL_SYS_FREQ_AUDIO,
+    HAL_SYS_FREQ_HAL_NULL_0, // 10
+    HAL_SYS_FREQ_SDMMC,
+    HAL_SYS_FREQ_SDMMC2,
+    HAL_SYS_FREQ_LCD,
+    HAL_SYS_FREQ_CLK_OUT,
+    HAL_SYS_FREQ_CAMCLK, // 15
+    HAL_SYS_FREQ_USB,
+    HAL_SYS_FREQ_DMA,
+    HAL_SYS_FREQ_VOC,
+    HAL_SYS_FREQ_AP,
+    HAL_SYS_FREQ_BTCPU, // 20
+    // !!! Add new sys users above !!!
+    HAL_SYS_FREQ_SYS_USER_END,
+    HAL_SYS_FREQ_SYS_LAST_USER = HAL_SYS_FREQ_SYS_USER_END-1,
+
+// The last sys user ID should be less than the first platform user
+// ID, which is 25 in hal_sys.h at present.
+// This is checked in hal_SysSetupSystemClock, PROTECTED function
+// called only once during hal_Open().
+    HAL_SYS_USER_START = HAL_SYS_FREQ_PLATFORM_FIRST_USER,
+
+    HAL_SYS_TOTAL_USERS_QTY = HAL_SYS_FREQ_USER_QTY
+
+} HAL_SYS_FREQ_SCAL_USERS_T;
+
+
+// =============================================================================
+// HAL_SYS_FREQ_SCAL_FREQ_T
+// -----------------------------------------------------------------------------
+/// This list the possible value for the frequency required by the frequence 
+/// scaling users. This type differs from the one in the interface because
+/// the value here have to be stored into the #HAL_SYS_FREQ_WIDTH (8 bits) wide
+/// field. It is only used in the managing of the frequency scaling.
+// =============================================================================
+typedef enum
+{
+    HAL_SYS_FREQ_SCAL_32K   = 0,
+    HAL_SYS_FREQ_SCAL_13M   = 1,
+    HAL_SYS_FREQ_SCAL_26M   = 2,
+    HAL_SYS_FREQ_SCAL_39M   = 3,
+    HAL_SYS_FREQ_SCAL_52M   = 4,
+    HAL_SYS_FREQ_SCAL_78M   = 5,
+    HAL_SYS_FREQ_SCAL_104M  = 6,
+    HAL_SYS_FREQ_SCAL_156M  = 7,
+#if (CHIP_HAS_ASYNC_TCU)
+    HAL_SYS_FREQ_SCAL_208M  = 8,
+    HAL_SYS_FREQ_SCAL_250M  = 9,
+    HAL_SYS_FREQ_SCAL_312M  = 10,
+#endif
+    HAL_SYS_FREQ_SCAL_QTY
+
+} HAL_SYS_FREQ_SCAL_FREQ_T;
+
+
+//// =============================================================================
+////  EXPORTED VARIABLES
+//// =============================================================================
+//
+//#if (CHIP_HAS_ASYNC_TCU)
+//// ============================================================================
+//// g_bootSysTcuRunningAt26M
+//// ----------------------------------------------------------------------------
+/////  Whether TCU is running at 26M
+//// ============================================================================
+//PUBLIC EXPORT BOOL g_bootSysTcuRunningAt26M;
+//#endif
+//
+//// =============================================================================
+//// g_halSysFreqScalRegistry
+//// -----------------------------------------------------------------------------
+///// This array is used to store the frequency required by each frequency scaling
+///// user, a dime a tens.
+//// =============================================================================
+//PROTECTED EXPORT UINT32 g_halSysFreqScalRegistry[HAL_SYS_FREQ_MAX_RESOURCE_NB/4];
+//
+//// ============================================================================
+//// g_halSysSystemFreq
+//// ----------------------------------------------------------------------------
+/////  Global var to have a view of the system frequency
+//// ============================================================================
+//PROTECTED EXPORT HAL_SYS_FREQ_T g_halSysSystemFreq;
+//
+//// ============================================================================
+//// g_halNumberOfUserPerFreq
+//// ----------------------------------------------------------------------------
+///// This array is used to calculate the minimum system frequency to set
+///// (that is the maximum required by a module among all the module) in a 
+///// constant time (relative to the number of users).
+///// 
+//// ============================================================================
+//PROTECTED EXPORT UINT32 g_halNumberOfUserPerFreq[HAL_SYS_FREQ_SCAL_QTY];
+//
+//
+//// =============================================================================
+////  FUNCTIONS
+//// =============================================================================
+//
+//// =============================================================================
+//// hal_SysFreqScalSet
+//// -----------------------------------------------------------------------------
+///// Set the required frequency for a given user in the frequency scaling
+///// registry.
+///// @param user Frequency scaling user Id.
+///// @param freq Minimum frequency required by this user.
+//// =============================================================================
+//INLINE VOID hal_SysFreqScalSet(HAL_SYS_FREQ_SCAL_USERS_T user, HAL_SYS_FREQ_SCAL_FREQ_T freq)
+//{
+//    UINT8* registry = (UINT8*)g_halSysFreqScalRegistry;
+//
+//    // We exit the previous frequency class
+//    g_halNumberOfUserPerFreq[registry[user]] -=1;
+//
+//    // To enter the new one
+//    g_halNumberOfUserPerFreq[freq] += 1;
+//
+//    // Update the registry
+//    registry[user] = freq;
+//}
+//
+//
+//
+//// =============================================================================
+//// hal_SysFreqScalGet
+//// -----------------------------------------------------------------------------
+///// Get the required frequency for a given user.
+///// @return The frequency required by a given user. 
+//// =============================================================================
+//INLINE HAL_SYS_FREQ_SCAL_FREQ_T hal_SysFreqScalGet(HAL_SYS_FREQ_SCAL_USERS_T user)
+//{
+//    UINT8* registry = (UINT8*)g_halSysFreqScalRegistry;
+//    return (registry[user]);
+//}
+//
+//// =============================================================================
+//// hal_SysSF2FSF
+//// -----------------------------------------------------------------------------
+///// Convert a System Frequency into a Frequency Scaling Frequency
+//// =============================================================================
+//PROTECTED HAL_SYS_FREQ_SCAL_FREQ_T hal_SysSF2FSF(HAL_SYS_FREQ_T freq);
+//
+//
+//
+//// =============================================================================
+//// hal_SysFSF2SF
+//// -----------------------------------------------------------------------------
+///// Convert a Frequency Scaling Frequency into a System Frequency
+//// =============================================================================
+//PROTECTED HAL_SYS_FREQ_T hal_SysFSF2SF(HAL_SYS_FREQ_SCAL_FREQ_T fsfFreq);
+//
+//
+//
+//// =============================================================================
+//// hal_SysSetupSystemClock
+//// -----------------------------------------------------------------------------
+///// Configure the initial settings of the system clock.
+///// This function is to be called only by hal_init.
+///// @param fastClockSetup Initial System Clock.
+//// =============================================================================
+//PROTECTED VOID hal_SysSetupSystemClock(HAL_SYS_FREQ_T fastClockSetup);
+//
+//
+//
+//// =============================================================================
+//// hal_SysXcpuSleep
+//// -----------------------------------------------------------------------------
+///// Put the XCPU to sleep
+///// @param wakeUpMask Set the WakeUp mask, a bitfield where a bit to '1'
+///// means that the corresponding IRQ can wake up the CPU.
+//// =============================================================================
+//INLINE VOID hal_SysXcpuSleep(VOID)
+//{
+//    hwp_sysIrq->Cpu_Sleep = SYS_IRQ_SLEEP;
+//    // flush the write buffer to ensure we sleep before exiting this function
+//    UINT32 clkSysDisable __attribute__((unused)) = hwp_sysIrq->Cpu_Sleep;
+//}
+//
+//// =============================================================================
+//// hal_SysEnablePLL
+//// -----------------------------------------------------------------------------
+///// Enable PLL
+//// =============================================================================
+//PROTECTED VOID hal_SysEnablePLL(VOID);
+//
+//// =============================================================================
+//// hal_SysDisablePLL
+//// -----------------------------------------------------------------------------
+///// Disable PLL and switch on low clock
+//// =============================================================================
+//PROTECTED VOID hal_SysDisablePLL(VOID);
+//
+//// =============================================================================
+//// hal_SysGetPLLLock
+//// -----------------------------------------------------------------------------
+///// Return PLL lock 
+///// @return PLL status
+/////         If \c TRUE, PLL locked.
+/////         If \c FALSE, PLL not locked.
+//// =============================================================================
+//PROTECTED BOOL hal_SysGetPLLLock(VOID);
+//
+//
+//#ifdef CHIP_IS_MODEM
+//// =============================================================================
+//// hal_SysApHostEnable
+//// -----------------------------------------------------------------------------
+///// Enable or disable usb host.
+///// This is useful to inform hal_SysProcessHostMonitor() that the AP Host functions
+///// must be called to process the host commands.
+///// @param enable \c TRUE to enable, \c FALSE to disable.
+//// =============================================================================
+//PROTECTED VOID hal_SysApHostEnable(BOOL enable);
+//
+//
+//// =============================================================================
+//// hal_SysEnableApClock
+//// -----------------------------------------------------------------------------
+///// Enable or disable AP clock.
+///// @param enable \c TRUE to enable, \c FALSE to disable.
+//// =============================================================================
+//PROTECTED VOID hal_SysEnableApClock(BOOL enable);
+//
+//
+//// =============================================================================
+//// hal_SysEnableApIrq
+//// -----------------------------------------------------------------------------
+///// Enable or disable AP irq.
+///// @param enable \c TRUE to enable, \c FALSE to disable.
+//// =============================================================================
+//PROTECTED VOID hal_SysEnableApIrq(BOOL enable);
+//
+//
+//// =============================================================================
+//// hal_SysApIrqActive
+//// -----------------------------------------------------------------------------
+///// Check AP irq status.
+///// @return TRUE if AP irq is active; FALSE otherwise
+//// =============================================================================
+//PROTECTED BOOL hal_SysApIrqActive(VOID);
+//
+//
+//#else // !CHIP_IS_MODEM
+//// =============================================================================
+//// hal_SysSetupClkUart
+//// -----------------------------------------------------------------------------
+///// Setup the uart clock
+///// Be careful not to use it with a uart2 which doesn't exist here (yet)
+///// or any improper parameter.
+///// @param Uart_id Id of the uart whose clock we want to setup
+///// @param divider Divider of the clock, from 2 to 1025
+//// =============================================================================
+//INLINE VOID hal_SysSetupClkUart(HAL_UART_ID_T uartId, UINT16 divider)
+//{
+//    hwp_sysCtrl->Cfg_Clk_Uart[uartId] = divider-2;
+//}
+//
+//
+//// =============================================================================
+//// hal_SysSetupClkPwm
+//// -----------------------------------------------------------------------------
+///// Setup the PWM clock
+///// The PWM clock is got by dividing the system clock    
+///// @param divider The divider used
+//// =============================================================================
+//INLINE VOID hal_SysSetupClkPwm(UINT8 divider)
+//{
+//    hwp_sysCtrl->Cfg_Clk_PWM = divider;
+//}
+//#endif // !CHIP_IS_MODEM
+//
+//
+//// =============================================================================
+//// hal_SysSetupSystemClock
+//// -----------------------------------------------------------------------------
+///// Configure the initial settings of the system clocks.
+///// This function is to be called only by hal_init.
+///// It also checks the validity of the public enum for HAL_SYS_FREQ_T and 
+///// the internal one HAL_SYS_FREQ_SCAL_USERS_T use for frequency scaling.
+///// @param fastClockSetup Initial System Clock.
+//// =============================================================================
+//PROTECTED VOID hal_SysSetupSystemClock(HAL_SYS_FREQ_T fastClockSetup);
+//
+//
+//
+//// =============================================================================
+//// hal_SysUpdateSystemFrequency
+//// -----------------------------------------------------------------------------
+///// Set the system frequency to the highest minimal frequency required 
+///// by the user of the system.
+//// =============================================================================
+//PROTECTED VOID hal_SysUpdateSystemFrequency();
+//
+//
+//// =============================================================================
+//// hal_SysUsbHostEnable
+//// -----------------------------------------------------------------------------
+///// Enable or disable usb host.
+///// This is useful to inform hal_SysProcessIdle() that the USB Host functions
+///// must be called to process the host commands.
+///// @param enable \c TRUE to enable, \c FALSE to disable.
+//// =============================================================================
+//PROTECTED VOID hal_SysUsbHostEnable(BOOL enable);
+
+
+#endif //  HAL_SYS_H
+
+
diff --git a/board/rda/common/include/rda_gic.h b/board/rda/common/include/rda_gic.h
new file mode 100644
index 0000000000..13c9230c05
--- /dev/null
+++ b/board/rda/common/include/rda_gic.h
@@ -0,0 +1,67 @@
+#ifndef __RDA_GIC_H
+#define __RDA_GIC_H
+
+#if defined(CONFIG_MACH_RDA8850E)
+#define RDA50E_GIC_BASE	0x20970000
+#define RDA_GICD_BASE	(RDA50E_GIC_BASE + 0x1000)
+#define RDA_GICC_BASE	(RDA50E_GIC_BASE + 0x2000)
+#elif defined(CONFIG_MACH_RDA8810H)
+#define RDA10H_GIC_BASE	0x20970000
+#define RDA_GICD_BASE	(RDA10H_GIC_BASE + 0x1000)
+#define RDA_GICC_BASE	(RDA10H_GIC_BASE + 0x2000)
+#else
+#error "unknown machine !"
+#endif
+
+#define VID_ARM	0x43B
+
+#define GIC_CPU_CTRL			0x00
+#define GIC_CPU_PRIMASK			0x04
+#define GIC_CPU_BINPOINT		0x08
+#define GIC_CPU_INTACK			0x0c
+#define GIC_CPU_EOI			0x10
+#define GIC_CPU_RUNNINGPRI		0x14
+#define GIC_CPU_HIGHPRI			0x18
+#define GIC_CPU_IID			0xFC
+
+#define GIC_DIST_CTRL			0x000
+#define GIC_DIST_CTR			0x004
+#define GIC_DIST_IID			0x008
+#define GIC_DIST_IGROUP			0x080
+#define GIC_DIST_ENABLE_SET		0x100
+#define GIC_DIST_ENABLE_CLEAR		0x180
+#define GIC_DIST_PENDING_SET		0x200
+#define GIC_DIST_PENDING_CLEAR		0x280
+#define GIC_DIST_ACTIVE_SET		0x300
+#define GIC_DIST_ACTIVE_CLEAR		0x380
+#define GIC_DIST_PRI			0x400
+#define GIC_DIST_TARGET			0x800
+#define GIC_DIST_CONFIG			0xc00
+#define GIC_DIST_SOFTINT		0xf00
+
+#define GICH_HCR			0x0
+#define GICH_VTR			0x4
+#define GICH_VMCR			0x8
+#define GICH_MISR			0x10
+#define GICH_EISR0 			0x20
+#define GICH_EISR1 			0x24
+#define GICH_ELRSR0 			0x30
+#define GICH_ELRSR1 			0x34
+#define GICH_APR			0xf0
+#define GICH_LR0			0x100
+
+#define GICH_HCR_EN			(1 << 0)
+#define GICH_HCR_UIE			(1 << 1)
+
+#define GICH_LR_VIRTUALID		(0x3ff << 0)
+#define GICH_LR_PHYSID_CPUID_SHIFT	(10)
+#define GICH_LR_PHYSID_CPUID		(7 << GICH_LR_PHYSID_CPUID_SHIFT)
+#define GICH_LR_STATE			(3 << 28)
+#define GICH_LR_PENDING_BIT		(1 << 28)
+#define GICH_LR_ACTIVE_BIT		(1 << 29)
+#define GICH_LR_EOI			(1 << 19)
+
+#define GICH_MISR_EOI			(1 << 0)
+#define GICH_MISR_U			(1 << 1)
+
+#endif
diff --git a/board/rda/common/include/rda_lcdc.h b/board/rda/common/include/rda_lcdc.h
new file mode 100644
index 0000000000..4da163de0b
--- /dev/null
+++ b/board/rda/common/include/rda_lcdc.h
@@ -0,0 +1,163 @@
+#ifndef __RDA_LCDC_H__
+#define __RDA_LCDC_H__
+
+#include <common.h>
+#include <asm/arch/cs_types.h>
+
+/*LCDC reg offset start*/
+#define LCDC_COMMAND			0x0
+#define LCDC_STATUS				0x04
+#define LCDC_EOF_IRQ			0x08
+#define LCDC_EOF_IRQ_MASK		0xC
+#define LCD_CTRL				0x10
+#define LCD_TIMING				0x14
+#define LCDC_MEM_ADDRESS		0x18
+#define LCD_STRIDE_OFFSET		0x1C
+#define LCDC_SINGLE_ACCESS		0x20
+#define LCDC_SPILCD_CONFIG		0x24
+#define LCDC_SPILCD_RD			0x28
+#define LCDC_DCT_SHIFT_UV_REG1	0x2C
+#define DPI_CONFIG				0x30
+#define DPI_FRAME0_ADDR			0x34
+#define DPI_FRAME0_CON			0x38
+#define DPI_FRAME1_ADRR			0x3C
+#define DPI_FRAME1_CON			0x40
+#define DPI_FRAME2_ADRR			0x44
+#define DPI_FRAME2_CON			0x48
+#define DPI_SIZE				0x4C
+#define DPI_FIFO_CTRL			0x50
+#define DPI_THROT				0x54
+#define DPI_POL					0x58
+#define DPI_TIME0				0x5C
+#define DPI_TIME1				0x60
+#define DPI_TIME2				0x64
+#define DPI_TIME3				0x68
+#define DPI_STATUS				0x6C
+#define LCDC_DITHER_CTRL		0x70
+#define LCDC_DITHER_MATRIX0_0	0x74
+#define LCDC_DITHER_MATRIX0_1	0x78
+#define LCDC_DITHER_MATRIX1		0x7C
+#define TECON					0x80
+#define TECON2					0x84
+#define DSI_REG_OFFSET			0x400
+
+/* rgb order */
+#define RGB_ORDER_RGB			(0<<3)
+#define RGB_ORDER_BGR			(1<<3)
+
+/* pixel format */
+#define RGB_PIX_FMT_RGB565		(0<<4)
+#define RGB_PIX_FMT_RGB888		(1<<4)
+#define RGB_PIX_FMT_XRGB888		(2<<4)
+#define RGB_PIX_FMT_RGBX888		(3<<4)
+
+#define MIPI_DSI_ENABLE			(1<<9)
+#define MIPI_DSI_DISABLE		(0<<9)
+
+#define MIPI_CMD_SEL_CMD		(1<<20)
+#define REG_PEND_REQ(n)			(((n)&0x1F)<<21)
+
+#define DPI_FRAME_LINE_STEP(n)	(((n)&0x1FFF)<<16)
+#define DPI_FRAME_VALID			(1<<0)
+
+//dpi size
+#define VERTICAL_PIX_NUM(n)		(((n)&0x7FF)<<16)
+#define HORIZONTAL_PIX_NUM(n)	(((n)&0x7FF)<<0)
+
+//dct_shift_uv_reg1
+#define DCT_SHIFT_UV_ENABLE		(1<<30)
+#define LCDC_RGB_WAIT			(1<<30)
+
+/*dpi_fifo_ctrl*/
+#define DPI_DATA_FIFO_LOWTHRES(n)	(((n)&0x3FF)<<16)
+#define DPI_DATA_FIFO_RST_AUTO		(1<<1)
+#define DPI_DATA_FIFO_RST			(1<<0)
+
+#define MIPI_DSI_LANE(n)		(((n)&0x3)<<0)
+
+//gd_eof_irq
+#define LCDC_EOF_CAUSE			(1 << 0)
+#define LCDC_VSYNC_RISE			(1 << 2)
+#define LCDC_VSYNC_FALL			(1 << 3)
+#define LCDC_DPI_OVERFLOW		(1 << 4)
+#define LCDC_DPI_FRAMEOVER		(1 << 5)
+#define LCDC_MIPI_INT			(1 << 6)
+#define LCDC_EOF_STATUS			(1 << 16)
+#define LCDC_IRQ_CLEAR_ALL		(~0)
+
+//gd_eof_irq_mask
+#define LCDC_EOF_MASK			(1<<0)
+#define LCDC_VSYNC_RISE_MASK	(1<<1)
+#define LCDC_VSYNC_FALL_MASK	(1<<2)
+#define LCDC_DPI_OVERFLOW_MASK	(1<<3)
+#define LCDC_DPI_FRAMEOVER_MAS	(1<<4)
+#define LCDC_MIPI_INT_MASK		(1<<5)
+#define LCDC_IRQ_MASK_ALL		(0x3f)
+
+/*dsi irq status*/
+#define DSI_TX_END_FLAG			(1 << 0)
+#define DSI_RX_END_FLAG			(1 << 1)
+
+/* lcd mode */
+#define LCD_DSI_MODE			(0x1)
+
+struct dsi_timing {
+	u32 off;
+	u32 value;
+};
+
+struct rda_dsi_phy_ctrl {
+	u32 pll[6];
+	struct dsi_timing video_timing[13];
+	struct dsi_timing cmd_timing[8];
+};
+
+struct mipi_panel_info {
+	u8 data_lane;
+	u8 mipi_mode;
+	u8 pixel_format;
+	u8 dsi_format;
+	u8 trans_mode;
+	u8 rgb_order;
+	bool bllp_enable;
+	u32 h_sync_active;
+	u32 h_back_porch;
+	u32 h_front_porch;
+	u32 v_sync_active;
+	u32 v_back_porch;
+	u32 v_front_porch;
+	u8 frame_rate;
+	u8 te_sel;
+	u32 dsi_pclk_rate;
+	const struct rda_dsi_phy_ctrl *dsi_phy_db;
+};
+
+struct lcd_panel_info {
+	u16 width;
+	u16 height;
+	u16 bpp;
+	struct mipi_panel_info mipi_pinfo;
+};
+
+#define LCDC_OUTL(addr, data) writel((data), (addr))
+#define LCDC_INL(addr) readl(addr)
+
+#define LCDC_OR_WITH_REG(addr, data)	\
+			do{ \
+				LCDC_OUTL(addr,data | LCDC_INL(addr));	\
+			}while(0);
+
+#define LCDC_AND_WITH_REG(addr, data)	\
+			do{ \
+				LCDC_OUTL(addr,data & LCDC_INL(addr));	\
+			}while(0);
+
+PUBLIC VOID rda_write_dsi_reg(u32 offset, u32 value);
+PUBLIC U32 rda_read_dsi_reg(u32 offset);
+PUBLIC VOID set_lcdc_for_cmd(u32 addr, int group_num);
+PUBLIC VOID set_lcdc_for_video(u32 addr, const struct lcd_panel_info *lcd);
+PUBLIC VOID rda_lcdc_set(const struct rda_dsi_phy_ctrl*dsi_phy_db);
+PUBLIC INT  rda_lcdc_irq_status(void);
+
+#endif /*__RDA_LCDC_H*/
+
diff --git a/board/rda/common/include/rda_md5.h b/board/rda/common/include/rda_md5.h
new file mode 100644
index 0000000000..e09c16a6e3
--- /dev/null
+++ b/board/rda/common/include/rda_md5.h
@@ -0,0 +1,34 @@
+/*
+ * This file was transplanted with slight modifications from Linux sources
+ * (fs/cifs/md5.h) into U-Boot by Bartlomiej Sieka <tur@semihalf.com>.
+ */
+
+#ifndef _MD5_H
+#define _MD5_H
+
+#include "compiler.h"
+
+struct MD5Context {
+	__u32 buf[4];
+	__u32 bits[2];
+	union {
+		unsigned char in[64];
+		__u32 in32[16];
+	};
+};
+
+/*
+ * Calculate and store in 'output' the MD5 digest of 'len' bytes at
+ * 'input'. 'output' must have enough space to hold 16 bytes.
+ */
+void md5 (unsigned char *input, int len, unsigned char output[16]);
+
+/*
+ * Calculate and store in 'output' the MD5 digest of 'len' bytes at 'input'.
+ * 'output' must have enough space to hold 16 bytes. If 'chunk' Trigger the
+ * watchdog every 'chunk_sz' bytes of input processed.
+ */
+void md5_wd (unsigned char *input, int len, unsigned char output[16],
+		unsigned int chunk_sz);
+
+#endif /* _MD5_H */
diff --git a/board/rda/common/include/rda_mipi_dsi.h b/board/rda/common/include/rda_mipi_dsi.h
new file mode 100644
index 0000000000..b84200bad6
--- /dev/null
+++ b/board/rda/common/include/rda_mipi_dsi.h
@@ -0,0 +1,60 @@
+#ifndef RDA_MIPI_DSI_H
+#define RDA_MIPI_DSI_H
+#include "rda_lcdc.h"
+
+struct rda_dsi_cmd{
+	int dtype;
+	int delay;
+	int dlen;
+	const char *payload;
+};
+
+enum mipi_mode{
+	DSI_VIDEO_MODE,
+	DSI_CMD_MODE,
+};
+
+enum dsi_tx_mode {
+	DSI_CMD,
+	DSI_PULSE,
+	DSI_EVENT,
+	DSI_BURST
+};
+
+enum dsi_cmd_mode {
+	CMD_LP_MODE,
+	CMD_HS_MODE
+};
+
+enum mipi_pixel_fmt {
+	DSI_FMT_RGB565 = 0,
+	DSI_FMT_RGB666,
+	DSI_FMT_RGB666L,
+	DSI_FMT_RGB888
+};
+
+#define DSI_HDR_SHORT_PKT	(0 << 5)	/*or 0x1*/
+#define DSI_HDR_LONG_PKT	(0x2 << 5)	/*or 0x3*/
+#define DSI_HDR_BTA			(1 << 0)
+#define DSI_HDR_HS			(1 << 1)
+
+#define DSI_HDR_VC(vc)		(((vc) & 0x03) << 14)
+#define DSI_HDR_DTYPE(dtype)(((dtype) & 0x03f) << 8)
+#define DSI_HDR_DATA2(data)	(((data) & 0x0ff) << 24)
+#define DSI_HDR_DATA1(data)	(((data) & 0x0ff) << 16)
+#define DSI_HDR_WC(wc)		(((wc) & 0x0ffff) << 16)
+
+/* dcs read/write */
+#define DTYPE_DCS_SWRITE	0x05	/* short write,with 0 parameter  */
+#define DTYPE_DCS_LWRITE	0x39	/* long write */
+
+PUBLIC VOID dsi_set_tx_mode(u8 mode);
+PUBLIC U8 dsi_get_tx_mode(void);
+PUBLIC VOID dsi_enable(bool on);
+PUBLIC VOID dsi_pll_on(bool enable);
+PUBLIC VOID dsi_op_mode(int mode);
+PUBLIC VOID dsi_swrite(u8 cmd);
+PUBLIC INT dsi_lwrite(const struct rda_dsi_cmd *cmds, int cmds_cnt);
+PUBLIC VOID dsi_config(const struct lcd_panel_info *lcd);
+
+#endif
diff --git a/board/rda/common/mipi_loop_test.c b/board/rda/common/mipi_loop_test.c
new file mode 100644
index 0000000000..21f8bc2543
--- /dev/null
+++ b/board/rda/common/mipi_loop_test.c
@@ -0,0 +1,310 @@
+#include <common.h>
+#include "asm/arch/cs_types.h"
+#include "hal_gpio.h"
+#include "rda_mipi_dsi.h"
+#include "rda_lcdc.h"
+#include "hal_camera.h"
+#include <asm/arch/reg_spi.h>
+#include <asm/arch/ispi.h>
+#include <asm/io.h>
+
+#define LDO_ACTIVE_SETTING1		(u32) 0x03
+#define LDO_ACTIVE_SETTING2		(u32) 0x04
+
+#define CONFIG_DRAM_START		0x80000000
+#define CONFIG_TEST_DRAM_ADDR  (CONFIG_DRAM_START + 0x2000000)
+
+#define CSI_BUFFER_SRC		0xa0000000
+#define CSI_BUFFER_DST		0xa1000000
+#define CSI_FRAME_BUFFER	0xa2000000
+
+#define AP_GPIO_A_MODE		0x11a0900c
+#define AP_GPIO_B_MODE		0x11a09010
+
+#define PIN_MUX_LCD		~(0x3FFF << 18)
+#define PIN_MUX_CAM		~(0x3FFF << 10)
+
+#define TEST_RESULT_ADDR	0x11C010F4
+
+static const struct rda_dsi_phy_ctrl pll_phy_260mhz = {
+	{0x2800, 0x0000, 0x10, 0xbc00, 0x20a, 0x20b},
+	{
+		{0x6C, 0x53}, {0x10C, 0x3}, {0x108,0x2}, {0x118, 0x4}, {0x11C, 0x0},
+		{0x120, 0xC}, {0x124, 0x2}, {0x128, 0x3}, {0x80, 0xE}, {0x84, 0xC},
+		{0x130, 0xC}, {0x150, 0x12}, {0x170, 0x87A},
+	},
+	{
+		{0x64, 0x3}, {0x134, 0x3}, {0x138, 0xB}, {0x14C, 0x2C}, {0x13C, 0x7},
+		{0x114, 0x40}, {0x170, 0x87A}, {0x140, 0xFF},
+	},
+};
+
+static const struct lcd_panel_info test_lcd = {
+		.width = 480,
+		.height = 800,
+		.bpp = 16,
+		.mipi_pinfo = {
+			.data_lane = 2,
+			.mipi_mode = DSI_VIDEO_MODE,
+			.pixel_format = RGB_PIX_FMT_RGB565,
+			.dsi_format = DSI_FMT_RGB565,
+			.rgb_order = RGB_ORDER_BGR,
+			.trans_mode = DSI_BURST,
+			.bllp_enable = TRUE,
+			.h_sync_active = 0x1c,
+			.h_back_porch = 0x7a,
+			.h_front_porch = 0x7b,
+			.v_sync_active = 0x8,
+			.v_back_porch = 0x5,
+			.v_front_porch = 0x6,
+			.frame_rate = 60,
+			.te_sel = TRUE,
+			.dsi_pclk_rate = 260,//260MHz
+			.dsi_phy_db = &pll_phy_260mhz,
+		}
+};
+
+/***************************************************
+	Synchronization Short Packet Data Type Codes
+	Data Type Description
+	0x00 Frame Start Code
+	0x01 Frame End Code
+	0x02 Line Start Code (Optional)
+	0x03 Line End Code (Optional)
+
+	Each image frame shall begin with a Frame Start (FS) Packet containing the Frame Start Code.
+	The FS Packet shall be followed by one or more long packets containing image data and zero or more short packets
+	containing synchronization codes.Each image frame shall end with a Frame End (FE) Packet containing the Frame End Code.
+
+	Frame Structure with Embedded Data at the Beginning and End of the Frame
+	YUV Image Data Types
+	Data Type Description
+	0x18 YUV420 8-bit
+	0x19 YUV420 10-bit
+	0x1A Legacy YUV420 8-bit
+	0x1B Reserved
+	0x1C YUV420 8-bit (Chroma Shifted Pixel Sampling)
+	0x1D YUV420 10-bit (Chroma Shifted Pixel Sampling)
+	0x1E YUV422 8-bit
+	0x1F YUV422 10-bit
+
+	RGB Image Data
+	defines the data type codes for RGB data formats described in this section.
+	RGB Image Data Types
+	Data Type Description
+	0x20 RGB444
+	0x21 RGB555
+	0x22 RGB565
+	0x23 RGB666
+	0x24 RGB888
+	0x25 Reserved
+	0x26 Reserved
+	0x27 Reserved
+*****************************************************/
+static void csi_send_frame(int len)
+{
+	U32 header = 0;
+
+	dsi_enable(FALSE);
+	dsi_op_mode(DSI_CMD);		  	//cmd mode
+	dsi_pll_on(TRUE);
+	rda_write_dsi_reg(0x40,0x2);
+	rda_write_dsi_reg(0x44,0x3);
+	rda_write_dsi_reg(0x180,0x02);		//Frame Start Code
+
+	header |= (len & 0xff) << 16;
+	header |= 0x1e << 8;
+	header |= DSI_HDR_LONG_PKT;
+	header |= DSI_HDR_HS;
+	rda_write_dsi_reg(0x184,header);	//hs cmd mode send
+	rda_write_dsi_reg(0x188,0x102); 	//Frame End Code
+	dsi_enable(TRUE);
+}
+
+static void dsi_hs_frame_init(void)
+{
+	int i;
+	unsigned char *frame = (unsigned char *)CSI_BUFFER_SRC;
+	unsigned char *data = (unsigned char *)CSI_FRAME_BUFFER;
+	for (i =0; i < 64; i += 4) {
+		*(data + i) = 0x11;
+		*(data + i + 1) = 0x22;
+		*(data + i + 2) = 0x33;
+		*(data + i + 3) = 0x44;
+	}
+	for (i = 0; i < 32; i++) {
+		frame = (unsigned char *)CSI_BUFFER_SRC + 8 * i;
+		*frame  = 0x11;
+		*(frame + 1) = 0x22;
+		*(frame + 2) = 0x33;
+		*(frame + 3) = 0x00;
+		*(frame + 4) = 0x44;
+		*(frame + 5) = 0x00;
+		*(frame + 6) = 0x00;
+		*(frame + 7) = 0x00;
+	}
+}
+
+static void camera_reg_config(void)
+{
+	u8 data_lane = 2;
+	HAL_CAMERA_CFG_T CamConfig = {0,};
+	HAL_CAMERA_IRQ_CAUSE_T mask = {0,0,0,0};
+	CamConfig.cam1PdnRemap.gpioId = HAL_GPIO_NONE;
+	CamConfig.camPdnRemap.gpioId = HAL_GPIO_NONE;
+	CamConfig.camRstRemap.gpioId = HAL_GPIO_NONE;
+	CamConfig.cam1RstRemap.gpioId = HAL_GPIO_NONE;
+
+	hal_SetCameraClkOut(0x101); 	// 0x11 = 13M	0x1 = 30M
+
+	CamConfig.rstActiveH = FALSE;
+	CamConfig.pdnActiveH = TRUE;
+	CamConfig.dropFrame = FALSE;
+	CamConfig.camClkDiv = 6;	// 156/x: 13M(x=12), 26M(x=6)
+	CamConfig.endianess = NO_SWAP;
+	CamConfig.csi_mode  =  TRUE;
+	CamConfig.num_d_term_en=21;
+	CamConfig.num_hs_settle=21;
+	CamConfig.num_c_term_en=55;
+	CamConfig.num_c_hs_settle=55;
+	CamConfig.csi_cs=0;		// 0 use csi1 . 1 use csi2
+	CamConfig.frame_line_number=1;
+
+	CamConfig.cropEnable = FALSE;
+
+	CamConfig.colRatio= 0;
+	CamConfig.rowRatio= 0;
+	CamConfig.reOrder = 4;
+
+	hal_CameraOpen(&CamConfig);
+	hal_CameraIrqSetMask(mask);
+	hal_CameraSetLane(data_lane);
+}
+
+static int receive_data(unsigned char * data)
+{
+	int data_len = 64;
+	int ret, times = 0;
+	HAL_CAMERA_IRQ_CAUSE_T cause = {0};
+
+	HAL_CAMERA_IRQ_CAUSE_T mask = {1,1,1,1};
+	hal_CameraStartXfer(data_len, (UINT8*)data);
+	hal_CameraIrqSetMask(mask);
+	hal_CameraControllerEnable(TRUE);
+
+	csi_send_frame(data_len);
+	mdelay(50);
+	ret = rda_lcdc_irq_status();
+	if (ret)
+		return 1;
+
+	while(times < 100) {
+		hal_getCameraStatus(&cause);
+
+		if (cause.fstart == 1)
+			printf("frame: fstart\n");
+		if (cause.fend == 1) {
+			hal_CameraControllerEnable(FALSE);
+			printf("frame:	fend\n");
+			if (hal_CameraStopXfer(FALSE) == XFER_SUCCESS)
+				printf("cam:AXI ok\n");
+		}
+		if (cause.overflow == 1)
+			printf("camera_cause .overflow\n");
+		if (cause.dma == 1)
+			printf("frame: dma donn\n");
+		if (cause.fend == 1)
+			break;
+		udelay(100);
+		times++;
+	}
+	if (times == 100)
+		return 2;
+	else
+		return 0;
+}
+
+static void set_pmu(void)
+{
+	u32 value = 0;
+
+	ispi_open(1);
+	value = ispi_reg_read(LDO_ACTIVE_SETTING1);
+	value |= 0x3 << 7;
+	ispi_reg_write(LDO_ACTIVE_SETTING1, value);		// v_cam_act, v_lcd_act
+
+	value = ispi_reg_read(LDO_ACTIVE_SETTING2);
+	value |= 0x3 << 9;
+	ispi_reg_write(LDO_ACTIVE_SETTING2, value);		//vcam=1.8v, vlcd=1.8v
+	ispi_open(0);
+}
+
+static void set_pinmux(void)
+{
+	unsigned long temp;
+
+	/* pinmux for lcd */
+	temp = readl(AP_GPIO_A_MODE);
+	temp &= PIN_MUX_LCD;
+	writel(temp, AP_GPIO_A_MODE);
+	/* pinmux for cam */
+	temp = readl(AP_GPIO_B_MODE);
+	temp &= PIN_MUX_CAM;
+	writel(temp, AP_GPIO_B_MODE);
+}
+
+int test_dsi_csi_loop(int times)
+{
+	int test_times = 1;
+	int ret;
+
+	set_pmu();
+	set_pinmux();
+	dsi_hs_frame_init();
+
+	while(test_times <= times) {
+		printf("\n%s: times %d / %d ...\n", __func__, test_times, times);
+		memset((char *)CSI_BUFFER_DST, 0, 100);
+		camera_reg_config();
+		rda_lcdc_set(test_lcd.mipi_pinfo.dsi_phy_db);
+		dsi_config(&test_lcd);
+		set_lcdc_for_cmd(CSI_BUFFER_SRC, 16);
+		ret = receive_data((unsigned char *)CSI_BUFFER_DST);
+
+		if (ret) {
+			printf("mipi_loop failed, ");
+			writel(0xdeaddead, TEST_RESULT_ADDR);
+			if (ret == 1) {
+				printf("dsi failed\n");
+
+				return 1;
+			} else if (ret == 2) {
+				printf("csi failed\n");
+
+				return 1;
+			}
+		}
+
+		// if ret == 0, dsi and csi both correct, loop should be successful
+		if(memcmp((char*)CSI_BUFFER_DST, (char*)CSI_FRAME_BUFFER, 64)) {
+			printf("mipi_loop failed, unknown reason\n");
+			writel(0xdeaddead, TEST_RESULT_ADDR);	//unknown reason
+
+			return 1;
+		} else {
+			printf("loop success\n");
+			writel(0x55aaaa55, TEST_RESULT_ADDR);	//success
+		}
+
+		printf("test done\n\n");
+		/*
+		char  *p= (char *)CSI_BUFFER_DST;
+		for (i = 0; i < 64; i++) {
+			printf("%x\n", *p++);
+		}*/
+		test_times++;
+	}
+
+	return 0;
+}
+
diff --git a/board/rda/common/misc.c b/board/rda/common/misc.c
new file mode 100644
index 0000000000..3497db60ba
--- /dev/null
+++ b/board/rda/common/misc.c
@@ -0,0 +1,19 @@
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = (_TGT_AP_OS_MEM_SIZE) << 20;
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
diff --git a/board/rda/common/rda_lcdc.c b/board/rda/common/rda_lcdc.c
new file mode 100644
index 0000000000..2ecbe194bd
--- /dev/null
+++ b/board/rda/common/rda_lcdc.c
@@ -0,0 +1,141 @@
+#include <common.h>
+#include <asm/arch/cs_types.h>
+#include <asm/arch/rda_iomap.h>
+#include "rda_lcdc.h"
+#include "rda_mipi_dsi.h"
+#include <asm/arch/reg_spi.h>
+#include <asm/arch/ispi.h>
+#include <asm/io.h>
+
+#define ALT_MUX_SELECT 0x11a09018
+
+u32 rda_read_dsi_reg(u32 offset)
+{
+	u32 value;
+
+	value = LCDC_INL(RDA_LCDC_BASE + DSI_REG_OFFSET + offset);
+	return value;
+}
+
+void rda_write_dsi_reg(u32 offset, u32 value)
+{
+	LCDC_OUTL(RDA_LCDC_BASE + DSI_REG_OFFSET + offset,value);
+}
+
+void reset_lcdc_fifo(void)
+{
+	LCDC_AND_WITH_REG(RDA_LCDC_BASE + DPI_FIFO_CTRL, ~DPI_DATA_FIFO_RST_AUTO);
+	LCDC_OR_WITH_REG(RDA_LCDC_BASE + DPI_FIFO_CTRL, DPI_DATA_FIFO_RST);
+	LCDC_AND_WITH_REG(RDA_LCDC_BASE + DPI_FIFO_CTRL, ~DPI_DATA_FIFO_RST);
+}
+
+static void rda_dsi_irq_clear(void)
+{
+    u32 reg;
+    reg = rda_read_dsi_reg(0x48);
+    reg |= 0x1 << 2;
+    rda_write_dsi_reg(0x48,0x1 << 2);
+    rda_write_dsi_reg(0x48,reg & ~(1 << 2));
+}
+
+void set_lcdc_for_cmd(u32 addr, int group_num)
+{
+	/* fifo reset */
+	reset_lcdc_fifo();
+	dsi_pll_on(TRUE);
+
+	LCDC_OUTL(RDA_LCDC_BASE + LCDC_EOF_IRQ_MASK, LCDC_MIPI_INT_MASK);
+	LCDC_OUTL(RDA_LCDC_BASE + LCDC_EOF_IRQ, LCDC_IRQ_CLEAR_ALL);
+	LCDC_OUTL(RDA_LCDC_BASE + DPI_FRAME0_ADDR, addr);
+	LCDC_OUTL(RDA_LCDC_BASE + DPI_FRAME0_CON, DPI_FRAME_LINE_STEP(group_num * 8) | DPI_FRAME_VALID);
+	LCDC_OUTL(RDA_LCDC_BASE + DPI_SIZE, VERTICAL_PIX_NUM(1) | HORIZONTAL_PIX_NUM(group_num * 2));
+	LCDC_OUTL(RDA_LCDC_BASE + LCDC_DCT_SHIFT_UV_REG1, LCDC_RGB_WAIT | 0x143);
+	LCDC_OUTL(RDA_LCDC_BASE + DPI_CONFIG, MIPI_CMD_SEL_CMD | MIPI_DSI_ENABLE | RGB_PIX_FMT_XRGB888);
+}
+
+void set_lcdc_for_video(u32 addr, const struct lcd_panel_info *lcd)
+{
+	u32 dsi_bpp;
+
+	reset_lcdc_fifo();
+	dsi_enable(FALSE);
+	rda_write_dsi_reg(0x144, 0x14);
+	dsi_pll_on(TRUE);
+	LCDC_OUTL(RDA_LCDC_BASE + DPI_FRAME0_ADDR, addr);
+	LCDC_OUTL(RDA_LCDC_BASE + DPI_FRAME0_CON, DPI_FRAME_LINE_STEP(lcd->width \
+		* (lcd->bpp >> 3)) | DPI_FRAME_VALID);
+	LCDC_OUTL(RDA_LCDC_BASE + DPI_SIZE, VERTICAL_PIX_NUM(lcd->height)
+		| HORIZONTAL_PIX_NUM(lcd->width));
+	LCDC_OUTL(RDA_LCDC_BASE + LCDC_DCT_SHIFT_UV_REG1, LCDC_RGB_WAIT | 0x143);
+	LCDC_OUTL(RDA_LCDC_BASE + DPI_CONFIG, MIPI_DSI_ENABLE | lcd->mipi_pinfo.pixel_format \
+		| RGB_ORDER_BGR | REG_PEND_REQ(16));
+	if (lcd->mipi_pinfo.pixel_format == RGB_PIX_FMT_RGB565)
+		LCDC_OUTL(RDA_LCDC_BASE + LCDC_DCT_SHIFT_UV_REG1, 0x143);
+
+	LCDC_OUTL(RDA_LCDC_BASE + DPI_FIFO_CTRL, DPI_DATA_FIFO_RST_AUTO);
+	rda_write_dsi_reg(0x8,lcd->mipi_pinfo.data_lane >> 1);
+
+	/*rgb num, width bytes	+ header + crc*/
+	dsi_bpp = lcd->bpp != 32 ? lcd->bpp : 24;
+	rda_write_dsi_reg(0x2c,(lcd->width * (dsi_bpp >> 3)+ 6) >> (lcd->mipi_pinfo.data_lane >> 1));
+	/*mipi tx mode*/
+	dsi_op_mode(DSI_BURST);
+	dsi_enable(TRUE);
+
+}
+
+static void set_dsi_ap_pll(const struct rda_dsi_phy_ctrl *pll_phy)
+{
+	ispi_open(0);
+	dsi_pll_on(TRUE);
+
+	ispi_reg_write(0xA5, pll_phy->pll[0]);
+	ispi_reg_write(0xA6, pll_phy->pll[1]);
+	ispi_reg_write(0xA7, pll_phy->pll[2]);
+	ispi_reg_write(0xA3, pll_phy->pll[3]);
+	ispi_reg_write(0xA2, pll_phy->pll[4]);
+	udelay(100);
+	ispi_reg_write(0xA2, pll_phy->pll[5]);
+}
+
+void rda_lcdc_set(const struct rda_dsi_phy_ctrl *dsi_phy_db)
+{
+	unsigned long temp;
+
+	LCDC_OUTL(RDA_SYSCTRL_BASE + 0x34, 0x10);
+	LCDC_OUTL(RDA_SYSCTRL_BASE + 0x38, 0x10);
+	temp = readl(ALT_MUX_SELECT);
+	temp |= LCD_DSI_MODE;
+	writel(temp, ALT_MUX_SELECT);
+	LCDC_OUTL(RDA_LCDC_BASE + DPI_FIFO_CTRL, DPI_DATA_FIFO_RST_AUTO);
+	set_dsi_ap_pll(dsi_phy_db);
+	LCDC_OUTL(RDA_LCDC_BASE + LCDC_EOF_IRQ_MASK, LCDC_MIPI_INT_MASK);
+	LCDC_OUTL(RDA_LCDC_BASE + LCDC_EOF_IRQ, LCDC_IRQ_CLEAR_ALL);
+}
+
+int rda_lcdc_irq_status(void)
+{
+	u8 time_out = 0;
+	u32 status;
+	do {
+		status = LCDC_INL(RDA_LCDC_BASE + LCDC_EOF_IRQ);
+		printf("irq status: %x\n",status);
+
+		if (status & LCDC_DPI_FRAMEOVER) {
+			printf("irq: LCDC_DPI_FRAMEOVER\n");
+			LCDC_OUTL(RDA_LCDC_BASE + LCDC_EOF_IRQ, LCDC_IRQ_CLEAR_ALL);
+		}
+		if (status & LCDC_MIPI_INT) {
+			status = rda_read_dsi_reg(0x90);
+			printf("irq: LCDC_MIPI_INT\r\n");
+			if(status & DSI_TX_END_FLAG || status & DSI_RX_END_FLAG){
+				rda_dsi_irq_clear();
+				LCDC_OUTL(RDA_LCDC_BASE + LCDC_EOF_IRQ, LCDC_IRQ_CLEAR_ALL);
+				return 0;
+			}
+		}
+		udelay(100);
+	} while (time_out++ < 10);
+	return -1;
+}
+
diff --git a/board/rda/common/rda_md5.c b/board/rda/common/rda_md5.c
new file mode 100644
index 0000000000..1cba0e4221
--- /dev/null
+++ b/board/rda/common/rda_md5.c
@@ -0,0 +1,314 @@
+/*
+ * This file was transplanted with slight modifications from Linux sources
+ * (fs/cifs/md5.c) into U-Boot by Bartlomiej Sieka <tur@semihalf.com>.
+ */
+
+/*
+ * This code implements the MD5 message-digest algorithm.
+ * The algorithm is due to Ron Rivest.  This code was
+ * written by Colin Plumb in 1993, no copyright is claimed.
+ * This code is in the public domain; do with it what you wish.
+ *
+ * Equivalent code is available from RSA Data Security, Inc.
+ * This code has been tested against that, and is equivalent,
+ * except that you don't need to include two pages of legalese
+ * with every copy.
+ *
+ * To compute the message digest of a chunk of bytes, declare an
+ * MD5Context structure, pass it to MD5Init, call MD5Update as
+ * needed on buffers full of bytes, and then call MD5Final, which
+ * will fill a supplied 16-byte array with the digest.
+ */
+
+/* This code slightly modified to fit into Samba by
+   abartlet@samba.org Jun 2001
+   and to fit the cifs vfs by
+   Steve French sfrench@us.ibm.com */
+
+#include "compiler.h"
+
+#ifndef USE_HOSTCC
+#include <common.h>
+#include <watchdog.h>
+#endif /* USE_HOSTCC */
+#include "rda_md5.h"
+
+static void
+MD5Transform(__u32 buf[4], __u32 const in[16]);
+
+/*
+ * Note: this code is harmless on little-endian machines.
+ */
+static void
+byteReverse(unsigned char *buf, unsigned longs)
+{
+	__u32 t;
+	do {
+		t = (__u32) ((unsigned) buf[3] << 8 | buf[2]) << 16 |
+		    ((unsigned) buf[1] << 8 | buf[0]);
+		*(__u32 *) buf = t;
+		buf += 4;
+	} while (--longs);
+}
+
+/*
+ * Start MD5 accumulation.  Set bit count to 0 and buffer to mysterious
+ * initialization constants.
+ */
+static void
+MD5Init(struct MD5Context *ctx)
+{
+	ctx->buf[0] = 0x67452301;
+	ctx->buf[1] = 0xefcdab89;
+	ctx->buf[2] = 0x98badcfe;
+	ctx->buf[3] = 0x10325476;
+
+	ctx->bits[0] = 0;
+	ctx->bits[1] = 0;
+}
+
+/*
+ * Update context to reflect the concatenation of another buffer full
+ * of bytes.
+ */
+static void
+MD5Update(struct MD5Context *ctx, unsigned char const *buf, unsigned len)
+{
+	register __u32 t;
+
+	/* Update bitcount */
+
+	t = ctx->bits[0];
+	if ((ctx->bits[0] = t + ((__u32) len << 3)) < t)
+		ctx->bits[1]++;	/* Carry from low to high */
+	ctx->bits[1] += len >> 29;
+
+	t = (t >> 3) & 0x3f;	/* Bytes already in shsInfo->data */
+
+	/* Handle any leading odd-sized chunks */
+
+	if (t) {
+		unsigned char *p = (unsigned char *) ctx->in + t;
+
+		t = 64 - t;
+		if (len < t) {
+			memmove(p, buf, len);
+			return;
+		}
+		memmove(p, buf, t);
+		byteReverse(ctx->in, 16);
+		MD5Transform(ctx->buf, (__u32 *) ctx->in);
+		buf += t;
+		len -= t;
+	}
+	/* Process data in 64-byte chunks */
+
+	while (len >= 64) {
+		memmove(ctx->in, buf, 64);
+		byteReverse(ctx->in, 16);
+		MD5Transform(ctx->buf, (__u32 *) ctx->in);
+		buf += 64;
+		len -= 64;
+	}
+
+	/* Handle any remaining bytes of data. */
+
+	memmove(ctx->in, buf, len);
+}
+
+/*
+ * Final wrapup - pad to 64-byte boundary with the bit pattern
+ * 1 0* (64-bit count of bits processed, MSB-first)
+ */
+static void
+MD5Final(unsigned char digest[16], struct MD5Context *ctx)
+{
+	unsigned int count;
+	unsigned char *p;
+
+	/* Compute number of bytes mod 64 */
+	count = (ctx->bits[0] >> 3) & 0x3F;
+
+	/* Set the first char of padding to 0x80.  This is safe since there is
+	   always at least one byte free */
+	p = ctx->in + count;
+	*p++ = 0x80;
+
+	/* Bytes of padding needed to make 64 bytes */
+	count = 64 - 1 - count;
+
+	/* Pad out to 56 mod 64 */
+	if (count < 8) {
+		/* Two lots of padding:  Pad the first block to 64 bytes */
+		memset(p, 0, count);
+		byteReverse(ctx->in, 16);
+		MD5Transform(ctx->buf, (__u32 *) ctx->in);
+
+		/* Now fill the next block with 56 bytes */
+		memset(ctx->in, 0, 56);
+	} else {
+		/* Pad block to 56 bytes */
+		memset(p, 0, count - 8);
+	}
+	byteReverse(ctx->in, 14);
+
+	/* Append length in bits and transform */
+	ctx->in32[14] = ctx->bits[0];
+	ctx->in32[15] = ctx->bits[1];
+
+	MD5Transform(ctx->buf, (__u32 *) ctx->in);
+	byteReverse((unsigned char *) ctx->buf, 4);
+	memmove(digest, ctx->buf, 16);
+	memset(ctx, 0, sizeof(*ctx));	/* In case it's sensitive */
+}
+
+/* The four core functions - F1 is optimized somewhat */
+
+/* #define F1(x, y, z) (x & y | ~x & z) */
+#define F1(x, y, z) (z ^ (x & (y ^ z)))
+#define F2(x, y, z) F1(z, x, y)
+#define F3(x, y, z) (x ^ y ^ z)
+#define F4(x, y, z) (y ^ (x | ~z))
+
+/* This is the central step in the MD5 algorithm. */
+#define MD5STEP(f, w, x, y, z, data, s) \
+	( w += f(x, y, z) + data,  w = w<<s | w>>(32-s),  w += x )
+
+/*
+ * The core of the MD5 algorithm, this alters an existing MD5 hash to
+ * reflect the addition of 16 longwords of new data.  MD5Update blocks
+ * the data and converts bytes into longwords for this routine.
+ */
+static void
+MD5Transform(__u32 buf[4], __u32 const in[16])
+{
+	register __u32 a, b, c, d;
+
+	a = buf[0];
+	b = buf[1];
+	c = buf[2];
+	d = buf[3];
+
+	MD5STEP(F1, a, b, c, d, in[0] + 0xd76aa478, 7);
+	MD5STEP(F1, d, a, b, c, in[1] + 0xe8c7b756, 12);
+	MD5STEP(F1, c, d, a, b, in[2] + 0x242070db, 17);
+	MD5STEP(F1, b, c, d, a, in[3] + 0xc1bdceee, 22);
+	MD5STEP(F1, a, b, c, d, in[4] + 0xf57c0faf, 7);
+	MD5STEP(F1, d, a, b, c, in[5] + 0x4787c62a, 12);
+	MD5STEP(F1, c, d, a, b, in[6] + 0xa8304613, 17);
+	MD5STEP(F1, b, c, d, a, in[7] + 0xfd469501, 22);
+	MD5STEP(F1, a, b, c, d, in[8] + 0x698098d8, 7);
+	MD5STEP(F1, d, a, b, c, in[9] + 0x8b44f7af, 12);
+	MD5STEP(F1, c, d, a, b, in[10] + 0xffff5bb1, 17);
+	MD5STEP(F1, b, c, d, a, in[11] + 0x895cd7be, 22);
+	MD5STEP(F1, a, b, c, d, in[12] + 0x6b901122, 7);
+	MD5STEP(F1, d, a, b, c, in[13] + 0xfd987193, 12);
+	MD5STEP(F1, c, d, a, b, in[14] + 0xa679438e, 17);
+	MD5STEP(F1, b, c, d, a, in[15] + 0x49b40821, 22);
+
+	MD5STEP(F2, a, b, c, d, in[1] + 0xf61e2562, 5);
+	MD5STEP(F2, d, a, b, c, in[6] + 0xc040b340, 9);
+	MD5STEP(F2, c, d, a, b, in[11] + 0x265e5a51, 14);
+	MD5STEP(F2, b, c, d, a, in[0] + 0xe9b6c7aa, 20);
+	MD5STEP(F2, a, b, c, d, in[5] + 0xd62f105d, 5);
+	MD5STEP(F2, d, a, b, c, in[10] + 0x02441453, 9);
+	MD5STEP(F2, c, d, a, b, in[15] + 0xd8a1e681, 14);
+	MD5STEP(F2, b, c, d, a, in[4] + 0xe7d3fbc8, 20);
+	MD5STEP(F2, a, b, c, d, in[9] + 0x21e1cde6, 5);
+	MD5STEP(F2, d, a, b, c, in[14] + 0xc33707d6, 9);
+	MD5STEP(F2, c, d, a, b, in[3] + 0xf4d50d87, 14);
+	MD5STEP(F2, b, c, d, a, in[8] + 0x455a14ed, 20);
+	MD5STEP(F2, a, b, c, d, in[13] + 0xa9e3e905, 5);
+	MD5STEP(F2, d, a, b, c, in[2] + 0xfcefa3f8, 9);
+	MD5STEP(F2, c, d, a, b, in[7] + 0x676f02d9, 14);
+	MD5STEP(F2, b, c, d, a, in[12] + 0x8d2a4c8a, 20);
+
+	MD5STEP(F3, a, b, c, d, in[5] + 0xfffa3942, 4);
+	MD5STEP(F3, d, a, b, c, in[8] + 0x8771f681, 11);
+	MD5STEP(F3, c, d, a, b, in[11] + 0x6d9d6122, 16);
+	MD5STEP(F3, b, c, d, a, in[14] + 0xfde5380c, 23);
+	MD5STEP(F3, a, b, c, d, in[1] + 0xa4beea44, 4);
+	MD5STEP(F3, d, a, b, c, in[4] + 0x4bdecfa9, 11);
+	MD5STEP(F3, c, d, a, b, in[7] + 0xf6bb4b60, 16);
+	MD5STEP(F3, b, c, d, a, in[10] + 0xbebfbc70, 23);
+	MD5STEP(F3, a, b, c, d, in[13] + 0x289b7ec6, 4);
+	MD5STEP(F3, d, a, b, c, in[0] + 0xeaa127fa, 11);
+	MD5STEP(F3, c, d, a, b, in[3] + 0xd4ef3085, 16);
+	MD5STEP(F3, b, c, d, a, in[6] + 0x04881d05, 23);
+	MD5STEP(F3, a, b, c, d, in[9] + 0xd9d4d039, 4);
+	MD5STEP(F3, d, a, b, c, in[12] + 0xe6db99e5, 11);
+	MD5STEP(F3, c, d, a, b, in[15] + 0x1fa27cf8, 16);
+	MD5STEP(F3, b, c, d, a, in[2] + 0xc4ac5665, 23);
+
+	MD5STEP(F4, a, b, c, d, in[0] + 0xf4292244, 6);
+	MD5STEP(F4, d, a, b, c, in[7] + 0x432aff97, 10);
+	MD5STEP(F4, c, d, a, b, in[14] + 0xab9423a7, 15);
+	MD5STEP(F4, b, c, d, a, in[5] + 0xfc93a039, 21);
+	MD5STEP(F4, a, b, c, d, in[12] + 0x655b59c3, 6);
+	MD5STEP(F4, d, a, b, c, in[3] + 0x8f0ccc92, 10);
+	MD5STEP(F4, c, d, a, b, in[10] + 0xffeff47d, 15);
+	MD5STEP(F4, b, c, d, a, in[1] + 0x85845dd1, 21);
+	MD5STEP(F4, a, b, c, d, in[8] + 0x6fa87e4f, 6);
+	MD5STEP(F4, d, a, b, c, in[15] + 0xfe2ce6e0, 10);
+	MD5STEP(F4, c, d, a, b, in[6] + 0xa3014314, 15);
+	MD5STEP(F4, b, c, d, a, in[13] + 0x4e0811a1, 21);
+	MD5STEP(F4, a, b, c, d, in[4] + 0xf7537e82, 6);
+	MD5STEP(F4, d, a, b, c, in[11] + 0xbd3af235, 10);
+	MD5STEP(F4, c, d, a, b, in[2] + 0x2ad7d2bb, 15);
+	MD5STEP(F4, b, c, d, a, in[9] + 0xeb86d391, 21);
+
+	buf[0] += a;
+	buf[1] += b;
+	buf[2] += c;
+	buf[3] += d;
+}
+
+/*
+ * Calculate and store in 'output' the MD5 digest of 'len' bytes at
+ * 'input'. 'output' must have enough space to hold 16 bytes.
+ */
+void
+md5 (unsigned char *input, int len, unsigned char output[16])
+{
+	struct MD5Context context;
+
+	MD5Init(&context);
+	MD5Update(&context, input, len);
+	MD5Final(output, &context);
+}
+
+
+/*
+ * Calculate and store in 'output' the MD5 digest of 'len' bytes at 'input'.
+ * 'output' must have enough space to hold 16 bytes. If 'chunk' Trigger the
+ * watchdog every 'chunk_sz' bytes of input processed.
+ */
+void
+md5_wd (unsigned char *input, int len, unsigned char output[16],
+	unsigned int chunk_sz)
+{
+	struct MD5Context context;
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+	unsigned char *end, *curr;
+	int chunk;
+#endif
+
+	MD5Init(&context);
+
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+	curr = input;
+	end = input + len;
+	while (curr < end) {
+		chunk = end - curr;
+		if (chunk > chunk_sz)
+			chunk = chunk_sz;
+		MD5Update(&context, curr, chunk);
+		curr += chunk;
+		WATCHDOG_RESET ();
+	}
+#else
+	MD5Update(&context, input, len);
+#endif
+
+	MD5Final(output, &context);
+}
diff --git a/board/rda/common/rda_mipi_dsi.c b/board/rda/common/rda_mipi_dsi.c
new file mode 100644
index 0000000000..e764b91e56
--- /dev/null
+++ b/board/rda/common/rda_mipi_dsi.c
@@ -0,0 +1,283 @@
+#include <common.h>
+#include <asm/arch/cs_types.h>
+#include "rda_lcdc.h"
+#include "rda_mipi_dsi.h"
+
+#define COMMANDS_ADDR 0x85000008
+#define CMD_QUEUE_BASE 0x180
+
+static u8 cmd_tx_mode = CMD_HS_MODE;
+
+void dsi_set_tx_mode(u8 mode)
+{
+	cmd_tx_mode = mode;
+}
+
+u8 dsi_get_tx_mode(void)
+{
+	return cmd_tx_mode;
+}
+
+static void dsi_dump_cmds(char *buf, int group_num)
+{
+	int i;
+	U64 *data = (U64 *)buf;
+
+	for(i = 0; i < group_num; i++)
+		printf("%16llx\n", *data++);
+}
+
+static int dsi_get_cmds_num(const struct rda_dsi_cmd *cmds, int cmds_cnt)
+{
+	int i,j,cmds_num = 0;
+
+	const struct rda_dsi_cmd *cmds_ptr = cmds;
+
+	for (i = 0; i < cmds_cnt; i++) {
+		for (j = 0; j < cmds_ptr->dlen; j++)
+			cmds_num++;
+		cmds_ptr++;
+	}
+	return cmds_num;
+}
+
+void dsi_enable(bool on)
+{
+	rda_write_dsi_reg(0x04, on ? 0x1 : 0x0);
+}
+
+void dsi_op_mode(int mode)
+{
+	rda_write_dsi_reg(0x14, mode);
+}
+
+void dsi_cmd_queue_init(int cmd_cnt)
+{
+	rda_write_dsi_reg(0x40, cmd_cnt - 1); 	// dsi cmds num,actualy cmd - 1
+	rda_write_dsi_reg(0x44, 0x03);			// dsi cmd queue enable
+}
+
+/****************************************************************
+***************** COMMAND DATA FORMAT IN DDR ********************
+*
+* LP MODE:	0x| xx | xx |xx|xx|xx|xx|xx|xx| first command useless
+*			0x|cmd0|cmd0|00|00|00|00|00|00|
+*			0x|cmd1|cmd1|00|00|00|00|00|00|
+*	   ...
+*
+* HS MODE:	0x|cmd0|cmd1|cmd2|00|cmd3|00|00|00|
+*			0x|cmd4|cmd5|cmd6|00|cmd7|00|00|00|
+*	   ...
+*
+****************************************************************/
+
+static void dsi_cmds_into_ddr(const struct rda_dsi_cmd *cmd, char **buf)
+{
+	int i,j;
+	u8 pd;
+	char *buf_ptr = *buf;
+	static int index = 0;
+	const char *payload;
+	payload = cmd->payload;
+	if (cmd_tx_mode == CMD_LP_MODE) {
+		for (i = 0; i < cmd->dlen; i++) {
+			pd = *payload++;
+			*buf_ptr++ = pd;
+			*buf_ptr++ = pd;
+			printf("cmd	%8x\n", pd);
+			for (j = 0; j < 6; j++)
+				*buf_ptr++ = 0x00;
+		}
+	} else {
+		j = 0;
+		start:
+			while (index < 3) {
+				if (j < cmd->dlen) {
+					*buf_ptr++ = *payload++;
+					index++;
+					j++;
+				} else {
+					*buf = buf_ptr;
+					return;
+				}
+			}
+			if (index == 3) {
+				*buf_ptr++ = 0;
+				index++;
+			}
+			if (index == 4) {
+				if (j < cmd->dlen) {
+					*buf_ptr++ = *payload++;
+					index++;
+					j++;
+				} else {
+					*buf = buf_ptr;
+					return;
+				}
+			}
+			while (index < 8) {
+				*buf_ptr++ = 0;
+				index++;
+			}
+			index = 0;
+			if (j < cmd->dlen)
+				goto start;
+	}
+	*buf = buf_ptr;
+}
+
+
+void dsi_pll_on(bool enable)
+{
+	if (enable)
+		rda_write_dsi_reg(0x00, 0x3);
+	else
+		rda_write_dsi_reg(0x00, 0x0);
+}
+
+static void dsi_set_timing(const struct rda_dsi_phy_ctrl *dsi_phy_db)
+{
+	int i;
+	u32 off,value;
+
+	/* cmd mode */
+	for (i = 0; i < ARRAY_SIZE(dsi_phy_db->cmd_timing); i++) {
+		off = dsi_phy_db->cmd_timing[i].off;
+		value = dsi_phy_db->cmd_timing[i].value;
+		rda_write_dsi_reg(off,value);
+	}
+	/* video mode */
+	for (i = 0; i < ARRAY_SIZE(dsi_phy_db->video_timing); i++) {
+		off = dsi_phy_db->video_timing[i].off;
+		value = dsi_phy_db->video_timing[i].value;
+		rda_write_dsi_reg(off, value);
+	}
+}
+
+static void dsi_set_parameter(const struct lcd_panel_info *lcd)
+{
+	u32 data_lane;
+	u32 dsi_bpp;
+	data_lane = (cmd_tx_mode == CMD_HS_MODE) ? lcd->mipi_pinfo.data_lane >> 1 : 0;
+	rda_write_dsi_reg(0x8,data_lane);
+	/*pixel num*/
+	rda_write_dsi_reg(0xc,lcd->width);
+	/*pixel type*/
+	rda_write_dsi_reg(0x10,lcd->mipi_pinfo.dsi_format);
+
+	/*vc,bllp enable*/
+	if(lcd->mipi_pinfo.bllp_enable)
+		rda_write_dsi_reg(0x18,0x1 << 2);
+
+	rda_write_dsi_reg(0x20,lcd->mipi_pinfo.h_sync_active);
+	rda_write_dsi_reg(0x24,lcd->mipi_pinfo.h_back_porch);
+	rda_write_dsi_reg(0x28,lcd->mipi_pinfo.h_front_porch);
+
+	dsi_bpp = (lcd->bpp != 32) ? lcd->bpp : 24;
+	rda_write_dsi_reg(0x2c,(lcd->width * (dsi_bpp >> 3)+ 6) >> data_lane);
+
+	rda_write_dsi_reg(0x30,lcd->mipi_pinfo.v_sync_active);
+	rda_write_dsi_reg(0x34,lcd->mipi_pinfo.v_back_porch);
+	rda_write_dsi_reg(0x38,lcd->mipi_pinfo.v_front_porch);
+	rda_write_dsi_reg(0x3c,lcd->height - 1);/*vat line */
+
+	/*
+	* sync data swap
+	*/
+	rda_write_dsi_reg(0x104,0x2);
+}
+
+void dsi_config(const struct lcd_panel_info *lcd)
+{
+	const struct rda_dsi_phy_ctrl *dsi_phy_db = lcd->mipi_pinfo.dsi_phy_db;
+
+	rda_write_dsi_reg(0x144, 0x14);		//analog phase
+	dsi_pll_on(TRUE);					//pll enable
+
+	dsi_enable(FALSE);					//dsi disable
+	dsi_op_mode(DSI_CMD);				//cmd mode
+	dsi_set_timing(dsi_phy_db);
+	dsi_set_parameter(lcd);
+}
+
+void dsi_swrite(u8 cmd)
+{
+
+	u32 cmd_header = 0;
+
+	cmd_header |= DSI_HDR_VC(0);
+	cmd_header |= DSI_HDR_SHORT_PKT;
+	if (cmd_tx_mode == CMD_HS_MODE)
+		cmd_header |= DSI_HDR_HS;
+	cmd_header |= DSI_HDR_DTYPE(DTYPE_DCS_SWRITE);
+	cmd_header |= DSI_HDR_DATA1(cmd);
+	cmd_header |= DSI_HDR_DATA2(0);
+
+	dsi_enable(FALSE);
+	dsi_op_mode(DSI_CMD);
+	dsi_cmd_queue_init(1);
+	rda_write_dsi_reg((u32)CMD_QUEUE_BASE, cmd_header);
+	dsi_enable(TRUE);
+}
+
+int dsi_lwrite(const struct rda_dsi_cmd *cmds, int cmds_cnt)
+{
+	u32 cmd_header = 0;
+	char *buf = (char *)COMMANDS_ADDR;
+	u32 offset = 0;
+	int cmds_num = 0, group_num = 0;
+	int i;
+
+	cmds_num = dsi_get_cmds_num(cmds, cmds_cnt);
+
+	if (cmd_tx_mode == CMD_LP_MODE) {
+		cmds_num++;
+		group_num = cmds_num;
+	} else
+		group_num = roundup(cmds_num, 4) / 4;
+
+	memset(buf, 0, group_num * 8);
+	if (cmd_tx_mode == CMD_LP_MODE) {
+		*buf++ = 0xaa;
+		for(i = 0; i < 7; i++)
+			*buf++ = 0x00;
+	}
+
+	for (i = 0; i < cmds_cnt; i++)
+		dsi_cmds_into_ddr(&cmds[i], &buf);
+
+	buf -= group_num * 8;
+	if (cmd_tx_mode == CMD_HS_MODE)
+		buf += (8 - cmds_num % 4);
+	printf("buf addr: %x\n", (u32)&(*buf));
+
+	dsi_dump_cmds(buf, group_num);
+	printf("cmds_num = %d\n", cmds_num);
+
+	set_lcdc_for_cmd((u32)&(*buf), group_num);
+
+	if (cmd_tx_mode == CMD_HS_MODE)
+		cmd_header |= DSI_HDR_HS;
+
+	dsi_enable(FALSE);
+	dsi_op_mode(DSI_CMD);
+	dsi_cmd_queue_init(cmds_cnt);
+	for (i = 0; i < cmds_cnt; i++) {
+		cmd_header |= DSI_HDR_WC(cmds[i].dlen);
+		cmd_header |= DSI_HDR_VC(0);
+		cmd_header |= DSI_HDR_LONG_PKT;
+		cmd_header |= DSI_HDR_DTYPE(DTYPE_DCS_LWRITE);
+		rda_write_dsi_reg(CMD_QUEUE_BASE + offset, cmd_header);
+		printf("cmd_header: %x   %x\n", cmd_header, offset);
+
+		offset += 4;
+		cmd_header = 0;
+		if (cmd_tx_mode == CMD_HS_MODE)
+			cmd_header |= DSI_HDR_HS;
+	}
+
+	dsi_enable(TRUE);
+
+	return 0;
+}
+
diff --git a/board/rda/common/timer_test.c b/board/rda/common/timer_test.c
new file mode 100644
index 0000000000..0cfbee680d
--- /dev/null
+++ b/board/rda/common/timer_test.c
@@ -0,0 +1,1620 @@
+#include <common.h>

+#include <asm/arch/cs_types.h>

+#include <asm/arch/global_macros.h>

+#include <asm/arch/reg_sysctrl.h>

+#include <asm/arch/reg_timer.h>

+

+#ifdef CONFIG_IRQ

+#include "irq.h"

+#endif

+

+#if defined(CONFIG_MACH_RDA8850E)

+static HWP_TIMER_AP_T *hwp_timer_tab[] = {hwp_apTimer,NULL,NULL};

+#elif defined(CONFIG_MACH_RDA8810H)

+//static HWP_TIMER_AP_T *hwp_timer_tab[] = {hwp_apTimer0,hwp_apTimer1,hwp_apTimer2};

+static HWP_TIMER_AP_T *hwp_timer_tab[] = {hwp_apTimer,NULL,NULL};

+#else

+#error "unknown machine !"

+#endif

+

+/* Hardware timer frequency value 2MHz or 16KHz */

+#define CONFIG_HW_TIMER_FAST_FREQ	2000000

+#define CONFIG_HW_TIMER_SLOW_FREQ	16384

+

+#define TIMER_BASE_TICK_US	1000000

+#define TIMER_BASE_TICK_MS	1000

+#define TIMER_BASE_TICK_S	1

+

+#define d_printf	printf

+

+#define USE_DATA_SIZE_64_BIT

+

+#ifdef USE_DATA_SIZE_64_BIT

+typedef unsigned long long int u64;

+#else

+typedef unsigned int u64;

+#endif /* USE_DATA_SIZE_64_BIT */

+

+typedef union

+{

+	volatile unsigned long long int timer;

+	struct

+	{

+		volatile unsigned int timer_l:32;

+		volatile unsigned int timer_h:32;

+	}fields;

+}TIMER;

+

+/* TIMER id number */

+enum TIMER_ID_TYPE

+{

+	TIMER0_ID = 0,

+	TIMER1_ID = 1,

+	TIMER2_ID = 2,

+};

+

+/* TIMER test case id number */

+enum TIMER_TC_ID_TYPE

+{

+	HWTIMER_TC_ID_REG_DEFAULT_VAL = 0,

+	HWTIMER_TC_ID_DELAY_US,

+	HWTIMER_TC_ID_DELAY_MS,

+	HWTIMER_TC_ID_DELAY_S,

+	HWTIMER_TC_ID_INTERVAL_IRQ_125MS,

+	HWTIMER_TC_ID_INTERVAL_IRQ_250MS,

+	HWTIMER_TC_ID_INTERVAL_IRQ_500MS,

+	HWTIMER_TC_ID_INTERVAL_IRQ_1000MS,

+	HWTIMER_TC_ID_DELAY_WAVE_1MS,

+	HWTIMER_TC_ID_IRQ_WAVE_125MS,

+	HWTIMER_TC_ID_IRQ_WAVE_250MS,

+	HWTIMER_TC_ID_IRQ_WAVE_500MS,

+	HWTIMER_TC_ID_IRQ_WAVE_1000MS,

+	HWTIMER_TC_ID_WRAP_IRQ,

+	HWTIMER_TC_ID_LOCK_VAL,

+	OSTIMER_TC_ID_REG_DEFAULT_VAL,

+	OSTIMER_TC_ID_DELAY_US,

+	OSTIMER_TC_ID_DELAY_MS,

+	OSTIMER_TC_ID_DELAY_WAVE_1MS,

+	OSTIMER_TC_ID_TEST_IRQ_STATUS,

+	OSTIMER_TC_ID_IRQ_WRAP,

+	OSTIMER_TC_ID_IRQ_REPEAT,

+	OSTIMER_TC_ID_LOCK_VAL,

+};

+

+/*

+ * TIMER LOCAL VARIBLE DEFINITION

+ *********************************************************

+ */

+

+/* hardware timer interval interrupt cycle*/

+enum TIMER_IT_CYCLE_TYPE

+{

+	IT_PERIOD_125MS = 0,

+	IT_PERIOD_250MS,

+	IT_PERIOD_500MS,

+	IT_PERIOD_1000MS,

+};

+

+static u32 g_hwtimer_freq = CONFIG_HW_TIMER_FAST_FREQ;

+static HWP_TIMER_AP_T *hwp_timer = hwp_apTimer;

+

+void hwt_delay_us(u32 us);

+static void timer_reset(void);

+static u32 caculate_tick_val(u32 time_us);

+static u32 caculate_time_val(u32 tick);

+static void set_timer_clk_freq(int fast_mode);

+static void ostimer_enable(int is_enable);

+static void ostimer_clear_irq(void);

+static void do_waiting_print(int *ptr_wait_cnt,int is_clear,const char *str);

+

+/*

+ * TIMER PRIVATE FUNCTION IMPLEMENTATION

+ *********************************************************

+ */

+static void get_hwtimer_time(TIMER *ptimer)

+{

+	/* Read high word first */

+	ptimer->fields.timer_h = (UINT32)(hwp_apTimer->HWTimer_LockVal_H);

+	ptimer->fields.timer_l = (UINT32)(hwp_apTimer->HWTimer_LockVal_L);

+	/* Check wrap case */

+	if (ptimer->fields.timer_h != hwp_apTimer->HWTimer_LockVal_H) {

+		ptimer->fields.timer_h = (UINT32)(hwp_apTimer->HWTimer_LockVal_H);

+		ptimer->fields.timer_l = (UINT32)(hwp_apTimer->HWTimer_LockVal_L);

+	}

+}

+

+static void hwtimer_delay_process(TIMER *start_time, TIMER *end_time,TIMER *cur_time,u64 tick)

+{

+	/* get current time value */

+	get_hwtimer_time(cur_time);

+

+	/* add us */

+	start_time->timer = cur_time->timer;

+	end_time->timer = cur_time->timer+tick;

+

+	/* wait until timeout */

+	while(1) {

+		get_hwtimer_time(cur_time);

+		if((cur_time->timer) > (end_time->timer))

+			break;

+	}

+}

+

+void hwt_delay_us(u32 us)

+{

+	TIMER start_time,end_time,cur_time;

+	u64 temp1,temp2;

+

+	temp1 = us * g_hwtimer_freq;

+	temp2 = TIMER_BASE_TICK_US;

+	temp1 = temp1 / temp2;

+	hwtimer_delay_process(&start_time,&end_time,&cur_time,temp1);

+}

+

+void hwt_delay_ms(u32 ms)

+{

+	u32 i = 0;

+	for(i = 0; i < ms; i++)

+		hwt_delay_us(1000); // delay 1 ms

+}

+

+static void do_waiting_print(int *ptr_wait_cnt,int is_clear,const char *str)

+{

+	static int cnt = 0;

+

+	if(is_clear) {

+		cnt = 0;

+		d_printf("\n");

+		return;

+	}

+	if(ptr_wait_cnt != NULL)

+		*ptr_wait_cnt = *ptr_wait_cnt + 1;

+	d_printf("%s",str);

+	cnt++;

+	if((cnt % 80) == 0) {

+		cnt = 0;

+		d_printf("\n");

+	}

+	hwt_delay_ms(1000);

+}

+

+static u32 caculate_tick_val(u32 time_us)

+{

+	u32 tick = 0;

+	u32 base = 0;

+	if(g_hwtimer_freq >= TIMER_BASE_TICK_US) {

+		  // fast freq = 2MHz, 1 us is 2 tick

+		  base = g_hwtimer_freq / (u32)TIMER_BASE_TICK_US;

+		  tick = time_us * base;

+	} else {

+		//slow freq = 16384Hz, 61 us is 1 tick

+		base = (u32)TIMER_BASE_TICK_US / g_hwtimer_freq;

+		tick = time_us / base;

+	}

+//	d_printf("cal tick value is 0x%x\n",tick);

+	return tick;

+}

+

+static u32 caculate_time_val(u32 tick)

+{	u32 base,time_val;

+	if(g_hwtimer_freq > TIMER_BASE_TICK_US) {

+		base = g_hwtimer_freq / TIMER_BASE_TICK_US;

+		time_val = tick / base;

+	} else {

+		base = TIMER_BASE_TICK_US / g_hwtimer_freq;

+		time_val = tick * base;

+	}

+//	d_printf("cal time value is 0x%x\n",time_val);

+	return time_val;

+}

+

+static void timer_reset(void)

+{

+	// reset all timer

+	hwp_sysCtrlAp->APB1_Rst_Set = SYS_CTRL_AP_SET_APB1_RST_TIMER;

+	hwp_sysCtrlAp->APB1_Rst_Clr = SYS_CTRL_AP_SET_APB1_RST_TIMER;

+}

+

+static void set_timer_clk_freq(int fast_mode)

+{

+	//0 is fast mode, 1 is slow mode

+	if(fast_mode) {

+		hwp_sysCtrlAp->Sel_Clock &= (~SYS_CTRL_AP_TIMER_SEL_FAST_SLOW);

+		g_hwtimer_freq = CONFIG_HW_TIMER_FAST_FREQ;

+	} else {

+		hwp_sysCtrlAp->Sel_Clock |= SYS_CTRL_AP_TIMER_SEL_FAST_SLOW;

+		g_hwtimer_freq = CONFIG_HW_TIMER_SLOW_FREQ;

+	}

+}

+

+#define GPIOA_SET_ADDR	0x20930030

+#define GPIOA_CLR_ADDR	0x20930034

+

+static void do_set_gpo_pin(int pin_id, int pin_val)

+{

+	unsigned int set_addr = GPIOA_SET_ADDR; //GPIOA 's GPO register set address

+	unsigned int clr_addr = GPIOA_CLR_ADDR; // GPIOA 's GPO register reset address

+	unsigned int val = 0;

+

+	/* pin_id must be 0,1,2 */

+	if((pin_id < 0) || (pin_id >= 3)) {

+		d_printf("set gpo pin value failed!,pin id is %d\n",pin_id);

+		return;

+	}

+	val = 1 << pin_id;

+	if(pin_val) {

+		*(volatile unsigned int *)set_addr = val;

+	} else {

+		*(volatile unsigned int *)clr_addr = val;

+	}

+#if 0

+	{

+		unsigned int val = *(volatile unsigned int *)set_addr;

+		d_printf("set_gpo_reg value : %x\n",val);

+	}

+#endif

+

+}

+/*

+ * TIMER PUBLIC FUNCTION IMPLEMENTATION

+ *********************************************************

+ */

+

+int hwtimer_reg_default_value(u8 is_reset)

+{

+	unsigned int reg_val[8];

+	int idx = 0;

+

+	d_printf("\nread HWTimer register value ...\n");

+	if(is_reset > 0) {

+	        timer_reset();

+	}

+	reg_val[idx++] = hwp_timer->HWTimer_Ctrl;

+	reg_val[idx++] = hwp_timer->HWTimer_CurVal_L;

+	reg_val[idx++] = hwp_timer->HWTimer_CurVal_H;

+	reg_val[idx++] = hwp_timer->HWTimer_LockVal_L;

+	reg_val[idx++] = hwp_timer->HWTimer_LockVal_H;

+	idx = 0;

+	d_printf("HWTimer_Ctrl:        0x%x\n",reg_val[idx++]);

+	d_printf("HWTimer_CurVal_L:    0x%x\n",reg_val[idx++]);

+	d_printf("HWTimer_CurVal_H:    0x%x\n",reg_val[idx++]);

+	d_printf("HWTimer_LockVal_L:   0x%x\n",reg_val[idx++]);

+	d_printf("HWTimer_LockVal_H:   0x%x\n",reg_val[idx++]);

+	return 0;

+}

+

+int hwtimer_delay_us(u32 us)

+{

+	TIMER start_time,end_time,cur_time;

+	u32 tick,dly_time = 0;

+	u32 real_err = 0,max_err = 5,err_diff;

+

+	d_printf("\nHWTimer delay %d us ...\n",(int)us);

+

+	tick = caculate_tick_val(us);

+	hwtimer_delay_process(&start_time,&end_time,&cur_time,tick);

+

+	/* get real delay value */

+	//dly_time = (cur_time.fields.timer_l - start_time.fields.timer_l) / tick_1us;

+	dly_time = caculate_time_val((cur_time.fields.timer_l - start_time.fields.timer_l));

+	err_diff = (dly_time > us) ? (dly_time - us):(us - dly_time);

+	real_err = (err_diff * 100) / us;

+

+	d_printf("\n");

+	d_printf("expect delay:   0x%x us\n",us);

+	d_printf("real delay:     0x%x us\n",dly_time);

+	d_printf("error value:    0x%x us\n",err_diff);

+	d_printf("error percent:  0x%x\n",real_err);

+	if(real_err <= max_err) {

+		d_printf("timer error %d is less than %d,test success !!!\n",

+				real_err,max_err);

+		return 0;

+	} else {

+		d_printf("time error %d is greater than %d,test failed ###\n",

+				real_err,max_err);

+		return -1;

+	}

+}

+

+int hwtimer_delay_ms(u32 ms)

+{

+	u32 i = 0;

+

+	d_printf("delay %d ms ...\n",(int)ms);

+	for(i = 0; i < ms; i++)

+		hwt_delay_us(1000); // delay 1 ms

+	d_printf("delay %d ms success !!!\n",(int)ms);

+	return 0;

+}

+

+int hwtimer_delay_s(u32 s)

+{

+	u32 i = 0;

+	d_printf("delay %d s ...\n",(int)s);

+	for(i = 0; i < s*1000; i++)

+		hwt_delay_us(1000); //delay 1 ms

+	d_printf("delay %d s success !!!\n",(int)s);

+	return 0;

+}

+

+int hwtimer_delay_wave(int period_us, int irq_times)

+{

+	int irq_cnt = 0;

+	int half_period = period_us / 2;

+	int gpo_pin = 0;

+

+	if(irq_times <= 0)

+		return -1;

+	d_printf("\n");

+	d_printf("HWTimer delay wave starts\n");

+	d_printf("period_us is 0x%x\n",period_us);

+	d_printf("irq_times is 0x%x\n",irq_times);

+	d_printf("Output wave from GPO 0 ...\n");

+	while(1) {

+		if(irq_cnt % 2) {

+			do_set_gpo_pin(gpo_pin,0);

+		} else {

+			do_set_gpo_pin(gpo_pin,1);

+		}

+		hwt_delay_us(half_period);

+		irq_cnt++;

+		if(irq_cnt >= irq_times)

+			break;

+	}

+	do_set_gpo_pin(gpo_pin,0);

+	d_printf("HWTimer delay wave passed !!!\n");

+	return 0;

+}

+

+/******************************************************************************

+ * @name:	 hwtimer_interval_irq

+ * @description: to test hwtimer interval irq function

+ * @parameter:

+ *	cycle:	interval cycle value, this value can be:

+ *		IT_PERIOD_125MS

+ *		IT_PERIOD_250MS

+ *		IT_PERIOD_500MS

+ *		IT_PERIOD_1000MS

+ *	irq_times: test times value

+ * @notes:

+ * 	step1: disable timer irq

+ * 	step2: configure irq cycle

+ * 	step3: clear irq mask

+ * 	step4: enable timer irq

+ * @return: 0(SUCCESS), -1(FAILED)

+ ******************************************************************************

+ */

+

+int hwtimer_interval_irq_wave( enum TIMER_IT_CYCLE_TYPE cycle,int irq_times)

+{

+	int irq_cnt = 0;

+	int gpo_pin = 0;

+

+	d_printf("\nHWTimer interval irq wave starts\n");

+	d_printf("cycle bit: 0x%x\n",cycle);

+	d_printf("irq_times: 0x%x\n",irq_times);

+

+	/* Disable interval IRQ */

+	hwp_timer->HWTimer_Ctrl &= (~TIMER_AP_INTERVAL_EN);

+

+	/* Set intterupt cycle */

+	hwp_timer->HWTimer_Ctrl &= TIMER_AP_INTERVAL(0x3); //bit0,bit1

+	hwp_timer->HWTimer_Ctrl |= TIMER_AP_INTERVAL(cycle);

+

+	/* Set irq mask interval */

+	hwp_timer->Timer_Irq_Mask_Set = TIMER_AP_HWTIMER_ITV_MASK;

+

+	// clear interval irq

+	hwp_timer->Timer_Irq_Clr = TIMER_AP_HWTIMER_ITV_CLR;

+	while((hwp_timer->Timer_Irq_Cause & TIMER_AP_HWTIMER_ITV_CAUSE) != 0);

+

+	d_printf("TIMER_Irq_Mask_Set: 0x%x\n",hwp_timer->Timer_Irq_Mask_Set);

+	d_printf("TIMER_Irq_Mask_Clr: 0x%x\n",hwp_timer->Timer_Irq_Mask_Clr);

+	d_printf("Timer_Irq_Clr:      0x%x\n",hwp_timer->Timer_Irq_Clr);

+	d_printf("HWTimer_Ctrl:       0x%x\n",hwp_timer->HWTimer_Ctrl);

+	d_printf("Output wave from GPO %x ...\n",gpo_pin);

+	/* Enable interval IRQ */

+	hwp_timer->HWTimer_Ctrl |= TIMER_AP_INTERVAL_EN;

+	// Get Start time

+	irq_cnt = 0;

+	while(1) {

+		// set gpo pin level HIGH or LOW

+		if(irq_cnt % 2)

+			do_set_gpo_pin(gpo_pin,0); // set low level

+		else

+			do_set_gpo_pin(gpo_pin,1); // set high level

+		// waiting for irq status set

+		while((hwp_timer->Timer_Irq_Cause & TIMER_AP_HWTIMER_ITV_CAUSE) == 0);

+		//clear irq status

+		hwp_timer->Timer_Irq_Clr = TIMER_AP_HWTIMER_ITV_CLR;

+		while((hwp_timer->Timer_Irq_Cause & TIMER_AP_HWTIMER_ITV_CAUSE) != 0);

+

+		irq_cnt++;

+		if(irq_cnt >= irq_times) {

+			break;

+		}

+	}

+	d_printf("Output wave end\n");

+	do_set_gpo_pin(gpo_pin,0);

+

+	// disable irq

+	hwp_timer->HWTimer_Ctrl &= (~TIMER_AP_INTERVAL_EN);

+

+	// clear mask

+	hwp_timer->Timer_Irq_Mask_Clr = TIMER_AP_HWTIMER_ITV_MASK;

+	d_printf("HWTimer interval irq wave passed !!!\n");

+	return 0;

+}

+

+int hwtimer_interval_irq( enum TIMER_IT_CYCLE_TYPE cycle,int irq_times)

+{

+	TIMER timer_a,timer_b;

+	u32 tick_diff = 0,e_period = 0,r_period,d_period = 0;

+	volatile int irq_cnt = 0;

+	u32 real_err = 0, max_err = 5;

+	volatile u32 t1;

+	volatile u32 t2;

+

+	d_printf("\nHWTimer interval irq test starts\n");

+	d_printf("cycle bit: 0x%x\n",cycle);

+	d_printf("irq_times: 0x%x\n",irq_times);

+

+	/* Disable interval IRQ */

+	hwp_timer->HWTimer_Ctrl &= (~TIMER_AP_INTERVAL_EN);

+

+	/* Set intterupt cycle */

+	hwp_timer->HWTimer_Ctrl &= TIMER_AP_INTERVAL(0x3); //bit0,bit1

+	hwp_timer->HWTimer_Ctrl |= TIMER_AP_INTERVAL(cycle);

+

+	/* Set/Clear irq mask interval */

+	hwp_timer->Timer_Irq_Mask_Set = TIMER_AP_HWTIMER_ITV_MASK;

+

+	// clear interval irq

+	hwp_timer->Timer_Irq_Clr = TIMER_AP_HWTIMER_ITV_CLR;

+	while((hwp_timer->Timer_Irq_Cause & TIMER_AP_HWTIMER_ITV_CAUSE) != 0);

+

+	d_printf("TIMER_Irq_Mask_Set: 0x%x\n",hwp_timer->Timer_Irq_Mask_Set);

+	d_printf("TIMER_Irq_Mask_Clr: 0x%x\n",hwp_timer->Timer_Irq_Mask_Clr);

+	d_printf("Timer_Irq_Clr:      0x%x\n",hwp_timer->Timer_Irq_Clr);

+	d_printf("HWTimer_Ctrl:       0x%x\n",hwp_timer->HWTimer_Ctrl);

+

+	/* Enable interval IRQ */

+	hwp_timer->HWTimer_Ctrl |= TIMER_AP_INTERVAL_EN;

+	// Get Start time

+	get_hwtimer_time(&timer_a);

+	while(1) {

+		//wait irq status

+		//while((hwp_timer->Timer_Irq_Cause & TIMER_AP_HWTIMER_ITV_STATUS) == 0);

+		while((hwp_timer->Timer_Irq_Cause & TIMER_AP_HWTIMER_ITV_CAUSE) == 0);

+		get_hwtimer_time(&timer_b);

+		//clear irq status

+		hwp_timer->Timer_Irq_Clr = TIMER_AP_HWTIMER_ITV_CLR;

+		while((hwp_timer->Timer_Irq_Cause & TIMER_AP_HWTIMER_ITV_CAUSE) != 0);

+

+		irq_cnt++;

+		if(irq_cnt >= irq_times) {

+			break;

+		}

+	}

+	// disable irq

+	hwp_timer->HWTimer_Ctrl &= (~TIMER_AP_INTERVAL_EN);

+	// clear mask

+	hwp_timer->Timer_Irq_Mask_Clr = TIMER_AP_HWTIMER_ITV_MASK;

+	// check result

+	d_printf("Timer_a value,h:%x,l:%x\n",

+			timer_a.fields.timer_h,

+			timer_a.fields.timer_l);

+	d_printf("Timer_b value,h:%x,l:%x\n",

+			timer_b.fields.timer_h,

+			timer_b.fields.timer_l);

+	switch(cycle) {

+	case IT_PERIOD_125MS: e_period = 125;break;

+	case IT_PERIOD_250MS: e_period = 250;break;

+	case IT_PERIOD_500MS: e_period = 500;break;

+	case IT_PERIOD_1000MS: e_period = 1000;break;

+	default:d_printf("timer cycle error,exit !\n");return -1;

+	}

+

+	t1 = (u32)(timer_b.fields.timer_l);

+	t2 = (u32)(timer_a.fields.timer_l);

+	tick_diff = t1 - t2;

+	r_period = caculate_time_val(tick_diff) / irq_times;

+	r_period = r_period / 1000;

+	d_period = (r_period > e_period)?(r_period - e_period):(e_period - r_period);

+	real_err = (d_period * 100) / e_period;

+

+	d_printf("\n");

+	d_printf("tick_diff:       0x%x\n",tick_diff);

+	d_printf("expected period: 0x%x\n",e_period);

+	d_printf("real period:     0x%x\n",r_period);

+	d_printf("error value:     0x%x\n",d_period);

+	d_printf("error percent    0x%x\n",real_err);

+	if(real_err <= max_err) {

+		d_printf("timer error %d is less than %d,test success !!!\n",

+				real_err,max_err);

+		return 0;

+	} else {

+		d_printf("timer error %d is greater than %d,test failed ###\n",

+				real_err,max_err);

+		return -1;

+	}

+}

+

+/******************************************************************************

+ * @name:	 hwtimer_wrap_irq

+ * @description: to test hwtimer wrap irq function

+ * @parameter:

+ *	irq_times: test times value

+ * @notes:

+ * @return: 0(SUCCESS), -1(FAILED)

+ ******************************************************************************

+ */

+

+int hwtimer_wrap_irq(int irq_times)

+{

+	int sec_count = 0;

+	u32 val_h,val_l,wait_sec = 3,wait_tick;

+

+	d_printf("test HWTimer wrap irq starts\n");

+	timer_reset();

+	// disable interval irq

+	hwp_timer->HWTimer_Ctrl &= (~TIMER_AP_INTERVAL_EN);

+	// disable warp irq

+	hwp_timer->Timer_Irq_Mask_Clr = TIMER_AP_HWTIMER_WRAP_MASK;

+	// clear warp irq

+	hwp_timer->Timer_Irq_Clr = TIMER_AP_HWTIMER_WRAP_CLR;

+	// enable wrap irq

+	hwp_timer->Timer_Irq_Mask_Set = TIMER_AP_HWTIMER_WRAP_MASK;

+	wait_tick = 0xFFFFFFFF - caculate_tick_val(wait_sec * 1000000);

+	sec_count = 0;

+	d_printf("\nWaiting high 32 bit Counter increasing to 0x%x...\n",

+			0xFFFFFFFE);

+	while(1) {

+		val_h = hwp_timer->HWTimer_LockVal_H;

+		val_l = hwp_timer->HWTimer_LockVal_L;

+		do_waiting_print(&sec_count,0,".");

+		if(val_h == 0xFFFFFFFE)

+			break;

+	}

+	d_printf("\nWaiting low 32 bit counter increasing to 0x%x\n",

+			wait_tick);

+	while(1) {

+		val_h = hwp_timer->HWTimer_LockVal_H;

+		val_l = hwp_timer->HWTimer_LockVal_L;

+		do_waiting_print(&sec_count,0,".");

+		if(val_l >= wait_tick)

+			break;

+	}

+	d_printf("\nWaiting Wrap interrupt occuring...\n");

+	while((hwp_timer->Timer_Irq_Cause & TIMER_AP_HWTIMER_WRAP_CAUSE) == 0);

+	val_h = hwp_timer->HWTimer_LockVal_H;

+	val_l = hwp_timer->HWTimer_LockVal_L;

+	hwp_timer->Timer_Irq_Clr = TIMER_AP_HWTIMER_WRAP_CLR;

+	while((hwp_timer->Timer_Irq_Cause & TIMER_AP_HWTIMER_WRAP_CAUSE) != 0);

+	// disable warp irq

+	hwp_timer->Timer_Irq_Mask_Clr = TIMER_AP_HWTIMER_WRAP_MASK;

+	// clear wrap interrupt status

+	hwp_timer->Timer_Irq_Clr = TIMER_AP_HWTIMER_WRAP_CLR;

+	d_printf("Time elasped 0x%x us\n",sec_count);

+	d_printf("When wrap irq occur, the timer tick is H:%x,L:%x\n",

+			val_h,val_l);

+	// after warp interrupt occur, the counter should change from maximum value to 0.

+	if((val_l & 0xFFFFFFF0) != 0) {

+		d_printf("HWTimer warp irq test failed ###\n");

+		return -1;

+	} else {

+		d_printf("HWTimer warp irq test success !!!\n");

+		return 0;

+	}

+}

+

+/******************************************************************************

+ * @name:	 hwtimer_lockval_function

+ * @description: to test hwtimer lock function

+ * @parameter:

+ * @notes:

+ * @return: 0(SUCCESS), -1(FAILED)

+ ******************************************************************************

+ */

+int hwtimer_lock_value(void)

+{

+	u32 val_h,val_l;

+	u32 wait_tick = 0, wait_sec = 3,cnt_1s = 0;

+	int ok = 0;

+

+	d_printf("\nHWTimer lock value starts\n");

+	wait_tick = 0xFFFFFFFF - caculate_tick_val(wait_sec * 1000000);

+	timer_reset();

+	val_l = hwp_timer->HWTimer_LockVal_L;

+	val_h = hwp_timer->HWTimer_LockVal_H;

+	if(val_h != 0) {

+		d_printf("High 32 bit counter is not zero,exit\n");

+		return -1;

+	}

+	d_printf("High 32 bit counter val: 0x%x\n",val_h);

+	d_printf("Low 32 bit counter val : 0x%x\n",val_l);

+	d_printf("\nWaiting for low 32 bit counter increasing to 0x%x...\n",wait_tick);

+	while(1) {

+		val_l = hwp_timer->HWTimer_LockVal_L;

+		val_h = hwp_timer->HWTimer_LockVal_H;

+		if(val_l >= wait_tick)

+			break;

+		do_waiting_print(NULL,0,".");

+		cnt_1s++;

+	}

+	d_printf("\nTime has elapsed 0x%x seconds\n",cnt_1s);

+	d_printf("\nWaiting for jitter occuring...\n");

+	while(1) {

+		val_l = hwp_timer->HWTimer_LockVal_L;

+		val_h = hwp_timer->HWTimer_LockVal_H;

+		if((val_l == 0) || (val_l <= 0xFF))

+			break;

+	}

+	// when jitter occur, 		val_h = 0x00000000, val_l = 0xffffffff,

+	// if okay, next should be: 	val_h = 0x00000001, val_l = 0x00000000

+	// if error, maybe: 		val_h = 0x00000000, val_h = 0x00000000;

+	if(val_h == 1)

+		ok = 1;

+	d_printf("Get last counter high 32 bit: 0x%x\n",val_h);

+	d_printf("Get last counter low  32 bit: 0x%x\n",val_l);

+	if(ok) {

+		d_printf("HWTimer lock value test success !!!\n");

+		return 0;

+	} else {

+		d_printf("HWTimer lock value test failed ###\n");

+		return -1;

+	}

+}

+

+/******************************************************************************

+ * @name:	 get_ostimer_register_value

+ * @description: to test ostimer register default value

+ * @parameter:

+ * @notes:

+ * @return: 0(SUCCESS), -1(FAILED)

+ ******************************************************************************

+ */

+

+int ostimer_reg_default_value(int is_reset)

+{

+	u32 reg_val[10];

+	int idx = 0;

+

+	d_printf("read OSTimer register value ...\n");

+	if(is_reset > 0) {

+	    timer_reset();

+	}

+	reg_val[idx++] = hwp_timer->OSTimer_Ctrl;

+	reg_val[idx++] = hwp_timer->OSTimer_LoadVal_L;

+	reg_val[idx++] = hwp_timer->OSTimer_CurVal_H;

+	reg_val[idx++] = hwp_timer->OSTimer_CurVal_L;

+	reg_val[idx++] = hwp_timer->OSTimer_LockVal_H;

+	reg_val[idx++] = hwp_timer->OSTimer_LockVal_L;

+	reg_val[idx++] = hwp_timer->Timer_Irq_Mask_Set;

+	reg_val[idx++] = hwp_timer->Timer_Irq_Mask_Clr;

+	reg_val[idx++] = hwp_timer->Timer_Irq_Cause;

+	idx = 0;

+	d_printf("OSTimer_Ctrl:       %x\n",reg_val[idx++]);

+	d_printf("OSTimer_LoadVal_L:  %x\n",reg_val[idx++]);

+	d_printf("OSTimer_CurVal_H:   %x\n",reg_val[idx++]);

+	d_printf("OSTimer_CurVal_L:   %x\n",reg_val[idx++]);

+	d_printf("OSTimer_LockVal_H:  %x\n",reg_val[idx++]);

+	d_printf("OSTimer_LockVal_L:  %x\n",reg_val[idx++]);

+	d_printf("Timer_Irq_Mask_Set: %x\n",reg_val[idx++]);

+	d_printf("Timer_Irq_Mask_Clr: %x\n",reg_val[idx++]);

+	d_printf("Timer_Irq_Cause:    %x\n",reg_val[idx++]);

+	return 0;

+}

+

+static void ostimer_enable(int is_enable)

+{

+	if(is_enable) {

+		hwp_timer->OSTimer_Ctrl |= TIMER_AP_ENABLE;

+		while((hwp_timer->OSTimer_Ctrl & TIMER_AP_ENABLED) == 0);

+	} else {

+		hwp_timer->OSTimer_Ctrl &= (u32)(~TIMER_AP_ENABLE);

+		while((hwp_timer->OSTimer_Ctrl & TIMER_AP_ENABLED) != 0);

+	}

+}

+

+static void ostimer_clear_irq(void)

+{

+	// Clear IRQ status

+	hwp_timer->Timer_Irq_Clr = TIMER_AP_OSTIMER_CLR;

+	// Waiting until state is cleared

+	//while((hwp_timer->OSTimer_Ctrl & TIMER_AP_CLEARED) != 0);

+	while((hwp_timer->Timer_Irq_Cause & TIMER_AP_OSTIMER_CAUSE) != 0);

+}

+

+/******************************************************************************

+ * @name:	    ostimer_test_irq_status

+ * @description:    to check irq status wether is set when interrupt occuring.

+ * @parameter:

+ *		tick: 	   the initial value of ostimer starts

+ * @notes:

+ * @return: 0(SUCCESS), -1(FAILED)

+ ******************************************************************************

+ */

+

+int ostimer_test_irq_status(u32 us)

+{

+	u64 temp;

+	u32 load_tick_h,load_tick_l;

+	int ok = 0;

+

+	d_printf("\nOSTimer test irq status starts\n");

+	// disable timer

+	ostimer_enable(0);

+	// repeat mode,not wrap

+	hwp_timer->OSTimer_Ctrl &= (~TIMER_AP_WRAP);

+	hwp_timer->OSTimer_Ctrl |= TIMER_AP_REPEAT;

+	// write initial value

+	temp = caculate_tick_val(us);

+	load_tick_l = 0xFFFFFFFF & temp;

+#ifdef USE_DATA_SIZE_64_BIT

+	load_tick_h = 0xFFFFFF & (temp >> 32);

+#else

+	load_tick_h = 0;

+#endif

+	hwp_timer->OSTimer_LoadVal_L = load_tick_l;

+	hwp_timer->OSTimer_Ctrl &= (~TIMER_AP_OS_LOADVAL_H_MASK);

+	hwp_timer->OSTimer_Ctrl |= load_tick_h;

+	// load to initial value

+	hwp_timer->OSTimer_Ctrl |= TIMER_AP_LOAD;

+	// clear irq status

+	ostimer_clear_irq();

+	d_printf("IRQ Mask is cleared\n");

+	// clear mask

+	hwp_timer->Timer_Irq_Mask_Clr = TIMER_AP_OSTIMER_MASK;

+	// print value for debug

+	d_printf("OSTimer_Ctrl:       0x%x\n",hwp_timer->OSTimer_Ctrl);

+	d_printf("OSTimer_LoadVal_L:  0x%x\n",hwp_timer->OSTimer_LoadVal_L);

+	d_printf("Timer_Irq_Mask_Set: 0x%x\n",hwp_timer->Timer_Irq_Mask_Set);

+	d_printf("Timer_Irq_Mask_Clr: 0x%x\n",hwp_timer->Timer_Irq_Mask_Clr);

+	d_printf("Timer_Irq_Cause:    0x%x\n",hwp_timer->Timer_Irq_Cause);

+	d_printf("OSTimer_LockVal_H:  0x%x\n",hwp_timer->OSTimer_LockVal_H);

+	d_printf("OSTimer_LockVal_L:  0x%x\n",hwp_timer->OSTimer_LockVal_L);

+	d_printf("\n");

+	d_printf("Enable timer ...\n");

+	d_printf("Waiting for interrupt occuring ...\n");

+	ostimer_enable(1);

+	// waiting for irq cause state

+	while(1) {

+		if(hwp_timer->Timer_Irq_Cause & TIMER_AP_OSTIMER_STATUS) {

+			// the irq cause flag should not be 1

+			if((hwp_timer->Timer_Irq_Cause & TIMER_AP_OSTIMER_CAUSE) == 0)

+				ok = 1;

+			else

+				ok = 0;

+			break;

+		}

+	}

+	d_printf("\n");

+	d_printf("OSTimer_Ctrl:       0x%x\n",hwp_timer->OSTimer_Ctrl);

+	d_printf("OSTimer_LoadVal_L:  0x%x\n",hwp_timer->OSTimer_LoadVal_L);

+	d_printf("Timer_Irq_Mask_Set: 0x%x\n",hwp_timer->Timer_Irq_Mask_Set);

+	d_printf("Timer_Irq_Mask_Clr: 0x%x\n",hwp_timer->Timer_Irq_Mask_Clr);

+	d_printf("Timer_Irq_Cause:    0x%x\n",hwp_timer->Timer_Irq_Cause);

+	d_printf("OSTimer_LockVal_H:  0x%x\n",hwp_timer->OSTimer_LockVal_H);

+	d_printf("OSTimer_LockVal_L:  0x%x\n",hwp_timer->OSTimer_LockVal_L);

+	d_printf("\n");

+	d_printf("disable timer ...\n");

+	ostimer_enable(0);

+	ostimer_clear_irq();

+	if(ok) {

+		d_printf("\nOSTimer irq status test success !!!\n");

+		return 0;

+	} else {

+		d_printf("\nOSTimer irq status test failed ###\n");

+		return -1;

+	}

+}

+

+/******************************************************************************

+ * @name:	 ostimer_delay_us

+ * @description: delay n us by ostimer

+ * @parameter:

+ * @notes:

+ * @return: 0(SUCCESS), -1(FAILED)

+ ******************************************************************************

+ */

+void ost_delay_us(u32 us)

+{

+	u32 load_tick_h,load_tick_l;

+	u64 temp;

+

+	// disable timer

+	ostimer_enable(0);

+	// repeat mode,not wrap

+	hwp_timer->OSTimer_Ctrl &= (~TIMER_AP_WRAP);

+	hwp_timer->OSTimer_Ctrl |= TIMER_AP_REPEAT;

+	// write initial value

+	temp = caculate_tick_val(us);

+	load_tick_l = 0xFFFFFFFF & temp;

+#ifdef USE_DATA_SIZE_64_BIT

+	load_tick_h = 0xFFFFFF & (temp >> 32);

+#else

+	load_tick_h = 0x0;

+#endif

+	hwp_timer->OSTimer_LoadVal_L = load_tick_l;

+	hwp_timer->OSTimer_Ctrl &= (~TIMER_AP_OS_LOADVAL_H_MASK);

+	hwp_timer->OSTimer_Ctrl |= load_tick_h;

+	// load to initial value

+	hwp_timer->OSTimer_Ctrl |= TIMER_AP_LOAD;

+	// clear irq status

+	ostimer_clear_irq();

+	// set mask

+	hwp_timer->Timer_Irq_Mask_Set = TIMER_AP_OSTIMER_MASK;

+	// enable timer

+	ostimer_enable(1);

+	// waiting for irq cause state

+	while(1) {

+		if(hwp_timer->Timer_Irq_Cause & TIMER_AP_OSTIMER_CAUSE) {

+			break;

+		}

+	}

+	ostimer_enable(0);

+	ostimer_clear_irq();

+	return;

+}

+

+int ostimer_delay_wave(int period_us,int times)

+{

+	u32 half_period = period_us / 2;

+	int cnt = 0;

+	int gpo_pin = 0;

+

+	d_printf("OSTimer delay wave starts\n");

+	while(1) {

+		if(cnt % 2) {

+			do_set_gpo_pin(gpo_pin,0);

+		} else {

+			do_set_gpo_pin(gpo_pin,1);

+		}

+		ost_delay_us(half_period);

+		cnt++;

+		if(cnt >= times)

+			break;

+	}

+	d_printf("OSTimer delay wave test success !!!\n");

+	return 0;

+}

+

+int ostimer_delay_us(u32 us)

+{

+	u32 load_tick_h,load_tick_l,real_dly,err_dly,max_err = 5,real_err;

+	u64 temp;

+	int ok = 0;

+	TIMER timer_a,timer_b;

+

+	d_printf("\nOSTimer delay %d us ...\n",us);

+	// disable timer

+	ostimer_enable(0);

+	// repeat mode,not wrap

+	hwp_timer->OSTimer_Ctrl &= (~TIMER_AP_WRAP);

+	hwp_timer->OSTimer_Ctrl |= TIMER_AP_REPEAT;

+	// write initial value

+	temp = caculate_tick_val(us);

+	load_tick_l = 0xFFFFFFFF & temp;

+#ifdef USE_DATA_SIZE_64_BIT

+	load_tick_h = 0xFFFFFF & (temp >> 32);

+#else

+	load_tick_h = 0x0;

+#endif

+	hwp_timer->OSTimer_LoadVal_L = load_tick_l;

+	hwp_timer->OSTimer_Ctrl &= (~TIMER_AP_OS_LOADVAL_H_MASK);

+	hwp_timer->OSTimer_Ctrl |= load_tick_h;

+	// load to initial value

+	hwp_timer->OSTimer_Ctrl |= TIMER_AP_LOAD;

+	// clear irq status

+	ostimer_clear_irq();

+	// set mask

+	hwp_timer->Timer_Irq_Mask_Set = TIMER_AP_OSTIMER_MASK;

+	// print value for debug

+	d_printf("OSTimer_Ctrl:       0x%x\n",hwp_timer->OSTimer_Ctrl);

+	d_printf("OSTimer_LoadVal_L:  0x%x\n",hwp_timer->OSTimer_LoadVal_L);

+	d_printf("Timer_Irq_Mask_Set: 0x%x\n",hwp_timer->Timer_Irq_Mask_Set);

+	d_printf("Timer_Irq_Mask_Clr: 0x%x\n",hwp_timer->Timer_Irq_Mask_Clr);

+	d_printf("Timer_Irq_Cause:    0x%x\n",hwp_timer->Timer_Irq_Cause);

+	d_printf("OSTimer_LockVal_H:  0x%x\n",hwp_timer->OSTimer_LockVal_H);

+	d_printf("OSTimer_LockVal_L:  0x%x\n",hwp_timer->OSTimer_LockVal_L);

+	d_printf("Enable timer...\n");

+	d_printf("Waiting for interrupt occuring...\n");

+	ostimer_enable(1);

+	get_hwtimer_time(&timer_a);

+	// waiting for irq cause state

+	while(1) {

+		if(hwp_timer->Timer_Irq_Cause & TIMER_AP_OSTIMER_CAUSE) {

+			get_hwtimer_time(&timer_b);

+			break;

+		}

+	}

+	real_dly = caculate_time_val((timer_b.fields.timer_l - timer_a.fields.timer_l));

+	err_dly = (real_dly > us) ? (real_dly - us):(us - real_dly);

+	real_err = (err_dly * 100) / real_dly;

+	if(real_err <= max_err)

+		ok = 1;

+	else

+		ok = 0;

+

+	d_printf("\n");

+	d_printf("Expected delay: 0x%x\n",us);

+	d_printf("Real delay:     0x%x\n",real_dly);

+	d_printf("Error value:    0x%x\n",err_dly);

+	d_printf("Error percent:  0x%x\n",real_err);

+	d_printf("\n");

+	d_printf("OSTimer_Ctrl:       0x%x\n",hwp_timer->OSTimer_Ctrl);

+	d_printf("OSTimer_LoadVal_L:  0x%x\n",hwp_timer->OSTimer_LoadVal_L);

+	d_printf("Timer_Irq_Mask_Set: 0x%x\n",hwp_timer->Timer_Irq_Mask_Set);

+	d_printf("Timer_Irq_Mask_Clr: 0x%x\n",hwp_timer->Timer_Irq_Mask_Clr);

+	d_printf("Timer_Irq_Cause:    0x%x\n",hwp_timer->Timer_Irq_Cause);

+	d_printf("OSTimer_LockVal_H:  0x%x\n",hwp_timer->OSTimer_LockVal_H);

+	d_printf("OSTimer_LockVal_L:  0x%x\n",hwp_timer->OSTimer_LockVal_L);

+	d_printf("\n");

+	d_printf("disable timer\n");

+	ostimer_enable(0);

+	ostimer_clear_irq();

+	if(ok) {

+		d_printf("\nerror %d is less than %d,test success !!!\n"

+				,real_err,max_err);

+		return 0;

+	} else {

+		d_printf("\nerror %d is greater than %d,test failed ####\n"

+				,real_err,max_err);

+		return -1;

+	}

+}

+

+/******************************************************************************

+ * @name:	 ostimer_delay_ms

+ * @description: delay n ms by ostimer

+ * @parameter:

+ * @notes:

+ * @return: 0(SUCCESS), -1(FAILED)

+ ******************************************************************************

+ */

+

+int ostimer_delay_ms(u32 ms)

+{

+	d_printf("OSTimer delay %d ms \n",ms);

+	ostimer_delay_us(ms * 1000);

+	d_printf("OSTimer delay ms test success !!!\n");

+	return 0;

+}

+

+/******************************************************************************

+ * @name:	    ostimer_repeat_irq

+ * @description:    to generate irq status when ostimer work at repeat mode

+ * @parameter:

+ *		period: 	the interrupt period us time value

+ *		irq_times: the irq occuring times when ostimer is running.

+ * @notes:

+ * @return: 0(SUCCESS), -1(FAILED)

+ ******************************************************************************

+ */

+

+int ostimer_repeat_irq(u32 period,int irq_times)

+{

+	u32 load_tick_h,load_tick_l,real_period,err_period,err_percent,max_err_percent = 5;

+	int irq_cnt = 0,ok = 0;

+	u64 temp;

+	TIMER timer_a,timer_b;

+

+	d_printf("\nOSTimer repeat irq %d times with period %d\n",irq_times,period);

+	// disable timer

+	ostimer_enable(0);

+	// repeat mode,not wrap

+	hwp_timer->OSTimer_Ctrl |= TIMER_AP_REPEAT;

+	hwp_timer->OSTimer_Ctrl &= (~TIMER_AP_WRAP);

+	// write initial value

+	temp = caculate_tick_val(period);

+	load_tick_l = 0xFFFFFFFF & (temp);

+#ifdef USE_DATA_SIZE_64_BIT

+	load_tick_h = 0xFFFFFF & (temp >> 32);

+#else

+	load_tick_h = 0x0;

+#endif

+	hwp_timer->OSTimer_LoadVal_L = load_tick_l;

+	hwp_timer->OSTimer_Ctrl &= (~TIMER_AP_OS_LOADVAL_H_MASK);

+	hwp_timer->OSTimer_Ctrl |= load_tick_h;

+	// load to initial value

+	hwp_timer->OSTimer_Ctrl |= TIMER_AP_LOAD;

+	// clear irq status

+	ostimer_clear_irq();

+	// set mask

+	hwp_timer->Timer_Irq_Mask_Set = TIMER_AP_OSTIMER_MASK;

+	// print value for debug

+	d_printf("OSTimer_Ctrl:       0x%x\n",hwp_timer->OSTimer_Ctrl);

+	d_printf("OSTimer_LoadVal_L:  0x%x\n",hwp_timer->OSTimer_LoadVal_L);

+	d_printf("Timer_Irq_Mask_Set: 0x%x\n",hwp_timer->Timer_Irq_Mask_Set);

+	d_printf("Timer_Irq_Mask_Clr: 0x%x\n",hwp_timer->Timer_Irq_Mask_Clr);

+	d_printf("Timer_Irq_Cause:    0x%x\n",hwp_timer->Timer_Irq_Cause);

+	d_printf("OSTimer_LockVal_H:  0x%x\n",hwp_timer->OSTimer_LockVal_H);

+	d_printf("OSTimer_LockVal_L:  0x%x\n",hwp_timer->OSTimer_LockVal_L);

+	d_printf("\n");

+	d_printf("Enable timer...\n");

+	d_printf("Waiting for interrupt occuring...\n");

+	ostimer_enable(1);

+	get_hwtimer_time(&timer_a);

+	// waiting for irq cause state

+	irq_cnt = 0;

+	while(1) {

+		if(hwp_timer->Timer_Irq_Cause & TIMER_AP_OSTIMER_CAUSE) {

+			d_printf(".");

+			ostimer_clear_irq();

+			irq_cnt++;

+		}

+		if(irq_cnt >= irq_times) {

+			get_hwtimer_time(&timer_b);

+			break;

+		}

+	}

+	real_period = caculate_time_val((timer_b.fields.timer_l - timer_a.fields.timer_l)) / irq_times;

+	err_period = (real_period > period) ? (real_period - period):(period - real_period);

+	err_percent = (err_period * 100) / period;

+	if(err_percent <= max_err_percent)

+		ok = 1;

+	else

+		ok = 0;

+	// disable timer

+	ostimer_enable(0);

+	// clear irq status

+	ostimer_clear_irq();

+	d_printf("\n");

+	d_printf("Expected period: 0x%x\n",period);

+	d_printf("Real period:     0x%x\n",real_period);

+	d_printf("Error value:     0x%x\n",err_period);

+	d_printf("Error percent:   0x%x\n",err_percent);

+	d_printf("\n");

+	if(ok) {

+		d_printf("\nerror %d is less than %d,test success !!!\n"

+				,err_percent,max_err_percent);

+		return 0;

+	} else {

+		d_printf("\nerr %d is greater than %d,test failed ###\n"

+				,err_percent,max_err_percent);

+		return -1;

+	}

+}

+

+/******************************************************************************

+ * @name:	    ostimer_wrap_irq

+ * @description:    to generate irq status when os timer work at wrap mode

+ * @parameter:

+ *		tick: 	   the initial value of ostimer starts

+ *		irq_times: the irq occuring times when ostimer is running.

+ * @notes:

+ * @return: 0(SUCCESS), -1(FAILED)

+ ******************************************************************************

+ */

+

+int ostimer_wrap_irq(u64 tick, int irq_times)

+{

+	u32 load_tick_h,load_tick_l;

+	int irq_cnt = 0,print_cnt = 0;

+	u32 tick_val_h,tick_val_l;

+	u32 tick_val_hh,tick_val_ll;

+

+	print_cnt = print_cnt;

+	d_printf("\nOSTimer wrap irq starts\n");

+	// disable timer

+	ostimer_enable(0);

+	// wrap mode,not repeat

+	hwp_timer->OSTimer_Ctrl |= TIMER_AP_WRAP;

+	hwp_timer->OSTimer_Ctrl &= (~TIMER_AP_REPEAT);

+	// write initial value

+	load_tick_l = 0xFFFFFFFF & tick;

+#ifdef USE_DATA_SIZE_64_BIT

+	load_tick_h = 0xFFFFFF & (tick >> 32);

+#else

+	load_tick_h = 0x0;

+#endif

+	hwp_timer->OSTimer_LoadVal_L = load_tick_l;

+	hwp_timer->OSTimer_Ctrl &= (~TIMER_AP_OS_LOADVAL_H_MASK);

+	hwp_timer->OSTimer_Ctrl |= load_tick_h;

+	// load to initial value

+	hwp_timer->OSTimer_Ctrl |= TIMER_AP_LOAD;

+	// clear irq status

+	ostimer_clear_irq();

+	// set mask

+	hwp_timer->Timer_Irq_Mask_Set = TIMER_AP_OSTIMER_MASK;

+	// print value for debug

+	d_printf("OSTimer_Ctrl:       0x%x\n",hwp_timer->OSTimer_Ctrl);

+	d_printf("OSTimer_LoadVal_L:  0x%x\n",hwp_timer->OSTimer_LoadVal_L);

+	d_printf("Timer_Irq_Mask_Set: 0x%x\n",hwp_timer->Timer_Irq_Mask_Set);

+	d_printf("Timer_Irq_Mask_Clr: 0x%x\n",hwp_timer->Timer_Irq_Mask_Clr);

+	d_printf("Timer_Irq_Cause:    0x%x\n",hwp_timer->Timer_Irq_Cause);

+	d_printf("OSTimer_LockVal_H:  0x%x\n",hwp_timer->OSTimer_LockVal_H);

+	d_printf("OSTimer_LockVal_L:  0x%x\n",hwp_timer->OSTimer_LockVal_L);

+	d_printf("\n");

+	d_printf("Enable timer...\n");

+	d_printf("Waiting for interrupt occuring...\n");

+	// enable  timer

+	ostimer_enable(1);

+	// waiting for irq cause state

+	irq_cnt = 0;

+	while(1) {

+		if(hwp_timer->Timer_Irq_Cause & TIMER_AP_OSTIMER_CAUSE) {

+			// clear irq status

+			ostimer_clear_irq();

+			irq_cnt++;

+		}

+		if(irq_cnt >= irq_times) {

+			// delay sometime, then to check lock value which should be the maximum value

+			//hwt_delay_us(1000);

+			tick_val_hh = hwp_timer->OSTimer_LockVal_H;

+			tick_val_ll = hwp_timer->OSTimer_LockVal_L;

+			break;

+		}

+	}

+	hwt_delay_us(10);

+	tick_val_h = hwp_timer->OSTimer_LockVal_H;

+	tick_val_l = hwp_timer->OSTimer_LockVal_L;

+	// disable timer

+	ostimer_enable(0);

+	// clear irq status

+	ostimer_clear_irq();

+	d_printf("OSTimer_LockVal_HH: 0x%x\n",tick_val_hh);

+	d_printf("OSTimer_LockVal_LL: 0x%x\n",tick_val_ll);

+	d_printf("OSTimer_LockVal_H: 0x%x\n",tick_val_h);

+	d_printf("OSTimer_LockVal_L: 0x%x\n",tick_val_l);

+	if(tick_val_h == 0xFFFFFFFF) {

+		d_printf("\nOSTimer wrap irq test success !!!\n");

+		return 0;

+	} else {

+		d_printf("\nOSTimer wrap irq test failed ###\n");

+		return -1;

+	}

+}

+

+/******************************************************************************

+ * @name:	    ostimer_lock_value

+ * @description:    to check lock function if worked when counter's value is

+ *		    changing.

+ * @parameter:

+ *		tick: 	   the initial value of ostimer starts

+ * @notes:

+ * @return: 0(SUCCESS), -1(FAILED)

+ ******************************************************************************

+ */

+

+int ostimer_lock_value(void)

+{

+	int ok = 0;

+	u32 read_val_h,read_val_l;

+	u32 val_h,val_l;

+

+	d_printf("\nOSTimer lock value test starts\n");

+	ostimer_enable(0);

+	// wrap mode,not repeat mode

+	hwp_timer->OSTimer_Ctrl |= TIMER_AP_WRAP;

+	hwp_timer->OSTimer_Ctrl &= (~TIMER_AP_REPEAT);

+	// write load value

+	val_h = 0x00000001;

+	val_l = 0x00000000;

+	hwp_timer->OSTimer_LoadVal_L = TIMER_AP_OS_LOADVAL_L(val_l);

+	hwp_timer->OSTimer_Ctrl &= ~(TIMER_AP_OS_LOADVAL_H_MASK);

+	hwp_timer->OSTimer_Ctrl |= TIMER_AP_OS_LOADVAL_H(val_h);

+	// load to initial value

+	hwp_timer->OSTimer_Ctrl |= TIMER_AP_LOAD;

+	// clear irq status

+	ostimer_clear_irq();

+	// set mask

+	hwp_timer->Timer_Irq_Mask_Set = TIMER_AP_OSTIMER_MASK;

+	d_printf("Waiting for jitter occur...\n");

+	// enable timer

+	ostimer_enable(1);

+	while(1) {

+			read_val_h = hwp_timer->OSTimer_LockVal_H;

+			read_val_l = hwp_timer->OSTimer_LockVal_L;

+			if(read_val_h == 0)

+				break;

+	}

+	// disable timer

+	ostimer_enable(0);

+	// clear irq status

+	ostimer_clear_irq();

+	/* When jitter occur,	read_val_h = 0x00000001,read_val_l = 0x00000000

+		if okay,	read_val_h = 0x00000000,read_val_l = 0xFFFFFFFF

+		if error,	read_val_h = 0x00000000,read_val_l = 0x00000000

+	*/

+	if((read_val_l & 0xFFFFFF00) == 0xFFFFFF00)

+		ok = 1;

+	else

+		ok = 0;

+	// read value

+	d_printf("Last lock value h: 0x%x\n",read_val_h);

+	d_printf("Last lock value l: 0x%x\n",read_val_l);

+	if(ok) {

+		d_printf("OSTimer lock value test success!!!\n");

+		return 0;

+	} else {

+		d_printf("OSTimer lock value test failed ###\n");

+		return -1;

+	}

+}

+

+int timer_simple_test_in(unsigned int period)

+{

+	int cnt = 0;

+	d_printf("print message with period %d ms\n",(int)period);

+	do {

+		hwt_delay_ms(period); // delay one second

+		d_printf("Hello world,0x%x\n",cnt);

+		cnt++;

+	}while(cnt<5);

+	d_printf("test finished\n");

+	return 0;

+}

+

+/*

+ * TIMER FULL TEST

+ *********************************************************

+ */

+int timer_full_test_in(int timer_id, enum TIMER_TC_ID_TYPE case_id)

+{

+	int ret = 0;

+	// reset timer

+	timer_reset();

+	hwt_delay_us(10);

+

+	switch(case_id) {

+	case HWTIMER_TC_ID_REG_DEFAULT_VAL:

+		ret = hwtimer_reg_default_value(1);

+		break;

+	case HWTIMER_TC_ID_DELAY_US:

+		//ret  = hwtimer_delay_us(61);

+		//ret += hwtimer_delay_us(610);

+		ret += hwtimer_delay_us(1000);

+		break;

+	case HWTIMER_TC_ID_DELAY_MS:

+		ret  = hwtimer_delay_ms(50);

+		ret += hwtimer_delay_ms(100);

+		ret += hwtimer_delay_ms(1000);

+		break;

+	case HWTIMER_TC_ID_DELAY_S:

+		ret  = hwtimer_delay_s(1);

+		ret += hwtimer_delay_s(2);

+		break;

+	case HWTIMER_TC_ID_DELAY_WAVE_1MS:

+		// output 10000 wave which period is 1000 us,

+		ret = hwtimer_delay_wave(1000,10000);

+		break;

+	case HWTIMER_TC_ID_INTERVAL_IRQ_125MS:

+		ret  = hwtimer_interval_irq(IT_PERIOD_125MS,4);

+		break;

+	case HWTIMER_TC_ID_INTERVAL_IRQ_250MS:

+		ret = hwtimer_interval_irq(IT_PERIOD_250MS,4);

+		break;

+	case HWTIMER_TC_ID_INTERVAL_IRQ_500MS:

+		ret = hwtimer_interval_irq(IT_PERIOD_500MS,2);

+		break;

+	case HWTIMER_TC_ID_INTERVAL_IRQ_1000MS:

+		ret = hwtimer_interval_irq(IT_PERIOD_1000MS,2);

+		break;

+	case HWTIMER_TC_ID_IRQ_WAVE_125MS:

+		ret = hwtimer_interval_irq_wave(IT_PERIOD_125MS,80);

+		break;

+	case HWTIMER_TC_ID_IRQ_WAVE_250MS:

+		ret = hwtimer_interval_irq_wave(IT_PERIOD_250MS,40);

+		break;

+	case HWTIMER_TC_ID_IRQ_WAVE_500MS:

+		ret = hwtimer_interval_irq_wave(IT_PERIOD_500MS,20);

+		break;

+	case HWTIMER_TC_ID_IRQ_WAVE_1000MS:

+		ret = hwtimer_interval_irq_wave(IT_PERIOD_1000MS,10);

+		break;

+	case HWTIMER_TC_ID_WRAP_IRQ:

+		ret = hwtimer_wrap_irq(1);//test only once

+		break;

+	case HWTIMER_TC_ID_LOCK_VAL:

+		ret = hwtimer_lock_value();

+		break;

+	case OSTIMER_TC_ID_REG_DEFAULT_VAL:

+		ret = ostimer_reg_default_value(1);

+		break;

+	case OSTIMER_TC_ID_DELAY_US:

+		ret = ostimer_delay_us(500); // delay 500 us

+		break;

+	case OSTIMER_TC_ID_DELAY_MS:

+		ret = ostimer_delay_ms(5); // delay 500 ms

+		break;

+	case OSTIMER_TC_ID_DELAY_WAVE_1MS:

+		ret = ostimer_delay_wave(1000,10000);

+		break;

+	case OSTIMER_TC_ID_TEST_IRQ_STATUS:

+		ret = ostimer_test_irq_status(500); // delay 500 us for checking irq status and irq cause

+		break;

+	case OSTIMER_TC_ID_IRQ_REPEAT:

+		ret = ostimer_repeat_irq(10000,10); // period = 10 ms, 10 times

+		break;

+	case OSTIMER_TC_ID_IRQ_WRAP:

+		ret = ostimer_wrap_irq(0x1000,1); //initial tick = 0x1000, test only once

+		break;

+	case OSTIMER_TC_ID_LOCK_VAL:

+		ret = ostimer_lock_value();

+		break;

+	default:

+		d_printf("Test case is not found\n");

+		ret = -1;

+		break;

+	}

+	return ret;

+}

+

+void config_clock_source(void)

+{

+	char ch;

+	while(1) {

+		d_printf("\nSelect TIMER clock source\n"

+			"\t 1: 2MHz clock source\n"

+			"\t 2: 16KHz clock source\n"

+			"\t q: exit\n");

+		ch = serial_getc();

+		if(ch == 'q') {

+			d_printf("Exit configuration\n");

+			return;

+		}

+		d_printf("Input cmd: ");

+		serial_putc(ch);

+		d_printf("\n");

+		switch(ch) {

+		case '1':

+			set_timer_clk_freq(1);

+			d_printf("Set 2MHz clock source OK\n");

+			break;

+		case '2':

+			set_timer_clk_freq(0);

+			d_printf("Set 16KHz clock source OK\n");

+			break;

+		default:

+			d_printf("Invalid cmd\n");

+			break;

+		}

+	}

+}

+

+void timer_single_test_in(int timer_id)

+{

+	char choice;

+	int case_id = 0xff;

+	d_printf("**************************************************************"

+		"\n\tThis program is used to output wave from GPO 0\n"

+		"\tAll waves are generated by HWTimer and OSTimer\n"

+		"*************************************************************");

+	while(1) {

+		d_printf("\nInput your choice:\n"

+			"\t1: wave period 1 ms by hwtimer\n"

+			"\t2: wave period 250ms\n"

+			"\t3: wave period 500ms\n"

+			"\t4: wave period 1000ms\n"

+			"\t5: wave period 2000ms\n"

+			"\t6: wave period 1 ms by ostimer\n"

+			"\tq: exit\n");

+		choice = serial_getc();

+		if(choice == 'q') {

+			d_printf("Have a nice day !\n");

+			return;

+		}

+		d_printf("Input cmd: ");

+		serial_putc(choice);

+		d_printf("\n");

+		switch(choice) {

+			case '1': case_id = HWTIMER_TC_ID_DELAY_WAVE_1MS;break;

+			case '2': case_id = HWTIMER_TC_ID_IRQ_WAVE_125MS;break;

+			case '3': case_id = HWTIMER_TC_ID_IRQ_WAVE_250MS;break;

+			case '4': case_id = HWTIMER_TC_ID_IRQ_WAVE_500MS;break;

+			case '5': case_id = HWTIMER_TC_ID_IRQ_WAVE_1000MS;break;

+			case '6': case_id = OSTIMER_TC_ID_DELAY_WAVE_1MS;break;

+			default: d_printf("\nInvalied input\n"); case_id = 0xFF;break;

+		}

+		if(case_id != 0xFF)

+			timer_full_test_in(timer_id, case_id);

+	}

+}

+

+#ifdef CONFIG_IRQ

+int start_ostimer(u32 us)

+{

+	u64 temp;

+	u32 load_tick_h,load_tick_l;

+

+	d_printf("OSTimer runs at repeat irq mode,period is %d us\n",us);

+	// disable timer

+	ostimer_enable(0);

+	// repeat mode,not wrap

+	hwp_timer->OSTimer_Ctrl &= (~TIMER_AP_WRAP);

+	hwp_timer->OSTimer_Ctrl |= TIMER_AP_REPEAT;

+	// write initial value

+	temp = caculate_tick_val(us);

+	load_tick_l = 0xFFFFFFFF & temp;

+#ifdef USE_DATA_SIZE_64_BIT

+	load_tick_h = 0xFFFFFF & (temp >> 32);

+#else

+	load_tick_h = 0;

+#endif

+	hwp_timer->OSTimer_LoadVal_L = load_tick_l;

+	hwp_timer->OSTimer_Ctrl &= (~TIMER_AP_OS_LOADVAL_H_MASK);

+	hwp_timer->OSTimer_Ctrl |= load_tick_h;

+	// load to initial value

+	hwp_timer->OSTimer_Ctrl |= TIMER_AP_LOAD;

+	// clear irq status

+	ostimer_clear_irq();

+	// set mask

+	hwp_timer->Timer_Irq_Mask_Set |= TIMER_AP_OSTIMER_MASK;

+	// print value for debug

+#if 0

+	d_printf("OSTimer_Ctrl:       0x%x\n",hwp_timer->OSTimer_Ctrl);

+	d_printf("OSTimer_LoadVal_L:  0x%x\n",hwp_timer->OSTimer_LoadVal_L);

+	d_printf("Timer_Irq_Mask_Set: 0x%x\n",hwp_timer->Timer_Irq_Mask_Set);

+	d_printf("Timer_Irq_Mask_Clr: 0x%x\n",hwp_timer->Timer_Irq_Mask_Clr);

+	d_printf("Timer_Irq_Cause:    0x%x\n",hwp_timer->Timer_Irq_Cause);

+	d_printf("OSTimer_LockVal_H:  0x%x\n",hwp_timer->OSTimer_LockVal_H);

+	d_printf("OSTimer_LockVal_L:  0x%x\n",hwp_timer->OSTimer_LockVal_L);

+	d_printf("\n");

+	d_printf("Enable timer ...\n");

+	d_printf("Waiting for interrupt occuring ...\n");

+#endif

+	d_printf("waiting for irq occuring ...\n");

+	ostimer_enable(1);

+	return 0;

+}

+

+int stop_ostimer(void)

+{

+	ostimer_enable(0);

+//	timer_reset();

+	return 0;

+}

+

+static volatile int ostimer_cb_tick = 0;

+void ostimer_callback(void)

+{

+	d_printf("ostimer tick is %d\n",++ostimer_cb_tick);

+	//clear OSTimer irq status

+	ostimer_clear_irq();

+}

+

+void ostimer_interrupt_test(int count)

+{

+	/* handler OSTIMER pointer */

+	hwp_timer = hwp_apTimer;

+	/* to stop timer firstly */

+	stop_ostimer();

+	/* request a irq for OSTIMER */

+	irq_request(RDA_IRQ_TIMEROS,ostimer_callback);

+	/* enable interrupt */

+	irq_unmask(RDA_IRQ_TIMEROS);

+	/* clear callback tick value */

+	ostimer_cb_tick = 0;

+	/* start OSTIMER and set IRQs period is 1 second */

+	start_ostimer(1000000);

+	d_printf("waiting ...\n");

+	while(1) {

+		if(ostimer_cb_tick > count) {

+			d_printf("stop\n");

+			stop_ostimer();

+			irq_mask(RDA_IRQ_TIMEROS);

+			irq_free(RDA_IRQ_TIMEROS);

+			break;

+		}

+//		d_printf(".");

+	}

+	d_printf("ostimer irq test finished \n");

+}

+#endif /* CONFIG_IRQ */

+

+/*

+ * TIMER TEST ENTRY

+ *********************************************************

+ */

+int timer_test_entry(int timer_id)

+{

+	int ret = 0;

+

+	if(timer_id > 2) {

+		d_printf("handle timer failed,timer id is %d\n",timer_id);

+		return -1;

+	}

+	hwp_timer = hwp_timer_tab[timer_id];

+	if(hwp_timer == NULL) {

+		d_printf("timer do not exist,timer id is %d\n",timer_id);

+		return -1;

+	}

+	d_printf("\nstart to test timer %d ...\n",timer_id);

+/* This is used to test OSTIMER's IRQ */

+#ifdef CONFIG_IRQ

+	d_printf("interrupts test ...\n");

+	set_timer_clk_freq(1);

+	hwt_delay_ms(1000);

+	ostimer_interrupt_test(5);

+#endif

+/* simple test */

+#if 1

+	d_printf("simple test ...\n");

+	set_timer_clk_freq(1);

+	hwt_delay_ms(1000);

+	ret = timer_simple_test_in(1000);

+#endif

+/* fast mode test */

+#if 1

+	d_printf("fast mode test ... clock frequency is 2MHz\n");

+	set_timer_clk_freq(1);

+	hwt_delay_ms(1000);

+	hwt_delay_ms(1000);

+

+	ret = 0;

+	ret += timer_full_test_in(timer_id,HWTIMER_TC_ID_REG_DEFAULT_VAL);

+	ret += timer_full_test_in(timer_id,HWTIMER_TC_ID_DELAY_US);

+	ret += timer_full_test_in(timer_id,HWTIMER_TC_ID_DELAY_MS);

+	ret += timer_full_test_in(timer_id,HWTIMER_TC_ID_DELAY_S);

+

+	ret += timer_full_test_in(timer_id,HWTIMER_TC_ID_INTERVAL_IRQ_125MS);

+	ret += timer_full_test_in(timer_id,HWTIMER_TC_ID_INTERVAL_IRQ_250MS);

+	ret += timer_full_test_in(timer_id,HWTIMER_TC_ID_INTERVAL_IRQ_500MS);

+	ret += timer_full_test_in(timer_id,HWTIMER_TC_ID_INTERVAL_IRQ_1000MS);

+

+	ret += timer_full_test_in(timer_id,OSTIMER_TC_ID_REG_DEFAULT_VAL);

+	ret += timer_full_test_in(timer_id,OSTIMER_TC_ID_DELAY_US);

+	ret += timer_full_test_in(timer_id,OSTIMER_TC_ID_DELAY_MS);

+	ret += timer_full_test_in(timer_id,OSTIMER_TC_ID_TEST_IRQ_STATUS);

+	ret += timer_full_test_in(timer_id,OSTIMER_TC_ID_IRQ_REPEAT);

+	ret += timer_full_test_in(timer_id,OSTIMER_TC_ID_IRQ_WRAP);

+	ret += timer_full_test_in(timer_id,OSTIMER_TC_ID_LOCK_VAL);

+#endif

+/* slow mode test */

+#if 1

+	d_printf("slow mode test ... clock frequency is 16384Hz\n");

+	set_timer_clk_freq(0);

+	hwt_delay_ms(1000);

+	hwt_delay_ms(1000);

+

+	ret += timer_full_test_in(timer_id,HWTIMER_TC_ID_REG_DEFAULT_VAL);

+	ret += timer_full_test_in(timer_id,HWTIMER_TC_ID_DELAY_US);

+	ret += timer_full_test_in(timer_id,HWTIMER_TC_ID_DELAY_MS);

+	ret += timer_full_test_in(timer_id,HWTIMER_TC_ID_DELAY_S);

+

+/*	ret += timer_full_test_in(timer_id,HWTIMER_TC_ID_INTERVAL_IRQ_125MS);

+	ret += timer_full_test_in(timer_id,HWTIMER_TC_ID_INTERVAL_IRQ_250MS);

+	ret += timer_full_test_in(timer_id,HWTIMER_TC_ID_INTERVAL_IRQ_500MS);

+	ret += timer_full_test_in(timer_id,HWTIMER_TC_ID_INTERVAL_IRQ_1000MS);

+*/

+	ret += timer_full_test_in(timer_id,OSTIMER_TC_ID_REG_DEFAULT_VAL);

+	ret += timer_full_test_in(timer_id,OSTIMER_TC_ID_DELAY_US);

+	ret += timer_full_test_in(timer_id,OSTIMER_TC_ID_DELAY_MS);

+	ret += timer_full_test_in(timer_id,OSTIMER_TC_ID_TEST_IRQ_STATUS);

+	ret += timer_full_test_in(timer_id,OSTIMER_TC_ID_IRQ_REPEAT);

+	ret += timer_full_test_in(timer_id,OSTIMER_TC_ID_IRQ_WRAP);

+	ret += timer_full_test_in(timer_id,OSTIMER_TC_ID_LOCK_VAL);

+#endif

+/* lock & wrap test in fast mode */

+#if 0

+	d_printf("lock and wrap test ... clock frequency is 2MHz\n");

+	set_timer_clk_freq(1);

+	hwt_delay_ms(1000);

+	hwt_delay_ms(1000);

+

+	ret += timer_full_test_in(timer_id,HWTIMER_TC_ID_LOCK_VAL);

+	ret += timer_full_test_in(timer_id,HWTIMER_TC_ID_WRAP_IRQ);

+#endif

+	if(ret != 0)

+		d_printf("\nreturn value is %x, test failed !!!\n",(unsigned int)ret);

+	else

+		d_printf("\nreturn value is %x, test successful!!!\n",(unsigned int)ret);

+	hwt_delay_ms(1000);

+	hwt_delay_ms(1000);

+	d_printf("timer test finished\n\n");

+	return ret;

+}

+

+int tim_test(int timer_id,int times)

+{

+	int ret = 0,n = 0;

+	while(n < times) {

+		n++;

+		printf("\ntim_test: %d / %d\n",n,times);

+		ret += timer_test_entry(timer_id);

+		printf("\ntim_test end,ret is %d\n",ret);

+	}

+	return ret;

+}

diff --git a/board/rda/common/uart_test.c b/board/rda/common/uart_test.c
new file mode 100644
index 0000000000..5dcd73cefc
--- /dev/null
+++ b/board/rda/common/uart_test.c
@@ -0,0 +1,1110 @@
+#include <asm/arch/cs_types.h>

+#include <asm/arch/global_macros.h>

+#include <asm/arch/reg_uart.h>

+#include <asm/arch/reg_sysctrl.h>

+

+#if defined(CONFIG_MACH_RDA8850E) || defined(CONFIG_MACH_RDA8810H)

+

+/* #define CONFIG_UART_DMA_TEST */

+

+/* #define UART_BAUD_RATE_DEFAULT	115200 */

+#define UART_BAUD_RATE_DEFAULT	921600

+

+#define MARRAY_SIZE(x) (sizeof(x)/(x)[0])

+#define CONFIG_PUTS_UART_INFO

+#define CONFIG_UART_TEST_DEBUG

+

+#ifdef CONFIG_UART_TEST_DEBUG

+#define d_printf printf

+#else

+#define d_printf(...) do{}while(0)

+#endif

+

+/*

+ *Default uart perpherial configuration

+ */

+#define SER_TEST_DATA_COUNT	10

+

+#else

+#error "CONFIG_MACH_RDA8850E or CONFIG_MACH_RDA8810H is undefined !"

+#endif

+

+enum UART_PORT_ID

+{

+	UART_ID_1 = 0,

+	UART_ID_2 = 1,

+	UART_ID_3 = 2,//this port is used to print debug message

+};

+

+/* UART test case id number*/

+enum UART_TC_ID

+{

+	UART_TC_ID_POL_TRANSMIT = 0,

+	UART_TC_ID_DMA_TRANSMIT,

+	UART_TC_ID_RX_IRQ,

+	UART_TC_ID_RX_OVF_IRQ,

+	UART_TC_ID_TX_IRQ,

+	UART_TC_ID_CTS_RTS,

+	UART_TC_ID_RX_OVF_STATE,

+	UART_TC_ID_REG_DEFAULT_VALUE,

+	UART_TC_ID_TX_FIFO_DEPTH,

+	UART_TC_ID_RX_FIFO_LEVEL,

+};

+

+enum UART_TEST_STATE

+{

+	TEST_OK = 0,

+	TEST_ERROR = -1,

+};

+

+static HWP_UART_T *hwpt_uart = hwp_uart3;

+static HWP_UART_T *hwp_uart_tab[] = {hwp_uart1,hwp_uart2,hwp_uart3};

+

+static int g_uart_id = UART_ID_3;//uart3 is used

+static u8 g_uart_buf[2080];

+static int serial_baud_rate_tab[] = {

+	2400,

+	4800,

+	9600,

+	//14400,

+	19200,

+	//28800,

+	//33600,

+	38400,

+	57600,

+	115200,

+	230400,

+	460800,

+	921600,

+	//1843200,

+};

+

+/*

+ * UART PRIVATE FUNCTION DECLARATION

+ *********************************************************

+ */

+

+static int set_speed(int speed);

+static int config_frame_format(int speed, int data_bit, int parity_bit, int stop_bit);

+static void put_case_info(const char *str);

+static void clear_error_state(void);

+static int tx_is_finished(void);

+static void enable_cts_rts(int enabled);

+static int reset_uart(int id);

+static void set_irq_trigger_level(int rx_triggered,int value);

+

+/*

+ * UART FUNCTION IMPLEMENTATION

+ *********************************************************

+ */

+

+#ifdef CONFIG_UART_DMA_TEST

+

+BOOL hal_UartDmaFifoEmpty(HAL_IFC_REQUEST_ID_T requestId)

+{

+	UINT8 i;

+	BOOL fifoIsEmpty = TRUE;

+

+	/* Check the requested id is not currently already used. */

+	for (i = 0; i < SYS_IFC_STD_CHAN_NB ; i++) {

+		if (GET_BITFIELD(hwp_sysIfc->std_ch[i].control,

+				SYS_IFC_REQ_SRC) == requestId) {

+			fifoIsEmpty = hal_IfcChannelIsFifoEmpty(requestId, i);

+			return fifoIsEmpty;

+		}

+	}

+	return TRUE;

+}

+

+void hal_UartDmaResetFifoTc(HAL_IFC_REQUEST_ID_T requestId)

+{

+	UINT8 i;

+	/* Check the requested id is not currently already used. */

+	for (i = 0; i < SYS_IFC_STD_CHAN_NB ; i++) {

+		if (GET_BITFIELD(hwp_sysIfc->std_ch[i].control,

+				SYS_IFC_REQ_SRC) == requestId){

+			hwp_sysIfc->std_ch[i].tc = 0;

+			return;

+		}

+	}

+	return;

+}

+

+void hal_UartRxDmaPurgeFifo(HAL_IFC_REQUEST_ID_T requestId)

+{

+	UINT8 i;

+	for (i = 0; i < SYS_IFC_STD_CHAN_NB ; i++){

+		if (GET_BITFIELD(hwp_sysIfc->std_ch[i].control,

+				SYS_IFC_REQ_SRC) == requestId) {

+			(void)hal_IfcChannelFlush(requestId, i);

+		}

+	}

+}

+

+UINT32 hal_UartSendData(CONST UINT8* data, UINT32 length)

+{

+	UINT8  TxChannelNum = 0;

+	TxChannelNum = hal_IfcTransferStart(HAL_IFC_UART3_TX,

+						(UINT8 *)data,

+						length,

+						HAL_IFC_SIZE_8_MODE_AUTO);

+	if (HAL_UNKNOWN_CHANNEL == TxChannelNum) {

+		/* No channel available */

+		return 0;

+	} else {

+		/* all data will be send */

+		return length;

+	}

+}

+

+UINT32 hal_UartGetData(UINT8* destAddress, UINT32 length)

+{

+	UINT8  RxChannelNum = 0;

+

+	/* (Re)Start transfert, this will reset the timeout counter.

+	   Do this before clearing the mask and cause, to prevent

+	   a previous unwanted timeout interrupt to occur right between the

+	   two clears and then the restart transfert. */

+

+	RxChannelNum = hal_IfcTransferStart(HAL_IFC_UART3_RX,

+						destAddress,

+						length,

+						HAL_IFC_SIZE_8_MODE_AUTO);

+

+	/* check if we got an IFC channel */

+	if (HAL_UNKNOWN_CHANNEL == RxChannelNum) {

+		/* No channel available */

+		/* No data received */

+		return 0;

+	} else {

+		/* all data will be fetched */

+		return length;

+	}

+}

+

+void serial_dma_init(void)

+{

+	set_speed(UART_BAUD_RATE_DEFAULT);

+

+	hwpt_uart->triggers  = UART_AFC_LEVEL(1); //7 ?

+	hwpt_uart->ctrl = UART_ENABLE

+		|UART_DATA_BITS_8_BITS

+		|UART_TX_STOP_BITS_1_BIT

+		|UART_PARITY_ENABLE_NO

+		|UART_DMA_MODE_ENABLE;

+	/* Allow reception */

+	hwpt_uart->CMD_Set    = UART_RTS;

+	hwpt_uart->irq_mask   = UART_RX_DMA_DONE | UART_RX_DMA_TIMEOUT;

+}

+

+void serial_dma_puts(const UINT8 *s)

+{

+	UINT32 length = 0;

+

+	length = (UINT32)strlen((const char *)s);

+

+	/* wait until fifo is empty, to prevent overlap original data */

+	while(!hal_UartDmaFifoEmpty(HAL_IFC_UART3_TX));

+	(void)hal_UartSendData(s, length);

+}

+

+void serial_dma_gets(UINT8 *s, UINT32 length)

+{

+	if (hwpt_uart->irq_cause & UART_RX_DMA_TIMEOUT) {

+		hal_UartRxDmaPurgeFifo(HAL_IFC_UART3_RX);

+		while(!hal_UartDmaFifoEmpty(HAL_IFC_UART3_RX));

+		hwpt_uart->irq_cause |= UART_RX_DMA_TIMEOUT;

+	}

+	hal_UartDmaResetFifoTc(HAL_IFC_UART3_RX);

+	(void)hal_UartGetData(s, length);

+}

+

+void serial_dma_getc(UINT8 *s)

+{

+	serial_dma_gets(s, 1);

+}

+

+//this case will test dma mode

+// Phepherial  to Memory

+// Memory to Phepherial

+static void subtest_dma(int len)

+{

+	u8 rd_buf[50] = {0};

+	int cnt = 0;

+	cnt = cnt;

+	len = (len > 50)?(50):(len);

+

+	//check error flags

+	clear_error_state();

+

+	/* Begin to receive data by DMA (Phepherial to Memory) */

+	serial_dma_gets(rd_buf,len);

+	/* Waiting for DMA Rx done*/

+	while(!(hwpt_uart->irq_cause & UART_RX_DMA_DONE));

+	/* Clear DMA Rx done flag*/

+	hwpt_uart->irq_cause |= UART_RX_DMA_DONE;

+	/* Waiting for DMA Tx FIFO is empty*/

+	while(!hal_UartDmaFifoEmpty(HAL_IFC_UART3_TX));

+	/* Send back data by DMA (Memory to Phepherial)*/

+	hal_UartSendData(rd_buf,len);

+

+//	while(!(hwpt_uart->irq_cause & UART_TX_DMA_DONE));

+//	hwpt_uart->irq_cause |= UART_TX_DMA_DONE;

+

+	/* Waiting for all data sending finished */

+	while((hwpt_uart->status & UART_TX_ACTIVE) == 0);

+	while((hwpt_uart->status & UART_TX_ACTIVE) != 0);

+

+	/* Clear DMA Tx done flag */

+	if(hwpt_uart->irq_cause & UART_TX_DMA_DONE)

+		hwpt_uart->irq_cause |= UART_TX_DMA_DONE;

+}

+

+int uart_case_dma_transmitting(void)

+{

+	int n=0;

+	int len = SER_TEST_DATA_COUNT;

+	int speed = 0;

+	int tab_size = MARRAY_SIZE(serial_baud_rate_tab);

+

+	put_case_info("Start UART DMA transmitting\n");

+	serial_init(); //921600 8 N 1

+	set_speed(UART_BAUD_RATE_DEFAULT);

+	serial_dma_init();

+	hwpt_uart->irq_mask |=UART_TX_DMA_DONE;

+	hwpt_uart->irq_mask |=UART_RX_DMA_DONE;

+	hwpt_uart->irq_mask |=UART_RX_DMA_TIMEOUT;

+	while(1) {

+		/* Get baudrate value */

+		speed = serial_baud_rate_tab[n];

+

+		/* Begin to DMA transmitting */

+		//8 N 1

+		config_frame_format(speed,

+					HAL_UART_8_DATA_BITS,

+					HAL_UART_NO_PARITY,

+					HAL_UART_1_STOP_BIT);

+		subtest_dma(len);

+		//8 E 1

+		config_frame_format(speed,

+					HAL_UART_8_DATA_BITS,

+					HAL_UART_EVEN_PARITY,

+					HAL_UART_1_STOP_BIT);

+		subtest_dma(len);

+		//8 O 1

+		config_frame_format(speed,

+					HAL_UART_8_DATA_BITS,

+					HAL_UART_ODD_PARITY,

+					HAL_UART_1_STOP_BIT);

+		subtest_dma(len);

+		//8 N 2

+		config_frame_format(speed,

+					HAL_UART_8_DATA_BITS,

+					HAL_UART_NO_PARITY,

+					HAL_UART_2_STOP_BITS);

+		subtest_dma(len);

+		//8 E 2

+		config_frame_format(speed,

+					HAL_UART_8_DATA_BITS,

+					HAL_UART_EVEN_PARITY,

+					HAL_UART_2_STOP_BITS);

+		subtest_dma(len);

+		//8 O 2

+		config_frame_format(speed,

+					HAL_UART_8_DATA_BITS,

+					HAL_UART_ODD_PARITY,

+					HAL_UART_2_STOP_BITS);

+		subtest_dma(len);

+		//7 N 1

+		config_frame_format(speed,

+					HAL_UART_7_DATA_BITS,

+					HAL_UART_NO_PARITY,

+					HAL_UART_1_STOP_BIT);

+		subtest_dma(len);

+		//7 E 1

+		config_frame_format(speed,

+					HAL_UART_7_DATA_BITS,

+					HAL_UART_EVEN_PARITY,

+					HAL_UART_1_STOP_BIT);

+		subtest_dma(len);

+		//7 O 1

+		config_frame_format(speed,

+					HAL_UART_7_DATA_BITS,

+					HAL_UART_ODD_PARITY,

+					HAL_UART_1_STOP_BIT);

+		subtest_dma(len);

+		//7 N 2

+		config_frame_format(speed,

+					HAL_UART_7_DATA_BITS,

+					HAL_UART_NO_PARITY,

+					HAL_UART_2_STOP_BITS);

+		subtest_dma(len);

+		//7 E 2

+		config_frame_format(speed,

+					HAL_UART_7_DATA_BITS,

+					HAL_UART_EVEN_PARITY,

+					HAL_UART_2_STOP_BITS);

+		subtest_dma(len);

+		//7 O 2

+		config_frame_format(speed,

+					HAL_UART_7_DATA_BITS,

+					HAL_UART_ODD_PARITY,

+					HAL_UART_2_STOP_BITS);

+		subtest_dma(len);

+

+		/* Change speed table index */

+		n++;

+		if(n == tab_size)

+			break;

+	}

+	hwpt_uart->ctrl &= (~(UART_DMA_MODE_ENABLE));

+	hwpt_uart->irq_mask &= (~UART_TX_DMA_DONE);

+	hwpt_uart->irq_mask &=(~UART_RX_DMA_DONE);

+	hwpt_uart->irq_mask &=(~UART_RX_DMA_TIMEOUT);

+	put_case_info("Finsh UART DMA transmitting\n");

+	return 0;

+}

+#endif /* CONFIG_UART_DMA_TEST */

+

+static int set_speed(int speed)

+{

+	u32 clksrc;

+	u32 divmode;

+	u32 div;

+	u32 reg;

+

+	if (speed > 3250000 ) {

+	    speed = 3250000;

+	    hwpt_uart->ctrl &= (~UART_DIVISOR_MODE);

+	    divmode = 4;

+	}

+	else if (speed < 6342 ) {

+	    hwpt_uart->ctrl |= UART_DIVISOR_MODE;

+	    divmode = 16;

+	} else {

+	    hwpt_uart->ctrl &= (~UART_DIVISOR_MODE);

+	    divmode = 4;

+	}

+	div = (26000000 + divmode / 2 * speed) / (divmode * speed) - 2;

+	clksrc = SYS_CTRL_AP_UART_SEL_PLL_SLOW;

+	//clksrc = SYS_CTRL_AP_UART_SEL_PLL_PLL;

+	reg = hwp_sysCtrlAp->Cfg_Clk_Uart[g_uart_id];

+	reg &= (~(SYS_CTRL_AP_UART_DIVIDER_MASK));

+	reg &= (~(SYS_CTRL_AP_UART_SEL_PLL_PLL));

+	reg |= (clksrc | SYS_CTRL_AP_UART_DIVIDER(div));

+	hwp_sysCtrlAp->Cfg_Clk_Uart[g_uart_id] = reg;

+//        iowrite32(clksrc | SYS_CTRL_AP_UART_DIVIDER(div),

+//                &hwp_sysCtrlAp->Cfg_Clk_Uart[g_uart_id]);

+	return 0;

+}

+

+static int config_frame_format(int speed, int data_bit, int parity_bit,

+				int stop_bit)

+{

+	int config_err = 0;

+	u32 ctrl_reg;

+

+	ctrl_reg = hwpt_uart->ctrl;

+

+	/* Set data bit: 8, 7 */

+	ctrl_reg &= (~UART_DATA_BITS);

+	switch(data_bit) {

+	case HAL_UART_8_DATA_BITS:

+		ctrl_reg |= UART_DATA_BITS_8_BITS;

+		break;

+	case HAL_UART_7_DATA_BITS:

+		ctrl_reg |= UART_DATA_BITS_7_BITS;

+		break;

+	default:

+		config_err |= 0x01;

+		break;

+	}

+	/* Set parity bit: N, O, E */

+	ctrl_reg &= (~UART_PARITY_ENABLE);

+	switch(parity_bit) {

+	case HAL_UART_NO_PARITY:

+		ctrl_reg |= UART_PARITY_ENABLE_NO;

+		break;

+	case HAL_UART_ODD_PARITY:

+		ctrl_reg |= UART_PARITY_ENABLE_YES;

+		ctrl_reg &= (~UART_PARITY_SELECT_MARK);

+		ctrl_reg |= UART_PARITY_SELECT_ODD;

+		break;

+	case HAL_UART_EVEN_PARITY:

+		ctrl_reg |= UART_PARITY_ENABLE_YES;

+		ctrl_reg &= (~UART_PARITY_SELECT_MARK);

+		ctrl_reg |= UART_PARITY_SELECT_EVEN;

+		break;

+	default:

+		config_err |= 0x02;

+		break;

+	}

+	/* Set stop bit: 1, 2 */

+	ctrl_reg &= (~UART_TX_STOP_BITS);

+	switch(stop_bit) {

+	case HAL_UART_1_STOP_BIT:

+		ctrl_reg |= UART_TX_STOP_BITS_1_BIT;

+		break;

+	case HAL_UART_2_STOP_BITS:

+		ctrl_reg |= UART_TX_STOP_BITS_2_BITS;

+		break;

+	default:

+		config_err |= 0x04;

+		break;

+	}

+	/* Enable UART */

+	ctrl_reg |= UART_ENABLE;

+	/* Check error */

+	if(config_err > 0) {

+		d_printf("config frame format failed,error is 0x%x\n",

+				config_err);

+		return -1;

+	}

+	/* Write to register */

+	hwpt_uart->ctrl = ctrl_reg;

+	/* Set baud rate*/

+	set_speed(speed);

+	return 0;

+}

+

+static int get_rx_fifo_level(void)

+{

+	int rx_level;

+	rx_level = (hwpt_uart->status & UART_RX_FIFO_LEVEL_MASK)

+			>> UART_RX_FIFO_LEVEL_SHIFT;

+	return rx_level;

+}

+

+static int get_tx_fifo_empty_space(void)

+{

+	int tx_space;

+	tx_space = (hwpt_uart->status & UART_TX_FIFO_SPACE_MASK)

+			>> UART_TX_FIFO_SPACE_SHIFT;

+	return tx_space;

+}

+

+static int tx_fifo_all_empty(void)

+{

+	int empty_space = get_tx_fifo_empty_space();

+	return ((empty_space == UART_TX_FIFO_SIZE)?(1):(0));

+}

+

+static int tx_is_active(void)

+{

+	int state;

+	state = (hwpt_uart->status & UART_TX_ACTIVE);

+	return ((state)?(1):(0));

+}

+

+static int tx_is_finished(void)

+{

+	if((tx_fifo_all_empty()) && (!tx_is_active()))

+		return 1;//tx finished

+	else

+		return 0;//tx do not finished

+}

+

+static void clear_error_state(void)

+{

+	u32 state_reg = hwpt_uart->status;

+	u32 err_mask = UART_TX_OVERFLOW_ERR

+			| UART_RX_OVERFLOW_ERR

+			| UART_RX_PARITY_ERR

+			| UART_RX_FRAMING_ERR;

+

+	/* Check error flags */

+	if(state_reg & err_mask) {

+		//reset FIFO

+		hwpt_uart->CMD_Set |= UART_RX_FIFO_RESET;

+		hwpt_uart->CMD_Set |= UART_TX_FIFO_RESET;

+		//clear error by writing

+		hwpt_uart->status = err_mask;

+		while(1) {

+			state_reg = hwpt_uart->status;

+			if(state_reg & err_mask)

+				hwpt_uart->status = err_mask;

+		//	else

+			break;

+		}

+	}

+}

+

+static void put_case_info(const char *str)

+{

+#ifdef CONFIG_PUTS_UART_INFO

+	while(!tx_is_finished());

+	serial_init(); //8 N 1

+	set_speed(UART_BAUD_RATE_DEFAULT);

+	serial_puts(str);

+	while(!tx_is_finished());

+#endif

+}

+

+int uart_case_test_tx_fifo_depth(void)

+{

+	int tx_space = 0;

+	//delay somtime

+	while(!tx_is_finished());

+	mdelay(100);

+	//reset tx fifo

+	hwpt_uart->CMD_Set |= UART_TX_FIFO_RESET;

+	clear_error_state();

+	mdelay(1);

+	//get fifo empty space number

+	tx_space = (hwpt_uart->status & UART_TX_FIFO_SPACE_MASK)

+			>> UART_TX_FIFO_SPACE_SHIFT;

+	if(tx_space != UART_TX_FIFO_SIZE){

+		d_printf("check tx fifo size error, should be %d\n",tx_space);

+		return -1;

+	} else {

+		d_printf("uart tx fifo size is %d\n",tx_space);

+		return 0;

+	}

+}

+

+int uart_case_test_rx_fifo_level(void)

+{

+	int rx_space = 0;

+

+	while(!tx_is_finished());

+	mdelay(100);

+	hwpt_uart->CMD_Set |= UART_RX_FIFO_RESET;

+	clear_error_state();

+	mdelay(1);

+	rx_space = (hwpt_uart->status & UART_RX_FIFO_LEVEL_MASK)

+			>> UART_RX_FIFO_LEVEL_SHIFT;

+	if(rx_space != 0) {

+		d_printf("check rx fifo level error,should be %d\n",0);

+		return -1;

+	} else {

+		d_printf("uart rx fifo level is %d\n",rx_space);

+		return 0;

+	}

+}

+

+static void subtest_pol(int len)

+{

+	u8 rd_buf[50] = {0};

+	int cnt = 0;

+

+	len = (len > 50)?(50):(len);

+	/* clear error flags */

+	clear_error_state();

+	/* receive data */

+	while(1) {

+		if(cnt >= len)

+			break;

+		rd_buf[cnt] = serial_getc();

+		cnt++;

+	}

+	/* delay n us for host ready */

+	mdelay(100);

+	/* write data back */

+	cnt = 0;

+	while(1) {

+		if(cnt >= len)

+			break;

+		// Place in the TX Fifo

+    		while ((GET_BITFIELD(hwpt_uart->status, UART_TX_FIFO_SPACE)) == 0);

+		hwpt_uart->rxtx_buffer = (UINT32)(rd_buf[cnt]);

+		cnt++;

+	}

+	/* wait until tx is finished */

+	while(!tx_is_finished());

+}

+

+int uart_case_pol_transmitting(void)

+{

+	int n=0;

+	int len = SER_TEST_DATA_COUNT;

+	int speed = 0;

+	int tab_size = MARRAY_SIZE(serial_baud_rate_tab);

+

+	put_case_info("start uart polling transmitting\n");

+	while(1) {

+		/* Get baudrate value */

+		speed = serial_baud_rate_tab[n];

+

+		/* Begin to data transmitting */

+		//8 N 1

+		config_frame_format(speed,

+					HAL_UART_8_DATA_BITS,

+					HAL_UART_NO_PARITY,

+					HAL_UART_1_STOP_BIT);

+		subtest_pol(len);

+		//8 E 1

+		config_frame_format(speed,

+					HAL_UART_8_DATA_BITS,

+					HAL_UART_EVEN_PARITY,

+					HAL_UART_1_STOP_BIT);

+		subtest_pol(len);

+		//8 O 1

+		config_frame_format(speed,

+					HAL_UART_8_DATA_BITS,

+					HAL_UART_ODD_PARITY,

+					HAL_UART_1_STOP_BIT);

+		subtest_pol(len);

+		//8 N 2

+		config_frame_format(speed,

+					HAL_UART_8_DATA_BITS,

+					HAL_UART_NO_PARITY,

+					HAL_UART_2_STOP_BITS);

+		subtest_pol(len);

+		//8 E 2

+		config_frame_format(speed,

+					HAL_UART_8_DATA_BITS,

+					HAL_UART_EVEN_PARITY,

+					HAL_UART_2_STOP_BITS);

+		subtest_pol(len);

+		//8 O 2

+		config_frame_format(speed,

+					HAL_UART_8_DATA_BITS,

+					HAL_UART_ODD_PARITY,

+					HAL_UART_2_STOP_BITS);

+		subtest_pol(len);

+		//7 N 1

+		config_frame_format(speed,

+					HAL_UART_7_DATA_BITS,

+					HAL_UART_NO_PARITY,

+					HAL_UART_1_STOP_BIT);

+		subtest_pol(len);

+		//7 E 1

+		config_frame_format(speed,

+					HAL_UART_7_DATA_BITS,

+					HAL_UART_EVEN_PARITY,

+					HAL_UART_1_STOP_BIT);

+		subtest_pol(len);

+		//7 O 1

+		config_frame_format(speed,

+					HAL_UART_7_DATA_BITS,

+					HAL_UART_ODD_PARITY,

+					HAL_UART_1_STOP_BIT);

+		subtest_pol(len);

+		//7 N 2

+		config_frame_format(speed,

+					HAL_UART_7_DATA_BITS,

+					HAL_UART_NO_PARITY,

+					HAL_UART_2_STOP_BITS);

+		subtest_pol(len);

+		//7 E 2

+		config_frame_format(speed,

+					HAL_UART_7_DATA_BITS,

+					HAL_UART_EVEN_PARITY,

+					HAL_UART_2_STOP_BITS);

+		subtest_pol(len);

+		//7 O 2

+		config_frame_format(speed,

+					HAL_UART_7_DATA_BITS,

+					HAL_UART_ODD_PARITY,

+					HAL_UART_2_STOP_BITS);

+		subtest_pol(len);

+

+		/* Change baudrate table index */

+		n++;

+		if(n == tab_size)

+			break;

+	}

+	put_case_info("finished polling transmitting\n");

+	return 0;

+}

+

+static void set_irq_trigger_level(int rx_triggered,int value)

+{

+	unsigned int reg = hwpt_uart->triggers;

+

+	if(rx_triggered) {

+		reg &= ~(0x1F);//bit4~bit0

+		reg |= UART_RX_TRIGGER(value);

+	} else {

+		reg &= ~(0xF00);//bit11~bit8

+		reg |= UART_TX_TRIGGER(value);

+	}

+	hwpt_uart->triggers = reg;

+}

+

+int uart_case_test_rx_irq(int triggered_val)

+{

+	int cnt = 0,err;

+	int temp;

+

+	//waiting for tx finished

+	while(!tx_is_finished());

+	//reset uart

+	reset_uart(g_uart_id);

+	//init uart

+	serial_init();

+	set_speed(UART_BAUD_RATE_DEFAULT);

+	// set rx triggered value

+	set_irq_trigger_level(1,triggered_val);

+	//set rx irq mask

+	hwpt_uart->irq_mask |= UART_RX_DATA_AVAILABLE;

+	d_printf("input more than %d data to trigger rx interrupt\n"

+			,triggered_val);

+	//waiting for irq flag

+	while((hwpt_uart->irq_cause & 0x02) == 0);

+	//check test result

+	cnt = triggered_val + 1;

+	temp = get_rx_fifo_level();

+	if(temp == cnt) {

+		err = 0;//the rx irq should occur when Rx_FIFO > Rx_Trigger

+		d_printf("triggered rx irq at correct level %d\n",temp);

+	} else {

+		err = -1;

+		d_printf("triggered rx irq at error level %d\n",temp);

+	}

+	while(!tx_is_finished());

+	reset_uart(g_uart_id);

+	return err;

+}

+

+int uart_case_test_tx_irq(int triggered_val)

+{

+	int cnt,err,a,b,c,d;

+	int i;

+	//waiting for tx finished

+	while(!tx_is_finished());

+	//reset uart

+	reset_uart(g_uart_id);

+	//init uart

+	serial_init();

+	set_speed(UART_BAUD_RATE_DEFAULT);

+	//set tx triggered value

+	set_irq_trigger_level(0,triggered_val);

+	mdelay(5);

+	a = hwpt_uart->triggers;

+	b = get_tx_fifo_empty_space();

+

+	if((hwpt_uart->irq_cause & 0x4)) {

+		d_printf("tx irq occured without irq enabled,exit\n");

+		return -1;

+	}

+

+	//enable tx irq

+	hwpt_uart->irq_mask |= UART_TX_DATA_NEEDED;

+	//write data to tx fifo

+	for(i = 0;i < 15;i++)

+		hwpt_uart->rxtx_buffer = 0x55;

+	c = get_tx_fifo_empty_space();

+	//waiting for irq flag

+	while((hwpt_uart->irq_cause & 0x04) == 0);

+	d = get_tx_fifo_empty_space();

+	//disable tx irq

+	hwpt_uart->irq_mask &= ~UART_TX_DATA_NEEDED;

+	cnt = UART_TX_FIFO_SIZE - d;

+	//check result

+	if(cnt <= triggered_val ) {

+		err = 0;//the tx irq should occur when TX_FIFO <= TX_Trigger

+		d_printf("\ntriggered tx irq at correct level %d\n",cnt);

+	} else {

+		err = -1;

+		d_printf("\ntriggered tx irq at error level %d,level should be %d\n",

+				cnt,triggered_val);

+	}

+	d_printf("a = %x,b = %d,c = %d,d= %d\n",a,b,c,d);

+	d_printf("wait tx is finished ...\n");

+	while(!tx_is_finished());

+	// wait irq cause flag change to zero from one

+	mdelay(6);

+	reset_uart(g_uart_id);

+	return err;

+}

+

+int uart_case_test_rx_ovf_irq(void)

+{

+	int cnt,err;

+

+	while(!tx_is_finished());

+	reset_uart(g_uart_id);

+

+	serial_init();

+	set_speed(UART_BAUD_RATE_DEFAULT);

+

+	d_printf("input more than %d data to trigger rx overflow irq:\n",

+			UART_RX_FIFO_SIZE);

+	hwpt_uart->irq_mask |= UART_RX_LINE_ERR;

+	while((hwpt_uart->irq_cause & 0x10) == 0);

+

+	cnt = get_rx_fifo_level();

+	d_printf("triggered rx ovf irq correctly and rx fifo level is %d\n",

+			cnt);

+	err = 0;

+	while(!tx_is_finished());

+	reset_uart(g_uart_id);

+	return err;

+}

+

+int uart_case_test_rx_ovf_state(void)

+{

+	int cnt = 0,err;

+

+	while(!tx_is_finished());

+	reset_uart(g_uart_id);

+

+	serial_init();

+	set_speed(UART_BAUD_RATE_DEFAULT);

+	clear_error_state();

+

+	d_printf("input more than %d data to rise up rx overflow state:\n",

+			UART_RX_FIFO_SIZE);

+	/* Waiting for Rx overflow error occurring */

+	while((hwpt_uart->status & UART_RX_OVERFLOW_ERR) == 0);

+	cnt = get_rx_fifo_level();

+	clear_error_state();

+	err = 0;

+	d_printf("rise up rx ovf state correctly and rx fifo level is %d\n",

+			cnt);

+	while(!tx_is_finished());

+	reset_uart(g_uart_id);

+	return err;

+}

+

+static void enable_cts_rts(int enabled)

+{

+	hwpt_uart->ctrl &= (~UART_AUTO_FLOW_CONTROL);

+	if(enabled)

+		hwpt_uart->ctrl |= UART_AUTO_FLOW_CONTROL;

+}

+

+int uart_case_test_cts_rts(void)

+{

+	int cnt = 0;

+	int len = 2048;

+

+	serial_init();

+	set_speed(UART_BAUD_RATE_DEFAULT);

+	//LAB_TEST_BEGIN:

+	enable_cts_rts(1);

+	//Check error flags

+	clear_error_state();

+	//Receive data

+	cnt = 0;

+	while(1) {

+		if(cnt >= len)

+			break;

+		g_uart_buf[cnt] = serial_getc();

+		cnt++;

+	}

+	//Delay n us for host ready

+	mdelay(100);

+	//Write data back

+	cnt = 0;

+	while(1) {

+		if(cnt >= len)

+			break;

+		while(!(GET_BITFIELD(hwpt_uart->status,UART_TX_FIFO_SPACE)));

+		hwpt_uart->rxtx_buffer = (UINT32)g_uart_buf[cnt];

+		cnt++;

+	}

+	//Waitting for data sending end

+	while(!tx_is_finished());

+	//Disable CTS/RTS

+	enable_cts_rts(0);

+	return 0;

+}

+

+/*

+ * when program runs in DRAM, the APB2 bus should not be reset

+ * otherwise it will dead

+ */

+#if 0

+static int reset_uart(int id)

+{

+	int ret = 0;

+	if(id == UART_ID_1) {

+		hwp_sysCtrlAp->APB2_Rst_Set = SYS_CTRL_AP_SET_APB2_RST_UART1;

+		hwp_sysCtrlAp->APB2_Rst_Clr = SYS_CTRL_AP_CLR_APB2_RST_UART1;

+	} else if(id == UART_ID_2) {

+		hwp_sysCtrlAp->APB2_Rst_Set = SYS_CTRL_AP_SET_APB2_RST_UART2;

+		hwp_sysCtrlAp->APB2_Rst_Clr = SYS_CTRL_AP_CLR_APB2_RST_UART2;

+	} else if(id == UART_ID_3) {

+		hwp_sysCtrlAp->APB2_Rst_Set = SYS_CTRL_AP_SET_APB2_RST_UART3;

+		hwp_sysCtrlAp->APB2_Rst_Clr = SYS_CTRL_AP_CLR_APB2_RST_UART3;

+	} else {

+		ret = -1;

+	}

+	return ret;

+}

+#else

+static int reset_uart(int id)

+{

+	/* reset the TX FIFO,RX FIFO */

+	hwpt_uart->CMD_Set |= UART_RX_FIFO_RESET;

+	hwpt_uart->CMD_Set |= UART_TX_FIFO_RESET;

+	return 0;

+}

+#endif

+int uart_case_test_default_value(void)

+{

+	unsigned int buf[10];

+	int idx = 0;

+

+	// reset uart

+	while(!tx_is_finished());

+	reset_uart(g_uart_id);

+

+	buf[idx++] = hwpt_uart->ctrl;

+	buf[idx++] = hwpt_uart->status;

+	buf[idx++] = hwpt_uart->irq_mask;

+	buf[idx++] = hwpt_uart->irq_cause;

+	buf[idx++] = hwpt_uart->triggers;

+	buf[idx++] = hwpt_uart->CMD_Set;

+	buf[idx++] = hwpt_uart->CMD_Clr;

+	//init uart

+	serial_init();

+	set_speed(UART_BAUD_RATE_DEFAULT);

+	idx = 0;

+	d_printf("\nread register default value ...\n");

+	d_printf("ctrl:      %x\n",buf[idx++]);

+	d_printf("status:    %x\n",buf[idx++]);

+	d_printf("irq_mask:  %x\n",buf[idx++]);

+	d_printf("irq_cause: %x\n",buf[idx++]);

+	d_printf("triggers:  %x\n",buf[idx++]);

+	d_printf("CMD_Set:   %x\n",buf[idx++]);

+	d_printf("CMD_Clr:   %x\n",buf[idx++]);

+	d_printf("\n");

+	return 0;

+}

+

+int uart_simple_test_in(int port_id)

+{

+	char data,reply;

+	serial_init();

+	set_speed(UART_BAUD_RATE_DEFAULT);

+	d_printf("\n\n Start UART easy test.\n");

+	d_printf("\nThis is a simple loop-back test."

+		"\nPlease input some string,Press q to exit\n");

+	do {

+		serial_puts("Check input: ");

+

+		data = (char)serial_getc();

+

+		if(data >= 'A' && data <='Z'){

+			reply = data + 'a' - 'A';

+		}else if(data >= 'a' && data <= 'z'){

+			reply = data + 'A' - 'a';

+		}else if(data >= '0' && data <= '9'){

+			reply = '0' + ((data - '0' + 5) % 10);

+		}else{

+			reply = data;

+		}

+		serial_putc(reply);

+		serial_puts("\n");

+		if (data == 'q' || data== 'Q')

+			break;

+	}while(1);

+	d_printf("\nFinish UART easy test.\n");

+	return 0;

+}

+

+int uart_full_test_in(int port_id, int case_id)

+{

+	int ret = 0;

+

+	/* Be ready */

+	serial_init();

+	set_speed(UART_BAUD_RATE_DEFAULT);

+	d_printf("start to test uart, case id is %d\n",case_id);

+	/* Begin tests */

+	switch(case_id) {

+	case UART_TC_ID_POL_TRANSMIT:

+		ret = uart_case_pol_transmitting();

+		break;

+	case UART_TC_ID_DMA_TRANSMIT:

+#ifdef XXXDMATEST //CONFIG_UART_DMA_TEST

+		ret = uart_case_dma_transmitting();

+#else

+		ret = -1;

+#endif

+		break;

+	case UART_TC_ID_RX_IRQ:

+		ret = uart_case_test_rx_irq(0);//min value

+		ret += uart_case_test_rx_irq(1);

+		ret += uart_case_test_rx_irq(2);

+		ret += uart_case_test_rx_irq(0x1F);//max value

+		break;

+	case UART_TC_ID_TX_IRQ:

+		ret = uart_case_test_tx_irq(3);

+		ret += uart_case_test_tx_irq(4);

+		ret += uart_case_test_tx_irq(5);

+		break;

+	case UART_TC_ID_RX_OVF_IRQ:

+		ret = uart_case_test_rx_ovf_irq();

+		break;

+	case UART_TC_ID_CTS_RTS:

+		ret = uart_case_test_cts_rts();

+		break;

+	case UART_TC_ID_RX_OVF_STATE:

+		ret = uart_case_test_rx_ovf_state();

+		break;

+	case UART_TC_ID_REG_DEFAULT_VALUE:

+		ret = uart_case_test_default_value();

+		break;

+	case UART_TC_ID_TX_FIFO_DEPTH:

+		ret = uart_case_test_tx_fifo_depth();

+		break;

+	case UART_TC_ID_RX_FIFO_LEVEL:

+		ret = uart_case_test_rx_fifo_level();

+		break;

+	default:

+		d_printf("unknown case id %d\n",case_id);

+		ret =-1;

+		break;

+	}

+	/* Print test result */

+	serial_init();

+	set_speed(UART_BAUD_RATE_DEFAULT);

+	if(ret == 0)

+		d_printf("UART test successful !!!\n");

+	else

+		d_printf("UART test failed ###\n");

+	return ret;

+}

+

+/*

+ * UART EASY TEST ENTRY

+ *********************************************************

+ */

+

+int uart_test_entry(int uart_id)

+{

+	int ret = 0;

+

+	/* Handle uart port */

+	if(uart_id > 2) {

+		d_printf("handle uart failed,uart id is %d\n",uart_id);

+		return -1;

+	}

+	hwpt_uart = hwp_uart_tab[uart_id];

+	if(hwpt_uart == NULL) {

+		d_printf("uart port do not exist,uart_id is %d\n",uart_id);

+		return -1;

+	}

+	d_printf("start to test uart %d\n ...",uart_id + 1);

+	g_uart_id = uart_id;

+	/* This is a simple case */

+	ret = uart_simple_test_in(g_uart_id);

+	/* These cases do not need a tester */

+	ret += uart_full_test_in(g_uart_id,UART_TC_ID_REG_DEFAULT_VALUE);

+	ret += uart_full_test_in(g_uart_id,UART_TC_ID_RX_FIFO_LEVEL);

+	ret += uart_full_test_in(g_uart_id,UART_TC_ID_TX_FIFO_DEPTH);

+	ret += uart_full_test_in(g_uart_id,UART_TC_ID_TX_IRQ);

+	ret += uart_full_test_in(g_uart_id,UART_TC_ID_RX_IRQ);

+	ret += uart_full_test_in(g_uart_id,UART_TC_ID_RX_OVF_IRQ);

+	ret += uart_full_test_in(g_uart_id,UART_TC_ID_RX_OVF_STATE);

+	/* These cases need a tester for Tx/Rx data */

+//	ret += uart_full_test_in(g_uart_id,UART_TC_ID_POL_TRANSMIT);

+//	ret += uart_full_test_in(g_uart_id,UART_TC_ID_CTS_RTS);

+	return ret;

+}

+

+int uart_test(int uart_id,int times)

+{

+	int ret = 0,n = 0;

+	while(n < times) {

+		n++;

+		printf("\nuart_test: %d / %d\n",n,times);

+		ret += uart_test_entry(uart_id);

+		printf("\nuart_test end,ret is %d\n",ret);

+	}

+	return ret;

+}

diff --git a/board/rda/common/vpu_test.c b/board/rda/common/vpu_test.c
new file mode 100644
index 0000000000..65e9acb9ac
--- /dev/null
+++ b/board/rda/common/vpu_test.c
@@ -0,0 +1,149 @@
+#include <common.h>
+#include <asm/arch/ispi.h>
+
+//#define VPU_TEST_DEBUG
+#ifdef VPU_TEST_DEBUG
+#define debug_printf	printf
+#else
+#define debug_printf(...)	do{}while(0)
+#endif
+
+//#define DO_WRITE_RESULT_TO_SRAM
+#ifdef DO_WRITE_RESULT_TO_SRAM
+#include <asm/io.h>
+/* VPU & MD5 test result storage address */
+#define VPU_TEST_DATA_BASE	0X11C010E4
+#define VPU_TEST_RESULT_ADDR (VPU_TEST_DATA_BASE+0X00)
+#define VPU_TEST_COUNT_ADDR	(VPU_TEST_DATA_BASE+0X04)
+#define MD5_TEST_RESULT_ADDR	(VPU_TEST_DATA_BASE+0X08)
+#define MD5_TEST_COUNT_ADDR	(VPU_TEST_DATA_BASE+0X0C)
+#define VPU_MD5_TEST_RESULT_OK	0XA55A6666
+#define VPU_MD5_TEST_RESULT_ERROR	0XDEADDEAD
+#endif
+
+#ifdef CONFIG_MACH_RDA8850E
+#define PMU_VCORE_VOLTAGE_REG	(u32)0x53
+#define PMU_DDR_VOLTAGE_VAL_REG	(u32)0x2A
+#elif defined(CONFIG_MACH_RDA8810E) || defined(CONFIG_MACH_RDA8810H) || defined(CONFIG_MACH_RDA8810)
+#define PMU_VCORE_VOLTAGE_REG	(u32)0x2F
+#define PMU_DDR_VOLTAGE_VAL_REG	(u32)0x2A
+#else
+#error "define pmu vcore,ddr register address error for vpu test!"
+#endif
+
+#if defined(CONFIG_MACH_RDA8810E) || defined(CONFIG_MACH_RDA8810H) || defined(CONFIG_MACH_RDA8850E)
+#include "vpu_test_coda7l.c"
+#elif defined(CONFIG_MACH_RDA8810)
+#include "vpu_test_coda960.c"
+#else
+static int _vpu_test(int md5_check)
+{
+	return 0;
+}
+#endif
+static void sys_get_pmu_values(unsigned int *vcore_value, unsigned int *ddr_value)
+{
+	ispi_open(1);
+	*vcore_value = ispi_reg_read(PMU_VCORE_VOLTAGE_REG);
+	*ddr_value = ispi_reg_read(PMU_DDR_VOLTAGE_VAL_REG);
+	ispi_open(0);
+}
+static void sys_set_pmu_values(unsigned int vcore_value, unsigned int ddr_value)
+{
+	ispi_open(1);
+	ispi_reg_write(PMU_VCORE_VOLTAGE_REG,vcore_value);
+	ispi_reg_write(PMU_DDR_VOLTAGE_VAL_REG,ddr_value);
+	ispi_open(0);
+}
+static void sys_setup_vpu_clk(unsigned int div)
+{
+	*((unsigned long *)0x209000E8) = div;
+}
+void vpu_sta_test(int times)
+{
+	unsigned int vcore_value, ddr_value,t_vcore=0,t_ddr=0;
+	int i,ret;
+	int err_buf[3] = {0,0,0};
+
+	printf("\n%s: current ticks = %llu\n",__func__,get_ticks());
+	sys_get_pmu_values(&vcore_value, &ddr_value);
+	debug_printf("\n%s: before test: vcore_value = %#x , ddr_value = %#x\n", __func__,vcore_value,ddr_value);
+#ifdef CONFIG_MACH_RDA8850E
+	sys_set_pmu_values(0x9525, 0xba45);//vcore=9,ddr=11
+#else
+	//sys_set_pmu_values(0xb444, 0xbab5); //vcore=11, ddr=11
+	//sys_set_pmu_values(0xb444, 0xaab5); //vcore=11, ddr=10
+	//sys_set_pmu_values(0xa444, 0x9ab5); //vcore=10, ddr=9
+	//sys_set_pmu_values(0x9444, 0x9ab5); //vcore=9, ddr=9
+	//sys_set_pmu_values(0xa444, 0xaab5); //vcore=10, ddr=10
+	sys_set_pmu_values(0xa444, 0xbab5); //vcore=10, ddr=11
+#endif
+	sys_get_pmu_values(&t_vcore, &t_ddr);
+	debug_printf("\n%s: when test: vcore_value = %#x, ddr_value = %#x\n", __func__, t_vcore, t_ddr);
+	printf("\n%s: %d times, test start\n",__func__,times);
+	for(i = 1;i <= times;i++) {
+		printf("\n%s: times %d / %d\n", __func__, i, times);
+		if(i % 2 == 1) {
+			sys_setup_vpu_clk(0x16);
+		} else {
+			sys_setup_vpu_clk(0x1c);
+		}
+		ret = _vpu_test(1);
+		/*
+		 * store test result to error buffer:
+		 * err_buf[0]: md5 check error
+		 * err_buf[1]: vpu decode error
+		 * err_buf[2]: success
+		 */
+		ret += 2;
+		if((ret >= 0) && (ret <= 2)) {
+			err_buf[ret] += 1;
+		}
+		printf("\n");
+	}
+	sys_set_pmu_values(vcore_value, ddr_value);
+	printf("\n%s: current ticks = %llu\n", __func__, get_ticks());
+	printf("\n%s: end seq\n",__func__);
+	printf("\n md5 error: %d, vpu error %d, success: %d, sum: %d\n\n",
+			err_buf[0],err_buf[1],err_buf[2],times);
+
+#ifdef DO_WRITE_RESULT_TO_SRAM
+	writel(i-1,VPU_TEST_COUNT_ADDR);
+	if(err_buf[1] != 0)
+		writel(VPU_MD5_TEST_RESULT_ERROR, VPU_TEST_RESULT_ADDR);
+	else
+		writel(VPU_MD5_TEST_RESULT_OK, VPU_TEST_RESULT_ADDR);
+
+	writel(i-1,MD5_TEST_COUNT_ADDR);
+	if(err_buf[0] != 0)
+		writel(VPU_MD5_TEST_RESULT_ERROR,MD5_TEST_RESULT_ADDR);
+	else
+		writel(VPU_MD5_TEST_RESULT_OK,MD5_TEST_RESULT_ADDR);
+#endif /* DO_WRITE_RESULT_TO_SRAM */
+	sys_get_pmu_values(&t_vcore, &t_ddr);
+	debug_printf("\n%s: after test: vcore_value = %#x, ddr_value = %#x\n", __func__, t_vcore, t_ddr);
+	printf("\n%s: finish successfully\n",__func__);
+}
+
+int vpu_md5_test(int times)
+{
+	unsigned int vcore_value, ddr_value;
+	int i, ret = 0;
+	debug_printf("\n%s: current ticks = %llu\n", __func__, get_ticks());
+#if 0
+	sys_get_pmu_values(&vcore_value, &ddr_value);
+	sys_set_pmu_values(0xa444, 0xbab5); //vcore=10, ddr=11
+#endif
+	for(i=1; i<=times; i++) {
+		printf("\n%s: times %d / %d\n", __func__, i, times);
+		ret = _vpu_test(1);
+		printf("\n");
+		if(ret)
+			break;
+	}
+#if 0
+	sys_set_pmu_values(vcore_value, ddr_value);
+#endif
+	debug_printf("\n%s: current ticks = %llu\n", __func__, get_ticks());
+	return ret;
+}
diff --git a/board/rda/common/vpu_test_coda7l.c b/board/rda/common/vpu_test_coda7l.c
new file mode 100644
index 0000000000..505147f49b
--- /dev/null
+++ b/board/rda/common/vpu_test_coda7l.c
@@ -0,0 +1,584 @@
+/**********************************
+vpu test.
+ver 1.0	: for CODA7L
+It's only for normal vpu decode, the advanced functions like on-the-fly down scale and YUV422 encoder will be test in vpurun.
+2015.03.30
+
+ver 1.1
+add md5 check.
+2015.09.29
+
+sheen
+***********************************/
+
+#include "coda7l_regs.h" //sync with cnm-coda-sw-pkg within android project.
+//vpu firmware
+//Falcon 94208*2Bytes
+#include "coda7l_fw.h"  //sync with cnm-coda-sw-pkg within android project.
+
+//test video stream.
+#define FRAME_TEST_NUM	(14) //decode frmae num < bit_stream frame num.
+const unsigned int bit_stream[] =
+{
+//don't rename bitstream!!
+//#include "bs_h264_5f_720x480.txt"
+#include "freh3_h264_99f_hp_cif.txt"
+};
+//16bytes each md5 digest.
+const unsigned char yuv_md5_digest[]=
+{
+//bs_h264_5f_720x480.txt yuv md5,create by coda960 cmodel.
+//coda7l and coda960 decode yuv is same.
+//#include "bs_h264_5f_720x480.md5"
+#include "freh3_h264_30f_hp_cif_decOrder.md5"
+};
+//#include <u-boot/md5.h>
+#include "rda_md5.h"
+/*************************************************
+	configs
+**************************************************/
+//0= little endian, 1= big endian.
+#define VPU_FRAME_ENDIAN			0
+#define VPU_STREAM_ENDIAN			0
+
+#define VPU_ENABLE_BWB			0	//burst write back. wirtes output with 8 burst in linear map mode.
+#define	CBCR_INTERLEAVE			0	//[default 1 for BW checking with CnMViedo Conformance] 0 (chroma separate mode), 1 (chroma interleave mode) // if the type of tiledmap uses the kind of MB_RASTER_MAP. must set to enable CBCR_INTERLEAVE
+#define VPU_REPORT_USERDATA		0//if enabled, user data is writen to user data buffer
+#define	USE_BIT_INTERNAL_BUF	1 //enable secondary AXI for prediction data of the bit-processor.
+#define USE_IP_INTERNAL_BUF		1 //enable secondary AXI for row pixel data of IP/AC-DC.
+#define	USE_DBKY_INTERNAL_BUF	1 //enable secondary AXI for temporal luminance data of the de-blocking filter.
+#define	USE_DBKC_INTERNAL_BUF	1 //enable secondary AXI for temporal chrominance data of the de-blocking filter.
+#define	USE_OVL_INTERNAL_BUF	0 //enable secondary AXI for temporal data of the overlap filter(VC1 only)
+#define	USE_BTP_INTERNAL_BUF	0//enable secondary AXI for bit-plane data of the bit-processor(VC1 only).
+
+typedef enum {
+	INT_BIT_INIT = 0,
+	INT_BIT_SEQ_INIT = 1,
+	INT_BIT_SEQ_END = 2,
+	INT_BIT_PIC_RUN = 3,
+	INT_BIT_FRAMEBUF_SET = 4,
+	INT_BIT_ENC_HEADER = 5,
+	INT_BIT_DEC_PARA_SET = 7,
+	INT_BIT_DEC_BUF_FLUSH = 8,
+	INT_BIT_USERDATA = 9,
+	INT_BIT_DEC_MB_ROWS = 13,
+	INT_BIT_BIT_BUF_EMPTY = 14,
+	INT_BIT_BIT_BUF_FULL = 15
+}InterruptBit;
+
+//ms
+#define VPU_ENC_TIMEOUT				5000
+#define VPU_DEC_TIMEOUT				5000
+
+
+/*****************************************************
+	register and memory base address.
+******************************************************/
+//vpu reg base addr. sheen
+#define BIT_REG_BASE		0x20830000 //CODA7L 8810E
+#define BIT_REG_SIZE		0x4000
+
+//second AXI base addr.
+//80k SECOND AXI ACCCESS MEMORY ON CHIP //8810E CODA7L
+//VC1 HD decoder MAX need 0x17D00=96k
+#define	HD_SEC_AXI_BASE_ADDR	0x100000
+#define	INTERNAL_SRAM_SIZE	0x1C000 //80k
+
+//external sdram base addr. sheen
+// FIRST AXI ACCCESS SDRAM
+//#define	HD_BASE_ADDR					0x8db00000
+#define	HD_BASE_ADDR					0x88000000  //minimum reserve 128M for 32 frames 1080P
+
+// Base address of the bitstream buffer. for the whole bitstream.
+#define	HD_ADDR_BIT_STREAM				(HD_BASE_ADDR + 0x000000)
+// Size of the bitstream buffer in byte,(1M bytes)
+#define	HD_STREAM_BUF_SIZE				0x100000
+// Base address for the Falcon.h firmware image, (firmware size 94208x2)
+#define	HD_ADDR_BIT_CODE				(HD_ADDR_BIT_STREAM + HD_STREAM_BUF_SIZE)
+//bitcode buf size 260KB
+#define CODE_BUF_SIZE	  (248*1024)//for CODA7L
+// Base address for the firmware common parameters buffer.
+//1.record decode frame buf YUV addr,384= 4*3*MAX32, 2.record MvColBuf.sheen
+#define	HD_ADDR_BIT_PARA				(HD_ADDR_BIT_CODE + CODE_BUF_SIZE)
+//common parameters buffer size 10KB
+#define PARA_BUF_SIZE	 (10*1024) //CODA7L
+// Base address for the firmware common working buffer.
+#define	HD_ADDR_BIT_WORK				(HD_ADDR_BIT_PARA + PARA_BUF_SIZE)
+//common work buffer size.
+//WORK_BUF_SIZE= (512*1024) + (MAX_NUM_INSTANCE*48*1024)  + MINI_PIPP    EN_SCALER_COEFFCIENT_ARRAY_SIZE= 512k+48k+256=564k
+#define WORK_BUF_SIZE	  (564*1024) //CODA7L
+// Slice Buffer of decoder. max as frame buffer.
+#define HD_ADDR_SLICE_BUFFER			(HD_ADDR_BIT_WORK + WORK_BUF_SIZE)
+//max slice save buffer size. max 1920*1088*1.5
+#define SLICE_SAVE_SIZE				 (1920*1088*3/4)
+//SPS/PPS save buffer. Parameter Set Buffer for H.264 decoder
+#define HD_ADDR_PS_SAVE_BUFFER			(HD_ADDR_SLICE_BUFFER + SLICE_SAVE_SIZE)
+//SPS/PPS save buffer size. CODA7L 512KB.
+#define PS_SAVE_SIZE				(512*1024)
+// Base address of the DPB.yuv frame buffer.
+#define HD_ADDR_FRAME_BASE				(HD_ADDR_PS_SAVE_BUFFER	+ PS_SAVE_SIZE)
+//register yuv buf num for decode. MAX=32, sheen
+#define HD_REG_FRAME_BUF_NUM   32
+// End address of the DPB(128MB-21MB)
+//resolution is limited to 1920x1088 (1920x1088x1.75x32=112 MB frame buffer size)
+#define HD_MAX_FRAME_BASE				(HD_ADDR_FRAME_BASE + (1920*1088*7/4)*HD_REG_FRAME_BUF_NUM)
+
+
+/********second AXI addr config***********/
+//second AXI SRAM size 0x1C000 (8810 CODA7L)
+//max size for 1920x1088(120x68MB) H.264 8810 CODA7L
+//H.264 Y Deblocking FIlter buffer, size 120*128= 0x3C00 bytes
+#define HD_ADDR_SEC_AXI_DBKY  			(HD_SEC_AXI_BASE_ADDR)
+//H.264 C Deblocking FIlter buffer, size 120*128= 0x3C00 bytes
+#define HD_ADDR_SEC_AXI_DBKC			(HD_ADDR_SEC_AXI_DBKY + 0x3C00)
+//H.264 MB Information, size 120*128= 0x3C00 bytes
+#define HD_ADDR_SEC_AXI_BIT 			(HD_ADDR_SEC_AXI_DBKC + 0x3C00)
+//H.264 Intra Prediciton buffer,  size 120*64=0x1e00 bytes
+#define HD_ADDR_SEC_AXI_IP			(HD_ADDR_SEC_AXI_BIT + 0x3C00)
+//VC1 only overlap Filter, size 120*80= 0x2580 bytes
+#define HD_ADDR_SEC_AXI_OVL  			(HD_ADDR_SEC_AXI_IP + 0x1E00)
+//VC1 only BIT PLANE, size 0xF00  bytes
+#define HD_ADDR_SEC_AXI_BTP  			(HD_ADDR_SEC_AXI_OVL + 0x2580)
+//CODA7L add for motion estimation buffers, size 120*16*36+2048=0x11600 bytes. size exceed internal sram, not use it.
+#define HD_ADDR_SEC_AXI_ME  			(HD_ADDR_SEC_AXI_OVL + 0xF00)
+//CODA7L add for on-the-fly scaler
+#define HD_ADDR_SEC_AXI_SCALER
+#define HD_ADDR_SEC_AXI_BUF_END  		(HD_SEC_AXI_BASE_ADDR + INTERNAL_SRAM_SIZE)
+
+/************************************************************/
+
+//vpu registers read/write
+#define VpuWriteReg(ADDR, DATA)   *((volatile unsigned int *)(ADDR + (unsigned int)BIT_REG_BASE)) = DATA
+#define VpuReadReg(ADDR)		*((volatile unsigned int *)(ADDR + (unsigned int)BIT_REG_BASE))
+
+//directly addr read/write
+#define MREAD_WORD(ADDR)	*((volatile int *)(ADDR))
+#define MWRITE_WORD(ADDR,DATA)	*((volatile int *)(ADDR)) = DATA
+
+
+static int _vpu_test(int md5_check)
+{
+	int  i,k;
+	int  ret;
+	int  sizeX;
+	int  sizeY;
+	int  FrameBufNum = 0;
+	int  PicSize = 0;
+	int  DispFrameIdx;
+	int  DecDecFrameIdx;
+	int  DecPicType;
+	unsigned int data;
+	int  dec_num=0;
+	int  stride;
+	unsigned int  DpbLum[HD_REG_FRAME_BUF_NUM];
+	unsigned int  DpbCb[HD_REG_FRAME_BUF_NUM];
+	unsigned int  DpbCr[HD_REG_FRAME_BUF_NUM];
+	unsigned int  MvColBuf[HD_REG_FRAME_BUF_NUM];
+	int dataSize;
+	int bitStreamSize;
+	unsigned char md5Data[16];
+	// VPP_MEDIA_NODE p_node;
+
+//RE_INIT:
+	printf("%s: start\n", __func__);
+
+	//store firmware in sdram and then dma firmware to internal PMEM by vpu. sheen
+	dataSize = sizeof(bit_code) / sizeof(bit_code[0]);//94208*2
+	for (k = 0; k < dataSize; k += 4) {
+		int dataH = 0;
+		int dataL = 0;
+		dataH = (bit_code[k+0] << 16) | bit_code[k+1];
+		dataL = (bit_code[k+2] << 16) | bit_code[k+3];
+		// 64 BIT BIG Endian
+		MWRITE_WORD(HD_ADDR_BIT_CODE + k * 2, dataL);
+		MWRITE_WORD(HD_ADDR_BIT_CODE+k * 2 + 4, dataH);
+		//j=50;   // which is 338us low level
+		//while(--j);
+	}
+
+	flush_dcache_range(HD_ADDR_BIT_CODE, HD_ADDR_BIT_CODE+CODE_BUF_SIZE);
+
+	//init_vpu register
+	for(k = 0; k <(64*1024) ; k += 4)
+		MWRITE_WORD(BIT_REG_BASE + k,0);
+
+	//32bits index for buf display.
+	VpuWriteReg(BIT_FRM_DIS_FLG, 0);
+
+	// Start decoding configuration
+	VpuWriteReg(BIT_BASE + 0xffc, 0x01); // enable clk, any other value than 0xA1B2C3D4
+	VpuWriteReg(BIT_CODE_RUN, 0x0);//control bit processor
+	VpuWriteReg(BIT_INT_ENABLE, 0x0);//Disable interrupt
+
+	//load bit stream to sdram. sheen
+	dataSize = sizeof(bit_stream) / sizeof(bit_stream[0]);
+	if(dataSize > (HD_STREAM_BUF_SIZE / 4))
+		dataSize = HD_STREAM_BUF_SIZE / 4;
+	bitStreamSize = dataSize * 4;
+	for(k = 0; k < dataSize; k++) {
+		data = bit_stream[k];
+		MWRITE_WORD(HD_ADDR_BIT_STREAM + k * 4, data);
+	}
+
+	if(dataSize < (HD_STREAM_BUF_SIZE / 4)) {
+		//set 0
+		for(k = dataSize; k < (HD_STREAM_BUF_SIZE / 4); k++)
+			MWRITE_WORD(HD_ADDR_BIT_STREAM + k * 4, 0);
+	}
+
+	flush_dcache_range(HD_ADDR_BIT_STREAM, HD_ADDR_BIT_STREAM+HD_STREAM_BUF_SIZE);
+	// Download init common firmware. sheen
+	// BIT_CODE_DOWN
+	for(k = 0; k <2048; k++) {
+		data = bit_code[k];
+		VpuWriteReg(BIT_CODE_DOWN,(k << 16) | data);
+	    i=50;
+	    while(i--);
+	}
+
+	// Initialize the CODA
+	//buffer for bit processor command execution argument and return data.
+	VpuWriteReg(BIT_PARA_BUF_ADDR, HD_ADDR_BIT_PARA);
+	//buffer for firmware code.
+	VpuWriteReg(BIT_CODE_BUF_ADDR, HD_ADDR_BIT_CODE);
+	//bitstream buffer endian format,0= 64bit little endian
+	VpuWriteReg(BIT_BIT_STREAM_CTRL, 0x0);
+	//if the whole stream feeded,set bit2=1.
+	VpuWriteReg(BIT_BIT_STREAM_PARAM, 0x0);
+	//Dpb YUV buffer Endian mode:bit0=0 64bit little endian, bit2=0 CbCr separate format.
+	VpuWriteReg(BIT_FRAME_MEM_CTRL , 0x0);
+	//disable interrupt.
+	VpuWriteReg(BIT_INT_ENABLE, 0x0);
+	//7 secAxi enable bit.(disable VC1(Ovl,Btp),ME )
+	VpuWriteReg(BIT_AXI_SRAM_USE, 0x0f0f);
+	//bit processor busy flag.
+	VpuWriteReg(BIT_BUSY_FLAG, 0x1);
+	//bit processor code reset.
+	VpuWriteReg(BIT_CODE_RESET, 0x1);
+	//start vpu.
+	VpuWriteReg(BIT_CODE_RUN , 0x1);
+	while (VpuReadReg(BIT_BUSY_FLAG) == 1);
+
+	debug_printf("%s:(VPU_Init,InitializeVPU) load base code and init vpu done.CUR_PC=%x\n", __func__, VpuReadReg(BIT_CUR_PC));
+
+	//bit stream buffer read ptr.
+	VpuWriteReg(BIT_RD_PTR, HD_ADDR_BIT_STREAM);
+	//maximum is 15M, this value is for real bitstream write point position
+	VpuWriteReg(BIT_WR_PTR, HD_ADDR_BIT_STREAM+HD_STREAM_BUF_SIZE);
+	//(bs input mode) If all the streams are feeded, the value is 4 , in demo stream, all the stream is feeded, should not exceed 15M
+	VpuWriteReg(BIT_BIT_STREAM_PARAM , 4);
+	//common working buffer
+	VpuWriteReg(BIT_WORK_BUF_ADDR, HD_ADDR_BIT_WORK);
+	// wait for BIT_BUSY_FLAG = 0
+	while (VpuReadReg(BIT_BUSY_FLAG ) == 1);
+	//current bitstream read address.(512bytes increased each time)
+	data= VpuReadReg(BIT_RD_PTR);
+
+	debug_printf("%s:set bit stream buf done. BIT_RD_PTR 0x%x\n", __func__,data);
+
+	//for BIT_RUN_COMMAND: SEQ_INIT.
+	//(BIT_BASE+0x180... reuse). sheen
+	//seq Bitstream buffer SDRAM byte address.(align with mem bus width)
+	VpuWriteReg(CMD_DEC_SEQ_BB_START, HD_ADDR_BIT_STREAM);
+	//seq Bitstream buffer size in kilo bytes count
+	VpuWriteReg(CMD_DEC_SEQ_BB_SIZE, HD_STREAM_BUF_SIZE/1024);
+	//valid seq stream offset from start addr.(only valid in SEQ_INIT).
+	VpuWriteReg(CMD_DEC_SEQ_START_BYTE, 0x0);
+	//bit[1],enable display buffer reordering.(for B frame, will make delay)
+	VpuWriteReg(CMD_DEC_SEQ_OPTION, 0x2);
+	//buffer for saving sps/pps info.(parameter sets)
+	VpuWriteReg(CMD_DEC_SEQ_PS_BB_START, HD_ADDR_PS_SAVE_BUFFER);
+	//ps buffer size.
+	VpuWriteReg(CMD_DEC_SEQ_PS_BB_SIZE, PS_SAVE_SIZE/1024);
+	//support x264.
+	VpuWriteReg(CMD_DEC_SEQ_X264_MV_EN, 0x1);
+
+	// Wait until busyFlag==0
+	while (VpuReadReg(BIT_BUSY_FLAG ) == 1);   // BIT_BUSY_FLAG = 0
+
+	debug_printf("%s: seq dec set done.\n", __func__);
+
+	// set busy.
+	VpuWriteReg(BIT_BUSY_FLAG, 0x1);
+	//common work buffer.
+	VpuWriteReg(BIT_WORK_BUF_ADDR, HD_ADDR_BIT_WORK);
+	//vpu instance index.
+	VpuWriteReg(BIT_RUN_INDEX, 0x0);
+	//codec standard:0= H.264 DECODER
+	VpuWriteReg(BIT_RUN_COD_STD, 0x0);
+	//auxiliary codec standard index.(exp.when COD_STD MPEG4,0=MPEG4,1=DivX3)
+	VpuWriteReg(BIT_RUN_AUX_STD, 0x0);
+	//run vpu command. 1=SEQ_INIT,decode sps and report sequence header info.
+	VpuWriteReg(BIT_RUN_COMMAND, 0x1);
+
+	/*!!!!!!!!!!!!!!!!!!!!!!!!!!!
+	need coolwatch write BUSY_FLAG to 0 when the first time hang after power on.
+	!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/
+	// Wait until busyFlag==0
+	while (VpuReadReg(BIT_BUSY_FLAG) == 1);
+
+	//cur bitstream addr after sps decode.
+	data= VpuReadReg(BIT_RD_PTR);
+
+	debug_printf("%s:(VPU_DecGetInitialInfo) seq header init done. BIT_RD_PTR 0x%x\n", __func__,data);
+
+#if 1
+	//CONFIG IPB BUS
+	for(k = 0; k < 144; k += 4)
+		VpuWriteReg(BIT_BASE + 0x1800 + k, 0x4040);
+
+	VpuWriteReg(BIT_BASE+0x1890, 0x0);
+	VpuWriteReg(BIT_BASE+0x18a0, 0xc30);
+	VpuWriteReg(BIT_BASE+0x18a4, 0xc30);
+	VpuWriteReg(BIT_BASE+0x18a8, 0xc30);
+
+	for(k = 0; k < 9; k++)
+		VpuWriteReg(BIT_BASE + 0x18ac + 4 * k, k * 65);
+
+	VpuWriteReg(BIT_BASE+0x18d0, 0x410);
+	VpuWriteReg(BIT_BASE+0x18d4, 0x451);
+	VpuWriteReg(BIT_BASE+0x18d8, 0x820);
+	VpuWriteReg(BIT_BASE+0x18dc, 0x861);
+
+	VpuWriteReg(BIT_BASE+0x18e0, 0x8a2);
+	VpuWriteReg(BIT_BASE+0x18e4, 0x8e3);
+	VpuWriteReg(BIT_BASE+0x18e8, 0x924);
+	VpuWriteReg(BIT_BASE+0x18ec, 0x965);
+
+	VpuWriteReg(BIT_BASE+0x18f0, 0x9a6);
+	VpuWriteReg(BIT_BASE+0x18f4, 0x9e7);
+	VpuWriteReg(BIT_BASE+0x18f8, 0xa28);
+	VpuWriteReg(BIT_BASE+0x18fc, 0xa69);
+
+	VpuWriteReg(BIT_BASE+0x1900, 0xaaa);
+	VpuWriteReg(BIT_BASE+0x1904, 0xaeb);
+	VpuWriteReg(BIT_BASE+0x1908, 0xb2c);
+	VpuWriteReg(BIT_BASE+0x190c, 0xb6d);
+
+	VpuWriteReg(BIT_BASE+0x1910, 0xbae);
+	VpuWriteReg(BIT_BASE+0x1914, 0xbef);
+	VpuWriteReg(BIT_BASE+0x1918, 0xc30);
+	VpuWriteReg(BIT_BASE+0x191c, 0xc30);
+
+	VpuWriteReg(BIT_BASE+0x1920, 0xc000000);
+#endif
+
+	// Wait until busyFlag==0
+	while (VpuReadReg(BIT_BUSY_FLAG ) == 1);
+
+	// Allocate DPB to the IP
+	// seqInitStatus for DEC_SEQ_INIT, 0 error, 1 success
+	ret = VpuReadReg(RET_DEC_SEQ_SUCCESS);
+	debug_printf("%s: seqInitStatus = %d\n", __func__, ret);
+	if (ret == 1) {
+	    //bit[31:16],pic width
+		sizeX = VpuReadReg(RET_DEC_SEQ_SRC_SIZE) >> 16;
+	    //bit[15:0],pic height
+		sizeY = VpuReadReg(RET_DEC_SEQ_SRC_SIZE) & 0xffff;
+		//minimum frame buffer number to decode.
+		FrameBufNum = VpuReadReg(RET_DEC_SEQ_FRAME_NEED);
+		if(FrameBufNum > HD_REG_FRAME_BUF_NUM)
+			FrameBufNum = HD_REG_FRAME_BUF_NUM;
+		debug_printf("%s: minimal request of frame buf num= %d\n", __func__, FrameBufNum);
+		//for BIT_RUN_COMMAND: SET_FRAME_BUF
+		// Number of frames used for reference or output reodering.
+		VpuWriteReg(CMD_SET_FRAME_BUF_NUM, FrameBufNum);
+
+		stride = ((sizeX + 15) & ~15);
+		VpuWriteReg(CMD_SET_FRAME_BUF_STRIDE, stride);// 8 multiplier, resolution width
+		PicSize = stride * ((sizeY + 15) & ~15);
+		debug_printf("%s: bufStride= %d sizex = %d, sizey = %d\n", __func__, stride, sizeX, sizeY);
+
+	} else {
+		// Report Error message
+		debug_printf("%s: seq dec err!!\n", __func__);
+		return -1;
+	}
+	// Wait until busyFlag==0
+	while (VpuReadReg(BIT_BUSY_FLAG ) == 1);
+
+	VpuWriteReg(CMD_SET_FRAME_AXI_BIT_ADDR, HD_ADDR_SEC_AXI_BIT);//second AXI address,ADDR_AXI_BIT
+	VpuWriteReg(CMD_SET_FRAME_AXI_IPACDC_ADDR, HD_ADDR_SEC_AXI_IP);//second AXI address,ADDR_AXI_IP
+	VpuWriteReg(CMD_SET_FRAME_AXI_DBKY_ADDR, HD_ADDR_SEC_AXI_DBKY);//second AXI address,ADDR_AXI_DBKY
+	VpuWriteReg(CMD_SET_FRAME_AXI_DBKC_ADDR, HD_ADDR_SEC_AXI_DBKC);//second AXI address,ADDR_AXI_DBKC
+#if 0 //for VC1 only
+	VpuWriteReg(CMD_SET_FRAME_AXI_OVL_ADDR, HD_ADDR_SEC_AXI_OVL);//second AXI address,ADDR_AXI_OVL
+	VpuWriteReg(CMD_SET_FRAME_AXI_BTP_ADDR, HD_ADDR_SEC_AXI_BTP);//second AXI address,ADDR_AXI_BTP
+#else
+	VpuWriteReg(CMD_SET_FRAME_AXI_OVL_ADDR, 0); //second AXI address,ADDR_AXI_OVL
+	//VpuWriteReg(CMD_SET_FRAME_AXI_BTP_ADDR, 0); //second AXI address,ADDR_AXI_BTP
+#endif
+	//VpuWriteReg(CMD_SET_FRAME_CACHE_CONFIG, 0x7e0);//2D CACHE CONFIG
+	//buffer for saving SLICE RBSP.
+	VpuWriteReg(CMD_SET_FRAME_SLICE_BB_START, HD_ADDR_SLICE_BUFFER);
+	//SILCE RBSP buffer size in kilo bytes.
+	VpuWriteReg(CMD_SET_FRAME_SLICE_BB_SIZE, SLICE_SAVE_SIZE/1024);
+
+	while (VpuReadReg(BIT_BUSY_FLAG ) == 1);
+
+	// 4b0000: H.264 DECODER
+	// 4b0001: VC-1 DECODER
+	// 4b0010: MPEG-2 DECODER
+	// 4b0011: MPEG-4/DivX-3 DECODER
+	// 4b0100: RV DECODER
+	// 4b0101: AVS DECODER
+	// 4b1000: MJPEG DECODER
+
+	// Calculate frame buffer addresses
+	{
+	int  addrNextLuma = HD_ADDR_FRAME_BASE;
+
+	for (k=0; k < FrameBufNum; k = k + 1) {
+		DpbLum[k]	= addrNextLuma;
+		DpbCb[k]	 = DpbLum[k]   + PicSize;
+		DpbCr[k]	 = DpbCb[k]	+ PicSize/4;
+		MvColBuf[k]  = DpbCr[k]	+ PicSize/4;
+		addrNextLuma = MvColBuf[k] + PicSize/4;
+		debug_printf("dump addr yuv[%d]:0x%x size %d\n",k,DpbLum[k],PicSize*3/2 );
+	}
+
+	// registering the base addresses of created frame buffers, little endian is ok?
+	for (k=0; k < FrameBufNum; k = k + 2) {
+		MWRITE_WORD(HD_ADDR_BIT_PARA + (k*12)	  , DpbCb[k]   );
+		MWRITE_WORD(HD_ADDR_BIT_PARA + (k*12) +  4, DpbLum[k]  );
+		MWRITE_WORD(HD_ADDR_BIT_PARA + (k*12) +  8, DpbLum[k+1]);
+		MWRITE_WORD(HD_ADDR_BIT_PARA + (k*12) + 12, DpbCr[k]   );
+		MWRITE_WORD(HD_ADDR_BIT_PARA + (k*12) + 16, DpbCr[k+1] );
+		MWRITE_WORD(HD_ADDR_BIT_PARA + (k*12) + 20, DpbCb[k+1] );
+	}
+
+	//mvCol buf
+	for (k=0; k < FrameBufNum; k = k + 2) {
+		MWRITE_WORD(HD_ADDR_BIT_PARA + 384+(k*4)	 , MvColBuf[k+1]);
+		MWRITE_WORD(HD_ADDR_BIT_PARA + 384+(k*4) +  4, MvColBuf[k]);
+
+	}
+
+	flush_dcache_range(HD_ADDR_BIT_PARA, HD_ADDR_BIT_PARA+PARA_BUF_SIZE);
+
+	}
+	// set busy flag.
+	VpuWriteReg(BIT_BUSY_FLAG, 0x1);
+	VpuWriteReg(BIT_WORK_BUF_ADDR, HD_ADDR_BIT_WORK);
+	//vpu run instance index.
+	VpuWriteReg(BIT_RUN_INDEX, 0x0);
+	//codec standard index.0= H.264
+	VpuWriteReg(BIT_RUN_COD_STD, 0x0);
+	//auxiliary codec standard index.
+	VpuWriteReg(BIT_RUN_AUX_STD, 0x0);
+	//n-th bit means display buffer index.
+	VpuWriteReg(BIT_FRM_DIS_FLG, 0x0);
+	// BIT_RUN_COMMAND: SET_FRAME_BUF= 0x4
+	VpuWriteReg(BIT_RUN_COMMAND, 0x4);
+
+	// Wait until busyFlag==0
+	while (VpuReadReg(BIT_BUSY_FLAG ) == 1);
+
+	// decode processing
+	while(1) {
+		debug_printf("%s: decoding...%d\n", __func__, dec_num);
+		/*
+		if(dec_num==0 || dec_num==1){
+			for(k=0;k<0x200;k+=4)
+			debug_printf("0x%03X: 0x%08X\n",k,VpuReadReg(k));
+		}*/
+
+		//for BIT_RUN_COMMAND: PIC_RUN
+		//n-th bit means: preScan,I search,B skip,user data report...
+		VpuWriteReg(CMD_DEC_PIC_OPTION, 0x0);
+		//CMD_DEC_PIC_SKIP_NUM:the number of frame decoder skips.
+		VpuWriteReg(BIT_BASE+0x198, 0x0);
+		//rotation and mirroring.
+		VpuWriteReg(CMD_DEC_PIC_ROT_MODE, 0x0);
+		// set busy flag
+		VpuWriteReg(BIT_BUSY_FLAG, 0x1);
+		VpuWriteReg(BIT_WORK_BUF_ADDR, HD_ADDR_BIT_WORK);
+		//vpu run instance index.
+		VpuWriteReg(BIT_RUN_INDEX, 0x0);
+		//codec standard. 0= H.264
+		VpuWriteReg(BIT_RUN_COD_STD, 0x0);
+		//auxiliary codec index. H.264/AVC =0
+		VpuWriteReg(BIT_RUN_AUX_STD, 0x0);
+		// BIT_RUN_COMMAND :PIC_RUN
+		VpuWriteReg(BIT_RUN_COMMAND , 0x3);
+
+		// decode 1 frame complete
+		// Wait until busyFlag==0
+		while (VpuReadReg(BIT_BUSY_FLAG ) == 1);
+
+		// Read output information
+		// Display frame index
+		DispFrameIdx = VpuReadReg(RET_DEC_PIC_DISPLAY_IDX);
+		// Decoded frame index
+		DecDecFrameIdx = VpuReadReg(RET_DEC_PIC_DECODED_IDX);
+		//0=I,1=P,2=B
+		DecPicType = VpuReadReg(RET_DEC_PIC_TYPE) & 0xff;
+		//PIC_RUN result.0=err in header.1=ok....
+		ret= VpuReadReg(RET_DEC_PIC_SUCCESS);
+		//frame bytes size
+		PicSize= VpuReadReg(BIT_RD_PTR)-data;
+		//cur bitstream addr
+		data= VpuReadReg(BIT_RD_PTR);
+
+		debug_printf("%s:ret 0x%x type %d disIDX %d decIDX %d BIT_RD_PTR 0x%x frmSz %d\n", __func__, ret, DecPicType,DispFrameIdx, DecDecFrameIdx,data,PicSize);
+
+		if(ret != 1 || PicSize <=0){
+			debug_printf("%s: One frame dec err!\n", __func__);
+			break;
+		}
+
+		if (DispFrameIdx == -1) // -1, no output ,end of the sequence.
+		{
+			// Decode successful
+			debug_printf("%s: EOS 1.\n", __func__);
+			break;
+
+		} else if (DispFrameIdx >=0 /*DispFrameIdx != -3 && DispFrameIdx != -2*/) { // -2,-3, no display frame
+			// Host handle output picture, such as display, then clear display flag
+			// For example, if host wants to display index0 frame, the Y, CB, CR addresses are // located in DpbLum[0]), DpbCb[0], DpbCr[0];
+			//  By calling VpuWriteReg(BIT_BASE+0x150, 0x0) to clear display flag of index0 after displaying index0 frame
+			//32 bits, each bit match one frame index.sheen
+			DispFrameIdx = VpuReadReg(BIT_FRM_DIS_FLG) & (~(1<<DispFrameIdx));
+			VpuWriteReg(BIT_FRM_DIS_FLG, DispFrameIdx);
+		}
+
+		//check md5
+		if(md5_check && DecDecFrameIdx>=0){
+			flush_dcache_range(DpbLum[DecDecFrameIdx],DpbLum[DecDecFrameIdx]+sizeX*sizeY*3/2);
+			md5((unsigned char*)DpbLum[DecDecFrameIdx], sizeX*sizeY*3/2, md5Data);
+
+			debug_printf("md5 digest[0-7]=[0x%x %x %x %x %x %x %x %x]\n",md5Data[0],md5Data[1],md5Data[2],md5Data[3],md5Data[4],md5Data[5],md5Data[6],md5Data[7]);
+			debug_printf("md5 digest[8-15]=[0x%x %x %x %x %x %x %x %x]\n",md5Data[8],md5Data[9],md5Data[10],md5Data[11],md5Data[12],md5Data[13],md5Data[14],md5Data[15]);
+			for(k=0;k<16;k++){
+				if(md5Data[k]!=yuv_md5_digest[dec_num*16+k]){
+					debug_printf("md5 check fail!!!\n");
+					return -2;
+				}
+			}
+			debug_printf("md5 check pass!!!\n");
+		}
+
+
+		// copying yuv data to a file
+		// You should use your own method to output decoded frames to outside, such as using USB library.
+		dec_num++;
+
+		if(dec_num >= FRAME_TEST_NUM )
+			break;
+
+		if((data - HD_ADDR_BIT_STREAM) >= (bitStreamSize - 7)){
+			debug_printf("%s: EOS 2.\n", __func__);
+			break;
+		}
+	}
+
+	debug_printf("%s: end seq.\n", __func__);
+	VpuWriteReg(BIT_BUSY_FLAG, 0x1);// set busy.sheen
+	VpuWriteReg(BIT_RUN_COMMAND , 0x2); // BIT_RUN_COMMAND :SEQ_END
+	while (VpuReadReg(BIT_BUSY_FLAG ) == 1);	// BIT_BUSY_FLAG = 0
+
+	// You can directly output these 32 frame buffers to outside using USB driver.
+	printf("%s: test success finish.\n", __func__);
+	return 0;
+}
+
diff --git a/board/rda/common/vpu_test_coda960.c b/board/rda/common/vpu_test_coda960.c
new file mode 100644
index 0000000000..82b0b1190f
--- /dev/null
+++ b/board/rda/common/vpu_test_coda960.c
@@ -0,0 +1,570 @@
+/**********************************
+vpu test.
+modify ver 1.0	: for CODA960-8810
+2014.12.29
+modify ver 1.1
+2015.01.07
+sheen
+***********************************/
+
+#include "coda960_regs.h" //sync with cnm-coda-sw-pkg within android project.
+//vpu firmware
+#include "coda960_fw.h"
+
+//test video stream.
+#define FRAME_TEST_NUM	(14) //decode frmae num < bit_stream frame num.
+const unsigned int bit_stream[] =
+{
+//don't rename bitstream!!
+//#include "bs_h264_5f_720x480.txt"
+#include "freh3_h264_99f_hp_cif.txt"
+};
+//16bytes each md5 digest.
+const unsigned char yuv_md5_digest[]=
+{
+//bs_h264_5f_720x480.txt yuv md5,create by coda960 cmodel.
+//#include "bs_h264_5f_720x480.md5"
+#include "freh3_h264_30f_hp_cif_decOrder.md5"
+};
+//#include <u-boot/md5.h>
+#include "rda_md5.h"
+/*************************************************
+	configs
+**************************************************/
+//0= little endian, 1= big endian.
+#define VPU_FRAME_ENDIAN			0
+#define VPU_STREAM_ENDIAN			0
+
+#define VPU_ENABLE_BWB			0	//burst write back. wirtes output with 8 burst in linear map mode.
+#define	CBCR_INTERLEAVE			0	//[default 1 for BW checking with CnMViedo Conformance] 0 (chroma separate mode), 1 (chroma interleave mode) // if the type of tiledmap uses the kind of MB_RASTER_MAP. must set to enable CBCR_INTERLEAVE
+#define VPU_REPORT_USERDATA		0//if enabled, user data is writen to user data buffer
+#define	USE_BIT_INTERNAL_BUF	1 //enable secondary AXI for prediction data of the bit-processor.
+#define USE_IP_INTERNAL_BUF		1 //enable secondary AXI for row pixel data of IP/AC-DC.
+#define	USE_DBKY_INTERNAL_BUF	1 //enable secondary AXI for temporal luminance data of the de-blocking filter.
+#define	USE_DBKC_INTERNAL_BUF	1 //enable secondary AXI for temporal chrominance data of the de-blocking filter.
+#define	USE_OVL_INTERNAL_BUF	0 //enable secondary AXI for temporal data of the overlap filter(VC1 only)
+#define	USE_BTP_INTERNAL_BUF	0//enable secondary AXI for bit-plane data of the bit-processor(VC1 only).
+
+typedef enum {
+	INT_BIT_INIT = 0,
+	INT_BIT_SEQ_INIT = 1,
+	INT_BIT_SEQ_END = 2,
+	INT_BIT_PIC_RUN = 3,
+	INT_BIT_FRAMEBUF_SET = 4,
+	INT_BIT_ENC_HEADER = 5,
+	INT_BIT_DEC_PARA_SET = 7,
+	INT_BIT_DEC_BUF_FLUSH = 8,
+	INT_BIT_USERDATA = 9,
+	INT_BIT_DEC_MB_ROWS = 13,
+	INT_BIT_BIT_BUF_EMPTY = 14,
+	INT_BIT_BIT_BUF_FULL = 15
+}InterruptBit;
+
+//ms
+#define VPU_ENC_TIMEOUT				5000
+#define VPU_DEC_TIMEOUT				5000
+
+
+/*****************************************************
+	register and memory base address.
+******************************************************/
+//vpu reg base addr. sheen
+#define BIT_REG_BASE		0x20830000 //CODA960
+#define BIT_REG_SIZE		0x4000
+
+//second AXI base addr.
+// SECOND AXI ACCCESS MEMORY ON CHIP
+//#define	HD_SEC_AXI_BASE_ADDR	0x1C00000	//8810 CODA960
+#define	HD_SEC_AXI_BASE_ADDR	0x100000	//8810 CODA960
+
+//external sdram base addr. sheen
+// FIRST AXI ACCCESS SDRAM
+//#define	HD_BASE_ADDR					0x8db00000
+#define	HD_BASE_ADDR					0x88000000  //minimum reserve 128M for 32 frames 1080P
+
+// Base address of the bitstream buffer. for the whole bitstream.
+#define	HD_ADDR_BIT_STREAM				(HD_BASE_ADDR + 0x000000)
+// Size of the bitstream buffer in byte,(1M bytes)
+#define	HD_STREAM_BUF_SIZE				0x100000
+// Base address for the firmware image, (firmware size 126976x2)
+#define	HD_ADDR_BIT_CODE				(HD_ADDR_BIT_STREAM + HD_STREAM_BUF_SIZE)
+//bitcode buf size 260KB
+#define CODE_BUF_SIZE	  (260*1024)//CODA960
+// Base address for the firmware common parameters buffer.
+//1.record decode frame buf YUV addr,384= 4*3*MAX32, 2.record MvColBuf.sheen
+#define	HD_ADDR_BIT_PARA				(HD_ADDR_BIT_CODE + CODE_BUF_SIZE)
+//common parameters buffer size 10KB
+#define PARA_BUF_SIZE	 (10*1024) //CODA960
+// Base address for the firmware common working buffer.
+#define	HD_ADDR_BIT_WORK				(HD_ADDR_BIT_PARA + PARA_BUF_SIZE)
+//common work buffer size, AVC MAX= (WORK_BUF_SIZE + PS_SAVE_SIZE)=(80KB+320KB)= 400KB
+#define WORK_BUF_SIZE	  (400*1024) //CODA960
+//base address of the firmware common temp buffer.
+#define HD_ADDR_TEMP_BUF				(HD_ADDR_BIT_WORK + WORK_BUF_SIZE)
+//common temp buffer size.
+#define TEMP_BUF_SIZE	  (204*1024) //CODA960
+// Slice Buffer of decoder. max as frame buffer.
+#define HD_ADDR_SLICE_BUFFER			(HD_ADDR_TEMP_BUF + TEMP_BUF_SIZE)
+// For VP8. reuse HD_ADDR_SLICE_BUFFER
+#define HD_ADDR_VP8DEC_MB_BUF	  		HD_ADDR_SLICE_BUFFER
+// For MP4. reuse HD_ADDR_SLICE_BUFFER
+#define HD_ADDR_MP4ENC_DP_BUF	  		HD_ADDR_SLICE_BUFFER
+//max slice save buffer size. max 1920*1088*1.5
+#define SLICE_SAVE_SIZE				 (1920*1088*3/4)
+//SPS/PPS save buffer. Parameter Set Buffer for H.264 decoder
+#define HD_ADDR_PS_SAVE_BUFFER			(HD_ADDR_SLICE_BUFFER + SLICE_SAVE_SIZE)
+//SPS/PPS save buffer size. CODA960 320KB, CODA7L 512KB.
+#define HD_PS_SAVE_SIZE					0x100000
+// Base address of the DPB.yuv frame buffer.
+#define HD_ADDR_FRAME_BASE				(HD_ADDR_PS_SAVE_BUFFER	+ HD_PS_SAVE_SIZE)
+//register yuv buf num for decode. MAX=32, sheen
+#define HD_REG_FRAME_BUF_NUM   32
+// End address of the DPB(128MB-21MB)
+//resolution is limited to 1920x1088 (1920x1088x1.75x32=112 MB frame buffer size)
+#define HD_MAX_FRAME_BASE				(HD_ADDR_FRAME_BASE + (1920*1088*7/4)*HD_REG_FRAME_BUF_NUM)
+
+
+/********second AXI addr config***********/
+//second AXI SRAM size 0x10000 (8810 CODA960)
+//max size for 1920x1088(120x68MB) H.264 8810 CODA960
+//Y Deblocking FIlter buffer, size 120*128= 0x3C00 bytes
+#define HD_ADDR_SEC_AXI_DBKY  			(HD_SEC_AXI_BASE_ADDR)
+//C Deblocking FIlter buffer, size 120*128= 0x3C00 bytes
+#define HD_ADDR_SEC_AXI_DBKC			(HD_ADDR_SEC_AXI_DBKY + 0x3C00)
+//MB Information, size 120*144= 0x4380 bytes
+#define HD_ADDR_SEC_AXI_BIT 			(HD_ADDR_SEC_AXI_DBKC + 0x3C00)
+//Intra Prediciton buffer,  size 120*64=0x1e00 bytes
+#define HD_ADDR_SEC_AXI_IP			(HD_ADDR_SEC_AXI_BIT + 0x4380)
+//VC1 only overlap Filter, size 0x2580 bytes
+#define HD_ADDR_SEC_AXI_OVL  			(HD_ADDR_SEC_AXI_IP + 0x1E00)
+//VC1 only BIT PLANE, size 0xF00  bytes
+#define HD_ADDR_SEC_AXI_BTP  			(HD_ADDR_SEC_AXI_OVL + 0x2580)
+#define HD_ADDR_SEC_AXI_BUF_END  		(HD_SEC_AXI_BASE_ADDR + 0x10000)
+
+/************************************************************/
+
+//vpu registers read/write
+#define VpuWriteReg(ADDR, DATA)   *((volatile unsigned int *)(ADDR + (unsigned int)BIT_REG_BASE)) = DATA
+#define VpuReadReg(ADDR)		*((volatile unsigned int *)(ADDR + (unsigned int)BIT_REG_BASE))
+
+//directly addr read/write
+#define MREAD_WORD(ADDR)	*((volatile int *)(ADDR))
+#define MWRITE_WORD(ADDR,DATA)	*((volatile int *)(ADDR)) = DATA
+
+static int _vpu_test(int md5_check)
+{
+	int  k;
+	int  ret;
+	int  sizeX;
+	int  sizeY;
+	int  FrameBufNum = 0;
+	int  PicSize = 0;
+	int  DispFrameIdx;
+	int  DecDecFrameIdx;
+	int  DecPicType;
+	unsigned int data;
+	int  dec_num=0;
+	int  stride;
+	unsigned int  DpbLum[HD_REG_FRAME_BUF_NUM];
+	unsigned int  DpbCb[HD_REG_FRAME_BUF_NUM];
+	unsigned int  DpbCr[HD_REG_FRAME_BUF_NUM];
+	unsigned int  MvColBuf[HD_REG_FRAME_BUF_NUM];
+	int dataSize;
+	int bitStreamSize;
+	unsigned char md5Data[16];
+	// VPP_MEDIA_NODE p_node;
+
+	printf("%s: start\n", __func__);
+
+	//store firmware in sdram and then dma firmware to internal PMEM by vpu. sheen
+	dataSize = sizeof(bit_code) / sizeof(bit_code[0]);//126976
+	for (k = 0; k < dataSize; k += 4) {
+		int dataH = 0;
+		int dataL = 0;
+		dataH = (bit_code[k+0] << 16) | bit_code[k+1];
+		dataL = (bit_code[k+2] << 16) | bit_code[k+3];
+		// 64 BIT BIG Endian
+		MWRITE_WORD(HD_ADDR_BIT_CODE + k * 2, dataL);
+		MWRITE_WORD(HD_ADDR_BIT_CODE+k * 2 + 4, dataH);
+		//j=50;   // which is 338us low level
+		//while(--j);
+	}
+
+	flush_dcache_range(HD_ADDR_BIT_CODE, HD_ADDR_BIT_CODE+CODE_BUF_SIZE);
+
+	//init_vpu register
+	for(k = 0; k < 0x200; k += 4)
+		MWRITE_WORD(BIT_REG_BASE + k, 0);
+
+	VpuWriteReg(BIT_FRM_DIS_FLG, 0);//BIT_FRM_DIS_FLG
+
+	// Start decoding configuration
+	VpuWriteReg(BIT_BASE + 0xffc, 0x01); // enable clk, any other value than 0xA1B2C3D4
+	VpuWriteReg(BIT_CODE_RUN, 0x0);  // BIT_CODE_RUN
+	VpuWriteReg(BIT_INT_ENABLE, 0x0);  // BIT_INT_ENABLE, Disable interrupt
+
+	//load bit stream to sdram. sheen
+	dataSize = sizeof(bit_stream) / sizeof(bit_stream[0]);
+	if(dataSize > (HD_STREAM_BUF_SIZE / 4))
+		dataSize = HD_STREAM_BUF_SIZE / 4;
+	bitStreamSize = dataSize * 4;
+	for(k = 0; k < dataSize; k++) {
+		data = bit_stream[k];
+		MWRITE_WORD(HD_ADDR_BIT_STREAM + k * 4, data);
+	}
+
+	if(dataSize < (HD_STREAM_BUF_SIZE / 4)) {
+		//set 0
+		for(k = dataSize; k < (HD_STREAM_BUF_SIZE / 4); k++)
+			MWRITE_WORD(HD_ADDR_BIT_STREAM + k * 4, 0);
+	}
+
+	flush_dcache_range(HD_ADDR_BIT_STREAM, HD_ADDR_BIT_STREAM+HD_STREAM_BUF_SIZE);
+	// Download init common firmware. sheen
+	// BIT_CODE_DOWN
+	for(k = 0; k < 512; k += 4) {
+		data = bit_code[k];
+		VpuWriteReg(BIT_CODE_DOWN,(k << 16) | data);
+
+		data = bit_code[k+1];
+		VpuWriteReg(BIT_CODE_DOWN,((k+1) << 16) | data);
+
+		data = bit_code[k+2];
+		VpuWriteReg(BIT_CODE_DOWN,((k+2) << 16) | data);
+
+		data = bit_code[k+3];
+		VpuWriteReg(BIT_CODE_DOWN,((k+3) << 16) | data);
+	}
+
+	// Initialize the CODA
+	VpuWriteReg(BIT_PARA_BUF_ADDR, HD_ADDR_BIT_PARA);	  // BIT_PARA_BUF_ADDR
+	//VpuWriteReg(BIT_BASE+0x104, HD_ADDR_BIT_WORK);	  // BIT_WORK_BUF_ADDR
+	VpuWriteReg(BIT_CODE_BUF_ADDR, HD_ADDR_BIT_CODE);	  // BIT_CODE_BUF_ADDR
+	VpuWriteReg(BIT_BIT_STREAM_CTRL, 0x0);  					// BIT_BIT_STREAM_CTRL, 0= 64bit little endian
+	VpuWriteReg(BIT_BIT_STREAM_PARAM, 0x0);  					// BIT_BIT_STREAM_PARAM
+	//VpuWriteReg(BIT_BASE+0x110, 0x1); 					// Dpb Endian mode:1, 64bit big endian
+	VpuWriteReg(BIT_FRAME_MEM_CTRL , 0x0); 					//BIT_FRAME_MEM_CTRL Dpb Endian mode:1, 0=64bit little endian
+
+	VpuWriteReg(BIT_INT_ENABLE, 0x0); 					// BIT_INT_ENABLE
+	VpuWriteReg(BIT_AXI_SRAM_USE, 0x0f0f);  				// BIT_AXI_SRAM_USE, 6 secAxi enable bit.(disable VC1(Ovl,Btp) )
+	//VpuWriteReg(BIT_BASE+0x140, 0x78f);  				// BIT_AXI_SRAM_USE
+	VpuWriteReg(BIT_BUSY_FLAG, 0x1); 					// BIT_BUSY_FLAG= 1
+	VpuWriteReg(BIT_CODE_RESET, 0x1); 					// BIT_CODE_RESET
+	VpuWriteReg(BIT_CODE_RUN , 0x1); 					// BIT_CODE_RUN
+	while (VpuReadReg(BIT_BUSY_FLAG) == 1);   			// BIT_BUSY_FLAG = 0
+
+	debug_printf("%s:(VPU_Init,InitializeVPU) load base code and init vpu done.\n", __func__);
+
+	VpuWriteReg(BIT_TEMP_BUF_ADDR, HD_ADDR_TEMP_BUF);
+	VpuWriteReg(BIT_RD_PTR, HD_ADDR_BIT_STREAM);	 // BIT_RD_PTR_0
+	VpuWriteReg(BIT_WR_PTR, HD_ADDR_BIT_STREAM+HD_STREAM_BUF_SIZE); // BIT_WR_PTR_0, maximum is 15M, this value is for real bitstream write point position
+	VpuWriteReg(BIT_BIT_STREAM_PARAM , 4); // BIT_BIT_STREAM_PARAM (bs input mode) If all the streams are feeded, the value is 4 , in demo stream, all the stream is feeded, should not exceed 15M
+
+	VpuWriteReg(BIT_WORK_BUF_ADDR, HD_ADDR_BIT_WORK);	  // BIT_WORK_BUF_ADDR
+
+	// wait for BIT_BUSY_FLAG = 0
+	while (VpuReadReg(BIT_BUSY_FLAG ) == 1);   // BIT_BUSY_FLAG = 0
+
+	data= VpuReadReg(BIT_RD_PTR);//cur bitstream addr
+
+	debug_printf("%s:set bit stream buf done. BIT_RD_PTR 0x%x\n", __func__,data);
+
+	//VpuWriteReg(BIT_BASE+0x124, HD_ADDR_BIT_STREAM); // BIT_WR_PTR_0, maximum is 15M, this value is for real bitstream write point position
+	//VpuWriteReg(BIT_BASE+0x110, 0x1);  // Dpb Endian mode:1, 64bit little endian
+	//VpuWriteReg(BIT_BASE+0x114, 0x0);  // BIT_BIT_STREAM_PARA
+
+	//for BIT_RUN_COMMAND: SEQ_INIT. (BIT_BASE+0x180... reuse). sheen
+	VpuWriteReg(CMD_DEC_SEQ_BB_START, HD_ADDR_BIT_STREAM);//CMD_DEC_SEQ_BB_START,seq Bitstream buffer SDRAM byte address
+	VpuWriteReg(CMD_DEC_SEQ_BB_SIZE, HD_STREAM_BUF_SIZE/1024);		//CMD_DEC_SEQ_BB_SIZE, 15K, Bitstream buffer size in kilo bytes count
+	//VpuWriteReg(BIT_BASE+0x190, 0x0);// ? sheen
+	VpuWriteReg(CMD_DEC_SEQ_OPTION, 0x2);//bit[1],enable display buffer reordering.
+	//VpuWriteReg(BIT_BASE+0x194, HD_ADDR_PS_SAVE_BUFFER);// CMD_DEC_SEQ_PS_BB_START ? sheen
+	//VpuWriteReg(BIT_BASE+0x198, 0x200);							// CMD_DEC_SEQ_PS_BB_SIZE
+	//VpuWriteReg(BIT_BASE+0x198, 0x80);// CMD_DEC_SEQ_PS_BB_SIZE ? sheen
+	VpuWriteReg(CMD_DEC_SEQ_X264_MV_EN, 0x1);//support x264. sheen
+	VpuWriteReg(CMD_DEC_SEQ_SPP_CHUNK_SIZE, 512);//GBU(get bit unit) size.
+
+	//VpuWriteReg(0xA0000000+0x198, HD_ADDR_PS_SAVE_BUFFER+0x200);// CMD_DEC_SEQ_PS_BB_SIZE
+
+	// Wait until busyFlag==0
+	while (VpuReadReg(BIT_BUSY_FLAG ) == 1);   // BIT_BUSY_FLAG = 0
+
+	debug_printf("%s: seq dec set done.\n", __func__);
+
+	// CMD_DEC_SEQ_OPTION
+	VpuWriteReg(BIT_BUSY_FLAG, 0x1);// set busy.sheen
+	VpuWriteReg(BIT_WORK_BUF_ADDR, HD_ADDR_BIT_WORK);
+	VpuWriteReg(BIT_RUN_INDEX, 0x0); 		//BIT_RUN_INDEX
+	VpuWriteReg(BIT_RUN_COD_STD, 0x0); 		//BIT_RUN_COD_STD 0: H.264 DECODER
+	// Command the CODA to initialize for the sequence level
+	VpuWriteReg(BIT_RUN_AUX_STD, 0x0); 		//BIT_RUN_AUX_STD
+
+	VpuWriteReg(BIT_RUN_COMMAND, 0x1); 		//BIT_RUN_COMMAND, SEQ_INIT=1  //////////source header
+	// Wait until busyFlag==0
+	while (VpuReadReg(BIT_BUSY_FLAG) == 1);   // BIT_BUSY_FLAG = 0
+
+	data= VpuReadReg(BIT_RD_PTR);//cur bitstream addr
+
+	debug_printf("%s:(VPU_DecGetInitialInfo) seq header init done. BIT_RD_PTR 0x%x\n", __func__,data);
+
+#if 1
+	//CONFIG IPB BUS
+	for(k = 0; k < 144; k += 4)
+		VpuWriteReg(BIT_BASE + 0x1800 + k, 0x4040);
+
+	VpuWriteReg(BIT_BASE+0x1890, 0x0);
+	VpuWriteReg(BIT_BASE+0x18a0, 0xc30);
+	VpuWriteReg(BIT_BASE+0x18a4, 0xc30);
+	VpuWriteReg(BIT_BASE+0x18a8, 0xc30);
+
+	for(k = 0; k < 9; k++)
+		VpuWriteReg(BIT_BASE + 0x18ac + 4 * k, k * 65);
+
+	VpuWriteReg(BIT_BASE+0x18d0, 0x410);
+	VpuWriteReg(BIT_BASE+0x18d4, 0x451);
+	VpuWriteReg(BIT_BASE+0x18d8, 0x820);
+	VpuWriteReg(BIT_BASE+0x18dc, 0x861);
+
+	VpuWriteReg(BIT_BASE+0x18e0, 0x8a2);
+	VpuWriteReg(BIT_BASE+0x18e4, 0x8e3);
+	VpuWriteReg(BIT_BASE+0x18e8, 0x924);
+	VpuWriteReg(BIT_BASE+0x18ec, 0x965);
+
+	VpuWriteReg(BIT_BASE+0x18f0, 0x9a6);
+	VpuWriteReg(BIT_BASE+0x18f4, 0x9e7);
+	VpuWriteReg(BIT_BASE+0x18f8, 0xa28);
+	VpuWriteReg(BIT_BASE+0x18fc, 0xa69);
+
+	VpuWriteReg(BIT_BASE+0x1900, 0xaaa);
+	VpuWriteReg(BIT_BASE+0x1904, 0xaeb);
+	VpuWriteReg(BIT_BASE+0x1908, 0xb2c);
+	VpuWriteReg(BIT_BASE+0x190c, 0xb6d);
+
+	VpuWriteReg(BIT_BASE+0x1910, 0xbae);
+	VpuWriteReg(BIT_BASE+0x1914, 0xbef);
+	VpuWriteReg(BIT_BASE+0x1918, 0xc30);
+	VpuWriteReg(BIT_BASE+0x191c, 0xc30);
+
+	VpuWriteReg(BIT_BASE+0x1920, 0xc000000);
+#endif
+
+	// Wait until busyFlag==0
+	while (VpuReadReg(BIT_BUSY_FLAG ) == 1);   // BIT_BUSY_FLAG = 0
+
+	//VpuWriteReg(BIT_WORK_BUF_ADDR, HD_ADDR_BIT_WORK);  // BIT_WORK_BUF_ADDR
+
+	// Allocate DPB to the IP
+	//REG32(0x10000000) = VpuReadReg(BIT_BASE+0x1c0);   // seqInitStatus, 0 error, 1 success
+	ret = VpuReadReg(RET_DEC_SEQ_SUCCESS);   	// seqInitStatus, 0 error, 1 success
+	debug_printf("%s: seqInitStatus = %d\n", __func__, ret);
+	if (ret == 1) {
+		//REG32(0x10000004) = VpuReadReg(BIT_BASE+0x1c4);   // RET_DEC_SEQ_SRC_SIZE
+		sizeX = VpuReadReg(RET_DEC_SEQ_SRC_SIZE) >> 16; // [31:16]
+		sizeY = VpuReadReg(RET_DEC_SEQ_SRC_SIZE) & 0xffff; // [15: 0]
+		//PicSize = sizeX * sizeY;
+		//debug_printf("%s: sizex = %d, sizey = %d\n", __func__, sizeX, sizeY);
+
+		//REG32(0x10000008) = VpuReadReg(BIT_BASE+0x1cc); // Minimum decoded frame buffer need to decode stream successfully.
+		FrameBufNum = VpuReadReg(RET_DEC_SEQ_FRAME_NEED);
+		//FrameBufNum = 32; //Allocate 32 frame buffer for decoding. resolution is limited to 1920x1080 (1920x1080x1.75x32=111 MB frame buffer size)
+		if(FrameBufNum > HD_REG_FRAME_BUF_NUM)
+			FrameBufNum = HD_REG_FRAME_BUF_NUM;
+		debug_printf("%s: minimal request of frame buf num= %d\n", __func__, FrameBufNum);
+		//for BIT_RUN_COMMAND: SET_FRAME_BUF
+		VpuWriteReg(CMD_SET_FRAME_BUF_NUM, FrameBufNum); // Number of frames used for reference or output reodering.
+
+		stride = ((sizeX + 15) & ~15);
+		VpuWriteReg(CMD_SET_FRAME_BUF_STRIDE, stride);// 8 multiplier, resolution width
+		PicSize = stride * ((sizeY + 15) & ~15);
+		debug_printf("%s: bufStride= %d sizex = %d, sizey = %d\n", __func__, stride, sizeX, sizeY);
+
+	} else {
+		// Report Error message
+		debug_printf("%s: seq dec err!!\n", __func__);
+		return -1;
+	}
+	// Wait until busyFlag==0
+	while (VpuReadReg(BIT_BUSY_FLAG ) == 1);// BIT_BUSY_FLAG = 0
+
+
+	VpuWriteReg(CMD_SET_FRAME_AXI_BIT_ADDR, HD_ADDR_SEC_AXI_BIT);//second AXI address,ADDR_AXI_BIT
+	VpuWriteReg(CMD_SET_FRAME_AXI_IPACDC_ADDR, HD_ADDR_SEC_AXI_IP);//second AXI address,ADDR_AXI_IP
+	VpuWriteReg(CMD_SET_FRAME_AXI_DBKY_ADDR, HD_ADDR_SEC_AXI_DBKY);//second AXI address,ADDR_AXI_DBKY
+	VpuWriteReg(CMD_SET_FRAME_AXI_DBKC_ADDR, HD_ADDR_SEC_AXI_DBKC);//second AXI address,ADDR_AXI_DBKC
+#if 0 //for VC1 only
+	VpuWriteReg(CMD_SET_FRAME_AXI_OVL_ADDR, HD_ADDR_SEC_AXI_OVL);//second AXI address,ADDR_AXI_OVL
+	VpuWriteReg(CMD_SET_FRAME_AXI_BTP_ADDR, HD_ADDR_SEC_AXI_BTP);//second AXI address,ADDR_AXI_BTP
+#else
+	VpuWriteReg(CMD_SET_FRAME_AXI_OVL_ADDR, 0); //second AXI address,ADDR_AXI_OVL
+	VpuWriteReg(CMD_SET_FRAME_AXI_BTP_ADDR, 0); //second AXI address,ADDR_AXI_BTP
+#endif
+	VpuWriteReg(CMD_SET_FRAME_CACHE_CONFIG, 0x7e0);//2D CACHE CONFIG
+
+	VpuWriteReg(CMD_SET_FRAME_SLICE_BB_START, HD_ADDR_SLICE_BUFFER);//ADDR_SLICE_BUFFER
+	VpuWriteReg(CMD_SET_FRAME_SLICE_BB_SIZE, SLICE_SAVE_SIZE);//ADDR_SLICE_SIZE
+
+	while (VpuReadReg(BIT_BUSY_FLAG ) == 1); // BIT_BUSY_FLAG = 0
+   /*
+	VpuWriteReg(BIT_RUN_INDEX, 0x0); 	// BIT_RUN_INDEX
+	VpuWriteReg(BIT_RUN_COD_STD, 0x0); 	// BIT_RUN_COD_STD, H.264
+	VpuWriteReg(BIT_RUN_AUX_STD, 0x0); 	// BIT_RUN_AUX_STD
+	VpuWriteReg(BIT_FRM_DIS_FLG, 0x0);  // BIT_FRM_DIS_FLG
+	*/
+
+	// 4b0000: H.264 DECODER
+	// 4b0001: VC-1 DECODER
+	// 4b0010: MPEG-2 DECODER
+	// 4b0011: MPEG-4/DivX-3 DECODER
+	// 4b0100: RV DECODER
+	// 4b0101: AVS DECODER
+	// 4b1000: MJPEG DECODER
+
+	// Calculate frame buffer addresses
+	{
+	int  addrNextLuma = HD_ADDR_FRAME_BASE;
+
+	for (k=0; k < FrameBufNum; k = k + 1) {
+		DpbLum[k]	= addrNextLuma;
+		DpbCb[k]	 = DpbLum[k]   + PicSize;
+		DpbCr[k]	 = DpbCb[k]	+ PicSize/4;
+		MvColBuf[k]  = DpbCr[k]	+ PicSize/4;
+		addrNextLuma = MvColBuf[k] + PicSize/4;
+		debug_printf("k=%d y=0x%x u=0x%x v=0x%x\n", k,DpbLum[k],DpbCb[k],DpbCr[k]);
+	}
+
+	// registering the base addresses of created frame buffers, little endian is ok?
+	for (k=0; k < FrameBufNum; k = k + 2) {
+		// 64 BIT BIG Endian
+		MWRITE_WORD(HD_ADDR_BIT_PARA + (k*12)	  , DpbCb[k]   );
+		MWRITE_WORD(HD_ADDR_BIT_PARA + (k*12) +  4, DpbLum[k]  );
+		MWRITE_WORD(HD_ADDR_BIT_PARA + (k*12) +  8, DpbLum[k+1]);
+		MWRITE_WORD(HD_ADDR_BIT_PARA + (k*12) + 12, DpbCr[k]   );
+		MWRITE_WORD(HD_ADDR_BIT_PARA + (k*12) + 16, DpbCr[k+1] );
+		MWRITE_WORD(HD_ADDR_BIT_PARA + (k*12) + 20, DpbCb[k+1] );
+	}
+
+	//mvCol buf
+	for (k=0; k < FrameBufNum; k = k + 2) {
+		// 64 BIT BIG Endian
+		MWRITE_WORD(HD_ADDR_BIT_PARA + 384+(k*4)	 , MvColBuf[k+1]);
+		MWRITE_WORD(HD_ADDR_BIT_PARA + 384+(k*4) +  4, MvColBuf[k]);
+	}
+
+	flush_dcache_range(HD_ADDR_BIT_PARA, HD_ADDR_BIT_PARA+PARA_BUF_SIZE);
+	}
+
+	VpuWriteReg(BIT_BUSY_FLAG, 0x1);// set busy.sheen
+	VpuWriteReg(BIT_WORK_BUF_ADDR, HD_ADDR_BIT_WORK);
+	VpuWriteReg(BIT_RUN_INDEX, 0x0); 	// BIT_RUN_INDEX
+	VpuWriteReg(BIT_RUN_COD_STD, 0x0); 	// BIT_RUN_COD_STD, H.264
+	VpuWriteReg(BIT_RUN_AUX_STD, 0x0); 	// BIT_RUN_AUX_STD
+	VpuWriteReg(BIT_FRM_DIS_FLG, 0x0);  // BIT_FRM_DIS_FLG
+
+	VpuWriteReg(BIT_RUN_COMMAND, 0x4); // BIT_RUN_COMMAND: SET_FRAME_BUF
+
+	// Wait until busyFlag==0
+	while (VpuReadReg(BIT_BUSY_FLAG ) == 1);   // BIT_BUSY_FLAG = 0
+
+	// decode processing
+	while(1) {
+		//ret= VpuReadReg(BIT_BIT_STREAM_PARAM);
+		debug_printf("%s: decoding...%d\n", __func__, dec_num);
+		//VpuWriteReg(BIT_BIT_STREAM_PARAM, 0);  // BIT_BIT_STREAM_PARAM
+		//VpuWriteReg(BIT_WORK_BUF_ADDR, HD_ADDR_BIT_WORK);	  // BIT_WORK_BUF_ADDR
+		/*
+		if(dec_num==0 || dec_num==1){
+			for(k=0;k<0x200;k+=4)
+			debug_printf("0x%03X: 0x%08X\n",k,VpuReadReg(k));
+		}*/
+
+		//for BIT_RUN_COMMAND: PIC_RUN
+		VpuWriteReg(CMD_DEC_PIC_OPTION, 0x0); //I search,B skip,user data report...sheen
+		VpuWriteReg(BIT_BASE+0x198, 0x0); //CMD_DEC_FRAME_SKIP_NUM .sheen
+		VpuWriteReg(CMD_DEC_PIC_ROT_MODE, 0x0); //rotation and mirroring.sheen
+
+		VpuWriteReg(BIT_BUSY_FLAG, 0x1);// set busy.sheen
+		VpuWriteReg(BIT_WORK_BUF_ADDR, HD_ADDR_BIT_WORK);
+		VpuWriteReg(BIT_RUN_INDEX, 0x0); //instance or process index.sheen
+		VpuWriteReg(BIT_RUN_COD_STD, 0x0); //codec index, H.264 =0
+		VpuWriteReg(BIT_RUN_AUX_STD, 0x0); //auxiliary codec index. H.264/AVC =0
+
+		VpuWriteReg(BIT_RUN_COMMAND , 0x3); // BIT_RUN_COMMAND :PIC_RUN
+
+		// decode 1 frame complete
+		// Wait until busyFlag==0
+		while (VpuReadReg(BIT_BUSY_FLAG ) == 1);	// BIT_BUSY_FLAG = 0
+
+		// Read output information
+		//REG32(0x1000000c)= VpuReadReg(BIT_BASE+0x1c4);   // Display frame index
+		DispFrameIdx = VpuReadReg(RET_DEC_PIC_DISPLAY_IDX);   // Display frame index
+		//REG32(0x10000010) = VpuReadReg(BIT_BASE+0x1dc);   // Decoded frame index
+		DecDecFrameIdx = VpuReadReg(RET_DEC_PIC_DECODED_IDX);
+
+		DecPicType = VpuReadReg(RET_DEC_PIC_TYPE) & 7;   // REC_DEC_PIC_TYPE
+		ret= VpuReadReg(RET_DEC_PIC_SUCCESS);//PIC_RUN result
+		PicSize= VpuReadReg(BIT_RD_PTR)-data; //frame bytes size
+		data= VpuReadReg(BIT_RD_PTR);//cur bitstream addr
+
+		debug_printf("%s:ret 0x%x type %d disIDX %d decIDX %d BIT_RD_PTR 0x%x frmSz %d\n", __func__, ret, DecPicType,DispFrameIdx, DecDecFrameIdx,data,PicSize);
+
+		if(ret != 1 || PicSize <=0){
+			debug_printf("%s: One frame dec err!\n", __func__);
+			break;
+		}
+
+		if (DispFrameIdx == -1) // -1, no output ,end of the sequence.
+		{
+			// Decode successful
+			debug_printf("%s: EOS 1.\n", __func__);
+			break;
+
+		} else if (DispFrameIdx >=0 /*DispFrameIdx != -3 && DispFrameIdx != -2*/) { // -2,-3, no display frame
+			// Host handle output picture, such as display, then clear display flag
+			// For example, if host wants to display index0 frame, the Y, CB, CR addresses are // located in DpbLum[0]), DpbCb[0], DpbCr[0];
+			//  By calling VpuWriteReg(BIT_BASE+0x150, 0x0) to clear display flag of index0 after displaying index0 frame
+			//32 bits, each bit match one frame index.sheen
+			DispFrameIdx = VpuReadReg(BIT_FRM_DIS_FLG) & (~(1<<DispFrameIdx));
+
+			VpuWriteReg(BIT_FRM_DIS_FLG, DispFrameIdx);
+		}
+
+		//check md5
+		if(md5_check && DecDecFrameIdx>=0){
+			flush_dcache_range(DpbLum[DecDecFrameIdx],DpbLum[DecDecFrameIdx]+sizeX*sizeY*3/2);
+			md5((unsigned char*)DpbLum[DecDecFrameIdx], sizeX*sizeY*3/2, md5Data);
+
+			debug_printf("md5 digest[0-7]=[0x%x %x %x %x %x %x %x %x]\n",md5Data[0],md5Data[1],md5Data[2],md5Data[3],md5Data[4],md5Data[5],md5Data[6],md5Data[7]);
+			debug_printf("md5 digest[8-15]=[0x%x %x %x %x %x %x %x %x]\n",md5Data[8],md5Data[9],md5Data[10],md5Data[11],md5Data[12],md5Data[13],md5Data[14],md5Data[15]);
+			for(k=0;k<16;k++){
+				if(md5Data[k]!=yuv_md5_digest[dec_num*16+k]){
+					debug_printf("md5 check fail!!!\n");
+					return -2;
+				}
+			}
+			debug_printf("md5 check pass!!!\n");
+		}
+
+
+		// copying yuv data to a file
+		// You should use your own method to output decoded frames to outside, such as using USB library.
+		dec_num++;
+
+		if(dec_num >= FRAME_TEST_NUM )
+			break;
+
+		if((data - HD_ADDR_BIT_STREAM) >= (bitStreamSize - 7)){
+			debug_printf("%s: EOS 2.\n", __func__);
+			break;
+		}
+	}
+
+	debug_printf("%s: end seq.\n", __func__);
+	VpuWriteReg(BIT_BUSY_FLAG, 0x1);// set busy.sheen
+	VpuWriteReg(BIT_RUN_COMMAND , 0x2); // BIT_RUN_COMMAND :SEQ_END
+	while (VpuReadReg(BIT_BUSY_FLAG ) == 1);	// BIT_BUSY_FLAG = 0
+
+	// You can directly output these 32 frame buffers to outside using USB driver.
+	printf("%s: test success finish.\n", __func__);
+	return 0;
+}
+
diff --git a/board/rda/rda8810/Makefile b/board/rda/rda8810/Makefile
new file mode 100644
index 0000000000..5750c05000
--- /dev/null
+++ b/board/rda/rda8810/Makefile
@@ -0,0 +1,82 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS-y	+= clock_config.o clock.o ddr3.o
+else
+COBJS-$(CONFIG_MACH_RDA8810) += hal_config.o
+endif
+
+RDA_TARGET_DEF_FILE := $(TOPDIR)/target-device.def
+RDA_GET_MAKEFILE_VAR_FUNC = $(strip $(shell sed -n 's/^[ 	]*$(1)[ 	]*[?:]\?=\([^\#]\+\)\#*.*$$/\1/p' $(2)))
+
+NUMBER_OF_SIM := $(call RDA_GET_MAKEFILE_VAR_FUNC,NUMBER_OF_SIM,$(RDA_TARGET_DEF_FILE))
+ifeq ($(NUMBER_OF_SIM),)
+$(error Failed to get NUMBER_OF_SIM in $(RDA_TARGET_DEF_FILE))
+endif
+
+USER_SIM_ORDER := $(call RDA_GET_MAKEFILE_VAR_FUNC,USER_SIM_ORDER,$(RDA_TARGET_DEF_FILE))
+ifeq ($(USER_SIM_ORDER),)
+$(error Failed to get USER_SIM_ORDER in $(RDA_TARGET_DEF_FILE))
+endif
+
+NULL_STRING :=
+SPACE := ${NULL_STRING} # end of the line
+COMMA := ,
+TGT_SIM_ORDER := $(foreach SIM,$(USER_SIM_ORDER),$(SIM)$(COMMA))
+TGT_SIM_ORDER := $(subst ${SPACE},,${TGT_SIM_ORDER})
+
+CPPFLAGS_board/$(BOARDDIR)/hal_config.o += -I$(TOPDIR)/board/$(VENDOR)/common/include -DTGT_SIM_ORDER=$(TGT_SIM_ORDER) -DNUMBER_OF_SIM=$(NUMBER_OF_SIM)
+
+ifeq ($(strip $(TARGET_TABLET_MODE)),true)
+CPPFLAGS_board/$(BOARDDIR)/clock.o += -DTARGET_TABLET_MODE
+endif
+
+COBJS   := $(COBJS-y)
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak *~ .depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/rda/rda8810/clock.c b/board/rda/rda8810/clock.c
new file mode 100644
index 0000000000..bbcefd036f
--- /dev/null
+++ b/board/rda/rda8810/clock.c
@@ -0,0 +1,1967 @@
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/rda_iomap.h>
+#include <asm/io.h>
+#include <asm/arch/reg_sysctrl.h>
+#include <asm/arch/hwcfg.h>
+#include <asm/arch/ispi.h>
+#include <asm/arch/rda_sys.h>
+#include <asm/arch/defs_mdcom.h>
+#include <asm/arch/spl_board_info.h>
+#include "clock_config.h"
+#include "debug.h"
+#include "ddr3.h"
+#include <rda/tgt_ap_clock_config.h>
+
+#if (PMU_VBUCK1_VAL < 0 || PMU_VBUCK1_VAL > 15)
+#error "Invalid PMU_VBUCK1_VAL"
+#endif
+#if (PMU_VBUCK3_VAL < 0 || PMU_VBUCK3_VAL > 15)
+#error "Invalid PMU_VBUCK3_VAL"
+#endif
+#ifdef PMU_VBUCK4_VAL
+#if (PMU_VBUCK4_VAL < 0 || PMU_VBUCK4_VAL > 15)
+#error "Invalid PMU_VBUCK4_VAL"
+#endif
+#endif
+
+//#define DO_SIMPLE_DDR_TEST
+//#define DO_DDR_PLL_DEBUG
+
+#ifdef _TGT_AP_DDR_AUTO_CALI_ENABLE
+extern UINT8 g_debug_ddr3;
+static UINT8 rda2_result[8] = {0};
+
+extern ulong __ddrcal_start;
+extern ulong __start;
+
+static u16 * spl_text_start_addr;
+static u16 * ddr_cal_val_start_addr;
+#endif
+
+enum {
+	AP_CPU_CLK_IDX = 0,
+	AP_BUS_CLK_IDX,
+	AP_MEM_CLK_IDX,
+	AP_USB_CLK_IDX,
+};
+
+static int pll_enabled(int idx)
+{
+	if ((hwp_sysCtrlAp->Cfg_Pll_Ctrl[idx] &
+			(SYS_CTRL_AP_AP_PLL_ENABLE_MASK |
+			 SYS_CTRL_AP_AP_PLL_LOCK_RESET_MASK)) ==
+			(SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE |
+			 SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET))
+		return 1;
+	else
+		return 0;
+}
+
+static int usb_in_use = 0;
+
+static void check_usb_usage(void)
+{
+	unsigned int mask = SYS_CTRL_AP_BUS_SEL_FAST_SLOW |
+		SYS_CTRL_AP_PLL_LOCKED_BUS_MASK |
+		SYS_CTRL_AP_PLL_LOCKED_USB_MASK;
+	unsigned int reg = SYS_CTRL_AP_BUS_SEL_FAST_FAST |
+		SYS_CTRL_AP_PLL_LOCKED_BUS_LOCKED |
+		SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED;
+
+	if ((hwp_sysCtrlAp->Sel_Clock & mask) == reg &&
+			pll_enabled(AP_BUS_CLK_IDX) &&
+			pll_enabled(AP_USB_CLK_IDX))
+		usb_in_use = 1;
+	else
+		usb_in_use = 0;
+}
+
+#ifdef DO_SIMPLE_DDR_TEST
+
+void mem_test_write(void)
+{
+	unsigned short flag, mask;
+	unsigned int i, a, b;
+	volatile unsigned int *addr;
+
+	printf("write ddr test!!!!!!\n");
+
+ 	addr = (volatile unsigned int *)(0x83000000);
+	while((uint32)addr < 0x85000000)
+	{
+	    for (i=0; i<16; i++) {
+		flag = 0x0101 << i;
+	        mask = ~flag;
+	        a = mask<<16 | mask;
+	        b = mask<<16 |flag ;
+	        *(addr++) = a;
+	        *(addr++) = a;
+	        *(addr++) = b;
+	        *(addr++) = a;
+	    }
+	}
+}
+
+void mem_test_read(void)
+{
+	unsigned short flag, mask;
+	unsigned int i, temp, a, b, i_err;
+	volatile unsigned int *addr;
+
+	printf("read ddr!!!!\n");
+
+	addr = (volatile unsigned int *)(0x83000000);
+	i_err=0;
+
+	while((uint32)addr < 0x85000000)
+	{
+	    for (i=0; i<16; i++) {
+	        flag = 0x0101 << i;
+	        mask = ~flag;
+	        a = mask<<16 | mask;
+	        b = mask<<16 |flag ;
+	        temp = *(addr++);
+	        if ( temp != a) {
+		    i_err=i_err+1;
+		    if (i_err > 2 )  break;
+	            printf("addr: 0x");
+	            print_u32((UINT32)addr);
+	            printf("\n");
+	            printf("error value: 0x");
+	            print_u32(temp);
+	            printf("\n");
+	            printf("right value: 0x");
+	            print_u32(a);
+	            printf("\n");
+	        }
+	        temp = *(addr++);
+	        if ( temp != a) {
+		    i_err=i_err+1;
+		    if (i_err > 2 )  break;
+	            printf("addr: 0x");
+	            print_u32((UINT32)addr);
+	            printf("\n");
+	            printf("error value: 0x");
+	            print_u32(temp);
+	            printf("\n");
+	            printf("right value: 0x");
+	            print_u32(a);
+	            printf("\n");
+	        }
+	        temp = *(addr++);
+	        if ( temp != b) {
+		    i_err=i_err+1;
+		    if (i_err > 2 )  break;
+	            printf("addr: 0x");
+	            print_u32((UINT32)addr);
+	            printf("\n");
+	            printf("error value: 0x");
+	            print_u32(temp);
+	            printf("\n");
+	            printf("right value: 0x");
+	            print_u32(b);
+	            printf("\n");
+	        }
+	        temp = *(addr++);
+	        if ( temp != a) {
+		    i_err=i_err+1;
+		    if (i_err > 2 )  break;
+	            printf("addr: 0x");
+	            print_u32((UINT32)addr);
+	            printf("\n");
+	            printf("error value: 0x");
+	            print_u32(temp);
+	            printf("\n");
+	            printf("right value: 0x");
+	            print_u32(a);
+	            printf("\n");
+	        }
+	    }
+	}
+	printf("test complete!\n");
+}
+
+#endif /* DO_SIMPLE_DDR_TEST */
+
+#ifndef CONFIG_RDA_FPGA
+
+// PMU bit fields
+#define PMU_SET_BITFIELD(dword, bitfield, value) \
+	(((dword) & ~(bitfield ## _MASK)) | (bitfield(value)))
+
+#define RDA_PMU_VBUCK1_BIT_ACT(n)        (((n)&0xf)<<12)
+#define RDA_PMU_VBUCK1_BIT_ACT_MASK      (0xf<<12)
+#define RDA_PMU_VBUCK1_BIT_ACT_SHIFT     (12)
+
+#define RDA_PMU_VBUCK4_BIT_ACT_SHIFT     (4)
+#define RDA_PMU_VBUCK4_BIT_ACT_MASK      (0xf<<4)
+#define RDA_PMU_VBUCK4_BIT_ACT(n)        (((n)&0xf)<<4)
+
+#define RDA_PMU_VBUCK3_BIT_ACT_SHIFT     (12)
+#define RDA_PMU_VBUCK3_BIT_ACT_MASK      (0xf<<12)
+#define RDA_PMU_VBUCK3_BIT_ACT(n)        (((n)&0xf)<<12)
+
+struct pll_freq {
+	UINT32 freq_mhz;
+	UINT16 major;
+	UINT16 minor;
+	UINT16 with_div;
+	UINT16 div;
+};
+
+typedef enum {
+	PLL_REG_CPU_BASE = 0x00,
+	PLL_REG_BUS_BASE = 0x20,
+	PLL_REG_MEM_BASE = 0x60,
+	PLL_REG_USB_BASE = 0x80,
+} PLL_REG_BASE_INDEX_t;
+
+typedef enum {
+	PLL_REG_OFFSET_01H = 1,
+	PLL_REG_OFFSET_02H = 2,
+	PLL_REG_OFFSET_DIV = 3,
+	PLL_REG_OFFSET_04H = 4,
+	PLL_REG_OFFSET_MAJOR = 5,
+	PLL_REG_OFFSET_MINOR = 6,
+	PLL_REG_OFFSET_07H = 7,
+} PLL_REG_OFFSET_INDEX_t;
+
+/* MajorMinor = 2^29 * (freq / 26), only hign 32bits */
+static struct pll_freq pll_freq_table[] = {
+	/* MHz Major   Minor   div */
+	{1600, 0x7B13, 0xB138, 0, 0x0000},
+	{1200, 0x5C4E, 0xC4EC, 0, 0x0000},
+	{1150, 0x5876, 0x2762, 0, 0x0000},
+	{1100, 0x549D, 0x89D8, 0, 0x0000},
+	{1050, 0x50C4, 0xEC4E, 0, 0x0000},
+	{1020, 0x4E76, 0x2762, 0, 0x0000},
+	{1010, 0x4DB1, 0x3B13, 0, 0x0000},
+	{1000, 0x4CEC, 0x4EC4, 0, 0x0000},
+	{ 988, 0x4C00, 0x0000, 0, 0x0000},
+	{ 800, 0x3D89, 0xD89C, 0, 0x0000},
+	{ 780, 0x3C00, 0x0000, 0, 0x0000},
+	{ 750, 0x39B1, 0x3B13, 0, 0x0000},
+	{ 600, 0x2E27, 0x6274, 0, 0x0000},
+	{ 520, 0x2800, 0x0000, 0, 0x0000},
+	{ 519, 0x27EC, 0x4EC4, 1, 0x0007},
+	{ 500, 0x2676, 0x2762, 1, 0x0007},
+	{ 480, 0x24EC, 0x4EC4, 0, 0x0000},
+	{ 455, 0x2300, 0x0000, 1, 0x0007},
+	{ 416, 0x2000, 0x0000, 1, 0x0007},
+	/* 800M div 1, PLL:800M  DDR:400M for mem pll only */
+	{ 400, 0x1EC4, 0xEC4C, 1, 0x0007},
+	{ 355, 0x369D, 0x89D8, 1, 0x0007},
+	/* 702M div 1, PLL:702M  DDR:351M for mem pll only */
+	{ 351, 0x3600, 0x0000, 1, 0x0007},
+	{ 333, 0x333B, 0x13B1, 1, 0x0007},
+	/* 624M div 1, PLL:624M  DDR:312M for mem pll only */
+	{ 312, 0x3000, 0x0000, 1, 0x0007},
+	{ 290, 0x2C9D, 0x89D8, 1, 0x0007},
+	/* 520M div 1, PLL:520M  DDR:260M for mem pll only */
+	{ 260, 0x2800, 0x0000, 1, 0x0007},
+	/* 800M div 2, PLL:400M  DDR:200M for mem pll only */
+	{ 200, 0x3D89, 0xD89C, 1, 0x0006},
+	/* DDR:156M for mem pll only */
+	{ 156, 0x3000, 0x0000, 1, 0x0006},
+	/* 800M div 4, PLL:200M  DDR:100M for mem pll only */
+	{ 100, 0x3D89, 0xD89C, 1, 0x0005},
+	/* 800M div 8, PLL:100M  DDR:50M for mem pll only */
+	{  50, 0x3D89, 0xD89C, 1, 0x0004},
+};
+
+static  struct clock_config *g_clock_config;
+
+#ifdef DO_DDR_PLL_DEBUG
+static struct clock_config clock_debug_config;
+static UINT32 ddrfreq = 400, ddr32bit = 0;
+#endif
+
+unsigned int * const g_reg_cache =
+	(unsigned int *)RDA_MDCOM_CHN_AT_BUF_ADD_WRITE;
+unsigned short g_reg_cnt = 0;
+const unsigned short g_reg_to_save[] = {
+	 0x65,  0x69, 0x100, 0x120, 0x140, 0x160,
+	0x107, 0x127, 0x147, 0x167, 0x18a, };
+
+#define AP_ISPI_REG_CACHE_FLAG      (0xac1561ca)
+
+static void reg_cache_start(void)
+{
+	*g_reg_cache = AP_ISPI_REG_CACHE_FLAG;
+}
+
+static void reg_cache_save(unsigned int idx, unsigned int value)
+{
+	int i;
+
+	for (i = 0; i < g_reg_cnt; i++) {
+		if ((*(g_reg_cache + 2 + i) >> 16) == idx) {
+			*(g_reg_cache + 2 + i) = (idx << 16) | (value & 0xFFFF);
+			return;
+		}
+	}
+
+	*(g_reg_cache + 2 + g_reg_cnt) = (idx << 16) | (value & 0xFFFF);
+	++g_reg_cnt;
+}
+
+static void reg_cache_end(void)
+{
+	*(g_reg_cache + 1) = g_reg_cnt;
+	*(g_reg_cache + 2 + g_reg_cnt) = AP_ISPI_REG_CACHE_FLAG;
+}
+
+static void ispi_reg_write_and_save(unsigned int idx, unsigned int value)
+{
+	int i;
+
+	ispi_reg_write(idx, value);
+
+	for (i = 0; i < ARRAY_SIZE(g_reg_to_save); i++) {
+		if (idx == g_reg_to_save[i])
+			reg_cache_save(idx, value);
+	}
+}
+
+static void sys_shutdown_pll(void)
+{
+	int i;
+
+	hwp_sysCtrlAp->REG_DBG = AP_CTRL_PROTECT_UNLOCK;
+
+	if (usb_in_use) {
+		hwp_sysCtrlAp->Sel_Clock = SYS_CTRL_AP_SLOW_SEL_RF_RF
+			| SYS_CTRL_AP_CPU_SEL_FAST_SLOW
+			| SYS_CTRL_AP_BUS_SEL_FAST_FAST
+			| SYS_CTRL_AP_TIMER_SEL_FAST_FAST;
+	} else {
+		hwp_sysCtrlAp->Sel_Clock = SYS_CTRL_AP_SLOW_SEL_RF_RF
+			| SYS_CTRL_AP_CPU_SEL_FAST_SLOW
+			| SYS_CTRL_AP_BUS_SEL_FAST_SLOW
+			| SYS_CTRL_AP_TIMER_SEL_FAST_FAST;
+	}
+
+	for (i = 0; i < 3; i++) {
+		/* In download mode, rom code has been set ap bus*/
+		if (usb_in_use) {
+			if (i == AP_BUS_CLK_IDX) // ap bus
+				continue;
+		}
+		hwp_sysCtrlAp->Cfg_Pll_Ctrl[i] =
+			SYS_CTRL_AP_AP_PLL_ENABLE_POWER_DOWN |
+			SYS_CTRL_AP_AP_PLL_LOCK_RESET_RESET;
+	}
+}
+
+static const unsigned short pll_patch_reg_base[] =
+{ PLL_REG_CPU_BASE, PLL_REG_BUS_BASE, PLL_REG_MEM_BASE, PLL_REG_USB_BASE };
+static char pll_patch_multi2[ARRAY_SIZE(pll_patch_reg_base)] = { 0, };
+
+void pll_patch_reg_set(unsigned int mask, unsigned int offset,
+		unsigned int value)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(pll_patch_reg_base); i++) {
+		if ((mask & (1 << i)) == 0) {
+			continue;
+		}
+
+		if (offset == PLL_REG_OFFSET_02H) {
+			// Keep the original refmulti2 flag
+			value |= pll_patch_multi2[i] ? (1 << 8) : 0;
+			if (i == AP_USB_CLK_IDX && rda_metal_id_get() >= 7)
+				value ^= (1 << 8);
+		}
+		ispi_reg_write_and_save(pll_patch_reg_base[i] + offset, value);
+	}
+}
+
+unsigned int pll_patch_reg_check(unsigned int mask, unsigned int check,
+		unsigned int count)
+{
+	int i, j;
+	unsigned int value;
+	unsigned int lockMask = mask;
+
+	for (j = 0; j < count; j++) {
+		for (i = 0; i < ARRAY_SIZE(pll_patch_reg_base); i++) {
+			if ((mask & (1 << i)) == 0) {
+				continue;
+			}
+
+			value = ispi_reg_read(pll_patch_reg_base[i] + PLL_REG_OFFSET_04H);
+			if ((value & check) != check) {
+				lockMask &= ~(1 << i);
+				if (lockMask == 0) {
+					goto _exit;
+				}
+			}
+		}
+	}
+
+_exit:
+	return lockMask;
+}
+
+static void pll_setup_patch(unsigned int mask)
+{
+	unsigned int cnt;
+	unsigned int lockMask;
+	unsigned int vcore;
+
+	if (mask == 0)
+		return;
+
+	/* AP ISPI read requires low vcore & high vpad */
+	ispi_open(1);
+	vcore = pmu_reg_read(0x2F);
+	pmu_reg_write(0x05, 0x4FF8);
+	pmu_reg_write(0x2F, 0x8444);
+	ispi_open(0);
+	udelay(5000);
+
+	lockMask = pll_patch_reg_check(mask, 0xE000, 10);
+	mask &= ~lockMask;
+	if (mask == 0) {
+		goto _exit;
+	}
+
+	pll_patch_reg_set(mask, PLL_REG_OFFSET_07H, 0x0010);
+	pll_patch_reg_set(mask, PLL_REG_OFFSET_02H, 0x02c9);
+
+	cnt = 0;
+	do {
+		if (cnt < 5 || (cnt % 100) == 0)
+			printf("Applying PLL enable patch: mask=0x%x\n", mask);
+
+		pll_patch_reg_set(mask, PLL_REG_OFFSET_01H, (cnt & 0x1) ? 0x7e70 : 0x7e7f);
+
+		lockMask = pll_patch_reg_check(mask, 0xA000, 1);
+		if (lockMask) {
+			pll_patch_reg_set(lockMask, PLL_REG_OFFSET_01H, 0x7e78);
+			pll_patch_reg_set(lockMask, PLL_REG_OFFSET_02H, 0x0209);
+			udelay(1000);
+			lockMask = pll_patch_reg_check(lockMask, 0xE000, 10);
+			mask &= ~lockMask;
+			if (mask == 0)
+				break;
+		}
+
+		cnt++;
+	} while (1);
+
+	printf("PLL enable patch done: %d\n", cnt);
+
+_exit:
+	ispi_open(1);
+	pmu_reg_write(0x2F, vcore);
+	ispi_open(0);
+	udelay(5000);
+}
+
+static void sys_setup_pll(void)
+{
+	int i;
+	UINT32 mask;
+	UINT32 locked;
+	int cnt = 10; //10us, according to IC, the pll must be locked
+	UINT32 pllMask = 0;
+
+	hwp_sysCtrlAp->REG_DBG = AP_CTRL_PROTECT_UNLOCK;
+
+	for (i = 0; i < 3; i++) {
+		/* In download mode, rom code has been set ap bus*/
+		if (usb_in_use) {
+			if (i == AP_BUS_CLK_IDX) // ap bus
+				continue;
+		}
+
+		pllMask |= (1 << i);
+
+		if (AP_MEM_CLK_IDX == i)
+			hwp_sysCtrlAp->Cfg_Pll_Ctrl[i] =
+				SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE |
+				SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET |
+				SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(1)|
+				SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(30);
+		else
+			hwp_sysCtrlAp->Cfg_Pll_Ctrl[i] =
+				SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE |
+				SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET |
+				SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(6)|
+				SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(30);
+	}
+
+	pll_setup_patch(pllMask);
+
+	mask = SYS_CTRL_AP_PLL_LOCKED_CPU_MASK
+	    | SYS_CTRL_AP_PLL_LOCKED_BUS_MASK
+	    | SYS_CTRL_AP_PLL_LOCKED_MEM_MASK
+	    //| SYS_CTRL_AP_PLL_LOCKED_USB_MASK
+	    ;
+	locked = SYS_CTRL_AP_PLL_LOCKED_CPU_LOCKED
+	    | SYS_CTRL_AP_PLL_LOCKED_BUS_LOCKED
+	    | SYS_CTRL_AP_PLL_LOCKED_MEM_LOCKED
+	    //| SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED
+	    ;
+
+	while (((hwp_sysCtrlAp->Sel_Clock & mask) != locked) && cnt) {
+		udelay(1);
+		cnt--;
+	}
+	if (cnt == 0) {
+		printf("WARNING, cannot lock cpu/bus/mem pll 0x%08x ",
+			hwp_sysCtrlAp->Sel_Clock);
+		printf("but we run anyway ...\n");
+	}
+
+	for (i = 0; i < 3; i++) {
+		hwp_sysCtrlAp->Cfg_Pll_Ctrl[i] |=
+		    SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_ENABLE;
+	}
+
+	hwp_sysCtrlAp->Sel_Clock = SYS_CTRL_AP_SLOW_SEL_RF_RF
+	    | SYS_CTRL_AP_CPU_SEL_FAST_FAST
+	    | SYS_CTRL_AP_BUS_SEL_FAST_FAST
+	    | SYS_CTRL_AP_TIMER_SEL_FAST_FAST;
+}
+
+static void sys_setup_clk(void)
+{
+	// Disable some power-consuming clocks
+#ifdef CONFIG_VPU_TEST
+	hwp_sysCtrlAp->Clk_APO_Enable = SYS_CTRL_AP_ENABLE_APOC_VPU;
+	hwp_sysCtrlAp->Clk_MEM_Enable = SYS_CTRL_AP_ENABLE_MEM_VPU;
+#else
+	hwp_sysCtrlAp->Clk_APO_Disable = SYS_CTRL_AP_DISABLE_APOC_VPU;
+	hwp_sysCtrlAp->Clk_MEM_Disable = SYS_CTRL_AP_DISABLE_MEM_VPU;
+#endif
+
+	// Init clock gating mode
+	hwp_sysCtrlAp->Clk_CPU_Mode = 0;
+#ifdef CONFIG_VPU_TEST
+	hwp_sysCtrlAp->Clk_AXI_Mode = SYS_CTRL_AP_MODE_AXI_DMA_MANUAL | SYS_CTRL_AP_MODE_APB0_CONF_MANUAL;
+#else
+	hwp_sysCtrlAp->Clk_AXI_Mode = SYS_CTRL_AP_MODE_AXI_DMA_MANUAL;
+#endif
+	hwp_sysCtrlAp->Clk_AXIDIV2_Mode = 0;
+	hwp_sysCtrlAp->Clk_GCG_Mode = SYS_CTRL_AP_MODE_GCG_GOUDA_MANUAL
+				| SYS_CTRL_AP_MODE_GCG_CAMERA_MANUAL;
+	hwp_sysCtrlAp->Clk_AHB1_Mode = 0;
+	hwp_sysCtrlAp->Clk_APB1_Mode = 0;
+	hwp_sysCtrlAp->Clk_APB2_Mode = 0;
+#ifdef CONFIG_VPU_TEST
+	hwp_sysCtrlAp->Clk_MEM_Mode = SYS_CTRL_AP_MODE_CLK_MEM_MANUAL;
+#else
+	hwp_sysCtrlAp->Clk_MEM_Mode = 0;
+#endif
+	hwp_sysCtrlAp->Clk_APO_Mode = SYS_CTRL_AP_MODE_APOC_VPU_MANUAL;
+
+	// Init module frequency
+	hwp_sysCtrlAp->Cfg_Clk_AP_CPU = g_clock_config->CLK_CPU;
+	hwp_sysCtrlAp->Cfg_Clk_AP_AXI = g_clock_config->CLK_AXI;
+	hwp_sysCtrlAp->Cfg_Clk_AP_GCG = g_clock_config->CLK_GCG;
+
+	if (!usb_in_use) {
+		hwp_sysCtrlAp->Cfg_Clk_AP_AHB1 = g_clock_config->CLK_AHB1;
+	}
+
+	hwp_sysCtrlAp->Cfg_Clk_AP_APB1 = g_clock_config->CLK_APB1;
+	hwp_sysCtrlAp->Cfg_Clk_AP_APB2 = g_clock_config->CLK_APB2;
+	hwp_sysCtrlAp->Cfg_Clk_AP_MEM = g_clock_config->CLK_MEM;
+	hwp_sysCtrlAp->Cfg_Clk_AP_GPU = g_clock_config->CLK_GPU;
+	hwp_sysCtrlAp->Cfg_Clk_AP_VPU = g_clock_config->CLK_VPU;
+	hwp_sysCtrlAp->Cfg_Clk_AP_VOC = g_clock_config->CLK_VOC;
+	hwp_sysCtrlAp->Cfg_Clk_AP_SFLSH = g_clock_config->CLK_SFLSH;
+}
+
+static void print_sys_reg(char *name, UINT32 value)
+{
+#if 0
+	printf("clk %s = %lx\n", name, value);
+#endif
+}
+
+static void sys_dump_clk(void)
+{
+	print_sys_reg("CPU", hwp_sysCtrlAp->Cfg_Clk_AP_CPU);
+	print_sys_reg("AXI", hwp_sysCtrlAp->Cfg_Clk_AP_AXI);
+	print_sys_reg("GCG", hwp_sysCtrlAp->Cfg_Clk_AP_GCG);
+	print_sys_reg("AHB1", hwp_sysCtrlAp->Cfg_Clk_AP_AHB1);
+	print_sys_reg("APB1", hwp_sysCtrlAp->Cfg_Clk_AP_APB1);
+	print_sys_reg("APB2", hwp_sysCtrlAp->Cfg_Clk_AP_APB2);
+	print_sys_reg("MEM", hwp_sysCtrlAp->Cfg_Clk_AP_MEM);
+	print_sys_reg("GPU", hwp_sysCtrlAp->Cfg_Clk_AP_GPU);
+	print_sys_reg("VPU", hwp_sysCtrlAp->Cfg_Clk_AP_VPU);
+	print_sys_reg("VOC", hwp_sysCtrlAp->Cfg_Clk_AP_VOC);
+	print_sys_reg("SFLSH", hwp_sysCtrlAp->Cfg_Clk_AP_SFLSH);
+}
+
+static int pll_freq_set(UINT32 reg_base, UINT32 freq_mhz)
+{
+	int i;
+	struct pll_freq *freq;
+	unsigned int major, minor;
+	unsigned short value_02h;
+
+	/* find pll_freq */
+	for (i = 0; i < ARRAY_SIZE(pll_freq_table); i++) {
+		if (pll_freq_table[i].freq_mhz == freq_mhz)
+			break;
+	}
+	if (i >= ARRAY_SIZE(pll_freq_table)) {
+		printf("pll_freq_set, fail to find freq\n");
+		return -1;
+	}
+
+	freq = &pll_freq_table[i];
+	if (freq->with_div && (reg_base == PLL_REG_MEM_BASE)) {
+		ispi_reg_write_and_save(reg_base + PLL_REG_OFFSET_DIV,
+				freq->div);
+		// Calculate the real MEM PLL freq
+		freq_mhz *= (1 << (8 - (freq->div & 0x7)));
+	}
+	if (freq_mhz >= 800 || reg_base == PLL_REG_USB_BASE) {
+		// Apply multi2 option for PLL over 800M
+		for (i = 0; i < ARRAY_SIZE(pll_patch_reg_base); i++) {
+			if (pll_patch_reg_base[i] == reg_base)
+				break;
+		}
+		if (i >= ARRAY_SIZE(pll_patch_reg_base)) {
+			printf("pll_freq_set: fail to find reg base: 0x%x",
+					(unsigned int)reg_base);
+			return -1;
+		}
+		pll_patch_multi2[i] = 1;
+		value_02h = 0x0309;
+		// Div PLL freq by 2
+		minor = ((freq->major & 0xFFFF) << 14) |
+			((freq->minor >> 2) & 0x3FFF);
+		minor >>= 1;
+		// Recalculate the divider
+		major = (minor >> 14) & 0xFFFF;
+		minor = (minor << 2) & 0xFFFF;
+	} else {
+		value_02h = 0x0209;
+		major = freq->major;
+		minor = freq->minor;
+	}
+	if (reg_base == PLL_REG_USB_BASE && rda_metal_id_get() >= 7)
+		value_02h ^= (1 << 8);
+	ispi_reg_write_and_save(reg_base + PLL_REG_OFFSET_02H, value_02h);
+	ispi_reg_write_and_save(reg_base + PLL_REG_OFFSET_MAJOR, major);
+	ispi_reg_write_and_save(reg_base + PLL_REG_OFFSET_MINOR, minor);
+	ispi_reg_write_and_save(reg_base + PLL_REG_OFFSET_07H, 0x0010);
+
+	return 0;
+}
+
+static void pll_setup_freq(void)
+{
+	pll_freq_set(PLL_REG_CPU_BASE, g_clock_config->PLL_FREQ_CPU);
+	// Always configure BUS PLL, even when it is being used
+	pll_freq_set(PLL_REG_BUS_BASE, g_clock_config->PLL_FREQ_BUS);
+	pll_freq_set(PLL_REG_MEM_BASE, g_clock_config->PLL_FREQ_MEM);
+	pll_freq_set(PLL_REG_USB_BASE, g_clock_config->PLL_FREQ_USB);
+}
+
+static void print_pll_freq(char *name, UINT32 value)
+{
+	printf("pll freq %s = %d\n", name, (int)value);
+}
+
+static void sys_dump_pll_freq(void)
+{
+	print_pll_freq("CPU", g_clock_config->PLL_FREQ_CPU);
+	print_pll_freq("BUS", g_clock_config->PLL_FREQ_BUS);
+	print_pll_freq("MEM", g_clock_config->PLL_FREQ_MEM);
+	//print_pll_freq("USB", g_clock_config->PLL_FREQ_USB);
+}
+
+#if 0
+static void pmu_get_efuse_dcdc(int buckVoltLow[])
+{
+	static const u8 setBitCnt[8] = { 0, 1, 1, 2, 1, 2, 2, 3, };
+	u16 dcdc;
+	int i;
+
+	pmu_reg_write(0x51, 0x02ed);
+	udelay(2000);
+	pmu_reg_write(0x51, 0x02fd);
+	dcdc = pmu_reg_read(0x52);
+	pmu_reg_write(0x51, 0x0200);
+
+	for (i = 0; i < 4; i++) {
+		buckVoltLow[i] = (setBitCnt[dcdc & 0x7] > 1);
+		dcdc >>= 3;
+	}
+}
+#endif
+
+static void pmu_setup_init(void)
+{
+	u32 value;
+	int buck_volt_low[4] = { 0, };
+
+	rda_nand_iodrive_set();
+
+#ifdef CONFIG_RDA_PDL
+	enable_charger(0);
+#endif
+
+	ispi_open(1);
+
+	// Disable vibrator
+	if (rda_metal_id_get() < 9)
+		pmu_reg_write(0x03, 0x9FDF);
+	else
+		pmu_reg_write(0x03, 0x9FFF);
+	// Enable bandgap chopper mode
+	pmu_reg_write(0x0F, 0x1E90);
+	// Enable high AC throttling
+	pmu_reg_write(0x12, 0x1218);
+#ifdef TARGET_TABLET_MODE
+	// Charger current (cc = 6, pre = 7)
+	pmu_reg_write(0x13, 0x1B70);
+#else
+	// Charger current (cc = 2, pre = 7)
+	pmu_reg_write(0x13, 0x1970);
+#endif
+	// Vcore DCDC freq
+	pmu_reg_write(0x2D, 0x96BA);
+	pmu_reg_write(0x2E, 0x12AA);
+#if 0
+	// Get efuse dcdc
+	pmu_get_efuse_dcdc(buck_volt_low);
+#endif
+	// Vcore voltage
+	value = 0x9444;
+	value = PMU_SET_BITFIELD(value, RDA_PMU_VBUCK1_BIT_ACT,
+			PMU_VBUCK1_VAL +
+			((PMU_VBUCK1_VAL < 15 && buck_volt_low[0]) ? 1 : 0));
+	pmu_reg_write(0x2F, value);
+	// DDR PWM mode
+	pmu_reg_write(0x0D, 0x92D0);
+	// DDR voltage
+	value = 0xAAB5;
+	value = PMU_SET_BITFIELD(value, RDA_PMU_VBUCK3_BIT_ACT,
+			PMU_VBUCK3_VAL +
+			((PMU_VBUCK3_VAL < 15 && buck_volt_low[2]) ? 1 : 0));
+#ifdef PMU_VBUCK4_VAL
+	value = PMU_SET_BITFIELD(value, RDA_PMU_VBUCK4_BIT_ACT,
+			PMU_VBUCK4_VAL +
+			((PMU_VBUCK4_VAL < 15 && buck_volt_low[3]) ? 1 : 0));
+	if (rda_metal_id_get() >= 9)
+		value ^= RDA_PMU_VBUCK4_BIT_ACT(8);
+	// vBuck4 in low voltage range
+	if (rda_metal_id_get() < 9)
+		pmu_reg_write(0x36, 0x6E44);
+	else
+		pmu_reg_write(0x36, 0x6E45);
+#else
+	if (rda_metal_id_get() < 9)
+		pmu_reg_write(0x36, 0x6E55);
+	else
+		pmu_reg_write(0x36, 0x6E54);
+#endif
+	pmu_reg_write(0x2A, value);
+	// DDR power parameters
+	pmu_reg_write(0x4A, 0x96AA);
+	pmu_reg_write(0x4B, 0x96AA);
+
+	ispi_open(0);
+	printf("PMU vbuck1 = %u, vbuck3 = %u\n", PMU_VBUCK1_VAL, PMU_VBUCK3_VAL);
+}
+
+static void setup_ddr_vtt(int vtt)
+{
+	if (rda_metal_id_get() >= 2) {
+		printf("setup ddr vtt to %d\n", vtt);
+		ispi_reg_write_and_save(0x69, 0x0008 | (vtt & 0x07) );
+	}
+}
+
+/*
+ * we initialize usb clock, but this won't cause the usb clock jitter,
+ * because wo don't setup the usb pll
+ */
+static void usb_clock_pre_init(void)
+{
+	if (rda_metal_id_get() < 2) {
+		ispi_reg_write_and_save(0x81, 0x7a68);
+		ispi_reg_write_and_save(0x82, 0x0308);
+		ispi_reg_write_and_save(0x83, 0xfae7);
+		ispi_reg_write_and_save(0x85, 0x1276);
+		ispi_reg_write_and_save(0x86, 0x2762);
+		ispi_reg_write_and_save(0x89, 0x7441);
+	} else {
+		ispi_reg_write_and_save(0x83, 0x72ef);
+		ispi_reg_write_and_save(0x89, 0x7400);
+	}
+}
+
+static void pll_setup_init(void)
+{
+	setup_ddr_vtt(DDR_VTT_VAL);
+
+	if (g_clock_config->DDR_CHAN_1_VALID) {
+		ispi_reg_write_and_save(0x100, g_clock_config->DDR_TIMING_100H);
+		ispi_reg_write_and_save(0x101, g_clock_config->DDR_TIMING_101H);
+		ispi_reg_write_and_save(0x102, g_clock_config->DDR_TIMING_102H);
+		ispi_reg_write_and_save(0x103, g_clock_config->DDR_TIMING_103H);
+		ispi_reg_write_and_save(0x104, g_clock_config->DDR_TIMING_104H);
+		ispi_reg_write_and_save(0x105, g_clock_config->DDR_TIMING_105H);
+		ispi_reg_write_and_save(0x106, g_clock_config->DDR_TIMING_106H);
+		ispi_reg_write_and_save(0x107, g_clock_config->DDR_TIMING_107H);
+		ispi_reg_write_and_save(0x108, g_clock_config->DDR_TIMING_108H);
+		ispi_reg_write_and_save(0x109, g_clock_config->DDR_TIMING_109H);
+		ispi_reg_write_and_save(0x10A, g_clock_config->DDR_TIMING_10AH);
+		ispi_reg_write_and_save(0x10B, g_clock_config->DDR_TIMING_10BH);
+	}
+
+	if (g_clock_config->DDR_CHAN_2_VALID) {
+		ispi_reg_write_and_save(0x120, g_clock_config->DDR_TIMING_120H);
+		ispi_reg_write_and_save(0x121, g_clock_config->DDR_TIMING_121H);
+		ispi_reg_write_and_save(0x122, g_clock_config->DDR_TIMING_122H);
+		ispi_reg_write_and_save(0x123, g_clock_config->DDR_TIMING_123H);
+		ispi_reg_write_and_save(0x124, g_clock_config->DDR_TIMING_124H);
+		ispi_reg_write_and_save(0x125, g_clock_config->DDR_TIMING_125H);
+		ispi_reg_write_and_save(0x126, g_clock_config->DDR_TIMING_126H);
+		ispi_reg_write_and_save(0x127, g_clock_config->DDR_TIMING_127H);
+		ispi_reg_write_and_save(0x128, g_clock_config->DDR_TIMING_128H);
+		ispi_reg_write_and_save(0x129, g_clock_config->DDR_TIMING_129H);
+		ispi_reg_write_and_save(0x12A, g_clock_config->DDR_TIMING_12AH);
+		ispi_reg_write_and_save(0x12B, g_clock_config->DDR_TIMING_12BH);
+	}
+
+	if (g_clock_config->DDR_CHAN_3_VALID) {
+		ispi_reg_write_and_save(0x140, g_clock_config->DDR_TIMING_140H);
+		ispi_reg_write_and_save(0x141, g_clock_config->DDR_TIMING_141H);
+		ispi_reg_write_and_save(0x142, g_clock_config->DDR_TIMING_142H);
+		ispi_reg_write_and_save(0x143, g_clock_config->DDR_TIMING_143H);
+		ispi_reg_write_and_save(0x144, g_clock_config->DDR_TIMING_144H);
+		ispi_reg_write_and_save(0x145, g_clock_config->DDR_TIMING_145H);
+		ispi_reg_write_and_save(0x146, g_clock_config->DDR_TIMING_146H);
+		ispi_reg_write_and_save(0x147, g_clock_config->DDR_TIMING_147H);
+		ispi_reg_write_and_save(0x148, g_clock_config->DDR_TIMING_148H);
+		ispi_reg_write_and_save(0x149, g_clock_config->DDR_TIMING_149H);
+		ispi_reg_write_and_save(0x14A, g_clock_config->DDR_TIMING_14AH);
+		ispi_reg_write_and_save(0x14B, g_clock_config->DDR_TIMING_14BH);
+	}
+
+	if (g_clock_config->DDR_CHAN_4_VALID) {
+		ispi_reg_write_and_save(0x160, g_clock_config->DDR_TIMING_160H);
+		ispi_reg_write_and_save(0x161, g_clock_config->DDR_TIMING_161H);
+		ispi_reg_write_and_save(0x162, g_clock_config->DDR_TIMING_162H);
+		ispi_reg_write_and_save(0x163, g_clock_config->DDR_TIMING_163H);
+		ispi_reg_write_and_save(0x164, g_clock_config->DDR_TIMING_164H);
+		ispi_reg_write_and_save(0x165, g_clock_config->DDR_TIMING_165H);
+		ispi_reg_write_and_save(0x166, g_clock_config->DDR_TIMING_166H);
+		ispi_reg_write_and_save(0x167, g_clock_config->DDR_TIMING_167H);
+		ispi_reg_write_and_save(0x168, g_clock_config->DDR_TIMING_168H);
+		ispi_reg_write_and_save(0x169, g_clock_config->DDR_TIMING_169H);
+		ispi_reg_write_and_save(0x16A, g_clock_config->DDR_TIMING_16AH);
+		ispi_reg_write_and_save(0x16B, g_clock_config->DDR_TIMING_16BH);
+	}
+
+	ispi_reg_write_and_save(0x180, g_clock_config->DDR_TIMING_180H);
+	ispi_reg_write_and_save(0x181, g_clock_config->DDR_TIMING_181H);
+	ispi_reg_write_and_save(0x182, g_clock_config->DDR_TIMING_182H);
+	ispi_reg_write_and_save(0x183, g_clock_config->DDR_TIMING_183H);
+	ispi_reg_write_and_save(0x184, g_clock_config->DDR_TIMING_184H);
+	ispi_reg_write_and_save(0x185, g_clock_config->DDR_TIMING_185H);
+	ispi_reg_write_and_save(0x186, g_clock_config->DDR_TIMING_186H);
+	ispi_reg_write_and_save(0x187, g_clock_config->DDR_TIMING_187H);
+	ispi_reg_write_and_save(0x188, g_clock_config->DDR_TIMING_188H);
+	ispi_reg_write_and_save(0x189, g_clock_config->DDR_TIMING_189H);
+	ispi_reg_write_and_save(0x18A, g_clock_config->DDR_TIMING_18AH);
+	ispi_reg_write_and_save(0x18B, g_clock_config->DDR_TIMING_18BH);
+	ispi_reg_write_and_save(0x18C, g_clock_config->DDR_TIMING_18CH);
+
+	usb_clock_pre_init();
+
+	udelay(5000);
+}
+
+static void pll_setup_mem(void)
+{
+}
+
+static void pll_setup_mem_cal(void)
+{
+}
+
+#if 0
+static void print_pll_reg(UINT32 index, UINT32 value)
+{
+	printf("pll reg %lx = %lx\n", index, value);
+}
+#endif
+
+static void pll_dump_reg(void)
+{
+#if 0
+	print_pll_reg(0x005, ispi_reg_read(0x005));
+	print_pll_reg(0x006, ispi_reg_read(0x006));
+	print_pll_reg(0x063, ispi_reg_read(0x063));
+	print_pll_reg(0x065, ispi_reg_read(0x065));
+	print_pll_reg(0x066, ispi_reg_read(0x066));
+
+	if (g_clock_config->DDR_CHAN_1_VALID)
+	{
+		print_pll_reg(0x100, ispi_reg_read(0x100));
+		print_pll_reg(0x101, ispi_reg_read(0x101));
+		print_pll_reg(0x102, ispi_reg_read(0x102));
+		print_pll_reg(0x103, ispi_reg_read(0x103));
+		print_pll_reg(0x104, ispi_reg_read(0x104));
+		print_pll_reg(0x105, ispi_reg_read(0x105));
+		print_pll_reg(0x106, ispi_reg_read(0x106));
+		print_pll_reg(0x107, ispi_reg_read(0x107));
+		print_pll_reg(0x108, ispi_reg_read(0x108));
+		print_pll_reg(0x109, ispi_reg_read(0x109));
+		print_pll_reg(0x10A, ispi_reg_read(0x10A));
+		print_pll_reg(0x10B, ispi_reg_read(0x10B));
+	}
+
+	if (g_clock_config->DDR_CHAN_2_VALID)
+	{
+		print_pll_reg(0x120, ispi_reg_read(0x120));
+		print_pll_reg(0x121, ispi_reg_read(0x121));
+		print_pll_reg(0x122, ispi_reg_read(0x122));
+		print_pll_reg(0x123, ispi_reg_read(0x123));
+		print_pll_reg(0x124, ispi_reg_read(0x124));
+		print_pll_reg(0x125, ispi_reg_read(0x125));
+		print_pll_reg(0x126, ispi_reg_read(0x126));
+		print_pll_reg(0x127, ispi_reg_read(0x127));
+		print_pll_reg(0x128, ispi_reg_read(0x128));
+		print_pll_reg(0x129, ispi_reg_read(0x129));
+		print_pll_reg(0x12A, ispi_reg_read(0x12A));
+		print_pll_reg(0x12B, ispi_reg_read(0x12B));
+	}
+
+	if (g_clock_config->DDR_CHAN_3_VALID)
+	{
+		print_pll_reg(0x140, ispi_reg_read(0x140));
+		print_pll_reg(0x141, ispi_reg_read(0x141));
+		print_pll_reg(0x142, ispi_reg_read(0x142));
+		print_pll_reg(0x143, ispi_reg_read(0x143));
+		print_pll_reg(0x144, ispi_reg_read(0x144));
+		print_pll_reg(0x145, ispi_reg_read(0x145));
+		print_pll_reg(0x146, ispi_reg_read(0x146));
+		print_pll_reg(0x147, ispi_reg_read(0x147));
+		print_pll_reg(0x148, ispi_reg_read(0x148));
+		print_pll_reg(0x149, ispi_reg_read(0x149));
+		print_pll_reg(0x14A, ispi_reg_read(0x14A));
+		print_pll_reg(0x14B, ispi_reg_read(0x14B));
+	}
+
+	if (g_clock_config->DDR_CHAN_4_VALID)
+	{
+		print_pll_reg(0x161, ispi_reg_read(0x161));
+		print_pll_reg(0x162, ispi_reg_read(0x162));
+		print_pll_reg(0x163, ispi_reg_read(0x163));
+		print_pll_reg(0x164, ispi_reg_read(0x164));
+		print_pll_reg(0x165, ispi_reg_read(0x165));
+		print_pll_reg(0x166, ispi_reg_read(0x166));
+		print_pll_reg(0x167, ispi_reg_read(0x167));
+		print_pll_reg(0x168, ispi_reg_read(0x168));
+		print_pll_reg(0x169, ispi_reg_read(0x169));
+		print_pll_reg(0x16A, ispi_reg_read(0x16A));
+		print_pll_reg(0x16B, ispi_reg_read(0x16B));
+	}
+
+	print_pll_reg(0x160, ispi_reg_read(0x160));
+	print_pll_reg(0x180, ispi_reg_read(0x180));
+	print_pll_reg(0x181, ispi_reg_read(0x181));
+	print_pll_reg(0x182, ispi_reg_read(0x182));
+	print_pll_reg(0x183, ispi_reg_read(0x183));
+	print_pll_reg(0x184, ispi_reg_read(0x184));
+	print_pll_reg(0x185, ispi_reg_read(0x185));
+	print_pll_reg(0x186, ispi_reg_read(0x186));
+	print_pll_reg(0x187, ispi_reg_read(0x187));
+	print_pll_reg(0x188, ispi_reg_read(0x188));
+	print_pll_reg(0x189, ispi_reg_read(0x189));
+	print_pll_reg(0x18A, ispi_reg_read(0x18A));
+	print_pll_reg(0x18B, ispi_reg_read(0x18B));
+#endif
+}
+
+static int clock_save_config(void)
+{
+	/* save config to nand */
+	return 1;
+}
+
+#ifdef DO_DDR_PLL_DEBUG
+
+static int ddr_get_freq(UINT8 chioce)
+{
+	switch(chioce)
+	{
+		case 1:
+			return 50;
+		case 2:
+			return 100;
+		case 3:
+			return 156;
+		case 4:
+			return 200;
+		case 5:
+			return 290;
+		case 6:
+			return 333;
+		case 7:
+			return 355;
+		case 8:
+			return 400;
+		case 9:
+			return 416;
+		case 10:
+			return 455;
+		case 11:
+			return 500;
+		case 12:
+			return 519;
+		default:
+			return -1;
+	}
+}
+
+static void freq_choose(void)
+{
+	UINT8 i = 0, buf[3] = {0}, choice = 0;
+	INT32 freq_temp = 0;
+
+	printf("\nPlese choose the ddr Freq:");
+	printf("\n1.50M  2.100M  3.156M  4.200M  5.290M  6.333M  7.355M  8.400M 9.416M 10.455M 11.500M 12.519M");
+	printf("\nThe number is:");
+
+	while(1)
+	{
+		if (i > 2)
+		{
+			printf("\n Sorry, you input is wrong. Please input again:");
+			i = 0;
+		}
+		buf[i] = serial_getc();
+		serial_putc(buf[i]);
+
+		if ( ('\r' == buf[i]) || ('\n' == buf[i]))
+		{
+			printf("\n");
+			break;
+		}
+
+		i++;
+	}
+
+	if (1 == i)
+		choice = buf[0] - 0x30;
+	else if (2 == i)
+		choice = 10*(buf[0] - 0x30) + (buf[1] - 0x30);
+	else
+		return;
+
+	freq_temp = ddr_get_freq(choice);
+	if (-1 == freq_temp )
+		printf("\n Sorry, the fre you choose is wrong");
+	ddrfreq = freq_temp;
+}
+
+static void data_bits_choose(void)
+{
+	UINT8 i = 0, buf[2] = {0};
+
+	printf("\nPlese choose the ddr data bits:");
+	printf("\n1.16  2.32");
+	printf("\nThe number is:");
+
+	while(1)
+	{
+		buf[i] =serial_getc();
+
+		if (i == 1)
+		{
+			if (('\r' == buf[i]) || ('\n' == buf[i]))
+			{
+				if (1 == (buf[0] - 0x30))
+					ddr32bit = 0;
+				else
+					ddr32bit = 1;
+				return;
+			}
+			else
+			{
+				printf("\n Sorry, you input is wrong. Please input again:");
+				i = 0;
+				continue;
+			}
+		}
+
+		serial_putc(buf[i]);
+
+		if ((buf[i] - 0x30) > 2 || 0 == (buf[i] - 0x30))
+			printf("\n Sorry, you input is wrong. Please input again:");
+		else
+			i++;
+	}
+}
+
+#if 0
+static void pmu_setup_calibration_voltage(UINT8 vcoreselect)
+{
+	UINT8 buf[3] = {0}, voltage = 0;
+	int i = 0;
+	UINT32 reg_value,temp, regid = 0;
+
+	ispi_open(1);
+	if (1 == vcoreselect)
+	{
+		regid = 0x2f;
+		printf("\nPlese input vcore voltage(0 ~ 15):");
+	}
+	else
+	{
+		regid = 0x2a;
+		printf("\nPlese input DDR voltage(0 ~ 15):");
+	}
+
+
+	while(1)
+	{
+		if (i > 2)
+		{
+			printf("\n Sorry, you input is wrong. Please input again:");
+			i = 0;
+		}
+		buf[i] = serial_getc();
+		serial_putc(buf[i]);
+
+		if ( ('\r' == buf[i]) || ('\n' == buf[i]))
+		{
+			printf("\n");
+			break;
+		}
+
+		i++;
+	}
+
+	if (1 == i)
+		voltage = buf[0] - 0x30;
+	else if (2 == i)
+		voltage = 10*(buf[0] - 0x30) + (buf[1] - 0x30);
+	else
+		return;
+
+	temp = (UINT32)voltage;
+	temp = (temp & 0xf) << 12;
+	reg_value = pmu_reg_read(regid);
+	reg_value &= ~(0xf << 12);
+	reg_value |= temp ;
+	pmu_reg_write(regid, reg_value);
+	mdelay(100);
+}
+#endif
+
+static void pmu_setup_calibration_voltage(UINT8 vcoreselect)
+{
+	UINT8 buf[3] = {0}, voltage = 0;
+	int i = 0;
+	UINT32 reg_value,temp, regid = 0;
+
+	ispi_open(1);
+	if (1 == vcoreselect)
+	{
+		regid = 0x2f;
+		printf("\nPlese input vcore voltage(0 ~ 15):");
+	}
+	else
+	{
+		regid = 0x2a;
+		if (2 == vcoreselect)
+			printf("\nPlese input DDR buck3 voltage(0 ~ 15):");
+		else
+			printf("\nPlese input DDR buck4 voltage(0 ~ 15):");
+	}
+
+	while(1)
+	{
+		if (i > 2)
+		{
+			printf("\n Sorry, you input is wrong. Please input again:");
+			i = 0;
+		}
+		buf[i] = serial_getc();
+		serial_putc(buf[i]);
+
+		if ( ('\r' == buf[i]) || ('\n' == buf[i]))
+		{
+			printf("\n");
+			break;
+		}
+
+		i++;
+	}
+
+	if (1 == i)
+		voltage = buf[0] - 0x30;
+	else if (2 == i)
+		voltage = 10*(buf[0] - 0x30) + (buf[1] - 0x30);
+	else
+		return;
+
+	if ((vcoreselect == 1) || (vcoreselect == 2))
+	{
+		temp = (UINT32)voltage;
+		temp = (temp & 0xf) << 12;
+		reg_value = pmu_reg_read(regid);
+		reg_value &= ~(0xf << 12);
+		reg_value |= temp ;
+		pmu_reg_write(regid, reg_value);
+		mdelay(100);
+	}
+	else
+	{
+		temp = (UINT32)voltage;
+		temp = (temp & 0xf) << 4;
+		reg_value = pmu_reg_read(regid);
+		reg_value &= ~(0xf << 4);
+		reg_value |= temp ;
+		if (rda_metal_id_get() >= 9)
+			reg_value ^= RDA_PMU_VBUCK4_BIT_ACT(8);
+		pmu_reg_write(regid, reg_value);
+		pmu_reg_write(0x0D, 0x92D0);
+		pmu_reg_write(0x4B, 0x96A8);
+		mdelay(100);
+	}
+}
+
+static void pmu_buck4_buck3_choose(void)
+{
+	UINT8 i = 0, buf[2] = {0};
+	UINT8 ddr_voltage_source = 0;
+
+	printf("\nPlese choose the ddr voltage:");
+	printf("\n1.DDR3L  2.DDR3");
+	printf("\nThe number is:");
+
+	while(1)
+	{
+		buf[i] =serial_getc();
+
+		if (i == 1)
+		{
+			if (('\r' == buf[i]) || ('\n' == buf[i]))
+			{
+				if (1 == (buf[0] - 0x30))
+					ddr_voltage_source =2;
+				else{
+					ddr_voltage_source = 3;
+					pmu_setup_calibration_voltage(2);
+				}
+				pmu_setup_calibration_voltage(ddr_voltage_source);
+				return;
+			}
+			else
+			{
+				printf("\n Sorry, you input is wrong. Please input again:");
+				i = 0;
+				continue;
+			}
+		}
+
+		serial_putc(buf[i]);
+
+		if ((buf[i] - 0x30) > 2 || 0 == (buf[i] - 0x30))
+			printf("\n Sorry, you input is wrong. Please input again:");
+		else
+			i++;
+	}
+}
+
+
+void clock_load_ddr_cal_config(void)
+{
+	clock_debug_config.PLL_FREQ_MEM = ddrfreq;
+	if (ddrfreq < 200)
+		clock_debug_config.DDR_FLAGS |= DDR_FLAGS_DLLOFF;
+	else
+		clock_debug_config.DDR_FLAGS &= ~DDR_FLAGS_DLLOFF;
+
+	if (0 == ddr32bit)
+	{
+		clock_debug_config.DDR_CHAN_3_VALID = 0;
+		clock_debug_config.DDR_CHAN_4_VALID = 0;
+	}
+
+	clock_debug_config.DDR_PARA &= ~DDR_PARA_MEM_BITS_MASK;
+	if (0 == ddr32bit)
+		clock_debug_config.DDR_PARA |= DDR_PARA_MEM_BITS(1);
+	else
+		clock_debug_config.DDR_PARA |= DDR_PARA_MEM_BITS(2);
+}
+
+static int serial_gets(UINT8 *pstr)
+{
+    UINT32 length;
+
+    length = 0;
+    while(1) {
+        pstr[length] = serial_getc();
+        if(pstr[length] == '\r') {
+            pstr[length] = 0x00;
+            break;
+        }
+        else if( pstr[length] == '\b' ) {
+            if(length>0) {
+                length --;
+                printf("\b");
+            }
+        }
+        else {
+            serial_putc(pstr[length]);
+            length ++;
+        }
+
+        if(length > 32)
+            return -1;
+    }
+    return length;
+}
+
+UINT32 asc2hex(UINT8 *pstr, UINT8 len)
+{
+	UINT8 i,ch,mylen;
+	UINT32 hexvalue;
+
+	for(mylen=0,i=0; i<8; i++)
+	{
+		if( pstr[i] == 0 )
+			break;
+		mylen ++;
+	}
+	if( len != 0 )
+	{
+		if(mylen>len)
+			mylen = len;
+	}
+	if(mylen>8)
+		mylen = 8;
+
+	hexvalue = 0;
+	for (i = 0; i < mylen; i++)
+	{
+		hexvalue <<= 4;
+		ch = *(pstr+i);
+		if((ch>='0') && (ch<='9'))
+			hexvalue |= ch - '0';
+		else if((ch>='A') && (ch<='F'))
+			hexvalue |= ch - ('A' - 10);
+		else if((ch>='a') && (ch<='f'))
+			hexvalue |= ch - ('a' - 10);
+		else
+			;
+	}
+	return(hexvalue);
+}
+
+#define DDR_ANALOG_PHY_NUM 65
+static const UINT16 ddr_pll_num[DDR_ANALOG_PHY_NUM] = {
+	0x0001,
+	0x100,
+	0x101,
+	0x102,
+	0x103,
+	0x104,
+	0x105,
+	0x106,
+	0x107,
+	0x108,
+	0x109,
+	0x10A,
+	0x10B,
+
+	0x0002,
+	0x120,
+	0x121,
+	0x122,
+	0x123,
+	0x124,
+	0x125,
+	0x126,
+	0x127,
+	0x128,
+	0x129,
+	0x12A,
+	0x12B,
+
+	0x0004,
+	0x140,
+	0x141,
+	0x142,
+	0x143,
+	0x144,
+	0x145,
+	0x146,
+	0x147,
+	0x148,
+	0x149,
+	0x14A,
+	0x14B,
+
+	0x0006,
+	0x160,
+	0x161,
+	0x162,
+	0x163,
+	0x164,
+	0x165,
+	0x166,
+	0x167,
+	0x168,
+	0x169,
+	0x16A,
+	0x16B,
+
+	0x180,
+	0x181,
+	0x182,
+	0x183,
+	0x184,
+	0x185,
+	0x186,
+	0x187,
+	0x188,
+	0x189,
+	0x18A,
+	0x18B,
+	0x18C
+};
+
+void ddr_pll_save_by_id(UINT16 reg_id, UINT16 reg_val)
+{
+	int i = 0;
+	UINT16 * ddr_pll_reg_base =  &g_clock_config->DDR_CHAN_1_VALID;
+
+	for (; i < DDR_ANALOG_PHY_NUM; i++)
+		if (reg_id == ddr_pll_num[i])
+			break;
+
+	if (i >= DDR_ANALOG_PHY_NUM)
+		return;
+
+	writew(reg_val, ddr_pll_reg_base + i);
+
+	return;
+}
+
+static int process_cmd(char * cmd)
+{
+	char cmd_element[3][16] = {{0}};
+	char * cmd_temp = cmd;
+	UINT8 i = 0, cmd_element_num = 0, former_space = 1;
+	UINT16 reg = 0, reg_value = 0;
+
+	if (NULL == cmd)
+		return -1;
+
+	while(('\0' != *cmd_temp) && ('\r' != *cmd_temp) && ('\n' != *cmd_temp))
+	{
+		if (' ' == * cmd_temp)
+		{
+			if (0 == former_space)
+			{
+				former_space = 1;
+				cmd_element[cmd_element_num][i] = '\0';
+				cmd_element_num++;
+				if (cmd_element_num > 2)
+					return -1;
+
+				i = 0;
+			}
+		}
+		else
+		{
+			former_space = 0;
+			cmd_element[cmd_element_num][i] = *cmd_temp;
+			i++;
+			if (i > 6)
+				return -1;
+		}
+
+		cmd_temp++;
+	}
+
+	cmd_element[cmd_element_num][i] = '\0';
+
+	if (!strcmp(cmd_element[0], "read"))
+	{
+		if (cmd_element_num == 2)
+			return -1;
+		if (('0' != cmd_element[1][0]) || ('x' != cmd_element[1][1]))
+			return -1;
+		reg = (UINT16)asc2hex((UINT8 *)&cmd_element[1][2], 4);
+		reg_value = ispi_reg_read(reg);
+		printf("value = 0x%x", reg_value);
+		printf("\nddrPll#");
+	}
+	else if (!strcmp(cmd_element[0], "write"))
+	{
+		if (cmd_element_num != 2)
+			return -1;
+		if (('0' != cmd_element[1][0]) || ('x' != cmd_element[1][1])
+		   || ('0' != cmd_element[2][0]) || ('x' != cmd_element[2][1]))
+			return -1;
+
+		reg = (UINT16)asc2hex((UINT8 *)&cmd_element[1][2], 4);
+		reg_value  = (UINT16)asc2hex((UINT8 *)&cmd_element[2][2], 4);
+		ispi_reg_write_and_save(reg, reg_value);
+		ddr_pll_save_by_id(reg, reg_value);
+	}
+	else if (!strcmp(cmd_element[0], "finish"))
+	{
+		return 1;
+	}
+	else if (!strcmp(cmd_element[0], "dump"))
+	{
+		pll_dump_reg();
+		printf("ddrPll#");
+	}
+	else
+	{
+		return -1;
+	}
+
+	return 0;
+}
+
+static void cmd_input(void)
+{
+	char cmd[48] = {0};
+	int len = 0;
+
+	ispi_open(0);
+	printf("\nddrPll#");
+	while(1)
+	{
+		len = serial_gets((UINT8 *)cmd);
+		printf("\nddrPll#");
+		if (len > 0)
+		{
+			int result = 0;
+
+			result =  process_cmd(cmd);
+			if (-1 == result)
+				printf("command error! \nddrPll#");
+			else if (1 == result)
+				break;
+			else
+				continue;
+		}
+	}
+
+	return;
+}
+
+#endif /* DO_DDR_PLL_DEBUG */
+
+#ifdef DDR_TIMING_101H_VAL_U08
+static void pll_val_reset(u16 meta_id)
+{
+	if (0xC == meta_id){
+		g_clock_config->DDR_TIMING_101H = DDR_TIMING_101H_VAL_U08;
+		g_clock_config->DDR_TIMING_102H = DDR_TIMING_102H_VAL_U08;
+		g_clock_config->DDR_TIMING_103H = DDR_TIMING_103H_VAL_U08;
+		g_clock_config->DDR_TIMING_104H = DDR_TIMING_104H_VAL_U08;
+		g_clock_config->DDR_TIMING_105H = DDR_TIMING_105H_VAL_U08;
+		g_clock_config->DDR_TIMING_106H = DDR_TIMING_106H_VAL_U08;
+
+		g_clock_config->DDR_TIMING_121H = DDR_TIMING_121H_VAL_U08;
+		g_clock_config->DDR_TIMING_122H = DDR_TIMING_122H_VAL_U08;
+		g_clock_config->DDR_TIMING_123H = DDR_TIMING_123H_VAL_U08;
+		g_clock_config->DDR_TIMING_124H = DDR_TIMING_124H_VAL_U08;
+		g_clock_config->DDR_TIMING_125H = DDR_TIMING_125H_VAL_U08;
+		g_clock_config->DDR_TIMING_126H = DDR_TIMING_126H_VAL_U08;
+
+		g_clock_config->DDR_TIMING_141H = DDR_TIMING_141H_VAL_U08;
+		g_clock_config->DDR_TIMING_142H = DDR_TIMING_142H_VAL_U08;
+		g_clock_config->DDR_TIMING_143H = DDR_TIMING_143H_VAL_U08;
+		g_clock_config->DDR_TIMING_144H = DDR_TIMING_144H_VAL_U08;
+		g_clock_config->DDR_TIMING_145H = DDR_TIMING_145H_VAL_U08;
+		g_clock_config->DDR_TIMING_146H = DDR_TIMING_146H_VAL_U08;
+
+		g_clock_config->DDR_TIMING_161H = DDR_TIMING_161H_VAL_U08;
+		g_clock_config->DDR_TIMING_162H = DDR_TIMING_162H_VAL_U08;
+		g_clock_config->DDR_TIMING_163H = DDR_TIMING_163H_VAL_U08;
+		g_clock_config->DDR_TIMING_164H = DDR_TIMING_164H_VAL_U08;
+		g_clock_config->DDR_TIMING_165H = DDR_TIMING_165H_VAL_U08;
+		g_clock_config->DDR_TIMING_166H = DDR_TIMING_166H_VAL_U08;
+
+		g_clock_config->DDR_TIMING_18BH = DDR_TIMING_18BH_VAL_U08;
+	}
+}
+#endif
+
+#ifdef _TGT_AP_DDR_AUTO_CALI_ENABLE
+static void sys_reset_mem(void)
+{
+	hwp_sysCtrlAp->MEM_Rst_Set = SYS_CTRL_AP_SET_MEM_RST_DMC | SYS_CTRL_AP_SET_MEM_RST_DDRPHY_P;
+	mdelay(1);
+	hwp_sysCtrlAp->MEM_Rst_Clr = SYS_CTRL_AP_CLR_MEM_RST_DMC | SYS_CTRL_AP_CLR_MEM_RST_DDRPHY_P;
+	mdelay(1);
+}
+
+static void pll_setup_init_cal_dynamic(u8 rda2)
+{
+	u16 reg_b = 0;
+
+	reg_b=rda2*0x1000;
+	reg_b |= (g_clock_config->DDR_TIMING_103H & 0xfff);
+
+	if (g_clock_config->DDR_CHAN_1_VALID)
+		ispi_reg_write_and_save(0x103, reg_b); //default 0x44b0, dqs_prsel_preset<3:0>,dq_prsel_todig<3:0>,dqs_prsel_todig<3:0>,dq_prsel_offset<35:32>
+
+	if (g_clock_config->DDR_CHAN_2_VALID)
+		ispi_reg_write_and_save(0x123, reg_b); //default 0x44b0, dqs_prsel_preset<3:0>,dq_prsel_todig<3:0>,dqs_prsel_todig<3:0>,dq_prsel_offset<35:32>
+
+	if (g_clock_config->DDR_CHAN_3_VALID)
+		ispi_reg_write_and_save(0x143, reg_b); //default 0x44b0, dqs_prsel_preset<3:0>,dq_prsel_todig<3:0>,dqs_prsel_todig<3:0>,dq_prsel_offset<35:32>
+
+	if (g_clock_config->DDR_CHAN_4_VALID)
+		ispi_reg_write_and_save(0x163, reg_b); //default 0x44b0, dqs_prsel_preset<3:0>,dq_prsel_todig<3:0>,dqs_prsel_todig<3:0>,dq_prsel_offset<35:32>
+}
+
+static void pll_save_ddr_cal_dynamic(UINT8 rda2)
+{
+	u16 reg_b = 0;
+
+	reg_b = rda2*0x1000;
+	reg_b |= (g_clock_config->DDR_TIMING_103H & 0xfff);
+
+	if (g_clock_config->DDR_CHAN_1_VALID)
+		g_clock_config->DDR_TIMING_103H = reg_b;
+
+	if (g_clock_config->DDR_CHAN_2_VALID)
+		g_clock_config->DDR_TIMING_123H = reg_b;
+
+	if (g_clock_config->DDR_CHAN_3_VALID)
+		g_clock_config->DDR_TIMING_143H = reg_b;
+
+	if (g_clock_config->DDR_CHAN_4_VALID)
+		g_clock_config->DDR_TIMING_163H = reg_b;
+}
+
+static void pll_setup_ddr_cal_dynamic(u16 val)
+{
+	if (g_clock_config->DDR_CHAN_1_VALID)
+		g_clock_config->DDR_TIMING_103H = val;
+
+	if (g_clock_config->DDR_CHAN_2_VALID)
+		g_clock_config->DDR_TIMING_123H = val;
+
+	if (g_clock_config->DDR_CHAN_3_VALID)
+		g_clock_config->DDR_TIMING_143H = val;
+
+	if (g_clock_config->DDR_CHAN_4_VALID)
+		g_clock_config->DDR_TIMING_163H = val;
+}
+static int print_rda2_result(UINT8 * rda2, UINT8 rda2_old)
+{
+	int j, first_position = 0, total_num = 0, chioce_rda2 = 0;
+
+	printf("\n\n");
+	printf("rda2 stand for dqs_prsel_preset \n");
+	printf("rda2=0 rda2=1 rda2=2 rda2=3 rda2=4 rda2=5 rda2=6 rda2=7\n");
+	for (j=0;j<8;j=j+1){
+		printf("   %c   ",rda2_result[j]);
+	}
+	printf("\nPlease check the result and choose the best one");
+
+	for (j=0;j<8;j=j+1)
+		if (('*' == rda2_result[j]) && ('R' == rda2_result[(j  + 1) % 8]))
+			break;
+
+	first_position = (j + 1) % 8;
+
+	for (j=0;j<8;j=j+1)
+		if ('R' == rda2_result[j])
+			total_num += 1;
+
+	chioce_rda2 = first_position + total_num/2 -1;
+
+	if (chioce_rda2 < 0)
+		printf("\nerror!The range of rda2 is 0~~7!Calculated rda2 is minus\n");
+
+	if (0 != (total_num % 2) )
+		chioce_rda2 += 1;
+
+	if (8 == total_num)
+		*rda2 = rda2_old;
+	else
+		*rda2 = ((UINT8)chioce_rda2 % 8);
+	printf("\n final rda2= %d, rda2_old = %d \n", *rda2, rda2_old);
+
+	return total_num;
+}
+
+static void mem_test_cal_write(UINT32 offset, UINT8 rda2)
+{
+	volatile unsigned int *addr, addr_val_write;
+
+	addr = (volatile unsigned int *)(0x83000000);
+	while((unsigned int)addr < offset){
+		if (((unsigned int )addr % 8) == 0)
+			addr_val_write = 0xfefefefe | rda2;
+		else
+			addr_val_write = (unsigned int)addr;
+		*addr = addr_val_write;
+		addr++;
+	}
+}
+
+static int mem_test_cal_read(UINT32 offset, UINT8 rda2)
+{
+	volatile unsigned int *addr, addr_val_read, addr_val_write;
+
+	addr = (volatile unsigned int *)(0x83000000);
+	while((unsigned int)addr < offset){
+		if (((unsigned int )addr % 8) == 0)
+			addr_val_write = 0xfefefefe | rda2;
+		else
+			addr_val_write = (unsigned int)addr;
+		addr_val_read = *addr;
+		if (addr_val_read != addr_val_write){
+			//printf("Read ddr error, write value = %x, read val = %x",(unsigned int)addr, addr_val_read);
+			return -1;
+		}
+		addr++;
+	}
+
+	return 0;
+}
+
+static void mem_test_result(UINT32 offset, UINT8 rda2)
+{
+	rda2_result[rda2]='R';
+
+	mem_test_cal_write(offset, rda2);
+	if (0 != mem_test_cal_read(offset, rda2))
+		rda2_result[rda2]='*';
+}
+
+static int ddr_rda2_cal(UINT32 offset, UINT8 * rda2_choose, UINT8 rda2_old)
+{
+	u8 rda2 = 0;
+
+	for (rda2=0;rda2 < 8;rda2=rda2 + 1){
+		sys_reset_mem();
+		sys_shutdown_pll();
+		ispi_open(0);
+		pll_setup_init();
+		pll_setup_init_cal_dynamic(rda2);
+		pll_setup_freq();
+		sys_setup_pll();
+		sys_setup_clk();
+
+		ddr_init(g_clock_config->DDR_FLAGS, g_clock_config->DDR_PARA);
+		mem_test_result(offset, rda2);
+	}
+
+	return print_rda2_result(rda2_choose, rda2_old);
+}
+
+/**
+SRAM MAP
+-- 0x100000
+| +CONFIG_TRAP_SIZE(0xC0)
+--
+| +CONFIG_UIMAGEHDR_SIZE(0x40)
+-- spl_text_start_addr
+| +TEXT DATA
+-- ddr_cal_val_start_addr
+| +CONFIG_DDR_CAL_VAL_SIZE
+--
+| + BSS STATCK
+--
+| +SPL BOARD INFO SIZE(0x200)
+-- 0x110000
+**/
+static void ddr_auto_cal_val_save(void)
+{
+	spl_bd_t * spl_board_info = (spl_bd_t *)CONFIG_SPL_BOARD_INFO_ADDR;
+
+	spl_board_info->spl_ddr_cal_info.ddr_auto_cal_flag = CONIFG_DDR_CAL_VAL_FLAG;
+	spl_board_info->spl_ddr_cal_info.ddr_auto_cal_offs = (u8 *)(ddr_cal_val_start_addr)
+		- (u8 *)(spl_text_start_addr) + CONFIG_UIMAGEHDR_SIZE;
+	spl_board_info->spl_ddr_cal_info.ddr_auto_cal_val[0] = g_clock_config->DDR_TIMING_103H;
+}
+
+static void ddr_auto_cal_choose(void)
+{
+	UINT8 rda2 = 0;
+	UINT8 rda2_old = 0;
+	int rda2_r_total_num = 0;
+	int i = 0;
+
+	g_debug_ddr3 = 0;
+	rda2_old = (g_clock_config->DDR_TIMING_103H & 0xf000) >> 12;
+
+	for (i = 0; i < 3; i++){
+		int off = i << 18;
+
+		if (2 == i)
+			off = i << 20;
+		rda2_r_total_num = ddr_rda2_cal(0x83040000 + off, &rda2, rda2_old);
+		if (8 != rda2_r_total_num)
+			break;
+	}
+
+	sys_reset_mem();
+	sys_shutdown_pll();
+	ispi_open(0);
+	pll_setup_init();
+	pll_save_ddr_cal_dynamic(rda2);
+	pll_setup_init_cal_dynamic(rda2);
+	pll_setup_freq();
+	sys_setup_pll();
+	sys_setup_clk();
+
+	g_debug_ddr3 = 1;
+}
+#endif
+
+int clock_init(void)
+{
+#ifdef DO_DDR_PLL_DEBUG
+	char choice = 'n';
+#endif
+
+#ifdef DDR_TIMING_101H_VAL_U08
+	u16 metal_id = rda_metal_id_get();
+#endif
+#ifdef _TGT_AP_DDR_AUTO_CALI_ENABLE
+	u16 ddr_auto_cal_val;
+	spl_text_start_addr = (u16 *)&__start;
+	ddr_cal_val_start_addr = (u16 *)&__ddrcal_start;
+
+	u16 ddr_auto_cal_flag = *ddr_cal_val_start_addr;
+	ddr_auto_cal_val = *(ddr_cal_val_start_addr + 1);
+#endif
+
+	/* First check current usb usage */
+	check_usb_usage();
+
+	printf("Init Clock ...\n");
+	g_clock_config = get_default_clock_config();
+
+	printf("Clock config ver: %d.%d\n",
+		g_clock_config->VERSION_MAJOR, g_clock_config->VERSION_MINOR);
+
+#ifdef _TGT_AP_DDR_AUTO_CALI_ENABLE
+	if (CONIFG_DDR_CAL_VAL_FLAG == ddr_auto_cal_flag)
+		pll_setup_ddr_cal_dynamic(ddr_auto_cal_val);
+#endif
+	pmu_setup_init();
+
+#ifdef DO_DDR_PLL_DEBUG
+	printf("If you want to config the ddr para manully ?(y = yes, n = no) \n");
+	choice = serial_getc();
+	if (choice == 'y')
+	{
+		memcpy(&clock_debug_config, g_clock_config,
+				sizeof(clock_debug_config));
+		g_clock_config = &clock_debug_config;
+		pmu_setup_calibration_voltage(1);
+		pmu_buck4_buck3_choose();
+		freq_choose();
+		data_bits_choose();
+		clock_load_ddr_cal_config();
+	}
+#endif
+
+	sys_shutdown_pll();
+	ispi_open(0);
+
+	reg_cache_start();
+
+#ifdef DDR_TIMING_101H_VAL_U08
+	printf("Metal id = %x\n", (int)metal_id);
+
+	if (0xA == metal_id){
+		printf("Default val will be used.");
+	}
+	else if (0xC == metal_id){
+		pll_val_reset(metal_id);
+	}
+	else{
+		printf("Sorry, metal id is not fit\n");
+	}
+#endif
+
+	pll_setup_init();
+#ifdef DO_DDR_PLL_DEBUG
+	if (choice == 'y')
+		cmd_input();
+#endif
+	pll_setup_freq();
+	sys_setup_pll();
+	sys_setup_clk();
+
+	if (g_clock_config->DDR_CAL) {
+		printf("Init DDR for ddr_cal\n");
+		ddr_init(g_clock_config->DDR_FLAGS, g_clock_config->DDR_PARA);
+		printf("Done\n");
+		pll_setup_mem_cal();
+		clock_save_config();
+	} else {
+		pll_setup_mem();
+	}
+#ifdef _TGT_AP_DDR_AUTO_CALI_ENABLE
+	if (CONIFG_DDR_CAL_VAL_FLAG != ddr_auto_cal_flag){
+		ddr_auto_cal_choose();
+	}
+#endif
+	sys_dump_pll_freq();
+	sys_dump_clk();
+	pll_dump_reg();
+
+	printf("Init DDR, flag = 0x%04x, para = 0x%08lx\n",
+		g_clock_config->DDR_FLAGS, g_clock_config->DDR_PARA);
+	ddr_init(g_clock_config->DDR_FLAGS, g_clock_config->DDR_PARA);
+#ifdef _TGT_AP_DDR_AUTO_CALI_ENABLE
+	ddr_auto_cal_val_save();
+#endif
+	reg_cache_end();
+
+	printf("Done\n");
+
+	return 0;
+}
+
+#else /* CONFIG_RDA_FPGA */
+int clock_init(void)
+{
+	u16 ddr_flags = DDR_FLAGS_DLLOFF
+		| DDR_FLAGS_ODT(1)
+		| DDR_FLAGS_RON(0);
+	//16bit
+	u32 ddr_para = DDR_PARA_MEM_BITS(1)
+		| DDR_PARA_BANK_BITS(3)
+		| DDR_PARA_ROW_BITS(3)
+		| DDR_PARA_COL_BITS(2);
+
+	printf("Init DDR\n");
+	ddr_init(ddr_flags, ddr_para);
+	printf("Done\n");
+
+#ifdef DO_SIMPLE_DDR_TEST
+	mem_test_write();
+	mem_test_read();
+#endif
+	return 0;
+}
+
+#endif /* CONFIG_RDA_FPGA */
+
diff --git a/board/rda/rda8810/clock_config.c b/board/rda/rda8810/clock_config.c
new file mode 100644
index 0000000000..5c635eaf04
--- /dev/null
+++ b/board/rda/rda8810/clock_config.c
@@ -0,0 +1,145 @@
+#ifndef TARGET_TOOL
+#include <common.h>
+#include <asm/arch/factory.h>
+#include "clock_config.h"
+#endif
+
+#include "ddr3.h"
+#include <rda/tgt_ap_clock_config.h>
+
+#ifndef DDR_TIMING_100H_VAL
+#define DDR_TIMING_100H_VAL		0
+#endif
+#ifndef DDR_TIMING_120H_VAL
+#define DDR_TIMING_120H_VAL		0
+#endif
+#ifndef DDR_TIMING_140H_VAL
+#define DDR_TIMING_140H_VAL		0
+#endif
+#ifndef DDR_TIMING_18CH_VAL
+#define DDR_TIMING_18CH_VAL		0
+#endif
+
+static  struct clock_config clock_default_config = {
+	/* Header */
+	0, 			// MAGIC;
+	CLOCK_VER_MAJOR,	// VERSION_MAJOR;
+	CLOCK_VER_MINOR,	// VERSION_MINOR;
+	/* PLL Freqs (MHz) */
+	_TGT_AP_PLL_CPU_FREQ,	// PLL_FREQ_CPU; /* 05, 06 */
+	_TGT_AP_PLL_BUS_FREQ,	// PLL_FREQ_BUS; /* 25, 26 */
+	_TGT_AP_PLL_MEM_FREQ,	// PLL_FREQ_MEM; /* 65, 66 */
+	_TGT_AP_PLL_USB_FREQ,	// PLL_FREQ_USB; /* 85, 86 */
+	/* DDR Cal */
+	0,			// DDR_CAL;
+	/* DDR_FLAGS */
+	DDR_FLAGS_ODT(_TGT_AP_DDR_ODT)	// 010 -- 120 Ohm
+#if (_TGT_AP_DDR_CLOCK < 200)
+	    | DDR_FLAGS_DLLOFF
+#endif
+#ifdef _TGT_AP_DDR_LOWPWR
+	    | DDR_FLAGS_LOWPWR
+#endif
+	    | DDR_FLAGS_RON(_TGT_AP_DDR_RON),	// 00 -- 40 Ohm
+	/* DDR_PARA */
+	DDR_PARA_CHIP_BITS(_TGT_AP_DDR_CHIP_BITS)
+	    | DDR_PARA_MEM_BITS(_TGT_AP_DDR_MEM_BITS)
+	    | DDR_PARA_BANK_BITS(_TGT_AP_DDR_BANK_BITS)
+	    | DDR_PARA_ROW_BITS(_TGT_AP_DDR_ROW_BITS )
+	    | DDR_PARA_COL_BITS(_TGT_AP_DDR_COL_BITS),
+
+	/* AP sysctrl */
+	_TGT_AP_CLK_CPU,	// CLK_CPU;
+	_TGT_AP_CLK_AXI,	// CLK_AXI;
+	_TGT_AP_CLK_GCG,	// CLK_GCG;
+	_TGT_AP_CLK_AHB1,	// CLK_AHB1;
+	_TGT_AP_CLK_APB1,	// CLK_APB1;
+	_TGT_AP_CLK_APB2,	// CLK_APB2;
+	_TGT_AP_CLK_MEM,	// CLK_MEM;
+	_TGT_AP_CLK_GPU,	// CLK_GPU;
+	_TGT_AP_CLK_VPU,	// CLK_VPU;
+	_TGT_AP_CLK_VOC,	// CLK_VOC;
+	_TGT_AP_CLK_SFLSH,	// CLK_SFLSH;
+	0,			// RESERVE;
+
+	/* DDR timings, defined in target */
+	DDR_CHAN_1_VALID_VAL,	// DDR_CHAN_1_VALID;
+	DDR_TIMING_100H_VAL,	// DDR_TIMING_18BH;
+	DDR_TIMING_101H_VAL,	// DDR_TIMING_101H;
+	DDR_TIMING_102H_VAL,	// DDR_TIMING_102H;
+	DDR_TIMING_103H_VAL,	// DDR_TIMING_103H;
+	DDR_TIMING_104H_VAL,	// DDR_TIMING_104H;
+	DDR_TIMING_105H_VAL,	// DDR_TIMING_105H;
+	DDR_TIMING_106H_VAL,	// DDR_TIMING_106H;
+	DDR_TIMING_107H_VAL,	// DDR_TIMING_107H;
+	DDR_TIMING_108H_VAL,	// DDR_TIMING_108H;
+	DDR_TIMING_109H_VAL,	// DDR_TIMING_109H;
+	DDR_TIMING_10AH_VAL,	// DDR_TIMING_10AH;
+	DDR_TIMING_10BH_VAL,	// DDR_TIMING_10BH;
+
+	DDR_CHAN_2_VALID_VAL,	// DDR_CHAN_2_VALID;
+	DDR_TIMING_120H_VAL,	// DDR_TIMING_18BH;
+	DDR_TIMING_121H_VAL,	// DDR_TIMING_121H;
+	DDR_TIMING_122H_VAL,	// DDR_TIMING_122H;
+	DDR_TIMING_123H_VAL,	// DDR_TIMING_123H;
+	DDR_TIMING_124H_VAL,	// DDR_TIMING_124H;
+	DDR_TIMING_125H_VAL,	// DDR_TIMING_125H;
+	DDR_TIMING_126H_VAL,	// DDR_TIMING_126H;
+	DDR_TIMING_127H_VAL,	// DDR_TIMING_127H;
+	DDR_TIMING_128H_VAL,	// DDR_TIMING_128H;
+	DDR_TIMING_129H_VAL,	// DDR_TIMING_129H;
+	DDR_TIMING_12AH_VAL,	// DDR_TIMING_12AH;
+	DDR_TIMING_12BH_VAL,	// DDR_TIMING_12BH;
+
+	DDR_CHAN_3_VALID_VAL,	// DDR_CHAN_3_VALID;
+	DDR_TIMING_140H_VAL,	// DDR_TIMING_18BH;
+	DDR_TIMING_141H_VAL,	// DDR_TIMING_141H;
+	DDR_TIMING_142H_VAL,	// DDR_TIMING_142H;
+	DDR_TIMING_143H_VAL,	// DDR_TIMING_143H;
+	DDR_TIMING_144H_VAL,	// DDR_TIMING_144H;
+	DDR_TIMING_145H_VAL,	// DDR_TIMING_145H;
+	DDR_TIMING_146H_VAL,	// DDR_TIMING_146H;
+	DDR_TIMING_147H_VAL,	// DDR_TIMING_147H;
+	DDR_TIMING_148H_VAL,	// DDR_TIMING_148H;
+	DDR_TIMING_149H_VAL,	// DDR_TIMING_149H;
+	DDR_TIMING_14AH_VAL,	// DDR_TIMING_14AH;
+	DDR_TIMING_14BH_VAL,	// DDR_TIMING_14BH;
+
+	DDR_CHAN_4_VALID_VAL,	// DDR_CHAN_4_VALID;
+	DDR_TIMING_160H_VAL,	// DDR_TIMING_160H;
+	DDR_TIMING_161H_VAL,	// DDR_TIMING_161H;
+	DDR_TIMING_162H_VAL,	// DDR_TIMING_162H;
+	DDR_TIMING_163H_VAL,	// DDR_TIMING_163H;
+	DDR_TIMING_164H_VAL,	// DDR_TIMING_164H;
+	DDR_TIMING_165H_VAL,	// DDR_TIMING_165H;
+	DDR_TIMING_166H_VAL,	// DDR_TIMING_166H;
+	DDR_TIMING_167H_VAL,	// DDR_TIMING_167H;
+	DDR_TIMING_168H_VAL,	// DDR_TIMING_168H;
+	DDR_TIMING_169H_VAL,	// DDR_TIMING_169H;
+	DDR_TIMING_16AH_VAL,	// DDR_TIMING_16AH;
+	DDR_TIMING_16BH_VAL,	// DDR_TIMING_16BH;
+
+	DDR_TIMING_180H_VAL,	// DDR_TIMING_180H;
+	DDR_TIMING_181H_VAL,	// DDR_TIMING_181H;
+	DDR_TIMING_182H_VAL,	// DDR_TIMING_182H;
+	DDR_TIMING_183H_VAL,	// DDR_TIMING_183H;
+	DDR_TIMING_184H_VAL,	// DDR_TIMING_184H;
+	DDR_TIMING_185H_VAL,	// DDR_TIMING_185H;
+	DDR_TIMING_186H_VAL,	// DDR_TIMING_186H;
+	DDR_TIMING_187H_VAL,	// DDR_TIMING_187H;
+	DDR_TIMING_188H_VAL,	// DDR_TIMING_188H;
+	DDR_TIMING_189H_VAL,	// DDR_TIMING_189H;
+	DDR_TIMING_18AH_VAL,	// DDR_TIMING_18AH;
+	DDR_TIMING_18BH_VAL,	// DDR_TIMING_18BH;
+	DDR_TIMING_18CH_VAL,	// DDR_TIMING_18CH;
+};
+
+struct clock_config *get_default_clock_config(void)
+{
+#ifndef TARGET_TOOL
+	BUILD_BUG_ON(sizeof(struct clock_config) > AP_FACTORY_CLOCK_CFG_LEN);
+#endif
+
+	return &clock_default_config;
+}
+
diff --git a/board/rda/rda8810/clock_config.h b/board/rda/rda8810/clock_config.h
new file mode 100644
index 0000000000..0c83efa678
--- /dev/null
+++ b/board/rda/rda8810/clock_config.h
@@ -0,0 +1,115 @@
+#ifndef __CLOCK_CONFIG_H__
+#define __CLOCK_CONFIG_H__
+
+typedef unsigned long               UINT32;
+typedef unsigned short              UINT16;
+typedef long                        INT32;
+typedef short                       INT16;
+typedef unsigned char               UINT8;
+typedef char                        INT8;
+
+#define CLOCK_VER_MAJOR		1
+#define CLOCK_VER_MINOR		0
+
+struct clock_config {
+	/* Header */
+	UINT32 MAGIC;
+	UINT16 VERSION_MAJOR;
+	UINT16 VERSION_MINOR;
+	/* PLL Freqs (MHz) */
+	UINT32 PLL_FREQ_CPU;	/* 05, 06 */
+	UINT32 PLL_FREQ_BUS;	/* 25, 26 */
+	UINT32 PLL_FREQ_MEM;	/* 65, 66 */
+	UINT32 PLL_FREQ_USB;	/* 85, 86 */
+	/* DDR Flags */
+	UINT16 DDR_CAL;
+	UINT16 DDR_FLAGS;
+	UINT32 DDR_PARA;
+	/* AP sysctrl */
+	UINT16 CLK_CPU;
+	UINT16 CLK_AXI;
+	UINT16 CLK_GCG;
+	UINT16 CLK_AHB1;
+	UINT16 CLK_APB1;
+	UINT16 CLK_APB2;
+	UINT16 CLK_MEM;
+	UINT16 CLK_GPU;
+	UINT16 CLK_VPU;
+	UINT16 CLK_VOC;
+	UINT16 CLK_SFLSH;
+	UINT16 RESERVE;
+	/* DDR timings */
+	UINT16 DDR_CHAN_1_VALID;
+	UINT16 DDR_TIMING_100H;
+	UINT16 DDR_TIMING_101H;
+	UINT16 DDR_TIMING_102H;
+	UINT16 DDR_TIMING_103H;
+	UINT16 DDR_TIMING_104H;
+	UINT16 DDR_TIMING_105H;
+	UINT16 DDR_TIMING_106H;
+	UINT16 DDR_TIMING_107H;
+	UINT16 DDR_TIMING_108H;
+	UINT16 DDR_TIMING_109H;
+	UINT16 DDR_TIMING_10AH;
+	UINT16 DDR_TIMING_10BH;
+
+	UINT16 DDR_CHAN_2_VALID;
+	UINT16 DDR_TIMING_120H;
+	UINT16 DDR_TIMING_121H;
+	UINT16 DDR_TIMING_122H;
+	UINT16 DDR_TIMING_123H;
+	UINT16 DDR_TIMING_124H;
+	UINT16 DDR_TIMING_125H;
+	UINT16 DDR_TIMING_126H;
+	UINT16 DDR_TIMING_127H;
+	UINT16 DDR_TIMING_128H;
+	UINT16 DDR_TIMING_129H;
+	UINT16 DDR_TIMING_12AH;
+	UINT16 DDR_TIMING_12BH;
+
+	UINT16 DDR_CHAN_3_VALID;
+	UINT16 DDR_TIMING_140H;
+	UINT16 DDR_TIMING_141H;
+	UINT16 DDR_TIMING_142H;
+	UINT16 DDR_TIMING_143H;
+	UINT16 DDR_TIMING_144H;
+	UINT16 DDR_TIMING_145H;
+	UINT16 DDR_TIMING_146H;
+	UINT16 DDR_TIMING_147H;
+	UINT16 DDR_TIMING_148H;
+	UINT16 DDR_TIMING_149H;
+	UINT16 DDR_TIMING_14AH;
+	UINT16 DDR_TIMING_14BH;
+
+	UINT16 DDR_CHAN_4_VALID;
+	UINT16 DDR_TIMING_160H;
+	UINT16 DDR_TIMING_161H;
+	UINT16 DDR_TIMING_162H;
+	UINT16 DDR_TIMING_163H;
+	UINT16 DDR_TIMING_164H;
+	UINT16 DDR_TIMING_165H;
+	UINT16 DDR_TIMING_166H;
+	UINT16 DDR_TIMING_167H;
+	UINT16 DDR_TIMING_168H;
+	UINT16 DDR_TIMING_169H;
+	UINT16 DDR_TIMING_16AH;
+	UINT16 DDR_TIMING_16BH;
+
+	UINT16 DDR_TIMING_180H;
+	UINT16 DDR_TIMING_181H;
+	UINT16 DDR_TIMING_182H;
+	UINT16 DDR_TIMING_183H;
+	UINT16 DDR_TIMING_184H;
+	UINT16 DDR_TIMING_185H;
+	UINT16 DDR_TIMING_186H;
+	UINT16 DDR_TIMING_187H;
+	UINT16 DDR_TIMING_188H;
+	UINT16 DDR_TIMING_189H;
+	UINT16 DDR_TIMING_18AH;
+	UINT16 DDR_TIMING_18BH;
+	UINT16 DDR_TIMING_18CH;
+};
+
+struct clock_config *get_default_clock_config(void);
+
+#endif
diff --git a/board/rda/rda8810/config.mk b/board/rda/rda8810/config.mk
new file mode 100644
index 0000000000..5c279539fd
--- /dev/null
+++ b/board/rda/rda8810/config.mk
@@ -0,0 +1,13 @@
+#
+#the spl code should not exceed the SPL_MAX_SIZE,and if 
+#the spl don't up to the max size, paddint the last with
+#zero(or 0xff?)
+
+#48kbytes, 48*1024
+#SPL_APPENDING_TO	:= 48
+#SPL_MAX_SIZE	:= 49512
+
+# space for spl(48KiB) & mtd partition table(24KiB)
+SPL_APPENDING_TO   := 72
+
+CONFIG_SPL_SIGNATURE_CHECK_IMAGE := y
diff --git a/board/rda/rda8810/ddr3.c b/board/rda/rda8810/ddr3.c
new file mode 100644
index 0000000000..bb7ef9a5b2
--- /dev/null
+++ b/board/rda/rda8810/ddr3.c
@@ -0,0 +1,524 @@
+#include <common.h>
+#include <asm/arch/rda_iomap.h>
+
+#include "ddr3.h"
+#include "ddr3_init.h"
+#include <rda/tgt_ap_clock_config.h>
+
+#pragma GCC push_options
+#pragma GCC optimize ("O0")
+
+#define DDR_TYPE _TGT_AP_DDR_TYPE
+
+#define DF_DELAY  (0x10000)
+
+#define DMC_REG_BASE RDA_DMC400_BASE
+#define PHY_REG_BASE RDA_DDRPHY_BASE
+
+#define  PHY_RDLAT          0
+#define  PHYWRDATA          1
+#define  STA                3
+#define  CLKSEL             4
+#define  PSSTART            5
+#define  PSDONE             6
+#define  LOCKED             6
+#define  CTRL_DELAY         7
+#define  RDELAY_SEL         8
+#define  WDELAY_SEL         9
+#define  PHY_RESET          10
+#define  RESET_DDR3         11
+#define  ODT_DELAY          12
+#define  DDR3_USED          13
+#define  WRITE_ENABLE_LAT   14
+#define  WRITE_DATA_LAT     15
+#define  DQOUT_ENABLE_LAT   16
+#define  DATA_ODT_ENABLE_REG 20
+#define  DATA_WRITE_ENABLE_REG   48
+#define  USE_ADDR   129
+
+#define ARRAY_NUM(n) (sizeof(n))/(sizeof(n[0]))
+#define debug_ddr3(fmt, args...)		\
+	do {					\
+		if (g_debug_ddr3)		\
+			printf(fmt, ##args);	\
+	} while (0)
+UINT8 g_debug_ddr3 = 1;
+
+#if (DDR_TYPE == 1)
+static dmc_reg_t dmc_reg_cfg[] = {
+	{T_REFI,	0x186,		0x186},
+	{T_RFC,		0x230024,	0x230024},
+	{T_RFC,		0x540024,	0x540024},
+	{T_MRR,		0x2,		0x2},
+	{T_MRW,		0x5,		0x5},
+	{T_RCD,		0x8,		0x8},
+	{T_RAS,		0x11,		0x11},
+	{T_RP,		0x8,		0x8},
+	{T_RPALL,	0x9,		0x9},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0x4,		0x4},
+	{T_RTW,		0xb,		0xb},
+	{T_RTP,		0x6,		0x6},
+	{T_WR,		0xe,		0xe},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTW,		0x40000,	0x40000},
+	{RD_LATENCY,	0x6,		0x6},
+	{WR_LATENCY,	0x3,		0x3},
+	{T_RDDATA_EN,	0x3,		0x3},
+	{T_PHYWRLAT,	0x101,		0x101},
+	{T_PHYWRLAT,	0x101,		0x101},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0x80003,	0x80003},
+	{T_ESR,		0x6,		0x6},
+	{T_XSR,		0x1000058,	0x1000058},
+	{T_XSR,		0x580058,	0x580058},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{T_EP,		0x5,		0x5},
+	{RDLVL_CTRL,	0x1010,		0x1010},
+	{RDLVL_CTRL,	0x1110,		0x1110},
+	{RDLVL_CTRL,	0x11110,	0x11110},
+	{REFRESH_CTRL,	0x0,		0x0},
+	{REFRESH_CTRL,	0x0,		0x0},
+	{ECC_CTRL,	0x0,		0x0},
+	{QOSX_CTRL7,	0x0f, 		0x0f},
+	{TURNAROUND_PRIO,0x1A, 		0x1A},
+	{HIT_PRIO,	0x1A, 		0x1A},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+};
+#elif (DDR_TYPE == 2)
+static dmc_reg_t dmc_reg_cfg[] = {
+	{T_REFI,	0x3f,		0x3f},
+	{T_RFC,		0x230024,	0x230024},
+	{T_RFC,		0x540024,	0x540024},
+	{T_MRR,		0x2,		0x2},
+	{T_MRW,		0x5,		0x5},
+	{T_RCD,		0x8,		0x8},
+	{T_RAS,		0x11,		0x11},
+	{T_RP,		0x8,		0x8},
+	{T_RPALL,	0x9,		0x9},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0x4,		0x4},
+	{T_RTW,		0x1f/*0xb*/,		0x1f/*0xb*/},
+	{T_RTP,		0x6,		0x6},
+	{T_WR,		0xe,		0xe},
+	{T_WTR,		0x1f001f/*0x4000b*/,	0x1f001f/*0x4000b*/},
+	{T_WTR,		0x1f001f/*0x4000b*/,	0x1f001f/*0x4000b*/},
+	{T_WTW,		0x40000,	0x40000},
+	{RD_LATENCY,	0x8/*0x6*/,		0x8/*0x6*/},
+	{WR_LATENCY,	0x4/*0x3*/,		0x4/*0x3*/},
+	{T_RDDATA_EN,	0x8/*0x3*/,		0x8/*0x3*/},
+	{T_PHYWRLAT,	0x104/*0x101*/,		0x104/*0x101*/},
+	{T_PHYWRLAT,	0x104/*0x103*/,		0x104/*0x103*/},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0x80003,	0x80003},
+	{T_ESR,		0x6,		0x6},
+	{T_XSR,		0x1000058,	0x1000058},
+	{T_XSR,		0x580058,	0x580058},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{T_EP,		0x5,		0x5},
+	{RDLVL_CTRL,	0x1010,		0x1010},
+	{RDLVL_CTRL,	0x1110,		0x1110},
+	{RDLVL_CTRL,	0x11110,	0x11110},
+	{REFRESH_CTRL,	0x1,		0x1},
+	{ECC_CTRL,	0x0,		0x0},
+	{QOSX_CTRL7,	0x0f, 		0x0f},
+	{TURNAROUND_PRIO,0x1A, 		0x1A},
+	{HIT_PRIO,	0x1A, 		0x1A},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+};
+#elif (DDR_TYPE == 3)
+static dmc_reg_t dmc_reg_cfg[] = {
+	{T_REFI,	0x186,		0x3f},
+	{T_RFC,		0x23008c,	0x23008c},
+	{T_RFC,		0x8c008c,	0x8c008c},
+	{T_MRR,		0x4,		0x4},
+	{T_MRW,		0xc,		0xc},
+	{T_RCD,		0x6,		0x5},
+	{T_RAS,		0xf,		0xf},
+	{T_RP,		0x6,		0x5},
+	{T_RPALL,	0x6,		0x5},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0x6,		0x6},
+//	{T_RTW,		0x7,		0x6},
+	{T_RTW,		0x0e,		0x0c},// turn for now
+//	{T_RTW,		0x1f,		0x1f},//for low speed
+	{T_RTP,		0x4,		0x4},
+	{T_WR,		0xf,		0x10},
+	{T_WTR,		0x4000d,	0x4000d},
+	{T_WTR,		0x6000d,	0x6000f},
+//	{T_WTR,		0x6001f,	0x6001f},//for low speed
+	{T_WTW,		0x60000,	0x60000},
+	{RD_LATENCY,	0x5,		0x5},
+	{WR_LATENCY,	0x5,		0x5},
+	{T_RDDATA_EN,	0x8,		0x1},
+	{T_PHYWRLAT,	0x103,		0x103},
+	{T_PHYWRLAT,	0x103,		0x104},
+	{T_EP,		0x3,		0x3},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0xa0003,	0xa0003},
+	{T_ESR,		0x4,		0x4},
+	{T_XSR,		0x1000090,	0x1000090},
+	{T_XSR,		0x2000090,	0x2000090},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{ECC_CTRL,	0x0,		0x0},
+	{QOSX_CTRL7,	0x0f, 		0x0f},
+	{TURNAROUND_PRIO,0x1A, 		0x1A},
+	{HIT_PRIO,	0x1A, 		0x1A},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+};
+#else
+#error "Wrong DDR Type"
+#endif
+
+void config_ddr_phy(UINT16 flag)
+{
+	int wait_idle;
+	UINT16 __attribute__((unused)) dll_off;
+
+	wait_idle = DF_DELAY + 16;
+	dll_off = flag & DDR_FLAGS_DLLOFF;
+
+	while (wait_idle--);
+
+#if (DDR_TYPE == 1)
+	*((volatile UINT32*)(PHY_REG_BASE + CTRL_DELAY * 4)) = 1;
+	debug_ddr3("ddr1 phy init done!\n");
+#elif (DDR_TYPE ==2)
+	*((volatile UINT32*)(PHY_REG_BASE + USE_ADDR * 4)) = 0;
+	*((volatile UINT32*)(PHY_REG_BASE + DATA_WRITE_ENABLE_REG *4))  = 0xf;
+	*((volatile UINT32*)(PHY_REG_BASE + DATA_ODT_ENABLE_REG *4))  = 0xf;
+	*((volatile UINT32*)(PHY_REG_BASE + WRITE_DATA_LAT *4))  = 0x0;
+	*((volatile UINT32*)(PHY_REG_BASE + WRITE_ENABLE_LAT *4))  = 0x0;
+	*((volatile UINT32*)(PHY_REG_BASE + WDELAY_SEL *4))  = 0x5;
+	*((volatile UINT32*)(PHY_REG_BASE + RDELAY_SEL *4))  = 0x6;
+	*((volatile UINT32*)(PHY_REG_BASE + DQOUT_ENABLE_LAT *4))  = 0x0;
+
+	debug_ddr3("ddr2 phy init done!\n");
+#else
+	*((volatile UINT32*)(PHY_REG_BASE + RESET_DDR3 * 4)) = 1;
+	*((volatile UINT32*)(PHY_REG_BASE + WRITE_DATA_LAT * 4)) = 1;
+	*((volatile UINT32*)(PHY_REG_BASE + DDR3_USED * 4)) = 1;
+	if (!dll_off)
+	*((volatile UINT32*)(PHY_REG_BASE + RDELAY_SEL * 4)) = 2;
+	*((volatile UINT32*)(PHY_REG_BASE + WDELAY_SEL * 4)) = 3;
+	*((volatile UINT32*)(PHY_REG_BASE + DQOUT_ENABLE_LAT * 4)) = 1;
+	*((volatile UINT32*)(PHY_REG_BASE + DATA_WRITE_ENABLE_REG *4))  = (3<<2);
+	*((volatile UINT32*)(PHY_REG_BASE + DATA_ODT_ENABLE_REG *4))  = (3<<2);
+	debug_ddr3("ddr3 phy init done!\n");
+#endif
+}
+
+void config_dmc400(UINT16 flag, UINT32 para)
+{
+	int i, wait_idle;
+	UINT32 val, tmp;
+	volatile UINT32 *addr;
+	UINT16 __attribute__((unused)) dll_off, lpw, odt, ron;
+	UINT32 mem_width, col_bits, row_bits, bank_bits;
+
+	dll_off = flag & DDR_FLAGS_DLLOFF;
+	lpw = flag & DDR_FLAGS_LOWPWR;
+	odt = (flag & DDR_FLAGS_ODT_MASK) >> DDR_FLAGS_ODT_SHIFT;
+	ron = (flag & DDR_FLAGS_RON_MASK) >> DDR_FLAGS_RON_SHIFT;
+	mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;
+	bank_bits = (para & DDR_PARA_BANK_BITS_MASK) >> DDR_PARA_BANK_BITS_SHIFT;
+	row_bits = (para & DDR_PARA_ROW_BITS_MASK) >> DDR_PARA_ROW_BITS_SHIFT;
+	col_bits = (para & DDR_PARA_COL_BITS_MASK) >> DDR_PARA_COL_BITS_SHIFT;
+
+
+	wait_idle = 0x4e;
+	while (wait_idle--);
+
+	for (i=0; i<ARRAY_NUM(dmc_reg_cfg); i++) {
+		addr = (volatile UINT32*)(DMC_REG_BASE + dmc_reg_cfg[i].reg_offset);
+		if (dll_off)
+			val = dmc_reg_cfg[i].dll_off_val;
+		else
+			val = dmc_reg_cfg[i].dll_on_val;
+
+		*addr = val;
+		wait_idle = 0x5;
+		while (wait_idle--);
+	}
+
+#if (DDR_TYPE == 3)
+	//config low power control register
+	if (lpw) {
+		addr = (volatile UINT32*)(DMC_REG_BASE + LOWPWR_CTRL);//0x20
+		*addr = 0x48;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_ESR);//0x260
+		*addr = 0xa;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_XSR);//0x264
+		*addr = 0x200;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_SRCKD);//0x268
+		*addr = 0xa;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_CKSRD);//0x26C
+		*addr = 0xa;
+		wait_idle = 0x5;
+		while (wait_idle--);	
+	}
+#elif (DDR_TYPE == 2)
+	addr = (volatile UINT32*)(DMC_REG_BASE + LOWPWR_CTRL);//0x20
+	*addr = 0x38;
+	wait_idle = 0x5;
+	while (wait_idle--);
+#endif
+
+	//config format control register
+	addr = (volatile UINT32*)(DMC_REG_BASE + FORMAT_CTRL);
+	val = *addr;
+	val &= ~0xf;
+	if (mem_width == 2)
+		val |= 0x2; //for 32bit DDR
+	else if ((mem_width == 1) || (mem_width == 0))
+		val |= 0x1; //for 16bit & 8bit DDR
+	else
+		debug_ddr3("unsupported DDR width: %lx\n", mem_width);
+	*addr = val;
+
+	debug_ddr3("format ctrl value: %lx\n", val);
+
+	wait_idle = 0x1d;
+	while (wait_idle--);
+
+	//config address control register
+	addr = (volatile UINT32*)(DMC_REG_BASE + ADDR_CTRL);
+	if (mem_width == 2)
+		tmp = col_bits; //for 32bit
+	else if (mem_width == 1)
+		tmp = col_bits - 1; //for 16bit
+	else if (mem_width == 0)
+		tmp = col_bits - 2; //for 8bit
+	else {
+		debug_ddr3("unsupported DDR width: %lx\n", mem_width);
+		tmp = col_bits;
+	}
+	val = (bank_bits << 16) | (row_bits << 8) | tmp;
+
+	*addr = val;
+
+	debug_ddr3("address ctrl value: %lx\n", val);
+	wait_idle = 0x5;
+	while (wait_idle--);
+
+	//config decode control register
+	addr = (volatile UINT32*)(DMC_REG_BASE + DECODE_CTRL);
+	tmp = 12 - (8 + col_bits + mem_width);
+	if (tmp < 8)
+		val = tmp << 4;
+	else
+		debug_ddr3("unsupported stripe decode: %lx\n", tmp);
+	*addr = val;
+
+	debug_ddr3("decode ctrl value: %lx\n", val);
+	wait_idle = 0x6;
+	while (wait_idle--);
+
+	wait_idle = DF_DELAY;
+	while (wait_idle--);
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+	*addr = 0x0;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0;
+#elif (DDR_TYPE == 2)
+	val = 0;
+#else
+	//config MR2
+	if (dll_off)
+		val = 0x10020008;
+	else
+		val = 0x10020000;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x6;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x20000000;
+#elif (DDR_TYPE == 2)
+	val = 0x1000003f;
+#else
+	//config MR3
+	val = 0x10030000;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x30000000;
+#elif (DDR_TYPE == 2)
+	val = 0x1000ff0a;
+#else
+	//config MR1 ODT [9,6,2] RON [5,1] DLLOFF [0]
+	val = 0x10010000;
+	val |= (odt & 0x4)<<7 | (odt & 0x2)<<5 | (odt & 0x1)<<2;
+	val |= (ron & 0x2)<<4 | (ron & 0x1)<<1;
+	if (dll_off)
+		val |= 0x1;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x30000000;
+#elif (DDR_TYPE == 2)
+	val = 0x10008301;
+#else
+	//config MR0
+	val = 0x10000520;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x6;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x10000033;
+#elif (DDR_TYPE == 2)
+	//val = 0x10000402;//0ld 0x10000102
+	val = 0x10000602;//0ld 0x10000102
+#else
+	val = 0x50000400;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x6;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x10020000;
+#elif (DDR_TYPE == 2)
+	val = 0x30000000;
+#else
+	val = 0x30000000;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x9;
+	while (wait_idle--);
+
+#if (DDR_TYPE == 2)
+/* zhangli for MCP */
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+	*addr = 0x10000403;
+	wait_idle = DF_DELAY + 0x9;
+	while (wait_idle--);
+#endif
+
+#if (DDR_TYPE == 2)
+	addr = (volatile UINT32*)(DMC_REG_BASE + MEMC_CMD);
+	val = 0x4;
+	*addr = val;
+	wait_idle = 0x5;
+	while (wait_idle--);
+#endif
+
+	//config ECC control
+	addr = (volatile UINT32*)(DMC_REG_BASE + ECC_CTRL);
+	val = 0x0;
+	*addr = val;
+	wait_idle = 0x4f;
+	while (wait_idle--);
+
+	//config MEMC CMD
+	addr = (volatile UINT32*)(DMC_REG_BASE + MEMC_CMD);
+	val = 0x3;
+	*addr = val;
+	wait_idle = 0x8;
+	while (wait_idle--);
+
+	//READ MEMC STATUS
+	addr = (volatile UINT32*)(DMC_REG_BASE + MEMC_STATUS);
+	val = 0;
+	do {
+		val = *addr;
+		//debug_ddr3("MEMC_STATUS value: %x\n", val);
+	} while (val != 3);
+}
+
+void axi_prio_init(void)
+{
+	*(volatile UINT32*)(0x20900100) = 0xaa0000aa;
+	*(volatile UINT32*)(0x21054100) = 0x00000008;
+	*(volatile UINT32*)(0x21054104) = 0x00000008;
+}
+
+void axi_outstandings_init(void)
+{
+	*(volatile UINT32*)(0x2105110C) = 0x00000060;
+	*(volatile UINT32*)(0x21051110) = 0x00000300;
+}
+
+int ddr_init(UINT16 flags, UINT32 para)
+{
+	UINT16 dll_off;
+	UINT32 mem_width;
+
+	axi_prio_init();
+	axi_outstandings_init();
+
+	dll_off = flags & DDR_FLAGS_DLLOFF;
+	mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;
+
+	switch (mem_width) {
+		case 0:
+			debug_ddr3("8bit ");
+			break;
+		case 1:
+			debug_ddr3("16bit ");
+			break;
+		case 2:
+			debug_ddr3("32bit ");
+			break;
+	}
+	if (dll_off)
+		debug_ddr3("dll-off Mode ...\n");
+	else
+		debug_ddr3("dll-on Mode ...\n");
+
+	config_ddr_phy(flags);
+	config_dmc400(flags, para);
+	debug_ddr3("dram init done ...\n");
+
+	return 0;
+}
+
diff --git a/board/rda/rda8810/ddr3.h b/board/rda/rda8810/ddr3.h
new file mode 100644
index 0000000000..7481954144
--- /dev/null
+++ b/board/rda/rda8810/ddr3.h
@@ -0,0 +1,50 @@
+#ifndef _SYS_DDR3_H_
+#define _SYS_DDR3_H_
+
+#include "clock_config.h"
+
+/*
+ * defination of ddr flags
+ */
+/* [Debug] DLL off mode, 0 is dll on mode */
+#define DDR_FLAGS_DLLOFF               0x8000
+/* [Debug] LowSpeed mode*/
+#define DDR_FLAGS_RESERVE              0x4000
+/* DDR LowPower mode */
+#define DDR_FLAGS_LOWPWR               0x2000
+/* ODT: 000--Null 001--60 010--120 011--40 100--20 101--30 */
+#define DDR_FLAGS_ODT(n)               (((n)<<0)&0x0007)
+#define DDR_FLAGS_ODT_SHIFT            0
+#define DDR_FLAGS_ODT_MASK             0x0007
+/* RON: 00--40 01--30 */
+#define DDR_FLAGS_RON(n)               (((n)<<3)&0x0018)
+#define DDR_FLAGS_RON_SHIFT            3
+#define DDR_FLAGS_RON_MASK             0x0018
+
+/*
+ * defination of ddr parameters
+ */
+#define DDR_PARA_CHIP_BITS(n)          (((n)<<0)&0x00000003)
+#define DDR_PARA_CHIP_BITS_SHIFT       0
+#define DDR_PARA_CHIP_BITS_MASK        0x00000003
+/* memory width 0--8bit 1--16bit 2--32bit */
+#define DDR_PARA_MEM_BITS(n)           (((n)<<2)&0x0000000c)
+#define DDR_PARA_MEM_BITS_SHIFT        2
+#define DDR_PARA_MEM_BITS_MASK         0x0000000c
+/* 2--4banks 3--8banks */
+#define DDR_PARA_BANK_BITS(n)          (((n)<<4)&0x000000f0)
+#define DDR_PARA_BANK_BITS_SHIFT       4
+#define DDR_PARA_BANK_BITS_MASK        0x000000f0
+/* 2--13rbs 3--14rbs 4--15rbs 5--16rbs */
+#define DDR_PARA_ROW_BITS(n)           (((n)<<8)&0x00000f00)
+#define DDR_PARA_ROW_BITS_SHIFT        8
+#define DDR_PARA_ROW_BITS_MASK         0x00000f00
+/* 0--8cbs 1--9cbs 2--10cbs 3--11cbs 4--12cbs */
+#define DDR_PARA_COL_BITS(n)           (((n)<<12)&0x0000f000)
+#define DDR_PARA_COL_BITS_SHIFT        12
+#define DDR_PARA_COL_BITS_MASK         0x0000f000
+
+int ddr_init(UINT16 flags, UINT32 para);
+
+#endif /* _SYS_DDR3_H_ */
+
diff --git a/board/rda/rda8810/ddr3_init.h b/board/rda/rda8810/ddr3_init.h
new file mode 100644
index 0000000000..402375d269
--- /dev/null
+++ b/board/rda/rda8810/ddr3_init.h
@@ -0,0 +1,101 @@
+#ifndef _SYS_RAM_INIT_H_
+#define _SYS_RAM_INIT_H_
+
+#define MEMC_STATUS			0x000
+#define MEMC_CONFIG			0x004
+#define MEMC_CMD			0x008
+#define ADDR_CTRL			0x010
+#define DECODE_CTRL			0x014
+#define FORMAT_CTRL			0x018
+#define LOWPWR_CTRL			0x020
+#define TURNAROUND_PRIO			0x030
+#define HIT_PRIO			0x034
+//QOS0~QOS15:038~078
+#define QOSX_CTRL			0x038
+#define QOSX_CTRL7			0x058
+#define QOSX_CTRL15			0x078
+#define TIMEOUT_CTRL			0x07C
+#define QUEUE_CTRL			0x080
+#define WR_PRIO_CTRL			0x088
+#define WR_PRIO_CTRL2			0x08C
+#define RD_PRIO_CTRL			0x090
+#define RD_PRIO_CTRL2			0x094
+#define ACCESS_ADDR_MATCH		0x098
+#define ACCESS_ADDR_MATCH_63_32		0x09C
+#define ACCESS_ADDR_MASK		0x0A0
+#define ACCESS_ADDR_MASK_63_32		0x0A4
+
+#define CHANNEL_STATUS			0x100
+#define DIRECT_CMD			0x108
+#define MR_DATA				0x110
+#define REFRESH_CTRL			0x120
+#define INTR_CTRL			0x128
+#define INTR_CLR			0x130
+#define INTR_STATUS			0x138
+#define INTR_INFO			0x140
+#define ECC_CTRL			0x148
+
+#define T_REFI				0x200
+#define T_RFC				0x204
+#define T_MRR				0x208
+#define T_MRW				0x20C
+#define T_RCD				0x218
+#define T_RAS				0x21C
+#define T_RP				0x220
+#define T_RPALL				0x224
+#define T_RRD				0x228
+#define T_FAW				0x22C
+#define RD_LATENCY			0x230
+#define T_RTR				0x234
+#define T_RTW				0x238
+#define T_RTP				0x23C
+#define WR_LATENCY			0x240
+#define T_WR				0x244
+#define T_WTR				0x248
+#define T_WTW				0x24C
+#define T_ECKD				0x250
+#define T_XCKD				0x254
+#define T_EP				0x258
+#define T_XP				0x25C
+#define T_ESR				0x260
+#define T_XSR				0x264
+#define T_SRCKD				0x268
+#define T_CKSRD				0x26C
+
+#define T_RDDATA_EN			0x300
+#define T_PHYWRLAT			0x304
+#define RDLVL_CTRL			0x308
+#define RDLVL_DIRECT			0x310
+#define T_RDLVL_EN			0x318
+#define T_RDLVL_RR			0x31C
+#define WRLVL_CTRL			0x328
+#define WRLVL_DIRECT			0x330
+#define T_WRLVL_EN			0x338
+#define T_WRLVL_WW			0x33C
+
+#define PHY_PWR_CTRL			0x348
+#define PHY_UPD_CTRL			0x350
+
+#define USER_STATUS			0x400
+#define USER_CONFIG0			0x404
+#define USER_CONFIG1			0x408
+
+#define INTEG_CFG			0xE00
+#define INTEG_OUTPUTS			0xE08
+
+#define PERIPH_ID_0			0xFE0
+#define PERIPH_ID_1			0xFE4
+#define PERIPH_ID_2			0xFE8
+#define PERIPH_ID_3			0xFEC
+#define COMPONENT_ID_0			0xFF0
+#define COMPONENT_ID_1			0xFF4
+#define COMPONENT_ID_2			0xFF8
+#define COMPONENT_ID_3			0xFFC
+
+typedef struct {
+	UINT32 reg_offset;
+	UINT32 dll_on_val;
+	UINT32 dll_off_val;
+} dmc_reg_t;
+
+#endif /* _SYS_RAM_INIT_H_ */
diff --git a/board/rda/rda8810/debug.h b/board/rda/rda8810/debug.h
new file mode 100644
index 0000000000..1d4f03bedb
--- /dev/null
+++ b/board/rda/rda8810/debug.h
@@ -0,0 +1,9 @@
+#ifndef _DEBUG_H_
+#define _DEBUG_H_
+
+void print_u8(u8 ch);
+void print_u16(u16 data);
+void print_u32(u32 data);
+void dump_buf(u8 *buf, u32 size);
+
+#endif /* _DEBUG_H_ */
diff --git a/board/rda/rda8810/hal_config.c b/board/rda/rda8810/hal_config.c
new file mode 100644
index 0000000000..294fbdf856
--- /dev/null
+++ b/board/rda/rda8810/hal_config.c
@@ -0,0 +1,1180 @@
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//            Copyright (C) 2013, RDA Microeletronics.                        //
+//                            All Rights Reserved                             //
+//                                                                            //
+//      This source code is the property of RDA Microeletronics and is        //
+//      confidential.  Any  modification, distribution,  reproduction or      //
+//      exploitation  of  any content of this file is totally forbidden,      //
+//      except  with the  written permission  of  RDA Microeletronics.        //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//  $HeadURL: http://svn.rdamicro.com/svn/developing1/Sources/chip/branches/8810/hal/8810/src/hal_config.c $ //
+//    $Author: huazeng $                                                        //
+//    $Date: 2013-08-31 17:48:58 +0800 (Sat, 31 Aug 2013) $                     //
+//    $Revision: 21005 $                                                          //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+/// @file hal_config.c
+/// Implementation of HAL initialization related with the particular instance
+/// of the IP.
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+
+/* uboot */
+#include <common.h>
+
+/* common */
+#include <asm/arch/rda_iomap.h>
+#include <asm/arch/hwcfg.h>
+#include <asm/arch/chip_id.h>
+#include <asm/arch/cs_types.h>
+#include <asm/arch/global_macros.h>
+#include <asm/arch/reg_gpio.h>
+
+/* device */
+#include "hal_sys.h"
+#include "halp_sys.h"
+#include "halp_gpio.h"
+#include "bootp_mode.h"
+#include "hal_config.h"
+#include "hal_ap_gpio.h"
+#include "hal_ap_config.h"
+#include <asm/arch/reg_cfg_regs.h>
+
+/* target */
+#include <rda/tgt_board_cfg.h>
+#include <rda/tgt_ap_gpio_setting.h>
+#define HAL_ASSERT(cond, fmt, ...) \
+	if(!(cond)) { \
+		hal_assert(fmt, ##__VA_ARGS__); \
+		g_halConfigError = TRUE; \
+	}
+
+//// =============================================================================
+////  GLOBAL VARIABLES
+//// =============================================================================
+PRIVATE CONST UINT8 g_halCfgSimOrder[] = { TGT_SIM_ORDER };
+PRIVATE HAL_CFG_CONFIG_T hal_cfg = TGT_HAL_CONFIG;
+PRIVATE UINT32 g_bootBootMode = 0;
+PRIVATE BOOL g_halConfigError = FALSE;
+
+
+// =============================================================================
+//  FUNCTIONS
+// =============================================================================
+// HAL_ASSERT
+PRIVATE VOID hal_assert(const char *fmt, ...)
+{
+	va_list args;
+	puts("\n#-------Board Mux config found error-------#\n");
+	va_start(args, fmt);
+	vprintf(fmt, args);
+	putc('\n');
+	puts("--------------------------------------------\n\n");
+	va_end(args);
+}
+
+// =============================================================================
+// hal_BoardSimUsed
+// -----------------------------------------------------------------------------
+/// Check whether a SIM card interface is used.
+// ============================================================================
+PRIVATE BOOL hal_BoardSimUsed(UINT32 simId)
+{
+    UINT32 i;
+    for (i=0; i<ARRAY_SIZE(g_halCfgSimOrder) && i<NUMBER_OF_SIM; i++)
+    {
+        if (g_halCfgSimOrder[i] == simId)
+        {
+            return TRUE;
+        }
+    }
+
+    return FALSE;
+}
+
+#if 0
+// =============================================================================
+// hal_BoardConfigClk32k
+// -----------------------------------------------------------------------------
+/// Configure CLK_32K output.
+/// @param enable TRUE to configure, and FALSE to disable.
+// ============================================================================
+PROTECTED VOID hal_BoardConfigClk32k(BOOL enable)
+{
+    HAL_ASSERT(g_halCfg->useClk32k == TRUE, "32K clock is not configured");
+
+    if (enable)
+    {
+        // Setup the pin as 32K clock output
+        hwp_configRegs->Alt_mux_select =
+            (hwp_configRegs->Alt_mux_select & ~CFG_REGS_GPO_2_MASK) |
+            CFG_REGS_GPO_2_CLK_32K;
+    }
+    else
+    {
+        // Setup the pin as GPO (and low ouput has been
+        // configured in hal_BoardSetup())
+        hwp_configRegs->Alt_mux_select =
+            (hwp_configRegs->Alt_mux_select & ~CFG_REGS_GPO_2_MASK) |
+            CFG_REGS_GPO_2_GPO_2;
+    }
+}
+#endif
+
+// =============================================================================
+// hal_BoardSetupGeneral
+// -----------------------------------------------------------------------------
+/// Apply board dependent configuration to HAL for general purpose
+/// @param halCfg Pointer to HAL configuration structure (from the target
+/// module).
+// ============================================================================
+PROTECTED VOID hal_BoardSetupGeneral(CONST HAL_CFG_CONFIG_T* halCfg)
+{
+    UINT32 altMux = 0;
+
+    UINT32 availableGpo_A = 0;
+
+    UINT32 availableGpio_C = 0;
+    UINT32 availableGpio_A = 0;
+    UINT32 availableGpio_B = 0;
+    UINT32 availableGpio_D = 0;
+
+    UINT32 bootModeGpio_C = 0;
+    UINT32 bootModeGpio_A = 0;
+    UINT32 bootModeGpio_B = 0;
+    UINT32 bootModeGpio_D = 0;
+
+    UINT32 noConnectMask_C = 0;
+    UINT32 noConnectMask_A = 0;
+    UINT32 noConnectMask_B = 0;
+    UINT32 noConnectMask_D = 0;
+
+    UINT32 gpoClr_A = 0;
+
+#ifdef FPGA
+
+    // no muxing, do nothing
+
+#else // !FPGA
+
+    // GPIOs as boot mode pins
+    bootModeGpio_C = HAL_GPIO_BIT(1)
+                   | HAL_GPIO_BIT(2)
+                   | HAL_GPIO_BIT(3)
+                   | HAL_GPIO_BIT(4)
+                   | HAL_GPIO_BIT(5);
+    bootModeGpio_A = HAL_GPIO_BIT(4)
+                   | HAL_GPIO_BIT(5)
+                   | HAL_GPIO_BIT(6)
+                   | HAL_GPIO_BIT(7);
+    bootModeGpio_B = HAL_GPIO_BIT(0);
+    bootModeGpio_D = 0;
+
+    // Available GPIOs
+    availableGpio_C |= HAL_GPIO_BIT(0)
+                     | HAL_GPIO_BIT(1)
+                     | HAL_GPIO_BIT(2)
+                     | HAL_GPIO_BIT(3)
+                     | HAL_GPIO_BIT(4)
+                     | HAL_GPIO_BIT(5);
+    // Volume down/up keys
+    availableGpio_D |= HAL_GPIO_BIT(5)
+                     | HAL_GPIO_BIT(6);
+
+    // Boot modes
+    BOOL spiFlashCam = FALSE;
+    BOOL spiFlashNand = FALSE;
+    if (g_bootBootMode & BOOT_MODE_BOOT_SPI)
+    {
+        if (g_bootBootMode & BOOT_MODE_SPI_PIN_NAND)
+        {
+            HAL_ASSERT((g_bootBootMode & BOOT_MODE_BOOT_EMMC),
+                "Emmc boot pin should be pulled up to boot on SPI flash over NAND pins");
+            spiFlashNand = TRUE;
+        }
+        else
+        {
+            spiFlashCam = TRUE;
+        }
+    }
+
+    UINT32 metalId = rda_metal_id_get();
+    UINT32 emmcBootModeMask;
+    if (metalId < 0x0B)
+    {
+        emmcBootModeMask = BOOT_MODE_BOOT_EMMC
+                         | BOOT_MODE_BOOT_SPI
+                         | BOOT_MODE_BOOT_SPI_NAND;
+    }
+    else
+    {
+        emmcBootModeMask = BOOT_MODE_BOOT_EMMC
+                         | BOOT_MODE_BOOT_SPI;
+    }
+    if ((g_bootBootMode & emmcBootModeMask) == BOOT_MODE_BOOT_EMMC)
+    {
+        // Boot from EMMC
+        HAL_ASSERT(halCfg->sdmmcCfg.sdmmc3Used, "SDMMC3 (EMMC) should be used");
+    }
+
+    if (metalId < 0x0B)
+    {
+        if ( (g_bootBootMode & (BOOT_MODE_BOOT_SPI|BOOT_MODE_BOOT_SPI_NAND))
+             == BOOT_MODE_BOOT_SPI_NAND ||
+             (g_bootBootMode & (BOOT_MODE_BOOT_SPI|BOOT_MODE_NAND_PAGE_SIZE_L))
+             == (BOOT_MODE_BOOT_SPI|BOOT_MODE_NAND_PAGE_SIZE_L)
+           )
+        {
+            // Boot from SDMMC1
+            HAL_ASSERT(halCfg->sdmmcCfg.sdmmcUsed, "SDMMC1 should be used");
+        }
+    }
+
+    // For convenience, we do not consider spiFlashCam at present.
+    // We assume that SPI flash always uses parallel nand pins.
+#if 0
+    BOOL parallelNandUsed = halCfg->parallelNandUsed;
+#else
+    BOOL parallelNandUsed = !spiFlashNand && !halCfg->sdmmcCfg.sdmmc3Used;
+#endif
+    BOOL nand8_15Cam = FALSE;
+    BOOL nand8_15Lcd = FALSE;
+    if ((g_bootBootMode & (BOOT_MODE_BOOT_SPI|BOOT_MODE_BOOT_EMMC)) == 0)
+    {
+        HAL_ASSERT(parallelNandUsed, "Parallel NAND should be used");
+    }
+    if (parallelNandUsed)
+    {
+        HAL_ASSERT(!spiFlashNand, "SPI flash uses parallel NAND pins");
+        HAL_ASSERT(!halCfg->sdmmcCfg.sdmmc3Used,
+            "SDMMC3 (EMMC) uses parallel NAND pins");
+        if ((g_bootBootMode & BOOT_MODE_NAND_8BIT) == 0)
+        {
+            if (g_bootBootMode & BOOT_MODE_NAND_HIGH_PIN_CAM)
+            {
+                HAL_ASSERT(!spiFlashCam, "SPI flash uses NAND 8-15 bits on cam pins");
+                nand8_15Cam = TRUE;
+            }
+            else
+            {
+                nand8_15Lcd = TRUE;
+            }
+        }
+    }
+
+    if (!(parallelNandUsed || spiFlashNand))
+    {
+        availableGpio_B |= HAL_GPIO_BIT(25)
+                         | HAL_GPIO_BIT(26)
+                         | HAL_GPIO_BIT(27)
+                         | HAL_GPIO_BIT(28)
+                         | HAL_GPIO_BIT(29);
+        availableGpio_D |= HAL_GPIO_BIT(4);
+    }
+
+    CONST HAL_CFG_CAM_T *camCfg = &halCfg->camCfg;
+    CONST HAL_LCD_MODE_T lcdMode = halCfg->goudaCfg.lcdMode;
+
+    // LCD
+    if (lcdMode == HAL_LCD_MODE_PARALLEL_16BIT)
+    {
+        HAL_ASSERT(!nand8_15Lcd, "NAND uses LCD 8-15 bits");
+        altMux |= CFG_REGS_LCD_MODE_PARALLEL_16BIT;
+    }
+    else if (lcdMode == HAL_LCD_MODE_DSI)
+    {
+        altMux |= CFG_REGS_LCD_MODE_DSI;
+        availableGpio_A |= HAL_GPIO_BIT(22)
+                         | HAL_GPIO_BIT(23);
+    }
+    else if (lcdMode == HAL_LCD_MODE_RGB_16BIT ||
+             lcdMode == HAL_LCD_MODE_RGB_24BIT)
+    {
+        HAL_ASSERT(!nand8_15Lcd, "NAND uses LCD 8-15 bits");
+        if (lcdMode == HAL_LCD_MODE_RGB_24BIT)
+        {
+            if (halCfg->goudaCfg.lcd16_23Cam)
+            {
+                HAL_ASSERT(
+                    !(camCfg->camMode == HAL_CAM_MODE_PARALLEL &&
+                      (camCfg->camUsed || camCfg->cam1Used)),
+                    "Parallel camera uses LCD 16-23 bits");
+                HAL_ASSERT(
+                    !(halCfg->i2cCfg.i2c2Used && halCfg->i2cCfg.i2c2PinsCam),
+                    "I2C2 uses LCD 22-23 bits");
+                HAL_ASSERT(!spiFlashCam, "SPI flash uses LCD 16-21 bits");
+                HAL_ASSERT(!nand8_15Cam, "NAND uses LCD 16-23 bits");
+                HAL_ASSERT(
+                    !(camCfg->camMode == HAL_CAM_MODE_CSI &&
+                      ((camCfg->camUsed && camCfg->camCsiId == HAL_CAM_CSI_1) ||
+                       (camCfg->cam1Used && camCfg->cam1CsiId == HAL_CAM_CSI_1))),
+                    "Camera CSI1 uses LCD 16-21 bits");
+                altMux |= CFG_REGS_LCD24_CAM_CAM_IO;
+            }
+            else
+            {
+                HAL_ASSERT(!parallelNandUsed, "NAND uses LCD 16-23 bits");
+                HAL_ASSERT(!halCfg->sdmmcCfg.sdmmc3Used, "SDMMC3 uses LCD 16-23 bits");
+                altMux |= CFG_REGS_LCD24_CAM_NAND_IO;
+            }
+        }
+        altMux |= CFG_REGS_LCD_MODE_RGB_24BIT;
+    }
+    else if (lcdMode == HAL_LCD_MODE_SPI)
+    {
+        HAL_ASSERT(!(halCfg->goudaCfg.cs0Used || halCfg->goudaCfg.cs1Used),
+            "LCD CS 0/1 use SPI LCD pins");
+        HAL_ASSERT((halCfg->usedGpo_A & (HAL_GPO_BIT(3)|HAL_GPO_BIT(4))) == 0,
+            "GPO 3/4 use SPI LCD pins");
+        altMux |= CFG_REGS_SPI_LCD_SPI_LCD;
+        availableGpio_A |= HAL_GPIO_BIT(18)
+                         | HAL_GPIO_BIT(19)
+                         | HAL_GPIO_BIT(20)
+                         | HAL_GPIO_BIT(21);
+    }
+    else
+    {
+        HAL_ASSERT(FALSE, "Lcd mode not defined!");
+    }
+
+    if (lcdMode == HAL_LCD_MODE_DSI || lcdMode == HAL_LCD_MODE_SPI)
+    {
+        if (!nand8_15Lcd)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(24)
+                             | HAL_GPIO_BIT(25)
+                             | HAL_GPIO_BIT(26)
+                             | HAL_GPIO_BIT(27)
+                             | HAL_GPIO_BIT(28)
+                             | HAL_GPIO_BIT(29)
+                             | HAL_GPIO_BIT(30)
+                             | HAL_GPIO_BIT(31);
+        }
+    }
+
+    if (halCfg->goudaCfg.cs0Used)
+    {
+        altMux |= CFG_REGS_GPO_4_LCD_CS_0;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_4_GPO_4;
+        availableGpo_A |= HAL_GPO_BIT(4);
+    }
+
+    if (halCfg->goudaCfg.cs1Used)
+    {
+        altMux |= CFG_REGS_GPO_3_LCD_CS_1;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_3_GPO_3;
+        availableGpo_A |= HAL_GPO_BIT(3);
+    }
+
+    // I2C
+    if (!halCfg->i2cCfg.i2cUsed)
+    {
+        availableGpio_B |= HAL_GPIO_BIT(30)
+                         | HAL_GPIO_BIT(31);
+    }
+
+    if (halCfg->i2cCfg.i2c2Used)
+    {
+        if (halCfg->i2cCfg.i2c2PinsCam)
+        {
+            if (camCfg->camUsed)
+            {
+                HAL_ASSERT(camCfg->camPdnRemap == GPIO_NONE &&
+                    camCfg->camRstRemap == GPIO_NONE,
+                    "Cam uses PDN/RST pins");
+            }
+            if (camCfg->cam1Used)
+            {
+                HAL_ASSERT(camCfg->cam1PdnRemap == GPIO_NONE &&
+                    camCfg->cam1RstRemap == GPIO_NONE,
+                    "Cam1 uses PDN/RST pins");
+            }
+            HAL_ASSERT(!nand8_15Cam, "NAND uses cam PDN/RST pins");
+            availableGpio_A |= HAL_GPIO_BIT(0)
+                             | HAL_GPIO_BIT(1);
+            altMux |= CFG_REGS_CAM_I2C2_I2C2;
+        }
+        else
+        {
+            // I2C2 does not use cam pins
+            altMux |= CFG_REGS_CAM_I2C2_CAM;
+        }
+    }
+    else
+    {
+        // I2C2 does not use cam pins
+        altMux |= CFG_REGS_CAM_I2C2_CAM;
+        availableGpio_A |= HAL_GPIO_BIT(0)
+                         | HAL_GPIO_BIT(1);
+    }
+
+    if (halCfg->i2cCfg.i2c3Used)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x18) == 0, "Keyout 3/4 use I2C3 pins");
+        altMux |= CFG_REGS_KEYOUT_3_4_I2C3;
+    }
+    else
+    {
+        altMux |= CFG_REGS_KEYOUT_3_4_KEYOUT_3_4;
+        if ((halCfg->keyOutMask & 0x8) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(6);
+        }
+        if ((halCfg->keyOutMask & 0x10) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(7);
+        }
+    }
+
+    // Camera
+    if (camCfg->camUsed || camCfg->cam1Used)
+    {
+        if(camCfg->camMode == HAL_CAM_MODE_PARALLEL)
+        {
+            HAL_ASSERT(!spiFlashCam, "SPI flash uses cam pins");
+            HAL_ASSERT(!nand8_15Cam, "NAND 8-15 bits use cam pins");
+            altMux |= CFG_REGS_CSI2_PARALLEL_CAM;
+            availableGpio_B |= HAL_GPIO_BIT(24);
+        }
+        else if (camCfg->camMode == HAL_CAM_MODE_SPI)
+        {
+            altMux |= CFG_REGS_CSI2_SPI_CAM;
+            availableGpio_B |= HAL_GPIO_BIT(14);
+            if (!(spiFlashCam || nand8_15Cam ||
+                  (lcdMode == HAL_LCD_MODE_RGB_24BIT &&
+                   halCfg->goudaCfg.lcd16_23Cam)
+                 )
+               )
+            {
+                availableGpio_B |= HAL_GPIO_BIT(13)
+                                 | HAL_GPIO_BIT(20)
+                                 | HAL_GPIO_BIT(21)
+                                 | HAL_GPIO_BIT(22)
+                                 | HAL_GPIO_BIT(23)
+                                 | HAL_GPIO_BIT(24);
+            }
+        }
+        else if (camCfg->camMode == HAL_CAM_MODE_CSI)
+        {
+            if ((camCfg->camUsed && camCfg->camCsiId == HAL_CAM_CSI_1) ||
+                (camCfg->cam1Used && camCfg->cam1CsiId == HAL_CAM_CSI_1))
+            {
+                HAL_ASSERT(!spiFlashCam, "SPI flash uses CSI1 pins");
+                HAL_ASSERT(!nand8_15Cam, "NAND 8-15 bits use CSI1 pins");
+            }
+            else
+            {
+                // CSI1 is unused
+                if (!(spiFlashCam || nand8_15Cam ||
+                      (lcdMode == HAL_LCD_MODE_RGB_24BIT &&
+                       halCfg->goudaCfg.lcd16_23Cam)
+                     )
+                   )
+                {
+                    availableGpio_B |= HAL_GPIO_BIT(13)
+                                     | HAL_GPIO_BIT(20)
+                                     | HAL_GPIO_BIT(21)
+                                     | HAL_GPIO_BIT(22)
+                                     | HAL_GPIO_BIT(23)
+                                     | HAL_GPIO_BIT(24);
+                }
+            }
+            altMux |= CFG_REGS_CSI2_CSI2;
+            // If CSI2 is unused
+            if (!((camCfg->camUsed && camCfg->camCsiId == HAL_CAM_CSI_2) ||
+                  (camCfg->cam1Used && camCfg->cam1CsiId == HAL_CAM_CSI_2)))
+            {
+                availableGpio_B |= HAL_GPIO_BIT(14)
+                                 | HAL_GPIO_BIT(15)
+                                 | HAL_GPIO_BIT(16)
+                                 | HAL_GPIO_BIT(17)
+                                 | HAL_GPIO_BIT(18)
+                                 | HAL_GPIO_BIT(19);
+            }
+        }
+        else
+        {
+            HAL_ASSERT(FALSE, "Invalid cam mode: %d", camCfg->camMode);
+        }
+
+        // Cam PDN/RST pins
+        if (!(nand8_15Cam ||
+              (lcdMode == HAL_LCD_MODE_RGB_24BIT && halCfg->goudaCfg.lcd16_23Cam) ||
+              (halCfg->i2cCfg.i2c2Used && halCfg->i2cCfg.i2c2PinsCam)
+             )
+           )
+        {
+            if (!((camCfg->camUsed && camCfg->camRstRemap == GPIO_NONE) ||
+                  (camCfg->cam1Used && camCfg->cam1RstRemap == GPIO_NONE)))
+            {
+                availableGpio_B |= HAL_GPIO_BIT(10);
+            }
+            if (!((camCfg->camUsed && camCfg->camPdnRemap == GPIO_NONE) ||
+                  (camCfg->cam1Used && camCfg->cam1PdnRemap == GPIO_NONE)))
+            {
+                availableGpio_B |= HAL_GPIO_BIT(11);
+            }
+        }
+    }
+    else // cam is unused
+    {
+        availableGpio_B |= HAL_GPIO_BIT(12)
+                         | HAL_GPIO_BIT(14)
+                         | HAL_GPIO_BIT(15)
+                         | HAL_GPIO_BIT(16)
+                         | HAL_GPIO_BIT(17)
+                         | HAL_GPIO_BIT(18)
+                         | HAL_GPIO_BIT(19);
+        if (!(nand8_15Cam ||
+              (lcdMode == HAL_LCD_MODE_RGB_24BIT && halCfg->goudaCfg.lcd16_23Cam) ||
+              (halCfg->i2cCfg.i2c2Used && halCfg->i2cCfg.i2c2PinsCam)
+             )
+           )
+        {
+            availableGpio_B |= HAL_GPIO_BIT(10)
+                             | HAL_GPIO_BIT(11);
+        }
+        if (!(spiFlashCam || nand8_15Cam ||
+              (lcdMode == HAL_LCD_MODE_RGB_24BIT && halCfg->goudaCfg.lcd16_23Cam)
+             )
+           )
+        {
+            availableGpio_B |= HAL_GPIO_BIT(13)
+                             | HAL_GPIO_BIT(20)
+                             | HAL_GPIO_BIT(21)
+                             | HAL_GPIO_BIT(22)
+                             | HAL_GPIO_BIT(23)
+                             | HAL_GPIO_BIT(24);
+        }
+    }
+
+    // UART 1 Pin configuration
+    switch (halCfg->uartCfg[0])
+    {
+        case HAL_UART_CONFIG_NONE:
+            altMux |= CFG_REGS_KEYOUT_7_KEYOUT_7;
+            availableGpio_C |= HAL_GPIO_BIT(6);
+            availableGpio_A |= HAL_GPIO_BIT(14);
+            if ((halCfg->keyInMask & 0x80) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(15);
+            }
+            if ((halCfg->keyInMask & 0x80) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(16);
+            }
+            break;
+        case HAL_UART_CONFIG_DATA:
+             // use UART1 TXD, RXD
+            altMux |= CFG_REGS_KEYOUT_7_KEYOUT_7;
+            if ((halCfg->keyInMask & 0x80) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(15);
+            }
+            if ((halCfg->keyInMask & 0x80) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(16);
+            }
+            break;
+        case HAL_UART_CONFIG_FLOWCONTROL:
+             // use UART1 TXD, RXD, CTS, RTS
+            HAL_ASSERT((halCfg->keyInMask & 0x80) == 0, "Keyin 7 uses UART1 CTS");
+            HAL_ASSERT((halCfg->keyOutMask & 0x80) == 0, "Keyout 7 uses UART1 RTS");
+            altMux |= CFG_REGS_KEYOUT_7_UART1_RTS;
+            break;
+        case HAL_UART_CONFIG_MODEM:
+            // use UART1 TXD, RXD, CTS, RTS, RI, DSR, DCD, DTR
+            HAL_ASSERT((halCfg->keyInMask & 0x80) == 0, "Keyin 7 uses UART1 CTS");
+            HAL_ASSERT((halCfg->keyOutMask & 0x80) == 0, "Keyout 7 uses UART1 RTS");
+            HAL_ASSERT(!halCfg->hostUartUsed, "Host UART uses UART1 DCD/DTR");
+            HAL_ASSERT(halCfg->uartCfg[1] == HAL_UART_CONFIG_NONE,
+                    "UART 2 must be unused to use UART1 Modem lines.");
+            HAL_ASSERT((halCfg->keyInMask & 0x40) == 0, "Keyin 6 uses UART1 DSR");
+            HAL_ASSERT((halCfg->keyOutMask & 0x40) == 0, "Keyout 6 uses UART1 RI");
+            altMux |= CFG_REGS_KEYOUT_7_UART1_RTS
+                    | CFG_REGS_UART1_8LINE_UART1_8_LINE;
+            break;
+        default:
+            HAL_ASSERT(FALSE,
+                    "Invalid Uart 1 Configuration (%d).",
+                    halCfg->uartCfg[0]);
+            break;
+    }
+
+    // Host UART
+    if (halCfg->hostUartUsed)
+    {
+        HAL_ASSERT(halCfg->uartCfg[1] == HAL_UART_CONFIG_NONE,
+                "UART2 uses host UART RXD/TXD.");
+    }
+
+    // UART 2 Pin configuration
+    switch (halCfg->uartCfg[1])
+    {
+        case HAL_UART_CONFIG_NONE:
+            altMux |= CFG_REGS_UART2_HOST_UART
+                    | CFG_REGS_KEYOUT_6_KEYOUT_6;
+            if (halCfg->uartCfg[0] != HAL_UART_CONFIG_MODEM)
+            {
+                availableGpio_C |= HAL_GPIO_BIT(7)
+                                 | HAL_GPIO_BIT(8);
+            }
+            if ((halCfg->keyInMask & 0x40) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(8);
+            }
+            if ((halCfg->keyOutMask & 0x40) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(9);
+            }
+            break;
+        case HAL_UART_CONFIG_DATA:
+            // use UART2 TXD, RXD
+            altMux |= CFG_REGS_UART2_UART2
+                    | CFG_REGS_KEYOUT_6_KEYOUT_6;
+            if ((halCfg->keyInMask & 0x40) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(8);
+            }
+            if ((halCfg->keyOutMask & 0x40) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(9);
+            }
+            break;
+        case HAL_UART_CONFIG_FLOWCONTROL:
+             // use UART2 TXD, RXD, CTS, RTS
+            HAL_ASSERT((halCfg->keyInMask & 0x40) == 0, "Keyin 6 uses UART2 CTS");
+            HAL_ASSERT((halCfg->keyOutMask & 0x40) == 0, "Keyout 6 uses UART2 RTS");
+            altMux |= CFG_REGS_UART2_UART2
+                    | CFG_REGS_KEYOUT_6_UART2_RTS;
+            break;
+        case HAL_UART_CONFIG_MODEM:
+        default:
+            HAL_ASSERT(FALSE,
+                    "Invalid Uart2 Configuration (%d).",
+                    halCfg->uartCfg[1]);
+            break;
+    }
+
+    // UART 3 Pin configuration
+    switch (halCfg->uartCfg[2])
+    {
+        case HAL_UART_CONFIG_NONE:
+            availableGpio_D |= HAL_GPIO_BIT(0)
+                             | HAL_GPIO_BIT(1)
+                             | HAL_GPIO_BIT(2)
+                             | HAL_GPIO_BIT(3);
+            break;
+        case HAL_UART_CONFIG_DATA:
+            // use UART3 TXD, RXD
+            availableGpio_D |= HAL_GPIO_BIT(2)
+                             | HAL_GPIO_BIT(3);
+            break;
+        case HAL_UART_CONFIG_FLOWCONTROL:
+             // use UART3 TXD, RXD, CTS, RTS
+            break;
+        case HAL_UART_CONFIG_MODEM:
+        default:
+            HAL_ASSERT(FALSE,
+                    "Invalid Uart3 Configuration (%d).",
+                    halCfg->uartCfg[2]);
+            break;
+    }
+
+    // I2S
+    altMux |= CFG_REGS_DAI_I2S;
+    if (halCfg->i2sCfg.di0Used || halCfg->i2sCfg.di1Used ||
+        halCfg->i2sCfg.di2Used || halCfg->i2sCfg.doUsed)
+    {
+        if (!halCfg->i2sCfg.di0Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(11);
+        }
+        if (!halCfg->i2sCfg.di1Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(12);
+        }
+        if (halCfg->i2sCfg.di2Used)
+        {
+            HAL_ASSERT((halCfg->keyInMask & 0x4) == 0, "Keyin 2 uses I2S DI2");
+            altMux |= CFG_REGS_I2S_DI_2_I2S_DI_2;
+        }
+        else
+        {
+            altMux |= CFG_REGS_I2S_DI_2_KEYIN_2;
+            if ((halCfg->keyInMask & 0x4) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(2);
+            }
+        }
+        if (!halCfg->i2sCfg.doUsed)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(13);
+        }
+    }
+    else
+    {
+        availableGpio_A |= HAL_GPIO_BIT(9)
+                         | HAL_GPIO_BIT(10)
+                         | HAL_GPIO_BIT(11)
+                         | HAL_GPIO_BIT(12)
+                         | HAL_GPIO_BIT(13);
+    }
+
+    // LPS CO1
+    if (halCfg->useLpsCo1)
+    {
+        HAL_ASSERT((halCfg->keyInMask & 0x10) == 0, "Keyin 4 uses LPS_CO1");
+        altMux |= CFG_REGS_LPSCO_1_LPSCO_1;
+    }
+    else
+    {
+        altMux |= CFG_REGS_LPSCO_1_KEYIN_4;
+        if ((halCfg->keyInMask & 0x10) == 0)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(7);
+        }
+    }
+
+    // TCO
+    if (halCfg->usedTco & 0x1)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x1) == 0, "Keyout 0 uses TCO0");
+        altMux |= CFG_REGS_TCO_0_TCO_0;
+    }
+    else
+    {
+        altMux |= CFG_REGS_TCO_0_KEYOUT_0;
+        if ((halCfg->keyOutMask & 0x1) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(3);
+        }
+    }
+
+    if (halCfg->usedTco & 0x2)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x2) == 0, "Keyout 1 uses TCO1");
+        altMux |= CFG_REGS_TCO_1_TCO_1;
+    }
+    else
+    {
+        altMux |= CFG_REGS_TCO_1_KEYOUT_1;
+        if ((halCfg->keyOutMask & 0x2) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(4);
+        }
+    }
+
+    if (halCfg->usedTco & 0x4)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x4) == 0, "Keyout 2 uses TCO2");
+        altMux |= CFG_REGS_TCO_2_TCO_2;
+    }
+    else
+    {
+        altMux |= CFG_REGS_TCO_2_KEYOUT_2;
+        if ((halCfg->keyOutMask & 0x4) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(5);
+        }
+    }
+
+    // PWM
+    if (halCfg->pwmCfg.pwtUsed)
+    {
+        HAL_ASSERT((halCfg->keyInMask & 0x20) == 0, "Keyin 5 uses PWT");
+        altMux |= CFG_REGS_GPO_0_PWT;
+    }
+    else if (halCfg->keyInMask & 0x20)
+    {
+        altMux |= CFG_REGS_GPO_0_KEYIN_5;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_0_GPO_0;
+        availableGpo_A |= HAL_GPO_BIT(0);
+    }
+
+    if (halCfg->pwmCfg.lpgUsed)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x20) == 0, "Keyout 5 uses LPG");
+        altMux |= CFG_REGS_GPO_1_LPG;
+    }
+    else if (halCfg->keyOutMask & 0x20)
+    {
+        altMux |= CFG_REGS_GPO_1_KEYOUT_5;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_1_GPO_1;
+        availableGpo_A |= HAL_GPO_BIT(1);
+    }
+
+    if (halCfg->pwmCfg.pwl1Used)
+    {
+        HAL_ASSERT(!halCfg->useClk32k, "Clk 32k uses PWL1");
+        altMux |= CFG_REGS_GPO_2_PWL_1;
+    }
+    else if (halCfg->useClk32k)
+    {
+        // Default to GPO low output
+        // 32K clock will be enabled per request
+        //altMux |= CFG_REGS_GPO_2_CLK_32K;
+        altMux |= CFG_REGS_GPO_2_GPO_2;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_2_GPO_2;
+        availableGpo_A |= HAL_GPO_BIT(2);
+    }
+
+    // Clock out and host clock
+    if (halCfg->clkOutUsed)
+    {
+        HAL_ASSERT(!halCfg->hostClkUsed, "HST_CLK uses CLK_OUT pin");
+        altMux |= CFG_REGS_CLK_OUT_CLK_OUT;
+    }
+    else if (halCfg->hostClkUsed)
+    {
+        altMux |= CFG_REGS_CLK_OUT_HST_CLK;
+    }
+    else
+    {
+        altMux |= CFG_REGS_CLK_OUT_HST_CLK;
+        availableGpo_A |= HAL_GPO_BIT(8);
+    }
+
+    // SPI
+    if (halCfg->spiCfg[0].cs0Used || halCfg->spiCfg[0].cs1Used ||
+        halCfg->spiCfg[0].cs2Used)
+    {
+        HAL_ASSERT(!(halCfg->modemSpiCfg[0].cs0Used ||
+                     halCfg->modemSpiCfg[0].cs1Used ||
+                     halCfg->modemSpiCfg[0].cs2Used), "Modem SPI1 is in use");
+        altMux |= CFG_REGS_AP_SPI1_AP_SPI1;
+        if (!halCfg->spiCfg[0].cs0Used)
+        {
+            availableGpio_C |= HAL_GPIO_BIT(22);
+        }
+        if (!halCfg->spiCfg[0].cs1Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(17);
+        }
+        if (halCfg->spiCfg[0].cs2Used)
+        {
+            HAL_ASSERT((halCfg->keyInMask & 0x2) == 0, "Keyin 1 uses SPI1 CS2");
+            altMux |= CFG_REGS_SPI1_CS_2_SPI1_CS_2;
+        }
+        else
+        {
+            altMux |= CFG_REGS_SPI1_CS_2_KEYIN_1;
+            if ((halCfg->keyInMask & 0x2) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(1);
+            }
+        }
+        if (!halCfg->spiCfg[0].di0Used)
+        {
+            availableGpio_C |= HAL_GPIO_BIT(23);
+        }
+        if (!halCfg->spiCfg[0].di1Used)
+        {
+            availableGpio_C |= HAL_GPIO_BIT(24);
+        }
+    }
+    else // AP SPI1 unused
+    {
+        altMux |= CFG_REGS_AP_SPI1_BB_SPI1;
+        if (halCfg->modemSpiCfg[0].cs0Used || halCfg->modemSpiCfg[0].cs1Used ||
+            halCfg->modemSpiCfg[0].cs2Used)
+        {
+            if (!halCfg->modemSpiCfg[0].cs0Used)
+            {
+                availableGpio_C |= HAL_GPIO_BIT(22);
+            }
+            if (!halCfg->modemSpiCfg[0].cs1Used)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(17);
+            }
+            if (!halCfg->modemSpiCfg[0].di0Used)
+            {
+                availableGpio_C |= HAL_GPIO_BIT(23);
+            }
+            if (!halCfg->modemSpiCfg[0].di1Used)
+            {
+                availableGpio_C |= HAL_GPIO_BIT(24);
+            }
+        }
+        else
+        {
+            availableGpio_A |= HAL_GPIO_BIT(17);
+            availableGpio_C |= HAL_GPIO_BIT(21)
+                             | HAL_GPIO_BIT(22)
+                             | HAL_GPIO_BIT(23)
+                             | HAL_GPIO_BIT(24);
+            if ((halCfg->keyInMask & 0x2) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(1);
+            }
+        }
+    }
+    if (halCfg->spiCfg[1].cs0Used || halCfg->spiCfg[1].cs1Used)
+    {
+        if (!halCfg->spiCfg[1].cs0Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(5);
+        }
+        if (halCfg->spiCfg[1].cs1Used)
+        {
+            HAL_ASSERT((halCfg->keyInMask & 0x8) == 0, "Keyin 3 uses SPI2 CS1");
+            altMux |= CFG_REGS_KEYIN_3_SPI2_CS_1;
+        }
+        else
+        {
+            altMux |= CFG_REGS_KEYIN_3_KEYIN_3;
+            if ((halCfg->keyInMask & 0x8) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(6);
+            }
+        }
+        if (!halCfg->spiCfg[1].di0Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(3);
+        }
+        if (!halCfg->spiCfg[1].di1Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(4);
+        }
+    }
+    else // AP SPI2 unused
+    {
+        availableGpio_A |= HAL_GPIO_BIT(2)
+                         | HAL_GPIO_BIT(3)
+                         | HAL_GPIO_BIT(4)
+                         | HAL_GPIO_BIT(5);
+        if ((halCfg->keyInMask & 0x8) == 0)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(6);
+        }
+    }
+
+    // Standalone keyin/out
+    if ((halCfg->keyInMask & 0x1) == 0)
+    {
+        availableGpio_B |= HAL_GPIO_BIT(0);
+    }
+
+    // SDMMC
+    if (!halCfg->sdmmcCfg.sdmmcUsed)
+    {
+        availableGpio_C |= HAL_GPIO_BIT(9)
+                         | HAL_GPIO_BIT(10)
+                         | HAL_GPIO_BIT(11)
+                         | HAL_GPIO_BIT(12)
+                         | HAL_GPIO_BIT(13)
+                         | HAL_GPIO_BIT(14);
+    }
+    if (!halCfg->sdmmcCfg.sdmmc2Used)
+    {
+        availableGpio_C |= HAL_GPIO_BIT(15)
+                         | HAL_GPIO_BIT(16)
+                         | HAL_GPIO_BIT(17)
+                         | HAL_GPIO_BIT(18)
+                         | HAL_GPIO_BIT(19)
+                         | HAL_GPIO_BIT(20);
+    }
+    HAL_ASSERT(!(parallelNandUsed && halCfg->sdmmcCfg.sdmmc3Used),
+        "Parallel NAND uses SDMMC3 pins");
+
+    // SIM
+    if (1)
+    {
+        availableGpio_C |= HAL_GPIO_BIT(25)
+                         | HAL_GPIO_BIT(26)
+                         | HAL_GPIO_BIT(27);
+    }
+
+    if (!hal_BoardSimUsed(3))
+    {
+        availableGpio_C |= HAL_GPIO_BIT(28)
+                         | HAL_GPIO_BIT(29)
+                         | HAL_GPIO_BIT(30);
+    }
+
+    UINT32 gpioMask;
+    // GPIO_C mask check
+    gpioMask = ~availableGpio_C & halCfg->usedGpio_C;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO C are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_C & halCfg->noConnectGpio_C;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO C declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_C & halCfg->noConnectGpio_C;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO C declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_C &
+               (~halCfg->usedGpio_C & ~halCfg->noConnectGpio_C);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO C declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPIO_A mask check
+    gpioMask = ~availableGpio_A & halCfg->usedGpio_A;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO A are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_A & halCfg->noConnectGpio_A;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO A declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_A & halCfg->noConnectGpio_A;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO A declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_A &
+               (~halCfg->usedGpio_A & ~halCfg->noConnectGpio_A);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO A declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPIO_B mask check
+    gpioMask = ~availableGpio_B & halCfg->usedGpio_B;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO B are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_B & halCfg->noConnectGpio_B;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO B declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_B & halCfg->noConnectGpio_B;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO B declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_B &
+               (~halCfg->usedGpio_B & ~halCfg->noConnectGpio_B);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO B declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPIO_D mask check
+    gpioMask = ~availableGpio_D & halCfg->usedGpio_D;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO D are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_D & halCfg->noConnectGpio_D;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO D declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_D & halCfg->noConnectGpio_D;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO D declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_D &
+               (~halCfg->usedGpio_D & ~halCfg->noConnectGpio_D);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO D declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPO_A mask check
+    gpioMask = ~availableGpo_A & halCfg->usedGpo_A;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPO A are not available (0x%x)",
+               gpioMask);
+
+#endif // !FPGA
+
+    // Set IO drive
+    hwp_configRegs->IO_Drive1_Select = halCfg->ioDrive.select1;
+    hwp_configRegs->IO_Drive2_Select = halCfg->ioDrive.select2;
+
+    // Set the not connected ones as output and drive 0
+    // But keep boot mode GPIOs as input to avoid current leakage
+    noConnectMask_C = halCfg->noConnectGpio_C & ~bootModeGpio_C;
+    noConnectMask_A = halCfg->noConnectGpio_A & ~bootModeGpio_A;
+    noConnectMask_B = halCfg->noConnectGpio_B & ~bootModeGpio_B;
+    noConnectMask_D = halCfg->noConnectGpio_D & ~bootModeGpio_D;
+
+    hwp_gpio->gpio_clr = noConnectMask_C;
+    hwp_gpio->gpio_oen_set_out = noConnectMask_C;
+
+    hwp_apGpioA->gpio_clr = noConnectMask_A;
+    hwp_apGpioA->gpio_oen_set_out = noConnectMask_A;
+
+    hwp_apGpioB->gpio_clr = noConnectMask_B;
+    hwp_apGpioB->gpio_oen_set_out = noConnectMask_B;
+
+    hwp_apGpioD->gpio_clr = noConnectMask_D;
+    hwp_apGpioD->gpio_oen_set_out = noConnectMask_D;
+
+    // Init GPO_A values
+    gpoClr_A = availableGpo_A;
+    if (halCfg->useClk32k)
+    {
+        // Init 32K clock pin to low (by setting up GPO)
+        gpoClr_A |= HAL_GPO_BIT(2);
+    }
+#ifdef _TGT_AP_GPIO_USBID_CTRL
+    // if GPO_1 used for usb id, it should be high
+    gpoClr_A &= ~(HAL_GPO_BIT(1));
+#endif
+    hwp_apGpioA->gpo_clr = gpoClr_A;
+
+    // Configure MUX after initializing all the GPO pins
+    // (GPIO pins are in input mode by default)
+
+    // Set GPIO mode
+    hwp_configRegs->BB_GPIO_Mode = availableGpio_C;
+    hwp_configRegs->AP_GPIO_A_Mode = availableGpio_A;
+    hwp_configRegs->AP_GPIO_B_Mode = availableGpio_B;
+    hwp_configRegs->AP_GPIO_D_Mode = availableGpio_D;
+    // Set Alt Mux configuration
+    hwp_configRegs->Alt_mux_select = altMux;
+
+    // --------------------------------------------------
+    // As of now, all connected GPIOs, which are as GPIO
+    // or not used at all but connected are configured as
+    // GPIOs in input mode, except for Gouda reset pins
+    // --------------------------------------------------
+
+}
+
+
+// =============================================================================
+// hal_BoardSetup
+// -----------------------------------------------------------------------------
+/// Apply board dependent configuration to HAL
+/// @param halCfg Pointer to HAL configuration structure (from the target
+/// module).
+// ============================================================================
+//PROTECTED VOID hal_BoardSetup(CONST HAL_CFG_CONFIG_T* halCfg)
+PUBLIC INT32 hal_BoardSetup(INT8 run_mode)
+{
+	g_bootBootMode = rda_hwcfg_get();
+	hal_BoardSetupGeneral(&hal_cfg);
+
+	if(g_halConfigError)
+		return CMD_RET_FAILURE;
+	else
+		return CMD_RET_SUCCESS;
+}
diff --git a/board/rda/rda8810/u-boot-spl.lds b/board/rda/rda8810/u-boot-spl.lds
new file mode 100644
index 0000000000..2528012e2a
--- /dev/null
+++ b/board/rda/rda8810/u-boot-spl.lds
@@ -0,0 +1,44 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00100100;
+	. = ALIGN(4);
+	.text :
+	{
+		__start = .;
+		arch/arm/cpu/armv7/start.o (.text)
+			*(.text)
+	}
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+	. = ALIGN(4);
+	.data : {
+		*(.data)
+	}
+	. = ALIGN(4);
+	. = .;
+	. = ALIGN(4);
+	__image_copy_end = .;
+	_end = .;
+	. = __start + CONFIG_DDR_CAL_SEC_OFFS;
+	. = ALIGN(4);
+	.ddrcal : {
+		__ddrcal_start = .;
+		. = __ddrcal_start + CONFIG_DDR_CAL_VAL_SIZE;
+		__ddrcal_end = .;
+	}
+	. = .;
+	. = ALIGN(4);
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+		ASSERT((ABSOLUTE(__bss_end__) < 0x00110000 - CONFIG_SPL_BOARD_INFO_SIZE), \
+			"too big data in spl, don't exceed intrenal ram");
+	}
+}
diff --git a/board/rda/rda8810e/Makefile b/board/rda/rda8810e/Makefile
new file mode 100644
index 0000000000..073f60c53f
--- /dev/null
+++ b/board/rda/rda8810e/Makefile
@@ -0,0 +1,82 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS-y	+= clock_config.o clock.o ddr3.o
+else
+COBJS-$(CONFIG_MACH_RDA8810E) += hal_config.o
+endif
+
+RDA_TARGET_DEF_FILE := $(ANDROID_BUILD_TOP)/$(RDA_TARGET_DEVICE_DIR)/target.def
+RDA_GET_MAKEFILE_VAR_FUNC = $(strip $(shell sed -n 's/^[ 	]*$(1)[ 	]*[?:]\?=\([^\#]\+\)\#*.*$$/\1/p' $(2)))
+
+NUMBER_OF_SIM := $(call RDA_GET_MAKEFILE_VAR_FUNC,NUMBER_OF_SIM,$(RDA_TARGET_DEF_FILE))
+ifeq ($(NUMBER_OF_SIM),)
+$(error Failed to get NUMBER_OF_SIM in $(RDA_TARGET_DEF_FILE))
+endif
+
+USER_SIM_ORDER := $(call RDA_GET_MAKEFILE_VAR_FUNC,USER_SIM_ORDER,$(RDA_TARGET_DEF_FILE))
+ifeq ($(USER_SIM_ORDER),)
+$(error Failed to get USER_SIM_ORDER in $(RDA_TARGET_DEF_FILE))
+endif
+
+NULL_STRING :=
+SPACE := ${NULL_STRING} # end of the line
+COMMA := ,
+TGT_SIM_ORDER := $(foreach SIM,$(USER_SIM_ORDER),$(SIM)$(COMMA))
+TGT_SIM_ORDER := $(subst ${SPACE},,${TGT_SIM_ORDER})
+
+CPPFLAGS_board/$(BOARDDIR)/hal_config.o += -I$(TOPDIR)/board/$(VENDOR)/common/include -DTGT_SIM_ORDER=$(TGT_SIM_ORDER) -DNUMBER_OF_SIM=$(NUMBER_OF_SIM)
+
+ifeq ($(strip $(TARGET_TABLET_MODE)),true)
+CPPFLAGS_board/$(BOARDDIR)/clock.o += -DTARGET_TABLET_MODE
+endif
+
+COBJS   := $(COBJS-y)
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak *~ .depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/rda/rda8810e/clock.c b/board/rda/rda8810e/clock.c
new file mode 100644
index 0000000000..30a063b3b5
--- /dev/null
+++ b/board/rda/rda8810e/clock.c
@@ -0,0 +1,1338 @@
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/rda_iomap.h>
+#include <asm/io.h>
+#include <asm/arch/reg_sysctrl.h>
+#include <asm/arch/hwcfg.h>
+#include <asm/arch/ispi.h>
+#include <asm/arch/rda_sys.h>
+#include "clock_config.h"
+#include "debug.h"
+#include "ddr3.h"
+#include "tgt_ap_clock_config.h"
+
+#if (PMU_VBUCK1_VAL < 0 || PMU_VBUCK1_VAL > 15)
+#error "Invalid PMU_VBUCK1_VAL"
+#endif
+#if (PMU_VBUCK3_VAL < 0 || PMU_VBUCK3_VAL > 15)
+#error "Invalid PMU_VBUCK3_VAL"
+#endif
+#ifdef PMU_VBUCK4_VAL
+#if (PMU_VBUCK4_VAL < 0 || PMU_VBUCK4_VAL > 15)
+#error "Invalid PMU_VBUCK4_VAL"
+#endif
+#endif
+
+//#define DO_SIMPLE_DDR_TEST
+//#define DO_DDR_PLL_DEBUG
+
+enum {
+	AP_CPU_CLK_IDX = 0,
+	AP_BUS_CLK_IDX,
+	AP_MEM_CLK_IDX,
+	AP_USB_CLK_IDX,
+};
+
+static int pll_enabled(int idx)
+{
+	if ((hwp_sysCtrlAp->Cfg_Pll_Ctrl[idx] &
+			(SYS_CTRL_AP_AP_PLL_ENABLE_MASK |
+			 SYS_CTRL_AP_AP_PLL_LOCK_RESET_MASK)) ==
+			(SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE |
+			 SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET))
+		return 1;
+	else
+		return 0;
+}
+
+static int usb_in_use = 0;
+
+static void check_usb_usage(void)
+{
+	unsigned int mask = SYS_CTRL_AP_BUS_SEL_FAST_SLOW |
+		SYS_CTRL_AP_PLL_LOCKED_BUS_MASK |
+		SYS_CTRL_AP_PLL_LOCKED_USB_MASK;
+	unsigned int reg = SYS_CTRL_AP_BUS_SEL_FAST_FAST |
+		SYS_CTRL_AP_PLL_LOCKED_BUS_LOCKED |
+		SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED;
+
+	if ((hwp_sysCtrlAp->Sel_Clock & mask) == reg &&
+			pll_enabled(AP_BUS_CLK_IDX) &&
+			pll_enabled(AP_USB_CLK_IDX))
+		usb_in_use = 1;
+	else
+		usb_in_use = 0;
+}
+
+#ifdef DO_SIMPLE_DDR_TEST
+
+void mem_test_write(void)
+{
+	volatile unsigned int *addr;
+
+	printf("write ddr test!!!!!!\n");
+
+ 	addr = (volatile unsigned int *)(0x80000000);
+	while((unsigned int)addr < 0x81000000)
+	{
+		*addr = (unsigned int )addr;
+		addr++;
+	}
+}
+
+void mem_test_read(void)
+{
+	volatile unsigned int *addr;
+
+	printf("read ddr!!!!\n");
+
+	addr = (volatile unsigned int *)(0x80000000);
+
+	while((unsigned int)addr < 0x81000000)
+	{
+		if (*addr != (unsigned int)addr){
+			int i = 0;
+			
+			printf("test error!!!!!, addr = %x\n", (unsigned int)addr);
+			for (i = 0; i < 80;i++){
+				printf("%x ", *(addr + i));
+				if ((i % 4) == 0)
+					printf("\n");
+			}
+
+			return;
+		}
+
+		addr++;
+	}
+	printf("test complete!\n");
+}
+
+#endif /* DO_SIMPLE_DDR_TEST */
+
+#ifndef CONFIG_RDA_FPGA
+
+// PMU bit fields
+#define PMU_SET_BITFIELD(dword, bitfield, value) \
+	(((dword) & ~(bitfield ## _MASK)) | (bitfield(value)))
+
+#define RDA_PMU_VBUCK1_BIT_ACT(n)        (((n)&0xf)<<12)
+#define RDA_PMU_VBUCK1_BIT_ACT_MASK      (0xf<<12)
+#define RDA_PMU_VBUCK1_BIT_ACT_SHIFT     (12)
+
+#define RDA_PMU_VBUCK4_BIT_ACT_SHIFT     (4)
+#define RDA_PMU_VBUCK4_BIT_ACT_MASK      (0xf<<4)
+#define RDA_PMU_VBUCK4_BIT_ACT(n)        (((n)&0xf)<<4)
+
+#define RDA_PMU_VBUCK3_BIT_ACT_SHIFT     (12)
+#define RDA_PMU_VBUCK3_BIT_ACT_MASK      (0xf<<12)
+#define RDA_PMU_VBUCK3_BIT_ACT(n)        (((n)&0xf)<<12)
+
+struct pll_freq {
+	UINT32 freq_mhz;
+	UINT16 major;
+	UINT16 minor;
+	UINT16 with_div;
+	UINT16 div;
+};
+
+typedef enum {
+	PLL_REG_CPU_BASE = 0x00,
+	PLL_REG_BUS_BASE = 0x20,
+	PLL_REG_MEM_BASE = 0x60,
+	PLL_REG_USB_BASE = 0x80,
+} PLL_REG_BASE_INDEX_t;
+
+typedef enum {
+	PLL_REG_OFFSET_01H = 1,
+	PLL_REG_OFFSET_02H = 2,
+	PLL_REG_OFFSET_DIV = 3,
+	PLL_REG_OFFSET_04H = 4,
+	PLL_REG_OFFSET_MAJOR = 5,
+	PLL_REG_OFFSET_MINOR = 6,
+	PLL_REG_OFFSET_07H = 7,
+} PLL_REG_OFFSET_INDEX_t;
+
+#define PLL_FREQ_TABLE_COUNT        23
+
+static struct pll_freq pll_freq_table[PLL_FREQ_TABLE_COUNT] = {
+	/* MHz Major   Minor   div */
+	{1600, 0x7B13, 0xB138, 0, 0x0000},
+	{1200, 0x5C4E, 0xC4EC, 0, 0x0000},
+	{1000, 0x4BEC, 0x4EC4, 0, 0x0000},
+	{ 988, 0x4000, 0x0000, 0, 0x0000},
+	{ 800, 0x3C00, 0x0000, 0, 0x0000},
+	{ 600, 0x2E27, 0x6274, 0, 0x0000},
+	{ 533, 0x2900, 0x0000, 1, 0xc797},
+	{ 519, 0x27EC, 0x4EC4, 1, 0xc797},
+	{ 500, 0x2676, 0x2762, 1, 0xc797},
+	{ 480, 0x24EC, 0x4EC4, 0, 0x0000},
+	{ 455, 0x2300, 0x0000, 1, 0xC297},
+	{ 416, 0x1FD8, 0x0000, 1, 0xCB97},
+	/* 800M div 1, PLL:800M  DDR:400M for mem pll only */
+	{ 400, 0x1F00, 0x0000, 1, 0xCA97},
+	{ 355, 0x369D, 0x89D8, 1, 0xD597},
+	/* 702M div 1, PLL:702M  DDR:351M for mem pll only */
+	{ 351, 0x3600, 0x0000, 1, 0xD297},
+	{ 333, 0x333B, 0x13B1, 1, 0xD097},
+	/* 624M div 1, PLL:624M  DDR:312M for mem pll only */
+	{ 312, 0x3000, 0x0000, 1, 0xD897},
+	{ 290, 0x2C9D, 0x89D8, 1, 0xE097},
+	/* 520M div 1, PLL:520M  DDR:260M for mem pll only */
+	{ 260, 0x2800, 0x0000, 1, 0xE897},
+	/* 800M div 2, PLL:400M  DDR:200M for mem pll only */
+	{ 200, 0x3D89, 0xD89C, 1, 0x0006},
+	/* DDR:156M for mem pll only */
+	{ 156, 0x3000, 0x0000, 1, 0x0006},
+	/* 800M div 4, PLL:200M  DDR:100M for mem pll only */
+	{ 100, 0x3D89, 0xD89C, 1, 0x0005},
+	/* 800M div 8, PLL:100M  DDR:50M for mem pll only */
+	{  50, 0x3D89, 0xD89C, 1, 0x0004},
+};
+
+static const struct clock_config *g_clock_config;
+
+#ifdef DO_DDR_PLL_DEBUG
+static struct clock_config clock_debug_config;
+static UINT32 ddrfreq = 400, ddr32bit = 0;
+#endif
+
+static void sys_shutdown_pll(void)
+{
+	int i;
+
+	hwp_sysCtrlAp->REG_DBG = AP_CTRL_PROTECT_UNLOCK;
+
+	if (usb_in_use) {
+		hwp_sysCtrlAp->Sel_Clock = SYS_CTRL_AP_SLOW_SEL_RF_RF
+			| SYS_CTRL_AP_CPU_SEL_FAST_SLOW
+			| SYS_CTRL_AP_BUS_SEL_FAST_FAST
+			| SYS_CTRL_AP_TIMER_SEL_FAST_FAST;
+	} else {
+		hwp_sysCtrlAp->Sel_Clock = SYS_CTRL_AP_SLOW_SEL_RF_RF
+			| SYS_CTRL_AP_CPU_SEL_FAST_SLOW
+			| SYS_CTRL_AP_BUS_SEL_FAST_SLOW
+			| SYS_CTRL_AP_TIMER_SEL_FAST_FAST;
+	}
+
+	for (i = 0; i < 3; i++) {
+		/* In download mode, rom code has been set ap bus*/
+		if (usb_in_use) {
+			if (i == AP_BUS_CLK_IDX) // ap bus
+				continue;
+		}
+		hwp_sysCtrlAp->Cfg_Pll_Ctrl[i] =
+			SYS_CTRL_AP_AP_PLL_ENABLE_POWER_DOWN |
+			SYS_CTRL_AP_AP_PLL_LOCK_RESET_RESET;
+	}
+}
+
+static void sys_setup_pll(void)
+{
+	int i;
+	UINT32 mask;
+	UINT32 locked;
+	int cnt = 10; //10us, according to IC, the pll must be locked
+
+	hwp_sysCtrlAp->REG_DBG = AP_CTRL_PROTECT_UNLOCK;
+
+	for (i = 0; i < 3; i++) {
+		/* In download mode, rom code has been set ap bus*/
+		if (usb_in_use) {
+			if (i == AP_BUS_CLK_IDX) // ap bus
+				continue;
+		}
+
+		if (AP_MEM_CLK_IDX == i)
+			hwp_sysCtrlAp->Cfg_Pll_Ctrl[i] =
+				SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE |
+				SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET |
+				SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(1)|
+				SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(30);
+		else
+			hwp_sysCtrlAp->Cfg_Pll_Ctrl[i] =
+				SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE |
+				SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET |
+				SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(6)|
+				SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(30);
+	}
+
+	mask = SYS_CTRL_AP_PLL_LOCKED_CPU_MASK
+	    | SYS_CTRL_AP_PLL_LOCKED_BUS_MASK
+	    | SYS_CTRL_AP_PLL_LOCKED_MEM_MASK
+	    //| SYS_CTRL_AP_PLL_LOCKED_USB_MASK
+	    ;
+	locked = SYS_CTRL_AP_PLL_LOCKED_CPU_LOCKED
+	    | SYS_CTRL_AP_PLL_LOCKED_BUS_LOCKED
+	    | SYS_CTRL_AP_PLL_LOCKED_MEM_LOCKED
+	    //| SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED
+	    ;
+
+	while (((hwp_sysCtrlAp->Sel_Clock & mask) != locked) && cnt) {
+		udelay(1);
+		cnt--;
+	}
+	if (cnt == 0) {
+		printf("WARNING, cannot lock cpu/bus/mem pll 0x%08x ",
+			hwp_sysCtrlAp->Sel_Clock);
+		printf("but we run anyway ...\n");
+	}
+
+	for (i = 0; i < 3; i++) {
+		hwp_sysCtrlAp->Cfg_Pll_Ctrl[i] |=
+		    SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_ENABLE;
+	}
+
+	hwp_sysCtrlAp->Sel_Clock = SYS_CTRL_AP_SLOW_SEL_RF_RF
+	    | SYS_CTRL_AP_CPU_SEL_FAST_FAST
+	    | SYS_CTRL_AP_BUS_SEL_FAST_FAST
+	    | SYS_CTRL_AP_TIMER_SEL_FAST_FAST;
+}
+
+static void sys_setup_clk(void)
+{
+	// Disable some power-consuming clocks
+#ifdef CONFIG_VPU_TEST
+	hwp_sysCtrlAp->Clk_APO_Enable = SYS_CTRL_AP_ENABLE_APOC_VPU;
+	//hwp_sysCtrlAp->Clk_MEM_Enable = SYS_CTRL_AP_ENABLE_MEM_VPU;
+#else
+	hwp_sysCtrlAp->Clk_APO_Disable = SYS_CTRL_AP_DISABLE_APOC_VPU;
+	//hwp_sysCtrlAp->Clk_MEM_Disable = SYS_CTRL_AP_DISABLE_MEM_VPU;
+#endif
+
+	// Init clock gating mode
+	hwp_sysCtrlAp->Clk_CPU_Mode = 0;
+#ifdef CONFIG_VPU_TEST
+	hwp_sysCtrlAp->Clk_AXI_Mode = SYS_CTRL_AP_MODE_AXI_DMA_MANUAL | SYS_CTRL_AP_MODE_APB0_CONF_MANUAL;
+#else
+	hwp_sysCtrlAp->Clk_AXI_Mode = SYS_CTRL_AP_MODE_AXI_DMA_MANUAL;
+#endif
+	hwp_sysCtrlAp->Clk_AXIDIV2_Mode = 0;
+	hwp_sysCtrlAp->Clk_GCG_Mode = SYS_CTRL_AP_MODE_GCG_GOUDA_MANUAL
+				| SYS_CTRL_AP_MODE_GCG_CAMERA_MANUAL;
+	hwp_sysCtrlAp->Clk_AHB1_Mode = 0;
+	hwp_sysCtrlAp->Clk_APB1_Mode = 0;
+	hwp_sysCtrlAp->Clk_APB2_Mode = 0;
+#ifdef CONFIG_VPU_TEST
+	hwp_sysCtrlAp->Clk_MEM_Mode = SYS_CTRL_AP_MODE_CLK_MEM_MANUAL;
+#else
+	hwp_sysCtrlAp->Clk_MEM_Mode = 0;
+#endif
+	//hwp_sysCtrlAp->Clk_APO_Mode = SYS_CTRL_AP_MODE_APOC_VPU_MANUAL;
+
+	// Init module frequency
+	hwp_sysCtrlAp->Cfg_Clk_AP_CPU = g_clock_config->CLK_CPU;
+	hwp_sysCtrlAp->Cfg_Clk_AP_AXI = g_clock_config->CLK_AXI;
+	hwp_sysCtrlAp->Cfg_Clk_AP_GCG = g_clock_config->CLK_GCG;
+
+	if (!usb_in_use) {
+		hwp_sysCtrlAp->Cfg_Clk_AP_AHB1 = g_clock_config->CLK_AHB1;
+	}
+
+	hwp_sysCtrlAp->Cfg_Clk_AP_APB1 = g_clock_config->CLK_APB1;
+	hwp_sysCtrlAp->Cfg_Clk_AP_APB2 = g_clock_config->CLK_APB2;
+	hwp_sysCtrlAp->Cfg_Clk_AP_MEM = g_clock_config->CLK_MEM;
+	hwp_sysCtrlAp->Cfg_Clk_AP_GPU = g_clock_config->CLK_GPU;
+	hwp_sysCtrlAp->Cfg_Clk_AP_VPU = g_clock_config->CLK_VPU;
+	hwp_sysCtrlAp->Cfg_Clk_AP_VOC = g_clock_config->CLK_VOC;
+	hwp_sysCtrlAp->Cfg_Clk_AP_SFLSH = g_clock_config->CLK_SFLSH;
+}
+
+static void print_sys_reg(char *name, UINT32 value)
+{
+	printf("clk %s = %lx\n", name, value);
+}
+
+static void sys_dump_clk(void)
+{
+	print_sys_reg("CPU", hwp_sysCtrlAp->Cfg_Clk_AP_CPU);
+	print_sys_reg("AXI", hwp_sysCtrlAp->Cfg_Clk_AP_AXI);
+	print_sys_reg("GCG", hwp_sysCtrlAp->Cfg_Clk_AP_GCG);
+	print_sys_reg("AHB1", hwp_sysCtrlAp->Cfg_Clk_AP_AHB1);
+	print_sys_reg("APB1", hwp_sysCtrlAp->Cfg_Clk_AP_APB1);
+	print_sys_reg("APB2", hwp_sysCtrlAp->Cfg_Clk_AP_APB2);
+	print_sys_reg("MEM", hwp_sysCtrlAp->Cfg_Clk_AP_MEM);
+	print_sys_reg("GPU", hwp_sysCtrlAp->Cfg_Clk_AP_GPU);
+	print_sys_reg("VPU", hwp_sysCtrlAp->Cfg_Clk_AP_VPU);
+	print_sys_reg("VOC", hwp_sysCtrlAp->Cfg_Clk_AP_VOC);
+	print_sys_reg("SFLSH", hwp_sysCtrlAp->Cfg_Clk_AP_SFLSH);
+}
+
+static int pll_freq_set(UINT32 reg_base, UINT32 freq_mhz)
+{
+	int i;
+	struct pll_freq *freq;
+	unsigned int major, minor;
+	unsigned short value_02h;
+
+	/* find pll_freq */
+	for (i = 0; i < PLL_FREQ_TABLE_COUNT; i++) {
+		if (pll_freq_table[i].freq_mhz == freq_mhz)
+			break;
+	}
+	if (i >= PLL_FREQ_TABLE_COUNT) {
+		printf("pll_freq_set, fail to find freq\n");
+		return -1;
+	}
+
+	freq = &pll_freq_table[i];
+
+	if (freq_mhz >= 800 || reg_base == PLL_REG_USB_BASE) {
+		value_02h = 0x0309;
+		// Div PLL freq by 2
+		minor = ((freq->major & 0xFFFF) << 14) |
+			((freq->minor >> 2) & 0x3FFF);
+		minor >>= 1;
+		// Recalculate the divider
+		major = (minor >> 14) & 0xFFFF;
+		minor = (minor << 2) & 0xFFFF;
+	} else {
+		value_02h = 0x0209;
+		major = freq->major;
+		minor = freq->minor;
+	}
+	if (reg_base == PLL_REG_USB_BASE)
+		value_02h ^= (1 << 8);
+
+	if ((freq_mhz >= 400) && (PLL_REG_MEM_BASE == reg_base)){
+		value_02h = 0x308;
+	}
+
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_02H, value_02h);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_MAJOR, major);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_MINOR, minor);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_07H, 0x0010);
+
+	if (reg_base == PLL_REG_MEM_BASE) {
+		ispi_reg_write(0x63, freq->div&0x7FFF);
+		udelay(10000);
+		ispi_reg_write(0x63, freq->div);
+	}
+
+	udelay(10000);
+	return 0;
+}
+
+static void pll_setup_freq(void)
+{
+	pll_freq_set(PLL_REG_CPU_BASE, g_clock_config->PLL_FREQ_CPU);
+	// Always configure BUS PLL, even when it is being used
+	pll_freq_set(PLL_REG_BUS_BASE, g_clock_config->PLL_FREQ_BUS);
+	pll_freq_set(PLL_REG_MEM_BASE, g_clock_config->PLL_FREQ_MEM);
+	//pll_freq_set(PLL_REG_USB_BASE, g_clock_config->PLL_FREQ_USB);
+}
+
+static void print_pll_freq(char *name, UINT32 value)
+{
+	printf("pll freq %s = %d\n", name, (int)value);
+}
+
+static void sys_dump_pll_freq(void)
+{
+	print_pll_freq("CPU", g_clock_config->PLL_FREQ_CPU);
+	print_pll_freq("BUS", g_clock_config->PLL_FREQ_BUS);
+	print_pll_freq("MEM", g_clock_config->PLL_FREQ_MEM);
+	//print_pll_freq("USB", g_clock_config->PLL_FREQ_USB);
+}
+
+static void pmu_get_efuse_dcdc(int buckVoltLow[])
+{
+	static const u8 setBitCnt[8] = { 0, 1, 1, 2, 1, 2, 2, 3, };
+	u16 dcdc;
+	int i;
+
+	ispi_reg_write(0x51, 0x02ed);
+	udelay(2000);
+	ispi_reg_write(0x51, 0x02fd);
+	dcdc = ispi_reg_read(0x52);
+	ispi_reg_write(0x51, 0x0200);
+
+	for (i = 0; i < 4; i++) {
+		buckVoltLow[i] = (setBitCnt[dcdc & 0x7] > 1);
+		dcdc >>= 3;
+	}
+}
+
+static void pmu_setup_init(void)
+{
+	u32 value;
+	int buck_volt_low[4] = { 0, };
+
+	rda_nand_iodrive_set();
+
+#ifdef CONFIG_RDA_PDL
+	enable_charger(0);
+#endif
+
+	ispi_open(1);
+
+	// Disable vibrator
+	ispi_reg_write(0x03, 0x9FFF);
+	// Enable bandgap chopper mode
+	ispi_reg_write(0x0F, 0x1E90);
+	// Enable high AC throttling
+	ispi_reg_write(0x12, 0x1218);
+#ifdef TARGET_TABLET_MODE
+	// Charger current (cc = 6, pre = 7)
+	ispi_reg_write(0x13, 0x1B70);
+#else
+	// Charger current (cc = 2, pre = 7)
+	ispi_reg_write(0x13, 0x1970);
+#endif
+	// Vcore DCDC freq
+	ispi_reg_write(0x2D, 0x96BA);
+	ispi_reg_write(0x2E, 0x12AA);
+	// Get efuse dcdc
+	pmu_get_efuse_dcdc(buck_volt_low);
+	// Vcore voltage
+	value = 0x9244;
+	value = PMU_SET_BITFIELD(value, RDA_PMU_VBUCK1_BIT_ACT,
+			PMU_VBUCK1_VAL +
+			((PMU_VBUCK1_VAL < 15 && buck_volt_low[0]) ? 1 : 0));
+	ispi_reg_write(0x2F, value);
+	// DDR PWM mode
+	ispi_reg_write(0x0D, 0x92D0);
+	// DDR voltage
+	value = 0xAAB5;
+	value = PMU_SET_BITFIELD(value, RDA_PMU_VBUCK3_BIT_ACT,
+			PMU_VBUCK3_VAL +
+			((PMU_VBUCK3_VAL < 15 && buck_volt_low[2]) ? 1 : 0));
+#ifdef PMU_VBUCK4_VAL
+	value = PMU_SET_BITFIELD(value, RDA_PMU_VBUCK4_BIT_ACT,
+			PMU_VBUCK4_VAL +
+			((PMU_VBUCK4_VAL < 15 && buck_volt_low[3]) ? 1 : 0));
+	value ^= RDA_PMU_VBUCK4_BIT_ACT(8);
+	// vBuck4 in low voltage range
+	ispi_reg_write(0x36, 0x6E45);
+#else
+	ispi_reg_write(0x36, 0x6E54);
+#endif
+	ispi_reg_write(0x2A, value);
+	// DDR power parameters
+	ispi_reg_write(0x4A, 0x96AA);
+	ispi_reg_write(0x4B, 0x96AA);
+
+	ispi_open(0);
+}
+
+static void setup_ddr_vtt(int vtt)
+{
+	printf("setup ddr vtt to %d\n", vtt);
+	ispi_reg_write(0x69, g_clock_config->DDR_TIMING_069H);
+}
+
+#if 0
+/*
+ * we initialize usb clock, but this won't cause the usb clock jitter,
+ * because wo don't setup the usb pll
+ */
+static void usb_clock_pre_init(void)
+{
+	ispi_reg_write(0x83, 0x72ef);
+	ispi_reg_write(0x89, 0x7400);
+}
+#endif
+
+static void pll_setup_init(void)
+{
+	setup_ddr_vtt(DDR_VTT_VAL);
+
+	if (g_clock_config->DDR_CHAN_1_VALID) {
+		ispi_reg_write(0x100, g_clock_config->DDR_TIMING_100H);
+		ispi_reg_write(0x101, g_clock_config->DDR_TIMING_101H);
+		ispi_reg_write(0x102, g_clock_config->DDR_TIMING_102H);
+		ispi_reg_write(0x103, g_clock_config->DDR_TIMING_103H);
+		ispi_reg_write(0x104, g_clock_config->DDR_TIMING_104H);
+		ispi_reg_write(0x105, g_clock_config->DDR_TIMING_105H);
+		ispi_reg_write(0x106, g_clock_config->DDR_TIMING_106H);
+		ispi_reg_write(0x107, g_clock_config->DDR_TIMING_107H);
+		ispi_reg_write(0x108, g_clock_config->DDR_TIMING_108H);
+		ispi_reg_write(0x109, g_clock_config->DDR_TIMING_109H);
+		ispi_reg_write(0x10A, g_clock_config->DDR_TIMING_10AH);
+		ispi_reg_write(0x10B, g_clock_config->DDR_TIMING_10BH);
+		ispi_reg_write(0x10C, g_clock_config->DDR_TIMING_10CH);
+		ispi_reg_write(0x10D, g_clock_config->DDR_TIMING_10DH);
+		ispi_reg_write(0x10E, g_clock_config->DDR_TIMING_10EH);
+		ispi_reg_write(0x10F, g_clock_config->DDR_TIMING_10FH);
+	}
+
+	if (g_clock_config->DDR_CHAN_2_VALID) {
+		ispi_reg_write(0x120, g_clock_config->DDR_TIMING_120H);
+		ispi_reg_write(0x121, g_clock_config->DDR_TIMING_121H);
+		ispi_reg_write(0x122, g_clock_config->DDR_TIMING_122H);
+		ispi_reg_write(0x123, g_clock_config->DDR_TIMING_123H);
+		ispi_reg_write(0x124, g_clock_config->DDR_TIMING_124H);
+		ispi_reg_write(0x125, g_clock_config->DDR_TIMING_125H);
+		ispi_reg_write(0x126, g_clock_config->DDR_TIMING_126H);
+		ispi_reg_write(0x127, g_clock_config->DDR_TIMING_127H);
+		ispi_reg_write(0x128, g_clock_config->DDR_TIMING_128H);
+		ispi_reg_write(0x129, g_clock_config->DDR_TIMING_129H);
+		ispi_reg_write(0x12A, g_clock_config->DDR_TIMING_12AH);
+		ispi_reg_write(0x12B, g_clock_config->DDR_TIMING_12BH);
+		ispi_reg_write(0x12C, g_clock_config->DDR_TIMING_12CH);
+		ispi_reg_write(0x12D, g_clock_config->DDR_TIMING_12DH);
+		ispi_reg_write(0x12E, g_clock_config->DDR_TIMING_12EH);
+		ispi_reg_write(0x12F, g_clock_config->DDR_TIMING_12FH);
+	}
+
+	if (g_clock_config->DDR_CHAN_3_VALID) {
+		ispi_reg_write(0x140, g_clock_config->DDR_TIMING_140H);
+		ispi_reg_write(0x141, g_clock_config->DDR_TIMING_141H);
+		ispi_reg_write(0x142, g_clock_config->DDR_TIMING_142H);
+		ispi_reg_write(0x143, g_clock_config->DDR_TIMING_143H);
+		ispi_reg_write(0x144, g_clock_config->DDR_TIMING_144H);
+		ispi_reg_write(0x145, g_clock_config->DDR_TIMING_145H);
+		ispi_reg_write(0x146, g_clock_config->DDR_TIMING_146H);
+		ispi_reg_write(0x147, g_clock_config->DDR_TIMING_147H);
+		ispi_reg_write(0x148, g_clock_config->DDR_TIMING_148H);
+		ispi_reg_write(0x149, g_clock_config->DDR_TIMING_149H);
+		ispi_reg_write(0x14A, g_clock_config->DDR_TIMING_14AH);
+		ispi_reg_write(0x14B, g_clock_config->DDR_TIMING_14BH);
+		ispi_reg_write(0x14C, g_clock_config->DDR_TIMING_14CH);
+		ispi_reg_write(0x14D, g_clock_config->DDR_TIMING_14DH);
+		ispi_reg_write(0x14E, g_clock_config->DDR_TIMING_14EH);
+		ispi_reg_write(0x14F, g_clock_config->DDR_TIMING_14FH);
+	}
+
+	if (g_clock_config->DDR_CHAN_4_VALID) {
+		ispi_reg_write(0x160, g_clock_config->DDR_TIMING_160H);
+		ispi_reg_write(0x161, g_clock_config->DDR_TIMING_161H);
+		ispi_reg_write(0x162, g_clock_config->DDR_TIMING_162H);
+		ispi_reg_write(0x163, g_clock_config->DDR_TIMING_163H);
+		ispi_reg_write(0x164, g_clock_config->DDR_TIMING_164H);
+		ispi_reg_write(0x165, g_clock_config->DDR_TIMING_165H);
+		ispi_reg_write(0x166, g_clock_config->DDR_TIMING_166H);
+		ispi_reg_write(0x167, g_clock_config->DDR_TIMING_167H);
+		ispi_reg_write(0x168, g_clock_config->DDR_TIMING_168H);
+		ispi_reg_write(0x169, g_clock_config->DDR_TIMING_169H);
+		ispi_reg_write(0x16A, g_clock_config->DDR_TIMING_16AH);
+		ispi_reg_write(0x16B, g_clock_config->DDR_TIMING_16BH);
+		ispi_reg_write(0x16C, g_clock_config->DDR_TIMING_16CH);
+		ispi_reg_write(0x16D, g_clock_config->DDR_TIMING_16DH);
+		ispi_reg_write(0x16E, g_clock_config->DDR_TIMING_16EH);
+		ispi_reg_write(0x16F, g_clock_config->DDR_TIMING_16FH);
+	}
+
+	ispi_reg_write(0x180, g_clock_config->DDR_TIMING_180H);
+	ispi_reg_write(0x181, g_clock_config->DDR_TIMING_181H);
+	ispi_reg_write(0x182, g_clock_config->DDR_TIMING_182H);
+	ispi_reg_write(0x183, g_clock_config->DDR_TIMING_183H);
+	ispi_reg_write(0x184, g_clock_config->DDR_TIMING_184H);
+	ispi_reg_write(0x185, g_clock_config->DDR_TIMING_185H);
+	ispi_reg_write(0x186, g_clock_config->DDR_TIMING_186H);
+	ispi_reg_write(0x187, g_clock_config->DDR_TIMING_187H);
+	ispi_reg_write(0x188, g_clock_config->DDR_TIMING_188H);
+	ispi_reg_write(0x189, g_clock_config->DDR_TIMING_189H);
+	ispi_reg_write(0x18A, g_clock_config->DDR_TIMING_18AH);
+	ispi_reg_write(0x18B, g_clock_config->DDR_TIMING_18BH);
+	ispi_reg_write(0x18C, g_clock_config->DDR_TIMING_18CH);
+
+	//usb_clock_pre_init();
+
+	udelay(5000);
+}
+
+static void pll_setup_mem(void)
+{
+}
+
+static void pll_setup_mem_cal(void)
+{
+}
+
+static void print_pll_reg(UINT32 index, UINT32 value)
+{
+	printf("pll reg %lx = %lx\n", index, value);
+}
+
+static void pll_dump_reg(void)
+{
+	print_pll_reg(0x005, ispi_reg_read(0x005));
+	print_pll_reg(0x006, ispi_reg_read(0x006));
+	print_pll_reg(0x063, ispi_reg_read(0x063));
+	print_pll_reg(0x065, ispi_reg_read(0x065));
+	print_pll_reg(0x066, ispi_reg_read(0x066));
+	print_pll_reg(0x069, ispi_reg_read(0x069));
+
+	if (g_clock_config->DDR_CHAN_1_VALID)
+	{
+		print_pll_reg(0x100, ispi_reg_read(0x100));
+		print_pll_reg(0x101, ispi_reg_read(0x101));
+		print_pll_reg(0x102, ispi_reg_read(0x102));
+		print_pll_reg(0x103, ispi_reg_read(0x103));
+		print_pll_reg(0x104, ispi_reg_read(0x104));
+		print_pll_reg(0x105, ispi_reg_read(0x105));
+		print_pll_reg(0x106, ispi_reg_read(0x106));
+		print_pll_reg(0x107, ispi_reg_read(0x107));
+		print_pll_reg(0x108, ispi_reg_read(0x108));
+		print_pll_reg(0x109, ispi_reg_read(0x109));
+		print_pll_reg(0x10A, ispi_reg_read(0x10A));
+		print_pll_reg(0x10B, ispi_reg_read(0x10B));
+		print_pll_reg(0x10C, ispi_reg_read(0x10C));
+		print_pll_reg(0x10D, ispi_reg_read(0x10D));
+		print_pll_reg(0x10E, ispi_reg_read(0x10E));
+		print_pll_reg(0x10F, ispi_reg_read(0x10F));
+	}
+
+	if (g_clock_config->DDR_CHAN_2_VALID)
+	{
+		print_pll_reg(0x120, ispi_reg_read(0x120));
+		print_pll_reg(0x121, ispi_reg_read(0x121));
+		print_pll_reg(0x122, ispi_reg_read(0x122));
+		print_pll_reg(0x123, ispi_reg_read(0x123));
+		print_pll_reg(0x124, ispi_reg_read(0x124));
+		print_pll_reg(0x125, ispi_reg_read(0x125));
+		print_pll_reg(0x126, ispi_reg_read(0x126));
+		print_pll_reg(0x127, ispi_reg_read(0x127));
+		print_pll_reg(0x128, ispi_reg_read(0x128));
+		print_pll_reg(0x129, ispi_reg_read(0x129));
+		print_pll_reg(0x12A, ispi_reg_read(0x12A));
+		print_pll_reg(0x12B, ispi_reg_read(0x12B));
+		print_pll_reg(0x12C, ispi_reg_read(0x12C));
+		print_pll_reg(0x12D, ispi_reg_read(0x12D));
+		print_pll_reg(0x12E, ispi_reg_read(0x12E));
+		print_pll_reg(0x12F, ispi_reg_read(0x12F));
+	}
+
+	if (g_clock_config->DDR_CHAN_3_VALID)
+	{
+		print_pll_reg(0x140, ispi_reg_read(0x140));
+		print_pll_reg(0x141, ispi_reg_read(0x141));
+		print_pll_reg(0x142, ispi_reg_read(0x142));
+		print_pll_reg(0x143, ispi_reg_read(0x143));
+		print_pll_reg(0x144, ispi_reg_read(0x144));
+		print_pll_reg(0x145, ispi_reg_read(0x145));
+		print_pll_reg(0x146, ispi_reg_read(0x146));
+		print_pll_reg(0x147, ispi_reg_read(0x147));
+		print_pll_reg(0x148, ispi_reg_read(0x148));
+		print_pll_reg(0x149, ispi_reg_read(0x149));
+		print_pll_reg(0x14A, ispi_reg_read(0x14A));
+		print_pll_reg(0x14B, ispi_reg_read(0x14B));
+		print_pll_reg(0x14C, ispi_reg_read(0x14C));
+		print_pll_reg(0x14D, ispi_reg_read(0x14D));
+		print_pll_reg(0x14E, ispi_reg_read(0x14E));
+		print_pll_reg(0x14F, ispi_reg_read(0x14F));
+	}
+
+	if (g_clock_config->DDR_CHAN_4_VALID)
+	{
+		print_pll_reg(0x160, ispi_reg_read(0x160));
+		print_pll_reg(0x161, ispi_reg_read(0x161));
+		print_pll_reg(0x162, ispi_reg_read(0x162));
+		print_pll_reg(0x163, ispi_reg_read(0x163));
+		print_pll_reg(0x164, ispi_reg_read(0x164));
+		print_pll_reg(0x165, ispi_reg_read(0x165));
+		print_pll_reg(0x166, ispi_reg_read(0x166));
+		print_pll_reg(0x167, ispi_reg_read(0x167));
+		print_pll_reg(0x168, ispi_reg_read(0x168));
+		print_pll_reg(0x169, ispi_reg_read(0x169));
+		print_pll_reg(0x16A, ispi_reg_read(0x16A));
+		print_pll_reg(0x16B, ispi_reg_read(0x16B));
+		print_pll_reg(0x16C, ispi_reg_read(0x16C));
+		print_pll_reg(0x16D, ispi_reg_read(0x16D));
+		print_pll_reg(0x16E, ispi_reg_read(0x16E));
+		print_pll_reg(0x16F, ispi_reg_read(0x16F));
+	}
+
+	print_pll_reg(0x180, ispi_reg_read(0x180));
+	print_pll_reg(0x181, ispi_reg_read(0x181));
+	print_pll_reg(0x182, ispi_reg_read(0x182));
+	print_pll_reg(0x183, ispi_reg_read(0x183));
+	print_pll_reg(0x184, ispi_reg_read(0x184));
+	print_pll_reg(0x185, ispi_reg_read(0x185));
+	print_pll_reg(0x186, ispi_reg_read(0x186));
+	print_pll_reg(0x187, ispi_reg_read(0x187));
+	print_pll_reg(0x188, ispi_reg_read(0x188));
+	print_pll_reg(0x189, ispi_reg_read(0x189));
+	print_pll_reg(0x18A, ispi_reg_read(0x18A));
+	print_pll_reg(0x18B, ispi_reg_read(0x18B));
+	print_pll_reg(0x18C, ispi_reg_read(0x18C));
+}
+
+static int clock_save_config(void)
+{
+	/* save config to nand */
+	return 1;
+}
+
+#ifdef DO_DDR_PLL_DEBUG
+
+static int ddr_get_freq(UINT8 chioce)
+{
+	switch(chioce)
+	{
+		case 1:
+			return 50;
+		case 2:
+			return 100;
+		case 3:
+			return 156;
+		case 4:
+			return 200;
+		case 5:
+			return 290;
+		case 6:
+			return 333;
+		case 7:
+			return 355;
+		case 8:
+			return 400;
+		case 9:
+			return 416;
+		case 10:
+			return 455;
+		case 11:
+			return 519;
+		case 12:
+			return 533;
+		case 13:
+			return 260;
+		default:
+			return -1;
+	}
+}
+
+static void freq_choose(void)
+{
+	UINT8 i = 0, buf[3] = {0}, choice = 0;
+	INT32 freq_temp = 0;
+
+	printf("\nPlese choose the ddr Freq:");
+	printf("\n1.50M  2.100M  3.156M  4.200M  5.290M  6.333M  7.355M  8.400M 9.416M 10.455M 11.519M 12.533M 13.260M");
+	printf("\nThe number is:");
+
+	while(1)
+	{
+		if (i > 2)
+		{
+			printf("\n Sorry, you input is wrong. Please input again:");
+			i = 0;
+		}
+		buf[i] = serial_getc();
+		serial_putc(buf[i]);
+
+		if ( ('\r' == buf[i]) || ('\n' == buf[i]))
+		{
+			serial_puts("\n");
+			break;
+		}
+
+		i++;
+	}
+
+	if (1 == i)
+		choice = buf[0] - 0x30;
+	else if (2 == i)
+		choice = 10*(buf[0] - 0x30) + (buf[1] - 0x30);
+	else
+		return;
+
+	freq_temp = ddr_get_freq(choice);
+	if (-1 == freq_temp )
+		printf("\n Sorry, the fre you choose is wrong");
+	ddrfreq = freq_temp;
+}
+
+static void data_bits_choose(void)
+{
+	UINT8 i = 0, buf[2] = {0};
+
+	printf("\nPlese choose the ddr data bits:");
+	printf("\n1.16  2.32");
+	printf("\nThe number is:");
+
+	while(1)
+	{
+		buf[i] =serial_getc();
+
+		if (i == 1)
+		{
+			if (('\r' == buf[i]) || ('\n' == buf[i]))
+			{
+				if (1 == (buf[0] - 0x30))
+					ddr32bit = 0;
+				else
+					ddr32bit = 1;
+				return;
+			}
+			else
+			{
+				printf("\n Sorry, you input is wrong. Please input again:");
+				i = 0;
+				continue;
+			}
+		}
+
+		serial_putc(buf[i]);
+
+		if ((buf[i] - 0x30) > 2 || 0 == (buf[i] - 0x30))
+			printf("\n Sorry, you input is wrong. Please input again:");
+		else
+			i++;
+	}
+}
+
+#if 0
+static void pmu_setup_calibration_voltage(UINT8 vcoreselect)
+{
+	UINT8 buf[3] = {0}, voltage = 0;
+	int i = 0;
+	UINT32 reg_value,temp, regid = 0;
+
+	ispi_open(1);
+	if (1 == vcoreselect)
+	{
+		regid = 0x2f;
+		printf("\nPlese input vcore voltage(0 ~ 15):");
+	}
+	else
+	{
+		regid = 0x2a;
+		printf("\nPlese input DDR voltage(0 ~ 15):");
+	}
+
+
+	while(1)
+	{
+		if (i > 2)
+		{
+			printf("\n Sorry, you input is wrong. Please input again:");
+			i = 0;
+		}
+		buf[i] = serial_getc();
+		serial_putc(buf[i]);
+
+		if ( ('\r' == buf[i]) || ('\n' == buf[i]))
+		{
+			printf("\n");
+			break;
+		}
+
+		i++;
+	}
+
+	if (1 == i)
+		voltage = buf[0] - 0x30;
+	else if (2 == i)
+		voltage = 10*(buf[0] - 0x30) + (buf[1] - 0x30);
+	else
+		return;
+
+	temp = (UINT32)voltage;
+	temp = (temp & 0xf) << 12;
+	reg_value = ispi_reg_read(regid);
+	reg_value &= ~(0xf << 12);
+	reg_value |= temp ;
+	ispi_reg_write(regid, reg_value);
+	mdelay(100);
+}
+#endif
+
+static void pmu_setup_calibration_voltage(UINT8 vcoreselect)
+{
+	UINT8 buf[3] = {0}, voltage = 0;
+	int i = 0;
+	UINT32 reg_value,temp, regid = 0;
+
+	ispi_open(1);
+	if (1 == vcoreselect)
+	{
+		regid = 0x2f;
+		printf("\nPlese input vcore voltage(0 ~ 15):");
+	}
+	else
+	{
+		regid = 0x2a;
+		if (2 == vcoreselect)
+			printf("\nPlese input DDR buck3 voltage(0 ~ 15):");
+		else
+			printf("\nPlese input DDR buck4 voltage(0 ~ 15):");
+	}
+
+	while(1)
+	{
+		if (i > 2)
+		{
+			printf("\n Sorry, you input is wrong. Please input again:");
+			i = 0;
+		}
+		buf[i] = serial_getc();
+		serial_putc(buf[i]);
+
+		if ( ('\r' == buf[i]) || ('\n' == buf[i]))
+		{
+			printf("\n");
+			break;
+		}
+
+		i++;
+	}
+
+	if (1 == i)
+		voltage = buf[0] - 0x30;
+	else if (2 == i)
+		voltage = 10*(buf[0] - 0x30) + (buf[1] - 0x30);
+	else
+		return;
+
+	if ((vcoreselect == 1) || (vcoreselect == 2))
+	{
+		temp = (UINT32)voltage;
+		temp = (temp & 0xf) << 12;
+		reg_value = ispi_reg_read(regid);
+		reg_value &= ~(0xf << 12);
+		reg_value |= temp ;
+		ispi_reg_write(regid, reg_value);
+		mdelay(100);
+	}
+	else
+	{
+		temp = (UINT32)voltage;
+		temp = (temp & 0xf) << 4;
+		reg_value = ispi_reg_read(regid);
+		reg_value &= ~(0xf << 4);
+		reg_value |= temp ;
+		reg_value ^= RDA_PMU_VBUCK4_BIT_ACT(8);
+		ispi_reg_write(regid, reg_value);
+		ispi_reg_write(0x0D, 0x92D0);
+		ispi_reg_write(0x4B, 0x96A8);
+		mdelay(100);
+	}
+}
+
+static void pmu_buck4_buck3_choose(void)
+{
+	UINT8 i = 0, buf[2] = {0};
+	UINT8 ddr_voltage_source = 0;
+
+	printf("\nPlese choose the ddr voltage:");
+	printf("\n1.DDR3L  2.DDR3");
+	printf("\nThe number is:");
+
+	while(1)
+	{
+		buf[i] =serial_getc();
+
+		if (i == 1)
+		{
+			if (('\r' == buf[i]) || ('\n' == buf[i]))
+			{
+				if (1 == (buf[0] - 0x30))
+					ddr_voltage_source =2;
+				else{
+					ddr_voltage_source = 3;
+					pmu_setup_calibration_voltage(2);
+				}
+				pmu_setup_calibration_voltage(ddr_voltage_source);
+				return;
+			}
+			else
+			{
+				printf("\n Sorry, you input is wrong. Please input again:");
+				i = 0;
+				continue;
+			}
+		}
+
+		serial_putc(buf[i]);
+
+		if ((buf[i] - 0x30) > 2 || 0 == (buf[i] - 0x30))
+			printf("\n Sorry, you input is wrong. Please input again:");
+		else
+			i++;
+	}
+}
+
+
+void clock_load_ddr_cal_config(void)
+{
+	clock_debug_config.PLL_FREQ_MEM = ddrfreq;
+	if (ddrfreq < 200)
+		clock_debug_config.DDR_FLAGS |= DDR_FLAGS_DLLOFF;
+	else
+		clock_debug_config.DDR_FLAGS &= ~DDR_FLAGS_DLLOFF;
+
+	if (0 == ddr32bit)
+	{
+		clock_debug_config.DDR_CHAN_3_VALID = 0;
+		clock_debug_config.DDR_CHAN_4_VALID = 0;
+	}
+
+	clock_debug_config.DDR_PARA &= ~DDR_PARA_MEM_BITS_MASK;
+	if (0 == ddr32bit)
+		clock_debug_config.DDR_PARA |= DDR_PARA_MEM_BITS(1);
+	else
+		clock_debug_config.DDR_PARA |= DDR_PARA_MEM_BITS(2);
+}
+
+static int serial_gets(UINT8 *pstr)
+{
+    UINT32 length;
+
+    length = 0;
+    while(1) {
+        pstr[length] = serial_getc();
+        if(pstr[length] == '\r') {
+            pstr[length] = 0x00;
+            break;
+        }
+        else if( pstr[length] == '\b' ) {
+            if(length>0) {
+                length --;
+                printf("\b");
+            }
+        }
+        else {
+            serial_putc(pstr[length]);
+            length ++;
+        }
+
+        if(length > 32)
+            return -1;
+    }
+    return length;
+}
+
+UINT32 asc2hex(UINT8 *pstr, UINT8 len)
+{
+	UINT8 i,ch,mylen;
+	UINT32 hexvalue;
+
+	for(mylen=0,i=0; i<8; i++)
+	{
+		if( pstr[i] == 0 )
+			break;
+		mylen ++;
+	}
+	if( len != 0 )
+	{
+		if(mylen>len)
+			mylen = len;
+	}
+	if(mylen>8)
+		mylen = 8;
+
+	hexvalue = 0;
+	for (i = 0; i < mylen; i++)
+	{
+		hexvalue <<= 4;
+		ch = *(pstr+i);
+		if((ch>='0') && (ch<='9'))
+			hexvalue |= ch - '0';
+		else if((ch>='A') && (ch<='F'))
+			hexvalue |= ch - ('A' - 10);
+		else if((ch>='a') && (ch<='f'))
+			hexvalue |= ch - ('a' - 10);
+		else
+			;
+	}
+	return(hexvalue);
+}
+
+static int process_cmd(char * cmd)
+{
+	char cmd_element[3][16] = {{0}};
+	char * cmd_temp = cmd;
+	UINT8 i = 0, cmd_element_num = 0, former_space = 1;
+	UINT16 reg = 0, reg_value = 0;
+
+	if (NULL == cmd)
+		return -1;
+
+	while(('\0' != *cmd_temp) && ('\r' != *cmd_temp) && ('\n' != *cmd_temp))
+	{
+		if (' ' == * cmd_temp)
+		{
+			if (0 == former_space)
+			{
+				former_space = 1;
+				cmd_element[cmd_element_num][i] = '\0';
+				cmd_element_num++;
+				if (cmd_element_num > 2)
+					return -1;
+			
+				i = 0;
+			}
+		}
+		else
+		{
+			former_space = 0;
+			cmd_element[cmd_element_num][i] = *cmd_temp;
+			i++;
+			if (i > 6)
+				return -1;
+		}
+
+		cmd_temp++;	
+	}
+
+	cmd_element[cmd_element_num][i] = '\0';
+
+	if (!strcmp(cmd_element[0], "read"))
+	{
+		if (cmd_element_num == 2)
+			return -1;
+		if (('0' != cmd_element[1][0]) || ('x' != cmd_element[1][1]))
+			return -1;
+		reg = (UINT16)asc2hex((UINT8 *)&cmd_element[1][2], 4);
+		reg_value = ispi_reg_read(reg);
+		printf("value = 0x%x", reg_value);
+		printf("\nddrPll#");
+	}	
+	else if (!strcmp(cmd_element[0], "write"))
+	{
+		if (cmd_element_num != 2)
+			return -1;
+		if (('0' != cmd_element[1][0]) || ('x' != cmd_element[1][1])
+		   || ('0' != cmd_element[2][0]) || ('x' != cmd_element[2][1]))
+			return -1;
+
+		reg = (UINT16)asc2hex((UINT8 *)&cmd_element[1][2], 4);
+		reg_value  = (UINT16)asc2hex((UINT8 *)&cmd_element[2][2], 4);
+		ispi_reg_write(reg, reg_value);
+	}
+	else if (!strcmp(cmd_element[0], "finish"))
+	{
+		return 1;
+	}
+	else if (!strcmp(cmd_element[0], "dump"))
+	{    
+		pll_dump_reg();
+		printf("ddrPll#");
+	}
+	else
+	{    
+		return -1;
+	}
+
+	return 0;
+}
+
+static void cmd_input(void)
+{
+	char cmd[48] = {0};
+	int len = 0;
+	
+	ispi_open(0);
+	printf("\nddrPll#");
+	while(1)
+	{
+		len = serial_gets((UINT8 *)cmd);
+		printf("\nddrPll#");
+		if (len > 0)
+		{
+			int result = 0;
+
+			result =  process_cmd(cmd);
+			if (-1 == result)
+				printf("command error! \nddrPll#");
+			else if (1 == result)
+				break;
+			else
+				continue;
+		}
+	}
+
+	return;
+}
+
+#endif /* DO_DDR_PLL_DEBUG */
+
+int clock_init(void)
+{
+#ifdef DO_DDR_PLL_DEBUG
+	char choice = 'n';
+#endif
+
+	/* First check current usb usage */
+	check_usb_usage();
+
+	printf("Init Clock ...\n");
+	g_clock_config = get_default_clock_config();
+
+	printf("Clock config ver: %d.%d\n",
+		g_clock_config->VERSION_MAJOR, g_clock_config->VERSION_MINOR);
+
+	pmu_setup_init();
+
+#ifdef DO_DDR_PLL_DEBUG
+	printf("If you want to config the ddr para manully ?(y = yes, n = no) \n");
+	choice = serial_getc();
+	if (choice == 'y')
+	{
+		memcpy(&clock_debug_config, g_clock_config,
+				sizeof(clock_debug_config));
+		g_clock_config = &clock_debug_config;
+		pmu_setup_calibration_voltage(1);
+		pmu_buck4_buck3_choose();
+		freq_choose();
+		data_bits_choose();
+		clock_load_ddr_cal_config();
+	}
+#endif
+
+	sys_shutdown_pll();
+	ispi_open(0);
+	pll_setup_init();
+#ifdef DO_DDR_PLL_DEBUG
+	if (choice == 'y')
+		cmd_input();
+#endif
+	pll_setup_freq();
+	sys_setup_pll();
+	sys_setup_clk();
+
+	if (g_clock_config->DDR_CAL) {
+		printf("Init DDR for ddr_cal\n");
+		ddr_init(g_clock_config->DDR_FLAGS, g_clock_config->DDR_PARA);
+		printf("Done\n");
+		pll_setup_mem_cal();
+		clock_save_config();
+	} else {
+		pll_setup_mem();
+	}
+
+	sys_dump_pll_freq();
+	sys_dump_clk();
+	pll_dump_reg();
+
+	printf("Init DDR, flag = 0x%04x, para = 0x%08lx\n",
+		g_clock_config->DDR_FLAGS, g_clock_config->DDR_PARA);
+	ddr_init(g_clock_config->DDR_FLAGS, g_clock_config->DDR_PARA);
+	printf("Done\n");
+
+	#ifdef DO_SIMPLE_DDR_TEST
+	mem_test_write();
+	mem_test_read();
+#endif
+
+	return 0;
+}
+
+#else /* CONFIG_RDA_FPGA */
+
+int clock_init(void)
+{
+	u16 ddr_flags = DDR_FLAGS_DLLOFF
+		| DDR_FLAGS_ODT(1)
+		| DDR_FLAGS_RON(0);
+	//16bit
+	u32 ddr_para = DDR_PARA_MEM_BITS(1)
+		| DDR_PARA_BANK_BITS(3)
+		| DDR_PARA_ROW_BITS(3)
+		| DDR_PARA_COL_BITS(2);
+
+	printf("Init DDR\n");
+	ddr_init(ddr_flags, ddr_para);
+	printf("Done\n");
+
+#ifdef DO_SIMPLE_DDR_TEST
+	mem_test_write();
+	mem_test_read();
+#endif
+
+	return 0;
+}
+
+#endif /* CONFIG_RDA_FPGA */
+
diff --git a/board/rda/rda8810e/clock_config.c b/board/rda/rda8810e/clock_config.c
new file mode 100644
index 0000000000..85254c90d7
--- /dev/null
+++ b/board/rda/rda8810e/clock_config.c
@@ -0,0 +1,149 @@
+#ifndef TARGET_TOOL
+#include <common.h>
+#include <asm/arch/factory.h>
+#include "clock_config.h"
+#endif
+
+#include "ddr3.h"
+#include "tgt_ap_clock_config.h"
+
+static const struct clock_config clock_default_config = {
+	/* Header */
+	0, 			// MAGIC;
+	CLOCK_VER_MAJOR,	// VERSION_MAJOR;
+	CLOCK_VER_MINOR,	// VERSION_MINOR;
+	/* PLL Freqs (MHz) */
+	_TGT_AP_PLL_CPU_FREQ,	// PLL_FREQ_CPU; /* 05, 06 */
+	_TGT_AP_PLL_BUS_FREQ,	// PLL_FREQ_BUS; /* 25, 26 */
+	_TGT_AP_PLL_MEM_FREQ,	// PLL_FREQ_MEM; /* 65, 66 */
+	_TGT_AP_PLL_USB_FREQ,	// PLL_FREQ_USB; /* 85, 86 */
+	/* DDR Cal */
+	0,			// DDR_CAL;
+	/* DDR_FLAGS */
+	DDR_FLAGS_ODT(_TGT_AP_DDR_ODT)	// 010 -- 120 Ohm
+#if (_TGT_AP_DDR_CLOCK < 200)
+	    | DDR_FLAGS_DLLOFF
+#endif
+#ifdef _TGT_AP_DDR_LOWPWR
+	    | DDR_FLAGS_LOWPWR
+#endif
+	    | DDR_FLAGS_RON(_TGT_AP_DDR_RON),	// 00 -- 40 Ohm
+	/* DDR_PARA */
+	DDR_PARA_CHIP_BITS(_TGT_AP_DDR_CHIP_BITS)
+	    | DDR_PARA_MEM_BITS(_TGT_AP_DDR_MEM_BITS)
+	    | DDR_PARA_BANK_BITS(_TGT_AP_DDR_BANK_BITS)
+	    | DDR_PARA_ROW_BITS(_TGT_AP_DDR_ROW_BITS )
+	    | DDR_PARA_COL_BITS(_TGT_AP_DDR_COL_BITS),
+
+	/* AP sysctrl */
+	_TGT_AP_CLK_CPU,	// CLK_CPU;
+	_TGT_AP_CLK_AXI,	// CLK_AXI;
+	_TGT_AP_CLK_GCG,	// CLK_GCG;
+	_TGT_AP_CLK_AHB1,	// CLK_AHB1;
+	_TGT_AP_CLK_APB1,	// CLK_APB1;
+	_TGT_AP_CLK_APB2,	// CLK_APB2;
+	_TGT_AP_CLK_MEM,	// CLK_MEM;
+	_TGT_AP_CLK_GPU,	// CLK_GPU;
+	_TGT_AP_CLK_VPU,	// CLK_VPU;
+	_TGT_AP_CLK_VOC,	// CLK_VOC;
+	_TGT_AP_CLK_SFLSH,	// CLK_SFLSH;
+	0,			// RESERVE;
+
+	/* DDR timings, defined in target */
+	DDR_CHAN_1_VALID_VAL,	// DDR_CHAN_1_VALID;
+	DDR_TIMING_100H_VAL,	// DDR_TIMING_100H;
+	DDR_TIMING_101H_VAL,	// DDR_TIMING_101H;
+	DDR_TIMING_102H_VAL,	// DDR_TIMING_102H;
+	DDR_TIMING_103H_VAL,	// DDR_TIMING_103H;
+	DDR_TIMING_104H_VAL,	// DDR_TIMING_104H;
+	DDR_TIMING_105H_VAL,	// DDR_TIMING_105H;
+	DDR_TIMING_106H_VAL,	// DDR_TIMING_106H;
+	DDR_TIMING_107H_VAL,	// DDR_TIMING_107H;
+	DDR_TIMING_108H_VAL,	// DDR_TIMING_108H;
+	DDR_TIMING_109H_VAL,	// DDR_TIMING_109H;
+	DDR_TIMING_10AH_VAL,	// DDR_TIMING_10AH;
+	DDR_TIMING_10BH_VAL,	// DDR_TIMING_10BH;
+	DDR_TIMING_10CH_VAL,	// DDR_TIMING_10CH;
+	DDR_TIMING_10DH_VAL,	// DDR_TIMING_10DH;
+	DDR_TIMING_10EH_VAL,	// DDR_TIMING_10EH;
+	DDR_TIMING_10FH_VAL,	// DDR_TIMING_10FH;
+
+	DDR_CHAN_2_VALID_VAL,	// DDR_CHAN_2_VALID;
+	DDR_TIMING_120H_VAL,	// DDR_TIMING_120H;
+	DDR_TIMING_121H_VAL,	// DDR_TIMING_121H;
+	DDR_TIMING_122H_VAL,	// DDR_TIMING_122H;
+	DDR_TIMING_123H_VAL,	// DDR_TIMING_123H;
+	DDR_TIMING_124H_VAL,	// DDR_TIMING_124H;
+	DDR_TIMING_125H_VAL,	// DDR_TIMING_125H;
+	DDR_TIMING_126H_VAL,	// DDR_TIMING_126H;
+	DDR_TIMING_127H_VAL,	// DDR_TIMING_127H;
+	DDR_TIMING_128H_VAL,	// DDR_TIMING_128H;
+	DDR_TIMING_129H_VAL,	// DDR_TIMING_129H;
+	DDR_TIMING_12AH_VAL,	// DDR_TIMING_12AH;
+	DDR_TIMING_12BH_VAL,	// DDR_TIMING_12BH;
+	DDR_TIMING_12CH_VAL,	// DDR_TIMING_12CH;
+	DDR_TIMING_12DH_VAL,	// DDR_TIMING_12DH;
+	DDR_TIMING_12EH_VAL,	// DDR_TIMING_12EH;
+	DDR_TIMING_12FH_VAL,	// DDR_TIMING_12FH;
+
+	DDR_CHAN_3_VALID_VAL,	// DDR_CHAN_3_VALID;
+	DDR_TIMING_140H_VAL,	// DDR_TIMING_140H;
+	DDR_TIMING_141H_VAL,	// DDR_TIMING_141H;
+	DDR_TIMING_142H_VAL,	// DDR_TIMING_142H;
+	DDR_TIMING_143H_VAL,	// DDR_TIMING_143H;
+	DDR_TIMING_144H_VAL,	// DDR_TIMING_144H;
+	DDR_TIMING_145H_VAL,	// DDR_TIMING_145H;
+	DDR_TIMING_146H_VAL,	// DDR_TIMING_146H;
+	DDR_TIMING_147H_VAL,	// DDR_TIMING_147H;
+	DDR_TIMING_148H_VAL,	// DDR_TIMING_148H;
+	DDR_TIMING_149H_VAL,	// DDR_TIMING_149H;
+	DDR_TIMING_14AH_VAL,	// DDR_TIMING_14AH;
+	DDR_TIMING_14BH_VAL,	// DDR_TIMING_14BH;
+	DDR_TIMING_14CH_VAL,	// DDR_TIMING_14CH;
+	DDR_TIMING_14DH_VAL,	// DDR_TIMING_14DH;
+	DDR_TIMING_14EH_VAL,	// DDR_TIMING_14EH;
+	DDR_TIMING_14FH_VAL,	// DDR_TIMING_14FH;
+
+	DDR_CHAN_4_VALID_VAL,	// DDR_CHAN_4_VALID;
+	DDR_TIMING_160H_VAL,	// DDR_TIMING_160H;
+	DDR_TIMING_161H_VAL,	// DDR_TIMING_161H;
+	DDR_TIMING_162H_VAL,	// DDR_TIMING_162H;
+	DDR_TIMING_163H_VAL,	// DDR_TIMING_163H;
+	DDR_TIMING_164H_VAL,	// DDR_TIMING_164H;
+	DDR_TIMING_165H_VAL,	// DDR_TIMING_165H;
+	DDR_TIMING_166H_VAL,	// DDR_TIMING_166H;
+	DDR_TIMING_167H_VAL,	// DDR_TIMING_167H;
+	DDR_TIMING_168H_VAL,	// DDR_TIMING_168H;
+	DDR_TIMING_169H_VAL,	// DDR_TIMING_169H;
+	DDR_TIMING_16AH_VAL,	// DDR_TIMING_16AH;
+	DDR_TIMING_16BH_VAL,	// DDR_TIMING_16BH;
+	DDR_TIMING_16CH_VAL,	// DDR_TIMING_16CH;
+	DDR_TIMING_16DH_VAL,	// DDR_TIMING_16DH;
+	DDR_TIMING_16EH_VAL,	// DDR_TIMING_16EH;
+	DDR_TIMING_16FH_VAL,	// DDR_TIMING_16FH;
+
+	DDR_TIMING_180H_VAL,	// DDR_TIMING_180H;
+	DDR_TIMING_181H_VAL,	// DDR_TIMING_181H;
+	DDR_TIMING_182H_VAL,	// DDR_TIMING_182H;
+	DDR_TIMING_183H_VAL,	// DDR_TIMING_183H;
+	DDR_TIMING_184H_VAL,	// DDR_TIMING_184H;
+	DDR_TIMING_185H_VAL,	// DDR_TIMING_185H;
+	DDR_TIMING_186H_VAL,	// DDR_TIMING_186H;
+	DDR_TIMING_187H_VAL,	// DDR_TIMING_187H;
+	DDR_TIMING_188H_VAL,	// DDR_TIMING_188H;
+	DDR_TIMING_189H_VAL,	// DDR_TIMING_189H;
+	DDR_TIMING_18AH_VAL,	// DDR_TIMING_18AH;
+	DDR_TIMING_18BH_VAL,	// DDR_TIMING_18BH;
+	DDR_TIMING_18CH_VAL,	// DDR_TIMING_18CH;
+	DDR_TIMING_069H_VAL		// DDR_TIMING_18CH;
+};
+
+const struct clock_config *get_default_clock_config(void)
+{
+#ifndef TARGET_TOOL
+	BUILD_BUG_ON(sizeof(struct clock_config) > AP_FACTORY_CLOCK_CFG_LEN);
+#endif
+
+	return &clock_default_config;
+}
+
diff --git a/board/rda/rda8810e/clock_config.h b/board/rda/rda8810e/clock_config.h
new file mode 100644
index 0000000000..3e472df08d
--- /dev/null
+++ b/board/rda/rda8810e/clock_config.h
@@ -0,0 +1,132 @@
+#ifndef __CLOCK_CONFIG_H__
+#define __CLOCK_CONFIG_H__
+
+typedef unsigned long               UINT32;
+typedef unsigned short              UINT16;
+typedef long                        INT32;
+typedef short                       INT16;
+typedef unsigned char               UINT8;
+typedef char                        INT8;
+
+#define CLOCK_VER_MAJOR		2
+#define CLOCK_VER_MINOR		0
+
+struct clock_config {
+	/* Header */
+	UINT32 MAGIC;
+	UINT16 VERSION_MAJOR;
+	UINT16 VERSION_MINOR;
+	/* PLL Freqs (MHz) */
+	UINT32 PLL_FREQ_CPU;	/* 05, 06 */
+	UINT32 PLL_FREQ_BUS;	/* 25, 26 */
+	UINT32 PLL_FREQ_MEM;	/* 65, 66 */
+	UINT32 PLL_FREQ_USB;	/* 85, 86 */
+	/* DDR Flags */
+	UINT16 DDR_CAL;
+	UINT16 DDR_FLAGS;
+	UINT32 DDR_PARA;
+	/* AP sysctrl */
+	UINT16 CLK_CPU;
+	UINT16 CLK_AXI;
+	UINT16 CLK_GCG;
+	UINT16 CLK_AHB1;
+	UINT16 CLK_APB1;
+	UINT16 CLK_APB2;
+	UINT16 CLK_MEM;
+	UINT16 CLK_GPU;
+	UINT16 CLK_VPU;
+	UINT16 CLK_VOC;
+	UINT16 CLK_SFLSH;
+	UINT16 RESERVE;
+	/* DDR timings */
+	UINT16 DDR_CHAN_1_VALID;
+	UINT16 DDR_TIMING_100H;
+	UINT16 DDR_TIMING_101H;
+	UINT16 DDR_TIMING_102H;
+	UINT16 DDR_TIMING_103H;
+	UINT16 DDR_TIMING_104H;
+	UINT16 DDR_TIMING_105H;
+	UINT16 DDR_TIMING_106H;
+	UINT16 DDR_TIMING_107H;
+	UINT16 DDR_TIMING_108H;
+	UINT16 DDR_TIMING_109H;
+	UINT16 DDR_TIMING_10AH;
+	UINT16 DDR_TIMING_10BH;
+	UINT16 DDR_TIMING_10CH;
+	UINT16 DDR_TIMING_10DH;
+	UINT16 DDR_TIMING_10EH;
+	UINT16 DDR_TIMING_10FH;
+
+	UINT16 DDR_CHAN_2_VALID;
+	UINT16 DDR_TIMING_120H;
+	UINT16 DDR_TIMING_121H;
+	UINT16 DDR_TIMING_122H;
+	UINT16 DDR_TIMING_123H;
+	UINT16 DDR_TIMING_124H;
+	UINT16 DDR_TIMING_125H;
+	UINT16 DDR_TIMING_126H;
+	UINT16 DDR_TIMING_127H;
+	UINT16 DDR_TIMING_128H;
+	UINT16 DDR_TIMING_129H;
+	UINT16 DDR_TIMING_12AH;
+	UINT16 DDR_TIMING_12BH;
+	UINT16 DDR_TIMING_12CH;
+	UINT16 DDR_TIMING_12DH;
+	UINT16 DDR_TIMING_12EH;
+	UINT16 DDR_TIMING_12FH;
+
+	UINT16 DDR_CHAN_3_VALID;
+	UINT16 DDR_TIMING_140H;
+	UINT16 DDR_TIMING_141H;
+	UINT16 DDR_TIMING_142H;
+	UINT16 DDR_TIMING_143H;
+	UINT16 DDR_TIMING_144H;
+	UINT16 DDR_TIMING_145H;
+	UINT16 DDR_TIMING_146H;
+	UINT16 DDR_TIMING_147H;
+	UINT16 DDR_TIMING_148H;
+	UINT16 DDR_TIMING_149H;
+	UINT16 DDR_TIMING_14AH;
+	UINT16 DDR_TIMING_14BH;
+	UINT16 DDR_TIMING_14CH;
+	UINT16 DDR_TIMING_14DH;
+	UINT16 DDR_TIMING_14EH;
+	UINT16 DDR_TIMING_14FH;
+
+	UINT16 DDR_CHAN_4_VALID;
+	UINT16 DDR_TIMING_160H;
+	UINT16 DDR_TIMING_161H;
+	UINT16 DDR_TIMING_162H;
+	UINT16 DDR_TIMING_163H;
+	UINT16 DDR_TIMING_164H;
+	UINT16 DDR_TIMING_165H;
+	UINT16 DDR_TIMING_166H;
+	UINT16 DDR_TIMING_167H;
+	UINT16 DDR_TIMING_168H;
+	UINT16 DDR_TIMING_169H;
+	UINT16 DDR_TIMING_16AH;
+	UINT16 DDR_TIMING_16BH;
+	UINT16 DDR_TIMING_16CH;
+	UINT16 DDR_TIMING_16DH;
+	UINT16 DDR_TIMING_16EH;
+	UINT16 DDR_TIMING_16FH;
+
+	UINT16 DDR_TIMING_180H;
+	UINT16 DDR_TIMING_181H;
+	UINT16 DDR_TIMING_182H;
+	UINT16 DDR_TIMING_183H;
+	UINT16 DDR_TIMING_184H;
+	UINT16 DDR_TIMING_185H;
+	UINT16 DDR_TIMING_186H;
+	UINT16 DDR_TIMING_187H;
+	UINT16 DDR_TIMING_188H;
+	UINT16 DDR_TIMING_189H;
+	UINT16 DDR_TIMING_18AH;
+	UINT16 DDR_TIMING_18BH;
+	UINT16 DDR_TIMING_18CH;
+	UINT16 DDR_TIMING_069H;
+};
+
+const struct clock_config *get_default_clock_config(void);
+
+#endif
diff --git a/board/rda/rda8810e/config.mk b/board/rda/rda8810e/config.mk
new file mode 100644
index 0000000000..ec124aff34
--- /dev/null
+++ b/board/rda/rda8810e/config.mk
@@ -0,0 +1,11 @@
+#
+#the spl code should not exceed the SPL_MAX_SIZE,and if 
+#the spl don't up to the max size, paddint the last with
+#zero(or 0xff?)
+
+#48kbytes, 48*1024
+#SPL_APPENDING_TO	:= 48
+#SPL_MAX_SIZE	:= 49512
+
+# space for spl(48KiB) & mtd partition table(24KiB)
+SPL_APPENDING_TO   := 72
diff --git a/board/rda/rda8810e/ddr3.c b/board/rda/rda8810e/ddr3.c
new file mode 100644
index 0000000000..13af197db1
--- /dev/null
+++ b/board/rda/rda8810e/ddr3.c
@@ -0,0 +1,533 @@
+#include <common.h>
+#include <asm/arch/rda_iomap.h>
+
+#include "ddr3.h"
+#include "ddr3_init.h"
+#include "tgt_ap_clock_config.h"
+
+#pragma GCC push_options
+#pragma GCC optimize ("O0")
+
+#define DDR_TYPE _TGT_AP_DDR_TYPE
+
+#define DF_DELAY  (0x10000)
+
+#define DMC_REG_BASE RDA_DMC400_BASE
+#define PHY_REG_BASE RDA_DDRPHY_BASE
+
+#define  PHY_RDLAT          0
+#define  PHYWRDATA          1
+#define  STA                3
+#define  CLKSEL             4
+#define  PSSTART            5
+#define  PSDONE             6
+#define  LOCKED             6
+#define  CTRL_DELAY         7
+#define  RDELAY_SEL         8
+#define  WDELAY_SEL         9
+#define  PHY_RESET          10
+#define  RESET_DDR3         11
+#define  ODT_DELAY          12
+#define  DDR3_USED          13
+#define  WRITE_ENABLE_LAT   14
+#define  WRITE_DATA_LAT     15
+#define  DQOUT_ENABLE_LAT   16
+#define  DATA_ODT_ENABLE_REG	20
+#define  DATA_WRITE_ENABLE_REG  48   
+#define  DMC_READY	128
+#define  USE_ADDR   129
+
+#define ARRAY_NUM(n) (sizeof(n))/(sizeof(n[0]))
+
+#if (DDR_TYPE == 1)
+static dmc_reg_t dmc_reg_cfg[] = {
+	{T_REFI,	0x186,		0x186},
+	{T_RFC,		0x230024,	0x230024},
+	{T_RFC,		0x540024,	0x540024},
+	{T_MRR,		0x2,		0x2},
+	{T_MRW,		0x5,		0x5},
+	{T_RCD,		0x8,		0x8},
+	{T_RAS,		0x11,		0x11},
+	{T_RP,		0x8,		0x8},
+	{T_RPALL,	0x9,		0x9},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0x4,		0x4},
+	{T_RTW,		0xb,		0xb},
+	{T_RTP,		0x6,		0x6},
+	{T_WR,		0xe,		0xe},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTW,		0x40000,	0x40000},
+	{RD_LATENCY,	0x6,		0x6},
+	{WR_LATENCY,	0x3,		0x3},
+	{T_RDDATA_EN,	0x3,		0x3},
+	{T_PHYWRLAT,	0x101,		0x101},
+	{T_PHYWRLAT,	0x101,		0x101},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0x80003,	0x80003},
+	{T_ESR,		0x6,		0x6},
+	{T_XSR,		0x1000058,	0x1000058},
+	{T_XSR,		0x580058,	0x580058},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{T_EP,		0x5,		0x5},
+	{RDLVL_CTRL,	0x1010,		0x1010},
+	{RDLVL_CTRL,	0x1110,		0x1110},
+	{RDLVL_CTRL,	0x11110,	0x11110},
+	{REFRESH_CTRL,	0x0,		0x0},
+	{REFRESH_CTRL,	0x0,		0x0},
+	{ECC_CTRL,	0x0,		0x0},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+};
+#elif (DDR_TYPE == 2)
+static dmc_reg_t dmc_reg_cfg[] = {
+	{T_REFI,	0x3f,		0x3f},
+	{T_RFC,		0x230024,	0x230024},
+	{T_RFC,		0x540024,	0x540024},
+	{T_MRR,		0x3f,		0x3f},
+	{T_MRW,		0x3f,		0x3f},
+	{T_RCD,		0x8,		0x8},
+	{T_RAS,		0x11,		0x11},
+	{T_RP,		0x8,		0x8},
+	{T_RPALL,	0x9,		0x9},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0xf,		0xf},
+	{T_RTW,		0x1f,		0x1f},
+	{T_RTP,		0x6,		0x6},
+	{T_WR,		0xe,		0xe},
+	{T_WTR,		0x4001f,	0x4001f},
+	{T_WTR,		0x4001f,	0x4001f},
+	{T_WTW,		0x40000,	0x40000},
+	{RD_LATENCY,	0x8,		0x8},
+	{WR_LATENCY,	0x4,		0x4},
+	{T_RDDATA_EN,	0x8,		0x8},
+	{T_PHYWRLAT,	0x103,		0x103},
+	{T_PHYWRLAT,	0x103,		0x103},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0x80003,	0x80003},
+	{T_ESR,		0x6,		0x6},
+	{T_XSR,		0x1000058,	0x1000058},
+	{T_XSR,		0x580058,	0x580058},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{T_EP,		0x5,		0x5},
+	{RDLVL_CTRL,	0x1010,		0x1010},
+	{RDLVL_CTRL,	0x1110,		0x1110},
+	{RDLVL_CTRL,	0x11110,	0x11110},
+	{REFRESH_CTRL,	0x1,		0x1},
+	{ECC_CTRL,	0x0,		0x0},
+	{QOSX_CTRL7,	0x0f, 		0x0f},
+	{TURNAROUND_PRIO,0x1A, 		0x1A},
+	{HIT_PRIO,	0x1A, 		0x1A},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+};
+#elif (DDR_TYPE == 3)
+static dmc_reg_t dmc_reg_cfg[] = {
+	{QOSX_CTRL7,	0x08, 		0x08},
+	{TURNAROUND_PRIO,0x1A, 		0x0},
+	{HIT_PRIO,	0x1A, 		0x0},
+	{T_REFI,	0x186,		0x3f},
+	{QUEUE_CTRL,	0xffff,		0x0},
+	{T_RFC,		0x23008c,	0x23008c},
+	{T_RFC,		0x8c008c,	0x8c008c},
+	{T_MRR,		0x4,		0x4},
+	{T_MRW,		0xc,		0xc},
+	{T_RCD,		0x6,		0x6},
+	{T_RAS,		0xf,		0xf},
+	{T_RP,		0x6,		0x6},
+	{T_RPALL,	0x6,		0x5},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0x6,		0x6},
+//	{T_RTW,		0x7,		0x6},
+	{T_RTW,		0x0c,		0x6},// turn for now
+//	{T_RTW,		0x1f,		0x1f},//for low speed
+	{T_RTP,		0x4,		0x4},
+	{T_WR,		0xf,		0x10},
+	{T_WTR,		0x4000d,	0x4000d},
+	{T_WTR,		0x6000d,	0x6000f},
+//	{T_WTR,		0x6001f,	0x6001f},//for low speed
+	{T_WTW,		0x60000,	0x60000},
+	{RD_LATENCY,	0x5,		0x5},
+	{WR_LATENCY,	0x5,		0x5},
+	{T_RDDATA_EN,	0x8,		0x2},
+	{T_PHYWRLAT,	0x104,		0x105},
+	{T_PHYWRLAT,	0x104,		0x105},
+	{T_EP,		0x3,		0x3},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0xa0003,	0xa0003},
+	{T_ESR,		0x4,		0x4},
+	{T_XSR,		0x1000090,	0x1000090},
+	{T_XSR,		0x2000090,	0x2000090},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{ECC_CTRL,	0x0,		0x0},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+};
+#else
+#error "Wrong DDR Type"
+#endif
+
+void config_ddr_phy(UINT16 flag)
+{
+	int wait_idle;
+	UINT16 __attribute__((unused)) dll_off;
+
+	wait_idle = DF_DELAY + 16;
+	dll_off = flag & DDR_FLAGS_DLLOFF;
+
+	while (wait_idle--);
+
+#if (DDR_TYPE == 1)
+	*((volatile UINT32*)(PHY_REG_BASE + CTRL_DELAY * 4)) = 1;
+	printf("ddr1 phy init done!\n");
+#elif (DDR_TYPE ==2)
+	*((volatile UINT32*)(PHY_REG_BASE + USE_ADDR * 4)) = 0;
+	*((volatile UINT32*)(PHY_REG_BASE + DATA_WRITE_ENABLE_REG *4))  = 0xf;
+	*((volatile UINT32*)(PHY_REG_BASE + DATA_ODT_ENABLE_REG *4))  = 0xf;
+	*((volatile UINT32*)(PHY_REG_BASE + WRITE_DATA_LAT *4))  = 0x0;
+	*((volatile UINT32*)(PHY_REG_BASE + WRITE_ENABLE_LAT *4))  = 0x0;
+	*((volatile UINT32*)(PHY_REG_BASE + WDELAY_SEL *4))  = 0x7;
+	*((volatile UINT32*)(PHY_REG_BASE + RDELAY_SEL *4))  = 0x6;
+	*((volatile UINT32*)(PHY_REG_BASE + DQOUT_ENABLE_LAT *4))  = 0x1;
+	printf("ddr2 phy init done!\n");
+#else
+	*((volatile UINT32*)(PHY_REG_BASE + 128 *4))  = 0x0;
+	*((volatile UINT32*)(PHY_REG_BASE + RESET_DDR3 * 4)) = 1;
+
+	if (dll_off)
+		*((volatile UINT32*)(PHY_REG_BASE + WRITE_DATA_LAT * 4)) = 1;
+
+	*((volatile UINT32*)(PHY_REG_BASE + DDR3_USED * 4)) = 1;
+	*((volatile UINT32*)(PHY_REG_BASE + WDELAY_SEL * 4)) = 3;
+
+	if (!dll_off){
+		*((volatile UINT32*)(PHY_REG_BASE + PHY_RDLAT * 4)) = 7;
+		*((volatile UINT32*)(PHY_REG_BASE + CTRL_DELAY * 4)) =2;
+		*((volatile UINT32*)(PHY_REG_BASE + WRITE_ENABLE_LAT * 4)) =2;
+		*((volatile UINT32*)(PHY_REG_BASE + WRITE_DATA_LAT * 4)) = 3;
+		*((volatile UINT32*)(PHY_REG_BASE + DQOUT_ENABLE_LAT * 4)) = 3;
+	}else
+		*((volatile UINT32*)(PHY_REG_BASE + DQOUT_ENABLE_LAT * 4)) = 1;
+
+	*((volatile UINT32*)(PHY_REG_BASE + DATA_ODT_ENABLE_REG *4))  = 0xf;
+	*((volatile UINT32*)(PHY_REG_BASE + DATA_WRITE_ENABLE_REG *4))  = 0xf;
+	
+	serial_puts("ddr3 phy init done!\n");
+#endif
+}
+
+void config_dmc400(UINT16 flag, UINT32 para)
+{
+	int i, wait_idle;
+	UINT32 val, tmp;
+	volatile UINT32 *addr;
+	UINT16 __attribute__((unused)) dll_off, lpw, odt, ron;
+	UINT32 mem_width, col_bits, row_bits, bank_bits;
+
+	dll_off = flag & DDR_FLAGS_DLLOFF;
+	lpw = flag & DDR_FLAGS_LOWPWR;
+	odt = (flag & DDR_FLAGS_ODT_MASK) >> DDR_FLAGS_ODT_SHIFT;
+	ron = (flag & DDR_FLAGS_RON_MASK) >> DDR_FLAGS_RON_SHIFT;
+	mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;
+	bank_bits = (para & DDR_PARA_BANK_BITS_MASK) >> DDR_PARA_BANK_BITS_SHIFT;
+	row_bits = (para & DDR_PARA_ROW_BITS_MASK) >> DDR_PARA_ROW_BITS_SHIFT;
+	col_bits = (para & DDR_PARA_COL_BITS_MASK) >> DDR_PARA_COL_BITS_SHIFT;
+
+
+	wait_idle = 0x4e;
+	while (wait_idle--);
+
+	for (i=0; i<ARRAY_NUM(dmc_reg_cfg); i++) {
+		addr = (volatile UINT32*)(DMC_REG_BASE + dmc_reg_cfg[i].reg_offset);
+		if (dll_off)
+			val = dmc_reg_cfg[i].dll_off_val;
+		else
+			val = dmc_reg_cfg[i].dll_on_val;
+
+		*addr = val;
+		wait_idle = 0x5;
+		while (wait_idle--);
+	}
+
+#if (DDR_TYPE == 3)
+	//config low power control register
+	if (lpw) {
+		addr = (volatile UINT32*)(DMC_REG_BASE + LOWPWR_CTRL);//0x20
+		*addr = 0x48;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_ESR);//0x260
+		*addr = 0xa;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_XSR);//0x264
+		*addr = 0x200;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_SRCKD);//0x268
+		*addr = 0xa;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_CKSRD);//0x26C
+		*addr = 0xa;
+		wait_idle = 0x5;
+		while (wait_idle--);	
+	}
+#elif (DDR_TYPE == 2)
+	addr = (volatile UINT32*)(DMC_REG_BASE + LOWPWR_CTRL);//0x20
+	*addr = 0x38;
+	wait_idle = 0x5;
+	while (wait_idle--);
+#endif
+
+	//config format control register
+	addr = (volatile UINT32*)(DMC_REG_BASE + FORMAT_CTRL);
+	val = *addr;
+	val &= ~0xf;
+	if (mem_width == 2)
+		val |= 0x2; //for 32bit DDR
+	else if ((mem_width == 1) || (mem_width == 0))
+		val |= 0x1; //for 16bit & 8bit DDR
+	else
+		printf("unsupported DDR width: %lx\n", mem_width);
+	*addr = val;
+
+	printf("format ctrl value: %lx\n", val);
+
+	wait_idle = 0x1d;
+	while (wait_idle--);
+
+	//config address control register
+	addr = (volatile UINT32*)(DMC_REG_BASE + ADDR_CTRL);
+	if (mem_width == 2)
+		tmp = col_bits; //for 32bit
+	else if (mem_width == 1)
+		tmp = col_bits - 1; //for 16bit
+	else if (mem_width == 0)
+		tmp = col_bits - 2; //for 8bit
+	else {
+		printf("unsupported DDR width: %lx\n", mem_width);
+		tmp = col_bits;
+	}
+	val = (bank_bits << 16) | (row_bits << 8) | tmp;
+
+	*addr = val;
+
+	printf("address ctrl value: %lx\n", val);
+	wait_idle = 0x5;
+	while (wait_idle--);
+
+	//config decode control register
+	addr = (volatile UINT32*)(DMC_REG_BASE + DECODE_CTRL);
+	tmp = 12 - (8 + col_bits + mem_width);
+	if (tmp < 8)
+		val = tmp << 4;
+	else
+		printf("unsupported stripe decode: %lx\n", tmp);
+	*addr = val;
+
+	printf("decode ctrl value: %lx\n", val);
+	wait_idle = 0x6;
+	while (wait_idle--);
+
+	wait_idle = DF_DELAY;
+	while (wait_idle--);
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+	*addr = 0x0;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0;
+#elif (DDR_TYPE == 2)
+	val = 0;
+#else
+	//config MR2
+	if (dll_off)
+		val = 0x10020008;
+	else
+		val = 0x10020000;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x20000000;
+#elif (DDR_TYPE == 2)
+	val = 0x1000003f;
+#else
+	//config MR3
+	val = 0x10030000;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x30000000;
+#elif (DDR_TYPE == 2)
+	val = 0x1000ff0a;
+#else
+	//config MR1 ODT [9,6,2] RON [5,1] DLLOFF [0]
+	val = 0x10010000;
+	val |= (odt & 0x4)<<7 | (odt & 0x2)<<5 | (odt & 0x1)<<2;
+	val |= (ron & 0x2)<<4 | (ron & 0x1)<<1;
+	if (dll_off)
+		val |= 0x1;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x30000000;
+#elif (DDR_TYPE == 2)
+	val = 0x10008301;
+#else
+	//config MR0
+	val = 0x10000520;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x10000033;
+#elif (DDR_TYPE == 2)
+	val = 0x10000602;//0ld 0x10000102
+#else
+	val = 0x50000400;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+#if (DDR_TYPE == 2)
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+	val = 0x10000103;//0ld 0x10000102
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+#endif
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x10020000;
+#elif (DDR_TYPE == 2)
+	val = 0x30000000;
+#else
+	val = 0x30000000;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+#if (DDR_TYPE == 2)
+/* zhangli for MCP */
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+	*addr = 0x10000103;
+	wait_idle = DF_DELAY + 0x9;
+	while (wait_idle--);
+#endif
+
+#if (DDR_TYPE == 2)
+	addr = (volatile UINT32*)(DMC_REG_BASE + MEMC_CMD);
+	val = 0x4;
+	*addr = val;
+#endif
+
+	//config ECC control
+	wait_idle = 0x6;
+	while (wait_idle--);
+	addr = (volatile UINT32*)(DMC_REG_BASE + ECC_CTRL);
+	val = 0x0;
+	*addr = val;
+	wait_idle = 0x8;
+	while (wait_idle--);
+
+	//config MEMC CMD
+	addr = (volatile UINT32*)(DMC_REG_BASE + MEMC_CMD);
+	val = 0x3;
+	*addr = val;
+
+	//READ MEMC STATUS
+	addr = (volatile UINT32*)(DMC_REG_BASE + MEMC_STATUS);
+	val = 0;
+	do {
+		val = *addr;
+		//printf("MEMC_STATUS value: %x\n", val);
+	} while (val != 3);
+}
+
+void axi_prio_init(void)
+{
+	*(volatile UINT32*)(0x20900100) = 0xaa0000aa;
+	*(volatile UINT32*)(0x21054100) = 0x00000008;
+	*(volatile UINT32*)(0x21054104) = 0x00000008;
+}
+
+void axi_outstandings_init(void)
+{
+	*(volatile UINT32*)(0x2104210C) = 0x00000060;
+	*(volatile UINT32*)(0x21042110) = 0x00000300;
+}
+
+int ddr_init(UINT16 flags, UINT32 para)
+{
+	UINT16 dll_off;
+	UINT32 mem_width;
+
+	//axi_prio_init();
+	axi_outstandings_init();
+
+	dll_off = flags & DDR_FLAGS_DLLOFF;
+	mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;
+
+	switch (mem_width) {
+		case 0:
+			printf("8bit ");
+			break;
+		case 1:
+			printf("16bit ");
+			break;
+		case 2:
+			printf("32bit ");
+			break;
+	}
+	if (dll_off)
+		printf("dll-off Mode ...\n");
+	else
+		printf("dll-on Mode ...\n");
+
+	config_ddr_phy(flags);
+	config_dmc400(flags, para);
+	printf("dram init done ...\n");
+
+	return 0;
+}
+
diff --git a/board/rda/rda8810e/ddr3.h b/board/rda/rda8810e/ddr3.h
new file mode 100644
index 0000000000..7481954144
--- /dev/null
+++ b/board/rda/rda8810e/ddr3.h
@@ -0,0 +1,50 @@
+#ifndef _SYS_DDR3_H_
+#define _SYS_DDR3_H_
+
+#include "clock_config.h"
+
+/*
+ * defination of ddr flags
+ */
+/* [Debug] DLL off mode, 0 is dll on mode */
+#define DDR_FLAGS_DLLOFF               0x8000
+/* [Debug] LowSpeed mode*/
+#define DDR_FLAGS_RESERVE              0x4000
+/* DDR LowPower mode */
+#define DDR_FLAGS_LOWPWR               0x2000
+/* ODT: 000--Null 001--60 010--120 011--40 100--20 101--30 */
+#define DDR_FLAGS_ODT(n)               (((n)<<0)&0x0007)
+#define DDR_FLAGS_ODT_SHIFT            0
+#define DDR_FLAGS_ODT_MASK             0x0007
+/* RON: 00--40 01--30 */
+#define DDR_FLAGS_RON(n)               (((n)<<3)&0x0018)
+#define DDR_FLAGS_RON_SHIFT            3
+#define DDR_FLAGS_RON_MASK             0x0018
+
+/*
+ * defination of ddr parameters
+ */
+#define DDR_PARA_CHIP_BITS(n)          (((n)<<0)&0x00000003)
+#define DDR_PARA_CHIP_BITS_SHIFT       0
+#define DDR_PARA_CHIP_BITS_MASK        0x00000003
+/* memory width 0--8bit 1--16bit 2--32bit */
+#define DDR_PARA_MEM_BITS(n)           (((n)<<2)&0x0000000c)
+#define DDR_PARA_MEM_BITS_SHIFT        2
+#define DDR_PARA_MEM_BITS_MASK         0x0000000c
+/* 2--4banks 3--8banks */
+#define DDR_PARA_BANK_BITS(n)          (((n)<<4)&0x000000f0)
+#define DDR_PARA_BANK_BITS_SHIFT       4
+#define DDR_PARA_BANK_BITS_MASK        0x000000f0
+/* 2--13rbs 3--14rbs 4--15rbs 5--16rbs */
+#define DDR_PARA_ROW_BITS(n)           (((n)<<8)&0x00000f00)
+#define DDR_PARA_ROW_BITS_SHIFT        8
+#define DDR_PARA_ROW_BITS_MASK         0x00000f00
+/* 0--8cbs 1--9cbs 2--10cbs 3--11cbs 4--12cbs */
+#define DDR_PARA_COL_BITS(n)           (((n)<<12)&0x0000f000)
+#define DDR_PARA_COL_BITS_SHIFT        12
+#define DDR_PARA_COL_BITS_MASK         0x0000f000
+
+int ddr_init(UINT16 flags, UINT32 para);
+
+#endif /* _SYS_DDR3_H_ */
+
diff --git a/board/rda/rda8810e/ddr3_8810.c b/board/rda/rda8810e/ddr3_8810.c
new file mode 100644
index 0000000000..b6ccc52375
--- /dev/null
+++ b/board/rda/rda8810e/ddr3_8810.c
@@ -0,0 +1,540 @@
+#include <common.h>
+#include <asm/arch/rda_iomap.h>
+
+#include "ddr3.h"
+#include "ddr3_init.h"
+#include "tgt_ap_clock_config.h"
+
+#pragma GCC push_options
+#pragma GCC optimize ("O0")
+
+#define DDR_TYPE _TGT_AP_DDR_TYPE
+
+#define DF_DELAY  (0x10000)
+
+#define DMC_REG_BASE RDA_DMC400_BASE
+#define PHY_REG_BASE RDA_DDRPHY_BASE
+
+#define  PHY_RDLAT          0
+#define  PHYWRDATA          1
+#define  STA                3
+#define  CLKSEL             4
+#define  PSSTART            5
+#define  PSDONE             6
+#define  LOCKED             6
+#define  CTRL_DELAY         7
+#define  RDELAY_SEL         8
+#define  WDELAY_SEL         9
+#define  PHY_RESET          10
+#define  RESET_DDR3         11
+#define  ODT_DELAY          12
+#define  DDR3_USED          13
+#define  WRITE_ENABLE_LAT   14
+#define  WRITE_DATA_LAT     15
+#define  DQOUT_ENABLE_LAT   16
+
+#define ARRAY_NUM(n) (sizeof(n))/(sizeof(n[0]))
+
+#if (DDR_TYPE == 1)
+static dmc_reg_t dmc_reg_cfg[] = {
+	{T_REFI,	0x186,		0x186},
+	{T_RFC,		0x230024,	0x230024},
+	{T_RFC,		0x540024,	0x540024},
+	{T_MRR,		0x2,		0x2},
+	{T_MRW,		0x5,		0x5},
+	{T_RCD,		0x8,		0x8},
+	{T_RAS,		0x11,		0x11},
+	{T_RP,		0x8,		0x8},
+	{T_RPALL,	0x9,		0x9},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0x4,		0x4},
+	{T_RTW,		0xb,		0xb},
+	{T_RTP,		0x6,		0x6},
+	{T_WR,		0xe,		0xe},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTW,		0x40000,	0x40000},
+	{RD_LATENCY,	0x6,		0x6},
+	{WR_LATENCY,	0x3,		0x3},
+	{T_RDDATA_EN,	0x3,		0x3},
+	{T_PHYWRLAT,	0x101,		0x101},
+	{T_PHYWRLAT,	0x101,		0x101},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0x80003,	0x80003},
+	{T_ESR,		0x6,		0x6},
+	{T_XSR,		0x1000058,	0x1000058},
+	{T_XSR,		0x580058,	0x580058},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{T_EP,		0x5,		0x5},
+	{RDLVL_CTRL,	0x1010,		0x1010},
+	{RDLVL_CTRL,	0x1110,		0x1110},
+	{RDLVL_CTRL,	0x11110,	0x11110},
+	{REFRESH_CTRL,	0x0,		0x0},
+	{REFRESH_CTRL,	0x0,		0x0},
+	{ECC_CTRL,	0x0,		0x0},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+};
+#elif (DDR_TYPE == 2)
+static dmc_reg_t dmc_reg_cfg[] = {
+	{T_REFI,	0x3f,		0x3f},
+	{T_RFC,		0x230024,	0x230024},
+	{T_RFC,		0x540024,	0x540024},
+	{T_MRR,		0x2,		0x2},
+	{T_MRW,		0x5,		0x5},
+	{T_RCD,		0x8,		0x8},
+	{T_RAS,		0x11,		0x11},
+	{T_RP,		0x8,		0x8},
+	{T_RPALL,	0x9,		0x9},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0x4,		0x4},
+	{T_RTW,		0xb,		0xb},
+	{T_RTP,		0x6,		0x6},
+	{T_WR,		0xe,		0xe},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTW,		0x40000,	0x40000},
+	{RD_LATENCY,	0x6,		0x6},
+	{WR_LATENCY,	0x3,		0x3},
+	{T_RDDATA_EN,	0x3,		0x3},
+	{T_PHYWRLAT,	0x101,		0x101},
+	{T_PHYWRLAT,	0x103,		0x103},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0x80003,	0x80003},
+	{T_ESR,		0x6,		0x6},
+	{T_XSR,		0x1000058,	0x1000058},
+	{T_XSR,		0x580058,	0x580058},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{T_EP,		0x5,		0x5},
+	{RDLVL_CTRL,	0x1010,		0x1010},
+	{RDLVL_CTRL,	0x1110,		0x1110},
+	{RDLVL_CTRL,	0x11110,	0x11110},
+	{REFRESH_CTRL,	0x1,		0x1},
+	{ECC_CTRL,	0x0,		0x0},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+};
+#elif (DDR_TYPE == 3)
+static dmc_reg_t dmc_reg_cfg[] = {
+	{T_REFI,	0x186,		0x3f},
+	{T_RFC,		0x23008c,	0x23008c},
+	{T_RFC,		0x8c008c,	0x8c008c},
+	{T_MRR,		0x4,		0x4},
+	{T_MRW,		0xc,		0xc},
+	{T_RCD,		0x6,		0x5},
+	{T_RAS,		0xf,		0xf},
+	{T_RP,		0x6,		0x5},
+	{T_RPALL,	0x6,		0x5},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0x6,		0x6},
+//	{T_RTW,		0x7,		0x6},
+	{T_RTW,		0x0e,		0x0c},// turn for now
+//	{T_RTW,		0x1f,		0x1f},//for low speed
+	{T_RTP,		0x4,		0x4},
+	{T_WR,		0xf,		0x10},
+	{T_WTR,		0x4000d,	0x4000d},
+	{T_WTR,		0x6000d,	0x6000f},
+//	{T_WTR,		0x6001f,	0x6001f},//for low speed
+	{T_WTW,		0x60000,	0x60000},
+	{RD_LATENCY,	0x5,		0x5},
+	{WR_LATENCY,	0x5,		0x5},
+	{T_RDDATA_EN,	0x8,		0x1},
+	{T_PHYWRLAT,	0x103,		0x103},
+	{T_PHYWRLAT,	0x103,		0x104},
+	{T_EP,		0x3,		0x3},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0xa0003,	0xa0003},
+	{T_ESR,		0x4,		0x4},
+	{T_XSR,		0x1000090,	0x1000090},
+	{T_XSR,		0x2000090,	0x2000090},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{ECC_CTRL,	0x0,		0x0},
+	{QOSX_CTRL7,	0x0f, 		0x0f},
+	{TURNAROUND_PRIO,0x1A, 		0x1A},
+	{HIT_PRIO,	0x1A, 		0x1A},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+};
+#else
+#error "Wrong DDR Type"
+#endif
+
+void config_ddr_phy(UINT16 flag)
+{
+	int wait_idle;
+	UINT16 dll_off;
+
+	wait_idle = DF_DELAY + 16;
+	dll_off = flag & DDR_FLAGS_DLLOFF;
+
+	while (wait_idle--);
+
+#if (DDR_TYPE == 1)
+	*((volatile UINT32*)(PHY_REG_BASE + CTRL_DELAY * 4)) = 1;
+	printf("ddr1 phy init done!\n");
+#elif (DDR_TYPE ==2)
+	*((volatile UINT32*)(PHY_REG_BASE + 129 * 4)) = 0;
+	*((volatile UINT32*)(PHY_REG_BASE + WDELAY_SEL * 4)) = 3;
+	*((volatile UINT32*)(PHY_REG_BASE + DQOUT_ENABLE_LAT * 4)) = 1;
+	*((volatile UINT32*)(PHY_REG_BASE + 48 *4))  = 0xf;
+	*((volatile UINT32*)(PHY_REG_BASE + 20 *4))  = 0xf;
+	printf("ddr2 phy init done!\n");
+#else
+	*((volatile UINT32*)(PHY_REG_BASE + RESET_DDR3 * 4)) = 1;
+	*((volatile UINT32*)(PHY_REG_BASE + WRITE_DATA_LAT * 4)) = 1;
+	*((volatile UINT32*)(PHY_REG_BASE + DDR3_USED * 4)) = 1;
+	if (!dll_off)
+	*((volatile UINT32*)(PHY_REG_BASE + RDELAY_SEL * 4)) = 2;
+	*((volatile UINT32*)(PHY_REG_BASE + WDELAY_SEL * 4)) = 3;
+	*((volatile UINT32*)(PHY_REG_BASE + DQOUT_ENABLE_LAT * 4)) = 1;
+	*((volatile UINT32*)(PHY_REG_BASE + 48 *4))  = (3<<2);
+	*((volatile UINT32*)(PHY_REG_BASE + 20 *4))  = (3<<2);
+	printf("ddr3 phy init done!\n");
+#endif
+}
+
+void config_dmc400(UINT16 flag, UINT32 para)
+{
+	int i, wait_idle;
+	UINT32 val, tmp;
+	volatile UINT32 *addr;
+	UINT16 dll_off, lpw, odt, ron;
+	UINT32 mem_width, col_bits, row_bits, bank_bits;
+
+	dll_off = flag & DDR_FLAGS_DLLOFF;
+	lpw = flag & DDR_FLAGS_LOWPWR;
+	odt = (flag & DDR_FLAGS_ODT_MASK) >> DDR_FLAGS_ODT_SHIFT;
+	ron = (flag & DDR_FLAGS_RON_MASK) >> DDR_FLAGS_RON_SHIFT;
+	mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;
+	bank_bits = (para & DDR_PARA_BANK_BITS_MASK) >> DDR_PARA_BANK_BITS_SHIFT;
+	row_bits = (para & DDR_PARA_ROW_BITS_MASK) >> DDR_PARA_ROW_BITS_SHIFT;
+	col_bits = (para & DDR_PARA_COL_BITS_MASK) >> DDR_PARA_COL_BITS_SHIFT;
+
+
+	wait_idle = 0x4e;
+	while (wait_idle--);
+
+	for (i=0; i<ARRAY_NUM(dmc_reg_cfg); i++) {
+		addr = (volatile UINT32*)(DMC_REG_BASE + dmc_reg_cfg[i].reg_offset);
+		if (dll_off)
+			val = dmc_reg_cfg[i].dll_off_val;
+		else
+			val = dmc_reg_cfg[i].dll_on_val;
+
+		*addr = val;
+		wait_idle = 0x5;
+		while (wait_idle--);
+	}
+
+#if (DDR_TYPE == 3)
+	//config low power control register
+	if (lpw) {
+		addr = (volatile UINT32*)(DMC_REG_BASE + LOWPWR_CTRL);//0x20
+		*addr = 0x48;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_ESR);//0x260
+		*addr = 0xa;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_XSR);//0x264
+		*addr = 0x200;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_SRCKD);//0x268
+		*addr = 0xa;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_CKSRD);//0x26C
+		*addr = 0xa;
+		wait_idle = 0x5;
+		while (wait_idle--);	
+	}
+#elif (DDR_TYPE == 2)
+	addr = (volatile UINT32*)(DMC_REG_BASE + LOWPWR_CTRL);//0x20
+	*addr = 0x38;
+	wait_idle = 0x5;
+	while (wait_idle--);
+#endif
+
+	//config format control register
+	addr = (volatile UINT32*)(DMC_REG_BASE + FORMAT_CTRL);
+#if (DDR_TYPE == 1)
+	val = 0x22000202;
+#elif (DDR_TYPE == 2)
+	val = 0x22000202;
+#else
+	val = *addr;
+	val &= ~0xf;
+	if (mem_width == 2)
+		val |= 0x2; //for 32bit DDR
+	else if ((mem_width == 1) || (mem_width == 0))
+		val |= 0x1; //for 16bit & 8bit DDR
+	else
+		printf("unsupported DDR width: %lx\n", mem_width);
+#endif
+	*addr = val;
+
+	printf("format ctrl value: %lx\n", val);
+
+	wait_idle = 0x1d;
+	while (wait_idle--);
+
+	//config address control register
+	addr = (volatile UINT32*)(DMC_REG_BASE + ADDR_CTRL);
+#if (DDR_TYPE == 1)
+	val = 0x20302;
+#elif (DDR_TYPE == 2)
+	val = 0x30200;
+#else
+	if (mem_width == 2)
+		tmp = col_bits; //for 32bit
+	else if (mem_width == 1)
+		tmp = col_bits - 1; //for 16bit
+	else if (mem_width == 0)
+		tmp = col_bits - 2; //for 8bit
+	else {
+		printf("unsupported DDR width: %lx\n", mem_width);
+		tmp = col_bits;
+	}
+
+	val = (bank_bits << 16) | (row_bits << 8) | tmp;
+#endif
+	*addr = val;
+
+	printf("address ctrl value: %lx\n", val);
+	wait_idle = 0x5;
+	while (wait_idle--);
+
+#if (DDR_TYPE == 2)
+	addr = (volatile UINT32*)(DMC_REG_BASE + ADDR_CTRL);
+
+	val = 0x30301;
+
+	*addr = val;
+
+	printf("address ctrl 2 value: %lx\n", val);
+	wait_idle = 0x5;
+	while (wait_idle--);
+#endif
+
+	//config decode control register
+	addr = (volatile UINT32*)(DMC_REG_BASE + DECODE_CTRL);
+#if (DDR_TYPE == 1)
+	val = 0x00;
+#elif (DDR_TYPE == 2)
+	val = 0x50;
+#else
+	tmp = 12 - (8 + col_bits + mem_width);
+	if (tmp < 8)
+		val = tmp << 4;
+	else
+		printf("unsupported stripe decode: %lx\n", tmp);
+#endif
+	*addr = val;
+	wait_idle = 0x6;
+	while (wait_idle--);
+
+#if (DDR_TYPE == 2)
+	addr = (volatile UINT32*)(DMC_REG_BASE + DECODE_CTRL);
+	val = 0x10;
+	*addr = val;
+	wait_idle = 0x6;
+	while (wait_idle--);
+#endif	
+
+	wait_idle = DF_DELAY;
+	while (wait_idle--);
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+	*addr = 0x0;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0;
+#elif (DDR_TYPE == 2)
+	val = 0;
+#else
+	//config MR2
+	if (dll_off)
+		val = 0x10020008;
+	else
+		val = 0x10020000;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x6;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x20000000;
+#elif (DDR_TYPE == 2)
+	val = 0x1000003f;
+#else
+	//config MR3
+	val = 0x10030000;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x30000000;
+#elif (DDR_TYPE == 2)
+	val = 0x1000ff0a;
+#else
+	//config MR1 ODT [9,6,2] RON [5,1] DLLOFF [0]
+	val = 0x10010000;
+	val |= (odt & 0x4)<<7 | (odt & 0x2)<<5 | (odt & 0x1)<<2;
+	val |= (ron & 0x2)<<4 | (ron & 0x1)<<1;
+	if (dll_off)
+		val |= 0x1;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x30000000;
+#elif (DDR_TYPE == 2)
+	val = 0x10008301;
+#else
+	//config MR0
+	val = 0x10000520;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x6;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x10000033;
+#elif (DDR_TYPE == 2)
+	val = 0x10000402;//0ld 0x10000102
+#else
+	val = 0x50000400;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x6;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x10020000;
+#elif (DDR_TYPE == 2)
+	val = 0x30000000;
+#else
+	val = 0x30000000;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x9;
+	while (wait_idle--);
+
+#if (DDR_TYPE == 2)
+/* zhangli for MCP */
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+	*addr = 0x10000103;
+	wait_idle = DF_DELAY + 0x9;
+	while (wait_idle--);
+#endif
+
+#if (DDR_TYPE == 2)
+	addr = (volatile UINT32*)(DMC_REG_BASE + MEMC_CMD);
+	val = 0x4;
+	*addr = val;
+	wait_idle = 0x5;
+	while (wait_idle--);
+#endif
+
+	//config ECC control
+	addr = (volatile UINT32*)(DMC_REG_BASE + ECC_CTRL);
+	val = 0x0;
+	*addr = val;
+	wait_idle = 0x4f;
+	while (wait_idle--);
+
+	//config MEMC CMD
+	addr = (volatile UINT32*)(DMC_REG_BASE + MEMC_CMD);
+	val = 0x3;
+	*addr = val;
+	wait_idle = 0x8;
+	while (wait_idle--);
+
+	//READ MEMC STATUS
+	addr = (volatile UINT32*)(DMC_REG_BASE + MEMC_STATUS);
+	val = 0;
+	do {
+		val = *addr;
+		//printf("MEMC_STATUS value: %x\n", val);
+	} while (val != 3);
+}
+
+void axi_prio_init(void)
+{
+	*(volatile UINT32*)(0x20900100) = 0xaa0000aa;
+	*(volatile UINT32*)(0x21054100) = 0x00000008;
+	*(volatile UINT32*)(0x21054104) = 0x00000008;
+}
+
+void axi_outstandings_init(void)
+{
+	*(volatile UINT32*)(0x2104210C) = 0x00000060;
+	*(volatile UINT32*)(0x21042110) = 0x00000300;
+}
+
+int ddr_init(UINT16 flags, UINT32 para)
+{
+	UINT16 dll_off;
+	UINT32 mem_width;
+
+	//axi_prio_init();
+	axi_outstandings_init();
+
+	dll_off = flags & DDR_FLAGS_DLLOFF;
+	mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;
+
+	switch (mem_width) {
+		case 0:
+			printf("8bit ");
+			break;
+		case 1:
+			printf("16bit ");
+			break;
+		case 2:
+			printf("32bit ");
+			break;
+	}
+	if (dll_off)
+		printf("dll-off Mode ...\n");
+	else
+		printf("dll-on Mode ...\n");
+
+	config_ddr_phy(flags);
+	config_dmc400(flags, para);
+	printf("dram init done ...\n");
+
+	return 0;
+}
+
diff --git a/board/rda/rda8810e/ddr3_8810e_16bit.c b/board/rda/rda8810e/ddr3_8810e_16bit.c
new file mode 100644
index 0000000000..2469e0c75e
--- /dev/null
+++ b/board/rda/rda8810e/ddr3_8810e_16bit.c
@@ -0,0 +1,388 @@
+#include <common.h>

+#include <asm/arch/rda_iomap.h>

+

+#include "ddr3.h"

+#include "tgt_ap_clock_config.h"

+

+#define DDR_TYPE	3

+#define DF_DELAY	(0x100000)

+

+#define DMC_REG_BASE RDA_DMC400_BASE

+#define PHY_REG_BASE RDA_DDRPHY_BASE

+

+#define  PHY_RDLAT		0

+#define  PHYWRDATA		1

+#define  STA			3

+#define  CLKSEL			4

+#define  PSSTART		5

+#define  PSDONE			6

+#define  LOCKED			6

+#define  CTRL_DELAY		7

+#define  RDELAY_SEL		8

+#define  WDELAY_SEL		9

+#define  PHY_RESET		10

+#define  RESET_DDR3		11

+#define  ODT_DELAY		12

+#define  DDR3_USED		13

+#define  WRITE_ENABLE_LAT	14

+#define  WRITE_DATA_LAT		15

+#define  DQOUT_ENABLE_LAT	16

+#define  DMC_READY          128

+

+#define ARRAY_NUM(n) (sizeof(n))/(sizeof(n[0]))

+

+#define DMCREG_BADDR DMC_REG_BASE

+#define PHY_BADDR PHY_REG_BASE

+

+void DDR_CONFIG_DELAY(int delay)

+{

+   int i;

+   i = delay;

+   while(i--);

+}

+//////////////////////////////////////////////////////////////////////

+void config_ddr_phy(UINT16 flag)

+{

+	int cnt;

+    volatile int * addr;

+    cnt = 16;

+    while(cnt--);

+        

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (PHY_BADDR + DMC_READY*4);

+    *addr = 0;    

+    

+    addr = (int *) (PHY_BADDR + RESET_DDR3*4);

+    *addr = 1;

+

+    addr = (int *) (PHY_BADDR + WRITE_DATA_LAT*4);

+    *addr = 1;    

+    

+    addr = (int *) (PHY_BADDR + DDR3_USED*4);

+    *addr = 1;    

+   

+    addr = (int *) (PHY_BADDR + WDELAY_SEL*4);

+    *addr = 3;    

+    

+    addr = (int *) (PHY_BADDR + DQOUT_ENABLE_LAT*4);

+    *addr = 1;

+	serial_puts("ddr3 phy init done!\n");  

+}

+///////////////////////////////////////////////////////////////////

+void config_dmc400(UINT16 flag, UINT32 para)

+{

+	int wait_idle;

+	volatile int * addr;

+ wait_idle = 0x4e;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x200);

+*addr = 0x3f;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x204);

+*addr = 0x23008c;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x204);

+*addr = 0x8c008c;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x208);

+*addr = 0x4;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x20c);

+*addr = 0xc;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x218);

+*addr = 0x6;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x21c);

+*addr = 0xf;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x220);

+*addr = 0x6;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x224);

+*addr = 0x5;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x228);

+*addr = 0x4;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x22c);

+*addr = 0x14;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x234);

+*addr = 0x6;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x238);

+*addr = 0x6;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x23c);

+*addr = 0x4;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x244);

+*addr = 0x10;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x248);

+*addr = 0x4000d;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x248);

+*addr = 0x6000f;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x24c);

+*addr = 0x60000;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x230);

+*addr = 0x5;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x240);

+*addr = 0x5;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x300);

+*addr = 0x2;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x304);

+*addr = 0x105;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x304);

+*addr = 0x105;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x258);

+*addr = 0x3;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x25c);

+*addr = 0x20003;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x25c);

+*addr = 0xa0003;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x260);

+*addr = 0x4;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x264);

+*addr = 0x1000090;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x264);

+*addr = 0x2000090;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x268);

+*addr = 0x5;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x26c);

+*addr = 0x5;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x250);

+*addr = 0x5;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x254);

+*addr = 0x5;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x148);

+*addr = 0x0;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x10);

+*addr = 0x30200;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x10);

+*addr = 0x30200;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x10);

+*addr = 0x30200;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x18);

+*addr = 0x22000201;

+

+ wait_idle = 0x1d;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x10);

+*addr = 0x30200;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x10);

+*addr = 0x30401;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x14);

+*addr = 0x50;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x14);

+*addr = 0x10;

+

+ wait_idle = 0x6;

+ while(wait_idle--);

+DDR_CONFIG_DELAY(DF_DELAY); 

+addr = (int *) (DMCREG_BADDR + 0x108);

+*addr = 0x0;

+

+ wait_idle = 0x10;

+ while(wait_idle--);

+DDR_CONFIG_DELAY(DF_DELAY); 

+addr = (int *) (DMCREG_BADDR + 0x108);

+*addr = 0x10020008;

+

+ wait_idle = 0x10;

+ while(wait_idle--);

+DDR_CONFIG_DELAY(DF_DELAY); 

+addr = (int *) (DMCREG_BADDR + 0x108);

+*addr = 0x10030000;

+

+ wait_idle = 0x10;

+ while(wait_idle--);

+DDR_CONFIG_DELAY(DF_DELAY); 

+addr = (int *) (DMCREG_BADDR + 0x108);

+*addr = 0x10010001;

+

+ wait_idle = 0x10;

+ while(wait_idle--);

+DDR_CONFIG_DELAY(DF_DELAY); 

+addr = (int *) (DMCREG_BADDR + 0x108);

+*addr = 0x10000520;

+

+ wait_idle = 0x10;

+ while(wait_idle--);

+DDR_CONFIG_DELAY(DF_DELAY); 

+addr = (int *) (DMCREG_BADDR + 0x108);

+*addr = 0x50000400;

+

+ wait_idle = 0x10;

+ while(wait_idle--);

+DDR_CONFIG_DELAY(DF_DELAY); 

+addr = (int *) (DMCREG_BADDR + 0x108);

+*addr = 0x30000000;

+

+ wait_idle = 0x6;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x148);

+*addr = 0x0;

+

+ wait_idle = 0x8;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x8);

+*addr = 0x3;

+

+addr = (int * ) (DMCREG_BADDR + 0x0);

+wait_idle = 0;

+while ( wait_idle != 3)

+wait_idle = *addr;

+serial_puts("ddr3 dmc400 init done!\n");

+}

+

+///////////////////////////////////////////////////////////////////

+void axi_prio_init(void)

+{

+	*(volatile UINT32*)(0x20900100) = 0xaa0000aa;

+	*(volatile UINT32*)(0x21054100) = 0x00000008;

+	*(volatile UINT32*)(0x21054104) = 0x00000008;

+}

+

+int ddr_init(UINT16 flags, UINT32 para)

+{

+	UINT16 dll_off;

+	UINT32 mem_width;

+

+	axi_prio_init();

+

+	dll_off = flags & DDR_FLAGS_DLLOFF;

+	mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;

+

+	switch (mem_width) {

+		case 0:

+			serial_puts("8bit ");

+			break;

+		case 1:

+			serial_puts("16bit ");

+			break;

+		case 2:

+			serial_puts("32bit ");

+			break;

+	}

+	if (dll_off)

+		serial_puts("dll-off Mode ...\n");

+	else

+		serial_puts("dll-on Mode ...\n");

+

+	config_ddr_phy(flags);

+	config_dmc400(flags, para);

+	//serial_puts("dram");

+	//print_u32(DDR_TYPE);

+	//serial_puts(" init done ...\n");

+	printf("dram%d init done ...\n", DDR_TYPE);

+

+	return 0;

+}

+

diff --git a/board/rda/rda8810e/ddr3_8810e_32bit.c b/board/rda/rda8810e/ddr3_8810e_32bit.c
new file mode 100644
index 0000000000..c3a8c1fa95
--- /dev/null
+++ b/board/rda/rda8810e/ddr3_8810e_32bit.c
@@ -0,0 +1,410 @@
+#include <common.h>

+#include <asm/arch/rda_iomap.h>

+

+#include "ddr3.h"

+#include "tgt_ap_clock_config.h"

+

+#define DDR_TYPE	3

+#define DF_DELAY	(0x100000)

+

+#define DMC_REG_BASE RDA_DMC400_BASE

+#define PHY_REG_BASE RDA_DDRPHY_BASE

+

+#define  PHY_RDLAT		0

+#define  PHYWRDATA		1

+#define  STA			3

+#define  CLKSEL			4

+#define  PSSTART		5

+#define  PSDONE			6

+#define  LOCKED			6

+#define  CTRL_DELAY		7

+#define  RDELAY_SEL		8

+#define  WDELAY_SEL		9

+#define  PHY_RESET		10

+#define  RESET_DDR3		11

+#define  ODT_DELAY		12

+#define  DDR3_USED		13

+#define  WRITE_ENABLE_LAT	14

+#define  WRITE_DATA_LAT		15

+#define  DQOUT_ENABLE_LAT	16

+#define  DMC_READY          128

+#define  DATA_ODT_ENABLE_REG    20

+#define  DATA_WRITE_ENABLE_REG  48   

+

+#define ARRAY_NUM(n) (sizeof(n))/(sizeof(n[0]))

+

+#define DMCREG_BADDR DMC_REG_BASE

+#define PHY_BADDR PHY_REG_BASE

+

+void DDR_CONFIG_DELAY(int delay)

+{

+    int i;

+    i = delay;

+    while(i--);

+}

+

+void config_ddr_phy(UINT16 flag)

+{

+    int cnt;

+    volatile int * addr;

+    cnt = 16;

+    while(cnt--);

+        

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (PHY_BADDR + DMC_READY*4);

+    *addr = 0;    

+    

+    addr = (int *) (PHY_BADDR + RESET_DDR3*4);

+    *addr = 1;

+

+    addr = (int *) (PHY_BADDR + WRITE_DATA_LAT*4);

+    *addr = 1;    

+    

+    addr = (int *) (PHY_BADDR + DDR3_USED*4);

+    *addr = 1;    

+   

+    addr = (int *) (PHY_BADDR + WDELAY_SEL*4);

+    *addr = 3;    

+    

+    addr = (int *) (PHY_BADDR + DQOUT_ENABLE_LAT*4);

+    *addr = 1;

+

+    addr = (int *) (PHY_BADDR + DATA_ODT_ENABLE_REG*4);

+    *addr = 0xf;

+    

+    addr = (int *) (PHY_BADDR + DATA_WRITE_ENABLE_REG*4);

+    *addr = 0xf;  

+          	

+    serial_puts("ddr3 phy init done!\n");  

+}

+

+#define DMC_WAIT_IDLE     1

+

+void config_dmc400(UINT16 flag, UINT32 para)

+{

+    int wait_idle;

+    volatile int *addr;

+    volatile int temp;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x200);

+    *addr = 0x3f;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x204);

+    *addr = 0x23008c;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x204);

+    *addr = 0x8c008c;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x208);

+    *addr = 0x4;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x20c);

+    *addr = 0xc;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x218);

+    *addr = 0x6;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x21c);

+    *addr = 0xf;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x220);

+    *addr = 0x6;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x224);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x228);

+    *addr = 0x4;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x22c);

+    *addr = 0x14;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x234);

+    *addr = 0x6;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x238);

+    *addr = 0x6;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x23c);

+    *addr = 0x4;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x244);

+    *addr = 0x10;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x248);

+    *addr = 0x4000d;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x248);

+    *addr = 0x6000f;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x24c);

+    *addr = 0x60000;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x230);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x240);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x300);

+    *addr = 0x2;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x304);

+    *addr = 0x105;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x304);

+    *addr = 0x105;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x258);

+    *addr = 0x3;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x25c);

+    *addr = 0x20003;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x25c);

+    *addr = 0xa0003;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x260);

+    *addr = 0x4;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x264);

+    *addr = 0x1000090;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x264);

+    *addr = 0x2000090;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x268);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x26c);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x250);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x254);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x148);

+    *addr = 0x0;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    *addr = 0x30200;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    *addr = 0x30200;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    *addr = 0x30200;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x18);

+    //*addr = 0x22000201;

+    *addr = 0x22000202;

+

+    wait_idle = DMC_WAIT_IDLE * 0x1d;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    *addr = 0x30200;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    //*addr = 0x30401;

+    *addr = 0x30302;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x14);

+    *addr = 0x50;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x14);

+    //*addr = 0x10;

+    *addr = 0x00;

+

+    wait_idle = DMC_WAIT_IDLE * 0x6;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x0;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x10020008;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x10030000;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x10010001;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x10000520;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x50000400;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x30000000;

+

+    wait_idle = DMC_WAIT_IDLE * 0x6;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x148);

+    *addr = 0x0;

+

+    wait_idle = DMC_WAIT_IDLE * 0x8;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x8);

+    *addr = 0x3;

+

+    addr = (int * ) (DMCREG_BADDR + 0x0);

+    temp = 0;

+    while (temp != 3)

+        temp = *addr;

+

+    serial_puts("ddr3 dmc400 init done!\n");

+}

+

+void axi_prio_init(void)

+{

+    *(volatile UINT32*)(0x20900100) = 0xaa0000aa;

+    *(volatile UINT32*)(0x21054100) = 0x00000008;

+    *(volatile UINT32*)(0x21054104) = 0x00000008;

+}

+

+void axi_outstandings_init(void)

+{

+    *(volatile UINT32*)(0x2104210C) = 0x00000060;

+    *(volatile UINT32*)(0x21042110) = 0x00000300;

+}

+

+int ddr_init(UINT16 flags, UINT32 para)

+{

+    UINT16 dll_off;

+    UINT32 mem_width;

+

+    //axi_prio_init();

+    axi_outstandings_init();

+

+    dll_off = flags & DDR_FLAGS_DLLOFF;

+    mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;

+

+    switch (mem_width) {

+    case 0:

+        serial_puts("8bit ");

+        break;

+    case 1:

+        serial_puts("16bit ");

+        break;

+    case 2:

+        serial_puts("32bit ");

+        break;

+    }

+    if (dll_off)

+        serial_puts("dll-off Mode ...\n");

+    else

+        serial_puts("dll-on Mode ...\n");

+

+    config_ddr_phy(flags);

+    config_dmc400(flags, para);

+    //serial_puts("dram ");

+    //print_u32(DDR_TYPE);

+    //serial_puts(" init done ...\n");

+    printf("ddr%d init done\n");

+

+    return 0;

+}

diff --git a/board/rda/rda8810e/ddr3_init.h b/board/rda/rda8810e/ddr3_init.h
new file mode 100644
index 0000000000..402375d269
--- /dev/null
+++ b/board/rda/rda8810e/ddr3_init.h
@@ -0,0 +1,101 @@
+#ifndef _SYS_RAM_INIT_H_
+#define _SYS_RAM_INIT_H_
+
+#define MEMC_STATUS			0x000
+#define MEMC_CONFIG			0x004
+#define MEMC_CMD			0x008
+#define ADDR_CTRL			0x010
+#define DECODE_CTRL			0x014
+#define FORMAT_CTRL			0x018
+#define LOWPWR_CTRL			0x020
+#define TURNAROUND_PRIO			0x030
+#define HIT_PRIO			0x034
+//QOS0~QOS15:038~078
+#define QOSX_CTRL			0x038
+#define QOSX_CTRL7			0x058
+#define QOSX_CTRL15			0x078
+#define TIMEOUT_CTRL			0x07C
+#define QUEUE_CTRL			0x080
+#define WR_PRIO_CTRL			0x088
+#define WR_PRIO_CTRL2			0x08C
+#define RD_PRIO_CTRL			0x090
+#define RD_PRIO_CTRL2			0x094
+#define ACCESS_ADDR_MATCH		0x098
+#define ACCESS_ADDR_MATCH_63_32		0x09C
+#define ACCESS_ADDR_MASK		0x0A0
+#define ACCESS_ADDR_MASK_63_32		0x0A4
+
+#define CHANNEL_STATUS			0x100
+#define DIRECT_CMD			0x108
+#define MR_DATA				0x110
+#define REFRESH_CTRL			0x120
+#define INTR_CTRL			0x128
+#define INTR_CLR			0x130
+#define INTR_STATUS			0x138
+#define INTR_INFO			0x140
+#define ECC_CTRL			0x148
+
+#define T_REFI				0x200
+#define T_RFC				0x204
+#define T_MRR				0x208
+#define T_MRW				0x20C
+#define T_RCD				0x218
+#define T_RAS				0x21C
+#define T_RP				0x220
+#define T_RPALL				0x224
+#define T_RRD				0x228
+#define T_FAW				0x22C
+#define RD_LATENCY			0x230
+#define T_RTR				0x234
+#define T_RTW				0x238
+#define T_RTP				0x23C
+#define WR_LATENCY			0x240
+#define T_WR				0x244
+#define T_WTR				0x248
+#define T_WTW				0x24C
+#define T_ECKD				0x250
+#define T_XCKD				0x254
+#define T_EP				0x258
+#define T_XP				0x25C
+#define T_ESR				0x260
+#define T_XSR				0x264
+#define T_SRCKD				0x268
+#define T_CKSRD				0x26C
+
+#define T_RDDATA_EN			0x300
+#define T_PHYWRLAT			0x304
+#define RDLVL_CTRL			0x308
+#define RDLVL_DIRECT			0x310
+#define T_RDLVL_EN			0x318
+#define T_RDLVL_RR			0x31C
+#define WRLVL_CTRL			0x328
+#define WRLVL_DIRECT			0x330
+#define T_WRLVL_EN			0x338
+#define T_WRLVL_WW			0x33C
+
+#define PHY_PWR_CTRL			0x348
+#define PHY_UPD_CTRL			0x350
+
+#define USER_STATUS			0x400
+#define USER_CONFIG0			0x404
+#define USER_CONFIG1			0x408
+
+#define INTEG_CFG			0xE00
+#define INTEG_OUTPUTS			0xE08
+
+#define PERIPH_ID_0			0xFE0
+#define PERIPH_ID_1			0xFE4
+#define PERIPH_ID_2			0xFE8
+#define PERIPH_ID_3			0xFEC
+#define COMPONENT_ID_0			0xFF0
+#define COMPONENT_ID_1			0xFF4
+#define COMPONENT_ID_2			0xFF8
+#define COMPONENT_ID_3			0xFFC
+
+typedef struct {
+	UINT32 reg_offset;
+	UINT32 dll_on_val;
+	UINT32 dll_off_val;
+} dmc_reg_t;
+
+#endif /* _SYS_RAM_INIT_H_ */
diff --git a/board/rda/rda8810e/debug.h b/board/rda/rda8810e/debug.h
new file mode 100644
index 0000000000..1d4f03bedb
--- /dev/null
+++ b/board/rda/rda8810e/debug.h
@@ -0,0 +1,9 @@
+#ifndef _DEBUG_H_
+#define _DEBUG_H_
+
+void print_u8(u8 ch);
+void print_u16(u16 data);
+void print_u32(u32 data);
+void dump_buf(u8 *buf, u32 size);
+
+#endif /* _DEBUG_H_ */
diff --git a/board/rda/rda8810e/hal_config.c b/board/rda/rda8810e/hal_config.c
new file mode 100644
index 0000000000..86af7cd2c8
--- /dev/null
+++ b/board/rda/rda8810e/hal_config.c
@@ -0,0 +1,1449 @@
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//            Copyright (C) 2013, RDA Microeletronics.                        //
+//                            All Rights Reserved                             //
+//                                                                            //
+//      This source code is the property of RDA Microeletronics and is        //
+//      confidential.  Any  modification, distribution,  reproduction or      //
+//      exploitation  of  any content of this file is totally forbidden,      //
+//      except  with the  written permission  of  RDA Microeletronics.        //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//  $HeadURL: http://svn.rdamicro.com/svn/developing1/Sources/chip/branches/8810/hal/8810/src/hal_config.c $ //
+//    $Author: huazeng $                                                        //
+//    $Date: 2013-08-31 17:48:58 +0800 (Sat, 31 Aug 2013) $                     //
+//    $Revision: 21005 $                                                          //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+/// @file hal_config.c
+/// Implementation of HAL initialization related with the particular instance
+/// of the IP.
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+
+/* uboot */
+#include <common.h>
+
+/* common */
+#include <asm/arch/rda_iomap.h>
+#include <asm/arch/hwcfg.h>
+#include <asm/arch/chip_id.h>
+#include <asm/arch/cs_types.h>
+#include <asm/arch/global_macros.h>
+#include <asm/arch/reg_gpio.h>
+
+/* device */
+#include "hal_sys.h"
+#include "halp_sys.h"
+#include "halp_gpio.h"
+#include "bootp_mode.h"
+#include "hal_config.h"
+#include "hal_ap_gpio.h"
+#include "hal_ap_config.h"
+#include <asm/arch/reg_cfg_regs.h>
+
+/* target */
+#include "tgt_board_cfg.h"
+#include "tgt_ap_gpio_setting.h"
+#define HAL_ASSERT(cond, fmt, ...) \
+    if(!(cond)) { \
+        hal_assert(fmt, ##__VA_ARGS__); \
+        g_halConfigError = TRUE; \
+    }
+
+//// =============================================================================
+////  GLOBAL VARIABLES
+//// =============================================================================
+PRIVATE CONST UINT8 g_halCfgSimOrder[] = { TGT_SIM_ORDER };
+PRIVATE HAL_CFG_CONFIG_T hal_cfg = TGT_HAL_CONFIG;
+PRIVATE UINT32 g_bootBootMode = 0;
+PRIVATE BOOL g_halConfigError = FALSE;
+
+
+// =============================================================================
+//  FUNCTIONS
+// =============================================================================
+// HAL_ASSERT
+PRIVATE VOID hal_assert(const char *fmt, ...)
+{
+    va_list args;
+    puts("\n#-------Board Mux config found error-------#\n");
+    va_start(args, fmt);
+    vprintf(fmt, args);
+    putc('\n');
+    puts("--------------------------------------------\n\n");
+    va_end(args);
+}
+
+// =============================================================================
+// hal_BoardSimUsed
+// -----------------------------------------------------------------------------
+/// Check whether a SIM card interface is used.
+// ============================================================================
+PRIVATE BOOL hal_BoardSimUsed(UINT32 simId)
+{
+    UINT32 i;
+    for (i=0; i<ARRAY_SIZE(g_halCfgSimOrder) && i<NUMBER_OF_SIM; i++)
+    {
+        if (g_halCfgSimOrder[i] == simId)
+        {
+            return TRUE;
+        }
+    }
+
+    return FALSE;
+}
+
+#if 0
+// =============================================================================
+// hal_BoardConfigClk32k
+// -----------------------------------------------------------------------------
+/// Configure CLK_32K output.
+/// @param enable TRUE to configure, and FALSE to disable.
+// ============================================================================
+PROTECTED VOID hal_BoardConfigClk32k(BOOL enable)
+{
+    HAL_ASSERT(g_halCfg->useClk32k == TRUE, "32K clock is not configured");
+
+    if (enable)
+    {
+        // Setup the pin as 32K clock output
+        hwp_configRegs->Alt_mux_select =
+            (hwp_configRegs->Alt_mux_select & ~CFG_REGS_GPO_2_MASK) |
+            CFG_REGS_GPO_2_CLK_32K;
+    }
+    else
+    {
+        // Setup the pin as GPO (and low ouput has been
+        // configured in hal_BoardSetup())
+        hwp_configRegs->Alt_mux_select =
+            (hwp_configRegs->Alt_mux_select & ~CFG_REGS_GPO_2_MASK) |
+            CFG_REGS_GPO_2_GPO_2;
+    }
+}
+#endif
+
+// =============================================================================
+// hal_BoardSetupGeneral
+// -----------------------------------------------------------------------------
+/// Apply board dependent configuration to HAL for general purpose
+/// @param halCfg Pointer to HAL configuration structure (from the target
+/// module).
+// ============================================================================
+PROTECTED VOID hal_BoardSetupGeneral(CONST HAL_CFG_CONFIG_T* halCfg)
+{
+    UINT32 altMux = 0;
+    UINT32 altMux2 = 0;
+
+    UINT32 availableGpo_A = 0;
+
+    UINT32 availableGpio_C = 0;
+    UINT32 availableGpio_A = 0;
+    UINT32 availableGpio_B = 0;
+    UINT32 availableGpio_D = 0;
+    UINT32 availableGpio_E = 0;
+
+    UINT32 bootModeGpio_C = 0;
+    UINT32 bootModeGpio_A = 0;
+    UINT32 bootModeGpio_B = 0;
+    UINT32 bootModeGpio_D = 0;
+    UINT32 bootModeGpio_E = 0;
+
+    UINT32 noConnectMask_C = 0;
+    UINT32 noConnectMask_A = 0;
+    UINT32 noConnectMask_B = 0;
+    UINT32 noConnectMask_D = 0;
+    UINT32 noConnectMask_E = 0;
+
+    UINT32 gpoClr_A = 0;
+
+#ifdef FPGA
+
+    // no muxing, do nothing
+
+#else // !FPGA
+
+    // GPIOs as boot mode pins
+    bootModeGpio_C = HAL_GPIO_BIT(1)
+                   | HAL_GPIO_BIT(2)
+                   | HAL_GPIO_BIT(3)
+                   | HAL_GPIO_BIT(4)
+                   | HAL_GPIO_BIT(5);
+    bootModeGpio_A = HAL_GPIO_BIT(4)
+                   | HAL_GPIO_BIT(5)
+                   | HAL_GPIO_BIT(6)
+                   | HAL_GPIO_BIT(7);
+    bootModeGpio_B = HAL_GPIO_BIT(0);
+    bootModeGpio_D = 0;
+    bootModeGpio_E = 0;
+
+    // Available GPIOs
+    availableGpio_C |= HAL_GPIO_BIT(0)
+                     | HAL_GPIO_BIT(1)
+                     | HAL_GPIO_BIT(2)
+                     | HAL_GPIO_BIT(3)
+                     | HAL_GPIO_BIT(4)
+                     | HAL_GPIO_BIT(5);
+    // Volume down/up keys
+    availableGpio_D |= HAL_GPIO_BIT(5)
+                     | HAL_GPIO_BIT(6);
+
+    // Boot modes
+    BOOL spiFlashCam = FALSE;
+    BOOL spiFlashNand = FALSE;
+    if (g_bootBootMode & BOOT_MODE_BOOT_SPI)
+    {
+        if (g_bootBootMode & BOOT_MODE_SPI_PIN_NAND)
+        {
+            HAL_ASSERT((g_bootBootMode & BOOT_MODE_BOOT_EMMC),
+                "Emmc boot pin should be pulled up to boot on SPI flash over NAND pins");
+            spiFlashNand = TRUE;
+        }
+        else
+        {
+            spiFlashCam = TRUE;
+        }
+    }
+
+    //UINT32 metalId = rda_metal_id_get();
+    UINT32 emmcBootModeMask;
+    if (1) //metalId < 0x02)
+    {
+        emmcBootModeMask = BOOT_MODE_BOOT_EMMC
+                         | BOOT_MODE_BOOT_SPI
+                         | BOOT_MODE_BOOT_SPI_NAND;
+    }
+    else
+    {
+        emmcBootModeMask = BOOT_MODE_BOOT_EMMC
+                         | BOOT_MODE_BOOT_SPI;
+    }
+    if ((g_bootBootMode & emmcBootModeMask) == BOOT_MODE_BOOT_EMMC)
+    {
+        // Boot from EMMC
+        HAL_ASSERT(halCfg->sdmmcCfg.sdmmc3Used, "SDMMC3 (EMMC) should be used");
+    }
+
+    if (1) //metalId < 0x02)
+    {
+        if ( (g_bootBootMode & (BOOT_MODE_BOOT_SPI|BOOT_MODE_BOOT_SPI_NAND))
+             == BOOT_MODE_BOOT_SPI_NAND ||
+             (g_bootBootMode & (BOOT_MODE_BOOT_SPI|BOOT_MODE_NAND_PAGE_SIZE_L))
+             == (BOOT_MODE_BOOT_SPI|BOOT_MODE_NAND_PAGE_SIZE_L)
+           )
+        {
+            // Boot from SDMMC1
+            HAL_ASSERT(halCfg->sdmmcCfg.sdmmcUsed, "SDMMC1 should be used");
+        }
+    }
+
+    // For convenience, we do not consider spiFlashCam at present.
+    // We assume that SPI flash always uses parallel nand pins.
+#if 0
+    BOOL parallelNandUsed = halCfg->parallelNandUsed;
+#else
+    BOOL parallelNandUsed = !spiFlashNand && !halCfg->sdmmcCfg.sdmmc3Used;
+#endif
+    BOOL nand8_15Cam = FALSE;
+    BOOL nand8_15Lcd = FALSE;
+    if ((g_bootBootMode & (BOOT_MODE_BOOT_SPI|BOOT_MODE_BOOT_EMMC)) == 0)
+    {
+        HAL_ASSERT(parallelNandUsed, "Parallel NAND should be used");
+    }
+    if (parallelNandUsed)
+    {
+        HAL_ASSERT(!spiFlashNand, "SPI flash uses parallel NAND pins");
+        HAL_ASSERT(!halCfg->sdmmcCfg.sdmmc3Used,
+            "SDMMC3 (EMMC) uses parallel NAND pins");
+        if ((g_bootBootMode & BOOT_MODE_NAND_8BIT) == 0)
+        {
+            if (g_bootBootMode & BOOT_MODE_NAND_HIGH_PIN_CAM)
+            {
+                HAL_ASSERT(!spiFlashCam, "SPI flash uses NAND 8-15 bits on cam pins");
+                nand8_15Cam = TRUE;
+            }
+            else
+            {
+                nand8_15Lcd = TRUE;
+            }
+        }
+    }
+
+    if (!parallelNandUsed)
+    {
+        availableGpio_D |= HAL_GPIO_BIT(9);
+
+#ifdef NAND_IO_RECONFIG_WORKROUND
+        if (spiFlashNand)
+        {/*GPIO_B:25,26,27,28,29; GPIO_D:4  the output level is inverted*/
+            availableGpio_B |= HAL_GPIO_BIT(25)
+                             | HAL_GPIO_BIT(26)
+                             | HAL_GPIO_BIT(27)
+                             | HAL_GPIO_BIT(28)
+                             | HAL_GPIO_BIT(29);
+            availableGpio_D |= HAL_GPIO_BIT(4);
+        }else{
+	     availableGpio_D |= HAL_GPIO_BIT(8);
+	}
+#else
+        if (!spiFlashNand)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(25)
+                             | HAL_GPIO_BIT(26)
+                             | HAL_GPIO_BIT(27)
+                             | HAL_GPIO_BIT(28)
+                             | HAL_GPIO_BIT(29);
+            availableGpio_D |= HAL_GPIO_BIT(4)
+                             | HAL_GPIO_BIT(8);
+        }
+#endif
+
+        if (!halCfg->sdmmcCfg.sdmmc3Used)
+        {
+            availableGpio_D |= HAL_GPIO_BIT(10);
+        }
+    	}
+#ifdef NAND_IO_RECONFIG_WORKROUND
+	else
+	{/*GPIO_B:25,26,27,28,29; GPIO_D:4  the output level is inverted*/
+            availableGpio_B |= HAL_GPIO_BIT(25)
+                             | HAL_GPIO_BIT(26)
+                             | HAL_GPIO_BIT(27)
+                             | HAL_GPIO_BIT(28)
+                             | HAL_GPIO_BIT(29);
+            availableGpio_D |= HAL_GPIO_BIT(4);
+        }
+#endif
+
+    CONST HAL_CFG_CAM_T *camCfg = &halCfg->camCfg;
+    CONST HAL_CFG_CAM_T *cam2Cfg = &halCfg->cam2Cfg;
+    CONST HAL_LCD_MODE_T lcdMode = halCfg->goudaCfg.lcdMode;
+
+    // LCD
+    if (lcdMode == HAL_LCD_MODE_PARALLEL_16BIT)
+    {
+        /* Check LCD 8-15 bits */
+        HAL_ASSERT(!nand8_15Lcd, "NAND uses LCD 8-15 bits");
+        HAL_ASSERT(!halCfg->goudaCfg.lcd8_23Cam2, "Parallel LCD 8-5 bits should use NAND pins only");
+        altMux |= CFG_REGS_LCD_MODE_PARALLEL_16BIT;
+    }
+    else if (lcdMode == HAL_LCD_MODE_DSI)
+    {
+        altMux |= CFG_REGS_LCD_MODE_DSI;
+        availableGpio_A |= HAL_GPIO_BIT(22)
+                         | HAL_GPIO_BIT(23);
+    }
+    else if (lcdMode == HAL_LCD_MODE_RGB_16BIT ||
+             lcdMode == HAL_LCD_MODE_RGB_18BIT ||
+             lcdMode == HAL_LCD_MODE_RGB_24BIT)
+    {
+        /* Check LCD 8-15 bits */
+        if (halCfg->goudaCfg.lcd8_23Cam2)
+        {
+            HAL_ASSERT(!(cam2Cfg->camUsed || cam2Cfg->cam1Used),
+                "Camera2 uses LCD 8-15 bits");
+            altMux2 |= CFG_REGS_RGB_CAM_2_ENABLE;
+        }
+        else
+        {
+            HAL_ASSERT(!nand8_15Lcd, "NAND uses LCD 8-15 bits");
+        }
+        if (lcdMode == HAL_LCD_MODE_RGB_18BIT ||
+            lcdMode == HAL_LCD_MODE_RGB_24BIT)
+        {
+            /* Check LCD 16-23 bits */
+            if (lcdMode == HAL_LCD_MODE_RGB_18BIT && halCfg->goudaCfg.lcd16_17Cs)
+            {
+                HAL_ASSERT(!halCfg->goudaCfg.lcd16_23Cam,
+                    "LCD 16-17 bits have been configured on camera pins");
+                HAL_ASSERT(!(halCfg->goudaCfg.cs0Used || halCfg->goudaCfg.cs1Used),
+                    "LCD CS 0/1 use LCD 16-17 bits");
+                altMux2 |= CFG_REGS_LCD_RGB_17_16_LCD_DATA;
+            }
+            else if (halCfg->goudaCfg.lcd8_23Cam2)
+            {
+                HAL_ASSERT(!halCfg->goudaCfg.lcd16_23Cam,
+                    "LCD 16-23 bits have been configured on camera pins");
+                HAL_ASSERT(halCfg->goudaCfg.lcd16_17Cs,
+                    "LCD 16-17 bits should use LCD CS 0/1");
+                HAL_ASSERT(!(halCfg->goudaCfg.cs0Used || halCfg->goudaCfg.cs1Used),
+                    "LCD CS 0/1 use LCD 16-17 bits");
+                HAL_ASSERT(!(cam2Cfg->camUsed || cam2Cfg->cam1Used),
+                    "Camera2 uses LCD 18-23 bits");
+                altMux2 |= CFG_REGS_LCD_RGB_17_16_LCD_DATA;
+                altMux2 |= CFG_REGS_RGB_CAM_2_ENABLE;
+            }
+            else if (halCfg->goudaCfg.lcd16_23Cam)
+            {
+                HAL_ASSERT(!(halCfg->goudaCfg.lcd16_17Cs || halCfg->goudaCfg.lcd8_23Cam2),
+                    "LCD 16-23 bits have been configured on LCD CS 0/1 and camera2 pins");
+                HAL_ASSERT(
+                    !(camCfg->camMode == HAL_CAM_MODE_PARALLEL &&
+                      (camCfg->camUsed || camCfg->cam1Used)),
+                    "Parallel camera uses LCD 16-23 bits");
+                HAL_ASSERT(
+                    !(halCfg->i2cCfg.i2c2Used && halCfg->i2cCfg.i2c2PinsCam),
+                    "I2C2 uses LCD 22-23 bits");
+                HAL_ASSERT(!spiFlashCam, "SPI flash uses LCD 16-21 bits");
+                HAL_ASSERT(!nand8_15Cam, "NAND uses LCD 16-23 bits");
+                HAL_ASSERT(
+                    !(camCfg->camMode == HAL_CAM_MODE_CSI &&
+                      ((camCfg->camUsed && camCfg->camCsiId == HAL_CAM_CSI_1) ||
+                       (camCfg->cam1Used && camCfg->cam1CsiId == HAL_CAM_CSI_1))),
+                    "Camera CSI1 uses LCD 16-21 bits");
+                altMux |= CFG_REGS_RGB_CAM_ENABLE;
+            }
+            else
+            {
+                HAL_ASSERT(!parallelNandUsed, "NAND uses LCD 16-23 bits");
+                HAL_ASSERT(!halCfg->sdmmcCfg.sdmmc3Used, "SDMMC3 uses LCD 16-23 bits");
+                altMux |= CFG_REGS_RGB_CAM_DISABLE;
+            }
+        }
+        altMux |= CFG_REGS_LCD_MODE_RGB_24BIT;
+    }
+    else if (lcdMode == HAL_LCD_MODE_SPI)
+    {
+        HAL_ASSERT(!(halCfg->goudaCfg.cs0Used || halCfg->goudaCfg.cs1Used),
+            "LCD CS 0/1 use SPI LCD pins");
+        HAL_ASSERT((halCfg->usedGpo_A & (HAL_GPO_BIT(3)|HAL_GPO_BIT(4))) == 0,
+            "GPO 3/4 use SPI LCD pins");
+        altMux |= CFG_REGS_SPI_LCD_SPI_LCD;
+        availableGpio_A |= HAL_GPIO_BIT(18)
+                         | HAL_GPIO_BIT(19)
+                         | HAL_GPIO_BIT(20)
+                         | HAL_GPIO_BIT(21);
+    }
+    else
+    {
+        HAL_ASSERT(FALSE, "Lcd mode not defined!");
+    }
+
+    if (lcdMode == HAL_LCD_MODE_DSI ||
+        lcdMode == HAL_LCD_MODE_SPI ||
+        ((lcdMode == HAL_LCD_MODE_RGB_16BIT ||
+          lcdMode == HAL_LCD_MODE_RGB_18BIT ||
+          lcdMode == HAL_LCD_MODE_RGB_24BIT) &&
+         halCfg->goudaCfg.lcd8_23Cam2))
+    {
+        if (!nand8_15Lcd)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(24)
+                             | HAL_GPIO_BIT(25)
+                             | HAL_GPIO_BIT(26)
+                             | HAL_GPIO_BIT(27)
+                             | HAL_GPIO_BIT(28)
+                             | HAL_GPIO_BIT(29)
+                             | HAL_GPIO_BIT(30)
+                             | HAL_GPIO_BIT(31);
+        }
+    }
+
+    if (halCfg->goudaCfg.cs0Used)
+    {
+        altMux |= CFG_REGS_GPO_4_LCD_CS_0;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_4_GPO_4;
+        availableGpo_A |= HAL_GPO_BIT(4);
+    }
+
+    if (halCfg->goudaCfg.cs1Used)
+    {
+        altMux |= CFG_REGS_GPO_3_LCD_CS_1;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_3_GPO_3;
+        availableGpo_A |= HAL_GPO_BIT(3);
+    }
+
+    // I2C
+    if (!halCfg->i2cCfg.i2cUsed)
+    {
+        availableGpio_B |= HAL_GPIO_BIT(30)
+                         | HAL_GPIO_BIT(31);
+    }
+
+    if (halCfg->i2cCfg.i2c2Used)
+    {
+        if (halCfg->i2cCfg.i2c2PinsCam)
+        {
+            if (camCfg->camUsed)
+            {
+                HAL_ASSERT(camCfg->camPdnRemap == GPIO_NONE &&
+                    camCfg->camRstRemap == GPIO_NONE,
+                    "Cam uses PDN/RST pins");
+            }
+            if (camCfg->cam1Used)
+            {
+                HAL_ASSERT(camCfg->cam1PdnRemap == GPIO_NONE &&
+                    camCfg->cam1RstRemap == GPIO_NONE,
+                    "Cam1 uses PDN/RST pins");
+            }
+            HAL_ASSERT(!nand8_15Cam, "NAND uses cam PDN/RST pins");
+            availableGpio_A |= HAL_GPIO_BIT(0)
+                             | HAL_GPIO_BIT(1);
+            altMux |= CFG_REGS_CAM_I2C2_I2C2;
+        }
+        else
+        {
+            // I2C2 does not use cam pins
+            altMux |= CFG_REGS_CAM_I2C2_CAM;
+        }
+    }
+    else
+    {
+        // I2C2 does not use cam pins
+        altMux |= CFG_REGS_CAM_I2C2_CAM;
+        availableGpio_A |= HAL_GPIO_BIT(0)
+                         | HAL_GPIO_BIT(1);
+    }
+
+    if (halCfg->i2cCfg.i2c3Used)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x18) == 0, "Keyout 3/4 use I2C3 pins");
+        altMux |= CFG_REGS_KEYOUT_3_4_I2C3;
+    }
+    else
+    {
+        altMux |= CFG_REGS_KEYOUT_3_4_KEYOUT_3_4;
+        if ((halCfg->keyOutMask & 0x8) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(6);
+        }
+        if ((halCfg->keyOutMask & 0x10) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(7);
+        }
+    }
+
+    if (halCfg->i2cCfg.modemI2cUsed)
+    {
+        HAL_ASSERT(!halCfg->emacUsed, "EMAC uses modem I2C pins");
+    }
+    else
+    {
+        if (!halCfg->emacUsed)
+        {
+            availableGpio_E |= HAL_GPIO_BIT(0)
+                             | HAL_GPIO_BIT(1);
+        }
+    }
+
+    // Camera
+    if (camCfg->camUsed || camCfg->cam1Used)
+    {
+        if(camCfg->camMode == HAL_CAM_MODE_PARALLEL)
+        {
+            HAL_ASSERT(!spiFlashCam, "SPI flash uses cam pins");
+            HAL_ASSERT(!nand8_15Cam, "NAND 8-15 bits use cam pins");
+            altMux |= CFG_REGS_CSI2_PARALLEL_CAM;
+            availableGpio_B |= HAL_GPIO_BIT(24);
+        }
+        else if (camCfg->camMode == HAL_CAM_MODE_SPI)
+        {
+            altMux |= CFG_REGS_CSI2_SPI_CAM;
+            availableGpio_B |= HAL_GPIO_BIT(14);
+            if (!(spiFlashCam || nand8_15Cam ||
+                  (lcdMode == HAL_LCD_MODE_RGB_24BIT &&
+                   halCfg->goudaCfg.lcd16_23Cam)
+                 )
+               )
+            {
+                availableGpio_B |= HAL_GPIO_BIT(13)
+                                 | HAL_GPIO_BIT(20)
+                                 | HAL_GPIO_BIT(21)
+                                 | HAL_GPIO_BIT(22)
+                                 | HAL_GPIO_BIT(23)
+                                 | HAL_GPIO_BIT(24);
+            }
+        }
+        else if (camCfg->camMode == HAL_CAM_MODE_CSI)
+        {
+            if ((camCfg->camUsed && camCfg->camCsiId == HAL_CAM_CSI_1) ||
+                (camCfg->cam1Used && camCfg->cam1CsiId == HAL_CAM_CSI_1))
+            {
+                HAL_ASSERT(!spiFlashCam, "SPI flash uses CSI1 pins");
+                HAL_ASSERT(!nand8_15Cam, "NAND 8-15 bits use CSI1 pins");
+            }
+            else
+            {
+                // CSI1 is unused
+                if (!(spiFlashCam || nand8_15Cam ||
+                      (lcdMode == HAL_LCD_MODE_RGB_24BIT &&
+                       halCfg->goudaCfg.lcd16_23Cam)
+                     )
+                   )
+                {
+                    availableGpio_B |= HAL_GPIO_BIT(13)
+                                     | HAL_GPIO_BIT(20)
+                                     | HAL_GPIO_BIT(21)
+                                     | HAL_GPIO_BIT(22)
+                                     | HAL_GPIO_BIT(23)
+                                     | HAL_GPIO_BIT(24);
+                }
+            }
+            altMux |= CFG_REGS_CSI2_CSI2;
+            // If CSI2 is unused
+            if (!((camCfg->camUsed && camCfg->camCsiId == HAL_CAM_CSI_2) ||
+                  (camCfg->cam1Used && camCfg->cam1CsiId == HAL_CAM_CSI_2)))
+            {
+                availableGpio_B |= HAL_GPIO_BIT(14)
+                                 | HAL_GPIO_BIT(15)
+                                 | HAL_GPIO_BIT(16)
+                                 | HAL_GPIO_BIT(17)
+                                 | HAL_GPIO_BIT(18)
+                                 | HAL_GPIO_BIT(19);
+            }
+        }
+        else
+        {
+            HAL_ASSERT(FALSE, "Invalid cam mode: %d", camCfg->camMode);
+        }
+
+        // Cam PDN/RST pins
+        if (!(nand8_15Cam ||
+              (lcdMode == HAL_LCD_MODE_RGB_24BIT && halCfg->goudaCfg.lcd16_23Cam) ||
+              (halCfg->i2cCfg.i2c2Used && halCfg->i2cCfg.i2c2PinsCam)
+             )
+           )
+        {
+            if (!((camCfg->camUsed && camCfg->camRstRemap == GPIO_NONE) ||
+                  (camCfg->cam1Used && camCfg->cam1RstRemap == GPIO_NONE)))
+            {
+                availableGpio_B |= HAL_GPIO_BIT(10);
+            }
+            if (!((camCfg->camUsed && camCfg->camPdnRemap == GPIO_NONE) ||
+                  (camCfg->cam1Used && camCfg->cam1PdnRemap == GPIO_NONE)))
+            {
+                availableGpio_B |= HAL_GPIO_BIT(11);
+            }
+        }
+    }
+    else // cam is unused
+    {
+        availableGpio_B |= HAL_GPIO_BIT(12)
+                         | HAL_GPIO_BIT(14)
+                         | HAL_GPIO_BIT(15)
+                         | HAL_GPIO_BIT(16)
+                         | HAL_GPIO_BIT(17)
+                         | HAL_GPIO_BIT(18)
+                         | HAL_GPIO_BIT(19);
+        if (!(nand8_15Cam ||
+              (lcdMode == HAL_LCD_MODE_RGB_24BIT && halCfg->goudaCfg.lcd16_23Cam) ||
+              (halCfg->i2cCfg.i2c2Used && halCfg->i2cCfg.i2c2PinsCam)
+             )
+           )
+        {
+            availableGpio_B |= HAL_GPIO_BIT(10)
+                             | HAL_GPIO_BIT(11);
+        }
+        if (!(spiFlashCam || nand8_15Cam ||
+              (lcdMode == HAL_LCD_MODE_RGB_24BIT && halCfg->goudaCfg.lcd16_23Cam)
+             )
+           )
+        {
+            availableGpio_B |= HAL_GPIO_BIT(13)
+                             | HAL_GPIO_BIT(20)
+                             | HAL_GPIO_BIT(21)
+                             | HAL_GPIO_BIT(22)
+                             | HAL_GPIO_BIT(23)
+                             | HAL_GPIO_BIT(24);
+        }
+    }
+
+    // Camera2
+    if (cam2Cfg->camUsed || cam2Cfg->cam1Used)
+    {
+        if(cam2Cfg->camMode == HAL_CAM_MODE_PARALLEL)
+        {
+            altMux2 |= CFG_REGS_CSI2_2_PARALLEL_CAM;
+        }
+        else if (cam2Cfg->camMode == HAL_CAM_MODE_SPI)
+        {
+            altMux2 |= CFG_REGS_CSI2_2_SPI_CAM;
+            availableGpio_E |= HAL_GPIO_BIT(4)
+                             | HAL_GPIO_BIT(5)
+                             | HAL_GPIO_BIT(6)
+                             | HAL_GPIO_BIT(12)
+                             | HAL_GPIO_BIT(13)
+                             | HAL_GPIO_BIT(14)
+                             | HAL_GPIO_BIT(15);
+        }
+        else if (cam2Cfg->camMode == HAL_CAM_MODE_CSI)
+        {
+            if ((cam2Cfg->camUsed && (cam2Cfg->camCsiId == HAL_CAM_CSI_1 ||
+                                      cam2Cfg->camCsiId == HAL_CAM_CSI_2)) ||
+                (cam2Cfg->cam1Used && (cam2Cfg->cam1CsiId == HAL_CAM_CSI_1 ||
+                                       cam2Cfg->cam1CsiId == HAL_CAM_CSI_2)))
+            {
+                altMux2 |= CFG_REGS_CSI2_2_CSI2;
+            }
+            else
+            {
+                availableGpio_E |= HAL_GPIO_BIT(4)
+                                 | HAL_GPIO_BIT(5)
+                                 | HAL_GPIO_BIT(6)
+                                 | HAL_GPIO_BIT(7)
+                                 | HAL_GPIO_BIT(8)
+                                 | HAL_GPIO_BIT(9)
+                                 | HAL_GPIO_BIT(10)
+                                 | HAL_GPIO_BIT(11)
+                                 | HAL_GPIO_BIT(12)
+                                 | HAL_GPIO_BIT(13)
+                                 | HAL_GPIO_BIT(14)
+                                 | HAL_GPIO_BIT(15);
+            }
+        }
+        else
+        {
+            HAL_ASSERT(FALSE, "Invalid cam2 mode: %d", cam2Cfg->camMode);
+        }
+
+        // Cam2 PDN/RST pins
+        if (!((cam2Cfg->camUsed && cam2Cfg->camRstRemap == GPIO_NONE) ||
+              (cam2Cfg->cam1Used && cam2Cfg->cam1RstRemap == GPIO_NONE)))
+        {
+            availableGpio_E |= HAL_GPIO_BIT(2);
+        }
+        if (!((cam2Cfg->camUsed && cam2Cfg->camPdnRemap == GPIO_NONE) ||
+              (cam2Cfg->cam1Used && cam2Cfg->cam1PdnRemap == GPIO_NONE) ||
+              (altMux2 & CFG_REGS_CSI2_2_CSI2)))
+        {
+            availableGpio_E |= HAL_GPIO_BIT(3);
+        }
+    }
+    else // cam2 is unused
+    {
+        if (!((lcdMode == HAL_LCD_MODE_RGB_16BIT ||
+               lcdMode == HAL_LCD_MODE_RGB_18BIT ||
+               lcdMode == HAL_LCD_MODE_RGB_24BIT) &&
+              halCfg->goudaCfg.lcd8_23Cam2))
+        {
+                availableGpio_E |= HAL_GPIO_BIT(2)
+                                 | HAL_GPIO_BIT(3)
+                                 | HAL_GPIO_BIT(4)
+                                 | HAL_GPIO_BIT(5)
+                                 | HAL_GPIO_BIT(6)
+                                 | HAL_GPIO_BIT(7)
+                                 | HAL_GPIO_BIT(8)
+                                 | HAL_GPIO_BIT(9)
+                                 | HAL_GPIO_BIT(10)
+                                 | HAL_GPIO_BIT(11)
+                                 | HAL_GPIO_BIT(12)
+                                 | HAL_GPIO_BIT(13)
+                                 | HAL_GPIO_BIT(14)
+                                 | HAL_GPIO_BIT(15);
+        }
+    }
+
+    // UART 1 Pin configuration
+    switch (halCfg->uartCfg[0])
+    {
+        case HAL_UART_CONFIG_NONE:
+            altMux |= CFG_REGS_KEYOUT_7_KEYOUT_7;
+            availableGpio_C |= HAL_GPIO_BIT(6);
+            availableGpio_A |= HAL_GPIO_BIT(14);
+            if ((halCfg->keyInMask & 0x80) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(15);
+            }
+            if ((halCfg->keyInMask & 0x80) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(16);
+            }
+            break;
+        case HAL_UART_CONFIG_DATA:
+             // use UART1 TXD, RXD
+            altMux |= CFG_REGS_KEYOUT_7_KEYOUT_7;
+            if ((halCfg->keyInMask & 0x80) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(15);
+            }
+            if ((halCfg->keyInMask & 0x80) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(16);
+            }
+            break;
+        case HAL_UART_CONFIG_FLOWCONTROL:
+             // use UART1 TXD, RXD, CTS, RTS
+            HAL_ASSERT((halCfg->keyInMask & 0x80) == 0, "Keyin 7 uses UART1 CTS");
+            HAL_ASSERT((halCfg->keyOutMask & 0x80) == 0, "Keyout 7 uses UART1 RTS");
+            altMux |= CFG_REGS_KEYOUT_7_UART1_RTS;
+            break;
+        case HAL_UART_CONFIG_MODEM:
+            // use UART1 TXD, RXD, CTS, RTS, RI, DSR, DCD, DTR
+            HAL_ASSERT((halCfg->keyInMask & 0x80) == 0, "Keyin 7 uses UART1 CTS");
+            HAL_ASSERT((halCfg->keyOutMask & 0x80) == 0, "Keyout 7 uses UART1 RTS");
+            HAL_ASSERT(!halCfg->hostUartUsed, "Host UART uses UART1 DCD/DTR");
+            HAL_ASSERT(halCfg->uartCfg[1] == HAL_UART_CONFIG_NONE,
+                    "UART 2 must be unused to use UART1 Modem lines.");
+            HAL_ASSERT((halCfg->keyInMask & 0x40) == 0, "Keyin 6 uses UART1 DSR");
+            HAL_ASSERT((halCfg->keyOutMask & 0x40) == 0, "Keyout 6 uses UART1 RI");
+            altMux |= CFG_REGS_KEYOUT_7_UART1_RTS
+                    | CFG_REGS_UART1_8LINE_UART1_8_LINE;
+            break;
+        default:
+            HAL_ASSERT(FALSE,
+                    "Invalid Uart 1 Configuration (%d).",
+                    halCfg->uartCfg[0]);
+            break;
+    }
+
+    // Host UART
+    if (halCfg->hostUartUsed)
+    {
+        HAL_ASSERT(halCfg->uartCfg[1] == HAL_UART_CONFIG_NONE,
+                "UART2 uses host UART RXD/TXD.");
+    }
+
+    // UART 2 Pin configuration
+    switch (halCfg->uartCfg[1])
+    {
+        case HAL_UART_CONFIG_NONE:
+            altMux |= CFG_REGS_UART2_HOST_UART
+                    | CFG_REGS_KEYOUT_6_KEYOUT_6;
+            if (halCfg->uartCfg[0] != HAL_UART_CONFIG_MODEM)
+            {
+                availableGpio_C |= HAL_GPIO_BIT(7)
+                                 | HAL_GPIO_BIT(8);
+            }
+            if ((halCfg->keyInMask & 0x40) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(8);
+            }
+            if ((halCfg->keyOutMask & 0x40) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(9);
+            }
+            break;
+        case HAL_UART_CONFIG_DATA:
+            // use UART2 TXD, RXD
+            altMux |= CFG_REGS_UART2_UART2
+                    | CFG_REGS_KEYOUT_6_KEYOUT_6;
+            if ((halCfg->keyInMask & 0x40) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(8);
+            }
+            if ((halCfg->keyOutMask & 0x40) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(9);
+            }
+            break;
+        case HAL_UART_CONFIG_FLOWCONTROL:
+             // use UART2 TXD, RXD, CTS, RTS
+            HAL_ASSERT((halCfg->keyInMask & 0x40) == 0, "Keyin 6 uses UART2 CTS");
+            HAL_ASSERT((halCfg->keyOutMask & 0x40) == 0, "Keyout 6 uses UART2 RTS");
+            altMux |= CFG_REGS_UART2_UART2
+                    | CFG_REGS_KEYOUT_6_UART2_RTS;
+            break;
+        case HAL_UART_CONFIG_MODEM:
+        default:
+            HAL_ASSERT(FALSE,
+                    "Invalid Uart2 Configuration (%d).",
+                    halCfg->uartCfg[1]);
+            break;
+    }
+
+    // UART 3 Pin configuration
+    switch (halCfg->uartCfg[2])
+    {
+        case HAL_UART_CONFIG_NONE:
+            availableGpio_D |= HAL_GPIO_BIT(0)
+                             | HAL_GPIO_BIT(1)
+                             | HAL_GPIO_BIT(2)
+                             | HAL_GPIO_BIT(3);
+            break;
+        case HAL_UART_CONFIG_DATA:
+            // use UART3 TXD, RXD
+            availableGpio_D |= HAL_GPIO_BIT(2)
+                             | HAL_GPIO_BIT(3);
+            break;
+        case HAL_UART_CONFIG_FLOWCONTROL:
+             // use UART3 TXD, RXD, CTS, RTS
+            break;
+        case HAL_UART_CONFIG_MODEM:
+        default:
+            HAL_ASSERT(FALSE,
+                    "Invalid Uart3 Configuration (%d).",
+                    halCfg->uartCfg[2]);
+            break;
+    }
+
+    // I2S
+    altMux |= CFG_REGS_DAI_I2S;
+    if (halCfg->i2sCfg.di0Used || halCfg->i2sCfg.di1Used ||
+        halCfg->i2sCfg.di2Used || halCfg->i2sCfg.doUsed)
+    {
+        if (!halCfg->i2sCfg.di0Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(11);
+        }
+        if (!halCfg->i2sCfg.di1Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(12);
+        }
+        if (halCfg->i2sCfg.di2Used)
+        {
+            HAL_ASSERT((halCfg->keyInMask & 0x4) == 0, "Keyin 2 uses I2S DI2");
+            altMux |= CFG_REGS_I2S_DI_2_I2S_DI_2;
+        }
+        else
+        {
+            altMux |= CFG_REGS_I2S_DI_2_KEYIN_2;
+            if ((halCfg->keyInMask & 0x4) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(2);
+            }
+        }
+        if (!halCfg->i2sCfg.doUsed)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(13);
+        }
+    }
+    else
+    {
+        availableGpio_A |= HAL_GPIO_BIT(9)
+                         | HAL_GPIO_BIT(10)
+                         | HAL_GPIO_BIT(11)
+                         | HAL_GPIO_BIT(12)
+                         | HAL_GPIO_BIT(13);
+    }
+
+    // I2S2
+    if (halCfg->i2s2Cfg.di0Used || halCfg->i2s2Cfg.di1Used ||
+        halCfg->i2s2Cfg.di2Used || halCfg->i2s2Cfg.doUsed)
+    {
+        HAL_ASSERT(!halCfg->emacUsed, "EMAC uses I2S2 pins");
+        if (!halCfg->i2s2Cfg.di0Used)
+        {
+            availableGpio_D |= HAL_GPIO_BIT(13);
+        }
+        if (!halCfg->i2s2Cfg.di1Used)
+        {
+            availableGpio_D |= HAL_GPIO_BIT(14);
+        }
+        if (!halCfg->i2s2Cfg.doUsed)
+        {
+            availableGpio_D |= HAL_GPIO_BIT(15);
+        }
+    }
+    else
+    {
+        availableGpio_D |= HAL_GPIO_BIT(11)
+                         | HAL_GPIO_BIT(12)
+                         | HAL_GPIO_BIT(13)
+                         | HAL_GPIO_BIT(14)
+                         | HAL_GPIO_BIT(15);
+    }
+
+    // LPS CO1
+    if (halCfg->useLpsCo1)
+    {
+        HAL_ASSERT((halCfg->keyInMask & 0x10) == 0, "Keyin 4 uses LPS_CO1");
+        altMux |= CFG_REGS_LPSCO_1_LPSCO_1;
+    }
+    else
+    {
+        altMux |= CFG_REGS_LPSCO_1_KEYIN_4;
+        if ((halCfg->keyInMask & 0x10) == 0)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(7);
+        }
+    }
+
+    // TCO
+    if (halCfg->usedTco & 0x1)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x1) == 0, "Keyout 0 uses TCO0");
+        altMux |= CFG_REGS_TCO_0_TCO_0;
+    }
+    else
+    {
+        altMux |= CFG_REGS_TCO_0_KEYOUT_0;
+        if ((halCfg->keyOutMask & 0x1) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(3);
+        }
+    }
+
+    if (halCfg->usedTco & 0x2)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x2) == 0, "Keyout 1 uses TCO1");
+        altMux |= CFG_REGS_TCO_1_TCO_1;
+    }
+    else
+    {
+        altMux |= CFG_REGS_TCO_1_KEYOUT_1;
+        if ((halCfg->keyOutMask & 0x2) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(4);
+        }
+    }
+
+    if (halCfg->usedTco & 0x4)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x4) == 0, "Keyout 2 uses TCO2");
+        altMux |= CFG_REGS_TCO_2_TCO_2;
+    }
+    else
+    {
+        altMux |= CFG_REGS_TCO_2_KEYOUT_2;
+        if ((halCfg->keyOutMask & 0x4) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(5);
+        }
+    }
+
+    // PWM
+    if (halCfg->pwmCfg.pwtUsed)
+    {
+        HAL_ASSERT((halCfg->keyInMask & 0x20) == 0, "Keyin 5 uses PWT");
+        altMux |= CFG_REGS_GPO_0_PWT;
+    }
+    else if (halCfg->keyInMask & 0x20)
+    {
+        altMux |= CFG_REGS_GPO_0_KEYIN_5;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_0_GPO_0;
+        availableGpo_A |= HAL_GPO_BIT(0);
+    }
+
+    if (halCfg->pwmCfg.lpgUsed)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x20) == 0, "Keyout 5 uses LPG");
+        altMux |= CFG_REGS_GPO_1_LPG;
+    }
+    else if (halCfg->keyOutMask & 0x20)
+    {
+        altMux |= CFG_REGS_GPO_1_KEYOUT_5;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_1_GPO_1;
+        availableGpo_A |= HAL_GPO_BIT(1);
+    }
+
+    if (halCfg->pwmCfg.pwl1Used)
+    {
+        HAL_ASSERT(!halCfg->useClk32k, "Clk 32k uses PWL1");
+        altMux |= CFG_REGS_GPO_2_PWL_1;
+    }
+    else if (halCfg->useClk32k)
+    {
+        // Default to GPO low output
+        // 32K clock will be enabled per request
+        //altMux |= CFG_REGS_GPO_2_CLK_32K;
+        altMux |= CFG_REGS_GPO_2_GPO_2;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_2_GPO_2;
+        availableGpo_A |= HAL_GPO_BIT(2);
+    }
+
+    // Clock out and host clock
+    if (halCfg->clkOutUsed)
+    {
+        HAL_ASSERT(!halCfg->hostClkUsed, "HST_CLK uses CLK_OUT pin");
+        altMux |= CFG_REGS_CLK_OUT_CLK_OUT;
+    }
+    else if (halCfg->hostClkUsed)
+    {
+        altMux |= CFG_REGS_CLK_OUT_HST_CLK;
+    }
+    else
+    {
+        altMux |= CFG_REGS_CLK_OUT_HST_CLK;
+        availableGpo_A |= HAL_GPO_BIT(8);
+    }
+
+    // SPI
+    if (halCfg->spiCfg[0].cs0Used || halCfg->spiCfg[0].cs1Used ||
+        halCfg->spiCfg[0].cs2Used)
+    {
+        HAL_ASSERT(!(halCfg->modemSpiCfg[0].cs0Used ||
+                     halCfg->modemSpiCfg[0].cs1Used ||
+                     halCfg->modemSpiCfg[0].cs2Used), "Modem SPI1 is in use");
+        altMux |= CFG_REGS_AP_SPI1_AP_SPI1;
+        if (!halCfg->spiCfg[0].cs0Used)
+        {
+            availableGpio_C |= HAL_GPIO_BIT(22);
+        }
+        if (!halCfg->spiCfg[0].cs1Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(17);
+        }
+        if (halCfg->spiCfg[0].cs2Used)
+        {
+            HAL_ASSERT((halCfg->keyInMask & 0x2) == 0, "Keyin 1 uses SPI1 CS2");
+            altMux |= CFG_REGS_SPI1_CS_2_SPI1_CS_2;
+        }
+        else
+        {
+            altMux |= CFG_REGS_SPI1_CS_2_KEYIN_1;
+            if ((halCfg->keyInMask & 0x2) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(1);
+            }
+        }
+        if (!halCfg->spiCfg[0].di0Used)
+        {
+            availableGpio_C |= HAL_GPIO_BIT(23);
+        }
+        if (!halCfg->spiCfg[0].di1Used)
+        {
+            availableGpio_C |= HAL_GPIO_BIT(24);
+        }
+    }
+    else // AP SPI1 unused
+    {
+        altMux |= CFG_REGS_AP_SPI1_BB_SPI1;
+        if (halCfg->modemSpiCfg[0].cs0Used || halCfg->modemSpiCfg[0].cs1Used ||
+            halCfg->modemSpiCfg[0].cs2Used)
+        {
+            if (!halCfg->modemSpiCfg[0].cs0Used)
+            {
+                availableGpio_C |= HAL_GPIO_BIT(22);
+            }
+            if (!halCfg->modemSpiCfg[0].cs1Used)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(17);
+            }
+            if (!halCfg->modemSpiCfg[0].di0Used)
+            {
+                availableGpio_C |= HAL_GPIO_BIT(23);
+            }
+            if (!halCfg->modemSpiCfg[0].di1Used)
+            {
+                availableGpio_C |= HAL_GPIO_BIT(24);
+            }
+        }
+        else
+        {
+            availableGpio_A |= HAL_GPIO_BIT(17);
+            availableGpio_C |= HAL_GPIO_BIT(21)
+                             | HAL_GPIO_BIT(22)
+                             | HAL_GPIO_BIT(23)
+                             | HAL_GPIO_BIT(24);
+            if ((halCfg->keyInMask & 0x2) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(1);
+            }
+        }
+    }
+    if (halCfg->spiCfg[1].cs0Used || halCfg->spiCfg[1].cs1Used)
+    {
+        if (!halCfg->spiCfg[1].cs0Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(5);
+        }
+        if (halCfg->spiCfg[1].cs1Used)
+        {
+            HAL_ASSERT((halCfg->keyInMask & 0x8) == 0, "Keyin 3 uses SPI2 CS1");
+            altMux |= CFG_REGS_KEYIN_3_SPI2_CS_1;
+        }
+        else
+        {
+            altMux |= CFG_REGS_KEYIN_3_KEYIN_3;
+            if ((halCfg->keyInMask & 0x8) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(6);
+            }
+        }
+        if (!halCfg->spiCfg[1].di0Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(3);
+        }
+        if (!halCfg->spiCfg[1].di1Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(4);
+        }
+    }
+    else // AP SPI2 unused
+    {
+        availableGpio_A |= HAL_GPIO_BIT(2)
+                         | HAL_GPIO_BIT(3)
+                         | HAL_GPIO_BIT(4)
+                         | HAL_GPIO_BIT(5);
+        if ((halCfg->keyInMask & 0x8) == 0)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(6);
+        }
+    }
+
+    // Standalone keyin/out
+    if ((halCfg->keyInMask & 0x1) == 0)
+    {
+        availableGpio_B |= HAL_GPIO_BIT(0);
+    }
+
+    // SDMMC
+    if (!halCfg->sdmmcCfg.sdmmcUsed)
+    {
+        availableGpio_C |= HAL_GPIO_BIT(9)
+                         | HAL_GPIO_BIT(10)
+                         | HAL_GPIO_BIT(11)
+                         | HAL_GPIO_BIT(12)
+                         | HAL_GPIO_BIT(13)
+                         | HAL_GPIO_BIT(14);
+    }
+    if (!halCfg->sdmmcCfg.sdmmc2Used)
+    {
+        availableGpio_C |= HAL_GPIO_BIT(15)
+                         | HAL_GPIO_BIT(16);
+        if (!halCfg->sdio2Uart1Used)
+        {
+            availableGpio_C |= HAL_GPIO_BIT(17)
+                             | HAL_GPIO_BIT(18)
+                             | HAL_GPIO_BIT(19)
+                             | HAL_GPIO_BIT(20);
+        }
+    }
+    HAL_ASSERT(!(parallelNandUsed && halCfg->sdmmcCfg.sdmmc3Used),
+        "Parallel NAND uses SDMMC3 pins");
+
+    // SDIO2_UART1
+    if (halCfg->sdio2Uart1Used)
+    {
+        HAL_ASSERT(halCfg->uartCfg[0] == HAL_UART_CONFIG_NONE,
+            "UART1 has been configured on UART1 pins");
+        altMux2 |= CFG_REGS_UART1_SDIO2_UART1;
+    }
+    else
+    {
+        altMux2 |= CFG_REGS_UART1_SDIO2_SDIO2;
+    }
+
+    // EMAC
+    if (halCfg->emacUsed)
+    {
+        altMux2 |= CFG_REGS_MAC_EN_ENABLE;
+    }
+    else
+    {
+        altMux2 |= CFG_REGS_MAC_EN_DISABLE;
+    }
+
+    // SIM
+    if (!hal_BoardSimUsed(2))
+    {
+        availableGpio_C |= HAL_GPIO_BIT(25)
+                         | HAL_GPIO_BIT(26)
+                         | HAL_GPIO_BIT(27);
+    }
+
+    if (hal_BoardSimUsed(3))
+    {
+        HAL_ASSERT(!halCfg->emacUsed, "EMAC uses SIM3 pins");
+    }
+    else
+    {
+        if (!halCfg->emacUsed)
+        {
+            availableGpio_C |= HAL_GPIO_BIT(28)
+                             | HAL_GPIO_BIT(29)
+                             | HAL_GPIO_BIT(30);
+        }
+    }
+
+    UINT32 gpioMask;
+    // GPIO_C mask check
+    gpioMask = ~availableGpio_C & halCfg->usedGpio_C;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO C are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_C & halCfg->noConnectGpio_C;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO C declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_C & halCfg->noConnectGpio_C;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO C declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_C &
+               (~halCfg->usedGpio_C & ~halCfg->noConnectGpio_C);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO C declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPIO_A mask check
+    gpioMask = ~availableGpio_A & halCfg->usedGpio_A;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO A are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_A & halCfg->noConnectGpio_A;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO A declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_A & halCfg->noConnectGpio_A;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO A declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_A &
+               (~halCfg->usedGpio_A & ~halCfg->noConnectGpio_A);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO A declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPIO_B mask check
+    gpioMask = ~availableGpio_B & halCfg->usedGpio_B;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO B are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_B & halCfg->noConnectGpio_B;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO B declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_B & halCfg->noConnectGpio_B;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO B declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_B &
+               (~halCfg->usedGpio_B & ~halCfg->noConnectGpio_B);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO B declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPIO_D mask check
+    gpioMask = ~availableGpio_D & halCfg->usedGpio_D;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO D are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_D & halCfg->noConnectGpio_D;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO D declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_D & halCfg->noConnectGpio_D;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO D declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_D &
+               (~halCfg->usedGpio_D & ~halCfg->noConnectGpio_D);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO D declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPIO_E mask check
+    gpioMask = ~availableGpio_E & halCfg->usedGpio_E;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO E are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_E & halCfg->noConnectGpio_E;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO E declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_E & halCfg->noConnectGpio_E;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO E declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_E &
+               (~halCfg->usedGpio_E & ~halCfg->noConnectGpio_E);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO E declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPO_A mask check
+    gpioMask = ~availableGpo_A & halCfg->usedGpo_A;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPO A are not available (0x%x)",
+               gpioMask);
+
+#endif // !FPGA
+
+    // Set IO drive
+    hwp_configRegs->IO_Drive1_Select = halCfg->ioDrive.select1;
+    hwp_configRegs->IO_Drive2_Select = halCfg->ioDrive.select2;
+
+    // Set the not connected ones as output and drive 0
+    // But keep boot mode GPIOs as input to avoid current leakage
+    noConnectMask_C = halCfg->noConnectGpio_C & ~bootModeGpio_C;
+    noConnectMask_A = halCfg->noConnectGpio_A & ~bootModeGpio_A;
+    noConnectMask_B = halCfg->noConnectGpio_B & ~bootModeGpio_B;
+    noConnectMask_D = halCfg->noConnectGpio_D & ~bootModeGpio_D;
+    noConnectMask_E = halCfg->noConnectGpio_E & ~bootModeGpio_E;
+
+    hwp_gpio->gpio_clr = noConnectMask_C;
+    hwp_gpio->gpio_oen_set_out = noConnectMask_C;
+
+    hwp_apGpioA->gpio_clr = noConnectMask_A;
+    hwp_apGpioA->gpio_oen_set_out = noConnectMask_A;
+
+    hwp_apGpioB->gpio_clr = noConnectMask_B;
+    hwp_apGpioB->gpio_oen_set_out = noConnectMask_B;
+
+    hwp_apGpioD->gpio_clr = noConnectMask_D;
+    hwp_apGpioD->gpio_oen_set_out = noConnectMask_D;
+
+    hwp_apGpioE->gpio_clr = noConnectMask_E;
+    hwp_apGpioE->gpio_oen_set_out = noConnectMask_E;
+
+    // Init GPO_A values
+    gpoClr_A = availableGpo_A;
+    if (halCfg->useClk32k)
+    {
+        // Init 32K clock pin to low (by setting up GPO)
+        gpoClr_A |= HAL_GPO_BIT(2);
+    }
+#ifdef _TGT_AP_GPIO_USBID_CTRL
+    // if GPO_1 used for usb id, it should be high
+    gpoClr_A &= ~(HAL_GPO_BIT(1));
+#endif
+    hwp_apGpioA->gpo_clr = gpoClr_A;
+
+    // Configure MUX after initializing all the GPO pins
+    // (GPIO pins are in input mode by default)
+
+    // Set GPIO mode
+    hwp_configRegs->BB_GPIO_Mode = availableGpio_C;
+    hwp_configRegs->AP_GPIO_A_Mode = availableGpio_A;
+    hwp_configRegs->AP_GPIO_B_Mode = availableGpio_B;
+    hwp_configRegs->AP_GPIO_D_Mode = availableGpio_D;
+    hwp_configRegs->AP_GPIO_E_Mode = availableGpio_E;
+    // Set Alt Mux configuration
+    hwp_configRegs->Alt_mux_select = altMux;
+    hwp_configRegs->Alt_mux_select2 = altMux2;
+
+    // --------------------------------------------------
+    // As of now, all connected GPIOs, which are as GPIO
+    // or not used at all but connected are configured as
+    // GPIOs in input mode, except for Gouda reset pins
+    // --------------------------------------------------
+
+}
+
+
+// =============================================================================
+// hal_BoardSetup
+// -----------------------------------------------------------------------------
+/// Apply board dependent configuration to HAL
+/// @param halCfg Pointer to HAL configuration structure (from the target
+/// module).
+// ============================================================================
+//PROTECTED VOID hal_BoardSetup(CONST HAL_CFG_CONFIG_T* halCfg)
+PUBLIC INT32 hal_BoardSetup(INT8 run_mode)
+{
+    g_bootBootMode = rda_hwcfg_get();
+    hal_BoardSetupGeneral(&hal_cfg);
+
+    if(g_halConfigError)
+        return CMD_RET_FAILURE;
+    else
+        return CMD_RET_SUCCESS;
+}
diff --git a/board/rda/rda8810e/u-boot-spl.lds b/board/rda/rda8810e/u-boot-spl.lds
new file mode 100644
index 0000000000..afe35fd2a8
--- /dev/null
+++ b/board/rda/rda8810e/u-boot-spl.lds
@@ -0,0 +1,35 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00100100;
+	. = ALIGN(4);
+	.text :
+	{
+		__start = .;
+		arch/arm/cpu/armv7/start.o (.text)
+			*(.text)
+	}
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+	. = ALIGN(4);
+	.data : {
+		*(.data)
+	}
+	. = ALIGN(4);
+	. = .;
+	. = ALIGN(4);
+	__image_copy_end = .;
+	_end = .;
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+		ASSERT((ABSOLUTE(__bss_end__) < 0x00110000), \
+			"too big data in spl, don't exceed intrenal ram");
+	}
+}
diff --git a/board/rda/rda8810h/Makefile b/board/rda/rda8810h/Makefile
new file mode 100644
index 0000000000..7412489b30
--- /dev/null
+++ b/board/rda/rda8810h/Makefile
@@ -0,0 +1,82 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS-y	+= clock_config.o clock.o ddr3.o
+else
+COBJS-$(CONFIG_MACH_RDA8810H) += hal_config.o
+endif
+
+RDA_TARGET_DEF_FILE := $(ANDROID_BUILD_TOP)/$(RDA_TARGET_DEVICE_DIR)/target.def
+RDA_GET_MAKEFILE_VAR_FUNC = $(strip $(shell sed -n 's/^[ 	]*$(1)[ 	]*[?:]\?=\([^\#]\+\)\#*.*$$/\1/p' $(2)))
+
+NUMBER_OF_SIM := $(call RDA_GET_MAKEFILE_VAR_FUNC,NUMBER_OF_SIM,$(RDA_TARGET_DEF_FILE))
+ifeq ($(NUMBER_OF_SIM),)
+$(error Failed to get NUMBER_OF_SIM in $(RDA_TARGET_DEF_FILE))
+endif
+
+USER_SIM_ORDER := $(call RDA_GET_MAKEFILE_VAR_FUNC,USER_SIM_ORDER,$(RDA_TARGET_DEF_FILE))
+ifeq ($(USER_SIM_ORDER),)
+$(error Failed to get USER_SIM_ORDER in $(RDA_TARGET_DEF_FILE))
+endif
+
+NULL_STRING :=
+SPACE := ${NULL_STRING} # end of the line
+COMMA := ,
+TGT_SIM_ORDER := $(foreach SIM,$(USER_SIM_ORDER),$(SIM)$(COMMA))
+TGT_SIM_ORDER := $(subst ${SPACE},,${TGT_SIM_ORDER})
+
+CPPFLAGS_board/$(BOARDDIR)/hal_config.o += -I$(TOPDIR)/board/$(VENDOR)/common/include -DTGT_SIM_ORDER=$(TGT_SIM_ORDER) -DNUMBER_OF_SIM=$(NUMBER_OF_SIM)
+
+ifeq ($(strip $(TARGET_TABLET_MODE)),true)
+CPPFLAGS_board/$(BOARDDIR)/clock.o += -DTARGET_TABLET_MODE
+endif
+
+COBJS   := $(COBJS-y)
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak *~ .depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/rda/rda8810h/clock.c b/board/rda/rda8810h/clock.c
new file mode 100644
index 0000000000..45caa4177d
--- /dev/null
+++ b/board/rda/rda8810h/clock.c
@@ -0,0 +1,1329 @@
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/rda_iomap.h>
+#include <asm/io.h>
+#include <asm/arch/reg_sysctrl.h>
+#include <asm/arch/hwcfg.h>
+#include <asm/arch/ispi.h>
+#include <asm/arch/rda_sys.h>
+#include "clock_config.h"
+#include "debug.h"
+#include "ddr3.h"
+#include "tgt_ap_clock_config.h"
+
+#if (PMU_VBUCK1_VAL < 0 || PMU_VBUCK1_VAL > 15)
+#error "Invalid PMU_VBUCK1_VAL"
+#endif
+#if (PMU_VBUCK3_VAL < 0 || PMU_VBUCK3_VAL > 15)
+#error "Invalid PMU_VBUCK3_VAL"
+#endif
+#ifdef PMU_VBUCK4_VAL
+#if (PMU_VBUCK4_VAL < 0 || PMU_VBUCK4_VAL > 15)
+#error "Invalid PMU_VBUCK4_VAL"
+#endif
+#endif
+
+//#define DO_SIMPLE_DDR_TEST
+//#define DO_DDR_PLL_DEBUG
+
+enum {
+	AP_CPU_CLK_IDX = 0,
+	AP_BUS_CLK_IDX,
+	AP_MEM_CLK_IDX,
+	AP_USB_CLK_IDX,
+};
+
+static int pll_enabled(int idx)
+{
+	if ((hwp_sysCtrlAp->Cfg_Pll_Ctrl[idx] &
+			(SYS_CTRL_AP_AP_PLL_ENABLE_MASK |
+			 SYS_CTRL_AP_AP_PLL_LOCK_RESET_MASK)) ==
+			(SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE |
+			 SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET))
+		return 1;
+	else
+		return 0;
+}
+
+static int usb_in_use = 0;
+
+static void check_usb_usage(void)
+{
+	unsigned int mask = SYS_CTRL_AP_BUS_SEL_FAST_SLOW |
+		SYS_CTRL_AP_PLL_LOCKED_BUS_MASK |
+		SYS_CTRL_AP_PLL_LOCKED_USB_MASK;
+	unsigned int reg = SYS_CTRL_AP_BUS_SEL_FAST_FAST |
+		SYS_CTRL_AP_PLL_LOCKED_BUS_LOCKED |
+		SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED;
+
+	if ((hwp_sysCtrlAp->Sel_Clock & mask) == reg &&
+			pll_enabled(AP_BUS_CLK_IDX) &&
+			pll_enabled(AP_USB_CLK_IDX))
+		usb_in_use = 1;
+	else
+		usb_in_use = 0;
+}
+
+#ifdef DO_SIMPLE_DDR_TEST
+
+void mem_test_write(void)
+{
+	volatile unsigned int *addr;
+
+	printf("write ddr test!!!!!!\n");
+
+ 	addr = (volatile unsigned int *)(0x80000000);
+	while((unsigned int)addr < 0x81000000)
+	{
+		*addr = (unsigned int )addr;
+		addr++;
+	}
+}
+
+void mem_test_read(void)
+{
+	volatile unsigned int *addr;
+
+	printf("read ddr!!!!\n");
+
+	addr = (volatile unsigned int *)(0x80000000);
+
+	while((unsigned int)addr < 0x81000000)
+	{
+		if (*addr != (unsigned int)addr){
+			int i = 0;
+			
+			printf("test error!!!!!, addr = %x\n", (unsigned int)addr);
+			for (i = 0; i < 80;i++){
+				printf("%x ", *(addr + i));
+				if ((i % 4) == 0)
+					printf("\n");
+			}
+
+			return;
+		}
+
+		addr++;
+	}
+	printf("test complete!\n");
+}
+
+#endif /* DO_SIMPLE_DDR_TEST */
+
+#ifndef CONFIG_RDA_FPGA
+
+// PMU bit fields
+#define PMU_SET_BITFIELD(dword, bitfield, value) \
+	(((dword) & ~(bitfield ## _MASK)) | (bitfield(value)))
+
+#define RDA_PMU_VBUCK1_BIT_ACT(n)        (((n)&0xf)<<12)
+#define RDA_PMU_VBUCK1_BIT_ACT_MASK      (0xf<<12)
+#define RDA_PMU_VBUCK1_BIT_ACT_SHIFT     (12)
+
+#define RDA_PMU_VBUCK4_BIT_ACT_SHIFT     (4)
+#define RDA_PMU_VBUCK4_BIT_ACT_MASK      (0xf<<4)
+#define RDA_PMU_VBUCK4_BIT_ACT(n)        (((n)&0xf)<<4)
+
+#define RDA_PMU_VBUCK3_BIT_ACT_SHIFT     (12)
+#define RDA_PMU_VBUCK3_BIT_ACT_MASK      (0xf<<12)
+#define RDA_PMU_VBUCK3_BIT_ACT(n)        (((n)&0xf)<<12)
+
+struct pll_freq {
+	UINT32 freq_mhz;
+	UINT16 major;
+	UINT16 minor;
+	UINT16 with_div;
+	UINT16 div;
+};
+
+typedef enum {
+	PLL_REG_CPU_BASE = 0x00,
+	PLL_REG_BUS_BASE = 0x20,
+	PLL_REG_MEM_BASE = 0x60,
+	PLL_REG_USB_BASE = 0x80,
+} PLL_REG_BASE_INDEX_t;
+
+typedef enum {
+	PLL_REG_OFFSET_01H = 1,
+	PLL_REG_OFFSET_02H = 2,
+	PLL_REG_OFFSET_DIV = 3,
+	PLL_REG_OFFSET_04H = 4,
+	PLL_REG_OFFSET_MAJOR = 5,
+	PLL_REG_OFFSET_MINOR = 6,
+	PLL_REG_OFFSET_07H = 7,
+} PLL_REG_OFFSET_INDEX_t;
+
+static struct pll_freq pll_freq_table[] = {
+	/* MHz Major   Minor   div */
+	{1600, 0x7B13, 0xB138, 0, 0x0000},
+	{1200, 0x5C4E, 0xC4EC, 0, 0x0000},
+	{1000, 0x4BEC, 0x4EC4, 0, 0x0000},
+	{ 988, 0x4000, 0x0000, 0, 0x0000},
+	{ 800, 0x3C00, 0x0000, 0, 0x0000},
+	{ 600, 0x2E27, 0x6274, 0, 0x0000},
+	{ 533, 0x2900, 0x0000, 1, 0xc797},
+	{ 519, 0x27EC, 0x4EC4, 1, 0xc797},
+	{ 500, 0x2676, 0x2762, 1, 0xc797},
+	{ 480, 0x24EC, 0x4EC4, 0, 0x0000},
+	{ 455, 0x2300, 0x0000, 1, 0xC297},
+	{ 416, 0x1FD8, 0x0000, 1, 0xCB97},
+	/* 800M div 1, PLL:800M  DDR:400M for mem pll only */
+	{ 400, 0x1F00, 0x0000, 1, 0xCA97},
+	{ 355, 0x369D, 0x89D8, 1, 0xD597},
+	/* 702M div 1, PLL:702M  DDR:351M for mem pll only */
+	{ 351, 0x3600, 0x0000, 1, 0xD297},
+	{ 333, 0x333B, 0x13B1, 1, 0xD097},
+	/* 624M div 1, PLL:624M  DDR:312M for mem pll only */
+	{ 312, 0x3000, 0x0000, 1, 0xD897},
+	{ 290, 0x2C9D, 0x89D8, 1, 0xE097},
+	/* 520M div 1, PLL:520M  DDR:260M for mem pll only */
+	{ 260, 0x2800, 0x0000, 1, 0xE897},
+	/* 800M div 2, PLL:400M  DDR:200M for mem pll only */
+	{ 200, 0x3D89, 0xD89C, 1, 0x0006},
+	/* DDR:156M for mem pll only */
+	{ 156, 0x3000, 0x0000, 1, 0x0006},
+	/* 800M div 4, PLL:200M  DDR:100M for mem pll only */
+	{ 100, 0x3D89, 0xD89C, 1, 0x0005},
+	/* 800M div 8, PLL:100M  DDR:50M for mem pll only */
+	{  50, 0x3D89, 0xD89C, 1, 0x0004},
+};
+
+static const struct clock_config *g_clock_config;
+
+#ifdef DO_DDR_PLL_DEBUG
+static struct clock_config clock_debug_config;
+static UINT32 ddrfreq = 400, ddr32bit = 0;
+#endif
+
+static void sys_shutdown_pll(void)
+{
+	int i;
+
+	hwp_sysCtrlAp->REG_DBG = AP_CTRL_PROTECT_UNLOCK;
+
+	if (usb_in_use) {
+		hwp_sysCtrlAp->Sel_Clock = SYS_CTRL_AP_SLOW_SEL_RF_RF
+			| SYS_CTRL_AP_CPU_SEL_FAST_SLOW
+			| SYS_CTRL_AP_BUS_SEL_FAST_FAST
+			| SYS_CTRL_AP_TIMER_SEL_FAST_FAST;
+	} else {
+		hwp_sysCtrlAp->Sel_Clock = SYS_CTRL_AP_SLOW_SEL_RF_RF
+			| SYS_CTRL_AP_CPU_SEL_FAST_SLOW
+			| SYS_CTRL_AP_BUS_SEL_FAST_SLOW
+			| SYS_CTRL_AP_TIMER_SEL_FAST_FAST;
+	}
+
+	for (i = 0; i < 3; i++) {
+		/* In download mode, rom code has been set ap bus*/
+		if (usb_in_use) {
+			if (i == AP_BUS_CLK_IDX) // ap bus
+				continue;
+		}
+		hwp_sysCtrlAp->Cfg_Pll_Ctrl[i] =
+			SYS_CTRL_AP_AP_PLL_ENABLE_POWER_DOWN |
+			SYS_CTRL_AP_AP_PLL_LOCK_RESET_RESET;
+	}
+}
+
+static void sys_setup_pll(void)
+{
+	int i;
+	UINT32 mask;
+	UINT32 locked;
+	int cnt = 10; //10us, according to IC, the pll must be locked
+
+	hwp_sysCtrlAp->REG_DBG = AP_CTRL_PROTECT_UNLOCK;
+
+	for (i = 0; i < 3; i++) {
+		/* In download mode, rom code has been set ap bus*/
+		if (usb_in_use) {
+			if (i == AP_BUS_CLK_IDX) // ap bus
+				continue;
+		}
+
+		if (AP_MEM_CLK_IDX == i)
+			hwp_sysCtrlAp->Cfg_Pll_Ctrl[i] =
+				SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE |
+				SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET |
+				SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(1)|
+				SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(30);
+		else
+			hwp_sysCtrlAp->Cfg_Pll_Ctrl[i] =
+				SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE |
+				SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET |
+				SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(6)|
+				SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(30);
+	}
+
+	mask = SYS_CTRL_AP_PLL_LOCKED_CPU_MASK
+	    | SYS_CTRL_AP_PLL_LOCKED_BUS_MASK
+	    | SYS_CTRL_AP_PLL_LOCKED_MEM_MASK
+	    //| SYS_CTRL_AP_PLL_LOCKED_USB_MASK
+	    ;
+	locked = SYS_CTRL_AP_PLL_LOCKED_CPU_LOCKED
+	    | SYS_CTRL_AP_PLL_LOCKED_BUS_LOCKED
+	    | SYS_CTRL_AP_PLL_LOCKED_MEM_LOCKED
+	    //| SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED
+	    ;
+
+	while (((hwp_sysCtrlAp->Sel_Clock & mask) != locked) && cnt) {
+		udelay(1);
+		cnt--;
+	}
+	if (cnt == 0) {
+		printf("WARNING, cannot lock cpu/bus/mem pll 0x%08x ",
+			hwp_sysCtrlAp->Sel_Clock);
+		printf("but we run anyway ...\n");
+	}
+
+	for (i = 0; i < 3; i++) {
+		hwp_sysCtrlAp->Cfg_Pll_Ctrl[i] |=
+		    SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_ENABLE;
+	}
+
+	hwp_sysCtrlAp->Sel_Clock = SYS_CTRL_AP_SLOW_SEL_RF_RF
+	    | SYS_CTRL_AP_CPU_SEL_FAST_FAST
+	    | SYS_CTRL_AP_BUS_SEL_FAST_FAST
+	    | SYS_CTRL_AP_TIMER_SEL_FAST_FAST;
+}
+
+static void sys_setup_clk(void)
+{
+	// Disable some power-consuming clocks
+#ifdef CONFIG_VPU_TEST
+	hwp_sysCtrlAp->Clk_APO_Enable = SYS_CTRL_AP_ENABLE_APOC_VPU;
+	//hwp_sysCtrlAp->Clk_MEM_Enable = SYS_CTRL_AP_ENABLE_MEM_VPU;
+#else
+	hwp_sysCtrlAp->Clk_APO_Disable = SYS_CTRL_AP_DISABLE_APOC_VPU;
+	//hwp_sysCtrlAp->Clk_MEM_Disable = SYS_CTRL_AP_DISABLE_MEM_VPU;
+#endif
+
+	// Init clock gating mode
+	hwp_sysCtrlAp->Clk_CPU_Mode = 0;
+#ifdef CONFIG_VPU_TEST
+	hwp_sysCtrlAp->Clk_AXI_Mode = SYS_CTRL_AP_MODE_AXI_DMA_MANUAL | SYS_CTRL_AP_MODE_APB0_CONF_MANUAL;
+#else
+	hwp_sysCtrlAp->Clk_AXI_Mode = SYS_CTRL_AP_MODE_AXI_DMA_MANUAL;
+#endif
+	hwp_sysCtrlAp->Clk_AXIDIV2_Mode = 0;
+	hwp_sysCtrlAp->Clk_GCG_Mode = SYS_CTRL_AP_MODE_GCG_GOUDA_MANUAL
+				| SYS_CTRL_AP_MODE_GCG_CAMERA_MANUAL;
+	hwp_sysCtrlAp->Clk_AHB1_Mode = 0;
+	hwp_sysCtrlAp->Clk_APB1_Mode = 0;
+	hwp_sysCtrlAp->Clk_APB2_Mode = 0;
+#ifdef CONFIG_VPU_TEST
+	hwp_sysCtrlAp->Clk_MEM_Mode = SYS_CTRL_AP_MODE_CLK_MEM_MANUAL;
+#else
+	hwp_sysCtrlAp->Clk_MEM_Mode = 0;
+#endif
+	//hwp_sysCtrlAp->Clk_APO_Mode = SYS_CTRL_AP_MODE_APOC_VPU_MANUAL;
+
+	// Init module frequency
+	hwp_sysCtrlAp->Cfg_Clk_AP_CPU = g_clock_config->CLK_CPU;
+	hwp_sysCtrlAp->Cfg_Clk_AP_AXI = g_clock_config->CLK_AXI;
+	hwp_sysCtrlAp->Cfg_Clk_AP_GCG = g_clock_config->CLK_GCG;
+
+	if (!usb_in_use) {
+		hwp_sysCtrlAp->Cfg_Clk_AP_AHB1 = g_clock_config->CLK_AHB1;
+	}
+
+	hwp_sysCtrlAp->Cfg_Clk_AP_APB1 = g_clock_config->CLK_APB1;
+	hwp_sysCtrlAp->Cfg_Clk_AP_APB2 = g_clock_config->CLK_APB2;
+	hwp_sysCtrlAp->Cfg_Clk_AP_MEM = g_clock_config->CLK_MEM;
+	hwp_sysCtrlAp->Cfg_Clk_AP_GPU = g_clock_config->CLK_GPU;
+	hwp_sysCtrlAp->Cfg_Clk_AP_VPU = g_clock_config->CLK_VPU;
+	hwp_sysCtrlAp->Cfg_Clk_AP_VOC = g_clock_config->CLK_VOC;
+	hwp_sysCtrlAp->Cfg_Clk_AP_SFLSH = g_clock_config->CLK_SFLSH;
+}
+
+static void print_sys_reg(char *name, UINT32 value)
+{
+	printf("clk %s = %lx\n", name, value);
+}
+
+static void sys_dump_clk(void)
+{
+	print_sys_reg("CPU", hwp_sysCtrlAp->Cfg_Clk_AP_CPU);
+	print_sys_reg("AXI", hwp_sysCtrlAp->Cfg_Clk_AP_AXI);
+	print_sys_reg("GCG", hwp_sysCtrlAp->Cfg_Clk_AP_GCG);
+	print_sys_reg("AHB1", hwp_sysCtrlAp->Cfg_Clk_AP_AHB1);
+	print_sys_reg("APB1", hwp_sysCtrlAp->Cfg_Clk_AP_APB1);
+	print_sys_reg("APB2", hwp_sysCtrlAp->Cfg_Clk_AP_APB2);
+	print_sys_reg("MEM", hwp_sysCtrlAp->Cfg_Clk_AP_MEM);
+	print_sys_reg("GPU", hwp_sysCtrlAp->Cfg_Clk_AP_GPU);
+	print_sys_reg("VPU", hwp_sysCtrlAp->Cfg_Clk_AP_VPU);
+	print_sys_reg("VOC", hwp_sysCtrlAp->Cfg_Clk_AP_VOC);
+	print_sys_reg("SFLSH", hwp_sysCtrlAp->Cfg_Clk_AP_SFLSH);
+}
+
+static int pll_freq_set(UINT32 reg_base, UINT32 freq_mhz)
+{
+	int i;
+	struct pll_freq *freq;
+	unsigned int major, minor;
+	unsigned short value_02h;
+
+	/* find pll_freq */
+	for (i = 0; i < ARRAY_SIZE(pll_freq_table); i++) {
+		if (pll_freq_table[i].freq_mhz == freq_mhz)
+			break;
+	}
+	if (i >= ARRAY_SIZE(pll_freq_table)) {
+		printf("pll_freq_set, fail to find freq\n");
+		return -1;
+	}
+
+	freq = &pll_freq_table[i];
+	if (freq->with_div && (reg_base == PLL_REG_MEM_BASE)) {
+		ispi_reg_write(reg_base + PLL_REG_OFFSET_DIV,
+				freq->div);
+		// Calculate the real MEM PLL freq
+		freq_mhz *= (1 << (8 - (freq->div & 0x7)));
+	}
+	if (freq_mhz >= 800 || reg_base == PLL_REG_USB_BASE) {
+		value_02h = 0x0309;
+		// Div PLL freq by 2
+		minor = ((freq->major & 0xFFFF) << 14) |
+			((freq->minor >> 2) & 0x3FFF);
+		minor >>= 1;
+		// Recalculate the divider
+		major = (minor >> 14) & 0xFFFF;
+		minor = (minor << 2) & 0xFFFF;
+	} else {
+		value_02h = 0x0209;
+		major = freq->major;
+		minor = freq->minor;
+	}
+	if (reg_base == PLL_REG_USB_BASE)
+		value_02h ^= (1 << 8);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_02H, value_02h);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_MAJOR, major);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_MINOR, minor);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_07H, 0x0010);
+
+	return 0;
+}
+
+static void pll_setup_freq(void)
+{
+	pll_freq_set(PLL_REG_CPU_BASE, g_clock_config->PLL_FREQ_CPU);
+	// Always configure BUS PLL, even when it is being used
+	pll_freq_set(PLL_REG_BUS_BASE, g_clock_config->PLL_FREQ_BUS);
+	pll_freq_set(PLL_REG_MEM_BASE, g_clock_config->PLL_FREQ_MEM);
+	pll_freq_set(PLL_REG_USB_BASE, g_clock_config->PLL_FREQ_USB);
+}
+
+static void print_pll_freq(char *name, UINT32 value)
+{
+	printf("pll freq %s = %d\n", name, (int)value);
+}
+
+static void sys_dump_pll_freq(void)
+{
+	print_pll_freq("CPU", g_clock_config->PLL_FREQ_CPU);
+	print_pll_freq("BUS", g_clock_config->PLL_FREQ_BUS);
+	print_pll_freq("MEM", g_clock_config->PLL_FREQ_MEM);
+	//print_pll_freq("USB", g_clock_config->PLL_FREQ_USB);
+}
+
+static void pmu_get_efuse_dcdc(int buckVoltLow[])
+{
+	static const u8 setBitCnt[8] = { 0, 1, 1, 2, 1, 2, 2, 3, };
+	u16 dcdc;
+	int i;
+
+	ispi_reg_write(0x51, 0x02ed);
+	udelay(2000);
+	ispi_reg_write(0x51, 0x02fd);
+	dcdc = ispi_reg_read(0x52);
+	ispi_reg_write(0x51, 0x0200);
+
+	for (i = 0; i < 4; i++) {
+		buckVoltLow[i] = (setBitCnt[dcdc & 0x7] > 1);
+		dcdc >>= 3;
+	}
+}
+
+static void pmu_setup_init(void)
+{
+	u32 value;
+	int buck_volt_low[4] = { 0, };
+
+	rda_nand_iodrive_set();
+
+#ifdef CONFIG_RDA_PDL
+	enable_charger(0);
+#endif
+
+	ispi_open(1);
+
+	// Disable vibrator
+	ispi_reg_write(0x03, 0x9FFF);
+	// Enable bandgap chopper mode
+	ispi_reg_write(0x0F, 0x1E90);
+	// Enable high AC throttling
+	ispi_reg_write(0x12, 0x1218);
+#ifdef TARGET_TABLET_MODE
+	// Charger current (cc = 6, pre = 7)
+	ispi_reg_write(0x13, 0x1B70);
+#else
+	// Charger current (cc = 2, pre = 7)
+	ispi_reg_write(0x13, 0x1970);
+#endif
+	// Vcore DCDC freq
+	ispi_reg_write(0x2D, 0x96BA);
+	ispi_reg_write(0x2E, 0x12AA);
+	// Get efuse dcdc
+	pmu_get_efuse_dcdc(buck_volt_low);
+	// Vcore voltage
+	value = 0x9244;
+	value = PMU_SET_BITFIELD(value, RDA_PMU_VBUCK1_BIT_ACT,
+			PMU_VBUCK1_VAL +
+			((PMU_VBUCK1_VAL < 15 && buck_volt_low[0]) ? 1 : 0));
+	ispi_reg_write(0x2F, value);
+	// DDR PWM mode
+	ispi_reg_write(0x0D, 0x92D0);
+	// DDR voltage
+	value = 0xAAB5;
+	value = PMU_SET_BITFIELD(value, RDA_PMU_VBUCK3_BIT_ACT,
+			PMU_VBUCK3_VAL +
+			((PMU_VBUCK3_VAL < 15 && buck_volt_low[2]) ? 1 : 0));
+#ifdef PMU_VBUCK4_VAL
+	value = PMU_SET_BITFIELD(value, RDA_PMU_VBUCK4_BIT_ACT,
+			PMU_VBUCK4_VAL +
+			((PMU_VBUCK4_VAL < 15 && buck_volt_low[3]) ? 1 : 0));
+	value ^= RDA_PMU_VBUCK4_BIT_ACT(8);
+	// vBuck4 in low voltage range
+	ispi_reg_write(0x36, 0x6E45);
+#else
+	ispi_reg_write(0x36, 0x6E54);
+#endif
+	ispi_reg_write(0x2A, value);
+	// DDR power parameters
+	ispi_reg_write(0x4A, 0x96AA);
+	ispi_reg_write(0x4B, 0x96AA);
+
+	ispi_open(0);
+}
+
+static void setup_ddr_vtt(int vtt)
+{
+	printf("setup ddr vtt to %d\n", vtt);
+	ispi_reg_write(0x69, g_clock_config->DDR_TIMING_069H);
+}
+
+#if 0
+/*
+ * we initialize usb clock, but this won't cause the usb clock jitter,
+ * because wo don't setup the usb pll
+ */
+static void usb_clock_pre_init(void)
+{
+	ispi_reg_write(0x83, 0x72ef);
+	ispi_reg_write(0x89, 0x7400);
+}
+#endif
+
+static void pll_setup_init(void)
+{
+	setup_ddr_vtt(DDR_VTT_VAL);
+
+	if (g_clock_config->DDR_CHAN_1_VALID) {
+		ispi_reg_write(0x100, g_clock_config->DDR_TIMING_100H);
+		ispi_reg_write(0x101, g_clock_config->DDR_TIMING_101H);
+		ispi_reg_write(0x102, g_clock_config->DDR_TIMING_102H);
+		ispi_reg_write(0x103, g_clock_config->DDR_TIMING_103H);
+		ispi_reg_write(0x104, g_clock_config->DDR_TIMING_104H);
+		ispi_reg_write(0x105, g_clock_config->DDR_TIMING_105H);
+		ispi_reg_write(0x106, g_clock_config->DDR_TIMING_106H);
+		ispi_reg_write(0x107, g_clock_config->DDR_TIMING_107H);
+		ispi_reg_write(0x108, g_clock_config->DDR_TIMING_108H);
+		ispi_reg_write(0x109, g_clock_config->DDR_TIMING_109H);
+		ispi_reg_write(0x10A, g_clock_config->DDR_TIMING_10AH);
+		ispi_reg_write(0x10B, g_clock_config->DDR_TIMING_10BH);
+		ispi_reg_write(0x10C, g_clock_config->DDR_TIMING_10CH);
+		ispi_reg_write(0x10D, g_clock_config->DDR_TIMING_10DH);
+		ispi_reg_write(0x10E, g_clock_config->DDR_TIMING_10EH);
+		ispi_reg_write(0x10F, g_clock_config->DDR_TIMING_10FH);
+	}
+
+	if (g_clock_config->DDR_CHAN_2_VALID) {
+		ispi_reg_write(0x120, g_clock_config->DDR_TIMING_120H);
+		ispi_reg_write(0x121, g_clock_config->DDR_TIMING_121H);
+		ispi_reg_write(0x122, g_clock_config->DDR_TIMING_122H);
+		ispi_reg_write(0x123, g_clock_config->DDR_TIMING_123H);
+		ispi_reg_write(0x124, g_clock_config->DDR_TIMING_124H);
+		ispi_reg_write(0x125, g_clock_config->DDR_TIMING_125H);
+		ispi_reg_write(0x126, g_clock_config->DDR_TIMING_126H);
+		ispi_reg_write(0x127, g_clock_config->DDR_TIMING_127H);
+		ispi_reg_write(0x128, g_clock_config->DDR_TIMING_128H);
+		ispi_reg_write(0x129, g_clock_config->DDR_TIMING_129H);
+		ispi_reg_write(0x12A, g_clock_config->DDR_TIMING_12AH);
+		ispi_reg_write(0x12B, g_clock_config->DDR_TIMING_12BH);
+		ispi_reg_write(0x12C, g_clock_config->DDR_TIMING_12CH);
+		ispi_reg_write(0x12D, g_clock_config->DDR_TIMING_12DH);
+		ispi_reg_write(0x12E, g_clock_config->DDR_TIMING_12EH);
+		ispi_reg_write(0x12F, g_clock_config->DDR_TIMING_12FH);
+	}
+
+	if (g_clock_config->DDR_CHAN_3_VALID) {
+		ispi_reg_write(0x140, g_clock_config->DDR_TIMING_140H);
+		ispi_reg_write(0x141, g_clock_config->DDR_TIMING_141H);
+		ispi_reg_write(0x142, g_clock_config->DDR_TIMING_142H);
+		ispi_reg_write(0x143, g_clock_config->DDR_TIMING_143H);
+		ispi_reg_write(0x144, g_clock_config->DDR_TIMING_144H);
+		ispi_reg_write(0x145, g_clock_config->DDR_TIMING_145H);
+		ispi_reg_write(0x146, g_clock_config->DDR_TIMING_146H);
+		ispi_reg_write(0x147, g_clock_config->DDR_TIMING_147H);
+		ispi_reg_write(0x148, g_clock_config->DDR_TIMING_148H);
+		ispi_reg_write(0x149, g_clock_config->DDR_TIMING_149H);
+		ispi_reg_write(0x14A, g_clock_config->DDR_TIMING_14AH);
+		ispi_reg_write(0x14B, g_clock_config->DDR_TIMING_14BH);
+		ispi_reg_write(0x14C, g_clock_config->DDR_TIMING_14CH);
+		ispi_reg_write(0x14D, g_clock_config->DDR_TIMING_14DH);
+		ispi_reg_write(0x14E, g_clock_config->DDR_TIMING_14EH);
+		ispi_reg_write(0x14F, g_clock_config->DDR_TIMING_14FH);
+	}
+
+	if (g_clock_config->DDR_CHAN_4_VALID) {
+		ispi_reg_write(0x160, g_clock_config->DDR_TIMING_160H);
+		ispi_reg_write(0x161, g_clock_config->DDR_TIMING_161H);
+		ispi_reg_write(0x162, g_clock_config->DDR_TIMING_162H);
+		ispi_reg_write(0x163, g_clock_config->DDR_TIMING_163H);
+		ispi_reg_write(0x164, g_clock_config->DDR_TIMING_164H);
+		ispi_reg_write(0x165, g_clock_config->DDR_TIMING_165H);
+		ispi_reg_write(0x166, g_clock_config->DDR_TIMING_166H);
+		ispi_reg_write(0x167, g_clock_config->DDR_TIMING_167H);
+		ispi_reg_write(0x168, g_clock_config->DDR_TIMING_168H);
+		ispi_reg_write(0x169, g_clock_config->DDR_TIMING_169H);
+		ispi_reg_write(0x16A, g_clock_config->DDR_TIMING_16AH);
+		ispi_reg_write(0x16B, g_clock_config->DDR_TIMING_16BH);
+		ispi_reg_write(0x16C, g_clock_config->DDR_TIMING_16CH);
+		ispi_reg_write(0x16D, g_clock_config->DDR_TIMING_16DH);
+		ispi_reg_write(0x16E, g_clock_config->DDR_TIMING_16EH);
+		ispi_reg_write(0x16F, g_clock_config->DDR_TIMING_16FH);
+	}
+
+	ispi_reg_write(0x180, g_clock_config->DDR_TIMING_180H);
+	ispi_reg_write(0x181, g_clock_config->DDR_TIMING_181H);
+	ispi_reg_write(0x182, g_clock_config->DDR_TIMING_182H);
+	ispi_reg_write(0x183, g_clock_config->DDR_TIMING_183H);
+	ispi_reg_write(0x184, g_clock_config->DDR_TIMING_184H);
+	ispi_reg_write(0x185, g_clock_config->DDR_TIMING_185H);
+	ispi_reg_write(0x186, g_clock_config->DDR_TIMING_186H);
+	ispi_reg_write(0x187, g_clock_config->DDR_TIMING_187H);
+	ispi_reg_write(0x188, g_clock_config->DDR_TIMING_188H);
+	ispi_reg_write(0x189, g_clock_config->DDR_TIMING_189H);
+	ispi_reg_write(0x18A, g_clock_config->DDR_TIMING_18AH);
+	ispi_reg_write(0x18B, g_clock_config->DDR_TIMING_18BH);
+	ispi_reg_write(0x18C, g_clock_config->DDR_TIMING_18CH);
+
+	//usb_clock_pre_init();
+
+	udelay(5000);
+}
+
+static void pll_setup_mem(void)
+{
+}
+
+static void pll_setup_mem_cal(void)
+{
+}
+
+static void print_pll_reg(UINT32 index, UINT32 value)
+{
+	printf("pll reg %lx = %lx\n", index, value);
+}
+
+static void pll_dump_reg(void)
+{
+	print_pll_reg(0x005, ispi_reg_read(0x005));
+	print_pll_reg(0x006, ispi_reg_read(0x006));
+	print_pll_reg(0x063, ispi_reg_read(0x063));
+	print_pll_reg(0x065, ispi_reg_read(0x065));
+	print_pll_reg(0x066, ispi_reg_read(0x066));
+	print_pll_reg(0x069, ispi_reg_read(0x069));
+
+	if (g_clock_config->DDR_CHAN_1_VALID)
+	{
+		print_pll_reg(0x100, ispi_reg_read(0x100));
+		print_pll_reg(0x101, ispi_reg_read(0x101));
+		print_pll_reg(0x102, ispi_reg_read(0x102));
+		print_pll_reg(0x103, ispi_reg_read(0x103));
+		print_pll_reg(0x104, ispi_reg_read(0x104));
+		print_pll_reg(0x105, ispi_reg_read(0x105));
+		print_pll_reg(0x106, ispi_reg_read(0x106));
+		print_pll_reg(0x107, ispi_reg_read(0x107));
+		print_pll_reg(0x108, ispi_reg_read(0x108));
+		print_pll_reg(0x109, ispi_reg_read(0x109));
+		print_pll_reg(0x10A, ispi_reg_read(0x10A));
+		print_pll_reg(0x10B, ispi_reg_read(0x10B));
+		print_pll_reg(0x10C, ispi_reg_read(0x10C));
+		print_pll_reg(0x10D, ispi_reg_read(0x10D));
+		print_pll_reg(0x10E, ispi_reg_read(0x10E));
+		print_pll_reg(0x10F, ispi_reg_read(0x10F));
+	}
+
+	if (g_clock_config->DDR_CHAN_2_VALID)
+	{
+		print_pll_reg(0x120, ispi_reg_read(0x120));
+		print_pll_reg(0x121, ispi_reg_read(0x121));
+		print_pll_reg(0x122, ispi_reg_read(0x122));
+		print_pll_reg(0x123, ispi_reg_read(0x123));
+		print_pll_reg(0x124, ispi_reg_read(0x124));
+		print_pll_reg(0x125, ispi_reg_read(0x125));
+		print_pll_reg(0x126, ispi_reg_read(0x126));
+		print_pll_reg(0x127, ispi_reg_read(0x127));
+		print_pll_reg(0x128, ispi_reg_read(0x128));
+		print_pll_reg(0x129, ispi_reg_read(0x129));
+		print_pll_reg(0x12A, ispi_reg_read(0x12A));
+		print_pll_reg(0x12B, ispi_reg_read(0x12B));
+		print_pll_reg(0x12C, ispi_reg_read(0x12C));
+		print_pll_reg(0x12D, ispi_reg_read(0x12D));
+		print_pll_reg(0x12E, ispi_reg_read(0x12E));
+		print_pll_reg(0x12F, ispi_reg_read(0x12F));
+	}
+
+	if (g_clock_config->DDR_CHAN_3_VALID)
+	{
+		print_pll_reg(0x140, ispi_reg_read(0x140));
+		print_pll_reg(0x141, ispi_reg_read(0x141));
+		print_pll_reg(0x142, ispi_reg_read(0x142));
+		print_pll_reg(0x143, ispi_reg_read(0x143));
+		print_pll_reg(0x144, ispi_reg_read(0x144));
+		print_pll_reg(0x145, ispi_reg_read(0x145));
+		print_pll_reg(0x146, ispi_reg_read(0x146));
+		print_pll_reg(0x147, ispi_reg_read(0x147));
+		print_pll_reg(0x148, ispi_reg_read(0x148));
+		print_pll_reg(0x149, ispi_reg_read(0x149));
+		print_pll_reg(0x14A, ispi_reg_read(0x14A));
+		print_pll_reg(0x14B, ispi_reg_read(0x14B));
+		print_pll_reg(0x14C, ispi_reg_read(0x14C));
+		print_pll_reg(0x14D, ispi_reg_read(0x14D));
+		print_pll_reg(0x14E, ispi_reg_read(0x14E));
+		print_pll_reg(0x14F, ispi_reg_read(0x14F));
+	}
+
+	if (g_clock_config->DDR_CHAN_4_VALID)
+	{
+		print_pll_reg(0x160, ispi_reg_read(0x160));
+		print_pll_reg(0x161, ispi_reg_read(0x161));
+		print_pll_reg(0x162, ispi_reg_read(0x162));
+		print_pll_reg(0x163, ispi_reg_read(0x163));
+		print_pll_reg(0x164, ispi_reg_read(0x164));
+		print_pll_reg(0x165, ispi_reg_read(0x165));
+		print_pll_reg(0x166, ispi_reg_read(0x166));
+		print_pll_reg(0x167, ispi_reg_read(0x167));
+		print_pll_reg(0x168, ispi_reg_read(0x168));
+		print_pll_reg(0x169, ispi_reg_read(0x169));
+		print_pll_reg(0x16A, ispi_reg_read(0x16A));
+		print_pll_reg(0x16B, ispi_reg_read(0x16B));
+		print_pll_reg(0x16C, ispi_reg_read(0x16C));
+		print_pll_reg(0x16D, ispi_reg_read(0x16D));
+		print_pll_reg(0x16E, ispi_reg_read(0x16E));
+		print_pll_reg(0x16F, ispi_reg_read(0x16F));
+	}
+
+	print_pll_reg(0x180, ispi_reg_read(0x180));
+	print_pll_reg(0x181, ispi_reg_read(0x181));
+	print_pll_reg(0x182, ispi_reg_read(0x182));
+	print_pll_reg(0x183, ispi_reg_read(0x183));
+	print_pll_reg(0x184, ispi_reg_read(0x184));
+	print_pll_reg(0x185, ispi_reg_read(0x185));
+	print_pll_reg(0x186, ispi_reg_read(0x186));
+	print_pll_reg(0x187, ispi_reg_read(0x187));
+	print_pll_reg(0x188, ispi_reg_read(0x188));
+	print_pll_reg(0x189, ispi_reg_read(0x189));
+	print_pll_reg(0x18A, ispi_reg_read(0x18A));
+	print_pll_reg(0x18B, ispi_reg_read(0x18B));
+	print_pll_reg(0x18C, ispi_reg_read(0x18C));
+}
+
+static int clock_save_config(void)
+{
+	/* save config to nand */
+	return 1;
+}
+
+#ifdef DO_DDR_PLL_DEBUG
+
+static int ddr_get_freq(UINT8 chioce)
+{
+	switch(chioce)
+	{
+		case 1:
+			return 50;
+		case 2:
+			return 100;
+		case 3:
+			return 156;
+		case 4:
+			return 200;
+		case 5:
+			return 290;
+		case 6:
+			return 333;
+		case 7:
+			return 355;
+		case 8:
+			return 400;
+		case 9:
+			return 416;
+		case 10:
+			return 455;
+		case 11:
+			return 519;
+		case 12:
+			return 533;
+		case 13:
+			return 260;
+		default:
+			return -1;
+	}
+}
+
+static void freq_choose(void)
+{
+	UINT8 i = 0, buf[3] = {0}, choice = 0;
+	INT32 freq_temp = 0;
+
+	printf("\nPlese choose the ddr Freq:");
+	printf("\n1.50M  2.100M  3.156M  4.200M  5.290M  6.333M  7.355M  8.400M 9.416M 10.455M 11.519M 12.533M 13.260M");
+	printf("\nThe number is:");
+
+	while(1)
+	{
+		if (i > 2)
+		{
+			printf("\n Sorry, you input is wrong. Please input again:");
+			i = 0;
+		}
+		buf[i] = serial_getc();
+		serial_putc(buf[i]);
+
+		if ( ('\r' == buf[i]) || ('\n' == buf[i]))
+		{
+			serial_puts("\n");
+			break;
+		}
+
+		i++;
+	}
+
+	if (1 == i)
+		choice = buf[0] - 0x30;
+	else if (2 == i)
+		choice = 10*(buf[0] - 0x30) + (buf[1] - 0x30);
+	else
+		return;
+
+	freq_temp = ddr_get_freq(choice);
+	if (-1 == freq_temp )
+		printf("\n Sorry, the fre you choose is wrong");
+	ddrfreq = freq_temp;
+}
+
+static void data_bits_choose(void)
+{
+	UINT8 i = 0, buf[2] = {0};
+
+	printf("\nPlese choose the ddr data bits:");
+	printf("\n1.16  2.32");
+	printf("\nThe number is:");
+
+	while(1)
+	{
+		buf[i] =serial_getc();
+
+		if (i == 1)
+		{
+			if (('\r' == buf[i]) || ('\n' == buf[i]))
+			{
+				if (1 == (buf[0] - 0x30))
+					ddr32bit = 0;
+				else
+					ddr32bit = 1;
+				return;
+			}
+			else
+			{
+				printf("\n Sorry, you input is wrong. Please input again:");
+				i = 0;
+				continue;
+			}
+		}
+
+		serial_putc(buf[i]);
+
+		if ((buf[i] - 0x30) > 2 || 0 == (buf[i] - 0x30))
+			printf("\n Sorry, you input is wrong. Please input again:");
+		else
+			i++;
+	}
+}
+
+#if 0
+static void pmu_setup_calibration_voltage(UINT8 vcoreselect)
+{
+	UINT8 buf[3] = {0}, voltage = 0;
+	int i = 0;
+	UINT32 reg_value,temp, regid = 0;
+
+	ispi_open(1);
+	if (1 == vcoreselect)
+	{
+		regid = 0x2f;
+		printf("\nPlese input vcore voltage(0 ~ 15):");
+	}
+	else
+	{
+		regid = 0x2a;
+		printf("\nPlese input DDR voltage(0 ~ 15):");
+	}
+
+
+	while(1)
+	{
+		if (i > 2)
+		{
+			printf("\n Sorry, you input is wrong. Please input again:");
+			i = 0;
+		}
+		buf[i] = serial_getc();
+		serial_putc(buf[i]);
+
+		if ( ('\r' == buf[i]) || ('\n' == buf[i]))
+		{
+			printf("\n");
+			break;
+		}
+
+		i++;
+	}
+
+	if (1 == i)
+		voltage = buf[0] - 0x30;
+	else if (2 == i)
+		voltage = 10*(buf[0] - 0x30) + (buf[1] - 0x30);
+	else
+		return;
+
+	temp = (UINT32)voltage;
+	temp = (temp & 0xf) << 12;
+	reg_value = ispi_reg_read(regid);
+	reg_value &= ~(0xf << 12);
+	reg_value |= temp ;
+	ispi_reg_write(regid, reg_value);
+	mdelay(100);
+}
+#endif
+
+static void pmu_setup_calibration_voltage(UINT8 vcoreselect)
+{
+	UINT8 buf[3] = {0}, voltage = 0;
+	int i = 0;
+	UINT32 reg_value,temp, regid = 0;
+
+	ispi_open(1);
+	if (1 == vcoreselect)
+	{
+		regid = 0x2f;
+		printf("\nPlese input vcore voltage(0 ~ 15):");
+	}
+	else
+	{
+		regid = 0x2a;
+		if (2 == vcoreselect)
+			printf("\nPlese input DDR buck3 voltage(0 ~ 15):");
+		else
+			printf("\nPlese input DDR buck4 voltage(0 ~ 15):");
+	}
+
+	while(1)
+	{
+		if (i > 2)
+		{
+			printf("\n Sorry, you input is wrong. Please input again:");
+			i = 0;
+		}
+		buf[i] = serial_getc();
+		serial_putc(buf[i]);
+
+		if ( ('\r' == buf[i]) || ('\n' == buf[i]))
+		{
+			printf("\n");
+			break;
+		}
+
+		i++;
+	}
+
+	if (1 == i)
+		voltage = buf[0] - 0x30;
+	else if (2 == i)
+		voltage = 10*(buf[0] - 0x30) + (buf[1] - 0x30);
+	else
+		return;
+
+	if ((vcoreselect == 1) || (vcoreselect == 2))
+	{
+		temp = (UINT32)voltage;
+		temp = (temp & 0xf) << 12;
+		reg_value = ispi_reg_read(regid);
+		reg_value &= ~(0xf << 12);
+		reg_value |= temp ;
+		ispi_reg_write(regid, reg_value);
+		mdelay(100);
+	}
+	else
+	{
+		temp = (UINT32)voltage;
+		temp = (temp & 0xf) << 4;
+		reg_value = ispi_reg_read(regid);
+		reg_value &= ~(0xf << 4);
+		reg_value |= temp ;
+		reg_value ^= RDA_PMU_VBUCK4_BIT_ACT(8);
+		ispi_reg_write(regid, reg_value);
+		ispi_reg_write(0x0D, 0x92D0);
+		ispi_reg_write(0x4B, 0x96A8);
+		mdelay(100);
+	}
+}
+
+static void pmu_buck4_buck3_choose(void)
+{
+	UINT8 i = 0, buf[2] = {0};
+	UINT8 ddr_voltage_source = 0;
+
+	printf("\nPlese choose the ddr voltage:");
+	printf("\n1.DDR3L  2.DDR3");
+	printf("\nThe number is:");
+
+	while(1)
+	{
+		buf[i] =serial_getc();
+
+		if (i == 1)
+		{
+			if (('\r' == buf[i]) || ('\n' == buf[i]))
+			{
+				if (1 == (buf[0] - 0x30))
+					ddr_voltage_source =2;
+				else{
+					ddr_voltage_source = 3;
+					pmu_setup_calibration_voltage(2);
+				}
+				pmu_setup_calibration_voltage(ddr_voltage_source);
+				return;
+			}
+			else
+			{
+				printf("\n Sorry, you input is wrong. Please input again:");
+				i = 0;
+				continue;
+			}
+		}
+
+		serial_putc(buf[i]);
+
+		if ((buf[i] - 0x30) > 2 || 0 == (buf[i] - 0x30))
+			printf("\n Sorry, you input is wrong. Please input again:");
+		else
+			i++;
+	}
+}
+
+
+void clock_load_ddr_cal_config(void)
+{
+	clock_debug_config.PLL_FREQ_MEM = ddrfreq;
+	if (ddrfreq < 200)
+		clock_debug_config.DDR_FLAGS |= DDR_FLAGS_DLLOFF;
+	else
+		clock_debug_config.DDR_FLAGS &= ~DDR_FLAGS_DLLOFF;
+
+	if (0 == ddr32bit)
+	{
+		clock_debug_config.DDR_CHAN_3_VALID = 0;
+		clock_debug_config.DDR_CHAN_4_VALID = 0;
+	}
+
+	clock_debug_config.DDR_PARA &= ~DDR_PARA_MEM_BITS_MASK;
+	if (0 == ddr32bit)
+		clock_debug_config.DDR_PARA |= DDR_PARA_MEM_BITS(1);
+	else
+		clock_debug_config.DDR_PARA |= DDR_PARA_MEM_BITS(2);
+}
+
+static int serial_gets(UINT8 *pstr)
+{
+    UINT32 length;
+
+    length = 0;
+    while(1) {
+        pstr[length] = serial_getc();
+        if(pstr[length] == '\r') {
+            pstr[length] = 0x00;
+            break;
+        }
+        else if( pstr[length] == '\b' ) {
+            if(length>0) {
+                length --;
+                printf("\b");
+            }
+        }
+        else {
+            serial_putc(pstr[length]);
+            length ++;
+        }
+
+        if(length > 32)
+            return -1;
+    }
+    return length;
+}
+
+UINT32 asc2hex(UINT8 *pstr, UINT8 len)
+{
+	UINT8 i,ch,mylen;
+	UINT32 hexvalue;
+
+	for(mylen=0,i=0; i<8; i++)
+	{
+		if( pstr[i] == 0 )
+			break;
+		mylen ++;
+	}
+	if( len != 0 )
+	{
+		if(mylen>len)
+			mylen = len;
+	}
+	if(mylen>8)
+		mylen = 8;
+
+	hexvalue = 0;
+	for (i = 0; i < mylen; i++)
+	{
+		hexvalue <<= 4;
+		ch = *(pstr+i);
+		if((ch>='0') && (ch<='9'))
+			hexvalue |= ch - '0';
+		else if((ch>='A') && (ch<='F'))
+			hexvalue |= ch - ('A' - 10);
+		else if((ch>='a') && (ch<='f'))
+			hexvalue |= ch - ('a' - 10);
+		else
+			;
+	}
+	return(hexvalue);
+}
+
+static int process_cmd(char * cmd)
+{
+	char cmd_element[3][16] = {{0}};
+	char * cmd_temp = cmd;
+	UINT8 i = 0, cmd_element_num = 0, former_space = 1;
+	UINT16 reg = 0, reg_value = 0;
+
+	if (NULL == cmd)
+		return -1;
+
+	while(('\0' != *cmd_temp) && ('\r' != *cmd_temp) && ('\n' != *cmd_temp))
+	{
+		if (' ' == * cmd_temp)
+		{
+			if (0 == former_space)
+			{
+				former_space = 1;
+				cmd_element[cmd_element_num][i] = '\0';
+				cmd_element_num++;
+				if (cmd_element_num > 2)
+					return -1;
+			
+				i = 0;
+			}
+		}
+		else
+		{
+			former_space = 0;
+			cmd_element[cmd_element_num][i] = *cmd_temp;
+			i++;
+			if (i > 6)
+				return -1;
+		}
+
+		cmd_temp++;	
+	}
+
+	cmd_element[cmd_element_num][i] = '\0';
+
+	if (!strcmp(cmd_element[0], "read"))
+	{
+		if (cmd_element_num == 2)
+			return -1;
+		if (('0' != cmd_element[1][0]) || ('x' != cmd_element[1][1]))
+			return -1;
+		reg = (UINT16)asc2hex((UINT8 *)&cmd_element[1][2], 4);
+		reg_value = ispi_reg_read(reg);
+		printf("value = 0x%x", reg_value);
+		printf("\nddrPll#");
+	}	
+	else if (!strcmp(cmd_element[0], "write"))
+	{
+		if (cmd_element_num != 2)
+			return -1;
+		if (('0' != cmd_element[1][0]) || ('x' != cmd_element[1][1])
+		   || ('0' != cmd_element[2][0]) || ('x' != cmd_element[2][1]))
+			return -1;
+
+		reg = (UINT16)asc2hex((UINT8 *)&cmd_element[1][2], 4);
+		reg_value  = (UINT16)asc2hex((UINT8 *)&cmd_element[2][2], 4);
+		ispi_reg_write(reg, reg_value);
+	}
+	else if (!strcmp(cmd_element[0], "finish"))
+	{
+		return 1;
+	}
+	else if (!strcmp(cmd_element[0], "dump"))
+	{    
+		pll_dump_reg();
+		printf("ddrPll#");
+	}
+	else
+	{    
+		return -1;
+	}
+
+	return 0;
+}
+
+static void cmd_input(void)
+{
+	char cmd[48] = {0};
+	int len = 0;
+	
+	ispi_open(0);
+	printf("\nddrPll#");
+	while(1)
+	{
+		len = serial_gets((UINT8 *)cmd);
+		printf("\nddrPll#");
+		if (len > 0)
+		{
+			int result = 0;
+
+			result =  process_cmd(cmd);
+			if (-1 == result)
+				printf("command error! \nddrPll#");
+			else if (1 == result)
+				break;
+			else
+				continue;
+		}
+	}
+
+	return;
+}
+
+#endif /* DO_DDR_PLL_DEBUG */
+
+int clock_init(void)
+{
+#ifdef DO_DDR_PLL_DEBUG
+	char choice = 'n';
+#endif
+
+	/* First check current usb usage */
+	check_usb_usage();
+
+	printf("Init Clock ...\n");
+	g_clock_config = get_default_clock_config();
+
+	printf("Clock config ver: %d.%d\n",
+		g_clock_config->VERSION_MAJOR, g_clock_config->VERSION_MINOR);
+
+	pmu_setup_init();
+
+#ifdef DO_DDR_PLL_DEBUG
+	printf("If you want to config the ddr para manully ?(y = yes, n = no) \n");
+	choice = serial_getc();
+	if (choice == 'y')
+	{
+		memcpy(&clock_debug_config, g_clock_config,
+				sizeof(clock_debug_config));
+		g_clock_config = &clock_debug_config;
+		pmu_setup_calibration_voltage(1);
+		pmu_buck4_buck3_choose();
+		freq_choose();
+		data_bits_choose();
+		clock_load_ddr_cal_config();
+	}
+#endif
+
+	sys_shutdown_pll();
+	ispi_open(0);
+	pll_setup_init();
+#ifdef DO_DDR_PLL_DEBUG
+	if (choice == 'y')
+		cmd_input();
+#endif
+	pll_setup_freq();
+	sys_setup_pll();
+	sys_setup_clk();
+
+	if (g_clock_config->DDR_CAL) {
+		printf("Init DDR for ddr_cal\n");
+		ddr_init(g_clock_config->DDR_FLAGS, g_clock_config->DDR_PARA);
+		printf("Done\n");
+		pll_setup_mem_cal();
+		clock_save_config();
+	} else {
+		pll_setup_mem();
+	}
+
+	sys_dump_pll_freq();
+	sys_dump_clk();
+	pll_dump_reg();
+
+	printf("Init DDR, flag = 0x%04x, para = 0x%08lx\n",
+		g_clock_config->DDR_FLAGS, g_clock_config->DDR_PARA);
+	ddr_init(g_clock_config->DDR_FLAGS, g_clock_config->DDR_PARA);
+	printf("Done\n");
+
+	#ifdef DO_SIMPLE_DDR_TEST
+	mem_test_write();
+	mem_test_read();
+#endif
+
+	return 0;
+}
+
+#else /* CONFIG_RDA_FPGA */
+
+int clock_init(void)
+{
+	u16 ddr_flags = DDR_FLAGS_DLLOFF
+		| DDR_FLAGS_ODT(1)
+		| DDR_FLAGS_RON(0);
+	//16bit
+	u32 ddr_para = DDR_PARA_MEM_BITS(2)
+		| DDR_PARA_BANK_BITS(3)
+		| DDR_PARA_ROW_BITS(3)
+		| DDR_PARA_COL_BITS(1);
+
+	printf("Init DDR\n");
+	ddr_init(ddr_flags, ddr_para);
+	printf("Done\n");
+
+#ifdef DO_SIMPLE_DDR_TEST
+	mem_test_write();
+	mem_test_read();
+#endif
+
+	return 0;
+}
+
+#endif /* CONFIG_RDA_FPGA */
+
diff --git a/board/rda/rda8810h/clock_config.c b/board/rda/rda8810h/clock_config.c
new file mode 100644
index 0000000000..85254c90d7
--- /dev/null
+++ b/board/rda/rda8810h/clock_config.c
@@ -0,0 +1,149 @@
+#ifndef TARGET_TOOL
+#include <common.h>
+#include <asm/arch/factory.h>
+#include "clock_config.h"
+#endif
+
+#include "ddr3.h"
+#include "tgt_ap_clock_config.h"
+
+static const struct clock_config clock_default_config = {
+	/* Header */
+	0, 			// MAGIC;
+	CLOCK_VER_MAJOR,	// VERSION_MAJOR;
+	CLOCK_VER_MINOR,	// VERSION_MINOR;
+	/* PLL Freqs (MHz) */
+	_TGT_AP_PLL_CPU_FREQ,	// PLL_FREQ_CPU; /* 05, 06 */
+	_TGT_AP_PLL_BUS_FREQ,	// PLL_FREQ_BUS; /* 25, 26 */
+	_TGT_AP_PLL_MEM_FREQ,	// PLL_FREQ_MEM; /* 65, 66 */
+	_TGT_AP_PLL_USB_FREQ,	// PLL_FREQ_USB; /* 85, 86 */
+	/* DDR Cal */
+	0,			// DDR_CAL;
+	/* DDR_FLAGS */
+	DDR_FLAGS_ODT(_TGT_AP_DDR_ODT)	// 010 -- 120 Ohm
+#if (_TGT_AP_DDR_CLOCK < 200)
+	    | DDR_FLAGS_DLLOFF
+#endif
+#ifdef _TGT_AP_DDR_LOWPWR
+	    | DDR_FLAGS_LOWPWR
+#endif
+	    | DDR_FLAGS_RON(_TGT_AP_DDR_RON),	// 00 -- 40 Ohm
+	/* DDR_PARA */
+	DDR_PARA_CHIP_BITS(_TGT_AP_DDR_CHIP_BITS)
+	    | DDR_PARA_MEM_BITS(_TGT_AP_DDR_MEM_BITS)
+	    | DDR_PARA_BANK_BITS(_TGT_AP_DDR_BANK_BITS)
+	    | DDR_PARA_ROW_BITS(_TGT_AP_DDR_ROW_BITS )
+	    | DDR_PARA_COL_BITS(_TGT_AP_DDR_COL_BITS),
+
+	/* AP sysctrl */
+	_TGT_AP_CLK_CPU,	// CLK_CPU;
+	_TGT_AP_CLK_AXI,	// CLK_AXI;
+	_TGT_AP_CLK_GCG,	// CLK_GCG;
+	_TGT_AP_CLK_AHB1,	// CLK_AHB1;
+	_TGT_AP_CLK_APB1,	// CLK_APB1;
+	_TGT_AP_CLK_APB2,	// CLK_APB2;
+	_TGT_AP_CLK_MEM,	// CLK_MEM;
+	_TGT_AP_CLK_GPU,	// CLK_GPU;
+	_TGT_AP_CLK_VPU,	// CLK_VPU;
+	_TGT_AP_CLK_VOC,	// CLK_VOC;
+	_TGT_AP_CLK_SFLSH,	// CLK_SFLSH;
+	0,			// RESERVE;
+
+	/* DDR timings, defined in target */
+	DDR_CHAN_1_VALID_VAL,	// DDR_CHAN_1_VALID;
+	DDR_TIMING_100H_VAL,	// DDR_TIMING_100H;
+	DDR_TIMING_101H_VAL,	// DDR_TIMING_101H;
+	DDR_TIMING_102H_VAL,	// DDR_TIMING_102H;
+	DDR_TIMING_103H_VAL,	// DDR_TIMING_103H;
+	DDR_TIMING_104H_VAL,	// DDR_TIMING_104H;
+	DDR_TIMING_105H_VAL,	// DDR_TIMING_105H;
+	DDR_TIMING_106H_VAL,	// DDR_TIMING_106H;
+	DDR_TIMING_107H_VAL,	// DDR_TIMING_107H;
+	DDR_TIMING_108H_VAL,	// DDR_TIMING_108H;
+	DDR_TIMING_109H_VAL,	// DDR_TIMING_109H;
+	DDR_TIMING_10AH_VAL,	// DDR_TIMING_10AH;
+	DDR_TIMING_10BH_VAL,	// DDR_TIMING_10BH;
+	DDR_TIMING_10CH_VAL,	// DDR_TIMING_10CH;
+	DDR_TIMING_10DH_VAL,	// DDR_TIMING_10DH;
+	DDR_TIMING_10EH_VAL,	// DDR_TIMING_10EH;
+	DDR_TIMING_10FH_VAL,	// DDR_TIMING_10FH;
+
+	DDR_CHAN_2_VALID_VAL,	// DDR_CHAN_2_VALID;
+	DDR_TIMING_120H_VAL,	// DDR_TIMING_120H;
+	DDR_TIMING_121H_VAL,	// DDR_TIMING_121H;
+	DDR_TIMING_122H_VAL,	// DDR_TIMING_122H;
+	DDR_TIMING_123H_VAL,	// DDR_TIMING_123H;
+	DDR_TIMING_124H_VAL,	// DDR_TIMING_124H;
+	DDR_TIMING_125H_VAL,	// DDR_TIMING_125H;
+	DDR_TIMING_126H_VAL,	// DDR_TIMING_126H;
+	DDR_TIMING_127H_VAL,	// DDR_TIMING_127H;
+	DDR_TIMING_128H_VAL,	// DDR_TIMING_128H;
+	DDR_TIMING_129H_VAL,	// DDR_TIMING_129H;
+	DDR_TIMING_12AH_VAL,	// DDR_TIMING_12AH;
+	DDR_TIMING_12BH_VAL,	// DDR_TIMING_12BH;
+	DDR_TIMING_12CH_VAL,	// DDR_TIMING_12CH;
+	DDR_TIMING_12DH_VAL,	// DDR_TIMING_12DH;
+	DDR_TIMING_12EH_VAL,	// DDR_TIMING_12EH;
+	DDR_TIMING_12FH_VAL,	// DDR_TIMING_12FH;
+
+	DDR_CHAN_3_VALID_VAL,	// DDR_CHAN_3_VALID;
+	DDR_TIMING_140H_VAL,	// DDR_TIMING_140H;
+	DDR_TIMING_141H_VAL,	// DDR_TIMING_141H;
+	DDR_TIMING_142H_VAL,	// DDR_TIMING_142H;
+	DDR_TIMING_143H_VAL,	// DDR_TIMING_143H;
+	DDR_TIMING_144H_VAL,	// DDR_TIMING_144H;
+	DDR_TIMING_145H_VAL,	// DDR_TIMING_145H;
+	DDR_TIMING_146H_VAL,	// DDR_TIMING_146H;
+	DDR_TIMING_147H_VAL,	// DDR_TIMING_147H;
+	DDR_TIMING_148H_VAL,	// DDR_TIMING_148H;
+	DDR_TIMING_149H_VAL,	// DDR_TIMING_149H;
+	DDR_TIMING_14AH_VAL,	// DDR_TIMING_14AH;
+	DDR_TIMING_14BH_VAL,	// DDR_TIMING_14BH;
+	DDR_TIMING_14CH_VAL,	// DDR_TIMING_14CH;
+	DDR_TIMING_14DH_VAL,	// DDR_TIMING_14DH;
+	DDR_TIMING_14EH_VAL,	// DDR_TIMING_14EH;
+	DDR_TIMING_14FH_VAL,	// DDR_TIMING_14FH;
+
+	DDR_CHAN_4_VALID_VAL,	// DDR_CHAN_4_VALID;
+	DDR_TIMING_160H_VAL,	// DDR_TIMING_160H;
+	DDR_TIMING_161H_VAL,	// DDR_TIMING_161H;
+	DDR_TIMING_162H_VAL,	// DDR_TIMING_162H;
+	DDR_TIMING_163H_VAL,	// DDR_TIMING_163H;
+	DDR_TIMING_164H_VAL,	// DDR_TIMING_164H;
+	DDR_TIMING_165H_VAL,	// DDR_TIMING_165H;
+	DDR_TIMING_166H_VAL,	// DDR_TIMING_166H;
+	DDR_TIMING_167H_VAL,	// DDR_TIMING_167H;
+	DDR_TIMING_168H_VAL,	// DDR_TIMING_168H;
+	DDR_TIMING_169H_VAL,	// DDR_TIMING_169H;
+	DDR_TIMING_16AH_VAL,	// DDR_TIMING_16AH;
+	DDR_TIMING_16BH_VAL,	// DDR_TIMING_16BH;
+	DDR_TIMING_16CH_VAL,	// DDR_TIMING_16CH;
+	DDR_TIMING_16DH_VAL,	// DDR_TIMING_16DH;
+	DDR_TIMING_16EH_VAL,	// DDR_TIMING_16EH;
+	DDR_TIMING_16FH_VAL,	// DDR_TIMING_16FH;
+
+	DDR_TIMING_180H_VAL,	// DDR_TIMING_180H;
+	DDR_TIMING_181H_VAL,	// DDR_TIMING_181H;
+	DDR_TIMING_182H_VAL,	// DDR_TIMING_182H;
+	DDR_TIMING_183H_VAL,	// DDR_TIMING_183H;
+	DDR_TIMING_184H_VAL,	// DDR_TIMING_184H;
+	DDR_TIMING_185H_VAL,	// DDR_TIMING_185H;
+	DDR_TIMING_186H_VAL,	// DDR_TIMING_186H;
+	DDR_TIMING_187H_VAL,	// DDR_TIMING_187H;
+	DDR_TIMING_188H_VAL,	// DDR_TIMING_188H;
+	DDR_TIMING_189H_VAL,	// DDR_TIMING_189H;
+	DDR_TIMING_18AH_VAL,	// DDR_TIMING_18AH;
+	DDR_TIMING_18BH_VAL,	// DDR_TIMING_18BH;
+	DDR_TIMING_18CH_VAL,	// DDR_TIMING_18CH;
+	DDR_TIMING_069H_VAL		// DDR_TIMING_18CH;
+};
+
+const struct clock_config *get_default_clock_config(void)
+{
+#ifndef TARGET_TOOL
+	BUILD_BUG_ON(sizeof(struct clock_config) > AP_FACTORY_CLOCK_CFG_LEN);
+#endif
+
+	return &clock_default_config;
+}
+
diff --git a/board/rda/rda8810h/clock_config.h b/board/rda/rda8810h/clock_config.h
new file mode 100644
index 0000000000..3e472df08d
--- /dev/null
+++ b/board/rda/rda8810h/clock_config.h
@@ -0,0 +1,132 @@
+#ifndef __CLOCK_CONFIG_H__
+#define __CLOCK_CONFIG_H__
+
+typedef unsigned long               UINT32;
+typedef unsigned short              UINT16;
+typedef long                        INT32;
+typedef short                       INT16;
+typedef unsigned char               UINT8;
+typedef char                        INT8;
+
+#define CLOCK_VER_MAJOR		2
+#define CLOCK_VER_MINOR		0
+
+struct clock_config {
+	/* Header */
+	UINT32 MAGIC;
+	UINT16 VERSION_MAJOR;
+	UINT16 VERSION_MINOR;
+	/* PLL Freqs (MHz) */
+	UINT32 PLL_FREQ_CPU;	/* 05, 06 */
+	UINT32 PLL_FREQ_BUS;	/* 25, 26 */
+	UINT32 PLL_FREQ_MEM;	/* 65, 66 */
+	UINT32 PLL_FREQ_USB;	/* 85, 86 */
+	/* DDR Flags */
+	UINT16 DDR_CAL;
+	UINT16 DDR_FLAGS;
+	UINT32 DDR_PARA;
+	/* AP sysctrl */
+	UINT16 CLK_CPU;
+	UINT16 CLK_AXI;
+	UINT16 CLK_GCG;
+	UINT16 CLK_AHB1;
+	UINT16 CLK_APB1;
+	UINT16 CLK_APB2;
+	UINT16 CLK_MEM;
+	UINT16 CLK_GPU;
+	UINT16 CLK_VPU;
+	UINT16 CLK_VOC;
+	UINT16 CLK_SFLSH;
+	UINT16 RESERVE;
+	/* DDR timings */
+	UINT16 DDR_CHAN_1_VALID;
+	UINT16 DDR_TIMING_100H;
+	UINT16 DDR_TIMING_101H;
+	UINT16 DDR_TIMING_102H;
+	UINT16 DDR_TIMING_103H;
+	UINT16 DDR_TIMING_104H;
+	UINT16 DDR_TIMING_105H;
+	UINT16 DDR_TIMING_106H;
+	UINT16 DDR_TIMING_107H;
+	UINT16 DDR_TIMING_108H;
+	UINT16 DDR_TIMING_109H;
+	UINT16 DDR_TIMING_10AH;
+	UINT16 DDR_TIMING_10BH;
+	UINT16 DDR_TIMING_10CH;
+	UINT16 DDR_TIMING_10DH;
+	UINT16 DDR_TIMING_10EH;
+	UINT16 DDR_TIMING_10FH;
+
+	UINT16 DDR_CHAN_2_VALID;
+	UINT16 DDR_TIMING_120H;
+	UINT16 DDR_TIMING_121H;
+	UINT16 DDR_TIMING_122H;
+	UINT16 DDR_TIMING_123H;
+	UINT16 DDR_TIMING_124H;
+	UINT16 DDR_TIMING_125H;
+	UINT16 DDR_TIMING_126H;
+	UINT16 DDR_TIMING_127H;
+	UINT16 DDR_TIMING_128H;
+	UINT16 DDR_TIMING_129H;
+	UINT16 DDR_TIMING_12AH;
+	UINT16 DDR_TIMING_12BH;
+	UINT16 DDR_TIMING_12CH;
+	UINT16 DDR_TIMING_12DH;
+	UINT16 DDR_TIMING_12EH;
+	UINT16 DDR_TIMING_12FH;
+
+	UINT16 DDR_CHAN_3_VALID;
+	UINT16 DDR_TIMING_140H;
+	UINT16 DDR_TIMING_141H;
+	UINT16 DDR_TIMING_142H;
+	UINT16 DDR_TIMING_143H;
+	UINT16 DDR_TIMING_144H;
+	UINT16 DDR_TIMING_145H;
+	UINT16 DDR_TIMING_146H;
+	UINT16 DDR_TIMING_147H;
+	UINT16 DDR_TIMING_148H;
+	UINT16 DDR_TIMING_149H;
+	UINT16 DDR_TIMING_14AH;
+	UINT16 DDR_TIMING_14BH;
+	UINT16 DDR_TIMING_14CH;
+	UINT16 DDR_TIMING_14DH;
+	UINT16 DDR_TIMING_14EH;
+	UINT16 DDR_TIMING_14FH;
+
+	UINT16 DDR_CHAN_4_VALID;
+	UINT16 DDR_TIMING_160H;
+	UINT16 DDR_TIMING_161H;
+	UINT16 DDR_TIMING_162H;
+	UINT16 DDR_TIMING_163H;
+	UINT16 DDR_TIMING_164H;
+	UINT16 DDR_TIMING_165H;
+	UINT16 DDR_TIMING_166H;
+	UINT16 DDR_TIMING_167H;
+	UINT16 DDR_TIMING_168H;
+	UINT16 DDR_TIMING_169H;
+	UINT16 DDR_TIMING_16AH;
+	UINT16 DDR_TIMING_16BH;
+	UINT16 DDR_TIMING_16CH;
+	UINT16 DDR_TIMING_16DH;
+	UINT16 DDR_TIMING_16EH;
+	UINT16 DDR_TIMING_16FH;
+
+	UINT16 DDR_TIMING_180H;
+	UINT16 DDR_TIMING_181H;
+	UINT16 DDR_TIMING_182H;
+	UINT16 DDR_TIMING_183H;
+	UINT16 DDR_TIMING_184H;
+	UINT16 DDR_TIMING_185H;
+	UINT16 DDR_TIMING_186H;
+	UINT16 DDR_TIMING_187H;
+	UINT16 DDR_TIMING_188H;
+	UINT16 DDR_TIMING_189H;
+	UINT16 DDR_TIMING_18AH;
+	UINT16 DDR_TIMING_18BH;
+	UINT16 DDR_TIMING_18CH;
+	UINT16 DDR_TIMING_069H;
+};
+
+const struct clock_config *get_default_clock_config(void);
+
+#endif
diff --git a/board/rda/rda8810h/config.mk b/board/rda/rda8810h/config.mk
new file mode 100644
index 0000000000..39782ba05e
--- /dev/null
+++ b/board/rda/rda8810h/config.mk
@@ -0,0 +1,15 @@
+#
+#the spl code should not exceed the SPL_MAX_SIZE,and if 
+#the spl don't up to the max size, paddint the last with
+#zero(or 0xff?)
+
+#48kbytes, 48*1024
+#SPL_APPENDING_TO	:= 48
+#SPL_MAX_SIZE	:= 49512
+
+# space for spl(48KiB) & mtd partition table(4KiB),
+# so uboot offset 52KiB(48 + 4).
+
+SPL_APPENDING_TO   := 52
+
+CONFIG_SPL_SIGNATURE_CHECK_IMAGE := y
diff --git a/board/rda/rda8810h/ddr3.c b/board/rda/rda8810h/ddr3.c
new file mode 100644
index 0000000000..a0f49e6efe
--- /dev/null
+++ b/board/rda/rda8810h/ddr3.c
@@ -0,0 +1,533 @@
+#include <common.h>
+#include <asm/arch/rda_iomap.h>
+
+#include "ddr3.h"
+#include "ddr3_init.h"
+#include "tgt_ap_clock_config.h"
+
+#pragma GCC push_options
+#pragma GCC optimize ("O0")
+
+#define DDR_TYPE _TGT_AP_DDR_TYPE
+
+#define DF_DELAY  (0x10000)
+
+#define DMC_REG_BASE RDA_DMC400_BASE
+#define PHY_REG_BASE RDA_DDRPHY_BASE
+
+#define  PHY_RDLAT          0
+#define  PHYWRDATA          1
+#define  STA                3
+#define  CLKSEL             4
+#define  PSSTART            5
+#define  PSDONE             6
+#define  LOCKED             6
+#define  CTRL_DELAY         7
+#define  RDELAY_SEL         8
+#define  WDELAY_SEL         9
+#define  PHY_RESET          10
+#define  RESET_DDR3         11
+#define  ODT_DELAY          12
+#define  DDR3_USED          13
+#define  WRITE_ENABLE_LAT   14
+#define  WRITE_DATA_LAT     15
+#define  DQOUT_ENABLE_LAT   16
+#define  DATA_ODT_ENABLE_REG	20
+#define  DATA_WRITE_ENABLE_REG  48   
+#define  DMC_READY	128
+#define  USE_ADDR   129
+
+#define ARRAY_NUM(n) (sizeof(n))/(sizeof(n[0]))
+
+#if (DDR_TYPE == 1)
+static dmc_reg_t dmc_reg_cfg[] = {
+	{T_REFI,	0x186,		0x186},
+	{T_RFC,		0x230024,	0x230024},
+	{T_RFC,		0x540024,	0x540024},
+	{T_MRR,		0x2,		0x2},
+	{T_MRW,		0x5,		0x5},
+	{T_RCD,		0x8,		0x8},
+	{T_RAS,		0x11,		0x11},
+	{T_RP,		0x8,		0x8},
+	{T_RPALL,	0x9,		0x9},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0x4,		0x4},
+	{T_RTW,		0xb,		0xb},
+	{T_RTP,		0x6,		0x6},
+	{T_WR,		0xe,		0xe},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTW,		0x40000,	0x40000},
+	{RD_LATENCY,	0x6,		0x6},
+	{WR_LATENCY,	0x3,		0x3},
+	{T_RDDATA_EN,	0x3,		0x3},
+	{T_PHYWRLAT,	0x101,		0x101},
+	{T_PHYWRLAT,	0x101,		0x101},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0x80003,	0x80003},
+	{T_ESR,		0x6,		0x6},
+	{T_XSR,		0x1000058,	0x1000058},
+	{T_XSR,		0x580058,	0x580058},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{T_EP,		0x5,		0x5},
+	{RDLVL_CTRL,	0x1010,		0x1010},
+	{RDLVL_CTRL,	0x1110,		0x1110},
+	{RDLVL_CTRL,	0x11110,	0x11110},
+	{REFRESH_CTRL,	0x0,		0x0},
+	{REFRESH_CTRL,	0x0,		0x0},
+	{ECC_CTRL,	0x0,		0x0},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+};
+#elif (DDR_TYPE == 2)
+static dmc_reg_t dmc_reg_cfg[] = {
+	{T_REFI,	0x3f,		0x3f},
+	{T_RFC,		0x230024,	0x230024},
+	{T_RFC,		0x540024,	0x540024},
+	{T_MRR,		0x3f,		0x3f},
+	{T_MRW,		0x3f,		0x3f},
+	{T_RCD,		0x8,		0x8},
+	{T_RAS,		0x11,		0x11},
+	{T_RP,		0x8,		0x8},
+	{T_RPALL,	0x9,		0x9},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0xf,		0xf},
+	{T_RTW,		0x1f,		0x1f},
+	{T_RTP,		0x6,		0x6},
+	{T_WR,		0xe,		0xe},
+	{T_WTR,		0x4001f,	0x4001f},
+	{T_WTR,		0x4001f,	0x4001f},
+	{T_WTW,		0x40000,	0x40000},
+	{RD_LATENCY,	0x8,		0x8},
+	{WR_LATENCY,	0x4,		0x4},
+	{T_RDDATA_EN,	0x8,		0x8},
+	{T_PHYWRLAT,	0x103,		0x103},
+	{T_PHYWRLAT,	0x103,		0x103},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0x80003,	0x80003},
+	{T_ESR,		0x6,		0x6},
+	{T_XSR,		0x1000058,	0x1000058},
+	{T_XSR,		0x580058,	0x580058},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{T_EP,		0x5,		0x5},
+	{RDLVL_CTRL,	0x1010,		0x1010},
+	{RDLVL_CTRL,	0x1110,		0x1110},
+	{RDLVL_CTRL,	0x11110,	0x11110},
+	{REFRESH_CTRL,	0x1,		0x1},
+	{ECC_CTRL,	0x0,		0x0},
+	{QOSX_CTRL7,	0x0f, 		0x0f},
+	{TURNAROUND_PRIO,0x1A, 		0x1A},
+	{HIT_PRIO,	0x1A, 		0x1A},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+};
+#elif (DDR_TYPE == 3)
+static dmc_reg_t dmc_reg_cfg[] = {
+	{QOSX_CTRL7,	0x08, 		0x08},
+	{TURNAROUND_PRIO,0x1A, 		0x0},
+	{HIT_PRIO,	0x1A, 		0x0},
+	{T_REFI,	0x186,		0x3f},
+	{QUEUE_CTRL,	0xffff,		0x0},
+	{T_RFC,		0x23008c,	0x23008c},
+	{T_RFC,		0x8c008c,	0x8c008c},
+	{T_MRR,		0x4,		0x4},
+	{T_MRW,		0xc,		0xc},
+	{T_RCD,		0x6,		0x6},
+	{T_RAS,		0xf,		0xf},
+	{T_RP,		0x6,		0x6},
+	{T_RPALL,	0x6,		0x5},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0x6,		0x6},
+//	{T_RTW,		0x7,		0x6},
+	{T_RTW,		0x0c,		0x6},// turn for now
+	{T_RTW,		0x1f,		0x1f},//for low speed
+	{T_RTP,		0x4,		0x4},
+	{T_WR,		0xf,		0x10},
+	{T_WTR,		0x4000d,	0x4000d},
+	{T_WTR,		0x6000d,	0x6000f},
+//	{T_WTR,		0x6001f,	0x6001f},//for low speed
+	{T_WTW,		0x60000,	0x60000},
+	{RD_LATENCY,	0x5,		0x5},
+	{WR_LATENCY,	0x5,		0x5},
+	{T_RDDATA_EN,	0x8,		0x3},
+	{T_PHYWRLAT,	0x102,		0x102},
+	{T_PHYWRLAT,	0x102,		0x103},
+	{T_EP,		0x3,		0x3},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0xa0003,	0xa0003},
+	{T_ESR,		0x4,		0x4},
+	{T_XSR,		0x1000090,	0x1000090},
+	{T_XSR,		0x2000090,	0x2000090},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{ECC_CTRL,	0x0,		0x0},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+};
+#else
+#error "Wrong DDR Type"
+#endif
+
+void config_ddr_phy(UINT16 flag)
+{
+	int wait_idle;
+	UINT16 __attribute__((unused)) dll_off;
+
+	wait_idle = DF_DELAY + 16;
+	dll_off = flag & DDR_FLAGS_DLLOFF;
+
+	while (wait_idle--);
+
+#if (DDR_TYPE == 1)
+	*((volatile UINT32*)(PHY_REG_BASE + CTRL_DELAY * 4)) = 1;
+	printf("ddr1 phy init done!\n");
+#elif (DDR_TYPE ==2)
+	*((volatile UINT32*)(PHY_REG_BASE + USE_ADDR * 4)) = 0;
+	*((volatile UINT32*)(PHY_REG_BASE + DATA_WRITE_ENABLE_REG *4))  = 0xf;
+	*((volatile UINT32*)(PHY_REG_BASE + DATA_ODT_ENABLE_REG *4))  = 0xf;
+	*((volatile UINT32*)(PHY_REG_BASE + WRITE_DATA_LAT *4))  = 0x0;
+	*((volatile UINT32*)(PHY_REG_BASE + WRITE_ENABLE_LAT *4))  = 0x0;
+	*((volatile UINT32*)(PHY_REG_BASE + WDELAY_SEL *4))  = 0x7;
+	*((volatile UINT32*)(PHY_REG_BASE + RDELAY_SEL *4))  = 0x6;
+	*((volatile UINT32*)(PHY_REG_BASE + DQOUT_ENABLE_LAT *4))  = 0x1;
+	printf("ddr2 phy init done!\n");
+#else
+	*((volatile UINT32*)(PHY_REG_BASE + DMC_READY *4))  = 0x0;
+	*((volatile UINT32*)(PHY_REG_BASE + RESET_DDR3 * 4)) = 1;
+
+	if (dll_off)
+		*((volatile UINT32*)(PHY_REG_BASE + WRITE_DATA_LAT * 4)) = 1;
+
+	*((volatile UINT32*)(PHY_REG_BASE + DDR3_USED * 4)) = 1;
+	*((volatile UINT32*)(PHY_REG_BASE + WDELAY_SEL * 4)) = 3;
+
+	if (!dll_off){
+		*((volatile UINT32*)(PHY_REG_BASE + PHY_RDLAT * 4)) = 7;
+		*((volatile UINT32*)(PHY_REG_BASE + CTRL_DELAY * 4)) =2;
+		*((volatile UINT32*)(PHY_REG_BASE + WRITE_ENABLE_LAT * 4)) =2;
+		*((volatile UINT32*)(PHY_REG_BASE + WRITE_DATA_LAT * 4)) = 3;
+		*((volatile UINT32*)(PHY_REG_BASE + DQOUT_ENABLE_LAT * 4)) = 3;
+	}else
+		*((volatile UINT32*)(PHY_REG_BASE + DQOUT_ENABLE_LAT * 4)) = 1;
+
+	*((volatile UINT32*)(PHY_REG_BASE + DATA_ODT_ENABLE_REG *4))  = 0xf;
+	*((volatile UINT32*)(PHY_REG_BASE + DATA_WRITE_ENABLE_REG *4))  = 0xf;
+	
+	serial_puts("ddr3 phy init done!\n");
+#endif
+}
+
+void config_dmc400(UINT16 flag, UINT32 para)
+{
+	int i, wait_idle;
+	UINT32 val, tmp;
+	volatile UINT32 *addr;
+	UINT16 __attribute__((unused)) dll_off, lpw, odt, ron;
+	UINT32 mem_width, col_bits, row_bits, bank_bits;
+
+	dll_off = flag & DDR_FLAGS_DLLOFF;
+	lpw = flag & DDR_FLAGS_LOWPWR;
+	odt = (flag & DDR_FLAGS_ODT_MASK) >> DDR_FLAGS_ODT_SHIFT;
+	ron = (flag & DDR_FLAGS_RON_MASK) >> DDR_FLAGS_RON_SHIFT;
+	mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;
+	bank_bits = (para & DDR_PARA_BANK_BITS_MASK) >> DDR_PARA_BANK_BITS_SHIFT;
+	row_bits = (para & DDR_PARA_ROW_BITS_MASK) >> DDR_PARA_ROW_BITS_SHIFT;
+	col_bits = (para & DDR_PARA_COL_BITS_MASK) >> DDR_PARA_COL_BITS_SHIFT;
+
+
+	wait_idle = 0x4e;
+	while (wait_idle--);
+
+	for (i=0; i<ARRAY_NUM(dmc_reg_cfg); i++) {
+		addr = (volatile UINT32*)(DMC_REG_BASE + dmc_reg_cfg[i].reg_offset);
+		if (dll_off)
+			val = dmc_reg_cfg[i].dll_off_val;
+		else
+			val = dmc_reg_cfg[i].dll_on_val;
+
+		*addr = val;
+		wait_idle = 0x5;
+		while (wait_idle--);
+	}
+
+#if (DDR_TYPE == 3)
+	//config low power control register
+	if (lpw) {
+		addr = (volatile UINT32*)(DMC_REG_BASE + LOWPWR_CTRL);//0x20
+		*addr = 0x48;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_ESR);//0x260
+		*addr = 0xa;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_XSR);//0x264
+		*addr = 0x200;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_SRCKD);//0x268
+		*addr = 0xa;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_CKSRD);//0x26C
+		*addr = 0xa;
+		wait_idle = 0x5;
+		while (wait_idle--);	
+	}
+#elif (DDR_TYPE == 2)
+	addr = (volatile UINT32*)(DMC_REG_BASE + LOWPWR_CTRL);//0x20
+	*addr = 0x38;
+	wait_idle = 0x5;
+	while (wait_idle--);
+#endif
+
+	//config format control register
+	addr = (volatile UINT32*)(DMC_REG_BASE + FORMAT_CTRL);
+	val = *addr;
+	val &= ~0xf;
+	if (mem_width == 2)
+		val |= 0x2; //for 32bit DDR
+	else if ((mem_width == 1) || (mem_width == 0))
+		val |= 0x1; //for 16bit & 8bit DDR
+	else
+		printf("unsupported DDR width: %lx\n", mem_width);
+	*addr = val;
+
+	printf("format ctrl value: %lx\n", val);
+
+	wait_idle = 0x1d;
+	while (wait_idle--);
+
+	//config address control register
+	addr = (volatile UINT32*)(DMC_REG_BASE + ADDR_CTRL);
+	if (mem_width == 2)
+		tmp = col_bits; //for 32bit
+	else if (mem_width == 1)
+		tmp = col_bits - 1; //for 16bit
+	else if (mem_width == 0)
+		tmp = col_bits - 2; //for 8bit
+	else {
+		printf("unsupported DDR width: %lx\n", mem_width);
+		tmp = col_bits;
+	}
+	val = (bank_bits << 16) | (row_bits << 8) | tmp;
+
+	*addr = val;
+
+	printf("address ctrl value: %lx\n", val);
+	wait_idle = 0x5;
+	while (wait_idle--);
+
+	//config decode control register
+	addr = (volatile UINT32*)(DMC_REG_BASE + DECODE_CTRL);
+	tmp = 12 - (8 + col_bits + mem_width);
+	if (tmp < 8)
+		val = tmp << 4;
+	else
+		printf("unsupported stripe decode: %lx\n", tmp);
+	*addr = val;
+
+	printf("decode ctrl value: %lx\n", val);
+	wait_idle = 0x6;
+	while (wait_idle--);
+
+	wait_idle = DF_DELAY;
+	while (wait_idle--);
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+	*addr = 0x0;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0;
+#elif (DDR_TYPE == 2)
+	val = 0;
+#else
+	//config MR2
+	if (dll_off)
+		val = 0x10020008;
+	else
+		val = 0x10020000;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x20000000;
+#elif (DDR_TYPE == 2)
+	val = 0x1000003f;
+#else
+	//config MR3
+	val = 0x10030000;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x30000000;
+#elif (DDR_TYPE == 2)
+	val = 0x1000ff0a;
+#else
+	//config MR1 ODT [9,6,2] RON [5,1] DLLOFF [0]
+	val = 0x10010000;
+	val |= (odt & 0x4)<<7 | (odt & 0x2)<<5 | (odt & 0x1)<<2;
+	val |= (ron & 0x2)<<4 | (ron & 0x1)<<1;
+	if (dll_off)
+		val |= 0x1;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x30000000;
+#elif (DDR_TYPE == 2)
+	val = 0x10008301;
+#else
+	//config MR0
+	val = 0x10000520;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x10000033;
+#elif (DDR_TYPE == 2)
+	val = 0x10000602;//0ld 0x10000102
+#else
+	val = 0x50000400;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+#if (DDR_TYPE == 2)
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+	val = 0x10000103;//0ld 0x10000102
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+#endif
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x10020000;
+#elif (DDR_TYPE == 2)
+	val = 0x30000000;
+#else
+	val = 0x30000000;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+#if (DDR_TYPE == 2)
+/* zhangli for MCP */
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+	*addr = 0x10000103;
+	wait_idle = DF_DELAY + 0x9;
+	while (wait_idle--);
+#endif
+
+#if (DDR_TYPE == 2)
+	addr = (volatile UINT32*)(DMC_REG_BASE + MEMC_CMD);
+	val = 0x4;
+	*addr = val;
+#endif
+
+	//config ECC control
+	wait_idle = 0x6;
+	while (wait_idle--);
+	addr = (volatile UINT32*)(DMC_REG_BASE + ECC_CTRL);
+	val = 0x0;
+	*addr = val;
+	wait_idle = 0x8;
+	while (wait_idle--);
+
+	//config MEMC CMD
+	addr = (volatile UINT32*)(DMC_REG_BASE + MEMC_CMD);
+	val = 0x3;
+	*addr = val;
+
+	//READ MEMC STATUS
+	addr = (volatile UINT32*)(DMC_REG_BASE + MEMC_STATUS);
+	val = 0;
+	do {
+		val = *addr;
+		//printf("MEMC_STATUS value: %x\n", val);
+	} while (val != 3);
+}
+
+void axi_prio_init(void)
+{
+	*(volatile UINT32*)(0x20900100) = 0xaa0000aa;
+	*(volatile UINT32*)(0x21054100) = 0x00000008;
+	*(volatile UINT32*)(0x21054104) = 0x00000008;
+}
+
+void axi_outstandings_init(void)
+{
+	*(volatile UINT32*)(0x2104210C) = 0x00000060;
+	*(volatile UINT32*)(0x21042110) = 0x00000300;
+}
+
+int ddr_init(UINT16 flags, UINT32 para)
+{
+	UINT16 dll_off;
+	UINT32 mem_width;
+
+	axi_prio_init();
+	//axi_outstandings_init();
+
+	dll_off = flags & DDR_FLAGS_DLLOFF;
+	mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;
+
+	switch (mem_width) {
+		case 0:
+			printf("8bit ");
+			break;
+		case 1:
+			printf("16bit ");
+			break;
+		case 2:
+			printf("32bit ");
+			break;
+	}
+	if (dll_off)
+		printf("dll-off Mode ...\n");
+	else
+		printf("dll-on Mode ...\n");
+
+	config_ddr_phy(flags);
+	config_dmc400(flags, para);
+	printf("dram init done ...\n");
+
+	return 0;
+}
+
diff --git a/board/rda/rda8810h/ddr3.h b/board/rda/rda8810h/ddr3.h
new file mode 100644
index 0000000000..7481954144
--- /dev/null
+++ b/board/rda/rda8810h/ddr3.h
@@ -0,0 +1,50 @@
+#ifndef _SYS_DDR3_H_
+#define _SYS_DDR3_H_
+
+#include "clock_config.h"
+
+/*
+ * defination of ddr flags
+ */
+/* [Debug] DLL off mode, 0 is dll on mode */
+#define DDR_FLAGS_DLLOFF               0x8000
+/* [Debug] LowSpeed mode*/
+#define DDR_FLAGS_RESERVE              0x4000
+/* DDR LowPower mode */
+#define DDR_FLAGS_LOWPWR               0x2000
+/* ODT: 000--Null 001--60 010--120 011--40 100--20 101--30 */
+#define DDR_FLAGS_ODT(n)               (((n)<<0)&0x0007)
+#define DDR_FLAGS_ODT_SHIFT            0
+#define DDR_FLAGS_ODT_MASK             0x0007
+/* RON: 00--40 01--30 */
+#define DDR_FLAGS_RON(n)               (((n)<<3)&0x0018)
+#define DDR_FLAGS_RON_SHIFT            3
+#define DDR_FLAGS_RON_MASK             0x0018
+
+/*
+ * defination of ddr parameters
+ */
+#define DDR_PARA_CHIP_BITS(n)          (((n)<<0)&0x00000003)
+#define DDR_PARA_CHIP_BITS_SHIFT       0
+#define DDR_PARA_CHIP_BITS_MASK        0x00000003
+/* memory width 0--8bit 1--16bit 2--32bit */
+#define DDR_PARA_MEM_BITS(n)           (((n)<<2)&0x0000000c)
+#define DDR_PARA_MEM_BITS_SHIFT        2
+#define DDR_PARA_MEM_BITS_MASK         0x0000000c
+/* 2--4banks 3--8banks */
+#define DDR_PARA_BANK_BITS(n)          (((n)<<4)&0x000000f0)
+#define DDR_PARA_BANK_BITS_SHIFT       4
+#define DDR_PARA_BANK_BITS_MASK        0x000000f0
+/* 2--13rbs 3--14rbs 4--15rbs 5--16rbs */
+#define DDR_PARA_ROW_BITS(n)           (((n)<<8)&0x00000f00)
+#define DDR_PARA_ROW_BITS_SHIFT        8
+#define DDR_PARA_ROW_BITS_MASK         0x00000f00
+/* 0--8cbs 1--9cbs 2--10cbs 3--11cbs 4--12cbs */
+#define DDR_PARA_COL_BITS(n)           (((n)<<12)&0x0000f000)
+#define DDR_PARA_COL_BITS_SHIFT        12
+#define DDR_PARA_COL_BITS_MASK         0x0000f000
+
+int ddr_init(UINT16 flags, UINT32 para);
+
+#endif /* _SYS_DDR3_H_ */
+
diff --git a/board/rda/rda8810h/ddr3_init.h b/board/rda/rda8810h/ddr3_init.h
new file mode 100644
index 0000000000..402375d269
--- /dev/null
+++ b/board/rda/rda8810h/ddr3_init.h
@@ -0,0 +1,101 @@
+#ifndef _SYS_RAM_INIT_H_
+#define _SYS_RAM_INIT_H_
+
+#define MEMC_STATUS			0x000
+#define MEMC_CONFIG			0x004
+#define MEMC_CMD			0x008
+#define ADDR_CTRL			0x010
+#define DECODE_CTRL			0x014
+#define FORMAT_CTRL			0x018
+#define LOWPWR_CTRL			0x020
+#define TURNAROUND_PRIO			0x030
+#define HIT_PRIO			0x034
+//QOS0~QOS15:038~078
+#define QOSX_CTRL			0x038
+#define QOSX_CTRL7			0x058
+#define QOSX_CTRL15			0x078
+#define TIMEOUT_CTRL			0x07C
+#define QUEUE_CTRL			0x080
+#define WR_PRIO_CTRL			0x088
+#define WR_PRIO_CTRL2			0x08C
+#define RD_PRIO_CTRL			0x090
+#define RD_PRIO_CTRL2			0x094
+#define ACCESS_ADDR_MATCH		0x098
+#define ACCESS_ADDR_MATCH_63_32		0x09C
+#define ACCESS_ADDR_MASK		0x0A0
+#define ACCESS_ADDR_MASK_63_32		0x0A4
+
+#define CHANNEL_STATUS			0x100
+#define DIRECT_CMD			0x108
+#define MR_DATA				0x110
+#define REFRESH_CTRL			0x120
+#define INTR_CTRL			0x128
+#define INTR_CLR			0x130
+#define INTR_STATUS			0x138
+#define INTR_INFO			0x140
+#define ECC_CTRL			0x148
+
+#define T_REFI				0x200
+#define T_RFC				0x204
+#define T_MRR				0x208
+#define T_MRW				0x20C
+#define T_RCD				0x218
+#define T_RAS				0x21C
+#define T_RP				0x220
+#define T_RPALL				0x224
+#define T_RRD				0x228
+#define T_FAW				0x22C
+#define RD_LATENCY			0x230
+#define T_RTR				0x234
+#define T_RTW				0x238
+#define T_RTP				0x23C
+#define WR_LATENCY			0x240
+#define T_WR				0x244
+#define T_WTR				0x248
+#define T_WTW				0x24C
+#define T_ECKD				0x250
+#define T_XCKD				0x254
+#define T_EP				0x258
+#define T_XP				0x25C
+#define T_ESR				0x260
+#define T_XSR				0x264
+#define T_SRCKD				0x268
+#define T_CKSRD				0x26C
+
+#define T_RDDATA_EN			0x300
+#define T_PHYWRLAT			0x304
+#define RDLVL_CTRL			0x308
+#define RDLVL_DIRECT			0x310
+#define T_RDLVL_EN			0x318
+#define T_RDLVL_RR			0x31C
+#define WRLVL_CTRL			0x328
+#define WRLVL_DIRECT			0x330
+#define T_WRLVL_EN			0x338
+#define T_WRLVL_WW			0x33C
+
+#define PHY_PWR_CTRL			0x348
+#define PHY_UPD_CTRL			0x350
+
+#define USER_STATUS			0x400
+#define USER_CONFIG0			0x404
+#define USER_CONFIG1			0x408
+
+#define INTEG_CFG			0xE00
+#define INTEG_OUTPUTS			0xE08
+
+#define PERIPH_ID_0			0xFE0
+#define PERIPH_ID_1			0xFE4
+#define PERIPH_ID_2			0xFE8
+#define PERIPH_ID_3			0xFEC
+#define COMPONENT_ID_0			0xFF0
+#define COMPONENT_ID_1			0xFF4
+#define COMPONENT_ID_2			0xFF8
+#define COMPONENT_ID_3			0xFFC
+
+typedef struct {
+	UINT32 reg_offset;
+	UINT32 dll_on_val;
+	UINT32 dll_off_val;
+} dmc_reg_t;
+
+#endif /* _SYS_RAM_INIT_H_ */
diff --git a/board/rda/rda8810h/debug.h b/board/rda/rda8810h/debug.h
new file mode 100644
index 0000000000..1d4f03bedb
--- /dev/null
+++ b/board/rda/rda8810h/debug.h
@@ -0,0 +1,9 @@
+#ifndef _DEBUG_H_
+#define _DEBUG_H_
+
+void print_u8(u8 ch);
+void print_u16(u16 data);
+void print_u32(u32 data);
+void dump_buf(u8 *buf, u32 size);
+
+#endif /* _DEBUG_H_ */
diff --git a/board/rda/rda8810h/hal_config.c b/board/rda/rda8810h/hal_config.c
new file mode 100644
index 0000000000..ade97c4b5a
--- /dev/null
+++ b/board/rda/rda8810h/hal_config.c
@@ -0,0 +1,1451 @@
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//            Copyright (C) 2013, RDA Microeletronics.                        //
+//                            All Rights Reserved                             //
+//                                                                            //
+//      This source code is the property of RDA Microeletronics and is        //
+//      confidential.  Any  modification, distribution,  reproduction or      //
+//      exploitation  of  any content of this file is totally forbidden,      //
+//      except  with the  written permission  of  RDA Microeletronics.        //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//  $HeadURL: http://svn.rdamicro.com/svn/developing1/Sources/chip/branches/8810/hal/8810/src/hal_config.c $ //
+//    $Author: huazeng $                                                        //
+//    $Date: 2013-08-31 17:48:58 +0800 (Sat, 31 Aug 2013) $                     //
+//    $Revision: 21005 $                                                          //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+/// @file hal_config.c
+/// Implementation of HAL initialization related with the particular instance
+/// of the IP.
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+
+/* uboot */
+#include <common.h>
+
+/* common */
+#include <asm/arch/rda_iomap.h>
+#include <asm/arch/hwcfg.h>
+#include <asm/arch/chip_id.h>
+#include <asm/arch/cs_types.h>
+#include <asm/arch/global_macros.h>
+#include <asm/arch/reg_gpio.h>
+
+/* device */
+#include "hal_sys.h"
+#include "halp_sys.h"
+#include "halp_gpio.h"
+#include "bootp_mode.h"
+#include "hal_config.h"
+#include "hal_ap_gpio.h"
+#include "hal_ap_config.h"
+#include <asm/arch/reg_cfg_regs.h>
+
+/* target */
+#include "tgt_board_cfg.h"
+#include "tgt_ap_gpio_setting.h"
+#define HAL_ASSERT(cond, fmt, ...) \
+    if(!(cond)) { \
+        hal_assert(fmt, ##__VA_ARGS__); \
+        g_halConfigError = TRUE; \
+    }
+
+//// =============================================================================
+////  GLOBAL VARIABLES
+//// =============================================================================
+PRIVATE CONST UINT8 g_halCfgSimOrder[] = { TGT_SIM_ORDER };
+PRIVATE HAL_CFG_CONFIG_T hal_cfg = TGT_HAL_CONFIG;
+PRIVATE UINT32 g_bootBootMode = 0;
+PRIVATE BOOL g_halConfigError = FALSE;
+
+
+// =============================================================================
+//  FUNCTIONS
+// =============================================================================
+// HAL_ASSERT
+PRIVATE VOID hal_assert(const char *fmt, ...)
+{
+    va_list args;
+    puts("\n#-------Board Mux config found error-------#\n");
+    va_start(args, fmt);
+    vprintf(fmt, args);
+    putc('\n');
+    puts("--------------------------------------------\n\n");
+    va_end(args);
+}
+
+// =============================================================================
+// hal_BoardSimUsed
+// -----------------------------------------------------------------------------
+/// Check whether a SIM card interface is used.
+// ============================================================================
+PRIVATE BOOL hal_BoardSimUsed(UINT32 simId)
+{
+    UINT32 i;
+    for (i=0; i<ARRAY_SIZE(g_halCfgSimOrder) && i<NUMBER_OF_SIM; i++)
+    {
+        if (g_halCfgSimOrder[i] == simId)
+        {
+            return TRUE;
+        }
+    }
+
+    return FALSE;
+}
+
+#if 0
+// =============================================================================
+// hal_BoardConfigClk32k
+// -----------------------------------------------------------------------------
+/// Configure CLK_32K output.
+/// @param enable TRUE to configure, and FALSE to disable.
+// ============================================================================
+PROTECTED VOID hal_BoardConfigClk32k(BOOL enable)
+{
+    HAL_ASSERT(g_halCfg->useClk32k == TRUE, "32K clock is not configured");
+
+    if (enable)
+    {
+        // Setup the pin as 32K clock output
+        hwp_configRegs->Alt_mux_select =
+            (hwp_configRegs->Alt_mux_select & ~CFG_REGS_GPO_2_MASK) |
+            CFG_REGS_GPO_2_CLK_32K;
+    }
+    else
+    {
+        // Setup the pin as GPO (and low ouput has been
+        // configured in hal_BoardSetup())
+        hwp_configRegs->Alt_mux_select =
+            (hwp_configRegs->Alt_mux_select & ~CFG_REGS_GPO_2_MASK) |
+            CFG_REGS_GPO_2_GPO_2;
+    }
+}
+#endif
+
+// =============================================================================
+// hal_BoardSetupGeneral
+// -----------------------------------------------------------------------------
+/// Apply board dependent configuration to HAL for general purpose
+/// @param halCfg Pointer to HAL configuration structure (from the target
+/// module).
+// ============================================================================
+PROTECTED VOID hal_BoardSetupGeneral(CONST HAL_CFG_CONFIG_T* halCfg)
+{
+    UINT32 altMux = 0;
+    UINT32 altMux2 = 0;
+
+    UINT32 availableGpo_A = 0;
+
+    UINT32 availableGpio_C = 0;
+    UINT32 availableGpio_A = 0;
+    UINT32 availableGpio_B = 0;
+    UINT32 availableGpio_D = 0;
+    UINT32 availableGpio_E = 0;
+
+    UINT32 bootModeGpio_C = 0;
+    UINT32 bootModeGpio_A = 0;
+    UINT32 bootModeGpio_B = 0;
+    UINT32 bootModeGpio_D = 0;
+    UINT32 bootModeGpio_E = 0;
+
+    UINT32 noConnectMask_C = 0;
+    UINT32 noConnectMask_A = 0;
+    UINT32 noConnectMask_B = 0;
+    UINT32 noConnectMask_D = 0;
+    UINT32 noConnectMask_E = 0;
+
+    UINT32 gpoClr_A = 0;
+
+#ifdef CONFIG_RDA_FPGA
+
+    // no muxing, do nothing
+    // add support for sd card
+    hwp_configRegs->BB_GPIO_Mode &= ~(0x3F<<9);
+
+#else // !FPGA
+
+    // GPIOs as boot mode pins
+    bootModeGpio_C = HAL_GPIO_BIT(1)
+                   | HAL_GPIO_BIT(2)
+                   | HAL_GPIO_BIT(3)
+                   | HAL_GPIO_BIT(4)
+                   | HAL_GPIO_BIT(5);
+    bootModeGpio_A = HAL_GPIO_BIT(4)
+                   | HAL_GPIO_BIT(5)
+                   | HAL_GPIO_BIT(6)
+                   | HAL_GPIO_BIT(7);
+    bootModeGpio_B = HAL_GPIO_BIT(0);
+    bootModeGpio_D = 0;
+    bootModeGpio_E = 0;
+
+    // Available GPIOs
+    availableGpio_C |= HAL_GPIO_BIT(0)
+                     | HAL_GPIO_BIT(1)
+                     | HAL_GPIO_BIT(2)
+                     | HAL_GPIO_BIT(3)
+                     | HAL_GPIO_BIT(4)
+                     | HAL_GPIO_BIT(5);
+    // Volume down/up keys
+    availableGpio_D |= HAL_GPIO_BIT(5)
+                     | HAL_GPIO_BIT(6);
+
+    // Boot modes
+    BOOL spiFlashCam = FALSE;
+    BOOL spiFlashNand = FALSE;
+    if (g_bootBootMode & BOOT_MODE_BOOT_SPI)
+    {
+        if (g_bootBootMode & BOOT_MODE_SPI_PIN_NAND)
+        {
+            HAL_ASSERT((g_bootBootMode & BOOT_MODE_BOOT_EMMC),
+                "Emmc boot pin should be pulled up to boot on SPI flash over NAND pins");
+            spiFlashNand = TRUE;
+        }
+        else
+        {
+            spiFlashCam = TRUE;
+        }
+    }
+
+    //UINT32 metalId = rda_metal_id_get();
+    UINT32 emmcBootModeMask;
+    if (1) //metalId < 0x02)
+    {
+        emmcBootModeMask = BOOT_MODE_BOOT_EMMC
+                         | BOOT_MODE_BOOT_SPI
+                         | BOOT_MODE_BOOT_SPI_NAND;
+    }
+    else
+    {
+        emmcBootModeMask = BOOT_MODE_BOOT_EMMC
+                         | BOOT_MODE_BOOT_SPI;
+    }
+    if ((g_bootBootMode & emmcBootModeMask) == BOOT_MODE_BOOT_EMMC)
+    {
+        // Boot from EMMC
+        HAL_ASSERT(halCfg->sdmmcCfg.sdmmc3Used, "SDMMC3 (EMMC) should be used");
+    }
+
+    if (1) //metalId < 0x02)
+    {
+        if ( (g_bootBootMode & (BOOT_MODE_BOOT_SPI|BOOT_MODE_BOOT_SPI_NAND))
+             == BOOT_MODE_BOOT_SPI_NAND ||
+             (g_bootBootMode & (BOOT_MODE_BOOT_SPI|BOOT_MODE_NAND_PAGE_SIZE_L))
+             == (BOOT_MODE_BOOT_SPI|BOOT_MODE_NAND_PAGE_SIZE_L)
+           )
+        {
+            // Boot from SDMMC1
+            HAL_ASSERT(halCfg->sdmmcCfg.sdmmcUsed, "SDMMC1 should be used");
+        }
+    }
+
+    // For convenience, we do not consider spiFlashCam at present.
+    // We assume that SPI flash always uses parallel nand pins.
+#if 0
+    BOOL parallelNandUsed = halCfg->parallelNandUsed;
+#else
+    BOOL parallelNandUsed = !spiFlashNand && !halCfg->sdmmcCfg.sdmmc3Used;
+#endif
+    BOOL nand8_15Cam = FALSE;
+    BOOL nand8_15Lcd = FALSE;
+    if ((g_bootBootMode & (BOOT_MODE_BOOT_SPI|BOOT_MODE_BOOT_EMMC)) == 0)
+    {
+        HAL_ASSERT(parallelNandUsed, "Parallel NAND should be used");
+    }
+    if (parallelNandUsed)
+    {
+        HAL_ASSERT(!spiFlashNand, "SPI flash uses parallel NAND pins");
+        HAL_ASSERT(!halCfg->sdmmcCfg.sdmmc3Used,
+            "SDMMC3 (EMMC) uses parallel NAND pins");
+        if ((g_bootBootMode & BOOT_MODE_NAND_8BIT) == 0)
+        {
+            if (g_bootBootMode & BOOT_MODE_NAND_HIGH_PIN_CAM)
+            {
+                HAL_ASSERT(!spiFlashCam, "SPI flash uses NAND 8-15 bits on cam pins");
+                nand8_15Cam = TRUE;
+            }
+            else
+            {
+                nand8_15Lcd = TRUE;
+            }
+        }
+    }
+
+    if (!parallelNandUsed)
+    {
+        availableGpio_D |= HAL_GPIO_BIT(9);
+
+#ifdef NAND_IO_RECONFIG_WORKROUND
+        if (spiFlashNand)
+        {/*GPIO_B:25,26,27,28,29; GPIO_D:4  the output level is inverted*/
+            availableGpio_B |= HAL_GPIO_BIT(25)
+                             | HAL_GPIO_BIT(26)
+                             | HAL_GPIO_BIT(27)
+                             | HAL_GPIO_BIT(28)
+                             | HAL_GPIO_BIT(29);
+            availableGpio_D |= HAL_GPIO_BIT(4);
+        }else{
+	     availableGpio_D |= HAL_GPIO_BIT(8);
+	}
+#else
+        if (!spiFlashNand)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(25)
+                             | HAL_GPIO_BIT(26)
+                             | HAL_GPIO_BIT(27)
+                             | HAL_GPIO_BIT(28)
+                             | HAL_GPIO_BIT(29);
+            availableGpio_D |= HAL_GPIO_BIT(4)
+                             | HAL_GPIO_BIT(8);
+        }
+#endif
+
+        if (!halCfg->sdmmcCfg.sdmmc3Used)
+        {
+            availableGpio_D |= HAL_GPIO_BIT(10);
+        }
+    	}
+#ifdef NAND_IO_RECONFIG_WORKROUND
+	else
+	{/*GPIO_B:25,26,27,28,29; GPIO_D:4  the output level is inverted*/
+            availableGpio_B |= HAL_GPIO_BIT(25)
+                             | HAL_GPIO_BIT(26)
+                             | HAL_GPIO_BIT(27)
+                             | HAL_GPIO_BIT(28)
+                             | HAL_GPIO_BIT(29);
+            availableGpio_D |= HAL_GPIO_BIT(4);
+        }
+#endif
+
+    CONST HAL_CFG_CAM_T *camCfg = &halCfg->camCfg;
+    CONST HAL_CFG_CAM_T *cam2Cfg = &halCfg->cam2Cfg;
+    CONST HAL_LCD_MODE_T lcdMode = halCfg->goudaCfg.lcdMode;
+
+    // LCD
+    if (lcdMode == HAL_LCD_MODE_PARALLEL_16BIT)
+    {
+        /* Check LCD 8-15 bits */
+        HAL_ASSERT(!nand8_15Lcd, "NAND uses LCD 8-15 bits");
+        HAL_ASSERT(!halCfg->goudaCfg.lcd8_23Cam2, "Parallel LCD 8-5 bits should use NAND pins only");
+        altMux |= CFG_REGS_LCD_MODE_PARALLEL_16BIT;
+    }
+    else if (lcdMode == HAL_LCD_MODE_DSI)
+    {
+        altMux |= CFG_REGS_LCD_MODE_DSI;
+        availableGpio_A |= HAL_GPIO_BIT(22)
+                         | HAL_GPIO_BIT(23);
+    }
+    else if (lcdMode == HAL_LCD_MODE_RGB_16BIT ||
+             lcdMode == HAL_LCD_MODE_RGB_18BIT ||
+             lcdMode == HAL_LCD_MODE_RGB_24BIT)
+    {
+        /* Check LCD 8-15 bits */
+        if (halCfg->goudaCfg.lcd8_23Cam2)
+        {
+            HAL_ASSERT(!(cam2Cfg->camUsed || cam2Cfg->cam1Used),
+                "Camera2 uses LCD 8-15 bits");
+            altMux2 |= CFG_REGS_RGB_CAM_2_ENABLE;
+        }
+        else
+        {
+            HAL_ASSERT(!nand8_15Lcd, "NAND uses LCD 8-15 bits");
+        }
+        if (lcdMode == HAL_LCD_MODE_RGB_18BIT ||
+            lcdMode == HAL_LCD_MODE_RGB_24BIT)
+        {
+            /* Check LCD 16-23 bits */
+            if (lcdMode == HAL_LCD_MODE_RGB_18BIT && halCfg->goudaCfg.lcd16_17Cs)
+            {
+                HAL_ASSERT(!halCfg->goudaCfg.lcd16_23Cam,
+                    "LCD 16-17 bits have been configured on camera pins");
+                HAL_ASSERT(!(halCfg->goudaCfg.cs0Used || halCfg->goudaCfg.cs1Used),
+                    "LCD CS 0/1 use LCD 16-17 bits");
+                altMux2 |= CFG_REGS_LCD_RGB_17_16_LCD_DATA;
+            }
+            else if (halCfg->goudaCfg.lcd8_23Cam2)
+            {
+                HAL_ASSERT(!halCfg->goudaCfg.lcd16_23Cam,
+                    "LCD 16-23 bits have been configured on camera pins");
+                HAL_ASSERT(halCfg->goudaCfg.lcd16_17Cs,
+                    "LCD 16-17 bits should use LCD CS 0/1");
+                HAL_ASSERT(!(halCfg->goudaCfg.cs0Used || halCfg->goudaCfg.cs1Used),
+                    "LCD CS 0/1 use LCD 16-17 bits");
+                HAL_ASSERT(!(cam2Cfg->camUsed || cam2Cfg->cam1Used),
+                    "Camera2 uses LCD 18-23 bits");
+                altMux2 |= CFG_REGS_LCD_RGB_17_16_LCD_DATA;
+                altMux2 |= CFG_REGS_RGB_CAM_2_ENABLE;
+            }
+            else if (halCfg->goudaCfg.lcd16_23Cam)
+            {
+                HAL_ASSERT(!(halCfg->goudaCfg.lcd16_17Cs || halCfg->goudaCfg.lcd8_23Cam2),
+                    "LCD 16-23 bits have been configured on LCD CS 0/1 and camera2 pins");
+                HAL_ASSERT(
+                    !(camCfg->camMode == HAL_CAM_MODE_PARALLEL &&
+                      (camCfg->camUsed || camCfg->cam1Used)),
+                    "Parallel camera uses LCD 16-23 bits");
+                HAL_ASSERT(
+                    !(halCfg->i2cCfg.i2c2Used && halCfg->i2cCfg.i2c2PinsCam),
+                    "I2C2 uses LCD 22-23 bits");
+                HAL_ASSERT(!spiFlashCam, "SPI flash uses LCD 16-21 bits");
+                HAL_ASSERT(!nand8_15Cam, "NAND uses LCD 16-23 bits");
+                HAL_ASSERT(
+                    !(camCfg->camMode == HAL_CAM_MODE_CSI &&
+                      ((camCfg->camUsed && camCfg->camCsiId == HAL_CAM_CSI_1) ||
+                       (camCfg->cam1Used && camCfg->cam1CsiId == HAL_CAM_CSI_1))),
+                    "Camera CSI1 uses LCD 16-21 bits");
+                altMux |= CFG_REGS_RGB_CAM_ENABLE;
+            }
+            else
+            {
+                HAL_ASSERT(!parallelNandUsed, "NAND uses LCD 16-23 bits");
+                HAL_ASSERT(!halCfg->sdmmcCfg.sdmmc3Used, "SDMMC3 uses LCD 16-23 bits");
+                altMux |= CFG_REGS_RGB_CAM_DISABLE;
+            }
+        }
+        altMux |= CFG_REGS_LCD_MODE_RGB_24BIT;
+    }
+    else if (lcdMode == HAL_LCD_MODE_SPI)
+    {
+        HAL_ASSERT(!(halCfg->goudaCfg.cs0Used || halCfg->goudaCfg.cs1Used),
+            "LCD CS 0/1 use SPI LCD pins");
+        HAL_ASSERT((halCfg->usedGpo_A & (HAL_GPO_BIT(3)|HAL_GPO_BIT(4))) == 0,
+            "GPO 3/4 use SPI LCD pins");
+        altMux |= CFG_REGS_SPI_LCD_SPI_LCD;
+        availableGpio_A |= HAL_GPIO_BIT(18)
+                         | HAL_GPIO_BIT(19)
+                         | HAL_GPIO_BIT(20)
+                         | HAL_GPIO_BIT(21);
+    }
+    else
+    {
+        HAL_ASSERT(FALSE, "Lcd mode not defined!");
+    }
+
+    if (lcdMode == HAL_LCD_MODE_DSI ||
+        lcdMode == HAL_LCD_MODE_SPI ||
+        ((lcdMode == HAL_LCD_MODE_RGB_16BIT ||
+          lcdMode == HAL_LCD_MODE_RGB_18BIT ||
+          lcdMode == HAL_LCD_MODE_RGB_24BIT) &&
+         halCfg->goudaCfg.lcd8_23Cam2))
+    {
+        if (!nand8_15Lcd)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(24)
+                             | HAL_GPIO_BIT(25)
+                             | HAL_GPIO_BIT(26)
+                             | HAL_GPIO_BIT(27)
+                             | HAL_GPIO_BIT(28)
+                             | HAL_GPIO_BIT(29)
+                             | HAL_GPIO_BIT(30)
+                             | HAL_GPIO_BIT(31);
+        }
+    }
+
+    if (halCfg->goudaCfg.cs0Used)
+    {
+        altMux |= CFG_REGS_GPO_4_LCD_CS_0;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_4_GPO_4;
+        availableGpo_A |= HAL_GPO_BIT(4);
+    }
+
+    if (halCfg->goudaCfg.cs1Used)
+    {
+        altMux |= CFG_REGS_GPO_3_LCD_CS_1;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_3_GPO_3;
+        availableGpo_A |= HAL_GPO_BIT(3);
+    }
+
+    // I2C
+    if (!halCfg->i2cCfg.i2cUsed)
+    {
+        availableGpio_B |= HAL_GPIO_BIT(30)
+                         | HAL_GPIO_BIT(31);
+    }
+
+    if (halCfg->i2cCfg.i2c2Used)
+    {
+        if (halCfg->i2cCfg.i2c2PinsCam)
+        {
+            if (camCfg->camUsed)
+            {
+                HAL_ASSERT(camCfg->camPdnRemap == GPIO_NONE &&
+                    camCfg->camRstRemap == GPIO_NONE,
+                    "Cam uses PDN/RST pins");
+            }
+            if (camCfg->cam1Used)
+            {
+                HAL_ASSERT(camCfg->cam1PdnRemap == GPIO_NONE &&
+                    camCfg->cam1RstRemap == GPIO_NONE,
+                    "Cam1 uses PDN/RST pins");
+            }
+            HAL_ASSERT(!nand8_15Cam, "NAND uses cam PDN/RST pins");
+            availableGpio_A |= HAL_GPIO_BIT(0)
+                             | HAL_GPIO_BIT(1);
+            altMux |= CFG_REGS_CAM_I2C2_I2C2;
+        }
+        else
+        {
+            // I2C2 does not use cam pins
+            altMux |= CFG_REGS_CAM_I2C2_CAM;
+        }
+    }
+    else
+    {
+        // I2C2 does not use cam pins
+        altMux |= CFG_REGS_CAM_I2C2_CAM;
+        availableGpio_A |= HAL_GPIO_BIT(0)
+                         | HAL_GPIO_BIT(1);
+    }
+
+    if (halCfg->i2cCfg.i2c3Used)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x18) == 0, "Keyout 3/4 use I2C3 pins");
+        altMux |= CFG_REGS_KEYOUT_3_4_I2C3;
+    }
+    else
+    {
+        altMux |= CFG_REGS_KEYOUT_3_4_KEYOUT_3_4;
+        if ((halCfg->keyOutMask & 0x8) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(6);
+        }
+        if ((halCfg->keyOutMask & 0x10) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(7);
+        }
+    }
+
+    if (halCfg->i2cCfg.modemI2cUsed)
+    {
+        HAL_ASSERT(!halCfg->emacUsed, "EMAC uses modem I2C pins");
+    }
+    else
+    {
+        if (!halCfg->emacUsed)
+        {
+            availableGpio_E |= HAL_GPIO_BIT(0)
+                             | HAL_GPIO_BIT(1);
+        }
+    }
+
+    // Camera
+    if (camCfg->camUsed || camCfg->cam1Used)
+    {
+        if(camCfg->camMode == HAL_CAM_MODE_PARALLEL)
+        {
+            HAL_ASSERT(!spiFlashCam, "SPI flash uses cam pins");
+            HAL_ASSERT(!nand8_15Cam, "NAND 8-15 bits use cam pins");
+            altMux |= CFG_REGS_CSI2_PARALLEL_CAM;
+            availableGpio_B |= HAL_GPIO_BIT(24);
+        }
+        else if (camCfg->camMode == HAL_CAM_MODE_SPI)
+        {
+            altMux |= CFG_REGS_CSI2_SPI_CAM;
+            availableGpio_B |= HAL_GPIO_BIT(14);
+            if (!(spiFlashCam || nand8_15Cam ||
+                  (lcdMode == HAL_LCD_MODE_RGB_24BIT &&
+                   halCfg->goudaCfg.lcd16_23Cam)
+                 )
+               )
+            {
+                availableGpio_B |= HAL_GPIO_BIT(13)
+                                 | HAL_GPIO_BIT(20)
+                                 | HAL_GPIO_BIT(21)
+                                 | HAL_GPIO_BIT(22)
+                                 | HAL_GPIO_BIT(23)
+                                 | HAL_GPIO_BIT(24);
+            }
+        }
+        else if (camCfg->camMode == HAL_CAM_MODE_CSI)
+        {
+            if ((camCfg->camUsed && camCfg->camCsiId == HAL_CAM_CSI_1) ||
+                (camCfg->cam1Used && camCfg->cam1CsiId == HAL_CAM_CSI_1))
+            {
+                HAL_ASSERT(!spiFlashCam, "SPI flash uses CSI1 pins");
+                HAL_ASSERT(!nand8_15Cam, "NAND 8-15 bits use CSI1 pins");
+            }
+            else
+            {
+                // CSI1 is unused
+                if (!(spiFlashCam || nand8_15Cam ||
+                      (lcdMode == HAL_LCD_MODE_RGB_24BIT &&
+                       halCfg->goudaCfg.lcd16_23Cam)
+                     )
+                   )
+                {
+                    availableGpio_B |= HAL_GPIO_BIT(13)
+                                     | HAL_GPIO_BIT(20)
+                                     | HAL_GPIO_BIT(21)
+                                     | HAL_GPIO_BIT(22)
+                                     | HAL_GPIO_BIT(23)
+                                     | HAL_GPIO_BIT(24);
+                }
+            }
+            altMux |= CFG_REGS_CSI2_CSI2;
+            // If CSI2 is unused
+            if (!((camCfg->camUsed && camCfg->camCsiId == HAL_CAM_CSI_2) ||
+                  (camCfg->cam1Used && camCfg->cam1CsiId == HAL_CAM_CSI_2)))
+            {
+                availableGpio_B |= HAL_GPIO_BIT(14)
+                                 | HAL_GPIO_BIT(15)
+                                 | HAL_GPIO_BIT(16)
+                                 | HAL_GPIO_BIT(17)
+                                 | HAL_GPIO_BIT(18)
+                                 | HAL_GPIO_BIT(19);
+            }
+        }
+        else
+        {
+            HAL_ASSERT(FALSE, "Invalid cam mode: %d", camCfg->camMode);
+        }
+
+        // Cam PDN/RST pins
+        if (!(nand8_15Cam ||
+              (lcdMode == HAL_LCD_MODE_RGB_24BIT && halCfg->goudaCfg.lcd16_23Cam) ||
+              (halCfg->i2cCfg.i2c2Used && halCfg->i2cCfg.i2c2PinsCam)
+             )
+           )
+        {
+            if (!((camCfg->camUsed && camCfg->camRstRemap == GPIO_NONE) ||
+                  (camCfg->cam1Used && camCfg->cam1RstRemap == GPIO_NONE)))
+            {
+                availableGpio_B |= HAL_GPIO_BIT(10);
+            }
+            if (!((camCfg->camUsed && camCfg->camPdnRemap == GPIO_NONE) ||
+                  (camCfg->cam1Used && camCfg->cam1PdnRemap == GPIO_NONE)))
+            {
+                availableGpio_B |= HAL_GPIO_BIT(11);
+            }
+        }
+    }
+    else // cam is unused
+    {
+        availableGpio_B |= HAL_GPIO_BIT(12)
+                         | HAL_GPIO_BIT(14)
+                         | HAL_GPIO_BIT(15)
+                         | HAL_GPIO_BIT(16)
+                         | HAL_GPIO_BIT(17)
+                         | HAL_GPIO_BIT(18)
+                         | HAL_GPIO_BIT(19);
+        if (!(nand8_15Cam ||
+              (lcdMode == HAL_LCD_MODE_RGB_24BIT && halCfg->goudaCfg.lcd16_23Cam) ||
+              (halCfg->i2cCfg.i2c2Used && halCfg->i2cCfg.i2c2PinsCam)
+             )
+           )
+        {
+            availableGpio_B |= HAL_GPIO_BIT(10)
+                             | HAL_GPIO_BIT(11);
+        }
+        if (!(spiFlashCam || nand8_15Cam ||
+              (lcdMode == HAL_LCD_MODE_RGB_24BIT && halCfg->goudaCfg.lcd16_23Cam)
+             )
+           )
+        {
+            availableGpio_B |= HAL_GPIO_BIT(13)
+                             | HAL_GPIO_BIT(20)
+                             | HAL_GPIO_BIT(21)
+                             | HAL_GPIO_BIT(22)
+                             | HAL_GPIO_BIT(23)
+                             | HAL_GPIO_BIT(24);
+        }
+    }
+
+    // Camera2
+    if (cam2Cfg->camUsed || cam2Cfg->cam1Used)
+    {
+        if(cam2Cfg->camMode == HAL_CAM_MODE_PARALLEL)
+        {
+            altMux2 |= CFG_REGS_CSI2_2_PARALLEL_CAM;
+        }
+        else if (cam2Cfg->camMode == HAL_CAM_MODE_SPI)
+        {
+            altMux2 |= CFG_REGS_CSI2_2_SPI_CAM;
+            availableGpio_E |= HAL_GPIO_BIT(4)
+                             | HAL_GPIO_BIT(5)
+                             | HAL_GPIO_BIT(6)
+                             | HAL_GPIO_BIT(12)
+                             | HAL_GPIO_BIT(13)
+                             | HAL_GPIO_BIT(14)
+                             | HAL_GPIO_BIT(15);
+        }
+        else if (cam2Cfg->camMode == HAL_CAM_MODE_CSI)
+        {
+            if ((cam2Cfg->camUsed && (cam2Cfg->camCsiId == HAL_CAM_CSI_1 ||
+                                      cam2Cfg->camCsiId == HAL_CAM_CSI_2)) ||
+                (cam2Cfg->cam1Used && (cam2Cfg->cam1CsiId == HAL_CAM_CSI_1 ||
+                                       cam2Cfg->cam1CsiId == HAL_CAM_CSI_2)))
+            {
+                altMux2 |= CFG_REGS_CSI2_2_CSI2;
+            }
+            else
+            {
+                availableGpio_E |= HAL_GPIO_BIT(4)
+                                 | HAL_GPIO_BIT(5)
+                                 | HAL_GPIO_BIT(6)
+                                 | HAL_GPIO_BIT(7)
+                                 | HAL_GPIO_BIT(8)
+                                 | HAL_GPIO_BIT(9)
+                                 | HAL_GPIO_BIT(10)
+                                 | HAL_GPIO_BIT(11)
+                                 | HAL_GPIO_BIT(12)
+                                 | HAL_GPIO_BIT(13)
+                                 | HAL_GPIO_BIT(14)
+                                 | HAL_GPIO_BIT(15);
+            }
+        }
+        else
+        {
+            HAL_ASSERT(FALSE, "Invalid cam2 mode: %d", cam2Cfg->camMode);
+        }
+
+        // Cam2 PDN/RST pins
+        if (!((cam2Cfg->camUsed && cam2Cfg->camRstRemap == GPIO_NONE) ||
+              (cam2Cfg->cam1Used && cam2Cfg->cam1RstRemap == GPIO_NONE)))
+        {
+            availableGpio_E |= HAL_GPIO_BIT(2);
+        }
+        if (!((cam2Cfg->camUsed && cam2Cfg->camPdnRemap == GPIO_NONE) ||
+              (cam2Cfg->cam1Used && cam2Cfg->cam1PdnRemap == GPIO_NONE) ||
+              (altMux2 & CFG_REGS_CSI2_2_CSI2)))
+        {
+            availableGpio_E |= HAL_GPIO_BIT(3);
+        }
+    }
+    else // cam2 is unused
+    {
+        if (!((lcdMode == HAL_LCD_MODE_RGB_16BIT ||
+               lcdMode == HAL_LCD_MODE_RGB_18BIT ||
+               lcdMode == HAL_LCD_MODE_RGB_24BIT) &&
+              halCfg->goudaCfg.lcd8_23Cam2))
+        {
+                availableGpio_E |= HAL_GPIO_BIT(2)
+                                 | HAL_GPIO_BIT(3)
+                                 | HAL_GPIO_BIT(4)
+                                 | HAL_GPIO_BIT(5)
+                                 | HAL_GPIO_BIT(6)
+                                 | HAL_GPIO_BIT(7)
+                                 | HAL_GPIO_BIT(8)
+                                 | HAL_GPIO_BIT(9)
+                                 | HAL_GPIO_BIT(10)
+                                 | HAL_GPIO_BIT(11)
+                                 | HAL_GPIO_BIT(12)
+                                 | HAL_GPIO_BIT(13)
+                                 | HAL_GPIO_BIT(14)
+                                 | HAL_GPIO_BIT(15);
+        }
+    }
+
+    // UART 1 Pin configuration
+    switch (halCfg->uartCfg[0])
+    {
+        case HAL_UART_CONFIG_NONE:
+            altMux |= CFG_REGS_KEYOUT_7_KEYOUT_7;
+            availableGpio_C |= HAL_GPIO_BIT(6);
+            availableGpio_A |= HAL_GPIO_BIT(14);
+            if ((halCfg->keyInMask & 0x80) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(15);
+            }
+            if ((halCfg->keyInMask & 0x80) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(16);
+            }
+            break;
+        case HAL_UART_CONFIG_DATA:
+             // use UART1 TXD, RXD
+            altMux |= CFG_REGS_KEYOUT_7_KEYOUT_7;
+            if ((halCfg->keyInMask & 0x80) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(15);
+            }
+            if ((halCfg->keyInMask & 0x80) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(16);
+            }
+            break;
+        case HAL_UART_CONFIG_FLOWCONTROL:
+             // use UART1 TXD, RXD, CTS, RTS
+            HAL_ASSERT((halCfg->keyInMask & 0x80) == 0, "Keyin 7 uses UART1 CTS");
+            HAL_ASSERT((halCfg->keyOutMask & 0x80) == 0, "Keyout 7 uses UART1 RTS");
+            altMux |= CFG_REGS_KEYOUT_7_UART1_RTS;
+            break;
+        case HAL_UART_CONFIG_MODEM:
+            // use UART1 TXD, RXD, CTS, RTS, RI, DSR, DCD, DTR
+            HAL_ASSERT((halCfg->keyInMask & 0x80) == 0, "Keyin 7 uses UART1 CTS");
+            HAL_ASSERT((halCfg->keyOutMask & 0x80) == 0, "Keyout 7 uses UART1 RTS");
+            HAL_ASSERT(!halCfg->hostUartUsed, "Host UART uses UART1 DCD/DTR");
+            HAL_ASSERT(halCfg->uartCfg[1] == HAL_UART_CONFIG_NONE,
+                    "UART 2 must be unused to use UART1 Modem lines.");
+            HAL_ASSERT((halCfg->keyInMask & 0x40) == 0, "Keyin 6 uses UART1 DSR");
+            HAL_ASSERT((halCfg->keyOutMask & 0x40) == 0, "Keyout 6 uses UART1 RI");
+            altMux |= CFG_REGS_KEYOUT_7_UART1_RTS
+                    | CFG_REGS_UART1_8LINE_UART1_8_LINE;
+            break;
+        default:
+            HAL_ASSERT(FALSE,
+                    "Invalid Uart 1 Configuration (%d).",
+                    halCfg->uartCfg[0]);
+            break;
+    }
+
+    // Host UART
+    if (halCfg->hostUartUsed)
+    {
+        HAL_ASSERT(halCfg->uartCfg[1] == HAL_UART_CONFIG_NONE,
+                "UART2 uses host UART RXD/TXD.");
+    }
+
+    // UART 2 Pin configuration
+    switch (halCfg->uartCfg[1])
+    {
+        case HAL_UART_CONFIG_NONE:
+            altMux |= CFG_REGS_UART2_HOST_UART
+                    | CFG_REGS_KEYOUT_6_KEYOUT_6;
+            if (halCfg->uartCfg[0] != HAL_UART_CONFIG_MODEM)
+            {
+                availableGpio_C |= HAL_GPIO_BIT(7)
+                                 | HAL_GPIO_BIT(8);
+            }
+            if ((halCfg->keyInMask & 0x40) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(8);
+            }
+            if ((halCfg->keyOutMask & 0x40) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(9);
+            }
+            break;
+        case HAL_UART_CONFIG_DATA:
+            // use UART2 TXD, RXD
+            altMux |= CFG_REGS_UART2_UART2
+                    | CFG_REGS_KEYOUT_6_KEYOUT_6;
+            if ((halCfg->keyInMask & 0x40) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(8);
+            }
+            if ((halCfg->keyOutMask & 0x40) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(9);
+            }
+            break;
+        case HAL_UART_CONFIG_FLOWCONTROL:
+             // use UART2 TXD, RXD, CTS, RTS
+            HAL_ASSERT((halCfg->keyInMask & 0x40) == 0, "Keyin 6 uses UART2 CTS");
+            HAL_ASSERT((halCfg->keyOutMask & 0x40) == 0, "Keyout 6 uses UART2 RTS");
+            altMux |= CFG_REGS_UART2_UART2
+                    | CFG_REGS_KEYOUT_6_UART2_RTS;
+            break;
+        case HAL_UART_CONFIG_MODEM:
+        default:
+            HAL_ASSERT(FALSE,
+                    "Invalid Uart2 Configuration (%d).",
+                    halCfg->uartCfg[1]);
+            break;
+    }
+
+    // UART 3 Pin configuration
+    switch (halCfg->uartCfg[2])
+    {
+        case HAL_UART_CONFIG_NONE:
+            availableGpio_D |= HAL_GPIO_BIT(0)
+                             | HAL_GPIO_BIT(1)
+                             | HAL_GPIO_BIT(2)
+                             | HAL_GPIO_BIT(3);
+            break;
+        case HAL_UART_CONFIG_DATA:
+            // use UART3 TXD, RXD
+            availableGpio_D |= HAL_GPIO_BIT(2)
+                             | HAL_GPIO_BIT(3);
+            break;
+        case HAL_UART_CONFIG_FLOWCONTROL:
+             // use UART3 TXD, RXD, CTS, RTS
+            break;
+        case HAL_UART_CONFIG_MODEM:
+        default:
+            HAL_ASSERT(FALSE,
+                    "Invalid Uart3 Configuration (%d).",
+                    halCfg->uartCfg[2]);
+            break;
+    }
+
+    // I2S
+    altMux |= CFG_REGS_DAI_I2S;
+    if (halCfg->i2sCfg.di0Used || halCfg->i2sCfg.di1Used ||
+        halCfg->i2sCfg.di2Used || halCfg->i2sCfg.doUsed)
+    {
+        if (!halCfg->i2sCfg.di0Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(11);
+        }
+        if (!halCfg->i2sCfg.di1Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(12);
+        }
+        if (halCfg->i2sCfg.di2Used)
+        {
+            HAL_ASSERT((halCfg->keyInMask & 0x4) == 0, "Keyin 2 uses I2S DI2");
+            altMux |= CFG_REGS_I2S_DI_2_I2S_DI_2;
+        }
+        else
+        {
+            altMux |= CFG_REGS_I2S_DI_2_KEYIN_2;
+            if ((halCfg->keyInMask & 0x4) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(2);
+            }
+        }
+        if (!halCfg->i2sCfg.doUsed)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(13);
+        }
+    }
+    else
+    {
+        availableGpio_A |= HAL_GPIO_BIT(9)
+                         | HAL_GPIO_BIT(10)
+                         | HAL_GPIO_BIT(11)
+                         | HAL_GPIO_BIT(12)
+                         | HAL_GPIO_BIT(13);
+    }
+
+    // I2S2
+    if (halCfg->i2s2Cfg.di0Used || halCfg->i2s2Cfg.di1Used ||
+        halCfg->i2s2Cfg.di2Used || halCfg->i2s2Cfg.doUsed)
+    {
+        HAL_ASSERT(!halCfg->emacUsed, "EMAC uses I2S2 pins");
+        if (!halCfg->i2s2Cfg.di0Used)
+        {
+            availableGpio_D |= HAL_GPIO_BIT(13);
+        }
+        if (!halCfg->i2s2Cfg.di1Used)
+        {
+            availableGpio_D |= HAL_GPIO_BIT(14);
+        }
+        if (!halCfg->i2s2Cfg.doUsed)
+        {
+            availableGpio_D |= HAL_GPIO_BIT(15);
+        }
+    }
+    else
+    {
+        availableGpio_D |= HAL_GPIO_BIT(11)
+                         | HAL_GPIO_BIT(12)
+                         | HAL_GPIO_BIT(13)
+                         | HAL_GPIO_BIT(14)
+                         | HAL_GPIO_BIT(15);
+    }
+
+    // LPS CO1
+    if (halCfg->useLpsCo1)
+    {
+        HAL_ASSERT((halCfg->keyInMask & 0x10) == 0, "Keyin 4 uses LPS_CO1");
+        altMux |= CFG_REGS_LPSCO_1_LPSCO_1;
+    }
+    else
+    {
+        altMux |= CFG_REGS_LPSCO_1_KEYIN_4;
+        if ((halCfg->keyInMask & 0x10) == 0)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(7);
+        }
+    }
+
+    // TCO
+    if (halCfg->usedTco & 0x1)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x1) == 0, "Keyout 0 uses TCO0");
+        altMux |= CFG_REGS_TCO_0_TCO_0;
+    }
+    else
+    {
+        altMux |= CFG_REGS_TCO_0_KEYOUT_0;
+        if ((halCfg->keyOutMask & 0x1) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(3);
+        }
+    }
+
+    if (halCfg->usedTco & 0x2)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x2) == 0, "Keyout 1 uses TCO1");
+        altMux |= CFG_REGS_TCO_1_TCO_1;
+    }
+    else
+    {
+        altMux |= CFG_REGS_TCO_1_KEYOUT_1;
+        if ((halCfg->keyOutMask & 0x2) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(4);
+        }
+    }
+
+    if (halCfg->usedTco & 0x4)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x4) == 0, "Keyout 2 uses TCO2");
+        altMux |= CFG_REGS_TCO_2_TCO_2;
+    }
+    else
+    {
+        altMux |= CFG_REGS_TCO_2_KEYOUT_2;
+        if ((halCfg->keyOutMask & 0x4) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(5);
+        }
+    }
+
+    // PWM
+    if (halCfg->pwmCfg.pwtUsed)
+    {
+        HAL_ASSERT((halCfg->keyInMask & 0x20) == 0, "Keyin 5 uses PWT");
+        altMux |= CFG_REGS_GPO_0_PWT;
+    }
+    else if (halCfg->keyInMask & 0x20)
+    {
+        altMux |= CFG_REGS_GPO_0_KEYIN_5;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_0_GPO_0;
+        availableGpo_A |= HAL_GPO_BIT(0);
+    }
+
+    if (halCfg->pwmCfg.lpgUsed)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x20) == 0, "Keyout 5 uses LPG");
+        altMux |= CFG_REGS_GPO_1_LPG;
+    }
+    else if (halCfg->keyOutMask & 0x20)
+    {
+        altMux |= CFG_REGS_GPO_1_KEYOUT_5;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_1_GPO_1;
+        availableGpo_A |= HAL_GPO_BIT(1);
+    }
+
+    if (halCfg->pwmCfg.pwl1Used)
+    {
+        HAL_ASSERT(!halCfg->useClk32k, "Clk 32k uses PWL1");
+        altMux |= CFG_REGS_GPO_2_PWL_1;
+    }
+    else if (halCfg->useClk32k)
+    {
+        // Default to GPO low output
+        // 32K clock will be enabled per request
+        //altMux |= CFG_REGS_GPO_2_CLK_32K;
+        altMux |= CFG_REGS_GPO_2_GPO_2;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_2_GPO_2;
+        availableGpo_A |= HAL_GPO_BIT(2);
+    }
+
+    // Clock out and host clock
+    if (halCfg->clkOutUsed)
+    {
+        HAL_ASSERT(!halCfg->hostClkUsed, "HST_CLK uses CLK_OUT pin");
+        altMux |= CFG_REGS_CLK_OUT_CLK_OUT;
+    }
+    else if (halCfg->hostClkUsed)
+    {
+        altMux |= CFG_REGS_CLK_OUT_HST_CLK;
+    }
+    else
+    {
+        altMux |= CFG_REGS_CLK_OUT_HST_CLK;
+        availableGpo_A |= HAL_GPO_BIT(8);
+    }
+
+    // SPI
+    if (halCfg->spiCfg[0].cs0Used || halCfg->spiCfg[0].cs1Used ||
+        halCfg->spiCfg[0].cs2Used)
+    {
+        HAL_ASSERT(!(halCfg->modemSpiCfg[0].cs0Used ||
+                     halCfg->modemSpiCfg[0].cs1Used ||
+                     halCfg->modemSpiCfg[0].cs2Used), "Modem SPI1 is in use");
+        altMux |= CFG_REGS_AP_SPI1_AP_SPI1;
+        if (!halCfg->spiCfg[0].cs0Used)
+        {
+            availableGpio_C |= HAL_GPIO_BIT(22);
+        }
+        if (!halCfg->spiCfg[0].cs1Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(17);
+        }
+        if (halCfg->spiCfg[0].cs2Used)
+        {
+            HAL_ASSERT((halCfg->keyInMask & 0x2) == 0, "Keyin 1 uses SPI1 CS2");
+            altMux |= CFG_REGS_SPI1_CS_2_SPI1_CS_2;
+        }
+        else
+        {
+            altMux |= CFG_REGS_SPI1_CS_2_KEYIN_1;
+            if ((halCfg->keyInMask & 0x2) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(1);
+            }
+        }
+        if (!halCfg->spiCfg[0].di0Used)
+        {
+            availableGpio_C |= HAL_GPIO_BIT(23);
+        }
+        if (!halCfg->spiCfg[0].di1Used)
+        {
+            availableGpio_C |= HAL_GPIO_BIT(24);
+        }
+    }
+    else // AP SPI1 unused
+    {
+        altMux |= CFG_REGS_AP_SPI1_BB_SPI1;
+        if (halCfg->modemSpiCfg[0].cs0Used || halCfg->modemSpiCfg[0].cs1Used ||
+            halCfg->modemSpiCfg[0].cs2Used)
+        {
+            if (!halCfg->modemSpiCfg[0].cs0Used)
+            {
+                availableGpio_C |= HAL_GPIO_BIT(22);
+            }
+            if (!halCfg->modemSpiCfg[0].cs1Used)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(17);
+            }
+            if (!halCfg->modemSpiCfg[0].di0Used)
+            {
+                availableGpio_C |= HAL_GPIO_BIT(23);
+            }
+            if (!halCfg->modemSpiCfg[0].di1Used)
+            {
+                availableGpio_C |= HAL_GPIO_BIT(24);
+            }
+        }
+        else
+        {
+            availableGpio_A |= HAL_GPIO_BIT(17);
+            availableGpio_C |= HAL_GPIO_BIT(21)
+                             | HAL_GPIO_BIT(22)
+                             | HAL_GPIO_BIT(23)
+                             | HAL_GPIO_BIT(24);
+            if ((halCfg->keyInMask & 0x2) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(1);
+            }
+        }
+    }
+    if (halCfg->spiCfg[1].cs0Used || halCfg->spiCfg[1].cs1Used)
+    {
+        if (!halCfg->spiCfg[1].cs0Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(5);
+        }
+        if (halCfg->spiCfg[1].cs1Used)
+        {
+            HAL_ASSERT((halCfg->keyInMask & 0x8) == 0, "Keyin 3 uses SPI2 CS1");
+            altMux |= CFG_REGS_KEYIN_3_SPI2_CS_1;
+        }
+        else
+        {
+            altMux |= CFG_REGS_KEYIN_3_KEYIN_3;
+            if ((halCfg->keyInMask & 0x8) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(6);
+            }
+        }
+        if (!halCfg->spiCfg[1].di0Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(3);
+        }
+        if (!halCfg->spiCfg[1].di1Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(4);
+        }
+    }
+    else // AP SPI2 unused
+    {
+        availableGpio_A |= HAL_GPIO_BIT(2)
+                         | HAL_GPIO_BIT(3)
+                         | HAL_GPIO_BIT(4)
+                         | HAL_GPIO_BIT(5);
+        if ((halCfg->keyInMask & 0x8) == 0)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(6);
+        }
+    }
+
+    // Standalone keyin/out
+    if ((halCfg->keyInMask & 0x1) == 0)
+    {
+        availableGpio_B |= HAL_GPIO_BIT(0);
+    }
+
+    // SDMMC
+    if (!halCfg->sdmmcCfg.sdmmcUsed)
+    {
+        availableGpio_C |= HAL_GPIO_BIT(9)
+                         | HAL_GPIO_BIT(10)
+                         | HAL_GPIO_BIT(11)
+                         | HAL_GPIO_BIT(12)
+                         | HAL_GPIO_BIT(13)
+                         | HAL_GPIO_BIT(14);
+    }
+    if (!halCfg->sdmmcCfg.sdmmc2Used)
+    {
+        availableGpio_C |= HAL_GPIO_BIT(15)
+                         | HAL_GPIO_BIT(16);
+        if (!halCfg->sdio2Uart1Used)
+        {
+            availableGpio_C |= HAL_GPIO_BIT(17)
+                             | HAL_GPIO_BIT(18)
+                             | HAL_GPIO_BIT(19)
+                             | HAL_GPIO_BIT(20);
+        }
+    }
+    HAL_ASSERT(!(parallelNandUsed && halCfg->sdmmcCfg.sdmmc3Used),
+        "Parallel NAND uses SDMMC3 pins");
+
+    // SDIO2_UART1
+    if (halCfg->sdio2Uart1Used)
+    {
+        HAL_ASSERT(halCfg->uartCfg[0] == HAL_UART_CONFIG_NONE,
+            "UART1 has been configured on UART1 pins");
+        altMux2 |= CFG_REGS_UART1_SDIO2_UART1;
+    }
+    else
+    {
+        altMux2 |= CFG_REGS_UART1_SDIO2_SDIO2;
+    }
+
+    // EMAC
+    if (halCfg->emacUsed)
+    {
+        altMux2 |= CFG_REGS_MAC_EN_ENABLE;
+    }
+    else
+    {
+        altMux2 |= CFG_REGS_MAC_EN_DISABLE;
+    }
+
+    // SIM
+    if (!hal_BoardSimUsed(2))
+    {
+        availableGpio_C |= HAL_GPIO_BIT(25)
+                         | HAL_GPIO_BIT(26)
+                         | HAL_GPIO_BIT(27);
+    }
+
+    if (hal_BoardSimUsed(3))
+    {
+        HAL_ASSERT(!halCfg->emacUsed, "EMAC uses SIM3 pins");
+    }
+    else
+    {
+        if (!halCfg->emacUsed)
+        {
+            availableGpio_C |= HAL_GPIO_BIT(28)
+                             | HAL_GPIO_BIT(29)
+                             | HAL_GPIO_BIT(30);
+        }
+    }
+
+    UINT32 gpioMask;
+    // GPIO_C mask check
+    gpioMask = ~availableGpio_C & halCfg->usedGpio_C;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO C are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_C & halCfg->noConnectGpio_C;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO C declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_C & halCfg->noConnectGpio_C;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO C declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_C &
+               (~halCfg->usedGpio_C & ~halCfg->noConnectGpio_C);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO C declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPIO_A mask check
+    gpioMask = ~availableGpio_A & halCfg->usedGpio_A;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO A are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_A & halCfg->noConnectGpio_A;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO A declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_A & halCfg->noConnectGpio_A;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO A declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_A &
+               (~halCfg->usedGpio_A & ~halCfg->noConnectGpio_A);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO A declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPIO_B mask check
+    gpioMask = ~availableGpio_B & halCfg->usedGpio_B;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO B are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_B & halCfg->noConnectGpio_B;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO B declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_B & halCfg->noConnectGpio_B;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO B declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_B &
+               (~halCfg->usedGpio_B & ~halCfg->noConnectGpio_B);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO B declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPIO_D mask check
+    gpioMask = ~availableGpio_D & halCfg->usedGpio_D;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO D are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_D & halCfg->noConnectGpio_D;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO D declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_D & halCfg->noConnectGpio_D;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO D declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_D &
+               (~halCfg->usedGpio_D & ~halCfg->noConnectGpio_D);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO D declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPIO_E mask check
+    gpioMask = ~availableGpio_E & halCfg->usedGpio_E;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO E are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_E & halCfg->noConnectGpio_E;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO E declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_E & halCfg->noConnectGpio_E;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO E declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_E &
+               (~halCfg->usedGpio_E & ~halCfg->noConnectGpio_E);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO E declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPO_A mask check
+    gpioMask = ~availableGpo_A & halCfg->usedGpo_A;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPO A are not available (0x%x)",
+               gpioMask);
+
+#endif // !FPGA
+
+    // Set IO drive
+    hwp_configRegs->IO_Drive1_Select = halCfg->ioDrive.select1;
+    hwp_configRegs->IO_Drive2_Select = halCfg->ioDrive.select2;
+
+    // Set the not connected ones as output and drive 0
+    // But keep boot mode GPIOs as input to avoid current leakage
+    noConnectMask_C = halCfg->noConnectGpio_C & ~bootModeGpio_C;
+    noConnectMask_A = halCfg->noConnectGpio_A & ~bootModeGpio_A;
+    noConnectMask_B = halCfg->noConnectGpio_B & ~bootModeGpio_B;
+    noConnectMask_D = halCfg->noConnectGpio_D & ~bootModeGpio_D;
+    noConnectMask_E = halCfg->noConnectGpio_E & ~bootModeGpio_E;
+
+    hwp_gpio->gpio_clr = noConnectMask_C;
+    hwp_gpio->gpio_oen_set_out = noConnectMask_C;
+
+    hwp_apGpioA->gpio_clr = noConnectMask_A;
+    hwp_apGpioA->gpio_oen_set_out = noConnectMask_A;
+
+    hwp_apGpioB->gpio_clr = noConnectMask_B;
+    hwp_apGpioB->gpio_oen_set_out = noConnectMask_B;
+
+    hwp_apGpioD->gpio_clr = noConnectMask_D;
+    hwp_apGpioD->gpio_oen_set_out = noConnectMask_D;
+
+    hwp_apGpioE->gpio_clr = noConnectMask_E;
+    hwp_apGpioE->gpio_oen_set_out = noConnectMask_E;
+
+    // Init GPO_A values
+    gpoClr_A = availableGpo_A;
+    if (halCfg->useClk32k)
+    {
+        // Init 32K clock pin to low (by setting up GPO)
+        gpoClr_A |= HAL_GPO_BIT(2);
+    }
+#ifdef _TGT_AP_GPIO_USBID_CTRL
+    // if GPO_1 used for usb id, it should be high
+    gpoClr_A &= ~(HAL_GPO_BIT(1));
+#endif
+    hwp_apGpioA->gpo_clr = gpoClr_A;
+
+    // Configure MUX after initializing all the GPO pins
+    // (GPIO pins are in input mode by default)
+
+    // Set GPIO mode
+    hwp_configRegs->BB_GPIO_Mode = availableGpio_C;
+    hwp_configRegs->AP_GPIO_A_Mode = availableGpio_A;
+    hwp_configRegs->AP_GPIO_B_Mode = availableGpio_B;
+    hwp_configRegs->AP_GPIO_D_Mode = availableGpio_D;
+    hwp_configRegs->AP_GPIO_E_Mode = availableGpio_E;
+    // Set Alt Mux configuration
+    hwp_configRegs->Alt_mux_select = altMux;
+    hwp_configRegs->Alt_mux_select2 = altMux2;
+
+    // --------------------------------------------------
+    // As of now, all connected GPIOs, which are as GPIO
+    // or not used at all but connected are configured as
+    // GPIOs in input mode, except for Gouda reset pins
+    // --------------------------------------------------
+
+}
+
+
+// =============================================================================
+// hal_BoardSetup
+// -----------------------------------------------------------------------------
+/// Apply board dependent configuration to HAL
+/// @param halCfg Pointer to HAL configuration structure (from the target
+/// module).
+// ============================================================================
+//PROTECTED VOID hal_BoardSetup(CONST HAL_CFG_CONFIG_T* halCfg)
+PUBLIC INT32 hal_BoardSetup(INT8 run_mode)
+{
+    g_bootBootMode = rda_hwcfg_get();
+    hal_BoardSetupGeneral(&hal_cfg);
+
+    if(g_halConfigError)
+        return CMD_RET_FAILURE;
+    else
+        return CMD_RET_SUCCESS;
+}
diff --git a/board/rda/rda8810h/u-boot-spl.lds b/board/rda/rda8810h/u-boot-spl.lds
new file mode 100644
index 0000000000..afe35fd2a8
--- /dev/null
+++ b/board/rda/rda8810h/u-boot-spl.lds
@@ -0,0 +1,35 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00100100;
+	. = ALIGN(4);
+	.text :
+	{
+		__start = .;
+		arch/arm/cpu/armv7/start.o (.text)
+			*(.text)
+	}
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+	. = ALIGN(4);
+	.data : {
+		*(.data)
+	}
+	. = ALIGN(4);
+	. = .;
+	. = ALIGN(4);
+	__image_copy_end = .;
+	_end = .;
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+		ASSERT((ABSOLUTE(__bss_end__) < 0x00110000), \
+			"too big data in spl, don't exceed intrenal ram");
+	}
+}
diff --git a/board/rda/rda8820/Makefile b/board/rda/rda8820/Makefile
new file mode 100644
index 0000000000..ba9ad575bb
--- /dev/null
+++ b/board/rda/rda8820/Makefile
@@ -0,0 +1,82 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS-y	+= clock_config.o clock.o ddr3_zhangli_32bit_dlloff.o
+else
+COBJS-$(CONFIG_MACH_RDA8820) += hal_config.o
+endif
+
+RDA_TARGET_DEF_FILE := $(ANDROID_BUILD_TOP)/$(RDA_TARGET_DEVICE_DIR)/target.def
+RDA_GET_MAKEFILE_VAR_FUNC = $(strip $(shell sed -n 's/^[ 	]*$(1)[ 	]*[?:]\?=\([^\#]\+\)\#*.*$$/\1/p' $(2)))
+
+NUMBER_OF_SIM := $(call RDA_GET_MAKEFILE_VAR_FUNC,NUMBER_OF_SIM,$(RDA_TARGET_DEF_FILE))
+ifeq ($(NUMBER_OF_SIM),)
+$(error Failed to get NUMBER_OF_SIM in $(RDA_TARGET_DEF_FILE))
+endif
+
+USER_SIM_ORDER := $(call RDA_GET_MAKEFILE_VAR_FUNC,USER_SIM_ORDER,$(RDA_TARGET_DEF_FILE))
+ifeq ($(USER_SIM_ORDER),)
+$(error Failed to get USER_SIM_ORDER in $(RDA_TARGET_DEF_FILE))
+endif
+
+NULL_STRING :=
+SPACE := ${NULL_STRING} # end of the line
+COMMA := ,
+TGT_SIM_ORDER := $(foreach SIM,$(USER_SIM_ORDER),$(SIM)$(COMMA))
+TGT_SIM_ORDER := $(subst ${SPACE},,${TGT_SIM_ORDER})
+
+CPPFLAGS_board/$(BOARDDIR)/hal_config.o += -I$(TOPDIR)/board/$(VENDOR)/common/include -DTGT_SIM_ORDER=$(TGT_SIM_ORDER) -DNUMBER_OF_SIM=$(NUMBER_OF_SIM)
+
+ifeq ($(strip $(TARGET_TABLET_MODE)),true)
+CPPFLAGS_board/$(BOARDDIR)/clock.o += -DTARGET_TABLET_MODE
+endif
+
+COBJS   := $(COBJS-y)
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak *~ .depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/rda/rda8820/clock.c b/board/rda/rda8820/clock.c
new file mode 100644
index 0000000000..264f3f777f
--- /dev/null
+++ b/board/rda/rda8820/clock.c
@@ -0,0 +1,1312 @@
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/rda_iomap.h>
+#include <asm/io.h>
+#include <asm/arch/reg_sysctrl.h>
+#include <asm/arch/hwcfg.h>
+#include <asm/arch/ispi.h>
+#include <asm/arch/rda_sys.h>
+#include "clock_config.h"
+#include "debug.h"
+#include "ddr3.h"
+#include "tgt_ap_clock_config.h"
+
+#if (PMU_VBUCK1_VAL < 0 || PMU_VBUCK1_VAL > 15)
+#error "Invalid PMU_VBUCK1_VAL"
+#endif
+#if (PMU_VBUCK3_VAL < 0 || PMU_VBUCK3_VAL > 15)
+#error "Invalid PMU_VBUCK3_VAL"
+#endif
+#ifdef PMU_VBUCK4_VAL
+#if (PMU_VBUCK4_VAL < 0 || PMU_VBUCK4_VAL > 15)
+#error "Invalid PMU_VBUCK4_VAL"
+#endif
+#endif
+
+//#define DO_SIMPLE_DDR_TEST
+//#define DO_DDR_PLL_DEBUG
+
+enum {
+	AP_CPU_CLK_IDX = 0,
+	AP_BUS_CLK_IDX,
+	AP_MEM_CLK_IDX,
+	AP_USB_CLK_IDX,
+};
+
+static int pll_enabled(int idx)
+{
+	if ((hwp_sysCtrlAp->Cfg_Pll_Ctrl[idx] &
+			(SYS_CTRL_AP_AP_PLL_ENABLE_MASK |
+			 SYS_CTRL_AP_AP_PLL_LOCK_RESET_MASK)) ==
+			(SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE |
+			 SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET))
+		return 1;
+	else
+		return 0;
+}
+
+static int usb_in_use = 0;
+
+static void check_usb_usage(void)
+{
+	unsigned int mask = SYS_CTRL_AP_BUS_SEL_FAST_SLOW |
+		SYS_CTRL_AP_PLL_LOCKED_BUS_MASK |
+		SYS_CTRL_AP_PLL_LOCKED_USB_MASK;
+	unsigned int reg = SYS_CTRL_AP_BUS_SEL_FAST_FAST |
+		SYS_CTRL_AP_PLL_LOCKED_BUS_LOCKED |
+		SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED;
+
+	if ((hwp_sysCtrlAp->Sel_Clock & mask) == reg &&
+			pll_enabled(AP_BUS_CLK_IDX) &&
+			pll_enabled(AP_USB_CLK_IDX))
+		usb_in_use = 1;
+	else
+		usb_in_use = 0;
+}
+
+#ifdef DO_SIMPLE_DDR_TEST
+
+void mem_test_write(void)
+{
+	volatile unsigned int *addr;
+
+	printf("write ddr test!!!!!!\n");
+
+ 	addr = (volatile unsigned int *)(0x80000000);
+	while((unsigned int)addr < 0x81000000)
+	{
+		*addr = (unsigned int )addr;
+		addr++;
+	}
+}
+
+void mem_test_read(void)
+{
+	volatile unsigned int *addr;
+
+	printf("read ddr!!!!\n");
+
+	addr = (volatile unsigned int *)(0x80000000);
+
+	while((unsigned int)addr < 0x81000000)
+	{
+		if (*addr != (unsigned int)addr){
+			int i = 0;
+			
+			printf("test error!!!!!, addr = %x\n", (unsigned int)addr);
+			for (i = 0; i < 80;i++){
+				printf("%x ", *(addr + i));
+				if ((i % 4) == 0)
+					printf("\n");
+			}
+
+			return;
+		}
+
+		addr++;
+	}
+	printf("test complete!\n");
+}
+
+#endif /* DO_SIMPLE_DDR_TEST */
+
+#ifndef CONFIG_RDA_FPGA
+
+// PMU bit fields
+#define PMU_SET_BITFIELD(dword, bitfield, value) \
+	(((dword) & ~(bitfield ## _MASK)) | (bitfield(value)))
+
+#define RDA_PMU_VBUCK1_BIT_ACT(n)        (((n)&0xf)<<12)
+#define RDA_PMU_VBUCK1_BIT_ACT_MASK      (0xf<<12)
+#define RDA_PMU_VBUCK1_BIT_ACT_SHIFT     (12)
+
+#define RDA_PMU_VBUCK4_BIT_ACT_SHIFT     (4)
+#define RDA_PMU_VBUCK4_BIT_ACT_MASK      (0xf<<4)
+#define RDA_PMU_VBUCK4_BIT_ACT(n)        (((n)&0xf)<<4)
+
+#define RDA_PMU_VBUCK3_BIT_ACT_SHIFT     (12)
+#define RDA_PMU_VBUCK3_BIT_ACT_MASK      (0xf<<12)
+#define RDA_PMU_VBUCK3_BIT_ACT(n)        (((n)&0xf)<<12)
+
+struct pll_freq {
+	UINT32 freq_mhz;
+	UINT16 major;
+	UINT16 minor;
+	UINT16 with_div;
+	UINT16 div;
+};
+
+typedef enum {
+	PLL_REG_CPU_BASE = 0x00,
+	PLL_REG_BUS_BASE = 0x20,
+	PLL_REG_MEM_BASE = 0x60,
+	PLL_REG_USB_BASE = 0x80,
+} PLL_REG_BASE_INDEX_t;
+
+typedef enum {
+	PLL_REG_OFFSET_01H = 1,
+	PLL_REG_OFFSET_02H = 2,
+	PLL_REG_OFFSET_DIV = 3,
+	PLL_REG_OFFSET_04H = 4,
+	PLL_REG_OFFSET_MAJOR = 5,
+	PLL_REG_OFFSET_MINOR = 6,
+	PLL_REG_OFFSET_07H = 7,
+} PLL_REG_OFFSET_INDEX_t;
+
+#define PLL_FREQ_TABLE_COUNT        21
+
+static struct pll_freq pll_freq_table[PLL_FREQ_TABLE_COUNT] = {
+	/* MHz Major   Minor   div */
+	{1600, 0x7B13, 0xB138, 0, 0x0000},
+	{1200, 0x5C4E, 0xC4EC, 0, 0x0000},
+	{1000, 0x4CEC, 0x4EC4, 0, 0x0000},
+	{ 800, 0x3D89, 0xD89C, 0, 0x0000},
+	{ 600, 0x2E27, 0x6274, 0, 0x0000},
+	{ 519, 0x27EC, 0x4EC4, 1, 0x0007},
+	{ 500, 0x2676, 0x2762, 1, 0x0007},
+	{ 480, 0x24EC, 0x4EC4, 0, 0x0000},
+	{ 455, 0x2300, 0x0000, 1, 0xF397},
+	{ 416, 0x2000, 0x0000, 1, 0xFA97},
+	/* 800M div 1, PLL:800M  DDR:400M for mem pll only */
+	{ 400, 0x1EC4, 0xEC4C, 1, 0xF997},
+	{ 355, 0x369D, 0x89D8, 1, 0x9597},
+	/* 702M div 1, PLL:702M  DDR:351M for mem pll only */
+	{ 351, 0x3600, 0x0000, 1, 0x9597},
+	{ 333, 0x333B, 0x13B1, 1, 0x9D97},
+	/* 624M div 1, PLL:624M  DDR:312M for mem pll only */
+	{ 312, 0x3000, 0x0000, 1, 0x9D97},
+	{ 290, 0x2C9D, 0x89D8, 1, 0x9A97},
+	/* 520M div 1, PLL:520M  DDR:260M for mem pll only */
+	{ 260, 0x2800, 0x0000, 1, 0xA297},
+	/* 800M div 2, PLL:400M  DDR:200M for mem pll only */
+	{ 200, 0x3D89, 0xD89C, 1, 0xB996},
+	/* DDR:156M for mem pll only */
+	{ 156, 0x3000, 0x0000, 1, 0x0006},
+	/* 800M div 4, PLL:200M  DDR:100M for mem pll only */
+	{ 100, 0x3D89, 0xD89C, 1, 0x0005},
+	/* 800M div 8, PLL:100M  DDR:50M for mem pll only */
+	{  50, 0x3D89, 0xD89C, 1, 0x0004},
+};
+
+static const struct clock_config *g_clock_config;
+
+#ifdef DO_DDR_PLL_DEBUG
+static struct clock_config clock_debug_config;
+static UINT32 ddrfreq = 400, ddr32bit = 0;
+#endif
+
+static void sys_shutdown_pll(void)
+{
+	int i;
+
+	hwp_sysCtrlAp->REG_DBG = AP_CTRL_PROTECT_UNLOCK;
+
+	if (usb_in_use) {
+		hwp_sysCtrlAp->Sel_Clock = SYS_CTRL_AP_SLOW_SEL_RF_RF
+			| SYS_CTRL_AP_CPU_SEL_FAST_SLOW
+			| SYS_CTRL_AP_BUS_SEL_FAST_FAST
+			| SYS_CTRL_AP_TIMER_SEL_FAST_FAST;
+	} else {
+		hwp_sysCtrlAp->Sel_Clock = SYS_CTRL_AP_SLOW_SEL_RF_RF
+			| SYS_CTRL_AP_CPU_SEL_FAST_SLOW
+			| SYS_CTRL_AP_BUS_SEL_FAST_SLOW
+			| SYS_CTRL_AP_TIMER_SEL_FAST_FAST;
+	}
+
+	for (i = 0; i < 3; i++) {
+		/* In download mode, rom code has been set ap bus*/
+		if (usb_in_use) {
+			if (i == AP_BUS_CLK_IDX) // ap bus
+				continue;
+		}
+		hwp_sysCtrlAp->Cfg_Pll_Ctrl[i] =
+			SYS_CTRL_AP_AP_PLL_ENABLE_POWER_DOWN |
+			SYS_CTRL_AP_AP_PLL_LOCK_RESET_RESET;
+	}
+}
+
+static void sys_setup_pll(void)
+{
+	int i;
+	UINT32 mask;
+	UINT32 locked;
+	int cnt = 10; //10us, according to IC, the pll must be locked
+
+	hwp_sysCtrlAp->REG_DBG = AP_CTRL_PROTECT_UNLOCK;
+
+	for (i = 0; i < 3; i++) {
+		/* In download mode, rom code has been set ap bus*/
+		if (usb_in_use) {
+			if (i == AP_BUS_CLK_IDX) // ap bus
+				continue;
+		}
+
+		if (AP_MEM_CLK_IDX == i)
+			hwp_sysCtrlAp->Cfg_Pll_Ctrl[i] =
+				SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE |
+				SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET |
+				SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(1)|
+				SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(30);
+		else
+			hwp_sysCtrlAp->Cfg_Pll_Ctrl[i] =
+				SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE |
+				SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET |
+				SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(6)|
+				SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(30);
+	}
+
+	mask = SYS_CTRL_AP_PLL_LOCKED_CPU_MASK
+	    | SYS_CTRL_AP_PLL_LOCKED_BUS_MASK
+	    | SYS_CTRL_AP_PLL_LOCKED_MEM_MASK
+	    //| SYS_CTRL_AP_PLL_LOCKED_USB_MASK
+	    ;
+	locked = SYS_CTRL_AP_PLL_LOCKED_CPU_LOCKED
+	    | SYS_CTRL_AP_PLL_LOCKED_BUS_LOCKED
+	    | SYS_CTRL_AP_PLL_LOCKED_MEM_LOCKED
+	    //| SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED
+	    ;
+
+	while (((hwp_sysCtrlAp->Sel_Clock & mask) != locked) && cnt) {
+		udelay(1);
+		cnt--;
+	}
+	if (cnt == 0) {
+		printf("WARNING, cannot lock cpu/bus/mem pll 0x%08x ",
+			hwp_sysCtrlAp->Sel_Clock);
+		printf("but we run anyway ...\n");
+	}
+
+	for (i = 0; i < 3; i++) {
+		hwp_sysCtrlAp->Cfg_Pll_Ctrl[i] |=
+		    SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_ENABLE;
+	}
+
+	hwp_sysCtrlAp->Sel_Clock = SYS_CTRL_AP_SLOW_SEL_RF_RF
+	    | SYS_CTRL_AP_CPU_SEL_FAST_FAST
+	    | SYS_CTRL_AP_BUS_SEL_FAST_FAST
+	    | SYS_CTRL_AP_TIMER_SEL_FAST_FAST;
+}
+
+static void sys_setup_clk(void)
+{
+	// Disable some power-consuming clocks
+	hwp_sysCtrlAp->Clk_APO_Disable = SYS_CTRL_AP_DISABLE_APOC_VPU;
+	//hwp_sysCtrlAp->Clk_MEM_Disable = SYS_CTRL_AP_DISABLE_MEM_VPU;
+
+	// Init clock gating mode
+	hwp_sysCtrlAp->Clk_CPU_Mode = 0;
+	hwp_sysCtrlAp->Clk_AXI_Mode = SYS_CTRL_AP_MODE_AXI_DMA_MANUAL;
+	hwp_sysCtrlAp->Clk_AXIDIV2_Mode = 0;
+	hwp_sysCtrlAp->Clk_GCG_Mode = SYS_CTRL_AP_MODE_GCG_GOUDA_MANUAL
+				| SYS_CTRL_AP_MODE_GCG_CAMERA_MANUAL;
+	hwp_sysCtrlAp->Clk_AHB1_Mode = 0;
+	hwp_sysCtrlAp->Clk_APB1_Mode = 0;
+	hwp_sysCtrlAp->Clk_APB2_Mode = 0;
+	hwp_sysCtrlAp->Clk_MEM_Mode = 0;
+	//hwp_sysCtrlAp->Clk_APO_Mode = SYS_CTRL_AP_MODE_APOC_VPU_MANUAL;
+
+	// Init module frequency
+	hwp_sysCtrlAp->Cfg_Clk_AP_CPU = g_clock_config->CLK_CPU;
+	hwp_sysCtrlAp->Cfg_Clk_AP_AXI = g_clock_config->CLK_AXI;
+	hwp_sysCtrlAp->Cfg_Clk_AP_GCG = g_clock_config->CLK_GCG;
+
+	if (!usb_in_use) {
+		hwp_sysCtrlAp->Cfg_Clk_AP_AHB1 = g_clock_config->CLK_AHB1;
+	}
+
+	hwp_sysCtrlAp->Cfg_Clk_AP_APB1 = g_clock_config->CLK_APB1;
+	hwp_sysCtrlAp->Cfg_Clk_AP_APB2 = g_clock_config->CLK_APB2;
+	hwp_sysCtrlAp->Cfg_Clk_AP_MEM = g_clock_config->CLK_MEM;
+	hwp_sysCtrlAp->Cfg_Clk_AP_GPU = g_clock_config->CLK_GPU;
+	hwp_sysCtrlAp->Cfg_Clk_AP_VPU = g_clock_config->CLK_VPU;
+	hwp_sysCtrlAp->Cfg_Clk_AP_VOC = g_clock_config->CLK_VOC;
+	hwp_sysCtrlAp->Cfg_Clk_AP_SFLSH = g_clock_config->CLK_SFLSH;
+}
+
+static void print_sys_reg(char *name, UINT32 value)
+{
+	printf("clk %s = %lx\n", name, value);
+}
+
+static void sys_dump_clk(void)
+{
+	print_sys_reg("CPU", hwp_sysCtrlAp->Cfg_Clk_AP_CPU);
+	print_sys_reg("AXI", hwp_sysCtrlAp->Cfg_Clk_AP_AXI);
+	print_sys_reg("GCG", hwp_sysCtrlAp->Cfg_Clk_AP_GCG);
+	print_sys_reg("AHB1", hwp_sysCtrlAp->Cfg_Clk_AP_AHB1);
+	print_sys_reg("APB1", hwp_sysCtrlAp->Cfg_Clk_AP_APB1);
+	print_sys_reg("APB2", hwp_sysCtrlAp->Cfg_Clk_AP_APB2);
+	print_sys_reg("MEM", hwp_sysCtrlAp->Cfg_Clk_AP_MEM);
+	print_sys_reg("GPU", hwp_sysCtrlAp->Cfg_Clk_AP_GPU);
+	print_sys_reg("VPU", hwp_sysCtrlAp->Cfg_Clk_AP_VPU);
+	print_sys_reg("VOC", hwp_sysCtrlAp->Cfg_Clk_AP_VOC);
+	print_sys_reg("SFLSH", hwp_sysCtrlAp->Cfg_Clk_AP_SFLSH);
+}
+
+static int pll_freq_set(UINT32 reg_base, UINT32 freq_mhz)
+{
+	int i;
+	struct pll_freq *freq;
+	unsigned int major, minor;
+	unsigned short value_02h;
+
+	/* find pll_freq */
+	for (i = 0; i < PLL_FREQ_TABLE_COUNT; i++) {
+		if (pll_freq_table[i].freq_mhz == freq_mhz)
+			break;
+	}
+	if (i >= PLL_FREQ_TABLE_COUNT) {
+		printf("pll_freq_set, fail to find freq\n");
+		return -1;
+	}
+
+	freq = &pll_freq_table[i];
+	if (freq->with_div && (reg_base == PLL_REG_MEM_BASE)) {
+		ispi_reg_write(reg_base + PLL_REG_OFFSET_DIV,
+				freq->div);
+		// Calculate the real MEM PLL freq
+		freq_mhz *= (1 << (8 - (freq->div & 0x7)));
+	}
+	if (freq_mhz >= 800 || reg_base == PLL_REG_USB_BASE) {
+		value_02h = 0x0309;
+		// Div PLL freq by 2
+		minor = ((freq->major & 0xFFFF) << 14) |
+			((freq->minor >> 2) & 0x3FFF);
+		minor >>= 1;
+		// Recalculate the divider
+		major = (minor >> 14) & 0xFFFF;
+		minor = (minor << 2) & 0xFFFF;
+	} else {
+		value_02h = 0x0209;
+		major = freq->major;
+		minor = freq->minor;
+	}
+	if (reg_base == PLL_REG_USB_BASE)
+		value_02h ^= (1 << 8);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_02H, value_02h);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_MAJOR, major);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_MINOR, minor);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_07H, 0x0010);
+
+	return 0;
+}
+
+static void pll_setup_freq(void)
+{
+	pll_freq_set(PLL_REG_CPU_BASE, g_clock_config->PLL_FREQ_CPU);
+	// Always configure BUS PLL, even when it is being used
+	pll_freq_set(PLL_REG_BUS_BASE, g_clock_config->PLL_FREQ_BUS);
+	pll_freq_set(PLL_REG_MEM_BASE, g_clock_config->PLL_FREQ_MEM);
+	pll_freq_set(PLL_REG_USB_BASE, g_clock_config->PLL_FREQ_USB);
+}
+
+static void print_pll_freq(char *name, UINT32 value)
+{
+	printf("pll freq %s = %d\n", name, (int)value);
+}
+
+static void sys_dump_pll_freq(void)
+{
+	print_pll_freq("CPU", g_clock_config->PLL_FREQ_CPU);
+	print_pll_freq("BUS", g_clock_config->PLL_FREQ_BUS);
+	print_pll_freq("MEM", g_clock_config->PLL_FREQ_MEM);
+	//print_pll_freq("USB", g_clock_config->PLL_FREQ_USB);
+}
+
+static void pmu_get_efuse_dcdc(int buckVoltLow[])
+{
+	static const u8 setBitCnt[8] = { 0, 1, 1, 2, 1, 2, 2, 3, };
+	u16 dcdc;
+	int i;
+
+	ispi_reg_write(0x51, 0x02ed);
+	udelay(2000);
+	ispi_reg_write(0x51, 0x02fd);
+	dcdc = ispi_reg_read(0x52);
+	ispi_reg_write(0x51, 0x0200);
+
+	for (i = 0; i < 4; i++) {
+		buckVoltLow[i] = (setBitCnt[dcdc & 0x7] > 1);
+		dcdc >>= 3;
+	}
+}
+
+static void pmu_setup_init(void)
+{
+	u32 value;
+	int buck_volt_low[4] = { 0, };
+
+	rda_nand_iodrive_set();
+
+#ifdef CONFIG_RDA_PDL
+	enable_charger(0);
+#endif
+
+	ispi_open(1);
+
+	// Disable vibrator
+	ispi_reg_write(0x03, 0x9FFF);
+	// Enable bandgap chopper mode
+	ispi_reg_write(0x0F, 0x1E90);
+	// Enable high AC throttling
+	ispi_reg_write(0x12, 0x1218);
+#ifdef TARGET_TABLET_MODE
+	// Charger current (cc = 6, pre = 7)
+	ispi_reg_write(0x13, 0x1B70);
+#else
+	// Charger current (cc = 2, pre = 7)
+	ispi_reg_write(0x13, 0x1970);
+#endif
+	// Vcore DCDC freq
+	ispi_reg_write(0x2D, 0x96BA);
+	ispi_reg_write(0x2E, 0x12AA);
+	// Get efuse dcdc
+	pmu_get_efuse_dcdc(buck_volt_low);
+	// Vcore voltage
+	value = 0x9244;
+	value = PMU_SET_BITFIELD(value, RDA_PMU_VBUCK1_BIT_ACT,
+			PMU_VBUCK1_VAL +
+			((PMU_VBUCK1_VAL < 15 && buck_volt_low[0]) ? 1 : 0));
+	ispi_reg_write(0x2F, value);
+	// DDR PWM mode
+	ispi_reg_write(0x0D, 0x92D0);
+	// DDR voltage
+	value = 0xAAB5;
+	value = PMU_SET_BITFIELD(value, RDA_PMU_VBUCK3_BIT_ACT,
+			PMU_VBUCK3_VAL +
+			((PMU_VBUCK3_VAL < 15 && buck_volt_low[2]) ? 1 : 0));
+#ifdef PMU_VBUCK4_VAL
+	value = PMU_SET_BITFIELD(value, RDA_PMU_VBUCK4_BIT_ACT,
+			PMU_VBUCK4_VAL +
+			((PMU_VBUCK4_VAL < 15 && buck_volt_low[3]) ? 1 : 0));
+	value ^= RDA_PMU_VBUCK4_BIT_ACT(8);
+	// vBuck4 in low voltage range
+	ispi_reg_write(0x36, 0x6E45);
+#else
+	ispi_reg_write(0x36, 0x6E54);
+#endif
+	ispi_reg_write(0x2A, value);
+	// DDR power parameters
+	ispi_reg_write(0x4A, 0x96AA);
+	ispi_reg_write(0x4B, 0x96AA);
+
+	ispi_open(0);
+}
+
+static void setup_ddr_vtt(int vtt)
+{
+	printf("setup ddr vtt to %d\n", vtt);
+	ispi_reg_write(0x69, 0x0008 | (vtt & 0x07) );
+}
+
+#if 0
+/*
+ * we initialize usb clock, but this won't cause the usb clock jitter,
+ * because wo don't setup the usb pll
+ */
+static void usb_clock_pre_init(void)
+{
+	ispi_reg_write(0x83, 0x72ef);
+	ispi_reg_write(0x89, 0x7400);
+}
+#endif
+
+static void pll_setup_init(void)
+{
+	setup_ddr_vtt(DDR_VTT_VAL);
+
+	if (g_clock_config->DDR_CHAN_1_VALID) {
+		ispi_reg_write(0x101, g_clock_config->DDR_TIMING_101H);
+		ispi_reg_write(0x102, g_clock_config->DDR_TIMING_102H);
+		ispi_reg_write(0x103, g_clock_config->DDR_TIMING_103H);
+		ispi_reg_write(0x104, g_clock_config->DDR_TIMING_104H);
+		ispi_reg_write(0x105, g_clock_config->DDR_TIMING_105H);
+		ispi_reg_write(0x106, g_clock_config->DDR_TIMING_106H);
+		ispi_reg_write(0x107, g_clock_config->DDR_TIMING_107H);
+		ispi_reg_write(0x108, g_clock_config->DDR_TIMING_108H);
+		ispi_reg_write(0x109, g_clock_config->DDR_TIMING_109H);
+		ispi_reg_write(0x10A, g_clock_config->DDR_TIMING_10AH);
+		ispi_reg_write(0x10B, g_clock_config->DDR_TIMING_10BH);
+		ispi_reg_write(0x10C, g_clock_config->DDR_TIMING_10CH);
+		ispi_reg_write(0x10D, g_clock_config->DDR_TIMING_10DH);
+		ispi_reg_write(0x10E, g_clock_config->DDR_TIMING_10EH);
+		ispi_reg_write(0x10F, g_clock_config->DDR_TIMING_10FH);
+	}
+
+	if (g_clock_config->DDR_CHAN_2_VALID) {
+		ispi_reg_write(0x121, g_clock_config->DDR_TIMING_121H);
+		ispi_reg_write(0x122, g_clock_config->DDR_TIMING_122H);
+		ispi_reg_write(0x123, g_clock_config->DDR_TIMING_123H);
+		ispi_reg_write(0x124, g_clock_config->DDR_TIMING_124H);
+		ispi_reg_write(0x125, g_clock_config->DDR_TIMING_125H);
+		ispi_reg_write(0x126, g_clock_config->DDR_TIMING_126H);
+		ispi_reg_write(0x127, g_clock_config->DDR_TIMING_127H);
+		ispi_reg_write(0x128, g_clock_config->DDR_TIMING_128H);
+		ispi_reg_write(0x129, g_clock_config->DDR_TIMING_129H);
+		ispi_reg_write(0x12A, g_clock_config->DDR_TIMING_12AH);
+		ispi_reg_write(0x12B, g_clock_config->DDR_TIMING_12BH);
+		ispi_reg_write(0x12C, g_clock_config->DDR_TIMING_12CH);
+		ispi_reg_write(0x12D, g_clock_config->DDR_TIMING_12DH);
+		ispi_reg_write(0x12E, g_clock_config->DDR_TIMING_12EH);
+		ispi_reg_write(0x12F, g_clock_config->DDR_TIMING_12FH);
+	}
+
+	if (g_clock_config->DDR_CHAN_3_VALID) {
+		ispi_reg_write(0x141, g_clock_config->DDR_TIMING_141H);
+		ispi_reg_write(0x142, g_clock_config->DDR_TIMING_142H);
+		ispi_reg_write(0x143, g_clock_config->DDR_TIMING_143H);
+		ispi_reg_write(0x144, g_clock_config->DDR_TIMING_144H);
+		ispi_reg_write(0x145, g_clock_config->DDR_TIMING_145H);
+		ispi_reg_write(0x146, g_clock_config->DDR_TIMING_146H);
+		ispi_reg_write(0x147, g_clock_config->DDR_TIMING_147H);
+		ispi_reg_write(0x148, g_clock_config->DDR_TIMING_148H);
+		ispi_reg_write(0x149, g_clock_config->DDR_TIMING_149H);
+		ispi_reg_write(0x14A, g_clock_config->DDR_TIMING_14AH);
+		ispi_reg_write(0x14B, g_clock_config->DDR_TIMING_14BH);
+		ispi_reg_write(0x14C, g_clock_config->DDR_TIMING_14CH);
+		ispi_reg_write(0x14D, g_clock_config->DDR_TIMING_14DH);
+		ispi_reg_write(0x14E, g_clock_config->DDR_TIMING_14EH);
+		ispi_reg_write(0x14F, g_clock_config->DDR_TIMING_14FH);
+	}
+
+	if (g_clock_config->DDR_CHAN_4_VALID) {
+		ispi_reg_write(0x161, g_clock_config->DDR_TIMING_161H);
+		ispi_reg_write(0x162, g_clock_config->DDR_TIMING_162H);
+		ispi_reg_write(0x163, g_clock_config->DDR_TIMING_163H);
+		ispi_reg_write(0x164, g_clock_config->DDR_TIMING_164H);
+		ispi_reg_write(0x165, g_clock_config->DDR_TIMING_165H);
+		ispi_reg_write(0x166, g_clock_config->DDR_TIMING_166H);
+		ispi_reg_write(0x167, g_clock_config->DDR_TIMING_167H);
+		ispi_reg_write(0x168, g_clock_config->DDR_TIMING_168H);
+		ispi_reg_write(0x169, g_clock_config->DDR_TIMING_169H);
+		ispi_reg_write(0x16A, g_clock_config->DDR_TIMING_16AH);
+		ispi_reg_write(0x16B, g_clock_config->DDR_TIMING_16BH);
+		ispi_reg_write(0x16C, g_clock_config->DDR_TIMING_16CH);
+		ispi_reg_write(0x16D, g_clock_config->DDR_TIMING_16DH);
+		ispi_reg_write(0x16E, g_clock_config->DDR_TIMING_16EH);
+		ispi_reg_write(0x16F, g_clock_config->DDR_TIMING_16FH);
+	}
+
+	ispi_reg_write(0x160, g_clock_config->DDR_TIMING_160H);
+	ispi_reg_write(0x180, g_clock_config->DDR_TIMING_180H);
+	ispi_reg_write(0x181, g_clock_config->DDR_TIMING_181H);
+	ispi_reg_write(0x182, g_clock_config->DDR_TIMING_182H);
+	ispi_reg_write(0x183, g_clock_config->DDR_TIMING_183H);
+	ispi_reg_write(0x184, g_clock_config->DDR_TIMING_184H);
+	ispi_reg_write(0x185, g_clock_config->DDR_TIMING_185H);
+	ispi_reg_write(0x186, g_clock_config->DDR_TIMING_186H);
+	ispi_reg_write(0x187, g_clock_config->DDR_TIMING_187H);
+	ispi_reg_write(0x188, g_clock_config->DDR_TIMING_188H);
+	ispi_reg_write(0x189, g_clock_config->DDR_TIMING_189H);
+	ispi_reg_write(0x18A, g_clock_config->DDR_TIMING_18AH);
+	ispi_reg_write(0x18B, g_clock_config->DDR_TIMING_18BH);
+	ispi_reg_write(0x18C, g_clock_config->DDR_TIMING_18CH);
+
+	//usb_clock_pre_init();
+
+	udelay(5000);
+}
+
+static void pll_setup_mem(void)
+{
+}
+
+static void pll_setup_mem_cal(void)
+{
+}
+
+static void print_pll_reg(UINT32 index, UINT32 value)
+{
+	printf("pll reg %lx = %lx\n", index, value);
+}
+
+static void pll_dump_reg(void)
+{
+	print_pll_reg(0x005, ispi_reg_read(0x005));
+	print_pll_reg(0x006, ispi_reg_read(0x006));
+	print_pll_reg(0x063, ispi_reg_read(0x063));
+	print_pll_reg(0x065, ispi_reg_read(0x065));
+	print_pll_reg(0x066, ispi_reg_read(0x066));
+
+	if (g_clock_config->DDR_CHAN_1_VALID)
+	{
+		print_pll_reg(0x100, ispi_reg_read(0x100));
+		print_pll_reg(0x101, ispi_reg_read(0x101));
+		print_pll_reg(0x102, ispi_reg_read(0x102));
+		print_pll_reg(0x103, ispi_reg_read(0x103));
+		print_pll_reg(0x104, ispi_reg_read(0x104));
+		print_pll_reg(0x105, ispi_reg_read(0x105));
+		print_pll_reg(0x106, ispi_reg_read(0x106));
+		print_pll_reg(0x107, ispi_reg_read(0x107));
+		print_pll_reg(0x108, ispi_reg_read(0x108));
+		print_pll_reg(0x109, ispi_reg_read(0x109));
+		print_pll_reg(0x10A, ispi_reg_read(0x10A));
+		print_pll_reg(0x10B, ispi_reg_read(0x10B));
+		print_pll_reg(0x10C, ispi_reg_read(0x10C));
+		print_pll_reg(0x10D, ispi_reg_read(0x10D));
+		print_pll_reg(0x10E, ispi_reg_read(0x10E));
+		print_pll_reg(0x10F, ispi_reg_read(0x10F));
+	}
+
+	if (g_clock_config->DDR_CHAN_2_VALID)
+	{
+		print_pll_reg(0x120, ispi_reg_read(0x120));
+		print_pll_reg(0x121, ispi_reg_read(0x121));
+		print_pll_reg(0x122, ispi_reg_read(0x122));
+		print_pll_reg(0x123, ispi_reg_read(0x123));
+		print_pll_reg(0x124, ispi_reg_read(0x124));
+		print_pll_reg(0x125, ispi_reg_read(0x125));
+		print_pll_reg(0x126, ispi_reg_read(0x126));
+		print_pll_reg(0x127, ispi_reg_read(0x127));
+		print_pll_reg(0x128, ispi_reg_read(0x128));
+		print_pll_reg(0x129, ispi_reg_read(0x129));
+		print_pll_reg(0x12A, ispi_reg_read(0x12A));
+		print_pll_reg(0x12B, ispi_reg_read(0x12B));
+		print_pll_reg(0x12C, ispi_reg_read(0x12C));
+		print_pll_reg(0x12D, ispi_reg_read(0x12D));
+		print_pll_reg(0x12E, ispi_reg_read(0x12E));
+		print_pll_reg(0x12F, ispi_reg_read(0x12F));
+	}
+
+	if (g_clock_config->DDR_CHAN_3_VALID)
+	{
+		print_pll_reg(0x140, ispi_reg_read(0x140));
+		print_pll_reg(0x141, ispi_reg_read(0x141));
+		print_pll_reg(0x142, ispi_reg_read(0x142));
+		print_pll_reg(0x143, ispi_reg_read(0x143));
+		print_pll_reg(0x144, ispi_reg_read(0x144));
+		print_pll_reg(0x145, ispi_reg_read(0x145));
+		print_pll_reg(0x146, ispi_reg_read(0x146));
+		print_pll_reg(0x147, ispi_reg_read(0x147));
+		print_pll_reg(0x148, ispi_reg_read(0x148));
+		print_pll_reg(0x149, ispi_reg_read(0x149));
+		print_pll_reg(0x14A, ispi_reg_read(0x14A));
+		print_pll_reg(0x14B, ispi_reg_read(0x14B));
+		print_pll_reg(0x14C, ispi_reg_read(0x14C));
+		print_pll_reg(0x14D, ispi_reg_read(0x14D));
+		print_pll_reg(0x14E, ispi_reg_read(0x14E));
+		print_pll_reg(0x14F, ispi_reg_read(0x14F));
+	}
+
+	if (g_clock_config->DDR_CHAN_4_VALID)
+	{
+		print_pll_reg(0x161, ispi_reg_read(0x161));
+		print_pll_reg(0x162, ispi_reg_read(0x162));
+		print_pll_reg(0x163, ispi_reg_read(0x163));
+		print_pll_reg(0x164, ispi_reg_read(0x164));
+		print_pll_reg(0x165, ispi_reg_read(0x165));
+		print_pll_reg(0x166, ispi_reg_read(0x166));
+		print_pll_reg(0x167, ispi_reg_read(0x167));
+		print_pll_reg(0x168, ispi_reg_read(0x168));
+		print_pll_reg(0x169, ispi_reg_read(0x169));
+		print_pll_reg(0x16A, ispi_reg_read(0x16A));
+		print_pll_reg(0x16B, ispi_reg_read(0x16B));
+		print_pll_reg(0x16C, ispi_reg_read(0x16C));
+		print_pll_reg(0x16D, ispi_reg_read(0x16D));
+		print_pll_reg(0x16E, ispi_reg_read(0x16E));
+		print_pll_reg(0x16F, ispi_reg_read(0x16F));
+	}
+
+	print_pll_reg(0x160, ispi_reg_read(0x160));
+	print_pll_reg(0x180, ispi_reg_read(0x180));
+	print_pll_reg(0x181, ispi_reg_read(0x181));
+	print_pll_reg(0x182, ispi_reg_read(0x182));
+	print_pll_reg(0x183, ispi_reg_read(0x183));
+	print_pll_reg(0x184, ispi_reg_read(0x184));
+	print_pll_reg(0x185, ispi_reg_read(0x185));
+	print_pll_reg(0x186, ispi_reg_read(0x186));
+	print_pll_reg(0x187, ispi_reg_read(0x187));
+	print_pll_reg(0x188, ispi_reg_read(0x188));
+	print_pll_reg(0x189, ispi_reg_read(0x189));
+	print_pll_reg(0x18A, ispi_reg_read(0x18A));
+	print_pll_reg(0x18B, ispi_reg_read(0x18B));
+	print_pll_reg(0x18C, ispi_reg_read(0x18C));
+}
+
+static int clock_save_config(void)
+{
+	/* save config to nand */
+	return 1;
+}
+
+#ifdef DO_DDR_PLL_DEBUG
+
+static int ddr_get_freq(UINT8 chioce)
+{
+	switch(chioce)
+	{
+		case 1:
+			return 50;
+		case 2:
+			return 100;
+		case 3:
+			return 156;
+		case 4:
+			return 200;
+		case 5:
+			return 290;
+		case 6:
+			return 333;
+		case 7:
+			return 355;
+		case 8:
+			return 400;
+		case 9:
+			return 416;
+		case 10:
+			return 455;
+		case 11:
+			return 500;
+		case 12:
+			return 519;
+		case 13:
+			return 260;
+		default:
+			return -1;
+	}
+}
+
+static void freq_choose(void)
+{
+	UINT8 i = 0, buf[3] = {0}, choice = 0;
+	INT32 freq_temp = 0;
+
+	printf("\nPlese choose the ddr Freq:");
+	printf("\n1.50M  2.100M  3.156M  4.200M  5.290M  6.333M  7.355M  8.400M 9.416M 10.455M 11.500M 12.519M 13.260M");
+	printf("\nThe number is:");
+
+	while(1)
+	{
+		if (i > 2)
+		{
+			printf("\n Sorry, you input is wrong. Please input again:");
+			i = 0;
+		}
+		buf[i] = serial_getc();
+		serial_putc(buf[i]);
+
+		if ( ('\r' == buf[i]) || ('\n' == buf[i]))
+		{
+			serial_puts("\n");
+			break;
+		}
+
+		i++;
+	}
+
+	if (1 == i)
+		choice = buf[0] - 0x30;
+	else if (2 == i)
+		choice = 10*(buf[0] - 0x30) + (buf[1] - 0x30);
+	else
+		return;
+
+	freq_temp = ddr_get_freq(choice);
+	if (-1 == freq_temp )
+		printf("\n Sorry, the fre you choose is wrong");
+	ddrfreq = freq_temp;
+}
+
+static void data_bits_choose(void)
+{
+	UINT8 i = 0, buf[2] = {0};
+
+	printf("\nPlese choose the ddr data bits:");
+	printf("\n1.16  2.32");
+	printf("\nThe number is:");
+
+	while(1)
+	{
+		buf[i] =serial_getc();
+
+		if (i == 1)
+		{
+			if (('\r' == buf[i]) || ('\n' == buf[i]))
+			{
+				if (1 == (buf[0] - 0x30))
+					ddr32bit = 0;
+				else
+					ddr32bit = 1;
+				return;
+			}
+			else
+			{
+				printf("\n Sorry, you input is wrong. Please input again:");
+				i = 0;
+				continue;
+			}
+		}
+
+		serial_putc(buf[i]);
+
+		if ((buf[i] - 0x30) > 2 || 0 == (buf[i] - 0x30))
+			printf("\n Sorry, you input is wrong. Please input again:");
+		else
+			i++;
+	}
+}
+
+#if 0
+static void pmu_setup_calibration_voltage(UINT8 vcoreselect)
+{
+	UINT8 buf[3] = {0}, voltage = 0;
+	int i = 0;
+	UINT32 reg_value,temp, regid = 0;
+
+	ispi_open(1);
+	if (1 == vcoreselect)
+	{
+		regid = 0x2f;
+		printf("\nPlese input vcore voltage(0 ~ 15):");
+	}
+	else
+	{
+		regid = 0x2a;
+		printf("\nPlese input DDR voltage(0 ~ 15):");
+	}
+
+
+	while(1)
+	{
+		if (i > 2)
+		{
+			printf("\n Sorry, you input is wrong. Please input again:");
+			i = 0;
+		}
+		buf[i] = serial_getc();
+		serial_putc(buf[i]);
+
+		if ( ('\r' == buf[i]) || ('\n' == buf[i]))
+		{
+			printf("\n");
+			break;
+		}
+
+		i++;
+	}
+
+	if (1 == i)
+		voltage = buf[0] - 0x30;
+	else if (2 == i)
+		voltage = 10*(buf[0] - 0x30) + (buf[1] - 0x30);
+	else
+		return;
+
+	temp = (UINT32)voltage;
+	temp = (temp & 0xf) << 12;
+	reg_value = ispi_reg_read(regid);
+	reg_value &= ~(0xf << 12);
+	reg_value |= temp ;
+	ispi_reg_write(regid, reg_value);
+	mdelay(100);
+}
+#endif
+
+static void pmu_setup_calibration_voltage(UINT8 vcoreselect)
+{
+	UINT8 buf[3] = {0}, voltage = 0;
+	int i = 0;
+	UINT32 reg_value,temp, regid = 0;
+
+	ispi_open(1);
+	if (1 == vcoreselect)
+	{
+		regid = 0x2f;
+		printf("\nPlese input vcore voltage(0 ~ 15):");
+	}
+	else
+	{
+		regid = 0x2a;
+		if (2 == vcoreselect)
+			printf("\nPlese input DDR buck3 voltage(0 ~ 15):");
+		else
+			printf("\nPlese input DDR buck4 voltage(0 ~ 15):");
+	}
+
+	while(1)
+	{
+		if (i > 2)
+		{
+			printf("\n Sorry, you input is wrong. Please input again:");
+			i = 0;
+		}
+		buf[i] = serial_getc();
+		serial_putc(buf[i]);
+
+		if ( ('\r' == buf[i]) || ('\n' == buf[i]))
+		{
+			printf("\n");
+			break;
+		}
+
+		i++;
+	}
+
+	if (1 == i)
+		voltage = buf[0] - 0x30;
+	else if (2 == i)
+		voltage = 10*(buf[0] - 0x30) + (buf[1] - 0x30);
+	else
+		return;
+
+	if ((vcoreselect == 1) || (vcoreselect == 2))
+	{
+		temp = (UINT32)voltage;
+		temp = (temp & 0xf) << 12;
+		reg_value = ispi_reg_read(regid);
+		reg_value &= ~(0xf << 12);
+		reg_value |= temp ;
+		ispi_reg_write(regid, reg_value);
+		mdelay(100);
+	}
+	else
+	{
+		temp = (UINT32)voltage;
+		temp = (temp & 0xf) << 4;
+		reg_value = ispi_reg_read(regid);
+		reg_value &= ~(0xf << 4);
+		reg_value |= temp ;
+		reg_value ^= RDA_PMU_VBUCK4_BIT_ACT(8);
+		ispi_reg_write(regid, reg_value);
+		ispi_reg_write(0x0D, 0x92D0);
+		ispi_reg_write(0x4B, 0x96A8);
+		mdelay(100);
+	}
+}
+
+static void pmu_buck4_buck3_choose(void)
+{
+	UINT8 i = 0, buf[2] = {0};
+	UINT8 ddr_voltage_source = 0;
+
+	printf("\nPlese choose the ddr voltage:");
+	printf("\n1.DDR3L  2.DDR3");
+	printf("\nThe number is:");
+
+	while(1)
+	{
+		buf[i] =serial_getc();
+
+		if (i == 1)
+		{
+			if (('\r' == buf[i]) || ('\n' == buf[i]))
+			{
+				if (1 == (buf[0] - 0x30))
+					ddr_voltage_source =2;
+				else{
+					ddr_voltage_source = 3;
+					pmu_setup_calibration_voltage(2);
+				}
+				pmu_setup_calibration_voltage(ddr_voltage_source);
+				return;
+			}
+			else
+			{
+				printf("\n Sorry, you input is wrong. Please input again:");
+				i = 0;
+				continue;
+			}
+		}
+
+		serial_putc(buf[i]);
+
+		if ((buf[i] - 0x30) > 2 || 0 == (buf[i] - 0x30))
+			printf("\n Sorry, you input is wrong. Please input again:");
+		else
+			i++;
+	}
+}
+
+
+void clock_load_ddr_cal_config(void)
+{
+	clock_debug_config.PLL_FREQ_MEM = ddrfreq;
+	if (ddrfreq < 200)
+		clock_debug_config.DDR_FLAGS |= DDR_FLAGS_DLLOFF;
+	else
+		clock_debug_config.DDR_FLAGS &= ~DDR_FLAGS_DLLOFF;
+
+	if (0 == ddr32bit)
+	{
+		clock_debug_config.DDR_CHAN_3_VALID = 0;
+		clock_debug_config.DDR_CHAN_4_VALID = 0;
+	}
+
+	clock_debug_config.DDR_PARA &= ~DDR_PARA_MEM_BITS_MASK;
+	if (0 == ddr32bit)
+		clock_debug_config.DDR_PARA |= DDR_PARA_MEM_BITS(1);
+	else
+		clock_debug_config.DDR_PARA |= DDR_PARA_MEM_BITS(2);
+}
+
+static int serial_gets(UINT8 *pstr)
+{
+    UINT32 length;
+
+    length = 0;
+    while(1) {
+        pstr[length] = serial_getc();
+        if(pstr[length] == '\r') {
+            pstr[length] = 0x00;
+            break;
+        }
+        else if( pstr[length] == '\b' ) {
+            if(length>0) {
+                length --;
+                printf("\b");
+            }
+        }
+        else {
+            serial_putc(pstr[length]);
+            length ++;
+        }
+
+        if(length > 32)
+            return -1;
+    }
+    return length;
+}
+
+UINT32 asc2hex(UINT8 *pstr, UINT8 len)
+{
+	UINT8 i,ch,mylen;
+	UINT32 hexvalue;
+
+	for(mylen=0,i=0; i<8; i++)
+	{
+		if( pstr[i] == 0 )
+			break;
+		mylen ++;
+	}
+	if( len != 0 )
+	{
+		if(mylen>len)
+			mylen = len;
+	}
+	if(mylen>8)
+		mylen = 8;
+
+	hexvalue = 0;
+	for (i = 0; i < mylen; i++)
+	{
+		hexvalue <<= 4;
+		ch = *(pstr+i);
+		if((ch>='0') && (ch<='9'))
+			hexvalue |= ch - '0';
+		else if((ch>='A') && (ch<='F'))
+			hexvalue |= ch - ('A' - 10);
+		else if((ch>='a') && (ch<='f'))
+			hexvalue |= ch - ('a' - 10);
+		else
+			;
+	}
+	return(hexvalue);
+}
+
+static int process_cmd(char * cmd)
+{
+	char cmd_element[3][16] = {{0}};
+	char * cmd_temp = cmd;
+	UINT8 i = 0, cmd_element_num = 0, former_space = 1;
+	UINT16 reg = 0, reg_value = 0;
+
+	if (NULL == cmd)
+		return -1;
+
+	while(('\0' != *cmd_temp) && ('\r' != *cmd_temp) && ('\n' != *cmd_temp))
+	{
+		if (' ' == * cmd_temp)
+		{
+			if (0 == former_space)
+			{
+				former_space = 1;
+				cmd_element[cmd_element_num][i] = '\0';
+				cmd_element_num++;
+				if (cmd_element_num > 2)
+					return -1;
+			
+				i = 0;
+			}
+		}
+		else
+		{
+			former_space = 0;
+			cmd_element[cmd_element_num][i] = *cmd_temp;
+			i++;
+			if (i > 6)
+				return -1;
+		}
+
+		cmd_temp++;	
+	}
+
+	cmd_element[cmd_element_num][i] = '\0';
+
+	if (!strcmp(cmd_element[0], "read"))
+	{
+		if (cmd_element_num == 2)
+			return -1;
+		if (('0' != cmd_element[1][0]) || ('x' != cmd_element[1][1]))
+			return -1;
+		reg = (UINT16)asc2hex((UINT8 *)&cmd_element[1][2], 4);
+		reg_value = ispi_reg_read(reg);
+		printf("value = 0x%x", reg_value);
+		printf("\nddrPll#");
+	}	
+	else if (!strcmp(cmd_element[0], "write"))
+	{
+		if (cmd_element_num != 2)
+			return -1;
+		if (('0' != cmd_element[1][0]) || ('x' != cmd_element[1][1])
+		   || ('0' != cmd_element[2][0]) || ('x' != cmd_element[2][1]))
+			return -1;
+
+		reg = (UINT16)asc2hex((UINT8 *)&cmd_element[1][2], 4);
+		reg_value  = (UINT16)asc2hex((UINT8 *)&cmd_element[2][2], 4);
+		ispi_reg_write(reg, reg_value);
+	}
+	else if (!strcmp(cmd_element[0], "finish"))
+	{
+		return 1;
+	}
+	else if (!strcmp(cmd_element[0], "dump"))
+	{    
+		pll_dump_reg();
+		printf("ddrPll#");
+	}
+	else
+	{    
+		return -1;
+	}
+
+	return 0;
+}
+
+static void cmd_input(void)
+{
+	char cmd[48] = {0};
+	int len = 0;
+	
+	ispi_open(0);
+	printf("\nddrPll#");
+	while(1)
+	{
+		len = serial_gets((UINT8 *)cmd);
+		printf("\nddrPll#");
+		if (len > 0)
+		{
+			int result = 0;
+
+			result =  process_cmd(cmd);
+			if (-1 == result)
+				printf("command error! \nddrPll#");
+			else if (1 == result)
+				break;
+			else
+				continue;
+		}
+	}
+
+	return;
+}
+
+#endif /* DO_DDR_PLL_DEBUG */
+
+int clock_init(void)
+{
+#ifdef DO_DDR_PLL_DEBUG
+	char choice = 'n';
+#endif
+
+	/* First check current usb usage */
+	check_usb_usage();
+
+	printf("Init Clock ...\n");
+	g_clock_config = get_default_clock_config();
+
+	printf("Clock config ver: %d.%d\n",
+		g_clock_config->VERSION_MAJOR, g_clock_config->VERSION_MINOR);
+
+	pmu_setup_init();
+
+#ifdef DO_DDR_PLL_DEBUG
+	printf("If you want to config the ddr para manully ?(y = yes, n = no) \n");
+	choice = serial_getc();
+	if (choice == 'y')
+	{
+		memcpy(&clock_debug_config, g_clock_config,
+				sizeof(clock_debug_config));
+		g_clock_config = &clock_debug_config;
+		pmu_setup_calibration_voltage(1);
+		pmu_buck4_buck3_choose();
+		freq_choose();
+		data_bits_choose();
+		clock_load_ddr_cal_config();
+	}
+#endif
+
+	sys_shutdown_pll();
+	ispi_open(0);
+	pll_setup_init();
+#ifdef DO_DDR_PLL_DEBUG
+	if (choice == 'y')
+		cmd_input();
+#endif
+	pll_setup_freq();
+	sys_setup_pll();
+	sys_setup_clk();
+
+	if (g_clock_config->DDR_CAL) {
+		printf("Init DDR for ddr_cal\n");
+		ddr_init(g_clock_config->DDR_FLAGS, g_clock_config->DDR_PARA);
+		printf("Done\n");
+		pll_setup_mem_cal();
+		clock_save_config();
+	} else {
+		pll_setup_mem();
+	}
+
+	sys_dump_pll_freq();
+	sys_dump_clk();
+	pll_dump_reg();
+
+	printf("Init DDR, flag = 0x%04x, para = 0x%08lx\n",
+		g_clock_config->DDR_FLAGS, g_clock_config->DDR_PARA);
+	ddr_init(g_clock_config->DDR_FLAGS, g_clock_config->DDR_PARA);
+	printf("Done\n");
+
+	#ifdef DO_SIMPLE_DDR_TEST
+	mem_test_write();
+	mem_test_read();
+#endif
+
+	return 0;
+}
+
+#else /* CONFIG_RDA_FPGA */
+
+int clock_init(void)
+{
+	u16 ddr_flags = DDR_FLAGS_DLLOFF
+		| DDR_FLAGS_ODT(1)
+		| DDR_FLAGS_RON(0);
+	//32bit
+	u32 ddr_para = DDR_PARA_MEM_BITS(2)
+		| DDR_PARA_BANK_BITS(3)
+		| DDR_PARA_ROW_BITS(3)
+		| DDR_PARA_COL_BITS(2);
+
+	printf("Init DDR\n");
+	ddr_init(ddr_flags, ddr_para);
+	printf("Done\n");
+
+#ifdef DO_SIMPLE_DDR_TEST
+	mem_test_write();
+	mem_test_read();
+#endif
+
+	return 0;
+}
+
+#endif /* CONFIG_RDA_FPGA */
+
diff --git a/board/rda/rda8820/clock_config.c b/board/rda/rda8820/clock_config.c
new file mode 100644
index 0000000000..84091581fc
--- /dev/null
+++ b/board/rda/rda8820/clock_config.c
@@ -0,0 +1,147 @@
+#ifndef TARGET_TOOL
+#include <common.h>
+#include <asm/arch/factory.h>
+#include "clock_config.h"
+#endif
+
+#include "ddr3.h"
+#include "tgt_ap_clock_config.h"
+
+static const struct clock_config clock_default_config = {
+	/* Header */
+	0, 			// MAGIC;
+	CLOCK_VER_MAJOR,	// VERSION_MAJOR;
+	CLOCK_VER_MINOR,	// VERSION_MINOR;
+	/* PLL Freqs (MHz) */
+	_TGT_AP_PLL_CPU_FREQ,	// PLL_FREQ_CPU; /* 05, 06 */
+	_TGT_AP_PLL_BUS_FREQ,	// PLL_FREQ_BUS; /* 25, 26 */
+	_TGT_AP_PLL_MEM_FREQ,	// PLL_FREQ_MEM; /* 65, 66 */
+	_TGT_AP_PLL_USB_FREQ,	// PLL_FREQ_USB; /* 85, 86 */
+	/* DDR Cal */
+	0,			// DDR_CAL;
+	/* DDR_FLAGS */
+	DDR_FLAGS_ODT(_TGT_AP_DDR_ODT)	// 010 -- 120 Ohm
+#if (_TGT_AP_DDR_CLOCK < 200)
+	    | DDR_FLAGS_DLLOFF
+#endif
+#ifdef _TGT_AP_DDR_LOWPWR
+	    | DDR_FLAGS_LOWPWR
+#endif
+	    | DDR_FLAGS_RON(_TGT_AP_DDR_RON),	// 00 -- 40 Ohm
+	/* DDR_PARA */
+	DDR_PARA_CHIP_BITS(_TGT_AP_DDR_CHIP_BITS)
+	    | DDR_PARA_MEM_BITS(_TGT_AP_DDR_MEM_BITS)
+	    | DDR_PARA_BANK_BITS(_TGT_AP_DDR_BANK_BITS)
+	    | DDR_PARA_ROW_BITS(_TGT_AP_DDR_ROW_BITS )
+	    | DDR_PARA_COL_BITS(_TGT_AP_DDR_COL_BITS),
+
+	/* AP sysctrl */
+	_TGT_AP_CLK_CPU,	// CLK_CPU;
+	_TGT_AP_CLK_AXI,	// CLK_AXI;
+	_TGT_AP_CLK_GCG,	// CLK_GCG;
+	_TGT_AP_CLK_AHB1,	// CLK_AHB1;
+	_TGT_AP_CLK_APB1,	// CLK_APB1;
+	_TGT_AP_CLK_APB2,	// CLK_APB2;
+	_TGT_AP_CLK_MEM,	// CLK_MEM;
+	_TGT_AP_CLK_GPU,	// CLK_GPU;
+	_TGT_AP_CLK_VPU,	// CLK_VPU;
+	_TGT_AP_CLK_VOC,	// CLK_VOC;
+	_TGT_AP_CLK_SFLSH,	// CLK_SFLSH;
+	0,			// RESERVE;
+
+#if 0
+	/* DDR timings, defined in target */
+	DDR_CHAN_1_VALID_VAL,	// DDR_CHAN_1_VALID;
+	DDR_TIMING_101H_VAL,	// DDR_TIMING_101H;
+	DDR_TIMING_102H_VAL,	// DDR_TIMING_102H;
+	DDR_TIMING_103H_VAL,	// DDR_TIMING_103H;
+	DDR_TIMING_104H_VAL,	// DDR_TIMING_104H;
+	DDR_TIMING_105H_VAL,	// DDR_TIMING_105H;
+	DDR_TIMING_106H_VAL,	// DDR_TIMING_106H;
+	DDR_TIMING_107H_VAL,	// DDR_TIMING_107H;
+	DDR_TIMING_108H_VAL,	// DDR_TIMING_108H;
+	DDR_TIMING_109H_VAL,	// DDR_TIMING_109H;
+	DDR_TIMING_10AH_VAL,	// DDR_TIMING_10AH;
+	DDR_TIMING_10BH_VAL,	// DDR_TIMING_10BH;
+	DDR_TIMING_10CH_VAL,	// DDR_TIMING_10CH;
+	DDR_TIMING_10DH_VAL,	// DDR_TIMING_10DH;
+	DDR_TIMING_10EH_VAL,	// DDR_TIMING_10EH;
+	DDR_TIMING_10FH_VAL,	// DDR_TIMING_10FH;
+
+	DDR_CHAN_2_VALID_VAL,	// DDR_CHAN_2_VALID;
+	DDR_TIMING_121H_VAL,	// DDR_TIMING_121H;
+	DDR_TIMING_122H_VAL,	// DDR_TIMING_122H;
+	DDR_TIMING_123H_VAL,	// DDR_TIMING_123H;
+	DDR_TIMING_124H_VAL,	// DDR_TIMING_124H;
+	DDR_TIMING_125H_VAL,	// DDR_TIMING_125H;
+	DDR_TIMING_126H_VAL,	// DDR_TIMING_126H;
+	DDR_TIMING_127H_VAL,	// DDR_TIMING_127H;
+	DDR_TIMING_128H_VAL,	// DDR_TIMING_128H;
+	DDR_TIMING_129H_VAL,	// DDR_TIMING_129H;
+	DDR_TIMING_12AH_VAL,	// DDR_TIMING_12AH;
+	DDR_TIMING_12BH_VAL,	// DDR_TIMING_12BH;
+	DDR_TIMING_12CH_VAL,	// DDR_TIMING_12CH;
+	DDR_TIMING_12DH_VAL,	// DDR_TIMING_12DH;
+	DDR_TIMING_12EH_VAL,	// DDR_TIMING_12EH;
+	DDR_TIMING_12FH_VAL,	// DDR_TIMING_12FH;
+
+	DDR_CHAN_3_VALID_VAL,	// DDR_CHAN_3_VALID;
+	DDR_TIMING_141H_VAL,	// DDR_TIMING_141H;
+	DDR_TIMING_142H_VAL,	// DDR_TIMING_142H;
+	DDR_TIMING_143H_VAL,	// DDR_TIMING_143H;
+	DDR_TIMING_144H_VAL,	// DDR_TIMING_144H;
+	DDR_TIMING_145H_VAL,	// DDR_TIMING_145H;
+	DDR_TIMING_146H_VAL,	// DDR_TIMING_146H;
+	DDR_TIMING_147H_VAL,	// DDR_TIMING_147H;
+	DDR_TIMING_148H_VAL,	// DDR_TIMING_148H;
+	DDR_TIMING_149H_VAL,	// DDR_TIMING_149H;
+	DDR_TIMING_14AH_VAL,	// DDR_TIMING_14AH;
+	DDR_TIMING_14BH_VAL,	// DDR_TIMING_14BH;
+	DDR_TIMING_14CH_VAL,	// DDR_TIMING_14CH;
+	DDR_TIMING_14DH_VAL,	// DDR_TIMING_14DH;
+	DDR_TIMING_14EH_VAL,	// DDR_TIMING_14EH;
+	DDR_TIMING_14FH_VAL,	// DDR_TIMING_14FH;
+
+	DDR_CHAN_4_VALID_VAL,	// DDR_CHAN_4_VALID;
+	DDR_TIMING_161H_VAL,	// DDR_TIMING_161H;
+	DDR_TIMING_162H_VAL,	// DDR_TIMING_162H;
+	DDR_TIMING_163H_VAL,	// DDR_TIMING_163H;
+	DDR_TIMING_164H_VAL,	// DDR_TIMING_164H;
+	DDR_TIMING_165H_VAL,	// DDR_TIMING_165H;
+	DDR_TIMING_166H_VAL,	// DDR_TIMING_166H;
+	DDR_TIMING_167H_VAL,	// DDR_TIMING_167H;
+	DDR_TIMING_168H_VAL,	// DDR_TIMING_168H;
+	DDR_TIMING_169H_VAL,	// DDR_TIMING_169H;
+	DDR_TIMING_16AH_VAL,	// DDR_TIMING_16AH;
+	DDR_TIMING_16BH_VAL,	// DDR_TIMING_16BH;
+	DDR_TIMING_16CH_VAL,	// DDR_TIMING_16CH;
+	DDR_TIMING_16DH_VAL,	// DDR_TIMING_16DH;
+	DDR_TIMING_16EH_VAL,	// DDR_TIMING_16EH;
+	DDR_TIMING_16FH_VAL,	// DDR_TIMING_16FH;
+
+	DDR_TIMING_160H_VAL,	// DDR_TIMING_160H;
+	DDR_TIMING_180H_VAL,	// DDR_TIMING_180H;
+	DDR_TIMING_181H_VAL,	// DDR_TIMING_181H;
+	DDR_TIMING_182H_VAL,	// DDR_TIMING_182H;
+	DDR_TIMING_183H_VAL,	// DDR_TIMING_183H;
+	DDR_TIMING_184H_VAL,	// DDR_TIMING_184H;
+	DDR_TIMING_185H_VAL,	// DDR_TIMING_185H;
+	DDR_TIMING_186H_VAL,	// DDR_TIMING_186H;
+	DDR_TIMING_187H_VAL,	// DDR_TIMING_187H;
+	DDR_TIMING_188H_VAL,	// DDR_TIMING_188H;
+	DDR_TIMING_189H_VAL,	// DDR_TIMING_189H;
+	DDR_TIMING_18AH_VAL,	// DDR_TIMING_18AH;
+	DDR_TIMING_18BH_VAL,	// DDR_TIMING_18BH;
+	DDR_TIMING_18CH_VAL,	// DDR_TIMING_18CH;
+#endif
+};
+
+const struct clock_config *get_default_clock_config(void)
+{
+#ifndef TARGET_TOOL
+	BUILD_BUG_ON(sizeof(struct clock_config) > AP_FACTORY_CLOCK_CFG_LEN);
+#endif
+
+	return &clock_default_config;
+}
+
diff --git a/board/rda/rda8820/clock_config.h b/board/rda/rda8820/clock_config.h
new file mode 100644
index 0000000000..e39dfa8652
--- /dev/null
+++ b/board/rda/rda8820/clock_config.h
@@ -0,0 +1,128 @@
+#ifndef __CLOCK_CONFIG_H__
+#define __CLOCK_CONFIG_H__
+
+typedef unsigned long               UINT32;
+typedef unsigned short              UINT16;
+typedef long                        INT32;
+typedef short                       INT16;
+typedef unsigned char               UINT8;
+typedef char                        INT8;
+
+#define CLOCK_VER_MAJOR		2
+#define CLOCK_VER_MINOR		0
+
+struct clock_config {
+	/* Header */
+	UINT32 MAGIC;
+	UINT16 VERSION_MAJOR;
+	UINT16 VERSION_MINOR;
+	/* PLL Freqs (MHz) */
+	UINT32 PLL_FREQ_CPU;	/* 05, 06 */
+	UINT32 PLL_FREQ_BUS;	/* 25, 26 */
+	UINT32 PLL_FREQ_MEM;	/* 65, 66 */
+	UINT32 PLL_FREQ_USB;	/* 85, 86 */
+	/* DDR Flags */
+	UINT16 DDR_CAL;
+	UINT16 DDR_FLAGS;
+	UINT32 DDR_PARA;
+	/* AP sysctrl */
+	UINT16 CLK_CPU;
+	UINT16 CLK_AXI;
+	UINT16 CLK_GCG;
+	UINT16 CLK_AHB1;
+	UINT16 CLK_APB1;
+	UINT16 CLK_APB2;
+	UINT16 CLK_MEM;
+	UINT16 CLK_GPU;
+	UINT16 CLK_VPU;
+	UINT16 CLK_VOC;
+	UINT16 CLK_SFLSH;
+	UINT16 RESERVE;
+	/* DDR timings */
+	UINT16 DDR_CHAN_1_VALID;
+	UINT16 DDR_TIMING_101H;
+	UINT16 DDR_TIMING_102H;
+	UINT16 DDR_TIMING_103H;
+	UINT16 DDR_TIMING_104H;
+	UINT16 DDR_TIMING_105H;
+	UINT16 DDR_TIMING_106H;
+	UINT16 DDR_TIMING_107H;
+	UINT16 DDR_TIMING_108H;
+	UINT16 DDR_TIMING_109H;
+	UINT16 DDR_TIMING_10AH;
+	UINT16 DDR_TIMING_10BH;
+	UINT16 DDR_TIMING_10CH;
+	UINT16 DDR_TIMING_10DH;
+	UINT16 DDR_TIMING_10EH;
+	UINT16 DDR_TIMING_10FH;
+
+	UINT16 DDR_CHAN_2_VALID;
+	UINT16 DDR_TIMING_121H;
+	UINT16 DDR_TIMING_122H;
+	UINT16 DDR_TIMING_123H;
+	UINT16 DDR_TIMING_124H;
+	UINT16 DDR_TIMING_125H;
+	UINT16 DDR_TIMING_126H;
+	UINT16 DDR_TIMING_127H;
+	UINT16 DDR_TIMING_128H;
+	UINT16 DDR_TIMING_129H;
+	UINT16 DDR_TIMING_12AH;
+	UINT16 DDR_TIMING_12BH;
+	UINT16 DDR_TIMING_12CH;
+	UINT16 DDR_TIMING_12DH;
+	UINT16 DDR_TIMING_12EH;
+	UINT16 DDR_TIMING_12FH;
+
+	UINT16 DDR_CHAN_3_VALID;
+	UINT16 DDR_TIMING_141H;
+	UINT16 DDR_TIMING_142H;
+	UINT16 DDR_TIMING_143H;
+	UINT16 DDR_TIMING_144H;
+	UINT16 DDR_TIMING_145H;
+	UINT16 DDR_TIMING_146H;
+	UINT16 DDR_TIMING_147H;
+	UINT16 DDR_TIMING_148H;
+	UINT16 DDR_TIMING_149H;
+	UINT16 DDR_TIMING_14AH;
+	UINT16 DDR_TIMING_14BH;
+	UINT16 DDR_TIMING_14CH;
+	UINT16 DDR_TIMING_14DH;
+	UINT16 DDR_TIMING_14EH;
+	UINT16 DDR_TIMING_14FH;
+
+	UINT16 DDR_CHAN_4_VALID;
+	UINT16 DDR_TIMING_161H;
+	UINT16 DDR_TIMING_162H;
+	UINT16 DDR_TIMING_163H;
+	UINT16 DDR_TIMING_164H;
+	UINT16 DDR_TIMING_165H;
+	UINT16 DDR_TIMING_166H;
+	UINT16 DDR_TIMING_167H;
+	UINT16 DDR_TIMING_168H;
+	UINT16 DDR_TIMING_169H;
+	UINT16 DDR_TIMING_16AH;
+	UINT16 DDR_TIMING_16BH;
+	UINT16 DDR_TIMING_16CH;
+	UINT16 DDR_TIMING_16DH;
+	UINT16 DDR_TIMING_16EH;
+	UINT16 DDR_TIMING_16FH;
+
+	UINT16 DDR_TIMING_160H;
+	UINT16 DDR_TIMING_180H;
+	UINT16 DDR_TIMING_181H;
+	UINT16 DDR_TIMING_182H;
+	UINT16 DDR_TIMING_183H;
+	UINT16 DDR_TIMING_184H;
+	UINT16 DDR_TIMING_185H;
+	UINT16 DDR_TIMING_186H;
+	UINT16 DDR_TIMING_187H;
+	UINT16 DDR_TIMING_188H;
+	UINT16 DDR_TIMING_189H;
+	UINT16 DDR_TIMING_18AH;
+	UINT16 DDR_TIMING_18BH;
+	UINT16 DDR_TIMING_18CH;
+};
+
+const struct clock_config *get_default_clock_config(void);
+
+#endif
diff --git a/board/rda/rda8820/config.mk b/board/rda/rda8820/config.mk
new file mode 100644
index 0000000000..ec124aff34
--- /dev/null
+++ b/board/rda/rda8820/config.mk
@@ -0,0 +1,11 @@
+#
+#the spl code should not exceed the SPL_MAX_SIZE,and if 
+#the spl don't up to the max size, paddint the last with
+#zero(or 0xff?)
+
+#48kbytes, 48*1024
+#SPL_APPENDING_TO	:= 48
+#SPL_MAX_SIZE	:= 49512
+
+# space for spl(48KiB) & mtd partition table(24KiB)
+SPL_APPENDING_TO   := 72
diff --git a/board/rda/rda8820/ddr3.c b/board/rda/rda8820/ddr3.c
new file mode 100644
index 0000000000..e3628005ac
--- /dev/null
+++ b/board/rda/rda8820/ddr3.c
@@ -0,0 +1,516 @@
+#include <common.h>
+#include <asm/arch/rda_iomap.h>
+
+#include "ddr3.h"
+#include "ddr3_init.h"
+#include "tgt_ap_clock_config.h"
+
+#pragma GCC push_options
+#pragma GCC optimize ("O0")
+
+#define DDR_TYPE _TGT_AP_DDR_TYPE
+
+#define DF_DELAY  (0x10000)
+
+#define DMC_REG_BASE RDA_DMC400_BASE
+#define PHY_REG_BASE RDA_DDRPHY_BASE
+
+#define  PHY_RDLAT          0
+#define  PHYWRDATA          1
+#define  STA                3
+#define  CLKSEL             4
+#define  PSSTART            5
+#define  PSDONE             6
+#define  LOCKED             6
+#define  CTRL_DELAY         7
+#define  RDELAY_SEL         8
+#define  WDELAY_SEL         9
+#define  PHY_RESET          10
+#define  RESET_DDR3         11
+#define  ODT_DELAY          12
+#define  DDR3_USED          13
+#define  WRITE_ENABLE_LAT   14
+#define  WRITE_DATA_LAT     15
+#define  DQOUT_ENABLE_LAT   16
+#define  DATA_ODT_ENABLE_REG	20
+#define  DATA_WRITE_ENABLE_REG  48   
+#define  DMC_READY	128
+
+#define ARRAY_NUM(n) (sizeof(n))/(sizeof(n[0]))
+
+#if (DDR_TYPE == 1)
+static dmc_reg_t dmc_reg_cfg[] = {
+	{T_REFI,	0x186,		0x186},
+	{T_RFC,		0x230024,	0x230024},
+	{T_RFC,		0x540024,	0x540024},
+	{T_MRR,		0x2,		0x2},
+	{T_MRW,		0x5,		0x5},
+	{T_RCD,		0x8,		0x8},
+	{T_RAS,		0x11,		0x11},
+	{T_RP,		0x8,		0x8},
+	{T_RPALL,	0x9,		0x9},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0x4,		0x4},
+	{T_RTW,		0xb,		0xb},
+	{T_RTP,		0x6,		0x6},
+	{T_WR,		0xe,		0xe},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTW,		0x40000,	0x40000},
+	{RD_LATENCY,	0x6,		0x6},
+	{WR_LATENCY,	0x3,		0x3},
+	{T_RDDATA_EN,	0x3,		0x3},
+	{T_PHYWRLAT,	0x101,		0x101},
+	{T_PHYWRLAT,	0x101,		0x101},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0x80003,	0x80003},
+	{T_ESR,		0x6,		0x6},
+	{T_XSR,		0x1000058,	0x1000058},
+	{T_XSR,		0x580058,	0x580058},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{T_EP,		0x5,		0x5},
+	{RDLVL_CTRL,	0x1010,		0x1010},
+	{RDLVL_CTRL,	0x1110,		0x1110},
+	{RDLVL_CTRL,	0x11110,	0x11110},
+	{REFRESH_CTRL,	0x0,		0x0},
+	{REFRESH_CTRL,	0x0,		0x0},
+	{ECC_CTRL,	0x0,		0x0},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+};
+#elif (DDR_TYPE == 2)
+static dmc_reg_t dmc_reg_cfg[] = {
+	{T_REFI,	0x3f,		0x3f},
+	{T_RFC,		0x230024,	0x230024},
+	{T_RFC,		0x540024,	0x540024},
+	{T_MRR,		0x2,		0x2},
+	{T_MRW,		0x5,		0x5},
+	{T_RCD,		0x8,		0x8},
+	{T_RAS,		0x11,		0x11},
+	{T_RP,		0x8,		0x8},
+	{T_RPALL,	0x9,		0x9},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0x4,		0x4},
+	{T_RTW,		0xb,		0xb},
+	{T_RTP,		0x6,		0x6},
+	{T_WR,		0xe,		0xe},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTW,		0x40000,	0x40000},
+	{RD_LATENCY,	0x6,		0x6},
+	{WR_LATENCY,	0x3,		0x3},
+	{T_RDDATA_EN,	0x3,		0x3},
+	{T_PHYWRLAT,	0x101,		0x101},
+	{T_PHYWRLAT,	0x103,		0x103},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0x80003,	0x80003},
+	{T_ESR,		0x6,		0x6},
+	{T_XSR,		0x1000058,	0x1000058},
+	{T_XSR,		0x580058,	0x580058},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{T_EP,		0x5,		0x5},
+	{RDLVL_CTRL,	0x1010,		0x1010},
+	{RDLVL_CTRL,	0x1110,		0x1110},
+	{RDLVL_CTRL,	0x11110,	0x11110},
+	{REFRESH_CTRL,	0x1,		0x1},
+	{ECC_CTRL,	0x0,		0x0},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+};
+#elif (DDR_TYPE == 3)
+static dmc_reg_t dmc_reg_cfg[] = {
+	{QOSX_CTRL7,	0x08, 		0x08},
+	{TURNAROUND_PRIO,0x1A, 		0x0},
+	{HIT_PRIO,	0x1A, 		0x0},
+	{T_REFI,	0x186,		0x3f},
+	{QUEUE_CTRL,	0xffff,		0x0},
+	{T_RFC,		0x23008c,	0x23008c},
+	{T_RFC,		0x8c008c,	0x8c008c},
+	{T_MRR,		0x4,		0x4},
+	{T_MRW,		0xc,		0xc},
+	{T_RCD,		0x6,		0x6},
+	{T_RAS,		0xf,		0xf},
+	{T_RP,		0x6,		0x6},
+	{T_RPALL,	0x6,		0x5},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0x6,		0x6},
+//	{T_RTW,		0x7,		0x6},
+	{T_RTW,		0x0c,		0x6},// turn for now
+//	{T_RTW,		0x1f,		0x1f},//for low speed
+	{T_RTP,		0x4,		0x4},
+	{T_WR,		0xf,		0x10},
+	{T_WTR,		0x4000d,	0x4000d},
+	{T_WTR,		0x6000d,	0x6000f},
+//	{T_WTR,		0x6001f,	0x6001f},//for low speed
+	{T_WTW,		0x60000,	0x60000},
+	{RD_LATENCY,	0x5,		0x5},
+	{WR_LATENCY,	0x5,		0x5},
+	{T_RDDATA_EN,	0x8,		0x2},
+	{T_PHYWRLAT,	0x104,		0x105},
+	{T_PHYWRLAT,	0x104,		0x105},
+	{T_EP,		0x3,		0x3},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0xa0003,	0xa0003},
+	{T_ESR,		0x4,		0x4},
+	{T_XSR,		0x1000090,	0x1000090},
+	{T_XSR,		0x2000090,	0x2000090},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{ECC_CTRL,	0x0,		0x0},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+};
+#else
+#error "Wrong DDR Type"
+#endif
+
+void config_ddr_phy(UINT16 flag)
+{
+	int wait_idle;
+	UINT16 __attribute__((unused)) dll_off;
+
+	wait_idle = DF_DELAY + 16;
+	dll_off = flag & DDR_FLAGS_DLLOFF;
+
+	while (wait_idle--);
+
+#if (DDR_TYPE == 1)
+	*((volatile UINT32*)(PHY_REG_BASE + CTRL_DELAY * 4)) = 1;
+	printf("ddr1 phy init done!\n");
+#elif (DDR_TYPE ==2)
+	*((volatile UINT32*)(PHY_REG_BASE + 129 * 4)) = 0;
+	*((volatile UINT32*)(PHY_REG_BASE + WDELAY_SEL * 4)) = 3;
+	*((volatile UINT32*)(PHY_REG_BASE + DQOUT_ENABLE_LAT * 4)) = 1;
+	*((volatile UINT32*)(PHY_REG_BASE + 48 *4))  = 0xf;
+	*((volatile UINT32*)(PHY_REG_BASE + 20 *4))  = 0xf;
+	printf("ddr2 phy init done!\n");
+#else
+	*((volatile UINT32*)(PHY_REG_BASE + 128 *4))  = 0x0;
+	*((volatile UINT32*)(PHY_REG_BASE + RESET_DDR3 * 4)) = 1;
+
+	if (dll_off)
+		*((volatile UINT32*)(PHY_REG_BASE + WRITE_DATA_LAT * 4)) = 1;
+
+	*((volatile UINT32*)(PHY_REG_BASE + DDR3_USED * 4)) = 1;
+	*((volatile UINT32*)(PHY_REG_BASE + WDELAY_SEL * 4)) = 3;
+
+	if (!dll_off){
+		*((volatile UINT32*)(PHY_REG_BASE + PHY_RDLAT * 4)) = 7;
+		*((volatile UINT32*)(PHY_REG_BASE + CTRL_DELAY * 4)) =2;
+		*((volatile UINT32*)(PHY_REG_BASE + WRITE_ENABLE_LAT * 4)) =2;
+		*((volatile UINT32*)(PHY_REG_BASE + WRITE_DATA_LAT * 4)) = 3;
+		*((volatile UINT32*)(PHY_REG_BASE + DQOUT_ENABLE_LAT * 4)) = 3;
+	}else
+		*((volatile UINT32*)(PHY_REG_BASE + DQOUT_ENABLE_LAT * 4)) = 1;
+
+	*((volatile UINT32*)(PHY_REG_BASE + DATA_ODT_ENABLE_REG *4))  = 0xf;
+	*((volatile UINT32*)(PHY_REG_BASE + DATA_WRITE_ENABLE_REG *4))  = 0xf;
+	
+	serial_puts("ddr3 phy init done!\n");
+#endif
+}
+
+void config_dmc400(UINT16 flag, UINT32 para)
+{
+	int i, wait_idle;
+	UINT32 val, tmp;
+	volatile UINT32 *addr;
+	UINT16 __attribute__((unused)) dll_off, lpw, odt, ron;
+	UINT32 mem_width, col_bits, row_bits, bank_bits;
+
+	dll_off = flag & DDR_FLAGS_DLLOFF;
+	lpw = flag & DDR_FLAGS_LOWPWR;
+	odt = (flag & DDR_FLAGS_ODT_MASK) >> DDR_FLAGS_ODT_SHIFT;
+	ron = (flag & DDR_FLAGS_RON_MASK) >> DDR_FLAGS_RON_SHIFT;
+	mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;
+	bank_bits = (para & DDR_PARA_BANK_BITS_MASK) >> DDR_PARA_BANK_BITS_SHIFT;
+	row_bits = (para & DDR_PARA_ROW_BITS_MASK) >> DDR_PARA_ROW_BITS_SHIFT;
+	col_bits = (para & DDR_PARA_COL_BITS_MASK) >> DDR_PARA_COL_BITS_SHIFT;
+
+
+	wait_idle = 0x4e;
+	while (wait_idle--);
+
+	for (i=0; i<ARRAY_NUM(dmc_reg_cfg); i++) {
+		addr = (volatile UINT32*)(DMC_REG_BASE + dmc_reg_cfg[i].reg_offset);
+		if (dll_off)
+			val = dmc_reg_cfg[i].dll_off_val;
+		else
+			val = dmc_reg_cfg[i].dll_on_val;
+
+		*addr = val;
+		wait_idle = 0x5;
+		while (wait_idle--);
+	}
+
+#if (DDR_TYPE == 3)
+	//config low power control register
+	if (lpw) {
+		addr = (volatile UINT32*)(DMC_REG_BASE + LOWPWR_CTRL);//0x20
+		*addr = 0x48;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_ESR);//0x260
+		*addr = 0xa;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_XSR);//0x264
+		*addr = 0x200;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_SRCKD);//0x268
+		*addr = 0xa;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_CKSRD);//0x26C
+		*addr = 0xa;
+		wait_idle = 0x5;
+		while (wait_idle--);	
+	}
+#elif (DDR_TYPE == 2)
+	addr = (volatile UINT32*)(DMC_REG_BASE + LOWPWR_CTRL);//0x20
+	*addr = 0x38;
+	wait_idle = 0x5;
+	while (wait_idle--);
+#endif
+
+	//config format control register
+	addr = (volatile UINT32*)(DMC_REG_BASE + FORMAT_CTRL);
+	val = *addr;
+	val &= ~0xf;
+	if (mem_width == 2)
+		val |= 0x2; //for 32bit DDR
+	else if ((mem_width == 1) || (mem_width == 0))
+		val |= 0x1; //for 16bit & 8bit DDR
+	else
+		printf("unsupported DDR width: %lx\n", mem_width);
+	*addr = val;
+
+	printf("format ctrl value: %lx\n", val);
+
+	wait_idle = 0x1d;
+	while (wait_idle--);
+
+	//config address control register
+	addr = (volatile UINT32*)(DMC_REG_BASE + ADDR_CTRL);
+	if (mem_width == 2)
+		tmp = col_bits; //for 32bit
+	else if (mem_width == 1)
+		tmp = col_bits - 1; //for 16bit
+	else if (mem_width == 0)
+		tmp = col_bits - 2; //for 8bit
+	else {
+		printf("unsupported DDR width: %lx\n", mem_width);
+		tmp = col_bits;
+	}
+	val = (bank_bits << 16) | (row_bits << 8) | tmp;
+
+	*addr = val;
+
+	printf("address ctrl value: %lx\n", val);
+	wait_idle = 0x5;
+	while (wait_idle--);
+
+	//config decode control register
+	addr = (volatile UINT32*)(DMC_REG_BASE + DECODE_CTRL);
+	tmp = 12 - (8 + col_bits + mem_width);
+	if (tmp < 8)
+		val = tmp << 4;
+	else
+		printf("unsupported stripe decode: %lx\n", tmp);
+	*addr = val;
+
+	printf("decode ctrl value: %lx\n", val);
+	wait_idle = 0x6;
+	while (wait_idle--);
+
+	wait_idle = DF_DELAY;
+	while (wait_idle--);
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+	*addr = 0x0;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0;
+#elif (DDR_TYPE == 2)
+	val = 0;
+#else
+	//config MR2
+	if (dll_off)
+		val = 0x10020008;
+	else
+		val = 0x10020000;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x20000000;
+#elif (DDR_TYPE == 2)
+	val = 0x1000003f;
+#else
+	//config MR3
+	val = 0x10030000;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x30000000;
+#elif (DDR_TYPE == 2)
+	val = 0x1000ff0a;
+#else
+	//config MR1 ODT [9,6,2] RON [5,1] DLLOFF [0]
+	val = 0x10010000;
+	val |= (odt & 0x4)<<7 | (odt & 0x2)<<5 | (odt & 0x1)<<2;
+	val |= (ron & 0x2)<<4 | (ron & 0x1)<<1;
+	if (dll_off)
+		val |= 0x1;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x30000000;
+#elif (DDR_TYPE == 2)
+	val = 0x10008301;
+#else
+	//config MR0
+	val = 0x10000520;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x10000033;
+#elif (DDR_TYPE == 2)
+	val = 0x10000402;//0ld 0x10000102
+#else
+	val = 0x50000400;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x10020000;
+#elif (DDR_TYPE == 2)
+	val = 0x30000000;
+#else
+	val = 0x30000000;
+#endif
+	*addr = val;
+
+#if (DDR_TYPE == 2)
+/* zhangli for MCP */
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+	*addr = 0x10000103;
+	wait_idle = DF_DELAY + 0x9;
+	while (wait_idle--);
+#endif
+
+#if (DDR_TYPE == 2)
+	addr = (volatile UINT32*)(DMC_REG_BASE + MEMC_CMD);
+	val = 0x4;
+	*addr = val;
+#endif
+
+	//config ECC control
+	wait_idle = 0x6;
+	while (wait_idle--);
+	addr = (volatile UINT32*)(DMC_REG_BASE + ECC_CTRL);
+	val = 0x0;
+	*addr = val;
+	wait_idle = 0x8;
+	while (wait_idle--);
+
+	//config MEMC CMD
+	addr = (volatile UINT32*)(DMC_REG_BASE + MEMC_CMD);
+	val = 0x3;
+	*addr = val;
+
+	//READ MEMC STATUS
+	addr = (volatile UINT32*)(DMC_REG_BASE + MEMC_STATUS);
+	val = 0;
+	do {
+		val = *addr;
+		//printf("MEMC_STATUS value: %x\n", val);
+	} while (val != 3);
+}
+
+void axi_prio_init(void)
+{
+	*(volatile UINT32*)(0x20900100) = 0xaa0000aa;
+	*(volatile UINT32*)(0x21054100) = 0x00000008;
+	*(volatile UINT32*)(0x21054104) = 0x00000008;
+}
+
+void axi_outstandings_init(void)
+{
+	*(volatile UINT32*)(0x2105110C) = 0x00000060;
+	*(volatile UINT32*)(0x21051110) = 0x00000300;
+}
+
+int ddr_init(UINT16 flags, UINT32 para)
+{
+	UINT16 dll_off;
+	UINT32 mem_width;
+
+	axi_prio_init();
+	axi_outstandings_init();
+
+	dll_off = flags & DDR_FLAGS_DLLOFF;
+	mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;
+
+	switch (mem_width) {
+		case 0:
+			printf("8bit ");
+			break;
+		case 1:
+			printf("16bit ");
+			break;
+		case 2:
+			printf("32bit ");
+			break;
+	}
+	if (dll_off)
+		printf("dll-off Mode ...\n");
+	else
+		printf("dll-on Mode ...\n");
+
+	config_ddr_phy(flags);
+	config_dmc400(flags, para);
+	printf("dram init done ...\n");
+
+	return 0;
+}
+
diff --git a/board/rda/rda8820/ddr3.h b/board/rda/rda8820/ddr3.h
new file mode 100644
index 0000000000..7481954144
--- /dev/null
+++ b/board/rda/rda8820/ddr3.h
@@ -0,0 +1,50 @@
+#ifndef _SYS_DDR3_H_
+#define _SYS_DDR3_H_
+
+#include "clock_config.h"
+
+/*
+ * defination of ddr flags
+ */
+/* [Debug] DLL off mode, 0 is dll on mode */
+#define DDR_FLAGS_DLLOFF               0x8000
+/* [Debug] LowSpeed mode*/
+#define DDR_FLAGS_RESERVE              0x4000
+/* DDR LowPower mode */
+#define DDR_FLAGS_LOWPWR               0x2000
+/* ODT: 000--Null 001--60 010--120 011--40 100--20 101--30 */
+#define DDR_FLAGS_ODT(n)               (((n)<<0)&0x0007)
+#define DDR_FLAGS_ODT_SHIFT            0
+#define DDR_FLAGS_ODT_MASK             0x0007
+/* RON: 00--40 01--30 */
+#define DDR_FLAGS_RON(n)               (((n)<<3)&0x0018)
+#define DDR_FLAGS_RON_SHIFT            3
+#define DDR_FLAGS_RON_MASK             0x0018
+
+/*
+ * defination of ddr parameters
+ */
+#define DDR_PARA_CHIP_BITS(n)          (((n)<<0)&0x00000003)
+#define DDR_PARA_CHIP_BITS_SHIFT       0
+#define DDR_PARA_CHIP_BITS_MASK        0x00000003
+/* memory width 0--8bit 1--16bit 2--32bit */
+#define DDR_PARA_MEM_BITS(n)           (((n)<<2)&0x0000000c)
+#define DDR_PARA_MEM_BITS_SHIFT        2
+#define DDR_PARA_MEM_BITS_MASK         0x0000000c
+/* 2--4banks 3--8banks */
+#define DDR_PARA_BANK_BITS(n)          (((n)<<4)&0x000000f0)
+#define DDR_PARA_BANK_BITS_SHIFT       4
+#define DDR_PARA_BANK_BITS_MASK        0x000000f0
+/* 2--13rbs 3--14rbs 4--15rbs 5--16rbs */
+#define DDR_PARA_ROW_BITS(n)           (((n)<<8)&0x00000f00)
+#define DDR_PARA_ROW_BITS_SHIFT        8
+#define DDR_PARA_ROW_BITS_MASK         0x00000f00
+/* 0--8cbs 1--9cbs 2--10cbs 3--11cbs 4--12cbs */
+#define DDR_PARA_COL_BITS(n)           (((n)<<12)&0x0000f000)
+#define DDR_PARA_COL_BITS_SHIFT        12
+#define DDR_PARA_COL_BITS_MASK         0x0000f000
+
+int ddr_init(UINT16 flags, UINT32 para);
+
+#endif /* _SYS_DDR3_H_ */
+
diff --git a/board/rda/rda8820/ddr3_8810.c b/board/rda/rda8820/ddr3_8810.c
new file mode 100644
index 0000000000..d665019b8d
--- /dev/null
+++ b/board/rda/rda8820/ddr3_8810.c
@@ -0,0 +1,540 @@
+#include <common.h>
+#include <asm/arch/rda_iomap.h>
+
+#include "ddr3.h"
+#include "ddr3_init.h"
+#include "tgt_ap_clock_config.h"
+
+#pragma GCC push_options
+#pragma GCC optimize ("O0")
+
+#define DDR_TYPE _TGT_AP_DDR_TYPE
+
+#define DF_DELAY  (0x10000)
+
+#define DMC_REG_BASE RDA_DMC400_BASE
+#define PHY_REG_BASE RDA_DDRPHY_BASE
+
+#define  PHY_RDLAT          0
+#define  PHYWRDATA          1
+#define  STA                3
+#define  CLKSEL             4
+#define  PSSTART            5
+#define  PSDONE             6
+#define  LOCKED             6
+#define  CTRL_DELAY         7
+#define  RDELAY_SEL         8
+#define  WDELAY_SEL         9
+#define  PHY_RESET          10
+#define  RESET_DDR3         11
+#define  ODT_DELAY          12
+#define  DDR3_USED          13
+#define  WRITE_ENABLE_LAT   14
+#define  WRITE_DATA_LAT     15
+#define  DQOUT_ENABLE_LAT   16
+
+#define ARRAY_NUM(n) (sizeof(n))/(sizeof(n[0]))
+
+#if (DDR_TYPE == 1)
+static dmc_reg_t dmc_reg_cfg[] = {
+	{T_REFI,	0x186,		0x186},
+	{T_RFC,		0x230024,	0x230024},
+	{T_RFC,		0x540024,	0x540024},
+	{T_MRR,		0x2,		0x2},
+	{T_MRW,		0x5,		0x5},
+	{T_RCD,		0x8,		0x8},
+	{T_RAS,		0x11,		0x11},
+	{T_RP,		0x8,		0x8},
+	{T_RPALL,	0x9,		0x9},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0x4,		0x4},
+	{T_RTW,		0xb,		0xb},
+	{T_RTP,		0x6,		0x6},
+	{T_WR,		0xe,		0xe},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTW,		0x40000,	0x40000},
+	{RD_LATENCY,	0x6,		0x6},
+	{WR_LATENCY,	0x3,		0x3},
+	{T_RDDATA_EN,	0x3,		0x3},
+	{T_PHYWRLAT,	0x101,		0x101},
+	{T_PHYWRLAT,	0x101,		0x101},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0x80003,	0x80003},
+	{T_ESR,		0x6,		0x6},
+	{T_XSR,		0x1000058,	0x1000058},
+	{T_XSR,		0x580058,	0x580058},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{T_EP,		0x5,		0x5},
+	{RDLVL_CTRL,	0x1010,		0x1010},
+	{RDLVL_CTRL,	0x1110,		0x1110},
+	{RDLVL_CTRL,	0x11110,	0x11110},
+	{REFRESH_CTRL,	0x0,		0x0},
+	{REFRESH_CTRL,	0x0,		0x0},
+	{ECC_CTRL,	0x0,		0x0},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+};
+#elif (DDR_TYPE == 2)
+static dmc_reg_t dmc_reg_cfg[] = {
+	{T_REFI,	0x3f,		0x3f},
+	{T_RFC,		0x230024,	0x230024},
+	{T_RFC,		0x540024,	0x540024},
+	{T_MRR,		0x2,		0x2},
+	{T_MRW,		0x5,		0x5},
+	{T_RCD,		0x8,		0x8},
+	{T_RAS,		0x11,		0x11},
+	{T_RP,		0x8,		0x8},
+	{T_RPALL,	0x9,		0x9},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0x4,		0x4},
+	{T_RTW,		0xb,		0xb},
+	{T_RTP,		0x6,		0x6},
+	{T_WR,		0xe,		0xe},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTW,		0x40000,	0x40000},
+	{RD_LATENCY,	0x6,		0x6},
+	{WR_LATENCY,	0x3,		0x3},
+	{T_RDDATA_EN,	0x3,		0x3},
+	{T_PHYWRLAT,	0x101,		0x101},
+	{T_PHYWRLAT,	0x103,		0x103},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0x80003,	0x80003},
+	{T_ESR,		0x6,		0x6},
+	{T_XSR,		0x1000058,	0x1000058},
+	{T_XSR,		0x580058,	0x580058},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{T_EP,		0x5,		0x5},
+	{RDLVL_CTRL,	0x1010,		0x1010},
+	{RDLVL_CTRL,	0x1110,		0x1110},
+	{RDLVL_CTRL,	0x11110,	0x11110},
+	{REFRESH_CTRL,	0x1,		0x1},
+	{ECC_CTRL,	0x0,		0x0},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+};
+#elif (DDR_TYPE == 3)
+static dmc_reg_t dmc_reg_cfg[] = {
+	{T_REFI,	0x186,		0x3f},
+	{T_RFC,		0x23008c,	0x23008c},
+	{T_RFC,		0x8c008c,	0x8c008c},
+	{T_MRR,		0x4,		0x4},
+	{T_MRW,		0xc,		0xc},
+	{T_RCD,		0x6,		0x5},
+	{T_RAS,		0xf,		0xf},
+	{T_RP,		0x6,		0x5},
+	{T_RPALL,	0x6,		0x5},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0x6,		0x6},
+//	{T_RTW,		0x7,		0x6},
+	{T_RTW,		0x0e,		0x0c},// turn for now
+//	{T_RTW,		0x1f,		0x1f},//for low speed
+	{T_RTP,		0x4,		0x4},
+	{T_WR,		0xf,		0x10},
+	{T_WTR,		0x4000d,	0x4000d},
+	{T_WTR,		0x6000d,	0x6000f},
+//	{T_WTR,		0x6001f,	0x6001f},//for low speed
+	{T_WTW,		0x60000,	0x60000},
+	{RD_LATENCY,	0x5,		0x5},
+	{WR_LATENCY,	0x5,		0x5},
+	{T_RDDATA_EN,	0x8,		0x1},
+	{T_PHYWRLAT,	0x103,		0x103},
+	{T_PHYWRLAT,	0x103,		0x104},
+	{T_EP,		0x3,		0x3},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0xa0003,	0xa0003},
+	{T_ESR,		0x4,		0x4},
+	{T_XSR,		0x1000090,	0x1000090},
+	{T_XSR,		0x2000090,	0x2000090},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{ECC_CTRL,	0x0,		0x0},
+	{QOSX_CTRL7,	0x0f, 		0x0f},
+	{TURNAROUND_PRIO,0x1A, 		0x1A},
+	{HIT_PRIO,	0x1A, 		0x1A},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+};
+#else
+#error "Wrong DDR Type"
+#endif
+
+void config_ddr_phy(UINT16 flag)
+{
+	int wait_idle;
+	UINT16 dll_off;
+
+	wait_idle = DF_DELAY + 16;
+	dll_off = flag & DDR_FLAGS_DLLOFF;
+
+	while (wait_idle--);
+
+#if (DDR_TYPE == 1)
+	*((volatile UINT32*)(PHY_REG_BASE + CTRL_DELAY * 4)) = 1;
+	printf("ddr1 phy init done!\n");
+#elif (DDR_TYPE ==2)
+	*((volatile UINT32*)(PHY_REG_BASE + 129 * 4)) = 0;
+	*((volatile UINT32*)(PHY_REG_BASE + WDELAY_SEL * 4)) = 3;
+	*((volatile UINT32*)(PHY_REG_BASE + DQOUT_ENABLE_LAT * 4)) = 1;
+	*((volatile UINT32*)(PHY_REG_BASE + 48 *4))  = 0xf;
+	*((volatile UINT32*)(PHY_REG_BASE + 20 *4))  = 0xf;
+	printf("ddr2 phy init done!\n");
+#else
+	*((volatile UINT32*)(PHY_REG_BASE + RESET_DDR3 * 4)) = 1;
+	*((volatile UINT32*)(PHY_REG_BASE + WRITE_DATA_LAT * 4)) = 1;
+	*((volatile UINT32*)(PHY_REG_BASE + DDR3_USED * 4)) = 1;
+	if (!dll_off)
+	*((volatile UINT32*)(PHY_REG_BASE + RDELAY_SEL * 4)) = 2;
+	*((volatile UINT32*)(PHY_REG_BASE + WDELAY_SEL * 4)) = 3;
+	*((volatile UINT32*)(PHY_REG_BASE + DQOUT_ENABLE_LAT * 4)) = 1;
+	*((volatile UINT32*)(PHY_REG_BASE + 48 *4))  = (3<<2);
+	*((volatile UINT32*)(PHY_REG_BASE + 20 *4))  = (3<<2);
+	printf("ddr3 phy init done!\n");
+#endif
+}
+
+void config_dmc400(UINT16 flag, UINT32 para)
+{
+	int i, wait_idle;
+	UINT32 val, tmp;
+	volatile UINT32 *addr;
+	UINT16 dll_off, lpw, odt, ron;
+	UINT32 mem_width, col_bits, row_bits, bank_bits;
+
+	dll_off = flag & DDR_FLAGS_DLLOFF;
+	lpw = flag & DDR_FLAGS_LOWPWR;
+	odt = (flag & DDR_FLAGS_ODT_MASK) >> DDR_FLAGS_ODT_SHIFT;
+	ron = (flag & DDR_FLAGS_RON_MASK) >> DDR_FLAGS_RON_SHIFT;
+	mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;
+	bank_bits = (para & DDR_PARA_BANK_BITS_MASK) >> DDR_PARA_BANK_BITS_SHIFT;
+	row_bits = (para & DDR_PARA_ROW_BITS_MASK) >> DDR_PARA_ROW_BITS_SHIFT;
+	col_bits = (para & DDR_PARA_COL_BITS_MASK) >> DDR_PARA_COL_BITS_SHIFT;
+
+
+	wait_idle = 0x4e;
+	while (wait_idle--);
+
+	for (i=0; i<ARRAY_NUM(dmc_reg_cfg); i++) {
+		addr = (volatile UINT32*)(DMC_REG_BASE + dmc_reg_cfg[i].reg_offset);
+		if (dll_off)
+			val = dmc_reg_cfg[i].dll_off_val;
+		else
+			val = dmc_reg_cfg[i].dll_on_val;
+
+		*addr = val;
+		wait_idle = 0x5;
+		while (wait_idle--);
+	}
+
+#if (DDR_TYPE == 3)
+	//config low power control register
+	if (lpw) {
+		addr = (volatile UINT32*)(DMC_REG_BASE + LOWPWR_CTRL);//0x20
+		*addr = 0x48;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_ESR);//0x260
+		*addr = 0xa;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_XSR);//0x264
+		*addr = 0x200;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_SRCKD);//0x268
+		*addr = 0xa;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_CKSRD);//0x26C
+		*addr = 0xa;
+		wait_idle = 0x5;
+		while (wait_idle--);	
+	}
+#elif (DDR_TYPE == 2)
+	addr = (volatile UINT32*)(DMC_REG_BASE + LOWPWR_CTRL);//0x20
+	*addr = 0x38;
+	wait_idle = 0x5;
+	while (wait_idle--);
+#endif
+
+	//config format control register
+	addr = (volatile UINT32*)(DMC_REG_BASE + FORMAT_CTRL);
+#if (DDR_TYPE == 1)
+	val = 0x22000202;
+#elif (DDR_TYPE == 2)
+	val = 0x22000202;
+#else
+	val = *addr;
+	val &= ~0xf;
+	if (mem_width == 2)
+		val |= 0x2; //for 32bit DDR
+	else if ((mem_width == 1) || (mem_width == 0))
+		val |= 0x1; //for 16bit & 8bit DDR
+	else
+		printf("unsupported DDR width: %lx\n", mem_width);
+#endif
+	*addr = val;
+
+	printf("format ctrl value: %lx\n", val);
+
+	wait_idle = 0x1d;
+	while (wait_idle--);
+
+	//config address control register
+	addr = (volatile UINT32*)(DMC_REG_BASE + ADDR_CTRL);
+#if (DDR_TYPE == 1)
+	val = 0x20302;
+#elif (DDR_TYPE == 2)
+	val = 0x30200;
+#else
+	if (mem_width == 2)
+		tmp = col_bits; //for 32bit
+	else if (mem_width == 1)
+		tmp = col_bits - 1; //for 16bit
+	else if (mem_width == 0)
+		tmp = col_bits - 2; //for 8bit
+	else {
+		printf("unsupported DDR width: %lx\n", mem_width);
+		tmp = col_bits;
+	}
+
+	val = (bank_bits << 16) | (row_bits << 8) | tmp;
+#endif
+	*addr = val;
+
+	printf("address ctrl value: %lx\n", val);
+	wait_idle = 0x5;
+	while (wait_idle--);
+
+#if (DDR_TYPE == 2)
+	addr = (volatile UINT32*)(DMC_REG_BASE + ADDR_CTRL);
+
+	val = 0x30301;
+
+	*addr = val;
+
+	printf("address ctrl 2 value: %lx\n", val);
+	wait_idle = 0x5;
+	while (wait_idle--);
+#endif
+
+	//config decode control register
+	addr = (volatile UINT32*)(DMC_REG_BASE + DECODE_CTRL);
+#if (DDR_TYPE == 1)
+	val = 0x00;
+#elif (DDR_TYPE == 2)
+	val = 0x50;
+#else
+	tmp = 12 - (8 + col_bits + mem_width);
+	if (tmp < 8)
+		val = tmp << 4;
+	else
+		printf("unsupported stripe decode: %lx\n", tmp);
+#endif
+	*addr = val;
+	wait_idle = 0x6;
+	while (wait_idle--);
+
+#if (DDR_TYPE == 2)
+	addr = (volatile UINT32*)(DMC_REG_BASE + DECODE_CTRL);
+	val = 0x10;
+	*addr = val;
+	wait_idle = 0x6;
+	while (wait_idle--);
+#endif	
+
+	wait_idle = DF_DELAY;
+	while (wait_idle--);
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+	*addr = 0x0;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0;
+#elif (DDR_TYPE == 2)
+	val = 0;
+#else
+	//config MR2
+	if (dll_off)
+		val = 0x10020008;
+	else
+		val = 0x10020000;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x6;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x20000000;
+#elif (DDR_TYPE == 2)
+	val = 0x1000003f;
+#else
+	//config MR3
+	val = 0x10030000;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x30000000;
+#elif (DDR_TYPE == 2)
+	val = 0x1000ff0a;
+#else
+	//config MR1 ODT [9,6,2] RON [5,1] DLLOFF [0]
+	val = 0x10010000;
+	val |= (odt & 0x4)<<7 | (odt & 0x2)<<5 | (odt & 0x1)<<2;
+	val |= (ron & 0x2)<<4 | (ron & 0x1)<<1;
+	if (dll_off)
+		val |= 0x1;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x30000000;
+#elif (DDR_TYPE == 2)
+	val = 0x10008301;
+#else
+	//config MR0
+	val = 0x10000520;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x6;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x10000033;
+#elif (DDR_TYPE == 2)
+	val = 0x10000402;//0ld 0x10000102
+#else
+	val = 0x50000400;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x6;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x10020000;
+#elif (DDR_TYPE == 2)
+	val = 0x30000000;
+#else
+	val = 0x30000000;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x9;
+	while (wait_idle--);
+
+#if (DDR_TYPE == 2)
+/* zhangli for MCP */
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+	*addr = 0x10000103;
+	wait_idle = DF_DELAY + 0x9;
+	while (wait_idle--);
+#endif
+
+#if (DDR_TYPE == 2)
+	addr = (volatile UINT32*)(DMC_REG_BASE + MEMC_CMD);
+	val = 0x4;
+	*addr = val;
+	wait_idle = 0x5;
+	while (wait_idle--);
+#endif
+
+	//config ECC control
+	addr = (volatile UINT32*)(DMC_REG_BASE + ECC_CTRL);
+	val = 0x0;
+	*addr = val;
+	wait_idle = 0x4f;
+	while (wait_idle--);
+
+	//config MEMC CMD
+	addr = (volatile UINT32*)(DMC_REG_BASE + MEMC_CMD);
+	val = 0x3;
+	*addr = val;
+	wait_idle = 0x8;
+	while (wait_idle--);
+
+	//READ MEMC STATUS
+	addr = (volatile UINT32*)(DMC_REG_BASE + MEMC_STATUS);
+	val = 0;
+	do {
+		val = *addr;
+		//printf("MEMC_STATUS value: %x\n", val);
+	} while (val != 3);
+}
+
+void axi_prio_init(void)
+{
+	*(volatile UINT32*)(0x20900100) = 0xaa0000aa;
+	*(volatile UINT32*)(0x21054100) = 0x00000008;
+	*(volatile UINT32*)(0x21054104) = 0x00000008;
+}
+
+void axi_outstandings_init(void)
+{
+	*(volatile UINT32*)(0x2105110C) = 0x00000060;
+	*(volatile UINT32*)(0x21051110) = 0x00000300;
+}
+
+int ddr_init(UINT16 flags, UINT32 para)
+{
+	UINT16 dll_off;
+	UINT32 mem_width;
+
+	axi_prio_init();
+	axi_outstandings_init();
+
+	dll_off = flags & DDR_FLAGS_DLLOFF;
+	mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;
+
+	switch (mem_width) {
+		case 0:
+			printf("8bit ");
+			break;
+		case 1:
+			printf("16bit ");
+			break;
+		case 2:
+			printf("32bit ");
+			break;
+	}
+	if (dll_off)
+		printf("dll-off Mode ...\n");
+	else
+		printf("dll-on Mode ...\n");
+
+	config_ddr_phy(flags);
+	config_dmc400(flags, para);
+	printf("dram init done ...\n");
+
+	return 0;
+}
+
diff --git a/board/rda/rda8820/ddr3_8810e_16bit.c b/board/rda/rda8820/ddr3_8810e_16bit.c
new file mode 100644
index 0000000000..2469e0c75e
--- /dev/null
+++ b/board/rda/rda8820/ddr3_8810e_16bit.c
@@ -0,0 +1,388 @@
+#include <common.h>

+#include <asm/arch/rda_iomap.h>

+

+#include "ddr3.h"

+#include "tgt_ap_clock_config.h"

+

+#define DDR_TYPE	3

+#define DF_DELAY	(0x100000)

+

+#define DMC_REG_BASE RDA_DMC400_BASE

+#define PHY_REG_BASE RDA_DDRPHY_BASE

+

+#define  PHY_RDLAT		0

+#define  PHYWRDATA		1

+#define  STA			3

+#define  CLKSEL			4

+#define  PSSTART		5

+#define  PSDONE			6

+#define  LOCKED			6

+#define  CTRL_DELAY		7

+#define  RDELAY_SEL		8

+#define  WDELAY_SEL		9

+#define  PHY_RESET		10

+#define  RESET_DDR3		11

+#define  ODT_DELAY		12

+#define  DDR3_USED		13

+#define  WRITE_ENABLE_LAT	14

+#define  WRITE_DATA_LAT		15

+#define  DQOUT_ENABLE_LAT	16

+#define  DMC_READY          128

+

+#define ARRAY_NUM(n) (sizeof(n))/(sizeof(n[0]))

+

+#define DMCREG_BADDR DMC_REG_BASE

+#define PHY_BADDR PHY_REG_BASE

+

+void DDR_CONFIG_DELAY(int delay)

+{

+   int i;

+   i = delay;

+   while(i--);

+}

+//////////////////////////////////////////////////////////////////////

+void config_ddr_phy(UINT16 flag)

+{

+	int cnt;

+    volatile int * addr;

+    cnt = 16;

+    while(cnt--);

+        

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (PHY_BADDR + DMC_READY*4);

+    *addr = 0;    

+    

+    addr = (int *) (PHY_BADDR + RESET_DDR3*4);

+    *addr = 1;

+

+    addr = (int *) (PHY_BADDR + WRITE_DATA_LAT*4);

+    *addr = 1;    

+    

+    addr = (int *) (PHY_BADDR + DDR3_USED*4);

+    *addr = 1;    

+   

+    addr = (int *) (PHY_BADDR + WDELAY_SEL*4);

+    *addr = 3;    

+    

+    addr = (int *) (PHY_BADDR + DQOUT_ENABLE_LAT*4);

+    *addr = 1;

+	serial_puts("ddr3 phy init done!\n");  

+}

+///////////////////////////////////////////////////////////////////

+void config_dmc400(UINT16 flag, UINT32 para)

+{

+	int wait_idle;

+	volatile int * addr;

+ wait_idle = 0x4e;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x200);

+*addr = 0x3f;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x204);

+*addr = 0x23008c;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x204);

+*addr = 0x8c008c;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x208);

+*addr = 0x4;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x20c);

+*addr = 0xc;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x218);

+*addr = 0x6;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x21c);

+*addr = 0xf;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x220);

+*addr = 0x6;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x224);

+*addr = 0x5;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x228);

+*addr = 0x4;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x22c);

+*addr = 0x14;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x234);

+*addr = 0x6;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x238);

+*addr = 0x6;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x23c);

+*addr = 0x4;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x244);

+*addr = 0x10;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x248);

+*addr = 0x4000d;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x248);

+*addr = 0x6000f;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x24c);

+*addr = 0x60000;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x230);

+*addr = 0x5;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x240);

+*addr = 0x5;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x300);

+*addr = 0x2;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x304);

+*addr = 0x105;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x304);

+*addr = 0x105;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x258);

+*addr = 0x3;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x25c);

+*addr = 0x20003;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x25c);

+*addr = 0xa0003;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x260);

+*addr = 0x4;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x264);

+*addr = 0x1000090;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x264);

+*addr = 0x2000090;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x268);

+*addr = 0x5;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x26c);

+*addr = 0x5;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x250);

+*addr = 0x5;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x254);

+*addr = 0x5;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x148);

+*addr = 0x0;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x10);

+*addr = 0x30200;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x10);

+*addr = 0x30200;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x10);

+*addr = 0x30200;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x18);

+*addr = 0x22000201;

+

+ wait_idle = 0x1d;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x10);

+*addr = 0x30200;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x10);

+*addr = 0x30401;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x14);

+*addr = 0x50;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x14);

+*addr = 0x10;

+

+ wait_idle = 0x6;

+ while(wait_idle--);

+DDR_CONFIG_DELAY(DF_DELAY); 

+addr = (int *) (DMCREG_BADDR + 0x108);

+*addr = 0x0;

+

+ wait_idle = 0x10;

+ while(wait_idle--);

+DDR_CONFIG_DELAY(DF_DELAY); 

+addr = (int *) (DMCREG_BADDR + 0x108);

+*addr = 0x10020008;

+

+ wait_idle = 0x10;

+ while(wait_idle--);

+DDR_CONFIG_DELAY(DF_DELAY); 

+addr = (int *) (DMCREG_BADDR + 0x108);

+*addr = 0x10030000;

+

+ wait_idle = 0x10;

+ while(wait_idle--);

+DDR_CONFIG_DELAY(DF_DELAY); 

+addr = (int *) (DMCREG_BADDR + 0x108);

+*addr = 0x10010001;

+

+ wait_idle = 0x10;

+ while(wait_idle--);

+DDR_CONFIG_DELAY(DF_DELAY); 

+addr = (int *) (DMCREG_BADDR + 0x108);

+*addr = 0x10000520;

+

+ wait_idle = 0x10;

+ while(wait_idle--);

+DDR_CONFIG_DELAY(DF_DELAY); 

+addr = (int *) (DMCREG_BADDR + 0x108);

+*addr = 0x50000400;

+

+ wait_idle = 0x10;

+ while(wait_idle--);

+DDR_CONFIG_DELAY(DF_DELAY); 

+addr = (int *) (DMCREG_BADDR + 0x108);

+*addr = 0x30000000;

+

+ wait_idle = 0x6;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x148);

+*addr = 0x0;

+

+ wait_idle = 0x8;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x8);

+*addr = 0x3;

+

+addr = (int * ) (DMCREG_BADDR + 0x0);

+wait_idle = 0;

+while ( wait_idle != 3)

+wait_idle = *addr;

+serial_puts("ddr3 dmc400 init done!\n");

+}

+

+///////////////////////////////////////////////////////////////////

+void axi_prio_init(void)

+{

+	*(volatile UINT32*)(0x20900100) = 0xaa0000aa;

+	*(volatile UINT32*)(0x21054100) = 0x00000008;

+	*(volatile UINT32*)(0x21054104) = 0x00000008;

+}

+

+int ddr_init(UINT16 flags, UINT32 para)

+{

+	UINT16 dll_off;

+	UINT32 mem_width;

+

+	axi_prio_init();

+

+	dll_off = flags & DDR_FLAGS_DLLOFF;

+	mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;

+

+	switch (mem_width) {

+		case 0:

+			serial_puts("8bit ");

+			break;

+		case 1:

+			serial_puts("16bit ");

+			break;

+		case 2:

+			serial_puts("32bit ");

+			break;

+	}

+	if (dll_off)

+		serial_puts("dll-off Mode ...\n");

+	else

+		serial_puts("dll-on Mode ...\n");

+

+	config_ddr_phy(flags);

+	config_dmc400(flags, para);

+	//serial_puts("dram");

+	//print_u32(DDR_TYPE);

+	//serial_puts(" init done ...\n");

+	printf("dram%d init done ...\n", DDR_TYPE);

+

+	return 0;

+}

+

diff --git a/board/rda/rda8820/ddr3_8810e_32bit.c b/board/rda/rda8820/ddr3_8810e_32bit.c
new file mode 100644
index 0000000000..6cdef162f6
--- /dev/null
+++ b/board/rda/rda8820/ddr3_8810e_32bit.c
@@ -0,0 +1,410 @@
+#include <common.h>

+#include <asm/arch/rda_iomap.h>

+

+#include "ddr3.h"

+#include "tgt_ap_clock_config.h"

+

+#define DDR_TYPE	3

+#define DF_DELAY	(0x100000)

+

+#define DMC_REG_BASE RDA_DMC400_BASE

+#define PHY_REG_BASE RDA_DDRPHY_BASE

+

+#define  PHY_RDLAT		0

+#define  PHYWRDATA		1

+#define  STA			3

+#define  CLKSEL			4

+#define  PSSTART		5

+#define  PSDONE			6

+#define  LOCKED			6

+#define  CTRL_DELAY		7

+#define  RDELAY_SEL		8

+#define  WDELAY_SEL		9

+#define  PHY_RESET		10

+#define  RESET_DDR3		11

+#define  ODT_DELAY		12

+#define  DDR3_USED		13

+#define  WRITE_ENABLE_LAT	14

+#define  WRITE_DATA_LAT		15

+#define  DQOUT_ENABLE_LAT	16

+#define  DMC_READY          128

+#define  DATA_ODT_ENABLE_REG    20

+#define  DATA_WRITE_ENABLE_REG  48   

+

+#define ARRAY_NUM(n) (sizeof(n))/(sizeof(n[0]))

+

+#define DMCREG_BADDR DMC_REG_BASE

+#define PHY_BADDR PHY_REG_BASE

+

+void DDR_CONFIG_DELAY(int delay)

+{

+    int i;

+    i = delay;

+    while(i--);

+}

+

+void config_ddr_phy(UINT16 flag)

+{

+    int cnt;

+    volatile int * addr;

+    cnt = 16;

+    while(cnt--);

+        

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (PHY_BADDR + DMC_READY*4);

+    *addr = 0;    

+    

+    addr = (int *) (PHY_BADDR + RESET_DDR3*4);

+    *addr = 1;

+

+    addr = (int *) (PHY_BADDR + WRITE_DATA_LAT*4);

+    *addr = 1;    

+    

+    addr = (int *) (PHY_BADDR + DDR3_USED*4);

+    *addr = 1;    

+   

+    addr = (int *) (PHY_BADDR + WDELAY_SEL*4);

+    *addr = 3;    

+    

+    addr = (int *) (PHY_BADDR + DQOUT_ENABLE_LAT*4);

+    *addr = 1;

+

+    addr = (int *) (PHY_BADDR + DATA_ODT_ENABLE_REG*4);

+    *addr = 0xf;

+    

+    addr = (int *) (PHY_BADDR + DATA_WRITE_ENABLE_REG*4);

+    *addr = 0xf;  

+          	

+    serial_puts("ddr3 phy init done!\n");  

+}

+

+#define DMC_WAIT_IDLE     1

+

+void config_dmc400(UINT16 flag, UINT32 para)

+{

+    int wait_idle;

+    volatile int *addr;

+    volatile int temp;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x200);

+    *addr = 0x3f;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x204);

+    *addr = 0x23008c;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x204);

+    *addr = 0x8c008c;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x208);

+    *addr = 0x4;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x20c);

+    *addr = 0xc;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x218);

+    *addr = 0x6;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x21c);

+    *addr = 0xf;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x220);

+    *addr = 0x6;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x224);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x228);

+    *addr = 0x4;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x22c);

+    *addr = 0x14;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x234);

+    *addr = 0x6;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x238);

+    *addr = 0x6;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x23c);

+    *addr = 0x4;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x244);

+    *addr = 0x10;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x248);

+    *addr = 0x4000d;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x248);

+    *addr = 0x6000f;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x24c);

+    *addr = 0x60000;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x230);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x240);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x300);

+    *addr = 0x2;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x304);

+    *addr = 0x105;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x304);

+    *addr = 0x105;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x258);

+    *addr = 0x3;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x25c);

+    *addr = 0x20003;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x25c);

+    *addr = 0xa0003;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x260);

+    *addr = 0x4;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x264);

+    *addr = 0x1000090;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x264);

+    *addr = 0x2000090;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x268);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x26c);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x250);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x254);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x148);

+    *addr = 0x0;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    *addr = 0x30200;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    *addr = 0x30200;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    *addr = 0x30200;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x18);

+    //*addr = 0x22000201;

+    *addr = 0x22000202;

+

+    wait_idle = DMC_WAIT_IDLE * 0x1d;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    *addr = 0x30200;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    //*addr = 0x30401;

+    *addr = 0x30302;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x14);

+    *addr = 0x50;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x14);

+    //*addr = 0x10;

+    *addr = 0x00;

+

+    wait_idle = DMC_WAIT_IDLE * 0x6;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x0;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x10020008;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x10030000;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x10010001;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x10000520;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x50000400;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x30000000;

+

+    wait_idle = DMC_WAIT_IDLE * 0x6;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x148);

+    *addr = 0x0;

+

+    wait_idle = DMC_WAIT_IDLE * 0x8;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x8);

+    *addr = 0x3;

+

+    addr = (int * ) (DMCREG_BADDR + 0x0);

+    temp = 0;

+    while (temp != 3)

+        temp = *addr;

+

+    serial_puts("ddr3 dmc400 init done!\n");

+}

+

+void axi_prio_init(void)

+{

+    *(volatile UINT32*)(0x20900100) = 0xaa0000aa;

+    *(volatile UINT32*)(0x21054100) = 0x00000008;

+    *(volatile UINT32*)(0x21054104) = 0x00000008;

+}

+

+void axi_outstandings_init(void)

+{

+    *(volatile UINT32*)(0x2105110C) = 0x00000060;

+    *(volatile UINT32*)(0x21051110) = 0x00000300;

+}

+

+int ddr_init(UINT16 flags, UINT32 para)

+{

+    UINT16 dll_off;

+    UINT32 mem_width;

+

+    axi_prio_init();

+    axi_outstandings_init();

+

+    dll_off = flags & DDR_FLAGS_DLLOFF;

+    mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;

+

+    switch (mem_width) {

+    case 0:

+        serial_puts("8bit ");

+        break;

+    case 1:

+        serial_puts("16bit ");

+        break;

+    case 2:

+        serial_puts("32bit ");

+        break;

+    }

+    if (dll_off)

+        serial_puts("dll-off Mode ...\n");

+    else

+        serial_puts("dll-on Mode ...\n");

+

+    config_ddr_phy(flags);

+    config_dmc400(flags, para);

+    //serial_puts("dram ");

+    //print_u32(DDR_TYPE);

+    //serial_puts(" init done ...\n");

+    printf("ddr%d init done\n");

+

+    return 0;

+}

diff --git a/board/rda/rda8820/ddr3_init.h b/board/rda/rda8820/ddr3_init.h
new file mode 100644
index 0000000000..402375d269
--- /dev/null
+++ b/board/rda/rda8820/ddr3_init.h
@@ -0,0 +1,101 @@
+#ifndef _SYS_RAM_INIT_H_
+#define _SYS_RAM_INIT_H_
+
+#define MEMC_STATUS			0x000
+#define MEMC_CONFIG			0x004
+#define MEMC_CMD			0x008
+#define ADDR_CTRL			0x010
+#define DECODE_CTRL			0x014
+#define FORMAT_CTRL			0x018
+#define LOWPWR_CTRL			0x020
+#define TURNAROUND_PRIO			0x030
+#define HIT_PRIO			0x034
+//QOS0~QOS15:038~078
+#define QOSX_CTRL			0x038
+#define QOSX_CTRL7			0x058
+#define QOSX_CTRL15			0x078
+#define TIMEOUT_CTRL			0x07C
+#define QUEUE_CTRL			0x080
+#define WR_PRIO_CTRL			0x088
+#define WR_PRIO_CTRL2			0x08C
+#define RD_PRIO_CTRL			0x090
+#define RD_PRIO_CTRL2			0x094
+#define ACCESS_ADDR_MATCH		0x098
+#define ACCESS_ADDR_MATCH_63_32		0x09C
+#define ACCESS_ADDR_MASK		0x0A0
+#define ACCESS_ADDR_MASK_63_32		0x0A4
+
+#define CHANNEL_STATUS			0x100
+#define DIRECT_CMD			0x108
+#define MR_DATA				0x110
+#define REFRESH_CTRL			0x120
+#define INTR_CTRL			0x128
+#define INTR_CLR			0x130
+#define INTR_STATUS			0x138
+#define INTR_INFO			0x140
+#define ECC_CTRL			0x148
+
+#define T_REFI				0x200
+#define T_RFC				0x204
+#define T_MRR				0x208
+#define T_MRW				0x20C
+#define T_RCD				0x218
+#define T_RAS				0x21C
+#define T_RP				0x220
+#define T_RPALL				0x224
+#define T_RRD				0x228
+#define T_FAW				0x22C
+#define RD_LATENCY			0x230
+#define T_RTR				0x234
+#define T_RTW				0x238
+#define T_RTP				0x23C
+#define WR_LATENCY			0x240
+#define T_WR				0x244
+#define T_WTR				0x248
+#define T_WTW				0x24C
+#define T_ECKD				0x250
+#define T_XCKD				0x254
+#define T_EP				0x258
+#define T_XP				0x25C
+#define T_ESR				0x260
+#define T_XSR				0x264
+#define T_SRCKD				0x268
+#define T_CKSRD				0x26C
+
+#define T_RDDATA_EN			0x300
+#define T_PHYWRLAT			0x304
+#define RDLVL_CTRL			0x308
+#define RDLVL_DIRECT			0x310
+#define T_RDLVL_EN			0x318
+#define T_RDLVL_RR			0x31C
+#define WRLVL_CTRL			0x328
+#define WRLVL_DIRECT			0x330
+#define T_WRLVL_EN			0x338
+#define T_WRLVL_WW			0x33C
+
+#define PHY_PWR_CTRL			0x348
+#define PHY_UPD_CTRL			0x350
+
+#define USER_STATUS			0x400
+#define USER_CONFIG0			0x404
+#define USER_CONFIG1			0x408
+
+#define INTEG_CFG			0xE00
+#define INTEG_OUTPUTS			0xE08
+
+#define PERIPH_ID_0			0xFE0
+#define PERIPH_ID_1			0xFE4
+#define PERIPH_ID_2			0xFE8
+#define PERIPH_ID_3			0xFEC
+#define COMPONENT_ID_0			0xFF0
+#define COMPONENT_ID_1			0xFF4
+#define COMPONENT_ID_2			0xFF8
+#define COMPONENT_ID_3			0xFFC
+
+typedef struct {
+	UINT32 reg_offset;
+	UINT32 dll_on_val;
+	UINT32 dll_off_val;
+} dmc_reg_t;
+
+#endif /* _SYS_RAM_INIT_H_ */
diff --git a/board/rda/rda8820/ddr3_zhangli_32bit_dlloff.c b/board/rda/rda8820/ddr3_zhangli_32bit_dlloff.c
new file mode 100644
index 0000000000..aeabca6ba2
--- /dev/null
+++ b/board/rda/rda8820/ddr3_zhangli_32bit_dlloff.c
@@ -0,0 +1,400 @@
+#include <common.h>

+#include <asm/arch/rda_iomap.h>

+

+#include "ddr3.h"

+

+#define DDR_TYPE	3

+#define DF_DELAY	(0x100000)

+

+#define DMC_REG_BASE RDA_DMC400_BASE

+#define PHY_REG_BASE RDA_DDRPHY_BASE

+

+#define  PHY_RDLAT		0

+#define  PHYWRDATA		1

+#define  STA			3

+#define  CLKSEL			4

+#define  PSSTART		5

+#define  PSDONE			6

+#define  LOCKED			6

+#define  CTRL_DELAY		7

+#define  RDELAY_SEL		8

+#define  WDELAY_SEL		9

+#define  PHY_RESET		10

+#define  RESET_DDR3		11

+#define  ODT_DELAY		12

+#define  DDR3_USED		13

+#define  WRITE_ENABLE_LAT	14

+#define  WRITE_DATA_LAT		15

+#define  DQOUT_ENABLE_LAT	16

+#define  DMC_READY          128

+#define  DATA_ODT_ENABLE_REG    20

+#define  DATA_WRITE_ENABLE_REG  48   

+

+#define ARRAY_NUM(n) (sizeof(n))/(sizeof(n[0]))

+

+#define DMCREG_BADDR DMC_REG_BASE

+#define PHY_BADDR PHY_REG_BASE

+

+void DDR_CONFIG_DELAY(int delay)

+{

+    int i;

+    i = delay;

+    while(i--);

+}

+

+void config_ddr_phy(UINT16 flag)

+{

+    int cnt;

+    volatile int * addr;

+    cnt = 16;

+    while(cnt--);

+        

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (PHY_BADDR + DMC_READY*4);

+    *addr = 0;    

+    

+    addr = (int *) (PHY_BADDR + RESET_DDR3*4);

+    *addr = 1;

+

+    addr = (int *) (PHY_BADDR + WRITE_DATA_LAT*4);

+    *addr = 1;    

+    

+    addr = (int *) (PHY_BADDR + DDR3_USED*4);

+    *addr = 1;    

+   

+    addr = (int *) (PHY_BADDR + WDELAY_SEL*4);

+    *addr = 3;    

+    

+    addr = (int *) (PHY_BADDR + DQOUT_ENABLE_LAT*4);

+    *addr = 1;

+

+    addr = (int *) (PHY_BADDR + DATA_ODT_ENABLE_REG*4);

+    *addr = 0xf;

+    

+    addr = (int *) (PHY_BADDR + DATA_WRITE_ENABLE_REG*4);

+    *addr = 0xf;  

+          	

+    printf("ddr3 phy init done!\n");  

+}

+

+#define DMC_WAIT_IDLE     1

+

+void config_dmc400(UINT16 flag, UINT32 para)

+{

+    int wait_idle;

+    volatile int *addr;

+    volatile int temp;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x200);

+    *addr = 0x3f;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x204);

+    *addr = 0x23008c;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x204);

+    *addr = 0x8c008c;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x208);

+    *addr = 0x4;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x20c);

+    *addr = 0xc;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x218);

+    *addr = 0x6;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x21c);

+    *addr = 0xf;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x220);

+    *addr = 0x6;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x224);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x228);

+    *addr = 0x4;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x22c);

+    *addr = 0x14;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x234);

+    *addr = 0x6;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x238);

+    *addr = 0x6;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x23c);

+    *addr = 0x4;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x244);

+    *addr = 0x10;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x248);

+    *addr = 0x4000d;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x248);

+    *addr = 0x6000f;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x24c);

+    *addr = 0x60000;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x230);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x240);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x300);

+    *addr = 0x2;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x304);

+    *addr = 0x105;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x304);

+    *addr = 0x105;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x258);

+    *addr = 0x3;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x25c);

+    *addr = 0x20003;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x25c);

+    *addr = 0xa0003;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x260);

+    *addr = 0x4;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x264);

+    *addr = 0x1000090;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x264);

+    *addr = 0x2000090;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x268);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x26c);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x250);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x254);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x148);

+    *addr = 0x0;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    *addr = 0x30200;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    *addr = 0x30200;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    *addr = 0x30200;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x18);

+    //*addr = 0x22000201;

+    *addr = 0x22000202;

+

+    wait_idle = DMC_WAIT_IDLE * 0x1d;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    *addr = 0x30200;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    //*addr = 0x30401;

+    *addr = 0x30302;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x14);

+    *addr = 0x50;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x14);

+    //*addr = 0x10;

+    *addr = 0x00;

+

+    wait_idle = DMC_WAIT_IDLE * 0x6;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x0;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x10020008;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x10030000;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x10010001;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x10000520;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x50000400;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x30000000;

+

+    wait_idle = DMC_WAIT_IDLE * 0x6;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x148);

+    *addr = 0x0;

+

+    wait_idle = DMC_WAIT_IDLE * 0x8;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x8);

+    *addr = 0x3;

+

+    addr = (int * ) (DMCREG_BADDR + 0x0);

+    temp = 0;

+    while (temp != 3)

+        temp = *addr;

+

+    printf("ddr3 dmc400 init done!\n");

+}

+

+void axi_prio_init(void)

+{

+	*(volatile UINT32*)(0x20900100) = 0xaa0000aa;

+	*(volatile UINT32*)(0x21054100) = 0x00000008;

+	*(volatile UINT32*)(0x21054104) = 0x00000008;

+}

+

+int ddr_init(UINT16 flags, UINT32 para)

+{

+    UINT16 dll_off;

+    UINT32 mem_width;

+

+    axi_prio_init();

+

+    dll_off = flags & DDR_FLAGS_DLLOFF;

+    mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;

+

+    switch (mem_width) {

+    case 0:

+        printf("8bit ");

+        break;

+    case 1:

+        printf("16bit ");

+        break;

+    case 2:

+        printf("32bit ");

+        break;

+    }

+    if (dll_off)

+        printf("dll-off Mode ...\n");

+    else

+        printf("dll-on Mode ...\n");

+

+    config_ddr_phy(flags);

+    config_dmc400(flags, para);

+	printf("dram%x init done ...\n", DDR_TYPE);

+

+    return 0;

+}

+

diff --git a/board/rda/rda8820/debug.h b/board/rda/rda8820/debug.h
new file mode 100644
index 0000000000..1d4f03bedb
--- /dev/null
+++ b/board/rda/rda8820/debug.h
@@ -0,0 +1,9 @@
+#ifndef _DEBUG_H_
+#define _DEBUG_H_
+
+void print_u8(u8 ch);
+void print_u16(u16 data);
+void print_u32(u32 data);
+void dump_buf(u8 *buf, u32 size);
+
+#endif /* _DEBUG_H_ */
diff --git a/board/rda/rda8820/hal_config.c b/board/rda/rda8820/hal_config.c
new file mode 100644
index 0000000000..c52d21d0d2
--- /dev/null
+++ b/board/rda/rda8820/hal_config.c
@@ -0,0 +1,1166 @@
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//            Copyright (C) 2013, RDA Microeletronics.                        //
+//                            All Rights Reserved                             //
+//                                                                            //
+//      This source code is the property of RDA Microeletronics and is        //
+//      confidential.  Any  modification, distribution,  reproduction or      //
+//      exploitation  of  any content of this file is totally forbidden,      //
+//      except  with the  written permission  of  RDA Microeletronics.        //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//  $HeadURL: http://svn.rdamicro.com/svn/developing1/Sources/chip/branches/8810/hal/8810/src/hal_config.c $ //
+//    $Author: huazeng $                                                        //
+//    $Date: 2013-08-31 17:48:58 +0800 (Sat, 31 Aug 2013) $                     //
+//    $Revision: 21005 $                                                          //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+/// @file hal_config.c
+/// Implementation of HAL initialization related with the particular instance
+/// of the IP.
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+
+/* uboot */
+#include <common.h>
+
+/* common */
+#include <asm/arch/rda_iomap.h>
+#include <asm/arch/hwcfg.h>
+#include <asm/arch/chip_id.h>
+#include <asm/arch/cs_types.h>
+#include <asm/arch/global_macros.h>
+#include <asm/arch/reg_gpio.h>
+
+/* device */
+#include "hal_sys.h"
+#include "halp_sys.h"
+#include "halp_gpio.h"
+#include "bootp_mode.h"
+#include "hal_config.h"
+#include "hal_ap_gpio.h"
+#include "hal_ap_config.h"
+#include <asm/arch/reg_cfg_regs.h>
+
+/* target */
+#include "tgt_board_cfg.h"
+#include "tgt_ap_gpio_setting.h"
+#define HAL_ASSERT(cond, fmt, ...) \
+	if(!(cond)) { \
+		hal_assert(fmt, ##__VA_ARGS__); \
+		g_halConfigError = TRUE; \
+	}
+
+//// =============================================================================
+////  GLOBAL VARIABLES
+//// =============================================================================
+PRIVATE CONST UINT8 g_halCfgSimOrder[] = { TGT_SIM_ORDER };
+PRIVATE HAL_CFG_CONFIG_T hal_cfg = TGT_HAL_CONFIG;
+PRIVATE UINT32 g_bootBootMode = 0;
+PRIVATE BOOL g_halConfigError = FALSE;
+
+
+// =============================================================================
+//  FUNCTIONS
+// =============================================================================
+// HAL_ASSERT
+PRIVATE VOID hal_assert(const char *fmt, ...)
+{
+	va_list args;
+	puts("\n#-------Board Mux config found error-------#\n");
+	va_start(args, fmt);
+	vprintf(fmt, args);
+	putc('\n');
+	puts("--------------------------------------------\n\n");
+	va_end(args);
+}
+
+// =============================================================================
+// hal_BoardSimUsed
+// -----------------------------------------------------------------------------
+/// Check whether a SIM card interface is used.
+// ============================================================================
+PRIVATE BOOL hal_BoardSimUsed(UINT32 simId)
+{
+	UINT32 i = 0;
+    //for (UINT32 i=0; i<ARRAY_SIZE(g_halCfgSimOrder) && i<NUMBER_OF_SIM; i++)
+    for (i=0; i<ARRAY_SIZE(g_halCfgSimOrder) && i<NUMBER_OF_SIM; i++)
+    {
+        if (g_halCfgSimOrder[i] == simId)
+        {
+            return TRUE;
+        }
+    }
+
+    return FALSE;
+}
+
+#if 0
+// =============================================================================
+// hal_BoardConfigClk32k
+// -----------------------------------------------------------------------------
+/// Configure CLK_32K output.
+/// @param enable TRUE to configure, and FALSE to disable.
+// ============================================================================
+PROTECTED VOID hal_BoardConfigClk32k(BOOL enable)
+{
+    HAL_ASSERT(g_halCfg->useClk32k == TRUE, "32K clock is not configured");
+
+    if (enable)
+    {
+        // Setup the pin as 32K clock output
+        hwp_configRegs->Alt_mux_select =
+            (hwp_configRegs->Alt_mux_select & ~CFG_REGS_GPO_2_MASK) |
+            CFG_REGS_GPO_2_CLK_32K;
+    }
+    else
+    {
+        // Setup the pin as GPO (and low ouput has been
+        // configured in hal_BoardSetup())
+        hwp_configRegs->Alt_mux_select =
+            (hwp_configRegs->Alt_mux_select & ~CFG_REGS_GPO_2_MASK) |
+            CFG_REGS_GPO_2_GPO_2;
+    }
+}
+#endif
+
+// =============================================================================
+// hal_BoardSetupGeneral
+// -----------------------------------------------------------------------------
+/// Apply board dependent configuration to HAL for general purpose
+/// @param halCfg Pointer to HAL configuration structure (from the target
+/// module).
+// ============================================================================
+PROTECTED VOID hal_BoardSetupGeneral(CONST HAL_CFG_CONFIG_T* halCfg)
+{
+    UINT32 altMux = 0;
+
+    UINT32 availableGpo_A = 0;
+
+    UINT32 availableGpio_C = 0;
+    UINT32 availableGpio_A = 0;
+    UINT32 availableGpio_B = 0;
+    UINT32 availableGpio_D = 0;
+
+    UINT32 bootModeGpio_C = 0;
+    UINT32 bootModeGpio_A = 0;
+    UINT32 bootModeGpio_B = 0;
+    UINT32 bootModeGpio_D = 0;
+
+    UINT32 noConnectMask_C = 0;
+    UINT32 noConnectMask_A = 0;
+    UINT32 noConnectMask_B = 0;
+    UINT32 noConnectMask_D = 0;
+
+#ifdef FPGA
+
+    // no muxing, do nothing
+
+#else // !FPGA
+
+    // GPIOs as boot mode pins
+    bootModeGpio_C = HAL_GPIO_BIT(1)
+                   | HAL_GPIO_BIT(2)
+                   | HAL_GPIO_BIT(3)
+                   | HAL_GPIO_BIT(4)
+                   | HAL_GPIO_BIT(5);
+    bootModeGpio_A = HAL_GPIO_BIT(4)
+                   | HAL_GPIO_BIT(5)
+                   | HAL_GPIO_BIT(6)
+                   | HAL_GPIO_BIT(7);
+    bootModeGpio_B = HAL_GPIO_BIT(0);
+    bootModeGpio_D = 0;
+
+    // Available GPIOs
+    availableGpio_C |= HAL_GPIO_BIT(0)
+                     | HAL_GPIO_BIT(1)
+                     | HAL_GPIO_BIT(2)
+                     | HAL_GPIO_BIT(3)
+                     | HAL_GPIO_BIT(4)
+                     | HAL_GPIO_BIT(5);
+    // Volume down/up keys
+    availableGpio_D |= HAL_GPIO_BIT(5)
+                     | HAL_GPIO_BIT(6);
+
+    // Boot modes
+    BOOL spiFlashCam = FALSE;
+    BOOL spiFlashNand = FALSE;
+    if (g_bootBootMode & BOOT_MODE_BOOT_SPI)
+    {
+        if (g_bootBootMode & BOOT_MODE_SPI_PIN_NAND)
+        {
+            HAL_ASSERT((g_bootBootMode & BOOT_MODE_BOOT_EMMC),
+                "Emmc boot pin should be pulled up to boot on SPI flash over NAND pins");
+            spiFlashNand = TRUE;
+        }
+        else
+        {
+            spiFlashCam = TRUE;
+        }
+    }
+
+    if ((g_bootBootMode & (BOOT_MODE_BOOT_EMMC|BOOT_MODE_BOOT_SPI|BOOT_MODE_BOOT_SPI_NAND))
+        == BOOT_MODE_BOOT_EMMC)
+    {
+        // Boot from EMMC
+        HAL_ASSERT(halCfg->sdmmcCfg.sdmmc3Used, "SDMMC3 should be used");
+    }
+
+    if ( (g_bootBootMode & (BOOT_MODE_BOOT_SPI|BOOT_MODE_BOOT_SPI_NAND))
+         == BOOT_MODE_BOOT_SPI_NAND ||
+         (g_bootBootMode & (BOOT_MODE_BOOT_SPI|BOOT_MODE_NAND_PAGE_SIZE_L))
+         == (BOOT_MODE_BOOT_SPI|BOOT_MODE_NAND_PAGE_SIZE_L)
+       )
+    {
+        // Boot from SDMMC1
+        HAL_ASSERT(halCfg->sdmmcCfg.sdmmcUsed, "SDMMC1 should be used");
+    }
+
+    // For convenience, we do not consider spiFlashCam at present.
+    // We assume that SPI flash always uses parallel nand pins.
+#if 0
+    BOOL parallelNandUsed = halCfg->parallelNandUsed;
+#else
+    BOOL parallelNandUsed = !spiFlashNand && !halCfg->sdmmcCfg.sdmmc3Used;
+#endif
+    BOOL nand8_15Cam = FALSE;
+    BOOL nand8_15Lcd = FALSE;
+    if ((g_bootBootMode & BOOT_MODE_BOOT_EMMC) == 0)
+    {
+        // If BOOT_MODE_BOOT_EMMC is not set, the parallel NAND pins
+        // are multiplexed to parallel NAND controller
+        HAL_ASSERT(parallelNandUsed, "Parallel NAND should be used");
+        if ((g_bootBootMode & BOOT_MODE_NAND_8BIT) == 0)
+        {
+            if (g_bootBootMode & BOOT_MODE_NAND_HIGH_PIN_CAM)
+            {
+                nand8_15Cam = TRUE;
+            }
+            else
+            {
+                nand8_15Lcd = TRUE;
+            }
+        }
+    }
+
+    HAL_ASSERT(!(parallelNandUsed && spiFlashNand), "SPI flash uses parallel NAND pins");
+    HAL_ASSERT(!(nand8_15Cam && spiFlashCam), "NAND 8-15 bits and SPI flash both use cam pins");
+
+    if (!(parallelNandUsed || spiFlashNand))
+    {
+        availableGpio_B |= HAL_GPIO_BIT(25)
+                         | HAL_GPIO_BIT(26)
+                         | HAL_GPIO_BIT(27)
+                         | HAL_GPIO_BIT(28)
+                         | HAL_GPIO_BIT(29);
+        availableGpio_D |= HAL_GPIO_BIT(4);
+    }
+
+    CONST HAL_CFG_CAM_T *camCfg = &halCfg->camCfg;
+    CONST HAL_LCD_MODE_T lcdMode = halCfg->goudaCfg.lcdMode;
+
+    // LCD
+    if (lcdMode == HAL_LCD_MODE_PARALLEL_16BIT)
+    {
+        HAL_ASSERT(!nand8_15Lcd, "NAND uses LCD 8-15 bits");
+        altMux |= CFG_REGS_LCD_MODE_PARALLEL_16BIT;
+    }
+    else if (lcdMode == HAL_LCD_MODE_DSI)
+    {
+        altMux |= CFG_REGS_LCD_MODE_DSI;
+        availableGpio_A |= HAL_GPIO_BIT(22)
+                         | HAL_GPIO_BIT(23);
+    }
+    else if (lcdMode == HAL_LCD_MODE_RGB_16BIT)
+    {
+        HAL_ASSERT(!nand8_15Lcd, "NAND uses LCD 8-15 bits");
+        altMux |= CFG_REGS_LCD_MODE_RGB_16BIT;
+    }
+    else if (lcdMode == HAL_LCD_MODE_RGB_24BIT)
+    {
+        HAL_ASSERT(!nand8_15Lcd, "NAND uses LCD 8-15 bits");
+        if (halCfg->goudaCfg.lcd16_23Cam)
+        {
+            HAL_ASSERT(
+                !(camCfg->camMode == HAL_CAM_MODE_PARALLEL &&
+                  (camCfg->camUsed || camCfg->cam1Used)),
+                "Parallel camera uses LCD 16-23 bits");
+            HAL_ASSERT(
+                !(halCfg->i2cCfg.i2c2Used && halCfg->i2cCfg.i2c2PinsCam),
+                "I2C2 uses LCD 22-23 bits");
+            HAL_ASSERT(!spiFlashCam, "SPI flash uses LCD 16-21 bits");
+            HAL_ASSERT(!nand8_15Cam, "NAND uses LCD 16-23 bits");
+            HAL_ASSERT(
+                !(camCfg->camMode == HAL_CAM_MODE_CSI &&
+                  ((camCfg->camUsed && camCfg->camCsiId == HAL_CAM_CSI_1) ||
+                   (camCfg->cam1Used && camCfg->cam1CsiId == HAL_CAM_CSI_1))),
+                "Camera CSI1 uses LCD 16-21 bits");
+            altMux |= CFG_REGS_LCD24_CAM_CAM_IO;
+        }
+        else
+        {
+            HAL_ASSERT(!parallelNandUsed, "NAND uses LCD 16-23 bits");
+            HAL_ASSERT(!halCfg->sdmmcCfg.sdmmc3Used, "SDMMC3 uses LCD 16-23 bits");
+            altMux |= CFG_REGS_LCD24_CAM_NAND_IO;
+        }
+        altMux |= CFG_REGS_LCD_MODE_RGB_24BIT;
+    }
+    else if (lcdMode == HAL_LCD_MODE_SPI)
+    {
+        HAL_ASSERT(!(halCfg->goudaCfg.cs0Used || halCfg->goudaCfg.cs1Used),
+            "LCD CS 0/1 use SPI LCD pins");
+        HAL_ASSERT((halCfg->usedGpo_A & 0x18) == 0, "GPO 3/4 use SPI LCD pins");
+        altMux |= CFG_REGS_SPI_LCD_SPI_LCD;
+        availableGpio_A |= HAL_GPIO_BIT(18)
+                         | HAL_GPIO_BIT(19)
+                         | HAL_GPIO_BIT(20)
+                         | HAL_GPIO_BIT(21);
+    }
+    else
+    {
+        HAL_ASSERT(FALSE, "Lcd mode not defined!");
+    }
+
+    if (lcdMode == HAL_LCD_MODE_DSI || lcdMode == HAL_LCD_MODE_SPI)
+    {
+        if (nand8_15Lcd)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(24)
+                             | HAL_GPIO_BIT(25)
+                             | HAL_GPIO_BIT(26)
+                             | HAL_GPIO_BIT(27)
+                             | HAL_GPIO_BIT(28)
+                             | HAL_GPIO_BIT(29)
+                             | HAL_GPIO_BIT(30)
+                             | HAL_GPIO_BIT(31);
+        }
+    }
+
+    if (halCfg->goudaCfg.cs0Used)
+    {
+        altMux |= CFG_REGS_GPO_4_LCD_CS_0;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_4_GPO_4;
+        availableGpo_A |= HAL_GPO_BIT(4);
+    }
+
+    if (halCfg->goudaCfg.cs1Used)
+    {
+        altMux |= CFG_REGS_GPO_3_LCD_CS_1;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_3_GPO_3;
+        availableGpo_A |= HAL_GPO_BIT(3);
+    }
+
+    // I2C
+    if (!halCfg->i2cCfg.i2cUsed)
+    {
+        availableGpio_B |= HAL_GPIO_BIT(30)
+                         | HAL_GPIO_BIT(31);
+    }
+
+    if (halCfg->i2cCfg.i2c2Used)
+    {
+        if (halCfg->i2cCfg.i2c2PinsCam)
+        {
+            if (camCfg->camUsed)
+            {
+                HAL_ASSERT(camCfg->camPdnRemap == GPIO_NONE &&
+                    camCfg->camRstRemap == GPIO_NONE,
+                    "Cam uses PDN/RST pins");
+            }
+            if (camCfg->cam1Used)
+            {
+                HAL_ASSERT(camCfg->cam1PdnRemap == GPIO_NONE &&
+                    camCfg->cam1RstRemap == GPIO_NONE,
+                    "Cam1 uses PDN/RST pins");
+            }
+            HAL_ASSERT(!nand8_15Cam, "NAND uses cam PDN/RST pins");
+            availableGpio_A |= HAL_GPIO_BIT(0)
+                             | HAL_GPIO_BIT(1);
+            altMux |= CFG_REGS_CAM_I2C2_I2C2;
+        }
+        else
+        {
+            // I2C2 does not use cam pins
+            altMux |= CFG_REGS_CAM_I2C2_CAM;
+        }
+    }
+    else
+    {
+        // I2C2 does not use cam pins
+        altMux |= CFG_REGS_CAM_I2C2_CAM;
+        availableGpio_A |= HAL_GPIO_BIT(0)
+                         | HAL_GPIO_BIT(1);
+    }
+
+    if (halCfg->i2cCfg.i2c3Used)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x18) == 0, "Keyout 3/4 use I2C3 pins");
+        altMux |= CFG_REGS_KEYOUT_3_4_I2C3;
+    }
+    else
+    {
+        altMux |= CFG_REGS_KEYOUT_3_4_KEYOUT_3_4;
+        if ((halCfg->keyOutMask & 0x8) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(6);
+        }
+        if ((halCfg->keyOutMask & 0x10) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(7);
+        }
+    }
+
+    // Camera
+    if (camCfg->camUsed || camCfg->cam1Used)
+    {
+        if(camCfg->camMode == HAL_CAM_MODE_PARALLEL)
+        {
+            HAL_ASSERT(!spiFlashCam, "SPI flash uses cam pins");
+            HAL_ASSERT(!nand8_15Cam, "NAND 8-15 bits use cam pins");
+            altMux |= CFG_REGS_CSI2_PARALLEL_CAM;
+            availableGpio_B |= HAL_GPIO_BIT(24);
+        }
+        else if (camCfg->camMode == HAL_CAM_MODE_SPI)
+        {
+            altMux |= CFG_REGS_CSI2_SPI_CAM;
+            availableGpio_B |= HAL_GPIO_BIT(14);
+            if (!(spiFlashCam || nand8_15Cam ||
+                  (lcdMode == HAL_LCD_MODE_RGB_24BIT &&
+                   halCfg->goudaCfg.lcd16_23Cam)
+                 )
+               )
+            {
+                availableGpio_B |= HAL_GPIO_BIT(13)
+                                 | HAL_GPIO_BIT(20)
+                                 | HAL_GPIO_BIT(21)
+                                 | HAL_GPIO_BIT(22)
+                                 | HAL_GPIO_BIT(23)
+                                 | HAL_GPIO_BIT(24);
+            }
+        }
+        else if (camCfg->camMode == HAL_CAM_MODE_CSI)
+        {
+            if ((camCfg->camUsed && camCfg->camCsiId == HAL_CAM_CSI_1) ||
+                (camCfg->cam1Used && camCfg->cam1CsiId == HAL_CAM_CSI_1))
+            {
+                HAL_ASSERT(!spiFlashCam, "SPI flash uses CSI1 pins");
+                HAL_ASSERT(!nand8_15Cam, "NAND 8-15 bits use CSI1 pins");
+            }
+            else
+            {
+                // CSI1 is unused
+                if (!(spiFlashCam || nand8_15Cam ||
+                      (lcdMode == HAL_LCD_MODE_RGB_24BIT &&
+                       halCfg->goudaCfg.lcd16_23Cam)
+                     )
+                   )
+                {
+                    availableGpio_B |= HAL_GPIO_BIT(13)
+                                     | HAL_GPIO_BIT(20)
+                                     | HAL_GPIO_BIT(21)
+                                     | HAL_GPIO_BIT(22)
+                                     | HAL_GPIO_BIT(23)
+                                     | HAL_GPIO_BIT(24);
+                }
+            }
+            altMux |= CFG_REGS_CSI2_CSI2;
+            // If CSI2 is unused
+            if (!((camCfg->camUsed && camCfg->camCsiId == HAL_CAM_CSI_2) ||
+                  (camCfg->cam1Used && camCfg->cam1CsiId == HAL_CAM_CSI_2)))
+            {
+                availableGpio_B |= HAL_GPIO_BIT(14)
+                                 | HAL_GPIO_BIT(15)
+                                 | HAL_GPIO_BIT(16)
+                                 | HAL_GPIO_BIT(17)
+                                 | HAL_GPIO_BIT(18)
+                                 | HAL_GPIO_BIT(19);
+            }
+        }
+        else
+        {
+            HAL_ASSERT(FALSE,"Invalid cam mode: %d", camCfg->camMode);
+        }
+
+        // Cam PDN/RST pins
+        if (!(nand8_15Cam ||
+              (lcdMode == HAL_LCD_MODE_RGB_24BIT && halCfg->goudaCfg.lcd16_23Cam) ||
+              (halCfg->i2cCfg.i2c2Used && halCfg->i2cCfg.i2c2PinsCam)
+             )
+           )
+        {
+            if (!((camCfg->camUsed && camCfg->camRstRemap == GPIO_NONE) ||
+                  (camCfg->cam1Used && camCfg->cam1RstRemap == GPIO_NONE)))
+            {
+                availableGpio_B |= HAL_GPIO_BIT(10);
+            }
+            if (!((camCfg->camUsed && camCfg->camPdnRemap == GPIO_NONE) ||
+                  (camCfg->cam1Used && camCfg->cam1PdnRemap == GPIO_NONE)))
+            {
+                availableGpio_B |= HAL_GPIO_BIT(11);
+            }
+        }
+    }
+    else // cam is unused
+    {
+        availableGpio_B |= HAL_GPIO_BIT(12)
+                         | HAL_GPIO_BIT(14)
+                         | HAL_GPIO_BIT(15)
+                         | HAL_GPIO_BIT(16)
+                         | HAL_GPIO_BIT(17)
+                         | HAL_GPIO_BIT(18)
+                         | HAL_GPIO_BIT(19);
+        if (!(nand8_15Cam ||
+              (lcdMode == HAL_LCD_MODE_RGB_24BIT && halCfg->goudaCfg.lcd16_23Cam) ||
+              (halCfg->i2cCfg.i2c2Used && halCfg->i2cCfg.i2c2PinsCam)
+             )
+           )
+        {
+            availableGpio_B |= HAL_GPIO_BIT(10)
+                             | HAL_GPIO_BIT(11);
+        }
+        if (!(spiFlashCam || nand8_15Cam ||
+              (lcdMode == HAL_LCD_MODE_RGB_24BIT && halCfg->goudaCfg.lcd16_23Cam)
+             )
+           )
+        {
+            availableGpio_B |= HAL_GPIO_BIT(13)
+                             | HAL_GPIO_BIT(20)
+                             | HAL_GPIO_BIT(21)
+                             | HAL_GPIO_BIT(22)
+                             | HAL_GPIO_BIT(23)
+                             | HAL_GPIO_BIT(24);
+        }
+    }
+
+    // UART 1 Pin configuration
+    switch (halCfg->uartCfg[0])
+    {
+        case HAL_UART_CONFIG_NONE:
+            altMux |= CFG_REGS_KEYOUT_7_KEYOUT_7;
+            availableGpio_C |= HAL_GPIO_BIT(6);
+            availableGpio_A |= HAL_GPIO_BIT(14);
+            if ((halCfg->keyInMask & 0x80) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(15);
+            }
+            if ((halCfg->keyInMask & 0x80) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(16);
+            }
+            break;
+        case HAL_UART_CONFIG_DATA:
+             // use UART1 TXD, RXD
+            altMux |= CFG_REGS_KEYOUT_7_KEYOUT_7;
+            if ((halCfg->keyInMask & 0x80) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(15);
+            }
+            if ((halCfg->keyInMask & 0x80) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(16);
+            }
+            break;
+        case HAL_UART_CONFIG_FLOWCONTROL:
+             // use UART1 TXD, RXD, CTS, RTS
+            HAL_ASSERT((halCfg->keyInMask & 0x80) == 0, "Keyin 7 uses UART1 CTS");
+            HAL_ASSERT((halCfg->keyOutMask & 0x80) == 0, "Keyout 7 uses UART1 RTS");
+            altMux |= CFG_REGS_KEYOUT_7_UART1_RTS;
+            break;
+        case HAL_UART_CONFIG_MODEM:
+            // use UART1 TXD, RXD, CTS, RTS, RI, DSR, DCD, DTR
+            HAL_ASSERT((halCfg->keyInMask & 0x80) == 0, "Keyin 7 uses UART1 CTS");
+            HAL_ASSERT((halCfg->keyOutMask & 0x80) == 0, "Keyout 7 uses UART1 RTS");
+            HAL_ASSERT(!halCfg->hostUartUsed, "Host UART uses UART1 DCD/DTR");
+            HAL_ASSERT(halCfg->uartCfg[1] == HAL_UART_CONFIG_NONE,
+                    "UART 2 must be unused to use UART1 Modem lines.");
+            HAL_ASSERT((halCfg->keyInMask & 0x40) == 0, "Keyin 6 uses UART1 DSR");
+            HAL_ASSERT((halCfg->keyOutMask & 0x40) == 0, "Keyout 6 uses UART1 RI");
+            altMux |= CFG_REGS_KEYOUT_7_UART1_RTS
+                    | CFG_REGS_UART1_8LINE_UART1_8_LINE;
+            break;
+        default:
+            HAL_ASSERT(FALSE,
+                    "Invalid Uart 1 Configuration (%d).",
+                    halCfg->uartCfg[0]);
+            break;
+    }
+
+    // Host UART
+    if (halCfg->hostUartUsed)
+    {
+        HAL_ASSERT(halCfg->uartCfg[1] == HAL_UART_CONFIG_NONE,
+                "UART2 uses host UART RXD/TXD.");
+    }
+
+    // UART 2 Pin configuration
+    switch (halCfg->uartCfg[1])
+    {
+        case HAL_UART_CONFIG_NONE:
+            altMux |= CFG_REGS_UART2_HOST_UART
+                    | CFG_REGS_KEYOUT_6_KEYOUT_6;
+            if (halCfg->uartCfg[0] != HAL_UART_CONFIG_MODEM)
+            {
+                availableGpio_C |= HAL_GPIO_BIT(7)
+                                 | HAL_GPIO_BIT(8);
+            }
+            if ((halCfg->keyInMask & 0x40) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(8);
+            }
+            if ((halCfg->keyOutMask & 0x40) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(9);
+            }
+            break;
+        case HAL_UART_CONFIG_DATA:
+            // use UART2 TXD, RXD
+            altMux |= CFG_REGS_UART2_UART2
+                    | CFG_REGS_KEYOUT_6_KEYOUT_6;
+            if ((halCfg->keyInMask & 0x40) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(8);
+            }
+            if ((halCfg->keyOutMask & 0x40) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(9);
+            }
+            break;
+        case HAL_UART_CONFIG_FLOWCONTROL:
+             // use UART2 TXD, RXD, CTS, RTS
+            HAL_ASSERT((halCfg->keyInMask & 0x40) == 0, "Keyin 6 uses UART2 CTS");
+            HAL_ASSERT((halCfg->keyOutMask & 0x40) == 0, "Keyout 6 uses UART2 RTS");
+            altMux |= CFG_REGS_UART2_UART2
+                    | CFG_REGS_KEYOUT_6_UART2_RTS;
+            break;
+        case HAL_UART_CONFIG_MODEM:
+        default:
+            HAL_ASSERT(FALSE,
+                    "Invalid Uart2 Configuration (%d).",
+                    halCfg->uartCfg[1]);
+            break;
+    }
+
+    // UART 3 Pin configuration
+    switch (halCfg->uartCfg[2])
+    {
+        case HAL_UART_CONFIG_NONE:
+            availableGpio_D |= HAL_GPIO_BIT(0)
+                             | HAL_GPIO_BIT(1)
+                             | HAL_GPIO_BIT(2)
+                             | HAL_GPIO_BIT(3);
+            break;
+        case HAL_UART_CONFIG_DATA:
+            // use UART3 TXD, RXD
+            availableGpio_D |= HAL_GPIO_BIT(2)
+                             | HAL_GPIO_BIT(3);
+            break;
+        case HAL_UART_CONFIG_FLOWCONTROL:
+             // use UART3 TXD, RXD, CTS, RTS
+            break;
+        case HAL_UART_CONFIG_MODEM:
+        default:
+            HAL_ASSERT(FALSE,
+                    "Invalid Uart3 Configuration (%d).",
+                    halCfg->uartCfg[2]);
+            break;
+    }
+
+    // I2S
+    altMux |= CFG_REGS_DAI_I2S;
+    if (halCfg->i2sCfg.di0Used || halCfg->i2sCfg.di1Used ||
+        halCfg->i2sCfg.di2Used || halCfg->i2sCfg.doUsed)
+    {
+        if (!halCfg->i2sCfg.di0Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(11);
+        }
+        if (!halCfg->i2sCfg.di1Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(12);
+        }
+        if (halCfg->i2sCfg.di2Used)
+        {
+            HAL_ASSERT((halCfg->keyInMask & 0x4) == 0, "Keyin 2 uses I2S DI2");
+            altMux |= CFG_REGS_I2S_DI_2_I2S_DI_2;
+        }
+        else
+        {
+            altMux |= CFG_REGS_I2S_DI_2_KEYIN_2;
+            if ((halCfg->keyInMask & 0x4) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(2);
+            }
+        }
+        if (!halCfg->i2sCfg.doUsed)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(13);
+        }
+    }
+    else
+    {
+        availableGpio_A |= HAL_GPIO_BIT(9)
+                         | HAL_GPIO_BIT(10)
+                         | HAL_GPIO_BIT(11)
+                         | HAL_GPIO_BIT(12)
+                         | HAL_GPIO_BIT(13);
+    }
+
+    // LPS CO1
+    if (halCfg->useLpsCo1)
+    {
+        HAL_ASSERT((halCfg->keyInMask & 0x10) == 0, "Keyin 4 uses LPS_CO1");
+        altMux |= CFG_REGS_LPSCO_1_LPSCO_1;
+    }
+    else
+    {
+        altMux |= CFG_REGS_LPSCO_1_KEYIN_4;
+        if ((halCfg->keyInMask & 0x10) == 0)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(7);
+        }
+    }
+
+    // TCO
+    if (halCfg->usedTco & 0x1)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x1) == 0, "Keyout 0 uses TCO0");
+        altMux |= CFG_REGS_TCO_0_TCO_0;
+    }
+    else
+    {
+        altMux |= CFG_REGS_TCO_0_KEYOUT_0;
+        if ((halCfg->keyOutMask & 0x1) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(3);
+        }
+    }
+
+    if (halCfg->usedTco & 0x2)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x2) == 0, "Keyout 1 uses TCO1");
+        altMux |= CFG_REGS_TCO_1_TCO_1;
+    }
+    else
+    {
+        altMux |= CFG_REGS_TCO_1_KEYOUT_1;
+        if ((halCfg->keyOutMask & 0x2) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(4);
+        }
+    }
+
+    if (halCfg->usedTco & 0x4)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x4) == 0, "Keyout 2 uses TCO2");
+        altMux |= CFG_REGS_TCO_2_TCO_2;
+    }
+    else
+    {
+        altMux |= CFG_REGS_TCO_2_KEYOUT_2;
+        if ((halCfg->keyOutMask & 0x4) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(5);
+        }
+    }
+
+    // PWM
+    if (halCfg->pwmCfg.pwtUsed)
+    {
+        HAL_ASSERT((halCfg->keyInMask & 0x20) == 0, "Keyin 5 uses PWT");
+        altMux |= CFG_REGS_GPO_0_PWT;
+    }
+    else if (halCfg->keyInMask & 0x20)
+    {
+        altMux |= CFG_REGS_GPO_0_KEYIN_5;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_0_GPO_0;
+        availableGpo_A |= HAL_GPO_BIT(0);
+    }
+
+    if (halCfg->pwmCfg.lpgUsed)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x20) == 0, "Keyout 5 uses LPG");
+        altMux |= CFG_REGS_GPO_1_LPG;
+    }
+    else if (halCfg->keyOutMask & 0x20)
+    {
+        altMux |= CFG_REGS_GPO_1_KEYOUT_5;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_1_GPO_1;
+        availableGpo_A |= HAL_GPO_BIT(1);
+    }
+
+    if (halCfg->pwmCfg.pwl1Used)
+    {
+        HAL_ASSERT(!halCfg->useClk32k, "Clk 32k uses PWL1");
+        altMux |= CFG_REGS_GPO_2_PWL_1;
+    }
+    else if (halCfg->useClk32k)
+    {
+        // Default to GPO low output
+        // 32K clock will be enabled per request
+        //altMux |= CFG_REGS_GPO_2_CLK_32K;
+        altMux |= CFG_REGS_GPO_2_GPO_2;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_2_GPO_2;
+        availableGpo_A |= HAL_GPO_BIT(2);
+    }
+
+    // Clock out and host clock
+    if (halCfg->clkOutUsed)
+    {
+        HAL_ASSERT(!halCfg->hostClkUsed, "HST_CLK uses CLK_OUT pin");
+        altMux |= CFG_REGS_CLK_OUT_CLK_OUT;
+    }
+    else if (halCfg->hostClkUsed)
+    {
+        altMux |= CFG_REGS_CLK_OUT_HST_CLK;
+    }
+    else
+    {
+        altMux |= CFG_REGS_CLK_OUT_HST_CLK;
+        availableGpo_A |= HAL_GPO_BIT(8);
+    }
+
+    // SPI
+    if (halCfg->spiCfg[0].cs0Used || halCfg->spiCfg[0].cs1Used ||
+        halCfg->spiCfg[0].cs2Used)
+    {
+        HAL_ASSERT(!(halCfg->modemSpiCfg[0].cs0Used ||
+                     halCfg->modemSpiCfg[0].cs1Used ||
+                     halCfg->modemSpiCfg[0].cs2Used), "Modem SPI1 is in use");
+        altMux |= CFG_REGS_AP_SPI1_AP_SPI1;
+        if (!halCfg->spiCfg[0].cs0Used)
+        {
+            availableGpio_C |= HAL_GPIO_BIT(22);
+        }
+        if (!halCfg->spiCfg[0].cs1Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(17);
+        }
+        if (halCfg->spiCfg[0].cs2Used)
+        {
+            HAL_ASSERT((halCfg->keyInMask & 0x2) == 0, "Keyin 1 uses SPI1 CS2");
+            altMux |= CFG_REGS_SPI1_CS_2_SPI1_CS_2;
+        }
+        else
+        {
+            altMux |= CFG_REGS_SPI1_CS_2_KEYIN_1;
+            if ((halCfg->keyInMask & 0x2) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(1);
+            }
+        }
+        if (!halCfg->spiCfg[0].di0Used)
+        {
+            availableGpio_C |= HAL_GPIO_BIT(23);
+        }
+        if (!halCfg->spiCfg[0].di1Used)
+        {
+            availableGpio_C |= HAL_GPIO_BIT(24);
+        }
+    }
+    else // AP SPI1 unused
+    {
+        altMux |= CFG_REGS_AP_SPI1_BB_SPI1;
+        if (halCfg->modemSpiCfg[0].cs0Used || halCfg->modemSpiCfg[0].cs1Used ||
+            halCfg->modemSpiCfg[0].cs2Used)
+        {
+            if (!halCfg->modemSpiCfg[0].cs0Used)
+            {
+                availableGpio_C |= HAL_GPIO_BIT(22);
+            }
+            if (!halCfg->modemSpiCfg[0].cs1Used)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(17);
+            }
+            if (!halCfg->modemSpiCfg[0].di0Used)
+            {
+                availableGpio_C |= HAL_GPIO_BIT(23);
+            }
+            if (!halCfg->modemSpiCfg[0].di1Used)
+            {
+                availableGpio_C |= HAL_GPIO_BIT(24);
+            }
+        }
+        else
+        {
+            availableGpio_A |= HAL_GPIO_BIT(17);
+            availableGpio_C |= HAL_GPIO_BIT(21)
+                             | HAL_GPIO_BIT(22)
+                             | HAL_GPIO_BIT(23)
+                             | HAL_GPIO_BIT(24);
+            if ((halCfg->keyInMask & 0x2) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(1);
+            }
+        }
+    }
+    if (halCfg->spiCfg[1].cs0Used || halCfg->spiCfg[1].cs1Used)
+    {
+        if (!halCfg->spiCfg[1].cs0Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(5);
+        }
+        if (halCfg->spiCfg[1].cs1Used)
+        {
+            HAL_ASSERT((halCfg->keyInMask & 0x8) == 0, "Keyin 3 uses SPI2 CS1");
+            altMux |= CFG_REGS_KEYIN_3_SPI2_CS_1;
+        }
+        else
+        {
+            altMux |= CFG_REGS_KEYIN_3_KEYIN_3;
+            if ((halCfg->keyInMask & 0x8) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(6);
+            }
+        }
+        if (!halCfg->spiCfg[1].di0Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(3);
+        }
+        if (!halCfg->spiCfg[1].di1Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(4);
+        }
+    }
+    else // AP SPI2 unused
+    {
+        availableGpio_A |= HAL_GPIO_BIT(2)
+                         | HAL_GPIO_BIT(3)
+                         | HAL_GPIO_BIT(4)
+                         | HAL_GPIO_BIT(5);
+        if ((halCfg->keyInMask & 0x8) == 0)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(6);
+        }
+    }
+
+    // Standalone keyin/out
+    if ((halCfg->keyInMask & 0x1) == 0)
+    {
+        availableGpio_B |= HAL_GPIO_BIT(0);
+    }
+
+    // SDMMC
+    if (!halCfg->sdmmcCfg.sdmmcUsed)
+    {
+        availableGpio_C |= HAL_GPIO_BIT(9)
+                         | HAL_GPIO_BIT(10)
+                         | HAL_GPIO_BIT(11)
+                         | HAL_GPIO_BIT(12)
+                         | HAL_GPIO_BIT(13)
+                         | HAL_GPIO_BIT(14);
+    }
+    if (!halCfg->sdmmcCfg.sdmmc2Used)
+    {
+        availableGpio_C |= HAL_GPIO_BIT(15)
+                         | HAL_GPIO_BIT(16)
+                         | HAL_GPIO_BIT(17)
+                         | HAL_GPIO_BIT(18)
+                         | HAL_GPIO_BIT(19)
+                         | HAL_GPIO_BIT(20);
+    }
+    HAL_ASSERT(!(parallelNandUsed && halCfg->sdmmcCfg.sdmmc3Used),
+        "Parallel NAND uses SDMMC3 pins");
+
+    // SIM
+    if (!hal_BoardSimUsed(2))
+    {
+        availableGpio_C |= HAL_GPIO_BIT(25)
+                         | HAL_GPIO_BIT(26)
+                         | HAL_GPIO_BIT(27);
+    }
+
+    if (!hal_BoardSimUsed(3))
+    {
+        availableGpio_C |= HAL_GPIO_BIT(28)
+                         | HAL_GPIO_BIT(29)
+                         | HAL_GPIO_BIT(30);
+    }
+
+    UINT32 gpioMask;
+    // GPIO_C mask check
+    gpioMask = ~availableGpio_C & halCfg->usedGpio_C;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO C are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_C & halCfg->noConnectGpio_C;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO C declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_C & halCfg->noConnectGpio_C;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO C declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_C &
+               (~halCfg->usedGpio_C & ~halCfg->noConnectGpio_C);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO C declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPIO_A mask check
+    gpioMask = ~availableGpio_A & halCfg->usedGpio_A;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO A are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_A & halCfg->noConnectGpio_A;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO A declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_A & halCfg->noConnectGpio_A;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO A declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_A &
+               (~halCfg->usedGpio_A & ~halCfg->noConnectGpio_A);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO A declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPIO_B mask check
+    gpioMask = ~availableGpio_B & halCfg->usedGpio_B;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO B are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_B & halCfg->noConnectGpio_B;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO B declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_B & halCfg->noConnectGpio_B;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO B declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_B &
+               (~halCfg->usedGpio_B & ~halCfg->noConnectGpio_B);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO B declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPIO_D mask check
+    gpioMask = ~availableGpio_D & halCfg->usedGpio_D;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO D are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_D & halCfg->noConnectGpio_D;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO D declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_D & halCfg->noConnectGpio_D;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO D declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_D &
+               (~halCfg->usedGpio_D & ~halCfg->noConnectGpio_D);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO D declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPO_A mask check
+    gpioMask = ~availableGpo_A & halCfg->usedGpo_A;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPO A are not available (0x%x)",
+               gpioMask);
+
+#endif // !FPGA
+
+    // Set IO drive
+    hwp_configRegs->IO_Drive1_Select = halCfg->ioDrive.select1;
+    hwp_configRegs->IO_Drive2_Select = halCfg->ioDrive.select2;
+
+    // Set the not connected ones as output and drive 0
+    // But keep boot mode GPIOs as input to avoid current leakage
+    noConnectMask_C = halCfg->noConnectGpio_C & ~bootModeGpio_C;
+    noConnectMask_A = halCfg->noConnectGpio_A & ~bootModeGpio_A;
+    noConnectMask_B = halCfg->noConnectGpio_B & ~bootModeGpio_B;
+    noConnectMask_D = halCfg->noConnectGpio_D & ~bootModeGpio_D;
+
+    hwp_gpio->gpio_clr = noConnectMask_C;
+    hwp_gpio->gpio_oen_set_out = noConnectMask_C;
+
+    hwp_apGpioA->gpio_clr = noConnectMask_A;
+    hwp_apGpioA->gpio_oen_set_out = noConnectMask_A;
+
+    hwp_apGpioB->gpio_clr = noConnectMask_B;
+    hwp_apGpioB->gpio_oen_set_out = noConnectMask_B;
+
+    hwp_apGpioD->gpio_clr = noConnectMask_D;
+    hwp_apGpioD->gpio_oen_set_out = noConnectMask_D;
+
+    // Init GPO_A values
+    if (halCfg->useClk32k)
+    {
+        // Init 32K clock pin to low (by setting up GPO)
+        hwp_apGpioA->gpo_clr = availableGpo_A
+                             | HAL_GPO_BIT(2);
+    }
+    else
+    {
+	/* if GPO_1 used for usb id, it should be high */
+	#if defined(_TGT_AP_GPIO_USBID_CTRL)
+		hwp_apGpioA->gpo_clr = availableGpo_A & ~0x2;
+	#else
+		hwp_apGpioA->gpo_clr = availableGpo_A;
+	#endif
+    }
+
+    // Configure MUX after initializing all the GPO pins
+    // (GPIO pins are in input mode by default)
+
+    // Set GPIO mode
+    hwp_configRegs->BB_GPIO_Mode = availableGpio_C;
+    hwp_configRegs->AP_GPIO_A_Mode = availableGpio_A;
+    hwp_configRegs->AP_GPIO_B_Mode = availableGpio_B;
+    hwp_configRegs->AP_GPIO_D_Mode = availableGpio_D;
+    // Set Alt Mux configuration
+    hwp_configRegs->Alt_mux_select = altMux;
+
+    // --------------------------------------------------
+    // As of now, all connected GPIOs, which are as GPIO
+    // or not used at all but connected are configured as
+    // GPIOs in input mode, except for Gouda reset pins
+    // --------------------------------------------------
+
+}
+
+
+// =============================================================================
+// hal_BoardSetup
+// -----------------------------------------------------------------------------
+/// Apply board dependent configuration to HAL
+/// @param halCfg Pointer to HAL configuration structure (from the target
+/// module).
+// ============================================================================
+//PROTECTED VOID hal_BoardSetup(CONST HAL_CFG_CONFIG_T* halCfg)
+PUBLIC INT32 hal_BoardSetup(INT8 run_mode)
+{
+	g_bootBootMode = rda_hwcfg_get();
+	hal_BoardSetupGeneral(&hal_cfg);
+
+	if(g_halConfigError)
+		return CMD_RET_FAILURE;
+	else
+		return CMD_RET_SUCCESS;
+}
diff --git a/board/rda/rda8820/u-boot-spl.lds b/board/rda/rda8820/u-boot-spl.lds
new file mode 100644
index 0000000000..afe35fd2a8
--- /dev/null
+++ b/board/rda/rda8820/u-boot-spl.lds
@@ -0,0 +1,35 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00100100;
+	. = ALIGN(4);
+	.text :
+	{
+		__start = .;
+		arch/arm/cpu/armv7/start.o (.text)
+			*(.text)
+	}
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+	. = ALIGN(4);
+	.data : {
+		*(.data)
+	}
+	. = ALIGN(4);
+	. = .;
+	. = ALIGN(4);
+	__image_copy_end = .;
+	_end = .;
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+		ASSERT((ABSOLUTE(__bss_end__) < 0x00110000), \
+			"too big data in spl, don't exceed intrenal ram");
+	}
+}
diff --git a/board/rda/rda8850/Makefile b/board/rda/rda8850/Makefile
new file mode 100644
index 0000000000..2fc03d19cb
--- /dev/null
+++ b/board/rda/rda8850/Makefile
@@ -0,0 +1,82 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS-y	+= clock_config.o clock.o ddr3.o
+else
+COBJS-$(CONFIG_MACH_RDA8850) += hal_config.o
+endif
+
+RDA_TARGET_DEF_FILE := $(ANDROID_BUILD_TOP)/$(RDA_TARGET_DEVICE_DIR)/target.def
+RDA_GET_MAKEFILE_VAR_FUNC = $(strip $(shell sed -n 's/^[ 	]*$(1)[ 	]*[?:]\?=\([^\#]\+\)\#*.*$$/\1/p' $(2)))
+
+NUMBER_OF_SIM := $(call RDA_GET_MAKEFILE_VAR_FUNC,NUMBER_OF_SIM,$(RDA_TARGET_DEF_FILE))
+ifeq ($(NUMBER_OF_SIM),)
+$(error Failed to get NUMBER_OF_SIM in $(RDA_TARGET_DEF_FILE))
+endif
+
+USER_SIM_ORDER := $(call RDA_GET_MAKEFILE_VAR_FUNC,USER_SIM_ORDER,$(RDA_TARGET_DEF_FILE))
+ifeq ($(USER_SIM_ORDER),)
+$(error Failed to get USER_SIM_ORDER in $(RDA_TARGET_DEF_FILE))
+endif
+
+NULL_STRING :=
+SPACE := ${NULL_STRING} # end of the line
+COMMA := ,
+TGT_SIM_ORDER := $(foreach SIM,$(USER_SIM_ORDER),$(SIM)$(COMMA))
+TGT_SIM_ORDER := $(subst ${SPACE},,${TGT_SIM_ORDER})
+
+CPPFLAGS_board/$(BOARDDIR)/hal_config.o += -I$(TOPDIR)/board/$(VENDOR)/common/include -DTGT_SIM_ORDER=$(TGT_SIM_ORDER) -DNUMBER_OF_SIM=$(NUMBER_OF_SIM)
+
+ifeq ($(strip $(TARGET_TABLET_MODE)),true)
+CPPFLAGS_board/$(BOARDDIR)/clock.o += -DTARGET_TABLET_MODE
+endif
+
+COBJS   := $(COBJS-y)
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak *~ .depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/rda/rda8850/clock.c b/board/rda/rda8850/clock.c
new file mode 100644
index 0000000000..d773e9ccab
--- /dev/null
+++ b/board/rda/rda8850/clock.c
@@ -0,0 +1,1313 @@
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/rda_iomap.h>
+#include <asm/io.h>
+#include <asm/arch/reg_sysctrl.h>
+#include <asm/arch/hwcfg.h>
+#include <asm/arch/ispi.h>
+#include <asm/arch/rda_sys.h>
+#include "clock_config.h"
+#include "debug.h"
+#include "ddr3.h"
+#include "tgt_ap_clock_config.h"
+
+#if (PMU_VBUCK1_VAL < 0 || PMU_VBUCK1_VAL > 15)
+#error "Invalid PMU_VBUCK1_VAL"
+#endif
+#if (PMU_VBUCK3_VAL < 0 || PMU_VBUCK3_VAL > 15)
+#error "Invalid PMU_VBUCK3_VAL"
+#endif
+#ifdef PMU_VBUCK4_VAL
+#if (PMU_VBUCK4_VAL < 0 || PMU_VBUCK4_VAL > 15)
+#error "Invalid PMU_VBUCK4_VAL"
+#endif
+#endif
+
+//#define DO_SIMPLE_DDR_TEST
+//#define DO_DDR_PLL_DEBUG
+
+enum {
+	AP_CPU_CLK_IDX = 0,
+	AP_BUS_CLK_IDX,
+	AP_MEM_CLK_IDX,
+	AP_USB_CLK_IDX,
+};
+
+static int pll_enabled(int idx)
+{
+	if ((hwp_sysCtrlAp->Cfg_Pll_Ctrl[idx] &
+			(SYS_CTRL_AP_AP_PLL_ENABLE_MASK |
+			 SYS_CTRL_AP_AP_PLL_LOCK_RESET_MASK)) ==
+			(SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE |
+			 SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET))
+		return 1;
+	else
+		return 0;
+}
+
+static int usb_in_use = 0;
+
+static void check_usb_usage(void)
+{
+	unsigned int mask = SYS_CTRL_AP_BUS_SEL_FAST_SLOW |
+		SYS_CTRL_AP_PLL_LOCKED_BUS_MASK |
+		SYS_CTRL_AP_PLL_LOCKED_USB_MASK;
+	unsigned int reg = SYS_CTRL_AP_BUS_SEL_FAST_FAST |
+		SYS_CTRL_AP_PLL_LOCKED_BUS_LOCKED |
+		SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED;
+
+	if ((hwp_sysCtrlAp->Sel_Clock & mask) == reg &&
+			pll_enabled(AP_BUS_CLK_IDX) &&
+			pll_enabled(AP_USB_CLK_IDX))
+		usb_in_use = 1;
+	else
+		usb_in_use = 0;
+}
+
+#ifdef DO_SIMPLE_DDR_TEST
+
+void mem_test_write(void)
+{
+	volatile unsigned int *addr;
+
+	printf("write ddr test!!!!!!\n");
+
+ 	addr = (volatile unsigned int *)(0x80000000);
+	while((unsigned int)addr < 0x81000000)
+	{
+		*addr = (unsigned int )addr;
+		addr++;
+	}
+}
+
+void mem_test_read(void)
+{
+	volatile unsigned int *addr;
+
+	printf("read ddr!!!!\n");
+
+	addr = (volatile unsigned int *)(0x80000000);
+
+	while((unsigned int)addr < 0x81000000)
+	{
+		if (*addr != (unsigned int)addr){
+			int i = 0;
+			
+			printf("test error!!!!!, addr = %x\n", (unsigned int)addr);
+			for (i = 0; i < 80;i++){
+				printf("%x ", *(addr + i));
+				if ((i % 4) == 0)
+					printf("\n");
+			}
+
+			return;
+		}
+
+		addr++;
+	}
+	printf("test complete!\n");
+}
+
+#endif /* DO_SIMPLE_DDR_TEST */
+
+#ifndef CONFIG_RDA_FPGA
+
+// PMU bit fields
+#define PMU_SET_BITFIELD(dword, bitfield, value) \
+	(((dword) & ~(bitfield ## _MASK)) | (bitfield(value)))
+
+#define RDA_PMU_VBUCK1_BIT_ACT(n)        (((n)&0xf)<<12)
+#define RDA_PMU_VBUCK1_BIT_ACT_MASK      (0xf<<12)
+#define RDA_PMU_VBUCK1_BIT_ACT_SHIFT     (12)
+
+#define RDA_PMU_VBUCK4_BIT_ACT_SHIFT     (4)
+#define RDA_PMU_VBUCK4_BIT_ACT_MASK      (0xf<<4)
+#define RDA_PMU_VBUCK4_BIT_ACT(n)        (((n)&0xf)<<4)
+
+#define RDA_PMU_VBUCK3_BIT_ACT_SHIFT     (12)
+#define RDA_PMU_VBUCK3_BIT_ACT_MASK      (0xf<<12)
+#define RDA_PMU_VBUCK3_BIT_ACT(n)        (((n)&0xf)<<12)
+
+struct pll_freq {
+	UINT32 freq_mhz;
+	UINT16 major;
+	UINT16 minor;
+	UINT16 with_div;
+	UINT16 div;
+};
+
+typedef enum {
+	PLL_REG_CPU_BASE = 0x00,
+	PLL_REG_BUS_BASE = 0x20,
+	PLL_REG_MEM_BASE = 0x60,
+	PLL_REG_USB_BASE = 0x80,
+} PLL_REG_BASE_INDEX_t;
+
+typedef enum {
+	PLL_REG_OFFSET_01H = 1,
+	PLL_REG_OFFSET_02H = 2,
+	PLL_REG_OFFSET_DIV = 3,
+	PLL_REG_OFFSET_04H = 4,
+	PLL_REG_OFFSET_MAJOR = 5,
+	PLL_REG_OFFSET_MINOR = 6,
+	PLL_REG_OFFSET_07H = 7,
+} PLL_REG_OFFSET_INDEX_t;
+
+#define PLL_FREQ_TABLE_COUNT        21
+
+static struct pll_freq pll_freq_table[PLL_FREQ_TABLE_COUNT] = {
+	/* MHz Major   Minor   div */
+	{1600, 0x7B13, 0xB138, 0, 0x0000},
+	{1200, 0x5C4E, 0xC4EC, 0, 0x0000},
+	{1000, 0x4CEC, 0x4EC4, 0, 0x0000},
+	{ 800, 0x3D89, 0xD89C, 0, 0x0000},
+	{ 600, 0x2E27, 0x6274, 0, 0x0000},
+	{ 519, 0x27EC, 0x4EC4, 1, 0x0007},
+	{ 500, 0x2676, 0x2762, 1, 0x0007},
+	{ 480, 0x24EC, 0x4EC4, 0, 0x0000},
+	{ 455, 0x2300, 0x0000, 1, 0xF397},
+	{ 416, 0x2000, 0x0000, 1, 0xFA97},
+	/* 800M div 1, PLL:800M  DDR:400M for mem pll only */
+	{ 400, 0x1EC4, 0xEC4C, 1, 0xF997},
+	{ 355, 0x369D, 0x89D8, 1, 0x9597},
+	/* 702M div 1, PLL:702M  DDR:351M for mem pll only */
+	{ 351, 0x3600, 0x0000, 1, 0x9597},
+	{ 333, 0x333B, 0x13B1, 1, 0x9D97},
+	/* 624M div 1, PLL:624M  DDR:312M for mem pll only */
+	{ 312, 0x3000, 0x0000, 1, 0x9D97},
+	{ 290, 0x2C9D, 0x89D8, 1, 0x9A97},
+	/* 520M div 1, PLL:520M  DDR:260M for mem pll only */
+	{ 260, 0x2800, 0x0000, 1, 0xA297},
+	/* 800M div 2, PLL:400M  DDR:200M for mem pll only */
+	{ 200, 0x3D89, 0xD89C, 1, 0xB996},
+	/* DDR:156M for mem pll only */
+	{ 156, 0x3000, 0x0000, 1, 0x0006},
+	/* 800M div 4, PLL:200M  DDR:100M for mem pll only */
+	{ 100, 0x3D89, 0xD89C, 1, 0x0005},
+	/* 800M div 8, PLL:100M  DDR:50M for mem pll only */
+	{  50, 0x3D89, 0xD89C, 1, 0x0004},
+};
+
+static const struct clock_config *g_clock_config;
+
+#ifdef DO_DDR_PLL_DEBUG
+static struct clock_config clock_debug_config;
+static UINT32 ddrfreq = 400, ddr32bit = 0;
+#endif
+
+static void sys_shutdown_pll(void)
+{
+	int i;
+
+	hwp_sysCtrlAp->REG_DBG = AP_CTRL_PROTECT_UNLOCK;
+
+	if (usb_in_use) {
+		hwp_sysCtrlAp->Sel_Clock = SYS_CTRL_AP_SLOW_SEL_RF_RF
+			| SYS_CTRL_AP_CPU_SEL_FAST_SLOW
+			| SYS_CTRL_AP_BUS_SEL_FAST_FAST
+			| SYS_CTRL_AP_TIMER_SEL_FAST_FAST;
+	} else {
+		hwp_sysCtrlAp->Sel_Clock = SYS_CTRL_AP_SLOW_SEL_RF_RF
+			| SYS_CTRL_AP_CPU_SEL_FAST_SLOW
+			| SYS_CTRL_AP_BUS_SEL_FAST_SLOW
+			| SYS_CTRL_AP_TIMER_SEL_FAST_FAST;
+	}
+
+	for (i = 0; i < 3; i++) {
+		/* In download mode, rom code has been set ap bus*/
+		if (usb_in_use) {
+			if (i == AP_BUS_CLK_IDX) // ap bus
+				continue;
+		}
+		hwp_sysCtrlAp->Cfg_Pll_Ctrl[i] =
+			SYS_CTRL_AP_AP_PLL_ENABLE_POWER_DOWN |
+			SYS_CTRL_AP_AP_PLL_LOCK_RESET_RESET;
+	}
+}
+
+static void sys_setup_pll(void)
+{
+	int i;
+	UINT32 mask;
+	UINT32 locked;
+	int cnt = 10; //10us, according to IC, the pll must be locked
+
+	hwp_sysCtrlAp->REG_DBG = AP_CTRL_PROTECT_UNLOCK;
+
+	for (i = 0; i < 3; i++) {
+		/* In download mode, rom code has been set ap bus*/
+		if (usb_in_use) {
+			if (i == AP_BUS_CLK_IDX) // ap bus
+				continue;
+		}
+
+		if (AP_MEM_CLK_IDX == i)
+			hwp_sysCtrlAp->Cfg_Pll_Ctrl[i] =
+				SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE |
+				SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET |
+				SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(1)|
+				SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(30);
+		else
+			hwp_sysCtrlAp->Cfg_Pll_Ctrl[i] =
+				SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE |
+				SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET |
+				SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(6)|
+				SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(30);
+	}
+
+	mask = SYS_CTRL_AP_PLL_LOCKED_CPU_MASK
+	    | SYS_CTRL_AP_PLL_LOCKED_BUS_MASK
+	    | SYS_CTRL_AP_PLL_LOCKED_MEM_MASK
+	    //| SYS_CTRL_AP_PLL_LOCKED_USB_MASK
+	    ;
+	locked = SYS_CTRL_AP_PLL_LOCKED_CPU_LOCKED
+	    | SYS_CTRL_AP_PLL_LOCKED_BUS_LOCKED
+	    | SYS_CTRL_AP_PLL_LOCKED_MEM_LOCKED
+	    //| SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED
+	    ;
+
+	while (((hwp_sysCtrlAp->Sel_Clock & mask) != locked) && cnt) {
+		udelay(1);
+		cnt--;
+	}
+	if (cnt == 0) {
+		printf("WARNING, cannot lock cpu/bus/mem pll 0x%08x ",
+			hwp_sysCtrlAp->Sel_Clock);
+		printf("but we run anyway ...\n");
+	}
+
+	for (i = 0; i < 3; i++) {
+		hwp_sysCtrlAp->Cfg_Pll_Ctrl[i] |=
+		    SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_ENABLE;
+	}
+
+	hwp_sysCtrlAp->Sel_Clock = SYS_CTRL_AP_SLOW_SEL_RF_RF
+	    | SYS_CTRL_AP_CPU_SEL_FAST_FAST
+	    | SYS_CTRL_AP_BUS_SEL_FAST_FAST
+	    | SYS_CTRL_AP_TIMER_SEL_FAST_FAST;
+}
+
+static void sys_setup_clk(void)
+{
+	// Disable some power-consuming clocks
+	hwp_sysCtrlAp->Clk_APO_Disable = SYS_CTRL_AP_DISABLE_APOC_VPU;
+	//hwp_sysCtrlAp->Clk_MEM_Disable = SYS_CTRL_AP_DISABLE_MEM_VPU;
+
+	// Init clock gating mode
+	hwp_sysCtrlAp->Clk_CPU_Mode = 0;
+	hwp_sysCtrlAp->Clk_AXI_Mode = SYS_CTRL_AP_MODE_AXI_DMA_MANUAL;
+	hwp_sysCtrlAp->Clk_AXIDIV2_Mode = 0;
+	hwp_sysCtrlAp->Clk_GCG_Mode = SYS_CTRL_AP_MODE_GCG_GOUDA_MANUAL
+				| SYS_CTRL_AP_MODE_GCG_CAMERA_MANUAL;
+	hwp_sysCtrlAp->Clk_AHB1_Mode = 0;
+	hwp_sysCtrlAp->Clk_APB1_Mode = 0;
+	hwp_sysCtrlAp->Clk_APB2_Mode = 0;
+	hwp_sysCtrlAp->Clk_MEM_Mode = 0;
+	//hwp_sysCtrlAp->Clk_APO_Mode = SYS_CTRL_AP_MODE_APOC_VPU_MANUAL;
+
+	// Init module frequency
+	hwp_sysCtrlAp->Cfg_Clk_AP_CPU = g_clock_config->CLK_CPU;
+	hwp_sysCtrlAp->Cfg_Clk_AP_AXI = g_clock_config->CLK_AXI;
+	hwp_sysCtrlAp->Cfg_Clk_AP_GCG = g_clock_config->CLK_GCG;
+
+	if (!usb_in_use) {
+		hwp_sysCtrlAp->Cfg_Clk_AP_AHB1 = g_clock_config->CLK_AHB1;
+	}
+
+	hwp_sysCtrlAp->Cfg_Clk_AP_APB1 = g_clock_config->CLK_APB1;
+	hwp_sysCtrlAp->Cfg_Clk_AP_APB2 = g_clock_config->CLK_APB2;
+	hwp_sysCtrlAp->Cfg_Clk_AP_MEM = g_clock_config->CLK_MEM;
+	hwp_sysCtrlAp->Cfg_Clk_AP_GPU = g_clock_config->CLK_GPU;
+	hwp_sysCtrlAp->Cfg_Clk_AP_VPU = g_clock_config->CLK_VPU;
+	hwp_sysCtrlAp->Cfg_Clk_AP_VOC = g_clock_config->CLK_VOC;
+	hwp_sysCtrlAp->Cfg_Clk_AP_SFLSH = g_clock_config->CLK_SFLSH;
+}
+
+static void print_sys_reg(char *name, UINT32 value)
+{
+	printf("clk %s = %lx\n", name, value);
+}
+
+static void sys_dump_clk(void)
+{
+	print_sys_reg("CPU", hwp_sysCtrlAp->Cfg_Clk_AP_CPU);
+	print_sys_reg("AXI", hwp_sysCtrlAp->Cfg_Clk_AP_AXI);
+	print_sys_reg("GCG", hwp_sysCtrlAp->Cfg_Clk_AP_GCG);
+	print_sys_reg("AHB1", hwp_sysCtrlAp->Cfg_Clk_AP_AHB1);
+	print_sys_reg("APB1", hwp_sysCtrlAp->Cfg_Clk_AP_APB1);
+	print_sys_reg("APB2", hwp_sysCtrlAp->Cfg_Clk_AP_APB2);
+	print_sys_reg("MEM", hwp_sysCtrlAp->Cfg_Clk_AP_MEM);
+	print_sys_reg("GPU", hwp_sysCtrlAp->Cfg_Clk_AP_GPU);
+	print_sys_reg("VPU", hwp_sysCtrlAp->Cfg_Clk_AP_VPU);
+	print_sys_reg("VOC", hwp_sysCtrlAp->Cfg_Clk_AP_VOC);
+	print_sys_reg("SFLSH", hwp_sysCtrlAp->Cfg_Clk_AP_SFLSH);
+}
+
+static int pll_freq_set(UINT32 reg_base, UINT32 freq_mhz)
+{
+	int i;
+	struct pll_freq *freq;
+	unsigned int major, minor;
+	unsigned short value_02h;
+
+	/* find pll_freq */
+	for (i = 0; i < PLL_FREQ_TABLE_COUNT; i++) {
+		if (pll_freq_table[i].freq_mhz == freq_mhz)
+			break;
+	}
+	if (i >= PLL_FREQ_TABLE_COUNT) {
+		printf("pll_freq_set, fail to find freq\n");
+		return -1;
+	}
+
+	freq = &pll_freq_table[i];
+	if (freq->with_div && (reg_base == PLL_REG_MEM_BASE)) {
+		ispi_reg_write(reg_base + PLL_REG_OFFSET_DIV,
+				freq->div);
+		// Calculate the real MEM PLL freq
+		freq_mhz *= (1 << (8 - (freq->div & 0x7)));
+	}
+	if (freq_mhz >= 800 || reg_base == PLL_REG_USB_BASE) {
+		value_02h = 0x0309;
+		// Div PLL freq by 2
+		minor = ((freq->major & 0xFFFF) << 14) |
+			((freq->minor >> 2) & 0x3FFF);
+		minor >>= 1;
+		// Recalculate the divider
+		major = (minor >> 14) & 0xFFFF;
+		minor = (minor << 2) & 0xFFFF;
+	} else {
+		value_02h = 0x0209;
+		major = freq->major;
+		minor = freq->minor;
+	}
+	if (reg_base == PLL_REG_USB_BASE)
+		value_02h ^= (1 << 8);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_02H, value_02h);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_MAJOR, major);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_MINOR, minor);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_07H, 0x0010);
+
+	return 0;
+}
+
+static void pll_setup_freq(void)
+{
+	pll_freq_set(PLL_REG_CPU_BASE, g_clock_config->PLL_FREQ_CPU);
+	// Always configure BUS PLL, even when it is being used
+	pll_freq_set(PLL_REG_BUS_BASE, g_clock_config->PLL_FREQ_BUS);
+	pll_freq_set(PLL_REG_MEM_BASE, g_clock_config->PLL_FREQ_MEM);
+	pll_freq_set(PLL_REG_USB_BASE, g_clock_config->PLL_FREQ_USB);
+}
+
+static void print_pll_freq(char *name, UINT32 value)
+{
+	printf("pll freq %s = %d\n", name, (int)value);
+}
+
+static void sys_dump_pll_freq(void)
+{
+	print_pll_freq("CPU", g_clock_config->PLL_FREQ_CPU);
+	print_pll_freq("BUS", g_clock_config->PLL_FREQ_BUS);
+	print_pll_freq("MEM", g_clock_config->PLL_FREQ_MEM);
+	//print_pll_freq("USB", g_clock_config->PLL_FREQ_USB);
+}
+
+static void pmu_get_efuse_dcdc(int buckVoltLow[])
+{
+	static const u8 setBitCnt[8] = { 0, 1, 1, 2, 1, 2, 2, 3, };
+	u16 dcdc;
+	int i;
+
+	ispi_reg_write(0x51, 0x02ed);
+	udelay(2000);
+	ispi_reg_write(0x51, 0x02fd);
+	dcdc = ispi_reg_read(0x52);
+	ispi_reg_write(0x51, 0x0200);
+
+	for (i = 0; i < 4; i++) {
+		buckVoltLow[i] = (setBitCnt[dcdc & 0x7] > 1);
+		dcdc >>= 3;
+	}
+}
+
+static void pmu_setup_init(void)
+{
+	u32 value;
+	int buck_volt_low[4] = { 0, };
+
+	rda_nand_iodrive_set();
+
+#ifdef CONFIG_RDA_PDL
+	enable_charger(0);
+#endif
+
+	ispi_open(1);
+
+	// Disable vibrator
+	ispi_reg_write(0x03, 0x9FFF);
+	// Enable bandgap chopper mode
+	ispi_reg_write(0x0F, 0x1E90);
+	// Enable high AC throttling
+	ispi_reg_write(0x12, 0x1218);
+#ifdef TARGET_TABLET_MODE
+	// Charger current (cc = 6, pre = 7)
+	ispi_reg_write(0x13, 0x1B70);
+#else
+	// Charger current (cc = 2, pre = 7)
+	ispi_reg_write(0x13, 0x1970);
+#endif
+	// Vcore DCDC freq
+	ispi_reg_write(0x2D, 0x96BA);
+	ispi_reg_write(0x2E, 0x12AA);
+	// Get efuse dcdc
+	pmu_get_efuse_dcdc(buck_volt_low);
+	// Vcore voltage
+	value = 0x9244;
+	value = PMU_SET_BITFIELD(value, RDA_PMU_VBUCK1_BIT_ACT,
+			PMU_VBUCK1_VAL +
+			((PMU_VBUCK1_VAL < 15 && buck_volt_low[0]) ? 1 : 0));
+	ispi_reg_write(0x2F, value);
+	// DDR PWM mode
+	ispi_reg_write(0x0D, 0x92D0);
+	// DDR voltage
+	value = 0xAAB5;
+	value = PMU_SET_BITFIELD(value, RDA_PMU_VBUCK3_BIT_ACT,
+			PMU_VBUCK3_VAL +
+			((PMU_VBUCK3_VAL < 15 && buck_volt_low[2]) ? 1 : 0));
+#ifdef PMU_VBUCK4_VAL
+	value = PMU_SET_BITFIELD(value, RDA_PMU_VBUCK4_BIT_ACT,
+			PMU_VBUCK4_VAL +
+			((PMU_VBUCK4_VAL < 15 && buck_volt_low[3]) ? 1 : 0));
+	value ^= RDA_PMU_VBUCK4_BIT_ACT(8);
+	// vBuck4 in low voltage range
+	ispi_reg_write(0x36, 0x6E45);
+#else
+	ispi_reg_write(0x36, 0x6E54);
+#endif
+	ispi_reg_write(0x2A, value);
+	// DDR power parameters
+	ispi_reg_write(0x4A, 0x96AA);
+	ispi_reg_write(0x4B, 0x96AA);
+
+	ispi_open(0);
+}
+
+static void setup_ddr_vtt(int vtt)
+{
+	printf("setup ddr vtt to %d\n", vtt);
+	ispi_reg_write(0x69, 0x0008 | (vtt & 0x07) );
+}
+
+#if 0
+/*
+ * we initialize usb clock, but this won't cause the usb clock jitter,
+ * because wo don't setup the usb pll
+ */
+static void usb_clock_pre_init(void)
+{
+	ispi_reg_write(0x83, 0x72ef);
+	ispi_reg_write(0x89, 0x7400);
+}
+#endif
+
+static void pll_setup_init(void)
+{
+	setup_ddr_vtt(DDR_VTT_VAL);
+
+	if (g_clock_config->DDR_CHAN_1_VALID) {
+		ispi_reg_write(0x101, g_clock_config->DDR_TIMING_101H);
+		ispi_reg_write(0x102, g_clock_config->DDR_TIMING_102H);
+		ispi_reg_write(0x103, g_clock_config->DDR_TIMING_103H);
+		ispi_reg_write(0x104, g_clock_config->DDR_TIMING_104H);
+		ispi_reg_write(0x105, g_clock_config->DDR_TIMING_105H);
+		ispi_reg_write(0x106, g_clock_config->DDR_TIMING_106H);
+		ispi_reg_write(0x107, g_clock_config->DDR_TIMING_107H);
+		ispi_reg_write(0x108, g_clock_config->DDR_TIMING_108H);
+		ispi_reg_write(0x109, g_clock_config->DDR_TIMING_109H);
+		ispi_reg_write(0x10A, g_clock_config->DDR_TIMING_10AH);
+		ispi_reg_write(0x10B, g_clock_config->DDR_TIMING_10BH);
+		ispi_reg_write(0x10C, g_clock_config->DDR_TIMING_10CH);
+		ispi_reg_write(0x10D, g_clock_config->DDR_TIMING_10DH);
+		ispi_reg_write(0x10E, g_clock_config->DDR_TIMING_10EH);
+		ispi_reg_write(0x10F, g_clock_config->DDR_TIMING_10FH);
+	}
+
+	if (g_clock_config->DDR_CHAN_2_VALID) {
+		ispi_reg_write(0x121, g_clock_config->DDR_TIMING_121H);
+		ispi_reg_write(0x122, g_clock_config->DDR_TIMING_122H);
+		ispi_reg_write(0x123, g_clock_config->DDR_TIMING_123H);
+		ispi_reg_write(0x124, g_clock_config->DDR_TIMING_124H);
+		ispi_reg_write(0x125, g_clock_config->DDR_TIMING_125H);
+		ispi_reg_write(0x126, g_clock_config->DDR_TIMING_126H);
+		ispi_reg_write(0x127, g_clock_config->DDR_TIMING_127H);
+		ispi_reg_write(0x128, g_clock_config->DDR_TIMING_128H);
+		ispi_reg_write(0x129, g_clock_config->DDR_TIMING_129H);
+		ispi_reg_write(0x12A, g_clock_config->DDR_TIMING_12AH);
+		ispi_reg_write(0x12B, g_clock_config->DDR_TIMING_12BH);
+		ispi_reg_write(0x12C, g_clock_config->DDR_TIMING_12CH);
+		ispi_reg_write(0x12D, g_clock_config->DDR_TIMING_12DH);
+		ispi_reg_write(0x12E, g_clock_config->DDR_TIMING_12EH);
+		ispi_reg_write(0x12F, g_clock_config->DDR_TIMING_12FH);
+	}
+
+	if (g_clock_config->DDR_CHAN_3_VALID) {
+		ispi_reg_write(0x141, g_clock_config->DDR_TIMING_141H);
+		ispi_reg_write(0x142, g_clock_config->DDR_TIMING_142H);
+		ispi_reg_write(0x143, g_clock_config->DDR_TIMING_143H);
+		ispi_reg_write(0x144, g_clock_config->DDR_TIMING_144H);
+		ispi_reg_write(0x145, g_clock_config->DDR_TIMING_145H);
+		ispi_reg_write(0x146, g_clock_config->DDR_TIMING_146H);
+		ispi_reg_write(0x147, g_clock_config->DDR_TIMING_147H);
+		ispi_reg_write(0x148, g_clock_config->DDR_TIMING_148H);
+		ispi_reg_write(0x149, g_clock_config->DDR_TIMING_149H);
+		ispi_reg_write(0x14A, g_clock_config->DDR_TIMING_14AH);
+		ispi_reg_write(0x14B, g_clock_config->DDR_TIMING_14BH);
+		ispi_reg_write(0x14C, g_clock_config->DDR_TIMING_14CH);
+		ispi_reg_write(0x14D, g_clock_config->DDR_TIMING_14DH);
+		ispi_reg_write(0x14E, g_clock_config->DDR_TIMING_14EH);
+		ispi_reg_write(0x14F, g_clock_config->DDR_TIMING_14FH);
+	}
+
+	if (g_clock_config->DDR_CHAN_4_VALID) {
+		ispi_reg_write(0x161, g_clock_config->DDR_TIMING_161H);
+		ispi_reg_write(0x162, g_clock_config->DDR_TIMING_162H);
+		ispi_reg_write(0x163, g_clock_config->DDR_TIMING_163H);
+		ispi_reg_write(0x164, g_clock_config->DDR_TIMING_164H);
+		ispi_reg_write(0x165, g_clock_config->DDR_TIMING_165H);
+		ispi_reg_write(0x166, g_clock_config->DDR_TIMING_166H);
+		ispi_reg_write(0x167, g_clock_config->DDR_TIMING_167H);
+		ispi_reg_write(0x168, g_clock_config->DDR_TIMING_168H);
+		ispi_reg_write(0x169, g_clock_config->DDR_TIMING_169H);
+		ispi_reg_write(0x16A, g_clock_config->DDR_TIMING_16AH);
+		ispi_reg_write(0x16B, g_clock_config->DDR_TIMING_16BH);
+		ispi_reg_write(0x16C, g_clock_config->DDR_TIMING_16CH);
+		ispi_reg_write(0x16D, g_clock_config->DDR_TIMING_16DH);
+		ispi_reg_write(0x16E, g_clock_config->DDR_TIMING_16EH);
+		ispi_reg_write(0x16F, g_clock_config->DDR_TIMING_16FH);
+	}
+
+	ispi_reg_write(0x160, g_clock_config->DDR_TIMING_160H);
+	ispi_reg_write(0x180, g_clock_config->DDR_TIMING_180H);
+	ispi_reg_write(0x181, g_clock_config->DDR_TIMING_181H);
+	ispi_reg_write(0x182, g_clock_config->DDR_TIMING_182H);
+	ispi_reg_write(0x183, g_clock_config->DDR_TIMING_183H);
+	ispi_reg_write(0x184, g_clock_config->DDR_TIMING_184H);
+	ispi_reg_write(0x185, g_clock_config->DDR_TIMING_185H);
+	ispi_reg_write(0x186, g_clock_config->DDR_TIMING_186H);
+	ispi_reg_write(0x187, g_clock_config->DDR_TIMING_187H);
+	ispi_reg_write(0x188, g_clock_config->DDR_TIMING_188H);
+	ispi_reg_write(0x189, g_clock_config->DDR_TIMING_189H);
+	ispi_reg_write(0x18A, g_clock_config->DDR_TIMING_18AH);
+	ispi_reg_write(0x18B, g_clock_config->DDR_TIMING_18BH);
+
+	//usb_clock_pre_init();
+
+	udelay(5000);
+}
+
+static void pll_setup_mem(void)
+{
+}
+
+static void pll_setup_mem_cal(void)
+{
+}
+
+static void print_pll_reg(UINT32 index, UINT32 value)
+{
+	printf("pll reg %lx = %lx\n", index, value);
+}
+
+static void pll_dump_reg(void)
+{
+/*
+	print_pll_reg(0x005, ispi_reg_read(0x005));
+	print_pll_reg(0x006, ispi_reg_read(0x006));
+	print_pll_reg(0x063, ispi_reg_read(0x063));
+	print_pll_reg(0x065, ispi_reg_read(0x065));
+	print_pll_reg(0x066, ispi_reg_read(0x066));
+
+	if (g_clock_config->DDR_CHAN_1_VALID)
+	{
+		print_pll_reg(0x100, ispi_reg_read(0x100));
+		print_pll_reg(0x101, ispi_reg_read(0x101));
+		print_pll_reg(0x102, ispi_reg_read(0x102));
+		print_pll_reg(0x103, ispi_reg_read(0x103));
+		print_pll_reg(0x104, ispi_reg_read(0x104));
+		print_pll_reg(0x105, ispi_reg_read(0x105));
+		print_pll_reg(0x106, ispi_reg_read(0x106));
+		print_pll_reg(0x107, ispi_reg_read(0x107));
+		print_pll_reg(0x108, ispi_reg_read(0x108));
+		print_pll_reg(0x109, ispi_reg_read(0x109));
+		print_pll_reg(0x10A, ispi_reg_read(0x10A));
+		print_pll_reg(0x10B, ispi_reg_read(0x10B));
+		print_pll_reg(0x10C, ispi_reg_read(0x10C));
+		print_pll_reg(0x10D, ispi_reg_read(0x10D));
+		print_pll_reg(0x10E, ispi_reg_read(0x10E));
+		print_pll_reg(0x10F, ispi_reg_read(0x10F));
+	}
+
+	if (g_clock_config->DDR_CHAN_2_VALID)
+	{
+		print_pll_reg(0x120, ispi_reg_read(0x120));
+		print_pll_reg(0x121, ispi_reg_read(0x121));
+		print_pll_reg(0x122, ispi_reg_read(0x122));
+		print_pll_reg(0x123, ispi_reg_read(0x123));
+		print_pll_reg(0x124, ispi_reg_read(0x124));
+		print_pll_reg(0x125, ispi_reg_read(0x125));
+		print_pll_reg(0x126, ispi_reg_read(0x126));
+		print_pll_reg(0x127, ispi_reg_read(0x127));
+		print_pll_reg(0x128, ispi_reg_read(0x128));
+		print_pll_reg(0x129, ispi_reg_read(0x129));
+		print_pll_reg(0x12A, ispi_reg_read(0x12A));
+		print_pll_reg(0x12B, ispi_reg_read(0x12B));
+		print_pll_reg(0x12C, ispi_reg_read(0x12C));
+		print_pll_reg(0x12D, ispi_reg_read(0x12D));
+		print_pll_reg(0x12E, ispi_reg_read(0x12E));
+		print_pll_reg(0x12F, ispi_reg_read(0x12F));
+	}
+
+	if (g_clock_config->DDR_CHAN_3_VALID)
+	{
+		print_pll_reg(0x140, ispi_reg_read(0x140));
+		print_pll_reg(0x141, ispi_reg_read(0x141));
+		print_pll_reg(0x142, ispi_reg_read(0x142));
+		print_pll_reg(0x143, ispi_reg_read(0x143));
+		print_pll_reg(0x144, ispi_reg_read(0x144));
+		print_pll_reg(0x145, ispi_reg_read(0x145));
+		print_pll_reg(0x146, ispi_reg_read(0x146));
+		print_pll_reg(0x147, ispi_reg_read(0x147));
+		print_pll_reg(0x148, ispi_reg_read(0x148));
+		print_pll_reg(0x149, ispi_reg_read(0x149));
+		print_pll_reg(0x14A, ispi_reg_read(0x14A));
+		print_pll_reg(0x14B, ispi_reg_read(0x14B));
+		print_pll_reg(0x14C, ispi_reg_read(0x14C));
+		print_pll_reg(0x14D, ispi_reg_read(0x14D));
+		print_pll_reg(0x14E, ispi_reg_read(0x14E));
+		print_pll_reg(0x14F, ispi_reg_read(0x14F));
+	}
+
+	if (g_clock_config->DDR_CHAN_4_VALID)
+	{
+		print_pll_reg(0x161, ispi_reg_read(0x161));
+		print_pll_reg(0x162, ispi_reg_read(0x162));
+		print_pll_reg(0x163, ispi_reg_read(0x163));
+		print_pll_reg(0x164, ispi_reg_read(0x164));
+		print_pll_reg(0x165, ispi_reg_read(0x165));
+		print_pll_reg(0x166, ispi_reg_read(0x166));
+		print_pll_reg(0x167, ispi_reg_read(0x167));
+		print_pll_reg(0x168, ispi_reg_read(0x168));
+		print_pll_reg(0x169, ispi_reg_read(0x169));
+		print_pll_reg(0x16A, ispi_reg_read(0x16A));
+		print_pll_reg(0x16B, ispi_reg_read(0x16B));
+		print_pll_reg(0x16C, ispi_reg_read(0x16C));
+		print_pll_reg(0x16D, ispi_reg_read(0x16D));
+		print_pll_reg(0x16E, ispi_reg_read(0x16E));
+		print_pll_reg(0x16F, ispi_reg_read(0x16F));
+	}
+
+	print_pll_reg(0x160, ispi_reg_read(0x160));
+	print_pll_reg(0x180, ispi_reg_read(0x180));
+	print_pll_reg(0x181, ispi_reg_read(0x181));
+	print_pll_reg(0x182, ispi_reg_read(0x182));
+	print_pll_reg(0x183, ispi_reg_read(0x183));
+	print_pll_reg(0x184, ispi_reg_read(0x184));
+	print_pll_reg(0x185, ispi_reg_read(0x185));
+	print_pll_reg(0x186, ispi_reg_read(0x186));
+	print_pll_reg(0x187, ispi_reg_read(0x187));
+	print_pll_reg(0x188, ispi_reg_read(0x188));
+	print_pll_reg(0x189, ispi_reg_read(0x189));
+	print_pll_reg(0x18A, ispi_reg_read(0x18A));
+	print_pll_reg(0x18B, ispi_reg_read(0x18B));
+	print_pll_reg(0x18C, ispi_reg_read(0x18C));
+*/
+}
+
+static int clock_save_config(void)
+{
+	/* save config to nand */
+	return 1;
+}
+
+#ifdef DO_DDR_PLL_DEBUG
+
+static int ddr_get_freq(UINT8 chioce)
+{
+	switch(chioce)
+	{
+		case 1:
+			return 50;
+		case 2:
+			return 100;
+		case 3:
+			return 156;
+		case 4:
+			return 200;
+		case 5:
+			return 290;
+		case 6:
+			return 333;
+		case 7:
+			return 355;
+		case 8:
+			return 400;
+		case 9:
+			return 416;
+		case 10:
+			return 455;
+		case 11:
+			return 500;
+		case 12:
+			return 519;
+		case 13:
+			return 260;
+		default:
+			return -1;
+	}
+}
+
+static void freq_choose(void)
+{
+	UINT8 i = 0, buf[3] = {0}, choice = 0;
+	INT32 freq_temp = 0;
+
+	printf("\nPlese choose the ddr Freq:");
+	printf("\n1.50M  2.100M  3.156M  4.200M  5.290M  6.333M  7.355M  8.400M 9.416M 10.455M 11.500M 12.519M 13.260M");
+	printf("\nThe number is:");
+
+	while(1)
+	{
+		if (i > 2)
+		{
+			printf("\n Sorry, you input is wrong. Please input again:");
+			i = 0;
+		}
+		buf[i] = serial_getc();
+		serial_putc(buf[i]);
+
+		if ( ('\r' == buf[i]) || ('\n' == buf[i]))
+		{
+			serial_puts("\n");
+			break;
+		}
+
+		i++;
+	}
+
+	if (1 == i)
+		choice = buf[0] - 0x30;
+	else if (2 == i)
+		choice = 10*(buf[0] - 0x30) + (buf[1] - 0x30);
+	else
+		return;
+
+	freq_temp = ddr_get_freq(choice);
+	if (-1 == freq_temp )
+		printf("\n Sorry, the fre you choose is wrong");
+	ddrfreq = freq_temp;
+}
+
+static void data_bits_choose(void)
+{
+	UINT8 i = 0, buf[2] = {0};
+
+	printf("\nPlese choose the ddr data bits:");
+	printf("\n1.16  2.32");
+	printf("\nThe number is:");
+
+	while(1)
+	{
+		buf[i] =serial_getc();
+
+		if (i == 1)
+		{
+			if (('\r' == buf[i]) || ('\n' == buf[i]))
+			{
+				if (1 == (buf[0] - 0x30))
+					ddr32bit = 0;
+				else
+					ddr32bit = 1;
+				return;
+			}
+			else
+			{
+				printf("\n Sorry, you input is wrong. Please input again:");
+				i = 0;
+				continue;
+			}
+		}
+
+		serial_putc(buf[i]);
+
+		if ((buf[i] - 0x30) > 2 || 0 == (buf[i] - 0x30))
+			printf("\n Sorry, you input is wrong. Please input again:");
+		else
+			i++;
+	}
+}
+
+#if 0
+static void pmu_setup_calibration_voltage(UINT8 vcoreselect)
+{
+	UINT8 buf[3] = {0}, voltage = 0;
+	int i = 0;
+	UINT32 reg_value,temp, regid = 0;
+
+	ispi_open(1);
+	if (1 == vcoreselect)
+	{
+		regid = 0x2f;
+		printf("\nPlese input vcore voltage(0 ~ 15):");
+	}
+	else
+	{
+		regid = 0x2a;
+		printf("\nPlese input DDR voltage(0 ~ 15):");
+	}
+
+
+	while(1)
+	{
+		if (i > 2)
+		{
+			printf("\n Sorry, you input is wrong. Please input again:");
+			i = 0;
+		}
+		buf[i] = serial_getc();
+		serial_putc(buf[i]);
+
+		if ( ('\r' == buf[i]) || ('\n' == buf[i]))
+		{
+			printf("\n");
+			break;
+		}
+
+		i++;
+	}
+
+	if (1 == i)
+		voltage = buf[0] - 0x30;
+	else if (2 == i)
+		voltage = 10*(buf[0] - 0x30) + (buf[1] - 0x30);
+	else
+		return;
+
+	temp = (UINT32)voltage;
+	temp = (temp & 0xf) << 12;
+	reg_value = ispi_reg_read(regid);
+	reg_value &= ~(0xf << 12);
+	reg_value |= temp ;
+	ispi_reg_write(regid, reg_value);
+	mdelay(100);
+}
+#endif
+
+static void pmu_setup_calibration_voltage(UINT8 vcoreselect)
+{
+	UINT8 buf[3] = {0}, voltage = 0;
+	int i = 0;
+	UINT32 reg_value,temp, regid = 0;
+
+	ispi_open(1);
+	if (1 == vcoreselect)
+	{
+		regid = 0x2f;
+		printf("\nPlese input vcore voltage(0 ~ 15):");
+	}
+	else
+	{
+		regid = 0x2a;
+		if (2 == vcoreselect)
+			printf("\nPlese input DDR buck3 voltage(0 ~ 15):");
+		else
+			printf("\nPlese input DDR buck4 voltage(0 ~ 15):");
+	}
+
+	while(1)
+	{
+		if (i > 2)
+		{
+			printf("\n Sorry, you input is wrong. Please input again:");
+			i = 0;
+		}
+		buf[i] = serial_getc();
+		serial_putc(buf[i]);
+
+		if ( ('\r' == buf[i]) || ('\n' == buf[i]))
+		{
+			printf("\n");
+			break;
+		}
+
+		i++;
+	}
+
+	if (1 == i)
+		voltage = buf[0] - 0x30;
+	else if (2 == i)
+		voltage = 10*(buf[0] - 0x30) + (buf[1] - 0x30);
+	else
+		return;
+
+	if ((vcoreselect == 1) || (vcoreselect == 2))
+	{
+		temp = (UINT32)voltage;
+		temp = (temp & 0xf) << 12;
+		reg_value = ispi_reg_read(regid);
+		reg_value &= ~(0xf << 12);
+		reg_value |= temp ;
+		ispi_reg_write(regid, reg_value);
+		mdelay(100);
+	}
+	else
+	{
+		temp = (UINT32)voltage;
+		temp = (temp & 0xf) << 4;
+		reg_value = ispi_reg_read(regid);
+		reg_value &= ~(0xf << 4);
+		reg_value |= temp ;
+		reg_value ^= RDA_PMU_VBUCK4_BIT_ACT(8);
+		ispi_reg_write(regid, reg_value);
+		ispi_reg_write(0x0D, 0x92D0);
+		ispi_reg_write(0x4B, 0x96A8);
+		mdelay(100);
+	}
+}
+
+static void pmu_buck4_buck3_choose(void)
+{
+	UINT8 i = 0, buf[2] = {0};
+	UINT8 ddr_voltage_source = 0;
+
+	printf("\nPlese choose the ddr voltage:");
+	printf("\n1.DDR3L  2.DDR3");
+	printf("\nThe number is:");
+
+	while(1)
+	{
+		buf[i] =serial_getc();
+
+		if (i == 1)
+		{
+			if (('\r' == buf[i]) || ('\n' == buf[i]))
+			{
+				if (1 == (buf[0] - 0x30))
+					ddr_voltage_source =2;
+				else{
+					ddr_voltage_source = 3;
+					pmu_setup_calibration_voltage(2);
+				}
+				pmu_setup_calibration_voltage(ddr_voltage_source);
+				return;
+			}
+			else
+			{
+				printf("\n Sorry, you input is wrong. Please input again:");
+				i = 0;
+				continue;
+			}
+		}
+
+		serial_putc(buf[i]);
+
+		if ((buf[i] - 0x30) > 2 || 0 == (buf[i] - 0x30))
+			printf("\n Sorry, you input is wrong. Please input again:");
+		else
+			i++;
+	}
+}
+
+
+void clock_load_ddr_cal_config(void)
+{
+	clock_debug_config.PLL_FREQ_MEM = ddrfreq;
+	if (ddrfreq < 200)
+		clock_debug_config.DDR_FLAGS |= DDR_FLAGS_DLLOFF;
+	else
+		clock_debug_config.DDR_FLAGS &= ~DDR_FLAGS_DLLOFF;
+
+	if (0 == ddr32bit)
+	{
+		clock_debug_config.DDR_CHAN_3_VALID = 0;
+		clock_debug_config.DDR_CHAN_4_VALID = 0;
+	}
+
+	clock_debug_config.DDR_PARA &= ~DDR_PARA_MEM_BITS_MASK;
+	if (0 == ddr32bit)
+		clock_debug_config.DDR_PARA |= DDR_PARA_MEM_BITS(1);
+	else
+		clock_debug_config.DDR_PARA |= DDR_PARA_MEM_BITS(2);
+}
+
+static int serial_gets(UINT8 *pstr)
+{
+    UINT32 length;
+
+    length = 0;
+    while(1) {
+        pstr[length] = serial_getc();
+        if(pstr[length] == '\r') {
+            pstr[length] = 0x00;
+            break;
+        }
+        else if( pstr[length] == '\b' ) {
+            if(length>0) {
+                length --;
+                printf("\b");
+            }
+        }
+        else {
+            serial_putc(pstr[length]);
+            length ++;
+        }
+
+        if(length > 32)
+            return -1;
+    }
+    return length;
+}
+
+UINT32 asc2hex(UINT8 *pstr, UINT8 len)
+{
+	UINT8 i,ch,mylen;
+	UINT32 hexvalue;
+
+	for(mylen=0,i=0; i<8; i++)
+	{
+		if( pstr[i] == 0 )
+			break;
+		mylen ++;
+	}
+	if( len != 0 )
+	{
+		if(mylen>len)
+			mylen = len;
+	}
+	if(mylen>8)
+		mylen = 8;
+
+	hexvalue = 0;
+	for (i = 0; i < mylen; i++)
+	{
+		hexvalue <<= 4;
+		ch = *(pstr+i);
+		if((ch>='0') && (ch<='9'))
+			hexvalue |= ch - '0';
+		else if((ch>='A') && (ch<='F'))
+			hexvalue |= ch - ('A' - 10);
+		else if((ch>='a') && (ch<='f'))
+			hexvalue |= ch - ('a' - 10);
+		else
+			;
+	}
+	return(hexvalue);
+}
+
+static int process_cmd(char * cmd)
+{
+	char cmd_element[3][16] = {{0}};
+	char * cmd_temp = cmd;
+	UINT8 i = 0, cmd_element_num = 0, former_space = 1;
+	UINT16 reg = 0, reg_value = 0;
+
+	if (NULL == cmd)
+		return -1;
+
+	while(('\0' != *cmd_temp) && ('\r' != *cmd_temp) && ('\n' != *cmd_temp))
+	{
+		if (' ' == * cmd_temp)
+		{
+			if (0 == former_space)
+			{
+				former_space = 1;
+				cmd_element[cmd_element_num][i] = '\0';
+				cmd_element_num++;
+				if (cmd_element_num > 2)
+					return -1;
+			
+				i = 0;
+			}
+		}
+		else
+		{
+			former_space = 0;
+			cmd_element[cmd_element_num][i] = *cmd_temp;
+			i++;
+			if (i > 6)
+				return -1;
+		}
+
+		cmd_temp++;	
+	}
+
+	cmd_element[cmd_element_num][i] = '\0';
+
+	if (!strcmp(cmd_element[0], "read"))
+	{
+		if (cmd_element_num == 2)
+			return -1;
+		if (('0' != cmd_element[1][0]) || ('x' != cmd_element[1][1]))
+			return -1;
+		reg = (UINT16)asc2hex((UINT8 *)&cmd_element[1][2], 4);
+		reg_value = ispi_reg_read(reg);
+		printf("value = 0x%x", reg_value);
+		printf("\nddrPll#");
+	}	
+	else if (!strcmp(cmd_element[0], "write"))
+	{
+		if (cmd_element_num != 2)
+			return -1;
+		if (('0' != cmd_element[1][0]) || ('x' != cmd_element[1][1])
+		   || ('0' != cmd_element[2][0]) || ('x' != cmd_element[2][1]))
+			return -1;
+
+		reg = (UINT16)asc2hex((UINT8 *)&cmd_element[1][2], 4);
+		reg_value  = (UINT16)asc2hex((UINT8 *)&cmd_element[2][2], 4);
+		ispi_reg_write(reg, reg_value);
+	}
+	else if (!strcmp(cmd_element[0], "finish"))
+	{
+		return 1;
+	}
+	else if (!strcmp(cmd_element[0], "dump"))
+	{    
+		pll_dump_reg();
+		printf("ddrPll#");
+	}
+	else
+	{    
+		return -1;
+	}
+
+	return 0;
+}
+
+static void cmd_input(void)
+{
+	char cmd[48] = {0};
+	int len = 0;
+	
+	ispi_open(0);
+	printf("\nddrPll#");
+	while(1)
+	{
+		len = serial_gets((UINT8 *)cmd);
+		printf("\nddrPll#");
+		if (len > 0)
+		{
+			int result = 0;
+
+			result =  process_cmd(cmd);
+			if (-1 == result)
+				printf("command error! \nddrPll#");
+			else if (1 == result)
+				break;
+			else
+				continue;
+		}
+	}
+
+	return;
+}
+
+#endif /* DO_DDR_PLL_DEBUG */
+
+int clock_init(void)
+{
+#ifdef DO_DDR_PLL_DEBUG
+	char choice = 'n';
+#endif
+
+	/* First check current usb usage */
+	check_usb_usage();
+
+	printf("Init Clock ...\n");
+	g_clock_config = get_default_clock_config();
+
+	printf("Clock config ver: %d.%d\n",
+		g_clock_config->VERSION_MAJOR, g_clock_config->VERSION_MINOR);
+
+	pmu_setup_init();
+
+#ifdef DO_DDR_PLL_DEBUG
+	printf("If you want to config the ddr para manully ?(y = yes, n = no) \n");
+	choice = serial_getc();
+	if (choice == 'y')
+	{
+		memcpy(&clock_debug_config, g_clock_config,
+				sizeof(clock_debug_config));
+		g_clock_config = &clock_debug_config;
+		pmu_setup_calibration_voltage(1);
+		pmu_buck4_buck3_choose();
+		freq_choose();
+		data_bits_choose();
+		clock_load_ddr_cal_config();
+	}
+#endif
+
+	sys_shutdown_pll();
+	ispi_open(0);
+	pll_setup_init();
+#ifdef DO_DDR_PLL_DEBUG
+	if (choice == 'y')
+		cmd_input();
+#endif
+	pll_setup_freq();
+	sys_setup_pll();
+	sys_setup_clk();
+
+	if (g_clock_config->DDR_CAL) {
+		printf("Init DDR for ddr_cal\n");
+		ddr_init(g_clock_config->DDR_FLAGS, g_clock_config->DDR_PARA);
+		printf("Done\n");
+		pll_setup_mem_cal();
+		clock_save_config();
+	} else {
+		pll_setup_mem();
+	}
+
+	sys_dump_pll_freq();
+	sys_dump_clk();
+	pll_dump_reg();
+
+	printf("Init DDR, flag = 0x%04x, para = 0x%08lx\n",
+		g_clock_config->DDR_FLAGS, g_clock_config->DDR_PARA);
+	ddr_init(g_clock_config->DDR_FLAGS, g_clock_config->DDR_PARA);
+	printf("Done\n");
+
+	#ifdef DO_SIMPLE_DDR_TEST
+	mem_test_write();
+	mem_test_read();
+#endif
+
+	return 0;
+}
+
+#else /* CONFIG_RDA_FPGA */
+
+int clock_init(void)
+{
+	u16 ddr_flags = DDR_FLAGS_DLLOFF
+		| DDR_FLAGS_ODT(1)
+		| DDR_FLAGS_RON(0);
+	//32bit
+	u32 ddr_para = DDR_PARA_MEM_BITS(2)
+		| DDR_PARA_BANK_BITS(3)
+		| DDR_PARA_ROW_BITS(3)
+		| DDR_PARA_COL_BITS(2);
+
+	printf("Init DDR\n");
+	ddr_init(ddr_flags, ddr_para);
+	printf("Done\n");
+
+#ifdef DO_SIMPLE_DDR_TEST
+	mem_test_write();
+	mem_test_read();
+#endif
+
+	return 0;
+}
+
+#endif /* CONFIG_RDA_FPGA */
+
diff --git a/board/rda/rda8850/clock_config.c b/board/rda/rda8850/clock_config.c
new file mode 100644
index 0000000000..6df3c72e62
--- /dev/null
+++ b/board/rda/rda8850/clock_config.c
@@ -0,0 +1,147 @@
+#ifndef TARGET_TOOL
+#include <common.h>
+#include <asm/arch/factory.h>
+#include "clock_config.h"
+#endif
+
+#include "ddr3.h"
+#include "tgt_ap_clock_config.h"
+
+static const struct clock_config clock_default_config = {
+	/* Header */
+	0, 			// MAGIC;
+	CLOCK_VER_MAJOR,	// VERSION_MAJOR;
+	CLOCK_VER_MINOR,	// VERSION_MINOR;
+	/* PLL Freqs (MHz) */
+	_TGT_AP_PLL_CPU_FREQ,	// PLL_FREQ_CPU; /* 05, 06 */
+	_TGT_AP_PLL_BUS_FREQ,	// PLL_FREQ_BUS; /* 25, 26 */
+	_TGT_AP_PLL_MEM_FREQ,	// PLL_FREQ_MEM; /* 65, 66 */
+	_TGT_AP_PLL_USB_FREQ,	// PLL_FREQ_USB; /* 85, 86 */
+	/* DDR Cal */
+	0,			// DDR_CAL;
+	/* DDR_FLAGS */
+	DDR_FLAGS_ODT(_TGT_AP_DDR_ODT)	// 010 -- 120 Ohm
+#if (_TGT_AP_DDR_CLOCK < 200)
+	    | DDR_FLAGS_DLLOFF
+#endif
+#ifdef _TGT_AP_DDR_LOWPWR
+	    | DDR_FLAGS_LOWPWR
+#endif
+	    | DDR_FLAGS_RON(_TGT_AP_DDR_RON),	// 00 -- 40 Ohm
+	/* DDR_PARA */
+	DDR_PARA_CHIP_BITS(_TGT_AP_DDR_CHIP_BITS)
+	    | DDR_PARA_MEM_BITS(_TGT_AP_DDR_MEM_BITS)
+	    | DDR_PARA_BANK_BITS(_TGT_AP_DDR_BANK_BITS)
+	    | DDR_PARA_ROW_BITS(_TGT_AP_DDR_ROW_BITS )
+	    | DDR_PARA_COL_BITS(_TGT_AP_DDR_COL_BITS),
+
+	/* AP sysctrl */
+	_TGT_AP_CLK_CPU,	// CLK_CPU;
+	_TGT_AP_CLK_AXI,	// CLK_AXI;
+	_TGT_AP_CLK_GCG,	// CLK_GCG;
+	_TGT_AP_CLK_AHB1,	// CLK_AHB1;
+	_TGT_AP_CLK_APB1,	// CLK_APB1;
+	_TGT_AP_CLK_APB2,	// CLK_APB2;
+	_TGT_AP_CLK_MEM,	// CLK_MEM;
+	_TGT_AP_CLK_GPU,	// CLK_GPU;
+	_TGT_AP_CLK_VPU,	// CLK_VPU;
+	_TGT_AP_CLK_VOC,	// CLK_VOC;
+	_TGT_AP_CLK_SFLSH,	// CLK_SFLSH;
+	0,			// RESERVE;
+
+	/* DDR timings, defined in target */
+	DDR_CHAN_1_VALID_VAL,	// DDR_CHAN_1_VALID;
+	DDR_TIMING_100H_VAL,	// DDR_TIMING_100H;
+	DDR_TIMING_101H_VAL,	// DDR_TIMING_101H;
+	DDR_TIMING_102H_VAL,	// DDR_TIMING_102H;
+	DDR_TIMING_103H_VAL,	// DDR_TIMING_103H;
+	DDR_TIMING_104H_VAL,	// DDR_TIMING_104H;
+	DDR_TIMING_105H_VAL,	// DDR_TIMING_105H;
+	DDR_TIMING_106H_VAL,	// DDR_TIMING_106H;
+	DDR_TIMING_107H_VAL,	// DDR_TIMING_107H;
+	DDR_TIMING_108H_VAL,	// DDR_TIMING_108H;
+	DDR_TIMING_109H_VAL,	// DDR_TIMING_109H;
+	DDR_TIMING_10AH_VAL,	// DDR_TIMING_10AH;
+	DDR_TIMING_10BH_VAL,	// DDR_TIMING_10BH;
+	DDR_TIMING_10CH_VAL,	// DDR_TIMING_10CH;
+	DDR_TIMING_10DH_VAL,	// DDR_TIMING_10DH;
+	DDR_TIMING_10EH_VAL,	// DDR_TIMING_10EH;
+	DDR_TIMING_10FH_VAL,	// DDR_TIMING_10FH;
+
+	DDR_CHAN_2_VALID_VAL,	// DDR_CHAN_2_VALID;
+	DDR_TIMING_120H_VAL,	// DDR_TIMING_120H;
+	DDR_TIMING_121H_VAL,	// DDR_TIMING_121H;
+	DDR_TIMING_122H_VAL,	// DDR_TIMING_122H;
+	DDR_TIMING_123H_VAL,	// DDR_TIMING_123H;
+	DDR_TIMING_124H_VAL,	// DDR_TIMING_124H;
+	DDR_TIMING_125H_VAL,	// DDR_TIMING_125H;
+	DDR_TIMING_126H_VAL,	// DDR_TIMING_126H;
+	DDR_TIMING_127H_VAL,	// DDR_TIMING_127H;
+	DDR_TIMING_128H_VAL,	// DDR_TIMING_128H;
+	DDR_TIMING_129H_VAL,	// DDR_TIMING_129H;
+	DDR_TIMING_12AH_VAL,	// DDR_TIMING_12AH;
+	DDR_TIMING_12BH_VAL,	// DDR_TIMING_12BH;
+	DDR_TIMING_12CH_VAL,	// DDR_TIMING_12CH;
+	DDR_TIMING_12DH_VAL,	// DDR_TIMING_12DH;
+	DDR_TIMING_12EH_VAL,	// DDR_TIMING_12EH;
+	DDR_TIMING_12FH_VAL,	// DDR_TIMING_12FH;
+
+	DDR_CHAN_3_VALID_VAL,	// DDR_CHAN_3_VALID;
+	DDR_TIMING_140H_VAL,	// DDR_TIMING_140H;
+	DDR_TIMING_141H_VAL,	// DDR_TIMING_141H;
+	DDR_TIMING_142H_VAL,	// DDR_TIMING_142H;
+	DDR_TIMING_143H_VAL,	// DDR_TIMING_143H;
+	DDR_TIMING_144H_VAL,	// DDR_TIMING_144H;
+	DDR_TIMING_145H_VAL,	// DDR_TIMING_145H;
+	DDR_TIMING_146H_VAL,	// DDR_TIMING_146H;
+	DDR_TIMING_147H_VAL,	// DDR_TIMING_147H;
+	DDR_TIMING_148H_VAL,	// DDR_TIMING_148H;
+	DDR_TIMING_149H_VAL,	// DDR_TIMING_149H;
+	DDR_TIMING_14AH_VAL,	// DDR_TIMING_14AH;
+	DDR_TIMING_14BH_VAL,	// DDR_TIMING_14BH;
+	DDR_TIMING_14CH_VAL,	// DDR_TIMING_14CH;
+	DDR_TIMING_14DH_VAL,	// DDR_TIMING_14DH;
+	DDR_TIMING_14EH_VAL,	// DDR_TIMING_14EH;
+	DDR_TIMING_14FH_VAL,	// DDR_TIMING_14FH;
+
+	DDR_CHAN_4_VALID_VAL,	// DDR_CHAN_4_VALID;
+	DDR_TIMING_161H_VAL,	// DDR_TIMING_161H;
+	DDR_TIMING_162H_VAL,	// DDR_TIMING_162H;
+	DDR_TIMING_163H_VAL,	// DDR_TIMING_163H;
+	DDR_TIMING_164H_VAL,	// DDR_TIMING_164H;
+	DDR_TIMING_165H_VAL,	// DDR_TIMING_165H;
+	DDR_TIMING_166H_VAL,	// DDR_TIMING_166H;
+	DDR_TIMING_167H_VAL,	// DDR_TIMING_167H;
+	DDR_TIMING_168H_VAL,	// DDR_TIMING_168H;
+	DDR_TIMING_169H_VAL,	// DDR_TIMING_169H;
+	DDR_TIMING_16AH_VAL,	// DDR_TIMING_16AH;
+	DDR_TIMING_16BH_VAL,	// DDR_TIMING_16BH;
+	DDR_TIMING_16CH_VAL,	// DDR_TIMING_16CH;
+	DDR_TIMING_16DH_VAL,	// DDR_TIMING_16DH;
+	DDR_TIMING_16EH_VAL,	// DDR_TIMING_16EH;
+	DDR_TIMING_16FH_VAL,	// DDR_TIMING_16FH;
+
+	DDR_TIMING_160H_VAL,	// DDR_TIMING_160H;
+	DDR_TIMING_180H_VAL,	// DDR_TIMING_180H;
+	DDR_TIMING_181H_VAL,	// DDR_TIMING_181H;
+	DDR_TIMING_182H_VAL,	// DDR_TIMING_182H;
+	DDR_TIMING_183H_VAL,	// DDR_TIMING_183H;
+	DDR_TIMING_184H_VAL,	// DDR_TIMING_184H;
+	DDR_TIMING_185H_VAL,	// DDR_TIMING_185H;
+	DDR_TIMING_186H_VAL,	// DDR_TIMING_186H;
+	DDR_TIMING_187H_VAL,	// DDR_TIMING_187H;
+	DDR_TIMING_188H_VAL,	// DDR_TIMING_188H;
+	DDR_TIMING_189H_VAL,	// DDR_TIMING_189H;
+	DDR_TIMING_18AH_VAL,	// DDR_TIMING_18AH;
+	DDR_TIMING_18BH_VAL,	// DDR_TIMING_18BH;
+};
+
+const struct clock_config *get_default_clock_config(void)
+{
+#ifndef TARGET_TOOL
+	BUILD_BUG_ON(sizeof(struct clock_config) > AP_FACTORY_CLOCK_CFG_LEN);
+#endif
+
+	return &clock_default_config;
+}
+
diff --git a/board/rda/rda8850/clock_config.h b/board/rda/rda8850/clock_config.h
new file mode 100644
index 0000000000..57e31bb6d3
--- /dev/null
+++ b/board/rda/rda8850/clock_config.h
@@ -0,0 +1,130 @@
+#ifndef __CLOCK_CONFIG_H__
+#define __CLOCK_CONFIG_H__
+
+typedef unsigned long               UINT32;
+typedef unsigned short              UINT16;
+typedef long                        INT32;
+typedef short                       INT16;
+typedef unsigned char               UINT8;
+typedef char                        INT8;
+
+#define CLOCK_VER_MAJOR		2
+#define CLOCK_VER_MINOR		0
+
+struct clock_config {
+	/* Header */
+	UINT32 MAGIC;
+	UINT16 VERSION_MAJOR;
+	UINT16 VERSION_MINOR;
+	/* PLL Freqs (MHz) */
+	UINT32 PLL_FREQ_CPU;	/* 05, 06 */
+	UINT32 PLL_FREQ_BUS;	/* 25, 26 */
+	UINT32 PLL_FREQ_MEM;	/* 65, 66 */
+	UINT32 PLL_FREQ_USB;	/* 85, 86 */
+	/* DDR Flags */
+	UINT16 DDR_CAL;
+	UINT16 DDR_FLAGS;
+	UINT32 DDR_PARA;
+	/* AP sysctrl */
+	UINT16 CLK_CPU;
+	UINT16 CLK_AXI;
+	UINT16 CLK_GCG;
+	UINT16 CLK_AHB1;
+	UINT16 CLK_APB1;
+	UINT16 CLK_APB2;
+	UINT16 CLK_MEM;
+	UINT16 CLK_GPU;
+	UINT16 CLK_VPU;
+	UINT16 CLK_VOC;
+	UINT16 CLK_SFLSH;
+	UINT16 RESERVE;
+	/* DDR timings */
+	UINT16 DDR_CHAN_1_VALID;
+	UINT16 DDR_TIMING_100H;
+	UINT16 DDR_TIMING_101H;
+	UINT16 DDR_TIMING_102H;
+	UINT16 DDR_TIMING_103H;
+	UINT16 DDR_TIMING_104H;
+	UINT16 DDR_TIMING_105H;
+	UINT16 DDR_TIMING_106H;
+	UINT16 DDR_TIMING_107H;
+	UINT16 DDR_TIMING_108H;
+	UINT16 DDR_TIMING_109H;
+	UINT16 DDR_TIMING_10AH;
+	UINT16 DDR_TIMING_10BH;
+	UINT16 DDR_TIMING_10CH;
+	UINT16 DDR_TIMING_10DH;
+	UINT16 DDR_TIMING_10EH;
+	UINT16 DDR_TIMING_10FH;
+
+	UINT16 DDR_CHAN_2_VALID;
+	UINT16 DDR_TIMING_120H;
+	UINT16 DDR_TIMING_121H;
+	UINT16 DDR_TIMING_122H;
+	UINT16 DDR_TIMING_123H;
+	UINT16 DDR_TIMING_124H;
+	UINT16 DDR_TIMING_125H;
+	UINT16 DDR_TIMING_126H;
+	UINT16 DDR_TIMING_127H;
+	UINT16 DDR_TIMING_128H;
+	UINT16 DDR_TIMING_129H;
+	UINT16 DDR_TIMING_12AH;
+	UINT16 DDR_TIMING_12BH;
+	UINT16 DDR_TIMING_12CH;
+	UINT16 DDR_TIMING_12DH;
+	UINT16 DDR_TIMING_12EH;
+	UINT16 DDR_TIMING_12FH;
+
+	UINT16 DDR_CHAN_3_VALID;
+	UINT16 DDR_TIMING_140H;
+	UINT16 DDR_TIMING_141H;
+	UINT16 DDR_TIMING_142H;
+	UINT16 DDR_TIMING_143H;
+	UINT16 DDR_TIMING_144H;
+	UINT16 DDR_TIMING_145H;
+	UINT16 DDR_TIMING_146H;
+	UINT16 DDR_TIMING_147H;
+	UINT16 DDR_TIMING_148H;
+	UINT16 DDR_TIMING_149H;
+	UINT16 DDR_TIMING_14AH;
+	UINT16 DDR_TIMING_14BH;
+	UINT16 DDR_TIMING_14CH;
+	UINT16 DDR_TIMING_14DH;
+	UINT16 DDR_TIMING_14EH;
+	UINT16 DDR_TIMING_14FH;
+
+	UINT16 DDR_CHAN_4_VALID;
+	UINT16 DDR_TIMING_161H;
+	UINT16 DDR_TIMING_162H;
+	UINT16 DDR_TIMING_163H;
+	UINT16 DDR_TIMING_164H;
+	UINT16 DDR_TIMING_165H;
+	UINT16 DDR_TIMING_166H;
+	UINT16 DDR_TIMING_167H;
+	UINT16 DDR_TIMING_168H;
+	UINT16 DDR_TIMING_169H;
+	UINT16 DDR_TIMING_16AH;
+	UINT16 DDR_TIMING_16BH;
+	UINT16 DDR_TIMING_16CH;
+	UINT16 DDR_TIMING_16DH;
+	UINT16 DDR_TIMING_16EH;
+	UINT16 DDR_TIMING_16FH;
+
+	UINT16 DDR_TIMING_160H;
+	UINT16 DDR_TIMING_180H;
+	UINT16 DDR_TIMING_181H;
+	UINT16 DDR_TIMING_182H;
+	UINT16 DDR_TIMING_183H;
+	UINT16 DDR_TIMING_184H;
+	UINT16 DDR_TIMING_185H;
+	UINT16 DDR_TIMING_186H;
+	UINT16 DDR_TIMING_187H;
+	UINT16 DDR_TIMING_188H;
+	UINT16 DDR_TIMING_189H;
+	UINT16 DDR_TIMING_18AH;
+	UINT16 DDR_TIMING_18BH;
+};
+
+const struct clock_config *get_default_clock_config(void);
+
+#endif
diff --git a/board/rda/rda8850/config.mk b/board/rda/rda8850/config.mk
new file mode 100644
index 0000000000..ec124aff34
--- /dev/null
+++ b/board/rda/rda8850/config.mk
@@ -0,0 +1,11 @@
+#
+#the spl code should not exceed the SPL_MAX_SIZE,and if 
+#the spl don't up to the max size, paddint the last with
+#zero(or 0xff?)
+
+#48kbytes, 48*1024
+#SPL_APPENDING_TO	:= 48
+#SPL_MAX_SIZE	:= 49512
+
+# space for spl(48KiB) & mtd partition table(24KiB)
+SPL_APPENDING_TO   := 72
diff --git a/board/rda/rda8850/ddr3.c b/board/rda/rda8850/ddr3.c
new file mode 100644
index 0000000000..e3628005ac
--- /dev/null
+++ b/board/rda/rda8850/ddr3.c
@@ -0,0 +1,516 @@
+#include <common.h>
+#include <asm/arch/rda_iomap.h>
+
+#include "ddr3.h"
+#include "ddr3_init.h"
+#include "tgt_ap_clock_config.h"
+
+#pragma GCC push_options
+#pragma GCC optimize ("O0")
+
+#define DDR_TYPE _TGT_AP_DDR_TYPE
+
+#define DF_DELAY  (0x10000)
+
+#define DMC_REG_BASE RDA_DMC400_BASE
+#define PHY_REG_BASE RDA_DDRPHY_BASE
+
+#define  PHY_RDLAT          0
+#define  PHYWRDATA          1
+#define  STA                3
+#define  CLKSEL             4
+#define  PSSTART            5
+#define  PSDONE             6
+#define  LOCKED             6
+#define  CTRL_DELAY         7
+#define  RDELAY_SEL         8
+#define  WDELAY_SEL         9
+#define  PHY_RESET          10
+#define  RESET_DDR3         11
+#define  ODT_DELAY          12
+#define  DDR3_USED          13
+#define  WRITE_ENABLE_LAT   14
+#define  WRITE_DATA_LAT     15
+#define  DQOUT_ENABLE_LAT   16
+#define  DATA_ODT_ENABLE_REG	20
+#define  DATA_WRITE_ENABLE_REG  48   
+#define  DMC_READY	128
+
+#define ARRAY_NUM(n) (sizeof(n))/(sizeof(n[0]))
+
+#if (DDR_TYPE == 1)
+static dmc_reg_t dmc_reg_cfg[] = {
+	{T_REFI,	0x186,		0x186},
+	{T_RFC,		0x230024,	0x230024},
+	{T_RFC,		0x540024,	0x540024},
+	{T_MRR,		0x2,		0x2},
+	{T_MRW,		0x5,		0x5},
+	{T_RCD,		0x8,		0x8},
+	{T_RAS,		0x11,		0x11},
+	{T_RP,		0x8,		0x8},
+	{T_RPALL,	0x9,		0x9},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0x4,		0x4},
+	{T_RTW,		0xb,		0xb},
+	{T_RTP,		0x6,		0x6},
+	{T_WR,		0xe,		0xe},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTW,		0x40000,	0x40000},
+	{RD_LATENCY,	0x6,		0x6},
+	{WR_LATENCY,	0x3,		0x3},
+	{T_RDDATA_EN,	0x3,		0x3},
+	{T_PHYWRLAT,	0x101,		0x101},
+	{T_PHYWRLAT,	0x101,		0x101},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0x80003,	0x80003},
+	{T_ESR,		0x6,		0x6},
+	{T_XSR,		0x1000058,	0x1000058},
+	{T_XSR,		0x580058,	0x580058},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{T_EP,		0x5,		0x5},
+	{RDLVL_CTRL,	0x1010,		0x1010},
+	{RDLVL_CTRL,	0x1110,		0x1110},
+	{RDLVL_CTRL,	0x11110,	0x11110},
+	{REFRESH_CTRL,	0x0,		0x0},
+	{REFRESH_CTRL,	0x0,		0x0},
+	{ECC_CTRL,	0x0,		0x0},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+};
+#elif (DDR_TYPE == 2)
+static dmc_reg_t dmc_reg_cfg[] = {
+	{T_REFI,	0x3f,		0x3f},
+	{T_RFC,		0x230024,	0x230024},
+	{T_RFC,		0x540024,	0x540024},
+	{T_MRR,		0x2,		0x2},
+	{T_MRW,		0x5,		0x5},
+	{T_RCD,		0x8,		0x8},
+	{T_RAS,		0x11,		0x11},
+	{T_RP,		0x8,		0x8},
+	{T_RPALL,	0x9,		0x9},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0x4,		0x4},
+	{T_RTW,		0xb,		0xb},
+	{T_RTP,		0x6,		0x6},
+	{T_WR,		0xe,		0xe},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTW,		0x40000,	0x40000},
+	{RD_LATENCY,	0x6,		0x6},
+	{WR_LATENCY,	0x3,		0x3},
+	{T_RDDATA_EN,	0x3,		0x3},
+	{T_PHYWRLAT,	0x101,		0x101},
+	{T_PHYWRLAT,	0x103,		0x103},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0x80003,	0x80003},
+	{T_ESR,		0x6,		0x6},
+	{T_XSR,		0x1000058,	0x1000058},
+	{T_XSR,		0x580058,	0x580058},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{T_EP,		0x5,		0x5},
+	{RDLVL_CTRL,	0x1010,		0x1010},
+	{RDLVL_CTRL,	0x1110,		0x1110},
+	{RDLVL_CTRL,	0x11110,	0x11110},
+	{REFRESH_CTRL,	0x1,		0x1},
+	{ECC_CTRL,	0x0,		0x0},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+};
+#elif (DDR_TYPE == 3)
+static dmc_reg_t dmc_reg_cfg[] = {
+	{QOSX_CTRL7,	0x08, 		0x08},
+	{TURNAROUND_PRIO,0x1A, 		0x0},
+	{HIT_PRIO,	0x1A, 		0x0},
+	{T_REFI,	0x186,		0x3f},
+	{QUEUE_CTRL,	0xffff,		0x0},
+	{T_RFC,		0x23008c,	0x23008c},
+	{T_RFC,		0x8c008c,	0x8c008c},
+	{T_MRR,		0x4,		0x4},
+	{T_MRW,		0xc,		0xc},
+	{T_RCD,		0x6,		0x6},
+	{T_RAS,		0xf,		0xf},
+	{T_RP,		0x6,		0x6},
+	{T_RPALL,	0x6,		0x5},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0x6,		0x6},
+//	{T_RTW,		0x7,		0x6},
+	{T_RTW,		0x0c,		0x6},// turn for now
+//	{T_RTW,		0x1f,		0x1f},//for low speed
+	{T_RTP,		0x4,		0x4},
+	{T_WR,		0xf,		0x10},
+	{T_WTR,		0x4000d,	0x4000d},
+	{T_WTR,		0x6000d,	0x6000f},
+//	{T_WTR,		0x6001f,	0x6001f},//for low speed
+	{T_WTW,		0x60000,	0x60000},
+	{RD_LATENCY,	0x5,		0x5},
+	{WR_LATENCY,	0x5,		0x5},
+	{T_RDDATA_EN,	0x8,		0x2},
+	{T_PHYWRLAT,	0x104,		0x105},
+	{T_PHYWRLAT,	0x104,		0x105},
+	{T_EP,		0x3,		0x3},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0xa0003,	0xa0003},
+	{T_ESR,		0x4,		0x4},
+	{T_XSR,		0x1000090,	0x1000090},
+	{T_XSR,		0x2000090,	0x2000090},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{ECC_CTRL,	0x0,		0x0},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+};
+#else
+#error "Wrong DDR Type"
+#endif
+
+void config_ddr_phy(UINT16 flag)
+{
+	int wait_idle;
+	UINT16 __attribute__((unused)) dll_off;
+
+	wait_idle = DF_DELAY + 16;
+	dll_off = flag & DDR_FLAGS_DLLOFF;
+
+	while (wait_idle--);
+
+#if (DDR_TYPE == 1)
+	*((volatile UINT32*)(PHY_REG_BASE + CTRL_DELAY * 4)) = 1;
+	printf("ddr1 phy init done!\n");
+#elif (DDR_TYPE ==2)
+	*((volatile UINT32*)(PHY_REG_BASE + 129 * 4)) = 0;
+	*((volatile UINT32*)(PHY_REG_BASE + WDELAY_SEL * 4)) = 3;
+	*((volatile UINT32*)(PHY_REG_BASE + DQOUT_ENABLE_LAT * 4)) = 1;
+	*((volatile UINT32*)(PHY_REG_BASE + 48 *4))  = 0xf;
+	*((volatile UINT32*)(PHY_REG_BASE + 20 *4))  = 0xf;
+	printf("ddr2 phy init done!\n");
+#else
+	*((volatile UINT32*)(PHY_REG_BASE + 128 *4))  = 0x0;
+	*((volatile UINT32*)(PHY_REG_BASE + RESET_DDR3 * 4)) = 1;
+
+	if (dll_off)
+		*((volatile UINT32*)(PHY_REG_BASE + WRITE_DATA_LAT * 4)) = 1;
+
+	*((volatile UINT32*)(PHY_REG_BASE + DDR3_USED * 4)) = 1;
+	*((volatile UINT32*)(PHY_REG_BASE + WDELAY_SEL * 4)) = 3;
+
+	if (!dll_off){
+		*((volatile UINT32*)(PHY_REG_BASE + PHY_RDLAT * 4)) = 7;
+		*((volatile UINT32*)(PHY_REG_BASE + CTRL_DELAY * 4)) =2;
+		*((volatile UINT32*)(PHY_REG_BASE + WRITE_ENABLE_LAT * 4)) =2;
+		*((volatile UINT32*)(PHY_REG_BASE + WRITE_DATA_LAT * 4)) = 3;
+		*((volatile UINT32*)(PHY_REG_BASE + DQOUT_ENABLE_LAT * 4)) = 3;
+	}else
+		*((volatile UINT32*)(PHY_REG_BASE + DQOUT_ENABLE_LAT * 4)) = 1;
+
+	*((volatile UINT32*)(PHY_REG_BASE + DATA_ODT_ENABLE_REG *4))  = 0xf;
+	*((volatile UINT32*)(PHY_REG_BASE + DATA_WRITE_ENABLE_REG *4))  = 0xf;
+	
+	serial_puts("ddr3 phy init done!\n");
+#endif
+}
+
+void config_dmc400(UINT16 flag, UINT32 para)
+{
+	int i, wait_idle;
+	UINT32 val, tmp;
+	volatile UINT32 *addr;
+	UINT16 __attribute__((unused)) dll_off, lpw, odt, ron;
+	UINT32 mem_width, col_bits, row_bits, bank_bits;
+
+	dll_off = flag & DDR_FLAGS_DLLOFF;
+	lpw = flag & DDR_FLAGS_LOWPWR;
+	odt = (flag & DDR_FLAGS_ODT_MASK) >> DDR_FLAGS_ODT_SHIFT;
+	ron = (flag & DDR_FLAGS_RON_MASK) >> DDR_FLAGS_RON_SHIFT;
+	mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;
+	bank_bits = (para & DDR_PARA_BANK_BITS_MASK) >> DDR_PARA_BANK_BITS_SHIFT;
+	row_bits = (para & DDR_PARA_ROW_BITS_MASK) >> DDR_PARA_ROW_BITS_SHIFT;
+	col_bits = (para & DDR_PARA_COL_BITS_MASK) >> DDR_PARA_COL_BITS_SHIFT;
+
+
+	wait_idle = 0x4e;
+	while (wait_idle--);
+
+	for (i=0; i<ARRAY_NUM(dmc_reg_cfg); i++) {
+		addr = (volatile UINT32*)(DMC_REG_BASE + dmc_reg_cfg[i].reg_offset);
+		if (dll_off)
+			val = dmc_reg_cfg[i].dll_off_val;
+		else
+			val = dmc_reg_cfg[i].dll_on_val;
+
+		*addr = val;
+		wait_idle = 0x5;
+		while (wait_idle--);
+	}
+
+#if (DDR_TYPE == 3)
+	//config low power control register
+	if (lpw) {
+		addr = (volatile UINT32*)(DMC_REG_BASE + LOWPWR_CTRL);//0x20
+		*addr = 0x48;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_ESR);//0x260
+		*addr = 0xa;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_XSR);//0x264
+		*addr = 0x200;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_SRCKD);//0x268
+		*addr = 0xa;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_CKSRD);//0x26C
+		*addr = 0xa;
+		wait_idle = 0x5;
+		while (wait_idle--);	
+	}
+#elif (DDR_TYPE == 2)
+	addr = (volatile UINT32*)(DMC_REG_BASE + LOWPWR_CTRL);//0x20
+	*addr = 0x38;
+	wait_idle = 0x5;
+	while (wait_idle--);
+#endif
+
+	//config format control register
+	addr = (volatile UINT32*)(DMC_REG_BASE + FORMAT_CTRL);
+	val = *addr;
+	val &= ~0xf;
+	if (mem_width == 2)
+		val |= 0x2; //for 32bit DDR
+	else if ((mem_width == 1) || (mem_width == 0))
+		val |= 0x1; //for 16bit & 8bit DDR
+	else
+		printf("unsupported DDR width: %lx\n", mem_width);
+	*addr = val;
+
+	printf("format ctrl value: %lx\n", val);
+
+	wait_idle = 0x1d;
+	while (wait_idle--);
+
+	//config address control register
+	addr = (volatile UINT32*)(DMC_REG_BASE + ADDR_CTRL);
+	if (mem_width == 2)
+		tmp = col_bits; //for 32bit
+	else if (mem_width == 1)
+		tmp = col_bits - 1; //for 16bit
+	else if (mem_width == 0)
+		tmp = col_bits - 2; //for 8bit
+	else {
+		printf("unsupported DDR width: %lx\n", mem_width);
+		tmp = col_bits;
+	}
+	val = (bank_bits << 16) | (row_bits << 8) | tmp;
+
+	*addr = val;
+
+	printf("address ctrl value: %lx\n", val);
+	wait_idle = 0x5;
+	while (wait_idle--);
+
+	//config decode control register
+	addr = (volatile UINT32*)(DMC_REG_BASE + DECODE_CTRL);
+	tmp = 12 - (8 + col_bits + mem_width);
+	if (tmp < 8)
+		val = tmp << 4;
+	else
+		printf("unsupported stripe decode: %lx\n", tmp);
+	*addr = val;
+
+	printf("decode ctrl value: %lx\n", val);
+	wait_idle = 0x6;
+	while (wait_idle--);
+
+	wait_idle = DF_DELAY;
+	while (wait_idle--);
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+	*addr = 0x0;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0;
+#elif (DDR_TYPE == 2)
+	val = 0;
+#else
+	//config MR2
+	if (dll_off)
+		val = 0x10020008;
+	else
+		val = 0x10020000;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x20000000;
+#elif (DDR_TYPE == 2)
+	val = 0x1000003f;
+#else
+	//config MR3
+	val = 0x10030000;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x30000000;
+#elif (DDR_TYPE == 2)
+	val = 0x1000ff0a;
+#else
+	//config MR1 ODT [9,6,2] RON [5,1] DLLOFF [0]
+	val = 0x10010000;
+	val |= (odt & 0x4)<<7 | (odt & 0x2)<<5 | (odt & 0x1)<<2;
+	val |= (ron & 0x2)<<4 | (ron & 0x1)<<1;
+	if (dll_off)
+		val |= 0x1;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x30000000;
+#elif (DDR_TYPE == 2)
+	val = 0x10008301;
+#else
+	//config MR0
+	val = 0x10000520;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x10000033;
+#elif (DDR_TYPE == 2)
+	val = 0x10000402;//0ld 0x10000102
+#else
+	val = 0x50000400;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x10020000;
+#elif (DDR_TYPE == 2)
+	val = 0x30000000;
+#else
+	val = 0x30000000;
+#endif
+	*addr = val;
+
+#if (DDR_TYPE == 2)
+/* zhangli for MCP */
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+	*addr = 0x10000103;
+	wait_idle = DF_DELAY + 0x9;
+	while (wait_idle--);
+#endif
+
+#if (DDR_TYPE == 2)
+	addr = (volatile UINT32*)(DMC_REG_BASE + MEMC_CMD);
+	val = 0x4;
+	*addr = val;
+#endif
+
+	//config ECC control
+	wait_idle = 0x6;
+	while (wait_idle--);
+	addr = (volatile UINT32*)(DMC_REG_BASE + ECC_CTRL);
+	val = 0x0;
+	*addr = val;
+	wait_idle = 0x8;
+	while (wait_idle--);
+
+	//config MEMC CMD
+	addr = (volatile UINT32*)(DMC_REG_BASE + MEMC_CMD);
+	val = 0x3;
+	*addr = val;
+
+	//READ MEMC STATUS
+	addr = (volatile UINT32*)(DMC_REG_BASE + MEMC_STATUS);
+	val = 0;
+	do {
+		val = *addr;
+		//printf("MEMC_STATUS value: %x\n", val);
+	} while (val != 3);
+}
+
+void axi_prio_init(void)
+{
+	*(volatile UINT32*)(0x20900100) = 0xaa0000aa;
+	*(volatile UINT32*)(0x21054100) = 0x00000008;
+	*(volatile UINT32*)(0x21054104) = 0x00000008;
+}
+
+void axi_outstandings_init(void)
+{
+	*(volatile UINT32*)(0x2105110C) = 0x00000060;
+	*(volatile UINT32*)(0x21051110) = 0x00000300;
+}
+
+int ddr_init(UINT16 flags, UINT32 para)
+{
+	UINT16 dll_off;
+	UINT32 mem_width;
+
+	axi_prio_init();
+	axi_outstandings_init();
+
+	dll_off = flags & DDR_FLAGS_DLLOFF;
+	mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;
+
+	switch (mem_width) {
+		case 0:
+			printf("8bit ");
+			break;
+		case 1:
+			printf("16bit ");
+			break;
+		case 2:
+			printf("32bit ");
+			break;
+	}
+	if (dll_off)
+		printf("dll-off Mode ...\n");
+	else
+		printf("dll-on Mode ...\n");
+
+	config_ddr_phy(flags);
+	config_dmc400(flags, para);
+	printf("dram init done ...\n");
+
+	return 0;
+}
+
diff --git a/board/rda/rda8850/ddr3.h b/board/rda/rda8850/ddr3.h
new file mode 100644
index 0000000000..7481954144
--- /dev/null
+++ b/board/rda/rda8850/ddr3.h
@@ -0,0 +1,50 @@
+#ifndef _SYS_DDR3_H_
+#define _SYS_DDR3_H_
+
+#include "clock_config.h"
+
+/*
+ * defination of ddr flags
+ */
+/* [Debug] DLL off mode, 0 is dll on mode */
+#define DDR_FLAGS_DLLOFF               0x8000
+/* [Debug] LowSpeed mode*/
+#define DDR_FLAGS_RESERVE              0x4000
+/* DDR LowPower mode */
+#define DDR_FLAGS_LOWPWR               0x2000
+/* ODT: 000--Null 001--60 010--120 011--40 100--20 101--30 */
+#define DDR_FLAGS_ODT(n)               (((n)<<0)&0x0007)
+#define DDR_FLAGS_ODT_SHIFT            0
+#define DDR_FLAGS_ODT_MASK             0x0007
+/* RON: 00--40 01--30 */
+#define DDR_FLAGS_RON(n)               (((n)<<3)&0x0018)
+#define DDR_FLAGS_RON_SHIFT            3
+#define DDR_FLAGS_RON_MASK             0x0018
+
+/*
+ * defination of ddr parameters
+ */
+#define DDR_PARA_CHIP_BITS(n)          (((n)<<0)&0x00000003)
+#define DDR_PARA_CHIP_BITS_SHIFT       0
+#define DDR_PARA_CHIP_BITS_MASK        0x00000003
+/* memory width 0--8bit 1--16bit 2--32bit */
+#define DDR_PARA_MEM_BITS(n)           (((n)<<2)&0x0000000c)
+#define DDR_PARA_MEM_BITS_SHIFT        2
+#define DDR_PARA_MEM_BITS_MASK         0x0000000c
+/* 2--4banks 3--8banks */
+#define DDR_PARA_BANK_BITS(n)          (((n)<<4)&0x000000f0)
+#define DDR_PARA_BANK_BITS_SHIFT       4
+#define DDR_PARA_BANK_BITS_MASK        0x000000f0
+/* 2--13rbs 3--14rbs 4--15rbs 5--16rbs */
+#define DDR_PARA_ROW_BITS(n)           (((n)<<8)&0x00000f00)
+#define DDR_PARA_ROW_BITS_SHIFT        8
+#define DDR_PARA_ROW_BITS_MASK         0x00000f00
+/* 0--8cbs 1--9cbs 2--10cbs 3--11cbs 4--12cbs */
+#define DDR_PARA_COL_BITS(n)           (((n)<<12)&0x0000f000)
+#define DDR_PARA_COL_BITS_SHIFT        12
+#define DDR_PARA_COL_BITS_MASK         0x0000f000
+
+int ddr_init(UINT16 flags, UINT32 para);
+
+#endif /* _SYS_DDR3_H_ */
+
diff --git a/board/rda/rda8850/ddr3_8810.c b/board/rda/rda8850/ddr3_8810.c
new file mode 100644
index 0000000000..d665019b8d
--- /dev/null
+++ b/board/rda/rda8850/ddr3_8810.c
@@ -0,0 +1,540 @@
+#include <common.h>
+#include <asm/arch/rda_iomap.h>
+
+#include "ddr3.h"
+#include "ddr3_init.h"
+#include "tgt_ap_clock_config.h"
+
+#pragma GCC push_options
+#pragma GCC optimize ("O0")
+
+#define DDR_TYPE _TGT_AP_DDR_TYPE
+
+#define DF_DELAY  (0x10000)
+
+#define DMC_REG_BASE RDA_DMC400_BASE
+#define PHY_REG_BASE RDA_DDRPHY_BASE
+
+#define  PHY_RDLAT          0
+#define  PHYWRDATA          1
+#define  STA                3
+#define  CLKSEL             4
+#define  PSSTART            5
+#define  PSDONE             6
+#define  LOCKED             6
+#define  CTRL_DELAY         7
+#define  RDELAY_SEL         8
+#define  WDELAY_SEL         9
+#define  PHY_RESET          10
+#define  RESET_DDR3         11
+#define  ODT_DELAY          12
+#define  DDR3_USED          13
+#define  WRITE_ENABLE_LAT   14
+#define  WRITE_DATA_LAT     15
+#define  DQOUT_ENABLE_LAT   16
+
+#define ARRAY_NUM(n) (sizeof(n))/(sizeof(n[0]))
+
+#if (DDR_TYPE == 1)
+static dmc_reg_t dmc_reg_cfg[] = {
+	{T_REFI,	0x186,		0x186},
+	{T_RFC,		0x230024,	0x230024},
+	{T_RFC,		0x540024,	0x540024},
+	{T_MRR,		0x2,		0x2},
+	{T_MRW,		0x5,		0x5},
+	{T_RCD,		0x8,		0x8},
+	{T_RAS,		0x11,		0x11},
+	{T_RP,		0x8,		0x8},
+	{T_RPALL,	0x9,		0x9},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0x4,		0x4},
+	{T_RTW,		0xb,		0xb},
+	{T_RTP,		0x6,		0x6},
+	{T_WR,		0xe,		0xe},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTW,		0x40000,	0x40000},
+	{RD_LATENCY,	0x6,		0x6},
+	{WR_LATENCY,	0x3,		0x3},
+	{T_RDDATA_EN,	0x3,		0x3},
+	{T_PHYWRLAT,	0x101,		0x101},
+	{T_PHYWRLAT,	0x101,		0x101},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0x80003,	0x80003},
+	{T_ESR,		0x6,		0x6},
+	{T_XSR,		0x1000058,	0x1000058},
+	{T_XSR,		0x580058,	0x580058},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{T_EP,		0x5,		0x5},
+	{RDLVL_CTRL,	0x1010,		0x1010},
+	{RDLVL_CTRL,	0x1110,		0x1110},
+	{RDLVL_CTRL,	0x11110,	0x11110},
+	{REFRESH_CTRL,	0x0,		0x0},
+	{REFRESH_CTRL,	0x0,		0x0},
+	{ECC_CTRL,	0x0,		0x0},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+};
+#elif (DDR_TYPE == 2)
+static dmc_reg_t dmc_reg_cfg[] = {
+	{T_REFI,	0x3f,		0x3f},
+	{T_RFC,		0x230024,	0x230024},
+	{T_RFC,		0x540024,	0x540024},
+	{T_MRR,		0x2,		0x2},
+	{T_MRW,		0x5,		0x5},
+	{T_RCD,		0x8,		0x8},
+	{T_RAS,		0x11,		0x11},
+	{T_RP,		0x8,		0x8},
+	{T_RPALL,	0x9,		0x9},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0x4,		0x4},
+	{T_RTW,		0xb,		0xb},
+	{T_RTP,		0x6,		0x6},
+	{T_WR,		0xe,		0xe},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTR,		0x4000b,	0x4000b},
+	{T_WTW,		0x40000,	0x40000},
+	{RD_LATENCY,	0x6,		0x6},
+	{WR_LATENCY,	0x3,		0x3},
+	{T_RDDATA_EN,	0x3,		0x3},
+	{T_PHYWRLAT,	0x101,		0x101},
+	{T_PHYWRLAT,	0x103,		0x103},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0x80003,	0x80003},
+	{T_ESR,		0x6,		0x6},
+	{T_XSR,		0x1000058,	0x1000058},
+	{T_XSR,		0x580058,	0x580058},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{T_EP,		0x5,		0x5},
+	{RDLVL_CTRL,	0x1010,		0x1010},
+	{RDLVL_CTRL,	0x1110,		0x1110},
+	{RDLVL_CTRL,	0x11110,	0x11110},
+	{REFRESH_CTRL,	0x1,		0x1},
+	{ECC_CTRL,	0x0,		0x0},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+};
+#elif (DDR_TYPE == 3)
+static dmc_reg_t dmc_reg_cfg[] = {
+	{T_REFI,	0x186,		0x3f},
+	{T_RFC,		0x23008c,	0x23008c},
+	{T_RFC,		0x8c008c,	0x8c008c},
+	{T_MRR,		0x4,		0x4},
+	{T_MRW,		0xc,		0xc},
+	{T_RCD,		0x6,		0x5},
+	{T_RAS,		0xf,		0xf},
+	{T_RP,		0x6,		0x5},
+	{T_RPALL,	0x6,		0x5},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0x6,		0x6},
+//	{T_RTW,		0x7,		0x6},
+	{T_RTW,		0x0e,		0x0c},// turn for now
+//	{T_RTW,		0x1f,		0x1f},//for low speed
+	{T_RTP,		0x4,		0x4},
+	{T_WR,		0xf,		0x10},
+	{T_WTR,		0x4000d,	0x4000d},
+	{T_WTR,		0x6000d,	0x6000f},
+//	{T_WTR,		0x6001f,	0x6001f},//for low speed
+	{T_WTW,		0x60000,	0x60000},
+	{RD_LATENCY,	0x5,		0x5},
+	{WR_LATENCY,	0x5,		0x5},
+	{T_RDDATA_EN,	0x8,		0x1},
+	{T_PHYWRLAT,	0x103,		0x103},
+	{T_PHYWRLAT,	0x103,		0x104},
+	{T_EP,		0x3,		0x3},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0xa0003,	0xa0003},
+	{T_ESR,		0x4,		0x4},
+	{T_XSR,		0x1000090,	0x1000090},
+	{T_XSR,		0x2000090,	0x2000090},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{ECC_CTRL,	0x0,		0x0},
+	{QOSX_CTRL7,	0x0f, 		0x0f},
+	{TURNAROUND_PRIO,0x1A, 		0x1A},
+	{HIT_PRIO,	0x1A, 		0x1A},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ADDR_CTRL,	0x30200,	0x30200},
+};
+#else
+#error "Wrong DDR Type"
+#endif
+
+void config_ddr_phy(UINT16 flag)
+{
+	int wait_idle;
+	UINT16 dll_off;
+
+	wait_idle = DF_DELAY + 16;
+	dll_off = flag & DDR_FLAGS_DLLOFF;
+
+	while (wait_idle--);
+
+#if (DDR_TYPE == 1)
+	*((volatile UINT32*)(PHY_REG_BASE + CTRL_DELAY * 4)) = 1;
+	printf("ddr1 phy init done!\n");
+#elif (DDR_TYPE ==2)
+	*((volatile UINT32*)(PHY_REG_BASE + 129 * 4)) = 0;
+	*((volatile UINT32*)(PHY_REG_BASE + WDELAY_SEL * 4)) = 3;
+	*((volatile UINT32*)(PHY_REG_BASE + DQOUT_ENABLE_LAT * 4)) = 1;
+	*((volatile UINT32*)(PHY_REG_BASE + 48 *4))  = 0xf;
+	*((volatile UINT32*)(PHY_REG_BASE + 20 *4))  = 0xf;
+	printf("ddr2 phy init done!\n");
+#else
+	*((volatile UINT32*)(PHY_REG_BASE + RESET_DDR3 * 4)) = 1;
+	*((volatile UINT32*)(PHY_REG_BASE + WRITE_DATA_LAT * 4)) = 1;
+	*((volatile UINT32*)(PHY_REG_BASE + DDR3_USED * 4)) = 1;
+	if (!dll_off)
+	*((volatile UINT32*)(PHY_REG_BASE + RDELAY_SEL * 4)) = 2;
+	*((volatile UINT32*)(PHY_REG_BASE + WDELAY_SEL * 4)) = 3;
+	*((volatile UINT32*)(PHY_REG_BASE + DQOUT_ENABLE_LAT * 4)) = 1;
+	*((volatile UINT32*)(PHY_REG_BASE + 48 *4))  = (3<<2);
+	*((volatile UINT32*)(PHY_REG_BASE + 20 *4))  = (3<<2);
+	printf("ddr3 phy init done!\n");
+#endif
+}
+
+void config_dmc400(UINT16 flag, UINT32 para)
+{
+	int i, wait_idle;
+	UINT32 val, tmp;
+	volatile UINT32 *addr;
+	UINT16 dll_off, lpw, odt, ron;
+	UINT32 mem_width, col_bits, row_bits, bank_bits;
+
+	dll_off = flag & DDR_FLAGS_DLLOFF;
+	lpw = flag & DDR_FLAGS_LOWPWR;
+	odt = (flag & DDR_FLAGS_ODT_MASK) >> DDR_FLAGS_ODT_SHIFT;
+	ron = (flag & DDR_FLAGS_RON_MASK) >> DDR_FLAGS_RON_SHIFT;
+	mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;
+	bank_bits = (para & DDR_PARA_BANK_BITS_MASK) >> DDR_PARA_BANK_BITS_SHIFT;
+	row_bits = (para & DDR_PARA_ROW_BITS_MASK) >> DDR_PARA_ROW_BITS_SHIFT;
+	col_bits = (para & DDR_PARA_COL_BITS_MASK) >> DDR_PARA_COL_BITS_SHIFT;
+
+
+	wait_idle = 0x4e;
+	while (wait_idle--);
+
+	for (i=0; i<ARRAY_NUM(dmc_reg_cfg); i++) {
+		addr = (volatile UINT32*)(DMC_REG_BASE + dmc_reg_cfg[i].reg_offset);
+		if (dll_off)
+			val = dmc_reg_cfg[i].dll_off_val;
+		else
+			val = dmc_reg_cfg[i].dll_on_val;
+
+		*addr = val;
+		wait_idle = 0x5;
+		while (wait_idle--);
+	}
+
+#if (DDR_TYPE == 3)
+	//config low power control register
+	if (lpw) {
+		addr = (volatile UINT32*)(DMC_REG_BASE + LOWPWR_CTRL);//0x20
+		*addr = 0x48;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_ESR);//0x260
+		*addr = 0xa;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_XSR);//0x264
+		*addr = 0x200;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_SRCKD);//0x268
+		*addr = 0xa;
+		wait_idle = 0x5;
+		while (wait_idle--);
+
+		addr = (volatile UINT32*)(DMC_REG_BASE + T_CKSRD);//0x26C
+		*addr = 0xa;
+		wait_idle = 0x5;
+		while (wait_idle--);	
+	}
+#elif (DDR_TYPE == 2)
+	addr = (volatile UINT32*)(DMC_REG_BASE + LOWPWR_CTRL);//0x20
+	*addr = 0x38;
+	wait_idle = 0x5;
+	while (wait_idle--);
+#endif
+
+	//config format control register
+	addr = (volatile UINT32*)(DMC_REG_BASE + FORMAT_CTRL);
+#if (DDR_TYPE == 1)
+	val = 0x22000202;
+#elif (DDR_TYPE == 2)
+	val = 0x22000202;
+#else
+	val = *addr;
+	val &= ~0xf;
+	if (mem_width == 2)
+		val |= 0x2; //for 32bit DDR
+	else if ((mem_width == 1) || (mem_width == 0))
+		val |= 0x1; //for 16bit & 8bit DDR
+	else
+		printf("unsupported DDR width: %lx\n", mem_width);
+#endif
+	*addr = val;
+
+	printf("format ctrl value: %lx\n", val);
+
+	wait_idle = 0x1d;
+	while (wait_idle--);
+
+	//config address control register
+	addr = (volatile UINT32*)(DMC_REG_BASE + ADDR_CTRL);
+#if (DDR_TYPE == 1)
+	val = 0x20302;
+#elif (DDR_TYPE == 2)
+	val = 0x30200;
+#else
+	if (mem_width == 2)
+		tmp = col_bits; //for 32bit
+	else if (mem_width == 1)
+		tmp = col_bits - 1; //for 16bit
+	else if (mem_width == 0)
+		tmp = col_bits - 2; //for 8bit
+	else {
+		printf("unsupported DDR width: %lx\n", mem_width);
+		tmp = col_bits;
+	}
+
+	val = (bank_bits << 16) | (row_bits << 8) | tmp;
+#endif
+	*addr = val;
+
+	printf("address ctrl value: %lx\n", val);
+	wait_idle = 0x5;
+	while (wait_idle--);
+
+#if (DDR_TYPE == 2)
+	addr = (volatile UINT32*)(DMC_REG_BASE + ADDR_CTRL);
+
+	val = 0x30301;
+
+	*addr = val;
+
+	printf("address ctrl 2 value: %lx\n", val);
+	wait_idle = 0x5;
+	while (wait_idle--);
+#endif
+
+	//config decode control register
+	addr = (volatile UINT32*)(DMC_REG_BASE + DECODE_CTRL);
+#if (DDR_TYPE == 1)
+	val = 0x00;
+#elif (DDR_TYPE == 2)
+	val = 0x50;
+#else
+	tmp = 12 - (8 + col_bits + mem_width);
+	if (tmp < 8)
+		val = tmp << 4;
+	else
+		printf("unsupported stripe decode: %lx\n", tmp);
+#endif
+	*addr = val;
+	wait_idle = 0x6;
+	while (wait_idle--);
+
+#if (DDR_TYPE == 2)
+	addr = (volatile UINT32*)(DMC_REG_BASE + DECODE_CTRL);
+	val = 0x10;
+	*addr = val;
+	wait_idle = 0x6;
+	while (wait_idle--);
+#endif	
+
+	wait_idle = DF_DELAY;
+	while (wait_idle--);
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+	*addr = 0x0;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0;
+#elif (DDR_TYPE == 2)
+	val = 0;
+#else
+	//config MR2
+	if (dll_off)
+		val = 0x10020008;
+	else
+		val = 0x10020000;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x6;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x20000000;
+#elif (DDR_TYPE == 2)
+	val = 0x1000003f;
+#else
+	//config MR3
+	val = 0x10030000;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x30000000;
+#elif (DDR_TYPE == 2)
+	val = 0x1000ff0a;
+#else
+	//config MR1 ODT [9,6,2] RON [5,1] DLLOFF [0]
+	val = 0x10010000;
+	val |= (odt & 0x4)<<7 | (odt & 0x2)<<5 | (odt & 0x1)<<2;
+	val |= (ron & 0x2)<<4 | (ron & 0x1)<<1;
+	if (dll_off)
+		val |= 0x1;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x30000000;
+#elif (DDR_TYPE == 2)
+	val = 0x10008301;
+#else
+	//config MR0
+	val = 0x10000520;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x6;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x10000033;
+#elif (DDR_TYPE == 2)
+	val = 0x10000402;//0ld 0x10000102
+#else
+	val = 0x50000400;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x6;
+	while (wait_idle--);
+
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+#if (DDR_TYPE == 1)
+	val = 0x10020000;
+#elif (DDR_TYPE == 2)
+	val = 0x30000000;
+#else
+	val = 0x30000000;
+#endif
+	*addr = val;
+	wait_idle = DF_DELAY + 0x9;
+	while (wait_idle--);
+
+#if (DDR_TYPE == 2)
+/* zhangli for MCP */
+	addr = (volatile UINT32*)(DMC_REG_BASE + DIRECT_CMD);
+	*addr = 0x10000103;
+	wait_idle = DF_DELAY + 0x9;
+	while (wait_idle--);
+#endif
+
+#if (DDR_TYPE == 2)
+	addr = (volatile UINT32*)(DMC_REG_BASE + MEMC_CMD);
+	val = 0x4;
+	*addr = val;
+	wait_idle = 0x5;
+	while (wait_idle--);
+#endif
+
+	//config ECC control
+	addr = (volatile UINT32*)(DMC_REG_BASE + ECC_CTRL);
+	val = 0x0;
+	*addr = val;
+	wait_idle = 0x4f;
+	while (wait_idle--);
+
+	//config MEMC CMD
+	addr = (volatile UINT32*)(DMC_REG_BASE + MEMC_CMD);
+	val = 0x3;
+	*addr = val;
+	wait_idle = 0x8;
+	while (wait_idle--);
+
+	//READ MEMC STATUS
+	addr = (volatile UINT32*)(DMC_REG_BASE + MEMC_STATUS);
+	val = 0;
+	do {
+		val = *addr;
+		//printf("MEMC_STATUS value: %x\n", val);
+	} while (val != 3);
+}
+
+void axi_prio_init(void)
+{
+	*(volatile UINT32*)(0x20900100) = 0xaa0000aa;
+	*(volatile UINT32*)(0x21054100) = 0x00000008;
+	*(volatile UINT32*)(0x21054104) = 0x00000008;
+}
+
+void axi_outstandings_init(void)
+{
+	*(volatile UINT32*)(0x2105110C) = 0x00000060;
+	*(volatile UINT32*)(0x21051110) = 0x00000300;
+}
+
+int ddr_init(UINT16 flags, UINT32 para)
+{
+	UINT16 dll_off;
+	UINT32 mem_width;
+
+	axi_prio_init();
+	axi_outstandings_init();
+
+	dll_off = flags & DDR_FLAGS_DLLOFF;
+	mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;
+
+	switch (mem_width) {
+		case 0:
+			printf("8bit ");
+			break;
+		case 1:
+			printf("16bit ");
+			break;
+		case 2:
+			printf("32bit ");
+			break;
+	}
+	if (dll_off)
+		printf("dll-off Mode ...\n");
+	else
+		printf("dll-on Mode ...\n");
+
+	config_ddr_phy(flags);
+	config_dmc400(flags, para);
+	printf("dram init done ...\n");
+
+	return 0;
+}
+
diff --git a/board/rda/rda8850/ddr3_8810e_16bit.c b/board/rda/rda8850/ddr3_8810e_16bit.c
new file mode 100644
index 0000000000..2469e0c75e
--- /dev/null
+++ b/board/rda/rda8850/ddr3_8810e_16bit.c
@@ -0,0 +1,388 @@
+#include <common.h>

+#include <asm/arch/rda_iomap.h>

+

+#include "ddr3.h"

+#include "tgt_ap_clock_config.h"

+

+#define DDR_TYPE	3

+#define DF_DELAY	(0x100000)

+

+#define DMC_REG_BASE RDA_DMC400_BASE

+#define PHY_REG_BASE RDA_DDRPHY_BASE

+

+#define  PHY_RDLAT		0

+#define  PHYWRDATA		1

+#define  STA			3

+#define  CLKSEL			4

+#define  PSSTART		5

+#define  PSDONE			6

+#define  LOCKED			6

+#define  CTRL_DELAY		7

+#define  RDELAY_SEL		8

+#define  WDELAY_SEL		9

+#define  PHY_RESET		10

+#define  RESET_DDR3		11

+#define  ODT_DELAY		12

+#define  DDR3_USED		13

+#define  WRITE_ENABLE_LAT	14

+#define  WRITE_DATA_LAT		15

+#define  DQOUT_ENABLE_LAT	16

+#define  DMC_READY          128

+

+#define ARRAY_NUM(n) (sizeof(n))/(sizeof(n[0]))

+

+#define DMCREG_BADDR DMC_REG_BASE

+#define PHY_BADDR PHY_REG_BASE

+

+void DDR_CONFIG_DELAY(int delay)

+{

+   int i;

+   i = delay;

+   while(i--);

+}

+//////////////////////////////////////////////////////////////////////

+void config_ddr_phy(UINT16 flag)

+{

+	int cnt;

+    volatile int * addr;

+    cnt = 16;

+    while(cnt--);

+        

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (PHY_BADDR + DMC_READY*4);

+    *addr = 0;    

+    

+    addr = (int *) (PHY_BADDR + RESET_DDR3*4);

+    *addr = 1;

+

+    addr = (int *) (PHY_BADDR + WRITE_DATA_LAT*4);

+    *addr = 1;    

+    

+    addr = (int *) (PHY_BADDR + DDR3_USED*4);

+    *addr = 1;    

+   

+    addr = (int *) (PHY_BADDR + WDELAY_SEL*4);

+    *addr = 3;    

+    

+    addr = (int *) (PHY_BADDR + DQOUT_ENABLE_LAT*4);

+    *addr = 1;

+	serial_puts("ddr3 phy init done!\n");  

+}

+///////////////////////////////////////////////////////////////////

+void config_dmc400(UINT16 flag, UINT32 para)

+{

+	int wait_idle;

+	volatile int * addr;

+ wait_idle = 0x4e;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x200);

+*addr = 0x3f;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x204);

+*addr = 0x23008c;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x204);

+*addr = 0x8c008c;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x208);

+*addr = 0x4;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x20c);

+*addr = 0xc;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x218);

+*addr = 0x6;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x21c);

+*addr = 0xf;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x220);

+*addr = 0x6;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x224);

+*addr = 0x5;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x228);

+*addr = 0x4;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x22c);

+*addr = 0x14;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x234);

+*addr = 0x6;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x238);

+*addr = 0x6;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x23c);

+*addr = 0x4;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x244);

+*addr = 0x10;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x248);

+*addr = 0x4000d;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x248);

+*addr = 0x6000f;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x24c);

+*addr = 0x60000;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x230);

+*addr = 0x5;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x240);

+*addr = 0x5;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x300);

+*addr = 0x2;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x304);

+*addr = 0x105;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x304);

+*addr = 0x105;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x258);

+*addr = 0x3;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x25c);

+*addr = 0x20003;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x25c);

+*addr = 0xa0003;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x260);

+*addr = 0x4;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x264);

+*addr = 0x1000090;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x264);

+*addr = 0x2000090;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x268);

+*addr = 0x5;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x26c);

+*addr = 0x5;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x250);

+*addr = 0x5;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x254);

+*addr = 0x5;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x148);

+*addr = 0x0;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x10);

+*addr = 0x30200;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x10);

+*addr = 0x30200;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x10);

+*addr = 0x30200;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x18);

+*addr = 0x22000201;

+

+ wait_idle = 0x1d;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x10);

+*addr = 0x30200;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x10);

+*addr = 0x30401;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x14);

+*addr = 0x50;

+

+ wait_idle = 0x5;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x14);

+*addr = 0x10;

+

+ wait_idle = 0x6;

+ while(wait_idle--);

+DDR_CONFIG_DELAY(DF_DELAY); 

+addr = (int *) (DMCREG_BADDR + 0x108);

+*addr = 0x0;

+

+ wait_idle = 0x10;

+ while(wait_idle--);

+DDR_CONFIG_DELAY(DF_DELAY); 

+addr = (int *) (DMCREG_BADDR + 0x108);

+*addr = 0x10020008;

+

+ wait_idle = 0x10;

+ while(wait_idle--);

+DDR_CONFIG_DELAY(DF_DELAY); 

+addr = (int *) (DMCREG_BADDR + 0x108);

+*addr = 0x10030000;

+

+ wait_idle = 0x10;

+ while(wait_idle--);

+DDR_CONFIG_DELAY(DF_DELAY); 

+addr = (int *) (DMCREG_BADDR + 0x108);

+*addr = 0x10010001;

+

+ wait_idle = 0x10;

+ while(wait_idle--);

+DDR_CONFIG_DELAY(DF_DELAY); 

+addr = (int *) (DMCREG_BADDR + 0x108);

+*addr = 0x10000520;

+

+ wait_idle = 0x10;

+ while(wait_idle--);

+DDR_CONFIG_DELAY(DF_DELAY); 

+addr = (int *) (DMCREG_BADDR + 0x108);

+*addr = 0x50000400;

+

+ wait_idle = 0x10;

+ while(wait_idle--);

+DDR_CONFIG_DELAY(DF_DELAY); 

+addr = (int *) (DMCREG_BADDR + 0x108);

+*addr = 0x30000000;

+

+ wait_idle = 0x6;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x148);

+*addr = 0x0;

+

+ wait_idle = 0x8;

+ while(wait_idle--);

+addr = (int *) (DMCREG_BADDR + 0x8);

+*addr = 0x3;

+

+addr = (int * ) (DMCREG_BADDR + 0x0);

+wait_idle = 0;

+while ( wait_idle != 3)

+wait_idle = *addr;

+serial_puts("ddr3 dmc400 init done!\n");

+}

+

+///////////////////////////////////////////////////////////////////

+void axi_prio_init(void)

+{

+	*(volatile UINT32*)(0x20900100) = 0xaa0000aa;

+	*(volatile UINT32*)(0x21054100) = 0x00000008;

+	*(volatile UINT32*)(0x21054104) = 0x00000008;

+}

+

+int ddr_init(UINT16 flags, UINT32 para)

+{

+	UINT16 dll_off;

+	UINT32 mem_width;

+

+	axi_prio_init();

+

+	dll_off = flags & DDR_FLAGS_DLLOFF;

+	mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;

+

+	switch (mem_width) {

+		case 0:

+			serial_puts("8bit ");

+			break;

+		case 1:

+			serial_puts("16bit ");

+			break;

+		case 2:

+			serial_puts("32bit ");

+			break;

+	}

+	if (dll_off)

+		serial_puts("dll-off Mode ...\n");

+	else

+		serial_puts("dll-on Mode ...\n");

+

+	config_ddr_phy(flags);

+	config_dmc400(flags, para);

+	//serial_puts("dram");

+	//print_u32(DDR_TYPE);

+	//serial_puts(" init done ...\n");

+	printf("dram%d init done ...\n", DDR_TYPE);

+

+	return 0;

+}

+

diff --git a/board/rda/rda8850/ddr3_8810e_32bit.c b/board/rda/rda8850/ddr3_8810e_32bit.c
new file mode 100644
index 0000000000..6cdef162f6
--- /dev/null
+++ b/board/rda/rda8850/ddr3_8810e_32bit.c
@@ -0,0 +1,410 @@
+#include <common.h>

+#include <asm/arch/rda_iomap.h>

+

+#include "ddr3.h"

+#include "tgt_ap_clock_config.h"

+

+#define DDR_TYPE	3

+#define DF_DELAY	(0x100000)

+

+#define DMC_REG_BASE RDA_DMC400_BASE

+#define PHY_REG_BASE RDA_DDRPHY_BASE

+

+#define  PHY_RDLAT		0

+#define  PHYWRDATA		1

+#define  STA			3

+#define  CLKSEL			4

+#define  PSSTART		5

+#define  PSDONE			6

+#define  LOCKED			6

+#define  CTRL_DELAY		7

+#define  RDELAY_SEL		8

+#define  WDELAY_SEL		9

+#define  PHY_RESET		10

+#define  RESET_DDR3		11

+#define  ODT_DELAY		12

+#define  DDR3_USED		13

+#define  WRITE_ENABLE_LAT	14

+#define  WRITE_DATA_LAT		15

+#define  DQOUT_ENABLE_LAT	16

+#define  DMC_READY          128

+#define  DATA_ODT_ENABLE_REG    20

+#define  DATA_WRITE_ENABLE_REG  48   

+

+#define ARRAY_NUM(n) (sizeof(n))/(sizeof(n[0]))

+

+#define DMCREG_BADDR DMC_REG_BASE

+#define PHY_BADDR PHY_REG_BASE

+

+void DDR_CONFIG_DELAY(int delay)

+{

+    int i;

+    i = delay;

+    while(i--);

+}

+

+void config_ddr_phy(UINT16 flag)

+{

+    int cnt;

+    volatile int * addr;

+    cnt = 16;

+    while(cnt--);

+        

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (PHY_BADDR + DMC_READY*4);

+    *addr = 0;    

+    

+    addr = (int *) (PHY_BADDR + RESET_DDR3*4);

+    *addr = 1;

+

+    addr = (int *) (PHY_BADDR + WRITE_DATA_LAT*4);

+    *addr = 1;    

+    

+    addr = (int *) (PHY_BADDR + DDR3_USED*4);

+    *addr = 1;    

+   

+    addr = (int *) (PHY_BADDR + WDELAY_SEL*4);

+    *addr = 3;    

+    

+    addr = (int *) (PHY_BADDR + DQOUT_ENABLE_LAT*4);

+    *addr = 1;

+

+    addr = (int *) (PHY_BADDR + DATA_ODT_ENABLE_REG*4);

+    *addr = 0xf;

+    

+    addr = (int *) (PHY_BADDR + DATA_WRITE_ENABLE_REG*4);

+    *addr = 0xf;  

+          	

+    serial_puts("ddr3 phy init done!\n");  

+}

+

+#define DMC_WAIT_IDLE     1

+

+void config_dmc400(UINT16 flag, UINT32 para)

+{

+    int wait_idle;

+    volatile int *addr;

+    volatile int temp;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x200);

+    *addr = 0x3f;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x204);

+    *addr = 0x23008c;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x204);

+    *addr = 0x8c008c;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x208);

+    *addr = 0x4;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x20c);

+    *addr = 0xc;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x218);

+    *addr = 0x6;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x21c);

+    *addr = 0xf;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x220);

+    *addr = 0x6;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x224);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x228);

+    *addr = 0x4;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x22c);

+    *addr = 0x14;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x234);

+    *addr = 0x6;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x238);

+    *addr = 0x6;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x23c);

+    *addr = 0x4;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x244);

+    *addr = 0x10;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x248);

+    *addr = 0x4000d;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x248);

+    *addr = 0x6000f;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x24c);

+    *addr = 0x60000;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x230);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x240);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x300);

+    *addr = 0x2;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x304);

+    *addr = 0x105;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x304);

+    *addr = 0x105;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x258);

+    *addr = 0x3;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x25c);

+    *addr = 0x20003;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x25c);

+    *addr = 0xa0003;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x260);

+    *addr = 0x4;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x264);

+    *addr = 0x1000090;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x264);

+    *addr = 0x2000090;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x268);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x26c);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x250);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x254);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x148);

+    *addr = 0x0;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    *addr = 0x30200;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    *addr = 0x30200;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    *addr = 0x30200;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x18);

+    //*addr = 0x22000201;

+    *addr = 0x22000202;

+

+    wait_idle = DMC_WAIT_IDLE * 0x1d;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    *addr = 0x30200;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    //*addr = 0x30401;

+    *addr = 0x30302;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x14);

+    *addr = 0x50;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x14);

+    //*addr = 0x10;

+    *addr = 0x00;

+

+    wait_idle = DMC_WAIT_IDLE * 0x6;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x0;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x10020008;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x10030000;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x10010001;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x10000520;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x50000400;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x30000000;

+

+    wait_idle = DMC_WAIT_IDLE * 0x6;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x148);

+    *addr = 0x0;

+

+    wait_idle = DMC_WAIT_IDLE * 0x8;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x8);

+    *addr = 0x3;

+

+    addr = (int * ) (DMCREG_BADDR + 0x0);

+    temp = 0;

+    while (temp != 3)

+        temp = *addr;

+

+    serial_puts("ddr3 dmc400 init done!\n");

+}

+

+void axi_prio_init(void)

+{

+    *(volatile UINT32*)(0x20900100) = 0xaa0000aa;

+    *(volatile UINT32*)(0x21054100) = 0x00000008;

+    *(volatile UINT32*)(0x21054104) = 0x00000008;

+}

+

+void axi_outstandings_init(void)

+{

+    *(volatile UINT32*)(0x2105110C) = 0x00000060;

+    *(volatile UINT32*)(0x21051110) = 0x00000300;

+}

+

+int ddr_init(UINT16 flags, UINT32 para)

+{

+    UINT16 dll_off;

+    UINT32 mem_width;

+

+    axi_prio_init();

+    axi_outstandings_init();

+

+    dll_off = flags & DDR_FLAGS_DLLOFF;

+    mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;

+

+    switch (mem_width) {

+    case 0:

+        serial_puts("8bit ");

+        break;

+    case 1:

+        serial_puts("16bit ");

+        break;

+    case 2:

+        serial_puts("32bit ");

+        break;

+    }

+    if (dll_off)

+        serial_puts("dll-off Mode ...\n");

+    else

+        serial_puts("dll-on Mode ...\n");

+

+    config_ddr_phy(flags);

+    config_dmc400(flags, para);

+    //serial_puts("dram ");

+    //print_u32(DDR_TYPE);

+    //serial_puts(" init done ...\n");

+    printf("ddr%d init done\n");

+

+    return 0;

+}

diff --git a/board/rda/rda8850/ddr3_init.h b/board/rda/rda8850/ddr3_init.h
new file mode 100644
index 0000000000..402375d269
--- /dev/null
+++ b/board/rda/rda8850/ddr3_init.h
@@ -0,0 +1,101 @@
+#ifndef _SYS_RAM_INIT_H_
+#define _SYS_RAM_INIT_H_
+
+#define MEMC_STATUS			0x000
+#define MEMC_CONFIG			0x004
+#define MEMC_CMD			0x008
+#define ADDR_CTRL			0x010
+#define DECODE_CTRL			0x014
+#define FORMAT_CTRL			0x018
+#define LOWPWR_CTRL			0x020
+#define TURNAROUND_PRIO			0x030
+#define HIT_PRIO			0x034
+//QOS0~QOS15:038~078
+#define QOSX_CTRL			0x038
+#define QOSX_CTRL7			0x058
+#define QOSX_CTRL15			0x078
+#define TIMEOUT_CTRL			0x07C
+#define QUEUE_CTRL			0x080
+#define WR_PRIO_CTRL			0x088
+#define WR_PRIO_CTRL2			0x08C
+#define RD_PRIO_CTRL			0x090
+#define RD_PRIO_CTRL2			0x094
+#define ACCESS_ADDR_MATCH		0x098
+#define ACCESS_ADDR_MATCH_63_32		0x09C
+#define ACCESS_ADDR_MASK		0x0A0
+#define ACCESS_ADDR_MASK_63_32		0x0A4
+
+#define CHANNEL_STATUS			0x100
+#define DIRECT_CMD			0x108
+#define MR_DATA				0x110
+#define REFRESH_CTRL			0x120
+#define INTR_CTRL			0x128
+#define INTR_CLR			0x130
+#define INTR_STATUS			0x138
+#define INTR_INFO			0x140
+#define ECC_CTRL			0x148
+
+#define T_REFI				0x200
+#define T_RFC				0x204
+#define T_MRR				0x208
+#define T_MRW				0x20C
+#define T_RCD				0x218
+#define T_RAS				0x21C
+#define T_RP				0x220
+#define T_RPALL				0x224
+#define T_RRD				0x228
+#define T_FAW				0x22C
+#define RD_LATENCY			0x230
+#define T_RTR				0x234
+#define T_RTW				0x238
+#define T_RTP				0x23C
+#define WR_LATENCY			0x240
+#define T_WR				0x244
+#define T_WTR				0x248
+#define T_WTW				0x24C
+#define T_ECKD				0x250
+#define T_XCKD				0x254
+#define T_EP				0x258
+#define T_XP				0x25C
+#define T_ESR				0x260
+#define T_XSR				0x264
+#define T_SRCKD				0x268
+#define T_CKSRD				0x26C
+
+#define T_RDDATA_EN			0x300
+#define T_PHYWRLAT			0x304
+#define RDLVL_CTRL			0x308
+#define RDLVL_DIRECT			0x310
+#define T_RDLVL_EN			0x318
+#define T_RDLVL_RR			0x31C
+#define WRLVL_CTRL			0x328
+#define WRLVL_DIRECT			0x330
+#define T_WRLVL_EN			0x338
+#define T_WRLVL_WW			0x33C
+
+#define PHY_PWR_CTRL			0x348
+#define PHY_UPD_CTRL			0x350
+
+#define USER_STATUS			0x400
+#define USER_CONFIG0			0x404
+#define USER_CONFIG1			0x408
+
+#define INTEG_CFG			0xE00
+#define INTEG_OUTPUTS			0xE08
+
+#define PERIPH_ID_0			0xFE0
+#define PERIPH_ID_1			0xFE4
+#define PERIPH_ID_2			0xFE8
+#define PERIPH_ID_3			0xFEC
+#define COMPONENT_ID_0			0xFF0
+#define COMPONENT_ID_1			0xFF4
+#define COMPONENT_ID_2			0xFF8
+#define COMPONENT_ID_3			0xFFC
+
+typedef struct {
+	UINT32 reg_offset;
+	UINT32 dll_on_val;
+	UINT32 dll_off_val;
+} dmc_reg_t;
+
+#endif /* _SYS_RAM_INIT_H_ */
diff --git a/board/rda/rda8850/ddr3_zhangli_32bit_dlloff.c b/board/rda/rda8850/ddr3_zhangli_32bit_dlloff.c
new file mode 100644
index 0000000000..aeabca6ba2
--- /dev/null
+++ b/board/rda/rda8850/ddr3_zhangli_32bit_dlloff.c
@@ -0,0 +1,400 @@
+#include <common.h>

+#include <asm/arch/rda_iomap.h>

+

+#include "ddr3.h"

+

+#define DDR_TYPE	3

+#define DF_DELAY	(0x100000)

+

+#define DMC_REG_BASE RDA_DMC400_BASE

+#define PHY_REG_BASE RDA_DDRPHY_BASE

+

+#define  PHY_RDLAT		0

+#define  PHYWRDATA		1

+#define  STA			3

+#define  CLKSEL			4

+#define  PSSTART		5

+#define  PSDONE			6

+#define  LOCKED			6

+#define  CTRL_DELAY		7

+#define  RDELAY_SEL		8

+#define  WDELAY_SEL		9

+#define  PHY_RESET		10

+#define  RESET_DDR3		11

+#define  ODT_DELAY		12

+#define  DDR3_USED		13

+#define  WRITE_ENABLE_LAT	14

+#define  WRITE_DATA_LAT		15

+#define  DQOUT_ENABLE_LAT	16

+#define  DMC_READY          128

+#define  DATA_ODT_ENABLE_REG    20

+#define  DATA_WRITE_ENABLE_REG  48   

+

+#define ARRAY_NUM(n) (sizeof(n))/(sizeof(n[0]))

+

+#define DMCREG_BADDR DMC_REG_BASE

+#define PHY_BADDR PHY_REG_BASE

+

+void DDR_CONFIG_DELAY(int delay)

+{

+    int i;

+    i = delay;

+    while(i--);

+}

+

+void config_ddr_phy(UINT16 flag)

+{

+    int cnt;

+    volatile int * addr;

+    cnt = 16;

+    while(cnt--);

+        

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (PHY_BADDR + DMC_READY*4);

+    *addr = 0;    

+    

+    addr = (int *) (PHY_BADDR + RESET_DDR3*4);

+    *addr = 1;

+

+    addr = (int *) (PHY_BADDR + WRITE_DATA_LAT*4);

+    *addr = 1;    

+    

+    addr = (int *) (PHY_BADDR + DDR3_USED*4);

+    *addr = 1;    

+   

+    addr = (int *) (PHY_BADDR + WDELAY_SEL*4);

+    *addr = 3;    

+    

+    addr = (int *) (PHY_BADDR + DQOUT_ENABLE_LAT*4);

+    *addr = 1;

+

+    addr = (int *) (PHY_BADDR + DATA_ODT_ENABLE_REG*4);

+    *addr = 0xf;

+    

+    addr = (int *) (PHY_BADDR + DATA_WRITE_ENABLE_REG*4);

+    *addr = 0xf;  

+          	

+    printf("ddr3 phy init done!\n");  

+}

+

+#define DMC_WAIT_IDLE     1

+

+void config_dmc400(UINT16 flag, UINT32 para)

+{

+    int wait_idle;

+    volatile int *addr;

+    volatile int temp;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x200);

+    *addr = 0x3f;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x204);

+    *addr = 0x23008c;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x204);

+    *addr = 0x8c008c;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x208);

+    *addr = 0x4;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x20c);

+    *addr = 0xc;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x218);

+    *addr = 0x6;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x21c);

+    *addr = 0xf;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x220);

+    *addr = 0x6;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x224);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x228);

+    *addr = 0x4;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x22c);

+    *addr = 0x14;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x234);

+    *addr = 0x6;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x238);

+    *addr = 0x6;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x23c);

+    *addr = 0x4;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x244);

+    *addr = 0x10;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x248);

+    *addr = 0x4000d;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x248);

+    *addr = 0x6000f;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x24c);

+    *addr = 0x60000;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x230);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x240);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x300);

+    *addr = 0x2;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x304);

+    *addr = 0x105;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x304);

+    *addr = 0x105;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x258);

+    *addr = 0x3;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x25c);

+    *addr = 0x20003;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x25c);

+    *addr = 0xa0003;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x260);

+    *addr = 0x4;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x264);

+    *addr = 0x1000090;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x264);

+    *addr = 0x2000090;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x268);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x26c);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x250);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x254);

+    *addr = 0x5;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x148);

+    *addr = 0x0;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    *addr = 0x30200;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    *addr = 0x30200;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    *addr = 0x30200;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x18);

+    //*addr = 0x22000201;

+    *addr = 0x22000202;

+

+    wait_idle = DMC_WAIT_IDLE * 0x1d;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    *addr = 0x30200;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x10);

+    //*addr = 0x30401;

+    *addr = 0x30302;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x14);

+    *addr = 0x50;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x14);

+    //*addr = 0x10;

+    *addr = 0x00;

+

+    wait_idle = DMC_WAIT_IDLE * 0x6;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x0;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x10020008;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x10030000;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x10010001;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x10000520;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x50000400;

+

+    wait_idle = DMC_WAIT_IDLE;

+    while(wait_idle--);

+    DDR_CONFIG_DELAY(DF_DELAY); 

+    addr = (int *) (DMCREG_BADDR + 0x108);

+    *addr = 0x30000000;

+

+    wait_idle = DMC_WAIT_IDLE * 0x6;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x148);

+    *addr = 0x0;

+

+    wait_idle = DMC_WAIT_IDLE * 0x8;

+    while(wait_idle--);

+    addr = (int *) (DMCREG_BADDR + 0x8);

+    *addr = 0x3;

+

+    addr = (int * ) (DMCREG_BADDR + 0x0);

+    temp = 0;

+    while (temp != 3)

+        temp = *addr;

+

+    printf("ddr3 dmc400 init done!\n");

+}

+

+void axi_prio_init(void)

+{

+	*(volatile UINT32*)(0x20900100) = 0xaa0000aa;

+	*(volatile UINT32*)(0x21054100) = 0x00000008;

+	*(volatile UINT32*)(0x21054104) = 0x00000008;

+}

+

+int ddr_init(UINT16 flags, UINT32 para)

+{

+    UINT16 dll_off;

+    UINT32 mem_width;

+

+    axi_prio_init();

+

+    dll_off = flags & DDR_FLAGS_DLLOFF;

+    mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;

+

+    switch (mem_width) {

+    case 0:

+        printf("8bit ");

+        break;

+    case 1:

+        printf("16bit ");

+        break;

+    case 2:

+        printf("32bit ");

+        break;

+    }

+    if (dll_off)

+        printf("dll-off Mode ...\n");

+    else

+        printf("dll-on Mode ...\n");

+

+    config_ddr_phy(flags);

+    config_dmc400(flags, para);

+	printf("dram%x init done ...\n", DDR_TYPE);

+

+    return 0;

+}

+

diff --git a/board/rda/rda8850/debug.h b/board/rda/rda8850/debug.h
new file mode 100644
index 0000000000..1d4f03bedb
--- /dev/null
+++ b/board/rda/rda8850/debug.h
@@ -0,0 +1,9 @@
+#ifndef _DEBUG_H_
+#define _DEBUG_H_
+
+void print_u8(u8 ch);
+void print_u16(u16 data);
+void print_u32(u32 data);
+void dump_buf(u8 *buf, u32 size);
+
+#endif /* _DEBUG_H_ */
diff --git a/board/rda/rda8850/hal_config.c b/board/rda/rda8850/hal_config.c
new file mode 100644
index 0000000000..e07d22afaa
--- /dev/null
+++ b/board/rda/rda8850/hal_config.c
@@ -0,0 +1,1168 @@
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//            Copyright (C) 2013, RDA Microeletronics.                        //
+//                            All Rights Reserved                             //
+//                                                                            //
+//      This source code is the property of RDA Microeletronics and is        //
+//      confidential.  Any  modification, distribution,  reproduction or      //
+//      exploitation  of  any content of this file is totally forbidden,      //
+//      except  with the  written permission  of  RDA Microeletronics.        //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//  $HeadURL: http://svn.rdamicro.com/svn/developing1/Sources/chip/branches/8810/hal/8810/src/hal_config.c $ //
+//    $Author: huazeng $                                                        //
+//    $Date: 2013-08-31 17:48:58 +0800 (Sat, 31 Aug 2013) $                     //
+//    $Revision: 21005 $                                                          //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+/// @file hal_config.c
+/// Implementation of HAL initialization related with the particular instance
+/// of the IP.
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+
+/* uboot */
+#include <common.h>
+
+/* common */
+#include <asm/arch/rda_iomap.h>
+#include <asm/arch/hwcfg.h>
+#include <asm/arch/chip_id.h>
+#include <asm/arch/cs_types.h>
+#include <asm/arch/global_macros.h>
+#include <asm/arch/reg_gpio.h>
+
+/* device */
+#include "hal_sys.h"
+#include "halp_sys.h"
+#include "halp_gpio.h"
+#include "bootp_mode.h"
+#include "hal_config.h"
+#include "hal_ap_gpio.h"
+#include "hal_ap_config.h"
+#include <asm/arch/reg_cfg_regs.h>
+
+/* target */
+#include "tgt_board_cfg.h"
+#include "tgt_ap_gpio_setting.h"
+#define HAL_ASSERT(cond, fmt, ...) \
+	if(!(cond)) { \
+		hal_assert(fmt, ##__VA_ARGS__); \
+		g_halConfigError = TRUE; \
+	}
+
+//// =============================================================================
+////  GLOBAL VARIABLES
+//// =============================================================================
+PRIVATE CONST UINT8 g_halCfgSimOrder[] = { TGT_SIM_ORDER };
+PRIVATE HAL_CFG_CONFIG_T hal_cfg = TGT_HAL_CONFIG;
+PRIVATE UINT32 g_bootBootMode = 0;
+PRIVATE BOOL g_halConfigError = FALSE;
+
+
+// =============================================================================
+//  FUNCTIONS
+// =============================================================================
+// HAL_ASSERT
+PRIVATE VOID hal_assert(const char *fmt, ...)
+{
+	va_list args;
+	puts("\n#-------Board Mux config found error-------#\n");
+	va_start(args, fmt);
+	vprintf(fmt, args);
+	putc('\n');
+	puts("--------------------------------------------\n\n");
+	va_end(args);
+}
+
+// =============================================================================
+// hal_BoardSimUsed
+// -----------------------------------------------------------------------------
+/// Check whether a SIM card interface is used.
+// ============================================================================
+PRIVATE BOOL hal_BoardSimUsed(UINT32 simId)
+{
+	UINT32 i = 0;
+    //for (UINT32 i=0; i<ARRAY_SIZE(g_halCfgSimOrder) && i<NUMBER_OF_SIM; i++)
+    for (i=0; i<ARRAY_SIZE(g_halCfgSimOrder) && i<NUMBER_OF_SIM; i++)
+    {
+        if (g_halCfgSimOrder[i] == simId)
+        {
+            return TRUE;
+        }
+    }
+
+    return FALSE;
+}
+
+#if 0
+// =============================================================================
+// hal_BoardConfigClk32k
+// -----------------------------------------------------------------------------
+/// Configure CLK_32K output.
+/// @param enable TRUE to configure, and FALSE to disable.
+// ============================================================================
+PROTECTED VOID hal_BoardConfigClk32k(BOOL enable)
+{
+    HAL_ASSERT(g_halCfg->useClk32k == TRUE, "32K clock is not configured");
+
+    if (enable)
+    {
+        // Setup the pin as 32K clock output
+        hwp_configRegs->Alt_mux_select =
+            (hwp_configRegs->Alt_mux_select & ~CFG_REGS_GPO_2_MASK) |
+            CFG_REGS_GPO_2_CLK_32K;
+    }
+    else
+    {
+        // Setup the pin as GPO (and low ouput has been
+        // configured in hal_BoardSetup())
+        hwp_configRegs->Alt_mux_select =
+            (hwp_configRegs->Alt_mux_select & ~CFG_REGS_GPO_2_MASK) |
+            CFG_REGS_GPO_2_GPO_2;
+    }
+}
+#endif
+
+// =============================================================================
+// hal_BoardSetupGeneral
+// -----------------------------------------------------------------------------
+/// Apply board dependent configuration to HAL for general purpose
+/// @param halCfg Pointer to HAL configuration structure (from the target
+/// module).
+// ============================================================================
+PROTECTED VOID hal_BoardSetupGeneral(CONST HAL_CFG_CONFIG_T* halCfg)
+{
+    UINT32 altMux = 0;
+
+    UINT32 availableGpo_A = 0;
+
+    UINT32 availableGpio_C = 0;
+    UINT32 availableGpio_A = 0;
+    UINT32 availableGpio_B = 0;
+    UINT32 availableGpio_D = 0;
+
+    UINT32 bootModeGpio_C = 0;
+    UINT32 bootModeGpio_A = 0;
+    UINT32 bootModeGpio_B = 0;
+    UINT32 bootModeGpio_D = 0;
+
+    UINT32 noConnectMask_C = 0;
+    UINT32 noConnectMask_A = 0;
+    UINT32 noConnectMask_B = 0;
+    UINT32 noConnectMask_D = 0;
+
+#ifdef FPGA
+
+    // no muxing, do nothing
+
+#else // !FPGA
+
+    // GPIOs as boot mode pins
+    bootModeGpio_C = HAL_GPIO_BIT(1)
+                   | HAL_GPIO_BIT(2)
+                   | HAL_GPIO_BIT(3)
+                   | HAL_GPIO_BIT(4)
+                   | HAL_GPIO_BIT(5);
+    bootModeGpio_A = HAL_GPIO_BIT(4)
+                   | HAL_GPIO_BIT(5)
+                   | HAL_GPIO_BIT(6)
+                   | HAL_GPIO_BIT(7);
+    bootModeGpio_B = HAL_GPIO_BIT(0);
+    bootModeGpio_D = 0;
+
+    // Available GPIOs
+    availableGpio_C |= HAL_GPIO_BIT(0)
+                     | HAL_GPIO_BIT(1)
+                     | HAL_GPIO_BIT(2)
+                     | HAL_GPIO_BIT(3)
+                     | HAL_GPIO_BIT(4)
+                     | HAL_GPIO_BIT(5);
+    // Volume down/up keys
+    availableGpio_D |= HAL_GPIO_BIT(5)
+                     | HAL_GPIO_BIT(6);
+
+    // Boot modes
+    BOOL spiFlashCam = FALSE;
+    BOOL spiFlashNand = FALSE;
+    if (g_bootBootMode & BOOT_MODE_BOOT_SPI)
+    {
+        if (g_bootBootMode & BOOT_MODE_SPI_PIN_NAND)
+        {
+            HAL_ASSERT((g_bootBootMode & BOOT_MODE_BOOT_EMMC),
+                "Emmc boot pin should be pulled up to boot on SPI flash over NAND pins");
+            spiFlashNand = TRUE;
+        }
+        else
+        {
+            spiFlashCam = TRUE;
+        }
+    }
+
+    if ((g_bootBootMode & (BOOT_MODE_BOOT_EMMC|BOOT_MODE_BOOT_SPI|BOOT_MODE_BOOT_SPI_NAND))
+        == BOOT_MODE_BOOT_EMMC)
+    {
+        // Boot from EMMC
+        HAL_ASSERT(halCfg->sdmmcCfg.sdmmc3Used, "SDMMC3 should be used");
+    }
+
+    if ( (g_bootBootMode & (BOOT_MODE_BOOT_SPI|BOOT_MODE_BOOT_SPI_NAND))
+         == BOOT_MODE_BOOT_SPI_NAND ||
+         (g_bootBootMode & (BOOT_MODE_BOOT_SPI|BOOT_MODE_NAND_PAGE_SIZE_L))
+         == (BOOT_MODE_BOOT_SPI|BOOT_MODE_NAND_PAGE_SIZE_L)
+       )
+    {
+        // Boot from SDMMC1
+        HAL_ASSERT(halCfg->sdmmcCfg.sdmmcUsed, "SDMMC1 should be used");
+    }
+
+    // For convenience, we do not consider spiFlashCam at present.
+    // We assume that SPI flash always uses parallel nand pins.
+#if 0
+    BOOL parallelNandUsed = halCfg->parallelNandUsed;
+#else
+    BOOL parallelNandUsed = !spiFlashNand && !halCfg->sdmmcCfg.sdmmc3Used;
+#endif
+    BOOL nand8_15Cam = FALSE;
+    BOOL nand8_15Lcd = FALSE;
+    if ((g_bootBootMode & BOOT_MODE_BOOT_EMMC) == 0)
+    {
+        // If BOOT_MODE_BOOT_EMMC is not set, the parallel NAND pins
+        // are multiplexed to parallel NAND controller
+        HAL_ASSERT(parallelNandUsed, "Parallel NAND should be used");
+        if ((g_bootBootMode & BOOT_MODE_NAND_8BIT) == 0)
+        {
+            if (g_bootBootMode & BOOT_MODE_NAND_HIGH_PIN_CAM)
+            {
+                nand8_15Cam = TRUE;
+            }
+            else
+            {
+                nand8_15Lcd = TRUE;
+            }
+        }
+    }
+
+    HAL_ASSERT(!(parallelNandUsed && spiFlashNand), "SPI flash uses parallel NAND pins");
+    HAL_ASSERT(!(nand8_15Cam && spiFlashCam), "NAND 8-15 bits and SPI flash both use cam pins");
+
+    if (!(parallelNandUsed || spiFlashNand))
+    {
+        availableGpio_B |= HAL_GPIO_BIT(25)
+                         | HAL_GPIO_BIT(26)
+                         | HAL_GPIO_BIT(27)
+                         | HAL_GPIO_BIT(28)
+                         | HAL_GPIO_BIT(29);
+        availableGpio_D |= HAL_GPIO_BIT(4);
+    }
+
+    CONST HAL_CFG_CAM_T *camCfg = &halCfg->camCfg;
+    CONST HAL_LCD_MODE_T lcdMode = halCfg->goudaCfg.lcdMode;
+
+    // LCD
+    if (lcdMode == HAL_LCD_MODE_PARALLEL_16BIT)
+    {
+        HAL_ASSERT(!nand8_15Lcd, "NAND uses LCD 8-15 bits");
+        altMux |= CFG_REGS_LCD_MODE_PARALLEL_16BIT;
+    }
+    else if (lcdMode == HAL_LCD_MODE_DSI)
+    {
+        altMux |= CFG_REGS_LCD_MODE_DSI;
+        availableGpio_A |= HAL_GPIO_BIT(22)
+                         | HAL_GPIO_BIT(23);
+    }
+    else if (lcdMode == HAL_LCD_MODE_RGB_16BIT)
+    {
+        HAL_ASSERT(!nand8_15Lcd, "NAND uses LCD 8-15 bits");
+        altMux |= CFG_REGS_LCD_MODE_RGB_16BIT;
+    }
+/*
+    else if (lcdMode == HAL_LCD_MODE_RGB_24BIT)
+    {
+        HAL_ASSERT(!nand8_15Lcd, "NAND uses LCD 8-15 bits");
+        if (halCfg->goudaCfg.lcd16_23Cam)
+        {
+            HAL_ASSERT(
+                !(camCfg->camMode == HAL_CAM_MODE_PARALLEL &&
+                  (camCfg->camUsed || camCfg->cam1Used)),
+                "Parallel camera uses LCD 16-23 bits");
+            HAL_ASSERT(
+                !(halCfg->i2cCfg.i2c2Used && halCfg->i2cCfg.i2c2PinsCam),
+                "I2C2 uses LCD 22-23 bits");
+            HAL_ASSERT(!spiFlashCam, "SPI flash uses LCD 16-21 bits");
+            HAL_ASSERT(!nand8_15Cam, "NAND uses LCD 16-23 bits");
+            HAL_ASSERT(
+                !(camCfg->camMode == HAL_CAM_MODE_CSI &&
+                  ((camCfg->camUsed && camCfg->camCsiId == HAL_CAM_CSI_1) ||
+                   (camCfg->cam1Used && camCfg->cam1CsiId == HAL_CAM_CSI_1))),
+                "Camera CSI1 uses LCD 16-21 bits");
+            altMux |= CFG_REGS_LCD24_CAM_CAM_IO;
+        }
+        else
+        {
+            HAL_ASSERT(!parallelNandUsed, "NAND uses LCD 16-23 bits");
+            HAL_ASSERT(!halCfg->sdmmcCfg.sdmmc3Used, "SDMMC3 uses LCD 16-23 bits");
+            altMux |= CFG_REGS_LCD24_CAM_NAND_IO;
+        }
+        altMux |= CFG_REGS_LCD_MODE_RGB_24BIT;
+    }
+*/
+    else if (lcdMode == HAL_LCD_MODE_SPI)
+    {
+        HAL_ASSERT(!(halCfg->goudaCfg.cs0Used || halCfg->goudaCfg.cs1Used),
+            "LCD CS 0/1 use SPI LCD pins");
+        HAL_ASSERT((halCfg->usedGpo_A & 0x18) == 0, "GPO 3/4 use SPI LCD pins");
+        altMux |= CFG_REGS_SPI_LCD_SPI_LCD;
+        availableGpio_A |= HAL_GPIO_BIT(18)
+                         | HAL_GPIO_BIT(19)
+                         | HAL_GPIO_BIT(20)
+                         | HAL_GPIO_BIT(21);
+    }
+    else
+    {
+        HAL_ASSERT(FALSE, "Lcd mode not defined!");
+    }
+
+    if (lcdMode == HAL_LCD_MODE_DSI || lcdMode == HAL_LCD_MODE_SPI)
+    {
+        if (nand8_15Lcd)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(24)
+                             | HAL_GPIO_BIT(25)
+                             | HAL_GPIO_BIT(26)
+                             | HAL_GPIO_BIT(27)
+                             | HAL_GPIO_BIT(28)
+                             | HAL_GPIO_BIT(29)
+                             | HAL_GPIO_BIT(30)
+                             | HAL_GPIO_BIT(31);
+        }
+    }
+
+    if (halCfg->goudaCfg.cs0Used)
+    {
+        altMux |= CFG_REGS_GPO_4_LCD_CS_0;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_4_GPO_4;
+        availableGpo_A |= HAL_GPO_BIT(4);
+    }
+
+    if (halCfg->goudaCfg.cs1Used)
+    {
+        altMux |= CFG_REGS_GPO_3_LCD_CS_1;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_3_GPO_3;
+        availableGpo_A |= HAL_GPO_BIT(3);
+    }
+
+    // I2C
+    if (!halCfg->i2cCfg.i2cUsed)
+    {
+        availableGpio_B |= HAL_GPIO_BIT(30)
+                         | HAL_GPIO_BIT(31);
+    }
+
+    if (halCfg->i2cCfg.i2c2Used)
+    {
+        if (halCfg->i2cCfg.i2c2PinsCam)
+        {
+            if (camCfg->camUsed)
+            {
+                HAL_ASSERT(camCfg->camPdnRemap == GPIO_NONE &&
+                    camCfg->camRstRemap == GPIO_NONE,
+                    "Cam uses PDN/RST pins");
+            }
+            if (camCfg->cam1Used)
+            {
+                HAL_ASSERT(camCfg->cam1PdnRemap == GPIO_NONE &&
+                    camCfg->cam1RstRemap == GPIO_NONE,
+                    "Cam1 uses PDN/RST pins");
+            }
+            HAL_ASSERT(!nand8_15Cam, "NAND uses cam PDN/RST pins");
+            availableGpio_A |= HAL_GPIO_BIT(0)
+                             | HAL_GPIO_BIT(1);
+            altMux |= CFG_REGS_CAM_I2C2_I2C2;
+        }
+        else
+        {
+            // I2C2 does not use cam pins
+            altMux |= CFG_REGS_CAM_I2C2_CAM;
+        }
+    }
+    else
+    {
+        // I2C2 does not use cam pins
+        altMux |= CFG_REGS_CAM_I2C2_CAM;
+        availableGpio_A |= HAL_GPIO_BIT(0)
+                         | HAL_GPIO_BIT(1);
+    }
+
+    if (halCfg->i2cCfg.i2c3Used)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x18) == 0, "Keyout 3/4 use I2C3 pins");
+        altMux |= CFG_REGS_KEYOUT_3_4_I2C3;
+    }
+    else
+    {
+        altMux |= CFG_REGS_KEYOUT_3_4_KEYOUT_3_4;
+        if ((halCfg->keyOutMask & 0x8) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(6);
+        }
+        if ((halCfg->keyOutMask & 0x10) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(7);
+        }
+    }
+
+    // Camera
+    if (camCfg->camUsed || camCfg->cam1Used)
+    {
+        if(camCfg->camMode == HAL_CAM_MODE_PARALLEL)
+        {
+            HAL_ASSERT(!spiFlashCam, "SPI flash uses cam pins");
+            HAL_ASSERT(!nand8_15Cam, "NAND 8-15 bits use cam pins");
+            altMux |= CFG_REGS_CSI2_PARALLEL_CAM;
+            availableGpio_B |= HAL_GPIO_BIT(24);
+        }
+        else if (camCfg->camMode == HAL_CAM_MODE_SPI)
+        {
+            altMux |= CFG_REGS_CSI2_SPI_CAM;
+            availableGpio_B |= HAL_GPIO_BIT(14);
+            if (!(spiFlashCam || nand8_15Cam ||
+                  (lcdMode == HAL_LCD_MODE_RGB_24BIT &&
+                   halCfg->goudaCfg.lcd16_23Cam)
+                 )
+               )
+            {
+                availableGpio_B |= HAL_GPIO_BIT(13)
+                                 | HAL_GPIO_BIT(20)
+                                 | HAL_GPIO_BIT(21)
+                                 | HAL_GPIO_BIT(22)
+                                 | HAL_GPIO_BIT(23)
+                                 | HAL_GPIO_BIT(24);
+            }
+        }
+        else if (camCfg->camMode == HAL_CAM_MODE_CSI)
+        {
+            if ((camCfg->camUsed && camCfg->camCsiId == HAL_CAM_CSI_1) ||
+                (camCfg->cam1Used && camCfg->cam1CsiId == HAL_CAM_CSI_1))
+            {
+                HAL_ASSERT(!spiFlashCam, "SPI flash uses CSI1 pins");
+                HAL_ASSERT(!nand8_15Cam, "NAND 8-15 bits use CSI1 pins");
+            }
+            else
+            {
+                // CSI1 is unused
+                if (!(spiFlashCam || nand8_15Cam ||
+                      (lcdMode == HAL_LCD_MODE_RGB_24BIT &&
+                       halCfg->goudaCfg.lcd16_23Cam)
+                     )
+                   )
+                {
+                    availableGpio_B |= HAL_GPIO_BIT(13)
+                                     | HAL_GPIO_BIT(20)
+                                     | HAL_GPIO_BIT(21)
+                                     | HAL_GPIO_BIT(22)
+                                     | HAL_GPIO_BIT(23)
+                                     | HAL_GPIO_BIT(24);
+                }
+            }
+            altMux |= CFG_REGS_CSI2_CSI2;
+            // If CSI2 is unused
+            if (!((camCfg->camUsed && camCfg->camCsiId == HAL_CAM_CSI_2) ||
+                  (camCfg->cam1Used && camCfg->cam1CsiId == HAL_CAM_CSI_2)))
+            {
+                availableGpio_B |= HAL_GPIO_BIT(14)
+                                 | HAL_GPIO_BIT(15)
+                                 | HAL_GPIO_BIT(16)
+                                 | HAL_GPIO_BIT(17)
+                                 | HAL_GPIO_BIT(18)
+                                 | HAL_GPIO_BIT(19);
+            }
+        }
+        else
+        {
+            HAL_ASSERT(FALSE,"Invalid cam mode: %d", camCfg->camMode);
+        }
+
+        // Cam PDN/RST pins
+        if (!(nand8_15Cam ||
+              (lcdMode == HAL_LCD_MODE_RGB_24BIT && halCfg->goudaCfg.lcd16_23Cam) ||
+              (halCfg->i2cCfg.i2c2Used && halCfg->i2cCfg.i2c2PinsCam)
+             )
+           )
+        {
+            if (!((camCfg->camUsed && camCfg->camRstRemap == GPIO_NONE) ||
+                  (camCfg->cam1Used && camCfg->cam1RstRemap == GPIO_NONE)))
+            {
+                availableGpio_B |= HAL_GPIO_BIT(10);
+            }
+            if (!((camCfg->camUsed && camCfg->camPdnRemap == GPIO_NONE) ||
+                  (camCfg->cam1Used && camCfg->cam1PdnRemap == GPIO_NONE)))
+            {
+                availableGpio_B |= HAL_GPIO_BIT(11);
+            }
+        }
+    }
+    else // cam is unused
+    {
+        availableGpio_B |= HAL_GPIO_BIT(12)
+                         | HAL_GPIO_BIT(14)
+                         | HAL_GPIO_BIT(15)
+                         | HAL_GPIO_BIT(16)
+                         | HAL_GPIO_BIT(17)
+                         | HAL_GPIO_BIT(18)
+                         | HAL_GPIO_BIT(19);
+        if (!(nand8_15Cam ||
+              (lcdMode == HAL_LCD_MODE_RGB_24BIT && halCfg->goudaCfg.lcd16_23Cam) ||
+              (halCfg->i2cCfg.i2c2Used && halCfg->i2cCfg.i2c2PinsCam)
+             )
+           )
+        {
+            availableGpio_B |= HAL_GPIO_BIT(10)
+                             | HAL_GPIO_BIT(11);
+        }
+        if (!(spiFlashCam || nand8_15Cam ||
+              (lcdMode == HAL_LCD_MODE_RGB_24BIT && halCfg->goudaCfg.lcd16_23Cam)
+             )
+           )
+        {
+            availableGpio_B |= HAL_GPIO_BIT(13)
+                             | HAL_GPIO_BIT(20)
+                             | HAL_GPIO_BIT(21)
+                             | HAL_GPIO_BIT(22)
+                             | HAL_GPIO_BIT(23)
+                             | HAL_GPIO_BIT(24);
+        }
+    }
+
+    // UART 1 Pin configuration
+    switch (halCfg->uartCfg[0])
+    {
+        case HAL_UART_CONFIG_NONE:
+            altMux |= CFG_REGS_KEYOUT_7_KEYOUT_7;
+            availableGpio_C |= HAL_GPIO_BIT(6);
+            availableGpio_A |= HAL_GPIO_BIT(14);
+            if ((halCfg->keyInMask & 0x80) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(15);
+            }
+            if ((halCfg->keyInMask & 0x80) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(16);
+            }
+            break;
+        case HAL_UART_CONFIG_DATA:
+             // use UART1 TXD, RXD
+            altMux |= CFG_REGS_KEYOUT_7_KEYOUT_7;
+            if ((halCfg->keyInMask & 0x80) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(15);
+            }
+            if ((halCfg->keyInMask & 0x80) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(16);
+            }
+            break;
+        case HAL_UART_CONFIG_FLOWCONTROL:
+             // use UART1 TXD, RXD, CTS, RTS
+            HAL_ASSERT((halCfg->keyInMask & 0x80) == 0, "Keyin 7 uses UART1 CTS");
+            HAL_ASSERT((halCfg->keyOutMask & 0x80) == 0, "Keyout 7 uses UART1 RTS");
+            altMux |= CFG_REGS_KEYOUT_7_UART1_RTS;
+            break;
+        case HAL_UART_CONFIG_MODEM:
+            // use UART1 TXD, RXD, CTS, RTS, RI, DSR, DCD, DTR
+            HAL_ASSERT((halCfg->keyInMask & 0x80) == 0, "Keyin 7 uses UART1 CTS");
+            HAL_ASSERT((halCfg->keyOutMask & 0x80) == 0, "Keyout 7 uses UART1 RTS");
+            HAL_ASSERT(!halCfg->hostUartUsed, "Host UART uses UART1 DCD/DTR");
+            HAL_ASSERT(halCfg->uartCfg[1] == HAL_UART_CONFIG_NONE,
+                    "UART 2 must be unused to use UART1 Modem lines.");
+            HAL_ASSERT((halCfg->keyInMask & 0x40) == 0, "Keyin 6 uses UART1 DSR");
+            HAL_ASSERT((halCfg->keyOutMask & 0x40) == 0, "Keyout 6 uses UART1 RI");
+            altMux |= CFG_REGS_KEYOUT_7_UART1_RTS
+                    | CFG_REGS_UART1_8LINE_UART1_8_LINE;
+            break;
+        default:
+            HAL_ASSERT(FALSE,
+                    "Invalid Uart 1 Configuration (%d).",
+                    halCfg->uartCfg[0]);
+            break;
+    }
+
+    // Host UART
+    if (halCfg->hostUartUsed)
+    {
+        HAL_ASSERT(halCfg->uartCfg[1] == HAL_UART_CONFIG_NONE,
+                "UART2 uses host UART RXD/TXD.");
+    }
+
+    // UART 2 Pin configuration
+    switch (halCfg->uartCfg[1])
+    {
+        case HAL_UART_CONFIG_NONE:
+            altMux |= CFG_REGS_UART2_HOST_UART
+                    | CFG_REGS_KEYOUT_6_KEYOUT_6;
+            if (halCfg->uartCfg[0] != HAL_UART_CONFIG_MODEM)
+            {
+                availableGpio_C |= HAL_GPIO_BIT(7)
+                                 | HAL_GPIO_BIT(8);
+            }
+            if ((halCfg->keyInMask & 0x40) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(8);
+            }
+            if ((halCfg->keyOutMask & 0x40) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(9);
+            }
+            break;
+        case HAL_UART_CONFIG_DATA:
+            // use UART2 TXD, RXD
+            altMux |= CFG_REGS_UART2_UART2
+                    | CFG_REGS_KEYOUT_6_KEYOUT_6;
+            if ((halCfg->keyInMask & 0x40) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(8);
+            }
+            if ((halCfg->keyOutMask & 0x40) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(9);
+            }
+            break;
+        case HAL_UART_CONFIG_FLOWCONTROL:
+             // use UART2 TXD, RXD, CTS, RTS
+            HAL_ASSERT((halCfg->keyInMask & 0x40) == 0, "Keyin 6 uses UART2 CTS");
+            HAL_ASSERT((halCfg->keyOutMask & 0x40) == 0, "Keyout 6 uses UART2 RTS");
+            altMux |= CFG_REGS_UART2_UART2
+                    | CFG_REGS_KEYOUT_6_UART2_RTS;
+            break;
+        case HAL_UART_CONFIG_MODEM:
+        default:
+            HAL_ASSERT(FALSE,
+                    "Invalid Uart2 Configuration (%d).",
+                    halCfg->uartCfg[1]);
+            break;
+    }
+
+    // UART 3 Pin configuration
+    switch (halCfg->uartCfg[2])
+    {
+        case HAL_UART_CONFIG_NONE:
+            availableGpio_D |= HAL_GPIO_BIT(0)
+                             | HAL_GPIO_BIT(1)
+                             | HAL_GPIO_BIT(2)
+                             | HAL_GPIO_BIT(3);
+            break;
+        case HAL_UART_CONFIG_DATA:
+            // use UART3 TXD, RXD
+            availableGpio_D |= HAL_GPIO_BIT(2)
+                             | HAL_GPIO_BIT(3);
+            break;
+        case HAL_UART_CONFIG_FLOWCONTROL:
+             // use UART3 TXD, RXD, CTS, RTS
+            break;
+        case HAL_UART_CONFIG_MODEM:
+        default:
+            HAL_ASSERT(FALSE,
+                    "Invalid Uart3 Configuration (%d).",
+                    halCfg->uartCfg[2]);
+            break;
+    }
+
+    // I2S
+    altMux |= CFG_REGS_DAI_I2S;
+    if (halCfg->i2sCfg.di0Used || halCfg->i2sCfg.di1Used ||
+        halCfg->i2sCfg.di2Used || halCfg->i2sCfg.doUsed)
+    {
+        if (!halCfg->i2sCfg.di0Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(11);
+        }
+        if (!halCfg->i2sCfg.di1Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(12);
+        }
+        if (halCfg->i2sCfg.di2Used)
+        {
+            HAL_ASSERT((halCfg->keyInMask & 0x4) == 0, "Keyin 2 uses I2S DI2");
+            altMux |= CFG_REGS_I2S_DI_2_I2S_DI_2;
+        }
+        else
+        {
+            altMux |= CFG_REGS_I2S_DI_2_KEYIN_2;
+            if ((halCfg->keyInMask & 0x4) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(2);
+            }
+        }
+        if (!halCfg->i2sCfg.doUsed)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(13);
+        }
+    }
+    else
+    {
+        availableGpio_A |= HAL_GPIO_BIT(9)
+                         | HAL_GPIO_BIT(10)
+                         | HAL_GPIO_BIT(11)
+                         | HAL_GPIO_BIT(12)
+                         | HAL_GPIO_BIT(13);
+    }
+
+    // LPS CO1
+    if (halCfg->useLpsCo1)
+    {
+        HAL_ASSERT((halCfg->keyInMask & 0x10) == 0, "Keyin 4 uses LPS_CO1");
+        altMux |= CFG_REGS_LPSCO_1_LPSCO_1;
+    }
+    else
+    {
+        altMux |= CFG_REGS_LPSCO_1_KEYIN_4;
+        if ((halCfg->keyInMask & 0x10) == 0)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(7);
+        }
+    }
+
+    // TCO
+    if (halCfg->usedTco & 0x1)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x1) == 0, "Keyout 0 uses TCO0");
+        altMux |= CFG_REGS_TCO_0_TCO_0;
+    }
+    else
+    {
+        altMux |= CFG_REGS_TCO_0_KEYOUT_0;
+        if ((halCfg->keyOutMask & 0x1) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(3);
+        }
+    }
+
+    if (halCfg->usedTco & 0x2)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x2) == 0, "Keyout 1 uses TCO1");
+        altMux |= CFG_REGS_TCO_1_TCO_1;
+    }
+    else
+    {
+        altMux |= CFG_REGS_TCO_1_KEYOUT_1;
+        if ((halCfg->keyOutMask & 0x2) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(4);
+        }
+    }
+
+    if (halCfg->usedTco & 0x4)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x4) == 0, "Keyout 2 uses TCO2");
+        altMux |= CFG_REGS_TCO_2_TCO_2;
+    }
+    else
+    {
+        altMux |= CFG_REGS_TCO_2_KEYOUT_2;
+        if ((halCfg->keyOutMask & 0x4) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(5);
+        }
+    }
+
+    // PWM
+    if (halCfg->pwmCfg.pwtUsed)
+    {
+        HAL_ASSERT((halCfg->keyInMask & 0x20) == 0, "Keyin 5 uses PWT");
+        altMux |= CFG_REGS_GPO_0_PWT;
+    }
+    else if (halCfg->keyInMask & 0x20)
+    {
+        altMux |= CFG_REGS_GPO_0_KEYIN_5;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_0_GPO_0;
+        availableGpo_A |= HAL_GPO_BIT(0);
+    }
+
+    if (halCfg->pwmCfg.lpgUsed)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x20) == 0, "Keyout 5 uses LPG");
+        altMux |= CFG_REGS_GPO_1_LPG;
+    }
+    else if (halCfg->keyOutMask & 0x20)
+    {
+        altMux |= CFG_REGS_GPO_1_KEYOUT_5;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_1_GPO_1;
+        availableGpo_A |= HAL_GPO_BIT(1);
+    }
+
+    if (halCfg->pwmCfg.pwl1Used)
+    {
+        HAL_ASSERT(!halCfg->useClk32k, "Clk 32k uses PWL1");
+        altMux |= CFG_REGS_GPO_2_PWL_1;
+    }
+    else if (halCfg->useClk32k)
+    {
+        // Default to GPO low output
+        // 32K clock will be enabled per request
+        //altMux |= CFG_REGS_GPO_2_CLK_32K;
+        altMux |= CFG_REGS_GPO_2_GPO_2;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_2_GPO_2;
+        availableGpo_A |= HAL_GPO_BIT(2);
+    }
+
+    // Clock out and host clock
+    if (halCfg->clkOutUsed)
+    {
+        HAL_ASSERT(!halCfg->hostClkUsed, "HST_CLK uses CLK_OUT pin");
+        altMux |= CFG_REGS_CLK_OUT_CLK_OUT;
+    }
+    else if (halCfg->hostClkUsed)
+    {
+        altMux |= CFG_REGS_CLK_OUT_HST_CLK;
+    }
+    else
+    {
+        altMux |= CFG_REGS_CLK_OUT_HST_CLK;
+        availableGpo_A |= HAL_GPO_BIT(8);
+    }
+
+    // SPI
+    if (halCfg->spiCfg[0].cs0Used || halCfg->spiCfg[0].cs1Used ||
+        halCfg->spiCfg[0].cs2Used)
+    {
+        HAL_ASSERT(!(halCfg->modemSpiCfg[0].cs0Used ||
+                     halCfg->modemSpiCfg[0].cs1Used ||
+                     halCfg->modemSpiCfg[0].cs2Used), "Modem SPI1 is in use");
+        altMux |= CFG_REGS_AP_SPI1_AP_SPI1;
+        if (!halCfg->spiCfg[0].cs0Used)
+        {
+            availableGpio_C |= HAL_GPIO_BIT(22);
+        }
+        if (!halCfg->spiCfg[0].cs1Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(17);
+        }
+        if (halCfg->spiCfg[0].cs2Used)
+        {
+            HAL_ASSERT((halCfg->keyInMask & 0x2) == 0, "Keyin 1 uses SPI1 CS2");
+            altMux |= CFG_REGS_SPI1_CS_2_SPI1_CS_2;
+        }
+        else
+        {
+            altMux |= CFG_REGS_SPI1_CS_2_KEYIN_1;
+            if ((halCfg->keyInMask & 0x2) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(1);
+            }
+        }
+        if (!halCfg->spiCfg[0].di0Used)
+        {
+            availableGpio_C |= HAL_GPIO_BIT(23);
+        }
+        if (!halCfg->spiCfg[0].di1Used)
+        {
+            availableGpio_C |= HAL_GPIO_BIT(24);
+        }
+    }
+    else // AP SPI1 unused
+    {
+        altMux |= CFG_REGS_AP_SPI1_BB_SPI1;
+        if (halCfg->modemSpiCfg[0].cs0Used || halCfg->modemSpiCfg[0].cs1Used ||
+            halCfg->modemSpiCfg[0].cs2Used)
+        {
+            if (!halCfg->modemSpiCfg[0].cs0Used)
+            {
+                availableGpio_C |= HAL_GPIO_BIT(22);
+            }
+            if (!halCfg->modemSpiCfg[0].cs1Used)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(17);
+            }
+            if (!halCfg->modemSpiCfg[0].di0Used)
+            {
+                availableGpio_C |= HAL_GPIO_BIT(23);
+            }
+            if (!halCfg->modemSpiCfg[0].di1Used)
+            {
+                availableGpio_C |= HAL_GPIO_BIT(24);
+            }
+        }
+        else
+        {
+            availableGpio_A |= HAL_GPIO_BIT(17);
+            availableGpio_C |= HAL_GPIO_BIT(21)
+                             | HAL_GPIO_BIT(22)
+                             | HAL_GPIO_BIT(23)
+                             | HAL_GPIO_BIT(24);
+            if ((halCfg->keyInMask & 0x2) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(1);
+            }
+        }
+    }
+    if (halCfg->spiCfg[1].cs0Used || halCfg->spiCfg[1].cs1Used)
+    {
+        if (!halCfg->spiCfg[1].cs0Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(5);
+        }
+        if (halCfg->spiCfg[1].cs1Used)
+        {
+            HAL_ASSERT((halCfg->keyInMask & 0x8) == 0, "Keyin 3 uses SPI2 CS1");
+            altMux |= CFG_REGS_KEYIN_3_SPI2_CS_1;
+        }
+        else
+        {
+            altMux |= CFG_REGS_KEYIN_3_KEYIN_3;
+            if ((halCfg->keyInMask & 0x8) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(6);
+            }
+        }
+        if (!halCfg->spiCfg[1].di0Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(3);
+        }
+        if (!halCfg->spiCfg[1].di1Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(4);
+        }
+    }
+    else // AP SPI2 unused
+    {
+        availableGpio_A |= HAL_GPIO_BIT(2)
+                         | HAL_GPIO_BIT(3)
+                         | HAL_GPIO_BIT(4)
+                         | HAL_GPIO_BIT(5);
+        if ((halCfg->keyInMask & 0x8) == 0)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(6);
+        }
+    }
+
+    // Standalone keyin/out
+    if ((halCfg->keyInMask & 0x1) == 0)
+    {
+        availableGpio_B |= HAL_GPIO_BIT(0);
+    }
+
+    // SDMMC
+    if (!halCfg->sdmmcCfg.sdmmcUsed)
+    {
+        availableGpio_C |= HAL_GPIO_BIT(9)
+                         | HAL_GPIO_BIT(10)
+                         | HAL_GPIO_BIT(11)
+                         | HAL_GPIO_BIT(12)
+                         | HAL_GPIO_BIT(13)
+                         | HAL_GPIO_BIT(14);
+    }
+    if (!halCfg->sdmmcCfg.sdmmc2Used)
+    {
+        availableGpio_C |= HAL_GPIO_BIT(15)
+                         | HAL_GPIO_BIT(16)
+                         | HAL_GPIO_BIT(17)
+                         | HAL_GPIO_BIT(18)
+                         | HAL_GPIO_BIT(19)
+                         | HAL_GPIO_BIT(20);
+    }
+    HAL_ASSERT(!(parallelNandUsed && halCfg->sdmmcCfg.sdmmc3Used),
+        "Parallel NAND uses SDMMC3 pins");
+
+    // SIM
+    if (!hal_BoardSimUsed(2))
+    {
+        availableGpio_C |= HAL_GPIO_BIT(25)
+                         | HAL_GPIO_BIT(26)
+                         | HAL_GPIO_BIT(27);
+    }
+
+    if (!hal_BoardSimUsed(3))
+    {
+        availableGpio_C |= HAL_GPIO_BIT(28)
+                         | HAL_GPIO_BIT(29)
+                         | HAL_GPIO_BIT(30);
+    }
+
+    UINT32 gpioMask;
+    // GPIO_C mask check
+    gpioMask = ~availableGpio_C & halCfg->usedGpio_C;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO C are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_C & halCfg->noConnectGpio_C;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO C declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_C & halCfg->noConnectGpio_C;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO C declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_C &
+               (~halCfg->usedGpio_C & ~halCfg->noConnectGpio_C);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO C declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPIO_A mask check
+    gpioMask = ~availableGpio_A & halCfg->usedGpio_A;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO A are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_A & halCfg->noConnectGpio_A;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO A declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_A & halCfg->noConnectGpio_A;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO A declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_A &
+               (~halCfg->usedGpio_A & ~halCfg->noConnectGpio_A);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO A declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPIO_B mask check
+    gpioMask = ~availableGpio_B & halCfg->usedGpio_B;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO B are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_B & halCfg->noConnectGpio_B;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO B declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_B & halCfg->noConnectGpio_B;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO B declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_B &
+               (~halCfg->usedGpio_B & ~halCfg->noConnectGpio_B);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO B declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPIO_D mask check
+    gpioMask = ~availableGpio_D & halCfg->usedGpio_D;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO D are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_D & halCfg->noConnectGpio_D;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO D declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_D & halCfg->noConnectGpio_D;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO D declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_D &
+               (~halCfg->usedGpio_D & ~halCfg->noConnectGpio_D);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO D declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPO_A mask check
+    gpioMask = ~availableGpo_A & halCfg->usedGpo_A;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPO A are not available (0x%x)",
+               gpioMask);
+
+#endif // !FPGA
+
+    // Set IO drive
+    hwp_configRegs->IO_Drive1_Select = halCfg->ioDrive.select1;
+    hwp_configRegs->IO_Drive2_Select = halCfg->ioDrive.select2;
+
+    // Set the not connected ones as output and drive 0
+    // But keep boot mode GPIOs as input to avoid current leakage
+    noConnectMask_C = halCfg->noConnectGpio_C & ~bootModeGpio_C;
+    noConnectMask_A = halCfg->noConnectGpio_A & ~bootModeGpio_A;
+    noConnectMask_B = halCfg->noConnectGpio_B & ~bootModeGpio_B;
+    noConnectMask_D = halCfg->noConnectGpio_D & ~bootModeGpio_D;
+
+    hwp_gpio->gpio_clr = noConnectMask_C;
+    hwp_gpio->gpio_oen_set_out = noConnectMask_C;
+
+    hwp_apGpioA->gpio_clr = noConnectMask_A;
+    hwp_apGpioA->gpio_oen_set_out = noConnectMask_A;
+
+    hwp_apGpioB->gpio_clr = noConnectMask_B;
+    hwp_apGpioB->gpio_oen_set_out = noConnectMask_B;
+
+    hwp_apGpioD->gpio_clr = noConnectMask_D;
+    hwp_apGpioD->gpio_oen_set_out = noConnectMask_D;
+
+    // Init GPO_A values
+    if (halCfg->useClk32k)
+    {
+        // Init 32K clock pin to low (by setting up GPO)
+        hwp_apGpioA->gpo_clr = availableGpo_A
+                             | HAL_GPO_BIT(2);
+    }
+    else
+    {
+	/* if GPO_1 used for usb id, it should be high */
+	#if defined(_TGT_AP_GPIO_USBID_CTRL)
+		hwp_apGpioA->gpo_clr = availableGpo_A & ~0x2;
+	#else
+		hwp_apGpioA->gpo_clr = availableGpo_A;
+	#endif
+    }
+
+    // Configure MUX after initializing all the GPO pins
+    // (GPIO pins are in input mode by default)
+
+    // Set GPIO mode
+    hwp_configRegs->BB_GPIO_Mode = availableGpio_C;
+    hwp_configRegs->AP_GPIO_A_Mode = availableGpio_A;
+    hwp_configRegs->AP_GPIO_B_Mode = availableGpio_B;
+    hwp_configRegs->AP_GPIO_D_Mode = availableGpio_D;
+    // Set Alt Mux configuration
+    hwp_configRegs->Alt_mux_select = altMux;
+
+    // --------------------------------------------------
+    // As of now, all connected GPIOs, which are as GPIO
+    // or not used at all but connected are configured as
+    // GPIOs in input mode, except for Gouda reset pins
+    // --------------------------------------------------
+
+}
+
+
+// =============================================================================
+// hal_BoardSetup
+// -----------------------------------------------------------------------------
+/// Apply board dependent configuration to HAL
+/// @param halCfg Pointer to HAL configuration structure (from the target
+/// module).
+// ============================================================================
+//PROTECTED VOID hal_BoardSetup(CONST HAL_CFG_CONFIG_T* halCfg)
+PUBLIC INT32 hal_BoardSetup(INT8 run_mode)
+{
+	g_bootBootMode = rda_hwcfg_get();
+	hal_BoardSetupGeneral(&hal_cfg);
+
+	if(g_halConfigError)
+		return CMD_RET_FAILURE;
+	else
+		return CMD_RET_SUCCESS;
+}
diff --git a/board/rda/rda8850/u-boot-spl.lds b/board/rda/rda8850/u-boot-spl.lds
new file mode 100644
index 0000000000..afe35fd2a8
--- /dev/null
+++ b/board/rda/rda8850/u-boot-spl.lds
@@ -0,0 +1,35 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00100100;
+	. = ALIGN(4);
+	.text :
+	{
+		__start = .;
+		arch/arm/cpu/armv7/start.o (.text)
+			*(.text)
+	}
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+	. = ALIGN(4);
+	.data : {
+		*(.data)
+	}
+	. = ALIGN(4);
+	. = .;
+	. = ALIGN(4);
+	__image_copy_end = .;
+	_end = .;
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+		ASSERT((ABSOLUTE(__bss_end__) < 0x00110000), \
+			"too big data in spl, don't exceed intrenal ram");
+	}
+}
diff --git a/board/rda/rda8850e/Makefile b/board/rda/rda8850e/Makefile
new file mode 100644
index 0000000000..c4aa06a9a7
--- /dev/null
+++ b/board/rda/rda8850e/Makefile
@@ -0,0 +1,82 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS-y	+= clock_config.o clock.o ddr.o
+else
+COBJS-$(CONFIG_MACH_RDA8850E) += hal_config.o
+endif
+
+RDA_TARGET_DEF_FILE := $(ANDROID_BUILD_TOP)/$(RDA_TARGET_DEVICE_DIR)/target.def
+RDA_GET_MAKEFILE_VAR_FUNC = $(strip $(shell sed -n 's/^[ 	]*$(1)[ 	]*[?:]\?=\([^\#]\+\)\#*.*$$/\1/p' $(2)))
+
+NUMBER_OF_SIM := $(call RDA_GET_MAKEFILE_VAR_FUNC,NUMBER_OF_SIM,$(RDA_TARGET_DEF_FILE))
+ifeq ($(NUMBER_OF_SIM),)
+$(error Failed to get NUMBER_OF_SIM in $(RDA_TARGET_DEF_FILE))
+endif
+
+USER_SIM_ORDER := $(call RDA_GET_MAKEFILE_VAR_FUNC,USER_SIM_ORDER,$(RDA_TARGET_DEF_FILE))
+ifeq ($(USER_SIM_ORDER),)
+$(error Failed to get USER_SIM_ORDER in $(RDA_TARGET_DEF_FILE))
+endif
+
+NULL_STRING :=
+SPACE := ${NULL_STRING} # end of the line
+COMMA := ,
+TGT_SIM_ORDER := $(foreach SIM,$(USER_SIM_ORDER),$(SIM)$(COMMA))
+TGT_SIM_ORDER := $(subst ${SPACE},,${TGT_SIM_ORDER})
+
+CPPFLAGS_board/$(BOARDDIR)/hal_config.o += -I$(TOPDIR)/board/$(VENDOR)/common/include -DTGT_SIM_ORDER=$(TGT_SIM_ORDER) -DNUMBER_OF_SIM=$(NUMBER_OF_SIM)
+
+ifeq ($(strip $(TARGET_TABLET_MODE)),true)
+CPPFLAGS_board/$(BOARDDIR)/clock.o += -DTARGET_TABLET_MODE
+endif
+
+COBJS   := $(COBJS-y)
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak *~ .depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/rda/rda8850e/clock.c b/board/rda/rda8850e/clock.c
new file mode 100644
index 0000000000..884b6c9259
--- /dev/null
+++ b/board/rda/rda8850e/clock.c
@@ -0,0 +1,2331 @@
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/rda_iomap.h>
+#include <asm/io.h>
+#include <asm/arch/reg_sysctrl.h>
+#include <asm/arch/hwcfg.h>
+#include <asm/arch/ispi.h>
+#include <asm/arch/rda_sys.h>
+#include "clock_config.h"
+#include "debug.h"
+#include "ddr.h"
+#include "tgt_ap_clock_config.h"
+
+#if (PMU_VBUCK3_VAL < 0 || PMU_VBUCK3_VAL > 15)
+#error "Invalid PMU_VBUCK3_VAL"
+#endif
+
+#ifdef PMU_VBUCK5_VAL
+#if (PMU_VBUCK5_VAL < 0 || PMU_VBUCK5_VAL > 15)
+#error "Invalid PMU_VBUCK5_VAL"
+#endif
+#endif
+
+//#define DO_DDR_PLL_DEBUG
+
+#define RDA_PMU_VBUCK4_BIT_ACT_SHIFT     (4)
+#define RDA_PMU_VBUCK4_BIT_ACT_MASK      (0xf<<4)
+#define RDA_PMU_VBUCK4_BIT_ACT(n)        (((n)&0xf)<<4)
+
+/* This macro is used to select GPU, VPU, CPU clock value manully */
+//#define TGT_AP_SELECT_CLK
+/* For staying so that watching register value */
+#ifdef TGT_AP_SELECT_CLK
+#define DO_STAY_FOR_WATCHING
+#endif
+#define PMU_REG_VIBRATOR_NUM 3
+#define PMU_REG_VIBRATOR_BIT 5
+
+const static UINT32 test_pattern[] =
+{
+
+          0xa5a5a5a5, 0x5a5a5a5a,
+
+          0x4f35b7da, 0x8e354c91,
+
+          0x00000000, 0xFFFFFFFF,
+
+          0x00000000, 0x00000000,
+
+          0x0000FFFF, 0x00000000,
+};
+
+enum {
+	AP_CPU_CLK_IDX = 0,
+	AP_BUS_CLK_IDX,
+	AP_MEM_CLK_IDX,
+	AP_USB_CLK_IDX,
+};
+
+static int pll_enabled(int idx)
+{
+	if ((hwp_sysCtrlAp->Cfg_Pll_Ctrl[idx] &
+			(SYS_CTRL_AP_AP_PLL_ENABLE_MASK |
+			 SYS_CTRL_AP_AP_PLL_LOCK_RESET_MASK)) ==
+			(SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE |
+			 SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET))
+		return 1;
+	else
+		return 0;
+}
+
+static int usb_in_use = 0;
+
+static void check_usb_usage(void)
+{
+	unsigned int mask = SYS_CTRL_AP_BUS_SEL_FAST_SLOW |
+		SYS_CTRL_AP_PLL_LOCKED_BUS_MASK |
+		SYS_CTRL_AP_PLL_LOCKED_USB_MASK;
+	unsigned int reg = SYS_CTRL_AP_BUS_SEL_FAST_FAST |
+		SYS_CTRL_AP_PLL_LOCKED_BUS_LOCKED |
+		SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED;
+
+	if ((hwp_sysCtrlAp->Sel_Clock & mask) == reg &&
+			pll_enabled(AP_BUS_CLK_IDX) &&
+			pll_enabled(AP_USB_CLK_IDX))
+		usb_in_use = 1;
+	else
+		usb_in_use = 0;
+}
+
+#ifndef CONFIG_RDA_FPGA
+struct pll_freq {
+	UINT32 freq_mhz;
+	UINT16 major;
+	UINT16 minor;
+	UINT16 with_div;
+	UINT16 div;
+};
+
+struct pmu_reg {
+	UINT32 reg_num;
+	UINT32 reg_val;
+};
+
+static const struct pmu_reg pmu_reg_table[] = {
+		{0x3f, 0x30fb},/*set nand protect battery voltage:
+			0x30f3:2.4v  0x30f7:2.7v  0x30fb:3.0v  0x30ff:3.2v*/
+		//{0x01, 0x000b},/*enable nand protect, 0x000a in default*/
+		{0x03, 0x1853},/*shut down vbuck1, vasw, vcam, vlcd, vmic,bb1_led voltage*/
+		{0x04, 0x9670},/* vmc_vsel_act = 0 */
+		{0x0f, 0x1e90},/* enable bandgap chopper mode */
+		{0x13, 0x3b70},
+		{0x2d, 0x96ae},/*all dcdc settings are set to 0x96ae */
+		{0x2e, 0x96ae},/*all dcdc settings are set to 0x96ae */
+		{0x2f, 0x9244},
+		{0x53, 0x9505}, /*vbuck5 val = 8, vout_sel_buck5_lp = 0 */
+		{0x0d, 0x8280},/* shut down vbuck4 voltage.If backlight need, please open. */
+		{0x36, 0x6e45},
+		{0x2a, 0xaa45},
+		{0x4a, 0x96ae},/*all dcdc settings are set to 0x96ae */
+		{0x4b, 0x96ae},/*all dcdc settings are set to 0x96ae */
+		{0x54, 0x96ae},/*all dcdc settings are set to 0x96ae */
+};
+
+typedef enum {
+	PLL_REG_CPU_BASE = 0x00,
+	PLL_REG_BUS_BASE = 0x20,
+	PLL_REG_MEM_BASE = 0x60,
+	PLL_REG_USB_BASE = 0x80,
+} PLL_REG_BASE_INDEX_t;
+
+typedef enum {
+	PLL_REG_OFFSET_01H = 1,
+	PLL_REG_OFFSET_02H = 2,
+	PLL_REG_OFFSET_DIV = 3,
+	PLL_REG_OFFSET_04H = 4,
+	PLL_REG_OFFSET_MAJOR = 5,
+	PLL_REG_OFFSET_MINOR = 6,
+	PLL_REG_OFFSET_07H = 7,
+} PLL_REG_OFFSET_INDEX_t;
+
+static const struct pll_freq pll_freq_table[] = {
+	/* MHz Major   Minor   div */
+	{1600, 0x7B13, 0xB138, 0, 0x0000},
+	{1200, 0x5C4E, 0xC4EC, 0, 0x0000},
+	{1150, 0x5876, 0x2762, 0, 0x0000},
+	{1100, 0x549D, 0x89D8, 0, 0x0000},
+	{1050, 0x50C4, 0xEC4E, 0, 0x0000},
+	{1020, 0x4E76, 0x2762, 0, 0x0000},
+	{1010, 0x4DB1, 0x3B13, 0, 0x0000},
+	{1000, 0x4CEC, 0x4EC4, 0, 0x0000},
+	{ 988, 0x4C00, 0x0000, 0, 0x0000},
+	{ 962, 0x4A00, 0x0000, 0, 0x0000},
+	{ 936, 0x4800, 0x0000, 0, 0x0000},
+	{ 910, 0x4600, 0x0000, 0, 0x0000},
+	{ 884, 0x4400, 0x0000, 0, 0x0000},
+	{ 858, 0x4200, 0x0000, 0, 0x0000},
+	{ 832, 0x4000, 0x0000, 0, 0x0000},
+	{ 806, 0x3E00, 0x0000, 0, 0x0000},
+	{ 800, 0x3D89, 0xD89C, 0, 0x0000},
+	{ 780, 0x3C00, 0x0000, 0, 0x0000},
+	{ 750, 0x39B1, 0x3B13, 0, 0x0000},
+	{ 600, 0x2E27, 0x6274, 0, 0x0000},
+	{ 520, 0x2800, 0x0000, 0, 0x0000},
+	{ 519, 0x27EC, 0x4EC4, 1, 0x0007},
+	{ 500, 0x2676, 0x2762, 1, 0x0007},
+	{ 480, 0x24EC, 0x4EC4, 0, 0x0000},
+	{ 455, 0x2300, 0x0000, 1, 0x0007},
+	{ 416, 0x2000, 0x0000, 1, 0x0007},
+	{ 400, 0x1EC4, 0xEC4C, 1, 0x0007},
+};
+static const struct pll_freq pll_ddr_freq_table[] = {
+	/* MHz Major   Minor   div */
+	{ 600, 0x2E27, 0x6274, 1, 0xC497},
+	{ 590, 0x2D62, 0x7624, 1, 0xC497},
+	{ 573, 0x2C13, 0xB138, 1, 0xC497},
+	{ 555, 0x2AB1, 0x3B10, 1, 0xC497},
+	{ 538, 0x2962, 0x7624, 1, 0xC497},
+	{ 519, 0x27EC, 0x4EC4, 1, 0xC497},
+	{ 500, 0x2676, 0x2760, 1, 0xC397},
+	{ 480, 0x24EC, 0x4EC4, 1, 0xC297},
+	{ 455, 0x2300, 0x0000, 1, 0xC097},
+	{ 429, 0x2100, 0x0000, 1, 0xC097},
+	{ 416, 0x2000, 0x0000, 1, 0xC897},
+	{ 403, 0x1F00, 0x0000, 1, 0xC897},
+	{ 400, 0x1EC4, 0xEC4C, 1, 0xC897},
+	{ 397, 0x1E89, 0xD89C, 1, 0xC897},
+	{ 390, 0x1E00, 0x0000, 1, 0xC897},
+	{ 383, 0x1D76, 0x2760, 1, 0xC897},
+	{ 377, 0x1D00, 0x0000, 1, 0xD397},
+	{ 370, 0x1C76, 0x2760, 1, 0xD297},
+	{ 364, 0x1C00, 0x0000, 1, 0xD297},
+	{ 358, 0x1B89, 0xD89C, 1, 0xD197},
+	{ 355, 0x369D, 0x89D8, 0, 0xD097},
+	{ 351, 0x3600, 0x0000, 0, 0xD097},
+	{ 338, 0x3400, 0x0000, 0, 0xC897},
+	{ 333, 0x333B, 0x13B0, 0, 0xC897},
+	{ 328, 0x3276, 0x2760, 0, 0xC897},
+	{ 325, 0x3200, 0x0000, 0, 0xC897},
+	{ 321, 0x3162, 0x7624, 0, 0xC897},
+	{ 316, 0x309D, 0x89D8, 0, 0xC897},
+	{ 312, 0x3000, 0x0000, 0, 0xD897},
+	{ 290, 0x2C9D, 0x89D8, 0, 0xE097},
+	{ 260, 0x2800, 0x0000, 0, 0xF097},
+	{ 200, 0x1EC4, 0xEC4C, 1, 0xB996},
+	{ 156, 0x3000, 0x0000, 0, 0x0006},
+	{ 100, 0x1EC4, 0xEC4C, 1, 0x0005},
+	{  50, 0x1EC4, 0xEC4C, 1, 0x0004},
+};
+
+static const struct clock_config *g_clock_config;
+
+#ifdef DO_DDR_PLL_DEBUG
+static struct clock_config clock_debug_config;
+static UINT32 ddrfreq = 400, ddr32bit = 0;
+#endif
+
+static void sys_shutdown_pll(void)
+{
+	int i;
+
+	hwp_sysCtrlAp->REG_DBG = AP_CTRL_PROTECT_UNLOCK;
+
+	if (usb_in_use) {
+		hwp_sysCtrlAp->Sel_Clock = SYS_CTRL_AP_SLOW_SEL_RF_RF
+			| SYS_CTRL_AP_CPU_SEL_FAST_SLOW
+			| SYS_CTRL_AP_BUS_SEL_FAST_FAST
+			| SYS_CTRL_AP_TIMER_SEL_FAST_FAST;
+	} else {
+		hwp_sysCtrlAp->Sel_Clock = SYS_CTRL_AP_SLOW_SEL_RF_RF
+			| SYS_CTRL_AP_CPU_SEL_FAST_SLOW
+			| SYS_CTRL_AP_BUS_SEL_FAST_SLOW
+			| SYS_CTRL_AP_TIMER_SEL_FAST_FAST;
+	}
+
+	for (i = 0; i < 3; i++) {
+		/* In download mode, rom code has been set ap bus*/
+		if (usb_in_use) {
+			if (i == AP_BUS_CLK_IDX) // ap bus
+				continue;
+		}
+		hwp_sysCtrlAp->Cfg_Pll_Ctrl[i] =
+			SYS_CTRL_AP_AP_PLL_ENABLE_POWER_DOWN |
+			SYS_CTRL_AP_AP_PLL_LOCK_RESET_RESET;
+	}
+}
+
+static void sys_setup_pll(void)
+{
+	int i;
+	UINT32 mask;
+	UINT32 locked;
+	int cnt = 10; //10us, according to IC, the pll must be locked
+
+	hwp_sysCtrlAp->REG_DBG = AP_CTRL_PROTECT_UNLOCK;
+
+	for (i = 0; i < 3; i++) {
+		/* In download mode, rom code has been set ap bus*/
+		if (usb_in_use) {
+			if (i == AP_BUS_CLK_IDX) // ap bus
+				continue;
+		}
+
+		if (AP_MEM_CLK_IDX == i)
+			hwp_sysCtrlAp->Cfg_Pll_Ctrl[i] =
+				SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE |
+				SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET |
+				SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(1)|
+				SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(30);
+		else
+			hwp_sysCtrlAp->Cfg_Pll_Ctrl[i] =
+				SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE |
+				SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET |
+				SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(6)|
+				SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(30);
+	}
+
+	mask = SYS_CTRL_AP_PLL_LOCKED_CPU_MASK
+	    | SYS_CTRL_AP_PLL_LOCKED_BUS_MASK
+	    | SYS_CTRL_AP_PLL_LOCKED_MEM_MASK
+	    //| SYS_CTRL_AP_PLL_LOCKED_USB_MASK
+	    ;
+	locked = SYS_CTRL_AP_PLL_LOCKED_CPU_LOCKED
+	    | SYS_CTRL_AP_PLL_LOCKED_BUS_LOCKED
+	    | SYS_CTRL_AP_PLL_LOCKED_MEM_LOCKED
+	    //| SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED
+	    ;
+
+	while (((hwp_sysCtrlAp->Sel_Clock & mask) != locked) && cnt) {
+		udelay(1);
+		cnt--;
+	}
+	if (cnt == 0) {
+		printf("WARNING, cannot lock cpu/bus/mem pll 0x%08x ",
+			hwp_sysCtrlAp->Sel_Clock);
+		printf("but we run anyway ...\n");
+	}
+
+	for (i = 0; i < 3; i++) {
+		hwp_sysCtrlAp->Cfg_Pll_Ctrl[i] |=
+		    SYS_CTRL_AP_AP_PLL_CLK_FAST_ENABLE_ENABLE;
+	}
+
+	hwp_sysCtrlAp->Sel_Clock = SYS_CTRL_AP_SLOW_SEL_RF_RF
+	    | SYS_CTRL_AP_CPU_SEL_FAST_FAST
+	    | SYS_CTRL_AP_BUS_SEL_FAST_FAST
+	    | SYS_CTRL_AP_TIMER_SEL_FAST_FAST;
+}
+
+static void sys_setup_clk(void)
+{
+	// Disable some power-consuming clocks
+#ifdef CONFIG_VPU_TEST
+	hwp_sysCtrlAp->Clk_APO_Enable = SYS_CTRL_AP_ENABLE_APOC_VPU;
+	//hwp_sysCtrlAp->Clk_MEM_Enable = SYS_CTRL_AP_ENABLE_MEM_VPU;
+#else
+	hwp_sysCtrlAp->Clk_APO_Disable = SYS_CTRL_AP_DISABLE_APOC_VPU;
+	//hwp_sysCtrlAp->Clk_MEM_Disable = SYS_CTRL_AP_DISABLE_MEM_VPU;
+#endif
+
+	// Init clock gating mode
+	hwp_sysCtrlAp->Clk_CPU_Mode = 0;
+#ifdef CONFIG_VPU_TEST
+	hwp_sysCtrlAp->Clk_AXI_Mode = SYS_CTRL_AP_MODE_AXI_DMA_MANUAL | SYS_CTRL_AP_MODE_APB0_CONF_MANUAL;
+#else
+	hwp_sysCtrlAp->Clk_AXI_Mode = SYS_CTRL_AP_MODE_AXI_DMA_MANUAL;
+#endif
+	hwp_sysCtrlAp->Clk_AXIDIV2_Mode = 0;
+	hwp_sysCtrlAp->Clk_GCG_Mode = SYS_CTRL_AP_MODE_GCG_GOUDA_MANUAL
+				| SYS_CTRL_AP_MODE_GCG_CAMERA_MANUAL;
+	hwp_sysCtrlAp->Clk_AHB1_Mode = 0;
+	hwp_sysCtrlAp->Clk_APB1_Mode = 0;
+	hwp_sysCtrlAp->Clk_APB2_Mode = 0;
+#ifdef CONFIG_VPU_TEST
+	hwp_sysCtrlAp->Clk_MEM_Mode = SYS_CTRL_AP_MODE_CLK_MEM_MANUAL;
+#else
+	hwp_sysCtrlAp->Clk_MEM_Mode = 0;
+#endif
+	//hwp_sysCtrlAp->Clk_APO_Mode = SYS_CTRL_AP_MODE_APOC_VPU_MANUAL;
+
+	// Init module frequency
+	hwp_sysCtrlAp->Cfg_Clk_AP_CPU = g_clock_config->CLK_CPU;
+	hwp_sysCtrlAp->Cfg_Clk_AP_AXI = g_clock_config->CLK_AXI;
+	hwp_sysCtrlAp->Cfg_Clk_AP_GCG = g_clock_config->CLK_GCG;
+
+	if (!usb_in_use) {
+		hwp_sysCtrlAp->Cfg_Clk_AP_AHB1 = g_clock_config->CLK_AHB1;
+	}
+
+	hwp_sysCtrlAp->Cfg_Clk_AP_APB1 = g_clock_config->CLK_APB1;
+	hwp_sysCtrlAp->Cfg_Clk_AP_APB2 = g_clock_config->CLK_APB2;
+	hwp_sysCtrlAp->Cfg_Clk_AP_MEM = g_clock_config->CLK_MEM;
+	hwp_sysCtrlAp->Cfg_Clk_AP_GPU = g_clock_config->CLK_GPU;
+	hwp_sysCtrlAp->Cfg_Clk_AP_VPU = g_clock_config->CLK_VPU;
+	hwp_sysCtrlAp->Cfg_Clk_AP_VOC = g_clock_config->CLK_VOC;
+	hwp_sysCtrlAp->Cfg_Clk_AP_SFLSH = g_clock_config->CLK_SFLSH;
+}
+
+static void print_sys_reg(char *name, UINT32 value)
+{
+	printf("clk %s = %lx\n", name, value);
+}
+
+static void sys_dump_clk(void)
+{
+	print_sys_reg("CPU", hwp_sysCtrlAp->Cfg_Clk_AP_CPU);
+	print_sys_reg("AXI", hwp_sysCtrlAp->Cfg_Clk_AP_AXI);
+	print_sys_reg("GCG", hwp_sysCtrlAp->Cfg_Clk_AP_GCG);
+	print_sys_reg("AHB1", hwp_sysCtrlAp->Cfg_Clk_AP_AHB1);
+	print_sys_reg("APB1", hwp_sysCtrlAp->Cfg_Clk_AP_APB1);
+	print_sys_reg("APB2", hwp_sysCtrlAp->Cfg_Clk_AP_APB2);
+	print_sys_reg("MEM", hwp_sysCtrlAp->Cfg_Clk_AP_MEM);
+	print_sys_reg("GPU", hwp_sysCtrlAp->Cfg_Clk_AP_GPU);
+	print_sys_reg("VPU", hwp_sysCtrlAp->Cfg_Clk_AP_VPU);
+	print_sys_reg("VOC", hwp_sysCtrlAp->Cfg_Clk_AP_VOC);
+	print_sys_reg("SFLSH", hwp_sysCtrlAp->Cfg_Clk_AP_SFLSH);
+}
+
+static int pll_freq_set(UINT32 reg_base, UINT32 freq_mhz)
+{
+	int i;
+	const struct pll_freq *freq;
+	unsigned int major, minor;
+	unsigned short value_02h;
+
+	/* find pll_freq */
+	for (i = 0; i < ARRAY_SIZE(pll_freq_table); i++) {
+		if (pll_freq_table[i].freq_mhz == freq_mhz)
+			break;
+	}
+	if (i >= ARRAY_SIZE(pll_freq_table)) {
+		printf("pll_freq_set, fail to find freq\n");
+		return -1;
+	}
+
+	freq = &pll_freq_table[i];
+	if (freq->with_div && (reg_base == PLL_REG_MEM_BASE)) {
+		if (freq_mhz >= 200)
+			ispi_reg_write(reg_base + PLL_REG_OFFSET_DIV, freq->div & 0x7fff);
+		mdelay(5);
+		ispi_reg_write(reg_base + PLL_REG_OFFSET_DIV,
+				freq->div);
+		// Calculate the real MEM PLL freq
+		freq_mhz *= (1 << (8 - (freq->div & 0x7)));
+	}
+	if (freq_mhz >= 800 || reg_base == PLL_REG_USB_BASE) {
+		value_02h = 0x030B;
+		// Div PLL freq by 2
+		minor = ((freq->major & 0xFFFF) << 14) |
+			((freq->minor >> 2) & 0x3FFF);
+		minor >>= 1;
+		// Recalculate the divider
+		major = (minor >> 14) & 0xFFFF;
+		minor = (minor << 2) & 0xFFFF;
+	} else {
+		value_02h = 0x020B;
+		major = freq->major;
+		minor = freq->minor;
+	}
+
+	if(reg_base == PLL_REG_USB_BASE)
+		ispi_reg_write(reg_base + 0x9, 0x7100);
+	if (reg_base == PLL_REG_USB_BASE)
+		value_02h ^= (1 << 8);
+#ifndef _TGT_AP_CPU_PLL_FREQ_AUTO_REGULATE
+	if(reg_base == PLL_REG_CPU_BASE) {
+		/* Disable pll freq divided by 2 when VCore voltage is lower than a threshold value. */
+		if(rda_metal_id_get() > 1)
+			ispi_reg_write(reg_base + PLL_REG_OFFSET_DIV, 0x72A2);
+	}
+#endif
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_02H, value_02h);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_MAJOR, major);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_MINOR, minor);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_07H, 0x0012);
+	mdelay(1);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_07H, 0x0013);
+	return 0;
+}
+
+static int pll_ddr_freq_set(UINT32 reg_base, UINT32 freq_mhz)
+{
+	int i;
+	const struct pll_freq *freq;
+	unsigned int major, minor;
+	unsigned short value_02h;
+
+	/* find pll_freq */
+	for (i = 0; i < ARRAY_SIZE(pll_ddr_freq_table); i++) {
+		if (pll_ddr_freq_table[i].freq_mhz == freq_mhz)
+			break;
+	}
+	if (i >= ARRAY_SIZE(pll_ddr_freq_table)) {
+		printf("pll_freq_set, fail to find freq\n");
+		return -1;
+	}
+
+	freq = &pll_ddr_freq_table[i];
+	if (freq->with_div)
+		value_02h = 0x030B;
+	else
+		value_02h = 0x020B;
+	major = freq->major;
+	minor = freq->minor;
+
+	printf("major = %x, minor = %x --\n", major, minor);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_02H, value_02h);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_MAJOR, major);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_MINOR, minor);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_07H, 0x0012);
+	mdelay(1);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_07H, 0x0013);
+	mdelay(1);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_DIV, freq->div & 0x7fff);
+	mdelay(1);
+	ispi_reg_write(reg_base + PLL_REG_OFFSET_DIV, freq->div);
+	return 0;
+}
+
+void modem_RfspiInit_624M(void);
+void modem_8850eeco2_RfspiInit_624M(void);
+
+static void pll_setup_freq(void)
+{
+	u16 metal_id = rda_metal_id_get();
+
+	pll_freq_set(PLL_REG_CPU_BASE, g_clock_config->PLL_FREQ_CPU);
+	// Always configure BUS PLL, even when it is being used
+	pll_freq_set(PLL_REG_BUS_BASE, g_clock_config->PLL_FREQ_BUS);
+	pll_ddr_freq_set(PLL_REG_MEM_BASE, g_clock_config->PLL_FREQ_MEM);
+	pll_freq_set(PLL_REG_USB_BASE, g_clock_config->PLL_FREQ_USB);
+
+	if (metal_id < 2)
+		modem_RfspiInit_624M();
+	else
+		modem_8850eeco2_RfspiInit_624M();
+}
+
+static void print_pll_freq(char *name, UINT32 value)
+{
+	printf("pll freq %s = %d\n", name, (int)value);
+}
+
+static void sys_dump_pll_freq(void)
+{
+	print_pll_freq("CPU", g_clock_config->PLL_FREQ_CPU);
+	print_pll_freq("BUS", g_clock_config->PLL_FREQ_BUS);
+	print_pll_freq("MEM", g_clock_config->PLL_FREQ_MEM);
+	//print_pll_freq("USB", g_clock_config->PLL_FREQ_USB);
+}
+
+static void pmu_setup_init(void)
+{
+	int i;
+	u16 metal_id = rda_metal_id_get();
+	u32 reg_val = 0;
+
+	rda_nand_iodrive_set();
+
+	ispi_open(1);
+	for (i = 0; i < ARRAY_SIZE(pmu_reg_table); i++){
+		/*Fix is used for vibrator shutdown for eco2 and later chip.
+		  If 8850e eco1 is not used, then we should change reg3 value 
+		  in pmu_reg_table and remove the redundant code*/
+		reg_val = pmu_reg_table[i].reg_val;
+		if ((metal_id >= 2) && (pmu_reg_table[i].reg_num == PMU_REG_VIBRATOR_NUM))
+			reg_val &= ~(1 << PMU_REG_VIBRATOR_NUM);
+		if (pmu_reg_table[i].reg_num == 0x53)
+			reg_val = (reg_val & ~(0xf << 5)) | (PMU_VBUCK5_VAL << 5);
+		ispi_reg_write(pmu_reg_table[i].reg_num, reg_val);
+	}
+	ispi_open(0);
+
+#ifdef CONFIG_RDA_PDL
+	enable_charger(0);
+#endif
+}
+
+/*
+ * we initialize usb clock, but this won't cause the usb clock jitter,
+ * because wo don't setup the usb pll
+ */
+static void usb_clock_pre_init(void)
+{
+#if 0
+	u16 val = ispi_reg_read(0x83);
+	printf("%s: reg 0x83 = %#x\n", __func__, val);
+	val = ispi_reg_read(0x89);
+	printf("%s: reg 0x89 = %#x\n", __func__, val);
+	val = ispi_reg_read(0x8d);
+	printf("%s: reg 0x8d = %#x\n", __func__, val);
+#endif
+	ispi_reg_write(0x83, 0x72ff); /* default 0x72e3, update bit 1~4, b0001 -> b1111 */
+	ispi_reg_write(0x89, 0x7180); /* default 0x7100, update bit 7, b0 -> b1 */
+	ispi_reg_write(0x8d, 0x0302); /* default 0x0304, update bit 0~2, b100 -> b010 */
+}
+
+static void pll_setup_init(void)
+{
+	if (g_clock_config->DDR_CHAN_1_VALID) {
+		ispi_reg_write(0x101, g_clock_config->DDR_TIMING_101H);
+		ispi_reg_write(0x102, g_clock_config->DDR_TIMING_102H);
+		ispi_reg_write(0x103, g_clock_config->DDR_TIMING_103H);
+		ispi_reg_write(0x104, g_clock_config->DDR_TIMING_104H);
+		ispi_reg_write(0x105, g_clock_config->DDR_TIMING_105H);
+		ispi_reg_write(0x106, g_clock_config->DDR_TIMING_106H);
+		ispi_reg_write(0x107, g_clock_config->DDR_TIMING_107H);
+		ispi_reg_write(0x108, g_clock_config->DDR_TIMING_108H);
+		ispi_reg_write(0x109, g_clock_config->DDR_TIMING_109H);
+		ispi_reg_write(0x10A, g_clock_config->DDR_TIMING_10AH);
+		ispi_reg_write(0x10B, g_clock_config->DDR_TIMING_10BH);
+		ispi_reg_write(0x10C, g_clock_config->DDR_TIMING_10CH);
+		ispi_reg_write(0x10D, g_clock_config->DDR_TIMING_10DH);
+		ispi_reg_write(0x10E, g_clock_config->DDR_TIMING_10EH);
+		ispi_reg_write(0x10F, g_clock_config->DDR_TIMING_10FH);
+	}
+
+	if (g_clock_config->DDR_CHAN_2_VALID) {
+		ispi_reg_write(0x121, g_clock_config->DDR_TIMING_121H);
+		ispi_reg_write(0x122, g_clock_config->DDR_TIMING_122H);
+		ispi_reg_write(0x123, g_clock_config->DDR_TIMING_123H);
+		ispi_reg_write(0x124, g_clock_config->DDR_TIMING_124H);
+		ispi_reg_write(0x125, g_clock_config->DDR_TIMING_125H);
+		ispi_reg_write(0x126, g_clock_config->DDR_TIMING_126H);
+		ispi_reg_write(0x127, g_clock_config->DDR_TIMING_127H);
+		ispi_reg_write(0x128, g_clock_config->DDR_TIMING_128H);
+		ispi_reg_write(0x129, g_clock_config->DDR_TIMING_129H);
+		ispi_reg_write(0x12A, g_clock_config->DDR_TIMING_12AH);
+		ispi_reg_write(0x12B, g_clock_config->DDR_TIMING_12BH);
+		ispi_reg_write(0x12C, g_clock_config->DDR_TIMING_12CH);
+		ispi_reg_write(0x12D, g_clock_config->DDR_TIMING_12DH);
+		ispi_reg_write(0x12E, g_clock_config->DDR_TIMING_12EH);
+		ispi_reg_write(0x12F, g_clock_config->DDR_TIMING_12FH);
+	}
+
+	if (g_clock_config->DDR_CHAN_3_VALID) {
+		ispi_reg_write(0x141, g_clock_config->DDR_TIMING_141H);
+		ispi_reg_write(0x142, g_clock_config->DDR_TIMING_142H);
+		ispi_reg_write(0x143, g_clock_config->DDR_TIMING_143H);
+		ispi_reg_write(0x144, g_clock_config->DDR_TIMING_144H);
+		ispi_reg_write(0x145, g_clock_config->DDR_TIMING_145H);
+		ispi_reg_write(0x146, g_clock_config->DDR_TIMING_146H);
+		ispi_reg_write(0x147, g_clock_config->DDR_TIMING_147H);
+		ispi_reg_write(0x148, g_clock_config->DDR_TIMING_148H);
+		ispi_reg_write(0x149, g_clock_config->DDR_TIMING_149H);
+		ispi_reg_write(0x14A, g_clock_config->DDR_TIMING_14AH);
+		ispi_reg_write(0x14B, g_clock_config->DDR_TIMING_14BH);
+		ispi_reg_write(0x14C, g_clock_config->DDR_TIMING_14CH);
+		ispi_reg_write(0x14D, g_clock_config->DDR_TIMING_14DH);
+		ispi_reg_write(0x14E, g_clock_config->DDR_TIMING_14EH);
+		ispi_reg_write(0x14F, g_clock_config->DDR_TIMING_14FH);
+	}
+
+	if (g_clock_config->DDR_CHAN_4_VALID) {
+		ispi_reg_write(0x161, g_clock_config->DDR_TIMING_161H);
+		ispi_reg_write(0x162, g_clock_config->DDR_TIMING_162H);
+		ispi_reg_write(0x163, g_clock_config->DDR_TIMING_163H);
+		ispi_reg_write(0x164, g_clock_config->DDR_TIMING_164H);
+		ispi_reg_write(0x165, g_clock_config->DDR_TIMING_165H);
+		ispi_reg_write(0x166, g_clock_config->DDR_TIMING_166H);
+		ispi_reg_write(0x167, g_clock_config->DDR_TIMING_167H);
+		ispi_reg_write(0x168, g_clock_config->DDR_TIMING_168H);
+		ispi_reg_write(0x169, g_clock_config->DDR_TIMING_169H);
+		ispi_reg_write(0x16A, g_clock_config->DDR_TIMING_16AH);
+		ispi_reg_write(0x16B, g_clock_config->DDR_TIMING_16BH);
+		ispi_reg_write(0x16C, g_clock_config->DDR_TIMING_16CH);
+		ispi_reg_write(0x16D, g_clock_config->DDR_TIMING_16DH);
+		ispi_reg_write(0x16E, g_clock_config->DDR_TIMING_16EH);
+		ispi_reg_write(0x16F, g_clock_config->DDR_TIMING_16FH);
+	}
+
+	ispi_reg_write(0x160, g_clock_config->DDR_TIMING_160H);
+	ispi_reg_write(0x180, g_clock_config->DDR_TIMING_180H);
+	ispi_reg_write(0x181, g_clock_config->DDR_TIMING_181H);
+	ispi_reg_write(0x182, g_clock_config->DDR_TIMING_182H);
+	ispi_reg_write(0x183, g_clock_config->DDR_TIMING_183H);
+	ispi_reg_write(0x184, g_clock_config->DDR_TIMING_184H);
+	ispi_reg_write(0x185, g_clock_config->DDR_TIMING_185H);
+	ispi_reg_write(0x186, g_clock_config->DDR_TIMING_186H);
+	ispi_reg_write(0x187, g_clock_config->DDR_TIMING_187H);
+	ispi_reg_write(0x188, g_clock_config->DDR_TIMING_188H);
+	ispi_reg_write(0x189, g_clock_config->DDR_TIMING_189H);
+	ispi_reg_write(0x18A, g_clock_config->DDR_TIMING_18AH);
+	ispi_reg_write(0x18B, g_clock_config->DDR_TIMING_18BH);
+	ispi_reg_write(0x18C, g_clock_config->DDR_TIMING_18CH);
+	ispi_reg_write(0x18D, g_clock_config->DDR_TIMING_18DH);
+	ispi_reg_write(0x18E, g_clock_config->DDR_TIMING_18EH);
+	ispi_reg_write(0x18F, g_clock_config->DDR_TIMING_18FH);
+
+	ispi_reg_write(0x69, g_clock_config->DDR_TIMING_69H);
+	usb_clock_pre_init();
+
+	udelay(5000);
+}
+
+static void pll_setup_mem(void)
+{
+}
+
+static void pll_setup_mem_cal(void)
+{
+}
+
+static void print_pll_reg(UINT32 index, UINT32 value)
+{
+	printf("pll reg %lx = %lx\n", index, value);
+}
+
+static void pll_dump_reg(void)
+{
+	print_pll_reg(0x005, ispi_reg_read(0x005));
+	print_pll_reg(0x006, ispi_reg_read(0x006));
+	print_pll_reg(0x063, ispi_reg_read(0x063));
+	print_pll_reg(0x065, ispi_reg_read(0x065));
+	print_pll_reg(0x066, ispi_reg_read(0x066));
+
+	if (g_clock_config->DDR_CHAN_1_VALID)
+	{
+		print_pll_reg(0x100, ispi_reg_read(0x100));
+		print_pll_reg(0x101, ispi_reg_read(0x101));
+		print_pll_reg(0x102, ispi_reg_read(0x102));
+		print_pll_reg(0x103, ispi_reg_read(0x103));
+		print_pll_reg(0x104, ispi_reg_read(0x104));
+		print_pll_reg(0x105, ispi_reg_read(0x105));
+		print_pll_reg(0x106, ispi_reg_read(0x106));
+		print_pll_reg(0x107, ispi_reg_read(0x107));
+		print_pll_reg(0x108, ispi_reg_read(0x108));
+		print_pll_reg(0x109, ispi_reg_read(0x109));
+		print_pll_reg(0x10A, ispi_reg_read(0x10A));
+		print_pll_reg(0x10B, ispi_reg_read(0x10B));
+		print_pll_reg(0x10C, ispi_reg_read(0x10C));
+		print_pll_reg(0x10D, ispi_reg_read(0x10D));
+		print_pll_reg(0x10E, ispi_reg_read(0x10E));
+		print_pll_reg(0x10F, ispi_reg_read(0x10F));
+	}
+
+	if (g_clock_config->DDR_CHAN_2_VALID)
+	{
+		print_pll_reg(0x120, ispi_reg_read(0x120));
+		print_pll_reg(0x121, ispi_reg_read(0x121));
+		print_pll_reg(0x122, ispi_reg_read(0x122));
+		print_pll_reg(0x123, ispi_reg_read(0x123));
+		print_pll_reg(0x124, ispi_reg_read(0x124));
+		print_pll_reg(0x125, ispi_reg_read(0x125));
+		print_pll_reg(0x126, ispi_reg_read(0x126));
+		print_pll_reg(0x127, ispi_reg_read(0x127));
+		print_pll_reg(0x128, ispi_reg_read(0x128));
+		print_pll_reg(0x129, ispi_reg_read(0x129));
+		print_pll_reg(0x12A, ispi_reg_read(0x12A));
+		print_pll_reg(0x12B, ispi_reg_read(0x12B));
+		print_pll_reg(0x12C, ispi_reg_read(0x12C));
+		print_pll_reg(0x12D, ispi_reg_read(0x12D));
+		print_pll_reg(0x12E, ispi_reg_read(0x12E));
+		print_pll_reg(0x12F, ispi_reg_read(0x12F));
+	}
+
+	if (g_clock_config->DDR_CHAN_3_VALID)
+	{
+		print_pll_reg(0x140, ispi_reg_read(0x140));
+		print_pll_reg(0x141, ispi_reg_read(0x141));
+		print_pll_reg(0x142, ispi_reg_read(0x142));
+		print_pll_reg(0x143, ispi_reg_read(0x143));
+		print_pll_reg(0x144, ispi_reg_read(0x144));
+		print_pll_reg(0x145, ispi_reg_read(0x145));
+		print_pll_reg(0x146, ispi_reg_read(0x146));
+		print_pll_reg(0x147, ispi_reg_read(0x147));
+		print_pll_reg(0x148, ispi_reg_read(0x148));
+		print_pll_reg(0x149, ispi_reg_read(0x149));
+		print_pll_reg(0x14A, ispi_reg_read(0x14A));
+		print_pll_reg(0x14B, ispi_reg_read(0x14B));
+		print_pll_reg(0x14C, ispi_reg_read(0x14C));
+		print_pll_reg(0x14D, ispi_reg_read(0x14D));
+		print_pll_reg(0x14E, ispi_reg_read(0x14E));
+		print_pll_reg(0x14F, ispi_reg_read(0x14F));
+	}
+
+	if (g_clock_config->DDR_CHAN_4_VALID)
+	{
+		print_pll_reg(0x161, ispi_reg_read(0x161));
+		print_pll_reg(0x162, ispi_reg_read(0x162));
+		print_pll_reg(0x163, ispi_reg_read(0x163));
+		print_pll_reg(0x164, ispi_reg_read(0x164));
+		print_pll_reg(0x165, ispi_reg_read(0x165));
+		print_pll_reg(0x166, ispi_reg_read(0x166));
+		print_pll_reg(0x167, ispi_reg_read(0x167));
+		print_pll_reg(0x168, ispi_reg_read(0x168));
+		print_pll_reg(0x169, ispi_reg_read(0x169));
+		print_pll_reg(0x16A, ispi_reg_read(0x16A));
+		print_pll_reg(0x16B, ispi_reg_read(0x16B));
+		print_pll_reg(0x16C, ispi_reg_read(0x16C));
+		print_pll_reg(0x16D, ispi_reg_read(0x16D));
+		print_pll_reg(0x16E, ispi_reg_read(0x16E));
+		print_pll_reg(0x16F, ispi_reg_read(0x16F));
+	}
+
+	print_pll_reg(0x160, ispi_reg_read(0x160));
+	print_pll_reg(0x180, ispi_reg_read(0x180));
+	print_pll_reg(0x181, ispi_reg_read(0x181));
+	print_pll_reg(0x182, ispi_reg_read(0x182));
+	print_pll_reg(0x183, ispi_reg_read(0x183));
+	print_pll_reg(0x184, ispi_reg_read(0x184));
+	print_pll_reg(0x185, ispi_reg_read(0x185));
+	print_pll_reg(0x186, ispi_reg_read(0x186));
+	print_pll_reg(0x187, ispi_reg_read(0x187));
+	print_pll_reg(0x188, ispi_reg_read(0x188));
+	print_pll_reg(0x189, ispi_reg_read(0x189));
+	print_pll_reg(0x18A, ispi_reg_read(0x18A));
+	print_pll_reg(0x18B, ispi_reg_read(0x18B));
+	print_pll_reg(0x18C, ispi_reg_read(0x18C));
+	print_pll_reg(0x18D, ispi_reg_read(0x18D));
+	print_pll_reg(0x18E, ispi_reg_read(0x18E));
+	print_pll_reg(0x18F, ispi_reg_read(0x18F));
+}
+
+static int clock_save_config(void)
+{
+	/* save config to nand */
+	return 1;
+}
+
+#ifdef DO_DDR_PLL_DEBUG
+
+static int ddr_get_freq(UINT8 chioce)
+{
+	switch(chioce)
+	{
+		case 1:
+			return 200;
+		case 2:
+			return 290;
+		case 3:
+			return 312;
+		case 4:
+			return 316;
+		case 5:
+			return 321;
+		case 6:
+			return 325;
+		case 7:
+			return 328;
+		case 8:
+			return 333;
+		case 9:
+			return 338;
+		case 10:
+			return 351;
+		case 11:
+			return 355;
+		case 12:
+			return 358;
+		case 13:
+			return 364;
+		case 14:
+			return 370;
+		case 15:
+			return 377;
+		case 16:
+			return 383;
+		case 17:
+			return 390;
+		case 18:
+			return 397;
+		case 19:
+			return 400;
+		case 20:
+			return 403;
+		case 21:
+			return 416;
+		case 22:
+			return 429;
+		case 23:
+			return 455;
+		case 24:
+			return 480;
+		case 25:
+			return 100;
+		case 26:
+			return 500;
+		case 27:
+			return 519;
+		case 28:
+			return 538;
+		case 29:
+			return 555;
+		case 30:
+			return 573;
+		case 31:
+			return 590;
+		case 32:
+			return 600;
+
+		default:
+			return -1;
+	}
+}
+
+static void freq_choose(void)
+{
+	UINT8 i = 0, buf[3] = {0}, choice = 0;
+	INT32 freq_temp = 0;
+
+	printf("\nPlese choose the ddr Freq:");
+	printf("\n 1.200M  2.290M  3.312M  4.316M  5.321M ");
+	printf("\n 6.325M  7.328M  8.333M  9.338M 10.351M ");
+	printf("\n11.355M 12.358M 13.364M 14.370M 15.377M ");
+	printf("\n11.355M 12.358M 13.364M 14.370M 15.377M ");
+	printf("\n16.383M 17.390M 18.397M 19.400M 20.403M ");
+	printf("\n21.416M 22.429M 23.455M 24.480M 25.100M ");
+	printf("\n26.500M 27.519M 28.538M 29.555M 30.573M ");
+	printf("\n31.590M 32.600M ");
+	printf("\nThe number is:");
+
+	while(1)
+	{
+		if (i > 2)
+		{
+			printf("\n Sorry, you input is wrong. Please input again:");
+			i = 0;
+		}
+		buf[i] = serial_getc();
+		serial_putc(buf[i]);
+
+		if ( ('\r' == buf[i]) || ('\n' == buf[i]))
+		{
+			serial_puts("\n");
+			break;
+		}
+
+		i++;
+	}
+
+	if (1 == i)
+		choice = buf[0] - 0x30;
+	else if (2 == i)
+		choice = 10*(buf[0] - 0x30) + (buf[1] - 0x30);
+	else
+		return;
+
+	freq_temp = ddr_get_freq(choice);
+	if (-1 == freq_temp )
+		printf("\n Sorry, the fre you choose is wrong");
+	ddrfreq = freq_temp;
+}
+
+static void data_bits_choose(void)
+{
+	UINT8 i = 0, buf[2] = {0};
+
+	printf("\nPlese choose the ddr data bits:");
+	printf("\n1.16  2.32");
+	printf("\nThe number is:");
+
+	while(1)
+	{
+		buf[i] =serial_getc();
+
+		if (i == 1)
+		{
+			if (('\r' == buf[i]) || ('\n' == buf[i]))
+			{
+				if (1 == (buf[0] - 0x30))
+					ddr32bit = 0;
+				else
+					ddr32bit = 1;
+				return;
+			}
+			else
+			{
+				printf("\n Sorry, you input is wrong. Please input again:");
+				i = 0;
+				continue;
+			}
+		}
+
+		serial_putc(buf[i]);
+
+		if ((buf[i] - 0x30) > 2 || 0 == (buf[i] - 0x30))
+			printf("\n Sorry, you input is wrong. Please input again:");
+		else
+			i++;
+	}
+}
+
+static void pmu_setup_calibration_voltage(UINT8 vcoreselect)
+{
+	UINT8 buf[3] = {0}, voltage = 0;
+	int i = 0;
+	UINT32 reg_value,temp, regid = 0;
+
+	ispi_open(1);
+	switch(vcoreselect) {
+	case 1:
+		regid = 0x53;
+		printf("\nPlese input vcore voltage(0 ~ 15):");
+		break;
+	case 2:
+		regid = 0x2a;
+		printf("\nPlese input DDR buck3 voltage(0 ~ 15):");
+		break;
+	case 3:
+		regid = 0x2a;
+		printf("\nPlese input DDR buck4 voltage(0 ~ 15):");
+		break;
+	default:
+		printf("\ninvalid vcoreselect,exit\n");
+		return;
+	}
+
+	while(1) {
+		if (i > 2) {
+			printf("\n Sorry, you input is wrong. Please input again:");
+			i = 0;
+		}
+		buf[i] = serial_getc();
+		serial_putc(buf[i]);
+
+		if ( ('\r' == buf[i]) || ('\n' == buf[i])) {
+			printf("\n");
+			break;
+		}
+		i++;
+	}
+	if (1 == i)
+		voltage = buf[0] - 0x30;
+	else if (2 == i)
+		voltage = 10*(buf[0] - 0x30) + (buf[1] - 0x30);
+	else
+		return;
+	printf("voltage is: 0x%x\n",(unsigned int)voltage);
+
+	if (vcoreselect == 1){
+		reg_value = 0x9415;
+		reg_value &= ~(0xf << 5);
+		reg_value |= ((voltage & 0xf) << 5);
+		ispi_reg_write(regid, reg_value);//write vbuc5 act voltage bit5~bit8
+	} else if (vcoreselect == 2) {
+		temp = (UINT32)voltage;
+		temp = (temp & 0xf) << 12;
+		reg_value = ispi_reg_read(regid);
+		reg_value &= ~(0xf << 12);
+		reg_value |= temp ;
+		ispi_reg_write(regid, reg_value);//write vbuck3 act voltage,bit12~bit15
+		mdelay(100);
+	} else {
+		temp = (UINT32)voltage;
+		temp = (temp & 0xf) << 4;
+		reg_value = ispi_reg_read(regid);
+		reg_value &= ~(0xf << 4);
+		reg_value |= temp ;
+		ispi_reg_write(regid, reg_value);//write vbuck4 act voltage,bit4~bit7
+		mdelay(100);
+	}
+	printf("write reg: 0x%x,val: 0x%x\n",(unsigned int)regid,(unsigned int)reg_value);
+}
+#if 0
+static void pmu_buck4_buck3_choose(void)
+{
+	UINT8 i = 0, buf[2] = {0};
+	UINT8 ddr_voltage_source = 0;
+
+	printf("\nPlese choose the ddr voltage:");
+	printf("\n1.DDR3L  2.DDR3");
+	printf("\nThe number is:");
+
+	while(1)
+	{
+		buf[i] =serial_getc();
+
+		if (i == 1)
+		{
+			if (('\r' == buf[i]) || ('\n' == buf[i]))
+			{
+				if (1 == (buf[0] - 0x30))
+					ddr_voltage_source =2;
+				else{
+					ddr_voltage_source = 3;
+					pmu_setup_calibration_voltage(2);
+				}
+				pmu_setup_calibration_voltage(ddr_voltage_source);
+				return;
+			}
+			else
+			{
+				printf("\n Sorry, you input is wrong. Please input again:");
+				i = 0;
+				continue;
+			}
+		}
+
+		serial_putc(buf[i]);
+
+		if ((buf[i] - 0x30) > 2 || 0 == (buf[i] - 0x30))
+			printf("\n Sorry, you input is wrong. Please input again:");
+		else
+			i++;
+	}
+}
+#endif
+
+void clock_load_ddr_cal_config(void)
+{
+	clock_debug_config.PLL_FREQ_MEM = ddrfreq;
+	if (ddrfreq < 200)
+		clock_debug_config.DDR_FLAGS |= DDR_FLAGS_DLLOFF;
+	else
+		clock_debug_config.DDR_FLAGS &= ~DDR_FLAGS_DLLOFF;
+
+	if (0 == ddr32bit)
+	{
+		clock_debug_config.DDR_CHAN_3_VALID = 0;
+		clock_debug_config.DDR_CHAN_4_VALID = 0;
+	}
+
+	clock_debug_config.DDR_PARA &= ~DDR_PARA_MEM_BITS_MASK;
+	if (0 == ddr32bit)
+		clock_debug_config.DDR_PARA |= DDR_PARA_MEM_BITS(1);
+	else
+		clock_debug_config.DDR_PARA |= DDR_PARA_MEM_BITS(2);
+}
+
+static int serial_gets(UINT8 *pstr)
+{
+    UINT32 length;
+
+    length = 0;
+    while(1) {
+        pstr[length] = serial_getc();
+        if(pstr[length] == '\r') {
+            pstr[length] = 0x00;
+            break;
+        }
+        else if( pstr[length] == '\b' ) {
+            if(length>0) {
+                length --;
+                printf("\b");
+            }
+        }
+        else {
+            serial_putc(pstr[length]);
+            length ++;
+        }
+
+        if(length > 32)
+            return -1;
+    }
+    return length;
+}
+
+UINT32 asc2hex(UINT8 *pstr, UINT8 len)
+{
+	UINT8 i,ch,mylen;
+	UINT32 hexvalue;
+
+	for(mylen=0,i=0; i<8; i++)
+	{
+		if( pstr[i] == 0 )
+			break;
+		mylen ++;
+	}
+	if( len != 0 )
+	{
+		if(mylen>len)
+			mylen = len;
+	}
+	if(mylen>8)
+		mylen = 8;
+
+	hexvalue = 0;
+	for (i = 0; i < mylen; i++)
+	{
+		hexvalue <<= 4;
+		ch = *(pstr+i);
+		if((ch>='0') && (ch<='9'))
+			hexvalue |= ch - '0';
+		else if((ch>='A') && (ch<='F'))
+			hexvalue |= ch - ('A' - 10);
+		else if((ch>='a') && (ch<='f'))
+			hexvalue |= ch - ('a' - 10);
+		else
+			;
+	}
+	return(hexvalue);
+}
+
+static int process_cmd(char * pname, char * cmd, UINT32 reb_base)
+{
+	char cmd_element[3][16] = {{0}};
+	char * cmd_temp = cmd;
+	UINT8 i = 0, cmd_element_num = 0, former_space = 1;
+	UINT32 reg = 0, reg_value = 0;
+
+	if (NULL == cmd)
+		return -1;
+
+	while(('\0' != *cmd_temp) && ('\r' != *cmd_temp) && ('\n' != *cmd_temp))
+	{
+		if (' ' == * cmd_temp)
+		{
+			if (0 == former_space)
+			{
+				former_space = 1;
+				cmd_element[cmd_element_num][i] = '\0';
+				cmd_element_num++;
+				if (cmd_element_num > 2)
+					return -1;
+				i = 0;
+			}
+		}
+		else
+		{
+			former_space = 0;
+			cmd_element[cmd_element_num][i] = *cmd_temp;
+			i++;
+			if (i > 10)
+				return -1;
+		}
+
+		cmd_temp++;
+	}
+
+	cmd_element[cmd_element_num][i] = '\0';
+
+	if (!strcmp(cmd_element[0], "read"))
+	{
+		if (cmd_element_num == 2)
+			return -1;
+		if (('0' != cmd_element[1][0]) || ('x' != cmd_element[1][1]))
+			return -1;
+
+		reg = asc2hex((UINT8 *)&cmd_element[1][2], 8);
+		if (reb_base)
+			reg_value = *(UINT32 *)(reb_base + reg);
+		else
+			reg_value = ispi_reg_read(reg);
+
+		printf("value = 0x%x", (unsigned int)reg_value);
+		printf("\n%s#", pname);
+	}
+	else if (!strcmp(cmd_element[0], "write"))
+	{
+		if (cmd_element_num != 2)
+			return -1;
+		if (('0' != cmd_element[1][0]) || ('x' != cmd_element[1][1])
+		   || ('0' != cmd_element[2][0]) || ('x' != cmd_element[2][1]))
+			return -1;
+
+		reg = asc2hex((UINT8 *)&cmd_element[1][2], 8);
+		reg_value  = asc2hex((UINT8 *)&cmd_element[2][2], 8);
+		if (reb_base)
+			*(UINT32 *)(reb_base + reg) = reg_value;
+		else
+			ispi_reg_write(reg, reg_value);
+	}
+	else if (!strcmp(cmd_element[0], "finish"))
+	{
+		return 1;
+	}
+	else if (!strcmp(cmd_element[0], "dump"))
+	{
+		if (reb_base == 0)
+			pll_dump_reg();
+		printf("\n%s#", pname);
+	}
+	else
+	{
+		return -1;
+	}
+
+	return 0;
+}
+
+void cmd_input(char * pname, UINT32 reg_base)
+{
+	char cmd[48] = {0};
+	int len = 0;
+
+	ispi_open(0);
+	printf("\n%s#", pname);
+	while(1)
+	{
+		len = serial_gets((UINT8 *)cmd);
+		printf("\n%s#", pname);
+		if (len > 0)
+		{
+			int result = 0;
+
+			result =  process_cmd(pname, cmd, reg_base);
+			if (-1 == result)
+				printf("command error! \n%s#", pname);
+			else if (1 == result)
+				break;
+			else
+				continue;
+		}
+	}
+	printf("Command is finished .\n");
+	return;
+}
+
+#endif /* DO_DDR_PLL_DEBUG */
+
+
+#ifdef TGT_AP_SELECT_CLK
+
+/* clock divider table size */
+#define CLOCK_DIV_TAB_SIZE 60
+const static UINT16 clock_div_tab[CLOCK_DIV_TAB_SIZE][2] = {
+	{10, 0x1F},{11, 0x1F},{12, 0x1F},{13, 0x1F},{14, 0x1F},
+	{15, 0x1F},{16, 0x1F},{17, 0x1F},{18, 0x1F},{19, 0x1F},
+	{20, 0x1E},{21, 0x1E},{22, 0x1E},{23, 0x1E},{24, 0x1E},
+	{25, 0x1D},{26, 0x1D},{27, 0x1D},{28, 0x1D},{29, 0x1D},
+	{30, 0x1C},{31, 0x1C},{32, 0x1C},{33, 0x1C},{34, 0x1C},
+	{35, 0x1B},{36, 0x1B},{37, 0x1B},{38, 0x1B},{39, 0x1B},
+	{40, 0x1A},{41, 0x1A},{42, 0x1A},{43, 0x1A},{44, 0x1A},
+	{45, 0x19},{46, 0x19},{47, 0x19},{48, 0x19},{49, 0x19},
+	{50, 0x18},{51, 0x18},{52, 0x18},{53, 0x18},{54, 0x18},
+	{55, 0x17},{56, 0x17},{57, 0x17},{58, 0x17},{59, 0x17},
+	{60, 0x16},{61, 0x16},{62, 0x16},{63, 0x16},{64, 0x16},
+	{65, 0x15},{66, 0x15},{67, 0x15},{68, 0x15},{69, 0x15},
+};
+
+static struct clock_config clock_select_config;
+
+static void do_clock_selection(void)
+{
+	char choice = 'n';
+
+	UINT32 set_cpu_clk = _TGT_AP_PLL_CPU_FREQ;
+	UINT16 set_vpu_clk = 133,vpu_clk_div = _TGT_AP_CLK_VPU; //divided 6
+	UINT16 set_gpu_clk = 200,gpu_clk_div = _TGT_AP_CLK_GPU; //divided 4
+	UINT16 set_axi_clk = 400,axi_clk_div = _TGT_AP_CLK_AXI; //divided 2
+	UINT32 real_vpu_clk = 0;
+	UINT32 real_gpu_clk = 0;
+	UINT32 real_axi_clk = 0;
+	UINT16 clk_div;
+	int i;
+
+	printf("If you want to configure clock manully?(y=yes,n=no)\n");
+	choice = serial_getc();
+	if((choice != 'y') && (choice != 'Y')) {
+		printf("Use default value as CPU,VPU,GPU AXI clock\n");
+		return;
+	}
+	printf("\nYou are trying to set CPU,VPU,GPU AXI clock.\n"
+		"Press <Enter> will use default value.\n\n");
+	/* CPU clock selection process */
+	choice = '1';
+	printf("Set CPU clock:\n"
+		"\t 1: 800 MHz\n"
+		"\t 2: 910 MHz\n"
+		"\t 3: 962 MHz\n");
+	choice = serial_getc();
+	switch(choice) {
+	case '1':
+		set_cpu_clk = 800;
+		break;
+	case '2':
+		set_cpu_clk = 910;
+		break;
+	case '3':
+		set_cpu_clk = 962;
+		break;
+	default:
+		printf("Use default value: %d\n",(int)set_cpu_clk);
+		break;
+	}
+	printf("CPU clock value is %d MHz\n",(int)set_cpu_clk);
+	/* GPU clock selection process */
+	choice = '1';
+	printf("Set GPU clock:\n"
+		"\t 1: 400 MHz\n"
+		"\t 2: 320 MHz\n"
+		"\t 3: 266 MHz\n");
+	choice = serial_getc();
+	switch(choice) {
+	case '1':
+		set_gpu_clk = 400;
+		break;
+	case '2':
+		set_gpu_clk = 320;
+		break;
+	case '3':
+		set_gpu_clk = 266;
+		break;
+	default:
+		printf("Use default value: %d\n",(int)set_gpu_clk);
+		break;
+	}
+	printf("GPU clock value is %d MHz\n",(int)set_gpu_clk);
+
+	/* VPU clock selection process */
+	choice = '1';
+	printf("Set VPU clock:\n"
+		"\t 1: 228 MHz\n"
+		"\t 2: 200 MHz\n");
+	choice = serial_getc();
+	switch(choice) {
+	case '1':
+		set_vpu_clk = 228;
+		break;
+	case '2':
+		set_vpu_clk = 200;
+		break;
+	default:
+		printf("Use default value: %d\n",(int)set_vpu_clk);
+		break;
+	}
+	printf("VPU clock value is %d MHz\n",(int)set_vpu_clk);
+	choice = '1';
+	printf("Set AXI clock:\n"
+		"\t 1: 400 MHz\n"
+		"\t 2: 320 MHz\n");
+	choice = serial_getc();
+	switch(choice) {
+	case '1':
+		set_axi_clk = 400;
+		break;
+	case '2':
+		set_axi_clk = 320;
+		break;
+	case '3':
+		set_axi_clk = 266;
+		break;
+	default:
+		printf("Use default value: %d\n",(int)set_axi_clk);
+		break;
+	}
+	printf("AXI clock value is %d MHz\n",(int)set_axi_clk);
+
+	/* Get GPU clock div value */
+	clk_div = (10 * set_cpu_clk) / set_gpu_clk;
+	for ( i = 0; i < CLOCK_DIV_TAB_SIZE; i++) {
+		if(clock_div_tab[i][0] == clk_div) {
+			break;
+		}
+	}
+	gpu_clk_div = clock_div_tab[i][1];
+	real_gpu_clk = (10 * set_cpu_clk) / clk_div;
+
+	/* Get VPU clock div value */
+	clk_div = (10 * set_cpu_clk) / set_vpu_clk;
+	for ( i = 0; i < CLOCK_DIV_TAB_SIZE; i++) {
+		if(clock_div_tab[i][0] == clk_div) {
+			break;
+		}
+	}
+	vpu_clk_div = clock_div_tab[i][1];
+	real_vpu_clk = (10 * set_cpu_clk) / clk_div;
+
+	/* Get AXI clock div value */
+	clk_div = (10 * set_cpu_clk) / set_axi_clk;
+	for ( i = 0; i < CLOCK_DIV_TAB_SIZE; i++) {
+		if(clock_div_tab[i][0] == clk_div) {
+			break;
+		}
+	}
+	axi_clk_div = clock_div_tab[i][1];
+	real_axi_clk = (10 * set_cpu_clk) / clk_div;
+
+	printf("\nAll clock value:\n");
+	printf("CPU clk: %d\n",(int)set_cpu_clk);
+	printf("GPU max clk: %d MHz, div val: 0x%x, real clk: %d MHz\n",(int)set_gpu_clk,(int)gpu_clk_div,(int)real_gpu_clk);
+	printf("VPU max clk: %d MHz, div val: 0x%x, real clk: %d MHz\n",(int)set_vpu_clk,(int)vpu_clk_div,(int)real_vpu_clk);
+	printf("AXI max clk: %d MHz, div val: 0x%x, real clk: %d MHz\n",(int)set_axi_clk,(int)axi_clk_div,(int)real_axi_clk);
+
+	printf("Write to register ? (y=yes,n=no)\n");
+	choice = 'y';
+	choice = serial_getc();
+	if((choice != 'y')&&(choice != 'Y')) {
+		printf("Clock selection canceled\n");
+		return;
+	}
+	/* Set CPU, GPU, VPU AXI clock value */
+	memcpy(&clock_select_config,g_clock_config,
+		sizeof(clock_select_config));
+	clock_select_config.PLL_FREQ_CPU = set_cpu_clk;
+	clock_select_config.CLK_GPU = gpu_clk_div;
+	clock_select_config.CLK_VPU = vpu_clk_div;
+	clock_select_config.CLK_AXI = axi_clk_div;
+	g_clock_config = &clock_select_config;
+	printf("Set Clock successful !!!\n");
+}
+
+#endif /* TGT_AP_SELECT_CLK */
+
+#ifdef DO_STAY_FOR_WATCHING
+
+void do_stay_for_watching_clock_reg(void)
+{
+	char ch;
+	printf("Press <Enter> to continue\n");
+	ch = serial_getc();
+	ch = ch;
+}
+
+#endif /* DO_STAY_FOR_WATCHING */
+
+
+#ifdef TGT_AP_DO_DDR_TEST
+
+/* DDR test case list */
+#define DDR_T_C_GET_INFO
+#define DDR_T_C_FUNCTION
+#define DDR_T_C_MEMORY_COPY
+#define DDR_T_C_BOUNDARY_SCAN
+#define DDR_T_C_PLL_SWITCH
+
+/* DDR test result storage base address */
+#define DDR_TEST_DATA_BASE 0x11C010C0
+#define DDR_T_MANU_ID_ADDR	(DDR_TEST_DATA_BASE+0X00)
+#define DDR_T_CAPACITY_ADDR	(DDR_TEST_DATA_BASE+0X04)
+#define DDR_T_BAND_WIDTH_ADDR	(DDR_TEST_DATA_BASE+0X08)
+#define DDR_T_PLL_SWITCH_ADDR	(DDR_TEST_DATA_BASE+0X0C)
+#define DDR_T_FUNCTION_ADDR	(DDR_TEST_DATA_BASE+0X10)
+#define DDR_T_BOUNDARY_ADDR	(DDR_TEST_DATA_BASE+0X14)
+#define DDR_T_MEM_COPY_ADDR	(DDR_TEST_DATA_BASE+0X18)
+#define DDR_T_MANU_NAME_ADDR	(DDR_TEST_DATA_BASE+0X1C)
+#define DDR_T_MANU_NAME_SIZE	8
+
+#define DDR_TEST_RESULT_OK	0XA55A6666
+#define DDR_TEST_RESULT_ERROR	0XDEADDEAD
+
+typedef unsigned int uint32;
+
+typedef struct ddr_manufacture {
+    UINT32 value;
+    const char* name;
+}DDR_MANUFACTURE;
+
+const static DDR_MANUFACTURE g_ddr_type[] = {
+	{0x0,"S4 SDRAM"},
+	{0x1,"S2 SDRAM"},
+	{0x2,"N NVM"},
+};
+
+const static DDR_MANUFACTURE g_ddr_manuacture[] ={
+    {0x3, "Elpida"},
+    {0x5, "Nanya"},
+    {0xff, "Micron"}
+};
+
+const static UINT16 g_ddr_capacity_value[] = {
+    8,
+    16,
+    32,
+    64,
+    128,
+    256,
+    512,
+    1024,
+    2048,
+    4096
+};
+
+const static UINT16 g_ddr_io_width[]={
+    32,
+    16,
+    8
+};
+
+extern unsigned int g_ddr_manufacture_id;
+extern unsigned int g_ddr_capacity_id;
+extern unsigned int con_dram_mrdata(unsigned int val);
+
+static void write_ddr_test_result( unsigned int addr , unsigned int val);
+static void do_set_gpo_pin(int pin_id, int pin_val);
+
+int get_dram_info(void)
+{
+	int i = 0;
+	UINT8 ddr_cap_id = 0;
+	UINT8 ddr_band_id = 0;
+	UINT8 ddr_type_id = 0;
+	char *ptr_addr;
+	const char *ptr_str;
+
+	printf("Read dram info... ");
+	ddr_cap_id = (g_ddr_capacity_id & 0x3C)>>2; //bit 2 3 4 5
+	ddr_band_id = (g_ddr_capacity_id & 0xC0)>>6; // bit 6 7
+	if((ddr_band_id >=0x1) || (ddr_cap_id < 0x4)) {
+		g_ddr_manufacture_id = con_dram_mrdata(g_ddr_manufacture_id);
+		g_ddr_capacity_id = con_dram_mrdata(g_ddr_capacity_id);
+	}
+	for(i = 0; i < 3; i++) {
+		if((g_ddr_manufacture_id & 0xFF) == g_ddr_manuacture[i].value) {
+			break;
+		}
+	}
+	if(i > 2) {
+		printf("unknown manufacture id: 0x%x\n",g_ddr_manufacture_id);
+		return -1;
+	}
+
+	ddr_cap_id = (g_ddr_capacity_id & 0x3C)>>2; //bit 2 3 4 5
+	ddr_band_id = (g_ddr_capacity_id & 0xC0)>>6; // bit 6 7
+	ddr_type_id = (g_ddr_capacity_id & 0x03); //bit 0 1
+	if(ddr_type_id > 2) {
+		printf("unknown type id 0x%x\n",ddr_type_id);
+		return -1;
+	}
+	if(ddr_band_id > 2) {
+		printf("unknown band id 0x%x\n",ddr_band_id);
+		return -1;
+	}
+	if(ddr_cap_id > 9) {
+		printf("unknown capacity id 0x%x\n",ddr_cap_id);
+		return -1;
+	}
+	printf("%s, ",g_ddr_type[ddr_type_id].name);
+	printf("%s, ", g_ddr_manuacture[i].name);
+	printf("id: 0x%x, ", (int)g_ddr_manuacture[i].value);
+	printf("bandwidth: %d bit, ", g_ddr_io_width[ddr_band_id]);
+	printf("capacity: %d MB\n", g_ddr_capacity_value[ddr_cap_id]);
+
+	writel((int)(g_ddr_io_width[ddr_band_id]),DDR_T_BAND_WIDTH_ADDR);
+	writel((int)(g_ddr_capacity_value[ddr_cap_id]),DDR_T_CAPACITY_ADDR);
+	writel((int)(g_ddr_manuacture[i].value),DDR_T_MANU_ID_ADDR);
+
+	ptr_str = (g_ddr_manuacture[i].name);
+	ptr_addr = (char *)(DDR_T_MANU_NAME_ADDR);
+	for(i = 0;i < DDR_T_MANU_NAME_SIZE; i++)
+		*ptr_addr++ = '\0';
+	ptr_addr = (char *)(DDR_T_MANU_NAME_ADDR);
+	for(i = 0;i < DDR_T_MANU_NAME_SIZE; i++)
+		*ptr_addr++ = *ptr_str++;
+	return 0;
+}
+
+#define DMC_STAT_CONFIG 0
+#define DMC_STAT_READY	3
+#define DMC_REG_BASE	RDA_DMC400_BASE
+#define DRAM_RW_TEST_DEBUG 0
+#include "ddr_init.h"
+static u32 get_dram_paramter(unsigned int offset_addr)
+{
+	unsigned int reg = 0;
+	unsigned status;
+
+	writel(DMC_STAT_CONFIG, DMC_REG_BASE + MEMC_CMD);
+	do {
+		status = readl(DMC_REG_BASE + MEMC_STATUS);
+#if DRAM_RW_TEST_DEBUG
+		printf("dmc status is %d\n",(int)status);
+#endif
+	} while (status != DMC_STAT_CONFIG);
+
+	reg = readl(RDA_DMC400_BASE+offset_addr);
+#if DRAM_RW_TEST_DEBUG
+	printf("read dmc reg 0x%x = 0x%x\n",offset_addr, reg);
+#endif
+	writel(DMC_STAT_READY, DMC_REG_BASE + MEMC_CMD);
+	do {
+		status = readl(DMC_REG_BASE + MEMC_STATUS);
+#if DRAM_RW_TEST_DEBUG
+		printf("dmc status is %d\n",(int)status);
+#endif
+	} while (status != DMC_STAT_READY);
+
+	return reg;
+}
+static int parse_dram_address(u32 *row_bits, u32 *col_bits, u32 *bank_bits, u32 *channel_bits,u32 *chip_bits,u32 *addr_order)
+{
+	u32 reg_val = 0,t;
+
+	// Get ADDR_CTRL register value
+	reg_val = get_dram_paramter(ADDR_CTRL);
+
+	/* Get column bits number */
+	t = reg_val & 0x0F;
+	if(t < 5)
+		*col_bits = 8 + t;
+	else
+		return -1;
+
+	/* Get row bits number */
+	t = (reg_val & 0x0F00)>>8;
+	if((t >= 2)&&(t <= 5))
+		*row_bits = 11 + t;
+	else
+		return -1;
+
+	/* Get bank bits number */
+	t = (reg_val & 0xF0000)>>16;
+	if((t == 2)||(t == 3))
+		*bank_bits = t;
+	else
+		return -1;
+
+	/* Get chip bits number */
+	t = (reg_val & 0x03000000)>>24;//bit24, bit25
+	if((t == 0)||(t == 1))
+		*chip_bits = t;
+	else
+		return -1;
+
+	/* Get channel bits number */
+	t = (reg_val & 0x30000000)>>28;//bit28, bit29
+	if((t == 0)||(t == 1))
+		*channel_bits = t;
+	else
+		return -1;
+
+	/* Get decode control register value */
+	reg_val = get_dram_paramter(DECODE_CTRL);
+	*addr_order = reg_val & 0x03;
+	return 0;
+}
+/*
+ ****************************************************************************************
+ *	@name:	ddr_rw_data_test
+ *	@description:	DRAM reading and writing row,bank,column address test.
+ *	@parameter
+ *		dram_offset_addr: the DRAM's offset address
+ * 		reverse_data: 	0, data will be reversed,such as 0xfe,0xfd,0xfc...
+ *		 		1, adta will not be reversed,such as 0x1,0x2,0x3...
+ * 		is_addr32: 	0, 8 bit address reading or writing
+ *	      			1, 32 bit address reading or writing
+ *	@return:	0(OK), -1(FAILED)
+ ****************************************************************************************
+*/
+int ddr_rw_data_test(unsigned int dram_offset_addr, unsigned int reverse_data, unsigned int is_addr32)
+{
+	unsigned int dat,rd_dat;
+	unsigned int temp_addr = 0,row_addr = 0,col_addr = 0,bank_addr = 0, end_addr = 0,dram_base_addr = 0x80000000;
+	unsigned int row_bits,col_bits,bank_bits,channel_bits,chip_bits,addr_order;
+	int i,is_err = 0,err_cnt = 0;
+	/* Parse DRAM address parameters */
+	i = parse_dram_address(&row_bits, &col_bits, &bank_bits, &channel_bits, &chip_bits, &addr_order);
+	if( i != 0) {
+		printf("Parse DRAM address parameter failed.\n");
+		return -1;
+	}
+	dram_base_addr += dram_offset_addr;
+	printf("\nDRAM RW test,offset addr 0x%x,",dram_offset_addr);
+	if(is_addr32)
+		printf("32 bit,");
+	else
+		printf("8 bit,");
+	if(reverse_data)
+		printf("reversed data\n");
+	else
+		printf("no reversed data\n");
+
+	/* Row address 8 bit or 32 bit data writing */
+	printf("\nStart row address RW test\n");
+	printf("Writing row data...\n");
+	row_addr = 0;
+	dat = 0;
+	i = 0;
+	end_addr = 0x100; //writing ending address
+	while(i < end_addr){
+		if(reverse_data)
+			dat = (unsigned int)~i;
+		else
+			dat = i;
+		row_addr = (unsigned int )i;
+		if(addr_order == 0x00)
+			temp_addr = (row_addr)<<(col_bits+bank_bits);
+		else if(addr_order == 0x02)
+			temp_addr = (row_addr)<<(col_bits+channel_bits);
+		else
+			temp_addr = (row_addr)<<(channel_bits + chip_bits + col_bits + bank_bits);
+
+		if(is_addr32){
+			//32bit data address
+			*(unsigned int *)(dram_base_addr + temp_addr) = (unsigned int )dat;
+			i += 4;
+		} else {
+			//8bit data address
+			dat = dat & 0xFF;
+			*(unsigned char *)(dram_base_addr + temp_addr) = (unsigned char)dat;
+			i += 1;
+		}
+#if DRAM_RW_TEST_DEBUG
+		printf("Row addr: 0x%x, data: 0x%x\n", (dram_base_addr + temp_addr), dat);
+#endif
+	}
+	/* Row address 8 bit or 32 bit data reading */
+	printf("Reading row data...\n");
+	row_addr = 0;
+	dat = 0;
+	i = 0;
+	is_err = 0;
+	err_cnt = 0;
+	while(i < end_addr){
+		if(reverse_data)
+			dat = (unsigned int)~i;
+		else
+			dat = i;
+		row_addr = i;
+		if(addr_order == 0x00)
+			temp_addr = (row_addr)<<(col_bits+bank_bits);
+		else if(addr_order == 0x02)
+			temp_addr = (row_addr)<<(col_bits+channel_bits);
+		else
+			temp_addr = (row_addr)<<(channel_bits + chip_bits + col_bits + bank_bits);
+
+		if(is_addr32) {
+			//32bit data address
+			rd_dat = *(unsigned int *)(dram_base_addr + temp_addr);
+			i += 4;
+		} else {
+			//8bit data address
+			dat = dat & 0xFF;
+			rd_dat = *(unsigned char *)(dram_base_addr + temp_addr);
+			i += 1;
+		}
+#if DRAM_RW_TEST_DEBUG
+		printf("Row addr: 0x%x, data: 0x%x\n", (dram_base_addr + temp_addr), rd_dat);
+#endif
+		if ( rd_dat != dat) {
+			is_err = 1;
+			err_cnt++;
+		}
+	}
+	if(!is_err) {
+		printf("Row address RW test passed !!!\n");
+	}else{
+		printf("Row address RW test failed ###\t, error count is 0x%d\n",err_cnt);
+		return -1;
+	}
+	/* Start to test column address reading ,writing */
+	printf("\nStart column address RW test\n");
+	printf("Writing column data...\n");
+	col_addr = 0;
+	dat = 0;
+	i = 0;
+	end_addr = 0x100;
+	while(i < end_addr) {
+		if(reverse_data)
+			dat = (unsigned int)~i;
+		else
+			dat = i;
+		col_addr = (unsigned int)i;
+		temp_addr = col_addr;
+		if(is_addr32){
+			*(unsigned int *)(dram_base_addr + temp_addr) = dat;
+			i += 4;
+		} else {
+			dat = dat & 0xFF;
+			*(unsigned char *)(dram_base_addr + temp_addr) = (unsigned char)dat;
+			i += 1;
+		}
+#if DRAM_RW_TEST_DEBUG
+		printf("Column addr: 0x%x, data: 0x%x\n", (dram_base_addr + temp_addr), dat);
+#endif
+	}
+	printf("Reading column data...\n");
+	col_addr = 0;
+	dat = 0;
+	i = 0;
+	err_cnt = 0;
+	is_err = 0;
+	while(i < end_addr) {
+		if(reverse_data)
+			dat = (unsigned int)~i;
+		else
+			dat = i;
+		col_addr = (unsigned int)i;
+		temp_addr = col_addr;
+		if(is_addr32){
+			rd_dat = *(unsigned int *)(dram_base_addr + temp_addr);
+			i += 4;
+		} else {
+			dat = dat & 0xFF;
+			rd_dat = *(unsigned char *)(dram_base_addr + temp_addr);
+			i += 1;
+		}
+#if DRAM_RW_TEST_DEBUG
+		printf("Column addr: 0x%x, data: 0x%x\n", (dram_base_addr + temp_addr), rd_dat);
+#endif
+		if ( rd_dat != dat) {
+			is_err = 1;
+			err_cnt++;
+		}
+	}
+	if(!is_err) {
+		printf("Column address RW test passed !!!\n");
+	}else{
+		printf("Column address RW test failed ###\t, error count is 0x%d\n",err_cnt);
+		return -1;
+	}
+	/* Start to test bank address reading and writing */
+	printf("\nStart bank address RW test\n");
+	printf("Writing bank data...\n");
+	bank_addr = 0;
+	dat = 0;
+	i = 0;
+	end_addr = 0x8;
+	while(i < end_addr) {
+		if(reverse_data)
+			dat = (unsigned int)~i;
+		else
+			dat = i;
+		bank_addr = (unsigned int)i;
+		if(addr_order == 0x02)
+			temp_addr = (bank_addr)<<(col_bits + channel_bits + row_bits);
+		else if(addr_order == 0x03)
+			temp_addr = (bank_addr)<<(col_bits+channel_bits);
+		else
+			temp_addr = (bank_addr)<<(col_bits);
+
+		if(is_addr32){
+			*(unsigned int *)(dram_base_addr + temp_addr) = dat;
+			i += 4;
+		} else {
+			dat = dat & 0xFF;
+			*(unsigned char *)(dram_base_addr + temp_addr) = (unsigned char)dat;
+			i += 1;
+		}
+#if DRAM_RW_TEST_DEBUG
+		printf("Bank addr: 0x%x, data: 0x%x\n", (dram_base_addr + temp_addr), dat);
+#endif
+	}
+	printf("Reading bank data...\n");
+	bank_addr = 0;
+	dat = 0;
+	i = 0;
+	err_cnt = 0;
+	is_err = 0;
+	while(i < end_addr) {
+		if(reverse_data)
+			dat = (unsigned int)~i;
+		else
+			dat = i;
+		bank_addr = (unsigned int)i;
+		if(addr_order == 0x02)
+			temp_addr = (bank_addr)<<(col_bits + channel_bits + row_bits);
+		else if(addr_order == 0x03)
+			temp_addr = (bank_addr)<<(col_bits+channel_bits);
+		else
+			temp_addr = (bank_addr)<<(col_bits);
+
+		if(is_addr32){
+			rd_dat = *(unsigned int *)(dram_base_addr + temp_addr);
+			i += 4;
+		} else {
+			dat = dat & 0xFF;
+			rd_dat = *(unsigned char *)(dram_base_addr + temp_addr);
+			i += 1;
+		}
+#if DRAM_RW_TEST_DEBUG
+		printf("Bank addr: 0x%x, data: 0x%x\n", (dram_base_addr + temp_addr), rd_dat);
+#endif
+		if ( rd_dat != dat) {
+			is_err = 1;
+			err_cnt++;
+		}
+	}
+	if(!is_err) {
+		printf("Bank address RW test passed !!!\n");
+	}else{
+		printf("Bank address RW test failed ###\t, error count is 0x%d\n",err_cnt);
+		return -1;
+	}
+	return 0;
+}
+
+int ddr_memory_copy_test(uint32 src_addr, uint32 des_addr, uint32 nwords)
+{
+	int ret = 0;
+	unsigned int dat = 0x00,t = 0;;
+	uint32 count;
+	volatile unsigned int *psrc, *pdes;
+
+	printf("ddr memory copy test: from  0x%x to 0x%x,0x%x words\n",
+		src_addr, des_addr, nwords);
+	/* write n bytes to src address */
+	psrc = (volatile unsigned int *)src_addr;
+	pdes = (volatile unsigned int *)des_addr;
+	count = nwords;
+	dat = 0;
+	while(count--)  {
+		*psrc++ = dat++;
+	}
+	/* copy bytes from src addr to des addr */
+	psrc = (volatile unsigned int *)src_addr;
+	pdes = (volatile unsigned int *)des_addr;
+	count = nwords;
+	while(count--) {
+		dat = *psrc++;
+		*pdes++ = dat;
+	}
+	/* compare data */
+	psrc = (volatile unsigned int *)src_addr;
+	pdes = (volatile unsigned int *)des_addr;
+	count = nwords;
+	dat = 0;
+	while(count--) {
+		t = *psrc++;
+		if(dat != t) {
+			printf("compare data error,position = %d\n",(int)count);
+			ret = -1;
+			break;
+		}
+		dat++;
+	}
+	return ret;
+}
+
+int ddr_boundscan_test(uint32 addr, uint32 nwords)
+{
+	unsigned int dat = 0;
+	uint32 count = nwords;
+	volatile unsigned int *pdes;
+
+	printf("ddr boundary scan test: addr: 0x%x, nwords: 0x%x\n",
+		addr,nwords);
+	if(nwords == 0)
+		return -1;
+	/* read data from boundary address */
+	pdes = (volatile unsigned int *)addr;
+	while(count--) {
+		dat = *pdes;
+		dat = dat;
+		printf("0x%x\n",dat);
+		pdes++;
+	}
+	return 0;
+}
+
+int ddr_pll_switch_test(int times)
+{
+	printf("ddr pll switch test times: %d\n",times);
+	while(times--) {
+		sys_shutdown_pll();
+		//ispi_open(0);
+		//pll_setup_init();
+		//pll_setup_freq();
+		sys_setup_pll();
+	}
+	return 0;
+}
+
+static void do_set_gpo_pin(int pin_id, int pin_val)
+{
+	unsigned int set_addr = 0x20930030; //GPIOA 's GPO register set address
+	unsigned int clr_addr = 0x20930034; // GPIOA 's GPO register reset address
+
+	switch(pin_id) {
+	case 0:
+		if(pin_val)
+			*(volatile unsigned int *)set_addr = 0x01;//gpo 0 = 1
+		else
+			*(volatile unsigned int *)clr_addr = 0x01;//gpo 0 = 0
+	break;
+	case 1:
+		if(pin_val)
+			*(volatile unsigned int *)set_addr = 0x02;//gpo 1 = 1
+		else
+			*(volatile unsigned int *)clr_addr = 0x02;//gpo 1 = 0
+	break;
+	case 2:
+		if(pin_val)
+			*(volatile unsigned int *)set_addr = 0x04;//gpo 2 = 1
+		else
+			*(volatile unsigned int *)clr_addr = 0x04;
+	break;
+	default:
+	break;
+	}
+#if 0
+	{
+		unsigned int val = *(volatile unsigned int *)set_addr;
+		printf("set_gpo_reg value : %x\n",val);
+	}
+#endif
+
+}
+
+static void write_ddr_test_result( unsigned int addr , unsigned int val)
+{
+	writel(val,addr);
+#if 0
+	printf("Write ddr test result: addr =  0x%x,val = 0x%x\n",addr,val);
+#endif
+}
+
+static void ddr_test_entry(void)
+{
+	int res[7]= {0},j = 0,err = 0;
+	uint32 ddr_start_addr = 0x80000000, ddr_end_addr = 0xbfffffff, scan_len = 6;
+
+	printf("\n%s: current ticks = %llu\n",__func__,get_ticks());
+	printf("--------------------DDR test starts-------------------------\n");
+	printf("MP:DDR test bootloader 4.0\n");
+	printf("SV:0x10\n");
+
+	/* ddr test starts */
+	do_set_gpo_pin(1,0);
+
+	/* reset gpo0 to low level */
+	do_set_gpo_pin(0,0);
+
+	/* avoid generating building warnning*/
+	for(j = 0;j<7;j++)
+		res[j] = 0;
+
+	ddr_start_addr = ddr_start_addr;
+	ddr_end_addr = ddr_end_addr;
+	scan_len = scan_len;
+
+#ifdef DDR_T_C_PLL_SWITCH
+	/* ddr pll switch test */
+	res[0] = ddr_pll_switch_test(100);
+#endif
+
+#ifdef DDR_T_C_GET_INFO
+	/* get ddr information */
+	res[1] = get_dram_info();
+#endif
+
+#ifdef DDR_T_C_FUNCTION
+	/* ddr function test */
+	res[2]  = ddr_rw_data_test(0x01000000,0,0);
+	res[2] += ddr_rw_data_test(0x02000000,0,1);
+	res[3]  = ddr_rw_data_test(0x03000000,1,0);
+	res[3] += ddr_rw_data_test(0x04000000,1,1);
+	if((res[2] == 0) && (res[3] == 0)) {
+		printf("ddr function test OK\n");
+		write_ddr_test_result(DDR_T_FUNCTION_ADDR,DDR_TEST_RESULT_OK);
+	} else {
+		printf("ddr function test error,res1 = %d,res2 = %d\n",res[2],res[3]);
+		write_ddr_test_result(DDR_T_FUNCTION_ADDR,DDR_TEST_RESULT_ERROR);
+	}
+#endif
+
+#ifdef DDR_T_C_BOUNDARY_SCAN
+	/* ddr boundary scan test from 0x80000000 to 0xBFFFFFFF */
+	scan_len = 3;
+	ddr_start_addr = 0x80000000;
+	ddr_end_addr = 0xBFFFFFFF;
+	res[4] = ddr_boundscan_test(ddr_start_addr, scan_len);
+	res[5] = ddr_boundscan_test((ddr_end_addr-scan_len), scan_len);
+	if((res[4] == 0) && (res[5] == 0)) {
+		printf("ddr boundary scan test OK\n");
+		write_ddr_test_result(DDR_T_BOUNDARY_ADDR,DDR_TEST_RESULT_OK);
+	} else {
+		printf("ddr boudary scan test error, res = 0x%x\n",res[4]);
+		write_ddr_test_result(DDR_T_BOUNDARY_ADDR,DDR_TEST_RESULT_ERROR);
+	}
+#endif
+
+#ifdef DDR_T_C_MEMORY_COPY
+	/* ddr memory copy test */
+	res[6] = ddr_memory_copy_test(0x84000000, 0x85000000, 0x1000);
+	if(res[6] == 0) {
+		printf("ddr memory copy test OK\n");
+		write_ddr_test_result(DDR_T_MEM_COPY_ADDR,DDR_TEST_RESULT_OK);
+	} else {
+		printf("ddr memory copy test error, res = 0x%x\n",res[6]);
+		write_ddr_test_result(DDR_T_MEM_COPY_ADDR,DDR_TEST_RESULT_ERROR);
+	}
+#endif
+
+#ifdef DDR_T_C_PLL_SWITCH
+	printf("ddr pll switch test OK\n");
+	write_ddr_test_result(DDR_T_PLL_SWITCH_ADDR, DDR_TEST_RESULT_OK);
+#endif
+	/*check all test case result */
+	err = 0;
+	for(j = 0; j<7;j++){
+		if(res[j] != 0){
+			err = -1;
+			break;
+		}
+	}
+	if(!err) {
+		do_set_gpo_pin(0,1);//test result ok
+		printf("\nDDR test successfully !!!\n");
+	}
+	/* ddr test ends */
+	do_set_gpo_pin(1,1);//gpo1 set high level
+	printf("--------------------DDR test ends-------------------------\n");
+	printf("\n%s: current ticks = %llu\n",__func__,get_ticks());
+}
+#endif /* TGT_AP_DO_DDR_TEST */
+
+#ifdef CONFIG_MEM_WR_TEST
+void mem_test_write(void)
+{
+        volatile unsigned int *addr;
+        int pos = 0, cnt = 0;
+
+        printf("Start writing DDR test!!!!!!\n");
+        addr = (volatile unsigned int *)(0x83000000);
+        while((u32)addr < 0x83008000) {
+                pos = cnt % 10;
+                *addr = test_pattern[pos];
+                addr++;
+                cnt++;
+        }
+}
+
+int mem_test_read(void)
+{
+        volatile unsigned int *addr;
+        unsigned int temp= 0;
+        int pos = 0, cnt = 0, i = 0;
+
+        printf("Start reading DDR test!!!!\n");
+
+        addr = (volatile unsigned int *)(0x83000000);
+
+        while((u32)addr < 0x83008000) {
+
+                pos = cnt % 10;
+                temp = test_pattern[pos];
+                if ( temp != *addr) {
+			printf("test error!!!!!, addr = %x\n", (unsigned int)addr);
+			//printf("GPIO output,addr=0x20930030,value=0x01\n");
+			//*(volatile unsigned int *)0x20930030 = 0x01;
+
+                        for (i = 0; i < 80;i++){
+                                printf("%x ", *(addr + i));
+                                if ((i % 4) == 0)
+                                        printf("\n");
+                        }
+
+                        return -1;
+                }
+
+                addr++;
+                cnt++;
+        }
+        serial_puts("DDR test OK********************************!\n");
+	//printf("GPIO output,addr = 0x20930030,value=0x02;\n");
+	//*(volatile unsigned int *)0x20930030 = 0x02;
+        return 0;
+}
+#endif /* CONFIG_MEM_WR_TEST */
+
+void sys_config_dcache_ema(unsigned int ema_val)
+{
+	unsigned int val;
+	unsigned int addr = RDA_APDEBUG_BASE + 0x24;
+	val = readl(addr);
+	/* clear bit 8,7,6 */
+	val &= (~(0x7 << 6));
+	val |= ((ema_val & 0x7) << 6);
+	writel(val,addr);
+}
+
+void sys_config_dram_qos(unsigned int idx)
+{
+	unsigned int val;
+	//L2cc_Ctrl register address
+	unsigned int addr = RDA_SYSCTRL_BASE + 0x100;
+	val = readl(addr);
+	val &= 0xFFFF00FF;
+	val |= (idx << 8);
+	val |= (idx << 12);
+	writel(val,addr);
+}
+
+int clock_init(void)
+{
+#ifdef DO_DDR_PLL_DEBUG
+	char choice = 'n';
+#endif
+
+	/* First check current usb usage */
+	check_usb_usage();
+
+	printf("Init Clock ...\n");
+	g_clock_config = get_default_clock_config();
+
+	printf("Clock config ver: %d.%d\n",
+		g_clock_config->VERSION_MAJOR, g_clock_config->VERSION_MINOR);
+
+	pmu_setup_init();
+
+#ifdef TGT_AP_SELECT_CLK
+	do_clock_selection();
+#endif /* TGT_AP_SELECT_CLK */
+
+#ifdef DO_DDR_PLL_DEBUG
+	printf("If you want to config the ddr para manully ?(y = yes, n = no) \n");
+	choice = serial_getc();
+	if (choice == 'y') {
+		memcpy(&clock_debug_config, g_clock_config,
+				sizeof(clock_debug_config));
+		g_clock_config = &clock_debug_config;
+		pmu_setup_calibration_voltage(1);
+		pmu_setup_calibration_voltage(2);
+		//pmu_buck4_buck3_choose();
+		freq_choose();
+		data_bits_choose();
+		clock_load_ddr_cal_config();
+	}
+#endif
+
+	sys_shutdown_pll();
+	ispi_open(0);
+	pll_setup_init();
+#ifdef DO_DDR_PLL_DEBUG
+	if (choice == 'y')
+		cmd_input("ddrPll", 0);
+#endif
+	pll_setup_freq();
+	sys_setup_pll();
+	sys_setup_clk();
+	/* modem use qos6_ctrl register */
+	sys_config_dram_qos(6);
+	/* set l2 d-cache ema is 0 */
+	sys_config_dcache_ema(0);
+
+	if (g_clock_config->DDR_CAL) {
+		printf("Init DDR for ddr_cal\n");
+		ddr_init(g_clock_config->DDR_FLAGS, g_clock_config->DDR_PARA);
+		printf("Done\n");
+		pll_setup_mem_cal();
+		clock_save_config();
+	} else {
+		pll_setup_mem();
+	}
+
+	sys_dump_pll_freq();
+	sys_dump_clk();
+	pll_dump_reg();
+
+	printf("Init DDR, flag = 0x%04x, para = 0x%08lx\n",
+		g_clock_config->DDR_FLAGS, g_clock_config->DDR_PARA);
+	ddr_init(g_clock_config->DDR_FLAGS, g_clock_config->DDR_PARA);
+	printf("Done\n");
+
+#ifdef TGT_AP_DO_DDR_TEST
+	ddr_test_entry();
+#endif /* TGT_AP_DO_DDR_TEST */
+
+#ifdef CONFIG_MEM_WR_TEST
+	mem_test_write();
+	mem_test_read();
+#endif /* CONFIG_MEM_WR_TEST */
+
+#ifdef DO_STAY_FOR_WATCHING
+	do_stay_for_watching_clock_reg();
+#endif /* DO_STAY_FOR_WATCHING */
+
+	return 0;
+}
+#else /* CONFIG_RDA_FPGA */
+
+int clock_init(void)
+{
+	u16 ddr_flags = DDR_FLAGS_DLLOFF
+		| DDR_FLAGS_ODT(1)
+		| DDR_FLAGS_RON(0);
+	//16bit
+	u32 ddr_para = DDR_PARA_MEM_BITS(2)
+		| DDR_PARA_BANK_BITS(3)
+		| DDR_PARA_ROW_BITS(4)
+		| DDR_PARA_COL_BITS(1);
+
+	printf("Init DDR\n");
+	ddr_init(ddr_flags, ddr_para);
+	printf("Done\n");
+
+#ifdef TGT_AP_DO_DDR_TEST
+	ddr_test_entry();
+#endif /* TGT_AP_DO_DDR_TEST */
+
+#ifdef CONFIG_MEM_WR_TEST
+	mem_test_write();
+	mem_test_read();
+#endif /* CONFIG_MEM_WR_TEST */
+
+	return 0;
+}
+
+#endif /* CONFIG_RDA_FPGA */
diff --git a/board/rda/rda8850e/clock_config.c b/board/rda/rda8850e/clock_config.c
new file mode 100644
index 0000000000..ac169fb37b
--- /dev/null
+++ b/board/rda/rda8850e/clock_config.c
@@ -0,0 +1,150 @@
+#ifndef TARGET_TOOL
+#include <common.h>
+#include <asm/arch/factory.h>
+#include "clock_config.h"
+#endif
+
+#include "ddr.h"
+#include "tgt_ap_clock_config.h"
+
+static const struct clock_config clock_default_config = {
+	/* Header */
+	0, 			// MAGIC;
+	CLOCK_VER_MAJOR,	// VERSION_MAJOR;
+	CLOCK_VER_MINOR,	// VERSION_MINOR;
+	/* PLL Freqs (MHz) */
+	_TGT_AP_PLL_CPU_FREQ,	// PLL_FREQ_CPU; /* 05, 06 */
+	_TGT_AP_PLL_BUS_FREQ,	// PLL_FREQ_BUS; /* 25, 26 */
+	_TGT_AP_PLL_MEM_FREQ,	// PLL_FREQ_MEM; /* 65, 66 */
+	_TGT_AP_PLL_USB_FREQ,	// PLL_FREQ_USB; /* 85, 86 */
+	/* DDR Cal */
+	0,			// DDR_CAL;
+	/* DDR_FLAGS */
+	DDR_FLAGS_ODT(_TGT_AP_DDR_ODT)	// 010 -- 120 Ohm
+#if (_TGT_AP_DDR_CLOCK < 200)
+	    | DDR_FLAGS_DLLOFF
+#endif
+#ifdef _TGT_AP_DDR_LOWPWR
+	    | DDR_FLAGS_LOWPWR
+#endif
+	    | DDR_FLAGS_RON(_TGT_AP_DDR_RON),	// 00 -- 40 Ohm
+
+	/* DDR_PARA */
+	DDR_PARA_CHIP_BITS(_TGT_AP_DDR_CHIP_BITS)
+	    | DDR_PARA_MEM_BITS(_TGT_AP_DDR_MEM_BITS)
+	    | DDR_PARA_BANK_BITS(_TGT_AP_DDR_BANK_BITS)
+	    | DDR_PARA_ROW_BITS(_TGT_AP_DDR_ROW_BITS )
+	    | DDR_PARA_COL_BITS(_TGT_AP_DDR_COL_BITS),
+
+	/* AP sysctrl */
+	_TGT_AP_CLK_CPU,	// CLK_CPU;
+	_TGT_AP_CLK_AXI,	// CLK_AXI;
+	_TGT_AP_CLK_GCG,	// CLK_GCG;
+	_TGT_AP_CLK_AHB1,	// CLK_AHB1;
+	_TGT_AP_CLK_APB1,	// CLK_APB1;
+	_TGT_AP_CLK_APB2,	// CLK_APB2;
+	_TGT_AP_CLK_MEM,	// CLK_MEM;
+	_TGT_AP_CLK_GPU,	// CLK_GPU;
+	_TGT_AP_CLK_VPU,	// CLK_VPU;
+	_TGT_AP_CLK_VOC,	// CLK_VOC;
+	_TGT_AP_CLK_SFLSH,	// CLK_SFLSH;
+	0,			// RESERVE;
+
+	/* DDR timings, defined in target */
+	DDR_CHAN_1_VALID_VAL,	// DDR_CHAN_1_VALID;
+	DDR_TIMING_101H_VAL,	// DDR_TIMING_101H;
+	DDR_TIMING_102H_VAL,	// DDR_TIMING_102H;
+	DDR_TIMING_103H_VAL,	// DDR_TIMING_103H;
+	DDR_TIMING_104H_VAL,	// DDR_TIMING_104H;
+	DDR_TIMING_105H_VAL,	// DDR_TIMING_105H;
+	DDR_TIMING_106H_VAL,	// DDR_TIMING_106H;
+	DDR_TIMING_107H_VAL,	// DDR_TIMING_107H;
+	DDR_TIMING_108H_VAL,	// DDR_TIMING_108H;
+	DDR_TIMING_109H_VAL,	// DDR_TIMING_109H;
+	DDR_TIMING_10AH_VAL,	// DDR_TIMING_10AH;
+	DDR_TIMING_10BH_VAL,	// DDR_TIMING_10BH;
+	DDR_TIMING_10CH_VAL,	// DDR_TIMING_10CH;
+	DDR_TIMING_10DH_VAL,	// DDR_TIMING_10DH;
+	DDR_TIMING_10EH_VAL,	// DDR_TIMING_10EH;
+	DDR_TIMING_10FH_VAL,	// DDR_TIMING_10FH;
+
+	DDR_CHAN_2_VALID_VAL,	// DDR_CHAN_2_VALID;
+	DDR_TIMING_121H_VAL,	// DDR_TIMING_121H;
+	DDR_TIMING_122H_VAL,	// DDR_TIMING_122H;
+	DDR_TIMING_123H_VAL,	// DDR_TIMING_123H;
+	DDR_TIMING_124H_VAL,	// DDR_TIMING_124H;
+	DDR_TIMING_125H_VAL,	// DDR_TIMING_125H;
+	DDR_TIMING_126H_VAL,	// DDR_TIMING_126H;
+	DDR_TIMING_127H_VAL,	// DDR_TIMING_127H;
+	DDR_TIMING_128H_VAL,	// DDR_TIMING_128H;
+	DDR_TIMING_129H_VAL,	// DDR_TIMING_129H;
+	DDR_TIMING_12AH_VAL,	// DDR_TIMING_12AH;
+	DDR_TIMING_12BH_VAL,	// DDR_TIMING_12BH;
+	DDR_TIMING_12CH_VAL,	// DDR_TIMING_12CH;
+	DDR_TIMING_12DH_VAL,	// DDR_TIMING_12DH;
+	DDR_TIMING_12EH_VAL,	// DDR_TIMING_12EH;
+	DDR_TIMING_12FH_VAL,	// DDR_TIMING_12FH;
+
+	DDR_CHAN_3_VALID_VAL,	// DDR_CHAN_3_VALID;
+	DDR_TIMING_141H_VAL,	// DDR_TIMING_141H;
+	DDR_TIMING_142H_VAL,	// DDR_TIMING_142H;
+	DDR_TIMING_143H_VAL,	// DDR_TIMING_143H;
+	DDR_TIMING_144H_VAL,	// DDR_TIMING_144H;
+	DDR_TIMING_145H_VAL,	// DDR_TIMING_145H;
+	DDR_TIMING_146H_VAL,	// DDR_TIMING_146H;
+	DDR_TIMING_147H_VAL,	// DDR_TIMING_147H;
+	DDR_TIMING_148H_VAL,	// DDR_TIMING_148H;
+	DDR_TIMING_149H_VAL,	// DDR_TIMING_149H;
+	DDR_TIMING_14AH_VAL,	// DDR_TIMING_14AH;
+	DDR_TIMING_14BH_VAL,	// DDR_TIMING_14BH;
+	DDR_TIMING_14CH_VAL,	// DDR_TIMING_14CH;
+	DDR_TIMING_14DH_VAL,	// DDR_TIMING_14DH;
+	DDR_TIMING_14EH_VAL,	// DDR_TIMING_14EH;
+	DDR_TIMING_14FH_VAL,	// DDR_TIMING_14FH;
+
+	DDR_CHAN_4_VALID_VAL,	// DDR_CHAN_4_VALID;
+	DDR_TIMING_161H_VAL,	// DDR_TIMING_161H;
+	DDR_TIMING_162H_VAL,	// DDR_TIMING_162H;
+	DDR_TIMING_163H_VAL,	// DDR_TIMING_163H;
+	DDR_TIMING_164H_VAL,	// DDR_TIMING_164H;
+	DDR_TIMING_165H_VAL,	// DDR_TIMING_165H;
+	DDR_TIMING_166H_VAL,	// DDR_TIMING_166H;
+	DDR_TIMING_167H_VAL,	// DDR_TIMING_167H;
+	DDR_TIMING_168H_VAL,	// DDR_TIMING_168H;
+	DDR_TIMING_169H_VAL,	// DDR_TIMING_169H;
+	DDR_TIMING_16AH_VAL,	// DDR_TIMING_16AH;
+	DDR_TIMING_16BH_VAL,	// DDR_TIMING_16BH;
+	DDR_TIMING_16CH_VAL,	// DDR_TIMING_16CH;
+	DDR_TIMING_16DH_VAL,	// DDR_TIMING_16DH;
+	DDR_TIMING_16EH_VAL,	// DDR_TIMING_16EH;
+	DDR_TIMING_16FH_VAL,	// DDR_TIMING_16FH;
+
+	DDR_TIMING_160H_VAL,	// DDR_TIMING_160H;
+	DDR_TIMING_180H_VAL,	// DDR_TIMING_180H;
+	DDR_TIMING_181H_VAL,	// DDR_TIMING_181H;
+	DDR_TIMING_182H_VAL,	// DDR_TIMING_182H;
+	DDR_TIMING_183H_VAL,	// DDR_TIMING_183H;
+	DDR_TIMING_184H_VAL,	// DDR_TIMING_184H;
+	DDR_TIMING_185H_VAL,	// DDR_TIMING_185H;
+	DDR_TIMING_186H_VAL,	// DDR_TIMING_186H;
+	DDR_TIMING_187H_VAL,	// DDR_TIMING_187H;
+	DDR_TIMING_188H_VAL,	// DDR_TIMING_188H;
+	DDR_TIMING_189H_VAL,	// DDR_TIMING_189H;
+	DDR_TIMING_18AH_VAL,	// DDR_TIMING_18AH;
+	DDR_TIMING_18BH_VAL,	// DDR_TIMING_18BH;
+	DDR_TIMING_18CH_VAL,	// DDR_TIMING_18CH;
+	DDR_TIMING_18DH_VAL,	// DDR_TIMING_18DH;
+	DDR_TIMING_18EH_VAL,	// DDR_TIMING_18EH;
+	DDR_TIMING_18FH_VAL,	// DDR_TIMING_18FH;
+	DDR_TIMING_69H_VAL,	// DDR_TIMING_69H;
+};
+
+const struct clock_config *get_default_clock_config(void)
+{
+#ifndef TARGET_TOOL
+	BUILD_BUG_ON(sizeof(struct clock_config) > AP_FACTORY_CLOCK_CFG_LEN);
+#endif
+
+	return &clock_default_config;
+}
+
diff --git a/board/rda/rda8850e/clock_config.h b/board/rda/rda8850e/clock_config.h
new file mode 100644
index 0000000000..46a090b15c
--- /dev/null
+++ b/board/rda/rda8850e/clock_config.h
@@ -0,0 +1,133 @@
+#ifndef __CLOCK_CONFIG_H__
+#define __CLOCK_CONFIG_H__
+
+typedef unsigned long               UINT32;
+typedef unsigned short              UINT16;
+typedef long                        INT32;
+typedef short                       INT16;
+typedef unsigned char               UINT8;
+typedef char                        INT8;
+
+#define CLOCK_VER_MAJOR		2
+#define CLOCK_VER_MINOR		0
+
+struct clock_config {
+	/* Header */
+	UINT32 MAGIC;
+	UINT16 VERSION_MAJOR;
+	UINT16 VERSION_MINOR;
+	/* PLL Freqs (MHz) */
+	UINT32 PLL_FREQ_CPU;	/* 05, 06 */
+	UINT32 PLL_FREQ_BUS;	/* 25, 26 */
+	UINT32 PLL_FREQ_MEM;	/* 65, 66 */
+	UINT32 PLL_FREQ_USB;	/* 85, 86 */
+	/* DDR Flags */
+	UINT16 DDR_CAL;
+	UINT16 DDR_FLAGS;
+	UINT32 DDR_PARA;
+	/* AP sysctrl */
+	UINT16 CLK_CPU;
+	UINT16 CLK_AXI;
+	UINT16 CLK_GCG;
+	UINT16 CLK_AHB1;
+	UINT16 CLK_APB1;
+	UINT16 CLK_APB2;
+	UINT16 CLK_MEM;
+	UINT16 CLK_GPU;
+	UINT16 CLK_VPU;
+	UINT16 CLK_VOC;
+	UINT16 CLK_SFLSH;
+	UINT16 RESERVE;
+	/* DDR timings */
+	UINT16 DDR_CHAN_1_VALID;
+	UINT16 DDR_TIMING_101H;
+	UINT16 DDR_TIMING_102H;
+	UINT16 DDR_TIMING_103H;
+	UINT16 DDR_TIMING_104H;
+	UINT16 DDR_TIMING_105H;
+	UINT16 DDR_TIMING_106H;
+	UINT16 DDR_TIMING_107H;
+	UINT16 DDR_TIMING_108H;
+	UINT16 DDR_TIMING_109H;
+	UINT16 DDR_TIMING_10AH;
+	UINT16 DDR_TIMING_10BH;
+	UINT16 DDR_TIMING_10CH;
+	UINT16 DDR_TIMING_10DH;
+	UINT16 DDR_TIMING_10EH;
+	UINT16 DDR_TIMING_10FH;
+
+	UINT16 DDR_CHAN_2_VALID;
+	UINT16 DDR_TIMING_121H;
+	UINT16 DDR_TIMING_122H;
+	UINT16 DDR_TIMING_123H;
+	UINT16 DDR_TIMING_124H;
+	UINT16 DDR_TIMING_125H;
+	UINT16 DDR_TIMING_126H;
+	UINT16 DDR_TIMING_127H;
+	UINT16 DDR_TIMING_128H;
+	UINT16 DDR_TIMING_129H;
+	UINT16 DDR_TIMING_12AH;
+	UINT16 DDR_TIMING_12BH;
+	UINT16 DDR_TIMING_12CH;
+	UINT16 DDR_TIMING_12DH;
+	UINT16 DDR_TIMING_12EH;
+	UINT16 DDR_TIMING_12FH;
+
+	UINT16 DDR_CHAN_3_VALID;
+	UINT16 DDR_TIMING_141H;
+	UINT16 DDR_TIMING_142H;
+	UINT16 DDR_TIMING_143H;
+	UINT16 DDR_TIMING_144H;
+	UINT16 DDR_TIMING_145H;
+	UINT16 DDR_TIMING_146H;
+	UINT16 DDR_TIMING_147H;
+	UINT16 DDR_TIMING_148H;
+	UINT16 DDR_TIMING_149H;
+	UINT16 DDR_TIMING_14AH;
+	UINT16 DDR_TIMING_14BH;
+	UINT16 DDR_TIMING_14CH;
+	UINT16 DDR_TIMING_14DH;
+	UINT16 DDR_TIMING_14EH;
+	UINT16 DDR_TIMING_14FH;
+
+	UINT16 DDR_CHAN_4_VALID;
+	UINT16 DDR_TIMING_161H;
+	UINT16 DDR_TIMING_162H;
+	UINT16 DDR_TIMING_163H;
+	UINT16 DDR_TIMING_164H;
+	UINT16 DDR_TIMING_165H;
+	UINT16 DDR_TIMING_166H;
+	UINT16 DDR_TIMING_167H;
+	UINT16 DDR_TIMING_168H;
+	UINT16 DDR_TIMING_169H;
+	UINT16 DDR_TIMING_16AH;
+	UINT16 DDR_TIMING_16BH;
+	UINT16 DDR_TIMING_16CH;
+	UINT16 DDR_TIMING_16DH;
+	UINT16 DDR_TIMING_16EH;
+	UINT16 DDR_TIMING_16FH;
+
+	UINT16 DDR_TIMING_160H;
+	UINT16 DDR_TIMING_180H;
+	UINT16 DDR_TIMING_181H;
+	UINT16 DDR_TIMING_182H;
+	UINT16 DDR_TIMING_183H;
+	UINT16 DDR_TIMING_184H;
+	UINT16 DDR_TIMING_185H;
+	UINT16 DDR_TIMING_186H;
+	UINT16 DDR_TIMING_187H;
+	UINT16 DDR_TIMING_188H;
+	UINT16 DDR_TIMING_189H;
+	UINT16 DDR_TIMING_18AH;
+	UINT16 DDR_TIMING_18BH;
+	UINT16 DDR_TIMING_18CH;
+	UINT16 DDR_TIMING_18DH;
+	UINT16 DDR_TIMING_18EH;
+	UINT16 DDR_TIMING_18FH;
+
+	UINT16 DDR_TIMING_69H;
+};
+
+const struct clock_config *get_default_clock_config(void);
+
+#endif
diff --git a/board/rda/rda8850e/config.mk b/board/rda/rda8850e/config.mk
new file mode 100644
index 0000000000..39782ba05e
--- /dev/null
+++ b/board/rda/rda8850e/config.mk
@@ -0,0 +1,15 @@
+#
+#the spl code should not exceed the SPL_MAX_SIZE,and if 
+#the spl don't up to the max size, paddint the last with
+#zero(or 0xff?)
+
+#48kbytes, 48*1024
+#SPL_APPENDING_TO	:= 48
+#SPL_MAX_SIZE	:= 49512
+
+# space for spl(48KiB) & mtd partition table(4KiB),
+# so uboot offset 52KiB(48 + 4).
+
+SPL_APPENDING_TO   := 52
+
+CONFIG_SPL_SIGNATURE_CHECK_IMAGE := y
diff --git a/board/rda/rda8850e/ddr.c b/board/rda/rda8850e/ddr.c
new file mode 100644
index 0000000000..b288e2017b
--- /dev/null
+++ b/board/rda/rda8850e/ddr.c
@@ -0,0 +1,753 @@
+#include <common.h>
+#include <asm/arch/rda_iomap.h>
+#include <asm/io.h>
+#include "tgt_ap_clock_config.h"
+
+#define DDR_TYPE	_TGT_AP_DDR_TYPE
+#if (DDR_TYPE == 2)
+#include "lpddr2_init.h"
+#elif (DDR_TYPE == 3)
+#include "ddr3_init.h"
+#else
+#error "_TGT_AP_DDR_TYPE is not valid !"
+#endif
+#include <asm/arch/rda_sys.h>
+
+#pragma GCC push_options
+#pragma GCC optimize ("O0")
+
+#define DF_DELAY  (0x10000)
+
+#define DMC_REG_BASE RDA_DMC400_BASE
+#define PHY_REG_BASE RDA_DDRPHY_BASE
+
+/*To test DDR self-refresh timing */
+#ifdef TGT_AP_SET_DDR_LP_PARAM
+#define SEL_DDR_REG_ESR_TAB_SIZE 16
+#define SEL_DDR_REG_NUMBER 4
+
+enum DMC_STATE_VALUE
+{
+	DMC_STATE_CONFIG = 0X0,
+	DMC_STATE_LOW_POWER = 0X1,
+	DMC_STATE_PAUSED = 0X2,
+	DMC_STATE_READY = 0X03,
+};
+enum SEL_DDR_REG_INDEX
+{
+	DDR_REG_IDX_ESR = 0,
+	DDR_REG_IDX_XSR,
+	DDR_REG_IDX_XRCKD,
+	DDR_REG_IDX_CKSRD,
+};
+typedef struct
+{
+	const char *sel_str;
+	UINT32 sel_val;
+}sel_ddr_reg_val_item_t;
+
+const static sel_ddr_reg_val_item_t sel_ddr_reg_esr_tab[] = {
+	{"0: 0x00",0x00},{"1: 0x01",0x01},{"2: 0x02",0x02},{"3: 0x03",0x03},
+	{"4: 0x04",0x04},{"5: 0x05",0x05},{"6: 0x06",0x06},{"7: 0x07",0x07},
+	{"8: 0x08",0x08},{"9: 0x09",0x09},{"a: 0x0A",0x0A},{"b: 0x0B",0x0B},
+	{"c: 0x0C",0x0C},{"d: 0x0D",0x0D},{"e: 0x0E",0x0E},{"f: 0x0F",0x0F},
+};
+const static sel_ddr_reg_val_item_t sel_ddr_reg_xsr_tab[] = {
+	{"0: 0x1D8",0x1D8},
+	{"1: 0x1DC",0x1DC},
+	{"2: 0x1E0",0x1E0},
+	{"3: 0x1E4",0x1E4},
+	{"4: 0x1E8",0x1E8},
+	{"5: 0x1EC",0x1EC},
+	{"6: 0x1F0",0x1F0},
+	{"7: 0x1F4",0x1F4},
+	{"8: 0x1F8",0x1F8},
+	{"9: 0x1FA",0x1FA},
+	{"a: 0x1FB",0x1FB},
+	{"b: 0x1FC",0x1FC},
+	{"c: 0x1FD",0x1FD},
+	{"d: 0x1FE",0x1FE},
+	{"e: 0x1FF",0x1FF},
+	{"f: 0x200",0x200},
+};
+const static sel_ddr_reg_val_item_t sel_ddr_reg_xrckd_tab[] = {
+	{"0: 0x00",0x00},{"1: 0x01",0x01},{"2: 0x02",0x02},{"3: 0x03",0x03},
+	{"4: 0x04",0x04},{"5: 0x05",0x05},{"6: 0x06",0x06},{"7: 0x07",0x07},
+	{"8: 0x08",0x08},{"9: 0x09",0x09},{"a: 0x0A",0x0A},{"b: 0x0B",0x0B},
+	{"c: 0x0C",0x0C},{"d: 0x0D",0x0D},{"e: 0x0E",0x0E},{"f: 0x0F",0x0F},
+};
+
+typedef struct {
+	const char *name_str;
+	unsigned int offset_val;
+}sel_ddr_reg_info_item_t;
+
+const static sel_ddr_reg_info_item_t sel_ddr_reg_tab[] = {
+	{"enter self-refresh timing",0x260,},
+	{"exit self-refresh timing",0x264,},
+	{"self-refresh to DRAM clock disable timing",0x268,},
+	{"DRAM clock enable to exist self-refresh timing",0x26C,},
+};
+typedef struct
+{
+	unsigned int stop_mem_clock_idle:1; //bit0
+	unsigned int stop_mem_clock_sref:1; //bit1
+	unsigned int auto_power_down	:1; //bit2
+	unsigned int auto_self_refresh	:1; //bit3
+	unsigned int asr_period		:4; //bit4-bit7
+} ddr_lp_cntl_reg_bit_t;
+typedef union
+{
+	unsigned int value;
+	ddr_lp_cntl_reg_bit_t bit;
+} ddr_lp_cntl_reg_t;
+
+static int _ddr_config_low_power_mode(void)
+{
+	char choice = 'n';
+	int wait_idle = 0;
+	unsigned int dmc_state = 0,temp;
+	ddr_lp_cntl_reg_t lp_reg,lp_reg_set;
+
+	/* Print message for selection */
+	printf("\nConfigure LOWPWR_CTRL register manully?(y=yes,n=no)\n");
+	choice = serial_getc();
+	if((choice != 'y') && (choice != 'Y')) {
+		printf("Using default value for DDR configuration\n");
+		return -1;
+	}
+LAB_CONFIG:
+	/* initiale value */
+	dmc_state = 0;
+	temp = 0;
+	lp_reg.value = 0;
+	lp_reg_set.value = 0;
+
+	/* check dmc current state */
+	dmc_state = readl(DMC_REG_BASE + MEMC_STATUS);
+	if(dmc_state != DMC_STATE_CONFIG) {
+		printf("DMC is not in CONFIG state, current state value: 0x%x,exit\n",dmc_state);
+		return -1;
+	}
+	/* read current low power configuration value */
+	lp_reg_set.value = 0;
+	lp_reg.value = readl(DMC_REG_BASE + LOWPWR_CTRL);
+	printf("Current LOWPWR_CTRL register value: 0x%x\n",lp_reg.value);
+	/* set stop_mem_clock_idle */
+#if 0
+	/* In RDA8850E, the DMC400 do not support auto power down mode,
+	   so
+		stop_mem_clock_idle = 0,
+		stop_mem_clock_sref = 0,
+		auto_power_down = 0
+	*/
+	lp_reg_set.bit.stop_mem_clock_idle = 0;
+	lp_reg_set.bit.stop_mem_clock_sref = 0;
+	lp_reg_set.bit.auto_power_down = 0;
+	lp_reg_set.bit.auto_self_refresh = 1; //enable auto self refresh mode
+#else
+	printf("Enable or disable stop_mem_clock_idle ? (e/d)\n");
+	choice = serial_getc();
+	printf("Your choice is: %c\n",choice);
+	if((choice == 'e')||(choice == 'E')) {
+		lp_reg_set.bit.stop_mem_clock_idle = 1;
+	} else {
+		lp_reg_set.bit.stop_mem_clock_idle = 0;
+	}
+	/* set stop_mem_clock_sref */
+	printf("Enable or disable stop_mem_clock_sref ? (e/d)\n");
+	choice = serial_getc();
+	printf("Your choice is: %c\n",choice);
+	if((choice == 'e')||(choice == 'E')) {
+		lp_reg_set.bit.stop_mem_clock_sref = 1;
+	} else {
+		lp_reg_set.bit.stop_mem_clock_sref = 0;
+	}
+	/* set auto_power_down */
+	printf("Enable or disable auto_power_down ? (e/d)\n");
+	choice = serial_getc();
+	printf("Your choice is: %c\n",choice);
+	if((choice == 'e')||(choice == 'E')) {
+		lp_reg_set.bit.auto_power_down = 1;
+	} else {
+		lp_reg_set.bit.auto_power_down = 0;
+	}
+	/* set auto_self_refresh */
+	printf("Enable or disable auto_self_refresh ? (e/d)\n");
+	choice = serial_getc();
+	printf("Your choice is: %c\n",choice);
+	if((choice == 'e')||(choice == 'E')) {
+		lp_reg_set.bit.auto_self_refresh = 1;
+	} else {
+		lp_reg_set.bit.auto_self_refresh = 0;
+	}
+#endif
+	/* set asr period */
+	printf("Set asr_period: 0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f\n");
+	choice = serial_getc();
+	printf("Your choice is: %c\n",choice);
+	if((choice >= 'a')&&(choice <= 'f'))
+		choice -= 0x20;
+	if((choice >= 'A') && (choice <= 'F'))
+		choice -=0x37;
+	else
+		choice -=0x30;
+
+	temp = (unsigned int )choice;
+	printf("temp: 0x%x\n",temp);
+	if(temp > 0x0F) {
+		printf("Input data error,use default value 0x04\n");
+		temp = 0x04;
+	}
+	lp_reg_set.bit.asr_period = temp;
+	/* be sure to write */
+	printf("LOWPWR_CTRL register's setting value: 0x%x\n",lp_reg_set.value);
+	printf("Write to register ? (y/n)\n");
+	choice = serial_getc();
+	if((choice != 'y')&&(choice != 'Y')) {
+		printf("Writing cancelled,exit\n");
+		goto LAB_RECONFIG;
+	}
+	/* write register */
+	printf("Writing register...");
+	writel(lp_reg_set.value, DMC_REG_BASE + LOWPWR_CTRL);
+	wait_idle = DF_DELAY + 0x10;
+	while (wait_idle--);
+	printf("address is 0x%x, value is 0x%x\n",LOWPWR_CTRL,lp_reg_set.value);
+	/* read resigter */
+	printf("Reading register...");
+	temp = readl(DMC_REG_BASE + LOWPWR_CTRL);
+	printf("address is 0x%x, value is 0x%x\n",LOWPWR_CTRL,temp);
+LAB_RECONFIG:
+	printf("\nRe-configure LOWPWR_CTRL register ? (y/n)\n");
+	choice = serial_getc();
+	if((choice == 'y') || (choice == 'Y')) {
+		goto LAB_CONFIG;
+	}
+	printf("Configure LOWPWR_CTRL register success !!!\n");
+	return 0;
+}
+static int _ddr_set_refresh_timing(void)
+{
+	char choice = 'n';
+	int try_times = 0,i,idx = 0,wait_idle = 0;
+	unsigned int temp,reg_val[SEL_DDR_REG_NUMBER] = {0};
+	unsigned int dmc_status = 0;
+
+	dmc_status = dmc_status;
+	/* Print message for selection */
+	printf("Configure DDR parameters manully?(y=yes,n=no)\n");
+	choice = serial_getc();
+	if((choice != 'y') && (choice != 'Y')) {
+		printf("Using default value for DDR configuration\n");
+		return 0;
+	}
+	idx = 0;
+LAB_INPUT:
+	try_times = 0;
+	while(1) {
+		/* get current register value */
+		temp = readl(DMC_REG_BASE + sel_ddr_reg_tab[idx].offset_val);
+		printf("\nConfigure %s parameter, current value is: 0x%x\n",
+			sel_ddr_reg_tab[idx].name_str, temp);
+		/* print selection table */
+		switch(idx){
+		case DDR_REG_IDX_ESR:
+			for( i = 0; i < SEL_DDR_REG_ESR_TAB_SIZE; i++)
+				printf("\t%s\n",sel_ddr_reg_esr_tab[i].sel_str);
+		break;
+		case DDR_REG_IDX_XSR:
+			for( i = 0; i < SEL_DDR_REG_ESR_TAB_SIZE; i++)
+				printf("\t%s\n",sel_ddr_reg_xsr_tab[i].sel_str);
+		break;
+		case DDR_REG_IDX_XRCKD:
+		case DDR_REG_IDX_CKSRD:
+			for( i = 0; i < SEL_DDR_REG_ESR_TAB_SIZE; i++)
+				printf("\t%s\n",sel_ddr_reg_xrckd_tab[i].sel_str);
+		break;
+		default:
+			printf("print selection table error,idx = %d\n",idx);
+			return -1;
+		}
+		/* input selection :[0,9],[A,F],[a,f] */
+		choice = serial_getc();
+		try_times++;
+		if((choice < '0')
+			||((choice > '9')&&(choice < 'A'))
+			||((choice > 'F')&&(choice < 'a'))
+			||(choice > 'f')) {
+			printf("Your input:%c is invalid,asc is 0x%x\n",choice,choice);
+			if(try_times > 3)
+				break;
+			else
+				continue;
+		}
+		break;
+	}
+	if(try_times > 3) {
+		printf("Invalid input over 3 times ,exit\n");
+		return -1;
+	}
+	printf("debug: choice is 0x%x\n",choice);
+	if((choice >= 'a')&&(choice <= 'f'))
+		choice -= 0x20;
+	if((choice >= 'A') && (choice <= 'F'))
+		choice -=0x37;
+	else
+		choice -=0x30;
+
+	if(choice >= SEL_DDR_REG_ESR_TAB_SIZE) {
+		printf("Input error choice 0x%x, exit\n",choice);
+		return -1;
+	}
+	i = (int)(choice);
+	switch(idx) {
+	case DDR_REG_IDX_ESR:
+		reg_val[idx] = sel_ddr_reg_esr_tab[i].sel_val;
+	break;
+	case DDR_REG_IDX_XSR:
+		reg_val[idx] = sel_ddr_reg_xsr_tab[i].sel_val;
+	break;
+	case DDR_REG_IDX_XRCKD:
+	case DDR_REG_IDX_CKSRD:
+		reg_val[idx] = sel_ddr_reg_xrckd_tab[i].sel_val;
+	break;
+	default:
+		printf("read selection table error,idx = %d\n",idx);
+		return -1;
+	break;
+	}
+	printf("Register offset: 0x%x, value: 0x%x\n",
+		sel_ddr_reg_tab[idx].offset_val,reg_val[idx]);
+	idx++;
+	if(idx < SEL_DDR_REG_NUMBER)
+		goto LAB_INPUT;
+	/* List all selection */
+	printf("\nList your selection:\n");
+	for(i = 0; i < SEL_DDR_REG_NUMBER; i++)
+		printf("\t%s, value: 0x%x\n",sel_ddr_reg_tab[i].name_str, reg_val[i]);
+
+	/* Request writing decision */
+	printf("\nWrite to register ?(y=yes,n=no)\n");
+	choice = serial_getc();
+	if((choice != 'y') && (choice != 'Y')) {
+		printf("Using default value for DDR configuration\n");
+		return 0;
+	}
+	/* write to register */
+	printf("Writing DMC register...\n");
+	for(i = 0; i < SEL_DDR_REG_NUMBER; i++){
+		writel(reg_val[i],DMC_REG_BASE + sel_ddr_reg_tab[i].offset_val);
+		wait_idle = DF_DELAY + 0x10;
+		while (wait_idle--);
+		printf("Address: 0x%x, value: 0x%x\n",
+			sel_ddr_reg_tab[i].offset_val, reg_val[i]);
+	}
+	/* read from register */
+	printf("Reading DMC register...\n");
+	for( i = 0;i < SEL_DDR_REG_NUMBER; i++) {
+		temp = readl(DMC_REG_BASE + sel_ddr_reg_tab[i].offset_val);
+		wait_idle = DF_DELAY + 0x10;
+		while (wait_idle--);
+		printf("Address: 0x%x, value: 0x%x\n",
+			sel_ddr_reg_tab[i].offset_val, temp);
+	}
+	/* Finish configuration */
+	printf("Configure DDR parameter successful !!!.\n");
+	return 0;
+}
+
+#endif /* TGT_AP_SET_DDR_LP_PARAM */
+
+/* This macro is used to test DDR */
+#ifdef TGT_AP_DO_DDR_TEST
+unsigned int g_ddr_manufacture_id = 0;
+unsigned int g_ddr_capacity_id = 0;
+#endif /* TGT_AP_DO_DDR_TEST */
+
+typedef struct
+{
+	unsigned char val;
+	const char *str;
+}dram_info_t;
+
+const static dram_info_t dram_manu[] =
+{
+	{0x01,"Samsung"},
+	{0x03,"Elpida"},
+	{0x05,"Nanya"},
+	{0x06,"Hynix"},
+	{0x08,"Winbond"},
+	{0x0E,"Intel"},
+	{0xFF,"Micron"},
+};
+
+const static char *dram_density[] =
+{
+	"64Mb",
+	"128Mb",
+	"256Mb",
+	"512Mb",
+	"1Gb",
+	"2Gb",
+	"4Gb",
+	"8Gb",
+	"16Gb",
+	"32Gb",
+};
+
+const static char *dram_type[] =
+{
+	"S4 SDRAM",
+	"S2 SDRAM",
+	"N NVM",
+	"Reserved",
+};
+
+const static int dram_io_width[] =
+{
+	32,
+	16,
+	8,
+	0,
+};
+
+unsigned int con_dram_mrdata(unsigned int val)
+{
+	unsigned int t = 0;
+	/* order: 7 6 5 4 3 2 1 0 -> 7 3 1 6 5 4 2 0 */
+	t |= (val & 0x80);
+	t |= (val & 0x40)>>2;
+	t |= (val & 0x20)>>2;
+	t |= (val & 0x10)>>2;
+	t |= (val & 0x08)<<3;
+	t |= (val & 0x04)>>1;
+	t |= (val & 0x02)<<4;
+	t |= (val & 0x01);
+	return t;
+}
+
+void show_dram_info(void)
+{
+	int wait_idle,i,num;
+	unsigned int mr5,mr8,status;
+	unsigned char manu_idx,den_idx,width_idx,type_idx;
+	/* read dmc status */
+	status = readl(DMC_REG_BASE+MEMC_STATUS);
+	if(status != 0) {
+		return;
+	}
+	/* read MR5, manufacture id */
+	writel(0x60000005,DMC_REG_BASE+DIRECT_CMD);
+	wait_idle = DF_DELAY+0xFF;
+	while(wait_idle--);
+	mr5 = readl(DMC_REG_BASE + MR_DATA);
+	/* read MR8, capacity id */
+	writel(0x60000008,DMC_REG_BASE+DIRECT_CMD);
+	wait_idle = DF_DELAY+0xFF;
+	while(wait_idle--);
+	mr8 = readl(DMC_REG_BASE + MR_DATA);
+#ifdef TGT_AP_DO_DDR_TEST
+	g_ddr_manufacture_id = mr5;
+	g_ddr_capacity_id = mr8;
+#endif /* TGT_AP_DO_DDR_TEST */
+	/* to determine wether to transform bit order */
+	width_idx = (mr8 >> 6) & 0x3;
+	den_idx = (mr8 >> 2) & 0xF;
+	if((width_idx >= 0x1) || (den_idx < 0x4)) {
+		mr5 = con_dram_mrdata(mr5);
+		mr8 = con_dram_mrdata(mr8);
+	}
+	/* parse dram info */
+	manu_idx = mr5 & 0xFF;
+	num = ARRAY_SIZE(dram_manu);
+	for(i = 0;i < num;i++) {
+		if(dram_manu[i].val == manu_idx)
+			break;
+	}
+	if(i >= num) {
+		printf("unknown manu id %x\n",mr5);
+		return;
+	}
+	manu_idx = i;
+	type_idx = mr8 & 0x3;
+	den_idx = (mr8 >> 2) & 0xF;
+	width_idx = (mr8 >> 6) & 0x3;
+	num = ARRAY_SIZE(dram_density);
+	if(den_idx >= num) {
+		printf("unknown density %x\n",mr8);
+		return;
+	}
+	printf("dram info: %s, %s, %s, x%d\n",
+		dram_manu[manu_idx].str,
+		dram_type[type_idx],
+		dram_density[den_idx],
+		dram_io_width[width_idx]);
+}
+
+#ifdef DO_DDR_PLL_DEBUG
+extern void cmd_input(char * pname, UINT32 reg_base);
+#endif /* DO_DDR_PLL_DEBUG */
+
+void config_ddr_phy(UINT16 flag)
+{
+	UINT16 __attribute__((unused)) dll_off;
+	dll_off = flag & DDR_FLAGS_DLLOFF;
+
+#if (DDR_TYPE == 2) /* LPDDR2 */
+	int wait_idle, i, num;
+	UINT32 val;
+	u16 metal_id = rda_metal_id_get();
+	dmc_reg_t *dmc_digphy_config_ptr;
+
+	wait_idle = DF_DELAY + 16;
+	while (wait_idle--);
+
+	if (metal_id < 2) {
+		dmc_digphy_config_ptr = (dmc_reg_t *)dmc_digphy_config;
+		num = ARRAY_SIZE(dmc_digphy_config);
+	} else {
+		dmc_digphy_config_ptr = (dmc_reg_t *)dmc_digphy_eco2_config;
+		num = ARRAY_SIZE(dmc_digphy_eco2_config);
+	}
+
+	for (i = 0; i < num; i++) {
+		if (dll_off)
+			val = dmc_digphy_config_ptr[i].dll_off_val;
+		else
+			val = dmc_digphy_config_ptr[i].dll_on_val;
+
+		writel(val, PHY_REG_BASE + dmc_digphy_config_ptr[i].reg_offset);
+		//printf("reg = %x, val = %x \n",PHY_REG_BASE + dmc_digphy_config_ptr[i].reg_offset, val );
+	}
+#else /* DDR3 */
+	writel(0x00,PHY_REG_BASE + DMC_READY *4);
+	writel(0x01,PHY_REG_BASE + RESET_DDR3 *4);
+
+	if (dll_off)
+		writel(0x01,PHY_REG_BASE + WRITE_DATA_LAT *4);
+
+	writel(0x01,PHY_REG_BASE + DDR3_USED *4);
+	writel(0x03,PHY_REG_BASE + WDELAY_SEL *4);
+
+	if (!dll_off){
+		writel(0x07,PHY_REG_BASE + PHY_RDLAT *4);
+		writel(0x02,PHY_REG_BASE + CTRL_DELAY *4);
+		writel(0x02,PHY_REG_BASE + WRITE_ENABLE_LAT *4);
+		writel(0x03,PHY_REG_BASE + WRITE_DATA_LAT *4);
+		writel(0x03,PHY_REG_BASE + DQOUT_ENABLE_LAT *4);
+	}else
+		writel(0x01,PHY_REG_BASE + DQOUT_ENABLE_LAT *4);
+
+	writel(0x0e,PHY_REG_BASE + DATA_ODT_ENABLE_REG *4);
+	writel(0x0f,PHY_REG_BASE + DATA_WRITE_ENABLE_REG *4);
+
+#endif
+	printf("ddr %d phy init done!\n",(int)DDR_TYPE);
+}
+
+void config_dmc400(UINT16 flag, UINT32 para)
+{
+	int i, wait_idle;
+	UINT32 val, tmp;
+	UINT16 __attribute__((unused)) dll_off, lpw;
+	UINT32 mem_width, col_bits, row_bits, bank_bits;
+#if (DDR_TYPE == 3)
+	UINT16 odt,ron;
+
+	odt = (flag & DDR_FLAGS_ODT_MASK) >> DDR_FLAGS_ODT_SHIFT;
+	ron = (flag & DDR_FLAGS_RON_MASK) >> DDR_FLAGS_RON_SHIFT;
+#endif
+	// parse parameter
+	dll_off = flag & DDR_FLAGS_DLLOFF;
+	lpw = flag & DDR_FLAGS_LOWPWR;
+	mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;
+	bank_bits = (para & DDR_PARA_BANK_BITS_MASK) >> DDR_PARA_BANK_BITS_SHIFT;
+	row_bits = (para & DDR_PARA_ROW_BITS_MASK) >> DDR_PARA_ROW_BITS_SHIFT;
+	col_bits = (para & DDR_PARA_COL_BITS_MASK) >> DDR_PARA_COL_BITS_SHIFT;
+
+	wait_idle = 0x4e;
+	while (wait_idle--);
+	//config MEMC CMD
+	writel(0x0, DMC_REG_BASE + MEMC_CMD);
+
+	//READ MEMC STATUS
+	val = 0;
+	do {
+		val = readl(DMC_REG_BASE + MEMC_STATUS);
+		//printf("MEMC_STATUS value: %x\n", val);
+	} while (val != 0);
+
+	for (i = 0; i < ARRAY_SIZE(dmc_reg_cfg); i++) {
+		if (dll_off)
+			val = dmc_reg_cfg[i].dll_off_val;
+		else
+			val = dmc_reg_cfg[i].dll_on_val;
+
+		writel(val, DMC_REG_BASE + dmc_reg_cfg[i].reg_offset);
+		wait_idle = 0x5;
+		while (wait_idle--);
+		/*printf("dmc reg 0x%x = 0x%x\n",
+			(unsigned int)(dmc_reg_cfg[i].reg_offset),(unsigned int)val);*/
+	}
+	//config low power control register
+	if (lpw) {
+		printf("enter low power mode \n");
+		for (i = 0; i < ARRAY_SIZE(dmc_reg_low_power_cfg); i++) {
+			writel(dmc_reg_low_power_cfg[i].dll_off_val,
+				DMC_REG_BASE + dmc_reg_low_power_cfg[i].reg_offset);
+			wait_idle = 0x5;
+			while (wait_idle--);
+		}
+	}
+#ifdef DO_DDR_PLL_DEBUG
+	cmd_input("Dmc400",DMC_REG_BASE);
+#endif
+	//config format control register
+	val = readl(DMC_REG_BASE + FORMAT_CTRL);
+	val &= ~0xf;
+	if (mem_width == 2)
+		val |= 0x2; //for 32bit DDR
+	else if ((mem_width == 1) || (mem_width == 0))
+		val |= 0x1; //for 16bit & 8bit DDR
+	else
+		printf("unsupported DDR width: %lx\n", mem_width);
+	writel(val, DMC_REG_BASE + FORMAT_CTRL);
+
+	printf("format ctrl value: %lx\n", val);
+
+	wait_idle = 0x1d;
+	while (wait_idle--);
+
+	//config address control register
+	if (mem_width == 2)
+		tmp = col_bits; //for 32bit
+	else if (mem_width == 1)
+		tmp = col_bits - 1; //for 16bit
+	else if (mem_width == 0)
+		tmp = col_bits - 2; //for 8bit
+	else {
+		printf("unsupported DDR width: %lx\n", mem_width);
+		tmp = col_bits;
+	}
+	val = (bank_bits << 16) | (row_bits << 8) | tmp;
+	writel(val, DMC_REG_BASE + ADDR_CTRL);
+
+	printf("address ctrl value: %lx\n", val);
+
+	wait_idle = 0x5;
+	while (wait_idle--);
+
+	//config decode control register
+	tmp = 12 - (8 + col_bits + mem_width);
+	if (tmp < 8)
+		val = tmp << 4;
+	else
+		printf("unsupported stripe decode: %lx\n", tmp);
+	writel(val, DMC_REG_BASE + DECODE_CTRL);
+
+	printf("decode ctrl value: %lx\n", val);
+
+	wait_idle = 0x6;
+	while (wait_idle--);
+#if (DDR_TYPE == 2)
+	//config direct command
+	for (i = 0; i < ARRAY_SIZE(ddr_config); i++) {
+		mdelay(1);
+		wait_idle = DF_DELAY + 0x10;
+		while (wait_idle--);
+		writel(ddr_config[i].dll_off_val, DMC_REG_BASE + ddr_config[i].reg_offset);
+/*		printf("reg 0x%x = 0x%x\n",
+			(unsigned int)(ddr_config[i].reg_offset),
+			(unsigned int)(ddr_config[i].dll_off_val));*/
+	}
+#else
+	//direct cmd ddr3
+	for (i = 0; i < ARRAY_SIZE(ddr_config); i++) {
+		mdelay(1);
+		wait_idle = DF_DELAY + 0x10;
+		while (wait_idle--);
+		if(i == 3) {
+			//config MR1 ODT [9,6,2] RON [5,1] DLLOFF [0]
+			val = 0x10010000;
+			val |= (odt & 0x4)<<7 | (odt & 0x2)<<5 | (odt & 0x1)<<2;
+			val |= (ron & 0x2)<<4 | (ron & 0x1)<<1;
+			if (dll_off)
+				val |= 0x1;
+			writel(val, DMC_REG_BASE + ddr_config[i].reg_offset);
+		/*	printf("MR1 is %x\n", (unsigned int)val);*/
+		} else {
+			writel(ddr_config[i].dll_off_val, DMC_REG_BASE + ddr_config[i].reg_offset);
+		/*	printf("reg 0x%x = 0x%x\n",
+				(unsigned int)(ddr_config[i].reg_offset),
+				(unsigned int)(ddr_config[i].dll_off_val));*/
+		}
+	}
+#endif
+#if (DDR_TYPE == 2)
+	show_dram_info();
+#ifdef TGT_AP_SET_DDR_LP_PARAM
+	_ddr_config_low_power_mode();
+	_ddr_set_refresh_timing();
+#endif
+#endif
+	//config MEMC CMD to READY state
+	writel(0x3, DMC_REG_BASE + MEMC_CMD);
+
+	//READ MEMC STATUS
+	val = 0;
+	do {
+		val = readl(DMC_REG_BASE + MEMC_STATUS);
+		//printf("MEMC_STATUS value: %x\n", val);
+	} while (val != 3);
+}
+
+void axi_prio_init(void)
+{
+	writel(0xaa0000aa, 0x20900100);
+	writel(0x00000008, 0x21054100);
+	writel(0x00000008, 0x21054104);
+}
+
+void axi_outstandings_init(void)
+{
+	writel(0x00000060, 0x2104210c);
+	writel(0x00000300, 0x21042110);
+}
+
+int ddr_init(UINT16 flags, UINT32 para)
+{
+	UINT16 dll_off;
+	UINT32 mem_width;
+
+	//axi_prio_init();
+	axi_outstandings_init();
+
+	dll_off = flags & DDR_FLAGS_DLLOFF;
+	mem_width = (para & DDR_PARA_MEM_BITS_MASK) >> DDR_PARA_MEM_BITS_SHIFT;
+
+	switch (mem_width) {
+	case 0:
+		printf("8bit ");
+		break;
+	case 1:
+		printf("16bit ");
+		break;
+	case 2:
+		printf("32bit ");
+		break;
+	}
+	if (dll_off)
+		printf("dll-off Mode ...\n");
+	else
+		printf("dll-on Mode ...\n");
+
+	config_ddr_phy(flags);
+#ifdef DO_DDR_PLL_DEBUG
+	cmd_input("DigPhy", PHY_REG_BASE);
+#endif
+	config_dmc400(flags, para);
+	printf("dram init done ...\n");
+
+	return 0;
+}
diff --git a/board/rda/rda8850e/ddr.h b/board/rda/rda8850e/ddr.h
new file mode 100644
index 0000000000..7481954144
--- /dev/null
+++ b/board/rda/rda8850e/ddr.h
@@ -0,0 +1,50 @@
+#ifndef _SYS_DDR3_H_
+#define _SYS_DDR3_H_
+
+#include "clock_config.h"
+
+/*
+ * defination of ddr flags
+ */
+/* [Debug] DLL off mode, 0 is dll on mode */
+#define DDR_FLAGS_DLLOFF               0x8000
+/* [Debug] LowSpeed mode*/
+#define DDR_FLAGS_RESERVE              0x4000
+/* DDR LowPower mode */
+#define DDR_FLAGS_LOWPWR               0x2000
+/* ODT: 000--Null 001--60 010--120 011--40 100--20 101--30 */
+#define DDR_FLAGS_ODT(n)               (((n)<<0)&0x0007)
+#define DDR_FLAGS_ODT_SHIFT            0
+#define DDR_FLAGS_ODT_MASK             0x0007
+/* RON: 00--40 01--30 */
+#define DDR_FLAGS_RON(n)               (((n)<<3)&0x0018)
+#define DDR_FLAGS_RON_SHIFT            3
+#define DDR_FLAGS_RON_MASK             0x0018
+
+/*
+ * defination of ddr parameters
+ */
+#define DDR_PARA_CHIP_BITS(n)          (((n)<<0)&0x00000003)
+#define DDR_PARA_CHIP_BITS_SHIFT       0
+#define DDR_PARA_CHIP_BITS_MASK        0x00000003
+/* memory width 0--8bit 1--16bit 2--32bit */
+#define DDR_PARA_MEM_BITS(n)           (((n)<<2)&0x0000000c)
+#define DDR_PARA_MEM_BITS_SHIFT        2
+#define DDR_PARA_MEM_BITS_MASK         0x0000000c
+/* 2--4banks 3--8banks */
+#define DDR_PARA_BANK_BITS(n)          (((n)<<4)&0x000000f0)
+#define DDR_PARA_BANK_BITS_SHIFT       4
+#define DDR_PARA_BANK_BITS_MASK        0x000000f0
+/* 2--13rbs 3--14rbs 4--15rbs 5--16rbs */
+#define DDR_PARA_ROW_BITS(n)           (((n)<<8)&0x00000f00)
+#define DDR_PARA_ROW_BITS_SHIFT        8
+#define DDR_PARA_ROW_BITS_MASK         0x00000f00
+/* 0--8cbs 1--9cbs 2--10cbs 3--11cbs 4--12cbs */
+#define DDR_PARA_COL_BITS(n)           (((n)<<12)&0x0000f000)
+#define DDR_PARA_COL_BITS_SHIFT        12
+#define DDR_PARA_COL_BITS_MASK         0x0000f000
+
+int ddr_init(UINT16 flags, UINT32 para);
+
+#endif /* _SYS_DDR3_H_ */
+
diff --git a/board/rda/rda8850e/ddr3_init.h b/board/rda/rda8850e/ddr3_init.h
new file mode 100644
index 0000000000..58b5f04aba
--- /dev/null
+++ b/board/rda/rda8850e/ddr3_init.h
@@ -0,0 +1,127 @@
+#ifndef _SYS_DDR_INIT_H_
+#define _SYS_DDR_INIT_H_
+
+#include <common.h>
+#include "ddr.h"
+#include "ddr_init.h"
+
+#define  PHY_RDLAT          0
+#define  PHYWRDATA          1
+#define  STA                3
+#define  CLKSEL             4
+#define  PSSTART            5
+#define  PSDONE             6
+#define  LOCKED             6
+#define  CTRL_DELAY         7
+#define  RDELAY_SEL         8
+#define  WDELAY_SEL         9
+#define  PHY_RESET          10
+#define  RESET_DDR3         11
+#define  ODT_DELAY          12
+#define  DDR3_USED          13
+#define  WRITE_ENABLE_LAT   14
+#define  WRITE_DATA_LAT     15
+#define  DQOUT_ENABLE_LAT   16
+#define  DATA_ODT_ENABLE_REG	20
+#define  DATA_WRITE_ENABLE_REG  48
+#define  DMC_READY	128
+#define  USE_ADDR	129
+
+const dmc_reg_t dmc_reg_cfg[] = {
+		{QOSX_CTRL7,	0x08,		0x08},
+		{TURNAROUND_PRIO,0x1A,		0x0},
+		{HIT_PRIO,	0x1A,		0x0},
+		{T_REFI,	0x186,		0x3f},
+		{QUEUE_CTRL,	0xffff, 	0x0},
+		{T_RFC, 	0x23008c,	0x23008c},
+		{T_RFC, 	0x8c008c,	0x8c008c},
+		{T_MRR, 	0x4,		0x4},
+		{T_MRW, 	0xc,		0xc},
+		{T_RCD, 	0x6,		0x6},
+		{T_RAS, 	0xf,		0xf},
+		{T_RP,		0x6,		0x6},
+		{T_RPALL,	0x6,		0x5},
+		{T_RRD, 	0x4,		0x4},
+		{T_FAW, 	0x14,		0x14},
+		{T_RTR, 	0x6,		0x6},
+	//	{T_RTW, 	0x7,		0x6},
+		{T_RTW, 	0x0c,		0x6},// turn for now
+		{T_RTW, 	0x1f,		0x1f},//for low speed
+		{T_RTP, 	0x4,		0x4},
+		{T_WR,		0xf,		0x10},
+		{T_WTR, 	0x4000d,	0x4000d},
+		{T_WTR, 	0x6000d,	0x6000f},
+	//	{T_WTR, 	0x6001f,	0x6001f},//for low speed
+		{T_WTW, 	0x60000,	0x60000},
+		{RD_LATENCY,	0x5,		0x5},
+		{WR_LATENCY,	0x5,		0x5},
+		{T_RDDATA_EN,	0x8,		0x3},
+		{T_PHYWRLAT,	0x102,		0x102},
+		{T_PHYWRLAT,	0x102,		0x103},
+		{T_EP,		0x3,		0x3},
+		{T_XP,		0x20003,	0x20003},
+		{T_XP,		0xa0003,	0xa0003},
+		{T_ESR, 	0x4,		0x4},
+		{T_XSR, 	0x1000090,	0x1000090},
+		{T_XSR, 	0x2000090,	0x2000090},
+		{T_SRCKD,	0x5,		0x5},
+		{T_CKSRD,	0x5,		0x5},
+		{T_ECKD,	0x5,		0x5},
+		{T_XCKD,	0x5,		0x5},
+		{ECC_CTRL,	0x0,		0x0},
+		{ADDR_CTRL, 0x30200,	0x30200},
+		{ADDR_CTRL, 0x30200,	0x30200},
+		{ADDR_CTRL, 0x30200,	0x30200},
+
+};
+
+const dmc_reg_t dmc_reg_low_power_cfg[] = {
+	{LOWPWR_CTRL,	0x48,	0x48},
+	{T_ESR,		0xa,	0xa},
+	{T_XSR,		0x200,	0x200},
+	{T_SRCKD,	0xa,	0xa},
+	{T_CKSRD,	0xa,	0xa},
+};
+
+const dmc_reg_t ddr_config[] = {
+	{DIRECT_CMD,	0x0,		0x0},
+	{DIRECT_CMD,	0x10020000,	0x10020008},
+	{DIRECT_CMD,	0x10030000,	0x10030000},
+	{DIRECT_CMD,	0x10010004,	0x10010005},
+	{DIRECT_CMD,	0x10000520,	0x10000520},
+	{DIRECT_CMD,	0x50000400,	0x50000400},
+	{DIRECT_CMD,	0x30000000,	0x30000000},
+};
+
+const dmc_reg_t dmc_digphy_config[] = {
+	{DMC_READY*4,			0x0,	0x0},
+	{RESET_DDR3*4,			0x1,	0x1},
+	{WRITE_DATA_LAT*4,		0x3,	0x1},
+	{DDR3_USED*4,			0x1,	0x1},
+	{WDELAY_SEL*4,			0x3,	0x3},
+//	{RDELAY_SEL*4,			0x1,	0x1},
+	{PHY_RDLAT*4,			0x7,	0x7},
+	{CTRL_DELAY*4,			0x2,	0x2},
+	{WRITE_ENABLE_LAT*4,		0x2,	0x2},
+	{DQOUT_ENABLE_LAT*4,		0x3,	0x1},
+	{DATA_WRITE_ENABLE_REG*4,	0xf,	0xf},
+	{DATA_ODT_ENABLE_REG*4,		0xe,	0xe},
+
+};
+
+const dmc_reg_t dmc_digphy_eco2_config[] = {
+	{DMC_READY*4,			0x0,	0x0},
+	{RESET_DDR3*4,			0x1,	0x1},
+	{WRITE_DATA_LAT*4,		0x3,	0x1},
+	{DDR3_USED*4,			0x1,	0x1},
+	{WDELAY_SEL*4,			0x3,	0x3},
+//	{RDELAY_SEL*4,			0x1,	0x1},
+	{PHY_RDLAT*4,			0x7,	0x7},
+	{CTRL_DELAY*4,			0x2,	0x2},
+	{WRITE_ENABLE_LAT*4,		0x2,	0x2},
+	{DQOUT_ENABLE_LAT*4,		0x3,	0x1},
+	{DATA_WRITE_ENABLE_REG*4,	0xf,	0xf},
+	{DATA_ODT_ENABLE_REG*4,		0xe,	0xe},
+
+};
+#endif
diff --git a/board/rda/rda8850e/ddr_init.h b/board/rda/rda8850e/ddr_init.h
new file mode 100644
index 0000000000..1d3f4d130f
--- /dev/null
+++ b/board/rda/rda8850e/ddr_init.h
@@ -0,0 +1,114 @@
+#ifndef _SYS_RAM_INIT_H_
+#define _SYS_RAM_INIT_H_
+
+#define MEMC_STATUS			0x000
+#define MEMC_CONFIG			0x004
+#define MEMC_CMD			0x008
+#define ADDR_CTRL			0x010
+#define DECODE_CTRL			0x014
+#define FORMAT_CTRL			0x018
+#define LOWPWR_CTRL			0x020
+#define TURNAROUND_PRIO			0x030
+#define HIT_PRIO			0x034
+//QOS0~QOS15:038~078
+#define QOSX_CTRL0			0x038
+#define QOSX_CTRL1			0x03C
+#define QOSX_CTRL2			0x040
+#define QOSX_CTRL3			0x044
+#define QOSX_CTRL4			0x048
+#define QOSX_CTRL5			0x04C
+#define QOSX_CTRL6			0x050
+#define QOSX_CTRL7			0x054
+#define QOSX_CTRL8			0x058
+#define QOSX_CTRL9			0x05C
+#define QOSX_CTRL10			0x060
+#define QOSX_CTRL11			0x064
+#define QOSX_CTRL12			0x068
+#define QOSX_CTRL13			0x070
+#define QOSX_CTRL14			0x074
+#define QOSX_CTRL15			0x078
+#define TIMEOUT_CTRL			0x07C
+#define QUEUE_CTRL			0x080
+#define WR_PRIO_CTRL			0x088
+#define WR_PRIO_CTRL2			0x08C
+#define RD_PRIO_CTRL			0x090
+#define RD_PRIO_CTRL2			0x094
+#define ACCESS_ADDR_MATCH		0x098
+#define ACCESS_ADDR_MATCH_63_32		0x09C
+#define ACCESS_ADDR_MASK		0x0A0
+#define ACCESS_ADDR_MASK_63_32		0x0A4
+
+#define CHANNEL_STATUS			0x100
+#define DIRECT_CMD			0x108
+#define MR_DATA				0x110
+#define REFRESH_CTRL			0x120
+#define INTR_CTRL			0x128
+#define INTR_CLR			0x130
+#define INTR_STATUS			0x138
+#define INTR_INFO			0x140
+#define ECC_CTRL			0x148
+
+#define T_REFI				0x200
+#define T_RFC				0x204
+#define T_MRR				0x208
+#define T_MRW				0x20C
+#define T_RCD				0x218
+#define T_RAS				0x21C
+#define T_RP				0x220
+#define T_RPALL				0x224
+#define T_RRD				0x228
+#define T_FAW				0x22C
+#define RD_LATENCY			0x230
+#define T_RTR				0x234
+#define T_RTW				0x238
+#define T_RTP				0x23C
+#define WR_LATENCY			0x240
+#define T_WR				0x244
+#define T_WTR				0x248
+#define T_WTW				0x24C
+#define T_ECKD				0x250
+#define T_XCKD				0x254
+#define T_EP				0x258
+#define T_XP				0x25C
+#define T_ESR				0x260
+#define T_XSR				0x264
+#define T_SRCKD				0x268
+#define T_CKSRD				0x26C
+
+#define T_RDDATA_EN			0x300
+#define T_PHYWRLAT			0x304
+#define RDLVL_CTRL			0x308
+#define RDLVL_DIRECT			0x310
+#define T_RDLVL_EN			0x318
+#define T_RDLVL_RR			0x31C
+#define WRLVL_CTRL			0x328
+#define WRLVL_DIRECT			0x330
+#define T_WRLVL_EN			0x338
+#define T_WRLVL_WW			0x33C
+
+#define PHY_PWR_CTRL			0x348
+#define PHY_UPD_CTRL			0x350
+
+#define USER_STATUS			0x400
+#define USER_CONFIG0			0x404
+#define USER_CONFIG1			0x408
+
+#define INTEG_CFG			0xE00
+#define INTEG_OUTPUTS			0xE08
+
+#define PERIPH_ID_0			0xFE0
+#define PERIPH_ID_1			0xFE4
+#define PERIPH_ID_2			0xFE8
+#define PERIPH_ID_3			0xFEC
+#define COMPONENT_ID_0			0xFF0
+#define COMPONENT_ID_1			0xFF4
+#define COMPONENT_ID_2			0xFF8
+#define COMPONENT_ID_3			0xFFC
+
+typedef struct {
+	UINT32 reg_offset;
+	UINT32 dll_on_val;
+	UINT32 dll_off_val;
+} dmc_reg_t;
+
+#endif /* _SYS_RAM_INIT_H_ */
diff --git a/board/rda/rda8850e/debug.h b/board/rda/rda8850e/debug.h
new file mode 100644
index 0000000000..1d4f03bedb
--- /dev/null
+++ b/board/rda/rda8850e/debug.h
@@ -0,0 +1,9 @@
+#ifndef _DEBUG_H_
+#define _DEBUG_H_
+
+void print_u8(u8 ch);
+void print_u16(u16 data);
+void print_u32(u32 data);
+void dump_buf(u8 *buf, u32 size);
+
+#endif /* _DEBUG_H_ */
diff --git a/board/rda/rda8850e/hal_config.c b/board/rda/rda8850e/hal_config.c
new file mode 100644
index 0000000000..1364297b8b
--- /dev/null
+++ b/board/rda/rda8850e/hal_config.c
@@ -0,0 +1,1166 @@
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//            Copyright (C) 2013, RDA Microeletronics.                        //
+//                            All Rights Reserved                             //
+//                                                                            //
+//      This source code is the property of RDA Microeletronics and is        //
+//      confidential.  Any  modification, distribution,  reproduction or      //
+//      exploitation  of  any content of this file is totally forbidden,      //
+//      except  with the  written permission  of  RDA Microeletronics.        //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//  $HeadURL: http://svn.rdamicro.com/svn/developing1/Sources/chip/branches/8810/hal/8810/src/hal_config.c $ //
+//    $Author: huazeng $                                                        //
+//    $Date: 2013-08-31 17:48:58 +0800 (Sat, 31 Aug 2013) $                     //
+//    $Revision: 21005 $                                                          //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+/// @file hal_config.c
+/// Implementation of HAL initialization related with the particular instance
+/// of the IP.
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+
+/* uboot */
+#include <common.h>
+
+/* common */
+#include <asm/arch/rda_iomap.h>
+#include <asm/arch/hwcfg.h>
+#include <asm/arch/chip_id.h>
+#include <asm/arch/cs_types.h>
+#include <asm/arch/global_macros.h>
+#include <asm/arch/reg_gpio.h>
+
+/* device */
+#include "hal_sys.h"
+#include "halp_sys.h"
+#include "halp_gpio.h"
+#include "bootp_mode.h"
+#include "hal_config.h"
+#include "hal_ap_gpio.h"
+#include "hal_ap_config.h"
+#include <asm/arch/reg_cfg_regs.h>
+
+/* target */
+#include "tgt_board_cfg.h"
+#include "tgt_ap_gpio_setting.h"
+#define HAL_ASSERT(cond, fmt, ...) \
+	if(!(cond)) { \
+		hal_assert(fmt, ##__VA_ARGS__); \
+		g_halConfigError = TRUE; \
+	}
+
+//// =============================================================================
+////  GLOBAL VARIABLES
+//// =============================================================================
+PRIVATE CONST UINT8 g_halCfgSimOrder[] = { TGT_SIM_ORDER };
+PRIVATE HAL_CFG_CONFIG_T hal_cfg = TGT_HAL_CONFIG;
+PRIVATE UINT32 g_bootBootMode = 0;
+PRIVATE BOOL g_halConfigError = FALSE;
+
+
+// =============================================================================
+//  FUNCTIONS
+// =============================================================================
+// HAL_ASSERT
+PRIVATE VOID hal_assert(const char *fmt, ...)
+{
+	va_list args;
+	puts("\n#-------Board Mux config found error-------#\n");
+	va_start(args, fmt);
+	vprintf(fmt, args);
+	putc('\n');
+	puts("--------------------------------------------\n\n");
+	va_end(args);
+}
+
+// =============================================================================
+// hal_BoardSimUsed
+// -----------------------------------------------------------------------------
+/// Check whether a SIM card interface is used.
+// ============================================================================
+PRIVATE BOOL hal_BoardSimUsed(UINT32 simId)
+{
+	UINT32 i = 0;
+    //for (UINT32 i=0; i<ARRAY_SIZE(g_halCfgSimOrder) && i<NUMBER_OF_SIM; i++)
+    for (i=0; i<ARRAY_SIZE(g_halCfgSimOrder) && i<NUMBER_OF_SIM; i++)
+    {
+        if (g_halCfgSimOrder[i] == simId)
+        {
+            return TRUE;
+        }
+    }
+
+    return FALSE;
+}
+
+#if 0
+// =============================================================================
+// hal_BoardConfigClk32k
+// -----------------------------------------------------------------------------
+/// Configure CLK_32K output.
+/// @param enable TRUE to configure, and FALSE to disable.
+// ============================================================================
+PROTECTED VOID hal_BoardConfigClk32k(BOOL enable)
+{
+    HAL_ASSERT(g_halCfg->useClk32k == TRUE, "32K clock is not configured");
+
+    if (enable)
+    {
+        // Setup the pin as 32K clock output
+        hwp_configRegs->Alt_mux_select =
+            (hwp_configRegs->Alt_mux_select & ~CFG_REGS_GPO_2_MASK) |
+            CFG_REGS_GPO_2_CLK_32K;
+    }
+    else
+    {
+        // Setup the pin as GPO (and low ouput has been
+        // configured in hal_BoardSetup())
+        hwp_configRegs->Alt_mux_select =
+            (hwp_configRegs->Alt_mux_select & ~CFG_REGS_GPO_2_MASK) |
+            CFG_REGS_GPO_2_GPO_2;
+    }
+}
+#endif
+
+// =============================================================================
+// hal_BoardSetupGeneral
+// -----------------------------------------------------------------------------
+/// Apply board dependent configuration to HAL for general purpose
+/// @param halCfg Pointer to HAL configuration structure (from the target
+/// module).
+// ============================================================================
+PROTECTED VOID hal_BoardSetupGeneral(CONST HAL_CFG_CONFIG_T* halCfg)
+{
+    UINT32 altMux = 0;
+
+    UINT32 availableGpo_A = 0;
+
+    UINT32 availableGpio_C = 0;
+    UINT32 availableGpio_A = 0;
+    UINT32 availableGpio_B = 0;
+    UINT32 availableGpio_D = 0;
+
+    UINT32 bootModeGpio_C = 0;
+    UINT32 bootModeGpio_A = 0;
+    UINT32 bootModeGpio_B = 0;
+    UINT32 bootModeGpio_D = 0;
+
+    UINT32 noConnectMask_C = 0;
+    UINT32 noConnectMask_A = 0;
+    UINT32 noConnectMask_B = 0;
+    UINT32 noConnectMask_D = 0;
+
+#ifdef CONFIG_RDA_FPGA
+    // add support for sd card
+    hwp_configRegs->BB_GPIO_Mode &= ~(0x3F<<9);
+#else // !FPGA
+
+    // GPIOs as boot mode pins
+    bootModeGpio_C = HAL_GPIO_BIT(1)
+                   | HAL_GPIO_BIT(2)
+                   | HAL_GPIO_BIT(3)
+                   | HAL_GPIO_BIT(4)
+                   | HAL_GPIO_BIT(5);
+    bootModeGpio_A = HAL_GPIO_BIT(4)
+                   | HAL_GPIO_BIT(5)
+                   | HAL_GPIO_BIT(6)
+                   | HAL_GPIO_BIT(7);
+    bootModeGpio_B = HAL_GPIO_BIT(0);
+    bootModeGpio_D = 0;
+
+    // Available GPIOs
+    availableGpio_C |= HAL_GPIO_BIT(0)
+                     | HAL_GPIO_BIT(1)
+                     | HAL_GPIO_BIT(2)
+                     | HAL_GPIO_BIT(3)
+                     | HAL_GPIO_BIT(4)
+                     | HAL_GPIO_BIT(5);
+    // Volume down/up keys
+    availableGpio_D |= HAL_GPIO_BIT(5)
+                     | HAL_GPIO_BIT(6);
+
+    // Boot modes
+    BOOL spiFlashCam = FALSE;
+    BOOL spiFlashNand = FALSE;
+    if (g_bootBootMode & BOOT_MODE_BOOT_SPI)
+    {
+        if (g_bootBootMode & BOOT_MODE_SPI_PIN_NAND)
+        {
+            HAL_ASSERT((g_bootBootMode & BOOT_MODE_BOOT_EMMC),
+                "Emmc boot pin should be pulled up to boot on SPI flash over NAND pins");
+            spiFlashNand = TRUE;
+        }
+        else
+        {
+            spiFlashCam = TRUE;
+        }
+    }
+
+    if ((g_bootBootMode & (BOOT_MODE_BOOT_EMMC|BOOT_MODE_BOOT_SPI|BOOT_MODE_BOOT_SPI_NAND))
+        == BOOT_MODE_BOOT_EMMC)
+    {
+        // Boot from EMMC
+        HAL_ASSERT(halCfg->sdmmcCfg.sdmmc3Used, "SDMMC3 should be used");
+    }
+
+    if ( (g_bootBootMode & (BOOT_MODE_BOOT_SPI|BOOT_MODE_BOOT_SPI_NAND))
+         == BOOT_MODE_BOOT_SPI_NAND ||
+         (g_bootBootMode & (BOOT_MODE_BOOT_SPI|BOOT_MODE_NAND_PAGE_SIZE_L))
+         == (BOOT_MODE_BOOT_SPI|BOOT_MODE_NAND_PAGE_SIZE_L)
+       )
+    {
+        // Boot from SDMMC1
+        HAL_ASSERT(halCfg->sdmmcCfg.sdmmcUsed, "SDMMC1 should be used");
+    }
+
+    // For convenience, we do not consider spiFlashCam at present.
+    // We assume that SPI flash always uses parallel nand pins.
+#if 0
+    BOOL parallelNandUsed = halCfg->parallelNandUsed;
+#else
+    BOOL parallelNandUsed = !spiFlashNand && !halCfg->sdmmcCfg.sdmmc3Used;
+#endif
+    BOOL nand8_15Cam = FALSE;
+    BOOL nand8_15Lcd = FALSE;
+    if ((g_bootBootMode & BOOT_MODE_BOOT_EMMC) == 0)
+    {
+        // If BOOT_MODE_BOOT_EMMC is not set, the parallel NAND pins
+        // are multiplexed to parallel NAND controller
+        HAL_ASSERT(parallelNandUsed, "Parallel NAND should be used");
+        if ((g_bootBootMode & BOOT_MODE_NAND_8BIT) == 0)
+        {
+            if (g_bootBootMode & BOOT_MODE_NAND_HIGH_PIN_CAM)
+            {
+                nand8_15Cam = TRUE;
+            }
+            else
+            {
+                nand8_15Lcd = TRUE;
+            }
+        }
+    }
+
+    HAL_ASSERT(!(parallelNandUsed && spiFlashNand), "SPI flash uses parallel NAND pins");
+    HAL_ASSERT(!(nand8_15Cam && spiFlashCam), "NAND 8-15 bits and SPI flash both use cam pins");
+
+    if (!(parallelNandUsed || spiFlashNand))
+    {
+        availableGpio_B |= HAL_GPIO_BIT(25)
+                         | HAL_GPIO_BIT(26)
+                         | HAL_GPIO_BIT(27)
+                         | HAL_GPIO_BIT(28)
+                         | HAL_GPIO_BIT(29);
+        availableGpio_D |= HAL_GPIO_BIT(4);
+    }
+
+    const HAL_CFG_CAM_T *camCfg = &halCfg->camCfg;
+    const HAL_LCD_MODE_T lcdMode = halCfg->goudaCfg.lcdMode;
+
+    // LCD
+    if (lcdMode == HAL_LCD_MODE_PARALLEL_16BIT)
+    {
+        HAL_ASSERT(!nand8_15Lcd, "NAND uses LCD 8-15 bits");
+        altMux |= CFG_REGS_LCD_MODE_PARALLEL_16BIT;
+    }
+    else if (lcdMode == HAL_LCD_MODE_DSI)
+    {
+        altMux |= CFG_REGS_LCD_MODE_DSI;
+        availableGpio_A |= HAL_GPIO_BIT(22)
+                         | HAL_GPIO_BIT(23);
+    }
+    else if (lcdMode == HAL_LCD_MODE_RGB_16BIT)
+    {
+        HAL_ASSERT(!nand8_15Lcd, "NAND uses LCD 8-15 bits");
+        altMux |= CFG_REGS_LCD_MODE_RGB_16BIT;
+    }
+    else if (lcdMode == HAL_LCD_MODE_RGB_24BIT)
+    {
+        HAL_ASSERT(!nand8_15Lcd, "NAND uses LCD 8-15 bits");
+        if (halCfg->goudaCfg.lcd16_23Cam)
+        {
+            HAL_ASSERT(
+                !(camCfg->camMode == HAL_CAM_MODE_PARALLEL &&
+                  (camCfg->camUsed || camCfg->cam1Used)),
+                "Parallel camera uses LCD 16-23 bits");
+            HAL_ASSERT(
+                !(halCfg->i2cCfg.i2c2Used && halCfg->i2cCfg.i2c2PinsCam),
+                "I2C2 uses LCD 22-23 bits");
+            HAL_ASSERT(!spiFlashCam, "SPI flash uses LCD 16-21 bits");
+            HAL_ASSERT(!nand8_15Cam, "NAND uses LCD 16-23 bits");
+            HAL_ASSERT(
+                !(camCfg->camMode == HAL_CAM_MODE_CSI &&
+                  ((camCfg->camUsed && camCfg->camCsiId == HAL_CAM_CSI_1) ||
+                   (camCfg->cam1Used && camCfg->cam1CsiId == HAL_CAM_CSI_1))),
+                "Camera CSI1 uses LCD 16-21 bits");
+            //altMux |= CFG_REGS_LCD24_CAM_CAM_IO;
+        }
+        else
+        {
+            HAL_ASSERT(!parallelNandUsed, "NAND uses LCD 16-23 bits");
+            HAL_ASSERT(!halCfg->sdmmcCfg.sdmmc3Used, "SDMMC3 uses LCD 16-23 bits");
+            //altMux |= CFG_REGS_LCD24_CAM_NAND_IO;
+        }
+        altMux |= CFG_REGS_LCD_MODE_RGB_24BIT;
+    }
+    else if (lcdMode == HAL_LCD_MODE_SPI)
+    {
+        HAL_ASSERT(!(halCfg->goudaCfg.cs0Used || halCfg->goudaCfg.cs1Used),
+            "LCD CS 0/1 use SPI LCD pins");
+        HAL_ASSERT((halCfg->usedGpo_A & 0x18) == 0, "GPO 3/4 use SPI LCD pins");
+        altMux |= CFG_REGS_SPI_LCD_SPI_LCD;
+        availableGpio_A |= HAL_GPIO_BIT(18)
+                         | HAL_GPIO_BIT(19)
+                         | HAL_GPIO_BIT(20)
+                         | HAL_GPIO_BIT(21);
+    }
+    else
+    {
+        HAL_ASSERT(FALSE, "Lcd mode not defined!");
+    }
+
+    if (lcdMode == HAL_LCD_MODE_DSI || lcdMode == HAL_LCD_MODE_SPI)
+    {
+        if (nand8_15Lcd)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(24)
+                             | HAL_GPIO_BIT(25)
+                             | HAL_GPIO_BIT(26)
+                             | HAL_GPIO_BIT(27)
+                             | HAL_GPIO_BIT(28)
+                             | HAL_GPIO_BIT(29)
+                             | HAL_GPIO_BIT(30)
+                             | HAL_GPIO_BIT(31);
+        }
+    }
+
+    if (halCfg->goudaCfg.cs0Used)
+    {
+        altMux |= CFG_REGS_GPO_4_LCD_CS_0;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_4_GPO_4;
+        availableGpo_A |= HAL_GPO_BIT(4);
+    }
+
+    if (halCfg->goudaCfg.cs1Used)
+    {
+        altMux |= CFG_REGS_GPO_3_LCD_CS_1;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_3_GPO_3;
+        availableGpo_A |= HAL_GPO_BIT(3);
+    }
+
+    // I2C
+    if (!halCfg->i2cCfg.i2cUsed)
+    {
+        availableGpio_B |= HAL_GPIO_BIT(30)
+                         | HAL_GPIO_BIT(31);
+    }
+
+    if (halCfg->i2cCfg.i2c2Used)
+    {
+        if (halCfg->i2cCfg.i2c2PinsCam)
+        {
+            if (camCfg->camUsed)
+            {
+                HAL_ASSERT(camCfg->camPdnRemap == GPIO_NONE &&
+                    camCfg->camRstRemap == GPIO_NONE,
+                    "Cam uses PDN/RST pins");
+            }
+            if (camCfg->cam1Used)
+            {
+                HAL_ASSERT(camCfg->cam1PdnRemap == GPIO_NONE &&
+                    camCfg->cam1RstRemap == GPIO_NONE,
+                    "Cam1 uses PDN/RST pins");
+            }
+            HAL_ASSERT(!nand8_15Cam, "NAND uses cam PDN/RST pins");
+            availableGpio_A |= HAL_GPIO_BIT(0)
+                             | HAL_GPIO_BIT(1);
+            altMux |= CFG_REGS_CAM_I2C2_I2C2;
+        }
+        else
+        {
+            // I2C2 does not use cam pins
+            altMux |= CFG_REGS_CAM_I2C2_CAM;
+        }
+    }
+    else
+    {
+        // I2C2 does not use cam pins
+        altMux |= CFG_REGS_CAM_I2C2_CAM;
+        availableGpio_A |= HAL_GPIO_BIT(0)
+                         | HAL_GPIO_BIT(1);
+    }
+
+    if (halCfg->i2cCfg.i2c3Used)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x18) == 0, "Keyout 3/4 use I2C3 pins");
+        altMux |= CFG_REGS_KEYOUT_3_4_I2C3;
+    }
+    else
+    {
+        altMux |= CFG_REGS_KEYOUT_3_4_KEYOUT_3_4;
+        if ((halCfg->keyOutMask & 0x8) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(6);
+        }
+        if ((halCfg->keyOutMask & 0x10) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(7);
+        }
+    }
+
+    // Camera
+    if (camCfg->camUsed || camCfg->cam1Used)
+    {
+        if(camCfg->camMode == HAL_CAM_MODE_PARALLEL)
+        {
+            HAL_ASSERT(!spiFlashCam, "SPI flash uses cam pins");
+            HAL_ASSERT(!nand8_15Cam, "NAND 8-15 bits use cam pins");
+            altMux |= CFG_REGS_CSI2_PARALLEL_CAM;
+            availableGpio_B |= HAL_GPIO_BIT(24);
+        }
+        else if (camCfg->camMode == HAL_CAM_MODE_SPI)
+        {
+            altMux |= CFG_REGS_CSI2_SPI_CAM;
+            availableGpio_B |= HAL_GPIO_BIT(14);
+            if (!(spiFlashCam || nand8_15Cam ||
+                  (lcdMode == HAL_LCD_MODE_RGB_24BIT &&
+                   halCfg->goudaCfg.lcd16_23Cam)
+                 )
+               )
+            {
+                availableGpio_B |= HAL_GPIO_BIT(13)
+                                 | HAL_GPIO_BIT(20)
+                                 | HAL_GPIO_BIT(21)
+                                 | HAL_GPIO_BIT(22)
+                                 | HAL_GPIO_BIT(23)
+                                 | HAL_GPIO_BIT(24);
+            }
+        }
+        else if (camCfg->camMode == HAL_CAM_MODE_CSI)
+        {
+            if ((camCfg->camUsed && camCfg->camCsiId == HAL_CAM_CSI_1) ||
+                (camCfg->cam1Used && camCfg->cam1CsiId == HAL_CAM_CSI_1))
+            {
+                HAL_ASSERT(!spiFlashCam, "SPI flash uses CSI1 pins");
+                HAL_ASSERT(!nand8_15Cam, "NAND 8-15 bits use CSI1 pins");
+            }
+            else
+            {
+                // CSI1 is unused
+                if (!(spiFlashCam || nand8_15Cam ||
+                      (lcdMode == HAL_LCD_MODE_RGB_24BIT &&
+                       halCfg->goudaCfg.lcd16_23Cam)
+                     )
+                   )
+                {
+                    availableGpio_B |= HAL_GPIO_BIT(13)
+                                     | HAL_GPIO_BIT(20)
+                                     | HAL_GPIO_BIT(21)
+                                     | HAL_GPIO_BIT(22)
+                                     | HAL_GPIO_BIT(23)
+                                     | HAL_GPIO_BIT(24);
+                }
+            }
+            altMux |= CFG_REGS_CSI2_CSI2;
+            // If CSI2 is unused
+            if (!((camCfg->camUsed && camCfg->camCsiId == HAL_CAM_CSI_2) ||
+                  (camCfg->cam1Used && camCfg->cam1CsiId == HAL_CAM_CSI_2)))
+            {
+                availableGpio_B |= HAL_GPIO_BIT(14)
+                                 | HAL_GPIO_BIT(15)
+                                 | HAL_GPIO_BIT(16)
+                                 | HAL_GPIO_BIT(17)
+                                 | HAL_GPIO_BIT(18)
+                                 | HAL_GPIO_BIT(19);
+            }
+        }
+        else
+        {
+            HAL_ASSERT(FALSE,"Invalid cam mode: %d", camCfg->camMode);
+        }
+
+        // Cam PDN/RST pins
+        if (!(nand8_15Cam ||
+              (lcdMode == HAL_LCD_MODE_RGB_24BIT && halCfg->goudaCfg.lcd16_23Cam) ||
+              (halCfg->i2cCfg.i2c2Used && halCfg->i2cCfg.i2c2PinsCam)
+             )
+           )
+        {
+            if (!((camCfg->camUsed && camCfg->camRstRemap == GPIO_NONE) ||
+                  (camCfg->cam1Used && camCfg->cam1RstRemap == GPIO_NONE)))
+            {
+                availableGpio_B |= HAL_GPIO_BIT(10);
+            }
+            if (!((camCfg->camUsed && camCfg->camPdnRemap == GPIO_NONE) ||
+                  (camCfg->cam1Used && camCfg->cam1PdnRemap == GPIO_NONE)))
+            {
+                availableGpio_B |= HAL_GPIO_BIT(11);
+                availableGpio_B |= HAL_GPIO_BIT(3);
+            }
+        }
+    }
+    else // cam is unused
+    {
+        availableGpio_B |= HAL_GPIO_BIT(12)
+                         | HAL_GPIO_BIT(14)
+                         | HAL_GPIO_BIT(15)
+                         | HAL_GPIO_BIT(16)
+                         | HAL_GPIO_BIT(17)
+                         | HAL_GPIO_BIT(18)
+                         | HAL_GPIO_BIT(19);
+        if (!(nand8_15Cam ||
+              (lcdMode == HAL_LCD_MODE_RGB_24BIT && halCfg->goudaCfg.lcd16_23Cam) ||
+              (halCfg->i2cCfg.i2c2Used && halCfg->i2cCfg.i2c2PinsCam)
+             )
+           )
+        {
+            availableGpio_B |= HAL_GPIO_BIT(10)
+                             | HAL_GPIO_BIT(11);
+        }
+        if (!(spiFlashCam || nand8_15Cam ||
+              (lcdMode == HAL_LCD_MODE_RGB_24BIT && halCfg->goudaCfg.lcd16_23Cam)
+             )
+           )
+        {
+            availableGpio_B |= HAL_GPIO_BIT(13)
+                             | HAL_GPIO_BIT(20)
+                             | HAL_GPIO_BIT(21)
+                             | HAL_GPIO_BIT(22)
+                             | HAL_GPIO_BIT(23)
+                             | HAL_GPIO_BIT(24);
+        }
+    }
+
+    // UART 1 Pin configuration
+    switch (halCfg->uartCfg[0])
+    {
+        case HAL_UART_CONFIG_NONE:
+            altMux |= CFG_REGS_KEYOUT_7_KEYOUT_7;
+            availableGpio_C |= HAL_GPIO_BIT(6);
+            availableGpio_A |= HAL_GPIO_BIT(14);
+            if ((halCfg->keyInMask & 0x80) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(15);
+            }
+            if ((halCfg->keyInMask & 0x80) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(16);
+            }
+            break;
+        case HAL_UART_CONFIG_DATA:
+             // use UART1 TXD, RXD
+            altMux |= CFG_REGS_KEYOUT_7_KEYOUT_7;
+            if ((halCfg->keyInMask & 0x80) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(15);
+            }
+            if ((halCfg->keyInMask & 0x80) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(16);
+            }
+            break;
+        case HAL_UART_CONFIG_FLOWCONTROL:
+             // use UART1 TXD, RXD, CTS, RTS
+            HAL_ASSERT((halCfg->keyInMask & 0x80) == 0, "Keyin 7 uses UART1 CTS");
+            HAL_ASSERT((halCfg->keyOutMask & 0x80) == 0, "Keyout 7 uses UART1 RTS");
+            altMux |= CFG_REGS_KEYOUT_7_UART1_RTS;
+            break;
+        case HAL_UART_CONFIG_MODEM:
+            // use UART1 TXD, RXD, CTS, RTS, RI, DSR, DCD, DTR
+            HAL_ASSERT((halCfg->keyInMask & 0x80) == 0, "Keyin 7 uses UART1 CTS");
+            HAL_ASSERT((halCfg->keyOutMask & 0x80) == 0, "Keyout 7 uses UART1 RTS");
+            HAL_ASSERT(!halCfg->hostUartUsed, "Host UART uses UART1 DCD/DTR");
+            HAL_ASSERT(halCfg->uartCfg[1] == HAL_UART_CONFIG_NONE,
+                    "UART 2 must be unused to use UART1 Modem lines.");
+            HAL_ASSERT((halCfg->keyInMask & 0x40) == 0, "Keyin 6 uses UART1 DSR");
+            HAL_ASSERT((halCfg->keyOutMask & 0x40) == 0, "Keyout 6 uses UART1 RI");
+            altMux |= CFG_REGS_KEYOUT_7_UART1_RTS
+                    | CFG_REGS_UART1_8LINE_UART1_8_LINE;
+            break;
+        default:
+            HAL_ASSERT(FALSE,
+                    "Invalid Uart 1 Configuration (%d).",
+                    halCfg->uartCfg[0]);
+            break;
+    }
+
+    // Host UART
+    if (halCfg->hostUartUsed)
+    {
+        HAL_ASSERT(halCfg->uartCfg[1] == HAL_UART_CONFIG_NONE,
+                "UART2 uses host UART RXD/TXD.");
+    }
+
+    // UART 2 Pin configuration
+    switch (halCfg->uartCfg[1])
+    {
+        case HAL_UART_CONFIG_NONE:
+            altMux |= CFG_REGS_UART2_HOST_UART
+                    | CFG_REGS_KEYOUT_6_KEYOUT_6;
+            if (halCfg->uartCfg[0] != HAL_UART_CONFIG_MODEM)
+            {
+                availableGpio_C |= HAL_GPIO_BIT(7)
+                                 | HAL_GPIO_BIT(8);
+            }
+            if ((halCfg->keyInMask & 0x40) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(8);
+            }
+            if ((halCfg->keyOutMask & 0x40) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(9);
+            }
+            break;
+        case HAL_UART_CONFIG_DATA:
+            // use UART2 TXD, RXD
+            altMux |= CFG_REGS_UART2_UART2
+                    | CFG_REGS_KEYOUT_6_KEYOUT_6;
+            if ((halCfg->keyInMask & 0x40) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(8);
+            }
+            if ((halCfg->keyOutMask & 0x40) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(9);
+            }
+            break;
+        case HAL_UART_CONFIG_FLOWCONTROL:
+             // use UART2 TXD, RXD, CTS, RTS
+            HAL_ASSERT((halCfg->keyInMask & 0x40) == 0, "Keyin 6 uses UART2 CTS");
+            HAL_ASSERT((halCfg->keyOutMask & 0x40) == 0, "Keyout 6 uses UART2 RTS");
+            altMux |= CFG_REGS_UART2_UART2
+                    | CFG_REGS_KEYOUT_6_UART2_RTS;
+            break;
+        case HAL_UART_CONFIG_MODEM:
+        default:
+            HAL_ASSERT(FALSE,
+                    "Invalid Uart2 Configuration (%d).",
+                    halCfg->uartCfg[1]);
+            break;
+    }
+
+    // UART 3 Pin configuration
+    switch (halCfg->uartCfg[2])
+    {
+        case HAL_UART_CONFIG_NONE:
+            availableGpio_D |= HAL_GPIO_BIT(0)
+                             | HAL_GPIO_BIT(1)
+                             | HAL_GPIO_BIT(2)
+                             | HAL_GPIO_BIT(3);
+            break;
+        case HAL_UART_CONFIG_DATA:
+            // use UART3 TXD, RXD
+            availableGpio_D |= HAL_GPIO_BIT(2)
+                             | HAL_GPIO_BIT(3);
+            break;
+        case HAL_UART_CONFIG_FLOWCONTROL:
+             // use UART3 TXD, RXD, CTS, RTS
+            break;
+        case HAL_UART_CONFIG_MODEM:
+        default:
+            HAL_ASSERT(FALSE,
+                    "Invalid Uart3 Configuration (%d).",
+                    halCfg->uartCfg[2]);
+            break;
+    }
+
+    // I2S
+    altMux |= CFG_REGS_DAI_I2S;
+    if (halCfg->i2sCfg.di0Used || halCfg->i2sCfg.di1Used ||
+        halCfg->i2sCfg.di2Used || halCfg->i2sCfg.doUsed)
+    {
+        if (!halCfg->i2sCfg.di0Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(11);
+        }
+        if (!halCfg->i2sCfg.di1Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(12);
+        }
+        if (halCfg->i2sCfg.di2Used)
+        {
+            HAL_ASSERT((halCfg->keyInMask & 0x4) == 0, "Keyin 2 uses I2S DI2");
+            altMux |= CFG_REGS_I2S_DI_2_I2S_DI_2;
+        }
+        else
+        {
+            altMux |= CFG_REGS_I2S_DI_2_KEYIN_2;
+            if ((halCfg->keyInMask & 0x4) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(2);
+            }
+        }
+        if (!halCfg->i2sCfg.doUsed)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(13);
+        }
+    }
+    else
+    {
+        availableGpio_A |= HAL_GPIO_BIT(9)
+                         | HAL_GPIO_BIT(10)
+                         | HAL_GPIO_BIT(11)
+                         | HAL_GPIO_BIT(12)
+                         | HAL_GPIO_BIT(13);
+    }
+
+    // LPS CO1
+    if (halCfg->useLpsCo1)
+    {
+        HAL_ASSERT((halCfg->keyInMask & 0x10) == 0, "Keyin 4 uses LPS_CO1");
+        altMux |= CFG_REGS_LPSCO_1_LPSCO_1;
+    }
+    else
+    {
+        altMux |= CFG_REGS_LPSCO_1_KEYIN_4;
+        if ((halCfg->keyInMask & 0x10) == 0)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(7);
+        }
+    }
+
+    // TCO
+    if (halCfg->usedTco & 0x1)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x1) == 0, "Keyout 0 uses TCO0");
+        altMux |= CFG_REGS_TCO_0_TCO_0;
+    }
+    else
+    {
+        altMux |= CFG_REGS_TCO_0_KEYOUT_0;
+        if ((halCfg->keyOutMask & 0x1) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(3);
+        }
+    }
+
+    if (halCfg->usedTco & 0x2)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x2) == 0, "Keyout 1 uses TCO1");
+        altMux |= CFG_REGS_TCO_1_TCO_1;
+    }
+    else
+    {
+        altMux |= CFG_REGS_TCO_1_KEYOUT_1;
+        if ((halCfg->keyOutMask & 0x2) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(4);
+        }
+    }
+
+    if (halCfg->usedTco & 0x4)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x4) == 0, "Keyout 2 uses TCO2");
+        altMux |= CFG_REGS_TCO_2_TCO_2;
+    }
+    else
+    {
+        altMux |= CFG_REGS_TCO_2_KEYOUT_2;
+        if ((halCfg->keyOutMask & 0x4) == 0)
+        {
+            availableGpio_B |= HAL_GPIO_BIT(5);
+        }
+    }
+
+    // PWM
+    if (halCfg->pwmCfg.pwtUsed)
+    {
+        HAL_ASSERT((halCfg->keyInMask & 0x20) == 0, "Keyin 5 uses PWT");
+        altMux |= CFG_REGS_GPO_0_PWT;
+    }
+    else if (halCfg->keyInMask & 0x20)
+    {
+        altMux |= CFG_REGS_GPO_0_KEYIN_5;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_0_GPO_0;
+        availableGpo_A |= HAL_GPO_BIT(0);
+    }
+
+    if (halCfg->pwmCfg.lpgUsed)
+    {
+        HAL_ASSERT((halCfg->keyOutMask & 0x20) == 0, "Keyout 5 uses LPG");
+        altMux |= CFG_REGS_GPO_1_LPG;
+    }
+    else if (halCfg->keyOutMask & 0x20)
+    {
+        altMux |= CFG_REGS_GPO_1_KEYOUT_5;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_1_GPO_1;
+        availableGpo_A |= HAL_GPO_BIT(1);
+    }
+
+    if (halCfg->pwmCfg.pwl1Used)
+    {
+        HAL_ASSERT(!halCfg->useClk32k, "Clk 32k uses PWL1");
+        altMux |= CFG_REGS_GPO_2_PWL_1;
+    }
+    else if (halCfg->useClk32k)
+    {
+        // Default to GPO low output
+        // 32K clock will be enabled per request
+        //altMux |= CFG_REGS_GPO_2_CLK_32K;
+        altMux |= CFG_REGS_GPO_2_GPO_2;
+    }
+    else
+    {
+        altMux |= CFG_REGS_GPO_2_GPO_2;
+        availableGpo_A |= HAL_GPO_BIT(2);
+    }
+
+    // Clock out and host clock
+    if (halCfg->clkOutUsed)
+    {
+        HAL_ASSERT(!halCfg->hostClkUsed, "HST_CLK uses CLK_OUT pin");
+        altMux |= CFG_REGS_CLK_OUT_CLK_OUT;
+    }
+    else if (halCfg->hostClkUsed)
+    {
+        altMux |= CFG_REGS_CLK_OUT_HST_CLK;
+    }
+    else
+    {
+        altMux |= CFG_REGS_CLK_OUT_HST_CLK;
+        availableGpo_A |= HAL_GPO_BIT(8);
+    }
+
+    // SPI
+    if (halCfg->spiCfg[0].cs0Used || halCfg->spiCfg[0].cs1Used ||
+        halCfg->spiCfg[0].cs2Used)
+    {
+        HAL_ASSERT(!(halCfg->modemSpiCfg[0].cs0Used ||
+                     halCfg->modemSpiCfg[0].cs1Used ||
+                     halCfg->modemSpiCfg[0].cs2Used), "Modem SPI1 is in use");
+        altMux |= CFG_REGS_AP_SPI1_AP_SPI1;
+        if (!halCfg->spiCfg[0].cs0Used)
+        {
+            availableGpio_C |= HAL_GPIO_BIT(22);
+        }
+        if (!halCfg->spiCfg[0].cs1Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(17);
+        }
+        if (halCfg->spiCfg[0].cs2Used)
+        {
+            HAL_ASSERT((halCfg->keyInMask & 0x2) == 0, "Keyin 1 uses SPI1 CS2");
+            altMux |= CFG_REGS_SPI1_CS_2_SPI1_CS_2;
+        }
+        else
+        {
+            altMux |= CFG_REGS_SPI1_CS_2_KEYIN_1;
+            if ((halCfg->keyInMask & 0x2) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(1);
+            }
+        }
+        if (!halCfg->spiCfg[0].di0Used)
+        {
+            availableGpio_C |= HAL_GPIO_BIT(23);
+        }
+        if (!halCfg->spiCfg[0].di1Used)
+        {
+            availableGpio_C |= HAL_GPIO_BIT(24);
+        }
+    }
+    else // AP SPI1 unused
+    {
+        altMux |= CFG_REGS_AP_SPI1_BB_SPI1;
+        if (halCfg->modemSpiCfg[0].cs0Used || halCfg->modemSpiCfg[0].cs1Used ||
+            halCfg->modemSpiCfg[0].cs2Used)
+        {
+            if (!halCfg->modemSpiCfg[0].cs0Used)
+            {
+                availableGpio_C |= HAL_GPIO_BIT(22);
+            }
+            if (!halCfg->modemSpiCfg[0].cs1Used)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(17);
+            }
+            if (!halCfg->modemSpiCfg[0].di0Used)
+            {
+                availableGpio_C |= HAL_GPIO_BIT(23);
+            }
+            if (!halCfg->modemSpiCfg[0].di1Used)
+            {
+                availableGpio_C |= HAL_GPIO_BIT(24);
+            }
+        }
+        else
+        {
+            availableGpio_A |= HAL_GPIO_BIT(17);
+            availableGpio_C |= HAL_GPIO_BIT(21)
+                             | HAL_GPIO_BIT(22)
+                             | HAL_GPIO_BIT(23)
+                             | HAL_GPIO_BIT(24);
+            if ((halCfg->keyInMask & 0x2) == 0)
+            {
+                availableGpio_B |= HAL_GPIO_BIT(1);
+            }
+        }
+    }
+    if (halCfg->spiCfg[1].cs0Used || halCfg->spiCfg[1].cs1Used)
+    {
+        if (!halCfg->spiCfg[1].cs0Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(5);
+        }
+        if (halCfg->spiCfg[1].cs1Used)
+        {
+            HAL_ASSERT((halCfg->keyInMask & 0x8) == 0, "Keyin 3 uses SPI2 CS1");
+            altMux |= CFG_REGS_KEYIN_3_SPI2_CS_1;
+        }
+        else
+        {
+            altMux |= CFG_REGS_KEYIN_3_KEYIN_3;
+            if ((halCfg->keyInMask & 0x8) == 0)
+            {
+                availableGpio_A |= HAL_GPIO_BIT(6);
+            }
+        }
+        if (!halCfg->spiCfg[1].di0Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(3);
+        }
+        if (!halCfg->spiCfg[1].di1Used)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(4);
+        }
+    }
+    else // AP SPI2 unused
+    {
+        availableGpio_A |= HAL_GPIO_BIT(2)
+                         | HAL_GPIO_BIT(3)
+                         | HAL_GPIO_BIT(4)
+                         | HAL_GPIO_BIT(5);
+        if ((halCfg->keyInMask & 0x8) == 0)
+        {
+            availableGpio_A |= HAL_GPIO_BIT(6);
+        }
+    }
+
+    // Standalone keyin/out
+    if ((halCfg->keyInMask & 0x1) == 0)
+    {
+        availableGpio_B |= HAL_GPIO_BIT(0);
+    }
+
+    // SDMMC
+    if (!halCfg->sdmmcCfg.sdmmcUsed)
+    {
+        availableGpio_C |= HAL_GPIO_BIT(9)
+                         | HAL_GPIO_BIT(10)
+                         | HAL_GPIO_BIT(11)
+                         | HAL_GPIO_BIT(12)
+                         | HAL_GPIO_BIT(13)
+                         | HAL_GPIO_BIT(14);
+    }
+    if (!halCfg->sdmmcCfg.sdmmc2Used)
+    {
+        availableGpio_C |= HAL_GPIO_BIT(15)
+                         | HAL_GPIO_BIT(16)
+                         | HAL_GPIO_BIT(17)
+                         | HAL_GPIO_BIT(18)
+                         | HAL_GPIO_BIT(19)
+                         | HAL_GPIO_BIT(20);
+    }
+    HAL_ASSERT(!(parallelNandUsed && halCfg->sdmmcCfg.sdmmc3Used),
+        "Parallel NAND uses SDMMC3 pins");
+
+    // SIM
+    if (!hal_BoardSimUsed(2))
+    {
+        availableGpio_C |= HAL_GPIO_BIT(25)
+                         | HAL_GPIO_BIT(26)
+                         | HAL_GPIO_BIT(27);
+    }
+
+    if (!hal_BoardSimUsed(3))
+    {
+        availableGpio_C |= HAL_GPIO_BIT(28)
+                         | HAL_GPIO_BIT(29)
+                         | HAL_GPIO_BIT(30);
+    }
+    
+    UINT32 gpioMask;
+    // GPIO_C mask check
+    gpioMask = ~availableGpio_C & halCfg->usedGpio_C;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO C are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_C & halCfg->noConnectGpio_C;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO C declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_C & halCfg->noConnectGpio_C;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO C declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_C &
+               (~halCfg->usedGpio_C & ~halCfg->noConnectGpio_C);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO C declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPIO_A mask check
+    gpioMask = ~availableGpio_A & halCfg->usedGpio_A;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO A are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_A & halCfg->noConnectGpio_A;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO A declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_A & halCfg->noConnectGpio_A;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO A declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_A &
+               (~halCfg->usedGpio_A & ~halCfg->noConnectGpio_A);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO A declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPIO_B mask check
+    gpioMask = ~availableGpio_B & halCfg->usedGpio_B;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO B are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_B & halCfg->noConnectGpio_B;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO B declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_B & halCfg->noConnectGpio_B;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO B declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_B &
+               (~halCfg->usedGpio_B & ~halCfg->noConnectGpio_B);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO B declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPIO_D mask check
+    gpioMask = ~availableGpio_D & halCfg->usedGpio_D;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPIO D are not available (0x%x)",
+               gpioMask);
+    gpioMask = ~availableGpio_D & halCfg->noConnectGpio_D;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO D declared as not connected are not available (0x%x)",
+               gpioMask);
+    gpioMask = halCfg->usedGpio_D & halCfg->noConnectGpio_D;
+    HAL_ASSERT(gpioMask == 0,
+               "Some GPIO D declared as not connected are used (0x%x)",
+               gpioMask);
+#ifdef CHECK_GPIO_ALT_FUNC
+    gpioMask = availableGpio_D &
+               (~halCfg->usedGpio_D & ~halCfg->noConnectGpio_D);
+    HAL_ASSERT(gpioMask == 0,
+               "Some available GPIO D declared as alt function (0x%x)",
+               gpioMask);
+#endif
+
+    // GPO_A mask check
+    gpioMask = ~availableGpo_A & halCfg->usedGpo_A;
+    HAL_ASSERT(gpioMask == 0,
+               "Some used GPO A are not available (0x%x)",
+               gpioMask);
+
+#endif // !FPGA
+
+    // Set IO drive
+    hwp_configRegs->IO_Drive1_Select = halCfg->ioDrive.select1;
+    hwp_configRegs->IO_Drive2_Select = halCfg->ioDrive.select2;
+
+    // Set the not connected ones as output and drive 0
+    // But keep boot mode GPIOs as input to avoid current leakage
+    noConnectMask_C = halCfg->noConnectGpio_C & ~bootModeGpio_C;
+    noConnectMask_A = halCfg->noConnectGpio_A & ~bootModeGpio_A;
+    noConnectMask_B = halCfg->noConnectGpio_B & ~bootModeGpio_B;
+    noConnectMask_D = halCfg->noConnectGpio_D & ~bootModeGpio_D;
+
+    hwp_gpio->gpio_clr = noConnectMask_C;
+    hwp_gpio->gpio_oen_set_out = noConnectMask_C;
+
+    hwp_apGpioA->gpio_clr = noConnectMask_A;
+    hwp_apGpioA->gpio_oen_set_out = noConnectMask_A;
+
+    hwp_apGpioB->gpio_clr = noConnectMask_B;
+    hwp_apGpioB->gpio_oen_set_out = noConnectMask_B;
+
+    hwp_apGpioD->gpio_clr = noConnectMask_D;
+    hwp_apGpioD->gpio_oen_set_out = noConnectMask_D;
+
+    // Init GPO_A values
+    if (halCfg->useClk32k)
+    {
+        // Init 32K clock pin to low (by setting up GPO)
+        hwp_apGpioA->gpo_clr = availableGpo_A
+                             | HAL_GPO_BIT(2);
+    }
+    else
+    {
+	/* if GPO_1 used for usb id, it should be high */
+	#if defined(_TGT_AP_GPIO_USBID_CTRL)
+		hwp_apGpioA->gpo_clr = availableGpo_A & ~0x2;
+	#else
+		hwp_apGpioA->gpo_clr = availableGpo_A;
+	#endif
+    }
+
+    // Configure MUX after initializing all the GPO pins
+    // (GPIO pins are in input mode by default)
+
+    // Set GPIO mode
+    hwp_configRegs->BB_GPIO_Mode = availableGpio_C;
+    hwp_configRegs->AP_GPIO_A_Mode = availableGpio_A;
+    hwp_configRegs->AP_GPIO_B_Mode = availableGpio_B;
+    hwp_configRegs->AP_GPIO_D_Mode = availableGpio_D;
+    // Set Alt Mux configuration
+    hwp_configRegs->Alt_mux_select = altMux;
+
+    // --------------------------------------------------
+    // As of now, all connected GPIOs, which are as GPIO
+    // or not used at all but connected are configured as
+    // GPIOs in input mode, except for Gouda reset pins
+    // --------------------------------------------------
+
+}
+
+
+// =============================================================================
+// hal_BoardSetup
+// -----------------------------------------------------------------------------
+/// Apply board dependent configuration to HAL
+/// @param halCfg Pointer to HAL configuration structure (from the target
+/// module).
+// ============================================================================
+//PROTECTED VOID hal_BoardSetup(CONST HAL_CFG_CONFIG_T* halCfg)
+PUBLIC INT32 hal_BoardSetup(INT8 run_mode)
+{
+	g_bootBootMode = rda_hwcfg_get();
+	hal_BoardSetupGeneral(&hal_cfg);
+
+	if(g_halConfigError)
+		return CMD_RET_FAILURE;
+	else
+		return CMD_RET_SUCCESS;
+}
diff --git a/board/rda/rda8850e/lpddr2_init.h b/board/rda/rda8850e/lpddr2_init.h
new file mode 100644
index 0000000000..8e7dc70d62
--- /dev/null
+++ b/board/rda/rda8850e/lpddr2_init.h
@@ -0,0 +1,114 @@
+#ifndef _SYS_DDR_INIT_H_
+#define _SYS_DDR_INIT_H_
+
+#include <common.h>
+#include "ddr.h"
+#include "ddr_init.h"
+
+#define  PHY_RDLAT          0
+#define  PHYWRDATA          1
+#define  STA                3
+#define  CLKSEL             4
+#define  PSSTART            5
+#define  PSDONE             6
+#define  LOCKED             6
+#define  CTRL_DELAY         7
+#define  RDELAY_SEL         8
+#define  WDELAY_SEL         9
+#define  PHY_RESET          10
+#define  RESET_DDR3         11
+#define  ODT_DELAY          12
+#define  DDR3_USED          13
+#define  WRITE_ENABLE_LAT   14
+#define  WRITE_DATA_LAT     15
+#define  DQOUT_ENABLE_LAT   16
+#define  DATA_ODT_ENABLE_REG	20
+#define  DATA_WRITE_ENABLE_REG  48
+#define  DMC_READY	128
+#define  USE_ADDR	129
+
+const dmc_reg_t dmc_reg_cfg[] = {
+	{T_REFI,	0x90,		0x90},
+	{T_RFC,		0x2F0016,	0x2F0016},
+	{T_MRR,		0x2,		0x2},
+	{T_MRW,		0x5,		0x5},
+	{T_RCD,		0x8,		0x8},
+	{T_RAS,		0x11,		0x11},
+	{T_RP,		0x8,		0x8},
+	{T_RPALL,	0x9,		0x9},
+	{T_RRD,		0x4,		0x4},
+	{T_FAW,		0x14,		0x14},
+	{T_RTR,		0x4,		0x4},
+	{T_RTW,		0x0F,		0x0F},
+	{T_RTP,		0x6,		0x6},
+	{T_WR,		0xE,		0xE},
+	{T_WTR,		0x1F000F,	0x1F000F},
+	{T_WTW,		0x40000,	0x40000},
+	{RD_LATENCY,	0x8,		0x8},
+	{WR_LATENCY,	0x4,		0x4},
+	{T_RDDATA_EN,	0x9,		0x9},
+	{T_PHYWRLAT,	0x103,		0x103},
+	{T_XP,		0x20003,	0x20003},
+	{T_XP,		0x80003,	0x80003},
+	{T_ESR,		0x6,		0x6},
+	{T_XSR,		0x580032,	0x580032},
+	{T_SRCKD,	0x5,		0x5},
+	{T_CKSRD,	0x5,		0x5},
+	{T_ECKD,	0x5,		0x5},
+	{T_XCKD,	0x5,		0x5},
+	{T_EP,		0x5,		0x5},
+	{RDLVL_CTRL,	0x1010,		0x1010},
+	{RDLVL_CTRL,	0x1110,		0x1110},
+	{RDLVL_CTRL,	0x11110,	0x11110},
+	{REFRESH_CTRL,	0x1,		0x1},
+	{ECC_CTRL,	0x0,		0x0},
+	{ADDR_CTRL,	0x30200,	0x30200},
+	{ECC_CTRL,	0x0,		0x0},
+	{QOSX_CTRL6,	0x9,		0x9}, //set qos priority 9 for modem
+	{QUEUE_CTRL,	0x10,		0x10},//reserve 1 queue for modem
+};
+
+const dmc_reg_t dmc_reg_low_power_cfg[] = {
+	{LOWPWR_CTRL,	0x48,	0x48},
+	{T_ESR,		0x6,	0x6},
+	{T_XSR,		0x32,	0x32},
+	{T_SRCKD,	0xa,	0xa},
+	{T_CKSRD,	0xa,	0x5},
+};
+
+const dmc_reg_t ddr_config[] = {
+	{DIRECT_CMD,	0x0,		0x0},
+	{DIRECT_CMD,	0x1000003f,	0x1000003f},
+	{DIRECT_CMD,	0x1000ff0a,	0x1000ff0a},
+	{DIRECT_CMD,	0x10008301,	0x10008301},
+	{DIRECT_CMD,	0x10000602,	0x10000602},
+	{DIRECT_CMD,	0x10000103,	0x10000103},
+	{DIRECT_CMD,	0x30000000,	0x30000000},
+};
+
+const dmc_reg_t dmc_digphy_config[] = {
+	{USE_ADDR*4,			0x0,	0x0},
+	{WDELAY_SEL*4,			0x3,	0x3},
+	{RDELAY_SEL*4,			0x6,	0x6},
+	{DQOUT_ENABLE_LAT*4,		0x1,	0x1},
+	{DATA_WRITE_ENABLE_REG*4,	0xf,	0xf},
+#ifdef CONFIG_RDA_FPGA
+	{DATA_ODT_ENABLE_REG*4,		0xe,	0xe},
+#else
+	{DATA_ODT_ENABLE_REG*4,		0xf,	0xf},
+#endif
+};
+
+const dmc_reg_t dmc_digphy_eco2_config[] = {
+	{USE_ADDR*4,			0x0,	0x0},
+	{WDELAY_SEL*4,			0x7,	0x7},
+	{RDELAY_SEL*4,			0x6,	0x6},
+	{DQOUT_ENABLE_LAT*4,            0x3,    0x3},
+	{DATA_WRITE_ENABLE_REG*4,	0xf,	0xf},
+#ifdef CONFIG_RDA_FPGA
+	{DATA_ODT_ENABLE_REG*4,		0xe,	0xe},
+#else
+	{DATA_ODT_ENABLE_REG*4,		0xf,	0xf},
+#endif
+};
+#endif
diff --git a/board/rda/rda8850e/u-boot-spl.lds b/board/rda/rda8850e/u-boot-spl.lds
new file mode 100644
index 0000000000..afe35fd2a8
--- /dev/null
+++ b/board/rda/rda8850e/u-boot-spl.lds
@@ -0,0 +1,35 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00100100;
+	. = ALIGN(4);
+	.text :
+	{
+		__start = .;
+		arch/arm/cpu/armv7/start.o (.text)
+			*(.text)
+	}
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+	. = ALIGN(4);
+	.data : {
+		*(.data)
+	}
+	. = ALIGN(4);
+	. = .;
+	. = ALIGN(4);
+	__image_copy_end = .;
+	_end = .;
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+		ASSERT((ABSOLUTE(__bss_end__) < 0x00110000), \
+			"too big data in spl, don't exceed intrenal ram");
+	}
+}
diff --git a/board/rda/rdaarm926ejs/Makefile b/board/rda/rdaarm926ejs/Makefile
new file mode 100644
index 0000000000..f78058b490
--- /dev/null
+++ b/board/rda/rdaarm926ejs/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-$(CONFIG_MACH_RDAARM926EJS)	+= rdaarm926ejs.o misc.o 
+
+COBJS   := $(COBJS-y)
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak *~ .depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/rda/rdaarm926ejs/misc.c b/board/rda/rdaarm926ejs/misc.c
new file mode 100644
index 0000000000..00b67fe49f
--- /dev/null
+++ b/board/rda/rdaarm926ejs/misc.c
@@ -0,0 +1,22 @@
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size(
+			(volatile void *)CONFIG_SYS_SDRAM_BASE,
+			CONFIG_MAX_RAM_BANK_SIZE);
+	icache_enable();
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
diff --git a/board/rda/rdaarm926ejs/rdaarm926ejs.c b/board/rda/rdaarm926ejs/rdaarm926ejs.c
new file mode 100644
index 0000000000..97c7959603
--- /dev/null
+++ b/board/rda/rdaarm926ejs/rdaarm926ejs.c
@@ -0,0 +1,67 @@
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void rda_dump_buf(char *data, size_t len)
+{
+    char temp_buf[64];
+    size_t i, off = 0;
+
+    memset(temp_buf, 0, 64);
+    for (i=0;i<len;i++) {
+        if(i%8 == 0) {
+            sprintf(&temp_buf[off], "  ");
+            off += 2;
+        }
+        sprintf(&temp_buf[off], "%02x ", data[i]);
+        off += 3;
+        if((i+1)%16 == 0 || (i+1) == len) {
+            printf("%s\n", temp_buf);
+            memset(temp_buf, 0, 64);
+            off = 0;
+        }
+    }
+    printf("\n");
+}
+
+/*
+ * get_board_rev() - setup to pass kernel board revision information
+ * Returns:
+ * bit[0-3]	Maximum cpu clock rate supported by onboard SoC
+ */
+u32 get_board_rev(void)
+{
+	u32 rev = 0;
+	return rev;
+}
+
+int board_init(void)
+{
+	/* arch number of the board */
+	gd->bd->bi_arch_number = MACH_TYPE_RDAARM926EJS;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	return 0;
+}
+
+#ifdef CONFIG_RDA_MMC
+int rda_mmc_init(void);
+#endif
+
+int board_mmc_init(bd_t *bis)
+{
+	int err = -1;
+
+#ifdef CONFIG_RDA_MMC
+	err = rda_mmc_init();
+	if (err)
+		return err;
+#endif
+
+	return err;
+}
+
diff --git a/board/samsung/smdk5250/tzpc_init.c b/board/samsung/smdk5250/tzpc_init.c
index c2ccef3381..c833541fd0 100644
--- a/board/samsung/smdk5250/tzpc_init.c
+++ b/board/samsung/smdk5250/tzpc_init.c
@@ -28,11 +28,11 @@
 /* Setting TZPC[TrustZone Protection Controller] */
 void tzpc_init(void)
 {
-	struct exynos5_tzpc *tzpc;
+	struct exynos_tzpc *tzpc;
 	unsigned int addr;
 
 	for (addr = TZPC0_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) {
-		tzpc = (struct exynos5_tzpc *)addr;
+		tzpc = (struct exynos_tzpc *)addr;
 
 		if (addr == TZPC0_BASE)
 			writel(R0SIZE, &tzpc->r0size);
diff --git a/board/samsung/smdk6400/.gitignore b/board/samsung/smdk6400/.gitignore
deleted file mode 100644
index 25ab492c50..0000000000
--- a/board/samsung/smdk6400/.gitignore
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Generated files
-#
-
-/config.tmp
diff --git a/board/samsung/smdkc100/onenand.c b/board/samsung/smdkc100/onenand.c
index 501855edd3..e34cd31f24 100644
--- a/board/samsung/smdkc100/onenand.c
+++ b/board/samsung/smdkc100/onenand.c
@@ -22,7 +22,7 @@
  */
 
 #include <common.h>
-#include <linux/mtd/compat.h>
+#include <linux/compat.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/onenand.h>
 #include <linux/mtd/samsung_onenand.h>
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index aa4291df4a..3085de1a14 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -2,6 +2,7 @@
  * Copyright (C) 2011 Samsung Electronics
  * Heungjun Kim <riverful.kim@samsung.com>
  * Kyungmin Park <kyungmin.park@samsung.com>
+ * Donghwa Lee <dh09.lee@samsung.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -23,16 +24,19 @@
  */
 
 #include <common.h>
+#include <lcd.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/mipi_dsim.h>
 #include <asm/arch/watchdog.h>
 #include <asm/arch/power.h>
 #include <pmic.h>
 #include <usb/s3c_udc.h>
-#include <max8998_pmic.h>
+#include <max8997_pmic.h>
 
 #include "setup.h"
 
@@ -216,26 +220,19 @@ static int s5pc210_phy_control(int on)
 		return -1;
 
 	if (on) {
-		ret |= pmic_set_output(p,
-				       MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
-				       MAX8998_SAFEOUT1, LDO_ON);
-		ret |= pmic_set_output(p, MAX8998_REG_ONOFF1,
-				      MAX8998_LDO3, LDO_ON);
-		ret |= pmic_set_output(p, MAX8998_REG_ONOFF2,
-				      MAX8998_LDO8, LDO_ON);
-
+		ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
+				      ENSAFEOUT1, LDO_ON);
+		ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO);
+		ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO);
 	} else {
-		ret |= pmic_set_output(p, MAX8998_REG_ONOFF2,
-				      MAX8998_LDO8, LDO_OFF);
-		ret |= pmic_set_output(p, MAX8998_REG_ONOFF1,
-				      MAX8998_LDO3, LDO_OFF);
-		ret |= pmic_set_output(p,
-				       MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
-				       MAX8998_SAFEOUT1, LDO_OFF);
+		ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO);
+		ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO);
+		ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
+				      ENSAFEOUT1, LDO_OFF);
 	}
 
 	if (ret) {
-		puts("MAX8998 LDO setting error!\n");
+		puts("MAX8997 LDO setting error!\n");
 		return -1;
 	}
 
@@ -364,3 +361,145 @@ int board_early_init_f(void)
 
 	return 0;
 }
+
+static void lcd_reset(void)
+{
+	struct exynos4_gpio_part2 *gpio2 =
+		(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
+
+	s5p_gpio_direction_output(&gpio2->y4, 5, 1);
+	udelay(10000);
+	s5p_gpio_direction_output(&gpio2->y4, 5, 0);
+	udelay(10000);
+	s5p_gpio_direction_output(&gpio2->y4, 5, 1);
+}
+
+static int lcd_power(void)
+{
+	int ret = 0;
+	struct pmic *p = get_pmic();
+
+	if (pmic_probe(p))
+		return 0;
+
+	/* LDO15 voltage: 2.2v */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
+	/* LDO13 voltage: 3.0v */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
+
+	if (ret) {
+		puts("MAX8997 LDO setting error!\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+static struct mipi_dsim_config dsim_config = {
+	.e_interface		= DSIM_VIDEO,
+	.e_virtual_ch		= DSIM_VIRTUAL_CH_0,
+	.e_pixel_format		= DSIM_24BPP_888,
+	.e_burst_mode		= DSIM_BURST_SYNC_EVENT,
+	.e_no_data_lane		= DSIM_DATA_LANE_4,
+	.e_byte_clk		= DSIM_PLL_OUT_DIV8,
+	.hfp			= 1,
+
+	.p			= 3,
+	.m			= 120,
+	.s			= 1,
+
+	/* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
+	.pll_stable_time	= 500,
+
+	/* escape clk : 10MHz */
+	.esc_clk		= 20 * 1000000,
+
+	/* stop state holding counter after bta change count 0 ~ 0xfff */
+	.stop_holding_cnt	= 0x7ff,
+	/* bta timeout 0 ~ 0xff */
+	.bta_timeout		= 0xff,
+	/* lp rx timeout 0 ~ 0xffff */
+	.rx_timeout		= 0xffff,
+};
+
+static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
+	.lcd_panel_info = NULL,
+	.dsim_config = &dsim_config,
+};
+
+static struct mipi_dsim_lcd_device mipi_lcd_device = {
+	.name	= "s6e8ax0",
+	.id	= -1,
+	.bus_id	= 0,
+	.platform_data	= (void *)&s6e8ax0_platform_data,
+};
+
+static int mipi_power(void)
+{
+	int ret = 0;
+	struct pmic *p = get_pmic();
+
+	if (pmic_probe(p))
+		return 0;
+
+	/* LDO3 voltage: 1.1v */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
+	/* LDO4 voltage: 1.8v */
+	ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
+
+	if (ret) {
+		puts("MAX8997 LDO setting error!\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+void init_panel_info(vidinfo_t *vid)
+{
+	vid->vl_freq	= 60;
+	vid->vl_col	= 720;
+	vid->vl_row	= 1280;
+	vid->vl_width	= 720;
+	vid->vl_height	= 1280;
+	vid->vl_clkp	= CONFIG_SYS_HIGH;
+	vid->vl_hsp	= CONFIG_SYS_LOW;
+	vid->vl_vsp	= CONFIG_SYS_LOW;
+	vid->vl_dp	= CONFIG_SYS_LOW;
+
+	vid->vl_bpix	= 5;
+	vid->dual_lcd_enabled = 0;
+
+	/* s6e8ax0 Panel */
+	vid->vl_hspw	= 5;
+	vid->vl_hbpd	= 10;
+	vid->vl_hfpd	= 10;
+
+	vid->vl_vspw	= 2;
+	vid->vl_vbpd	= 1;
+	vid->vl_vfpd	= 13;
+	vid->vl_cmd_allow_len = 0xf;
+
+	vid->win_id = 3;
+	vid->cfg_gpio = NULL;
+	vid->backlight_on = NULL;
+	vid->lcd_power_on = NULL;	/* lcd_power_on in mipi dsi driver */
+	vid->reset_lcd = lcd_reset;
+
+	vid->init_delay = 0;
+	vid->power_on_delay = 0;
+	vid->reset_delay = 0;
+	vid->interface_mode = FIMD_RGB_INTERFACE;
+	vid->mipi_enabled = 1;
+
+	strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
+	s6e8ax0_platform_data.lcd_power = lcd_power;
+	s6e8ax0_platform_data.mipi_power = mipi_power;
+	s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
+	s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
+	exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
+	s6e8ax0_init();
+	exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
+
+	setenv("lcdinfo", "lcd=s6e8ax0");
+}
diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c
index d0ff8341f6..90fff5cf5e 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -58,13 +58,13 @@ int board_init(void)
 	gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
-	check_hw_revision();
-	printf("HW Revision:\t0x%x\n", board_rev);
-
 #if defined(CONFIG_PMIC)
 	pmic_init();
 #endif
 
+	check_hw_revision();
+	printf("HW Revision:\t0x%x\n", board_rev);
+
 	return 0;
 }
 
@@ -109,10 +109,27 @@ static unsigned short get_adc_value(int channel)
 	return ret;
 }
 
+static int adc_power_control(int on)
+{
+	int ret;
+	struct pmic *p = get_pmic();
+
+	if (pmic_probe(p))
+		return -1;
+
+	ret = pmic_set_output(p,
+			      MAX8998_REG_ONOFF1,
+			      MAX8998_LDO4, !!on);
+
+	return ret;
+}
+
 static unsigned int get_hw_revision(void)
 {
 	int hwrev, mode0, mode1;
 
+	adc_power_control(1);
+
 	mode0 = get_adc_value(1);		/* HWREV_MODE0 */
 	mode1 = get_adc_value(2);		/* HWREV_MODE1 */
 
@@ -135,6 +152,8 @@ static unsigned int get_hw_revision(void)
 
 	debug("mode0: %d, mode1: %d, hwrev 0x%x\n", mode0, mode1, hwrev);
 
+	adc_power_control(0);
+
 	return hwrev;
 }
 
diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c
index b92758692d..c2b10ac1ea 100644
--- a/board/technexion/twister/twister.c
+++ b/board/technexion/twister/twister.c
@@ -133,7 +133,7 @@ int board_eth_init(bd_t *bis)
 	!defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
-	return omap_mmc_init(0);
+	return omap_mmc_init(0, 0, 0);
 }
 #endif
 
diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c
index c5eb42c362..9fbaedd792 100644
--- a/board/teejet/mt_ventoux/mt_ventoux.c
+++ b/board/teejet/mt_ventoux/mt_ventoux.c
@@ -196,13 +196,6 @@ int board_init(void)
 	return 0;
 }
 
-int misc_init_r(void)
-{
-	dieid_num_r();
-
-	return 0;
-}
-
 /*
  * Routine: set_muxconf_regs
  * Description: Setting up the configuration Mux registers specific to the
@@ -228,6 +221,6 @@ int board_eth_init(bd_t *bis)
 	!defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
-	return omap_mmc_init(0);
+	return omap_mmc_init(0, 0, 0);
 }
 #endif
diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c
index 436645a83f..888398deac 100644
--- a/board/ti/am3517crane/am3517crane.c
+++ b/board/ti/am3517crane/am3517crane.c
@@ -78,7 +78,7 @@ void set_muxconf_regs(void)
 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
-	omap_mmc_init(0);
+	omap_mmc_init(0, 0, 0);
 	return 0;
 }
 #endif
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index e26b387934..9edd3c5c4f 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -477,7 +477,7 @@ void set_muxconf_regs(void)
 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
-	omap_mmc_init(0);
+	omap_mmc_init(0, 0, 0);
 	return 0;
 }
 #endif
diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
index 8497aee6de..61fc7b5531 100644
--- a/board/ti/evm/evm.c
+++ b/board/ti/evm/evm.c
@@ -278,7 +278,7 @@ int board_eth_init(bd_t *bis)
 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
-	omap_mmc_init(0);
+	omap_mmc_init(0, 0, 0);
 	return 0;
 }
 #endif
diff --git a/board/ti/omap5912osk/omap5912osk.c b/board/ti/omap5912osk/omap5912osk.c
index 6f0e763f01..fac683a7e6 100644
--- a/board/ti/omap5912osk/omap5912osk.c
+++ b/board/ti/omap5912osk/omap5912osk.c
@@ -81,13 +81,6 @@ int board_init (void)
 	return 0;
 }
 
-
-int misc_init_r (void)
-{
-	/* currently empty */
-	return (0);
-}
-
 /******************************
  Routine:
  Description:
diff --git a/board/ti/omap5_evm/evm.c b/board/ti/omap5_evm/evm.c
index ea0cb13b43..c8dfdf8142 100644
--- a/board/ti/omap5_evm/evm.c
+++ b/board/ti/omap5_evm/evm.c
@@ -23,7 +23,7 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
-#include <twl6030.h>
+#include <twl6035.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 
@@ -63,8 +63,8 @@ int board_eth_init(bd_t *bis)
  */
 int misc_init_r(void)
 {
-#ifdef CONFIG_TWL6030_POWER
-	twl6030_init_battery_charging();
+#ifdef CONFIG_TWL6035_POWER
+	twl6035_init_settings();
 #endif
 	return 0;
 }
@@ -94,8 +94,8 @@ void set_muxconf_regs_non_essential(void)
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
-	omap_mmc_init(0);
-	omap_mmc_init(1);
+	omap_mmc_init(0, 0, 0);
+	omap_mmc_init(1, 0, 0);
 	return 0;
 }
 #endif
diff --git a/board/ti/omap5_evm/mux_data.h b/board/ti/omap5_evm/mux_data.h
index 18f4729257..296eb682e1 100644
--- a/board/ti/omap5_evm/mux_data.h
+++ b/board/ti/omap5_evm/mux_data.h
@@ -2,8 +2,7 @@
  * (C) Copyright 2010
  * Texas Instruments Incorporated, <www.ti.com>
  *
- *	Balaji Krishnamoorthy	<balajitk@ti.com>
- *	Aneesh V		<aneesh@ti.com>
+ *	Sricharan R		<r.sricharan@ti.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -30,246 +29,276 @@
 
 const struct pad_conf_entry core_padconf_array_essential[] = {
 
-{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
-{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
-{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
-{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
-{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
-{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
-{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
-{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
-{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},	 /* sdmmc2_clk */
-{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
-{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},	 /* sdmmc1_clk */
-{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
-{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
-{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
-{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
-{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
-{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
-{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
-{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
-{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
-{UART3_CTS_RCTX, (PTU | IEN | M0)},			/* uart3_tx */
-{UART3_RTS_SD, (M0)},					/* uart3_rts_sd */
-{UART3_RX_IRRX, (IEN | M0)},				/* uart3_rx */
-{UART3_TX_IRTX, (M0)}					/* uart3_tx */
+	{EMMC_CLK, (PTU | IEN | M0)}, /*  EMMC_CLK   */
+	{EMMC_CMD, (PTU | IEN | M0)}, /*  EMMC_CMD   */
+	{EMMC_DATA0, (PTU | IEN | M0)}, /*  EMMC_DATA0 */
+	{EMMC_DATA1, (PTU | IEN | M0)}, /*  EMMC_DATA1 */
+	{EMMC_DATA2, (PTU | IEN | M0)}, /*  EMMC_DATA2 */
+	{EMMC_DATA3, (PTU | IEN | M0)}, /*  EMMC_DATA3 */
+	{EMMC_DATA4, (PTU | IEN | M0)}, /*  EMMC_DATA4 */
+	{EMMC_DATA5, (PTU | IEN | M0)}, /*  EMMC_DATA5 */
+	{EMMC_DATA6, (PTU | IEN | M0)}, /*  EMMC_DATA6 */
+	{EMMC_DATA7, (PTU | IEN | M0)}, /*  EMMC_DATA7 */
+	{SDCARD_CLK, (PTU | IEN | M0)}, /*  SDCARD_CLK  */
+	{SDCARD_CMD, (PTU | IEN | M0)}, /*  SDCARD_CMD  */
+	{SDCARD_DATA0, (PTU | IEN | M0)}, /*  SDCARD_DATA0*/
+	{SDCARD_DATA1, (PTU | IEN | M0)}, /*  SDCARD_DATA1*/
+	{SDCARD_DATA2, (PTU | IEN | M0)}, /*  SDCARD_DATA2*/
+	{SDCARD_DATA3, (PTU | IEN | M0)}, /*  SDCARD_DATA3*/
+	{UART3_RX_IRRX, (PTU | IEN | M0)}, /*  UART3_RX_IRRX    */
+	{UART3_TX_IRTX, (M0)},    /*  UART3_TX_IRTX    */
 
 };
 
 const struct pad_conf_entry wkup_padconf_array_essential[] = {
 
-{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
-{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
-{PAD1_SYS_32K, (IEN | M0)}	 /* sys_32k */
+	{SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */
+	{SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */
+	{SYS_32K, (IEN | M0)}, /*  SYS_32K     */
 
 };
 
 const struct pad_conf_entry core_padconf_array_non_essential[] = {
-	{GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* gpio_32 */
-	{GPMC_AD9, (PTU | IEN | M3)},					/* gpio_33 */
-	{GPMC_AD10, (PTU | IEN | M3)},					/* gpio_34 */
-	{GPMC_AD11, (PTU | IEN | M3)},					/* gpio_35 */
-	{GPMC_AD12, (PTU | IEN | M3)},					/* gpio_36 */
-	{GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_37 */
-	{GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_38 */
-	{GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_39 */
-	{GPMC_A16, (M3)},						/* gpio_40 */
-	{GPMC_A17, (PTD | M3)},						/* gpio_41 */
-	{GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row6 */
-	{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row7 */
-	{GPMC_A20, (IEN | M3)},						/* gpio_44 */
-	{GPMC_A21, (M3)},						/* gpio_45 */
-	{GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col6 */
-	{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col7 */
-	{GPMC_A24, (PTD | M3)},						/* gpio_48 */
-	{GPMC_A25, (PTD | M3)},						/* gpio_49 */
-	{GPMC_NCS0, (M3)},						/* gpio_50 */
-	{GPMC_NCS1, (IEN | M3)},					/* gpio_51 */
-	{GPMC_NCS2, (IEN | M3)},					/* gpio_52 */
-	{GPMC_NCS3, (IEN | M3)},					/* gpio_53 */
-	{GPMC_NWP, (M3)},						/* gpio_54 */
-	{GPMC_CLK, (PTD | M3)},						/* gpio_55 */
-	{GPMC_NADV_ALE, (M3)},						/* gpio_56 */
-	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
-	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
-	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
-	{GPMC_WAIT1, (IEN | M3)},					/* gpio_62 */
-	{C2C_DATA11, (PTD | M3)},					/* gpio_100 */
-	{C2C_DATA12, (M1)},						/* dsi1_te0 */
-	{C2C_DATA13, (PTD | M3)},					/* gpio_102 */
-	{C2C_DATA14, (M1)},						/* dsi2_te0 */
-	{C2C_DATA15, (PTD | M3)},					/* gpio_104 */
-	{HDMI_HPD, (M0)},						/* hdmi_hpd */
-	{HDMI_CEC, (M0)},						/* hdmi_cec */
-	{HDMI_DDC_SCL, (PTU | M0)},					/* hdmi_ddc_scl */
-	{HDMI_DDC_SDA, (PTU | IEN | M0)},				/* hdmi_ddc_sda */
-	{CSI21_DX0, (IEN | M0)},					/* csi21_dx0 */
-	{CSI21_DY0, (IEN | M0)},					/* csi21_dy0 */
-	{CSI21_DX1, (IEN | M0)},					/* csi21_dx1 */
-	{CSI21_DY1, (IEN | M0)},					/* csi21_dy1 */
-	{CSI21_DX2, (IEN | M0)},					/* csi21_dx2 */
-	{CSI21_DY2, (IEN | M0)},					/* csi21_dy2 */
-	{CSI21_DX3, (PTD | M7)},					/* csi21_dx3 */
-	{CSI21_DY3, (PTD | M7)},					/* csi21_dy3 */
-	{CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dx4 */
-	{CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)},		/* csi21_dy4 */
-	{CSI22_DX0, (IEN | M0)},					/* csi22_dx0 */
-	{CSI22_DY0, (IEN | M0)},					/* csi22_dy0 */
-	{CSI22_DX1, (IEN | M0)},					/* csi22_dx1 */
-	{CSI22_DY1, (IEN | M0)},					/* csi22_dy1 */
-	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
-	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
-	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
-	{USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cawake */
-	{USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cadata */
-	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caflag */
-	{USBB1_ULPITLL_NXT, (OFF_EN | M1)},				/* hsi1_acready */
-	{USBB1_ULPITLL_DAT0, (OFF_EN | M1)},				/* hsi1_acwake */
-	{USBB1_ULPITLL_DAT1, (OFF_EN | M1)},				/* hsi1_acdata */
-	{USBB1_ULPITLL_DAT2, (OFF_EN | M1)},				/* hsi1_acflag */
-	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caready */
-	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
-	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
-	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
-	{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat7 */
-	{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_data */
-	{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
-	{USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
-	{USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
-	{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_clkx */
-	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
-	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
-	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
-	{ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_clkx */
-	{ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp1_dr */
-	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
-	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
-	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */
-	{ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_dl_data */
-	{ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_frame */
-	{ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_lb_clk */
-	{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_clks */
-	{ABE_DMIC_CLK1, (M0)},						/* abe_dmic_clk1 */
-	{ABE_DMIC_DIN1, (IEN | M0)},					/* abe_dmic_din1 */
-	{ABE_DMIC_DIN2, (IEN | M0)},					/* abe_dmic_din2 */
-	{ABE_DMIC_DIN3, (IEN | M0)},					/* abe_dmic_din3 */
-	{UART2_CTS, (PTU | IEN | M0)},					/* uart2_cts */
-	{UART2_RTS, (M0)},						/* uart2_rts */
-	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
-	{UART2_TX, (M0)},						/* uart2_tx */
-	{HDQ_SIO, (M3)},						/* gpio_127 */
-	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
-	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
-	{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_simo */
-	{MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi1_cs0 */
-	{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)},	/* mcspi1_cs1 */
-	{MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_139 */
-	{MCSPI1_CS3, (PTU | IEN | M3)},					/* gpio_140 */
-	{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* sdmmc5_clk */
-	{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_cmd */
-	{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat0 */
-	{SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat1 */
-	{SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat2 */
-	{SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* sdmmc5_dat3 */
-	{MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_clk */
-	{MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_simo */
-	{MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi4_somi */
-	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
-	{UART4_RX, (IEN | M0)},						/* uart4_rx */
-	{UART4_TX, (M0)},						/* uart4_tx */
-	{USBB2_ULPITLL_CLK, (PTD | IEN | M3)},				/* gpio_157 */
-	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
-	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
-	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */
-	{USBB2_ULPITLL_DAT0, (IEN | M5)},				/* dispc2_data20 */
-	{USBB2_ULPITLL_DAT1, (IEN | M5)},				/* dispc2_data19 */
-	{USBB2_ULPITLL_DAT2, (IEN | M5)},				/* dispc2_data18 */
-	{USBB2_ULPITLL_DAT3, (IEN | M5)},				/* dispc2_data15 */
-	{USBB2_ULPITLL_DAT4, (IEN | M5)},				/* dispc2_data14 */
-	{USBB2_ULPITLL_DAT5, (IEN | M5)},				/* dispc2_data13 */
-	{USBB2_ULPITLL_DAT6, (IEN | M5)},				/* dispc2_data12 */
-	{USBB2_ULPITLL_DAT7, (IEN | M5)},				/* dispc2_data11 */
-	{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_169 */
-	{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_170 */
-	{UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col0 */
-	{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col1 */
-	{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col2 */
-	{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col3 */
-	{UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col4 */
-	{UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col5 */
-	{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row0 */
-	{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row1 */
-	{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row2 */
-	{UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row3 */
-	{UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row4 */
-	{UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row5 */
-	{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},	/* usba0_otg_ce */
-	{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
-	{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
-	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
-	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
-	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
-	{SYS_NIRQ2, (M7)},						/* sys_nirq2 */
-	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
-	{SYS_BOOT1, (M3)},						/* gpio_185 */
-	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
-	{SYS_BOOT3, (PTD | IEN | M3)},					/* gpio_187 */
-	{SYS_BOOT4, (M3)},						/* gpio_188 */
-	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
-	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */
-	{DPM_EMU1, (IEN | M0)},						/* dpm_emu1 */
-	{DPM_EMU2, (IEN | M0)},						/* dpm_emu2 */
-	{DPM_EMU3, (IEN | M5)},						/* dispc2_data10 */
-	{DPM_EMU4, (IEN | M5)},						/* dispc2_data9 */
-	{DPM_EMU5, (IEN | M5)},						/* dispc2_data16 */
-	{DPM_EMU6, (IEN | M5)},						/* dispc2_data17 */
-	{DPM_EMU7, (IEN | M5)},						/* dispc2_hsync */
-	{DPM_EMU8, (IEN | M5)},						/* dispc2_pclk */
-	{DPM_EMU9, (IEN | M5)},						/* dispc2_vsync */
-	{DPM_EMU10, (IEN | M5)},					/* dispc2_de */
-	{DPM_EMU11, (IEN | M5)},					/* dispc2_data8 */
-	{DPM_EMU12, (IEN | M5)},					/* dispc2_data7 */
-	{DPM_EMU13, (IEN | M5)},					/* dispc2_data6 */
-	{DPM_EMU14, (IEN | M5)},					/* dispc2_data5 */
-	{DPM_EMU15, (IEN | M5)},					/* dispc2_data4 */
-	{DPM_EMU16, (M3)},						/* gpio_27 */
-	{DPM_EMU17, (IEN | M5)},					/* dispc2_data2 */
-	{DPM_EMU18, (IEN | M5)},					/* dispc2_data1 */
-	{DPM_EMU19, (IEN | M5)},					/* dispc2_data0 */
-	{I2C1_SCL, (PTU | IEN | M0)},				/* i2c1_scl */
-	{I2C1_SDA, (PTU | IEN | M0)},				/* i2c1_sda */
-	{I2C2_SCL, (PTU | IEN | M0)},				/* i2c2_scl */
-	{I2C2_SDA, (PTU | IEN | M0)},				/* i2c2_sda */
-	{I2C3_SCL, (PTU | IEN | M0)},				/* i2c3_scl */
-	{I2C3_SDA, (PTU | IEN | M0)},				/* i2c3_sda */
-	{I2C4_SCL, (PTU | IEN | M0)},				/* i2c4_scl */
-	{I2C4_SDA, (PTU | IEN | M0)}				/* i2c4_sda */
+
+	{C2C_DATAIN0, (IEN | M0)},    /*  C2C_DATAIN0   */
+	{C2C_DATAIN1, (IEN | M0)},    /*  C2C_DATAIN1   */
+	{C2C_DATAIN2, (IEN | M0)},    /*  C2C_DATAIN2   */
+	{C2C_DATAIN3, (IEN | M0)},    /*  C2C_DATAIN3   */
+	{C2C_DATAIN4, (IEN | M0)},    /*  C2C_DATAIN4   */
+	{C2C_DATAIN5, (IEN | M0)},    /*  C2C_DATAIN5   */
+	{C2C_DATAIN6, (IEN | M0)},    /*  C2C_DATAIN6   */
+	{C2C_DATAIN7, (IEN | M0)},    /*  C2C_DATAIN7   */
+	{C2C_CLKIN1,  (IEN | M0)},    /*  C2C_CLKIN1    */
+	{C2C_CLKIN0,  (IEN | M0)},    /*  C2C_CLKIN0    */
+	{C2C_CLKOUT0, (M0)},    /*  C2C_CLKOUT0   */
+	{C2C_CLKOUT1, (M0)},    /*  C2C_CLKOUT1   */
+	{C2C_DATAOUT0, (M0)},    /*  C2C_DATAOUT0  */
+	{C2C_DATAOUT1, (M0)},    /*  C2C_DATAOUT1  */
+	{C2C_DATAOUT2, (M0)},    /*  C2C_DATAOUT2  */
+	{C2C_DATAOUT3, (M0)},    /*  C2C_DATAOUT3  */
+	{C2C_DATAOUT4, (M0)},    /*  C2C_DATAOUT4  */
+	{C2C_DATAOUT5, (M0)},    /*  C2C_DATAOUT5  */
+	{C2C_DATAOUT6, (M0)},    /*  C2C_DATAOUT6  */
+	{C2C_DATAOUT7, (M0)},    /*  C2C_DATAOUT7  */
+	{C2C_DATA8, (IEN | M0)},    /*  C2C_DATA8     */
+	{C2C_DATA9, (IEN | M0)},    /*  C2C_DATA9     */
+	{C2C_DATA10, (IEN | M0)},    /*  C2C_DATA10    */
+	{C2C_DATA11, (IEN | M0)},    /*  C2C_DATA11    */
+	{C2C_DATA12, (IEN | M0)},    /*  C2C_DATA12    */
+	{C2C_DATA13, (IEN | M0)},    /*  C2C_DATA13    */
+	{C2C_DATA14, (IEN | M0)},    /*  C2C_DATA14    */
+	{C2C_DATA15, (IEN | M0)},    /*  C2C_DATA15    */
+	{LLIB_WAKEREQOUT, (PTU | IEN | M6)},    /*  GPIO2_32      */
+	{LLIA_WAKEREQOUT, (M1)},    /*  C2C_WAKEREQOUT */
+	{HSI1_ACREADY, (PTD | M6)},    /*  GPIO3_64  */
+	{HSI1_CAREADY, (PTD | M6)},    /*  GPIO3_65  */
+	{HSI1_ACWAKE,  (PTD | IEN | M6)},    /*  GPIO3_66  */
+	{HSI1_CAWAKE,  (PTU | IEN | M6)},    /*  GPIO3_67  */
+	{HSI1_ACFLAG,  (PTD | IEN | M6)},    /*  GPIO3_68  */
+	{HSI1_ACDATA,  (PTD | M6)},    /*  GPIO3_69  */
+	{HSI1_CAFLAG,  (M6)},    /*  GPIO3_70  */
+	{HSI1_CADATA,  (M6)},    /*  GPIO3_71  */
+	{UART1_TX, (M0)},    /*  UART1_TX  */
+	{UART1_CTS, (PTU | IEN | M0)},    /*  UART1_CTS */
+	{UART1_RX, (PTU | IEN | M0)},    /*  UART1_RX  */
+	{UART1_RTS, (M0)},    /*  UART1_RTS */
+	{HSI2_CAREADY, (IEN | M0)},    /*  HSI2_CAREADY */
+	{HSI2_ACREADY, (OFF_EN | M0)},    /*  HSI2_ACREADY */
+	{HSI2_CAWAKE, (IEN | PTD | M0)},    /*  HSI2_CAWAKE  */
+	{HSI2_ACWAKE, (M0)},    /*  HSI2_ACWAKE  */
+	{HSI2_CAFLAG, (IEN | PTD | M0)},    /*  HSI2_CAFLAG  */
+	{HSI2_CADATA, (IEN | PTD | M0)},    /*  HSI2_CADATA  */
+	{HSI2_ACFLAG, (M0)},    /*  HSI2_ACFLAG  */
+	{HSI2_ACDATA, (M0)},    /*  HSI2_ACDATA  */
+	{UART2_RTS, (IEN | M1)},    /*  MCSPI3_SOMI  */
+	{UART2_CTS, (IEN | M1)},    /*  MCSPI3_CS0   */
+	{UART2_RX, (IEN | M1)},    /*  MCSPI3_SIMO  */
+	{UART2_TX, (IEN | M1)},    /*  MCSPI3_CLK   */
+	{USBB1_HSIC_STROBE, (PTU | IEN | M0)},    /*  USBB1_HSIC_STROBE */
+	{USBB1_HSIC_DATA, (PTU | IEN | M0)},    /*  USBB1_HSIC_DATA */
+	{USBB2_HSIC_STROBE, (PTU | IEN | M0)},    /*  USBB2_HSIC_STROBE */
+	{USBB2_HSIC_DATA, (PTU | IEN | M0)},    /*  USBB2_HSIC_DATA  */
+	{TIMER10_PWM_EVT, (IEN | M0)},    /*  TIMER10_PWM_EVT  */
+	{DSIPORTA_TE0, (IEN | M0)},    /*  DSIPORTA_TE0     */
+	{DSIPORTA_LANE0X, (IEN | M0)},    /*  DSIPORTA_LANE0X  */
+	{DSIPORTA_LANE0Y, (IEN | M0)},    /*  DSIPORTA_LANE0Y  */
+	{DSIPORTA_LANE1X, (IEN | M0)},    /*  DSIPORTA_LANE1X  */
+	{DSIPORTA_LANE1Y, (IEN | M0)},    /*  DSIPORTA_LANE1Y  */
+	{DSIPORTA_LANE2X, (IEN | M0)},    /*  DSIPORTA_LANE2X  */
+	{DSIPORTA_LANE2Y, (IEN | M0)},    /*  DSIPORTA_LANE2Y  */
+	{DSIPORTA_LANE3X, (IEN | M0)},    /*  DSIPORTA_LANE3X  */
+	{DSIPORTA_LANE3Y, (IEN | M0)},    /*  DSIPORTA_LANE3Y  */
+	{DSIPORTA_LANE4X, (IEN | M0)},    /*  DSIPORTA_LANE4X  */
+	{DSIPORTA_LANE4Y, (IEN | M0)},    /*  DSIPORTA_LANE4Y  */
+	{TIMER9_PWM_EVT, (IEN | M0)},    /*  TIMER9_PWM_EVT   */
+	{DSIPORTC_TE0, (IEN | M0)},    /*  DSIPORTC_TE0     */
+	{DSIPORTC_LANE0X, (IEN | M0)},    /*  DSIPORTC_LANE0X  */
+	{DSIPORTC_LANE0Y, (IEN | M0)},    /*  DSIPORTC_LANE0Y  */
+	{DSIPORTC_LANE1X, (IEN | M0)},    /*  DSIPORTC_LANE1X  */
+	{DSIPORTC_LANE1Y, (IEN | M0)},    /*  DSIPORTC_LANE1Y  */
+	{DSIPORTC_LANE2X, (IEN | M0)},    /*  DSIPORTC_LANE2X  */
+	{DSIPORTC_LANE2Y, (IEN | M0)},    /*  DSIPORTC_LANE2Y  */
+	{DSIPORTC_LANE3X, (IEN | M0)},    /*  DSIPORTC_LANE3X  */
+	{DSIPORTC_LANE3Y, (IEN | M0)},    /*  DSIPORTC_LANE3Y  */
+	{DSIPORTC_LANE4X, (IEN | M0)},    /*  DSIPORTC_LANE4X  */
+	{DSIPORTC_LANE4Y, (IEN | M0)},    /*  DSIPORTC_LANE4Y  */
+	{RFBI_HSYNC0, (M4)},    /*  KBD_COL5   */
+	{RFBI_TE_VSYNC0, (PTD | M6)},    /*  GPIO6_161  */
+	{RFBI_RE, (M4)},    /*  KBD_COL4   */
+	{RFBI_A0, (PTD | IEN | M6)},    /*  GPIO6_165  */
+	{RFBI_DATA8, (M4)},    /*  KBD_COL3   */
+	{RFBI_DATA9, (PTD | M6)},    /*  GPIO6_175  */
+	{RFBI_DATA10, (PTD | M6)},    /*  GPIO6_176  */
+	{RFBI_DATA11, (PTD | M6)},    /*  GPIO6_177  */
+	{RFBI_DATA12, (PTD | M6)},    /*  GPIO6_178  */
+	{RFBI_DATA13, (PTU | IEN | M6)},    /*  GPIO6_179  */
+	{RFBI_DATA14, (M4)},    /*  KBD_COL7   */
+	{RFBI_DATA15, (M4)},    /*  KBD_COL6   */
+	{GPIO6_182, (M6)},    /*  GPIO6_182  */
+	{GPIO6_183, (PTD | M6)},    /*  GPIO6_183  */
+	{GPIO6_184, (M4)},    /*  KBD_COL2   */
+	{GPIO6_185, (PTD | IEN | M6)},    /*  GPIO6_185  */
+	{GPIO6_186, (PTD | M6)},    /*  GPIO6_186  */
+	{GPIO6_187, (PTU | IEN | M4)},    /*  KBD_ROW2   */
+	{RFBI_DATA0, (PTD | M6)},    /*  GPIO6_166  */
+	{RFBI_DATA1, (PTD | M6)},    /*  GPIO6_167  */
+	{RFBI_DATA2, (PTD | M6)},    /*  GPIO6_168  */
+	{RFBI_DATA3, (PTD | IEN | M6)},    /*  GPIO6_169  */
+	{RFBI_DATA4, (IEN | M6)},    /*  GPIO6_170  */
+	{RFBI_DATA5, (IEN | M6)},    /*  GPIO6_171  */
+	{RFBI_DATA6, (PTD | M6)},    /*  GPIO6_172  */
+	{RFBI_DATA7, (PTD | M6)},    /*  GPIO6_173  */
+	{RFBI_CS0, (PTD | IEN | M6)},    /*  GPIO6_163  */
+	{RFBI_WE, (PTD | M6)},    /*  GPIO6_162  */
+	{MCSPI2_CS0, (M0)},    /*  MCSPI2_CS0 */
+	{MCSPI2_CLK, (IEN | M0)},    /*  MCSPI2_CLK */
+	{MCSPI2_SIMO, (IEN | M0)},    /*  MCSPI2_SIMO*/
+	{MCSPI2_SOMI, (PTU | IEN | M0)},    /*  MCSPI2_SOMI*/
+	{I2C4_SCL, (IEN | M0)},    /*  I2C4_SCL   */
+	{I2C4_SDA, (IEN | M0)},    /*  I2C4_SDA   */
+	{HDMI_CEC, (IEN | M0)},    /*  HDMI_CEC   */
+	{HDMI_HPD, (PTD | IEN | M0)},    /*  HDMI_HPD   */
+	{HDMI_DDC_SCL, (IEN | M0)},    /*  HDMI_DDC_SCL */
+	{HDMI_DDC_SDA, (IEN | M0)},    /*  HDMI_DDC_SDA */
+	{CSIPORTA_LANE0X, (IEN | M0)},    /*  CSIPORTA_LANE0X  */
+	{CSIPORTA_LANE0Y, (IEN | M0)},    /*  CSIPORTA_LANE0Y  */
+	{CSIPORTA_LANE1Y, (IEN | M0)},    /*  CSIPORTA_LANE1Y  */
+	{CSIPORTA_LANE1X, (IEN | M0)},    /*  CSIPORTA_LANE1X  */
+	{CSIPORTA_LANE2Y, (IEN | M0)},    /*  CSIPORTA_LANE2Y  */
+	{CSIPORTA_LANE2X, (IEN | M0)},    /*  CSIPORTA_LANE2X  */
+	{CSIPORTA_LANE3X, (IEN | M0)},    /*  CSIPORTA_LANE3X  */
+	{CSIPORTA_LANE3Y, (IEN | M0)},    /*  CSIPORTA_LANE3Y  */
+	{CSIPORTA_LANE4X, (IEN | M0)},    /*  CSIPORTA_LANE4X  */
+	{CSIPORTA_LANE4Y, (IEN | M0)},    /*  CSIPORTA_LANE4Y  */
+	{CSIPORTB_LANE0X, (IEN | M0)},    /*  CSIPORTB_LANE0X  */
+	{CSIPORTB_LANE0Y, (IEN | M0)},    /*  CSIPORTB_LANE0Y  */
+	{CSIPORTB_LANE1Y, (IEN | M0)},    /*  CSIPORTB_LANE1Y  */
+	{CSIPORTB_LANE1X, (IEN | M0)},    /*  CSIPORTB_LANE1X  */
+	{CSIPORTB_LANE2Y, (IEN | M0)},    /*  CSIPORTB_LANE2Y  */
+	{CSIPORTB_LANE2X, (IEN | M0)},    /*  CSIPORTB_LANE2X  */
+	{CSIPORTC_LANE0Y, (IEN | M0)},    /*  CSIPORTC_LANE0Y  */
+	{CSIPORTC_LANE0X, (IEN | M0)},    /*  CSIPORTC_LANE0X  */
+	{CSIPORTC_LANE1Y, (IEN | M0)},    /*  CSIPORTC_LANE1Y  */
+	{CSIPORTC_LANE1X, (IEN | M0)},    /*  CSIPORTC_LANE1X  */
+	{CAM_SHUTTER, (M0)},    /*  CAM_SHUTTER      */
+	{CAM_STROBE, (M0)},    /*  CAM_STROBE       */
+	{CAM_GLOBALRESET, (IEN | M0)},    /*  CAM_GLOBALRESET  */
+	{TIMER11_PWM_EVT, (PTD | M6)},    /*  GPIO8_227  */
+	{TIMER5_PWM_EVT, (PTD | M6)},    /*  GPIO8_228  */
+	{TIMER6_PWM_EVT, (PTD | M6)},    /*  GPIO8_229  */
+	{TIMER8_PWM_EVT,      (PTU | M6)},    /*  GPIO8_230  */
+	{I2C3_SCL, (IEN | M0)},    /*  I2C3_SCL   */
+	{I2C3_SDA, (IEN | M0)},    /*  I2C3_SDA   */
+	{GPIO8_233, (IEN | M2)},    /*  TIMER8_PWM_EVT   */
+	{ABE_CLKS, (IEN | M0)},    /*  ABE_CLKS  */
+	{ABEDMIC_DIN1, (IEN | M0)},    /*  ABEDMIC_DIN1 */
+	{ABEDMIC_DIN2, (IEN | M0)},    /*  ABEDMIC_DIN2 */
+	{ABEDMIC_DIN3, (IEN | M0)},    /*  ABEDMIC_DIN3 */
+	{ABEDMIC_CLK1, (M0)},    /*  ABEDMIC_CLK1 */
+	{ABEDMIC_CLK2, (IEN | M1)},    /*  ABEMCBSP1_FSX */
+	{ABEDMIC_CLK3, (M1)},    /*  ABEMCBSP1_DX  */
+	{ABESLIMBUS1_CLOCK, (IEN | M1)},    /*  ABEMCBSP1_CLKX   */
+	{ABESLIMBUS1_DATA, (IEN | M1)},    /*  ABEMCBSP1_DR */
+	{ABEMCBSP2_DR, (IEN | M0)},    /*  ABEMCBSP2_DR */
+	{ABEMCBSP2_DX, (M0)},    /*  ABEMCBSP2_DX */
+	{ABEMCBSP2_FSX, (IEN | M0)},    /*  ABEMCBSP2_FSX  */
+	{ABEMCBSP2_CLKX, (IEN | M0)},    /*  ABEMCBSP2_CLKX */
+	{ABEMCPDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},    /*  ABEMCPDM_UL_DATA */
+	{ABEMCPDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},    /*  ABEMCPDM_DL_DATA */
+	{ABEMCPDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},    /*  ABEMCPDM_FRAME   */
+	{ABEMCPDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},    /*  ABEMCPDM_LB_CLK  */
+	{WLSDIO_CLK, (PTU | IEN | M0)},    /*  WLSDIO_CLK  */
+	{WLSDIO_CMD, (PTU | IEN | M0)},    /*  WLSDIO_CMD  */
+	{WLSDIO_DATA0, (PTU | IEN | M0)},    /*  WLSDIO_DATA0*/
+	{WLSDIO_DATA1, (PTU | IEN | M0)},    /*  WLSDIO_DATA1*/
+	{WLSDIO_DATA2, (PTU | IEN | M0)},    /*  WLSDIO_DATA2*/
+	{WLSDIO_DATA3, (PTU | IEN | M0)},    /*  WLSDIO_DATA3*/
+	{UART5_RX, (PTU | IEN | M0)},    /*  UART5_RX    */
+	{UART5_TX, (M0)},    /*  UART5_TX    */
+	{UART5_CTS, (PTU | IEN | M0)},    /*  UART5_CTS   */
+	{UART5_RTS, (M0)},    /*  UART5_RTS   */
+	{I2C2_SCL, (IEN | M0)},    /*  I2C2_SCL    */
+	{I2C2_SDA, (IEN | M0)},    /*  I2C2_SDA    */
+	{MCSPI1_CLK, (M6)},    /*  GPIO5_140   */
+	{MCSPI1_SOMI, (IEN | M6)},    /*  GPIO5_141   */
+	{MCSPI1_SIMO, (PTD | M6)},    /*  GPIO5_142   */
+	{MCSPI1_CS0, (PTD | M6)},    /*  GPIO5_143   */
+	{MCSPI1_CS1, (PTD | IEN | M6)},    /*  GPIO5_144   */
+	{I2C5_SCL, (IEN | M0)},    /*  I2C5_SCL    */
+	{I2C5_SDA, (IEN | M0)},    /*  I2C5_SDA    */
+	{PERSLIMBUS2_CLOCK, (PTD | M6)},    /*  GPIO5_145   */
+	{PERSLIMBUS2_DATA, (PTD | IEN | M6)},    /*  GPIO5_146   */
+	{UART6_TX, (PTU | IEN | M6)},    /*  GPIO5_149   */
+	{UART6_RX, (PTU | IEN | M6)},    /*  GPIO5_150   */
+	{UART6_CTS, (PTU | IEN | M6)},    /*  GPIO5_151   */
+	{UART6_RTS, (PTU | M0)},    /*  UART6_RTS   */
+	{UART3_CTS_RCTX, (PTU | IEN | M6)},    /*  GPIO5_153   */
+	{UART3_RTS_IRSD, (PTU | IEN | M1)},    /*  HDQ_SIO     */
+	{USBB3_HSIC_STROBE, (PTU | IEN | M0)},    /*  USBB3_HSIC_STROBE*/
+	{USBB3_HSIC_DATA, (PTU | IEN | M0)},    /*  USBB3_HSIC_DATA  */
+	{USBD0_HS_DP, (IEN | M0)},    /*  USBD0_HS_DP */
+	{USBD0_HS_DM, (IEN | M0)},    /*  USBD0_HS_DM */
+	{USBD0_SS_RX, (IEN | M0)},    /*  USBD0_SS_RX */
+	{I2C1_PMIC_SCL, (PTU | IEN | M0)},    /*  I2C1_PMIC_SCL  */
+	{I2C1_PMIC_SDA, (PTU | IEN | M0)},    /*  I2C1_PMIC_SDA  */
+
 };
 
 const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
-	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
-	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
-	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
-	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
-	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
-	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
-	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
-	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
-	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
-	{PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)},	/* # */
-	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
-	{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},	/* # */
-	{PAD0_FREF_CLK4_OUT, (M0)},		/* # */
-	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
-	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
-	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
-	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
-	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
-	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
-	{PAD1_FREF_CLK3_REQ, (M3)},		/* gpio_wk30 */
-	{PAD1_FREF_CLK4_REQ, (M3)},		/* gpio_wk7 */
-	{PAD0_FREF_CLK4_OUT, (M3)},		/* gpio_wk8 */
+
+/*
+ * This pad keeps C2C Module always enabled.
+ * Putting this in safe mode do not cause the issue.
+ * C2C driver could enable this mux setting if needed.
+ */
+	{LLIA_WAKEREQIN, (M7)},    /*  SAFE MODE  */
+	{LLIB_WAKEREQIN, (M7)},    /*  SAFE MODE  */
+	{DRM_EMU0, (PTU | IEN | M0)},    /*  DRM_EMU0    */
+	{DRM_EMU1, (PTU | IEN | M0)},    /*  DRM_EMU1    */
+	{JTAG_NTRST, (IEN | M0)},    /*  JTAG_NTRST  */
+	{JTAG_TCK, (IEN | M0)},    /*  JTAG_TCK    */
+	{JTAG_RTCK, (M0)},    /*  JTAG_RTCK   */
+	{JTAG_TMSC, (IEN | M0)},    /*  JTAG_TMSC   */
+	{JTAG_TDI, (IEN | M0)},    /*  JTAG_TDI    */
+	{JTAG_TDO, (M0)},    /*  JTAG_TDO    */
+	{FREF_CLK_IOREQ, (IEN | M0)},    /*  FREF_CLK_IOREQ */
+	{FREF_CLK0_OUT, (M0)},    /*  FREF_CLK0_OUT  */
+	{FREF_CLK1_OUT, (M0)},    /*  FREF_CLK1_OUT  */
+	{FREF_CLK2_OUT, (M0)},    /*  FREF_CLK2_OUT  */
+	{FREF_CLK2_REQ, (PTU | IEN | M6)},    /*  GPIO1_WK9      */
+	{FREF_CLK1_REQ, (PTD | IEN | M6)},    /*  GPIO1_WK8      */
+	{SYS_NRESPWRON, (IEN | M0)},    /*  SYS_NRESPWRON  */
+	{SYS_NRESWARM, (PTU | IEN | M0)},    /*  SYS_NRESWARM   */
+	{SYS_PWR_REQ, (M0)},    /*  SYS_PWR_REQ    */
+	{SYS_NIRQ1, (PTU | IEN | M0)},    /*  SYS_NIRQ1      */
+	{SYS_NIRQ2, (PTU | IEN | M0)},    /*  SYS_NIRQ2      */
+	{SYS_BOOT0, (IEN | M0)},    /*  SYS_BOOT0      */
+	{SYS_BOOT1, (IEN | M0)},    /*  SYS_BOOT1      */
+	{SYS_BOOT2, (IEN | M0)},    /*  SYS_BOOT2      */
+	{SYS_BOOT3, (IEN | M0)},    /*  SYS_BOOT3      */
+	{SYS_BOOT4, (IEN | M0)},    /*  SYS_BOOT4      */
+	{SYS_BOOT5, (IEN | M0)},    /*  SYS_BOOT5      */
+
 };
 
 #endif /* _EVM4430_MUX_DATA_H */
diff --git a/board/ti/omap730p2/omap730p2.c b/board/ti/omap730p2/omap730p2.c
index 954ced5efe..36204b2c88 100644
--- a/board/ti/omap730p2/omap730p2.c
+++ b/board/ti/omap730p2/omap730p2.c
@@ -129,12 +129,6 @@ int board_init (void)
 	return 0;
 }
 
-int misc_init_r (void)
-{
-	/* currently empty */
-	return (0);
-}
-
 /******************************
  Routine:
  Description:
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index ca4b8b35eb..ee82771b08 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -179,7 +179,7 @@ void set_muxconf_regs_non_essential(void)
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
-	omap_mmc_init(0);
+	omap_mmc_init(0, 0, 0);
 	return 0;
 }
 #endif
diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h
index 5b66a14242..dc8b3886c2 100644
--- a/board/ti/panda/panda_mux_data.h
+++ b/board/ti/panda/panda_mux_data.h
@@ -76,7 +76,7 @@ const struct pad_conf_entry wkup_padconf_array_essential[] = {
 
 const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
 
-{PAD1_FREF_CLK4_REQ, (PTU | M7)}, /* gpio_wk7 for TPS: safe mode + pull up */
+{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */
 
 };
 
@@ -168,10 +168,10 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{ABE_DMIC_DIN1, (IEN | M0)},					/* abe_dmic_din1 */
 	{ABE_DMIC_DIN2, (PTU | IEN | M3)},				/* gpio_121 */
 	{ABE_DMIC_DIN3, (IEN | M0)},					/* abe_dmic_din3 */
-	{UART2_CTS, (PTU | IEN | M0)},					/* uart2_cts */
-	{UART2_RTS, (M0)},						/* uart2_rts */
-	{UART2_RX, (PTU | IEN | M0)},					/* uart2_rx */
-	{UART2_TX, (M0)},						/* uart2_tx */
+	{UART2_CTS, (PTU | IEN | M7)},					/* uart2_cts */
+	{UART2_RTS, (M7)},						/* uart2_rts */
+	{UART2_RX, (PTU | IEN | M7)},					/* uart2_rx */
+	{UART2_TX, (M7)},						/* uart2_tx */
 	{HDQ_SIO, (M3)},						/* gpio_127 */
 	{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_clk */
 	{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* mcspi1_somi */
diff --git a/board/ti/sdp3430/sdp.c b/board/ti/sdp3430/sdp.c
index d73f501819..9a1c012145 100644
--- a/board/ti/sdp3430/sdp.c
+++ b/board/ti/sdp3430/sdp.c
@@ -209,7 +209,7 @@ void set_muxconf_regs(void)
 #ifdef CONFIG_GENERIC_MMC
 int board_mmc_init(bd_t *bis)
 {
-	omap_mmc_init(0);
+	omap_mmc_init(0, 0, 0);
 	return 0;
 }
 #endif
diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c
index 9ae9e2c602..982c771a73 100644
--- a/board/ti/sdp4430/sdp.c
+++ b/board/ti/sdp4430/sdp.c
@@ -108,8 +108,8 @@ void set_muxconf_regs_non_essential(void)
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 int board_mmc_init(bd_t *bis)
 {
-	omap_mmc_init(0);
-	omap_mmc_init(1);
+	omap_mmc_init(0, 0, 0);
+	omap_mmc_init(1, 0, 0);
 	return 0;
 }
 #endif
diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h
index 0a20968978..6140b999ef 100644
--- a/board/ti/sdp4430/sdp4430_mux_data.h
+++ b/board/ti/sdp4430/sdp4430_mux_data.h
@@ -67,7 +67,7 @@ const struct pad_conf_entry wkup_padconf_array_essential[] = {
 
 const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
 
-{PAD1_FREF_CLK4_REQ, (PTU | M7)}, /* gpio_wk7 for TPS: safe mode + pull up */
+{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */
 
 };
 
diff --git a/board/timll/devkit3250/Makefile b/board/timll/devkit3250/Makefile
new file mode 100644
index 0000000000..ea7827c80d
--- /dev/null
+++ b/board/timll/devkit3250/Makefile
@@ -0,0 +1,44 @@
+#
+# Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA  02110-1301, USA.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= devkit3250.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/timll/devkit3250/devkit3250.c b/board/timll/devkit3250/devkit3250.c
new file mode 100644
index 0000000000..6b0ec80fcd
--- /dev/null
+++ b/board/timll/devkit3250/devkit3250.c
@@ -0,0 +1,65 @@
+/*
+ * Embest/Timll DevKit3250 board support
+ *
+ * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/emc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
+
+int board_early_init_f(void)
+{
+	lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params  = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_SYS_FLASH_CFI
+	/* Use 16-bit memory interface for NOR Flash */
+	emc->stat[0].config	= EMC_STAT_CONFIG_PB | EMC_STAT_CONFIG_16BIT;
+
+	/* Change the NOR timings to optimum value to get maximum bandwidth */
+	emc->stat[0].waitwen	= EMC_STAT_WAITWEN(1);
+	emc->stat[0].waitoen	= EMC_STAT_WAITOEN(1);
+	emc->stat[0].waitrd	= EMC_STAT_WAITRD(12);
+	emc->stat[0].waitpage	= EMC_STAT_WAITPAGE(12);
+	emc->stat[0].waitwr	= EMC_STAT_WAITWR(5);
+	emc->stat[0].waitturn	= EMC_STAT_WAITTURN(2);
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+
+	return 0;
+}
diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c
index d75e86b32e..35f5e15fc2 100644
--- a/board/timll/devkit8000/devkit8000.c
+++ b/board/timll/devkit8000/devkit8000.c
@@ -136,7 +136,7 @@ void set_muxconf_regs(void)
 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
-	omap_mmc_init(0);
+	omap_mmc_init(0, 0, 0);
 	return 0;
 }
 #endif
diff --git a/board/xilinx/ml507/.gitignore b/board/xilinx/ml507/.gitignore
deleted file mode 100644
index f6418a0c50..0000000000
--- a/board/xilinx/ml507/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/config.tmp
diff --git a/board/xilinx/ppc405-generic/.gitignore b/board/xilinx/ppc405-generic/.gitignore
deleted file mode 100644
index b644f59941..0000000000
--- a/board/xilinx/ppc405-generic/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-config.tmp
diff --git a/board/xilinx/ppc440-generic/.gitignore b/board/xilinx/ppc440-generic/.gitignore
deleted file mode 100644
index f6418a0c50..0000000000
--- a/board/xilinx/ppc440-generic/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/config.tmp
diff --git a/boards.cfg b/boards.cfg
index 3cf75c3151..da1458c576 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -136,6 +136,7 @@ hawkboard                    arm         arm926ejs   da8xxevm            davinci
 hawkboard_uart               arm         arm926ejs   da8xxevm            davinci        davinci     hawkboard:UART_U_BOOT
 enbw_cmc                     arm         arm926ejs   enbw_cmc            enbw           davinci
 calimain                     arm         arm926ejs   calimain            omicron        davinci
+pogo_e02                     arm         arm926ejs   -                   cloudengines   kirkwood
 dns325                       arm         arm926ejs   -                   d-link         kirkwood
 km_kirkwood                  arm         arm926ejs   km_arm              keymile        kirkwood	km_kirkwood:KM_DISABLE_PCI
 km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood	km_kirkwood:KM_RECONFIG_XLX
@@ -153,7 +154,9 @@ openrd_client                arm         arm926ejs   openrd              Marvell
 openrd_ultimate              arm         arm926ejs   openrd              Marvell        kirkwood        openrd:BOARD_IS_OPENRD_ULTIMATE
 rd6281a                      arm         arm926ejs   -                   Marvell        kirkwood
 sheevaplug                   arm         arm926ejs   -                   Marvell        kirkwood
+ib62x0                       arm         arm926ejs   ib62x0              raidsonic      kirkwood
 dockstar                     arm         arm926ejs   -                   Seagate        kirkwood
+devkit3250                   arm         arm926ejs   devkit3250          timll          lpc32xx
 jadecpu                      arm         arm926ejs   jadecpu             syteco         mb86r0x
 mx25pdk                      arm         arm926ejs   mx25pdk             freescale      mx25		mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg
 tx25                         arm         arm926ejs   tx25                karo           mx25
@@ -170,6 +173,7 @@ omap730p2_cs0boot	     arm         arm926ejs   omap730p2		 ti             omap
 omap730p2_cs3boot	     arm         arm926ejs   omap730p2		 ti             omap        omap730p2:CS3_BOOT
 edminiv2                     arm         arm926ejs   -                   LaCie          orion5x
 dkb			     arm         arm926ejs   -                   Marvell        pantheon
+rdaarm926ejs                 arm         arm926ejs   rdaarm926ejs        rda            rda
 spear300                     arm         arm926ejs   spear300            spear          spear       spear3xx:spear300
 spear310                     arm         arm926ejs   spear310            spear          spear       spear3xx:spear310
 spear320                     arm         arm926ejs   spear320            spear          spear       spear3xx:spear320
@@ -189,6 +193,7 @@ mx53ard                      arm         armv7       mx53ard             freesca
 mx53evk                      arm         armv7       mx53evk             freescale      mx5		mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg
 mx53loco                     arm         armv7       mx53loco            freescale      mx5		mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg
 mx53smd                      arm         armv7       mx53smd             freescale      mx5		mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg
+ima3-mx53                    arm         armv7       ima3-mx53           esg            mx5		ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg
 vision2                      arm         armv7       vision2             ttcontrol      mx5		vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg
 mx6qarm2                     arm         armv7       mx6qarm2            freescale      mx6		mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg
 mx6qsabrelite                arm         armv7       mx6qsabrelite       freescale      mx6		mx6qsabrelite:IMX_CONFIG=board/freescale/mx6qsabrelite/imximage.cfg
@@ -196,8 +201,8 @@ cm_t35                       arm         armv7       cm_t35              -
 omap3_overo                  arm         armv7       overo               -              omap3
 omap3_pandora                arm         armv7       pandora             -              omap3
 dig297                       arm         armv7       dig297              comelit        omap3
-igep0020                     arm         armv7       igep0020            isee           omap3
-igep0030                     arm         armv7       igep0030            isee           omap3
+igep0020                     arm         armv7       igep0020            isee           omap3		igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020
+igep0030                     arm         armv7       igep0030            isee           omap3		igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030
 am3517_evm                   arm         armv7       am3517evm           logicpd        omap3
 mt_ventoux                   arm         armv7       mt_ventoux          teejet         omap3
 omap3_zoom1                  arm         armv7       zoom1               logicpd        omap3
@@ -228,6 +233,12 @@ harmony                      arm         armv7       harmony             nvidia
 seaboard                     arm         armv7       seaboard            nvidia         tegra2
 ventana                      arm         armv7       ventana             nvidia         tegra2
 u8500_href                   arm         armv7       u8500               st-ericsson    u8500
+rda8810                      arm         armv7       rda8810             rda            rda
+rda8810e                     arm         armv7       rda8810e            rda            rda
+rda8810h                     arm         armv7       rda8810h            rda            rda
+rda8820                      arm         armv7       rda8820             rda            rda
+rda8850                      arm         armv7       rda8850             rda            rda
+rda8850e                     arm         armv7       rda8850e            rda            rda
 actux1_4_16                  arm         ixp         actux1              -              -           actux1:FLASH2X2
 actux1_4_32                  arm         ixp         actux1              -              -           actux1:FLASH2X2,RAM_32MB
 actux1_8_16                  arm         ixp         actux1              -              -           actux1:FLASH1X8
@@ -370,6 +381,7 @@ incaip_150MHz                mips        mips32      incaip              -
 qi_lb60                      mips        xburst      qi_lb60             qi
 adp-ag101                    nds32       n1213       adp-ag101           AndesTech      ag101
 adp-ag101p                   nds32       n1213       adp-ag101p          AndesTech      ag101
+adp-ag102                    nds32       n1213       adp-ag102           AndesTech      ag102
 nios2-generic                nios2       nios2       nios2-generic       altera
 PCI5441                      nios2       nios2       pci5441             psyent
 PK1C20                       nios2       nios2       pk1c20              psyent
@@ -742,6 +754,7 @@ P2020RDB-PC_SPIFLASH         powerpc     mpc85xx     p1_p2_rdb_pc        freesca
 P2020RDB_SDCARD              powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020RDB,SDCARD
 P2020RDB_SPIFLASH            powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020RDB,SPIFLASH
 P2041RDB                     powerpc     mpc85xx     p2041rdb            freescale
+P2041RDB_NAND	             powerpc     mpc85xx     p2041rdb            freescale      -           P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
 P2041RDB_SDCARD              powerpc     mpc85xx     p2041rdb            freescale      -           P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
 P2041RDB_SECURE_BOOT         powerpc     mpc85xx     p2041rdb            freescale      -           P2041RDB:SECURE_BOOT
 P2041RDB_SPIFLASH            powerpc     mpc85xx     p2041rdb            freescale      -           P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
@@ -750,6 +763,8 @@ P3041DS_NAND		     powerpc     mpc85xx     corenet_ds          freescale      -
 P3041DS_SDCARD		     powerpc     mpc85xx     corenet_ds          freescale      -           P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
 P3041DS_SECURE_BOOT          powerpc     mpc85xx     corenet_ds          freescale      -           P3041DS:SECURE_BOOT
 P3041DS_SPIFLASH	     powerpc     mpc85xx     corenet_ds          freescale      -           P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
+P3041DS_SRIOBOOT_MASTER		     powerpc     mpc85xx     corenet_ds          freescale      -           P3041DS:SRIOBOOT_MASTER
+P3041DS_SRIOBOOT_SLAVE          powerpc     mpc85xx     corenet_ds          freescale      -           P3041DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
 P3060QDS		     powerpc	 mpc85xx     p3060qds		 freescale
 P3060QDS_NAND		     powerpc     mpc85xx     p3060qds		 freescale	-	    P3060QDS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
 P3060QDS_SECURE_BOOT         powerpc     mpc85xx     p3060qds            freescale      -           P3060QDS:SECURE_BOOT
@@ -757,11 +772,15 @@ P4080DS                      powerpc     mpc85xx     corenet_ds          freesca
 P4080DS_SDCARD		     powerpc     mpc85xx     corenet_ds          freescale      -           P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
 P4080DS_SECURE_BOOT          powerpc     mpc85xx     corenet_ds          freescale      -           P4080DS:SECURE_BOOT
 P4080DS_SPIFLASH	     powerpc     mpc85xx     corenet_ds          freescale      -           P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
+P4080DS_SRIOBOOT_MASTER		     powerpc     mpc85xx     corenet_ds          freescale      -           P4080DS:SRIOBOOT_MASTER
+P4080DS_SRIOBOOT_SLAVE          powerpc     mpc85xx     corenet_ds          freescale      -           P4080DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
 P5020DS                      powerpc     mpc85xx     corenet_ds          freescale
 P5020DS_NAND		     powerpc     mpc85xx     corenet_ds          freescale      -           P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
 P5020DS_SDCARD		     powerpc     mpc85xx     corenet_ds          freescale      -           P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
 P5020DS_SECURE_BOOT          powerpc     mpc85xx     corenet_ds          freescale      -           P5020DS:SECURE_BOOT
 P5020DS_SPIFLASH	     powerpc     mpc85xx     corenet_ds          freescale      -           P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
+P5020DS_SRIOBOOT_MASTER		     powerpc     mpc85xx     corenet_ds          freescale      -           P5020DS:SRIOBOOT_MASTER
+P5020DS_SRIOBOOT_SLAVE          powerpc     mpc85xx     corenet_ds          freescale      -           P5020DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
 stxgp3                       powerpc     mpc85xx     stxgp3              stx
 stxssa                       powerpc     mpc85xx     stxssa              stx            -           stxssa
 stxssa_4M                    powerpc     mpc85xx     stxssa              stx            -           stxssa:STXSSA_4M
@@ -982,7 +1001,7 @@ intip                        powerpc     ppc4xx      intip               gdsys
 io                           powerpc     ppc4xx      405ep               gdsys
 io64                         powerpc     ppc4xx      405ex               gdsys
 iocon                        powerpc     ppc4xx      405ep               gdsys
-neo                          powerpc     ppc4xx      -                   gdsys
+neo                          powerpc     ppc4xx      405ep               gdsys
 icon                         powerpc     ppc4xx      -                   mosaixtech
 MIP405                       powerpc     ppc4xx      mip405              mpl
 MIP405T                      powerpc     ppc4xx      mip405              mpl            -           MIP405:MIP405T
diff --git a/common/Makefile b/common/Makefile
index d9f10f3f6e..7c828fc587 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -59,6 +59,7 @@ COBJS-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
 COBJS-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o
 COBJS-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o
 COBJS-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
+COBJS-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o
 COBJS-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
 
 # command
@@ -123,6 +124,7 @@ ifdef CONFIG_PHYLIB
 COBJS-$(CONFIG_CMD_MII) += cmd_mdio.o
 endif
 COBJS-$(CONFIG_CMD_MISC) += cmd_misc.o
+COBJS-$(CONFIG_CMD_MDCOM) += cmd_mdcom.o
 COBJS-$(CONFIG_CMD_MMC) += cmd_mmc.o
 COBJS-$(CONFIG_CMD_MMC_SPI) += cmd_mmc_spi.o
 COBJS-$(CONFIG_MP) += cmd_mp.o
@@ -189,6 +191,7 @@ endif
 
 ifdef CONFIG_SPL_BUILD
 COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
+COBJS-$(CONFIG_SPL_IMAGE_SUPPORT) += image.o
 endif
 COBJS-y += console.o
 COBJS-y += dlmalloc.o
@@ -204,6 +207,11 @@ XOBJS	:= $(addprefix $(obj),$(XCOBJS))
 
 CPPFLAGS += -I..
 
+ifeq ($(REBOOT_WHEN_CRASH),1)
+CPPFLAGS_common/cmd_misc.o += -DREBOOT_WHEN_CRASH
+CPPFLAGS_common/main.o += -DREBOOT_WHEN_CRASH
+endif
+
 all:	$(LIB) $(XOBJS)
 
 $(LIB): $(obj).depend $(OBJS)
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 5359a47859..42f08fdd0d 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -119,6 +119,14 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	print_mhz("pevfreq",		bd->bi_pevfreq);
 #endif
 
+#ifdef CONFIG_ENABLE_36BIT_PHYS
+#ifdef CONFIG_PHYS_64BIT
+	puts("addressing  = 36-bit\n");
+#else
+	puts("addressing  = 32-bit\n");
+#endif
+#endif
+
 	print_eth(0);
 #if defined(CONFIG_HAS_ETH1)
 	print_eth(1);
@@ -139,7 +147,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_HERMES
 	print_mhz("ethspeed",		bd->bi_ethspeed);
 #endif
-	printf("IP addr     = %pI4\n", &bd->bi_ip_addr);
+	printf("IP addr     = %s\n", getenv("ipaddr"));
 	printf("baudrate    = %6ld bps\n", bd->bi_baudrate);
 	print_num("relocaddr", gd->relocaddr);
 	return 0;
@@ -164,7 +172,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 #if defined(CONFIG_CMD_NET)
 	print_eth(0);
-	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+	printf("ip_addr     = %s\n", getenv("ipaddr"));
 #endif
 
 	printf("baudrate    = %ld bps\n", bd->bi_baudrate);
@@ -188,7 +196,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #endif
 #if defined(CONFIG_CMD_NET)
 	print_eth(0);
-	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+	printf("ip_addr     = %s\n", getenv("ipaddr"));
 #endif
 	printf("baudrate    = %ld bps\n", (ulong)bd->bi_baudrate);
 	return 0;
@@ -221,7 +229,7 @@ int do_bdinfo(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 
 #if defined(CONFIG_CMD_NET)
 	print_eth(0);
-	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+	printf("ip_addr     = %s\n", getenv("ipaddr"));
 #endif
 	printf("baudrate               = %6ld bps\n", bd->bi_baudrate);
 	return 0;
@@ -267,7 +275,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	print_eth(3);
 #endif
 
-	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+	printf("ip_addr     = %s\n", getenv("ipaddr"));
 #endif
 	printf("baudrate    = %ld bps\n", bd->bi_baudrate);
 
@@ -295,7 +303,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	print_num("flashoffset",	(ulong)bd->bi_flashoffset);
 
 	print_eth(0);
-	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+	printf("ip_addr     = %s\n", getenv("ipaddr"));
 	printf("baudrate    = %d bps\n", bd->bi_baudrate);
 
 	return 0;
@@ -315,7 +323,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	print_num("flashoffset",	(ulong)bd->bi_flashoffset);
 
 	print_eth(0);
-	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+	printf("ip_addr     = %s\n", getenv("ipaddr"));
 	printf("baudrate    = %d bps\n", bd->bi_baudrate);
 
 	return 0;
@@ -335,7 +343,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	print_num("flashoffset",	(ulong)bd->bi_flashoffset);
 
 	print_eth(0);
-	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+	printf("ip_addr     = %s\n", getenv("ipaddr"));
 	printf("baudrate    = %lu bps\n", bd->bi_baudrate);
 
 	return 0;
@@ -359,7 +367,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 #if defined(CONFIG_CMD_NET)
 	print_eth(0);
-	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+	printf("ip_addr     = %s\n", getenv("ipaddr"));
 #endif
 	printf("baudrate    = %d bps\n", bd->bi_baudrate);
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
@@ -395,7 +403,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 #if defined(CONFIG_CMD_NET)
 	print_eth(0);
-	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+	printf("ip_addr     = %s\n", getenv("ipaddr"));
 #endif
 	printf("baudrate    = %ld bps\n", (ulong)bd->bi_baudrate);
 	return 0;
@@ -428,7 +436,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 #if defined(CONFIG_CMD_NET)
 	print_eth(0);
-	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+	printf("ip_addr     = %s\n", getenv("ipaddr"));
 	print_mhz("ethspeed",	    bd->bi_ethspeed);
 #endif
 	printf("baudrate    = %d bps\n", bd->bi_baudrate);
@@ -453,7 +461,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 #if defined(CONFIG_CMD_NET)
 	print_eth(0);
-	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+	printf("ip_addr     = %s\n", getenv("ipaddr"));
 #endif
 	print_num("FB base  ", gd->fb_base);
 	return 0;
@@ -477,7 +485,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 #if defined(CONFIG_CMD_NET)
 	print_eth(0);
-	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+	printf("ip_addr     = %s\n", getenv("ipaddr"));
 #endif
 	printf("baudrate    = %d bps\n", bd->bi_baudrate);
 
@@ -498,7 +506,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 #if defined(CONFIG_CMD_NET)
 	print_eth(0);
-	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+	printf("ip_addr     = %s\n", getenv("ipaddr"));
 #endif
 
 	printf("baudrate    = %ld bps\n", bd->bi_baudrate);
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 5685232892..45e726af8b 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -1587,7 +1587,6 @@ static int bootz_start(cmd_tbl_t *cmdtp, int flag, int argc,
 
 static int do_bootz(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	ulong		iflag;
 	bootm_headers_t	images;
 
 	if (bootz_start(cmdtp, flag, argc, argv, &images))
@@ -1598,7 +1597,7 @@ static int do_bootz(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	 * overwrite all exception vector code, so we cannot easily
 	 * recover from any failures any more...
 	 */
-	iflag = disable_interrupts();
+	disable_interrupts();
 
 #if defined(CONFIG_CMD_USB)
 	/*
diff --git a/common/cmd_load.c b/common/cmd_load.c
index f4d66deae3..cd00ad1251 100644
--- a/common/cmd_load.c
+++ b/common/cmd_load.c
@@ -975,7 +975,7 @@ static ulong load_serial_ymodem (ulong offset)
 	ulong addr = 0;
 
 	size = 0;
-	info.mode = xyzModem_ymodem;
+	info.mode = xyzModem_xmodem;
 	res = xyzModem_stream_open (&info, &err);
 	if (!res) {
 
diff --git a/common/cmd_mdcom.c b/common/cmd_mdcom.c
new file mode 100644
index 0000000000..a2bc1bac59
--- /dev/null
+++ b/common/cmd_mdcom.c
@@ -0,0 +1,1360 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Misc functions
+ */
+#include <common.h>
+#include <command.h>
+#include <usb/usbserial.h>
+#include <nand.h>
+#include <jffs2/jffs2.h>
+#include <asm/arch/mdcom.h>
+#include <asm/arch/hwcfg.h>
+#include <asm/arch/factory.h>
+#include <asm/arch/prdinfo.h>
+#include <asm/arch/rda_sys.h>
+#include <part.h>
+#include <mmc.h>
+#include <mmc/mmcpart.h>
+#include <nand.h>
+#include <malloc.h>
+#include <linux/mtd/nand.h>
+#include <mtd/nand/rda_nand.h>
+
+
+#if 1
+#define bb_dbg(fmt, args...) printf(fmt, ##args)
+#else
+#define bb_dbg(fmt, args...) do {} while(0)
+#endif
+
+#define RDA_ADD_ROUNDUP(x)	(((x) + 3) & ~3)
+#define RDA_CHN_BUF_LEN		140
+
+struct rda_sys_hdr {
+	u16 magic;
+	u16 mod_id;
+	u32 req_id;
+	u32 ret_val;
+	u16 msg_id;
+	u16 ext_len;
+	u8 ext_data[];
+};
+
+struct rda_bp_info {
+	u32 bm_ver;
+	u32 bm_commit_rev;
+	u32 bm_build_date;
+	u32 bs_ver;
+	u32 bs_commit_rev;
+	u32 bs_build_date;
+};
+
+extern int mtdparts_init_default(void);
+extern int find_dev_and_part(const char *id, struct mtd_device **dev,
+			     u8 *part_num, struct part_info **part);
+
+#ifdef REBOOT_WHEN_CRASH
+#define ROLLBACK_TO_RECOVERY_MODE		0
+#endif
+
+/*
+ * Syntax:
+ *  mdcom_send {channel} {adress} {size} [{timeout} {mode}]
+ */
+int do_mdcom_send(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned int channel;
+	void *buf;
+	int size;
+	int timeout = 0;
+	int mode = 0;
+
+	if (argc < 4)
+		return CMD_RET_USAGE;
+
+	channel = simple_strtoul(argv[1], NULL, 10);
+	buf = (void*) simple_strtoul(argv[2], NULL, 16);
+	size = simple_strtoul(argv[3], NULL, 10);
+	if (argc >4)
+		timeout = simple_strtoul(argv[4], NULL, 10);
+	if (argc >5)
+		mode = simple_strtoul(argv[5], NULL, 10);
+
+	if (mode) {
+		bb_dbg("MDCOM send %d bytes stream to channel %d with returned value %d.\n",
+		       size, channel, rda_mdcom_channel_buf_send_stream(channel, buf,
+				       size, timeout));
+	} else {
+		bb_dbg("MDCOM send %d bytes dgram to channel %d with returned value %d.\n",
+		       size, channel, rda_mdcom_channel_buf_send_dgram(channel, buf,
+				       size, timeout));
+	}
+
+	rda_mdcom_channel_show(channel);
+	return 0;
+}
+
+/*
+ * Syntax:
+ *  mdcom_recv {channel} {adress} {size} [{timeout} {mode}]
+ */
+int do_mdcom_recv(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned int channel;
+	void *buf;
+	int size;
+	int timeout = 0;
+	int mode = 0;
+
+	if (argc < 4)
+		return CMD_RET_USAGE;
+
+	channel = simple_strtoul(argv[1], NULL, 10);
+	buf = (void*) simple_strtoul(argv[2], NULL, 16);
+	size = simple_strtoul(argv[3], NULL, 10);
+	if (argc >4)
+		timeout = simple_strtoul(argv[4], NULL, 10);
+	if (argc >5)
+		mode = simple_strtoul(argv[5], NULL, 10);
+
+	if (mode) {
+		bb_dbg("MDCOM receive %d bytes stream from channel %d with returned value %d.\n",
+		       size, channel, rda_mdcom_channel_buf_recv_stream(channel, buf,
+				       size, timeout));
+	} else {
+		bb_dbg("MDCOM receive %d bytes dgram from channel %d with returned value %d.\n",
+		       size, channel, rda_mdcom_channel_buf_recv_dgram(channel, buf,
+				       size, timeout));
+	}
+
+	rda_mdcom_channel_show(channel);
+	return 0;
+}
+
+static int rda_image_verify_header(const image_header_t *hdr)
+{
+	bb_dbg("   Verifying Image Header ... ");
+	if (!image_check_magic(hdr)) {
+		bb_dbg("Bad Magic Number\n");
+		return CMD_RET_FAILURE;
+	}
+
+	if (!image_check_hcrc(hdr)) {
+		bb_dbg("Bad Header Checksum\n");
+		return CMD_RET_FAILURE;
+	}
+	bb_dbg("OK\n");
+
+	image_print_contents(hdr);
+
+	return CMD_RET_SUCCESS;
+}
+
+static int rda_image_verify_data(const image_header_t *hdr)
+{
+	bb_dbg("   Verifying Data Checksum ... ");
+	if (!image_check_dcrc(hdr)) {
+		bb_dbg("Bad Data CRC\n");
+		return CMD_RET_FAILURE;
+	}
+	bb_dbg("OK\n");
+
+	return CMD_RET_SUCCESS;
+}
+
+static int rda_image_verify(const image_header_t *hdr)
+{
+	int ret;
+
+	ret = rda_image_verify_header(hdr);
+	if (ret == CMD_RET_SUCCESS) {
+		ret = rda_image_verify_data(hdr);
+	}
+	return ret;
+}
+
+int rda_modem_image_load(const image_header_t *hdr, int cal_en)
+{
+	u32 pc, param;
+	u32 modem_load_addr = image_get_load(hdr);
+	u32 ap_load_addr = rda_mdcom_address_modem2ap(modem_load_addr);
+
+	bb_dbg("%08x (AP address %08x) ...\n", modem_load_addr, ap_load_addr);
+
+	memcpy((void *)ap_load_addr, (const void *)image_get_data(hdr),
+			image_get_size(hdr));
+
+	pc = image_get_ep(hdr);
+	param = cal_en ? 0xCA1BCA1B : 0;
+	if (rda_mdcom_setup_run_env(pc, param))
+		return -1;
+
+	bb_dbg("    pc = %08x\n", pc);
+	bb_dbg("    param = %08x\n", param);
+	bb_dbg("Done\n");
+
+	return 0;
+}
+
+int rda_modem_cal_save(void)
+{
+	u32 addr, size;
+	int ret;
+
+	/* update all data to factorydata part. */
+	rda_mdcom_get_calib_section(&addr, &size);
+	factory_set_modem_calib((unsigned char *)addr);
+	rda_mdcom_get_ext_calib_section(&addr, &size);
+	factory_set_modem_ext_calib((unsigned char *)addr);
+	rda_mdcom_get_factory_section(&addr, &size);
+	factory_set_modem_factory((unsigned char *)addr);
+	rda_mdcom_get_ap_factory_section(&addr, &size);
+	factory_set_ap_factory((unsigned char *)addr);
+
+	ret = factory_burn();
+	if (ret) {
+		bb_dbg("Error when saving calibration data\n");
+		return ret;
+	}
+	return 0;
+}
+
+static void rda_modem_handle_syscmd(void)
+{
+	u8 md_com_buf[RDA_CHN_BUF_LEN / sizeof(u8)];
+	struct rda_sys_hdr *phdr = (struct rda_sys_hdr *)md_com_buf;
+
+#ifdef TEST_SYS
+	static int test_num = 0;
+	u8 tx_buf[RDA_CHN_BUF_LEN / sizeof(u8)];
+	struct rda_sys_hdr *ptx_hdr;
+	u32 *pext;
+	int ret;
+
+	if (test_num < 40) {
+		ptx_hdr = (struct rda_sys_hdr *) tx_buf;
+
+		ptx_hdr->magic = 0xA8B1;
+		ptx_hdr->mod_id = 0x1;
+		ptx_hdr->msg_id = 0x2000 + test_num;
+		ptx_hdr->req_id = 0xA1234567;
+		ptx_hdr->ret_val = 0xF7654321;
+
+		ptx_hdr->ext_len = 4;
+		pext = (u32 *)ptx_hdr->ext_data;
+		pext[0] = 0x1000123F;
+
+		ret = rda_mdcom_channel_buf_send_dgram(RDA_MDCOM_CHANNEL_SYSTEM, tx_buf, 16, 0);
+		if (!ret) {
+			rda_mdcom_line_set(RDA_MDCOM_PORT1, 2);
+			test_num++;
+		}
+	}
+#endif /* TEST_SYS */
+
+	if (!rda_mdcom_tstc(RDA_MDCOM_CHANNEL_SYSTEM))
+		return;
+
+	if (rda_mdcom_channel_buf_recv_dgram(
+				RDA_MDCOM_CHANNEL_SYSTEM,
+				md_com_buf,
+				16,
+				usec2ticks(1000)))
+		return;
+
+	if (phdr->magic == 0xA8B1) {
+		u16 len;
+		u8 *pdata;
+		u32 i;
+		u32 *pret;
+
+		len = phdr->ext_len;
+
+		bb_dbg("## RECEIVED SYSTEM CMD:\n");
+		bb_dbg("MODID - 0x%04x\n", phdr->mod_id);
+		bb_dbg("REQID - 0x%08x\n", phdr->req_id);
+		bb_dbg("RETVAL - 0x%08x\n", phdr->ret_val);
+		bb_dbg("MSGID - 0x%04x\n", phdr->msg_id);
+		bb_dbg("LEN - 0x%04x\n", phdr->ext_len);
+
+		if (len) {
+			pdata = phdr->ext_data;
+
+			if (len > 128) {
+				bb_dbg("Length is invalid!\n");
+			} else if (len != rda_mdcom_channel_buf_recv_stream(
+						RDA_MDCOM_CHANNEL_SYSTEM, pdata, len, 0)) {
+				bb_dbg("Read Parameters Failed!\n");
+			} else {
+				bb_dbg("Params - ");
+				for (i = 0; i < len; i++) {
+					bb_dbg("%02x ", pdata[i]);
+				}
+				bb_dbg("\n\n");
+			}
+		} else {
+			if ((phdr->mod_id == 1) && (phdr->msg_id == 2)) {
+				bb_dbg("Calibration done\n");
+				phdr->msg_id = 0x1001;
+				phdr->ext_len = 4;
+				pret = (u32 *) phdr->ext_data;
+
+				if (rda_modem_cal_save()) {
+					pret[0] = 0x0;
+					bb_dbg("Calibration data save failed\n");
+				} else {
+					pret[0] = 0x1;
+					bb_dbg("Calibration data save succeed\n");
+					prdinfo_set_cali_result(1);
+				}
+
+				rda_mdcom_channel_buf_send_dgram(
+					RDA_MDCOM_CHANNEL_SYSTEM, md_com_buf, 20, 0);
+				rda_mdcom_line_set(RDA_MDCOM_PORT1, 2);
+			}
+		}
+	}
+}
+
+static void rda_modem_handle_trace(void)
+{
+	u8 md_com_buf[RDA_CHN_BUF_LEN / sizeof(u8)];
+	int ch;
+
+	while (rda_mdcom_tstc(RDA_MDCOM_CHANNEL_TRACE)) {
+		int len = rda_mdcom_channel_buf_recv_stream(
+				  RDA_MDCOM_CHANNEL_TRACE,
+				  md_com_buf,
+				  128,
+				  0);
+		usbser_write(USB_ACM_CHAN_0, (unsigned char *) md_com_buf, len);
+	}
+
+	while (usbser_tstc(USB_ACM_CHAN_0) &&
+			rda_mdcom_channel_buf_send_available(RDA_MDCOM_CHANNEL_TRACE)) {
+		ch = usbser_getc(USB_ACM_CHAN_0);
+		rda_mdcom_putc((char) ch, RDA_MDCOM_CHANNEL_TRACE);
+	}
+}
+
+static void rda_modem_handle_atcmd(void)
+{
+	u8 md_com_buf[RDA_CHN_BUF_LEN / sizeof(u8)];
+	if (!rda_mdcom_tstc(RDA_MDCOM_CHANNEL_AT))
+		return;
+
+	bb_dbg("## RECEIVED AT CMD:");
+	do {
+		unsigned short len = rda_mdcom_channel_buf_recv_stream(
+					     RDA_MDCOM_CHANNEL_AT,
+					     md_com_buf,
+					     128,
+					     0);
+		*((char*) md_com_buf + len) = 0;
+		puts((const char *) md_com_buf);
+	} while (rda_mdcom_tstc(RDA_MDCOM_CHANNEL_AT));
+	bb_dbg("\n");
+}
+
+int rda_modem_cal_load(void)
+{
+	u32 addr, size;
+	const u8 *data;
+
+	/* extended calibration data */
+	rda_mdcom_get_ext_calib_section(&addr, &size);
+	data = factory_get_modem_ext_calib();
+	memcpy((u8 *)addr, data, size);
+	bb_dbg("MOMEM EXT CALIB address %08x ...\n", addr);
+
+	/* calibration data */
+	rda_mdcom_get_calib_section(&addr, &size);
+	data = factory_get_modem_calib();
+	memcpy((u8 *)addr, data, size);
+	bb_dbg("MOMEM CALIB address %08x ...\n", addr);
+
+	/* modem fact data */
+	rda_mdcom_get_factory_section(&addr, &size);
+	data = factory_get_modem_factory();
+	memcpy((u8 *)addr, data, size);
+	bb_dbg("MOMEM FACT address %08x ...\n", addr);
+
+	/* ap fact data */
+	rda_mdcom_get_ap_factory_section(&addr, &size);
+	data = factory_get_ap_factory();
+	memcpy((u8 *)addr, data, size);
+	bb_dbg("AP FACT address %08x ...\n", addr);
+
+	return 0;
+}
+
+static int rda_check_ap_calib_msg(void)
+{
+	unsigned int msg_id = 0;
+	unsigned int msg_size = 0;
+	unsigned char *msg_data = malloc(RDA_AP_CALIB_MSG_DATA_LEN);
+
+	if (!msg_data)
+		return -1;
+
+	if (factory_get_ap_calib_msg(&msg_id, &msg_size, msg_data)) {
+		free(msg_data);
+		return -1;
+	}
+
+	if (msg_id & RDA_AP_CALIB_MSG_SET_PRDINFO)
+		prdinfo_set_data((struct prdinfo *)msg_data);
+
+	free(msg_data);
+	return 0;
+}
+
+/* use this function after factorydata is loaded */
+static int rda_send_prdinfo_data(void)
+{
+	unsigned int msg_id = 0;
+	unsigned int msg_size = 0;
+	unsigned char *msg_data = malloc(RDA_AP_CALIB_MSG_DATA_LEN);
+
+	if (!msg_data)
+		return -1;
+
+	memset(msg_data, 0, RDA_AP_CALIB_MSG_DATA_LEN);
+	prdinfo_get_data((struct prdinfo *)msg_data);
+
+	msg_id = RDA_AP_CALIB_MSG_GET_PRDINFO;
+	msg_size = sizeof(struct prdinfo);
+	factory_set_ap_calib_msg(msg_id, msg_size, msg_data);
+	free(msg_data);
+	return 0;
+}
+
+void rda_modem_cal_loop(void)
+{
+	/* send prdinfo data to calib tool */
+	rda_send_prdinfo_data();
+
+	while (1) {
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+		WATCHDOG_RESET();
+#endif
+		/* check Ctrl-C */
+		ctrlc();
+		if ((had_ctrlc())) {
+			bb_dbg("\n## ABORT MANUALLY!\n\n");
+			return;
+		}
+
+		rda_modem_handle_syscmd();
+
+		rda_modem_handle_trace();
+
+		rda_modem_handle_atcmd();
+
+		/* check message to u-boot from PC calib tool*/
+		rda_check_ap_calib_msg();
+	}
+}
+
+int rda_modem_bbimages_load_from_nand(const image_header_t **hdrInit,
+		const image_header_t **hdrWork)
+{
+	struct mtd_info *nand;
+	struct mtd_device *dev;
+	struct part_info *part;
+	size_t page_size, block_size;
+	loff_t offset;
+	size_t read_size, image_size;
+	u8 pnum;
+	int ret;
+	u_char *buffer;
+	image_header_t *hdr;
+	u32 bad_blocks;
+	char buf[256];
+	u32 ih_len;
+	int i;
+
+	ret = mtdparts_init_default();
+	if (ret != 0) {
+		bb_dbg("mtdparts init error\n");
+		return ret;
+	}
+
+	ret = find_dev_and_part("modem", &dev, &pnum, &part);
+	if (ret) {
+		bb_dbg("unknown partition name - modem\n");
+		return ret;
+	} else if (dev->id->type != MTD_DEV_TYPE_NAND) {
+		bb_dbg("mtd dev type error");
+		return CMD_RET_FAILURE;
+	}
+	bb_dbg("found modem part '%s' offset: 0x%llx length: 0x%llx\n",
+		part->name, part->offset, part->size);
+
+	nand = &nand_info[dev->id->num];
+	page_size = nand->writesize;
+	block_size = nand->erasesize;
+
+	bb_dbg("\n## Checking Modem Code Image ...\n\n");
+
+	for (i = 0; i < 2; ++i) {
+		if (i == 0) {
+			offset = part->offset;
+			buffer = (u_char *)SCRATCH_ADDR;
+			hdr = (image_header_t *)buffer;
+		} else {
+			hdr = (image_header_t *)((u8 *)hdr + image_size);
+		}
+
+		if (buffer < (u8 *)hdr + sizeof(image_header_t)) {
+			read_size = (u8 *)hdr + sizeof(image_header_t) - buffer;
+			if (is_power_of_2(page_size))
+				read_size = ROUND(read_size, page_size);
+			else
+				read_size = roundup(read_size, page_size);
+			bad_blocks = 0;
+
+			bb_dbg("read 0x%x bytes from '%s' offset: 0x%08x\n",
+			       read_size, part->name, (u32)offset);
+			ret = nand_read_skip_bad_new(nand, offset, &read_size,
+					buffer, &bad_blocks);
+			if (ret) {
+				bb_dbg("nand read fail\n");
+				return ret;
+			}
+
+			offset += read_size + block_size * bad_blocks;
+			buffer += read_size;
+		}
+
+		ret = rda_image_verify_header(hdr);
+		if (ret)
+			return ret;
+
+		image_size = image_get_image_size(hdr);
+
+		if (buffer < (u8 *)hdr + image_size) {
+			read_size = (u8 *)hdr + image_size - buffer;
+			if (is_power_of_2(page_size))
+				read_size = ROUND(read_size, page_size);
+			else
+				read_size = roundup(read_size, page_size);
+
+			bb_dbg("\nread 0x%x bytes from '%s' offset: 0x%08x\n",
+			       read_size, part->name, (u32)offset);
+			ret = nand_read_skip_bad_new(nand, offset, &read_size,
+					buffer, &bad_blocks);
+			if (ret) {
+				bb_dbg("nand read fail\n");
+				return ret;
+			}
+
+			offset += read_size + block_size * bad_blocks;
+			buffer += read_size;
+		}
+
+		ret = rda_image_verify_data(hdr);
+		if (ret)
+			return ret;
+
+		if (i == 0) {
+			ih_len = min(sizeof(buf), IH_NMLEN);
+			strncpy(buf, (const char *)hdr->ih_name, ih_len);
+			buf[ih_len - 1] = '\0';
+		}
+		if (i == 0 && strstr(buf, "raminit")) {
+			bb_dbg("## Raminit Image Detected\n");
+			bb_dbg("\n");
+			*hdrInit = hdr;
+		} else {
+			bb_dbg("## Work Image Detected\n");
+			bb_dbg("\n");
+			*hdrWork = hdr;
+			break;;
+		}
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+int rda_modem_bbimages_load_from_mmc(const image_header_t **hdrInit,
+		const image_header_t **hdrWork)
+{
+	u64  offset = 0;
+	size_t read_size, image_size;
+	u_char *buffer;
+	image_header_t *hdr;
+	char buf[256];
+	u32 ih_len;
+	int i;
+	int ret;
+	disk_partition_t *ptn;
+	block_dev_desc_t *mmc_blkdev;
+	struct mmc *mmc;
+
+	mmc_blkdev = get_dev_by_name(CONFIG_MMC_DEV_NAME);
+	if (mmc_blkdev)
+		mmc = container_of(mmc_blkdev, struct mmc, block_dev);
+	else
+		return CMD_RET_FAILURE;
+
+	if (!mmc) {
+                bb_dbg("mmc doesn't exist");
+		return CMD_RET_FAILURE;
+	}
+
+	ptn = partition_find_ptn("modem");
+        if(ptn == 0) {
+                bb_dbg("mmc partition table doesn't exist");
+                return -1;
+        }
+
+	bb_dbg("found modem part  offset: 0x%lx\n", ptn->start);
+
+	bb_dbg("\n## Checking Modem Code Image ...\n\n");
+
+	for (i = 0; i < 2; ++i) {
+		if (i == 0) {
+			offset = ptn->start * ptn->blksz;
+			buffer = (u_char *)SCRATCH_ADDR;
+			hdr = (image_header_t *)buffer;
+		} else {
+			hdr = (image_header_t *)((u8 *)hdr + image_size);
+		}
+
+		if (buffer < (u8 *)hdr + sizeof(image_header_t)) {
+			read_size = (u8 *)hdr + sizeof(image_header_t) - buffer;
+			read_size = ROUND(read_size, 512);
+
+			bb_dbg("read 0x%x bytes  offset: 0x%08x\n",
+				read_size, (u32)offset);
+			ret = mmc_read(mmc, offset, buffer, read_size);
+			if (ret <= 0) {
+				bb_dbg("mmc read fail\n");
+				return ret;
+			}
+
+			offset += read_size;
+			buffer += read_size;
+		}
+
+		ret = rda_image_verify_header(hdr);
+		if (ret)
+			return ret;
+
+		image_size = image_get_image_size(hdr);
+
+		if (buffer < (u8 *)hdr + image_size) {
+			read_size = (u8 *)hdr + image_size - buffer;
+			read_size = ROUND(read_size, 512);
+
+			bb_dbg("\nread 0x%x bytes offset: 0x%08x\n",
+			       read_size, (u32)offset);
+			ret = mmc_read(mmc, offset, buffer, read_size);
+			if (ret <= 0) {
+				bb_dbg("mmc read fail\n");
+				return ret;
+			}
+
+			offset += read_size;
+			buffer += read_size;
+		}
+
+		ret = rda_image_verify_data(hdr);
+		if (ret)
+			return ret;
+
+		if (i == 0) {
+			ih_len = min(sizeof(buf), IH_NMLEN);
+			strncpy(buf, (const char *)hdr->ih_name, ih_len);
+			buf[ih_len - 1] = '\0';
+		}
+		if (i == 0 && strstr(buf, "raminit")) {
+			bb_dbg("## Raminit Image Detected\n");
+			bb_dbg("\n");
+			*hdrInit = hdr;
+		} else {
+			bb_dbg("## Work Image Detected\n");
+			bb_dbg("\n");
+			*hdrWork = hdr;
+			break;;
+		}
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+void rdaHexPuts(char* p, int l)
+{
+	char strBuf[64];
+	char* s = strBuf;
+	if (l > 20)
+		l = 20;
+
+	while (l--) {
+		unsigned char c = (unsigned char) *p++;
+		*s = ((c >> 4) & 0xF) + '0';
+		if (*s > '9')
+			*s = *s + 'A' - '9' - 1;
+
+		*++s = (c & 0xF) + '0';
+		if (*s > '9')
+			*s = *s + 'A' - '9' - 1;
+
+		*++s = ' ';
+		++s;
+	}
+	*s = '\r';
+	*++s = '\n';
+	*++s = 0;
+	puts((const char *) strBuf);
+}
+
+void rda_modem_cal_test(void)
+{
+	char cmdbuf[16];
+	unsigned long long end_time = get_ticks();
+
+	while (1) {
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+		WATCHDOG_RESET();
+#endif
+		/* check Ctrl-C */
+		ctrlc();
+		if ((had_ctrlc())) {
+			bb_dbg("\n## ABORT MANUALLY!\n\n");
+			return;
+		}
+
+		if (end_time < get_ticks()) {
+			char* p = cmdbuf;
+			*p++ = 0xad;
+			*p++ = 0x00;
+			*p++ = 0x0a;
+			*p++ = 0xFF;
+			*p++ = 0x82;
+			*p++ = 0x00;
+			*p++ = 0x00;
+			*p++ = 0x00;
+			*p++ = 0x82;
+			*p++ = (char)((end_time >> 0) & 0xFF);
+			*p++ = (char)((end_time >> 8) & 0xFF);
+			*p++ = (char)((end_time >> 16) & 0xFF);
+			*p++ = (char)((end_time >> 24) & 0xFF);
+			*p++ = 0xFF;
+			bb_dbg("## Send write cmd to modem: ");
+			rdaHexPuts(cmdbuf, rda_mdcom_channel_buf_send_stream(
+					   RDA_MDCOM_CHANNEL_TRACE, cmdbuf, 14, 0));
+
+			p = cmdbuf;
+			*p++ = 0xad;
+			*p++ = 0x00;
+			*p++ = 0x07;
+			*p++ = 0xFF;
+			*p++ = 0x02;
+			*p++ = 0x00;
+			*p++ = 0x00;
+			*p++ = 0x00;
+			*p++ = 0x82;
+			*p++ = (char)((end_time >> 24) & 0xFF);
+			*p++ = 0xFF;
+			bb_dbg("## Send read cmd to modem: ");
+			rdaHexPuts(cmdbuf, rda_mdcom_channel_buf_send_stream(
+					   RDA_MDCOM_CHANNEL_TRACE, cmdbuf, 11, 0));
+
+			end_time = get_ticks() + usec2ticks(20000);
+		}
+
+		if (rda_mdcom_tstc(RDA_MDCOM_CHANNEL_TRACE)) {
+			bb_dbg("## received from modem:");
+			do {
+				rdaHexPuts(cmdbuf, rda_mdcom_channel_buf_recv_stream(
+						   RDA_MDCOM_CHANNEL_TRACE, cmdbuf,
+						   sizeof(cmdbuf), 0));
+			} while (rda_mdcom_tstc(RDA_MDCOM_CHANNEL_TRACE));
+		}
+	}
+}
+
+static void rda_show_modem_exception(void)
+{
+	char *addr;
+	unsigned int len;
+	char buf[256];
+
+	rda_mdcom_get_modem_exception_info((u32 *)&addr, &len);
+	snprintf(buf, sizeof(buf), "%s\n", addr);
+	buf[sizeof(buf) - 1] = '\0';
+	puts("\n");
+	if (addr) {
+		puts("Modem exception info:\n");
+		puts("---------------------\n");
+		puts(buf);
+		puts("---------------------\n");
+	} else {
+		puts("No valid modem exception info\n");
+	}
+}
+
+extern void shutdown_system(void);
+
+static void rda_modem_shutdown_system(void)
+{
+	struct rda_sys_hdr hdr;
+
+	bb_dbg("\n## System is being shutdown ... ");
+
+	hdr.magic = 0xA8B1;
+	hdr.mod_id = 0x0;
+	hdr.msg_id = 0x1001;
+	hdr.req_id = 0x0;
+	hdr.ret_val = 0x0;
+	hdr.ext_len = 0;
+
+	rda_mdcom_channel_buf_send_dgram(
+		RDA_MDCOM_CHANNEL_SYSTEM, &hdr, sizeof(hdr),
+		usec2ticks(100000));
+	rda_mdcom_line_set(RDA_MDCOM_PORT1, 2);
+	/* Wait sometime until modem shutdowns the system (about 1.8s) */
+	udelay(5000000);
+	/* Modem is in trouble. Shutdown the system directly. */
+	bb_dbg("\n## Bootloader directly shutdown ... ");
+	shutdown_system();
+}
+
+int bbimages_get_header(const u8 *p_image, const image_header_t **hdrInit,
+		const image_header_t **hdrWork)
+{
+	int retVal;
+	char buf[256];
+	u32 ih_len;
+	int i;
+	image_header_t *hdr;
+
+	for (i = 0; i < 2; i++) {
+		hdr = (image_header_t *) RDA_ADD_ROUNDUP((int) p_image);
+
+		bb_dbg("\n## Checking Modem Code Image at %08x ...\n",
+				(unsigned int)hdr);
+		retVal = rda_image_verify(hdr);
+		if (retVal) {
+			/* If there is no image, we initialize channels
+			 * still.  Otherwise kernel would not be
+			 * loaded. */
+			rda_mdcom_channel_all_init();
+			return retVal;
+		}
+
+		if (i == 0) {
+			ih_len = min(sizeof(buf), IH_NMLEN);
+			strncpy(buf, (const char *)hdr->ih_name, ih_len);
+			buf[ih_len - 1] = '\0';
+		}
+		if (i == 0 && strstr(buf, "raminit")) {
+			bb_dbg("## Raminit Image Detected\n");
+			p_image += image_get_image_size(hdr);
+			*hdrInit = hdr;
+		} else {
+			bb_dbg("## Work Image Detected\n");
+			*hdrWork = hdr;
+			break;
+		}
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+int mdcom_check_and_wait_modem(int check_boot_key)
+{
+	int shutdown = 0;
+	unsigned long long end_time;
+	u32 reset_cause;
+	u32 itf_version;
+
+	/* Set a timeout of 2 seconds to wait for BP */
+	bb_dbg("\n## Waiting for modem response ... ");
+
+	end_time = get_ticks() + usec2ticks(2000000);
+	while (!rda_mdcom_line_set_wait(RDA_MDCOM_PORT0,
+				RDA_MDCOM_LINE_CMD_START, 100)) {
+		/* check exception */
+		if (rda_mdcom_line_set_check(RDA_MDCOM_PORT0,
+					RDA_MDCOM_LINE_EXCEPTION)) {
+			bb_dbg("\n\n");
+			bb_dbg("**********************************\n");
+			bb_dbg("*** Error: Detect modem exception!\n");
+			rda_show_modem_exception();
+#ifdef REBOOT_WHEN_CRASH
+			bb_dbg("Rebooting ...\n\n\n");
+			udelay(5000);
+			disable_interrupts();
+			if (ROLLBACK_TO_RECOVERY_MODE)
+				rda_reboot(REBOOT_TO_RECOVERY_MODE);
+			else
+				rda_reboot(REBOOT_TO_NORMAL_MODE);
+#endif
+			return CMD_RET_FAILURE;
+		}
+		/* check timeout */
+		if (get_ticks() > end_time) {
+#ifdef REBOOT_WHEN_CRASH
+			bb_dbg("\n\n## Error: Timeout when waiting for "
+			       "modem response. Rebooting ...\n\n\n");
+			udelay(5000);
+			disable_interrupts();
+			if (ROLLBACK_TO_RECOVERY_MODE)
+				rda_reboot(REBOOT_TO_RECOVERY_MODE);
+			else
+				rda_reboot(REBOOT_TO_NORMAL_MODE);
+#else
+			end_time = -1;
+			bb_dbg("\n\n## Warning: Timeout when waiting for "
+			       "modem response. Press Ctrl-C to abort.\n");
+#endif
+		}
+		/* check Ctrl-C */
+		ctrlc();
+		if ((had_ctrlc())) {
+			bb_dbg("\n## ABORT MANUALLY!\n\n");
+			return CMD_RET_FAILURE;
+		}
+	}
+	bb_dbg("Done\n");
+
+	reset_cause = rda_mdcom_get_reset_cause();
+	itf_version = rda_mdcom_get_interface_version();
+	bb_dbg("\n## Reset cause : 0x%08x\n", reset_cause);
+	bb_dbg("\n## Communication interface version : 0x%08x\n", itf_version);
+	if (itf_version != RDA_BP_VER) {
+		bb_dbg("*** Error: Unsupported version. 0x%08x is expected.\n",
+				RDA_BP_VER);
+		return CMD_RET_FAILURE;
+	}
+
+	if (reset_cause == RDA_RESET_CAUSE_NORMAL) {
+		/* Check power-on key status */
+		if (check_boot_key && !get_saved_boot_key_state()) {
+			shutdown = 0;
+			bb_dbg("\n## Power-on key is not pressed for normal boot.");
+			bb_dbg("\n## ****** Shutdown is needed later ******\n");
+		}
+	}
+
+	bb_dbg("\n## Init mdcom channels ... ");
+	rda_mdcom_channel_all_init();
+	rda_mdcom_line_clear(RDA_MDCOM_PORT0, RDA_MDCOM_LINE_CMD_START);
+	bb_dbg("Done\n");
+
+	/* Check if shutdown is needed after modem fully starts up */
+	if (shutdown)
+		rda_modem_shutdown_system();
+
+	/* rda_mdcom_show_software_version(); */
+	return CMD_RET_SUCCESS;
+}
+
+static int do_check_and_wait_modem(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int check_boot_key = 0;
+
+	if (argc >= 2)
+		check_boot_key = (int) simple_strtoul(argv[1], NULL, 10);
+
+	return mdcom_check_and_wait_modem(check_boot_key);
+}
+
+int bbimages_load(const image_header_t *hdrInit, const image_header_t *hdrWork,
+		int cal_en)
+{
+	unsigned long long end_time;
+	u32 addr, len;
+	char buf[256];
+	int update_calib = 0, update_factory = 0, update_ap_factory = 0;
+	u32 modem_load_addr = image_get_load(hdrWork);
+
+	/* set modem logic base address for modem side,
+	   by the work code loading address in image header */
+	rda_mdcom_set_logic_base_addr(modem_load_addr);
+
+	bb_dbg("\n## Init mdcom ports ... ");
+	rda_mdcom_init_port(RDA_MDCOM_PORT0);
+	rda_mdcom_init_port(RDA_MDCOM_PORT1);
+	bb_dbg("Done\n");
+
+	if (hdrInit) {
+		bb_dbg("\n## Load Raminit Code to modem at ");
+		rda_modem_image_load(hdrInit, 0);
+
+		bb_dbg("\n## Start modem and waiting for response ... ");
+		rda_mdcom_line_set(RDA_MDCOM_PORT0, RDA_MDCOM_LINE_DL_HANDSHAKE);
+		/* Set a timeout of 2 seconds to wait for BP */
+		end_time = get_ticks() + usec2ticks(2000000);
+		while (!rda_mdcom_line_set_wait(RDA_MDCOM_PORT0,
+					RDA_MDCOM_LINE_DL_HANDSHAKE, 100)) {
+			/* check timeout */
+			if (get_ticks() > end_time) {
+#ifdef REBOOT_WHEN_CRASH
+				bb_dbg("\n\n## Error: Timeout when waiting for "
+				       "modem response. Rebooting ...\n\n\n");
+				udelay(5000);
+				disable_interrupts();
+				if (ROLLBACK_TO_RECOVERY_MODE)
+					rda_reboot(REBOOT_TO_RECOVERY_MODE);
+				else
+					rda_reboot(REBOOT_TO_NORMAL_MODE);
+#else
+				end_time = -1;
+				bb_dbg("\n\n## Warning: Timeout when waiting for "
+				       "modem response. Press Ctrl-C to abort.\n");
+#endif
+			}
+			/* check Ctrl-C */
+			ctrlc();
+			if ((had_ctrlc())) {
+				bb_dbg("\n## ABORT MANUALLY!\n\n");
+				return CMD_RET_FAILURE;
+			}
+		}
+		rda_mdcom_line_clear(RDA_MDCOM_PORT0, RDA_MDCOM_LINE_DL_HANDSHAKE);
+		bb_dbg("Done\n");
+	}
+
+	/* Check whether modem crashed in the last run */
+	if (rda_mdcom_modem_crashed_before()) {
+		rda_mdcom_get_modem_exception_info(&addr, &len);
+		buf[0] = '\0';
+		if (addr) {
+			snprintf(buf, sizeof(buf), "%s", (char *)addr);
+			buf[sizeof(buf) - 1] = '\0';
+			/* TODO: Save the exception info to nand/sdmmc */
+		}
+		rda_mdcom_get_modem_log_info(&addr, &len);
+		if (addr) {
+			/* TODO: Save the log info to nand/sdmmc */
+			/* NOTE: The log is in binary format! */
+		}
+	}
+	/* Check whether to udpate modem calib and factory data */
+	if (system_rebooted()) {
+		update_calib = rda_mdcom_calib_update_cmd_valid();
+		if (update_calib) {
+			bb_dbg("\n## Detect calib update command\n");
+			rda_mdcom_get_calib_section(&addr, &len);
+			factory_set_modem_calib((unsigned char *)addr);
+			rda_mdcom_get_ext_calib_section(&addr, &len);
+			factory_set_modem_ext_calib((unsigned char *)addr);
+		}
+		update_factory = rda_mdcom_factory_update_cmd_valid();
+		if (update_factory) {
+			bb_dbg("\n## Detect factory update command\n");
+			rda_mdcom_get_factory_section(&addr, &len);
+			factory_set_modem_factory((unsigned char *)addr);
+		}
+		update_ap_factory = rda_mdcom_ap_factory_update_cmd_valid();
+		if (update_ap_factory) {
+			bb_dbg("\n## Detect AP factory update command\n");
+			rda_mdcom_get_ap_factory_section(&addr, &len);
+			factory_set_ap_factory((unsigned char *)addr);
+		}
+		if (update_calib || update_factory || update_ap_factory) {
+			bb_dbg("\n## Burn calib and/or factory data\n");
+			if (factory_burn())
+				bb_dbg("\n** Error when burning data\n");
+		}
+	}
+	/* Init all log info and some magic numbers */
+	rda_mdcom_init_all_log_info();
+
+	bb_dbg("\n## Load Work Code to modem at ");
+	if (rda_modem_image_load(hdrWork, cal_en)) {
+		printf("\n## Load modem failed!\n");
+		return CMD_RET_FAILURE;
+	}
+
+	bb_dbg("\n## Load Calib Data to modem at ");
+	rda_modem_cal_load();
+
+	bb_dbg("\n## Start modem ...\n");
+	rda_mdcom_line_set(RDA_MDCOM_PORT0, RDA_MDCOM_LINE_DL_HANDSHAKE);
+
+	return CMD_RET_SUCCESS;
+}
+
+int mdcom_load_from_mem(const u8 *data, int cal_en)
+{
+	const image_header_t *hdrInit = NULL;
+	const image_header_t *hdrWork = NULL;
+
+	if (bbimages_get_header(data, &hdrInit, &hdrWork)) {
+		/* If there is no image, we initialize channels still.
+		 * Otherwise kernel would not be loaded. */
+		rda_mdcom_channel_all_init();
+		return CMD_RET_FAILURE;
+	}
+
+	return bbimages_load(hdrInit, hdrWork, cal_en);
+}
+
+int mdcom_load_from_flash(int cal_en)
+{
+	int ret;
+	const image_header_t *hdrInit = NULL;
+	const image_header_t *hdrWork = NULL;
+
+	/*
+	 * Save the boot key state now.
+	 * It takes about 1.9s to run into here if boot delay is 1s.
+	 */
+	save_current_boot_key_state();
+
+	if (rda_media_get() == MEDIA_MMC)
+		ret = rda_modem_bbimages_load_from_mmc(&hdrInit, &hdrWork);
+	else
+		ret = rda_modem_bbimages_load_from_nand(&hdrInit, &hdrWork);
+
+	if (ret) {
+		/*
+		 * If there is no image, we initialize channels still.
+		 * Otherwise kernel would not be loaded.
+		 */
+		rda_mdcom_channel_all_init();
+		return CMD_RET_FAILURE;
+	}
+	return bbimages_load(hdrInit, hdrWork, cal_en);
+}
+
+/*
+ * Syntax:
+ *  mdcom_loadm {adress} [cal_en]
+ */
+int do_mdcom_loadm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int cal_en = 0;
+	const u8 *data;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+	if (argc >= 3)
+		cal_en = (int) simple_strtoul(argv[2], NULL, 10);
+
+	data = (const u8 *)simple_strtoul(argv[1], NULL, 16);
+
+	return mdcom_load_from_mem(data, cal_en);
+}
+
+int do_mdcom_cal_loadm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	const u8 *data;
+	if (argc != 2)
+		return CMD_RET_USAGE;
+
+	data = (const u8 *)simple_strtoul(argv[1], NULL, 16);
+	if (rda_image_verify_header((const image_header_t *)data))
+		return CMD_RET_FAILURE;
+
+	if (factory_copy_from_mem(data))
+		return CMD_RET_FAILURE;
+
+	return CMD_RET_SUCCESS;
+}
+
+/*
+ * Syntax:
+ *  mdcom_loadf [cal_en]
+ */
+int do_mdcom_loadf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int cal_en = 0;
+
+	if (argc >= 2)
+		cal_en = (int) simple_strtoul(argv[1], NULL, 10);
+
+	return mdcom_load_from_flash(cal_en);
+}
+
+int do_mdcom_cal_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	rda_modem_cal_test();
+	return CMD_RET_SUCCESS;
+}
+
+int do_mdcom_cal(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	drv_usbser_init();
+	rda_modem_cal_loop();
+	return CMD_RET_SUCCESS;
+}
+
+int do_mdcom_ch_show(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	bb_dbg("\n## MDCOM Channel AT Show:\n");
+	rda_mdcom_channel_show(RDA_MDCOM_CHANNEL_AT);
+	bb_dbg("\n## MDCOM Channel SYS Show:\n");
+	rda_mdcom_channel_show(RDA_MDCOM_CHANNEL_SYSTEM);
+	bb_dbg("\n## MDCOM Channel TRACE Show:\n");
+	rda_mdcom_channel_show(RDA_MDCOM_CHANNEL_TRACE);
+	return CMD_RET_SUCCESS;
+}
+
+int do_mdcom_cal_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (rda_modem_cal_save())
+		return CMD_RET_FAILURE;
+	else
+		return CMD_RET_SUCCESS;
+}
+
+int do_mdcom_cal_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (rda_modem_cal_load())
+		return CMD_RET_FAILURE;
+	else
+		return CMD_RET_SUCCESS;
+}
+
+int do_mdcom_diag(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	rda_mdcom_show_xcpu_info();
+	return CMD_RET_SUCCESS;
+}
+
+int do_mdcom_ver(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	rda_mdcom_show_software_version();
+	return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+	mdcom_send ,    6,    1,     do_mdcom_send,
+	"send data to mdCom channels",
+	"Syntax:\n"
+	"    - mdcom_send {channel} {adress} {size} [{timeout} {mode}]"
+	"Parameters:\n"
+	"    - channel:  the mdcom channel number\n"
+	"    - adress:   the address of the data buffer to send\n"
+	"    - size: 	 the size of the sending buffer\n"
+	"    - timeout:  (optional) the timeout with unit ms\n"
+	"    - mode: 	 (optional) 0 - stream mode; else - dgram mode\n"
+);
+
+U_BOOT_CMD(
+	mdcom_recv ,    6,    1,     do_mdcom_recv,
+	"send data to mdCom channels",
+	"Syntax:\n"
+	"    - mdcom_recv {channel} {address} {size} [{timeout} {mode}]\n"
+	"Parameters:\n"
+	"    - channel:  the mdcom channel number\n"
+	"    - adress:   the address of the buffer to receive data\n"
+	"    - size: 	 the size of the receiving buffer\n"
+	"    - timeout:  (optional) the timeout with unit ms\n"
+	"    - mode: 	 (optional) 0 - stream mode; else - dgram mode\n"
+);
+
+U_BOOT_CMD(
+	mdcom_cal_loadm ,    2,    1,     do_mdcom_cal_loadm,
+	"load modem calibration data from memory",
+	"Syntax:\n"
+	"    - mdcom_cal_loadm {address} \n"
+	"Parameters:\n"
+	"    - address:        the address of the buffer to receive data\n"
+);
+
+U_BOOT_CMD(
+	mdcom_loadm ,    3,    1,     do_mdcom_loadm,
+	"load modem codes from memory",
+	"Syntax:\n"
+	"    - mdcom_loadm {adress} [{cal_en}] \n"
+	"Parameters:\n"
+	"    - address:        the address of the buffer to receive data\n"
+	"    - cal_en:         enable calibration\n"
+);
+
+U_BOOT_CMD(
+	mdcom_loadf ,    2,    1,     do_mdcom_loadf,
+	"load modem codes from flash",
+	"Syntax:\n"
+	"    - mdcom_loadf [{cal_en}] \n"
+	"Parameters:\n"
+	"    - cal_en:   enable calibration\n"
+);
+
+U_BOOT_CMD(
+	mdcom_calt ,    1,    1,     do_mdcom_cal_test,
+	"modem calibration test",
+	"Syntax:\n"
+	"    - mdcom_calt\n"
+);
+
+U_BOOT_CMD(
+	mdcom_cal ,    1,    1,     do_mdcom_cal,
+	"modem calibration",
+	"Syntax:\n"
+	"    - mdcom_cal\n"
+);
+
+U_BOOT_CMD(
+	mdcom_show ,    1,    1,     do_mdcom_ch_show,
+	"show mdcom all channels",
+	"Syntax:\n"
+	"    - mdcom_show\n"
+);
+
+U_BOOT_CMD(
+	mdcom_cal_save ,    1,    1,     do_mdcom_cal_save,
+	"modem calibration data save",
+	"Syntax:\n"
+	"    - mdcom_cal_save\n"
+);
+
+U_BOOT_CMD(
+	mdcom_cal_load ,    1,    1,     do_mdcom_cal_load,
+	"modem calibration data load",
+	"Syntax:\n"
+	"    - mdcom_cal_load\n"
+);
+
+U_BOOT_CMD(
+	mdcom_diag,    1,    1,     do_mdcom_diag,
+	"Show modem XCPU diagostic information",
+	"Syntax:\n"
+	"    - mdcom_diag\n"
+);
+
+U_BOOT_CMD(
+	mdcom_ver,    1,    1,     do_mdcom_ver,
+	"Show modem software versions",
+	"Syntax:\n"
+	"    - mdcom_ver\n"
+);
+
+U_BOOT_CMD(
+	mdcom_check,    2,    1,     do_check_and_wait_modem,
+	"check modem status, may wait",
+	"Syntax:\n"
+	"    - mdcom_check {[check_boot_key]}\n"
+	"Parameters:\n"
+	"    - check_boot_key: whether to check boot key status\n"
+);
+
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index fa6f5991a5..38e4fa264e 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -261,7 +261,7 @@ int do_mem_mwc ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	ulong	addr1, addr2, count, ngood;
+	ulong	addr1, addr2, count, ngood, nbad;
 	int	size;
 	int     rcode = 0;
 
@@ -296,6 +296,7 @@ int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #endif
 
 	ngood = 0;
+	nbad = 0;
 
 	while (count-- > 0) {
 		if (size == 4) {
@@ -306,7 +307,8 @@ int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 					"!= word at 0x%08lx (0x%08lx)\n",
 					addr1, word1, addr2, word2);
 				rcode = 1;
-				break;
+				nbad++;
+				//break;
 			}
 		}
 		else if (size == 2) {
@@ -317,7 +319,8 @@ int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 					"!= halfword at 0x%08lx (0x%04x)\n",
 					addr1, hword1, addr2, hword2);
 				rcode = 1;
-				break;
+				nbad++;
+				//break;
 			}
 		}
 		else {
@@ -328,10 +331,20 @@ int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 					"!= byte at 0x%08lx (0x%02x)\n",
 					addr1, byte1, addr2, byte2);
 				rcode = 1;
-				break;
+				nbad++;
+			//	break;
 			}
 		}
-		ngood++;
+
+		if(rcode == 1){
+			rcode = 0;
+			if(nbad > 100){
+				return 1;
+			}
+		}
+		else
+			ngood++;
+
 		addr1 += size;
 		addr2 += size;
 
@@ -343,6 +356,9 @@ int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	printf("Total of %ld %s%s were the same\n",
 		ngood, size == 4 ? "word" : size == 2 ? "halfword" : "byte",
 		ngood == 1 ? "" : "s");
+	printf("Total of %ld %s%s were different\n",
+		nbad, size == 4 ? "word" : size == 2 ? "halfword" : "byte",
+		nbad == 1 ? "" : "s");
 	return rcode;
 }
 
diff --git a/common/cmd_misc.c b/common/cmd_misc.c
index 973b1c2082..5d2a0a30e9 100644
--- a/common/cmd_misc.c
+++ b/common/cmd_misc.c
@@ -26,8 +26,39 @@
  */
 #include <common.h>
 #include <command.h>
+#include <usb/usbserial.h>
+#include <nand.h>
+#include <jffs2/jffs2.h>
+#include <asm/arch/mdcom.h>
+#include <asm/arch/hwcfg.h>
+#include <asm/arch/factory.h>
+#include <asm/arch/prdinfo.h>
+#include <asm/arch/rda_sys.h>
+#include <part.h>
+#include <mmc.h>
+#include <mmc/mmcpart.h>
+#include <nand.h>
+#include <linux/mtd/nand.h>
+#include <mtd/nand/rda_nand.h>
+#include <android/android_boot.h>
+#include <android/android_bootimg.h>
+#include <rda/tgt_ap_panel_setting.h>
+#include <asm/arch/spl_board_info.h>
 
-int do_sleep (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+#ifdef FLASH_PAGE_SIZE
+#undef FLASH_PAGE_SIZE
+#endif
+#define FLASH_PAGE_SIZE 2048
+
+#define rda_dbg(fmt, args...) printf(fmt, ##args)
+
+extern int mtdparts_init_default(void);
+extern int find_dev_and_part(const char *id, struct mtd_device **dev,
+			     u8 *part_num, struct part_info **part);
+
+static int rollback_to_recovery_mode = 0;
+
+int do_sleep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	ulong start = get_timer(0);
 	ulong delay;
@@ -38,18 +69,673 @@ int do_sleep (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	delay = simple_strtoul(argv[1], NULL, 10) * CONFIG_SYS_HZ;
 
 	while (get_timer(start) < delay) {
-		if (ctrlc ())
+		if (ctrlc())
 			return (-1);
 
-		udelay (100);
+		udelay(100);
+	}
+
+	return 0;
+}
+
+int do_flush_dcache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned long start_addr = 0;
+	unsigned long end_addr = 0;
+
+	if (argc < 3) {
+		printf("do flush dcache all...\n");
+		flush_dcache_all();
+		return 0;
+	}
+
+	start_addr = simple_strtoul(argv[1], NULL, 16);
+	end_addr = simple_strtoul(argv[2], NULL, 16);
+
+	printf("flush dcache %#x -> %#x\n", (unsigned int)start_addr, (unsigned int)end_addr);
+	flush_dcache_range(start_addr, end_addr);
+	return 0;
+}
+
+
+int do_mytest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong usec;
+
+	if (argc != 2)
+		return CMD_RET_USAGE;
+
+	usec = simple_strtoul(argv[1], NULL, 10) * 1000000;
+
+	udelay(usec);
+
+	return 0;
+}
+
+int do_rdaswcfg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	u16 swcfg;
+
+	if (argc != 2)
+		return CMD_RET_USAGE;
+
+	swcfg = (u16)simple_strtoul(argv[1], NULL, 10);
+	rda_swcfg_reg_set(swcfg);
+
+	return 0;
+}
+
+int do_rdahwcfg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	printf("RDA: HW_CFG 0x%04x\n", rda_hwcfg_get());
+	return 0;
+}
+
+int do_rdabm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	printf("RDA: Boot_Mode %d\n", rda_bm_get());
+	return 0;
+}
+
+int do_rdabminit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	rda_bm_init();
+
+	return 0;
+}
+
+static int get_lcd_name(void)
+{
+	char lcd_paras[50] = "lcd=";
+	char *lcd_name = (char *)factory_get_lcd_name();
+
+#define PANEL_PARM	"lcd="PANEL_NAME
+
+	setenv("lcd", PANEL_PARM);
+	if (!lcd_name || strlen(lcd_name) == 0) {
+		rda_dbg("factorydata does not contain lcd name, using default\n");
+		return 0;
+	}
+
+	if (strstr(RDA_PANEL_SUPPORT_LIST, lcd_name) == NULL) {
+		rda_dbg("RDA does not support %s lcd panel\n", lcd_name);
+		rda_dbg("Using default, please contact RDA.n");
+		return 0;
+	}
+
+	strncat(lcd_paras, lcd_name, 50);
+	setenv("lcd", lcd_paras);
+	return 0;
+}
+
+
+static int get_bootlogo_name(void)
+{
+	char logo_paras[50] = "bootlogo=";
+#ifdef CONFIG_MACH_RDA8810E//need debug in future
+	char *name = NULL;//(char *)factory_get_bootlogo_name();
+#else
+	char *name = (char *)factory_get_bootlogo_name();
+#endif
+
+	if (!name || strlen(name) == 0) {
+		rda_dbg("Does not find bootlogo name, using default\n");
+		return 0;
 	}
 
+	strncat(logo_paras, name, 50);
+	setenv("bootlogo", logo_paras);
 	return 0;
 }
 
+int do_get_bootlogo_name(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (get_bootlogo_name())
+		return CMD_RET_FAILURE;
+	else
+		return CMD_RET_SUCCESS;
+}
+
+int do_ap_factory_use(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	u8* addr;
+
+	if (argc != 2)
+		return CMD_RET_USAGE;
+	addr = (u8*)simple_strtoul(argv[1], NULL, 16);
+
+	if (factory_set_ap_factory(addr))
+		return CMD_RET_FAILURE;
+	else
+		return CMD_RET_SUCCESS;
+}
+
+int do_ap_factory_update(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	u8* addr;
+
+	if (argc != 2)
+		return CMD_RET_USAGE;
+	addr = (u8*)simple_strtoul(argv[1], NULL, 16);
+
+	if (factory_update_ap_factory(addr))
+		return CMD_RET_FAILURE;
+	else
+		return CMD_RET_SUCCESS;
+}
+
+int do_get_lcd_name(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (get_lcd_name())
+		return CMD_RET_FAILURE;
+	else
+		return CMD_RET_SUCCESS;
+}
+
+int do_get_emmc_id(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	struct spl_emmc_info * emmc_info = get_bd_spl_emmc_info();
+	char emmc_id[16] = {0};
+
+	if(CONFIG_MMC_DEV_NUM == 0)
+		return CMD_RET_SUCCESS;
+
+	sprintf(emmc_id, "emmc_id=%d", emmc_info->manufacturer_id);
+
+	setenv("emmc_id", emmc_id);
+
+	return CMD_RET_SUCCESS;
+}
+
+extern int rda_flash_intf_is_spi(void);
+
+static int do_get_flash_intf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (rda_media_get() == MEDIA_MMC ) {
+#ifdef CONFIG_SDMMC_BOOT
+		setenv("flash_if", "flash_if=sdcard");
+#else
+		setenv("flash_if", "flash_if=emmc");
+#endif
+	} else {
+		if(rda_flash_intf_is_spi())
+			setenv("flash_if", "flash_if=spi");
+		else
+			setenv("flash_if", "flash_if=normal");
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+extern int hal_BoardSetup(void);
+
+static int do_board_mux_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+#ifdef CONFIG_RDA_MUX_CONFIG
+	int ret = 0;
+	ret = hal_BoardSetup();
+	if(ret == CMD_RET_SUCCESS)
+		puts("Board Mux : Done. \n");
+	else
+		puts("Board Mux : Error. \n");
+
+	return ret;
+#else
+	puts("Board Mux : Bypass bootloader board mux config. \n");
+	return CMD_RET_SUCCESS;
+#endif
+}
+
+static int do_get_android_bm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	enum rda_bm_type bm;
+	u32 reset_cause;
+
+	setenv("chargerboot", "0");
+	bm = rda_bm_get();
+	switch (bm) {
+	case RDA_BM_RECOVERY:
+		setenv("androidboot", "androidboot.mode=recovery");
+		break;
+	case RDA_BM_FACTORY:
+		setenv("androidboot", "androidboot.mode=factory");
+		break;
+	default:
+		reset_cause = rda_mdcom_get_reset_cause();
+		if (reset_cause == RDA_RESET_CAUSE_CHARGER) {
+			setenv("androidboot", "androidboot.mode=charger");
+#ifdef CHARGER_IN_RECOVERY
+/* only move charger to recovery partition after aosp 4.4 (including)*/
+			setenv("chargerboot", "1");
+#endif
+		} else {
+			setenv("androidboot", "androidboot.mode=normal");
+		}
+		break;
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+static u8 *recovery_image = (u8 *)SCRATCH_ADDR;
+
+static int load_recovery_from_nand(void)
+{
+	void *data = (void *)recovery_image;
+	struct mtd_info *nand;
+	struct mtd_device *dev;
+	struct part_info *part;
+	size_t size = 0;
+	u8 pnum;
+	int ret;
+
+	ret = find_dev_and_part("recovery", &dev, &pnum, &part);
+	if (ret) {
+		serial_printf("unknown partition name");
+		return CMD_RET_FAILURE;
+	} else if (dev->id->type != MTD_DEV_TYPE_NAND) {
+		serial_printf("mtd dev type error");
+		return CMD_RET_FAILURE;
+	}
+	nand = &nand_info[dev->id->num];
+	serial_printf("found part '%s' offset: 0x%llx length: 0x%llx\n",
+		part->name, part->offset, part->size);
+
+	size = part->size;
+
+	serial_printf("read 0x%x bytes from '%s' offset: 0x%llx\n",
+		size, part->name, part->offset);
+	ret = nand_read_skip_bad(nand, part->offset, &size, (u_char *) data);
+	if (ret) {
+		serial_printf("nand read fail");
+		return CMD_RET_FAILURE;
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+static int load_recovery_from_mmc(void)
+{
+	void *data = (void *)recovery_image;
+	disk_partition_t *ptn;
+	block_dev_desc_t *mmc_blkdev;
+	loff_t size = 0;
+
+	serial_printf("%s\n", __func__);
+	mmc_blkdev = get_dev_by_name(CONFIG_MMC_DEV_NAME);
+	ptn = partition_find_ptn("recovery");
+
+	if (ptn == 0) {
+		serial_printf("mmc partition table doesn't exist");
+		puts("Board Mux : Done. \n");
+		return CMD_RET_FAILURE;
+	}
+
+	size = ptn->size * ptn->blksz;
+
+	serial_printf("read 0x%x bytes from recovery offset: %lx\n", (unsigned int)size,
+		ptn->start);
+	if (partition_read_bytes(mmc_blkdev, ptn, &size, data)) {
+		serial_printf("mmc read failure");
+		return CMD_RET_FAILURE;
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+static int check_recovery_image(void)
+{
+	boot_img_hdr *hdr;
+
+	/* Check recovery image header */
+	hdr = (boot_img_hdr *)recovery_image;
+	if (memcmp(hdr->magic, BOOT_MAGIC, BOOT_MAGIC_SIZE)) {
+		serial_printf("Invalid magic\n");
+		return CMD_RET_FAILURE;
+	}
+
+	if (hdr->page_size != FLASH_PAGE_SIZE) {
+		serial_printf("Invalid page size: %d (expecting %d)\n",
+				hdr->page_size, FLASH_PAGE_SIZE);
+		return CMD_RET_FAILURE;
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+
+static int load_ap_recovery(void)
+{
+	int ret = CMD_RET_SUCCESS;
+	enum media_type media;
+
+	media = rda_media_get();
+	if (media == MEDIA_MMC)
+		ret = load_recovery_from_mmc();
+	else if ((media == MEDIA_NAND) || media == MEDIA_SPINAND)
+		ret = load_recovery_from_nand();
+	else {
+		serial_printf("%s can't find boot media\n", __func__);
+		ret = CMD_RET_FAILURE;
+	}
+
+	if (ret != CMD_RET_SUCCESS) {
+		serial_printf("%s failed, ret is %d\n", __func__, ret);
+		return ret;
+	}
+	ret = check_recovery_image();
+
+	return ret;
+}
+
+/*
+ * For moving charger to recovery image to save 500KB in ramdisk
+ *     CHARGER BOOT mode will need to load recovery kernel and rootfs
+ * 1. load modem from boot image and normal boot image first, so no extra delay
+ *    for normal boot. (rda_mdcom_get_reset_cause only works after modem is up)
+ * 2. after modem is up and CHARGER MODE detected, load recovery image
+ */
+static int do_load_ap_recovery(cmd_tbl_t *cmdtp, int flag, int argc,
+		                   char * const argv[])
+{
+    return load_ap_recovery();
+}
+
+extern int mdcom_load_from_flash(int cal_en);
+extern int mdcom_load_from_mem(const u8 *data, int cal_en);
+extern int mdcom_check_and_wait_modem(int check_boot_key);
+
+static int do_load_recovery(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int ret = CMD_RET_SUCCESS;
+	enum rda_bm_type bm;
+	boot_img_hdr *hdr;
+	unsigned kernel_actual;
+	unsigned ramdisk_actual;
+	unsigned second_actual;
+	unsigned size;
+
+	/* Load recovery modem only in recovery mode, and
+	 * load normal modem in factory mode */
+	bm = rda_bm_get();
+	if (bm != RDA_BM_RECOVERY) {
+		rollback_to_recovery_mode = 1;
+		ret = mdcom_load_from_flash(0);
+		if (ret != CMD_RET_SUCCESS) {
+			serial_printf("Bad modem image. Try recovery mode\n");
+			udelay(5000);
+			rda_reboot(REBOOT_TO_RECOVERY_MODE);
+		}
+	}
+
+	ret = load_ap_recovery();
+	if (ret != CMD_RET_SUCCESS)
+		return ret;
+
+
+	if (bm == RDA_BM_RECOVERY) {
+		hdr = (boot_img_hdr *)recovery_image;
+		kernel_actual = ROUND(hdr->kernel_size, FLASH_PAGE_SIZE);
+		ramdisk_actual = ROUND(hdr->ramdisk_size, FLASH_PAGE_SIZE);
+		second_actual = ROUND(hdr->second_size, FLASH_PAGE_SIZE);
+		size = FLASH_PAGE_SIZE + kernel_actual + ramdisk_actual +
+			second_actual;
+
+		ret = mdcom_load_from_mem(recovery_image + size, 0);
+
+		if (ret != CMD_RET_SUCCESS)
+			return ret;
+	}
+
+	ret = mdcom_check_and_wait_modem(0);
+	if (ret != CMD_RET_SUCCESS && bm != RDA_BM_RECOVERY) {
+		serial_printf("Modem no response. Try recovery mode\n");
+		udelay(5000);
+		rda_reboot(REBOOT_TO_RECOVERY_MODE);
+	}
+
+	return ret;
+}
+
+int load_boot_from_nand(void)
+{
+	boot_img_hdr *hdr;
+	void *data = (void *)SCRATCH_ADDR;
+	struct mtd_info *nand;
+	struct mtd_device *dev;
+	struct part_info *part;
+	size_t size = 0;
+	u8 pnum;
+	unsigned kernel_actual;
+	unsigned ramdisk_actual;
+	int ret;
+
+	ret = find_dev_and_part("boot", &dev, &pnum, &part);
+	if (ret) {
+		rda_dbg("unknown partition name\n");
+		return CMD_RET_FAILURE;
+	} else if (dev->id->type != MTD_DEV_TYPE_NAND) {
+		rda_dbg("mtd dev type error\n");
+		return CMD_RET_FAILURE;
+	}
+	nand = &nand_info[dev->id->num];
+	rda_dbg("found part '%s' offset: 0x%llx length: 0x%llx\n",
+		part->name, part->offset, part->size);
+
+	/* get hdr first */
+	size = ROUND(2048, FLASH_PAGE_SIZE);
+	rda_dbg("read 0x%x bytes from '%s' offset: 0x%llx\n",
+		size, part->name, part->offset);
+
+	ret = nand_read_skip_bad(nand, part->offset, &size, (u_char *) data);
+	if (ret) {
+		rda_dbg("nand read fail\n");
+		return CMD_RET_FAILURE;
+	}
+
+	/* get size from hdr */
+	hdr = (boot_img_hdr *) data;
+	kernel_actual = ROUND(hdr->kernel_size, FLASH_PAGE_SIZE);
+	ramdisk_actual = ROUND(hdr->ramdisk_size, FLASH_PAGE_SIZE);
+	size = 2048 + kernel_actual + ramdisk_actual;
+
+	/* load whole boot.img */
+	rda_dbg("read 0x%x bytes from '%s' offset: 0x%llx\n",
+		size, part->name, part->offset);
+	ret = nand_read_skip_bad(nand, part->offset, &size, (u_char *) data);
+	if (ret) {
+		rda_dbg("nand read fail\n");
+		return CMD_RET_FAILURE;
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+static block_dev_desc_t *mmc_blkdev;
+int load_boot_from_mmc(void)
+{
+	void *data = (void *)SCRATCH_ADDR;
+	disk_partition_t *ptn;
+	loff_t size = 0;
+
+	rda_dbg("%s\n", __func__);
+	mmc_blkdev = get_dev_by_name(CONFIG_MMC_DEV_NAME);
+	ptn = partition_find_ptn("boot");
+
+	if (ptn == 0) {
+		rda_dbg("mmc partition table doesn't exist\n");
+		return CMD_RET_FAILURE;
+	}
+
+	size = ptn->size * ptn->blksz;
+
+	rda_dbg("read 0x%x bytes from boot offset: %lx\n", (unsigned int)size,
+		ptn->start);
+	if (partition_read_bytes(mmc_blkdev, ptn, &size, data)) {
+		rda_dbg("mmc read failure\n");
+		return CMD_RET_FAILURE;
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_load_boot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int ret = CMD_RET_FAILURE;
+	enum media_type media;
+
+	media = rda_media_get();
+	serial_printf("load boot image ...\n");
+	if (media == MEDIA_MMC)
+		ret = load_boot_from_mmc();
+	else if ((media == MEDIA_NAND) || (media == MEDIA_SPINAND))
+		ret = load_boot_from_nand();
+	else
+		serial_printf("load_boot can't find boot media\n");
+
+	return ret;
+}
+
+static int do_adjust_bootdelay(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int bootmode;
+
+	bootmode = rda_bm_get();
+	if (bootmode == RDA_BM_FASTBOOT)
+		setenv("bootdelay", "3");
+
+	return CMD_RET_SUCCESS;
+}
 U_BOOT_CMD(
 	sleep ,    2,    1,     do_sleep,
 	"delay execution for some time",
 	"N\n"
 	"    - delay execution for N seconds (N is _decimal_ !!!)"
 );
+
+U_BOOT_CMD(
+	flush_dcache ,    3,    1,     do_flush_dcache,
+	"flush dcache",
+	"start_addr end_addr\n"
+	"    - flush dcache from [start_addr] to [end_addr]"
+);
+
+U_BOOT_CMD(
+	mytest ,    2,    1,     do_mytest,
+	"exec certain test routine",
+	"arg\n"
+	"    - exec with arg (arg is _decimal_ !!!)"
+);
+
+U_BOOT_CMD(
+	rdaswcfg ,    2,    1,     do_rdaswcfg,
+	"set rda swcfg",
+	"Syntax:\n"
+	"    - rdaswcfg swcfg\n"
+);
+
+U_BOOT_CMD(
+	rdahwcfg ,    1,    1,     do_rdahwcfg,
+	"get rda hwcfg",
+	"Syntax:\n"
+	"    - rdahwcfg\n"
+);
+
+U_BOOT_CMD(
+	rdabm ,    1,    1,     do_rdabm,
+	"get rda boot_mode",
+	"Syntax:\n"
+	"    - rdabm\n"
+);
+
+U_BOOT_CMD(
+	rdabminit ,    1,    1,     do_rdabminit,
+	"init rda boot_mode",
+	"Syntax:\n"
+	"    - rdabminit\n"
+);
+
+U_BOOT_CMD(
+	ap_factory_use ,    2,    1,     do_ap_factory_use,
+	"use ap factory data from specified memory",
+	"Syntax:\n"
+	"    - factory_use addr\n"
+);
+
+
+U_BOOT_CMD(
+	ap_factory_update ,    2,    1,     do_ap_factory_update,
+	"update ap factory data from specified memory",
+	"Syntax:\n"
+	"    - factory_update addr\n"
+);
+
+U_BOOT_CMD(
+	get_lcd_name ,    1,    1,     do_get_lcd_name,
+	"ap find lcd panel name",
+	"Syntax:\n"
+	"    - find_lcd_name\n"
+);
+
+U_BOOT_CMD(
+	get_flash_intf,    1,    1,     do_get_flash_intf,
+	"ap find flash interface",
+	"Syntax:\n"
+	"    - get_flash_intf\n"
+);
+
+U_BOOT_CMD(
+	get_emmc_id,    1,    1,     do_get_emmc_id,
+	"ap find emmc manufacturer id and pass it to kernel",
+	"Syntax:\n"
+	"    - get_emmc_id\n"
+);
+
+U_BOOT_CMD(
+	mux_config,	1,	1,	do_board_mux_config,
+	"check and set board mux config (pinmux,io drive,io pin mode...)",
+	"Syntax:\n"
+	"    - mux_config\n"
+);
+
+U_BOOT_CMD(
+	get_android_bm,    1,    1,     do_get_android_bm,
+	"get android bootmode",
+	"Syntax:\n"
+	"    - get_android_bm \n"
+);
+
+U_BOOT_CMD(
+	load_ap_recovery,    1,    1,     do_load_ap_recovery,
+	"load recovery kernel and ramdisk to address",
+	"Syntax:\n"
+	"    - load_ap_recovery address \n"
+);
+
+U_BOOT_CMD(
+	load_recovery,    1,    1,     do_load_recovery,
+	"load recovery image to address",
+	"Syntax:\n"
+	"    - load_recovery address \n"
+);
+
+U_BOOT_CMD(
+	load_boot,    1,    1,     do_load_boot,
+	"load boot image to address",
+	"Syntax:\n"
+	"    - load_boot address \n"
+);
+
+U_BOOT_CMD(
+	get_bootlogo_name ,    1,    1,     do_get_bootlogo_name,
+	"find bootlogo name",
+	"Syntax:\n"
+	"    - get_bootlogo_name\n"
+);
+
+U_BOOT_CMD(
+	adjust_bootdelay ,    1,    1,     do_adjust_bootdelay,
+	"re-adjust bootdelay according to bootmode",
+	"Syntax:\n"
+	"    - adjust_bootdelay\n"
+);
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
index 750509da5e..674c1f5a7e 100644
--- a/common/cmd_mmc.c
+++ b/common/cmd_mmc.c
@@ -2,23 +2,7 @@
  * (C) Copyright 2003
  * Kyle Harris, kharris@nexus-tech.net
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -92,6 +76,8 @@ enum mmc_state {
 	MMC_READ,
 	MMC_WRITE,
 	MMC_ERASE,
+	MMC_ERASE_PART,
+	MMC_TEST,
 };
 static void print_mmcinfo(struct mmc *mmc)
 {
@@ -106,7 +92,7 @@ static void print_mmcinfo(struct mmc *mmc)
 	printf("Rd Block Len: %d\n", mmc->read_bl_len);
 
 	printf("%s version %d.%d\n", IS_SD(mmc) ? "SD" : "MMC",
-			(mmc->version >> 4) & 0xf, mmc->version & 0xf);
+			(mmc->version >> 8) & 0xf, mmc->version & 0xff);
 
 	printf("High Capacity: %s\n", mmc->high_capacity ? "Yes" : "No");
 	puts("Capacity: ");
@@ -115,13 +101,13 @@ static void print_mmcinfo(struct mmc *mmc)
 	printf("Bus Width: %d-bit\n", mmc->bus_width);
 }
 
-int do_mmcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_mmcinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	struct mmc *mmc;
 
 	if (curr_device < 0) {
 		if (get_mmc_num() > 0)
-			curr_device = 0;
+			curr_device = 1;
 		else {
 			puts("No MMC device available\n");
 			return 1;
@@ -144,11 +130,40 @@ int do_mmcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 U_BOOT_CMD(
 	mmcinfo, 1, 0, do_mmcinfo,
 	"display MMC info",
-	"    - device number of the device to dislay info of\n"
-	""
+	"- display info of the current MMC device"
 );
 
-int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+static int boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
+{
+	int err;
+	err = mmc_boot_part_access(mmc, ack, part_num, access);
+
+	if ((err == 0) && (access != 0)) {
+		printf("\t\t\t!!!Notice!!!\n");
+
+		printf("!You must close EMMC boot Partition");
+		printf("after all images are written\n");
+
+		printf("!EMMC boot partition has continuity");
+		printf("at image writing time.\n");
+
+		printf("!So, do not close the boot partition");
+		printf("before all images are written.\n");
+		return 0;
+	} else if ((err == 0) && (access == 0))
+		return 0;
+	else if ((err != 0) && (access != 0)) {
+		printf("EMMC boot partition-%d OPEN Failed.\n", part_num);
+		return 1;
+	} else {
+		printf("EMMC boot partition-%d CLOSE Failed.\n", part_num);
+		return 1;
+	}
+}
+#endif
+
+static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	enum mmc_state state;
 
@@ -157,7 +172,7 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	if (curr_device < 0) {
 		if (get_mmc_num() > 0)
-			curr_device = 0;
+			curr_device = 1;
 		else {
 			puts("No MMC device available\n");
 			return 1;
@@ -165,8 +180,12 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	}
 
 	if (strcmp(argv[1], "rescan") == 0) {
-		struct mmc *mmc = find_mmc_device(curr_device);
+		struct mmc *mmc;
+
+		if (argc != 2)
+			return CMD_RET_USAGE;
 
+		mmc = find_mmc_device(curr_device);
 		if (!mmc) {
 			printf("no mmc device at slot %x\n", curr_device);
 			return 1;
@@ -180,8 +199,12 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			return 0;
 	} else if (strncmp(argv[1], "part", 4) == 0) {
 		block_dev_desc_t *mmc_dev;
-		struct mmc *mmc = find_mmc_device(curr_device);
+		struct mmc *mmc;
+
+		if (argc != 2)
+			return CMD_RET_USAGE;
 
+		mmc = find_mmc_device(curr_device);
 		if (!mmc) {
 			printf("no mmc device at slot %x\n", curr_device);
 			return 1;
@@ -197,8 +220,56 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		puts("get mmc type error!\n");
 		return 1;
 	} else if (strcmp(argv[1], "list") == 0) {
+		if (argc != 2)
+			return CMD_RET_USAGE;
 		print_mmc_devices('\n');
 		return 0;
+	} else if (strncmp(argv[1], "speed", 5) == 0) {
+		struct mmc *mmc;
+		int ret;
+		u64 offset;
+		unsigned long long start_clock, end_clock;
+		unsigned long duration, mmc_read_speed, mmc_write_speed;
+		u_char *datbuf;
+		size_t test_data_size;
+
+		if (argc < 5) {
+			datbuf = (u_char *)(0x80000000);
+			offset = (u64)(0x00100000);
+			test_data_size = (size_t)(0x00A00000);
+		} else {
+			datbuf = (u_char *)simple_strtoul(argv[2], NULL, 16);
+			offset = (u64)simple_strtoul(argv[3], NULL, 16);
+			test_data_size = (size_t)simple_strtoul(argv[4], NULL, 16);
+		}
+
+		mmc = find_mmc_device(curr_device);
+		mmc_init(mmc);
+
+		start_clock = get_ticks();
+		ret = mmc_read(mmc, offset, datbuf, test_data_size);
+		end_clock = get_ticks();
+		duration = (unsigned long)(end_clock - start_clock);
+		mmc_read_speed = (unsigned long)(test_data_size / (duration * 1000 / get_tbclk()) * 1000 / 1024);
+		if (ret == test_data_size)
+			printf("\nMmc Read speed = %ld Kbyte/s\n", mmc_read_speed);
+		else {
+			printf("\nRead data from Mmc failed\n");
+			return 1;
+		}
+
+		start_clock = get_ticks();
+		ret = mmc_write(mmc, offset, datbuf, test_data_size);
+		end_clock = get_ticks();
+		duration = (unsigned long)(end_clock - start_clock);
+		mmc_write_speed = (unsigned long)(test_data_size / (duration * 1000 / get_tbclk()) * 1000 / 1024);
+		if (ret == test_data_size)
+			printf("\nMmc Write speed = %ld Kbyte/s\n", mmc_write_speed);
+		else {
+			printf("\nWrite data to Mmc failed\n");
+			return 1;
+		}
+		return 0;
 	} else if (strcmp(argv[1], "dev") == 0) {
 		int dev, part = -1;
 		struct mmc *mmc;
@@ -237,7 +308,7 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 				if (!ret)
 					mmc->part_num = part;
 
-				printf("switch to partions #%d, %s\n",
+				printf("switch to partitions #%d, %s\n",
 						part, (!ret) ? "OK" : "ERROR");
 			}
 		}
@@ -249,41 +320,132 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 				curr_device, mmc->part_num);
 
 		return 0;
-	}
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+	} else if ((strcmp(argv[1], "open") == 0) ||
+			(strcmp(argv[1], "close") == 0)) {
+		int dev;
+		struct mmc *mmc;
+		u8 part_num, access = 0;
 
-	if (strcmp(argv[1], "read") == 0)
+		if (argc == 4) {
+			dev = simple_strtoul(argv[2], NULL, 10);
+			part_num = simple_strtoul(argv[3], NULL, 10);
+		} else {
+			return CMD_RET_USAGE;
+		}
+
+		mmc = find_mmc_device(dev);
+		if (!mmc) {
+			printf("no mmc device at slot %x\n", dev);
+			return 1;
+		}
+
+		if (IS_SD(mmc)) {
+			printf("SD device cannot be opened/closed\n");
+			return 1;
+		}
+
+		if ((part_num <= 0) || (part_num > MMC_NUM_BOOT_PARTITION)) {
+			printf("Invalid boot partition number:\n");
+			printf("Boot partition number cannot be <= 0\n");
+			printf("EMMC44 supports only 2 boot partitions\n");
+			return 1;
+		}
+
+		if (strcmp(argv[1], "open") == 0)
+			access = part_num; /* enable R/W access to boot part*/
+		else
+			access = 0; /* No access to boot partition */
+
+		/* acknowledge to be sent during boot operation */
+		return boot_part_access(mmc, 1, part_num, access);
+
+	} else if (strcmp(argv[1], "bootpart") == 0) {
+		int dev;
+		dev = simple_strtoul(argv[2], NULL, 10);
+
+		u32 bootsize = simple_strtoul(argv[3], NULL, 10);
+		u32 rpmbsize = simple_strtoul(argv[4], NULL, 10);
+		struct mmc *mmc = find_mmc_device(dev);
+		if (!mmc) {
+			printf("no mmc device at slot %x\n", dev);
+			return 1;
+		}
+
+		if (IS_SD(mmc)) {
+			printf("It is not a EMMC device\n");
+			return 1;
+		}
+
+		if (0 == mmc_boot_partition_size_change(mmc,
+							bootsize, rpmbsize)) {
+			printf("EMMC boot partition Size %d MB\n", bootsize);
+			printf("EMMC RPMB partition Size %d MB\n", rpmbsize);
+			return 0;
+		} else {
+			printf("EMMC boot partition Size change Failed.\n");
+			return 1;
+		}
+#endif /* CONFIG_SUPPORT_EMMC_BOOT */
+	}
+	state = MMC_INVALID;
+	if (argc == 5 && strcmp(argv[1], "read") == 0)
 		state = MMC_READ;
-	else if (strcmp(argv[1], "write") == 0)
+	else if (argc == 5 && strcmp(argv[1], "write") == 0)
 		state = MMC_WRITE;
-	else if (strcmp(argv[1], "erase") == 0)
+	else if (argc == 6 && strcmp(argv[1], "test") == 0)
+		state = MMC_TEST;
+	else if (argc == 4 && strcmp(argv[1], "erase") == 0)
 		state = MMC_ERASE;
-	else
-		state = MMC_INVALID;
+	else if (argc == 3 && strcmp(argv[1], "erase.part") == 0)
+		state = MMC_ERASE_PART;
 
 	if (state != MMC_INVALID) {
 		struct mmc *mmc = find_mmc_device(curr_device);
 		int idx = 2;
 		u32 blk, cnt, n;
-		void *addr;
-
-		if (state != MMC_ERASE) {
-			addr = (void *)simple_strtoul(argv[idx], NULL, 16);
-			++idx;
-		} else
-			addr = 0;
-		blk = simple_strtoul(argv[idx], NULL, 16);
-		cnt = simple_strtoul(argv[idx + 1], NULL, 16);
+		void *addr = NULL;
+		int times = 10;
 
 		if (!mmc) {
 			printf("no mmc device at slot %x\n", curr_device);
 			return 1;
 		}
 
-		printf("\nMMC %s: dev # %d, block # %d, count %d ... ",
-				argv[1], curr_device, blk, cnt);
-
 		mmc_init(mmc);
 
+		if ((state == MMC_WRITE || state == MMC_ERASE)) {
+			if (mmc_getwp(mmc) == 1) {
+				printf("Error: card is write protected!\n");
+				return 1;
+			}
+		}
+
+		if (state == MMC_ERASE_PART) {
+			disk_partition_t *ptn;
+			ptn = partition_find_ptn(argv[idx]);
+			if (!ptn) {
+				printf("Error: not found part [%s]\n", argv[idx]);
+				return 1;
+			}
+			blk = ptn->start;
+			cnt = ptn->size;
+			state = MMC_ERASE;
+
+		} else {
+			if (state != MMC_ERASE) {
+				addr = (void *)simple_strtoul(argv[idx], NULL, 16);
+				++idx;
+			}
+			blk = simple_strtoul(argv[idx], NULL, 16);
+			cnt = simple_strtoul(argv[idx + 1], NULL, 16);
+			if (state == MMC_TEST)
+				times = simple_strtoul(argv[idx + 2], NULL, 10);
+		}
+
+		printf("\nMMC %s: dev # %d, block # %d, count %d ... ",
+					argv[1], curr_device, blk, cnt);
+
 		switch (state) {
 		case MMC_READ:
 			n = mmc->block_dev.block_read(curr_device, blk,
@@ -298,6 +460,51 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		case MMC_ERASE:
 			n = mmc->block_dev.block_erase(curr_device, blk, cnt);
 			break;
+		case MMC_TEST:
+			{
+				u32 pat = 0x5a5a1234;
+				u32 *dat = addr;
+				u32 crc1 = 0, crc2 = 0;
+				u32 siz = cnt * 512;
+				int i, t;
+
+				/* test write/read */
+				n = cnt;
+				printf("\nTest start...\n");
+				for(t = 1; t <= times; t++)
+				{
+					/* fill buffer by pattern */
+					dat = addr;
+					for(i = 0; i < siz; i += 4)
+					{
+						*dat++ = pat;
+						pat += 0x10001;
+					}
+					crc1 = crc32(0, (void *)addr, siz);
+					pat = ~pat;
+
+					/* write to device */
+					mmc->block_dev.block_write(curr_device, blk, cnt, addr);
+
+					/* clear buffer */
+					memset((void*)addr, 0, siz);
+
+					/* read back */
+					mmc->block_dev.block_read(curr_device, blk, cnt, addr);
+					flush_cache((ulong)addr, cnt * 512);
+
+					/* compare and show result */
+					crc2 = crc32(0, (void *)addr, siz);
+					printf("Test %02d: expect crc = 0x%08x, got = 0x%08x, %s\n", 
+							t, crc1, crc2, 
+							(crc1==crc2) ? "SUCCESS!" : "FAIL!");
+
+					/* make fail tag */
+					if(crc1 != crc2)
+						n = cnt - 1;
+				}
+			}
+			break;
 		default:
 			BUG();
 		}
@@ -315,9 +522,20 @@ U_BOOT_CMD(
 	"MMC sub system",
 	"read addr blk# cnt\n"
 	"mmc write addr blk# cnt\n"
+	"mmc test addr blk# cnt times\n"
 	"mmc erase blk# cnt\n"
+	"mmc erase.part part_name\n"
 	"mmc rescan\n"
 	"mmc part - lists available partition on current mmc device\n"
 	"mmc dev [dev] [part] - show or set current mmc device [partition]\n"
-	"mmc list - lists available devices");
+	"mmc list - lists available devices\n"
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+	"mmc open <dev> <boot_partition>\n"
+	" - Enable boot_part for booting and enable R/W access of boot_part\n"
+	"mmc close <dev> <boot_partition>\n"
+	" - Enable boot_part for booting and disable access to boot_part\n"
+	"mmc bootpart <device num> <boot part size MB> <RPMB part size MB>\n"
+	" - change sizes of boot and RPMB partitions of specified device\n"
 #endif
+	);
+#endif /* !CONFIG_GENERIC_MMC */
diff --git a/common/cmd_mtdparts.c b/common/cmd_mtdparts.c
index 22688293ae..add0585037 100644
--- a/common/cmd_mtdparts.c
+++ b/common/cmd_mtdparts.c
@@ -99,6 +99,7 @@
 #if defined(CONFIG_CMD_NAND)
 #include <linux/mtd/nand.h>
 #include <nand.h>
+#include <mtd/nand/rda_nand.h>
 #endif
 
 #if defined(CONFIG_CMD_ONENAND)
@@ -325,7 +326,7 @@ static int part_validate_eraseblock(struct mtdids *id, struct part_info *part)
 {
 	struct mtd_info *mtd = NULL;
 	int i, j;
-	ulong start;
+	u64 start;
 
 	if (get_mtd_info(id->type, id->num, &mtd))
 		return 1;
@@ -337,7 +338,7 @@ static int part_validate_eraseblock(struct mtdids *id, struct part_info *part)
 		 * Only one eraseregion (NAND, OneNAND or uniform NOR),
 		 * checking for alignment is easy here
 		 */
-		if ((unsigned long)part->offset % mtd->erasesize) {
+		if (part->offset % (u64)mtd->erasesize) {
 			printf("%s%d: partition (%s) start offset"
 			       "alignment incorrect\n",
 			       MTD_DEV_TYPE(id->type), id->num, part->name);
@@ -412,19 +413,20 @@ static int part_validate(struct mtdids *id, struct part_info *part)
 		part->size = id->size - part->offset;
 
 	if (part->offset > id->size) {
-		printf("%s: offset %08x beyond flash size %08x\n",
+		printf("%s: offset %llx beyond flash size 0x%llx\n",
 				id->mtd_id, part->offset, id->size);
 		return 1;
 	}
 
-	if ((part->offset + part->size) <= part->offset) {
+	if (((u64)part->offset + (u64)part->size) <= (u64)part->offset) {
 		printf("%s%d: partition (%s) size too big\n",
 				MTD_DEV_TYPE(id->type), id->num, part->name);
 		return 1;
 	}
 
 	if (part->offset + part->size > id->size) {
-		printf("%s: partitioning exceeds flash size\n", id->mtd_id);
+		printf("%s: partitioning exceeds flash size %llx, part %llx+%llx\n",
+			id->mtd_id, id->size, part->offset, part->size);
 		return 1;
 	}
 
@@ -462,7 +464,7 @@ static int part_del(struct mtd_device *dev, struct part_info *part)
 			if (curr_pi == part) {
 				printf("current partition deleted, resetting current to 0\n");
 				current_mtd_partnum = 0;
-			} else if (part->offset <= curr_pi->offset) {
+			} else if (part->offset <= (u64)curr_pi->offset) {
 				current_mtd_partnum--;
 			}
 			current_save_needed = 1;
@@ -595,8 +597,7 @@ static int part_add(struct mtd_device *dev, struct part_info *part)
 static int part_parse(const char *const partdef, const char **ret, struct part_info **retpart)
 {
 	struct part_info *part;
-	unsigned long size;
-	unsigned long offset;
+	u64 size, offset;
 	const char *name;
 	int name_len;
 	unsigned int mask_flags;
@@ -615,7 +616,7 @@ static int part_parse(const char *const partdef, const char **ret, struct part_i
 	} else {
 		size = memsize_parse(p, &p);
 		if (size < MIN_PART_SIZE) {
-			printf("partition size too small (%lx)\n", size);
+			printf("partition size too small (%llx)\n", size);
 			return 1;
 		}
 	}
@@ -680,6 +681,8 @@ static int part_parse(const char *const partdef, const char **ret, struct part_i
 	part->offset = offset;
 	part->mask_flags = mask_flags;
 	part->name = (char *)(part + 1);
+	/*we set the mtdpart is dirty and force erase before program if needed*/
+	part->dirty = 1;
 
 	if (name) {
 		/* copy user provided name */
@@ -687,14 +690,14 @@ static int part_parse(const char *const partdef, const char **ret, struct part_i
 		part->auto_name = 0;
 	} else {
 		/* auto generated name in form of size@offset */
-		sprintf(part->name, "0x%08lx@0x%08lx", size, offset);
+		sprintf(part->name, "0x%llx@0x%llx", size, offset);
 		part->auto_name = 1;
 	}
 
 	part->name[name_len - 1] = '\0';
 	INIT_LIST_HEAD(&part->link);
 
-	debug("+ partition: name %-22s size 0x%08x offset 0x%08x mask flags %d\n",
+	debug("+ partition: name %-22s size 0x%llx offset 0x%llx mask flags %d\n",
 			part->name, part->size,
 			part->offset, part->mask_flags);
 
@@ -710,7 +713,7 @@ static int part_parse(const char *const partdef, const char **ret, struct part_i
  * @param size a pointer to the size of the mtd device (output)
  * @return 0 if device is valid, 1 otherwise
  */
-int mtd_device_validate(u8 type, u8 num, u32 *size)
+int mtd_device_validate(u8 type, u8 num, u64 *size)
 {
 	struct mtd_info *mtd = NULL;
 
@@ -843,7 +846,7 @@ static int device_parse(const char *const mtd_dev, const char **ret, struct mtd_
 	LIST_HEAD(tmp_list);
 	struct list_head *entry, *n;
 	u16 num_parts;
-	u32 offset;
+	u64 offset;
 	int err = 1;
 
 	debug("===device_parse===\n");
@@ -1087,7 +1090,8 @@ static int generate_mtdparts(char *buf, u32 buflen)
 	struct part_info *part, *prev_part;
 	char *p = buf;
 	char tmpbuf[32];
-	u32 size, offset, len, part_cnt;
+	u64 size, offset;
+	u32 len, part_cnt;
 	u32 maxlen = buflen - 1;
 
 	debug("--- generate_mtdparts ---\n");
@@ -1274,7 +1278,7 @@ static void print_partition_table(void)
 			part = list_entry(pentry, struct part_info, link);
 			net_size = net_part_size(mtd, part);
 			size_note = part->size == net_size ? " " : " (!)";
-			printf("%2d: %-20s0x%08x\t0x%08x%s\t0x%08x\t%d\n",
+			printf("%2d: %-20s0x%llx\t0x%08x%s\t0x%llx\t%d\n",
 					part_num, part->name, part->size,
 					net_size, size_note, part->offset,
 					part->mask_flags);
@@ -1286,7 +1290,7 @@ static void print_partition_table(void)
 
 		list_for_each(pentry, &dev->parts) {
 			part = list_entry(pentry, struct part_info, link);
-			printf("%2d: %-20s0x%08x\t0x%08x\t%d\n",
+			printf("%2d: %-20s0x%llx\t0x%llx\t%d\n",
 					part_num, part->name, part->size,
 					part->offset, part->mask_flags);
 #endif /* defined(CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES) */
@@ -1299,6 +1303,41 @@ static void print_partition_table(void)
 }
 
 /**
+ * Given nand partition number find the partition info and
+ * corresponding nand device
+ *
+ * @param part_num  nand partition number
+ * @param part pointer to requested partition (output)
+ * @param nand pointer to the nand device (output)
+ * @return 0 on success, -1 otherwise
+ */
+int find_nand_part_info(int part_num, struct part_info **part,
+		struct mtd_info **nand)
+{
+	struct list_head *dentry;
+	struct mtd_device *dev;
+
+	if (list_empty(&devices)) {
+		printf("no partitions defined\n");
+		return -1;
+	}
+
+	list_for_each(dentry, &devices) {
+		dev = list_entry(dentry, struct mtd_device, link);
+		/* list partitions for given device */
+
+		if (dev->id->type == MTD_DEV_TYPE_NAND) {
+			*part = mtd_part_info(dev, part_num);
+			if (!part)
+				return -1;
+			*nand = &nand_info[dev->id->num];
+			return 0;
+		}
+	}
+
+	return -1;
+}
+/**
  * Format and print out a partition list for each device from global device
  * list.
  */
@@ -1313,7 +1352,7 @@ static void list_partitions(void)
 	if (current_mtd_dev) {
 		part = mtd_part_info(current_mtd_dev, current_mtd_partnum);
 		if (part) {
-			printf("\nactive partition: %s%d,%d - (%s) 0x%08x @ 0x%08x\n",
+			printf("\nactive partition: %s%d,%d - (%s) 0x%llx @ 0x%llx\n",
 					MTD_DEV_TYPE(current_mtd_dev->id->type),
 					current_mtd_dev->id->num, current_mtd_partnum,
 					part->name, part->size, part->offset);
@@ -1413,7 +1452,7 @@ static int delete_partition(const char *id)
 
 	if (find_dev_and_part(id, &dev, &pnum, &part) == 0) {
 
-		debug("delete_partition: device = %s%d, partition %d = (%s) 0x%08x@0x%08x\n",
+		debug("delete_partition: device = %s%d, partition %d = (%s) 0x%llx@0x%llx\n",
 				MTD_DEV_TYPE(dev->id->type), dev->id->num, pnum,
 				part->name, part->size, part->offset);
 
@@ -1502,7 +1541,7 @@ static int spread_partitions(void)
 			part = list_entry(pentry, struct part_info, link);
 
 			debug("spread_partitions: device = %s%d, partition %d ="
-				" (%s) 0x%08x@0x%08x\n",
+				" (%s) 0x%08x@0x%llx\n",
 				MTD_DEV_TYPE(dev->id->type), dev->id->num,
 				part_num, part->name, part->size,
 				part->offset);
@@ -1599,7 +1638,7 @@ static int parse_mtdids(const char *const ids)
 	struct list_head *entry, *n;
 	struct mtdids *id_tmp;
 	u8 type, num;
-	u32 size;
+	u64 size;
 	int ret = 1;
 
 	debug("\n---parse_mtdids---\nmtdids = %s\n\n", ids);
@@ -1673,7 +1712,7 @@ static int parse_mtdids(const char *const ids)
 		id->mtd_id[mtd_id_len - 1] = '\0';
 		INIT_LIST_HEAD(&id->link);
 
-		debug("+ id %s%d\t%16d bytes\t%s\n",
+		debug("+ id %s%d\t%lld bytes\t%s\n",
 				MTD_DEV_TYPE(id->type), id->num,
 				id->size, id->mtd_id);
 
@@ -1829,6 +1868,296 @@ int mtdparts_init(void)
 	return 0;
 }
 
+/* Load mtd partition table from flash */
+static int mtdparts_ptbl_read(char *data)
+{
+	nand_info_t *nand;
+	int dev = nand_curr_device;
+	int ret = 0;
+	char *buff;
+	size_t rsize;
+	u32 offs = CONFIG_MTD_PTBL_OFFS;
+	u32 data_size, data_crc;
+
+	if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE ||
+		!nand_info[dev].name) {
+		printf("%s: nand not init.\n", __func__);
+		return -1;
+	}
+	nand = &nand_info[dev];
+
+	{
+		struct nand_chip *this = nand->priv;
+		struct rda_nand_info *info = this->priv;
+		offs = (offs * info->spl_adjust_ratio) / 2;
+	}
+
+	buff = malloc(CONFIG_MTD_PTBL_SIZE);
+	if(!buff) {
+		printf("%s: can't malloc memory.\n", __func__);
+		return -1;
+	}
+
+	/* calculate read size */
+	rsize = nand->erasesize - (offs % nand->erasesize);
+	if(rsize > CONFIG_MTD_PTBL_SIZE) {
+		rsize = CONFIG_MTD_PTBL_SIZE;
+	}
+
+	/* read data from flash */
+	ret = nand_read_skip_bad(nand, offs, &rsize, (u_char *)buff);
+	if(ret) {
+		printf("%s: flash read error %d\n", __func__, ret);
+		ret = -1;
+		goto exit;
+	}
+
+	memcpy((void*)&data_size, (void*)&buff[0], 4);
+	memcpy((void*)&data_crc, (void*)&buff[4], 4);
+	if(!data_size || data_size > (CONFIG_MTD_PTBL_SIZE - 8)) {
+		printf("%s: partition table is invalid.\n", __func__);
+		ret = -1;
+		goto exit;
+	}
+
+	/* crc checking */
+	if(data_crc != crc32(0, (const unsigned char *)(&buff[8]), data_size)) {
+		printf("%s: crc checking failed.\n", __func__);
+		ret = -1;
+		goto exit;
+	}
+
+	memcpy(data, (void*)&buff[8], data_size);
+	printf("%s: load partition table from %#x\n", __func__, offs);
+	printf("partition table: %s\n", data);
+
+exit:
+	free(buff);
+	return ret;
+}
+
+/* save mtd partition table to flash */
+static int mtdparts_ptbl_write(char *data, int need_erase)
+{
+	nand_info_t *nand;
+	int dev = nand_curr_device;
+	int ret = 0;
+	size_t wsize, rsize;
+	char *buff;
+	u32 offs = CONFIG_MTD_PTBL_OFFS;
+	nand_erase_options_t opts;
+	u32 data_size = strlen(data) + 1;
+	u32 data_crc;
+
+	buff = malloc(CONFIG_MTD_PTBL_SIZE);
+	if(!buff) {
+		printf("%s: can't malloc memory.\n", __func__);
+		return -1;
+	}
+
+	/* check if the new table is same as old */
+	if(mtdparts_ptbl_read(buff) == 0) {
+		if(strcmp(buff, data) == 0) {
+			printf("%s: same as old, do nothing.\n", __func__);
+			free(buff);
+			return 0;
+		}
+	}
+	free(buff);
+
+	if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE ||
+		!nand_info[dev].name) {
+		printf("%s: nand not init.\n", __func__);
+		return -1;
+	}
+	nand = &nand_info[dev];
+
+	{
+		printf("mtdparts_ptbl_write0: offs = 0x%x \n", offs);
+		struct nand_chip *this = nand->priv;
+		struct rda_nand_info *info = this->priv;
+		offs = (offs * info->spl_adjust_ratio) / 2;
+		printf("mtdparts_ptbl_write1: offs = 0x%x \n", offs);
+	}
+
+	printf("%s: save partition table to %#x\n", __func__, offs);
+	printf("%s: %s\n", __func__, data);
+
+	/* Limit data in one block */
+	if(data_size > (CONFIG_MTD_PTBL_SIZE - 8) ||
+		data_size > (nand->erasesize - (offs % nand->erasesize) - 8)) {
+		printf("%s: data size is too large.\n", __func__);
+		return -1;
+	}
+
+	buff = malloc(nand->erasesize);
+	if(!buff) {
+		printf("%s: can't malloc memory.\n", __func__);
+		return -1;
+	}
+
+	/* not need to do erase */
+	if(!need_erase) {
+		/* fill buffer */
+		data_crc = crc32(0, (const unsigned char *)data, data_size);
+		memcpy((void *)(buff), &data_size, 4);
+		memcpy((void *)(buff+4), &data_crc, 4);
+		memcpy((void *)(buff+8), data, data_size);
+
+		/* write data to flash */
+		wsize = data_size + 8;
+		ret = nand_write_skip_bad(nand, offs, &wsize, (u_char *)buff, 0);
+		if(ret) {
+			printf("%s: flash write error %d\n", __func__, ret);
+		}
+		goto exit;
+	}
+
+	/* need to do erase */
+
+	memset(&opts, 0, sizeof(opts));
+	opts.offset = (loff_t) (offs - (offs % nand->erasesize));
+	opts.length = (loff_t) nand->erasesize;
+	opts.jffs2 = 0;
+	opts.quiet = 0;
+
+	/* Read this block data to buffer */
+	rsize = nand->erasesize;
+	ret = nand_read_skip_bad(nand, opts.offset, &rsize, (u_char *)buff);
+	if(ret) {
+		printf("%s: flash read error %d\n", __func__, ret);
+		goto exit;
+	}
+
+	/* erase block */
+	ret = nand_erase_opts(nand, &opts);
+	if(ret) {
+		printf("%s: flash erase error %d\n", __func__, ret);
+		goto exit;
+	}
+
+	/* fill buffer */
+	data_crc = crc32(0, (const unsigned char *)data, data_size);
+	memcpy((void *)(buff+(offs % nand->erasesize)), &data_size, 4);
+	memcpy((void *)(buff+(offs % nand->erasesize)+4), &data_crc, 4);
+	memcpy((void *)(buff+(offs % nand->erasesize)+8), data, data_size);
+
+	/* write data to flash */
+	wsize = nand->erasesize;
+	ret = nand_write_skip_bad(nand, opts.offset, &wsize, (u_char *)buff, 0);
+	if(ret) {
+		printf("%s: flash write error %d\n", __func__, ret);
+	}
+
+exit:
+	free(buff);
+	return ret;
+}
+
+int mtdparts_init_from_ptbl(void)
+{
+	char *mtdparts_str = malloc(CONFIG_MTD_PTBL_SIZE);
+
+	setenv("mtdparts", (char *)mtdparts_default);
+
+	/* load partition table from flash */
+	if(mtdparts_str){
+		if(mtdparts_ptbl_read(mtdparts_str) == 0) {
+			setenv("mtdparts", mtdparts_str);
+		}
+		free(mtdparts_str);
+	}
+
+	setenv("mtdids", (char *)mtdids_default);
+	setenv("partition", NULL);
+
+	return mtdparts_init();
+}
+
+int mtdparts_save_ptbl(int need_erase)
+{
+	if(mtdparts_ptbl_write((char *)mtdparts_default, need_erase)){
+		printf("%s: save partition table failed.\n", __func__);
+		return -1;
+	}
+	return 0;
+}
+
+int mtdparts_init_default(void)
+{
+	setenv("mtdids", (char *)mtdids_default);
+	setenv("mtdparts", (char *)mtdparts_default);
+	setenv("partition", NULL);
+
+	return mtdparts_init();
+}
+
+/* Check if the partition table is same with the table stored in flash */
+int mtdparts_ptbl_check(int *same)
+{
+	int ret;
+	char *buff;
+
+	if(!same) return -1;
+	*same = 0;
+
+	if(!mtdparts_default) {
+		return -1;
+	}
+
+	buff = malloc(CONFIG_MTD_PTBL_SIZE);
+	if(!buff) {
+		printf("%s: can't malloc memory.\n", __func__);
+		return -1;
+	}
+
+	ret = mtdparts_ptbl_read(buff);
+	if(!ret) {
+		printf("mtdparts_default: %s\n", mtdparts_default);
+		printf("mtdparts_in_flash: %s\n", buff);
+		if(strcmp(buff, mtdparts_default) == 0) {
+			*same = 1;
+		}
+	}
+
+	free(buff);
+	return ret;
+}
+
+/* Check if the part(bootloader & factorydata) of partition
+   table is same with the table stored in flash */
+int mtdparts_ptbl_check_factorydata(int *same)
+{
+	int ret;
+	char *buff;
+
+	if(!same) return -1;
+	*same = 0;
+
+	if(!mtdparts_default) {
+		return -1;
+	}
+
+	buff = malloc(CONFIG_MTD_PTBL_SIZE);
+	if(!buff) {
+		printf("%s: can't malloc memory.\n", __func__);
+		return -1;
+	}
+
+	ret = mtdparts_ptbl_read(buff);
+	if(!ret) {
+		int len = strstr(buff, "factorydata") - buff;
+		//printf("mtdparts_default: %s\n", mtdparts_default);
+		//printf("mtdparts_in_flash: %s\n", buff);
+		if(strncmp(buff, mtdparts_default, len) == 0) {
+			*same = 1;
+		}
+	}
+
+	free(buff);
+	return ret;
+}
+
 /**
  * Return pointer to the partition of a requested number from a requested
  * device.
@@ -1870,6 +2199,23 @@ static struct part_info* mtd_part_info(struct mtd_device *dev, unsigned int part
 	return NULL;
 }
 
+int mtdparts_clear_all_dirty(struct mtd_device *dev)
+{
+	struct list_head *entry;
+	struct part_info *part;
+
+	if(!dev)
+		return -1;
+
+	printf("clear all %d mtdparts's dirty\n", dev->num_parts);
+	list_for_each(entry, &dev->parts) {
+		part = list_entry(entry, struct part_info, link);
+		if (part)
+			part->dirty = 0;
+	}
+	return 0;
+
+}
 /***************************************************/
 /* U-boot commands				   */
 /***************************************************/
diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index bae630dfb6..cdd1258b1b 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -11,7 +11,7 @@
  * Added 16-bit nand support
  * (C) 2004 Texas Instruments
  *
- * Copyright 2010 Freescale Semiconductor
+ * Copyright 2010, 2012 Freescale Semiconductor
  * The portions of this file whose copyright is held by Freescale and which
  * are not considered a derived work of GPL v2-only code may be distributed
  * and/or modified under the terms of the GNU General Public License as
@@ -27,6 +27,7 @@
 #include <asm/byteorder.h>
 #include <jffs2/jffs2.h>
 #include <nand.h>
+#include <mtd/nand/rda_nand.h>
 
 #if defined(CONFIG_CMD_MTDPARTS)
 
@@ -37,11 +38,17 @@ int find_dev_and_part(const char *id, struct mtd_device **dev,
 		      u8 *part_num, struct part_info **part);
 #endif
 
-static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
+static int nand_dump(nand_info_t *nand, uint64_t off, int only_oob, int repeat)
 {
 	int i;
 	u_char *datbuf, *oobbuf, *p;
 	static loff_t last;
+	struct nand_chip *chip = nand->priv;
+	struct rda_nand_info *info = chip->priv;
+
+	/* just for dump nand first 16k bytes in nand driver V3,*/
+	/* no care to nand driver V1. */
+	info->dump_debug_flag = 1;
 
 	if (repeat)
 		off = last + nand->writesize;
@@ -54,7 +61,13 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
 		puts("No memory for page buffer\n");
 		return 1;
 	}
-	off &= ~(nand->writesize - 1);
+
+	/* off is 64 bit*/
+	if(chip->page_shift == 0)
+		off = (loff_t)mtd_div_by_ws(off, nand) * nand->writesize;
+	else
+		off &= ~((loff_t)nand->writesize - 1);
+
 	loff_t addr = (loff_t) off;
 	struct mtd_oob_ops ops;
 	memset(&ops, 0, sizeof(ops));
@@ -65,12 +78,12 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
 	ops.mode = MTD_OOB_RAW;
 	i = nand->read_oob(nand, addr, &ops);
 	if (i < 0) {
-		printf("Error (%d) reading page %08lx\n", i, off);
+		printf("Error (%d) reading page 0x%llx\n", i, off);
 		free(datbuf);
 		free(oobbuf);
 		return 1;
 	}
-	printf("Page %08lx dump:\n", off);
+	printf("Page 0x%llx dump:\n", off);
 	i = nand->writesize >> 4;
 	p = datbuf;
 
@@ -91,6 +104,8 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
 		       p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
 		p += 8;
 	}
+
+	info->dump_debug_flag = 0;
 	free(datbuf);
 	free(oobbuf);
 
@@ -191,7 +206,7 @@ static int arg_off_size(int argc, char *const argv[], int *idx,
 			loff_t *off, loff_t *size)
 {
 	int ret;
-	loff_t maxsize;
+	loff_t maxsize = 0;
 
 	if (argc == 0) {
 		*off = 0;
@@ -277,6 +292,7 @@ int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char *const argv[])
 	int ret;
 	uint32_t oob_buf[ENV_OFFSET_SIZE/sizeof(uint32_t)];
 	nand_info_t *nand = &nand_info[0];
+	struct nand_chip *chip = nand->priv;
 	char *cmd = argv[1];
 
 	if (CONFIG_SYS_MAX_NAND_DEVICE == 0 || !nand->name) {
@@ -319,9 +335,16 @@ int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char *const argv[])
 			return 1;
 		}
 
-		if ((addr & (nand->erasesize - 1)) != 0) {
-			printf("Environment offset must be block-aligned\n");
-			return 1;
+		if (chip->bbt_erase_shift == 0) {
+			if(mtd_mod_by_eb(addr, nand) != 0){
+				printf("Environment offset must be block-aligned\n");
+				return 1;
+			}
+		} else {
+			if ((addr & (nand->erasesize - 1)) != 0) {
+				printf("Environment offset must be block-aligned\n");
+				return 1;
+			}
 		}
 
 		ops.datbuf = NULL;
@@ -390,6 +413,47 @@ static void nand_print_and_set_info(int idx)
 	setenv("nand_erasesize", buf);
 }
 
+static void nand_print_ID(void)
+{
+	nand_info_t *nand = &nand_info[0];
+	struct nand_chip *chip = nand->priv;
+
+	chip->read_nand_ID(nand);
+}
+
+static int raw_access(nand_info_t *nand, ulong addr, loff_t off, ulong count,
+			int read)
+{
+	int ret = 0;
+
+	while (count--) {
+		/* Raw access */
+		mtd_oob_ops_t ops = {
+			.datbuf = (u8 *)addr,
+			.oobbuf = ((u8 *)addr) + nand->writesize,
+			.len = nand->writesize,
+			.ooblen = nand->oobsize,
+			.mode = MTD_OOB_RAW
+		};
+
+		if (read)
+			ret = nand->read_oob(nand, off, &ops);
+		else
+			ret = nand->write_oob(nand, off, &ops);
+
+		if (ret) {
+			printf("%s: error at offset %llx, ret %d\n",
+				__func__, (long long)off, ret);
+			break;
+		}
+
+		addr += nand->writesize + nand->oobsize;
+		off += nand->writesize;
+	}
+
+	return ret;
+}
+
 int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 {
 	int i, ret = 0;
@@ -429,6 +493,11 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 		return 0;
 	}
 
+	if (strcmp(cmd, "id") == 0 || strcmp(cmd, "ID") == 0) {
+		nand_print_ID();
+		return 0;
+	}
+
 	if (strcmp(cmd, "device") == 0) {
 		if (argc < 3) {
 			putc('\n');
@@ -560,15 +629,75 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 		if (argc < 3)
 			goto usage;
 
-		off = (int)simple_strtoul(argv[2], NULL, 16);
+		off = simple_strtoull(argv[2], NULL, 16);
 		ret = nand_dump(nand, off, !strcmp(&cmd[4], ".oob"), repeat);
 
 		return ret == 0 ? 1 : 0;
 	}
 
+	if (strncmp(cmd, "speed", 5) == 0) {
+
+		unsigned long long start_clock, end_clock;
+		unsigned long duration, nand_speed;
+		u_char *datbuf;
+		nand_erase_options_t opts;
+		uint32_t test_data_size;
+
+		if (argc < 5){
+			datbuf = (u_char *)(0x80000000);
+			off = (ulong)(0x00100000);
+			test_data_size = (ulong)(0x00A00000);
+		} else {
+			datbuf = (u_char *)simple_strtoul(argv[2], NULL, 16);
+			off = (ulong)simple_strtoul(argv[3], NULL, 16);
+			test_data_size = (ulong)simple_strtoul(argv[4], NULL, 16);
+		}
+
+		start_clock = get_ticks();
+		ret = nand_read_skip_bad(nand, off, &test_data_size, datbuf);
+		end_clock = get_ticks();
+		duration = (unsigned long)(end_clock - start_clock);
+		nand_speed = (unsigned long)(test_data_size / (duration * 1000 / get_tbclk()) * 1000 / 1024);
+		if (!ret)
+			printf("\nNand Read speed = %ld Kbyte/s\n\n", nand_speed);
+		else {
+			printf("\nRead data from Nand failed\n");
+			return 1;
+		}
+
+		/* set nand erasing parameters */
+		memset(&opts, 0, sizeof(opts));
+		opts.offset = off;
+		opts.length = test_data_size;
+		opts.jffs2 = 0;
+		opts.quiet = 0;
+		opts.spread = 0;
+
+		/* erase flash */
+		start_clock = get_ticks();
+		ret = nand_erase_opts(nand, &opts);
+		if(ret != 0) {
+			printf("erase nand flash error, returned value: ret = %d\n", ret);
+			return 1;
+		}
+		ret = nand_write_skip_bad(nand, off, &test_data_size, datbuf, 0);
+		end_clock = get_ticks();
+		duration = (unsigned long)(end_clock - start_clock);
+		nand_speed = (unsigned long)(test_data_size / (duration * 1000 / get_tbclk()) * 1000 / 1024);
+		if (!ret)
+			printf("\nNand Write speed = %ld Kbyte/s\n", nand_speed);
+		else {
+			printf("\nWrite data to Nand failed\n");
+			return 1;
+		}
+		return ret == 0 ? 0 : 1;
+	}
+
 	if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) {
 		size_t rwsize;
+		ulong pagecount = 1;
 		int read;
+		int raw;
 
 		if (argc < 4)
 			goto usage;
@@ -577,13 +706,36 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 
 		read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */
 		printf("\nNAND %s: ", read ? "read" : "write");
-		if (arg_off_size(argc - 3, argv + 3, &dev, &off, &size) != 0)
-			return 1;
 
 		nand = &nand_info[dev];
-		rwsize = size;
 
 		s = strchr(cmd, '.');
+
+		if (!strcmp(s, ".raw")) {
+			raw = 1;
+
+			if (arg_off(argv[3], &dev, &off, &size))
+				return 1;
+
+			if (argc > 4 && !str2long(argv[4], &pagecount)) {
+				printf("'%s' is not a number\n", argv[4]);
+				return 1;
+			}
+
+			if (pagecount * nand->writesize > size) {
+				puts("Size exceeds partition or device limit\n");
+				return -1;
+			}
+
+			rwsize = pagecount * (nand->writesize + nand->oobsize);
+		} else {
+			if (arg_off_size(argc - 3, argv + 3, &dev,
+						&off, &size) != 0)
+				return 1;
+
+			rwsize = size;
+		}
+
 		if (!s || !strcmp(s, ".jffs2") ||
 		    !strcmp(s, ".e") || !strcmp(s, ".i")) {
 			if (read)
@@ -609,7 +761,8 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 				return 1;
 			}
 			ret = nand_write_skip_bad(nand, off, &rwsize,
-						(u_char *)addr, WITH_YAFFS_OOB);
+						(u_char *)addr,
+						WITH_YAFFS_OOB); // WITH_INLINE_OOB); ???
 #endif
 		} else if (!strcmp(s, ".oob")) {
 			/* out-of-band data */
@@ -623,22 +776,8 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 				ret = nand->read_oob(nand, off, &ops);
 			else
 				ret = nand->write_oob(nand, off, &ops);
-		} else if (!strcmp(s, ".raw")) {
-			/* Raw access */
-			mtd_oob_ops_t ops = {
-				.datbuf = (u8 *)addr,
-				.oobbuf = ((u8 *)addr) + nand->writesize,
-				.len = nand->writesize,
-				.ooblen = nand->oobsize,
-				.mode = MTD_OOB_RAW
-			};
-
-			rwsize = nand->writesize + nand->oobsize;
-
-			if (read)
-				ret = nand->read_oob(nand, off, &ops);
-			else
-				ret = nand->write_oob(nand, off, &ops);
+		} else if (raw) {
+			ret = raw_access(nand, addr, off, pagecount, read);
 		} else {
 			printf("Unknown nand command suffix '%s'.\n", s);
 			return 1;
@@ -726,15 +865,16 @@ usage:
 U_BOOT_CMD(
 	nand, CONFIG_SYS_MAXARGS, 1, do_nand,
 	"NAND sub-system",
+	"id or ID - print nand ID \n"
 	"info - show available NAND devices\n"
 	"nand device [dev] - show or set current device\n"
 	"nand read - addr off|partition size\n"
 	"nand write - addr off|partition size\n"
 	"    read/write 'size' bytes starting at offset 'off'\n"
 	"    to/from memory address 'addr', skipping bad blocks.\n"
-	"nand read.raw - addr off|partition\n"
-	"nand write.raw - addr off|partition\n"
-	"    Use read.raw/write.raw to avoid ECC and access the page as-is.\n"
+	"nand read.raw - addr off|partition [count]\n"
+	"nand write.raw - addr off|partition [count]\n"
+	"    Use read.raw/write.raw to avoid ECC and access the flash as-is.\n"
 #ifdef CONFIG_CMD_NAND_TRIMFFS
 	"nand write.trimffs - addr off|partition size\n"
 	"    write 'size' bytes starting at offset 'off' from memory address\n"
@@ -754,6 +894,7 @@ U_BOOT_CMD(
 	"nand erase.chip [clean] - erase entire chip'\n"
 	"nand bad - show bad blocks\n"
 	"nand dump[.oob] off - dump page\n"
+	"nand speed [-addr -off -test data length]- show read speed and write speed of NAND\n"
 	"nand scrub [-y] off size | scrub.part partition | scrub.chip\n"
 	"    really clean NAND erasing bad blocks (UNSAFE)\n"
 	"nand markbad off [...] - mark bad block(s) at offset (UNSAFE)\n"
@@ -936,3 +1077,202 @@ U_BOOT_CMD(nboot, 4, 1, do_nandboot,
 	"boot from NAND device",
 	"[partition] | [[[loadAddr] dev] offset]"
 );
+
+static  char test_buf[4096 + 224];
+static  char temp_buf[4096 + 224];
+
+int erase_block(nand_info_t *nand, loff_t off)
+{
+	int ret;
+	nand_erase_options_t opts;
+	struct nand_chip *chip = nand->priv;
+
+	if (chip->phys_erase_shift == 0) {
+		if(mtd_mod_by_eb(off, nand) != 0){
+			printf("not aligned erase size\n");
+			return 1;
+		}
+	} else {
+		if ((off & (nand->erasesize - 1)) != 0 ) {
+			printf("not aligned erase size\n");
+			return 1;
+		}
+	}
+
+	memset(&opts, 0, sizeof(opts));
+	opts.offset = off;
+	opts.length = nand->erasesize;
+	opts.jffs2  = 0;
+	opts.quiet  = 0;
+	opts.spread = 0;
+
+	ret = nand_erase_opts(nand, &opts);
+	printf("%s\n", ret ? "ERROR" : "OK");
+
+	return ret == 0 ? 0 : 1;
+}
+
+static void dump_flash_buf(nand_info_t *nand, char *new)
+{
+	int i;
+
+	printf("flash data:\n");
+	for (i = 0; i < nand->writesize; i+=8)
+		printf("%04x: %2x %2x %2x %2x %2x %2x %2x %2x\n",i, new[i], new[i+1], new[i+2],
+			new[i+3], new[i+4], new[i+5], new[i+6], new[i+7]);
+
+	printf("flash oob:\n");
+	for (; i < (nand->writesize + nand->oobsize); i+=8)
+		printf("%04x: %2x %2x %2x %2x %2x %2x %2x %2x\n",i, new[i], new[i+1], new[i+2],
+			new[i+3], new[i+4], new[i+5], new[i+6], new[i+7]);
+}
+
+/*
+ * use lcd backlight as trigger of digital analyzer
+ */
+#include <asm/arch/reg_nand.h>
+#include <asm/io.h>
+static void trigger_gpio(int high)
+{
+#define RDA_GPIO_DIR (RDA_GPIO_A_BASE + 0x04)
+#define RDA_GPIO_VAL (RDA_GPIO_A_BASE + 0x0c)
+#define RDA_GPIO_SET (RDA_GPIO_A_BASE + 0x10)
+#define RDA_GPIO_CLR (RDA_GPIO_A_BASE + 0x14)
+
+	__raw_writel(0xffffffff, RDA_GPIO_DIR);
+	if (high) {
+		__raw_writel(0x0f, RDA_GPIO_SET);
+	} else {
+		__raw_writel(0x0f, RDA_GPIO_CLR);
+	}
+}
+int do_nandstress(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
+{
+	int i;
+	int dev = nand_curr_device;
+	int ret;
+	nand_info_t *nand;
+	unsigned long long count_h, count_l;
+	loff_t off = 0;
+	char * s;
+	int need_erase = 1;
+
+	if (argc < 2)
+		goto usage;
+
+	off = simple_strtoul(argv[1], NULL, 16);
+	printf("nand stress test offset %llx\n", off);
+	s = argv[2];
+
+	/*
+	 DANGROUS!!!!!!!
+	 if you dont erase the block and write/read
+	 the page, the page maybe damaged for ever.
+	 this test used as test the hardware ecc functions:
+	 write the page repeatedly until the page error, and test if
+	 the handware ecc can detect and correct them;
+	*/
+	if (!strcmp(s, "noerase")) {
+		const char *noerase_warning =
+			"!!!!!DANGROUS test!!!!!!\n"
+			"This may damage the flash page for ever ....y/N\n";
+		puts(noerase_warning);
+		if (getc() == 'y') {
+			puts("y");
+			if (getc() == '\r') {
+				printf("\nwill don't erase the block anyway...\n");
+				need_erase = 0;
+			}
+		}
+	}
+
+	printf("nand stress test erase/write/read ....\n");
+
+	count_h = 0;
+	count_l = 0;
+	nand = &nand_info[dev];
+
+	for (i = 0; i < (nand->writesize + nand->oobsize); i++) {
+		test_buf[i] = i+255;
+	}
+
+	trigger_gpio(1);
+	while (1) {
+		int error_count;
+		/* Raw access */
+		mtd_oob_ops_t ops_w= {
+			.datbuf = (u8 *)test_buf,
+			.oobbuf = ((u8 *)test_buf) + nand->writesize,
+			.len = nand->writesize,
+			.ooblen = nand->oobsize,
+			.mode = MTD_OOB_RAW
+		};
+		mtd_oob_ops_t ops_r= {
+			.datbuf = (u8 *)temp_buf,
+			.oobbuf = ((u8 *)temp_buf) + nand->writesize,
+			.len = nand->writesize,
+			.ooblen = nand->oobsize,
+			.mode = MTD_OOB_RAW
+		};
+
+		if (need_erase) {
+			if (erase_block(nand, off)){
+				trigger_gpio(0);
+				printf("oops, erase error\n");
+				goto error;
+			}
+		}
+		ret = nand->write_oob(nand, off, &ops_w);
+		if (ret) {
+			trigger_gpio(0);
+			printf("%s: error at offset %llx, ret %d\n",
+				__func__, (long long)off, ret);
+			goto error;
+		}
+		ret = nand->read_oob(nand, off, &ops_r);
+		if (ret) {
+			printf("%s: error at offset %llx, ret %d\n",
+				__func__, (long long)off, ret);
+			goto error;
+		}
+
+		error_count = 0;
+		//for (i = 0; i < (nand->writesize + nand->oobsize); i++) {
+		for (i = 0; i < (nand->writesize); i++) {
+			if(test_buf[i] != temp_buf[i]) {
+				trigger_gpio(0);
+				printf("oops, read/write is error at %x, source %02x, flash %02x\n",
+					 i, test_buf[i], temp_buf[i]);
+				printf("nand interrupt stauts %x\n",__raw_readl(NANDFC_REG_INT_STAT));
+				printf("nand busy flag %x\n",__raw_readl(NANDFC_REG_BUSY_FLAG));
+				error_count ++;
+			}
+		}
+
+		if (error_count) {
+			printf("oops, error num %d, \n",error_count);
+			dump_flash_buf(nand, temp_buf);
+			printf("read nand fifo \n");
+			goto error;
+		}
+		count_l++;
+		if (count_l == 0) {
+			count_h++;
+		}
+		printf("###################NAND testing... the loop is:high %lld, low %lld\n"
+			, count_h, count_l);
+	};
+
+	return 1;
+usage:
+	return CMD_RET_USAGE;
+error:
+	printf("NAND stress test end, the loop is:high %lld, low %lld\n", count_h, count_l);
+	return 1;
+}
+
+U_BOOT_CMD(nandstress, 3, 1, do_nandstress,
+	"nand stress test for one page read/write: nandstress off",
+	"[ off ]\n"
+	"    - test nand from page offset 'off'"
+);
diff --git a/common/cmd_net.c b/common/cmd_net.c
index 65f32bceef..a9ade8b927 100644
--- a/common/cmd_net.c
+++ b/common/cmd_net.c
@@ -153,12 +153,16 @@ static void netboot_update_env (void)
 		ip_to_string (NetOurIP, tmp);
 		setenv ("ipaddr", tmp);
 	}
-
+#if !defined(CONFIG_BOOTP_SERVERIP)
+	/*
+	 * Only attempt to change serverip if net/bootp.c:BootpCopyNetParams()
+	 * could have set it
+	 */
 	if (NetServerIP) {
 		ip_to_string (NetServerIP, tmp);
 		setenv ("serverip", tmp);
 	}
-
+#endif
 	if (NetOurDNSIP) {
 		ip_to_string (NetOurDNSIP, tmp);
 		setenv ("dnsip", tmp);
@@ -424,3 +428,34 @@ U_BOOT_CMD(
 );
 
 #endif	/* CONFIG_CMD_DNS */
+
+#if defined(CONFIG_CMD_LINK_LOCAL)
+static int do_link_local(cmd_tbl_t *cmdtp, int flag, int argc,
+			char * const argv[])
+{
+	char tmp[22];
+
+	if (NetLoop(LINKLOCAL) < 0)
+		return 1;
+
+	NetOurGatewayIP = 0;
+	ip_to_string(NetOurGatewayIP, tmp);
+	setenv("gatewayip", tmp);
+
+	ip_to_string(NetOurSubnetMask, tmp);
+	setenv("netmask", tmp);
+
+	ip_to_string(NetOurIP, tmp);
+	setenv("ipaddr", tmp);
+	setenv("llipaddr", tmp); /* store this for next time */
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	linklocal,	1,	1,	do_link_local,
+	"acquire a network IP address using the link-local protocol",
+	""
+);
+
+#endif  /* CONFIG_CMD_LINK_LOCAL */
diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
index b1494dcb0c..271200266c 100644
--- a/common/cmd_nvedit.c
+++ b/common/cmd_nvedit.c
@@ -66,9 +66,10 @@ DECLARE_GLOBAL_DATA_PTR;
 	!defined(CONFIG_ENV_IS_IN_NVRAM)	&& \
 	!defined(CONFIG_ENV_IS_IN_ONENAND)	&& \
 	!defined(CONFIG_ENV_IS_IN_SPI_FLASH)	&& \
+	!defined(CONFIG_ENV_IS_IN_REMOTE)	&& \
 	!defined(CONFIG_ENV_IS_NOWHERE)
 # error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|\
-SPI_FLASH|MG_DISK|NVRAM|MMC|FAT} or CONFIG_ENV_IS_NOWHERE
+SPI_FLASH|MG_DISK|NVRAM|MMC|FAT|REMOTE} or CONFIG_ENV_IS_NOWHERE
 #endif
 
 #define XMK_STR(x)	#x
@@ -203,7 +204,6 @@ static int do_env_grep(cmd_tbl_t *cmdtp, int flag,
  */
 int _do_env_set(int flag, int argc, char * const argv[])
 {
-	bd_t  *bd = gd->bd;
 	int   i, len;
 	int   console = -1;
 	char  *name, *value, *s;
@@ -342,21 +342,7 @@ int _do_env_set(int flag, int argc, char * const argv[])
 	 * Some variables should be updated when the corresponding
 	 * entry in the environment is changed
 	 */
-	if (strcmp(name, "ipaddr") == 0) {
-		char *s = argv[2];	/* always use only one arg */
-		char *e;
-		unsigned long addr;
-		bd->bi_ip_addr = 0;
-		for (addr = 0, i = 0; i < 4; ++i) {
-			ulong val = s ? simple_strtoul(s, &e, 10) : 0;
-			addr <<= 8;
-			addr  |= val & 0xFF;
-			if (s)
-				s = *e ? e + 1 : e;
-		}
-		bd->bi_ip_addr = htonl(addr);
-		return 0;
-	} else if (strcmp(argv[1], "loadaddr") == 0) {
+	if (strcmp(argv[1], "loadaddr") == 0) {
 		load_addr = simple_strtoul(argv[2], NULL, 16);
 		return 0;
 	}
diff --git a/common/cmd_onenand.c b/common/cmd_onenand.c
index 0f2e208717..a0d25e5521 100644
--- a/common/cmd_onenand.c
+++ b/common/cmd_onenand.c
@@ -13,7 +13,7 @@
 #include <command.h>
 #include <malloc.h>
 
-#include <linux/mtd/compat.h>
+#include <linux/compat.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/onenand.h>
 
diff --git a/common/cmd_sata.c b/common/cmd_sata.c
index 7b1703fe41..3f98235a38 100644
--- a/common/cmd_sata.c
+++ b/common/cmd_sata.c
@@ -48,9 +48,12 @@ int __sata_initialize(void)
 		sata_dev_desc[i].block_write = sata_write;
 
 		rc = init_sata(i);
-		rc = scan_sata(i);
-		if ((sata_dev_desc[i].lba > 0) && (sata_dev_desc[i].blksz > 0))
-			init_part(&sata_dev_desc[i]);
+		if (!rc) {
+			rc = scan_sata(i);
+			if (!rc && (sata_dev_desc[i].lba > 0) &&
+				(sata_dev_desc[i].blksz > 0))
+				init_part(&sata_dev_desc[i]);
+		}
 	}
 	sata_curr_device = 0;
 	return rc;
diff --git a/common/cmd_test.c b/common/cmd_test.c
index fcb5ef2f71..cd9a1a2836 100644
--- a/common/cmd_test.c
+++ b/common/cmd_test.c
@@ -171,3 +171,220 @@ U_BOOT_CMD(
 	"do nothing, successfully",
 	NULL
 );
+
+#ifdef CONFIG_VPU_TEST
+#include <asm/arch/hw_test.h>
+int do_vpu_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int times = 1;
+	if(argc > 1) {
+		times = simple_strtoul(argv[1], NULL, 10);
+	}
+	vpu_sta_test(times);
+	return 0;
+}
+U_BOOT_CMD(
+	vpu_test,	CONFIG_SYS_MAXARGS,	1,	do_vpu_test,
+	"vpu test",
+	NULL
+);
+
+#ifdef CONFIG_VPU_MD5_TEST
+int do_vpu_md5_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int times = 1;
+	if(argc > 1) {
+		times = simple_strtoul(argv[1], NULL, 10);
+	}
+	vpu_md5_test(times);
+	return 0;
+}
+U_BOOT_CMD(
+	vpu_md5_test,	CONFIG_SYS_MAXARGS,	1,	do_vpu_md5_test,
+	"vpu md5 test",
+	NULL
+);
+#endif //CONFIG_VPU_MD5_TEST
+#endif //CONFIG_VPU_TEST
+
+#ifdef CONFIG_CPU_TEST
+#include <asm/arch/hw_test.h>
+int do_cpu_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int times = 1;
+	if(argc > 1) {
+		times = simple_strtoul(argv[1], NULL, 10);
+	}
+	cpu_pll_test(times);
+	return 0;
+}
+U_BOOT_CMD(
+	cpu_test,	CONFIG_SYS_MAXARGS,	1,	do_cpu_test,
+	"cpu test",
+	NULL
+);
+#endif //CONFIG_VPU_TEST
+
+#ifdef CONFIG_DDR_TEST
+#include <asm/arch/hw_test.h>
+int do_ddr_mem_copy_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int times = 1;
+	unsigned int src_addr = 0x80000000,des_addr = 0x83000000,n = 0x10;
+
+	if(argc > 1) {
+		times = simple_strtoul(argv[1], NULL, 10);
+	}
+	if(argc > 2) {
+		src_addr = simple_strtoul(argv[2],NULL,16);
+	}
+	if(argc > 3) {
+		des_addr = simple_strtoul(argv[3],NULL,16);
+	}
+	if(argc > 4) {
+		n = simple_strtoul(argv[4],NULL,16);
+	}
+	ddr_mem_copy_test(times,src_addr,des_addr,n);
+	return 0;
+}
+
+U_BOOT_CMD(
+	ddr_mem_cp,	5,	1,	do_ddr_mem_copy_test,
+	"ddr memory copy test",
+	NULL
+);
+#endif //CONFIG_DDR_TEST
+
+#ifdef CONFIG_TIMER_TEST
+#include <asm/arch/hw_test.h>
+int do_timer_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int times = 1;
+	unsigned int timer_id = 0;
+
+	if(argc > 1) {
+		timer_id = simple_strtoul(argv[1], NULL, 10);
+	}
+	if(argc > 2) {
+		times = simple_strtoul(argv[2],NULL,16);
+	}
+	tim_test(timer_id,times);
+	return 0;
+}
+
+U_BOOT_CMD(
+	timer_test,	5,	1,	do_timer_test,
+	"timer_test timer_id(0~2) times",
+	NULL
+);
+#endif /* CONFIG_TIMER_TEST */
+
+#ifdef CONFIG_UART_TEST
+#include <asm/arch/hw_test.h>
+int do_uart_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int times = 1;
+	unsigned int uart_id = 2;// uart3 as default test port
+
+	if(argc > 1) {
+		uart_id = simple_strtoul(argv[1], NULL, 10);
+	}
+	if(argc > 2) {
+		times = simple_strtoul(argv[2],NULL,16);
+	}
+	uart_test(uart_id,times);
+	return 0;
+}
+
+U_BOOT_CMD(
+	uart_test,	5,	1,	do_uart_test,
+	"uart_test uart_id(0~2) times",
+	NULL
+);
+#endif /* CONFIG_UART_TEST */
+
+#ifdef CONFIG_GIC_TEST
+#include <asm/arch/hw_test.h>
+int do_gic_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int times = 1;
+
+	if(argc > 1) {
+		times = simple_strtoul(argv[1], NULL, 10);
+	}
+	gic_test(times);
+	return 0;
+}
+
+U_BOOT_CMD(
+	gic_test,	5,	1,	do_gic_test,
+	"gic_test times",
+	NULL
+);
+#endif /* CONFIG_GIC_TEST */
+
+#ifdef CONFIG_CACHE_TEST
+#include <asm/arch/hw_test.h>
+int do_cache_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int times = 1;
+
+	if(argc > 1) {
+		times = simple_strtoul(argv[1], NULL, 10);
+	}
+	cpu_cache_test(times);
+	return 0;
+}
+
+U_BOOT_CMD(
+	cache_test,	5,	1,	do_cache_test,
+	"cpu L1/L2 D-cache I-cache test",
+	NULL
+);
+#endif /* CONFIG_CACHE_TEST */
+
+#ifdef CONFIG_MIPI_LOOP_TEST
+#include<asm/arch/hw_test.h>
+int do_mipi_loop_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int times = 1;
+
+	if (argc > 1)
+		times = simple_strtoull(argv[1], NULL, 10);
+	if (times < 1) {
+		printf("Invalid parameter\n");
+		return 1;
+	}
+	test_dsi_csi_loop(times);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	mipi_loop,	5,	5,	do_mipi_loop_test,
+	"mipi loop test",
+	NULL
+);
+#endif /* CONFIG_MIPI_LOOP_TEST */
+
+#ifdef CONFIG_I2C_TEST
+#include<asm/arch/hw_test.h>
+int do_i2c_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int times = 1;
+	int id = 2; /* I2C id number:0,1,2,I2C 2 is default device */
+
+	if(argc > 1)
+		times = simple_strtoull(argv[1], NULL, 10);
+	if(argc > 2)
+		id = simple_strtoul(argv[2],NULL,10);
+	test_i2c(id,times);
+	return 0;
+}
+
+U_BOOT_CMD(
+	i2c_test,	5,	5,	do_i2c_test,
+	"i2c test",
+	NULL
+);
+#endif /* CONFIG_I2C_TET */
diff --git a/common/cmd_ubi.c b/common/cmd_ubi.c
index 35b1d31f9c..aff6d69de5 100644
--- a/common/cmd_ubi.c
+++ b/common/cmd_ubi.c
@@ -149,7 +149,10 @@ static int verify_mkvol_req(const struct ubi_device *ubi,
 	if (req->alignment > ubi->leb_size)
 		goto bad;
 
-	n = req->alignment % ubi->min_io_size;
+	if (is_power_of_2(ubi->min_io_size))
+		n = req->alignment & (ubi->min_io_size -1);
+	else
+		n = req->alignment % ubi->min_io_size;
 	if (req->alignment != 1 && n)
 		goto bad;
 
@@ -164,7 +167,7 @@ bad:
 	return err;
 }
 
-static int ubi_create_vol(char *volume, int size, int dynamic)
+static int ubi_create_vol(const char *volume, int64_t size, int dynamic)
 {
 	struct ubi_mkvol_req req;
 	int err;
@@ -188,13 +191,13 @@ static int ubi_create_vol(char *volume, int size, int dynamic)
 		printf("verify_mkvol_req failed %d\n", err);
 		return err;
 	}
-	printf("Creating %s volume %s of size %d\n",
+	printf("Creating %s volume %s of size 0x%llx\n",
 		dynamic ? "dynamic" : "static", volume, size);
 	/* Call real ubi create volume */
 	return ubi_create_volume(ubi, &req);
 }
 
-static struct ubi_volume *ubi_find_volume(char *volume)
+static struct ubi_volume *ubi_find_volume(const char *volume)
 {
 	struct ubi_volume *vol = NULL;
 	int i;
@@ -209,7 +212,7 @@ static struct ubi_volume *ubi_find_volume(char *volume)
 	return NULL;
 }
 
-static int ubi_remove_vol(char *volume)
+static int ubi_remove_vol(const char *volume)
 {
 	int err, reserved_pebs, i;
 	struct ubi_volume *vol;
@@ -263,7 +266,7 @@ out_err:
 	return err;
 }
 
-static int ubi_volume_write(char *volume, void *buf, size_t size)
+static int ubi_volume_write(const char *volume, void *buf, size_t size)
 {
 	int err = 1;
 	int rsvd_bytes = 0;
@@ -313,13 +316,12 @@ static int ubi_volume_write(char *volume, void *buf, size_t size)
 	return 0;
 }
 
-static int ubi_volume_read(char *volume, char *buf, size_t size)
+static int ubi_volume_read(const char *volume, loff_t offp, char *buf, size_t size)
 {
 	int err, lnum, off, len, tbuf_size;
 	void *tbuf;
 	unsigned long long tmp;
 	struct ubi_volume *vol;
-	loff_t offp = 0;
 
 	vol = ubi_find_volume(volume);
 	if (vol == NULL)
@@ -349,8 +351,12 @@ static int ubi_volume_read(char *volume, char *buf, size_t size)
 		size = vol->used_bytes - offp;
 
 	tbuf_size = vol->usable_leb_size;
-	if (size < tbuf_size)
-		tbuf_size = ALIGN(size, ubi->min_io_size);
+	if (size < tbuf_size) {
+		if (is_power_of_2(ubi->min_io_size))
+			tbuf_size = ALIGN(size, ubi->min_io_size);
+		else
+			tbuf_size = roundup(size, ubi->min_io_size);
+	}
 	tbuf = malloc(tbuf_size);
 	if (!tbuf) {
 		printf("NO MEM\n");
@@ -390,7 +396,7 @@ static int ubi_volume_read(char *volume, char *buf, size_t size)
 	return err;
 }
 
-static int ubi_dev_scan(struct mtd_info *info, char *ubidev,
+static int ubi_dev_scan(struct mtd_info *info, const char *ubidev,
 		const char *vid_header_offset)
 {
 	struct mtd_device *dev;
@@ -431,6 +437,272 @@ static int ubi_dev_scan(struct mtd_info *info, char *ubidev,
 	return 0;
 }
 
+#ifdef MTDPARTS_UBI_DEF
+int ubi_part_scan(const char *part_name)
+{
+	struct mtd_info *info;
+	struct mtd_device *dev;
+	struct part_info *part;
+	nand_erase_options_t opts;
+	char mtd_dev[20];
+	u8 pnum;
+	int ret = 0;
+
+	if(ubi_initialized){
+		ubi = ubi_devices[0];
+		return 0;
+	}
+	/*
+	 * Search the mtd device number where this partition
+	 * is located
+	 */
+	if (find_dev_and_part(part_name, &dev, &pnum, &part)) {
+		printf("Partition %s not found!\n", part_name);
+		return -1;
+	}
+	sprintf(mtd_dev, "%s%d", MTD_DEV_TYPE(dev->id->type), dev->id->num);
+	info = get_mtd_device_nm(mtd_dev);
+	if (IS_ERR(info)) {
+		printf("Partition %s not found on device %s!\n", part_name, mtd_dev);
+		return 1;
+	}
+	printf("found part '%s' offset: 0x%llx length: 0x%llx id: %d\n",
+		part->name, part->offset, part->size, dev->id->num);
+
+	ret = ubi_dev_scan(info, part_name, NULL);
+	/* if fail, erase the part, try again */
+	if(ret) {
+		memset(&opts, 0, sizeof(opts));
+		opts.offset = (loff_t) part->offset;
+		opts.length = (loff_t) part->size;
+		opts.jffs2 = 0;
+		opts.quiet = 0;
+
+		ret = nand_erase_opts(info, &opts);
+		if(ret)
+			return ret;
+		ret = ubi_dev_scan(info, part_name, NULL);
+		if(ret)
+			return ret;
+	}
+
+	ubi = ubi_devices[0];
+	return ret;
+}
+
+struct ubi_vol_info {
+	char name[20];
+	size_t size;
+};
+static int ubi_parse_ubi_str(const char *ubi_default_str,
+		struct ubi_vol_info **ubivol_info, int *ubivol_count)
+{
+	char *def_str = malloc(strlen(ubi_default_str)+1);
+	char *p = def_str;
+	char *q;
+	int i = 0;
+	struct ubi_vol_info *info;
+
+	if(!def_str)
+		return -1;
+	strcpy(def_str, ubi_default_str);
+
+	while(1) {
+		q = strstr(p, "M(");
+		if(!q) {
+			q = strstr(p, "-(");
+			if(!q)
+				break;
+		}
+		i++;
+		p = q + 2;
+	}
+
+	info = (struct ubi_vol_info *)malloc(sizeof(struct ubi_vol_info) * i);
+	*ubivol_info = info;
+	*ubivol_count = i;
+
+	p = def_str;
+	i = 0;
+	while(1) {
+		/* size */
+		q = strstr(p, "M(");
+		if(q) {
+			*q = '\0';
+			info[i].size = simple_strtoul(p, NULL, 10) * 1024 * 1024;
+			p = q + 2;
+		} else {
+			q = strstr(p, "-(");
+			if(q) {
+				info[i].size = 0;
+				p = q + 2;
+			} else {
+				break;
+			}
+		}
+
+		/* name */
+		q = strstr(p, ")");
+		if(q)
+			*q = '\0';
+		strcpy(info[i].name, p);
+		if(!q)
+			break;
+		p = q + 1;
+		if(*p == ',')
+			p++;
+
+		i++;
+	}
+	free(def_str);
+	return 0;
+}
+
+int ubi_check_default_vols(const char *ubi_default_str)
+{
+	int ret = 0;
+	struct ubi_vol_info *info = NULL;
+	int count = 0, i;
+	int checked = 1;
+	struct ubi_volume *vol;
+
+	if(ubi_parse_ubi_str(ubi_default_str, &info, &count))
+		return -1;
+	if(count <= 0 || !info)
+		return -1;
+
+	for(i = 0; i < count; i++) {
+		vol = ubi_find_volume(info[i].name);
+		if(vol == NULL) {
+			checked = 0;
+			break;
+		}
+	}
+
+	/* format */
+	if(!checked) {
+		/* remove all volumes */
+		for(i = 0; i < (ubi->vtbl_slots + 1); i++) {
+			if(!ubi->volumes[i])
+				continue;
+			ret = ubi_remove_vol(ubi->volumes[i]->name);
+			if(ret) break;
+		}
+		/* create new volumes */
+		for(i = 0; i < count; i++) {
+			/* Use maximum available size */
+			if (!info[i].size) {
+				info[i].size = ubi->avail_pebs * ubi->leb_size;
+				printf("No size specified -> Using max size (%u)\n", info[i].size);
+			}
+			ret = ubi_create_vol(info[i].name, info[i].size, 1);
+			if(ret) break;
+		}
+	}
+
+	free(info);
+	return ret;
+}
+
+int ubi_erase_vol(const char *vol_name)
+{
+	struct ubi_volume *vol;
+
+	vol = ubi_find_volume(vol_name);
+	if(vol == NULL) { /* not need to erase */
+		return 0;
+	}
+	return ubi_volume_write(vol_name, "", 0);
+}
+
+int ubi_read_vol(const char *vol_name, loff_t offp, void *buf, size_t size)
+{
+	return ubi_volume_read(vol_name, offp, buf, size);
+}
+
+int ubi_prepare_write_vol(const char *volume, size_t size)
+{
+	int err = 1;
+	int rsvd_bytes = 0;
+	struct ubi_volume *vol;
+
+	vol = ubi_find_volume(volume);
+	if (vol == NULL)
+		return -ENODEV;
+
+	rsvd_bytes = vol->reserved_pebs * (ubi->leb_size - vol->data_pad);
+	if (size < 0 || size > rsvd_bytes) {
+		printf("size > volume size! Aborting!\n");
+		return -EINVAL;
+	}
+
+	err = ubi_start_update(ubi, vol, size);
+	if (err < 0) {
+		printf("Cannot start volume update\n");
+		return err;
+	}
+
+	printf("prepare to write %d bytes to volume %s\n", size, volume);
+	return 0;
+}
+
+int ubi_do_write_vol(const char *volume, void *buf, size_t size)
+{
+	int err = 1;
+	struct ubi_volume *vol;
+
+	vol = ubi_find_volume(volume);
+	if (vol == NULL)
+		return -ENODEV;
+
+	err = ubi_more_update_data(ubi, vol, buf, size);
+	if (err < 0) {
+		printf("Couldnt or partially wrote data\n");
+		return err;
+	}
+
+	printf("%d bytes written to volume %s\n", size, volume);
+	return 0;
+}
+
+int ubi_finish_write_vol(const char *volume)
+{
+	int err = 1;
+	struct ubi_volume *vol;
+
+	vol = ubi_find_volume(volume);
+	if (vol == NULL)
+		return -ENODEV;
+
+	err = ubi_check_volume(ubi, vol->vol_id);
+	if (err < 0)
+		return err;
+
+	if (err) {
+		ubi_warn("volume %d on UBI device %d is corrupted",
+					vol->vol_id, ubi->ubi_num);
+		vol->corrupted = 1;
+	}
+
+	vol->checked = 1;
+	ubi_gluebi_updated(vol);
+
+	printf("finish to write volume %s\n", volume);
+	return 0;
+}
+
+int ubi_update_vol(const char *vol_name, void *buf, size_t size)
+{
+	return ubi_volume_write(vol_name, buf, size);
+}
+
+size_t ubi_sizeof_vol(const char *vol_name)
+{
+	struct ubi_volume *vol = ubi_find_volume(vol_name);
+	return vol->used_bytes;
+}
+#endif /* MTDPARTS_UBI_DEF */
+
 static int do_ubi(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 {
 	size_t size = 0;
@@ -598,7 +870,7 @@ static int do_ubi(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 		}
 
 		if (argc == 3)
-			return ubi_volume_read(argv[3], (char *)addr, size);
+			return ubi_volume_read(argv[3], 0, (char *)addr, size);
 	}
 
 	printf("Please see usage\n");
diff --git a/common/cmd_usb.c b/common/cmd_usb.c
index 9eba2713ea..a8e3ae5b67 100644
--- a/common/cmd_usb.c
+++ b/common/cmd_usb.c
@@ -150,7 +150,8 @@ void usb_display_class_sub(unsigned char dclass, unsigned char subclass,
 
 void usb_display_string(struct usb_device *dev, int index)
 {
-	char buffer[256];
+	ALLOC_CACHE_ALIGN_BUFFER(char, buffer, 256);
+
 	if (index != 0) {
 		if (usb_string(dev, index, &buffer[0], 256) > 0)
 			printf("String: \"%s\"", buffer);
diff --git a/common/cmd_version.c b/common/cmd_version.c
index e4b2ac1efc..bdb476df94 100644
--- a/common/cmd_version.c
+++ b/common/cmd_version.c
@@ -25,6 +25,8 @@
 #include <command.h>
 #include <version.h>
 #include <linux/compiler.h>
+#include <timestamp.h>
+#include "generated/version_autogenerated.h"
 
 const char __weak version_string[] = U_BOOT_VERSION_STRING;
 
diff --git a/common/cmd_yaffs2.c b/common/cmd_yaffs2.c
index 0e22d90e7a..d43a9d444c 100644
--- a/common/cmd_yaffs2.c
+++ b/common/cmd_yaffs2.c
@@ -1,18 +1,37 @@
+/* Yaffs commands.
+ * Modified by Charles Manning by adding ydevconfig command.
+ *
+ * Use ydevconfig to configure a mountpoint before use.
+ * For example:
+ *  # Configure mountpt xxx using nand device 0 using blocks 100-500
+ *  ydevconfig xxx 0 100 500
+ *  # Mount it
+ *  ymount xxx
+ *  # yls, yrdm etc
+ *  yls -l xxx
+ *  yrdm xxx/boot-image 82000000
+ *  ...
+ */
+
 #include <common.h>
 
 #include <config.h>
 #include <command.h>
 
-#ifdef  YAFFS2_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
+#ifdef YAFFS2_DEBUG
+#define PRINTF(fmt, args...) printf(fmt, ##args)
 #else
-#define PRINTF(fmt,args...)
+#define PRINTF(fmt, args...) do { } while (0)
 #endif
 
+extern void cmd_yaffs_dev_ls(void);
+extern void cmd_yaffs_tracemask(unsigned set, unsigned mask);
+extern void cmd_yaffs_devconfig(char *mp, int flash_dev,
+				int start_block, int end_block);
 extern void cmd_yaffs_mount(char *mp);
 extern void cmd_yaffs_umount(char *mp);
 extern void cmd_yaffs_read_file(char *fn);
-extern void cmd_yaffs_write_file(char *fn,char bval,int sizeOfFile);
+extern void cmd_yaffs_write_file(char *fn, char bval, int sizeOfFile);
 extern void cmd_yaffs_ls(const char *mountpt, int longlist);
 extern void cmd_yaffs_mwrite_file(char *fn, char *addr, int size);
 extern void cmd_yaffs_mread_file(char *fn, char *addr);
@@ -21,193 +40,287 @@ extern void cmd_yaffs_rmdir(const char *dir);
 extern void cmd_yaffs_rm(const char *path);
 extern void cmd_yaffs_mv(const char *oldPath, const char *newPath);
 
-extern int yaffs_DumpDevStruct(const char *path);
+extern int yaffs_dump_dev(const char *path);
+
+/* ytrace - show/set yaffs trace mask */
+int do_ytrace(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	if (argc > 1)
+		cmd_yaffs_tracemask(1, simple_strtol(argv[1], NULL, 16));
+	else
+		cmd_yaffs_tracemask(0, 0);
 
+	return 0;
+}
 
-int do_ymount (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+/* ydevls - lists yaffs mount points. */
+int do_ydevls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
-    char *mtpoint = argv[1];
-    cmd_yaffs_mount(mtpoint);
+	cmd_yaffs_dev_ls();
 
-    return(0);
+	return 0;
 }
 
-int do_yumount (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+/* ydevconfig mount_pt mtd_dev_num start_block end_block */
+int do_ydevconfig(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
-    char *mtpoint = argv[1];
-    cmd_yaffs_umount(mtpoint);
+	char *mtpoint;
+	int mtd_dev;
+	int start_block;
+	int end_block;
+
+	if (argc != 5) {
+		printf
+		    ("Bad arguments: ydevconfig mount_pt mtd_dev start_block end_block\n");
+		return -1;
+	}
+
+	mtpoint = argv[1];
+	mtd_dev = simple_strtol(argv[2], NULL, 16);
+	start_block = simple_strtol(argv[3], NULL, 16);
+	end_block = simple_strtol(argv[4], NULL, 16);
 
-    return(0);
+	cmd_yaffs_devconfig(mtpoint, mtd_dev, start_block, end_block);
+
+	return 0;
 }
 
-int do_yls (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_ymount(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
-    char *dirname = argv[argc-1];
+	char *mtpoint;
+
+	if (argc != 2) {
+		printf("Bad arguments: ymount mount_pt\n");
+		return -1;
+	}
+
+	mtpoint = argv[1];
+	printf("Mounting yaffs2 mount point %s\n", mtpoint);
 
-    cmd_yaffs_ls(dirname, (argc>2)?1:0);
+	cmd_yaffs_mount(mtpoint);
 
-    return(0);
+	return 0;
 }
 
-int do_yrd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_yumount(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
-    char *filename = argv[1];
-    printf ("Reading file %s ", filename);
+	char *mtpoint;
 
-    cmd_yaffs_read_file(filename);
+	if (argc != 2) {
+		printf("Bad arguments: yumount mount_pt\n");
+		return -1;
+	}
 
-    printf ("done\n");
-    return(0);
+	mtpoint = argv[1];
+	printf("Unmounting yaffs2 mount point %s\n", mtpoint);
+	cmd_yaffs_umount(mtpoint);
+
+	return 0;
 }
 
-int do_ywr (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_yls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
-    char *filename = argv[1];
-    ulong value = simple_strtoul(argv[2], NULL, 16);
-    ulong numValues = simple_strtoul(argv[3], NULL, 16);
+	char *dirname;
+
+	if (argc < 2 || argc > 3 || (argc == 3 && strcmp(argv[1], "-l"))) {
+		printf("Bad arguments: yls [-l] dir\n");
+		return -1;
+	}
 
-    printf ("Writing value (%lx) %lx times to %s... ", value, numValues, filename);
+	dirname = argv[argc - 1];
 
-    cmd_yaffs_write_file(filename,value,numValues);
+	cmd_yaffs_ls(dirname, (argc > 2) ? 1 : 0);
 
-    printf ("done\n");
-    return(0);
+	return 0;
 }
 
-int do_yrdm (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_yrd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
-    char *filename = argv[1];
-    ulong addr = simple_strtoul(argv[2], NULL, 16);
+	char *filename;
+
+	if (argc != 2) {
+		printf("Bad arguments: yrd file_name\n");
+		return -1;
+	}
 
-    cmd_yaffs_mread_file(filename, (char *)addr);
+	filename = argv[1];
 
-    return(0);
+	printf("Reading file %s ", filename);
+
+	cmd_yaffs_read_file(filename);
+
+	printf("done\n");
+	return 0;
 }
 
-int do_ywrm (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_ywr(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
-    char *filename = argv[1];
-    ulong addr = simple_strtoul(argv[2], NULL, 16);
-    ulong size = simple_strtoul(argv[3], NULL, 16);
+	char *filename;
+	ulong value;
+	ulong numValues;
+
+	if (argc != 4) {
+		printf("Bad arguments: ywr file_name value n_values\n");
+		return -1;
+	}
 
-    cmd_yaffs_mwrite_file(filename, (char *)addr, size);
+	filename = argv[1];
+	value = simple_strtoul(argv[2], NULL, 16);
+	numValues = simple_strtoul(argv[3], NULL, 16);
 
-    return(0);
+	printf("Writing value (%lx) %lx times to %s... ", value, numValues,
+	       filename);
+
+	cmd_yaffs_write_file(filename, value, numValues);
+
+	printf("done\n");
+	return 0;
 }
 
-int do_ymkdir (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_yrdm(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
-    char *dirname = argv[1];
+	char *filename;
+	ulong addr;
+
+	if (argc != 3) {
+		printf("Bad arguments: yrdm file_name addr\n");
+		return -1;
+	}
 
-    cmd_yaffs_mkdir(dirname);
+	filename = argv[1];
+	addr = simple_strtoul(argv[2], NULL, 16);
 
-    return(0);
+	cmd_yaffs_mread_file(filename, (char *)addr);
+
+	return 0;
 }
 
-int do_yrmdir (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_ywrm(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
-    char *dirname = argv[1];
+	char *filename;
+	ulong addr;
+	ulong size;
+
+	if (argc != 4) {
+		printf("Bad arguments: ywrm file_name addr size\n");
+		return -1;
+	}
+
+	filename = argv[1];
+	addr = simple_strtoul(argv[2], NULL, 16);
+	size = simple_strtoul(argv[3], NULL, 16);
 
-    cmd_yaffs_rmdir(dirname);
+	cmd_yaffs_mwrite_file(filename, (char *)addr, size);
 
-    return(0);
+	return 0;
 }
 
-int do_yrm (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_ymkdir(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
-    char *path = argv[1];
+	char *dirname;
 
-    cmd_yaffs_rm(path);
+	if (argc != 2) {
+		printf("Bad arguments: ymkdir dir_name\n");
+		return -1;
+	}
 
-    return(0);
+	dirname = argv[1];
+	cmd_yaffs_mkdir(dirname);
+
+	return 0;
 }
 
-int do_ymv (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_yrmdir(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
-    char *oldPath = argv[1];
-    char *newPath = argv[2];
+	char *dirname;
+
+	if (argc != 2) {
+		printf("Bad arguments: yrmdir dir_name\n");
+		return -1;
+	}
 
-    cmd_yaffs_mv(newPath, oldPath);
+	dirname = argv[1];
+	cmd_yaffs_rmdir(dirname);
 
-    return(0);
+	return 0;
 }
 
-int do_ydump (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_yrm(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
-    char *dirname = argv[1];
-    if (yaffs_DumpDevStruct(dirname) != 0)
-	printf("yaffs_DumpDevStruct returning error when dumping path: , %s\n", dirname);
-    return 0;
+	char *name;
+
+	if (argc != 2) {
+		printf("Bad arguments: yrm name\n");
+		return -1;
+	}
+
+	name = argv[1];
+
+	cmd_yaffs_rm(name);
+
+	return 0;
+}
+
+int do_ymv(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	char *oldPath;
+	char *newPath;
+
+	if (argc != 3) {
+		printf("Bad arguments: ymv old_path new_path\n");
+		return -1;
+	}
+
+	oldPath = argv[1];
+	newPath = argv[2];
+
+	cmd_yaffs_mv(newPath, oldPath);
+
+	return 0;
 }
 
-U_BOOT_CMD(
-    ymount, 3,  0,  do_ymount,
-    "mount yaffs",
-    ""
-);
-
-U_BOOT_CMD(
-    yumount, 3,  0,  do_yumount,
-    "unmount yaffs",
-    ""
-);
-
-U_BOOT_CMD(
-    yls,    4,  0,  do_yls,
-    "yaffs ls",
-    "[-l] name"
-);
-
-U_BOOT_CMD(
-    yrd,    2,  0,  do_yrd,
-    "read file from yaffs",
-    "filename"
-);
-
-U_BOOT_CMD(
-    ywr,    4,  0,  do_ywr,
-    "write file to yaffs",
-    "filename value num_vlues"
-);
-
-U_BOOT_CMD(
-    yrdm,   3,  0,  do_yrdm,
-    "read file to memory from yaffs",
-    "filename offset"
-);
-
-U_BOOT_CMD(
-    ywrm,   4,  0,  do_ywrm,
-    "write file from memory to yaffs",
-    "filename offset size"
-);
-
-U_BOOT_CMD(
-    ymkdir, 2,  0,  do_ymkdir,
-    "YAFFS mkdir",
-    "dirname"
-);
-
-U_BOOT_CMD(
-    yrmdir, 2,  0,  do_yrmdir,
-    "YAFFS rmdir",
-    "dirname"
-);
-
-U_BOOT_CMD(
-    yrm,    2,  0,  do_yrm,
-    "YAFFS rm",
-    "path"
-);
-
-U_BOOT_CMD(
-    ymv,    4,  0,  do_ymv,
-    "YAFFS mv",
-    "oldPath newPath"
-);
-
-U_BOOT_CMD(
-    ydump,  2,  0,  do_ydump,
-    "YAFFS device struct",
-    "dirname"
-);
+U_BOOT_CMD(ytrace, 2, 0, do_ytrace,
+	   "show/set yaffs trace mask",
+	   "ytrace [new_mask]  show/set yaffs trace mask");
+
+U_BOOT_CMD(ydevls, 1, 0, do_ydevls,
+	   "list yaffs mount points", "list yaffs mount points");
+
+U_BOOT_CMD(ydevconfig, 5, 0, do_ydevconfig,
+	   "configure yaffs mount point",
+	   "ydevconfig mtpoint mtd_id start_block end_block   configures a yaffs2 mount point");
+
+U_BOOT_CMD(ymount, 2, 0, do_ymount,
+	   "mount yaffs", "ymount mtpoint  mounts a yaffs2 mount point");
+
+U_BOOT_CMD(yumount, 2, 0, do_yumount,
+	   "unmount yaffs", "yunmount mtpoint  unmounts a yaffs2 mount point");
+
+U_BOOT_CMD(yls, 3, 0, do_yls, "yaffs ls", "yls [-l] dirname");
+
+U_BOOT_CMD(yrd, 2, 0, do_yrd,
+	   "read file from yaffs", "yrd path   read file from yaffs");
+
+U_BOOT_CMD(ywr, 4, 0, do_ywr,
+	   "write file to yaffs",
+	   "ywr filename value num_vlues   write values to yaffs file");
+
+U_BOOT_CMD(yrdm, 3, 0, do_yrdm,
+	   "read file to memory from yaffs",
+	   "yrdm filename offset    reads yaffs file into memory");
+
+U_BOOT_CMD(ywrm, 4, 0, do_ywrm,
+	   "write file from memory to yaffs",
+	   "ywrm filename offset size  writes memory to yaffs file");
+
+U_BOOT_CMD(ymkdir, 2, 0, do_ymkdir,
+	   "YAFFS mkdir", "ymkdir dir    create a yaffs directory");
+
+U_BOOT_CMD(yrmdir, 2, 0, do_yrmdir,
+	   "YAFFS rmdir", "yrmdir dirname   removes a yaffs directory");
+
+U_BOOT_CMD(yrm, 2, 0, do_yrm, "YAFFS rm", "yrm path   removes a yaffs file");
+
+U_BOOT_CMD(ymv, 4, 0, do_ymv,
+	   "YAFFS mv",
+	   "ymv old_path new_path   moves/rename files within a yaffs mount point");
diff --git a/common/env_onenand.c b/common/env_onenand.c
index 652665a189..7197ab6585 100644
--- a/common/env_onenand.c
+++ b/common/env_onenand.c
@@ -33,7 +33,7 @@
 #include <errno.h>
 #include <onenand_uboot.h>
 
-#include <linux/mtd/compat.h>
+#include <linux/compat.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/onenand.h>
 
diff --git a/common/env_remote.c b/common/env_remote.c
new file mode 100644
index 0000000000..3bf0f957b3
--- /dev/null
+++ b/common/env_remote.c
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+#include <linux/stddef.h>
+
+char *env_name_spec = "Remote";
+
+#ifdef ENV_IS_EMBEDDED
+env_t *env_ptr = &environment;
+#else /* ! ENV_IS_EMBEDDED */
+env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR;
+#endif /* ENV_IS_EMBEDDED */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !defined(CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_OFFSET 0
+#endif
+
+uchar env_get_char_spec(int index)
+{
+	return *((uchar *)(gd->env_addr + index));
+}
+
+int env_init(void)
+{
+	if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
+		gd->env_addr = (ulong)&(env_ptr->data);
+		gd->env_valid = 1;
+		return 0;
+	}
+
+	gd->env_addr = (ulong)default_environment;
+	gd->env_valid = 0;
+	return 0;
+}
+
+#ifdef CONFIG_CMD_SAVEENV
+int saveenv(void)
+{
+#ifdef CONFIG_SRIOBOOT_SLAVE
+	printf("Can not support the 'saveenv' when boot from SRIO!\n");
+	return 1;
+#else
+	return 0;
+#endif
+}
+#endif /* CONFIG_CMD_SAVEENV */
+
+void env_relocate_spec(void)
+{
+#ifndef ENV_IS_EMBEDDED
+	env_import((char *)env_ptr, 1);
+#endif
+}
diff --git a/common/hush.c b/common/hush.c
index 672ab9e157..888c4a1a32 100644
--- a/common/hush.c
+++ b/common/hush.c
@@ -1042,7 +1042,7 @@ static void get_user_input(struct in_str *i)
 		else {
 			if (console_buffer[0] != '\n') {
 				strcpy(the_command,console_buffer);
-				flag_repeat = 1;
+				/* flag_repeat = 1; */
 			}
 			else {
 				do_repeat = 1;
diff --git a/common/image.c b/common/image.c
index 342b315918..ba6f010ac6 100644
--- a/common/image.c
+++ b/common/image.c
@@ -78,12 +78,13 @@ static const table_entry_t uimage_arch[] = {
 	{	IH_ARCH_INVALID,	NULL,		"Invalid ARCH",	},
 	{	IH_ARCH_ALPHA,		"alpha",	"Alpha",	},
 	{	IH_ARCH_ARM,		"arm",		"ARM",		},
+	{	IH_ARCH_MIPS,		"mips",		"MIPS",		},
+	{	IH_ARCH_MIPS64,		"mips64",	"MIPS 64 Bit",	},
+#ifndef CONFIG_SPL_BUILD
 	{	IH_ARCH_I386,		"x86",		"Intel x86",	},
 	{	IH_ARCH_IA64,		"ia64",		"IA64",		},
 	{	IH_ARCH_M68K,		"m68k",		"M68K",		},
 	{	IH_ARCH_MICROBLAZE,	"microblaze",	"MicroBlaze",	},
-	{	IH_ARCH_MIPS,		"mips",		"MIPS",		},
-	{	IH_ARCH_MIPS64,		"mips64",	"MIPS 64 Bit",	},
 	{	IH_ARCH_NIOS2,		"nios2",	"NIOS II",	},
 	{	IH_ARCH_PPC,		"powerpc",	"PowerPC",	},
 	{	IH_ARCH_PPC,		"ppc",		"PowerPC",	},
@@ -95,19 +96,21 @@ static const table_entry_t uimage_arch[] = {
 	{	IH_ARCH_AVR32,		"avr32",	"AVR32",	},
 	{	IH_ARCH_NDS32,		"nds32",	"NDS32",	},
 	{	IH_ARCH_OPENRISC,	"or1k",		"OpenRISC 1000",},
+#endif
 	{	-1,			"",		"",		},
 };
 
 static const table_entry_t uimage_os[] = {
 	{	IH_OS_INVALID,	NULL,		"Invalid OS",		},
 	{	IH_OS_LINUX,	"linux",	"Linux",		},
+	{	IH_OS_U_BOOT,	"u-boot",	"U-Boot",		},
+#ifndef CONFIG_SPL_BUILD
 #if defined(CONFIG_LYNXKDI) || defined(USE_HOSTCC)
 	{	IH_OS_LYNXOS,	"lynxos",	"LynxOS",		},
 #endif
 	{	IH_OS_NETBSD,	"netbsd",	"NetBSD",		},
 	{	IH_OS_OSE,	"ose",		"Enea OSE",		},
 	{	IH_OS_RTEMS,	"rtems",	"RTEMS",		},
-	{	IH_OS_U_BOOT,	"u-boot",	"U-Boot",		},
 #if defined(CONFIG_CMD_ELF) || defined(USE_HOSTCC)
 	{	IH_OS_QNX,	"qnx",		"QNX",			},
 	{	IH_OS_VXWORKS,	"vxworks",	"VxWorks",		},
@@ -128,6 +131,7 @@ static const table_entry_t uimage_os[] = {
 	{	IH_OS_SOLARIS,	"solaris",	"Solaris",		},
 	{	IH_OS_SVR4,	"svr4",		"SVR4",			},
 #endif
+#endif
 	{	-1,		"",		"",			},
 };
 
@@ -1829,7 +1833,7 @@ static int fit_parse_spec(const char *spec, char sepc, ulong addr_curr,
  *     addr and conf_name are set accordingly
  *     0 otherwise
  */
-inline int fit_parse_conf(const char *spec, ulong addr_curr,
+int fit_parse_conf(const char *spec, ulong addr_curr,
 		ulong *addr, const char **conf_name)
 {
 	return fit_parse_spec(spec, '#', addr_curr, addr, conf_name);
@@ -1855,7 +1859,7 @@ inline int fit_parse_conf(const char *spec, ulong addr_curr,
  *     addr and image_name are set accordingly
  *     0 otherwise
  */
-inline int fit_parse_subimage(const char *spec, ulong addr_curr,
+int fit_parse_subimage(const char *spec, ulong addr_curr,
 		ulong *addr, const char **image_name)
 {
 	return fit_parse_spec(spec, ':', addr_curr, addr, image_name);
diff --git a/common/main.c b/common/main.c
index 3b9e39a980..8b7fd8fffe 100644
--- a/common/main.c
+++ b/common/main.c
@@ -43,6 +43,8 @@
 #include <linux/ctype.h>
 #include <menu.h>
 
+/* #define DEBUG_BOOTKEYS	1 */
+
 #if defined(CONFIG_SILENT_CONSOLE) || defined(CONFIG_POST) || defined(CONFIG_CMDLINE_EDITING)
 DECLARE_GLOBAL_DATA_PTR;
 #endif
@@ -50,7 +52,7 @@ DECLARE_GLOBAL_DATA_PTR;
 /*
  * Board-specific Platform code can reimplement show_boot_progress () if needed
  */
-void inline __show_boot_progress (int val) {}
+void __show_boot_progress (int val) {}
 void show_boot_progress (int val) __attribute__((weak, alias("__show_boot_progress")));
 
 #if defined(CONFIG_UPDATE_TFTP)
@@ -95,7 +97,7 @@ static inline
 int abortboot(int bootdelay)
 {
 	int abort = 0;
-	uint64_t etime = endtick(bootdelay);
+	uint64_t etime = endtick(1);
 	struct {
 		char* str;
 		u_int len;
@@ -113,10 +115,6 @@ int abortboot(int bootdelay)
 	u_int presskey_max = 0;
 	u_int i;
 
-#  ifdef CONFIG_AUTOBOOT_PROMPT
-	printf(CONFIG_AUTOBOOT_PROMPT);
-#  endif
-
 #  ifdef CONFIG_AUTOBOOT_DELAY_STR
 	if (delaykey[0].str == NULL)
 		delaykey[0].str = CONFIG_AUTOBOOT_DELAY_STR;
@@ -134,6 +132,10 @@ int abortboot(int bootdelay)
 		delaykey[3].str = CONFIG_AUTOBOOT_STOP_STR2;
 #  endif
 
+#  if DEBUG_BOOTKEYS
+	printf("\n");
+#  endif
+
 	for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i ++) {
 		delaykey[i].len = delaykey[i].str == NULL ?
 				    0 : strlen (delaykey[i].str);
@@ -144,16 +146,46 @@ int abortboot(int bootdelay)
 				    presskey_max : delaykey[i].len;
 
 #  if DEBUG_BOOTKEYS
-		printf("%s key:<%s>\n",
-		       delaykey[i].retry ? "delay" : "stop",
-		       delaykey[i].str ? delaykey[i].str : "NULL");
+		u_int j;
+		printf("%s key: <", delaykey[i].retry ? "Delay" : "Stop ");
+		if (delaykey[i].str) {
+			for (j = 0; j < delaykey[i].len; j++) {
+				if (delaykey[i].str[j] < 0x80 &&
+						isprint(delaykey[i].str[j])) {
+					printf("%c", delaykey[i].str[j]);
+				} else {
+					printf("\\x%02X", delaykey[i].str[j]);
+				}
+			}
+		} else {
+			printf("NULL");
+		}
+		printf(">\n");
 #  endif
 	}
 
+#  if DEBUG_BOOTKEYS
+	printf("\n");
+#  endif
+
+#  ifdef CONFIG_AUTOBOOT_PROMPT
+	printf(CONFIG_AUTOBOOT_PROMPT);
+#  else
+	printf("Hit delay/stop key to delay/stop autoboot: %2d ", bootdelay);
+#  endif
+
 	/* In order to keep up with incoming data, check timeout only
 	 * when catch up.
 	 */
-	do {
+	while (!abort && bootdelay > 0) {
+		if (get_ticks() > etime) {
+			etime = endtick(1);
+			--bootdelay;
+#  ifndef CONFIG_AUTOBOOT_PROMPT
+			printf("\b\b\b%2d ", bootdelay);
+#  endif
+		}
+
 		if (tstc()) {
 			if (presskey_len < presskey_max) {
 				presskey [presskey_len ++] = getc();
@@ -172,11 +204,14 @@ int abortboot(int bootdelay)
 			    memcmp (presskey + presskey_len - delaykey[i].len,
 				    delaykey[i].str,
 				    delaykey[i].len) == 0) {
+#  ifndef CONFIG_AUTOBOOT_PROMPT
+				puts("\n");
+#  endif
 #  if DEBUG_BOOTKEYS
-				printf("got %skey\n",
+				printf("Got %s key\n",
 				       delaykey[i].retry ? "delay" : "stop");
 #  endif
-
+				puts("\n");
 #  ifdef CONFIG_BOOT_RETRY_TIME
 				/* don't retry auto boot */
 				if (! delaykey[i].retry)
@@ -185,12 +220,17 @@ int abortboot(int bootdelay)
 				abort = 1;
 			}
 		}
-	} while (!abort && get_ticks() <= etime);
+	}
 
+	if (!abort) {
+#  ifndef CONFIG_AUTOBOOT_PROMPT
+		puts("\n");
+#  endif
 #  if DEBUG_BOOTKEYS
-	if (!abort)
-		puts("key timeout\n");
+		puts("Key timeout\n");
 #  endif
+		puts("\n");
+	}
 
 #ifdef CONFIG_SILENT_CONSOLE
 	if (abort)
@@ -227,7 +267,9 @@ int abortboot(int bootdelay)
 	if (bootdelay >= 0) {
 		if (tstc()) {	/* we got a key press	*/
 			(void) getc();  /* consume input	*/
+#ifndef CONFIG_MENUPROMPT
 			puts ("\b\b\b 0");
+#endif
 			abort = 1;	/* don't auto boot	*/
 		}
 	}
@@ -252,7 +294,9 @@ int abortboot(int bootdelay)
 			udelay(10000);
 		}
 
+#ifndef CONFIG_MENUPROMPT
 		printf("\b\b\b%2d ", bootdelay);
+#endif
 	}
 
 	putc('\n');
@@ -271,6 +315,7 @@ int abortboot(int bootdelay)
 
 void main_loop (void)
 {
+	int autoboot;
 #ifndef CONFIG_SYS_HUSH_PARSER
 	static char lastcommand[CONFIG_SYS_CBSIZE] = { 0, };
 	int len;
@@ -376,7 +421,12 @@ void main_loop (void)
 
 	debug ("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>");
 
-	if (bootdelay >= 0 && s && !abortboot (bootdelay)) {
+# ifdef REBOOT_WHEN_CRASH
+	autoboot = (s != NULL);
+# else
+	autoboot = (bootdelay >= 0 && s && !abortboot (bootdelay));
+# endif
+	if (autoboot) {
 # ifdef CONFIG_AUTOBOOT_KEYED
 		int prev = disable_ctrlc(1);	/* disable Control C checking */
 # endif
@@ -973,7 +1023,6 @@ int readline_into_buffer(const char *const prompt, char *buffer, int timeout)
 
 #ifdef CONFIG_SHOW_ACTIVITY
 		while (!tstc()) {
-			extern void show_activity(int arg);
 			show_activity(0);
 			WATCHDOG_RESET();
 		}
diff --git a/common/usb.c b/common/usb.c
index 1ec30bc058..c80155ce76 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -47,6 +47,7 @@
 #include <common.h>
 #include <command.h>
 #include <asm/processor.h>
+#include <linux/compiler.h>
 #include <linux/ctype.h>
 #include <asm/byteorder.h>
 #include <asm/unaligned.h>
@@ -169,7 +170,7 @@ int usb_control_msg(struct usb_device *dev, unsigned int pipe,
 			unsigned short value, unsigned short index,
 			void *data, unsigned short size, int timeout)
 {
-	struct devrequest setup_packet;
+	ALLOC_CACHE_ALIGN_BUFFER(struct devrequest, setup_packet, 1);
 
 	if ((timeout == 0) && (!asynch_allowed)) {
 		/* request for a asynch control pipe is not allowed */
@@ -177,17 +178,17 @@ int usb_control_msg(struct usb_device *dev, unsigned int pipe,
 	}
 
 	/* set setup command */
-	setup_packet.requesttype = requesttype;
-	setup_packet.request = request;
-	setup_packet.value = cpu_to_le16(value);
-	setup_packet.index = cpu_to_le16(index);
-	setup_packet.length = cpu_to_le16(size);
+	setup_packet->requesttype = requesttype;
+	setup_packet->request = request;
+	setup_packet->value = cpu_to_le16(value);
+	setup_packet->index = cpu_to_le16(index);
+	setup_packet->length = cpu_to_le16(size);
 	USB_PRINTF("usb_control_msg: request: 0x%X, requesttype: 0x%X, " \
 		   "value 0x%X index 0x%X length 0x%X\n",
 		   request, requesttype, value, index, size);
 	dev->status = USB_ST_NOT_PROC; /*not yet processed */
 
-	submit_control_msg(dev, pipe, data, size, &setup_packet);
+	submit_control_msg(dev, pipe, data, size, setup_packet);
 	if (timeout == 0)
 		return (int)size;
 
@@ -261,7 +262,7 @@ int usb_maxpacket(struct usb_device *dev, unsigned long pipe)
  *
  * NOTE: Similar behaviour was observed with GCC4.6 on ARMv5.
  */
-static void  __attribute__((noinline))
+static void noinline
 usb_set_maxpacket_ep(struct usb_device *dev, int if_idx, int ep_idx)
 {
 	int b;
@@ -681,7 +682,7 @@ static int usb_string_sub(struct usb_device *dev, unsigned int langid,
  */
 int usb_string(struct usb_device *dev, int index, char *buf, size_t size)
 {
-	unsigned char mybuf[USB_BUFSIZ];
+	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, mybuf, USB_BUFSIZ);
 	unsigned char *tbuf;
 	int err;
 	unsigned int u, idx;
@@ -781,7 +782,7 @@ int usb_new_device(struct usb_device *dev)
 {
 	int addr, err;
 	int tmp;
-	unsigned char tmpbuf[USB_BUFSIZ];
+	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, tmpbuf, USB_BUFSIZ);
 
 	/* We still haven't set the Address yet */
 	addr = dev->devnum;
@@ -908,8 +909,8 @@ int usb_new_device(struct usb_device *dev)
 	le16_to_cpus(&dev->descriptor.idProduct);
 	le16_to_cpus(&dev->descriptor.bcdDevice);
 	/* only support for one config for now */
-	usb_get_configuration_no(dev, &tmpbuf[0], 0);
-	usb_parse_config(dev, &tmpbuf[0], 0);
+	usb_get_configuration_no(dev, tmpbuf, 0);
+	usb_parse_config(dev, tmpbuf, 0);
 	usb_set_maxpacket(dev);
 	/* we set the default configuration here */
 	if (usb_set_configuration(dev, dev->config.desc.bConfigurationValue)) {
diff --git a/common/usb_hub.c b/common/usb_hub.c
index e0edaad56b..f35ad95324 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -153,7 +153,7 @@ int hub_port_reset(struct usb_device *dev, int port,
 			unsigned short *portstat)
 {
 	int tries;
-	struct usb_port_status portsts;
+	ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
 	unsigned short portstatus, portchange;
 
 	USB_HUB_PRINTF("hub_port_reset: resetting port %d...\n", port);
@@ -162,13 +162,13 @@ int hub_port_reset(struct usb_device *dev, int port,
 		usb_set_port_feature(dev, port + 1, USB_PORT_FEAT_RESET);
 		mdelay(200);
 
-		if (usb_get_port_status(dev, port + 1, &portsts) < 0) {
+		if (usb_get_port_status(dev, port + 1, portsts) < 0) {
 			USB_HUB_PRINTF("get_port_status failed status %lX\n",
 					dev->status);
 			return -1;
 		}
-		portstatus = le16_to_cpu(portsts.wPortStatus);
-		portchange = le16_to_cpu(portsts.wPortChange);
+		portstatus = le16_to_cpu(portsts->wPortStatus);
+		portchange = le16_to_cpu(portsts->wPortChange);
 
 		USB_HUB_PRINTF("portstatus %x, change %x, %s\n",
 				portstatus, portchange,
@@ -206,19 +206,19 @@ int hub_port_reset(struct usb_device *dev, int port,
 void usb_hub_port_connect_change(struct usb_device *dev, int port)
 {
 	struct usb_device *usb;
-	struct usb_port_status portsts;
+	ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
 	unsigned short portstatus;
 
 	/* Check status */
-	if (usb_get_port_status(dev, port + 1, &portsts) < 0) {
+	if (usb_get_port_status(dev, port + 1, portsts) < 0) {
 		USB_HUB_PRINTF("get_port_status failed\n");
 		return;
 	}
 
-	portstatus = le16_to_cpu(portsts.wPortStatus);
+	portstatus = le16_to_cpu(portsts->wPortStatus);
 	USB_HUB_PRINTF("portstatus %x, change %x, %s\n",
 			portstatus,
-			le16_to_cpu(portsts.wPortChange),
+			le16_to_cpu(portsts->wPortChange),
 			portspeed(portstatus));
 
 	/* Clear the connection change status */
@@ -267,7 +267,8 @@ void usb_hub_port_connect_change(struct usb_device *dev, int port)
 static int usb_hub_configure(struct usb_device *dev)
 {
 	int i;
-	unsigned char buffer[USB_BUFSIZ], *bitmap;
+	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, USB_BUFSIZ);
+	unsigned char *bitmap;
 	struct usb_hub_descriptor *descriptor;
 	struct usb_hub_device *hub;
 #ifdef USB_HUB_DEBUG
@@ -389,16 +390,16 @@ static int usb_hub_configure(struct usb_device *dev)
 	usb_hub_power_on(hub);
 
 	for (i = 0; i < dev->maxchild; i++) {
-		struct usb_port_status portsts;
+		ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
 		unsigned short portstatus, portchange;
 
-		if (usb_get_port_status(dev, i + 1, &portsts) < 0) {
+		if (usb_get_port_status(dev, i + 1, portsts) < 0) {
 			USB_HUB_PRINTF("get_port_status failed\n");
 			continue;
 		}
 
-		portstatus = le16_to_cpu(portsts.wPortStatus);
-		portchange = le16_to_cpu(portsts.wPortChange);
+		portstatus = le16_to_cpu(portsts->wPortStatus);
+		portchange = le16_to_cpu(portsts->wPortChange);
 		USB_HUB_PRINTF("Port %d Status %X Change %X\n",
 				i + 1, portstatus, portchange);
 
diff --git a/common/usb_storage.c b/common/usb_storage.c
index 12083337b0..faad23706f 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -79,8 +79,7 @@ static const unsigned char us_direction[256/8] = {
 };
 #define US_DIRECTION(x) ((us_direction[x>>3] >> (x & 7)) & 1)
 
-static unsigned char usb_stor_buf[512];
-static ccb usb_ccb;
+static ccb usb_ccb __attribute__((aligned(ARCH_DMA_MINALIGN)));
 
 /*
  * CBI style
@@ -210,17 +209,17 @@ int usb_stor_info(void)
 static unsigned int usb_get_max_lun(struct us_data *us)
 {
 	int len;
-	unsigned char result;
+	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, result, 1);
 	len = usb_control_msg(us->pusb_dev,
 			      usb_rcvctrlpipe(us->pusb_dev, 0),
 			      US_BBB_GET_MAX_LUN,
 			      USB_TYPE_CLASS | USB_RECIP_INTERFACE | USB_DIR_IN,
 			      0, us->ifnum,
-			      &result, sizeof(result),
+			      result, sizeof(char),
 			      USB_CNTL_TIMEOUT * 5);
 	USB_STOR_PRINTF("Get Max LUN -> len = %i, result = %i\n",
-			len, (int) result);
-	return (len > 0) ? result : 0;
+			len, (int) *result);
+	return (len > 0) ? *result : 0;
 }
 
 /*******************************************************************************
@@ -233,9 +232,6 @@ int usb_stor_scan(int mode)
 	unsigned char i;
 	struct usb_device *dev;
 
-	/* GJ */
-	memset(usb_stor_buf, 0, sizeof(usb_stor_buf));
-
 	if (mode == 1)
 		printf("       scanning bus for storage devices... ");
 
@@ -499,7 +495,7 @@ int usb_stor_BBB_comdat(ccb *srb, struct us_data *us)
 	int actlen;
 	int dir_in;
 	unsigned int pipe;
-	umass_bbb_cbw_t cbw;
+	ALLOC_CACHE_ALIGN_BUFFER(umass_bbb_cbw_t, cbw, 1);
 
 	dir_in = US_DIRECTION(srb->cmd[0]);
 
@@ -522,16 +518,16 @@ int usb_stor_BBB_comdat(ccb *srb, struct us_data *us)
 	/* always OUT to the ep */
 	pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out);
 
-	cbw.dCBWSignature = cpu_to_le32(CBWSIGNATURE);
-	cbw.dCBWTag = cpu_to_le32(CBWTag++);
-	cbw.dCBWDataTransferLength = cpu_to_le32(srb->datalen);
-	cbw.bCBWFlags = (dir_in ? CBWFLAGS_IN : CBWFLAGS_OUT);
-	cbw.bCBWLUN = srb->lun;
-	cbw.bCDBLength = srb->cmdlen;
+	cbw->dCBWSignature = cpu_to_le32(CBWSIGNATURE);
+	cbw->dCBWTag = cpu_to_le32(CBWTag++);
+	cbw->dCBWDataTransferLength = cpu_to_le32(srb->datalen);
+	cbw->bCBWFlags = (dir_in ? CBWFLAGS_IN : CBWFLAGS_OUT);
+	cbw->bCBWLUN = srb->lun;
+	cbw->bCDBLength = srb->cmdlen;
 	/* copy the command data into the CBW command data buffer */
 	/* DST SRC LEN!!! */
-	memcpy(cbw.CBWCDB, srb->cmd, srb->cmdlen);
-	result = usb_bulk_msg(us->pusb_dev, pipe, &cbw, UMASS_BBB_CBW_SIZE,
+	memcpy(cbw->CBWCDB, srb->cmd, srb->cmdlen);
+	result = usb_bulk_msg(us->pusb_dev, pipe, cbw, UMASS_BBB_CBW_SIZE,
 			      &actlen, USB_CNTL_TIMEOUT * 5);
 	if (result < 0)
 		USB_STOR_PRINTF("usb_stor_BBB_comdat:usb_bulk_msg error\n");
@@ -675,7 +671,7 @@ int usb_stor_BBB_transport(ccb *srb, struct us_data *us)
 	int dir_in;
 	int actlen, data_actlen;
 	unsigned int pipe, pipein, pipeout;
-	umass_bbb_csw_t csw;
+	ALLOC_CACHE_ALIGN_BUFFER(umass_bbb_csw_t, csw, 1);
 #ifdef BBB_XPORT_TRACE
 	unsigned char *ptr;
 	int index;
@@ -733,7 +729,7 @@ st:
 	retry = 0;
 again:
 	USB_STOR_PRINTF("STATUS phase\n");
-	result = usb_bulk_msg(us->pusb_dev, pipein, &csw, UMASS_BBB_CSW_SIZE,
+	result = usb_bulk_msg(us->pusb_dev, pipein, csw, UMASS_BBB_CSW_SIZE,
 				&actlen, USB_CNTL_TIMEOUT*5);
 
 	/* special handling of STALL in STATUS phase */
@@ -753,28 +749,28 @@ again:
 		return USB_STOR_TRANSPORT_FAILED;
 	}
 #ifdef BBB_XPORT_TRACE
-	ptr = (unsigned char *)&csw;
+	ptr = (unsigned char *)csw;
 	for (index = 0; index < UMASS_BBB_CSW_SIZE; index++)
 		printf("ptr[%d] %#x ", index, ptr[index]);
 	printf("\n");
 #endif
 	/* misuse pipe to get the residue */
-	pipe = le32_to_cpu(csw.dCSWDataResidue);
+	pipe = le32_to_cpu(csw->dCSWDataResidue);
 	if (pipe == 0 && srb->datalen != 0 && srb->datalen - data_actlen != 0)
 		pipe = srb->datalen - data_actlen;
-	if (CSWSIGNATURE != le32_to_cpu(csw.dCSWSignature)) {
+	if (CSWSIGNATURE != le32_to_cpu(csw->dCSWSignature)) {
 		USB_STOR_PRINTF("!CSWSIGNATURE\n");
 		usb_stor_BBB_reset(us);
 		return USB_STOR_TRANSPORT_FAILED;
-	} else if ((CBWTag - 1) != le32_to_cpu(csw.dCSWTag)) {
+	} else if ((CBWTag - 1) != le32_to_cpu(csw->dCSWTag)) {
 		USB_STOR_PRINTF("!Tag\n");
 		usb_stor_BBB_reset(us);
 		return USB_STOR_TRANSPORT_FAILED;
-	} else if (csw.bCSWStatus > CSWSTATUS_PHASE) {
+	} else if (csw->bCSWStatus > CSWSTATUS_PHASE) {
 		USB_STOR_PRINTF(">PHASE\n");
 		usb_stor_BBB_reset(us);
 		return USB_STOR_TRANSPORT_FAILED;
-	} else if (csw.bCSWStatus == CSWSTATUS_PHASE) {
+	} else if (csw->bCSWStatus == CSWSTATUS_PHASE) {
 		USB_STOR_PRINTF("=PHASE\n");
 		usb_stor_BBB_reset(us);
 		return USB_STOR_TRANSPORT_FAILED;
@@ -782,7 +778,7 @@ again:
 		USB_STOR_PRINTF("transferred %dB instead of %ldB\n",
 			data_actlen, srb->datalen);
 		return USB_STOR_TRANSPORT_FAILED;
-	} else if (csw.bCSWStatus == CSWSTATUS_FAILED) {
+	} else if (csw->bCSWStatus == CSWSTATUS_FAILED) {
 		USB_STOR_PRINTF("FAILED\n");
 		return USB_STOR_TRANSPORT_FAILED;
 	}
@@ -1343,7 +1339,8 @@ int usb_stor_get_info(struct usb_device *dev, struct us_data *ss,
 		      block_dev_desc_t *dev_desc)
 {
 	unsigned char perq, modi;
-	unsigned long cap[2];
+	ALLOC_CACHE_ALIGN_BUFFER(unsigned long, cap, 2);
+	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, usb_stor_buf, 36);
 	unsigned long *capacity, *blksz;
 	ccb *pccb = &usb_ccb;
 
@@ -1367,9 +1364,9 @@ int usb_stor_get_info(struct usb_device *dev, struct us_data *ss,
 		/* drive is removable */
 		dev_desc->removable = 1;
 	}
-	memcpy(&dev_desc->vendor[0], &usb_stor_buf[8], 8);
-	memcpy(&dev_desc->product[0], &usb_stor_buf[16], 16);
-	memcpy(&dev_desc->revision[0], &usb_stor_buf[32], 4);
+	memcpy(&dev_desc->vendor[0], (const void *) &usb_stor_buf[8], 8);
+	memcpy(&dev_desc->product[0], (const void *) &usb_stor_buf[16], 16);
+	memcpy(&dev_desc->revision[0], (const void *) &usb_stor_buf[32], 4);
 	dev_desc->vendor[8] = 0;
 	dev_desc->product[16] = 0;
 	dev_desc->revision[4] = 0;
diff --git a/config.mk b/config.mk
index fa33e62851..5b570e1092 100644
--- a/config.mk
+++ b/config.mk
@@ -104,19 +104,27 @@ HOSTCFLAGS	+= -pedantic
 
 #########################################################################
 #
-# Option checker (courtesy linux kernel) to ensure
+# Option checker, gcc version (courtesy linux kernel) to ensure
 # only supported compiler options are used
 #
 CC_OPTIONS_CACHE_FILE := $(OBJTREE)/include/generated/cc_options.mk
-CC_TEST_OFILE := $(OBJTREE)/include/generated/cc_test_file.o
+CC_TEST_OFILE = $(OBJTREE)/include/generated/cc_test_file_$$$$.o
 
 -include $(CC_OPTIONS_CACHE_FILE)
 
-cc-option-sys = $(shell mkdir -p $(dir $(CC_TEST_OFILE)); \
-		if $(CC) $(CFLAGS) $(1) -S -xc /dev/null -o $(CC_TEST_OFILE) \
-		> /dev/null 2>&1; then \
-		echo 'CC_OPTIONS += $(strip $1)' >> $(CC_OPTIONS_CACHE_FILE); \
-		echo "$(1)"; fi)
+cc-option-sys-cmd =					\
+	set -e;						\
+	mkdir -p "$(dir $(CC_TEST_OFILE))";		\
+	if ( $(CC) $(CFLAGS) $(1) -S -xc /dev/null	\
+		-o "$(CC_TEST_OFILE)" )			\
+		>/dev/null 2>&1; then			\
+	echo "CC_OPTIONS += $(strip $1)"		\
+		>> "$(CC_OPTIONS_CACHE_FILE)";		\
+	echo "$(1)";					\
+	fi;						\
+	rm -f "$(CC_TEST_OFILE)"
+
+cc-option-sys = $(shell $(cc-option-sys-cmd))
 
 ifeq ($(CONFIG_CC_OPT_CACHE_DISABLE),y)
 cc-option = $(strip $(if $(call cc-option-sys,$1),$1,$2))
@@ -125,6 +133,10 @@ cc-option = $(strip $(if $(findstring $1,$(CC_OPTIONS)),$1,\
 		$(if $(call cc-option-sys,$1),$1,$2)))
 endif
 
+# cc-version
+# Usage gcc-ver := $(call cc-version)
+cc-version = $(shell $(SHELL) $(SRCTREE)/tools/gcc-version.sh $(CC))
+
 #
 # Include the make variables (CC, etc...)
 #
@@ -213,7 +225,10 @@ ifneq ($(OBJTREE),$(SRCTREE))
 CPPFLAGS += -I$(OBJTREE)/include2 -I$(OBJTREE)/include
 endif
 
-CPPFLAGS += -I$(TOPDIR)/include
+
+CPPFLAGS += -DCHARGER_IN_RECOVERY
+
+CPPFLAGS += -I$(TOPDIR)/include -mno-unaligned-access
 CPPFLAGS += -fno-builtin -ffreestanding -nostdinc	\
 	-isystem $(gccincdir) -pipe $(PLATFORM_CPPFLAGS)
 
@@ -305,14 +320,19 @@ ALL_CFLAGS += $(EXTRA_CPPFLAGS)
 EXTRA_CPPFLAGS_DEP = $(CPPFLAGS_$(BCURDIR)/$(addsuffix .o,$(basename $<))) \
 		$(CPPFLAGS_$(BCURDIR))
 $(obj)%.s:	%.S
+	$(XECHO) "	CPP	$<"
 	$(CPP) $(ALL_AFLAGS) -o $@ $<
 $(obj)%.o:	%.S
+	$(XECHO) "	CC	$<"
 	$(CC)  $(ALL_AFLAGS) -o $@ $< -c
 $(obj)%.o:	%.c
+	$(XECHO) "	CC	$<"
 	$(CC)  $(ALL_CFLAGS) -o $@ $< -c
 $(obj)%.i:	%.c
+	$(XECHO) "	CC	$<"
 	$(CPP) $(ALL_CFLAGS) -o $@ $< -c
 $(obj)%.s:	%.c
+	$(XECHO) "	CC	$<"
 	$(CC)  $(ALL_CFLAGS) -o $@ $< -c -S
 
 #########################################################################
diff --git a/customer.mk b/customer.mk
new file mode 100644
index 0000000000..7302385287
--- /dev/null
+++ b/customer.mk
@@ -0,0 +1,47 @@
+# different one for slc
+# flash config
+BOARD_NAND_PAGE_SIZE := 4096
+BOARD_NAND_SPARE_SIZE := 128
+# 4096 * 64
+BOARD_FLASH_BLOCK_SIZE := 262144
+
+# touch screen selection
+   RDA_CUSTOMER_DRV_TS := TS_GSL168X
+#  GSL168X_MODEL := GSL168X_MODEL_35_HVGA_1680
+#  GSL168X_MODEL := GSL168X_MODEL_35_HVGA_1688E
+   GSL168X_MODEL := GSL168X_MODEL_40_WVGA
+#RDA_CUSTOMER_DRV_TS := TS_MSG2133 TS_FT6X06
+# RDA_CUSTOMER_DRV_TS := TS_FT6X06
+#   TS_FT6X06_MODEL := VIR_HVGA_VER
+# RDA_CUSTOMER_DRV_TS := TS_IT7252
+# RDA_CUSTOMER_DRV_TS := TS_GTP868
+# RDA_CUSTOMER_DRV_TS := TS_ICN831X
+
+# gsensor selection
+# RDA_CUSTOMER_DRV_GS := GS_MMA865X
+# RDA_CUSTOMER_DRV_GS := GS_MMA7660
+# RDA_CUSTOMER_DRV_GS := GS_STK8312
+# RDA_CUSTOMER_DRV_GS := GS_MMA845X
+RDA_CUSTOMER_DRV_GS := GS_MXC622X
+
+# light sensor selection
+RDA_CUSTOMER_DRV_LS := LS_NONE
+
+#camera sensor selection
+# supported list in device/rda/driver/camera/inc/
+# RDA_CUSTOMER_DRV_CSB := GC0309
+RDA_CUSTOMER_DRV_CSB := GC2035
+#RDA_CUSTOMER_DRV_CSF := GC0329
+#RDA_CUSTOMER_DRV_ATV := RDA5888
+
+export RDA_CUSTOMER_DRV_TS
+ifeq ($(RDA_CUSTOMER_DRV_TS), TS_GSL168X)
+export GSL168X_MODEL
+endif
+export RDA_CUSTOMER_DRV_GS
+export RDA_CUSTOMER_DRV_LS
+export RDA_CUSTOMER_DRV_CSB
+#export RDA_CUSTOMER_DRV_CSF
+export TS_FT6X06_MODEL
+#export RDA_CUSTOMER_DRV_ATV
+
diff --git a/disk/part.c b/disk/part.c
index 8ca5d4bdfc..f54a704e99 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -1,6 +1,7 @@
 /*
  * (C) Copyright 2001
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Copyright (C) 2011-2012 Google, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -25,6 +26,7 @@
 #include <command.h>
 #include <ide.h>
 #include <part.h>
+#include <mmc/sparse.h>
 
 #undef	PART_DEBUG
 
@@ -74,7 +76,7 @@ static const struct block_drvr block_drvr[] = {
 
 DECLARE_GLOBAL_DATA_PTR;
 
-block_dev_desc_t *get_dev(char* ifname, int dev)
+block_dev_desc_t *get_dev(const char* ifname, int dev)
 {
 	const struct block_drvr *drvr = block_drvr;
 	block_dev_desc_t* (*reloc_get_dev)(int dev);
@@ -100,11 +102,642 @@ block_dev_desc_t *get_dev(char* ifname, int dev)
 	}
 	return NULL;
 }
+/*
+ * Given a devname with a concatenated ifname and an id (e.g. "mmc0"), return
+ * a pointer to the associated block device structure.
+ */
+block_dev_desc_t *get_dev_by_name(char *devname)
+{
+	char *digit_pointer, *ep, c;
+	int devid;
+	for (digit_pointer = devname; (c = *digit_pointer); ) {
+		if ('0' <= c && c <= '9') {
+			/*
+			 * Due to the ambiguity of determining if characters in
+			 * the range of 'a' to 'f' are hex digits or part of
+			 * the device interface, we use base 10.
+			 */
+			devid = (int)simple_strtoul(digit_pointer, &ep, 10);
+			if (*ep != '\0') {
+				/*
+				 * There's non-digits after our digits, keep
+				 * scanning for digits at the end.
+				 */
+				digit_pointer = ep;
+				continue;
+			}
+			/*
+			 * Normally, you would think we would put a '\0' at
+			 * digit_pointer, but we don't want to modify the
+			 * passed devname, and get_dev() uses strncmp() so it
+			 * will match even if there is "junk" after the match.
+			 * In our case, the "junk" is the id that we just
+			 * parsed.  Go ahead and call get_dev().
+			 */
+			return get_dev(devname, devid);
+		}
+		digit_pointer++;
+	}
+	return NULL;
+}
+
+int get_partition_by_name(block_dev_desc_t *dev, const char *partition_name,
+					disk_partition_t *partition_info)
+{
+	int i;
+	if (!dev)
+		return -ENODEV;
+	if (!partition_name || !partition_info)
+		return -EINVAL;
+	if (dev->part_type == PART_TYPE_UNKNOWN) {
+		init_part(dev); /* Maybe it is just uninitialized. */
+		if (dev->part_type == PART_TYPE_UNKNOWN)
+			return -ENOENT;
+	}
+	for (i = CONFIG_MIN_PARTITION_NUM; i <= CONFIG_MAX_PARTITION_NUM; i++) {
+		if (get_partition_info(dev, i, partition_info))
+			continue;
+		if (!strcmp((char *)partition_info->name, partition_name))
+			return 0;
+	}
+	return -ENOENT;
+}
+
+/*
+ * Note that the partition functions use environment variables for storing
+ * commands that need to be executed before and after the operations.
+ * Refer to doc/README.partition_funcs for information about this.
+ */
+
+/*
+ * Provide a helper function that will get the value of an environment
+ * variable and interpret the value as commands to be run.  This is used to
+ * allow users to have commands executed before and after partition
+ * operations.  The environment variable that will be used is based upon the
+ * three passed arguments.  Assuming that you want commands to be executed
+ * before and after writing to a partition named "bob", you could do something
+ * like:
+ *	setenv pre_write.bob echo before
+ *	setenv post_write.bob echo after
+ */
+enum when_t {BEFORE, AFTER};
+static int run_env(enum when_t when, const char *op_str, const uchar *ptn_name)
+{
+	char var_name[sizeof("post_write.")
+				+ sizeof(((disk_partition_t *)0)->name)
+				+ 8 /* Extra future-proofing insurance */];
+	char *var_val;
+	int len;
+
+	len = snprintf(var_name, sizeof(var_name), "%s_%s.%s",
+		       (when == BEFORE) ? "pre" : "post", op_str, ptn_name);
+	if (len >= sizeof(var_name))
+		return -EOVERFLOW;
+
+	var_val = getenv(var_name);
+	if (var_val && run_command(var_val, 0) < 0)
+		return -ENOEXEC;
+	return 0;
+}
+int partition_erase_pre(disk_partition_t *ptn)
+{
+	return run_env(BEFORE, "erase", ptn->name);
+}
+int partition_erase_post(disk_partition_t *ptn)
+{
+	return run_env(AFTER, "erase", ptn->name);
+}
+int partition_read_pre(disk_partition_t *ptn)
+{
+	return run_env(BEFORE, "read", ptn->name);
+}
+int partition_read_post(disk_partition_t *ptn)
+{
+	return run_env(AFTER, "read", ptn->name);
+}
+int partition_write_pre(disk_partition_t *ptn)
+{
+	return run_env(BEFORE, "write", ptn->name);
+}
+int partition_write_post(disk_partition_t *ptn)
+{
+	return run_env(AFTER, "write", ptn->name);
+}
+
+/* Simple helper for partition_* functions to validate arguments. */
+static int _partition_validate(block_dev_desc_t *dev, disk_partition_t *ptn,
+			loff_t *bytecnt, lbaint_t *blkcnt, const void *buffer)
+{
+	if (!dev)
+		return -ENODEV;
+	if (!ptn || !buffer || (blkcnt && bytecnt) /* One or the other */)
+		return -EINVAL;
+	if (blkcnt && *blkcnt > ptn->size)
+		return -EFBIG;
+	/*
+	 * Don't validate bytecnt yet because the pre_ commands
+	 * (e.g. nandoob enable) may change the block size.
+	 */
+	return 0;
+}
+
+static loff_t get_and_zero_loff_t(loff_t *p)
+{
+	loff_t n;
+	if (p) {
+		n = *p;
+		*p = 0;
+		return n;
+	}
+	return 0;
+}
+static lbaint_t get_and_zero_lbaint_t(lbaint_t *p)
+{
+	lbaint_t n;
+	if (p) {
+		n = *p;
+		*p = 0;
+		return n;
+	}
+	return 0;
+}
+/*
+ * Define the guts of the partition_ functions.  The _blks and _bytes
+ * permutations will call these to do the actual work.
+ */
+static int _partition_erase(block_dev_desc_t *dev, disk_partition_t *ptn,
+				loff_t *bytecnt_p, lbaint_t *blkcnt_p)
+{
+	/*
+	 * Fetch the number of bytes or blocks and then zero them right away
+	 * to make the error handling easier.
+	 */
+	loff_t bytes_to_do = get_and_zero_loff_t(bytecnt_p);
+	lbaint_t blks_to_do = get_and_zero_lbaint_t(blkcnt_p), blks_done;
+	int err = _partition_validate(dev, ptn, bytecnt_p, blkcnt_p,
+							(void *)-1/*fake*/);
+	if (err)
+		return err;
+
+	err = partition_erase_pre(ptn);
+	if (err)
+		return err;
+
+	if (bytes_to_do) {
+		blks_to_do = DIV_ROUND_UP(bytes_to_do, dev->blksz);
+		if (blks_to_do > ptn->size)
+			return -EFBIG;
+	} else if (!blks_to_do)
+		blks_to_do = ptn->size;
+
+	blks_done = dev->block_erase(dev->dev, ptn->start, blks_to_do);
+	if (blkcnt_p)
+		*blkcnt_p = blks_done;
+	if (bytecnt_p)
+		*bytecnt_p = (loff_t)blks_done * dev->blksz;
+
+	err = partition_erase_post(ptn);
+
+	if (blks_done != blks_to_do)
+		return -EIO;
+	return err;
+}
+int partition_erase_blks(block_dev_desc_t *dev, disk_partition_t *ptn,
+							lbaint_t *blkcnt)
+{
+	return _partition_erase(dev, ptn, NULL, blkcnt);
+}
+int partition_erase_bytes(block_dev_desc_t *dev, disk_partition_t *ptn,
+							loff_t *bytecnt)
+{
+	return _partition_erase(dev, ptn, bytecnt, NULL);
+}
+
+#ifdef CONFIG_MD5
+void partition_md5_helper(block_dev_desc_t *dev, lbaint_t blk_start,
+				lbaint_t *blkcnt, unsigned char md5[16])
+{
+	struct MD5Context context;
+	lbaint_t buf_blks, blks_left, blks_read;
+	unsigned char *buf;
+#ifndef CONF_MD5_BUFLEN
+#define CONF_MD5_BUFLEN (16*1024)
+#endif
+
+	buf_blks = CONF_MD5_BUFLEN / dev->blksz;
+	if (!buf_blks) {
+		*blkcnt = 0;
+		return;
+	}
+	buf = malloc(buf_blks * dev->blksz);
+	if (!buf) {
+		*blkcnt = 0;
+		return;
+	}
+
+	MD5Init(&context);
+	blks_left = *blkcnt;
+	while (blks_left) {
+		if (blks_left < buf_blks)
+			buf_blks = blks_left;
+
+		blks_read = dev->block_read(dev->dev, blk_start, buf_blks,
+									buf);
+		MD5Update(&context, buf, blks_read * dev->blksz);
+		blk_start += blks_read;
+		blks_left -= blks_read;
+		if (blks_read != buf_blks)
+			break;
+	}
+	MD5Final(md5, &context);
+
+	free(buf);
+	*blkcnt -= blks_left;
+}
+static int _partition_md5(block_dev_desc_t *dev, disk_partition_t *ptn,
+				loff_t *bytecnt_p, lbaint_t *blkcnt_p,
+				unsigned char md5[16])
+{
+	/*
+	 * Fetch the number of bytes or blocks and then zero them right away
+	 * to make the error handling easier.
+	 */
+	loff_t bytes_to_do = get_and_zero_loff_t(bytecnt_p);
+	lbaint_t blks_to_do = get_and_zero_lbaint_t(blkcnt_p), blks_done;
+	int err = _partition_validate(dev, ptn, bytecnt_p, blkcnt_p,
+							(void *)-1/*fake*/);
+	if (err)
+		return err;
+
+	err = partition_read_pre(ptn);
+	if (err)
+		return err;
+
+	if (bytes_to_do) {
+		blks_to_do = DIV_ROUND_UP(bytes_to_do, dev->blksz);
+		if (blks_to_do > ptn->size)
+			return -EFBIG;
+	} else if (!blks_to_do)
+		blks_to_do = ptn->size;
+
+	blks_done = blks_to_do;
+	partition_md5_helper(dev, ptn->start, &blks_done, md5);
+
+	if (blkcnt_p)
+		*blkcnt_p = blks_done;
+	if (bytecnt_p)
+		*bytecnt_p = (loff_t)blks_done * dev->blksz;
+
+	err = partition_read_post(ptn);
+
+	if (blks_done != blks_to_do)
+		return -EIO;
+	return err;
+}
+int partition_md5_blks(block_dev_desc_t *dev, disk_partition_t *ptn,
+				lbaint_t *blkcnt, unsigned char md5[16])
+{
+	return _partition_md5(dev, ptn, NULL, blkcnt, md5);
+}
+int partition_md5_bytes(block_dev_desc_t *dev, disk_partition_t *ptn,
+				loff_t *bytecnt, unsigned char md5[16])
+{
+	return _partition_md5(dev, ptn, bytecnt, NULL, md5);
+}
+#endif /* CONFIG_MD5 */
+
+static int _partition_read(block_dev_desc_t *dev, disk_partition_t *ptn,
+				loff_t *bytecnt_p, lbaint_t *blkcnt_p,
+				void *buffer)
+{
+	/*
+	 * Fetch the number of bytes or blocks and then zero them right away
+	 * to make the error handling easier.
+	 */
+	loff_t bytes_to_do = get_and_zero_loff_t(bytecnt_p);
+	lbaint_t blks_to_do = get_and_zero_lbaint_t(blkcnt_p), blks_done;
+	int err = _partition_validate(dev, ptn, bytecnt_p, blkcnt_p, buffer);
+	if (err)
+		return err;
+
+	err = partition_read_pre(ptn);
+	if (err)
+		return err;
+
+	if (bytes_to_do) {
+		blks_to_do = DIV_ROUND_UP(bytes_to_do, dev->blksz);
+		if (blks_to_do > ptn->size)
+			return -EFBIG;
+	} else if (!blks_to_do)
+		blks_to_do = ptn->size;
+
+	blks_done = dev->block_read(dev->dev, ptn->start, blks_to_do, buffer);
+	if (blkcnt_p)
+		*blkcnt_p = blks_done;
+	if (bytecnt_p)
+		*bytecnt_p = (loff_t)blks_done * dev->blksz;
+
+	err = partition_read_post(ptn);
+
+	if (blks_done != blks_to_do)
+		return -EIO;
+	return err;
+}
+int partition_read_blks(block_dev_desc_t *dev, disk_partition_t *ptn,
+					lbaint_t *blkcnt, void *buffer)
+{
+	return _partition_read(dev, ptn, NULL, blkcnt, buffer);
+}
+int partition_read_bytes(block_dev_desc_t *dev, disk_partition_t *ptn,
+					loff_t *bytecnt, void *buffer)
+{
+	return _partition_read(dev, ptn, bytecnt, NULL, buffer);
+}
+
+static int _partition_write(block_dev_desc_t *dev, disk_partition_t *ptn,
+				loff_t *bytecnt_p, lbaint_t *blkcnt_p,
+				const void *buffer)
+{
+#if defined(CONFIG_ERASE_PARTITION_ALWAYS)
+	int do_erase = 1;
+#else
+	int do_erase = 0;
+#endif
+	/*
+	 * Fetch the number of bytes or blocks and then zero them right away
+	 * to make the error handling easier.
+	 */
+	loff_t bytes_to_do = get_and_zero_loff_t(bytecnt_p);
+	lbaint_t blks_done,  blks_to_do = get_and_zero_lbaint_t(blkcnt_p);
+	int err = _partition_validate(dev, ptn, bytecnt_p, blkcnt_p, buffer);
+	if (err)
+		return err;
+
+	err = partition_write_pre(ptn);
+	if (!err) {
+		if (bytes_to_do) {
+			blks_to_do = DIV_ROUND_UP(bytes_to_do, dev->blksz);
+			if (blks_to_do > ptn->size)
+				err = -EFBIG;
+		} else if (!blks_to_do)
+			blks_to_do = ptn->size;
+	}
+	blks_done = blks_to_do;
+	if (!err) {
+		if (do_erase)
+			blks_done = dev->block_erase(dev->dev, ptn->start,
+								blks_to_do);
+		if (!do_erase || (blks_done == blks_to_do)) {
+			blks_done = dev->block_write(dev->dev, ptn->start,
+							blks_to_do, buffer);
+			if (blkcnt_p)
+				*blkcnt_p = blks_done;
+			if (bytecnt_p)
+				*bytecnt_p = (loff_t)blks_done * dev->blksz;
+		}
+
+		err = partition_write_post(ptn);
+	}
+
+	if (blks_done != blks_to_do)
+		return -EIO;
+	return err;
+}
+
+int partition_write_blks(block_dev_desc_t *dev, disk_partition_t *ptn,
+					lbaint_t *blkcnt, const void *buffer)
+{
+	return _partition_write(dev, ptn, NULL, blkcnt, buffer);
+}
+int partition_write_bytes(block_dev_desc_t *dev, disk_partition_t *ptn,
+					loff_t *bytecnt, const void *buffer)
+{
+	return _partition_write(dev, ptn, bytecnt, NULL, buffer);
+}
+
+#define SPARSE_HEADER_MAJOR_VER 1
+
+static int _unsparse(block_dev_desc_t *bdev, unsigned char *source,
+					lbaint_t sector, lbaint_t num_blks)
+{
+	sparse_header_t *header = (void *) source;
+	u32 i;
+	unsigned long blksz = bdev->blksz;
+	u64 section_size = (u64)num_blks * blksz;
+	u64 outlen = 0;
+	int blksz_shift;
+
+	blksz_shift = LOG2(blksz);
+	PRINTF("sparse_header:\n");
+	PRINTF("\t         magic=0x%08X\n", header->magic);
+	PRINTF("\t       version=%u.%u\n", header->major_version,
+						header->minor_version);
+	PRINTF("\t file_hdr_size=%u\n", header->file_hdr_sz);
+	PRINTF("\tchunk_hdr_size=%u\n", header->chunk_hdr_sz);
+	PRINTF("\t        blk_sz=%u\n", header->blk_sz);
+	PRINTF("\t    total_blks=%u\n", header->total_blks);
+	PRINTF("\t  total_chunks=%u\n", header->total_chunks);
+	PRINTF("\timage_checksum=%u\n", header->image_checksum);
+	PRINTF("\tblock device shift=%d\n", blksz_shift);
+
+	if (header->magic != SPARSE_HEADER_MAGIC) {
+		printf("sparse: bad magic\n");
+		return 1;
+	}
+
+	if (((u64)header->total_blks * header->blk_sz) > section_size) {
+		printf("sparse: section size %llu MB limit: exceeded\n",
+				section_size/(1024*1024));
+		return 1;
+	}
+
+	if ((header->major_version != SPARSE_HEADER_MAJOR_VER) ||
+	    (header->file_hdr_sz != sizeof(sparse_header_t)) ||
+	    (header->chunk_hdr_sz != sizeof(chunk_header_t))) {
+		printf("sparse: incompatible format\n");
+		return 1;
+	}
+
+	/* Skip the header now */
+	source += header->file_hdr_sz;
+
+	for (i = 0; i < header->total_chunks; i++) {
+		u64 clen = 0;
+		lbaint_t blkcnt;
+		chunk_header_t *chunk = (void *) source;
+
+		PRINTF("chunk_header:\n");
+		PRINTF("\t    chunk_type=%u\n", chunk->chunk_type);
+		PRINTF("\t      chunk_sz=%u\n", chunk->chunk_sz);
+		PRINTF("\t      total_sz=%u\n", chunk->total_sz);
+		/* move to next chunk */
+		source += sizeof(chunk_header_t);
+
+		switch (chunk->chunk_type) {
+		case CHUNK_TYPE_RAW:
+			clen = (u64)chunk->chunk_sz * header->blk_sz;
+			PRINTF("sparse: RAW blk=%d bsz=%d:"
+			       " write(sector=%lu,clen=%llu)\n",
+			       chunk->chunk_sz, header->blk_sz, sector, clen);
+
+			if (chunk->total_sz != (clen + sizeof(chunk_header_t))) {
+				printf("sparse: bad chunk size for"
+				       " chunk %d, type Raw\n", i);
+				return 1;
+			}
+
+			outlen += clen;
+			if (outlen > section_size) {
+				printf("sparse: section size %llu MB limit:"
+				       " exceeded\n", section_size/(1024*1024));
+				return 1;
+			}
+			blkcnt = clen >> blksz_shift;
+			debug("sparse: RAW blk=%d bsz=%d:"
+			       " write(sector=%lu,clen=%llu)\n",
+			       chunk->chunk_sz, header->blk_sz, sector, clen);
+			if (bdev->block_write(bdev->dev,
+						       sector, blkcnt, source)
+						!= blkcnt) {
+				printf("sparse: block write to sector %lu"
+					" of %llu bytes (%ld blkcnt) failed\n",
+					sector, clen, blkcnt);
+				return 1;
+			}
+
+			sector += (clen >> blksz_shift);
+			source += clen;
+			break;
+
+		case CHUNK_TYPE_DONT_CARE:
+			if (chunk->total_sz != sizeof(chunk_header_t)) {
+				printf("sparse: bogus DONT CARE chunk\n");
+				return 1;
+			}
+			clen = (u64)chunk->chunk_sz * header->blk_sz;
+			debug("sparse: DONT_CARE blk=%d bsz=%d:"
+			       " skip(sector=%lu,clen=%llu)\n",
+			       chunk->chunk_sz, header->blk_sz, sector, clen);
+
+			outlen += clen;
+			if (outlen > section_size) {
+				printf("sparse: section size %llu MB limit:"
+				       " exceeded\n", section_size/(1024*1024));
+				return 1;
+			}
+			sector += (clen >> blksz_shift);
+			break;
+
+		default:
+			printf("sparse: unknown chunk ID %04x\n",
+			       chunk->chunk_type);
+			return 1;
+		}
+	}
+
+	printf("sparse: out-length %llu MB\n", outlen/(1024*1024));
+	return 0;
+}
+/*
+  unsparse an image with sparse header
+*/
+
+int partition_unsparse(block_dev_desc_t *dev, disk_partition_t *ptn,
+		unsigned char *source, lbaint_t sector, lbaint_t num_blks)
+{
+	int rtn;
+	if (partition_write_pre(ptn))
+		return 1;
+
+	rtn = _unsparse(dev, source, sector, num_blks);
+
+	if (partition_write_post(ptn))
+		return 1;
+
+	return rtn;
+}
+
+
 #else
 block_dev_desc_t *get_dev(char* ifname, int dev)
 {
 	return NULL;
 }
+block_dev_desc_t *get_dev_by_name(char *devname)
+{
+	return NULL;
+}
+int get_partition_by_name(block_dev_desc_t *dev, const char *partition_name,
+					disk_partition_t *partition_info)
+{
+	return -ENODEV;
+}
+int partition_erase_pre(disk_partition_t *ptn)
+{
+	return -ENODEV;
+}
+int partition_erase_post(disk_partition_t *ptn)
+{
+	return -ENODEV;
+}
+int partition_read_pre(disk_partition_t *ptn)
+{
+	return -ENODEV;
+}
+int partition_read_post(disk_partition_t *ptn)
+{
+	return -ENODEV;
+}
+int partition_write_pre(disk_partition_t *ptn)
+{
+	return -ENODEV;
+}
+int partition_write_post(disk_partition_t *ptn)
+{
+	return -ENODEV;
+}
+int partition_erase_blks(block_dev_desc_t *dev, disk_partition_t *ptn,
+							lbaint_t *blkcnt)
+{
+	return -ENODEV;
+}
+int partition_erase_bytes(block_dev_desc_t *dev, disk_partition_t *partition,
+							loff_t *bytecnt)
+{
+	return -ENODEV;
+}
+#ifdef CONFIG_MD5
+int partition_md5_blks(block_dev_desc_t *dev, disk_partition_t *ptn,
+							lbaint_t *blkcnt)
+{
+	return -ENODEV;
+}
+int partition_md5_bytes(block_dev_desc_t *dev, disk_partition_t *partition,
+							loff_t *bytecnt)
+{
+	return -ENODEV;
+}
+#endif /* CONFIG_MD5 */
+int partition_read_blks(block_dev_desc_t *dev, disk_partition_t *ptn,
+					lbaint_t *blkcnt, void *buffer)
+{
+	return -ENODEV;
+}
+int partition_read_bytes(block_dev_desc_t *dev, disk_partition_t *partition,
+					loff_t *bytecnt, void *buffer)
+{
+	return -ENODEV;
+}
+int partition_write_blks(block_dev_desc_t *dev, disk_partition_t *ptn,
+					lbaint_t *blkcnt, const void *buffer)
+{
+	return -ENODEV;
+}
+int partition_write_bytes(block_dev_desc_t *dev, disk_partition_t *partition,
+					loff_t *bytecnt, const void *buffer)
+{
+	return -ENODEV;
+}
 #endif
 
 #if (defined(CONFIG_CMD_IDE) || \
@@ -300,6 +933,9 @@ void init_part (block_dev_desc_t * dev_desc)
 int get_partition_info (block_dev_desc_t *dev_desc, int part
 					, disk_partition_t *info)
 {
+	if (dev_desc->part_type == PART_TYPE_UNKNOWN)
+		init_part(dev_desc); /* Maybe it is just uninitialized. */
+
 	switch (dev_desc->part_type) {
 #ifdef CONFIG_MAC_PARTITION
 	case PART_TYPE_MAC:
@@ -387,6 +1023,8 @@ static void print_part_header (const char *type, block_dev_desc_t * dev_desc)
 
 void print_part (block_dev_desc_t * dev_desc)
 {
+	if (dev_desc->part_type == PART_TYPE_UNKNOWN)
+		init_part(dev_desc); /* Maybe it is just uninitialized. */
 
 		switch (dev_desc->part_type) {
 #ifdef CONFIG_MAC_PARTITION
diff --git a/disk/part_dos.c b/disk/part_dos.c
index b5bcb3735c..c028aaf1b1 100644
--- a/disk/part_dos.c
+++ b/disk/part_dos.c
@@ -87,7 +87,7 @@ static int test_block_type(unsigned char *buffer)
 
 int test_part_dos (block_dev_desc_t *dev_desc)
 {
-	unsigned char buffer[dev_desc->blksz];
+	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
 
 	if ((dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *) buffer) != 1) ||
 	    (buffer[DOS_PART_MAGIC_OFFSET + 0] != 0x55) ||
@@ -102,7 +102,7 @@ int test_part_dos (block_dev_desc_t *dev_desc)
 static void print_partition_extended (block_dev_desc_t *dev_desc, int ext_part_sector, int relative,
 							   int part_num)
 {
-	unsigned char buffer[dev_desc->blksz];
+	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
 	dos_partition_t *pt;
 	int i;
 
@@ -166,7 +166,7 @@ static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part
 				 int relative, int part_num,
 				 int which_part, disk_partition_t *info)
 {
-	unsigned char buffer[dev_desc->blksz];
+	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
 	dos_partition_t *pt;
 	int i;
 
diff --git a/doc/README.ag102 b/doc/README.ag102
new file mode 100644
index 0000000000..7d142a70d1
--- /dev/null
+++ b/doc/README.ag102
@@ -0,0 +1,36 @@
+Andes Technology SoC AG102
+==========================
+
+AG102 is the second SoC produced by Andes Technology using N1213 CPU core
+with FPU and DDR contoller support.
+AG102 has integrated both AHB and APB bus and many periphals for application
+and product development.
+
+ADP-AG102
+=========
+
+ADP-AG102 is the SoC with AG102 hardcore CPU.
+
+Configurations
+==============
+
+CONFIG_MEM_REMAP:
+	Doing memory remap is essential for preparing some non-OS or RTOS
+	applications.
+
+CONFIG_SKIP_LOWLEVEL_INIT:
+	If you want to boot this system from SPI ROM and bypass e-bios (the
+	other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
+	in "include/configs/adp-ag102.h".
+
+Build and boot steps
+====================
+
+build:
+1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
+2. Use `make adp-ag102` in u-boot root to build the image.
+
+Burn u-boot to SPI ROM:
+====================
+
+This section will be added later.
diff --git a/doc/README.link-local b/doc/README.link-local
new file mode 100644
index 0000000000..e623e5659f
--- /dev/null
+++ b/doc/README.link-local
@@ -0,0 +1,76 @@
+------------------------------------------
+ Link-local IP address auto-configuration
+------------------------------------------
+
+Negotiate with other link-local clients on the local network
+for an address that doesn't require explicit configuration.
+This is especially useful if a DHCP server cannot be guaranteed
+to exist in all environments that the device must operate.
+
+This is an implementation of RFC3927.
+
+----------
+ Commands
+----------
+
+When CONFIG_CMD_LINK_LOCAL is defined in the board config file,
+the "linklocal" command is available.  This running this will
+take approximately 5 seconds while the address is negotiated.
+
+------------------------
+ Environment interation
+------------------------
+
+The "llipaddr" variable is set with the most recently
+negotiated address and is preferred in future negotiations.
+
+The "ipaddr", "netmask", and "gatewayip" variables are set
+after successful negotiation to enable network access.
+
+-------------
+ Limitations
+-------------
+
+RFC3927 requires that addresses are continuously checked to
+avoid conflicts, however this can only happen when the NetLoop
+is getting called.  It is possible for a conflict to go undetected
+until a command that accesses the network is executed.
+
+Using NetConsole is one way to ensure that NetLoop is always
+processing packets and monitoring for conflicts.
+
+This is also not a concern if the feature is use to connect
+directly to another machine that may not be running a DHCP server.
+
+----------------
+ Example script
+----------------
+
+This script allows use of DHCP and/or Link-local controlled
+by env variables.  It depends on CONFIG_CMD_LINK_LOCAL, CONFIG_CMD_DHCP,
+and CONFIG_BOOTP_MAY_FAIL.
+If both fail or are disabled, static settings are used.
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"ipconfigcmd=if test \\\"$dhcpenabled\\\" -ne 0;"		\
+		"then "							\
+			"dhcpfail=0;dhcp || dhcpfail=1;"		\
+		"else "							\
+			"dhcpfail=-1;"					\
+		"fi;"							\
+		"if test \\\"$linklocalenabled\\\" -ne 0 -a "		\
+			"\\\"$dhcpfail\\\" -ne 0;"			\
+		"then "							\
+			"linklocal;"					\
+			"llfail=0;"					\
+		"else "							\
+			"llfail=-1;"					\
+		"fi;"							\
+		"if test \\\"$llfail\\\" -ne 0 -a "			\
+			"\\\"$dhcpfail\\\" -ne 0; "			\
+		"then "							\
+			"setenv ipaddr $sipaddr; "			\
+			"setenv netmask $snetmask; "			\
+			"setenv gatewayip $sgatewayip; "		\
+		"fi;\0"							\
+
diff --git a/doc/README.nand b/doc/README.nand
index 04a87c9918..1602b5eee9 100644
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -94,14 +94,14 @@ Commands:
       of data for one 512-byte page or 2 256-byte pages. There is no check
       for bad blocks.
 
-   nand read.raw addr ofs|partition
-      Read page from `ofs' in NAND flash to `addr'. This reads the raw page,
-      so ECC is avoided and the OOB area is read as well.
-
-   nand write.raw addr ofs|partition
-      Write page from `addr' to `ofs' in NAND flash. This writes the raw page,
-      so ECC is avoided and the OOB area is written as well, making the whole
-      page written as-is.
+   nand read.raw addr ofs|partition [count]
+   nand write.raw addr ofs|partition [count]
+      Read or write one or more pages at "ofs" in NAND flash, from or to
+      "addr" in memory.  This is a raw access, so ECC is avoided and the
+      OOB area is transferred as well.  If count is absent, it is assumed
+      to be one page.  As with .yaffs2 accesses, the data is formatted as
+      a packed sequence of "data, oob, data, oob, ..." -- no alignment of
+      individual pages is maintained.
 
 Configuration Options:
 
diff --git a/doc/README.srio-boot-corenet b/doc/README.srio-boot-corenet
new file mode 100644
index 0000000000..56b094c9a2
--- /dev/null
+++ b/doc/README.srio-boot-corenet
@@ -0,0 +1,103 @@
+------------------------------
+SRIO Boot on Corenet Platforms
+------------------------------
+
+For some PowerPC processors with SRIO interface, boot location can be configured
+to SRIO by RCW. The processor booting from SRIO can do without flash for u-boot
+image, ucode and ENV. All the images can be fetched from another processor's
+memory space by SRIO link connected between them.
+
+This document describes the processes based on an example implemented on P4080DS
+platforms and a RCW example with boot from SRIO configuration.
+
+Environment of the SRIO boot:
+	a) Master and slave can be SOCs in one board or SOCs in separate boards.
+	b) They are connected with SRIO links, whether 1x or 4x, and directly or
+	   through switch system.
+	c) Only Master has NorFlash for booting, and all the Master's and Slave's
+	   U-Boot images, UCodes will be stored in this flash.
+	d) Slave has its own EEPROM for RCW and PBI.
+	e) Slave's RCW should configure the SerDes for SRIO boot port, set the boot
+	   location to SRIO, and holdoff all the cores if needed.
+
+	----------        -----------             -----------
+	|		  |       |         |             |         |
+	|		  |       |         |             |         |
+	| NorFlash|<----->| Master  |    SRIO     |  Slave  |<---->[EEPROM]
+	|		  |       |         |<===========>|         |
+	|		  |       |         |             |         |
+	----------        -----------             -----------
+
+The example based on P4080DS platform:
+	Two P4080DS platforms can be used to implement the boot from SRIO. Their SRIO
+	ports 0 will be connected directly and will be used for the boot from SRIO.
+
+	1. Slave's RCW example for boot from SRIO port 0 and core 0 not in holdoff.
+		00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000
+		00000010: 1818 1818 0000 8888 7440 4000 0000 2000
+		00000020: f400 0000 0100 0000 0000 0000 0000 0000
+		00000030: 0000 0000 0083 0000 0000 0000 0000 0000
+		00000040: 0000 0000 0000 0000 0813 8040 698b 93fe
+
+	2. Slave's RCW example for boot from SRIO port 0 and all cores in holdoff.
+		00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000
+		00000010: 1818 1818 0000 8888 7440 4000 0000 2000
+		00000020: f440 0000 0100 0000 0000 0000 0000 0000
+		00000030: 0000 0000 0083 0000 0000 0000 0000 0000
+		00000040: 0000 0000 0000 0000 0813 8040 063c 778f
+
+	3. Sequence in Step by Step.
+		a) Update RCW for slave with boot from SRIO port 0 configuration.
+		b) Program slave's U-Boot image, UCode, and ENV parameters into master's
+		   NorFlash.
+		c) Start up master and it will boot up normally from its NorFlash.
+		   Then, it will finish necessary configurations for slave's boot from
+		   SRIO port 0.
+		d) Master will set inbound SRIO windows covered slave's U-Boot image stored
+		   in master's NorFlash.
+		e) Master will set an inbound SRIO window covered slave's UCode stored in
+		   master's NorFlash.
+		f) Master will set an inbound SRIO window covered slave's ENV stored in
+		   master's NorFlash.
+		g) If need to release slave's core, master will set outbound SRIO windows
+		   in order to configure slave's registers for the core's releasing.
+		h) If all cores of slave in holdoff, slave should be powered on before all
+		   the above master's steps, and wait to be released by master. If not all
+		   cores in holdoff, that means core 0 will start up normally, slave should
+		   be powered on after all the above master's steps. In the startup phase
+		   of the slave from SRIO, it will finish some necessary configurations.
+		i) Slave will set a specific TLB entry for the boot process.
+		j) Slave will set a LAW entry with the TargetID SRIO port 0 for the boot.
+		k) Slave will set a specific TLB entry in order to fetch UCode and ENV
+		   from master.
+		l) Slave will set a LAW entry with the TargetID SRIO port 0 for UCode and ENV.
+
+How to use this feature:
+	To use this feature, you need to focus three points.
+
+	1. Slave's RCW with SRIO boot configurations, and all cores in holdoff
+	   configurations if needed.
+	   Please refer to the examples given above.
+
+	2. U-Boot image's compilation.
+		For master, U-Boot image should be generated specifically by
+
+				make xxxx_SRIOBOOT_MASTER_config.
+
+		For example, master U-Boot image used on P4080DS should be compiled with
+
+				make P4080DS_SRIOBOOT_MASTER_config.
+
+		For slave, U-Boot image should be generated specifically by
+
+				make xxxx_SRIOBOOT_SLAVE_config.
+
+		For example, slave U-Boot image used on P4080DS should be compiled with
+
+				make P4080DS_SRIOBOOT_SLAVE_config.
+
+	3. Necessary modifications based on a specific environment.
+		For a specific environment, the SRIO port for boot, the addresses of the
+		slave's U-Boot image, UCode, ENV stored in master's NorFlash, and any other
+		configurations can be modified in the file:
+					include/configs/corenet_ds.h.
diff --git a/doc/SPL/README.omap3 b/doc/SPL/README.omap3
index cc5d5c09ad..a543e65d39 100644
--- a/doc/SPL/README.omap3
+++ b/doc/SPL/README.omap3
@@ -34,14 +34,14 @@ DDR1: 0x80000000 - 0xBFFFFFFF
 
 Option 1 (SPL only):
 0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata
-0x4020BC00 - 0x4020FFFC: Area for the SPL stack.
+0x4020E000 - 0x4020FFFC: Area for the SPL stack.
 0x80000000 - 0x8007FFFF: Area for the SPL BSS.
 0x80100000: CONFIG_SYS_TEXT_BASE of U-Boot
 0x80208000 - 0x80307FFF: malloc() pool available to SPL.
 
 Option 2 (SPL or X-Loader):
 0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata
-0x4020BC00 - 0x4020FFFC: Area for the SPL stack.
+0x4020E000 - 0x4020FFFC: Area for the SPL stack.
 0x80008000: CONFIG_SYS_TEXT_BASE of U-Boot
 0x87000000 - 0x8707FFFF: Area for the SPL BSS.
 0x87080000 - 0x870FFFFF: malloc() pool available to SPL.
diff --git a/drivers/bios_emulator/x86emu/prim_ops.c b/drivers/bios_emulator/x86emu/prim_ops.c
index 7553087b26..5f6c795fb7 100644
--- a/drivers/bios_emulator/x86emu/prim_ops.c
+++ b/drivers/bios_emulator/x86emu/prim_ops.c
@@ -118,11 +118,6 @@ static u32 x86emu_parity_tab[8] =
 
 #define PARITY(x)   (((x86emu_parity_tab[(x) / 32] >> ((x) % 32)) & 1) == 0)
 #define XOR2(x)	    (((x) ^ ((x)>>1)) & 0x1)
-/*----------------------------- Implementation ----------------------------*/
-int abs(int v)
-{
-	return (v>0)?v:-v;
-}
 
 /*----------------------------- Implementation ----------------------------*/
 
diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index 98560ef76f..b9c20475c2 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -27,6 +27,7 @@ LIB	:= $(obj)libblock.o
 
 COBJS-$(CONFIG_SCSI_AHCI) += ahci.o
 COBJS-$(CONFIG_ATA_PIIX) += ata_piix.o
+COBJS-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
 COBJS-$(CONFIG_FSL_SATA) += fsl_sata.o
 COBJS-$(CONFIG_IDE_FTIDE020) += ftide020.o
 COBJS-$(CONFIG_LIBATA) += libata.o
diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
new file mode 100644
index 0000000000..2703d3dc84
--- /dev/null
+++ b/drivers/block/dwc_ahsata.c
@@ -0,0 +1,969 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Terry Lv <r65388@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ *
+ */
+
+#include <libata.h>
+#include <ahci.h>
+#include <fis.h>
+
+#include <common.h>
+#include <malloc.h>
+#include <linux/ctype.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <asm/arch/clock.h>
+#include "dwc_ahsata.h"
+
+struct sata_port_regs {
+	u32 clb;
+	u32 clbu;
+	u32 fb;
+	u32 fbu;
+	u32 is;
+	u32 ie;
+	u32 cmd;
+	u32 res1[1];
+	u32 tfd;
+	u32 sig;
+	u32 ssts;
+	u32 sctl;
+	u32 serr;
+	u32 sact;
+	u32 ci;
+	u32 sntf;
+	u32 res2[1];
+	u32 dmacr;
+	u32 res3[1];
+	u32 phycr;
+	u32 physr;
+};
+
+struct sata_host_regs {
+	u32 cap;
+	u32 ghc;
+	u32 is;
+	u32 pi;
+	u32 vs;
+	u32 ccc_ctl;
+	u32 ccc_ports;
+	u32 res1[2];
+	u32 cap2;
+	u32 res2[30];
+	u32 bistafr;
+	u32 bistcr;
+	u32 bistfctr;
+	u32 bistsr;
+	u32 bistdecr;
+	u32 res3[2];
+	u32 oobr;
+	u32 res4[8];
+	u32 timer1ms;
+	u32 res5[1];
+	u32 gparam1r;
+	u32 gparam2r;
+	u32 pparamr;
+	u32 testr;
+	u32 versionr;
+	u32 idr;
+};
+
+#define MAX_DATA_BYTES_PER_SG  (4 * 1024 * 1024)
+#define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
+
+#define writel_with_flush(a, b)	do { writel(a, b); readl(b); } while (0)
+
+static int is_ready;
+
+static inline u32 ahci_port_base(u32 base, u32 port)
+{
+	return base + 0x100 + (port * 0x80);
+}
+
+static int waiting_for_cmd_completed(u8 *offset,
+					int timeout_msec,
+					u32 sign)
+{
+	int i;
+	u32 status;
+
+	for (i = 0;
+		((status = readl(offset)) & sign) && i < timeout_msec;
+		++i)
+		mdelay(1);
+
+	return (i < timeout_msec) ? 0 : -1;
+}
+
+static int ahci_setup_oobr(struct ahci_probe_ent *probe_ent,
+						int clk)
+{
+	struct sata_host_regs *host_mmio =
+		(struct sata_host_regs *)probe_ent->mmio_base;
+
+	writel(SATA_HOST_OOBR_WE, &(host_mmio->oobr));
+	writel(0x02060b14, &(host_mmio->oobr));
+
+	return 0;
+}
+
+static int ahci_host_init(struct ahci_probe_ent *probe_ent)
+{
+	u32 tmp, cap_save, num_ports;
+	int i, j, timeout = 1000;
+	struct sata_port_regs *port_mmio = NULL;
+	struct sata_host_regs *host_mmio =
+		(struct sata_host_regs *)probe_ent->mmio_base;
+	int clk = mxc_get_clock(MXC_SATA_CLK);
+
+	cap_save = readl(&(host_mmio->cap));
+	cap_save |= SATA_HOST_CAP_SSS;
+
+	/* global controller reset */
+	tmp = readl(&(host_mmio->ghc));
+	if ((tmp & SATA_HOST_GHC_HR) == 0)
+		writel_with_flush(tmp | SATA_HOST_GHC_HR, &(host_mmio->ghc));
+
+	while ((readl(&(host_mmio->ghc)) & SATA_HOST_GHC_HR)
+		&& --timeout)
+		;
+
+	if (timeout <= 0) {
+		debug("controller reset failed (0x%x)\n", tmp);
+		return -1;
+	}
+
+	/* Set timer 1ms */
+	writel(clk / 1000, &(host_mmio->timer1ms));
+
+	ahci_setup_oobr(probe_ent, 0);
+
+	writel_with_flush(SATA_HOST_GHC_AE, &(host_mmio->ghc));
+	writel(cap_save, &(host_mmio->cap));
+	num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1;
+	writel_with_flush((1 << num_ports) - 1,
+				&(host_mmio->pi));
+
+	/*
+	 * Determine which Ports are implemented by the DWC_ahsata,
+	 * by reading the PI register. This bit map value aids the
+	 * software to determine how many Ports are available and
+	 * which Port registers need to be initialized.
+	 */
+	probe_ent->cap = readl(&(host_mmio->cap));
+	probe_ent->port_map = readl(&(host_mmio->pi));
+
+	/* Determine how many command slots the HBA supports */
+	probe_ent->n_ports =
+		(probe_ent->cap & SATA_HOST_CAP_NP_MASK) + 1;
+
+	debug("cap 0x%x  port_map 0x%x  n_ports %d\n",
+		probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
+
+	for (i = 0; i < probe_ent->n_ports; i++) {
+		probe_ent->port[i].port_mmio =
+			ahci_port_base((u32)host_mmio, i);
+		port_mmio =
+			(struct sata_port_regs *)probe_ent->port[i].port_mmio;
+
+		/* Ensure that the DWC_ahsata is in idle state */
+		tmp = readl(&(port_mmio->cmd));
+
+		/*
+		 * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
+		 * are all cleared, the Port is in an idle state.
+		 */
+		if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR |
+			SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) {
+
+			/*
+			 * System software places a Port into the idle state by
+			 * clearing P#CMD.ST and waiting for P#CMD.CR to return
+			 * 0 when read.
+			 */
+			tmp &= ~SATA_PORT_CMD_ST;
+			writel_with_flush(tmp, &(port_mmio->cmd));
+
+			/*
+			 * spec says 500 msecs for each bit, so
+			 * this is slightly incorrect.
+			 */
+			mdelay(500);
+
+			timeout = 1000;
+			while ((readl(&(port_mmio->cmd)) & SATA_PORT_CMD_CR)
+				&& --timeout)
+				;
+
+			if (timeout <= 0) {
+				debug("port reset failed (0x%x)\n", tmp);
+				return -1;
+			}
+		}
+
+		/* Spin-up device */
+		tmp = readl(&(port_mmio->cmd));
+		writel((tmp | SATA_PORT_CMD_SUD), &(port_mmio->cmd));
+
+		/* Wait for spin-up to finish */
+		timeout = 1000;
+		while (!(readl(&(port_mmio->cmd)) | SATA_PORT_CMD_SUD)
+			&& --timeout)
+			;
+		if (timeout <= 0) {
+			debug("Spin-Up can't finish!\n");
+			return -1;
+		}
+
+		for (j = 0; j < 100; ++j) {
+			mdelay(10);
+			tmp = readl(&(port_mmio->ssts));
+			if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) ||
+				((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1))
+				break;
+		}
+
+		/* Wait for COMINIT bit 26 (DIAG_X) in SERR */
+		timeout = 1000;
+		while (!(readl(&(port_mmio->serr)) | SATA_PORT_SERR_DIAG_X)
+			&& --timeout)
+			;
+		if (timeout <= 0) {
+			debug("Can't find DIAG_X set!\n");
+			return -1;
+		}
+
+		/*
+		 * For each implemented Port, clear the P#SERR
+		 * register, by writing ones to each implemented\
+		 * bit location.
+		 */
+		tmp = readl(&(port_mmio->serr));
+		debug("P#SERR 0x%x\n",
+				tmp);
+		writel(tmp, &(port_mmio->serr));
+
+		/* Ack any pending irq events for this port */
+		tmp = readl(&(host_mmio->is));
+		debug("IS 0x%x\n", tmp);
+		if (tmp)
+			writel(tmp, &(host_mmio->is));
+
+		writel(1 << i, &(host_mmio->is));
+
+		/* set irq mask (enables interrupts) */
+		writel(DEF_PORT_IRQ, &(port_mmio->ie));
+
+		/* register linkup ports */
+		tmp = readl(&(port_mmio->ssts));
+		debug("Port %d status: 0x%x\n", i, tmp);
+		if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03)
+			probe_ent->link_port_map |= (0x01 << i);
+	}
+
+	tmp = readl(&(host_mmio->ghc));
+	debug("GHC 0x%x\n", tmp);
+	writel(tmp | SATA_HOST_GHC_IE, &(host_mmio->ghc));
+	tmp = readl(&(host_mmio->ghc));
+	debug("GHC 0x%x\n", tmp);
+
+	return 0;
+}
+
+static void ahci_print_info(struct ahci_probe_ent *probe_ent)
+{
+	struct sata_host_regs *host_mmio =
+		(struct sata_host_regs *)probe_ent->mmio_base;
+	u32 vers, cap, impl, speed;
+	const char *speed_s;
+	const char *scc_s;
+
+	vers = readl(&(host_mmio->vs));
+	cap = probe_ent->cap;
+	impl = probe_ent->port_map;
+
+	speed = (cap & SATA_HOST_CAP_ISS_MASK)
+		>> SATA_HOST_CAP_ISS_OFFSET;
+	if (speed == 1)
+		speed_s = "1.5";
+	else if (speed == 2)
+		speed_s = "3";
+	else
+		speed_s = "?";
+
+	scc_s = "SATA";
+
+	printf("AHCI %02x%02x.%02x%02x "
+		"%u slots %u ports %s Gbps 0x%x impl %s mode\n",
+		(vers >> 24) & 0xff,
+		(vers >> 16) & 0xff,
+		(vers >> 8) & 0xff,
+		vers & 0xff,
+		((cap >> 8) & 0x1f) + 1,
+		(cap & 0x1f) + 1,
+		speed_s,
+		impl,
+		scc_s);
+
+	printf("flags: "
+		"%s%s%s%s%s%s"
+		"%s%s%s%s%s%s%s\n",
+		cap & (1 << 31) ? "64bit " : "",
+		cap & (1 << 30) ? "ncq " : "",
+		cap & (1 << 28) ? "ilck " : "",
+		cap & (1 << 27) ? "stag " : "",
+		cap & (1 << 26) ? "pm " : "",
+		cap & (1 << 25) ? "led " : "",
+		cap & (1 << 24) ? "clo " : "",
+		cap & (1 << 19) ? "nz " : "",
+		cap & (1 << 18) ? "only " : "",
+		cap & (1 << 17) ? "pmp " : "",
+		cap & (1 << 15) ? "pio " : "",
+		cap & (1 << 14) ? "slum " : "",
+		cap & (1 << 13) ? "part " : "");
+}
+
+static int ahci_init_one(int pdev)
+{
+	int rc;
+	struct ahci_probe_ent *probe_ent = NULL;
+
+	probe_ent = malloc(sizeof(struct ahci_probe_ent));
+	memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
+	probe_ent->dev = pdev;
+
+	probe_ent->host_flags = ATA_FLAG_SATA
+				| ATA_FLAG_NO_LEGACY
+				| ATA_FLAG_MMIO
+				| ATA_FLAG_PIO_DMA
+				| ATA_FLAG_NO_ATAPI;
+
+	probe_ent->mmio_base = CONFIG_DWC_AHSATA_BASE_ADDR;
+
+	/* initialize adapter */
+	rc = ahci_host_init(probe_ent);
+	if (rc)
+		goto err_out;
+
+	ahci_print_info(probe_ent);
+
+	/* Save the private struct to block device struct */
+	sata_dev_desc[pdev].priv = (void *)probe_ent;
+
+	return 0;
+
+err_out:
+	return rc;
+}
+
+static int ahci_fill_sg(struct ahci_probe_ent *probe_ent,
+			u8 port, unsigned char *buf, int buf_len)
+{
+	struct ahci_ioports *pp = &(probe_ent->port[port]);
+	struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
+	u32 sg_count, max_bytes;
+	int i;
+
+	max_bytes = MAX_DATA_BYTES_PER_SG;
+	sg_count = ((buf_len - 1) / max_bytes) + 1;
+	if (sg_count > AHCI_MAX_SG) {
+		printf("Error:Too much sg!\n");
+		return -1;
+	}
+
+	for (i = 0; i < sg_count; i++) {
+		ahci_sg->addr =
+			cpu_to_le32((u32)buf + i * max_bytes);
+		ahci_sg->addr_hi = 0;
+		ahci_sg->flags_size = cpu_to_le32(0x3fffff &
+					(buf_len < max_bytes
+					? (buf_len - 1)
+					: (max_bytes - 1)));
+		ahci_sg++;
+		buf_len -= max_bytes;
+	}
+
+	return sg_count;
+}
+
+static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
+{
+	struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
+					AHCI_CMD_SLOT_SZ * cmd_slot);
+
+	memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
+	cmd_hdr->opts = cpu_to_le32(opts);
+	cmd_hdr->status = 0;
+	cmd_hdr->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
+	cmd_hdr->tbl_addr_hi = 0;
+}
+
+#define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
+
+static int ahci_exec_ata_cmd(struct ahci_probe_ent *probe_ent,
+		u8 port, struct sata_fis_h2d *cfis,
+		u8 *buf, u32 buf_len, s32 is_write)
+{
+	struct ahci_ioports *pp = &(probe_ent->port[port]);
+	struct sata_port_regs *port_mmio =
+			(struct sata_port_regs *)pp->port_mmio;
+	u32 opts;
+	int sg_count = 0, cmd_slot = 0;
+
+	cmd_slot = AHCI_GET_CMD_SLOT(readl(&(port_mmio->ci)));
+	if (32 == cmd_slot) {
+		printf("Can't find empty command slot!\n");
+		return 0;
+	}
+
+	/* Check xfer length */
+	if (buf_len > MAX_BYTES_PER_TRANS) {
+		printf("Max transfer length is %dB\n\r",
+			MAX_BYTES_PER_TRANS);
+		return 0;
+	}
+
+	memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d));
+	if (buf && buf_len)
+		sg_count = ahci_fill_sg(probe_ent, port, buf, buf_len);
+	opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
+	if (is_write)
+		opts |= 0x40;
+	ahci_fill_cmd_slot(pp, cmd_slot, opts);
+
+	writel_with_flush(1 << cmd_slot, &(port_mmio->ci));
+
+	if (waiting_for_cmd_completed((u8 *)&(port_mmio->ci),
+				10000, 0x1 << cmd_slot)) {
+		printf("timeout exit!\n");
+		return -1;
+	}
+	debug("ahci_exec_ata_cmd: %d byte transferred.\n",
+	      pp->cmd_slot->status);
+
+	return buf_len;
+}
+
+static void ahci_set_feature(u8 dev, u8 port)
+{
+	struct ahci_probe_ent *probe_ent =
+		(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+	struct sata_fis_h2d h2d, *cfis = &h2d;
+
+	memset(cfis, 0, sizeof(struct sata_fis_h2d));
+	cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+	cfis->pm_port_c = 1 << 7;
+	cfis->command = ATA_CMD_SET_FEATURES;
+	cfis->features = SETFEATURES_XFER;
+	cfis->sector_count = ffs(probe_ent->udma_mask + 1) + 0x3e;
+
+	ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, READ_CMD);
+}
+
+static int ahci_port_start(struct ahci_probe_ent *probe_ent,
+					u8 port)
+{
+	struct ahci_ioports *pp = &(probe_ent->port[port]);
+	struct sata_port_regs *port_mmio =
+		(struct sata_port_regs *)pp->port_mmio;
+	u32 port_status;
+	u32 mem;
+	int timeout = 10000000;
+
+	debug("Enter start port: %d\n", port);
+	port_status = readl(&(port_mmio->ssts));
+	debug("Port %d status: %x\n", port, port_status);
+	if ((port_status & 0xf) != 0x03) {
+		printf("No Link on this port!\n");
+		return -1;
+	}
+
+	mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
+	if (!mem) {
+		free(pp);
+		printf("No mem for table!\n");
+		return -ENOMEM;
+	}
+
+	mem = (mem + 0x400) & (~0x3ff);	/* Aligned to 1024-bytes */
+	memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
+
+	/*
+	 * First item in chunk of DMA memory: 32-slot command table,
+	 * 32 bytes each in size
+	 */
+	pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
+	debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot);
+	mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
+
+	/*
+	 * Second item: Received-FIS area, 256-Byte aligned
+	 */
+	pp->rx_fis = mem;
+	mem += AHCI_RX_FIS_SZ;
+
+	/*
+	 * Third item: data area for storing a single command
+	 * and its scatter-gather table
+	 */
+	pp->cmd_tbl = mem;
+	debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
+
+	mem += AHCI_CMD_TBL_HDR;
+
+	writel_with_flush(0x00004444, &(port_mmio->dmacr));
+	pp->cmd_tbl_sg = (struct ahci_sg *)mem;
+	writel_with_flush((u32)pp->cmd_slot, &(port_mmio->clb));
+	writel_with_flush(pp->rx_fis, &(port_mmio->fb));
+
+	/* Enable FRE */
+	writel_with_flush((SATA_PORT_CMD_FRE | readl(&(port_mmio->cmd))),
+			&(port_mmio->cmd));
+
+	/* Wait device ready */
+	while ((readl(&(port_mmio->tfd)) & (SATA_PORT_TFD_STS_ERR |
+		SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY))
+		&& --timeout)
+		;
+	if (timeout <= 0) {
+		debug("Device not ready for BSY, DRQ and"
+			"ERR in TFD!\n");
+		return -1;
+	}
+
+	writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
+			  PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
+			  PORT_CMD_START, &(port_mmio->cmd));
+
+	debug("Exit start port %d\n", port);
+
+	return 0;
+}
+
+int init_sata(int dev)
+{
+	int i;
+	u32 linkmap;
+	struct ahci_probe_ent *probe_ent = NULL;
+
+	if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
+		printf("The sata index %d is out of ranges\n\r", dev);
+		return -1;
+	}
+
+	ahci_init_one(dev);
+
+	probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+	linkmap = probe_ent->link_port_map;
+
+	if (0 == linkmap) {
+		printf("No port device detected!\n");
+		return 1;
+	}
+
+	for (i = 0; i < probe_ent->n_ports; i++) {
+		if ((linkmap >> i) && ((linkmap >> i) & 0x01)) {
+			if (ahci_port_start(probe_ent, (u8)i)) {
+				printf("Can not start port %d\n", i);
+				return 1;
+			}
+			probe_ent->hard_port_no = i;
+			break;
+		}
+	}
+
+	return 0;
+}
+
+static void dwc_ahsata_print_info(int dev)
+{
+	block_dev_desc_t *pdev = &(sata_dev_desc[dev]);
+
+	printf("SATA Device Info:\n\r");
+#ifdef CONFIG_SYS_64BIT_LBA
+	printf("S/N: %s\n\rProduct model number: %s\n\r"
+		"Firmware version: %s\n\rCapacity: %lld sectors\n\r",
+		pdev->product, pdev->vendor, pdev->revision, pdev->lba);
+#else
+	printf("S/N: %s\n\rProduct model number: %s\n\r"
+		"Firmware version: %s\n\rCapacity: %ld sectors\n\r",
+		pdev->product, pdev->vendor, pdev->revision, pdev->lba);
+#endif
+}
+
+static void dwc_ahsata_identify(int dev, u16 *id)
+{
+	struct ahci_probe_ent *probe_ent =
+		(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+	struct sata_fis_h2d h2d, *cfis = &h2d;
+	u8 port = probe_ent->hard_port_no;
+
+	memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+	cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+	cfis->pm_port_c = 0x80; /* is command */
+	cfis->command = ATA_CMD_ID_ATA;
+
+	ahci_exec_ata_cmd(probe_ent, port, cfis,
+			(u8 *)id, ATA_ID_WORDS * 2, READ_CMD);
+	ata_swap_buf_le16(id, ATA_ID_WORDS);
+}
+
+static void dwc_ahsata_xfer_mode(int dev, u16 *id)
+{
+	struct ahci_probe_ent *probe_ent =
+		(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+
+	probe_ent->pio_mask = id[ATA_ID_PIO_MODES];
+	probe_ent->udma_mask = id[ATA_ID_UDMA_MODES];
+	debug("pio %04x, udma %04x\n\r",
+		probe_ent->pio_mask, probe_ent->udma_mask);
+}
+
+static u32 dwc_ahsata_rw_cmd(int dev, u32 start, u32 blkcnt,
+				u8 *buffer, int is_write)
+{
+	struct ahci_probe_ent *probe_ent =
+		(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+	struct sata_fis_h2d h2d, *cfis = &h2d;
+	u8 port = probe_ent->hard_port_no;
+	u32 block;
+
+	block = start;
+
+	memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+	cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+	cfis->pm_port_c = 0x80; /* is command */
+	cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
+	cfis->device = ATA_LBA;
+
+	cfis->device |= (block >> 24) & 0xf;
+	cfis->lba_high = (block >> 16) & 0xff;
+	cfis->lba_mid = (block >> 8) & 0xff;
+	cfis->lba_low = block & 0xff;
+	cfis->sector_count = (u8)(blkcnt & 0xff);
+
+	if (ahci_exec_ata_cmd(probe_ent, port, cfis,
+			buffer, ATA_SECT_SIZE * blkcnt, is_write) > 0)
+		return blkcnt;
+	else
+		return 0;
+}
+
+void dwc_ahsata_flush_cache(int dev)
+{
+	struct ahci_probe_ent *probe_ent =
+		(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+	struct sata_fis_h2d h2d, *cfis = &h2d;
+	u8 port = probe_ent->hard_port_no;
+
+	memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+	cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+	cfis->pm_port_c = 0x80; /* is command */
+	cfis->command = ATA_CMD_FLUSH;
+
+	ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, 0);
+}
+
+static u32 dwc_ahsata_rw_cmd_ext(int dev, u32 start, lbaint_t blkcnt,
+				u8 *buffer, int is_write)
+{
+	struct ahci_probe_ent *probe_ent =
+		(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+	struct sata_fis_h2d h2d, *cfis = &h2d;
+	u8 port = probe_ent->hard_port_no;
+	u64 block;
+
+	block = (u64)start;
+
+	memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+	cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+	cfis->pm_port_c = 0x80; /* is command */
+
+	cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
+				 : ATA_CMD_READ_EXT;
+
+	cfis->lba_high_exp = (block >> 40) & 0xff;
+	cfis->lba_mid_exp = (block >> 32) & 0xff;
+	cfis->lba_low_exp = (block >> 24) & 0xff;
+	cfis->lba_high = (block >> 16) & 0xff;
+	cfis->lba_mid = (block >> 8) & 0xff;
+	cfis->lba_low = block & 0xff;
+	cfis->device = ATA_LBA;
+	cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
+	cfis->sector_count = blkcnt & 0xff;
+
+	if (ahci_exec_ata_cmd(probe_ent, port, cfis, buffer,
+			ATA_SECT_SIZE * blkcnt, is_write) > 0)
+		return blkcnt;
+	else
+		return 0;
+}
+
+u32 dwc_ahsata_rw_ncq_cmd(int dev, u32 start, lbaint_t blkcnt,
+				u8 *buffer, int is_write)
+{
+	struct ahci_probe_ent *probe_ent =
+		(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+	struct sata_fis_h2d h2d, *cfis = &h2d;
+	u8 port = probe_ent->hard_port_no;
+	u64 block;
+
+	if (sata_dev_desc[dev].lba48 != 1) {
+		printf("execute FPDMA command on non-LBA48 hard disk\n\r");
+		return -1;
+	}
+
+	block = (u64)start;
+
+	memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+	cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+	cfis->pm_port_c = 0x80; /* is command */
+
+	cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE
+				 : ATA_CMD_FPDMA_READ;
+
+	cfis->lba_high_exp = (block >> 40) & 0xff;
+	cfis->lba_mid_exp = (block >> 32) & 0xff;
+	cfis->lba_low_exp = (block >> 24) & 0xff;
+	cfis->lba_high = (block >> 16) & 0xff;
+	cfis->lba_mid = (block >> 8) & 0xff;
+	cfis->lba_low = block & 0xff;
+
+	cfis->device = ATA_LBA;
+	cfis->features_exp = (blkcnt >> 8) & 0xff;
+	cfis->features = blkcnt & 0xff;
+
+	/* Use the latest queue */
+	ahci_exec_ata_cmd(probe_ent, port, cfis,
+			buffer, ATA_SECT_SIZE * blkcnt, is_write);
+
+	return blkcnt;
+}
+
+void dwc_ahsata_flush_cache_ext(int dev)
+{
+	struct ahci_probe_ent *probe_ent =
+		(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+	struct sata_fis_h2d h2d, *cfis = &h2d;
+	u8 port = probe_ent->hard_port_no;
+
+	memset(cfis, 0, sizeof(struct sata_fis_h2d));
+
+	cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
+	cfis->pm_port_c = 0x80; /* is command */
+	cfis->command = ATA_CMD_FLUSH_EXT;
+
+	ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, 0);
+}
+
+static void dwc_ahsata_init_wcache(int dev, u16 *id)
+{
+	struct ahci_probe_ent *probe_ent =
+		(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+
+	if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
+		probe_ent->flags |= SATA_FLAG_WCACHE;
+	if (ata_id_has_flush(id))
+		probe_ent->flags |= SATA_FLAG_FLUSH;
+	if (ata_id_has_flush_ext(id))
+		probe_ent->flags |= SATA_FLAG_FLUSH_EXT;
+}
+
+u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt,
+				void *buffer, int is_write)
+{
+	u32 start, blks;
+	u8 *addr;
+	int max_blks;
+
+	start = blknr;
+	blks = blkcnt;
+	addr = (u8 *)buffer;
+
+	max_blks = ATA_MAX_SECTORS_LBA48;
+
+	do {
+		if (blks > max_blks) {
+			if (max_blks != dwc_ahsata_rw_cmd_ext(dev, start,
+						max_blks, addr, is_write))
+				return 0;
+			start += max_blks;
+			blks -= max_blks;
+			addr += ATA_SECT_SIZE * max_blks;
+		} else {
+			if (blks != dwc_ahsata_rw_cmd_ext(dev, start,
+						blks, addr, is_write))
+				return 0;
+			start += blks;
+			blks = 0;
+			addr += ATA_SECT_SIZE * blks;
+		}
+	} while (blks != 0);
+
+	return blkcnt;
+}
+
+u32 ata_low_level_rw_lba28(int dev, u32 blknr, lbaint_t blkcnt,
+				void *buffer, int is_write)
+{
+	u32 start, blks;
+	u8 *addr;
+	int max_blks;
+
+	start = blknr;
+	blks = blkcnt;
+	addr = (u8 *)buffer;
+
+	max_blks = ATA_MAX_SECTORS;
+	do {
+		if (blks > max_blks) {
+			if (max_blks != dwc_ahsata_rw_cmd(dev, start,
+						max_blks, addr, is_write))
+				return 0;
+			start += max_blks;
+			blks -= max_blks;
+			addr += ATA_SECT_SIZE * max_blks;
+		} else {
+			if (blks != dwc_ahsata_rw_cmd(dev, start,
+						blks, addr, is_write))
+				return 0;
+			start += blks;
+			blks = 0;
+			addr += ATA_SECT_SIZE * blks;
+		}
+	} while (blks != 0);
+
+	return blkcnt;
+}
+
+/*
+ * SATA interface between low level driver and command layer
+ */
+ulong sata_read(int dev, unsigned long blknr, lbaint_t blkcnt, void *buffer)
+{
+	u32 rc;
+
+	if (sata_dev_desc[dev].lba48)
+		rc = ata_low_level_rw_lba48(dev, blknr, blkcnt,
+						buffer, READ_CMD);
+	else
+		rc = ata_low_level_rw_lba28(dev, blknr, blkcnt,
+						buffer, READ_CMD);
+	return rc;
+}
+
+ulong sata_write(int dev, unsigned long blknr, lbaint_t blkcnt, void *buffer)
+{
+	u32 rc;
+	struct ahci_probe_ent *probe_ent =
+		(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+	u32 flags = probe_ent->flags;
+
+	if (sata_dev_desc[dev].lba48) {
+		rc = ata_low_level_rw_lba48(dev, blknr, blkcnt,
+						buffer, WRITE_CMD);
+		if ((flags & SATA_FLAG_WCACHE) &&
+			(flags & SATA_FLAG_FLUSH_EXT))
+			dwc_ahsata_flush_cache_ext(dev);
+	} else {
+		rc = ata_low_level_rw_lba28(dev, blknr, blkcnt,
+						buffer, WRITE_CMD);
+		if ((flags & SATA_FLAG_WCACHE) &&
+			(flags & SATA_FLAG_FLUSH))
+			dwc_ahsata_flush_cache(dev);
+	}
+	return rc;
+}
+
+int scan_sata(int dev)
+{
+	u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
+	u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
+	u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
+	u16 *id;
+	u64 n_sectors;
+	struct ahci_probe_ent *probe_ent =
+		(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
+	u8 port = probe_ent->hard_port_no;
+	block_dev_desc_t *pdev = &(sata_dev_desc[dev]);
+
+	id = (u16 *)malloc(ATA_ID_WORDS * 2);
+	if (!id) {
+		printf("id malloc failed\n\r");
+		return -1;
+	}
+
+	/* Identify device to get information */
+	dwc_ahsata_identify(dev, id);
+
+	/* Serial number */
+	ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
+	memcpy(pdev->product, serial, sizeof(serial));
+
+	/* Firmware version */
+	ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
+	memcpy(pdev->revision, firmware, sizeof(firmware));
+
+	/* Product model */
+	ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
+	memcpy(pdev->vendor, product, sizeof(product));
+
+	/* Totoal sectors */
+	n_sectors = ata_id_n_sectors(id);
+	pdev->lba = (u32)n_sectors;
+
+	pdev->type = DEV_TYPE_HARDDISK;
+	pdev->blksz = ATA_SECT_SIZE;
+	pdev->lun = 0 ;
+
+	/* Check if support LBA48 */
+	if (ata_id_has_lba48(id)) {
+		pdev->lba48 = 1;
+		debug("Device support LBA48\n\r");
+	}
+
+	/* Get the NCQ queue depth from device */
+	probe_ent->flags &= (~SATA_FLAG_Q_DEP_MASK);
+	probe_ent->flags |= ata_id_queue_depth(id);
+
+	/* Get the xfer mode from device */
+	dwc_ahsata_xfer_mode(dev, id);
+
+	/* Get the write cache status from device */
+	dwc_ahsata_init_wcache(dev, id);
+
+	/* Set the xfer mode to highest speed */
+	ahci_set_feature(dev, port);
+
+	free((void *)id);
+
+	dwc_ahsata_print_info(dev);
+
+	is_ready = 1;
+
+	return 0;
+}
diff --git a/drivers/block/dwc_ahsata.h b/drivers/block/dwc_ahsata.h
new file mode 100644
index 0000000000..84860ea492
--- /dev/null
+++ b/drivers/block/dwc_ahsata.h
@@ -0,0 +1,335 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Terry Lv <r65388@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FSL_SATA_H__
+#define __FSL_SATA_H__
+
+#define DWC_AHSATA_MAX_CMD_SLOTS	32
+
+/* Max host controller numbers */
+#define SATA_HC_MAX_NUM		4
+/* Max command queue depth per host controller */
+#define DWC_AHSATA_HC_MAX_CMD	32
+/* Max port number per host controller */
+#define SATA_HC_MAX_PORT	16
+
+/* Generic Host Register */
+
+/* HBA Capabilities Register */
+#define SATA_HOST_CAP_S64A		0x80000000
+#define SATA_HOST_CAP_SNCQ		0x40000000
+#define SATA_HOST_CAP_SSNTF		0x20000000
+#define SATA_HOST_CAP_SMPS		0x10000000
+#define SATA_HOST_CAP_SSS		0x08000000
+#define SATA_HOST_CAP_SALP		0x04000000
+#define SATA_HOST_CAP_SAL		0x02000000
+#define SATA_HOST_CAP_SCLO		0x01000000
+#define SATA_HOST_CAP_ISS_MASK		0x00f00000
+#define SATA_HOST_CAP_ISS_OFFSET	20
+#define SATA_HOST_CAP_SNZO		0x00080000
+#define SATA_HOST_CAP_SAM		0x00040000
+#define SATA_HOST_CAP_SPM		0x00020000
+#define SATA_HOST_CAP_PMD		0x00008000
+#define SATA_HOST_CAP_SSC		0x00004000
+#define SATA_HOST_CAP_PSC		0x00002000
+#define SATA_HOST_CAP_NCS		0x00001f00
+#define SATA_HOST_CAP_CCCS		0x00000080
+#define SATA_HOST_CAP_EMS		0x00000040
+#define SATA_HOST_CAP_SXS		0x00000020
+#define SATA_HOST_CAP_NP_MASK		0x0000001f
+
+/* Global HBA Control Register */
+#define SATA_HOST_GHC_AE	0x80000000
+#define SATA_HOST_GHC_IE	0x00000002
+#define SATA_HOST_GHC_HR	0x00000001
+
+/* Interrupt Status Register */
+
+/* Ports Implemented Register */
+
+/* AHCI Version Register */
+#define SATA_HOST_VS_MJR_MASK	0xffff0000
+#define SATA_HOST_VS_MJR_OFFSET	16
+#define SATA_HOST_VS_MJR_MNR	0x0000ffff
+
+/* Command Completion Coalescing Control */
+#define SATA_HOST_CCC_CTL_TV_MASK	0xffff0000
+#define SATA_HOST_CCC_CTL_TV_OFFSET		16
+#define SATA_HOST_CCC_CTL_CC_MASK	0x0000ff00
+#define SATA_HOST_CCC_CTL_CC_OFFSET		8
+#define SATA_HOST_CCC_CTL_INT_MASK	0x000000f8
+#define SATA_HOST_CCC_CTL_INT_OFFSET	3
+#define SATA_HOST_CCC_CTL_EN	0x00000001
+
+/* Command Completion Coalescing Ports */
+
+/* HBA Capabilities Extended Register */
+#define SATA_HOST_CAP2_APST		0x00000004
+
+/* BIST Activate FIS Register */
+#define SATA_HOST_BISTAFR_NCP_MASK	0x0000ff00
+#define SATA_HOST_BISTAFR_NCP_OFFSET	8
+#define SATA_HOST_BISTAFR_PD_MASK	0x000000ff
+#define SATA_HOST_BISTAFR_PD_OFFSET		0
+
+/* BIST Control Register */
+#define SATA_HOST_BISTCR_FERLB	0x00100000
+#define SATA_HOST_BISTCR_TXO	0x00040000
+#define SATA_HOST_BISTCR_CNTCLR	0x00020000
+#define SATA_HOST_BISTCR_NEALB	0x00010000
+#define SATA_HOST_BISTCR_LLC_MASK	0x00000700
+#define SATA_HOST_BISTCR_LLC_OFFSET	8
+#define SATA_HOST_BISTCR_ERREN	0x00000040
+#define SATA_HOST_BISTCR_FLIP	0x00000020
+#define SATA_HOST_BISTCR_PV		0x00000010
+#define SATA_HOST_BISTCR_PATTERN_MASK	0x0000000f
+#define SATA_HOST_BISTCR_PATTERN_OFFSET	0
+
+/* BIST FIS Count Register */
+
+/* BIST Status Register */
+#define SATA_HOST_BISTSR_FRAMERR_MASK	0x0000ffff
+#define SATA_HOST_BISTSR_FRAMERR_OFFSET	0
+#define SATA_HOST_BISTSR_BRSTERR_MASK	0x00ff0000
+#define SATA_HOST_BISTSR_BRSTERR_OFFSET	16
+
+/* BIST DWORD Error Count Register */
+
+/* OOB Register*/
+#define SATA_HOST_OOBR_WE		0x80000000
+#define SATA_HOST_OOBR_cwMin_MASK	0x7f000000
+#define SATA_HOST_OOBR_cwMAX_MASK	0x00ff0000
+#define SATA_HOST_OOBR_ciMin_MASK	0x0000ff00
+#define SATA_HOST_OOBR_ciMax_MASK	0x000000ff
+
+/* Timer 1-ms Register */
+
+/* Global Parameter 1 Register */
+#define SATA_HOST_GPARAM1R_ALIGN_M	0x80000000
+#define SATA_HOST_GPARAM1R_RX_BUFFER	0x40000000
+#define SATA_HOST_GPARAM1R_PHY_DATA_MASK	0x30000000
+#define SATA_HOST_GPARAM1R_PHY_RST	0x08000000
+#define SATA_HOST_GPARAM1R_PHY_CTRL_MASK	0x07e00000
+#define SATA_HOST_GPARAM1R_PHY_STAT_MASK	0x001f8000
+#define SATA_HOST_GPARAM1R_LATCH_M	0x00004000
+#define SATA_HOST_GPARAM1R_BIST_M	0x00002000
+#define SATA_HOST_GPARAM1R_PHY_TYPE	0x00001000
+#define SATA_HOST_GPARAM1R_RETURN_ERR	0x00000400
+#define SATA_HOST_GPARAM1R_AHB_ENDIAN_MASK	0x00000300
+#define SATA_HOST_GPARAM1R_S_HADDR	0X00000080
+#define SATA_HOST_GPARAM1R_M_HADDR	0X00000040
+
+/* Global Parameter 2 Register */
+#define SATA_HOST_GPARAM2R_DEV_CP	0x00004000
+#define SATA_HOST_GPARAM2R_DEV_MP	0x00002000
+#define SATA_HOST_GPARAM2R_DEV_ENCODE_M	0x00001000
+#define SATA_HOST_GPARAM2R_RXOOB_CLK_M	0x00000800
+#define SATA_HOST_GPARAM2R_RXOOB_M	0x00000400
+#define SATA_HOST_GPARAM2R_TX_OOB_M	0x00000200
+#define SATA_HOST_GPARAM2R_RXOOB_CLK_MASK	0x000001ff
+
+/* Port Parameter Register */
+#define SATA_HOST_PPARAMR_TX_MEM_M	0x00000200
+#define SATA_HOST_PPARAMR_TX_MEM_S	0x00000100
+#define SATA_HOST_PPARAMR_RX_MEM_M	0x00000080
+#define SATA_HOST_PPARAMR_RX_MEM_S	0x00000040
+#define SATA_HOST_PPARAMR_TXFIFO_DEPTH_MASK	0x00000038
+#define SATA_HOST_PPARAMR_RXFIFO_DEPTH_MASK	0x00000007
+
+/* Test Register */
+#define SATA_HOST_TESTR_PSEL_MASK	0x00070000
+#define SATA_HOST_TESTR_TEST_IF		0x00000001
+
+/* Port Register Descriptions */
+/* Port# Command List Base Address Register */
+#define SATA_PORT_CLB_CLB_MASK		0xfffffc00
+
+/* Port# Command List Base Address Upper 32-Bits Register */
+
+/* Port# FIS Base Address Register */
+#define SATA_PORT_FB_FB_MASK		0xfffffff0
+
+/* Port# FIS Base Address Upper 32-Bits Register */
+
+/* Port# Interrupt Status Register */
+#define SATA_PORT_IS_CPDS		0x80000000
+#define SATA_PORT_IS_TFES		0x40000000
+#define SATA_PORT_IS_HBFS		0x20000000
+#define SATA_PORT_IS_HBDS		0x10000000
+#define SATA_PORT_IS_IFS		0x08000000
+#define SATA_PORT_IS_INFS		0x04000000
+#define SATA_PORT_IS_OFS		0x01000000
+#define SATA_PORT_IS_IPMS		0x00800000
+#define SATA_PORT_IS_PRCS		0x00400000
+#define SATA_PORT_IS_DMPS		0x00000080
+#define SATA_PORT_IS_PCS		0x00000040
+#define SATA_PORT_IS_DPS		0x00000020
+#define SATA_PORT_IS_UFS		0x00000010
+#define SATA_PORT_IS_SDBS		0x00000008
+#define SATA_PORT_IS_DSS		0x00000004
+#define SATA_PORT_IS_PSS		0x00000002
+#define SATA_PORT_IS_DHRS		0x00000001
+
+/* Port# Interrupt Enable Register */
+#define SATA_PORT_IE_CPDE		0x80000000
+#define SATA_PORT_IE_TFEE		0x40000000
+#define SATA_PORT_IE_HBFE		0x20000000
+#define SATA_PORT_IE_HBDE		0x10000000
+#define SATA_PORT_IE_IFE		0x08000000
+#define SATA_PORT_IE_INFE		0x04000000
+#define SATA_PORT_IE_OFE		0x01000000
+#define SATA_PORT_IE_IPME		0x00800000
+#define SATA_PORT_IE_PRCE		0x00400000
+#define SATA_PORT_IE_DMPE		0x00000080
+#define SATA_PORT_IE_PCE		0x00000040
+#define SATA_PORT_IE_DPE		0x00000020
+#define SATA_PORT_IE_UFE		0x00000010
+#define SATA_PORT_IE_SDBE		0x00000008
+#define SATA_PORT_IE_DSE		0x00000004
+#define SATA_PORT_IE_PSE		0x00000002
+#define SATA_PORT_IE_DHRE		0x00000001
+
+/* Port# Command Register */
+#define SATA_PORT_CMD_ICC_MASK		0xf0000000
+#define SATA_PORT_CMD_ASP		0x08000000
+#define SATA_PORT_CMD_ALPE		0x04000000
+#define SATA_PORT_CMD_DLAE		0x02000000
+#define SATA_PORT_CMD_ATAPI		0x01000000
+#define SATA_PORT_CMD_APSTE		0x00800000
+#define SATA_PORT_CMD_ESP		0x00200000
+#define SATA_PORT_CMD_CPD		0x00100000
+#define SATA_PORT_CMD_MPSP		0x00080000
+#define SATA_PORT_CMD_HPCP		0x00040000
+#define SATA_PORT_CMD_PMA		0x00020000
+#define SATA_PORT_CMD_CPS		0x00010000
+#define SATA_PORT_CMD_CR		0x00008000
+#define SATA_PORT_CMD_FR		0x00004000
+#define SATA_PORT_CMD_MPSS		0x00002000
+#define SATA_PORT_CMD_CCS_MASK		0x00001f00
+#define SATA_PORT_CMD_FRE		0x00000010
+#define SATA_PORT_CMD_CLO		0x00000008
+#define SATA_PORT_CMD_POD		0x00000004
+#define SATA_PORT_CMD_SUD		0x00000002
+#define SATA_PORT_CMD_ST		0x00000001
+
+/* Port# Task File Data Register */
+#define SATA_PORT_TFD_ERR_MASK		0x0000ff00
+#define SATA_PORT_TFD_STS_MASK		0x000000ff
+#define SATA_PORT_TFD_STS_ERR		0x00000001
+#define SATA_PORT_TFD_STS_DRQ		0x00000008
+#define SATA_PORT_TFD_STS_BSY		0x00000080
+
+/* Port# Signature Register */
+
+/* Port# Serial ATA Status {SStatus} Register */
+#define SATA_PORT_SSTS_IPM_MASK		0x00000f00
+#define SATA_PORT_SSTS_SPD_MASK		0x000000f0
+#define SATA_PORT_SSTS_DET_MASK		0x0000000f
+
+/* Port# Serial ATA Control {SControl} Register */
+#define SATA_PORT_SCTL_IPM_MASK		0x00000f00
+#define SATA_PORT_SCTL_SPD_MASK		0x000000f0
+#define SATA_PORT_SCTL_DET_MASK		0x0000000f
+
+/* Port# Serial ATA Error {SError} Register */
+#define SATA_PORT_SERR_DIAG_X		0x04000000
+#define SATA_PORT_SERR_DIAG_F		0x02000000
+#define SATA_PORT_SERR_DIAG_T		0x01000000
+#define SATA_PORT_SERR_DIAG_S		0x00800000
+#define SATA_PORT_SERR_DIAG_H		0x00400000
+#define SATA_PORT_SERR_DIAG_C		0x00200000
+#define SATA_PORT_SERR_DIAG_D		0x00100000
+#define SATA_PORT_SERR_DIAG_B		0x00080000
+#define SATA_PORT_SERR_DIAG_W		0x00040000
+#define SATA_PORT_SERR_DIAG_I		0x00020000
+#define SATA_PORT_SERR_DIAG_N		0x00010000
+#define SATA_PORT_SERR_ERR_E		0x00000800
+#define SATA_PORT_SERR_ERR_P		0x00000400
+#define SATA_PORT_SERR_ERR_C		0x00000200
+#define SATA_PORT_SERR_ERR_T		0x00000100
+#define SATA_PORT_SERR_ERR_M		0x00000002
+#define SATA_PORT_SERR_ERR_I		0x00000001
+
+/* Port# Serial ATA Active {SActive} Register */
+
+/* Port# Command Issue Register */
+
+/* Port# Serial ATA Notification Register */
+
+/* Port# DMA Control Register */
+#define SATA_PORT_DMACR_RXABL_MASK	0x0000f000
+#define SATA_PORT_DMACR_TXABL_MASK	0x00000f00
+#define SATA_PORT_DMACR_RXTS_MASK	0x000000f0
+#define SATA_PORT_DMACR_TXTS_MASK	0x0000000f
+
+/* Port# PHY Control Register */
+
+/* Port# PHY Status Register */
+
+#define SATA_HC_CMD_HDR_ENTRY_SIZE	sizeof(struct cmd_hdr_entry)
+
+/* DW0
+*/
+#define CMD_HDR_DI_CFL_MASK	0x0000001f
+#define CMD_HDR_DI_CFL_OFFSET	0
+#define CMD_HDR_DI_A			0x00000020
+#define CMD_HDR_DI_W			0x00000040
+#define CMD_HDR_DI_P			0x00000080
+#define CMD_HDR_DI_R			0x00000100
+#define CMD_HDR_DI_B			0x00000200
+#define CMD_HDR_DI_C			0x00000400
+#define CMD_HDR_DI_PMP_MASK	0x0000f000
+#define CMD_HDR_DI_PMP_OFFSET	12
+#define CMD_HDR_DI_PRDTL		0xffff0000
+#define CMD_HDR_DI_PRDTL_OFFSET	16
+
+/* prde_fis_len
+*/
+#define CMD_HDR_PRD_ENTRY_SHIFT	16
+#define CMD_HDR_PRD_ENTRY_MASK	0x003f0000
+#define CMD_HDR_FIS_LEN_SHIFT	2
+
+/* attribute
+*/
+#define CMD_HDR_ATTR_RES	0x00000800 /* Reserved bit, should be 1 */
+#define CMD_HDR_ATTR_VBIST	0x00000400 /* Vendor BIST */
+/* Snoop enable for all descriptor */
+#define CMD_HDR_ATTR_SNOOP	0x00000200
+#define CMD_HDR_ATTR_FPDMA	0x00000100 /* FPDMA queued command */
+#define CMD_HDR_ATTR_RESET	0x00000080 /* Reset - a SRST or device reset */
+/* BIST - require the host to enter BIST mode */
+#define CMD_HDR_ATTR_BIST	0x00000040
+#define CMD_HDR_ATTR_ATAPI	0x00000020 /* ATAPI command */
+#define CMD_HDR_ATTR_TAG	0x0000001f /* TAG mask */
+
+#define FLAGS_DMA	0x00000000
+#define FLAGS_FPDMA	0x00000001
+
+#define SATA_FLAG_Q_DEP_MASK	0x0000000f
+#define SATA_FLAG_WCACHE	0x00000100
+#define SATA_FLAG_FLUSH		0x00000200
+#define SATA_FLAG_FLUSH_EXT	0x00000400
+
+#define READ_CMD	0
+#define WRITE_CMD	1
+
+extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
+
+#endif /* __FSL_SATA_H__ */
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 5d864b56ef..c01ffa54fe 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -29,6 +29,7 @@ COBJS-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
 COBJS-$(CONFIG_APBH_DMA) += apbh_dma.o
 COBJS-$(CONFIG_FSL_DMA) += fsl_dma.o
 COBJS-$(CONFIG_OMAP3_DMA) += omap3_dma.o
+COBJS-$(CONFIG_NAND_RDA_DMA) += rda_dma.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
diff --git a/drivers/dma/rda_dma.c b/drivers/dma/rda_dma.c
new file mode 100644
index 0000000000..c7f74c9930
--- /dev/null
+++ b/drivers/dma/rda_dma.c
@@ -0,0 +1,143 @@
+/***************************************************************
+*
+* Copyright(C) RDA Micro Company.,2012
+* All Rights Reserved. Confidential
+*
+****************************************************************
+*
+* Project: RDA8810
+* File Name: drivers/dma/rda_dma.c
+*
+* Author: Jason Tao
+* Creation Date: 2012-11-15
+*
+*****************************************************************
+*
+* Implementation of functions of DMA
+*
+*****************************************************************
+*/
+
+#include <common.h>
+#include <asm/arch/rda_iomap.h>
+#include <asm/arch/dma.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <linux/compiler.h>
+
+/* 0x20820000 */
+static void __iomem *dma_base = (void __iomem *)RDA_DMA_BASE;
+
+static inline void __dma_write(u32 val, u32 offset, u8 ch)
+{
+	__raw_writel(val, dma_base + offset);
+}
+
+static inline u32 __dma_read(u32 offset, u8 ch)
+{
+	u32 val;
+
+	val = __raw_readl(dma_base + offset);
+	return val;
+}
+
+int rda_set_dma_params(u8 ch, struct rda_dma_chan_params *params)
+{
+	dma_addr_t src;
+	dma_addr_t dst;
+	u32 size;
+	u32 mode;
+
+	if (!params) {
+		printf("rda8810 dma : Invalid parameter!\n");
+		return -EINVAL;
+	}
+
+	src = params->src_addr;
+	dst = params->dst_addr;
+	size = params->xfer_size;
+	mode = (params->dma_mode & RDA_DMA_MODE_MASK);
+#if 0
+	printf("[rda_dma] : src = 0x%08x, dst = 0x%08x, size = 0x%x\n", src,
+	       dst, size);
+#endif /* #if 0 */
+	switch (mode) {
+	case RDA_DMA_FW_MODE:
+		/*
+		 * DMA transits data by a word(4 bytes).
+		 * The mask is only for NANDFC that supports no more than 2048 words(8192 bytes),
+		 * but our address's unit is byte. So we have to mask 0x1FFF.
+		 */
+		dst &= 0x1FFF;
+		break;
+
+	case RDA_DMA_FR_MODE:
+		src &= 0x1FFF;
+		break;
+
+	case RDA_DMA_NOR_MODE:
+		/* Nothing to do */
+		break;
+
+	default:
+		printf("[rda8810 dma] : Invalid mode of dma!\r\n");
+		return -EINVAL;
+	}
+
+	/* Fill src address */
+	__dma_write(src, RDA_DMA_SRC_REG, ch);
+	/* Fill dst address */
+	__dma_write(dst, RDA_DMA_DST_REG, ch);
+	/* Fill size */
+	__dma_write(size, RDA_DMA_XFER_SIZE_REG, ch);
+
+	/* Set ctl flag */
+	__dma_write(mode, RDA_DMA_CTL_REG, ch);
+
+	return 0;
+}
+
+void rda_start_dma(u8 ch)
+{
+	u32 reg = 0;
+
+	reg = __dma_read(RDA_DMA_CTL_REG, ch);
+
+	reg |= RDA_DMA_CTL_EN;
+	__dma_write(reg, RDA_DMA_CTL_REG, ch);
+
+	return;
+}
+
+void rda_stop_dma(u8 ch)
+{
+	u32 reg = RDA_DMA_CTL_INT_CLE;
+
+	__dma_write(reg, RDA_DMA_CTL_REG, ch);
+	return;
+}
+
+void rda_poll_dma(u8 ch)
+{
+	u32 reg = 0;
+
+	while (!((reg = __dma_read(RDA_DMA_STATUS_REG, ch)) & RDA_DMA_STA_INT)) {
+		asm("nop");
+	}
+
+	return;
+}
+
+int rda_request_dma(u8 * dma_ch_out)
+{
+	/* Clear interrupt flag and disble dma. */
+	rda_stop_dma(0);
+	*dma_ch_out = 0;
+
+	return 0;
+}
+
+void rda_free_dma(u8 ch)
+{
+	return;
+}
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index f1b1c16b1b..661553552e 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -41,7 +41,8 @@ static unsigned long gpio_ports[] = {
 	[0] = GPIO1_BASE_ADDR,
 	[1] = GPIO2_BASE_ADDR,
 	[2] = GPIO3_BASE_ADDR,
-#if defined(CONFIG_MX51) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
+#if defined(CONFIG_MX25) || defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
+		defined(CONFIG_MX6Q)
 	[3] = GPIO4_BASE_ADDR,
 #endif
 #if defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index f86e46c111..5dbdbe3672 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -27,6 +27,7 @@ LIB	:= $(obj)libi2c.o
 
 COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
 COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o
+COBJS-$(CONFIG_DW_I2C) += designware_i2c.o
 COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o
 COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
 COBJS-$(CONFIG_I2C_MV) += mv_i2c.o
@@ -40,11 +41,11 @@ COBJS-$(CONFIG_PPC4XX_I2C) += ppc4xx_i2c.o
 COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
 COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o
 COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o
-COBJS-$(CONFIG_SPEAR_I2C) += spr_i2c.o
 COBJS-$(CONFIG_TEGRA_I2C) += tegra_i2c.o
 COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
 COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o
 COBJS-$(CONFIG_SH_I2C) += sh_i2c.o
+COBJS-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
diff --git a/drivers/i2c/spr_i2c.c b/drivers/i2c/designware_i2c.c
index eabfe843f7..6d118acec4 100644
--- a/drivers/i2c/spr_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/spr_i2c.h>
+#include "designware_i2c.h"
 
 static struct i2c_regs *const i2c_regs_p =
     (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
@@ -40,6 +40,13 @@ static void set_speed(int i2c_spd)
 	unsigned int cntl;
 	unsigned int hcnt, lcnt;
 	unsigned int high, low;
+	unsigned int enbl;
+
+	/* to set speed cltr must be disabled */
+	enbl = readl(&i2c_regs_p->ic_enable);
+	enbl &= ~IC_ENABLE_0B;
+	writel(enbl, &i2c_regs_p->ic_enable);
+
 
 	cntl = (readl(&i2c_regs_p->ic_con) & (~IC_CON_SPD_MSK));
 
@@ -71,6 +78,10 @@ static void set_speed(int i2c_spd)
 
 	lcnt = (IC_CLK * low) / NANO_TO_MICRO;
 	writel(lcnt, &i2c_regs_p->ic_fs_scl_lcnt);
+
+	/* re-enable i2c ctrl back now that speed is set */
+	enbl |= IC_ENABLE_0B;
+	writel(enbl, &i2c_regs_p->ic_enable);
 }
 
 /*
@@ -113,7 +124,7 @@ int i2c_get_bus_speed(void)
 /*
  * i2c_init - Init function
  * @speed:	required i2c speed
- * @slaveadd:	slave address for the spear device
+ * @slaveadd:	slave address for the device
  *
  * Initialization function.
  */
diff --git a/arch/arm/include/asm/arch-spear/spr_i2c.h b/drivers/i2c/designware_i2c.h
index 7521ebc6cf..03b520ed43 100644
--- a/arch/arm/include/asm/arch-spear/spr_i2c.h
+++ b/drivers/i2c/designware_i2c.h
@@ -21,8 +21,8 @@
  * MA 02111-1307 USA
  */
 
-#ifndef __SPR_I2C_H_
-#define __SPR_I2C_H_
+#ifndef __DW_I2C_H_
+#define __DW_I2C_H_
 
 struct i2c_regs {
 	u32 ic_con;
@@ -143,4 +143,4 @@ struct i2c_regs {
 #define I2C_FAST_SPEED		400000
 #define I2C_STANDARD_SPEED	100000
 
-#endif /* __SPR_I2C_H_ */
+#endif /* __DW_I2C_H_ */
diff --git a/drivers/i2c/sh_sh7734_i2c.c b/drivers/i2c/sh_sh7734_i2c.c
new file mode 100644
index 0000000000..9da173d31e
--- /dev/null
+++ b/drivers/i2c/sh_sh7734_i2c.c
@@ -0,0 +1,387 @@
+/*
+ * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+
+struct sh_i2c {
+	u8 iccr1;
+	u8 iccr2;
+	u8 icmr;
+	u8 icier;
+	u8 icsr;
+	u8 sar;
+	u8 icdrt;
+	u8 icdrr;
+	u8 nf2cyc;
+	u8 __pad0;
+	u8 __pad1;
+};
+
+static struct sh_i2c *base;
+static u8 iccr1_cks, nf2cyc;
+
+/* ICCR1 */
+#define SH_I2C_ICCR1_ICE	(1 << 7)
+#define SH_I2C_ICCR1_RCVD	(1 << 6)
+#define SH_I2C_ICCR1_MST	(1 << 5)
+#define SH_I2C_ICCR1_TRS	(1 << 4)
+#define SH_I2C_ICCR1_MTRS	\
+	(SH_I2C_ICCR1_MST | SH_I2C_ICCR1_TRS)
+
+/* ICCR1 */
+#define SH_I2C_ICCR2_BBSY	(1 << 7)
+#define SH_I2C_ICCR2_SCP	(1 << 6)
+#define SH_I2C_ICCR2_SDAO	(1 << 5)
+#define SH_I2C_ICCR2_SDAOP	(1 << 4)
+#define SH_I2C_ICCR2_SCLO	(1 << 3)
+#define SH_I2C_ICCR2_IICRST	(1 << 1)
+
+#define SH_I2C_ICIER_TIE	(1 << 7)
+#define SH_I2C_ICIER_TEIE	(1 << 6)
+#define SH_I2C_ICIER_RIE	(1 << 5)
+#define SH_I2C_ICIER_NAKIE	(1 << 4)
+#define SH_I2C_ICIER_STIE	(1 << 3)
+#define SH_I2C_ICIER_ACKE	(1 << 2)
+#define SH_I2C_ICIER_ACKBR	(1 << 1)
+#define SH_I2C_ICIER_ACKBT	(1 << 0)
+
+#define SH_I2C_ICSR_TDRE	(1 << 7)
+#define SH_I2C_ICSR_TEND	(1 << 6)
+#define SH_I2C_ICSR_RDRF	(1 << 5)
+#define SH_I2C_ICSR_NACKF	(1 << 4)
+#define SH_I2C_ICSR_STOP	(1 << 3)
+#define SH_I2C_ICSR_ALOVE	(1 << 2)
+#define SH_I2C_ICSR_AAS		(1 << 1)
+#define SH_I2C_ICSR_ADZ		(1 << 0)
+
+#define IRQ_WAIT 1000
+
+static void sh_i2c_send_stop(struct sh_i2c *base)
+{
+	clrbits_8(&base->iccr2, SH_I2C_ICCR2_BBSY | SH_I2C_ICCR2_SCP);
+}
+
+static int check_icsr_bits(struct sh_i2c *base, u8 bits)
+{
+	int i;
+
+	for (i = 0; i < IRQ_WAIT; i++) {
+		if (bits & readb(&base->icsr))
+			return 0;
+		udelay(10);
+	}
+
+	return 1;
+}
+
+static int check_stop(struct sh_i2c *base)
+{
+	int ret = check_icsr_bits(base, SH_I2C_ICSR_STOP);
+	clrbits_8(&base->icsr, SH_I2C_ICSR_STOP);
+
+	return ret;
+}
+
+static int check_tend(struct sh_i2c *base, int stop)
+{
+	int ret = check_icsr_bits(base, SH_I2C_ICSR_TEND);
+
+	if (stop) {
+		clrbits_8(&base->icsr, SH_I2C_ICSR_STOP);
+		sh_i2c_send_stop(base);
+	}
+
+	clrbits_8(&base->icsr, SH_I2C_ICSR_TEND);
+	return ret;
+}
+
+static int check_tdre(struct sh_i2c *base)
+{
+	return check_icsr_bits(base, SH_I2C_ICSR_TDRE);
+}
+
+static int check_rdrf(struct sh_i2c *base)
+{
+	return check_icsr_bits(base, SH_I2C_ICSR_RDRF);
+}
+
+static int check_bbsy(struct sh_i2c *base)
+{
+	int i;
+
+	for (i = 0 ; i < IRQ_WAIT ; i++) {
+		if (!(SH_I2C_ICCR2_BBSY & readb(&base->iccr2)))
+			return 0;
+		udelay(10);
+	}
+	return 1;
+}
+
+static int check_ackbr(struct sh_i2c *base)
+{
+	int i;
+
+	for (i = 0 ; i < IRQ_WAIT ; i++) {
+		if (!(SH_I2C_ICIER_ACKBR & readb(&base->icier)))
+			return 0;
+		udelay(10);
+	}
+
+	return 1;
+}
+
+static void sh_i2c_reset(struct sh_i2c *base)
+{
+	setbits_8(&base->iccr2, SH_I2C_ICCR2_IICRST);
+
+	udelay(100);
+
+	clrbits_8(&base->iccr2, SH_I2C_ICCR2_IICRST);
+}
+
+static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg)
+{
+	if (check_bbsy(base)) {
+		puts("i2c bus busy\n");
+		goto fail;
+	}
+
+	setbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS);
+	clrsetbits_8(&base->iccr2, SH_I2C_ICCR2_SCP, SH_I2C_ICCR2_BBSY);
+
+	writeb((id << 1), &base->icdrt);
+
+	if (check_tend(base, 0)) {
+		puts("TEND check fail...\n");
+		goto fail;
+	}
+
+	if (check_ackbr(base)) {
+		check_tend(base, 0);
+		sh_i2c_send_stop(base);
+		goto fail;
+	}
+
+	writeb(reg, &base->icdrt);
+
+	if (check_tdre(base)) {
+		puts("TDRE check fail...\n");
+		goto fail;
+	}
+
+	if (check_tend(base, 0)) {
+		puts("TEND check fail...\n");
+		goto fail;
+	}
+
+	return 0;
+fail:
+
+	return 1;
+}
+
+static int
+i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 *val, int size)
+{
+	int i;
+
+	if (i2c_set_addr(base, id, reg)) {
+		puts("Fail set slave address\n");
+		return 1;
+	}
+
+	for (i = 0; i < size; i++) {
+		writeb(val[i], &base->icdrt);
+		check_tdre(base);
+	}
+
+	check_tend(base, 1);
+	check_stop(base);
+
+	udelay(100);
+
+	clrbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS);
+	clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE);
+	sh_i2c_reset(base);
+
+	return 0;
+}
+
+static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
+{
+	u8 ret = 0;
+
+	if (i2c_set_addr(base, id, reg)) {
+		puts("Fail set slave address\n");
+		goto fail;
+	}
+
+	clrsetbits_8(&base->iccr2, SH_I2C_ICCR2_SCP, SH_I2C_ICCR2_BBSY);
+	writeb((id << 1) | 1, &base->icdrt);
+
+	if (check_tend(base, 0))
+		puts("TDRE check fail...\n");
+
+	clrsetbits_8(&base->iccr1, SH_I2C_ICCR1_TRS, SH_I2C_ICCR1_MST);
+	clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE);
+	setbits_8(&base->icier, SH_I2C_ICIER_ACKBT);
+	setbits_8(&base->iccr1, SH_I2C_ICCR1_RCVD);
+
+	/* read data (dummy) */
+	ret = readb(&base->icdrr);
+
+	if (check_rdrf(base)) {
+		puts("check RDRF error\n");
+		goto fail;
+	}
+
+	clrbits_8(&base->icsr, SH_I2C_ICSR_STOP);
+	udelay(1000);
+
+	sh_i2c_send_stop(base);
+
+	if (check_stop(base)) {
+		puts("check STOP error\n");
+		goto fail;
+	}
+
+	clrbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS);
+	clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE);
+
+	/* data read */
+	ret = readb(&base->icdrr);
+
+fail:
+	clrbits_8(&base->iccr1, SH_I2C_ICCR1_RCVD);
+
+	return ret;
+}
+
+#ifdef CONFIG_I2C_MULTI_BUS
+static unsigned int current_bus;
+
+/**
+ * i2c_set_bus_num - change active I2C bus
+ *	@bus: bus index, zero based
+ *	@returns: 0 on success, non-0 on failure
+ */
+int i2c_set_bus_num(unsigned int bus)
+{
+	switch (bus) {
+	case 0:
+		base = (void *)CONFIG_SH_I2C_BASE0;
+		break;
+	case 1:
+		base = (void *)CONFIG_SH_I2C_BASE1;
+		break;
+	default:
+		printf("Bad bus: %d\n", bus);
+		return -1;
+	}
+
+	current_bus = bus;
+
+	return 0;
+}
+
+/**
+ * i2c_get_bus_num - returns index of active I2C bus
+ */
+unsigned int i2c_get_bus_num(void)
+{
+	return current_bus;
+}
+#endif
+
+void i2c_init(int speed, int slaveaddr)
+{
+#ifdef CONFIG_I2C_MULTI_BUS
+	current_bus = 0;
+#endif
+	base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0;
+
+	if (speed == 400000)
+		iccr1_cks = 0x07;
+	else
+		iccr1_cks = 0x0F;
+
+	nf2cyc = 1;
+
+	/* Reset */
+	sh_i2c_reset(base);
+
+	/* ICE enable and set clock */
+	writeb(SH_I2C_ICCR1_ICE | iccr1_cks, &base->iccr1);
+	writeb(nf2cyc, &base->nf2cyc);
+}
+
+/*
+ * i2c_read: - Read multiple bytes from an i2c device
+ *
+ * The higher level routines take into account that this function is only
+ * called with len < page length of the device (see configuration file)
+ *
+ * @chip:   address of the chip which is to be read
+ * @addr:   i2c data address within the chip
+ * @alen:   length of the i2c data address (1..2 bytes)
+ * @buffer: where to write the data
+ * @len:    how much byte do we want to read
+ * @return: 0 in case of success
+ */
+int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len)
+{
+	int i = 0;
+	for (i = 0; i < len; i++)
+		buffer[i] = i2c_raw_read(base, chip, addr + i);
+
+	return 0;
+}
+
+/*
+ * i2c_write: -  Write multiple bytes to an i2c device
+ *
+ * The higher level routines take into account that this function is only
+ * called with len < page length of the device (see configuration file)
+ *
+ * @chip:   address of the chip which is to be written
+ * @addr:   i2c data address within the chip
+ * @alen:   length of the i2c data address (1..2 bytes)
+ * @buffer: where to find the data to be written
+ * @len:    how much byte do we want to read
+ * @return: 0 in case of success
+ */
+int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len)
+{
+	return i2c_raw_write(base, chip, addr, buffer, len);
+}
+
+/*
+ * i2c_probe: - Test if a chip answers for a given i2c address
+ *
+ * @chip:   address of the chip which is searched for
+ * @return: 0 if a chip was found, -1 otherwhise
+ */
+int i2c_probe(u8 chip)
+{
+	u8 byte;
+	return i2c_read(chip, 0, 0, &byte, 1);
+}
diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c
index 21f6897269..5b6ea0e759 100644
--- a/drivers/i2c/tegra_i2c.c
+++ b/drivers/i2c/tegra_i2c.c
@@ -567,3 +567,17 @@ int i2c_set_bus_num(unsigned int bus)
 	return 0;
 }
 #endif
+
+int tegra_i2c_get_dvc_bus_num(void)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_SYS_MAX_I2C_BUS; i++) {
+		struct i2c_bus *bus = &i2c_controllers[i];
+
+		if (bus->inited && bus->is_dvc)
+			return i;
+	}
+
+	return -1;
+}
diff --git a/drivers/input/Makefile b/drivers/input/Makefile
index 1f4dad35b5..5c831b2611 100644
--- a/drivers/input/Makefile
+++ b/drivers/input/Makefile
@@ -26,10 +26,13 @@ include $(TOPDIR)/config.mk
 LIB	:= $(obj)libinput.o
 
 COBJS-$(CONFIG_I8042_KBD) += i8042.o
+COBJS-$(CONFIG_TEGRA2_KEYBOARD) += tegra-kbc.o
 ifdef CONFIG_PS2KBD
 COBJS-y += keyboard.o pc_keyb.o
 COBJS-$(CONFIG_PS2MULT) += ps2mult.o ps2ser.o
 endif
+COBJS-y += input.o
+COBJS-$(CONFIG_OF_CONTROL) += key_matrix.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
diff --git a/drivers/input/input.c b/drivers/input/input.c
new file mode 100644
index 0000000000..4eadd773b4
--- /dev/null
+++ b/drivers/input/input.c
@@ -0,0 +1,430 @@
+/*
+ * Translate key codes into ASCII
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2004 DENX Software Engineering, Wolfgang Denk, wd@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <stdio_dev.h>
+#include <input.h>
+#include <linux/input.h>
+
+enum {
+	/* These correspond to the lights on the keyboard */
+	FLAG_NUM_LOCK		= 1 << 0,
+	FLAG_CAPS_LOCK		= 1 << 1,
+	FLAG_SCROLL_LOCK	= 1 << 2,
+
+	/* Special flag ORed with key code to indicate release */
+	KEY_RELEASE		= 1 << 15,
+	KEY_MASK		= 0xfff,
+};
+
+/*
+ * These takes map key codes to ASCII. 0xff means no key, or special key.
+ * Three tables are provided - one for plain keys, one for when the shift
+ * 'modifier' key is pressed and one for when the ctrl modifier key is
+ * pressed.
+ */
+static const uchar kbd_plain_xlate[] = {
+	0xff, 0x1b, '1',  '2',  '3',  '4',  '5',  '6',
+	'7',  '8',  '9',  '0',  '-',  '=', '\b', '\t',	/* 0x00 - 0x0f */
+	'q',  'w',  'e',  'r',  't',  'y',  'u',  'i',
+	'o',  'p',  '[',  ']', '\r', 0xff,  'a',  's',  /* 0x10 - 0x1f */
+	'd',  'f',  'g',  'h',  'j',  'k',  'l',  ';',
+	'\'',  '`', 0xff, '\\', 'z',  'x',  'c',  'v',	/* 0x20 - 0x2f */
+	'b',  'n',  'm',  ',' ,  '.', '/', 0xff, 0xff, 0xff,
+	' ', 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 0x30 - 0x3f */
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  '7',
+	'8',  '9',  '-',  '4',  '5',  '6',  '+',  '1',	/* 0x40 - 0x4f */
+	'2',  '3',  '0',  '.', 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 0x50 - 0x5F */
+	'\r', 0xff, 0xff
+};
+
+static unsigned char kbd_shift_xlate[] = {
+	0xff, 0x1b, '!', '@', '#', '$', '%', '^',
+	'&', '*', '(', ')', '_', '+', '\b', '\t',	/* 0x00 - 0x0f */
+	'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I',
+	'O', 'P', '{', '}', '\r', 0xff, 'A', 'S',	/* 0x10 - 0x1f */
+	'D', 'F', 'G', 'H', 'J', 'K', 'L', ':',
+	'"', '~', 0xff, '|', 'Z', 'X', 'C', 'V',	/* 0x20 - 0x2f */
+	'B', 'N', 'M', '<', '>', '?', 0xff, 0xff, 0xff,
+	' ', 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 0x30 - 0x3f */
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, '7',
+	'8', '9', '-', '4', '5', '6', '+', '1',	/* 0x40 - 0x4f */
+	'2', '3', '0', '.', 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 0x50 - 0x5F */
+	'\r', 0xff, 0xff
+};
+
+static unsigned char kbd_ctrl_xlate[] = {
+	0xff, 0x1b, '1', 0x00, '3', '4', '5', 0x1E,
+	'7', '8', '9', '0', 0x1F, '=', '\b', '\t',	/* 0x00 - 0x0f */
+	0x11, 0x17, 0x05, 0x12, 0x14, 0x18, 0x15, 0x09,
+	0x0f, 0x10, 0x1b, 0x1d, '\n', 0xff, 0x01, 0x13,	/* 0x10 - 0x1f */
+	0x04, 0x06, 0x08, 0x09, 0x0a, 0x0b, 0x0c, ';',
+	'\'', '~', 0x00, 0x1c, 0x1a, 0x18, 0x03, 0x16,	/* 0x20 - 0x2f */
+	0x02, 0x0e, 0x0d, '<', '>', '?', 0xff, 0xff,
+	0xff, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 0x30 - 0x3f */
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, '7',
+	'8', '9', '-', '4', '5', '6', '+', '1',		/* 0x40 - 0x4f */
+	'2', '3', '0', '.', 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 0x50 - 0x5F */
+	'\r', 0xff, 0xff
+};
+
+
+int input_queue_ascii(struct input_config *config, int ch)
+{
+	if (config->fifo_in + 1 == INPUT_BUFFER_LEN) {
+		if (!config->fifo_out)
+			return -1; /* buffer full */
+		else
+			config->fifo_in = 0;
+	} else {
+		if (config->fifo_in + 1 == config->fifo_out)
+			return -1; /* buffer full */
+		config->fifo_in++;
+	}
+	config->fifo[config->fifo_in] = (uchar)ch;
+
+	return 0;
+}
+
+int input_tstc(struct input_config *config)
+{
+	if (config->fifo_in == config->fifo_out && config->read_keys) {
+		if (!(*config->read_keys)(config))
+			return 0;
+	}
+	return config->fifo_in != config->fifo_out;
+}
+
+int input_getc(struct input_config *config)
+{
+	int err = 0;
+
+	while (config->fifo_in == config->fifo_out) {
+		if (config->read_keys)
+			err = (*config->read_keys)(config);
+		if (err)
+			return -1;
+	}
+
+	if (++config->fifo_out == INPUT_BUFFER_LEN)
+		config->fifo_out = 0;
+
+	return config->fifo[config->fifo_out];
+}
+
+/**
+ * Process a modifier/special key press or release and decide which key
+ * translation array should be used as a result.
+ *
+ * TODO: Should keep track of modifier press/release
+ *
+ * @param config	Input state
+ * @param key		Key code to process
+ * @param release	0 if a press, 1 if a release
+ * @return pointer to keycode->ascii translation table that should be used
+ */
+static struct input_key_xlate *process_modifier(struct input_config *config,
+						int key, int release)
+{
+	struct input_key_xlate *table;
+	int flip = -1;
+	int i;
+
+	/* Start with the main table, and see what modifiers change it */
+	assert(config->num_tables > 0);
+	table = &config->table[0];
+	for (i = 1; i < config->num_tables; i++) {
+		struct input_key_xlate *tab = &config->table[i];
+
+		if (key == tab->left_keycode || key == tab->right_keycode)
+			table = tab;
+	}
+
+	/* Handle the lighted keys */
+	if (!release) {
+		switch (key) {
+		case KEY_SCROLLLOCK:
+			flip = FLAG_SCROLL_LOCK;
+			break;
+		case KEY_NUMLOCK:
+			flip = FLAG_NUM_LOCK;
+			break;
+		case KEY_CAPSLOCK:
+			flip = FLAG_CAPS_LOCK;
+			break;
+		}
+	}
+
+	if (flip != -1) {
+		int leds = 0;
+
+		config->leds ^= flip;
+		if (config->flags & FLAG_NUM_LOCK)
+			leds |= INPUT_LED_NUM;
+		if (config->flags & FLAG_CAPS_LOCK)
+			leds |= INPUT_LED_CAPS;
+		if (config->flags & FLAG_SCROLL_LOCK)
+			leds |= INPUT_LED_SCROLL;
+		config->leds = leds;
+	}
+
+	return table;
+}
+
+/**
+ * Search an int array for a key value
+ *
+ * @param array	Array to search
+ * @param count	Number of elements in array
+ * @param key	Key value to find
+ * @return element where value was first found, -1 if none
+ */
+static int array_search(int *array, int count, int key)
+{
+	int i;
+
+	for (i = 0; i < count; i++) {
+		if (array[i] == key)
+			return i;
+	}
+
+	return -1;
+}
+
+/**
+ * Sort an array so that those elements that exist in the ordering are
+ * first in the array, and in the same order as the ordering. The algorithm
+ * is O(count * ocount) and designed for small arrays.
+ *
+ * TODO: Move this to common / lib?
+ *
+ * @param dest		Array with elements to sort, also destination array
+ * @param count		Number of elements to sort
+ * @param order		Array containing ordering elements
+ * @param ocount	Number of ordering elements
+ * @return number of elements in dest that are in order (these will be at the
+ *	start of dest).
+ */
+static int sort_array_by_ordering(int *dest, int count, int *order,
+				   int ocount)
+{
+	int temp[count];
+	int dest_count;
+	int same;	/* number of elements which are the same */
+	int i;
+
+	/* setup output items, copy items to be sorted into our temp area */
+	memcpy(temp, dest, count * sizeof(*dest));
+	dest_count = 0;
+
+	/* work through the ordering, move over the elements we agree on */
+	for (i = 0; i < ocount; i++) {
+		if (array_search(temp, count, order[i]) != -1)
+			dest[dest_count++] = order[i];
+	}
+	same = dest_count;
+
+	/* now move over the elements that are not in the ordering */
+	for (i = 0; i < count; i++) {
+		if (array_search(order, ocount, temp[i]) == -1)
+			dest[dest_count++] = temp[i];
+	}
+	assert(dest_count == count);
+	return same;
+}
+
+/**
+ * Check a list of key codes against the previous key scan
+ *
+ * Given a list of new key codes, we check how many of these are the same
+ * as last time.
+ *
+ * @param config	Input state
+ * @param keycode	List of key codes to examine
+ * @param num_keycodes	Number of key codes
+ * @param same		Returns number of key codes which are the same
+ */
+static int input_check_keycodes(struct input_config *config,
+			   int keycode[], int num_keycodes, int *same)
+{
+	/* Select the 'plain' xlate table to start with */
+	if (!config->num_tables) {
+		debug("%s: No xlate tables: cannot decode keys\n", __func__);
+		return -1;
+	}
+
+	/* sort the keycodes into the same order as the previous ones */
+	*same = sort_array_by_ordering(keycode, num_keycodes,
+			config->prev_keycodes, config->num_prev_keycodes);
+
+	memcpy(config->prev_keycodes, keycode, num_keycodes * sizeof(int));
+	config->num_prev_keycodes = num_keycodes;
+
+	return *same != num_keycodes;
+}
+
+/**
+ * Convert a list of key codes into ASCII
+ *
+ * You must call input_check_keycodes() before this. It turns the keycode
+ * list into a list of ASCII characters which are ready to send to the
+ * input layer.
+ *
+ * Characters which were seen last time do not generate fresh ASCII output.
+ *
+ * @param config	Input state
+ * @param keycode	List of key codes to examine
+ * @param num_keycodes	Number of key codes
+ * @param same		Number of key codes which are the same
+ */
+static int input_keycodes_to_ascii(struct input_config *config,
+		int keycode[], int num_keycodes, char output_ch[], int same)
+{
+	struct input_key_xlate *table;
+	int ch_count;
+	int i;
+
+	table = &config->table[0];
+
+	/* deal with modifiers first */
+	for (i = 0; i < num_keycodes; i++) {
+		int key = keycode[i] & KEY_MASK;
+
+		if (key >= table->num_entries || table->xlate[key] == 0xff) {
+			table = process_modifier(config, key,
+					keycode[i] & KEY_RELEASE);
+		}
+	}
+
+	/* now find normal keys */
+	for (i = ch_count = 0; i < num_keycodes; i++) {
+		int key = keycode[i];
+
+		if (key < table->num_entries && i >= same) {
+			int ch = table->xlate[key];
+
+			/* If a normal key with an ASCII value, add it! */
+			if (ch != 0xff)
+				output_ch[ch_count++] = (uchar)ch;
+		}
+	}
+
+	/* ok, so return keys */
+	return ch_count;
+}
+
+int input_send_keycodes(struct input_config *config,
+			int keycode[], int num_keycodes)
+{
+	char ch[num_keycodes];
+	int count, i, same = 0;
+	int is_repeat = 0;
+	unsigned delay_ms;
+
+	config->modifiers = 0;
+	if (!input_check_keycodes(config, keycode, num_keycodes, &same)) {
+		/*
+		 * Same as last time - is it time for another repeat?
+		 * TODO(sjg@chromium.org) We drop repeats here and since
+		 * the caller may not call in again for a while, our
+		 * auto-repeat speed is not quite correct. We should
+		 * insert another character if we later realise that we
+		 * have missed a repeat slot.
+		 */
+		is_repeat = (int)get_timer(config->next_repeat_ms) >= 0;
+		if (!is_repeat)
+			return 0;
+	}
+
+	count = input_keycodes_to_ascii(config, keycode, num_keycodes,
+					ch, is_repeat ? 0 : same);
+	for (i = 0; i < count; i++)
+		input_queue_ascii(config, ch[i]);
+	delay_ms = is_repeat ?
+			config->repeat_rate_ms :
+			config->repeat_delay_ms;
+
+	config->next_repeat_ms = get_timer(0) + delay_ms;
+	return 0;
+}
+
+int input_add_table(struct input_config *config, int left_keycode,
+		    int right_keycode, const uchar *xlate, int num_entries)
+{
+	struct input_key_xlate *table;
+
+	if (config->num_tables == INPUT_MAX_MODIFIERS) {
+		debug("%s: Too many modifier tables\n", __func__);
+		return -1;
+	}
+
+	table = &config->table[config->num_tables++];
+	table->left_keycode = left_keycode;
+	table->right_keycode = right_keycode;
+	table->xlate = xlate;
+	table->num_entries = num_entries;
+
+	return 0;
+}
+
+int input_init(struct input_config *config, int leds, int repeat_delay_ms,
+	       int repeat_rate_ms)
+{
+	memset(config, '\0', sizeof(*config));
+	config->leds = leds;
+	config->repeat_delay_ms = repeat_delay_ms;
+	config->repeat_rate_ms = repeat_rate_ms;
+	if (input_add_table(config, -1, -1,
+			kbd_plain_xlate, ARRAY_SIZE(kbd_plain_xlate)) ||
+		input_add_table(config, KEY_LEFTSHIFT, KEY_RIGHTSHIFT,
+			kbd_shift_xlate, ARRAY_SIZE(kbd_shift_xlate)) ||
+		input_add_table(config, KEY_LEFTCTRL, KEY_RIGHTCTRL,
+			kbd_ctrl_xlate, ARRAY_SIZE(kbd_ctrl_xlate))) {
+		debug("%s: Could not add modifier tables\n", __func__);
+		return -1;
+	}
+
+	return 0;
+}
+
+int input_stdio_register(struct stdio_dev *dev)
+{
+	int error;
+
+	error = stdio_register(dev);
+
+	/* check if this is the standard input device */
+	if (!error && strcmp(getenv("stdin"), dev->name) == 0) {
+		/* reassign the console */
+		if (OVERWRITE_CONSOLE ||
+				console_assign(stdin, dev->name))
+			return -1;
+	}
+
+	return 0;
+}
diff --git a/drivers/input/key_matrix.c b/drivers/input/key_matrix.c
new file mode 100644
index 0000000000..84b898ff38
--- /dev/null
+++ b/drivers/input/key_matrix.c
@@ -0,0 +1,208 @@
+/*
+ * Manage Keyboard Matrices
+ *
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * (C) Copyright 2004 DENX Software Engineering, Wolfgang Denk, wd@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <fdtdec.h>
+#include <key_matrix.h>
+#include <malloc.h>
+#include <linux/input.h>
+
+/**
+ * Determine if the current keypress configuration can cause key ghosting
+ *
+ * We figure this out by seeing if we have two or more keys in the same
+ * column, as well as two or more keys in the same row.
+ *
+ * @param config	Keyboard matrix config
+ * @param keys		List of keys to check
+ * @param valid		Number of valid keypresses to check
+ * @return 0 if no ghosting is possible, 1 if it is
+ */
+static int has_ghosting(struct key_matrix *config, struct key_matrix_key *keys,
+			int valid)
+{
+	int key_in_same_col = 0, key_in_same_row = 0;
+	int i, j;
+
+	for (i = 0; i < valid; i++) {
+		/*
+		 * Find 2 keys such that one key is in the same row
+		 * and the other is in the same column as the i-th key.
+		 */
+		for (j = i + 1; j < valid; j++) {
+			if (keys[j].col == keys[i].col)
+				key_in_same_col = 1;
+			if (keys[j].row == keys[i].row)
+				key_in_same_row = 1;
+		}
+	}
+
+	if (key_in_same_col && key_in_same_row)
+		return 1;
+	else
+		return 0;
+}
+
+int key_matrix_decode(struct key_matrix *config, struct key_matrix_key keys[],
+		      int num_keys, int keycode[], int max_keycodes)
+{
+	const u8 *keymap;
+	int valid, upto;
+	int pos;
+
+	debug("%s: num_keys = %d\n", __func__, num_keys);
+	keymap = config->plain_keycode;
+	for (valid = upto = 0; upto < num_keys; upto++) {
+		struct key_matrix_key *key = &keys[upto];
+
+		debug("  valid=%d, row=%d, col=%d\n", key->valid, key->row,
+		      key->col);
+		if (!key->valid)
+			continue;
+		pos = key->row * config->num_cols + key->col;
+		if (config->fn_keycode && pos == config->fn_pos)
+			keymap = config->fn_keycode;
+
+		/* Convert the (row, col) values into a keycode */
+		if (valid < max_keycodes)
+			keycode[valid++] = keymap[pos];
+		debug("    keycode=%d\n", keymap[pos]);
+	}
+
+	/* For a ghost key config, ignore the keypresses for this iteration. */
+	if (valid >= 3 && has_ghosting(config, keys, valid)) {
+		valid = 0;
+		debug("    ghosting detected!\n");
+	}
+	debug("  %d valid keycodes found\n", valid);
+
+	return valid;
+}
+
+/**
+ * Create a new keycode map from some provided data
+ *
+ * This decodes a keycode map in the format used by the fdt, which is one
+ * word per entry, with the row, col and keycode encoded in that word.
+ *
+ * We create a (row x col) size byte array with each entry containing the
+ * keycode for that (row, col). We also search for map_keycode and return
+ * its position if found (this is used for finding the Fn key).
+ *
+ * @param config        Key matrix dimensions structure
+ * @param data          Keycode data
+ * @param len           Number of entries in keycode table
+ * @param map_keycode   Key code to find in the map
+ * @param pos           Returns position of map_keycode, if found, else -1
+ * @return map  Pointer to allocated map
+ */
+static uchar *create_keymap(struct key_matrix *config, u32 *data, int len,
+			    int map_keycode, int *pos)
+{
+	uchar *map;
+
+	if (pos)
+		*pos = -1;
+	map = (uchar *)calloc(1, config->key_count);
+	if (!map) {
+		debug("%s: failed to malloc %d bytes\n", __func__,
+			config->key_count);
+		return NULL;
+	}
+
+	for (; len >= sizeof(u32); data++, len -= 4) {
+		u32 tmp = fdt32_to_cpu(*data);
+		int key_code, row, col;
+		int entry;
+
+		row = (tmp >> 24) & 0xff;
+		col = (tmp >> 16) & 0xff;
+		key_code = tmp & 0xffff;
+		entry = row * config->num_cols + col;
+		map[entry] = key_code;
+		if (pos && map_keycode == key_code)
+			*pos = entry;
+	}
+
+	return map;
+}
+
+int key_matrix_decode_fdt(struct key_matrix *config, const void *blob,
+			  int node)
+{
+	const struct fdt_property *prop;
+	int offset;
+
+	/* Check each property name for ones that we understand */
+	for (offset = fdt_first_property_offset(blob, node);
+		      offset > 0;
+		      offset = fdt_next_property_offset(blob, offset)) {
+		const char *name;
+		int len;
+
+		prop = fdt_get_property_by_offset(blob, offset, NULL);
+		name = fdt_string(blob, fdt32_to_cpu(prop->nameoff));
+		len = strlen(name);
+
+		/* Name needs to match "1,<type>keymap" */
+		debug("%s: property '%s'\n", __func__, name);
+		if (strncmp(name, "1,", 2) || len < 8 ||
+		    strcmp(name + len - 6, "keymap"))
+			continue;
+
+		len -= 8;
+		if (len == 0) {
+			config->plain_keycode = create_keymap(config,
+				(u32 *)prop->data, fdt32_to_cpu(prop->len),
+				KEY_FN, &config->fn_pos);
+		} else if (0 == strncmp(name + 2, "fn-", len)) {
+			config->fn_keycode = create_keymap(config,
+				(u32 *)prop->data, fdt32_to_cpu(prop->len),
+				-1, NULL);
+		} else {
+			debug("%s: unrecognised property '%s'\n", __func__,
+			      name);
+		}
+	}
+	debug("%s: Decoded key maps %p, %p from fdt\n", __func__,
+	      config->plain_keycode, config->fn_keycode);
+
+	if (!config->plain_keycode) {
+		debug("%s: cannot find keycode-plain map\n", __func__);
+		return -1;
+	}
+
+	return 0;
+}
+
+int key_matrix_init(struct key_matrix *config, int rows, int cols)
+{
+	memset(config, '\0', sizeof(*config));
+	config->num_rows = rows;
+	config->num_cols = cols;
+	config->key_count = rows * cols;
+	assert(config->key_count > 0);
+
+	return 0;
+}
diff --git a/drivers/input/tegra-kbc.c b/drivers/input/tegra-kbc.c
new file mode 100644
index 0000000000..f164791bee
--- /dev/null
+++ b/drivers/input/tegra-kbc.c
@@ -0,0 +1,375 @@
+/*
+ *  (C) Copyright 2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <input.h>
+#include <key_matrix.h>
+#include <stdio_dev.h>
+#include <tegra-kbc.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/timer.h>
+#include <linux/input.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	KBC_MAX_GPIO		= 24,
+	KBC_MAX_KPENT		= 8,	/* size of keypress entry queue */
+};
+
+#define KBC_FIFO_TH_CNT_SHIFT		14
+#define KBC_DEBOUNCE_CNT_SHIFT		4
+#define KBC_CONTROL_FIFO_CNT_INT_EN	(1 << 3)
+#define KBC_CONTROL_KBC_EN		(1 << 0)
+#define KBC_INT_FIFO_CNT_INT_STATUS	(1 << 2)
+#define KBC_KPENT_VALID			(1 << 7)
+#define KBC_ST_STATUS			(1 << 3)
+
+enum {
+	KBC_DEBOUNCE_COUNT	= 2,
+	KBC_REPEAT_RATE_MS	= 30,
+	KBC_REPEAT_DELAY_MS	= 240,
+	KBC_CLOCK_KHZ		= 32,	/* Keyboard uses a 32KHz clock */
+};
+
+/* keyboard controller config and state */
+static struct keyb {
+	struct input_config input;	/* The input layer */
+	struct key_matrix matrix;	/* The key matrix layer */
+
+	struct kbc_tegra *kbc;		/* tegra keyboard controller */
+	unsigned char inited;		/* 1 if keyboard has been inited */
+	unsigned char first_scan;	/* 1 if this is our first key scan */
+
+	/*
+	 * After init we must wait a short time before polling the keyboard.
+	 * This gives the tegra keyboard controller time to react after reset
+	 * and lets us grab keys pressed during reset.
+	 */
+	unsigned int init_dly_ms;	/* Delay before we can read keyboard */
+	unsigned int start_time_ms;	/* Time that we inited (in ms) */
+	unsigned int last_poll_ms;	/* Time we should last polled */
+	unsigned int next_repeat_ms;	/* Next time we repeat a key */
+} config;
+
+/**
+ * reads the keyboard fifo for current keypresses
+ *
+ * @param config	Keyboard config
+ * @param fifo		Place to put fifo results
+ * @param max_keycodes	Maximum number of key codes to put in the fifo
+ * @return number of items put into fifo
+ */
+static int tegra_kbc_find_keys(struct keyb *config, int *fifo,
+			       int max_keycodes)
+{
+	struct key_matrix_key keys[KBC_MAX_KPENT], *key;
+	u32 kp_ent = 0;
+	int i;
+
+	for (key = keys, i = 0; i < KBC_MAX_KPENT; i++, key++) {
+		/* Get next word */
+		if (!(i & 3))
+			kp_ent = readl(&config->kbc->kp_ent[i / 4]);
+
+		key->valid = (kp_ent & KBC_KPENT_VALID) != 0;
+		key->row = (kp_ent >> 3) & 0xf;
+		key->col = kp_ent & 0x7;
+
+		/* Shift to get next entry */
+		kp_ent >>= 8;
+	}
+	return key_matrix_decode(&config->matrix, keys, KBC_MAX_KPENT, fifo,
+				 max_keycodes);
+}
+
+/**
+ * Process all the keypress sequences in fifo and send key codes
+ *
+ * The fifo contains zero or more keypress sets. Each set
+ * consists of from 1-8 keycodes, representing the keycodes which
+ * were simultaneously pressed during that scan.
+ *
+ * This function works through each set and generates ASCII characters
+ * for each. Not that one set may produce more than one ASCII characters -
+ * for example holding down 'd' and 'f' at the same time will generate
+ * two ASCII characters.
+ *
+ * Note: if fifo_cnt is 0, we will tell the input layer that no keys are
+ * pressed.
+ *
+ * @param config	Keyboard config
+ * @param fifo_cnt	Number of entries in the keyboard fifo
+ */
+static void process_fifo(struct keyb *config, int fifo_cnt)
+{
+	int fifo[KBC_MAX_KPENT];
+	int cnt = 0;
+
+	/* Always call input_send_keycodes() at least once */
+	do {
+		if (fifo_cnt)
+			cnt = tegra_kbc_find_keys(config, fifo, KBC_MAX_KPENT);
+
+		input_send_keycodes(&config->input, fifo, cnt);
+	} while (--fifo_cnt > 0);
+}
+
+/**
+ * Check the keyboard controller and emit ASCII characters for any keys that
+ * are pressed.
+ *
+ * @param config	Keyboard config
+ */
+static void check_for_keys(struct keyb *config)
+{
+	int fifo_cnt;
+
+	if (!config->first_scan &&
+			get_timer(config->last_poll_ms) < KBC_REPEAT_RATE_MS)
+		return;
+	config->last_poll_ms = get_timer(0);
+	config->first_scan = 0;
+
+	/*
+	 * Once we get here we know the keyboard has been scanned. So if there
+	 * scan waiting for us, we know that nothing is held down.
+	 */
+	fifo_cnt = (readl(&config->kbc->interrupt) >> 4) & 0xf;
+	process_fifo(config, fifo_cnt);
+}
+
+/**
+ * In order to detect keys pressed on boot, wait for the hardware to
+ * complete scanning the keys. This includes time to transition from
+ * Wkup mode to Continous polling mode and the repoll time. We can
+ * deduct the time that's already elapsed.
+ *
+ * @param config	Keyboard config
+ */
+static void kbd_wait_for_fifo_init(struct keyb *config)
+{
+	if (!config->inited) {
+		unsigned long elapsed_time;
+		long delay_ms;
+
+		elapsed_time = get_timer(config->start_time_ms);
+		delay_ms = config->init_dly_ms - elapsed_time;
+		if (delay_ms > 0) {
+			udelay(delay_ms * 1000);
+			debug("%s: delay %ldms\n", __func__, delay_ms);
+		}
+
+		config->inited = 1;
+	}
+}
+
+/**
+ * Check the tegra keyboard, and send any keys that are pressed.
+ *
+ * This is called by input_tstc() and input_getc() when they need more
+ * characters
+ *
+ * @param input		Input configuration
+ * @return 1, to indicate that we have something to look at
+ */
+int tegra_kbc_check(struct input_config *input)
+{
+	kbd_wait_for_fifo_init(&config);
+	check_for_keys(&config);
+
+	return 1;
+}
+
+/**
+ * Test if keys are available to be read
+ *
+ * @return 0 if no keys available, 1 if keys are available
+ */
+static int kbd_tstc(void)
+{
+	/* Just get input to do this for us */
+	return input_tstc(&config.input);
+}
+
+/**
+ * Read a key
+ *
+ * TODO: U-Boot wants 0 for no key, but Ctrl-@ is a valid key...
+ *
+ * @return ASCII key code, or 0 if no key, or -1 if error
+ */
+static int kbd_getc(void)
+{
+	/* Just get input to do this for us */
+	return input_getc(&config.input);
+}
+
+/* configures keyboard GPIO registers to use the rows and columns */
+static void config_kbc_gpio(struct kbc_tegra *kbc)
+{
+	int i;
+
+	for (i = 0; i < KBC_MAX_GPIO; i++) {
+		u32 row_cfg, col_cfg;
+		u32 r_shift = 5 * (i % 6);
+		u32 c_shift = 4 * (i % 8);
+		u32 r_mask = 0x1f << r_shift;
+		u32 c_mask = 0xf << c_shift;
+		u32 r_offs = i / 6;
+		u32 c_offs = i / 8;
+
+		row_cfg = readl(&kbc->row_cfg[r_offs]);
+		col_cfg = readl(&kbc->col_cfg[c_offs]);
+
+		row_cfg &= ~r_mask;
+		col_cfg &= ~c_mask;
+
+		if (i < config.matrix.num_rows) {
+			row_cfg |= ((i << 1) | 1) << r_shift;
+		} else {
+			col_cfg |= (((i - config.matrix.num_rows) << 1) | 1)
+					<< c_shift;
+		}
+
+		writel(row_cfg, &kbc->row_cfg[r_offs]);
+		writel(col_cfg, &kbc->col_cfg[c_offs]);
+	}
+}
+
+/**
+ * Start up the keyboard device
+ */
+static void tegra_kbc_open(void)
+{
+	struct kbc_tegra *kbc = config.kbc;
+	unsigned int scan_period;
+	u32 val;
+
+	/*
+	 * We will scan at twice the keyboard repeat rate, so that there is
+	 * always a scan ready when we check it in check_for_keys().
+	 */
+	scan_period = KBC_REPEAT_RATE_MS / 2;
+	writel(scan_period * KBC_CLOCK_KHZ, &kbc->rpt_dly);
+	writel(scan_period * KBC_CLOCK_KHZ, &kbc->init_dly);
+	/*
+	 * Before reading from the keyboard we must wait for the init_dly
+	 * plus the rpt_delay, plus 2ms for the row scan time.
+	 */
+	config.init_dly_ms = scan_period * 2 + 2;
+
+	val = KBC_DEBOUNCE_COUNT << KBC_DEBOUNCE_CNT_SHIFT;
+	val |= 1 << KBC_FIFO_TH_CNT_SHIFT;	/* fifo interrupt threshold */
+	val |= KBC_CONTROL_KBC_EN;		/* enable */
+	writel(val, &kbc->control);
+
+	config.start_time_ms = get_timer(0);
+	config.last_poll_ms = config.next_repeat_ms = get_timer(0);
+	config.first_scan = 1;
+}
+
+/**
+ * Set up the tegra keyboard. This is called by the stdio device handler
+ *
+ * We want to do this init when the keyboard is actually used rather than
+ * at start-up, since keyboard input may not currently be selected.
+ *
+ * Once the keyboard starts there will be a period during which we must
+ * wait for the keyboard to init. We do this only when a key is first
+ * read - see kbd_wait_for_fifo_init().
+ *
+ * @return 0 if ok, -ve on error
+ */
+static int init_tegra_keyboard(void)
+{
+#ifdef CONFIG_OF_CONTROL
+	int	node;
+
+	node = fdtdec_next_compatible(gd->fdt_blob, 0,
+					  COMPAT_NVIDIA_TEGRA20_KBC);
+	if (node < 0) {
+		debug("%s: cannot locate keyboard node\n", __func__);
+		return node;
+	}
+	config.kbc = (struct kbc_tegra *)fdtdec_get_addr(gd->fdt_blob,
+		       node, "reg");
+	if ((fdt_addr_t)config.kbc == FDT_ADDR_T_NONE) {
+		debug("%s: No keyboard register found\n", __func__);
+		return -1;
+	}
+
+	/* Decode the keyboard matrix information (16 rows, 8 columns) */
+	if (key_matrix_init(&config.matrix, 16, 8)) {
+		debug("%s: Could not init key matrix\n", __func__);
+		return -1;
+	}
+	if (key_matrix_decode_fdt(&config.matrix, gd->fdt_blob, node)) {
+		debug("%s: Could not decode key matrix from fdt\n", __func__);
+		return -1;
+	}
+	if (config.matrix.fn_keycode) {
+		if (input_add_table(&config.input, KEY_FN, -1,
+				    config.matrix.fn_keycode,
+				    config.matrix.key_count))
+			return -1;
+	}
+#else
+#error "Tegra keyboard driver requires FDT definitions"
+#endif
+
+	/* Set up pin mux and enable the clock */
+	funcmux_select(PERIPH_ID_KBC, FUNCMUX_DEFAULT);
+	clock_enable(PERIPH_ID_KBC);
+	config_kbc_gpio(config.kbc);
+
+	tegra_kbc_open();
+	debug("%s: Tegra keyboard ready\n", __func__);
+
+	return 0;
+}
+
+int drv_keyboard_init(void)
+{
+	struct stdio_dev dev;
+
+	if (input_init(&config.input, 0, KBC_REPEAT_DELAY_MS,
+			KBC_REPEAT_RATE_MS)) {
+		debug("%s: Cannot set up input\n", __func__);
+		return -1;
+	}
+	config.input.read_keys = tegra_kbc_check;
+
+	memset(&dev, '\0', sizeof(dev));
+	strcpy(dev.name, "tegra-kbc");
+	dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+	dev.getc = kbd_getc;
+	dev.tstc = kbd_tstc;
+	dev.start = init_tegra_keyboard;
+
+	/* Register the device. init_tegra_keyboard() will be called soon */
+	return input_stdio_register(&dev);
+}
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index a70970784c..fdf6813149 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -35,10 +35,14 @@ COBJS-$(CONFIG_PDSP188x) += pdsp188x.o
 COBJS-$(CONFIG_STATUS_LED) += status_led.o
 COBJS-$(CONFIG_TWL4030_LED) += twl4030_led.o
 COBJS-$(CONFIG_PMIC) += pmic_core.o
+COBJS-$(CONFIG_DIALOG_PMIC) += pmic_dialog.o
 COBJS-$(CONFIG_PMIC_FSL) += pmic_fsl.o
 COBJS-$(CONFIG_PMIC_I2C) += pmic_i2c.o
 COBJS-$(CONFIG_PMIC_SPI) += pmic_spi.o
 COBJS-$(CONFIG_PMIC_MAX8998) += pmic_max8998.o
+COBJS-$(CONFIG_PMIC_MAX8997) += pmic_max8997.o
+COBJS-$(CONFIG_RDA_FACTORY) += factory.o
+COBJS-$(CONFIG_RDA_PRDINFO) += prdinfo.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
diff --git a/drivers/misc/factory.c b/drivers/misc/factory.c
new file mode 100644
index 0000000000..addf32ea1d
--- /dev/null
+++ b/drivers/misc/factory.c
@@ -0,0 +1,715 @@
+#include <linux/types.h>
+#include <common.h>
+#include <errno.h>
+#include <nand.h>
+#include <pdl.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <part.h>
+#include <mmc/mmcpart.h>
+#include <jffs2/load_kernel.h>
+#include <asm/arch/rda_iomap.h>
+#include <asm/arch/factory.h>
+#include <asm/arch/rda_sys.h>
+
+enum FACTORY_DATA_STATUS {
+	FACTORY_DATA_UNKNOWN = 0,
+	FACTORY_DATA_INVALID,
+	FACTORY_DATA_VALID,
+};
+
+struct ap_factory_config_v0 {
+	u32 magic;
+	u8 lcd_name[128];
+	u8 clock_config[1024];
+	u8 reserved[1024];
+};
+
+const static char factory_sector_name[] = "factorydata";
+
+static enum FACTORY_DATA_STATUS factory_data_status
+	= FACTORY_DATA_UNKNOWN;
+
+static struct factory_data_sector factory_data
+	__attribute__((__aligned__(32)));
+
+static int factory_data_is_valid(u8 *data, u32 size)
+{
+	struct factory_data_sector *sector = (void *)data;
+	struct ap_factory_config *config = (void *)sector->ap_factory_data;
+	int valid = 0;
+	u32 crc, crc_calc;
+	u32 version;
+
+	BUILD_BUG_ON(sizeof(struct ap_factory_config) > RDA_AP_FACT_LEN);
+
+	memcpy(&version, &config->version, sizeof(version));
+	printf("Factory version: 0x%08X\n", version);
+	if ((version & 0xFFFF0000) == AP_FACTORY_MARK_VERSION) {
+		u32 crc_size = RDA_FACT_TOTAL_LEN;
+		/* Factory structure version the current version */
+		if (version == AP_FACTORY_VERSION_NUMBER) {
+			valid = 1;
+		/* Factory structure version is old, but we can support it */
+		} else if (version == AP_FACTORY_VERSION_1_NUMBER) {
+			crc_size = AP_FACTORY_VERSION_1_LEN;
+			valid = 1;
+		} else {
+			/* Factory structure version is invalid */
+			printf("Factory version is unknown\n");
+			printf("Current code version: 0x%08X\n",
+					AP_FACTORY_VERSION_NUMBER);
+		}
+
+		if(size < crc_size) {
+			valid = 0;
+			printf("Factory data size is too small.\n");
+		}
+
+		if(valid) {
+			memcpy(&crc, &config->crc, sizeof(crc));
+			memset(&config->crc, 0, sizeof(crc));
+			crc_calc = crc32(0, (u8 *)sector, crc_size);
+			memcpy(&config->crc, &crc, sizeof(crc));
+			if (crc == crc_calc) {
+				printf("Factory CRC is OK %#x\n", crc);
+			} else {
+				printf("ERROR: Bad factory CRC, got %#x, expect %#x\n",
+								crc_calc, crc);
+				valid = 0;
+			}
+		}
+	} else {
+		printf("No valid factory data\n");
+	}
+
+	return valid;
+}
+
+extern int find_dev_and_part(const char *id, struct mtd_device **dev,
+			     u8 *part_num, struct part_info **part);
+
+static int nand_mtd_factory_init(struct mtd_info **minfo,
+		struct part_info **pinfo)
+{
+	struct mtd_info *nand;
+	struct mtd_device *dev;
+	struct part_info *part;
+	u8 pnum;
+	int ret;
+	u32 block_size, page_size;
+	u32 block_nums;
+
+	ret = find_dev_and_part(factory_sector_name, &dev, &pnum, &part);
+	if (ret) {
+		printf("unknown partition name '%s'\n", factory_sector_name);
+		return ret;
+	} else if (dev->id->type != MTD_DEV_TYPE_NAND) {
+		printf("mtd dev type error: %d\n", dev->id->type);
+		return -EIO;
+	}
+	printf("found factorydata part '%s' offset: 0x%llx length: 0x%llx\n",
+	       part->name, part->offset, part->size);
+
+	nand = &nand_info[dev->id->num];
+	block_size = nand->erasesize;
+	page_size = nand->writesize;
+
+	printf("nand info: blockSize=%d pageSize=%d\n", block_size, page_size);
+
+	if (block_size < sizeof(struct factory_data_sector)) {
+		printf("Invalid block size: %d (should >= %d)\n",
+				block_size, sizeof(struct factory_data_sector));
+		hang();
+	}
+	block_nums = part->size / nand->erasesize;
+	if (block_nums < 2) {
+		printf("partition for factorydata is too small");
+		printf(" at least two blocks\n");
+		hang();
+	}
+	*minfo = nand;
+	*pinfo = part;
+	return 0;
+}
+
+static int nand_mtd_load_factory(u8 *dst)
+{
+	struct mtd_info *nand;
+	struct part_info *part;
+	size_t size;
+	int ret;
+	u64 offs;
+	u32 block_size;
+	u32 bad_blocks = 0;
+
+	ret = nand_mtd_factory_init(&nand, &part);
+	if (ret)
+		return ret;
+
+	block_size = nand->erasesize;
+	size = sizeof(struct factory_data_sector);
+	offs = part->offset;
+
+	printf("read 0x%x bytes from '%s' offset: 0x%llx\n",
+	       size, part->name, offs);
+	ret = nand_read_skip_bad_new(nand, offs, &size, dst, &bad_blocks);
+	if (ret) {
+		printf("nand read fail\n");
+		return ret;
+	}
+
+	if (factory_data_is_valid(dst, size))
+		return 0;
+
+	printf("Try the backup copy of factory data\n");
+
+	size = sizeof(struct factory_data_sector);
+	offs = part->offset + (bad_blocks + 1) * block_size;
+
+	printf("read 0x%x bytes from '%s' offset: 0x%llx\n",
+	       size, part->name, offs);
+
+	ret = nand_read_skip_bad_new(nand, offs, &size, dst, &bad_blocks);
+	if (ret) {
+		printf("nand read fail\n");
+		return ret;
+	}
+
+	if (factory_data_is_valid(dst, size))
+		return 0;
+
+	return -EIO;
+}
+
+static void factory_data_prepare_write(u8 *buf)
+{
+	struct factory_data_sector *sector = (void *)buf;
+	struct ap_factory_config *config = (void *)sector->ap_factory_data;
+	u32 version = AP_FACTORY_VERSION_NUMBER;
+	u32 crc_size = sizeof(*sector);
+	u32 crc;
+
+	if(config->version == AP_FACTORY_VERSION_1_NUMBER)
+		crc_size = AP_FACTORY_VERSION_1_LEN;
+	else
+		memcpy(&config->version, &version, sizeof(config->version));
+
+	memset(&config->crc, 0, sizeof(config->crc));
+	crc = crc32(0, (u8 *)sector, crc_size);
+	memcpy(&config->crc, &crc, sizeof(config->crc));
+}
+
+static void factory_data_dump(u8 *data, size_t size, int flash)
+{
+	printf("dump factory data from %s :\n", flash ? "flash" : "tools");
+	rda_dump_buf((char *)data, size);
+}
+
+static int factory_data_check(struct mtd_info *nand, u32 offs, u8 *data)
+{
+	int ret = 0;;
+	u8 *dst;
+	size_t size;
+	u32 bad_blocks = 0;
+	int i;
+
+	if (pdl_dbg_rw_check == 0 && pdl_dbg_factory_part == 0)
+		return 0;
+
+	printf("Check the factory data just written ...\n");
+
+	dst = malloc(sizeof(struct factory_data_sector));
+	if (dst == NULL) {
+		printf("Failed to malloc buffer %d bytes\n",
+				sizeof(struct factory_data_sector));
+		return -ENOMEM;
+	}
+
+	size = sizeof(struct factory_data_sector);
+
+	printf("read 0x%x bytes offset: 0x%08x\n", size, offs);
+	ret = nand_read_skip_bad_new(nand, offs, &size, dst, &bad_blocks);
+	if (ret) {
+		printf("nand read fail\n");
+		goto _exit;
+	}
+
+	if (pdl_dbg_factory_part)
+		factory_data_dump(dst, sizeof(struct factory_data_sector), 1);
+
+	if (pdl_dbg_rw_check) {
+		for (i = 0; i < sizeof(struct factory_data_sector); ++i) {
+			if (data[i] != dst[i])
+				break;
+		}
+		if (i < sizeof(struct factory_data_sector)) {
+			ret = -EIO;
+			size = sizeof(struct factory_data_sector) - i;
+			if (size > 2048)
+				size = 2048;
+			printf("*** CHECK FAILURE: offset=%d\n", i);
+			printf("==> Before %p is:\n", data);
+			rda_dump_buf((char *)&data[i], size);
+			printf("==> After  %p is:\n", dst);
+			rda_dump_buf((char *)&dst[i], size);
+		}
+	}
+
+_exit:
+	free(dst);
+	return ret;
+}
+
+static loff_t factory_backup_offs = 0;
+
+static int write_factory(nand_info_t *nand, loff_t offset, size_t size,
+			 loff_t max_limit, u8 *buf)
+{
+	nand_erase_options_t opts;
+	struct nand_chip *chip = nand->priv;
+	int ret;
+
+	if (chip->bbt_erase_shift == 0) {
+		if(mtd_mod_by_eb(offset, nand) != 0)
+			return -EINVAL;
+	} else {
+		if ((offset & (nand->erasesize -1)) != 0)
+			return -EINVAL;
+	}
+
+	if (chip->bbt_erase_shift == 0) {
+		while (offset < max_limit) {
+			if (nand_block_isbad (nand,
+		 		mtd_div_by_eb(offset, nand) * nand->erasesize)) {
+				printf ("Skip bad block 0x%08llx\n",
+		 			(loff_t)mtd_div_by_eb(offset, nand) * nand->erasesize);
+				offset += nand->erasesize;
+				continue;
+			} else {
+				break;
+			}
+		}
+	} else {
+		while (offset < max_limit) {
+			if (nand_block_isbad (nand,
+				offset & ~(nand->erasesize - 1))) {
+				printf ("Skip bad block 0x%08llx\n",
+					offset & ~(nand->erasesize - 1));
+				offset += nand->erasesize;
+				continue;
+			} else {
+				break;
+			}
+		}
+	}
+
+	if (offset >= max_limit) {
+		printf("no good block for factory data\n");
+		return -EIO;
+	}
+	/* erase the factory partition */
+	memset(&opts, 0, sizeof(opts));
+	opts.offset = offset;
+	opts.length = nand->erasesize;
+	opts.jffs2 = 0;
+	opts.quiet = 0;
+	printf("erase 0x%x bytes to  offset: 0x%08x\n",
+		(unsigned int)opts.length,
+		(unsigned int)opts.offset);
+	ret = nand_erase_opts(nand, &opts);
+	if (ret) {
+		printf("nand erase fail\n");
+		return ret;
+	}
+
+	ret = nand_write(nand, offset, &size, buf);
+	if (ret) {
+		printf("nand write fail\n");
+		return ret;
+	} else {
+		/* Check the factory data in flash */
+		ret = factory_data_check(nand, offset, buf);
+		if (ret)
+			return ret;
+	}
+
+	factory_backup_offs = offset + nand->erasesize;
+	return 0;
+}
+
+static int nand_mtd_write_factory(u8 *buf)
+{
+	struct mtd_info *nand;
+	struct part_info *part;
+	int ret;
+	size_t size;
+	u64 offs;
+	loff_t max_limit;
+
+	ret = nand_mtd_factory_init(&nand, &part);
+	if (ret)
+		return ret;
+
+	max_limit = part->offset + part->size;
+
+	/* Dump the data from tools */
+	if (pdl_dbg_factory_part)
+		factory_data_dump(buf, sizeof(struct factory_data_sector), 0);
+
+	/* Set version and crc */
+	factory_data_prepare_write(buf);
+
+	/* write back the factory */
+	size = sizeof(struct factory_data_sector);
+	offs = part->offset;
+	printf("write 0x%x bytes to '%s' offset: 0x%llx\n",
+		size, part->name, offs);
+
+	ret = write_factory(nand, offs, size, max_limit, buf);
+	if (ret) {
+		printf("factorydata write fail\n");
+		return ret;
+	}
+
+	printf("Write the backup copy of factory data\n");
+
+	size = sizeof(struct factory_data_sector);
+	offs = factory_backup_offs;
+	printf("write 0x%x bytes to '%s' offset: 0x%llx\n",
+		size, part->name, offs);
+
+	ret = write_factory(nand, offs, size, max_limit, buf);
+	if (ret) {
+		printf("factorydata backup write fail, ");
+		printf("and only one copy in factorydata\n");
+	}
+	return 0;
+}
+
+#define BACKUP_FACTORY_START	128	/* 128 mmc blocks, 64KB */
+int emmc_load_factory(u8 *dst)
+{
+	disk_partition_t *ptn;
+	block_dev_desc_t *mmc_blkdev;
+	struct mmc *mmc;
+	u64 offset;
+	u64 backup_offset;
+	size_t size;
+	int blksz_shift;
+
+	mmc_blkdev = get_dev_by_name(CONFIG_MMC_DEV_NAME);
+	if (mmc_blkdev)
+		mmc = container_of(mmc_blkdev, struct mmc, block_dev);
+	else
+		return -1;
+
+	if (!mmc) {
+		printf("mmc doesn't exist");
+		return -1;
+	}
+
+	ptn = partition_find_ptn("factorydata");
+	if(!ptn) {
+		printf("mmc partition table doesn't exist");
+		return -1;
+	}
+
+	blksz_shift = LOG2(ptn->blksz);
+	offset = (u64)ptn->start << blksz_shift;
+	size = sizeof(struct factory_data_sector);
+	printf("read 0x%x bytes from '%s' offset: 0x%08llx\n",
+	       size, ptn->name, offset);
+	if (mmc_read(mmc, offset, dst, size) <= 0) {
+		printf("mmc read fail\n");
+		return -EIO;
+	}
+
+	if (factory_data_is_valid(dst, size))
+		return 0;
+
+	printf("Try the backup copy of factory data\n");
+
+	size = sizeof(struct factory_data_sector);
+	backup_offset = offset + (BACKUP_FACTORY_START << blksz_shift);
+
+	printf("read 0x%x bytes from '%s' offset: 0x%08llx\n",
+	       size, ptn->name, backup_offset);
+
+	if (mmc_read(mmc, backup_offset, dst, size) <= 0) {
+		printf("mmc read backup factorydata fail\n");
+		return -EIO;
+	}
+
+	if (factory_data_is_valid(dst, size))
+		return 0;
+
+	return -EIO;
+}
+
+static int emmc_write_factory(u8 *buf)
+{
+	disk_partition_t *ptn;
+	block_dev_desc_t *mmc_blkdev;
+	struct mmc *mmc;
+	u64 offset;
+	u64 backup_offset;
+	size_t size;
+	int blksz_shift;
+
+	mmc_blkdev = get_dev_by_name(CONFIG_MMC_DEV_NAME);
+	if (mmc_blkdev)
+		mmc = container_of(mmc_blkdev, struct mmc, block_dev);
+	else
+		return -1;
+
+	if (!mmc) {
+		printf("mmc doesn't exist");
+		return -1;
+	}
+
+	ptn = partition_find_ptn("factorydata");
+	if (!ptn) {
+		printf("mmc partition table doesn't exist");
+		return -1;
+	}
+
+	/* Dump the data from tools */
+	if (pdl_dbg_factory_part)
+		factory_data_dump(buf, sizeof(struct factory_data_sector), 0);
+
+	/* Set version and crc */
+	factory_data_prepare_write(buf);
+
+	/* write back the factory */
+	size = sizeof(struct factory_data_sector);
+	blksz_shift = LOG2(ptn->blksz);
+	offset = (u64)ptn->start << blksz_shift;
+	printf("write 0x%x bytes to '%s' offset: 0x%llx\n",
+		size, ptn->name, offset);
+
+	if (mmc_write(mmc, offset, buf, size) <= 0) {
+		printf("factorydata write fail\n");
+		return -EIO;
+	}
+
+	printf("Write the backup copy of factory data\n");
+
+	size = sizeof(struct factory_data_sector);
+	backup_offset = offset + (BACKUP_FACTORY_START << blksz_shift);
+	printf("write 0x%x bytes to '%s' offset: 0x%llx\n",
+		size, ptn->name, backup_offset);
+
+	if (mmc_write(mmc, backup_offset, buf, size) <= 0) {
+		printf("factorydata backup write fail, ");
+		printf("and only one copy in factorydata\n");
+	}
+	return 0;
+}
+
+int factory_copy_from_mem(const u8 *buf)
+{
+	u8 *data = (u8 *)image_get_data((const image_header_t *)buf);
+	size_t size = image_get_data_size((const image_header_t *)buf);
+
+	if (factory_data_is_valid(data, size)) {
+		printf("Calibration data is valid, copying to memory\n");
+		memcpy(&factory_data, data, sizeof(factory_data));
+		factory_data_status = FACTORY_DATA_VALID;
+		return 0;
+	} else {
+		printf("Calibration data is invalid\n");
+		return 1;
+	}
+}
+
+int factory_load(void)
+{
+	int ret = 0;
+
+	if (factory_data_status != FACTORY_DATA_UNKNOWN) {
+		printf("Factory already loaded\n");
+		return ret;
+	}
+
+	printf("Load factory from flash ...\n");
+
+	if (rda_media_get() == MEDIA_MMC)
+		ret = emmc_load_factory((u8 *)&factory_data);
+	else
+		ret = nand_mtd_load_factory((u8 *)&factory_data);
+	if (ret) {
+		printf("Load Failed\n");
+		memset(&factory_data, 0, sizeof(factory_data));
+		factory_data_status = FACTORY_DATA_INVALID;
+		return ret;
+	}
+
+	printf("Done\n");
+	factory_data_status = FACTORY_DATA_VALID;
+	return ret;
+}
+
+const unsigned char* factory_get_lcd_name(void)
+{
+	struct ap_factory_config *config =
+		(void *)factory_data.ap_factory_data;
+	factory_load();
+	return config->lcd_name;
+}
+
+const unsigned char* factory_get_bootlogo_name(void)
+{
+	struct ap_factory_config *config =
+		(void *)factory_data.ap_factory_data;
+	factory_load();
+	return config->bootlogo_name;
+}
+
+const unsigned char* factory_get_ap_factory(void)
+{
+	factory_load();
+	return factory_data.ap_factory_data;
+}
+
+const unsigned char* factory_get_modem_factory(void)
+{
+	factory_load();
+	return factory_data.modem_factory_data;
+}
+
+const unsigned char* factory_get_modem_calib(void)
+{
+	factory_load();
+	return factory_data.modem_calib_data;
+}
+
+const unsigned char* factory_get_modem_ext_calib(void)
+{
+	factory_load();
+	return factory_data.modem_ext_calib_data;
+}
+
+unsigned long factory_get_all(unsigned char *buf)
+{
+	struct ap_factory_config *config =
+		(void *)factory_data.ap_factory_data;
+	if (!buf)
+		return 0;
+
+	factory_load();
+	memcpy(buf, &factory_data, sizeof(factory_data));
+
+	if(config->version == AP_FACTORY_VERSION_1_NUMBER)
+		return AP_FACTORY_VERSION_1_LEN;
+
+	return sizeof(factory_data);
+}
+
+int factory_set_ap_factory(unsigned char *data)
+{
+	factory_load();
+	memcpy(factory_data.ap_factory_data, data,
+			sizeof(factory_data.ap_factory_data));
+	return 0;
+}
+
+int factory_set_modem_calib(unsigned char *data)
+{
+	factory_load();
+	memcpy(factory_data.modem_calib_data, data,
+			sizeof(factory_data.modem_calib_data));
+	return 0;
+}
+
+int factory_set_modem_ext_calib(unsigned char *data)
+{
+	factory_load();
+	memcpy(factory_data.modem_ext_calib_data, data,
+			sizeof(factory_data.modem_ext_calib_data));
+	return 0;
+}
+
+int factory_set_modem_factory(unsigned char *data)
+{
+	factory_load();
+	memcpy(factory_data.modem_factory_data, data,
+			sizeof(factory_data.modem_factory_data));
+	return 0;
+}
+
+int factory_burn(void)
+{
+	if (rda_media_get() == MEDIA_MMC)
+		return emmc_write_factory((u8 *)&factory_data);
+	else
+		return nand_mtd_write_factory((u8 *)&factory_data);
+}
+
+int factory_update_modem_calib(unsigned char *data)
+{
+	factory_set_modem_calib(data);
+	return factory_burn();
+}
+
+int factory_update_modem_ext_calib(unsigned char *data)
+{
+	factory_set_modem_ext_calib(data);
+	return factory_burn();
+}
+
+int factory_update_modem_factory(unsigned char *data)
+{
+	factory_set_modem_factory(data);
+	return factory_burn();
+}
+
+int factory_update_ap_factory(unsigned char *data)
+{
+	factory_set_ap_factory(data);
+	return factory_burn();
+}
+
+int factory_update_all(unsigned char *data, unsigned long size)
+{
+	if (!factory_data_is_valid(data, size)) {
+		printf("factory data is invalid.\n");
+		return -EINVAL;
+	}
+	factory_load();
+	memcpy(&factory_data, data, sizeof(factory_data));
+	return factory_burn();
+}
+
+
+/* message rx/tx for PC calib tool and u-boot */
+int factory_get_ap_calib_msg(unsigned int *id, unsigned int *size, unsigned char *data)
+{
+	struct ap_calib_message *msg = (struct ap_calib_message *)RDA_AP_CALIB_MSG_ADDR;
+	if (msg->magic == RDA_AP_CALIB_MSG_MAGIC &&
+		!(msg->id & 0x80000000) ) {
+		*id = msg->id;
+		if (size)
+			*size = msg->size;
+		if (data)
+			memcpy(data, msg->data, msg->size);
+		/* clear */
+		memset(msg, 0, RDA_AP_CALIB_MSG_LEN);
+		flush_dcache_range(RDA_AP_CALIB_MSG_ADDR, RDA_AP_CALIB_MSG_ADDR+RDA_AP_CALIB_MSG_LEN);
+		return 0;
+	}
+	return -1;
+}
+
+int factory_set_ap_calib_msg(unsigned int id, unsigned int size, unsigned char *data)
+{
+	struct ap_calib_message *msg = (struct ap_calib_message *)RDA_AP_CALIB_MSG_ADDR;
+	msg->magic = RDA_AP_CALIB_MSG_MAGIC;
+	msg->id = id;
+	msg->size = size;
+	if (data)
+		memcpy(msg->data, data, size);
+	flush_dcache_range(RDA_AP_CALIB_MSG_ADDR, RDA_AP_CALIB_MSG_ADDR+RDA_AP_CALIB_MSG_LEN);
+	return 0;
+}
+
diff --git a/drivers/misc/pmic_dialog.c b/drivers/misc/pmic_dialog.c
new file mode 100644
index 0000000000..e97af1d1d0
--- /dev/null
+++ b/drivers/misc/pmic_dialog.c
@@ -0,0 +1,37 @@
+/*
+ *  Copyright (C) 2011 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <pmic.h>
+#include <dialog_pmic.h>
+
+int pmic_dialog_init(void)
+{
+	struct pmic *p = get_pmic();
+	static const char name[] = "DIALOG_PMIC";
+
+	p->name = name;
+	p->number_of_regs = DIALOG_NUM_OF_REGS;
+
+	p->interface = PMIC_I2C;
+	p->hw.i2c.addr = CONFIG_SYS_DIALOG_PMIC_I2C_ADDR;
+	p->hw.i2c.tx_num = 1;
+	p->bus = I2C_PMIC;
+
+	return 0;
+}
diff --git a/drivers/misc/pmic_max8997.c b/drivers/misc/pmic_max8997.c
new file mode 100644
index 0000000000..62dbc05311
--- /dev/null
+++ b/drivers/misc/pmic_max8997.c
@@ -0,0 +1,43 @@
+/*
+ *  Copyright (C) 2012 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pmic.h>
+#include <max8997_pmic.h>
+
+int pmic_init(void)
+{
+	struct pmic *p = get_pmic();
+	static const char name[] = "MAX8997_PMIC";
+
+	puts("Board PMIC init\n");
+
+	p->name = name;
+	p->interface = PMIC_I2C;
+	p->number_of_regs = PMIC_NUM_OF_REGS;
+	p->hw.i2c.addr = MAX8997_I2C_ADDR;
+	p->hw.i2c.tx_num = 1;
+	p->bus = I2C_PMIC;
+
+	return 0;
+}
diff --git a/drivers/misc/prdinfo.c b/drivers/misc/prdinfo.c
new file mode 100644
index 0000000000..8f42df776e
--- /dev/null
+++ b/drivers/misc/prdinfo.c
@@ -0,0 +1,344 @@
+#include <linux/types.h>
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <nand.h>
+#include <pdl.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <part.h>
+#include <mmc/mmcpart.h>
+#include <asm/arch/hwcfg.h>
+#include <asm/arch/mtdparts_def.h>
+#include <asm/arch/rda_sys.h>
+#include <asm/arch/prdinfo.h>
+
+int nand_read_partition(const char *part_name, unsigned char *data,
+		size_t size, size_t *actual_len);
+int nand_write_partition(const char *part_name, unsigned char *data,
+		size_t size);
+int nand_erase_partition(const char *part_name);
+int emmc_erase_partition(const char *part_name);
+int emmc_read_partition(const char *part_name, unsigned char *data, size_t size,
+			size_t *actual_len);
+int emmc_write_partition(const char *part_name, unsigned char *data, size_t size);
+
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+static unsigned char prdinfo_buf[PRDINFO_TOTAL_SIZE]
+			__attribute__((__aligned__(CONFIG_SYS_CACHELINE_SIZE)));
+#else
+static unsigned char prdinfo_buf[PRDINFO_TOTAL_SIZE]
+			__attribute__((__aligned__(32)));
+#endif
+int prdinfo_load(void)
+{
+	int ret = 0;
+	static int loaded = 0;
+	unsigned char *data = prdinfo_buf;
+	struct prdinfo *info = (struct prdinfo *)data;
+	size_t actual_sz = 0;
+	size_t total_sz = PRDINFO_TOTAL_SIZE;
+	uint32_t crc = 0, new_crc = 0;
+
+	if(loaded)
+		return 0;
+
+	if (rda_media_get() == MEDIA_MMC)
+		ret = emmc_read_partition(PRDINFO_PART_NAME, data,
+						total_sz, &actual_sz);
+	else
+		ret = nand_read_partition(PRDINFO_PART_NAME, data,
+						total_sz, &actual_sz);
+
+	if(ret)
+		return -1;
+
+	/* crc verify */
+	memcpy(&crc, &data[PRDINFO_CRC_OFFSET], sizeof(uint32_t));
+	new_crc = crc32(0, data, total_sz - sizeof(uint32_t));
+
+	/* if data is invalid, fill by zero */
+	if(crc == 0 || crc == 0xffffffff || crc != new_crc)
+		memset((void *)data, 0, total_sz);
+
+	if(info->pdl_image_count > PDL_IMAGE_MAX_NUM)
+		info->pdl_image_count = PDL_IMAGE_MAX_NUM;
+
+	loaded = 1;
+	return 0;
+}
+
+int prdinfo_save(void)
+{
+	int ret = 0;
+	unsigned char *data = prdinfo_buf;
+	size_t total_sz = PRDINFO_TOTAL_SIZE;
+	uint32_t *crc_p;
+
+	crc_p = (uint32_t *)&data[PRDINFO_CRC_OFFSET];
+	*crc_p = crc32(0, data, total_sz - sizeof(uint32_t));
+
+	if (rda_media_get() == MEDIA_MMC) {
+		ret = emmc_write_partition(PRDINFO_PART_NAME, data, total_sz);
+	} else {
+		ret = nand_erase_partition(PRDINFO_PART_NAME);
+		if(!ret)
+			ret = nand_write_partition(PRDINFO_PART_NAME, data, total_sz);
+	}
+
+	return ret;
+}
+
+int prdinfo_update_all(char *buf, unsigned long sz)
+{
+	if(sz != PRDINFO_TOTAL_SIZE) {
+		printf("%s: size %lu is invaild.\n", __func__, sz);
+		return -1;
+	}
+	memcpy(prdinfo_buf, buf, sz);
+	prdinfo_save();
+	return 0;
+}
+
+int prdinfo_set_data(struct prdinfo *info)
+{
+	memcpy(prdinfo_buf, (void *)info, sizeof(struct prdinfo));
+	prdinfo_save();
+	return 0;
+}
+
+int prdinfo_get_data(struct prdinfo *info)
+{
+	if(prdinfo_load())
+		return -1;
+	memcpy((void *)info, prdinfo_buf, sizeof(struct prdinfo));
+	return 0;
+}
+
+static int prdinfo_clear(void)
+{
+	memset(prdinfo_buf, 0, PRDINFO_TOTAL_SIZE);
+
+	if (rda_media_get() == MEDIA_MMC)
+		return emmc_erase_partition(PRDINFO_PART_NAME);
+	else
+		return nand_erase_partition(PRDINFO_PART_NAME);
+}
+
+void prdinfo_dump(void)
+{
+	int i;
+	struct prdinfo *info = (struct prdinfo *)prdinfo_buf;
+
+	printf("product infomation:\n");
+	printf("  Download      : %s\n", info->pdl_result ? "OK" : "None");
+	for(i = 0; i < info->pdl_image_count; i++) {
+		int r = info->pdl_images[i].result;
+		printf("    %10s: %s\n", info->pdl_images[i].name,
+				r ? "OK" : "None");
+	}
+	printf("  Calibration   : %s\n", info->cali_result ? "OK" : "None");
+	printf("  Autocall Test : %s\n", info->autocall_result ? "OK" : "None");
+	printf("  Factory Test  : %s\n", info->factorytest_result ? "OK" : "None");
+	printf("  IMEI Write    : %s\n", info->imei_result ? "OK" : "None");
+	printf("  PSN Write     : %s\n", info->psn_result ? "OK" : "None");
+	printf("  MBSN Write    : %s\n", info->mbsn_result ? "OK" : "None");
+	printf("  MACAddr Write : %s\n", info->macaddr_result ? "OK" : "None");
+	printf("  BTAddr Write  : %s\n", info->btaddr_result ? "OK" : "None");
+	printf("  FTM TAG       : %#x\n", info->factory_tag);
+	printf("  Reserve Data  : ");
+	for(i = 0; i < 10; i++) {
+		printf("0x%x ", ((u32)info->reserve[i]) & 0xff);
+	}
+	printf("\n");
+}
+
+int prdinfo_set_pdl_result(uint8_t rt, uint32_t ftm_tag)
+{
+	int ret = 0;
+	struct prdinfo *info = (struct prdinfo *)prdinfo_buf;
+
+	ret = prdinfo_load();
+	if(!ret) {
+		info->pdl_result = !!rt;
+		info->factory_tag = ftm_tag ? FACTORY_TAG_NUM : 0;
+		ret = prdinfo_save();
+	}
+	return ret;
+}
+
+int prdinfo_set_cali_result(uint8_t rt)
+{
+	int ret = 0;
+	struct prdinfo *info = (struct prdinfo *)prdinfo_buf;
+
+	ret = prdinfo_load();
+	if(!ret) {
+		info->cali_result = !!rt;
+		ret = prdinfo_save();
+	}
+	return ret;
+}
+
+int prdinfo_set_autocall_result(uint8_t rt)
+{
+	int ret = 0;
+	struct prdinfo *info = (struct prdinfo *)prdinfo_buf;
+
+	ret = prdinfo_load();
+	if(!ret) {
+		info->autocall_result = !!rt;
+		ret = prdinfo_save();
+	}
+	return ret;
+}
+
+int prdinfo_set_coupling_result(uint8_t rt)
+{
+	int ret = 0;
+	struct prdinfo *info = (struct prdinfo *)prdinfo_buf;
+
+	ret = prdinfo_load();
+	if(!ret) {
+		info->reserve[0] = !!rt;
+		ret = prdinfo_save();
+	}
+	return ret;
+}
+
+int prdinfo_set_factorytest_result(uint8_t rt)
+{
+	int ret = 0;
+	struct prdinfo *info = (struct prdinfo *)prdinfo_buf;
+
+	ret = prdinfo_load();
+	if(!ret) {
+		info->factorytest_result = !!rt;
+		ret = prdinfo_save();
+	}
+	return ret;
+}
+
+int prdinfo_init(char *image_list)
+{
+	int ret = 0;
+	int i, len;
+	char *buff, *p, *q;
+	struct prdinfo *info = (struct prdinfo *)prdinfo_buf;
+
+	/* clear old data first */
+	prdinfo_clear();
+
+	len = strlen(image_list);
+	if(len < 1) {
+		printf("%s: name list is empty!\n", __func__);
+		return -1;
+	}
+
+	buff = malloc(len + 1);
+	if(!buff)
+		return -1;
+	memcpy(buff, image_list, len+1);
+
+	/* get image names */
+	p = buff;
+	i = 0;
+	while(1) {
+		q = strstr(p, ",");
+		if(q) *q = '\0';
+
+		if(strlen(p) > 0) {
+			strncpy(info->pdl_images[i++].name, p, PDL_IMAGE_NAME_LEN-1);
+			if(i >= PDL_IMAGE_MAX_NUM) break;
+		}
+
+		if(!q) break;
+
+		p = q + 1;
+		if(*p == '\0') break;
+	}
+	info->pdl_image_count = i;
+
+	/* write data to flash */
+	ret = prdinfo_save();
+
+	free(buff);
+	return ret;
+
+}
+
+int prdinfo_set_pdl_image_download_result(char *image_name, uint8_t dl_rt)
+{
+	int ret = 0;
+	int update = 0;
+	int i;
+	struct prdinfo *info = (struct prdinfo *)prdinfo_buf;
+
+	ret = prdinfo_load();
+	if(ret)
+		return ret;
+
+	for(i = 0; i < info->pdl_image_count; i++) {
+		if(strcmp(image_name, info->pdl_images[i].name) == 0) {
+			if(info->pdl_images[i].result != !!dl_rt) {
+				info->pdl_images[i].result = !!dl_rt;
+				update = 1;
+			}
+			break;
+		}
+	}
+
+	if(update) {
+		ret = prdinfo_save();
+		printf("part '%s', set download result '%s'\n", image_name,
+				(!!dl_rt) ? "success" : "fail");
+	}
+
+	return ret;
+}
+
+uint32_t prdinfo_get_factory_tag(void)
+{
+	uint32_t tag = 0;
+	struct prdinfo *info = (struct prdinfo *)prdinfo_buf;
+
+	if(!prdinfo_load())
+		tag = info->factory_tag;
+	return tag;
+}
+
+
+/****************************************************************************/
+/****************************************************************************/
+/****************************************************************************/
+#ifdef CONFIG_CMD_PRDINFO
+int do_dump_prdinfo(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
+{
+	prdinfo_dump();
+	return CMD_RET_SUCCESS;
+}
+
+int do_rda_check_factory_tag(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if(prdinfo_get_factory_tag() == FACTORY_TAG_NUM){
+		enum rda_bm_type bm;
+		char str[2];
+
+		bm = rda_bm_get();
+		if(bm == RDA_BM_NORMAL) {
+			rda_bm_set(RDA_BM_FACTORY);
+			sprintf(str, "%1d", RDA_BM_FACTORY);
+			setenv("bootmode", str);
+			printf("Found factory tag, change bootmode to %1d\n", RDA_BM_FACTORY);
+		}
+	}
+	return 0;
+}
+
+U_BOOT_CMD(prdinfo, 1, 1, do_dump_prdinfo,
+	"dump product infomation", "");
+
+U_BOOT_CMD(rdachkfactag ,    1,    1,     do_rda_check_factory_tag,
+	"check FTM tag 0xFAC12345 in 'misc' part", "");
+
+#endif
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index c245352aca..40c79b3f30 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -25,6 +25,14 @@ include $(TOPDIR)/config.mk
 
 LIB	:= $(obj)libmmc.o
 
+ifdef CONFIG_SPL_BUILD 
+ifdef CONFIG_SPL_EMMC_LOAD
+COBJS-y	+= mmc_spl_load.o
+endif 
+else
+COBJS-$(CONFIG_GENERIC_MMC) += mmc_write.o
+endif
+
 COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
 COBJS-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
 COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
@@ -39,10 +47,15 @@ COBJS-$(CONFIG_MXS_MMC) += mxsmmc.o
 COBJS-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o
 COBJS-$(CONFIG_PXA_MMC) += pxa_mmc.o
 COBJS-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
-COBJS-$(CONFIG_S5P_MMC) += s5p_mmc.o
+COBJS-$(CONFIG_RDA_MMC) += rda_mmc.o
+COBJS-$(CONFIG_RDA_MMC_LEGACY) += rda_mmc_legacy.o
 COBJS-$(CONFIG_SDHCI) += sdhci.o
+COBJS-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
 COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o
 COBJS-$(CONFIG_TEGRA2_MMC) += tegra2_mmc.o
+ifndef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_PARTITIONS) += mmc_parts.o
+endif
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c
index 08fc5c1d3e..8d59d46c64 100644
--- a/drivers/mmc/bfin_sdh.c
+++ b/drivers/mmc/bfin_sdh.c
@@ -256,7 +256,6 @@ int bfin_mmc_init(bd_t *bis)
 	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 	mmc->f_max = get_sclk();
 	mmc->f_min = mmc->f_max >> 9;
-	mmc->block_dev.part_type = PART_TYPE_DOS;
 
 	mmc->b_max = 0;
 
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index a2f35e3e99..07370b5729 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -307,19 +307,56 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 #else
 	esdhc_write32(&regs->xfertyp, xfertyp);
 #endif
+
+	/* Mask all irqs */
+	esdhc_write32(&regs->irqsigen, 0);
+
 	/* Wait for the command to complete */
-	while (!(esdhc_read32(&regs->irqstat) & IRQSTAT_CC))
+	while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
 		;
 
 	irqstat = esdhc_read32(&regs->irqstat);
 	esdhc_write32(&regs->irqstat, irqstat);
 
+	/* Reset CMD and DATA portions on error */
+	if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) {
+		esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
+			      SYSCTL_RSTC);
+		while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
+			;
+
+		if (data) {
+			esdhc_write32(&regs->sysctl,
+				      esdhc_read32(&regs->sysctl) |
+				      SYSCTL_RSTD);
+			while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
+				;
+		}
+	}
+
 	if (irqstat & CMD_ERR)
 		return COMM_ERR;
 
 	if (irqstat & IRQSTAT_CTOE)
 		return TIMEOUT;
 
+	/* Workaround for ESDHC errata ENGcm03648 */
+	if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
+		int timeout = 2500;
+
+		/* Poll on DATA0 line for cmd with busy signal for 250 ms */
+		while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
+					PRSSTAT_DAT0)) {
+			udelay(100);
+			timeout--;
+		}
+
+		if (timeout <= 0) {
+			printf("Timeout waiting for DAT0 to go high!\n");
+			return TIMEOUT;
+		}
+	}
+
 	/* Copy the response to the response buffer */
 	if (cmd->resp_type & MMC_RSP_136) {
 		u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 596732e80e..1d09a56f3e 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -4,23 +4,7 @@
  *
  * Based vaguely on the Linux code
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <config.h>
@@ -31,6 +15,10 @@
 #include <malloc.h>
 #include <linux/list.h>
 #include <div64.h>
+#include "mmc_private.h"
+
+//#define CONFIG_MMC_TRACE
+//#define CONFIG_MMC_DDR_MODE
 
 /* Set block count limit because of 16 bit register limit on some hardware*/
 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
@@ -40,118 +28,58 @@
 static struct list_head mmc_devices;
 static int cur_dev_num = -1;
 
-int __board_mmc_getcd(struct mmc *mmc) {
-	return -1;
-}
-
-int board_mmc_getcd(struct mmc *mmc)__attribute__((weak,
-	alias("__board_mmc_getcd")));
+/*
+*	Manufacturer ID list
+*/
+static const struct mmc_manufacturers mmc_manuf_ids[] = {
+	{MMC_MFR_TOSHIBA, "Toshiba"},
+	{MMC_MFR_SAMSUNG, "Samsung"},
+	{MMC_MFR_SANDISK, "SanDisk"},
+	{MMC_MFR_GIGADEVICE, "GigaDevice"},
+	{MMC_MFR_HYNIX, "Hynix"},
+	{MMC_MFR_MICRON, "Micron"},
+	{MMC_MFR_MICRON1, "Micron"},
+	{0x0, "Unknown"}
+};
 
-#ifdef CONFIG_MMC_BOUNCE_BUFFER
-static int mmc_bounce_need_bounce(struct mmc_data *orig)
+int __weak board_mmc_getwp(struct mmc *mmc)
 {
-	ulong addr, len;
-
-	if (orig->flags & MMC_DATA_READ)
-		addr = (ulong)orig->dest;
-	else
-		addr = (ulong)orig->src;
-
-	if (addr % ARCH_DMA_MINALIGN) {
-		debug("MMC: Unaligned data destination address %08lx!\n", addr);
-		return 1;
-	}
-
-	len = (ulong)(orig->blocksize * orig->blocks);
-	if (len % ARCH_DMA_MINALIGN) {
-		debug("MMC: Unaligned data destination length %08lx!\n", len);
-		return 1;
-	}
-
-	return 0;
+	return -1;
 }
 
-static int mmc_bounce_buffer_start(struct mmc_data *backup,
-					struct mmc_data *orig)
+int mmc_getwp(struct mmc *mmc)
 {
-	ulong origlen, len;
-	void *buffer;
+	int wp;
 
-	if (!orig)
-		return 0;
-
-	if (!mmc_bounce_need_bounce(orig))
-		return 0;
+	wp = board_mmc_getwp(mmc);
 
-	memcpy(backup, orig, sizeof(struct mmc_data));
-
-	origlen = orig->blocksize * orig->blocks;
-	len = roundup(origlen, ARCH_DMA_MINALIGN);
-	buffer = memalign(ARCH_DMA_MINALIGN, len);
-	if (!buffer) {
-		puts("MMC: Error allocating MMC bounce buffer!\n");
-		return 1;
-	}
-
-	if (orig->flags & MMC_DATA_READ) {
-		orig->dest = buffer;
-	} else {
-		memcpy(buffer, orig->src, origlen);
-		orig->src = buffer;
+	if (wp < 0) {
+		if (mmc->getwp)
+			wp = mmc->getwp(mmc);
+		else
+			wp = 0;
 	}
 
-	return 0;
+	return wp;
 }
 
-static void mmc_bounce_buffer_stop(struct mmc_data *backup,
-					struct mmc_data *orig)
-{
-	ulong len;
-
-	if (!orig)
-		return;
-
-	if (!mmc_bounce_need_bounce(backup))
-		return;
-
-	if (backup->flags & MMC_DATA_READ) {
-		len = backup->blocksize * backup->blocks;
-		memcpy(backup->dest, orig->dest, len);
-		free(orig->dest);
-		orig->dest = backup->dest;
-	} else {
-		free((void *)orig->src);
-		orig->src = backup->src;
-	}
-
-	return;
-
+int __board_mmc_getcd(struct mmc *mmc) {
+	return -1;
 }
-#else
-static inline int mmc_bounce_buffer_start(struct mmc_data *backup,
-					struct mmc_data *orig) { return 0; }
-static inline void mmc_bounce_buffer_stop(struct mmc_data *backup,
-					struct mmc_data *orig) { }
-#endif
+
+int board_mmc_getcd(struct mmc *mmc)__attribute__((weak,
+	alias("__board_mmc_getcd")));
 
 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 {
-	struct mmc_data backup;
 	int ret;
 
-	memset(&backup, 0, sizeof(backup));
-
-	ret = mmc_bounce_buffer_start(&backup, data);
-	if (ret)
-		return ret;
-
 #ifdef CONFIG_MMC_TRACE
 	int i;
 	u8 *ptr;
 
 	printf("CMD_SEND:%d\n", cmd->cmdidx);
 	printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
-	printf("\t\tFLAG\t\t\t %d\n", cmd->flags);
 	ret = mmc->send_cmd(mmc, cmd, data);
 	switch (cmd->resp_type) {
 		case MMC_RSP_NONE:
@@ -197,7 +125,6 @@ int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 #else
 	ret = mmc->send_cmd(mmc, cmd, data);
 #endif
-	mmc_bounce_buffer_stop(&backup, data);
 	return ret;
 }
 
@@ -213,7 +140,6 @@ int mmc_send_status(struct mmc *mmc, int timeout)
 	cmd.resp_type = MMC_RSP_R1;
 	if (!mmc_host_is_spi(mmc))
 		cmd.cmdarg = mmc->rca << 16;
-	cmd.flags = 0;
 
 	do {
 		err = mmc_send_cmd(mmc, &cmd, NULL);
@@ -223,8 +149,10 @@ int mmc_send_status(struct mmc *mmc, int timeout)
 			     MMC_STATE_PRG)
 				break;
 			else if (cmd.response[0] & MMC_STATUS_MASK) {
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 				printf("Status Error: 0x%08X\n",
 					cmd.response[0]);
+#endif
 				return COMM_ERR;
 			}
 		} else if (--retries < 0)
@@ -238,10 +166,14 @@ int mmc_send_status(struct mmc *mmc, int timeout)
 	status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
 	printf("CURR STATE:%d\n", status);
 #endif
-	if (!timeout) {
+	if (timeout <= 0) {
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 		printf("Timeout waiting card ready\n");
+#endif
 		return TIMEOUT;
 	}
+	if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR)
+		return SWITCH_ERR;
 
 	return 0;
 }
@@ -250,10 +182,14 @@ int mmc_set_blocklen(struct mmc *mmc, int len)
 {
 	struct mmc_cmd cmd;
 
+#ifdef CONFIG_MMC_DDR_MODE
+	if (mmc->card_caps & MMC_MODE_DDR_52MHz)
+		return 0;
+#endif
+
 	cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
 	cmd.resp_type = MMC_RSP_R1;
 	cmd.cmdarg = len;
-	cmd.flags = 0;
 
 	return mmc_send_cmd(mmc, &cmd, NULL);
 }
@@ -270,175 +206,15 @@ struct mmc *find_mmc_device(int dev_num)
 			return m;
 	}
 
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 	printf("MMC Device %d not found\n", dev_num);
+#endif
 
 	return NULL;
 }
 
-static ulong mmc_erase_t(struct mmc *mmc, ulong start, lbaint_t blkcnt)
-{
-	struct mmc_cmd cmd;
-	ulong end;
-	int err, start_cmd, end_cmd;
-
-	if (mmc->high_capacity)
-		end = start + blkcnt - 1;
-	else {
-		end = (start + blkcnt - 1) * mmc->write_bl_len;
-		start *= mmc->write_bl_len;
-	}
-
-	if (IS_SD(mmc)) {
-		start_cmd = SD_CMD_ERASE_WR_BLK_START;
-		end_cmd = SD_CMD_ERASE_WR_BLK_END;
-	} else {
-		start_cmd = MMC_CMD_ERASE_GROUP_START;
-		end_cmd = MMC_CMD_ERASE_GROUP_END;
-	}
-
-	cmd.cmdidx = start_cmd;
-	cmd.cmdarg = start;
-	cmd.resp_type = MMC_RSP_R1;
-	cmd.flags = 0;
-
-	err = mmc_send_cmd(mmc, &cmd, NULL);
-	if (err)
-		goto err_out;
-
-	cmd.cmdidx = end_cmd;
-	cmd.cmdarg = end;
-
-	err = mmc_send_cmd(mmc, &cmd, NULL);
-	if (err)
-		goto err_out;
-
-	cmd.cmdidx = MMC_CMD_ERASE;
-	cmd.cmdarg = SECURE_ERASE;
-	cmd.resp_type = MMC_RSP_R1b;
-
-	err = mmc_send_cmd(mmc, &cmd, NULL);
-	if (err)
-		goto err_out;
-
-	return 0;
-
-err_out:
-	puts("mmc erase failed\n");
-	return err;
-}
-
-static unsigned long
-mmc_berase(int dev_num, unsigned long start, lbaint_t blkcnt)
-{
-	int err = 0;
-	struct mmc *mmc = find_mmc_device(dev_num);
-	lbaint_t blk = 0, blk_r = 0;
-
-	if (!mmc)
-		return -1;
-
-	if ((start % mmc->erase_grp_size) || (blkcnt % mmc->erase_grp_size))
-		printf("\n\nCaution! Your devices Erase group is 0x%x\n"
-			"The erase range would be change to 0x%lx~0x%lx\n\n",
-		       mmc->erase_grp_size, start & ~(mmc->erase_grp_size - 1),
-		       ((start + blkcnt + mmc->erase_grp_size)
-		       & ~(mmc->erase_grp_size - 1)) - 1);
-
-	while (blk < blkcnt) {
-		blk_r = ((blkcnt - blk) > mmc->erase_grp_size) ?
-			mmc->erase_grp_size : (blkcnt - blk);
-		err = mmc_erase_t(mmc, start + blk, blk_r);
-		if (err)
-			break;
-
-		blk += blk_r;
-	}
-
-	return blk;
-}
-
-static ulong
-mmc_write_blocks(struct mmc *mmc, ulong start, lbaint_t blkcnt, const void*src)
-{
-	struct mmc_cmd cmd;
-	struct mmc_data data;
-	int timeout = 1000;
-
-	if ((start + blkcnt) > mmc->block_dev.lba) {
-		printf("MMC: block number 0x%lx exceeds max(0x%lx)\n",
-			start + blkcnt, mmc->block_dev.lba);
-		return 0;
-	}
-
-	if (blkcnt > 1)
-		cmd.cmdidx = MMC_CMD_WRITE_MULTIPLE_BLOCK;
-	else
-		cmd.cmdidx = MMC_CMD_WRITE_SINGLE_BLOCK;
-
-	if (mmc->high_capacity)
-		cmd.cmdarg = start;
-	else
-		cmd.cmdarg = start * mmc->write_bl_len;
-
-	cmd.resp_type = MMC_RSP_R1;
-	cmd.flags = 0;
-
-	data.src = src;
-	data.blocks = blkcnt;
-	data.blocksize = mmc->write_bl_len;
-	data.flags = MMC_DATA_WRITE;
-
-	if (mmc_send_cmd(mmc, &cmd, &data)) {
-		printf("mmc write failed\n");
-		return 0;
-	}
-
-	/* SPI multiblock writes terminate using a special
-	 * token, not a STOP_TRANSMISSION request.
-	 */
-	if (!mmc_host_is_spi(mmc) && blkcnt > 1) {
-		cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
-		cmd.cmdarg = 0;
-		cmd.resp_type = MMC_RSP_R1b;
-		cmd.flags = 0;
-		if (mmc_send_cmd(mmc, &cmd, NULL)) {
-			printf("mmc fail to send stop cmd\n");
-			return 0;
-		}
-	}
-
-	/* Waiting for the ready status */
-	if (mmc_send_status(mmc, timeout))
-		return 0;
-
-	return blkcnt;
-}
-
-static ulong
-mmc_bwrite(int dev_num, ulong start, lbaint_t blkcnt, const void*src)
-{
-	lbaint_t cur, blocks_todo = blkcnt;
-
-	struct mmc *mmc = find_mmc_device(dev_num);
-	if (!mmc)
-		return 0;
-
-	if (mmc_set_blocklen(mmc, mmc->write_bl_len))
-		return 0;
-
-	do {
-		cur = (blocks_todo > mmc->b_max) ?  mmc->b_max : blocks_todo;
-		if(mmc_write_blocks(mmc, start, cur, src) != cur)
-			return 0;
-		blocks_todo -= cur;
-		start += cur;
-		src += cur * mmc->write_bl_len;
-	} while (blocks_todo > 0);
-
-	return blkcnt;
-}
-
-int mmc_read_blocks(struct mmc *mmc, void *dst, ulong start, lbaint_t blkcnt)
+static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
+			   lbaint_t blkcnt)
 {
 	struct mmc_cmd cmd;
 	struct mmc_data data;
@@ -454,7 +230,6 @@ int mmc_read_blocks(struct mmc *mmc, void *dst, ulong start, lbaint_t blkcnt)
 		cmd.cmdarg = start * mmc->read_bl_len;
 
 	cmd.resp_type = MMC_RSP_R1;
-	cmd.flags = 0;
 
 	data.dest = dst;
 	data.blocks = blkcnt;
@@ -468,9 +243,10 @@ int mmc_read_blocks(struct mmc *mmc, void *dst, ulong start, lbaint_t blkcnt)
 		cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
 		cmd.cmdarg = 0;
 		cmd.resp_type = MMC_RSP_R1b;
-		cmd.flags = 0;
 		if (mmc_send_cmd(mmc, &cmd, NULL)) {
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 			printf("mmc fail to send stop cmd\n");
+#endif
 			return 0;
 		}
 	}
@@ -478,7 +254,7 @@ int mmc_read_blocks(struct mmc *mmc, void *dst, ulong start, lbaint_t blkcnt)
 	return blkcnt;
 }
 
-static ulong mmc_bread(int dev_num, ulong start, lbaint_t blkcnt, void *dst)
+static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst)
 {
 	lbaint_t cur, blocks_todo = blkcnt;
 
@@ -490,8 +266,10 @@ static ulong mmc_bread(int dev_num, ulong start, lbaint_t blkcnt, void *dst)
 		return 0;
 
 	if ((start + blkcnt) > mmc->block_dev.lba) {
-		printf("MMC: block number 0x%lx exceeds max(0x%lx)\n",
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+		printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
 			start + blkcnt, mmc->block_dev.lba);
+#endif
 		return 0;
 	}
 
@@ -510,7 +288,7 @@ static ulong mmc_bread(int dev_num, ulong start, lbaint_t blkcnt, void *dst)
 	return blkcnt;
 }
 
-int mmc_go_idle(struct mmc* mmc)
+static int mmc_go_idle(struct mmc *mmc)
 {
 	struct mmc_cmd cmd;
 	int err;
@@ -520,7 +298,6 @@ int mmc_go_idle(struct mmc* mmc)
 	cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
 	cmd.cmdarg = 0;
 	cmd.resp_type = MMC_RSP_NONE;
-	cmd.flags = 0;
 
 	err = mmc_send_cmd(mmc, &cmd, NULL);
 
@@ -532,8 +309,7 @@ int mmc_go_idle(struct mmc* mmc)
 	return 0;
 }
 
-int
-sd_send_op_cond(struct mmc *mmc)
+static int sd_send_op_cond(struct mmc *mmc)
 {
 	int timeout = 1000;
 	int err;
@@ -543,7 +319,6 @@ sd_send_op_cond(struct mmc *mmc)
 		cmd.cmdidx = MMC_CMD_APP_CMD;
 		cmd.resp_type = MMC_RSP_R1;
 		cmd.cmdarg = 0;
-		cmd.flags = 0;
 
 		err = mmc_send_cmd(mmc, &cmd, NULL);
 
@@ -584,7 +359,6 @@ sd_send_op_cond(struct mmc *mmc)
 		cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
 		cmd.resp_type = MMC_RSP_R3;
 		cmd.cmdarg = 0;
-		cmd.flags = 0;
 
 		err = mmc_send_cmd(mmc, &cmd, NULL);
 
@@ -600,66 +374,92 @@ sd_send_op_cond(struct mmc *mmc)
 	return 0;
 }
 
+/* We pass in the cmd since otherwise the init seems to fail */
+static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd,
+		int use_arg)
+{
+	int err;
+
+	cmd->cmdidx = MMC_CMD_SEND_OP_COND;
+	cmd->resp_type = MMC_RSP_R3;
+	cmd->cmdarg = 0;
+	if (use_arg && !mmc_host_is_spi(mmc)) {
+		cmd->cmdarg =
+			(mmc->voltages &
+			(mmc->op_cond_response & OCR_VOLTAGE_MASK)) |
+			(mmc->op_cond_response & OCR_ACCESS_MODE);
+	}
+	if (mmc->host_caps & MMC_MODE_HC)
+		cmd->cmdarg |= OCR_HCS;
+
+	err = mmc_send_cmd(mmc, cmd, NULL);
+	if (err)
+		return err;
+	mmc->op_cond_response = cmd->response[0];
+	mmc->ocr = cmd->response[0];
+	return 0;
+}
+
 int mmc_send_op_cond(struct mmc *mmc)
 {
-	int timeout = 10000;
 	struct mmc_cmd cmd;
-	int err;
+	int err, i;
 
 	/* Some cards seem to need this */
 	mmc_go_idle(mmc);
 
  	/* Asking to the card its capabilities */
- 	cmd.cmdidx = MMC_CMD_SEND_OP_COND;
- 	cmd.resp_type = MMC_RSP_R3;
- 	cmd.cmdarg = 0;
- 	cmd.flags = 0;
-
- 	err = mmc_send_cmd(mmc, &cmd, NULL);
-
- 	if (err)
- 		return err;
-
- 	udelay(1000);
-
-	do {
-		cmd.cmdidx = MMC_CMD_SEND_OP_COND;
-		cmd.resp_type = MMC_RSP_R3;
-		cmd.cmdarg = (mmc_host_is_spi(mmc) ? 0 :
-				(mmc->voltages &
-				(cmd.response[0] & OCR_VOLTAGE_MASK)) |
-				(cmd.response[0] & OCR_ACCESS_MODE));
-
-		if (mmc->host_caps & MMC_MODE_HC)
-			cmd.cmdarg |= OCR_HCS;
-
-		cmd.flags = 0;
-
-		err = mmc_send_cmd(mmc, &cmd, NULL);
-
+	mmc->op_cond_pending = 1;
+	for (i = 0; i < 2; i++) {
+		err = mmc_send_op_cond_iter(mmc, &cmd, i != 0);
 		if (err)
 			return err;
 
-		udelay(1000);
-	} while (!(cmd.response[0] & OCR_BUSY) && timeout--);
+		/* exit if not busy (flag seems to be inverted) */
+		if (mmc->op_cond_response & OCR_BUSY)
+			return 0;
+	}
+	return IN_PROGRESS;
+}
 
-	if (timeout <= 0)
-		return UNUSABLE_ERR;
+int mmc_complete_op_cond(struct mmc *mmc)
+{
+	struct mmc_cmd cmd;
+	int timeout = 1000;
+	uint start;
+	int err;
+
+	mmc->op_cond_pending = 0;
+
+	/* If device is ready, do not check OCR again.
+	*  For NCMMCS16G, another OCR reading may cause that it's not working. */
+	if(!(mmc->ocr & OCR_BUSY))
+	{
+		start = get_timer(0);
+		do {
+			err = mmc_send_op_cond_iter(mmc, &cmd, 1);
+			if (err)
+				return err;
+			if (get_timer(start) > timeout)
+				return UNUSABLE_ERR;
+			udelay(100);
+		} while (!(mmc->op_cond_response & OCR_BUSY));
+	}
 
 	if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
 		cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
 		cmd.resp_type = MMC_RSP_R3;
 		cmd.cmdarg = 0;
-		cmd.flags = 0;
 
 		err = mmc_send_cmd(mmc, &cmd, NULL);
 
 		if (err)
 			return err;
+
+		mmc->ocr = cmd.response[0];
 	}
 
 	mmc->version = MMC_VERSION_UNKNOWN;
-	mmc->ocr = cmd.response[0];
 
 	mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
 	mmc->rca = 0;
@@ -668,7 +468,7 @@ int mmc_send_op_cond(struct mmc *mmc)
 }
 
 
-int mmc_send_ext_csd(struct mmc *mmc, char *ext_csd)
+static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
 {
 	struct mmc_cmd cmd;
 	struct mmc_data data;
@@ -678,11 +478,10 @@ int mmc_send_ext_csd(struct mmc *mmc, char *ext_csd)
 	cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
 	cmd.resp_type = MMC_RSP_R1;
 	cmd.cmdarg = 0;
-	cmd.flags = 0;
 
-	data.dest = ext_csd;
+	data.dest = (char *)ext_csd;
 	data.blocks = 1;
-	data.blocksize = 512;
+	data.blocksize = MMC_MAX_BLOCK_LEN;
 	data.flags = MMC_DATA_READ;
 
 	err = mmc_send_cmd(mmc, &cmd, &data);
@@ -691,7 +490,7 @@ int mmc_send_ext_csd(struct mmc *mmc, char *ext_csd)
 }
 
 
-int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
+static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
 {
 	struct mmc_cmd cmd;
 	int timeout = 1000;
@@ -702,7 +501,6 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
 	cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
 				 (index << 16) |
 				 (value << 8);
-	cmd.flags = 0;
 
 	ret = mmc_send_cmd(mmc, &cmd, NULL);
 
@@ -714,9 +512,9 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
 
 }
 
-int mmc_change_freq(struct mmc *mmc)
+static int mmc_change_freq(struct mmc *mmc)
 {
-	ALLOC_CACHE_ALIGN_BUFFER(char, ext_csd, 512);
+	ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
 	char cardtype;
 	int err;
 
@@ -739,7 +537,7 @@ int mmc_change_freq(struct mmc *mmc)
 	err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
 
 	if (err)
-		return err;
+		return err == SWITCH_ERR ? 0 : err;
 
 	/* Now check to see that it worked */
 	err = mmc_send_ext_csd(mmc, ext_csd);
@@ -752,10 +550,43 @@ int mmc_change_freq(struct mmc *mmc)
 		return 0;
 
 	/* High Speed is set, there are two types: 52MHz and 26MHz */
-	if (cardtype & MMC_HS_52MHZ)
+	if (cardtype & EXT_CSD_CARD_TYPE_52) {
+#ifdef CONFIG_MMC_DDR_MODE
+		if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
+			mmc->card_caps |= MMC_MODE_DDR_52MHz;
+#endif
 		mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
-	else
+	} else {
 		mmc->card_caps |= MMC_MODE_HS;
+	}
+
+	return 0;
+}
+
+static int mmc_set_capacity(struct mmc *mmc, int part_num)
+{
+	switch (part_num) {
+	case 0:
+		mmc->capacity = mmc->capacity_user;
+		break;
+	case 1:
+	case 2:
+		mmc->capacity = mmc->capacity_boot;
+		break;
+	case 3:
+		mmc->capacity = mmc->capacity_rpmb;
+		break;
+	case 4:
+	case 5:
+	case 6:
+	case 7:
+		mmc->capacity = mmc->capacity_gp[part_num - 4];
+		break;
+	default:
+		return -1;
+	}
+
+	mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
 
 	return 0;
 }
@@ -763,13 +594,18 @@ int mmc_change_freq(struct mmc *mmc)
 int mmc_switch_part(int dev_num, unsigned int part_num)
 {
 	struct mmc *mmc = find_mmc_device(dev_num);
+	int ret;
 
 	if (!mmc)
 		return -1;
 
-	return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
-			  (mmc->part_config & ~PART_ACCESS_MASK)
-			  | (part_num & PART_ACCESS_MASK));
+	ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
+			 (mmc->part_config & ~PART_ACCESS_MASK)
+			 | (part_num & PART_ACCESS_MASK));
+	if (ret)
+		return ret;
+
+	return mmc_set_capacity(mmc, part_num);
 }
 
 int mmc_getcd(struct mmc *mmc)
@@ -778,13 +614,17 @@ int mmc_getcd(struct mmc *mmc)
 
 	cd = board_mmc_getcd(mmc);
 
-	if ((cd < 0) && mmc->getcd)
-		cd = mmc->getcd(mmc);
+	if (cd < 0) {
+		if (mmc->getcd)
+			cd = mmc->getcd(mmc);
+		else
+			cd = 1;
+	}
 
 	return cd;
 }
 
-int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
+static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
 {
 	struct mmc_cmd cmd;
 	struct mmc_data data;
@@ -795,7 +635,6 @@ int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
 	cmd.cmdarg = (mode << 31) | 0xffffff;
 	cmd.cmdarg &= ~(0xf << (group * 4));
 	cmd.cmdarg |= value << (group * 4);
-	cmd.flags = 0;
 
 	data.dest = (char *)resp;
 	data.blocksize = 64;
@@ -806,7 +645,7 @@ int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
 }
 
 
-int sd_change_freq(struct mmc *mmc)
+static int sd_change_freq(struct mmc *mmc)
 {
 	int err;
 	struct mmc_cmd cmd;
@@ -824,7 +663,6 @@ int sd_change_freq(struct mmc *mmc)
 	cmd.cmdidx = MMC_CMD_APP_CMD;
 	cmd.resp_type = MMC_RSP_R1;
 	cmd.cmdarg = mmc->rca << 16;
-	cmd.flags = 0;
 
 	err = mmc_send_cmd(mmc, &cmd, NULL);
 
@@ -834,7 +672,6 @@ int sd_change_freq(struct mmc *mmc)
 	cmd.cmdidx = SD_CMD_APP_SEND_SCR;
 	cmd.resp_type = MMC_RSP_R1;
 	cmd.cmdarg = 0;
-	cmd.flags = 0;
 
 	timeout = 3;
 
@@ -865,6 +702,8 @@ retry_scr:
 			break;
 		case 2:
 			mmc->version = SD_VERSION_2;
+			if ((mmc->scr[0] >> 15) & 0x1)
+				mmc->version = SD_VERSION_3;
 			break;
 		default:
 			mmc->version = SD_VERSION_1_0;
@@ -947,7 +786,7 @@ static const int multipliers[] = {
 	80,
 };
 
-void mmc_set_ios(struct mmc *mmc)
+static void mmc_set_ios(struct mmc *mmc)
 {
 	mmc->set_ios(mmc);
 }
@@ -965,21 +804,21 @@ void mmc_set_clock(struct mmc *mmc, uint clock)
 	mmc_set_ios(mmc);
 }
 
-void mmc_set_bus_width(struct mmc *mmc, uint width)
+static void mmc_set_bus_width(struct mmc *mmc, uint width)
 {
 	mmc->bus_width = width;
 
 	mmc_set_ios(mmc);
 }
 
-int mmc_startup(struct mmc *mmc)
+static int mmc_startup(struct mmc *mmc)
 {
-	int err, width;
+	int err, i;
 	uint mult, freq;
 	u64 cmult, csize, capacity;
 	struct mmc_cmd cmd;
-	ALLOC_CACHE_ALIGN_BUFFER(char, ext_csd, 512);
-	ALLOC_CACHE_ALIGN_BUFFER(char, test_csd, 512);
+	ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
+	ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
 	int timeout = 1000;
 
 #ifdef CONFIG_MMC_SPI_CRC_ON
@@ -987,7 +826,6 @@ int mmc_startup(struct mmc *mmc)
 		cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
 		cmd.resp_type = MMC_RSP_R1;
 		cmd.cmdarg = 1;
-		cmd.flags = 0;
 		err = mmc_send_cmd(mmc, &cmd, NULL);
 
 		if (err)
@@ -1000,7 +838,6 @@ int mmc_startup(struct mmc *mmc)
 		MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
 	cmd.resp_type = MMC_RSP_R2;
 	cmd.cmdarg = 0;
-	cmd.flags = 0;
 
 	err = mmc_send_cmd(mmc, &cmd, NULL);
 
@@ -1018,7 +855,6 @@ int mmc_startup(struct mmc *mmc)
 		cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
 		cmd.cmdarg = mmc->rca << 16;
 		cmd.resp_type = MMC_RSP_R6;
-		cmd.flags = 0;
 
 		err = mmc_send_cmd(mmc, &cmd, NULL);
 
@@ -1033,7 +869,6 @@ int mmc_startup(struct mmc *mmc)
 	cmd.cmdidx = MMC_CMD_SEND_CSD;
 	cmd.resp_type = MMC_RSP_R2;
 	cmd.cmdarg = mmc->rca << 16;
-	cmd.flags = 0;
 
 	err = mmc_send_cmd(mmc, &cmd, NULL);
 
@@ -1096,21 +931,24 @@ int mmc_startup(struct mmc *mmc)
 		cmult = (mmc->csd[2] & 0x00038000) >> 15;
 	}
 
-	mmc->capacity = (csize + 1) << (cmult + 2);
-	mmc->capacity *= mmc->read_bl_len;
+	mmc->capacity_user = (csize + 1) << (cmult + 2);
+	mmc->capacity_user *= mmc->read_bl_len;
+	mmc->capacity_boot = 0;
+	mmc->capacity_rpmb = 0;
+	for (i = 0; i < 4; i++)
+		mmc->capacity_gp[i] = 0;
 
-	if (mmc->read_bl_len > 512)
-		mmc->read_bl_len = 512;
+	if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
+		mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
 
-	if (mmc->write_bl_len > 512)
-		mmc->write_bl_len = 512;
+	if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
+		mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
 
 	/* Select the card, and put it into Transfer Mode */
 	if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
 		cmd.cmdidx = MMC_CMD_SELECT_CARD;
 		cmd.resp_type = MMC_RSP_R1;
 		cmd.cmdarg = mmc->rca << 16;
-		cmd.flags = 0;
 		err = mmc_send_cmd(mmc, &cmd, NULL);
 
 		if (err)
@@ -1125,7 +963,7 @@ int mmc_startup(struct mmc *mmc)
 	if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
 		/* check  ext_csd version and capacity */
 		err = mmc_send_ext_csd(mmc, ext_csd);
-		if (!err & (ext_csd[EXT_CSD_REV] >= 2)) {
+		if (!err && (ext_csd[EXT_CSD_REV] >= 2)) {
 			/*
 			 * According to the JEDEC Standard, the value of
 			 * ext_csd's capacity is valid if the value is more
@@ -1135,20 +973,48 @@ int mmc_startup(struct mmc *mmc)
 					| ext_csd[EXT_CSD_SEC_CNT + 1] << 8
 					| ext_csd[EXT_CSD_SEC_CNT + 2] << 16
 					| ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
-			capacity *= 512;
+			capacity *= MMC_MAX_BLOCK_LEN;
 			if ((capacity >> 20) > 2 * 1024)
-				mmc->capacity = capacity;
+				mmc->capacity_user = capacity;
+		}
+
+		switch (ext_csd[EXT_CSD_REV]) {
+		case 1:
+			mmc->version = MMC_VERSION_4_1;
+			break;
+		case 2:
+			mmc->version = MMC_VERSION_4_2;
+			break;
+		case 3:
+			mmc->version = MMC_VERSION_4_3;
+			break;
+		case 5:
+			mmc->version = MMC_VERSION_4_41;
+			break;
+		case 6:
+			mmc->version = MMC_VERSION_4_5;
+			break;
 		}
 
 		/*
-		 * Check whether GROUP_DEF is set, if yes, read out
-		 * group size from ext_csd directly, or calculate
-		 * the group size from the csd value.
+		 * Host needs to enable ERASE_GRP_DEF bit if device is
+		 * partitioned. This bit will be lost every time after a reset
+		 * or power off. This will affect erase size.
 		 */
-		if (ext_csd[EXT_CSD_ERASE_GROUP_DEF])
+		if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
+		    (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) {
+			err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+				EXT_CSD_ERASE_GROUP_DEF, 1);
+
+			if (err)
+				return err;
+
+			/* Read out group size from ext_csd */
 			mmc->erase_grp_size =
-			      ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 512 * 1024;
-		else {
+				ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] *
+					MMC_MAX_BLOCK_LEN * 1024;
+		} else {
+			/* Calculate the group size from the csd value. */
 			int erase_gsz, erase_gmul;
 			erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
 			erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
@@ -1157,10 +1023,28 @@ int mmc_startup(struct mmc *mmc)
 		}
 
 		/* store the partition info of emmc */
-		if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT)
+		if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
+		    ext_csd[EXT_CSD_BOOT_MULT])
 			mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
+
+		mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
+
+		mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
+
+		for (i = 0; i < 4; i++) {
+			int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
+			mmc->capacity_gp[i] = (ext_csd[idx + 2] << 16) +
+				(ext_csd[idx + 1] << 8) + ext_csd[idx];
+			mmc->capacity_gp[i] *=
+				ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
+			mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
+		}
 	}
 
+	err = mmc_set_capacity(mmc, mmc->part_num);
+	if (err)
+		return err;
+
 	if (IS_SD(mmc))
 		err = sd_change_freq(mmc);
 	else
@@ -1177,7 +1061,6 @@ int mmc_startup(struct mmc *mmc)
 			cmd.cmdidx = MMC_CMD_APP_CMD;
 			cmd.resp_type = MMC_RSP_R1;
 			cmd.cmdarg = mmc->rca << 16;
-			cmd.flags = 0;
 
 			err = mmc_send_cmd(mmc, &cmd, NULL);
 			if (err)
@@ -1186,7 +1069,6 @@ int mmc_startup(struct mmc *mmc)
 			cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
 			cmd.resp_type = MMC_RSP_R1;
 			cmd.cmdarg = 2;
-			cmd.flags = 0;
 			err = mmc_send_cmd(mmc, &cmd, NULL);
 			if (err)
 				return err;
@@ -1195,23 +1077,59 @@ int mmc_startup(struct mmc *mmc)
 		}
 
 		if (mmc->card_caps & MMC_MODE_HS)
-			mmc_set_clock(mmc, 50000000);
+			mmc->tran_speed = 50000000;
 		else
-			mmc_set_clock(mmc, 25000000);
+			mmc->tran_speed = 25000000;
 	} else {
-		for (width = EXT_CSD_BUS_WIDTH_8; width >= 0; width--) {
-			/* Set the card to use 4 bit*/
+		int idx;
+
+		/* An array of possible bus widths in order of preference */
+		static unsigned ext_csd_bits[] = {
+#ifdef CONFIG_MMC_DDR_MODE
+			EXT_CSD_DDR_BUS_WIDTH_8,
+			EXT_CSD_DDR_BUS_WIDTH_4,
+#endif
+			EXT_CSD_BUS_WIDTH_8,
+			EXT_CSD_BUS_WIDTH_4,
+			EXT_CSD_BUS_WIDTH_1,
+		};
+
+		/* An array to map CSD bus widths to host cap bits */
+		static unsigned ext_to_hostcaps[] = {
+#ifdef CONFIG_MMC_DDR_MODE
+			[EXT_CSD_DDR_BUS_WIDTH_4] = MMC_MODE_DDR_52MHz,
+			[EXT_CSD_DDR_BUS_WIDTH_8] = MMC_MODE_DDR_52MHz,
+#endif
+			[EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
+			[EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
+		};
+
+		/* An array to map chosen bus width to an integer */
+		static unsigned widths[] = {
+#ifdef CONFIG_MMC_DDR_MODE
+			0x80000008, 0x80000004, /* ddr mode */
+#endif
+			8, 4, 1,
+		};
+
+		for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
+			unsigned int extw = ext_csd_bits[idx];
+
+			/*
+			 * Check to make sure the controller supports
+			 * this bus width, if it's more than 1
+			 */
+			if (extw != EXT_CSD_BUS_WIDTH_1 &&
+					!(mmc->host_caps & ext_to_hostcaps[extw]))
+				continue;
+
 			err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
-					EXT_CSD_BUS_WIDTH, width);
+					EXT_CSD_BUS_WIDTH, extw);
 
 			if (err)
 				continue;
 
-			if (!width) {
-				mmc_set_bus_width(mmc, 1);
-				break;
-			} else
-				mmc_set_bus_width(mmc, 4 * width);
+			mmc_set_bus_width(mmc, widths[idx]);
 
 			err = mmc_send_ext_csd(mmc, test_csd);
 			if (!err && ext_csd[EXT_CSD_PARTITIONING_SUPPORT] \
@@ -1225,38 +1143,76 @@ int mmc_startup(struct mmc *mmc)
 				 && memcmp(&ext_csd[EXT_CSD_SEC_CNT], \
 					&test_csd[EXT_CSD_SEC_CNT], 4) == 0) {
 
-				mmc->card_caps |= width;
+				mmc->card_caps |= ext_to_hostcaps[extw];
 				break;
 			}
 		}
 
 		if (mmc->card_caps & MMC_MODE_HS) {
 			if (mmc->card_caps & MMC_MODE_HS_52MHz)
-				mmc_set_clock(mmc, 52000000);
+				mmc->tran_speed = 52000000;
 			else
-				mmc_set_clock(mmc, 26000000);
-		} else
-			mmc_set_clock(mmc, 20000000);
+				mmc->tran_speed = 26000000;
+		}
 	}
 
+	mmc_set_clock(mmc, mmc->tran_speed);
+
 	/* fill in device description */
 	mmc->block_dev.lun = 0;
 	mmc->block_dev.type = 0;
 	mmc->block_dev.blksz = mmc->read_bl_len;
+	mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
 	mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
-	sprintf(mmc->block_dev.vendor, "Man %06x Snr %08x", mmc->cid[0] >> 8,
-			(mmc->cid[2] << 8) | (mmc->cid[3] >> 24));
-	sprintf(mmc->block_dev.product, "%c%c%c%c%c", mmc->cid[0] & 0xff,
-			(mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
-			(mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff);
-	sprintf(mmc->block_dev.revision, "%d.%d", mmc->cid[2] >> 28,
-			(mmc->cid[2] >> 24) & 0xf);
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+	sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x",
+		mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
+		(mmc->cid[3] >> 16) & 0xffff);
+	sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
+		(mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
+		(mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
+		(mmc->cid[2] >> 24) & 0xff);
+	sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
+		(mmc->cid[2] >> 16) & 0xf);
+#else
+	mmc->block_dev.vendor[0] = 0;
+	mmc->block_dev.product[0] = 0;
+	mmc->block_dev.revision[0] = 0;
+#endif
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
 	init_part(&mmc->block_dev);
+#endif
 
 	return 0;
 }
 
-int mmc_send_if_cond(struct mmc *mmc)
+static void print_mmcinfo(struct mmc *mmc)
+{
+	int maf_idx;
+	for (maf_idx = 0; mmc_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
+		if (mmc_manuf_ids[maf_idx].id == (mmc->cid[0] >> 24))
+			break;
+	}
+
+	printf("-------------MMC information-----------\n");
+	printf("Manufacturer ID: %x,  Name: %s \n", mmc->cid[0] >> 24, mmc_manuf_ids[maf_idx].name);
+	printf("OEM: %x\n", (mmc->cid[0] >> 8) & 0xffff);
+
+	printf("Tran Speed: %d\n", mmc->tran_speed);
+	printf("Rd Block Len: %d\n", mmc->read_bl_len);
+
+	printf("%s version %d.%d\n", IS_SD(mmc) ? "SD" : "MMC",
+			(mmc->version >> 8) & 0xf, mmc->version & 0xff);
+
+	printf("High Capacity: %s\n", mmc->high_capacity ? "Yes" : "No");
+	puts("Capacity: ");
+	//print_size(mmc->capacity, "\n");
+
+	printf("Bus Width: %d-bit\n", mmc->bus_width);
+	printf("-----------------------------------------\n");
+}
+
+static int mmc_send_if_cond(struct mmc *mmc)
 {
 	struct mmc_cmd cmd;
 	int err;
@@ -1265,7 +1221,6 @@ int mmc_send_if_cond(struct mmc *mmc)
 	/* We set the bit if the host supports voltages between 2.7 and 3.6 V */
 	cmd.cmdarg = ((mmc->voltages & 0xff8000) != 0) << 8 | 0xaa;
 	cmd.resp_type = MMC_RSP_R7;
-	cmd.flags = 0;
 
 	err = mmc_send_cmd(mmc, &cmd, NULL);
 
@@ -1303,18 +1258,22 @@ int mmc_register(struct mmc *mmc)
 block_dev_desc_t *mmc_get_dev(int dev)
 {
 	struct mmc *mmc = find_mmc_device(dev);
+	if (!mmc || mmc_init(mmc))
+		return NULL;
 
-	return mmc ? &mmc->block_dev : NULL;
+	return &mmc->block_dev;
 }
 #endif
 
-int mmc_init(struct mmc *mmc)
+int mmc_start_init(struct mmc *mmc)
 {
 	int err;
 
 	if (mmc_getcd(mmc) == 0) {
 		mmc->has_init = 0;
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 		printf("MMC: no card present\n");
+#endif
 		return NO_CARD_ERR;
 	}
 
@@ -1348,17 +1307,51 @@ int mmc_init(struct mmc *mmc)
 	if (err == TIMEOUT) {
 		err = mmc_send_op_cond(mmc);
 
-		if (err) {
+		if (err && err != IN_PROGRESS) {
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 			printf("Card did not respond to voltage select!\n");
+#endif
 			return UNUSABLE_ERR;
 		}
 	}
 
-	err = mmc_startup(mmc);
+	if (err == IN_PROGRESS)
+		mmc->init_in_progress = 1;
+
+	return err;
+}
+
+static int mmc_complete_init(struct mmc *mmc)
+{
+	int err = 0;
+
+	if (mmc->op_cond_pending)
+		err = mmc_complete_op_cond(mmc);
+
+	if (!err)
+		err = mmc_startup(mmc);
 	if (err)
 		mmc->has_init = 0;
 	else
 		mmc->has_init = 1;
+	mmc->init_in_progress = 0;
+	return err;
+}
+
+int mmc_init(struct mmc *mmc)
+{
+	int err = IN_PROGRESS;
+	unsigned start = get_timer(0);
+
+	if (mmc->has_init)
+		return 0;
+	if (!mmc->init_in_progress)
+		err = mmc_start_init(mmc);
+
+	if (!err || err == IN_PROGRESS)
+		err = mmc_complete_init(mmc);
+	debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
+	print_mmcinfo(mmc);
 	return err;
 }
 
@@ -1374,6 +1367,8 @@ static int __def_mmc_init(bd_t *bis)
 int cpu_mmc_init(bd_t *bis) __attribute__((weak, alias("__def_mmc_init")));
 int board_mmc_init(bd_t *bis) __attribute__((weak, alias("__def_mmc_init")));
 
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+
 void print_mmc_devices(char separator)
 {
 	struct mmc *m;
@@ -1391,11 +1386,34 @@ void print_mmc_devices(char separator)
 	printf("\n");
 }
 
+#else
+void print_mmc_devices(char separator) { }
+#endif
+
 int get_mmc_num(void)
 {
 	return cur_dev_num;
 }
 
+void mmc_set_preinit(struct mmc *mmc, int preinit)
+{
+	mmc->preinit = preinit;
+}
+
+static void do_preinit(void)
+{
+	struct mmc *m;
+	struct list_head *entry;
+
+	list_for_each(entry, &mmc_devices) {
+		m = list_entry(entry, struct mmc, link);
+
+		if (m->preinit)
+			mmc_start_init(m);
+	}
+}
+
+
 int mmc_initialize(bd_t *bis)
 {
 	INIT_LIST_HEAD (&mmc_devices);
@@ -1404,7 +1422,144 @@ int mmc_initialize(bd_t *bis)
 	if (board_mmc_init(bis) < 0)
 		cpu_mmc_init(bis);
 
+#ifndef CONFIG_SPL_BUILD
 	print_mmc_devices(',');
+#endif
 
+	do_preinit();
 	return 0;
 }
+
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+/*
+ * This function changes the size of boot partition and the size of rpmb
+ * partition present on EMMC devices.
+ *
+ * Input Parameters:
+ * struct *mmc: pointer for the mmc device strcuture
+ * bootsize: size of boot partition
+ * rpmbsize: size of rpmb partition
+ *
+ * Returns 0 on success.
+ */
+
+int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
+				unsigned long rpmbsize)
+{
+	int err;
+	struct mmc_cmd cmd;
+
+	/* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
+	cmd.cmdidx = MMC_CMD_RES_MAN;
+	cmd.resp_type = MMC_RSP_R1b;
+	cmd.cmdarg = MMC_CMD62_ARG1;
+
+	err = mmc_send_cmd(mmc, &cmd, NULL);
+	if (err) {
+		debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
+		return err;
+	}
+
+	/* Boot partition changing mode */
+	cmd.cmdidx = MMC_CMD_RES_MAN;
+	cmd.resp_type = MMC_RSP_R1b;
+	cmd.cmdarg = MMC_CMD62_ARG2;
+
+	err = mmc_send_cmd(mmc, &cmd, NULL);
+	if (err) {
+		debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
+		return err;
+	}
+	/* boot partition size is multiple of 128KB */
+	bootsize = (bootsize * 1024) / 128;
+
+	/* Arg: boot partition size */
+	cmd.cmdidx = MMC_CMD_RES_MAN;
+	cmd.resp_type = MMC_RSP_R1b;
+	cmd.cmdarg = bootsize;
+
+	err = mmc_send_cmd(mmc, &cmd, NULL);
+	if (err) {
+		debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
+		return err;
+	}
+	/* RPMB partition size is multiple of 128KB */
+	rpmbsize = (rpmbsize * 1024) / 128;
+	/* Arg: RPMB partition size */
+	cmd.cmdidx = MMC_CMD_RES_MAN;
+	cmd.resp_type = MMC_RSP_R1b;
+	cmd.cmdarg = rpmbsize;
+
+	err = mmc_send_cmd(mmc, &cmd, NULL);
+	if (err) {
+		debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
+		return err;
+	}
+	return 0;
+}
+
+/*
+ * This function shall form and send the commands to open / close the
+ * boot partition specified by user.
+ *
+ * Input Parameters:
+ * ack: 0x0 - No boot acknowledge sent (default)
+ *	0x1 - Boot acknowledge sent during boot operation
+ * part_num: User selects boot data that will be sent to master
+ *	0x0 - Device not boot enabled (default)
+ *	0x1 - Boot partition 1 enabled for boot
+ *	0x2 - Boot partition 2 enabled for boot
+ * access: User selects partitions to access
+ *	0x0 : No access to boot partition (default)
+ *	0x1 : R/W boot partition 1
+ *	0x2 : R/W boot partition 2
+ *	0x3 : R/W Replay Protected Memory Block (RPMB)
+ *
+ * Returns 0 on success.
+ */
+int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
+{
+	int err;
+	struct mmc_cmd cmd;
+
+	/* Boot ack enable, boot partition enable , boot partition access */
+	cmd.cmdidx = MMC_CMD_SWITCH;
+	cmd.resp_type = MMC_RSP_R1b;
+
+	cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
+			(EXT_CSD_PART_CONF << 16) |
+			((EXT_CSD_BOOT_ACK(ack) |
+			EXT_CSD_BOOT_PART_NUM(part_num) |
+			EXT_CSD_PARTITION_ACCESS(access)) << 8);
+
+	err = mmc_send_cmd(mmc, &cmd, NULL);
+	if (err) {
+		if (access) {
+			debug("mmc boot partition#%d open fail:Error1 = %d\n",
+			      part_num, err);
+		} else {
+			debug("mmc boot partition#%d close fail:Error = %d\n",
+			      part_num, err);
+		}
+		return err;
+	}
+
+	if (access) {
+		/* 4bit transfer mode at booting time. */
+		cmd.cmdidx = MMC_CMD_SWITCH;
+		cmd.resp_type = MMC_RSP_R1b;
+
+		cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
+				(EXT_CSD_BOOT_BUS_WIDTH << 16) |
+				((1 << 0) << 8);
+
+		err = mmc_send_cmd(mmc, &cmd, NULL);
+		if (err) {
+			debug("mmc boot partition#%d open fail:Error2 = %d\n",
+			      part_num, err);
+			return err;
+		}
+	}
+	return 0;
+}
+#endif
diff --git a/drivers/mmc/mmc_parts.c b/drivers/mmc/mmc_parts.c
new file mode 100644
index 0000000000..c50d75fd76
--- /dev/null
+++ b/drivers/mmc/mmc_parts.c
@@ -0,0 +1,725 @@
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+ *   * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <linux/string.h>
+#include "common.h"
+#include <malloc.h>
+#include <asm/arch/rda_sys.h>
+#include "mmc.h"
+#include <part.h>
+
+#define EFI_ENTRIES	32
+
+static int part_nums;
+
+/* To support the Android-style naming of flash */
+#define MAX_PTN (CONFIG_MAX_PARTITION_NUM - CONFIG_MIN_PARTITION_NUM + 1)
+static disk_partition_t ptable[MAX_PTN];
+
+/* special size referring to all the remaining space in a partition */
+#define SIZE_REMAINING		(u64)(-1)
+
+/* special offset value, it is used when not provided by user
+ *
+ * this value is used temporarily during parsing, later such offests
+ * are recalculated */
+#define OFFSET_NOT_SPECIFIED	(u64)(-1)
+
+
+/* a bunch of this is duplicate of part_efi.c and part_efi.h
+ * we should consider putting this code in there and layer
+ * the partition info.
+ */
+#define EFI_VERSION 0x00010000
+#define EFI_NAMELEN 36
+
+static const u8 partition_type[16] = {
+	0xa2, 0xa0, 0xd0, 0xeb, 0xe5, 0xb9, 0x33, 0x44,
+	0x87, 0xc0, 0x68, 0xb6, 0xb7, 0x26, 0x99, 0xc7,
+};
+
+static const u8 random_uuid[16] = {
+	0xff, 0x1f, 0xf2, 0xf9, 0xd4, 0xa8, 0x0e, 0x5f,
+	0x97, 0x46, 0x59, 0x48, 0x69, 0xae, 0xc3, 0x4e,
+};
+
+struct efi_entry {
+	u8 type_uuid[16];
+	u8 uniq_uuid[16];
+	u64 first_lba;
+	u64 last_lba;
+	u64 attr;
+	u16 name[EFI_NAMELEN];
+};
+
+struct efi_header {
+	u8 magic[8];
+
+	u32 version;
+	u32 header_sz;
+
+	u32 crc32;
+	u32 reserved;
+
+	u64 header_lba;
+	u64 backup_lba;
+	u64 first_lba;
+	u64 last_lba;
+
+	u8 volume_uuid[16];
+
+	u64 entries_lba;
+
+	u32 entries_count;
+	u32 entries_size;
+	u32 entries_crc32;
+} __attribute__((packed));
+
+struct ptable {
+	u8 mbr[512];
+	union {
+		struct efi_header header;
+		u8 block[512];
+	};
+	struct efi_entry entry[EFI_ENTRIES];
+};
+
+static struct ptable the_ptable;
+
+/* in a board specific file */
+struct fbt_partition {
+	char name[32];
+	char type[32];
+	u64	offset;
+	u64 	size;
+	unsigned int attr;
+};
+/* For the 16GB eMMC part used in Tungsten, the erase group size is 512KB.
+ * So every partition should be at least 512KB to make it possible to use
+ * the mmc erase operation when doing 'fastboot erase'.
+ * However, the xloader is an exception because in order for the OMAP4 ROM
+ * bootloader to find it, it must be at offset 0KB, 128KB, 256KB, or 384KB.
+ * Since the partition table is at 0KB, we choose 128KB.  Special care
+ * must be kept to prevent erase the partition table when/if the xloader
+ * partition is being erased.
+ */
+struct fbt_partition fbt_partitions[EFI_ENTRIES];
+
+/**
+ * Parses a string into a number.  The number stored at ptr is
+ * potentially suffixed with K (for kilobytes, or 1024 bytes),
+ * M (for megabytes, or 1048576 bytes), or G (for gigabytes, or
+ * 1073741824).  If the number is suffixed with K, M, or G, then
+ * the return value is the number multiplied by one kilobyte, one
+ * megabyte, or one gigabyte, respectively.
+ *
+ * @param ptr where parse begins
+ * @param retptr output pointer to next char after parse completes (output)
+ * @return resulting unsigned int
+ */
+static unsigned long memsize_parse (const char *const ptr, const char **retptr)
+{
+	unsigned long ret = simple_strtoul(ptr, (char **)retptr, 0);
+
+	switch (**retptr) {
+	case 'G':
+	case 'g':
+		ret <<= 10;
+	case 'M':
+	case 'm':
+		ret <<= 10;
+	case 'K':
+	case 'k':
+		ret <<= 10;
+		(*retptr)++;
+	default:
+		break;
+	}
+
+	return ret;
+}
+
+#define MIN_PART_SIZE	4096
+/**
+ * Parse one partition definition, allocate memory and return pointer to this
+ * location in retpart.
+ *
+ * @param partdef pointer to the partition definition string i.e. <part-def>
+ * @param ret output pointer to next char after parse completes (output)
+ * @param retpart pointer to the allocated partition (output)
+ * @return 0 on success, 1 otherwise
+ */
+static int part_parse(const char *const partdef, const char **ret, struct fbt_partition *part)
+{
+	u64 size;
+	u64 offset;
+	const char *name;
+	int name_len;
+	unsigned int mask_flags;
+	const char *p;
+
+	p = partdef;
+	*ret = NULL;
+
+	/* fetch the partition size */
+	if (*p == '-') {
+		/* assign all remaining space to this partition */
+		debug("'-': remaining size assigned\n");
+		size = SIZE_REMAINING;
+		p++;
+	} else {
+		size = memsize_parse(p, &p);
+		if (size < MIN_PART_SIZE) {
+			printf("partition size too small (%llx)\n", size);
+			return 1;
+		}
+	}
+
+	/* check for offset */
+	offset = OFFSET_NOT_SPECIFIED;
+	if (*p == '@') {
+		p++;
+		offset = memsize_parse(p, &p);
+	}
+
+	/* now look for the name */
+	if (*p == '(') {
+		name = ++p;
+		if ((p = strchr(name, ')')) == NULL) {
+			printf("no closing ) found in partition name\n");
+			return 1;
+		}
+		name_len = p - name + 1;
+		if ((name_len - 1) == 0) {
+			printf("empty partition name\n");
+			return 1;
+		}
+		p++;
+	} else {
+		/* 0x00000000@0x00000000 */
+		name_len = 22;
+		name = NULL;
+	}
+
+	/* test for options */
+	mask_flags = 0;
+	if (strncmp(p, "ro", 2) == 0) {
+		mask_flags |= 1;
+		p += 2;
+	}
+
+	/* check for next partition definition */
+	if (*p == ',') {
+		if (size == SIZE_REMAINING) {
+			*ret = NULL;
+			printf("no partitions allowed after a fill-up partition\n");
+			return 1;
+		}
+		*ret = ++p;
+	} else if ((*p == ';') || (*p == '\0')) {
+		*ret = p;
+	} else {
+		printf("unexpected character '%c' at the end of partition\n", *p);
+		*ret = NULL;
+		return 1;
+	}
+
+	memset(part, 0, sizeof(struct fbt_partition));
+	part->size = size;
+	part->offset = offset;
+	part->attr = mask_flags;
+
+	if (name) {
+		/* copy user provided name */
+		strncpy(part->name, name, name_len - 1);
+	} else {
+		/* auto generated name in form of size@offset */
+		sprintf(part->name, "0x%llx@0x%llx", size, offset);
+	}
+
+	part->name[name_len - 1] = '\0';
+
+	debug("+ partition: name %-22s size 0x%llx offset 0x%llx mask flags %x\n",
+			part->name, part->size,
+			part->offset, part->attr);
+
+	return 0;
+}
+
+/**
+ * Performs sanity check for supplied partition. Offset and size are verified
+ * to be within valid range. Partition type is checked and either
+ * parts_validate_nor() or parts_validate_nand() is called with the argument
+ * of part.
+ *
+ * @param id of the parent device
+ * @param part partition to validate
+ * @return 0 if partition is valid, 1 otherwise
+ */
+static int part_validate(struct mmc *mmc, struct fbt_partition *part)
+{
+
+	if (part->size == SIZE_REMAINING)
+		part->size = mmc->capacity - part->offset;
+/*
+
+	if (part->offset > id->size) {
+		printf("%s: offset %08x beyond flash size 0x%llx\n",
+				id->mtd_id, part->offset, id->size);
+		return 1;
+	}
+
+	if (((u64)part->offset + (u64)part->size) <= (u64)part->offset) {
+		printf("%s%d: partition (%s) size too big\n",
+				MTD_DEV_TYPE(id->type), id->num, part->name);
+		return 1;
+	}
+
+	if (part->offset + part->size > id->size) {
+		printf("%s: partitioning exceeds flash size %llx, part %x+%x\n",
+			id->mtd_id, id->size, part->offset, part->size);
+		return 1;
+	}
+*/
+	/*
+	 * Now we need to check if the partition starts and ends on
+	 * sector (eraseblock) regions
+	 */
+	return 0;
+}
+
+static const char *const mmcparts_default = MTDPARTS_DEF;
+
+int mmc_part_parse(struct mmc *mmc)
+{
+	const char *p;
+	struct fbt_partition *part;
+	u64 offset;
+	int index = 0;
+	int err = 0;
+
+	p = mmcparts_default;
+	offset = 0;
+	while (p && (*p != '\0') && (*p != ';')) {
+		err = 1;
+		part =  &fbt_partitions[index];
+		if ((part_parse(p, &p, part) != 0))
+			break;
+
+		/* calculate offset when not specified */
+		if (part->offset == OFFSET_NOT_SPECIFIED)
+			part->offset = offset;
+		else
+			offset = part->offset;
+
+		/* verify alignment and size */
+		if (part_validate(mmc, part) != 0)
+			break;
+
+		offset += part->size;
+
+		/* partition is ok, add it to the list */
+		index++;
+		if (index > EFI_ENTRIES)
+			break;
+		err = 0;
+	debug("++++++++++++ partition: name %-22s size 0x%llx offset 0x%llx mask flags %x\n",
+			part->name, part->size,
+			part->offset, part->attr);
+	}
+	part_nums = index;
+	return err;
+}
+
+
+static void init_mbr(u8 *mbr, u32 blocks)
+{
+	mbr[0x1be] = 0x00; // nonbootable
+	mbr[0x1bf] = 0xFF; // bogus CHS
+	mbr[0x1c0] = 0xFF;
+	mbr[0x1c1] = 0xFF;
+
+	mbr[0x1c2] = 0xEE; // GPT partition
+	mbr[0x1c3] = 0xFF; // bogus CHS
+	mbr[0x1c4] = 0xFF;
+	mbr[0x1c5] = 0xFF;
+
+	mbr[0x1c6] = 0x01; // start
+	mbr[0x1c7] = 0x00;
+	mbr[0x1c8] = 0x00;
+	mbr[0x1c9] = 0x00;
+
+	memcpy(mbr + 0x1ca, &blocks, sizeof(u32));
+
+	mbr[0x1fe] = 0x55;
+	mbr[0x1ff] = 0xaa;
+}
+
+static void start_ptbl(struct ptable *ptbl, unsigned blocks)
+{
+	struct efi_header *hdr = &ptbl->header;
+
+	memset(ptbl, 0, sizeof(*ptbl));
+
+	init_mbr(ptbl->mbr, blocks - 1);
+
+	memcpy(hdr->magic, "EFI PART", 8);
+	hdr->version = EFI_VERSION;
+	hdr->header_sz = sizeof(struct efi_header);
+	hdr->header_lba = 1;
+	hdr->backup_lba = blocks - 1;
+	hdr->first_lba = 34;
+	hdr->last_lba = blocks - 1;
+	memcpy(hdr->volume_uuid, random_uuid, 16);
+	hdr->entries_lba = 2;
+	hdr->entries_count = EFI_ENTRIES;
+	hdr->entries_size = sizeof(struct efi_entry);
+}
+
+static void end_ptbl(struct ptable *ptbl)
+{
+	struct efi_header *hdr = &ptbl->header;
+	u32 n;
+
+	n = crc32(0, 0, 0);
+	n = crc32(n, (void*) ptbl->entry, sizeof(ptbl->entry));
+	hdr->entries_crc32 = n;
+
+	n = crc32(0, 0, 0);
+	n = crc32(0, (void*) &ptbl->header, sizeof(ptbl->header));
+	hdr->crc32 = n;
+}
+
+static int add_ptn(struct ptable *ptbl, u64 first, u64 last, const char *name)
+{
+	struct efi_header *hdr = &ptbl->header;
+	struct efi_entry *entry = ptbl->entry;
+	unsigned n;
+
+	if (first < 34) {
+		printf("partition '%s' overlaps partition table\n", name);
+		return -1;
+	}
+
+	if (last > hdr->last_lba) {
+		printf("partition '%s' does not fit\n", name);
+		return -1;
+	}
+	for (n = 0; n < EFI_ENTRIES; n++, entry++) {
+		if (entry->last_lba)
+			continue;
+		memcpy(entry->type_uuid, partition_type, 16);
+		memcpy(entry->uniq_uuid, random_uuid, 16);
+		entry->uniq_uuid[0] = n;
+		entry->first_lba = first;
+		entry->last_lba = last;
+		for (n = 0; (n < EFI_NAMELEN) && *name; n++)
+			entry->name[n] = *name++;
+		return 0;
+	}
+	printf("out of partition table entries\n");
+	return -1;
+}
+
+static unsigned int pcount;
+void fbt_add_ptn(disk_partition_t *ptn)
+{
+	if (pcount < MAX_PTN) {
+		memcpy(ptable + pcount, ptn, sizeof(*ptn));
+		pcount++;
+	}
+}
+
+
+static block_dev_desc_t *mmc_blkdev;
+
+static int __def_fbt_load_ptbl(void)
+{
+	u64 length;
+	disk_partition_t ptn;
+	int n;
+	int res = -1;
+	block_dev_desc_t *blkdev = mmc_blkdev;
+	unsigned long blksz = blkdev->blksz;
+
+	init_part(blkdev);
+	if (blkdev->part_type == PART_TYPE_UNKNOWN) {
+		printf("unknown partition table on %s\n", CONFIG_MMC_DEV_NAME);
+		return -1;
+	}
+
+	printf("lba size = %lu\n", blksz);
+	printf("lba_start      partition_size          name\n");
+	printf("=========  ======================  ==============\n");
+	for (n = CONFIG_MIN_PARTITION_NUM; n <= CONFIG_MAX_PARTITION_NUM; n++) {
+		if (get_partition_info(blkdev, n, &ptn))
+			continue;	/* No partition <n> */
+		if (!ptn.size || !ptn.blksz || !ptn.name[0])
+			continue;	/* Partition <n> is empty (or sick) */
+		fbt_add_ptn(&ptn);
+
+		length = (u64)blksz * ptn.size;
+		if (length > (1024 * 1024))
+			printf(" %8lu  %12llu(%7lluM)  %s\n",
+						ptn.start,
+						length, length/(1024*1024),
+						ptn.name);
+		else
+			printf(" %8lu  %12llu(%7lluK)  %s\n",
+						ptn.start,
+						length, length/1024,
+						ptn.name);
+		res = 0;
+	}
+	printf("=========  ======================  ==============\n");
+	return res;
+}
+
+int board_fbt_load_ptbl(void)
+	__attribute__((weak, alias("__def_fbt_load_ptbl")));
+
+disk_partition_t *partition_find_ptn(const char *name);
+
+static int fbt_load_partition_table(void)
+{
+	if (board_fbt_load_ptbl()) {
+		printf("board_fbt_load_ptbl() failed\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+disk_partition_t *partition_find_ptn(const char *name)
+{
+	unsigned int n;
+
+	if (pcount == 0) {
+		if (fbt_load_partition_table()) {
+			printf("Unable to load partition table, aborting\n");
+			return NULL;
+		}
+	}
+
+	for (n = 0; n < pcount; n++)
+		if (!strcmp((char *)ptable[n].name, name))
+			return ptable + n;
+	return NULL;
+}
+
+void fbt_reset_ptn(void)
+{
+	pcount = 0;
+	if (fbt_load_partition_table())
+		printf("Unable to load partition table\n");
+}
+
+static int do_format(void)
+{
+	struct ptable *ptbl = &the_ptable;
+	unsigned next;
+	int n;
+	block_dev_desc_t *dev_desc;
+	unsigned long blocks_to_write, result;
+	struct mmc *mmc;
+
+	dev_desc = get_dev_by_name(CONFIG_MMC_DEV_NAME);
+	if (!dev_desc) {
+		printf("error getting device %s\n", CONFIG_MMC_DEV_NAME);
+		return -1;
+	}
+	if (!dev_desc->lba) {
+		printf("device %s has no space\n", CONFIG_MMC_DEV_NAME);
+		return -1;
+	}
+	mmc = container_of(dev_desc, struct mmc, block_dev);
+
+	mmc_part_parse(mmc);
+	start_ptbl(ptbl, dev_desc->lba);
+	for (n = 0; n < part_nums; n++) {
+		u64 sz = fbt_partitions[n].size / 512;
+		next = fbt_partitions[n].offset / 512;
+		if (fbt_partitions[n].name[0] == '-') {
+			next += sz;
+			continue;
+		}
+		if (sz == 0)
+			sz = dev_desc->lba - next;
+
+		if (add_ptn(ptbl, next, next + sz - 1, fbt_partitions[n].name))
+			return -1;
+	}
+	end_ptbl(ptbl);
+
+	blocks_to_write = DIV_ROUND_UP(sizeof(struct ptable), dev_desc->blksz);
+	result = dev_desc->block_write(dev_desc->dev, 0, blocks_to_write, ptbl);
+	if (result != blocks_to_write) {
+		printf("\nFormat failed, block_write() returned %lu instead of %lu\n",
+				 result, blocks_to_write);
+		return -1;
+	}
+
+	debug("\nnew partition table of %lu %lu-byte blocks\n",
+		blocks_to_write, dev_desc->blksz);
+	fbt_reset_ptn();
+
+	return 0;
+}
+
+/* check if the partition table is same with the table stored in device */
+int mmc_check_parts(int *same)
+{
+	struct ptable *ptbl = NULL;
+	struct ptable *ptbl_r = NULL;
+	unsigned next;
+	int n;
+	block_dev_desc_t *dev_desc;
+	unsigned long blocks_to_read, result;
+	struct mmc *mmc;
+
+	if(!same) return -1;
+	*same = 0;
+
+	dev_desc = get_dev_by_name(CONFIG_MMC_DEV_NAME);
+	if (!dev_desc) {
+		printf("error getting device %s\n", CONFIG_MMC_DEV_NAME);
+		return -1;
+	}
+	if (!dev_desc->lba) {
+		printf("device %s has no space\n", CONFIG_MMC_DEV_NAME);
+		return -1;
+	}
+	mmc = container_of(dev_desc, struct mmc, block_dev);
+
+	ptbl = (struct ptable *)malloc(sizeof(struct ptable));
+	if(!ptbl) {
+		printf("can't malloc memory.\n");
+		return -1;
+	}
+	ptbl_r = (struct ptable *)malloc(sizeof(struct ptable));
+	if(!ptbl_r) {
+		printf("can't malloc memory.\n");
+		free(ptbl);
+		return -1;
+	}
+
+	mmc_part_parse(mmc);
+	start_ptbl(ptbl, dev_desc->lba);
+	for (n = 0; n < part_nums; n++) {
+		u64 sz = fbt_partitions[n].size / 512;
+		next = fbt_partitions[n].offset / 512;
+		if (fbt_partitions[n].name[0] == '-') {
+			next += sz;
+			continue;
+		}
+		if (sz == 0)
+			sz = dev_desc->lba - next;
+
+		if (add_ptn(ptbl, next, next + sz - 1, fbt_partitions[n].name)) {
+			free(ptbl);
+			free(ptbl_r);
+			return -1;
+		}
+	}
+	end_ptbl(ptbl);
+
+	memset((void *)ptbl_r, 0, sizeof(struct ptable));
+	blocks_to_read = DIV_ROUND_UP(sizeof(struct ptable), dev_desc->blksz);
+	result = dev_desc->block_read(dev_desc->dev, 0, blocks_to_read, ptbl_r);
+	if (result != blocks_to_read) {
+		printf("\nCheck Failed, block_read() returned %lu instead of %lu\n",
+				 result, blocks_to_read);
+		free(ptbl);
+		free(ptbl_r);
+		return -1;
+	}
+
+#if 0
+	/* dump */
+	printf("New paritition table:\n");
+	for(n = 0; n < sizeof(struct ptable); n++) {
+		char *p = (char *)ptbl;
+		printf("%02x ", p[n]);
+		if((n + 1) % 32 == 0 )
+			printf("\n");
+	}
+	printf("Old partition table:\n");
+	for(n = 0; n < sizeof(struct ptable); n++) {
+		char *p = (char *)ptbl_r;
+		printf("%02x ", p[n]);
+		if((n + 1) % 32 == 0 )
+			printf("\n");
+	}
+#endif
+
+	if(memcmp(ptbl, ptbl_r, sizeof(struct ptable)) == 0) {
+		*same = 1;
+	}
+
+	free(ptbl);
+	free(ptbl_r);
+	return 0;
+}
+
+int mmc_parts_format(void)
+{
+	if (!mmc_blkdev) {
+		printf("mmc block device hasn't initialize\n");
+		return -1;
+	}
+
+	return do_format();
+}
+
+int mmc_parts_init(void)
+{
+	struct mmc* mmc = NULL;
+
+	/* We register only one device. So, the dev id is always 0 */
+	mmc = find_mmc_device(CONFIG_MMC_DEV_NUM);
+	if (!mmc) {
+		printf("make_write_mbr_ebr: mmc device not found!!\n");
+		return -1;
+	}
+	mmc_init(mmc);
+
+	if (part_nums > EFI_ENTRIES) {
+		printf("too many mmc parts\n");
+		return -1;
+	}
+
+
+	mmc_blkdev = get_dev_by_name(CONFIG_MMC_DEV_NAME);
+	if (!mmc_blkdev) {
+		printf("%s: fastboot device %s not found\n",
+						__func__, CONFIG_MMC_DEV_NAME);
+		return -1;
+	}
+
+	return 0;
+}
+
diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h
new file mode 100644
index 0000000000..16dcf9ff61
--- /dev/null
+++ b/drivers/mmc/mmc_private.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2008,2010 Freescale Semiconductor, Inc
+ * Andy Fleming
+ *
+ * Based (loosely) on the Linux code
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _MMC_PRIVATE_H_
+#define _MMC_PRIVATE_H_
+
+#include <mmc.h>
+
+extern int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+			struct mmc_data *data);
+extern int mmc_send_status(struct mmc *mmc, int timeout);
+extern int mmc_set_blocklen(struct mmc *mmc, int len);
+
+#ifndef CONFIG_SPL_BUILD
+
+extern unsigned long mmc_berase(int dev_num, lbaint_t start, lbaint_t blkcnt);
+
+extern ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt,
+		const void *src);
+
+#else /* CONFIG_SPL_BUILD */
+
+/* SPL will never write or erase, declare dummies to reduce code size. */
+
+static inline unsigned long mmc_berase(int dev_num, lbaint_t start,
+		lbaint_t blkcnt)
+{
+	return 0;
+}
+
+static inline ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt,
+		const void *src)
+{
+	return 0;
+}
+
+#endif /* CONFIG_SPL_BUILD */
+
+#endif /* _MMC_PRIVATE_H_ */
diff --git a/drivers/mmc/mmc_spl_load.c b/drivers/mmc/mmc_spl_load.c
new file mode 100644
index 0000000000..a9f36a748c
--- /dev/null
+++ b/drivers/mmc/mmc_spl_load.c
@@ -0,0 +1,111 @@
+#include <common.h>
+#include <mmc.h>
+#include <asm/errno.h>
+#include <asm/arch/spl_board_info.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SPL_CHECK_IMAGE
+int check_uimage(unsigned int *buf);
+#endif
+
+static struct mmc *boot_mmc = NULL;
+
+int emmc_spl_load_image(uint32_t offs, unsigned int size, void *dst)
+{
+	unsigned long err;
+	unsigned int start_block, block_num, block_size;
+
+	block_size = 512;
+	start_block = offs/block_size;
+	block_num = (size + block_size - 1)/block_size;
+
+	if (!boot_mmc) {
+		printf("spl emmc not initialized\n");
+		return -ENODEV;
+	}
+
+	err = boot_mmc->block_dev.block_read(CONFIG_MMC_DEV_NUM,
+			start_block,
+			block_num, (void *)dst);
+
+	if (err <= 0) {
+		printf("spl emmc read err %d\n", (unsigned int)err);
+		return err;
+	}
+	return 0;
+}
+
+extern int mmc_set_host_mclk_adj_inv(struct mmc *mmc, u8 adj, u8 inv);
+
+void emmc_init(void)
+{
+	int err;
+	int i = 0;
+	struct spl_emmc_info *info = get_bd_spl_emmc_info();
+
+	info->manufacturer_id = 0;
+
+	mmc_initialize(gd->bd);
+
+	boot_mmc = find_mmc_device(CONFIG_MMC_DEV_NUM);
+	if (!boot_mmc) {
+		puts("spl emmc device not found\n");
+		return;
+	}
+
+	for(; i < 32; i++){
+		int adj = i % 16;
+		int inv = (i >= 16)? 1: 0;
+
+		if(mmc_set_host_mclk_adj_inv(boot_mmc, adj, inv) < 0){
+			printf("mmc_set_host_mclk_adj_inv failed \n");
+			boot_mmc = NULL;
+			return;
+		}
+
+		err = mmc_init(boot_mmc);
+		if (err) {
+			printf("spl emmc init failed, err %d\n", err);
+		} else
+			break;
+	}
+
+	if (i < 32){
+		info->manufacturer_id = boot_mmc->cid[0] >> 24;
+		printf("boot_mmc mfr id = %x \n",  boot_mmc->cid[0] >> 24);
+	} else{
+		printf("After loop, spl emmc init failed.\n");
+		boot_mmc = NULL;
+		return;
+	}
+}
+
+/*
+ * The main entry for EMMC booting. It's necessary that SDRAM is already
+ * configured and available since this code loads the main U-Boot image
+ * from EMMC into SDRAM and starts it from there.
+ */
+void emmc_boot(void)
+{
+	__attribute__((noreturn)) void (*uboot)(void);
+
+	/*
+	 * Load U-Boot image from EMMC into RAM
+	 */
+	emmc_spl_load_image(CONFIG_SYS_EMMC_U_BOOT_OFFS,
+			CONFIG_SYS_EMMC_U_BOOT_SIZE,
+			(void *)CONFIG_SYS_EMMC_U_BOOT_DST);
+
+#ifdef CONFIG_SPL_CHECK_IMAGE
+	if (check_uimage((unsigned int*)CONFIG_SYS_EMMC_U_BOOT_DST)) {
+		printf("EMMC boot failed.\n");
+		return;
+	}
+#endif
+
+	/*
+	 * Jump to U-Boot image
+	 */
+	uboot = (void *)CONFIG_SYS_EMMC_U_BOOT_START;
+	(*uboot)();
+}
diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
new file mode 100644
index 0000000000..2bc21d32db
--- /dev/null
+++ b/drivers/mmc/mmc_write.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright 2008, Freescale Semiconductor, Inc
+ * Andy Fleming
+ *
+ * Based vaguely on the Linux code
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <part.h>
+#include "mmc_private.h"
+
+static ulong mmc_erase_t(struct mmc *mmc, ulong start, lbaint_t blkcnt)
+{
+	struct mmc_cmd cmd;
+	ulong end;
+	int err, start_cmd, end_cmd;
+
+	if (mmc->high_capacity) {
+		end = start + blkcnt - 1;
+	} else {
+		end = (start + blkcnt - 1) * mmc->write_bl_len;
+		start *= mmc->write_bl_len;
+	}
+
+	if (IS_SD(mmc)) {
+		start_cmd = SD_CMD_ERASE_WR_BLK_START;
+		end_cmd = SD_CMD_ERASE_WR_BLK_END;
+	} else {
+		start_cmd = MMC_CMD_ERASE_GROUP_START;
+		end_cmd = MMC_CMD_ERASE_GROUP_END;
+	}
+
+	cmd.cmdidx = start_cmd;
+	cmd.cmdarg = start;
+	cmd.resp_type = MMC_RSP_R1;
+
+	err = mmc_send_cmd(mmc, &cmd, NULL);
+	if (err)
+		goto err_out;
+
+	cmd.cmdidx = end_cmd;
+	cmd.cmdarg = end;
+
+	err = mmc_send_cmd(mmc, &cmd, NULL);
+	if (err)
+		goto err_out;
+
+	cmd.cmdidx = MMC_CMD_ERASE;
+	cmd.cmdarg = SECURE_ERASE;
+	cmd.resp_type = MMC_RSP_R1b;
+
+	err = mmc_send_cmd(mmc, &cmd, NULL);
+	if (err)
+		goto err_out;
+
+	return 0;
+
+err_out:
+	puts("mmc erase failed\n");
+	return err;
+}
+
+unsigned long mmc_berase(int dev_num, lbaint_t start, lbaint_t blkcnt)
+{
+	int err = 0;
+	struct mmc *mmc = find_mmc_device(dev_num);
+	lbaint_t blk = 0, blk_r = 0;
+	int timeout = 1000;
+
+	if (!mmc)
+		return -1;
+
+	if ((start % mmc->erase_grp_size) || (blkcnt % mmc->erase_grp_size))
+		printf("\n\nCaution! Your devices Erase group is 0x%x\n"
+		       "The erase range would be change to "
+		       "0x" LBAF "~0x" LBAF "\n\n",
+		       mmc->erase_grp_size, start & ~(mmc->erase_grp_size - 1),
+		       ((start + blkcnt + mmc->erase_grp_size)
+		       & ~(mmc->erase_grp_size - 1)) - 1);
+
+	/* try to erase all at one time */
+	err = mmc_erase_t(mmc, start, blkcnt);
+	if(!err) {
+		if(!mmc_send_status(mmc, timeout*10))
+			return blkcnt;
+	}
+
+	/* erase group one by one */
+	while (blk < blkcnt) {
+		blk_r = ((blkcnt - blk) > mmc->erase_grp_size) ?
+			mmc->erase_grp_size : (blkcnt - blk);
+		err = mmc_erase_t(mmc, start + blk, blk_r);
+		if (err)
+			break;
+
+		blk += blk_r;
+
+		/* Waiting for the ready status */
+		if (mmc_send_status(mmc, timeout))
+			return 0;
+	}
+
+	return blk;
+}
+
+static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t start,
+		lbaint_t blkcnt, const void *src)
+{
+	struct mmc_cmd cmd;
+	struct mmc_data data;
+	int timeout = 1000;
+
+	if ((start + blkcnt) > mmc->block_dev.lba) {
+		printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
+		       start + blkcnt, mmc->block_dev.lba);
+		return 0;
+	}
+
+	if (blkcnt == 0)
+		return 0;
+	else if (blkcnt == 1)
+		cmd.cmdidx = MMC_CMD_WRITE_SINGLE_BLOCK;
+	else
+		cmd.cmdidx = MMC_CMD_WRITE_MULTIPLE_BLOCK;
+
+	if (mmc->high_capacity)
+		cmd.cmdarg = start;
+	else
+		cmd.cmdarg = start * mmc->write_bl_len;
+
+	cmd.resp_type = MMC_RSP_R1;
+
+	data.src = src;
+	data.blocks = blkcnt;
+	data.blocksize = mmc->write_bl_len;
+	data.flags = MMC_DATA_WRITE;
+
+	if (mmc_send_cmd(mmc, &cmd, &data)) {
+		printf("mmc write failed\n");
+		return 0;
+	}
+
+	/* SPI multiblock writes terminate using a special
+	 * token, not a STOP_TRANSMISSION request.
+	 */
+	if (!mmc_host_is_spi(mmc) && blkcnt > 1) {
+		cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
+		cmd.cmdarg = 0;
+		cmd.resp_type = MMC_RSP_R1b;
+		if (mmc_send_cmd(mmc, &cmd, NULL)) {
+			printf("mmc fail to send stop cmd\n");
+			return 0;
+		}
+	}
+
+	/* Waiting for the ready status */
+	if (mmc_send_status(mmc, timeout))
+		return 0;
+
+	return blkcnt;
+}
+
+ulong mmc_bwrite(int dev_num, lbaint_t start, lbaint_t blkcnt, const void *src)
+{
+	lbaint_t cur, blocks_todo = blkcnt;
+
+	struct mmc *mmc = find_mmc_device(dev_num);
+	if (!mmc)
+		return 0;
+
+	if (mmc_set_blocklen(mmc, mmc->write_bl_len))
+		return 0;
+
+	do {
+		cur = (blocks_todo > mmc->b_max) ?  mmc->b_max : blocks_todo;
+		if (mmc_write_blocks(mmc, start, cur, src) != cur)
+			return 0;
+		blocks_todo -= cur;
+		start += cur;
+		src += cur * mmc->write_bl_len;
+	} while (blocks_todo > 0);
+
+	return blkcnt;
+}
diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c
index 35c6bdabb0..4187a94120 100644
--- a/drivers/mmc/mxsmmc.c
+++ b/drivers/mmc/mxsmmc.c
@@ -133,7 +133,8 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 		/* READ or WRITE */
 		if (data->flags & MMC_DATA_READ) {
 			ctrl0 |= SSP_CTRL0_READ;
-		} else if (priv->mmc_is_wp(mmc->block_dev.dev)) {
+		} else if (priv->mmc_is_wp &&
+			priv->mmc_is_wp(mmc->block_dev.dev)) {
 			printf("MMC%d: Can not write a locked card!\n",
 				mmc->block_dev.dev);
 			return UNUSABLE_ERR;
@@ -406,7 +407,7 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int))
 	 */
 	mmc->f_min = 400000;
 	mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2;
-	mmc->b_max = 0x40;
+	mmc->b_max = 0x20;
 
 	mmc_register(mmc);
 	return 0;
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 2400db2f35..afd9b30b51 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -29,10 +29,15 @@
 #include <i2c.h>
 #include <twl4030.h>
 #include <twl6030.h>
+#include <twl6035.h>
 #include <asm/io.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
 
+/* common definitions for all OMAPs */
+#define SYSCTL_SRC	(1 << 25)
+#define SYSCTL_SRD	(1 << 26)
+
 /* If we fail after 1 second wait, something is really bad */
 #define MAX_RETRY_MS	1000
 
@@ -45,8 +50,8 @@ static struct mmc hsmmc_dev[2];
 static void omap4_vmmc_pbias_config(struct mmc *mmc)
 {
 	u32 value = 0;
-	struct omap4_sys_ctrl_regs *const ctrl =
-		(struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
+	struct omap_sys_ctrl_regs *const ctrl =
+		(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
 
 
 	value = readl(&ctrl->control_pbiaslite);
@@ -60,17 +65,51 @@ static void omap4_vmmc_pbias_config(struct mmc *mmc)
 }
 #endif
 
-unsigned char mmc_board_init(struct mmc *mmc)
+#if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
+static void omap5_pbias_config(struct mmc *mmc)
 {
-#if defined(CONFIG_TWL4030_POWER)
-	twl4030_power_mmc_init();
+	u32 value = 0;
+	struct omap_sys_ctrl_regs *const ctrl =
+		(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
+
+	value = readl(&ctrl->control_pbias);
+	value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
+	value |= SDCARD_BIAS_HIZ_MODE;
+	writel(value, &ctrl->control_pbias);
+
+	twl6035_mmc1_poweron_ldo();
+
+	value = readl(&ctrl->control_pbias);
+	value &= ~SDCARD_BIAS_HIZ_MODE;
+	value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ;
+	writel(value, &ctrl->control_pbias);
+
+	value = readl(&ctrl->control_pbias);
+	if (value & (1 << 23)) {
+		value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
+		value |= SDCARD_BIAS_HIZ_MODE;
+		writel(value, &ctrl->control_pbias);
+	}
+}
 #endif
 
+unsigned char mmc_board_init(struct mmc *mmc)
+{
 #if defined(CONFIG_OMAP34XX)
 	t2_t *t2_base = (t2_t *)T2_BASE;
 	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+	u32 pbias_lite;
 
-	writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
+	pbias_lite = readl(&t2_base->pbias_lite);
+	pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
+	writel(pbias_lite, &t2_base->pbias_lite);
+#endif
+#if defined(CONFIG_TWL4030_POWER)
+	twl4030_power_mmc_init();
+	mdelay(100);	/* ramp-up delay from Linux code */
+#endif
+#if defined(CONFIG_OMAP34XX)
+	writel(pbias_lite | PBIASLITEPWRDNZ1 |
 		PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 		&t2_base->pbias_lite);
 
@@ -80,6 +119,11 @@ unsigned char mmc_board_init(struct mmc *mmc)
 	writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 		&t2_base->devconf1);
 
+	/* Change from default of 52MHz to 26MHz if necessary */
+	if (!(mmc->host_caps & MMC_MODE_HS_52MHz))
+		writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
+			&t2_base->ctl_prog_io1);
+
 	writel(readl(&prcm_base->fclken1_core) |
 		EN_MMC1 | EN_MMC2 | EN_MMC3,
 		&prcm_base->fclken1_core);
@@ -94,6 +138,10 @@ unsigned char mmc_board_init(struct mmc *mmc)
 	if (mmc->block_dev.dev == 0)
 		omap4_vmmc_pbias_config(mmc);
 #endif
+#if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
+	if (mmc->block_dev.dev == 0)
+		omap5_pbias_config(mmc);
+#endif
 
 	return 0;
 }
@@ -189,6 +237,27 @@ static int mmc_init_setup(struct mmc *mmc)
 	return 0;
 }
 
+/*
+ * MMC controller internal finite state machine reset
+ *
+ * Used to reset command or data internal state machines, using respectively
+ * SRC or SRD bit of SYSCTL register
+ */
+static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
+{
+	ulong start;
+
+	mmc_reg_out(&mmc_base->sysctl, bit, bit);
+
+	start = get_timer(0);
+	while ((readl(&mmc_base->sysctl) & bit) != 0) {
+		if (get_timer(0) - start > MAX_RETRY_MS) {
+			printf("%s: timedout waiting for sysctl %x to clear\n",
+				__func__, bit);
+			return;
+		}
+	}
+}
 
 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 			struct mmc_data *data)
@@ -209,7 +278,8 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 	start = get_timer(0);
 	while (readl(&mmc_base->stat)) {
 		if (get_timer(0) - start > MAX_RETRY_MS) {
-			printf("%s: timedout waiting for stat!\n", __func__);
+			printf("%s: timedout waiting for STAT (%x) to clear\n",
+				__func__, readl(&mmc_base->stat));
 			return TIMEOUT;
 		}
 	}
@@ -277,9 +347,10 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 		}
 	} while (!mmc_stat);
 
-	if ((mmc_stat & IE_CTO) != 0)
+	if ((mmc_stat & IE_CTO) != 0) {
+		mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 		return TIMEOUT;
-	else if ((mmc_stat & ERRI_MASK) != 0)
+	} else if ((mmc_stat & ERRI_MASK) != 0)
 		return -1;
 
 	if (mmc_stat & CC_MASK) {
@@ -330,6 +401,9 @@ static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
 			}
 		} while (mmc_stat == 0);
 
+		if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
+			mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
+
 		if ((mmc_stat & ERRI_MASK) != 0)
 			return 1;
 
@@ -382,6 +456,9 @@ static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 			}
 		} while (mmc_stat == 0);
 
+		if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
+			mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
+
 		if ((mmc_stat & ERRI_MASK) != 0)
 			return 1;
 
@@ -463,7 +540,7 @@ static void mmc_set_ios(struct mmc *mmc)
 	writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 }
 
-int omap_mmc_init(int dev_index)
+int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max)
 {
 	struct mmc *mmc;
 
@@ -494,11 +571,22 @@ int omap_mmc_init(int dev_index)
 		return 1;
 	}
 	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
-	mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
-				MMC_MODE_HC;
+	mmc->host_caps = (MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
+				MMC_MODE_HC) & ~host_caps_mask;
 
 	mmc->f_min = 400000;
-	mmc->f_max = 52000000;
+
+	if (f_max != 0)
+		mmc->f_max = f_max;
+	else {
+		if (mmc->host_caps & MMC_MODE_HS) {
+			if (mmc->host_caps & MMC_MODE_HS_52MHz)
+				mmc->f_max = 52000000;
+			else
+				mmc->f_max = 26000000;
+		} else
+			mmc->f_max = 20000000;
+	}
 
 	mmc->b_max = 0;
 
diff --git a/drivers/mmc/rda_mmc.c b/drivers/mmc/rda_mmc.c
new file mode 100644
index 0000000000..1a527e810e
--- /dev/null
+++ b/drivers/mmc/rda_mmc.c
@@ -0,0 +1,892 @@
+#include <asm/io.h>
+#include "common.h"
+#include <errno.h>
+#include <mmc.h>
+#include <malloc.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/reg_mmc.h>
+#include <asm/arch/reg_ifc.h>
+#include <asm/arch/ifc.h>
+#include <asm/arch/rda_sys.h>
+#include <mmc/mmcpart.h>
+#include <rda/tgt_ap_board_config.h>
+#include <asm/arch/spl_board_info.h>
+
+//#define SDMMC_DEBUG
+
+#ifdef CONFIG_RDA_FPGA
+#define CONFIG_APB2_CLOCK         26000000
+#else
+#define CONFIG_APB2_CLOCK         200000000
+#endif
+
+#define SECOND                    * CONFIG_SYS_HZ_CLOCK
+#define MCD_CMD_TIMEOUT           ( 2 SECOND / 10 )
+#define MCD_RESP_TIMEOUT          ( 2 SECOND / 10 )
+#define MCD_DATA_TIMEOUT          ( 2 SECOND )
+#define MMC_DEV_NUM 2
+struct mmc_host {
+	int dev_num;
+	u32 phyaddr;
+	u8  mclk_adj;
+	u8  mclk_inv;
+	u16  reserved;
+};
+
+struct emmc_mfr_mclk_adj_inv {
+	u8 mfr_id;
+	u8 mclk_adj;
+	u8 mclk_inv;
+	u8 mclk_inv_kernel;/*Because the u-boot and kernel mode isn't same, so inv set is different sometime*/
+};
+
+static const struct emmc_mfr_mclk_adj_inv emmc_mclk_adj_inv[] = {
+	{MMC_MFR_TOSHIBA, 0, 0, 1},
+	{MMC_MFR_GIGADEVICE, 0, 0, 1},
+	{MMC_MFR_SAMSUNG, 0, 0, 1},
+	{MMC_MFR_SANDISK, 0, 0, 1},
+	{MMC_MFR_HYNIX, 0, 0, 1},
+	{MMC_MFR_MICRON, 0, 0, 1},
+	{MMC_MFR_MICRON1, 0, 0, 1},
+	{0, 0, 0, 0},
+};
+
+struct mmc mmc_device_glob[MMC_DEV_NUM];
+struct mmc_host mmc_host_dev[MMC_DEV_NUM];
+static int rda_ddr_mode = 0;
+
+typedef struct
+{
+	/// This address in the system memory
+	u8* sysMemAddr;
+	/// Quantity of data to transfer, in blocks
+	u32 blockNum;
+	/// Block size
+	u32 blockSize;
+	HAL_SDMMC_DIRECTION_T direction;
+	HAL_IFC_REQUEST_ID_T ifcReq;
+	u32 channel;
+} HAL_SDMMC_TRANSFER_T;
+
+u64 hal_getticks(void)
+{
+	return get_ticks();
+}
+
+static void hal_send_cmd(struct mmc *dev, struct mmc_cmd *cmd, struct mmc_data *data)
+{
+	u32 configReg = 0;
+	struct mmc_host *host = dev->priv;
+	u32 ddr_bits = 0;
+	HWP_SDMMC_T *  hwp_sdmmc = (HWP_SDMMC_T*)(host->phyaddr);
+
+#if defined(CONFIG_MACH_RDA8810E) || defined(CONFIG_MACH_RDA8810H)
+	/* check ddr mode is enabled */
+	if(rda_ddr_mode) {
+		ddr_bits = (1<<17) | (1<<23);
+	}
+#endif
+
+	//hwp_sdmmc->SDMMC_CONFIG = SDMMC_AUTO_FLAG_EN;
+	hwp_sdmmc->SDMMC_CONFIG = 0x00000000 | ddr_bits;
+
+	configReg = SDMMC_SDMMC_SENDCMD;
+	if (cmd->resp_type & MMC_RSP_PRESENT) {
+		configReg |= SDMMC_RSP_EN;
+		if (cmd->resp_type & MMC_RSP_136)
+			configReg |= SDMMC_RSP_SEL_R2;
+		else if (cmd->resp_type & MMC_RSP_CRC)
+			configReg |= SDMMC_RSP_SEL_OTHER;
+		else
+			configReg |= SDMMC_RSP_SEL_R3;
+	}
+
+	/* cases for data transfer */
+	if (cmd->cmdidx == MMC_CMD_READ_SINGLE_BLOCK) {
+		configReg |= (SDMMC_RD_WT_EN | SDMMC_RD_WT_SEL_READ);
+	} else if (cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) {
+		configReg |= (SDMMC_RD_WT_EN | SDMMC_RD_WT_SEL_READ | SDMMC_S_M_SEL_MULTIPLE);
+	} else if (cmd->cmdidx == MMC_CMD_WRITE_SINGLE_BLOCK) {
+		configReg |= (SDMMC_RD_WT_EN | SDMMC_RD_WT_SEL_WRITE);
+#if defined(CONFIG_MACH_RDA8810E) || defined(CONFIG_MACH_RDA8810H)
+		/* when do write, the edge selection is reverse.
+		 * it's a workaround. */
+		if(rda_ddr_mode) {
+			ddr_bits = (1<<17);
+		}
+#endif
+	} else if (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK) {
+		configReg |= (SDMMC_RD_WT_EN | SDMMC_RD_WT_SEL_WRITE | SDMMC_S_M_SEL_MULTIPLE);
+#if defined(CONFIG_MACH_RDA8810E) || defined(CONFIG_MACH_RDA8810H)
+		/* when do write, the edge selection is reverse.
+		 * it's a workaround. */
+		if(rda_ddr_mode) {
+			ddr_bits = (1<<17);
+		}
+#endif
+	} else if (cmd->cmdidx == SD_CMD_APP_SEND_SCR) {
+		configReg |= (SDMMC_RD_WT_EN | SDMMC_RD_WT_SEL_READ);
+	} else if (cmd->cmdidx == SD_CMD_SWITCH_FUNC && data) {
+		configReg |= (SDMMC_RD_WT_EN | SDMMC_RD_WT_SEL_READ);
+	} else if (cmd->cmdidx == MMC_CMD_SEND_EXT_CSD) {
+		configReg |= (SDMMC_RD_WT_EN | SDMMC_RD_WT_SEL_READ);
+	}
+
+	configReg |= ddr_bits;
+#ifdef SDMMC_DEBUG
+	printf("  idx_reg = 0x%08x, arg_reg = 0x%08x, config = 0x%08x\n",
+		SDMMC_COMMAND(cmd->cmdidx),
+		SDMMC_ARGUMENT(cmd->cmdarg),
+		configReg);
+#endif
+
+	hwp_sdmmc->SDMMC_CMD_INDEX = SDMMC_COMMAND(cmd->cmdidx);
+	hwp_sdmmc->SDMMC_CMD_ARG   = SDMMC_ARGUMENT(cmd->cmdarg);
+	//hwp_sdmmc->SDMMC_CONFIG    = configReg |SDMMC_AUTO_FLAG_EN;
+	hwp_sdmmc->SDMMC_CONFIG    = configReg;
+}
+
+static int hal_cmd_done(struct mmc *dev)
+{
+	struct mmc_host *host = dev->priv;
+	HWP_SDMMC_T*  hwp_sdmmc = (HWP_SDMMC_T*)(host->phyaddr);
+
+	return (!(hwp_sdmmc->SDMMC_STATUS & SDMMC_NOT_SDMMC_OVER));
+}
+
+static int hal_wait_cmd_done(struct mmc *dev)
+{
+	u64 startTime = hal_getticks();
+	u64 time_out;
+
+	time_out = MCD_CMD_TIMEOUT;
+
+	while(hal_getticks() - startTime < time_out && !hal_cmd_done(dev));
+
+	if (!hal_cmd_done(dev))
+	{
+		printf("cmd waiting timeout\n");
+		return TIMEOUT;
+	}
+	else
+	{
+		return 0;
+	}
+}
+
+HAL_SDMMC_OP_STATUS_T hal_get_op_status(struct mmc *dev)
+{
+	struct mmc_host *host = dev->priv;
+	HWP_SDMMC_T*  hwp_sdmmc = (HWP_SDMMC_T*)(host->phyaddr);
+
+	return ((HAL_SDMMC_OP_STATUS_T)(u32)hwp_sdmmc->SDMMC_STATUS);
+}
+
+static int hal_wait_cmd_resp(struct mmc *dev)
+{
+	HAL_SDMMC_OP_STATUS_T status = hal_get_op_status(dev);
+	u64 startTime = hal_getticks();
+	u64 rsp_time_out;
+
+	rsp_time_out = MCD_RESP_TIMEOUT;
+
+	while(hal_getticks() - startTime < rsp_time_out &&status.fields.noResponseReceived){
+		status = hal_get_op_status(dev);
+	}
+
+	if (status.fields.noResponseReceived){
+		printf("  response timeout\n");
+		return TIMEOUT;
+	}
+
+	if(status.fields.responseCrcError){
+		printf("  response CRC error\n");
+		return -EILSEQ;
+	}
+
+	return 0;
+}
+
+static void hal_get_resp(struct mmc *dev, struct mmc_cmd *cmd)
+{
+	struct mmc_host *host = dev->priv;
+	HWP_SDMMC_T*  hwp_sdmmc = (HWP_SDMMC_T*)(host->phyaddr);
+
+	if (cmd->resp_type & MMC_RSP_PRESENT) {
+		if (cmd->resp_type & MMC_RSP_136) {
+			cmd->response[0] = hwp_sdmmc->SDMMC_RESP_ARG3;
+			cmd->response[1] = hwp_sdmmc->SDMMC_RESP_ARG2;
+			cmd->response[2] = hwp_sdmmc->SDMMC_RESP_ARG1;
+			cmd->response[3] = hwp_sdmmc->SDMMC_RESP_ARG0 << 1;
+		}else {
+			cmd->response[0] = hwp_sdmmc->SDMMC_RESP_ARG3;
+			cmd->response[1] = 0;
+			cmd->response[2] = 0;
+			cmd->response[3] = 0;
+		}
+	}
+	else {
+		cmd->response[0] = 0;
+		cmd->response[1] = 0;
+		cmd->response[2] = 0;
+		cmd->response[3] = 0;
+	}
+}
+
+static int hal_data_transfer_start(struct mmc *dev,HAL_SDMMC_TRANSFER_T* transfer)
+{
+	u32 length = 0;
+	u32 lengthExp = 0;
+	struct mmc_host *host = dev->priv;
+	HWP_SDMMC_T*  hwp_sdmmc = (HWP_SDMMC_T*)(host->phyaddr);
+
+	length = transfer->blockSize;
+
+	// The block size register
+	while (length != 1)
+	{
+		length >>= 1;
+		lengthExp++;
+	}
+
+	// Configure amount of data
+	hwp_sdmmc->SDMMC_BLOCK_CNT  = SDMMC_SDMMC_BLOCK_CNT(transfer->blockNum);
+	hwp_sdmmc->SDMMC_BLOCK_SIZE = SDMMC_SDMMC_BLOCK_SIZE(lengthExp);
+
+	// Configure Bytes reordering
+	hwp_sdmmc->apbi_ctrl_sdmmc = SDMMC_SOFT_RST_L | SDMMC_L_ENDIAN(1);
+	//hwp_sdmmc->apbi_ctrl_sdmmc = SDMMC_L_ENDIAN(1);
+
+	switch (transfer->direction){
+		case HAL_SDMMC_DIRECTION_READ:
+			if (0 == host->dev_num)
+				transfer->ifcReq = HAL_IFC_SDMMC_RX;
+			else
+				transfer->ifcReq = HAL_IFC_SDMMC3_RX;
+			break;
+
+		case HAL_SDMMC_DIRECTION_WRITE:
+			if (0 == host->dev_num)
+				transfer->ifcReq = HAL_IFC_SDMMC_TX;
+			else
+				transfer->ifcReq = HAL_IFC_SDMMC3_TX;
+			break;
+
+		default:
+			printf("hal_SdmmcTransfer with wrong direction %d\n", transfer->direction);
+		return -EILSEQ;
+	}
+
+	transfer->channel = hal_IfcTransferStart(transfer->ifcReq, transfer->sysMemAddr,
+					transfer->blockNum*transfer->blockSize,
+					HAL_IFC_SIZE_32_MODE_MANUAL);
+	if (transfer->channel == HAL_UNKNOWN_CHANNEL){
+		printf("hal_IfcTransferStart error\n");
+		return -EILSEQ;
+	}
+	return 0;
+}
+
+static void hal_data_transfer_stop(struct mmc *dev, HAL_SDMMC_TRANSFER_T* transfer)
+{
+	struct mmc_host *host = dev->priv;
+	HWP_SDMMC_T*  hwp_sdmmc = (HWP_SDMMC_T*)(host->phyaddr);
+
+	// Configure amount of data
+	hwp_sdmmc->SDMMC_BLOCK_CNT  = SDMMC_SDMMC_BLOCK_CNT(0);
+	hwp_sdmmc->SDMMC_BLOCK_SIZE = SDMMC_SDMMC_BLOCK_SIZE(0);
+
+	//  Put the FIFO in reset state.
+	//hwp_sdmmc->apbi_ctrl_sdmmc = 0 | SDMMC_L_ENDIAN(1);
+	hwp_sdmmc->apbi_ctrl_sdmmc = SDMMC_SOFT_RST_L | SDMMC_L_ENDIAN(1);
+
+	hal_IfcChannelFlush(transfer->ifcReq, transfer->channel);
+	while(!hal_IfcChannelIsFifoEmpty(transfer->ifcReq, transfer->channel));
+	hal_IfcChannelRelease(transfer->ifcReq, transfer->channel);
+	transfer->channel = HAL_UNKNOWN_CHANNEL;
+}
+
+static int hal_data_transfer_done(struct mmc *dev, HAL_SDMMC_TRANSFER_T* transfer)
+{
+	struct mmc_host *host = dev->priv;
+	HWP_SDMMC_T*  hwp_sdmmc = (HWP_SDMMC_T*)(host->phyaddr);
+
+	// The link is not full duplex. We check both the
+	// direction, but only one can be in progress at a time.
+
+	if (transfer->channel != HAL_UNKNOWN_CHANNEL)
+	{
+		// Operation in progress is a read.
+		// The SDMMC module itself can know it has finished
+		if ((hwp_sdmmc->SDMMC_INT_STATUS & SDMMC_DAT_OVER_INT)
+		 && (hwp_sysIfc->std_ch[transfer->channel].tc == 0))
+		{
+			// Transfer is over
+			hwp_sdmmc->SDMMC_INT_CLEAR = SDMMC_DAT_OVER_CL;
+			hal_IfcChannelRelease(transfer->ifcReq, transfer->channel);
+
+			// We finished a read
+			transfer->channel = HAL_UNKNOWN_CHANNEL;
+
+			//  Put the FIFO in reset state.
+			//hwp_sdmmc->apbi_ctrl_sdmmc = 0 | SDMMC_L_ENDIAN(1);
+			hwp_sdmmc->apbi_ctrl_sdmmc = SDMMC_SOFT_RST_L | SDMMC_L_ENDIAN(1);
+
+			return 1;
+		}
+		else {
+			return 0;
+		}
+	}
+	else {
+		printf("unknown channel\n");
+		return 1;
+	}
+}
+
+static int hal_wait_data_transfer_done(struct mmc *dev,
+			HAL_SDMMC_TRANSFER_T* transfer)
+{
+	u64 startTime = hal_getticks();
+	u64 tran_time_out = MCD_DATA_TIMEOUT * transfer->blockNum;
+#ifdef SDMMC_DEBUG
+	struct mmc_host *host = dev->priv;
+	HWP_SDMMC_T*  hwp_sdmmc = (HWP_SDMMC_T*)(host->phyaddr);
+#endif
+
+	// Wait
+	while(!hal_data_transfer_done(dev, transfer)) {
+		if (hal_getticks() - startTime > (tran_time_out)) {
+			printf("data transfer timeout\n");
+#ifdef SDMMC_DEBUG
+			printf("SDMMC_STATUS=%#x, INT_STATUS=%#x\n", hwp_sdmmc->SDMMC_STATUS,
+					hwp_sdmmc->SDMMC_INT_STATUS);
+#endif
+			hal_data_transfer_stop(dev, transfer);
+			return TIMEOUT;
+		}
+	}
+	return 0;
+}
+
+static int hal_data_read_check_crc(struct mmc *dev)
+{
+	HAL_SDMMC_OP_STATUS_T operationStatus;
+
+	operationStatus = hal_get_op_status(dev);
+	if (operationStatus.fields.dataError != 0) {
+	// 0 means no CRC error during transmission
+#ifdef SDMMC_DEBUG
+		printf("data_read_check_crc fail, status:%08x\n",
+				operationStatus.reg);
+#endif
+		return -EILSEQ;
+	} else {
+		return 0;
+	}
+}
+
+static int hal_data_write_check_crc(struct mmc *dev)
+{
+	HAL_SDMMC_OP_STATUS_T operationStatus;
+
+	operationStatus = hal_get_op_status(dev);
+	if (operationStatus.fields.crcStatus != 2) {
+	// 0b010 = transmissionRight TODO a macro ?
+#ifdef SDMMC_DEBUG
+		printf("data_write_check_crc fail, status:%08x\n",
+				operationStatus.reg);
+#endif
+		return -EILSEQ;
+	} else {
+		return 0;
+	}
+}
+
+/* send command to the mmc card and wait for results */
+static int do_command(struct mmc *dev,
+			    struct mmc_cmd *cmd,
+			    struct mmc_data *data)
+{
+	int result;
+	//struct mmc_host *host = dev->priv;
+
+#ifdef SDMMC_DEBUG
+	printf("do_command, cmdidx = %d, cmdarg = 0x%08x, resp_type = %x\n",
+		cmd->cmdidx, cmd->cmdarg, cmd->resp_type);
+#endif
+
+	hal_send_cmd(dev, cmd, data);
+	result = hal_wait_cmd_done(dev);
+	if (result)
+		return result;
+	if (cmd->resp_type & MMC_RSP_PRESENT)
+	{
+		result= hal_wait_cmd_resp(dev);
+		if (result)
+			return result;
+	}
+	hal_get_resp(dev, cmd);
+
+#ifdef SDMMC_DEBUG
+	printf("  response: %08x %08x %08x %08x\n",
+		cmd->response[0], cmd->response[1],
+		cmd->response[2], cmd->response[3]);
+#endif
+
+	/* After CMD2 set RCA to a none zero value. */
+	//if (cmd->cmdidx == MMC_CMD_ALL_SEND_CID)
+	//	dev->rca = 10;
+
+	/* After CMD3 open drain is switched off and push pull is used. */
+	//if (cmd->cmdidx == MMC_CMD_SET_RELATIVE_ADDR) {
+	// we don't actually need this
+	//}
+
+	return result;
+}
+
+static int do_data_transfer(struct mmc *dev,
+			    struct mmc_cmd *cmd,
+			    struct mmc_data *data)
+{
+	int result = 0;
+	//struct mmc_host *host = dev->priv;
+	HAL_SDMMC_TRANSFER_T data_transfer;
+
+#ifdef SDMMC_DEBUG
+	printf("do_data_transfer, cmdidx = %d, flag = %d, blks = %d, addr = 0x%08x\n",
+		cmd->cmdidx, data->flags, data->blocks,
+		(data->flags & MMC_DATA_READ)?(u32)data->dest:(u32)data->src);
+#endif
+
+	if (data->flags & MMC_DATA_READ) {
+		flush_dcache_range((ulong)data->dest, (ulong)data->dest +
+			data->blocks * data->blocksize);
+
+		data_transfer.sysMemAddr = (u8*)data->dest;
+		data_transfer.blockNum   = data->blocks;
+		data_transfer.blockSize  = data->blocksize;
+		data_transfer.direction  = HAL_SDMMC_DIRECTION_READ;
+
+		// Initiate data migration through Ifc.
+		result = hal_data_transfer_start(dev, &data_transfer);
+		if (result)
+			return result;
+
+		result = do_command(dev, cmd, data);
+		if (result) {
+			hal_data_transfer_stop(dev, &data_transfer);
+			return result;
+		}
+
+		result = hal_wait_data_transfer_done(dev, &data_transfer);
+		if (result)
+		{
+			hal_data_transfer_stop(dev, &data_transfer);
+			return result;
+		}
+
+		result = hal_data_read_check_crc(dev);
+		if (result)
+		{
+			printf("data read crc check fail\n");
+			return result;
+		}
+#ifdef SDMMC_DEBUG
+		{
+			int i;
+			for (i=0;i<data->blocksize;i++)
+			{
+				printf("%02x ", data->dest[i]);
+				if ((i+1)%16 == 0)
+					printf("\n");
+			}
+		}
+#endif
+		invalidate_dcache_range((ulong)data->dest,
+			(ulong)data->dest + data->blocks * data->blocksize);
+	} else if (data->flags & MMC_DATA_WRITE) {
+		flush_dcache_range((ulong)data->src, (ulong)data->src +
+			data->blocks * data->blocksize);
+
+		data_transfer.sysMemAddr = (u8*)data->src;
+		data_transfer.blockNum   = data->blocks;
+		data_transfer.blockSize  = data->blocksize;
+		data_transfer.direction  = HAL_SDMMC_DIRECTION_WRITE;
+
+		// Initiate data migration through Ifc.
+		result = hal_data_transfer_start(dev, &data_transfer);
+		if (result)
+			return result;
+
+		result = do_command(dev, cmd, data);
+		if (result) {
+			hal_data_transfer_stop(dev, &data_transfer);
+			return result;
+		}
+
+		result = hal_wait_data_transfer_done(dev, &data_transfer);
+		if (result)
+		{
+			hal_data_transfer_stop(dev, &data_transfer);
+			return result;
+		}
+
+		result = hal_data_write_check_crc(dev);
+		if (result)
+		{
+			printf("data write crc check fail\n");
+			return result;
+		}
+	}
+
+	return result;
+}
+
+static int host_request(struct mmc *dev,
+			struct mmc_cmd *cmd,
+			struct mmc_data *data)
+{
+	int result;
+
+	if (data)
+		result = do_data_transfer(dev, cmd, data);
+	else
+		result = do_command(dev, cmd, data);
+
+	return result;
+}
+
+/* MMC uses open drain drivers in the enumeration phase */
+static int mmc_host_reset(struct mmc *dev)
+{
+	return 0;
+}
+
+static void host_set_ios(struct mmc *dev)
+{
+	struct mmc_host *host = dev->priv;
+	HWP_SDMMC_T*  hwp_sdmmc = (HWP_SDMMC_T*)(host->phyaddr);
+	unsigned long clk_div;
+	unsigned long apb2_clock = CONFIG_APB2_CLOCK;
+
+	/* Ramp up the clock rate */
+	if (dev->clock) {
+		clk_div = apb2_clock / (2 * dev->clock);
+		if (apb2_clock % (2 * dev->clock))
+			clk_div ++;
+
+		if (clk_div >= 1) {
+			clk_div -= 1;
+		}
+		if (clk_div > 255) {
+		/* clock too slow */
+			clk_div = 255;
+		}
+
+		hwp_sdmmc->SDMMC_TRANS_SPEED = SDMMC_SDMMC_TRANS_SPEED(clk_div);
+		if( host->dev_num == 0 ) {
+			hwp_sdmmc->SDMMC_MCLK_ADJUST = SDMMC_SDMMC_MCLK_ADJUST(_TGT_AP_SDMMC1_MCLK_ADJ);
+#if defined(_TGT_AP_SDMMC1_MCLK_INV) && (_TGT_AP_SDMMC1_MCLK_INV)
+			hwp_sdmmc->SDMMC_MCLK_ADJUST |= SDMMC_CLK_INV;
+#endif
+#ifdef CONFIG_RDA_FPGA
+			hwp_sdmmc->SDMMC_MCLK_ADJUST = 0;
+#endif
+		} else {
+			hwp_sdmmc->SDMMC_MCLK_ADJUST = SDMMC_SDMMC_MCLK_ADJUST(host->mclk_adj);
+			if(host->mclk_inv)
+				hwp_sdmmc->SDMMC_MCLK_ADJUST |= SDMMC_CLK_INV;
+		}
+#ifdef SDMMC_DEBUG
+		printf("set clock to %d, div = %lu\n", dev->clock, clk_div);
+#endif
+	}
+
+	/* Set the bus width */
+	if (dev->bus_width) {
+#ifdef SDMMC_DEBUG
+		printf("set bus_width to %#x\n", dev->bus_width);
+#endif
+
+		switch (dev->bus_width & 0xf) {
+		case 1:
+			hwp_sdmmc->SDMMC_DATA_WIDTH = 1;
+			break;
+		case 4:
+			hwp_sdmmc->SDMMC_DATA_WIDTH = 4;
+			break;
+		case 8:
+			hwp_sdmmc->SDMMC_DATA_WIDTH = 8;
+			break;
+		default:
+			printf("invalid bus width\n");
+			break;
+		}
+
+		/* check ddr enable/disable bit from bus_width */
+		if(dev->bus_width & 0x80000000) {
+			rda_ddr_mode = 1;
+#ifdef SDMMC_DEBUG
+			printf("mmc ddr mode is enabled.\n");
+#endif
+		} else {
+			rda_ddr_mode = 0;
+		}
+	}
+}
+
+
+struct mmc *alloc_mmc_struct(unsigned int dev_num)
+{
+	struct mmc_host *host = NULL;
+	struct mmc *mmc_device = NULL;
+
+	if (dev_num >=  MMC_DEV_NUM)
+		return NULL;
+
+	host = &mmc_host_dev[dev_num];
+	if (!host)
+		return NULL;
+
+	host->dev_num = dev_num;
+	if (0 == dev_num)
+		host->phyaddr =  RDA_SDMMC1_BASE;
+	else
+		host->phyaddr =  RDA_SDMMC3_BASE;
+
+	mmc_device = &mmc_device_glob[dev_num];
+	if (!mmc_device)
+		goto err;
+
+	mmc_device->priv = host;
+	return mmc_device;
+
+err:
+	return NULL;
+}
+
+#define VOLTAGE_WINDOW_MMC 0x00FF8080
+
+/*
+ * mmc_host_init - initialize the mmc controller.
+ * Set initial clock and power for mmc slot.
+ * Initialize mmc struct and register with mmc framework.
+ */
+static int rda_mmc_host_init(struct mmc *dev)
+{
+	struct mmc_host *host = dev->priv;
+	unsigned long clk_div;
+	HWP_SDMMC_T*  hwp_sdmmc = (HWP_SDMMC_T*)(host->phyaddr);
+	struct spl_emmc_info *info = get_bd_spl_emmc_info();
+
+	// clk_div = 0;		// for APB2 = 48M, 48/2
+	//clk_div = 1;		// for APB2 = 120M, 120/4
+	clk_div = 0x21;		// for APB2 = 240M, 240/16
+
+	host->reserved = 0;
+
+	// We don't use interrupts.
+	hwp_sdmmc->SDMMC_INT_MASK = 0x0;
+	hwp_sdmmc->SDMMC_TRANS_SPEED = SDMMC_SDMMC_TRANS_SPEED(clk_div);
+	if (0 == host->dev_num){
+		hwp_sdmmc->SDMMC_MCLK_ADJUST = SDMMC_SDMMC_MCLK_ADJUST(_TGT_AP_SDMMC1_MCLK_ADJ);
+#if defined(_TGT_AP_SDMMC1_MCLK_INV) && (_TGT_AP_SDMMC1_MCLK_INV)
+		hwp_sdmmc->SDMMC_MCLK_ADJUST |= SDMMC_CLK_INV;
+#endif
+#ifdef CONFIG_RDA_FPGA
+		hwp_sdmmc->SDMMC_MCLK_ADJUST = 0;
+#endif
+		dev->host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HC;
+	} else if (1 == host->dev_num){
+		host->mclk_adj = 0;
+		host->mclk_inv = 0;
+		if (info->manufacturer_id){
+			int i;
+
+			for(i = 0; emmc_mclk_adj_inv[i].mfr_id != 0; i++ )
+				if (info->manufacturer_id == emmc_mclk_adj_inv[i].mfr_id ){
+					host->mclk_adj = emmc_mclk_adj_inv[i].mclk_adj;
+					host->mclk_inv = emmc_mclk_adj_inv[i].mclk_inv;
+					break;
+				}
+
+			if (emmc_mclk_adj_inv[i].mfr_id == 0)
+				printf("Cannot find the emmc corresponding mclk adj and inv.Now use default zero. Please add it \n");
+		} else
+			printf("Spl init emmc first, use default zero mclk adj and inv.\n");
+		hwp_sdmmc->SDMMC_MCLK_ADJUST = SDMMC_SDMMC_MCLK_ADJUST(host->mclk_adj);
+		if(host->mclk_inv)
+			hwp_sdmmc->SDMMC_MCLK_ADJUST |= SDMMC_CLK_INV;
+
+#if defined(CONFIG_MACH_RDA8810E) || defined(CONFIG_MACH_RDA8810H)
+		dev->host_caps = MMC_MODE_8BIT | MMC_MODE_HS | MMC_MODE_HC | MMC_MODE_DDR_52MHz;
+#else
+		dev->host_caps = MMC_MODE_8BIT | MMC_MODE_HS | MMC_MODE_HC;
+#endif
+	} else{
+		printf("invalid mmc device number \n");
+	}
+
+	sprintf(dev->name, "MMC");
+	dev->clock = 400000;
+	dev->send_cmd = host_request;
+	dev->set_ios = host_set_ios;
+	dev->init = mmc_host_reset;
+	dev->voltages = VOLTAGE_WINDOW_MMC;
+	dev->f_min = 400000;
+	if( host->dev_num == 0 ) {
+		dev->f_max = _TGT_AP_SDMMC1_MAX_FREQ;
+	} else {
+		dev->f_max = _TGT_AP_SDMMC3_MAX_FREQ;
+	}
+
+#ifdef CONFIG_RDA_FPGA
+	printf("mmc host %d init, speed=0x%x, adjust = 0x%x \n",
+		host->dev_num,  hwp_sdmmc->SDMMC_TRANS_SPEED,hwp_sdmmc->SDMMC_MCLK_ADJUST);
+#endif
+	return 0;
+}
+int mmc_set_host_mclk_adj_inv(struct mmc *mmc, u8 adj, u8 inv)
+{
+	struct mmc_host *host = mmc->priv;
+
+	if (!host)
+		return -1;
+
+	host->mclk_adj = adj;
+	host->mclk_inv = inv;
+
+	return 0;
+}
+
+/*
+ * MMC write function
+ */
+int mmc_read(struct mmc *mmc, u64 from, uchar *buf, int size)
+{
+	unsigned long cnt;
+	unsigned int start_block, block_num, block_size;
+	int blksz_shift;
+
+	if (!mmc) {
+#ifdef SDMMC_DEBUG
+		printf("mmc_read: mmc device not found!!\n");
+#endif
+		return -1;
+	}
+
+	block_size = mmc->read_bl_len;
+	blksz_shift = mmc->block_dev.log2blksz;
+	start_block = from >> blksz_shift;
+	block_num = (size + block_size - 1) >> blksz_shift;
+
+	/* Read the header too to avoid extra memcpy */
+	cnt = mmc->block_dev.block_read(mmc->block_dev.dev,
+			start_block,
+			block_num, (void *)buf);
+	if (cnt != block_num) {
+#ifdef SDMMC_DEBUG
+		printf("mmc blk read error!\n");
+#endif
+		return -1;
+	}
+
+	return size;
+}
+
+
+int mmc_write(struct mmc *mmc, u64 to, uchar *buf, int size)
+{
+	unsigned long cnt;
+	unsigned int start_block, block_num, block_size;
+	int blksz_shift;
+
+	if (!mmc) {
+#ifdef SDMMC_DEBUG
+		printf("mmc_write: mmc device not found!!\n");
+#endif
+		return -1;
+	}
+
+	blksz_shift = mmc->block_dev.log2blksz;
+	block_size = mmc->write_bl_len;
+	start_block = to >> blksz_shift;
+	block_num = (size + block_size - 1) >> blksz_shift;
+
+	cnt = mmc->block_dev.block_write(mmc->block_dev.dev,
+			start_block,
+			block_num, (void *)buf);
+	if (cnt != block_num) {
+#ifdef SDMMC_DEBUG
+		printf("mmc blk write error!\n");
+#endif
+		return -1;
+	}
+
+	return size;
+}
+
+static void setup_bb_cfg_sdmmc(void)
+{
+#ifdef CONFIG_SDMMC_BOOT
+    unsigned long temp;
+
+    /* pinmux for sdmmc0 */
+    temp = readl(0x11a09008);
+    temp &= ~(0x3F<<9);
+    writel(temp, 0x11a09008);
+#endif
+}
+
+#define RDA_MMC_MAX_BLOCKS    (1024)
+int rda_mmc_init(void)
+{
+	int error,i;
+	struct mmc *dev;
+
+#ifdef SDMMC_DEBUG
+	printf("MMC: rda_mmc_init\n");
+#endif
+	setup_bb_cfg_sdmmc();
+
+	for(i = 0; i < MMC_DEV_NUM; i++){
+		dev = alloc_mmc_struct(i);
+		if (!dev)
+			return -1;
+
+		error = rda_mmc_host_init(dev);
+		if (error) {
+			printf("rda_mmc_host_init %d, error = %d\n",
+				dev->block_dev.dev, error);
+			return -1;
+		}
+
+		dev->b_max = RDA_MMC_MAX_BLOCKS;
+		mmc_register(dev);
+		printf("MMC: registered mmc interface %d\n",
+			dev->block_dev.dev);
+	}
+
+	return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int err = -1;
+
+	err = rda_mmc_init();
+	if (err)
+		return err;
+
+#if defined(CONFIG_PARTITIONS) && !defined(CONFIG_SPL_BUILD)
+	if (rda_media_get() == MEDIA_MMC) {
+		err = mmc_parts_init();
+		if (err)
+			return err;
+	}
+#endif
+	return err;
+}
+
diff --git a/drivers/mmc/rda_mmc.h b/drivers/mmc/rda_mmc.h
new file mode 100644
index 0000000000..64e08a738f
--- /dev/null
+++ b/drivers/mmc/rda_mmc.h
@@ -0,0 +1,221 @@
+#ifndef _SDMMC_H_
+#define _SDMMC_H_
+
+#include <asm/arch/hardware.h>
+
+// =============================================================================
+// TYPES 
+// =============================================================================
+
+typedef struct
+{
+    u8   mid;
+    u32  oid;
+    u32  pnm1;
+    u8   pnm2;
+    u8   prv;
+    u32  psn;
+    u32  mdt;
+    u8   crc;
+} MCD_CID_FORMAT_T;
+
+
+// =============================================================================
+// MCD_CARD_STATE_T
+// -----------------------------------------------------------------------------
+/// The state of the card when receiving the command. If the command execution 
+/// causes a state change, it will be visible to the host in the response to 
+/// the next command. The four bits are interpreted as a binary coded number 
+/// between 0 and 15.
+// =============================================================================
+typedef enum
+{
+    MCD_CARD_STATE_IDLE    = 0,
+    MCD_CARD_STATE_READY   = 1,
+    MCD_CARD_STATE_IDENT   = 2,
+    MCD_CARD_STATE_STBY    = 3,
+    MCD_CARD_STATE_TRAN    = 4,
+    MCD_CARD_STATE_DATA    = 5,
+    MCD_CARD_STATE_RCV     = 6,
+    MCD_CARD_STATE_PRG     = 7,
+    MCD_CARD_STATE_DIS     = 8
+} MCD_CARD_STATE_T;
+
+
+// =============================================================================
+// MCD_CARD_STATUS_T
+// -----------------------------------------------------------------------------
+/// Card status as returned by R1 reponses (spec V2 pdf p.)
+// =============================================================================
+typedef union
+{
+    u32 reg;
+    struct
+    {
+        u32                          :3;
+        u32 akeSeqError              :1;
+        u32                          :1;
+        u32 appCmd                   :1;
+        u32                          :2;
+        u32 readyForData             :1;
+        MCD_CARD_STATE_T currentState   :4;
+        u32 eraseReset               :1;
+        u32 cardEccDisabled          :1;
+        u32 wpEraseSkip              :1;
+        u32 csdOverwrite             :1;
+        u32                          :2;
+        u32 error                    :1;
+        u32 ccError                  :1;
+        u32 cardEccFailed            :1;
+        u32 illegalCommand           :1;
+        u32 comCrcError              :1;
+        u32 lockUnlockFail           :1;
+        u32 cardIsLocked             :1;
+        u32 wpViolation              :1;
+        u32 eraseParam               :1;
+        u32 eraseSeqError            :1;
+        u32 blockLenError            :1;
+        u32 addressError             :1;
+        u32 outOfRange               :1;
+    } fields;
+} MCD_CARD_STATUS_T;
+
+// =============================================================================
+// MCD_CSD_T
+// -----------------------------------------------------------------------------
+/// This structure contains the fields of the MMC chip's register.
+/// For more details, please refer to your MMC specification.
+// =============================================================================
+typedef struct
+{                                   // Ver 2. // Ver 1.0 (if different)   
+    u8   csdStructure;           // 127:126
+    u8   specVers;                   // 125:122
+    u8   taac;                   // 119:112
+    u8   nsac;                   // 111:104
+    u8   tranSpeed;              // 103:96
+    UINT16  ccc;                    //  95:84
+    u8   readBlLen;              //  83:80
+    BOOL    readBlPartial;          //  79:79
+    BOOL    writeBlkMisalign;       //  78:78
+    BOOL    readBlkMisalign;        //  77:77
+    BOOL    dsrImp;                 //  76:76
+    u32  cSize;                  //  69:48 // 73:62
+    u8   vddRCurrMin;            //           61:59
+    u8   vddRCurrMax;            //           58:56
+    u8   vddWCurrMin;             //           55:53
+    u8   vddWCurrMax;            //           52:50
+    u8   cSizeMult;              //           49:47
+    // FIXME 
+    u8   eraseBlkEnable;
+    u8   eraseGrpSize;           //  ??? 46:42
+    // FIXME
+    u8   sectorSize;
+    u8   eraseGrpMult;           //  ??? 41:37
+
+    u8   wpGrpSize;              //  38:32
+    BOOL    wpGrpEnable;            //  31:31
+    u8   defaultEcc;             //  30:29
+    u8   r2wFactor;              //  28:26
+    u8   writeBlLen;             //  25:22
+    BOOL    writeBlPartial;         //  21:21
+    BOOL    contentProtApp;         //  16:16
+    BOOL    fileFormatGrp;          //  15:15
+    BOOL    copy;                   //  14:14
+    BOOL    permWriteProtect;       //  13:13
+    BOOL    tmpWriteProtect;        //  12:12
+    u8   fileFormat;             //  11:10
+    u8   ecc;                    //   9:8
+    u8   crc;                    //   7:1
+    /// This field is not from the CSD register.
+    /// This is the actual block number.
+    u32  blockNumber;
+} MCD_CSD_T;
+
+
+// =============================================================================
+// MCD_ERR_T
+// -----------------------------------------------------------------------------
+/// Type used to describe the error status of the MMC driver.
+// =============================================================================
+typedef enum
+{
+    MCD_ERR_NO = 0,
+    MCD_ERR_CARD_TIMEOUT = 1,
+    MCD_ERR_DMA_BUSY = 3,
+    MCD_ERR_CSD = 4,
+    MCD_ERR_SPI_BUSY = 5,
+    MCD_ERR_BLOCK_LEN = 6,
+    MCD_ERR_CARD_NO_RESPONSE,
+    MCD_ERR_CARD_RESPONSE_BAD_CRC,
+    MCD_ERR_CMD,
+    MCD_ERR_UNUSABLE_CARD,
+    MCD_ERR_NO_CARD,
+    MCD_ERR_NO_HOTPLUG,
+
+    /// A general error value
+    MCD_ERR,
+} MCD_ERR_T;
+
+// =============================================================================
+// MCD_STATUS_T
+// -----------------------------------------------------------------------------
+/// Status of card
+// =============================================================================
+typedef enum
+{
+    // Card present and mcd is open
+    MCD_STATUS_OPEN,
+    // Card present and mcd is not open
+    MCD_STATUS_NOTOPEN_PRESENT,
+    // Card not present
+    MCD_STATUS_NOTPRESENT,
+    // Card removed, still open (please close !)
+    MCD_STATUS_OPEN_NOTPRESENT
+} MCD_STATUS_T ;
+
+// =============================================================================
+// MCD_CARD_SIZE_T
+// -----------------------------------------------------------------------------
+/// Card size
+// =============================================================================
+typedef struct
+{
+    u32 nbBlock;
+    u32 blockLen;
+} MCD_CARD_SIZE_T ;
+
+
+// =============================================================================
+// MCD_CARD_VER
+// -----------------------------------------------------------------------------
+/// Card version
+// =============================================================================
+
+typedef enum 
+{
+    MCD_CARD_V1,
+    MCD_CARD_V2
+}MCD_CARD_VER;
+
+
+// =============================================================================
+// MCD_CARD_ID
+// -----------------------------------------------------------------------------
+/// Card version
+// =============================================================================
+
+typedef enum 
+{
+    MCD_CARD_ID_0,
+    MCD_CARD_ID_1,
+    MCD_CARD_ID_NO,
+}MCD_CARD_ID;
+
+
+MCD_ERR_T mcd_Open(MCD_CSD_T* mcdCsd, MCD_CARD_VER mcdVer);
+MCD_ERR_T mcd_Close(void);
+MCD_ERR_T mcd_Write(u32 startAddr, u8* blockWr, u32 size);
+MCD_ERR_T mcd_Read(u32 startAddr, u8* blockRd, u32 size);
+
+#endif /* _SDMMC_H_ */
+
diff --git a/drivers/mmc/rda_mmc_legacy.c b/drivers/mmc/rda_mmc_legacy.c
new file mode 100644
index 0000000000..f7f2d7c61a
--- /dev/null
+++ b/drivers/mmc/rda_mmc_legacy.c
@@ -0,0 +1,2419 @@
+#include <common.h>
+#include <part.h>
+#include <fat.h>
+#include <mmc.h> 
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/reg_mmc.h>
+#include <asm/arch/reg_ifc.h>
+#include <asm/arch/ifc.h>
+
+#include "rda_mmc.h"
+
+#ifdef DEBUG
+#include <assert.h>
+#else
+#define assert(...)
+#endif 
+
+#define MCD_TRACE(...)
+
+// =============================================================================
+// HAL_SDMMC_TRANSFER_T
+// -----------------------------------------------------------------------------
+/// Describe a transfer between the SDmmc module and the SD card
+// =============================================================================
+typedef struct
+{
+    /// This address in the system memory
+    u8* sysMemAddr;
+    /// Address in the SD card
+    u8* sdCardAddr;
+    /// Quantity of data to transfer, in blocks
+    u32 blockNum;
+    /// Block size
+    u32 blockSize;
+    HAL_SDMMC_DIRECTION_T direction;
+} HAL_SDMMC_TRANSFER_T;
+
+// =============================================================================
+//  Global variables
+// =============================================================================
+u8 g_halSdmmcWriteCh = HAL_UNKNOWN_CHANNEL;
+u8 g_halSdmmcReadCh = HAL_UNKNOWN_CHANNEL;
+
+/// SDMMC clock frequency.
+static u32 g_halSdmmcFreq = 200000;
+
+//=============================================================================
+// hal_SdmmcUpdateDivider
+//-----------------------------------------------------------------------------
+/// Update the SDMMC module divider to keep the desired frequency, whatever
+/// the system frequency is.
+/// @param sysFreq System Frequency currently applied or that will be applied
+/// if faster.
+//=============================================================================
+//static void hal_SdmmcUpdateDivider(HAL_SYS_FREQ_T sysFreq);
+
+//=============================================================================
+// hal_SdmmcOpen
+//-----------------------------------------------------------------------------
+/// Open the SDMMC module. Take a resource.
+//=============================================================================
+void hal_SdmmcOpen(u8 clk_adj)
+{
+    // Make sure the last clock is set
+    //hal_SdmmcUpdateDivider(hal_SysGetFreq());
+
+    // Take the module out of reset
+    //hwp_sysCtrl->REG_DBG     = SYS_CTRL_PROTECT_UNLOCK;
+    //hwp_sysCtrl->Sys_Rst_Clr = SYS_CTRL_CLR_RST_SDMMC;
+    //hwp_sysCtrl->REG_DBG     = SYS_CTRL_PROTECT_LOCK;
+
+    // We don't use interrupts.
+    hwp_sdmmc->SDMMC_INT_MASK = 0x0;
+    hwp_sdmmc->SDMMC_MCLK_ADJUST = clk_adj;
+
+    // Take a resource (The idea is to be able to get a 25Mhz clock)
+    //hal_SysRequestFreq(HAL_SYS_FREQ_SDMMC, HAL_SYS_FREQ_52M, hal_SdmmcUpdateDivider);
+}
+
+//=============================================================================
+// hal_SdmmcClose
+//-----------------------------------------------------------------------------
+/// Close the SDMMC module. Take a resource.
+//=============================================================================
+void hal_SdmmcClose(void)
+{
+    // Free a resource
+    //hal_SysRequestFreq(HAL_SYS_FREQ_SDMMC, HAL_SYS_FREQ_32K, NULL);
+
+    // Put the module in reset, as its clock is free running.
+    //hwp_sysCtrl->REG_DBG = SYS_CTRL_PROTECT_UNLOCK;
+    //hwp_sysCtrl->Sys_Rst_Set = SYS_CTRL_SET_RST_SDMMC;
+    //hwp_sysCtrl->REG_DBG = SYS_CTRL_PROTECT_LOCK;
+}
+
+//=============================================================================
+// hal_SdmmcWakeUp
+//-----------------------------------------------------------------------------
+/// This function requests a resource of #HAL_SYS_FREQ_52M. 
+/// hal_SdmmcSleep() must be called before any other
+//=============================================================================
+void hal_SdmmcWakeUp(void)
+{
+    // Take a resource (The idea is to be able to get a 25Mhz clock)
+    //hal_SysRequestFreq(HAL_SYS_FREQ_SDMMC, HAL_SYS_FREQ_52M, hal_SdmmcUpdateDivider);
+}
+
+//=============================================================================
+// hal_SdmmcSleep
+//-----------------------------------------------------------------------------
+/// This function release the resource to #HAL_SYS_FREQ_32K.
+//=============================================================================
+void hal_SdmmcSleep(void)
+{
+    // We just release the resource, because the clock gating in sdmmc controller
+    // will disable the clock. We should wait for the clock to be actually disabled
+    // but the module does not seam to have a status for that...
+
+    // Free a resource
+    //hal_SysRequestFreq(HAL_SYS_FREQ_SDMMC, HAL_SYS_FREQ_32K, NULL);
+}
+
+// =============================================================================
+// hal_SdmmcSendCmd
+// -----------------------------------------------------------------------------
+/// Send a command to a SD card plugged to the sdmmc port.
+/// @param cmd Command
+/// @param arg Argument of the command
+/// @param suspend Feature not implemented yet.
+// =============================================================================
+void hal_SdmmcSendCmd(HAL_SDMMC_CMD_T cmd, u32 arg, BOOL suspend)
+{
+    u32 configReg = 0;
+    //hwp_sdmmc->SDMMC_CONFIG = SDMMC_AUTO_FLAG_EN;
+    hwp_sdmmc->SDMMC_CONFIG = 0x00000000;
+    
+    switch (cmd)
+    {
+        case HAL_SDMMC_CMD_GO_IDLE_STATE:
+            configReg = SDMMC_SDMMC_SENDCMD;
+            break;
+
+            
+        case HAL_SDMMC_CMD_ALL_SEND_CID:
+            configReg = SDMMC_RSP_SEL_R2    | SDMMC_RSP_EN | SDMMC_SDMMC_SENDCMD; // 0x51
+            break;
+
+        case HAL_SDMMC_CMD_SEND_RELATIVE_ADDR:
+            configReg = SDMMC_RSP_SEL_OTHER | SDMMC_RSP_EN | SDMMC_SDMMC_SENDCMD; // 0x11
+            break;
+
+        case HAL_SDMMC_CMD_SEND_IF_COND:
+            configReg = SDMMC_RSP_SEL_OTHER | SDMMC_RSP_EN | SDMMC_SDMMC_SENDCMD; // 0x11
+            break;
+
+        case HAL_SDMMC_CMD_SET_DSR:
+            configReg = SDMMC_SDMMC_SENDCMD;
+            break;
+
+        case HAL_SDMMC_CMD_SELECT_CARD:
+            configReg = SDMMC_RSP_SEL_OTHER | SDMMC_RSP_EN | SDMMC_SDMMC_SENDCMD;
+            break;
+
+        case HAL_SDMMC_CMD_SEND_CSD                :
+            configReg = SDMMC_RSP_SEL_R2    | SDMMC_RSP_EN | SDMMC_SDMMC_SENDCMD;
+            break;
+
+        case HAL_SDMMC_CMD_STOP_TRANSMISSION        :
+            configReg = 0; // TODO
+            break;
+
+        case HAL_SDMMC_CMD_SEND_STATUS            :
+            configReg = SDMMC_RSP_SEL_OTHER | SDMMC_RSP_EN | SDMMC_SDMMC_SENDCMD;
+            break;
+
+        case HAL_SDMMC_CMD_SET_BLOCKLEN            :
+            configReg = SDMMC_RSP_SEL_OTHER | SDMMC_RSP_EN | SDMMC_SDMMC_SENDCMD;
+            break;
+
+        case HAL_SDMMC_CMD_READ_SINGLE_BLOCK        :
+            configReg =  SDMMC_RD_WT_SEL_READ
+                       | SDMMC_RD_WT_EN
+                       | SDMMC_RSP_SEL_OTHER
+                       | SDMMC_RSP_EN
+                       | SDMMC_SDMMC_SENDCMD; // 0x111
+            break;
+
+        case HAL_SDMMC_CMD_READ_MULT_BLOCK        :
+            configReg =  SDMMC_S_M_SEL_MULTIPLE
+                       | SDMMC_RD_WT_SEL_READ
+                       | SDMMC_RD_WT_EN
+                       | SDMMC_RSP_SEL_OTHER
+                       | SDMMC_RSP_EN
+                       | SDMMC_SDMMC_SENDCMD; // 0x511;
+            break;
+
+        case HAL_SDMMC_CMD_WRITE_SINGLE_BLOCK    :
+            configReg = SDMMC_RD_WT_SEL_WRITE
+                       | SDMMC_RD_WT_EN
+                       | SDMMC_RSP_SEL_OTHER
+                       | SDMMC_RSP_EN
+                       | SDMMC_SDMMC_SENDCMD; // 0x311
+            break;
+
+        case HAL_SDMMC_CMD_WRITE_MULT_BLOCK        :
+            configReg =  SDMMC_S_M_SEL_MULTIPLE
+                       | SDMMC_RD_WT_SEL_WRITE
+                       | SDMMC_RD_WT_EN
+                       | SDMMC_RSP_SEL_OTHER
+                       | SDMMC_RSP_EN
+                       | SDMMC_SDMMC_SENDCMD; // 0x711
+            break;
+
+        case HAL_SDMMC_CMD_APP_CMD                :
+            configReg = SDMMC_RSP_SEL_OTHER | SDMMC_RSP_EN | SDMMC_SDMMC_SENDCMD; // 0x11
+            break;
+
+        case HAL_SDMMC_CMD_SET_BUS_WIDTH            :
+        case HAL_SDMMC_CMD_SWITCH:
+            configReg = SDMMC_RSP_SEL_OTHER | SDMMC_RSP_EN | SDMMC_SDMMC_SENDCMD; // 0x11
+            break;
+
+        case HAL_SDMMC_CMD_SEND_NUM_WR_BLOCKS    :
+            configReg =  SDMMC_RD_WT_SEL_READ
+                       | SDMMC_RD_WT_EN
+                       | SDMMC_RSP_SEL_OTHER
+                       | SDMMC_RSP_EN
+                       | SDMMC_SDMMC_SENDCMD; // 0x111
+            break;
+
+        case HAL_SDMMC_CMD_SET_WR_BLK_COUNT        :
+            configReg =  SDMMC_RSP_SEL_OTHER | SDMMC_RSP_EN | SDMMC_SDMMC_SENDCMD; // 0x11
+            break;
+
+        case HAL_SDMMC_CMD_MMC_SEND_OP_COND:
+        case HAL_SDMMC_CMD_SEND_OP_COND:
+            configReg =  SDMMC_RSP_SEL_R3    | SDMMC_RSP_EN | SDMMC_SDMMC_SENDCMD; // 0x31
+            break;
+
+        default:
+            break;
+    }
+
+    // TODO Add suspend management
+    hwp_sdmmc->SDMMC_CMD_INDEX = SDMMC_COMMAND(cmd);
+    hwp_sdmmc->SDMMC_CMD_ARG   = SDMMC_ARGUMENT(arg);
+    //hwp_sdmmc->SDMMC_CONFIG    = configReg |SDMMC_AUTO_FLAG_EN;
+    hwp_sdmmc->SDMMC_CONFIG    = configReg ;
+}
+
+// =============================================================================
+// hal_SdmmcNeedResponse
+// -----------------------------------------------------------------------------
+/// Tells if the given command waits for a reponse.
+/// @return \c TRUE if the command needs an answer, \c FALSE otherwise.
+// =============================================================================
+BOOL hal_SdmmcNeedResponse(HAL_SDMMC_CMD_T cmd)
+{
+    switch (cmd)
+    {
+        case HAL_SDMMC_CMD_GO_IDLE_STATE:
+        case HAL_SDMMC_CMD_SET_DSR:
+        case HAL_SDMMC_CMD_STOP_TRANSMISSION:
+            return FALSE;
+            break;
+
+            
+        case HAL_SDMMC_CMD_ALL_SEND_CID:
+        case HAL_SDMMC_CMD_SEND_RELATIVE_ADDR:
+        case HAL_SDMMC_CMD_SEND_IF_COND:
+
+        case HAL_SDMMC_CMD_SELECT_CARD:
+        case HAL_SDMMC_CMD_SEND_CSD:
+        case HAL_SDMMC_CMD_SEND_STATUS:
+        case HAL_SDMMC_CMD_SET_BLOCKLEN:
+        case HAL_SDMMC_CMD_READ_SINGLE_BLOCK:
+        case HAL_SDMMC_CMD_READ_MULT_BLOCK:
+        case HAL_SDMMC_CMD_WRITE_SINGLE_BLOCK:
+        case HAL_SDMMC_CMD_WRITE_MULT_BLOCK:
+        case HAL_SDMMC_CMD_APP_CMD:
+        case HAL_SDMMC_CMD_SET_BUS_WIDTH:
+        case HAL_SDMMC_CMD_SEND_NUM_WR_BLOCKS:
+        case HAL_SDMMC_CMD_SET_WR_BLK_COUNT:
+        case HAL_SDMMC_CMD_MMC_SEND_OP_COND:
+        case HAL_SDMMC_CMD_SEND_OP_COND:
+        case HAL_SDMMC_CMD_SWITCH:
+            return TRUE;
+            break;
+        
+        default:
+            //assert(FALSE, "Unsupported SDMMC command:%d", cmd);
+            // Dummy return, for the compiler to be pleased.
+            return FALSE;
+            break;
+    }
+}
+
+// =============================================================================
+// hal_SdmmcCmdDone
+// -----------------------------------------------------------------------------
+/// @return \c TRUE of there is not command pending or being processed.
+// =============================================================================
+BOOL hal_SdmmcCmdDone(void)
+{
+    return (!(hwp_sdmmc->SDMMC_STATUS & SDMMC_NOT_SDMMC_OVER));
+}
+
+// =============================================================================
+// hal_SdmmcGetCardDetectPinLevel
+// -----------------------------------------------------------------------------
+/// @return \c TRUE if card detect (DAT3) line is high,
+///         \c FALSE if the line is low.
+/// User must check with SD spec and board pull-up/down resistor to 
+/// interpret this value.
+// =============================================================================
+BOOL hal_SdmmcGetCardDetectPinLevel(void)
+{
+#if 0
+#if (CHIP_ASIC_ID == CHIP_ASIC_ID_GREENSTONE)
+    u32               value;
+
+    hal_GpioSetIn(HAL_GPIO_26);
+    //IOMUX control is useless, the input pins are not filtered but goes to both
+    //SDMMC and GPIO module
+    //hwp_extApb->GPIO_Mode &= ~REGS_MODE_PIN_SDMMC_DATA3;
+    value = hal_GpioGet(HAL_GPIO_26);
+    //hwp_extApb->GPIO_Mode |=  REGS_MODE_PIN_SDMMC_DATA3;
+
+    //HAL_TRACE(TSTDOUT, 0, "----- Value %i\n", value);
+
+    return value != 0;
+#else
+    assert(FALSE, "TODO: hal_SdmmcGetCardDetectPinLevel not implemented for your chip!");
+    return FALSE;
+#endif
+#endif
+    return TRUE;
+}
+
+//=============================================================================
+// hal_SdmmcUpdateDivider
+//-----------------------------------------------------------------------------
+/// Update the SDMMC module divider to keep the desired frequency, whatever
+/// the system frequency is.
+/// @param sysFreq System Frequency currently applied or that will be applied
+/// if faster.
+//=============================================================================
+static void hal_SdmmcUpdateDivider(void)
+{
+    //if (g_halSdmmcFreq != 0)
+    //{
+    //    u32 divider = (sysFreq-1)/(2*g_halSdmmcFreq) + 1;
+    //    if (divider>1)
+    //    {
+    //        divider = divider-1;
+    //    }
+
+    //    if (divider > 0xFF)
+    //    {
+    //        divider = 0xFF;
+    //    }
+
+    // wngl, use 25M/8 as clock
+    hwp_sdmmc->SDMMC_TRANS_SPEED = SDMMC_SDMMC_TRANS_SPEED(8);
+    //}
+}
+
+// =============================================================================
+// hal_SdmmcSetClk
+// -----------------------------------------------------------------------------
+/// Set the SDMMC clock frequency to something inferior but close to that,
+/// taking into account system frequency.
+// =============================================================================
+void hal_SdmmcSetClk(u32 clock)
+{
+    // TODO Add assert to stay on supported values ?
+    g_halSdmmcFreq = clock;
+    
+    // Update the divider takes care of the registers configuration
+    hal_SdmmcUpdateDivider();
+}
+
+// =============================================================================
+// hal_SdmmcGetOpStatus
+// -----------------------------------------------------------------------------
+/// @return The operational status of the SDMMC module.
+// =============================================================================
+HAL_SDMMC_OP_STATUS_T hal_SdmmcGetOpStatus(void)
+{
+    return ((HAL_SDMMC_OP_STATUS_T)(u32)hwp_sdmmc->SDMMC_STATUS);
+}
+
+
+// =============================================================================
+// hal_SdmmcGetResp
+// -----------------------------------------------------------------------------
+/// This function is to be used to get the argument of the response of a 
+/// command. It is needed to provide the command index and its application 
+/// specific status, in order to determine the type of answer expected.
+///
+/// @param cmd Command to send
+/// @param arg Pointer to a four 32 bit word array, where the argument will be 
+/// stored. Only the first case is set in case of a response of type R1, R3 or 
+/// R6, 4 if it is a R2 response.
+/// @param suspend Unsupported
+// =============================================================================
+void hal_SdmmcGetResp(HAL_SDMMC_CMD_T cmd, u32* arg, BOOL suspend)
+{
+    // TODO Check in the spec for all the commands response types
+    switch (cmd)
+    {
+        // If they require a response, it is cargoed 
+        // with a 32 bit argument.
+        case HAL_SDMMC_CMD_GO_IDLE_STATE       : 
+        case HAL_SDMMC_CMD_SEND_RELATIVE_ADDR  : 
+        case HAL_SDMMC_CMD_SEND_IF_COND        : 
+        case HAL_SDMMC_CMD_SET_DSR               : 
+        case HAL_SDMMC_CMD_SELECT_CARD           : 
+        case HAL_SDMMC_CMD_STOP_TRANSMISSION   : 
+        case HAL_SDMMC_CMD_SEND_STATUS           : 
+        case HAL_SDMMC_CMD_SET_BLOCKLEN           : 
+        case HAL_SDMMC_CMD_READ_SINGLE_BLOCK   : 
+        case HAL_SDMMC_CMD_READ_MULT_BLOCK       : 
+        case HAL_SDMMC_CMD_WRITE_SINGLE_BLOCK  : 
+        case HAL_SDMMC_CMD_WRITE_MULT_BLOCK       : 
+        case HAL_SDMMC_CMD_APP_CMD               : 
+        case HAL_SDMMC_CMD_SET_BUS_WIDTH       : 
+        case HAL_SDMMC_CMD_SEND_NUM_WR_BLOCKS  : 
+        case HAL_SDMMC_CMD_SET_WR_BLK_COUNT       :
+        case HAL_SDMMC_CMD_MMC_SEND_OP_COND    :
+        case HAL_SDMMC_CMD_SEND_OP_COND           :
+        case HAL_SDMMC_CMD_SWITCH:
+            arg[0] = hwp_sdmmc->SDMMC_RESP_ARG3;
+            arg[1] = 0;
+            arg[2] = 0;
+            arg[3] = 0;
+            break;
+
+        // Those response arguments are 128 bits
+        case HAL_SDMMC_CMD_ALL_SEND_CID           : 
+        case HAL_SDMMC_CMD_SEND_CSD               :
+            arg[0] = hwp_sdmmc->SDMMC_RESP_ARG0;
+            arg[1] = hwp_sdmmc->SDMMC_RESP_ARG1;
+            arg[2] = hwp_sdmmc->SDMMC_RESP_ARG2;
+            arg[3] = hwp_sdmmc->SDMMC_RESP_ARG3;
+            break;
+
+        default:
+            //assert(FALSE, "hal_SdmmcGetResp called with "
+            //                  "an unsupported command: %d", cmd);
+            break;
+    }
+}
+
+// =============================================================================
+// hal_SdmmcGetResp32BitsArgument
+// -----------------------------------------------------------------------------
+/// This function is to be used to get the argument of the response of a 
+/// command triggerring a response with a 32 bits argument (typically, 
+/// R1, R3 or R6).
+/// @return 32 bits of arguments of a 48 bits response token
+// =============================================================================
+u32 hal_SdmmcGetResp32BitsArgument(void)
+{
+    return hwp_sdmmc->SDMMC_RESP_ARG3;
+}
+
+// =============================================================================
+// hal_SdmmcGetResp128BitsArgument
+// -----------------------------------------------------------------------------
+/// This function is to be used to get the argument of the response of a 
+/// command triggerring a response with a 128 bits argument (typically, 
+/// R2).
+/// @param Pointer to a 4 case arrays of 32 bits where the argument of the 
+/// function will be stored.
+// =============================================================================
+void hal_SdmmcGetResp128BitsArgument(u32* buf)
+{
+    buf[0] = hwp_sdmmc->SDMMC_RESP_ARG0;
+    buf[1] = hwp_sdmmc->SDMMC_RESP_ARG1;
+    buf[2] = hwp_sdmmc->SDMMC_RESP_ARG2;
+    buf[3] = hwp_sdmmc->SDMMC_RESP_ARG3;
+}
+
+// =============================================================================
+// hal_SdmmcEnterDataTransferMode
+// -----------------------------------------------------------------------------
+/// Configure the SDMMC module to support data transfers
+/// FIXME Find out why we need that out of the transfer functions...
+// =============================================================================
+void hal_SdmmcEnterDataTransferMode(void)
+{
+    hwp_sdmmc->SDMMC_CONFIG |= SDMMC_RD_WT_EN;
+}
+
+// =============================================================================
+// hal_SdmmcSetDataWidth
+// -----------------------------------------------------------------------------
+/// Set the data bus width
+/// @param width Number of line of the SD data bus used.
+// =============================================================================
+void hal_SdmmcSetDataWidth(HAL_SDMMC_DATA_BUS_WIDTH_T width)
+{
+    switch (width)
+    {
+        case HAL_SDMMC_DATA_BUS_WIDTH_1:
+            hwp_sdmmc->SDMMC_DATA_WIDTH = 1;
+            break;
+
+        case HAL_SDMMC_DATA_BUS_WIDTH_4:
+            hwp_sdmmc->SDMMC_DATA_WIDTH = 4;
+            break;
+
+        default:
+            //assert(FALSE, "hal_SdmmcSetDataWidth(%d) is an invalid width",
+            //        width);
+            break;
+    }
+}
+
+// =============================================================================
+// hal_SdmmcTransfer
+// -----------------------------------------------------------------------------
+/// Start the ifc transfer to feed the SDMMC controller fifo.
+/// @param transfer Transfer to program.
+/// @return HAL_ERR_NO or HAL_ERR_RESOURCE_BUSY.
+// =============================================================================
+int hal_SdmmcTransfer(HAL_SDMMC_TRANSFER_T* transfer)
+{
+    u8 channel = 0;
+    HAL_IFC_REQUEST_ID_T ifcReq = HAL_IFC_NO_REQWEST;
+    u32 length = 0;
+    u32 lengthExp = 0;
+
+    //assert((transfer->blockSize>=4) && (transfer->blockSize<=2048),
+    //            "Block Length(%d) is invalid!\n", transfer->blockSize);
+
+    length =  transfer->blockSize;
+    
+    // The block size register 
+    while (length != 1)
+    {
+        length >>= 1;
+        lengthExp++;
+    }
+
+    // Configure amount of data
+    hwp_sdmmc->SDMMC_BLOCK_CNT  = SDMMC_SDMMC_BLOCK_CNT(transfer->blockNum);
+    hwp_sdmmc->SDMMC_BLOCK_SIZE = SDMMC_SDMMC_BLOCK_SIZE(lengthExp);
+
+    // Configure Bytes reordering
+    hwp_sdmmc->apbi_ctrl_sdmmc = SDMMC_SOFT_RST_L | SDMMC_L_ENDIAN(1);
+
+    switch (transfer->direction)
+    {
+        case HAL_SDMMC_DIRECTION_READ:
+            ifcReq = HAL_IFC_SDMMC_RX;
+            break;
+
+        case HAL_SDMMC_DIRECTION_WRITE:
+            ifcReq = HAL_IFC_SDMMC_TX;
+            break;
+
+        default:
+            assert(FALSE, "hal_SdmmcTransfer with erroneous %d direction",
+                            transfer->direction);
+            break;
+    }
+
+    channel = hal_IfcTransferStart(ifcReq, transfer->sysMemAddr, 
+                                   transfer->blockNum*transfer->blockSize,
+                                   HAL_IFC_SIZE_32_MODE_MANUAL);
+    if (channel == HAL_UNKNOWN_CHANNEL)
+    {
+        printf("Chal_SdmmcTransfer error\n");
+        return -1;
+    }
+    else
+    {
+        // Record Channel used.
+        if (transfer->direction == HAL_SDMMC_DIRECTION_READ)
+        {
+            g_halSdmmcReadCh = channel;
+        }
+        else
+        {
+            g_halSdmmcWriteCh = channel;
+        }
+        return 0;
+    }
+}
+
+// =============================================================================
+// hal_SdmmcTransferDone
+// -----------------------------------------------------------------------------
+/// Check the end of transfer status.
+/// Attention: This means the SDMMC module has finished to transfer data.
+/// In case of a read operation, the Ifc will finish its transfer shortly 
+/// after. Considering the way this function is used (after reading at least
+/// 512 bytes, and flushing cache before releasing the data to the user), and
+/// the fifo sizes, this is closely equivalent to the end of the transfer.
+/// @return \c TRUE if a transfer is over, \c FALSE otherwise.
+// =============================================================================
+BOOL hal_SdmmcTransferDone(void)
+{
+    // The link is not full duplex. We check both the
+    // direction, but only one can be in progress at a time.
+
+    if (g_halSdmmcReadCh != HAL_UNKNOWN_CHANNEL)
+    {
+        // Operation in progress is a read.
+        // The SDMMC module itself can know it has finished
+        if ((hwp_sdmmc->SDMMC_INT_STATUS & SDMMC_DAT_OVER_INT)
+         && (hwp_sysIfc->std_ch[g_halSdmmcReadCh].tc == 0))
+        {
+            // Transfer is over
+            hwp_sdmmc->SDMMC_INT_CLEAR = SDMMC_DAT_OVER_CL;
+            hal_IfcChannelRelease(HAL_IFC_SDMMC_RX, g_halSdmmcReadCh);
+
+            // We finished a read
+            g_halSdmmcReadCh = HAL_UNKNOWN_CHANNEL;
+    
+            //  Put the FIFO in reset state.
+            hwp_sdmmc->apbi_ctrl_sdmmc = 0 | SDMMC_L_ENDIAN(1);
+
+            return TRUE;
+        }
+    }
+
+    if (g_halSdmmcWriteCh != HAL_UNKNOWN_CHANNEL)
+    {
+        // Operation in progress is a write.
+        // The SDMMC module itself can know it has finished
+        if ((hwp_sdmmc->SDMMC_INT_STATUS & SDMMC_DAT_OVER_INT)
+         && (hwp_sysIfc->std_ch[g_halSdmmcWriteCh].tc == 0))
+        {
+            // Transfer is over
+            hwp_sdmmc->SDMMC_INT_CLEAR = SDMMC_DAT_OVER_CL;
+            hal_IfcChannelRelease(HAL_IFC_SDMMC_TX, g_halSdmmcWriteCh);
+
+            // We finished a write
+            g_halSdmmcWriteCh = HAL_UNKNOWN_CHANNEL;
+    
+            //  Put the FIFO in reset state.
+            hwp_sdmmc->apbi_ctrl_sdmmc = 0 | SDMMC_L_ENDIAN(1);
+
+            return TRUE;
+        }
+    }
+    
+    // there's still data running through a pipe (or no transfer in progress ...)
+    return FALSE;
+}
+
+// =============================================================================
+// hal_SdmmcStopTransfer
+// -----------------------------------------------------------------------------
+/// Stop the ifc transfer feeding the SDMMC controller fifo.
+/// @param transfer Transfer to program.
+/// @return #HAL_ERR_NO
+// =============================================================================
+void hal_SdmmcStopTransfer(HAL_SDMMC_TRANSFER_T* transfer)
+{
+    // Configure amount of data
+    hwp_sdmmc->SDMMC_BLOCK_CNT  = SDMMC_SDMMC_BLOCK_CNT(0);
+    hwp_sdmmc->SDMMC_BLOCK_SIZE = SDMMC_SDMMC_BLOCK_SIZE(0);
+    
+    //  Put the FIFO in reset state.
+    hwp_sdmmc->apbi_ctrl_sdmmc = 0 | SDMMC_L_ENDIAN(1);
+
+    if (transfer->direction == HAL_SDMMC_DIRECTION_READ)
+    {
+        hal_IfcChannelFlush(HAL_IFC_SDMMC_RX, g_halSdmmcReadCh);
+        while(!hal_IfcChannelIsFifoEmpty(HAL_IFC_SDMMC_RX, g_halSdmmcReadCh));
+        hal_IfcChannelRelease(HAL_IFC_SDMMC_RX, g_halSdmmcReadCh);
+        g_halSdmmcReadCh = HAL_UNKNOWN_CHANNEL;
+    }
+    else
+    {
+        hal_IfcChannelFlush(HAL_IFC_SDMMC_TX, g_halSdmmcWriteCh);
+        while(!hal_IfcChannelIsFifoEmpty(HAL_IFC_SDMMC_TX, g_halSdmmcReadCh));
+        hal_IfcChannelRelease(HAL_IFC_SDMMC_TX, g_halSdmmcWriteCh);
+        g_halSdmmcWriteCh = HAL_UNKNOWN_CHANNEL;
+    }
+}
+
+// =============================================================================
+// hal_SdmmcIsBusy
+// -----------------------------------------------------------------------------
+/// Check if the SD/MMC is busy.
+/// 
+/// @return \c TRUE if the SD/MMC controller is busy.
+///         \c FALSE otherwise.
+// =============================================================================
+BOOL hal_SdmmcIsBusy(void)
+{
+    //if (g_halSdmmcReadCh    != HAL_UNKNOWN_CHANNEL
+    // || g_halSdmmcWriteCh   != HAL_UNKNOWN_CHANNEL
+    // || ((hwp_sdmmc->SDMMC_STATUS & (SDMMC_NOT_SDMMC_OVER | SDMMC_BUSY | SDMMC_DL_BUSY)) != 0)
+    //   )
+    if ((hwp_sdmmc->SDMMC_STATUS & (SDMMC_NOT_SDMMC_OVER | SDMMC_BUSY | SDMMC_DL_BUSY)) != 0)
+    {
+        // SD/MMc is busy doing something.
+        return TRUE;
+    }
+    else
+    {
+        return FALSE;
+    }
+}
+
+// =============================================================================
+//  MACROS
+// =============================================================================
+#define BROAD_ADDR  0
+#define NOT_SDMMC_OVER  (1<<0)
+
+#define MCD_MAX_BLOCK_NUM       128
+
+#define MCD_SDMMC_OCR_TIMEOUT    (1 SECOND)  // the card is supposed to answer within 1s
+                                             //  - Max wait is 128 * 10ms=1,28s
+                                             //  TODO: where those 10ms come from ??
+
+// Command 8 things: cf spec Vers.2 section 4.3.13
+#define MCD_CMD8_CHECK_PATTERN      0xaa
+#define MCD_CMD8_VOLTAGE_SEL        (0x1<<8)
+//#define MCD_CMD8_VOLTAGE_SEL        (0x2<<8)   // wngl, change to low voltage
+#define MCD_OCR_HCS                 (1<<30)
+#define MCD_OCR_CCS_MASK            (1<<30)
+
+#define SECOND                    * CONFIG_SYS_HZ_CLOCK
+// Timeouts for V1
+#define MCD_CMD_TIMEOUT_V1        ( 1 SECOND / 1 )
+#define MCD_RESP_TIMEOUT_V1       ( 1 SECOND / 1 )
+#define MCD_TRAN_TIMEOUT_V1       ( 1 SECOND / 1 )
+#define MCD_READ_TIMEOUT_V1       ( 5 SECOND )
+#define MCD_WRITE_TIMEOUT_V1      ( 5 SECOND )
+
+// Timeouts for V2
+#define MCD_CMD_TIMEOUT_V2        ( 1 SECOND / 10 )
+#define MCD_RESP_TIMEOUT_V2       ( 1 SECOND / 10 )
+#define MCD_TRAN_TIMEOUT_V2       ( 1 SECOND / 10 )
+#define MCD_READ_TIMEOUT_V2       ( 5 SECOND )
+#define MCD_WRITE_TIMEOUT_V2      (5 SECOND )
+
+// =============================================================================
+// Global variables
+// =============================================================================
+
+// Spec Ver2 p96
+#define MCD_SDMMC_OCR_VOLT_PROF_MASK  0x00ff8000
+
+static u32 g_mcdOcrReg = MCD_SDMMC_OCR_VOLT_PROF_MASK;
+
+/// Relative Card Address Register
+/// Nota RCA is sixteen bit long, but is always used
+/// as the 16 upper bits of a 32 bits word. Therefore
+/// is variable is in fact (RCA<<16), to avoid operation
+/// (shift, unshift), to always place the RCA value as the
+/// upper bits of a data word.
+static u32 g_mcdRcaReg = 0x00000000;
+
+// Driver Stage Register p.118
+// (To adjust bus capacitance)
+// TODO Tune and put in calibration ?
+static u32 g_mcdSdmmcDsr = 0x04040000;
+
+
+static u32 g_mcdSdmmcFreq = 200000; 
+
+static MCD_CID_FORMAT_T  g_mcdCidReg;
+static u32            g_mcdBlockLen   = 0;
+static u32            g_mcdNbBlock    = 0;
+static BOOL              g_mcdCardIsSdhc = FALSE;
+
+static MCD_STATUS_T      g_mcdStatus = MCD_STATUS_NOTOPEN_PRESENT;
+
+//static CONST TGT_MCD_CONFIG_T*     g_mcdConfig=NULL;
+//static MCD_CARD_DETECT_HANDLER_T   g_mcdCardDetectHandler=NULL;
+
+/// Semaphore to ensure proper concurrency of the MCD accesses
+/// among all tasks.
+static u32           g_mcdSemaphore   = 0xFF;  
+
+/// Current in-progress transfer, if any.
+static HAL_SDMMC_TRANSFER_T g_mcdSdmmcTransfer = 
+                        {
+                            .sysMemAddr = 0,
+                            .sdCardAddr = 0,
+                            .blockNum   = 0,
+                            .blockSize  = 0,
+                            .direction  = HAL_SDMMC_DIRECTION_WRITE,
+                        };
+
+static MCD_CSD_T g_mcdLatestCsd;
+
+static MCD_CARD_VER g_mcdVer = MCD_CARD_V2;
+
+// =============================================================================
+// Functions
+// =============================================================================
+u32 hal_TimGetUpTime(void)
+{
+    return (u32)get_ticks();
+}
+// =============================================================================
+// Functions for the HAL Driver ?
+// =============================================================================
+#if 0
+/// Macro to easily implement concurrency in the MCD driver.
+/// Enter in the 'critical section'.
+#define MCD_CS_ENTER \
+    if (g_mcdSemaphore != 0xFF)             \
+    {                                       \
+        sxr_TakeSemaphore(g_mcdSemaphore);  \
+    }                                       \
+    else                                    \
+    {                                       \
+        return MCD_ERR;                     \
+    }
+
+
+/// Macro to easily implement concurrency in the MCD driver.
+/// Exit in the 'critical section'.
+#define MCD_CS_EXIT \
+    {                                       \
+    sxr_ReleaseSemaphore(g_mcdSemaphore);   \
+    }
+#endif
+
+MCD_ERR_T mcd_GetCardSize(MCD_CARD_SIZE_T* size)
+{
+    //MCD_CS_ENTER;
+
+    size->blockLen = g_mcdBlockLen;
+    size->nbBlock  = g_mcdNbBlock;
+
+    //MCD_CS_EXIT;
+    return MCD_ERR_NO;
+}
+
+// Wait for a command to be done or timeouts
+static MCD_ERR_T mcd_SdmmcWaitCmdOver(void)
+{
+    u32 startTime = hal_TimGetUpTime();
+    u32 time_out;
+    
+    time_out =  (MCD_CARD_V1 == g_mcdVer) ? MCD_CMD_TIMEOUT_V1:MCD_CMD_TIMEOUT_V2;
+   
+    while(hal_TimGetUpTime() - startTime < time_out && !hal_SdmmcCmdDone());    
+
+    if (!hal_SdmmcCmdDone())
+    {
+        MCD_TRACE(MCD_INFO_TRC, 0, "SDC Waiting is Time out");
+        return MCD_ERR_CARD_TIMEOUT;
+    }
+    else
+    {
+        return MCD_ERR_NO;
+    }
+}
+
+#if 0
+/// Update g_mcdStatus
+/// @return TRUE is card present (only exact when GPIO is used for card detect.)
+static BOOL mcd_CardDetectUpdateStatus(void)
+{
+    if(NULL == g_mcdConfig)
+    {
+        g_mcdConfig = tgt_GetMcdConfig();
+    }
+
+    if(g_mcdConfig->cardDetectGpio != HAL_GPIO_NONE)
+    {
+        BOOL gpioState = !!hal_GpioGet(g_mcdConfig->cardDetectGpio);
+        // CARD ?
+        if(gpioState == g_mcdConfig->gpioCardDetectHigh)
+        { // card detected
+            switch(g_mcdStatus)
+            {
+                case MCD_STATUS_OPEN_NOTPRESENT: // wait for the close !
+                case MCD_STATUS_OPEN:
+                // No change
+                break;
+                default:
+                g_mcdStatus = MCD_STATUS_NOTOPEN_PRESENT;
+            }
+            return TRUE;
+        }
+        else
+        { // no card
+            switch(g_mcdStatus)
+            {
+                case MCD_STATUS_OPEN_NOTPRESENT:
+                case MCD_STATUS_OPEN:
+                    g_mcdStatus = MCD_STATUS_OPEN_NOTPRESENT;
+                    break;
+                default:
+                    g_mcdStatus = MCD_STATUS_NOTPRESENT;
+            }
+            return FALSE;
+        }
+    }
+    // estimated
+    switch(g_mcdStatus)
+    {
+        case MCD_STATUS_OPEN:
+        case MCD_STATUS_NOTOPEN_PRESENT:
+            return TRUE;
+        default:
+            return FALSE;
+    }
+}
+
+static void mcd_CardDetectHandler(void)
+{
+    BOOL CardPresent = mcd_CardDetectUpdateStatus();
+
+    g_mcdCardDetectHandler(CardPresent);
+}
+
+// =============================================================================
+// mcd_SetCardDetectHandler
+// -----------------------------------------------------------------------------
+/// Register a handler for card detection
+///
+/// @param handler function called when insertion/removal is detected.
+// =============================================================================
+MCD_ERR_T mcd_SetCardDetectHandler(MCD_CARD_DETECT_HANDLER_T handler)
+{
+    if(NULL == g_mcdConfig)
+    {
+        g_mcdConfig = tgt_GetMcdConfig();
+    }
+
+    if(g_mcdConfig->cardDetectGpio == HAL_GPIO_NONE)
+    {
+        return MCD_ERR_NO_HOTPLUG;
+    }
+
+    if(NULL != handler)
+    {
+        HAL_GPIO_CFG_T cfg  = 
+            {
+            .direction      = HAL_GPIO_DIRECTION_INPUT,
+            .irqMask        = 
+                {
+                .rising     = TRUE,
+                .falling    = TRUE,
+                .debounce   = TRUE,
+                .level      = FALSE
+                },
+            .irqHandler     = mcd_CardDetectHandler
+            };
+
+        hal_GpioOpen(g_mcdConfig->cardDetectGpio, &cfg);
+        g_mcdCardDetectHandler = handler;
+    }
+    else
+    {
+        hal_GpioClose(g_mcdConfig->cardDetectGpio);
+        g_mcdCardDetectHandler = NULL;
+    }
+    
+    return MCD_ERR_NO;
+}
+
+// =============================================================================
+// mcd_CardStatus
+// -----------------------------------------------------------------------------
+/// Return the card status
+///
+/// @return Card status see #MCD_STATUS_T
+// =============================================================================
+MCD_STATUS_T mcd_CardStatus(void)
+{
+    mcd_CardDetectUpdateStatus();
+    return g_mcdStatus;
+}
+#endif
+
+// =============================================================================
+// mcd_SdmmcWaitResp
+// -----------------------------------------------------------------------------
+/// Wait for a response for a time configured by MCD_RESP_TIMEOUT
+/// @return MCD_ERR_NO if a response with a good crc was received,
+///         MCD_ERR_CARD_NO_RESPONSE if no response was received within the 
+/// driver configured timeout.
+//          MCD_ERR_CARD_RESPONSE_BAD_CRC if the received response presented
+//  a bad CRC.
+// =============================================================================
+static MCD_ERR_T mcd_SdmmcWaitResp(void)
+{
+    HAL_SDMMC_OP_STATUS_T status = hal_SdmmcGetOpStatus();
+    u32 startTime = hal_TimGetUpTime(); 
+    u32 rsp_time_out;
+    
+    rsp_time_out =  (MCD_CARD_V1 == g_mcdVer) ? MCD_RESP_TIMEOUT_V1:MCD_RESP_TIMEOUT_V2;
+    
+    while(hal_TimGetUpTime() - startTime < rsp_time_out &&status.fields.noResponseReceived)
+    {
+        status = hal_SdmmcGetOpStatus();
+    }
+
+    if (status.fields.noResponseReceived)
+    {
+        MCD_TRACE(MCD_INFO_TRC, 0, "Response is Time out");
+        return MCD_ERR_CARD_NO_RESPONSE;
+    }
+
+    if(status.fields.responseCrcError)
+    {
+        MCD_TRACE(MCD_INFO_TRC, 0, "Response CRC is Error");
+        return MCD_ERR_CARD_RESPONSE_BAD_CRC;
+    }
+
+    return MCD_ERR_NO;
+}
+
+//=============================================================================
+// mcd_SdmmcReadCheckCrc
+//-----------------------------------------------------------------------------
+/// Check the read state of the sdmmc card.
+/// @return MCD_ERR_NO if the Crc of read data was correct, 
+/// MCD_ERR_CARD_RESPONSE_BAD_CRC otherwise.
+//=============================================================================
+static MCD_ERR_T mcd_SdmmcReadCheckCrc(void)
+{  
+    HAL_SDMMC_OP_STATUS_T operationStatus;
+    operationStatus = hal_SdmmcGetOpStatus();
+    if (operationStatus.fields.dataError != 0) // 0 means no CRC error during transmission
+    {
+        MCD_TRACE(MCD_INFO_TRC, 0, "sdC status:%0x", operationStatus.reg);
+        return MCD_ERR_CARD_RESPONSE_BAD_CRC;
+    }
+    else
+    {
+        return MCD_ERR_NO;
+    }
+}
+
+//=============================================================================
+// mcd_SdmmcWriteCheckCrc
+//-----------------------------------------------------------------------------
+/// Check the crc state of the write operation of the sdmmc card.
+/// @return MCD_ERR_NO if the Crc of read data was correct, 
+/// MCD_ERR_CARD_RESPONSE_BAD_CRC otherwise.
+//=============================================================================
+static MCD_ERR_T mcd_SdmmcWriteCheckCrc(void)
+{
+    HAL_SDMMC_OP_STATUS_T operationStatus;
+    operationStatus = hal_SdmmcGetOpStatus();
+
+    if (operationStatus.fields.crcStatus != 2) // 0b010 = transmissionRight TODO a macro ?
+    {
+        MCD_TRACE(MCD_INFO_TRC, 0, "sdC status:%0x", operationStatus.reg);
+        return MCD_ERR_CARD_RESPONSE_BAD_CRC;
+    }
+    else
+    {
+        return MCD_ERR_NO;
+    }
+}
+
+// =============================================================================
+// mcd_SdmmcSendCmd
+// -----------------------------------------------------------------------------
+/// Send a command to the card, and fetch the response if one is expected.
+/// @param cmd CMD to send
+/// @param arg Argument of the ACMD.
+/// @param resp Buffer to store card response.
+/// @param suspend Not supported.
+/// @return MCD_ERR_NO if a response with a good crc was received,
+///         MCD_ERR_CARD_NO_RESPONSE if no reponse was received within the 
+/// driver configured timeout.
+///          MCD_ERR_CARD_RESPONSE_BAD_CRC if the received response presented
+///  a bad CRC.
+///         MCD_ERR_CARD_TIMEOUT if the card timedout during procedure.
+// =============================================================================
+static MCD_ERR_T mcd_SdmmcSendCmd(HAL_SDMMC_CMD_T cmd, u32 arg,
+                                  u32* resp, BOOL suspend)
+{
+    MCD_ERR_T errStatus = MCD_ERR_NO;
+    MCD_CARD_STATUS_T cardStatus = {0};
+    u32  cmd55Response[4] = {0, 0, 0, 0};
+    if (cmd & HAL_SDMMC_ACMD_SEL)
+    {
+        // This is an application specific command, 
+        // we send the CMD55 first
+        hal_SdmmcSendCmd(HAL_SDMMC_CMD_APP_CMD, g_mcdRcaReg, FALSE);
+        
+        // Wait for command over
+        if (MCD_ERR_CARD_TIMEOUT == mcd_SdmmcWaitCmdOver())
+        {
+            MCD_TRACE(MCD_INFO_TRC, 0, "Cmd55 Send is Time out");
+            return MCD_ERR_CARD_TIMEOUT;
+        }
+        
+        // Wait for response
+        if (hal_SdmmcNeedResponse(HAL_SDMMC_CMD_APP_CMD))
+        {
+            errStatus = mcd_SdmmcWaitResp();
+        }
+        if (MCD_ERR_NO != errStatus)
+        {
+            MCD_TRACE(MCD_INFO_TRC, 0, "cmd55 response error");
+            return errStatus;
+        }
+
+        // Fetch response
+        hal_SdmmcGetResp(HAL_SDMMC_CMD_APP_CMD, cmd55Response, FALSE);
+
+        cardStatus.reg = cmd55Response[0];
+        if(HAL_SDMMC_CMD_SEND_OP_COND == cmd) // for some special card
+        {
+           //if (!(cardStatus.fields.readyForData) || !(cardStatus.fields.appCmd))
+           if (!(cardStatus.fields.appCmd))
+            {
+                MCD_TRACE(MCD_INFO_TRC, 0, "cmd55(acmd41) status=%0x", cardStatus.reg);
+                return MCD_ERR;
+            }
+        }
+        else
+        {
+            if (!(cardStatus.fields.readyForData) || !(cardStatus.fields.appCmd))
+            {
+                MCD_TRACE(MCD_INFO_TRC, 0, "cmd55 status=%0x", cardStatus.reg);
+                return MCD_ERR;
+            }
+
+        }
+    }
+
+    // Send proper command. If it was an ACMD, the CMD55 have just been sent.
+    hal_SdmmcSendCmd(cmd, arg, suspend);
+
+    // Wait for command to be sent 
+    errStatus = mcd_SdmmcWaitCmdOver();
+    
+
+    if (MCD_ERR_CARD_TIMEOUT == errStatus)
+    {
+        if (cmd & HAL_SDMMC_ACMD_SEL)
+        {
+            MCD_TRACE(MCD_INFO_TRC, 0, "ACMD %d Sending Timed out", (cmd & HAL_SDMMC_CMD_MASK));
+        }
+        else
+        {
+            MCD_TRACE(MCD_INFO_TRC, 0, "CMD %d Sending Timed out", (cmd & HAL_SDMMC_CMD_MASK));
+        }
+        return MCD_ERR_CARD_TIMEOUT;
+    }
+
+    // Wait for response and get its argument
+    if (hal_SdmmcNeedResponse(cmd))
+    {
+        errStatus = mcd_SdmmcWaitResp();
+    }
+
+    if (MCD_ERR_NO != errStatus)
+    {
+        if (cmd & HAL_SDMMC_ACMD_SEL)
+        {
+            MCD_TRACE(MCD_INFO_TRC, 0, "ACMD %d Response Error", (cmd & HAL_SDMMC_CMD_MASK));
+        }
+        else
+        {
+            MCD_TRACE(MCD_INFO_TRC, 0, "CMD %d Response Error", (cmd & HAL_SDMMC_CMD_MASK));
+            return errStatus;
+        }
+    }
+
+    // Fetch response
+    hal_SdmmcGetResp(cmd, resp, FALSE);
+
+    //FOR DEBUG: MCD_TRACE(MCD_INFO_TRC, 0, "CMD %d Response is %#x", (cmd & HAL_SDMMC_CMD_MASK), resp[0]);
+
+    return MCD_ERR_NO;
+}
+
+// =============================================================================
+// mcd_SdmmcInitCid
+// -----------------------------------------------------------------------------
+/// Set the CID in the driver from the data read on the card.
+/// @param cid 4 word array read from the card, holding the CID register value.
+// =============================================================================
+static MCD_ERR_T mcd_SdmmcInitCid(u32* cid)
+{
+    // Fill the structure with the register bitfields value.
+    g_mcdCidReg.mid     = (u8)((cid[3]&(0xff<<24))>>24);
+    g_mcdCidReg.oid     = (cid[3]&(0xffff<<8))>>8;
+    g_mcdCidReg.pnm2    = (u8)(cid[3]&0xff);
+    g_mcdCidReg.pnm1    = cid[2];
+    g_mcdCidReg.prv     = (u8)((cid[1]&(0xff<<24))>>24);
+    g_mcdCidReg.psn     = (cid[1]&0xffffff)<<8;
+    g_mcdCidReg.psn     = g_mcdCidReg.psn|((cid[0]&(0xff<<23))>>23);
+    g_mcdCidReg.mdt     = (cid[0]&(0xfff<<7))>>7;
+    g_mcdCidReg.crc     = (u8)(cid[0]&0x7f);
+    
+    return MCD_ERR_NO;
+}
+
+#define MCD_CSD_VERSION_1       0
+#define MCD_CSD_VERSION_2       1
+// =============================================================================
+// mcd_SdmmcInitCsd
+// -----------------------------------------------------------------------------
+/// Fill MCD_CSD_T structure from the array of data read from the card
+/// 
+/// @param csd Pointer to the structure
+/// @param csdRaw Pointer to the raw data.
+/// @return MCD_ERR_NO
+// =============================================================================
+static MCD_ERR_T mcd_SdmmcInitCsd(MCD_CSD_T* csd, u32* csdRaw)
+{
+    // CF SD spec version2, CSD version 1 ?
+    csd->csdStructure       = (u8)((csdRaw[3]&(0x3<<30))>>30);
+    
+    // Byte 47 to 75 are different depending on the version 
+    // of the CSD srtucture.
+    csd->specVers           = (u8)((csdRaw[3]&(0xf<26))>>26);
+    csd->taac               = (u8)((csdRaw[3]&(0xff<<16))>>16);
+    csd->nsac               = (u8)((csdRaw[3]&(0xff<<8))>>8);
+    csd->tranSpeed          = (u8)(csdRaw[3]&0xff);
+
+    csd->ccc                = (csdRaw[2]&(0xfff<<20))>>20;
+    csd->readBlLen          = (u8)((csdRaw[2]&(0xf<<16))>>16);
+    csd->readBlPartial      = (u8)((csdRaw[2]&(0x1<<15))>>15);
+    csd->writeBlkMisalign   = (u8)((csdRaw[2]&(0x1<<14))>>14);
+    csd->readBlkMisalign    = (u8)((csdRaw[2]&(0x1<<13))>>13);
+    csd->dsrImp             = (u8)((csdRaw[2]&(0x1<<12))>>12);
+
+    if (csd->csdStructure == MCD_CSD_VERSION_1)
+    {
+        csd->cSize              = (csdRaw[2]&0x3ff)<<2;
+
+        csd->cSize              = csd->cSize|((csdRaw[1]&(0x3<<30))>>30);
+        csd->vddRCurrMin        = (u8)((csdRaw[1]&(0x7<<27))>>27);
+        csd->vddRCurrMax        = (u8)((csdRaw[1]&(0x7<<24))>>24);
+        csd->vddWCurrMin        = (u8)((csdRaw[1]&(0x7<<21))>>21);
+        csd->vddWCurrMax        = (u8)((csdRaw[1]&(0x7<<18))>>18);
+        csd->cSizeMult          = (u8)((csdRaw[1]&(0x7<<15))>>15);
+        
+        // Block number: cf Spec Version 2 page 103 (116).
+        csd->blockNumber        = (csd->cSize + 1)<<(csd->cSizeMult + 2);
+    }
+    else
+    {
+        // csd->csdStructure == MCD_CSD_VERSION_2
+        csd->cSize = ((csdRaw[2]&0x3f))|((csdRaw[1]&(0xffff<<16))>>16);
+        
+        // Other fields are undefined --> zeroed
+        csd->vddRCurrMin = 0;
+        csd->vddRCurrMax = 0;
+        csd->vddWCurrMin = 0;
+        csd->vddWCurrMax = 0;
+        csd->cSizeMult   = 0;
+        
+        // Block number: cf Spec Version 2 page 109 (122).
+        csd->blockNumber        = (csd->cSize + 1) * 1024;
+        //should check incompatible size and return MCD_ERR_UNUSABLE_CARD;
+    }
+
+    csd->eraseBlkEnable     = (u8)((csdRaw[1]&(0x1<<14))>>14);
+    csd->sectorSize         = (u8)((csdRaw[1]&(0x7f<<7))>>7);
+    csd->wpGrpSize          = (u8)(csdRaw[1]&0x7f);
+
+    csd->wpGrpEnable        = (u8)((csdRaw[0]&(0x1<<31))>>31);
+    csd->r2wFactor          = (u8)((csdRaw[0]&(0x7<<26))>>26);
+    csd->writeBlLen         = (u8)((csdRaw[0]&(0xf<<22))>>22);
+    csd->writeBlPartial     = (u8)((csdRaw[0]&(0x1<<21))>>21);
+    csd->fileFormatGrp      = (u8)((csdRaw[0]&(0x1<<15))>>15);
+    csd->copy               = (u8)((csdRaw[0]&(0x1<<14))>>14);
+    csd->permWriteProtect   = (u8)((csdRaw[0]&(0x1<<13))>>13);
+    csd->tmpWriteProtect    = (u8)((csdRaw[0]&(0x1<<12))>>12);
+    csd->fileFormat         = (u8)((csdRaw[0]&(0x3<<10))>>10);
+    csd->crc                = (u8)((csdRaw[0]&(0x7f<<1))>>1);
+
+
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:csdStructure = %d", csd->csdStructure        ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:specVers     = %d", csd->specVers           ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:taac         = %d", csd->taac                ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:nsac         = %d", csd->nsac                ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:tranSpeed    = %d", csd->tranSpeed           ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:ccc          = %d", csd->ccc             ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:readBlLen    = %d", csd->readBlLen           ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:readBlPartial = %d", csd->readBlPartial      ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:writeBlkMisalign = %d", csd->writeBlkMisalign    ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:readBlkMisalign  = %d", csd->readBlkMisalign    ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:dsrImp       = %d", csd->dsrImp              ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:cSize        = %d", csd->cSize               ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:vddRCurrMin  = %d", csd->vddRCurrMin     ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:vddRCurrMax  = %d", csd->vddRCurrMax     ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:vddWCurrMin  = %d", csd->vddWCurrMin     ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:vddWCurrMax  = %d", csd->vddWCurrMax     ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:cSizeMult    = %d", csd->cSizeMult           ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:eraseBlkEnable = %d", csd->eraseBlkEnable        ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:sectorSize   = %d", csd->sectorSize          ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:wpGrpSize    = %d", csd->wpGrpSize           ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:wpGrpEnable  = %d", csd->wpGrpEnable     ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:r2wFactor    = %d", csd->r2wFactor           ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:writeBlLen   = %d", csd->writeBlLen          ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:writeBlPartial = %d", csd->writeBlPartial        ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:fileFormatGrp = %d", csd->fileFormatGrp       ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:copy  = %d", csd->copy                 );
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:permWriteProtect = %d", csd->permWriteProtect      );
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:tmpWriteProtect  = %d", csd->tmpWriteProtect ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:fileFormat       = %d", csd->fileFormat          ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:crc              = %d", csd->crc                ); 
+    MCD_TRACE(MCD_INFO_TRC, 0, "CSD:block number     = %d", csd->blockNumber        ); 
+
+    return MCD_ERR_NO;
+}
+
+// =============================================================================
+//  FUNCTIONS (public)
+// =============================================================================
+
+// =============================================================================
+// mcd_ReadCsd
+// -----------------------------------------------------------------------------
+/// @brief Read the MMC CSD register
+/// @param mcdCsd Pointer to the structure where the MMC CSD register info
+/// are going to be written. 
+// =============================================================================
+static MCD_ERR_T mcd_ReadCsd(MCD_CSD_T* mcdCsd)
+{
+    MCD_ERR_T errStatus = MCD_ERR_NO;
+    u32 response[4];
+
+    // Get card CSD
+    errStatus = mcd_SdmmcSendCmd(HAL_SDMMC_CMD_SEND_CSD, g_mcdRcaReg, response, FALSE);
+    if (errStatus == MCD_ERR_NO)
+    {
+        errStatus = mcd_SdmmcInitCsd(mcdCsd, response);
+    }
+
+    // Store it localy
+    // FIXME: Is this real ? cf Physical Spec version 2
+    // page 59 (72) about CMD16 : default block length
+    // is 512 bytes. Isn't 512 bytes a good block
+    // length ? And I quote : "In both cases, if block length is set larger
+    // than 512Bytes, the card sets the BLOCK_LEN_ERROR bit."
+    g_mcdBlockLen = (1 << mcdCsd->readBlLen);
+    //if (g_mcdBlockLen > 512)
+    //{
+        g_mcdBlockLen = 512;
+    //}
+    //g_mcdNbBlock  = mcdCsd->blockNumber * ((1 << mcdCsd->readBlLen)/g_mcdBlockLen);
+    g_mcdNbBlock  = mcdCsd->blockNumber * ((1 << mcdCsd->readBlLen)>>9);
+
+    return errStatus;
+}
+
+
+// =============================================================================
+// mcd_Open
+// -----------------------------------------------------------------------------
+/// @brief Open the SD-MMC chip
+/// This function does the init process of the MMC chip, including reseting
+/// the chip, sending a command of init to MMC, and reading the CSD
+/// configurations.
+///
+/// @param mcdCsd Pointer to the structure where the MMC CSD register info
+/// are going to be written.
+///
+/// @param mcdVer is t card version.
+// =============================================================================
+MCD_ERR_T mcd_Open(MCD_CSD_T* mcdCsd, MCD_CARD_VER mcdVer)
+{
+    MCD_ERR_T                  errStatus   = MCD_ERR_NO;
+    u32                     response[4] = {0, 0, 0, 0};
+    MCD_CARD_STATUS_T          cardStatus  = {0};
+    BOOL                       isMmc       = FALSE;
+    HAL_SDMMC_DATA_BUS_WIDTH_T dataBusWidth;
+    u32 startTime = 0;
+    
+    //MCD_PROFILE_FUNCTION_ENTER(mcd_Open);
+    MCD_TRACE(MCD_INFO_TRC, 0, "mcd_Open starts ...");
+
+#if 0
+    // Check concurrency. Only one mcd_Open.
+    u32 cs = hal_SysEnterCriticalSection();
+    if (g_mcdSemaphore == 0xFF)
+    {
+        // Create semaphore and go on with the driver.
+        
+        // NOTE: This semaphore is never deleted for now, as
+        // 1. sema deletion while other task is waiting for it will cause an error;
+        // 2. sema deletion will make trouble if already-open state is considered OK.
+        g_mcdSemaphore = sxr_NewSemaphore(1);
+    }
+    hal_SysExitCriticalSection(cs);
+
+    // Following operation should be kept protected
+    MCD_CS_ENTER;
+
+    if(NULL == g_mcdConfig)
+    {
+        g_mcdConfig = tgt_GetMcdConfig();
+    }
+
+    if(g_mcdConfig->cardDetectGpio != HAL_GPIO_NONE)
+    {
+        // Only if GPIO for detection exists, else we try to open anyway.
+        if(!mcd_CardDetectUpdateStatus())
+        {
+            MCD_TRACE(MCD_INFO_TRC, 0, "mcd_Open: GPIO detection - no card");
+            MCD_CS_EXIT;
+            MCD_PROFILE_FUNCTION_EXIT(mcd_Open);
+            return MCD_ERR_NO_CARD;
+        }
+    }
+
+    if (g_mcdStatus == MCD_STATUS_OPEN)
+    {
+        // Already opened, just return OK
+        MCD_TRACE(MCD_INFO_TRC, 0, "mcd_Open: Already opened");
+        *mcdCsd = g_mcdLatestCsd;
+        
+        MCD_CS_EXIT;
+        MCD_PROFILE_FUNCTION_EXIT(mcd_Open);
+        return MCD_ERR_NO;
+    }
+#endif
+
+    //printf("mcd_Open\n");
+
+    if(MCD_CARD_V1 == mcdVer)
+    {
+        hal_SdmmcOpen(0x05);
+    }
+    else
+    {
+        hal_SdmmcOpen(0x0);
+    }
+    
+    ///@todo: should use g_mcdConfig->dat3HasPullDown if true, we can handle 
+    /// basic card detection as follows:
+    /// call hal_SdmmcGetCardDetectPinLevel() to check if card as changed (back 1)
+    /// send command ACMD42 to disable internal pull up (so pin goes to 0)
+    /// meaning if pin is 1, there was a removal, file system should be told to
+    /// remount the card as it might be a different one (or the content might have
+    /// been changed externally).
+
+    // RCA = 0x0000 for card identification phase.
+    g_mcdRcaReg = 0;
+
+    g_mcdSdmmcFreq = 200000;
+    hal_SdmmcSetClk(g_mcdSdmmcFreq);
+
+    // assume it's not an SDHC card
+    g_mcdCardIsSdhc = FALSE;
+    g_mcdOcrReg = MCD_SDMMC_OCR_VOLT_PROF_MASK;
+
+    //printf("CMD0\n");
+
+    // Send Power On command
+    errStatus = mcd_SdmmcSendCmd(HAL_SDMMC_CMD_GO_IDLE_STATE, BROAD_ADDR, response, FALSE);
+    if (MCD_ERR_NO != errStatus)
+    {
+        printf("CMD0 Error\n");
+        g_mcdStatus = MCD_STATUS_NOTPRESENT;
+        MCD_TRACE(MCD_INFO_TRC, 0, "Because Power on, Initialize Failed");
+        MCD_TRACE(MCD_INFO_TRC, 0, "Error Status = %d", errStatus);
+        hal_SdmmcClose();
+
+        //MCD_CS_EXIT;
+        //MCD_PROFILE_FUNCTION_EXIT(mcd_Open);
+        return errStatus;
+    }
+    else
+    {
+        //printf("CMD0 Done\n");
+        MCD_TRACE(MCD_INFO_TRC, 0, "Card successfully in Idle state");
+    }
+
+    //printf("CMD8\n");
+
+    // Check if the card is a spec vers.2 one
+    errStatus = mcd_SdmmcSendCmd(HAL_SDMMC_CMD_SEND_IF_COND, (MCD_CMD8_VOLTAGE_SEL | MCD_CMD8_CHECK_PATTERN), response, FALSE);
+    if (MCD_ERR_NO != errStatus)
+    {
+        printf("CMD8 Error\n");
+        MCD_TRACE(MCD_INFO_TRC, 0, "This card doesn't comply to the spec version 2.0");
+    }
+    else
+    {
+        // This card comply to the SD spec version 2. Is it compatible with the
+        // proposed voltage, and is it an high capacity one ?
+        if (response[0] != (MCD_CMD8_VOLTAGE_SEL | MCD_CMD8_CHECK_PATTERN))
+        {
+            printf("CMD8, Not Supported\n");
+            // Bad pattern or unsupported voltage.
+            MCD_TRACE(MCD_INFO_TRC, 0, "Bad pattern or unsupported voltage");
+            hal_SdmmcClose();
+            g_mcdStatus = MCD_STATUS_NOTPRESENT;
+            //g_mcdVer = MCD_CARD_V1;  
+            //MCD_CS_EXIT;
+            //MCD_PROFILE_FUNCTION_EXIT(mcd_Open);
+            return MCD_ERR_UNUSABLE_CARD;
+        }
+        else
+        {
+            //printf("CMD8, Supported\n");
+            g_mcdOcrReg |= MCD_OCR_HCS;
+        }
+    }
+
+    // TODO HCS mask bit to ACMD 41 if high capacity
+    // Send OCR, as long as the card return busy
+    startTime = hal_TimGetUpTime();
+    
+    while(1)
+    {
+        if(hal_TimGetUpTime() - startTime > MCD_SDMMC_OCR_TIMEOUT )
+        {
+            printf("ACMD41, Retry Timeout\n");
+            MCD_TRACE(MCD_INFO_TRC, 0, "SD OCR timeout");
+            hal_SdmmcClose();
+            g_mcdStatus = MCD_STATUS_NOTPRESENT;
+            
+            //MCD_CS_EXIT;
+            //MCD_PROFILE_FUNCTION_EXIT(mcd_Open);
+            return MCD_ERR;
+        }
+
+        //printf("ACMD41\n");
+        errStatus = mcd_SdmmcSendCmd(HAL_SDMMC_CMD_SEND_OP_COND, g_mcdOcrReg, response, FALSE);
+        if (errStatus == MCD_ERR_CARD_NO_RESPONSE)
+        {
+            printf("ACMD41, No Response, MMC Card?\n");
+            MCD_TRACE(MCD_INFO_TRC, 0, "Inserted Card is a MMC");
+            // CMD 55 was not recognised: this is not an SD card !
+            isMmc = TRUE;
+            break;
+        }
+
+        // Bit 31 is power up busy status bit(pdf spec p. 109)
+        g_mcdOcrReg = (response[0] & 0x7fffffff);
+        
+        // Power up busy bit is set to 1, 
+        // we can continue ...
+        if (response[0] & 0x80000000)
+        {
+            //printf("ACMD41, PowerUp done\n");
+            // Version 2?
+            if((g_mcdOcrReg & MCD_OCR_HCS) == MCD_OCR_HCS)
+            {
+                // Card is V2: check for high capacity
+                if (response[0] & MCD_OCR_CCS_MASK)
+                {
+                    g_mcdCardIsSdhc = TRUE;
+                    printf("Card is SDHC\n");
+                    MCD_TRACE(MCD_INFO_TRC, 0, "Card is SDHC");
+                }
+                else
+                {
+                    g_mcdCardIsSdhc = FALSE;
+                    printf("Card is V2, but NOT SDHC\n");
+                    MCD_TRACE(MCD_INFO_TRC, 0, "Card is standard capacity SD");
+                }
+            }
+            else {
+                printf("Card is NOT V2\n");
+            }
+            MCD_TRACE(MCD_INFO_TRC, 0, "Inserted Card is a SD card");
+            break;
+        }
+    }
+
+    if (isMmc)
+    {
+        printf("MMC Card\n");
+        while(1)
+        {
+            if(hal_TimGetUpTime() - startTime > MCD_SDMMC_OCR_TIMEOUT )
+            {
+                MCD_TRACE(MCD_INFO_TRC, 0, "MMC OCR timeout");
+                hal_SdmmcClose();
+                g_mcdStatus = MCD_STATUS_NOTPRESENT;
+            
+                //MCD_CS_EXIT;
+                //MCD_PROFILE_FUNCTION_EXIT(mcd_Open);
+                return MCD_ERR;
+            }
+            
+            errStatus = mcd_SdmmcSendCmd(HAL_SDMMC_CMD_MMC_SEND_OP_COND, g_mcdOcrReg, response, FALSE);
+            if (errStatus == MCD_ERR_CARD_NO_RESPONSE)
+            {
+                MCD_TRACE(MCD_INFO_TRC, 0, "MMC OCR didn't answer");
+                hal_SdmmcClose();
+                g_mcdStatus = MCD_STATUS_NOTPRESENT;
+            
+                //MCD_CS_EXIT;
+                //MCD_PROFILE_FUNCTION_EXIT(mcd_Open);
+                return MCD_ERR;
+            }
+
+            // Bit 31 is power up busy status bit(pdf spec p. 109)
+            g_mcdOcrReg = (response[0] & 0x7fffffff);
+            
+            // Power up busy bit is set to 1, 
+            // we can continue ...
+            if (response[0] & 0x80000000)
+            {
+                break;
+            }
+        }    
+
+    }
+
+    //printf("CMD2\n");
+    
+    // Get the CID of the card.
+    errStatus = mcd_SdmmcSendCmd(HAL_SDMMC_CMD_ALL_SEND_CID, BROAD_ADDR, response, FALSE);
+    if(MCD_ERR_NO != errStatus)
+    {
+        printf("CMD2 Fail\n");
+        MCD_TRACE(MCD_INFO_TRC, 0, "Because Get CID, Initialize Failed");
+        hal_SdmmcClose();
+        g_mcdStatus = MCD_STATUS_NOTPRESENT;
+            
+        //MCD_CS_EXIT;
+        //MCD_PROFILE_FUNCTION_EXIT(mcd_Open);
+        return errStatus;
+    }
+    mcd_SdmmcInitCid(response);
+
+    //printf("CMD3\n");
+    
+    // Get card RCA
+    errStatus = mcd_SdmmcSendCmd(HAL_SDMMC_CMD_SEND_RELATIVE_ADDR, BROAD_ADDR, response, FALSE);
+    if (MCD_ERR_NO != errStatus)
+    {
+        printf("CMD3 Fail\n");
+        MCD_TRACE(MCD_INFO_TRC, 0, "Because Get Relative Address, Initialize Failed");
+        hal_SdmmcClose();
+        g_mcdStatus = MCD_STATUS_NOTPRESENT;
+            
+        //MCD_CS_EXIT;
+        //MCD_PROFILE_FUNCTION_EXIT(mcd_Open);
+        return errStatus;
+    }
+    
+    // Spec Ver 2 pdf p. 81 - rca are the 16 upper bit of this 
+    // R6 answer. (lower bits are stuff bits)
+    g_mcdRcaReg = response[0] & 0xffff0000;
+
+    //printf("CMD9\n");
+    // Get card CSD
+    errStatus = mcd_ReadCsd(mcdCsd);
+    if (errStatus != MCD_ERR_NO)
+    {
+        printf("CMD9 Fail\n");
+        MCD_TRACE(MCD_INFO_TRC, 0, "Because Get CSD, Initialize Failed");
+        hal_SdmmcClose();
+        g_mcdStatus = MCD_STATUS_NOTPRESENT;
+            
+        //MCD_CS_EXIT;
+        //MCD_PROFILE_FUNCTION_EXIT(mcd_Open);
+        return errStatus;
+    }
+
+    // If possible, set the DSR
+    if (mcdCsd->dsrImp)
+    {
+        //printf("CMD4\n");
+        errStatus = mcd_SdmmcSendCmd(HAL_SDMMC_CMD_SET_DSR, g_mcdSdmmcDsr, response, FALSE);
+        if (errStatus != MCD_ERR_NO)
+        {
+            printf("CMD4 Fail\n");
+            MCD_TRACE(MCD_INFO_TRC, 0, "Because Set DSR, Initialize Failed");
+            hal_SdmmcClose();
+            g_mcdStatus = MCD_STATUS_NOTPRESENT;
+            
+            //MCD_CS_EXIT;
+            //MCD_PROFILE_FUNCTION_EXIT(mcd_Open);
+            return errStatus;
+        }
+    }
+
+    //printf("CMD7\n");
+    // Select the card 
+    errStatus = mcd_SdmmcSendCmd(HAL_SDMMC_CMD_SELECT_CARD, g_mcdRcaReg, response, FALSE);
+    if (errStatus != MCD_ERR_NO)
+    {
+        printf("CMD7 Fail\n");
+        MCD_TRACE(MCD_INFO_TRC, 0, "Because Select Card, Initialize Failed");
+        MCD_TRACE(MCD_INFO_TRC, 0, "errStatus = %d", errStatus);
+        hal_SdmmcClose();
+        g_mcdStatus = MCD_STATUS_NOTPRESENT;
+            
+        //MCD_CS_EXIT;
+        //MCD_PROFILE_FUNCTION_EXIT(mcd_Open);
+        return errStatus;
+    }
+    // That command returns the card status, we check we're in data mode.
+    cardStatus.reg = response[0];
+
+    if(!(cardStatus.fields.readyForData))
+    {
+        MCD_TRACE(MCD_INFO_TRC, 0, "CMD7 status=%0x", cardStatus.reg);
+        hal_SdmmcClose();
+        g_mcdStatus = MCD_STATUS_NOTPRESENT;
+            
+        //MCD_CS_EXIT;
+        //MCD_PROFILE_FUNCTION_EXIT(mcd_Open);
+        return MCD_ERR;
+    }
+
+    // Set the bus width (use 4 data lines for SD cards only)
+    if (isMmc)
+    {
+        dataBusWidth = HAL_SDMMC_DATA_BUS_WIDTH_1;
+    }
+    else
+    {
+        
+        dataBusWidth = MCD_CARD_V1 == mcdVer ? HAL_SDMMC_DATA_BUS_WIDTH_1 : HAL_SDMMC_DATA_BUS_WIDTH_4;
+       
+    }
+
+    errStatus = mcd_SdmmcSendCmd(HAL_SDMMC_CMD_SET_BUS_WIDTH, dataBusWidth,
+                                  response, FALSE);
+    if (errStatus != MCD_ERR_NO)
+    {
+        MCD_TRACE(MCD_INFO_TRC, 0, "Because Set Bus, Initialize Failed");
+        hal_SdmmcClose();
+        g_mcdStatus = MCD_STATUS_NOTPRESENT;
+            
+        //MCD_CS_EXIT;
+        //MCD_PROFILE_FUNCTION_EXIT(mcd_Open);
+        return errStatus;
+    }
+
+    // That command returns the card status, in tran state ?
+    cardStatus.reg = response[0];
+    if (   !(cardStatus.fields.appCmd)
+        || !(cardStatus.fields.readyForData)
+        || (cardStatus.fields.currentState != MCD_CARD_STATE_TRAN))
+    {
+        MCD_TRACE(MCD_INFO_TRC, 0, "ACMD6 status=%0x", cardStatus.reg);
+        hal_SdmmcClose();
+        g_mcdStatus = MCD_STATUS_NOTPRESENT;
+            
+        //MCD_CS_EXIT;
+        //MCD_PROFILE_FUNCTION_EXIT(mcd_Open);
+        return MCD_ERR;
+    }
+    
+    // Configure the controller to use that many lines.
+    hal_SdmmcSetDataWidth(dataBusWidth);
+
+    // Configure the block lenght
+    errStatus = mcd_SdmmcSendCmd(HAL_SDMMC_CMD_SET_BLOCKLEN, g_mcdBlockLen, response, FALSE);
+    if (errStatus != MCD_ERR_NO)
+    {
+        MCD_TRACE(MCD_INFO_TRC, 0, "Because Set Block Length, Initialize Failed");
+        hal_SdmmcClose();
+        g_mcdStatus = MCD_STATUS_NOTPRESENT;
+            
+        //MCD_CS_EXIT;
+        //MCD_PROFILE_FUNCTION_EXIT(mcd_Open);
+        return errStatus;
+    }
+
+    // That command returns the card status, in tran state ?
+    cardStatus.reg = response[0];
+    {
+        MCD_CARD_STATUS_T expectedCardStatus;
+        expectedCardStatus.reg  = 0;
+        expectedCardStatus.fields.readyForData = 1;
+        expectedCardStatus.fields.currentState = MCD_CARD_STATE_TRAN;     
+        
+        if (cardStatus.reg != expectedCardStatus.reg)
+        {
+            MCD_TRACE(MCD_INFO_TRC, 0, "CMD16 status=%0x", cardStatus.reg);
+            hal_SdmmcClose();
+            g_mcdStatus = MCD_STATUS_NOTPRESENT;
+            
+            //MCD_CS_EXIT;
+            //MCD_PROFILE_FUNCTION_EXIT(mcd_Open);
+            return MCD_ERR;
+        }
+    }
+    
+    hal_SdmmcEnterDataTransferMode();
+
+    
+    // Set the clock of the SD bus for the fastest possible rate.
+ 
+    g_mcdSdmmcFreq = MCD_CARD_V1 == mcdVer ? 6000000 : 20000000;
+     
+    hal_SdmmcSetClk(g_mcdSdmmcFreq);
+
+    g_mcdLatestCsd = *mcdCsd;
+    g_mcdStatus = MCD_STATUS_OPEN;
+    hal_SdmmcSleep();
+    g_mcdVer = mcdVer;
+
+    //printf("mcd_Open Done\n");
+
+    //MCD_CS_EXIT;
+    //MCD_PROFILE_FUNCTION_EXIT(mcd_Open);
+    return MCD_ERR_NO;
+}
+
+// =============================================================================
+// mcd_Close
+// -----------------------------------------------------------------------------
+/// Close MCD.
+///
+/// To be called at the end of the operations
+/// @return MCD_ERR_NO if a response with a good crc was received,
+///         MCD_ERR_CARD_NO_RESPONSE if no reponse was received within the 
+/// driver configured timeout.
+///          MCD_ERR_CARD_RESPONSE_BAD_CRC if the received response presented
+///  a bad CRC.
+///         MCD_ERR_CARD_TIMEOUT if the card timedout during procedure.
+// =============================================================================
+MCD_ERR_T mcd_Close(void)
+{
+    MCD_TRACE(MCD_INFO_TRC, 0, "mcd_Close");
+
+    if (g_mcdSemaphore == 0xFF)
+    {
+        MCD_TRACE(MCD_INFO_TRC, 0, "mcd_Close: Never opened before");
+        return MCD_ERR_NO;
+    }
+
+    //MCD_CS_ENTER;
+
+    MCD_ERR_T errStatus = MCD_ERR_NO;
+    
+    //MCD_PROFILE_FUNCTION_ENTER(mcd_Close);
+
+    // Don't close the MCD driver if a transfer is in progress,
+    // and be definitive about it:
+    if (hal_SdmmcIsBusy() == TRUE)
+    {
+        MCD_TRACE(MCD_WARN_TRC, 0, "MCD: Attempt to close MCD while a transfer is in progress");
+    }
+
+    hal_SdmmcWakeUp();
+    
+    // Brutal force stop current transfer, if any.
+    hal_SdmmcStopTransfer(&g_mcdSdmmcTransfer);
+
+    // Close the SDMMC module
+    hal_SdmmcClose();
+
+    g_mcdStatus = MCD_STATUS_NOTOPEN_PRESENT; // without GPIO
+    //mcd_CardDetectUpdateStatus(); // Test GPIO for card detect
+
+    //MCD_CS_EXIT;
+    //MCD_PROFILE_FUNCTION_EXIT(mcd_Close);
+    return errStatus;
+}
+
+//=============================================================================
+// mcd_SdmmcTranState
+//-----------------------------------------------------------------------------
+/// Blocking function checking that the card is in the transfer state, 
+/// acknowledging thus that, for example, end of transmission.
+/// @param iter Number of attempt to be made.
+/// @param duration Sleeping time before the next attempt (in sys ticks). 
+//=============================================================================
+static MCD_ERR_T mcd_SdmmcTranState(u32 iter)
+{
+    u32 cardResponse[4] = {0, 0, 0, 0};
+    MCD_ERR_T errStatus = MCD_ERR_NO;
+    MCD_CARD_STATUS_T cardStatusTranState;
+    // Using reg to clear all bit of the bitfields that are not
+    // explicitly set.
+    cardStatusTranState.reg = 0;
+    cardStatusTranState.fields.readyForData = 1; 
+    cardStatusTranState.fields.currentState = MCD_CARD_STATE_TRAN;    
+    u32 startTime = hal_TimGetUpTime();
+    u32 time_out;
+
+    while(1)
+    {
+        //printf("CMD13, Set Trans State\n");
+
+        errStatus = mcd_SdmmcSendCmd(HAL_SDMMC_CMD_SEND_STATUS, g_mcdRcaReg, cardResponse, FALSE);
+        if (errStatus != MCD_ERR_NO)
+        {
+            printf("CMD13, Fail\n");
+            // error while sending the command
+            MCD_TRACE(MCD_INFO_TRC, 0, "Sd Tran Read Aft State error! err nb:%d", errStatus);
+            return MCD_ERR;
+        }
+        else if (cardResponse[0] == cardStatusTranState.reg)
+        {
+            //printf("CMD13, Done\n");
+            // the status is the expected one - success
+            return MCD_ERR_NO;
+        }
+        else
+        {
+            // try again
+            // check for timeout 
+            time_out =  (MCD_CARD_V1 == g_mcdVer) ? MCD_CMD_TIMEOUT_V1:MCD_CMD_TIMEOUT_V2;            
+            if (hal_TimGetUpTime() - startTime >  time_out )
+            {
+                printf("CMD13, Timeout\n");
+                MCD_TRACE(MCD_INFO_TRC, 0, "Sd Tran don't finished");
+                MCD_TRACE(MCD_INFO_TRC, 0, "current state =%0x", cardResponse[0]);
+                return MCD_ERR;
+            }
+        }
+    }
+}
+
+//=============================================================================
+// mcd_SdmmcMultBlockWrite
+//-----------------------------------------------------------------------------
+/// Write one or a bunch of data blocks.
+/// @param blockAddr Address on the card where to write data.
+/// @param pWrite Pointer towards the buffer of data to write.
+/// @param blockNum Number of blocks to write.
+//=============================================================================
+static MCD_ERR_T mcd_SdmmcMultBlockWrite(u8* blockAddr, u8* pWrite, u32 blockNum)
+{
+    u32 cardResponse[4] = {0, 0, 0, 0};
+    MCD_ERR_T errStatus = MCD_ERR_NO;
+    MCD_CARD_STATUS_T cardStatusTranState;
+    // Using reg to clear all bit of the bitfields that are not
+    // explicitly set.
+    cardStatusTranState.reg = 0;
+    cardStatusTranState.fields.readyForData = 1; 
+    cardStatusTranState.fields.currentState = MCD_CARD_STATE_TRAN;
+    
+    MCD_CARD_STATUS_T cardStatusPreErasedState;
+    cardStatusPreErasedState.reg    = 0;
+    cardStatusPreErasedState.fields.appCmd       = 1;
+    cardStatusPreErasedState.fields.readyForData = 1;
+    cardStatusPreErasedState.fields.currentState = MCD_CARD_STATE_TRAN;
+
+    MCD_CARD_STATUS_T cardStatusResponse = {0,};
+
+    u32 startTime = 0;
+
+    HAL_SDMMC_CMD_T writeCmd;
+    u32 tran_time_out;
+    u32 write_time_out;
+
+    g_mcdSdmmcTransfer.sysMemAddr = (u8*) pWrite;
+    g_mcdSdmmcTransfer.sdCardAddr = blockAddr;
+    g_mcdSdmmcTransfer.blockNum   = blockNum;
+    g_mcdSdmmcTransfer.blockSize  = g_mcdBlockLen;
+    g_mcdSdmmcTransfer.direction  = HAL_SDMMC_DIRECTION_WRITE;
+
+
+// FIXME find what the heck is that !:
+// program_right_num=0;
+
+    // Check buffer.
+    assert(pWrite != NULL, "SDMMC write: Buffer is NULL");
+    assert(((u32)pWrite & 0x3) ==0,
+               "SDMMC write: buffer is not aligned! addr=%08x", pWrite);
+    assert(blockNum>=1 && blockNum<= MCD_MAX_BLOCK_NUM,
+                "Block Num is overflow");
+        
+    // Check that the card is in tran (Transmission) state.
+    tran_time_out =  (MCD_CARD_V1 == g_mcdVer) ? MCD_TRAN_TIMEOUT_V1:MCD_TRAN_TIMEOUT_V2;
+    if (MCD_ERR_NO != mcd_SdmmcTranState(tran_time_out))
+    // 5200000, 0, initially, that is to say rougly 0.1 sec ?
+    {
+        MCD_TRACE(MCD_INFO_TRC, 0, "Write on Sdmmc while not in Tran state");
+        return MCD_ERR_CARD_TIMEOUT;
+    }
+
+    // The command for single block or multiple blocks are differents
+    if (blockNum == 1)
+    {
+        writeCmd = HAL_SDMMC_CMD_WRITE_SINGLE_BLOCK;
+    }
+    else
+    {
+        writeCmd = HAL_SDMMC_CMD_WRITE_MULT_BLOCK;
+    }
+
+    // PreErasing, to accelerate the multi-block write operations
+    if (blockNum >1)
+    {
+        //printf("SET_WR_BLK_COUNT\n");
+        if(MCD_ERR == mcd_SdmmcSendCmd(HAL_SDMMC_CMD_SET_WR_BLK_COUNT, blockNum, cardResponse, FALSE))
+        {
+            MCD_TRACE(MCD_INFO_TRC, 0, "Set Pre-erase Failed");
+            return MCD_ERR;
+        }
+
+        // Advance compatibility,to support 1.0 t-flash.
+        if (cardResponse[0] != cardStatusPreErasedState.reg)
+        {
+            MCD_TRACE(MCD_INFO_TRC, 0, "warning ACMD23 status=%0x", cardResponse[0]);
+           // cardResponse[0] = cardStatusPreErasedState.reg;
+            // return MCD_ERR;
+        }
+    }
+    
+
+    // Initiate data migration through Ifc.
+    if (hal_SdmmcTransfer(&g_mcdSdmmcTransfer) != 0)
+    {
+        MCD_TRACE(MCD_INFO_TRC, 0, "write sd no ifc channel");
+        return MCD_ERR_DMA_BUSY;
+    }
+
+    //printf("writeCmd\n");
+
+    // Initiate data migration of multiple blocks through SD bus.
+    errStatus = mcd_SdmmcSendCmd(writeCmd,
+                                 (u32)blockAddr,
+                                 cardResponse,
+                                 FALSE);
+    if (errStatus != MCD_ERR_NO)
+    {
+        printf("writeCmd Fail, err = %d\n", (int)errStatus);
+        MCD_TRACE(MCD_INFO_TRC, 0, "Set sd write had error");
+        hal_SdmmcStopTransfer(&g_mcdSdmmcTransfer);
+        return MCD_ERR_CMD;
+    }
+
+    cardStatusResponse.reg = cardResponse[0] ;
+    // Check for error, by listing all valid states
+    // TODO: FIXME, more states could be legal here
+    // The sixteen uper bits are error bits: they all must be null
+    // (Physical Spec V.2, p71)
+    if ((cardResponse[0] != cardStatusTranState.reg)
+     && !((cardStatusResponse.fields.readyForData == 1)   
+            && (cardStatusResponse.fields.currentState == MCD_CARD_STATE_RCV)
+            && ((cardStatusResponse.reg&0xFFFF0000) == 0)) 
+     && !(cardStatusResponse.fields.currentState == MCD_CARD_STATE_RCV
+            && ((cardStatusResponse.reg&0xFFFF0000) == 0))
+     && !(cardStatusResponse.fields.currentState == MCD_CARD_STATE_PRG
+            && ((cardStatusResponse.reg&0xFFFF0000) == 0))
+     )
+    {
+        MCD_TRACE(MCD_INFO_TRC, 0, "Write block,Card Reponse: %x", cardResponse[0]);
+        hal_SdmmcStopTransfer(&g_mcdSdmmcTransfer);
+        return MCD_ERR;
+    }
+
+
+    // Wait 
+    startTime = hal_TimGetUpTime();
+    write_time_out =  (MCD_CARD_V1 == g_mcdVer) ? MCD_WRITE_TIMEOUT_V1:MCD_WRITE_TIMEOUT_V2;
+    while(!hal_SdmmcTransferDone()) 
+    {
+        if (hal_TimGetUpTime() - startTime >  (write_time_out*blockNum))
+        {
+            printf("writeCmd Timeout\n");
+            MCD_TRACE(MCD_INFO_TRC, 0, "Write on Sdmmc timeout");
+            // Abort the transfert.
+            hal_SdmmcStopTransfer(&g_mcdSdmmcTransfer);
+            return MCD_ERR_CARD_TIMEOUT;
+        }
+    }
+    //printf("writeCmd Done\n");
+
+
+    // Nota: CMD12 (stop transfer) is automatically 
+    // sent by the SDMMC controller.
+
+    if (mcd_SdmmcWriteCheckCrc() != MCD_ERR_NO)
+    {
+        MCD_TRACE(MCD_INFO_TRC, 0, "SDMMC Write error");
+        return MCD_ERR;
+    }
+    //printf("CheckCRC Done\n");
+    
+    // Check that the card is in tran (Transmission) state.
+    if (MCD_ERR_NO != mcd_SdmmcTranState(tran_time_out))
+    // 5200000, 0, initially, that is to say rougly 0.1 sec ?
+    {
+        MCD_TRACE(MCD_INFO_TRC, 0, "Write on Sdmmc while not in Tran state");
+        return MCD_ERR_CARD_TIMEOUT;
+    }
+    //printf("Check Tran State Done\n");
+    return MCD_ERR_NO;
+
+}
+
+//=============================================================================
+// mcd_SdmmcMultBlockRead
+//-----------------------------------------------------------------------------
+/// Read one or a bunch of data blocks.
+/// @param blockAddr Address on the card where to read data.
+/// @param pRead Pointer towards the buffer of data to read.
+/// @param blockNum Number of blocks to read.
+//=============================================================================
+static MCD_ERR_T mcd_SdmmcMultBlockRead(u8* blockAddr, u8* pRead, u32 blockNum)
+{
+    u32                  cardResponse[4]     = {0, 0, 0, 0};
+    MCD_ERR_T               errStatus           = MCD_ERR_NO;
+    HAL_SDMMC_CMD_T         readCmd;
+    MCD_CARD_STATUS_T cardStatusTranState;
+    // Using reg to clear all bit of the bitfields that are not
+    // explicitly set.
+    cardStatusTranState.reg = 0;
+    cardStatusTranState.fields.readyForData = 1; 
+    cardStatusTranState.fields.currentState = MCD_CARD_STATE_TRAN;
+    
+    u32 startTime=0;
+    u32 tran_time_out;
+    u32 read_time_out;
+
+    g_mcdSdmmcTransfer.sysMemAddr = (u8*) pRead;
+    g_mcdSdmmcTransfer.sdCardAddr = blockAddr;
+    g_mcdSdmmcTransfer.blockNum   = blockNum;
+    g_mcdSdmmcTransfer.blockSize  = g_mcdBlockLen;
+    g_mcdSdmmcTransfer.direction  = HAL_SDMMC_DIRECTION_READ;
+    
+    // Check buffer.
+    assert(pRead != NULL, "SDMMC write: Buffer is NULL");
+    assert(((u32)pRead & 0x3) ==0, "SDMMC write: buffer is not aligned");
+    assert(blockNum>=1 && blockNum<= MCD_MAX_BLOCK_NUM,
+                "Block Num is overflow");
+
+    // Command are different for reading one or several blocks of data
+    if (blockNum == 1)
+    {
+        readCmd = HAL_SDMMC_CMD_READ_SINGLE_BLOCK;
+    }
+    else
+    {
+        readCmd = HAL_SDMMC_CMD_READ_MULT_BLOCK;
+    }
+
+    // Initiate data migration through Ifc.
+    if (hal_SdmmcTransfer(&g_mcdSdmmcTransfer) != 0)
+    {
+        MCD_TRACE(MCD_INFO_TRC, 0, "write sd no ifc channel");
+        return MCD_ERR_DMA_BUSY;
+    }
+
+    // Initiate data migration of multiple blocks through SD bus.
+    errStatus = mcd_SdmmcSendCmd(readCmd,
+                                  (u32)blockAddr,
+                                  cardResponse,
+                                  FALSE);
+    if (errStatus != MCD_ERR_NO)
+    {
+        printf("mcd_SdmmcMultBlockRead, send command error\n");
+        MCD_TRACE(MCD_INFO_TRC, 0, "Set sd write had error");
+        hal_SdmmcStopTransfer(&g_mcdSdmmcTransfer);
+        return MCD_ERR_CMD;
+    }
+
+    if (cardResponse[0] != cardStatusTranState.reg)
+    {
+        printf("mcd_SdmmcMultBlockRead, command response error\n");
+        MCD_TRACE(MCD_INFO_TRC, 0, "CMD%d status=%0x", cardResponse[0], readCmd);
+        hal_SdmmcStopTransfer(&g_mcdSdmmcTransfer);
+        return MCD_ERR;
+    }
+
+    // Wait 
+    startTime = hal_TimGetUpTime();
+    read_time_out =  (MCD_CARD_V1 == g_mcdVer) ? MCD_READ_TIMEOUT_V1:MCD_READ_TIMEOUT_V2;
+    while(!hal_SdmmcTransferDone()) 
+    {
+        if (hal_TimGetUpTime() - startTime > (read_time_out*blockNum))
+        {
+            printf("mcd_SdmmcMultBlockRead, timeout\n");
+            MCD_TRACE(MCD_INFO_TRC, 0, "Read on Sdmmc timeout");
+            // Abort the transfert.
+            hal_SdmmcStopTransfer(&g_mcdSdmmcTransfer);
+            return MCD_ERR_CARD_TIMEOUT;
+        }
+    }
+
+    // Nota: CMD12 (stop transfer) is automatically 
+    // sent by the SDMMC controller.
+ 
+    if (mcd_SdmmcReadCheckCrc() != MCD_ERR_NO)
+    {
+        printf("mcd_SdmmcMultBlockRead, crc error\n");
+        MCD_TRACE(MCD_INFO_TRC, 0, "sdc read state error");
+        return MCD_ERR;
+    }
+
+    tran_time_out = (MCD_CARD_V1 == g_mcdVer) ? MCD_TRAN_TIMEOUT_V1:MCD_TRAN_TIMEOUT_V2;
+    // Check that the card is in tran (Transmission) state.
+    if (MCD_ERR_NO != mcd_SdmmcTranState(tran_time_out))
+    // 5200000, 0, initially, that is to say rougly 0.1 sec ?
+    {
+        printf("mcd_SdmmcMultBlockRead, trans state timeout\n");
+        MCD_TRACE(MCD_INFO_TRC, 0, "Read on Sdmmc while not in Tran state");
+        return MCD_ERR_CARD_TIMEOUT;
+    } 
+    
+    // Flush Cache
+    //hal_SysInvalidateCache(pRead, blockNum * g_mcdBlockLen);
+
+    return MCD_ERR_NO;
+}
+
+// =============================================================================
+// mcd_Write
+// -----------------------------------------------------------------------------
+/// @brief Write a block of data to MMC.
+///
+/// This function is used to write blocks of data on the MMC.
+/// @param startAddr Start Adress  of the SD memory block where the
+/// data will be written
+/// @param blockWr Pointer to the block of data to write. Must be aligned 
+/// on a 32 bits boundary.
+/// @param size Number of bytes to write. Must be an interger multiple of the 
+/// sector size of the card
+// =============================================================================
+MCD_ERR_T mcd_Write(u32 startAddr, u8* blockWr, u32 size)
+{
+    //MCD_CS_ENTER;
+    u8*      tmpAdd  = NULL;
+    MCD_ERR_T   value   = MCD_ERR_NO;
+    u32 i = 0;
+    
+    //MCD_PROFILE_FUNCTION_ENTER(mcd_Write);
+    assert(g_mcdBlockLen != 0, "mcd_Write called before a successful mcd_Open");
+    assert(startAddr % g_mcdBlockLen == 0,
+        "write card address is not aligned");
+    assert((size % g_mcdBlockLen) == 0, "mcd_Write size (%d) is not a multiple of"
+                                        "the block size (%d)",
+                                        size, g_mcdBlockLen);
+
+    //printf("mcd_Write\n");
+
+    //if(!mcd_CardDetectUpdateStatus())
+    //{
+    //    MCD_PROFILE_FUNCTION_EXIT(mcd_Write);
+    //    MCD_CS_EXIT;
+    //    return MCD_ERR_NO_CARD;
+    //}
+
+    hal_SdmmcWakeUp();
+    // Addresses are block number for high capacity card
+    if (g_mcdCardIsSdhc)
+    {
+        tmpAdd = (u8*) (startAddr);
+    }
+    else
+    {
+        tmpAdd = (u8*) (startAddr * g_mcdBlockLen);
+    }
+    if(MCD_CARD_V1 == g_mcdVer)
+    {
+        //printf("mcd_Write, V1\n");
+
+        //for(i = 0; i < size/g_mcdBlockLen; i++)
+        for(i = 0; i < size>>9; i++)
+        {
+            value = mcd_SdmmcMultBlockWrite(tmpAdd + i*g_mcdBlockLen, blockWr + i*g_mcdBlockLen, 1);
+            if(value != MCD_ERR_NO)
+            {
+                break;
+            }
+        }
+    }
+    else
+    {
+        //printf("mcd_Write, V2\n");
+        //value = mcd_SdmmcMultBlockWrite(tmpAdd, blockWr, size/g_mcdBlockLen);
+        value = mcd_SdmmcMultBlockWrite(tmpAdd, blockWr, size>>9);
+    }
+
+    hal_SdmmcSleep();
+    //MCD_PROFILE_FUNCTION_EXIT(mcd_Write);
+    //MCD_CS_EXIT;
+    return value;
+}
+
+// =============================================================================
+// mcd_Read
+// -----------------------------------------------------------------------------
+/// @brief Read using pattern mode.
+/// @ param startAddr: of the SD memory block where the data
+/// will be read
+/// @param blockRd Pointer to the buffer where the data will be stored. Must be aligned 
+/// on a 32 bits boundary.
+/// @param size Number of bytes to read. Must be an interger multiple of the 
+/// sector size of the card.
+// =============================================================================
+MCD_ERR_T mcd_Read(u32 startAddr, u8* blockRd, u32 size)
+{
+    //MCD_CS_ENTER;
+    u8*      tmpAdd  = NULL;
+    MCD_ERR_T   value   = MCD_ERR_NO;
+
+    //MCD_PROFILE_FUNCTION_ENTER(mcd_Read);
+    assert(g_mcdBlockLen != 0, "mcd_Read called before a successful mcd_Open_V1 or mcd_Open_V2");
+    assert(startAddr % g_mcdBlockLen == 0,
+                "read card address is not aligned");
+    assert((size % g_mcdBlockLen) == 0, "mcd_Read size (%d) is not a multiple of"
+                                        "the block size (%d)",
+                                        size, g_mcdBlockLen);
+
+    //printf("mcd_Read\n");
+
+    //if(!mcd_CardDetectUpdateStatus())
+    //{
+    //    MCD_PROFILE_FUNCTION_EXIT(mcd_Read);
+    //    MCD_CS_EXIT;
+    //    return MCD_ERR_NO_CARD;
+    //}
+
+    hal_SdmmcWakeUp();
+    // Addresses are block number for high capacity card
+    if (g_mcdCardIsSdhc)
+    {
+        tmpAdd = (u8*) (startAddr);
+    }
+    else
+    {
+        tmpAdd = (u8*) (startAddr * g_mcdBlockLen);
+    }
+    
+    //value = mcd_SdmmcMultBlockRead(tmpAdd, blockRd, size/g_mcdBlockLen);
+    value = mcd_SdmmcMultBlockRead(tmpAdd, blockRd, size >> 9);
+
+    hal_SdmmcSleep();
+
+    //MCD_PROFILE_FUNCTION_EXIT(mcd_Read);
+    //MCD_CS_EXIT;
+    return value;
+
+}
+
+BOOL mcd_IsHighCapacityCard(void)
+{
+    if(g_mcdCardIsSdhc == TRUE)
+    {
+        return TRUE;
+    }
+    return FALSE;
+
+}
+
+static block_dev_desc_t mmc_blk_dev;
+static int initialized = 0;
+
+int mmc_set_dev(int dev_num)
+{
+	return 0;
+}
+
+block_dev_desc_t *mmc_get_dev(int dev)
+{
+	if (initialized)
+		return (block_dev_desc_t *) &mmc_blk_dev;
+	else
+		return NULL;
+}
+
+static unsigned long mmc_bread(int dev_num, unsigned long blknr,
+		lbaint_t blkcnt, void *dst)
+{
+    MCD_ERR_T mcd_ret;
+    int block_size, i;
+
+    block_size = 512;
+
+    printf("\nmmc_bread, %ld blks from %ld, dst = 0x%08lx\n",
+        (u32)blkcnt, blknr, (u32)dst);
+    for (i=0;i<blkcnt;i++) {
+        mcd_ret = mcd_Read(blknr + i, 
+            (u8 *)(dst) + i*block_size, 
+            block_size);
+        if (mcd_ret != MCD_ERR_NO) {
+            printf("Read SD card Failed\n");
+            return i;
+        }
+    }
+    printf("Done\n");
+
+	return i;
+}
+
+int mmc_legacy_init(int dev)
+{
+    MCD_ERR_T mcd_ret;
+    MCD_CSD_T mcd_csd;
+
+    mcd_ret = mcd_Open(&mcd_csd, MCD_CARD_V2);
+    if (mcd_ret != MCD_ERR_NO) {
+        printf("Open SD card Failed\n");
+        return 1;
+    }
+
+    printf("Open SD card Done\n");
+
+	mmc_blk_dev.if_type = IF_TYPE_MMC;
+	mmc_blk_dev.part_type = PART_TYPE_DOS;
+	mmc_blk_dev.dev = 0;
+	mmc_blk_dev.lun = 0;
+	mmc_blk_dev.type = 0;
+
+	/* FIXME fill in the correct size (is set to 32MByte) */
+	mmc_blk_dev.blksz = 512;
+	mmc_blk_dev.lba = 0x10000;
+	mmc_blk_dev.removable = 0;
+	mmc_blk_dev.block_read = mmc_bread;
+
+#if 0
+	if (fat_register_device(&mmc_blk_dev, 1))
+		printf("Could not register MMC fat device\n");
+#else
+	init_part(&mmc_blk_dev);
+#endif
+
+	initialized = 1;
+	return 0;
+}
+
diff --git a/drivers/mmc/s5p_mmc.c b/drivers/mmc/s5p_mmc.c
deleted file mode 100644
index 4ae3aaf773..0000000000
--- a/drivers/mmc/s5p_mmc.c
+++ /dev/null
@@ -1,490 +0,0 @@
-/*
- * (C) Copyright 2009 SAMSUNG Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Jaehoon Chung <jh80.chung@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <common.h>
-#include <mmc.h>
-#include <asm/io.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/clk.h>
-
-/* support 4 mmc hosts */
-struct mmc mmc_dev[4];
-struct mmc_host mmc_host[4];
-
-static inline struct s5p_mmc *s5p_get_base_mmc(int dev_index)
-{
-	unsigned long offset = dev_index * sizeof(struct s5p_mmc);
-	return (struct s5p_mmc *)(samsung_get_base_mmc() + offset);
-}
-
-static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
-{
-	unsigned char ctrl;
-
-	debug("data->dest: %08x\n", (u32)data->dest);
-	writel((u32)data->dest, &host->reg->sysad);
-	/*
-	 * DMASEL[4:3]
-	 * 00 = Selects SDMA
-	 * 01 = Reserved
-	 * 10 = Selects 32-bit Address ADMA2
-	 * 11 = Selects 64-bit Address ADMA2
-	 */
-	ctrl = readb(&host->reg->hostctl);
-	ctrl &= ~(3 << 3);
-	writeb(ctrl, &host->reg->hostctl);
-
-	/* We do not handle DMA boundaries, so set it to max (512 KiB) */
-	writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize);
-	writew(data->blocks, &host->reg->blkcnt);
-}
-
-static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
-{
-	unsigned short mode;
-
-	/*
-	 * TRNMOD
-	 * MUL1SIN0[5]	: Multi/Single Block Select
-	 * RD1WT0[4]	: Data Transfer Direction Select
-	 *	1 = read
-	 *	0 = write
-	 * ENACMD12[2]	: Auto CMD12 Enable
-	 * ENBLKCNT[1]	: Block Count Enable
-	 * ENDMA[0]	: DMA Enable
-	 */
-	mode = (1 << 1) | (1 << 0);
-	if (data->blocks > 1)
-		mode |= (1 << 5);
-	if (data->flags & MMC_DATA_READ)
-		mode |= (1 << 4);
-
-	writew(mode, &host->reg->trnmod);
-}
-
-static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
-			struct mmc_data *data)
-{
-	struct mmc_host *host = (struct mmc_host *)mmc->priv;
-	int flags, i;
-	unsigned int timeout;
-	unsigned int mask;
-	unsigned int retry = 0x100000;
-
-	/* Wait max 10 ms */
-	timeout = 10;
-
-	/*
-	 * PRNSTS
-	 * CMDINHDAT[1]	: Command Inhibit (DAT)
-	 * CMDINHCMD[0]	: Command Inhibit (CMD)
-	 */
-	mask = (1 << 0);
-	if ((data != NULL) || (cmd->resp_type & MMC_RSP_BUSY))
-		mask |= (1 << 1);
-
-	/*
-	 * We shouldn't wait for data inihibit for stop commands, even
-	 * though they might use busy signaling
-	 */
-	if (data)
-		mask &= ~(1 << 1);
-
-	while (readl(&host->reg->prnsts) & mask) {
-		if (timeout == 0) {
-			printf("%s: timeout error\n", __func__);
-			return -1;
-		}
-		timeout--;
-		udelay(1000);
-	}
-
-	if (data)
-		mmc_prepare_data(host, data);
-
-	debug("cmd->arg: %08x\n", cmd->cmdarg);
-	writel(cmd->cmdarg, &host->reg->argument);
-
-	if (data)
-		mmc_set_transfer_mode(host, data);
-
-	if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
-		return -1;
-
-	/*
-	 * CMDREG
-	 * CMDIDX[13:8]	: Command index
-	 * DATAPRNT[5]	: Data Present Select
-	 * ENCMDIDX[4]	: Command Index Check Enable
-	 * ENCMDCRC[3]	: Command CRC Check Enable
-	 * RSPTYP[1:0]
-	 *	00 = No Response
-	 *	01 = Length 136
-	 *	10 = Length 48
-	 *	11 = Length 48 Check busy after response
-	 */
-	if (!(cmd->resp_type & MMC_RSP_PRESENT))
-		flags = 0;
-	else if (cmd->resp_type & MMC_RSP_136)
-		flags = (1 << 0);
-	else if (cmd->resp_type & MMC_RSP_BUSY)
-		flags = (3 << 0);
-	else
-		flags = (2 << 0);
-
-	if (cmd->resp_type & MMC_RSP_CRC)
-		flags |= (1 << 3);
-	if (cmd->resp_type & MMC_RSP_OPCODE)
-		flags |= (1 << 4);
-	if (data)
-		flags |= (1 << 5);
-
-	debug("cmd: %d\n", cmd->cmdidx);
-
-	writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
-
-	for (i = 0; i < retry; i++) {
-		mask = readl(&host->reg->norintsts);
-		/* Command Complete */
-		if (mask & (1 << 0)) {
-			if (!data)
-				writel(mask, &host->reg->norintsts);
-			break;
-		}
-	}
-
-	if (i == retry) {
-		printf("%s: waiting for status update\n", __func__);
-		return TIMEOUT;
-	}
-
-	if (mask & (1 << 16)) {
-		/* Timeout Error */
-		debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
-		return TIMEOUT;
-	} else if (mask & (1 << 15)) {
-		/* Error Interrupt */
-		debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
-		return -1;
-	}
-
-	if (cmd->resp_type & MMC_RSP_PRESENT) {
-		if (cmd->resp_type & MMC_RSP_136) {
-			/* CRC is stripped so we need to do some shifting. */
-			for (i = 0; i < 4; i++) {
-				unsigned int offset =
-					(unsigned int)(&host->reg->rspreg3 - i);
-				cmd->response[i] = readl(offset) << 8;
-
-				if (i != 3) {
-					cmd->response[i] |=
-						readb(offset - 1);
-				}
-				debug("cmd->resp[%d]: %08x\n",
-						i, cmd->response[i]);
-			}
-		} else if (cmd->resp_type & MMC_RSP_BUSY) {
-			for (i = 0; i < retry; i++) {
-				/* PRNTDATA[23:20] : DAT[3:0] Line Signal */
-				if (readl(&host->reg->prnsts)
-					& (1 << 20))	/* DAT[0] */
-					break;
-			}
-
-			if (i == retry) {
-				printf("%s: card is still busy\n", __func__);
-				return TIMEOUT;
-			}
-
-			cmd->response[0] = readl(&host->reg->rspreg0);
-			debug("cmd->resp[0]: %08x\n", cmd->response[0]);
-		} else {
-			cmd->response[0] = readl(&host->reg->rspreg0);
-			debug("cmd->resp[0]: %08x\n", cmd->response[0]);
-		}
-	}
-
-	if (data) {
-		while (1) {
-			mask = readl(&host->reg->norintsts);
-
-			if (mask & (1 << 15)) {
-				/* Error Interrupt */
-				writel(mask, &host->reg->norintsts);
-				printf("%s: error during transfer: 0x%08x\n",
-						__func__, mask);
-				return -1;
-			} else if (mask & (1 << 3)) {
-				/*
-				 * DMA Interrupt, restart the transfer where
-				 * it was interrupted.
-				 */
-				unsigned int address = readl(&host->reg->sysad);
-
-				debug("DMA end\n");
-				writel((1 << 3), &host->reg->norintsts);
-				writel(address, &host->reg->sysad);
-			} else if (mask & (1 << 1)) {
-				/* Transfer Complete */
-				debug("r/w is done\n");
-				break;
-			}
-		}
-		writel(mask, &host->reg->norintsts);
-	}
-
-	udelay(1000);
-	return 0;
-}
-
-static void mmc_change_clock(struct mmc_host *host, uint clock)
-{
-	int div;
-	unsigned short clk;
-	unsigned long timeout;
-	unsigned long ctrl2;
-
-	/*
-	 * SELBASECLK[5:4]
-	 * 00/01 = HCLK
-	 * 10 = EPLL
-	 * 11 = XTI or XEXTCLK
-	 */
-	ctrl2 = readl(&host->reg->control2);
-	ctrl2 &= ~(3 << 4);
-	ctrl2 |= (2 << 4);
-	writel(ctrl2, &host->reg->control2);
-
-	writew(0, &host->reg->clkcon);
-
-	/* XXX: we assume that clock is between 40MHz and 50MHz */
-	if (clock == 0)
-		goto out;
-	else if (clock <= 400000)
-		div = 0x100;
-	else if (clock <= 20000000)
-		div = 4;
-	else if (clock <= 26000000)
-		div = 2;
-	else
-		div = 1;
-	debug("div: %d\n", div);
-
-	div >>= 1;
-	/*
-	 * CLKCON
-	 * SELFREQ[15:8]	: base clock divied by value
-	 * ENSDCLK[2]		: SD Clock Enable
-	 * STBLINTCLK[1]	: Internal Clock Stable
-	 * ENINTCLK[0]		: Internal Clock Enable
-	 */
-	clk = (div << 8) | (1 << 0);
-	writew(clk, &host->reg->clkcon);
-
-	set_mmc_clk(host->dev_index, div);
-
-	/* Wait max 10 ms */
-	timeout = 10;
-	while (!(readw(&host->reg->clkcon) & (1 << 1))) {
-		if (timeout == 0) {
-			printf("%s: timeout error\n", __func__);
-			return;
-		}
-		timeout--;
-		udelay(1000);
-	}
-
-	clk |= (1 << 2);
-	writew(clk, &host->reg->clkcon);
-
-out:
-	host->clock = clock;
-}
-
-static void mmc_set_ios(struct mmc *mmc)
-{
-	struct mmc_host *host = mmc->priv;
-	unsigned char ctrl;
-	unsigned long val;
-
-	debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
-
-	/*
-	 * SELCLKPADDS[17:16]
-	 * 00 = 2mA
-	 * 01 = 4mA
-	 * 10 = 7mA
-	 * 11 = 9mA
-	 */
-	writel(0x3 << 16, &host->reg->control4);
-
-	val = readl(&host->reg->control2);
-	val &= (0x3 << 4);
-
-	val |=	(1 << 31) |	/* write status clear async mode enable */
-		(1 << 30) |	/* command conflict mask enable */
-		(1 << 14) |	/* Feedback Clock Enable for Rx Clock */
-		(1 << 8);	/* SDCLK hold enable */
-
-	writel(val, &host->reg->control2);
-
-	/*
-	 * FCSEL1[15] FCSEL0[7]
-	 * FCSel[1:0] : Rx Feedback Clock Delay Control
-	 *	Inverter delay means10ns delay if SDCLK 50MHz setting
-	 *	01 = Delay1 (basic delay)
-	 *	11 = Delay2 (basic delay + 2ns)
-	 *	00 = Delay3 (inverter delay)
-	 *	10 = Delay4 (inverter delay + 2ns)
-	 */
-	writel(0x8080, &host->reg->control3);
-
-	mmc_change_clock(host, mmc->clock);
-
-	ctrl = readb(&host->reg->hostctl);
-
-	/*
-	 * WIDE8[5]
-	 * 0 = Depend on WIDE4
-	 * 1 = 8-bit mode
-	 * WIDE4[1]
-	 * 1 = 4-bit mode
-	 * 0 = 1-bit mode
-	 */
-	if (mmc->bus_width == 8)
-		ctrl |= (1 << 5);
-	else if (mmc->bus_width == 4)
-		ctrl |= (1 << 1);
-	else
-		ctrl &= ~(1 << 1);
-
-	/*
-	 * OUTEDGEINV[2]
-	 * 1 = Riging edge output
-	 * 0 = Falling edge output
-	 */
-	ctrl &= ~(1 << 2);
-
-	writeb(ctrl, &host->reg->hostctl);
-}
-
-static void mmc_reset(struct mmc_host *host)
-{
-	unsigned int timeout;
-
-	/*
-	 * RSTALL[0] : Software reset for all
-	 * 1 = reset
-	 * 0 = work
-	 */
-	writeb((1 << 0), &host->reg->swrst);
-
-	host->clock = 0;
-
-	/* Wait max 100 ms */
-	timeout = 100;
-
-	/* hw clears the bit when it's done */
-	while (readb(&host->reg->swrst) & (1 << 0)) {
-		if (timeout == 0) {
-			printf("%s: timeout error\n", __func__);
-			return;
-		}
-		timeout--;
-		udelay(1000);
-	}
-}
-
-static int mmc_core_init(struct mmc *mmc)
-{
-	struct mmc_host *host = (struct mmc_host *)mmc->priv;
-	unsigned int mask;
-
-	mmc_reset(host);
-
-	host->version = readw(&host->reg->hcver);
-
-	/* mask all */
-	writel(0xffffffff, &host->reg->norintstsen);
-	writel(0xffffffff, &host->reg->norintsigen);
-
-	writeb(0xe, &host->reg->timeoutcon);	/* TMCLK * 2^27 */
-
-	/*
-	 * NORMAL Interrupt Status Enable Register init
-	 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
-	 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
-	 * [3] ENSTADMAINT : DMA Interrupt Status Enable
-	 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
-	 * [0] ENSTACMDCMPLT : Command Complete Status Enable
-	 */
-	mask = readl(&host->reg->norintstsen);
-	mask &= ~(0xffff);
-	mask |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 1) | (1 << 0);
-	writel(mask, &host->reg->norintstsen);
-
-	/*
-	 * NORMAL Interrupt Signal Enable Register init
-	 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
-	 */
-	mask = readl(&host->reg->norintsigen);
-	mask &= ~(0xffff);
-	mask |= (1 << 1);
-	writel(mask, &host->reg->norintsigen);
-
-	return 0;
-}
-
-static int s5p_mmc_initialize(int dev_index, int bus_width)
-{
-	struct mmc *mmc;
-
-	mmc = &mmc_dev[dev_index];
-
-	sprintf(mmc->name, "SAMSUNG SD/MMC");
-	mmc->priv = &mmc_host[dev_index];
-	mmc->send_cmd = mmc_send_cmd;
-	mmc->set_ios = mmc_set_ios;
-	mmc->init = mmc_core_init;
-	mmc->getcd = NULL;
-
-	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
-	if (bus_width == 8)
-		mmc->host_caps = MMC_MODE_8BIT;
-	else
-		mmc->host_caps = MMC_MODE_4BIT;
-	mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
-
-	mmc->f_min = 400000;
-	mmc->f_max = 52000000;
-
-	mmc_host[dev_index].dev_index = dev_index;
-	mmc_host[dev_index].clock = 0;
-	mmc_host[dev_index].reg = s5p_get_base_mmc(dev_index);
-	mmc->b_max = 0;
-	mmc_register(mmc);
-
-	return 0;
-}
-
-int s5p_mmc_init(int dev_index, int bus_width)
-{
-	return s5p_mmc_initialize(dev_index, bus_width);
-}
diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c
new file mode 100644
index 0000000000..1d4481b974
--- /dev/null
+++ b/drivers/mmc/s5p_sdhci.c
@@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * Jaehoon Chung <jh80.chung@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <sdhci.h>
+#include <asm/arch/mmc.h>
+
+static char *S5P_NAME = "SAMSUNG SDHCI";
+static void s5p_sdhci_set_control_reg(struct sdhci_host *host)
+{
+	unsigned long val, ctrl;
+	/*
+	 * SELCLKPADDS[17:16]
+	 * 00 = 2mA
+	 * 01 = 4mA
+	 * 10 = 7mA
+	 * 11 = 9mA
+	 */
+	sdhci_writel(host, SDHCI_CTRL4_DRIVE_MASK(0x3), SDHCI_CONTROL4);
+
+	val = sdhci_readl(host, SDHCI_CONTROL2);
+	val &= SDHCI_CTRL2_SELBASECLK_SHIFT;
+
+	val |=	SDHCI_CTRL2_ENSTAASYNCCLR |
+		SDHCI_CTRL2_ENCMDCNFMSK |
+		SDHCI_CTRL2_ENFBCLKRX |
+		SDHCI_CTRL2_ENCLKOUTHOLD;
+
+	sdhci_writel(host, val, SDHCI_CONTROL2);
+
+	/*
+	 * FCSEL3[31] FCSEL2[23] FCSEL1[15] FCSEL0[7]
+	 * FCSel[1:0] : Rx Feedback Clock Delay Control
+	 *	Inverter delay means10ns delay if SDCLK 50MHz setting
+	 *	01 = Delay1 (basic delay)
+	 *	11 = Delay2 (basic delay + 2ns)
+	 *	00 = Delay3 (inverter delay)
+	 *	10 = Delay4 (inverter delay + 2ns)
+	 */
+	val = SDHCI_CTRL3_FCSEL3 | SDHCI_CTRL3_FCSEL1;
+	sdhci_writel(host, val, SDHCI_CONTROL3);
+
+	/*
+	 * SELBASECLK[5:4]
+	 * 00/01 = HCLK
+	 * 10 = EPLL
+	 * 11 = XTI or XEXTCLK
+	 */
+	ctrl = sdhci_readl(host, SDHCI_CONTROL2);
+	ctrl &= ~SDHCI_CTRL2_SELBASECLK_MASK(0x3);
+	ctrl |= SDHCI_CTRL2_SELBASECLK_MASK(0x2);
+	sdhci_writel(host, ctrl, SDHCI_CONTROL2);
+}
+
+int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks)
+{
+	struct sdhci_host *host = NULL;
+	host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
+	if (!host) {
+		printf("sdhci__host malloc fail!\n");
+		return 1;
+	}
+
+	host->name = S5P_NAME;
+	host->ioaddr = (void *)regbase;
+	host->quirks = quirks;
+
+	host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE;
+	host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+	if (quirks & SDHCI_QUIRK_REG32_RW)
+		host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
+	else
+		host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+
+	host->set_control_reg = &s5p_sdhci_set_control_reg;
+
+	host->host_caps = MMC_MODE_HC;
+
+	add_sdhci(host, max_clk, min_clk);
+	return 0;
+}
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index fc904b5308..1709643da8 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -128,6 +128,7 @@ int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 	int trans_bytes = 0, is_aligned = 1;
 	u32 mask, flags, mode;
 	unsigned int timeout, start_addr = 0;
+	unsigned int retry = 10000;
 
 	/* Wait max 10 ms */
 	timeout = 10;
@@ -210,8 +211,19 @@ int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 		stat = sdhci_readl(host, SDHCI_INT_STATUS);
 		if (stat & SDHCI_INT_ERROR)
 			break;
+		if (--retry == 0)
+			break;
 	} while ((stat & mask) != mask);
 
+	if (retry == 0) {
+		if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
+			return 0;
+		else {
+			printf("Timeout for status update!\n");
+			return TIMEOUT;
+		}
+	}
+
 	if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
 		sdhci_cmd_done(host, cmd);
 		sdhci_writel(host, mask, SDHCI_INT_STATUS);
@@ -325,6 +337,9 @@ void sdhci_set_ios(struct mmc *mmc)
 	u32 ctrl;
 	struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
 
+	if (host->set_control_reg)
+		host->set_control_reg(host);
+
 	if (mmc->clock != host->clock)
 		sdhci_set_clock(mmc, mmc->clock);
 
@@ -348,6 +363,9 @@ void sdhci_set_ios(struct mmc *mmc)
 	else
 		ctrl &= ~SDHCI_CTRL_HISPD;
 
+	if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
+		ctrl &= ~SDHCI_CTRL_HISPD;
+
 	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 }
 
@@ -431,9 +449,15 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
 		mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 	if (caps & SDHCI_CAN_VDD_180)
 		mmc->voltages |= MMC_VDD_165_195;
+
+	if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
+		mmc->voltages |= host->voltages;
+
 	mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
 	if (caps & SDHCI_CAN_DO_8BIT)
 		mmc->host_caps |= MMC_MODE_8BIT;
+	if (host->host_caps)
+		mmc->host_caps |= host->host_caps;
 
 	sdhci_reset(host, SDHCI_RESET_ALL);
 	mmc_register(mmc);
diff --git a/drivers/mtd/mtdconcat.c b/drivers/mtd/mtdconcat.c
index fc2270127a..a4b8728cde 100644
--- a/drivers/mtd/mtdconcat.c
+++ b/drivers/mtd/mtdconcat.c
@@ -9,7 +9,7 @@
  */
 
 #include <linux/mtd/mtd.h>
-#include <linux/mtd/compat.h>
+#include <linux/compat.h>
 #include <linux/mtd/concat.h>
 #include <ubi_uboot.h>
 
@@ -289,6 +289,7 @@ static int concat_dev_erase(struct mtd_info *mtd, struct erase_info *erase)
 static int concat_erase(struct mtd_info *mtd, struct erase_info *instr)
 {
 	struct mtd_concat *concat = CONCAT(mtd);
+	struct nand_chip *chip = concat->mtd.priv;
 	struct mtd_info *subdev;
 	int i, err;
 	uint64_t length, offset = 0;
@@ -311,10 +312,19 @@ static int concat_erase(struct mtd_info *mtd, struct erase_info *instr)
 	 */
 	if (!concat->mtd.numeraseregions) {
 		/* the easy case: device has uniform erase block size */
-		if (instr->addr & (concat->mtd.erasesize - 1))
-			return -EINVAL;
-		if (instr->len & (concat->mtd.erasesize - 1))
-			return -EINVAL;
+		if (chip->phys_erase_shift == 0) {
+			if(mtd_mod_by_eb(instr->addr,  &concat->mtd))
+				return -EINVAL;
+
+			if (mtd_mod_by_eb(instr->len, &concat->mtd))
+				return -EINVAL;
+		} else {
+			if (instr->addr & (concat->mtd.erasesize - 1))
+				return -EINVAL;
+
+			if (instr->len & (concat->mtd.erasesize - 1))
+				return -EINVAL;
+		}
 	} else {
 		/* device has variable erase size */
 		struct mtd_erase_region_info *erase_regions =
@@ -332,8 +342,13 @@ static int concat_erase(struct mtd_info *mtd, struct erase_info *instr)
 		 * to-be-erased area begins. Verify that the starting
 		 * offset is aligned to this region's erase size:
 		 */
-		if (instr->addr & (erase_regions[i].erasesize - 1))
-			return -EINVAL;
+		if (is_power_of_2(erase_regions[i].erasesize)){
+			if (instr->addr & (erase_regions[i].erasesize - 1))
+				return -EINVAL;
+		} else {
+			if (mtd_mod_by_var(instr->addr, erase_regions[i].erasesize))
+				return -EINVAL;
+		}
 
 		/*
 		 * now find the erase region where the to-be-erased area ends:
@@ -345,9 +360,13 @@ static int concat_erase(struct mtd_info *mtd, struct erase_info *instr)
 		/*
 		 * check if the ending offset is aligned to this region's erase size
 		 */
-		if ((instr->addr + instr->len) & (erase_regions[i].erasesize -
-						  1))
-			return -EINVAL;
+		if (is_power_of_2(erase_regions[i].erasesize)){
+			if ((instr->addr + instr->len) & (erase_regions[i].erasesize - 1))
+				return -EINVAL;
+		} else {
+			if (mtd_mod_by_var((instr->addr + instr->len), erase_regions[i].erasesize))
+				return -EINVAL;
+		}
 	}
 
 	instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c
index a195ddab35..fb35596175 100644
--- a/drivers/mtd/mtdcore.c
+++ b/drivers/mtd/mtdcore.c
@@ -8,7 +8,7 @@
  */
 
 #include <linux/mtd/mtd.h>
-#include <linux/mtd/compat.h>
+#include <linux/compat.h>
 #include <ubi_uboot.h>
 
 struct mtd_info *mtd_table[MAX_MTD_DEVICES];
@@ -161,6 +161,7 @@ void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t offset,
 {
 	*truncated = 0;
 	*len_incl_bad = 0;
+	struct nand_chip *chip = mtd->priv;
 
 	if (!mtd->block_isbad) {
 		*len_incl_bad = length;
@@ -176,10 +177,17 @@ void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t offset,
 			return;
 		}
 
-		block_len = mtd->erasesize - (offset & (mtd->erasesize - 1));
+		if (chip->phys_erase_shift == 0){
+			block_len = mtd->erasesize - mtd_mod_by_eb(offset, mtd);
 
-		if (!mtd->block_isbad(mtd, offset & ~(mtd->erasesize - 1)))
-			len_excl_bad += block_len;
+			if (!mtd->block_isbad(mtd, mtd_div_by_eb(offset, mtd)*mtd->erasesize))
+				len_excl_bad += block_len;
+		} else {
+			block_len = mtd->erasesize - (offset & (mtd->erasesize - 1));
+
+			if (!mtd->block_isbad(mtd, offset & ~(mtd->erasesize - 1)))
+				len_excl_bad += block_len;
+		}
 
 		*len_incl_bad += block_len;
 		offset       += block_len;
diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c
index f647e43668..96dcda2b2b 100644
--- a/drivers/mtd/mtdpart.c
+++ b/drivers/mtd/mtdpart.c
@@ -17,7 +17,7 @@
 #include <linux/list.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
-#include <linux/mtd/compat.h>
+#include <linux/compat.h>
 
 /* Our partition linked list */
 struct list_head mtd_partitions;
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 1d1b628651..b9e683cdcb 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -63,6 +63,7 @@ COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
 COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o
 COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
 COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
+COBJS-$(CONFIG_NAND_RDA) += rda_nand.o rda_spi_nand.o rda_nand_base.o
 endif
 
 COBJS	:= $(COBJS-y)
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 5cac78b296..b3b7c705e1 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -384,19 +384,30 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 
 	/* READID must read all possible bytes while CEB is active */
 	case NAND_CMD_READID:
+	case NAND_CMD_PARAM: {
+		int timing = IFC_FIR_OP_RB;
+		if (command == NAND_CMD_PARAM)
+			timing = IFC_FIR_OP_RBCD;
+
 		out_be32(&ifc->ifc_nand.nand_fir0,
 				(IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) |
 				(IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
-				(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
+				(timing << IFC_NAND_FIR0_OP2_SHIFT));
 		out_be32(&ifc->ifc_nand.nand_fcr0,
-				NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
-		/* 4 bytes for manuf, device and exts */
-		out_be32(&ifc->ifc_nand.nand_fbcr, 4);
-		ctrl->read_bytes = 4;
+				command << IFC_NAND_FCR0_CMD0_SHIFT);
+		out_be32(&ifc->ifc_nand.row3, column);
+
+		/*
+		 * although currently it's 8 bytes for READID, we always read
+		 * the maximum 256 bytes(for PARAM)
+		 */
+		out_be32(&ifc->ifc_nand.nand_fbcr, 256);
+		ctrl->read_bytes = 256;
 
 		set_addr(mtd, 0, 0, 0);
 		fsl_ifc_run_command(mtd);
 		return;
+	}
 
 	/* ERASE1 stores the block and page address */
 	case NAND_CMD_ERASE1:
@@ -764,6 +775,7 @@ int board_nand_init(struct nand_chip *nand)
 	if (priv->bank >= MAX_BANKS) {
 		printf("%s: address did not match any "
 		       "chip selects\n", __func__);
+		kfree(priv);
 		return -ENODEV;
 	}
 
diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c
index 7fd8a35479..e6b7a70661 100644
--- a/drivers/mtd/nand/mpc5121_nfc.c
+++ b/drivers/mtd/nand/mpc5121_nfc.c
@@ -29,7 +29,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/nand_ecc.h>
-#include <linux/mtd/compat.h>
+#include <linux/compat.h>
 
 #include <asm/errno.h>
 #include <asm/io.h>
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 35e89a0f4d..936186f75e 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -1302,12 +1302,45 @@ static void mxc_setup_config1(void)
 #define mxc_setup_config1()
 #endif
 
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
+
+static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
+static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
+
+static struct nand_bbt_descr bbt_main_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+		   NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+	.offs =	0,
+	.len = 4,
+	.veroffs = 4,
+	.maxblocks = 4,
+	.pattern = bbt_pattern,
+};
+
+static struct nand_bbt_descr bbt_mirror_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+		   NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+	.offs =	0,
+	.len = 4,
+	.veroffs = 4,
+	.maxblocks = 4,
+	.pattern = mirror_pattern,
+};
+
+#endif
+
 int board_nand_init(struct nand_chip *this)
 {
 	struct mtd_info *mtd;
 	uint16_t tmp;
 	int err = 0;
 
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
+	this->options |= NAND_USE_FLASH_BBT;
+	this->bbt_td = &bbt_main_descr;
+	this->bbt_md = &bbt_mirror_descr;
+#endif
+
 	/* structures must be linked */
 	mtd = &host->mtd;
 	mtd->priv = this;
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 44f7b91457..d293f71d3f 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -39,7 +39,7 @@
 #include <malloc.h>
 #include <watchdog.h>
 #include <linux/err.h>
-#include <linux/mtd/compat.h>
+#include <linux/compat.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/nand_ecc.h>
@@ -79,7 +79,7 @@ static struct nand_ecclayout nand_oob_16 = {
 	.eccpos = {0, 1, 2, 3, 6, 7},
 	.oobfree = {
 		{.offset = 8,
-		 . length = 8} }
+		 .length = 8} }
 };
 
 static struct nand_ecclayout nand_oob_64 = {
@@ -122,16 +122,31 @@ static int check_offs_len(struct mtd_info *mtd,
 	int ret = 0;
 
 	/* Start address must align on block boundary */
-	if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
-		MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
-		ret = -EINVAL;
+	if (chip->phys_erase_shift == 0) {
+		if (mtd_mod_by_eb(ofs, mtd)) {
+			MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
+			ret = -EINVAL;
+		}
+	} else {
+		if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
+			MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
+			ret = -EINVAL;
+		}
 	}
 
 	/* Length must align on block boundary */
-	if (len & ((1 << chip->phys_erase_shift) - 1)) {
-		MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
+	if (chip->phys_erase_shift == 0) {
+		if (mtd_mod_by_eb(len, mtd)) {
+			MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
 					__func__);
-		ret = -EINVAL;
+			ret = -EINVAL;
+		}
+	} else {
+		if (len & ((1 << chip->phys_erase_shift) - 1)) {
+			MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
+					__func__);
+			ret = -EINVAL;
+		}
 	}
 
 	/* Do not allow past end of device */
@@ -350,10 +365,16 @@ static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 	if (chip->options & NAND_BBT_SCANLASTPAGE)
 		ofs += mtd->erasesize - mtd->writesize;
 
-	page = (int)(ofs >> chip->page_shift) & chip->pagemask;
+	if ( chip->page_shift == 0)
+		page = mtd_div_by_ws(ofs, mtd) & chip->pagemask;
+	else
+		page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 
 	if (getchip) {
-		chipnr = (int)(ofs >> chip->chip_shift);
+		if (chip->chip_shift == 0)
+			chipnr = mtd_div_by_cs(ofs, mtd);
+		else
+			chipnr = (int)(ofs >> chip->chip_shift);
 
 		nand_get_device(chip, mtd, FL_READING);
 
@@ -403,7 +424,11 @@ static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 		ofs += mtd->erasesize - mtd->writesize;
 
 	/* Get block number */
-	block = (int)(ofs >> chip->bbt_erase_shift);
+	if (chip->bbt_erase_shift == 0)
+		block = mtd_div_by_eb(ofs, mtd);
+	else
+		block = (int)(ofs >> chip->bbt_erase_shift);
+
 	if (chip->bbt)
 		chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 
@@ -1200,10 +1225,9 @@ static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
 			    struct mtd_oob_ops *ops)
 {
-	int chipnr, page, realpage, col, bytes, aligned;
+	int chipnr, page, realpage, col, bytes, aligned, blkcheck;
 	struct nand_chip *chip = mtd->priv;
 	struct mtd_ecc_stats stats;
-	int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
 	int sndcmd = 1;
 	int ret = 0;
 	uint32_t readlen = ops->len;
@@ -1213,15 +1237,30 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
 
 	uint8_t *bufpoi, *oob, *buf;
 
+	if (chip->phys_erase_shift == 0 || chip->page_shift == 0)
+		blkcheck = mtd_div_by_ws(mtd->erasesize, mtd) - 1;
+	else
+		blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
+
 	stats = mtd->ecc_stats;
+	if (chip->chip_shift == 0)
+		chipnr = mtd_div_by_cs(from, mtd);
+	else
+		chipnr = (int)(from >> chip->chip_shift);
 
-	chipnr = (int)(from >> chip->chip_shift);
 	chip->select_chip(mtd, chipnr);
 
-	realpage = (int)(from >> chip->page_shift);
+	if (chip->page_shift == 0)
+		realpage = mtd_div_by_ws(from, mtd);
+	else
+		realpage = (int)(from >> chip->page_shift);
+
 	page = realpage & chip->pagemask;
 
-	col = (int)(from & (mtd->writesize - 1));
+	if (chip->page_shift == 0)
+		col = mtd_mod_by_ws(from, mtd);
+	else
+		col = (int)(from & (mtd->writesize - 1));
 
 	buf = ops->datbuf;
 	oob = ops->oobbuf;
@@ -1518,13 +1557,18 @@ static int nand_write_oob_syndrome(struct mtd_info *mtd,
 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
 			    struct mtd_oob_ops *ops)
 {
-	int page, realpage, chipnr, sndcmd = 1;
+	int page, realpage, chipnr, sndcmd = 1, blkcheck;
 	struct nand_chip *chip = mtd->priv;
-	int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
+
 	int readlen = ops->ooblen;
 	int len;
 	uint8_t *buf = ops->oobbuf;
 
+	if (chip->phys_erase_shift == 0 ||chip->page_shift == 0)
+		blkcheck = (mtd->erasesize / mtd->writesize) - 1;
+	else
+		blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
+
 	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
 			__func__, (unsigned long long)from, readlen);
 
@@ -1539,20 +1583,38 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
 		return -EINVAL;
 	}
 
-	/* Do not allow reads past end of device */
-	if (unlikely(from >= mtd->size ||
+	if (chip->page_shift == 0 || chip->chip_shift == 0) {
+		/* Do not allow reads past end of device */
+		if (unlikely(from >= mtd->size ||
+		     ops->ooboffs + readlen > (mtd_div_by_ws(mtd->size, mtd) -
+		    							mtd_div_by_ws(from, mtd)) * len)) {
+			MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
+					"of device\n", __func__);
+			return -EINVAL;
+		}
+
+		chipnr = mtd_div_by_cs(from, mtd);
+		chip->select_chip(mtd, chipnr);
+
+		/* Shift to get page */
+		realpage = mtd_div_by_ws(from, mtd);
+	} else {
+		/* Do not allow reads past end of device */
+		if (unlikely(from >= mtd->size ||
 		     ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
 					(from >> chip->page_shift)) * len)) {
-		MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
+			MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
 					"of device\n", __func__);
-		return -EINVAL;
-	}
+			return -EINVAL;
+		}
 
-	chipnr = (int)(from >> chip->chip_shift);
-	chip->select_chip(mtd, chipnr);
+		chipnr = (int)(from >> chip->chip_shift);
+		chip->select_chip(mtd, chipnr);
+
+		/* Shift to get page */
+		realpage = (int)(from >> chip->page_shift);
+	}
 
-	/* Shift to get page */
-	realpage = (int)(from >> chip->page_shift);
 	page = realpage & chip->pagemask;
 
 	while (1) {
@@ -1903,7 +1965,7 @@ static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
 	return NULL;
 }
 
-#define NOTALIGNED(x)	((x & (chip->subpagesize - 1)) != 0)
+#define NOTALIGNED(x)	((x  % chip->subpagesize) != 0)
 
 /**
  * nand_do_write_ops - [Internal] NAND write with ECC
@@ -1932,13 +1994,22 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
 	if (!writelen)
 		return 0;
 
-	column = to & (mtd->writesize - 1);
-	subpage = column || (writelen & (mtd->writesize - 1));
+	if (chip->page_shift == 0) {
+		column = mtd_mod_by_ws(to, mtd);
+		subpage = column || mtd_mod_by_ws(writelen, mtd);
+	} else {
+		column = to & (mtd->writesize - 1);
+		subpage = column || (writelen & (mtd->writesize - 1));
+	}
 
 	if (subpage && oob)
 		return -EINVAL;
 
-	chipnr = (int)(to >> chip->chip_shift);
+	if (chip->chip_shift == 0)
+		chipnr = mtd_div_by_cs(to, mtd);
+	else
+		chipnr = (int)(to >> chip->chip_shift);
+
 	chip->select_chip(mtd, chipnr);
 
 	/* Check, if it is write protected */
@@ -1947,14 +2018,25 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
 		return -EIO;
 	}
 
-	realpage = (int)(to >> chip->page_shift);
-	page = realpage & chip->pagemask;
-	blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
+	if (chip->page_shift == 0 || chip->phys_erase_shift == 0) {
+		realpage = mtd_div_by_ws(to, mtd);
+		page = realpage & chip->pagemask;
+		blockmask = mtd->erasesize / mtd->writesize - 1;
 
-	/* Invalidate the page cache, when we write to the cached page */
-	if (to <= (chip->pagebuf << chip->page_shift) &&
-	    (chip->pagebuf << chip->page_shift) < (to + ops->len))
-		chip->pagebuf = -1;
+		/* Invalidate the page cache, when we write to the cached page */
+		if (to <= chip->pagebuf * mtd->writesize &&
+			chip->pagebuf *mtd->writesize < (to + ops->len))
+			chip->pagebuf = -1;
+	} else {
+		realpage = (int)(to >> chip->page_shift);
+		page = realpage & chip->pagemask;
+		blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
+
+		/* Invalidate the page cache, when we write to the cached page */
+		if (to <= (chip->pagebuf << chip->page_shift) &&
+	    		(chip->pagebuf << chip->page_shift) < (to + ops->len))
+			chip->pagebuf = -1;
+	}
 
 	/* If we're not given explicit OOB data, let it be 0xFF */
 	if (likely(!oob))
@@ -2087,21 +2169,39 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 		return -EINVAL;
 	}
 
-	/* Do not allow write past end of device */
-	if (unlikely(to >= mtd->size ||
+	if (chip->page_shift == 0 ||chip->chip_shift == 0) {
+		/* Do not allow write past end of device */
+		if (unlikely(to >= mtd->size ||
+		     ops->ooboffs + ops->ooblen >
+			 (mtd_div_by_ws(mtd->size, mtd) -
+			 mtd_div_by_ws(to, mtd)) * len)) {
+			MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
+				"end of device\n", __func__);
+			return -EINVAL;
+		}
+
+		chipnr = mtd_div_by_cs(to, mtd);
+		chip->select_chip(mtd, chipnr);
+
+		/* Shift to get page */
+		page = mtd_div_by_ws(to, mtd);
+	} else {
+		/* Do not allow write past end of device */
+		if (unlikely(to >= mtd->size ||
 		     ops->ooboffs + ops->ooblen >
 			((mtd->size >> chip->page_shift) -
 			 (to >> chip->page_shift)) * len)) {
-		MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
+			MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
 				"end of device\n", __func__);
-		return -EINVAL;
-	}
+			return -EINVAL;
+		}
 
-	chipnr = (int)(to >> chip->chip_shift);
-	chip->select_chip(mtd, chipnr);
+		chipnr = (int)(to >> chip->chip_shift);
+		chip->select_chip(mtd, chipnr);
 
-	/* Shift to get page */
-	page = (int)(to >> chip->page_shift);
+		/* Shift to get page */
+		page = (int)(to >> chip->page_shift);
+	}
 
 	/*
 	 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
@@ -2251,12 +2351,20 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 	/* Grab the lock and see if the device is available */
 	nand_get_device(chip, mtd, FL_ERASING);
 
-	/* Shift to get first page */
-	page = (int)(instr->addr >> chip->page_shift);
-	chipnr = (int)(instr->addr >> chip->chip_shift);
+	if (chip->page_shift == 0 ||chip->chip_shift == 0) {
+		/* Shift to get first page */
+		page = mtd_div_by_ws(instr->addr, mtd);
+		chipnr = mtd_div_by_cs(instr->addr, mtd);
 
-	/* Calculate pages in each block */
-	pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
+		/* Calculate pages in each block */
+		pages_per_block = mtd->erasesize / mtd->writesize;
+	} else {
+		page = (int)(instr->addr >> chip->page_shift);
+		chipnr = (int)(instr->addr >> chip->chip_shift);
+
+		/* Calculate pages in each block */
+		pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
+	}
 
 	/* Select the NAND device */
 	chip->select_chip(mtd, chipnr);
@@ -2288,13 +2396,23 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 		/*
 		 * heck if we have a bad block, we do not erase bad blocks !
 		 */
-		if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
+		 if (chip->page_shift == 0) {
+			if (!instr->scrub && nand_block_checkbad(mtd, (loff_t)page *
+					mtd->writesize, 0, allowbbt)) {
+				printk(KERN_WARNING "%s: attempt to erase a bad block "
+					"at page 0x%08x\n", __func__, page);
+				instr->state = MTD_ERASE_FAILED;
+				goto erase_exit;
+			}
+		 } else {
+			if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
 					chip->page_shift, 0, allowbbt)) {
-			printk(KERN_WARNING "%s: attempt to erase a bad block "
+				printk(KERN_WARNING "%s: attempt to erase a bad block "
 					"at page 0x%08x\n", __func__, page);
-			instr->state = MTD_ERASE_FAILED;
-			goto erase_exit;
-		}
+				instr->state = MTD_ERASE_FAILED;
+				goto erase_exit;
+			}
+		 }
 
 		/*
 		 * Invalidate the page cache, if we erase the block which
@@ -2317,26 +2435,44 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 					       status, page);
 
 		/* See if block erase succeeded */
-		if (status & NAND_STATUS_FAIL) {
-			MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
-					"page 0x%08x\n", __func__, page);
-			instr->state = MTD_ERASE_FAILED;
-			instr->fail_addr =
-				((loff_t)page << chip->page_shift);
-			goto erase_exit;
+		if (chip->page_shift == 0) {
+			if (status & NAND_STATUS_FAIL) {
+				MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
+						"page 0x%08x\n", __func__, page);
+				instr->state = MTD_ERASE_FAILED;
+				instr->fail_addr = (loff_t)page * mtd->writesize;
+				goto erase_exit;
+			}
+		} else {
+			if (status & NAND_STATUS_FAIL) {
+				MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
+						"page 0x%08x\n", __func__, page);
+				instr->state = MTD_ERASE_FAILED;
+				instr->fail_addr =	((loff_t)page << chip->page_shift);
+				goto erase_exit;
+			}
 		}
 
 		/*
 		 * If BBT requires refresh, set the BBT rewrite flag to the
 		 * page being erased
 		 */
-		if (bbt_masked_page != 0xffffffff &&
-		    (page & BBT_PAGE_MASK) == bbt_masked_page)
-			rewrite_bbt[chipnr] =
-				((loff_t)page << chip->page_shift);
+		if (chip->page_shift == 0) {
+			if (bbt_masked_page != 0xffffffff &&
+				(page & BBT_PAGE_MASK) == bbt_masked_page)
+			rewrite_bbt[chipnr] = (loff_t)page * mtd->writesize;
+		} else {
+			if (bbt_masked_page != 0xffffffff &&
+				(page & BBT_PAGE_MASK) == bbt_masked_page)
+			rewrite_bbt[chipnr] = ((loff_t)page << chip->page_shift);
+		}
 
 		/* Increment page address and decrement length */
-		len -= (1 << chip->phys_erase_shift);
+		if (chip->phys_erase_shift == 0)
+			len -= mtd->erasesize;
+		else
+			len -= (1 << chip->phys_erase_shift);
+
 		page += pages_per_block;
 
 		/* Check, if we cross a chip boundary */
@@ -2530,13 +2666,14 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
 		chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
 		return 0;
 
-	printk(KERN_INFO "ONFI flash detected\n");
+	MTDDEBUG(MTD_DEBUG_LEVEL0, "ONFI flash detected\n");
 	chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
 	for (i = 0; i < 3; i++) {
 		chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
 		if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
 				le16_to_cpu(p->crc)) {
-			printk(KERN_INFO "ONFI param page %d valid\n", i);
+			MTDDEBUG(MTD_DEBUG_LEVEL0,
+				 "ONFI param page %d valid\n", i);
 			break;
 		}
 	}
@@ -2732,10 +2869,14 @@ static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 		/*
 		 * Old devices have chip data hardcoded in the device id table
 		 */
-		mtd->erasesize = type->erasesize;
-		mtd->writesize = type->pagesize;
-		mtd->oobsize = mtd->writesize / 32;
-		busw = type->options & NAND_BUSWIDTH_16;
+		 if(chip->init_size) {
+			busw = chip->init_size(mtd, chip, id_data);
+		 } else {
+			mtd->erasesize = type->erasesize;
+			mtd->writesize = type->pagesize;
+			mtd->oobsize = mtd->writesize / 32;
+			busw = type->options & NAND_BUSWIDTH_16;
+		 }
 
 		/*
 		 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
@@ -2786,18 +2927,57 @@ ident_done:
 		return ERR_PTR(-EINVAL);
 	}
 
-	/* Calculate the address shift from the page size */
-	chip->page_shift = ffs(mtd->writesize) - 1;
-	/* Convert chipsize to number of pages per chip -1. */
-	chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
+	if (is_power_of_2(mtd->writesize)) {
+		/* Calculate the address shift from the page size */
+		chip->page_shift = ffs(mtd->writesize) - 1;
+		/* Convert chipsize to number of pages per chip -1. */
+		if (mtd->erasesize == 0x300000) {
+			/*page 0x180 ~ 0x1ff are invalid, so need skip to next block.*/
+			chip->pagemask = 0xffffffff;
+		} else {
+			chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
+		}
+	} else {
+		chip->page_shift = 0;
+		if (mtd->erasesize == 0x300000) {
+			/*page 0x180 ~ 0x1ff are invalid, so need skip to next block.*/
+			chip->pagemask = 0xffffffff;
+		} else {
+			chip->pagemask = mtd_div_by_ws(chip->chipsize , mtd) - 1;
+		}
+	}
+
+	if (is_power_of_2(mtd->erasesize))
+		chip->bbt_erase_shift = chip->phys_erase_shift = ffs(mtd->erasesize) - 1;
+	else
+		chip->bbt_erase_shift = chip->phys_erase_shift = 0;
+
+	if(chip->chipsize >> 32){
+		//assume the chipsize is not out of 4096TB(4*1024*1024*GB)
+		//4096TB is 52bits.
+		if(is_power_of_2(chip->chipsize >> 20)){
+			chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
+			chip->chip_shift += 32 - 1;
+		}else{
+			chip->chip_shift = 0;
+		}
+	} else {
+		if (is_power_of_2(chip->chipsize)) {
+			chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
+		}else{
+			chip->chip_shift = 0;
+		}
+	}
+
+	printf("nand page_shift = 0x%x, erase_shift = 0x%x, chip_shift = 0x%x \n", chip->page_shift, chip->bbt_erase_shift, chip->chip_shift);
 
-	chip->bbt_erase_shift = chip->phys_erase_shift =
-		ffs(mtd->erasesize) - 1;
-	if (chip->chipsize & 0xffffffff)
-		chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
-	else {
-		chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
-		chip->chip_shift += 32 - 1;
+	if (mtd->oobsize != 32 && mtd->oobsize != 16) {
+		if (mtd->writesize == 3072)
+			mtd->oobsize = 128;
+		else if (mtd->writesize == 6144)
+			mtd->oobsize = 256;
+		else if (mtd->writesize == 12288)
+			mtd->oobsize = 512;
 	}
 
 	chip->badblockbits = 8;
diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c
index 2b730e09c9..74d4fb9a73 100644
--- a/drivers/mtd/nand/nand_bbt.c
+++ b/drivers/mtd/nand/nand_bbt.c
@@ -61,7 +61,7 @@
 
 #include <common.h>
 #include <malloc.h>
-#include <linux/mtd/compat.h>
+#include <linux/compat.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/nand_ecc.h>
@@ -210,7 +210,7 @@ static u32 add_marker_len(struct nand_bbt_descr *td)
  *
  */
 static int read_bbt(struct mtd_info *mtd, uint8_t *buf, int page, int num,
-		struct nand_bbt_descr *td, int offs)
+		struct nand_bbt_descr *td, loff_t offs)
 {
 	int res, i, j, act = 0;
 	struct nand_chip *this = mtd->priv;
@@ -223,10 +223,17 @@ static int read_bbt(struct mtd_info *mtd, uint8_t *buf, int page, int num,
 
 	totlen = (num * bits) >> 3;
 	marker_len = add_marker_len(td);
-	from = ((loff_t) page) << this->page_shift;
+	if (this->page_shift == 0)
+		from = (loff_t)page * mtd->writesize;
+	else
+		from = ((loff_t) page) << this->page_shift;
 
 	while (totlen) {
-		len = min(totlen, (size_t) (1 << this->bbt_erase_shift));
+		if (this->bbt_erase_shift == 0)
+			len = min(totlen, mtd->erasesize);
+		else
+			len = min(totlen, (size_t) (1 << this->bbt_erase_shift));
+
 		if (marker_len) {
 			/*
 			 * In case the BBT marker is not in the OOB area it
@@ -253,16 +260,29 @@ static int read_bbt(struct mtd_info *mtd, uint8_t *buf, int page, int num,
 				if (tmp == msk)
 					continue;
 				if (reserved_block_code && (tmp == reserved_block_code)) {
-					printk(KERN_DEBUG "nand_read_bbt: Reserved block at 0x%012llx\n",
-					       (loff_t)((offs << 2) + (act >> 1)) << this->bbt_erase_shift);
+					if (this->bbt_erase_shift == 0)
+						printk(KERN_DEBUG "nand_read_bbt: " \
+							"Reserved block at 0x%012llx\n",
+						 (loff_t)((offs << 2) + (act >> 1)) * mtd->erasesize);
+					else
+						printk(KERN_DEBUG "nand_read_bbt: " \
+							"Reserved block at 0x%012llx\n",
+					       (loff_t)((offs << 2) + (act >> 1)) <<
+					       this->bbt_erase_shift);
+
 					this->bbt[offs + (act >> 3)] |= 0x2 << (act & 0x06);
 					mtd->ecc_stats.bbtblocks++;
 					continue;
 				}
-				/* Leave it for now, if its matured we can move this
-				 * message to MTD_DEBUG_LEVEL0 */
-				printk(KERN_DEBUG "nand_read_bbt: Bad block at 0x%012llx\n",
-				       (loff_t)((offs << 2) + (act >> 1)) << this->bbt_erase_shift);
+				if (this->bbt_erase_shift == 0)
+					MTDDEBUG(MTD_DEBUG_LEVEL0, "nand_read_bbt: " \
+					"Bad block at 0x%012llx\n",
+					(loff_t)((offs << 2) + (act >> 1)) * mtd->erasesize);
+				else
+					MTDDEBUG(MTD_DEBUG_LEVEL0, "nand_read_bbt: " \
+					"Bad block at 0x%012llx\n",
+					(loff_t)((offs << 2) + (act >> 1))
+					<< this->bbt_erase_shift);
 				/* Factory marked bad or worn out ? */
 				if (tmp == 0)
 					this->bbt[offs + (act >> 3)] |= 0x3 << (act & 0x06);
@@ -294,19 +314,34 @@ static int read_abs_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_desc
 	int res = 0, i;
 
 	if (td->options & NAND_BBT_PERCHIP) {
-		int offs = 0;
+		loff_t offs = 0;
 		for (i = 0; i < this->numchips; i++) {
-			if (chip == -1 || chip == i)
-				res = read_bbt(mtd, buf, td->pages[i],
+			if (chip == -1 || chip == i) {
+				if (this->bbt_erase_shift == 0) {
+					res = read_bbt(mtd, buf, td->pages[i],
+					mtd_div_by_eb(this->chipsize, mtd),
+					td, offs);
+				} else {
+					res = read_bbt(mtd, buf, td->pages[i],
 					this->chipsize >> this->bbt_erase_shift,
 					td, offs);
+				}
+			}
 			if (res)
 				return res;
-			offs += this->chipsize >> (this->bbt_erase_shift + 2);
+			if (this->bbt_erase_shift == 0)
+				offs += mtd_div_by_eb(this->chipsize >> 2, mtd);
+			else
+				offs += this->chipsize >> (this->bbt_erase_shift + 2);
 		}
 	} else {
-		res = read_bbt(mtd, buf, td->pages[0],
+		if (this->bbt_erase_shift == 0)
+			res = read_bbt(mtd, buf, td->pages[0],
+				mtd_div_by_eb(mtd->size, mtd), td, 0);
+		else
+			res = read_bbt(mtd, buf, td->pages[0],
 				mtd->size >> this->bbt_erase_shift, td, 0);
+
 		if (res)
 			return res;
 	}
@@ -419,8 +454,13 @@ static int read_abs_bbts(struct mtd_info *mtd, uint8_t *buf,
 
 	/* Read the primary version, if available */
 	if (td->options & NAND_BBT_VERSION) {
-		scan_read_raw(mtd, buf, (loff_t)td->pages[0] << this->page_shift,
+		if (this->page_shift == 0)
+			scan_read_raw(mtd, buf, (loff_t)td->pages[0] * mtd->writesize,
 			      mtd->writesize, td);
+		else
+			scan_read_raw(mtd, buf, (loff_t)td->pages[0] << this->page_shift,
+			      mtd->writesize, td);
+
 		td->version[0] = buf[bbt_get_ver_offs(mtd, td)];
 		printk(KERN_DEBUG "Bad block table at page %d, version 0x%02X\n",
 		       td->pages[0], td->version[0]);
@@ -428,8 +468,13 @@ static int read_abs_bbts(struct mtd_info *mtd, uint8_t *buf,
 
 	/* Read the mirror version, if available */
 	if (md && (md->options & NAND_BBT_VERSION)) {
-		scan_read_raw(mtd, buf, (loff_t)md->pages[0] << this->page_shift,
+		if (this->page_shift == 0)
+			scan_read_raw(mtd, buf, (loff_t)md->pages[0] * mtd->writesize,
+			      mtd->writesize, td);
+		else
+			scan_read_raw(mtd, buf, (loff_t)md->pages[0] << this->page_shift,
 			      mtd->writesize, td);
+
 		md->version[0] = buf[bbt_get_ver_offs(mtd, md)];
 		printk(KERN_DEBUG "Bad block table at page %d, version 0x%02X\n",
 		       md->pages[0], md->version[0]);
@@ -512,9 +557,12 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf,
 
 	MTDDEBUG(MTD_DEBUG_LEVEL0, "Scanning device for bad blocks\n");
 
-	if (bd->options & NAND_BBT_SCANALLPAGES)
-		len = 1 << (this->bbt_erase_shift - this->page_shift);
-	else if (bd->options & NAND_BBT_SCAN2NDPAGE)
+	if (bd->options & NAND_BBT_SCANALLPAGES) {
+		if (this->page_shift == 0 || this->bbt_erase_shift == 0)
+			len = mtd->erasesize / mtd->writesize;
+		else
+			len = 1 << (this->bbt_erase_shift - this->page_shift);
+	} else if (bd->options & NAND_BBT_SCAN2NDPAGE)
 		len = 2;
 	else
 		len = 1;
@@ -532,7 +580,11 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf,
 	if (chip == -1) {
 		/* Note that numblocks is 2 * (real numblocks) here, see i+=2
 		 * below as it makes shifting and masking less painful */
-		numblocks = mtd->size >> (this->bbt_erase_shift - 1);
+		if (this->bbt_erase_shift == 0)
+			numblocks = mtd_div_by_eb(mtd->size << 1, mtd);
+		else
+			numblocks = mtd->size >> (this->bbt_erase_shift - 1);
+
 		startblock = 0;
 		from = 0;
 	} else {
@@ -541,10 +593,19 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf,
 			       chip + 1, this->numchips);
 			return -EINVAL;
 		}
-		numblocks = this->chipsize >> (this->bbt_erase_shift - 1);
+
+		if (this->bbt_erase_shift == 0)
+			numblocks = mtd_div_by_eb(this->chipsize << 1, mtd);
+		else
+			numblocks = this->chipsize >> (this->bbt_erase_shift - 1);
+
 		startblock = chip * numblocks;
 		numblocks += startblock;
-		from = (loff_t)startblock << (this->bbt_erase_shift - 1);
+
+		if (this->bbt_erase_shift == 0)
+			from = (loff_t)startblock * (mtd->erasesize >> 1);
+		else
+			from = (loff_t)startblock << (this->bbt_erase_shift - 1);
 	}
 
 	if (this->options & NAND_BBT_SCANLASTPAGE)
@@ -573,7 +634,11 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf,
 		}
 
 		i += 2;
-		from += (1 << this->bbt_erase_shift);
+
+		if (this->bbt_erase_shift == 0)
+			from += mtd->erasesize;
+		else
+			from += (1 << this->bbt_erase_shift);
 	}
 	return 0;
 }
@@ -602,11 +667,14 @@ static int search_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr
 	int startblock, block, dir;
 	int scanlen = mtd->writesize + mtd->oobsize;
 	int bbtblocks;
-	int blocktopage = this->bbt_erase_shift - this->page_shift;
 
 	/* Search direction top -> down ? */
 	if (td->options & NAND_BBT_LASTBLOCK) {
-		startblock = (mtd->size >> this->bbt_erase_shift) - 1;
+		if (this->bbt_erase_shift == 0)
+			startblock = mtd_div_by_eb(mtd->size, mtd) - 1;
+		else
+			startblock = (mtd->size >> this->bbt_erase_shift) - 1;
+
 		dir = -1;
 	} else {
 		startblock = 0;
@@ -616,11 +684,18 @@ static int search_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr
 	/* Do we have a bbt per chip ? */
 	if (td->options & NAND_BBT_PERCHIP) {
 		chips = this->numchips;
-		bbtblocks = this->chipsize >> this->bbt_erase_shift;
+		if (this->bbt_erase_shift == 0)
+			bbtblocks = mtd_div_by_eb(this->chipsize, mtd);
+		else
+			bbtblocks = this->chipsize >> this->bbt_erase_shift;
+
 		startblock &= bbtblocks - 1;
 	} else {
 		chips = 1;
-		bbtblocks = mtd->size >> this->bbt_erase_shift;
+		if (this->bbt_erase_shift == 0)
+			bbtblocks = mtd_div_by_eb(mtd->size, mtd);
+		else
+			bbtblocks = mtd->size >> this->bbt_erase_shift;
 	}
 
 	for (i = 0; i < chips; i++) {
@@ -629,14 +704,21 @@ static int search_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr
 		td->pages[i] = -1;
 		/* Scan the maximum number of blocks */
 		for (block = 0; block < td->maxblocks; block++) {
-
+			loff_t offs;
 			int actblock = startblock + dir * block;
-			loff_t offs = (loff_t)actblock << this->bbt_erase_shift;
+			if (this->bbt_erase_shift == 0)
+				offs = (loff_t)actblock * mtd->erasesize;
+			else
+				offs = (loff_t)actblock << this->bbt_erase_shift;
 
 			/* Read first page */
 			scan_read_raw(mtd, buf, offs, mtd->writesize, td);
 			if (!check_pattern(buf, scanlen, mtd->writesize, td)) {
-				td->pages[i] = actblock << blocktopage;
+				if (this->page_shift == 0 || this->bbt_erase_shift == 0)
+					td->pages[i] = actblock * (mtd->erasesize / mtd->writesize);
+				else
+					td->pages[i] = actblock << (this->bbt_erase_shift - this->page_shift);
+
 				if (td->options & NAND_BBT_VERSION) {
 					offs = bbt_get_ver_offs(mtd, td);
 					td->version[i] = buf[offs];
@@ -644,15 +726,19 @@ static int search_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr
 				break;
 			}
 		}
-		startblock += this->chipsize >> this->bbt_erase_shift;
+		if (this->bbt_erase_shift == 0)
+			startblock += mtd_div_by_eb(this->chipsize, mtd);
+		else
+			startblock += this->chipsize >> this->bbt_erase_shift;
 	}
 	/* Check, if we found a bbt for each requested chip */
 	for (i = 0; i < chips; i++) {
 		if (td->pages[i] == -1)
 			printk(KERN_WARNING "Bad block table not found for chip %d\n", i);
 		else
-			printk(KERN_DEBUG "Bad block table found at page %d, version 0x%02X\n", td->pages[i],
-			       td->version[i]);
+			MTDDEBUG(MTD_DEBUG_LEVEL0, "Bad block table found " \
+				"at page %d, version 0x%02X\n", td->pages[i],
+				td->version[i]);
 	}
 	return 0;
 }
@@ -698,12 +784,12 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf,
 	struct nand_chip *this = mtd->priv;
 	struct erase_info einfo;
 	int i, j, res, chip = 0;
-	int bits, startblock, dir, page, offs, numblocks, sft, sftmsk;
+	int bits, startblock, dir, page, numblocks, sft, sftmsk;
 	int nrchips, bbtoffs, pageoffs, ooboffs;
 	uint8_t msk[4];
 	uint8_t rcode = td->reserved_block_code;
 	size_t retlen, len = 0;
-	loff_t to;
+	loff_t offs, to;
 	struct mtd_oob_ops ops;
 
 	ops.ooblen = mtd->oobsize;
@@ -715,7 +801,10 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf,
 		rcode = 0xff;
 	/* Write bad block table per chip rather than per device ? */
 	if (td->options & NAND_BBT_PERCHIP) {
-		numblocks = (int)(this->chipsize >> this->bbt_erase_shift);
+		if (this->bbt_erase_shift == 0)
+			numblocks = mtd_div_by_eb(this->chipsize, mtd);
+		else
+			numblocks = (int)(this->chipsize >> this->bbt_erase_shift);
 		/* Full device write or specific chip ? */
 		if (chipsel == -1) {
 			nrchips = this->numchips;
@@ -724,7 +813,11 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf,
 			chip = chipsel;
 		}
 	} else {
-		numblocks = (int)(mtd->size >> this->bbt_erase_shift);
+		if (this->bbt_erase_shift == 0)
+			numblocks = mtd_div_by_eb(mtd->size, mtd);
+		else
+			numblocks = (int)(mtd->size >> this->bbt_erase_shift);
+
 		nrchips = 1;
 	}
 
@@ -759,8 +852,11 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf,
 			case 0x03:
 				continue;
 			}
-			page = block <<
-				(this->bbt_erase_shift - this->page_shift);
+			if (this->bbt_erase_shift == 0 || this->page_shift == 0)
+				page = block *(mtd->erasesize / mtd->writesize);
+			else
+				page = block << (this->bbt_erase_shift - this->page_shift);
+
 			/* Check, if the block is used by the mirror table */
 			if (!md || md->pages[chip] != page)
 				goto write;
@@ -789,14 +885,21 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf,
 		}
 
 		bbtoffs = chip * (numblocks >> 2);
-
-		to = ((loff_t) page) << this->page_shift;
+		if (this->page_shift == 0)
+			to = (loff_t) page * mtd->writesize;
+		else
+			to = ((loff_t) page) << this->page_shift;
 
 		/* Must we save the block contents ? */
 		if (td->options & NAND_BBT_SAVECONTENT) {
 			/* Make it block aligned */
-			to &= ~((loff_t) ((1 << this->bbt_erase_shift) - 1));
-			len = 1 << this->bbt_erase_shift;
+			if (this->bbt_erase_shift == 0) {
+				to = mtd_div_by_eb(to, mtd) * mtd->erasesize;
+				len = mtd->erasesize;
+			} else {
+				to &= ~((loff_t) ((1 << this->bbt_erase_shift) - 1));
+				len = 1 << this->bbt_erase_shift;
+			}
 			res = mtd->read(mtd, to, len, &retlen, buf);
 			if (res < 0) {
 				if (retlen != len) {
@@ -810,19 +913,28 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf,
 				       "bad block table\n");
 			}
 			/* Read oob data */
-			ops.ooblen = (len >> this->page_shift) * mtd->oobsize;
+			if (this->page_shift == 0)
+				ops.ooblen = mtd_div_by_ws(len, mtd) * mtd->oobsize;
+			else
+				ops.ooblen = (len >> this->page_shift) * mtd->oobsize;
+
 			ops.oobbuf = &buf[len];
 			res = mtd->read_oob(mtd, to + mtd->writesize, &ops);
 			if (res < 0 || ops.oobretlen != ops.ooblen)
 				goto outerr;
 
 			/* Calc the byte offset in the buffer */
-			pageoffs = page - (int)(to >> this->page_shift);
-			offs = pageoffs << this->page_shift;
+			if (this->page_shift == 0) {
+				pageoffs = page - mtd_div_by_ws(to, mtd);
+				offs = pageoffs * mtd->writesize;
+			} else {
+				pageoffs = page - (int)(to >> this->page_shift);
+				offs = pageoffs << this->page_shift;
+			}
+
 			/* Preset the bbt area with 0xff */
 			memset(&buf[offs], 0xff, (size_t) (numblocks >> sft));
 			ooboffs = len + (pageoffs * mtd->oobsize);
-
 		} else if (td->options & NAND_BBT_NO_OOB) {
 			ooboffs = 0;
 			offs = td->len;
@@ -833,7 +945,11 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf,
 			len = (size_t) (numblocks >> sft);
 			len += offs;
 			/* Make it page aligned ! */
-			len = ALIGN(len, mtd->writesize);
+			if (this->page_shift == 0)
+				len = roundup(len, mtd->writesize);
+			else
+				len = ALIGN(len, mtd->writesize);
+
 			/* Preset the buffer with 0xff */
 			memset(buf, 0xff, len);
 			/* Pattern is located at the begin of first page */
@@ -842,10 +958,18 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf,
 			/* Calc length */
 			len = (size_t) (numblocks >> sft);
 			/* Make it page aligned ! */
-			len = ALIGN(len, mtd->writesize);
+			if (this->page_shift == 0)
+				len = roundup(len, mtd->writesize);
+			else
+				len = ALIGN(len, mtd->writesize);
 			/* Preset the buffer with 0xff */
-			memset(buf, 0xff, len +
-			       (len >> this->page_shift)* mtd->oobsize);
+			if (this->page_shift == 0)
+				memset(buf, 0xff, len +
+					mtd_div_by_ws(len, mtd) * mtd->oobsize);
+			else
+				memset(buf, 0xff, len +
+			       	(len >> this->page_shift)* mtd->oobsize);
+
 			offs = 0;
 			ooboffs = len;
 			/* Pattern is located in oob area of first page */
@@ -871,7 +995,11 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf,
 		memset(&einfo, 0, sizeof(einfo));
 		einfo.mtd = mtd;
 		einfo.addr = to;
-		einfo.len = 1 << this->bbt_erase_shift;
+		if (this->bbt_erase_shift == 0)
+			einfo.len = mtd->erasesize;
+		else
+			einfo.len = 1 << this->bbt_erase_shift;
+
 		res = nand_erase_nand(mtd, &einfo, 1);
 		if (res < 0)
 			goto outerr;
@@ -1047,10 +1175,16 @@ static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td)
 	/* Do we have a bbt per chip ? */
 	if (td->options & NAND_BBT_PERCHIP) {
 		chips = this->numchips;
-		nrblocks = (int)(this->chipsize >> this->bbt_erase_shift);
+		if (this->bbt_erase_shift == 0)
+			nrblocks = mtd_div_by_eb(this->chipsize, mtd);
+		else
+			nrblocks = (int)(this->chipsize >> this->bbt_erase_shift);
 	} else {
 		chips = 1;
-		nrblocks = (int)(mtd->size >> this->bbt_erase_shift);
+		if (this->bbt_erase_shift == 0)
+			nrblocks = mtd_div_by_eb(mtd->size, mtd);
+		else
+			nrblocks = (int)(mtd->size >> this->bbt_erase_shift);
 	}
 
 	for (i = 0; i < chips; i++) {
@@ -1058,13 +1192,21 @@ static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td)
 		    !(td->options & NAND_BBT_WRITE)) {
 			if (td->pages[i] == -1)
 				continue;
-			block = td->pages[i] >> (this->bbt_erase_shift - this->page_shift);
+			if (this->bbt_erase_shift == 0 || this->page_shift == 0)
+				block = td->pages[i] / (mtd->erasesize / mtd->writesize);
+			else
+				block = td->pages[i] >> (this->bbt_erase_shift - this->page_shift);
+
 			block <<= 1;
 			oldval = this->bbt[(block >> 3)];
 			newval = oldval | (0x2 << (block & 0x06));
 			this->bbt[(block >> 3)] = newval;
-			if ((oldval != newval) && td->reserved_block_code)
-				nand_update_bbt(mtd, (loff_t)block << (this->bbt_erase_shift - 1));
+			if ((oldval != newval) && td->reserved_block_code) {
+				if (this->bbt_erase_shift == 0)
+					nand_update_bbt(mtd, (loff_t)block * (mtd->erasesize >> 1));
+				else
+					nand_update_bbt(mtd, (loff_t)block << (this->bbt_erase_shift - 1));
+			}
 			continue;
 		}
 		update = 0;
@@ -1084,8 +1226,12 @@ static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td)
 		/* If we want reserved blocks to be recorded to flash, and some
 		   new ones have been marked, then we need to update the stored
 		   bbts.  This should only happen once. */
-		if (update && td->reserved_block_code)
-			nand_update_bbt(mtd, (loff_t)(block - 2) << (this->bbt_erase_shift - 1));
+		if (update && td->reserved_block_code) {
+			if (this->bbt_erase_shift == 0)
+				nand_update_bbt(mtd, (loff_t)(block - 2) * (mtd->erasesize >> 1));
+			else
+				nand_update_bbt(mtd, (loff_t)(block - 2) << (this->bbt_erase_shift - 1));
+		}
 	}
 }
 
@@ -1126,15 +1272,26 @@ static void verify_bbt_descr(struct mtd_info *mtd, struct nand_bbt_descr *bd)
 		BUG_ON(bd->options & NAND_BBT_SAVECONTENT);
 	}
 
-	if (bd->options & NAND_BBT_PERCHIP)
-		table_size = this->chipsize >> this->bbt_erase_shift;
-	else
-		table_size = mtd->size >> this->bbt_erase_shift;
+	if (bd->options & NAND_BBT_PERCHIP) {
+		if (this->bbt_erase_shift == 0)
+			table_size = mtd_div_by_eb(this->chipsize, mtd);
+		else
+			table_size = this->chipsize >> this->bbt_erase_shift;
+	} else {
+		if (this->bbt_erase_shift == 0)
+			table_size = mtd_div_by_eb(mtd->size, mtd);
+		else
+			table_size = mtd->size >> this->bbt_erase_shift;
+	}
 	table_size >>= 3;
 	table_size *= bits;
 	if (bd->options & NAND_BBT_NO_OOB)
 		table_size += pattern_len;
-	BUG_ON(table_size > (1 << this->bbt_erase_shift));
+
+	if (this->bbt_erase_shift == 0)
+		BUG_ON(table_size > mtd->erasesize);
+	else
+		BUG_ON(table_size > (1 << this->bbt_erase_shift));
 }
 
 /**
@@ -1159,7 +1316,11 @@ int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
 	struct nand_bbt_descr *td = this->bbt_td;
 	struct nand_bbt_descr *md = this->bbt_md;
 
-	len = mtd->size >> (this->bbt_erase_shift + 2);
+	if (this->bbt_erase_shift == 0)
+		len = mtd_div_by_eb(mtd->size >> 2, mtd);
+	else
+		len = mtd->size >> (this->bbt_erase_shift + 2);
+
 	/* Allocate memory (2bit per block) and clear the memory bad block table */
 	this->bbt = kzalloc(len, GFP_KERNEL);
 	if (!this->bbt) {
@@ -1182,8 +1343,13 @@ int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
 	verify_bbt_descr(mtd, md);
 
 	/* Allocate a temporary buffer for one eraseblock incl. oob */
-	len = (1 << this->bbt_erase_shift);
-	len += (len >> this->page_shift) * mtd->oobsize;
+	if (this->bbt_erase_shift == 0 || this->page_shift == 0) {
+		len = mtd->erasesize;
+		len += mtd_div_by_ws(len, mtd) * mtd->oobsize;
+	} else {
+		len = (1 << this->bbt_erase_shift);
+		len += (len >> this->page_shift) * mtd->oobsize;
+	}
 	buf = vmalloc(len);
 	if (!buf) {
 		printk(KERN_ERR "nand_bbt: Out of memory\n");
@@ -1232,8 +1398,13 @@ int nand_update_bbt(struct mtd_info *mtd, loff_t offs)
 		return -EINVAL;
 
 	/* Allocate a temporary buffer for one eraseblock incl. oob */
-	len = (1 << this->bbt_erase_shift);
-	len += (len >> this->page_shift) * mtd->oobsize;
+	if (this->bbt_erase_shift == 0 || this->page_shift == 0) {
+		len = mtd->erasesize;
+		len += mtd_div_by_ws(len, mtd) * mtd->oobsize;
+	} else {
+		len = (1 << this->bbt_erase_shift);
+		len += (len >> this->page_shift) * mtd->oobsize;
+	}
 	buf = kmalloc(len, GFP_KERNEL);
 	if (!buf) {
 		printk(KERN_ERR "nand_update_bbt: Out of memory\n");
@@ -1244,7 +1415,11 @@ int nand_update_bbt(struct mtd_info *mtd, loff_t offs)
 
 	/* Do we have a bbt per chip ? */
 	if (td->options & NAND_BBT_PERCHIP) {
-		chip = (int)(offs >> this->chip_shift);
+		if (this->chip_shift == 0)
+			chip = mtd_div_by_cs(offs, mtd);
+		else
+			chip = (int)(offs >> this->chip_shift);
+
 		chipsel = chip;
 	} else {
 		chip = 0;
@@ -1428,7 +1603,11 @@ int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt)
 	uint8_t res;
 
 	/* Get block number * 2 */
-	block = (int)(offs >> (this->bbt_erase_shift - 1));
+	if (this->bbt_erase_shift == 0)
+		block = mtd_div_by_eb(offs << 1, mtd);
+	else
+		block = (int)(offs >> (this->bbt_erase_shift - 1));
+
 	res = (this->bbt[block >> 3] >> (block & 0x06)) & 0x03;
 
 	MTDDEBUG(MTD_DEBUG_LEVEL2, "nand_isbad_bbt(): bbt info for offs 0x%08x: (block %d) 0x%02x\n",
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index 39535497f8..580a080c1c 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -11,6 +11,13 @@
 
 #include <common.h>
 #include <linux/mtd/nand.h>
+#include <rda/tgt_ap_board_config.h>
+#include <rda/tgt_ap_flash_parts.h>
+
+#if defined(CONFIG_NAND_RDA_V1) && !defined(_TGT_AP_NAND_DISABLE_HEC)
+#define RDA_NAND_WITH_HEC
+#endif
+
 /*
 *	Chip ID list
 *
@@ -77,7 +84,7 @@ const struct nand_flash_dev nand_flash_ids[] = {
 	/*512 Megabit */
 	{"NAND 64MiB 1,8V 8-bit",	0xA2, 0,  64, 0, LP_OPTIONS},
 	{"NAND 64MiB 1,8V 8-bit",	0xA0, 0,  64, 0, LP_OPTIONS},
-	{"NAND 64MiB 3,3V 8-bit",	0xF2, 0,  64, 0, LP_OPTIONS},
+	/*{"NAND 64MiB 3,3V 8-bit",	0xF2, 0,  64, 0, LP_OPTIONS},*/
 	{"NAND 64MiB 3,3V 8-bit",	0xD0, 0,  64, 0, LP_OPTIONS},
 	{"NAND 64MiB 1,8V 16-bit",	0xB2, 0,  64, 0, LP_OPTIONS16},
 	{"NAND 64MiB 1,8V 16-bit",	0xB0, 0,  64, 0, LP_OPTIONS16},
@@ -90,7 +97,7 @@ const struct nand_flash_dev nand_flash_ids[] = {
 	{"NAND 128MiB 3,3V 8-bit",	0xD1, 0, 128, 0, LP_OPTIONS},
 	{"NAND 128MiB 1,8V 16-bit",	0xB1, 0, 128, 0, LP_OPTIONS16},
 	{"NAND 128MiB 3,3V 16-bit",	0xC1, 0, 128, 0, LP_OPTIONS16},
-	{"NAND 128MiB 1,8V 16-bit",     0xAD, 0, 128, 0, LP_OPTIONS16},
+	{"NAND 128MiB 1,8V 16-bit", 0xAD, 0, 128, 0, LP_OPTIONS16},
 
 	/* 2 Gigabit */
 	{"NAND 256MiB 1,8V 8-bit",	0xAA, 0, 256, 0, LP_OPTIONS},
@@ -101,42 +108,43 @@ const struct nand_flash_dev nand_flash_ids[] = {
 	/* 4 Gigabit */
 	{"NAND 512MiB 1,8V 8-bit",	0xAC, 0, 512, 0, LP_OPTIONS},
 	{"NAND 512MiB 3,3V 8-bit",	0xDC, 0, 512, 0, LP_OPTIONS},
+	//{"NAND 512MiB 3,3V 8-bit",	0xDC, 0, 384, 0, LP_OPTIONS},
 	{"NAND 512MiB 1,8V 16-bit",	0xBC, 0, 512, 0, LP_OPTIONS16},
 	{"NAND 512MiB 3,3V 16-bit",	0xCC, 0, 512, 0, LP_OPTIONS16},
 
 	/* 8 Gigabit */
 	{"NAND 1GiB 1,8V 8-bit",	0xA3, 0, 1024, 0, LP_OPTIONS},
-	{"NAND 1GiB 3,3V 8-bit",	0xD3, 0, 1024, 0, LP_OPTIONS},
+	//{"NAND 1GiB 3,3V 8-bit",	0xD3, 0, 1024, 0, LP_OPTIONS},
 	{"NAND 1GiB 1,8V 16-bit",	0xB3, 0, 1024, 0, LP_OPTIONS16},
 	{"NAND 1GiB 3,3V 16-bit",	0xC3, 0, 1024, 0, LP_OPTIONS16},
 
 	/* 16 Gigabit */
 	{"NAND 2GiB 1,8V 8-bit",	0xA5, 0, 2048, 0, LP_OPTIONS},
-	{"NAND 2GiB 3,3V 8-bit",	0xD5, 0, 2048, 0, LP_OPTIONS},
+	//{"NAND 2GiB 3,3V 8-bit",	0xD5, 0, 2048, 0, LP_OPTIONS},
 	{"NAND 2GiB 1,8V 16-bit",	0xB5, 0, 2048, 0, LP_OPTIONS16},
 	{"NAND 2GiB 3,3V 16-bit",	0xC5, 0, 2048, 0, LP_OPTIONS16},
 
 	/* 32 Gigabit */
 	{"NAND 4GiB 1,8V 8-bit",	0xA7, 0, 4096, 0, LP_OPTIONS},
-	{"NAND 4GiB 3,3V 8-bit",	0xD7, 0, 4096, 0, LP_OPTIONS},
+//	{"NAND 4GiB 3,3V 8-bit",	0xD7, 0, 4096, 0, LP_OPTIONS},
 	{"NAND 4GiB 1,8V 16-bit",	0xB7, 0, 4096, 0, LP_OPTIONS16},
 	{"NAND 4GiB 3,3V 16-bit",	0xC7, 0, 4096, 0, LP_OPTIONS16},
 
 	/* 64 Gigabit */
 	{"NAND 8GiB 1,8V 8-bit",	0xAE, 0, 8192, 0, LP_OPTIONS},
-	{"NAND 8GiB 3,3V 8-bit",	0xDE, 0, 8192, 0, LP_OPTIONS},
+	//{"NAND 8GiB 3,3V 8-bit",	0xDE, 0, 8192, 0, LP_OPTIONS},
 	{"NAND 8GiB 1,8V 16-bit",	0xBE, 0, 8192, 0, LP_OPTIONS16},
 	{"NAND 8GiB 3,3V 16-bit",	0xCE, 0, 8192, 0, LP_OPTIONS16},
 
 	/* 128 Gigabit */
 	{"NAND 16GiB 1,8V 8-bit",	0x1A, 0, 16384, 0, LP_OPTIONS},
-	{"NAND 16GiB 3,3V 8-bit",	0x3A, 0, 16384, 0, LP_OPTIONS},
+	//{"NAND 16GiB 3,3V 8-bit",	0x3A, 0, 16384, 0, LP_OPTIONS},
 	{"NAND 16GiB 1,8V 16-bit",	0x2A, 0, 16384, 0, LP_OPTIONS16},
 	{"NAND 16GiB 3,3V 16-bit",	0x4A, 0, 16384, 0, LP_OPTIONS16},
 
 	/* 256 Gigabit */
 	{"NAND 32GiB 1,8V 8-bit",	0x1C, 0, 32768, 0, LP_OPTIONS},
-	{"NAND 32GiB 3,3V 8-bit",	0x3C, 0, 32768, 0, LP_OPTIONS},
+	//{"NAND 32GiB 3,3V 8-bit",	0x3C, 0, 32768, 0, LP_OPTIONS},
 	{"NAND 32GiB 1,8V 16-bit",	0x2C, 0, 32768, 0, LP_OPTIONS16},
 	{"NAND 32GiB 3,3V 16-bit",	0x4C, 0, 32768, 0, LP_OPTIONS16},
 
@@ -161,6 +169,204 @@ const struct nand_flash_dev nand_flash_ids[] = {
 	 BBT_AUTO_REFRESH
 	},
 
+	/*
+	 * RDA Normal HW ECC support
+	 * use 4K page as 4K page, support SLC nand only
+	 */
+	{"NAND 512MB 1,8V 16-bit",	0xbc, 0, 512, 0x40000,
+	 LP_OPTIONS16
+	},
+	/*
+	{"NAND 1,8V 16-bit slc",	0xbc, 4096, 512, 0x40000,
+	 LP_OPTIONS16
+	},
+	*/
+
+#ifdef RDA_NAND_WITH_HEC
+	/*
+	 * RDA HEC support, for 4k MLC nand
+	 * use 4K page as 2K page, leave 2K space for HEC
+	 * therefore, chip_size should be half
+	 * and erase_size should be 256*2k = 512k = 0x80000
+	 * Now, supported NAND
+	 *   - Micron MT29F16xxxCA: ID = 2C 48 xx xx (16Gb use as a 8Gb NAND)
+	 *   - Micron MT29F32xxxCA: ID = 2C 68 xx xx (32Gb use as a 16Gb NAND)
+	 *   - sptek              : ID = 2C 64 xx xx (32Gb use as a 16Gb NAND) 
+	 *   - hynix              : ID = AD D7 xx xx (32Gb use as a 16Gb NAND) 
+	 */
+	{"NAND 1GiB 3,3V 8-bit",	0x48, 2048, 1024, 0x80000,
+	 LP_OPTIONS
+	},
+#if(__TGT_AP_FLASH_USE_PART_OF_PAGE__ == 1)
+#if(__TGT_AP_FLASH_LOGIC_PAGE_SIZE_N_KB__ == __TGT_AP_FLASH_USE_4KAS2K_PAGE_DIV__)
+	{"NAND 2GiB 3,3V 8-bit",	0x68, 2048, 2048, 0x80000,
+	 LP_OPTIONS
+	},
+#else
+#if(__TGT_AP_FLASH_LOGIC_PAGE_SIZE_N_KB__ == __TGT_AP_FLASH_USE_4KAS3K_PAGE_DIV__)
+	{"NAND 3GiB 3,3V 8-bit",	0x68, 3072, 3072, 0xc0000,
+	 LP_OPTIONS
+	},
+#endif
+#endif
+
+#if(__TGT_AP_FLASH_LOGIC_PAGE_SIZE_N_KB__ == __TGT_AP_FLASH_USE_8KAS6K_PAGE_DIV__)
+	/*
+	 * RDA HEC support, for 8k MLC nand
+	 * use 8K page as 6K page, leave 2K space for HEC
+	 * therefore, chip_size should be three quarter
+	 * and erase_size should be 256*6k = 1536k = 0x180000
+	 * Now, supported NAND
+	 *   - Micron MT29F32xxxDA: ID = 2C 44 xx xx (32Gb use as a 24Gb NAND)
+	 */
+	{"NAND 3GiB 3,3V 8-bit",	0x44, 6144, 3072, 0x180000,
+	 LP_OPTIONS
+	},
+	{"NAND 6GiB 3,3V 8-bit",	0x64, 6144, 6144, 0x180000,
+	 LP_OPTIONS
+	},
+/* //samsung 8k chip
+	{"NAND 3GiB 3,3V 8-bit",	0xd7, 6144, 3072, 0xc0000,
+	 LP_OPTIONS
+	},
+*/
+	{"NAND 3GiB 3,3V 8-bit",	0xd7, 6144, 3072, 0x180000,
+	 LP_OPTIONS
+	},
+#else
+#if(__TGT_AP_FLASH_LOGIC_PAGE_SIZE_N_KB__ == __TGT_AP_FLASH_USE_8KAS4K_PAGE_DIV__)
+	{"NAND 2GiB 3,3V 8-bit",	0x44, 4096, 2048, 0x100000,
+	 LP_OPTIONS
+	},
+	{"NAND 4GiB 3,3V 8-bit",	0x64, 4096, 4096, 0x100000,
+	 LP_OPTIONS
+	},
+/* //samsung 8k chip
+	{"NAND 2GiB 3,3V 8-bit",	0xd7, 4096, 2048, 0x80000,
+	 LP_OPTIONS
+	},
+*/
+	{"NAND 2GiB 3,3V 8-bit",	0xd7, 4096, 2048, 0x100000,
+	 LP_OPTIONS
+	},
+#endif
+#endif
+
+#if(__TGT_AP_FLASH_LOGIC_PAGE_SIZE_N_KB__ == __TGT_AP_FLASH_USE_16KAS8K_PAGE_DIV__)
+	{"NAND 2GiB 3,3V 8-bit",	0xd7, 8192, 2048, 0x200000,
+	 LP_OPTIONS
+	},
+	{"NAND 4GiB 3,3V 8-bit",	0xde, 8192, 4096, 0x200000,
+	 LP_OPTIONS
+	},
+#else
+#if(__TGT_AP_FLASH_LOGIC_PAGE_SIZE_N_KB__ == __TGT_AP_FLASH_USE_16KAS12K_PAGE_DIV__)
+	{"NAND 3GiB 3,3V 8-bit",	0xd7, 12288, 3072, 0x300000,
+	 LP_OPTIONS
+	},
+	{"NAND 6GiB 3,3V 8-bit",	0xde, 12288, 6144, 0x300000,
+	 LP_OPTIONS
+	},
+#endif
+#endif
+#else
+	{"NAND 2GiB 3,3V 8-bit",	0x68, 2048, 2048, 0x80000,
+	 LP_OPTIONS
+	},
+	/*
+	 * RDA HEC support, for 8k MLC nand
+	 * use 8K page as 4K page, leave 4K space for HEC
+	 * therefore, chip_size should be half
+	 * and erase_size should be 256*4k = 1024k = 0x100000
+	 * Now, supported NAND
+	 *   - Micron MT29F32xxxDA: ID = 2C 44 xx xx (32Gb use as a 16Gb NAND)
+	 */
+	{"NAND 2GiB 3,3V 8-bit",	0x44, 4096, 2048, 0x100000,
+	 LP_OPTIONS
+	},
+#endif
+	{"NAND 2GiB 3,3V 8-bit",	0x64, 2048, 2048, 0x80000,
+	 LP_OPTIONS
+	},
+	{"NAND 2GiB 3,3V 8-bit",	0xd7, 2048, 2048, 0x80000,
+	 LP_OPTIONS
+	},
+#else
+	/* 2K page SLC nand */
+	{"NAND 256MiB 3,3V 8-bit",	0xD2, 0, 256, 0, LP_OPTIONS},
+
+	/* 4K page MLC nand */
+	{"NAND 2GiB 3,3V 8-bit",	0x48, 4096, 2048, 0x100000,
+	 LP_OPTIONS
+	},
+	{"NAND 4GiB 3,3V 8-bit",	0x68, 4096, 4096, 0x100000,
+	 LP_OPTIONS
+	},
+	{"NAND 8GiB 3,3V 8-bit",	0x64, 8192, 8192, 0x200000,
+	 LP_OPTIONS
+	},
+	/* 8K page MLC nand */
+	{"NAND 4GiB 3,3V 8-bit",	0x44, 8192, 4096, 0x200000,
+	 LP_OPTIONS
+	},
+	/*block size is 3M, so chipsize is time of 3.*/
+	{"NAND 8GiB 3,3V 8-bit",	0x88, 8192, 8190, 0x300000,
+	 LP_OPTIONS
+	},
+	/* 16K page MLC nand */
+	{"NAND 8GiB 3,3V 8-bit",	0xd3, 16384, 8192, 0x400000,
+	 LP_OPTIONS
+	},
+	/* 16K page MLC nand */
+	{"NAND 8GiB 3,3V 8-bit",	0xd5, 16384, 8192, 0x400000,
+	 LP_OPTIONS
+	},
+	/*This is conflict with a 8k nand*/
+	/* 16K page MLC nand */
+	{"NAND 8GiB 3,3V 8-bit",	0xd7, 16384, 4096, 0x400000,
+	 LP_OPTIONS
+	},
+	/*
+	{"NAND 8GiB 3,3V 8-bit",	0xd7, 7168, 3584, 0x1c0000,
+	 LP_OPTIONS
+	},
+	*/
+	/* 16K page MLC nand */
+	{"NAND 8GiB 3,3V 8-bit",	0xde, 16384, 8192, 0x400000,
+	 LP_OPTIONS
+	},
+	/*
+	{"NAND 8GiB 3,3V 8-bit",	0xde, 14336, 7168, 0x380000,
+	 LP_OPTIONS
+	},
+	*/
+	/* 16K page MLC nand */
+	{"NAND 16GiB 3,3V 8-bit",	0x3A, 16384, 16384, 0x400000,
+	 LP_OPTIONS
+	},
+	/* 16K page MLC nand */
+	{"NAND 16GiB 3,3V 8-bit",	0x3C, 16384, 32768, 0x400000,
+	 LP_OPTIONS
+	},
+#endif /* _TGT_AP_NAND_DISABLE_HEC */
+
+	/* RDA SPI nand support */
+	{"NAND 128MiB 1,8V 4-bit",	0xe1, 2048, 128, 0x20000,
+	 LP_OPTIONS},
+	{"NAND 128MiB 3,3V 4-bit",	0xf1, 2048, 128, 0x20000,
+	 LP_OPTIONS},
+	{"NAND 256MiB 1,8V 4-bit",	0xe2, 2048, 256, 0x20000,
+	 LP_OPTIONS},
+	{"NAND 256MiB 3,3V 4-bit",	0xf2, 2048, 256, 0x20000,
+	 LP_OPTIONS},
+	{"NAND 512MiB 1,8V 4-bit",	0xe4, 2048, 512, 0x20000,
+	 LP_OPTIONS},
+	{"NAND 512MiB 3,3V 4-bit",	0xf4, 2048, 512, 0x20000,
+	 LP_OPTIONS},
+	{"NAND 512MiB 1,8V 4-bit",	0xc4, 4096, 512, 0x40000,
+	 LP_OPTIONS},
+	{"NAND 512MiB 3,3V 4-bit",	0xd4, 4096, 512, 0x40000,
+	 LP_OPTIONS},
 	{NULL,}
 };
 
@@ -177,5 +383,6 @@ const struct nand_manufacturers nand_manuf_ids[] = {
 	{NAND_MFR_HYNIX, "Hynix"},
 	{NAND_MFR_MICRON, "Micron"},
 	{NAND_MFR_AMD, "AMD"},
+	{NAND_MFR_ESMT,"ESMT"},
 	{0x0, "Unknown"}
 };
diff --git a/drivers/mtd/nand/nand_spl_load.c b/drivers/mtd/nand/nand_spl_load.c
index 215459a83c..bd6c988266 100644
--- a/drivers/mtd/nand/nand_spl_load.c
+++ b/drivers/mtd/nand/nand_spl_load.c
@@ -21,6 +21,10 @@
 #include <common.h>
 #include <nand.h>
 
+#ifdef CONFIG_SPL_CHECK_IMAGE
+int check_uimage(unsigned int *buf);
+#endif
+
 /*
  * The main entry for NAND booting. It's necessary that SDRAM is already
  * configured and available since this code loads the main U-Boot image
@@ -28,23 +32,49 @@
  */
 void nand_boot(void)
 {
+	int ret = 0;
+
 	__attribute__((noreturn)) void (*uboot)(void);
 
 	/*
 	 * Load U-Boot image from NAND into RAM
 	 */
-	nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+	ret = nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
 			CONFIG_SYS_NAND_U_BOOT_SIZE,
 			(void *)CONFIG_SYS_NAND_U_BOOT_DST);
 
+	if (0 != ret){
+		printf("Read u_boot from nand failed. \n");
+		return;
+	}
+
 #ifdef CONFIG_NAND_ENV_DST
-	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+	ret = nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
 			(void *)CONFIG_NAND_ENV_DST);
+	if (0 != ret){
+		printf("Read env from nand failed . \n");
+		return;
+	}
 
 #ifdef CONFIG_ENV_OFFSET_REDUND
-	nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
+	ret = nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
 			(void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
+	if (0 != ret){
+		printf("Read redund from nand failed . \n");
+		return;
+	}
+#endif
+#endif
+
+#ifdef CONFIG_SPL_CHECK_IMAGE
+	if (check_uimage((unsigned int*)CONFIG_SYS_NAND_U_BOOT_DST)) {
+		printf("Nand boot failed:DDR error or nand data error!\n");
+#ifdef CONFIG_RDA_FPGA
+		nand_dirty_block_erase(0);
 #endif
+		printf("please try to load uboot.img or reset!\n");
+		return;
+	}
 #endif
 
 	/*
diff --git a/drivers/mtd/nand/nand_spl_simple.c b/drivers/mtd/nand/nand_spl_simple.c
index 4a4d02f4c8..33795db32f 100644
--- a/drivers/mtd/nand/nand_spl_simple.c
+++ b/drivers/mtd/nand/nand_spl_simple.c
@@ -22,11 +22,13 @@
 #include <nand.h>
 #include <asm/io.h>
 #include <linux/mtd/nand_ecc.h>
+#include <mtd/nand/rda_nand.h>
 
-static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
 static nand_info_t mtd;
 static struct nand_chip nand_chip;
 
+#ifndef CONFIG_NAND_RDA
+static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
 #define ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
 					CONFIG_SYS_NAND_ECCSIZE)
 #define ECCTOTAL	(ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
@@ -219,40 +221,178 @@ static int nand_read_page(int block, int page, void *dst)
 }
 #endif
 
-int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
+#else
+#define MAX_OOBSIZE 	32
+static int nand_is_bad_block(int block)
+{
+	struct nand_chip *this = mtd.priv;
+	int page = block *  (mtd.erasesize / mtd.writesize);
+	static u_char oob[MAX_OOBSIZE];
+
+	this->cmdfunc(&mtd, NAND_CMD_READOOB, 0, page);
+	this->read_buf(&mtd, oob, 32);
+
+	/*
+	 * Read one byte (or two if it's a 16 bit chip).
+	 */
+	if (this->options & NAND_BUSWIDTH_16) {
+		unsigned short oob_w = (oob[1] << 8) | oob[0];
+		if (oob_w != 0xffff)
+			return 1;
+	} else {
+		if (oob[0] != 0xff)
+			return 1;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_RDA_FPGA
+void nand_dirty_block_erase(int page)
+{
+	struct nand_chip *this = mtd.priv;
+	/* Send commands to erase a block */
+	this->cmdfunc(&mtd, NAND_CMD_ERASE1, -1, page);
+	this->cmdfunc(&mtd, NAND_CMD_ERASE2, -1, -1);
+}
+#endif
+
+static int nand_read_page(int block, int page, uchar *dst)
+{
+	struct nand_chip *this = mtd.priv;
+	unsigned int page_cnt = mtd.erasesize / mtd.writesize;
+	int page_addr = page + block * page_cnt;
+
+	this->cmdfunc(&mtd, NAND_CMD_READ0, 0, page_addr);
+	this->read_buf(&mtd, dst, mtd.writesize);
+
+	return 0;
+}
+#endif //CONFIG_NAND_RDA
+
+int nand_spl_read_skip_bad(uint64_t offs, uint64_t size, u8 *dst,
+					u32 *skip_blocks)
 {
 	unsigned int block, lastblock;
 	unsigned int page;
+	unsigned int page_count = 0, page_num;
+	unsigned int  bad = 0;
+	unsigned int page_offset = offs % mtd.writesize;
+	unsigned int data_valid_len = mtd.writesize - page_offset;
+
+	if (page_offset) {/* u-boot is not page aligned */
+		block = offs / mtd.erasesize;
+		page = (offs / mtd.writesize) % (mtd.erasesize / mtd.writesize);
+		do {
+			if (!nand_is_bad_block(block)) {
+				nand_read_page(block, page, dst);
+				memcpy(dst, dst + page_offset, data_valid_len);
+				dst += data_valid_len;
+				offs += data_valid_len;
+				size -= data_valid_len;
+			} else {
+				bad++;
+				block++;
+			}
+			page_offset = offs % mtd.writesize;
+		} while(bad < 16 && page_offset);
+	}
 
 	/*
 	 * offs has to be aligned to a page address!
 	 */
-	block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
-	lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
-	page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
+	block = offs / mtd.erasesize;
+	lastblock = (offs + size + mtd.erasesize - 1) / mtd.erasesize;
+	page = (offs / mtd.writesize) % (mtd.erasesize / mtd.writesize);
+	page_num = (size + mtd.writesize - 1) / mtd.writesize;
 
-	while (block <= lastblock) {
+	while (block < lastblock) {
 		if (!nand_is_bad_block(block)) {
 			/*
 			 * Skip bad blocks
 			 */
-			while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
+			while (page < (mtd.erasesize / mtd.writesize)) {
 				nand_read_page(block, page, dst);
-				dst += CONFIG_SYS_NAND_PAGE_SIZE;
+				dst += mtd.writesize;
 				page++;
+				page_count++;
+				if(page_count >= page_num)
+					goto exit;
 			}
-
 			page = 0;
 		} else {
+			bad++;
+			if (bad >= 16) {
+				*skip_blocks = bad;
+				printf("too many bad blocks\n");
+				return -1;
+			}
 			lastblock++;
 		}
 
 		block++;
 	}
+exit:
+
+	*skip_blocks = bad;
+
+	if (0 == page_count){
+		printf("Error:read 0 page from nand \n");
+		return -1;
+	}
 
 	return 0;
 }
 
+int nand_spl_load_image(uint64_t offs, uint64_t size, void *dst)
+{
+	u32 bad_blocks = 0;
+	struct rda_nand_info *info = nand_chip.priv;
+
+	printf("nand_spl_load_image: offs = 0x%llx, size = 0x%llx \n", offs, size);
+
+	offs = ((offs - CONFIG_MTD_PTBL_SIZE) * info->spl_adjust_ratio) / 2 + CONFIG_MTD_PTBL_SIZE;
+	//size -= (CONFIG_SPL_MAX_SIZE * info->spl_adjust_ratio) / 2 - CONFIG_SPL_MAX_SIZE;
+
+	printf("nand_spl_load_image,adjust: offs = 0x%llx, size = 0x%llx \n", offs, size);
+
+	if(nand_spl_read_skip_bad(offs, size, dst, &bad_blocks)) {
+		printf("fatal error, cannot load bootload....\n");
+		return -1;
+	}
+
+	if (bad_blocks > 0) {
+		printf("spl, there are %d bad block in bootloader partition",
+			bad_blocks);
+	}
+	return 0;
+}
+
+void nand_spl_mtd_info(u32 *page_size, u32 *block_size)
+{
+	*page_size = mtd.writesize;
+	*block_size = mtd.erasesize;
+}
+
+static int nand_sanity_check(void)
+{
+	int ret = 0;
+
+#if defined(NAND_PAGE_SIZE) && defined(NAND_BLOCK_SIZE)
+	if (mtd.writesize != NAND_PAGE_SIZE)
+		ret = -1;
+	if (mtd.erasesize != NAND_BLOCK_SIZE)
+		ret = -1;
+	if (ret) {
+		printf("nand parameters error: real pagesize: %d, blocksize %d\n",
+				mtd.writesize, mtd.erasesize);
+		printf("but We expect pagesize: %d, blocksize %d\n",
+				NAND_PAGE_SIZE, NAND_BLOCK_SIZE);
+		printf("please check device/rda/.../customer.mk\n");
+	}
+#endif
+	return ret;
+}
 /* nand_init() - initialize data to make nand usable by SPL */
 void nand_init(void)
 {
@@ -264,15 +404,15 @@ void nand_init(void)
 		(void  __iomem *)CONFIG_SYS_NAND_BASE;
 	board_nand_init(&nand_chip);
 
-#ifdef CONFIG_SPL_NAND_SOFTECC
-	if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
-		nand_chip.ecc.calculate = nand_calculate_ecc;
-		nand_chip.ecc.correct = nand_correct_data;
-	}
-#endif
+	if (nand_chip.init_size)
+		nand_chip.init_size(&mtd, &nand_chip, NULL);
 
 	if (nand_chip.select_chip)
 		nand_chip.select_chip(&mtd, 0);
+
+	if(nand_sanity_check()) {
+		for(;;);
+	}
 }
 
 /* Unselect after operation */
diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c
index 60c778e637..8581a3a1a9 100644
--- a/drivers/mtd/nand/nand_util.c
+++ b/drivers/mtd/nand/nand_util.c
@@ -49,14 +49,16 @@
 #include <linux/mtd/mtd.h>
 #include <nand.h>
 #include <jffs2/jffs2.h>
+#include <mmc/sparse.h>
 
 typedef struct erase_info erase_info_t;
-typedef struct mtd_info	  mtd_info_t;
+typedef struct mtd_info mtd_info_t;
 
 /* support only for native endian JFFS2 */
 #define cpu_to_je16(x) (x)
 #define cpu_to_je32(x) (x)
 
+extern void udc_irq(void);
 /**
  * nand_erase_opts: - erase NAND flash with support for various options
  *		      (jffs2 formating)
@@ -68,11 +70,11 @@ typedef struct mtd_info	  mtd_info_t;
  * This code is ported from flash_eraseall.c from Linux mtd utils by
  * Arcom Control System Ltd.
  */
-int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
+int nand_erase_opts(nand_info_t * meminfo, const nand_erase_options_t * opts)
 {
 	struct jffs2_unknown_node cleanmarker;
 	erase_info_t erase;
-	unsigned long erase_length, erased_length; /* in blocks */
+	unsigned long erase_length, erased_length;	/* in blocks */
 	int bbtest = 1;
 	int result;
 	int percent_complete = -1;
@@ -80,22 +82,29 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
 	struct mtd_oob_ops oob_opts;
 	struct nand_chip *chip = meminfo->priv;
 
-	if ((opts->offset & (meminfo->writesize - 1)) != 0) {
-		printf("Attempt to erase non page aligned data\n");
-		return -1;
+	if (chip->page_shift == 0) {
+		if (mtd_mod_by_ws(opts->offset, meminfo) != 0){
+			printf("Attempt to erase non page aligned data\n");
+			return -1;
+		}
+	} else {
+		if ((opts->offset & (meminfo->writesize - 1)) != 0) {
+			printf("Attempt to erase non page aligned data\n");
+			return -1;
+		}
 	}
 
 	memset(&erase, 0, sizeof(erase));
 	memset(&oob_opts, 0, sizeof(oob_opts));
 
 	erase.mtd = meminfo;
-	erase.len  = meminfo->erasesize;
+	erase.len = meminfo->erasesize;
 	erase.addr = opts->offset;
 	erase_length = lldiv(opts->length + meminfo->erasesize - 1,
 			     meminfo->erasesize);
 
-	cleanmarker.magic = cpu_to_je16 (JFFS2_MAGIC_BITMASK);
-	cleanmarker.nodetype = cpu_to_je16 (JFFS2_NODETYPE_CLEANMARKER);
+	cleanmarker.magic = cpu_to_je16(JFFS2_MAGIC_BITMASK);
+	cleanmarker.nodetype = cpu_to_je16(JFFS2_NODETYPE_CLEANMARKER);
 	cleanmarker.totlen = cpu_to_je32(8);
 
 	/* scrub option allows to erase badblock. To prevent internal
@@ -115,10 +124,10 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
 	}
 
 	for (erased_length = 0;
-	     erased_length < erase_length;
-	     erase.addr += meminfo->erasesize) {
+	     erased_length < erase_length; erase.addr += meminfo->erasesize) {
 
-		WATCHDOG_RESET ();
+		WATCHDOG_RESET();
+		udc_irq();
 
 		if (!opts->scrub && bbtest) {
 			int ret = meminfo->block_isbad(meminfo, erase.addr);
@@ -136,8 +145,7 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
 
 			} else if (ret < 0) {
 				printf("\n%s: MTD get bad block failed: %d\n",
-				       mtd_device,
-				       ret);
+				       mtd_device, ret);
 				return -1;
 			}
 		}
@@ -155,13 +163,12 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
 		if (opts->jffs2 && chip->ecc.layout->oobavail >= 8) {
 			chip->ops.ooblen = 8;
 			chip->ops.datbuf = NULL;
-			chip->ops.oobbuf = (uint8_t *)&cleanmarker;
+			chip->ops.oobbuf = (uint8_t *) & cleanmarker;
 			chip->ops.ooboffs = 0;
 			chip->ops.mode = MTD_OOB_AUTO;
 
 			result = meminfo->write_oob(meminfo,
-			                            erase.addr,
-			                            &chip->ops);
+						    erase.addr, &chip->ops);
 			if (result != 0) {
 				printf("\n%s: MTD writeoob failure: %d\n",
 				       mtd_device, result);
@@ -183,12 +190,13 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
 			if (percent != percent_complete) {
 				percent_complete = percent;
 
-				printf("\rErasing at 0x%llx -- %3d%% complete.",
+				printf("\rErasing at 0x%llx -- %3d%% complete.\n",
 				       erase.addr, percent);
 
 				if (opts->jffs2 && result == 0)
-					printf(" Cleanmarker written at 0x%llx.",
-					       erase.addr);
+					printf
+					    (" Cleanmarker written at 0x%llx.",
+					     erase.addr);
 			}
 		}
 	}
@@ -244,8 +252,7 @@ int nand_lock(struct mtd_info *mtd, int tight)
 	chip->select_chip(mtd, 0);
 
 	chip->cmdfunc(mtd,
-		      (tight ? NAND_CMD_LOCK_TIGHT : NAND_CMD_LOCK),
-		      -1, -1);
+		      (tight ? NAND_CMD_LOCK_TIGHT : NAND_CMD_LOCK), -1, -1);
 
 	/* call wait ready function */
 	status = chip->waitfunc(mtd, chip);
@@ -283,27 +290,42 @@ int nand_get_lock_status(struct mtd_info *mtd, loff_t offset)
 	struct nand_chip *chip = mtd->priv;
 
 	/* select the NAND device */
-	chipnr = (int)(offset >> chip->chip_shift);
+	if (chip->chip_shift == 0)
+		chipnr = mtd_div_by_cs(offset, mtd);
+	else
+		chipnr = (int)(offset >> chip->chip_shift);
+
 	chip->select_chip(mtd, chipnr);
 
+	if (chip->page_shift == 0) {
+		if (mtd_mod_by_ws(offset, mtd) != 0){
+			printf("nand_get_lock_status: "
+		       	"Start address must be beginning of " "nand page!\n");
+			ret = -1;
+			goto out;
+		}
 
-	if ((offset & (mtd->writesize - 1)) != 0) {
-		printf ("nand_get_lock_status: "
-			"Start address must be beginning of "
-			"nand page!\n");
-		ret = -1;
-		goto out;
+		/* check the Lock Status */
+		page = mtd_div_by_ws(offset, mtd);
+	} else {
+		if ((offset & (mtd->writesize - 1)) != 0) {
+			printf("nand_get_lock_status: "
+		       	"Start address must be beginning of " "nand page!\n");
+			ret = -1;
+			goto out;
+		}
+
+		/* check the Lock Status */
+		page = (int)(offset >> chip->page_shift);
 	}
 
-	/* check the Lock Status */
-	page = (int)(offset >> chip->page_shift);
 	chip->cmdfunc(mtd, NAND_CMD_LOCK_STATUS, -1, page & chip->pagemask);
 
 	ret = chip->read_byte(mtd) & (NAND_LOCK_STATUS_TIGHT
-					  | NAND_LOCK_STATUS_LOCK
-					  | NAND_LOCK_STATUS_UNLOCK);
+				      | NAND_LOCK_STATUS_LOCK
+				      | NAND_LOCK_STATUS_UNLOCK);
 
- out:
+out:
 	/* de-select the NAND device */
 	chip->select_chip(mtd, -1);
 	return ret;
@@ -327,33 +349,53 @@ int nand_unlock(struct mtd_info *mtd, ulong start, ulong length)
 	int status;
 	int page;
 	struct nand_chip *chip = mtd->priv;
-	printf ("nand_unlock: start: %08x, length: %d!\n",
-		(int)start, (int)length);
+	printf("nand_unlock: start: %08x, length: %d!\n",
+	       (int)start, (int)length);
 
 	/* select the NAND device */
-	chipnr = (int)(start >> chip->chip_shift);
+	if (chip->chip_shift == 0)
+		chipnr = mtd_div_by_cs(start, mtd);
+	else
+		chipnr = (int)(start >> chip->chip_shift);
+
 	chip->select_chip(mtd, chipnr);
 
 	/* check the WP bit */
 	chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 	if (!(chip->read_byte(mtd) & NAND_STATUS_WP)) {
-		printf ("nand_unlock: Device is write protected!\n");
+		printf("nand_unlock: Device is write protected!\n");
 		ret = -1;
 		goto out;
 	}
 
-	if ((start & (mtd->erasesize - 1)) != 0) {
-		printf ("nand_unlock: Start address must be beginning of "
-			"nand block!\n");
-		ret = -1;
-		goto out;
-	}
+	if (chip->phy_erase_shift == 0) {
+		if (mtd_mod_by_eb(start, mtd) != 0) {
+			printf("nand_unlock: Start address must be beginning of "
+		       	"nand block!\n");
+			ret = -1;
+			goto out;
+		}
 
-	if (length == 0 || (length & (mtd->erasesize - 1)) != 0) {
-		printf ("nand_unlock: Length must be a multiple of nand block "
-			"size %08x!\n", mtd->erasesize);
-		ret = -1;
-		goto out;
+		if (length == 0 || mtd_mod_by_eb(length, mtd) != 0) {
+			printf("nand_unlock: Length must be a multiple of nand block "
+		       	"size %08x!\n", mtd->erasesize);
+			ret = -1;
+			goto out;
+		}
+	} else {
+		if ((start & (mtd->erasesize - 1)) != 0) {
+			printf("nand_unlock: Start address must be beginning of "
+		       	"nand block!\n");
+			ret = -1;
+			goto out;
+		}
+
+		if (length == 0 || (length & (mtd->erasesize - 1)) != 0) {
+			printf("nand_unlock: Length must be a multiple of nand block "
+		       	"size %08x!\n", mtd->erasesize);
+			ret = -1;
+			goto out;
+		}
 	}
 
 	/*
@@ -363,11 +405,19 @@ int nand_unlock(struct mtd_info *mtd, ulong start, ulong length)
 	length -= mtd->erasesize;
 
 	/* submit address of first page to unlock */
-	page = (int)(start >> chip->page_shift);
+	if (chip->page_shift == 0)
+		page = mtd_div_by_ws(start, mtd);
+	else
+		page = (int)(start >> chip->page_shift);
+
 	chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
 
 	/* submit ADDRESS of LAST page to unlock */
-	page += (int)(length >> chip->page_shift);
+	if (chip->page_shift == 0)
+		page += mtd_div_by_ws(length, mtd);
+	else
+		page += (int)(length >> chip->page_shift);
+
 	chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, page & chip->pagemask);
 
 	/* call wait ready function */
@@ -379,7 +429,7 @@ int nand_unlock(struct mtd_info *mtd, ulong start, ulong length)
 		goto out;
 	}
 
- out:
+out:
 	/* de-select the NAND device */
 	chip->select_chip(mtd, -1);
 	return ret;
@@ -392,27 +442,39 @@ int nand_unlock(struct mtd_info *mtd, ulong start, ulong length)
  * Check if there are any bad blocks, and whether length including bad
  * blocks fits into device
  *
- * @param nand NAND device
- * @param offset offset in flash
- * @param length image length
+ * @param nand		NAND device
+ * @param offset	offset in flash
+ * @param length	image length
+ * @param max_limit	maximun access offset in flash
  * @return 0 if the image fits and there are no bad blocks
  *         1 if the image fits, but there are bad blocks
  *        -1 if the image does not fit
  */
-static int check_skip_len(nand_info_t *nand, loff_t offset, size_t length)
+static int check_skip_len(nand_info_t * nand, loff_t offset, size_t length,
+			  loff_t max_limit)
 {
 	size_t len_excl_bad = 0;
 	int ret = 0;
+	struct nand_chip *chip = nand->priv;
+
+	if (max_limit == 0)
+		max_limit = nand->size;
 
 	while (len_excl_bad < length) {
 		size_t block_len, block_off;
 		loff_t block_start;
 
-		if (offset >= nand->size)
+		if (offset >= max_limit)
 			return -1;
 
-		block_start = offset & ~(loff_t)(nand->erasesize - 1);
-		block_off = offset & (nand->erasesize - 1);
+		if (chip->phys_erase_shift == 0) {
+			block_start = mtd_div_by_eb(offset, nand) * nand->erasesize;
+			block_off = mtd_mod_by_eb(offset, nand);
+		} else {
+			block_start = offset & ~(loff_t) (nand->erasesize - 1);
+			block_off = offset & (nand->erasesize - 1);
+		}
+
 		block_len = nand->erasesize - block_off;
 
 		if (!nand_block_isbad(nand, block_start))
@@ -427,8 +489,8 @@ static int check_skip_len(nand_info_t *nand, loff_t offset, size_t length)
 }
 
 #ifdef CONFIG_CMD_NAND_TRIMFFS
-static size_t drop_ffs(const nand_info_t *nand, const u_char *buf,
-			const size_t *len)
+static size_t drop_ffs(const nand_info_t * nand, const u_char * buf,
+		       const size_t * len)
 {
 	size_t i, l = *len;
 
@@ -439,7 +501,7 @@ static size_t drop_ffs(const nand_info_t *nand, const u_char *buf,
 	/* The resulting length must be aligned to the minimum flash I/O size */
 	l = i + 1;
 	l = (l + nand->writesize - 1) / nand->writesize;
-	l *=  nand->writesize;
+	l *= nand->writesize;
 
 	/*
 	 * since the input length may be unaligned, prevent access past the end
@@ -450,7 +512,7 @@ static size_t drop_ffs(const nand_info_t *nand, const u_char *buf,
 #endif
 
 /**
- * nand_write_skip_bad:
+ * nand_write_skip_bad_new:
  *
  * Write image to NAND flash.
  * Blocks that are marked bad are skipped and the is written to the next
@@ -460,18 +522,23 @@ static size_t drop_ffs(const nand_info_t *nand, const u_char *buf,
  * @param nand  	NAND device
  * @param offset	offset in flash
  * @param length	buffer length
- * @param buffer        buffer to read from
+ * @param max_limit	maximun access offset in flash
+ * @param buffer	buffer to read from
  * @param flags		flags modifying the behaviour of the write to NAND
+ * @skip_blocks		the blocks has been skiped in this write
  * @return		0 in case of success
  */
-int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
-			u_char *buffer, int flags)
+int nand_write_skip_bad_new(nand_info_t * nand, loff_t offset, size_t * length,
+			    loff_t max_limit, u_char * buffer, int flags,
+			    u32 * skip_blocks)
 {
 	int rval = 0, blocksize;
 	size_t left_to_write = *length;
 	u_char *p_buffer = buffer;
 	int need_skip;
+	struct nand_chip *chip = nand->priv;
 
+	*skip_blocks = 0;
 #ifdef CONFIG_CMD_NAND_YAFFS
 	if (flags & WITH_YAFFS_OOB) {
 		if (flags & ~WITH_YAFFS_OOB)
@@ -481,8 +548,8 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 		pages = nand->erasesize / nand->writesize;
 		blocksize = (pages * nand->oobsize) + nand->erasesize;
 		if (*length % (nand->writesize + nand->oobsize)) {
-			printf ("Attempt to write incomplete page"
-				" in yaffs mode\n");
+			printf("Attempt to write incomplete page"
+			       " in yaffs mode\n");
 			return -EINVAL;
 		}
 	} else
@@ -502,41 +569,61 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 	 * you should only start a block skipping access at a
 	 * partition boundary).  So don't try to handle that.
 	 */
-	if ((offset & (nand->writesize - 1)) != 0) {
-		printf ("Attempt to write non page aligned data\n");
-		*length = 0;
-		return -EINVAL;
+	if (chip->page_shift == 0) {
+		if (mtd_mod_by_ws(offset, nand) != 0) {
+			printf("Attempt to write non page aligned data\n");
+			*length = 0;
+			return -EINVAL;
+		}
+	} else {
+		if ((offset & (nand->writesize - 1)) != 0) {
+			printf("Attempt to write non page aligned data\n");
+			*length = 0;
+			return -EINVAL;
+		}
 	}
 
-	need_skip = check_skip_len(nand, offset, *length);
+	need_skip = check_skip_len(nand, offset, *length, max_limit);
 	if (need_skip < 0) {
-		printf ("Attempt to write outside the flash area\n");
+		printf("Attempt to write outside the flash area\n");
 		*length = 0;
 		return -EINVAL;
 	}
 
-	if (!need_skip && !(flags & WITH_DROP_FFS)) {
-		rval = nand_write (nand, offset, length, buffer);
+	if (!need_skip && !(flags & WITH_DROP_FFS) && !(flags & WITH_YAFFS_OOB)) {
+		rval = nand_write(nand, offset, length, buffer);
 		if (rval == 0)
 			return 0;
 
 		*length = 0;
-		printf ("NAND write to offset %llx failed %d\n",
-			offset, rval);
+		printf("NAND write to offset %llx failed %d\n", offset, rval);
 		return rval;
 	}
 
 	while (left_to_write > 0) {
-		size_t block_offset = offset & (nand->erasesize - 1);
-		size_t write_size, truncated_write_size;
+		size_t write_size, truncated_write_size, block_offset;
 
-		WATCHDOG_RESET ();
+		WATCHDOG_RESET();
 
-		if (nand_block_isbad (nand, offset & ~(nand->erasesize - 1))) {
-			printf ("Skip bad block 0x%08llx\n",
-				offset & ~(nand->erasesize - 1));
-			offset += nand->erasesize - block_offset;
-			continue;
+		if (chip->phys_erase_shift == 0) {
+			block_offset = mtd_mod_by_eb(offset, nand);
+
+			if (nand_block_isbad(nand, mtd_div_by_eb(offset, nand) * nand->erasesize)) {
+				printf("Skip bad block 0x%08llx\n",
+					(loff_t)mtd_div_by_eb(offset, nand) * nand->erasesize);
+				offset += nand->erasesize - block_offset;
+				*skip_blocks += 1;
+				continue;
+			}
+		}else {
+			block_offset = offset & (nand->erasesize - 1);
+
+			if (nand_block_isbad(nand, offset & ~(nand->erasesize - 1))) {
+				printf("Skip bad block 0x%08llx\n", offset & ~(nand->erasesize - 1));
+				offset += nand->erasesize - block_offset;
+				*skip_blocks += 1;
+				continue;
+			}
 		}
 
 		if (left_to_write < (blocksize - block_offset))
@@ -564,32 +651,31 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 				ops.oobbuf = ops.datbuf + pagesize;
 
 				rval = nand->write_oob(nand, offset, &ops);
-				if (!rval)
+				if (rval != 0)
 					break;
 
 				offset += pagesize;
 				p_buffer += pagesize_oob;
 			}
-		}
-		else
+		} else
 #endif
 		{
 			truncated_write_size = write_size;
 #ifdef CONFIG_CMD_NAND_TRIMFFS
 			if (flags & WITH_DROP_FFS)
 				truncated_write_size = drop_ffs(nand, p_buffer,
-						&write_size);
+								&write_size);
 #endif
 
 			rval = nand_write(nand, offset, &truncated_write_size,
-					p_buffer);
+					  p_buffer);
 			offset += write_size;
 			p_buffer += write_size;
 		}
 
 		if (rval != 0) {
-			printf ("NAND write to offset %llx failed %d\n",
-				offset, rval);
+			printf("NAND write to offset %llx failed %d\n",
+			       offset, rval);
 			*length -= left_to_write;
 			return rval;
 		}
@@ -600,8 +686,358 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 	return 0;
 }
 
+#define SPARSE_HEADER_MAJOR_VER 1
+#define SECTOR_SIZE     512
+struct rnftl_oobinfo_t {
+	int16_t sect;
+	int16_t ec;		//00, Bad
+	int16_t vtblk;		//-1 , free,-2~-10, Snapshot
+	unsigned timestamp:15;
+	unsigned status_page:1;
+	int8_t maigic[4];
+	uint8_t reserved[2];
+};
+
+static int sparse_parse(unsigned char *buffer, sparse_header_t ** header,
+			loff_t max_limit)
+{
+	sparse_header_t *pheader;
+
+	pheader = (sparse_header_t *) buffer;
+	if (pheader->magic != SPARSE_HEADER_MAGIC) {
+		printf("sparse: bad magic.\n");
+		return -1;
+	}
+
+	if (((u64) pheader->total_blks * pheader->blk_sz) > max_limit) {
+		printf("sparse: section size %08llx MB limit: exceeded\n",
+		       max_limit / (1024 * 1024));
+		return -1;
+	}
+
+	if ((pheader->major_version != SPARSE_HEADER_MAJOR_VER) ||
+	    (pheader->file_hdr_sz != sizeof(sparse_header_t)) ||
+	    (pheader->chunk_hdr_sz != sizeof(chunk_header_t))) {
+		printf("sparse: incompatible format\n");
+		return -1;
+	}
+	*header = pheader;
+	return 0;
+}
+
+static int trunk_parse(unsigned char *buffer, sparse_header_t * sparse_header,
+		       chunk_header_t ** header)
+{
+	chunk_header_t *pheader;
+
+	pheader = (chunk_header_t *) buffer;
+	if (pheader->chunk_type != CHUNK_TYPE_RAW &&
+	    pheader->chunk_type != CHUNK_TYPE_DONT_CARE) {
+		printf("chunk: unknow chunk type:0x%x.\n", pheader->chunk_type);
+		return -1;
+	}
+
+	if (pheader->chunk_sz == 0) {
+		printf("chunk: chunk_sz = 0.\n");
+		return -1;
+	}
+
+	if (pheader->chunk_type == CHUNK_TYPE_RAW &&
+	    pheader->total_sz !=
+	    (u64) pheader->chunk_sz * sparse_header->blk_sz +
+	    sizeof(chunk_header_t)) {
+		printf
+		    ("chunk: total_sz error.total_size = 0x%x,chunk_sz = 0x%x.\n",
+		     pheader->total_sz, pheader->chunk_sz);
+		return -1;
+	}
+
+	if (pheader->chunk_type == CHUNK_TYPE_DONT_CARE &&
+	    pheader->total_sz != sizeof(chunk_header_t)) {
+		printf
+		    ("chunk: total_sz error.total_size = 0x%x,chunk_sz = 0x%x.\n",
+		     pheader->total_sz, pheader->chunk_sz);
+		return -1;
+	}
+	*header = pheader;
+	return 0;
+}
+
+static int nand_write_nftl(nand_info_t * nand, loff_t offset,
+			   unsigned char *buffer, int16_t vt_block,
+			   int16_t vt_sect, uint16_t timestamp)
+{
+	int rval;
+	struct mtd_oob_ops ops;
+	struct rnftl_oobinfo_t nftl_oob;
+
+	memset(&ops, 0, sizeof(ops));
+	memset(&nftl_oob, 0, sizeof(nftl_oob));
+	// ops
+	ops.len = nand->writesize;
+	ops.ooblen = sizeof(nftl_oob);
+	ops.mode = MTD_OOB_AUTO;
+	ops.ooboffs = 2;
+	ops.oobbuf = (uint8_t *) & nftl_oob;
+	ops.datbuf = buffer;
+	//nftl_oob
+	nftl_oob.ec = 0;
+	nftl_oob.status_page = 1;
+	memcpy(&(nftl_oob.maigic), "rda", 3);
+	nftl_oob.sect = vt_sect;
+	nftl_oob.vtblk = vt_block;
+	nftl_oob.timestamp = timestamp;
+
+	rval = nand->write_oob(nand, offset, &ops);
+	if (rval != 0) {
+		printf("write_oob fail, rval = %d.\n", rval);
+		return -1;
+	}
+	return 0;
+}
+
+int nand_write_unsparse(nand_info_t * nand, loff_t offset, size_t * length,
+			loff_t max_limit, unsigned char *buffer, int flags,
+			u32 * skip_blocks)
+{
+	int rval = 0;
+	u32 trunk_nr;
+	u64 chunk_len = 0;
+	u64 outlen = 0;
+	loff_t base_offset;
+	uint8_t *page_buffer = NULL;
+	int16_t page_len = 0;
+	int16_t page_per_block;
+	int16_t vt_block = 0;
+	int16_t vt_sect = 0;
+	uint16_t timestamp = 0;
+	sparse_header_t *sparse_h;
+	struct nand_chip *chip = nand->priv;
+
+	printf("nand_write_unsparse begin.\n");
+	printf("offset:0x%08llx.\n", offset);
+	printf("max_limit:0x%08llx.\n", max_limit);
+	printf("flags:0x%x.\n", *length);
+	printf("flags:0x%x.\n", flags);
+	printf("skip_blocks:0x%x.\n", *skip_blocks);
+	base_offset = offset;
+	page_per_block = (nand->erasesize / nand->writesize);
+	rval = sparse_parse(buffer, &sparse_h, max_limit);
+	if (rval) {
+		printf("nand_unsprase: sparse_parse fail.\n");
+		return -1;
+	}
+	buffer += sizeof(sparse_header_t);
+	(*length) -= sizeof(sparse_header_t);
+	page_buffer = malloc(nand->writesize);
+	for (trunk_nr = 0; trunk_nr < sparse_h->total_chunks; trunk_nr++) {
+		chunk_header_t *chunk_h;
+
+		rval = trunk_parse(buffer, sparse_h, &chunk_h);
+		if (rval) {
+			printf("nand_unsprase: trunk_parse fail.\n");
+			free(page_buffer);
+			return -1;
+		}
+		/*
+		   printf("trunk:0x%x,0x%x,0x%x.\n",
+		   trunk_nr,chunk_h->chunk_type,chunk_h->chunk_sz);
+		 */
+		buffer += sizeof(chunk_header_t);
+		(*length) -= sizeof(chunk_header_t);
+		chunk_len = (u64) chunk_h->chunk_sz * (u64) sparse_h->blk_sz;
+		while (chunk_len > 0) {
+			uint8_t *data_buff = page_buffer;
+			if (chunk_h->chunk_type == CHUNK_TYPE_RAW) {
+				memcpy(data_buff + page_len, buffer,
+				       SECTOR_SIZE);
+				buffer += SECTOR_SIZE;
+				(*length) -= SECTOR_SIZE;
+				page_len += SECTOR_SIZE;
+				chunk_len -= SECTOR_SIZE;
+
+			} else if (chunk_h->chunk_type == CHUNK_TYPE_DONT_CARE) {
+				if(chunk_len >= (nand->writesize - page_len))
+					chunk_len -= (nand->writesize - page_len);
+				else
+					chunk_len = 0;
+				if (page_len) {
+					printf("write spare data.page_len = 0x%x.\n",
+					     page_len);
+					/* memset(data_buff + page_len, 0,nand->writesize - page_len); */
+				} else {
+					/* memset(data_buff, 0,nand->writesize); */
+					data_buff = NULL;
+				}
+				page_len = nand->writesize;
+			} else {
+				printf("nand_unsprase:"
+					"Unknow Trunk type: 0x%x.\n",
+					chunk_h->chunk_type);
+				break;
+			}
+			if (page_len == nand->writesize) {
+				/* skip bad block. */
+				do {
+					size_t block_offset;
+					if (chip->phys_erase_shift == 0) {
+						block_offset = mtd_mod_by_eb(offset, nand);
+						if (nand_block_isbad(nand, mtd_div_by_eb(offset, nand) * nand->erasesize)) {
+							printf("nand_unsprase:Skip bad block 0x%08llx.\n",
+									(loff_t)mtd_div_by_eb(offset, nand) * nand->erasesize);
+							offset += nand->erasesize -block_offset;
+							(*skip_blocks)++;
+							continue;
+						} else {
+							break;
+						}
+					} else {
+						block_offset = offset & (nand->erasesize - 1);
+						if (nand_block_isbad(nand,offset & ~(nand->erasesize - 1))) {
+							printf("nand_unsprase:Skip bad block 0x%08llx.\n",
+									offset & ~(nand->erasesize -1));
+							offset += nand->erasesize -block_offset;
+							(*skip_blocks)++;
+							continue;
+						} else {
+							break;
+						}
+					}
+				} while (1);
+
+				if (offset + nand->writesize >
+				    base_offset + max_limit) {
+					printf("nand_unsprase:"
+					       "exceed.section max_limit:0x%08llx,offset:0x%08llx.\n",
+					       max_limit,
+					       offset + nand->writesize -
+					       base_offset);
+					free(page_buffer);
+					return -1;
+				}
+				rval = nand_write_nftl(nand, offset, data_buff,
+						       vt_block, vt_sect,
+						       timestamp);
+				if (rval) {
+					printf("nand_unsprase: nand_write_nftl fail.\n");
+					free(page_buffer);
+					return -1;
+				}
+				page_len = 0;
+				if (vt_sect + 1 == page_per_block) {
+					vt_block++;
+					vt_sect = 0;
+					timestamp = timestamp == 0x7fff ? 0 : timestamp + 1;
+					if ((vt_block % 8) == 0
+					    && vt_block >= 8) {
+						printf("write block:0x%x - 0x%x.\n",
+						     vt_block - 8, vt_block - 1);
+					}
+				} else {
+					vt_sect++;
+				}
+				offset += nand->writesize;
+				outlen += nand->writesize;
+			}
+		}
+	}
+	if (page_len > 0) {
+		printf("nand_unsprase:last spare data: 0x%x,0x%x,0x%x.\n",
+		       vt_block, vt_sect, page_len);
+		/* memset(page_buffer + page_len, 0, nand->writesize - page_len); */
+		if (offset + nand->writesize > base_offset + max_limit) {
+			printf("nand_unsprase:"
+			       "exceed max_limit:0x%08llx,offset:0x%08llx.\n",
+			       max_limit,
+			       offset + nand->writesize - base_offset);
+			free(page_buffer);
+			return -1;
+		}
+		/* skip bad block. */
+		do {
+			size_t block_offset;
+			if (chip->phys_erase_shift == 0) {
+				block_offset = mtd_mod_by_eb(offset, nand);
+				if (nand_block_isbad(nand, mtd_div_by_eb(offset, nand) * nand->erasesize)) {
+					printf("Skip bad block 0x%08llx.\n",
+						(loff_t)mtd_div_by_eb(offset, nand) * nand->erasesize);
+					offset += nand->erasesize - block_offset;
+					(*skip_blocks)++;
+					continue;
+				} else {
+					break;
+				}
+			} else {
+				block_offset = offset & (nand->erasesize - 1);
+				if (nand_block_isbad(nand, offset & ~(nand->erasesize - 1))) {
+					printf("Skip bad block 0x%08llx.\n",
+				       	offset & ~(nand->erasesize - 1));
+					offset += nand->erasesize - block_offset;
+					(*skip_blocks)++;
+					continue;
+				} else {
+					break;
+				}
+			}
+		} while (1);
+
+		rval = nand_write_nftl(nand, offset, page_buffer,
+				       vt_block, vt_sect, timestamp);
+		if (rval) {
+			printf("nand_unsprase: nand_write_nftl fail.\n");
+			free(page_buffer);
+			return -1;
+		}
+		page_len = 0;
+		if (vt_sect + 1 == page_per_block) {
+			vt_block++;
+			vt_sect = 0;
+			timestamp = timestamp == 0x7fff ? 0 : timestamp + 1;
+		} else {
+			vt_sect++;
+		}
+		offset += nand->writesize;
+		outlen += nand->writesize;
+	}
+	if (vt_block % 8) {
+		printf("write block:0x%x - 0x%x,vt_sector:0x%x.\n",
+		       vt_block - (vt_block % 8), vt_block, vt_sect);
+	}
+	/*
+	   while(offset +  nand->writesize <= max_limit)
+	   {
+	   rval =  nand_write_nftl(nand, offset, NULL,
+	   vt_block, vt_sect,timestamp);
+	   if (rval) {
+	   printf("nand_unsprase: nand_write_nftl fail.\n");
+	   free(page_buffer);
+	   return -1;
+	   }
+	   if (vt_sect + 1 == page_per_block) {
+	   vt_block++;
+	   vt_sect = 0;
+	   timestamp = timestamp == 0x7fff ?
+	   0 : timestamp + 1;
+	   } else {
+	   vt_sect++;
+	   }
+	   offset += nand->writesize;
+	   outlen += nand->writesize;
+	   }
+	 */
+	free(page_buffer);
+	printf("nand_unsprase end.\n");
+	// printf("vt_block:0x%x.\n", vt_block);
+	// printf("vt_sect:0x%x.\n", vt_sect);
+	printf("*length:0x%x.\n", *length);
+	printf("offset:0x%08llx.\n", offset);
+	printf("out-length:0x%08llx.\n", outlen);
+	printf("skip_blocks:0x%x.\n", *skip_blocks);
+	return 0;
+}
+
 /**
- * nand_read_skip_bad:
+ * nand_read_skip_bad_new:
  *
  * Read image from NAND flash.
  * Blocks that are marked bad are skipped and the next block is readen
@@ -612,51 +1048,75 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
  * @param offset offset in flash
  * @param length buffer length, on return holds remaining bytes to read
  * @param buffer buffer to write to
+ * @param skip_block the bad block skipped
  * @return 0 in case of success
  */
-int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
-		       u_char *buffer)
+int nand_read_skip_bad_new(nand_info_t * nand, loff_t offset,
+			   size_t * length, u_char * buffer, u32 * skip_blocks)
 {
 	int rval;
 	size_t left_to_read = *length;
 	u_char *p_buffer = buffer;
 	int need_skip;
+	struct nand_chip *chip = nand->priv;
 
-	if ((offset & (nand->writesize - 1)) != 0) {
-		printf ("Attempt to read non page aligned data\n");
-		*length = 0;
-		return -EINVAL;
+	*skip_blocks = 0;
+	if (chip->page_shift == 0) {
+		if (mtd_mod_by_ws(offset, nand) != 0) {
+			printf("Attempt to read non page aligned data\n");
+			*length = 0;
+			return -EINVAL;
+		}
+	} else {
+		if ((offset & (nand->writesize - 1)) != 0) {
+			printf("Attempt to read non page aligned data\n");
+			*length = 0;
+			return -EINVAL;
+		}
 	}
 
-	need_skip = check_skip_len(nand, offset, *length);
+	need_skip = check_skip_len(nand, offset, *length, 0);
 	if (need_skip < 0) {
-		printf ("Attempt to read outside the flash area\n");
+		printf("Attempt to read outside the flash area\n");
 		*length = 0;
 		return -EINVAL;
 	}
 
 	if (!need_skip) {
-		rval = nand_read (nand, offset, length, buffer);
+		rval = nand_read(nand, offset, length, buffer);
 		if (!rval || rval == -EUCLEAN)
 			return 0;
 
 		*length = 0;
-		printf ("NAND read from offset %llx failed %d\n",
-			offset, rval);
+		printf("NAND read from offset %llx failed %d\n", offset, rval);
 		return rval;
 	}
 
 	while (left_to_read > 0) {
-		size_t block_offset = offset & (nand->erasesize - 1);
+		size_t block_offset;
 		size_t read_length;
 
-		WATCHDOG_RESET ();
+		WATCHDOG_RESET();
+		if (chip->phys_erase_shift == 0) {
+			block_offset = mtd_mod_by_eb(offset, nand);
 
-		if (nand_block_isbad (nand, offset & ~(nand->erasesize - 1))) {
-			printf ("Skipping bad block 0x%08llx\n",
-				offset & ~(nand->erasesize - 1));
-			offset += nand->erasesize - block_offset;
-			continue;
+			if (nand_block_isbad(nand, mtd_div_by_eb(offset, nand) * nand->erasesize)) {
+				printf("Skipping bad block 0x%08llx\n",
+					(loff_t)mtd_div_by_eb(offset, nand) * nand->erasesize);
+				offset += nand->erasesize - block_offset;
+				*skip_blocks += 1;
+				continue;
+			}
+		} else {
+			block_offset = offset & (nand->erasesize - 1);
+
+			if (nand_block_isbad(nand, offset & ~(nand->erasesize - 1))) {
+				printf("Skipping bad block 0x%08llx\n",
+			       	offset & ~(nand->erasesize - 1));
+				offset += nand->erasesize - block_offset;
+				*skip_blocks += 1;
+				continue;
+			}
 		}
 
 		if (left_to_read < (nand->erasesize - block_offset))
@@ -664,18 +1124,65 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 		else
 			read_length = nand->erasesize - block_offset;
 
-		rval = nand_read (nand, offset, &read_length, p_buffer);
+		rval = nand_read(nand, offset, &read_length, p_buffer);
 		if (rval && rval != -EUCLEAN) {
-			printf ("NAND read from offset %llx failed %d\n",
-				offset, rval);
+			printf("NAND read from offset %llx failed %d\n",
+			       offset, rval);
 			*length -= left_to_read;
 			return rval;
 		}
 
 		left_to_read -= read_length;
-		offset       += read_length;
-		p_buffer     += read_length;
+		offset += read_length;
+		p_buffer += read_length;
 	}
 
 	return 0;
 }
+
+/**
+ * nand_write_skip_bad:
+ *
+ * Write image to NAND flash.
+ * Blocks that are marked bad are skipped and the is written to the next
+ * block instead as long as the image is short enough to fit even after
+ * skipping the bad blocks.
+ *
+ * @param nand  	NAND device
+ * @param offset	offset in flash
+ * @param length	buffer length
+ * @param buffer	buffer to read from
+ * @param flags		flags modifying the behaviour of the write to NAND
+ * @return		0 in case of success
+ */
+int nand_write_skip_bad(nand_info_t * nand, loff_t offset, size_t * length,
+			u_char * buffer, int flags)
+{
+	u32 bad_blocks = 0;
+
+	return nand_write_skip_bad_new(nand, offset, length, 0,
+				       buffer, flags, &bad_blocks);
+}
+
+/**
+ * nand_read_skip_bad:
+ *
+ * Read image from NAND flash.
+ * Blocks that are marked bad are skipped and the next block is readen
+ * instead as long as the image is short enough to fit even after skipping the
+ * bad blocks.
+ *
+ * @param nand NAND device
+ * @param offset offset in flash
+ * @param length buffer length, on return holds remaining bytes to read
+ * @param buffer buffer to write to
+ * @return 0 in case of success
+ */
+int nand_read_skip_bad(nand_info_t * nand, loff_t offset, size_t * length,
+		       u_char * buffer)
+{
+	u32 bad_blocks = 0;
+
+	return nand_read_skip_bad_new(nand, offset, length, buffer,
+				      &bad_blocks);
+}
diff --git a/drivers/mtd/nand/rda_nand.c b/drivers/mtd/nand/rda_nand.c
new file mode 100644
index 0000000000..54bb77bc73
--- /dev/null
+++ b/drivers/mtd/nand/rda_nand.c
@@ -0,0 +1,12 @@
+#include <common.h>
+
+#ifdef CONFIG_NAND_RDA_V1
+#include "rda_nand_v1.c"
+#elif defined(CONFIG_NAND_RDA_V2)
+#include "rda_nand_v2.c"
+#elif defined(CONFIG_NAND_RDA_V3)
+#include "rda_nand_v3.c"
+#else
+#error "undefined RDA NAND Controller Version"
+#endif
+
diff --git a/drivers/mtd/nand/rda_nand_base.c b/drivers/mtd/nand/rda_nand_base.c
new file mode 100644
index 0000000000..ae3d01fd49
--- /dev/null
+++ b/drivers/mtd/nand/rda_nand_base.c
@@ -0,0 +1,95 @@
+#include <common.h>
+#include <asm/types.h>
+#include <nand.h>
+
+#include <asm/errno.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/reg_sysctrl.h>
+#include <asm/arch/hwcfg.h>
+#include <mtd/nand/rda_nand.h>
+extern int rda_nand_init(struct nand_chip *nand);
+extern int rda_spi_nand_init(struct nand_chip *nand);
+
+int board_nand_init(struct nand_chip *chip) __attribute__ ((weak));
+
+static int flash_intf_spi = 0;
+
+#if defined(CONFIG_MACH_RDA8810)
+int board_nand_init(struct nand_chip *chip)
+{
+	u16 hwcfg = rda_hwcfg_get();
+	u16 metal_id = rda_metal_id_get();
+
+	if (!(hwcfg & RDA_HW_CFG_BIT_3) && (hwcfg & RDA_HW_CFG_BIT_2)) {
+		printf("metal %d hwcfg %x, use eMMC, skip nand init\n",
+			metal_id, hwcfg);
+		return -ENODEV;
+	}
+
+	if ((metal_id >= 7) && (hwcfg & RDA_HW_CFG_BIT_3)) {
+		printf("metal %d hwcfg %x, use SPI NAND\n",
+			metal_id, hwcfg);
+		flash_intf_spi = 1;
+		return rda_spi_nand_init(chip);
+	} else {
+		printf("metal %d hwcfg %x, use NAND\n",
+			metal_id, hwcfg);
+		return rda_nand_init(chip);
+	}
+}
+#else /* 8810H*/
+#if defined(CONFIG_MACH_RDA8810H)
+int board_nand_init(struct nand_chip *chip)
+{
+	u16 hwcfg = rda_hwcfg_get();
+	u16 metal_id = rda_metal_id_get();
+	enum media_type media = rda_media_get();
+
+	if (media == MEDIA_MMC) {
+		printf("metal %d hwcfg %x, use eMMC, skip nand init\n",
+			metal_id, hwcfg);
+		return -ENODEV;
+	} else if (media == MEDIA_SPINAND) {
+		printf("metal %d hwcfg %x, use SPI NAND\n",
+			metal_id, hwcfg);
+		flash_intf_spi = 1;
+		return rda_spi_nand_init(chip);
+	} else if (media == MEDIA_NAND) {
+		printf("metal %d hwcfg %x, use NAND\n",
+			metal_id, hwcfg);
+		return rda_nand_init(chip);
+	} else {
+		printf("invalid bootmode:hwcfg=0x%x\n", hwcfg);
+		return -ENODEV;
+	}
+}
+#else /* 8810E, 8820, 8850, 8850e */
+int board_nand_init(struct nand_chip *chip)
+{
+	u16 hwcfg = rda_hwcfg_get();
+	u16 metal_id = rda_metal_id_get();
+
+	if (!(hwcfg & RDA_HW_CFG_BIT_3) && (hwcfg & RDA_HW_CFG_BIT_2)) {
+		printf("metal %d hwcfg %x, use eMMC, skip nand init\n",
+			metal_id, hwcfg);
+		return -ENODEV;
+	}
+
+	if (hwcfg & RDA_HW_CFG_BIT_3) {
+		printf("metal %d hwcfg %x, use SPI NAND\n",
+			metal_id, hwcfg);
+		flash_intf_spi = 1;
+		return rda_spi_nand_init(chip);
+	} else {
+		printf("metal %d hwcfg %x, use NAND\n",
+			metal_id, hwcfg);
+		return rda_nand_init(chip);
+	}
+}
+#endif
+#endif
+
+int rda_flash_intf_is_spi(void)
+{
+	return flash_intf_spi;
+}
diff --git a/drivers/mtd/nand/rda_nand_v1.c b/drivers/mtd/nand/rda_nand_v1.c
new file mode 100644
index 0000000000..d485721283
--- /dev/null
+++ b/drivers/mtd/nand/rda_nand_v1.c
@@ -0,0 +1,1661 @@
+#include <common.h>
+#include <malloc.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <nand.h>
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/reg_nand.h>
+#include <asm/arch/reg_sysctrl.h>
+#include <asm/arch/hwcfg.h>
+#include <mtd/nand/rda_nand.h>
+
+#include <rda/tgt_ap_board_config.h>
+#include <rda/tgt_ap_clock_config.h>
+#include <rda/tgt_ap_flash_parts.h>
+
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_NAND_RDA_DMA
+#endif
+
+#ifdef CONFIG_NAND_RDA_DMA
+#include <asm/dma-mapping.h>
+#include <asm/arch/dma.h>
+#endif
+
+//#define NAND_DEBUG
+//#define NAND_DEBUG_VERBOSE
+
+#if (_TGT_NAND_TYPE_ == _PARALLEL_NAND_USED_)
+
+#define hal_gettime     get_ticks
+#define SECOND          * CONFIG_SYS_HZ_CLOCK
+#define NAND_TIMEOUT    ( 2 SECOND )
+#define PLL_BUS_FREQ	(_TGT_AP_PLL_BUS_FREQ * 1000000)
+
+/***********************nand  global buffer define ************************/
+/******************for 8810 support  8k/16k nand flash*********************/
+#ifdef CONFIG_SPL_BUILD
+/*sram space is not enough, so use sdram space as middle data buffer*/
+static u8 *g_nand_flash_temp_buffer = (u8 *)CONFIG_SPL_NAND_MIDDLE_DATA_BUFFER;
+#else
+#define NAND_FLASH_PHYSICAL_PAGE_SIZE	16384
+#define NAND_FLASH_PHYSICAL_SPARE_SIZE	1280
+static u8 g_nand_flash_temp_buffer[NAND_FLASH_PHYSICAL_PAGE_SIZE + \
+					NAND_FLASH_PHYSICAL_SPARE_SIZE] __attribute__ ((__aligned__(64)));
+#endif
+//#define NAND_CONTROLLER_BUFFER_DATA_SIZE	4096
+//#define NAND_CONTROLLER_BUFFER_OOB_SIZE	224
+#define NAND_CONTROLLER_TEMP_BUFFER_SIZE	4320
+
+/*when system use ext4+ftl mode, FTL oob struct is 12bytes, and is stored in flash OOB space.*/
+/*the nand page size use 3K bytes data + 128 bytes oob, or 6k bytes data + 256 bytes oob, or*/
+/*12k bytes data + 512 bytes oob. but nand controller has hardware ecc error,only could 3K ecc*/
+/*in 4k byte,  so OOB could not be ecc protecked. But maybe have some error bits in this space,*/
+/*so the method is: copy FTL oob struct 12 bytes + 4 bytes checksum several times in oob space,*/
+/*when read, find the first right checksum data, then use this array data.  */
+#define __FTL_OOB_STRUCT_LENGTH__ 12  //bytes, when FTL oob struct add member, this sould increase.
+#define OOB_SW_PROTECT_SWITCH_ON 1
+
+/* clock division value map */
+const static u8 clk_div_map[] = {
+	4*60,	/* 0 */
+	4*60,	/* 1 */
+	4*60,	/* 2 */
+	4*60,	/* 3 */
+	4*60,	/* 4 */
+	4*60,	/* 5 */
+	4*60,	/* 6 */
+	4*60,	/* 7 */
+	4*40,	/* 8 */
+	4*30,	/* 9 */
+	4*24,	/* 10 */
+	4*20,	/* 11 */
+	4*17,	/* 12 */
+	4*15,	/* 13 */
+	4*13,	/* 14 */
+	4*12,	/* 15 */
+	4*11,	/* 16 */
+	4*10,	/* 17 */
+	4*9,	/* 18 */
+	4*8,	/* 19 */
+	4*7,	/* 20 */
+	4*13/2,	/* 21 */
+	4*6,	/* 22 */
+	4*11/2,	/* 23 */
+	4*5,	/* 24 */
+	4*9/2,	/* 25 */
+	4*4,	/* 26 */
+	4*7/2,	/* 27 */
+	4*3,	/* 28 */
+	4*5/2,	/* 29 */
+	4*2,	/* 30 */
+	4*1,	/* 31 */
+};
+
+static struct nand_ecclayout rda_nand_oob_64 = {
+	.eccbytes = 0,
+	.eccpos = {},
+	.oobfree = {
+		{.offset = 2,
+		 .length = 62} }
+};
+
+static struct nand_ecclayout rda_nand_oob_128 = {
+	.eccbytes = 0,
+	.eccpos = {},
+	.oobfree = {
+		{.offset = 2,
+		 .length = 126} }
+};
+
+static struct nand_ecclayout rda_nand_oob_256 = {
+	.eccbytes = 0,
+	.eccpos = {},
+	.oobfree = {
+		{.offset = 2,
+		 .length = 254} }
+};
+
+static struct nand_ecclayout rda_nand_oob_512 = {
+	.eccbytes = 0,
+	.eccpos = {},
+	.oobfree = {
+		{.offset = 2,
+		 .length = 510} }
+};
+
+extern void rda_dump_buf(char *data, size_t len);
+
+#if (OOB_SW_PROTECT_SWITCH_ON == 1)
+static uint32_t nand_checksum32( unsigned char* data, uint32_t data_size)
+{
+	uint32_t checksum = 0;
+	uint32_t i;
+
+	for(i = 0; i < data_size; i++)
+		checksum = ((checksum << 31) | (checksum >> 1)) + (uint32_t)data[i];
+
+	return checksum;
+}
+
+struct select_data{
+	u8 data;
+	u8 count;
+};
+
+static void nand_sw_ecc_check(u8 * buf, u8 *dst, u8 copy_number, u8 array_length)
+{
+	u8 i, j, k, m;
+	struct select_data select[30];
+	u8 temp;
+
+	for(i = 0; i < array_length; i++){
+		m = 0;
+		select[m].data = buf[i];
+		select[m].count = 1;
+		for(j = 1; j < copy_number; j++){
+			k = 0;
+			while(1){
+				if(select[k].data == buf[i + j * (array_length + 4)]){
+					select[k].count++;
+					break;
+				}
+
+				if(k >= m){
+					select[m+1].data = buf[i + j * (array_length + 4)];
+					select[m+1].count = 1;
+					m++;
+					break;
+				}
+				k++;
+			}
+		}
+
+		temp = select[0].count;
+		dst[i] = select[0].data;
+		for(j = 1; j <= m; j++){
+			if(select[j].count > temp){
+				dst[i] = select[j].data;
+				temp = select[j].count;
+			}
+		}
+	}
+}
+#endif
+
+static void hal_send_cmd(unsigned char cmd, unsigned int page_addr)
+{
+	unsigned long cmd_reg;
+
+	cmd_reg = NANDFC_DCMD(cmd) | NANDFC_PAGE_ADDR(page_addr);
+#ifdef NAND_DEBUG
+	printf("  hal_send_cmd 0x%08lx\n", cmd_reg);
+#endif
+	__raw_writel(cmd_reg, NANDFC_REG_DCMD_ADDR);
+}
+
+static void hal_set_col_addr(unsigned int col_addr)
+{
+	__raw_writel(col_addr, NANDFC_REG_COL_ADDR);
+}
+
+static void hal_set_col_cmd(unsigned int col_cmd)
+{
+	__raw_writel(0x50010000 |col_cmd, NANDFC_REG_CMD_DEF_B);
+}
+
+static void hal_flush_buf(struct mtd_info *mtd)
+{
+	/*
+	 there is no reg NANDFC_REG_BUF_CTRL
+	 */
+	//__raw_writel(0x7, NANDFC_REG_BUF_CTRL);
+}
+
+static unsigned long hal_wait_cmd_complete(void)
+{
+	unsigned long int_stat;
+	unsigned long long wait_time = NAND_TIMEOUT;
+	unsigned long long start_time = hal_gettime();
+	int timeout = 0;
+
+	/* wait done */
+	do {
+		int_stat = __raw_readl(NANDFC_REG_INT_STAT);
+		if (hal_gettime() - start_time >= wait_time) {
+			timeout = 1;
+		}
+	} while (!(int_stat & NANDFC_INT_DONE) && !timeout);
+
+	/* to clear */
+	__raw_writel(int_stat & NANDFC_INT_CLR_MASK, NANDFC_REG_INT_STAT);
+
+	if (timeout) {
+		printf("nand error, cmd timeout\n");
+		return -ETIME;
+	}
+
+	if (int_stat & NANDFC_INT_ERR_ALL) {
+		printf("nand error, int_stat = %lx\n", int_stat);
+		return (int_stat & NANDFC_INT_ERR_ALL);
+	}
+	return 0;
+}
+
+static int init_nand_info(struct rda_nand_info *info,
+			int nand_type, int bus_width_16)
+{
+	info->type = nand_type;
+	switch (nand_type) {
+	case NAND_TYPE_2KL:
+		info->hard_ecc_hec = 0;
+		info->bus_width_16 = bus_width_16;
+		info->page_shift = 11;
+		info->oob_size = 64;
+		info->page_num_per_block = 64;
+		info->vir_page_size = 2048;
+		info->vir_page_shift = 11;
+		info->vir_oob_size = 64;
+		info->vir_erase_size =
+			info->vir_page_size * info->page_num_per_block;
+		info->nand_use_type = 0;
+		break;
+#if(__TGT_AP_FLASH_USE_PART_OF_PAGE__ == 1)
+	case NAND_TYPE_MLC4K:
+		info->hard_ecc_hec = 1;
+		info->bus_width_16 = bus_width_16;
+		info->page_shift = 12;
+		info->oob_size = 224;
+		info->page_num_per_block = 256;
+#if(__TGT_AP_FLASH_LOGIC_PAGE_SIZE_N_KB__ == __TGT_AP_FLASH_USE_4KAS2K_PAGE_DIV__)
+		info->vir_page_size = 2048;
+		info->vir_oob_size = 64;
+#else
+#if(__TGT_AP_FLASH_LOGIC_PAGE_SIZE_N_KB__ == __TGT_AP_FLASH_USE_4KAS3K_PAGE_DIV__)
+		info->vir_page_size = 3072;
+		info->vir_oob_size = 128;
+#endif
+#endif
+		info->vir_page_shift = 0;
+		info->vir_erase_size =
+			info->vir_page_size * info->page_num_per_block;
+		info->nand_use_type = 0;
+		break;
+#else
+	case NAND_TYPE_MLC4K:
+		info->hard_ecc_hec = 1;
+		info->bus_width_16 = bus_width_16;
+		info->page_shift = 12;
+		info->oob_size = 224;
+		info->page_num_per_block = 256;
+		info->vir_page_size = 2048;
+		info->vir_page_shift = 11;
+		info->vir_oob_size = 64;
+		info->vir_erase_size =
+			info->vir_page_size * info->page_num_per_block;
+		info->nand_use_type = 0;
+		break;
+#endif
+	case NAND_TYPE_SLC4K:
+		info->hard_ecc_hec = 0;
+		info->bus_width_16 = bus_width_16;
+		info->page_shift = 12;
+		/* slc 4k, u-boot kernel yaffs use 128 oob */
+		info->oob_size = 128;
+#ifdef _TGT_AP_NAND_DISABLE_HEC
+		/* this flag also implies using MLC */
+		info->page_num_per_block = 256;
+#else
+		info->page_num_per_block = 64;
+#endif
+		info->vir_page_size = 4096;
+		info->vir_page_shift = 12;
+		info->vir_oob_size = 128;
+		info->vir_erase_size =
+			info->vir_page_size * info->page_num_per_block;
+		info->nand_use_type = 0;
+		break;
+#if(__TGT_AP_FLASH_USE_PART_OF_PAGE__ == 1)
+	case NAND_TYPE_MLC8K:
+		info->hard_ecc_hec = 1;
+		info->bus_width_16 = bus_width_16;
+		info->page_shift = 13;
+		info->oob_size = 744;
+		info->page_num_per_block = 256;
+#if(__TGT_AP_FLASH_LOGIC_PAGE_SIZE_N_KB__ == __TGT_AP_FLASH_USE_8KAS6K_PAGE_DIV__)
+		info->vir_page_size = 6144;
+		info->vir_oob_size = 256;
+		info->nand_use_type = 1;
+#else
+#if(__TGT_AP_FLASH_LOGIC_PAGE_SIZE_N_KB__ == __TGT_AP_FLASH_USE_8KAS4K_PAGE_DIV__)
+		info->vir_page_size = 4096;
+		info->vir_oob_size = 128;
+		info->nand_use_type = 1;
+#endif
+#endif
+		info->vir_page_shift = 0;
+		info->vir_erase_size =
+			info->vir_page_size * info->page_num_per_block;
+		break;
+#else
+	case NAND_TYPE_MLC8K:
+		info->hard_ecc_hec = 1;
+		info->bus_width_16 = bus_width_16;
+		info->page_shift = 13;
+		info->oob_size = 744;
+		info->page_num_per_block = 256;
+		info->vir_page_size = 4096;
+		info->vir_page_shift = 12;
+		info->vir_oob_size = 128;
+		info->vir_erase_size =
+			info->vir_page_size * info->page_num_per_block;
+		info->nand_use_type = 1;
+		break;
+#endif
+	case NAND_TYPE_SLC8K:
+		info->hard_ecc_hec = 0;
+		info->bus_width_16 = bus_width_16;
+		info->page_shift = 13;
+		info->oob_size = 744;
+		info->page_num_per_block = 256;
+		info->vir_page_size = 8192;
+		info->vir_page_shift = 13;
+		info->vir_oob_size = 256;
+		info->vir_erase_size =
+			info->vir_page_size * info->page_num_per_block;
+		info->nand_use_type = 1;
+		break;
+#if(__TGT_AP_FLASH_USE_PART_OF_PAGE__ == 1)
+	case NAND_TYPE_MLC16K:
+		info->hard_ecc_hec = 1;
+		info->bus_width_16 = bus_width_16;
+		info->page_shift = 14;
+		info->oob_size = 1280;
+		info->page_num_per_block = 256;
+#if(__TGT_AP_FLASH_LOGIC_PAGE_SIZE_N_KB__ == __TGT_AP_FLASH_USE_16KAS8K_PAGE_DIV__)
+		info->vir_page_size = 8192;
+		info->vir_oob_size = 256;
+#else
+#if(__TGT_AP_FLASH_LOGIC_PAGE_SIZE_N_KB__ == __TGT_AP_FLASH_USE_16KAS12K_PAGE_DIV__)
+		info->vir_page_size = 12288;
+		info->vir_oob_size = 512;
+#endif
+#endif
+		info->vir_page_shift = 0;
+		info->vir_erase_size =
+			info->vir_page_size * info->page_num_per_block;
+		info->nand_use_type = 3;
+		break;
+#else
+	case NAND_TYPE_MLC16K:
+		info->hard_ecc_hec = 1;
+		info->bus_width_16 = bus_width_16;
+		info->page_shift = 14;
+		info->oob_size = 1280;
+		info->page_num_per_block = 256;
+		info->vir_page_size = 8192;
+		info->vir_page_shift = 13;
+		info->vir_oob_size = 256;
+		info->vir_erase_size =
+			info->vir_page_size * info->page_num_per_block;
+		info->nand_use_type = 3;
+		break;
+#endif
+	case NAND_TYPE_SLC16K:
+		info->hard_ecc_hec = 0;
+		info->bus_width_16 = bus_width_16;
+		info->page_shift = 14;
+		info->oob_size = 1280;
+		info->page_num_per_block = 256;
+		info->vir_page_size = 16384;
+		info->vir_page_shift = 14;
+		info->vir_oob_size = 512;
+		info->vir_erase_size =
+			info->vir_page_size * info->page_num_per_block;
+		info->nand_use_type = 3;
+		break;
+	default:
+		printf("invalid nand type\n");
+		return -EINVAL;
+	}
+
+	info->logic_page_size = info->vir_page_size / (info->nand_use_type + 1);
+	info->logic_oob_size = info->vir_oob_size / (info->nand_use_type + 1);
+	return 0;
+}
+
+static u32 cal_freq_by_divreg(u32 basefreq, u32 reg, u32 div2)
+{
+	u32 newfreq;
+
+	if (reg >= ARRAY_SIZE(clk_div_map)) {
+		printf("nand:Invalid div reg: %u\n", reg);
+		reg = ARRAY_SIZE(clk_div_map) - 1;
+	}
+	/* Assuming basefreq is smaller than 2^31 (2.147G Hz) */
+	newfreq = (basefreq << (div2 ? 0 : 1)) / (clk_div_map[reg] >> 1);
+	return newfreq;
+}
+
+unsigned long get_master_clk_rate(u32 reg)
+{
+	u32 div2;
+	unsigned long rate;
+
+	div2 = reg & SYS_CTRL_AP_AP_APB2_SRC_SEL;
+	reg = GET_BITFIELD(reg, SYS_CTRL_AP_AP_APB2_FREQ);
+	rate = cal_freq_by_divreg(PLL_BUS_FREQ, reg, div2);
+
+	return rate;
+}
+
+static unsigned long rda_nand_cld_div_tbl[16] = {
+	3, 4, 5, 6, 7, 8, 9, 10,
+	12, 14, 16, 18, 20, 22, 24, 28
+};
+
+static unsigned long hal_calc_divider(struct rda_nand_info *info)
+{
+	unsigned long mclk = info->master_clk;
+	unsigned long div, clk_div;
+	int i;
+
+	div = mclk / info->clk;
+	if (mclk % info->clk)
+		div += 1;
+
+	if (div < 7) {
+		/* 7 is minimal divider by hardware */
+		div = 7;
+	}
+
+	for (i=0;i<16;i++) {
+		if(div <= rda_nand_cld_div_tbl[i]) {
+			clk_div = i;
+			break;
+		}
+	}
+
+	if (i>=16) {
+		clk_div = 15;
+	}
+
+	//printf("NAND: div:%ld, clk_div:%ld\n", div, clk_div);
+	return clk_div;
+}
+
+static int hal_init(struct rda_nand_info *info)
+{
+	unsigned long config_a, config_b;
+	unsigned long clk_div=hal_calc_divider(info);
+
+	// clk_div = 4;		// for APB2 = 48MHz,  48/7
+	//clk_div = 11;		// for APB2 = 120MHz, 120/18
+	//clk_div = 15;	// for APB2 = 240MHz, 240/28
+
+	/* setup config_a and config_b */
+	config_a = NANDFC_CYCLE(clk_div);
+	config_b = 0;
+	config_a |= NANDFC_CHIP_SEL(0x0e);
+	config_a |= NANDFC_POLARITY_IO(0);	// set 0 invert IO
+	config_a |= NANDFC_POLARITY_MEM(1);	// set 1 invert MEM
+
+	switch (info->type) {
+	case NAND_TYPE_512S:
+	case NAND_TYPE_512L:
+		printf("Not support 512 nand any more\n");
+		return 1;
+	case NAND_TYPE_2KS:
+		config_a |= NANDFC_TIMING(0x7B);
+		break;
+	case NAND_TYPE_2KL:
+	case NAND_TYPE_MLC2K:
+		config_a |= NANDFC_TIMING(0x8B);
+		break;
+	case NAND_TYPE_MLC4K:
+	case NAND_TYPE_SLC4K:
+		config_a |= NANDFC_TIMING(0x8C);
+		break;
+	case NAND_TYPE_MLC8K:
+	case NAND_TYPE_SLC8K:
+		config_a |= NANDFC_TIMING(0x8c);
+		config_b |= 0x20;
+		break;
+	case NAND_TYPE_MLC16K:
+	case NAND_TYPE_SLC16K:
+		config_a |= NANDFC_TIMING(0x8c) | (0x00 << 20);
+		config_b |= 0x10;
+		break;
+	default:
+		printf("invalid nand type\n");
+		return -EINVAL;
+	}
+
+	//enable the 16bit mode;
+	if (info->bus_width_16)
+		config_a |= NANDFC_WDITH_16BIT(1);
+
+	config_b |= NANDFC_HWECC(1);
+	if (info->hard_ecc_hec)
+		config_b |= NANDFC_ECC_MODE(0x02);
+	__raw_writel(config_a, NANDFC_REG_CONFIG_A);
+	__raw_writel(config_b, NANDFC_REG_CONFIG_B);
+
+	/* set readid type, 0x06 for 8 bytes ID */
+	__raw_writel(0x6, NANDFC_REG_IDTPYE);
+
+#ifdef _TGT_AP_NAND_READDELAY
+	{
+	unsigned int delay;
+	/* Set an interval of filter for erasing operation. */
+	delay = __raw_readl(NANDFC_REG_DELAY);
+	delay &= ~0xffff;
+	delay |=  _TGT_AP_NAND_READDELAY;
+	__raw_writel(delay, NANDFC_REG_DELAY);
+	printf("Nand delay : 0x%x .\n",  (delay & 0xffff));
+	}
+#endif /* #if _TGT_AP_NAND_READDELAY */
+	printf("Nand Init Done, %08lx %08lx\n", config_a, config_b);
+
+	return 0;
+}
+
+static u8 nand_rda_read_byte(struct mtd_info *mtd)
+{
+	u8 ret;
+	struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	ret = *((u8 *) info->byte_buf + info->index);
+	info->index++;
+#ifdef NAND_DEBUG
+	printf("nand_read_byte, ret = %02x\n", ret);
+#endif
+	return ret;
+}
+
+static u16 nand_rda_read_word(struct mtd_info *mtd)
+{
+	u16 ret;
+	struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	ret = *(u16 *) ((uint8_t *) info->byte_buf + info->index);
+	info->index += 2;
+#ifdef NAND_DEBUG
+	printf("nand_read_word, ret = %04x\n", ret);
+#endif
+	return ret;
+}
+
+#ifdef CONFIG_NAND_RDA_DMA
+static void nand_rda_dma_move_data(struct mtd_info *mtd, uint8_t * dst, uint8_t * src,
+										int len, enum dma_data_direction dir)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	struct rda_dma_chan_params dma_param;
+	dma_addr_t dst_phys_addr, src_phys_addr;
+	void *dst_addr = (void *)dst;
+	void *src_addr = (void *)src;
+	int ret = 0;
+
+	if (((u32)dst_addr & 0x7) != 0 || ((u32)src_addr & 0x7) != 0) {
+		printf("ERROR, nand dma read buffer dst %p or src %p is not 8bytes aligned\n",
+			dst_addr, src_addr);
+		return;
+	}
+
+	if(dir == DMA_FROM_DEVICE){
+		dst_phys_addr = dma_map_single(dst_addr, len, DMA_FROM_DEVICE);
+		src_phys_addr = (dma_addr_t)src;
+	}
+	else if(dir == DMA_TO_DEVICE){
+		dst_phys_addr = (dma_addr_t)dst;
+		src_phys_addr = dma_map_single(src_addr, len, DMA_TO_DEVICE);
+	}
+	else{
+		dst_phys_addr = dma_map_single(dst_addr, len, DMA_BIDIRECTIONAL);
+		src_phys_addr = dma_map_single(src_addr, len, DMA_BIDIRECTIONAL);
+	}
+
+	dma_param.src_addr = src_phys_addr;
+	dma_param.dst_addr = dst_phys_addr;
+	dma_param.xfer_size = len;
+	//dma_param.dma_mode = RDA_DMA_FR_MODE;
+	dma_param.dma_mode = RDA_DMA_NOR_MODE;
+
+	ret = rda_set_dma_params(info->dma_ch, &dma_param);
+	if (ret < 0) {
+		printf("rda nand : DMA failed to set parameter!\n");
+		if(dir == DMA_FROM_DEVICE)
+			dma_unmap_single(dst_addr, len, DMA_FROM_DEVICE);
+		else if(dir == DMA_TO_DEVICE)
+			dma_unmap_single(src_addr, len, DMA_TO_DEVICE);
+		else{
+			dma_unmap_single(dst_addr, len, DMA_BIDIRECTIONAL);
+			dma_unmap_single(src_addr, len, DMA_BIDIRECTIONAL);
+		}
+		return;
+	}
+
+	/* use flush to avoid annoying unaligned warning */
+	/* however, invalidate after the dma it the right thing to do */
+	if(dir == DMA_FROM_DEVICE)
+		flush_dcache_range((u32)dst_addr, (u32)(dst_addr + len));
+	else if(dir == DMA_TO_DEVICE)
+		flush_dcache_range((u32)src_addr, (u32)(src_addr + len));
+	else{
+		flush_dcache_range((u32)dst_addr, (u32)(dst_addr + len));
+		flush_dcache_range((u32)src_addr, (u32)(src_addr + len));
+	}
+
+	rda_start_dma(info->dma_ch);
+	rda_poll_dma(info->dma_ch);
+	rda_stop_dma(info->dma_ch);
+
+	/* use flush to avoid annoying unaligned warning */
+	//invalidate_dcache_range((u32)addr, (u32)(addr + len));
+
+	/* Free the specified physical address */
+	if(dir == DMA_FROM_DEVICE)
+		dma_unmap_single(dst_addr, len, DMA_FROM_DEVICE);
+	else if(dir == DMA_TO_DEVICE)
+		dma_unmap_single(src_addr, len, DMA_TO_DEVICE);
+	else{
+		dma_unmap_single(dst_addr, len, DMA_BIDIRECTIONAL);
+		dma_unmap_single(src_addr, len, DMA_BIDIRECTIONAL);
+	}
+}
+#endif/*CONFIG_NAND_RDA_DMA*/
+
+static void nand_rda_logic_read_cache(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	unsigned long cmd_ret;
+
+	hal_set_col_addr(info->col_addr);
+	hal_send_cmd((unsigned char)info->cmd, info->page_addr);
+	cmd_ret = hal_wait_cmd_complete();
+	if (cmd_ret) {
+		printf("logic read fail, cmd = %x, page_addr = %x, col_addr = %x\n",
+		       info->cmd, info->page_addr, info->col_addr);
+	}
+}
+
+static void nand_rda_read_cache(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	u8 *nand_ptr = (u8 *) (chip->IO_ADDR_R);
+	u8 *u_nand_temp_buffer = &g_nand_flash_temp_buffer[0];
+
+	if(info->nand_use_type > 0){
+#ifndef CONFIG_NAND_RDA_DMA
+		memcpy((void *)u_nand_temp_buffer,
+				(void *)nand_ptr,
+				info->logic_page_size);
+		memcpy((void *)(u_nand_temp_buffer + mtd->writesize),
+				(void *)(nand_ptr + info->logic_page_size),
+				info->logic_oob_size);
+#else
+		nand_rda_dma_move_data(mtd,
+				u_nand_temp_buffer,
+				nand_ptr,
+				info->logic_page_size,
+				DMA_FROM_DEVICE);
+		nand_rda_dma_move_data(mtd,
+				(uint8_t*)(u_nand_temp_buffer + mtd->writesize),
+				(uint8_t*)(nand_ptr + info->logic_page_size),
+				info->logic_oob_size,
+				DMA_FROM_DEVICE);
+#endif
+		//printf("\nread chip buffer0:\n");
+		//rda_dump_buf(nand_ptr, 4320);
+
+		info->col_addr += NAND_CONTROLLER_TEMP_BUFFER_SIZE;
+		hal_set_col_cmd(0xe0);
+		info->cmd = NAND_CMD_RNDOUT;
+		nand_rda_logic_read_cache(mtd);
+
+#ifndef CONFIG_NAND_RDA_DMA
+		memcpy((void *)(u_nand_temp_buffer + info->logic_page_size),
+				(void *)nand_ptr,
+				info->logic_page_size);
+		memcpy((void *)(u_nand_temp_buffer + mtd->writesize + info->logic_oob_size),
+				(void *)(nand_ptr + info->logic_page_size),
+				info->logic_oob_size);
+#else
+		nand_rda_dma_move_data(mtd,
+				(uint8_t*)(u_nand_temp_buffer + info->logic_page_size),
+				nand_ptr,
+				info->logic_page_size,
+				DMA_FROM_DEVICE);
+		nand_rda_dma_move_data(mtd,
+				(uint8_t*)(u_nand_temp_buffer + mtd->writesize + info->logic_oob_size),
+				(uint8_t*)(nand_ptr + info->logic_page_size),
+				info->logic_oob_size,
+				DMA_FROM_DEVICE);
+#endif
+
+		//printf("\nread chip buffer1:\n");
+		//rda_dump_buf(nand_ptr, 4320);
+		if(info->type == NAND_TYPE_SLC16K || info->type == NAND_TYPE_MLC16K){
+			info->col_addr += NAND_CONTROLLER_TEMP_BUFFER_SIZE;
+			nand_rda_logic_read_cache(mtd);
+
+#ifndef CONFIG_NAND_RDA_DMA
+			memcpy((void *)(u_nand_temp_buffer + info->logic_page_size * 2),
+					(void *)nand_ptr,
+					info->logic_page_size);
+			memcpy((void *)(u_nand_temp_buffer + mtd->writesize + info->logic_oob_size * 2),
+					(void *)(nand_ptr + info->logic_page_size),
+					info->logic_oob_size);
+#else
+			nand_rda_dma_move_data(mtd,
+					(uint8_t*)(u_nand_temp_buffer + info->logic_page_size * 2),
+					nand_ptr,
+					info->logic_page_size,
+					DMA_FROM_DEVICE);
+			nand_rda_dma_move_data(mtd,
+					(uint8_t*)(u_nand_temp_buffer + mtd->writesize + info->logic_oob_size * 2),
+					(uint8_t*)(nand_ptr + info->logic_page_size),
+					info->logic_oob_size,
+					DMA_FROM_DEVICE);
+#endif
+
+			info->col_addr += NAND_CONTROLLER_TEMP_BUFFER_SIZE;
+			nand_rda_logic_read_cache(mtd);
+
+#ifndef CONFIG_NAND_RDA_DMA
+			memcpy((void *)(u_nand_temp_buffer + info->logic_page_size * 3),
+					(void *)nand_ptr,
+					info->logic_page_size);
+			memcpy((void *)(u_nand_temp_buffer + mtd->writesize + info->logic_oob_size * 3),
+					(void *)(nand_ptr + info->logic_page_size),
+					info->logic_oob_size);
+#else
+			nand_rda_dma_move_data(mtd,
+					(uint8_t*)(u_nand_temp_buffer + info->logic_page_size * 3),
+					nand_ptr,
+					info->logic_page_size,
+					DMA_FROM_DEVICE);
+			nand_rda_dma_move_data(mtd,
+					(uint8_t*)(u_nand_temp_buffer + mtd->writesize + info->logic_oob_size * 3),
+					(uint8_t*)(nand_ptr + info->logic_page_size),
+					info->logic_oob_size,
+					DMA_FROM_DEVICE);
+#endif
+		}
+		hal_set_col_cmd(0x30);
+		hal_set_col_addr(0);
+	}
+}
+
+static void nand_rda_read_buf(struct mtd_info *mtd, uint8_t * buf, int len)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	u8 *nand_ptr = (u8 *) (chip->IO_ADDR_R + info->read_ptr);
+	u8 *u_nand_temp_buffer = &g_nand_flash_temp_buffer[info->read_ptr];
+#if (OOB_SW_PROTECT_SWITCH_ON == 1)
+	uint8_t *oob_temp_ptr = &g_nand_flash_temp_buffer[16384+512];
+	uint8_t oob_byte_count = 2 + __FTL_OOB_STRUCT_LENGTH__ + 2 + 4;
+	uint8_t oob_copy_number = info->vir_oob_size / oob_byte_count;
+	uint32_t checksum, checksum_load;
+	u8 i;
+#endif
+
+#ifdef NAND_DEBUG
+	printf("read : buf addr = 0x%p, len = %d, read_ptr = %d\n", buf, len,
+	       info->read_ptr);
+#endif /* NAND_DEBUG */
+
+#if 1//ndef CONFIG_NAND_RDA_DMA
+	if(info->nand_use_type > 0){
+#if (OOB_SW_PROTECT_SWITCH_ON == 1)
+		memset(oob_temp_ptr, 0xff, info->vir_oob_size);
+		if(info->read_ptr > 0){
+			if(info->vir_page_size == 6144 || info->vir_page_size == 12288){
+				for(i = 0; i < oob_copy_number; i++){
+					u32 index = i * oob_byte_count + oob_byte_count;
+
+					checksum = nand_checksum32(&u_nand_temp_buffer[i * oob_byte_count],
+								oob_byte_count - 4);
+					checksum_load = u_nand_temp_buffer[index - 4];
+					checksum_load |= u_nand_temp_buffer[index - 3] << 8;
+					checksum_load |= u_nand_temp_buffer[index - 2] << 16;
+					checksum_load |= u_nand_temp_buffer[index - 1] << 24;
+					if(checksum == checksum_load || checksum_load == ~0x0){
+						memcpy(oob_temp_ptr,
+							&u_nand_temp_buffer[i * oob_byte_count],
+							oob_byte_count);
+						break;
+					}
+				}
+				if(i == oob_copy_number){
+					printf("6k or 12k oob ecc warning, data select!!!! \n");
+					nand_sw_ecc_check(u_nand_temp_buffer,
+						oob_temp_ptr,
+						oob_copy_number,
+						oob_byte_count - 4);
+				}
+
+				u_nand_temp_buffer = oob_temp_ptr;
+			}
+		}
+#endif
+		memcpy((void *)buf, (void *)u_nand_temp_buffer, len);
+	}else{
+#if (OOB_SW_PROTECT_SWITCH_ON == 1)
+		if(info->read_ptr > 0){
+			if(info->vir_page_size == 3072){
+				for(i = 0; i < oob_copy_number; i++){
+					u32 index = i * oob_byte_count + oob_byte_count;
+
+					checksum = nand_checksum32(&nand_ptr[i * oob_byte_count],
+						oob_byte_count - 4);
+					checksum_load = nand_ptr[index - 4];
+					checksum_load |= nand_ptr[index - 3] << 8;
+					checksum_load |= nand_ptr[index - 2] << 16;
+					checksum_load |= nand_ptr[index - 1] << 24;
+					if(checksum == checksum_load || checksum_load == ~0x0){
+						memcpy(oob_temp_ptr, &nand_ptr[i * oob_byte_count], oob_byte_count);
+						break;
+					}
+				}
+				if(i == oob_copy_number){
+					printf("3k oob ecc warning, data select!!!! \n");
+					nand_sw_ecc_check(nand_ptr,
+						oob_temp_ptr,
+						oob_copy_number,
+						oob_byte_count - 4);
+				}
+
+				nand_ptr = oob_temp_ptr;
+			}
+		}
+#endif
+		memcpy((void *)buf, (void *)nand_ptr, len);
+	}
+	info->read_ptr += len;
+
+#ifdef NAND_DEBUG_VERBOSE
+	rda_dump_buf((char *)buf, len);
+#endif
+
+#else
+	struct rda_dma_chan_params dma_param;
+	dma_addr_t phys_addr;
+	void *addr = (void *)buf;
+	int ret = 0;
+
+	/*
+	 * If size is less than the size of oob,
+	 * we copy directly them to mapping buffer.
+	 */
+	if (len <= mtd->oobsize) {
+		memcpy(buf, (void *)nand_ptr, len);
+		info->read_ptr = 0;
+		return;
+	}
+
+	if (((u32)addr & 0x7) != 0) {
+		printf("ERROR, nand dma read buffer %p is not 8bytes aligned\n",
+			addr);
+		return;
+	}
+
+	phys_addr = dma_map_single(addr, len, DMA_FROM_DEVICE);
+
+	dma_param.src_addr = (u32) info->nand_data_phys;
+	dma_param.dst_addr = phys_addr;
+	dma_param.xfer_size = len;
+	//dma_param.dma_mode = RDA_DMA_FR_MODE;
+	dma_param.dma_mode = RDA_DMA_NOR_MODE;
+
+	ret = rda_set_dma_params(info->dma_ch, &dma_param);
+	if (ret < 0) {
+		printf("rda nand : Failed to set parameter\n");
+		dma_unmap_single(addr, len, DMA_FROM_DEVICE);
+		return;
+	}
+
+	/* use flush to avoid annoying unaligned warning */
+	/* however, invalidate after the dma it the right thing to do */
+	flush_dcache_range((u32)addr, (u32)(addr + len));
+
+	rda_start_dma(info->dma_ch);
+	rda_poll_dma(info->dma_ch);
+	rda_stop_dma(info->dma_ch);
+
+	/* use flush to avoid annoying unaligned warning */
+	//invalidate_dcache_range((u32)addr, (u32)(addr + len));
+
+	/* Free the specified physical address */
+	dma_unmap_single(addr, len, DMA_FROM_DEVICE);
+	info->read_ptr += len;
+
+	return;
+#endif /* CONFIG_NAND_RDA_DMA */
+}
+
+static void nand_rda_write_buf(struct mtd_info *mtd, const uint8_t * buf,
+			       int len)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	u8 *nand_ptr = (u8 *) (chip->IO_ADDR_W + info->write_ptr);
+	u8 *u_nand_temp_buffer = &g_nand_flash_temp_buffer[info->write_ptr];
+	uint8_t *temp_ptr = (uint8_t *)buf;
+#if (OOB_SW_PROTECT_SWITCH_ON == 1)
+	uint8_t *oob_temp_ptr = &g_nand_flash_temp_buffer[16384+512];
+	uint8_t oob_byte_count = 2 + __FTL_OOB_STRUCT_LENGTH__ + 2 + 4;
+	uint8_t oob_copy_number = info->vir_oob_size / oob_byte_count;
+	uint32_t checksum;
+#endif
+
+#ifdef NAND_DEBUG
+	printf("write : buf addr = 0x%p, len = %d, write_ptr = %d\n", buf, len,
+	       info->write_ptr);
+#endif /* NAND_DEBUG */
+
+#ifdef NAND_DEBUG_VERBOSE
+	rda_dump_buf((char *)buf, len);
+#endif
+
+#if 1//ndef CONFIG_NAND_RDA_DMA
+	if(info->nand_use_type > 0){
+		if(info->write_ptr > 0){/*write OOB to buffer*/
+#if (OOB_SW_PROTECT_SWITCH_ON == 1)
+			if(info->vir_page_size == 6144 ||info->vir_page_size == 12288){
+				checksum = nand_checksum32(temp_ptr, oob_byte_count - 4);
+				memcpy(oob_temp_ptr, temp_ptr, oob_byte_count - 4);
+				oob_temp_ptr[oob_byte_count - 4] = (uint8_t)(checksum & 0xff);
+				oob_temp_ptr[oob_byte_count - 3] = (uint8_t)((checksum >> 8) & 0xff);
+				oob_temp_ptr[oob_byte_count - 2] = (uint8_t)((checksum >> 16) & 0xff);
+				oob_temp_ptr[oob_byte_count - 1] = (uint8_t)((checksum >> 24) & 0xff);
+				while(oob_copy_number > 1){
+					oob_copy_number--;
+					memcpy(&oob_temp_ptr[oob_copy_number * oob_byte_count],
+						oob_temp_ptr,
+						oob_byte_count);
+				}
+
+				temp_ptr = oob_temp_ptr;
+			}
+#endif
+			info->write_ptr = info->logic_page_size;
+			u_nand_temp_buffer = &g_nand_flash_temp_buffer[info->write_ptr];
+			memcpy((void *)u_nand_temp_buffer, (void *)temp_ptr, info->logic_oob_size);
+			memcpy((void *)(u_nand_temp_buffer + NAND_CONTROLLER_TEMP_BUFFER_SIZE),
+							(void *)(temp_ptr + info->logic_oob_size), info->logic_oob_size);
+			if(info->type == NAND_TYPE_SLC16K || info->type == NAND_TYPE_MLC16K){
+				memcpy((void *)(u_nand_temp_buffer + NAND_CONTROLLER_TEMP_BUFFER_SIZE * 2),
+							(void *)(temp_ptr + info->logic_oob_size * 2), info->logic_oob_size);
+				memcpy((void *)(u_nand_temp_buffer + NAND_CONTROLLER_TEMP_BUFFER_SIZE * 3),
+							(void *)(temp_ptr + info->logic_oob_size * 3), info->logic_oob_size);
+			}
+		}else{/*write data to buffer*/
+			memcpy((void *)u_nand_temp_buffer, (void *)temp_ptr, info->logic_page_size);
+			memcpy((void *)(u_nand_temp_buffer + NAND_CONTROLLER_TEMP_BUFFER_SIZE),
+							(void *)(temp_ptr + info->logic_page_size), info->logic_page_size);
+			if(info->type == NAND_TYPE_SLC16K || info->type == NAND_TYPE_MLC16K){
+				memcpy((void *)(u_nand_temp_buffer + NAND_CONTROLLER_TEMP_BUFFER_SIZE * 2),
+							(void *)(temp_ptr + info->logic_page_size * 2), info->logic_page_size);
+				memcpy((void *)(u_nand_temp_buffer + NAND_CONTROLLER_TEMP_BUFFER_SIZE * 3),
+							(void *)(temp_ptr + info->logic_page_size * 3), info->logic_page_size);
+			}
+			info->write_ptr += info->logic_page_size;
+		}
+	}else{
+#if (OOB_SW_PROTECT_SWITCH_ON == 1)
+		if(info->write_ptr > 0 && info->vir_page_size == 3072){
+			checksum = nand_checksum32(temp_ptr, oob_byte_count - 4);
+			memcpy(oob_temp_ptr, temp_ptr, oob_byte_count - 4);
+			oob_temp_ptr[oob_byte_count - 4] = (uint8_t)(checksum & 0xff);
+			oob_temp_ptr[oob_byte_count - 3] = (uint8_t)((checksum >> 8) & 0xff);
+			oob_temp_ptr[oob_byte_count - 2] = (uint8_t)((checksum >> 16) & 0xff);
+			oob_temp_ptr[oob_byte_count - 1] = (uint8_t)((checksum >> 24) & 0xff);
+			while(oob_copy_number > 1){
+				oob_copy_number--;
+				memcpy(&oob_temp_ptr[oob_copy_number * oob_byte_count],
+					oob_temp_ptr,
+					oob_byte_count);
+			}
+
+			temp_ptr = oob_temp_ptr;
+		}
+#endif
+		memcpy((void *)nand_ptr, (void *)temp_ptr, len);
+		info->write_ptr += len;
+	}
+#else
+	struct rda_dma_chan_params dma_param;
+	dma_addr_t phys_addr;
+	void *addr = (void *)buf;
+	int ret = 0;
+
+	/*
+	 * If size is less than the size of oob,
+	 * we copy directly them to mapping buffer.
+	 */
+	if (len <= mtd->oobsize) {
+		memcpy((void *)nand_ptr, (void *)buf, len);
+		info->write_ptr += len;
+		return;
+	}
+
+	if (((u32)addr & 0x7) != 0) {
+		printf("ERROR, nand dma write %p buffer is not 8bytes aligned\n",
+			addr);
+		return;
+	}
+	phys_addr = dma_map_single(addr, len, DMA_TO_DEVICE);
+
+	dma_param.src_addr = phys_addr;
+	dma_param.dst_addr = (u32) info->nand_data_phys;
+	dma_param.xfer_size = len;
+	//dma_param.dma_mode = RDA_DMA_FW_MODE;
+	dma_param.dma_mode = RDA_DMA_NOR_MODE;
+
+	ret = rda_set_dma_params(info->dma_ch, &dma_param);
+	if (ret < 0) {
+		printf("rda nand : Failed to set parameter\n");
+		dma_unmap_single(addr, len, DMA_TO_DEVICE);
+		return;
+	}
+
+	flush_dcache_range((u32)addr, (u32)(addr + len));
+
+	rda_start_dma(info->dma_ch);
+	rda_poll_dma(info->dma_ch);
+	rda_stop_dma(info->dma_ch);
+
+	/* Free the specified physical address */
+	dma_unmap_single(addr, len, DMA_TO_DEVICE);
+	info->write_ptr += len;
+
+	return;
+#endif /* CONFIG_NAND_RDA_DMA */
+}
+
+static void nand_rda_write_cache(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	u8 *nand_ptr = (u8 *) (chip->IO_ADDR_W + info->write_ptr);
+	u8 *u_nand_temp_buffer = &g_nand_flash_temp_buffer[info->col_addr];
+
+	if(info->nand_use_type > 0){
+#ifndef CONFIG_NAND_RDA_DMA
+		memcpy((void *)nand_ptr,
+			(void *)u_nand_temp_buffer,
+			NAND_CONTROLLER_TEMP_BUFFER_SIZE);
+#else
+		nand_rda_dma_move_data(mtd,
+			nand_ptr,
+			u_nand_temp_buffer,
+			NAND_CONTROLLER_TEMP_BUFFER_SIZE,
+			DMA_TO_DEVICE);
+#endif
+	}
+}
+
+static void nand_rda_do_cmd_pre(struct mtd_info *mtd)
+{
+	struct nand_chip *this = mtd->priv;
+	struct rda_nand_info *info = this->priv;
+
+	__raw_writel(0xfff, NANDFC_REG_INT_STAT);
+	switch (info->cmd) {
+	case NAND_CMD_SEQIN:
+		info->write_ptr = 0;
+		nand_rda_write_cache(mtd);
+		break;
+	case NAND_CMD_READ0:
+		hal_flush_buf(mtd);
+		//info->read_ptr = 0;
+		break;
+	case NAND_CMD_RNDIN:
+		nand_rda_write_cache(mtd);
+		break;
+	default:
+		break;
+	}
+}
+
+static void nand_rda_do_cmd_post(struct mtd_info *mtd)
+{
+	struct nand_chip *this = mtd->priv;
+	struct rda_nand_info *info = this->priv;
+	u32 temp;
+
+	switch (info->cmd) {
+	case NAND_CMD_RESET:
+		return;
+	case NAND_CMD_READID:
+		temp = __raw_readl(NANDFC_REG_IDCODE_A);
+		info->byte_buf[0] = temp;
+		temp = __raw_readl(NANDFC_REG_IDCODE_B);
+		info->byte_buf[1] = temp;
+		info->index = 0;
+		break;
+	case NAND_CMD_STATUS:
+		temp = __raw_readl(NANDFC_REG_OP_STATUS);
+		info->byte_buf[0] = (temp & 0xFF);
+		info->index = 0;
+		if (info->byte_buf[0] != 0xe0) {
+			printf("nand error in op status %x\n",
+			       info->byte_buf[0]);
+		}
+#ifdef NAND_DEBUG
+		printf("post_cmd read status %x\n", info->byte_buf[0]);
+#endif
+		break;
+	case NAND_CMD_READ0:	// NAND_CMD_READOOB goes here too
+		nand_rda_read_cache(mtd);
+		info->index = 0;
+		if(NAND_CMD_READOOB == info->cmd_flag){
+			if(info->nand_use_type > 0){
+				temp = g_nand_flash_temp_buffer[mtd->writesize];
+				temp |= g_nand_flash_temp_buffer[mtd->writesize+1] << 8;
+				info->byte_buf[0] = temp;
+			}else{
+				u8 *nand_ptr = (u8 *) (this->IO_ADDR_R + mtd->writesize);
+				memcpy((u8*)&info->byte_buf[0], nand_ptr, 2);
+			}
+			info->cmd_flag = NAND_CMD_NONE;
+		}
+		break;
+	case NAND_CMD_SEQIN:
+		if(info->nand_use_type > 0){
+			info->logic_operate_time += 1;
+			info->col_addr += NAND_CONTROLLER_TEMP_BUFFER_SIZE;
+			info->cmd = NAND_CMD_RNDIN;
+		}
+		break;
+	case NAND_CMD_RNDIN:
+		if(info->nand_use_type > 0){
+			info->logic_operate_time += 1;
+			info->col_addr += NAND_CONTROLLER_TEMP_BUFFER_SIZE;
+		}
+		break;
+/* delay 10ms, for erase to complete */
+	case NAND_CMD_ERASE1:
+		udelay(10000);
+		break;
+
+	default:
+		break;
+	}
+}
+
+static void nand_rda_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+#ifdef NAND_DEBUG
+        printf("nand_rda_hwcontrol, cmd = %x, ctrl = %x, not use anymore\n",
+               cmd, ctrl);
+#endif
+}
+
+static void nand_rda_cmdfunc(struct mtd_info *mtd, unsigned int command,
+			     int column, int page_addr)
+{
+	register struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	unsigned long cmd_ret;
+
+#ifdef NAND_DEBUG
+	printf("nand_rda_cmdfunc, cmd = %x, page_addr = %x, col_addr = %x\n",
+	       command, page_addr, column);
+#endif
+
+	/* remap command */
+	switch (command) {
+	case NAND_CMD_SEQIN:	/* 0x80 do nothing, wait for 0x10 */
+		info->page_addr = page_addr;
+		info->col_addr = column;
+		info->cmd = NAND_CMD_NONE;
+		info->write_ptr= column;
+		info->logic_operate_time = 0;
+		break;
+	case NAND_CMD_READSTART:	/* hw auto gen 0x30 for read */
+	case NAND_CMD_ERASE2:	/* hw auto gen 0xd0 for erase */
+#ifdef NAND_DEBUG
+		printf("erase block, erase_size = %x\n", mtd->erasesize);
+#endif
+		info->cmd = NAND_CMD_NONE;
+		break;
+	case NAND_CMD_PAGEPROG:	/* 0x10 do the real program */
+		info->cmd = NAND_CMD_SEQIN;
+		info->col_addr = 0;
+		break;
+	case NAND_CMD_READOOB:	/* Emulate NAND_CMD_READOOB */
+		info->page_addr = page_addr;
+		info->cmd = NAND_CMD_READ0;
+		/* Offset of oob */
+		info->col_addr = column;
+		info->read_ptr = mtd->writesize;
+		info->cmd_flag = NAND_CMD_READOOB;
+		break;
+	case NAND_CMD_READ0:	/* Emulate NAND_CMD_READOOB */
+		info->read_ptr = 0;
+		/*fall though, don't need break;*/
+	default:
+		info->page_addr = page_addr;
+		info->col_addr = column;
+		info->cmd = command;
+		break;
+	}
+	if (info->cmd == NAND_CMD_NONE) {
+		return;
+	}
+	//info->col_addr >>= 1;
+#ifdef NAND_DEBUG
+	printf("after cmd remap, cmd = %x, page_addr = %x, col_addr = %x\n",
+	       info->cmd, info->page_addr, info->col_addr);
+#endif
+
+loop:
+	if (info->col_addr != -1) {
+		hal_set_col_addr(info->col_addr);
+	}
+	if (info->page_addr == -1)
+		info->page_addr = 0;
+
+	nand_rda_do_cmd_pre(mtd);
+
+	hal_send_cmd((unsigned char)info->cmd, info->page_addr);
+	cmd_ret = hal_wait_cmd_complete();
+	if (cmd_ret) {
+		printf("cmd fail, cmd = %x, page_addr = %x, col_addr = %x\n",
+		       info->cmd, info->page_addr, info->col_addr);
+	}
+
+	nand_rda_do_cmd_post(mtd);
+
+	if(info->nand_use_type > 0 && info->logic_operate_time <= info->nand_use_type && \
+		(info->cmd == NAND_CMD_SEQIN || info->cmd == NAND_CMD_RNDIN))
+		goto loop;
+
+	nand_wait_ready(mtd);
+}
+
+static int nand_rda_dev_ready(struct mtd_info *mtd)
+{
+	return 1;
+}
+
+static int nand_reset_flash(void)
+{
+	int ret = 0;
+
+	hal_send_cmd(NAND_CMD_RESET, 0);
+	ret = hal_wait_cmd_complete();
+	if (ret) {
+		printf("reset flash failed\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+static int nand_read_id(unsigned int id[2])
+{
+	int ret = 0;
+
+	hal_send_cmd(NAND_CMD_READID, 0);
+	ret = hal_wait_cmd_complete();
+	if (ret) {
+		printf("nand_read_id failed\n");
+		return ret;
+	}
+
+	id[0] = __raw_readl(NANDFC_REG_IDCODE_A);
+	id[1] = __raw_readl(NANDFC_REG_IDCODE_B);
+
+	printf("Nand ID: %08x %08x\n", id[0], id[1]);
+
+	return ret;
+}
+
+static void read_ID(struct mtd_info *mtd)
+{
+	unsigned int id[2];
+
+	nand_read_id(id);
+}
+
+#if(__TGT_AP_FLASH_USE_PART_OF_PAGE__ == 1)
+static void nand_page_type_setting(struct rda_nand_info *info, int *bus_width_16)
+{
+#if(__TGT_AP_FLASH_LOGIC_PAGE_SIZE_N_KB__ == __TGT_AP_FLASH_USE_4KAS3K_PAGE_DIV__)
+	printf("MLC 4K as 3K, %s bus\n", (*bus_width_16)?"16bit":"8bit");
+	info->spl_adjust_ratio = 3;//actally ratio * 2
+#else
+#if(__TGT_AP_FLASH_LOGIC_PAGE_SIZE_N_KB__ == __TGT_AP_FLASH_USE_4KAS2K_PAGE_DIV__)
+	printf("MLC 4K as 2K, %s bus\n", (*bus_width_16)?"16bit":"8bit");
+	info->spl_adjust_ratio = 2;//actally ratio * 2
+#endif
+#endif
+
+#if(__TGT_AP_FLASH_LOGIC_PAGE_SIZE_N_KB__ == __TGT_AP_FLASH_USE_8KAS4K_PAGE_DIV__)
+	printf("MLC 8K as 4K, %s bus\n", (*bus_width_16)?"16bit":"8bit");
+	info->spl_adjust_ratio = 4;//actally ratio * 2
+#else
+#if(__TGT_AP_FLASH_LOGIC_PAGE_SIZE_N_KB__ == __TGT_AP_FLASH_USE_8KAS6K_PAGE_DIV__)
+	printf("MLC 8K as 6K, %s bus\n", (*bus_width_16)?"16bit":"8bit");
+	info->spl_adjust_ratio = 6;//actally ratio * 2
+#endif
+#endif
+
+#if(__TGT_AP_FLASH_LOGIC_PAGE_SIZE_N_KB__ == __TGT_AP_FLASH_USE_16KAS8K_PAGE_DIV__)
+	printf("MLC 16K as 8K, %s bus\n", (*bus_width_16)?"16bit":"8bit");
+	info->spl_adjust_ratio = 8;//actally ratio * 2
+#else
+#if(__TGT_AP_FLASH_LOGIC_PAGE_SIZE_N_KB__ == __TGT_AP_FLASH_USE_16KAS12K_PAGE_DIV__)
+	printf("MLC 16K as 12K, %s bus\n", (*bus_width_16)?"16bit":"8bit");
+	info->spl_adjust_ratio = 12;//actally ratio * 2
+#endif
+#endif
+}
+#endif
+
+/********************************************************************************
+******************page size bits(bit[1...0] of the fourth id byte)***************
+1.hynix nand
+ 1) bit1  bit0  pagesize       2) bit1  bit0  pagesize
+      0    0        2K             0    0        4K
+      0    1        4k             0    1        8K
+      1    0        8k             1    0        16K
+      1    1        null           1    1        32K
+ nand ID:
+ (1)AD D7 94 DA 74 C3          (1)AD D7 94 91 60 44
+*********************************************************************************/
+static int nand_get_type(struct rda_nand_info *info, unsigned int id[2],
+		int *rda_nand_type, int *bus_width_16)
+{
+	u16 hwcfg_nand_type;
+	int metal_id;
+
+	info->spl_adjust_ratio = 2;
+	metal_id = rda_metal_id_get();
+
+#if defined(CONFIG_MACH_RDA8810) || defined(CONFIG_MACH_RDA8850)
+	printf("RDA8810/RDA8850 get type, metal %d\n", metal_id);
+
+	if (metal_id == 0) {
+		hwcfg_nand_type = rda_hwcfg_get() & 0x03;
+		switch(hwcfg_nand_type) {
+		case 0b00:
+			printf("MLC 4K, 8bit bus\n");
+			*rda_nand_type = NAND_TYPE_MLC4K;
+			*bus_width_16 = 0;
+			break;
+		case 0b10:
+			printf("SLC 4K page, 16bit bus\n");
+			*rda_nand_type = NAND_TYPE_SLC4K;
+			*bus_width_16 = 1;
+			break;
+		case 0b01:
+			printf("2K page, 8bit bus\n");
+			*rda_nand_type = NAND_TYPE_2KL;
+			*bus_width_16 = 0;
+			break;
+		case 0b11:
+			printf("2K page, 16bit bus\n");
+			*rda_nand_type = NAND_TYPE_2KL;
+			*bus_width_16 = 1;
+			break;
+		default:
+			printf("NAND: type %d not support\n", hwcfg_nand_type);
+			*rda_nand_type = NAND_TYPE_INVALID;
+			return -ENODEV;
+		}
+	}
+	else if ((metal_id == 2) || (metal_id == 1)) {
+		hwcfg_nand_type = rda_hwcfg_get() & 0x03;
+		switch(hwcfg_nand_type) {
+		case 0b00:
+			printf("SLC 4K, 16bit bus\n");
+			*rda_nand_type = NAND_TYPE_SLC4K;
+			*bus_width_16 = 1;
+			break;
+		case 0b10:
+			printf("MLC 4K, 8bit bus\n");
+			*rda_nand_type = NAND_TYPE_MLC4K;
+			*bus_width_16 = 0;
+			break;
+		case 0b11:
+			printf("MLC 8K, 8bit bus\n");
+			*rda_nand_type = NAND_TYPE_MLC8K;
+			*bus_width_16 = 0;
+			break;
+		default:
+			printf("NAND: type %d not support\n", hwcfg_nand_type);
+			*rda_nand_type = NAND_TYPE_INVALID;
+			return -ENODEV;
+		}
+	}
+	else if (metal_id >= 3) {
+#define RDA_NAND_TYPE_BIT_TYPE    (1 << 0)    /* 1: MLC; 0: SLC */
+#define RDA_NAND_TYPE_BIT_BUS     (1 << 1)    /* 1: 8-bit; 0: 16-bit */
+#define RDA_NAND_TYPE_BIT_SIZE    (1 << 7)    /* 1: 4K SLC / 8K MLC; 0: 2K SLC / 4K MLC */
+		hwcfg_nand_type = rda_hwcfg_get() & 0x83;
+		if (hwcfg_nand_type & RDA_NAND_TYPE_BIT_BUS)
+			*bus_width_16 = 0;
+		else
+			*bus_width_16 = 1;
+		if (hwcfg_nand_type & RDA_NAND_TYPE_BIT_TYPE) {
+			if (hwcfg_nand_type & RDA_NAND_TYPE_BIT_SIZE) {
+				printf("MLC 8K, %s bus\n",
+					(*bus_width_16)?"16bit":"8bit");
+				*rda_nand_type = NAND_TYPE_MLC8K;
+			} else {
+#if(__TGT_AP_FLASH_USE_PART_OF_PAGE__ == 1)
+				switch(id[0] & 0xff){
+				case NAND_MFR_HYNIX:
+					if(id[0] == 0xda94d7ad || id[0] == 0x9e14d7ad){//hynix for nanya
+						*rda_nand_type = NAND_TYPE_MLC8K;
+					}else{
+						switch((id[0] >> 24)&0x3){//MLC
+						case 0:
+							*rda_nand_type = NAND_TYPE_MLC4K;
+							break;
+						case 1:
+							*rda_nand_type = NAND_TYPE_MLC8K;
+							break;
+						case 2:
+							*rda_nand_type = NAND_TYPE_MLC16K;
+							break;
+						case 3:
+							*rda_nand_type = NAND_TYPE_MLC16K;//reserved for 32k
+							break;
+						}
+					}
+					break;
+				case NAND_MFR_TOSHIBA://mlc
+				case NAND_MFR_SAMSUNG:
+					switch((id[0] >> 24)&0x3){
+					case 0:
+						printf("nand:no 2k MLC nand.\n");
+						break;
+					case 1:
+						*rda_nand_type = NAND_TYPE_MLC4K;
+						break;
+					case 2:
+						*rda_nand_type = NAND_TYPE_MLC8K;
+						break;
+					case 3:
+						*rda_nand_type = NAND_TYPE_MLC16K;
+						break;
+					}
+					break;
+				default:
+					switch((id[0] >> 24)&0x3){
+					case 0:
+						printf("nand:not support 1k nand.\n");
+						break;
+					case 1:
+						printf("nand:no 2k MLC nand.\n");
+						break;
+					case 2:
+						*rda_nand_type = NAND_TYPE_MLC4K;
+						break;
+					case 3:
+						*rda_nand_type = NAND_TYPE_MLC8K;
+						break;
+					}
+					break;
+				}
+				nand_page_type_setting(info, bus_width_16);
+#else
+				printf("MLC 4K, %s bus\n", (*bus_width_16)?"16bit":"8bit");
+				*rda_nand_type = NAND_TYPE_MLC4K;
+#endif
+			}
+		} else {
+			if (hwcfg_nand_type & RDA_NAND_TYPE_BIT_SIZE) {
+					printf("SLC 4K, %s bus\n", (*bus_width_16)?"16bit":"8bit");
+					*rda_nand_type = NAND_TYPE_SLC4K;
+			} else {
+				printf("SLC 2KL, %s bus\n",
+					(*bus_width_16)?"16bit":"8bit");
+				*rda_nand_type = NAND_TYPE_2KL;
+			}
+		}
+	}
+	else {
+		printf("NAND: invalid metal id %d\n", metal_id);
+		return -ENODEV;
+	}
+#elif defined(CONFIG_MACH_RDA8810E) || defined(CONFIG_MACH_RDA8820)
+#error "RDA8810E/RDA8820 does not match RDA NAND Controller V1"
+#else
+#error "unknown MACH"
+#endif
+
+	printf("SPL adjust ratio is %d. \n", info->spl_adjust_ratio);
+	return 0;
+}
+
+static int nand_rda_init(struct nand_chip *this, struct rda_nand_info *info)
+{
+	unsigned int id[2];
+	int ret = 0;
+	int rda_nand_type = NAND_TYPE_INVALID;
+	int bus_width_16 = 0;
+
+	ret = nand_reset_flash();
+	if (ret)
+		return ret;
+	ret = nand_read_id(id);
+	if (ret)
+		return ret;
+	ret = nand_get_type(info, id, &rda_nand_type, &bus_width_16);
+	if (ret)
+		return ret;
+	ret = init_nand_info(info, rda_nand_type, bus_width_16);
+	if (ret)
+		return ret;
+	if (info->bus_width_16)
+		this->options |= NAND_BUSWIDTH_16;
+
+	return hal_init(info);
+}
+
+static 	int nand_rda_init_size(struct mtd_info *mtd, struct nand_chip *this,
+			u8 *id_data)
+{
+	struct rda_nand_info *info = this->priv;
+
+	mtd->erasesize = info->vir_erase_size;
+	mtd->writesize = info->vir_page_size;
+	mtd->oobsize = info->vir_oob_size;
+
+	return (info->bus_width_16) ? NAND_BUSWIDTH_16 : 0;
+}
+
+int rda_nand_init(struct nand_chip *nand)
+{
+	struct rda_nand_info *info;
+	static struct rda_nand_info rda_nand_info;
+
+	info = &rda_nand_info;
+
+	nand->chip_delay = 0;
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
+	nand->options |= NAND_USE_FLASH_BBT;
+#endif
+	/*
+	 * in fact, nand controler we do hardware ECC silently, and
+	 * we don't need tell mtd layer, and will simple nand operations
+	*/
+	nand->ecc.mode = NAND_ECC_NONE;
+	/* Set address of hardware control function */
+	nand->cmd_ctrl = nand_rda_hwcontrol;
+	nand->init_size = nand_rda_init_size;
+	nand->cmdfunc = nand_rda_cmdfunc;
+
+	nand->read_byte = nand_rda_read_byte;
+	nand->read_word = nand_rda_read_word;
+	nand->read_buf = nand_rda_read_buf;
+	nand->write_buf = nand_rda_write_buf;
+	nand->read_nand_ID = read_ID;
+	nand->dev_ready = nand_rda_dev_ready;
+
+	nand->priv = (void *)info;
+	nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)NANDFC_DATA_BUF;
+#ifdef CONFIG_NAND_RDA_DMA
+	info->nand_data_phys = (void __iomem *)NANDFC_DATA_BUF;
+#endif /* CONFIG_NAND_RDA_DMA */
+	info->index = 0;
+	info->write_ptr = 0;
+	info->read_ptr = 0;
+	info->cmd_flag = NAND_CMD_NONE;
+	info->master_clk = get_master_clk_rate(_TGT_AP_CLK_APB2);
+	info->clk=_TGT_AP_NAND_CLOCK;
+
+#ifdef CONFIG_NAND_RDA_DMA
+	rda_request_dma(&info->dma_ch);
+#endif /* CONFIG_NAND_RDA_DMA */
+
+	 nand_rda_init(nand, info);
+
+	if (!nand->ecc.layout && (nand->ecc.mode != NAND_ECC_SOFT_BCH)) {
+		switch (info->vir_oob_size) {
+		case 64:
+			nand->ecc.layout = &rda_nand_oob_64;
+			break;
+		case 128:
+			nand->ecc.layout = &rda_nand_oob_128;
+			break;
+		case 256:
+			nand->ecc.layout = &rda_nand_oob_256;
+			break;
+		case 512:
+			nand->ecc.layout = &rda_nand_oob_512;
+			break;
+		default:
+			printf("error oob size: %d \n", info->vir_oob_size);
+		}
+	}
+
+	return 0;
+}
+
+#else
+int rda_nand_init(struct nand_chip *nand) {return 0;}
+#endif
+
+#if 0
+/* move to rda_nand_base.c */
+int board_nand_init(struct nand_chip *chip) __attribute__ ((weak));
+
+int board_nand_init(struct nand_chip *chip)
+{
+	return rda_nand_init(chip);
+}
+#endif
diff --git a/drivers/mtd/nand/rda_nand_v2.c b/drivers/mtd/nand/rda_nand_v2.c
new file mode 100644
index 0000000000..925a1c81c8
--- /dev/null
+++ b/drivers/mtd/nand/rda_nand_v2.c
@@ -0,0 +1,941 @@
+#include <common.h>
+#include <malloc.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <nand.h>
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/reg_nand.h>
+#include <asm/arch/reg_sysctrl.h>
+#include <asm/arch/hwcfg.h>
+#include <mtd/nand/rda_nand.h>
+
+#include "tgt_ap_board_config.h"
+#include "tgt_ap_clock_config.h"
+
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_NAND_RDA_DMA
+#endif
+
+#ifdef CONFIG_NAND_RDA_DMA
+#include <asm/dma-mapping.h>
+#include <asm/arch/dma.h>
+#endif
+
+//#define NAND_DEBUG
+//#define NAND_DEBUG_VERBOSE
+
+#define NAND_NEED_OOB_OFF_FIX
+#ifdef NAND_NEED_OOB_OFF_FIX
+static uint8_t oob_ff_pattern[] = { 0xff, 0xff }; 
+#define NAND_4K_86_OOB_OFF      0x10B8
+#define NAND_8K_86_OOB_OFF      0x2170
+#define NAND_8K_83_OOB_OFF      0x23C0
+#endif
+
+#define hal_gettime     get_ticks
+#define SECOND          * CONFIG_SYS_HZ_CLOCK
+#define NAND_TIMEOUT    ( 2 SECOND )
+#define PLL_BUS_FREQ	(_TGT_AP_PLL_BUS_FREQ * 1000000)
+
+/* clock division value map */
+const static u8 clk_div_map[] = {
+	4*60,	/* 0 */
+	4*60,	/* 1 */
+	4*60,	/* 2 */
+	4*60,	/* 3 */
+	4*60,	/* 4 */
+	4*60,	/* 5 */
+	4*60,	/* 6 */
+	4*60,	/* 7 */
+	4*40,	/* 8 */
+	4*30,	/* 9 */
+	4*24,	/* 10 */
+	4*20,	/* 11 */
+	4*17,	/* 12 */
+	4*15,	/* 13 */
+	4*13,	/* 14 */
+	4*12,	/* 15 */
+	4*11,	/* 16 */
+	4*10,	/* 17 */
+	4*9,	/* 18 */
+	4*8,	/* 19 */
+	4*7,	/* 20 */
+	4*13/2,	/* 21 */
+	4*6,	/* 22 */
+	4*11/2,	/* 23 */
+	4*5,	/* 24 */
+	4*9/2,	/* 25 */
+	4*4,	/* 26 */
+	4*7/2,	/* 27 */
+	4*3,	/* 28 */
+	4*5/2,	/* 29 */
+	4*2,	/* 30 */
+	4*1,	/* 31 */
+};
+
+static struct nand_ecclayout rda_nand_oob_40 = {
+	.eccbytes = 0,
+	.eccpos = {},
+	.oobfree = {
+		{.offset = 2,
+		 .length = 38} }
+};
+
+static struct nand_ecclayout rda_nand_oob_64 = {
+	.eccbytes = 0,
+	.eccpos = {},
+	.oobfree = {
+		{.offset = 2,
+		 .length = 62} }
+};
+
+static struct nand_ecclayout rda_nand_oob_128 = {
+	.eccbytes = 0,
+	.eccpos = {},
+	.oobfree = {
+		{.offset = 2,
+		 .length = 126} }
+};
+
+static struct nand_ecclayout rda_nand_oob_256 = {
+	.eccbytes = 0,
+	.eccpos = {},
+	.oobfree = {
+		{.offset = 2,
+		 .length = 254} }
+};
+
+static struct nand_ecclayout rda_nand_oob_512 = {
+	.eccbytes = 0,
+	.eccpos = {},
+	.oobfree = {
+		{.offset = 2,
+		 .length = 510} }
+};
+
+extern void rda_dump_buf(char *data, size_t len);
+
+static void hal_send_cmd(unsigned char cmd, unsigned int page_addr)
+{
+	unsigned long cmd_reg;
+
+	cmd_reg = NANDFC_DCMD(cmd) | NANDFC_PAGE_ADDR(page_addr);
+#ifdef NAND_DEBUG
+	printf("  hal_send_cmd 0x%08lx\n", cmd_reg);
+#endif
+	__raw_writel(cmd_reg, NANDFC_REG_DCMD_ADDR);
+}
+
+static void hal_set_col_addr(unsigned int col_addr)
+{
+	__raw_writel(col_addr, NANDFC_REG_COL_ADDR);
+}
+
+static void hal_flush_buf(struct mtd_info *mtd)
+{
+	/*
+	 there is no reg NANDFC_REG_BUF_CTRL
+	 */
+	//__raw_writel(0x7, NANDFC_REG_BUF_CTRL);
+}
+
+static unsigned long hal_wait_cmd_complete(void)
+{
+	unsigned long int_stat;
+	unsigned long long wait_time = NAND_TIMEOUT;
+	unsigned long long start_time = hal_gettime();
+	int timeout = 0;
+
+	/* wait done */
+	/*
+	 * Use NANDFC_INT_STAT_IDLE instead of NANDFC_INT_DONE
+	 * this is HW bug, NANDFC_INT_DONE comes too early
+	 * however, NANDFC_INT_STAT_IDLE is not an interrupt source
+	 * need HW fix anyway
+	 */
+	do {
+		int_stat = __raw_readl(NANDFC_REG_INT_STAT);
+		if (hal_gettime() - start_time >= wait_time) {
+			timeout = 1;
+		}
+#ifdef CONFIG_MACH_RDA8810E
+	} while (!(int_stat & NANDFC_INT_STAT_IDLE) && !timeout);
+#else
+	} while (!(int_stat & NANDFC_INT_DONE) && !timeout);
+#endif
+
+	/* to clear */
+	__raw_writel(int_stat & NANDFC_INT_CLR_MASK, NANDFC_REG_INT_STAT);
+
+	if (timeout) {
+		printf("nand error, cmd timeout\n");
+		return -ETIME;
+	}
+
+	if (int_stat & NANDFC_INT_ERR_ALL) {
+		printf("nand error, int_stat = %lx\n", int_stat);
+		return (int_stat & NANDFC_INT_ERR_ALL);
+	}
+	return 0;
+}
+
+static int init_nand_info(struct rda_nand_info *info,
+			int nand_type, int nand_ecc, int bus_width_16)
+{
+	info->type = nand_type;
+	info->ecc_mode = nand_ecc;
+	info->bus_width_16 = bus_width_16;
+	switch (nand_type) {
+	case NAND_TYPE_2K:
+		info->page_size = 2048;
+		info->page_shift = 11;
+		info->oob_size = 64;
+		break;
+	case NAND_TYPE_4K:
+		info->page_size = 4096;
+		info->page_shift = 12;
+		info->oob_size = 224;
+		info->vir_oob_size = 40;
+		break;
+	case NAND_TYPE_8K:
+		info->page_size = 8192;
+		info->page_shift = 13;
+		info->oob_size = 744;
+		break;
+	default:
+		printf("invalid nand type %d\n", nand_type);
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static u32 cal_freq_by_divreg(u32 basefreq, u32 reg, u32 div2)
+{
+	u32 newfreq;
+
+	if (reg >= ARRAY_SIZE(clk_div_map)) {
+		printf("nand:Invalid div reg: %u\n", reg);
+		reg = ARRAY_SIZE(clk_div_map) - 1;
+	}
+	/* Assuming basefreq is smaller than 2^31 (2.147G Hz) */
+	newfreq = (basefreq << (div2 ? 0 : 1)) / (clk_div_map[reg] >> 1);
+	return newfreq;
+}
+
+unsigned long get_master_clk_rate(u32 reg)
+{
+	u32 div2;
+	unsigned long rate;
+
+	div2 = reg & SYS_CTRL_AP_AP_APB2_SRC_SEL;
+	reg = GET_BITFIELD(reg, SYS_CTRL_AP_AP_APB2_FREQ);
+	rate = cal_freq_by_divreg(PLL_BUS_FREQ, reg, div2);
+
+	return rate;
+}
+
+static unsigned long rda_nand_cld_div_tbl[16] = {
+	3, 4, 5, 6, 7, 8, 9, 10,
+	12, 14, 16, 18, 20, 22, 24, 28
+};
+
+static unsigned long hal_calc_divider(struct rda_nand_info *info)
+{
+	unsigned long mclk = info->master_clk;
+	unsigned long div, clk_div;
+	int i;
+
+	div = mclk / info->clk;
+	if (mclk % info->clk)
+		div += 1;
+
+	if (div < 5) {
+		/* 5 is minimal divider by V2 hardware */
+		div = 5;
+	}
+
+	for (i=0;i<16;i++) {
+		if(div <= rda_nand_cld_div_tbl[i]) {
+			clk_div = i;
+			break;
+		}
+	}
+
+	if (i>=16) {
+		clk_div = 15;
+	}
+
+	printf("NAND: max clk: %ld, bus clk: %ld\n", info->clk, mclk);
+	printf("NAND: div: %ld, clk_div: %ld\n", div, clk_div);
+	return clk_div;
+}
+
+static int hal_init(struct rda_nand_info *info)
+{
+	unsigned long config_a, config_b;
+#ifdef CONFIG_RDA_FPGA
+	unsigned long clk_div = 4;
+#else
+	unsigned long clk_div = hal_calc_divider(info);
+#endif
+
+	/* setup config_a and config_b */
+	config_a = NANDFC_CYCLE(clk_div);
+	config_a |= NANDFC_CHIP_SEL(0x0e);
+	config_a |= NANDFC_POLARITY_IO(0);	// set 0 invert IO
+	config_a |= NANDFC_POLARITY_MEM(1);	// set 1 invert MEM
+
+	switch (info->type) {
+	case NAND_TYPE_2K:
+		config_a |= NANDFC_TIMING(0x8B);
+		break;
+	case NAND_TYPE_4K:
+		config_a |= NANDFC_TIMING(0x8C);
+		break;
+	case NAND_TYPE_8K:
+		config_a |= NANDFC_TIMING(0x8D);
+		break;
+	default:
+		printf("invalid nand type %d\n", info->type);
+		return -EINVAL;
+	}
+
+	/* enable the 16bit mode; */
+	if (info->bus_width_16)
+		config_a |= NANDFC_WDITH_16BIT(1);
+
+	config_b = NANDFC_HWECC(1) | NANDFC_ECC_MODE(info->ecc_mode);
+
+	__raw_writel(config_a, NANDFC_REG_CONFIG_A);
+	__raw_writel(config_b, NANDFC_REG_CONFIG_B);
+
+#if 1
+	/* Set an interval of filter for erasing operation. */
+	unsigned long delay;
+	delay = __raw_readl(NANDFC_REG_DELAY);
+	delay |= 0x10;
+	__raw_writel(delay, NANDFC_REG_DELAY);
+#endif /* #if 0 */
+
+	printf("NAND: nand init done, %08lx %08lx\n", config_a, config_b);
+
+	return 0;
+}
+
+static u8 nand_rda_read_byte(struct mtd_info *mtd)
+{
+	u8 ret;
+	struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	ret = *((u8 *) info->byte_buf + info->index);
+	info->index++;
+#ifdef NAND_DEBUG
+	printf("nand_read_byte, ret = %02x\n", ret);
+#endif
+	return ret;
+}
+
+static u16 nand_rda_read_word(struct mtd_info *mtd)
+{
+	u16 ret;
+	struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	ret = *(u16 *) ((uint8_t *) info->byte_buf + info->index);
+	info->index += 2;
+#ifdef NAND_DEBUG
+	printf("nand_read_word, ret = %04x\n", ret);
+#endif
+	return ret;
+}
+
+static void nand_rda_read_buf(struct mtd_info *mtd, uint8_t * buf, int len)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	u8 *nand_ptr = (u8 *) (chip->IO_ADDR_R + info->read_ptr);
+
+#ifdef NAND_DEBUG
+	printf("read : buf addr = 0x%p, len = 0x%x, read_ptr = 0x%x \n", buf, len,
+	       info->read_ptr);
+#endif /* NAND_DEBUG */
+
+#ifndef CONFIG_NAND_RDA_DMA
+	memcpy((void *)buf, (void *)nand_ptr, len);
+	if(info->ecc_mode == NAND_ECC_1K24BIT)
+		info->read_ptr += 184;
+	info->read_ptr += len;
+
+#ifdef NAND_DEBUG_VERBOSE
+	rda_dump_buf((char *)buf, 2);
+#endif
+
+#else
+	struct rda_dma_chan_params dma_param;
+	dma_addr_t phys_addr;
+	void *addr = (void *)buf;
+	int ret = 0;
+
+	/*
+	 * If size is less than the size of oob,
+	 * we copy directly them to mapping buffer.
+	 */
+	if (len <= mtd->oobsize) {
+		memcpy(buf, (void *)nand_ptr, len);
+		info->read_ptr = 0;
+		return;
+	}
+
+	if (((u32)addr & 0x7) != 0) {
+		printf("ERROR, nand dma read buffer %p is not 8bytes aligned\n",
+			addr);
+		return;
+	}
+
+	phys_addr = dma_map_single(addr, len, DMA_FROM_DEVICE);
+
+	dma_param.src_addr = (u32) info->nand_data_phys;
+	dma_param.dst_addr = phys_addr;
+	dma_param.xfer_size = len;
+	//dma_param.dma_mode = RDA_DMA_FR_MODE;
+	dma_param.dma_mode = RDA_DMA_NOR_MODE;
+
+	ret = rda_set_dma_params(info->dma_ch, &dma_param);
+	if (ret < 0) {
+		printf("rda nand : Failed to set parameter\n");
+		dma_unmap_single(addr, len, DMA_FROM_DEVICE);
+		return;
+	}
+
+	/* use flush to avoid annoying unaligned warning */
+	/* however, invalidate after the dma it the right thing to do */
+	flush_dcache_range((u32)addr, (u32)(addr + len));
+
+	rda_start_dma(info->dma_ch);
+	rda_poll_dma(info->dma_ch);
+	rda_stop_dma(info->dma_ch);
+
+	/* use flush to avoid annoying unaligned warning */
+	//invalidate_dcache_range((u32)addr, (u32)(addr + len));
+
+	/* Free the specified physical address */
+	dma_unmap_single(addr, len, DMA_FROM_DEVICE);
+	info->read_ptr += len;
+
+	return;
+#endif /* CONFIG_NAND_RDA_DMA */
+}
+
+static void nand_rda_write_buf(struct mtd_info *mtd, const uint8_t * buf,
+			       int len)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	u8 *nand_ptr = (u8 *) (chip->IO_ADDR_W + info->write_ptr);
+
+#ifdef NAND_DEBUG
+	printf("write : buf addr = 0x%p, len = %d, write_ptr = %d\n", buf, len,
+	       info->write_ptr);
+#endif /* NAND_DEBUG */
+
+#ifdef NAND_DEBUG_VERBOSE
+	rda_dump_buf((char *)buf, len);
+#endif
+
+#ifdef NAND_NEED_OOB_OFF_FIX
+	u8 *nand_oob_ptr;
+	switch (info->type) {
+	case NAND_TYPE_2K:
+		break;
+	case NAND_TYPE_4K:
+		if(info->write_ptr > 0 && info->ecc_mode == NAND_ECC_1K24BIT){
+			nand_ptr = (u8 *)(chip->IO_ADDR_W + NAND_4K_86_OOB_OFF);
+			len = 40;
+		}
+		break;
+	case NAND_TYPE_8K:
+		if (info->ecc_mode == NAND_ECC_1K24BIT)
+			nand_oob_ptr = (u8 *)(chip->IO_ADDR_W + 
+				NAND_8K_86_OOB_OFF);
+		else
+			nand_oob_ptr = (u8 *)(chip->IO_ADDR_W + 
+				NAND_8K_83_OOB_OFF);
+		memcpy((void *)nand_oob_ptr, (void *)oob_ff_pattern, 2);
+		break;
+	default:
+		break;
+	}
+#endif
+
+#ifndef CONFIG_NAND_RDA_DMA
+	memcpy((void *)nand_ptr, (void *)buf, len);
+	info->write_ptr += len;
+
+#else
+	struct rda_dma_chan_params dma_param;
+	dma_addr_t phys_addr;
+	void *addr = (void *)buf;
+	int ret = 0;
+
+	/*
+	 * If size is less than the size of oob,
+	 * we copy directly them to mapping buffer.
+	 */
+	if (len <= mtd->oobsize) {
+		memcpy((void *)nand_ptr, (void *)buf, len);
+		info->write_ptr += len;
+		return;
+	}
+
+	if (((u32)addr & 0x7) != 0) {
+		printf("ERROR, nand dma write %p buffer is not 8bytes aligned\n",
+			addr);
+		return;
+	}
+	phys_addr = dma_map_single(addr, len, DMA_TO_DEVICE);
+
+	dma_param.src_addr = phys_addr;
+	dma_param.dst_addr = (u32) info->nand_data_phys;
+	dma_param.xfer_size = len;
+	//dma_param.dma_mode = RDA_DMA_FW_MODE;
+	dma_param.dma_mode = RDA_DMA_NOR_MODE;
+
+	ret = rda_set_dma_params(info->dma_ch, &dma_param);
+	if (ret < 0) {
+		printf("rda nand : Failed to set parameter\n");
+		dma_unmap_single(addr, len, DMA_TO_DEVICE);
+		return;
+	}
+
+	flush_dcache_range((u32)addr, (u32)(addr + len));
+
+	rda_start_dma(info->dma_ch);
+	rda_poll_dma(info->dma_ch);
+	rda_stop_dma(info->dma_ch);
+
+	/* Free the specified physical address */
+	dma_unmap_single(addr, len, DMA_TO_DEVICE);
+	info->write_ptr += len;
+
+	return;
+#endif /* CONFIG_NAND_RDA_DMA */
+}
+
+static void nand_rda_do_cmd_pre(struct mtd_info *mtd)
+{
+	struct nand_chip *this = mtd->priv;
+	struct rda_nand_info *info = this->priv;
+
+	__raw_writel(0xfff, NANDFC_REG_INT_STAT);
+	switch (info->cmd) {
+	case NAND_CMD_SEQIN:
+		hal_flush_buf(mtd);
+		info->write_ptr = 0;
+		break;
+	case NAND_CMD_READ0:
+		hal_flush_buf(mtd);
+		//info->read_ptr = 0;
+		break;
+	default:
+		break;
+	}
+}
+
+static void nand_rda_do_cmd_post(struct mtd_info *mtd)
+{
+	struct nand_chip *this = mtd->priv;
+	struct rda_nand_info *info = this->priv;
+	u32 temp;
+
+	switch (info->cmd) {
+	case NAND_CMD_RESET:
+		return;
+	case NAND_CMD_READID:
+		temp = __raw_readl(NANDFC_REG_IDCODE_A);
+		info->byte_buf[0] = temp;
+		temp = __raw_readl(NANDFC_REG_IDCODE_B);
+		info->byte_buf[1] = temp;
+		info->index = 0;
+		break;
+	case NAND_CMD_STATUS:
+		temp = __raw_readl(NANDFC_REG_OP_STATUS);
+		info->byte_buf[0] = (temp & 0xFF);
+		info->index = 0;
+		if (info->byte_buf[0] != 0xe0) {
+			printf("nand error in op status %x\n",
+			       info->byte_buf[0]);
+		}
+#ifdef NAND_DEBUG
+		printf("post_cmd read status %x\n", info->byte_buf[0]);
+#endif
+		break;
+	case NAND_CMD_READ0:	// NAND_CMD_READOOB goes here too
+		break;
+#if 0
+/* read back after write, for err checking */
+	case NAND_CMD_SEQIN:
+		{
+			int cmd_ret;
+			/* read back instantly and check fcs/crc result */
+			hal_send_cmd((unsigned char)NAND_CMD_READ0,
+				     info->page_addr);
+			cmd_ret = hal_wait_cmd_complete();
+			if (cmd_ret) {
+				printf
+				    ("readback cmd fail, page_addr = %x, ret = %x\n",
+				     info->page_addr, cmd_ret);
+			}
+		}
+		break;
+#endif
+#if 0
+/* delay 10ms, for erase to complete */
+	case NAND_CMD_ERASE1:
+		udelay(10000);
+		break;
+#endif
+	default:
+		break;
+	}
+}
+
+static void nand_rda_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+#ifdef NAND_DEBUG
+        printf("nand_rda_hwcontrol, cmd = %x, ctrl = %x, not use anymore\n",
+               cmd, ctrl);
+#endif
+}
+
+static void nand_rda_cmdfunc(struct mtd_info *mtd, unsigned int command,
+			     int column, int page_addr)
+{
+	register struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	unsigned long cmd_ret;
+
+#ifdef NAND_DEBUG
+	printf("nand_rda_cmdfunc, cmd = %x, page_addr = %x, col_addr = %x\n",
+	       command, page_addr, column);
+#endif
+
+	/* remap command */
+	switch (command) {
+	case NAND_CMD_SEQIN:	/* 0x80 do nothing, wait for 0x10 */
+		info->page_addr = page_addr;
+		info->col_addr = column;
+		info->cmd = NAND_CMD_NONE;
+		info->write_ptr= column;
+		break;
+	case NAND_CMD_READSTART:	/* hw auto gen 0x30 for read */
+	case NAND_CMD_ERASE2:	/* hw auto gen 0xd0 for erase */
+#ifdef NAND_DEBUG
+		printf("erase block, erase_size = %x\n", mtd->erasesize);
+#endif
+		info->cmd = NAND_CMD_NONE;
+		break;
+	case NAND_CMD_PAGEPROG:	/* 0x10 do the real program */
+		info->cmd = NAND_CMD_SEQIN;
+		info->col_addr = 0;
+		break;
+	case NAND_CMD_READOOB:	/* Emulate NAND_CMD_READOOB */
+		info->page_addr = page_addr;
+		info->cmd = NAND_CMD_READ0;
+		/* Offset of oob */
+		info->col_addr = column;
+		info->read_ptr = mtd->writesize;
+#ifdef NAND_NEED_OOB_OFF_FIX
+		switch (info->type) {
+		case NAND_TYPE_2K:
+			break;
+		case NAND_TYPE_4K:
+			//info->col_addr = NAND_4K_86_OOB_OFF;
+			info->read_ptr = NAND_4K_86_OOB_OFF;
+			break;
+		case NAND_TYPE_8K:
+			if (info->ecc_mode == NAND_ECC_1K24BIT) {
+				info->col_addr = NAND_8K_86_OOB_OFF;
+				info->read_ptr = NAND_8K_86_OOB_OFF;
+			}
+			else {
+				info->col_addr = NAND_8K_83_OOB_OFF;
+				info->read_ptr = NAND_8K_83_OOB_OFF;
+			}
+			break;
+		default:
+			break;
+		}
+#endif
+		break;
+	case NAND_CMD_READ0:	/* Emulate NAND_CMD_READOOB */
+		info->read_ptr = 0;
+		/*fall though, don't need break;*/
+	default:
+		info->page_addr = page_addr;
+		info->col_addr = column;
+		info->cmd = command;
+		break;
+	}
+	if (info->cmd == NAND_CMD_NONE) {
+		return;
+	}
+	//info->col_addr >>= 1;
+#ifdef NAND_DEBUG
+	printf("after cmd remap, cmd = %x, page_addr = %x, col_addr = %x\n",
+	       info->cmd, info->page_addr, info->col_addr);
+#endif
+
+	if (info->col_addr != -1) {
+		hal_set_col_addr(info->col_addr);
+	}
+	if (info->page_addr == -1)
+		info->page_addr = 0;
+
+	nand_rda_do_cmd_pre(mtd);
+
+	hal_send_cmd((unsigned char)info->cmd, info->page_addr);
+	cmd_ret = hal_wait_cmd_complete();
+	if (cmd_ret) {
+		printf("cmd fail, cmd = %x, page_addr = %x, col_addr = %x\n",
+		       info->cmd, info->page_addr, info->col_addr);
+	}
+
+	nand_rda_do_cmd_post(mtd);
+
+	nand_wait_ready(mtd);
+}
+
+static int nand_rda_dev_ready(struct mtd_info *mtd)
+{
+	return 1;
+}
+
+static int nand_reset_flash(void)
+{
+	int ret = 0;
+
+	hal_send_cmd(NAND_CMD_RESET, 0);
+	ret = hal_wait_cmd_complete();
+	if (ret) {
+		printf("nand_reset_flash failed\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+static int nand_read_id(unsigned int id[2])
+{
+	int ret = 0;
+
+	hal_send_cmd(NAND_CMD_READID, 0);
+	ret = hal_wait_cmd_complete();
+	if (ret) {
+		printf("nand_read_id failed\n");
+		return ret;
+	}
+
+	id[0] = __raw_readl(NANDFC_REG_IDCODE_A);
+	id[1] = __raw_readl(NANDFC_REG_IDCODE_B);
+
+	printf("NAND: Nand ID: %08x %08x\n", id[0], id[1]);
+
+	return ret;
+}
+
+static void read_ID(struct mtd_info *mtd)
+{
+	unsigned int id[2];
+
+	nand_read_id(id);
+}
+
+static int nand_get_type(struct rda_nand_info *info, unsigned int id[2],
+		int *rda_nand_type, int *rda_nand_ecc, int *bus_width_16)
+{
+	u16 hwcfg_nand_type;
+	int metal_id;
+
+	info->spl_adjust_ratio = 2;
+	metal_id = rda_metal_id_get();
+
+#if defined(CONFIG_MACH_RDA8810) || defined(CONFIG_MACH_RDA8850)
+#error "RDA8810/RDA8850 does not match RDA NAND Controller V2"
+#elif defined(CONFIG_MACH_RDA8810E) || defined(CONFIG_MACH_RDA8820)
+	printf("NAND: RDA8810E/RDA8820 get type, metal %d\n", metal_id);
+	if (1) {
+#define RDA_NAND_TYPE_BIT_7       (1 << 7)    /* 1: 8K NAND, 0 - 2K/4K NAND */
+#define RDA_NAND_TYPE_BIT_BUS     (1 << 1)    /* 1: 8-bit; 0: 16-bit */
+#define RDA_NAND_TYPE_BIT_0       (1 << 0)    /* if BIT_7 == 1 (8K NAND)  : 1 - 1K64bit ECC, 0 - 1K24bit ECC */
+                                              /* if BIT_7 == 0 (4K/2K)    : 1 - 4K(1K24bit), 0 - 2K(2K24bit) */
+		hwcfg_nand_type = rda_hwcfg_get() & 0x83;
+		if (hwcfg_nand_type & RDA_NAND_TYPE_BIT_BUS)
+			*bus_width_16 = 0;
+		else
+			*bus_width_16 = 1;
+		if (hwcfg_nand_type & RDA_NAND_TYPE_BIT_7) {
+			/* 8K */
+			*rda_nand_type = NAND_TYPE_8K;
+			if (hwcfg_nand_type & RDA_NAND_TYPE_BIT_0) {
+				printf("NAND: 8K page, 1K64BIT ECC, %s bus\n",
+					(*bus_width_16)?"16bit":"8bit");
+				*rda_nand_ecc = NAND_ECC_1K64BIT;
+			} else {
+				printf("NAND: 8K page, 1K24BIT ECC, %s bus\n",
+					(*bus_width_16)?"16bit":"8bit");
+				*rda_nand_ecc = NAND_ECC_1K24BIT;
+			}
+		} else {
+			/* 4K/2K */
+			if (hwcfg_nand_type & RDA_NAND_TYPE_BIT_0) {
+				printf("NAND: 4K page, 1K24BIT ECC, %s bus\n",
+					(*bus_width_16)?"16bit":"8bit");
+				*rda_nand_type = NAND_TYPE_4K;
+				*rda_nand_ecc = NAND_ECC_1K24BIT;
+			} else {
+				printf("NAND: 2K page, 2K24BIT ECC, %s bus\n",
+					(*bus_width_16)?"16bit":"8bit");
+				*rda_nand_type = NAND_TYPE_2K;
+				*rda_nand_ecc = NAND_ECC_2K24BIT;
+			}
+		}
+	}
+#else
+#error "unknown MACH"
+#endif
+
+	printf("NAND: actually ratio * 2, SPL adjust ratio is %d. \n",
+		info->spl_adjust_ratio);
+	return 0;
+}
+
+static int nand_rda_init(struct nand_chip *this, struct rda_nand_info *info)
+{
+	unsigned int id[2];
+	int ret = 0;
+	int rda_nand_type = NAND_TYPE_INVALID;
+	int rda_nand_ecc = NAND_ECC_INVALID;
+	int bus_width_16 = 0;
+
+	ret = nand_reset_flash();
+	if (ret)
+		return ret;
+	ret = nand_read_id(id);
+	if (ret)
+		return ret;
+	ret = nand_get_type(info, id, &rda_nand_type, &rda_nand_ecc, &bus_width_16);
+	if (ret)
+		return ret;
+	ret = init_nand_info(info, rda_nand_type, rda_nand_ecc, bus_width_16);
+	if (ret)
+		return ret;
+	if (info->bus_width_16)
+		this->options |= NAND_BUSWIDTH_16;
+
+	return hal_init(info);
+}
+
+#if defined(CONFIG_SPL_BUILD)
+/* this is for u-boot-spl only */
+static int nand_rda_init_size(struct mtd_info *mtd, struct nand_chip *this,
+			u8 *id_data)
+{
+	struct rda_nand_info *info = this->priv;
+
+	/* TODO: this is not always right
+	 * assuming nand is 2k/4k SLC for now
+	 * for other types of nand, 64 pages per block is not always true
+	 */
+	mtd->erasesize = info->page_size * 64;
+	mtd->writesize = info->page_size;
+	mtd->oobsize = (info->oob_size > 256)?256:info->oob_size;
+
+	return (info->bus_width_16) ? NAND_BUSWIDTH_16 : 0;
+}
+#endif
+
+int rda_nand_init(struct nand_chip *nand)
+{
+	struct rda_nand_info *info;
+	static struct rda_nand_info rda_nand_info;
+
+	info = &rda_nand_info;
+
+	nand->chip_delay = 0;
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
+	nand->options |= NAND_USE_FLASH_BBT;
+#endif
+	/*
+	 * in fact, nand controler we do hardware ECC silently, and
+	 * we don't need tell mtd layer, and will simple nand operations
+	*/
+	nand->ecc.mode = NAND_ECC_NONE;
+	/* Set address of hardware control function */
+	nand->cmd_ctrl = nand_rda_hwcontrol;
+#if defined(CONFIG_SPL_BUILD)
+	nand->init_size = nand_rda_init_size;
+#else
+	nand->init_size = NULL;
+#endif
+	nand->cmdfunc = nand_rda_cmdfunc;
+
+	nand->read_nand_ID = read_ID;
+	nand->read_byte = nand_rda_read_byte;
+	nand->read_word = nand_rda_read_word;
+	nand->read_buf = nand_rda_read_buf;
+	nand->write_buf = nand_rda_write_buf;
+
+	nand->dev_ready = nand_rda_dev_ready;
+
+	nand->priv = (void *)info;
+	nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)NANDFC_DATA_BUF;
+#ifdef CONFIG_NAND_RDA_DMA
+	info->nand_data_phys = (void __iomem *)NANDFC_DATA_BUF;
+#endif /* CONFIG_NAND_RDA_DMA */
+	info->index = 0;
+	info->write_ptr = 0;
+	info->read_ptr = 0;
+	info->master_clk = get_master_clk_rate(_TGT_AP_CLK_APB2);
+	info->clk=_TGT_AP_NAND_CLOCK;
+
+#ifdef CONFIG_NAND_RDA_DMA
+	rda_request_dma(&info->dma_ch);
+#endif /* CONFIG_NAND_RDA_DMA */
+
+	 nand_rda_init(nand, info);
+
+	if (!nand->ecc.layout && (nand->ecc.mode != NAND_ECC_SOFT_BCH)) {
+		switch (info->vir_oob_size) {
+		case 40:
+			nand->ecc.layout = &rda_nand_oob_40;
+			break;
+		case 64:
+			nand->ecc.layout = &rda_nand_oob_64;
+			break;
+		case 128:
+			nand->ecc.layout = &rda_nand_oob_128;
+			break;
+		case 256:
+			nand->ecc.layout = &rda_nand_oob_256;
+			break;
+		case 512:
+			nand->ecc.layout = &rda_nand_oob_512;
+			break;
+		default:
+			printf("error oob size: %d \n", info->vir_oob_size);
+		}
+	}
+
+	return 0;
+}
+
+#if 0
+/* move to rda_nand_base.c */
+int board_nand_init(struct nand_chip *chip) __attribute__ ((weak));
+
+int board_nand_init(struct nand_chip *chip)
+{
+	return rda_nand_init(chip);
+}
+#endif
diff --git a/drivers/mtd/nand/rda_nand_v3.c b/drivers/mtd/nand/rda_nand_v3.c
new file mode 100644
index 0000000000..f603bc143a
--- /dev/null
+++ b/drivers/mtd/nand/rda_nand_v3.c
@@ -0,0 +1,2050 @@
+#include <common.h>
+#include <malloc.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <nand.h>
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/reg_nand.h>
+#include <asm/arch/reg_sysctrl.h>
+#include <asm/arch/hwcfg.h>
+#include <asm/arch-rda/ispi.h>
+#include <mtd/nand/rda_nand.h>
+
+#include "tgt_ap_board_config.h"
+#include "tgt_ap_clock_config.h"
+#include "tgt_ap_flash_parts.h"
+
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_NAND_RDA_DMA
+#endif
+
+#ifdef CONFIG_NAND_RDA_DMA
+#include <asm/dma-mapping.h>
+#include <asm/arch/dma.h>
+#endif
+
+/* FOR NAND TEST */
+#ifdef TGT_AP_DO_NAND_TEST
+
+unsigned int gbl_nand_test_id_val[2];
+unsigned char g_nand_test_buf_write[4096] = {0};
+unsigned char g_nand_test_buf_read[4096] = {0};
+#endif /* TGT_AP_DO_NAND_TEST */
+
+//#define NAND_DEBUG
+//#define NAND_DEBUG_VERBOSE
+#define NAND_CONTROLLER_BUFFER_LEN 9216
+
+#define hal_gettime     get_ticks
+#define SECOND          * CONFIG_SYS_HZ_CLOCK
+#define NAND_TIMEOUT    ( 2 SECOND )
+#define PLL_BUS_FREQ	(_TGT_AP_PLL_BUS_FREQ * 1000000)
+
+#ifdef CONFIG_SPL_BUILD
+/*sram space is not enough, so use sdram space as middle data buffer*/
+static u8 *g_nand_flash_temp_buffer = (u8 *)CONFIG_SPL_NAND_MIDDLE_DATA_BUFFER;
+#else
+static u8 g_nand_flash_temp_buffer[32*1024];
+#endif
+
+#define ECCSIZE(n) ((n)*15/8)
+static const u8 g_nand_ecc_size[] = {
+	ECCSIZE(24),
+	ECCSIZE(96),
+	ECCSIZE(96),
+	ECCSIZE(64),
+	ECCSIZE(56),
+	ECCSIZE(40),
+	ECCSIZE(24),
+	ECCSIZE(48),
+	ECCSIZE(32),
+	ECCSIZE(16),
+	ECCSIZE(8),
+	ECCSIZE(72),
+	ECCSIZE(80),
+	ECCSIZE(88),
+};
+
+struct flash_nand_parameter {
+	unsigned int page_size;
+	unsigned int ecc_msg_len;
+	unsigned int spare_space_size;
+	unsigned int oob_size;
+	unsigned int ecc_bits;
+	unsigned int spl_offset;
+	unsigned int crc;
+};
+
+struct flash_nand_parameter nand_parameter;
+
+/* clock division value map */
+const static u8 clk_div_map[] = {
+	4*60,	/* 0 */
+	4*60,	/* 1 */
+	4*60,	/* 2 */
+	4*60,	/* 3 */
+	4*60,	/* 4 */
+	4*60,	/* 5 */
+	4*60,	/* 6 */
+	4*60,	/* 7 */
+	4*40,	/* 8 */
+	4*30,	/* 9 */
+	4*24,	/* 10 */
+	4*20,	/* 11 */
+	4*17,	/* 12 */
+	4*15,	/* 13 */
+	4*13,	/* 14 */
+	4*12,	/* 15 */
+	4*11,	/* 16 */
+	4*10,	/* 17 */
+	4*9,	/* 18 */
+	4*8,	/* 19 */
+	4*7,	/* 20 */
+	4*13/2,	/* 21 */
+	4*6,	/* 22 */
+	4*11/2,	/* 23 */
+	4*5,	/* 24 */
+	4*9/2,	/* 25 */
+	4*4,	/* 26 */
+	4*7/2,	/* 27 */
+	4*3,	/* 28 */
+	4*5/2,	/* 29 */
+	4*2,	/* 30 */
+	4*1,	/* 31 */
+};
+
+static struct nand_ecclayout rda_nand_oob_2k = {
+	.eccbytes = 0,
+	.eccpos = {},
+	.oobfree = {
+		{.offset = 2,
+		 .length = 30} }
+};
+
+static struct nand_ecclayout rda_nand_oob_4k = {
+	.eccbytes = 0,
+	.eccpos = {},
+	.oobfree = {
+		{.offset = 2,
+		 .length = 30} }
+};
+
+static struct nand_ecclayout rda_nand_oob_8k = {
+	.eccbytes = 0,
+	.eccpos = {},
+	.oobfree = {
+		{.offset = 2,
+		 .length = 30} }
+};
+
+static struct nand_ecclayout rda_nand_oob_16k = {
+	.eccbytes = 0,
+	.eccpos = {},
+	.oobfree = {
+		{.offset = 2,
+		 .length = 30} }
+};
+
+extern void rda_dump_buf(char *data, size_t len);
+
+static unsigned int checksum32( unsigned char* data, unsigned int data_size)
+{
+	unsigned int checksum = 0;
+	unsigned int i;
+
+	for(i = 0; i < data_size; i++)
+		checksum = ((checksum << 31) | (checksum >> 1)) + (unsigned int)data[i];
+
+	return checksum;
+}
+
+static void fill_nand_parameter(void)
+{
+	nand_parameter.page_size = NAND_PAGE_SIZE;
+	nand_parameter.spare_space_size = NAND_SPARE_SIZE;
+	nand_parameter.ecc_bits = NAND_ECCBITS;
+	nand_parameter.ecc_msg_len = NAND_ECCMSGLEN;
+	nand_parameter.oob_size = NAND_OOBSIZE;
+	nand_parameter.spl_offset = NAND_PAGE_SIZE;
+	nand_parameter.crc = checksum32((unsigned char *)&nand_parameter,
+		sizeof(struct flash_nand_parameter) - 4);
+}
+
+static void hal_send_cmd_brick(unsigned char data, unsigned char io16,
+			unsigned short num, unsigned char next_act)
+{
+	unsigned long cmd_reg;
+
+	cmd_reg = NANDFC_BRICK_DATA(data)
+		| NANDFC_BRICK_W_WIDTH(io16)
+		| NANDFC_BRICK_R_WIDTH(io16)
+		| NANDFC_BRICK_DATA_NUM(num)
+		| NANDFC_BRICK_NEXT_ACT(next_act);
+	__raw_writel(cmd_reg, NANDFC_REG_BRICK_FIFO_WRITE_POINTER);
+#ifdef NAND_DEBUG
+	printf("  hal_send_cmd_brick 0x%08lx\n", cmd_reg);
+#endif
+}
+
+static void hal_start_cmd_data(void)
+{
+	unsigned long cmd_reg;
+
+	cmd_reg = __raw_readl(NANDFC_REG_CONFIG_A);
+	cmd_reg |= NANDFC_CMDFULL_STA(1);
+
+	__raw_writel(cmd_reg, NANDFC_REG_CONFIG_A);
+}
+
+#ifdef __SCRAMBLE_ENABLE__
+static void hal_set_scramble_func(BOOL enable)
+{
+	unsigned long cmd_reg;
+
+	cmd_reg = __raw_readl(NANDFC_REG_CONFIG_A);
+	cmd_reg &=  ~ NANDFC_SCRAMBLE_ENABLE(1);
+	cmd_reg |= NANDFC_SCRAMBLE_ENABLE(enable);
+
+	__raw_writel(cmd_reg, NANDFC_REG_CONFIG_A);
+}
+#endif
+
+/*
+static void hal_set_col_addr(unsigned int col_addr)
+{
+	__raw_writel(col_addr, NANDFC_REG_COL_ADDR);
+}
+*/
+
+static void hal_flush_buf(struct mtd_info *mtd)
+{
+	/*
+	 there is no reg NANDFC_REG_BUF_CTRL
+	 */
+	//__raw_writel(0x7, NANDFC_REG_BUF_CTRL);
+}
+
+static unsigned long hal_wait_cmd_complete(void)
+{
+	unsigned long int_stat;
+	unsigned long long wait_time = NAND_TIMEOUT;
+	unsigned long long start_time = hal_gettime();
+	int timeout = 0;
+
+	/* wait done */
+	/*
+	 * Use NANDFC_INT_STAT_IDLE instead of NANDFC_INT_DONE
+	 * this is HW bug, NANDFC_INT_DONE comes too early
+	 * however, NANDFC_INT_STAT_IDLE is not an interrupt source
+	 * need HW fix anyway
+	 */
+	do {
+		int_stat = __raw_readl(NANDFC_REG_INT_STAT);
+		if (hal_gettime() - start_time >= wait_time) {
+			timeout = 1;
+		}
+	} while (!(int_stat & NANDFC_INT_DONE) && !timeout);
+
+	/* to clear */
+	__raw_writel(int_stat & NANDFC_INT_CLR_MASK, NANDFC_REG_INT_STAT);
+
+	if (timeout) {
+		printf("nand error, cmd timeout\n");
+		return -ETIME;
+	}
+
+	if (int_stat & NANDFC_INT_ERR_ALL) {
+		printf("nand error, int_stat = %lx\n", int_stat);
+		return (int_stat & NANDFC_INT_ERR_ALL);
+	}
+	return 0;
+}
+
+static u16 nand_cal_message_num_size(struct rda_nand_info *info,
+					u16 * message_num, u16* msg_ecc_size)
+{
+	u16 num, mod, ecc_size, page_size, oob_size, message_len, ecc_mode;
+
+	page_size	= info->vir_page_size;
+	oob_size 	= info->oob_size;
+	message_len	= info->message_len;
+	ecc_mode 	= info->ecc_mode;
+	
+	num = page_size / message_len;
+	mod = page_size % message_len;
+	if (mod)
+		num += 1;
+	else
+		mod = message_len;
+
+	ecc_size =  g_nand_ecc_size[ecc_mode];
+	if (ecc_size % 2)
+		ecc_size = ecc_size + 1;
+
+	if (ecc_size * num > (oob_size - info->vir_oob_size)){
+		printf("Error:ecc used bytes has passed the oob size\n");
+		//return 0;
+	}
+
+	*message_num = num;
+	*msg_ecc_size = ecc_size;
+	return mod;
+}
+
+static unsigned char get_nand_eccmode(unsigned short ecc_bits)
+{
+	unsigned char i;
+
+	if(ecc_bits < 8 || ecc_bits > 96 || (ecc_bits % 8) != 0) {
+		printf("wrong ecc_bits, nand controller not support! \n");
+		return 0xff;
+	}
+
+	for(i = 0; i < ARRAY_SIZE(g_nand_ecc_size); i++) {
+		if(ECCSIZE(ecc_bits) == g_nand_ecc_size[i]) {
+			return i;
+		}
+	}
+
+	return 0;
+}
+
+static uint8_t nand_eccmode_autoselect(struct rda_nand_info *info)
+{
+	u16 num, mod, ecc_size, ecc_bits, max_ecc_parity_num;
+
+	ecc_bits = 96;
+	max_ecc_parity_num = info->oob_size - info->vir_oob_size;
+
+	num = info->vir_page_size / info->message_len;
+	mod = info->vir_page_size % info->message_len;
+	if (mod)
+		num += 1;
+
+	while(ecc_bits >= 8) {
+		ecc_size = ECCSIZE(ecc_bits);
+		if (ecc_size % 2)
+			ecc_size = ecc_size + 1;
+
+		if (ecc_size * num > max_ecc_parity_num){
+			ecc_bits -= 8;
+		} else
+			break;
+	}
+
+	return get_nand_eccmode(ecc_bits);
+}
+
+static int init_nand_info(struct rda_nand_info *info)
+{
+	u16 message_num = 0, message_mod;
+	u16 msg_ecc_size = 0, page_ecc_size;
+	u16 bch_kk = 0, bch_nn = 0, bch_oob_kk = 0, bch_oob_nn = 0;
+
+	info->hard_ecc_hec = 0;
+	info->nand_use_type = 1;
+	info->oob_size = NAND_SPARE_SIZE;
+	info->vir_erase_size = NAND_BLOCK_SIZE;
+
+	if (info->parameter_mode_select  == NAND_PARAMETER_BY_GPIO) {
+		switch (info->type) {
+		case NAND_TYPE_2K:
+			info->vir_page_size = 2048;
+			info->vir_page_shift = 11;
+			break;
+		case NAND_TYPE_4K:
+			info->vir_page_size = 4096;
+			info->vir_page_shift = 12;
+			break;
+		case NAND_TYPE_8K:
+			info->vir_page_size = 8192;
+			info->vir_page_shift = 13;
+			break;
+		case NAND_TYPE_16K:
+			info->vir_page_size = 16384;
+			info->vir_page_shift = 14;
+			break;
+		default:
+			printf("invalid nand type %d\n", info->type);
+			return -EINVAL;
+		}
+
+		info->max_eccmode_support = nand_eccmode_autoselect(info);
+	} else {
+		info->vir_page_size = nand_parameter.page_size;
+		if (is_power_of_2(info->vir_page_size))
+			info->vir_page_shift = ffs(info->vir_page_size) - 1;
+		else
+			info->vir_page_shift = 0;
+
+		if (nand_parameter.spare_space_size) {
+			info->ecc_mode = nand_eccmode_autoselect(info);
+		} else {
+			info->ecc_mode = get_nand_eccmode(nand_parameter.ecc_bits);
+		}
+	}
+	info->ecc_mode_bak = info->ecc_mode;
+	info->type_bak = info->type;
+	info->cmd_flag = 0;
+	info->dump_debug_flag = 0;
+	message_mod = nand_cal_message_num_size(info, &message_num, &msg_ecc_size);
+	page_ecc_size = msg_ecc_size * message_num;
+
+	info->page_total_num = info->vir_page_size + info->vir_oob_size + page_ecc_size;
+	info->flash_oob_off = info->vir_page_size + page_ecc_size - msg_ecc_size;
+
+	bch_kk =  info->message_len;
+	bch_nn = bch_kk + g_nand_ecc_size[info->ecc_mode];
+	info->bch_data= NANDFC_BCH_KK_DATA(bch_kk) | NANDFC_BCH_NN_DATA(bch_nn);
+
+	bch_oob_kk = message_mod + info->vir_oob_size;
+	bch_oob_nn = bch_oob_kk + g_nand_ecc_size[info->ecc_mode];
+	info->bch_oob = NANDFC_BCH_KK_OOB(bch_oob_kk) | NANDFC_BCH_NN_OOB(bch_oob_nn) ;
+
+	return 0;
+}
+
+static u32 cal_freq_by_divreg(u32 basefreq, u32 reg, u32 div2)
+{
+	u32 newfreq;
+
+	if (reg >= ARRAY_SIZE(clk_div_map)) {
+		printf("nand:Invalid div reg: %u\n", reg);
+		reg = ARRAY_SIZE(clk_div_map) - 1;
+	}
+	/* Assuming basefreq is smaller than 2^31 (2.147G Hz) */
+	newfreq = (basefreq << (div2 ? 0 : 1)) / (clk_div_map[reg] >> 1);
+	return newfreq;
+}
+
+unsigned long get_master_clk_rate(u32 reg)
+{
+	u32 div2;
+	unsigned long rate;
+
+	div2 = reg & SYS_CTRL_AP_AP_APB2_SRC_SEL;
+	reg = GET_BITFIELD(reg, SYS_CTRL_AP_AP_APB2_FREQ);
+	rate = cal_freq_by_divreg(PLL_BUS_FREQ, reg, div2);
+
+	return rate;
+}
+
+#ifndef CONFIG_RDA_FPGA
+static unsigned long rda_nand_clk_div_tbl[] = {
+	2, 3, 4, 5, 6, 7, 8, 9, 10,
+	12, 14, 16, 18, 20, 22, 24,26, 28, 30, 32, 40
+};
+#endif
+
+static unsigned long hal_calc_divider(struct rda_nand_info *info)
+{
+#ifdef CONFIG_RDA_FPGA
+	return 7;
+#else
+	unsigned long mclk = info->master_clk;
+	unsigned long div, clk_div;
+	int i;
+	int size = ARRAY_SIZE(rda_nand_clk_div_tbl);
+
+	div = mclk / info->clk;
+	if (mclk % info->clk)
+		div += 1;
+
+	for (i = 0; i < size; i++) {
+		if(div <= rda_nand_clk_div_tbl[i]) {
+			clk_div = i;
+			break;
+		}
+	}
+
+	if (i >= size) {
+		clk_div = size - 1;
+	}
+
+	printf("NAND: max clk: %ld, bus clk: %ld\n", info->clk, mclk);
+	printf("NAND: div: %ld, clk_div: %ld\n", div, clk_div);
+	return clk_div;
+#endif
+}
+
+static int hal_init(struct rda_nand_info *info)
+{
+	unsigned long config_a, config_b,page_para,message_oob;
+	unsigned long clk_div = hal_calc_divider(info);
+	uint16_t msg_package_num, msg_package_mod;
+
+	__raw_writel((1 << 23), NANDFC_REG_CONFIG_A);
+	__raw_writel(0, NANDFC_REG_CONFIG_A);
+
+	/* setup config_a and config_b */
+	config_a = NANDFC_CYCLE(clk_div);
+	config_a |= NANDFC_CHIP_SEL(0x0e);
+	config_a |= NANDFC_POLARITY_IO(0);	// set 0 invert IO
+	config_a |= NANDFC_POLARITY_MEM(1);	// set 1 invert MEM
+	config_a |= NANDFC_BRICK_COMMAND(1);
+
+	/* enable the 16bit mode; */
+	if (info->bus_width_16)
+		config_a |= NANDFC_WDITH_16BIT(1);
+
+	config_a |= (1 << 20);
+
+	config_b = NANDFC_HWECC(1) | NANDFC_ECC_MODE(info->ecc_mode);
+
+	msg_package_num = info->vir_page_size/info->message_len;
+	msg_package_mod = info->vir_page_size%info->message_len;
+	if(msg_package_mod)
+		msg_package_num += 1;
+	else
+		msg_package_mod = info->vir_page_size;
+       /*16k page nand need program twice one page*/
+	/*package num need change when program if not time of 2*/
+	if (info->type == NAND_TYPE_16K || info->type == NAND_TYPE_14K)
+		msg_package_num >>= 1;
+
+	message_oob = NANDFC_OOB_SIZE(info->vir_oob_size) |
+		NANDFC_MESSAGE_SIZE(msg_package_num * info->message_len);
+	/*page size is not used, but package num is used*/
+	page_para = NANDFC_PAGE_SIZE(info->page_total_num) |
+		NANDFC_PACKAGE_NUM(msg_package_num);
+
+	__raw_writel(config_a, NANDFC_REG_CONFIG_A);
+	__raw_writel(config_b, NANDFC_REG_CONFIG_B);
+	__raw_writel(page_para, NANDFC_REG_PAGE_PARA);
+	if (msg_package_num == 1)
+		info->bch_data = info->bch_oob;
+	__raw_writel(info->bch_data, NANDFC_REG_BCH_DATA);
+	__raw_writel(info->bch_oob, NANDFC_REG_BCH_OOB);
+	__raw_writel(message_oob, NANDFC_REG_MESSAGE_OOB_SIZE);
+	__raw_writel(0x80008000, NANDFC_REG_IRBN_COUNT);
+	__raw_writel(0x20202020, NANDFC_REG_BRICK_FSM_TIME0);
+	__raw_writel(0x00006020, NANDFC_REG_BRICK_FSM_TIME1);
+	__raw_writel(0x80000000, NANDFC_REG_BRICK_FSM_TIME2);
+	printf("bch_data=0x%x, bch_oob=0x%x, page_total=0x%x, oob=0x%x \n",
+		info->bch_data, info->bch_oob, info->page_total_num, info->vir_oob_size);
+	printf("page_para=0x%08lx, message_oob=0x%08lx\n", page_para, message_oob);
+	printf("NAND: nand init done, config=0x%08lx configb=0x%08lx\n", config_a, config_b);
+
+	return 0;
+}
+
+static int nand_eccmode_setting(struct rda_nand_info *info,
+	NAND_BCHMODE_TYPE eccmode)
+{
+	u16 message_num = 0, message_mod;
+	u16 msg_ecc_size = 0, page_ecc_size;
+	u16 bch_kk = 0, bch_nn = 0, bch_oob_kk = 0, bch_oob_nn = 0;
+	unsigned long config_b,page_para,message_oob;
+
+	info->ecc_mode = eccmode;
+
+	message_mod = nand_cal_message_num_size(info, &message_num, &msg_ecc_size);
+	page_ecc_size = msg_ecc_size * message_num;
+
+	info->page_total_num = info->vir_page_size + info->vir_oob_size + page_ecc_size;
+	info->flash_oob_off = info->vir_page_size + page_ecc_size - msg_ecc_size;
+
+	bch_kk =  info->message_len;
+	bch_nn = bch_kk + g_nand_ecc_size[eccmode];
+	info->bch_data= NANDFC_BCH_KK_DATA(bch_kk) | NANDFC_BCH_NN_DATA(bch_nn);
+
+	bch_oob_kk = message_mod + info->vir_oob_size;
+	bch_oob_nn = bch_oob_kk + g_nand_ecc_size[eccmode];
+	info->bch_oob = NANDFC_BCH_KK_OOB(bch_oob_kk) | NANDFC_BCH_NN_OOB(bch_oob_nn) ;
+
+	config_b = NANDFC_HWECC(1) | NANDFC_ECC_MODE(info->ecc_mode);
+
+       /*16k page nand need program twice one page*/
+	/*package num need change when program if not time of 2*/
+	if (info->type == NAND_TYPE_16K || info->type == NAND_TYPE_14K)
+		message_num >>= 1;
+
+	message_oob = NANDFC_OOB_SIZE(info->vir_oob_size) |
+		NANDFC_MESSAGE_SIZE(info->message_len * message_num);
+	/*page size is not used, but package num is used*/
+	page_para = NANDFC_PAGE_SIZE(info->page_total_num) |
+		NANDFC_PACKAGE_NUM(message_num);
+
+	__raw_writel(config_b, NANDFC_REG_CONFIG_B);
+	__raw_writel(page_para, NANDFC_REG_PAGE_PARA);
+	if (message_num == 1)
+		info->bch_data = info->bch_oob;
+	__raw_writel(info->bch_data, NANDFC_REG_BCH_DATA);
+	__raw_writel(info->bch_oob, NANDFC_REG_BCH_OOB);
+	__raw_writel(message_oob, NANDFC_REG_MESSAGE_OOB_SIZE);
+
+#ifdef NAND_DEBUG
+	printf("nand_eccmode_setting:bch_data=0x%x, bch_oob=0x%x, page_total=0x%x, oob=0x%x\n",
+		info->bch_data, info->bch_oob, info->page_total_num, info->vir_oob_size);
+	printf("nand_eccmode_setting:page_para=0x%08lx, message_oob=0x%08lx\n",
+		page_para, message_oob);
+#endif
+	printf("nand ecc setting done, configA=0x%x, configb=0x%08lx, type=%d\n",
+		__raw_readl(NANDFC_REG_CONFIG_A), config_b, info->type);
+	return 0;
+}
+
+static void nand_eccmode_convert(unsigned int page_addr, struct mtd_info *mtd)
+{
+	register struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	u8 ecc_mode;
+
+	if(page_addr < info->boot_logic_end_pageaddr) {
+		ecc_mode = info->ecc_mode_bak;
+	} else {
+		ecc_mode = info->max_eccmode_support;
+	}
+
+	if (ecc_mode != info->ecc_mode)
+		nand_eccmode_setting(info, ecc_mode);
+}
+
+static u8 nand_rda_read_byte(struct mtd_info *mtd)
+{
+	u8 ret;
+	struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	ret = *((u8 *) info->byte_buf + info->index);
+	info->index++;
+#ifdef NAND_DEBUG
+	printf("nand_read_byte, ret = %02x\n", ret);
+#endif
+	return ret;
+}
+
+static u16 nand_rda_read_word(struct mtd_info *mtd)
+{
+	u16 ret;
+	struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	ret = *(u16 *) ((uint8_t *) info->byte_buf + info->index);
+	info->index += 2;
+#ifdef NAND_DEBUG
+	printf("nand_read_word, ret = %04x\n", ret);
+#endif
+	return ret;
+}
+
+static void nand_rda_read_buf(struct mtd_info *mtd, uint8_t * buf, int len)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	u8 *nand_ptr = (u8 *) (chip->IO_ADDR_R + info->read_ptr);
+	u8 * u_nand_temp_buffer = &g_nand_flash_temp_buffer[info->read_ptr];
+
+#ifdef NAND_DEBUG
+	printf("read : buf addr = 0x%x, len = %d, read_ptr = %d, u_nand_temp_buffer = 0x%x \n",
+			(u32) buf, (u32)len,
+	      (u32) info->read_ptr, (u32)u_nand_temp_buffer);
+#endif /* NAND_DEBUG */
+
+#ifndef CONFIG_NAND_RDA_DMA
+	if (info->type == NAND_TYPE_16K || info->type == NAND_TYPE_14K) {
+		memcpy((void *)buf, (void *)u_nand_temp_buffer, len);
+	} else {
+		if (info->page_addr == 0 && info->read_ptr == 0 &&
+			info->parameter_mode_select == NAND_PARAMETER_BY_NAND) {
+			/* specially do for nand when read 1KB of first page. */
+			if (info->dump_debug_flag == 0)
+				len = info->vir_page_size;/*no ecc bytes*/
+			else
+				len = 2048;/*ecc bytes needed*/
+			memset(buf, 0xff, info->page_size);
+		}
+		memcpy((void *)buf, (void *)nand_ptr, len);
+	}
+
+	info->read_ptr += len;
+
+#ifdef NAND_DEBUG_VERBOSE
+	rda_dump_buf((char *)buf, len);
+#endif
+
+#else
+	struct rda_dma_chan_params dma_param;
+	dma_addr_t phys_addr;
+	void *addr = (void *)buf;
+	int ret = 0;
+
+	/*
+	 * If size is less than the size of oob,
+	 * we copy directly them to mapping buffer.
+	 */
+	if (len <= mtd->oobsize) {
+		memcpy(buf, (void *)nand_ptr, len);
+		info->read_ptr = 0;
+		return;
+	}
+
+	if (((u32)addr & 0x7) != 0) {
+		printf("ERROR, nand dma read buffer %p is not 8bytes aligned\n",
+			addr);
+		return;
+	}
+
+	phys_addr = dma_map_single(addr, len, DMA_FROM_DEVICE);
+
+	dma_param.src_addr = (u32) info->nand_data_phys;
+	dma_param.dst_addr = phys_addr;
+	dma_param.xfer_size = len;
+	//dma_param.dma_mode = RDA_DMA_FR_MODE;
+	dma_param.dma_mode = RDA_DMA_NOR_MODE;
+
+	ret = rda_set_dma_params(info->dma_ch, &dma_param);
+	if (ret < 0) {
+		printf("rda nand : Failed to set parameter\n");
+		dma_unmap_single(addr, len, DMA_FROM_DEVICE);
+		return;
+	}
+
+	/* use flush to avoid annoying unaligned warning */
+	/* however, invalidate after the dma it the right thing to do */
+	flush_dcache_range((u32)addr, (u32)(addr + len));
+
+	rda_start_dma(info->dma_ch);
+	rda_poll_dma(info->dma_ch);
+	rda_stop_dma(info->dma_ch);
+
+	/* use flush to avoid annoying unaligned warning */
+	//invalidate_dcache_range((u32)addr, (u32)(addr + len));
+
+	/* Free the specified physical address */
+	dma_unmap_single(addr, len, DMA_FROM_DEVICE);
+	info->read_ptr += len;
+
+	return;
+#endif /* CONFIG_NAND_RDA_DMA */
+}
+
+static void nand_rda_write_buf(struct mtd_info *mtd, const uint8_t * buf,
+			       int len)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	u8 *nand_ptr = (u8 *) (chip->IO_ADDR_W + info->write_ptr);
+	u8 *u_nand_temp_buffer = &g_nand_flash_temp_buffer[info->write_ptr];
+
+#ifdef NAND_DEBUG
+	printf("write : buf addr = 0x%p, len = %d, write_ptr = %d\n", buf, len,
+	       info->write_ptr);
+#endif /* NAND_DEBUG */
+
+#ifdef NAND_DEBUG_VERBOSE
+	rda_dump_buf((char *)buf, len);
+#endif
+
+#ifndef CONFIG_NAND_RDA_DMA
+	if (info->type == NAND_TYPE_16K || info->type == NAND_TYPE_14K)
+		memcpy((void *)u_nand_temp_buffer, (void *)buf, len);
+	else
+		memcpy((void *)nand_ptr, (void *)buf, len);
+
+	info->write_ptr += len;
+#else
+	struct rda_dma_chan_params dma_param;
+	dma_addr_t phys_addr;
+	void *addr = (void *)buf;
+	int ret = 0;
+
+	/*
+	 * If size is less than the size of oob,
+	 * we copy directly them to mapping buffer.
+	 */
+	if (len <= mtd->oobsize) {
+		memcpy((void *)nand_ptr, (void *)buf, len);
+		info->write_ptr += len;
+		return;
+	}
+
+	if (((u32)addr & 0x7) != 0) {
+		printf("ERROR, nand dma write %p buffer is not 8bytes aligned\n",
+			addr);
+		return;
+	}
+	phys_addr = dma_map_single(addr, len, DMA_TO_DEVICE);
+
+	dma_param.src_addr = phys_addr;
+	dma_param.dst_addr = (u32) info->nand_data_phys;
+	dma_param.xfer_size = len;
+	//dma_param.dma_mode = RDA_DMA_FW_MODE;
+	dma_param.dma_mode = RDA_DMA_NOR_MODE;
+
+	ret = rda_set_dma_params(info->dma_ch, &dma_param);
+	if (ret < 0) {
+		printf("rda nand : Failed to set parameter\n");
+		dma_unmap_single(addr, len, DMA_TO_DEVICE);
+		return;
+	}
+
+	flush_dcache_range((u32)addr, (u32)(addr + len));
+
+	rda_start_dma(info->dma_ch);
+	rda_poll_dma(info->dma_ch);
+	rda_stop_dma(info->dma_ch);
+
+	/* Free the specified physical address */
+	dma_unmap_single(addr, len, DMA_TO_DEVICE);
+	info->write_ptr += len;
+
+	return;
+#endif /* CONFIG_NAND_RDA_DMA */
+}
+
+static void nand_rda_do_cmd_pre(struct mtd_info *mtd)
+{
+	struct nand_chip *this = mtd->priv;
+	struct rda_nand_info *info = this->priv;
+	unsigned int page_addr = info->page_addr;
+
+	__raw_writel(0xfff, NANDFC_REG_INT_STAT);
+	switch (info->cmd) {
+	case NAND_CMD_SEQIN:
+		hal_flush_buf(mtd);
+		info->write_ptr = 0;
+		break;
+	case NAND_CMD_READ0:
+		hal_flush_buf(mtd);
+		//info->read_ptr = 0;
+		if(info->parameter_mode_select == NAND_PARAMETER_BY_NAND &&
+			info->dump_debug_flag == 0) {
+			if (page_addr < info->boot_logic_end_pageaddr) {
+				page_addr += info->spl_logic_pageaddr;
+				info->page_addr = page_addr;
+			}
+		}
+		break;
+	default:
+		break;
+	}
+}
+
+static void nand_rda_do_cmd_post(struct mtd_info *mtd)
+{
+	struct nand_chip *this = mtd->priv;
+	struct rda_nand_info *info = this->priv;
+	u32 temp;
+
+	switch (info->cmd) {
+	case NAND_CMD_RESET:
+		return;
+	case NAND_CMD_READID:
+		temp = __raw_readl(NANDFC_REG_IDCODE_A);
+		info->byte_buf[0] = temp;
+		temp = __raw_readl(NANDFC_REG_IDCODE_B);
+		info->byte_buf[1] = temp;
+		info->index = 0;
+		break;
+	case NAND_CMD_STATUS:
+		temp = __raw_readl(NANDFC_REG_OP_STATUS);
+		info->byte_buf[0] = (temp & 0xFF);
+		info->index = 0;
+		if (info->byte_buf[0] != 0xe0) {
+			printf("nand error in op status %x\n",
+			       info->byte_buf[0]);
+		}
+#ifdef NAND_DEBUG
+		printf("post_cmd read status 0x3c = %x\n", info->byte_buf[0]);
+#endif
+		break;
+	case NAND_CMD_READ0:	// NAND_CMD_READOOB goes here too
+		break;
+#if 0
+/* read back after write, for err checking */
+	case NAND_CMD_SEQIN:
+		{
+			int cmd_ret;
+			/* read back instantly and check fcs/crc result */
+			hal_send_cmd((unsigned char)NAND_CMD_READ0,
+				     info->page_addr);
+			cmd_ret = hal_wait_cmd_complete();
+			if (cmd_ret) {
+				printf
+				    ("readback cmd fail, page_addr = %x, ret = %x\n",
+				     info->page_addr, cmd_ret);
+			}
+		}
+		break;
+#endif
+#if 0
+/* delay 10ms, for erase to complete */
+	case NAND_CMD_ERASE1:
+		udelay(10000);
+		break;
+#endif
+	default:
+		break;
+	}
+}
+
+static void nand_rda_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+#ifdef NAND_DEBUG
+        printf("nand_rda_hwcontrol, cmd = %x, ctrl = %x, not use anymore\n",
+               cmd, ctrl);
+#endif
+}
+
+static int nand_rda_dev_ready(struct mtd_info *mtd)
+{
+	return 1;
+}
+
+int nand_cmd_reset_flash(void)
+{
+	int ret = 0;
+
+	hal_send_cmd_brick(NAND_CMD_RESET,0,0,5);
+	hal_send_cmd_brick(0,0,0,0);
+	hal_start_cmd_data();
+	ret = hal_wait_cmd_complete();
+	if (ret)
+		printf("nand_reset_flash failed\n");
+
+	return ret;
+}
+
+int nand_cmd_read_id(void)
+{
+	int ret = 0;
+
+	hal_send_cmd_brick(NAND_CMD_READID,0,0,2);
+	hal_send_cmd_brick(0,0,0,6);
+	hal_send_cmd_brick(0,0,0,0xd);
+	hal_send_cmd_brick(0,0,7,0);
+	hal_start_cmd_data();
+	ret = hal_wait_cmd_complete();
+	if (ret)
+		printf("nand_cmd_read_id failed\n");
+
+	return ret;
+}
+
+void nand_cmd_write_page(struct rda_nand_info *info, unsigned int page_addr,
+	u16 page_size, u16 col_addr)
+{
+	u8 addr_temp = 0;
+
+	hal_send_cmd_brick(NAND_CMD_SEQIN,0,0,2);
+
+	addr_temp = col_addr & 0xff;
+	hal_send_cmd_brick(addr_temp,0,0,2);
+	addr_temp = (col_addr >> 8) & 0xff;
+	hal_send_cmd_brick(addr_temp,0,0,2);
+
+	if (NAND_BLOCK_SIZE == 0x300000) {
+		/*page 0x180 ~ 0x1ff are invalid, so need skip to next block.*/
+		page_addr += 0x80 * (page_addr / 0x180);
+		/*block 0xab0 ~ 0xfff are invalid, so need skip to next LUN.*/
+		page_addr += (0x550 << 9) * ((page_addr >> 9) / 0xab0);
+	}
+
+	addr_temp = page_addr & 0xff;
+	hal_send_cmd_brick(addr_temp,0,0,2);
+	addr_temp = (page_addr >> 8) & 0xff;
+	hal_send_cmd_brick(addr_temp,0,0,2);
+	addr_temp = (page_addr >> 16) & 0xff;
+	hal_send_cmd_brick(addr_temp,0,0,7);
+
+	hal_send_cmd_brick(0,0,page_size,3);
+
+	hal_send_cmd_brick(0,info->bus_width_16,page_size, 1);
+
+	hal_send_cmd_brick(NAND_CMD_PAGEPROG,0,0,5);
+	
+	hal_send_cmd_brick(0,0,0,0);
+
+	return;
+}
+
+void nand_cmd_read_page(struct rda_nand_info *info, unsigned int page_addr,
+	unsigned short num, unsigned short col_addr)
+{
+	u8 addr_temp = 0;
+	
+	hal_send_cmd_brick(NAND_CMD_READ0,0,0,2);
+
+	addr_temp = col_addr & 0xff;
+	hal_send_cmd_brick(addr_temp,0,0,2);
+	addr_temp = (col_addr >> 8)& 0xff;
+	hal_send_cmd_brick(addr_temp,0,0,2);
+
+	if (NAND_BLOCK_SIZE == 0x300000) {
+		/*page 0x180 ~ 0x1ff are invalid, so need skip to next block.*/
+		page_addr += 0x80 * (page_addr / 0x180);
+		/*block 0xab0 ~ 0xfff are invalid, so need skip to next LUN.*/
+		page_addr += (0x550 << 9) * ((page_addr >> 9) / 0xab0);
+	}
+
+	addr_temp = page_addr & 0xff;
+	hal_send_cmd_brick(addr_temp,0,0,2);
+	addr_temp = (page_addr >> 8) & 0xff;
+	hal_send_cmd_brick(addr_temp,0,0,2);
+	addr_temp = (page_addr >> 16) & 0xff;
+	hal_send_cmd_brick(addr_temp,0,0,1);
+
+	hal_send_cmd_brick(NAND_CMD_READSTART,0,0,5);
+	hal_send_cmd_brick(0,0,0,0xa);
+	hal_send_cmd_brick(0,0,0,0x4);
+
+	hal_send_cmd_brick(0,info->bus_width_16,num, 0);
+
+	return;
+}
+
+void nand_cmd_read_random(struct rda_nand_info *info, unsigned short num,
+	unsigned short col_addr)
+{
+	u8 addr_temp = 0;
+	
+	hal_send_cmd_brick(NAND_CMD_RNDOUT,0,0,2);
+
+	addr_temp = col_addr & 0xff;
+	hal_send_cmd_brick(addr_temp,0,0,2);
+	addr_temp = (col_addr >> 8)& 0xff;
+	hal_send_cmd_brick(addr_temp,0,0,1);
+	hal_send_cmd_brick(NAND_CMD_RNDOUTSTART,0,0,9);
+	hal_send_cmd_brick(0,0,0,0x4);
+
+	hal_send_cmd_brick(0,info->bus_width_16,num, 0);
+
+	return;
+}
+void nand_cmd_block_erase(unsigned int page_addr)
+{
+	u8 addr_temp = 0;
+	int ret = 0;
+	
+	hal_send_cmd_brick(NAND_CMD_ERASE1,0,0,2);
+
+	if (NAND_BLOCK_SIZE == 0x300000) {
+		/*page 0x180 ~ 0x1ff are invalid, so need skip to next block.*/
+		page_addr += 0x80 * (page_addr / 0x180);
+		/*block 0xab0 ~ 0xfff are invalid, so need skip to next LUN.*/
+		page_addr += (0x550 << 9) * ((page_addr >> 9) / 0xab0);
+	}
+
+	addr_temp = page_addr & 0xff;
+	hal_send_cmd_brick(addr_temp,0,0,2);
+	addr_temp = (page_addr >> 8) & 0xff;
+	hal_send_cmd_brick(addr_temp,0,0,2);
+	addr_temp = (page_addr >> 16) & 0xff;
+	hal_send_cmd_brick(addr_temp,0,0,1);
+
+	hal_send_cmd_brick(NAND_CMD_ERASE2,0,0,5);
+	hal_send_cmd_brick(0,0,0,0);
+
+	hal_start_cmd_data();
+	ret = hal_wait_cmd_complete();
+	if (ret) {
+		printf("nand_cmd_block_erase fail\n");
+		return;
+	}
+}
+
+void nand_cmd_read_status(void)
+{
+	int ret = 0;
+
+	hal_send_cmd_brick(NAND_CMD_STATUS,0,0,6);
+	hal_send_cmd_brick(0,0,0,0xd);
+	hal_send_cmd_brick(0,0,1,0);
+
+	hal_start_cmd_data();
+	ret = hal_wait_cmd_complete();
+	if (ret) {
+		printf("nand_cmd_read_status failed\n");
+		return;
+	}
+}
+
+void nandfc_page_write_first(struct rda_nand_info *info, unsigned int page_addr,
+	u16 page_size, u16 col_addr)
+{
+        u8 addr_temp = 0;
+
+        hal_send_cmd_brick(NAND_CMD_SEQIN,0,0,2);
+
+        addr_temp = col_addr & 0xff;
+        hal_send_cmd_brick(addr_temp,0,0,2);
+        addr_temp = (col_addr >> 8) & 0xff;
+        hal_send_cmd_brick(addr_temp,0,0,2);
+
+	if (NAND_BLOCK_SIZE == 0x300000) {
+		/*page 0x180 ~ 0x1ff are invalid, so need skip to next block.*/
+		page_addr += 0x80 * (page_addr / 0x180);
+		/*block 0xab0 ~ 0xfff are invalid, so need skip to next LUN.*/
+		page_addr += (0x550 << 9) * ((page_addr >> 9) / 0xab0);
+	}
+
+        addr_temp = page_addr & 0xff;
+        hal_send_cmd_brick(addr_temp,0,0,2);
+        addr_temp = (page_addr >> 8) & 0xff;
+        hal_send_cmd_brick(addr_temp,0,0,2);
+        addr_temp = (page_addr >> 16) & 0xff;
+        hal_send_cmd_brick(addr_temp,0,0,7);
+
+        hal_send_cmd_brick(0,0,0,3);
+
+        hal_send_cmd_brick(0,info->bus_width_16,page_size, 0);
+
+        return;
+}
+
+void nandfc_page_write_random(struct rda_nand_info *info, u16 col_addr,
+	int data_num, char cmd_2nd)
+{
+        u8 addr_temp = 0;
+
+        hal_send_cmd_brick(NAND_CMD_RNDIN,0,0,2);
+
+        addr_temp = col_addr & 0xff;
+        hal_send_cmd_brick(addr_temp,0,0,2);
+        addr_temp = (col_addr >> 8) & 0xff;
+        hal_send_cmd_brick(addr_temp,0,0,9);
+
+        hal_send_cmd_brick(0,0,data_num, 3);
+        hal_send_cmd_brick(0,info->bus_width_16,data_num, 1);
+
+        hal_send_cmd_brick(cmd_2nd,0,0,5);
+
+        hal_send_cmd_brick(0,0,0,0);
+}
+
+int nand_page_write_all(unsigned int page_addr, struct mtd_info *mtd)
+{
+	int ret = 0;
+	u16 page_size = 0;
+	u16 col_addr = 0;
+	u32 message_oob = 0, page_para;
+	register struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	u8 *nand_ptr = (u8 *) chip->IO_ADDR_W;
+	u8 *u_nand_temp_buffer = &g_nand_flash_temp_buffer[0];
+	u16 message_num = 0, message_mod = 0;
+	u16 first_wr_ecc_len = 0, first_wr_data_len = 0;
+
+	if(info->parameter_mode_select == NAND_PARAMETER_BY_GPIO)
+		nand_eccmode_convert(page_addr, mtd);
+
+	if (info->type == NAND_TYPE_16K || info->type == NAND_TYPE_14K) {
+		message_num = info->vir_page_size / info->message_len;
+		message_mod = info->vir_page_size % info->message_len;
+		if(message_mod)
+			message_num += 1;
+		else
+			message_mod = info->message_len;
+
+		first_wr_data_len = (message_num >> 1) * info->message_len;
+
+		message_oob = NANDFC_OOB_SIZE(0) |
+			NANDFC_MESSAGE_SIZE(first_wr_data_len);
+
+		__raw_writel(info->bch_data, NANDFC_REG_BCH_OOB);
+		__raw_writel(message_oob, NANDFC_REG_MESSAGE_OOB_SIZE);
+
+		first_wr_ecc_len = (info->page_total_num - info->vir_page_size - \
+			info->vir_oob_size) / message_num * (message_num >> 1);
+		page_size = first_wr_data_len + first_wr_ecc_len;
+		col_addr = page_size;
+
+		if (info->bus_width_16)
+			page_size = page_size - 2;
+		else
+			page_size = page_size - 1;
+
+		page_para = NANDFC_PAGE_SIZE(page_size) |
+			NANDFC_PACKAGE_NUM(message_num >> 1);
+		__raw_writel(page_para, NANDFC_REG_PAGE_PARA);
+
+		hal_flush_buf(mtd);
+		memcpy((void *)nand_ptr, (void *)u_nand_temp_buffer, first_wr_data_len);
+	}else{
+		if (info->bus_width_16)
+			page_size = info->page_total_num - 2;
+		else
+			page_size = info->page_total_num - 1;
+	}
+
+	if (info->type == NAND_TYPE_16K || info->type == NAND_TYPE_14K)
+		nandfc_page_write_first(info, page_addr, page_size, 0);
+	else
+		nand_cmd_write_page(info, page_addr, page_size, 0);
+	hal_start_cmd_data();
+	ret = hal_wait_cmd_complete();
+	if (ret) {
+		if (info->type == NAND_TYPE_16K || info->type == NAND_TYPE_14K)
+			printf ("nandfc_page_write 16k first half page failed: page_addr = 0x%x\n",
+					page_addr);
+		else
+			printf ("nandfc_page_write failed:  page_addr = 0x%x\n", page_addr);
+		return ret;
+	}
+
+	if (info->type == NAND_TYPE_16K || info->type == NAND_TYPE_14K) {
+		message_oob = NANDFC_OOB_SIZE(info->vir_oob_size) |
+			NANDFC_MESSAGE_SIZE(info->vir_page_size - first_wr_data_len);
+
+		__raw_writel(info->bch_oob, NANDFC_REG_BCH_OOB);
+		__raw_writel(message_oob, NANDFC_REG_MESSAGE_OOB_SIZE);
+		page_size = info->page_total_num - col_addr;
+
+		if (info->bus_width_16){
+			page_size = page_size - 2;
+			col_addr = col_addr >> 1;
+		} else
+			page_size = page_size - 1;
+
+		page_para = NANDFC_PAGE_SIZE(page_size) |
+			NANDFC_PACKAGE_NUM(message_num - (message_num >> 1));
+		__raw_writel(page_para, NANDFC_REG_PAGE_PARA);
+
+		hal_flush_buf(mtd);
+		memcpy((void *)nand_ptr, (void *)(u_nand_temp_buffer + first_wr_data_len),
+			info->vir_page_size + info->vir_oob_size - first_wr_data_len);
+
+		//nand_cmd_write_page(page_addr, page_size, col_addr);
+		nandfc_page_write_random(info, col_addr, page_size, NAND_CMD_PAGEPROG);
+		hal_start_cmd_data();
+		ret = hal_wait_cmd_complete();
+		if (ret) {
+			printf ("nandfc_page_write 16k second half page failed: page_addr = 0x%x\n",
+					page_addr);
+			return ret;
+		}
+	}
+
+	return ret;
+}
+
+int nand_page_read_all(unsigned int page_addr, struct mtd_info *mtd)
+{
+	int ret = 0;
+	unsigned short num = 0,col_addr = 0;
+	u32 message_oob = 0, page_para;
+	register struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	u8 *nand_ptr = (u8 *) chip->IO_ADDR_R;
+	u8 *u_nand_temp_buffer = &g_nand_flash_temp_buffer[0];
+	u16 message_num = 0, message_mod = 0;
+	u16 first_rd_ecc_len = 0, first_rd_data_len = 0;
+
+	if (info->parameter_mode_select == NAND_PARAMETER_BY_GPIO)
+		nand_eccmode_convert(page_addr, mtd);
+
+	if (info->type == NAND_TYPE_16K || info->type == NAND_TYPE_14K){
+		message_num = info->vir_page_size / info->message_len;
+		message_mod = info->vir_page_size % info->message_len;
+		if(message_mod)
+			message_num += 1;
+		else
+			message_mod = info->message_len;
+
+		first_rd_data_len =  info->message_len * (message_num >> 1);
+		message_oob = NANDFC_OOB_SIZE(0) | NANDFC_MESSAGE_SIZE(first_rd_data_len);
+
+		__raw_writel(info->bch_data, NANDFC_REG_BCH_OOB);
+		__raw_writel(message_oob, NANDFC_REG_MESSAGE_OOB_SIZE);
+
+		first_rd_ecc_len = (info->page_total_num - info->vir_page_size - \
+			info->vir_oob_size) / message_num * (message_num >> 1);
+		num = first_rd_data_len+ first_rd_ecc_len;
+
+		page_para = NANDFC_PAGE_SIZE(num) |
+			NANDFC_PACKAGE_NUM(message_num >> 1);
+		__raw_writel(page_para, NANDFC_REG_PAGE_PARA);
+	}else
+		num = info->page_total_num;
+
+	nand_cmd_read_page(info, page_addr, num, col_addr);
+	hal_start_cmd_data();
+	ret = hal_wait_cmd_complete();
+	if (ret) {
+		if (info->type != NAND_TYPE_16K && info->type != NAND_TYPE_14K) {
+			printf ("nandfc_page_read failed : page_addr = 0x%x\n", page_addr);
+			return ret;
+		} else
+			printf ("nandfc_page_read 16k first half page failed: page_addr = 0x%x\n",
+					page_addr);
+	}
+
+	if (info->type == NAND_TYPE_16K || info->type == NAND_TYPE_14K)
+		memcpy((void *)u_nand_temp_buffer, (void *)nand_ptr, first_rd_data_len);
+
+	if (info->type == NAND_TYPE_16K || info->type == NAND_TYPE_14K) {
+		message_oob = NANDFC_OOB_SIZE(info->vir_oob_size) |
+			NANDFC_MESSAGE_SIZE(info->vir_page_size - first_rd_data_len);
+
+		__raw_writel(info->bch_oob, NANDFC_REG_BCH_OOB);
+		__raw_writel(message_oob, NANDFC_REG_MESSAGE_OOB_SIZE);
+
+		col_addr = num;
+		num = info->page_total_num - col_addr;
+
+		page_para = NANDFC_PAGE_SIZE(num) |
+			NANDFC_PACKAGE_NUM(message_num - (message_num >> 1));
+		__raw_writel(page_para, NANDFC_REG_PAGE_PARA);
+
+		nand_cmd_read_random(info, num, col_addr);
+		hal_start_cmd_data();
+		ret = hal_wait_cmd_complete();
+		memcpy((void *)(u_nand_temp_buffer + first_rd_data_len), (void *)nand_ptr,
+			(info->vir_page_size + info->vir_oob_size - first_rd_data_len));
+		if (ret) {
+			printf ("nandfc_page_read 16k second half page failed: page_addr = 0x%x\n",
+					page_addr);
+			return ret;
+		}
+	}
+
+	return ret;
+}
+
+static void nand_parameter_info_wr(unsigned int page_addr, struct mtd_info *mtd)
+{
+	register struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	u8 *nand_ptr = (u8 *) (chip->IO_ADDR_W);
+	u8 ecc_mode;
+
+	if(page_addr < info->boot_logic_end_pageaddr && info->cmd_flag == 0) {
+		ecc_mode = NAND_ECC_96BIT_WITHOUT_CRC;
+		info->vir_page_size = 1024;
+		info->vir_page_shift = 10;
+		info->vir_oob_size = 32;
+		info->message_len = 1024;
+		info->type = NAND_TYPE_2K;
+		info->cmd_flag = 1;
+		nand_eccmode_setting(info, ecc_mode);
+
+		memset(nand_ptr, 0xff, 2048);
+		memcpy(nand_ptr, (unsigned char*)&nand_parameter,
+			sizeof(struct flash_nand_parameter));
+		nand_page_write_all(0, mtd);
+
+		ecc_mode = info->ecc_mode_bak;
+		info->vir_page_size = nand_parameter.page_size;
+		if (is_power_of_2(info->vir_page_size))
+			info->vir_page_shift = ffs(info->vir_page_size) - 1;
+		else
+			info->vir_page_shift = 0;
+		info->vir_oob_size = nand_parameter.oob_size;
+		info->message_len = nand_parameter.ecc_msg_len;
+		info->type = info->type_bak;
+		nand_eccmode_setting(info, ecc_mode);
+	}
+}
+
+static void nand_parameter_info_rd(unsigned int page_addr, struct mtd_info *mtd)
+{
+	register struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	u8 ecc_mode;
+
+	if(page_addr < info->spl_logic_pageaddr) {
+		ecc_mode = NAND_ECC_96BIT_WITHOUT_CRC;
+		if (ecc_mode != info->ecc_mode) {
+			info->vir_page_size = 1024;
+			info->vir_page_shift = 10;
+			info->vir_oob_size = 32;
+			info->message_len = 1024;
+			info->type = NAND_TYPE_2K;
+		}
+	} else {
+		ecc_mode = info->ecc_mode_bak;
+		if (ecc_mode != info->ecc_mode) {
+			info->vir_page_size = nand_parameter.page_size;
+			if (is_power_of_2(info->vir_page_size))
+				info->vir_page_shift = ffs(info->vir_page_size) - 1;
+			else
+				info->vir_page_shift = 0;
+			info->vir_oob_size = nand_parameter.oob_size;
+			info->message_len = nand_parameter.ecc_msg_len;
+			info->type = info->type_bak;
+		}
+	}
+
+	if (ecc_mode != info->ecc_mode) {
+		nand_eccmode_setting(info, ecc_mode);
+	}
+}
+
+static void nand_send_cmd_all(struct mtd_info *mtd)
+{
+	register struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	unsigned int page_addr = info->page_addr;
+
+	switch(info->cmd){
+		case NAND_CMD_READ0:
+			if(info->parameter_mode_select == NAND_PARAMETER_BY_NAND)
+				nand_parameter_info_rd(page_addr, mtd);
+			nand_page_read_all(page_addr, mtd);
+			break;
+		case NAND_CMD_RESET:
+			nand_cmd_reset_flash();
+			break;
+		case NAND_CMD_READID:
+			nand_cmd_read_id();
+			break;
+		case NAND_CMD_ERASE1:
+			nand_cmd_block_erase(page_addr);
+			if (info->parameter_mode_select == NAND_PARAMETER_BY_NAND) {
+				if (page_addr < info->boot_logic_end_pageaddr) {
+					info->cmd_flag = 0;
+					//nand_cmd_block_erase(0);
+				}
+			}
+			break;
+		case NAND_CMD_PAGEPROG:
+		case NAND_CMD_SEQIN:
+			nand_page_write_all(page_addr, mtd);
+			if(info->parameter_mode_select == NAND_PARAMETER_BY_NAND)
+				nand_parameter_info_wr(page_addr, mtd);
+			break;
+		case NAND_CMD_STATUS:
+			nand_cmd_read_status();
+			break;
+		default:
+			return;
+	}
+
+	//hal_start_cmd_data();
+}
+
+static void nand_rda_cmdfunc(struct mtd_info *mtd, unsigned int command,
+			     int column, int page_addr)
+{
+	register struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+
+#ifdef NAND_DEBUG
+	printf("nand_rda_cmdfunc, cmd = %x, page_addr = %x, col_addr = %x\n",
+	       command, page_addr, column);
+#endif
+
+	/* remap command */
+	switch (command) {
+	case NAND_CMD_SEQIN:	/* 0x80 do nothing, wait for 0x10 */
+		info->page_addr = page_addr;
+		info->col_addr = column;
+		info->cmd = NAND_CMD_NONE;
+		info->write_ptr= column;
+		if(info->parameter_mode_select == NAND_PARAMETER_BY_NAND) {
+			if (page_addr < info->boot_logic_end_pageaddr) {
+				page_addr += info->spl_logic_pageaddr;
+				info->page_addr = page_addr;
+			}
+			nand_parameter_info_rd(page_addr, mtd);
+		}
+		break;
+	case NAND_CMD_READSTART:	/* hw auto gen 0x30 for read */
+	case NAND_CMD_ERASE2:	/* hw auto gen 0xd0 for erase */
+#ifdef NAND_DEBUG
+		printf("erase block, erase_size = %x\n", mtd->erasesize);
+#endif
+		info->cmd = NAND_CMD_NONE;
+		break;
+	case NAND_CMD_PAGEPROG:	/* 0x10 do the real program */
+		info->cmd = NAND_CMD_SEQIN;
+		info->col_addr = 0;
+		break;
+	case NAND_CMD_READOOB:	/* Emulate NAND_CMD_READOOB */
+		info->page_addr = page_addr;
+		info->cmd = NAND_CMD_READ0;
+		/* Offset of oob */
+		info->col_addr = column;
+		info->read_ptr = mtd->writesize;
+		break;
+	case NAND_CMD_READ0:	/* Emulate NAND_CMD_READOOB */
+		info->read_ptr = 0;
+		/*fall though, don't need break;*/
+	default:
+		info->page_addr = page_addr;
+		info->col_addr = column;
+		info->cmd = command;
+		break;
+	}
+	if (info->cmd == NAND_CMD_NONE) {
+		return;
+	}
+
+#ifdef NAND_DEBUG
+	printf("after cmd remap, cmd = %x, page_addr = %x, col_addr = %x\n",
+	       info->cmd, info->page_addr, info->col_addr);
+#endif
+/*
+	if (info->col_addr != -1) {
+		hal_set_col_addr(info->col_addr);
+	}
+*/
+	if (info->page_addr == -1)
+		info->page_addr = 0;
+
+	nand_rda_do_cmd_pre(mtd);
+
+	nand_send_cmd_all(mtd);
+
+	nand_rda_do_cmd_post(mtd);
+
+	nand_wait_ready(mtd);
+}
+
+static int nand_reset_flash(void)
+{
+	int ret = 0;
+#ifdef NAND_DEBUG
+	printf("Enter function nand_rda_init\n");
+#endif
+	nand_cmd_reset_flash();
+
+	return ret;
+}
+
+static int nand_read_id(unsigned int id[2])
+{
+	int ret = 0;
+
+	nand_cmd_read_id();
+
+	id[0] = __raw_readl(NANDFC_REG_IDCODE_A);
+	id[1] = __raw_readl(NANDFC_REG_IDCODE_B);
+
+	printf("NAND: Nand ID: %08x %08x\n", id[0], id[1]);
+
+#ifdef TGT_AP_DO_NAND_TEST
+	gbl_nand_test_id_val[0] = id[0];
+	gbl_nand_test_id_val[1] = id[1];
+#endif /* TGT_AP_DO_NAND_TEST */
+	return ret;
+}
+
+static void read_ID(struct mtd_info *mtd)
+{
+	unsigned int id[2];
+
+	nand_read_id(id);
+}
+
+static void nand_rda_select_chip(struct mtd_info *mtd, int chip)
+{
+	unsigned long config_a = __raw_readl(NANDFC_REG_CONFIG_A);
+
+	if ((chip == -1) || (chip > 3))
+		return;
+
+	config_a |= NANDFC_CHIP_SEL(0x0f);
+	config_a &= ~ NANDFC_CHIP_SEL(1 << chip);
+
+	//printf("**********config_a = 0x%lx", config_a);
+	__raw_writel(config_a, NANDFC_REG_CONFIG_A);
+}
+
+static int nand_get_type(struct rda_nand_info *info, unsigned int id[2])
+{
+	u16 hwcfg_nand_type;
+	int metal_id;
+
+	info->spl_adjust_ratio = 2;
+	metal_id = rda_metal_id_get();
+
+#if defined(CONFIG_MACH_RDA8850E)
+#define RDA_NAND_TYPE_BIT_BUS  (1 << 1)    /* 1: 8-bit; 0: 16-bit */
+/*bit7 bit0 00 menas 2k, 01 means 4k, 10 means 8k, 11 means 16k*/
+#define RDA_NAND_TYPE_BIT_7       (1 << 7)
+#define RDA_NAND_TYPE_BIT_0       (1 << 0)
+	printf("NAND: RDA8850E chip, metal %d\n", metal_id);
+	hwcfg_nand_type = rda_hwcfg_get() & 0x83;
+	if (hwcfg_nand_type & RDA_NAND_TYPE_BIT_BUS)
+		info->bus_width_16 = 0;
+	else
+		info->bus_width_16 = 1;
+
+	info->vir_oob_size = NAND_OOBSIZE;
+	info->parameter_mode_select = NAND_PARAMETER_BY_GPIO;
+
+	u16 nand_type = ((hwcfg_nand_type & RDA_NAND_TYPE_BIT_7) >> 6)
+			| (hwcfg_nand_type & RDA_NAND_TYPE_BIT_0);
+	if(nand_type == 0) {
+		info->type = NAND_TYPE_2K;
+		info->parameter_mode_select = NAND_PARAMETER_BY_NAND;
+	}
+	else if(nand_type == 1)
+		info->type = NAND_TYPE_4K;
+	else
+		info->type = nand_type;
+
+	if (info->parameter_mode_select  == NAND_PARAMETER_BY_GPIO) {
+		switch(info->type){
+		case NAND_TYPE_2K:
+			info->page_size = 2048;
+			info->page_shift = 11;
+			info->ecc_mode = NAND_ECC_16BIT;
+			info->message_len = 2048;
+			break;
+		case NAND_TYPE_4K:
+			info->page_size = 4096;
+			info->page_shift = 12;
+			info->ecc_mode = NAND_ECC_24BIT;
+			info->message_len = 1024;
+			break;
+		case NAND_TYPE_8K:
+			info->page_size = 8192;
+			info->page_shift = 13;
+			info->ecc_mode = NAND_ECC_24BIT;
+			info->message_len = 1024;
+			break;
+		case NAND_TYPE_16K:
+			info->page_size = 16384;
+			info->page_shift = 14;
+			info->ecc_mode = NAND_ECC_32BIT;
+			info->message_len = 1024;
+			break;
+		default:
+			printf("Error nand type \n");
+			break;
+		}
+	}else {
+		fill_nand_parameter();
+		info->page_size = nand_parameter.page_size;
+		if (is_power_of_2(info->page_size))
+			info->page_shift = ffs(info->page_size) - 1;
+		else
+			info->page_shift = 0;
+		info->message_len = nand_parameter.ecc_msg_len;
+		info->vir_oob_size = nand_parameter.oob_size;
+		switch(info->page_size) {
+		case 2048:
+			info->type = NAND_TYPE_2K;
+			break;
+		case 4096:
+			info->type = NAND_TYPE_4K;
+			break;
+		case 8192:
+			info->type = NAND_TYPE_8K;
+			break;
+		case 16384:
+			info->type = NAND_TYPE_16K;
+			break;
+		case 3072:
+			info->type = NAND_TYPE_3K;
+			break;
+		case 7168:
+			info->type = NAND_TYPE_7K;
+			break;
+		case 14336:
+			info->type = NAND_TYPE_14K;
+			break;
+		default:
+			printf("Error nand type \n");
+			break;
+		}
+	}
+#else
+#if defined(CONFIG_MACH_RDA8810H)
+	printf("NAND: RDA8810H chip, metal %d\n", metal_id);
+	hwcfg_nand_type = rda_hwcfg_get();
+
+	if (RDA_HW_CFG_GET_BM_IDX(hwcfg_nand_type) == RDA_MODE_NAND_8BIT)
+		info->bus_width_16 = 0;
+	else
+	if (RDA_HW_CFG_GET_BM_IDX(hwcfg_nand_type) == RDA_MODE_NAND_16BIT)
+		info->bus_width_16 = 1;
+	else
+		printf("nand: invalid nand type \n");
+
+	info->parameter_mode_select = NAND_PARAMETER_BY_NAND;
+
+	fill_nand_parameter();
+	info->page_size = nand_parameter.page_size;
+	if (is_power_of_2(info->page_size))
+		info->page_shift = ffs(info->page_size) - 1;
+	else
+		info->page_shift = 0;
+	info->message_len = nand_parameter.ecc_msg_len;
+	info->vir_oob_size = nand_parameter.oob_size;
+	switch(info->page_size) {
+	case 2048:
+		info->type = NAND_TYPE_2K;
+		break;
+	case 4096:
+		info->type = NAND_TYPE_4K;
+		break;
+	case 8192:
+		info->type = NAND_TYPE_8K;
+		break;
+	case 16384:
+		info->type = NAND_TYPE_16K;
+		break;
+	case 3072:
+		info->type = NAND_TYPE_3K;
+		break;
+	case 7168:
+		info->type = NAND_TYPE_7K;
+		break;
+	case 14336:
+		info->type = NAND_TYPE_14K;
+		break;
+	default:
+		printf("Error nand type \n");
+		break;
+	}
+#else
+#error "WRONG MACH"
+#endif
+#endif
+
+	printf("NAND: actually ratio * 2, SPL adjust ratio is %d. \n",
+		info->spl_adjust_ratio);
+	return 0;
+}
+
+static int nand_rda_init(struct nand_chip *this, struct rda_nand_info *info)
+{
+	unsigned int id[2];
+	int ret = 0;
+
+#ifdef NAND_DEBUG
+	printf("Enter function nand_rda_init\n");
+#endif
+
+	ret = nand_get_type(info, id);
+	if (ret)
+		return ret;
+
+	ret = init_nand_info(info);
+	if (ret)
+		return ret;
+	if (info->bus_width_16)
+		this->options |= NAND_BUSWIDTH_16;
+
+	(void)hal_init(info);
+
+	ret = nand_reset_flash();
+	if (ret)
+		return ret;
+
+	ret = nand_read_id(id);
+	if (ret)
+		return ret;
+	
+	return ret;
+}
+
+static int nand_rda_init_size(struct mtd_info *mtd, struct nand_chip *this,
+			u8 *id_data)
+{
+	struct rda_nand_info *info = this->priv;
+
+	/* TODO: this is not always right
+	 * assuming nand is 2k/4k SLC for now
+	 * for other types of nand, 64 pages per block is not always true
+	 */
+	mtd->erasesize = info->vir_erase_size;
+	mtd->writesize = info->vir_page_size;
+	mtd->oobsize = info->vir_oob_size;
+
+	return (info->bus_width_16) ? NAND_BUSWIDTH_16 : 0;
+}
+
+int rda_nand_init(struct nand_chip *nand)
+{
+	struct rda_nand_info *info;
+	static struct rda_nand_info rda_nand_info;
+	int i;
+	u32 bootloader_end_addr = 0x400000;//4Mbytes
+
+	info = &rda_nand_info;
+#if 0
+	if (g_nand_flash_temp_buffer)
+		g_nand_flash_temp_buffer = (u8 *)malloc(18432);
+#endif
+	nand->chip_delay = 0;
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
+	nand->options |= NAND_USE_FLASH_BBT;
+#endif
+	/*
+	 * in fact, nand controler we do hardware ECC silently, and
+	 * we don't need tell mtd layer, and will simple nand operations
+	*/
+	nand->ecc.mode = NAND_ECC_NONE;
+	/* Set address of hardware control function */
+	nand->cmd_ctrl = nand_rda_hwcontrol;
+	nand->init_size = nand_rda_init_size;
+	nand->cmdfunc = nand_rda_cmdfunc;
+	nand->read_byte = nand_rda_read_byte;
+	nand->read_word = nand_rda_read_word;
+	nand->read_buf = nand_rda_read_buf;
+	nand->write_buf = nand_rda_write_buf;
+	nand->dev_ready = nand_rda_dev_ready;
+	nand->select_chip = nand_rda_select_chip;
+	nand->read_nand_ID = read_ID;
+	nand->priv = (void *)info;
+	nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)NANDFC_DATA_BUF;
+#ifdef CONFIG_NAND_RDA_DMA
+	info->nand_data_phys = (void __iomem *)NANDFC_DATA_BUF;
+#endif /* CONFIG_NAND_RDA_DMA */
+	info->index = 0;
+	info->write_ptr = 0;
+	info->read_ptr = 0;
+	info->master_clk = get_master_clk_rate(_TGT_AP_CLK_APB2);
+	info->clk=_TGT_AP_NAND_CLOCK;
+
+#ifdef CONFIG_NAND_RDA_DMA
+	rda_request_dma(&info->dma_ch);
+#endif /* CONFIG_NAND_RDA_DMA */
+
+	nand_rda_init(nand, info);
+
+	if (info->parameter_mode_select == NAND_PARAMETER_BY_NAND) {
+		switch (info->type) {
+		case NAND_TYPE_2K:
+			bootloader_end_addr = 0x200000;//2Mbytes
+			break;
+		case NAND_TYPE_4K:
+			bootloader_end_addr = 0x400000;//4Mbytes
+			break;
+		case NAND_TYPE_8K:
+			if (is_power_of_2(info->vir_erase_size))
+				bootloader_end_addr = 0x400000;//4Mbytes
+			else
+				bootloader_end_addr = 0x300000;//3Mbytes
+			break;
+		case NAND_TYPE_16K:
+			bootloader_end_addr = 0x400000;//4Mbytes
+			break;
+		case NAND_TYPE_3K:
+			bootloader_end_addr = 0x300000;//3Mbytes
+			break;
+		case NAND_TYPE_7K:
+			bootloader_end_addr = 0x700000;//7Mbytes
+			break;
+		case NAND_TYPE_14K:
+			bootloader_end_addr = 0x700000;//7Mbytes
+			break;
+		default:
+			printf("error nand type: %d \n", info->type);
+		}
+
+		bootloader_end_addr -= nand_parameter.spl_offset;
+
+		if (info->page_shift) {
+			info->boot_logic_end_pageaddr = bootloader_end_addr >> info->page_shift;
+			info->spl_logic_pageaddr = nand_parameter.spl_offset >> info->page_shift;
+		} else {
+			info->boot_logic_end_pageaddr = bootloader_end_addr / info->page_size;
+			info->spl_logic_pageaddr = nand_parameter.spl_offset / info->page_size;
+		}
+	}
+
+	if (!nand->ecc.layout && (nand->ecc.mode != NAND_ECC_SOFT_BCH)) {
+		switch (info->type) {
+		case NAND_TYPE_2K:
+			nand->ecc.layout = &rda_nand_oob_2k;
+			break;
+		case NAND_TYPE_4K:
+			nand->ecc.layout = &rda_nand_oob_4k;
+			break;
+		case NAND_TYPE_8K:
+			nand->ecc.layout = &rda_nand_oob_8k;
+			break;
+		case NAND_TYPE_16K:
+			nand->ecc.layout = &rda_nand_oob_16k;
+			break;
+		case NAND_TYPE_3K:
+			nand->ecc.layout = &rda_nand_oob_4k;
+			break;
+		case NAND_TYPE_7K:
+			nand->ecc.layout = &rda_nand_oob_8k;
+			break;
+		case NAND_TYPE_14K:
+			nand->ecc.layout = &rda_nand_oob_16k;
+			break;
+		default:
+			printf("error oob size: %d \n", info->vir_oob_size);
+		}
+		nand->ecc.layout->oobfree[0].length = info->vir_oob_size - 2;
+		for(i=1; i<MTD_MAX_OOBFREE_ENTRIES; i++)
+			nand->ecc.layout->oobfree[i].length = 0;
+	}
+
+	return 0;
+}
+
+#if 0
+/* move to rda_nand_base.c */
+int board_nand_init(struct nand_chip *chip) __attribute__ ((weak));
+
+int board_nand_init(struct nand_chip *chip)
+{
+	return rda_nand_init(chip);
+}
+#endif
+
+#ifdef TGT_AP_DO_NAND_TEST
+
+#define NAND_TEST_DATA_BASE	0x11c01080
+#define NAND_RESULT_DATA_ADDR	(NAND_TEST_DATA_BASE+0x00)
+#define NAND_TYPE_DATA_ADDR 	(NAND_TEST_DATA_BASE+0x04)
+#define NAND_PAGE_SIZE_ADDR     (NAND_TEST_DATA_BASE+0x08)
+#define NAND_VID_B1_ADDR	(NAND_TEST_DATA_BASE+0x0C)
+#define NAND_VID_B2_ADDR	(NAND_TEST_DATA_BASE+0x10)
+#define NAND_NAME_ADDR		(NAND_TEST_DATA_BASE+0x14)
+#define NAND_NAME_SIZE		0x08
+#define NAND_BUS_WIDTH_ADDR	(NAND_TEST_DATA_BASE+0x1C)
+
+#define NAND_TEST_OK_VAL	0xA55A6666
+#define NAND_TEST_ERROR_VAL	0xDEADDEAD
+
+static void print_nand_info(int dev_idx)
+{
+	nand_info_t *nand = &nand_info[dev_idx];
+	struct nand_chip *chip = nand->priv;
+	struct rda_nand_info *info = chip->priv;
+	unsigned int id[2],type_val = 0,bus_width = 8;
+	int man_id,j,k;
+	char *pname ;
+
+	id[0] = gbl_nand_test_id_val[0];
+	id[1] = gbl_nand_test_id_val[1];
+	man_id = id[0] & 0xFF;
+	pname = NULL;
+	for(j=0; nand_manuf_ids[j].id != 0x0;j++) {
+		if(nand_manuf_ids[j].id  == man_id) {
+			pname = nand_manuf_ids[j].name;
+			break;
+		}
+	}
+	printf("nand device info:\n");
+	if(pname != NULL)
+		printf("Nand name: %s\n",pname);
+	switch(info->type) {
+	case NAND_TYPE_4K: printf("Nand type: 4K\n"); type_val = 4;break;
+	case NAND_TYPE_2K: printf("Nand type: 2K\n"); type_val = 2;break;
+	case NAND_TYPE_8K: printf("Nand type: 8K\n"); type_val = 8;break;
+	case NAND_TYPE_16K: printf("Nand type: 16K\n"); type_val = 16;break;
+	default: printf("Nand type error\n"); type_val = 0;break;
+	}
+	//intf("Nand type: 0x%x\n",info->type);
+	//printf("Nand_used_type: 0x%x\n",info->nand_use_type);
+	printf("Nand page size: 0x%x\n",info->page_size);
+	printf("Nand ID: %08x %08x\n", id[0], id[1]);
+	printf("Nand page total num: 0x%x\n",info->page_total_num);
+
+	switch(info->bus_width_16) {
+	case 0:printf("Nand bus width: 8 bit\n"); bus_width = 8;break;
+	case 1:printf("Nand bus width: 16 bit\n"); bus_width = 16;break;
+	default:printf("Nand bus width error\n"); bus_width = 0;break;
+	}
+	*(unsigned int *)NAND_TYPE_DATA_ADDR = type_val;
+	*(unsigned int *)NAND_PAGE_SIZE_ADDR = info->page_size;
+	*(unsigned int *)NAND_VID_B1_ADDR = id[0];
+	*(unsigned int *)NAND_VID_B2_ADDR = id[1];
+	if(pname != NULL) {
+		for(k = 0;k<8;k++) {
+			*(unsigned char *)(NAND_NAME_ADDR + k) = '\0';
+		}
+		for(k = 0;k<8;k++) {
+			*(unsigned char *)(NAND_NAME_ADDR + k) = *(pname+k);
+		}
+	}
+	*(unsigned int *)NAND_BUS_WIDTH_ADDR = bus_width;
+}
+
+void test_nand_easily(void)
+{
+	nand_info_t *nand;
+	unsigned int i = 0,j = 0;
+	unsigned long addr =  0x1000000;
+	size_t len = 0;
+	int ret = 0;
+	nand_erase_options_t opts;
+
+	j = j;
+	ret = ret;
+	nand = &nand_info[0];
+
+	/* check test result */
+	if(*(unsigned int *)NAND_RESULT_DATA_ADDR == NAND_TEST_ERROR_VAL) {
+		printf("nand error!!!\n");
+		return;
+	}
+
+	printf("\n%s: current ticks = %llu\n",__func__,get_ticks());
+	printf("-------------Begin to test internal nand flash memory.............. \n");
+	len = nand->writesize;
+	for (i = 0; i < len; i++){
+		g_nand_test_buf_write[i] = i & 0xff;
+		g_nand_test_buf_read[i] =0;
+	}
+
+	/* set nand erasing parameters */
+	memset(&opts,0,sizeof(opts));
+	opts.offset = addr;
+	opts.length = len;
+	opts.jffs2 = 0;
+	opts.quiet = 0;
+	opts.spread = 0;
+
+	/* step0: read nand flash information data */
+	print_nand_info(0);
+	/* step1: erase flash */
+	printf("erase flash memory,addr = 0x%x,len = %d\n",(int)addr,(int)len);
+	//nand_erase(nand,addr,len);
+	ret = nand_erase_opts(nand, &opts);
+	if(ret != 0) {
+		printf("erase flash error, returned value: ret = %d\n",ret);
+		goto L_ERROR_END;
+	}
+	/* step2: write test data to flash */
+	printf("write test data to flash memory, addr = 0x%x, len = %d\n",(int)addr, (int)len);
+	/*
+	nand_write_skip_bad(nand,
+			addr,
+			&len,
+			g_nand_test_buf_write,
+			0);
+	*/
+	nand_write(nand, addr, &len,g_nand_test_buf_write);
+	printf("real writing test data len = %d\n",(int)len);
+	/* step3: read test data back */
+	printf("read test data from flash memory,addr = 0x%x, len = %d\n",(int)addr,(int)len);
+	//nand_read_skip_bad(nand,addr,&len,g_nand_test_buf_read);
+	nand_read(nand, addr,&len,g_nand_test_buf_read);
+	printf("real reading test data len = %d\n",(int)len);
+	#if 0
+	printf("display rx data\n");
+	for(i = 0; i < len; i++) {
+		printf("%x\t",g_nand_test_buf_read[i]);
+		j++;
+		if(j > 15) {
+		j = 0;
+		printf("\n");
+		}
+	}
+	#endif
+
+	/* step4: check test data for testing result */
+	printf("compare data\n");
+	for (i = 0; i < len; i++) {
+		if (g_nand_test_buf_write[i] != g_nand_test_buf_read[i]){
+			printf("nand operate error!!\n");
+			*(unsigned int *)NAND_RESULT_DATA_ADDR = NAND_TEST_ERROR_VAL;
+			return;
+		}
+	}
+//L_OK_END:
+
+	*(unsigned int *)NAND_RESULT_DATA_ADDR = NAND_TEST_OK_VAL;
+	printf("Write result data: addr = 0x%x,value = 0x%x\n",(int)NAND_RESULT_DATA_ADDR, NAND_TEST_OK_VAL);
+	printf("-------------Test internal nand flash memory OK.............. \n");
+	printf("\n%s: current ticks = %llu\n",__func__,get_ticks());
+	return;
+L_ERROR_END:
+	printf("-------------Test internal nand flash memory error.............. \n");
+	printf("\n%s: current ticks = %llu\n",__func__,get_ticks());
+	return;
+}
+#endif /* TGT_AP_DO_NAND_TEST */
diff --git a/drivers/mtd/nand/rda_spi_nand.c b/drivers/mtd/nand/rda_spi_nand.c
new file mode 100644
index 0000000000..0e78ec25d0
--- /dev/null
+++ b/drivers/mtd/nand/rda_spi_nand.c
@@ -0,0 +1,1654 @@
+#include <common.h>
+#include <malloc.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <nand.h>
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/reg_sysctrl.h>
+#include <asm/arch/hwcfg.h>
+#include <mtd/nand/rda_nand.h>
+
+#include <rda/tgt_ap_board_config.h>
+#include <rda/tgt_ap_clock_config.h>
+
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_NAND_RDA_DMA
+#endif
+
+#ifdef CONFIG_NAND_RDA_DMA
+#include <asm/dma-mapping.h>
+#include <asm/arch/dma.h>
+#endif
+
+#if (_TGT_NAND_TYPE_ == _SPI_NAND_USED_)
+/*******************************************************************/
+/*******************spi flash MACRO define******************************/
+#define SPI_NAND_READ_DATA_BUFFER_BASE 0xc0000000
+#define SPI_NAND_WRITE_DATA_BUFFER_BASE (RDA_SPIFLASH_BASE + 0x8)
+
+/*******************spi controller register define**************************/
+#define SPI_FLASH_REG_BASE RDA_SPIFLASH_BASE
+#define CMD_ADDR_OFFSET 0x0
+#define MODE_BLOCKSIZE_OFFSET 0x4
+#define DATA_FIFO_OFFSET 0x8
+#define STATUS_OFFSET 0xc
+#define READBACK_REG_OFFSET 0x10
+#define FLASH_CONFIG_OFFSET 0x14
+#define FIFO_CTRL_OFFSET 0x18
+#define DUAL_SPI_OFFSET 0x1c
+#define READ_CMD_OFFSET 0x20
+#define NAND_SPI_CONFIG_OFFSET 0x24
+#define NAND_SPI_CONFIG2_OFFSET 0x28
+
+#define SPI_CMD_ADDR (SPI_FLASH_REG_BASE+CMD_ADDR_OFFSET)
+#define SPI_BLOCK_SIZE (SPI_FLASH_REG_BASE+MODE_BLOCKSIZE_OFFSET)
+#define SPI_DATA_FIFO (SPI_FLASH_REG_BASE+DATA_FIFO_OFFSET)
+#define SPI_STATUS (SPI_FLASH_REG_BASE+STATUS_OFFSET)
+#define SPI_READ_BACK (SPI_FLASH_REG_BASE+READBACK_REG_OFFSET)
+#define SPI_CONFIG (SPI_FLASH_REG_BASE+FLASH_CONFIG_OFFSET)
+#define SPI_FIFO_CTRL (SPI_FLASH_REG_BASE+FIFO_CTRL_OFFSET)
+#define SPI_CS_SIZE (SPI_FLASH_REG_BASE+DUAL_SPI_OFFSET)
+#define SPI_READ_CMD (SPI_FLASH_REG_BASE+READ_CMD_OFFSET)
+#define SPI_NAND_CMD (SPI_FLASH_REG_BASE+NAND_SPI_CONFIG_OFFSET)
+#define SPI_NAND_CMD2 (SPI_FLASH_REG_BASE+NAND_SPI_CONFIG2_OFFSET)
+
+/*******************spi flash command define**************************/
+#define OPCODE_WRITE_ENABLE 0x06
+#define OPCODE_WRITE_DISABLE 0x04
+#define OPCODE_GET_FEATURE 0x0f
+#define OPCODE_SET_FEATURE 0x1f
+#define OPCODE_PAGE_READ_2_CACHE 0x13
+#define OPCODE_READ_FROM_CACHE  0x03
+#define OPCODE_READ_FROM_CACHEX4 0x6b
+#define OPCODE_READ_FROM_CACHE_QUADIO 0xeb
+#define OPCODE_READ_ID 0x9f
+#define OPCODE_PROGRAM_LOAD_RANDOM_DATA 0x84
+#define OPCODE_PROGRAM_LOAD_RANDOM_DATAX4 0xc4
+#define OPCODE_PROGRAM_LOAD_RANDOM_DATA_QUADIO 0x72
+#define OPCODE_PROGRAM_EXECUTE 0x10
+#define OPCODE_BLOCK_ERASE 0xd8
+#define OPCODE_FLASH_RESET 0Xff
+
+//spi nand state
+#define NANDFC_SPI_PROG_FAIL (1 << 3)
+#define NANDFC_SPI_ERASE_FAIL (1 << 2)
+#define NANDFC_SPI_OPERATE_ERROR (1 << 0)
+
+typedef enum {
+	SPINAND_TYPE_SPI2K = 16,	// SPI, 2048+64, 2Gb
+	SPINAND_TYPE_SPI4K = 17,	// SPI, 4096+128, 4Gb
+	SPINAND_TYPE_INVALID = 0xFF,
+} SPINAND_FLASH_TYPE;
+
+#define PLL_BUS_FREQ	(_TGT_AP_PLL_BUS_FREQ * 1000000)
+/*******************MACRO define***********************************/
+#define REG_READ_UINT32( _reg_ )			(*(volatile unsigned long*)(_reg_))
+#define REG_WRITE_UINT32( _reg_, _val_) 	((*(volatile unsigned long*)(_reg_)) = (unsigned long)(_val_))
+
+/*******************spi nand  global variables define **********************/
+//static u8 g_spi_flash_read_temp_buffer[4352] __attribute__ ((__aligned__(64)));
+/*sram space is not enough, so use sdram space as middle data buffer*/
+static u8 *g_spi_flash_read_temp_buffer = (u8 *)CONFIG_SPL_NAND_MIDDLE_DATA_BUFFER;
+/*******************************************************************/
+
+//#define NAND_DEBUG
+//#define NAND_DEBUG_VERBOSE
+/*read page data with 4k middle buffer:  g_spi_flash_read_temp_buffer[4352],
+   OOB always use middle buffer.*/
+//#define READ_PAGE_DATA_USE_MIDDLE_BUFFER
+#define READ_PAGE_DATA_WITH_SW_MODE
+
+#define hal_gettime     get_ticks
+#define SECOND          * CONFIG_SYS_HZ_CLOCK
+#define NAND_TIMEOUT    ( 2 SECOND )
+
+/* clock division value map */
+const static u8 clk_div_map[] = {
+	4*60,	/* 0 */
+	4*60,	/* 1 */
+	4*60,	/* 2 */
+	4*60,	/* 3 */
+	4*60,	/* 4 */
+	4*60,	/* 5 */
+	4*60,	/* 6 */
+	4*60,	/* 7 */
+	4*40,	/* 8 */
+	4*30,	/* 9 */
+	4*24,	/* 10 */
+	4*20,	/* 11 */
+	4*17,	/* 12 */
+	4*15,	/* 13 */
+	4*13,	/* 14 */
+	4*12,	/* 15 */
+	4*11,	/* 16 */
+	4*10,	/* 17 */
+	4*9,	/* 18 */
+	4*8,	/* 19 */
+	4*7,	/* 20 */
+	4*13/2,	/* 21 */
+	4*6,	/* 22 */
+	4*11/2,	/* 23 */
+	4*5,	/* 24 */
+	4*9/2,	/* 25 */
+	4*4,	/* 26 */
+	4*7/2,	/* 27 */
+	4*3,	/* 28 */
+	4*5/2,	/* 29 */
+	4*2,	/* 30 */
+	4*1,	/* 31 */
+};
+
+static struct nand_ecclayout spi_nand_oob_64 = {
+	.eccbytes = 16,
+	.eccpos = {
+		   12, 13, 14, 15, 28, 29, 30, 31,
+		   44, 45, 46, 47, 60, 61, 62, 63},
+	.oobfree = {
+		    {.offset = 2,
+		     .length = 10},
+		    {.offset = 16,
+		     .length = 12},
+		    {.offset = 32,
+		     .length = 12},
+		    {.offset = 48,
+		     .length = 12}}
+};
+
+static struct nand_ecclayout spi_nand_oob_128 = {
+	.eccbytes = 0,
+	.eccpos = {},
+	.oobfree = {
+		    {.offset = 2,
+		     .length = 126}}
+};
+
+/* Generic flash bbt decriptors
+*/
+static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
+static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
+
+static struct nand_bbt_descr spi_bbt_main_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
+	    | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+	.offs = 8,
+	.len = 4,
+	.veroffs = 16,
+	.maxblocks = 4,
+	.pattern = bbt_pattern
+};
+
+static struct nand_bbt_descr spi_bbt_mirror_descr = {
+	.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
+	    | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
+	.offs = 8,
+	.len = 4,
+	.veroffs = 16,
+	.maxblocks = 4,
+	.pattern = mirror_pattern
+};
+
+void wait_spi_busy(void)
+{				/*spi is busy,wait until idle */
+	u32 data_tmp_32;
+
+	data_tmp_32 = REG_READ_UINT32(SPI_STATUS);
+	while (data_tmp_32 & 0x1) {
+		data_tmp_32 = REG_READ_UINT32(SPI_STATUS);
+	}
+}
+
+void wait_spi_tx_fifo_empty(void)
+{				/*spi tx fifo not empty, wait until empty */
+	u32 data_tmp_32;
+
+	data_tmp_32 = REG_READ_UINT32(SPI_STATUS);
+	while (!(data_tmp_32 & 0x2)) {
+		data_tmp_32 = REG_READ_UINT32(SPI_STATUS);
+	}
+}
+
+void wait_spi_rx_fifo_empty(void)
+{				/*spi rx fifo not empty, wait until empty */
+	u32 data_tmp_32;
+
+	data_tmp_32 = REG_READ_UINT32(SPI_STATUS);
+	while (!(data_tmp_32 & 0x8)) {
+		data_tmp_32 = REG_READ_UINT32(SPI_STATUS);
+	}
+}
+
+void spi_tx_fifo_clear(void)
+{				/*clear spi tx fifo */
+	REG_WRITE_UINT32(SPI_FIFO_CTRL, 0x2);
+	wait_spi_tx_fifo_empty();
+}
+
+void spi_rx_fifo_clear(void)
+{				/*clear spi rx fifo */
+	REG_WRITE_UINT32(SPI_FIFO_CTRL, 0x1);
+	wait_spi_rx_fifo_empty();
+}
+
+static void push_fifo_data(u8 data_array[], u32 data_cnt, BOOL quard_flag,
+			   BOOL clr_flag)
+{
+	u32 data_tmp_32;
+	u16 i = 0;
+
+	if (clr_flag)
+		spi_tx_fifo_clear();
+
+	/*if tx fifo full, wait */
+	data_tmp_32 = REG_READ_UINT32(SPI_STATUS);
+	while (data_tmp_32 & 0x4)
+		data_tmp_32 = REG_READ_UINT32(SPI_STATUS);
+
+	/*put data into fifo */
+	for (i = 0; i < data_cnt; i++) {
+		data_tmp_32 = (u32) data_array[i];
+		if (quard_flag)
+			data_tmp_32 = data_tmp_32 | 0x100;
+		REG_WRITE_UINT32(SPI_DATA_FIFO, data_tmp_32);
+	}
+}
+
+/********************************************************************/
+/*	opmode = 0:	normal operation																		*/
+/*	opmode = 1:	extended serial read																*/
+/*	opmode = 2:	extended quard read																	*/
+/*	opmode = 3:	extended write		(OPCODE_WRITE_ENABLE, flash_addr, opmode, 0);																*/
+/********************************************************************/
+static void start_flash_operation(u8 cmd, u32 addr, u8 opmode, u16 blocksize)
+{
+	u32 data_tmp_32;
+
+	wait_spi_busy();
+
+	if (blocksize != 0) {
+		data_tmp_32 = REG_READ_UINT32(SPI_BLOCK_SIZE);
+		data_tmp_32 = (data_tmp_32 & (~0x1ff00)) | (blocksize << 8);
+		REG_WRITE_UINT32(SPI_BLOCK_SIZE, data_tmp_32);
+		wait_spi_busy();
+	}
+
+	if (opmode == 0) {
+		data_tmp_32 = ((addr << 8) & 0xffffff00) | cmd;
+		REG_WRITE_UINT32(SPI_CMD_ADDR, data_tmp_32);
+	} else if (opmode == 1) {
+		data_tmp_32 = (((cmd << 8) | 0x10000) & 0x000fff00);
+		REG_WRITE_UINT32(SPI_CMD_ADDR, data_tmp_32);
+	} else if (opmode == 2) {
+		data_tmp_32 = (((cmd << 8) | 0x30000) & 0x000fff00);
+		REG_WRITE_UINT32(SPI_CMD_ADDR, data_tmp_32);
+	} else if (opmode == 3) {
+		data_tmp_32 = ((cmd << 8) & 0x000fff00);
+		REG_WRITE_UINT32(SPI_CMD_ADDR, data_tmp_32);
+	} else {
+		data_tmp_32 = ((cmd << 8) & 0x000fff00);
+		REG_WRITE_UINT32(SPI_CMD_ADDR, data_tmp_32);
+	}
+}
+
+u8 get_flash_feature(u32 flash_addr)
+{
+	u32 data_tmp_32;
+	u8 opmode;
+	u8 data_array[2];
+	u8 data_size;
+	u8 quard_flag;
+
+	quard_flag = FALSE;
+	opmode = 1;
+	data_array[0] = 0xb0;
+	data_size = 1;
+
+	wait_spi_busy();
+	/*clear spi rx fifo */
+	spi_rx_fifo_clear();
+
+	/*put addr into spi tx fifo */
+	push_fifo_data(data_array, data_size, quard_flag, TRUE);
+	/*send command */
+	start_flash_operation(OPCODE_GET_FEATURE, flash_addr, opmode, 1);
+	wait_spi_busy();
+
+	/*wait until rx fifo not empty */
+	data_tmp_32 = REG_READ_UINT32(SPI_STATUS);
+	while (data_tmp_32 & 0x8)
+		data_tmp_32 = REG_READ_UINT32(SPI_STATUS);
+
+	return (REG_READ_UINT32(SPI_READ_BACK) & 0xff);
+}
+
+void set_flash_feature(u8 data)
+{
+	u8 opmode;
+	u8 data_array[2];
+	u8 data_size;
+	BOOL quard_flag;
+
+	quard_flag = FALSE;
+	opmode = 3;
+	data_array[1] = data;
+	data_array[0] = 0xb0;
+	data_size = 2;
+
+	wait_spi_busy();
+	push_fifo_data(data_array, data_size, quard_flag, TRUE);
+	start_flash_operation(OPCODE_SET_FEATURE, 0, opmode, 0);
+	wait_spi_busy();
+	wait_spi_tx_fifo_empty();
+}
+
+static BOOL spi_nand_flash_quad_enable = FALSE;
+void enable_spi_nand_flash_quad_mode(void)
+{
+	u8 data;
+
+	data = get_flash_feature(0);
+	data = data | 0x1;
+	set_flash_feature(data);
+	spi_nand_flash_quad_enable = TRUE;
+}
+
+void disable_spi_nand_flash_quad_mode(void)
+{
+	u8 data;
+
+	data = get_flash_feature(0);
+	data = data & 0xfe;
+	set_flash_feature(data);
+	spi_nand_flash_quad_enable = FALSE;
+}
+
+void enable_spi_nand_flash_ecc_mode(void)
+{
+	u8 data;
+
+	data = get_flash_feature(0);
+	data = data | 0x10;
+	set_flash_feature(data);
+}
+
+void disable_spi_nand_flash_ecc_mode(void)
+{
+	u8 data;
+
+	data = get_flash_feature(0);
+	data = data & 0xef;
+	set_flash_feature(data);
+}
+
+u8 get_flash_status(u32 flash_addr)
+{
+	u32 data_tmp_32;
+	u8 opmode;
+	u8 data_array[2];
+	u8 data_size;
+	BOOL quard_flag;
+
+	quard_flag = FALSE;
+	opmode = 1;
+	data_array[0] = 0xc0;
+	data_size = 1;
+
+	wait_spi_busy();
+	spi_rx_fifo_clear();
+
+	wait_spi_busy();
+	push_fifo_data(data_array, data_size, quard_flag, TRUE);
+	start_flash_operation(OPCODE_GET_FEATURE, flash_addr, opmode, 1);
+	wait_spi_busy();
+
+	data_tmp_32 = REG_READ_UINT32(SPI_STATUS);
+	while (data_tmp_32 & 0x8)
+		data_tmp_32 = REG_READ_UINT32(SPI_STATUS);
+
+	return (REG_READ_UINT32(SPI_READ_BACK) & 0xff);
+}
+
+void disable_flash_protection(u32 flash_addr)
+{
+	u8 opmode;
+	u8 data_array[2];
+	u8 data_size;
+
+	opmode = 3;
+	data_array[1] = 0;
+	data_array[0] = 0xa0;
+	data_size = 2;
+
+	wait_spi_busy();
+	push_fifo_data(data_array, data_size, FALSE, TRUE);
+	start_flash_operation(OPCODE_SET_FEATURE, flash_addr, opmode, 0);
+	wait_spi_busy();
+	wait_spi_tx_fifo_empty();
+}
+
+void spi_nand_flash_operate_mode_setting(u8 mode)
+{
+	u32 data_tmp_32;
+
+	data_tmp_32 = REG_READ_UINT32(SPI_NAND_CMD);
+	if (mode == 1)		// 1 command-1 addr- 1 data
+	{
+		data_tmp_32 |= OPCODE_READ_FROM_CACHE << 24;
+	} else if (mode == 2)	// 1 command- 1 addr- 4 data
+	{
+		data_tmp_32 |= OPCODE_READ_FROM_CACHEX4 << 24;
+	} else if (mode == 4)	// 1 command- 4 addr- 4 data
+	{
+		data_tmp_32 |= OPCODE_READ_FROM_CACHE_QUADIO << 24;
+	} else			// default:1 command-1 addr- 1 data
+	{
+		data_tmp_32 |= OPCODE_READ_FROM_CACHE << 24;
+	}
+
+	REG_WRITE_UINT32(SPI_NAND_CMD, data_tmp_32);
+}
+
+u16 get_flash_ID(u32 flash_addr)
+{
+	u32 data_tmp_32;
+	u8 opmode;
+	BOOL quard_flag;
+	u8 data_array[2];
+	u8 data_size;
+	u8 manufacturerID, device_memory_type_ID;
+
+	opmode = 1;
+	data_array[0] = 0x00;
+	data_size = 1;
+	quard_flag = FALSE;
+
+	wait_spi_busy();
+	spi_rx_fifo_clear();
+
+	push_fifo_data(data_array, data_size, quard_flag, TRUE);
+	start_flash_operation(OPCODE_READ_ID, flash_addr, opmode, 2);
+	wait_spi_busy();
+
+	data_tmp_32 = REG_READ_UINT32(SPI_STATUS);
+	while (data_tmp_32 & 0x8)
+		data_tmp_32 = REG_READ_UINT32(SPI_STATUS);
+
+	manufacturerID = (u8) (REG_READ_UINT32(SPI_READ_BACK) & 0xff);
+	device_memory_type_ID = (u8) (REG_READ_UINT32(SPI_READ_BACK) & 0xff);
+
+	return (manufacturerID | (device_memory_type_ID << 8));
+}
+
+void nand_spi_init(BOOL quard_flag, u8 clk_offset_val, u8 clkdiv_val)
+{
+	u32 data_tmp_32;
+
+	wait_spi_busy();
+	data_tmp_32 = ((clk_offset_val << 4) | (clkdiv_val << 8)) & 0xff70;
+	REG_WRITE_UINT32(SPI_CONFIG, data_tmp_32);
+	wait_spi_busy();
+
+	if (quard_flag) {
+		enable_spi_nand_flash_quad_mode();
+		spi_nand_flash_operate_mode_setting(4);
+	}else{
+		disable_spi_nand_flash_quad_mode();
+		spi_nand_flash_operate_mode_setting(1);
+	}
+
+	enable_spi_nand_flash_ecc_mode();
+}
+
+static void nand_spi_fifo_word_read_set(BOOL enable)
+{
+	u32 data_tmp_32;
+
+	wait_spi_busy();
+	data_tmp_32 = REG_READ_UINT32(SPI_CONFIG);
+	if(enable)
+		data_tmp_32 = (data_tmp_32 & (~(3 << 17))) |(2 << 17);
+	else
+		data_tmp_32 = data_tmp_32 & (~(3 << 17));
+	REG_WRITE_UINT32(SPI_CONFIG, data_tmp_32);
+	wait_spi_busy();
+}
+
+static int init_spi_nand_info(struct rda_nand_info *info,
+			      int nand_type, int bus_width_16)
+{
+	info->type = nand_type;
+	switch (nand_type) {
+	case SPINAND_TYPE_SPI2K:
+		info->hard_ecc_hec = 0;
+		info->bus_width_16 = bus_width_16;
+		info->page_shift = 11;
+		info->oob_size = 64;
+		info->page_num_per_block = 64;
+		info->vir_page_size = 2048;
+		info->vir_page_shift = 11;
+		info->vir_oob_size = 64;
+		info->vir_erase_size =
+		    info->vir_page_size * info->page_num_per_block;
+		break;
+	case SPINAND_TYPE_SPI4K:
+		info->hard_ecc_hec = 0;
+		info->bus_width_16 = bus_width_16;
+		info->page_shift = 12;
+		info->oob_size = 128;
+		info->page_num_per_block = 64;
+		info->vir_page_size = 4096;
+		info->vir_page_shift = 12;
+		info->vir_oob_size = 128;
+		info->vir_erase_size =
+		    info->vir_page_size * info->page_num_per_block;
+		break;
+	default:
+		printf("invalid nand type\n");
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static u8 spi_nand_rda_read_byte(struct mtd_info *mtd)
+{
+	u8 ret;
+	struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	ret = *((u8 *) info->byte_buf + info->index);
+	info->index++;
+#ifdef NAND_DEBUG
+	printf("spi_nand_read_byte, ret = %02x\n", ret);
+#endif
+	return ret;
+}
+
+static u16 spi_nand_rda_read_word(struct mtd_info *mtd)
+{
+	u16 ret;
+	struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	ret = *(u16 *) ((uint8_t *) info->byte_buf + info->index);
+	info->index += 2;
+#ifdef NAND_DEBUG
+	printf("spi_nand_read_word, ret = %04x\n", ret);
+#endif
+	return ret;
+}
+
+#ifdef READ_PAGE_DATA_WITH_SW_MODE
+static void spi_nand_flash_page_read2cache(u32 page_addr)
+{
+	u32 data_tmp_32;
+	u8 opmode;
+	u8 data_array[3];
+	u8 data_size;
+
+#ifdef NAND_DEBUG
+	printf("spi nand: OOB read to cache!page addr = %x\n", page_addr);
+#endif
+	opmode = 3;
+	data_array[2] = (u8)(page_addr & 0xff);
+	data_array[1] =  (u8)((page_addr >> 8) & 0xff);
+	data_array[0] =  (u8)((page_addr >> 16) & 0xff);
+	data_size = 3;
+
+	wait_spi_busy();
+	push_fifo_data(data_array, data_size, FALSE, TRUE);
+	start_flash_operation(OPCODE_PAGE_READ_2_CACHE, 0, opmode, 0);
+	wait_spi_busy();
+
+       data_tmp_32 = get_flash_status(0);
+       while (1)
+	{
+		if ((data_tmp_32 & 0x1) == 0)
+		{
+			break;
+		}
+		else
+		{
+			data_tmp_32 = get_flash_status(0);
+		}
+	}
+}
+#endif
+
+#define __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__  64   //bytes,  16 words
+static void spi_nand_flash_read_from_cache(u8 * buffer, u32 page_column_addr,
+					   u16 length)
+{
+	u32 data_tmp_32;
+	u8 opmode, i;
+	u8 data_array[3];
+	u8 data_size;
+	u32 data_count, data_value;
+	u32 loop_div_count, loop_mod_count;
+	BOOL quard_flag = FALSE;
+	u8 command = OPCODE_READ_FROM_CACHE;
+	u32 temp_column_addr;
+
+#ifdef NAND_DEBUG
+	printf
+	    ("spi nand: OOB read from cache to buffer!buffer_addr = %x, column = %x, length = %d\n",
+	     (u32) buffer, page_column_addr, length);
+#endif
+	opmode = 1;
+	data_array[2] = 0;
+	data_size = 3;
+
+	if (spi_nand_flash_quad_enable) {
+		command = OPCODE_READ_FROM_CACHE_QUADIO;
+		quard_flag = TRUE;
+		opmode = 0;
+	}
+#if  0
+	for (data_count = 0; data_count < length / 16; data_count++) {
+		temp_column_addr = page_column_addr + 16 * data_count;
+		data_array[1] = (u8) (temp_column_addr & 0xff);
+		data_array[0] = ((temp_column_addr >> 8) & 0x0f);
+
+		wait_spi_busy();
+		spi_rx_fifo_clear();
+
+		wait_spi_busy();
+		if (spi_nand_flash_quad_enable) {
+			start_flash_operation(command, temp_column_addr, opmode,
+					      16);
+		} else {
+			push_fifo_data(data_array, data_size, quard_flag, TRUE);
+			start_flash_operation(command, 0, opmode, 16);
+		}
+		wait_spi_busy();
+#ifdef NAND_DEBUG
+		printf
+		    ("read OOB: data [0] =  %x, data{1] = %x, data[2] = %x, quard_flag = %d, opmode = %d\n",
+		     data_array[0], data_array[1], data_array[2], quard_flag,
+		     opmode);
+#endif
+		for (i = 0; i < 16; i++) {
+			data_tmp_32 = REG_READ_UINT32(SPI_STATUS);
+			while (data_tmp_32 & 0x8)
+				data_tmp_32 = REG_READ_UINT32(SPI_STATUS);
+
+			buffer[data_count * 16 + i] =
+			    (u8) (REG_READ_UINT32(SPI_READ_BACK) & 0xff);
+#ifdef NAND_DEBUG
+			printf("buffer[%d] = %x \n", data_count * 16 + i,
+			       buffer[data_count * 16 + i]);
+#endif
+		}
+	}
+
+	if ((length % 16) > 0) {
+		temp_column_addr = page_column_addr + 16 * data_count;
+		data_array[1] = (u8) (temp_column_addr & 0xff);
+		data_array[0] = ((temp_column_addr >> 8) & 0x0f);
+
+		wait_spi_busy();
+		spi_rx_fifo_clear();
+
+		wait_spi_busy();
+		if (spi_nand_flash_quad_enable) {
+			start_flash_operation(command, temp_column_addr, opmode,
+					      length % 16);
+		} else {
+			push_fifo_data(data_array, data_size, quard_flag, TRUE);
+			start_flash_operation(command, 0, opmode, length % 16);
+		}
+		wait_spi_busy();
+
+		for (i = 0; i < (length % 16); i++) {
+			data_tmp_32 = REG_READ_UINT32(SPI_STATUS);
+			while (data_tmp_32 & 0x8)
+				data_tmp_32 = REG_READ_UINT32(SPI_STATUS);
+
+			buffer[data_count * 16 + i] =
+			    (u8) (REG_READ_UINT32(SPI_READ_BACK) & 0xff);
+#ifdef NAND_DEBUG
+			printf("buffer[%d] = %x \n", data_count * 16 + i,
+			       buffer[data_count * 16 + i]);
+#endif
+		}
+	}
+#else
+	nand_spi_fifo_word_read_set(TRUE);
+	if (length  > 0) {
+		loop_div_count = length / __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__;
+		loop_mod_count = length % __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__;
+		for (data_count = 0; data_count < loop_div_count; data_count++) {
+			temp_column_addr = page_column_addr + __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__ * data_count;
+		data_array[1] = (u8) (temp_column_addr & 0xff);
+		data_array[0] = ((temp_column_addr >> 8) & 0x0f);
+
+		wait_spi_busy();
+		spi_rx_fifo_clear();
+
+		wait_spi_busy();
+		if (spi_nand_flash_quad_enable) {
+			start_flash_operation(command, temp_column_addr, opmode,
+						      __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__);
+		} else {
+			push_fifo_data(data_array, data_size, quard_flag, TRUE);
+			start_flash_operation(command, 0, opmode, __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__);
+		}
+		wait_spi_busy();
+
+		for (i = 0; i < __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__; i += 4) {
+			data_tmp_32 = REG_READ_UINT32(SPI_STATUS);
+			while (data_tmp_32 & 0x8)
+				data_tmp_32 = REG_READ_UINT32(SPI_STATUS);
+
+				data_value = REG_READ_UINT32(SPI_READ_BACK);
+
+				buffer[i + data_count * __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__] = (u8) (data_value & 0xff);
+				buffer[i + 1 + data_count * __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__] = (u8) ((data_value >> 8) & 0xff);
+				buffer[i + 2 + data_count * __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__] = (u8) ((data_value >> 16) & 0xff);
+				buffer[i + 3 + data_count * __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__] = (u8) ((data_value >> 24) & 0xff);
+#ifdef NAND_DEBUG
+				printf("buffer[%d] = %x \n", i + data_count * __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__,
+								buffer[i + data_count * __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__]);
+				printf("buffer[%d] = %x \n", i + 1 + data_count * __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__,
+								buffer[i + 1 + data_count * __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__]);
+				printf("buffer[%d] = %x \n", i + 2 + data_count * __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__,
+								buffer[i + 2 + data_count * __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__]);
+				printf("buffer[%d] = %x \n", i + 3 + data_count * __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__,
+								buffer[i + 3 + data_count * __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__]);
+#endif
+			}
+		}
+
+		if(loop_mod_count){
+			temp_column_addr = page_column_addr + __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__ * data_count;
+			data_array[1] = (u8) (temp_column_addr & 0xff);
+			data_array[0] = ((temp_column_addr >> 8) & 0x0f);
+			wait_spi_busy();
+			spi_rx_fifo_clear();
+			wait_spi_busy();
+			if (spi_nand_flash_quad_enable) {
+				start_flash_operation(command, temp_column_addr, opmode, loop_mod_count);
+			} else {
+				push_fifo_data(data_array, data_size, quard_flag, TRUE);
+				start_flash_operation(command, 0, opmode, loop_mod_count);
+			}
+			wait_spi_busy();
+
+			for (i = 0; i < loop_mod_count; i += 4) {
+				data_tmp_32 = REG_READ_UINT32(SPI_STATUS);
+				while (data_tmp_32 & 0x8)
+					data_tmp_32 = REG_READ_UINT32(SPI_STATUS);
+
+				data_value = REG_READ_UINT32(SPI_READ_BACK);
+
+				buffer[i + data_count * __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__] = (u8) (data_value & 0xff);
+				buffer[i + 1 + data_count * __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__] = (u8) ((data_value >> 8) & 0xff);
+				buffer[i + 2 + data_count * __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__] = (u8) ((data_value >> 16) & 0xff);
+				buffer[i + 3 + data_count * __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__] = (u8) ((data_value >> 24) & 0xff);
+#ifdef NAND_DEBUG
+				printf("buffer[%d] = %x \n", i + data_count * __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__,
+								buffer[i + data_count * __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__]);
+				printf("buffer[%d] = %x \n", i + 1 + data_count * __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__,
+								buffer[i + 1 + data_count * __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__]);
+				printf("buffer[%d] = %x \n", i + 2 + data_count * __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__,
+								buffer[i + 2 + data_count * __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__]);
+				printf("buffer[%d] = %x \n", i + 3 + data_count * __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__,
+								buffer[i + 3 + data_count * __SPI_NAND_CONTROLLER_RCV_FIFO_LEVEL__]);
+#endif
+				}
+		}
+	}
+	nand_spi_fifo_word_read_set(FALSE);
+#endif
+}
+
+static void spi_nand_read_flash_data2buffer(struct mtd_info *mtd, u32 page_addr)
+{
+#ifndef READ_PAGE_DATA_WITH_SW_MODE
+	u32 flash_addr =
+	    SPI_NAND_READ_DATA_BUFFER_BASE + page_addr * mtd->writesize;
+#endif
+
+#ifdef NAND_DEBUG
+	printf("read flash : page addr = %x, flash_addr = %x\n", page_addr,
+	       flash_addr);
+#endif /* NAND_DEBUG */
+
+#if 1// ndef CONFIG_NAND_RDA_DMA
+#ifdef READ_PAGE_DATA_WITH_SW_MODE
+	spi_nand_flash_page_read2cache(page_addr);
+	spi_nand_flash_read_from_cache(&g_spi_flash_read_temp_buffer[0],
+				0, mtd->writesize);
+#else
+	memcpy((void *)(&g_spi_flash_read_temp_buffer[0]), (void *)flash_addr,
+	       mtd->writesize);
+#endif
+#ifdef NAND_DEBUG
+	printf("read flash: dst_addr = %x, src_addr = %x, length = %x\n",
+	       (u32) (&g_spi_flash_read_temp_buffer[0]), flash_addr,
+	       mtd->writesize);
+#endif /* NAND_DEBUG */
+#else
+	struct nand_chip *chip = mtd->priv;
+	struct rda_dma_chan_params dma_param;
+	dma_addr_t phys_addr;
+	void *addr = (void *)(&g_spi_flash_read_temp_buffer[0]);
+	int ret = 0;
+	struct rda_nand_info *info = chip->priv;
+
+	phys_addr = dma_map_single(addr, mtd->writesize, DMA_FROM_DEVICE);
+
+	dma_param.src_addr = flash_addr;
+	dma_param.dst_addr = phys_addr;
+	dma_param.xfer_size = mtd->writesize;
+	//dma_param.dma_mode = RDA_DMA_FR_MODE;
+	dma_param.dma_mode = RDA_DMA_NOR_MODE;
+
+	ret = rda_set_dma_params(info->dma_ch, &dma_param);
+	if (ret < 0) {
+		printf("rda spi nand : Failed to set parameter\n");
+		dma_unmap_single(addr, mtd->writesize, DMA_FROM_DEVICE);
+		return;
+	}
+
+	/* use flush to avoid annoying unaligned warning */
+	/* however, invalidate after the dma it the right thing to do */
+	flush_dcache_range((u32) addr, (u32) (addr + mtd->writesize));
+
+	rda_start_dma(info->dma_ch);
+	rda_poll_dma(info->dma_ch);
+	rda_stop_dma(info->dma_ch);
+
+	/* use flush to avoid annoying unaligned warning */
+	//invalidate_dcache_range((u32)addr, (u32)(addr + len));
+
+	/* Free the specified physical address */
+	dma_unmap_single(addr, mtd->writesize, DMA_FROM_DEVICE);
+#ifdef NAND_DEBUG
+	printf("read flash, middle buf-data:\n");
+	rda_dump_buf((char *)addr, mtd->writesize);
+#endif
+#endif
+}
+
+static void spi_nand_rda_read_buf(struct mtd_info *mtd, uint8_t * buf, int len)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	u8 *nand_ptr = (u8 *) (g_spi_flash_read_temp_buffer + info->read_ptr);
+#ifndef READ_PAGE_DATA_USE_MIDDLE_BUFFER
+#ifndef READ_PAGE_DATA_WITH_SW_MODE
+	u32 flash_addr =
+	    SPI_NAND_READ_DATA_BUFFER_BASE + info->page_addr * mtd->writesize;
+#endif/*READ_PAGE_DATA_WITH_SW_MODE*/
+#endif/*READ_PAGE_DATA_USE_MIDDLE_BUFFER*/
+
+#ifdef NAND_DEBUG
+	printf
+	    ("read buf: buf addr = %x, len = %d,  nand_ptr = %x, read_ptr = %d\n",
+	     (u32) buf, len, (u32) nand_ptr, info->read_ptr);
+#endif /* NAND_DEBUG */
+
+#if 1//ndef CONFIG_NAND_RDA_DMA
+#ifdef READ_PAGE_DATA_USE_MIDDLE_BUFFER
+	memcpy((void *)buf, (void *)nand_ptr, len);
+#else
+	if(info->read_ptr == 0){
+#ifndef READ_PAGE_DATA_WITH_SW_MODE		
+		memcpy((void *)buf, (void *)flash_addr, mtd->writesize);
+#else
+		spi_nand_flash_page_read2cache(info->page_addr);
+		spi_nand_flash_read_from_cache(buf, 0, mtd->writesize);
+#endif
+		spi_nand_flash_read_from_cache(&g_spi_flash_read_temp_buffer[mtd->writesize],
+				mtd->writesize, mtd->oobsize);
+		/*gigadevice flash hardware reserved block, add to BBT, 0xffe0000, 0x1ffc0000 */
+		if ((0xffe0000 == info->page_addr * mtd->writesize && info->type == SPINAND_TYPE_SPI2K)
+		|| (0x1ffc0000 == info->page_addr * mtd->writesize && info->type == SPINAND_TYPE_SPI4K)){
+			memset((void *)buf, 0, len);
+			memset(&g_spi_flash_read_temp_buffer[0], 0,
+			       mtd->writesize + mtd->oobsize);
+		}
+	}else{
+		memcpy((void *)buf, (void *)nand_ptr, len);
+	}
+#endif/*READ_PAGE_DATA_USE_MIDDLE_BUFFER*/
+
+	info->read_ptr += len;
+
+#ifdef NAND_DEBUG
+	printf("read buf, dst buf:\n");
+	rda_dump_buf((char *)buf, len);
+#endif
+
+#else
+	struct rda_dma_chan_params dma_param;
+	dma_addr_t phys_addr;
+	void *addr = (void *)buf;
+	int ret = 0;
+
+	/*
+	 * If size is less than the size of oob,
+	 * we copy directly them to mapping buffer.
+	 */
+	if (len <= mtd->oobsize) {
+		memcpy(buf, (void *)nand_ptr, len);
+		info->read_ptr = 0;
+#ifdef NAND_DEBUG
+		printf("read buf, dst buf-oob:\n");
+		rda_dump_buf((char *)buf, len);
+#endif
+		return;
+	}
+
+	phys_addr = dma_map_single(addr, len, DMA_BIDIRECTIONAL);
+
+	dma_param.src_addr = (u32) nand_ptr;
+	dma_param.dst_addr = phys_addr;
+	dma_param.xfer_size = len;
+	//dma_param.dma_mode = RDA_DMA_FR_MODE;
+	dma_param.dma_mode = RDA_DMA_NOR_MODE;
+
+	ret = rda_set_dma_params(info->dma_ch, &dma_param);
+	if (ret < 0) {
+		printf("rda spi nand : Failed to set parameter\n");
+		dma_unmap_single(addr, len, DMA_BIDIRECTIONAL);
+		return;
+	}
+
+	/* use flush to avoid annoying unaligned warning */
+	/* however, invalidate after the dma it the right thing to do */
+	flush_dcache_range((u32) addr, (u32) (addr + len));
+
+	rda_start_dma(info->dma_ch);
+	rda_poll_dma(info->dma_ch);
+	rda_stop_dma(info->dma_ch);
+
+	/* use flush to avoid annoying unaligned warning */
+	//invalidate_dcache_range((u32)addr, (u32)(addr + len));
+
+	/* Free the specified physical address */
+	dma_unmap_single(addr, len, DMA_BIDIRECTIONAL);
+	info->read_ptr += len;
+
+#ifdef NAND_DEBUG
+	printf("read buf, dst buf-data:\n");
+	rda_dump_buf((char *)addr, len);
+#endif
+
+	return;
+#endif /* CONFIG_NAND_RDA_DMA */
+}
+
+static void spi_nand_flash_write_data2cache_random(u8 * buffer,
+						   u32 page_column_addr,
+						   u32 length,
+						   BOOL bug_mode)
+{
+	u8 opmode;
+	u8 data_array[3];
+	u8 data_size;
+	BOOL quard_flag;
+	u8 opcommand;
+
+	if(bug_mode == FALSE){
+		if (spi_nand_flash_quad_enable) {
+			quard_flag = TRUE;
+			opcommand = OPCODE_PROGRAM_LOAD_RANDOM_DATA_QUADIO;
+		} else {
+			quard_flag = FALSE;
+			opcommand = OPCODE_PROGRAM_LOAD_RANDOM_DATA;
+		}
+
+		opmode = 3;
+		data_array[1] = (u8) (page_column_addr & 0xff);
+		data_array[0] = ((page_column_addr >> 8) & 0x0f);
+		data_size = 2;
+
+		wait_spi_busy();
+		push_fifo_data(data_array, data_size, quard_flag, TRUE);
+		push_fifo_data(buffer, length, quard_flag, FALSE);
+		start_flash_operation(opcommand, 0, opmode, 0);
+	}
+	else{/*0x84 standard mode for spi controller bug*/
+		wait_spi_busy();
+		push_fifo_data(buffer, length, FALSE, TRUE);
+		start_flash_operation(OPCODE_PROGRAM_LOAD_RANDOM_DATA, page_column_addr,
+							0, 0);
+	}
+
+	wait_spi_busy();
+	wait_spi_tx_fifo_empty();
+	wait_spi_busy();
+}
+
+void spi_nand_flash_write_one_page_cache_random(u8 * buffer, u32 length,
+						u32 write_pos)
+{
+	u32 i = 0, m, n;
+	u8 *w_buffer = buffer;
+
+#define SPI_NAND_OPERATE_LENGTH_ONCE  200
+
+//	if (write_pos == 0) {
+		m = length / SPI_NAND_OPERATE_LENGTH_ONCE;
+		n = length % SPI_NAND_OPERATE_LENGTH_ONCE;
+
+		if(n == 0){
+			m = m - 1;
+			n = SPI_NAND_OPERATE_LENGTH_ONCE;
+		}
+
+		if (m > 0) {
+			for (i = 0; i < m; i++) {
+				spi_nand_flash_write_data2cache_random(w_buffer
+								       +
+								       SPI_NAND_OPERATE_LENGTH_ONCE * i,
+								       SPI_NAND_OPERATE_LENGTH_ONCE * i + write_pos,
+								       SPI_NAND_OPERATE_LENGTH_ONCE,
+								       FALSE);
+			}
+		}
+
+		if (n > 0)
+			spi_nand_flash_write_data2cache_random(w_buffer +
+							       SPI_NAND_OPERATE_LENGTH_ONCE * i,
+							       SPI_NAND_OPERATE_LENGTH_ONCE * i + write_pos,
+							       n,
+							       TRUE);
+//	} else {
+//		spi_nand_flash_write_data2cache_random(w_buffer, write_pos,
+//						       length, TRUE);
+//	}
+}
+
+static int spi_nand_flash_program_execute(u32 block_page_addr)
+{
+	u32 data_tmp_32;
+	u8 opmode;
+	u8 data_array[5];
+	u8 data_size;
+
+	start_flash_operation(OPCODE_WRITE_ENABLE, 0, 0, 0);
+	wait_spi_busy();
+
+	opmode = 3;
+	data_array[2] = (u8) (block_page_addr & 0xff);
+	data_array[1] = (u8) ((block_page_addr >> 8) & 0xff);
+	data_array[0] = (u8) ((block_page_addr >> 16) & 0xff);
+	data_size = 3;
+
+	push_fifo_data(data_array, data_size, FALSE, TRUE);
+	start_flash_operation(OPCODE_PROGRAM_EXECUTE, 0, opmode, 0);
+	wait_spi_busy();
+
+	data_tmp_32 = get_flash_status(0);
+	while (1) {
+		if ((data_tmp_32 & 0x1) == 0) {
+			if ((data_tmp_32 & 0x8) == 0x8) {
+				printf("!!program failed page addr  = %x\n ",
+				       block_page_addr);
+				return NANDFC_SPI_PROG_FAIL;
+			}
+			break;
+		} else {
+			data_tmp_32 = get_flash_status(0);
+		}
+	}
+
+	return 0;
+}
+
+static void spi_nand_rda_write_buf(struct mtd_info *mtd, const uint8_t * buf,
+				   int len)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+	u8 *pbuf = (u8 *) buf;
+
+#ifdef NAND_DEBUG
+	printf("spi_nand_rda_write_buf : buf addr = %x, len = %d, write_pos = %d\n", (u32) pbuf,
+	       len, info->write_ptr);
+#endif /* NAND_DEBUG */
+
+#ifdef NAND_DEBUG
+	rda_dump_buf((char *)pbuf, len);
+#endif
+
+	if (len > mtd->writesize) {
+		printf("error: write size is out of page size!\n");
+	}
+
+	spi_nand_flash_write_one_page_cache_random(pbuf, len, info->write_ptr);
+	info->write_ptr += len;
+}
+
+u32 spi_nand_flash_block_erase(u32 block_page_addr)
+{
+	u32 data_tmp_32;
+	u8 opmode;
+	u8 data_array[3];
+	u8 data_size;
+
+	start_flash_operation(OPCODE_WRITE_ENABLE, 0, 0, 0);
+
+	opmode = 3;
+	data_array[2] = (u8) (block_page_addr & 0xff);
+	data_array[1] = ((block_page_addr >> 8) & 0xff);
+	data_array[0] = ((block_page_addr >> 16) & 0x0f);
+	data_size = 3;
+
+	wait_spi_busy();
+	push_fifo_data(data_array, data_size, 0, TRUE);
+	start_flash_operation(OPCODE_BLOCK_ERASE, 0, opmode, 0);
+	wait_spi_busy();
+
+	data_tmp_32 = get_flash_status(0);
+	while (1) {
+		if ((data_tmp_32 & 0x1) == 0) {
+			if ((data_tmp_32 & 0x4) == 0x4) {
+				printf("!!earse failed page addr  = %x \n",
+				       block_page_addr);
+				return NANDFC_SPI_ERASE_FAIL;
+			}
+			break;
+		} else {
+			data_tmp_32 = get_flash_status(0);
+		}
+	}
+	return 0;
+}
+
+static void nand_rda_do_cmd_post(struct mtd_info *mtd)
+{
+	struct nand_chip *this = mtd->priv;
+	struct rda_nand_info *info = this->priv;
+	u8 temp;
+
+	switch (info->cmd) {
+	case NAND_CMD_READID:
+		info->index = 0;
+		break;
+	case NAND_CMD_STATUS:
+		temp = get_flash_status(0);
+#ifdef NAND_DEBUG
+		printf("nand_rda_do_cmd_post: flash status = %x\n ", temp);
+#endif
+		if ((temp & NANDFC_SPI_ERASE_FAIL)
+		    && (info->cmd_flag == NAND_CMD_ERASE2))
+			info->byte_buf[0] = 0xE0 | NAND_STATUS_FAIL;
+		else if ((temp & NANDFC_SPI_PROG_FAIL)
+			 && (info->cmd_flag == NAND_CMD_PAGEPROG))
+			info->byte_buf[0] = 0xE0 | NAND_STATUS_FAIL;
+		else if (temp & NANDFC_SPI_OPERATE_ERROR)
+			info->byte_buf[0] = 0xE0 | NAND_STATUS_FAIL;
+		else
+			info->byte_buf[0] = 0xE0;
+
+		info->index = 0;
+		info->cmd_flag = 0;
+		break;
+	default:
+		break;
+	}
+}
+
+static void spi_nand_rda_hwcontrol(struct mtd_info *mtd, int cmd,
+				   unsigned int ctrl)
+{
+
+}
+
+static int spi_nand_reset_flash(void)
+{
+	u32 data_tmp_32;
+
+	start_flash_operation(OPCODE_FLASH_RESET, 0, 0, 0);
+	/*delay 10us for reset process */
+	udelay(10);
+
+	data_tmp_32 = get_flash_status(0);
+	while (1) {
+		if ((data_tmp_32 & 0x1) == 0) {
+			break;
+		} else {
+			data_tmp_32 = get_flash_status(0);
+		}
+	}
+	return 0;
+}
+
+static void spi_nand_rda_cmdfunc(struct mtd_info *mtd, unsigned int command,
+				 int column, int page_addr)
+{
+	register struct nand_chip *chip = mtd->priv;
+	struct rda_nand_info *info = chip->priv;
+
+#ifdef NAND_DEBUG
+	printf("nand_rda_cmdfunc, cmd = %x, page_addr = %x, col_addr = %x\n",
+	       command, page_addr, column);
+#endif
+
+	/* remap command */
+	switch (command) {
+	case NAND_CMD_RESET:
+		spi_nand_reset_flash();
+		return;
+
+	case NAND_CMD_READID:
+		info->byte_buf[0] = get_flash_ID(0);
+		info->byte_buf[1] = get_flash_ID(1);
+		info->index = 0;
+#ifdef NAND_DEBUG
+		printf("READID: id = %x \n", info->byte_buf[0]);
+#endif
+		break;
+
+	case NAND_CMD_SEQIN:	/* 0x80 do nothing, just only transfer write addr */
+		info->page_addr = page_addr;
+		info->col_addr = column;
+		info->cmd = NAND_CMD_NONE;
+		info->write_ptr = column;
+		break;
+	case NAND_CMD_READSTART:	/* hw auto gen 0x30 for read */
+		break;
+
+	case NAND_CMD_ERASE1:
+		disable_flash_protection(0);
+		if (NANDFC_SPI_ERASE_FAIL ==
+		    spi_nand_flash_block_erase(page_addr))
+			printf("spi nand: erase failed!page addr = %x\n",
+			       page_addr);
+		break;
+
+	case NAND_CMD_ERASE2:
+#ifdef NAND_DEBUG
+		printf("erase block complete!\n");
+#endif
+		info->cmd_flag = NAND_CMD_ERASE2;
+		info->cmd = NAND_CMD_NONE;
+		break;
+
+	case NAND_CMD_PAGEPROG:	/* 0x10 do the real program */
+		disable_flash_protection(0);
+		if (NANDFC_SPI_PROG_FAIL ==
+		    spi_nand_flash_program_execute(info->page_addr))
+			printf("spi nand: program failed!page addr = %x\n",
+			       page_addr);
+		info->cmd_flag = NAND_CMD_PAGEPROG;
+		info->cmd = NAND_CMD_NONE;
+		info->col_addr = 0;
+		info->write_ptr = 0;
+
+		//spi_nand_flash_cache_flush(mtd, info->page_addr);
+		break;
+
+	case NAND_CMD_READOOB:	/* Emulate NAND_CMD_READOOB */
+		info->page_addr = page_addr;
+		info->col_addr = column + mtd->writesize;
+		info->cmd = NAND_CMD_READ0;
+		/* Offset of oob */
+		info->read_ptr = info->col_addr;
+		/*read page data to cache */
+		spi_nand_read_flash_data2buffer(mtd, page_addr);
+		//spi_nand_flash_page_read2cache(page_addr);
+		spi_nand_flash_read_from_cache(&g_spi_flash_read_temp_buffer
+					       [mtd->writesize], mtd->writesize,
+					       mtd->oobsize);
+
+		/*gigadevice flash hardware reserved block, add to BBT, 0xffe0000, 0x1ffc0000 */
+		if ((0xffe0000 == page_addr * mtd->writesize && info->type == SPINAND_TYPE_SPI2K)
+		|| (0x1ffc0000 == info->page_addr * mtd->writesize && info->type == SPINAND_TYPE_SPI4K))
+			memset(&g_spi_flash_read_temp_buffer[0], 0,
+			       mtd->writesize + mtd->oobsize);
+
+		info->byte_buf[0] =
+		    g_spi_flash_read_temp_buffer[mtd->writesize];
+		info->index = 0;
+
+#ifdef NAND_DEBUG
+		printf("read flash, middle buf-oob0:\n");
+		rda_dump_buf((char *)
+			     &g_spi_flash_read_temp_buffer[mtd->writesize],
+			     mtd->oobsize);
+#endif
+		break;
+
+	case NAND_CMD_READ0:	/* Emulate NAND_CMD_READOOB */
+		info->read_ptr = 0;
+		info->page_addr = page_addr;
+#ifdef READ_PAGE_DATA_USE_MIDDLE_BUFFER
+		/*read page data to cache */
+		spi_nand_read_flash_data2buffer(mtd, page_addr);
+		/*read OOB to cache */
+		//spi_nand_flash_page_read2cache(page_addr);
+		spi_nand_flash_read_from_cache(&g_spi_flash_read_temp_buffer
+					       [mtd->writesize], mtd->writesize,
+					       mtd->oobsize);
+
+		/*gigadevice flash hardware reserved block, add to BBT, 0xffe0000, 0x1ffc0000 */
+		if ((0xffe0000 == page_addr * mtd->writesize && info->type == SPINAND_TYPE_SPI2K)
+		|| (0x1ffc0000 == info->page_addr * mtd->writesize && info->type == SPINAND_TYPE_SPI4K))
+			memset(&g_spi_flash_read_temp_buffer[0], 0,
+			       mtd->writesize + mtd->oobsize);
+#endif/*READ_PAGE_DATA_USE_MIDDLE_BUFFER*/
+
+#ifdef NAND_DEBUG
+		printf("read flash, middle buf-oob1:\n");
+		rda_dump_buf((char *)
+			     &g_spi_flash_read_temp_buffer[mtd->writesize],
+			     mtd->oobsize);
+#endif
+		break;
+
+	default:
+		info->page_addr = page_addr;
+		info->col_addr = column;
+		info->cmd = command;
+		break;
+	}
+
+	if (info->cmd == NAND_CMD_NONE) {
+		return;
+	}
+
+	nand_rda_do_cmd_post(mtd);
+}
+
+static int spi_nand_rda_dev_ready(struct mtd_info *mtd)
+{
+	return 1;
+}
+
+static void nand_rda_select_chip(struct mtd_info *mtd, int chip){}
+
+static int spi_nand_rda_wait(struct mtd_info *mtd, struct nand_chip *chip)
+{
+#ifdef NAND_DEBUG
+	printf("function: spi_nand_rda_wait\n");
+#endif
+	chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
+
+	return (int)chip->read_byte(mtd);
+}
+
+static int spi_nand_read_id(unsigned int id[2])
+{
+	id[0] = get_flash_ID(0);
+	id[1] = get_flash_ID(0);
+
+	printf("Nand ID: %08x %08x\n", id[0], id[1]);
+
+	return 0;
+}
+
+static void read_ID(struct mtd_info *mtd)
+{
+	unsigned int id[2];
+
+	spi_nand_read_id(id);
+}
+
+#define RDA_HW_CFG_BIT_7     (1 << 7)
+#define RDA_HW_CFG_BIT_4     (1 << 4)
+#define RDA_HW_CFG_BIT_3     (1 << 3)
+
+#if defined(CONFIG_MACH_RDA8810)
+static int spi_nand_get_type(struct rda_nand_info *info, unsigned int id[2],
+			     int *rda_nand_type, int *bus_width_16)
+{
+	int metal_id;
+
+	info->spl_adjust_ratio = 2;
+	metal_id = rda_metal_id_get();
+	printf("get type, metal %d\n", metal_id);
+
+	if (metal_id >= 7) {
+		if(id[0] == 0xc4c8 || id[0] == 0xd4c8){
+			*rda_nand_type = SPINAND_TYPE_SPI4K;
+			info->spl_adjust_ratio = 4; //actually ratio * 2
+		}else{
+			*rda_nand_type = SPINAND_TYPE_SPI2K;
+		}
+
+		*bus_width_16 = 0;
+	} else {
+		printf("invalid metal id %d\n", metal_id);
+		return -ENODEV;
+	}
+
+	printf("SPL adjust ratio is %d. \n", info->spl_adjust_ratio);
+	return 0;
+}
+#else /* 8810E, 8820, 8850 */
+static int spi_nand_get_type(struct rda_nand_info *info, unsigned int id[2],
+			     int *rda_nand_type, int *bus_width_16)
+{
+	int metal_id;
+
+	info->spl_adjust_ratio = 2;
+	metal_id = rda_metal_id_get();
+	printf("get type, metal %d\n", metal_id);
+
+	if(id[0] == 0xc4c8 || id[0] == 0xd4c8){
+		*rda_nand_type = SPINAND_TYPE_SPI4K;
+		info->spl_adjust_ratio = 4; //actually ratio * 2
+	}else{
+		*rda_nand_type = SPINAND_TYPE_SPI2K;
+	}
+
+	*bus_width_16 = 0;
+
+	printf("SPL adjust ratio is %d. \n", info->spl_adjust_ratio);
+	return 0;
+}
+#endif
+
+static u32 spi_nand_cal_freq_by_divreg(u32 basefreq, u32 reg, u32 div2)
+{
+	u32 newfreq;
+
+	if (reg >= ARRAY_SIZE(clk_div_map)) {
+		printf("nand:Invalid div reg: %u\n", reg);
+		reg = ARRAY_SIZE(clk_div_map) - 1;
+	}
+	/* Assuming basefreq is smaller than 2^31 (2.147G Hz) */
+	newfreq = (basefreq << (div2 ? 0 : 1)) / (clk_div_map[reg] >> 1);
+	return newfreq;
+}
+
+static unsigned long spi_nand_get_master_clk_rate(u32 reg)
+{
+	u32 div2;
+	unsigned long rate;
+
+	div2 = reg & SYS_CTRL_AP_AP_SFLSH_SRC_DIV2;
+	reg = GET_BITFIELD(reg, SYS_CTRL_AP_AP_SFLSH_FREQ);
+	rate = spi_nand_cal_freq_by_divreg(PLL_BUS_FREQ, reg, div2);
+
+	return rate;
+}
+
+static unsigned char spi_nand_calc_divider(struct rda_nand_info *info)
+{
+	unsigned long mclk = info->master_clk;
+	unsigned char div;
+	unsigned long real_clk;
+
+	div = mclk / info->clk;
+	if (mclk % info->clk)
+		div += 1;
+
+	if (div < 2) {
+		/* 2 is minimal divider by hardware */
+		div = 2;
+	}
+
+	if (div > 255) {
+		/* 255 is max divider by hardware */
+		div = 255;
+	}
+
+	real_clk = mclk / div;
+	printf("Spi nand real clock is %ld\n", real_clk);
+	return div;
+}
+
+static unsigned char spi_nand_calc_delay(struct rda_nand_info *info)
+{/*the value need check in future!*/
+	unsigned char delay;
+
+#ifndef _TGT_AP_SPI_NAND_READDELAY
+	unsigned long mclk = info->master_clk;
+	unsigned short clk_val;
+
+	clk_val = mclk / 1000000;
+	if (clk_val <= 220)
+		delay = 2;
+	else 	if (clk_val <= 280)
+		delay = 3;
+	else 	if (clk_val <= 350)
+		delay = 4;
+	else 	if (clk_val <= 420)
+		delay = 5;
+	else
+		delay = 6;
+#else
+		delay = _TGT_AP_SPI_NAND_READDELAY;
+#endif
+
+	printf("read delay:%d\n", delay);
+	return delay;
+}
+
+static int spi_nand_rda_init(struct nand_chip *this, struct rda_nand_info *info)
+{
+	unsigned int id[2];
+	int ret = 0;
+	int rda_nand_type = SPINAND_TYPE_INVALID;
+	int bus_width_16 = 0;
+	BOOL spi_nand_quad_mode = TRUE;
+	unsigned char spi_read_delay = 2; /*AP_CLK_SFLSH clock cycles*/
+	unsigned char spi_controller_div = 4; /*2~8*/
+
+	ret = spi_nand_reset_flash();
+	if (ret)
+		return ret;
+	ret = spi_nand_read_id(id);
+	if (ret)
+		return ret;
+	ret = spi_nand_get_type(info, id, &rda_nand_type, &bus_width_16);
+	if (ret)
+		return ret;
+	ret = init_spi_nand_info(info, rda_nand_type, bus_width_16);
+	if (ret)
+		return ret;
+	if (info->bus_width_16)
+		this->options |= NAND_BUSWIDTH_16;
+
+	spi_controller_div = spi_nand_calc_divider(info);
+	spi_read_delay = spi_nand_calc_delay(info);
+	//nand_spi_init(1, 4, 3);
+	//nand_spi_init(1, 2, 4);
+	nand_spi_init(spi_nand_quad_mode, spi_read_delay, spi_controller_div);
+
+
+	return 0;
+}
+
+static int spi_nand_rda_init_size(struct mtd_info *mtd, struct nand_chip *this,
+				  u8 * id_data)
+{
+	struct rda_nand_info *info = this->priv;
+
+	mtd->erasesize = info->vir_erase_size;
+	mtd->writesize = info->vir_page_size;
+	mtd->oobsize = info->vir_oob_size;
+
+	return (info->bus_width_16) ? NAND_BUSWIDTH_16 : 0;
+}
+
+int rda_spi_nand_init(struct nand_chip *nand)
+{
+	struct rda_nand_info *info;
+	static struct rda_nand_info rda_nand_info;
+
+	info = &rda_nand_info;
+
+	nand->chip_delay = 0;
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
+	nand->options |= NAND_USE_FLASH_BBT;
+#endif
+#ifdef NAND_DEBUG
+	printf("SPINAND: nand_options = %x\n", nand->options);
+#endif
+	/*
+	 * in fact, nand controler we do hardware ECC silently, and
+	 * we don't need tell mtd layer, and will simple nand operations
+	 */
+	nand->ecc.mode = NAND_ECC_NONE;
+	/* Set address of hardware control function */
+	nand->cmd_ctrl = spi_nand_rda_hwcontrol;
+	nand->init_size = spi_nand_rda_init_size;
+	nand->cmdfunc = spi_nand_rda_cmdfunc;
+	nand->read_byte = spi_nand_rda_read_byte;
+	nand->read_word = spi_nand_rda_read_word;
+	nand->read_buf = spi_nand_rda_read_buf;
+	nand->write_buf = spi_nand_rda_write_buf;
+	nand->dev_ready = spi_nand_rda_dev_ready;
+	nand->waitfunc = spi_nand_rda_wait;
+	nand->select_chip = nand_rda_select_chip;
+	nand->read_nand_ID = read_ID;
+	nand->priv = (void *)info;
+	nand->IO_ADDR_R = (void __iomem *)SPI_NAND_READ_DATA_BUFFER_BASE;
+	nand->IO_ADDR_W = (void __iomem *)SPI_NAND_WRITE_DATA_BUFFER_BASE;
+	info->index = 0;
+	info->write_ptr = 0;
+	info->read_ptr = 0;
+	info->cmd_flag = NAND_CMD_NONE;
+	info->master_clk = spi_nand_get_master_clk_rate(_TGT_AP_CLK_SFLSH);
+	info->clk = _TGT_AP_SPI_NAND_CLOCK;
+
+#ifdef CONFIG_NAND_RDA_DMA
+	rda_request_dma(&info->dma_ch);
+#endif /* CONFIG_NAND_RDA_DMA */
+
+	spi_nand_rda_init(nand, info);
+
+	if (!nand->ecc.layout && (nand->ecc.mode != NAND_ECC_SOFT_BCH)) {
+		switch (info->vir_oob_size) {
+		case 64:
+			nand->ecc.layout = &spi_nand_oob_64;
+			break;
+		case 128:
+			nand->ecc.layout = &spi_nand_oob_128;
+			break;
+		default:
+			printf("error oobsize: %d\n",
+			       info->vir_oob_size);
+		}
+	}
+
+	if (nand->options & NAND_USE_FLASH_BBT) {
+		/* Use the default pattern descriptors */
+		if (!nand->bbt_td) {
+			nand->bbt_td = &spi_bbt_main_descr;
+			nand->bbt_md = &spi_bbt_mirror_descr;
+		}
+	}
+
+	printf("SPINAND: Nand Init Done\n");
+	return 0;
+}
+
+#else
+int rda_spi_nand_init(struct nand_chip *nand){return 0;}
+#endif
+
+#if 0
+/* move to rda_nand_base.c */
+int board_nand_init(struct nand_chip *chip) __attribute__ ((weak));
+
+int board_nand_init(struct nand_chip *chip)
+{
+	return rda_spi_nand_init(chip);
+}
+#endif
diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c
index 1d0f196c12..1a7b40eaa3 100644
--- a/drivers/mtd/onenand/onenand_base.c
+++ b/drivers/mtd/onenand/onenand_base.c
@@ -20,7 +20,7 @@
  */
 
 #include <common.h>
-#include <linux/mtd/compat.h>
+#include <linux/compat.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/onenand.h>
 
diff --git a/drivers/mtd/onenand/onenand_bbt.c b/drivers/mtd/onenand/onenand_bbt.c
index 1354877729..9d5da54708 100644
--- a/drivers/mtd/onenand/onenand_bbt.c
+++ b/drivers/mtd/onenand/onenand_bbt.c
@@ -15,7 +15,7 @@
  */
 
 #include <common.h>
-#include <linux/mtd/compat.h>
+#include <linux/compat.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/onenand.h>
 #include <malloc.h>
diff --git a/drivers/mtd/onenand/onenand_uboot.c b/drivers/mtd/onenand/onenand_uboot.c
index c642016c2d..ae60c3bb71 100644
--- a/drivers/mtd/onenand/onenand_uboot.c
+++ b/drivers/mtd/onenand/onenand_uboot.c
@@ -14,7 +14,7 @@
  */
 
 #include <common.h>
-#include <linux/mtd/compat.h>
+#include <linux/compat.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/onenand.h>
 
diff --git a/drivers/mtd/onenand/samsung.c b/drivers/mtd/onenand/samsung.c
index c9d33ec825..0d94ea5b1f 100644
--- a/drivers/mtd/onenand/samsung.c
+++ b/drivers/mtd/onenand/samsung.c
@@ -28,7 +28,7 @@
 
 #include <common.h>
 #include <malloc.h>
-#include <linux/mtd/compat.h>
+#include <linux/compat.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/onenand.h>
 #include <linux/mtd/samsung_onenand.h>
diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index d144ac29bc..ca169a83e0 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -476,21 +476,21 @@ static int attach_by_scanning(struct ubi_device *ubi)
 	if (err)
 		goto out_si;
 
-	err = ubi_eba_init_scan(ubi, si);
-	if (err)
-		goto out_wl;
-
 	err = ubi_wl_init_scan(ubi, si);
 	if (err)
 		goto out_vtbl;
 
+	err = ubi_eba_init_scan(ubi, si);
+	if (err)
+		goto out_wl;
+
 	ubi_scan_destroy_si(si);
 	return 0;
 
-out_vtbl:
-	vfree(ubi->vtbl);
 out_wl:
 	ubi_wl_close(ubi);
+out_vtbl:
+	vfree(ubi->vtbl);
 out_si:
 	ubi_scan_destroy_si(si);
 	return err;
@@ -550,19 +550,18 @@ static int io_init(struct ubi_device *ubi)
 	 * fundamental reason for this assumption. It is just an optimization
 	 * which allows us to avoid costly division operations.
 	 */
-	if (!is_power_of_2(ubi->min_io_size)) {
-		ubi_err("min. I/O unit (%d) is not power of 2",
-			ubi->min_io_size);
-		return -EINVAL;
-	}
-
 	ubi_assert(ubi->hdrs_min_io_size > 0);
 	ubi_assert(ubi->hdrs_min_io_size <= ubi->min_io_size);
 	ubi_assert(ubi->min_io_size % ubi->hdrs_min_io_size == 0);
 
 	/* Calculate default aligned sizes of EC and VID headers */
-	ubi->ec_hdr_alsize = ALIGN(UBI_EC_HDR_SIZE, ubi->hdrs_min_io_size);
-	ubi->vid_hdr_alsize = ALIGN(UBI_VID_HDR_SIZE, ubi->hdrs_min_io_size);
+	if (is_power_of_2(ubi->hdrs_min_io_size)) {
+		ubi->ec_hdr_alsize = ALIGN(UBI_EC_HDR_SIZE, ubi->hdrs_min_io_size);
+		ubi->vid_hdr_alsize = ALIGN(UBI_VID_HDR_SIZE, ubi->hdrs_min_io_size);
+	} else {
+		ubi->ec_hdr_alsize = roundup(UBI_EC_HDR_SIZE, ubi->hdrs_min_io_size);
+		ubi->vid_hdr_alsize = roundup(UBI_VID_HDR_SIZE, ubi->hdrs_min_io_size);
+	}
 
 	dbg_msg("min_io_size      %d", ubi->min_io_size);
 	dbg_msg("hdrs_min_io_size %d", ubi->hdrs_min_io_size);
@@ -574,15 +573,22 @@ static int io_init(struct ubi_device *ubi)
 		ubi->vid_hdr_offset = ubi->vid_hdr_aloffset =
 				      ubi->ec_hdr_alsize;
 	else {
-		ubi->vid_hdr_aloffset = ubi->vid_hdr_offset &
+		if (is_power_of_2(ubi->hdrs_min_io_size))
+			ubi->vid_hdr_aloffset = ubi->vid_hdr_offset &
 						~(ubi->hdrs_min_io_size - 1);
+		else
+			ubi->vid_hdr_aloffset = (ubi->vid_hdr_offset / ubi->hdrs_min_io_size) *
+						ubi->hdrs_min_io_size;
 		ubi->vid_hdr_shift = ubi->vid_hdr_offset -
 						ubi->vid_hdr_aloffset;
 	}
 
 	/* Similar for the data offset */
 	ubi->leb_start = ubi->vid_hdr_offset + UBI_EC_HDR_SIZE;
-	ubi->leb_start = ALIGN(ubi->leb_start, ubi->min_io_size);
+	if (is_power_of_2(ubi->min_io_size))
+		ubi->leb_start = ALIGN(ubi->leb_start, ubi->min_io_size);
+	else
+		ubi->leb_start = roundup(ubi->leb_start, ubi->min_io_size);
 
 	dbg_msg("vid_hdr_offset   %d", ubi->vid_hdr_offset);
 	dbg_msg("vid_hdr_aloffset %d", ubi->vid_hdr_aloffset);
@@ -597,13 +603,24 @@ static int io_init(struct ubi_device *ubi)
 	}
 
 	/* Check sanity */
-	if (ubi->vid_hdr_offset < UBI_EC_HDR_SIZE ||
-	    ubi->leb_start < ubi->vid_hdr_offset + UBI_VID_HDR_SIZE ||
-	    ubi->leb_start > ubi->peb_size - UBI_VID_HDR_SIZE ||
-	    ubi->leb_start & (ubi->min_io_size - 1)) {
-		ubi_err("bad VID header (%d) or data offsets (%d)",
-			ubi->vid_hdr_offset, ubi->leb_start);
-		return -EINVAL;
+	if (is_power_of_2(ubi->min_io_size)) {
+		if (ubi->vid_hdr_offset < UBI_EC_HDR_SIZE ||
+				ubi->leb_start < ubi->vid_hdr_offset + UBI_VID_HDR_SIZE ||
+				ubi->leb_start > ubi->peb_size - UBI_VID_HDR_SIZE ||
+				ubi->leb_start & (ubi->min_io_size - 1)) {
+			ubi_err("bad VID header (%d) or data offsets (%d)",
+				ubi->vid_hdr_offset, ubi->leb_start);
+			return -EINVAL;
+		}
+	} else {
+		if (ubi->vid_hdr_offset < UBI_EC_HDR_SIZE ||
+				ubi->leb_start < ubi->vid_hdr_offset + UBI_VID_HDR_SIZE ||
+				ubi->leb_start > ubi->peb_size - UBI_VID_HDR_SIZE ||
+				(ubi->leb_start % ubi->min_io_size)) {
+			ubi_err("bad VID header (%d) or data offsets (%d)",
+				ubi->vid_hdr_offset, ubi->leb_start);
+			return -EINVAL;
+		}
 	}
 
 	/*
diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c
index d523c94b12..a58b9de06d 100644
--- a/drivers/mtd/ubi/eba.c
+++ b/drivers/mtd/ubi/eba.c
@@ -752,11 +752,19 @@ int ubi_eba_write_leb_st(struct ubi_device *ubi, struct ubi_volume *vol,
 	if (ubi->ro_mode)
 		return -EROFS;
 
-	if (lnum == used_ebs - 1)
-		/* If this is the last LEB @len may be unaligned */
-		len = ALIGN(data_size, ubi->min_io_size);
-	else
-		ubi_assert(!(len & (ubi->min_io_size - 1)));
+	if (is_power_of_2(ubi->min_io_size)) {
+		if (lnum == used_ebs - 1)
+			/* If this is the last LEB @len may be unaligned */
+			len = ALIGN(data_size, ubi->min_io_size);
+		else
+			ubi_assert(!(len & (ubi->min_io_size - 1)));
+	} else {
+		if (lnum == used_ebs - 1)
+			/* If this is the last LEB @len may be unaligned */
+			len = roundup(data_size, ubi->min_io_size);
+		else
+			ubi_assert(!(len % ubi->min_io_size));
+	}
 
 	vid_hdr = ubi_zalloc_vid_hdr(ubi, GFP_NOFS);
 	if (!vid_hdr)
@@ -988,7 +996,10 @@ int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to,
 
 	if (vid_hdr->vol_type == UBI_VID_STATIC) {
 		data_size = be32_to_cpu(vid_hdr->data_size);
-		aldata_size = ALIGN(data_size, ubi->min_io_size);
+		if (is_power_of_2(ubi->min_io_size))
+			aldata_size = ALIGN(data_size, ubi->min_io_size);
+		else
+			aldata_size = roundup(data_size, ubi->min_io_size);
 	} else
 		data_size = aldata_size =
 			    ubi->leb_size - be32_to_cpu(vid_hdr->data_pad);
diff --git a/drivers/mtd/ubi/kapi.c b/drivers/mtd/ubi/kapi.c
index 423d479152..df67cde5af 100644
--- a/drivers/mtd/ubi/kapi.c
+++ b/drivers/mtd/ubi/kapi.c
@@ -400,10 +400,17 @@ int ubi_leb_write(struct ubi_volume_desc *desc, int lnum, const void *buf,
 	if (desc->mode == UBI_READONLY || vol->vol_type == UBI_STATIC_VOLUME)
 		return -EROFS;
 
-	if (lnum < 0 || lnum >= vol->reserved_pebs || offset < 0 || len < 0 ||
-	    offset + len > vol->usable_leb_size ||
-	    offset & (ubi->min_io_size - 1) || len & (ubi->min_io_size - 1))
+	if (is_power_of_2(ubi->min_io_size)) {
+		if (lnum < 0 || lnum >= vol->reserved_pebs || offset < 0 || len < 0 ||
+				offset + len > vol->usable_leb_size ||
+				offset & (ubi->min_io_size - 1) || len & (ubi->min_io_size - 1))
+			return -EINVAL;
+	} else {
+		if (lnum < 0 || lnum >= vol->reserved_pebs || offset < 0 || len < 0 ||
+				offset + len > vol->usable_leb_size ||
+				(offset % ubi->min_io_size) || (len % ubi->min_io_size))
 		return -EINVAL;
+	}
 
 	if (dtype != UBI_LONGTERM && dtype != UBI_SHORTTERM &&
 	    dtype != UBI_UNKNOWN)
@@ -450,9 +457,17 @@ int ubi_leb_change(struct ubi_volume_desc *desc, int lnum, const void *buf,
 	if (desc->mode == UBI_READONLY || vol->vol_type == UBI_STATIC_VOLUME)
 		return -EROFS;
 
-	if (lnum < 0 || lnum >= vol->reserved_pebs || len < 0 ||
-	    len > vol->usable_leb_size || len & (ubi->min_io_size - 1))
-		return -EINVAL;
+	if (is_power_of_2(ubi->min_io_size)) {
+		if (lnum < 0 || lnum >= vol->reserved_pebs || len < 0 ||
+				len > vol->usable_leb_size ||
+				len & (ubi->min_io_size - 1))
+			return -EINVAL;
+	} else {
+		if (lnum < 0 || lnum >= vol->reserved_pebs || len < 0 ||
+				len > vol->usable_leb_size ||
+				(len % ubi->min_io_size))
+			return -EINVAL;
+	}
 
 	if (dtype != UBI_LONGTERM && dtype != UBI_SHORTTERM &&
 	    dtype != UBI_UNKNOWN)
diff --git a/drivers/mtd/ubi/misc.c b/drivers/mtd/ubi/misc.c
index a6410bfb6b..97d806b924 100644
--- a/drivers/mtd/ubi/misc.c
+++ b/drivers/mtd/ubi/misc.c
@@ -38,14 +38,20 @@ int ubi_calc_data_len(const struct ubi_device *ubi, const void *buf,
 {
 	int i;
 
-	ubi_assert(!(length & (ubi->min_io_size - 1)));
+	if (is_power_of_2(ubi->min_io_size))
+		ubi_assert(!(length & (ubi->min_io_size - 1)));
+	else
+		ubi_assert(!(length % ubi->min_io_size));
 
 	for (i = length - 1; i >= 0; i--)
 		if (((const uint8_t *)buf)[i] != 0xFF)
 			break;
 
 	/* The resulting length must be aligned to the minimum flash I/O size */
-	length = ALIGN(i + 1, ubi->min_io_size);
+	if (is_power_of_2(ubi->min_io_size))
+		length = ALIGN(i + 1, ubi->min_io_size);
+	else
+		length = roundup(i + 1, ubi->min_io_size);
 	return length;
 }
 
diff --git a/drivers/mtd/ubi/upd.c b/drivers/mtd/ubi/upd.c
index 5f7ed7b2ef..0c201ceca1 100644
--- a/drivers/mtd/ubi/upd.c
+++ b/drivers/mtd/ubi/upd.c
@@ -241,7 +241,12 @@ static int write_leb(struct ubi_device *ubi, struct ubi_volume *vol, int lnum,
 	int err;
 
 	if (vol->vol_type == UBI_DYNAMIC_VOLUME) {
-		int l = ALIGN(len, ubi->min_io_size);
+		int l;
+
+		if (is_power_of_2(ubi->min_io_size))
+			l = ALIGN(len, ubi->min_io_size);
+		else
+			l = roundup(len, ubi->min_io_size);
 
 		memset(buf + len, 0xFF, l - len);
 		len = ubi_calc_data_len(ubi, buf, l);
@@ -420,7 +425,11 @@ int ubi_more_leb_change_data(struct ubi_device *ubi, struct ubi_volume *vol,
 	vol->upd_received += count;
 
 	if (vol->upd_received == vol->upd_bytes) {
-		int len = ALIGN((int)vol->upd_bytes, ubi->min_io_size);
+		int len;
+		if (is_power_of_2(ubi->min_io_size))
+			len = ALIGN((int)vol->upd_bytes, ubi->min_io_size);
+		else
+			len = roundup((int)vol->upd_bytes, ubi->min_io_size);
 
 		memset(vol->upd_buf + vol->upd_bytes, 0xFF, len - vol->upd_bytes);
 		len = ubi_calc_data_len(ubi, vol->upd_buf, len);
diff --git a/drivers/mtd/ubi/vmt.c b/drivers/mtd/ubi/vmt.c
index ce9fec7fc9..f63730b9fd 100644
--- a/drivers/mtd/ubi/vmt.c
+++ b/drivers/mtd/ubi/vmt.c
@@ -732,8 +732,10 @@ static void paranoid_check_volume(struct ubi_device *ubi, int vol_id)
 		ubi_err("bad alignment");
 		goto fail;
 	}
-
-	n = vol->alignment & (ubi->min_io_size - 1);
+	if (is_power_of_2(ubi->min_io_size))
+		n = vol->alignment & (ubi->min_io_size - 1);
+	else
+		n = vol->alignment % ubi->min_io_size;
 	if (vol->alignment != 1 && n) {
 		ubi_err("alignment is not multiple of min I/O unit");
 		goto fail;
diff --git a/drivers/mtd/ubi/vtbl.c b/drivers/mtd/ubi/vtbl.c
index f679f06494..48cb62786c 100644
--- a/drivers/mtd/ubi/vtbl.c
+++ b/drivers/mtd/ubi/vtbl.c
@@ -174,7 +174,10 @@ static int vtbl_check(const struct ubi_device *ubi,
 			goto bad;
 		}
 
-		n = alignment & (ubi->min_io_size - 1);
+		if (is_power_of_2(ubi->min_io_size))
+			n = alignment & (ubi->min_io_size - 1);
+		else
+			n = alignment % ubi->min_io_size;
 		if (alignment != 1 && n) {
 			err = 5;
 			goto bad;
@@ -758,7 +761,10 @@ int ubi_read_volume_table(struct ubi_device *ubi, struct ubi_scan_info *si)
 		ubi->vtbl_slots = UBI_MAX_VOLUMES;
 
 	ubi->vtbl_size = ubi->vtbl_slots * UBI_VTBL_RECORD_SIZE;
-	ubi->vtbl_size = ALIGN(ubi->vtbl_size, ubi->min_io_size);
+	if (is_power_of_2(ubi->min_io_size))
+		ubi->vtbl_size = ALIGN(ubi->vtbl_size, ubi->min_io_size);
+	else
+		ubi->vtbl_size = roundup(ubi->vtbl_size, ubi->min_io_size);
 
 	sv = ubi_scan_find_sv(si, UBI_LAYOUT_VOLUME_ID);
 	if (!sv) {
diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c
index 73700dd0df..7c6e362f0e 100644
--- a/drivers/net/4xx_enet.c
+++ b/drivers/net/4xx_enet.c
@@ -1557,8 +1557,7 @@ get_speed:
 }
 
 
-static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
-			      int len)
+static int ppc_4xx_eth_send(struct eth_device *dev, void *ptr, int len)
 {
 	struct enet_frame *ef_ptr;
 	ulong time_start, time_now;
diff --git a/drivers/net/altera_tse.c b/drivers/net/altera_tse.c
index 0e6aac7173..de517f8dab 100644
--- a/drivers/net/altera_tse.c
+++ b/drivers/net/altera_tse.c
@@ -257,8 +257,7 @@ static int tse_adjust_link(struct altera_tse_priv *priv)
 	return 0;
 }
 
-static int tse_eth_send(struct eth_device *dev,
-			volatile void *packet, int length)
+static int tse_eth_send(struct eth_device *dev, void *packet, int length)
 {
 	struct altera_tse_priv *priv = dev->priv;
 	volatile struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c
index 52be3a7195..d318a36398 100644
--- a/drivers/net/armada100_fec.c
+++ b/drivers/net/armada100_fec.c
@@ -558,8 +558,7 @@ static void armdfec_halt(struct eth_device *dev)
 	clrbits_le32(&regs->pconf, PCR_EN);
 }
 
-static int armdfec_send(struct eth_device *dev, volatile void *dataptr,
-		    int datasize)
+static int armdfec_send(struct eth_device *dev, void *dataptr, int datasize)
 {
 	struct armdfec_device *darmdfec = to_darmdfec(dev);
 	struct armdfec_reg *regs = darmdfec->regs;
diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c
index 483c831c05..2fa6b686da 100644
--- a/drivers/net/at91_emac.c
+++ b/drivers/net/at91_emac.c
@@ -415,8 +415,7 @@ static void at91emac_halt(struct eth_device *netdev)
 	debug_cond(DEBUG_AT91EMAC, "halt MAC\n");
 }
 
-static int at91emac_send(struct eth_device *netdev, volatile void *packet,
-		     int length)
+static int at91emac_send(struct eth_device *netdev, void *packet, int length)
 {
 	at91_emac_t *emac;
 
diff --git a/drivers/net/ax88180.c b/drivers/net/ax88180.c
index bc3e6ad58a..f5017682d4 100644
--- a/drivers/net/ax88180.c
+++ b/drivers/net/ax88180.c
@@ -604,8 +604,7 @@ static int ax88180_recv (struct eth_device *dev)
 }
 
 /* Send a data block via Ethernet. */
-static int
-ax88180_send (struct eth_device *dev, volatile void *packet, int length)
+static int ax88180_send(struct eth_device *dev, void *packet, int length)
 {
 	struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
 	unsigned short TXDES_addr;
diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c
index dcc781a46a..e24ac4a174 100644
--- a/drivers/net/bfin_mac.c
+++ b/drivers/net/bfin_mac.c
@@ -118,8 +118,7 @@ int bfin_EMAC_initialize(bd_t *bis)
 	return 0;
 }
 
-static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
-			  int length)
+static int bfin_EMAC_send(struct eth_device *dev, void *packet, int length)
 {
 	int i;
 	int result = 0;
@@ -471,7 +470,7 @@ int ether_post_test(int flags)
 	for (i = 0; i < 42; i++)
 		buf[i + 22] = i;
 	printf("--------Send 64 bytes......\n");
-	bfin_EMAC_send(NULL, (volatile void *)buf, 64);
+	bfin_EMAC_send(NULL, buf, 64);
 	for (i = 0; i < 100; i++) {
 		udelay(10000);
 		if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
diff --git a/drivers/net/bfin_mac.h b/drivers/net/bfin_mac.h
index c731c179b5..54ffb3830e 100644
--- a/drivers/net/bfin_mac.h
+++ b/drivers/net/bfin_mac.h
@@ -58,7 +58,7 @@ static ADI_ETHER_BUFFER *SetupTxBuffer(int no);
 
 static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd);
 static void bfin_EMAC_halt(struct eth_device *dev);
-static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet, int length);
+static int bfin_EMAC_send(struct eth_device *dev, void *packet, int length);
 static int bfin_EMAC_recv(struct eth_device *dev);
 static int bfin_EMAC_setup_addr(struct eth_device *dev);
 
diff --git a/drivers/net/calxedaxgmac.c b/drivers/net/calxedaxgmac.c
index 00e26c2adc..e3553d68d8 100644
--- a/drivers/net/calxedaxgmac.c
+++ b/drivers/net/calxedaxgmac.c
@@ -434,7 +434,7 @@ static int xgmac_init(struct eth_device *dev, bd_t * bis)
 	return 0;
 }
 
-static int xgmac_tx(struct eth_device *dev, volatile void *packet, int length)
+static int xgmac_tx(struct eth_device *dev, void *packet, int length)
 {
 	struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
 	struct calxeda_eth_dev *priv = dev->priv;
@@ -442,7 +442,7 @@ static int xgmac_tx(struct eth_device *dev, volatile void *packet, int length)
 	struct xgmac_dma_desc *txdesc = &priv->tx_chain[currdesc];
 	int timeout;
 
-	desc_set_buf_addr_and_size(txdesc, (void *)packet, length);
+	desc_set_buf_addr_and_size(txdesc, packet, length);
 	desc_set_tx_owner(txdesc, TXDESC_FIRST_SEG |
 		TXDESC_LAST_SEG | TXDESC_CRC_EN_APPEND);
 
@@ -476,7 +476,7 @@ static int xgmac_rx(struct eth_device *dev)
 
 	length = desc_get_rx_frame_len(rxdesc);
 
-	NetReceive((volatile unsigned char *)desc_get_buf_addr(rxdesc), length);
+	NetReceive(desc_get_buf_addr(rxdesc), length);
 
 	/* set descriptor back to owned by XGMAC */
 	desc_set_rx_owner(rxdesc);
diff --git a/drivers/net/cs8900.c b/drivers/net/cs8900.c
index e04a784a4b..6aaa0cf49f 100644
--- a/drivers/net/cs8900.c
+++ b/drivers/net/cs8900.c
@@ -215,8 +215,7 @@ static int cs8900_recv(struct eth_device *dev)
 }
 
 /* Send a data block via Ethernet. */
-static int cs8900_send(struct eth_device *dev,
-			volatile void *packet, int length)
+static int cs8900_send(struct eth_device *dev, void *packet, int length)
 {
 	volatile u16 *addr;
 	int tmo;
diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index fbd0f1b7b5..e471d2ce33 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -637,7 +637,7 @@ static int tx_send_loop = 0;
  * positive number (number of bytes transmitted) or negative for error
  */
 static int davinci_eth_send_packet (struct eth_device *dev,
-					volatile void *packet, int length)
+					void *packet, int length)
 {
 	int ret_status = -1;
 	int index;
diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c
index 0fb616ac20..d9fcb5a13e 100644
--- a/drivers/net/dc2114x.c
+++ b/drivers/net/dc2114x.c
@@ -175,7 +175,7 @@ static void  read_hw_addr(struct eth_device* dev, bd_t * bis);
 static void  send_setup_frame(struct eth_device* dev, bd_t * bis);
 
 static int   dc21x4x_init(struct eth_device* dev, bd_t* bis);
-static int   dc21x4x_send(struct eth_device* dev, volatile void *packet, int length);
+static int   dc21x4x_send(struct eth_device *dev, void *packet, int length);
 static int   dc21x4x_recv(struct eth_device* dev);
 static void  dc21x4x_halt(struct eth_device* dev);
 #ifdef CONFIG_TULIP_SELECT_MEDIA
@@ -390,7 +390,7 @@ static int dc21x4x_init(struct eth_device* dev, bd_t* bis)
 	return 0;
 }
 
-static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length)
+static int dc21x4x_send(struct eth_device *dev, void *packet, int length)
 {
 	int		status = -1;
 	int		i;
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index e8e669bd90..9b17db41f6 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -189,8 +189,7 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis)
 	return 0;
 }
 
-static int dw_eth_send(struct eth_device *dev, volatile void *packet,
-		int length)
+static int dw_eth_send(struct eth_device *dev, void *packet, int length)
 {
 	struct dw_eth_dev *priv = dev->priv;
 	struct eth_dma_regs *dma_p = priv->dma_regs_p;
@@ -203,7 +202,7 @@ static int dw_eth_send(struct eth_device *dev, volatile void *packet,
 		return -1;
 	}
 
-	memcpy((void *)desc_p->dmamac_addr, (void *)packet, length);
+	memcpy((void *)desc_p->dmamac_addr, packet, length);
 
 #if defined(CONFIG_DW_ALTDESCRIPTOR)
 	desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c
index 04241109cc..f0c4499edb 100644
--- a/drivers/net/dm9000x.c
+++ b/drivers/net/dm9000x.c
@@ -406,8 +406,7 @@ static int dm9000_init(struct eth_device *dev, bd_t *bd)
   Hardware start transmission.
   Send a packet to media from the upper layer.
 */
-static int dm9000_send(struct eth_device *netdev, volatile void *packet,
-		     int length)
+static int dm9000_send(struct eth_device *netdev, void *packet, int length)
 {
 	int tmo;
 	struct board_info *db = &dm9000_info;
diff --git a/drivers/net/dnet.c b/drivers/net/dnet.c
index 15d0a6e741..944a0c046f 100644
--- a/drivers/net/dnet.c
+++ b/drivers/net/dnet.c
@@ -130,8 +130,7 @@ static u16 dnet_mdio_read(struct dnet_device *dnet, u8 reg)
 	return value;
 }
 
-static int dnet_send(struct eth_device *netdev, volatile void *packet,
-		     int length)
+static int dnet_send(struct eth_device *netdev, void *packet, int length)
 {
 	struct dnet_device *dnet = to_dnet(netdev);
 	int i, wrsz;
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index e726f398d4..94b2a41e14 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c
@@ -5031,10 +5031,9 @@ e1000_poll(struct eth_device *nic)
 /**************************************************************************
 TRANSMIT - Transmit a frame
 ***************************************************************************/
-static int
-e1000_transmit(struct eth_device *nic, volatile void *packet, int length)
+static int e1000_transmit(struct eth_device *nic, void *packet, int length)
 {
-	void * nv_packet = (void *)packet;
+	void *nv_packet = (void *)packet;
 	struct e1000_hw *hw = nic->priv;
 	struct e1000_tx_desc *txp;
 	int i = 0;
diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c
index 07ec34cbba..d2c8277de9 100644
--- a/drivers/net/eepro100.c
+++ b/drivers/net/eepro100.c
@@ -242,8 +242,7 @@ static void purge_tx_ring (struct eth_device *dev);
 static void read_hw_addr (struct eth_device *dev, bd_t * bis);
 
 static int eepro100_init (struct eth_device *dev, bd_t * bis);
-static int eepro100_send (struct eth_device *dev, volatile void *packet,
-						  int length);
+static int eepro100_send(struct eth_device *dev, void *packet, int length);
 static int eepro100_recv (struct eth_device *dev);
 static void eepro100_halt (struct eth_device *dev);
 
@@ -608,7 +607,7 @@ static int eepro100_init (struct eth_device *dev, bd_t * bis)
 	return status;
 }
 
-static int eepro100_send (struct eth_device *dev, volatile void *packet, int length)
+static int eepro100_send(struct eth_device *dev, void *packet, int length)
 {
 	int i, status = -1;
 	int tx_cur;
@@ -691,7 +690,7 @@ static int eepro100_recv (struct eth_device *dev)
 			/* Pass the packet up to the protocol
 			 * layers.
 			 */
-			NetReceive (rx_ring[rx_next].data, length);
+			NetReceive((u8 *)rx_ring[rx_next].data, length);
 		} else {
 			/* There was an error.
 			 */
diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c
index e2011aef4a..c55667c931 100644
--- a/drivers/net/enc28j60.c
+++ b/drivers/net/enc28j60.c
@@ -875,7 +875,7 @@ static int enc_recv(struct eth_device *dev)
  */
 static int enc_send(
 	struct eth_device *dev,
-	volatile void *packet,
+	void *packet,
 	int length)
 {
 	enc_dev_t *enc = dev->priv;
diff --git a/drivers/net/ep93xx_eth.c b/drivers/net/ep93xx_eth.c
index c09384c632..245ad1c25d 100644
--- a/drivers/net/ep93xx_eth.c
+++ b/drivers/net/ep93xx_eth.c
@@ -380,7 +380,7 @@ static int ep93xx_eth_rcv_packet(struct eth_device *dev)
  * Send a block of data via ethernet.
  */
 static int ep93xx_eth_send_packet(struct eth_device *dev,
-				volatile void * const packet, int const length)
+				void * const packet, int const length)
 {
 	struct mac_regs *mac = GET_REGS(dev);
 	struct ep93xx_priv *priv = GET_PRIV(dev);
diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
index 5824fd6827..af06d4fb82 100644
--- a/drivers/net/ethoc.c
+++ b/drivers/net/ethoc.c
@@ -414,7 +414,7 @@ static void ethoc_tx(struct eth_device *dev)
 		(void)ethoc_update_tx_stats(&bd);
 }
 
-static int ethoc_send(struct eth_device *dev, volatile void *packet, int length)
+static int ethoc_send(struct eth_device *dev, void *packet, int length)
 {
 	struct ethoc *priv = (struct ethoc *)dev->priv;
 	struct ethoc_bd bd;
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index d8db9f0c6e..eee41d7c8b 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -187,9 +187,10 @@ int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr,
 #ifndef CONFIG_PHYLIB
 static int miiphy_restart_aneg(struct eth_device *dev)
 {
+	int ret = 0;
+#if !defined(CONFIG_FEC_MXC_NO_ANEG)
 	struct fec_priv *fec = (struct fec_priv *)dev->priv;
 	struct ethernet_regs *eth = fec->bus->priv;
-	int ret = 0;
 
 	/*
 	 * Wake up from sleep if necessary
@@ -213,6 +214,7 @@ static int miiphy_restart_aneg(struct eth_device *dev)
 	if (fec->mii_postcall)
 		ret = fec->mii_postcall(fec->phy_id);
 
+#endif
 	return ret;
 }
 
@@ -398,6 +400,42 @@ static void fec_eth_phy_config(struct eth_device *dev)
 #endif
 }
 
+/*
+ * Do initial configuration of the FEC registers
+ */
+static void fec_reg_setup(struct fec_priv *fec)
+{
+	uint32_t rcntrl;
+
+	/*
+	 * Set interrupt mask register
+	 */
+	writel(0x00000000, &fec->eth->imask);
+
+	/*
+	 * Clear FEC-Lite interrupt event register(IEVENT)
+	 */
+	writel(0xffffffff, &fec->eth->ievent);
+
+
+	/*
+	 * Set FEC-Lite receive control register(R_CNTRL):
+	 */
+
+	/* Start with frame length = 1518, common for all modes. */
+	rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
+	if (fec->xcv_type == SEVENWIRE)
+		rcntrl |= FEC_RCNTRL_FCE;
+	else if (fec->xcv_type == RGMII)
+		rcntrl |= FEC_RCNTRL_RGMII;
+	else if (fec->xcv_type == RMII)
+		rcntrl |= FEC_RCNTRL_RMII;
+	else	/* MII mode */
+		rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
+
+	writel(rcntrl, &fec->eth->r_cntrl);
+}
+
 /**
  * Start the FEC engine
  * @param[in] dev Our device to handle
@@ -512,7 +550,6 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
 {
 	struct fec_priv *fec = (struct fec_priv *)dev->priv;
 	uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
-	uint32_t rcntrl;
 	uint32_t size;
 	int i, ret;
 
@@ -560,33 +597,7 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
 				   (unsigned)fec->rbd_base + size);
 	}
 
-	/*
-	 * Set interrupt mask register
-	 */
-	writel(0x00000000, &fec->eth->imask);
-
-	/*
-	 * Clear FEC-Lite interrupt event register(IEVENT)
-	 */
-	writel(0xffffffff, &fec->eth->ievent);
-
-
-	/*
-	 * Set FEC-Lite receive control register(R_CNTRL):
-	 */
-
-	/* Start with frame length = 1518, common for all modes. */
-	rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
-	if (fec->xcv_type == SEVENWIRE)
-		rcntrl |= FEC_RCNTRL_FCE;
-	else if (fec->xcv_type == RGMII)
-		rcntrl |= FEC_RCNTRL_RGMII;
-	else if (fec->xcv_type == RMII)
-		rcntrl |= FEC_RCNTRL_RMII;
-	else	/* MII mode */
-		rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
-
-	writel(rcntrl, &fec->eth->r_cntrl);
+	fec_reg_setup(fec);
 
 	if (fec->xcv_type == MII10 || fec->xcv_type == MII100)
 		fec_mii_setspeed(fec);
@@ -676,7 +687,7 @@ static void fec_halt(struct eth_device *dev)
  * @param[in] length Data count in bytes
  * @return 0 on success
  */
-static int fec_send(struct eth_device *dev, volatile void *packet, int length)
+static int fec_send(struct eth_device *dev, void *packet, int length)
 {
 	unsigned int status;
 	uint32_t size;
@@ -933,24 +944,7 @@ static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr)
 		udelay(10);
 	}
 
-	/*
-	 * Set interrupt mask register
-	 */
-	writel(0x00000000, &fec->eth->imask);
-
-	/*
-	 * Clear FEC-Lite interrupt event register(IEVENT)
-	 */
-	writel(0xffffffff, &fec->eth->ievent);
-
-	/*
-	 * Set FEC-Lite receive control register(R_CNTRL):
-	 */
-	/*
-	 * Frame length=1518; MII mode;
-	 */
-	writel((PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT) | FEC_RCNTRL_FCE |
-		FEC_RCNTRL_MII_MODE, &fec->eth->r_cntrl);
+	fec_reg_setup(fec);
 	fec_mii_setspeed(fec);
 
 	if (dev_id == -1) {
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index f7ed850c91..f34f4db6b6 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -420,7 +420,7 @@ static void fm_eth_halt(struct eth_device *dev)
 	phy_shutdown(fm_eth->phydev);
 }
 
-static int fm_eth_send(struct eth_device *dev, volatile void *buf, int len)
+static int fm_eth_send(struct eth_device *dev, void *buf, int len)
 {
 	struct fm_eth *fm_eth;
 	struct fm_port_global_pram *pram;
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 0b8c33fb7a..49c74c278a 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -408,6 +408,8 @@ int fm_init_common(int index, struct ccsr_fman *reg)
 		/* flush cache after read */
 		flush_cache((ulong)addr, cnt * 512);
 	}
+#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)
+	void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR;
 #endif
 
 	/* Upload the Fman microcode if it's present */
diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c
index 5330dbc79f..63842cd466 100644
--- a/drivers/net/fsl_mcdmafec.c
+++ b/drivers/net/fsl_mcdmafec.c
@@ -116,7 +116,7 @@ struct fec_info_dma fec_info[] = {
 #endif
 };
 
-static int fec_send(struct eth_device *dev, volatile void *packet, int length);
+static int fec_send(struct eth_device *dev, void *packet, int length);
 static int fec_recv(struct eth_device *dev);
 static int fec_init(struct eth_device *dev, bd_t * bd);
 static void fec_halt(struct eth_device *dev);
@@ -194,7 +194,7 @@ static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd,
 	}
 }
 
-static int fec_send(struct eth_device *dev, volatile void *packet, int length)
+static int fec_send(struct eth_device *dev, void *packet, int length)
 {
 	struct fec_info_dma *info = dev->priv;
 	cbd_t *pTbd, *pUsedTbd;
@@ -301,8 +301,7 @@ static int fec_recv(struct eth_device *dev)
 			frame_length = pRbd->cbd_datlen - 4;
 
 			/* Fill the buffer and pass it to upper layers */
-			NetReceive((volatile uchar *)pRbd->cbd_bufaddr,
-				   frame_length);
+			NetReceive((uchar *)pRbd->cbd_bufaddr, frame_length);
 			len = frame_length;
 		}
 
diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 0af0c3450f..69ba57d3d0 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -480,8 +480,7 @@ static int ftgmac100_recv(struct eth_device *dev)
 /*
  * Send a data block via Ethernet
  */
-static int
-ftgmac100_send(struct eth_device *dev, void *packet, int length)
+static int ftgmac100_send(struct eth_device *dev, void *packet, int length)
 {
 	struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
 	struct ftgmac100_data *priv = dev->priv;
diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c
index 94dc6d99ba..fdd3ec0ac2 100644
--- a/drivers/net/ftmac100.c
+++ b/drivers/net/ftmac100.c
@@ -190,8 +190,7 @@ static int ftmac100_recv (struct eth_device *dev)
 /*
  * Send a data block via Ethernet
  */
-static int
-ftmac100_send (struct eth_device *dev, volatile void *packet, int length)
+static int ftmac100_send(struct eth_device *dev, void *packet, int length)
 {
 	struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase;
 	struct ftmac100_data *priv = dev->priv;
diff --git a/drivers/net/greth.c b/drivers/net/greth.c
index 2aab52f378..08206c8711 100644
--- a/drivers/net/greth.c
+++ b/drivers/net/greth.c
@@ -403,7 +403,7 @@ void greth_halt(struct eth_device *dev)
 	}
 }
 
-int greth_send(struct eth_device *dev, volatile void *eth_data, int data_length)
+int greth_send(struct eth_device *dev, void *eth_data, int data_length)
 {
 	greth_priv *greth = dev->priv;
 	greth_regs *regs = greth->regs;
diff --git a/drivers/net/inca-ip_sw.c b/drivers/net/inca-ip_sw.c
index c45389e0cd..f0f62deaf8 100644
--- a/drivers/net/inca-ip_sw.c
+++ b/drivers/net/inca-ip_sw.c
@@ -158,7 +158,7 @@ static int initialized	= 0;
 
 
 static int inca_switch_init(struct eth_device *dev, bd_t * bis);
-static int inca_switch_send(struct eth_device *dev, volatile void *packet, int length);
+static int inca_switch_send(struct eth_device *dev, void *packet, int length);
 static int inca_switch_recv(struct eth_device *dev);
 static void inca_switch_halt(struct eth_device *dev);
 static void inca_init_switch_chip(void);
@@ -334,7 +334,7 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis)
 }
 
 
-static int inca_switch_send(struct eth_device *dev, volatile void *packet, int length)
+static int inca_switch_send(struct eth_device *dev, void *packet, int length)
 {
 	int		       i;
 	int		       res	= -1;
diff --git a/drivers/net/ks8695eth.c b/drivers/net/ks8695eth.c
index 8e988d1423..b4904b68e5 100644
--- a/drivers/net/ks8695eth.c
+++ b/drivers/net/ks8695eth.c
@@ -190,8 +190,7 @@ static int ks8695_eth_recv(struct eth_device *dev)
 
 /****************************************************************************/
 
-static int ks8695_eth_send(struct eth_device *dev, volatile void *packet,
-	int len)
+static int ks8695_eth_send(struct eth_device *dev, void *packet, int len)
 {
 	volatile struct ks8695_txdesc *dp;
 	static int next = 0;
diff --git a/drivers/net/lan91c96.c b/drivers/net/lan91c96.c
index 24b28da249..11d350eb8d 100644
--- a/drivers/net/lan91c96.c
+++ b/drivers/net/lan91c96.c
@@ -314,7 +314,7 @@ static void smc_shutdown(struct eth_device *dev)
  *	Enable the transmit interrupt, so I know if it failed
  *	Free the kernel data if I actually sent it.
  */
-static int smc_send_packet(struct eth_device *dev, volatile void *packet,
+static int smc_send_packet(struct eth_device *dev, void *packet,
 		int packet_length)
 {
 	byte packet_no;
@@ -700,7 +700,7 @@ static int lan91c96_recv(struct eth_device *dev)
 	return smc_rcv(dev);
 }
 
-static int lan91c96_send(struct eth_device *dev, volatile void *packet,
+static int lan91c96_send(struct eth_device *dev, void *packet,
 		int length)
 {
 	return smc_send_packet(dev, packet, length);
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index c63eea966a..45784678ba 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -197,8 +197,7 @@ int macb_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value)
 
 #if defined(CONFIG_CMD_NET)
 
-static int macb_send(struct eth_device *netdev, volatile void *packet,
-		     int length)
+static int macb_send(struct eth_device *netdev, void *packet, int length)
 {
 	struct macb_device *macb = to_macb(netdev);
 	unsigned long paddr, ctrl;
diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c
index a08ff278bf..ed7459c647 100644
--- a/drivers/net/mcffec.c
+++ b/drivers/net/mcffec.c
@@ -95,7 +95,6 @@ struct fec_info_s fec_info[] = {
 #endif
 };
 
-int fec_send(struct eth_device *dev, volatile void *packet, int length);
 int fec_recv(struct eth_device *dev);
 int fec_init(struct eth_device *dev, bd_t * bd);
 void fec_halt(struct eth_device *dev);
@@ -134,7 +133,7 @@ void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd)
 	}
 }
 
-int fec_send(struct eth_device *dev, volatile void *packet, int length)
+static int fec_send(struct eth_device *dev, void *packet, int length)
 {
 	struct fec_info_s *info = dev->priv;
 	volatile fec_t *fecp = (fec_t *) (info->iobase);
diff --git a/drivers/net/mpc512x_fec.c b/drivers/net/mpc512x_fec.c
index 0d5efd56ea..ad57d566be 100644
--- a/drivers/net/mpc512x_fec.c
+++ b/drivers/net/mpc512x_fec.c
@@ -452,8 +452,8 @@ static void mpc512x_fec_halt (struct eth_device *dev)
 
 /********************************************************************/
 
-static int mpc512x_fec_send (struct eth_device *dev, volatile void *eth_data,
-		int data_length)
+static int mpc512x_fec_send(struct eth_device *dev, void *eth_data,
+			    int data_length)
 {
 	/*
 	 * This routine transmits one frame.  This routine only accepts
diff --git a/drivers/net/mpc5xxx_fec.c b/drivers/net/mpc5xxx_fec.c
index bc8c9222dc..3d180db749 100644
--- a/drivers/net/mpc5xxx_fec.c
+++ b/drivers/net/mpc5xxx_fec.c
@@ -707,7 +707,7 @@ static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
 
 /********************************************************************/
 
-static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data,
+static int mpc5xxx_fec_send(struct eth_device *dev, void *eth_data,
 		int data_length)
 {
 	/*
diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index dcc1547c1c..47bf27c8ba 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -525,8 +525,7 @@ static int mvgbe_write_hwaddr(struct eth_device *dev)
 	return 0;
 }
 
-static int mvgbe_send(struct eth_device *dev, void *dataptr,
-		      int datasize)
+static int mvgbe_send(struct eth_device *dev, void *dataptr, int datasize)
 {
 	struct mvgbe_device *dmvgbe = to_mvgbe(dev);
 	struct mvgbe_registers *regs = dmvgbe->regs;
diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c
index 9386adf87f..04743bd2b3 100644
--- a/drivers/net/natsemi.c
+++ b/drivers/net/natsemi.c
@@ -237,8 +237,7 @@ static void natsemi_init_txd(struct eth_device *dev);
 static void natsemi_init_rxd(struct eth_device *dev);
 static void natsemi_set_rx_mode(struct eth_device *dev);
 static void natsemi_check_duplex(struct eth_device *dev);
-static int natsemi_send(struct eth_device *dev, volatile void *packet,
-			int length);
+static int natsemi_send(struct eth_device *dev, void *packet, int length);
 static int natsemi_poll(struct eth_device *dev);
 static void natsemi_disable(struct eth_device *dev);
 
@@ -754,8 +753,7 @@ natsemi_check_duplex(struct eth_device *dev)
  * Description: transmits a packet and waits for completion or timeout.
  *
  * Returns:   void.  */
-static int
-natsemi_send(struct eth_device *dev, volatile void *packet, int length)
+static int natsemi_send(struct eth_device *dev, void *packet, int length)
 {
 	u32 i, status = 0;
 	u32 tx_status = 0;
diff --git a/drivers/net/ne2000_base.c b/drivers/net/ne2000_base.c
index 8275091871..ef35922042 100644
--- a/drivers/net/ne2000_base.c
+++ b/drivers/net/ne2000_base.c
@@ -749,7 +749,7 @@ static int ne2k_recv(struct eth_device *dev)
 	return 1;
 }
 
-static int ne2k_send(struct eth_device *dev, volatile void *packet, int length)
+static int ne2k_send(struct eth_device *dev, void *packet, int length)
 {
 	int tmo;
 
diff --git a/drivers/net/netarm_eth.c b/drivers/net/netarm_eth.c
index f54817e58d..325f16c3a8 100644
--- a/drivers/net/netarm_eth.c
+++ b/drivers/net/netarm_eth.c
@@ -300,7 +300,7 @@ extern int eth_rx (void)
 }
 
 /* Send a data block via Ethernet. */
-extern int eth_send (volatile void *packet, int length)
+extern int eth_send(void *packet, int length)
 {
 	int i, length32;
 	char *pa;
diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c
index 56ba64fbb0..14243b8a92 100644
--- a/drivers/net/netconsole.c
+++ b/drivers/net/netconsole.c
@@ -29,81 +29,84 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static char input_buffer[512];
-static int input_size = 0;		/* char count in input buffer */
-static int input_offset = 0;		/* offset to valid chars in input buffer */
-static int input_recursion = 0;
-static int output_recursion = 0;
+static int input_size; /* char count in input buffer */
+static int input_offset; /* offset to valid chars in input buffer */
+static int input_recursion;
+static int output_recursion;
 static int net_timeout;
-static uchar nc_ether[6];		/* server enet address */
-static IPaddr_t nc_ip;			/* server ip */
-static short nc_port;			/* source/target port */
-static const char *output_packet;	/* used by first send udp */
-static int output_packet_len = 0;
+static uchar nc_ether[6]; /* server enet address */
+static IPaddr_t nc_ip; /* server ip */
+static short nc_port; /* source/target port */
+static const char *output_packet; /* used by first send udp */
+static int output_packet_len;
 
 static void nc_wait_arp_handler(uchar *pkt, unsigned dest,
 				 IPaddr_t sip, unsigned src,
 				 unsigned len)
 {
-	NetState = NETLOOP_SUCCESS;	/* got arp reply - quit net loop */
+	net_set_state(NETLOOP_SUCCESS); /* got arp reply - quit net loop */
 }
 
 static void nc_handler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src,
 			unsigned len)
 {
 	if (input_size)
-		NetState = NETLOOP_SUCCESS;	/* got input - quit net loop */
+		net_set_state(NETLOOP_SUCCESS); /* got input - quit net loop */
 }
 
-static void nc_timeout (void)
+static void nc_timeout(void)
 {
-	NetState = NETLOOP_SUCCESS;
+	net_set_state(NETLOOP_SUCCESS);
 }
 
-void NcStart (void)
+void NcStart(void)
 {
-	if (!output_packet_len || memcmp (nc_ether, NetEtherNullAddr, 6)) {
+	if (!output_packet_len || memcmp(nc_ether, NetEtherNullAddr, 6)) {
 		/* going to check for input packet */
-		NetSetHandler (nc_handler);
-		NetSetTimeout (net_timeout, nc_timeout);
+		net_set_udp_handler(nc_handler);
+		NetSetTimeout(net_timeout, nc_timeout);
 	} else {
 		/* send arp request */
 		uchar *pkt;
-		NetSetHandler (nc_wait_arp_handler);
-		pkt = (uchar *) NetTxPacket + NetEthHdrSize () + IP_HDR_SIZE;
-		memcpy (pkt, output_packet, output_packet_len);
-		NetSendUDPPacket (nc_ether, nc_ip, nc_port, nc_port, output_packet_len);
+		net_set_arp_handler(nc_wait_arp_handler);
+		pkt = (uchar *)NetTxPacket + NetEthHdrSize() + IP_UDP_HDR_SIZE;
+		memcpy(pkt, output_packet, output_packet_len);
+		NetSendUDPPacket(nc_ether, nc_ip, nc_port, nc_port,
+			output_packet_len);
 	}
 }
 
-int nc_input_packet (uchar * pkt, unsigned dest, unsigned src, unsigned len)
+int nc_input_packet(uchar *pkt, unsigned dest, unsigned src, unsigned len)
 {
 	int end, chunk;
 
 	if (dest != nc_port || !len)
-		return 0;		/* not for us */
+		return 0; /* not for us */
 
-	if (input_size == sizeof input_buffer)
-		return 1;		/* no space */
-	if (len > sizeof input_buffer - input_size)
-		len = sizeof input_buffer - input_size;
+	debug_cond(DEBUG_DEV_PKT, "input: \"%*.*s\"\n", len, len, pkt);
+
+	if (input_size == sizeof(input_buffer))
+		return 1; /* no space */
+	if (len > sizeof(input_buffer) - input_size)
+		len = sizeof(input_buffer) - input_size;
 
 	end = input_offset + input_size;
-	if (end > sizeof input_buffer)
-		end -= sizeof input_buffer;
+	if (end > sizeof(input_buffer))
+		end -= sizeof(input_buffer);
 
 	chunk = len;
-	if (end + len > sizeof input_buffer) {
-		chunk = sizeof input_buffer - end;
+	if (end + len > sizeof(input_buffer)) {
+		chunk = sizeof(input_buffer) - end;
 		memcpy(input_buffer, pkt + chunk, len - chunk);
 	}
-	memcpy (input_buffer + end, pkt, chunk);
+	memcpy(input_buffer + end, pkt, chunk);
 
 	input_size += len;
 
 	return 1;
 }
 
-static void nc_send_packet (const char *buf, int len)
+static void nc_send_packet(const char *buf, int len)
 {
 	struct eth_device *eth;
 	int inited = 0;
@@ -111,33 +114,35 @@ static void nc_send_packet (const char *buf, int len)
 	uchar *ether;
 	IPaddr_t ip;
 
-	if ((eth = eth_get_dev ()) == NULL) {
+	debug_cond(DEBUG_DEV_PKT, "output: \"%*.*s\"\n", len, len, buf);
+
+	eth = eth_get_dev();
+	if (eth == NULL)
 		return;
-	}
 
-	if (!memcmp (nc_ether, NetEtherNullAddr, 6)) {
+	if (!memcmp(nc_ether, NetEtherNullAddr, 6)) {
 		if (eth->state == ETH_STATE_ACTIVE)
 			return;	/* inside net loop */
 		output_packet = buf;
 		output_packet_len = len;
-		NetLoop (NETCONS);	/* wait for arp reply and send packet */
+		NetLoop(NETCONS); /* wait for arp reply and send packet */
 		output_packet_len = 0;
 		return;
 	}
 
 	if (eth->state != ETH_STATE_ACTIVE) {
-		if (eth_init (gd->bd) < 0)
+		if (eth_init(gd->bd) < 0)
 			return;
 		inited = 1;
 	}
-	pkt = (uchar *) NetTxPacket + NetEthHdrSize () + IP_HDR_SIZE;
-	memcpy (pkt, buf, len);
+	pkt = (uchar *)NetTxPacket + NetEthHdrSize() + IP_UDP_HDR_SIZE;
+	memcpy(pkt, buf, len);
 	ether = nc_ether;
 	ip = nc_ip;
-	NetSendUDPPacket (ether, ip, nc_port, nc_port, len);
+	NetSendUDPPacket(ether, ip, nc_port, nc_port, len);
 
 	if (inited)
-		eth_halt ();
+		eth_halt();
 }
 
 static int nc_start(void)
@@ -146,26 +151,33 @@ static int nc_start(void)
 
 	nc_port = 6666;		/* default port */
 
-	if (getenv ("ncip")) {
+	if (getenv("ncip")) {
 		char *p;
 
-		nc_ip = getenv_IPaddr ("ncip");
+		nc_ip = getenv_IPaddr("ncip");
 		if (!nc_ip)
 			return -1;	/* ncip is 0.0.0.0 */
-		if ((p = strchr (getenv ("ncip"), ':')) != NULL)
-			nc_port = simple_strtoul (p + 1, NULL, 10);
+		p = strchr(getenv("ncip"), ':');
+		if (p != NULL)
+			nc_port = simple_strtoul(p + 1, NULL, 10);
 	} else
 		nc_ip = ~0;		/* ncip is not set */
 
-	our_ip = getenv_IPaddr ("ipaddr");
-	netmask = getenv_IPaddr ("netmask");
+	our_ip = getenv_IPaddr("ipaddr");
+	netmask = getenv_IPaddr("netmask");
 
 	if (nc_ip == ~0 ||				/* 255.255.255.255 */
 	    ((netmask & our_ip) == (netmask & nc_ip) &&	/* on the same net */
-	    (netmask | nc_ip) == ~0))			/* broadcast to our net */
-		memset (nc_ether, 0xff, sizeof nc_ether);
+	    (netmask | nc_ip) == ~0))		/* broadcast to our net */
+		memset(nc_ether, 0xff, sizeof(nc_ether));
 	else
-		memset (nc_ether, 0, sizeof nc_ether);	/* force arp request */
+		memset(nc_ether, 0, sizeof(nc_ether));	/* force arp request */
+
+	/*
+	 * Initialize the static IP settings and buffer pointers
+	 * incase we call NetSendUDPPacket before NetLoop
+	 */
+	net_init();
 
 	return 0;
 }
@@ -176,7 +188,7 @@ static void nc_putc(char c)
 		return;
 	output_recursion = 1;
 
-	nc_send_packet (&c, 1);
+	nc_send_packet(&c, 1);
 
 	output_recursion = 0;
 }
@@ -208,14 +220,14 @@ static int nc_getc(void)
 
 	net_timeout = 0;	/* no timeout */
 	while (!input_size)
-		NetLoop (NETCONS);
+		NetLoop(NETCONS);
 
 	input_recursion = 0;
 
 	c = input_buffer[input_offset++];
 
-	if (input_offset >= sizeof input_buffer)
-		input_offset -= sizeof input_buffer;
+	if (input_offset >= sizeof(input_buffer))
+		input_offset -= sizeof(input_buffer);
 	input_size--;
 
 	return c;
@@ -231,28 +243,28 @@ static int nc_tstc(void)
 	if (input_size)
 		return 1;
 
-	eth = eth_get_dev ();
+	eth = eth_get_dev();
 	if (eth && eth->state == ETH_STATE_ACTIVE)
 		return 0;	/* inside net loop */
 
 	input_recursion = 1;
 
 	net_timeout = 1;
-	NetLoop (NETCONS);	/* kind of poll */
+	NetLoop(NETCONS);	/* kind of poll */
 
 	input_recursion = 0;
 
 	return input_size != 0;
 }
 
-int drv_nc_init (void)
+int drv_nc_init(void)
 {
 	struct stdio_dev dev;
 	int rc;
 
-	memset (&dev, 0, sizeof (dev));
+	memset(&dev, 0, sizeof(dev));
 
-	strcpy (dev.name, "nc");
+	strcpy(dev.name, "nc");
 	dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
 	dev.start = nc_start;
 	dev.putc = nc_putc;
@@ -260,7 +272,7 @@ int drv_nc_init (void)
 	dev.getc = nc_getc;
 	dev.tstc = nc_tstc;
 
-	rc = stdio_register (&dev);
+	rc = stdio_register(&dev);
 
 	return (rc == 0) ? 1 : rc;
 }
diff --git a/drivers/net/ns8382x.c b/drivers/net/ns8382x.c
index 11863feba3..cfe1f349db 100644
--- a/drivers/net/ns8382x.c
+++ b/drivers/net/ns8382x.c
@@ -258,8 +258,7 @@ static void ns8382x_init_txd(struct eth_device *dev);
 static void ns8382x_init_rxd(struct eth_device *dev);
 static void ns8382x_set_rx_mode(struct eth_device *dev);
 static void ns8382x_check_duplex(struct eth_device *dev);
-static int ns8382x_send(struct eth_device *dev, volatile void *packet,
-			int length);
+static int ns8382x_send(struct eth_device *dev, void *packet, int length);
 static int ns8382x_poll(struct eth_device *dev);
 static void ns8382x_disable(struct eth_device *dev);
 
@@ -735,8 +734,7 @@ ns8382x_check_duplex(struct eth_device *dev)
 /* Function: ns8382x_send
  * Description: transmits a packet and waits for completion or timeout.
  * Returns:   void.  */
-static int
-ns8382x_send(struct eth_device *dev, volatile void *packet, int length)
+static int ns8382x_send(struct eth_device *dev, void *packet, int length)
 {
 	u32 i, status = 0;
 	vu_long tx_stat = 0;
diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index 45066c8fea..c028a44a9e 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -141,8 +141,7 @@ static int pcnet_check (struct eth_device *dev)
 }
 
 static int pcnet_init (struct eth_device *dev, bd_t * bis);
-static int pcnet_send (struct eth_device *dev, volatile void *packet,
-		       int length);
+static int pcnet_send(struct eth_device *dev, void *packet, int length);
 static int pcnet_recv (struct eth_device *dev);
 static void pcnet_halt (struct eth_device *dev);
 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
@@ -415,8 +414,7 @@ static int pcnet_init (struct eth_device *dev, bd_t * bis)
 	return 0;
 }
 
-static int pcnet_send (struct eth_device *dev, volatile void *packet,
-		       int pkt_len)
+static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
 {
 	int i, status;
 	struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx];
diff --git a/drivers/net/plb2800_eth.c b/drivers/net/plb2800_eth.c
index d799c73823..93782c23ff 100644
--- a/drivers/net/plb2800_eth.c
+++ b/drivers/net/plb2800_eth.c
@@ -82,8 +82,7 @@ typedef volatile struct {
 
 
 static int plb2800_eth_init(struct eth_device *dev, bd_t * bis);
-static int plb2800_eth_send(struct eth_device *dev, volatile void *packet,
-						  int length);
+static int plb2800_eth_send(struct eth_device *dev, void *packet, int length);
 static int plb2800_eth_recv(struct eth_device *dev);
 static void plb2800_eth_halt(struct eth_device *dev);
 
@@ -162,8 +161,7 @@ static int plb2800_eth_init(struct eth_device *dev, bd_t * bis)
 }
 
 
-static int plb2800_eth_send(struct eth_device *dev, volatile void *packet,
-						  int length)
+static int plb2800_eth_send(struct eth_device *dev, void *packet, int length)
 {
 	int                    i;
 	int                    res         = -1;
diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c
index e3feef849c..4186699ff9 100644
--- a/drivers/net/rtl8139.c
+++ b/drivers/net/rtl8139.c
@@ -184,7 +184,7 @@ static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4)));
 static int rtl8139_probe(struct eth_device *dev, bd_t *bis);
 static int read_eeprom(int location, int addr_len);
 static void rtl_reset(struct eth_device *dev);
-static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length);
+static int rtl_transmit(struct eth_device *dev, void *packet, int length);
 static int rtl_poll(struct eth_device *dev);
 static void rtl_disable(struct eth_device *dev);
 #ifdef CONFIG_MCAST_TFTP/*  This driver already accepts all b/mcast */
@@ -407,7 +407,7 @@ static void rtl_reset(struct eth_device *dev)
 	outw(0, ioaddr + IntrMask);
 }
 
-static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length)
+static int rtl_transmit(struct eth_device *dev, void *packet, int length)
 {
 	unsigned int status;
 	unsigned long txstatus;
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index 1ad13bddd5..9864fd7b5c 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -464,7 +464,7 @@ static int rtl_recv(struct eth_device *dev)
 /**************************************************************************
 SEND - Transmit a frame
 ***************************************************************************/
-static int rtl_send(struct eth_device *dev, volatile void *packet, int length)
+static int rtl_send(struct eth_device *dev, void *packet, int length)
 {
 	/* send the packet to destination */
 
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 8d3dac20af..bb57e4d53a 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -46,7 +46,7 @@
 
 #define TIMEOUT_CNT 1000
 
-int sh_eth_send(struct eth_device *dev, volatile void *packet, int len)
+int sh_eth_send(struct eth_device *dev, void *packet, int len)
 {
 	struct sh_eth_dev *eth = dev->priv;
 	int port = eth->port, ret = 0, timeout;
@@ -59,7 +59,7 @@ int sh_eth_send(struct eth_device *dev, volatile void *packet, int len)
 	}
 
 	/* packet must be a 4 byte boundary */
-	if ((int)packet & (4 - 1)) {
+	if ((int)packet & 3) {
 		printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__);
 		ret = -EFAULT;
 		goto err;
@@ -103,15 +103,15 @@ int sh_eth_recv(struct eth_device *dev)
 	struct sh_eth_dev *eth = dev->priv;
 	int port = eth->port, len = 0;
 	struct sh_eth_info *port_info = &eth->port_info[port];
-	volatile u8 *packet;
+	uchar *packet;
 
 	/* Check if the rx descriptor is ready */
 	if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
 		/* Check for errors */
 		if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
 			len = port_info->rx_desc_cur->rd1 & 0xffff;
-			packet = (volatile u8 *)
-			    ADDR_TO_P2(port_info->rx_desc_cur->rd2);
+			packet = (uchar *)
+				ADDR_TO_P2(port_info->rx_desc_cur->rd2);
 			NetReceive(packet, len);
 		}
 
@@ -138,7 +138,7 @@ int sh_eth_recv(struct eth_device *dev)
 static int sh_eth_reset(struct sh_eth_dev *eth)
 {
 	int port = eth->port;
-#if defined(CONFIG_CPU_SH7763)
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 	int ret = 0, i;
 
 	/* Start e-dmac transmitter and receiver */
@@ -208,7 +208,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 	/* Point the controller to the tx descriptor list. Must use physical
 	   addresses */
 	outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port));
-#if defined(CONFIG_CPU_SH7763)
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 	outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port));
 	outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port));
 	outl(0x01, TDFFR(port));/* Last discriptor bit */
@@ -276,7 +276,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 
 	/* Point the controller to the rx descriptor list */
 	outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port));
-#if defined(CONFIG_CPU_SH7763)
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 	outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port));
 	outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port));
 	outl(RDFFR_RDLF, RDFFR(port));
@@ -346,8 +346,9 @@ static int sh_eth_phy_config(struct sh_eth_dev *eth)
 	struct eth_device *dev = port_info->dev;
 	struct phy_device *phydev;
 
-	phydev = phy_connect(miiphy_get_dev_by_name(dev->name),
-			port_info->phy_addr, dev, PHY_INTERFACE_MODE_MII);
+	phydev = phy_connect(
+			miiphy_get_dev_by_name(dev->name),
+			port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
 	port_info->phydev = phydev;
 	phy_config(phydev);
 
@@ -398,12 +399,15 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 	outl(APR_AP, APR(port));
 	outl(MPR_MP, MPR(port));
 #endif
-#if defined(CONFIG_CPU_SH7763)
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 	outl(TPAUSER_TPAUSE, TPAUSER(port));
 #elif defined(CONFIG_CPU_SH7757)
 	outl(TPAUSER_UNLIMITED, TPAUSER(port));
 #endif
 
+#if defined(CONFIG_CPU_SH7734)
+	outl(CONFIG_SH_ETHER_SH7734_MII, RMII_MII(port));
+#endif
 	/* Configure phy */
 	ret = sh_eth_phy_config(eth);
 	if (ret) {
@@ -418,7 +422,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 	/* Set the transfer speed */
 	if (phy->speed == 100) {
 		printf(SHETHER_NAME ": 100Base/");
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 		outl(GECMR_100B, GECMR(port));
 #elif defined(CONFIG_CPU_SH7757)
 		outl(1, RTRATE(port));
@@ -427,12 +431,18 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 #endif
 	} else if (phy->speed == 10) {
 		printf(SHETHER_NAME ": 10Base/");
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 		outl(GECMR_10B, GECMR(port));
 #elif defined(CONFIG_CPU_SH7757)
 		outl(0, RTRATE(port));
 #endif
 	}
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+	else if (phy->speed == 1000) {
+		printf(SHETHER_NAME ": 1000Base/");
+		outl(GECMR_1000B, GECMR(port));
+	}
+#endif
 
 	/* Check if full duplex mode is supported by the phy */
 	if (phy->duplex) {
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 27fde05bd6..a1ba68b1b4 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -188,13 +188,52 @@ struct sh_eth_dev {
 #define TPAUSER(port)	(BASE_IO_ADDR + 0x0164)
 #define MAHR(port)		(BASE_IO_ADDR + 0x01c0)
 #define MALR(port)		(BASE_IO_ADDR + 0x01c8)
+
+#elif defined(CONFIG_CPU_SH7734)
+#define BASE_IO_ADDR	0xFEE00000
+
+#define EDSR(port)		(BASE_IO_ADDR)
+
+#define TDLAR(port)		(BASE_IO_ADDR + 0x0010)
+#define TDFAR(port)		(BASE_IO_ADDR + 0x0014)
+#define TDFXR(port)		(BASE_IO_ADDR + 0x0018)
+#define TDFFR(port)		(BASE_IO_ADDR + 0x001c)
+#define RDLAR(port)		(BASE_IO_ADDR + 0x0030)
+#define RDFAR(port)		(BASE_IO_ADDR + 0x0034)
+#define RDFXR(port)		(BASE_IO_ADDR + 0x0038)
+#define RDFFR(port)		(BASE_IO_ADDR + 0x003c)
+
+#define EDMR(port)		(BASE_IO_ADDR + 0x0400)
+#define EDTRR(port)		(BASE_IO_ADDR + 0x0408)
+#define EDRRR(port)		(BASE_IO_ADDR + 0x0410)
+#define EESR(port)		(BASE_IO_ADDR + 0x0428)
+#define EESIPR(port)	(BASE_IO_ADDR + 0x0430)
+#define TRSCER(port)	(BASE_IO_ADDR + 0x0438)
+#define TFTR(port)		(BASE_IO_ADDR + 0x0448)
+#define FDR(port)		(BASE_IO_ADDR + 0x0450)
+#define RMCR(port)		(BASE_IO_ADDR + 0x0458)
+#define RPADIR(port)	(BASE_IO_ADDR + 0x0460)
+#define FCFTR(port)		(BASE_IO_ADDR + 0x0468)
+#define ECMR(port)		(BASE_IO_ADDR + 0x0500)
+#define RFLR(port)		(BASE_IO_ADDR + 0x0508)
+#define ECSIPR(port)	(BASE_IO_ADDR + 0x0518)
+#define PIR(port)		(BASE_IO_ADDR + 0x0520)
+#define PIPR(port)		(BASE_IO_ADDR + 0x052c)
+#define APR(port)		(BASE_IO_ADDR + 0x0554)
+#define MPR(port)		(BASE_IO_ADDR + 0x0558)
+#define TPAUSER(port)	(BASE_IO_ADDR + 0x0564)
+#define GECMR(port)		(BASE_IO_ADDR + 0x05b0)
+#define MAHR(port)		(BASE_IO_ADDR + 0x05C0)
+#define MALR(port)		(BASE_IO_ADDR + 0x05C8)
+#define RMII_MII(port)  (BASE_IO_ADDR + 0x0790)
+
 #endif
 
 /*
  * Register's bits
  * Copy from Linux driver source code
  */
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 /* EDSR */
 enum EDSR_BIT {
 	EDSR_ENT = 0x01, EDSR_ENR = 0x02,
@@ -205,11 +244,11 @@ enum EDSR_BIT {
 /* EDMR */
 enum DMAC_M_BIT {
 	EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
-#ifdef CONFIG_CPU_SH7763
-	EDMR_SRST	= 0x03,
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+	EDMR_SRST	= 0x03, /* Receive/Send reset */
 	EMDR_DESC_R	= 0x30, /* Descriptor reserve size */
 	EDMR_EL		= 0x40, /* Litte endian */
-#elif defined(CONFIG_CPU_SH7757) ||defined (CONFIG_CPU_SH7724)
+#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7724)
 	EDMR_SRST	= 0x01,
 	EMDR_DESC_R	= 0x30, /* Descriptor reserve size */
 	EDMR_EL		= 0x40, /* Litte endian */
@@ -223,7 +262,7 @@ enum DMAC_M_BIT {
 
 /* EDTRR */
 enum DMAC_T_BIT {
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 	EDTRR_TRNS = 0x03,
 #else
 	EDTRR_TRNS = 0x01,
@@ -262,7 +301,8 @@ enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
 
 /* EESR */
 enum EESR_BIT {
-#ifndef CONFIG_CPU_SH7763
+
+#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
 	EESR_TWB  = 0x40000000,
 #else
 	EESR_TWB  = 0xC0000000,
@@ -272,14 +312,14 @@ enum EESR_BIT {
 #endif
 	EESR_TABT = 0x04000000,
 	EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
-#ifndef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
 	EESR_ADE  = 0x00800000,
 #endif
 	EESR_ECI  = 0x00400000,
 	EESR_FTC  = 0x00200000, EESR_TDE  = 0x00100000,
 	EESR_TFE  = 0x00080000, EESR_FRC  = 0x00040000,
 	EESR_RDE  = 0x00020000, EESR_RFE  = 0x00010000,
-#ifndef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7724) && !defined(CONFIG_CPU_SH7757)
 	EESR_CND  = 0x00000800,
 #endif
 	EESR_DLC  = 0x00000400,
@@ -291,7 +331,7 @@ enum EESR_BIT {
 };
 
 
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 # define TX_CHECK (EESR_TC1 | EESR_FTC)
 # define EESR_ERR_CHECK	(EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
 		| EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
@@ -352,7 +392,7 @@ enum FCFTR_BIT {
 /* Transfer descriptor bit */
 enum TD_STS_BIT {
 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757) \
-		|| defined(CONFIG_CPU_SH7724)
+		|| defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7734)
 	TD_TACT = 0x80000000,
 #else
 	TD_TACT = 0x7fffffff,
@@ -368,7 +408,7 @@ enum TD_STS_BIT {
 enum RECV_RST_BIT { RMCR_RST = 0x01, };
 /* ECMR */
 enum FELIC_MODE_BIT {
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 	ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000,
 	ECMR_RZPF = 0x00100000,
 #endif
@@ -383,7 +423,7 @@ enum FELIC_MODE_BIT {
 
 };
 
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 #define ECMR_CHG_DM	(ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \
 						ECMR_TXF | ECMR_MCT)
 #elif CONFIG_CPU_SH7757
@@ -396,14 +436,14 @@ enum FELIC_MODE_BIT {
 
 /* ECSR */
 enum ECSR_STATUS_BIT {
-#ifndef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
 	ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
 #endif
 	ECSR_LCHNG = 0x04,
 	ECSR_MPD = 0x02, ECSR_ICD = 0x01,
 };
 
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
 #else
 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
@@ -412,14 +452,20 @@ enum ECSR_STATUS_BIT {
 
 /* ECSIPR */
 enum ECSIPR_STATUS_MASK_BIT {
-#ifndef CONFIG_CPU_SH7763
-	ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
-#endif
+#if defined(CONFIG_CPU_SH7724)
+	ECSIPR_PSRTOIP = 0x10,
+	ECSIPR_LCHNGIP = 0x04,
+	ECSIPR_ICDIP = 0x01,
+#elif defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
+	ECSIPR_PSRTOIP = 0x10,
+	ECSIPR_PHYIP = 0x08,
 	ECSIPR_LCHNGIP = 0x04,
-	ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
+	ECSIPR_MPDIP = 0x02,
+	ECSIPR_ICDIP = 0x01,
+#endif
 };
 
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
 #else
 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
@@ -458,7 +504,7 @@ enum RPADIR_BIT {
 	RPADIR_PADR = 0x0003f,
 };
 
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 # define RPADIR_INIT (0x00)
 #else
 # define RPADIR_INIT (RPADIR_PADS1)
diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c
index 5cfef4dd7b..6dc7ad52e4 100644
--- a/drivers/net/smc91111.c
+++ b/drivers/net/smc91111.c
@@ -426,8 +426,7 @@ static void smc_halt(struct eth_device *dev)
  .	Enable the transmit interrupt, so I know if it failed
  .	Free the kernel data if I actually sent it.
 */
-static int smc_send(struct eth_device *dev, volatile void *packet,
-	int packet_length)
+static int smc_send(struct eth_device *dev, void *packet, int packet_length)
 {
 	byte packet_no;
 	byte *buf;
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index e34b4879d0..b2aed7e14a 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -161,8 +161,7 @@ static int smc911x_init(struct eth_device *dev, bd_t * bd)
 	return 0;
 }
 
-static int smc911x_send(struct eth_device *dev,
-			volatile void *packet, int length)
+static int smc911x_send(struct eth_device *dev, void *packet, int length)
 {
 	u32 *data = (u32*)packet;
 	u32 tmplen;
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 160bc0597d..3c1c8f0799 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -44,8 +44,7 @@ static RTXBD rtx __attribute__ ((aligned(8)));
 #error "rtx must be 64-bit aligned"
 #endif
 
-static int tsec_send(struct eth_device *dev,
-	volatile void *packet, int length);
+static int tsec_send(struct eth_device *dev, void *packet, int length);
 
 /* Default initializations for TSEC controllers. */
 
@@ -377,7 +376,7 @@ static void startup_tsec(struct eth_device *dev)
  * do the same.	 Presumably, this would be zero if there were no
  * errors
  */
-static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
+static int tsec_send(struct eth_device *dev, void *packet, int length)
 {
 	int i;
 	int result = 0;
diff --git a/drivers/net/tsi108_eth.c b/drivers/net/tsi108_eth.c
index f100ec1a50..b2c1be54fe 100644
--- a/drivers/net/tsi108_eth.c
+++ b/drivers/net/tsi108_eth.c
@@ -433,8 +433,7 @@ static struct dma_descriptor rx_descr_array[NUM_RX_DESC]
 static struct dma_descriptor *rx_descr_current;
 
 static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis);
-static int tsi108_eth_send (struct eth_device *dev,
-			   volatile void *packet, int length);
+static int tsi108_eth_send(struct eth_device *dev, void *packet, int length);
 static int tsi108_eth_recv (struct eth_device *dev);
 static void tsi108_eth_halt (struct eth_device *dev);
 static unsigned int read_phy (unsigned int base,
@@ -872,8 +871,7 @@ static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis)
 /*
  * send a packet
  */
-static int tsi108_eth_send (struct eth_device *dev,
-			   volatile void *packet, int length)
+static int tsi108_eth_send(struct eth_device *dev, void *packet, int length)
 {
 	unsigned long base;
 	int timeout;
@@ -948,7 +946,7 @@ static int tsi108_eth_recv (struct eth_device *dev)
 	unsigned long base;
 	int length = 0;
 	unsigned long status;
-	volatile uchar *buffer;
+	uchar *buffer;
 
 	base = dev->iobase;
 
@@ -983,10 +981,8 @@ static int tsi108_eth_recv (struct eth_device *dev)
 			    le32_to_cpu(rx_descr->vlan_byte_count) & 0xFFFF;
 
 			/*** process packet ***/
-			buffer =
-			    (volatile uchar
-			     *)(le32_to_cpu (rx_descr->start_addr0));
-			NetReceive (buffer, length);
+			buffer = (uchar *)(le32_to_cpu(rx_descr->start_addr0));
+			NetReceive(buffer, length);
 
 			invalidate_dcache_range ((unsigned long)buffer,
 						(unsigned long)buffer +
diff --git a/drivers/net/uli526x.c b/drivers/net/uli526x.c
index 5933bddce5..9648901925 100644
--- a/drivers/net/uli526x.c
+++ b/drivers/net/uli526x.c
@@ -168,8 +168,7 @@ static char buf_pool[TX_BUF_ALLOC * TX_DESC_CNT + 4];
 static int mode = 8;
 
 /* function declaration -- */
-static int uli526x_start_xmit(struct eth_device *dev,
-				volatile void *packet, int length);
+static int uli526x_start_xmit(struct eth_device *dev, void *packet, int length);
 static const struct ethtool_ops netdev_ethtool_ops;
 static u16 read_srom_word(long, int);
 static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
@@ -443,8 +442,7 @@ static void uli526x_init(struct eth_device *dev)
  *	Send a packet to media from the upper layer.
  */
 
-static int uli526x_start_xmit(struct eth_device *dev,
-				volatile void *packet, int length)
+static int uli526x_start_xmit(struct eth_device *dev, void *packet, int length)
 {
 	struct uli526x_board_info *db = dev->priv;
 	struct tx_desc *txptr;
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 82e254b529..7854a04cae 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -468,7 +468,7 @@ static int axiemac_init(struct eth_device *dev, bd_t * bis)
 	return 0;
 }
 
-static int axiemac_send(struct eth_device *dev, volatile void *ptr, int len)
+static int axiemac_send(struct eth_device *dev, void *ptr, int len)
 {
 	struct axidma_priv *priv = dev->priv;
 	u32 timeout;
diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 9791b9a534..d5bd737827 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -199,7 +199,7 @@ static int xemaclite_txbufferavailable(struct eth_device *dev)
 	return !(txpingbusy && txpongbusy);
 }
 
-static int emaclite_send(struct eth_device *dev, volatile void *ptr, int len)
+static int emaclite_send(struct eth_device *dev, void *ptr, int len)
 {
 	u32 reg;
 	u32 baseaddress;
@@ -240,7 +240,7 @@ static int emaclite_send(struct eth_device *dev, volatile void *ptr, int len)
 
 		debug("Send packet from 0x%x\n", baseaddress);
 		/* Write the frame to the buffer */
-		xemaclite_alignedwrite((void *) ptr, baseaddress, len);
+		xemaclite_alignedwrite(ptr, baseaddress, len);
 		out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
 			(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
 		reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
@@ -261,7 +261,7 @@ static int emaclite_send(struct eth_device *dev, volatile void *ptr, int len)
 				& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
 			debug("Send packet from 0x%x\n", baseaddress);
 			/* Write the frame to the buffer */
-			xemaclite_alignedwrite((void *) ptr, baseaddress, len);
+			xemaclite_alignedwrite(ptr, baseaddress, len);
 			out_be32 (baseaddress + XEL_TPLR_OFFSET, (len &
 				(XEL_TPLR_LENGTH_MASK_HI |
 					XEL_TPLR_LENGTH_MASK_LO)));
diff --git a/drivers/net/xilinx_ll_temac_fifo.c b/drivers/net/xilinx_ll_temac_fifo.c
index 3ff0f347ed..d7fd989cd4 100644
--- a/drivers/net/xilinx_ll_temac_fifo.c
+++ b/drivers/net/xilinx_ll_temac_fifo.c
@@ -102,8 +102,7 @@ int ll_temac_recv_fifo(struct eth_device *dev)
 	return 0;
 }
 
-int ll_temac_send_fifo(struct eth_device *dev, volatile void *packet,
-							int length)
+int ll_temac_send_fifo(struct eth_device *dev, void *packet, int length)
 {
 	int i;
 	u32 *buf = (u32 *)packet;
diff --git a/drivers/net/xilinx_ll_temac_fifo.h b/drivers/net/xilinx_ll_temac_fifo.h
index f0d6e6823c..e5b4be9e6c 100644
--- a/drivers/net/xilinx_ll_temac_fifo.h
+++ b/drivers/net/xilinx_ll_temac_fifo.h
@@ -116,7 +116,6 @@ int ll_temac_reset_fifo(struct eth_device *dev);
 int ll_temac_recv_fifo(struct eth_device *dev);
 
 /* send buffered data to FIFO */
-int ll_temac_send_fifo(struct eth_device *dev, volatile void *packet,
-							int length);
+int ll_temac_send_fifo(struct eth_device *dev, void *packet, int length);
 
 #endif /* _XILINX_LL_TEMAC_FIFO_ */
diff --git a/drivers/net/xilinx_ll_temac_sdma.c b/drivers/net/xilinx_ll_temac_sdma.c
index 621d100f29..8637a6b1fc 100644
--- a/drivers/net/xilinx_ll_temac_sdma.c
+++ b/drivers/net/xilinx_ll_temac_sdma.c
@@ -324,8 +324,7 @@ int ll_temac_recv_sdma(struct eth_device *dev)
 	return 0;
 }
 
-int ll_temac_send_sdma(struct eth_device *dev, volatile void *packet,
-							int length)
+int ll_temac_send_sdma(struct eth_device *dev, void *packet, int length)
 {
 	unsigned timeout = 50;	/* 1usec * 50 = 50usec */
 	struct cdmac_bd *tx_dp = &cdmac_bd.tx[tx_idx];
diff --git a/drivers/net/xilinx_ll_temac_sdma.h b/drivers/net/xilinx_ll_temac_sdma.h
index 51e258d7f5..db00a57a16 100644
--- a/drivers/net/xilinx_ll_temac_sdma.h
+++ b/drivers/net/xilinx_ll_temac_sdma.h
@@ -275,7 +275,6 @@ int ll_temac_reset_sdma(struct eth_device *dev);
 int ll_temac_recv_sdma(struct eth_device *dev);
 
 /* send buffered data to SDMA */
-int ll_temac_send_sdma(struct eth_device *dev, volatile void *packet,
-							int length);
+int ll_temac_send_sdma(struct eth_device *dev, void *packet, int length);
 
 #endif /* _XILINX_LL_TEMAC_SDMA_ */
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index ead00f8dae..6bf388cb7d 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -26,8 +26,10 @@ include $(TOPDIR)/config.mk
 LIB 	:= $(obj)libpower.o
 
 COBJS-$(CONFIG_FTPMU010_POWER)	+= ftpmu010.o
+COBJS-$(CONFIG_TPS6586X_POWER)	+= tps6586x.o
 COBJS-$(CONFIG_TWL4030_POWER)	+= twl4030.o
 COBJS-$(CONFIG_TWL6030_POWER)	+= twl6030.o
+COBJS-$(CONFIG_TWL6035_POWER)	+= twl6035.o
 
 COBJS	:= $(COBJS-y)
 SRCS 	:= $(COBJS:.o=.c)
diff --git a/drivers/power/tps6586x.c b/drivers/power/tps6586x.c
new file mode 100644
index 0000000000..f3f2ec6e58
--- /dev/null
+++ b/drivers/power/tps6586x.c
@@ -0,0 +1,280 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <tps6586x.h>
+#include <asm/io.h>
+#include <i2c.h>
+
+static int bus_num;		/* I2C bus we are on */
+#define I2C_ADDRESS		0x34	/* chip requires this address */
+static char inited;		/* 1 if we have been inited */
+
+enum {
+	/* Registers that we access */
+	SUPPLY_CONTROL1		= 0x20,
+	SUPPLY_CONTROL2,
+	SM1_VOLTAGE_V1		= 0x23,
+	SM1_VOLTAGE_V2,
+	SM0_VOLTAGE_V1		= 0x26,
+	SM0_VOLTAGE_V2,
+	PFM_MODE		= 0x47,
+
+	/* Bits in the supply control registers */
+	CTRL_SM1_RAMP		= 0x01,
+	CTRL_SM1_SUPPLY2	= 0x02,
+	CTRL_SM0_RAMP		= 0x04,
+	CTRL_SM0_SUPPLY2	= 0x08,
+};
+
+#define MAX_I2C_RETRY	3
+int tps6586x_read(int reg)
+{
+	int	i;
+	uchar	data;
+	int	retval = -1;
+	int	old_bus_num;
+
+	old_bus_num = i2c_get_bus_num();
+	i2c_set_bus_num(bus_num);
+
+	for (i = 0; i < MAX_I2C_RETRY; ++i) {
+		if (!i2c_read(I2C_ADDRESS, reg, 1, &data, 1)) {
+			retval = (int)data;
+			goto exit;
+		}
+
+		/* i2c access failed, retry */
+		udelay(100);
+	}
+
+exit:
+	i2c_set_bus_num(old_bus_num);
+	debug("pmu_read %x=%x\n", reg, retval);
+	if (retval < 0)
+		debug("%s: failed to read register %#x: %d\n", __func__, reg,
+		      retval);
+	return retval;
+}
+
+int tps6586x_write(int reg, uchar *data, uint len)
+{
+	int	i;
+	int	retval = -1;
+	int	old_bus_num;
+
+	old_bus_num = i2c_get_bus_num();
+	i2c_set_bus_num(bus_num);
+
+	for (i = 0; i < MAX_I2C_RETRY; ++i) {
+		if (!i2c_write(I2C_ADDRESS, reg, 1, data, len)) {
+			retval = 0;
+			goto exit;
+		}
+
+		/* i2c access failed, retry */
+		udelay(100);
+	}
+
+exit:
+	i2c_set_bus_num(old_bus_num);
+	debug("pmu_write %x=%x: ", reg, retval);
+	for (i = 0; i < len; i++)
+		debug("%x ", data[i]);
+	if (retval)
+		debug("%s: failed to write register %#x\n", __func__, reg);
+	return retval;
+}
+
+/*
+ * Get current voltage of SM0 and SM1
+ *
+ * @param sm0	Place to put SM0 voltage
+ * @param sm1	Place to put SM1 voltage
+ * @return 0 if ok, -1 on error
+ */
+static int read_voltages(int *sm0, int *sm1)
+{
+	int ctrl1, ctrl2;
+	int is_v2;
+
+	/*
+	 * Each vdd has two supply sources, ie, v1 and v2.
+	 * The supply control reg1 and reg2 determine the current selection.
+	 */
+	ctrl1 = tps6586x_read(SUPPLY_CONTROL1);
+	ctrl2 = tps6586x_read(SUPPLY_CONTROL2);
+	if (ctrl1 == -1 || ctrl2 == -1)
+		return -1;
+
+	/* Figure out whether V1 or V2 is selected */
+	is_v2 = (ctrl1 | ctrl2) & CTRL_SM0_SUPPLY2;
+	*sm0 = tps6586x_read(is_v2 ? SM0_VOLTAGE_V2 : SM0_VOLTAGE_V1);
+	*sm1 = tps6586x_read(is_v2 ? SM1_VOLTAGE_V2 : SM1_VOLTAGE_V1);
+	if (*sm0 == -1 || *sm1 == -1)
+		return -1;
+
+	return 0;
+}
+
+static int set_voltage(int reg, int data, int rate)
+{
+	uchar control_bit;
+	uchar buff[3];
+
+	control_bit = (reg == SM0_VOLTAGE_V1 ? CTRL_SM0_RAMP : CTRL_SM1_RAMP);
+
+	/*
+	 * Only one supply is needed in u-boot. set both v1 and v2 to
+	 * same value.
+	 *
+	 * When both v1 and v2 are set to same value, we just need to set
+	 * control1 reg to trigger the supply selection.
+	 */
+	buff[0] = buff[1] = (uchar)data;
+	buff[2] = rate;
+
+	/* write v1, v2 and rate, then trigger */
+	if (tps6586x_write(reg, buff, 3) ||
+	    tps6586x_write(SUPPLY_CONTROL1, &control_bit, 1))
+		return -1;
+
+	return 0;
+}
+
+static int calculate_next_voltage(int voltage, int target, int step)
+{
+	int diff = voltage < target ? step : -step;
+
+	if (abs(target - voltage) > step)
+		voltage += diff;
+	else
+		voltage = target;
+
+	return voltage;
+}
+
+int tps6586x_set_pwm_mode(int mask)
+{
+	uchar val;
+	int ret;
+
+	assert(inited);
+	ret = tps6586x_read(PFM_MODE);
+	if (ret != -1) {
+		val = (uchar)ret;
+		val |= mask;
+
+		ret = tps6586x_write(PFM_MODE, &val, 1);
+	}
+
+	if (ret == -1)
+		debug("%s: Failed to read/write PWM mode reg\n", __func__);
+
+	return ret;
+}
+
+int tps6586x_adjust_sm0_sm1(int sm0_target, int sm1_target, int step, int rate,
+			    int min_sm0_over_sm1)
+{
+	int sm0, sm1;
+	int bad;
+
+	assert(inited);
+
+	/* get current voltage settings */
+	if (read_voltages(&sm0, &sm1)) {
+		debug("%s: Cannot read voltage settings\n", __func__);
+		return -1;
+	}
+
+	/*
+	 * if vdd_core < vdd_cpu + rel
+	 *    skip
+	 *
+	 * This condition may happen when system reboots due to kernel crash.
+	 */
+	if (min_sm0_over_sm1 != -1 && sm0 < sm1 + min_sm0_over_sm1) {
+		debug("%s: SM0 is %d, SM1 is %d, but min_sm0_over_sm1 is %d\n",
+		      __func__, sm0, sm1, min_sm0_over_sm1);
+		return -1;
+	}
+
+	/*
+	 * Since vdd_core and vdd_cpu may both stand at either greater or less
+	 * than their nominal voltage, the adjustment may go either directions.
+	 *
+	 * Make sure vdd_core is always higher than vdd_cpu with certain margin.
+	 * So, find out which vdd to adjust first in each step.
+	 *
+	 * case 1: both sm0 and sm1 need to move up
+	 *              adjust sm0 before sm1
+	 *
+	 * case 2: both sm0 and sm1 need to move down
+	 *              adjust sm1 before sm0
+	 *
+	 * case 3: sm0 moves down and sm1 moves up
+	 *              adjusting either one first is fine.
+	 *
+	 * Adjust vdd_core and vdd_cpu one step at a time until they reach
+	 * their nominal values.
+	 */
+	bad = 0;
+	while (!bad && (sm0 != sm0_target || sm1 != sm1_target)) {
+		int adjust_sm0_late = 0; /* flag to adjust vdd_core later */
+
+		debug("%d-%d   %d-%d   ", sm0, sm0_target, sm1, sm1_target);
+
+		if (sm0 != sm0_target) {
+			/*
+			 * if case 1 and case 3, set new sm0 first.
+			 * otherwise, hold down until new sm1 is set.
+			 */
+			sm0 = calculate_next_voltage(sm0, sm0_target, step);
+			if (sm1 < sm1_target)
+				bad |= set_voltage(SM0_VOLTAGE_V1, sm0, rate);
+			else
+				adjust_sm0_late = 1;
+		}
+
+		if (sm1 != sm1_target) {
+			sm1 = calculate_next_voltage(sm1, sm1_target, step);
+			bad |= set_voltage(SM1_VOLTAGE_V1, sm1, rate);
+		}
+
+		if (adjust_sm0_late)
+			bad |= set_voltage(SM0_VOLTAGE_V1, sm0, rate);
+		debug("%d\n", adjust_sm0_late);
+	}
+	debug("%d-%d   %d-%d   done\n", sm0, sm0_target, sm1, sm1_target);
+
+	return bad ? -1 : 0;
+}
+
+int tps6586x_init(int bus)
+{
+	bus_num = bus;
+	inited = 1;
+
+	return 0;
+}
diff --git a/drivers/power/twl6035.c b/drivers/power/twl6035.c
new file mode 100644
index 0000000000..624c09e85d
--- /dev/null
+++ b/drivers/power/twl6035.c
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <twl6035.h>
+
+/* Functions to read and write from TWL6030 */
+int twl6035_i2c_write_u8(u8 chip_no, u8 val, u8 reg)
+{
+	return i2c_write(chip_no, reg, 1, &val, 1);
+}
+
+int twl6035_i2c_read_u8(u8 chip_no, u8 *val, u8 reg)
+{
+	return i2c_read(chip_no, reg, 1, val, 1);
+}
+
+/* To align with i2c mw/mr address, reg, val command syntax */
+static inline int palmas_write_u8(u8 chip_no, u8 reg, u8 val)
+{
+	return i2c_write(chip_no, reg, 1, &val, 1);
+}
+
+static inline int palmas_read_u8(u8 chip_no, u8 reg, u8 *val)
+{
+	return i2c_read(chip_no, reg, 1, val, 1);
+}
+
+void twl6035_init_settings(void)
+{
+	return;
+}
+
+void twl6035_mmc1_poweron_ldo(void)
+{
+	u8 val = 0;
+
+	/* set LDO9 TWL6035 to 3V */
+	val = 0x2b; /* (3 -.9)*28 +1 */
+	palmas_write_u8(0x48, LDO9_VOLTAGE, val);
+
+	/* TURN ON LDO9 */
+	val = LDO_ON | LDO_MODE_SLEEP | LDO_MODE_ACTIVE;
+	palmas_write_u8(0x48, LDO9_CTRL, val);
+	return;
+}
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index 3e46e3515f..216c8982be 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -1288,7 +1288,7 @@ static void uec_halt(struct eth_device* dev)
 	uec_stop(uec, COMM_DIR_RX_AND_TX);
 }
 
-static int uec_send(struct eth_device* dev, volatile void *buf, int len)
+static int uec_send(struct eth_device *dev, void *buf, int len)
 {
 	uec_private_t		*uec;
 	ucc_fast_private_t	*uccf;
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 616b85703b..6249cc2e21 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -29,6 +29,7 @@ COBJS-$(CONFIG_ALTERA_UART) += altera_uart.o
 COBJS-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
 COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o
 COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o
+COBJS-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
 COBJS-$(CONFIG_MCFUART) += mcfuart.o
 COBJS-$(CONFIG_NS9750_UART) += ns9750_serial.o
 COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
@@ -56,10 +57,21 @@ COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
 COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
 COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
 
+CFLAGS  += -I $(TOPDIR)/pdl/include
+CPPFLAGS  += -I $(TOPDIR)/pdl/include
+
 ifndef CONFIG_SPL_BUILD
 COBJS-$(CONFIG_USB_TTY) += usbtty.o
 endif
 
+ifdef CONFIG_RDA_PDL
+COBJS-$(CONFIG_RDA_USB_SERIAL) += usb-serial.o
+endif
+
+ifndef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_RDA_USB_SERIAL) += usb-serial.o
+endif
+
 COBJS	:= $(sort $(COBJS-y))
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/drivers/serial/lpc32xx_hsuart.c b/drivers/serial/lpc32xx_hsuart.c
new file mode 100644
index 0000000000..8ce3382d86
--- /dev/null
+++ b/drivers/serial/lpc32xx_hsuart.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/uart.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct hsuart_regs *hsuart = (struct hsuart_regs *)HS_UART_BASE;
+
+static void lpc32xx_hsuart_set_baudrate(void)
+{
+	u32 div;
+
+	/* UART rate = PERIPH_CLK / ((HSU_RATE + 1) x 14) */
+	div = (get_serial_clock() / 14 + gd->baudrate / 2) / gd->baudrate - 1;
+	if (div > 255)
+		div = 255;
+
+	writel(div, &hsuart->rate);
+}
+
+static int lpc32xx_hsuart_getc(void)
+{
+	while (!(readl(&hsuart->level) & HSUART_LEVEL_RX))
+		/* NOP */;
+
+	return readl(&hsuart->rx) & HSUART_RX_DATA;
+}
+
+static void lpc32xx_hsuart_putc(const char c)
+{
+	writel(c, &hsuart->tx);
+
+	/* Wait for character to be sent */
+	while (readl(&hsuart->level) & HSUART_LEVEL_TX)
+		/* NOP */;
+}
+
+static int lpc32xx_hsuart_tstc(void)
+{
+	if (readl(&hsuart->level) & HSUART_LEVEL_RX)
+		return 1;
+
+	return 0;
+}
+
+static void lpc32xx_hsuart_init(void)
+{
+	lpc32xx_hsuart_set_baudrate();
+
+	/* Disable hardware RTS and CTS flow control, set up RX and TX FIFO */
+	writel(HSUART_CTRL_TMO_16 | HSUART_CTRL_HSU_OFFSET(20) |
+	       HSUART_CTRL_HSU_RX_TRIG_32 | HSUART_CTRL_HSU_TX_TRIG_0,
+	       &hsuart->ctrl);
+}
+
+void serial_setbrg(void)
+{
+	return lpc32xx_hsuart_set_baudrate();
+}
+
+void serial_putc(const char c)
+{
+	lpc32xx_hsuart_putc(c);
+
+	/* If \n, also do \r */
+	if (c == '\n')
+		lpc32xx_hsuart_putc('\r');
+}
+
+int serial_getc(void)
+{
+	return lpc32xx_hsuart_getc();
+}
+
+void serial_puts(const char *s)
+{
+	while (*s)
+		serial_putc(*s++);
+}
+
+int serial_tstc(void)
+{
+	return lpc32xx_hsuart_tstc();
+}
+
+int serial_init(void)
+{
+	lpc32xx_hsuart_init();
+
+	return 0;
+}
diff --git a/drivers/serial/usb-serial.c b/drivers/serial/usb-serial.c
new file mode 100644
index 0000000000..4138971967
--- /dev/null
+++ b/drivers/serial/usb-serial.c
@@ -0,0 +1,871 @@
+/*
+ * (C) Copyright 2003
+ * Gerry Hamel, geh@ti.com, Texas Instruments
+ *
+ * (C) Copyright 2006
+ * Bryan O'Donoghue, bodonoghue@codehermit.ie
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
+ *
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/unaligned.h>
+#include <usb/usbserial.h>
+#include "usbser.h"
+#include "usb_cdc_acm.h"
+#include "usbdescriptors.h"
+
+//#define DEBUG
+
+#ifdef DEBUG
+#define DBG(fmt,args...)\
+	serial_printf("[%s] %s %d: "fmt, __FILE__,__FUNCTION__,__LINE__,##args)
+#else
+#define DBG(fmt,args...) do{}while(0)
+#endif
+
+#if 1
+#define ERR(fmt,args...)\
+	serial_printf("ERROR![%s] %s %d: "fmt, __FILE__,__FUNCTION__,\
+	__LINE__,##args)
+#else
+#define ERR(fmt,args...) do{}while(0)
+#endif
+
+/*
+ * Defines
+ */
+#define NUM_CONFIGS    1
+#ifdef CONFIG_USB_ACM_TWO_CHANS
+#define MAX_INTERFACES 4
+#define NUM_ENDPOINTS  6
+#define NUM_ACM_INTERFACES 4
+#else
+#define MAX_INTERFACES 2
+#define NUM_ENDPOINTS  3
+#define NUM_ACM_INTERFACES 2
+#endif
+
+/*
+ * Buffers to hold input and output data
+ */
+
+
+/*
+ * Instance variables
+ */
+static struct usb_device_instance device_instance[1];
+static struct usb_bus_instance bus_instance[1];
+static struct usb_configuration_instance config_instance[NUM_CONFIGS];
+static struct usb_interface_instance interface_instance[MAX_INTERFACES];
+static struct usb_alternate_instance alternate_instance[MAX_INTERFACES];
+/* one extra for control endpoint */
+static struct usb_endpoint_instance endpoint_instance[NUM_ENDPOINTS+1];
+
+/*
+ * Global flag
+ */
+int usbser_configured_flag = 0;
+
+
+/* Indicies, References */
+static unsigned short rx_endpoint[2] = {0, 0};
+static unsigned short tx_endpoint[2] = {0, 0};
+
+/* Standard USB Data Structures */
+static struct usb_interface_descriptor interface_descriptors[MAX_INTERFACES];
+static struct usb_endpoint_descriptor *ep_descriptor_ptrs[NUM_ENDPOINTS];
+static struct usb_configuration_descriptor	*configuration_descriptor = 0;
+static struct usb_device_descriptor device_descriptor = {
+	.bLength = sizeof(struct usb_device_descriptor),
+	.bDescriptorType =	USB_DT_DEVICE,
+	.bcdUSB =		cpu_to_le16(USB_BCD_VERSION),
+#ifdef CONFIG_USB_ACM_TWO_CHANS /* enable interface association */
+	.bDeviceClass =		0xEF,
+	.bDeviceSubClass =	0x02,
+	.bDeviceProtocol =	0x01,
+#else
+	.bDeviceClass = 	COMMUNICATIONS_DEVICE_CLASS,
+	.bDeviceSubClass =	0x00,
+	.bDeviceProtocol =	0x00,
+#endif
+	.bMaxPacketSize0 =	EP0_MAX_PACKET_SIZE,
+	.idVendor =		cpu_to_le16(CONFIG_USBD_VENDORID),
+#ifdef CONFIG_USB_ACM_TWO_CHANS
+	.idProduct =		cpu_to_le16(CONFIG_USBD_PRODUCTID_RDAACM),
+#else
+	.idProduct =		cpu_to_le16(CONFIG_USBD_PRODUCTID_CDCACM),
+#endif
+	.bcdDevice =		cpu_to_le16(USBTTY_BCD_DEVICE),
+	.iManufacturer =	0,
+	.iProduct =		0,
+	.iSerialNumber =	0,
+	.bNumConfigurations =	NUM_CONFIGS
+};
+
+
+#if defined(CONFIG_USBD_HS)
+static struct usb_qualifier_descriptor qualifier_descriptor = {
+	.bLength = sizeof(struct usb_qualifier_descriptor),
+	.bDescriptorType =	USB_DT_QUAL,
+	.bcdUSB =		cpu_to_le16(USB_BCD_VERSION),
+	.bDeviceClass =		COMMUNICATIONS_DEVICE_CLASS,
+	.bDeviceSubClass =	0x00,
+	.bDeviceProtocol =	0x00,
+	.bMaxPacketSize0 =	EP0_MAX_PACKET_SIZE,
+	.bNumConfigurations =	NUM_CONFIGS
+};
+#endif
+
+/*
+ * Static CDC ACM specific descriptors
+ */
+
+struct acm_config_desc {
+	struct usb_configuration_descriptor configuration_desc;
+
+#ifdef CONFIG_USB_ACM_TWO_CHANS
+	/* function 1 */
+	struct usb_function_descriptor	function_desc;
+#endif
+
+	/* Master Interface */
+	struct usb_interface_descriptor interface_desc;
+
+	struct usb_class_header_function_descriptor usb_class_header;
+	struct usb_class_call_management_descriptor usb_class_call_mgt;
+	struct usb_class_abstract_control_descriptor usb_class_acm;
+	struct usb_class_union_function_descriptor usb_class_union;
+	struct usb_endpoint_descriptor notification_endpoint;
+
+	/* Slave Interface */
+	struct usb_interface_descriptor data_class_interface;
+	struct usb_endpoint_descriptor data_endpoints[2];
+
+#ifdef CONFIG_USB_ACM_TWO_CHANS
+	/* function 2 */
+	struct usb_function_descriptor	function_desc2;
+
+	/* Master Interface 2 */
+	struct usb_interface_descriptor interface_desc2;
+
+	struct usb_class_header_function_descriptor usb_class_header2;
+	struct usb_class_call_management_descriptor usb_class_call_mgt2;
+	struct usb_class_abstract_control_descriptor usb_class_acm2;
+	struct usb_class_union_function_descriptor usb_class_union2;
+	struct usb_endpoint_descriptor notification_endpoint2;
+
+	/* Slave Interface 2 */
+	struct usb_interface_descriptor data_class_interface2;
+	struct usb_endpoint_descriptor data_endpoints2[2];
+#endif
+} __attribute__((packed));
+
+static struct acm_config_desc acm_configuration_descriptors[NUM_CONFIGS] = {
+	{
+		.configuration_desc ={
+			.bLength =
+				sizeof(struct usb_configuration_descriptor),
+			.bDescriptorType = USB_DT_CONFIG,
+			.wTotalLength =
+				cpu_to_le16(sizeof(struct acm_config_desc)),
+			.bNumInterfaces = NUM_ACM_INTERFACES,
+			.bConfigurationValue = 1,
+			.iConfiguration = 0,
+			.bmAttributes =
+				BMATTRIBUTE_SELF_POWERED|BMATTRIBUTE_RESERVED,
+			.bMaxPower = USBTTY_MAXPOWER
+		},
+#ifdef CONFIG_USB_ACM_TWO_CHANS
+		/* function 1 */
+		.function_desc = {
+			.bLength = sizeof(struct usb_function_descriptor),
+			.bDescriptorType = 0x0B,
+			.bFirstInterface = 0,
+			.bInterfaceCount = 2,
+			.bFunctionClass = COMMUNICATIONS_INTERFACE_CLASS_CONTROL,
+			.bFunctionSubClass = COMMUNICATIONS_ACM_SUBCLASS,
+			.bFunctionProtocol = COMMUNICATIONS_V25TER_PROTOCOL,
+			.iFunction = 0,
+		},
+#endif
+		/* Interface 1 */
+		.interface_desc = {
+			.bLength  = sizeof(struct usb_interface_descriptor),
+			.bDescriptorType = USB_DT_INTERFACE,
+			.bInterfaceNumber = 0,
+			.bAlternateSetting = 0,
+			.bNumEndpoints = 0x01,
+			.bInterfaceClass =
+				COMMUNICATIONS_INTERFACE_CLASS_CONTROL,
+			.bInterfaceSubClass = COMMUNICATIONS_ACM_SUBCLASS,
+			.bInterfaceProtocol = COMMUNICATIONS_V25TER_PROTOCOL,
+			.iInterface = 0,
+		},
+		.usb_class_header = {
+			.bFunctionLength	=
+				sizeof(struct usb_class_header_function_descriptor),
+			.bDescriptorType	= CS_INTERFACE,
+			.bDescriptorSubtype	= USB_ST_HEADER,
+			.bcdCDC	= cpu_to_le16(110),
+		},
+		.usb_class_call_mgt = {
+			.bFunctionLength	=
+				sizeof(struct usb_class_call_management_descriptor),
+			.bDescriptorType	= CS_INTERFACE,
+			.bDescriptorSubtype	= USB_ST_CMF,
+			.bmCapabilities		= 0x00,
+			.bDataInterface		= 0x01,
+		},
+		.usb_class_acm = {
+			.bFunctionLength	=
+				sizeof(struct usb_class_abstract_control_descriptor),
+			.bDescriptorType	= CS_INTERFACE,
+			.bDescriptorSubtype	= USB_ST_ACMF,
+			.bmCapabilities		= 0x00,
+		},
+		.usb_class_union = {
+			.bFunctionLength	=
+				sizeof(struct usb_class_union_function_descriptor),
+			.bDescriptorType	= CS_INTERFACE,
+			.bDescriptorSubtype	= USB_ST_UF,
+			.bMasterInterface	= 0x00,
+			.bSlaveInterface0	= 0x01,
+		},
+		.notification_endpoint = {
+			.bLength =
+				sizeof(struct usb_endpoint_descriptor),
+			.bDescriptorType	= USB_DT_ENDPOINT,
+			.bEndpointAddress	= UDC_INT_ENDPOINT | USB_DIR_IN,
+			.bmAttributes		= USB_ENDPOINT_XFER_INT,
+			.wMaxPacketSize
+				= cpu_to_le16(CONFIG_USBD_SERIAL_INT_PKTSIZE),
+			.bInterval		= 0xb,
+		},
+
+		/* Interface 2 */
+		.data_class_interface = {
+			.bLength		=
+				sizeof(struct usb_interface_descriptor),
+			.bDescriptorType	= USB_DT_INTERFACE,
+			.bInterfaceNumber	= 0x01,
+			.bAlternateSetting	= 0x00,
+			.bNumEndpoints		= 0x02,
+			.bInterfaceClass	=
+				COMMUNICATIONS_INTERFACE_CLASS_DATA,
+			.bInterfaceSubClass	= DATA_INTERFACE_SUBCLASS_NONE,
+			.bInterfaceProtocol	= DATA_INTERFACE_PROTOCOL_NONE,
+			.iInterface		= 0,
+		},
+		.data_endpoints = {
+			{
+				.bLength		=
+					sizeof(struct usb_endpoint_descriptor),
+				.bDescriptorType	= USB_DT_ENDPOINT,
+				.bEndpointAddress	= UDC_OUT_ENDPOINT | USB_DIR_OUT,
+				.bmAttributes		=
+					USB_ENDPOINT_XFER_BULK,
+				.wMaxPacketSize		=
+					cpu_to_le16(CONFIG_USBD_SERIAL_BULK_PKTSIZE),
+				.bInterval		= 0xFF,
+			},
+			{
+				.bLength		=
+					sizeof(struct usb_endpoint_descriptor),
+				.bDescriptorType	= USB_DT_ENDPOINT,
+				.bEndpointAddress	= UDC_IN_ENDPOINT | USB_DIR_IN,
+				.bmAttributes		=
+					USB_ENDPOINT_XFER_BULK,
+				.wMaxPacketSize		=
+					cpu_to_le16(CONFIG_USBD_SERIAL_BULK_PKTSIZE),
+				.bInterval		= 0xFF,
+			},
+		},
+#ifdef CONFIG_USB_ACM_TWO_CHANS
+		/* function 2 */
+		.function_desc2 = {
+			.bLength = sizeof(struct usb_function_descriptor),
+			.bDescriptorType = 0x0B,
+			.bFirstInterface = 2,
+			.bInterfaceCount = 2,
+			.bFunctionClass = COMMUNICATIONS_INTERFACE_CLASS_CONTROL,
+			.bFunctionSubClass = COMMUNICATIONS_ACM_SUBCLASS,
+			.bFunctionProtocol = COMMUNICATIONS_V25TER_PROTOCOL,
+			.iFunction = 0,
+		},
+		/* Interface 3 */
+		.interface_desc2 = {
+			.bLength  = sizeof(struct usb_interface_descriptor),
+			.bDescriptorType = USB_DT_INTERFACE,
+			.bInterfaceNumber = 0x02,
+			.bAlternateSetting = 0,
+			.bNumEndpoints = 0x01,
+			.bInterfaceClass =
+				COMMUNICATIONS_INTERFACE_CLASS_CONTROL,
+			.bInterfaceSubClass = COMMUNICATIONS_ACM_SUBCLASS,
+			.bInterfaceProtocol = COMMUNICATIONS_V25TER_PROTOCOL,
+			.iInterface = 0,
+		},
+		.usb_class_header2 = {
+			.bFunctionLength	=
+				sizeof(struct usb_class_header_function_descriptor),
+			.bDescriptorType	= CS_INTERFACE,
+			.bDescriptorSubtype	= USB_ST_HEADER,
+			.bcdCDC	= cpu_to_le16(110),
+		},
+		.usb_class_call_mgt2 = {
+			.bFunctionLength	=
+				sizeof(struct usb_class_call_management_descriptor),
+			.bDescriptorType	= CS_INTERFACE,
+			.bDescriptorSubtype	= USB_ST_CMF,
+			.bmCapabilities		= 0x00,
+			.bDataInterface		= 0x03,
+		},
+		.usb_class_acm2 = {
+			.bFunctionLength	=
+				sizeof(struct usb_class_abstract_control_descriptor),
+			.bDescriptorType	= CS_INTERFACE,
+			.bDescriptorSubtype	= USB_ST_ACMF,
+			.bmCapabilities		= 0x00,
+		},
+		.usb_class_union2 = {
+			.bFunctionLength	=
+				sizeof(struct usb_class_union_function_descriptor),
+			.bDescriptorType	= CS_INTERFACE,
+			.bDescriptorSubtype	= USB_ST_UF,
+			.bMasterInterface	= 0x02,
+			.bSlaveInterface0	= 0x03,
+		},
+		.notification_endpoint2 = {
+			.bLength =
+				sizeof(struct usb_endpoint_descriptor),
+			.bDescriptorType	= USB_DT_ENDPOINT,
+			.bEndpointAddress	= UDC_INT_ENDPOINT2 | USB_DIR_IN,
+			.bmAttributes		= USB_ENDPOINT_XFER_INT,
+			.wMaxPacketSize
+				= cpu_to_le16(CONFIG_USBD_SERIAL_INT_PKTSIZE),
+			.bInterval		= 0xb,
+		},
+
+		/* Interface 4 */
+		.data_class_interface2 = {
+			.bLength		=
+				sizeof(struct usb_interface_descriptor),
+			.bDescriptorType	= USB_DT_INTERFACE,
+			.bInterfaceNumber	= 0x03,
+			.bAlternateSetting	= 0x00,
+			.bNumEndpoints		= 0x02,
+			.bInterfaceClass	=
+				COMMUNICATIONS_INTERFACE_CLASS_DATA,
+			.bInterfaceSubClass	= DATA_INTERFACE_SUBCLASS_NONE,
+			.bInterfaceProtocol	= DATA_INTERFACE_PROTOCOL_NONE,
+			.iInterface		= 0,
+		},
+		.data_endpoints2 = {
+			{
+				.bLength		=
+					sizeof(struct usb_endpoint_descriptor),
+				.bDescriptorType	= USB_DT_ENDPOINT,
+				.bEndpointAddress	= UDC_OUT_ENDPOINT2 | USB_DIR_OUT,
+				.bmAttributes		=
+					USB_ENDPOINT_XFER_BULK,
+				.wMaxPacketSize		=
+					cpu_to_le16(CONFIG_USBD_SERIAL_BULK_PKTSIZE),
+				.bInterval		= 0xFF,
+			},
+			{
+				.bLength		=
+					sizeof(struct usb_endpoint_descriptor),
+				.bDescriptorType	= USB_DT_ENDPOINT,
+				.bEndpointAddress	= UDC_IN_ENDPOINT2 | USB_DIR_IN,
+				.bmAttributes		=
+					USB_ENDPOINT_XFER_BULK,
+				.wMaxPacketSize		=
+					cpu_to_le16(CONFIG_USBD_SERIAL_BULK_PKTSIZE),
+				.bInterval		= 0xFF,
+			},
+		},
+#endif //CONFIG_USB_ACM_TWO_CHANS
+	},
+};
+
+static struct rs232_emu rs232_desc={
+		.dter		=	115200,
+		.stop_bits	=	0x00,
+		.parity		=	0x00,
+		.data_bits	=	0x08
+};
+
+/*
+ * Static Function Prototypes
+ */
+
+static void usbser_init_instances (void);
+static void usbser_init_endpoints (void);
+static void usbser_init_terminal_type(void);
+static void usbser_event_handler (struct usb_device_instance *device,
+				usb_device_event_t event, int data);
+static int usbser_cdc_setup(struct usb_device_request *request,
+				struct urb *urb);
+static int usbser_configured (void);
+
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+
+int usbser_tstc (int chan)
+{
+	udc_irq();
+
+	return udc_chars_in_rxfifo(rx_endpoint[chan]);
+}
+
+/*
+ * Read a single byte from the usb client port. Returns 1 on success, 0
+ * otherwise. When the function is succesfull, the character read is
+ * written into its argument c.
+ */
+int usbser_getc (int chan)
+{
+	unsigned char c = 0;
+
+	usbser_read(chan, &c, 1);
+	return c;
+}
+
+/*
+ * Output a single byte to the usb client port.
+ */
+void usbser_putc (int chan, const char c)
+{
+	usbser_write(chan, (u8 *)&c, 1);
+}
+
+int usbser_read(int chan, unsigned char *_buf, unsigned int len)
+{
+	int count = 0, i;
+	struct usb_endpoint_instance *ep_out = NULL;
+	struct urb *urb = NULL;
+	unsigned char *buf = _buf;
+	unsigned short ep = rx_endpoint[chan];
+	u32 rx_avail;
+
+	for(i = 1; i <= NUM_ENDPOINTS; i++) {
+		if(endpoint_instance[i].endpoint_address == (ep | USB_DIR_OUT))
+			ep_out = &endpoint_instance[i];
+	}
+	if(!ep_out)
+		return -1;
+	urb = ep_out->rcv_urb;
+
+	DBG(" buf len: %d\n", len);
+
+	rx_avail = udc_chars_in_rxfifo(ep);
+	if (rx_avail > 0) {
+		if (len <= rx_avail) {
+			usbd_setup_urb(urb, buf, len, 0);
+			udc_irq();
+			if(!urb->actual_length)
+				poll_rx_ep(ep);
+			usbd_free_urb(urb);
+			return len;
+		} else {
+			//first flush all chars in buffer
+			usbd_setup_urb(urb, buf, rx_avail, 0);
+			udc_irq();
+			if(!urb->actual_length)
+				poll_rx_ep(ep);
+			buf += rx_avail;
+			len -= rx_avail;
+			count += rx_avail;
+			usbd_free_urb(urb);
+		}
+	}
+	//now get remain data...
+	while (len > 0) {
+		int xfer;
+		int dma = 0;
+		int maxPktSize = ep_out->rcv_packetSize;
+
+		xfer = (len > maxPktSize) ? maxPktSize : len;
+		if (xfer == maxPktSize)
+			dma = 1;
+		usbd_setup_urb(urb, buf, xfer, dma);
+		udc_irq();
+		if(!urb->actual_length)
+			poll_rx_ep(ep);
+
+		DBG("urb actual_len :%d\n", urb->actual_length);
+		if (urb->actual_length) {
+			buf += urb->actual_length;
+			len -= urb->actual_length;
+			count += urb->actual_length;
+			usbd_free_urb(urb);
+		}
+	}
+
+	DBG("read : %d\n", count);
+	return count;
+}
+
+int usbser_write(int chan, const unsigned char *_buf, unsigned int len)
+{
+	int i;
+	struct usb_endpoint_instance *ep_in = NULL;
+	struct urb *current_urb = NULL;
+	unsigned char *buf = (unsigned char *)_buf;
+	int count = 0;
+	unsigned short ep = tx_endpoint[chan];
+#ifdef CONFIG_USB_ACM_TWO_CHANS
+	static int acm_ch1_opened = 1;
+	if(chan == USB_ACM_CHAN_1 && !acm_ch1_opened)
+		return -1;
+#endif
+
+	for(i = 1; i <= NUM_ENDPOINTS; i++) {
+		if(endpoint_instance[i].endpoint_address == (ep | USB_DIR_IN))
+			ep_in = &endpoint_instance[i];
+	}
+	if(!ep_in)
+		return -1;
+
+	if (!usbser_configured ()) {
+		return 0;
+	}
+	current_urb = ep_in->tx_urb;
+
+	while(len > 0) {
+		int xfer;
+		int maxPktSize = ep_in->rcv_packetSize;
+
+		xfer = (len > maxPktSize) ? maxPktSize : len;
+
+		current_urb->buffer = buf;
+		current_urb->actual_length = xfer;
+
+		if(udc_endpoint_write (ep_in))
+			goto oops;
+		count += xfer;
+		len -= xfer;
+		buf += xfer;
+	}
+
+	DBG("after write urb actual_len :%d count %d\n",
+		current_urb->actual_length, count);
+	return count;
+
+oops:
+	serial_puts("usb write error\n");
+#ifdef CONFIG_USB_ACM_TWO_CHANS
+	if(chan == USB_ACM_CHAN_1)
+		acm_ch1_opened = 0;
+#endif
+	return -1;
+}
+
+int drv_usbser_init (void)
+{
+	static int usb_init_flag = 0;
+
+	if (usb_init_flag)
+		return 0;
+	usb_init_flag = 1;
+
+	/* Decide on which type of UDC device to be.
+	 */
+	usbser_init_terminal_type();
+
+	/* Now, set up USB controller and infrastructure */
+	if (udc_is_initialized()) {
+		printf("UDC software initializing...\n");
+		udc_soft_init ();		/* Basic USB initialization */
+	} else {
+		printf("UDC hardware initializing...\n");
+		udc_init ();
+	}
+
+	usbser_init_instances ();
+	usbser_init_endpoints ();
+
+	if (!udc_is_initialized()) {
+		udc_startup_events (device_instance);/* Enable dev, init udc pointers */
+		udc_connect ();		/* Enable pullup for host detection */
+	} else {
+		udc_hot_startup(device_instance);
+	}
+
+	return 0;
+}
+
+
+#define init_wMaxPacketSize(x)	le16_to_cpu(get_unaligned(\
+			&ep_descriptor_ptrs[(x) - 1]->wMaxPacketSize));
+
+#define init_write_wMaxPacketSize(val, x)	 (put_unaligned(le16_to_cpu(val),\
+			&ep_descriptor_ptrs[(x) - 1]->wMaxPacketSize));
+
+static struct urb urb_pool[NUM_ENDPOINTS];
+static u8 int_ep_buffer[URB_BUF_SIZE] __attribute__((__aligned__(4)));
+
+static int endpoint_is_int(struct usb_endpoint_instance *instance)
+{
+	if (!instance)
+		return 0;
+
+	if (instance->tx_attributes == USB_ENDPOINT_XFER_INT)
+		return 1;
+	else
+		return 0;
+}
+static void usbser_init_instances (void)
+{
+	int i;
+
+	/* initialize device instance */
+	memset (device_instance, 0, sizeof (struct usb_device_instance));
+	if (!udc_is_initialized())
+		device_instance->device_state = STATE_INIT;
+	else
+		device_instance->device_state = STATE_CONFIGURED;
+	device_instance->device_descriptor = &device_descriptor;
+#if defined(CONFIG_USBD_HS)
+	device_instance->qualifier_descriptor = &qualifier_descriptor;
+#endif
+	device_instance->event = usbser_event_handler;
+	device_instance->cdc_recv_setup = usbser_cdc_setup;
+	device_instance->bus = bus_instance;
+	device_instance->configurations = NUM_CONFIGS;
+	device_instance->configuration_instance_array = config_instance;
+
+	/* initialize bus instance */
+	memset (bus_instance, 0, sizeof (struct usb_bus_instance));
+	bus_instance->device = device_instance;
+	bus_instance->endpoint_array = endpoint_instance;
+	bus_instance->max_endpoints = 1;
+	bus_instance->maxpacketsize = 64;
+
+	/* configuration instance */
+	memset (config_instance, 0,
+		sizeof (struct usb_configuration_instance));
+	config_instance->interfaces = NUM_ACM_INTERFACES;
+	config_instance->configuration_descriptor = configuration_descriptor;
+	config_instance->interface_instance_array = interface_instance;
+
+	/* interface instance */
+	memset (interface_instance, 0,
+		sizeof (struct usb_interface_instance));
+	interface_instance->alternates = 1;
+	interface_instance->alternates_instance_array = alternate_instance;
+
+	/* alternates instance */
+	memset (alternate_instance, 0,
+		sizeof (struct usb_alternate_instance));
+	alternate_instance->interface_descriptor = interface_descriptors;
+	alternate_instance->endpoints = NUM_ENDPOINTS;
+	alternate_instance->endpoints_descriptor_array = ep_descriptor_ptrs;
+
+	/* endpoint instances */
+	memset (&endpoint_instance[0], 0,
+		sizeof (struct usb_endpoint_instance));
+	endpoint_instance[0].endpoint_address = 0;
+	endpoint_instance[0].rcv_packetSize = EP0_MAX_PACKET_SIZE;
+	endpoint_instance[0].rcv_attributes = USB_ENDPOINT_XFER_CONTROL;
+	endpoint_instance[0].tx_packetSize = EP0_MAX_PACKET_SIZE;
+	endpoint_instance[0].tx_attributes = USB_ENDPOINT_XFER_CONTROL;
+	udc_setup_ep (device_instance, 0, &endpoint_instance[0]);
+
+	for (i = 1; i <= NUM_ENDPOINTS; i++) {
+		memset (&endpoint_instance[i], 0,
+			sizeof (struct usb_endpoint_instance));
+
+		endpoint_instance[i].endpoint_address =
+			ep_descriptor_ptrs[i - 1]->bEndpointAddress;
+
+		endpoint_instance[i].rcv_attributes =
+			ep_descriptor_ptrs[i - 1]->bmAttributes;
+
+		endpoint_instance[i].rcv_packetSize = init_wMaxPacketSize(i);
+
+		endpoint_instance[i].tx_attributes =
+			ep_descriptor_ptrs[i - 1]->bmAttributes;
+
+		endpoint_instance[i].tx_packetSize = init_wMaxPacketSize(i);
+
+
+		urb_link_init (&endpoint_instance[i].rcv);
+		urb_link_init (&endpoint_instance[i].rdy);
+		urb_link_init (&endpoint_instance[i].tx);
+		urb_link_init (&endpoint_instance[i].done);
+
+		if (endpoint_instance[i].endpoint_address & USB_DIR_IN) {
+			endpoint_instance[i].tx_urb = &urb_pool[i - 1];
+			/* function only has one interrupt endpoint */
+			if (endpoint_is_int(&endpoint_instance[i]))
+				usbd_init_urb (endpoint_instance[i].tx_urb, device_instance,
+					&endpoint_instance[i], int_ep_buffer, URB_BUF_SIZE);
+			else // bulk in&out re-use buffer with application driver
+				usbd_init_urb (endpoint_instance[i].tx_urb, device_instance,
+					&endpoint_instance[i], NULL, 0);
+		} else {
+			endpoint_instance[i].rcv_urb = &urb_pool[i - 1];
+			usbd_init_urb (endpoint_instance[i].rcv_urb, device_instance,
+					&endpoint_instance[i], NULL, 0);
+		}
+	}
+}
+
+static void usbser_init_endpoints (void)
+{
+	int i;
+
+	bus_instance->max_endpoints = NUM_ENDPOINTS + 1;
+
+	for (i = 0; i < NUM_ENDPOINTS; i++) {
+		if (((ep_descriptor_ptrs[i]->bmAttributes &
+			USB_ENDPOINT_XFERTYPE_MASK) ==
+			USB_ENDPOINT_XFER_BULK)
+			&& is_usbd_high_speed()) {
+
+			init_write_wMaxPacketSize(CONFIG_USBD_SERIAL_BULK_HS_PKTSIZE, i+1);
+		}
+
+		endpoint_instance[i + 1].tx_packetSize =  init_wMaxPacketSize(i + 1);
+		endpoint_instance[i + 1].rcv_packetSize =  init_wMaxPacketSize(i + 1);
+
+		udc_setup_ep (device_instance, i + 1, &endpoint_instance[i+1]);
+	}
+}
+
+/* usbser_init_terminal_type
+ *
+ * Do some late binding for our device type.
+ */
+static void usbser_init_terminal_type(void)
+{
+	/* CDC ACM */
+	/* Assign endpoint descriptors */
+	ep_descriptor_ptrs[0] =
+		&acm_configuration_descriptors[0].notification_endpoint;
+	ep_descriptor_ptrs[1] =
+		&acm_configuration_descriptors[0].data_endpoints[0];
+	ep_descriptor_ptrs[2] =
+		&acm_configuration_descriptors[0].data_endpoints[1];
+#ifdef CONFIG_USB_ACM_TWO_CHANS
+	ep_descriptor_ptrs[3] =
+		&acm_configuration_descriptors[0].notification_endpoint2;
+	ep_descriptor_ptrs[4] =
+		&acm_configuration_descriptors[0].data_endpoints2[0];
+	ep_descriptor_ptrs[5] =
+		&acm_configuration_descriptors[0].data_endpoints2[1];
+#endif
+
+#if defined(CONFIG_USBD_HS)
+	qualifier_descriptor.bDeviceClass =
+		COMMUNICATIONS_DEVICE_CLASS;
+#endif
+	/* Assign endpoint indices */
+	tx_endpoint[0] = UDC_IN_ENDPOINT;
+	rx_endpoint[0] = UDC_OUT_ENDPOINT;
+#ifdef CONFIG_USB_ACM_TWO_CHANS
+	tx_endpoint[1] = UDC_IN_ENDPOINT2;
+	rx_endpoint[1] = UDC_OUT_ENDPOINT2;
+#endif
+
+	/* Configuration Descriptor */
+	configuration_descriptor =
+		(struct usb_configuration_descriptor*)
+		&acm_configuration_descriptors;
+
+}
+
+static int usbser_configured (void)
+{
+	return usbser_configured_flag;
+}
+
+/******************************************************************************/
+
+static void usbser_event_handler (struct usb_device_instance *device,
+				  usb_device_event_t event, int data)
+{
+	switch (event) {
+	case DEVICE_RESET:
+	case DEVICE_BUS_INACTIVE:
+		usbser_configured_flag = 0;
+		break;
+	case DEVICE_CONFIGURED:
+		usbser_configured_flag = 1;
+		break;
+
+	case DEVICE_ADDRESS_ASSIGNED:
+		usbser_init_endpoints ();
+
+	default:
+		break;
+	}
+}
+
+/******************************************************************************/
+
+int usbser_cdc_setup(struct usb_device_request *request, struct urb *urb)
+{
+	switch (request->bRequest){
+
+		case ACM_SET_CONTROL_LINE_STATE:	/* Implies DTE ready */
+			break;
+		case ACM_SEND_ENCAPSULATED_COMMAND :	/* Required */
+			break;
+		case ACM_SET_LINE_ENCODING :		/* DTE stop/parity bits
+							 * per character */
+			break;
+		case ACM_GET_ENCAPSULATED_RESPONSE :	/* request response */
+			break;
+		case ACM_GET_LINE_ENCODING :		/* request DTE rate,
+							 * stop/parity bits */
+			memcpy (urb->buffer , &rs232_desc, sizeof(rs232_desc));
+			urb->actual_length = sizeof(rs232_desc);
+
+			break;
+		default:
+			return 1;
+	}
+	return 0;
+}
+
+/******************************************************************************/
+#include <command.h>
+int usbser_test(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	char c;
+
+	drv_usbser_init();
+	serial_puts("usb tty test\n");
+	while (1) {
+		c = usbser_getc(USB_ACM_CHAN_0);
+		serial_putc(c);
+		//usbser_puts("from usb ");
+		usbser_putc(USB_ACM_CHAN_0, c);
+		//usbser_puts("\n");
+		if (c == 'Q' || c == 'q')
+			break;
+	}
+	return 0;
+}
+
+U_BOOT_CMD(usbser_test, 1, 1, usbser_test,
+           "rda usbserial test", "loopback everything to user");
diff --git a/drivers/serial/usbser.h b/drivers/serial/usbser.h
new file mode 100644
index 0000000000..7c244d3641
--- /dev/null
+++ b/drivers/serial/usbser.h
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2003
+ * Gerry Hamel, geh@ti.com, Texas Instruments
+ *
+ * (C) Copyright 2006
+ * Bryan O'Donoghue, bodonoghue@codehermit.ie, CodeHermit
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
+ *
+ */
+
+#ifndef __USB_SER_H__
+#define __USB_SER_H__
+
+#include <usbdevice.h>
+#include <usb/musb_udc.h>
+
+
+
+/* If no VendorID/ProductID is defined in config.h, pretend to be Linux
+ * DO NOT Reuse this Vendor/Product setup with protocol incompatible devices */
+#ifndef CONFIG_USBD_VENDORID
+#define CONFIG_USBD_VENDORID		0x0525	/* Linux/NetChip */
+#endif
+#ifndef CONFIG_USBD_PRODUCTID_GSERIAL
+#define CONFIG_USBD_PRODUCTID_GSERIAL	0xa4a6	/* gserial */
+#endif
+#ifndef CONFIG_USBD_PRODUCTID_CDCACM
+#define CONFIG_USBD_PRODUCTID_CDCACM	0xa4a7	/* CDC ACM */
+#endif
+#ifndef CONFIG_USBD_PRODUCTID_RDAACM
+#define CONFIG_USBD_PRODUCTID_RDAACM	0xa4a9	/* for two acm channels */
+#endif
+
+#define CONFIG_USBD_SERIAL_OUT_ENDPOINT UDC_OUT_ENDPOINT
+#define CONFIG_USBD_SERIAL_OUT_PKTSIZE	UDC_OUT_PACKET_SIZE
+#define CONFIG_USBD_SERIAL_IN_ENDPOINT	UDC_IN_ENDPOINT
+#define CONFIG_USBD_SERIAL_IN_PKTSIZE	UDC_IN_PACKET_SIZE
+#define CONFIG_USBD_SERIAL_INT_ENDPOINT UDC_INT_ENDPOINT
+#define CONFIG_USBD_SERIAL_INT_PKTSIZE	UDC_INT_PACKET_SIZE
+#define CONFIG_USBD_SERIAL_BULK_PKTSIZE	UDC_BULK_PACKET_SIZE
+
+#if defined(CONFIG_USBD_HS)
+#define CONFIG_USBD_SERIAL_BULK_HS_PKTSIZE	UDC_BULK_HS_PACKET_SIZE
+#endif
+
+#define USBTTY_DEVICE_CLASS	COMMUNICATIONS_DEVICE_CLASS
+
+#define USBTTY_BCD_DEVICE	0x00
+#define USBTTY_MAXPOWER		0x00
+
+#endif
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index 4e6f14ee07..7859536a67 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -34,6 +34,8 @@
 
 #define	MXS_SPI_MAX_TIMEOUT	1000000
 #define	MXS_SPI_PORT_OFFSET	0x2000
+#define MXS_SSP_CHIPSELECT_MASK		0x00300000
+#define MXS_SSP_CHIPSELECT_SHIFT	20
 
 struct mxs_spi_slave {
 	struct spi_slave	slave;
@@ -51,14 +53,25 @@ void spi_init(void)
 {
 }
 
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	/* MXS SPI: 4 ports and 3 chip selects maximum */
+	if (bus > 3 || cs > 2)
+		return 0;
+	else
+		return 1;
+}
+
 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 				  unsigned int max_hz, unsigned int mode)
 {
 	struct mxs_spi_slave *mxs_slave;
 	uint32_t addr;
+	struct mx28_ssp_regs *ssp_regs;
+	int reg;
 
-	if (bus > 3) {
-		printf("MXS SPI: Max bus number is 3\n");
+	if (!spi_cs_is_valid(bus, cs)) {
+		printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
 		return NULL;
 	}
 
@@ -73,7 +86,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	mxs_slave->max_khz = max_hz / 1000;
 	mxs_slave->mode = mode;
 	mxs_slave->regs = (struct mx28_ssp_regs *)addr;
+	ssp_regs = mxs_slave->regs;
+
+	reg = readl(&ssp_regs->hw_ssp_ctrl0);
+	reg &= ~(MXS_SSP_CHIPSELECT_MASK);
+	reg |= cs << MXS_SSP_CHIPSELECT_SHIFT;
 
+	writel(reg, &ssp_regs->hw_ssp_ctrl0);
 	return &mxs_slave->slave;
 }
 
diff --git a/drivers/usb/eth/asix.c b/drivers/usb/eth/asix.c
index 2f116c0cb6..a3bf51a64d 100644
--- a/drivers/usb/eth/asix.c
+++ b/drivers/usb/eth/asix.c
@@ -419,7 +419,7 @@ out_err:
 	return -1;
 }
 
-static int asix_send(struct eth_device *eth, volatile void *packet, int length)
+static int asix_send(struct eth_device *eth, void *packet, int length)
 {
 	struct ueth_data *dev = (struct ueth_data *)eth->priv;
 	int err;
diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c
index 2f63340fdb..c7aebea4e3 100644
--- a/drivers/usb/eth/smsc95xx.c
+++ b/drivers/usb/eth/smsc95xx.c
@@ -657,8 +657,7 @@ static int smsc95xx_init(struct eth_device *eth, bd_t *bd)
 	return 0;
 }
 
-static int smsc95xx_send(struct eth_device *eth, volatile void* packet,
-			 int length)
+static int smsc95xx_send(struct eth_device *eth, void* packet, int length)
 {
 	struct ueth_data *dev = (struct ueth_data *)eth->priv;
 	int err;
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 87d1918cb9..c3eca4b9fe 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -47,6 +47,10 @@ COBJS-$(CONFIG_CPU_PXA27X) += pxa27x_udc.o
 endif
 endif
 
+ifndef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_USB_FASTBOOT) += f_fastboot.o fastboot.o
+endif
+
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
new file mode 100644
index 0000000000..ebb5131a9c
--- /dev/null
+++ b/drivers/usb/gadget/composite.c
@@ -0,0 +1,1082 @@
+/*
+ * composite.c - infrastructure for Composite USB Gadgets
+ *
+ * Copyright (C) 2006-2008 David Brownell
+ * U-boot porting: Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#undef DEBUG
+
+#include <linux/bitops.h>
+#include <linux/usb/composite.h>
+
+#define USB_BUFSIZ	4096
+
+static struct usb_composite_driver *composite;
+
+/**
+ * usb_add_function() - add a function to a configuration
+ * @config: the configuration
+ * @function: the function being added
+ * Context: single threaded during gadget setup
+ *
+ * After initialization, each configuration must have one or more
+ * functions added to it.  Adding a function involves calling its @bind()
+ * method to allocate resources such as interface and string identifiers
+ * and endpoints.
+ *
+ * This function returns the value of the function's bind(), which is
+ * zero for success else a negative errno value.
+ */
+int usb_add_function(struct usb_configuration *config,
+		struct usb_function *function)
+{
+	int	value = -EINVAL;
+
+	debug("adding '%s'/%p to config '%s'/%p\n",
+			function->name, function,
+			config->label, config);
+
+	if (!function->set_alt || !function->disable)
+		goto done;
+
+	function->config = config;
+	list_add_tail(&function->list, &config->functions);
+
+	if (function->bind) {
+		value = function->bind(config, function);
+		if (value < 0) {
+			list_del(&function->list);
+			function->config = NULL;
+		}
+	} else
+		value = 0;
+
+	if (!config->fullspeed && function->descriptors)
+		config->fullspeed = 1;
+	if (!config->highspeed && function->hs_descriptors)
+		config->highspeed = 1;
+
+done:
+	if (value)
+		debug("adding '%s'/%p --> %d\n",
+				function->name, function, value);
+	return value;
+}
+
+/**
+ * usb_function_deactivate - prevent function and gadget enumeration
+ * @function: the function that isn't yet ready to respond
+ *
+ * Blocks response of the gadget driver to host enumeration by
+ * preventing the data line pullup from being activated.  This is
+ * normally called during @bind() processing to change from the
+ * initial "ready to respond" state, or when a required resource
+ * becomes available.
+ *
+ * For example, drivers that serve as a passthrough to a userspace
+ * daemon can block enumeration unless that daemon (such as an OBEX,
+ * MTP, or print server) is ready to handle host requests.
+ *
+ * Not all systems support software control of their USB peripheral
+ * data pullups.
+ *
+ * Returns zero on success, else negative errno.
+ */
+int usb_function_deactivate(struct usb_function *function)
+{
+	struct usb_composite_dev	*cdev = function->config->cdev;
+	int				status = 0;
+
+	if (cdev->deactivations == 0)
+		status = usb_gadget_disconnect(cdev->gadget);
+	if (status == 0)
+		cdev->deactivations++;
+
+	return status;
+}
+
+/**
+ * usb_function_activate - allow function and gadget enumeration
+ * @function: function on which usb_function_activate() was called
+ *
+ * Reverses effect of usb_function_deactivate().  If no more functions
+ * are delaying their activation, the gadget driver will respond to
+ * host enumeration procedures.
+ *
+ * Returns zero on success, else negative errno.
+ */
+int usb_function_activate(struct usb_function *function)
+{
+	struct usb_composite_dev	*cdev = function->config->cdev;
+	int				status = 0;
+
+	if (cdev->deactivations == 0)
+		status = -EINVAL;
+	else {
+		cdev->deactivations--;
+		if (cdev->deactivations == 0)
+			status = usb_gadget_connect(cdev->gadget);
+	}
+
+	return status;
+}
+
+/**
+ * usb_interface_id() - allocate an unused interface ID
+ * @config: configuration associated with the interface
+ * @function: function handling the interface
+ * Context: single threaded during gadget setup
+ *
+ * usb_interface_id() is called from usb_function.bind() callbacks to
+ * allocate new interface IDs.  The function driver will then store that
+ * ID in interface, association, CDC union, and other descriptors.  It
+ * will also handle any control requests targetted at that interface,
+ * particularly changing its altsetting via set_alt().  There may
+ * also be class-specific or vendor-specific requests to handle.
+ *
+ * All interface identifier should be allocated using this routine, to
+ * ensure that for example different functions don't wrongly assign
+ * different meanings to the same identifier.  Note that since interface
+ * identifers are configuration-specific, functions used in more than
+ * one configuration (or more than once in a given configuration) need
+ * multiple versions of the relevant descriptors.
+ *
+ * Returns the interface ID which was allocated; or -ENODEV if no
+ * more interface IDs can be allocated.
+ */
+int usb_interface_id(struct usb_configuration *config,
+		struct usb_function *function)
+{
+	unsigned char id = config->next_interface_id;
+
+	if (id < MAX_CONFIG_INTERFACES) {
+		config->interface[id] = function;
+		config->next_interface_id = id + 1;
+		return id;
+	}
+	return -ENODEV;
+}
+
+static int config_buf(struct usb_configuration *config,
+		enum usb_device_speed speed, void *buf, u8 type)
+{
+	int				len = USB_BUFSIZ - USB_DT_CONFIG_SIZE;
+	void				*next = buf + USB_DT_CONFIG_SIZE;
+	struct usb_descriptor_header    **descriptors;
+	struct usb_config_descriptor	*c = buf;
+	int				status;
+	struct usb_function		*f;
+
+	/* write the config descriptor */
+	c = buf;
+	c->bLength = USB_DT_CONFIG_SIZE;
+	c->bDescriptorType = type;
+
+	c->bNumInterfaces = config->next_interface_id;
+	c->bConfigurationValue = config->bConfigurationValue;
+	c->iConfiguration = config->iConfiguration;
+	c->bmAttributes = USB_CONFIG_ATT_ONE | config->bmAttributes;
+	c->bMaxPower = config->bMaxPower ? : (CONFIG_USB_GADGET_VBUS_DRAW / 2);
+
+	/* There may be e.g. OTG descriptors */
+	if (config->descriptors) {
+		status = usb_descriptor_fillbuf(next, len,
+				config->descriptors);
+		if (status < 0)
+			return status;
+		len -= status;
+		next += status;
+	}
+
+	/* add each function's descriptors */
+	list_for_each_entry(f, &config->functions, list) {
+		if (speed == USB_SPEED_HIGH)
+			descriptors = f->hs_descriptors;
+		else
+			descriptors = f->descriptors;
+		if (!descriptors)
+			continue;
+		status = usb_descriptor_fillbuf(next, len,
+			(const struct usb_descriptor_header **) descriptors);
+		if (status < 0)
+			return status;
+		len -= status;
+		next += status;
+	}
+
+	len = next - buf;
+	c->wTotalLength = cpu_to_le16(len);
+	return len;
+}
+
+static int config_desc(struct usb_composite_dev *cdev, unsigned w_value)
+{
+	enum usb_device_speed		speed = USB_SPEED_UNKNOWN;
+	struct usb_gadget		*gadget = cdev->gadget;
+	u8				type = w_value >> 8;
+	int                             hs = 0;
+	struct usb_configuration	*c;
+
+	if (gadget_is_dualspeed(gadget)) {
+		if (gadget->speed == USB_SPEED_HIGH)
+			hs = 1;
+		if (type == USB_DT_OTHER_SPEED_CONFIG)
+			hs = !hs;
+		if (hs)
+			speed = USB_SPEED_HIGH;
+	}
+
+	w_value &= 0xff;
+	list_for_each_entry(c, &cdev->configs, list) {
+		if (speed == USB_SPEED_HIGH) {
+			if (!c->highspeed)
+				continue;
+		} else {
+			if (!c->fullspeed)
+				continue;
+		}
+		if (w_value == 0)
+			return config_buf(c, speed, cdev->req->buf, type);
+		w_value--;
+	}
+	return -EINVAL;
+}
+
+static int count_configs(struct usb_composite_dev *cdev, unsigned type)
+{
+	struct usb_gadget		*gadget = cdev->gadget;
+	unsigned			count = 0;
+	int				hs = 0;
+	struct usb_configuration	*c;
+
+	if (gadget_is_dualspeed(gadget)) {
+		if (gadget->speed == USB_SPEED_HIGH)
+			hs = 1;
+		if (type == USB_DT_DEVICE_QUALIFIER)
+			hs = !hs;
+	}
+	list_for_each_entry(c, &cdev->configs, list) {
+		/* ignore configs that won't work at this speed */
+		if (hs) {
+			if (!c->highspeed)
+				continue;
+		} else {
+			if (!c->fullspeed)
+				continue;
+		}
+		count++;
+	}
+	return count;
+}
+
+static void device_qual(struct usb_composite_dev *cdev)
+{
+	struct usb_qualifier_descriptor	*qual = cdev->req->buf;
+
+	qual->bLength = sizeof(*qual);
+	qual->bDescriptorType = USB_DT_DEVICE_QUALIFIER;
+	/* POLICY: same bcdUSB and device type info at both speeds */
+	qual->bcdUSB = cdev->desc.bcdUSB;
+	qual->bDeviceClass = cdev->desc.bDeviceClass;
+	qual->bDeviceSubClass = cdev->desc.bDeviceSubClass;
+	qual->bDeviceProtocol = cdev->desc.bDeviceProtocol;
+	/* ASSUME same EP0 fifo size at both speeds */
+	qual->bMaxPacketSize0 = cdev->desc.bMaxPacketSize0;
+	qual->bNumConfigurations = count_configs(cdev, USB_DT_DEVICE_QUALIFIER);
+	qual->bRESERVED = 0;
+}
+
+static void reset_config(struct usb_composite_dev *cdev)
+{
+	struct usb_function		*f;
+
+	debug("%s:\n", __func__);
+
+	list_for_each_entry(f, &cdev->config->functions, list) {
+		if (f->disable)
+			f->disable(f);
+
+		bitmap_zero(f->endpoints, 32);
+	}
+	cdev->config = NULL;
+}
+
+static int set_config(struct usb_composite_dev *cdev,
+		const struct usb_ctrlrequest *ctrl, unsigned number)
+{
+	struct usb_gadget	*gadget = cdev->gadget;
+	unsigned		power = gadget_is_otg(gadget) ? 8 : 100;
+	struct usb_descriptor_header **descriptors;
+	int			result = -EINVAL;
+	struct usb_endpoint_descriptor *ep;
+	struct usb_configuration *c = NULL;
+	int                     addr;
+	int			tmp;
+	struct usb_function	*f;
+
+	if (cdev->config)
+		reset_config(cdev);
+
+	if (number) {
+		list_for_each_entry(c, &cdev->configs, list) {
+			if (c->bConfigurationValue == number) {
+				result = 0;
+				break;
+			}
+		}
+		if (result < 0)
+			goto done;
+	} else
+		result = 0;
+
+	debug("%s: %s speed config #%d: %s\n", __func__,
+	     ({ char *speed;
+		     switch (gadget->speed) {
+		     case USB_SPEED_LOW:
+			     speed = "low";
+			     break;
+		     case USB_SPEED_FULL:
+			     speed = "full";
+			     break;
+		     case USB_SPEED_HIGH:
+			     speed = "high";
+			     break;
+		     default:
+			     speed = "?";
+			     break;
+		     };
+		     speed;
+	     }), number, c ? c->label : "unconfigured");
+
+	if (!c)
+		goto done;
+
+	cdev->config = c;
+
+	/* Initialize all interfaces by setting them to altsetting zero. */
+	for (tmp = 0; tmp < MAX_CONFIG_INTERFACES; tmp++) {
+		f = c->interface[tmp];
+		if (!f)
+			break;
+
+		/*
+		 * Record which endpoints are used by the function. This is used
+		 * to dispatch control requests targeted at that endpoint to the
+		 * function's setup callback instead of the current
+		 * configuration's setup callback.
+		 */
+		if (gadget->speed == USB_SPEED_HIGH)
+			descriptors = f->hs_descriptors;
+		else
+			descriptors = f->descriptors;
+
+		for (; *descriptors; ++descriptors) {
+			if ((*descriptors)->bDescriptorType != USB_DT_ENDPOINT)
+				continue;
+
+			ep = (struct usb_endpoint_descriptor *)*descriptors;
+			addr = ((ep->bEndpointAddress & 0x80) >> 3)
+			     |	(ep->bEndpointAddress & 0x0f);
+			__set_bit(addr, f->endpoints);
+		}
+
+		result = f->set_alt(f, tmp, 0);
+		if (result < 0) {
+			debug("interface %d (%s/%p) alt 0 --> %d\n",
+					tmp, f->name, f, result);
+
+			reset_config(cdev);
+			goto done;
+		}
+	}
+
+	/* when we return, be sure our power usage is valid */
+	power = c->bMaxPower ? (2 * c->bMaxPower) : CONFIG_USB_GADGET_VBUS_DRAW;
+done:
+	usb_gadget_vbus_draw(gadget, power);
+	return result;
+}
+
+/**
+ * usb_add_config() - add a configuration to a device.
+ * @cdev: wraps the USB gadget
+ * @config: the configuration, with bConfigurationValue assigned
+ * Context: single threaded during gadget setup
+ *
+ * One of the main tasks of a composite driver's bind() routine is to
+ * add each of the configurations it supports, using this routine.
+ *
+ * This function returns the value of the configuration's bind(), which
+ * is zero for success else a negative errno value.  Binding configurations
+ * assigns global resources including string IDs, and per-configuration
+ * resources such as interface IDs and endpoints.
+ */
+int usb_add_config(struct usb_composite_dev *cdev,
+		struct usb_configuration *config)
+{
+	int				status = -EINVAL;
+	struct usb_configuration	*c;
+	struct usb_function		*f;
+	unsigned int			i;
+
+	debug("%s: adding config #%u '%s'/%p\n", __func__,
+			config->bConfigurationValue,
+			config->label, config);
+
+	if (!config->bConfigurationValue || !config->bind)
+		goto done;
+
+	/* Prevent duplicate configuration identifiers */
+	list_for_each_entry(c, &cdev->configs, list) {
+		if (c->bConfigurationValue == config->bConfigurationValue) {
+			status = -EBUSY;
+			goto done;
+		}
+	}
+
+	config->cdev = cdev;
+	list_add_tail(&config->list, &cdev->configs);
+
+	INIT_LIST_HEAD(&config->functions);
+	config->next_interface_id = 0;
+
+	status = config->bind(config);
+	if (status < 0) {
+		list_del(&config->list);
+		config->cdev = NULL;
+	} else {
+		debug("cfg %d/%p speeds:%s%s\n",
+			config->bConfigurationValue, config,
+			config->highspeed ? " high" : "",
+			config->fullspeed
+				? (gadget_is_dualspeed(cdev->gadget)
+					? " full"
+					: " full/low")
+				: "");
+
+		for (i = 0; i < MAX_CONFIG_INTERFACES; i++) {
+			f = config->interface[i];
+			if (!f)
+				continue;
+			debug("%s: interface %d = %s/%p\n",
+			      __func__, i, f->name, f);
+		}
+	}
+
+	usb_ep_autoconfig_reset(cdev->gadget);
+
+done:
+	if (status)
+		debug("added config '%s'/%u --> %d\n", config->label,
+				config->bConfigurationValue, status);
+	return status;
+}
+
+/*
+ * We support strings in multiple languages ... string descriptor zero
+ * says which languages are supported.	The typical case will be that
+ * only one language (probably English) is used, with I18N handled on
+ * the host side.
+ */
+
+static void collect_langs(struct usb_gadget_strings **sp, __le16 *buf)
+{
+	const struct usb_gadget_strings	*s;
+	u16				language;
+	__le16				*tmp;
+
+	while (*sp) {
+		s = *sp;
+		language = cpu_to_le16(s->language);
+		for (tmp = buf; *tmp && tmp < &buf[126]; tmp++) {
+			if (*tmp == language)
+				goto repeat;
+		}
+		*tmp++ = language;
+repeat:
+		sp++;
+	}
+}
+
+static int lookup_string(
+	struct usb_gadget_strings	**sp,
+	void				*buf,
+	u16				language,
+	int				id
+)
+{
+	int				value;
+	struct usb_gadget_strings	*s;
+
+	while (*sp) {
+		s = *sp++;
+		if (s->language != language)
+			continue;
+		value = usb_gadget_get_string(s, id, buf);
+		if (value > 0)
+			return value;
+	}
+	return -EINVAL;
+}
+
+static int get_string(struct usb_composite_dev *cdev,
+		void *buf, u16 language, int id)
+{
+	struct usb_string_descriptor	*s = buf;
+	struct usb_gadget_strings	**sp;
+	int				len;
+	struct usb_configuration	*c;
+	struct usb_function		*f;
+
+	/*
+	 * Yes, not only is USB's I18N support probably more than most
+	 * folk will ever care about ... also, it's all supported here.
+	 * (Except for UTF8 support for Unicode's "Astral Planes".)
+	 */
+
+	/* 0 == report all available language codes */
+	if (id == 0) {
+		memset(s, 0, 256);
+		s->bDescriptorType = USB_DT_STRING;
+
+		sp = composite->strings;
+		if (sp)
+			collect_langs(sp, s->wData);
+
+		list_for_each_entry(c, &cdev->configs, list) {
+			sp = c->strings;
+			if (sp)
+				collect_langs(sp, s->wData);
+
+			list_for_each_entry(f, &c->functions, list) {
+				sp = f->strings;
+				if (sp)
+					collect_langs(sp, s->wData);
+			}
+		}
+
+		for (len = 0; len <= 126 && s->wData[len]; len++)
+			continue;
+		if (!len)
+			return -EINVAL;
+
+		s->bLength = 2 * (len + 1);
+		return s->bLength;
+	}
+
+	/*
+	 * Otherwise, look up and return a specified string.  String IDs
+	 * are device-scoped, so we look up each string table we're told
+	 * about.  These lookups are infrequent; simpler-is-better here.
+	 */
+	if (composite->strings) {
+		len = lookup_string(composite->strings, buf, language, id);
+		if (len > 0)
+			return len;
+	}
+	list_for_each_entry(c, &cdev->configs, list) {
+		if (c->strings) {
+			len = lookup_string(c->strings, buf, language, id);
+			if (len > 0)
+				return len;
+		}
+		list_for_each_entry(f, &c->functions, list) {
+			if (!f->strings)
+				continue;
+			len = lookup_string(f->strings, buf, language, id);
+			if (len > 0)
+				return len;
+		}
+	}
+	return -EINVAL;
+}
+
+/**
+ * usb_string_id() - allocate an unused string ID
+ * @cdev: the device whose string descriptor IDs are being allocated
+ * Context: single threaded during gadget setup
+ *
+ * @usb_string_id() is called from bind() callbacks to allocate
+ * string IDs.	Drivers for functions, configurations, or gadgets will
+ * then store that ID in the appropriate descriptors and string table.
+ *
+ * All string identifier should be allocated using this,
+ * @usb_string_ids_tab() or @usb_string_ids_n() routine, to ensure
+ * that for example different functions don't wrongly assign different
+ * meanings to the same identifier.
+ */
+int usb_string_id(struct usb_composite_dev *cdev)
+{
+	if (cdev->next_string_id < 254) {
+		/*
+		 * string id 0 is reserved by USB spec for list of
+		 * supported languages
+		 * 255 reserved as well? -- mina86
+		 */
+		cdev->next_string_id++;
+		return cdev->next_string_id;
+	}
+	return -ENODEV;
+}
+
+/**
+ * usb_string_ids() - allocate unused string IDs in batch
+ * @cdev: the device whose string descriptor IDs are being allocated
+ * @str: an array of usb_string objects to assign numbers to
+ * Context: single threaded during gadget setup
+ *
+ * @usb_string_ids() is called from bind() callbacks to allocate
+ * string IDs.	Drivers for functions, configurations, or gadgets will
+ * then copy IDs from the string table to the appropriate descriptors
+ * and string table for other languages.
+ *
+ * All string identifier should be allocated using this,
+ * @usb_string_id() or @usb_string_ids_n() routine, to ensure that for
+ * example different functions don't wrongly assign different meanings
+ * to the same identifier.
+ */
+int usb_string_ids_tab(struct usb_composite_dev *cdev, struct usb_string *str)
+{
+	u8 next = cdev->next_string_id;
+
+	for (; str->s; ++str) {
+		if (next >= 254)
+			return -ENODEV;
+		str->id = ++next;
+	}
+
+	cdev->next_string_id = next;
+
+	return 0;
+}
+
+/**
+ * usb_string_ids_n() - allocate unused string IDs in batch
+ * @c: the device whose string descriptor IDs are being allocated
+ * @n: number of string IDs to allocate
+ * Context: single threaded during gadget setup
+ *
+ * Returns the first requested ID.  This ID and next @n-1 IDs are now
+ * valid IDs.  At least provided that @n is non-zero because if it
+ * is, returns last requested ID which is now very useful information.
+ *
+ * @usb_string_ids_n() is called from bind() callbacks to allocate
+ * string IDs.	Drivers for functions, configurations, or gadgets will
+ * then store that ID in the appropriate descriptors and string table.
+ *
+ * All string identifier should be allocated using this,
+ * @usb_string_id() or @usb_string_ids_n() routine, to ensure that for
+ * example different functions don't wrongly assign different meanings
+ * to the same identifier.
+ */
+int usb_string_ids_n(struct usb_composite_dev *c, unsigned n)
+{
+	u8 next = c->next_string_id;
+
+	if (n > 254 || next + n > 254)
+		return -ENODEV;
+
+	c->next_string_id += n;
+	return next + 1;
+}
+
+static void composite_setup_complete(struct usb_ep *ep, struct usb_request *req)
+{
+	if (req->status || req->actual != req->length)
+		debug("%s: setup complete --> %d, %d/%d\n", __func__,
+				req->status, req->actual, req->length);
+}
+
+/*
+ * The setup() callback implements all the ep0 functionality that's
+ * not handled lower down, in hardware or the hardware driver(like
+ * device and endpoint feature flags, and their status).  It's all
+ * housekeeping for the gadget function we're implementing.  Most of
+ * the work is in config and function specific setup.
+ */
+static int
+composite_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
+{
+	u16				w_length = le16_to_cpu(ctrl->wLength);
+	u16				w_index = le16_to_cpu(ctrl->wIndex);
+	u16				w_value = le16_to_cpu(ctrl->wValue);
+	struct usb_composite_dev	*cdev = get_gadget_data(gadget);
+	u8				intf = w_index & 0xFF;
+	int				value = -EOPNOTSUPP;
+	struct usb_request		*req = cdev->req;
+	struct usb_function		*f = NULL;
+	int				standard;
+	u8				endp;
+	struct usb_configuration	*c;
+
+	/*
+	 * partial re-init of the response message; the function or the
+	 * gadget might need to intercept e.g. a control-OUT completion
+	 * when we delegate to it.
+	 */
+	req->zero = 0;
+	req->complete = composite_setup_complete;
+	req->length = USB_BUFSIZ;
+	gadget->ep0->driver_data = cdev;
+	standard = (ctrl->bRequestType & USB_TYPE_MASK)
+						== USB_TYPE_STANDARD;
+	if (!standard)
+		goto unknown;
+
+	switch (ctrl->bRequest) {
+
+	/* we handle all standard USB descriptors */
+	case USB_REQ_GET_DESCRIPTOR:
+		if (ctrl->bRequestType != USB_DIR_IN)
+			goto unknown;
+		switch (w_value >> 8) {
+
+		case USB_DT_DEVICE:
+			cdev->desc.bNumConfigurations =
+				count_configs(cdev, USB_DT_DEVICE);
+			value = min(w_length, (u16) sizeof cdev->desc);
+			memcpy(req->buf, &cdev->desc, value);
+			break;
+		case USB_DT_DEVICE_QUALIFIER:
+			if (!gadget_is_dualspeed(gadget))
+				break;
+			device_qual(cdev);
+			value = min(w_length,
+				sizeof(struct usb_qualifier_descriptor));
+			break;
+		case USB_DT_OTHER_SPEED_CONFIG:
+			if (!gadget_is_dualspeed(gadget))
+				break;
+
+		case USB_DT_CONFIG:
+			value = config_desc(cdev, w_value);
+			if (value >= 0)
+				value = min(w_length, (u16) value);
+			break;
+		case USB_DT_STRING:
+			value = get_string(cdev, req->buf,
+					w_index, w_value & 0xff);
+			if (value >= 0)
+				value = min(w_length, (u16) value);
+			break;
+		default:
+			goto unknown;
+		}
+		break;
+
+	/* any number of configs can work */
+	case USB_REQ_SET_CONFIGURATION:
+		if (ctrl->bRequestType != 0)
+			goto unknown;
+		if (gadget_is_otg(gadget)) {
+			if (gadget->a_hnp_support)
+				debug("HNP available\n");
+			else if (gadget->a_alt_hnp_support)
+				debug("HNP on another port\n");
+			else
+				debug("HNP inactive\n");
+		}
+
+		value = set_config(cdev, ctrl, w_value);
+		break;
+	case USB_REQ_GET_CONFIGURATION:
+		if (ctrl->bRequestType != USB_DIR_IN)
+			goto unknown;
+		if (cdev->config)
+			*(u8 *)req->buf = cdev->config->bConfigurationValue;
+		else
+			*(u8 *)req->buf = 0;
+		value = min(w_length, (u16) 1);
+		break;
+
+	/*
+	 * function drivers must handle get/set altsetting; if there's
+	 * no get() method, we know only altsetting zero works.
+	 */
+	case USB_REQ_SET_INTERFACE:
+		if (ctrl->bRequestType != USB_RECIP_INTERFACE)
+			goto unknown;
+		if (!cdev->config || w_index >= MAX_CONFIG_INTERFACES)
+			break;
+		f = cdev->config->interface[intf];
+		if (!f)
+			break;
+		if (w_value && !f->set_alt)
+			break;
+		value = f->set_alt(f, w_index, w_value);
+		break;
+	case USB_REQ_GET_INTERFACE:
+		if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE))
+			goto unknown;
+		if (!cdev->config || w_index >= MAX_CONFIG_INTERFACES)
+			break;
+		f = cdev->config->interface[intf];
+		if (!f)
+			break;
+		/* lots of interfaces only need altsetting zero... */
+		value = f->get_alt ? f->get_alt(f, w_index) : 0;
+		if (value < 0)
+			break;
+		*((u8 *)req->buf) = value;
+		value = min(w_length, (u16) 1);
+		break;
+	default:
+unknown:
+		debug("non-core control req%02x.%02x v%04x i%04x l%d\n",
+			ctrl->bRequestType, ctrl->bRequest,
+			w_value, w_index, w_length);
+
+		/*
+		 * functions always handle their interfaces and endpoints...
+		 * punt other recipients (other, WUSB, ...) to the current
+		 * configuration code.
+		 */
+		switch (ctrl->bRequestType & USB_RECIP_MASK) {
+		case USB_RECIP_INTERFACE:
+			f = cdev->config->interface[intf];
+			break;
+
+		case USB_RECIP_ENDPOINT:
+			endp = ((w_index & 0x80) >> 3) | (w_index & 0x0f);
+			list_for_each_entry(f, &cdev->config->functions, list) {
+				if (test_bit(endp, f->endpoints))
+					break;
+			}
+			if (&f->list == &cdev->config->functions)
+				f = NULL;
+			break;
+		}
+
+		if (f && f->setup)
+			value = f->setup(f, ctrl);
+		else {
+			c = cdev->config;
+			if (c && c->setup)
+				value = c->setup(c, ctrl);
+		}
+
+		goto done;
+	}
+
+	/* respond with data transfer before status phase? */
+	if (value >= 0) {
+		req->length = value;
+		req->zero = value < w_length;
+		value = usb_ep_queue(gadget->ep0, req, GFP_KERNEL);
+		if (value < 0) {
+			debug("ep_queue --> %d\n", value);
+			req->status = 0;
+			composite_setup_complete(gadget->ep0, req);
+		}
+	}
+
+done:
+	/* device either stalls (value < 0) or reports success */
+	return value;
+}
+
+static void composite_disconnect(struct usb_gadget *gadget)
+{
+	struct usb_composite_dev	*cdev = get_gadget_data(gadget);
+
+	if (cdev->config)
+		reset_config(cdev);
+	if (composite->disconnect)
+		composite->disconnect(cdev);
+}
+
+static void composite_unbind(struct usb_gadget *gadget)
+{
+	struct usb_composite_dev	*cdev = get_gadget_data(gadget);
+	struct usb_configuration	*c;
+	struct usb_function		*f;
+
+	/*
+	 * composite_disconnect() must already have been called
+	 * by the underlying peripheral controller driver!
+	 * so there's no i/o concurrency that could affect the
+	 * state protected by cdev->lock.
+	 */
+	BUG_ON(cdev->config);
+
+	while (!list_empty(&cdev->configs)) {
+		c = list_first_entry(&cdev->configs,
+				struct usb_configuration, list);
+		while (!list_empty(&c->functions)) {
+			f = list_first_entry(&c->functions,
+					struct usb_function, list);
+			list_del(&f->list);
+			if (f->unbind) {
+				debug("unbind function '%s'/%p\n",
+						f->name, f);
+				f->unbind(c, f);
+			}
+		}
+		list_del(&c->list);
+		if (c->unbind) {
+			debug("unbind config '%s'/%p\n", c->label, c);
+			c->unbind(c);
+		}
+	}
+	if (composite->unbind)
+		composite->unbind(cdev);
+
+	if (cdev->req) {
+		kfree(cdev->req->buf);
+		usb_ep_free_request(gadget->ep0, cdev->req);
+	}
+	kfree(cdev);
+	set_gadget_data(gadget, NULL);
+
+	composite = NULL;
+}
+
+static int composite_bind(struct usb_gadget *gadget)
+{
+	int				status = -ENOMEM;
+	struct usb_composite_dev	*cdev;
+
+	cdev = calloc(sizeof *cdev, 1);
+	if (!cdev)
+		return status;
+
+	cdev->gadget = gadget;
+	set_gadget_data(gadget, cdev);
+	INIT_LIST_HEAD(&cdev->configs);
+
+	/* preallocate control response and buffer */
+	cdev->req = usb_ep_alloc_request(gadget->ep0, GFP_KERNEL);
+	if (!cdev->req)
+		goto fail;
+	cdev->req->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, USB_BUFSIZ);
+	if (!cdev->req->buf)
+		goto fail;
+	cdev->req->complete = composite_setup_complete;
+	gadget->ep0->driver_data = cdev;
+
+	cdev->bufsiz = USB_BUFSIZ;
+	cdev->driver = composite;
+
+	usb_gadget_set_selfpowered(gadget);
+	usb_ep_autoconfig_reset(cdev->gadget);
+
+	status = composite->bind(cdev);
+	if (status < 0)
+		goto fail;
+
+	cdev->desc = *composite->dev;
+	cdev->desc.bMaxPacketSize0 = gadget->ep0->maxpacket;
+
+	debug("%s: ready\n", composite->name);
+	return 0;
+
+fail:
+	composite_unbind(gadget);
+	return status;
+}
+
+static void
+composite_suspend(struct usb_gadget *gadget)
+{
+	struct usb_composite_dev	*cdev = get_gadget_data(gadget);
+	struct usb_function		*f;
+
+	debug("%s: suspend\n", __func__);
+	if (cdev->config) {
+		list_for_each_entry(f, &cdev->config->functions, list) {
+			if (f->suspend)
+				f->suspend(f);
+		}
+	}
+	if (composite->suspend)
+		composite->suspend(cdev);
+
+	cdev->suspended = 1;
+}
+
+static void
+composite_resume(struct usb_gadget *gadget)
+{
+	struct usb_composite_dev	*cdev = get_gadget_data(gadget);
+	struct usb_function		*f;
+
+	debug("%s: resume\n", __func__);
+	if (composite->resume)
+		composite->resume(cdev);
+	if (cdev->config) {
+		list_for_each_entry(f, &cdev->config->functions, list) {
+			if (f->resume)
+				f->resume(f);
+		}
+	}
+
+	cdev->suspended = 0;
+}
+
+static struct usb_gadget_driver composite_driver = {
+	.speed		= USB_SPEED_HIGH,
+
+	.bind		= composite_bind,
+	.unbind         = composite_unbind,
+
+	.setup		= composite_setup,
+	.disconnect	= composite_disconnect,
+
+	.suspend        = composite_suspend,
+	.resume         = composite_resume,
+};
+
+/**
+ * usb_composite_register() - register a composite driver
+ * @driver: the driver to register
+ * Context: single threaded during gadget setup
+ *
+ * This function is used to register drivers using the composite driver
+ * framework.  The return value is zero, or a negative errno value.
+ * Those values normally come from the driver's @bind method, which does
+ * all the work of setting up the driver to match the hardware.
+ *
+ * On successful return, the gadget is ready to respond to requests from
+ * the host, unless one of its components invokes usb_gadget_disconnect()
+ * while it was binding.  That would usually be done in order to wait for
+ * some userspace participation.
+ */
+int usb_composite_register(struct usb_composite_driver *driver)
+{
+	if (!driver || !driver->dev || !driver->bind || composite)
+		return -EINVAL;
+
+	if (!driver->name)
+		driver->name = "composite";
+	composite = driver;
+
+	return usb_gadget_register_driver(&composite_driver);
+}
+
+/**
+ * usb_composite_unregister() - unregister a composite driver
+ * @driver: the driver to unregister
+ *
+ * This function is used to unregister drivers using the composite
+ * driver framework.
+ */
+void usb_composite_unregister(struct usb_composite_driver *driver)
+{
+	if (composite != driver)
+		return;
+	usb_gadget_unregister_driver(&composite_driver);
+}
diff --git a/drivers/usb/gadget/config.c b/drivers/usb/gadget/config.c
index f9163a80ed..f88d0c190c 100644
--- a/drivers/usb/gadget/config.c
+++ b/drivers/usb/gadget/config.c
@@ -27,6 +27,7 @@
 #include <linux/string.h>
 
 #include <linux/usb/ch9.h>
+#include <usbdescriptors.h>
 #include <linux/usb/gadget.h>
 
 
diff --git a/drivers/usb/gadget/core.c b/drivers/usb/gadget/core.c
index 46ab3f67f8..1ab14eb3b4 100644
--- a/drivers/usb/gadget/core.c
+++ b/drivers/usb/gadget/core.c
@@ -364,11 +364,12 @@ void usbd_rcv_complete(struct usb_endpoint_instance *endpoint, int len, int urb_
 			/*rcv_urb->actual_length, rcv_urb->buffer_length); */
 
 			/* check the urb is ok, are we adding data less than the packetsize */
-			if (!urb_bad && (len <= endpoint->rcv_packetSize)) {
+			if (!urb_bad) {
 			  /*usbdbg("updating actual_length by %d\n",len); */
 
 				/* increment the received data size */
 				rcv_urb->actual_length += len;
+				rcv_urb->req_length = 0;
 
 			} else {
 				usberr(" RECV_ERROR actual: %d buffer: %d urb_bad: %d\n",
@@ -560,14 +561,55 @@ struct urb *usbd_alloc_urb (struct usb_device_instance *device,
 	memset (urb, 0, sizeof (struct urb));
 	urb->endpoint = endpoint;
 	urb->device = device;
-	urb->buffer = (u8 *) urb->buffer_data;
-	urb->buffer_length = sizeof (urb->buffer_data);
+	urb->buffer = malloc(URB_BUF_SIZE);
+	if (!urb->buffer) {
+		usberr (" F A T A L:  mallocFAILED!!!!");
+		return NULL;
+	}
+	urb->buffer_length = URB_BUF_SIZE;
+	urb->buffer_data = urb->buffer;
 
 	urb_link_init (&urb->link);
 
 	return urb;
 }
 
+int usbd_init_urb (struct urb *urb,
+		struct usb_device_instance *device,
+		struct usb_endpoint_instance *endpoint,
+		u8 *buf, unsigned int len)
+{
+	/* Fill in known fields */
+	memset (urb, 0, sizeof (struct urb));
+	urb->endpoint = endpoint;
+	urb->device = device;
+	urb->buffer = buf;
+	urb->buffer_length = len;
+	urb->buffer_data = buf;
+
+	urb_link_init (&urb->link);
+
+	return 0;
+}
+
+int usbd_setup_urb(struct urb *urb, u8 *buf, u32 len, int dma)
+{
+	if (urb) {
+		urb->req_length = len;
+		urb->buffer = buf;
+		urb->use_dma = dma;
+	}
+	return 0;
+}
+
+void usbd_free_urb(struct urb *urb)
+{
+	if (urb) {
+		urb->req_length = 0;
+		urb->actual_length = 0;
+		urb->buffer = NULL;
+	}
+}
 /**
  * usbd_dealloc_urb - deallocate an URB and associated buffer
  * @urb: pointer to an urb structure
@@ -577,6 +619,8 @@ struct urb *usbd_alloc_urb (struct usb_device_instance *device,
 void usbd_dealloc_urb (struct urb *urb)
 {
 	if (urb) {
+		if (urb->buffer)
+			free (urb->buffer);
 		free (urb);
 	}
 }
diff --git a/drivers/usb/gadget/ep0.c b/drivers/usb/gadget/ep0.c
index aa8f91600d..40098c5fe9 100644
--- a/drivers/usb/gadget/ep0.c
+++ b/drivers/usb/gadget/ep0.c
@@ -388,6 +388,7 @@ static int ep0_get_descriptor (struct usb_device_instance *device,
  * or failure (STALL).
  *
  */
+void udc_clear_halt(unsigned int ep, int is_in);
 int ep0_recv_setup (struct urb *urb)
 {
 	/*struct usb_device_request *request = urb->buffer; */
@@ -540,14 +541,17 @@ int ep0_recv_setup (struct urb *urb)
 				return -1;
 
 			case USB_REQ_RECIPIENT_ENDPOINT:
-				dbg_ep0 (0, "ENDPOINT: %x", le16_to_cpu (request->wValue));
+				serial_printf ("ENDPOINT: %x \n", le16_to_cpu (request->wIndex) & 0x0f);
 				if (le16_to_cpu (request->wValue) == USB_ENDPOINT_HALT) {
+					u8 epnum = request->wIndex & 0xf;
+					int is_in = request->wIndex & USB_DIR_IN;
 					/*return usbd_device_feature (device, le16_to_cpu (request->wIndex), */
 					/*                    request->bRequest == USB_REQ_SET_FEATURE); */
 					/* NEED TO IMPLEMENT THIS!!! */
-					return -1;
+					udc_clear_halt(epnum, is_in);
+					return 0;
 				} else {
-					dbg_ep0 (1, "request %s bad wValue: %04x",
+					serial_printf ("request %s bad wValue: %04x",
 						 USBD_DEVICE_REQUESTS
 						 (request->bRequest),
 						 le16_to_cpu (request->wValue));
diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c
index 5b8776e0b7..b656c8b9f4 100644
--- a/drivers/usb/gadget/epautoconf.c
+++ b/drivers/usb/gadget/epautoconf.c
@@ -23,6 +23,7 @@
 
 #include <common.h>
 #include <linux/usb/ch9.h>
+#include <usbdescriptors.h>
 #include <asm/errno.h>
 #include <linux/usb/gadget.h>
 #include <asm/unaligned.h>
diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c
index 9fb0e80ad1..d975fb680e 100644
--- a/drivers/usb/gadget/ether.c
+++ b/drivers/usb/gadget/ether.c
@@ -24,6 +24,7 @@
 #include <asm/errno.h>
 #include <linux/netdevice.h>
 #include <linux/usb/ch9.h>
+#include <usbdescriptors.h>
 #include <linux/usb/cdc.h>
 #include <linux/usb/gadget.h>
 #include <net.h>
@@ -2396,8 +2397,7 @@ fail:
 	return -1;
 }
 
-static int usb_eth_send(struct eth_device *netdev,
-			volatile void *packet, int length)
+static int usb_eth_send(struct eth_device *netdev, void *packet, int length)
 {
 	int			retval;
 	void			*rndis_pkt = NULL;
@@ -2418,11 +2418,11 @@ static int usb_eth_send(struct eth_device *netdev,
 		}
 		rndis_add_hdr(rndis_pkt, length);
 		memcpy(rndis_pkt + sizeof(struct rndis_packet_msg_type),
-				(void *)packet, length);
+				packet, length);
 		packet = rndis_pkt;
 		length += sizeof(struct rndis_packet_msg_type);
 	}
-	req->buf = (void *)packet;
+	req->buf = packet;
 	req->context = NULL;
 	req->complete = tx_complete;
 
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
new file mode 100644
index 0000000000..67e5b76911
--- /dev/null
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -0,0 +1,473 @@
+/*
+ * ether.c -- Ethernet gadget driver, with CDC and non-CDC options
+ *
+ * Copyright (C) 2003-2005,2008 David Brownell
+ * Copyright (C) 2003-2004 Robert Schwebel, Benedikt Spranger
+ * Copyright (C) 2008 Nokia Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define DEBUG
+
+#include <common.h>
+#include <config.h>
+#include <asm/unaligned.h>
+#include "usbdescriptors.h"
+#include <usbdevice.h>
+
+#if defined(CONFIG_MUSB_UDC)
+#include <usb/musb_udc.h>
+#else
+#error "no usb device controller"
+#endif
+
+#define DEV_CONFIG_CDC	   1
+
+/* defined and used by gadget/ep0.c */
+extern struct usb_string_descriptor **usb_strings;
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * Thanks to NetChip Technologies for donating this product ID.
+ * It's for devices with only CDC Ethernet configurations.
+ */
+#define FASTBOOT_VENDOR_NUM		0x18D1	/* Goolge VID */
+#define FASTBOOT_PRODUCT_NUM		0x4EE0	/* Bootloader Product ID */
+
+#define FASTBOOT_MANUFACTURER			"RDAmicro"
+#define FASTBOOT_PRODUCT_NAME			"RDA Droid"
+#define FASTBOOT_CONFIGURATION_STR 	"fastboot"
+#define FASTBOOT_DATA_INTERFACE_STR 	"fastboot data intf"
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * DESCRIPTORS ... most are static, but strings and (full) configuration
+ * descriptors are built on demand.  For now we do either full CDC, or
+ * our simple subset.
+ */
+
+#define STRING_MANUFACTURER		1
+#define STRING_PRODUCT				2
+#define STRING_DATA				3
+#define STRING_CFG					4
+#define STRING_SERIALNUMBER		5
+
+#define NUM_ENDPOINTS 2
+
+static struct usb_device_instance fastboot_dev_instance[1];
+static struct usb_bus_instance fastboot_bus_instance[1];
+static struct usb_configuration_instance fastboot_cfg_instance;
+static struct usb_interface_instance fastboot_intf_instance[1];
+static struct usb_alternate_instance fastboot_alternate_instance[1];
+/* one extra for control endpoint */
+static struct usb_endpoint_instance fastboot_ep_instance[NUM_ENDPOINTS + 1];
+
+static char serial_number[] = "dragon2012";
+
+static struct usb_endpoint_descriptor *ep_desc_ptrs[NUM_ENDPOINTS];
+
+static struct usb_device_descriptor
+ device_desc = {
+	.bLength = sizeof device_desc,
+	.bDescriptorType = USB_DT_DEVICE,
+
+	.bcdUSB = __constant_cpu_to_le16(0x0200),
+
+	.bDeviceClass = USB_CLASS_VENDOR_SPEC,
+	.bDeviceSubClass = 0,
+	.bDeviceProtocol = 0,
+	.bMaxPacketSize0 = 64,
+	.idVendor = __constant_cpu_to_le16(FASTBOOT_VENDOR_NUM),
+	.idProduct = __constant_cpu_to_le16(FASTBOOT_PRODUCT_NUM),
+	.iManufacturer = STRING_MANUFACTURER,
+	.iProduct = STRING_PRODUCT,
+	.iSerialNumber = STRING_SERIALNUMBER,
+	.bNumConfigurations = 1,
+};
+
+static struct usb_interface_descriptor
+ data_intf = {
+	.bLength = sizeof data_intf,
+	.bDescriptorType = USB_DT_INTERFACE,
+
+	.bInterfaceNumber = 0,
+	.bAlternateSetting = 0,
+	.bNumEndpoints = 2,
+	.bInterfaceClass = USB_CLASS_VENDOR_SPEC,
+	.bInterfaceSubClass = 0x42,
+	.bInterfaceProtocol = 3,
+	.iInterface = STRING_DATA,
+};
+
+static struct usb_qualifier_descriptor
+ dev_qualifier = {
+	.bLength = sizeof dev_qualifier,
+	.bDescriptorType = USB_DT_QUAL,
+
+	.bcdUSB = __constant_cpu_to_le16(0x0200),
+	.bDeviceClass = USB_CLASS_VENDOR_SPEC,
+
+	.bMaxPacketSize0 = 64,
+	.bNumConfigurations = 1,
+};
+
+struct fastboot_config_desc {
+	struct usb_configuration_descriptor configuration_desc;
+	struct usb_interface_descriptor interface_desc[1];
+	struct usb_endpoint_descriptor data_eps[NUM_ENDPOINTS];
+} __attribute__ ((packed));
+
+static struct fastboot_config_desc
+fastboot_cfg_desc = {
+	.configuration_desc = {
+		.bLength =
+			sizeof(struct usb_configuration_descriptor),
+		.bDescriptorType = USB_DT_CONFIG,
+		.wTotalLength =
+			cpu_to_le16(sizeof
+					(struct fastboot_config_desc)),
+		.bNumInterfaces = 1,
+		.bConfigurationValue = 1,
+		.iConfiguration = STRING_CFG,
+		.bmAttributes =
+			BMATTRIBUTE_SELF_POWERED | BMATTRIBUTE_RESERVED,
+		.bMaxPower = 0xfa
+	},
+	.interface_desc = {
+		{
+			.bLength = sizeof(struct usb_interface_descriptor),
+			.bDescriptorType = USB_DT_INTERFACE,
+			.bInterfaceNumber = 0,
+			.bAlternateSetting = 0,
+			.bNumEndpoints = NUM_ENDPOINTS,
+			.bInterfaceClass = USB_CLASS_VENDOR_SPEC,
+			.bInterfaceSubClass = 0x42,
+			.bInterfaceProtocol = 3,
+			.iInterface = STRING_DATA
+		},
+	},
+	.data_eps = {
+		{
+			.bLength = sizeof(struct usb_endpoint_descriptor),
+			.bDescriptorType = USB_DT_ENDPOINT,
+			.bEndpointAddress = (1) | USB_DIR_OUT,
+			.bmAttributes = USB_ENDPOINT_XFER_BULK,
+			.wMaxPacketSize = cpu_to_le16(64),
+			.bInterval = 0xFF,
+		},
+		{
+			.bLength = sizeof(struct usb_endpoint_descriptor),
+			.bDescriptorType = USB_DT_ENDPOINT,
+			.bEndpointAddress = (2) | USB_DIR_IN,
+			.bmAttributes = USB_ENDPOINT_XFER_BULK,
+			.wMaxPacketSize = cpu_to_le16(64),
+			.bInterval = 0xFF,
+		},
+	},
+};
+
+/*-------------------------------------------------------------------------*/
+
+
+
+static int fastboot_configured_flag = 0;
+
+static void fastboot_init_endpoints(void);
+static void fastboot_event_handler(struct usb_device_instance *device,
+				   usb_device_event_t event, int data)
+{
+#if defined(CONFIG_USBD_HS)
+	int i;
+#endif
+	switch (event) {
+	case DEVICE_RESET:
+	case DEVICE_BUS_INACTIVE:
+		fastboot_configured_flag = 0;
+
+		break;
+	case DEVICE_CONFIGURED:
+		fastboot_configured_flag = 1;
+		break;
+
+	case DEVICE_ADDRESS_ASSIGNED:
+#if defined(CONFIG_USBD_HS)
+		/*
+		 * is_usbd_high_speed routine needs to be defined by
+		 * specific gadget driver
+		 * It returns TRUE if device enumerates at High speed
+		 * Retuns FALSE otherwise
+		 */
+		for (i = 0; i < NUM_ENDPOINTS; i++) {
+			if (((ep_desc_ptrs[i]->bmAttributes &
+			      USB_ENDPOINT_XFERTYPE_MASK) ==
+			     USB_ENDPOINT_XFER_BULK)
+			    && is_usbd_high_speed()) {
+
+				ep_desc_ptrs[i]->wMaxPacketSize = 512;
+			}
+
+			fastboot_ep_instance[i + 1].tx_packetSize =
+			    ep_desc_ptrs[i]->wMaxPacketSize;
+			fastboot_ep_instance[i + 1].rcv_packetSize =
+			    ep_desc_ptrs[i]->wMaxPacketSize;
+		}
+#endif
+		fastboot_init_endpoints();
+
+	default:
+		break;
+	}
+}
+
+/* utility function for converting char* to wide string used by USB */
+static void str2wide (char *str, u16 * wide)
+{
+	int i;
+	for (i = 0; i < strlen (str) && str[i]; i++){
+		#if defined(__LITTLE_ENDIAN)
+			wide[i] = (u16) str[i];
+		#elif defined(__BIG_ENDIAN)
+			wide[i] = ((u16)(str[i])<<8);
+		#else
+			#error "__LITTLE_ENDIAN or __BIG_ENDIAN undefined"
+		#endif
+	}
+}
+
+static struct usb_string_descriptor *fastboot_str_tab[10];
+
+static void fastboot_init_strings (void)
+{
+	struct usb_string_descriptor *string;
+
+	static u8 wstrLang[4] = {4,USB_DT_STRING,0x9,0x4};
+	static u8 wstrManufacturer[2 + 2*(sizeof(FASTBOOT_MANUFACTURER)-1)];
+	static u8 wstrProduct[2 + 2*(sizeof(FASTBOOT_PRODUCT_NAME)-1)];
+	static u8 wstrSerial[2 + 2*(sizeof(serial_number) - 1)];
+	static u8 wstrConfiguration[2 + 2*(sizeof(FASTBOOT_CONFIGURATION_STR)-1)];
+	static u8 wstrDataInterface[2 + 2*(sizeof(FASTBOOT_DATA_INTERFACE_STR)-1)];
+
+
+
+	fastboot_str_tab[0] =
+		(struct usb_string_descriptor*)wstrLang;
+
+	string = (struct usb_string_descriptor *) wstrManufacturer;
+	string->bLength = sizeof(wstrManufacturer);
+	string->bDescriptorType = USB_DT_STRING;
+	str2wide (FASTBOOT_MANUFACTURER, string->wData);
+	fastboot_str_tab[STRING_MANUFACTURER]=string;
+
+
+	string = (struct usb_string_descriptor *) wstrProduct;
+	string->bLength = sizeof(wstrProduct);
+	string->bDescriptorType = USB_DT_STRING;
+	str2wide (FASTBOOT_PRODUCT_NAME, string->wData);
+	fastboot_str_tab[STRING_PRODUCT]=string;
+
+
+	string = (struct usb_string_descriptor *) wstrSerial;
+	string->bLength = sizeof(wstrSerial);
+	string->bDescriptorType = USB_DT_STRING;
+	str2wide (serial_number, string->wData);
+	fastboot_str_tab[STRING_SERIALNUMBER]=string;
+
+	string = (struct usb_string_descriptor *) wstrConfiguration;
+	string->bLength = sizeof(wstrConfiguration);
+	string->bDescriptorType = USB_DT_STRING;
+	str2wide (FASTBOOT_CONFIGURATION_STR, string->wData);
+	fastboot_str_tab[STRING_CFG]=string;
+
+	string = (struct usb_string_descriptor *) wstrDataInterface;
+	string->bLength = sizeof(wstrDataInterface);
+	string->bDescriptorType = USB_DT_STRING;
+	str2wide (FASTBOOT_DATA_INTERFACE_STR, string->wData);
+	fastboot_str_tab[STRING_DATA]=string;
+
+	/* Now, initialize the string table for ep0 handling */
+	usb_strings = fastboot_str_tab;
+}
+#define init_wMaxPacketSize(x)	le16_to_cpu(get_unaligned(\
+			&ep_desc_ptrs[(x) - 1]->wMaxPacketSize));
+
+static void fastboot_init_instances(void)
+{
+	int i;
+
+	/* initialize device instance */
+	memset(fastboot_dev_instance, 0, sizeof(struct usb_device_instance));
+	fastboot_dev_instance->device_state = STATE_INIT;
+	fastboot_dev_instance->device_descriptor = &device_desc;
+#if defined(CONFIG_USBD_HS)
+	fastboot_dev_instance->qualifier_descriptor = &dev_qualifier;
+#endif
+	fastboot_dev_instance->event = fastboot_event_handler;
+	fastboot_dev_instance->bus = fastboot_bus_instance;
+	fastboot_dev_instance->configurations = 1;
+	fastboot_dev_instance->configuration_instance_array =
+	    &fastboot_cfg_instance;
+
+	/* initialize bus instance */
+	memset(fastboot_bus_instance, 0, sizeof(struct usb_bus_instance));
+	fastboot_bus_instance->device = fastboot_dev_instance;
+	fastboot_bus_instance->endpoint_array = fastboot_ep_instance;
+	fastboot_bus_instance->max_endpoints = 1;
+	fastboot_bus_instance->maxpacketsize = 64;
+	fastboot_bus_instance->serial_number_str = serial_number;
+
+	/* configuration instance */
+	memset(&fastboot_cfg_instance, 0,
+	       sizeof(struct usb_configuration_instance));
+	fastboot_cfg_instance.interfaces = 1;
+	fastboot_cfg_instance.configuration_descriptor =
+	    (struct usb_configuration_descriptor *)
+	    &fastboot_cfg_desc;
+	fastboot_cfg_instance.interface_instance_array =
+	    fastboot_intf_instance;
+
+	/* interface instance */
+	memset(fastboot_intf_instance, 0,
+	       sizeof(struct usb_interface_instance));
+	fastboot_intf_instance->alternates = 1;
+	fastboot_intf_instance->alternates_instance_array =
+	    fastboot_alternate_instance;
+
+	/* alternates instance */
+	memset(fastboot_alternate_instance, 0,
+	       sizeof(struct usb_alternate_instance));
+	fastboot_alternate_instance->interface_descriptor = &data_intf;
+	fastboot_alternate_instance->endpoints = NUM_ENDPOINTS;
+	fastboot_alternate_instance->endpoints_descriptor_array = ep_desc_ptrs;
+
+	/* endpoint instances */
+	memset(&fastboot_ep_instance[0], 0,
+	       sizeof(struct usb_endpoint_instance));
+	fastboot_ep_instance[0].endpoint_address = 0;
+	fastboot_ep_instance[0].rcv_packetSize = 64;
+	fastboot_ep_instance[0].rcv_attributes = USB_ENDPOINT_XFER_CONTROL;
+	fastboot_ep_instance[0].tx_packetSize = 64;
+	fastboot_ep_instance[0].tx_attributes = USB_ENDPOINT_XFER_CONTROL;
+	udc_setup_ep(fastboot_dev_instance, 0,
+		     &fastboot_ep_instance[0]);
+
+	for (i = 1; i <= NUM_ENDPOINTS; i++) {
+		memset(&fastboot_ep_instance[i], 0,
+		       sizeof(struct usb_endpoint_instance));
+
+		fastboot_ep_instance[i].endpoint_address =
+		    ep_desc_ptrs[i - 1]->bEndpointAddress;
+
+		fastboot_ep_instance[i].rcv_attributes =
+		    ep_desc_ptrs[i - 1]->bmAttributes;
+
+		fastboot_ep_instance[i].rcv_packetSize =
+		    init_wMaxPacketSize(i);
+
+		fastboot_ep_instance[i].tx_attributes =
+		    ep_desc_ptrs[i - 1]->bmAttributes;
+
+		fastboot_ep_instance[i].tx_packetSize =
+		    init_wMaxPacketSize(i);
+
+		fastboot_ep_instance[i].tx_attributes =
+		    ep_desc_ptrs[i - 1]->bmAttributes;
+
+		urb_link_init(&fastboot_ep_instance[i].rcv);
+		urb_link_init(&fastboot_ep_instance[i].rdy);
+		urb_link_init(&fastboot_ep_instance[i].tx);
+		urb_link_init(&fastboot_ep_instance[i].done);
+
+		if (fastboot_ep_instance[i].endpoint_address & USB_DIR_IN)
+			fastboot_ep_instance[i].tx_urb =
+			    usbd_alloc_urb(fastboot_dev_instance,
+					   &fastboot_ep_instance[i]);
+		else
+			fastboot_ep_instance[i].rcv_urb =
+			    usbd_alloc_urb(fastboot_dev_instance,
+					   &fastboot_ep_instance[i]);
+	}
+}
+
+static void fastboot_init_endpoints(void)
+{
+	int i;
+
+	fastboot_bus_instance->max_endpoints = NUM_ENDPOINTS + 1;
+	for (i = 1; i <= NUM_ENDPOINTS; i++) {
+		udc_setup_ep(fastboot_dev_instance, i,
+			     &fastboot_ep_instance[i]);
+	}
+}
+
+struct usb_endpoint_instance * fastboot_get_out_ep(void)
+{
+	int i;
+	int ep_addr;
+
+	for (i = 1; i <= NUM_ENDPOINTS; i++) {
+		ep_addr = fastboot_ep_instance[i].endpoint_address;
+		if ((ep_addr != 0) && ((ep_addr & 0x80) == 0))
+			return &fastboot_ep_instance[i];
+	}
+
+	serial_printf("no out endpoint for fastboot\n");
+	return NULL;
+}
+
+struct usb_endpoint_instance * fastboot_get_in_ep(void)
+{
+	int i;
+
+	for (i = 1; i <= NUM_ENDPOINTS; i++) {
+		if (fastboot_ep_instance[i].endpoint_address & USB_DIR_IN)
+			return &fastboot_ep_instance[i];
+	}
+
+	serial_printf("no in endpoint for fastboot\n");
+	return NULL;
+
+}
+
+int fastboot_configured (void)
+{
+	return fastboot_configured_flag;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * Initialize the usb client port.
+ *
+ */
+int drv_fastboot_init(void)
+{
+	ep_desc_ptrs[0] = &fastboot_cfg_desc.data_eps[0];
+	ep_desc_ptrs[1] = &fastboot_cfg_desc.data_eps[1];
+
+	/* Now, set up USB controller and infrastructure */
+
+	fastboot_init_strings ();
+	fastboot_init_instances();
+
+	fastboot_init_endpoints();
+
+	udc_startup_events(fastboot_dev_instance);	/* Enable dev, init udc pointers */
+	udc_connect();		/* Enable pullup for host detection */
+
+	return 0;
+}
+
diff --git a/drivers/usb/gadget/fastboot.c b/drivers/usb/gadget/fastboot.c
new file mode 100644
index 0000000000..21aaa0502b
--- /dev/null
+++ b/drivers/usb/gadget/fastboot.c
@@ -0,0 +1,986 @@
+/*
+ * Copyright (c) 2009, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+#include <common.h>
+#include <asm/errno.h>
+#include <usbdescriptors.h>
+#include <usbdevice.h>
+#include <linux/ctype.h>
+#include <malloc.h>
+#include <command.h>
+#include <nand.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <jffs2/jffs2.h>
+#include <asm/types.h>
+#include <asm/io.h>
+#include <android/android_boot.h>
+#include <android/android_bootimg.h>
+#include <android/boot_mode.h>
+#include <asm/arch/rda_sys.h>
+#include "fastboot.h"
+#include <mmc.h>
+#include <mmc/sparse.h>
+#include <mmc/mmcpart.h>
+#if defined(CONFIG_MUSB_UDC)
+#include <usb/musb_udc.h>
+#else
+#error "no usb device controller"
+#endif
+
+//#define DEBUG
+#ifdef DEBUG
+#define fb_dbg(fmt, args...) serial_printf(fmt, ##args)
+#else
+#define fb_dbg(fmt, args...) do {} while(0)
+#endif
+
+#define fb_info(fmt, args...) serial_printf(fmt, ##args)
+
+#ifdef FLASH_PAGE_SIZE
+#undef FLASH_PAGE_SIZE
+#endif
+#define FLASH_PAGE_SIZE 2048
+
+/** implemented in cmd_misc.c */
+extern int load_boot_from_nand(void);
+extern int load_boot_from_mmc(void);
+
+struct fastboot_cmd {
+	struct fastboot_cmd *next;
+	const char *prefix;
+	unsigned prefix_len;
+	void (*handle) (const char *arg, void *data, loff_t sz);
+};
+
+struct fastboot_var {
+	struct fastboot_var *next;
+	const char *name;
+	const char *value;
+};
+
+static struct fastboot_cmd *cmdlist;
+
+static void fastboot_register(const char *prefix,
+			      void (*handle) (const char *arg, void *data,
+					      loff_t sz))
+{
+	struct fastboot_cmd *cmd;
+	cmd = malloc(sizeof(*cmd));
+	if (cmd) {
+		cmd->prefix = prefix;
+		cmd->prefix_len = strlen(prefix);
+		cmd->handle = handle;
+		cmd->next = cmdlist;
+		cmdlist = cmd;
+	}
+}
+
+static struct fastboot_var *varlist;
+
+static void fastboot_publish(const char *name, const char *value)
+{
+	struct fastboot_var *var;
+	var = malloc(sizeof(*var));
+	if (var) {
+		var->name = name;
+		var->value = value;
+		var->next = varlist;
+		varlist = var;
+	}
+}
+
+static unsigned char buffer[4096];
+
+static void *download_base;
+static unsigned download_max;
+static unsigned download_size;
+
+enum {
+	STATE_OFFLINE,
+	STATE_COMMAND,
+	STATE_COMPLETE,
+	STATE_EXIT,
+	STATE_ERROR
+};
+
+static unsigned fastboot_state = STATE_OFFLINE;
+
+static void show_progress(unsigned img_size, unsigned xfer)
+{
+	static int step = 0;
+	static unsigned old_size = 0;
+
+	if (img_size != old_size) {
+		old_size = img_size;
+		step = 0;
+	}
+
+	if (step % 64 == 0)
+		fb_info(">");
+	step++;
+	if (step > 2560) {
+		printf("%3d%%\n", (u32) (((u64) xfer * 100) / img_size));
+		step = 0;
+	}
+	if (xfer >= img_size)
+		fb_info("100%% finised\n");
+}
+
+static int usb_read(void *_buf, unsigned len)
+{
+	int count = 0;
+	struct usb_endpoint_instance *ep_out = fastboot_get_out_ep();
+	struct urb *current_urb = NULL;
+	unsigned char *buf = _buf;
+	unsigned total = len;
+
+	if (!fastboot_configured()) {
+		return 0;
+	}
+
+	if (fastboot_state == STATE_ERROR)
+		goto oops;
+
+	if (!ep_out)
+		goto oops;
+
+	fb_dbg("%s, buf 0x%p, len :%d\n", __func__, _buf, len);
+	current_urb = ep_out->rcv_urb;
+	while (len > 0) {
+		int xfer;
+		int maxPktSize = ep_out->rcv_packetSize;
+		int dma = 0;
+
+		xfer = (len > maxPktSize) ? maxPktSize : len;
+		if (xfer == maxPktSize)
+			dma = 1;
+		usbd_setup_urb(current_urb, buf, xfer, dma);
+		udc_irq();
+		if (current_urb->actual_length) {
+			buf += current_urb->actual_length;
+			len -= current_urb->actual_length;
+			count += current_urb->actual_length;
+			if (xfer != current_urb->actual_length)
+				break;
+			show_progress(total, count);
+			current_urb->actual_length = 0;
+		}
+	}
+	current_urb->actual_length = 0;
+	fb_dbg("%s, read :%d\n", __func__, count);
+	return count;
+
+oops:
+	fb_info("fastboot usb read error\n");
+	fastboot_state = STATE_ERROR;
+	return -1;
+}
+
+static int usb_write(void *_buf, unsigned len)
+{
+	struct usb_endpoint_instance *ep_in = fastboot_get_in_ep();
+	struct urb *current_urb = NULL;
+	unsigned char *buf = _buf;
+	int count = 0;
+
+	if (!fastboot_configured()) {
+		return 0;
+	}
+
+	if (fastboot_state == STATE_ERROR)
+		goto oops;
+
+	if (!ep_in)
+		goto oops;
+
+	fb_dbg("%s, len :%d\n", __func__, len);
+	current_urb = ep_in->tx_urb;
+
+	while (len > 0) {
+		int xfer;
+		int maxPktSize = ep_in->tx_packetSize;
+
+		xfer = (len > maxPktSize) ? maxPktSize : len;
+		current_urb->buffer = buf;
+
+		current_urb->actual_length = xfer;
+		fb_dbg("urb actual_len :%d, ep sent, last %d\n",
+		       current_urb->actual_length, ep_in->sent, ep_in->last);
+		if (udc_endpoint_write(ep_in))
+			goto oops;
+		count += xfer;
+		len -= xfer;
+		buf += xfer;
+	}
+	fb_dbg("after write urb actual_len :%d, ep sent, last %d, count:%d\n",
+	       current_urb->actual_length, ep_in->sent, ep_in->last, count);
+
+	return count;
+
+oops:
+	fb_info("fastboot usb write error\n");
+	fastboot_state = STATE_ERROR;
+	return -1;
+}
+
+void fastboot_ack(const char *code, const char *reason)
+{
+	char response[64] = { 0 };
+
+	if (fastboot_state != STATE_COMMAND)
+		return;
+
+	if (reason == 0)
+		reason = "";
+
+	if (strlen(code) + strlen(reason) >= 64) {
+		fb_info("%s too long string\r\n", __func__);
+	}
+	sprintf(response, "%s%s", code, reason);
+	fastboot_state = STATE_COMPLETE;
+
+	usb_write(response, strlen(response));
+
+}
+
+void fastboot_fail(const char *reason)
+{
+	fastboot_ack("FAIL", reason);
+}
+
+void fastboot_okay(const char *info)
+{
+	fastboot_ack("OKAY", info);
+}
+
+void fastboot_info(const char *info)
+{
+	char response[64] = { 0 };
+	const char *code = "INFO";
+
+	if (info == 0)
+		info = "";
+
+	if (strlen(code) + strlen(info) >= 64) {
+		fb_info("%s too long string\r\n", __func__);
+	}
+	snprintf(response, 63, "%s%s", code, info);
+
+	usb_write(response, strlen(response));
+}
+
+static void cmd_getvar(const char *arg, void *data, loff_t sz)
+{
+	struct fastboot_var *var;
+	int value_len;
+	char str[60];
+
+	for (var = varlist; var; var = var->next) {
+		if (!strcmp(var->name, arg)) {
+			int index = 0;
+
+			value_len = strlen(var->value);
+			if (value_len < 60) {
+				fastboot_okay(var->value);
+				return;
+			}
+			/* value length > 60(+INFO > 64) */
+			while (value_len) {
+				int xfer = (value_len > 50) ? 50 : value_len;
+
+				memset(str, 0, sizeof(str));
+				strncpy(str, &var->value[index], xfer);
+				fastboot_info(str);
+				value_len -= xfer;
+				index += xfer;
+			}
+			fastboot_okay("");
+			return;
+		}
+	}
+	fastboot_okay("");
+}
+
+static void cmd_download(const char *arg, void *data, loff_t sz)
+{
+	char response[64];
+	unsigned len = simple_strtoul(arg, NULL, 16);
+	int r;
+
+	fb_dbg("%s\n", __func__);
+
+	fb_info("start downloading... length  %d is to %p\n", len, data);
+	download_size = 0;
+	if (len > download_max) {
+		fastboot_fail("data too large");
+		return;
+	}
+
+	sprintf(response, "DATA%08x", len);
+	if (usb_write(response, strlen(response)) < 0)
+		return;
+
+	r = usb_read(download_base, len);
+	if ((r < 0) || (r != len)) {
+		fastboot_state = STATE_ERROR;
+		return;
+	}
+	download_size = len;
+	fb_info("download ok\n");
+	fastboot_okay("");
+	//dump_log(download_base, len);
+}
+
+extern int mtdparts_init_default(void);
+extern int mtdparts_save_ptbl(int need_erase);
+
+#ifdef MTDPARTS_UBI_DEF
+extern int ubi_part_scan(char *part_name);
+extern int ubi_check_default_vols(const char *ubi_default_str);
+extern int ubi_erase_vol(char *vol_name);
+extern int ubi_update_vol(char *vol_name, void *buf, size_t size);
+static int cmd_flash_ubi(const char *arg, void *data, loff_t sz)
+{
+	int ret = 0;
+
+	ret = ubi_part_scan(MTDPARTS_UBI_PART_NAME);
+	if(ret) {
+		fastboot_fail("ubi init failed.");
+		goto exit;
+	}
+
+	ret = ubi_check_default_vols(MTDPARTS_UBI_DEF);
+	if(ret) {
+		fastboot_fail("ubi volumes check failed.");
+		goto exit;
+	}
+
+	fb_info("ready to update ubi volume '%s'\n", arg);
+	ret = ubi_update_vol((char *)arg, data, sz);
+exit:
+	return ret;
+}
+#endif /* MTDPARTS_UBI_DEF */
+static void cmd_flash_nand(const char *arg, void *data, loff_t sz)
+{
+	struct mtd_info *nand;
+	struct mtd_device *dev;
+	struct part_info *part;
+	size_t size = 0;
+	u8 pnum;
+	nand_erase_options_t opts;
+	int ret;
+	unsigned addr = simple_strtoul(arg, NULL, 16);
+	loff_t max_limit = 0;
+	u32 bad_blocks = 0;
+	sparse_header_t *header = (void *)data;
+
+	fb_info("%s, addr: %s date: %p, sz: 0x%llx\n", __func__, arg, data, sz);
+
+	/* use "flash" command for downloading purpose */
+	if (addr && (addr >= PHYS_SDRAM_1) &&
+	    (addr < (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))) {
+		fb_info("in memory, do copy to 0x%x\n", addr);
+		fastboot_okay("");
+		memcpy((void *)addr, download_base, sz);
+		fastboot_state = STATE_EXIT;
+		return;
+	}
+
+	data = download_base;	//previous downloaded date to download_base
+
+#ifdef MTDPARTS_UBI_DEF /* all ubi volumes are in one ubi part */
+	if(strstr(MTDPARTS_UBI_DEF, arg)) {
+		ret = cmd_flash_ubi(arg, data, sz);
+		goto exit;
+	}
+#endif
+
+	ret = find_dev_and_part(arg, &dev, &pnum, &part);
+	if (ret) {
+		fastboot_fail("unknown partition name");
+		return;
+	} else if (dev->id->type != MTD_DEV_TYPE_NAND) {
+		fastboot_fail("mtd dev type error");
+		return;
+	}
+	nand = &nand_info[dev->id->num];
+	fb_info("found part '%s' offset: 0x%llx length: 0x%llx id: %d\n",
+		part->name, part->offset, part->size, dev->id->num);
+
+	memset(&opts, 0, sizeof(opts));
+	opts.offset = (loff_t) part->offset;
+	opts.length = (loff_t) part->size;
+	opts.jffs2 = 0;
+	opts.quiet = 0;
+
+	fb_dbg("opts off  0x%08x\n", (uint32_t) opts.offset);
+	fb_dbg("opts size 0x%08x\n", (uint32_t) opts.length);
+	fb_dbg("nand write size 0x%08x\n", nand->writesize);
+	fb_info("erase 0x%llx bytes to '%s' offset: 0x%llx\n",
+		opts.length, part->name, opts.offset);
+	ret = nand_erase_opts(nand, &opts);
+	if (ret) {
+		fastboot_fail("nand erase error");
+		return;
+	}
+
+	if (!strcmp(part->name, "boot") || !strcmp(part->name, "recovery")) {
+		if (memcmp((void *)data, BOOT_MAGIC, BOOT_MAGIC_SIZE)) {
+			fastboot_fail("image is not a boot image");
+			return;
+		}
+	}
+
+	if (is_power_of_2(nand->writesize))
+		sz = ROUND(sz, nand->writesize);
+	else
+		sz = roundup(sz, nand->writesize);
+	size = sz;
+	max_limit = part->offset + part->size;
+
+	fb_info("writing 0x%x bytes to '%s' offset: 0x%llx\n", size,
+		part->name, part->offset);
+	header = (void *)data;
+	if (header->magic != SPARSE_HEADER_MAGIC) {
+		ret =
+		    nand_write_skip_bad_new(nand, part->offset, &size,
+					    max_limit, (u_char *) data,
+					    0,
+					    &bad_blocks);
+	} else {
+		ret = nand_write_unsparse(nand, part->offset, &size, max_limit,
+					  (u_char *) data,
+					  0,
+					  &bad_blocks);
+	}
+
+	/* the mtd partition table is saved in 'bootloader' partition,
+	 * if 'bootloader' is updated, need to re-write the partition table. */
+	if(strcmp(part->name,"bootloader") == 0) {
+		mtdparts_save_ptbl(1);
+	}
+
+#ifdef MTDPARTS_UBI_DEF
+exit:
+#endif
+	if (!ret)
+		fastboot_okay("");
+	else
+		fastboot_fail("flash error");
+	fb_info("flash ok\n");
+}
+
+static block_dev_desc_t *mmc_blkdev;
+void cmd_flash_mmc_img(const char *name, void *data, loff_t sz)
+{
+	disk_partition_t *ptn = 0;
+	u64 size = 0;
+
+	fb_info("flash to mmc part %s\n", name);
+	ptn = partition_find_ptn(name);
+	if (ptn == 0) {
+		fastboot_fail("partition table doesn't exist");
+		return;
+	}
+
+	if (!strcmp(name, "boot") || !strcmp(name, "recovery")) {
+		if (memcmp((void *)data, BOOT_MAGIC, BOOT_MAGIC_SIZE)) {
+			fastboot_fail("image is not a boot image");
+			return;
+		}
+	}
+
+	size = (u64) ptn->size * ptn->blksz;
+	fb_info("partition %s, type %s blocks " LBAFU ", size %llx\n",
+		ptn->name, ptn->type, ptn->size, size);
+	if (ROUND(sz, 512) > size) {
+		fastboot_fail("size too large");
+		return;
+	} else if (partition_write_bytes(mmc_blkdev, ptn, &sz, data)) {
+		fastboot_fail("flash write failure");
+		return;
+	}
+
+	fastboot_okay("");
+	return;
+}
+
+void cmd_flash_mmc_sparse_img(const char *part_name, void *data, loff_t sz)
+{
+	disk_partition_t *ptn;
+	unsigned long long size = 0;
+	int ret;
+
+	fb_info("unsparese and flash part %s\n", part_name);
+	ptn = partition_find_ptn(part_name);
+	if (ptn == 0) {
+		fastboot_fail("partition table doesn't exist");
+		return;
+	}
+
+	size = (u64) ptn->blksz * ptn->size;
+	if (ROUND(sz, 512) > size) {
+		fastboot_fail("size too large");
+		return;
+	}
+
+	ret = partition_unsparse(mmc_blkdev, ptn, data, ptn->start, ptn->size);
+	if (ret) {
+		fastboot_fail("partition cannot unsparse");
+		return;
+	}
+	fastboot_okay("");
+	return;
+}
+
+void cmd_flash_mmc(const char *arg, void *data, loff_t sz)
+{
+	sparse_header_t *sparse_header;
+
+	sparse_header = (sparse_header_t *) data;
+
+	/* Using to judge if ext4 file system */
+	if (sparse_header->magic != SPARSE_HEADER_MAGIC)
+		cmd_flash_mmc_img(arg, data, sz);
+	else
+		cmd_flash_mmc_sparse_img(arg, data, sz);
+
+	return;
+}
+
+static void cmd_flash(const char *arg, void *data, loff_t sz)
+{
+	if (rda_media_get() == MEDIA_MMC)
+		cmd_flash_mmc(arg, data, sz);
+	else
+		cmd_flash_nand(arg, data, sz);
+}
+
+static void cmd_erase_nand(const char *arg, void *data, unsigned sz)
+{
+	struct mtd_info *nand;
+	struct mtd_device *dev;
+	struct part_info *part;
+	u8 pnum;
+	nand_erase_options_t opts;
+	int ret;
+
+	fb_info("erase part: %s\n", arg);
+
+#ifdef MTDPARTS_UBI_DEF /* all ubi volumes are in one ubi part */
+	if(strstr(MTDPARTS_UBI_DEF, arg)) {
+		ubi_part_scan(MTDPARTS_UBI_PART_NAME);
+		ret = ubi_erase_vol((char *)arg);
+		if(ret)
+			fastboot_fail("ubi volume erase error");
+		else
+			fastboot_okay("");
+		return;
+	}
+#endif
+
+	ret = find_dev_and_part(arg, &dev, &pnum, &part);
+	if (ret) {
+		fastboot_fail("unknown partition name");
+		return;
+	} else if (dev->id->type != MTD_DEV_TYPE_NAND) {
+		fastboot_fail("mtd dev type error");
+		return;
+	}
+	nand = &nand_info[dev->id->num];
+	fb_info("found part '%s' offset: 0x%llx length: 0x%llx id: %d\n",
+		part->name, part->offset, part->size, dev->id->num);
+
+	memset(&opts, 0, sizeof(opts));
+	opts.offset = (loff_t) part->offset;
+	opts.length = (loff_t) part->size;
+	opts.jffs2 = 0;
+	opts.quiet = 0;
+
+	fb_dbg("opts off  0x%08x\n", (uint32_t) opts.offset);
+	fb_dbg("opts size 0x%08x\n", (uint32_t) opts.length);
+	fb_dbg("nand write size 0x%08x\n", nand->writesize);
+	ret = nand_erase_opts(nand, &opts);
+	if (ret)
+		fastboot_fail("nand erase error");
+	else
+		fastboot_okay("");
+}
+
+static void cmd_erase_mmc(const char *arg, void *data, loff_t sz)
+{
+	int ret;
+	disk_partition_t *ptn;
+	lbaint_t blkcnt;
+
+	fb_info("erase part: %s\n", arg);
+	ptn = partition_find_ptn(arg);
+	if (!ptn) {
+		fastboot_fail("partition table doesn't exist");
+		return;
+	}
+
+	blkcnt = ptn->size;
+	fb_info("erase mmc from %#x, blocks %#x\n",
+				(uint32_t)ptn->start, (uint32_t)blkcnt);
+	ret = partition_erase_blks(mmc_blkdev, ptn, &blkcnt);
+	if (ret || blkcnt != ptn->size) {
+		fastboot_fail("partition erase failed");
+		return;
+	}
+	fastboot_okay("");
+}
+
+static void cmd_erase(const char *arg, void *data, loff_t sz)
+{
+	if (rda_media_get() == MEDIA_MMC)
+		return cmd_erase_mmc(arg, data, sz);
+	else
+		return cmd_erase_nand(arg, data, sz);
+}
+
+static unsigned char raw_header[2048];
+
+static void cmd_boot(const char *arg, void *data, loff_t sz)
+{
+	boot_img_hdr *hdr = (boot_img_hdr *) raw_header;
+	unsigned kernel_actual;
+	unsigned ramdisk_actual;
+	char *cmdline;
+
+	fb_info("%s, arg: %s, data: %p, sz: 0x%llx\n", __func__, arg, data, sz);
+	memcpy(raw_header, data, 2048);
+	if (memcmp(hdr->magic, BOOT_MAGIC, BOOT_MAGIC_SIZE)) {
+		fb_info("boot image headr: %s\n", hdr->magic);
+		fastboot_fail("bad boot image header");
+		return;
+	}
+	kernel_actual = ROUND(hdr->kernel_size, FLASH_PAGE_SIZE);
+	if (kernel_actual <= 0) {
+		fastboot_fail("kernel image should not be zero");
+		return;
+	}
+	ramdisk_actual = ROUND(hdr->ramdisk_size, FLASH_PAGE_SIZE);
+	if (ramdisk_actual < 0) {
+		fastboot_fail("ramdisk size error");
+		return;
+	}
+
+	memcpy((void *)hdr->kernel_addr, (void *)data + FLASH_PAGE_SIZE,
+	       kernel_actual);
+	memcpy((void *)hdr->ramdisk_addr,
+	       (void *)data + FLASH_PAGE_SIZE + kernel_actual, ramdisk_actual);
+
+	fb_info("kernel @0x%08x (0x%08x bytes)\n", hdr->kernel_addr,
+		kernel_actual);
+	fb_info("ramdisk @0x%08x (0x%08x bytes)\n", hdr->ramdisk_addr,
+		ramdisk_actual);
+	//set boot environment
+	if (hdr->cmdline[0]) {
+		cmdline = (char *)hdr->cmdline;
+	} else {
+		cmdline = getenv("bootargs");
+	}
+
+	fb_info("cmdline %s\n", cmdline);
+	fastboot_okay("");
+	udc_power_off();
+	creat_atags(hdr->tags_addr, cmdline, hdr->ramdisk_addr,
+		    hdr->ramdisk_size);
+
+	cleanup_before_linux();
+	boot_linux(hdr->kernel_addr, hdr->tags_addr);
+}
+
+extern int do_cboot(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[]);
+
+static void cmd_continue(const char *arg, void *data, loff_t sz)
+{
+	fb_info("continue....\n");
+	fastboot_okay("");
+	udc_power_off();
+	fastboot_state = STATE_EXIT;
+	//do_cboot(NULL, 0, 1, NULL);
+	//normal_mode();
+}
+
+static void cmd_reboot(const char *arg, void *data, loff_t sz)
+{
+	fb_info("reboot....\n");
+	fastboot_okay("");
+	mdelay(10);
+	udc_power_off();
+	fastboot_state = STATE_EXIT;
+	rda_reboot(REBOOT_TO_NORMAL_MODE);
+}
+
+static void cmd_reboot_bootloader(const char *arg, void *data, loff_t sz)
+{
+	fb_info("reboot to bootloader....\n");
+	fastboot_okay("");
+	mdelay(10);
+	udc_power_off();
+	fastboot_state = STATE_EXIT;
+	rda_reboot(REBOOT_TO_FASTBOOT_MODE);
+}
+
+static void cmd_powerdown(const char *arg, void *data, loff_t sz)
+{
+	fb_info("power down....\n");
+	fastboot_okay("");
+	fastboot_state = STATE_EXIT;
+	//power_down_devices(0);
+}
+
+static void fastboot_command_loop(void)
+{
+	struct fastboot_cmd *cmd;
+	int r;
+	fb_dbg("fastboot: processing commands\n");
+
+again:
+	while ((fastboot_state != STATE_ERROR)
+	       && (fastboot_state != STATE_EXIT)) {
+		memset(buffer, 0, 64);
+		r = usb_read(buffer, 64);
+		if (r < 0)
+			break;
+		buffer[r] = 0;
+		fb_dbg("fastboot: %s, r:%d\n", buffer, r);
+
+		for (cmd = cmdlist; cmd; cmd = cmd->next) {
+			fb_dbg("cmd list :%s \n", cmd->prefix);
+			if (memcmp(buffer, cmd->prefix, cmd->prefix_len))
+				continue;
+			fastboot_state = STATE_COMMAND;
+			cmd->handle((const char *)buffer + cmd->prefix_len,
+				    (void *)download_base, download_size);
+			if (fastboot_state == STATE_COMMAND)
+				fastboot_fail("unknown reason");
+			if (fastboot_state == STATE_EXIT)
+				goto fb_done;
+			goto again;
+		}
+
+		fastboot_fail("unknown command");
+	}
+	fastboot_state = STATE_OFFLINE;
+fb_done:
+	fb_dbg("fastboot: done\n");
+}
+
+static int fastboot_handler(void *arg)
+{
+	while (fastboot_state != STATE_EXIT) {
+		fastboot_command_loop();
+	}
+	return 0;
+}
+
+static int fastboot_start(void *base, unsigned size)
+{
+	char *parts;
+
+	fb_info("fastboot start\n");
+
+	download_base = base;
+	download_max = size;
+
+	fastboot_register("getvar:", cmd_getvar);
+	fastboot_register("download:", cmd_download);
+	fastboot_register("flash:", cmd_flash);
+	fastboot_register("erase:", cmd_erase);
+	fastboot_register("boot", cmd_boot);
+	fastboot_register("reboot", cmd_reboot);
+	fastboot_register("powerdown", cmd_powerdown);
+	fastboot_register("continue", cmd_continue);
+	fastboot_register("reboot-bootloader", cmd_reboot_bootloader);
+
+	fastboot_publish("version", "1.0");
+
+	parts = getenv("mtdparts");
+	fastboot_publish("mtd", parts);
+
+	fastboot_handler(0);
+	return 0;
+}
+
+/*
+ * Since interrupt handling has not yet been implemented, we use this function
+ * to handle polling.  .
+ */
+static void fastboot_wait_for_configed(void)
+{
+	/* New interrupts? */
+	while (!fastboot_configured())
+		udc_irq();
+}
+
+void boot_linux_from_mem(void *data)
+{
+	boot_img_hdr *hdr = (boot_img_hdr *) data;
+	unsigned kernel_actual;
+	unsigned ramdisk_actual;
+	char *cmdline;
+
+	fb_info("%s, data: %p\n", __func__, data);
+	if (memcmp(hdr->magic, BOOT_MAGIC, BOOT_MAGIC_SIZE)) {
+		fb_info("boot image headr: %s\n", hdr->magic);
+		fastboot_fail("bad boot image header");
+		return;
+	}
+	kernel_actual = ROUND(hdr->kernel_size, FLASH_PAGE_SIZE);
+	if (kernel_actual <= 0) {
+		fastboot_fail("kernel image should not be zero");
+		return;
+	}
+	ramdisk_actual = ROUND(hdr->ramdisk_size, FLASH_PAGE_SIZE);
+	if (ramdisk_actual < 0) {
+		fastboot_fail("ramdisk size error");
+		return;
+	}
+
+	memcpy((void *)hdr->kernel_addr, (void *)data + FLASH_PAGE_SIZE,
+	       kernel_actual);
+	memcpy((void *)hdr->ramdisk_addr,
+	       (void *)data + FLASH_PAGE_SIZE + kernel_actual, ramdisk_actual);
+
+	fb_info("kernel @0x%08x (0x%08x bytes)\n", hdr->kernel_addr,
+		kernel_actual);
+	fb_info("ramdisk @0x%08x (0x%08x bytes)\n", hdr->ramdisk_addr,
+		ramdisk_actual);
+	//set boot environment
+	if (hdr->cmdline[0]) {
+		cmdline = (char *)hdr->cmdline;
+	} else {
+		cmdline = getenv("bootargs");
+	}
+
+	fb_info("cmdline %s\n", cmdline);
+	creat_atags(hdr->tags_addr, cmdline, hdr->ramdisk_addr,
+		    hdr->ramdisk_size);
+
+	cleanup_before_linux();
+	boot_linux(hdr->kernel_addr, hdr->tags_addr);
+}
+
+void boot_linux_from_nand(void)
+{
+    if(load_boot_from_nand() == CMD_RET_FAILURE) {
+        fb_info("fastboot load_boot_from_nand fail\n");
+        return;
+    }
+	/* boot from mem */
+	boot_linux_from_mem((void *)SCRATCH_ADDR);
+}
+
+void boot_linux_from_mmc(void)
+{
+    if(load_boot_from_mmc() == CMD_RET_FAILURE) {
+        fb_info("fastboot load_boot_from_mmc fail\n");
+        return;
+    }
+	/* boot from mem */
+	boot_linux_from_mem((void *)SCRATCH_ADDR);
+}
+
+void boot_linux_from_flash(void)
+{
+	enum media_type media = rda_media_get();
+
+	if (media == MEDIA_MMC)
+		boot_linux_from_mmc();
+	else if ((media == MEDIA_NAND) || (media == MEDIA_SPINAND))
+		boot_linux_from_nand();
+	else
+		fb_info("fastboot can't find media\n");
+}
+
+#if defined(CONFIG_CMD_FASTBOOT)
+extern int drv_fastboot_init(void);
+
+int do_fastboot(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
+{
+	int ret;
+	enum media_type media = rda_media_get();
+
+	udc_init();
+	drv_fastboot_init();
+
+	if ((media == MEDIA_NAND) || (media == MEDIA_SPINAND)) {
+		ret = mtdparts_init_default();
+		if(ret) {
+			fb_info("nand format partition fail %d\n", ret);
+			return -1;
+		}
+	}
+
+	if (media == MEDIA_MMC) {
+		ret = mmc_parts_format();
+		if (ret) {
+			fb_info("mmc format partition fail %d\n", ret);
+			return -1;
+		}
+		mmc_blkdev = get_dev_by_name(CONFIG_MMC_DEV_NAME);
+	}
+	fastboot_wait_for_configed();
+
+	fastboot_start((void *)SCRATCH_ADDR, FB_DOWNLOAD_BUF_SIZE);
+	return 0;
+}
+
+U_BOOT_CMD(fastboot, 1, 1, do_fastboot,
+	   "android fastboot protocol", "flash image to nand");
+
+int do_abootf(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
+{
+	boot_linux_from_flash();
+	return 1;
+}
+
+U_BOOT_CMD(abootf, 1, 0, do_abootf,
+	   "boot android boot.img from flash",
+	   "    - boot android boot.image from flash");
+
+int do_abootm(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
+{
+	ulong offset = 0;
+	if (argc >= 2) {
+		offset = simple_strtoul(argv[1], NULL, 16);
+	}
+	boot_linux_from_mem((void *)offset);
+	return 1;
+}
+
+U_BOOT_CMD(abootm, 2, 0, do_abootm,
+	   "boot android boot.img from memory",
+	   "[ off ]\n"
+	   "    - boot android boot.image from memory with offset 'off'");
+
+#endif
diff --git a/drivers/usb/gadget/fastboot.h b/drivers/usb/gadget/fastboot.h
new file mode 100644
index 0000000000..123f523b90
--- /dev/null
+++ b/drivers/usb/gadget/fastboot.h
@@ -0,0 +1,8 @@
+#ifndef __FASTBOOT_H__

+#define __FASTBOOT_H__

+

+extern struct usb_endpoint_instance * fastboot_get_out_ep(void);

+extern struct usb_endpoint_instance * fastboot_get_in_ep(void);

+extern int fastboot_configured (void);

+

+#endif

diff --git a/drivers/usb/gadget/s3c_udc_otg.c b/drivers/usb/gadget/s3c_udc_otg.c
index 1050a98b6c..3fdfdf7af0 100644
--- a/drivers/usb/gadget/s3c_udc_otg.c
+++ b/drivers/usb/gadget/s3c_udc_otg.c
@@ -30,13 +30,14 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  *
  */
-
+#undef DEBUG
 #include <common.h>
 #include <asm/errno.h>
 #include <linux/list.h>
 #include <malloc.h>
 
 #include <linux/usb/ch9.h>
+#include <usbdescriptors.h>
 #include <linux/usb/gadget.h>
 
 #include <asm/byteorder.h>
@@ -53,19 +54,11 @@
 
 #define OTG_DMA_MODE		1
 
-#undef DEBUG_S3C_UDC_SETUP
-#undef DEBUG_S3C_UDC_EP0
-#undef DEBUG_S3C_UDC_ISR
-#undef DEBUG_S3C_UDC_OUT_EP
-#undef DEBUG_S3C_UDC_IN_EP
-#undef DEBUG_S3C_UDC
-
-/* #define DEBUG_S3C_UDC_SETUP */
-/* #define DEBUG_S3C_UDC_EP0 */
-/* #define DEBUG_S3C_UDC_ISR */
-/* #define DEBUG_S3C_UDC_OUT_EP */
-/* #define DEBUG_S3C_UDC_IN_EP */
-/* #define DEBUG_S3C_UDC */
+#define DEBUG_SETUP 0
+#define DEBUG_EP0 0
+#define DEBUG_ISR 0
+#define DEBUG_OUT_EP 0
+#define DEBUG_IN_EP 0
 
 #include <usb/s3c_udc.h>
 
@@ -132,6 +125,19 @@ static void nuke(struct s3c_ep *ep, int status);
 static int s3c_udc_set_halt(struct usb_ep *_ep, int value);
 static void s3c_udc_set_nak(struct s3c_ep *ep);
 
+void set_udc_gadget_private_data(void *p)
+{
+	debug_cond(DEBUG_SETUP != 0,
+		   "%s: the_controller: 0x%p, p: 0x%p\n", __func__,
+		   the_controller, p);
+	the_controller->gadget.dev.device_data = p;
+}
+
+void *get_udc_gadget_private_data(struct usb_gadget *gadget)
+{
+	return gadget->dev.device_data;
+}
+
 static struct usb_ep_ops s3c_ep_ops = {
 	.enable = s3c_ep_enable,
 	.disable = s3c_ep_disable,
@@ -216,7 +222,7 @@ void otg_phy_off(struct s3c_udc *dev)
  */
 static void udc_disable(struct s3c_udc *dev)
 {
-	DEBUG_SETUP("%s: %p\n", __func__, dev);
+	debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
 
 	udc_set_address(dev, 0);
 
@@ -234,7 +240,7 @@ static void udc_reinit(struct s3c_udc *dev)
 {
 	unsigned int i;
 
-	DEBUG_SETUP("%s: %p\n", __func__, dev);
+	debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
 
 	/* device/ep0 records init */
 	INIT_LIST_HEAD(&dev->gadget.ep_list);
@@ -265,12 +271,13 @@ static void udc_reinit(struct s3c_udc *dev)
  */
 static int udc_enable(struct s3c_udc *dev)
 {
-	DEBUG_SETUP("%s: %p\n", __func__, dev);
+	debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
 
 	otg_phy_init(dev);
 	reconfig_usbd();
 
-	DEBUG_SETUP("S3C USB 2.0 OTG Controller Core Initialized : 0x%x\n",
+	debug_cond(DEBUG_SETUP != 0,
+		   "S3C USB 2.0 OTG Controller Core Initialized : 0x%x\n",
 		    readl(&reg->gintmsk));
 
 	dev->gadget.speed = USB_SPEED_UNKNOWN;
@@ -287,7 +294,7 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
 	int retval = 0;
 	unsigned long flags;
 
-	DEBUG_SETUP("%s: %s\n", __func__, "no name");
+	debug_cond(DEBUG_SETUP != 0, "%s: %s\n", __func__, "no name");
 
 	if (!driver
 	    || (driver->speed != USB_SPEED_FULL
@@ -311,7 +318,8 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
 
 	retval = driver->bind(&dev->gadget);
 	if (retval) {
-		DEBUG_SETUP("%s: bind to driver --> error %d\n",
+		debug_cond(DEBUG_SETUP != 0,
+			   "%s: bind to driver --> error %d\n",
 			    dev->gadget.name, retval);
 		dev->driver = 0;
 		return retval;
@@ -319,7 +327,8 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
 
 	enable_irq(IRQ_OTG);
 
-	DEBUG_SETUP("Registered gadget driver %s\n", dev->gadget.name);
+	debug_cond(DEBUG_SETUP != 0,
+		   "Registered gadget driver %s\n", dev->gadget.name);
 	udc_enable(dev);
 
 	return 0;
@@ -377,7 +386,7 @@ static void done(struct s3c_ep *ep, struct s3c_request *req, int status)
 	/* don't modify queue heads during completion callback */
 	ep->stopped = 1;
 
-#ifdef DEBUG_S3C_UDC
+#ifdef DEBUG
 	printf("calling complete callback\n");
 	{
 		int i, len = req->req.length;
@@ -671,7 +680,7 @@ static struct usb_request *s3c_alloc_request(struct usb_ep *ep,
 
 	debug("%s: %s %p\n", __func__, ep->name, ep);
 
-	req = kmalloc(sizeof *req, gfp_flags);
+	req = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*req));
 	if (!req)
 		return 0;
 
@@ -865,7 +874,8 @@ int s3c_udc_probe(struct s3c_plat_otg_data *pdata)
 	the_controller = dev;
 
 	for (i = 0; i < S3C_MAX_ENDPOINTS+1; i++) {
-		dev->dma_buf[i] = kmalloc(DMA_BUFFER_SIZE, GFP_KERNEL);
+		dev->dma_buf[i] = memalign(CONFIG_SYS_CACHELINE_SIZE,
+					   DMA_BUFFER_SIZE);
 		dev->dma_addr[i] = (dma_addr_t) dev->dma_buf[i];
 		invalidate_dcache_range((unsigned long) dev->dma_buf[i],
 					(unsigned long) (dev->dma_buf[i]
diff --git a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
index afd4931fa0..4be603783c 100644
--- a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
+++ b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
@@ -53,7 +53,7 @@ static inline void s3c_udc_ep0_zlp(struct s3c_udc *dev)
 	writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
 	       &reg->in_endp[EP0_CON].diepctl);
 
-	DEBUG_EP0("%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
+	debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
 		__func__, readl(&reg->in_endp[EP0_CON].diepctl));
 	dev->ep0state = WAIT_FOR_IN_COMPLETE;
 }
@@ -62,7 +62,8 @@ void s3c_udc_pre_setup(void)
 {
 	u32 ep_ctrl;
 
-	debug_cond(DEBUG_IN_EP, "%s : Prepare Setup packets.\n", __func__);
+	debug_cond(DEBUG_IN_EP,
+		   "%s : Prepare Setup packets.\n", __func__);
 
 	invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr,
 				(unsigned long) usb_ctrl_dma_addr
@@ -75,9 +76,9 @@ void s3c_udc_pre_setup(void)
 	ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
 	writel(ep_ctrl|DEPCTL_EPENA, &reg->out_endp[EP0_CON].doepctl);
 
-	DEBUG_EP0("%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
+	debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
 		__func__, readl(&reg->in_endp[EP0_CON].diepctl));
-	DEBUG_EP0("%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
+	debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
 		__func__, readl(&reg->out_endp[EP0_CON].doepctl));
 
 }
@@ -86,9 +87,9 @@ static inline void s3c_ep0_complete_out(void)
 {
 	u32 ep_ctrl;
 
-	DEBUG_EP0("%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
+	debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
 		__func__, readl(&reg->in_endp[EP0_CON].diepctl));
-	DEBUG_EP0("%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
+	debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
 		__func__, readl(&reg->out_endp[EP0_CON].doepctl));
 
 	debug_cond(DEBUG_IN_EP,
@@ -106,9 +107,9 @@ static inline void s3c_ep0_complete_out(void)
 	writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
 	       &reg->out_endp[EP0_CON].doepctl);
 
-	DEBUG_EP0("%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
+	debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
 		__func__, readl(&reg->in_endp[EP0_CON].diepctl));
-	DEBUG_EP0("%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
+	debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
 		__func__, readl(&reg->out_endp[EP0_CON].doepctl));
 
 }
@@ -145,14 +146,15 @@ static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req)
 	       &reg->out_endp[ep_num].doeptsiz);
 	writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, &reg->out_endp[ep_num].doepctl);
 
-	DEBUG_OUT_EP("%s: EP%d RX DMA start : DOEPDMA = 0x%x,"
-		     "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n"
-		     "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
-		     __func__, ep_num,
-		     readl(&reg->out_endp[ep_num].doepdma),
-		     readl(&reg->out_endp[ep_num].doeptsiz),
-		     readl(&reg->out_endp[ep_num].doepctl),
-		     buf, pktcnt, length);
+	debug_cond(DEBUG_OUT_EP != 0,
+		   "%s: EP%d RX DMA start : DOEPDMA = 0x%x,"
+		   "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n"
+		   "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
+		   __func__, ep_num,
+		   readl(&reg->out_endp[ep_num].doepdma),
+		   readl(&reg->out_endp[ep_num].doeptsiz),
+		   readl(&reg->out_endp[ep_num].doepctl),
+		   buf, pktcnt, length);
 	return 0;
 
 }
@@ -168,7 +170,7 @@ int setdma_tx(struct s3c_ep *ep, struct s3c_request *req)
 	length = req->req.length - req->req.actual;
 
 	if (ep_num == EP0_CON)
-		length = min_t(length, (u32)ep_maxpacket(ep));
+		length = min(length, (u32)ep_maxpacket(ep));
 
 	ep->len = length;
 	ep->dma_buf = buf;
@@ -225,8 +227,9 @@ static void complete_rx(struct s3c_udc *dev, u8 ep_num)
 	u32 *p = the_controller->dma_buf[ep_index(ep)+1];
 
 	if (list_empty(&ep->queue)) {
-		DEBUG_OUT_EP("%s: RX DMA done : NULL REQ on OUT EP-%d\n",
-					__func__, ep_num);
+		debug_cond(DEBUG_OUT_EP != 0,
+			   "%s: RX DMA done : NULL REQ on OUT EP-%d\n",
+			   __func__, ep_num);
 		return;
 
 	}
@@ -249,14 +252,15 @@ static void complete_rx(struct s3c_udc *dev, u8 ep_num)
 	req->req.actual += min(xfer_size, req->req.length - req->req.actual);
 	is_short = (xfer_size < ep->ep.maxpacket);
 
-	DEBUG_OUT_EP("%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
-		     "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n",
-			__func__, ep_num, req->req.actual, req->req.length,
-			is_short, ep_tsr, xfer_size);
+	debug_cond(DEBUG_OUT_EP != 0,
+		   "%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
+		   "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n",
+		   __func__, ep_num, req->req.actual, req->req.length,
+		   is_short, ep_tsr, xfer_size);
 
 	if (is_short || req->req.actual == req->req.length) {
 		if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
-			DEBUG_OUT_EP("	=> Send ZLP\n");
+			debug_cond(DEBUG_OUT_EP != 0, "	=> Send ZLP\n");
 			s3c_udc_ep0_zlp(dev);
 			/* packet will be completed in complete_tx() */
 			dev->ep0state = WAIT_FOR_IN_COMPLETE;
@@ -266,8 +270,9 @@ static void complete_rx(struct s3c_udc *dev, u8 ep_num)
 			if (!list_empty(&ep->queue)) {
 				req = list_entry(ep->queue.next,
 					struct s3c_request, queue);
-				DEBUG_OUT_EP("%s: Next Rx request start...\n",
-					 __func__);
+				debug_cond(DEBUG_OUT_EP != 0,
+					   "%s: Next Rx request start...\n",
+					   __func__);
 				setdma_rx(ep, req);
 			}
 		}
@@ -392,8 +397,9 @@ static void process_ep_in_intr(struct s3c_udc *dev)
 	while (ep_intr) {
 		if (ep_intr & DAINT_IN_EP_INT(1)) {
 			ep_intr_status = readl(&reg->in_endp[ep_num].diepint);
-			debug_cond(DEBUG_IN_EP, "\tEP%d-IN : DIEPINT = 0x%x\n",
-						ep_num, ep_intr_status);
+			debug_cond(DEBUG_IN_EP,
+				   "\tEP%d-IN : DIEPINT = 0x%x\n",
+				   ep_num, ep_intr_status);
 
 			/* Interrupt Clear */
 			writel(ep_intr_status, &reg->in_endp[ep_num].diepint);
@@ -430,16 +436,18 @@ static void process_ep_out_intr(struct s3c_udc *dev)
 	u8 ep_num = 0;
 
 	ep_intr = readl(&reg->daint);
-	DEBUG_OUT_EP("*** %s: EP OUT interrupt : DAINT = 0x%x\n",
-				__func__, ep_intr);
+	debug_cond(DEBUG_OUT_EP != 0,
+		   "*** %s: EP OUT interrupt : DAINT = 0x%x\n",
+		   __func__, ep_intr);
 
 	ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK;
 
 	while (ep_intr) {
 		if (ep_intr & 0x1) {
 			ep_intr_status = readl(&reg->out_endp[ep_num].doepint);
-			DEBUG_OUT_EP("\tEP%d-OUT : DOEPINT = 0x%x\n",
-						ep_num, ep_intr_status);
+			debug_cond(DEBUG_OUT_EP != 0,
+				   "\tEP%d-OUT : DOEPINT = 0x%x\n",
+				   ep_num, ep_intr_status);
 
 			/* Interrupt Clear */
 			writel(ep_intr_status, &reg->out_endp[ep_num].doepint);
@@ -457,7 +465,8 @@ static void process_ep_out_intr(struct s3c_udc *dev)
 
 				if (ep_intr_status &
 				    CTRL_OUT_EP_SETUP_PHASE_DONE) {
-					DEBUG_OUT_EP("SETUP packet arrived\n");
+					debug_cond(DEBUG_OUT_EP != 0,
+						   "SETUP packet arrived\n");
 					s3c_handle_ep0(dev);
 				}
 			} else {
@@ -503,7 +512,8 @@ static int s3c_udc_irq(int irq, void *_dev)
 		usb_status = (readl(&reg->dsts) & 0x6);
 
 		if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
-			debug_cond(DEBUG_ISR, "\t\tFull Speed Detection\n");
+			debug_cond(DEBUG_ISR,
+				   "\t\tFull Speed Detection\n");
 			set_max_pktsize(dev, USB_SPEED_FULL);
 
 		} else {
@@ -571,7 +581,8 @@ static int s3c_udc_irq(int irq, void *_dev)
 
 		} else {
 			reset_available = 1;
-			debug_cond(DEBUG_ISR, "\t\tRESET handling skipped\n");
+			debug_cond(DEBUG_ISR,
+				   "\t\tRESET handling skipped\n");
 		}
 	}
 
@@ -635,7 +646,7 @@ static int s3c_queue(struct usb_ep *_ep, struct usb_request *_req,
 		_req, _req->length, _req->buf,
 		list_empty(&ep->queue), ep->stopped);
 
-#ifdef DEBUG_S3C_UDC
+#ifdef DEBUG
 	{
 		int i, len = _req->length;
 
@@ -662,14 +673,15 @@ static int s3c_queue(struct usb_ep *_ep, struct usb_request *_req,
 		} else if (ep_is_in(ep)) {
 			gintsts = readl(&reg->gintsts);
 			debug_cond(DEBUG_IN_EP,
-				"%s: ep_is_in, S3C_UDC_OTG_GINTSTS=0x%x\n",
-				__func__, gintsts);
+				   "%s: ep_is_in, S3C_UDC_OTG_GINTSTS=0x%x\n",
+				   __func__, gintsts);
 
 			setdma_tx(ep, req);
 		} else {
 			gintsts = readl(&reg->gintsts);
-			DEBUG_OUT_EP("%s:ep_is_out, S3C_UDC_OTG_GINTSTS=0x%x\n",
-				__func__, gintsts);
+			debug_cond(DEBUG_OUT_EP != 0,
+				   "%s:ep_is_out, S3C_UDC_OTG_GINTSTS=0x%x\n",
+				   __func__, gintsts);
 
 			setdma_rx(ep, req);
 		}
@@ -697,7 +709,7 @@ static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req)
 
 	max = ep_maxpacket(ep);
 
-	DEBUG_EP0("%s: max = %d\n", __func__, max);
+	debug_cond(DEBUG_EP0 != 0, "%s: max = %d\n", __func__, max);
 
 	count = setdma_tx(ep, req);
 
@@ -712,10 +724,11 @@ static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req)
 			is_last = 1;
 	}
 
-	DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __func__,
-		  ep->ep.name, count,
-		  is_last ? "/L" : "",
-		  req->req.length - req->req.actual - count, req);
+	debug_cond(DEBUG_EP0 != 0,
+		   "%s: wrote %s %d bytes%s %d left %p\n", __func__,
+		   ep->ep.name, count,
+		   is_last ? "/L" : "",
+		   req->req.length - req->req.actual - count, req);
 
 	/* requests complete when all IN data is in the FIFO */
 	if (is_last) {
@@ -736,8 +749,9 @@ int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max)
 				(unsigned long) ep->dev->dma_buf[ep_index(ep)]
 				+ DMA_BUFFER_SIZE);
 
-	DEBUG_EP0("%s: bytes=%d, ep_index=%d %p\n", __func__,
-		  bytes, ep_index(ep), ep->dev->dma_buf[ep_index(ep)]);
+	debug_cond(DEBUG_EP0 != 0,
+		   "%s: bytes=%d, ep_index=%d %p\n", __func__,
+		   bytes, ep_index(ep), ep->dev->dma_buf[ep_index(ep)]);
 
 	return bytes;
 }
@@ -756,8 +770,9 @@ static void udc_set_address(struct s3c_udc *dev, unsigned char address)
 
 	s3c_udc_ep0_zlp(dev);
 
-	DEBUG_EP0("%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
-		__func__, address, readl(&reg->dcfg));
+	debug_cond(DEBUG_EP0 != 0,
+		   "%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
+		   __func__, address, readl(&reg->dcfg));
 
 	dev->usb_address = address;
 }
@@ -778,8 +793,9 @@ static inline void s3c_udc_ep0_set_stall(struct s3c_ep *ep)
 
 	writel(ep_ctrl, &reg->in_endp[EP0_CON].diepctl);
 
-	DEBUG_EP0("%s: set ep%d stall, DIEPCTL0 = 0x%x\n",
-		__func__, ep_index(ep), &reg->in_endp[EP0_CON].diepctl);
+	debug_cond(DEBUG_EP0 != 0,
+		   "%s: set ep%d stall, DIEPCTL0 = 0x%p\n",
+		   __func__, ep_index(ep), &reg->in_endp[EP0_CON].diepctl);
 	/*
 	 * The application can only set this bit, and the core clears it,
 	 * when a SETUP token is received for this endpoint
@@ -803,8 +819,9 @@ static void s3c_ep0_read(struct s3c_udc *dev)
 		return;
 	}
 
-	DEBUG_EP0("%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
-		__func__, req, req->req.length, req->req.actual);
+	debug_cond(DEBUG_EP0 != 0,
+		   "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
+		   __func__, req, req->req.length, req->req.actual);
 
 	if (req->req.length == 0) {
 		/* zlp for Set_configuration, Set_interface,
@@ -813,8 +830,9 @@ static void s3c_ep0_read(struct s3c_udc *dev)
 		ep->len = 0;
 		s3c_udc_ep0_zlp(dev);
 
-		DEBUG_EP0("%s: req.length = 0, bRequest = %d\n",
-			  __func__, usb_ctrl->bRequest);
+		debug_cond(DEBUG_EP0 != 0,
+			   "%s: req.length = 0, bRequest = %d\n",
+			   __func__, usb_ctrl->bRequest);
 		return;
 	}
 
@@ -836,12 +854,13 @@ static int s3c_ep0_write(struct s3c_udc *dev)
 		req = list_entry(ep->queue.next, struct s3c_request, queue);
 
 	if (!req) {
-		DEBUG_EP0("%s: NULL REQ\n", __func__);
+		debug_cond(DEBUG_EP0 != 0, "%s: NULL REQ\n", __func__);
 		return 0;
 	}
 
-	DEBUG_EP0("%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
-		__func__, req, req->req.length, req->req.actual);
+	debug_cond(DEBUG_EP0 != 0,
+		   "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
+		   __func__, req, req->req.length, req->req.actual);
 
 	if (req->req.length - req->req.actual == ep0_fifo_size) {
 		/* Next write will end with the packet size, */
@@ -854,11 +873,13 @@ static int s3c_ep0_write(struct s3c_udc *dev)
 	if ((ret == 1) && !need_zlp) {
 		/* Last packet */
 		dev->ep0state = WAIT_FOR_COMPLETE;
-		DEBUG_EP0("%s: finished, waiting for status\n", __func__);
+		debug_cond(DEBUG_EP0 != 0,
+			   "%s: finished, waiting for status\n", __func__);
 
 	} else {
 		dev->ep0state = DATA_STATE_XMIT;
-		DEBUG_EP0("%s: not finished\n", __func__);
+		debug_cond(DEBUG_EP0 != 0,
+			   "%s: not finished\n", __func__);
 	}
 
 	return 1;
@@ -873,30 +894,35 @@ int s3c_udc_get_status(struct s3c_udc *dev,
 	u32 ep_ctrl;
 	u32 *p = the_controller->dma_buf[1];
 
-	DEBUG_SETUP("%s: *** USB_REQ_GET_STATUS\n", __func__);
+	debug_cond(DEBUG_SETUP != 0,
+		   "%s: *** USB_REQ_GET_STATUS\n", __func__);
 	printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK);
 	switch (crq->bRequestType & USB_RECIP_MASK) {
 	case USB_RECIP_INTERFACE:
 		g_status = 0;
-		DEBUG_SETUP("\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n",
-			    g_status);
+		debug_cond(DEBUG_SETUP != 0,
+			   "\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n",
+			   g_status);
 		break;
 
 	case USB_RECIP_DEVICE:
 		g_status = 0x1; /* Self powered */
-		DEBUG_SETUP("\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n",
-			    g_status);
+		debug_cond(DEBUG_SETUP != 0,
+			   "\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n",
+			   g_status);
 		break;
 
 	case USB_RECIP_ENDPOINT:
 		if (crq->wLength > 2) {
-			DEBUG_SETUP("\tGET_STATUS:Not support EP or wLength\n");
+			debug_cond(DEBUG_SETUP != 0,
+				   "\tGET_STATUS:Not support EP or wLength\n");
 			return 1;
 		}
 
 		g_status = dev->ep[ep_num].stopped;
-		DEBUG_SETUP("\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n",
-			    g_status);
+		debug_cond(DEBUG_SETUP != 0,
+			   "\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n",
+			   g_status);
 
 		break;
 
@@ -1134,11 +1160,13 @@ static int s3c_udc_clear_feature(struct usb_ep *_ep)
 	ep_num = ep_index(ep);
 
 	dev = ep->dev;
-	DEBUG_SETUP("%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n",
-		__func__, ep_num, ep_is_in(ep), clear_feature_flag);
+	debug_cond(DEBUG_SETUP != 0,
+		   "%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n",
+		   __func__, ep_num, ep_is_in(ep), clear_feature_flag);
 
 	if (usb_ctrl->wLength != 0) {
-		DEBUG_SETUP("\tCLEAR_FEATURE: wLength is not zero.....\n");
+		debug_cond(DEBUG_SETUP != 0,
+			   "\tCLEAR_FEATURE: wLength is not zero.....\n");
 		return 1;
 	}
 
@@ -1146,11 +1174,13 @@ static int s3c_udc_clear_feature(struct usb_ep *_ep)
 	case USB_RECIP_DEVICE:
 		switch (usb_ctrl->wValue) {
 		case USB_DEVICE_REMOTE_WAKEUP:
-			DEBUG_SETUP("\tOFF:USB_DEVICE_REMOTE_WAKEUP\n");
+			debug_cond(DEBUG_SETUP != 0,
+				   "\tOFF:USB_DEVICE_REMOTE_WAKEUP\n");
 			break;
 
 		case USB_DEVICE_TEST_MODE:
-			DEBUG_SETUP("\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n");
+			debug_cond(DEBUG_SETUP != 0,
+				   "\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n");
 			/** @todo Add CLEAR_FEATURE for TEST modes. */
 			break;
 		}
@@ -1159,8 +1189,9 @@ static int s3c_udc_clear_feature(struct usb_ep *_ep)
 		break;
 
 	case USB_RECIP_ENDPOINT:
-		DEBUG_SETUP("\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n",
-				usb_ctrl->wValue);
+		debug_cond(DEBUG_SETUP != 0,
+			   "\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n",
+			   usb_ctrl->wValue);
 
 		if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
 			if (ep_num == 0) {
@@ -1193,11 +1224,13 @@ static int s3c_udc_set_feature(struct usb_ep *_ep)
 	ep_num = ep_index(ep);
 	dev = ep->dev;
 
-	DEBUG_SETUP("%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n",
+	debug_cond(DEBUG_SETUP != 0,
+		   "%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n",
 		    __func__, ep_num);
 
 	if (usb_ctrl->wLength != 0) {
-		DEBUG_SETUP("\tSET_FEATURE: wLength is not zero.....\n");
+		debug_cond(DEBUG_SETUP != 0,
+			   "\tSET_FEATURE: wLength is not zero.....\n");
 		return 1;
 	}
 
@@ -1205,20 +1238,24 @@ static int s3c_udc_set_feature(struct usb_ep *_ep)
 	case USB_RECIP_DEVICE:
 		switch (usb_ctrl->wValue) {
 		case USB_DEVICE_REMOTE_WAKEUP:
-			DEBUG_SETUP("\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n");
+			debug_cond(DEBUG_SETUP != 0,
+				   "\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n");
 			break;
 		case USB_DEVICE_B_HNP_ENABLE:
-			DEBUG_SETUP("\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
+			debug_cond(DEBUG_SETUP != 0,
+				   "\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
 			break;
 
 		case USB_DEVICE_A_HNP_SUPPORT:
 			/* RH port supports HNP */
-			DEBUG_SETUP("\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n");
+			debug_cond(DEBUG_SETUP != 0,
+				   "\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n");
 			break;
 
 		case USB_DEVICE_A_ALT_HNP_SUPPORT:
 			/* other RH port does */
-			DEBUG_SETUP("\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
+			debug_cond(DEBUG_SETUP != 0,
+				   "\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
 			break;
 		}
 
@@ -1226,11 +1263,13 @@ static int s3c_udc_set_feature(struct usb_ep *_ep)
 		return 0;
 
 	case USB_RECIP_INTERFACE:
-		DEBUG_SETUP("\tSET_FEATURE: USB_RECIP_INTERFACE\n");
+		debug_cond(DEBUG_SETUP != 0,
+			   "\tSET_FEATURE: USB_RECIP_INTERFACE\n");
 		break;
 
 	case USB_RECIP_ENDPOINT:
-		DEBUG_SETUP("\tSET_FEATURE: USB_RECIP_ENDPOINT\n");
+		debug_cond(DEBUG_SETUP != 0,
+			   "\tSET_FEATURE: USB_RECIP_ENDPOINT\n");
 		if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
 			if (ep_num == 0) {
 				s3c_udc_ep0_set_stall(ep);
@@ -1262,14 +1301,15 @@ void s3c_ep0_setup(struct s3c_udc *dev)
 	/* read control req from fifo (8 bytes) */
 	s3c_fifo_read(ep, (u32 *)usb_ctrl, 8);
 
-	DEBUG_SETUP("%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
-		    "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n",
-		    __func__, usb_ctrl->bRequestType,
-		    (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT",
-		    usb_ctrl->bRequest,
-		    usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex);
+	debug_cond(DEBUG_SETUP != 0,
+		   "%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
+		   "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n",
+		   __func__, usb_ctrl->bRequestType,
+		   (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT",
+		   usb_ctrl->bRequest,
+		   usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex);
 
-#ifdef DEBUG_S3C_UDC
+#ifdef DEBUG
 	{
 		int i, len = sizeof(*usb_ctrl);
 		char *p = (char *)usb_ctrl;
@@ -1286,10 +1326,12 @@ void s3c_ep0_setup(struct s3c_udc *dev)
 
 	if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST &&
 	    usb_ctrl->wLength != 1) {
-		DEBUG_SETUP("\t%s:GET_MAX_LUN_REQUEST:invalid",
-			      __func__);
-		DEBUG_SETUP("wLength = %d, setup returned\n",
-			    usb_ctrl->wLength);
+		debug_cond(DEBUG_SETUP != 0,
+			   "\t%s:GET_MAX_LUN_REQUEST:invalid",
+			   __func__);
+		debug_cond(DEBUG_SETUP != 0,
+			   "wLength = %d, setup returned\n",
+			   usb_ctrl->wLength);
 
 		s3c_udc_ep0_set_stall(ep);
 		dev->ep0state = WAIT_FOR_SETUP;
@@ -1298,8 +1340,9 @@ void s3c_ep0_setup(struct s3c_udc *dev)
 	} else if (usb_ctrl->bRequest == BOT_RESET_REQUEST &&
 		 usb_ctrl->wLength != 0) {
 		/* Bulk-Only *mass storge reset of class-specific request */
-		DEBUG_SETUP("%s:BOT Rest:invalid wLength =%d, setup returned\n",
-			    __func__, usb_ctrl->wLength);
+		debug_cond(DEBUG_SETUP != 0,
+			   "%s:BOT Rest:invalid wLength =%d, setup returned\n",
+			   __func__, usb_ctrl->wLength);
 
 		s3c_udc_ep0_set_stall(ep);
 		dev->ep0state = WAIT_FOR_SETUP;
@@ -1323,8 +1366,9 @@ void s3c_ep0_setup(struct s3c_udc *dev)
 	if (dev->req_std) {
 		switch (usb_ctrl->bRequest) {
 		case USB_REQ_SET_ADDRESS:
-		DEBUG_SETUP("%s: *** USB_REQ_SET_ADDRESS (%d)\n",
-				__func__, usb_ctrl->wValue);
+		debug_cond(DEBUG_SETUP != 0,
+			   "%s: *** USB_REQ_SET_ADDRESS (%d)\n",
+			   __func__, usb_ctrl->wValue);
 			if (usb_ctrl->bRequestType
 				!= (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
 				break;
@@ -1333,9 +1377,11 @@ void s3c_ep0_setup(struct s3c_udc *dev)
 			return;
 
 		case USB_REQ_SET_CONFIGURATION:
-			DEBUG_SETUP("=====================================\n");
-			DEBUG_SETUP("%s: USB_REQ_SET_CONFIGURATION (%d)\n",
-					__func__, usb_ctrl->wValue);
+			debug_cond(DEBUG_SETUP != 0,
+				   "=====================================\n");
+			debug_cond(DEBUG_SETUP != 0,
+				   "%s: USB_REQ_SET_CONFIGURATION (%d)\n",
+				   __func__, usb_ctrl->wValue);
 
 			if (usb_ctrl->bRequestType == USB_RECIP_DEVICE)
 				reset_available = 1;
@@ -1343,13 +1389,15 @@ void s3c_ep0_setup(struct s3c_udc *dev)
 			break;
 
 		case USB_REQ_GET_DESCRIPTOR:
-			DEBUG_SETUP("%s: *** USB_REQ_GET_DESCRIPTOR\n",
-				    __func__);
+			debug_cond(DEBUG_SETUP != 0,
+				   "%s: *** USB_REQ_GET_DESCRIPTOR\n",
+				   __func__);
 			break;
 
 		case USB_REQ_SET_INTERFACE:
-			DEBUG_SETUP("%s: *** USB_REQ_SET_INTERFACE (%d)\n",
-					__func__, usb_ctrl->wValue);
+			debug_cond(DEBUG_SETUP != 0,
+				   "%s: *** USB_REQ_SET_INTERFACE (%d)\n",
+				   __func__, usb_ctrl->wValue);
 
 			if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE)
 				reset_available = 1;
@@ -1357,8 +1405,9 @@ void s3c_ep0_setup(struct s3c_udc *dev)
 			break;
 
 		case USB_REQ_GET_CONFIGURATION:
-			DEBUG_SETUP("%s: *** USB_REQ_GET_CONFIGURATION\n",
-				    __func__);
+			debug_cond(DEBUG_SETUP != 0,
+				   "%s: *** USB_REQ_GET_CONFIGURATION\n",
+				   __func__);
 			break;
 
 		case USB_REQ_GET_STATUS:
@@ -1384,8 +1433,9 @@ void s3c_ep0_setup(struct s3c_udc *dev)
 			break;
 
 		default:
-			DEBUG_SETUP("%s: *** Default of usb_ctrl->bRequest=0x%x"
-				"happened.\n", __func__, usb_ctrl->bRequest);
+			debug_cond(DEBUG_SETUP != 0,
+				   "%s: *** Default of usb_ctrl->bRequest=0x%x"
+				   "happened.\n", __func__, usb_ctrl->bRequest);
 			break;
 		}
 	}
@@ -1394,7 +1444,8 @@ void s3c_ep0_setup(struct s3c_udc *dev)
 	if (likely(dev->driver)) {
 		/* device-2-host (IN) or no data setup command,
 		 * process immediately */
-		DEBUG_SETUP("%s:usb_ctrlreq will be passed to fsg_setup()\n",
+		debug_cond(DEBUG_SETUP != 0,
+			   "%s:usb_ctrlreq will be passed to fsg_setup()\n",
 			    __func__);
 
 		spin_unlock(&dev->lock);
@@ -1406,17 +1457,20 @@ void s3c_ep0_setup(struct s3c_udc *dev)
 			s3c_udc_ep0_set_stall(ep);
 			dev->ep0state = WAIT_FOR_SETUP;
 
-			DEBUG_SETUP("\tdev->driver->setup failed (%d),"
+			debug_cond(DEBUG_SETUP != 0,
+				   "\tdev->driver->setup failed (%d),"
 				    " bRequest = %d\n",
 				i, usb_ctrl->bRequest);
 
 
 		} else if (dev->req_pending) {
 			dev->req_pending = 0;
-			DEBUG_SETUP("\tdev->req_pending...\n");
+			debug_cond(DEBUG_SETUP != 0,
+				   "\tdev->req_pending...\n");
 		}
 
-		DEBUG_SETUP("\tep0state = %s\n", state_names[dev->ep0state]);
+		debug_cond(DEBUG_SETUP != 0,
+			   "\tep0state = %s\n", state_names[dev->ep0state]);
 
 	}
 }
@@ -1427,18 +1481,21 @@ void s3c_ep0_setup(struct s3c_udc *dev)
 static void s3c_handle_ep0(struct s3c_udc *dev)
 {
 	if (dev->ep0state == WAIT_FOR_SETUP) {
-		DEBUG_OUT_EP("%s: WAIT_FOR_SETUP\n", __func__);
+		debug_cond(DEBUG_OUT_EP != 0,
+			   "%s: WAIT_FOR_SETUP\n", __func__);
 		s3c_ep0_setup(dev);
 
 	} else {
-		DEBUG_OUT_EP("%s: strange state!!(state = %s)\n",
+		debug_cond(DEBUG_OUT_EP != 0,
+			   "%s: strange state!!(state = %s)\n",
 			__func__, state_names[dev->ep0state]);
 	}
 }
 
 static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep)
 {
-	DEBUG_EP0("%s: ep_is_in = %d\n", __func__, ep_is_in(ep));
+	debug_cond(DEBUG_EP0 != 0,
+		   "%s: ep_is_in = %d\n", __func__, ep_is_in(ep));
 	if (ep_is_in(ep)) {
 		dev->ep0state = DATA_STATE_XMIT;
 		s3c_ep0_write(dev);
diff --git a/drivers/usb/gadget/usbstring.c b/drivers/usb/gadget/usbstring.c
index 95555cf96b..4dbe060d6f 100644
--- a/drivers/usb/gadget/usbstring.c
+++ b/drivers/usb/gadget/usbstring.c
@@ -13,6 +13,7 @@
 #include <common.h>
 #include <asm/errno.h>
 #include <linux/usb/ch9.h>
+#include <usbdescriptors.h>
 #include <linux/usb/gadget.h>
 
 #include <asm/unaligned.h>
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 0d4657edf2..59c3e57563 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -50,6 +50,7 @@ COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
 COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
 COBJS-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
 COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
+COBJS-$(CONFIG_USB_EHCI_S5P) += ehci-s5p.o
 COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
 COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
 
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 38d6ae03d3..04300be110 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -108,99 +108,6 @@ static struct descriptor {
 #define ehci_is_TDI()	(0)
 #endif
 
-#if defined(CONFIG_EHCI_DCACHE)
-/*
- * Routines to handle (flush/invalidate) the dcache for the QH and qTD
- * structures and data buffers. This is needed on platforms using this
- * EHCI support with dcache enabled.
- */
-static void flush_invalidate(u32 addr, int size, int flush)
-{
-	if (flush)
-		flush_dcache_range(addr, addr + size);
-	else
-		invalidate_dcache_range(addr, addr + size);
-}
-
-static void cache_qtd(struct qTD *qtd, int flush)
-{
-	u32 *ptr = (u32 *)qtd->qt_buffer[0];
-	int len = (qtd->qt_token & 0x7fff0000) >> 16;
-
-	flush_invalidate((u32)qtd, sizeof(struct qTD), flush);
-	if (ptr && len)
-		flush_invalidate((u32)ptr, len, flush);
-}
-
-
-static inline struct QH *qh_addr(struct QH *qh)
-{
-	return (struct QH *)((u32)qh & 0xffffffe0);
-}
-
-static void cache_qh(struct QH *qh, int flush)
-{
-	struct qTD *qtd;
-	struct qTD *next;
-	static struct qTD *first_qtd;
-
-	/*
-	 * Walk the QH list and flush/invalidate all entries
-	 */
-	while (1) {
-		flush_invalidate((u32)qh_addr(qh), sizeof(struct QH), flush);
-		if ((u32)qh & QH_LINK_TYPE_QH)
-			break;
-		qh = qh_addr(qh);
-		qh = (struct QH *)qh->qh_link;
-	}
-	qh = qh_addr(qh);
-
-	/*
-	 * Save first qTD pointer, needed for invalidating pass on this QH
-	 */
-	if (flush)
-		first_qtd = qtd = (struct qTD *)(*(u32 *)&qh->qh_overlay &
-						 0xffffffe0);
-	else
-		qtd = first_qtd;
-
-	/*
-	 * Walk the qTD list and flush/invalidate all entries
-	 */
-	while (1) {
-		if (qtd == NULL)
-			break;
-		cache_qtd(qtd, flush);
-		next = (struct qTD *)((u32)qtd->qt_next & 0xffffffe0);
-		if (next == qtd)
-			break;
-		qtd = next;
-	}
-}
-
-static inline void ehci_flush_dcache(struct QH *qh)
-{
-	cache_qh(qh, 1);
-}
-
-static inline void ehci_invalidate_dcache(struct QH *qh)
-{
-	cache_qh(qh, 0);
-}
-#else /* CONFIG_EHCI_DCACHE */
-/*
- *
- */
-static inline void ehci_flush_dcache(struct QH *qh)
-{
-}
-
-static inline void ehci_invalidate_dcache(struct QH *qh)
-{
-}
-#endif /* CONFIG_EHCI_DCACHE */
-
 void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
 {
 	mdelay(50);
@@ -225,11 +132,6 @@ static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
 	return -1;
 }
 
-static void ehci_free(void *p, size_t sz)
-{
-
-}
-
 static int ehci_reset(void)
 {
 	uint32_t cmd;
@@ -266,43 +168,22 @@ out:
 	return ret;
 }
 
-static void *ehci_alloc(size_t sz, size_t align)
-{
-	static struct QH qh __attribute__((aligned(32)));
-	static struct qTD td[3] __attribute__((aligned (32)));
-	static int ntds;
-	void *p;
-
-	switch (sz) {
-	case sizeof(struct QH):
-		p = &qh;
-		ntds = 0;
-		break;
-	case sizeof(struct qTD):
-		if (ntds == 3) {
-			debug("out of TDs\n");
-			return NULL;
-		}
-		p = &td[ntds];
-		ntds++;
-		break;
-	default:
-		debug("unknown allocation size\n");
-		return NULL;
-	}
-
-	memset(p, 0, sz);
-	return p;
-}
-
 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
 {
-	uint32_t addr, delta, next;
+	uint32_t delta, next;
+	uint32_t addr = (uint32_t)buf;
+	size_t rsz = roundup(sz, 32);
 	int idx;
 
-	addr = (uint32_t) buf;
+	if (sz != rsz)
+		debug("EHCI-HCD: Misaligned buffer size (%08x)\n", sz);
+
+	if (addr & 31)
+		debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
+
 	idx = 0;
 	while (idx < 5) {
+		flush_dcache_range(addr, addr + rsz);
 		td->qt_buffer[idx] = cpu_to_hc32(addr);
 		td->qt_buffer_hi[idx] = 0;
 		next = (addr + 4096) & ~4095;
@@ -326,8 +207,10 @@ static int
 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
 		   int length, struct devrequest *req)
 {
-	struct QH *qh;
-	struct qTD *td;
+	static struct QH qh __attribute__((aligned(32)));
+	static struct qTD qtd[3] __attribute__((aligned (32)));
+	int qtd_counter = 0;
+
 	volatile struct qTD *vtd;
 	unsigned long ts;
 	uint32_t *tdp;
@@ -346,12 +229,22 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
 		      le16_to_cpu(req->value), le16_to_cpu(req->value),
 		      le16_to_cpu(req->index));
 
-	qh = ehci_alloc(sizeof(struct QH), 32);
-	if (qh == NULL) {
-		debug("unable to allocate QH\n");
-		return -1;
-	}
-	qh->qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
+	memset(&qh, 0, sizeof(struct QH));
+	memset(qtd, 0, sizeof(qtd));
+
+	toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
+
+	/*
+	 * Setup QH (3.6 in ehci-r10.pdf)
+	 *
+	 *   qh_link ................. 03-00 H
+	 *   qh_endpt1 ............... 07-04 H
+	 *   qh_endpt2 ............... 0B-08 H
+	 * - qh_curtd
+	 *   qh_overlay.qt_next ...... 13-10 H
+	 * - qh_overlay.qt_altnext
+	 */
+	qh.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
 	c = (usb_pipespeed(pipe) != USB_SPEED_HIGH &&
 	     usb_pipeendpoint(pipe) == 0) ? 1 : 0;
 	endpt = (8 << 28) |
@@ -362,88 +255,98 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
 	    (usb_pipespeed(pipe) << 12) |
 	    (usb_pipeendpoint(pipe) << 8) |
 	    (0 << 7) | (usb_pipedevice(pipe) << 0);
-	qh->qh_endpt1 = cpu_to_hc32(endpt);
+	qh.qh_endpt1 = cpu_to_hc32(endpt);
 	endpt = (1 << 30) |
 	    (dev->portnr << 23) |
 	    (dev->parent->devnum << 16) | (0 << 8) | (0 << 0);
-	qh->qh_endpt2 = cpu_to_hc32(endpt);
-	qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
-
-	td = NULL;
-	tdp = &qh->qh_overlay.qt_next;
+	qh.qh_endpt2 = cpu_to_hc32(endpt);
+	qh.qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
 
-	toggle =
-	    usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
+	tdp = &qh.qh_overlay.qt_next;
 
 	if (req != NULL) {
-		td = ehci_alloc(sizeof(struct qTD), 32);
-		if (td == NULL) {
-			debug("unable to allocate SETUP td\n");
-			goto fail;
-		}
-		td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
-		td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
+		/*
+		 * Setup request qTD (3.5 in ehci-r10.pdf)
+		 *
+		 *   qt_next ................ 03-00 H
+		 *   qt_altnext ............. 07-04 H
+		 *   qt_token ............... 0B-08 H
+		 *
+		 *   [ buffer, buffer_hi ] loaded with "req".
+		 */
+		qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
+		qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
 		token = (0 << 31) |
 		    (sizeof(*req) << 16) |
 		    (0 << 15) | (0 << 12) | (3 << 10) | (2 << 8) | (0x80 << 0);
-		td->qt_token = cpu_to_hc32(token);
-		if (ehci_td_buffer(td, req, sizeof(*req)) != 0) {
+		qtd[qtd_counter].qt_token = cpu_to_hc32(token);
+		if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req)) != 0) {
 			debug("unable construct SETUP td\n");
-			ehci_free(td, sizeof(*td));
 			goto fail;
 		}
-		*tdp = cpu_to_hc32((uint32_t) td);
-		tdp = &td->qt_next;
+		/* Update previous qTD! */
+		*tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
+		tdp = &qtd[qtd_counter++].qt_next;
 		toggle = 1;
 	}
 
 	if (length > 0 || req == NULL) {
-		td = ehci_alloc(sizeof(struct qTD), 32);
-		if (td == NULL) {
-			debug("unable to allocate DATA td\n");
-			goto fail;
-		}
-		td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
-		td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
+		/*
+		 * Setup request qTD (3.5 in ehci-r10.pdf)
+		 *
+		 *   qt_next ................ 03-00 H
+		 *   qt_altnext ............. 07-04 H
+		 *   qt_token ............... 0B-08 H
+		 *
+		 *   [ buffer, buffer_hi ] loaded with "buffer".
+		 */
+		qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
+		qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
 		token = (toggle << 31) |
 		    (length << 16) |
 		    ((req == NULL ? 1 : 0) << 15) |
 		    (0 << 12) |
 		    (3 << 10) |
 		    ((usb_pipein(pipe) ? 1 : 0) << 8) | (0x80 << 0);
-		td->qt_token = cpu_to_hc32(token);
-		if (ehci_td_buffer(td, buffer, length) != 0) {
+		qtd[qtd_counter].qt_token = cpu_to_hc32(token);
+		if (ehci_td_buffer(&qtd[qtd_counter], buffer, length) != 0) {
 			debug("unable construct DATA td\n");
-			ehci_free(td, sizeof(*td));
 			goto fail;
 		}
-		*tdp = cpu_to_hc32((uint32_t) td);
-		tdp = &td->qt_next;
+		/* Update previous qTD! */
+		*tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
+		tdp = &qtd[qtd_counter++].qt_next;
 	}
 
 	if (req != NULL) {
-		td = ehci_alloc(sizeof(struct qTD), 32);
-		if (td == NULL) {
-			debug("unable to allocate ACK td\n");
-			goto fail;
-		}
-		td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
-		td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
+		/*
+		 * Setup request qTD (3.5 in ehci-r10.pdf)
+		 *
+		 *   qt_next ................ 03-00 H
+		 *   qt_altnext ............. 07-04 H
+		 *   qt_token ............... 0B-08 H
+		 */
+		qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
+		qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
 		token = (toggle << 31) |
 		    (0 << 16) |
 		    (1 << 15) |
 		    (0 << 12) |
 		    (3 << 10) |
 		    ((usb_pipein(pipe) ? 0 : 1) << 8) | (0x80 << 0);
-		td->qt_token = cpu_to_hc32(token);
-		*tdp = cpu_to_hc32((uint32_t) td);
-		tdp = &td->qt_next;
+		qtd[qtd_counter].qt_token = cpu_to_hc32(token);
+		/* Update previous qTD! */
+		*tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
+		tdp = &qtd[qtd_counter++].qt_next;
 	}
 
-	qh_list.qh_link = cpu_to_hc32((uint32_t) qh | QH_LINK_TYPE_QH);
+	qh_list.qh_link = cpu_to_hc32((uint32_t)&qh | QH_LINK_TYPE_QH);
 
 	/* Flush dcache */
-	ehci_flush_dcache(&qh_list);
+	flush_dcache_range((uint32_t)&qh_list,
+		(uint32_t)&qh_list + sizeof(struct QH));
+	flush_dcache_range((uint32_t)&qh, (uint32_t)&qh + sizeof(struct QH));
+	flush_dcache_range((uint32_t)qtd, (uint32_t)qtd + sizeof(qtd));
 
 	usbsts = ehci_readl(&hcor->or_usbsts);
 	ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f));
@@ -462,17 +365,27 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
 
 	/* Wait for TDs to be processed. */
 	ts = get_timer(0);
-	vtd = td;
+	vtd = &qtd[qtd_counter - 1];
 	timeout = USB_TIMEOUT_MS(pipe);
 	do {
 		/* Invalidate dcache */
-		ehci_invalidate_dcache(&qh_list);
+		invalidate_dcache_range((uint32_t)&qh_list,
+			(uint32_t)&qh_list + sizeof(struct QH));
+		invalidate_dcache_range((uint32_t)&qh,
+			(uint32_t)&qh + sizeof(struct QH));
+		invalidate_dcache_range((uint32_t)qtd,
+			(uint32_t)qtd + sizeof(qtd));
+
 		token = hc32_to_cpu(vtd->qt_token);
 		if (!(token & 0x80))
 			break;
 		WATCHDOG_RESET();
 	} while (get_timer(ts) < timeout);
 
+	/* Invalidate the memory area occupied by buffer */
+	invalidate_dcache_range(((uint32_t)buffer & ~31),
+		((uint32_t)buffer & ~31) + roundup(length, 32));
+
 	/* Check that the TD processing happened */
 	if (token & 0x80) {
 		printf("EHCI timed out on TD - token=%#x\n", token);
@@ -492,7 +405,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
 
 	qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
 
-	token = hc32_to_cpu(qh->qh_overlay.qt_token);
+	token = hc32_to_cpu(qh.qh_overlay.qt_token);
 	if (!(token & 0x80)) {
 		debug("TOKEN=%#x\n", token);
 		switch (token & 0xfc) {
@@ -531,13 +444,6 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
 	return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
 
 fail:
-	td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next);
-	while (td != (void *)QT_NEXT_TERMINATE) {
-		qh->qh_overlay.qt_next = td->qt_next;
-		ehci_free(td, sizeof(*td));
-		td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next);
-	}
-	ehci_free(qh, sizeof(*qh));
 	return -1;
 }
 
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 5dec673c8e..42c77fe333 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -73,7 +73,8 @@ static void usbh1_internal_phy_clock_gate(int on)
 
 static void usbh1_power_config(void)
 {
-	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	struct anatop_regs __iomem *anatop =
+		(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
 	/*
 	 * Some phy and power's special controls for host1
 	 * 1. The external charger detector needs to be disabled
@@ -87,7 +88,7 @@ static void usbh1_power_config(void)
 		     &anatop->usb2_chrg_detect);
 
 	__raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
-		     &anatop->usb2_pll_480_ctrl);
+		     &anatop->usb2_pll_480_ctrl_clr);
 
 	__raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
 		     ANADIG_USB2_PLL_480_CTRL_POWER |
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index 61dbccd53c..45cbd18a00 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -125,11 +125,7 @@ int ehci_hcd_init(void)
 	hcor = (struct ehci_hcor *)((uint32_t) hccr +
 			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
 	setbits_le32(&ehci->usbmode, CM_HOST);
-#ifdef CONFIG_MX31
-	setbits_le32(&ehci->control, USB_EN);
-
 	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
-#endif
 	mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
 
 	udelay(10000);
diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
new file mode 100644
index 0000000000..4dd4ec168f
--- /dev/null
+++ b/drivers/usb/host/ehci-s5p.c
@@ -0,0 +1,110 @@
+/*
+ * SAMSUNG S5P USB HOST EHCI Controller
+ *
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ *	Vivek Gautam <gautam.vivek@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ehci-s5p.h>
+#include "ehci.h"
+#include "ehci-core.h"
+
+/* Setup the EHCI host controller. */
+static void setup_usb_phy(struct s5p_usb_phy *usb)
+{
+	clrbits_le32(&usb->usbphyctrl0,
+			HOST_CTRL0_FSEL_MASK |
+			HOST_CTRL0_COMMONON_N |
+			/* HOST Phy setting */
+			HOST_CTRL0_PHYSWRST |
+			HOST_CTRL0_PHYSWRSTALL |
+			HOST_CTRL0_SIDDQ |
+			HOST_CTRL0_FORCESUSPEND |
+			HOST_CTRL0_FORCESLEEP);
+
+	setbits_le32(&usb->usbphyctrl0,
+			/* Setting up the ref freq */
+			(CLK_24MHZ << 16) |
+			/* HOST Phy setting */
+			HOST_CTRL0_LINKSWRST |
+			HOST_CTRL0_UTMISWRST);
+	udelay(10);
+	clrbits_le32(&usb->usbphyctrl0,
+			HOST_CTRL0_LINKSWRST |
+			HOST_CTRL0_UTMISWRST);
+	udelay(20);
+
+	/* EHCI Ctrl setting */
+	setbits_le32(&usb->ehcictrl,
+			EHCICTRL_ENAINCRXALIGN |
+			EHCICTRL_ENAINCR4 |
+			EHCICTRL_ENAINCR8 |
+			EHCICTRL_ENAINCR16);
+}
+
+/* Reset the EHCI host controller. */
+static void reset_usb_phy(struct s5p_usb_phy *usb)
+{
+	/* HOST_PHY reset */
+	setbits_le32(&usb->usbphyctrl0,
+			HOST_CTRL0_PHYSWRST |
+			HOST_CTRL0_PHYSWRSTALL |
+			HOST_CTRL0_SIDDQ |
+			HOST_CTRL0_FORCESUSPEND |
+			HOST_CTRL0_FORCESLEEP);
+}
+
+/*
+ * EHCI-initialization
+ * Create the appropriate control structures to manage
+ * a new EHCI host controller.
+ */
+int ehci_hcd_init(void)
+{
+	struct s5p_usb_phy *usb;
+
+	usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy();
+	setup_usb_phy(usb);
+
+	hccr = (struct ehci_hccr *)(EXYNOS5_USB_HOST_EHCI_BASE);
+	hcor = (struct ehci_hcor *)((uint32_t) hccr
+				+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+	debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
+		(uint32_t)hccr, (uint32_t)hcor,
+		(uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+	return 0;
+}
+
+/*
+ * Destroy the appropriate control structures corresponding
+ * the EHCI host controller.
+ */
+int ehci_hcd_stop()
+{
+	struct s5p_usb_phy *usb;
+
+	usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy();
+	reset_usb_phy(usb);
+
+	return 0;
+}
diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
index 20b5503c90..ed4c60d8f9 100644
--- a/drivers/usb/musb/Makefile
+++ b/drivers/usb/musb/Makefile
@@ -32,6 +32,10 @@ COBJS-$(CONFIG_USB_DAVINCI) += davinci.o
 COBJS-$(CONFIG_USB_OMAP3) += omap3.o
 COBJS-$(CONFIG_USB_DA8XX) += da8xx.o
 COBJS-$(CONFIG_USB_AM35X) += am35x.o
+COBJS-$(CONFIG_USB_RDA) += rda.o
+ifndef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_MUSB_DMA) += musbhsdma.o
+endif
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
index 545ebf4b50..5972916f85 100644
--- a/drivers/usb/musb/musb_core.c
+++ b/drivers/usb/musb/musb_core.c
@@ -102,6 +102,7 @@ void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt)
 			if (csr & MUSB_TXCSR_TXPKTRDY)
 				writew(csr | MUSB_TXCSR_FLUSHFIFO,
 					&musbr->txcsr);
+			writew(epinfo->epsize, &musbr->txmaxp);
 		} else {
 			/* Configure fifo size and fifo base address */
 			config_fifo(rx, idx, fifoaddr);
@@ -115,6 +116,7 @@ void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt)
 			if (csr & MUSB_RXCSR_RXPKTRDY)
 				writew(csr | MUSB_RXCSR_FLUSHFIFO,
 					&musbr->rxcsr);
+			writew(epinfo->epsize, &musbr->rxmaxp);
 		}
 		fifoaddr += epinfo->epsize;
 		epinfo++;
diff --git a/drivers/usb/musb/musb_hcd.c b/drivers/usb/musb/musb_hcd.c
index 2df52c1c33..2464b05577 100644
--- a/drivers/usb/musb/musb_hcd.c
+++ b/drivers/usb/musb/musb_hcd.c
@@ -1113,10 +1113,11 @@ int usb_lowlevel_init(void)
 	 * should be a usb device connected.
 	 */
 	timeout = musb_cfg.timeout;
-	while (timeout--)
+	while (timeout) {
 		if (readb(&musbr->devctl) & MUSB_DEVCTL_HM)
 			break;
-
+		timeout--;
+	}
 	/* if musb core is not in host mode, then return */
 	if (!timeout)
 		return -1;
diff --git a/drivers/usb/musb/musb_udc.c b/drivers/usb/musb/musb_udc.c
index 09cdec31a9..035fa235cd 100644
--- a/drivers/usb/musb/musb_udc.c
+++ b/drivers/usb/musb/musb_udc.c
@@ -50,27 +50,28 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#define DEBUG
 
 #include <common.h>
 #include <usb/musb_udc.h>
 #include "../gadget/ep0.h"
 #include "musb_core.h"
+#include <usb/musb_dma.h>
 #if defined(CONFIG_USB_OMAP3)
 #include "omap3.h"
 #elif defined(CONFIG_USB_AM35X)
 #include "am35x.h"
 #elif defined(CONFIG_USB_DAVINCI)
 #include "davinci.h"
+#elif defined(CONFIG_USB_RDA)
+#include "rda.h"
 #endif
 
 /* Define MUSB_DEBUG for debugging */
-/* #define MUSB_DEBUG */
+ #define MUSB_DEBUG
 #include "musb_debug.h"
 
-#define MAX_ENDPOINT 15
-
-#define GET_ENDPOINT(dev,ep)						\
-(((struct usb_device_instance *)(dev))->bus->endpoint_array + ep)
+#define MAX_ENDPOINT 6
 
 #define SET_EP0_STATE(s)						\
 do {									\
@@ -95,8 +96,8 @@ do {									\
 } while (0)
 
 /* static implies these initialized to 0 or NULL */
-static int debug_setup;
-static int debug_level;
+static int debug_setup = 1;
+static int debug_level = 4;
 static struct musb_epinfo epinfo[MAX_ENDPOINT * 2];
 static enum ep0_state_enum {
 	IDLE = 0,
@@ -111,7 +112,10 @@ static char *ep0_state_strings[4] = {
 	"SET_ADDRESS",
 };
 
-static struct urb *ep0_urb;
+static u8 ep0_buffer_data[URB_BUF_SIZE] __attribute__((__aligned__(4)));
+
+static struct urb ep0_urb_instance;
+static struct urb *ep0_urb = &ep0_urb_instance;
 struct usb_endpoint_instance *ep0_endpoint;
 static struct usb_device_instance *udc_device;
 static int enabled;
@@ -125,6 +129,9 @@ static void musb_db_regs(void)
 	b = readb(&musbr->faddr);
 	serial_printf("\tfaddr   0x%2.2x\n", b);
 
+	w = readw(&musbr->hwvers);
+	serial_printf("\thardware version 0x%4.4x\n", w);
+
 	b = readb(&musbr->power);
 	musb_print_pwr(b);
 
@@ -174,7 +181,6 @@ static void musb_peri_softconnect(void)
 	readw(&musbr->intrtx);
 
 	udelay(1000 * 1000); /* 1 sec */
-
 	/* Power on MUSB */
 	power = readb(&musbr->power);
 	power |= MUSB_POWER_SOFTCONN;
@@ -182,7 +188,7 @@ static void musb_peri_softconnect(void)
 	 * The usb device interface is usb 1.1
 	 * Disable 2.0 high speed by clearring the hsenable bit.
 	 */
-	power &= ~MUSB_POWER_HSENAB;
+	//power &= ~MUSB_POWER_HSENAB;
 	writeb(power, &musbr->power);
 
 	/* Check if device is in b-peripheral mode */
@@ -398,7 +404,7 @@ static void musb_peri_ep0_idle(void)
 				      __PRETTY_FUNCTION__,
 				      udc_device->address, faddr);
 			udelay(1000 * 1000);
-			hang();
+			return;
 		}
 	}
 
@@ -638,63 +644,82 @@ static void musb_peri_ep0(void)
 		musb_peri_ep0_rx();
 }
 
+static inline struct usb_endpoint_instance *get_endpoint(
+		struct usb_device_instance *dev, unsigned int ep)
+{
+	int i;
+	for(i = 0; i < MAX_ENDPOINT; i++) {
+		if(dev->bus->endpoint_array[i].endpoint_address == (ep | USB_DIR_OUT))
+			return &(dev->bus->endpoint_array[i]);
+	}
+	return NULL;
+}
+
+#ifdef CONFIG_MUSB_DMA
+#define DMA_BUF_SIZE	1024
+static u8 dma_buf[DMA_BUF_SIZE] __attribute__((__aligned__(CONFIG_SYS_CACHELINE_SIZE)));
+#endif
 static void musb_peri_rx_ep(unsigned int ep)
 {
-	u16 peri_rxcount = readw(&musbr->ep[ep].epN.rxcount);
+	u16 peri_rxcount = udc_chars_in_rxfifo(ep);
 
 	if (peri_rxcount) {
 		struct usb_endpoint_instance *endpoint;
-		u32 length;
 		u8 *data;
 
-		endpoint = GET_ENDPOINT(udc_device, ep);
+		endpoint = get_endpoint((struct usb_device_instance *)udc_device, ep);
 		if (endpoint && endpoint->rcv_urb) {
 			struct urb *urb = endpoint->rcv_urb;
-			unsigned int remaining_space = urb->buffer_length -
-				urb->actual_length;
+			int urb_bad = 0; /* urb is good */
+			u32 xfer;
 
-			if (remaining_space) {
-				int urb_bad = 0; /* urb is good */
-
-				if (peri_rxcount > remaining_space)
-					length = remaining_space;
-				else
-					length = peri_rxcount;
-
-				data = (u8 *) urb->buffer_data;
-				data += urb->actual_length;
-
-				/* The common musb fifo reader */
-				read_fifo(ep, length, data);
+			xfer = MIN(peri_rxcount, urb->req_length);
 
+			data = (u8 *) urb->buffer;
+			if ((data == 0) || (xfer == 0))
+				return;
+#ifndef CONFIG_MUSB_DMA
+			/* The common musb fifo reader */
+			read_fifo(ep, xfer, data);
+			if (xfer == peri_rxcount) {//yes, we must read out all data
 				musb_peri_rx_ack(ep);
-
-				/*
-				 * urb's actual_length is updated in
-				 * usbd_rcv_complete
-				 */
-				usbd_rcv_complete(endpoint, length, urb_bad);
-
+			}
+#else
+			if (urb->use_dma && xfer <= DMA_BUF_SIZE &&
+				configure_dma_channel(ep, endpoint->rcv_packetSize, 0,
+								(u32)dma_buf, xfer, 0) == 0) {
+				wait_dma_xfer_done();
+				memcpy(data, dma_buf, xfer);
+				if (xfer == peri_rxcount)
+					musb_peri_rx_ack(ep);
 			} else {
-				if (debug_level > 0)
-					serial_printf("ERROR : %s %d no space "
-						      "in rcv buffer\n",
-						      __PRETTY_FUNCTION__, ep);
+				read_fifo(ep, xfer, data);
+				if (xfer == peri_rxcount) {//yes, we must read out all data
+					musb_peri_rx_ack(ep);
+				}
 			}
+#endif
+			/*
+			 * urb's actual_length is updated in
+			 * usbd_rcv_complete
+			 */
+			usbd_rcv_complete(endpoint, xfer, urb_bad);
 		} else {
 			if (debug_level > 0)
 				serial_printf("ERROR : %s %d problem with "
 					      "endpoint\n",
 					      __PRETTY_FUNCTION__, ep);
 		}
-
 	} else {
-		if (debug_level > 0)
-			serial_printf("ERROR : %s %d with nothing to do\n",
-				      __PRETTY_FUNCTION__, ep);
+		musb_peri_rx_ack(ep);
 	}
 }
 
+void poll_rx_ep(unsigned int ep)
+{
+	musb_peri_rx_ep(ep);
+}
+
 static void musb_peri_rx(u16 intr)
 {
 	unsigned int ep;
@@ -703,9 +728,11 @@ static void musb_peri_rx(u16 intr)
 	if (0x01 & intr)
 		musb_peri_ep0();
 
-	for (ep = 1; ep < 16; ep++) {
-		if ((1 << ep) & intr)
+	for (ep = 1; ep < MAX_ENDPOINT; ep++) {
+		if ((1 << ep) & intr) {
+			//serial_puts("from irq\n");
 			musb_peri_rx_ep(ep);
+		}
 	}
 }
 
@@ -761,12 +788,13 @@ void udc_irq(void)
 			usbd_device_event_irq(udc_device, DEVICE_HUB_RESET, 0);
 		}
 
+/*
 		if (MUSB_INTR_SOF & intrusb) {
 			usbd_device_event_irq(udc_device,
 					      DEVICE_BUS_ACTIVITY, 0);
 			musb_peri_resume();
 		}
-
+*/
 		if (MUSB_INTR_SUSPEND & intrusb) {
 			usbd_device_event_irq(udc_device,
 					      DEVICE_BUS_INACTIVE, 0);
@@ -780,7 +808,6 @@ void udc_irq(void)
 
 			if (intrrx)
 				musb_peri_rx(intrrx);
-
 			if (intrtx)
 				musb_peri_tx(intrtx);
 		} else {
@@ -808,6 +835,49 @@ void udc_unset_nak(int ep_num)
 	/* noop */
 }
 
+unsigned int udc_chars_in_rxfifo(unsigned int ep)
+{
+	u16 cnt;
+
+	cnt =  readw(&musbr->ep[ep].epN.rxcount);
+	/*
+	 * when the cnt is not aligned for 4, the data is not put into fifo by
+	 * udc, so wait a moment!!!!!!!!
+	 */
+	if ((cnt & 0x03) != 0)
+		udelay(100);
+
+	return cnt;
+}
+
+void udc_clear_halt(unsigned int ep, int is_in)
+{
+	u16 csr;
+
+	if(ep > MAX_ENDPOINT) {
+		printf("%s epnum %d too big\n", __func__, ep);
+		return;
+	}
+	printf("%s epnum %d is %s\n", __func__, ep, is_in ? "in" : "out");
+	if (is_in) {
+		csr = readw(&musbr->ep[ep].epN.txcsr);
+		csr |= MUSB_TXCSR_CLRDATATOG | MUSB_TXCSR_P_WZC_BITS;
+		csr &= ~(MUSB_TXCSR_P_SENDSTALL |
+				MUSB_TXCSR_P_SENTSTALL |
+				MUSB_TXCSR_TXPKTRDY);
+		writew(csr, &musbr->ep[ep].epN.txcsr);
+	} else {
+		csr = readw(&musbr->ep[ep].epN.rxcsr);
+		csr |= MUSB_RXCSR_CLRDATATOG | MUSB_RXCSR_P_WZC_BITS;
+		csr &= ~(MUSB_RXCSR_P_SENDSTALL |
+			 MUSB_RXCSR_P_SENTSTALL);
+		writew(csr, &musbr->ep[ep].epN.rxcsr);
+	}
+
+	return;
+}
+
+#define WRITE_TIMEOUT	1000000 /* us */
 int udc_endpoint_write(struct usb_endpoint_instance *endpoint)
 {
 	int ret = 0;
@@ -816,6 +886,7 @@ int udc_endpoint_write(struct usb_endpoint_instance *endpoint)
 	if (endpoint->tx_urb && endpoint->state == 0) {
 		unsigned int ep = endpoint->endpoint_address &
 			USB_ENDPOINT_NUMBER_MASK;
+		int timeout = WRITE_TIMEOUT;
 
 		u16 peri_txcsr = readw(&musbr->ep[ep].epN.txcsr);
 
@@ -825,9 +896,10 @@ int udc_endpoint_write(struct usb_endpoint_instance *endpoint)
 			writew(peri_txcsr, &musbr->ep[ep].epN.txcsr);
 		}
 
+/*
 		if (debug_level > 1)
 			musb_print_txcsr(peri_txcsr);
-
+*/
 		/* Check if a packet is waiting to be sent */
 		if (!(peri_txcsr & MUSB_TXCSR_TXPKTRDY)) {
 			u32 length;
@@ -849,9 +921,24 @@ int udc_endpoint_write(struct usb_endpoint_instance *endpoint)
 
 			musb_peri_tx_ready(ep);
 
-			endpoint->last = length;
-			/* usbd_tx_complete will take care of updating 'sent' */
-			usbd_tx_complete(endpoint);
+			while ((peri_txcsr & MUSB_TXCSR_FIFONOTEMPTY) && timeout) {
+				peri_txcsr = readw(&musbr->ep[ep].epN.txcsr);
+				timeout--;
+				udelay(1);
+			}
+
+			if (timeout <= 0) {
+				/* timeout, clear register */
+				serial_printf("ERROR, can not write out\n");
+				return -1;
+			} else {
+				endpoint->last = length;
+				/* usbd_tx_complete will take care of updating 'sent' */
+				usbd_tx_complete(endpoint);
+			}
+		} else {
+			printf("ERROR: txcsr = %#x, TXPKTRDY is set.\n", peri_txcsr);
+			return -1;
 		}
 	} else {
 		if (debug_level > 0)
@@ -871,20 +958,25 @@ void udc_setup_ep(struct usb_device_instance *device, unsigned int id,
 		/* EP0 */
 		ep0_endpoint = endpoint;
 		ep0_endpoint->endpoint_address = 0xff;
-		ep0_urb = usbd_alloc_urb(device, endpoint);
+		//ep0_urb = usbd_alloc_urb(device, endpoint);
+		usbd_init_urb(ep0_urb, device, endpoint, ep0_buffer_data, URB_BUF_SIZE);
 	} else if (MAX_ENDPOINT >= id) {
 		int ep_addr;
+		int index;
 
 		/* Check the direction */
 		ep_addr = endpoint->endpoint_address;
 		if (USB_DIR_IN == (ep_addr & USB_ENDPOINT_DIR_MASK)) {
 			/* IN */
-			epinfo[(id * 2) + 1].epsize = endpoint->tx_packetSize;
+			index = (id - 1) * 2 + 1;
+			epinfo[index].epsize = endpoint->tx_packetSize;
 		} else {
 			/* OUT */
-			epinfo[id * 2].epsize = endpoint->rcv_packetSize;
+			index = (id - 1) * 2;
+			epinfo[index].epsize = endpoint->rcv_packetSize;
 		}
 
+
 		musb_configure_ep(&epinfo[0],
 				  sizeof(epinfo) / sizeof(struct musb_epinfo));
 	} else {
@@ -918,6 +1010,13 @@ void udc_disable(void)
 	enabled = 0;
 }
 
+int is_usbd_high_speed(void)
+{
+	u8 power;
+	power = readb(&musbr->power);
+
+	return ((power & MUSB_POWER_HSMODE) ? 1 : 0);
+}
 void udc_startup_events(struct usb_device_instance *device)
 {
 	/* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */
@@ -935,6 +1034,17 @@ void udc_startup_events(struct usb_device_instance *device)
 	udc_enable(device);
 }
 
+void udc_hot_startup(struct usb_device_instance *device)
+{
+	u8 faddr;
+
+	usbd_device_event_irq(device, DEVICE_CONFIGURED, 0);
+	udc_enable(device);
+
+	faddr = readb(&musbr->faddr);
+	udc_device->address = faddr;
+}
+
 int udc_init(void)
 {
 	int ret;
@@ -947,6 +1057,7 @@ int udc_init(void)
 	/* Configure all the endpoint FIFO's and start usb controller */
 	musbr = musb_cfg.regs;
 
+
 	/* Initialize the endpoints */
 	for (ep_loop = 0; ep_loop < MAX_ENDPOINT * 2; ep_loop++) {
 		epinfo[ep_loop].epnum = (ep_loop / 2) + 1;
@@ -958,6 +1069,30 @@ int udc_init(void)
 
 	ret = 0;
 end:
-
 	return ret;
 }
+
+int udc_soft_init(void)
+{
+	int ep_loop;
+
+	/* Configure all the endpoint FIFO's and start usb controller */
+	musbr = musb_cfg.regs;
+
+
+	/* Initialize the endpoints */
+	for (ep_loop = 0; ep_loop < MAX_ENDPOINT * 2; ep_loop++) {
+		epinfo[ep_loop].epnum = (ep_loop / 2) + 1;
+		epinfo[ep_loop].epdir = ep_loop % 2; /* OUT, IN */
+		epinfo[ep_loop].epsize = 0;
+	}
+
+	readb(&musbr->intrusb);
+	readw(&musbr->intrrx);
+	readw(&musbr->intrtx);
+
+	musb_db_regs();
+
+	return 0;
+}
+
diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c
new file mode 100644
index 0000000000..3fb1b66ea2
--- /dev/null
+++ b/drivers/usb/musb/musbhsdma.c
@@ -0,0 +1,118 @@
+#include <common.h>
+#include "musbhsdma.h"
+#include "rda.h"
+
+
+static u32 start_addr = 0;
+static u32 dma_req_len = 0;
+static int complete = 0;
+
+int configure_dma_channel(u32 epnum, u16 packet_sz, u8 mode,
+				u32 dma_addr, u32 len, int tx)
+{
+	void *mbase = (void *)MUSB_BASE;
+	u8 bchannel = 0;
+	u16 csr = 0;
+
+	complete = 0;
+
+	/* check alignment for 32(0x20) */
+	if ((dma_addr % 32) != 0) {
+		//printf("%s: dma addr %#x is not aligned.\n", __func__, dma_addr);
+		return -1;
+	}
+	if ((len % 32) != 0) {
+		//printf("%s: dma xfer size %#x not aligned.\n", __func__, len);
+		return -1;
+	}
+
+	if (mode) {
+		csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
+		BUG_ON(len < packet_sz);
+	}
+	csr |= MUSB_HSDMA_BURSTMODE_INCR16
+				<< MUSB_HSDMA_BURSTMODE_SHIFT;
+
+	csr |= (epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
+		| (1 << MUSB_HSDMA_ENABLE_SHIFT)
+		| (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
+		| (tx ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
+				: 0);
+
+	start_addr = dma_addr;
+	dma_req_len = len;
+	/* address/count */
+	musb_write_hsdma_addr(mbase, bchannel, dma_addr);
+	musb_write_hsdma_count(mbase, bchannel, len);
+
+	if(tx)
+		flush_dcache_range(dma_addr, dma_addr+len);
+	else
+		invalidate_dcache_range(dma_addr, dma_addr+len);
+
+	/* control (this should start things) */
+	musb_writew(mbase,
+		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
+		csr);
+
+	return 0;
+}
+
+static int dma_controller_irq(void)
+{
+	void *mbase = (void *)MUSB_BASE;
+	u8 bchannel = 0;
+	u8 int_hsdma;
+
+	u32 addr;
+	u16 csr;
+	u32 actual_len;
+
+
+	int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
+
+	if (int_hsdma & (1 << bchannel)) {
+
+		csr = musb_readw(mbase,
+				MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
+					MUSB_HSDMA_CONTROL));
+
+		if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
+			serial_printf("dma bus error\n");
+		} else {
+			addr = musb_read_hsdma_addr(mbase,
+					bchannel);
+			actual_len = addr
+				- start_addr;
+			/*
+			   serial_printf("0x%x -> 0x%x (%zu / %d) %s\n",
+			   start_addr,
+			   addr, actual_len,
+			   dma_req_len,
+			   (actual_len
+			   < dma_req_len) ?
+			   "=> reconfig 0" : "=> complete");
+			 */
+			if (actual_len == dma_req_len)
+				complete = 1;
+		}
+	}
+
+	return 0;
+}
+
+int wait_dma_xfer_done(void)
+{
+	int timeout = 100000;
+
+	while(!complete && timeout) {
+		dma_controller_irq();
+		timeout--;
+	}
+	if (timeout <= 0) {
+		serial_printf("ERROR: dma xfer timeout\n");
+		return -1;
+	}
+
+	return 0;
+}
diff --git a/drivers/usb/musb/musbhsdma.h b/drivers/usb/musb/musbhsdma.h
new file mode 100644
index 0000000000..65d6700a03
--- /dev/null
+++ b/drivers/usb/musb/musbhsdma.h
@@ -0,0 +1,95 @@
+/*
+ * MUSB OTG driver - support for Mentor's DMA controller
+ *
+ * Copyright 2005 Mentor Graphics Corporation
+ * Copyright (C) 2005-2007 by Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#include <asm/io.h>
+
+static inline u8 musb_readb(const void *addr, unsigned offset)
+        { return readb(addr + offset); }
+
+static inline u16 musb_readw(const void *addr, unsigned offset)
+        { return readw(addr + offset); }
+
+static inline u32 musb_readl(const void *addr, unsigned offset)
+        { return readl(addr + offset); }
+
+
+static inline void musb_writeb(void *addr, unsigned offset, u8 data)
+        { writeb(data, addr + offset); }
+static inline void musb_writew(void *addr, unsigned offset, u16 data)
+        { writew(data, addr + offset); }
+
+static inline void musb_writel(void *addr, unsigned offset, u32 data)
+        { writel(data, addr + offset); }
+
+#define MUSB_HSDMA_BASE		0x200
+#define MUSB_HSDMA_INTR		(MUSB_HSDMA_BASE + 0)
+#define MUSB_HSDMA_CONTROL		0x4
+#define MUSB_HSDMA_ADDRESS		0x8
+#define MUSB_HSDMA_COUNT		0xc
+
+#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset)		\
+		(MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
+
+#define musb_read_hsdma_addr(mbase, bchannel)	\
+	musb_readl(mbase,	\
+		   MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))
+
+#define musb_write_hsdma_addr(mbase, bchannel, addr) \
+	musb_writel(mbase, \
+		    MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
+		    addr)
+
+#define musb_read_hsdma_count(mbase, bchannel)	\
+	musb_readl(mbase,	\
+		   MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT))
+
+#define musb_write_hsdma_count(mbase, bchannel, len) \
+	musb_writel(mbase, \
+		    MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
+		    len)
+
+/* control register (16-bit): */
+#define MUSB_HSDMA_ENABLE_SHIFT		0
+#define MUSB_HSDMA_TRANSMIT_SHIFT	1
+#define MUSB_HSDMA_MODE1_SHIFT		2
+#define MUSB_HSDMA_IRQENABLE_SHIFT	3
+#define MUSB_HSDMA_ENDPOINT_SHIFT	4
+#define MUSB_HSDMA_BUSERROR_SHIFT	8
+#define MUSB_HSDMA_BURSTMODE_SHIFT	9
+#define MUSB_HSDMA_BURSTMODE		(3 << MUSB_HSDMA_BURSTMODE_SHIFT)
+#define MUSB_HSDMA_BURSTMODE_UNSPEC	0
+#define MUSB_HSDMA_BURSTMODE_INCR4	1
+#define MUSB_HSDMA_BURSTMODE_INCR8	2
+#define MUSB_HSDMA_BURSTMODE_INCR16	3
+
+#define MUSB_HSDMA_CHANNELS		8
+
diff --git a/drivers/usb/musb/rda.c b/drivers/usb/musb/rda.c
new file mode 100644
index 0000000000..db2dbf52af
--- /dev/null
+++ b/drivers/usb/musb/rda.c
@@ -0,0 +1,212 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This is file is based on
+ * repository git.gitorious.org/u-boot-omap3/mainline.git,
+ * branch omap3-dev-usb, file drivers/usb/host/omap3530_usb.c
+ *
+ * This is the unique part of its copyright :
+ *
+ * ------------------------------------------------------------------------
+ *
+ * Copyright (c) 2009 Texas Instruments
+ *
+ * ------------------------------------------------------------------------
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include "rda.h"
+#include <asm/arch/reg_sysctrl.h>
+#include <asm/arch/hwcfg.h>
+#include <asm/arch/rda_sys.h>
+#include "musb_core.h"
+
+#define MONITOR_REG	(MUSB_BASE + 0x80)
+#define MONITOR_TRIG_REG	(MUSB_BASE + 0x84)
+#define UDC_PHY_CLK_REG	(MUSB_BASE + 0x8c)
+
+struct musb_config musb_cfg = {
+	.regs		= (struct musb_regs *)MUSB_BASE,
+	.timeout	= RDA_FPGA_USB_TIMEOUT,
+	.musb_speed	= 0,
+};
+
+static void udc_soft_reset(void)
+{
+	serial_printf("reset musb otg core...\n");
+	hwp_sysCtrlAp->AHB1_Rst_Set = SYS_CTRL_AP_SET_AHB1_RST_USBC;
+	udelay(1000);
+	hwp_sysCtrlAp->AHB1_Rst_Clr = SYS_CTRL_AP_CLR_AHB1_RST_USBC;
+}
+/*
+static void set_udc_monitor(int testcase)
+{
+	u32 value;
+
+	serial_printf("monitor trigger offset :%x \n", MONITOR_TRIG_REG);
+	value = 0x100 | (testcase & 0xff);
+	serial_printf("monitor trigger value :%x \n", value);
+	writel(value, MONITOR_TRIG_REG);
+
+	serial_printf("monitor offset :%x, result : %x\n", MONITOR_REG, readl(MONITOR_REG));
+}
+*/
+void udc_power_on(void)
+{
+}
+
+void udc_power_off(void)
+{
+}
+
+/*
+ udc maybe initialized by other module,always by ROM code
+ */
+int udc_is_initialized(void)
+{
+	/* some hacks for 8850E U02 USB issue, remove them in future. */
+#if defined(CONFIG_MACH_RDA8850E)
+	/* pdl1 always do hardware usb init */
+#if	defined(CONFIG_SPL_BUILD) && \
+	defined(CONFIG_RDA_PDL)
+	return 0;
+#endif
+	/* u-boot calib/autocall/pdl2 mode, need to do hardware usb init */
+#ifndef CONFIG_RDA_PDL
+	return 0;
+#endif
+#endif
+
+	return rda_bm_is_download();
+}
+
+static void udc_setup_pll(void)
+{
+	unsigned mask;
+	unsigned locked;
+	int cnt = 10; //timeout is in ms;
+
+	hwp_sysCtrlAp->Cfg_Pll_Ctrl[3] =
+	    SYS_CTRL_AP_AP_PLL_ENABLE_ENABLE |
+	    SYS_CTRL_AP_AP_PLL_LOCK_RESET_NO_RESET |
+	    SYS_CTRL_AP_AP_PLL_LOCK_NUM_LOW(6)
+	    | SYS_CTRL_AP_AP_PLL_LOCK_NUM_HIGH(30);
+
+	mask = SYS_CTRL_AP_PLL_LOCKED_USB_MASK;
+
+	locked = SYS_CTRL_AP_PLL_LOCKED_USB_LOCKED;
+
+	while (((hwp_sysCtrlAp->Sel_Clock & mask) != locked) && cnt) {
+		mdelay(1);
+		cnt--;
+	}
+	if (cnt == 0)
+		printf("ERROR, cannot lock usb pll\n");
+}
+
+static void musb_phy_init(void)
+{
+	udc_setup_pll();
+	/*
+	if (rda_metal_id_get() == 0) {
+		writel(0xf001, UDC_PHY_CLK_REG);
+	} else if (rda_metal_id_get() == 1) {
+		writel(0x5900f000, UDC_PHY_CLK_REG);
+	}
+	*/
+}
+
+int musb_platform_init(void)
+{
+	udc_soft_reset();
+	musb_phy_init();
+
+	return 0;
+}
+
+void musb_platform_deinit(void)
+{
+	/* noop */
+}
+
+void print_reg(void)
+{
+	u8 power;
+	u8 testmode;
+	u8 devctl;
+	musbr = musb_cfg.regs;
+	power = readb(&musbr->power);
+	testmode = readb(&musbr->testmode);
+	devctl = readb(&musbr->devctl);
+	printf("usb power: %x \n",power);
+	printf("usb testmode: %x \n",testmode);
+	printf("usb devctl: %x \n",devctl);
+}
+
+int do_usb_test(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	u8 devctl;
+	u8 test;
+	if (argc < 2 || argc > 3)
+		return CMD_RET_USAGE;
+	if (argc == 2) {
+		if (strcmp(argv[1],"init") == 0) {
+			musbr = musb_cfg.regs;
+			musb_platform_init();
+			musb_start();
+			devctl = readb(&musbr->devctl);
+			devctl |= MUSB_DEVCTL_SESSION;
+			writeb(devctl,&musbr->devctl);
+			printf("usb init finish\n");;
+		} else if (strcmp(argv[1],"j") == 0) {
+			test = readb(&musbr->testmode);
+			test &= ~(MUSB_TEST_K | MUSB_TEST_J);
+			test |= MUSB_TEST_J;
+			writeb(test,&musbr->testmode);
+			printf("usb test_j finish\n");
+		} else if (strcmp(argv[1],"k") == 0) {
+			test = readb(&musbr->testmode);
+			test &= ~(MUSB_TEST_K | MUSB_TEST_J);
+			test |= MUSB_TEST_K;
+			writeb(test,&musbr->testmode);
+			printf("usb test_k finish\n");
+		} else if (strcmp(argv[1],"host") == 0) {
+			writeb(MUSB_POWER_HSENAB,&musbr->power);
+			test = MUSB_TEST_FORCE_HOST | MUSB_TEST_FORCE_HS;
+			writeb(test,&musbr->testmode);
+			printf("usb force host finish\n");
+		} else {
+			printf("error argument!\n");
+			return CMD_RET_USAGE;
+		}
+#ifdef USB_TEST_DEBUG
+		print_reg();
+#endif
+	}
+	return 0;
+}
+
+U_BOOT_CMD(
+	usb_test, 2, 1, do_usb_test,
+	"rda usb slave test",
+	"[init, j, k, host]\n"
+	"	-init: 	USB INIT\n"
+	"	-j: 	TEST_J\n"
+	"	-k: 	TEST_k\n"
+	"	-host:	FORCE_HOST\n"
+);
diff --git a/drivers/usb/musb/rda.h b/drivers/usb/musb/rda.h
new file mode 100644
index 0000000000..751d421878
--- /dev/null
+++ b/drivers/usb/musb/rda.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This file is based on the file drivers/usb/musb/davinci.h
+ *
+ * This is the unique part of its copyright:
+ *
+ * --------------------------------------------------------------------
+ *
+ * Copyright (c) 2008 Texas Instruments
+ * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
+ *
+ * --------------------------------------------------------------------
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MUSB_RDA_H_
+#define _MUSB_RDA_H_
+
+#include <asm/arch/rda_iomap.h>
+#include "musb_core.h"
+
+/* Base address of MUSB registers */
+#define MUSB_BASE     RDA_USB_BASE
+
+/* Timeout for USB module */
+#define RDA_FPGA_USB_TIMEOUT 0x3FFFFFF
+
+int musb_platform_init(void);
+
+#endif /* _MUSB_RDA_H */
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 6252f6a25f..4fad20dd6e 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -28,7 +28,11 @@ LIB	:= $(obj)libvideo.o
 COBJS-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
 COBJS-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
 COBJS-$(CONFIG_CFB_CONSOLE) += cfb_console.o
+COBJS-$(CONFIG_EXYNOS_FB) += exynos_fb.o exynos_fimd.o
+COBJS-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \
+				exynos_mipi_dsi_lowlevel.o
 COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
+COBJS-$(CONFIG_S6E8AX0) += s6e8ax0.o
 COBJS-$(CONFIG_S6E63D6) += s6e63d6.o
 COBJS-$(CONFIG_SED156X) += sed156x.o
 COBJS-$(CONFIG_VIDEO_AMBA) += amba.o
diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c
new file mode 100644
index 0000000000..a1cf44964b
--- /dev/null
+++ b/drivers/video/exynos_fb.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: InKi Dae <inki.dae@samsung.com>
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <lcd.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/mipi_dsim.h>
+#include <asm/arch/system.h>
+
+#include "exynos_fb.h"
+
+int lcd_line_length;
+int lcd_color_fg;
+int lcd_color_bg;
+
+void *lcd_base;
+void *lcd_console_address;
+
+short console_col;
+short console_row;
+
+static unsigned int panel_width, panel_height;
+
+/* LCD Panel data */
+vidinfo_t panel_info;
+
+static void exynos_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
+{
+	unsigned long palette_size;
+	unsigned int fb_size;
+
+	fb_size = vid->vl_row * vid->vl_col * (NBITS(vid->vl_bpix) >> 3);
+
+	lcd_base = lcdbase;
+
+	palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
+
+	exynos_fimd_lcd_init_mem((unsigned long)lcd_base,
+			(unsigned long)fb_size, palette_size);
+}
+
+static void exynos_lcd_init(vidinfo_t *vid)
+{
+	exynos_fimd_lcd_init(vid);
+}
+
+static void lcd_panel_on(vidinfo_t *vid)
+{
+	udelay(vid->init_delay);
+
+	if (vid->backlight_reset)
+		vid->backlight_reset();
+
+	if (vid->cfg_gpio)
+		vid->cfg_gpio();
+
+	if (vid->lcd_power_on)
+		vid->lcd_power_on();
+
+	udelay(vid->power_on_delay);
+
+	if (vid->reset_lcd) {
+		vid->reset_lcd();
+		udelay(vid->reset_delay);
+	}
+
+	if (vid->backlight_on)
+		vid->backlight_on(1);
+
+	if (vid->cfg_ldo)
+		vid->cfg_ldo();
+
+	if (vid->enable_ldo)
+		vid->enable_ldo(1);
+
+	if (vid->mipi_enabled)
+		exynos_mipi_dsi_init();
+}
+
+void lcd_ctrl_init(void *lcdbase)
+{
+	set_system_display_ctrl();
+	set_lcd_clk();
+
+	/* initialize parameters which is specific to panel. */
+	init_panel_info(&panel_info);
+
+	panel_width = panel_info.vl_width;
+	panel_height = panel_info.vl_height;
+
+	exynos_lcd_init_mem(lcdbase, &panel_info);
+
+	exynos_lcd_init(&panel_info);
+}
+
+void lcd_enable(void)
+{
+	lcd_panel_on(&panel_info);
+}
+
+/* dummy function */
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
+{
+	return;
+}
diff --git a/drivers/video/exynos_fb.h b/drivers/video/exynos_fb.h
new file mode 100644
index 0000000000..66f5da6d46
--- /dev/null
+++ b/drivers/video/exynos_fb.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: InKi Dae <inki.dae@samsung.com>
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _EXYNOS_FB_H_
+#define _EXYNOS_FB_H_
+
+#include <asm/arch/fb.h>
+
+#define MAX_CLOCK	(86 * 1000000)
+
+enum exynos_fb_rgb_mode_t {
+	MODE_RGB_P = 0,
+	MODE_BGR_P = 1,
+	MODE_RGB_S = 2,
+	MODE_BGR_S = 3,
+};
+
+enum exynos_cpu_auto_cmd_rate {
+	DISABLE_AUTO_FRM,
+	PER_TWO_FRM,
+	PER_FOUR_FRM,
+	PER_SIX_FRM,
+	PER_EIGHT_FRM,
+	PER_TEN_FRM,
+	PER_TWELVE_FRM,
+	PER_FOURTEEN_FRM,
+	PER_SIXTEEN_FRM,
+	PER_EIGHTEEN_FRM,
+	PER_TWENTY_FRM,
+	PER_TWENTY_TWO_FRM,
+	PER_TWENTY_FOUR_FRM,
+	PER_TWENTY_SIX_FRM,
+	PER_TWENTY_EIGHT_FRM,
+	PER_THIRTY_FRM,
+};
+
+void exynos_fimd_lcd_init_mem(unsigned long screen_base, unsigned long fb_size,
+	unsigned long palette_size);
+void exynos_fimd_lcd_init(vidinfo_t *vid);
+unsigned long exynos_fimd_calc_fbsize(void);
+
+#endif
diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c
new file mode 100644
index 0000000000..6416b90fcc
--- /dev/null
+++ b/drivers/video/exynos_fimd.c
@@ -0,0 +1,354 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: InKi Dae <inki.dae@samsung.com>
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <lcd.h>
+#include <div64.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include "exynos_fb.h"
+
+static unsigned long *lcd_base_addr;
+static vidinfo_t *pvid;
+
+void exynos_fimd_lcd_init_mem(u_long screen_base, u_long fb_size,
+		u_long palette_size)
+{
+	lcd_base_addr = (unsigned long *)screen_base;
+}
+
+static void exynos_fimd_set_dualrgb(unsigned int enabled)
+{
+	struct exynos4_fb *fimd_ctrl =
+		(struct exynos4_fb *)samsung_get_base_fimd();
+	unsigned int cfg = 0;
+
+	if (enabled) {
+		cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT |
+			EXYNOS_DUALRGB_VDEN_EN_ENABLE;
+
+		/* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
+		cfg |= EXYNOS_DUALRGB_SUB_CNT(pvid->vl_col / 2) |
+			EXYNOS_DUALRGB_MAIN_CNT(0);
+	}
+
+	writel(cfg, &fimd_ctrl->dualrgb);
+}
+
+static void exynos_fimd_set_par(unsigned int win_id)
+{
+	unsigned int cfg = 0;
+	struct exynos4_fb *fimd_ctrl =
+		(struct exynos4_fb *)samsung_get_base_fimd();
+
+	/* set window control */
+	cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
+			EXYNOS_WINCON(win_id));
+
+	cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE |
+		EXYNOS_WINCON_HAWSWP_ENABLE | EXYNOS_WINCON_WSWP_ENABLE |
+		EXYNOS_WINCON_BURSTLEN_MASK | EXYNOS_WINCON_BPPMODE_MASK |
+		EXYNOS_WINCON_INRGB_MASK | EXYNOS_WINCON_DATAPATH_MASK);
+
+	/* DATAPATH is DMA */
+	cfg |= EXYNOS_WINCON_DATAPATH_DMA;
+
+	/* bpp is 32 */
+	cfg |= EXYNOS_WINCON_WSWP_ENABLE;
+
+	/* dma burst is 16 */
+	cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
+
+	/* pixel format is unpacked RGB888 */
+	cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
+
+	writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
+			EXYNOS_WINCON(win_id));
+
+	/* set window position to x=0, y=0*/
+	cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0);
+	writel(cfg, (unsigned int)&fimd_ctrl->vidosd0a +
+			EXYNOS_VIDOSD(win_id));
+
+	cfg = EXYNOS_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
+		EXYNOS_VIDOSD_BOTTOM_Y(pvid->vl_row - 1);
+	writel(cfg, (unsigned int)&fimd_ctrl->vidosd0b +
+			EXYNOS_VIDOSD(win_id));
+
+	/* set window size for window0*/
+	cfg = EXYNOS_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
+	writel(cfg, (unsigned int)&fimd_ctrl->vidosd0c +
+			EXYNOS_VIDOSD(win_id));
+}
+
+static void exynos_fimd_set_buffer_address(unsigned int win_id)
+{
+	unsigned long start_addr, end_addr;
+	struct exynos4_fb *fimd_ctrl =
+		(struct exynos4_fb *)samsung_get_base_fimd();
+
+	start_addr = (unsigned long)lcd_base_addr;
+	end_addr = start_addr + ((pvid->vl_col * (NBITS(pvid->vl_bpix) / 8)) *
+				pvid->vl_row);
+
+	writel(start_addr, (unsigned int)&fimd_ctrl->vidw00add0b0 +
+			EXYNOS_BUFFER_OFFSET(win_id));
+	writel(end_addr, (unsigned int)&fimd_ctrl->vidw00add1b0 +
+			EXYNOS_BUFFER_OFFSET(win_id));
+}
+
+static void exynos_fimd_set_clock(vidinfo_t *pvid)
+{
+	unsigned int cfg = 0, div = 0, remainder, remainder_div;
+	unsigned long pixel_clock;
+	unsigned long long src_clock;
+	struct exynos4_fb *fimd_ctrl =
+		(struct exynos4_fb *)samsung_get_base_fimd();
+
+	if (pvid->dual_lcd_enabled) {
+		pixel_clock = pvid->vl_freq *
+				(pvid->vl_hspw + pvid->vl_hfpd +
+				 pvid->vl_hbpd + pvid->vl_col / 2) *
+				(pvid->vl_vspw + pvid->vl_vfpd +
+				 pvid->vl_vbpd + pvid->vl_row);
+	} else if (pvid->interface_mode == FIMD_CPU_INTERFACE) {
+		pixel_clock = pvid->vl_freq *
+				pvid->vl_width * pvid->vl_height *
+				(pvid->cs_setup + pvid->wr_setup +
+				 pvid->wr_act + pvid->wr_hold + 1);
+	} else {
+		pixel_clock = pvid->vl_freq *
+				(pvid->vl_hspw + pvid->vl_hfpd +
+				 pvid->vl_hbpd + pvid->vl_col) *
+				(pvid->vl_vspw + pvid->vl_vfpd +
+				 pvid->vl_vbpd + pvid->vl_row);
+	}
+
+	cfg = readl(&fimd_ctrl->vidcon0);
+	cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK |
+		EXYNOS_VIDCON0_CLKVAL_F(0xFF) | EXYNOS_VIDCON0_VCLKEN_MASK |
+		EXYNOS_VIDCON0_CLKDIR_MASK);
+	cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS |
+		EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED);
+
+	if (pixel_clock > MAX_CLOCK)
+		pixel_clock = MAX_CLOCK;
+
+	src_clock = (unsigned long long) get_lcd_clk();
+
+	/* get quotient and remainder. */
+	remainder = do_div(src_clock, pixel_clock);
+	div = src_clock;
+
+	remainder *= 10;
+	remainder_div = remainder / pixel_clock;
+
+	/* round about one places of decimals. */
+	if (remainder_div >= 5)
+		div++;
+
+	/* in case of dual lcd mode. */
+	if (pvid->dual_lcd_enabled)
+		div--;
+
+	cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1);
+	writel(cfg, &fimd_ctrl->vidcon0);
+}
+
+void exynos_set_trigger(void)
+{
+	unsigned int cfg = 0;
+	struct exynos4_fb *fimd_ctrl =
+		(struct exynos4_fb *)samsung_get_base_fimd();
+
+	cfg = readl(&fimd_ctrl->trigcon);
+
+	cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG);
+
+	writel(cfg, &fimd_ctrl->trigcon);
+}
+
+int exynos_is_i80_frame_done(void)
+{
+	unsigned int cfg = 0;
+	int status;
+	struct exynos4_fb *fimd_ctrl =
+		(struct exynos4_fb *)samsung_get_base_fimd();
+
+	cfg = readl(&fimd_ctrl->trigcon);
+
+	/* frame done func is valid only when TRIMODE[0] is set to 1. */
+	status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) ==
+			EXYNOS_I80STATUS_TRIG_DONE;
+
+	return status;
+}
+
+static void exynos_fimd_lcd_on(void)
+{
+	unsigned int cfg = 0;
+	struct exynos4_fb *fimd_ctrl =
+		(struct exynos4_fb *)samsung_get_base_fimd();
+
+	/* display on */
+	cfg = readl(&fimd_ctrl->vidcon0);
+	cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE);
+	writel(cfg, &fimd_ctrl->vidcon0);
+}
+
+static void exynos_fimd_window_on(unsigned int win_id)
+{
+	unsigned int cfg = 0;
+	struct exynos4_fb *fimd_ctrl =
+		(struct exynos4_fb *)samsung_get_base_fimd();
+
+	/* enable window */
+	cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
+			EXYNOS_WINCON(win_id));
+	cfg |= EXYNOS_WINCON_ENWIN_ENABLE;
+	writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
+			EXYNOS_WINCON(win_id));
+
+	cfg = readl(&fimd_ctrl->winshmap);
+	cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id);
+	writel(cfg, &fimd_ctrl->winshmap);
+}
+
+void exynos_fimd_lcd_off(void)
+{
+	unsigned int cfg = 0;
+	struct exynos4_fb *fimd_ctrl =
+		(struct exynos4_fb *)samsung_get_base_fimd();
+
+	cfg = readl(&fimd_ctrl->vidcon0);
+	cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE);
+	writel(cfg, &fimd_ctrl->vidcon0);
+}
+
+void exynos_fimd_window_off(unsigned int win_id)
+{
+	unsigned int cfg = 0;
+	struct exynos4_fb *fimd_ctrl =
+		(struct exynos4_fb *)samsung_get_base_fimd();
+
+	cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
+			EXYNOS_WINCON(win_id));
+	cfg &= EXYNOS_WINCON_ENWIN_DISABLE;
+	writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
+			EXYNOS_WINCON(win_id));
+
+	cfg = readl(&fimd_ctrl->winshmap);
+	cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id);
+	writel(cfg, &fimd_ctrl->winshmap);
+}
+
+void exynos_fimd_lcd_init(vidinfo_t *vid)
+{
+	unsigned int cfg = 0, rgb_mode;
+	struct exynos4_fb *fimd_ctrl =
+		(struct exynos4_fb *)samsung_get_base_fimd();
+
+	/* store panel info to global variable */
+	pvid = vid;
+
+	rgb_mode = MODE_RGB_P;
+
+	if (vid->interface_mode == FIMD_RGB_INTERFACE) {
+		cfg |= EXYNOS_VIDCON0_VIDOUT_RGB;
+		writel(cfg, &fimd_ctrl->vidcon0);
+
+		cfg = readl(&fimd_ctrl->vidcon2);
+		cfg &= ~(EXYNOS_VIDCON2_WB_MASK |
+			EXYNOS_VIDCON2_TVFORMATSEL_MASK |
+			EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK);
+		cfg |= EXYNOS_VIDCON2_WB_DISABLE;
+		writel(cfg, &fimd_ctrl->vidcon2);
+
+		/* set polarity */
+		cfg = 0;
+		if (!pvid->vl_clkp)
+			cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE;
+		if (!pvid->vl_hsp)
+			cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT;
+		if (!pvid->vl_vsp)
+			cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT;
+		if (!pvid->vl_dp)
+			cfg |= EXYNOS_VIDCON1_IVDEN_INVERT;
+
+		writel(cfg, &fimd_ctrl->vidcon1);
+
+		/* set timing */
+		cfg = EXYNOS_VIDTCON0_VFPD(pvid->vl_vfpd - 1);
+		cfg |= EXYNOS_VIDTCON0_VBPD(pvid->vl_vbpd - 1);
+		cfg |= EXYNOS_VIDTCON0_VSPW(pvid->vl_vspw - 1);
+		writel(cfg, &fimd_ctrl->vidtcon0);
+
+		cfg = EXYNOS_VIDTCON1_HFPD(pvid->vl_hfpd - 1);
+		cfg |= EXYNOS_VIDTCON1_HBPD(pvid->vl_hbpd - 1);
+		cfg |= EXYNOS_VIDTCON1_HSPW(pvid->vl_hspw - 1);
+
+		writel(cfg, &fimd_ctrl->vidtcon1);
+
+		/* set lcd size */
+		cfg = EXYNOS_VIDTCON2_HOZVAL(pvid->vl_col - 1);
+		cfg |= EXYNOS_VIDTCON2_LINEVAL(pvid->vl_row - 1);
+
+		writel(cfg, &fimd_ctrl->vidtcon2);
+	}
+
+	/* set display mode */
+	cfg = readl(&fimd_ctrl->vidcon0);
+	cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK;
+	cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT);
+	writel(cfg, &fimd_ctrl->vidcon0);
+
+	/* set par */
+	exynos_fimd_set_par(pvid->win_id);
+
+	/* set memory address */
+	exynos_fimd_set_buffer_address(pvid->win_id);
+
+	/* set buffer size */
+	cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col * NBITS(pvid->vl_bpix) / 8);
+	writel(cfg, (unsigned int)&fimd_ctrl->vidw00add2 +
+					EXYNOS_BUFFER_SIZE(pvid->win_id));
+
+	/* set clock */
+	exynos_fimd_set_clock(pvid);
+
+	/* set rgb mode to dual lcd. */
+	exynos_fimd_set_dualrgb(pvid->dual_lcd_enabled);
+
+	/* display on */
+	exynos_fimd_lcd_on();
+
+	/* window on */
+	exynos_fimd_window_on(pvid->win_id);
+}
+
+unsigned long exynos_fimd_calc_fbsize(void)
+{
+	return pvid->vl_col * pvid->vl_row * (NBITS(pvid->vl_bpix) / 8);
+}
diff --git a/drivers/video/exynos_mipi_dsi.c b/drivers/video/exynos_mipi_dsi.c
new file mode 100644
index 0000000000..aee248c84f
--- /dev/null
+++ b/drivers/video/exynos_mipi_dsi.c
@@ -0,0 +1,253 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: InKi Dae <inki.dae@samsung.com>
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <linux/err.h>
+#include <asm/arch/dsim.h>
+#include <asm/arch/mipi_dsim.h>
+#include <asm/arch/power.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+
+#include "exynos_mipi_dsi_lowlevel.h"
+#include "exynos_mipi_dsi_common.h"
+
+#define master_to_driver(a)	(a->dsim_lcd_drv)
+#define master_to_device(a)	(a->dsim_lcd_dev)
+
+static struct exynos_platform_mipi_dsim *dsim_pd;
+
+struct mipi_dsim_ddi {
+	int				bus_id;
+	struct list_head		list;
+	struct mipi_dsim_lcd_device	*dsim_lcd_dev;
+	struct mipi_dsim_lcd_driver	*dsim_lcd_drv;
+};
+
+static LIST_HEAD(dsim_ddi_list);
+static LIST_HEAD(dsim_lcd_dev_list);
+
+int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device *lcd_dev)
+{
+	struct mipi_dsim_ddi *dsim_ddi;
+
+	if (!lcd_dev) {
+		debug("mipi_dsim_lcd_device is NULL.\n");
+		return -EFAULT;
+	}
+
+	if (!lcd_dev->name) {
+		debug("dsim_lcd_device name is NULL.\n");
+		return -EFAULT;
+	}
+
+	dsim_ddi = kzalloc(sizeof(struct mipi_dsim_ddi), GFP_KERNEL);
+	if (!dsim_ddi) {
+		debug("failed to allocate dsim_ddi object.\n");
+		return -EFAULT;
+	}
+
+	dsim_ddi->dsim_lcd_dev = lcd_dev;
+
+	list_add_tail(&dsim_ddi->list, &dsim_ddi_list);
+
+	return 0;
+}
+
+struct mipi_dsim_ddi
+	*exynos_mipi_dsi_find_lcd_device(struct mipi_dsim_lcd_driver *lcd_drv)
+{
+	struct mipi_dsim_ddi *dsim_ddi;
+	struct mipi_dsim_lcd_device *lcd_dev;
+
+	list_for_each_entry(dsim_ddi, &dsim_ddi_list, list) {
+		lcd_dev = dsim_ddi->dsim_lcd_dev;
+		if (!lcd_dev)
+			continue;
+
+		if (lcd_drv->id >= 0) {
+			if ((strcmp(lcd_drv->name, lcd_dev->name)) == 0 &&
+					lcd_drv->id == lcd_dev->id) {
+				/**
+				 * bus_id would be used to identify
+				 * connected bus.
+				 */
+				dsim_ddi->bus_id = lcd_dev->bus_id;
+
+				return dsim_ddi;
+			}
+		} else {
+			if ((strcmp(lcd_drv->name, lcd_dev->name)) == 0) {
+				/**
+				 * bus_id would be used to identify
+				 * connected bus.
+				 */
+				dsim_ddi->bus_id = lcd_dev->bus_id;
+
+				return dsim_ddi;
+			}
+		}
+
+		kfree(dsim_ddi);
+		list_del(&dsim_ddi_list);
+	}
+
+	return NULL;
+}
+
+int exynos_mipi_dsi_register_lcd_driver(struct mipi_dsim_lcd_driver *lcd_drv)
+{
+	struct mipi_dsim_ddi *dsim_ddi;
+
+	if (!lcd_drv) {
+		debug("mipi_dsim_lcd_driver is NULL.\n");
+		return -EFAULT;
+	}
+
+	if (!lcd_drv->name) {
+		debug("dsim_lcd_driver name is NULL.\n");
+		return -EFAULT;
+	}
+
+	dsim_ddi = exynos_mipi_dsi_find_lcd_device(lcd_drv);
+	if (!dsim_ddi) {
+		debug("mipi_dsim_ddi object not found.\n");
+		return -EFAULT;
+	}
+
+	dsim_ddi->dsim_lcd_drv = lcd_drv;
+
+	debug("registered panel driver(%s) to mipi-dsi driver.\n",
+		lcd_drv->name);
+
+	return 0;
+
+}
+
+struct mipi_dsim_ddi
+	*exynos_mipi_dsi_bind_lcd_ddi(struct mipi_dsim_device *dsim,
+			const char *name)
+{
+	struct mipi_dsim_ddi *dsim_ddi;
+	struct mipi_dsim_lcd_driver *lcd_drv;
+	struct mipi_dsim_lcd_device *lcd_dev;
+
+	list_for_each_entry(dsim_ddi, &dsim_ddi_list, list) {
+		lcd_drv = dsim_ddi->dsim_lcd_drv;
+		lcd_dev = dsim_ddi->dsim_lcd_dev;
+		if (!lcd_drv || !lcd_dev)
+			continue;
+
+		debug("lcd_drv->id = %d, lcd_dev->id = %d\n",
+					lcd_drv->id, lcd_dev->id);
+
+		if ((strcmp(lcd_drv->name, name) == 0)) {
+			lcd_dev->master = dsim;
+
+			dsim->dsim_lcd_dev = lcd_dev;
+			dsim->dsim_lcd_drv = lcd_drv;
+
+			return dsim_ddi;
+		}
+	}
+
+	return NULL;
+}
+
+/* define MIPI-DSI Master operations. */
+static struct mipi_dsim_master_ops master_ops = {
+	.cmd_write			= exynos_mipi_dsi_wr_data,
+	.get_dsim_frame_done		= exynos_mipi_dsi_get_frame_done_status,
+	.clear_dsim_frame_done		= exynos_mipi_dsi_clear_frame_done,
+};
+
+int exynos_mipi_dsi_init(void)
+{
+	struct mipi_dsim_device *dsim;
+	struct mipi_dsim_config *dsim_config;
+	struct mipi_dsim_ddi *dsim_ddi;
+
+	dsim = kzalloc(sizeof(struct mipi_dsim_device), GFP_KERNEL);
+	if (!dsim) {
+		debug("failed to allocate dsim object.\n");
+		return -EFAULT;
+	}
+
+	/* get mipi_dsim_config. */
+	dsim_config = dsim_pd->dsim_config;
+	if (dsim_config == NULL) {
+		debug("failed to get dsim config data.\n");
+		return -EFAULT;
+	}
+
+	dsim->pd = dsim_pd;
+	dsim->dsim_config = dsim_config;
+	dsim->master_ops = &master_ops;
+
+	/* bind lcd ddi matched with panel name. */
+	dsim_ddi = exynos_mipi_dsi_bind_lcd_ddi(dsim, dsim_pd->lcd_panel_name);
+	if (!dsim_ddi) {
+		debug("mipi_dsim_ddi object not found.\n");
+		return -ENOSYS;
+	}
+	if (dsim_pd->lcd_power)
+		dsim_pd->lcd_power();
+
+	if (dsim_pd->mipi_power)
+		dsim_pd->mipi_power();
+
+	/* phy_enable(unsigned int dev_index, unsigned int enable) */
+	if (dsim_pd->phy_enable)
+		dsim_pd->phy_enable(0, 1);
+
+	set_mipi_clk();
+
+	exynos_mipi_dsi_init_dsim(dsim);
+	exynos_mipi_dsi_init_link(dsim);
+	exynos_mipi_dsi_set_hs_enable(dsim);
+
+	/* set display timing. */
+	exynos_mipi_dsi_set_display_mode(dsim, dsim->dsim_config);
+
+	/* initialize mipi-dsi client(lcd panel). */
+	if (dsim_ddi->dsim_lcd_drv && dsim_ddi->dsim_lcd_drv->mipi_panel_init) {
+		dsim_ddi->dsim_lcd_drv->mipi_panel_init(dsim);
+		dsim_ddi->dsim_lcd_drv->mipi_display_on(dsim);
+	}
+
+	debug("mipi-dsi driver(%s mode) has been probed.\n",
+		(dsim_config->e_interface == DSIM_COMMAND) ?
+			"CPU" : "RGB");
+
+	return 0;
+}
+
+void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd)
+{
+	if (pd == NULL) {
+		debug("pd is NULL\n");
+		return;
+	}
+
+	dsim_pd = pd;
+}
diff --git a/drivers/video/exynos_mipi_dsi_common.c b/drivers/video/exynos_mipi_dsi_common.c
new file mode 100644
index 0000000000..6eeb46424f
--- /dev/null
+++ b/drivers/video/exynos_mipi_dsi_common.c
@@ -0,0 +1,637 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: InKi Dae <inki.dae@samsung.com>
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <lcd.h>
+#include <linux/err.h>
+#include <asm/arch/dsim.h>
+#include <asm/arch/mipi_dsim.h>
+
+#include "exynos_mipi_dsi_lowlevel.h"
+
+#define MHZ			(1000 * 1000)
+#define FIN_HZ			(24 * MHZ)
+
+#define DFIN_PLL_MIN_HZ		(6 * MHZ)
+#define DFIN_PLL_MAX_HZ		(12 * MHZ)
+
+#define DFVCO_MIN_HZ		(500 * MHZ)
+#define DFVCO_MAX_HZ		(1000 * MHZ)
+
+#define TRY_GET_FIFO_TIMEOUT	(5000 * 2)
+
+/* MIPI-DSIM status types. */
+enum {
+	DSIM_STATE_INIT,	/* should be initialized. */
+	DSIM_STATE_STOP,	/* CPU and LCDC are LP mode. */
+	DSIM_STATE_HSCLKEN,	/* HS clock was enabled. */
+	DSIM_STATE_ULPS
+};
+
+/* define DSI lane types. */
+enum {
+	DSIM_LANE_CLOCK = (1 << 0),
+	DSIM_LANE_DATA0 = (1 << 1),
+	DSIM_LANE_DATA1 = (1 << 2),
+	DSIM_LANE_DATA2 = (1 << 3),
+	DSIM_LANE_DATA3 = (1 << 4)
+};
+
+static unsigned int dpll_table[15] = {
+	100, 120, 170, 220, 270,
+	320, 390, 450, 510, 560,
+	640, 690, 770, 870, 950
+};
+
+static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim,
+		unsigned int data0, unsigned int data1)
+{
+	unsigned int data_cnt = 0, payload = 0;
+
+	/* in case that data count is more then 4 */
+	for (data_cnt = 0; data_cnt < data1; data_cnt += 4) {
+		/*
+		 * after sending 4bytes per one time,
+		 * send remainder data less then 4.
+		 */
+		if ((data1 - data_cnt) < 4) {
+			if ((data1 - data_cnt) == 3) {
+				payload = *(u8 *)(data0 + data_cnt) |
+					(*(u8 *)(data0 + (data_cnt + 1))) << 8 |
+					(*(u8 *)(data0 + (data_cnt + 2))) << 16;
+			debug("count = 3 payload = %x, %x %x %x\n",
+				payload, *(u8 *)(data0 + data_cnt),
+				*(u8 *)(data0 + (data_cnt + 1)),
+				*(u8 *)(data0 + (data_cnt + 2)));
+			} else if ((data1 - data_cnt) == 2) {
+				payload = *(u8 *)(data0 + data_cnt) |
+					(*(u8 *)(data0 + (data_cnt + 1))) << 8;
+			debug("count = 2 payload = %x, %x %x\n", payload,
+				*(u8 *)(data0 + data_cnt),
+				*(u8 *)(data0 + (data_cnt + 1)));
+			} else if ((data1 - data_cnt) == 1) {
+				payload = *(u8 *)(data0 + data_cnt);
+			}
+		} else {
+			/* send 4bytes per one time. */
+			payload = *(u8 *)(data0 + data_cnt) |
+				(*(u8 *)(data0 + (data_cnt + 1))) << 8 |
+				(*(u8 *)(data0 + (data_cnt + 2))) << 16 |
+				(*(u8 *)(data0 + (data_cnt + 3))) << 24;
+
+			debug("count = 4 payload = %x, %x %x %x %x\n",
+				payload, *(u8 *)(data0 + data_cnt),
+				*(u8 *)(data0 + (data_cnt + 1)),
+				*(u8 *)(data0 + (data_cnt + 2)),
+				*(u8 *)(data0 + (data_cnt + 3)));
+
+		}
+		exynos_mipi_dsi_wr_tx_data(dsim, payload);
+	}
+}
+
+int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
+	unsigned int data0, unsigned int data1)
+{
+	unsigned int timeout = TRY_GET_FIFO_TIMEOUT;
+	unsigned long delay_val, delay;
+	unsigned int check_rx_ack = 0;
+
+	if (dsim->state == DSIM_STATE_ULPS) {
+		debug("state is ULPS.\n");
+
+		return -EINVAL;
+	}
+
+	delay_val = MHZ / dsim->dsim_config->esc_clk;
+	delay = 10 * delay_val;
+
+	mdelay(delay);
+
+	/* only if transfer mode is LPDT, wait SFR becomes empty. */
+	if (dsim->state == DSIM_STATE_STOP) {
+		while (!(exynos_mipi_dsi_get_fifo_state(dsim) &
+				SFR_HEADER_EMPTY)) {
+			if ((timeout--) > 0)
+				mdelay(1);
+			else {
+				debug("SRF header fifo is not empty.\n");
+				return -EINVAL;
+			}
+		}
+	}
+
+	switch (data_id) {
+	/* short packet types of packet types for command. */
+	case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
+	case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
+	case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
+	case MIPI_DSI_DCS_SHORT_WRITE:
+	case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
+	case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
+		debug("data0 = %x data1 = %x\n",
+				data0, data1);
+		exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1);
+		if (check_rx_ack) {
+			/* process response func should be implemented */
+			return 0;
+		} else {
+			return -EINVAL;
+		}
+
+	/* general command */
+	case MIPI_DSI_COLOR_MODE_OFF:
+	case MIPI_DSI_COLOR_MODE_ON:
+	case MIPI_DSI_SHUTDOWN_PERIPHERAL:
+	case MIPI_DSI_TURN_ON_PERIPHERAL:
+		exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1);
+		if (check_rx_ack) {
+			/* process response func should be implemented. */
+			return 0;
+		} else {
+			return -EINVAL;
+		}
+
+	/* packet types for video data */
+	case MIPI_DSI_V_SYNC_START:
+	case MIPI_DSI_V_SYNC_END:
+	case MIPI_DSI_H_SYNC_START:
+	case MIPI_DSI_H_SYNC_END:
+	case MIPI_DSI_END_OF_TRANSMISSION:
+		return 0;
+
+	/* short and response packet types for command */
+	case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
+	case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
+	case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
+	case MIPI_DSI_DCS_READ:
+		exynos_mipi_dsi_clear_all_interrupt(dsim);
+		exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1);
+		/* process response func should be implemented. */
+		return 0;
+
+	/* long packet type and null packet */
+	case MIPI_DSI_NULL_PACKET:
+	case MIPI_DSI_BLANKING_PACKET:
+		return 0;
+	case MIPI_DSI_GENERIC_LONG_WRITE:
+	case MIPI_DSI_DCS_LONG_WRITE:
+	{
+		unsigned int data_cnt = 0, payload = 0;
+
+		/* if data count is less then 4, then send 3bytes data.  */
+		if (data1 < 4) {
+			payload = *(u8 *)(data0) |
+				*(u8 *)(data0 + 1) << 8 |
+				*(u8 *)(data0 + 2) << 16;
+
+			exynos_mipi_dsi_wr_tx_data(dsim, payload);
+
+			debug("count = %d payload = %x,%x %x %x\n",
+				data1, payload,
+				*(u8 *)(data0 + data_cnt),
+				*(u8 *)(data0 + (data_cnt + 1)),
+				*(u8 *)(data0 + (data_cnt + 2)));
+		} else {
+			/* in case that data count is more then 4 */
+			exynos_mipi_dsi_long_data_wr(dsim, data0, data1);
+		}
+
+		/* put data into header fifo */
+		exynos_mipi_dsi_wr_tx_header(dsim, data_id, data1 & 0xff,
+			(data1 & 0xff00) >> 8);
+
+	}
+	if (check_rx_ack)
+		/* process response func should be implemented. */
+		return 0;
+	else
+		return -EINVAL;
+
+	/* packet typo for video data */
+	case MIPI_DSI_PACKED_PIXEL_STREAM_16:
+	case MIPI_DSI_PACKED_PIXEL_STREAM_18:
+	case MIPI_DSI_PIXEL_STREAM_3BYTE_18:
+	case MIPI_DSI_PACKED_PIXEL_STREAM_24:
+		if (check_rx_ack) {
+			/* process response func should be implemented. */
+			return 0;
+		} else {
+			return -EINVAL;
+		}
+	default:
+		debug("data id %x is not supported current DSI spec.\n",
+			data_id);
+
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim, unsigned int enable)
+{
+	int sw_timeout;
+
+	if (enable) {
+		sw_timeout = 1000;
+
+		exynos_mipi_dsi_clear_interrupt(dsim);
+		exynos_mipi_dsi_enable_pll(dsim, 1);
+		while (1) {
+			sw_timeout--;
+			if (exynos_mipi_dsi_is_pll_stable(dsim))
+				return 0;
+			if (sw_timeout == 0)
+				return -EINVAL;
+		}
+	} else
+		exynos_mipi_dsi_enable_pll(dsim, 0);
+
+	return 0;
+}
+
+unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,
+	unsigned int pre_divider, unsigned int main_divider,
+	unsigned int scaler)
+{
+	unsigned long dfin_pll, dfvco, dpll_out;
+	unsigned int i, freq_band = 0xf;
+
+	dfin_pll = (FIN_HZ / pre_divider);
+
+	/******************************************************
+	 *	Serial Clock(=ByteClk X 8)	FreqBand[3:0] *
+	 ******************************************************
+	 *	~ 99.99 MHz			0000
+	 *	100 ~ 119.99 MHz		0001
+	 *	120 ~ 159.99 MHz		0010
+	 *	160 ~ 199.99 MHz		0011
+	 *	200 ~ 239.99 MHz		0100
+	 *	140 ~ 319.99 MHz		0101
+	 *	320 ~ 389.99 MHz		0110
+	 *	390 ~ 449.99 MHz		0111
+	 *	450 ~ 509.99 MHz		1000
+	 *	510 ~ 559.99 MHz		1001
+	 *	560 ~ 639.99 MHz		1010
+	 *	640 ~ 689.99 MHz		1011
+	 *	690 ~ 769.99 MHz		1100
+	 *	770 ~ 869.99 MHz		1101
+	 *	870 ~ 949.99 MHz		1110
+	 *	950 ~ 1000 MHz			1111
+	 ******************************************************/
+	if (dfin_pll < DFIN_PLL_MIN_HZ || dfin_pll > DFIN_PLL_MAX_HZ) {
+		debug("fin_pll range should be 6MHz ~ 12MHz\n");
+		exynos_mipi_dsi_enable_afc(dsim, 0, 0);
+	} else {
+		if (dfin_pll < 7 * MHZ)
+			exynos_mipi_dsi_enable_afc(dsim, 1, 0x1);
+		else if (dfin_pll < 8 * MHZ)
+			exynos_mipi_dsi_enable_afc(dsim, 1, 0x0);
+		else if (dfin_pll < 9 * MHZ)
+			exynos_mipi_dsi_enable_afc(dsim, 1, 0x3);
+		else if (dfin_pll < 10 * MHZ)
+			exynos_mipi_dsi_enable_afc(dsim, 1, 0x2);
+		else if (dfin_pll < 11 * MHZ)
+			exynos_mipi_dsi_enable_afc(dsim, 1, 0x5);
+		else
+			exynos_mipi_dsi_enable_afc(dsim, 1, 0x4);
+	}
+
+	dfvco = dfin_pll * main_divider;
+	debug("dfvco = %lu, dfin_pll = %lu, main_divider = %d\n",
+				dfvco, dfin_pll, main_divider);
+	if (dfvco < DFVCO_MIN_HZ || dfvco > DFVCO_MAX_HZ)
+		debug("fvco range should be 500MHz ~ 1000MHz\n");
+
+	dpll_out = dfvco / (1 << scaler);
+	debug("dpll_out = %lu, dfvco = %lu, scaler = %d\n",
+		dpll_out, dfvco, scaler);
+
+	for (i = 0; i < ARRAY_SIZE(dpll_table); i++) {
+		if (dpll_out < dpll_table[i] * MHZ) {
+			freq_band = i;
+			break;
+		}
+	}
+
+	debug("freq_band = %d\n", freq_band);
+
+	exynos_mipi_dsi_pll_freq(dsim, pre_divider, main_divider, scaler);
+
+	exynos_mipi_dsi_hs_zero_ctrl(dsim, 0);
+	exynos_mipi_dsi_prep_ctrl(dsim, 0);
+
+	/* Freq Band */
+	exynos_mipi_dsi_pll_freq_band(dsim, freq_band);
+
+	/* Stable time */
+	exynos_mipi_dsi_pll_stable_time(dsim,
+				dsim->dsim_config->pll_stable_time);
+
+	/* Enable PLL */
+	debug("FOUT of mipi dphy pll is %luMHz\n",
+		(dpll_out / MHZ));
+
+	return dpll_out;
+}
+
+int exynos_mipi_dsi_set_clock(struct mipi_dsim_device *dsim,
+	unsigned int byte_clk_sel, unsigned int enable)
+{
+	unsigned int esc_div;
+	unsigned long esc_clk_error_rate;
+	unsigned long hs_clk = 0, byte_clk = 0, escape_clk = 0;
+
+	if (enable) {
+		dsim->e_clk_src = byte_clk_sel;
+
+		/* Escape mode clock and byte clock source */
+		exynos_mipi_dsi_set_byte_clock_src(dsim, byte_clk_sel);
+
+		/* DPHY, DSIM Link : D-PHY clock out */
+		if (byte_clk_sel == DSIM_PLL_OUT_DIV8) {
+			hs_clk = exynos_mipi_dsi_change_pll(dsim,
+				dsim->dsim_config->p, dsim->dsim_config->m,
+				dsim->dsim_config->s);
+			if (hs_clk == 0) {
+				debug("failed to get hs clock.\n");
+				return -EINVAL;
+			}
+
+			byte_clk = hs_clk / 8;
+			exynos_mipi_dsi_enable_pll_bypass(dsim, 0);
+			exynos_mipi_dsi_pll_on(dsim, 1);
+		/* DPHY : D-PHY clock out, DSIM link : external clock out */
+		} else if (byte_clk_sel == DSIM_EXT_CLK_DIV8)
+			debug("not support EXT CLK source for MIPI DSIM\n");
+		else if (byte_clk_sel == DSIM_EXT_CLK_BYPASS)
+			debug("not support EXT CLK source for MIPI DSIM\n");
+
+		/* escape clock divider */
+		esc_div = byte_clk / (dsim->dsim_config->esc_clk);
+		debug("esc_div = %d, byte_clk = %lu, esc_clk = %lu\n",
+			esc_div, byte_clk, dsim->dsim_config->esc_clk);
+		if ((byte_clk / esc_div) >= (20 * MHZ) ||
+			(byte_clk / esc_div) > dsim->dsim_config->esc_clk)
+			esc_div += 1;
+
+		escape_clk = byte_clk / esc_div;
+		debug("escape_clk = %lu, byte_clk = %lu, esc_div = %d\n",
+			escape_clk, byte_clk, esc_div);
+
+		/* enable escape clock. */
+		exynos_mipi_dsi_enable_byte_clock(dsim, 1);
+
+		/* enable byte clk and escape clock */
+		exynos_mipi_dsi_set_esc_clk_prs(dsim, 1, esc_div);
+		/* escape clock on lane */
+		exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
+			(DSIM_LANE_CLOCK | dsim->data_lane), 1);
+
+		debug("byte clock is %luMHz\n",
+			(byte_clk / MHZ));
+		debug("escape clock that user's need is %lu\n",
+			(dsim->dsim_config->esc_clk / MHZ));
+		debug("escape clock divider is %x\n", esc_div);
+		debug("escape clock is %luMHz\n",
+			((byte_clk / esc_div) / MHZ));
+
+		if ((byte_clk / esc_div) > escape_clk) {
+			esc_clk_error_rate = escape_clk /
+				(byte_clk / esc_div);
+			debug("error rate is %lu over.\n",
+				(esc_clk_error_rate / 100));
+		} else if ((byte_clk / esc_div) < (escape_clk)) {
+			esc_clk_error_rate = (byte_clk / esc_div) /
+				escape_clk;
+			debug("error rate is %lu under.\n",
+				(esc_clk_error_rate / 100));
+		}
+	} else {
+		exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
+			(DSIM_LANE_CLOCK | dsim->data_lane), 0);
+		exynos_mipi_dsi_set_esc_clk_prs(dsim, 0, 0);
+
+		/* disable escape clock. */
+		exynos_mipi_dsi_enable_byte_clock(dsim, 0);
+
+		if (byte_clk_sel == DSIM_PLL_OUT_DIV8)
+			exynos_mipi_dsi_pll_on(dsim, 0);
+	}
+
+	return 0;
+}
+
+int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim)
+{
+	dsim->state = DSIM_STATE_INIT;
+
+	switch (dsim->dsim_config->e_no_data_lane) {
+	case DSIM_DATA_LANE_1:
+		dsim->data_lane = DSIM_LANE_DATA0;
+		break;
+	case DSIM_DATA_LANE_2:
+		dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;
+		break;
+	case DSIM_DATA_LANE_3:
+		dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
+			DSIM_LANE_DATA2;
+		break;
+	case DSIM_DATA_LANE_4:
+		dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
+			DSIM_LANE_DATA2 | DSIM_LANE_DATA3;
+		break;
+	default:
+		debug("data lane is invalid.\n");
+		return -EINVAL;
+	};
+
+	exynos_mipi_dsi_sw_reset(dsim);
+	exynos_mipi_dsi_dp_dn_swap(dsim, 0);
+
+	return 0;
+}
+
+int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
+	unsigned int enable)
+{
+	/* enable only frame done interrupt */
+	exynos_mipi_dsi_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable);
+
+	return 0;
+}
+
+static void convert_to_fb_videomode(struct fb_videomode *mode1,
+				vidinfo_t *mode2)
+{
+	mode1->xres = mode2->vl_width;
+	mode1->yres = mode2->vl_height;
+	mode1->upper_margin = mode2->vl_vfpd;
+	mode1->lower_margin = mode2->vl_vbpd;
+	mode1->left_margin = mode2->vl_hfpd;
+	mode1->right_margin = mode2->vl_hbpd;
+	mode1->vsync_len = mode2->vl_vspw;
+	mode1->hsync_len = mode2->vl_hspw;
+}
+
+int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
+	struct mipi_dsim_config *dsim_config)
+{
+	struct exynos_platform_mipi_dsim *dsim_pd;
+	struct fb_videomode lcd_video;
+	vidinfo_t *vid;
+
+	dsim_pd = (struct exynos_platform_mipi_dsim *)dsim->pd;
+	vid = (vidinfo_t *)dsim_pd->lcd_panel_info;
+
+	convert_to_fb_videomode(&lcd_video, vid);
+
+	/* in case of VIDEO MODE (RGB INTERFACE), it sets polarities. */
+	if (dsim->dsim_config->e_interface == (u32) DSIM_VIDEO) {
+		if (dsim->dsim_config->auto_vertical_cnt == 0) {
+			exynos_mipi_dsi_set_main_disp_vporch(dsim,
+				vid->vl_cmd_allow_len,
+				lcd_video.upper_margin,
+				lcd_video.lower_margin);
+			exynos_mipi_dsi_set_main_disp_hporch(dsim,
+				lcd_video.left_margin,
+				lcd_video.right_margin);
+			exynos_mipi_dsi_set_main_disp_sync_area(dsim,
+				lcd_video.vsync_len,
+				lcd_video.hsync_len);
+		}
+	}
+
+	exynos_mipi_dsi_set_main_disp_resol(dsim, lcd_video.xres,
+			lcd_video.yres);
+
+	exynos_mipi_dsi_display_config(dsim, dsim->dsim_config);
+
+	debug("lcd panel ==> width = %d, height = %d\n",
+			lcd_video.xres, lcd_video.yres);
+
+	return 0;
+}
+
+int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim)
+{
+	unsigned int time_out = 100;
+
+	switch (dsim->state) {
+	case DSIM_STATE_INIT:
+		exynos_mipi_dsi_init_fifo_pointer(dsim, 0x1f);
+
+		/* dsi configuration */
+		exynos_mipi_dsi_init_config(dsim);
+		exynos_mipi_dsi_enable_lane(dsim, DSIM_LANE_CLOCK, 1);
+		exynos_mipi_dsi_enable_lane(dsim, dsim->data_lane, 1);
+
+		/* set clock configuration */
+		exynos_mipi_dsi_set_clock(dsim,
+					dsim->dsim_config->e_byte_clk, 1);
+
+		/* check clock and data lane state are stop state */
+		while (!(exynos_mipi_dsi_is_lane_state(dsim))) {
+			time_out--;
+			if (time_out == 0) {
+				debug("DSI Master is not stop state.\n");
+				debug("Check initialization process\n");
+
+				return -EINVAL;
+			}
+		}
+
+		dsim->state = DSIM_STATE_STOP;
+
+		/* BTA sequence counters */
+		exynos_mipi_dsi_set_stop_state_counter(dsim,
+			dsim->dsim_config->stop_holding_cnt);
+		exynos_mipi_dsi_set_bta_timeout(dsim,
+			dsim->dsim_config->bta_timeout);
+		exynos_mipi_dsi_set_lpdr_timeout(dsim,
+			dsim->dsim_config->rx_timeout);
+
+		return 0;
+	default:
+		debug("DSI Master is already init.\n");
+		return 0;
+	}
+
+	return 0;
+}
+
+int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim)
+{
+	if (dsim->state == DSIM_STATE_STOP) {
+		if (dsim->e_clk_src != DSIM_EXT_CLK_BYPASS) {
+			dsim->state = DSIM_STATE_HSCLKEN;
+
+			 /* set LCDC and CPU transfer mode to HS. */
+			exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
+			exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
+
+			exynos_mipi_dsi_enable_hs_clock(dsim, 1);
+
+			return 0;
+		} else
+			debug("clock source is external bypass.\n");
+	} else
+		debug("DSIM is not stop state.\n");
+
+	return 0;
+}
+
+int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,
+		unsigned int mode)
+{
+	if (mode) {
+		if (dsim->state != DSIM_STATE_HSCLKEN) {
+			debug("HS Clock lane is not enabled.\n");
+			return -EINVAL;
+		}
+
+		exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
+	} else {
+		if (dsim->state == DSIM_STATE_INIT || dsim->state ==
+			DSIM_STATE_ULPS) {
+			debug("DSI Master is not STOP or HSDT state.\n");
+			return -EINVAL;
+		}
+
+		exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
+	}
+
+	return 0;
+}
+
+int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim)
+{
+	return _exynos_mipi_dsi_get_frame_done_status(dsim);
+}
+
+int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
+{
+	_exynos_mipi_dsi_clear_frame_done(dsim);
+
+	return 0;
+}
diff --git a/drivers/video/exynos_mipi_dsi_common.h b/drivers/video/exynos_mipi_dsi_common.h
new file mode 100644
index 0000000000..4d80679a5d
--- /dev/null
+++ b/drivers/video/exynos_mipi_dsi_common.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: InKi Dae <inki.dae@samsung.com>
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/fb.h>
+
+#ifndef _EXYNOS_MIPI_DSI_COMMON_H
+#define _EXYNOS_MIPI_DSI_COMMON_H
+
+int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
+	unsigned int data0, unsigned int data1);
+int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim, unsigned int enable);
+unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,
+	unsigned int pre_divider, unsigned int main_divider,
+	unsigned int scaler);
+int exynos_mipi_dsi_set_clock(struct mipi_dsim_device *dsim,
+	unsigned int byte_clk_sel, unsigned int enable);
+int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim);
+int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
+			struct mipi_dsim_config *dsim_info);
+int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim);
+int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim);
+int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,
+		unsigned int mode);
+int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
+	unsigned int enable);
+int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim);
+int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim);
+
+#endif /* _EXYNOS_MIPI_DSI_COMMON_H */
diff --git a/drivers/video/exynos_mipi_dsi_lowlevel.c b/drivers/video/exynos_mipi_dsi_lowlevel.c
new file mode 100644
index 0000000000..d61b773616
--- /dev/null
+++ b/drivers/video/exynos_mipi_dsi_lowlevel.c
@@ -0,0 +1,652 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: InKi Dae <inki.dae@samsung.com>
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/dsim.h>
+#include <asm/arch/mipi_dsim.h>
+#include <asm/arch/power.h>
+#include <asm/arch/cpu.h>
+
+#include "exynos_mipi_dsi_lowlevel.h"
+#include "exynos_mipi_dsi_common.h"
+
+void exynos_mipi_dsi_func_reset(struct mipi_dsim_device *dsim)
+{
+	unsigned int reg;
+
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	reg = readl(&mipi_dsim->swrst);
+
+	reg |= DSIM_FUNCRST;
+
+	writel(reg, &mipi_dsim->swrst);
+}
+
+void exynos_mipi_dsi_sw_reset(struct mipi_dsim_device *dsim)
+{
+	unsigned int reg = 0;
+
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	reg = readl(&mipi_dsim->swrst);
+
+	reg |= DSIM_SWRST;
+	reg |= DSIM_FUNCRST;
+
+	writel(reg, &mipi_dsim->swrst);
+}
+
+void exynos_mipi_dsi_sw_release(struct mipi_dsim_device *dsim)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = readl(&mipi_dsim->intsrc);
+
+	reg |= INTSRC_SWRST_RELEASE;
+
+	writel(reg, &mipi_dsim->intsrc);
+}
+
+void exynos_mipi_dsi_set_interrupt_mask(struct mipi_dsim_device *dsim,
+		unsigned int mode, unsigned int mask)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = readl(&mipi_dsim->intmsk);
+
+	if (mask)
+		reg |= mode;
+	else
+		reg &= ~mode;
+
+	writel(reg, &mipi_dsim->intmsk);
+}
+
+void exynos_mipi_dsi_init_fifo_pointer(struct mipi_dsim_device *dsim,
+		unsigned int cfg)
+{
+	unsigned int reg;
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	reg = readl(&mipi_dsim->fifoctrl);
+
+	writel(reg & ~(cfg), &mipi_dsim->fifoctrl);
+	udelay(10 * 1000);
+	reg |= cfg;
+
+	writel(reg, &mipi_dsim->fifoctrl);
+}
+
+/*
+ * this function set PLL P, M and S value in D-PHY
+ */
+void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim,
+		unsigned int value)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	writel(DSIM_AFC_CTL(value), &mipi_dsim->phyacchr);
+}
+
+void exynos_mipi_dsi_set_main_disp_resol(struct mipi_dsim_device *dsim,
+	unsigned int width_resol, unsigned int height_resol)
+{
+	unsigned int reg;
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	/* standby should be set after configuration so set to not ready*/
+	reg = (readl(&mipi_dsim->mdresol)) & ~(DSIM_MAIN_STAND_BY);
+	writel(reg, &mipi_dsim->mdresol);
+
+	/* reset resolution */
+	reg &= ~(DSIM_MAIN_VRESOL(0x7ff) | DSIM_MAIN_HRESOL(0x7ff));
+	reg |= DSIM_MAIN_VRESOL(height_resol) | DSIM_MAIN_HRESOL(width_resol);
+
+	reg |= DSIM_MAIN_STAND_BY;
+	writel(reg, &mipi_dsim->mdresol);
+}
+
+void exynos_mipi_dsi_set_main_disp_vporch(struct mipi_dsim_device *dsim,
+	unsigned int cmd_allow, unsigned int vfront, unsigned int vback)
+{
+	unsigned int reg;
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	reg = (readl(&mipi_dsim->mvporch)) &
+		~((DSIM_CMD_ALLOW_MASK) | (DSIM_STABLE_VFP_MASK) |
+		(DSIM_MAIN_VBP_MASK));
+
+	reg |= ((cmd_allow & 0xf) << DSIM_CMD_ALLOW_SHIFT) |
+		((vfront & 0x7ff) << DSIM_STABLE_VFP_SHIFT) |
+		((vback & 0x7ff) << DSIM_MAIN_VBP_SHIFT);
+
+	writel(reg, &mipi_dsim->mvporch);
+}
+
+void exynos_mipi_dsi_set_main_disp_hporch(struct mipi_dsim_device *dsim,
+	unsigned int front, unsigned int back)
+{
+	unsigned int reg;
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	reg = (readl(&mipi_dsim->mhporch)) &
+		~((DSIM_MAIN_HFP_MASK) | (DSIM_MAIN_HBP_MASK));
+
+	reg |= (front << DSIM_MAIN_HFP_SHIFT) | (back << DSIM_MAIN_HBP_SHIFT);
+
+	writel(reg, &mipi_dsim->mhporch);
+}
+
+void exynos_mipi_dsi_set_main_disp_sync_area(struct mipi_dsim_device *dsim,
+	unsigned int vert, unsigned int hori)
+{
+	unsigned int reg;
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	reg = (readl(&mipi_dsim->msync)) &
+		~((DSIM_MAIN_VSA_MASK) | (DSIM_MAIN_HSA_MASK));
+
+	reg |= ((vert & 0x3ff) << DSIM_MAIN_VSA_SHIFT) |
+		(hori << DSIM_MAIN_HSA_SHIFT);
+
+	writel(reg, &mipi_dsim->msync);
+}
+
+void exynos_mipi_dsi_set_sub_disp_resol(struct mipi_dsim_device *dsim,
+	unsigned int vert, unsigned int hori)
+{
+	unsigned int reg;
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	reg = (readl(&mipi_dsim->sdresol)) &
+		~(DSIM_SUB_STANDY_MASK);
+
+	writel(reg, &mipi_dsim->sdresol);
+
+	reg &= ~(DSIM_SUB_VRESOL_MASK) | ~(DSIM_SUB_HRESOL_MASK);
+	reg |= ((vert & 0x7ff) << DSIM_SUB_VRESOL_SHIFT) |
+		((hori & 0x7ff) << DSIM_SUB_HRESOL_SHIFT);
+	writel(reg, &mipi_dsim->sdresol);
+
+	/* DSIM STANDBY */
+	reg |= (1 << DSIM_SUB_STANDY_SHIFT);
+	writel(reg, &mipi_dsim->sdresol);
+}
+
+void exynos_mipi_dsi_init_config(struct mipi_dsim_device *dsim)
+{
+	struct mipi_dsim_config *dsim_config = dsim->dsim_config;
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int cfg = (readl(&mipi_dsim->config)) &
+		~((1 << DSIM_EOT_PACKET_SHIFT) |
+		(0x1f << DSIM_HSA_MODE_SHIFT) |
+		(0x3 << DSIM_NUM_OF_DATALANE_SHIFT));
+
+	cfg |=	(dsim_config->auto_flush << DSIM_AUTO_FLUSH_SHIFT) |
+		(dsim_config->eot_disable << DSIM_EOT_PACKET_SHIFT) |
+		(dsim_config->auto_vertical_cnt << DSIM_AUTO_MODE_SHIFT) |
+		(dsim_config->hse << DSIM_HSE_MODE_SHIFT) |
+		(dsim_config->hfp << DSIM_HFP_MODE_SHIFT) |
+		(dsim_config->hbp << DSIM_HBP_MODE_SHIFT) |
+		(dsim_config->hsa << DSIM_HSA_MODE_SHIFT) |
+		(dsim_config->e_no_data_lane << DSIM_NUM_OF_DATALANE_SHIFT);
+
+	writel(cfg, &mipi_dsim->config);
+}
+
+void exynos_mipi_dsi_display_config(struct mipi_dsim_device *dsim,
+				struct mipi_dsim_config *dsim_config)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	u32 reg = (readl(&mipi_dsim->config)) &
+		~((0x3 << DSIM_BURST_MODE_SHIFT) | (1 << DSIM_VIDEO_MODE_SHIFT)
+		| (0x3 << DSIM_MAINVC_SHIFT) | (0x7 << DSIM_MAINPIX_SHIFT)
+		| (0x3 << DSIM_SUBVC_SHIFT) | (0x7 << DSIM_SUBPIX_SHIFT));
+
+	if (dsim_config->e_interface == DSIM_VIDEO)
+		reg |= (1 << DSIM_VIDEO_MODE_SHIFT);
+	else if (dsim_config->e_interface == DSIM_COMMAND)
+		reg &= ~(1 << DSIM_VIDEO_MODE_SHIFT);
+	else {
+		printf("unknown lcd type.\n");
+		return;
+	}
+
+	/* main lcd */
+	reg |= ((u8) (dsim_config->e_burst_mode) & 0x3) << DSIM_BURST_MODE_SHIFT
+	| ((u8) (dsim_config->e_virtual_ch) & 0x3) << DSIM_MAINVC_SHIFT
+	| ((u8) (dsim_config->e_pixel_format) & 0x7) << DSIM_MAINPIX_SHIFT;
+
+	writel(reg, &mipi_dsim->config);
+}
+
+void exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim,
+			unsigned int lane, unsigned int enable)
+{
+	unsigned int reg;
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	reg = readl(&mipi_dsim->config);
+
+	if (enable)
+		reg |= DSIM_LANE_ENx(lane);
+	else
+		reg &= ~DSIM_LANE_ENx(lane);
+
+	writel(reg, &mipi_dsim->config);
+}
+
+void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim,
+	unsigned int count)
+{
+	unsigned int cfg;
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	/* get the data lane number. */
+	cfg = DSIM_NUM_OF_DATA_LANE(count);
+
+	writel(cfg, &mipi_dsim->config);
+}
+
+void exynos_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim,
+			unsigned int enable, unsigned int afc_code)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = readl(&mipi_dsim->phyacchr);
+
+	reg = 0;
+
+	if (enable) {
+		reg |= DSIM_AFC_EN;
+		reg &= ~(0x7 << DSIM_AFC_CTL_SHIFT);
+		reg |= DSIM_AFC_CTL(afc_code);
+	} else
+		reg &= ~DSIM_AFC_EN;
+
+	writel(reg, &mipi_dsim->phyacchr);
+}
+
+void exynos_mipi_dsi_enable_pll_bypass(struct mipi_dsim_device *dsim,
+	unsigned int enable)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->clkctrl)) &
+		~(DSIM_PLL_BYPASS_EXTERNAL);
+
+	reg |= enable << DSIM_PLL_BYPASS_SHIFT;
+
+	writel(reg, &mipi_dsim->clkctrl);
+}
+
+void exynos_mipi_dsi_pll_freq_band(struct mipi_dsim_device *dsim,
+		unsigned int freq_band)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->pllctrl)) &
+		~(0x1f << DSIM_FREQ_BAND_SHIFT);
+
+	reg |= ((freq_band & 0x1f) << DSIM_FREQ_BAND_SHIFT);
+
+	writel(reg, &mipi_dsim->pllctrl);
+}
+
+void exynos_mipi_dsi_pll_freq(struct mipi_dsim_device *dsim,
+		unsigned int pre_divider, unsigned int main_divider,
+		unsigned int scaler)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->pllctrl)) &
+		~(0x7ffff << 1);
+
+	reg |= ((pre_divider & 0x3f) << DSIM_PREDIV_SHIFT) |
+		((main_divider & 0x1ff) << DSIM_MAIN_SHIFT) |
+		((scaler & 0x7) << DSIM_SCALER_SHIFT);
+
+	writel(reg, &mipi_dsim->pllctrl);
+}
+
+void exynos_mipi_dsi_pll_stable_time(struct mipi_dsim_device *dsim,
+	unsigned int lock_time)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	writel(lock_time, &mipi_dsim->plltmr);
+}
+
+void exynos_mipi_dsi_enable_pll(struct mipi_dsim_device *dsim,
+				unsigned int enable)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->pllctrl)) &
+		~(0x1 << DSIM_PLL_EN_SHIFT);
+
+	reg |= ((enable & 0x1) << DSIM_PLL_EN_SHIFT);
+
+	writel(reg, &mipi_dsim->pllctrl);
+}
+
+void exynos_mipi_dsi_set_byte_clock_src(struct mipi_dsim_device *dsim,
+		unsigned int src)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->clkctrl)) &
+		~(0x3 << DSIM_BYTE_CLK_SRC_SHIFT);
+
+	reg |= ((unsigned int) src) << DSIM_BYTE_CLK_SRC_SHIFT;
+
+	writel(reg, &mipi_dsim->clkctrl);
+}
+
+void exynos_mipi_dsi_enable_byte_clock(struct mipi_dsim_device *dsim,
+		unsigned int enable)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->clkctrl)) &
+		~(1 << DSIM_BYTE_CLKEN_SHIFT);
+
+	reg |= enable << DSIM_BYTE_CLKEN_SHIFT;
+
+	writel(reg, &mipi_dsim->clkctrl);
+}
+
+void exynos_mipi_dsi_set_esc_clk_prs(struct mipi_dsim_device *dsim,
+		unsigned int enable, unsigned int prs_val)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->clkctrl)) &
+		~((1 << DSIM_ESC_CLKEN_SHIFT) | (0xffff));
+
+	reg |= enable << DSIM_ESC_CLKEN_SHIFT;
+	if (enable)
+		reg |= prs_val;
+
+	writel(reg, &mipi_dsim->clkctrl);
+}
+
+void exynos_mipi_dsi_enable_esc_clk_on_lane(struct mipi_dsim_device *dsim,
+		unsigned int lane_sel, unsigned int enable)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = readl(&mipi_dsim->clkctrl);
+
+	if (enable)
+		reg |= DSIM_LANE_ESC_CLKEN(lane_sel);
+	else
+		reg &= ~DSIM_LANE_ESC_CLKEN(lane_sel);
+
+	writel(reg, &mipi_dsim->clkctrl);
+}
+
+void exynos_mipi_dsi_force_dphy_stop_state(struct mipi_dsim_device *dsim,
+	unsigned int enable)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->escmode)) &
+		~(0x1 << DSIM_FORCE_STOP_STATE_SHIFT);
+
+	reg |= ((enable & 0x1) << DSIM_FORCE_STOP_STATE_SHIFT);
+
+	writel(reg, &mipi_dsim->escmode);
+}
+
+unsigned int exynos_mipi_dsi_is_lane_state(struct mipi_dsim_device *dsim)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = readl(&mipi_dsim->status);
+
+	/**
+	 * check clock and data lane states.
+	 * if MIPI-DSI controller was enabled at bootloader then
+	 * TX_READY_HS_CLK is enabled otherwise STOP_STATE_CLK.
+	 * so it should be checked for two case.
+	 */
+	if ((reg & DSIM_STOP_STATE_DAT(0xf)) &&
+			((reg & DSIM_STOP_STATE_CLK) ||
+			 (reg & DSIM_TX_READY_HS_CLK)))
+		return 1;
+	else
+		return 0;
+}
+
+void exynos_mipi_dsi_set_stop_state_counter(struct mipi_dsim_device *dsim,
+		unsigned int cnt_val)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->escmode)) &
+		~(0x7ff << DSIM_STOP_STATE_CNT_SHIFT);
+
+	reg |= ((cnt_val & 0x7ff) << DSIM_STOP_STATE_CNT_SHIFT);
+
+	writel(reg, &mipi_dsim->escmode);
+}
+
+void exynos_mipi_dsi_set_bta_timeout(struct mipi_dsim_device *dsim,
+		unsigned int timeout)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->timeout)) &
+		~(0xff << DSIM_BTA_TOUT_SHIFT);
+
+	reg |= (timeout << DSIM_BTA_TOUT_SHIFT);
+
+	writel(reg, &mipi_dsim->timeout);
+}
+
+void exynos_mipi_dsi_set_lpdr_timeout(struct mipi_dsim_device *dsim,
+		unsigned int timeout)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->timeout)) &
+		~(0xffff << DSIM_LPDR_TOUT_SHIFT);
+
+	reg |= (timeout << DSIM_LPDR_TOUT_SHIFT);
+
+	writel(reg, &mipi_dsim->timeout);
+}
+
+void exynos_mipi_dsi_set_cpu_transfer_mode(struct mipi_dsim_device *dsim,
+		unsigned int lp)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = readl(&mipi_dsim->escmode);
+
+	reg &= ~DSIM_CMD_LPDT_LP;
+
+	if (lp)
+		reg |= DSIM_CMD_LPDT_LP;
+
+	writel(reg, &mipi_dsim->escmode);
+}
+
+void exynos_mipi_dsi_set_lcdc_transfer_mode(struct mipi_dsim_device *dsim,
+		unsigned int lp)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = readl(&mipi_dsim->escmode);
+
+	reg &= ~DSIM_TX_LPDT_LP;
+
+	if (lp)
+		reg |= DSIM_TX_LPDT_LP;
+
+	writel(reg, &mipi_dsim->escmode);
+}
+
+void exynos_mipi_dsi_enable_hs_clock(struct mipi_dsim_device *dsim,
+		unsigned int enable)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->clkctrl)) &
+		~(1 << DSIM_TX_REQUEST_HSCLK_SHIFT);
+
+	reg |= enable << DSIM_TX_REQUEST_HSCLK_SHIFT;
+
+	writel(reg, &mipi_dsim->clkctrl);
+}
+
+void exynos_mipi_dsi_dp_dn_swap(struct mipi_dsim_device *dsim,
+		unsigned int swap_en)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = readl(&mipi_dsim->phyacchr1);
+
+	reg &= ~(0x3 << DSIM_DPDN_SWAP_DATA_SHIFT);
+	reg |= (swap_en & 0x3) << DSIM_DPDN_SWAP_DATA_SHIFT;
+
+	writel(reg, &mipi_dsim->phyacchr1);
+}
+
+void exynos_mipi_dsi_hs_zero_ctrl(struct mipi_dsim_device *dsim,
+		unsigned int hs_zero)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->pllctrl)) &
+		~(0xf << DSIM_ZEROCTRL_SHIFT);
+
+	reg |= ((hs_zero & 0xf) << DSIM_ZEROCTRL_SHIFT);
+
+	writel(reg, &mipi_dsim->pllctrl);
+}
+
+void exynos_mipi_dsi_prep_ctrl(struct mipi_dsim_device *dsim, unsigned int prep)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (readl(&mipi_dsim->pllctrl)) &
+		~(0x7 << DSIM_PRECTRL_SHIFT);
+
+	reg |= ((prep & 0x7) << DSIM_PRECTRL_SHIFT);
+
+	writel(reg, &mipi_dsim->pllctrl);
+}
+
+void exynos_mipi_dsi_clear_interrupt(struct mipi_dsim_device *dsim)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = readl(&mipi_dsim->intsrc);
+
+	reg |= INTSRC_PLL_STABLE;
+
+	writel(reg, &mipi_dsim->intsrc);
+}
+
+void exynos_mipi_dsi_clear_all_interrupt(struct mipi_dsim_device *dsim)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	writel(0xffffffff, &mipi_dsim->intsrc);
+}
+
+unsigned int exynos_mipi_dsi_is_pll_stable(struct mipi_dsim_device *dsim)
+{
+	unsigned int reg;
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	reg = readl(&mipi_dsim->status);
+
+	return reg & DSIM_PLL_STABLE ? 1 : 0;
+}
+
+unsigned int exynos_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	return readl(&mipi_dsim->fifoctrl) & ~(0x1f);
+}
+
+void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim,
+	unsigned int di, unsigned int data0, unsigned int data1)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = (DSIM_PKTHDR_DAT1(data1) | DSIM_PKTHDR_DAT0(data0) |
+			DSIM_PKTHDR_DI(di));
+
+	writel(reg, &mipi_dsim->pkthdr);
+}
+
+unsigned int _exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device
+						*dsim)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = readl(&mipi_dsim->intsrc);
+
+	return (reg & INTSRC_FRAME_DONE) ? 1 : 0;
+}
+
+void _exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+	unsigned int reg = readl(&mipi_dsim->intsrc);
+
+	writel(reg | INTSRC_FRAME_DONE, &mipi_dsim->intsrc);
+}
+
+void exynos_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim,
+		unsigned int tx_data)
+{
+	struct exynos_mipi_dsim *mipi_dsim =
+		(struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
+
+	writel(tx_data, &mipi_dsim->payload);
+}
diff --git a/drivers/video/exynos_mipi_dsi_lowlevel.h b/drivers/video/exynos_mipi_dsi_lowlevel.h
new file mode 100644
index 0000000000..4b8c441cb5
--- /dev/null
+++ b/drivers/video/exynos_mipi_dsi_lowlevel.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: InKi Dae <inki.dae@samsung.com>
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _EXYNOS_MIPI_DSI_LOWLEVEL_H
+#define _EXYNOS_MIPI_DSI_LOWLEVEL_H
+
+void exynos_mipi_dsi_register(struct mipi_dsim_device *dsim);
+void exynos_mipi_dsi_func_reset(struct mipi_dsim_device *dsim);
+void exynos_mipi_dsi_sw_reset(struct mipi_dsim_device *dsim);
+void exynos_mipi_dsi_sw_release(struct mipi_dsim_device *dsim);
+void exynos_mipi_dsi_set_interrupt_mask(struct mipi_dsim_device *dsim,
+	unsigned int mode, unsigned int mask);
+void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim,
+					unsigned int count);
+void exynos_mipi_dsi_init_fifo_pointer(struct mipi_dsim_device *dsim,
+					unsigned int cfg);
+void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim,
+				unsigned int value);
+void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim,
+				unsigned int value);
+void exynos_mipi_dsi_set_main_disp_resol(struct mipi_dsim_device *dsim,
+		unsigned int width_resol, unsigned int height_resol);
+void exynos_mipi_dsi_set_main_disp_vporch(struct mipi_dsim_device *dsim,
+	unsigned int cmd_allow, unsigned int vfront, unsigned int vback);
+void exynos_mipi_dsi_set_main_disp_hporch(struct mipi_dsim_device *dsim,
+			unsigned int front, unsigned int back);
+void exynos_mipi_dsi_set_main_disp_sync_area(struct mipi_dsim_device *dsim,
+				unsigned int vert, unsigned int hori);
+void exynos_mipi_dsi_set_sub_disp_resol(struct mipi_dsim_device *dsim,
+				unsigned int vert, unsigned int hori);
+void exynos_mipi_dsi_init_config(struct mipi_dsim_device *dsim);
+void exynos_mipi_dsi_display_config(struct mipi_dsim_device *dsim,
+				struct mipi_dsim_config *dsim_config);
+void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim,
+				unsigned int count);
+void exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim,
+			unsigned int lane, unsigned int enable);
+void exynos_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim,
+			unsigned int enable, unsigned int afc_code);
+void exynos_mipi_dsi_enable_pll_bypass(struct mipi_dsim_device *dsim,
+				unsigned int enable);
+void exynos_mipi_dsi_pll_freq_band(struct mipi_dsim_device *dsim,
+				unsigned int freq_band);
+void exynos_mipi_dsi_pll_freq(struct mipi_dsim_device *dsim,
+			unsigned int pre_divider, unsigned int main_divider,
+			unsigned int scaler);
+void exynos_mipi_dsi_pll_stable_time(struct mipi_dsim_device *dsim,
+			unsigned int lock_time);
+void exynos_mipi_dsi_enable_pll(struct mipi_dsim_device *dsim,
+					unsigned int enable);
+void exynos_mipi_dsi_set_byte_clock_src(struct mipi_dsim_device *dsim,
+					unsigned int src);
+void exynos_mipi_dsi_enable_byte_clock(struct mipi_dsim_device *dsim,
+					unsigned int enable);
+void exynos_mipi_dsi_set_esc_clk_prs(struct mipi_dsim_device *dsim,
+				unsigned int enable, unsigned int prs_val);
+void exynos_mipi_dsi_enable_esc_clk_on_lane(struct mipi_dsim_device *dsim,
+				unsigned int lane_sel, unsigned int enable);
+void exynos_mipi_dsi_force_dphy_stop_state(struct mipi_dsim_device *dsim,
+				unsigned int enable);
+unsigned int exynos_mipi_dsi_is_lane_state(struct mipi_dsim_device *dsim);
+void exynos_mipi_dsi_set_stop_state_counter(struct mipi_dsim_device *dsim,
+				unsigned int cnt_val);
+void exynos_mipi_dsi_set_bta_timeout(struct mipi_dsim_device *dsim,
+				unsigned int timeout);
+void exynos_mipi_dsi_set_lpdr_timeout(struct mipi_dsim_device *dsim,
+				unsigned int timeout);
+void exynos_mipi_dsi_set_lcdc_transfer_mode(struct mipi_dsim_device *dsim,
+					unsigned int lp);
+void exynos_mipi_dsi_set_cpu_transfer_mode(struct mipi_dsim_device *dsim,
+					unsigned int lp);
+void exynos_mipi_dsi_enable_hs_clock(struct mipi_dsim_device *dsim,
+				unsigned int enable);
+void exynos_mipi_dsi_dp_dn_swap(struct mipi_dsim_device *dsim,
+				unsigned int swap_en);
+void exynos_mipi_dsi_hs_zero_ctrl(struct mipi_dsim_device *dsim,
+				unsigned int hs_zero);
+void exynos_mipi_dsi_prep_ctrl(struct mipi_dsim_device *dsim,
+				unsigned int prep);
+void exynos_mipi_dsi_clear_interrupt(struct mipi_dsim_device *dsim);
+void exynos_mipi_dsi_clear_all_interrupt(struct mipi_dsim_device *dsim);
+unsigned int exynos_mipi_dsi_is_pll_stable(struct mipi_dsim_device *dsim);
+unsigned int exynos_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim);
+unsigned int _exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device
+						*dsim);
+void _exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim);
+void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim,
+		unsigned int di, unsigned int data0, unsigned int data1);
+void exynos_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim,
+		unsigned int tx_data);
+
+#endif /* _EXYNOS_MIPI_DSI_LOWLEVEL_H */
diff --git a/drivers/video/s6e8ax0.c b/drivers/video/s6e8ax0.c
new file mode 100644
index 0000000000..1ec7fd6e5a
--- /dev/null
+++ b/drivers/video/s6e8ax0.c
@@ -0,0 +1,256 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/mipi_dsim.h>
+
+#include "exynos_mipi_dsi_lowlevel.h"
+#include "exynos_mipi_dsi_common.h"
+
+static void s6e8ax0_panel_cond(struct mipi_dsim_device *dsim_dev)
+{
+	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
+	const unsigned char data_to_send[] = {
+		0xf8, 0x3d, 0x35, 0x00, 0x00, 0x00, 0x8d, 0x00, 0x4c,
+		0x6e, 0x10, 0x27, 0x7d, 0x3f, 0x10, 0x00, 0x00, 0x20,
+		0x04, 0x08, 0x6e, 0x00, 0x00, 0x00, 0x02, 0x08, 0x08,
+		0x23, 0x23, 0xc0, 0xc8, 0x08, 0x48, 0xc1, 0x00, 0xc3,
+		0xff, 0xff, 0xc8
+	};
+
+	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
+			(unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
+}
+
+static void s6e8ax0_display_cond(struct mipi_dsim_device *dsim_dev)
+{
+	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
+	const unsigned char data_to_send[] = {
+		0xf2, 0x80, 0x03, 0x0d
+	};
+
+	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
+			(unsigned int)data_to_send,
+			ARRAY_SIZE(data_to_send));
+}
+
+static void s6e8ax0_gamma_cond(struct mipi_dsim_device *dsim_dev)
+{
+	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
+	/* 7500K 2.2 Set (M3, 300cd) */
+	const unsigned char data_to_send[] = {
+		0xfa, 0x01, 0x0f, 0x00, 0x0f, 0xda, 0xc0, 0xe4, 0xc8,
+		0xc8, 0xc6, 0xd3, 0xd6, 0xd0, 0xab, 0xb2, 0xa6, 0xbf,
+		0xc2, 0xb9, 0x00, 0x93, 0x00, 0x86, 0x00, 0xd1
+	};
+
+	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
+			(unsigned int)data_to_send,
+			ARRAY_SIZE(data_to_send));
+}
+
+static void s6e8ax0_gamma_update(struct mipi_dsim_device *dsim_dev)
+{
+	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
+
+	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0xf7, 0x3);
+}
+
+static void s6e8ax0_etc_source_control(struct mipi_dsim_device *dsim_dev)
+{
+	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
+	const unsigned char data_to_send[] = {
+		0xf6, 0x00, 0x02, 0x00
+	};
+
+	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
+			(unsigned int)data_to_send,
+			ARRAY_SIZE(data_to_send));
+}
+
+static void s6e8ax0_etc_pentile_control(struct mipi_dsim_device *dsim_dev)
+{
+	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
+	const unsigned char data_to_send[] = {
+		0xb6, 0x0c, 0x02, 0x03, 0x32, 0xff, 0x44, 0x44, 0xc0,
+		0x00
+	};
+
+	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
+			(unsigned int)data_to_send,
+			ARRAY_SIZE(data_to_send));
+}
+
+static void s6e8ax0_etc_mipi_control1(struct mipi_dsim_device *dsim_dev)
+{
+	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
+	const unsigned char data_to_send[] = {
+		0xe1, 0x10, 0x1c, 0x17, 0x08, 0x1d
+	};
+
+	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
+			(unsigned int)data_to_send,
+			ARRAY_SIZE(data_to_send));
+}
+
+static void s6e8ax0_etc_mipi_control2(struct mipi_dsim_device *dsim_dev)
+{
+	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
+	const unsigned char data_to_send[] = {
+		0xe2, 0xed, 0x07, 0xc3, 0x13, 0x0d, 0x03
+	};
+
+	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
+			(unsigned int)data_to_send,
+			ARRAY_SIZE(data_to_send));
+}
+
+static void s6e8ax0_etc_power_control(struct mipi_dsim_device *dsim_dev)
+{
+	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
+	const unsigned char data_to_send[] = {
+		0xf4, 0xcf, 0x0a, 0x12, 0x10, 0x19, 0x33, 0x02
+	};
+
+	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
+		(unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
+}
+
+static void s6e8ax0_etc_mipi_control3(struct mipi_dsim_device *dsim_dev)
+{
+	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
+
+	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0xe3, 0x40);
+}
+
+static void s6e8ax0_etc_mipi_control4(struct mipi_dsim_device *dsim_dev)
+{
+	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
+	const unsigned char data_to_send[] = {
+		0xe4, 0x00, 0x00, 0x14, 0x80, 0x00, 0x00, 0x00
+	};
+
+	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
+		(unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
+}
+
+static void s6e8ax0_elvss_set(struct mipi_dsim_device *dsim_dev)
+{
+	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
+	const unsigned char data_to_send[] = {
+		0xb1, 0x04, 0x00
+	};
+
+	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
+			(unsigned int)data_to_send,
+			ARRAY_SIZE(data_to_send));
+}
+
+static void s6e8ax0_display_on(struct mipi_dsim_device *dsim_dev)
+{
+	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
+
+	ops->cmd_write(dsim_dev,
+		MIPI_DSI_DCS_SHORT_WRITE, 0x29, 0x00);
+}
+
+static void s6e8ax0_sleep_out(struct mipi_dsim_device *dsim_dev)
+{
+	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
+
+	ops->cmd_write(dsim_dev,
+		MIPI_DSI_DCS_SHORT_WRITE, 0x11, 0x00);
+}
+
+static void s6e8ax0_apply_level1_key(struct mipi_dsim_device *dsim_dev)
+{
+	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
+	const unsigned char data_to_send[] = {
+		0xf0, 0x5a, 0x5a
+	};
+
+	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
+		(unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
+}
+
+static void s6e8ax0_apply_mtp_key(struct mipi_dsim_device *dsim_dev)
+{
+	struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
+	const unsigned char data_to_send[] = {
+		0xf1, 0x5a, 0x5a
+	};
+
+	ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
+		(unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
+}
+
+static void s6e8ax0_panel_init(struct mipi_dsim_device *dsim_dev)
+{
+	/*
+	 * in case of setting gamma and panel condition at first,
+	 * it shuold be setting like below.
+	 * set_gamma() -> set_panel_condition()
+	 */
+
+	s6e8ax0_apply_level1_key(dsim_dev);
+	s6e8ax0_apply_mtp_key(dsim_dev);
+
+	s6e8ax0_sleep_out(dsim_dev);
+	mdelay(5);
+	s6e8ax0_panel_cond(dsim_dev);
+	s6e8ax0_display_cond(dsim_dev);
+	s6e8ax0_gamma_cond(dsim_dev);
+	s6e8ax0_gamma_update(dsim_dev);
+
+	s6e8ax0_etc_source_control(dsim_dev);
+	s6e8ax0_elvss_set(dsim_dev);
+	s6e8ax0_etc_pentile_control(dsim_dev);
+	s6e8ax0_etc_mipi_control1(dsim_dev);
+	s6e8ax0_etc_mipi_control2(dsim_dev);
+	s6e8ax0_etc_power_control(dsim_dev);
+	s6e8ax0_etc_mipi_control3(dsim_dev);
+	s6e8ax0_etc_mipi_control4(dsim_dev);
+}
+
+static int s6e8ax0_panel_set(struct mipi_dsim_device *dsim_dev)
+{
+	s6e8ax0_panel_init(dsim_dev);
+
+	return 0;
+}
+
+static void s6e8ax0_display_enable(struct mipi_dsim_device *dsim_dev)
+{
+	s6e8ax0_display_on(dsim_dev);
+}
+
+static struct mipi_dsim_lcd_driver s6e8ax0_dsim_ddi_driver = {
+	.name = "s6e8ax0",
+	.id = -1,
+
+	.mipi_panel_init = s6e8ax0_panel_set,
+	.mipi_display_on = s6e8ax0_display_enable,
+};
+
+void s6e8ax0_init(void)
+{
+	exynos_mipi_dsi_register_lcd_driver(&s6e8ax0_dsim_ddi_driver);
+}
diff --git a/examples/api/.gitignore b/examples/api/.gitignore
deleted file mode 100644
index d7b18dcef5..0000000000
--- a/examples/api/.gitignore
+++ /dev/null
@@ -1,2 +0,0 @@
-demo
-demo.bin
diff --git a/examples/standalone/.gitignore b/examples/standalone/.gitignore
deleted file mode 100644
index 4d9ce66402..0000000000
--- a/examples/standalone/.gitignore
+++ /dev/null
@@ -1,13 +0,0 @@
-/82559_eeprom
-/atmel_df_pow2
-/eepro100_eeprom
-/hello_world
-/interrupt
-/mem_to_mem_idma2intr
-/sched
-/smc91111_eeprom
-/smc911x_eeprom
-/test_burst
-/timer
-*.bin
-*.srec
diff --git a/fs/cramfs/uncompress.c b/fs/cramfs/uncompress.c
index 228fe68c11..f431cc46c1 100644
--- a/fs/cramfs/uncompress.c
+++ b/fs/cramfs/uncompress.c
@@ -27,9 +27,6 @@
 
 static z_stream stream;
 
-void *zalloc(void *, unsigned, unsigned);
-void zfree(void *, void *, unsigned);
-
 /* Returns length of decompressed data. */
 int cramfs_uncompress_block (void *dst, void *src, int srclen)
 {
@@ -59,8 +56,8 @@ int cramfs_uncompress_init (void)
 {
 	int err;
 
-	stream.zalloc = zalloc;
-	stream.zfree = zfree;
+	stream.zalloc = gzalloc;
+	stream.zfree = gzfree;
 	stream.next_in = 0;
 	stream.avail_in = 0;
 
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 1f95eb4caf..a3085b51d9 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -31,6 +31,8 @@
 #include <fat.h>
 #include <asm/byteorder.h>
 #include <part.h>
+#include <malloc.h>
+#include <linux/compiler.h>
 
 /*
  * Convert a string to lowercase.
@@ -62,7 +64,7 @@ static int disk_read(__u32 block, __u32 nr_blocks, void *buf)
 
 int fat_register_device (block_dev_desc_t * dev_desc, int part_no)
 {
-	unsigned char buffer[dev_desc->blksz];
+	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
 
 	/* First close any currently found FAT filesystem */
 	cur_dev = NULL;
@@ -293,7 +295,7 @@ get_cluster (fsdata *mydata, __u32 clustnum, __u8 *buffer,
 		return -1;
 	}
 	if (size % mydata->sect_size) {
-		__u8 tmpbuf[mydata->sect_size];
+		ALLOC_CACHE_ALIGN_BUFFER(__u8, tmpbuf, mydata->sect_size);
 
 		idx = size / mydata->sect_size;
 		ret = disk_read(startsect + idx, 1, tmpbuf);
@@ -428,8 +430,8 @@ static int slot2str (dir_slot *slotptr, char *l_name, int *idx)
  * into 'retdent'
  * Return 0 on success, -1 otherwise.
  */
-__attribute__ ((__aligned__ (__alignof__ (dir_entry))))
-__u8 get_vfatname_block[MAX_CLUSTSIZE];
+__u8 get_vfatname_block[MAX_CLUSTSIZE]
+	__aligned(ARCH_DMA_MINALIGN);
 
 static int
 get_vfatname (fsdata *mydata, int curclust, __u8 *cluster,
@@ -533,8 +535,8 @@ static __u8 mkcksum (const char *str)
  * Get the directory entry associated with 'filename' from the directory
  * starting at 'startsect'
  */
-__attribute__ ((__aligned__ (__alignof__ (dir_entry))))
-__u8 get_dentfromdir_block[MAX_CLUSTSIZE];
+__u8 get_dentfromdir_block[MAX_CLUSTSIZE]
+	__aligned(ARCH_DMA_MINALIGN);
 
 static dir_entry *get_dentfromdir (fsdata *mydata, int startsect,
 				   char *filename, dir_entry *retdent,
@@ -709,7 +711,7 @@ read_bootsectandvi (boot_sector *bs, volume_info *volinfo, int *fatsize)
 		return -1;
 	}
 
-	block = malloc(cur_dev->blksz);
+	block = memalign(ARCH_DMA_MINALIGN, cur_dev->blksz);
 	if (block == NULL) {
 		debug("Error: allocating block\n");
 		return -1;
@@ -765,8 +767,8 @@ exit:
 	return ret;
 }
 
-__attribute__ ((__aligned__ (__alignof__ (dir_entry))))
-__u8 do_fat_read_block[MAX_CLUSTSIZE];
+__u8 do_fat_read_block[MAX_CLUSTSIZE]
+	__aligned(ARCH_DMA_MINALIGN);
 
 long
 do_fat_read (const char *filename, void *buffer, unsigned long maxsize,
@@ -828,7 +830,7 @@ do_fat_read (const char *filename, void *buffer, unsigned long maxsize,
 	}
 
 	mydata->fatbufnum = -1;
-	mydata->fatbuf = malloc(FATBUFSIZE);
+	mydata->fatbuf = memalign(ARCH_DMA_MINALIGN, FATBUFSIZE);
 	if (mydata->fatbuf == NULL) {
 		debug("Error: allocating memory\n");
 		return -1;
diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c
index a0b02e4dda..c856983ef4 100644
--- a/fs/jffs2/jffs2_1pass.c
+++ b/fs/jffs2/jffs2_1pass.c
@@ -119,7 +119,7 @@
 #include <watchdog.h>
 #include <jffs2/jffs2.h>
 #include <jffs2/jffs2_1pass.h>
-#include <linux/mtd/compat.h>
+#include <linux/compat.h>
 #include <asm/errno.h>
 
 #include "jffs2_private.h"
diff --git a/fs/ubifs/io.c b/fs/ubifs/io.c
index aae5c65eae..1c3d275976 100644
--- a/fs/ubifs/io.c
+++ b/fs/ubifs/io.c
@@ -251,7 +251,10 @@ void ubifs_prepare_node(struct ubifs_info *c, void *node, int len, int pad)
 
 	if (pad) {
 		len = ALIGN(len, 8);
-		pad = ALIGN(len, c->min_io_size) - len;
+		if (is_power_of_2(c->min_io_size))
+			pad = ALIGN(len, c->min_io_size) - len;
+		else
+			pad = roundup(len, c->min_io_size) - len;
 		ubifs_pad(c, node + len, pad);
 	}
 }
diff --git a/fs/ubifs/lpt.c b/fs/ubifs/lpt.c
index 1a50d4cc27..542f4e0560 100644
--- a/fs/ubifs/lpt.c
+++ b/fs/ubifs/lpt.c
@@ -123,7 +123,10 @@ static void do_calc_lpt_geom(struct ubifs_info *c)
 		sz -= c->leb_size;
 		tot_wastage += per_leb_wastage;
 	}
-	tot_wastage += ALIGN(sz, c->min_io_size) - sz;
+	if (is_power_of_2(c->min_io_size))
+		tot_wastage += ALIGN(sz, c->min_io_size) - sz;
+	else
+		tot_wastage += roundup(sz, c->min_io_size) - sz;
 	c->lpt_sz += tot_wastage;
 }
 
diff --git a/fs/ubifs/master.c b/fs/ubifs/master.c
index 3f2926e870..e5f3bf1228 100644
--- a/fs/ubifs/master.c
+++ b/fs/ubifs/master.c
@@ -108,12 +108,22 @@ static int validate_master(const struct ubifs_info *c)
 		goto out;
 	}
 
-	if (c->lhead_lnum < UBIFS_LOG_LNUM ||
-	    c->lhead_lnum >= UBIFS_LOG_LNUM + c->log_lebs ||
-	    c->lhead_offs < 0 || c->lhead_offs >= c->leb_size ||
-	    c->lhead_offs & (c->min_io_size - 1)) {
-		err = 4;
-		goto out;
+	if (c->min_io_shift == 0) {
+		if (c->lhead_lnum < UBIFS_LOG_LNUM ||
+				c->lhead_lnum >= UBIFS_LOG_LNUM + c->log_lebs ||
+				c->lhead_offs < 0 || c->lhead_offs >= c->leb_size ||
+				c->lhead_offs % c->min_io_size) {
+			err = 4;
+			goto out;
+		}
+	} else {
+		if (c->lhead_lnum < UBIFS_LOG_LNUM ||
+				c->lhead_lnum >= UBIFS_LOG_LNUM + c->log_lebs ||
+				c->lhead_offs < 0 || c->lhead_offs >= c->leb_size ||
+				c->lhead_offs & (c->min_io_size - 1)) {
+			err = 4;
+			goto out;
+		}
 	}
 
 	if (c->zroot.lnum >= c->leb_cnt || c->zroot.lnum < c->main_first ||
diff --git a/fs/ubifs/recovery.c b/fs/ubifs/recovery.c
index 744465005c..83d8746f30 100644
--- a/fs/ubifs/recovery.c
+++ b/fs/ubifs/recovery.c
@@ -365,7 +365,11 @@ static int is_last_write(const struct ubifs_info *c, void *buf, int offs)
 	 * Round up to the next c->min_io_size boundary i.e. 'offs' is in the
 	 * last wbuf written. After that should be empty space.
 	 */
-	empty_offs = ALIGN(offs + 1, c->min_io_size);
+	 if (c->min_io_shift == 0)
+	 	empty_offs = roundup(offs + 1, c->min_io_size);
+	 else
+		empty_offs = ALIGN(offs + 1, c->min_io_size);
+
 	check_len = c->leb_size - empty_offs;
 	p = buf + empty_offs - offs;
 
@@ -401,7 +405,10 @@ static void clean_buf(const struct ubifs_info *c, void **buf, int lnum,
 	}
 
 	ubifs_assert(!(*offs & 7));
-	empty_offs = ALIGN(*offs, c->min_io_size);
+	if (c->min_io_shift == 0)
+		empty_offs = roundup(*offs, c->min_io_size);
+	else
+		empty_offs = ALIGN(*offs, c->min_io_size);
 	pad_len = empty_offs - *offs;
 	ubifs_pad(c, *buf, pad_len);
 	*offs += pad_len;
@@ -429,7 +436,10 @@ static int no_more_nodes(const struct ubifs_info *c, void *buf, int len,
 	int skip, dlen = le32_to_cpu(ch->len);
 
 	/* Check for empty space after the corrupt node's common header */
-	skip = ALIGN(offs + UBIFS_CH_SZ, c->min_io_size) - offs;
+	if (c->min_io_shift == 0)
+		skip = roundup(offs + UBIFS_CH_SZ, c->min_io_size) - offs;
+	else
+		skip = ALIGN(offs + UBIFS_CH_SZ, c->min_io_size) - offs;
 	if (is_empty(buf + skip, len - skip))
 		return 1;
 	/*
@@ -441,7 +451,10 @@ static int no_more_nodes(const struct ubifs_info *c, void *buf, int len,
 		return 0;
 	}
 	/* Now we know the corrupt node's length we can skip over it */
-	skip = ALIGN(offs + dlen, c->min_io_size) - offs;
+	if (c->min_io_shift == 0)
+		skip = roundup(offs + dlen, c->min_io_size) - offs;
+	else
+		skip = ALIGN(offs + dlen, c->min_io_size) - offs;
 	/* After which there should be empty space */
 	if (is_empty(buf + skip, len - skip))
 		return 1;
@@ -648,9 +661,17 @@ struct ubifs_scan_leb *ubifs_recover_leb(struct ubifs_info *c, int lnum,
 		need_clean = 1;
 	}
 
-	if (offs % c->min_io_size) {
-		clean_buf(c, &buf, lnum, &offs, &len);
-		need_clean = 1;
+	if (c->min_io_shift == 0)
+	{
+		if (offs % c->min_io_size) {
+			clean_buf(c, &buf, lnum, &offs, &len);
+			need_clean = 1;
+		}
+	} else {
+		if (offs & (c->min_io_size - 1)) {
+			clean_buf(c, &buf, lnum, &offs, &len);
+			need_clean = 1;
+		}
 	}
 
 	ubifs_end_scan(c, sleb, lnum, offs);
@@ -947,7 +968,10 @@ static int clean_an_unclean_leb(const struct ubifs_info *c,
 	}
 
 	/* Pad to min_io_size */
-	len = ALIGN(ucleb->endpt, c->min_io_size);
+	if (c->min_io_shift == 0)
+		len = roundup(ucleb->endpt, c->min_io_size);
+	else
+		len = ALIGN(ucleb->endpt, c->min_io_size);
 	if (len > ucleb->endpt) {
 		int pad_len = len - ALIGN(ucleb->endpt, 8);
 
diff --git a/fs/ubifs/replay.c b/fs/ubifs/replay.c
index da33a14ab6..1a351f606c 100644
--- a/fs/ubifs/replay.c
+++ b/fs/ubifs/replay.c
@@ -625,7 +625,10 @@ static int replay_bud(struct ubifs_info *c, int lnum, int offs, int jhead,
 		BUG();
 
 	ubifs_assert(sleb->endpt - offs >= used);
-	ubifs_assert(sleb->endpt % c->min_io_size == 0);
+	if (c->min_io_shift == 0)
+		ubifs_assert(sleb->endpt % c->min_io_size == 0);
+	else
+		ubifs_assert((sleb->endpt & (c->min_io_size - 1)) == 0);
 
 	*dirty = sleb->endpt - offs - used;
 	*free = c->leb_size - sleb->endpt;
@@ -795,10 +798,17 @@ static int validate_ref(struct ubifs_info *c, const struct ubifs_ref_node *ref)
 	 * to the end of LEB and we write reference node for it during commit.
 	 * So this is why we require 'offs > c->leb_size'.
 	 */
-	if (jhead >= c->jhead_cnt || lnum >= c->leb_cnt ||
-	    lnum < c->main_first || offs > c->leb_size ||
-	    offs & (c->min_io_size - 1))
-		return -EINVAL;
+	if (c->min_io_shift == 0) {
+		if (jhead >= c->jhead_cnt || lnum >= c->leb_cnt ||
+				lnum < c->main_first || offs > c->leb_size ||
+				offs % c->min_io_size)
+			return -EINVAL;
+	} else {
+		if (jhead >= c->jhead_cnt || lnum >= c->leb_cnt ||
+				lnum < c->main_first || offs > c->leb_size ||
+				offs & (c->min_io_size - 1))
+			return -EINVAL;
+	}
 
 	/* Make sure we have not already looked at this bud */
 	bud = ubifs_search_bud(c, lnum);
diff --git a/fs/ubifs/sb.c b/fs/ubifs/sb.c
index 00c9cd31a0..ed61330c64 100644
--- a/fs/ubifs/sb.c
+++ b/fs/ubifs/sb.c
@@ -199,7 +199,10 @@ struct ubifs_sb_node *ubifs_read_sb_node(struct ubifs_info *c)
 	struct ubifs_sb_node *sup;
 	int err;
 
-	sup = kmalloc(ALIGN(UBIFS_SB_NODE_SZ, c->min_io_size), GFP_NOFS);
+	if (c->min_io_shift == 0)
+		sup = kmalloc(roundup(UBIFS_SB_NODE_SZ, c->min_io_size), GFP_NOFS);
+	else
+		sup = kmalloc(ALIGN(UBIFS_SB_NODE_SZ, c->min_io_size), GFP_NOFS);
 	if (!sup)
 		return ERR_PTR(-ENOMEM);
 
diff --git a/fs/ubifs/scan.c b/fs/ubifs/scan.c
index 0ed82479b4..373ae2f9c4 100644
--- a/fs/ubifs/scan.c
+++ b/fs/ubifs/scan.c
@@ -177,9 +177,14 @@ void ubifs_end_scan(const struct ubifs_info *c, struct ubifs_scan_leb *sleb,
 {
 	lnum = lnum;
 	dbg_scan("stop scanning LEB %d at offset %d", lnum, offs);
-	ubifs_assert(offs % c->min_io_size == 0);
 
-	sleb->endpt = ALIGN(offs, c->min_io_size);
+	if (c->min_io_shift == 0) {
+		ubifs_assert((offs % c->min_io_size) == 0);
+		sleb->endpt = roundup(offs, c->min_io_size);
+	} else {
+		ubifs_assert((offs & (c->min_io_size - 1)) == 0);
+		sleb->endpt = ALIGN(offs, c->min_io_size);
+	}
 }
 
 /**
@@ -317,8 +322,13 @@ struct ubifs_scan_leb *ubifs_scan(const struct ubifs_info *c, int lnum,
 		len -= node_len;
 	}
 
-	if (offs % c->min_io_size)
-		goto corrupted;
+	if (c->min_io_shift == 0) {
+		if (offs % c->min_io_size)
+			goto corrupted;
+	} else {
+		if (offs & (c->min_io_size - 1))
+			goto corrupted;
+	}
 
 	ubifs_end_scan(c, sleb, lnum, offs);
 
diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c
index 26b48f029e..35e9bed4e1 100644
--- a/fs/ubifs/super.c
+++ b/fs/ubifs/super.c
@@ -314,7 +314,12 @@ static int init_constants_early(struct ubifs_info *c)
 	c->leb_size = c->vi.usable_leb_size;
 	c->half_leb_size = c->leb_size / 2;
 	c->min_io_size = c->di.min_io_size;
-	c->min_io_shift = fls(c->min_io_size) - 1;
+	if (is_power_of_2(c->min_io_size))
+		c->min_io_shift = fls(c->min_io_size) - 1;
+	else
+		c->min_io_shift = 0;
+
+	ubifs_msg("UBI min_io_shift = %d \n", c->min_io_shift);
 
 	if (c->leb_size < UBIFS_MIN_LEB_SZ) {
 		ubifs_err("too small LEBs (%d bytes), min. is %d bytes",
@@ -328,11 +333,6 @@ static int init_constants_early(struct ubifs_info *c)
 		return -EINVAL;
 	}
 
-	if (!is_power_of_2(c->min_io_size)) {
-		ubifs_err("bad min. I/O size %d", c->min_io_size);
-		return -EINVAL;
-	}
-
 	/*
 	 * UBIFS aligns all node to 8-byte boundary, so to make function in
 	 * io.c simpler, assume minimum I/O unit size to be 8 bytes if it is
@@ -343,8 +343,13 @@ static int init_constants_early(struct ubifs_info *c)
 		c->min_io_shift = 3;
 	}
 
-	c->ref_node_alsz = ALIGN(UBIFS_REF_NODE_SZ, c->min_io_size);
-	c->mst_node_alsz = ALIGN(UBIFS_MST_NODE_SZ, c->min_io_size);
+	if (c->min_io_shift == 0) {
+		c->ref_node_alsz = roundup(UBIFS_REF_NODE_SZ, c->min_io_size);
+		c->mst_node_alsz = roundup(UBIFS_MST_NODE_SZ, c->min_io_size);
+	} else {
+		c->ref_node_alsz = ALIGN(UBIFS_REF_NODE_SZ, c->min_io_size);
+		c->mst_node_alsz = ALIGN(UBIFS_MST_NODE_SZ, c->min_io_size);
+	}
 
 	/*
 	 * Initialize node length ranges which are mostly needed for node
@@ -383,8 +388,13 @@ static int init_constants_early(struct ubifs_info *c)
 	 * Initialize dead and dark LEB space watermarks. See gc.c for comments
 	 * about these values.
 	 */
-	c->dead_wm = ALIGN(MIN_WRITE_SZ, c->min_io_size);
-	c->dark_wm = ALIGN(UBIFS_MAX_NODE_SZ, c->min_io_size);
+	 if (c->min_io_shift == 0) {
+		c->dead_wm = roundup(MIN_WRITE_SZ, c->min_io_size);
+		c->dark_wm = roundup(UBIFS_MAX_NODE_SZ, c->min_io_size);
+	 } else {
+		c->dead_wm = ALIGN(MIN_WRITE_SZ, c->min_io_size);
+		c->dark_wm = ALIGN(UBIFS_MAX_NODE_SZ, c->min_io_size);
+	 }
 
 	/*
 	 * Calculate how many bytes would be wasted at the end of LEB if it was
@@ -424,7 +434,10 @@ static int init_constants_sb(struct ubifs_info *c)
 
 	/* Make sure LEB size is large enough to fit full commit */
 	tmp = UBIFS_CS_NODE_SZ + UBIFS_REF_NODE_SZ * c->jhead_cnt;
-	tmp = ALIGN(tmp, c->min_io_size);
+	 if (c->min_io_shift == 0)
+	 	tmp = roundup(tmp, c->min_io_size);
+	 else
+		tmp = ALIGN(tmp, c->min_io_size);
 	if (tmp > c->leb_size) {
 		dbg_err("too small LEB size %d, at least %d needed",
 			c->leb_size, tmp);
@@ -655,8 +668,13 @@ static int mount_ubifs(struct ubifs_info *c)
 	if (err)
 		goto out_free;
 
-	sz = ALIGN(c->max_idx_node_sz, c->min_io_size);
-	sz = ALIGN(sz + c->max_idx_node_sz, c->min_io_size);
+	if (c->min_io_shift == 0) {
+		sz = roundup(c->max_idx_node_sz, c->min_io_size);
+		sz = roundup(sz + c->max_idx_node_sz, c->min_io_size);
+	} else {
+		sz = ALIGN(c->max_idx_node_sz, c->min_io_size);
+		sz = ALIGN(sz + c->max_idx_node_sz, c->min_io_size);
+	}
 	c->cbuf = kmalloc(sz, GFP_NOFS);
 	if (!c->cbuf) {
 		err = -ENOMEM;
diff --git a/fs/yaffs2/Makefile b/fs/yaffs2/Makefile
index 904d6466ea..9b29d225a5 100644
--- a/fs/yaffs2/Makefile
+++ b/fs/yaffs2/Makefile
@@ -16,28 +16,43 @@
 #
 # $Id: Makefile,v 1.15 2007/07/18 19:40:38 charles Exp $
 
-#EXTRA_COMPILE_FLAGS = -DYAFFS_IGNORE_TAGS_ECC
 include $(TOPDIR)/config.mk
 
 LIB = $(obj)libyaffs2.o
 
 COBJS-$(CONFIG_YAFFS2) := \
-	yaffscfg.o yaffs_ecc.o yaffsfs.o yaffs_guts.o yaffs_packedtags1.o \
-	yaffs_tagscompat.o yaffs_packedtags2.o yaffs_tagsvalidity.o \
-	yaffs_nand.o yaffs_checkptrw.o yaffs_qsort.o yaffs_mtdif.o \
-	yaffs_mtdif2.o
+	yaffs_allocator.o yaffs_attribs.o yaffs_bitmap.o yaffs_uboot_glue.o\
+	yaffs_checkptrw.o yaffs_ecc.o yaffs_error.o \
+	yaffsfs.o yaffs_guts.o yaffs_nameval.o yaffs_nand.o\
+	yaffs_packedtags1.o yaffs_packedtags2.o yaffs_qsort.o \
+	yaffs_summary.o yaffs_tagscompat.o yaffs_verify.o yaffs_yaffs1.o \
+	yaffs_yaffs2.o yaffs_mtdif.o yaffs_mtdif2.o
 
 SRCS    := $(COBJS-y:.o=.c)
 OBJS    := $(addprefix $(obj),$(COBJS-y))
 
-# -DCONFIG_YAFFS_NO_YAFFS1
-CFLAGS +=    -DCONFIG_YAFFS_DIRECT -DCONFIG_YAFFS_SHORT_NAMES_IN_RAM -DCONFIG_YAFFS_YAFFS2 -DLINUX_VERSION_CODE=0x20622
+YCFLAGS =  -DCONFIG_YAFFS_DIRECT -DCONFIG_YAFFS_SHORT_NAMES_IN_RAM
+YCFLAGS += -DCONFIG_YAFFS_YAFFS2 -DNO_Y_INLINE
+YCFLAGS += -DCONFIG_YAFFS_PROVIDE_DEFS -DCONFIG_YAFFSFS_PROVIDE_VALUES
+
+CFLAGS += $(YCFLAGS)
+CPPFLAGS +=  $(YCFLAGS)
 
 all:  $(LIB)
 
-$(LIB): $(obj).depend $(OBJS)
+$(obj)libyaffs2.a: $(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+$(obj)libyaffs2.o: $(obj).depend $(OBJS)
 	$(call cmd_link_o_target, $(OBJS))
 
+.PHONY: clean distclean
+clean:
+	rm -f $(OBJS)
+
+distclean:  clean
+	rm -f $(LIB) core *.bak .depend
+
 #########################################################################
 
 # defines $(obj).depend target
diff --git a/fs/yaffs2/README-linux b/fs/yaffs2/README-linux
deleted file mode 100644
index 3851e360d8..0000000000
--- a/fs/yaffs2/README-linux
+++ /dev/null
@@ -1,201 +0,0 @@
-Welcome to YAFFS, the first file system developed specifically for NAND flash.
-
-It is now YAFFS2 - original YAFFS (AYFFS1) only supports 512-byte page
-NAND and is now deprectated. YAFFS2 supports 512b page in 'YAFFS1
-compatibility' mode (CONFIG_YAFFS_YAFFS1) and 2K or larger page NAND
-in YAFFS2 mode (CONFIG_YAFFS_YAFFS2).
-
-
-A note on licencing
--------------------
-YAFFS is available under the GPL and via alternative licensing
-arrangements with Aleph One. If you're using YAFFS as a Linux kernel
-file system then it will be under the GPL. For use in other situations
-you should discuss licensing issues with Aleph One.
-
-
-Terminology
------------
-Page -  NAND addressable unit (normally 512b or 2Kbyte size) - can
-	be read, written, marked bad. Has associated OOB.
-Block - Eraseable unit. 64 Pages. (128K on 2K NAND, 32K on 512b NAND)
-OOB -   'spare area' of each page for ECC, bad block marked and YAFFS
-	tags. 16 bytes per 512b - 64 bytes for 2K page size.
-Chunk - Basic YAFFS addressable unit. Same size as Page.
-Object - YAFFS Object: File, Directory, Link, Device etc.
-
-YAFFS design
-------------
-
-YAFFS is a log-structured filesystem. It is designed particularly for
-NAND (as opposed to NOR) flash, to be flash-friendly, robust due to
-journalling, and to have low RAM and boot time overheads. File data is
-stored in 'chunks'. Chunks are the same size as NAND pages. Each page
-is marked with file id and chunk number. These marking 'tags' are
-stored in the OOB (or 'spare') region of the flash. The chunk number
-is determined by dividing the file position by the chunk size. Each
-chunk has a number of valid bytes, which equals the page size for all
-except the last chunk in a file.
-
-File 'headers' are stored as the first page in a file, marked as a
-different type to data pages. The same mechanism is used to store
-directories, device files, links etc. The first page describes which
-type of object it is.
-
-YAFFS2 never re-writes a page, because the spec of NAND chips does not
-allow it. (YAFFS1 used to mark a block 'deleted' in the OOB). Deletion
-is managed by moving deleted objects to the special, hidden 'unlinked'
-directory. These records are preserved until all the pages containing
-the object have been erased (We know when this happen by keeping a
-count of chunks remaining on the system for each object - when it
-reaches zero the object really is gone).
-
-When data in a file is overwritten, the relevant chunks are replaced
-by writing new pages to flash containing the new data but the same
-tags.
-
-Pages are also marked with a short (2 bit) serial number that
-increments each time the page at this position is incremented. The
-reason for this is that if power loss/crash/other act of demonic
-forces happens before the replaced page is marked as discarded, it is
-possible to have two pages with the same tags. The serial number is
-used to arbitrate.
-
-A block containing only discarded pages (termed a dirty block) is an
-obvious candidate for garbage collection. Otherwise valid pages can be
-copied off a block thus rendering the whole block discarded and ready
-for garbage collection.
-
-In theory you don't need to hold the file structure in RAM... you
-could just scan the whole flash looking for pages when you need them.
-In practice though you'd want better file access times than that! The
-mechanism proposed here is to have a list of __u16 page addresses
-associated with each file. Since there are 2^18 pages in a 128MB NAND,
-a __u16 is insufficient to uniquely identify a page but is does
-identify a group of 4 pages - a small enough region to search
-exhaustively. This mechanism is clearly expandable to larger NAND
-devices - within reason. The RAM overhead with this approach is approx
-2 bytes per page - 512kB of RAM for a whole 128MB NAND.
-
-Boot-time scanning to build the file structure lists only requires
-one pass reading NAND. If proper shutdowns happen the current RAM
-summary of the filesystem status is saved to flash, called
-'checkpointing'. This saves re-scanning the flash on startup, and gives
-huge boot/mount time savings.
-
-YAFFS regenerates its state by 'replaying the tape'  - i.e. by
-scanning the chunks in their allocation order (i.e. block sequence ID
-order), which is usually different form the media block order. Each
-block is still only read once - starting from the end of the media and
-working back.
-
-YAFFS tags in YAFFS1 mode:
-
-18-bit Object ID (2^18 files, i.e. > 260,000 files). File id 0- is not
-       valid and indicates a deleted page. File od 0x3ffff is also not valid.
-       Synonymous with inode.
-2-bit  serial number
-20-bit Chunk ID within file. Limit of 2^20 chunks/pages per file (i.e.
-       > 500MB max file size). Chunk ID 0 is the file header for the file.
-10-bit counter of the number of bytes used in the page.
-12 bit ECC on tags
-
-YAFFS tags in YAFFS2 mode:
-  4 bytes 32-bit chunk ID
-  4 bytes 32-bit object ID
-  2 bytes Number of data bytes in this chunk
-  4 bytes Sequence number for this block
-  3 bytes ECC on tags
- 12 bytes ECC on data (3 bytes per 256 bytes of data)
-
-
-Page allocation and garbage collection
-
-Pages are allocated sequentially from the currently selected block.
-When all the pages in the block are filled, another clean block is
-selected for allocation. At least two or three clean blocks are
-reserved for garbage collection purposes. If there are insufficient
-clean blocks available, then a dirty block ( ie one containing only
-discarded pages) is erased to free it up as a clean block. If no dirty
-blocks are available, then the dirtiest block is selected for garbage
-collection.
-
-Garbage collection is performed by copying the valid data pages into
-new data pages thus rendering all the pages in this block dirty and
-freeing it up for erasure. I also like the idea of selecting a block
-at random some small percentage of the time - thus reducing the chance
-of wear differences.
-
-YAFFS is single-threaded. Garbage-collection is done as a parasitic
-task of writing data. So each time some data is written, a bit of
-pending garbage collection is done. More pages are garbage-collected
-when free space is tight.
-
-
-Flash writing
-
-YAFFS only ever writes each page once, complying with the requirements
-of the most restricitve NAND devices.
-
-Wear levelling
-
-This comes as a side-effect of the block-allocation strategy. Data is
-always written on the next free block, so they are all used equally.
-Blocks containing data that is written but never erased will not get
-back into the free list, so wear is levelled over only blocks which
-are free or become free, not blocks which never change.
-
-
-
-Some helpful info
------------------
-
-Formatting a YAFFS device is simply done by erasing it.
-
-Making an initial filesystem can be tricky because YAFFS uses the OOB
-and thus the bytes that get written depend on the YAFFS data (tags),
-and the ECC bytes and bad block markers which are dictated by the
-hardware and/or the MTD subsystem. The data layout also depends on the
-device page size (512b or 2K). Because YAFFS is only responsible for
-some of the OOB data, generating a filesystem offline requires
-detailed knowledge of what the other parts (MTD and NAND
-driver/hardware) are going to do.
-
-To make a YAFFS filesystem you have 3 options:
-
-1) Boot the system with an empty NAND device mounted as YAFFS and copy
-   stuff on.
-
-2) Make a filesystem image offline, then boot the system and use
-   MTDutils to write an image to flash.
-
-3) Make a filesystem image offline and use some tool like a bootloader to
-   write it to flash.
-
-Option 1 avoids a lot of issues because all the parts
-(YAFFS/MTD/hardware) all take care of their own bits and (if you have
-put things together properly) it will 'just work'. YAFFS just needs to
-know how many bytes of the OOB it can use. However sometimes it is not
-practical.
-
-Option 2 lets MTD/hardware take care of the ECC so the filesystem
-image just had to know which bytes to use for YAFFS Tags.
-
-Option 3 is hardest as the image creator needs to know exactly what
-ECC bytes, endianness and algorithm to use as well as which bytes are
-available to YAFFS.
-
-mkyaffs2image creates an image suitable for option 3 for the
-particular case of yaffs2 on 2K page NAND with default MTD layout.
-
-mkyaffsimage creates an equivalent image for 512b page NAND (i.e.
-yaffs1 format).
-
-Bootloaders
------------
-
-A bootloader using YAFFS needs to know how MTD is laying out the OOB
-so that it can skip bad blocks.
-
-YAFFS Tracing
--------------
diff --git a/fs/yaffs2/devextras.h b/fs/yaffs2/devextras.h
deleted file mode 100644
index f6e53610d6..0000000000
--- a/fs/yaffs2/devextras.h
+++ /dev/null
@@ -1,275 +0,0 @@
-/*
- * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
- *
- * Copyright (C) 2002-2007 Aleph One Ltd.
- *   for Toby Churchill Ltd and Brightstar Engineering
- *
- * Created by Charles Manning <charles@aleph1.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License version 2.1 as
- * published by the Free Software Foundation.
- *
- * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
- */
-
-/*
- * This file is just holds extra declarations used during development.
- * Most of these are from kernel includes placed here so we can use them in
- * applications.
- *
- */
-
-#ifndef __EXTRAS_H__
-#define __EXTRAS_H__
-
-#if defined WIN32
-#define __inline__ __inline
-#define new newHack
-#endif
-
-/* XXX U-BOOT XXX */
-#if 1 /* !(defined __KERNEL__) || (defined WIN32) */
-
-/* User space defines */
-
-/* XXX U-BOOT XXX */
-#if 0
-typedef unsigned char __u8;
-typedef unsigned short __u16;
-typedef unsigned __u32;
-#endif
-
-#include <asm/types.h>
-
-/*
- * Simple doubly linked list implementation.
- *
- * Some of the internal functions ("__xxx") are useful when
- * manipulating whole lists rather than single entries, as
- * sometimes we already know the next/prev entries and we can
- * generate better code by using them directly rather than
- * using the generic single-entry routines.
- */
-
-#define prefetch(x) 1
-
-struct list_head {
-	struct list_head *next, *prev;
-};
-
-#define LIST_HEAD_INIT(name) { &(name), &(name) }
-
-#define LIST_HEAD(name) \
-	struct list_head name = LIST_HEAD_INIT(name)
-
-#define INIT_LIST_HEAD(ptr) do { \
-	(ptr)->next = (ptr); (ptr)->prev = (ptr); \
-} while (0)
-
-/*
- * Insert a new entry between two known consecutive entries.
- *
- * This is only for internal list manipulation where we know
- * the prev/next entries already!
- */
-static __inline__ void __list_add(struct list_head *new,
-				  struct list_head *prev,
-				  struct list_head *next)
-{
-	next->prev = new;
-	new->next = next;
-	new->prev = prev;
-	prev->next = new;
-}
-
-/**
- * list_add - add a new entry
- * @new: new entry to be added
- * @head: list head to add it after
- *
- * Insert a new entry after the specified head.
- * This is good for implementing stacks.
- */
-static __inline__ void list_add(struct list_head *new, struct list_head *head)
-{
-	__list_add(new, head, head->next);
-}
-
-/**
- * list_add_tail - add a new entry
- * @new: new entry to be added
- * @head: list head to add it before
- *
- * Insert a new entry before the specified head.
- * This is useful for implementing queues.
- */
-static __inline__ void list_add_tail(struct list_head *new,
-				     struct list_head *head)
-{
-	__list_add(new, head->prev, head);
-}
-
-/*
- * Delete a list entry by making the prev/next entries
- * point to each other.
- *
- * This is only for internal list manipulation where we know
- * the prev/next entries already!
- */
-static __inline__ void __list_del(struct list_head *prev,
-				  struct list_head *next)
-{
-	next->prev = prev;
-	prev->next = next;
-}
-
-/**
- * list_del - deletes entry from list.
- * @entry: the element to delete from the list.
- * Note: list_empty on entry does not return true after this, the entry is
- * in an undefined state.
- */
-static __inline__ void list_del(struct list_head *entry)
-{
-	__list_del(entry->prev, entry->next);
-}
-
-/**
- * list_del_init - deletes entry from list and reinitialize it.
- * @entry: the element to delete from the list.
- */
-static __inline__ void list_del_init(struct list_head *entry)
-{
-	__list_del(entry->prev, entry->next);
-	INIT_LIST_HEAD(entry);
-}
-
-/**
- * list_empty - tests whether a list is empty
- * @head: the list to test.
- */
-static __inline__ int list_empty(struct list_head *head)
-{
-	return head->next == head;
-}
-
-/**
- * list_splice - join two lists
- * @list: the new list to add.
- * @head: the place to add it in the first list.
- */
-static __inline__ void list_splice(struct list_head *list,
-				   struct list_head *head)
-{
-	struct list_head *first = list->next;
-
-	if (first != list) {
-		struct list_head *last = list->prev;
-		struct list_head *at = head->next;
-
-		first->prev = head;
-		head->next = first;
-
-		last->next = at;
-		at->prev = last;
-	}
-}
-
-/**
- * list_entry - get the struct for this entry
- * @ptr:	the &struct list_head pointer.
- * @type:	the type of the struct this is embedded in.
- * @member:	the name of the list_struct within the struct.
- */
-#define list_entry(ptr, type, member) \
-	((type *)((char *)(ptr)-(unsigned long)(&((type *)0)->member)))
-
-/**
- * list_for_each	-	iterate over a list
- * @pos:	the &struct list_head to use as a loop counter.
- * @head:	the head for your list.
- */
-#define list_for_each(pos, head) \
-	for (pos = (head)->next, prefetch(pos->next); pos != (head); \
-		pos = pos->next, prefetch(pos->next))
-
-/**
- * list_for_each_safe	-	iterate over a list safe against removal
- *                              of list entry
- * @pos:	the &struct list_head to use as a loop counter.
- * @n:		another &struct list_head to use as temporary storage
- * @head:	the head for your list.
- */
-#define list_for_each_safe(pos, n, head) \
-	for (pos = (head)->next, n = pos->next; pos != (head); \
-		pos = n, n = pos->next)
-
-/*
- * File types
- */
-#define DT_UNKNOWN	0
-#define DT_FIFO		1
-#define DT_CHR		2
-#define DT_DIR		4
-#define DT_BLK		6
-#define DT_REG		8
-#define DT_LNK		10
-#define DT_SOCK		12
-#define DT_WHT		14
-
-#ifndef WIN32
-/* XXX U-BOOT XXX */
-#if 0
-#include <sys/stat.h>
-#else
-#include "common.h"
-#endif
-#endif
-
-/*
- * Attribute flags.  These should be or-ed together to figure out what
- * has been changed!
- */
-#define ATTR_MODE	1
-#define ATTR_UID	2
-#define ATTR_GID	4
-#define ATTR_SIZE	8
-#define ATTR_ATIME	16
-#define ATTR_MTIME	32
-#define ATTR_CTIME	64
-#define ATTR_ATIME_SET	128
-#define ATTR_MTIME_SET	256
-#define ATTR_FORCE	512	/* Not a change, but a change it */
-#define ATTR_ATTR_FLAG	1024
-
-struct iattr {
-	unsigned int ia_valid;
-	unsigned ia_mode;
-	unsigned ia_uid;
-	unsigned ia_gid;
-	unsigned ia_size;
-	unsigned ia_atime;
-	unsigned ia_mtime;
-	unsigned ia_ctime;
-	unsigned int ia_attr_flags;
-};
-
-#define KERN_DEBUG
-
-#else
-
-#ifndef WIN32
-#include <linux/types.h>
-#include <linux/list.h>
-#include <linux/fs.h>
-#include <linux/stat.h>
-#endif
-
-#endif
-
-#if defined WIN32
-#undef new
-#endif
-
-#endif
diff --git a/fs/yaffs2/yaffs_allocator.c b/fs/yaffs2/yaffs_allocator.c
new file mode 100644
index 0000000000..611061fb45
--- /dev/null
+++ b/fs/yaffs2/yaffs_allocator.c
@@ -0,0 +1,356 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2011 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "yaffs_allocator.h"
+#include "yaffs_guts.h"
+#include "yaffs_trace.h"
+#include "yportenv.h"
+
+/*
+ * Each entry in yaffs_tnode_list and yaffs_obj_list hold blocks
+ * of approx 100 objects that are themn allocated singly.
+ * This is basically a simplified slab allocator.
+ *
+ * We don't use the Linux slab allocator because slab does not allow
+ * us to dump all the objects in one hit when we do a umount and tear
+ * down  all the tnodes and objects. slab requires that we first free
+ * the individual objects.
+ *
+ * Once yaffs has been mainlined I shall try to motivate for a change
+ * to slab to provide the extra features we need here.
+ */
+
+struct yaffs_tnode_list {
+	struct yaffs_tnode_list *next;
+	struct yaffs_tnode *tnodes;
+};
+
+struct yaffs_obj_list {
+	struct yaffs_obj_list *next;
+	struct yaffs_obj *objects;
+};
+
+struct yaffs_allocator {
+	int n_tnodes_created;
+	struct yaffs_tnode *free_tnodes;
+	int n_free_tnodes;
+	struct yaffs_tnode_list *alloc_tnode_list;
+
+	int n_obj_created;
+	struct list_head free_objs;
+	int n_free_objects;
+
+	struct yaffs_obj_list *allocated_obj_list;
+};
+
+static void yaffs_deinit_raw_tnodes(struct yaffs_dev *dev)
+{
+	struct yaffs_allocator *allocator =
+	    (struct yaffs_allocator *)dev->allocator;
+	struct yaffs_tnode_list *tmp;
+
+	if (!allocator) {
+		BUG();
+		return;
+	}
+
+	while (allocator->alloc_tnode_list) {
+		tmp = allocator->alloc_tnode_list->next;
+
+		kfree(allocator->alloc_tnode_list->tnodes);
+		kfree(allocator->alloc_tnode_list);
+		allocator->alloc_tnode_list = tmp;
+	}
+
+	allocator->free_tnodes = NULL;
+	allocator->n_free_tnodes = 0;
+	allocator->n_tnodes_created = 0;
+}
+
+static void yaffs_init_raw_tnodes(struct yaffs_dev *dev)
+{
+	struct yaffs_allocator *allocator = dev->allocator;
+
+	if (!allocator) {
+		BUG();
+		return;
+	}
+
+	allocator->alloc_tnode_list = NULL;
+	allocator->free_tnodes = NULL;
+	allocator->n_free_tnodes = 0;
+	allocator->n_tnodes_created = 0;
+}
+
+static int yaffs_create_tnodes(struct yaffs_dev *dev, int n_tnodes)
+{
+	struct yaffs_allocator *allocator =
+	    (struct yaffs_allocator *)dev->allocator;
+	int i;
+	struct yaffs_tnode *new_tnodes;
+	u8 *mem;
+	struct yaffs_tnode *curr;
+	struct yaffs_tnode *next;
+	struct yaffs_tnode_list *tnl;
+
+	if (!allocator) {
+		BUG();
+		return YAFFS_FAIL;
+	}
+
+	if (n_tnodes < 1)
+		return YAFFS_OK;
+
+	/* make these things */
+	new_tnodes = kmalloc(n_tnodes * dev->tnode_size, GFP_NOFS);
+	mem = (u8 *) new_tnodes;
+
+	if (!new_tnodes) {
+		yaffs_trace(YAFFS_TRACE_ERROR,
+			"yaffs: Could not allocate Tnodes");
+		return YAFFS_FAIL;
+	}
+
+	/* New hookup for wide tnodes */
+	for (i = 0; i < n_tnodes - 1; i++) {
+		curr = (struct yaffs_tnode *)&mem[i * dev->tnode_size];
+		next = (struct yaffs_tnode *)&mem[(i + 1) * dev->tnode_size];
+		curr->internal[0] = next;
+	}
+
+	curr = (struct yaffs_tnode *)&mem[(n_tnodes - 1) * dev->tnode_size];
+	curr->internal[0] = allocator->free_tnodes;
+	allocator->free_tnodes = (struct yaffs_tnode *)mem;
+
+	allocator->n_free_tnodes += n_tnodes;
+	allocator->n_tnodes_created += n_tnodes;
+
+	/* Now add this bunch of tnodes to a list for freeing up.
+	 * NB If we can't add this to the management list it isn't fatal
+	 * but it just means we can't free this bunch of tnodes later.
+	 */
+	tnl = kmalloc(sizeof(struct yaffs_tnode_list), GFP_NOFS);
+	if (!tnl) {
+		yaffs_trace(YAFFS_TRACE_ERROR,
+			"Could not add tnodes to management list");
+		return YAFFS_FAIL;
+	} else {
+		tnl->tnodes = new_tnodes;
+		tnl->next = allocator->alloc_tnode_list;
+		allocator->alloc_tnode_list = tnl;
+	}
+
+	yaffs_trace(YAFFS_TRACE_ALLOCATE, "Tnodes added");
+
+	return YAFFS_OK;
+}
+
+struct yaffs_tnode *yaffs_alloc_raw_tnode(struct yaffs_dev *dev)
+{
+	struct yaffs_allocator *allocator =
+	    (struct yaffs_allocator *)dev->allocator;
+	struct yaffs_tnode *tn = NULL;
+
+	if (!allocator) {
+		BUG();
+		return NULL;
+	}
+
+	/* If there are none left make more */
+	if (!allocator->free_tnodes)
+		yaffs_create_tnodes(dev, YAFFS_ALLOCATION_NTNODES);
+
+	if (allocator->free_tnodes) {
+		tn = allocator->free_tnodes;
+		allocator->free_tnodes = allocator->free_tnodes->internal[0];
+		allocator->n_free_tnodes--;
+	}
+
+	return tn;
+}
+
+/* FreeTnode frees up a tnode and puts it back on the free list */
+void yaffs_free_raw_tnode(struct yaffs_dev *dev, struct yaffs_tnode *tn)
+{
+	struct yaffs_allocator *allocator = dev->allocator;
+
+	if (!allocator) {
+		BUG();
+		return;
+	}
+
+	if (tn) {
+		tn->internal[0] = allocator->free_tnodes;
+		allocator->free_tnodes = tn;
+		allocator->n_free_tnodes++;
+	}
+	dev->checkpoint_blocks_required = 0;	/* force recalculation */
+}
+
+/*--------------- yaffs_obj alloaction ------------------------
+ *
+ * Free yaffs_objs are stored in a list using obj->siblings.
+ * The blocks of allocated objects are stored in a linked list.
+ */
+
+static void yaffs_init_raw_objs(struct yaffs_dev *dev)
+{
+	struct yaffs_allocator *allocator = dev->allocator;
+
+	if (!allocator) {
+		BUG();
+		return;
+	}
+
+	allocator->allocated_obj_list = NULL;
+	INIT_LIST_HEAD(&allocator->free_objs);
+	allocator->n_free_objects = 0;
+}
+
+static void yaffs_deinit_raw_objs(struct yaffs_dev *dev)
+{
+	struct yaffs_allocator *allocator = dev->allocator;
+	struct yaffs_obj_list *tmp;
+
+	if (!allocator) {
+		BUG();
+		return;
+	}
+
+	while (allocator->allocated_obj_list) {
+		tmp = allocator->allocated_obj_list->next;
+		kfree(allocator->allocated_obj_list->objects);
+		kfree(allocator->allocated_obj_list);
+		allocator->allocated_obj_list = tmp;
+	}
+
+	INIT_LIST_HEAD(&allocator->free_objs);
+	allocator->n_free_objects = 0;
+	allocator->n_obj_created = 0;
+}
+
+static int yaffs_create_free_objs(struct yaffs_dev *dev, int n_obj)
+{
+	struct yaffs_allocator *allocator = dev->allocator;
+	int i;
+	struct yaffs_obj *new_objs;
+	struct yaffs_obj_list *list;
+
+	if (!allocator) {
+		BUG();
+		return YAFFS_FAIL;
+	}
+
+	if (n_obj < 1)
+		return YAFFS_OK;
+
+	/* make these things */
+	new_objs = kmalloc(n_obj * sizeof(struct yaffs_obj), GFP_NOFS);
+	list = kmalloc(sizeof(struct yaffs_obj_list), GFP_NOFS);
+
+	if (!new_objs || !list) {
+		kfree(new_objs);
+		new_objs = NULL;
+		kfree(list);
+		list = NULL;
+		yaffs_trace(YAFFS_TRACE_ALLOCATE,
+			"Could not allocate more objects");
+		return YAFFS_FAIL;
+	}
+
+	/* Hook them into the free list */
+	for (i = 0; i < n_obj; i++)
+		list_add(&new_objs[i].siblings, &allocator->free_objs);
+
+	allocator->n_free_objects += n_obj;
+	allocator->n_obj_created += n_obj;
+
+	/* Now add this bunch of Objects to a list for freeing up. */
+
+	list->objects = new_objs;
+	list->next = allocator->allocated_obj_list;
+	allocator->allocated_obj_list = list;
+
+	return YAFFS_OK;
+}
+
+struct yaffs_obj *yaffs_alloc_raw_obj(struct yaffs_dev *dev)
+{
+	struct yaffs_obj *obj = NULL;
+	struct list_head *lh;
+	struct yaffs_allocator *allocator = dev->allocator;
+
+	if (!allocator) {
+		BUG();
+		return obj;
+	}
+
+	/* If there are none left make more */
+	if (list_empty(&allocator->free_objs))
+		yaffs_create_free_objs(dev, YAFFS_ALLOCATION_NOBJECTS);
+
+	if (!list_empty(&allocator->free_objs)) {
+		lh = allocator->free_objs.next;
+		obj = list_entry(lh, struct yaffs_obj, siblings);
+		list_del_init(lh);
+		allocator->n_free_objects--;
+	}
+
+	return obj;
+}
+
+void yaffs_free_raw_obj(struct yaffs_dev *dev, struct yaffs_obj *obj)
+{
+
+	struct yaffs_allocator *allocator = dev->allocator;
+
+	if (!allocator) {
+		BUG();
+		return;
+	}
+
+	/* Link into the free list. */
+	list_add(&obj->siblings, &allocator->free_objs);
+	allocator->n_free_objects++;
+}
+
+void yaffs_deinit_raw_tnodes_and_objs(struct yaffs_dev *dev)
+{
+
+	if (!dev->allocator) {
+		BUG();
+		return;
+	}
+
+	yaffs_deinit_raw_tnodes(dev);
+	yaffs_deinit_raw_objs(dev);
+	kfree(dev->allocator);
+	dev->allocator = NULL;
+}
+
+void yaffs_init_raw_tnodes_and_objs(struct yaffs_dev *dev)
+{
+	struct yaffs_allocator *allocator;
+
+	if (dev->allocator) {
+		BUG();
+		return;
+	}
+
+	allocator = kmalloc(sizeof(struct yaffs_allocator), GFP_NOFS);
+	if (allocator) {
+		dev->allocator = allocator;
+		yaffs_init_raw_tnodes(dev);
+		yaffs_init_raw_objs(dev);
+	}
+}
diff --git a/fs/yaffs2/yaffs_allocator.h b/fs/yaffs2/yaffs_allocator.h
new file mode 100644
index 0000000000..a8cc322642
--- /dev/null
+++ b/fs/yaffs2/yaffs_allocator.h
@@ -0,0 +1,30 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2011 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_ALLOCATOR_H__
+#define __YAFFS_ALLOCATOR_H__
+
+#include "yaffs_guts.h"
+
+void yaffs_init_raw_tnodes_and_objs(struct yaffs_dev *dev);
+void yaffs_deinit_raw_tnodes_and_objs(struct yaffs_dev *dev);
+
+struct yaffs_tnode *yaffs_alloc_raw_tnode(struct yaffs_dev *dev);
+void yaffs_free_raw_tnode(struct yaffs_dev *dev, struct yaffs_tnode *tn);
+
+struct yaffs_obj *yaffs_alloc_raw_obj(struct yaffs_dev *dev);
+void yaffs_free_raw_obj(struct yaffs_dev *dev, struct yaffs_obj *obj);
+
+#endif
diff --git a/fs/yaffs2/yaffs_attribs.c b/fs/yaffs2/yaffs_attribs.c
new file mode 100644
index 0000000000..69664268e1
--- /dev/null
+++ b/fs/yaffs2/yaffs_attribs.c
@@ -0,0 +1,152 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2011 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "yaffs_attribs.h"
+
+
+void yaffs_load_attribs(struct yaffs_obj *obj, struct yaffs_obj_hdr *oh)
+{
+	obj->yst_uid = oh->yst_uid;
+	obj->yst_gid = oh->yst_gid;
+	obj->yst_atime = oh->yst_atime;
+	obj->yst_mtime = oh->yst_mtime;
+	obj->yst_ctime = oh->yst_ctime;
+	obj->yst_rdev = oh->yst_rdev;
+}
+
+
+void yaffs_load_attribs_oh(struct yaffs_obj_hdr *oh, struct yaffs_obj *obj)
+{
+#ifdef CONFIG_YAFFS_WINCE
+		oh->win_atime[0] = obj->win_atime[0];
+		oh->win_ctime[0] = obj->win_ctime[0];
+		oh->win_mtime[0] = obj->win_mtime[0];
+		oh->win_atime[1] = obj->win_atime[1];
+		oh->win_ctime[1] = obj->win_ctime[1];
+		oh->win_mtime[1] = obj->win_mtime[1];
+#else
+		oh->yst_uid = obj->yst_uid;
+		oh->yst_gid = obj->yst_gid;
+		oh->yst_atime = obj->yst_atime;
+		oh->yst_mtime = obj->yst_mtime;
+		oh->yst_ctime = obj->yst_ctime;
+		oh->yst_rdev = obj->yst_rdev;
+#endif
+
+}
+
+void yaffs_attribs_init(struct yaffs_obj *obj, u32 gid, u32 uid, u32 rdev)
+{
+
+#ifdef CONFIG_YAFFS_WINCE
+		yfsd_win_file_time_now(obj->win_atime);
+		obj->win_ctime[0] = obj->win_mtime[0] = obj->win_atime[0];
+		obj->win_ctime[1] = obj->win_mtime[1] = obj->win_atime[1];
+
+#else
+	yaffs_load_current_time(obj, 1, 1);
+	obj->yst_rdev = rdev;
+	obj->yst_uid = uid;
+	obj->yst_gid = gid;
+#endif
+}
+
+void yaffs_load_current_time(struct yaffs_obj *obj, int do_a, int do_c)
+{
+#ifdef CONFIG_YAFFS_WINCE
+		yfsd_win_file_time_now(the_obj->win_atime);
+		the_obj->win_ctime[0] = the_obj->win_mtime[0] =
+		    the_obj->win_atime[0];
+		the_obj->win_ctime[1] = the_obj->win_mtime[1] =
+		    the_obj->win_atime[1];
+
+#else
+
+	obj->yst_mtime = Y_CURRENT_TIME;
+	if (do_a)
+		obj->yst_atime = obj->yst_atime;
+	if (do_c)
+		obj->yst_ctime = obj->yst_atime;
+#endif
+}
+
+loff_t yaffs_get_file_size(struct yaffs_obj *obj)
+{
+	YCHAR *alias = NULL;
+	obj = yaffs_get_equivalent_obj(obj);
+
+	switch (obj->variant_type) {
+	case YAFFS_OBJECT_TYPE_FILE:
+		return obj->variant.file_variant.file_size;
+	case YAFFS_OBJECT_TYPE_SYMLINK:
+		alias = obj->variant.symlink_variant.alias;
+		if (!alias)
+			return 0;
+		return yaffs_strnlen(alias, YAFFS_MAX_ALIAS_LENGTH);
+	default:
+		return 0;
+	}
+}
+
+int yaffs_set_attribs(struct yaffs_obj *obj, struct iattr *attr)
+{
+	unsigned int valid = attr->ia_valid;
+
+	if (valid & ATTR_MODE)
+		obj->yst_mode = attr->ia_mode;
+	if (valid & ATTR_UID)
+		obj->yst_uid = attr->ia_uid;
+	if (valid & ATTR_GID)
+		obj->yst_gid = attr->ia_gid;
+
+	if (valid & ATTR_ATIME)
+		obj->yst_atime = Y_TIME_CONVERT(attr->ia_atime);
+	if (valid & ATTR_CTIME)
+		obj->yst_ctime = Y_TIME_CONVERT(attr->ia_ctime);
+	if (valid & ATTR_MTIME)
+		obj->yst_mtime = Y_TIME_CONVERT(attr->ia_mtime);
+
+	if (valid & ATTR_SIZE)
+		yaffs_resize_file(obj, attr->ia_size);
+
+	yaffs_update_oh(obj, NULL, 1, 0, 0, NULL);
+
+	return YAFFS_OK;
+
+}
+
+int yaffs_get_attribs(struct yaffs_obj *obj, struct iattr *attr)
+{
+	unsigned int valid = 0;
+
+	attr->ia_mode = obj->yst_mode;
+	valid |= ATTR_MODE;
+	attr->ia_uid = obj->yst_uid;
+	valid |= ATTR_UID;
+	attr->ia_gid = obj->yst_gid;
+	valid |= ATTR_GID;
+
+	Y_TIME_CONVERT(attr->ia_atime) = obj->yst_atime;
+	valid |= ATTR_ATIME;
+	Y_TIME_CONVERT(attr->ia_ctime) = obj->yst_ctime;
+	valid |= ATTR_CTIME;
+	Y_TIME_CONVERT(attr->ia_mtime) = obj->yst_mtime;
+	valid |= ATTR_MTIME;
+
+	attr->ia_size = yaffs_get_file_size(obj);
+	valid |= ATTR_SIZE;
+
+	attr->ia_valid = valid;
+
+	return YAFFS_OK;
+}
diff --git a/fs/yaffs2/yaffs_attribs.h b/fs/yaffs2/yaffs_attribs.h
new file mode 100644
index 0000000000..5b21b085b7
--- /dev/null
+++ b/fs/yaffs2/yaffs_attribs.h
@@ -0,0 +1,28 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2011 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_ATTRIBS_H__
+#define __YAFFS_ATTRIBS_H__
+
+#include "yaffs_guts.h"
+
+void yaffs_load_attribs(struct yaffs_obj *obj, struct yaffs_obj_hdr *oh);
+void yaffs_load_attribs_oh(struct yaffs_obj_hdr *oh, struct yaffs_obj *obj);
+void yaffs_attribs_init(struct yaffs_obj *obj, u32 gid, u32 uid, u32 rdev);
+void yaffs_load_current_time(struct yaffs_obj *obj, int do_a, int do_c);
+int yaffs_set_attribs(struct yaffs_obj *obj, struct iattr *attr);
+int yaffs_get_attribs(struct yaffs_obj *obj, struct iattr *attr);
+
+#endif
diff --git a/fs/yaffs2/yaffs_bitmap.c b/fs/yaffs2/yaffs_bitmap.c
new file mode 100644
index 0000000000..4440e930d6
--- /dev/null
+++ b/fs/yaffs2/yaffs_bitmap.c
@@ -0,0 +1,97 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2011 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "yaffs_bitmap.h"
+#include "yaffs_trace.h"
+/*
+ * Chunk bitmap manipulations
+ */
+
+static inline u8 *yaffs_block_bits(struct yaffs_dev *dev, int blk)
+{
+	if (blk < dev->internal_start_block || blk > dev->internal_end_block) {
+		yaffs_trace(YAFFS_TRACE_ERROR,
+			"BlockBits block %d is not valid",
+			blk);
+		BUG();
+	}
+	return dev->chunk_bits +
+	    (dev->chunk_bit_stride * (blk - dev->internal_start_block));
+}
+
+void yaffs_verify_chunk_bit_id(struct yaffs_dev *dev, int blk, int chunk)
+{
+	if (blk < dev->internal_start_block || blk > dev->internal_end_block ||
+	    chunk < 0 || chunk >= dev->param.chunks_per_block) {
+		yaffs_trace(YAFFS_TRACE_ERROR,
+			"Chunk Id (%d:%d) invalid",
+			blk, chunk);
+		BUG();
+	}
+}
+
+void yaffs_clear_chunk_bits(struct yaffs_dev *dev, int blk)
+{
+	u8 *blk_bits = yaffs_block_bits(dev, blk);
+
+	memset(blk_bits, 0, dev->chunk_bit_stride);
+}
+
+void yaffs_clear_chunk_bit(struct yaffs_dev *dev, int blk, int chunk)
+{
+	u8 *blk_bits = yaffs_block_bits(dev, blk);
+
+	yaffs_verify_chunk_bit_id(dev, blk, chunk);
+	blk_bits[chunk / 8] &= ~(1 << (chunk & 7));
+}
+
+void yaffs_set_chunk_bit(struct yaffs_dev *dev, int blk, int chunk)
+{
+	u8 *blk_bits = yaffs_block_bits(dev, blk);
+
+	yaffs_verify_chunk_bit_id(dev, blk, chunk);
+	blk_bits[chunk / 8] |= (1 << (chunk & 7));
+}
+
+int yaffs_check_chunk_bit(struct yaffs_dev *dev, int blk, int chunk)
+{
+	u8 *blk_bits = yaffs_block_bits(dev, blk);
+
+	yaffs_verify_chunk_bit_id(dev, blk, chunk);
+	return (blk_bits[chunk / 8] & (1 << (chunk & 7))) ? 1 : 0;
+}
+
+int yaffs_still_some_chunks(struct yaffs_dev *dev, int blk)
+{
+	u8 *blk_bits = yaffs_block_bits(dev, blk);
+	int i;
+
+	for (i = 0; i < dev->chunk_bit_stride; i++) {
+		if (*blk_bits)
+			return 1;
+		blk_bits++;
+	}
+	return 0;
+}
+
+int yaffs_count_chunk_bits(struct yaffs_dev *dev, int blk)
+{
+	u8 *blk_bits = yaffs_block_bits(dev, blk);
+	int i;
+	int n = 0;
+
+	for (i = 0; i < dev->chunk_bit_stride; i++, blk_bits++)
+		n += hweight8(*blk_bits);
+
+	return n;
+}
diff --git a/fs/yaffs2/yaffs_bitmap.h b/fs/yaffs2/yaffs_bitmap.h
new file mode 100644
index 0000000000..e26b37d89a
--- /dev/null
+++ b/fs/yaffs2/yaffs_bitmap.h
@@ -0,0 +1,33 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2011 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+/*
+ * Chunk bitmap manipulations
+ */
+
+#ifndef __YAFFS_BITMAP_H__
+#define __YAFFS_BITMAP_H__
+
+#include "yaffs_guts.h"
+
+void yaffs_verify_chunk_bit_id(struct yaffs_dev *dev, int blk, int chunk);
+void yaffs_clear_chunk_bits(struct yaffs_dev *dev, int blk);
+void yaffs_clear_chunk_bit(struct yaffs_dev *dev, int blk, int chunk);
+void yaffs_set_chunk_bit(struct yaffs_dev *dev, int blk, int chunk);
+int yaffs_check_chunk_bit(struct yaffs_dev *dev, int blk, int chunk);
+int yaffs_still_some_chunks(struct yaffs_dev *dev, int blk);
+int yaffs_count_chunk_bits(struct yaffs_dev *dev, int blk);
+
+#endif
diff --git a/fs/yaffs2/yaffs_checkptrw.c b/fs/yaffs2/yaffs_checkptrw.c
index 230f78fb89..997a618aee 100644
--- a/fs/yaffs2/yaffs_checkptrw.c
+++ b/fs/yaffs2/yaffs_checkptrw.c
@@ -1,7 +1,7 @@
 /*
  * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
  *
- * Copyright (C) 2002-2007 Aleph One Ltd.
+ * Copyright (C) 2002-2011 Aleph One Ltd.
  *   for Toby Churchill Ltd and Brightstar Engineering
  *
  * Created by Charles Manning <charles@aleph1.co.uk>
@@ -11,395 +11,398 @@
  * published by the Free Software Foundation.
  */
 
-/* XXX U-BOOT XXX */
-#include <common.h>
-#include <malloc.h>
-
-const char *yaffs_checkptrw_c_version =
-    "$Id: yaffs_checkptrw.c,v 1.14 2007/05/15 20:07:40 charles Exp $";
-
-
 #include "yaffs_checkptrw.h"
+#include "yaffs_getblockinfo.h"
 
-
-static int yaffs_CheckpointSpaceOk(yaffs_Device *dev)
+static int yaffs2_checkpt_space_ok(struct yaffs_dev *dev)
 {
+	int blocks_avail = dev->n_erased_blocks - dev->param.n_reserved_blocks;
 
-	int blocksAvailable = dev->nErasedBlocks - dev->nReservedBlocks;
+	yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+		"checkpt blocks_avail = %d", blocks_avail);
 
-	T(YAFFS_TRACE_CHECKPOINT,
-		(TSTR("checkpt blocks available = %d" TENDSTR),
-		blocksAvailable));
-
-
-	return (blocksAvailable <= 0) ? 0 : 1;
+	return (blocks_avail <= 0) ? 0 : 1;
 }
 
-
-static int yaffs_CheckpointErase(yaffs_Device *dev)
+static int yaffs_checkpt_erase(struct yaffs_dev *dev)
 {
-
 	int i;
 
-
-	if(!dev->eraseBlockInNAND)
+	if (!dev->param.erase_fn)
 		return 0;
-	T(YAFFS_TRACE_CHECKPOINT,(TSTR("checking blocks %d to %d"TENDSTR),
-		dev->internalStartBlock,dev->internalEndBlock));
-
-	for(i = dev->internalStartBlock; i <= dev->internalEndBlock; i++) {
-		yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev,i);
-		if(bi->blockState == YAFFS_BLOCK_STATE_CHECKPOINT){
-			T(YAFFS_TRACE_CHECKPOINT,(TSTR("erasing checkpt block %d"TENDSTR),i));
-			if(dev->eraseBlockInNAND(dev,i- dev->blockOffset /* realign */)){
-				bi->blockState = YAFFS_BLOCK_STATE_EMPTY;
-				dev->nErasedBlocks++;
-				dev->nFreeChunks += dev->nChunksPerBlock;
-			}
-			else {
-				dev->markNANDBlockBad(dev,i);
-				bi->blockState = YAFFS_BLOCK_STATE_DEAD;
+	yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+		"checking blocks %d to %d",
+		dev->internal_start_block, dev->internal_end_block);
+
+	for (i = dev->internal_start_block; i <= dev->internal_end_block; i++) {
+		struct yaffs_block_info *bi = yaffs_get_block_info(dev, i);
+		if (bi->block_state == YAFFS_BLOCK_STATE_CHECKPOINT) {
+			yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+			"erasing checkpt block %d", i);
+
+			dev->n_erasures++;
+
+			if (dev->param.
+			    erase_fn(dev,
+				     i - dev->block_offset /* realign */)) {
+				bi->block_state = YAFFS_BLOCK_STATE_EMPTY;
+				dev->n_erased_blocks++;
+				dev->n_free_chunks +=
+				    dev->param.chunks_per_block;
+			} else {
+				dev->param.bad_block_fn(dev, i);
+				bi->block_state = YAFFS_BLOCK_STATE_DEAD;
 			}
 		}
 	}
 
-	dev->blocksInCheckpoint = 0;
+	dev->blocks_in_checkpt = 0;
 
 	return 1;
 }
 
-
-static void yaffs_CheckpointFindNextErasedBlock(yaffs_Device *dev)
+static void yaffs2_checkpt_find_erased_block(struct yaffs_dev *dev)
 {
-	int  i;
-	int blocksAvailable = dev->nErasedBlocks - dev->nReservedBlocks;
-	T(YAFFS_TRACE_CHECKPOINT,
-		(TSTR("allocating checkpt block: erased %d reserved %d avail %d next %d "TENDSTR),
-		dev->nErasedBlocks,dev->nReservedBlocks,blocksAvailable,dev->checkpointNextBlock));
-
-	if(dev->checkpointNextBlock >= 0 &&
-	   dev->checkpointNextBlock <= dev->internalEndBlock &&
-	   blocksAvailable > 0){
-
-		for(i = dev->checkpointNextBlock; i <= dev->internalEndBlock; i++){
-			yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev,i);
-			if(bi->blockState == YAFFS_BLOCK_STATE_EMPTY){
-				dev->checkpointNextBlock = i + 1;
-				dev->checkpointCurrentBlock = i;
-				T(YAFFS_TRACE_CHECKPOINT,(TSTR("allocating checkpt block %d"TENDSTR),i));
+	int i;
+	int blocks_avail = dev->n_erased_blocks - dev->param.n_reserved_blocks;
+
+	yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+		"allocating checkpt block: erased %d reserved %d avail %d next %d ",
+		dev->n_erased_blocks, dev->param.n_reserved_blocks,
+		blocks_avail, dev->checkpt_next_block);
+
+	if (dev->checkpt_next_block >= 0 &&
+	    dev->checkpt_next_block <= dev->internal_end_block &&
+	    blocks_avail > 0) {
+
+		for (i = dev->checkpt_next_block; i <= dev->internal_end_block;
+		     i++) {
+			struct yaffs_block_info *bi =
+			    yaffs_get_block_info(dev, i);
+			if (bi->block_state == YAFFS_BLOCK_STATE_EMPTY) {
+				dev->checkpt_next_block = i + 1;
+				dev->checkpt_cur_block = i;
+				yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+					"allocating checkpt block %d", i);
 				return;
 			}
 		}
 	}
-	T(YAFFS_TRACE_CHECKPOINT,(TSTR("out of checkpt blocks"TENDSTR)));
+	yaffs_trace(YAFFS_TRACE_CHECKPOINT, "out of checkpt blocks");
 
-	dev->checkpointNextBlock = -1;
-	dev->checkpointCurrentBlock = -1;
+	dev->checkpt_next_block = -1;
+	dev->checkpt_cur_block = -1;
 }
 
-static void yaffs_CheckpointFindNextCheckpointBlock(yaffs_Device *dev)
+static void yaffs2_checkpt_find_block(struct yaffs_dev *dev)
 {
-	int  i;
-	yaffs_ExtendedTags tags;
-
-	T(YAFFS_TRACE_CHECKPOINT,(TSTR("find next checkpt block: start:  blocks %d next %d" TENDSTR),
-		dev->blocksInCheckpoint, dev->checkpointNextBlock));
-
-	if(dev->blocksInCheckpoint < dev->checkpointMaxBlocks)
-		for(i = dev->checkpointNextBlock; i <= dev->internalEndBlock; i++){
-			int chunk = i * dev->nChunksPerBlock;
-			int realignedChunk = chunk - dev->chunkOffset;
-
-			dev->readChunkWithTagsFromNAND(dev,realignedChunk,NULL,&tags);
-			T(YAFFS_TRACE_CHECKPOINT,(TSTR("find next checkpt block: search: block %d oid %d seq %d eccr %d" TENDSTR),
-				i, tags.objectId,tags.sequenceNumber,tags.eccResult));
-
-			if(tags.sequenceNumber == YAFFS_SEQUENCE_CHECKPOINT_DATA){
+	int i;
+	struct yaffs_ext_tags tags;
+
+	yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+		"find next checkpt block: start:  blocks %d next %d",
+		dev->blocks_in_checkpt, dev->checkpt_next_block);
+
+	if (dev->blocks_in_checkpt < dev->checkpt_max_blocks)
+		for (i = dev->checkpt_next_block; i <= dev->internal_end_block;
+		     i++) {
+			int chunk = i * dev->param.chunks_per_block;
+			int realigned_chunk = chunk - dev->chunk_offset;
+
+			dev->param.read_chunk_tags_fn(dev, realigned_chunk,
+						      NULL, &tags);
+			yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+				"find next checkpt block: search: block %d oid %d seq %d eccr %d",
+				i, tags.obj_id, tags.seq_number,
+				tags.ecc_result);
+
+			if (tags.seq_number == YAFFS_SEQUENCE_CHECKPOINT_DATA) {
 				/* Right kind of block */
-				dev->checkpointNextBlock = tags.objectId;
-				dev->checkpointCurrentBlock = i;
-				dev->checkpointBlockList[dev->blocksInCheckpoint] = i;
-				dev->blocksInCheckpoint++;
-				T(YAFFS_TRACE_CHECKPOINT,(TSTR("found checkpt block %d"TENDSTR),i));
+				dev->checkpt_next_block = tags.obj_id;
+				dev->checkpt_cur_block = i;
+				dev->checkpt_block_list[dev->
+							blocks_in_checkpt] = i;
+				dev->blocks_in_checkpt++;
+				yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+					"found checkpt block %d", i);
 				return;
 			}
 		}
 
-	T(YAFFS_TRACE_CHECKPOINT,(TSTR("found no more checkpt blocks"TENDSTR)));
+	yaffs_trace(YAFFS_TRACE_CHECKPOINT, "found no more checkpt blocks");
 
-	dev->checkpointNextBlock = -1;
-	dev->checkpointCurrentBlock = -1;
+	dev->checkpt_next_block = -1;
+	dev->checkpt_cur_block = -1;
 }
 
-
-int yaffs_CheckpointOpen(yaffs_Device *dev, int forWriting)
+int yaffs2_checkpt_open(struct yaffs_dev *dev, int writing)
 {
+	int i;
+
+	dev->checkpt_open_write = writing;
 
 	/* Got the functions we need? */
-	if (!dev->writeChunkWithTagsToNAND ||
-	    !dev->readChunkWithTagsFromNAND ||
-	    !dev->eraseBlockInNAND ||
-	    !dev->markNANDBlockBad)
+	if (!dev->param.write_chunk_tags_fn ||
+	    !dev->param.read_chunk_tags_fn ||
+	    !dev->param.erase_fn || !dev->param.bad_block_fn)
 		return 0;
 
-	if(forWriting && !yaffs_CheckpointSpaceOk(dev))
+	if (writing && !yaffs2_checkpt_space_ok(dev))
 		return 0;
 
-	if(!dev->checkpointBuffer)
-		dev->checkpointBuffer = YMALLOC_DMA(dev->nDataBytesPerChunk);
-	if(!dev->checkpointBuffer)
+	if (!dev->checkpt_buffer)
+		dev->checkpt_buffer =
+		    kmalloc(dev->param.total_bytes_per_chunk, GFP_NOFS);
+	if (!dev->checkpt_buffer)
 		return 0;
 
-
-	dev->checkpointPageSequence = 0;
-
-	dev->checkpointOpenForWrite = forWriting;
-
-	dev->checkpointByteCount = 0;
-	dev->checkpointSum = 0;
-	dev->checkpointXor = 0;
-	dev->checkpointCurrentBlock = -1;
-	dev->checkpointCurrentChunk = -1;
-	dev->checkpointNextBlock = dev->internalStartBlock;
+	dev->checkpt_page_seq = 0;
+	dev->checkpt_byte_count = 0;
+	dev->checkpt_sum = 0;
+	dev->checkpt_xor = 0;
+	dev->checkpt_cur_block = -1;
+	dev->checkpt_cur_chunk = -1;
+	dev->checkpt_next_block = dev->internal_start_block;
 
 	/* Erase all the blocks in the checkpoint area */
-	if(forWriting){
-		memset(dev->checkpointBuffer,0,dev->nDataBytesPerChunk);
-		dev->checkpointByteOffset = 0;
-		return yaffs_CheckpointErase(dev);
+	if (writing) {
+		memset(dev->checkpt_buffer, 0, dev->data_bytes_per_chunk);
+		dev->checkpt_byte_offs = 0;
+		return yaffs_checkpt_erase(dev);
+	}
 
+	/* Set to a value that will kick off a read */
+	dev->checkpt_byte_offs = dev->data_bytes_per_chunk;
+	/* A checkpoint block list of 1 checkpoint block per 16 block is
+	 * (hopefully) going to be way more than we need */
+	dev->blocks_in_checkpt = 0;
+	dev->checkpt_max_blocks =
+	    (dev->internal_end_block - dev->internal_start_block) / 16 + 2;
+	dev->checkpt_block_list =
+	    kmalloc(sizeof(int) * dev->checkpt_max_blocks, GFP_NOFS);
+
+	if (!dev->checkpt_block_list)
+		return 0;
 
-	} else {
-		int i;
-		/* Set to a value that will kick off a read */
-		dev->checkpointByteOffset = dev->nDataBytesPerChunk;
-		/* A checkpoint block list of 1 checkpoint block per 16 block is (hopefully)
-		 * going to be way more than we need */
-		dev->blocksInCheckpoint = 0;
-		dev->checkpointMaxBlocks = (dev->internalEndBlock - dev->internalStartBlock)/16 + 2;
-		dev->checkpointBlockList = YMALLOC(sizeof(int) * dev->checkpointMaxBlocks);
-		for(i = 0; i < dev->checkpointMaxBlocks; i++)
-			dev->checkpointBlockList[i] = -1;
-	}
+	for (i = 0; i < dev->checkpt_max_blocks; i++)
+		dev->checkpt_block_list[i] = -1;
 
 	return 1;
 }
 
-int yaffs_GetCheckpointSum(yaffs_Device *dev, __u32 *sum)
+int yaffs2_get_checkpt_sum(struct yaffs_dev *dev, u32 * sum)
 {
-	__u32 compositeSum;
-	compositeSum =  (dev->checkpointSum << 8) | (dev->checkpointXor & 0xFF);
-	*sum = compositeSum;
+	u32 composite_sum;
+
+	composite_sum = (dev->checkpt_sum << 8) | (dev->checkpt_xor & 0xff);
+	*sum = composite_sum;
 	return 1;
 }
 
-static int yaffs_CheckpointFlushBuffer(yaffs_Device *dev)
+static int yaffs2_checkpt_flush_buffer(struct yaffs_dev *dev)
 {
-
 	int chunk;
-	int realignedChunk;
-
-	yaffs_ExtendedTags tags;
+	int realigned_chunk;
+	struct yaffs_ext_tags tags;
 
-	if(dev->checkpointCurrentBlock < 0){
-		yaffs_CheckpointFindNextErasedBlock(dev);
-		dev->checkpointCurrentChunk = 0;
+	if (dev->checkpt_cur_block < 0) {
+		yaffs2_checkpt_find_erased_block(dev);
+		dev->checkpt_cur_chunk = 0;
 	}
 
-	if(dev->checkpointCurrentBlock < 0)
+	if (dev->checkpt_cur_block < 0)
 		return 0;
 
-	tags.chunkDeleted = 0;
-	tags.objectId = dev->checkpointNextBlock; /* Hint to next place to look */
-	tags.chunkId = dev->checkpointPageSequence + 1;
-	tags.sequenceNumber =  YAFFS_SEQUENCE_CHECKPOINT_DATA;
-	tags.byteCount = dev->nDataBytesPerChunk;
-	if(dev->checkpointCurrentChunk == 0){
+	tags.is_deleted = 0;
+	tags.obj_id = dev->checkpt_next_block;	/* Hint to next place to look */
+	tags.chunk_id = dev->checkpt_page_seq + 1;
+	tags.seq_number = YAFFS_SEQUENCE_CHECKPOINT_DATA;
+	tags.n_bytes = dev->data_bytes_per_chunk;
+	if (dev->checkpt_cur_chunk == 0) {
 		/* First chunk we write for the block? Set block state to
 		   checkpoint */
-		yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev,dev->checkpointCurrentBlock);
-		bi->blockState = YAFFS_BLOCK_STATE_CHECKPOINT;
-		dev->blocksInCheckpoint++;
+		struct yaffs_block_info *bi =
+		    yaffs_get_block_info(dev, dev->checkpt_cur_block);
+		bi->block_state = YAFFS_BLOCK_STATE_CHECKPOINT;
+		dev->blocks_in_checkpt++;
 	}
 
-	chunk = dev->checkpointCurrentBlock * dev->nChunksPerBlock + dev->checkpointCurrentChunk;
+	chunk =
+	    dev->checkpt_cur_block * dev->param.chunks_per_block +
+	    dev->checkpt_cur_chunk;
 
+	yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+		"checkpoint wite buffer nand %d(%d:%d) objid %d chId %d",
+		chunk, dev->checkpt_cur_block, dev->checkpt_cur_chunk,
+		tags.obj_id, tags.chunk_id);
 
-	T(YAFFS_TRACE_CHECKPOINT,(TSTR("checkpoint wite buffer nand %d(%d:%d) objid %d chId %d" TENDSTR),
-		chunk, dev->checkpointCurrentBlock, dev->checkpointCurrentChunk,tags.objectId,tags.chunkId));
+	realigned_chunk = chunk - dev->chunk_offset;
 
-	realignedChunk = chunk - dev->chunkOffset;
+	dev->n_page_writes++;
 
-	dev->writeChunkWithTagsToNAND(dev,realignedChunk,dev->checkpointBuffer,&tags);
-	dev->checkpointByteOffset = 0;
-	dev->checkpointPageSequence++;
-	dev->checkpointCurrentChunk++;
-	if(dev->checkpointCurrentChunk >= dev->nChunksPerBlock){
-		dev->checkpointCurrentChunk = 0;
-		dev->checkpointCurrentBlock = -1;
+	dev->param.write_chunk_tags_fn(dev, realigned_chunk,
+				       dev->checkpt_buffer, &tags);
+	dev->checkpt_byte_offs = 0;
+	dev->checkpt_page_seq++;
+	dev->checkpt_cur_chunk++;
+	if (dev->checkpt_cur_chunk >= dev->param.chunks_per_block) {
+		dev->checkpt_cur_chunk = 0;
+		dev->checkpt_cur_block = -1;
 	}
-	memset(dev->checkpointBuffer,0,dev->nDataBytesPerChunk);
+	memset(dev->checkpt_buffer, 0, dev->data_bytes_per_chunk);
 
 	return 1;
 }
 
-
-int yaffs_CheckpointWrite(yaffs_Device *dev,const void *data, int nBytes)
+int yaffs2_checkpt_wr(struct yaffs_dev *dev, const void *data, int n_bytes)
 {
-	int i=0;
+	int i = 0;
 	int ok = 1;
+	u8 *data_bytes = (u8 *) data;
 
-
-	__u8 * dataBytes = (__u8 *)data;
-
-
-
-	if(!dev->checkpointBuffer)
+	if (!dev->checkpt_buffer)
 		return 0;
 
-	if(!dev->checkpointOpenForWrite)
+	if (!dev->checkpt_open_write)
 		return -1;
 
-	while(i < nBytes && ok) {
-
-
-
-		dev->checkpointBuffer[dev->checkpointByteOffset] = *dataBytes ;
-		dev->checkpointSum += *dataBytes;
-		dev->checkpointXor ^= *dataBytes;
+	while (i < n_bytes && ok) {
+		dev->checkpt_buffer[dev->checkpt_byte_offs] = *data_bytes;
+		dev->checkpt_sum += *data_bytes;
+		dev->checkpt_xor ^= *data_bytes;
 
-		dev->checkpointByteOffset++;
+		dev->checkpt_byte_offs++;
 		i++;
-		dataBytes++;
-		dev->checkpointByteCount++;
-
-
-		if(dev->checkpointByteOffset < 0 ||
-		   dev->checkpointByteOffset >= dev->nDataBytesPerChunk)
-			ok = yaffs_CheckpointFlushBuffer(dev);
+		data_bytes++;
+		dev->checkpt_byte_count++;
 
+		if (dev->checkpt_byte_offs < 0 ||
+		    dev->checkpt_byte_offs >= dev->data_bytes_per_chunk)
+			ok = yaffs2_checkpt_flush_buffer(dev);
 	}
 
-	return 	i;
+	return i;
 }
 
-int yaffs_CheckpointRead(yaffs_Device *dev, void *data, int nBytes)
+int yaffs2_checkpt_rd(struct yaffs_dev *dev, void *data, int n_bytes)
 {
-	int i=0;
+	int i = 0;
 	int ok = 1;
-	yaffs_ExtendedTags tags;
-
-
+	struct yaffs_ext_tags tags;
 	int chunk;
-	int realignedChunk;
+	int realigned_chunk;
+	u8 *data_bytes = (u8 *) data;
 
-	__u8 *dataBytes = (__u8 *)data;
-
-	if(!dev->checkpointBuffer)
+	if (!dev->checkpt_buffer)
 		return 0;
 
-	if(dev->checkpointOpenForWrite)
+	if (dev->checkpt_open_write)
 		return -1;
 
-	while(i < nBytes && ok) {
-
+	while (i < n_bytes && ok) {
 
-		if(dev->checkpointByteOffset < 0 ||
-		   dev->checkpointByteOffset >= dev->nDataBytesPerChunk) {
+		if (dev->checkpt_byte_offs < 0 ||
+		    dev->checkpt_byte_offs >= dev->data_bytes_per_chunk) {
 
-		   	if(dev->checkpointCurrentBlock < 0){
-				yaffs_CheckpointFindNextCheckpointBlock(dev);
-				dev->checkpointCurrentChunk = 0;
+			if (dev->checkpt_cur_block < 0) {
+				yaffs2_checkpt_find_block(dev);
+				dev->checkpt_cur_chunk = 0;
 			}
 
-			if(dev->checkpointCurrentBlock < 0)
+			if (dev->checkpt_cur_block < 0) {
 				ok = 0;
-			else {
+				break;
+			}
 
-				chunk = dev->checkpointCurrentBlock * dev->nChunksPerBlock +
-				          dev->checkpointCurrentChunk;
+			chunk = dev->checkpt_cur_block *
+			    dev->param.chunks_per_block +
+			    dev->checkpt_cur_chunk;
 
-				realignedChunk = chunk - dev->chunkOffset;
+			realigned_chunk = chunk - dev->chunk_offset;
+			dev->n_page_reads++;
 
-	   			/* read in the next chunk */
-	   			/* printf("read checkpoint page %d\n",dev->checkpointPage); */
-				dev->readChunkWithTagsFromNAND(dev, realignedChunk,
-							       dev->checkpointBuffer,
-							      &tags);
+			/* read in the next chunk */
+			dev->param.read_chunk_tags_fn(dev,
+						realigned_chunk,
+						dev->checkpt_buffer,
+						&tags);
 
-				if(tags.chunkId != (dev->checkpointPageSequence + 1) ||
-				   tags.sequenceNumber != YAFFS_SEQUENCE_CHECKPOINT_DATA)
-				   ok = 0;
+			if (tags.chunk_id != (dev->checkpt_page_seq + 1) ||
+			    tags.ecc_result > YAFFS_ECC_RESULT_FIXED ||
+			    tags.seq_number != YAFFS_SEQUENCE_CHECKPOINT_DATA) {
+				ok = 0;
+				break;
+			}
 
-				dev->checkpointByteOffset = 0;
-				dev->checkpointPageSequence++;
-				dev->checkpointCurrentChunk++;
+			dev->checkpt_byte_offs = 0;
+			dev->checkpt_page_seq++;
+			dev->checkpt_cur_chunk++;
 
-				if(dev->checkpointCurrentChunk >= dev->nChunksPerBlock)
-					dev->checkpointCurrentBlock = -1;
-			}
+			if (dev->checkpt_cur_chunk >=
+					dev->param.chunks_per_block)
+				dev->checkpt_cur_block = -1;
 		}
 
-		if(ok){
-			*dataBytes = dev->checkpointBuffer[dev->checkpointByteOffset];
-			dev->checkpointSum += *dataBytes;
-			dev->checkpointXor ^= *dataBytes;
-			dev->checkpointByteOffset++;
-			i++;
-			dataBytes++;
-			dev->checkpointByteCount++;
-		}
+		*data_bytes = dev->checkpt_buffer[dev->checkpt_byte_offs];
+		dev->checkpt_sum += *data_bytes;
+		dev->checkpt_xor ^= *data_bytes;
+		dev->checkpt_byte_offs++;
+		i++;
+		data_bytes++;
+		dev->checkpt_byte_count++;
 	}
 
-	return 	i;
+	return i;
 }
 
-int yaffs_CheckpointClose(yaffs_Device *dev)
+int yaffs_checkpt_close(struct yaffs_dev *dev)
 {
+	int i;
 
-	if(dev->checkpointOpenForWrite){
-		if(dev->checkpointByteOffset != 0)
-			yaffs_CheckpointFlushBuffer(dev);
-	} else {
-		int i;
-		for(i = 0; i < dev->blocksInCheckpoint && dev->checkpointBlockList[i] >= 0; i++){
-			yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev,dev->checkpointBlockList[i]);
-			if(bi->blockState == YAFFS_BLOCK_STATE_EMPTY)
-				bi->blockState = YAFFS_BLOCK_STATE_CHECKPOINT;
-			else {
-				// Todo this looks odd...
-			}
+	if (dev->checkpt_open_write) {
+		if (dev->checkpt_byte_offs != 0)
+			yaffs2_checkpt_flush_buffer(dev);
+	} else if (dev->checkpt_block_list) {
+		for (i = 0;
+		     i < dev->blocks_in_checkpt &&
+		     dev->checkpt_block_list[i] >= 0; i++) {
+			int blk = dev->checkpt_block_list[i];
+			struct yaffs_block_info *bi = NULL;
+
+			if (dev->internal_start_block <= blk &&
+			    blk <= dev->internal_end_block)
+				bi = yaffs_get_block_info(dev, blk);
+			if (bi && bi->block_state == YAFFS_BLOCK_STATE_EMPTY)
+				bi->block_state = YAFFS_BLOCK_STATE_CHECKPOINT;
 		}
-		YFREE(dev->checkpointBlockList);
-		dev->checkpointBlockList = NULL;
+		kfree(dev->checkpt_block_list);
+		dev->checkpt_block_list = NULL;
 	}
 
-	dev->nFreeChunks -= dev->blocksInCheckpoint * dev->nChunksPerBlock;
-	dev->nErasedBlocks -= dev->blocksInCheckpoint;
+	dev->n_free_chunks -=
+		dev->blocks_in_checkpt * dev->param.chunks_per_block;
+	dev->n_erased_blocks -= dev->blocks_in_checkpt;
 
+	yaffs_trace(YAFFS_TRACE_CHECKPOINT, "checkpoint byte count %d",
+		dev->checkpt_byte_count);
 
-	T(YAFFS_TRACE_CHECKPOINT,(TSTR("checkpoint byte count %d" TENDSTR),
-			dev->checkpointByteCount));
-
-	if(dev->checkpointBuffer){
+	if (dev->checkpt_buffer) {
 		/* free the buffer */
-		YFREE(dev->checkpointBuffer);
-		dev->checkpointBuffer = NULL;
+		kfree(dev->checkpt_buffer);
+		dev->checkpt_buffer = NULL;
 		return 1;
-	}
-	else
+	} else {
 		return 0;
-
+	}
 }
 
-int yaffs_CheckpointInvalidateStream(yaffs_Device *dev)
+int yaffs2_checkpt_invalidate_stream(struct yaffs_dev *dev)
 {
-	/* Erase the first checksum block */
-
-	T(YAFFS_TRACE_CHECKPOINT,(TSTR("checkpoint invalidate"TENDSTR)));
+	/* Erase the checkpoint data */
 
-	if(!yaffs_CheckpointSpaceOk(dev))
-		return 0;
+	yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+		"checkpoint invalidate of %d blocks",
+		dev->blocks_in_checkpt);
 
-	return yaffs_CheckpointErase(dev);
+	return yaffs_checkpt_erase(dev);
 }
diff --git a/fs/yaffs2/yaffs_checkptrw.h b/fs/yaffs2/yaffs_checkptrw.h
index e59d151a27..cdbaba7153 100644
--- a/fs/yaffs2/yaffs_checkptrw.h
+++ b/fs/yaffs2/yaffs_checkptrw.h
@@ -1,7 +1,7 @@
 /*
  * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
  *
- * Copyright (C) 2002-2007 Aleph One Ltd.
+ * Copyright (C) 2002-2011 Aleph One Ltd.
  *   for Toby Churchill Ltd and Brightstar Engineering
  *
  * Created by Charles Manning <charles@aleph1.co.uk>
@@ -18,17 +18,16 @@
 
 #include "yaffs_guts.h"
 
-int yaffs_CheckpointOpen(yaffs_Device *dev, int forWriting);
+int yaffs2_checkpt_open(struct yaffs_dev *dev, int writing);
 
-int yaffs_CheckpointWrite(yaffs_Device *dev,const void *data, int nBytes);
+int yaffs2_checkpt_wr(struct yaffs_dev *dev, const void *data, int n_bytes);
 
-int yaffs_CheckpointRead(yaffs_Device *dev,void *data, int nBytes);
+int yaffs2_checkpt_rd(struct yaffs_dev *dev, void *data, int n_bytes);
 
-int yaffs_GetCheckpointSum(yaffs_Device *dev, __u32 *sum);
+int yaffs2_get_checkpt_sum(struct yaffs_dev *dev, u32 * sum);
 
-int yaffs_CheckpointClose(yaffs_Device *dev);
-
-int yaffs_CheckpointInvalidateStream(yaffs_Device *dev);
+int yaffs_checkpt_close(struct yaffs_dev *dev);
 
+int yaffs2_checkpt_invalidate_stream(struct yaffs_dev *dev);
 
 #endif
diff --git a/fs/yaffs2/yaffs_ecc.c b/fs/yaffs2/yaffs_ecc.c
index 1b4a05d71b..9294107c15 100644
--- a/fs/yaffs2/yaffs_ecc.c
+++ b/fs/yaffs2/yaffs_ecc.c
@@ -1,7 +1,7 @@
 /*
  * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
  *
- * Copyright (C) 2002-2007 Aleph One Ltd.
+ * Copyright (C) 2002-2011 Aleph One Ltd.
  *   for Toby Churchill Ltd and Brightstar Engineering
  *
  * Created by Charles Manning <charles@aleph1.co.uk>
@@ -16,28 +16,22 @@
  *
  * The ECC comprises 22 bits of parity information and is stuffed into 3 bytes.
  * The two unused bit are set to 1.
- * The ECC can correct single bit errors in a 256-byte page of data. Thus, two such ECC
- * blocks are used on a 512-byte NAND page.
+ * The ECC can correct single bit errors in a 256-byte page of data. Thus, two
+ * such ECC blocks are used on a 512-byte NAND page.
  *
  */
 
+#include "yportenv.h"
+
+#include "yaffs_ecc.h"
+
 /* Table generated by gen-ecc.c
  * Using a table means we do not have to calculate p1..p4 and p1'..p4'
  * for each byte of data. These are instead provided in a table in bits7..2.
- * Bit 0 of each entry indicates whether the entry has an odd or even parity, and therefore
- * this bytes influence on the line parity.
+ * Bit 0 of each entry indicates whether the entry has an odd or even parity,
+ * and therefore this bytes influence on the line parity.
  */
 
-/* XXX U-BOOT XXX */
-#include <common.h>
-
-const char *yaffs_ecc_c_version =
-    "$Id: yaffs_ecc.c,v 1.9 2007/02/14 01:09:06 wookey Exp $";
-
-#include "yportenv.h"
-
-#include "yaffs_ecc.h"
-
 static const unsigned char column_parity_table[] = {
 	0x00, 0x55, 0x59, 0x0c, 0x65, 0x30, 0x3c, 0x69,
 	0x69, 0x3c, 0x30, 0x65, 0x0c, 0x59, 0x55, 0x00,
@@ -73,35 +67,11 @@ static const unsigned char column_parity_table[] = {
 	0x69, 0x3c, 0x30, 0x65, 0x0c, 0x59, 0x55, 0x00,
 };
 
-/* Count the bits in an unsigned char or a U32 */
-
-static int yaffs_CountBits(unsigned char x)
-{
-	int r = 0;
-	while (x) {
-		if (x & 1)
-			r++;
-		x >>= 1;
-	}
-	return r;
-}
-
-static int yaffs_CountBits32(unsigned x)
-{
-	int r = 0;
-	while (x) {
-		if (x & 1)
-			r++;
-		x >>= 1;
-	}
-	return r;
-}
 
 /* Calculate the ECC for a 256-byte block of data */
-void yaffs_ECCCalculate(const unsigned char *data, unsigned char *ecc)
+void yaffs_ecc_calc(const unsigned char *data, unsigned char *ecc)
 {
 	unsigned int i;
-
 	unsigned char col_parity = 0;
 	unsigned char line_parity = 0;
 	unsigned char line_parity_prime = 0;
@@ -112,12 +82,10 @@ void yaffs_ECCCalculate(const unsigned char *data, unsigned char *ecc)
 		b = column_parity_table[*data++];
 		col_parity ^= b;
 
-		if (b & 0x01)	// odd number of bits in the byte
-		{
+		if (b & 0x01) {	/* odd number of bits in the byte */
 			line_parity ^= i;
 			line_parity_prime ^= ~i;
 		}
-
 	}
 
 	ecc[2] = (~col_parity) | 0x03;
@@ -160,19 +128,12 @@ void yaffs_ECCCalculate(const unsigned char *data, unsigned char *ecc)
 		t |= 0x01;
 	ecc[0] = ~t;
 
-#ifdef CONFIG_YAFFS_ECC_WRONG_ORDER
-	// Swap the bytes into the wrong order
-	t = ecc[0];
-	ecc[0] = ecc[1];
-	ecc[1] = t;
-#endif
 }
 
-
 /* Correct the ECC on a 256 byte block of data */
 
-int yaffs_ECCCorrect(unsigned char *data, unsigned char *read_ecc,
-		     const unsigned char *test_ecc)
+int yaffs_ecc_correct(unsigned char *data, unsigned char *read_ecc,
+		      const unsigned char *test_ecc)
 {
 	unsigned char d0, d1, d2;	/* deltas */
 
@@ -181,7 +142,7 @@ int yaffs_ECCCorrect(unsigned char *data, unsigned char *read_ecc,
 	d2 = read_ecc[2] ^ test_ecc[2];
 
 	if ((d0 | d1 | d2) == 0)
-		return 0; /* no error */
+		return 0;	/* no error */
 
 	if (((d0 ^ (d0 >> 1)) & 0x55) == 0x55 &&
 	    ((d1 ^ (d1 >> 1)) & 0x55) == 0x55 &&
@@ -191,15 +152,6 @@ int yaffs_ECCCorrect(unsigned char *data, unsigned char *read_ecc,
 		unsigned byte;
 		unsigned bit;
 
-#ifdef CONFIG_YAFFS_ECC_WRONG_ORDER
-		// swap the bytes to correct for the wrong order
-		unsigned char t;
-
-		t = d0;
-		d0 = d1;
-		d1 = t;
-#endif
-
 		bit = byte = 0;
 
 		if (d1 & 0x80)
@@ -228,19 +180,17 @@ int yaffs_ECCCorrect(unsigned char *data, unsigned char *read_ecc,
 
 		data[byte] ^= (1 << bit);
 
-		return 1; /* Corrected the error */
+		return 1;	/* Corrected the error */
 	}
 
-	if ((yaffs_CountBits(d0) +
-	     yaffs_CountBits(d1) +
-	     yaffs_CountBits(d2)) ==  1) {
+	if ((hweight8(d0) + hweight8(d1) + hweight8(d2)) == 1) {
 		/* Reccoverable error in ecc */
 
 		read_ecc[0] = test_ecc[0];
 		read_ecc[1] = test_ecc[1];
 		read_ecc[2] = test_ecc[2];
 
-		return 1; /* Corrected the error */
+		return 1;	/* Corrected the error */
 	}
 
 	/* Unrecoverable error */
@@ -249,25 +199,23 @@ int yaffs_ECCCorrect(unsigned char *data, unsigned char *read_ecc,
 
 }
 
-
 /*
  * ECCxxxOther does ECC calcs on arbitrary n bytes of data
  */
-void yaffs_ECCCalculateOther(const unsigned char *data, unsigned nBytes,
-			     yaffs_ECCOther * eccOther)
+void yaffs_ecc_calc_other(const unsigned char *data, unsigned n_bytes,
+			  struct yaffs_ecc_other *ecc_other)
 {
 	unsigned int i;
-
 	unsigned char col_parity = 0;
 	unsigned line_parity = 0;
 	unsigned line_parity_prime = 0;
 	unsigned char b;
 
-	for (i = 0; i < nBytes; i++) {
+	for (i = 0; i < n_bytes; i++) {
 		b = column_parity_table[*data++];
 		col_parity ^= b;
 
-		if (b & 0x01)	 {
+		if (b & 0x01) {
 			/* odd number of bits in the byte */
 			line_parity ^= i;
 			line_parity_prime ^= ~i;
@@ -275,59 +223,59 @@ void yaffs_ECCCalculateOther(const unsigned char *data, unsigned nBytes,
 
 	}
 
-	eccOther->colParity = (col_parity >> 2) & 0x3f;
-	eccOther->lineParity = line_parity;
-	eccOther->lineParityPrime = line_parity_prime;
+	ecc_other->col_parity = (col_parity >> 2) & 0x3f;
+	ecc_other->line_parity = line_parity;
+	ecc_other->line_parity_prime = line_parity_prime;
 }
 
-int yaffs_ECCCorrectOther(unsigned char *data, unsigned nBytes,
-			  yaffs_ECCOther * read_ecc,
-			  const yaffs_ECCOther * test_ecc)
+int yaffs_ecc_correct_other(unsigned char *data, unsigned n_bytes,
+			    struct yaffs_ecc_other *read_ecc,
+			    const struct yaffs_ecc_other *test_ecc)
 {
-	unsigned char cDelta;	/* column parity delta */
-	unsigned lDelta;	/* line parity delta */
-	unsigned lDeltaPrime;	/* line parity delta */
+	unsigned char delta_col;	/* column parity delta */
+	unsigned delta_line;	/* line parity delta */
+	unsigned delta_line_prime;	/* line parity delta */
 	unsigned bit;
 
-	cDelta = read_ecc->colParity ^ test_ecc->colParity;
-	lDelta = read_ecc->lineParity ^ test_ecc->lineParity;
-	lDeltaPrime = read_ecc->lineParityPrime ^ test_ecc->lineParityPrime;
+	delta_col = read_ecc->col_parity ^ test_ecc->col_parity;
+	delta_line = read_ecc->line_parity ^ test_ecc->line_parity;
+	delta_line_prime =
+	    read_ecc->line_parity_prime ^ test_ecc->line_parity_prime;
 
-	if ((cDelta | lDelta | lDeltaPrime) == 0)
-		return 0; /* no error */
+	if ((delta_col | delta_line | delta_line_prime) == 0)
+		return 0;	/* no error */
 
-	if (lDelta == ~lDeltaPrime &&
-	    (((cDelta ^ (cDelta >> 1)) & 0x15) == 0x15))
-	{
+	if (delta_line == ~delta_line_prime &&
+	    (((delta_col ^ (delta_col >> 1)) & 0x15) == 0x15)) {
 		/* Single bit (recoverable) error in data */
 
 		bit = 0;
 
-		if (cDelta & 0x20)
+		if (delta_col & 0x20)
 			bit |= 0x04;
-		if (cDelta & 0x08)
+		if (delta_col & 0x08)
 			bit |= 0x02;
-		if (cDelta & 0x02)
+		if (delta_col & 0x02)
 			bit |= 0x01;
 
-		if(lDelta >= nBytes)
+		if (delta_line >= n_bytes)
 			return -1;
 
-		data[lDelta] ^= (1 << bit);
+		data[delta_line] ^= (1 << bit);
 
-		return 1; /* corrected */
+		return 1;	/* corrected */
 	}
 
-	if ((yaffs_CountBits32(lDelta) + yaffs_CountBits32(lDeltaPrime) +
-	     yaffs_CountBits(cDelta)) == 1) {
+	if ((hweight32(delta_line) +
+	     hweight32(delta_line_prime) +
+	     hweight8(delta_col)) == 1) {
 		/* Reccoverable error in ecc */
 
 		*read_ecc = *test_ecc;
-		return 1; /* corrected */
+		return 1;	/* corrected */
 	}
 
 	/* Unrecoverable error */
 
 	return -1;
-
 }
diff --git a/fs/yaffs2/yaffs_ecc.h b/fs/yaffs2/yaffs_ecc.h
index 79bc3d1171..17d47bd80f 100644
--- a/fs/yaffs2/yaffs_ecc.h
+++ b/fs/yaffs2/yaffs_ecc.h
@@ -1,7 +1,7 @@
 /*
  * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
  *
- * Copyright (C) 2002-2007 Aleph One Ltd.
+ * Copyright (C) 2002-2011 Aleph One Ltd.
  *   for Toby Churchill Ltd and Brightstar Engineering
  *
  * Created by Charles Manning <charles@aleph1.co.uk>
@@ -13,32 +13,32 @@
  * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
  */
 
- /*
-  * This code implements the ECC algorithm used in SmartMedia.
-  *
-  * The ECC comprises 22 bits of parity information and is stuffed into 3 bytes.
-  * The two unused bit are set to 1.
-  * The ECC can correct single bit errors in a 256-byte page of data. Thus, two such ECC
-  * blocks are used on a 512-byte NAND page.
-  *
-  */
+/*
+ * This code implements the ECC algorithm used in SmartMedia.
+ *
+ * The ECC comprises 22 bits of parity information and is stuffed into 3 bytes.
+ * The two unused bit are set to 1.
+ * The ECC can correct single bit errors in a 256-byte page of data.
+ * Thus, two such ECC blocks are used on a 512-byte NAND page.
+ *
+ */
 
 #ifndef __YAFFS_ECC_H__
 #define __YAFFS_ECC_H__
 
-typedef struct {
-	unsigned char colParity;
-	unsigned lineParity;
-	unsigned lineParityPrime;
-} yaffs_ECCOther;
+struct yaffs_ecc_other {
+	unsigned char col_parity;
+	unsigned line_parity;
+	unsigned line_parity_prime;
+};
 
-void yaffs_ECCCalculate(const unsigned char *data, unsigned char *ecc);
-int yaffs_ECCCorrect(unsigned char *data, unsigned char *read_ecc,
-		     const unsigned char *test_ecc);
+void yaffs_ecc_calc(const unsigned char *data, unsigned char *ecc);
+int yaffs_ecc_correct(unsigned char *data, unsigned char *read_ecc,
+		      const unsigned char *test_ecc);
 
-void yaffs_ECCCalculateOther(const unsigned char *data, unsigned nBytes,
-			     yaffs_ECCOther * ecc);
-int yaffs_ECCCorrectOther(unsigned char *data, unsigned nBytes,
-			  yaffs_ECCOther * read_ecc,
-			  const yaffs_ECCOther * test_ecc);
+void yaffs_ecc_calc_other(const unsigned char *data, unsigned n_bytes,
+			  struct yaffs_ecc_other *ecc);
+int yaffs_ecc_correct_other(unsigned char *data, unsigned n_bytes,
+			    struct yaffs_ecc_other *read_ecc,
+			    const struct yaffs_ecc_other *test_ecc);
 #endif
diff --git a/fs/yaffs2/yaffs_error.c b/fs/yaffs2/yaffs_error.c
new file mode 100644
index 0000000000..11b75f7a0b
--- /dev/null
+++ b/fs/yaffs2/yaffs_error.c
@@ -0,0 +1,58 @@
+/*
+ * YAFFS: Yet another FFS. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2011 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Timothy Manning <timothy@yaffs.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "yaffsfs.h"
+
+struct error_entry {
+	int code;
+	const char *text;
+};
+
+static const struct error_entry error_list[] = {
+	{ ENOMEM , "ENOMEM" },
+	{ EBUSY , "EBUSY"},
+	{ ENODEV , "ENODEV"},
+	{ EINVAL , "EINVAL"},
+	{ EBADF , "EBADF"},
+	{ EACCES , "EACCES"},
+	{ EXDEV , "EXDEV" },
+	{ ENOENT , "ENOENT"},
+	{ ENOSPC , "ENOSPC"},
+	{ ERANGE , "ERANGE"},
+	{ ENODATA, "ENODATA"},
+	{ ENOTEMPTY, "ENOTEMPTY"},
+	{ ENAMETOOLONG, "ENAMETOOLONG"},
+	{ ENOMEM , "ENOMEM"},
+	{ EEXIST , "EEXIST"},
+	{ ENOTDIR , "ENOTDIR"},
+	{ EISDIR , "EISDIR"},
+	{ ENFILE, "ENFILE"},
+	{ EROFS, "EROFS"},
+	{ EFAULT, "EFAULT"},
+	{ 0, NULL }
+};
+
+const char *yaffs_error_to_str(int err)
+{
+	const struct error_entry *e = error_list;
+
+	if (err < 0)
+		err = -err;
+
+	while (e->code && e->text) {
+		if (err == e->code)
+			return e->text;
+		e++;
+	}
+	return "Unknown error code";
+}
diff --git a/fs/yaffs2/yaffs_flashif.h b/fs/yaffs2/yaffs_flashif.h
index 4e5157e252..e6e8979ee6 100644
--- a/fs/yaffs2/yaffs_flashif.h
+++ b/fs/yaffs2/yaffs_flashif.h
@@ -1,7 +1,7 @@
 /*
  * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
  *
- * Copyright (C) 2002-2007 Aleph One Ltd.
+ * Copyright (C) 2002-2011 Aleph One Ltd.
  *   for Toby Churchill Ltd and Brightstar Engineering
  *
  * Created by Charles Manning <charles@aleph1.co.uk>
@@ -18,14 +18,18 @@
 
 
 #include "yaffs_guts.h"
-int yflash_EraseBlockInNAND(yaffs_Device *dev, int blockNumber);
-int yflash_WriteChunkToNAND(yaffs_Device *dev,int chunkInNAND,const __u8 *data, const yaffs_Spare *spare);
-int yflash_WriteChunkWithTagsToNAND(yaffs_Device *dev,int chunkInNAND,const __u8 *data, yaffs_ExtendedTags *tags);
-int yflash_ReadChunkFromNAND(yaffs_Device *dev,int chunkInNAND, __u8 *data, yaffs_Spare *spare);
-int yflash_ReadChunkWithTagsFromNAND(yaffs_Device *dev,int chunkInNAND, __u8 *data, yaffs_ExtendedTags *tags);
-int yflash_EraseBlockInNAND(yaffs_Device *dev, int blockNumber);
-int yflash_InitialiseNAND(yaffs_Device *dev);
-int yflash_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo);
-int yflash_QueryNANDBlock(struct yaffs_DeviceStruct *dev, int blockNo, yaffs_BlockState *state, int *sequenceNumber);
+int yflash_EraseBlockInNAND(struct yaffs_dev *dev, int blockNumber);
+int yflash_WriteChunkToNAND(struct yaffs_dev *dev, int nand_chunk,
+			const u8 *data, const struct yaffs_spare *spare);
+int yflash_WriteChunkWithTagsToNAND(struct yaffs_dev *dev, int nand_chunk,
+			const u8 *data, const struct yaffs_ext_tags *tags);
+int yflash_ReadChunkFromNAND(struct yaffs_dev *dev, int nand_chunk,
+			u8 *data, struct yaffs_spare *spare);
+int yflash_ReadChunkWithTagsFromNAND(struct yaffs_dev *dev, int nand_chunk,
+			u8 *data, struct yaffs_ext_tags *tags);
+int yflash_InitialiseNAND(struct yaffs_dev *dev);
+int yflash_MarkNANDBlockBad(struct yaffs_dev *dev, int block_no);
+int yflash_QueryNANDBlock(struct yaffs_dev *dev, int block_no,
+			enum yaffs_block_state *state, u32 *seq_number);
 
 #endif
diff --git a/fs/yaffs2/yaffs_flashif2.h b/fs/yaffs2/yaffs_flashif2.h
new file mode 100644
index 0000000000..cfdbde9dc8
--- /dev/null
+++ b/fs/yaffs2/yaffs_flashif2.h
@@ -0,0 +1,35 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2011 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_FLASH2_H__
+#define __YAFFS_FLASH2_H__
+
+
+#include "yaffs_guts.h"
+int yflash2_EraseBlockInNAND(struct yaffs_dev *dev, int blockNumber);
+int yflash2_WriteChunkToNAND(struct yaffs_dev *dev, int nand_chunk,
+			const u8 *data, const struct yaffs_spare *spare);
+int yflash2_WriteChunkWithTagsToNAND(struct yaffs_dev *dev, int nand_chunk,
+			const u8 *data, const struct yaffs_ext_tags *tags);
+int yflash2_ReadChunkFromNAND(struct yaffs_dev *dev, int nand_chunk,
+			u8 *data, struct yaffs_spare *spare);
+int yflash2_ReadChunkWithTagsFromNAND(struct yaffs_dev *dev, int nand_chunk,
+			u8 *data, struct yaffs_ext_tags *tags);
+int yflash2_InitialiseNAND(struct yaffs_dev *dev);
+int yflash2_MarkNANDBlockBad(struct yaffs_dev *dev, int block_no);
+int yflash2_QueryNANDBlock(struct yaffs_dev *dev, int block_no,
+			enum yaffs_block_state *state, u32 *seq_number);
+
+#endif
diff --git a/fs/yaffs2/yaffs_getblockinfo.h b/fs/yaffs2/yaffs_getblockinfo.h
new file mode 100644
index 0000000000..8fd0802bdd
--- /dev/null
+++ b/fs/yaffs2/yaffs_getblockinfo.h
@@ -0,0 +1,35 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2011 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_GETBLOCKINFO_H__
+#define __YAFFS_GETBLOCKINFO_H__
+
+#include "yaffs_guts.h"
+#include "yaffs_trace.h"
+
+/* Function to manipulate block info */
+static inline struct yaffs_block_info *yaffs_get_block_info(struct yaffs_dev
+							      *dev, int blk)
+{
+	if (blk < dev->internal_start_block || blk > dev->internal_end_block) {
+		yaffs_trace(YAFFS_TRACE_ERROR,
+			"**>> yaffs: get_block_info block %d is not valid",
+			blk);
+		BUG();
+	}
+	return &dev->block_info[blk - dev->internal_start_block];
+}
+
+#endif
diff --git a/fs/yaffs2/yaffs_guts.c b/fs/yaffs2/yaffs_guts.c
index 7390b40e01..21441fd991 100644
--- a/fs/yaffs2/yaffs_guts.c
+++ b/fs/yaffs2/yaffs_guts.c
@@ -1,7 +1,7 @@
 /*
  * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
  *
- * Copyright (C) 2002-2007 Aleph One Ltd.
+ * Copyright (C) 2002-2011 Aleph One Ltd.
  *   for Toby Churchill Ltd and Brightstar Engineering
  *
  * Created by Charles Manning <charles@aleph1.co.uk>
@@ -11,259 +11,176 @@
  * published by the Free Software Foundation.
  */
 
-/* XXX U-BOOT XXX */
-#include <common.h>
-
-const char *yaffs_guts_c_version =
-    "$Id: yaffs_guts.c,v 1.52 2007/10/16 00:45:05 charles Exp $";
-
 #include "yportenv.h"
-#include "linux/stat.h"
+#include "yaffs_trace.h"
 
-#include "yaffsinterface.h"
-#include "yaffsfs.h"
 #include "yaffs_guts.h"
-#include "yaffs_tagsvalidity.h"
-
+#include "yaffs_getblockinfo.h"
 #include "yaffs_tagscompat.h"
-#ifndef  CONFIG_YAFFS_USE_OWN_SORT
-#include "yaffs_qsort.h"
-#endif
 #include "yaffs_nand.h"
-
-#include "yaffs_checkptrw.h"
-
+#include "yaffs_yaffs1.h"
+#include "yaffs_yaffs2.h"
+#include "yaffs_bitmap.h"
+#include "yaffs_verify.h"
 #include "yaffs_nand.h"
 #include "yaffs_packedtags2.h"
+#include "yaffs_nameval.h"
+#include "yaffs_allocator.h"
+#include "yaffs_attribs.h"
+#include "yaffs_summary.h"
 
-#include "malloc.h"
-
-#ifdef CONFIG_YAFFS_WINCE
-void yfsd_LockYAFFS(BOOL fsLockOnly);
-void yfsd_UnlockYAFFS(BOOL fsLockOnly);
-#endif
-
-#define YAFFS_PASSIVE_GC_CHUNKS 2
+/* Note YAFFS_GC_GOOD_ENOUGH must be <= YAFFS_GC_PASSIVE_THRESHOLD */
+#define YAFFS_GC_GOOD_ENOUGH 2
+#define YAFFS_GC_PASSIVE_THRESHOLD 4
 
 #include "yaffs_ecc.h"
 
+/* Forward declarations */
 
-/* Robustification (if it ever comes about...) */
-static void yaffs_RetireBlock(yaffs_Device * dev, int blockInNAND);
-static void yaffs_HandleWriteChunkError(yaffs_Device * dev, int chunkInNAND, int erasedOk);
-static void yaffs_HandleWriteChunkOk(yaffs_Device * dev, int chunkInNAND,
-				     const __u8 * data,
-				     const yaffs_ExtendedTags * tags);
-static void yaffs_HandleUpdateChunk(yaffs_Device * dev, int chunkInNAND,
-				    const yaffs_ExtendedTags * tags);
-
-/* Other local prototypes */
-static int yaffs_UnlinkObject( yaffs_Object *obj);
-static int yaffs_ObjectHasCachedWriteData(yaffs_Object *obj);
-
-static void yaffs_HardlinkFixup(yaffs_Device *dev, yaffs_Object *hardList);
-
-static int yaffs_WriteNewChunkWithTagsToNAND(yaffs_Device * dev,
-					     const __u8 * buffer,
-					     yaffs_ExtendedTags * tags,
-					     int useReserve);
-static int yaffs_PutChunkIntoFile(yaffs_Object * in, int chunkInInode,
-				  int chunkInNAND, int inScan);
-
-static yaffs_Object *yaffs_CreateNewObject(yaffs_Device * dev, int number,
-					   yaffs_ObjectType type);
-static void yaffs_AddObjectToDirectory(yaffs_Object * directory,
-				       yaffs_Object * obj);
-static int yaffs_UpdateObjectHeader(yaffs_Object * in, const YCHAR * name,
-				    int force, int isShrink, int shadows);
-static void yaffs_RemoveObjectFromDirectory(yaffs_Object * obj);
-static int yaffs_CheckStructures(void);
-static int yaffs_DoGenericObjectDeletion(yaffs_Object * in);
-
-static yaffs_BlockInfo *yaffs_GetBlockInfo(yaffs_Device * dev, int blockNo);
-
-static __u8 *yaffs_GetTempBuffer(yaffs_Device * dev, int lineNo);
-static void yaffs_ReleaseTempBuffer(yaffs_Device * dev, __u8 * buffer,
-				    int lineNo);
-
-static int yaffs_CheckChunkErased(struct yaffs_DeviceStruct *dev,
-				  int chunkInNAND);
-
-static int yaffs_UnlinkWorker(yaffs_Object * obj);
-static void yaffs_DestroyObject(yaffs_Object * obj);
-
-static int yaffs_TagsMatch(const yaffs_ExtendedTags * tags, int objectId,
-			   int chunkInObject);
+static int yaffs_wr_data_obj(struct yaffs_obj *in, int inode_chunk,
+			     const u8 *buffer, int n_bytes, int use_reserve);
 
-loff_t yaffs_GetFileSize(yaffs_Object * obj);
 
-static int yaffs_AllocateChunk(yaffs_Device * dev, int useReserve, yaffs_BlockInfo **blockUsedPtr);
 
-static void yaffs_VerifyFreeChunks(yaffs_Device * dev);
-
-static void yaffs_CheckObjectDetailsLoaded(yaffs_Object *in);
-
-#ifdef YAFFS_PARANOID
-static int yaffs_CheckFileSanity(yaffs_Object * in);
-#else
-#define yaffs_CheckFileSanity(in)
-#endif
+/* Function to calculate chunk and offset */
 
-static void yaffs_InvalidateWholeChunkCache(yaffs_Object * in);
-static void yaffs_InvalidateChunkCache(yaffs_Object * object, int chunkId);
+void yaffs_addr_to_chunk(struct yaffs_dev *dev, loff_t addr,
+				int *chunk_out, u32 *offset_out)
+{
+	int chunk;
+	u32 offset;
 
-static void yaffs_InvalidateCheckpoint(yaffs_Device *dev);
+	chunk = (u32) (addr >> dev->chunk_shift);
 
-static int yaffs_FindChunkInFile(yaffs_Object * in, int chunkInInode,
-				 yaffs_ExtendedTags * tags);
+	if (dev->chunk_div == 1) {
+		/* easy power of 2 case */
+		offset = (u32) (addr & dev->chunk_mask);
+	} else {
+		/* Non power-of-2 case */
 
-static __u32 yaffs_GetChunkGroupBase(yaffs_Device *dev, yaffs_Tnode *tn, unsigned pos);
-static yaffs_Tnode *yaffs_FindLevel0Tnode(yaffs_Device * dev,
-					  yaffs_FileStructure * fStruct,
-					  __u32 chunkId);
+		loff_t chunk_base;
 
+		chunk /= dev->chunk_div;
 
-/* Function to calculate chunk and offset */
-
-static void yaffs_AddrToChunk(yaffs_Device *dev, loff_t addr, __u32 *chunk, __u32 *offset)
-{
-	if(dev->chunkShift){
-		/* Easy-peasy power of 2 case */
-		*chunk  = (__u32)(addr >> dev->chunkShift);
-		*offset = (__u32)(addr & dev->chunkMask);
-	}
-	else if(dev->crumbsPerChunk)
-	{
-		/* Case where we're using "crumbs" */
-		*offset = (__u32)(addr & dev->crumbMask);
-		addr >>= dev->crumbShift;
-		*chunk = ((__u32)addr)/dev->crumbsPerChunk;
-		*offset += ((addr - (*chunk * dev->crumbsPerChunk)) << dev->crumbShift);
+		chunk_base = ((loff_t) chunk) * dev->data_bytes_per_chunk;
+		offset = (u32) (addr - chunk_base);
 	}
-	else
-		YBUG();
+
+	*chunk_out = chunk;
+	*offset_out = offset;
 }
 
-/* Function to return the number of shifts for a power of 2 greater than or equal
- * to the given number
+/* Function to return the number of shifts for a power of 2 greater than or
+ * equal to the given number
  * Note we don't try to cater for all possible numbers and this does not have to
  * be hellishly efficient.
  */
 
-static __u32 ShiftsGE(__u32 x)
+static inline u32 calc_shifts_ceiling(u32 x)
 {
-	int extraBits;
-	int nShifts;
+	int extra_bits;
+	int shifts;
 
-	nShifts = extraBits = 0;
+	shifts = extra_bits = 0;
 
-	while(x>1){
-		if(x & 1) extraBits++;
-		x>>=1;
-		nShifts++;
+	while (x > 1) {
+		if (x & 1)
+			extra_bits++;
+		x >>= 1;
+		shifts++;
 	}
 
-	if(extraBits)
-		nShifts++;
+	if (extra_bits)
+		shifts++;
 
-	return nShifts;
+	return shifts;
 }
 
 /* Function to return the number of shifts to get a 1 in bit 0
  */
 
-static __u32 ShiftDiv(__u32 x)
+static inline u32 calc_shifts(u32 x)
 {
-	int nShifts;
+	u32 shifts;
 
-	nShifts =  0;
+	shifts = 0;
 
-	if(!x) return 0;
+	if (!x)
+		return 0;
 
-	while( !(x&1)){
-		x>>=1;
-		nShifts++;
+	while (!(x & 1)) {
+		x >>= 1;
+		shifts++;
 	}
 
-	return nShifts;
+	return shifts;
 }
 
-
-
 /*
  * Temporary buffer manipulations.
  */
 
-static int yaffs_InitialiseTempBuffers(yaffs_Device *dev)
+static int yaffs_init_tmp_buffers(struct yaffs_dev *dev)
 {
 	int i;
-	__u8 *buf = (__u8 *)1;
+	u8 *buf = (u8 *) 1;
 
-	memset(dev->tempBuffer,0,sizeof(dev->tempBuffer));
+	memset(dev->temp_buffer, 0, sizeof(dev->temp_buffer));
 
 	for (i = 0; buf && i < YAFFS_N_TEMP_BUFFERS; i++) {
-		dev->tempBuffer[i].line = 0;	/* not in use */
-		dev->tempBuffer[i].buffer = buf =
-		    YMALLOC_DMA(dev->nDataBytesPerChunk);
+		dev->temp_buffer[i].in_use = 0;
+		buf = kmalloc(dev->param.total_bytes_per_chunk, GFP_NOFS);
+		dev->temp_buffer[i].buffer = buf;
 	}
 
 	return buf ? YAFFS_OK : YAFFS_FAIL;
-
 }
 
-static __u8 *yaffs_GetTempBuffer(yaffs_Device * dev, int lineNo)
+u8 *yaffs_get_temp_buffer(struct yaffs_dev * dev)
 {
-	int i, j;
-	for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) {
-		if (dev->tempBuffer[i].line == 0) {
-			dev->tempBuffer[i].line = lineNo;
-			if ((i + 1) > dev->maxTemp) {
-				dev->maxTemp = i + 1;
-				for (j = 0; j <= i; j++)
-					dev->tempBuffer[j].maxLine =
-					    dev->tempBuffer[j].line;
-			}
+	int i;
 
-			return dev->tempBuffer[i].buffer;
-		}
-	}
+	dev->temp_in_use++;
+	if (dev->temp_in_use > dev->max_temp)
+		dev->max_temp = dev->temp_in_use;
 
-	T(YAFFS_TRACE_BUFFERS,
-	  (TSTR("Out of temp buffers at line %d, other held by lines:"),
-	   lineNo));
 	for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) {
-		T(YAFFS_TRACE_BUFFERS, (TSTR(" %d "), dev->tempBuffer[i].line));
+		if (dev->temp_buffer[i].in_use == 0) {
+			dev->temp_buffer[i].in_use = 1;
+			return dev->temp_buffer[i].buffer;
+		}
 	}
-	T(YAFFS_TRACE_BUFFERS, (TSTR(" " TENDSTR)));
 
+	yaffs_trace(YAFFS_TRACE_BUFFERS, "Out of temp buffers");
 	/*
 	 * If we got here then we have to allocate an unmanaged one
 	 * This is not good.
 	 */
 
-	dev->unmanagedTempAllocations++;
-	return YMALLOC(dev->nDataBytesPerChunk);
+	dev->unmanaged_buffer_allocs++;
+	return kmalloc(dev->data_bytes_per_chunk, GFP_NOFS);
 
 }
 
-static void yaffs_ReleaseTempBuffer(yaffs_Device * dev, __u8 * buffer,
-				    int lineNo)
+void yaffs_release_temp_buffer(struct yaffs_dev *dev, u8 *buffer)
 {
 	int i;
+
+	dev->temp_in_use--;
+
 	for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) {
-		if (dev->tempBuffer[i].buffer == buffer) {
-			dev->tempBuffer[i].line = 0;
+		if (dev->temp_buffer[i].buffer == buffer) {
+			dev->temp_buffer[i].in_use = 0;
 			return;
 		}
 	}
 
 	if (buffer) {
 		/* assume it is an unmanaged one. */
-		T(YAFFS_TRACE_BUFFERS,
-		  (TSTR("Releasing unmanaged temp buffer in line %d" TENDSTR),
-		   lineNo));
-		YFREE(buffer);
-		dev->unmanagedTempDeallocations++;
+		yaffs_trace(YAFFS_TRACE_BUFFERS,
+			"Releasing unmanaged temp buffer");
+		kfree(buffer);
+		dev->unmanaged_buffer_deallocs++;
 	}
 
 }
@@ -271,621 +188,337 @@ static void yaffs_ReleaseTempBuffer(yaffs_Device * dev, __u8 * buffer,
 /*
  * Determine if we have a managed buffer.
  */
-int yaffs_IsManagedTempBuffer(yaffs_Device * dev, const __u8 * buffer)
+int yaffs_is_managed_tmp_buffer(struct yaffs_dev *dev, const u8 *buffer)
 {
 	int i;
+
 	for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) {
-		if (dev->tempBuffer[i].buffer == buffer)
+		if (dev->temp_buffer[i].buffer == buffer)
 			return 1;
-
 	}
 
-    for (i = 0; i < dev->nShortOpCaches; i++) {
-	if( dev->srCache[i].data == buffer )
-	    return 1;
-
-    }
+	for (i = 0; i < dev->param.n_caches; i++) {
+		if (dev->cache[i].data == buffer)
+			return 1;
+	}
 
-    if (buffer == dev->checkpointBuffer)
-      return 1;
+	if (buffer == dev->checkpt_buffer)
+		return 1;
 
-    T(YAFFS_TRACE_ALWAYS,
-	  (TSTR("yaffs: unmaged buffer detected.\n" TENDSTR)));
-    return 0;
+	yaffs_trace(YAFFS_TRACE_ALWAYS,
+	  "yaffs: unmaged buffer detected.");
+	return 0;
 }
 
-
-
 /*
- * Chunk bitmap manipulations
+ * Functions for robustisizing TODO
+ *
  */
 
-static Y_INLINE __u8 *yaffs_BlockBits(yaffs_Device * dev, int blk)
+static void yaffs_handle_chunk_wr_ok(struct yaffs_dev *dev, int nand_chunk,
+				     const u8 *data,
+				     const struct yaffs_ext_tags *tags)
 {
-	if (blk < dev->internalStartBlock || blk > dev->internalEndBlock) {
-		T(YAFFS_TRACE_ERROR,
-		  (TSTR("**>> yaffs: BlockBits block %d is not valid" TENDSTR),
-		   blk));
-		YBUG();
-	}
-	return dev->chunkBits +
-	    (dev->chunkBitmapStride * (blk - dev->internalStartBlock));
+	dev = dev;
+	nand_chunk = nand_chunk;
+	data = data;
+	tags = tags;
 }
 
-static Y_INLINE void yaffs_VerifyChunkBitId(yaffs_Device *dev, int blk, int chunk)
+static void yaffs_handle_chunk_update(struct yaffs_dev *dev, int nand_chunk,
+				      const struct yaffs_ext_tags *tags)
 {
-	if(blk < dev->internalStartBlock || blk > dev->internalEndBlock ||
-	   chunk < 0 || chunk >= dev->nChunksPerBlock) {
-	   T(YAFFS_TRACE_ERROR,
-	    (TSTR("**>> yaffs: Chunk Id (%d:%d) invalid"TENDSTR),blk,chunk));
-	    YBUG();
-	}
-}
-
-static Y_INLINE void yaffs_ClearChunkBits(yaffs_Device * dev, int blk)
-{
-	__u8 *blkBits = yaffs_BlockBits(dev, blk);
-
-	memset(blkBits, 0, dev->chunkBitmapStride);
+	dev = dev;
+	nand_chunk = nand_chunk;
+	tags = tags;
 }
 
-static Y_INLINE void yaffs_ClearChunkBit(yaffs_Device * dev, int blk, int chunk)
+void yaffs_handle_chunk_error(struct yaffs_dev *dev,
+			      struct yaffs_block_info *bi)
 {
-	__u8 *blkBits = yaffs_BlockBits(dev, blk);
+	if (!bi->gc_prioritise) {
+		bi->gc_prioritise = 1;
+		dev->has_pending_prioritised_gc = 1;
+		bi->chunk_error_strikes++;
 
-	yaffs_VerifyChunkBitId(dev,blk,chunk);
+		if (bi->chunk_error_strikes > 3) {
+			bi->needs_retiring = 1;	/* Too many stikes, so retire */
+			yaffs_trace(YAFFS_TRACE_ALWAYS,
+				"yaffs: Block struck out");
 
-	blkBits[chunk / 8] &= ~(1 << (chunk & 7));
-}
-
-static Y_INLINE void yaffs_SetChunkBit(yaffs_Device * dev, int blk, int chunk)
-{
-	__u8 *blkBits = yaffs_BlockBits(dev, blk);
-
-	yaffs_VerifyChunkBitId(dev,blk,chunk);
-
-	blkBits[chunk / 8] |= (1 << (chunk & 7));
+		}
+	}
 }
 
-static Y_INLINE int yaffs_CheckChunkBit(yaffs_Device * dev, int blk, int chunk)
+static void yaffs_handle_chunk_wr_error(struct yaffs_dev *dev, int nand_chunk,
+					int erased_ok)
 {
-	__u8 *blkBits = yaffs_BlockBits(dev, blk);
-	yaffs_VerifyChunkBitId(dev,blk,chunk);
+	int flash_block = nand_chunk / dev->param.chunks_per_block;
+	struct yaffs_block_info *bi = yaffs_get_block_info(dev, flash_block);
 
-	return (blkBits[chunk / 8] & (1 << (chunk & 7))) ? 1 : 0;
-}
+	yaffs_handle_chunk_error(dev, bi);
 
-static Y_INLINE int yaffs_StillSomeChunkBits(yaffs_Device * dev, int blk)
-{
-	__u8 *blkBits = yaffs_BlockBits(dev, blk);
-	int i;
-	for (i = 0; i < dev->chunkBitmapStride; i++) {
-		if (*blkBits)
-			return 1;
-		blkBits++;
+	if (erased_ok) {
+		/* Was an actual write failure,
+		 * so mark the block for retirement.*/
+		bi->needs_retiring = 1;
+		yaffs_trace(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS,
+		  "**>> Block %d needs retiring", flash_block);
 	}
-	return 0;
-}
-
-static int yaffs_CountChunkBits(yaffs_Device * dev, int blk)
-{
-	__u8 *blkBits = yaffs_BlockBits(dev, blk);
-	int i;
-	int n = 0;
-	for (i = 0; i < dev->chunkBitmapStride; i++) {
-		__u8 x = *blkBits;
-		while(x){
-			if(x & 1)
-				n++;
-			x >>=1;
-		}
 
-		blkBits++;
-	}
-	return n;
+	/* Delete the chunk */
+	yaffs_chunk_del(dev, nand_chunk, 1, __LINE__);
+	yaffs_skip_rest_of_block(dev);
 }
 
 /*
  * Verification code
  */
 
-static Y_INLINE int yaffs_SkipVerification(yaffs_Device *dev)
-{
-	return !(yaffs_traceMask & (YAFFS_TRACE_VERIFY | YAFFS_TRACE_VERIFY_FULL));
-}
-
-static Y_INLINE int yaffs_SkipFullVerification(yaffs_Device *dev)
-{
-	return !(yaffs_traceMask & (YAFFS_TRACE_VERIFY_FULL));
-}
+/*
+ *  Simple hash function. Needs to have a reasonable spread
+ */
 
-static Y_INLINE int yaffs_SkipNANDVerification(yaffs_Device *dev)
+static inline int yaffs_hash_fn(int n)
 {
-	return !(yaffs_traceMask & (YAFFS_TRACE_VERIFY_NAND));
+	if (n < 0)
+		n = -n;
+	return n % YAFFS_NOBJECT_BUCKETS;
 }
 
-static const char * blockStateName[] = {
-"Unknown",
-"Needs scanning",
-"Scanning",
-"Empty",
-"Allocating",
-"Full",
-"Dirty",
-"Checkpoint",
-"Collecting",
-"Dead"
-};
+/*
+ * Access functions to useful fake objects.
+ * Note that root might have a presence in NAND if permissions are set.
+ */
 
-static void yaffs_VerifyBlock(yaffs_Device *dev,yaffs_BlockInfo *bi,int n)
+struct yaffs_obj *yaffs_root(struct yaffs_dev *dev)
 {
-	int actuallyUsed;
-	int inUse;
-
-	if(yaffs_SkipVerification(dev))
-		return;
-
-	/* Report illegal runtime states */
-	if(bi->blockState <0 || bi->blockState >= YAFFS_NUMBER_OF_BLOCK_STATES)
-		T(YAFFS_TRACE_VERIFY,(TSTR("Block %d has undefined state %d"TENDSTR),n,bi->blockState));
-
-	switch(bi->blockState){
-	 case YAFFS_BLOCK_STATE_UNKNOWN:
-	 case YAFFS_BLOCK_STATE_SCANNING:
-	 case YAFFS_BLOCK_STATE_NEEDS_SCANNING:
-		T(YAFFS_TRACE_VERIFY,(TSTR("Block %d has bad run-state %s"TENDSTR),
-		n,blockStateName[bi->blockState]));
-	}
-
-	/* Check pages in use and soft deletions are legal */
-
-	actuallyUsed = bi->pagesInUse - bi->softDeletions;
-
-	if(bi->pagesInUse < 0 || bi->pagesInUse > dev->nChunksPerBlock ||
-	   bi->softDeletions < 0 || bi->softDeletions > dev->nChunksPerBlock ||
-	   actuallyUsed < 0 || actuallyUsed > dev->nChunksPerBlock)
-		T(YAFFS_TRACE_VERIFY,(TSTR("Block %d has illegal values pagesInUsed %d softDeletions %d"TENDSTR),
-		n,bi->pagesInUse,bi->softDeletions));
-
-
-	/* Check chunk bitmap legal */
-	inUse = yaffs_CountChunkBits(dev,n);
-	if(inUse != bi->pagesInUse)
-		T(YAFFS_TRACE_VERIFY,(TSTR("Block %d has inconsistent values pagesInUse %d counted chunk bits %d"TENDSTR),
-			n,bi->pagesInUse,inUse));
-
-	/* Check that the sequence number is valid.
-	 * Ten million is legal, but is very unlikely
-	 */
-	if(dev->isYaffs2 &&
-	   (bi->blockState == YAFFS_BLOCK_STATE_ALLOCATING || bi->blockState == YAFFS_BLOCK_STATE_FULL) &&
-	   (bi->sequenceNumber < YAFFS_LOWEST_SEQUENCE_NUMBER || bi->sequenceNumber > 10000000 ))
-		T(YAFFS_TRACE_VERIFY,(TSTR("Block %d has suspect sequence number of %d"TENDSTR),
-		n,bi->sequenceNumber));
-
+	return dev->root_dir;
 }
 
-static void yaffs_VerifyCollectedBlock(yaffs_Device *dev,yaffs_BlockInfo *bi,int n)
+struct yaffs_obj *yaffs_lost_n_found(struct yaffs_dev *dev)
 {
-	yaffs_VerifyBlock(dev,bi,n);
+	return dev->lost_n_found;
+}
 
-	/* After collection the block should be in the erased state */
-	/* TODO: This will need to change if we do partial gc */
+/*
+ *  Erased NAND checking functions
+ */
 
-	if(bi->blockState != YAFFS_BLOCK_STATE_EMPTY){
-		T(YAFFS_TRACE_ERROR,(TSTR("Block %d is in state %d after gc, should be erased"TENDSTR),
-			n,bi->blockState));
+int yaffs_check_ff(u8 *buffer, int n_bytes)
+{
+	/* Horrible, slow implementation */
+	while (n_bytes--) {
+		if (*buffer != 0xff)
+			return 0;
+		buffer++;
 	}
+	return 1;
 }
 
-static void yaffs_VerifyBlocks(yaffs_Device *dev)
+static int yaffs_check_chunk_erased(struct yaffs_dev *dev, int nand_chunk)
 {
-	int i;
-	int nBlocksPerState[YAFFS_NUMBER_OF_BLOCK_STATES];
-	int nIllegalBlockStates = 0;
-
-
-	if(yaffs_SkipVerification(dev))
-		return;
-
-	memset(nBlocksPerState,0,sizeof(nBlocksPerState));
-
+	int retval = YAFFS_OK;
+	u8 *data = yaffs_get_temp_buffer(dev);
+	struct yaffs_ext_tags tags;
 
-	for(i = dev->internalStartBlock; i <= dev->internalEndBlock; i++){
-		yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev,i);
-		yaffs_VerifyBlock(dev,bi,i);
+	yaffs_rd_chunk_tags_nand(dev, nand_chunk, data, &tags);
 
-		if(bi->blockState >=0 && bi->blockState < YAFFS_NUMBER_OF_BLOCK_STATES)
-			nBlocksPerState[bi->blockState]++;
-		else
-			nIllegalBlockStates++;
+	if (tags.ecc_result > YAFFS_ECC_RESULT_NO_ERROR)
+		retval = YAFFS_FAIL;
 
+	if (!yaffs_check_ff(data, dev->data_bytes_per_chunk) ||
+		tags.chunk_used) {
+		yaffs_trace(YAFFS_TRACE_NANDACCESS,
+			"Chunk %d not erased", nand_chunk);
+		retval = YAFFS_FAIL;
 	}
 
-	T(YAFFS_TRACE_VERIFY,(TSTR(""TENDSTR)));
-	T(YAFFS_TRACE_VERIFY,(TSTR("Block summary"TENDSTR)));
-
-	T(YAFFS_TRACE_VERIFY,(TSTR("%d blocks have illegal states"TENDSTR),nIllegalBlockStates));
-	if(nBlocksPerState[YAFFS_BLOCK_STATE_ALLOCATING] > 1)
-		T(YAFFS_TRACE_VERIFY,(TSTR("Too many allocating blocks"TENDSTR)));
-
-	for(i = 0; i < YAFFS_NUMBER_OF_BLOCK_STATES; i++)
-		T(YAFFS_TRACE_VERIFY,
-		  (TSTR("%s %d blocks"TENDSTR),
-		  blockStateName[i],nBlocksPerState[i]));
-
-	if(dev->blocksInCheckpoint != nBlocksPerState[YAFFS_BLOCK_STATE_CHECKPOINT])
-		T(YAFFS_TRACE_VERIFY,
-		 (TSTR("Checkpoint block count wrong dev %d count %d"TENDSTR),
-		 dev->blocksInCheckpoint, nBlocksPerState[YAFFS_BLOCK_STATE_CHECKPOINT]));
-
-	if(dev->nErasedBlocks != nBlocksPerState[YAFFS_BLOCK_STATE_EMPTY])
-		T(YAFFS_TRACE_VERIFY,
-		 (TSTR("Erased block count wrong dev %d count %d"TENDSTR),
-		 dev->nErasedBlocks, nBlocksPerState[YAFFS_BLOCK_STATE_EMPTY]));
-
-	if(nBlocksPerState[YAFFS_BLOCK_STATE_COLLECTING] > 1)
-		T(YAFFS_TRACE_VERIFY,
-		 (TSTR("Too many collecting blocks %d (max is 1)"TENDSTR),
-		 nBlocksPerState[YAFFS_BLOCK_STATE_COLLECTING]));
+	yaffs_release_temp_buffer(dev, data);
 
-	T(YAFFS_TRACE_VERIFY,(TSTR(""TENDSTR)));
+	return retval;
 
 }
 
-/*
- * Verify the object header. oh must be valid, but obj and tags may be NULL in which
- * case those tests will not be performed.
- */
-static void yaffs_VerifyObjectHeader(yaffs_Object *obj, yaffs_ObjectHeader *oh, yaffs_ExtendedTags *tags, int parentCheck)
+static int yaffs_verify_chunk_written(struct yaffs_dev *dev,
+				      int nand_chunk,
+				      const u8 *data,
+				      struct yaffs_ext_tags *tags)
 {
-	if(yaffs_SkipVerification(obj->myDev))
-		return;
-
-	if(!(tags && obj && oh)){
-		T(YAFFS_TRACE_VERIFY,
-				(TSTR("Verifying object header tags %x obj %x oh %x"TENDSTR),
-				(__u32)tags,(__u32)obj,(__u32)oh));
-		return;
-	}
-
-	if(oh->type <= YAFFS_OBJECT_TYPE_UNKNOWN ||
-	   oh->type > YAFFS_OBJECT_TYPE_MAX)
-		T(YAFFS_TRACE_VERIFY,
-		 (TSTR("Obj %d header type is illegal value 0x%x"TENDSTR),
-		 tags->objectId, oh->type));
-
-	if(tags->objectId != obj->objectId)
-		T(YAFFS_TRACE_VERIFY,
-		 (TSTR("Obj %d header mismatch objectId %d"TENDSTR),
-		 tags->objectId, obj->objectId));
+	int retval = YAFFS_OK;
+	struct yaffs_ext_tags temp_tags;
+	u8 *buffer = yaffs_get_temp_buffer(dev);
+
+	yaffs_rd_chunk_tags_nand(dev, nand_chunk, buffer, &temp_tags);
+	if (memcmp(buffer, data, dev->data_bytes_per_chunk) ||
+	    temp_tags.obj_id != tags->obj_id ||
+	    temp_tags.chunk_id != tags->chunk_id ||
+	    temp_tags.n_bytes != tags->n_bytes)
+		retval = YAFFS_FAIL;
 
+	yaffs_release_temp_buffer(dev, buffer);
 
-	/*
-	 * Check that the object's parent ids match if parentCheck requested.
-	 *
-	 * Tests do not apply to the root object.
-	 */
-
-	if(parentCheck && tags->objectId > 1 && !obj->parent)
-		T(YAFFS_TRACE_VERIFY,
-		 (TSTR("Obj %d header mismatch parentId %d obj->parent is NULL"TENDSTR),
-		 tags->objectId, oh->parentObjectId));
+	return retval;
+}
 
 
-	if(parentCheck && obj->parent &&
-	   oh->parentObjectId != obj->parent->objectId &&
-	   (oh->parentObjectId != YAFFS_OBJECTID_UNLINKED ||
-	    obj->parent->objectId != YAFFS_OBJECTID_DELETED))
-		T(YAFFS_TRACE_VERIFY,
-		 (TSTR("Obj %d header mismatch parentId %d parentObjectId %d"TENDSTR),
-		 tags->objectId, oh->parentObjectId, obj->parent->objectId));
+int yaffs_check_alloc_available(struct yaffs_dev *dev, int n_chunks)
+{
+	int reserved_chunks;
+	int reserved_blocks = dev->param.n_reserved_blocks;
+	int checkpt_blocks;
 
+	checkpt_blocks = yaffs_calc_checkpt_blocks_required(dev);
 
-	if(tags->objectId > 1 && oh->name[0] == 0) /* Null name */
-		T(YAFFS_TRACE_VERIFY,
-		(TSTR("Obj %d header name is NULL"TENDSTR),
-		 obj->objectId));
+	reserved_chunks =
+	    (reserved_blocks + checkpt_blocks) * dev->param.chunks_per_block;
 
-	if(tags->objectId > 1 && ((__u8)(oh->name[0])) == 0xff) /* Trashed name */
-		T(YAFFS_TRACE_VERIFY,
-		(TSTR("Obj %d header name is 0xFF"TENDSTR),
-		 obj->objectId));
+	return (dev->n_free_chunks > (reserved_chunks + n_chunks));
 }
 
-static void yaffs_VerifyFile(yaffs_Object *obj)
+static int yaffs_find_alloc_block(struct yaffs_dev *dev)
 {
-	int requiredTallness;
-	int actualTallness;
-	__u32 lastChunk;
-	__u32 x;
-	__u32 i;
-	yaffs_Device *dev;
-	yaffs_ExtendedTags tags;
-	yaffs_Tnode *tn;
-	__u32 objectId;
-
-	if(obj && yaffs_SkipVerification(obj->myDev))
-		return;
+	int i;
+	struct yaffs_block_info *bi;
 
-	dev = obj->myDev;
-	objectId = obj->objectId;
+	if (dev->n_erased_blocks < 1) {
+		/* Hoosterman we've got a problem.
+		 * Can't get space to gc
+		 */
+		yaffs_trace(YAFFS_TRACE_ERROR,
+		  "yaffs tragedy: no more erased blocks");
 
-	/* Check file size is consistent with tnode depth */
-	lastChunk =  obj->variant.fileVariant.fileSize / dev->nDataBytesPerChunk + 1;
-	x = lastChunk >> YAFFS_TNODES_LEVEL0_BITS;
-	requiredTallness = 0;
-	while (x> 0) {
-		x >>= YAFFS_TNODES_INTERNAL_BITS;
-		requiredTallness++;
+		return -1;
 	}
 
-	actualTallness = obj->variant.fileVariant.topLevel;
-
-	if(requiredTallness > actualTallness )
-		T(YAFFS_TRACE_VERIFY,
-		(TSTR("Obj %d had tnode tallness %d, needs to be %d"TENDSTR),
-		 obj->objectId,actualTallness, requiredTallness));
-
-
-	/* Check that the chunks in the tnode tree are all correct.
-	 * We do this by scanning through the tnode tree and
-	 * checking the tags for every chunk match.
-	 */
-
-	if(yaffs_SkipNANDVerification(dev))
-		return;
+	/* Find an empty block. */
 
-	for(i = 1; i <= lastChunk; i++){
-		tn = yaffs_FindLevel0Tnode(dev, &obj->variant.fileVariant,i);
-
-		if (tn) {
-			__u32 theChunk = yaffs_GetChunkGroupBase(dev,tn,i);
-			if(theChunk > 0){
-				/* T(~0,(TSTR("verifying (%d:%d) %d"TENDSTR),objectId,i,theChunk)); */
-				yaffs_ReadChunkWithTagsFromNAND(dev,theChunk,NULL, &tags);
-				if(tags.objectId != objectId || tags.chunkId != i){
-					T(~0,(TSTR("Object %d chunkId %d NAND mismatch chunk %d tags (%d:%d)"TENDSTR),
-						objectId, i, theChunk,
-						tags.objectId, tags.chunkId));
-				}
-			}
+	for (i = dev->internal_start_block; i <= dev->internal_end_block; i++) {
+		dev->alloc_block_finder++;
+		if (dev->alloc_block_finder < dev->internal_start_block
+		    || dev->alloc_block_finder > dev->internal_end_block) {
+			dev->alloc_block_finder = dev->internal_start_block;
 		}
 
+		bi = yaffs_get_block_info(dev, dev->alloc_block_finder);
+
+		if (bi->block_state == YAFFS_BLOCK_STATE_EMPTY) {
+			bi->block_state = YAFFS_BLOCK_STATE_ALLOCATING;
+			dev->seq_number++;
+			bi->seq_number = dev->seq_number;
+			dev->n_erased_blocks--;
+			yaffs_trace(YAFFS_TRACE_ALLOCATE,
+			  "Allocated block %d, seq  %d, %d left" ,
+			   dev->alloc_block_finder, dev->seq_number,
+			   dev->n_erased_blocks);
+			return dev->alloc_block_finder;
+		}
 	}
 
-}
-
-static void yaffs_VerifyDirectory(yaffs_Object *obj)
-{
-	if(obj && yaffs_SkipVerification(obj->myDev))
-		return;
-
-}
-
-static void yaffs_VerifyHardLink(yaffs_Object *obj)
-{
-	if(obj && yaffs_SkipVerification(obj->myDev))
-		return;
-
-	/* Verify sane equivalent object */
-}
-
-static void yaffs_VerifySymlink(yaffs_Object *obj)
-{
-	if(obj && yaffs_SkipVerification(obj->myDev))
-		return;
-
-	/* Verify symlink string */
-}
+	yaffs_trace(YAFFS_TRACE_ALWAYS,
+		"yaffs tragedy: no more erased blocks, but there should have been %d",
+		dev->n_erased_blocks);
 
-static void yaffs_VerifySpecial(yaffs_Object *obj)
-{
-	if(obj && yaffs_SkipVerification(obj->myDev))
-		return;
+	return -1;
 }
 
-static void yaffs_VerifyObject(yaffs_Object *obj)
+static int yaffs_alloc_chunk(struct yaffs_dev *dev, int use_reserver,
+			     struct yaffs_block_info **block_ptr)
 {
-	yaffs_Device *dev;
-
-	__u32 chunkMin;
-	__u32 chunkMax;
-
-	__u32 chunkIdOk;
-	__u32 chunkIsLive;
+	int ret_val;
+	struct yaffs_block_info *bi;
 
-	if(!obj)
-		return;
-
-	dev = obj->myDev;
-
-	if(yaffs_SkipVerification(dev))
-		return;
-
-	/* Check sane object header chunk */
-
-	chunkMin = dev->internalStartBlock * dev->nChunksPerBlock;
-	chunkMax = (dev->internalEndBlock+1) * dev->nChunksPerBlock - 1;
+	if (dev->alloc_block < 0) {
+		/* Get next block to allocate off */
+		dev->alloc_block = yaffs_find_alloc_block(dev);
+		dev->alloc_page = 0;
+	}
 
-	chunkIdOk = (obj->chunkId >= chunkMin && obj->chunkId <= chunkMax);
-	chunkIsLive = chunkIdOk &&
-			yaffs_CheckChunkBit(dev,
-					    obj->chunkId / dev->nChunksPerBlock,
-					    obj->chunkId % dev->nChunksPerBlock);
-	if(!obj->fake &&
-	    (!chunkIdOk || !chunkIsLive)) {
-	   T(YAFFS_TRACE_VERIFY,
-	   (TSTR("Obj %d has chunkId %d %s %s"TENDSTR),
-	   obj->objectId,obj->chunkId,
-	   chunkIdOk ? "" : ",out of range",
-	   chunkIsLive || !chunkIdOk ? "" : ",marked as deleted"));
+	if (!use_reserver && !yaffs_check_alloc_available(dev, 1)) {
+		/* No space unless we're allowed to use the reserve. */
+		return -1;
 	}
 
-	if(chunkIdOk && chunkIsLive &&!yaffs_SkipNANDVerification(dev)) {
-		yaffs_ExtendedTags tags;
-		yaffs_ObjectHeader *oh;
-		__u8 *buffer = yaffs_GetTempBuffer(dev,__LINE__);
+	if (dev->n_erased_blocks < dev->param.n_reserved_blocks
+	    && dev->alloc_page == 0)
+		yaffs_trace(YAFFS_TRACE_ALLOCATE, "Allocating reserve");
 
-		oh = (yaffs_ObjectHeader *)buffer;
+	/* Next page please.... */
+	if (dev->alloc_block >= 0) {
+		bi = yaffs_get_block_info(dev, dev->alloc_block);
 
-		yaffs_ReadChunkWithTagsFromNAND(dev, obj->chunkId,buffer, &tags);
+		ret_val = (dev->alloc_block * dev->param.chunks_per_block) +
+		    dev->alloc_page;
+		bi->pages_in_use++;
+		yaffs_set_chunk_bit(dev, dev->alloc_block, dev->alloc_page);
 
-		yaffs_VerifyObjectHeader(obj,oh,&tags,1);
+		dev->alloc_page++;
 
-		yaffs_ReleaseTempBuffer(dev,buffer,__LINE__);
-	}
+		dev->n_free_chunks--;
 
-	/* Verify it has a parent */
-	if(obj && !obj->fake &&
-	   (!obj->parent || obj->parent->myDev != dev)){
-	   T(YAFFS_TRACE_VERIFY,
-	   (TSTR("Obj %d has parent pointer %p which does not look like an object"TENDSTR),
-	   obj->objectId,obj->parent));
-	}
+		/* If the block is full set the state to full */
+		if (dev->alloc_page >= dev->param.chunks_per_block) {
+			bi->block_state = YAFFS_BLOCK_STATE_FULL;
+			dev->alloc_block = -1;
+		}
 
-	/* Verify parent is a directory */
-	if(obj->parent && obj->parent->variantType != YAFFS_OBJECT_TYPE_DIRECTORY){
-	   T(YAFFS_TRACE_VERIFY,
-	   (TSTR("Obj %d's parent is not a directory (type %d)"TENDSTR),
-	   obj->objectId,obj->parent->variantType));
-	}
+		if (block_ptr)
+			*block_ptr = bi;
 
-	switch(obj->variantType){
-	case YAFFS_OBJECT_TYPE_FILE:
-		yaffs_VerifyFile(obj);
-		break;
-	case YAFFS_OBJECT_TYPE_SYMLINK:
-		yaffs_VerifySymlink(obj);
-		break;
-	case YAFFS_OBJECT_TYPE_DIRECTORY:
-		yaffs_VerifyDirectory(obj);
-		break;
-	case YAFFS_OBJECT_TYPE_HARDLINK:
-		yaffs_VerifyHardLink(obj);
-		break;
-	case YAFFS_OBJECT_TYPE_SPECIAL:
-		yaffs_VerifySpecial(obj);
-		break;
-	case YAFFS_OBJECT_TYPE_UNKNOWN:
-	default:
-		T(YAFFS_TRACE_VERIFY,
-		(TSTR("Obj %d has illegaltype %d"TENDSTR),
-		obj->objectId,obj->variantType));
-		break;
+		return ret_val;
 	}
 
+	yaffs_trace(YAFFS_TRACE_ERROR,
+		"!!!!!!!!! Allocator out !!!!!!!!!!!!!!!!!");
 
+	return -1;
 }
 
-static void yaffs_VerifyObjects(yaffs_Device *dev)
+static int yaffs_get_erased_chunks(struct yaffs_dev *dev)
 {
-	yaffs_Object *obj;
-	int i;
-	struct list_head *lh;
-
-	if(yaffs_SkipVerification(dev))
-		return;
-
-	/* Iterate through the objects in each hash entry */
-
-	 for(i = 0; i <  YAFFS_NOBJECT_BUCKETS; i++){
-		list_for_each(lh, &dev->objectBucket[i].list) {
-			if (lh) {
-				obj = list_entry(lh, yaffs_Object, hashLink);
-				yaffs_VerifyObject(obj);
-			}
-		}
-	 }
+	int n;
 
-}
+	n = dev->n_erased_blocks * dev->param.chunks_per_block;
 
+	if (dev->alloc_block > 0)
+		n += (dev->param.chunks_per_block - dev->alloc_page);
 
-/*
- *  Simple hash function. Needs to have a reasonable spread
- */
+	return n;
 
-static Y_INLINE int yaffs_HashFunction(int n)
-{
-/* XXX U-BOOT XXX */
-	/*n = abs(n); */
-	if (n < 0)
-		n = -n;
-	return (n % YAFFS_NOBJECT_BUCKETS);
 }
 
 /*
- * Access functions to useful fake objects
+ * yaffs_skip_rest_of_block() skips over the rest of the allocation block
+ * if we don't want to write to it.
  */
-
-yaffs_Object *yaffs_Root(yaffs_Device * dev)
+void yaffs_skip_rest_of_block(struct yaffs_dev *dev)
 {
-	return dev->rootDir;
-}
-
-yaffs_Object *yaffs_LostNFound(yaffs_Device * dev)
-{
-	return dev->lostNFoundDir;
-}
-
-
-/*
- *  Erased NAND checking functions
- */
+	struct yaffs_block_info *bi;
 
-int yaffs_CheckFF(__u8 * buffer, int nBytes)
-{
-	/* Horrible, slow implementation */
-	while (nBytes--) {
-		if (*buffer != 0xFF)
-			return 0;
-		buffer++;
-	}
-	return 1;
-}
-
-static int yaffs_CheckChunkErased(struct yaffs_DeviceStruct *dev,
-				  int chunkInNAND)
-{
-
-	int retval = YAFFS_OK;
-	__u8 *data = yaffs_GetTempBuffer(dev, __LINE__);
-	yaffs_ExtendedTags tags;
-
-	yaffs_ReadChunkWithTagsFromNAND(dev, chunkInNAND, data, &tags);
-
-	if(tags.eccResult > YAFFS_ECC_RESULT_NO_ERROR)
-		retval = YAFFS_FAIL;
-
-
-	if (!yaffs_CheckFF(data, dev->nDataBytesPerChunk) || tags.chunkUsed) {
-		T(YAFFS_TRACE_NANDACCESS,
-		  (TSTR("Chunk %d not erased" TENDSTR), chunkInNAND));
-		retval = YAFFS_FAIL;
+	if (dev->alloc_block > 0) {
+		bi = yaffs_get_block_info(dev, dev->alloc_block);
+		if (bi->block_state == YAFFS_BLOCK_STATE_ALLOCATING) {
+			bi->block_state = YAFFS_BLOCK_STATE_FULL;
+			dev->alloc_block = -1;
+		}
 	}
-
-	yaffs_ReleaseTempBuffer(dev, data, __LINE__);
-
-	return retval;
-
 }
 
-static int yaffs_WriteNewChunkWithTagsToNAND(struct yaffs_DeviceStruct *dev,
-					     const __u8 * data,
-					     yaffs_ExtendedTags * tags,
-					     int useReserve)
+static int yaffs_write_new_chunk(struct yaffs_dev *dev,
+				 const u8 *data,
+				 struct yaffs_ext_tags *tags, int use_reserver)
 {
 	int attempts = 0;
-	int writeOk = 0;
+	int write_ok = 0;
 	int chunk;
 
-	yaffs_InvalidateCheckpoint(dev);
+	yaffs2_checkpt_invalidate(dev);
 
 	do {
-		yaffs_BlockInfo *bi = 0;
-		int erasedOk = 0;
+		struct yaffs_block_info *bi = 0;
+		int erased_ok = 0;
 
-		chunk = yaffs_AllocateChunk(dev, useReserve, &bi);
+		chunk = yaffs_alloc_chunk(dev, use_reserver, &bi);
 		if (chunk < 0) {
 			/* no space */
 			break;
@@ -897,7 +530,7 @@ static int yaffs_WriteNewChunkWithTagsToNAND(struct yaffs_DeviceStruct *dev,
 		 *
 		 * Check the first page we try to write in a block.
 		 * If the check passes then we don't need to check any
-		 * more.	If the check fails, we check again...
+		 * more.        If the check fails, we check again...
 		 * If the block has been erased, we don't need to check.
 		 *
 		 * However, if the block has been prioritised for gc,
@@ -909,55 +542,63 @@ static int yaffs_WriteNewChunkWithTagsToNAND(struct yaffs_DeviceStruct *dev,
 		 * chunk due to power loss.  This checking policy should
 		 * catch that case with very few checks and thus save a
 		 * lot of checks that are most likely not needed.
+		 *
+		 * Mods to the above
+		 * If an erase check fails or the write fails we skip the
+		 * rest of the block.
 		 */
-		if (bi->gcPrioritise) {
-			yaffs_DeleteChunk(dev, chunk, 1, __LINE__);
-			/* try another chunk */
-			continue;
-		}
 
 		/* let's give it a try */
 		attempts++;
 
-#ifdef CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED
-		bi->skipErasedCheck = 0;
-#endif
-		if (!bi->skipErasedCheck) {
-			erasedOk = yaffs_CheckChunkErased(dev, chunk);
-			if (erasedOk != YAFFS_OK) {
-				T(YAFFS_TRACE_ERROR,
-				(TSTR ("**>> yaffs chunk %d was not erased"
-				TENDSTR), chunk));
-
-				/* try another chunk */
+		if (dev->param.always_check_erased)
+			bi->skip_erased_check = 0;
+
+		if (!bi->skip_erased_check) {
+			erased_ok = yaffs_check_chunk_erased(dev, chunk);
+			if (erased_ok != YAFFS_OK) {
+				yaffs_trace(YAFFS_TRACE_ERROR,
+				  "**>> yaffs chunk %d was not erased",
+				  chunk);
+
+				/* If not erased, delete this one,
+				 * skip rest of block and
+				 * try another chunk */
+				yaffs_chunk_del(dev, chunk, 1, __LINE__);
+				yaffs_skip_rest_of_block(dev);
 				continue;
 			}
-			bi->skipErasedCheck = 1;
 		}
 
-		writeOk = yaffs_WriteChunkWithTagsToNAND(dev, chunk,
-				data, tags);
-		if (writeOk != YAFFS_OK) {
-			yaffs_HandleWriteChunkError(dev, chunk, erasedOk);
-			/* try another chunk */
+		write_ok = yaffs_wr_chunk_tags_nand(dev, chunk, data, tags);
+
+		if (!bi->skip_erased_check)
+			write_ok =
+			    yaffs_verify_chunk_written(dev, chunk, data, tags);
+
+		if (write_ok != YAFFS_OK) {
+			/* Clean up aborted write, skip to next block and
+			 * try another chunk */
+			yaffs_handle_chunk_wr_error(dev, chunk, erased_ok);
 			continue;
 		}
 
+		bi->skip_erased_check = 1;
+
 		/* Copy the data into the robustification buffer */
-		yaffs_HandleWriteChunkOk(dev, chunk, data, tags);
+		yaffs_handle_chunk_wr_ok(dev, chunk, data, tags);
 
-	} while (writeOk != YAFFS_OK &&
-		(yaffs_wr_attempts <= 0 || attempts <= yaffs_wr_attempts));
+	} while (write_ok != YAFFS_OK &&
+		 (yaffs_wr_attempts <= 0 || attempts <= yaffs_wr_attempts));
 
-	if(!writeOk)
+	if (!write_ok)
 		chunk = -1;
 
 	if (attempts > 1) {
-		T(YAFFS_TRACE_ERROR,
-			(TSTR("**>> yaffs write required %d attempts" TENDSTR),
-			attempts));
-
-		dev->nRetriedWrites += (attempts - 1);
+		yaffs_trace(YAFFS_TRACE_ERROR,
+			"**>> yaffs write required %d attempts",
+			attempts);
+		dev->n_retried_writes += (attempts - 1);
 	}
 
 	return chunk;
@@ -967,109 +608,97 @@ static int yaffs_WriteNewChunkWithTagsToNAND(struct yaffs_DeviceStruct *dev,
  * Block retiring for handling a broken block.
  */
 
-static void yaffs_RetireBlock(yaffs_Device * dev, int blockInNAND)
+static void yaffs_retire_block(struct yaffs_dev *dev, int flash_block)
 {
-	yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, blockInNAND);
+	struct yaffs_block_info *bi = yaffs_get_block_info(dev, flash_block);
 
-	yaffs_InvalidateCheckpoint(dev);
+	yaffs2_checkpt_invalidate(dev);
 
-	yaffs_MarkBlockBad(dev, blockInNAND);
+	yaffs2_clear_oldest_dirty_seq(dev, bi);
 
-	bi->blockState = YAFFS_BLOCK_STATE_DEAD;
-	bi->gcPrioritise = 0;
-	bi->needsRetiring = 0;
-
-	dev->nRetiredBlocks++;
-}
+	if (yaffs_mark_bad(dev, flash_block) != YAFFS_OK) {
+		if (yaffs_erase_block(dev, flash_block) != YAFFS_OK) {
+			yaffs_trace(YAFFS_TRACE_ALWAYS,
+				"yaffs: Failed to mark bad and erase block %d",
+				flash_block);
+		} else {
+			struct yaffs_ext_tags tags;
+			int chunk_id =
+			    flash_block * dev->param.chunks_per_block;
+
+			u8 *buffer = yaffs_get_temp_buffer(dev);
+
+			memset(buffer, 0xff, dev->data_bytes_per_chunk);
+			memset(&tags, 0, sizeof(tags));
+			tags.seq_number = YAFFS_SEQUENCE_BAD_BLOCK;
+			if (dev->param.write_chunk_tags_fn(dev, chunk_id -
+							   dev->chunk_offset,
+							   buffer,
+							   &tags) != YAFFS_OK)
+				yaffs_trace(YAFFS_TRACE_ALWAYS,
+					"yaffs: Failed to write bad block marker to block %d",
+					flash_block);
+
+			yaffs_release_temp_buffer(dev, buffer);
+		}
+	}
 
-/*
- * Functions for robustisizing TODO
- *
- */
+	bi->block_state = YAFFS_BLOCK_STATE_DEAD;
+	bi->gc_prioritise = 0;
+	bi->needs_retiring = 0;
 
-static void yaffs_HandleWriteChunkOk(yaffs_Device * dev, int chunkInNAND,
-				     const __u8 * data,
-				     const yaffs_ExtendedTags * tags)
-{
+	dev->n_retired_blocks++;
 }
 
-static void yaffs_HandleUpdateChunk(yaffs_Device * dev, int chunkInNAND,
-				    const yaffs_ExtendedTags * tags)
-{
-}
+/*---------------- Name handling functions ------------*/
 
-void yaffs_HandleChunkError(yaffs_Device *dev, yaffs_BlockInfo *bi)
+static u16 yaffs_calc_name_sum(const YCHAR *name)
 {
-	if(!bi->gcPrioritise){
-		bi->gcPrioritise = 1;
-		dev->hasPendingPrioritisedGCs = 1;
-		bi->chunkErrorStrikes ++;
+	u16 sum = 0;
+	u16 i = 1;
 
-		if(bi->chunkErrorStrikes > 3){
-			bi->needsRetiring = 1; /* Too many stikes, so retire this */
-			T(YAFFS_TRACE_ALWAYS, (TSTR("yaffs: Block struck out" TENDSTR)));
+	if (!name)
+		return 0;
 
-		}
+	while ((*name) && i < (YAFFS_MAX_NAME_LENGTH / 2)) {
 
+		/* 0x1f mask is case insensitive */
+		sum += ((*name) & 0x1f) * i;
+		i++;
+		name++;
 	}
+	return sum;
 }
 
-static void yaffs_HandleWriteChunkError(yaffs_Device * dev, int chunkInNAND, int erasedOk)
+void yaffs_set_obj_name(struct yaffs_obj *obj, const YCHAR * name)
 {
-
-	int blockInNAND = chunkInNAND / dev->nChunksPerBlock;
-	yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, blockInNAND);
-
-	yaffs_HandleChunkError(dev,bi);
-
-
-	if(erasedOk ) {
-		/* Was an actual write failure, so mark the block for retirement  */
-		bi->needsRetiring = 1;
-		T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS,
-		  (TSTR("**>> Block %d needs retiring" TENDSTR), blockInNAND));
-
-
-	}
-
-	/* Delete the chunk */
-	yaffs_DeleteChunk(dev, chunkInNAND, 1, __LINE__);
+	memset(obj->short_name, 0, sizeof(obj->short_name));
+	if (name &&
+		yaffs_strnlen(name, YAFFS_SHORT_NAME_LENGTH + 1) <=
+		YAFFS_SHORT_NAME_LENGTH)
+		yaffs_strcpy(obj->short_name, name);
+	else
+		obj->short_name[0] = _Y('\0');
+	obj->sum = yaffs_calc_name_sum(name);
 }
 
-
-/*---------------- Name handling functions ------------*/
-
-static __u16 yaffs_CalcNameSum(const YCHAR * name)
+void yaffs_set_obj_name_from_oh(struct yaffs_obj *obj,
+				const struct yaffs_obj_hdr *oh)
 {
-	__u16 sum = 0;
-	__u16 i = 1;
-
-	YUCHAR *bname = (YUCHAR *) name;
-	if (bname) {
-		while ((*bname) && (i < (YAFFS_MAX_NAME_LENGTH/2))) {
-
-#ifdef CONFIG_YAFFS_CASE_INSENSITIVE
-			sum += yaffs_toupper(*bname) * i;
+#ifdef CONFIG_YAFFS_AUTO_UNICODE
+	YCHAR tmp_name[YAFFS_MAX_NAME_LENGTH + 1];
+	memset(tmp_name, 0, sizeof(tmp_name));
+	yaffs_load_name_from_oh(obj->my_dev, tmp_name, oh->name,
+				YAFFS_MAX_NAME_LENGTH + 1);
+	yaffs_set_obj_name(obj, tmp_name);
 #else
-			sum += (*bname) * i;
+	yaffs_set_obj_name(obj, oh->name);
 #endif
-			i++;
-			bname++;
-		}
-	}
-	return sum;
 }
 
-static void yaffs_SetObjectName(yaffs_Object * obj, const YCHAR * name)
+loff_t yaffs_max_file_size(struct yaffs_dev *dev)
 {
-#ifdef CONFIG_YAFFS_SHORT_NAMES_IN_RAM
-	if (name && yaffs_strlen(name) <= YAFFS_SHORT_NAME_LENGTH) {
-		yaffs_strcpy(obj->shortName, name);
-	} else {
-		obj->shortName[0] = _Y('\0');
-	}
-#endif
-	obj->sum = yaffs_CalcNameSum(name);
+	return ((loff_t) YAFFS_MAX_CHUNK_ID) * dev->data_bytes_per_chunk;
 }
 
 /*-------------------- TNODES -------------------
@@ -1079,381 +708,235 @@ static void yaffs_SetObjectName(yaffs_Object * obj, const YCHAR * name)
  * in the tnode.
  */
 
-/* yaffs_CreateTnodes creates a bunch more tnodes and
- * adds them to the tnode free list.
- * Don't use this function directly
- */
-
-static int yaffs_CreateTnodes(yaffs_Device * dev, int nTnodes)
+struct yaffs_tnode *yaffs_get_tnode(struct yaffs_dev *dev)
 {
-	int i;
-	int tnodeSize;
-	yaffs_Tnode *newTnodes;
-	__u8 *mem;
-	yaffs_Tnode *curr;
-	yaffs_Tnode *next;
-	yaffs_TnodeList *tnl;
-
-	if (nTnodes < 1)
-		return YAFFS_OK;
-
-	/* Calculate the tnode size in bytes for variable width tnode support.
-	 * Must be a multiple of 32-bits  */
-	tnodeSize = (dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8;
-
-	/* make these things */
-
-	newTnodes = YMALLOC(nTnodes * tnodeSize);
-	mem = (__u8 *)newTnodes;
-
-	if (!newTnodes) {
-		T(YAFFS_TRACE_ERROR,
-		  (TSTR("yaffs: Could not allocate Tnodes" TENDSTR)));
-		return YAFFS_FAIL;
-	}
+	struct yaffs_tnode *tn = yaffs_alloc_raw_tnode(dev);
 
-	/* Hook them into the free list */
-#if 0
-	for (i = 0; i < nTnodes - 1; i++) {
-		newTnodes[i].internal[0] = &newTnodes[i + 1];
-#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG
-		newTnodes[i].internal[YAFFS_NTNODES_INTERNAL] = (void *)1;
-#endif
-	}
-
-	newTnodes[nTnodes - 1].internal[0] = dev->freeTnodes;
-#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG
-	newTnodes[nTnodes - 1].internal[YAFFS_NTNODES_INTERNAL] = (void *)1;
-#endif
-	dev->freeTnodes = newTnodes;
-#else
-	/* New hookup for wide tnodes */
-	for(i = 0; i < nTnodes -1; i++) {
-		curr = (yaffs_Tnode *) &mem[i * tnodeSize];
-		next = (yaffs_Tnode *) &mem[(i+1) * tnodeSize];
-		curr->internal[0] = next;
-	}
-
-	curr = (yaffs_Tnode *) &mem[(nTnodes - 1) * tnodeSize];
-	curr->internal[0] = dev->freeTnodes;
-	dev->freeTnodes = (yaffs_Tnode *)mem;
-
-#endif
-
-
-	dev->nFreeTnodes += nTnodes;
-	dev->nTnodesCreated += nTnodes;
-
-	/* Now add this bunch of tnodes to a list for freeing up.
-	 * NB If we can't add this to the management list it isn't fatal
-	 * but it just means we can't free this bunch of tnodes later.
-	 */
-
-	tnl = YMALLOC(sizeof(yaffs_TnodeList));
-	if (!tnl) {
-		T(YAFFS_TRACE_ERROR,
-		  (TSTR
-		   ("yaffs: Could not add tnodes to management list" TENDSTR)));
-		   return YAFFS_FAIL;
-
-	} else {
-		tnl->tnodes = newTnodes;
-		tnl->next = dev->allocatedTnodeList;
-		dev->allocatedTnodeList = tnl;
-	}
-
-	T(YAFFS_TRACE_ALLOCATE, (TSTR("yaffs: Tnodes added" TENDSTR)));
-
-	return YAFFS_OK;
-}
-
-/* GetTnode gets us a clean tnode. Tries to make allocate more if we run out */
-
-static yaffs_Tnode *yaffs_GetTnodeRaw(yaffs_Device * dev)
-{
-	yaffs_Tnode *tn = NULL;
-
-	/* If there are none left make more */
-	if (!dev->freeTnodes) {
-		yaffs_CreateTnodes(dev, YAFFS_ALLOCATION_NTNODES);
-	}
-
-	if (dev->freeTnodes) {
-		tn = dev->freeTnodes;
-#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG
-		if (tn->internal[YAFFS_NTNODES_INTERNAL] != (void *)1) {
-			/* Hoosterman, this thing looks like it isn't in the list */
-			T(YAFFS_TRACE_ALWAYS,
-			  (TSTR("yaffs: Tnode list bug 1" TENDSTR)));
-		}
-#endif
-		dev->freeTnodes = dev->freeTnodes->internal[0];
-		dev->nFreeTnodes--;
+	if (tn) {
+		memset(tn, 0, dev->tnode_size);
+		dev->n_tnodes++;
 	}
 
-	return tn;
-}
-
-static yaffs_Tnode *yaffs_GetTnode(yaffs_Device * dev)
-{
-	yaffs_Tnode *tn = yaffs_GetTnodeRaw(dev);
-
-	if(tn)
-		memset(tn, 0, (dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8);
+	dev->checkpoint_blocks_required = 0;	/* force recalculation */
 
 	return tn;
 }
 
 /* FreeTnode frees up a tnode and puts it back on the free list */
-static void yaffs_FreeTnode(yaffs_Device * dev, yaffs_Tnode * tn)
+static void yaffs_free_tnode(struct yaffs_dev *dev, struct yaffs_tnode *tn)
 {
-	if (tn) {
-#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG
-		if (tn->internal[YAFFS_NTNODES_INTERNAL] != 0) {
-			/* Hoosterman, this thing looks like it is already in the list */
-			T(YAFFS_TRACE_ALWAYS,
-			  (TSTR("yaffs: Tnode list bug 2" TENDSTR)));
-		}
-		tn->internal[YAFFS_NTNODES_INTERNAL] = (void *)1;
-#endif
-		tn->internal[0] = dev->freeTnodes;
-		dev->freeTnodes = tn;
-		dev->nFreeTnodes++;
-	}
+	yaffs_free_raw_tnode(dev, tn);
+	dev->n_tnodes--;
+	dev->checkpoint_blocks_required = 0;	/* force recalculation */
 }
 
-static void yaffs_DeinitialiseTnodes(yaffs_Device * dev)
+static void yaffs_deinit_tnodes_and_objs(struct yaffs_dev *dev)
 {
-	/* Free the list of allocated tnodes */
-	yaffs_TnodeList *tmp;
-
-	while (dev->allocatedTnodeList) {
-		tmp = dev->allocatedTnodeList->next;
-
-		YFREE(dev->allocatedTnodeList->tnodes);
-		YFREE(dev->allocatedTnodeList);
-		dev->allocatedTnodeList = tmp;
-
-	}
-
-	dev->freeTnodes = NULL;
-	dev->nFreeTnodes = 0;
+	yaffs_deinit_raw_tnodes_and_objs(dev);
+	dev->n_obj = 0;
+	dev->n_tnodes = 0;
 }
 
-static void yaffs_InitialiseTnodes(yaffs_Device * dev)
+void yaffs_load_tnode_0(struct yaffs_dev *dev, struct yaffs_tnode *tn,
+			unsigned pos, unsigned val)
 {
-	dev->allocatedTnodeList = NULL;
-	dev->freeTnodes = NULL;
-	dev->nFreeTnodes = 0;
-	dev->nTnodesCreated = 0;
+	u32 *map = (u32 *) tn;
+	u32 bit_in_map;
+	u32 bit_in_word;
+	u32 word_in_map;
+	u32 mask;
 
-}
-
-
-void yaffs_PutLevel0Tnode(yaffs_Device *dev, yaffs_Tnode *tn, unsigned pos, unsigned val)
-{
-  __u32 *map = (__u32 *)tn;
-  __u32 bitInMap;
-  __u32 bitInWord;
-  __u32 wordInMap;
-  __u32 mask;
-
-  pos &= YAFFS_TNODES_LEVEL0_MASK;
-  val >>= dev->chunkGroupBits;
+	pos &= YAFFS_TNODES_LEVEL0_MASK;
+	val >>= dev->chunk_grp_bits;
 
-  bitInMap = pos * dev->tnodeWidth;
-  wordInMap = bitInMap /32;
-  bitInWord = bitInMap & (32 -1);
+	bit_in_map = pos * dev->tnode_width;
+	word_in_map = bit_in_map / 32;
+	bit_in_word = bit_in_map & (32 - 1);
 
-  mask = dev->tnodeMask << bitInWord;
+	mask = dev->tnode_mask << bit_in_word;
 
-  map[wordInMap] &= ~mask;
-  map[wordInMap] |= (mask & (val << bitInWord));
+	map[word_in_map] &= ~mask;
+	map[word_in_map] |= (mask & (val << bit_in_word));
 
-  if(dev->tnodeWidth > (32-bitInWord)) {
-    bitInWord = (32 - bitInWord);
-    wordInMap++;;
-    mask = dev->tnodeMask >> (/*dev->tnodeWidth -*/ bitInWord);
-    map[wordInMap] &= ~mask;
-    map[wordInMap] |= (mask & (val >> bitInWord));
-  }
+	if (dev->tnode_width > (32 - bit_in_word)) {
+		bit_in_word = (32 - bit_in_word);
+		word_in_map++;
+		mask =
+		    dev->tnode_mask >> bit_in_word;
+		map[word_in_map] &= ~mask;
+		map[word_in_map] |= (mask & (val >> bit_in_word));
+	}
 }
 
-static __u32 yaffs_GetChunkGroupBase(yaffs_Device *dev, yaffs_Tnode *tn, unsigned pos)
+u32 yaffs_get_group_base(struct yaffs_dev *dev, struct yaffs_tnode *tn,
+			 unsigned pos)
 {
-  __u32 *map = (__u32 *)tn;
-  __u32 bitInMap;
-  __u32 bitInWord;
-  __u32 wordInMap;
-  __u32 val;
+	u32 *map = (u32 *) tn;
+	u32 bit_in_map;
+	u32 bit_in_word;
+	u32 word_in_map;
+	u32 val;
 
-  pos &= YAFFS_TNODES_LEVEL0_MASK;
+	pos &= YAFFS_TNODES_LEVEL0_MASK;
 
-  bitInMap = pos * dev->tnodeWidth;
-  wordInMap = bitInMap /32;
-  bitInWord = bitInMap & (32 -1);
+	bit_in_map = pos * dev->tnode_width;
+	word_in_map = bit_in_map / 32;
+	bit_in_word = bit_in_map & (32 - 1);
 
-  val = map[wordInMap] >> bitInWord;
+	val = map[word_in_map] >> bit_in_word;
 
-  if(dev->tnodeWidth > (32-bitInWord)) {
-    bitInWord = (32 - bitInWord);
-    wordInMap++;;
-    val |= (map[wordInMap] << bitInWord);
-  }
+	if (dev->tnode_width > (32 - bit_in_word)) {
+		bit_in_word = (32 - bit_in_word);
+		word_in_map++;
+		val |= (map[word_in_map] << bit_in_word);
+	}
 
-  val &= dev->tnodeMask;
-  val <<= dev->chunkGroupBits;
+	val &= dev->tnode_mask;
+	val <<= dev->chunk_grp_bits;
 
-  return val;
+	return val;
 }
 
 /* ------------------- End of individual tnode manipulation -----------------*/
 
 /* ---------Functions to manipulate the look-up tree (made up of tnodes) ------
- * The look up tree is represented by the top tnode and the number of topLevel
+ * The look up tree is represented by the top tnode and the number of top_level
  * in the tree. 0 means only the level 0 tnode is in the tree.
  */
 
 /* FindLevel0Tnode finds the level 0 tnode, if one exists. */
-static yaffs_Tnode *yaffs_FindLevel0Tnode(yaffs_Device * dev,
-					  yaffs_FileStructure * fStruct,
-					  __u32 chunkId)
+struct yaffs_tnode *yaffs_find_tnode_0(struct yaffs_dev *dev,
+				       struct yaffs_file_var *file_struct,
+				       u32 chunk_id)
 {
+	struct yaffs_tnode *tn = file_struct->top;
+	u32 i;
+	int required_depth;
+	int level = file_struct->top_level;
 
-	yaffs_Tnode *tn = fStruct->top;
-	__u32 i;
-	int requiredTallness;
-	int level = fStruct->topLevel;
+	dev = dev;
 
 	/* Check sane level and chunk Id */
-	if (level < 0 || level > YAFFS_TNODES_MAX_LEVEL) {
+	if (level < 0 || level > YAFFS_TNODES_MAX_LEVEL)
 		return NULL;
-	}
 
-	if (chunkId > YAFFS_MAX_CHUNK_ID) {
+	if (chunk_id > YAFFS_MAX_CHUNK_ID)
 		return NULL;
-	}
 
-	/* First check we're tall enough (ie enough topLevel) */
+	/* First check we're tall enough (ie enough top_level) */
 
-	i = chunkId >> YAFFS_TNODES_LEVEL0_BITS;
-	requiredTallness = 0;
+	i = chunk_id >> YAFFS_TNODES_LEVEL0_BITS;
+	required_depth = 0;
 	while (i) {
 		i >>= YAFFS_TNODES_INTERNAL_BITS;
-		requiredTallness++;
+		required_depth++;
 	}
 
-	if (requiredTallness > fStruct->topLevel) {
-		/* Not tall enough, so we can't find it, return NULL. */
-		return NULL;
-	}
+	if (required_depth > file_struct->top_level)
+		return NULL;	/* Not tall enough, so we can't find it */
 
 	/* Traverse down to level 0 */
 	while (level > 0 && tn) {
-		tn = tn->
-		    internal[(chunkId >>
-			       ( YAFFS_TNODES_LEVEL0_BITS +
-				 (level - 1) *
-				 YAFFS_TNODES_INTERNAL_BITS)
-			      ) &
-			     YAFFS_TNODES_INTERNAL_MASK];
+		tn = tn->internal[(chunk_id >>
+				   (YAFFS_TNODES_LEVEL0_BITS +
+				    (level - 1) *
+				    YAFFS_TNODES_INTERNAL_BITS)) &
+				  YAFFS_TNODES_INTERNAL_MASK];
 		level--;
-
 	}
 
 	return tn;
 }
 
-/* AddOrFindLevel0Tnode finds the level 0 tnode if it exists, otherwise first expands the tree.
+/* add_find_tnode_0 finds the level 0 tnode if it exists,
+ * otherwise first expands the tree.
  * This happens in two steps:
  *  1. If the tree isn't tall enough, then make it taller.
  *  2. Scan down the tree towards the level 0 tnode adding tnodes if required.
  *
  * Used when modifying the tree.
  *
- *  If the tn argument is NULL, then a fresh tnode will be added otherwise the specified tn will
- *  be plugged into the ttree.
+ *  If the tn argument is NULL, then a fresh tnode will be added otherwise the
+ *  specified tn will be plugged into the ttree.
  */
 
-static yaffs_Tnode *yaffs_AddOrFindLevel0Tnode(yaffs_Device * dev,
-					       yaffs_FileStructure * fStruct,
-					       __u32 chunkId,
-					       yaffs_Tnode *passedTn)
+struct yaffs_tnode *yaffs_add_find_tnode_0(struct yaffs_dev *dev,
+					   struct yaffs_file_var *file_struct,
+					   u32 chunk_id,
+					   struct yaffs_tnode *passed_tn)
 {
-
-	int requiredTallness;
+	int required_depth;
 	int i;
 	int l;
-	yaffs_Tnode *tn;
-
-	__u32 x;
-
+	struct yaffs_tnode *tn;
+	u32 x;
 
 	/* Check sane level and page Id */
-	if (fStruct->topLevel < 0 || fStruct->topLevel > YAFFS_TNODES_MAX_LEVEL) {
+	if (file_struct->top_level < 0 ||
+	    file_struct->top_level > YAFFS_TNODES_MAX_LEVEL)
 		return NULL;
-	}
 
-	if (chunkId > YAFFS_MAX_CHUNK_ID) {
+	if (chunk_id > YAFFS_MAX_CHUNK_ID)
 		return NULL;
-	}
 
-	/* First check we're tall enough (ie enough topLevel) */
+	/* First check we're tall enough (ie enough top_level) */
 
-	x = chunkId >> YAFFS_TNODES_LEVEL0_BITS;
-	requiredTallness = 0;
+	x = chunk_id >> YAFFS_TNODES_LEVEL0_BITS;
+	required_depth = 0;
 	while (x) {
 		x >>= YAFFS_TNODES_INTERNAL_BITS;
-		requiredTallness++;
+		required_depth++;
 	}
 
+	if (required_depth > file_struct->top_level) {
+		/* Not tall enough, gotta make the tree taller */
+		for (i = file_struct->top_level; i < required_depth; i++) {
 
-	if (requiredTallness > fStruct->topLevel) {
-		/* Not tall enough,gotta make the tree taller */
-		for (i = fStruct->topLevel; i < requiredTallness; i++) {
-
-			tn = yaffs_GetTnode(dev);
+			tn = yaffs_get_tnode(dev);
 
 			if (tn) {
-				tn->internal[0] = fStruct->top;
-				fStruct->top = tn;
+				tn->internal[0] = file_struct->top;
+				file_struct->top = tn;
+				file_struct->top_level++;
 			} else {
-				T(YAFFS_TRACE_ERROR,
-				  (TSTR("yaffs: no more tnodes" TENDSTR)));
+				yaffs_trace(YAFFS_TRACE_ERROR,
+					"yaffs: no more tnodes");
+				return NULL;
 			}
 		}
-
-		fStruct->topLevel = requiredTallness;
 	}
 
 	/* Traverse down to level 0, adding anything we need */
 
-	l = fStruct->topLevel;
-	tn = fStruct->top;
+	l = file_struct->top_level;
+	tn = file_struct->top;
 
-	if(l > 0) {
+	if (l > 0) {
 		while (l > 0 && tn) {
-			x = (chunkId >>
-			     ( YAFFS_TNODES_LEVEL0_BITS +
+			x = (chunk_id >>
+			     (YAFFS_TNODES_LEVEL0_BITS +
 			      (l - 1) * YAFFS_TNODES_INTERNAL_BITS)) &
 			    YAFFS_TNODES_INTERNAL_MASK;
 
-
-			if((l>1) && !tn->internal[x]){
+			if ((l > 1) && !tn->internal[x]) {
 				/* Add missing non-level-zero tnode */
-				tn->internal[x] = yaffs_GetTnode(dev);
-
-			} else if(l == 1) {
+				tn->internal[x] = yaffs_get_tnode(dev);
+				if (!tn->internal[x])
+					return NULL;
+			} else if (l == 1) {
 				/* Looking from level 1 at level 0 */
-				if (passedTn) {
-					/* If we already have one, then release it.*/
-					if(tn->internal[x])
-						yaffs_FreeTnode(dev,tn->internal[x]);
-					tn->internal[x] = passedTn;
-
-				} else if(!tn->internal[x]) {
+				if (passed_tn) {
+					/* If we already have one, release it */
+					if (tn->internal[x])
+						yaffs_free_tnode(dev,
+							tn->internal[x]);
+					tn->internal[x] = passed_tn;
+
+				} else if (!tn->internal[x]) {
 					/* Don't have one, none passed in */
-					tn->internal[x] = yaffs_GetTnode(dev);
+					tn->internal[x] = yaffs_get_tnode(dev);
+					if (!tn->internal[x])
+						return NULL;
 				}
 			}
 
@@ -1462,2979 +945,2471 @@ static yaffs_Tnode *yaffs_AddOrFindLevel0Tnode(yaffs_Device * dev,
 		}
 	} else {
 		/* top is level 0 */
-		if(passedTn) {
-			memcpy(tn,passedTn,(dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8);
-			yaffs_FreeTnode(dev,passedTn);
+		if (passed_tn) {
+			memcpy(tn, passed_tn,
+			       (dev->tnode_width * YAFFS_NTNODES_LEVEL0) / 8);
+			yaffs_free_tnode(dev, passed_tn);
 		}
 	}
 
 	return tn;
 }
 
-static int yaffs_FindChunkInGroup(yaffs_Device * dev, int theChunk,
-				  yaffs_ExtendedTags * tags, int objectId,
-				  int chunkInInode)
+static int yaffs_tags_match(const struct yaffs_ext_tags *tags, int obj_id,
+			    int chunk_obj)
 {
-	int j;
+	return (tags->chunk_id == chunk_obj &&
+		tags->obj_id == obj_id &&
+		!tags->is_deleted) ? 1 : 0;
 
-	for (j = 0; theChunk && j < dev->chunkGroupSize; j++) {
-		if (yaffs_CheckChunkBit
-		    (dev, theChunk / dev->nChunksPerBlock,
-		     theChunk % dev->nChunksPerBlock)) {
-			yaffs_ReadChunkWithTagsFromNAND(dev, theChunk, NULL,
-							tags);
-			if (yaffs_TagsMatch(tags, objectId, chunkInInode)) {
-				/* found it; */
-				return theChunk;
+}
 
+static int yaffs_find_chunk_in_group(struct yaffs_dev *dev, int the_chunk,
+					struct yaffs_ext_tags *tags, int obj_id,
+					int inode_chunk)
+{
+	int j;
+
+	for (j = 0; the_chunk && j < dev->chunk_grp_size; j++) {
+		if (yaffs_check_chunk_bit
+		    (dev, the_chunk / dev->param.chunks_per_block,
+		     the_chunk % dev->param.chunks_per_block)) {
+
+			if (dev->chunk_grp_size == 1)
+				return the_chunk;
+			else {
+				yaffs_rd_chunk_tags_nand(dev, the_chunk, NULL,
+							 tags);
+				if (yaffs_tags_match(tags,
+							obj_id, inode_chunk)) {
+					/* found it; */
+					return the_chunk;
+				}
 			}
 		}
-		theChunk++;
+		the_chunk++;
 	}
 	return -1;
 }
 
-static void yaffs_SoftDeleteChunk(yaffs_Device * dev, int chunk)
+static int yaffs_find_chunk_in_file(struct yaffs_obj *in, int inode_chunk,
+				    struct yaffs_ext_tags *tags)
 {
+	/*Get the Tnode, then get the level 0 offset chunk offset */
+	struct yaffs_tnode *tn;
+	int the_chunk = -1;
+	struct yaffs_ext_tags local_tags;
+	int ret_val = -1;
+	struct yaffs_dev *dev = in->my_dev;
 
-	yaffs_BlockInfo *theBlock;
-
-	T(YAFFS_TRACE_DELETION, (TSTR("soft delete chunk %d" TENDSTR), chunk));
-
-	theBlock = yaffs_GetBlockInfo(dev, chunk / dev->nChunksPerBlock);
-	if (theBlock) {
-		theBlock->softDeletions++;
-		dev->nFreeChunks++;
+	if (!tags) {
+		/* Passed a NULL, so use our own tags space */
+		tags = &local_tags;
 	}
-}
 
-/* SoftDeleteWorker scans backwards through the tnode tree and soft deletes all the chunks in the file.
- * All soft deleting does is increment the block's softdelete count and pulls the chunk out
- * of the tnode.
- * Thus, essentially this is the same as DeleteWorker except that the chunks are soft deleted.
- */
+	tn = yaffs_find_tnode_0(dev, &in->variant.file_variant, inode_chunk);
 
-static int yaffs_SoftDeleteWorker(yaffs_Object * in, yaffs_Tnode * tn,
-				  __u32 level, int chunkOffset)
-{
-	int i;
-	int theChunk;
-	int allDone = 1;
-	yaffs_Device *dev = in->myDev;
+	if (!tn)
+		return ret_val;
 
-	if (tn) {
-		if (level > 0) {
-
-			for (i = YAFFS_NTNODES_INTERNAL - 1; allDone && i >= 0;
-			     i--) {
-				if (tn->internal[i]) {
-					allDone =
-					    yaffs_SoftDeleteWorker(in,
-								   tn->
-								   internal[i],
-								   level - 1,
-								   (chunkOffset
-								    <<
-								    YAFFS_TNODES_INTERNAL_BITS)
-								   + i);
-					if (allDone) {
-						yaffs_FreeTnode(dev,
-								tn->
-								internal[i]);
-						tn->internal[i] = NULL;
-					} else {
-						/* Hoosterman... how could this happen? */
-					}
-				}
-			}
-			return (allDone) ? 1 : 0;
-		} else if (level == 0) {
-
-			for (i = YAFFS_NTNODES_LEVEL0 - 1; i >= 0; i--) {
-				theChunk = yaffs_GetChunkGroupBase(dev,tn,i);
-				if (theChunk) {
-					/* Note this does not find the real chunk, only the chunk group.
-					 * We make an assumption that a chunk group is not larger than
-					 * a block.
-					 */
-					yaffs_SoftDeleteChunk(dev, theChunk);
-					yaffs_PutLevel0Tnode(dev,tn,i,0);
-				}
-
-			}
-			return 1;
-
-		}
-
-	}
-
-	return 1;
+	the_chunk = yaffs_get_group_base(dev, tn, inode_chunk);
 
+	ret_val = yaffs_find_chunk_in_group(dev, the_chunk, tags, in->obj_id,
+					      inode_chunk);
+	return ret_val;
 }
 
-static void yaffs_SoftDeleteFile(yaffs_Object * obj)
+static int yaffs_find_del_file_chunk(struct yaffs_obj *in, int inode_chunk,
+				     struct yaffs_ext_tags *tags)
 {
-	if (obj->deleted &&
-	    obj->variantType == YAFFS_OBJECT_TYPE_FILE && !obj->softDeleted) {
-		if (obj->nDataChunks <= 0) {
-			/* Empty file with no duplicate object headers, just delete it immediately */
-			yaffs_FreeTnode(obj->myDev,
-					obj->variant.fileVariant.top);
-			obj->variant.fileVariant.top = NULL;
-			T(YAFFS_TRACE_TRACING,
-			  (TSTR("yaffs: Deleting empty file %d" TENDSTR),
-			   obj->objectId));
-			yaffs_DoGenericObjectDeletion(obj);
-		} else {
-			yaffs_SoftDeleteWorker(obj,
-					       obj->variant.fileVariant.top,
-					       obj->variant.fileVariant.
-					       topLevel, 0);
-			obj->softDeleted = 1;
-		}
-	}
-}
-
-/* Pruning removes any part of the file structure tree that is beyond the
- * bounds of the file (ie that does not point to chunks).
- *
- * A file should only get pruned when its size is reduced.
- *
- * Before pruning, the chunks must be pulled from the tree and the
- * level 0 tnode entries must be zeroed out.
- * Could also use this for file deletion, but that's probably better handled
- * by a special case.
- */
+	/* Get the Tnode, then get the level 0 offset chunk offset */
+	struct yaffs_tnode *tn;
+	int the_chunk = -1;
+	struct yaffs_ext_tags local_tags;
+	struct yaffs_dev *dev = in->my_dev;
+	int ret_val = -1;
 
-static yaffs_Tnode *yaffs_PruneWorker(yaffs_Device * dev, yaffs_Tnode * tn,
-				      __u32 level, int del0)
-{
-	int i;
-	int hasData;
+	if (!tags) {
+		/* Passed a NULL, so use our own tags space */
+		tags = &local_tags;
+	}
 
-	if (tn) {
-		hasData = 0;
+	tn = yaffs_find_tnode_0(dev, &in->variant.file_variant, inode_chunk);
 
-		for (i = 0; i < YAFFS_NTNODES_INTERNAL; i++) {
-			if (tn->internal[i] && level > 0) {
-				tn->internal[i] =
-				    yaffs_PruneWorker(dev, tn->internal[i],
-						      level - 1,
-						      (i == 0) ? del0 : 1);
-			}
-
-			if (tn->internal[i]) {
-				hasData++;
-			}
-		}
+	if (!tn)
+		return ret_val;
 
-		if (hasData == 0 && del0) {
-			/* Free and return NULL */
+	the_chunk = yaffs_get_group_base(dev, tn, inode_chunk);
 
-			yaffs_FreeTnode(dev, tn);
-			tn = NULL;
-		}
+	ret_val = yaffs_find_chunk_in_group(dev, the_chunk, tags, in->obj_id,
+					      inode_chunk);
 
-	}
-
-	return tn;
+	/* Delete the entry in the filestructure (if found) */
+	if (ret_val != -1)
+		yaffs_load_tnode_0(dev, tn, inode_chunk, 0);
 
+	return ret_val;
 }
 
-static int yaffs_PruneFileStructure(yaffs_Device * dev,
-				    yaffs_FileStructure * fStruct)
+int yaffs_put_chunk_in_file(struct yaffs_obj *in, int inode_chunk,
+			    int nand_chunk, int in_scan)
 {
-	int i;
-	int hasData;
-	int done = 0;
-	yaffs_Tnode *tn;
+	/* NB in_scan is zero unless scanning.
+	 * For forward scanning, in_scan is > 0;
+	 * for backward scanning in_scan is < 0
+	 *
+	 * nand_chunk = 0 is a dummy insert to make sure the tnodes are there.
+	 */
 
-	if (fStruct->topLevel > 0) {
-		fStruct->top =
-		    yaffs_PruneWorker(dev, fStruct->top, fStruct->topLevel, 0);
+	struct yaffs_tnode *tn;
+	struct yaffs_dev *dev = in->my_dev;
+	int existing_cunk;
+	struct yaffs_ext_tags existing_tags;
+	struct yaffs_ext_tags new_tags;
+	unsigned existing_serial, new_serial;
 
-		/* Now we have a tree with all the non-zero branches NULL but the height
-		 * is the same as it was.
-		 * Let's see if we can trim internal tnodes to shorten the tree.
-		 * We can do this if only the 0th element in the tnode is in use
-		 * (ie all the non-zero are NULL)
+	if (in->variant_type != YAFFS_OBJECT_TYPE_FILE) {
+		/* Just ignore an attempt at putting a chunk into a non-file
+		 * during scanning.
+		 * If it is not during Scanning then something went wrong!
 		 */
-
-		while (fStruct->topLevel && !done) {
-			tn = fStruct->top;
-
-			hasData = 0;
-			for (i = 1; i < YAFFS_NTNODES_INTERNAL; i++) {
-				if (tn->internal[i]) {
-					hasData++;
-				}
-			}
-
-			if (!hasData) {
-				fStruct->top = tn->internal[0];
-				fStruct->topLevel--;
-				yaffs_FreeTnode(dev, tn);
-			} else {
-				done = 1;
-			}
+		if (!in_scan) {
+			yaffs_trace(YAFFS_TRACE_ERROR,
+				"yaffs tragedy:attempt to put data chunk into a non-file"
+				);
+			BUG();
 		}
-	}
-
-	return YAFFS_OK;
-}
 
-/*-------------------- End of File Structure functions.-------------------*/
-
-/* yaffs_CreateFreeObjects creates a bunch more objects and
- * adds them to the object free list.
- */
-static int yaffs_CreateFreeObjects(yaffs_Device * dev, int nObjects)
-{
-	int i;
-	yaffs_Object *newObjects;
-	yaffs_ObjectList *list;
-
-	if (nObjects < 1)
+		yaffs_chunk_del(dev, nand_chunk, 1, __LINE__);
 		return YAFFS_OK;
-
-	/* make these things */
-	newObjects = YMALLOC(nObjects * sizeof(yaffs_Object));
-	list = YMALLOC(sizeof(yaffs_ObjectList));
-
-	if (!newObjects || !list) {
-		if(newObjects)
-			YFREE(newObjects);
-		if(list)
-			YFREE(list);
-		T(YAFFS_TRACE_ALLOCATE,
-		  (TSTR("yaffs: Could not allocate more objects" TENDSTR)));
-		return YAFFS_FAIL;
-	}
-
-	/* Hook them into the free list */
-	for (i = 0; i < nObjects - 1; i++) {
-		newObjects[i].siblings.next =
-		    (struct list_head *)(&newObjects[i + 1]);
-	}
-
-	newObjects[nObjects - 1].siblings.next = (void *)dev->freeObjects;
-	dev->freeObjects = newObjects;
-	dev->nFreeObjects += nObjects;
-	dev->nObjectsCreated += nObjects;
-
-	/* Now add this bunch of Objects to a list for freeing up. */
-
-	list->objects = newObjects;
-	list->next = dev->allocatedObjectList;
-	dev->allocatedObjectList = list;
-
-	return YAFFS_OK;
-}
-
-
-/* AllocateEmptyObject gets us a clean Object. Tries to make allocate more if we run out */
-static yaffs_Object *yaffs_AllocateEmptyObject(yaffs_Device * dev)
-{
-	yaffs_Object *tn = NULL;
-
-	/* If there are none left make more */
-	if (!dev->freeObjects) {
-		yaffs_CreateFreeObjects(dev, YAFFS_ALLOCATION_NOBJECTS);
 	}
 
-	if (dev->freeObjects) {
-		tn = dev->freeObjects;
-		dev->freeObjects =
-		    (yaffs_Object *) (dev->freeObjects->siblings.next);
-		dev->nFreeObjects--;
+	tn = yaffs_add_find_tnode_0(dev,
+				    &in->variant.file_variant,
+				    inode_chunk, NULL);
+	if (!tn)
+		return YAFFS_FAIL;
 
-		/* Now sweeten it up... */
+	if (!nand_chunk)
+		/* Dummy insert, bail now */
+		return YAFFS_OK;
 
-		memset(tn, 0, sizeof(yaffs_Object));
-		tn->myDev = dev;
-		tn->chunkId = -1;
-		tn->variantType = YAFFS_OBJECT_TYPE_UNKNOWN;
-		INIT_LIST_HEAD(&(tn->hardLinks));
-		INIT_LIST_HEAD(&(tn->hashLink));
-		INIT_LIST_HEAD(&tn->siblings);
+	existing_cunk = yaffs_get_group_base(dev, tn, inode_chunk);
 
-		/* Add it to the lost and found directory.
-		 * NB Can't put root or lostNFound in lostNFound so
-		 * check if lostNFound exists first
+	if (in_scan != 0) {
+		/* If we're scanning then we need to test for duplicates
+		 * NB This does not need to be efficient since it should only
+		 * happen when the power fails during a write, then only one
+		 * chunk should ever be affected.
+		 *
+		 * Correction for YAFFS2: This could happen quite a lot and we
+		 * need to think about efficiency! TODO
+		 * Update: For backward scanning we don't need to re-read tags
+		 * so this is quite cheap.
 		 */
-		if (dev->lostNFoundDir) {
-			yaffs_AddObjectToDirectory(dev->lostNFoundDir, tn);
-		}
-	}
 
-	return tn;
-}
-
-static yaffs_Object *yaffs_CreateFakeDirectory(yaffs_Device * dev, int number,
-					       __u32 mode)
-{
+		if (existing_cunk > 0) {
+			/* NB Right now existing chunk will not be real
+			 * chunk_id if the chunk group size > 1
+			 * thus we have to do a FindChunkInFile to get the
+			 * real chunk id.
+			 *
+			 * We have a duplicate now we need to decide which
+			 * one to use:
+			 *
+			 * Backwards scanning YAFFS2: The old one is what
+			 * we use, dump the new one.
+			 * YAFFS1: Get both sets of tags and compare serial
+			 * numbers.
+			 */
 
-	yaffs_Object *obj =
-	    yaffs_CreateNewObject(dev, number, YAFFS_OBJECT_TYPE_DIRECTORY);
-	if (obj) {
-		obj->fake = 1;		/* it is fake so it has no NAND presence... */
-		obj->renameAllowed = 0;	/* ... and we're not allowed to rename it... */
-		obj->unlinkAllowed = 0;	/* ... or unlink it */
-		obj->deleted = 0;
-		obj->unlinked = 0;
-		obj->yst_mode = mode;
-		obj->myDev = dev;
-		obj->chunkId = 0;	/* Not a valid chunk. */
-	}
+			if (in_scan > 0) {
+				/* Only do this for forward scanning */
+				yaffs_rd_chunk_tags_nand(dev,
+							 nand_chunk,
+							 NULL, &new_tags);
 
-	return obj;
+				/* Do a proper find */
+				existing_cunk =
+				    yaffs_find_chunk_in_file(in, inode_chunk,
+							     &existing_tags);
+			}
 
-}
+			if (existing_cunk <= 0) {
+				/*Hoosterman - how did this happen? */
 
-static void yaffs_UnhashObject(yaffs_Object * tn)
-{
-	int bucket;
-	yaffs_Device *dev = tn->myDev;
+				yaffs_trace(YAFFS_TRACE_ERROR,
+					"yaffs tragedy: existing chunk < 0 in scan"
+					);
 
-	/* If it is still linked into the bucket list, free from the list */
-	if (!list_empty(&tn->hashLink)) {
-		list_del_init(&tn->hashLink);
-		bucket = yaffs_HashFunction(tn->objectId);
-		dev->objectBucket[bucket].count--;
-	}
+			}
 
-}
+			/* NB The deleted flags should be false, otherwise
+			 * the chunks will not be loaded during a scan
+			 */
 
-/*  FreeObject frees up a Object and puts it back on the free list */
-static void yaffs_FreeObject(yaffs_Object * tn)
-{
+			if (in_scan > 0) {
+				new_serial = new_tags.serial_number;
+				existing_serial = existing_tags.serial_number;
+			}
 
-	yaffs_Device *dev = tn->myDev;
+			if ((in_scan > 0) &&
+			    (existing_cunk <= 0 ||
+			     ((existing_serial + 1) & 3) == new_serial)) {
+				/* Forward scanning.
+				 * Use new
+				 * Delete the old one and drop through to
+				 * update the tnode
+				 */
+				yaffs_chunk_del(dev, existing_cunk, 1,
+						__LINE__);
+			} else {
+				/* Backward scanning or we want to use the
+				 * existing one
+				 * Delete the new one and return early so that
+				 * the tnode isn't changed
+				 */
+				yaffs_chunk_del(dev, nand_chunk, 1, __LINE__);
+				return YAFFS_OK;
+			}
+		}
 
-/* XXX U-BOOT XXX */
-#if 0
-#ifdef  __KERNEL__
-	if (tn->myInode) {
-		/* We're still hooked up to a cached inode.
-		 * Don't delete now, but mark for later deletion
-		 */
-		tn->deferedFree = 1;
-		return;
 	}
-#endif
-#endif
-	yaffs_UnhashObject(tn);
 
-	/* Link into the free list. */
-	tn->siblings.next = (struct list_head *)(dev->freeObjects);
-	dev->freeObjects = tn;
-	dev->nFreeObjects++;
-}
+	if (existing_cunk == 0)
+		in->n_data_chunks++;
 
-/* XXX U-BOOT XXX */
-#if 0
-#ifdef __KERNEL__
+	yaffs_load_tnode_0(dev, tn, inode_chunk, nand_chunk);
 
-void yaffs_HandleDeferedFree(yaffs_Object * obj)
-{
-	if (obj->deferedFree) {
-		yaffs_FreeObject(obj);
-	}
+	return YAFFS_OK;
 }
 
-#endif
-#endif
-
-static void yaffs_DeinitialiseObjects(yaffs_Device * dev)
+static void yaffs_soft_del_chunk(struct yaffs_dev *dev, int chunk)
 {
-	/* Free the list of allocated Objects */
+	struct yaffs_block_info *the_block;
+	unsigned block_no;
 
-	yaffs_ObjectList *tmp;
+	yaffs_trace(YAFFS_TRACE_DELETION, "soft delete chunk %d", chunk);
 
-	while (dev->allocatedObjectList) {
-		tmp = dev->allocatedObjectList->next;
-		YFREE(dev->allocatedObjectList->objects);
-		YFREE(dev->allocatedObjectList);
-
-		dev->allocatedObjectList = tmp;
+	block_no = chunk / dev->param.chunks_per_block;
+	the_block = yaffs_get_block_info(dev, block_no);
+	if (the_block) {
+		the_block->soft_del_pages++;
+		dev->n_free_chunks++;
+		yaffs2_update_oldest_dirty_seq(dev, block_no, the_block);
 	}
-
-	dev->freeObjects = NULL;
-	dev->nFreeObjects = 0;
 }
 
-static void yaffs_InitialiseObjects(yaffs_Device * dev)
-{
-	int i;
-
-	dev->allocatedObjectList = NULL;
-	dev->freeObjects = NULL;
-	dev->nFreeObjects = 0;
-
-	for (i = 0; i < YAFFS_NOBJECT_BUCKETS; i++) {
-		INIT_LIST_HEAD(&dev->objectBucket[i].list);
-		dev->objectBucket[i].count = 0;
-	}
-
-}
+/* SoftDeleteWorker scans backwards through the tnode tree and soft deletes all
+ * the chunks in the file.
+ * All soft deleting does is increment the block's softdelete count and pulls
+ * the chunk out of the tnode.
+ * Thus, essentially this is the same as DeleteWorker except that the chunks
+ * are soft deleted.
+ */
 
-static int yaffs_FindNiceObjectBucket(yaffs_Device * dev)
+static int yaffs_soft_del_worker(struct yaffs_obj *in, struct yaffs_tnode *tn,
+				 u32 level, int chunk_offset)
 {
-	static int x = 0;
 	int i;
-	int l = 999;
-	int lowest = 999999;
+	int the_chunk;
+	int all_done = 1;
+	struct yaffs_dev *dev = in->my_dev;
 
-	/* First let's see if we can find one that's empty. */
+	if (!tn)
+		return 1;
 
-	for (i = 0; i < 10 && lowest > 0; i++) {
-		x++;
-		x %= YAFFS_NOBJECT_BUCKETS;
-		if (dev->objectBucket[x].count < lowest) {
-			lowest = dev->objectBucket[x].count;
-			l = x;
+	if (level > 0) {
+		for (i = YAFFS_NTNODES_INTERNAL - 1;
+			all_done && i >= 0;
+			i--) {
+			if (tn->internal[i]) {
+				all_done =
+				    yaffs_soft_del_worker(in,
+					tn->internal[i],
+					level - 1,
+					(chunk_offset <<
+					YAFFS_TNODES_INTERNAL_BITS)
+					+ i);
+				if (all_done) {
+					yaffs_free_tnode(dev,
+						tn->internal[i]);
+					tn->internal[i] = NULL;
+				} else {
+					/* Can this happen? */
+				}
+			}
 		}
-
+		return (all_done) ? 1 : 0;
 	}
 
-	/* If we didn't find an empty list, then try
-	 * looking a bit further for a short one
-	 */
-
-	for (i = 0; i < 10 && lowest > 3; i++) {
-		x++;
-		x %= YAFFS_NOBJECT_BUCKETS;
-		if (dev->objectBucket[x].count < lowest) {
-			lowest = dev->objectBucket[x].count;
-			l = x;
+	/* level 0 */
+	 for (i = YAFFS_NTNODES_LEVEL0 - 1; i >= 0; i--) {
+		the_chunk = yaffs_get_group_base(dev, tn, i);
+		if (the_chunk) {
+			yaffs_soft_del_chunk(dev, the_chunk);
+			yaffs_load_tnode_0(dev, tn, i, 0);
 		}
-
 	}
-
-	return l;
+	return 1;
 }
 
-static int yaffs_CreateNewObjectNumber(yaffs_Device * dev)
+static void yaffs_remove_obj_from_dir(struct yaffs_obj *obj)
 {
-	int bucket = yaffs_FindNiceObjectBucket(dev);
+	struct yaffs_dev *dev = obj->my_dev;
+	struct yaffs_obj *parent;
 
-	/* Now find an object value that has not already been taken
-	 * by scanning the list.
-	 */
+	yaffs_verify_obj_in_dir(obj);
+	parent = obj->parent;
 
-	int found = 0;
-	struct list_head *i;
+	yaffs_verify_dir(parent);
 
-	__u32 n = (__u32) bucket;
-
-	/* yaffs_CheckObjectHashSanity();  */
-
-	while (!found) {
-		found = 1;
-		n += YAFFS_NOBJECT_BUCKETS;
-		if (1 || dev->objectBucket[bucket].count > 0) {
-			list_for_each(i, &dev->objectBucket[bucket].list) {
-				/* If there is already one in the list */
-				if (i
-				    && list_entry(i, yaffs_Object,
-						  hashLink)->objectId == n) {
-					found = 0;
-				}
-			}
-		}
-	}
-
-
-	return n;
-}
-
-static void yaffs_HashObject(yaffs_Object * in)
-{
-	int bucket = yaffs_HashFunction(in->objectId);
-	yaffs_Device *dev = in->myDev;
+	if (dev && dev->param.remove_obj_fn)
+		dev->param.remove_obj_fn(obj);
 
-	list_add(&in->hashLink, &dev->objectBucket[bucket].list);
-	dev->objectBucket[bucket].count++;
+	list_del_init(&obj->siblings);
+	obj->parent = NULL;
 
+	yaffs_verify_dir(parent);
 }
 
-yaffs_Object *yaffs_FindObjectByNumber(yaffs_Device * dev, __u32 number)
+void yaffs_add_obj_to_dir(struct yaffs_obj *directory, struct yaffs_obj *obj)
 {
-	int bucket = yaffs_HashFunction(number);
-	struct list_head *i;
-	yaffs_Object *in;
-
-	list_for_each(i, &dev->objectBucket[bucket].list) {
-		/* Look if it is in the list */
-		if (i) {
-			in = list_entry(i, yaffs_Object, hashLink);
-			if (in->objectId == number) {
-/* XXX U-BOOT XXX */
-#if 0
-#ifdef __KERNEL__
-				/* Don't tell the VFS about this one if it is defered free */
-				if (in->deferedFree)
-					return NULL;
-#endif
-#endif
-				return in;
-			}
-		}
+	if (!directory) {
+		yaffs_trace(YAFFS_TRACE_ALWAYS,
+			"tragedy: Trying to add an object to a null pointer directory"
+			);
+		BUG();
+		return;
 	}
-
-	return NULL;
-}
-
-yaffs_Object *yaffs_CreateNewObject(yaffs_Device * dev, int number,
-				    yaffs_ObjectType type)
-{
-
-	yaffs_Object *theObject;
-	yaffs_Tnode *tn = NULL;
-
-	if (number < 0) {
-		number = yaffs_CreateNewObjectNumber(dev);
+	if (directory->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) {
+		yaffs_trace(YAFFS_TRACE_ALWAYS,
+			"tragedy: Trying to add an object to a non-directory"
+			);
+		BUG();
 	}
 
-	theObject = yaffs_AllocateEmptyObject(dev);
-	if(!theObject)
-		return NULL;
-
-	if(type == YAFFS_OBJECT_TYPE_FILE){
-		tn = yaffs_GetTnode(dev);
-		if(!tn){
-			yaffs_FreeObject(theObject);
-			return NULL;
-		}
+	if (obj->siblings.prev == NULL) {
+		/* Not initialised */
+		BUG();
 	}
 
+	yaffs_verify_dir(directory);
 
+	yaffs_remove_obj_from_dir(obj);
 
-	if (theObject) {
-		theObject->fake = 0;
-		theObject->renameAllowed = 1;
-		theObject->unlinkAllowed = 1;
-		theObject->objectId = number;
-		yaffs_HashObject(theObject);
-		theObject->variantType = type;
-#ifdef CONFIG_YAFFS_WINCE
-		yfsd_WinFileTimeNow(theObject->win_atime);
-		theObject->win_ctime[0] = theObject->win_mtime[0] =
-		    theObject->win_atime[0];
-		theObject->win_ctime[1] = theObject->win_mtime[1] =
-		    theObject->win_atime[1];
-
-#else
+	/* Now add it */
+	list_add(&obj->siblings, &directory->variant.dir_variant.children);
+	obj->parent = directory;
 
-		theObject->yst_atime = theObject->yst_mtime =
-		    theObject->yst_ctime = Y_CURRENT_TIME;
-#endif
-		switch (type) {
-		case YAFFS_OBJECT_TYPE_FILE:
-			theObject->variant.fileVariant.fileSize = 0;
-			theObject->variant.fileVariant.scannedFileSize = 0;
-			theObject->variant.fileVariant.shrinkSize = 0xFFFFFFFF;	/* max __u32 */
-			theObject->variant.fileVariant.topLevel = 0;
-			theObject->variant.fileVariant.top = tn;
-			break;
-		case YAFFS_OBJECT_TYPE_DIRECTORY:
-			INIT_LIST_HEAD(&theObject->variant.directoryVariant.
-				       children);
-			break;
-		case YAFFS_OBJECT_TYPE_SYMLINK:
-		case YAFFS_OBJECT_TYPE_HARDLINK:
-		case YAFFS_OBJECT_TYPE_SPECIAL:
-			/* No action required */
-			break;
-		case YAFFS_OBJECT_TYPE_UNKNOWN:
-			/* todo this should not happen */
-			break;
-		}
+	if (directory == obj->my_dev->unlinked_dir
+	    || directory == obj->my_dev->del_dir) {
+		obj->unlinked = 1;
+		obj->my_dev->n_unlinked_files++;
+		obj->rename_allowed = 0;
 	}
 
-	return theObject;
+	yaffs_verify_dir(directory);
+	yaffs_verify_obj_in_dir(obj);
 }
 
-static yaffs_Object *yaffs_FindOrCreateObjectByNumber(yaffs_Device * dev,
-						      int number,
-						      yaffs_ObjectType type)
+static int yaffs_change_obj_name(struct yaffs_obj *obj,
+				 struct yaffs_obj *new_dir,
+				 const YCHAR *new_name, int force, int shadows)
 {
-	yaffs_Object *theObject = NULL;
+	int unlink_op;
+	int del_op;
+	struct yaffs_obj *existing_target;
 
-	if (number > 0) {
-		theObject = yaffs_FindObjectByNumber(dev, number);
-	}
+	if (new_dir == NULL)
+		new_dir = obj->parent;	/* use the old directory */
 
-	if (!theObject) {
-		theObject = yaffs_CreateNewObject(dev, number, type);
+	if (new_dir->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) {
+		yaffs_trace(YAFFS_TRACE_ALWAYS,
+			"tragedy: yaffs_change_obj_name: new_dir is not a directory"
+			);
+		BUG();
 	}
 
-	return theObject;
+	unlink_op = (new_dir == obj->my_dev->unlinked_dir);
+	del_op = (new_dir == obj->my_dev->del_dir);
 
-}
+	existing_target = yaffs_find_by_name(new_dir, new_name);
 
+	/* If the object is a file going into the unlinked directory,
+	 *   then it is OK to just stuff it in since duplicate names are OK.
+	 *   else only proceed if the new name does not exist and we're putting
+	 *   it into a directory.
+	 */
+	if (!(unlink_op || del_op || force ||
+	      shadows > 0 || !existing_target) ||
+	      new_dir->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY)
+		return YAFFS_FAIL;
 
-static YCHAR *yaffs_CloneString(const YCHAR * str)
-{
-	YCHAR *newStr = NULL;
+	yaffs_set_obj_name(obj, new_name);
+	obj->dirty = 1;
+	yaffs_add_obj_to_dir(new_dir, obj);
 
-	if (str && *str) {
-		newStr = YMALLOC((yaffs_strlen(str) + 1) * sizeof(YCHAR));
-		if(newStr)
-			yaffs_strcpy(newStr, str);
-	}
+	if (unlink_op)
+		obj->unlinked = 1;
 
-	return newStr;
+	/* If it is a deletion then we mark it as a shrink for gc  */
+	if (yaffs_update_oh(obj, new_name, 0, del_op, shadows, NULL) >= 0)
+		return YAFFS_OK;
 
+	return YAFFS_FAIL;
 }
 
-/*
- * Mknod (create) a new object.
- * equivalentObject only has meaning for a hard link;
- * aliasString only has meaning for a sumlink.
- * rdev only has meaning for devices (a subset of special objects)
+/*------------------------ Short Operations Cache ------------------------------
+ *   In many situations where there is no high level buffering  a lot of
+ *   reads might be short sequential reads, and a lot of writes may be short
+ *   sequential writes. eg. scanning/writing a jpeg file.
+ *   In these cases, a short read/write cache can provide a huge perfomance
+ *   benefit with dumb-as-a-rock code.
+ *   In Linux, the page cache provides read buffering and the short op cache
+ *   provides write buffering.
+ *
+ *   There are a small number (~10) of cache chunks per device so that we don't
+ *   need a very intelligent search.
  */
 
-static yaffs_Object *yaffs_MknodObject(yaffs_ObjectType type,
-				       yaffs_Object * parent,
-				       const YCHAR * name,
-				       __u32 mode,
-				       __u32 uid,
-				       __u32 gid,
-				       yaffs_Object * equivalentObject,
-				       const YCHAR * aliasString, __u32 rdev)
+static int yaffs_obj_cache_dirty(struct yaffs_obj *obj)
 {
-	yaffs_Object *in;
-	YCHAR *str = NULL;
-
-	yaffs_Device *dev = parent->myDev;
-
-	/* Check if the entry exists. If it does then fail the call since we don't want a dup.*/
-	if (yaffs_FindObjectByName(parent, name)) {
-		return NULL;
-	}
-
-	in = yaffs_CreateNewObject(dev, -1, type);
+	struct yaffs_dev *dev = obj->my_dev;
+	int i;
+	struct yaffs_cache *cache;
+	int n_caches = obj->my_dev->param.n_caches;
 
-	if(type == YAFFS_OBJECT_TYPE_SYMLINK){
-		str = yaffs_CloneString(aliasString);
-		if(!str){
-			yaffs_FreeObject(in);
-			return NULL;
-		}
+	for (i = 0; i < n_caches; i++) {
+		cache = &dev->cache[i];
+		if (cache->object == obj && cache->dirty)
+			return 1;
 	}
 
+	return 0;
+}
 
+static void yaffs_flush_file_cache(struct yaffs_obj *obj)
+{
+	struct yaffs_dev *dev = obj->my_dev;
+	int lowest = -99;	/* Stop compiler whining. */
+	int i;
+	struct yaffs_cache *cache;
+	int chunk_written = 0;
+	int n_caches = obj->my_dev->param.n_caches;
 
-	if (in) {
-		in->chunkId = -1;
-		in->valid = 1;
-		in->variantType = type;
-
-		in->yst_mode = mode;
-
-#ifdef CONFIG_YAFFS_WINCE
-		yfsd_WinFileTimeNow(in->win_atime);
-		in->win_ctime[0] = in->win_mtime[0] = in->win_atime[0];
-		in->win_ctime[1] = in->win_mtime[1] = in->win_atime[1];
-
-#else
-		in->yst_atime = in->yst_mtime = in->yst_ctime = Y_CURRENT_TIME;
-
-		in->yst_rdev = rdev;
-		in->yst_uid = uid;
-		in->yst_gid = gid;
-#endif
-		in->nDataChunks = 0;
-
-		yaffs_SetObjectName(in, name);
-		in->dirty = 1;
-
-		yaffs_AddObjectToDirectory(parent, in);
-
-		in->myDev = parent->myDev;
-
-		switch (type) {
-		case YAFFS_OBJECT_TYPE_SYMLINK:
-			in->variant.symLinkVariant.alias = str;
-			break;
-		case YAFFS_OBJECT_TYPE_HARDLINK:
-			in->variant.hardLinkVariant.equivalentObject =
-			    equivalentObject;
-			in->variant.hardLinkVariant.equivalentObjectId =
-			    equivalentObject->objectId;
-			list_add(&in->hardLinks, &equivalentObject->hardLinks);
-			break;
-		case YAFFS_OBJECT_TYPE_FILE:
-		case YAFFS_OBJECT_TYPE_DIRECTORY:
-		case YAFFS_OBJECT_TYPE_SPECIAL:
-		case YAFFS_OBJECT_TYPE_UNKNOWN:
-			/* do nothing */
-			break;
+	if (n_caches < 1)
+		return;
+	do {
+		cache = NULL;
+
+		/* Find the lowest dirty chunk for this object */
+		for (i = 0; i < n_caches; i++) {
+			if (dev->cache[i].object == obj &&
+			    dev->cache[i].dirty) {
+				if (!cache ||
+				    dev->cache[i].chunk_id < lowest) {
+					cache = &dev->cache[i];
+					lowest = cache->chunk_id;
+				}
+			}
 		}
 
-		if (yaffs_UpdateObjectHeader(in, name, 0, 0, 0) < 0) {
-			/* Could not create the object header, fail the creation */
-			yaffs_DestroyObject(in);
-			in = NULL;
+		if (cache && !cache->locked) {
+			/* Write it out and free it up */
+			chunk_written =
+			    yaffs_wr_data_obj(cache->object,
+					      cache->chunk_id,
+					      cache->data,
+					      cache->n_bytes, 1);
+			cache->dirty = 0;
+			cache->object = NULL;
 		}
+	} while (cache && chunk_written > 0);
 
-	}
-
-	return in;
+	if (cache)
+		/* Hoosterman, disk full while writing cache out. */
+		yaffs_trace(YAFFS_TRACE_ERROR,
+			"yaffs tragedy: no space during cache write");
 }
 
-yaffs_Object *yaffs_MknodFile(yaffs_Object * parent, const YCHAR * name,
-			      __u32 mode, __u32 uid, __u32 gid)
-{
-	return yaffs_MknodObject(YAFFS_OBJECT_TYPE_FILE, parent, name, mode,
-				 uid, gid, NULL, NULL, 0);
-}
+/*yaffs_flush_whole_cache(dev)
+ *
+ *
+ */
 
-yaffs_Object *yaffs_MknodDirectory(yaffs_Object * parent, const YCHAR * name,
-				   __u32 mode, __u32 uid, __u32 gid)
+void yaffs_flush_whole_cache(struct yaffs_dev *dev)
 {
-	return yaffs_MknodObject(YAFFS_OBJECT_TYPE_DIRECTORY, parent, name,
-				 mode, uid, gid, NULL, NULL, 0);
-}
+	struct yaffs_obj *obj;
+	int n_caches = dev->param.n_caches;
+	int i;
 
-yaffs_Object *yaffs_MknodSpecial(yaffs_Object * parent, const YCHAR * name,
-				 __u32 mode, __u32 uid, __u32 gid, __u32 rdev)
-{
-	return yaffs_MknodObject(YAFFS_OBJECT_TYPE_SPECIAL, parent, name, mode,
-				 uid, gid, NULL, NULL, rdev);
-}
+	/* Find a dirty object in the cache and flush it...
+	 * until there are no further dirty objects.
+	 */
+	do {
+		obj = NULL;
+		for (i = 0; i < n_caches && !obj; i++) {
+			if (dev->cache[i].object && dev->cache[i].dirty)
+				obj = dev->cache[i].object;
+		}
+		if (obj)
+			yaffs_flush_file_cache(obj);
+	} while (obj);
 
-yaffs_Object *yaffs_MknodSymLink(yaffs_Object * parent, const YCHAR * name,
-				 __u32 mode, __u32 uid, __u32 gid,
-				 const YCHAR * alias)
-{
-	return yaffs_MknodObject(YAFFS_OBJECT_TYPE_SYMLINK, parent, name, mode,
-				 uid, gid, NULL, alias, 0);
 }
 
-/* yaffs_Link returns the object id of the equivalent object.*/
-yaffs_Object *yaffs_Link(yaffs_Object * parent, const YCHAR * name,
-			 yaffs_Object * equivalentObject)
+/* Grab us a cache chunk for use.
+ * First look for an empty one.
+ * Then look for the least recently used non-dirty one.
+ * Then look for the least recently used dirty one...., flush and look again.
+ */
+static struct yaffs_cache *yaffs_grab_chunk_worker(struct yaffs_dev *dev)
 {
-	/* Get the real object in case we were fed a hard link as an equivalent object */
-	equivalentObject = yaffs_GetEquivalentObject(equivalentObject);
+	int i;
 
-	if (yaffs_MknodObject
-	    (YAFFS_OBJECT_TYPE_HARDLINK, parent, name, 0, 0, 0,
-	     equivalentObject, NULL, 0)) {
-		return equivalentObject;
-	} else {
-		return NULL;
+	if (dev->param.n_caches > 0) {
+		for (i = 0; i < dev->param.n_caches; i++) {
+			if (!dev->cache[i].object)
+				return &dev->cache[i];
+		}
 	}
-
+	return NULL;
 }
 
-static int yaffs_ChangeObjectName(yaffs_Object * obj, yaffs_Object * newDir,
-				  const YCHAR * newName, int force, int shadows)
+static struct yaffs_cache *yaffs_grab_chunk_cache(struct yaffs_dev *dev)
 {
-	int unlinkOp;
-	int deleteOp;
-
-	yaffs_Object *existingTarget;
-
-	if (newDir == NULL) {
-		newDir = obj->parent;	/* use the old directory */
-	}
-
-	if (newDir->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) {
-		T(YAFFS_TRACE_ALWAYS,
-		  (TSTR
-		   ("tragendy: yaffs_ChangeObjectName: newDir is not a directory"
-		    TENDSTR)));
-		YBUG();
-	}
-
-	/* TODO: Do we need this different handling for YAFFS2 and YAFFS1?? */
-	if (obj->myDev->isYaffs2) {
-		unlinkOp = (newDir == obj->myDev->unlinkedDir);
-	} else {
-		unlinkOp = (newDir == obj->myDev->unlinkedDir
-			    && obj->variantType == YAFFS_OBJECT_TYPE_FILE);
-	}
+	struct yaffs_cache *cache;
+	struct yaffs_obj *the_obj;
+	int usage;
+	int i;
 
-	deleteOp = (newDir == obj->myDev->deletedDir);
+	if (dev->param.n_caches < 1)
+		return NULL;
 
-	existingTarget = yaffs_FindObjectByName(newDir, newName);
+	/* Try find a non-dirty one... */
 
-	/* If the object is a file going into the unlinked directory,
-	 *   then it is OK to just stuff it in since duplicate names are allowed.
-	 *   else only proceed if the new name does not exist and if we're putting
-	 *   it into a directory.
-	 */
-	if ((unlinkOp ||
-	     deleteOp ||
-	     force ||
-	     (shadows > 0) ||
-	     !existingTarget) &&
-	    newDir->variantType == YAFFS_OBJECT_TYPE_DIRECTORY) {
-		yaffs_SetObjectName(obj, newName);
-		obj->dirty = 1;
+	cache = yaffs_grab_chunk_worker(dev);
 
-		yaffs_AddObjectToDirectory(newDir, obj);
+	if (!cache) {
+		/* They were all dirty, find the LRU object and flush
+		 * its cache, then  find again.
+		 * NB what's here is not very accurate,
+		 * we actually flush the object with the LRU chunk.
+		 */
 
-		if (unlinkOp)
-			obj->unlinked = 1;
+		/* With locking we can't assume we can use entry zero,
+		 * Set the_obj to a valid pointer for Coverity. */
+		the_obj = dev->cache[0].object;
+		usage = -1;
+		cache = NULL;
+
+		for (i = 0; i < dev->param.n_caches; i++) {
+			if (dev->cache[i].object &&
+			    !dev->cache[i].locked &&
+			    (dev->cache[i].last_use < usage ||
+			    !cache)) {
+				usage = dev->cache[i].last_use;
+				the_obj = dev->cache[i].object;
+				cache = &dev->cache[i];
+			}
+		}
 
-		/* If it is a deletion then we mark it as a shrink for gc purposes. */
-		if (yaffs_UpdateObjectHeader(obj, newName, 0, deleteOp, shadows)>= 0)
-			return YAFFS_OK;
+		if (!cache || cache->dirty) {
+			/* Flush and try again */
+			yaffs_flush_file_cache(the_obj);
+			cache = yaffs_grab_chunk_worker(dev);
+		}
 	}
-
-	return YAFFS_FAIL;
+	return cache;
 }
 
-int yaffs_RenameObject(yaffs_Object * oldDir, const YCHAR * oldName,
-		       yaffs_Object * newDir, const YCHAR * newName)
+/* Find a cached chunk */
+static struct yaffs_cache *yaffs_find_chunk_cache(const struct yaffs_obj *obj,
+						  int chunk_id)
 {
-	yaffs_Object *obj;
-	yaffs_Object *existingTarget;
-	int force = 0;
+	struct yaffs_dev *dev = obj->my_dev;
+	int i;
 
-#ifdef CONFIG_YAFFS_CASE_INSENSITIVE
-	/* Special case for case insemsitive systems (eg. WinCE).
-	 * While look-up is case insensitive, the name isn't.
-	 * Therefore we might want to change x.txt to X.txt
-	*/
-	if (oldDir == newDir && yaffs_strcmp(oldName, newName) == 0) {
-		force = 1;
-	}
-#endif
+	if (dev->param.n_caches < 1)
+		return NULL;
 
-	obj = yaffs_FindObjectByName(oldDir, oldName);
-	/* Check new name to long. */
-	if (obj->variantType == YAFFS_OBJECT_TYPE_SYMLINK &&
-	    yaffs_strlen(newName) > YAFFS_MAX_ALIAS_LENGTH)
-	  /* ENAMETOOLONG */
-	  return YAFFS_FAIL;
-	else if (obj->variantType != YAFFS_OBJECT_TYPE_SYMLINK &&
-		 yaffs_strlen(newName) > YAFFS_MAX_NAME_LENGTH)
-	  /* ENAMETOOLONG */
-	  return YAFFS_FAIL;
-
-	if (obj && obj->renameAllowed) {
-
-		/* Now do the handling for an existing target, if there is one */
-
-		existingTarget = yaffs_FindObjectByName(newDir, newName);
-		if (existingTarget &&
-		    existingTarget->variantType == YAFFS_OBJECT_TYPE_DIRECTORY &&
-		    !list_empty(&existingTarget->variant.directoryVariant.children)) {
-			/* There is a target that is a non-empty directory, so we fail */
-			return YAFFS_FAIL;	/* EEXIST or ENOTEMPTY */
-		} else if (existingTarget && existingTarget != obj) {
-			/* Nuke the target first, using shadowing,
-			 * but only if it isn't the same object
-			 */
-			yaffs_ChangeObjectName(obj, newDir, newName, force,
-					       existingTarget->objectId);
-			yaffs_UnlinkObject(existingTarget);
-		}
+	for (i = 0; i < dev->param.n_caches; i++) {
+		if (dev->cache[i].object == obj &&
+		    dev->cache[i].chunk_id == chunk_id) {
+			dev->cache_hits++;
 
-		return yaffs_ChangeObjectName(obj, newDir, newName, 1, 0);
+			return &dev->cache[i];
+		}
 	}
-	return YAFFS_FAIL;
+	return NULL;
 }
 
-/*------------------------- Block Management and Page Allocation ----------------*/
-
-static int yaffs_InitialiseBlocks(yaffs_Device * dev)
+/* Mark the chunk for the least recently used algorithym */
+static void yaffs_use_cache(struct yaffs_dev *dev, struct yaffs_cache *cache,
+			    int is_write)
 {
-	int nBlocks = dev->internalEndBlock - dev->internalStartBlock + 1;
-
-	dev->blockInfo = NULL;
-	dev->chunkBits = NULL;
-
-	dev->allocationBlock = -1;	/* force it to get a new one */
-
-	/* If the first allocation strategy fails, thry the alternate one */
-	dev->blockInfo = YMALLOC(nBlocks * sizeof(yaffs_BlockInfo));
-	if(!dev->blockInfo){
-		dev->blockInfo = YMALLOC_ALT(nBlocks * sizeof(yaffs_BlockInfo));
-		dev->blockInfoAlt = 1;
-	}
-	else
-		dev->blockInfoAlt = 0;
+	int i;
 
-	if(dev->blockInfo){
+	if (dev->param.n_caches < 1)
+		return;
 
-		/* Set up dynamic blockinfo stuff. */
-		dev->chunkBitmapStride = (dev->nChunksPerBlock + 7) / 8; /* round up bytes */
-		dev->chunkBits = YMALLOC(dev->chunkBitmapStride * nBlocks);
-		if(!dev->chunkBits){
-			dev->chunkBits = YMALLOC_ALT(dev->chunkBitmapStride * nBlocks);
-			dev->chunkBitsAlt = 1;
-		}
-		else
-			dev->chunkBitsAlt = 0;
-	}
+	if (dev->cache_last_use < 0 ||
+		dev->cache_last_use > 100000000) {
+		/* Reset the cache usages */
+		for (i = 1; i < dev->param.n_caches; i++)
+			dev->cache[i].last_use = 0;
 
-	if (dev->blockInfo && dev->chunkBits) {
-		memset(dev->blockInfo, 0, nBlocks * sizeof(yaffs_BlockInfo));
-		memset(dev->chunkBits, 0, dev->chunkBitmapStride * nBlocks);
-		return YAFFS_OK;
+		dev->cache_last_use = 0;
 	}
+	dev->cache_last_use++;
+	cache->last_use = dev->cache_last_use;
 
-	return YAFFS_FAIL;
-
+	if (is_write)
+		cache->dirty = 1;
 }
 
-static void yaffs_DeinitialiseBlocks(yaffs_Device * dev)
+/* Invalidate a single cache page.
+ * Do this when a whole page gets written,
+ * ie the short cache for this page is no longer valid.
+ */
+static void yaffs_invalidate_chunk_cache(struct yaffs_obj *object, int chunk_id)
 {
-	if(dev->blockInfoAlt && dev->blockInfo)
-		YFREE_ALT(dev->blockInfo);
-	else if(dev->blockInfo)
-		YFREE(dev->blockInfo);
-
-	dev->blockInfoAlt = 0;
+	struct yaffs_cache *cache;
 
-	dev->blockInfo = NULL;
+	if (object->my_dev->param.n_caches > 0) {
+		cache = yaffs_find_chunk_cache(object, chunk_id);
 
-	if(dev->chunkBitsAlt && dev->chunkBits)
-		YFREE_ALT(dev->chunkBits);
-	else if(dev->chunkBits)
-		YFREE(dev->chunkBits);
-	dev->chunkBitsAlt = 0;
-	dev->chunkBits = NULL;
+		if (cache)
+			cache->object = NULL;
+	}
 }
 
-static int yaffs_BlockNotDisqualifiedFromGC(yaffs_Device * dev,
-					    yaffs_BlockInfo * bi)
+/* Invalidate all the cache pages associated with this object
+ * Do this whenever ther file is deleted or resized.
+ */
+static void yaffs_invalidate_whole_cache(struct yaffs_obj *in)
 {
 	int i;
-	__u32 seq;
-	yaffs_BlockInfo *b;
-
-	if (!dev->isYaffs2)
-		return 1;	/* disqualification only applies to yaffs2. */
+	struct yaffs_dev *dev = in->my_dev;
 
-	if (!bi->hasShrinkHeader)
-		return 1;	/* can gc */
-
-	/* Find the oldest dirty sequence number if we don't know it and save it
-	 * so we don't have to keep recomputing it.
-	 */
-	if (!dev->oldestDirtySequence) {
-		seq = dev->sequenceNumber;
-
-		for (i = dev->internalStartBlock; i <= dev->internalEndBlock;
-		     i++) {
-			b = yaffs_GetBlockInfo(dev, i);
-			if (b->blockState == YAFFS_BLOCK_STATE_FULL &&
-			    (b->pagesInUse - b->softDeletions) <
-			    dev->nChunksPerBlock && b->sequenceNumber < seq) {
-				seq = b->sequenceNumber;
-			}
+	if (dev->param.n_caches > 0) {
+		/* Invalidate it. */
+		for (i = 0; i < dev->param.n_caches; i++) {
+			if (dev->cache[i].object == in)
+				dev->cache[i].object = NULL;
 		}
-		dev->oldestDirtySequence = seq;
 	}
-
-	/* Can't do gc of this block if there are any blocks older than this one that have
-	 * discarded pages.
-	 */
-	return (bi->sequenceNumber <= dev->oldestDirtySequence);
-
 }
 
-/* FindDiretiestBlock is used to select the dirtiest block (or close enough)
- * for garbage collection.
- */
-
-static int yaffs_FindBlockForGarbageCollection(yaffs_Device * dev,
-					       int aggressive)
+static void yaffs_unhash_obj(struct yaffs_obj *obj)
 {
+	int bucket;
+	struct yaffs_dev *dev = obj->my_dev;
 
-	int b = dev->currentDirtyChecker;
-
-	int i;
-	int iterations;
-	int dirtiest = -1;
-	int pagesInUse = 0;
-	int prioritised=0;
-	yaffs_BlockInfo *bi;
-	int pendingPrioritisedExist = 0;
-
-	/* First let's see if we need to grab a prioritised block */
-	if(dev->hasPendingPrioritisedGCs){
-		for(i = dev->internalStartBlock; i < dev->internalEndBlock && !prioritised; i++){
-
-			bi = yaffs_GetBlockInfo(dev, i);
-			//yaffs_VerifyBlock(dev,bi,i);
-
-			if(bi->gcPrioritise) {
-				pendingPrioritisedExist = 1;
-				if(bi->blockState == YAFFS_BLOCK_STATE_FULL &&
-				   yaffs_BlockNotDisqualifiedFromGC(dev, bi)){
-					pagesInUse = (bi->pagesInUse - bi->softDeletions);
-					dirtiest = i;
-					prioritised = 1;
-					aggressive = 1; /* Fool the non-aggressive skip logiv below */
-				}
-			}
-		}
-
-		if(!pendingPrioritisedExist) /* None found, so we can clear this */
-			dev->hasPendingPrioritisedGCs = 0;
+	/* If it is still linked into the bucket list, free from the list */
+	if (!list_empty(&obj->hash_link)) {
+		list_del_init(&obj->hash_link);
+		bucket = yaffs_hash_fn(obj->obj_id);
+		dev->obj_bucket[bucket].count--;
 	}
+}
 
-	/* If we're doing aggressive GC then we are happy to take a less-dirty block, and
-	 * search harder.
-	 * else (we're doing a leasurely gc), then we only bother to do this if the
-	 * block has only a few pages in use.
-	 */
-
-	dev->nonAggressiveSkip--;
+/*  FreeObject frees up a Object and puts it back on the free list */
+static void yaffs_free_obj(struct yaffs_obj *obj)
+{
+	struct yaffs_dev *dev;
 
-	if (!aggressive && (dev->nonAggressiveSkip > 0)) {
-		return -1;
+	if (!obj) {
+		BUG();
+		return;
 	}
+	dev = obj->my_dev;
+	yaffs_trace(YAFFS_TRACE_OS, "FreeObject %p inode %p",
+		obj, obj->my_inode);
+	if (obj->parent)
+		BUG();
+	if (!list_empty(&obj->siblings))
+		BUG();
 
-	if(!prioritised)
-		pagesInUse =
-			(aggressive) ? dev->nChunksPerBlock : YAFFS_PASSIVE_GC_CHUNKS + 1;
-
-	if (aggressive) {
-		iterations =
-		    dev->internalEndBlock - dev->internalStartBlock + 1;
-	} else {
-		iterations =
-		    dev->internalEndBlock - dev->internalStartBlock + 1;
-		iterations = iterations / 16;
-		if (iterations > 200) {
-			iterations = 200;
-		}
+	if (obj->my_inode) {
+		/* We're still hooked up to a cached inode.
+		 * Don't delete now, but mark for later deletion
+		 */
+		obj->defered_free = 1;
+		return;
 	}
 
-	for (i = 0; i <= iterations && pagesInUse > 0 && !prioritised; i++) {
-		b++;
-		if (b < dev->internalStartBlock || b > dev->internalEndBlock) {
-			b = dev->internalStartBlock;
-		}
+	yaffs_unhash_obj(obj);
 
-		if (b < dev->internalStartBlock || b > dev->internalEndBlock) {
-			T(YAFFS_TRACE_ERROR,
-			  (TSTR("**>> Block %d is not valid" TENDSTR), b));
-			YBUG();
-		}
+	yaffs_free_raw_obj(dev, obj);
+	dev->n_obj--;
+	dev->checkpoint_blocks_required = 0;	/* force recalculation */
+}
 
-		bi = yaffs_GetBlockInfo(dev, b);
+void yaffs_handle_defered_free(struct yaffs_obj *obj)
+{
+	if (obj->defered_free)
+		yaffs_free_obj(obj);
+}
 
-#if 0
-		if (bi->blockState == YAFFS_BLOCK_STATE_CHECKPOINT) {
-			dirtiest = b;
-			pagesInUse = 0;
-		}
-		else
-#endif
+static int yaffs_generic_obj_del(struct yaffs_obj *in)
+{
+	/* Iinvalidate the file's data in the cache, without flushing. */
+	yaffs_invalidate_whole_cache(in);
 
-		if (bi->blockState == YAFFS_BLOCK_STATE_FULL &&
-		       (bi->pagesInUse - bi->softDeletions) < pagesInUse &&
-			yaffs_BlockNotDisqualifiedFromGC(dev, bi)) {
-			dirtiest = b;
-			pagesInUse = (bi->pagesInUse - bi->softDeletions);
-		}
+	if (in->my_dev->param.is_yaffs2 && in->parent != in->my_dev->del_dir) {
+		/* Move to unlinked directory so we have a deletion record */
+		yaffs_change_obj_name(in, in->my_dev->del_dir, _Y("deleted"), 0,
+				      0);
 	}
 
-	dev->currentDirtyChecker = b;
+	yaffs_remove_obj_from_dir(in);
+	yaffs_chunk_del(in->my_dev, in->hdr_chunk, 1, __LINE__);
+	in->hdr_chunk = 0;
 
-	if (dirtiest > 0) {
-		T(YAFFS_TRACE_GC,
-		  (TSTR("GC Selected block %d with %d free, prioritised:%d" TENDSTR), dirtiest,
-		   dev->nChunksPerBlock - pagesInUse,prioritised));
-	}
+	yaffs_free_obj(in);
+	return YAFFS_OK;
 
-	dev->oldestDirtySequence = 0;
+}
 
-	if (dirtiest > 0) {
-		dev->nonAggressiveSkip = 4;
-	}
+static void yaffs_soft_del_file(struct yaffs_obj *obj)
+{
+	if (!obj->deleted ||
+	    obj->variant_type != YAFFS_OBJECT_TYPE_FILE ||
+	    obj->soft_del)
+		return;
 
-	return dirtiest;
+	if (obj->n_data_chunks <= 0) {
+		/* Empty file with no duplicate object headers,
+		 * just delete it immediately */
+		yaffs_free_tnode(obj->my_dev, obj->variant.file_variant.top);
+		obj->variant.file_variant.top = NULL;
+		yaffs_trace(YAFFS_TRACE_TRACING,
+			"yaffs: Deleting empty file %d",
+			obj->obj_id);
+		yaffs_generic_obj_del(obj);
+	} else {
+		yaffs_soft_del_worker(obj,
+				      obj->variant.file_variant.top,
+				      obj->variant.
+				      file_variant.top_level, 0);
+		obj->soft_del = 1;
+	}
 }
 
-static void yaffs_BlockBecameDirty(yaffs_Device * dev, int blockNo)
-{
-	yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, blockNo);
+/* Pruning removes any part of the file structure tree that is beyond the
+ * bounds of the file (ie that does not point to chunks).
+ *
+ * A file should only get pruned when its size is reduced.
+ *
+ * Before pruning, the chunks must be pulled from the tree and the
+ * level 0 tnode entries must be zeroed out.
+ * Could also use this for file deletion, but that's probably better handled
+ * by a special case.
+ *
+ * This function is recursive. For levels > 0 the function is called again on
+ * any sub-tree. For level == 0 we just check if the sub-tree has data.
+ * If there is no data in a subtree then it is pruned.
+ */
 
-	int erasedOk = 0;
+static struct yaffs_tnode *yaffs_prune_worker(struct yaffs_dev *dev,
+					      struct yaffs_tnode *tn, u32 level,
+					      int del0)
+{
+	int i;
+	int has_data;
 
-	/* If the block is still healthy erase it and mark as clean.
-	 * If the block has had a data failure, then retire it.
-	 */
+	if (!tn)
+		return tn;
 
-	T(YAFFS_TRACE_GC | YAFFS_TRACE_ERASE,
-		(TSTR("yaffs_BlockBecameDirty block %d state %d %s"TENDSTR),
-		blockNo, bi->blockState, (bi->needsRetiring) ? "needs retiring" : ""));
+	has_data = 0;
 
-	bi->blockState = YAFFS_BLOCK_STATE_DIRTY;
+	if (level > 0) {
+		for (i = 0; i < YAFFS_NTNODES_INTERNAL; i++) {
+			if (tn->internal[i]) {
+				tn->internal[i] =
+				    yaffs_prune_worker(dev,
+						tn->internal[i],
+						level - 1,
+						(i == 0) ? del0 : 1);
+			}
 
-	if (!bi->needsRetiring) {
-		yaffs_InvalidateCheckpoint(dev);
-		erasedOk = yaffs_EraseBlockInNAND(dev, blockNo);
-		if (!erasedOk) {
-			dev->nErasureFailures++;
-			T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS,
-			  (TSTR("**>> Erasure failed %d" TENDSTR), blockNo));
+			if (tn->internal[i])
+				has_data++;
 		}
-	}
+	} else {
+		int tnode_size_u32 = dev->tnode_size / sizeof(u32);
+		u32 *map = (u32 *) tn;
 
-	if (erasedOk &&
-	    ((yaffs_traceMask & YAFFS_TRACE_ERASE) || !yaffs_SkipVerification(dev))) {
-		int i;
-		for (i = 0; i < dev->nChunksPerBlock; i++) {
-			if (!yaffs_CheckChunkErased
-			    (dev, blockNo * dev->nChunksPerBlock + i)) {
-				T(YAFFS_TRACE_ERROR,
-				  (TSTR
-				   (">>Block %d erasure supposedly OK, but chunk %d not erased"
-				    TENDSTR), blockNo, i));
-			}
+		for (i = 0; !has_data && i < tnode_size_u32; i++) {
+			if (map[i])
+				has_data++;
 		}
 	}
 
-	if (erasedOk) {
-		/* Clean it up... */
-		bi->blockState = YAFFS_BLOCK_STATE_EMPTY;
-		dev->nErasedBlocks++;
-		bi->pagesInUse = 0;
-		bi->softDeletions = 0;
-		bi->hasShrinkHeader = 0;
-		bi->skipErasedCheck = 1;  /* This is clean, so no need to check */
-		bi->gcPrioritise = 0;
-		yaffs_ClearChunkBits(dev, blockNo);
-
-		T(YAFFS_TRACE_ERASE,
-		  (TSTR("Erased block %d" TENDSTR), blockNo));
-	} else {
-		dev->nFreeChunks -= dev->nChunksPerBlock;	/* We lost a block of free space */
-
-		yaffs_RetireBlock(dev, blockNo);
-		T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS,
-		  (TSTR("**>> Block %d retired" TENDSTR), blockNo));
+	if (has_data == 0 && del0) {
+		/* Free and return NULL */
+		yaffs_free_tnode(dev, tn);
+		tn = NULL;
 	}
+	return tn;
 }
 
-static int yaffs_FindBlockForAllocation(yaffs_Device * dev)
+static int yaffs_prune_tree(struct yaffs_dev *dev,
+			    struct yaffs_file_var *file_struct)
 {
 	int i;
+	int has_data;
+	int done = 0;
+	struct yaffs_tnode *tn;
 
-	yaffs_BlockInfo *bi;
+	if (file_struct->top_level < 1)
+		return YAFFS_OK;
 
-	if (dev->nErasedBlocks < 1) {
-		/* Hoosterman we've got a problem.
-		 * Can't get space to gc
-		 */
-		T(YAFFS_TRACE_ERROR,
-		  (TSTR("yaffs tragedy: no more eraased blocks" TENDSTR)));
+	file_struct->top =
+	   yaffs_prune_worker(dev, file_struct->top, file_struct->top_level, 0);
 
-		return -1;
-	}
+	/* Now we have a tree with all the non-zero branches NULL but
+	 * the height is the same as it was.
+	 * Let's see if we can trim internal tnodes to shorten the tree.
+	 * We can do this if only the 0th element in the tnode is in use
+	 * (ie all the non-zero are NULL)
+	 */
 
-	/* Find an empty block. */
+	while (file_struct->top_level && !done) {
+		tn = file_struct->top;
 
-	for (i = dev->internalStartBlock; i <= dev->internalEndBlock; i++) {
-		dev->allocationBlockFinder++;
-		if (dev->allocationBlockFinder < dev->internalStartBlock
-		    || dev->allocationBlockFinder > dev->internalEndBlock) {
-			dev->allocationBlockFinder = dev->internalStartBlock;
+		has_data = 0;
+		for (i = 1; i < YAFFS_NTNODES_INTERNAL; i++) {
+			if (tn->internal[i])
+				has_data++;
 		}
 
-		bi = yaffs_GetBlockInfo(dev, dev->allocationBlockFinder);
-
-		if (bi->blockState == YAFFS_BLOCK_STATE_EMPTY) {
-			bi->blockState = YAFFS_BLOCK_STATE_ALLOCATING;
-			dev->sequenceNumber++;
-			bi->sequenceNumber = dev->sequenceNumber;
-			dev->nErasedBlocks--;
-			T(YAFFS_TRACE_ALLOCATE,
-			  (TSTR("Allocated block %d, seq  %d, %d left" TENDSTR),
-			   dev->allocationBlockFinder, dev->sequenceNumber,
-			   dev->nErasedBlocks));
-			return dev->allocationBlockFinder;
+		if (!has_data) {
+			file_struct->top = tn->internal[0];
+			file_struct->top_level--;
+			yaffs_free_tnode(dev, tn);
+		} else {
+			done = 1;
 		}
 	}
 
-	T(YAFFS_TRACE_ALWAYS,
-	  (TSTR
-	   ("yaffs tragedy: no more eraased blocks, but there should have been %d"
-	    TENDSTR), dev->nErasedBlocks));
-
-	return -1;
+	return YAFFS_OK;
 }
 
+/*-------------------- End of File Structure functions.-------------------*/
 
-// Check if there's space to allocate...
-// Thinks.... do we need top make this ths same as yaffs_GetFreeChunks()?
-static int yaffs_CheckSpaceForAllocation(yaffs_Device * dev)
+/* alloc_empty_obj gets us a clean Object.*/
+static struct yaffs_obj *yaffs_alloc_empty_obj(struct yaffs_dev *dev)
 {
-	int reservedChunks;
-	int reservedBlocks = dev->nReservedBlocks;
-	int checkpointBlocks;
+	struct yaffs_obj *obj = yaffs_alloc_raw_obj(dev);
 
-	checkpointBlocks =  dev->nCheckpointReservedBlocks - dev->blocksInCheckpoint;
-	if(checkpointBlocks < 0)
-		checkpointBlocks = 0;
+	if (!obj)
+		return obj;
 
-	reservedChunks = ((reservedBlocks + checkpointBlocks) * dev->nChunksPerBlock);
+	dev->n_obj++;
 
-	return (dev->nFreeChunks > reservedChunks);
-}
+	/* Now sweeten it up... */
 
-static int yaffs_AllocateChunk(yaffs_Device * dev, int useReserve, yaffs_BlockInfo **blockUsedPtr)
-{
-	int retVal;
-	yaffs_BlockInfo *bi;
+	memset(obj, 0, sizeof(struct yaffs_obj));
+	obj->being_created = 1;
 
-	if (dev->allocationBlock < 0) {
-		/* Get next block to allocate off */
-		dev->allocationBlock = yaffs_FindBlockForAllocation(dev);
-		dev->allocationPage = 0;
-	}
+	obj->my_dev = dev;
+	obj->hdr_chunk = 0;
+	obj->variant_type = YAFFS_OBJECT_TYPE_UNKNOWN;
+	INIT_LIST_HEAD(&(obj->hard_links));
+	INIT_LIST_HEAD(&(obj->hash_link));
+	INIT_LIST_HEAD(&obj->siblings);
 
-	if (!useReserve && !yaffs_CheckSpaceForAllocation(dev)) {
-		/* Not enough space to allocate unless we're allowed to use the reserve. */
-		return -1;
+	/* Now make the directory sane */
+	if (dev->root_dir) {
+		obj->parent = dev->root_dir;
+		list_add(&(obj->siblings),
+			 &dev->root_dir->variant.dir_variant.children);
 	}
 
-	if (dev->nErasedBlocks < dev->nReservedBlocks
-	    && dev->allocationPage == 0) {
-		T(YAFFS_TRACE_ALLOCATE, (TSTR("Allocating reserve" TENDSTR)));
-	}
-
-	/* Next page please.... */
-	if (dev->allocationBlock >= 0) {
-		bi = yaffs_GetBlockInfo(dev, dev->allocationBlock);
-
-		retVal = (dev->allocationBlock * dev->nChunksPerBlock) +
-		    dev->allocationPage;
-		bi->pagesInUse++;
-		yaffs_SetChunkBit(dev, dev->allocationBlock,
-				  dev->allocationPage);
-
-		dev->allocationPage++;
-
-		dev->nFreeChunks--;
-
-		/* If the block is full set the state to full */
-		if (dev->allocationPage >= dev->nChunksPerBlock) {
-			bi->blockState = YAFFS_BLOCK_STATE_FULL;
-			dev->allocationBlock = -1;
-		}
-
-		if(blockUsedPtr)
-			*blockUsedPtr = bi;
+	/* Add it to the lost and found directory.
+	 * NB Can't put root or lost-n-found in lost-n-found so
+	 * check if lost-n-found exists first
+	 */
+	if (dev->lost_n_found)
+		yaffs_add_obj_to_dir(dev->lost_n_found, obj);
 
-		return retVal;
-	}
+	obj->being_created = 0;
 
-	T(YAFFS_TRACE_ERROR,
-	  (TSTR("!!!!!!!!! Allocator out !!!!!!!!!!!!!!!!!" TENDSTR)));
+	dev->checkpoint_blocks_required = 0;	/* force recalculation */
 
-	return -1;
+	return obj;
 }
 
-static int yaffs_GetErasedChunks(yaffs_Device * dev)
+static int yaffs_find_nice_bucket(struct yaffs_dev *dev)
 {
-	int n;
+	int i;
+	int l = 999;
+	int lowest = 999999;
 
-	n = dev->nErasedBlocks * dev->nChunksPerBlock;
+	/* Search for the shortest list or one that
+	 * isn't too long.
+	 */
 
-	if (dev->allocationBlock > 0) {
-		n += (dev->nChunksPerBlock - dev->allocationPage);
+	for (i = 0; i < 10 && lowest > 4; i++) {
+		dev->bucket_finder++;
+		dev->bucket_finder %= YAFFS_NOBJECT_BUCKETS;
+		if (dev->obj_bucket[dev->bucket_finder].count < lowest) {
+			lowest = dev->obj_bucket[dev->bucket_finder].count;
+			l = dev->bucket_finder;
+		}
 	}
 
-	return n;
-
+	return l;
 }
 
-static int yaffs_GarbageCollectBlock(yaffs_Device * dev, int block)
+static int yaffs_new_obj_id(struct yaffs_dev *dev)
 {
-	int oldChunk;
-	int newChunk;
-	int chunkInBlock;
-	int markNAND;
-	int retVal = YAFFS_OK;
-	int cleanups = 0;
-	int i;
-	int isCheckpointBlock;
-	int matchingChunk;
-
-	int chunksBefore = yaffs_GetErasedChunks(dev);
-	int chunksAfter;
-
-	yaffs_ExtendedTags tags;
-
-	yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, block);
-
-	yaffs_Object *object;
-
-	isCheckpointBlock = (bi->blockState == YAFFS_BLOCK_STATE_CHECKPOINT);
-
-	bi->blockState = YAFFS_BLOCK_STATE_COLLECTING;
-
-	T(YAFFS_TRACE_TRACING,
-	  (TSTR("Collecting block %d, in use %d, shrink %d, " TENDSTR), block,
-	   bi->pagesInUse, bi->hasShrinkHeader));
-
-	/*yaffs_VerifyFreeChunks(dev); */
-
-	bi->hasShrinkHeader = 0;	/* clear the flag so that the block can erase */
+	int bucket = yaffs_find_nice_bucket(dev);
+	int found = 0;
+	struct list_head *i;
+	u32 n = (u32) bucket;
 
-	/* Take off the number of soft deleted entries because
-	 * they're going to get really deleted during GC.
+	/* Now find an object value that has not already been taken
+	 * by scanning the list.
 	 */
-	dev->nFreeChunks -= bi->softDeletions;
-
-	dev->isDoingGC = 1;
-
-	if (isCheckpointBlock ||
-	    !yaffs_StillSomeChunkBits(dev, block)) {
-		T(YAFFS_TRACE_TRACING,
-		  (TSTR
-		   ("Collecting block %d that has no chunks in use" TENDSTR),
-		   block));
-		yaffs_BlockBecameDirty(dev, block);
-	} else {
-
-		__u8 *buffer = yaffs_GetTempBuffer(dev, __LINE__);
-
-		yaffs_VerifyBlock(dev,bi,block);
-
-		for (chunkInBlock = 0, oldChunk = block * dev->nChunksPerBlock;
-		     chunkInBlock < dev->nChunksPerBlock
-		     && yaffs_StillSomeChunkBits(dev, block);
-		     chunkInBlock++, oldChunk++) {
-			if (yaffs_CheckChunkBit(dev, block, chunkInBlock)) {
-
-				/* This page is in use and might need to be copied off */
-
-				markNAND = 1;
-
-				yaffs_InitialiseTags(&tags);
-
-				yaffs_ReadChunkWithTagsFromNAND(dev, oldChunk,
-								buffer, &tags);
-
-				object =
-				    yaffs_FindObjectByNumber(dev,
-							     tags.objectId);
-
-				T(YAFFS_TRACE_GC_DETAIL,
-				  (TSTR
-				   ("Collecting page %d, %d %d %d " TENDSTR),
-				   chunkInBlock, tags.objectId, tags.chunkId,
-				   tags.byteCount));
-
-				if(object && !yaffs_SkipVerification(dev)){
-					if(tags.chunkId == 0)
-						matchingChunk = object->chunkId;
-					else if(object->softDeleted)
-						matchingChunk = oldChunk; /* Defeat the test */
-					else
-						matchingChunk = yaffs_FindChunkInFile(object,tags.chunkId,NULL);
 
-					if(oldChunk != matchingChunk)
-						T(YAFFS_TRACE_ERROR,
-						  (TSTR("gc: page in gc mismatch: %d %d %d %d"TENDSTR),
-						  oldChunk,matchingChunk,tags.objectId, tags.chunkId));
-
-				}
-
-				if (!object) {
-					T(YAFFS_TRACE_ERROR,
-					  (TSTR
-					   ("page %d in gc has no object: %d %d %d "
-					    TENDSTR), oldChunk,
-					    tags.objectId, tags.chunkId, tags.byteCount));
-				}
-
-				if (object && object->deleted
-				    && tags.chunkId != 0) {
-					/* Data chunk in a deleted file, throw it away
-					 * It's a soft deleted data chunk,
-					 * No need to copy this, just forget about it and
-					 * fix up the object.
-					 */
-
-					object->nDataChunks--;
-
-					if (object->nDataChunks <= 0) {
-						/* remeber to clean up the object */
-						dev->gcCleanupList[cleanups] =
-						    tags.objectId;
-						cleanups++;
-					}
-					markNAND = 0;
-				} else if (0
-					   /* Todo object && object->deleted && object->nDataChunks == 0 */
-					   ) {
-					/* Deleted object header with no data chunks.
-					 * Can be discarded and the file deleted.
-					 */
-					object->chunkId = 0;
-					yaffs_FreeTnode(object->myDev,
-							object->variant.
-							fileVariant.top);
-					object->variant.fileVariant.top = NULL;
-					yaffs_DoGenericObjectDeletion(object);
-
-				} else if (object) {
-					/* It's either a data chunk in a live file or
-					 * an ObjectHeader, so we're interested in it.
-					 * NB Need to keep the ObjectHeaders of deleted files
-					 * until the whole file has been deleted off
-					 */
-					tags.serialNumber++;
-
-					dev->nGCCopies++;
-
-					if (tags.chunkId == 0) {
-						/* It is an object Id,
-						 * We need to nuke the shrinkheader flags first
-						 * We no longer want the shrinkHeader flag since its work is done
-						 * and if it is left in place it will mess up scanning.
-						 * Also, clear out any shadowing stuff
-						 */
-
-						yaffs_ObjectHeader *oh;
-						oh = (yaffs_ObjectHeader *)buffer;
-						oh->isShrink = 0;
-						oh->shadowsObject = -1;
-						tags.extraShadows = 0;
-						tags.extraIsShrinkHeader = 0;
-
-						yaffs_VerifyObjectHeader(object,oh,&tags,1);
-					}
-
-					newChunk =
-					    yaffs_WriteNewChunkWithTagsToNAND(dev, buffer, &tags, 1);
-
-					if (newChunk < 0) {
-						retVal = YAFFS_FAIL;
-					} else {
-
-						/* Ok, now fix up the Tnodes etc. */
-
-						if (tags.chunkId == 0) {
-							/* It's a header */
-							object->chunkId =  newChunk;
-							object->serial =   tags.serialNumber;
-						} else {
-							/* It's a data chunk */
-							yaffs_PutChunkIntoFile
-							    (object,
-							     tags.chunkId,
-							     newChunk, 0);
-						}
-					}
+	while (!found) {
+		found = 1;
+		n += YAFFS_NOBJECT_BUCKETS;
+		if (1 || dev->obj_bucket[bucket].count > 0) {
+			list_for_each(i, &dev->obj_bucket[bucket].list) {
+				/* If there is already one in the list */
+				if (i && list_entry(i, struct yaffs_obj,
+						    hash_link)->obj_id == n) {
+					found = 0;
 				}
-
-				yaffs_DeleteChunk(dev, oldChunk, markNAND, __LINE__);
-
 			}
 		}
+	}
+	return n;
+}
 
-		yaffs_ReleaseTempBuffer(dev, buffer, __LINE__);
+static void yaffs_hash_obj(struct yaffs_obj *in)
+{
+	int bucket = yaffs_hash_fn(in->obj_id);
+	struct yaffs_dev *dev = in->my_dev;
 
+	list_add(&in->hash_link, &dev->obj_bucket[bucket].list);
+	dev->obj_bucket[bucket].count++;
+}
 
-		/* Do any required cleanups */
-		for (i = 0; i < cleanups; i++) {
-			/* Time to delete the file too */
-			object =
-			    yaffs_FindObjectByNumber(dev,
-						     dev->gcCleanupList[i]);
-			if (object) {
-				yaffs_FreeTnode(dev,
-						object->variant.fileVariant.
-						top);
-				object->variant.fileVariant.top = NULL;
-				T(YAFFS_TRACE_GC,
-				  (TSTR
-				   ("yaffs: About to finally delete object %d"
-				    TENDSTR), object->objectId));
-				yaffs_DoGenericObjectDeletion(object);
-				object->myDev->nDeletedFiles--;
-			}
+struct yaffs_obj *yaffs_find_by_number(struct yaffs_dev *dev, u32 number)
+{
+	int bucket = yaffs_hash_fn(number);
+	struct list_head *i;
+	struct yaffs_obj *in;
 
+	list_for_each(i, &dev->obj_bucket[bucket].list) {
+		/* Look if it is in the list */
+		in = list_entry(i, struct yaffs_obj, hash_link);
+		if (in->obj_id == number) {
+			/* Don't show if it is defered free */
+			if (in->defered_free)
+				return NULL;
+			return in;
 		}
-
 	}
 
-	yaffs_VerifyCollectedBlock(dev,bi,block);
-
-	if (chunksBefore >= (chunksAfter = yaffs_GetErasedChunks(dev))) {
-		T(YAFFS_TRACE_GC,
-		  (TSTR
-		   ("gc did not increase free chunks before %d after %d"
-		    TENDSTR), chunksBefore, chunksAfter));
-	}
-
-	dev->isDoingGC = 0;
-
-	return retVal;
+	return NULL;
 }
 
-/* New garbage collector
- * If we're very low on erased blocks then we do aggressive garbage collection
- * otherwise we do "leasurely" garbage collection.
- * Aggressive gc looks further (whole array) and will accept less dirty blocks.
- * Passive gc only inspects smaller areas and will only accept more dirty blocks.
- *
- * The idea is to help clear out space in a more spread-out manner.
- * Dunno if it really does anything useful.
- */
-static int yaffs_CheckGarbageCollection(yaffs_Device * dev)
+struct yaffs_obj *yaffs_new_obj(struct yaffs_dev *dev, int number,
+				enum yaffs_obj_type type)
 {
-	int block;
-	int aggressive;
-	int gcOk = YAFFS_OK;
-	int maxTries = 0;
+	struct yaffs_obj *the_obj = NULL;
+	struct yaffs_tnode *tn = NULL;
 
-	int checkpointBlockAdjust;
+	if (number < 0)
+		number = yaffs_new_obj_id(dev);
 
-	if (dev->isDoingGC) {
-		/* Bail out so we don't get recursive gc */
-		return YAFFS_OK;
+	if (type == YAFFS_OBJECT_TYPE_FILE) {
+		tn = yaffs_get_tnode(dev);
+		if (!tn)
+			return NULL;
 	}
 
-	/* This loop should pass the first time.
-	 * We'll only see looping here if the erase of the collected block fails.
-	 */
-
-	do {
-		maxTries++;
-
-		checkpointBlockAdjust = (dev->nCheckpointReservedBlocks - dev->blocksInCheckpoint);
-		if(checkpointBlockAdjust < 0)
-			checkpointBlockAdjust = 0;
+	the_obj = yaffs_alloc_empty_obj(dev);
+	if (!the_obj) {
+		if (tn)
+			yaffs_free_tnode(dev, tn);
+		return NULL;
+	}
 
-		if (dev->nErasedBlocks < (dev->nReservedBlocks + checkpointBlockAdjust + 2)) {
-			/* We need a block soon...*/
-			aggressive = 1;
-		} else {
-			/* We're in no hurry */
-			aggressive = 0;
-		}
+	the_obj->fake = 0;
+	the_obj->rename_allowed = 1;
+	the_obj->unlink_allowed = 1;
+	the_obj->obj_id = number;
+	yaffs_hash_obj(the_obj);
+	the_obj->variant_type = type;
+	yaffs_load_current_time(the_obj, 1, 1);
 
-		block = yaffs_FindBlockForGarbageCollection(dev, aggressive);
+	switch (type) {
+	case YAFFS_OBJECT_TYPE_FILE:
+		the_obj->variant.file_variant.file_size = 0;
+		the_obj->variant.file_variant.scanned_size = 0;
+		the_obj->variant.file_variant.shrink_size =
+						yaffs_max_file_size(dev);
+		the_obj->variant.file_variant.top_level = 0;
+		the_obj->variant.file_variant.top = tn;
+		break;
+	case YAFFS_OBJECT_TYPE_DIRECTORY:
+		INIT_LIST_HEAD(&the_obj->variant.dir_variant.children);
+		INIT_LIST_HEAD(&the_obj->variant.dir_variant.dirty);
+		break;
+	case YAFFS_OBJECT_TYPE_SYMLINK:
+	case YAFFS_OBJECT_TYPE_HARDLINK:
+	case YAFFS_OBJECT_TYPE_SPECIAL:
+		/* No action required */
+		break;
+	case YAFFS_OBJECT_TYPE_UNKNOWN:
+		/* todo this should not happen */
+		break;
+	}
+	return the_obj;
+}
 
-		if (block > 0) {
-			dev->garbageCollections++;
-			if (!aggressive) {
-				dev->passiveGarbageCollections++;
-			}
+static struct yaffs_obj *yaffs_create_fake_dir(struct yaffs_dev *dev,
+					       int number, u32 mode)
+{
 
-			T(YAFFS_TRACE_GC,
-			  (TSTR
-			   ("yaffs: GC erasedBlocks %d aggressive %d" TENDSTR),
-			   dev->nErasedBlocks, aggressive));
+	struct yaffs_obj *obj =
+	    yaffs_new_obj(dev, number, YAFFS_OBJECT_TYPE_DIRECTORY);
 
-			gcOk = yaffs_GarbageCollectBlock(dev, block);
-		}
+	if (!obj)
+		return NULL;
 
-		if (dev->nErasedBlocks < (dev->nReservedBlocks) && block > 0) {
-			T(YAFFS_TRACE_GC,
-			  (TSTR
-			   ("yaffs: GC !!!no reclaim!!! erasedBlocks %d after try %d block %d"
-			    TENDSTR), dev->nErasedBlocks, maxTries, block));
-		}
-	} while ((dev->nErasedBlocks < dev->nReservedBlocks) && (block > 0)
-		 && (maxTries < 2));
+	obj->fake = 1;	/* it is fake so it might not use NAND */
+	obj->rename_allowed = 0;
+	obj->unlink_allowed = 0;
+	obj->deleted = 0;
+	obj->unlinked = 0;
+	obj->yst_mode = mode;
+	obj->my_dev = dev;
+	obj->hdr_chunk = 0;	/* Not a valid chunk. */
+	return obj;
 
-	return aggressive ? gcOk : YAFFS_OK;
 }
 
-/*-------------------------  TAGS --------------------------------*/
 
-static int yaffs_TagsMatch(const yaffs_ExtendedTags * tags, int objectId,
-			   int chunkInObject)
+static void yaffs_init_tnodes_and_objs(struct yaffs_dev *dev)
 {
-	return (tags->chunkId == chunkInObject &&
-		tags->objectId == objectId && !tags->chunkDeleted) ? 1 : 0;
-
-}
+	int i;
 
+	dev->n_obj = 0;
+	dev->n_tnodes = 0;
+	yaffs_init_raw_tnodes_and_objs(dev);
 
-/*-------------------- Data file manipulation -----------------*/
+	for (i = 0; i < YAFFS_NOBJECT_BUCKETS; i++) {
+		INIT_LIST_HEAD(&dev->obj_bucket[i].list);
+		dev->obj_bucket[i].count = 0;
+	}
+}
 
-static int yaffs_FindChunkInFile(yaffs_Object * in, int chunkInInode,
-				 yaffs_ExtendedTags * tags)
+struct yaffs_obj *yaffs_find_or_create_by_number(struct yaffs_dev *dev,
+						 int number,
+						 enum yaffs_obj_type type)
 {
-	/*Get the Tnode, then get the level 0 offset chunk offset */
-	yaffs_Tnode *tn;
-	int theChunk = -1;
-	yaffs_ExtendedTags localTags;
-	int retVal = -1;
+	struct yaffs_obj *the_obj = NULL;
 
-	yaffs_Device *dev = in->myDev;
+	if (number > 0)
+		the_obj = yaffs_find_by_number(dev, number);
 
-	if (!tags) {
-		/* Passed a NULL, so use our own tags space */
-		tags = &localTags;
-	}
+	if (!the_obj)
+		the_obj = yaffs_new_obj(dev, number, type);
 
-	tn = yaffs_FindLevel0Tnode(dev, &in->variant.fileVariant, chunkInInode);
+	return the_obj;
 
-	if (tn) {
-		theChunk = yaffs_GetChunkGroupBase(dev,tn,chunkInInode);
-
-		retVal =
-		    yaffs_FindChunkInGroup(dev, theChunk, tags, in->objectId,
-					   chunkInInode);
-	}
-	return retVal;
 }
 
-static int yaffs_FindAndDeleteChunkInFile(yaffs_Object * in, int chunkInInode,
-					  yaffs_ExtendedTags * tags)
+YCHAR *yaffs_clone_str(const YCHAR *str)
 {
-	/* Get the Tnode, then get the level 0 offset chunk offset */
-	yaffs_Tnode *tn;
-	int theChunk = -1;
-	yaffs_ExtendedTags localTags;
+	YCHAR *new_str = NULL;
+	int len;
 
-	yaffs_Device *dev = in->myDev;
-	int retVal = -1;
+	if (!str)
+		str = _Y("");
 
-	if (!tags) {
-		/* Passed a NULL, so use our own tags space */
-		tags = &localTags;
+	len = yaffs_strnlen(str, YAFFS_MAX_ALIAS_LENGTH);
+	new_str = kmalloc((len + 1) * sizeof(YCHAR), GFP_NOFS);
+	if (new_str) {
+		yaffs_strncpy(new_str, str, len);
+		new_str[len] = 0;
 	}
+	return new_str;
 
-	tn = yaffs_FindLevel0Tnode(dev, &in->variant.fileVariant, chunkInInode);
-
-	if (tn) {
-
-		theChunk = yaffs_GetChunkGroupBase(dev,tn,chunkInInode);
+}
+/*
+ *yaffs_update_parent() handles fixing a directories mtime and ctime when a new
+ * link (ie. name) is created or deleted in the directory.
+ *
+ * ie.
+ *   create dir/a : update dir's mtime/ctime
+ *   rm dir/a:   update dir's mtime/ctime
+ *   modify dir/a: don't update dir's mtimme/ctime
+ *
+ * This can be handled immediately or defered. Defering helps reduce the number
+ * of updates when many files in a directory are changed within a brief period.
+ *
+ * If the directory updating is defered then yaffs_update_dirty_dirs must be
+ * called periodically.
+ */
 
-		retVal =
-		    yaffs_FindChunkInGroup(dev, theChunk, tags, in->objectId,
-					   chunkInInode);
+static void yaffs_update_parent(struct yaffs_obj *obj)
+{
+	struct yaffs_dev *dev;
 
-		/* Delete the entry in the filestructure (if found) */
-		if (retVal != -1) {
-			yaffs_PutLevel0Tnode(dev,tn,chunkInInode,0);
+	if (!obj)
+		return;
+	dev = obj->my_dev;
+	obj->dirty = 1;
+	yaffs_load_current_time(obj, 0, 1);
+	if (dev->param.defered_dir_update) {
+		struct list_head *link = &obj->variant.dir_variant.dirty;
+
+		if (list_empty(link)) {
+			list_add(link, &dev->dirty_dirs);
+			yaffs_trace(YAFFS_TRACE_BACKGROUND,
+			  "Added object %d to dirty directories",
+			   obj->obj_id);
 		}
-	} else {
-		/*T(("No level 0 found for %d\n", chunkInInode)); */
-	}
 
-	if (retVal == -1) {
-		/* T(("Could not find %d to delete\n",chunkInInode)); */
+	} else {
+		yaffs_update_oh(obj, NULL, 0, 0, 0, NULL);
 	}
-	return retVal;
 }
 
-#ifdef YAFFS_PARANOID
-
-static int yaffs_CheckFileSanity(yaffs_Object * in)
+void yaffs_update_dirty_dirs(struct yaffs_dev *dev)
 {
-	int chunk;
-	int nChunks;
-	int fSize;
-	int failed = 0;
-	int objId;
-	yaffs_Tnode *tn;
-	yaffs_Tags localTags;
-	yaffs_Tags *tags = &localTags;
-	int theChunk;
-	int chunkDeleted;
-
-	if (in->variantType != YAFFS_OBJECT_TYPE_FILE) {
-		/* T(("Object not a file\n")); */
-		return YAFFS_FAIL;
-	}
-
-	objId = in->objectId;
-	fSize = in->variant.fileVariant.fileSize;
-	nChunks =
-	    (fSize + in->myDev->nDataBytesPerChunk - 1) / in->myDev->nDataBytesPerChunk;
+	struct list_head *link;
+	struct yaffs_obj *obj;
+	struct yaffs_dir_var *d_s;
+	union yaffs_obj_var *o_v;
 
-	for (chunk = 1; chunk <= nChunks; chunk++) {
-		tn = yaffs_FindLevel0Tnode(in->myDev, &in->variant.fileVariant,
-					   chunk);
+	yaffs_trace(YAFFS_TRACE_BACKGROUND, "Update dirty directories");
 
-		if (tn) {
+	while (!list_empty(&dev->dirty_dirs)) {
+		link = dev->dirty_dirs.next;
+		list_del_init(link);
 
-			theChunk = yaffs_GetChunkGroupBase(dev,tn,chunk);
+		d_s = list_entry(link, struct yaffs_dir_var, dirty);
+		o_v = list_entry(d_s, union yaffs_obj_var, dir_variant);
+		obj = list_entry(o_v, struct yaffs_obj, variant);
 
-			if (yaffs_CheckChunkBits
-			    (dev, theChunk / dev->nChunksPerBlock,
-			     theChunk % dev->nChunksPerBlock)) {
-
-				yaffs_ReadChunkTagsFromNAND(in->myDev, theChunk,
-							    tags,
-							    &chunkDeleted);
-				if (yaffs_TagsMatch
-				    (tags, in->objectId, chunk, chunkDeleted)) {
-					/* found it; */
+		yaffs_trace(YAFFS_TRACE_BACKGROUND, "Update directory %d",
+			obj->obj_id);
 
-				}
-			} else {
-
-				failed = 1;
-			}
-
-		} else {
-			/* T(("No level 0 found for %d\n", chunk)); */
-		}
+		if (obj->dirty)
+			yaffs_update_oh(obj, NULL, 0, 0, 0, NULL);
 	}
-
-	return failed ? YAFFS_FAIL : YAFFS_OK;
 }
 
-#endif
+/*
+ * Mknod (create) a new object.
+ * equiv_obj only has meaning for a hard link;
+ * alias_str only has meaning for a symlink.
+ * rdev only has meaning for devices (a subset of special objects)
+ */
 
-static int yaffs_PutChunkIntoFile(yaffs_Object * in, int chunkInInode,
-				  int chunkInNAND, int inScan)
+static struct yaffs_obj *yaffs_create_obj(enum yaffs_obj_type type,
+					  struct yaffs_obj *parent,
+					  const YCHAR *name,
+					  u32 mode,
+					  u32 uid,
+					  u32 gid,
+					  struct yaffs_obj *equiv_obj,
+					  const YCHAR *alias_str, u32 rdev)
 {
-	/* NB inScan is zero unless scanning.
-	 * For forward scanning, inScan is > 0;
-	 * for backward scanning inScan is < 0
-	 */
-
-	yaffs_Tnode *tn;
-	yaffs_Device *dev = in->myDev;
-	int existingChunk;
-	yaffs_ExtendedTags existingTags;
-	yaffs_ExtendedTags newTags;
-	unsigned existingSerial, newSerial;
-
-	if (in->variantType != YAFFS_OBJECT_TYPE_FILE) {
-		/* Just ignore an attempt at putting a chunk into a non-file during scanning
-		 * If it is not during Scanning then something went wrong!
-		 */
-		if (!inScan) {
-			T(YAFFS_TRACE_ERROR,
-			  (TSTR
-			   ("yaffs tragedy:attempt to put data chunk into a non-file"
-			    TENDSTR)));
-			YBUG();
-		}
+	struct yaffs_obj *in;
+	YCHAR *str = NULL;
+	struct yaffs_dev *dev = parent->my_dev;
 
-		yaffs_DeleteChunk(dev, chunkInNAND, 1, __LINE__);
-		return YAFFS_OK;
-	}
+	/* Check if the entry exists.
+	 * If it does then fail the call since we don't want a dup. */
+	if (yaffs_find_by_name(parent, name))
+		return NULL;
 
-	tn = yaffs_AddOrFindLevel0Tnode(dev,
-					&in->variant.fileVariant,
-					chunkInInode,
-					NULL);
-	if (!tn) {
-		return YAFFS_FAIL;
+	if (type == YAFFS_OBJECT_TYPE_SYMLINK) {
+		str = yaffs_clone_str(alias_str);
+		if (!str)
+			return NULL;
 	}
 
-	existingChunk = yaffs_GetChunkGroupBase(dev,tn,chunkInInode);
+	in = yaffs_new_obj(dev, -1, type);
 
-	if (inScan != 0) {
-		/* If we're scanning then we need to test for duplicates
-		 * NB This does not need to be efficient since it should only ever
-		 * happen when the power fails during a write, then only one
-		 * chunk should ever be affected.
-		 *
-		 * Correction for YAFFS2: This could happen quite a lot and we need to think about efficiency! TODO
-		 * Update: For backward scanning we don't need to re-read tags so this is quite cheap.
-		 */
-
-		if (existingChunk != 0) {
-			/* NB Right now existing chunk will not be real chunkId if the device >= 32MB
-			 *    thus we have to do a FindChunkInFile to get the real chunk id.
-			 *
-			 * We have a duplicate now we need to decide which one to use:
-			 *
-			 * Backwards scanning YAFFS2: The old one is what we use, dump the new one.
-			 * Forward scanning YAFFS2: The new one is what we use, dump the old one.
-			 * YAFFS1: Get both sets of tags and compare serial numbers.
-			 */
-
-			if (inScan > 0) {
-				/* Only do this for forward scanning */
-				yaffs_ReadChunkWithTagsFromNAND(dev,
-								chunkInNAND,
-								NULL, &newTags);
+	if (!in) {
+		kfree(str);
+		return NULL;
+	}
 
-				/* Do a proper find */
-				existingChunk =
-				    yaffs_FindChunkInFile(in, chunkInInode,
-							  &existingTags);
-			}
+	in->hdr_chunk = 0;
+	in->valid = 1;
+	in->variant_type = type;
 
-			if (existingChunk <= 0) {
-				/*Hoosterman - how did this happen? */
+	in->yst_mode = mode;
 
-				T(YAFFS_TRACE_ERROR,
-				  (TSTR
-				   ("yaffs tragedy: existing chunk < 0 in scan"
-				    TENDSTR)));
+	yaffs_attribs_init(in, gid, uid, rdev);
 
-			}
+	in->n_data_chunks = 0;
 
-			/* NB The deleted flags should be false, otherwise the chunks will
-			 * not be loaded during a scan
-			 */
+	yaffs_set_obj_name(in, name);
+	in->dirty = 1;
 
-			newSerial = newTags.serialNumber;
-			existingSerial = existingTags.serialNumber;
+	yaffs_add_obj_to_dir(parent, in);
 
-			if ((inScan > 0) &&
-			    (in->myDev->isYaffs2 ||
-			     existingChunk <= 0 ||
-			     ((existingSerial + 1) & 3) == newSerial)) {
-				/* Forward scanning.
-				 * Use new
-				 * Delete the old one and drop through to update the tnode
-				 */
-				yaffs_DeleteChunk(dev, existingChunk, 1,
-						  __LINE__);
-			} else {
-				/* Backward scanning or we want to use the existing one
-				 * Use existing.
-				 * Delete the new one and return early so that the tnode isn't changed
-				 */
-				yaffs_DeleteChunk(dev, chunkInNAND, 1,
-						  __LINE__);
-				return YAFFS_OK;
-			}
-		}
+	in->my_dev = parent->my_dev;
 
+	switch (type) {
+	case YAFFS_OBJECT_TYPE_SYMLINK:
+		in->variant.symlink_variant.alias = str;
+		break;
+	case YAFFS_OBJECT_TYPE_HARDLINK:
+		in->variant.hardlink_variant.equiv_obj = equiv_obj;
+		in->variant.hardlink_variant.equiv_id = equiv_obj->obj_id;
+		list_add(&in->hard_links, &equiv_obj->hard_links);
+		break;
+	case YAFFS_OBJECT_TYPE_FILE:
+	case YAFFS_OBJECT_TYPE_DIRECTORY:
+	case YAFFS_OBJECT_TYPE_SPECIAL:
+	case YAFFS_OBJECT_TYPE_UNKNOWN:
+		/* do nothing */
+		break;
 	}
 
-	if (existingChunk == 0) {
-		in->nDataChunks++;
+	if (yaffs_update_oh(in, name, 0, 0, 0, NULL) < 0) {
+		/* Could not create the object header, fail */
+		yaffs_del_obj(in);
+		in = NULL;
 	}
 
-	yaffs_PutLevel0Tnode(dev,tn,chunkInInode,chunkInNAND);
+	if (in)
+		yaffs_update_parent(parent);
 
-	return YAFFS_OK;
+	return in;
 }
 
-static int yaffs_ReadChunkDataFromObject(yaffs_Object * in, int chunkInInode,
-					 __u8 * buffer)
+struct yaffs_obj *yaffs_create_file(struct yaffs_obj *parent,
+				    const YCHAR *name, u32 mode, u32 uid,
+				    u32 gid)
 {
-	int chunkInNAND = yaffs_FindChunkInFile(in, chunkInInode, NULL);
+	return yaffs_create_obj(YAFFS_OBJECT_TYPE_FILE, parent, name, mode,
+				uid, gid, NULL, NULL, 0);
+}
 
-	if (chunkInNAND >= 0) {
-		return yaffs_ReadChunkWithTagsFromNAND(in->myDev, chunkInNAND,
-						       buffer,NULL);
-	} else {
-		T(YAFFS_TRACE_NANDACCESS,
-		  (TSTR("Chunk %d not found zero instead" TENDSTR),
-		   chunkInNAND));
-		/* get sane (zero) data if you read a hole */
-		memset(buffer, 0, in->myDev->nDataBytesPerChunk);
-		return 0;
-	}
+struct yaffs_obj *yaffs_create_dir(struct yaffs_obj *parent, const YCHAR *name,
+				   u32 mode, u32 uid, u32 gid)
+{
+	return yaffs_create_obj(YAFFS_OBJECT_TYPE_DIRECTORY, parent, name,
+				mode, uid, gid, NULL, NULL, 0);
+}
 
+struct yaffs_obj *yaffs_create_special(struct yaffs_obj *parent,
+				       const YCHAR *name, u32 mode, u32 uid,
+				       u32 gid, u32 rdev)
+{
+	return yaffs_create_obj(YAFFS_OBJECT_TYPE_SPECIAL, parent, name, mode,
+				uid, gid, NULL, NULL, rdev);
 }
 
-void yaffs_DeleteChunk(yaffs_Device * dev, int chunkId, int markNAND, int lyn)
+struct yaffs_obj *yaffs_create_symlink(struct yaffs_obj *parent,
+				       const YCHAR *name, u32 mode, u32 uid,
+				       u32 gid, const YCHAR *alias)
 {
-	int block;
-	int page;
-	yaffs_ExtendedTags tags;
-	yaffs_BlockInfo *bi;
+	return yaffs_create_obj(YAFFS_OBJECT_TYPE_SYMLINK, parent, name, mode,
+				uid, gid, NULL, alias, 0);
+}
 
-	if (chunkId <= 0)
-		return;
+/* yaffs_link_obj returns the object id of the equivalent object.*/
+struct yaffs_obj *yaffs_link_obj(struct yaffs_obj *parent, const YCHAR * name,
+				 struct yaffs_obj *equiv_obj)
+{
+	/* Get the real object in case we were fed a hard link obj */
+	equiv_obj = yaffs_get_equivalent_obj(equiv_obj);
 
+	if (yaffs_create_obj(YAFFS_OBJECT_TYPE_HARDLINK,
+			parent, name, 0, 0, 0,
+			equiv_obj, NULL, 0))
+		return equiv_obj;
 
-	dev->nDeletions++;
-	block = chunkId / dev->nChunksPerBlock;
-	page = chunkId % dev->nChunksPerBlock;
+	return NULL;
 
+}
 
-	if(!yaffs_CheckChunkBit(dev,block,page))
-		T(YAFFS_TRACE_VERIFY,
-			(TSTR("Deleting invalid chunk %d"TENDSTR),
-			 chunkId));
 
-	bi = yaffs_GetBlockInfo(dev, block);
 
-	T(YAFFS_TRACE_DELETION,
-	  (TSTR("line %d delete of chunk %d" TENDSTR), lyn, chunkId));
+/*---------------------- Block Management and Page Allocation -------------*/
 
-	if (markNAND &&
-	    bi->blockState != YAFFS_BLOCK_STATE_COLLECTING && !dev->isYaffs2) {
+static void yaffs_deinit_blocks(struct yaffs_dev *dev)
+{
+	if (dev->block_info_alt && dev->block_info)
+		vfree(dev->block_info);
+	else
+		kfree(dev->block_info);
 
-		yaffs_InitialiseTags(&tags);
+	dev->block_info_alt = 0;
 
-		tags.chunkDeleted = 1;
+	dev->block_info = NULL;
 
-		yaffs_WriteChunkWithTagsToNAND(dev, chunkId, NULL, &tags);
-		yaffs_HandleUpdateChunk(dev, chunkId, &tags);
-	} else {
-		dev->nUnmarkedDeletions++;
-	}
+	if (dev->chunk_bits_alt && dev->chunk_bits)
+		vfree(dev->chunk_bits);
+	else
+		kfree(dev->chunk_bits);
+	dev->chunk_bits_alt = 0;
+	dev->chunk_bits = NULL;
+}
 
-	/* Pull out of the management area.
-	 * If the whole block became dirty, this will kick off an erasure.
-	 */
-	if (bi->blockState == YAFFS_BLOCK_STATE_ALLOCATING ||
-	    bi->blockState == YAFFS_BLOCK_STATE_FULL ||
-	    bi->blockState == YAFFS_BLOCK_STATE_NEEDS_SCANNING ||
-	    bi->blockState == YAFFS_BLOCK_STATE_COLLECTING) {
-		dev->nFreeChunks++;
+static int yaffs_init_blocks(struct yaffs_dev *dev)
+{
+	int n_blocks = dev->internal_end_block - dev->internal_start_block + 1;
 
-		yaffs_ClearChunkBit(dev, block, page);
+	dev->block_info = NULL;
+	dev->chunk_bits = NULL;
+	dev->alloc_block = -1;	/* force it to get a new one */
 
-		bi->pagesInUse--;
+	/* If the first allocation strategy fails, thry the alternate one */
+	dev->block_info =
+		kmalloc(n_blocks * sizeof(struct yaffs_block_info), GFP_NOFS);
+	if (!dev->block_info) {
+		dev->block_info =
+		    vmalloc(n_blocks * sizeof(struct yaffs_block_info));
+		dev->block_info_alt = 1;
+	} else {
+		dev->block_info_alt = 0;
+	}
 
-		if (bi->pagesInUse == 0 &&
-		    !bi->hasShrinkHeader &&
-		    bi->blockState != YAFFS_BLOCK_STATE_ALLOCATING &&
-		    bi->blockState != YAFFS_BLOCK_STATE_NEEDS_SCANNING) {
-			yaffs_BlockBecameDirty(dev, block);
-		}
+	if (!dev->block_info)
+		goto alloc_error;
 
+	/* Set up dynamic blockinfo stuff. Round up bytes. */
+	dev->chunk_bit_stride = (dev->param.chunks_per_block + 7) / 8;
+	dev->chunk_bits =
+		kmalloc(dev->chunk_bit_stride * n_blocks, GFP_NOFS);
+	if (!dev->chunk_bits) {
+		dev->chunk_bits =
+		    vmalloc(dev->chunk_bit_stride * n_blocks);
+		dev->chunk_bits_alt = 1;
 	} else {
-		/* T(("Bad news deleting chunk %d\n",chunkId)); */
+		dev->chunk_bits_alt = 0;
 	}
+	if (!dev->chunk_bits)
+		goto alloc_error;
 
-}
-
-static int yaffs_WriteChunkDataToObject(yaffs_Object * in, int chunkInInode,
-					const __u8 * buffer, int nBytes,
-					int useReserve)
-{
-	/* Find old chunk Need to do this to get serial number
-	 * Write new one and patch into tree.
-	 * Invalidate old tags.
-	 */
 
-	int prevChunkId;
-	yaffs_ExtendedTags prevTags;
+	memset(dev->block_info, 0, n_blocks * sizeof(struct yaffs_block_info));
+	memset(dev->chunk_bits, 0, dev->chunk_bit_stride * n_blocks);
+	return YAFFS_OK;
 
-	int newChunkId;
-	yaffs_ExtendedTags newTags;
+alloc_error:
+	yaffs_deinit_blocks(dev);
+	return YAFFS_FAIL;
+}
 
-	yaffs_Device *dev = in->myDev;
 
-	yaffs_CheckGarbageCollection(dev);
+void yaffs_block_became_dirty(struct yaffs_dev *dev, int block_no)
+{
+	struct yaffs_block_info *bi = yaffs_get_block_info(dev, block_no);
+	int erased_ok = 0;
+	int i;
 
-	/* Get the previous chunk at this location in the file if it exists */
-	prevChunkId = yaffs_FindChunkInFile(in, chunkInInode, &prevTags);
+	/* If the block is still healthy erase it and mark as clean.
+	 * If the block has had a data failure, then retire it.
+	 */
 
-	/* Set up new tags */
-	yaffs_InitialiseTags(&newTags);
+	yaffs_trace(YAFFS_TRACE_GC | YAFFS_TRACE_ERASE,
+		"yaffs_block_became_dirty block %d state %d %s",
+		block_no, bi->block_state,
+		(bi->needs_retiring) ? "needs retiring" : "");
 
-	newTags.chunkId = chunkInInode;
-	newTags.objectId = in->objectId;
-	newTags.serialNumber =
-	    (prevChunkId >= 0) ? prevTags.serialNumber + 1 : 1;
-	newTags.byteCount = nBytes;
+	yaffs2_clear_oldest_dirty_seq(dev, bi);
 
-	newChunkId =
-	    yaffs_WriteNewChunkWithTagsToNAND(dev, buffer, &newTags,
-					      useReserve);
+	bi->block_state = YAFFS_BLOCK_STATE_DIRTY;
 
-	if (newChunkId >= 0) {
-		yaffs_PutChunkIntoFile(in, chunkInInode, newChunkId, 0);
+	/* If this is the block being garbage collected then stop gc'ing */
+	if (block_no == dev->gc_block)
+		dev->gc_block = 0;
 
-		if (prevChunkId >= 0) {
-			yaffs_DeleteChunk(dev, prevChunkId, 1, __LINE__);
+	/* If this block is currently the best candidate for gc
+	 * then drop as a candidate */
+	if (block_no == dev->gc_dirtiest) {
+		dev->gc_dirtiest = 0;
+		dev->gc_pages_in_use = 0;
+	}
 
+	if (!bi->needs_retiring) {
+		yaffs2_checkpt_invalidate(dev);
+		erased_ok = yaffs_erase_block(dev, block_no);
+		if (!erased_ok) {
+			dev->n_erase_failures++;
+			yaffs_trace(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS,
+			  "**>> Erasure failed %d", block_no);
 		}
-
-		yaffs_CheckFileSanity(in);
 	}
-	return newChunkId;
-
-}
-
-/* UpdateObjectHeader updates the header on NAND for an object.
- * If name is not NULL, then that new name is used.
- */
-int yaffs_UpdateObjectHeader(yaffs_Object * in, const YCHAR * name, int force,
-			     int isShrink, int shadows)
-{
 
-	yaffs_BlockInfo *bi;
-
-	yaffs_Device *dev = in->myDev;
-
-	int prevChunkId;
-	int retVal = 0;
-
-	int newChunkId;
-	yaffs_ExtendedTags newTags;
-	yaffs_ExtendedTags oldTags;
-
-	__u8 *buffer = NULL;
-	YCHAR oldName[YAFFS_MAX_NAME_LENGTH + 1];
-
-	yaffs_ObjectHeader *oh = NULL;
-
-	yaffs_strcpy(oldName,"silly old name");
+	/* Verify erasure if needed */
+	if (erased_ok &&
+	    ((yaffs_trace_mask & YAFFS_TRACE_ERASE) ||
+	     !yaffs_skip_verification(dev))) {
+		for (i = 0; i < dev->param.chunks_per_block; i++) {
+			if (!yaffs_check_chunk_erased(dev,
+				block_no * dev->param.chunks_per_block + i)) {
+				yaffs_trace(YAFFS_TRACE_ERROR,
+					">>Block %d erasure supposedly OK, but chunk %d not erased",
+					block_no, i);
+			}
+		}
+	}
 
-	if (!in->fake || force) {
+	if (!erased_ok) {
+		/* We lost a block of free space */
+		dev->n_free_chunks -= dev->param.chunks_per_block;
+		yaffs_retire_block(dev, block_no);
+		yaffs_trace(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS,
+			"**>> Block %d retired", block_no);
+		return;
+	}
 
-		yaffs_CheckGarbageCollection(dev);
-		yaffs_CheckObjectDetailsLoaded(in);
+	/* Clean it up... */
+	bi->block_state = YAFFS_BLOCK_STATE_EMPTY;
+	bi->seq_number = 0;
+	dev->n_erased_blocks++;
+	bi->pages_in_use = 0;
+	bi->soft_del_pages = 0;
+	bi->has_shrink_hdr = 0;
+	bi->skip_erased_check = 1;	/* Clean, so no need to check */
+	bi->gc_prioritise = 0;
+	bi->has_summary = 0;
+
+	yaffs_clear_chunk_bits(dev, block_no);
+
+	yaffs_trace(YAFFS_TRACE_ERASE, "Erased block %d", block_no);
+}
+
+static inline int yaffs_gc_process_chunk(struct yaffs_dev *dev,
+					struct yaffs_block_info *bi,
+					int old_chunk, u8 *buffer)
+{
+	int new_chunk;
+	int mark_flash = 1;
+	struct yaffs_ext_tags tags;
+	struct yaffs_obj *object;
+	int matching_chunk;
+	int ret_val = YAFFS_OK;
+
+	memset(&tags, 0, sizeof(tags));
+	yaffs_rd_chunk_tags_nand(dev, old_chunk,
+				 buffer, &tags);
+	object = yaffs_find_by_number(dev, tags.obj_id);
+
+	yaffs_trace(YAFFS_TRACE_GC_DETAIL,
+		"Collecting chunk in block %d, %d %d %d ",
+		dev->gc_chunk, tags.obj_id,
+		tags.chunk_id, tags.n_bytes);
+
+	if (object && !yaffs_skip_verification(dev)) {
+		if (tags.chunk_id == 0)
+			matching_chunk =
+			    object->hdr_chunk;
+		else if (object->soft_del)
+			/* Defeat the test */
+			matching_chunk = old_chunk;
+		else
+			matching_chunk =
+			    yaffs_find_chunk_in_file
+			    (object, tags.chunk_id,
+			     NULL);
+
+		if (old_chunk != matching_chunk)
+			yaffs_trace(YAFFS_TRACE_ERROR,
+				"gc: page in gc mismatch: %d %d %d %d",
+				old_chunk,
+				matching_chunk,
+				tags.obj_id,
+				tags.chunk_id);
+	}
+
+	if (!object) {
+		yaffs_trace(YAFFS_TRACE_ERROR,
+			"page %d in gc has no object: %d %d %d ",
+			old_chunk,
+			tags.obj_id, tags.chunk_id,
+			tags.n_bytes);
+	}
+
+	if (object &&
+	    object->deleted &&
+	    object->soft_del && tags.chunk_id != 0) {
+		/* Data chunk in a soft deleted file,
+		 * throw it away.
+		 * It's a soft deleted data chunk,
+		 * No need to copy this, just forget
+		 * about it and fix up the object.
+		 */
 
-		buffer = yaffs_GetTempBuffer(in->myDev, __LINE__);
-		oh = (yaffs_ObjectHeader *) buffer;
+		/* Free chunks already includes
+		 * softdeleted chunks, how ever this
+		 * chunk is going to soon be really
+		 * deleted which will increment free
+		 * chunks. We have to decrement free
+		 * chunks so this works out properly.
+		 */
+		dev->n_free_chunks--;
+		bi->soft_del_pages--;
+
+		object->n_data_chunks--;
+		if (object->n_data_chunks <= 0) {
+			/* remeber to clean up obj */
+			dev->gc_cleanup_list[dev->n_clean_ups] = tags.obj_id;
+			dev->n_clean_ups++;
+		}
+		mark_flash = 0;
+	} else if (object) {
+		/* It's either a data chunk in a live
+		 * file or an ObjectHeader, so we're
+		 * interested in it.
+		 * NB Need to keep the ObjectHeaders of
+		 * deleted files until the whole file
+		 * has been deleted off
+		 */
+		tags.serial_number++;
+		dev->n_gc_copies++;
+
+		if (tags.chunk_id == 0) {
+			/* It is an object Id,
+			 * We need to nuke the
+			 * shrinkheader flags since its
+			 * work is done.
+			 * Also need to clean up
+			 * shadowing.
+			 */
+			struct yaffs_obj_hdr *oh;
+			oh = (struct yaffs_obj_hdr *) buffer;
+
+			oh->is_shrink = 0;
+			tags.extra_is_shrink = 0;
+			oh->shadows_obj = 0;
+			oh->inband_shadowed_obj_id = 0;
+			tags.extra_shadows = 0;
+
+			/* Update file size */
+			if (object->variant_type == YAFFS_OBJECT_TYPE_FILE) {
+				yaffs_oh_size_load(oh,
+				    object->variant.file_variant.file_size);
+				tags.extra_file_size =
+				    object->variant.file_variant.file_size;
+			}
 
-		prevChunkId = in->chunkId;
+			yaffs_verify_oh(object, oh, &tags, 1);
+			new_chunk =
+			    yaffs_write_new_chunk(dev, (u8 *) oh, &tags, 1);
+		} else {
+			new_chunk =
+			    yaffs_write_new_chunk(dev, buffer, &tags, 1);
+		}
 
-		if (prevChunkId >= 0) {
-			yaffs_ReadChunkWithTagsFromNAND(dev, prevChunkId,
-							buffer, &oldTags);
+		if (new_chunk < 0) {
+			ret_val = YAFFS_FAIL;
+		} else {
 
-			yaffs_VerifyObjectHeader(in,oh,&oldTags,0);
+			/* Now fix up the Tnodes etc. */
 
-			memcpy(oldName, oh->name, sizeof(oh->name));
+			if (tags.chunk_id == 0) {
+				/* It's a header */
+				object->hdr_chunk = new_chunk;
+				object->serial = tags.serial_number;
+			} else {
+				/* It's a data chunk */
+				yaffs_put_chunk_in_file(object, tags.chunk_id,
+							new_chunk, 0);
+			}
 		}
+	}
+	if (ret_val == YAFFS_OK)
+		yaffs_chunk_del(dev, old_chunk, mark_flash, __LINE__);
+	return ret_val;
+}
 
-		memset(buffer, 0xFF, dev->nDataBytesPerChunk);
+static int yaffs_gc_block(struct yaffs_dev *dev, int block, int whole_block)
+{
+	int old_chunk;
+	int ret_val = YAFFS_OK;
+	int i;
+	int is_checkpt_block;
+	int max_copies;
+	int chunks_before = yaffs_get_erased_chunks(dev);
+	int chunks_after;
+	struct yaffs_block_info *bi = yaffs_get_block_info(dev, block);
 
-		oh->type = in->variantType;
-		oh->yst_mode = in->yst_mode;
-		oh->shadowsObject = shadows;
+	is_checkpt_block = (bi->block_state == YAFFS_BLOCK_STATE_CHECKPOINT);
 
-#ifdef CONFIG_YAFFS_WINCE
-		oh->win_atime[0] = in->win_atime[0];
-		oh->win_ctime[0] = in->win_ctime[0];
-		oh->win_mtime[0] = in->win_mtime[0];
-		oh->win_atime[1] = in->win_atime[1];
-		oh->win_ctime[1] = in->win_ctime[1];
-		oh->win_mtime[1] = in->win_mtime[1];
-#else
-		oh->yst_uid = in->yst_uid;
-		oh->yst_gid = in->yst_gid;
-		oh->yst_atime = in->yst_atime;
-		oh->yst_mtime = in->yst_mtime;
-		oh->yst_ctime = in->yst_ctime;
-		oh->yst_rdev = in->yst_rdev;
-#endif
-		if (in->parent) {
-			oh->parentObjectId = in->parent->objectId;
-		} else {
-			oh->parentObjectId = 0;
-		}
+	yaffs_trace(YAFFS_TRACE_TRACING,
+		"Collecting block %d, in use %d, shrink %d, whole_block %d",
+		block, bi->pages_in_use, bi->has_shrink_hdr,
+		whole_block);
 
-		if (name && *name) {
-			memset(oh->name, 0, sizeof(oh->name));
-			yaffs_strncpy(oh->name, name, YAFFS_MAX_NAME_LENGTH);
-		} else if (prevChunkId>=0) {
-			memcpy(oh->name, oldName, sizeof(oh->name));
-		} else {
-			memset(oh->name, 0, sizeof(oh->name));
-		}
+	/*yaffs_verify_free_chunks(dev); */
 
-		oh->isShrink = isShrink;
+	if (bi->block_state == YAFFS_BLOCK_STATE_FULL)
+		bi->block_state = YAFFS_BLOCK_STATE_COLLECTING;
 
-		switch (in->variantType) {
-		case YAFFS_OBJECT_TYPE_UNKNOWN:
-			/* Should not happen */
-			break;
-		case YAFFS_OBJECT_TYPE_FILE:
-			oh->fileSize =
-			    (oh->parentObjectId == YAFFS_OBJECTID_DELETED
-			     || oh->parentObjectId ==
-			     YAFFS_OBJECTID_UNLINKED) ? 0 : in->variant.
-			    fileVariant.fileSize;
-			break;
-		case YAFFS_OBJECT_TYPE_HARDLINK:
-			oh->equivalentObjectId =
-			    in->variant.hardLinkVariant.equivalentObjectId;
-			break;
-		case YAFFS_OBJECT_TYPE_SPECIAL:
-			/* Do nothing */
-			break;
-		case YAFFS_OBJECT_TYPE_DIRECTORY:
-			/* Do nothing */
-			break;
-		case YAFFS_OBJECT_TYPE_SYMLINK:
-			yaffs_strncpy(oh->alias,
-				      in->variant.symLinkVariant.alias,
-				      YAFFS_MAX_ALIAS_LENGTH);
-			oh->alias[YAFFS_MAX_ALIAS_LENGTH] = 0;
-			break;
-		}
+	bi->has_shrink_hdr = 0;	/* clear the flag so that the block can erase */
 
-		/* Tags */
-		yaffs_InitialiseTags(&newTags);
-		in->serial++;
-		newTags.chunkId = 0;
-		newTags.objectId = in->objectId;
-		newTags.serialNumber = in->serial;
+	dev->gc_disable = 1;
 
-		/* Add extra info for file header */
+	yaffs_summary_gc(dev, block);
 
-		newTags.extraHeaderInfoAvailable = 1;
-		newTags.extraParentObjectId = oh->parentObjectId;
-		newTags.extraFileLength = oh->fileSize;
-		newTags.extraIsShrinkHeader = oh->isShrink;
-		newTags.extraEquivalentObjectId = oh->equivalentObjectId;
-		newTags.extraShadows = (oh->shadowsObject > 0) ? 1 : 0;
-		newTags.extraObjectType = in->variantType;
-
-		yaffs_VerifyObjectHeader(in,oh,&newTags,1);
+	if (is_checkpt_block || !yaffs_still_some_chunks(dev, block)) {
+		yaffs_trace(YAFFS_TRACE_TRACING,
+			"Collecting block %d that has no chunks in use",
+			block);
+		yaffs_block_became_dirty(dev, block);
+	} else {
 
-		/* Create new chunk in NAND */
-		newChunkId =
-		    yaffs_WriteNewChunkWithTagsToNAND(dev, buffer, &newTags,
-						      (prevChunkId >= 0) ? 1 : 0);
+		u8 *buffer = yaffs_get_temp_buffer(dev);
 
-		if (newChunkId >= 0) {
+		yaffs_verify_blk(dev, bi, block);
 
-			in->chunkId = newChunkId;
+		max_copies = (whole_block) ? dev->param.chunks_per_block : 5;
+		old_chunk = block * dev->param.chunks_per_block + dev->gc_chunk;
 
-			if (prevChunkId >= 0) {
-				yaffs_DeleteChunk(dev, prevChunkId, 1,
-						  __LINE__);
+		for (/* init already done */ ;
+		     ret_val == YAFFS_OK &&
+		     dev->gc_chunk < dev->param.chunks_per_block &&
+		     (bi->block_state == YAFFS_BLOCK_STATE_COLLECTING) &&
+		     max_copies > 0;
+		     dev->gc_chunk++, old_chunk++) {
+			if (yaffs_check_chunk_bit(dev, block, dev->gc_chunk)) {
+				/* Page is in use and might need to be copied */
+				max_copies--;
+				ret_val = yaffs_gc_process_chunk(dev, bi,
+							old_chunk, buffer);
 			}
+		}
+		yaffs_release_temp_buffer(dev, buffer);
+	}
 
-			if(!yaffs_ObjectHasCachedWriteData(in))
-				in->dirty = 0;
+	yaffs_verify_collected_blk(dev, bi, block);
 
-			/* If this was a shrink, then mark the block that the chunk lives on */
-			if (isShrink) {
-				bi = yaffs_GetBlockInfo(in->myDev,
-							newChunkId /in->myDev->	nChunksPerBlock);
-				bi->hasShrinkHeader = 1;
+	if (bi->block_state == YAFFS_BLOCK_STATE_COLLECTING) {
+		/*
+		 * The gc did not complete. Set block state back to FULL
+		 * because checkpointing does not restore gc.
+		 */
+		bi->block_state = YAFFS_BLOCK_STATE_FULL;
+	} else {
+		/* The gc completed. */
+		/* Do any required cleanups */
+		for (i = 0; i < dev->n_clean_ups; i++) {
+			/* Time to delete the file too */
+			struct yaffs_obj *object =
+			    yaffs_find_by_number(dev, dev->gc_cleanup_list[i]);
+			if (object) {
+				yaffs_free_tnode(dev,
+					  object->variant.file_variant.top);
+				object->variant.file_variant.top = NULL;
+				yaffs_trace(YAFFS_TRACE_GC,
+					"yaffs: About to finally delete object %d",
+					object->obj_id);
+				yaffs_generic_obj_del(object);
+				object->my_dev->n_deleted_files--;
 			}
 
 		}
-
-		retVal = newChunkId;
-
+		chunks_after = yaffs_get_erased_chunks(dev);
+		if (chunks_before >= chunks_after)
+			yaffs_trace(YAFFS_TRACE_GC,
+				"gc did not increase free chunks before %d after %d",
+				chunks_before, chunks_after);
+		dev->gc_block = 0;
+		dev->gc_chunk = 0;
+		dev->n_clean_ups = 0;
 	}
 
-	if (buffer)
-		yaffs_ReleaseTempBuffer(dev, buffer, __LINE__);
+	dev->gc_disable = 0;
 
-	return retVal;
+	return ret_val;
 }
 
-/*------------------------ Short Operations Cache ----------------------------------------
- *   In many situations where there is no high level buffering (eg WinCE) a lot of
- *   reads might be short sequential reads, and a lot of writes may be short
- *   sequential writes. eg. scanning/writing a jpeg file.
- *   In these cases, a short read/write cache can provide a huge perfomance benefit
- *   with dumb-as-a-rock code.
- *   In Linux, the page cache provides read buffering aand the short op cache provides write
- *   buffering.
- *
- *   There are a limited number (~10) of cache chunks per device so that we don't
- *   need a very intelligent search.
+/*
+ * find_gc_block() selects the dirtiest block (or close enough)
+ * for garbage collection.
  */
 
-static int yaffs_ObjectHasCachedWriteData(yaffs_Object *obj)
+static unsigned yaffs_find_gc_block(struct yaffs_dev *dev,
+				    int aggressive, int background)
 {
-	yaffs_Device *dev = obj->myDev;
 	int i;
-	yaffs_ChunkCache *cache;
-	int nCaches = obj->myDev->nShortOpCaches;
-
-	for(i = 0; i < nCaches; i++){
-		cache = &dev->srCache[i];
-		if (cache->object == obj &&
-		    cache->dirty)
-			return 1;
-	}
-
-	return 0;
-}
-
+	int iterations;
+	unsigned selected = 0;
+	int prioritised = 0;
+	int prioritised_exist = 0;
+	struct yaffs_block_info *bi;
+	int threshold;
 
-static void yaffs_FlushFilesChunkCache(yaffs_Object * obj)
-{
-	yaffs_Device *dev = obj->myDev;
-	int lowest = -99;	/* Stop compiler whining. */
-	int i;
-	yaffs_ChunkCache *cache;
-	int chunkWritten = 0;
-	int nCaches = obj->myDev->nShortOpCaches;
-
-	if (nCaches > 0) {
-		do {
-			cache = NULL;
-
-			/* Find the dirty cache for this object with the lowest chunk id. */
-			for (i = 0; i < nCaches; i++) {
-				if (dev->srCache[i].object == obj &&
-				    dev->srCache[i].dirty) {
-					if (!cache
-					    || dev->srCache[i].chunkId <
-					    lowest) {
-						cache = &dev->srCache[i];
-						lowest = cache->chunkId;
-					}
+	/* First let's see if we need to grab a prioritised block */
+	if (dev->has_pending_prioritised_gc && !aggressive) {
+		dev->gc_dirtiest = 0;
+		bi = dev->block_info;
+		for (i = dev->internal_start_block;
+		     i <= dev->internal_end_block && !selected; i++) {
+
+			if (bi->gc_prioritise) {
+				prioritised_exist = 1;
+				if (bi->block_state == YAFFS_BLOCK_STATE_FULL &&
+				    yaffs_block_ok_for_gc(dev, bi)) {
+					selected = i;
+					prioritised = 1;
 				}
 			}
-
-			if (cache && !cache->locked) {
-				/* Write it out and free it up */
-
-				chunkWritten =
-				    yaffs_WriteChunkDataToObject(cache->object,
-								 cache->chunkId,
-								 cache->data,
-								 cache->nBytes,
-								 1);
-				cache->dirty = 0;
-				cache->object = NULL;
-			}
-
-		} while (cache && chunkWritten > 0);
-
-		if (cache) {
-			/* Hoosterman, disk full while writing cache out. */
-			T(YAFFS_TRACE_ERROR,
-			  (TSTR("yaffs tragedy: no space during cache write" TENDSTR)));
-
+			bi++;
 		}
-	}
 
-}
+		/*
+		 * If there is a prioritised block and none was selected then
+		 * this happened because there is at least one old dirty block
+		 * gumming up the works. Let's gc the oldest dirty block.
+		 */
 
-/*yaffs_FlushEntireDeviceCache(dev)
- *
- *
- */
+		if (prioritised_exist &&
+		    !selected && dev->oldest_dirty_block > 0)
+			selected = dev->oldest_dirty_block;
 
-void yaffs_FlushEntireDeviceCache(yaffs_Device *dev)
-{
-	yaffs_Object *obj;
-	int nCaches = dev->nShortOpCaches;
-	int i;
+		if (!prioritised_exist)	/* None found, so we can clear this */
+			dev->has_pending_prioritised_gc = 0;
+	}
 
-	/* Find a dirty object in the cache and flush it...
-	 * until there are no further dirty objects.
+	/* If we're doing aggressive GC then we are happy to take a less-dirty
+	 * block, and search harder.
+	 * else (leasurely gc), then we only bother to do this if the
+	 * block has only a few pages in use.
 	 */
-	do {
-		obj = NULL;
-		for( i = 0; i < nCaches && !obj; i++) {
-			if (dev->srCache[i].object &&
-			    dev->srCache[i].dirty)
-				obj = dev->srCache[i].object;
 
-		}
-		if(obj)
-			yaffs_FlushFilesChunkCache(obj);
+	if (!selected) {
+		int pages_used;
+		int n_blocks =
+		    dev->internal_end_block - dev->internal_start_block + 1;
+		if (aggressive) {
+			threshold = dev->param.chunks_per_block;
+			iterations = n_blocks;
+		} else {
+			int max_threshold;
 
-	} while(obj);
+			if (background)
+				max_threshold = dev->param.chunks_per_block / 2;
+			else
+				max_threshold = dev->param.chunks_per_block / 8;
 
-}
+			if (max_threshold < YAFFS_GC_PASSIVE_THRESHOLD)
+				max_threshold = YAFFS_GC_PASSIVE_THRESHOLD;
 
+			threshold = background ? (dev->gc_not_done + 2) * 2 : 0;
+			if (threshold < YAFFS_GC_PASSIVE_THRESHOLD)
+				threshold = YAFFS_GC_PASSIVE_THRESHOLD;
+			if (threshold > max_threshold)
+				threshold = max_threshold;
 
-/* Grab us a cache chunk for use.
- * First look for an empty one.
- * Then look for the least recently used non-dirty one.
- * Then look for the least recently used dirty one...., flush and look again.
- */
-static yaffs_ChunkCache *yaffs_GrabChunkCacheWorker(yaffs_Device * dev)
-{
-	int i;
-	int usage;
-	int theOne;
+			iterations = n_blocks / 16 + 1;
+			if (iterations > 100)
+				iterations = 100;
+		}
 
-	if (dev->nShortOpCaches > 0) {
-		for (i = 0; i < dev->nShortOpCaches; i++) {
-			if (!dev->srCache[i].object)
-				return &dev->srCache[i];
+		for (i = 0;
+		     i < iterations &&
+		     (dev->gc_dirtiest < 1 ||
+		      dev->gc_pages_in_use > YAFFS_GC_GOOD_ENOUGH);
+		     i++) {
+			dev->gc_block_finder++;
+			if (dev->gc_block_finder < dev->internal_start_block ||
+			    dev->gc_block_finder > dev->internal_end_block)
+				dev->gc_block_finder =
+				    dev->internal_start_block;
+
+			bi = yaffs_get_block_info(dev, dev->gc_block_finder);
+
+			pages_used = bi->pages_in_use - bi->soft_del_pages;
+
+			if (bi->block_state == YAFFS_BLOCK_STATE_FULL &&
+			    pages_used < dev->param.chunks_per_block &&
+			    (dev->gc_dirtiest < 1 ||
+			     pages_used < dev->gc_pages_in_use) &&
+			    yaffs_block_ok_for_gc(dev, bi)) {
+				dev->gc_dirtiest = dev->gc_block_finder;
+				dev->gc_pages_in_use = pages_used;
+			}
 		}
 
-		return NULL;
+		if (dev->gc_dirtiest > 0 && dev->gc_pages_in_use <= threshold)
+			selected = dev->gc_dirtiest;
+	}
 
-		theOne = -1;
-		usage = 0;	/* just to stop the compiler grizzling */
+	/*
+	 * If nothing has been selected for a while, try the oldest dirty
+	 * because that's gumming up the works.
+	 */
 
-		for (i = 0; i < dev->nShortOpCaches; i++) {
-			if (!dev->srCache[i].dirty &&
-			    ((dev->srCache[i].lastUse < usage && theOne >= 0) ||
-			     theOne < 0)) {
-				usage = dev->srCache[i].lastUse;
-				theOne = i;
-			}
+	if (!selected && dev->param.is_yaffs2 &&
+	    dev->gc_not_done >= (background ? 10 : 20)) {
+		yaffs2_find_oldest_dirty_seq(dev);
+		if (dev->oldest_dirty_block > 0) {
+			selected = dev->oldest_dirty_block;
+			dev->gc_dirtiest = selected;
+			dev->oldest_dirty_gc_count++;
+			bi = yaffs_get_block_info(dev, selected);
+			dev->gc_pages_in_use =
+			    bi->pages_in_use - bi->soft_del_pages;
+		} else {
+			dev->gc_not_done = 0;
 		}
+	}
+
+	if (selected) {
+		yaffs_trace(YAFFS_TRACE_GC,
+			"GC Selected block %d with %d free, prioritised:%d",
+			selected,
+			dev->param.chunks_per_block - dev->gc_pages_in_use,
+			prioritised);
 
+		dev->n_gc_blocks++;
+		if (background)
+			dev->bg_gcs++;
 
-		return theOne >= 0 ? &dev->srCache[theOne] : NULL;
+		dev->gc_dirtiest = 0;
+		dev->gc_pages_in_use = 0;
+		dev->gc_not_done = 0;
+		if (dev->refresh_skip > 0)
+			dev->refresh_skip--;
 	} else {
-		return NULL;
+		dev->gc_not_done++;
+		yaffs_trace(YAFFS_TRACE_GC,
+			"GC none: finder %d skip %d threshold %d dirtiest %d using %d oldest %d%s",
+			dev->gc_block_finder, dev->gc_not_done, threshold,
+			dev->gc_dirtiest, dev->gc_pages_in_use,
+			dev->oldest_dirty_block, background ? " bg" : "");
 	}
 
+	return selected;
 }
 
-static yaffs_ChunkCache *yaffs_GrabChunkCache(yaffs_Device * dev)
+/* New garbage collector
+ * If we're very low on erased blocks then we do aggressive garbage collection
+ * otherwise we do "leasurely" garbage collection.
+ * Aggressive gc looks further (whole array) and will accept less dirty blocks.
+ * Passive gc only inspects smaller areas and only accepts more dirty blocks.
+ *
+ * The idea is to help clear out space in a more spread-out manner.
+ * Dunno if it really does anything useful.
+ */
+static int yaffs_check_gc(struct yaffs_dev *dev, int background)
 {
-	yaffs_ChunkCache *cache;
-	yaffs_Object *theObj;
-	int usage;
-	int i;
+	int aggressive = 0;
+	int gc_ok = YAFFS_OK;
+	int max_tries = 0;
+	int min_erased;
+	int erased_chunks;
+	int checkpt_block_adjust;
 
-	if (dev->nShortOpCaches > 0) {
-		/* Try find a non-dirty one... */
+	if (dev->param.gc_control && (dev->param.gc_control(dev) & 1) == 0)
+		return YAFFS_OK;
 
-		cache = yaffs_GrabChunkCacheWorker(dev);
+	if (dev->gc_disable)
+		/* Bail out so we don't get recursive gc */
+		return YAFFS_OK;
 
-		if (!cache) {
-			/* They were all dirty, find the last recently used object and flush
-			 * its cache, then  find again.
-			 * NB what's here is not very accurate, we actually flush the object
-			 * the last recently used page.
-			 */
+	/* This loop should pass the first time.
+	 * Only loops here if the collection does not increase space.
+	 */
 
-			/* With locking we can't assume we can use entry zero */
+	do {
+		max_tries++;
 
-			theObj = NULL;
-			usage = -1;
-			cache = NULL;
+		checkpt_block_adjust = yaffs_calc_checkpt_blocks_required(dev);
 
-			for (i = 0; i < dev->nShortOpCaches; i++) {
-				if (dev->srCache[i].object &&
-				    !dev->srCache[i].locked &&
-				    (dev->srCache[i].lastUse < usage || !cache))
-				{
-					usage = dev->srCache[i].lastUse;
-					theObj = dev->srCache[i].object;
-					cache = &dev->srCache[i];
-				}
-			}
+		min_erased =
+		    dev->param.n_reserved_blocks + checkpt_block_adjust + 1;
+		erased_chunks =
+		    dev->n_erased_blocks * dev->param.chunks_per_block;
 
-			if (!cache || cache->dirty) {
-				/* Flush and try again */
-				yaffs_FlushFilesChunkCache(theObj);
-				cache = yaffs_GrabChunkCacheWorker(dev);
+		/* If we need a block soon then do aggressive gc. */
+		if (dev->n_erased_blocks < min_erased)
+			aggressive = 1;
+		else {
+			if (!background
+			    && erased_chunks > (dev->n_free_chunks / 4))
+				break;
+
+			if (dev->gc_skip > 20)
+				dev->gc_skip = 20;
+			if (erased_chunks < dev->n_free_chunks / 2 ||
+			    dev->gc_skip < 1 || background)
+				aggressive = 0;
+			else {
+				dev->gc_skip--;
+				break;
 			}
-
 		}
-		return cache;
-	} else
-		return NULL;
 
-}
+		dev->gc_skip = 5;
 
-/* Find a cached chunk */
-static yaffs_ChunkCache *yaffs_FindChunkCache(const yaffs_Object * obj,
-					      int chunkId)
-{
-	yaffs_Device *dev = obj->myDev;
-	int i;
-	if (dev->nShortOpCaches > 0) {
-		for (i = 0; i < dev->nShortOpCaches; i++) {
-			if (dev->srCache[i].object == obj &&
-			    dev->srCache[i].chunkId == chunkId) {
-				dev->cacheHits++;
+		/* If we don't already have a block being gc'd then see if we
+		 * should start another */
 
-				return &dev->srCache[i];
-			}
+		if (dev->gc_block < 1 && !aggressive) {
+			dev->gc_block = yaffs2_find_refresh_block(dev);
+			dev->gc_chunk = 0;
+			dev->n_clean_ups = 0;
 		}
-	}
-	return NULL;
-}
-
-/* Mark the chunk for the least recently used algorithym */
-static void yaffs_UseChunkCache(yaffs_Device * dev, yaffs_ChunkCache * cache,
-				int isAWrite)
-{
-
-	if (dev->nShortOpCaches > 0) {
-		if (dev->srLastUse < 0 || dev->srLastUse > 100000000) {
-			/* Reset the cache usages */
-			int i;
-			for (i = 1; i < dev->nShortOpCaches; i++) {
-				dev->srCache[i].lastUse = 0;
-			}
-			dev->srLastUse = 0;
+		if (dev->gc_block < 1) {
+			dev->gc_block =
+			    yaffs_find_gc_block(dev, aggressive, background);
+			dev->gc_chunk = 0;
+			dev->n_clean_ups = 0;
 		}
 
-		dev->srLastUse++;
+		if (dev->gc_block > 0) {
+			dev->all_gcs++;
+			if (!aggressive)
+				dev->passive_gc_count++;
 
-		cache->lastUse = dev->srLastUse;
+			yaffs_trace(YAFFS_TRACE_GC,
+				"yaffs: GC n_erased_blocks %d aggressive %d",
+				dev->n_erased_blocks, aggressive);
 
-		if (isAWrite) {
-			cache->dirty = 1;
+			gc_ok = yaffs_gc_block(dev, dev->gc_block, aggressive);
 		}
-	}
-}
 
-/* Invalidate a single cache page.
- * Do this when a whole page gets written,
- * ie the short cache for this page is no longer valid.
- */
-static void yaffs_InvalidateChunkCache(yaffs_Object * object, int chunkId)
-{
-	if (object->myDev->nShortOpCaches > 0) {
-		yaffs_ChunkCache *cache = yaffs_FindChunkCache(object, chunkId);
-
-		if (cache) {
-			cache->object = NULL;
+		if (dev->n_erased_blocks < (dev->param.n_reserved_blocks) &&
+		    dev->gc_block > 0) {
+			yaffs_trace(YAFFS_TRACE_GC,
+				"yaffs: GC !!!no reclaim!!! n_erased_blocks %d after try %d block %d",
+				dev->n_erased_blocks, max_tries,
+				dev->gc_block);
 		}
-	}
-}
+	} while ((dev->n_erased_blocks < dev->param.n_reserved_blocks) &&
+		 (dev->gc_block > 0) && (max_tries < 2));
 
-/* Invalidate all the cache pages associated with this object
- * Do this whenever ther file is deleted or resized.
- */
-static void yaffs_InvalidateWholeChunkCache(yaffs_Object * in)
-{
-	int i;
-	yaffs_Device *dev = in->myDev;
-
-	if (dev->nShortOpCaches > 0) {
-		/* Invalidate it. */
-		for (i = 0; i < dev->nShortOpCaches; i++) {
-			if (dev->srCache[i].object == in) {
-				dev->srCache[i].object = NULL;
-			}
-		}
-	}
+	return aggressive ? gc_ok : YAFFS_OK;
 }
 
-/*--------------------- Checkpointing --------------------*/
-
-
-static int yaffs_WriteCheckpointValidityMarker(yaffs_Device *dev,int head)
+/*
+ * yaffs_bg_gc()
+ * Garbage collects. Intended to be called from a background thread.
+ * Returns non-zero if at least half the free chunks are erased.
+ */
+int yaffs_bg_gc(struct yaffs_dev *dev, unsigned urgency)
 {
-	yaffs_CheckpointValidity cp;
+	int erased_chunks = dev->n_erased_blocks * dev->param.chunks_per_block;
 
-	memset(&cp,0,sizeof(cp));
+	yaffs_trace(YAFFS_TRACE_BACKGROUND, "Background gc %u", urgency);
 
-	cp.structType = sizeof(cp);
-	cp.magic = YAFFS_MAGIC;
-	cp.version = YAFFS_CHECKPOINT_VERSION;
-	cp.head = (head) ? 1 : 0;
-
-	return (yaffs_CheckpointWrite(dev,&cp,sizeof(cp)) == sizeof(cp))?
-		1 : 0;
+	yaffs_check_gc(dev, 1);
+	return erased_chunks > dev->n_free_chunks / 2;
 }
 
-static int yaffs_ReadCheckpointValidityMarker(yaffs_Device *dev, int head)
-{
-	yaffs_CheckpointValidity cp;
-	int ok;
-
-	ok = (yaffs_CheckpointRead(dev,&cp,sizeof(cp)) == sizeof(cp));
-
-	if(ok)
-		ok = (cp.structType == sizeof(cp)) &&
-		     (cp.magic == YAFFS_MAGIC) &&
-		     (cp.version == YAFFS_CHECKPOINT_VERSION) &&
-		     (cp.head == ((head) ? 1 : 0));
-	return ok ? 1 : 0;
-}
+/*-------------------- Data file manipulation -----------------*/
 
-static void yaffs_DeviceToCheckpointDevice(yaffs_CheckpointDevice *cp,
-					   yaffs_Device *dev)
+static int yaffs_rd_data_obj(struct yaffs_obj *in, int inode_chunk, u8 * buffer)
 {
-	cp->nErasedBlocks = dev->nErasedBlocks;
-	cp->allocationBlock = dev->allocationBlock;
-	cp->allocationPage = dev->allocationPage;
-	cp->nFreeChunks = dev->nFreeChunks;
+	int nand_chunk = yaffs_find_chunk_in_file(in, inode_chunk, NULL);
 
-	cp->nDeletedFiles = dev->nDeletedFiles;
-	cp->nUnlinkedFiles = dev->nUnlinkedFiles;
-	cp->nBackgroundDeletions = dev->nBackgroundDeletions;
-	cp->sequenceNumber = dev->sequenceNumber;
-	cp->oldestDirtySequence = dev->oldestDirtySequence;
+	if (nand_chunk >= 0)
+		return yaffs_rd_chunk_tags_nand(in->my_dev, nand_chunk,
+						buffer, NULL);
+	else {
+		yaffs_trace(YAFFS_TRACE_NANDACCESS,
+			"Chunk %d not found zero instead",
+			nand_chunk);
+		/* get sane (zero) data if you read a hole */
+		memset(buffer, 0, in->my_dev->data_bytes_per_chunk);
+		return 0;
+	}
 
 }
 
-static void yaffs_CheckpointDeviceToDevice(yaffs_Device *dev,
-					   yaffs_CheckpointDevice *cp)
+void yaffs_chunk_del(struct yaffs_dev *dev, int chunk_id, int mark_flash,
+		     int lyn)
 {
-	dev->nErasedBlocks = cp->nErasedBlocks;
-	dev->allocationBlock = cp->allocationBlock;
-	dev->allocationPage = cp->allocationPage;
-	dev->nFreeChunks = cp->nFreeChunks;
+	int block;
+	int page;
+	struct yaffs_ext_tags tags;
+	struct yaffs_block_info *bi;
 
-	dev->nDeletedFiles = cp->nDeletedFiles;
-	dev->nUnlinkedFiles = cp->nUnlinkedFiles;
-	dev->nBackgroundDeletions = cp->nBackgroundDeletions;
-	dev->sequenceNumber = cp->sequenceNumber;
-	dev->oldestDirtySequence = cp->oldestDirtySequence;
-}
+	if (chunk_id <= 0)
+		return;
 
+	dev->n_deletions++;
+	block = chunk_id / dev->param.chunks_per_block;
+	page = chunk_id % dev->param.chunks_per_block;
 
-static int yaffs_WriteCheckpointDevice(yaffs_Device *dev)
-{
-	yaffs_CheckpointDevice cp;
-	__u32 nBytes;
-	__u32 nBlocks = (dev->internalEndBlock - dev->internalStartBlock + 1);
+	if (!yaffs_check_chunk_bit(dev, block, page))
+		yaffs_trace(YAFFS_TRACE_VERIFY,
+			"Deleting invalid chunk %d", chunk_id);
 
-	int ok;
+	bi = yaffs_get_block_info(dev, block);
 
-	/* Write device runtime values*/
-	yaffs_DeviceToCheckpointDevice(&cp,dev);
-	cp.structType = sizeof(cp);
+	yaffs2_update_oldest_dirty_seq(dev, block, bi);
 
-	ok = (yaffs_CheckpointWrite(dev,&cp,sizeof(cp)) == sizeof(cp));
+	yaffs_trace(YAFFS_TRACE_DELETION,
+		"line %d delete of chunk %d",
+		lyn, chunk_id);
 
-	/* Write block info */
-	if(ok) {
-		nBytes = nBlocks * sizeof(yaffs_BlockInfo);
-		ok = (yaffs_CheckpointWrite(dev,dev->blockInfo,nBytes) == nBytes);
-	}
+	if (!dev->param.is_yaffs2 && mark_flash &&
+	    bi->block_state != YAFFS_BLOCK_STATE_COLLECTING) {
 
-	/* Write chunk bits */
-	if(ok) {
-		nBytes = nBlocks * dev->chunkBitmapStride;
-		ok = (yaffs_CheckpointWrite(dev,dev->chunkBits,nBytes) == nBytes);
+		memset(&tags, 0, sizeof(tags));
+		tags.is_deleted = 1;
+		yaffs_wr_chunk_tags_nand(dev, chunk_id, NULL, &tags);
+		yaffs_handle_chunk_update(dev, chunk_id, &tags);
+	} else {
+		dev->n_unmarked_deletions++;
 	}
-	return	 ok ? 1 : 0;
 
+	/* Pull out of the management area.
+	 * If the whole block became dirty, this will kick off an erasure.
+	 */
+	if (bi->block_state == YAFFS_BLOCK_STATE_ALLOCATING ||
+	    bi->block_state == YAFFS_BLOCK_STATE_FULL ||
+	    bi->block_state == YAFFS_BLOCK_STATE_NEEDS_SCAN ||
+	    bi->block_state == YAFFS_BLOCK_STATE_COLLECTING) {
+		dev->n_free_chunks++;
+		yaffs_clear_chunk_bit(dev, block, page);
+		bi->pages_in_use--;
+
+		if (bi->pages_in_use == 0 &&
+		    !bi->has_shrink_hdr &&
+		    bi->block_state != YAFFS_BLOCK_STATE_ALLOCATING &&
+		    bi->block_state != YAFFS_BLOCK_STATE_NEEDS_SCAN) {
+			yaffs_block_became_dirty(dev, block);
+		}
+	}
 }
 
-static int yaffs_ReadCheckpointDevice(yaffs_Device *dev)
+static int yaffs_wr_data_obj(struct yaffs_obj *in, int inode_chunk,
+			     const u8 *buffer, int n_bytes, int use_reserve)
 {
-	yaffs_CheckpointDevice cp;
-	__u32 nBytes;
-	__u32 nBlocks = (dev->internalEndBlock - dev->internalStartBlock + 1);
+	/* Find old chunk Need to do this to get serial number
+	 * Write new one and patch into tree.
+	 * Invalidate old tags.
+	 */
 
-	int ok;
+	int prev_chunk_id;
+	struct yaffs_ext_tags prev_tags;
+	int new_chunk_id;
+	struct yaffs_ext_tags new_tags;
+	struct yaffs_dev *dev = in->my_dev;
 
-	ok = (yaffs_CheckpointRead(dev,&cp,sizeof(cp)) == sizeof(cp));
-	if(!ok)
-		return 0;
+	yaffs_check_gc(dev, 0);
 
-	if(cp.structType != sizeof(cp))
+	/* Get the previous chunk at this location in the file if it exists.
+	 * If it does not exist then put a zero into the tree. This creates
+	 * the tnode now, rather than later when it is harder to clean up.
+	 */
+	prev_chunk_id = yaffs_find_chunk_in_file(in, inode_chunk, &prev_tags);
+	if (prev_chunk_id < 1 &&
+	    !yaffs_put_chunk_in_file(in, inode_chunk, 0, 0))
 		return 0;
 
+	/* Set up new tags */
+	memset(&new_tags, 0, sizeof(new_tags));
 
-	yaffs_CheckpointDeviceToDevice(dev,&cp);
+	new_tags.chunk_id = inode_chunk;
+	new_tags.obj_id = in->obj_id;
+	new_tags.serial_number =
+	    (prev_chunk_id > 0) ? prev_tags.serial_number + 1 : 1;
+	new_tags.n_bytes = n_bytes;
 
-	nBytes = nBlocks * sizeof(yaffs_BlockInfo);
+	if (n_bytes < 1 || n_bytes > dev->param.total_bytes_per_chunk) {
+		yaffs_trace(YAFFS_TRACE_ERROR,
+		  "Writing %d bytes to chunk!!!!!!!!!",
+		   n_bytes);
+		BUG();
+	}
 
-	ok = (yaffs_CheckpointRead(dev,dev->blockInfo,nBytes) == nBytes);
+	new_chunk_id =
+	    yaffs_write_new_chunk(dev, buffer, &new_tags, use_reserve);
 
-	if(!ok)
-		return 0;
-	nBytes = nBlocks * dev->chunkBitmapStride;
+	if (new_chunk_id > 0) {
+		yaffs_put_chunk_in_file(in, inode_chunk, new_chunk_id, 0);
 
-	ok = (yaffs_CheckpointRead(dev,dev->chunkBits,nBytes) == nBytes);
+		if (prev_chunk_id > 0)
+			yaffs_chunk_del(dev, prev_chunk_id, 1, __LINE__);
 
-	return ok ? 1 : 0;
-}
+		yaffs_verify_file_sane(in);
+	}
+	return new_chunk_id;
 
-static void yaffs_ObjectToCheckpointObject(yaffs_CheckpointObject *cp,
-					   yaffs_Object *obj)
-{
+}
 
-	cp->objectId = obj->objectId;
-	cp->parentId = (obj->parent) ? obj->parent->objectId : 0;
-	cp->chunkId = obj->chunkId;
-	cp->variantType = obj->variantType;
-	cp->deleted = obj->deleted;
-	cp->softDeleted = obj->softDeleted;
-	cp->unlinked = obj->unlinked;
-	cp->fake = obj->fake;
-	cp->renameAllowed = obj->renameAllowed;
-	cp->unlinkAllowed = obj->unlinkAllowed;
-	cp->serial = obj->serial;
-	cp->nDataChunks = obj->nDataChunks;
 
-	if(obj->variantType == YAFFS_OBJECT_TYPE_FILE)
-		cp->fileSizeOrEquivalentObjectId = obj->variant.fileVariant.fileSize;
-	else if(obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK)
-		cp->fileSizeOrEquivalentObjectId = obj->variant.hardLinkVariant.equivalentObjectId;
-}
 
-static void yaffs_CheckpointObjectToObject( yaffs_Object *obj,yaffs_CheckpointObject *cp)
+static int yaffs_do_xattrib_mod(struct yaffs_obj *obj, int set,
+				const YCHAR *name, const void *value, int size,
+				int flags)
 {
+	struct yaffs_xattr_mod xmod;
+	int result;
 
-	yaffs_Object *parent;
+	xmod.set = set;
+	xmod.name = name;
+	xmod.data = value;
+	xmod.size = size;
+	xmod.flags = flags;
+	xmod.result = -ENOSPC;
 
-	obj->objectId = cp->objectId;
+	result = yaffs_update_oh(obj, NULL, 0, 0, 0, &xmod);
 
-	if(cp->parentId)
-		parent = yaffs_FindOrCreateObjectByNumber(
-					obj->myDev,
-					cp->parentId,
-					YAFFS_OBJECT_TYPE_DIRECTORY);
+	if (result > 0)
+		return xmod.result;
 	else
-		parent = NULL;
-
-	if(parent)
-		yaffs_AddObjectToDirectory(parent, obj);
-
-	obj->chunkId = cp->chunkId;
-	obj->variantType = cp->variantType;
-	obj->deleted = cp->deleted;
-	obj->softDeleted = cp->softDeleted;
-	obj->unlinked = cp->unlinked;
-	obj->fake = cp->fake;
-	obj->renameAllowed = cp->renameAllowed;
-	obj->unlinkAllowed = cp->unlinkAllowed;
-	obj->serial = cp->serial;
-	obj->nDataChunks = cp->nDataChunks;
-
-	if(obj->variantType == YAFFS_OBJECT_TYPE_FILE)
-		obj->variant.fileVariant.fileSize = cp->fileSizeOrEquivalentObjectId;
-	else if(obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK)
-		obj->variant.hardLinkVariant.equivalentObjectId = cp->fileSizeOrEquivalentObjectId;
-
-	if(obj->objectId >= YAFFS_NOBJECT_BUCKETS)
-		obj->lazyLoaded = 1;
+		return -ENOSPC;
 }
 
-
-
-static int yaffs_CheckpointTnodeWorker(yaffs_Object * in, yaffs_Tnode * tn,
-					__u32 level, int chunkOffset)
+static int yaffs_apply_xattrib_mod(struct yaffs_obj *obj, char *buffer,
+				   struct yaffs_xattr_mod *xmod)
 {
-	int i;
-	yaffs_Device *dev = in->myDev;
-	int ok = 1;
-	int nTnodeBytes = (dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8;
-
-	if (tn) {
-		if (level > 0) {
-
-			for (i = 0; i < YAFFS_NTNODES_INTERNAL && ok; i++){
-				if (tn->internal[i]) {
-					ok = yaffs_CheckpointTnodeWorker(in,
-							tn->internal[i],
-							level - 1,
-							(chunkOffset<<YAFFS_TNODES_INTERNAL_BITS) + i);
-				}
-			}
-		} else if (level == 0) {
-			__u32 baseOffset = chunkOffset <<  YAFFS_TNODES_LEVEL0_BITS;
-			/* printf("write tnode at %d\n",baseOffset); */
-			ok = (yaffs_CheckpointWrite(dev,&baseOffset,sizeof(baseOffset)) == sizeof(baseOffset));
-			if(ok)
-				ok = (yaffs_CheckpointWrite(dev,tn,nTnodeBytes) == nTnodeBytes);
-		}
-	}
-
-	return ok;
+	int retval = 0;
+	int x_offs = sizeof(struct yaffs_obj_hdr);
+	struct yaffs_dev *dev = obj->my_dev;
+	int x_size = dev->data_bytes_per_chunk - sizeof(struct yaffs_obj_hdr);
+	char *x_buffer = buffer + x_offs;
 
-}
+	if (xmod->set)
+		retval =
+		    nval_set(x_buffer, x_size, xmod->name, xmod->data,
+			     xmod->size, xmod->flags);
+	else
+		retval = nval_del(x_buffer, x_size, xmod->name);
 
-static int yaffs_WriteCheckpointTnodes(yaffs_Object *obj)
-{
-	__u32 endMarker = ~0;
-	int ok = 1;
+	obj->has_xattr = nval_hasvalues(x_buffer, x_size);
+	obj->xattr_known = 1;
+	xmod->result = retval;
 
-	if(obj->variantType == YAFFS_OBJECT_TYPE_FILE){
-		ok = yaffs_CheckpointTnodeWorker(obj,
-					    obj->variant.fileVariant.top,
-					    obj->variant.fileVariant.topLevel,
-					    0);
-		if(ok)
-			ok = (yaffs_CheckpointWrite(obj->myDev,&endMarker,sizeof(endMarker)) ==
-				sizeof(endMarker));
-	}
-
-	return ok ? 1 : 0;
+	return retval;
 }
 
-static int yaffs_ReadCheckpointTnodes(yaffs_Object *obj)
+static int yaffs_do_xattrib_fetch(struct yaffs_obj *obj, const YCHAR *name,
+				  void *value, int size)
 {
-	__u32 baseChunk;
-	int ok = 1;
-	yaffs_Device *dev = obj->myDev;
-	yaffs_FileStructure *fileStructPtr = &obj->variant.fileVariant;
-	yaffs_Tnode *tn;
-	int nread = 0;
+	char *buffer = NULL;
+	int result;
+	struct yaffs_ext_tags tags;
+	struct yaffs_dev *dev = obj->my_dev;
+	int x_offs = sizeof(struct yaffs_obj_hdr);
+	int x_size = dev->data_bytes_per_chunk - sizeof(struct yaffs_obj_hdr);
+	char *x_buffer;
+	int retval = 0;
 
-	ok = (yaffs_CheckpointRead(dev,&baseChunk,sizeof(baseChunk)) == sizeof(baseChunk));
+	if (obj->hdr_chunk < 1)
+		return -ENODATA;
 
-	while(ok && (~baseChunk)){
-		nread++;
-		/* Read level 0 tnode */
+	/* If we know that the object has no xattribs then don't do all the
+	 * reading and parsing.
+	 */
+	if (obj->xattr_known && !obj->has_xattr) {
+		if (name)
+			return -ENODATA;
+		else
+			return 0;
+	}
 
+	buffer = (char *)yaffs_get_temp_buffer(dev);
+	if (!buffer)
+		return -ENOMEM;
 
-		/* printf("read  tnode at %d\n",baseChunk); */
-		tn = yaffs_GetTnodeRaw(dev);
-		if(tn)
-			ok = (yaffs_CheckpointRead(dev,tn,(dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8) ==
-			      (dev->tnodeWidth * YAFFS_NTNODES_LEVEL0)/8);
-		else
-			ok = 0;
+	result =
+	    yaffs_rd_chunk_tags_nand(dev, obj->hdr_chunk, (u8 *) buffer, &tags);
 
-		if(tn && ok){
-			ok = yaffs_AddOrFindLevel0Tnode(dev,
-							fileStructPtr,
-							baseChunk,
-							tn) ? 1 : 0;
+	if (result != YAFFS_OK)
+		retval = -ENOENT;
+	else {
+		x_buffer = buffer + x_offs;
 
+		if (!obj->xattr_known) {
+			obj->has_xattr = nval_hasvalues(x_buffer, x_size);
+			obj->xattr_known = 1;
 		}
 
-		if(ok)
-			ok = (yaffs_CheckpointRead(dev,&baseChunk,sizeof(baseChunk)) == sizeof(baseChunk));
-
+		if (name)
+			retval = nval_get(x_buffer, x_size, name, value, size);
+		else
+			retval = nval_list(x_buffer, x_size, value, size);
 	}
-
-	T(YAFFS_TRACE_CHECKPOINT,(
-		TSTR("Checkpoint read tnodes %d records, last %d. ok %d" TENDSTR),
-		nread,baseChunk,ok));
-
-	return ok ? 1 : 0;
+	yaffs_release_temp_buffer(dev, (u8 *) buffer);
+	return retval;
 }
 
-
-static int yaffs_WriteCheckpointObjects(yaffs_Device *dev)
+int yaffs_set_xattrib(struct yaffs_obj *obj, const YCHAR * name,
+		      const void *value, int size, int flags)
 {
-	yaffs_Object *obj;
-	yaffs_CheckpointObject cp;
-	int i;
-	int ok = 1;
-	struct list_head *lh;
-
-
-	/* Iterate through the objects in each hash entry,
-	 * dumping them to the checkpointing stream.
-	 */
-
-	 for(i = 0; ok &&  i <  YAFFS_NOBJECT_BUCKETS; i++){
-		list_for_each(lh, &dev->objectBucket[i].list) {
-			if (lh) {
-				obj = list_entry(lh, yaffs_Object, hashLink);
-				if (!obj->deferedFree) {
-					yaffs_ObjectToCheckpointObject(&cp,obj);
-					cp.structType = sizeof(cp);
-
-					T(YAFFS_TRACE_CHECKPOINT,(
-						TSTR("Checkpoint write object %d parent %d type %d chunk %d obj addr %x" TENDSTR),
-						cp.objectId,cp.parentId,cp.variantType,cp.chunkId,(unsigned) obj));
-
-					ok = (yaffs_CheckpointWrite(dev,&cp,sizeof(cp)) == sizeof(cp));
-
-					if(ok && obj->variantType == YAFFS_OBJECT_TYPE_FILE){
-						ok = yaffs_WriteCheckpointTnodes(obj);
-					}
-				}
-			}
-		}
-	 }
-
-	 /* Dump end of list */
-	memset(&cp,0xFF,sizeof(yaffs_CheckpointObject));
-	cp.structType = sizeof(cp);
-
-	if(ok)
-		ok = (yaffs_CheckpointWrite(dev,&cp,sizeof(cp)) == sizeof(cp));
-
-	return ok ? 1 : 0;
+	return yaffs_do_xattrib_mod(obj, 1, name, value, size, flags);
 }
 
-static int yaffs_ReadCheckpointObjects(yaffs_Device *dev)
+int yaffs_remove_xattrib(struct yaffs_obj *obj, const YCHAR * name)
 {
-	yaffs_Object *obj;
-	yaffs_CheckpointObject cp;
-	int ok = 1;
-	int done = 0;
-	yaffs_Object *hardList = NULL;
-
-	while(ok && !done) {
-		ok = (yaffs_CheckpointRead(dev,&cp,sizeof(cp)) == sizeof(cp));
-		if(cp.structType != sizeof(cp)) {
-			T(YAFFS_TRACE_CHECKPOINT,(TSTR("struct size %d instead of %d ok %d"TENDSTR),
-				cp.structType,sizeof(cp),ok));
-			ok = 0;
-		}
-
-		T(YAFFS_TRACE_CHECKPOINT,(TSTR("Checkpoint read object %d parent %d type %d chunk %d " TENDSTR),
-			cp.objectId,cp.parentId,cp.variantType,cp.chunkId));
-
-		if(ok && cp.objectId == ~0)
-			done = 1;
-		else if(ok){
-			obj = yaffs_FindOrCreateObjectByNumber(dev,cp.objectId, cp.variantType);
-			if(obj) {
-				yaffs_CheckpointObjectToObject(obj,&cp);
-				if(obj->variantType == YAFFS_OBJECT_TYPE_FILE) {
-					ok = yaffs_ReadCheckpointTnodes(obj);
-				} else if(obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK) {
-					obj->hardLinks.next =
-						    (struct list_head *)
-						    hardList;
-					hardList = obj;
-				}
-
-			}
-		}
-	}
-
-	if(ok)
-		yaffs_HardlinkFixup(dev,hardList);
-
-	return ok ? 1 : 0;
+	return yaffs_do_xattrib_mod(obj, 0, name, NULL, 0, 0);
 }
 
-static int yaffs_WriteCheckpointSum(yaffs_Device *dev)
+int yaffs_get_xattrib(struct yaffs_obj *obj, const YCHAR * name, void *value,
+		      int size)
 {
-	__u32 checkpointSum;
-	int ok;
-
-	yaffs_GetCheckpointSum(dev,&checkpointSum);
-
-	ok = (yaffs_CheckpointWrite(dev,&checkpointSum,sizeof(checkpointSum)) == sizeof(checkpointSum));
-
-	if(!ok)
-		return 0;
+	return yaffs_do_xattrib_fetch(obj, name, value, size);
+}
 
-	return 1;
+int yaffs_list_xattrib(struct yaffs_obj *obj, char *buffer, int size)
+{
+	return yaffs_do_xattrib_fetch(obj, NULL, buffer, size);
 }
 
-static int yaffs_ReadCheckpointSum(yaffs_Device *dev)
+static void yaffs_check_obj_details_loaded(struct yaffs_obj *in)
 {
-	__u32 checkpointSum0;
-	__u32 checkpointSum1;
-	int ok;
+	u8 *buf;
+	struct yaffs_obj_hdr *oh;
+	struct yaffs_dev *dev;
+	struct yaffs_ext_tags tags;
 
-	yaffs_GetCheckpointSum(dev,&checkpointSum0);
+	if (!in || !in->lazy_loaded || in->hdr_chunk < 1)
+		return;
 
-	ok = (yaffs_CheckpointRead(dev,&checkpointSum1,sizeof(checkpointSum1)) == sizeof(checkpointSum1));
+	dev = in->my_dev;
+	in->lazy_loaded = 0;
+	buf = yaffs_get_temp_buffer(dev);
 
-	if(!ok)
-		return 0;
+	yaffs_rd_chunk_tags_nand(dev, in->hdr_chunk, buf, &tags);
+	oh = (struct yaffs_obj_hdr *)buf;
 
-	if(checkpointSum0 != checkpointSum1)
-		return 0;
+	in->yst_mode = oh->yst_mode;
+	yaffs_load_attribs(in, oh);
+	yaffs_set_obj_name_from_oh(in, oh);
 
-	return 1;
+	if (in->variant_type == YAFFS_OBJECT_TYPE_SYMLINK) {
+		in->variant.symlink_variant.alias =
+		    yaffs_clone_str(oh->alias);
+	}
+	yaffs_release_temp_buffer(dev, buf);
 }
 
+static void yaffs_load_name_from_oh(struct yaffs_dev *dev, YCHAR *name,
+				    const YCHAR *oh_name, int buff_size)
+{
+#ifdef CONFIG_YAFFS_AUTO_UNICODE
+	if (dev->param.auto_unicode) {
+		if (*oh_name) {
+			/* It is an ASCII name, do an ASCII to
+			 * unicode conversion */
+			const char *ascii_oh_name = (const char *)oh_name;
+			int n = buff_size - 1;
+			while (n > 0 && *ascii_oh_name) {
+				*name = *ascii_oh_name;
+				name++;
+				ascii_oh_name++;
+				n--;
+			}
+		} else {
+			yaffs_strncpy(name, oh_name + 1, buff_size - 1);
+		}
+	} else {
+#else
+	dev = dev;
+	{
+#endif
+		yaffs_strncpy(name, oh_name, buff_size - 1);
+	}
+}
 
-static int yaffs_WriteCheckpointData(yaffs_Device *dev)
+static void yaffs_load_oh_from_name(struct yaffs_dev *dev, YCHAR *oh_name,
+				    const YCHAR *name)
 {
+#ifdef CONFIG_YAFFS_AUTO_UNICODE
 
-	int ok = 1;
+	int is_ascii;
+	YCHAR *w;
 
-	if(dev->skipCheckpointWrite || !dev->isYaffs2){
-		T(YAFFS_TRACE_CHECKPOINT,(TSTR("skipping checkpoint write" TENDSTR)));
-		ok = 0;
-	}
+	if (dev->param.auto_unicode) {
 
-	if(ok)
-		ok = yaffs_CheckpointOpen(dev,1);
+		is_ascii = 1;
+		w = name;
 
-	if(ok){
-		T(YAFFS_TRACE_CHECKPOINT,(TSTR("write checkpoint validity" TENDSTR)));
-		ok = yaffs_WriteCheckpointValidityMarker(dev,1);
-	}
-	if(ok){
-		T(YAFFS_TRACE_CHECKPOINT,(TSTR("write checkpoint device" TENDSTR)));
-		ok = yaffs_WriteCheckpointDevice(dev);
-	}
-	if(ok){
-		T(YAFFS_TRACE_CHECKPOINT,(TSTR("write checkpoint objects" TENDSTR)));
-		ok = yaffs_WriteCheckpointObjects(dev);
-	}
-	if(ok){
-		T(YAFFS_TRACE_CHECKPOINT,(TSTR("write checkpoint validity" TENDSTR)));
-		ok = yaffs_WriteCheckpointValidityMarker(dev,0);
-	}
+		/* Figure out if the name will fit in ascii character set */
+		while (is_ascii && *w) {
+			if ((*w) & 0xff00)
+				is_ascii = 0;
+			w++;
+		}
 
-	if(ok){
-		ok = yaffs_WriteCheckpointSum(dev);
+		if (is_ascii) {
+			/* It is an ASCII name, so convert unicode to ascii */
+			char *ascii_oh_name = (char *)oh_name;
+			int n = YAFFS_MAX_NAME_LENGTH - 1;
+			while (n > 0 && *name) {
+				*ascii_oh_name = *name;
+				name++;
+				ascii_oh_name++;
+				n--;
+			}
+		} else {
+			/* Unicode name, so save starting at the second YCHAR */
+			*oh_name = 0;
+			yaffs_strncpy(oh_name + 1, name, YAFFS_MAX_NAME_LENGTH - 2);
+		}
+	} else {
+#else
+	dev = dev;
+	{
+#endif
+		yaffs_strncpy(oh_name, name, YAFFS_MAX_NAME_LENGTH - 1);
 	}
+}
 
+/* UpdateObjectHeader updates the header on NAND for an object.
+ * If name is not NULL, then that new name is used.
+ */
+int yaffs_update_oh(struct yaffs_obj *in, const YCHAR *name, int force,
+		    int is_shrink, int shadows, struct yaffs_xattr_mod *xmod)
+{
 
-	if(!yaffs_CheckpointClose(dev))
-		 ok = 0;
+	struct yaffs_block_info *bi;
+	struct yaffs_dev *dev = in->my_dev;
+	int prev_chunk_id;
+	int ret_val = 0;
+	int new_chunk_id;
+	struct yaffs_ext_tags new_tags;
+	struct yaffs_ext_tags old_tags;
+	const YCHAR *alias = NULL;
+	u8 *buffer = NULL;
+	YCHAR old_name[YAFFS_MAX_NAME_LENGTH + 1];
+	struct yaffs_obj_hdr *oh = NULL;
+	loff_t file_size = 0;
 
-	if(ok)
-		dev->isCheckpointed = 1;
-	 else
-		dev->isCheckpointed = 0;
+	yaffs_strcpy(old_name, _Y("silly old name"));
 
-	return dev->isCheckpointed;
-}
+	if (in->fake && in != dev->root_dir && !force && !xmod)
+		return ret_val;
 
-static int yaffs_ReadCheckpointData(yaffs_Device *dev)
-{
-	int ok = 1;
+	yaffs_check_gc(dev, 0);
+	yaffs_check_obj_details_loaded(in);
 
-	if(dev->skipCheckpointRead || !dev->isYaffs2){
-		T(YAFFS_TRACE_CHECKPOINT,(TSTR("skipping checkpoint read" TENDSTR)));
-		ok = 0;
-	}
+	buffer = yaffs_get_temp_buffer(in->my_dev);
+	oh = (struct yaffs_obj_hdr *)buffer;
 
-	if(ok)
-		ok = yaffs_CheckpointOpen(dev,0); /* open for read */
+	prev_chunk_id = in->hdr_chunk;
 
-	if(ok){
-		T(YAFFS_TRACE_CHECKPOINT,(TSTR("read checkpoint validity" TENDSTR)));
-		ok = yaffs_ReadCheckpointValidityMarker(dev,1);
-	}
-	if(ok){
-		T(YAFFS_TRACE_CHECKPOINT,(TSTR("read checkpoint device" TENDSTR)));
-		ok = yaffs_ReadCheckpointDevice(dev);
-	}
-	if(ok){
-		T(YAFFS_TRACE_CHECKPOINT,(TSTR("read checkpoint objects" TENDSTR)));
-		ok = yaffs_ReadCheckpointObjects(dev);
-	}
-	if(ok){
-		T(YAFFS_TRACE_CHECKPOINT,(TSTR("read checkpoint validity" TENDSTR)));
-		ok = yaffs_ReadCheckpointValidityMarker(dev,0);
-	}
+	if (prev_chunk_id > 0) {
+		yaffs_rd_chunk_tags_nand(dev, prev_chunk_id,
+					  buffer, &old_tags);
 
-	if(ok){
-		ok = yaffs_ReadCheckpointSum(dev);
-		T(YAFFS_TRACE_CHECKPOINT,(TSTR("read checkpoint checksum %d" TENDSTR),ok));
+		yaffs_verify_oh(in, oh, &old_tags, 0);
+		memcpy(old_name, oh->name, sizeof(oh->name));
+		memset(buffer, 0xff, sizeof(struct yaffs_obj_hdr));
+	} else {
+		memset(buffer, 0xff, dev->data_bytes_per_chunk);
 	}
 
-	if(!yaffs_CheckpointClose(dev))
-		ok = 0;
-
-	if(ok)
-		dev->isCheckpointed = 1;
-	 else
-		dev->isCheckpointed = 0;
+	oh->type = in->variant_type;
+	oh->yst_mode = in->yst_mode;
+	oh->shadows_obj = oh->inband_shadowed_obj_id = shadows;
 
-	return ok ? 1 : 0;
+	yaffs_load_attribs_oh(oh, in);
 
-}
+	if (in->parent)
+		oh->parent_obj_id = in->parent->obj_id;
+	else
+		oh->parent_obj_id = 0;
 
-static void yaffs_InvalidateCheckpoint(yaffs_Device *dev)
-{
-	if(dev->isCheckpointed ||
-	   dev->blocksInCheckpoint > 0){
-		dev->isCheckpointed = 0;
-		yaffs_CheckpointInvalidateStream(dev);
-		if(dev->superBlock && dev->markSuperBlockDirty)
-			dev->markSuperBlockDirty(dev->superBlock);
+	if (name && *name) {
+		memset(oh->name, 0, sizeof(oh->name));
+		yaffs_load_oh_from_name(dev, oh->name, name);
+	} else if (prev_chunk_id > 0) {
+		memcpy(oh->name, old_name, sizeof(oh->name));
+	} else {
+		memset(oh->name, 0, sizeof(oh->name));
 	}
-}
-
 
-int yaffs_CheckpointSave(yaffs_Device *dev)
-{
+	oh->is_shrink = is_shrink;
 
-	T(YAFFS_TRACE_CHECKPOINT,(TSTR("save entry: isCheckpointed %d"TENDSTR),dev->isCheckpointed));
+	switch (in->variant_type) {
+	case YAFFS_OBJECT_TYPE_UNKNOWN:
+		/* Should not happen */
+		break;
+	case YAFFS_OBJECT_TYPE_FILE:
+		if (oh->parent_obj_id != YAFFS_OBJECTID_DELETED &&
+		    oh->parent_obj_id != YAFFS_OBJECTID_UNLINKED)
+			file_size = in->variant.file_variant.file_size;
+		yaffs_oh_size_load(oh, file_size);
+		break;
+	case YAFFS_OBJECT_TYPE_HARDLINK:
+		oh->equiv_id = in->variant.hardlink_variant.equiv_id;
+		break;
+	case YAFFS_OBJECT_TYPE_SPECIAL:
+		/* Do nothing */
+		break;
+	case YAFFS_OBJECT_TYPE_DIRECTORY:
+		/* Do nothing */
+		break;
+	case YAFFS_OBJECT_TYPE_SYMLINK:
+		alias = in->variant.symlink_variant.alias;
+		if (!alias)
+			alias = _Y("no alias");
+		yaffs_strncpy(oh->alias, alias, YAFFS_MAX_ALIAS_LENGTH);
+		oh->alias[YAFFS_MAX_ALIAS_LENGTH] = 0;
+		break;
+	}
 
-	yaffs_VerifyObjects(dev);
-	yaffs_VerifyBlocks(dev);
-	yaffs_VerifyFreeChunks(dev);
+	/* process any xattrib modifications */
+	if (xmod)
+		yaffs_apply_xattrib_mod(in, (char *)buffer, xmod);
+
+	/* Tags */
+	memset(&new_tags, 0, sizeof(new_tags));
+	in->serial++;
+	new_tags.chunk_id = 0;
+	new_tags.obj_id = in->obj_id;
+	new_tags.serial_number = in->serial;
+
+	/* Add extra info for file header */
+	new_tags.extra_available = 1;
+	new_tags.extra_parent_id = oh->parent_obj_id;
+	new_tags.extra_file_size = file_size;
+	new_tags.extra_is_shrink = oh->is_shrink;
+	new_tags.extra_equiv_id = oh->equiv_id;
+	new_tags.extra_shadows = (oh->shadows_obj > 0) ? 1 : 0;
+	new_tags.extra_obj_type = in->variant_type;
+	yaffs_verify_oh(in, oh, &new_tags, 1);
+
+	/* Create new chunk in NAND */
+	new_chunk_id =
+	    yaffs_write_new_chunk(dev, buffer, &new_tags,
+				  (prev_chunk_id > 0) ? 1 : 0);
 
-	if(!dev->isCheckpointed) {
-		yaffs_InvalidateCheckpoint(dev);
-		yaffs_WriteCheckpointData(dev);
-	}
+	if (buffer)
+		yaffs_release_temp_buffer(dev, buffer);
 
-	T(YAFFS_TRACE_ALWAYS,(TSTR("save exit: isCheckpointed %d"TENDSTR),dev->isCheckpointed));
+	if (new_chunk_id < 0)
+		return new_chunk_id;
 
-	return dev->isCheckpointed;
-}
+	in->hdr_chunk = new_chunk_id;
 
-int yaffs_CheckpointRestore(yaffs_Device *dev)
-{
-	int retval;
-	T(YAFFS_TRACE_CHECKPOINT,(TSTR("restore entry: isCheckpointed %d"TENDSTR),dev->isCheckpointed));
+	if (prev_chunk_id > 0)
+		yaffs_chunk_del(dev, prev_chunk_id, 1, __LINE__);
 
-	retval = yaffs_ReadCheckpointData(dev);
+	if (!yaffs_obj_cache_dirty(in))
+		in->dirty = 0;
 
-	if(dev->isCheckpointed){
-		yaffs_VerifyObjects(dev);
-		yaffs_VerifyBlocks(dev);
-		yaffs_VerifyFreeChunks(dev);
+	/* If this was a shrink, then mark the block
+	 * that the chunk lives on */
+	if (is_shrink) {
+		bi = yaffs_get_block_info(in->my_dev,
+					  new_chunk_id /
+					  in->my_dev->param.chunks_per_block);
+		bi->has_shrink_hdr = 1;
 	}
 
-	T(YAFFS_TRACE_CHECKPOINT,(TSTR("restore exit: isCheckpointed %d"TENDSTR),dev->isCheckpointed));
 
-	return retval;
+	return new_chunk_id;
 }
 
 /*--------------------- File read/write ------------------------
@@ -4447,622 +3422,550 @@ int yaffs_CheckpointRestore(yaffs_Device *dev)
  * Curve-balls: the first chunk might also be the last chunk.
  */
 
-int yaffs_ReadDataFromFile(yaffs_Object * in, __u8 * buffer, loff_t offset,
-			   int nBytes)
+int yaffs_file_rd(struct yaffs_obj *in, u8 * buffer, loff_t offset, int n_bytes)
 {
+	int chunk;
+	u32 start;
+	int n_copy;
+	int n = n_bytes;
+	int n_done = 0;
+	struct yaffs_cache *cache;
+	struct yaffs_dev *dev;
 
-	__u32 chunk = 0;
-	__u32 start = 0;
-	int nToCopy;
-	int n = nBytes;
-	int nDone = 0;
-	yaffs_ChunkCache *cache;
-
-	yaffs_Device *dev;
-
-	dev = in->myDev;
+	dev = in->my_dev;
 
 	while (n > 0) {
-		//chunk = offset / dev->nDataBytesPerChunk + 1;
-		//start = offset % dev->nDataBytesPerChunk;
-		yaffs_AddrToChunk(dev,offset,&chunk,&start);
+		yaffs_addr_to_chunk(dev, offset, &chunk, &start);
 		chunk++;
 
 		/* OK now check for the curveball where the start and end are in
 		 * the same chunk.
 		 */
-		if ((start + n) < dev->nDataBytesPerChunk) {
-			nToCopy = n;
-		} else {
-			nToCopy = dev->nDataBytesPerChunk - start;
-		}
+		if ((start + n) < dev->data_bytes_per_chunk)
+			n_copy = n;
+		else
+			n_copy = dev->data_bytes_per_chunk - start;
 
-		cache = yaffs_FindChunkCache(in, chunk);
+		cache = yaffs_find_chunk_cache(in, chunk);
 
-		/* If the chunk is already in the cache or it is less than a whole chunk
-		 * then use the cache (if there is caching)
-		 * else bypass the cache.
+		/* If the chunk is already in the cache or it is less than
+		 * a whole chunk or we're using inband tags then use the cache
+		 * (if there is caching) else bypass the cache.
 		 */
-		if (cache || nToCopy != dev->nDataBytesPerChunk) {
-			if (dev->nShortOpCaches > 0) {
+		if (cache || n_copy != dev->data_bytes_per_chunk ||
+		    dev->param.inband_tags) {
+			if (dev->param.n_caches > 0) {
 
-				/* If we can't find the data in the cache, then load it up. */
+				/* If we can't find the data in the cache,
+				 * then load it up. */
 
 				if (!cache) {
-					cache = yaffs_GrabChunkCache(in->myDev);
+					cache =
+					    yaffs_grab_chunk_cache(in->my_dev);
 					cache->object = in;
-					cache->chunkId = chunk;
+					cache->chunk_id = chunk;
 					cache->dirty = 0;
 					cache->locked = 0;
-					yaffs_ReadChunkDataFromObject(in, chunk,
-								      cache->
-								      data);
-					cache->nBytes = 0;
+					yaffs_rd_data_obj(in, chunk,
+							  cache->data);
+					cache->n_bytes = 0;
 				}
 
-				yaffs_UseChunkCache(dev, cache, 0);
+				yaffs_use_cache(dev, cache, 0);
 
 				cache->locked = 1;
 
-#ifdef CONFIG_YAFFS_WINCE
-				yfsd_UnlockYAFFS(TRUE);
-#endif
-				memcpy(buffer, &cache->data[start], nToCopy);
+				memcpy(buffer, &cache->data[start], n_copy);
 
-#ifdef CONFIG_YAFFS_WINCE
-				yfsd_LockYAFFS(TRUE);
-#endif
 				cache->locked = 0;
 			} else {
-				/* Read into the local buffer then copy..*/
-
-				__u8 *localBuffer =
-				    yaffs_GetTempBuffer(dev, __LINE__);
-				yaffs_ReadChunkDataFromObject(in, chunk,
-							      localBuffer);
-#ifdef CONFIG_YAFFS_WINCE
-				yfsd_UnlockYAFFS(TRUE);
-#endif
-				memcpy(buffer, &localBuffer[start], nToCopy);
-
-#ifdef CONFIG_YAFFS_WINCE
-				yfsd_LockYAFFS(TRUE);
-#endif
-				yaffs_ReleaseTempBuffer(dev, localBuffer,
-							__LINE__);
-			}
-
-		} else {
-#ifdef CONFIG_YAFFS_WINCE
-			__u8 *localBuffer = yaffs_GetTempBuffer(dev, __LINE__);
+				/* Read into the local buffer then copy.. */
 
-			/* Under WinCE can't do direct transfer. Need to use a local buffer.
-			 * This is because we otherwise screw up WinCE's memory mapper
-			 */
-			yaffs_ReadChunkDataFromObject(in, chunk, localBuffer);
+				u8 *local_buffer =
+				    yaffs_get_temp_buffer(dev);
+				yaffs_rd_data_obj(in, chunk, local_buffer);
 
-#ifdef CONFIG_YAFFS_WINCE
-			yfsd_UnlockYAFFS(TRUE);
-#endif
-			memcpy(buffer, localBuffer, dev->nDataBytesPerChunk);
-
-#ifdef CONFIG_YAFFS_WINCE
-			yfsd_LockYAFFS(TRUE);
-			yaffs_ReleaseTempBuffer(dev, localBuffer, __LINE__);
-#endif
+				memcpy(buffer, &local_buffer[start], n_copy);
 
-#else
-			/* A full chunk. Read directly into the supplied buffer. */
-			yaffs_ReadChunkDataFromObject(in, chunk, buffer);
-#endif
+				yaffs_release_temp_buffer(dev, local_buffer);
+			}
+		} else {
+			/* A full chunk. Read directly into the buffer. */
+			yaffs_rd_data_obj(in, chunk, buffer);
 		}
-
-		n -= nToCopy;
-		offset += nToCopy;
-		buffer += nToCopy;
-		nDone += nToCopy;
-
+		n -= n_copy;
+		offset += n_copy;
+		buffer += n_copy;
+		n_done += n_copy;
 	}
-
-	return nDone;
+	return n_done;
 }
 
-int yaffs_WriteDataToFile(yaffs_Object * in, const __u8 * buffer, loff_t offset,
-			  int nBytes, int writeThrough)
+int yaffs_do_file_wr(struct yaffs_obj *in, const u8 *buffer, loff_t offset,
+		     int n_bytes, int write_through)
 {
 
-	__u32 chunk = 0;
-	__u32 start = 0;
-	int nToCopy;
-	int n = nBytes;
-	int nDone = 0;
-	int nToWriteBack;
-	int startOfWrite = offset;
-	int chunkWritten = 0;
-	int nBytesRead;
-
-	yaffs_Device *dev;
-
-	dev = in->myDev;
-
-	while (n > 0 && chunkWritten >= 0) {
-		//chunk = offset / dev->nDataBytesPerChunk + 1;
-		//start = offset % dev->nDataBytesPerChunk;
-		yaffs_AddrToChunk(dev,offset,&chunk,&start);
-		chunk++;
+	int chunk;
+	u32 start;
+	int n_copy;
+	int n = n_bytes;
+	int n_done = 0;
+	int n_writeback;
+	loff_t start_write = offset;
+	int chunk_written = 0;
+	u32 n_bytes_read;
+	loff_t chunk_start;
+	struct yaffs_dev *dev;
+
+	dev = in->my_dev;
+
+	while (n > 0 && chunk_written >= 0) {
+		yaffs_addr_to_chunk(dev, offset, &chunk, &start);
+
+		if (((loff_t)chunk) *
+		    dev->data_bytes_per_chunk + start != offset ||
+		    start >= dev->data_bytes_per_chunk) {
+			yaffs_trace(YAFFS_TRACE_ERROR,
+				"AddrToChunk of offset %lld gives chunk %d start %d",
+				offset, chunk, start);
+		}
+		chunk++;	/* File pos to chunk in file offset */
 
 		/* OK now check for the curveball where the start and end are in
 		 * the same chunk.
 		 */
 
-		if ((start + n) < dev->nDataBytesPerChunk) {
-			nToCopy = n;
+		if ((start + n) < dev->data_bytes_per_chunk) {
+			n_copy = n;
 
-			/* Now folks, to calculate how many bytes to write back....
-			 * If we're overwriting and not writing to then end of file then
-			 * we need to write back as much as was there before.
+			/* Now calculate how many bytes to write back....
+			 * If we're overwriting and not writing to then end of
+			 * file then we need to write back as much as was there
+			 * before.
 			 */
 
-			nBytesRead =
-			    in->variant.fileVariant.fileSize -
-			    ((chunk - 1) * dev->nDataBytesPerChunk);
+			chunk_start = (((loff_t)(chunk - 1)) *
+					dev->data_bytes_per_chunk);
 
-			if (nBytesRead > dev->nDataBytesPerChunk) {
-				nBytesRead = dev->nDataBytesPerChunk;
-			}
+			if (chunk_start > in->variant.file_variant.file_size)
+				n_bytes_read = 0;	/* Past end of file */
+			else
+				n_bytes_read =
+				    in->variant.file_variant.file_size -
+				    chunk_start;
+
+			if (n_bytes_read > dev->data_bytes_per_chunk)
+				n_bytes_read = dev->data_bytes_per_chunk;
 
-			nToWriteBack =
-			    (nBytesRead >
-			     (start + n)) ? nBytesRead : (start + n);
+			n_writeback =
+			    (n_bytes_read >
+			     (start + n)) ? n_bytes_read : (start + n);
+
+			if (n_writeback < 0 ||
+			    n_writeback > dev->data_bytes_per_chunk)
+				BUG();
 
 		} else {
-			nToCopy = dev->nDataBytesPerChunk - start;
-			nToWriteBack = dev->nDataBytesPerChunk;
+			n_copy = dev->data_bytes_per_chunk - start;
+			n_writeback = dev->data_bytes_per_chunk;
 		}
 
-		if (nToCopy != dev->nDataBytesPerChunk) {
-			/* An incomplete start or end chunk (or maybe both start and end chunk) */
-			if (dev->nShortOpCaches > 0) {
-				yaffs_ChunkCache *cache;
-				/* If we can't find the data in the cache, then load the cache */
-				cache = yaffs_FindChunkCache(in, chunk);
-
-				if (!cache
-				    && yaffs_CheckSpaceForAllocation(in->
-								     myDev)) {
-					cache = yaffs_GrabChunkCache(in->myDev);
+		if (n_copy != dev->data_bytes_per_chunk ||
+		    dev->param.inband_tags) {
+			/* An incomplete start or end chunk (or maybe both
+			 * start and end chunk), or we're using inband tags,
+			 * so we want to use the cache buffers.
+			 */
+			if (dev->param.n_caches > 0) {
+				struct yaffs_cache *cache;
+
+				/* If we can't find the data in the cache, then
+				 * load the cache */
+				cache = yaffs_find_chunk_cache(in, chunk);
+
+				if (!cache &&
+				    yaffs_check_alloc_available(dev, 1)) {
+					cache = yaffs_grab_chunk_cache(dev);
 					cache->object = in;
-					cache->chunkId = chunk;
+					cache->chunk_id = chunk;
 					cache->dirty = 0;
 					cache->locked = 0;
-					yaffs_ReadChunkDataFromObject(in, chunk,
-								      cache->
-								      data);
-				}
-				else if(cache &&
-					!cache->dirty &&
-					!yaffs_CheckSpaceForAllocation(in->myDev)){
-					/* Drop the cache if it was a read cache item and
-					 * no space check has been made for it.
+					yaffs_rd_data_obj(in, chunk,
+							  cache->data);
+				} else if (cache &&
+					   !cache->dirty &&
+					   !yaffs_check_alloc_available(dev,
+									1)) {
+					/* Drop the cache if it was a read cache
+					 * item and no space check has been made
+					 * for it.
 					 */
-					 cache = NULL;
+					cache = NULL;
 				}
 
 				if (cache) {
-					yaffs_UseChunkCache(dev, cache, 1);
+					yaffs_use_cache(dev, cache, 1);
 					cache->locked = 1;
-#ifdef CONFIG_YAFFS_WINCE
-					yfsd_UnlockYAFFS(TRUE);
-#endif
 
 					memcpy(&cache->data[start], buffer,
-					       nToCopy);
+					       n_copy);
 
-#ifdef CONFIG_YAFFS_WINCE
-					yfsd_LockYAFFS(TRUE);
-#endif
 					cache->locked = 0;
-					cache->nBytes = nToWriteBack;
+					cache->n_bytes = n_writeback;
 
-					if (writeThrough) {
-						chunkWritten =
-						    yaffs_WriteChunkDataToObject
+					if (write_through) {
+						chunk_written =
+						    yaffs_wr_data_obj
 						    (cache->object,
-						     cache->chunkId,
-						     cache->data, cache->nBytes,
-						     1);
+						     cache->chunk_id,
+						     cache->data,
+						     cache->n_bytes, 1);
 						cache->dirty = 0;
 					}
-
 				} else {
-					chunkWritten = -1;	/* fail the write */
+					chunk_written = -1;	/* fail write */
 				}
 			} else {
-				/* An incomplete start or end chunk (or maybe both start and end chunk)
-				 * Read into the local buffer then copy, then copy over and write back.
+				/* An incomplete start or end chunk (or maybe
+				 * both start and end chunk). Read into the
+				 * local buffer then copy over and write back.
 				 */
 
-				__u8 *localBuffer =
-				    yaffs_GetTempBuffer(dev, __LINE__);
+				u8 *local_buffer = yaffs_get_temp_buffer(dev);
 
-				yaffs_ReadChunkDataFromObject(in, chunk,
-							      localBuffer);
+				yaffs_rd_data_obj(in, chunk, local_buffer);
+				memcpy(&local_buffer[start], buffer, n_copy);
 
-#ifdef CONFIG_YAFFS_WINCE
-				yfsd_UnlockYAFFS(TRUE);
-#endif
-
-				memcpy(&localBuffer[start], buffer, nToCopy);
-
-#ifdef CONFIG_YAFFS_WINCE
-				yfsd_LockYAFFS(TRUE);
-#endif
-				chunkWritten =
-				    yaffs_WriteChunkDataToObject(in, chunk,
-								 localBuffer,
-								 nToWriteBack,
-								 0);
-
-				yaffs_ReleaseTempBuffer(dev, localBuffer,
-							__LINE__);
+				chunk_written =
+				    yaffs_wr_data_obj(in, chunk,
+						      local_buffer,
+						      n_writeback, 0);
 
+				yaffs_release_temp_buffer(dev, local_buffer);
 			}
-
 		} else {
+			/* A full chunk. Write directly from the buffer. */
 
-#ifdef CONFIG_YAFFS_WINCE
-			/* Under WinCE can't do direct transfer. Need to use a local buffer.
-			 * This is because we otherwise screw up WinCE's memory mapper
-			 */
-			__u8 *localBuffer = yaffs_GetTempBuffer(dev, __LINE__);
-#ifdef CONFIG_YAFFS_WINCE
-			yfsd_UnlockYAFFS(TRUE);
-#endif
-			memcpy(localBuffer, buffer, dev->nDataBytesPerChunk);
-#ifdef CONFIG_YAFFS_WINCE
-			yfsd_LockYAFFS(TRUE);
-#endif
-			chunkWritten =
-			    yaffs_WriteChunkDataToObject(in, chunk, localBuffer,
-							 dev->nDataBytesPerChunk,
-							 0);
-			yaffs_ReleaseTempBuffer(dev, localBuffer, __LINE__);
-#else
-			/* A full chunk. Write directly from the supplied buffer. */
-			chunkWritten =
-			    yaffs_WriteChunkDataToObject(in, chunk, buffer,
-							 dev->nDataBytesPerChunk,
-							 0);
-#endif
-			/* Since we've overwritten the cached data, we better invalidate it. */
-			yaffs_InvalidateChunkCache(in, chunk);
-		}
+			chunk_written =
+			    yaffs_wr_data_obj(in, chunk, buffer,
+					      dev->data_bytes_per_chunk, 0);
 
-		if (chunkWritten >= 0) {
-			n -= nToCopy;
-			offset += nToCopy;
-			buffer += nToCopy;
-			nDone += nToCopy;
+			/* Since we've overwritten the cached data,
+			 * we better invalidate it. */
+			yaffs_invalidate_chunk_cache(in, chunk);
 		}
 
+		if (chunk_written >= 0) {
+			n -= n_copy;
+			offset += n_copy;
+			buffer += n_copy;
+			n_done += n_copy;
+		}
 	}
 
 	/* Update file object */
 
-	if ((startOfWrite + nDone) > in->variant.fileVariant.fileSize) {
-		in->variant.fileVariant.fileSize = (startOfWrite + nDone);
-	}
+	if ((start_write + n_done) > in->variant.file_variant.file_size)
+		in->variant.file_variant.file_size = (start_write + n_done);
 
 	in->dirty = 1;
-
-	return nDone;
+	return n_done;
 }
 
+int yaffs_wr_file(struct yaffs_obj *in, const u8 *buffer, loff_t offset,
+		  int n_bytes, int write_through)
+{
+	yaffs2_handle_hole(in, offset);
+	return yaffs_do_file_wr(in, buffer, offset, n_bytes, write_through);
+}
 
 /* ---------------------- File resizing stuff ------------------ */
 
-static void yaffs_PruneResizedChunks(yaffs_Object * in, int newSize)
+static void yaffs_prune_chunks(struct yaffs_obj *in, loff_t new_size)
 {
 
-	yaffs_Device *dev = in->myDev;
-	int oldFileSize = in->variant.fileVariant.fileSize;
+	struct yaffs_dev *dev = in->my_dev;
+	loff_t old_size = in->variant.file_variant.file_size;
+	int i;
+	int chunk_id;
+	u32 dummy;
+	int last_del;
+	int start_del;
 
-	int lastDel = 1 + (oldFileSize - 1) / dev->nDataBytesPerChunk;
+	if (old_size > 0)
+		yaffs_addr_to_chunk(dev, old_size - 1, &last_del, &dummy);
+	else
+		last_del = 0;
 
-	int startDel = 1 + (newSize + dev->nDataBytesPerChunk - 1) /
-	    dev->nDataBytesPerChunk;
-	int i;
-	int chunkId;
+	yaffs_addr_to_chunk(dev, new_size + dev->data_bytes_per_chunk - 1,
+				&start_del, &dummy);
+	last_del++;
+	start_del++;
 
 	/* Delete backwards so that we don't end up with holes if
 	 * power is lost part-way through the operation.
 	 */
-	for (i = lastDel; i >= startDel; i--) {
+	for (i = last_del; i >= start_del; i--) {
 		/* NB this could be optimised somewhat,
 		 * eg. could retrieve the tags and write them without
-		 * using yaffs_DeleteChunk
+		 * using yaffs_chunk_del
 		 */
 
-		chunkId = yaffs_FindAndDeleteChunkInFile(in, i, NULL);
-		if (chunkId > 0) {
-			if (chunkId <
-			    (dev->internalStartBlock * dev->nChunksPerBlock)
-			    || chunkId >=
-			    ((dev->internalEndBlock +
-			      1) * dev->nChunksPerBlock)) {
-				T(YAFFS_TRACE_ALWAYS,
-				  (TSTR("Found daft chunkId %d for %d" TENDSTR),
-				   chunkId, i));
-			} else {
-				in->nDataChunks--;
-				yaffs_DeleteChunk(dev, chunkId, 1, __LINE__);
-			}
+		chunk_id = yaffs_find_del_file_chunk(in, i, NULL);
+
+		if (chunk_id < 1)
+			continue;
+
+		if (chunk_id <
+		    (dev->internal_start_block * dev->param.chunks_per_block) ||
+		    chunk_id >=
+		    ((dev->internal_end_block + 1) *
+		      dev->param.chunks_per_block)) {
+			yaffs_trace(YAFFS_TRACE_ALWAYS,
+				"Found daft chunk_id %d for %d",
+				chunk_id, i);
+		} else {
+			in->n_data_chunks--;
+			yaffs_chunk_del(dev, chunk_id, 1, __LINE__);
 		}
 	}
-
 }
 
-int yaffs_ResizeFile(yaffs_Object * in, loff_t newSize)
+void yaffs_resize_file_down(struct yaffs_obj *obj, loff_t new_size)
 {
+	int new_full;
+	u32 new_partial;
+	struct yaffs_dev *dev = obj->my_dev;
 
-	int oldFileSize = in->variant.fileVariant.fileSize;
-	__u32 newSizeOfPartialChunk = 0;
-	__u32 newFullChunks = 0;
-
-	yaffs_Device *dev = in->myDev;
+	yaffs_addr_to_chunk(dev, new_size, &new_full, &new_partial);
 
-	yaffs_AddrToChunk(dev, newSize, &newFullChunks, &newSizeOfPartialChunk);
+	yaffs_prune_chunks(obj, new_size);
 
-	yaffs_FlushFilesChunkCache(in);
-	yaffs_InvalidateWholeChunkCache(in);
+	if (new_partial != 0) {
+		int last_chunk = 1 + new_full;
+		u8 *local_buffer = yaffs_get_temp_buffer(dev);
 
-	yaffs_CheckGarbageCollection(dev);
+		/* Rewrite the last chunk with its new size and zero pad */
+		yaffs_rd_data_obj(obj, last_chunk, local_buffer);
+		memset(local_buffer + new_partial, 0,
+		       dev->data_bytes_per_chunk - new_partial);
 
-	if (in->variantType != YAFFS_OBJECT_TYPE_FILE) {
-		return yaffs_GetFileSize(in);
-	}
+		yaffs_wr_data_obj(obj, last_chunk, local_buffer,
+				  new_partial, 1);
 
-	if (newSize == oldFileSize) {
-		return oldFileSize;
+		yaffs_release_temp_buffer(dev, local_buffer);
 	}
 
-	if (newSize < oldFileSize) {
-
-		yaffs_PruneResizedChunks(in, newSize);
+	obj->variant.file_variant.file_size = new_size;
 
-		if (newSizeOfPartialChunk != 0) {
-			int lastChunk = 1 + newFullChunks;
-
-			__u8 *localBuffer = yaffs_GetTempBuffer(dev, __LINE__);
+	yaffs_prune_tree(dev, &obj->variant.file_variant);
+}
 
-			/* Got to read and rewrite the last chunk with its new size and zero pad */
-			yaffs_ReadChunkDataFromObject(in, lastChunk,
-						      localBuffer);
+int yaffs_resize_file(struct yaffs_obj *in, loff_t new_size)
+{
+	struct yaffs_dev *dev = in->my_dev;
+	loff_t old_size = in->variant.file_variant.file_size;
 
-			memset(localBuffer + newSizeOfPartialChunk, 0,
-			       dev->nDataBytesPerChunk - newSizeOfPartialChunk);
+	yaffs_flush_file_cache(in);
+	yaffs_invalidate_whole_cache(in);
 
-			yaffs_WriteChunkDataToObject(in, lastChunk, localBuffer,
-						     newSizeOfPartialChunk, 1);
+	yaffs_check_gc(dev, 0);
 
-			yaffs_ReleaseTempBuffer(dev, localBuffer, __LINE__);
-		}
+	if (in->variant_type != YAFFS_OBJECT_TYPE_FILE)
+		return YAFFS_FAIL;
 
-		in->variant.fileVariant.fileSize = newSize;
+	if (new_size == old_size)
+		return YAFFS_OK;
 
-		yaffs_PruneFileStructure(dev, &in->variant.fileVariant);
+	if (new_size > old_size) {
+		yaffs2_handle_hole(in, new_size);
+		in->variant.file_variant.file_size = new_size;
 	} else {
-		/* newsSize > oldFileSize */
-		in->variant.fileVariant.fileSize = newSize;
+		/* new_size < old_size */
+		yaffs_resize_file_down(in, new_size);
 	}
 
-
-
-	/* Write a new object header.
+	/* Write a new object header to reflect the resize.
 	 * show we've shrunk the file, if need be
-	 * Do this only if the file is not in the deleted directories.
+	 * Do this only if the file is not in the deleted directories
+	 * and is not shadowed.
 	 */
-	if (in->parent->objectId != YAFFS_OBJECTID_UNLINKED &&
-	    in->parent->objectId != YAFFS_OBJECTID_DELETED) {
-		yaffs_UpdateObjectHeader(in, NULL, 0,
-					 (newSize < oldFileSize) ? 1 : 0, 0);
-	}
+	if (in->parent &&
+	    !in->is_shadowed &&
+	    in->parent->obj_id != YAFFS_OBJECTID_UNLINKED &&
+	    in->parent->obj_id != YAFFS_OBJECTID_DELETED)
+		yaffs_update_oh(in, NULL, 0, 0, 0, NULL);
 
 	return YAFFS_OK;
 }
 
-loff_t yaffs_GetFileSize(yaffs_Object * obj)
-{
-	obj = yaffs_GetEquivalentObject(obj);
-
-	switch (obj->variantType) {
-	case YAFFS_OBJECT_TYPE_FILE:
-		return obj->variant.fileVariant.fileSize;
-	case YAFFS_OBJECT_TYPE_SYMLINK:
-		return yaffs_strlen(obj->variant.symLinkVariant.alias);
-	default:
-		return 0;
-	}
-}
-
-
-
-int yaffs_FlushFile(yaffs_Object * in, int updateTime)
+int yaffs_flush_file(struct yaffs_obj *in, int update_time, int data_sync)
 {
-	int retVal;
-	if (in->dirty) {
-		yaffs_FlushFilesChunkCache(in);
-		if (updateTime) {
-#ifdef CONFIG_YAFFS_WINCE
-			yfsd_WinFileTimeNow(in->win_mtime);
-#else
-
-			in->yst_mtime = Y_CURRENT_TIME;
+	if (!in->dirty)
+		return YAFFS_OK;
 
-#endif
-		}
+	yaffs_flush_file_cache(in);
 
-		retVal =
-		    (yaffs_UpdateObjectHeader(in, NULL, 0, 0, 0) >=
-		     0) ? YAFFS_OK : YAFFS_FAIL;
-	} else {
-		retVal = YAFFS_OK;
-	}
+	if (data_sync)
+		return YAFFS_OK;
 
-	return retVal;
+	if (update_time)
+		yaffs_load_current_time(in, 0, 0);
 
+	return (yaffs_update_oh(in, NULL, 0, 0, 0, NULL) >= 0) ?
+				YAFFS_OK : YAFFS_FAIL;
 }
 
-static int yaffs_DoGenericObjectDeletion(yaffs_Object * in)
-{
 
-	/* First off, invalidate the file's data in the cache, without flushing. */
-	yaffs_InvalidateWholeChunkCache(in);
-
-	if (in->myDev->isYaffs2 && (in->parent != in->myDev->deletedDir)) {
-		/* Move to the unlinked directory so we have a record that it was deleted. */
-		yaffs_ChangeObjectName(in, in->myDev->deletedDir,"deleted", 0, 0);
-
-	}
-
-	yaffs_RemoveObjectFromDirectory(in);
-	yaffs_DeleteChunk(in->myDev, in->chunkId, 1, __LINE__);
-	in->chunkId = -1;
-
-	yaffs_FreeObject(in);
-	return YAFFS_OK;
-
-}
-
-/* yaffs_DeleteFile deletes the whole file data
+/* yaffs_del_file deletes the whole file data
  * and the inode associated with the file.
  * It does not delete the links associated with the file.
  */
-static int yaffs_UnlinkFile(yaffs_Object * in)
-{
-
-	int retVal;
-	int immediateDeletion = 0;
-
-	if (1) {
-/* XXX U-BOOT XXX */
-#if 0
-#ifdef __KERNEL__
-		if (!in->myInode) {
-			immediateDeletion = 1;
-
-		}
-#endif
-#else
-		if (in->inUse <= 0) {
-			immediateDeletion = 1;
-
-		}
-#endif
-		if (immediateDeletion) {
-			retVal =
-			    yaffs_ChangeObjectName(in, in->myDev->deletedDir,
-						   "deleted", 0, 0);
-			T(YAFFS_TRACE_TRACING,
-			  (TSTR("yaffs: immediate deletion of file %d" TENDSTR),
-			   in->objectId));
-			in->deleted = 1;
-			in->myDev->nDeletedFiles++;
-			if (0 && in->myDev->isYaffs2) {
-				yaffs_ResizeFile(in, 0);
-			}
-			yaffs_SoftDeleteFile(in);
-		} else {
-			retVal =
-			    yaffs_ChangeObjectName(in, in->myDev->unlinkedDir,
-						   "unlinked", 0, 0);
-		}
-
+static int yaffs_unlink_file_if_needed(struct yaffs_obj *in)
+{
+	int ret_val;
+	int del_now = 0;
+	struct yaffs_dev *dev = in->my_dev;
+
+	if (!in->my_inode)
+		del_now = 1;
+
+	if (del_now) {
+		ret_val =
+		    yaffs_change_obj_name(in, in->my_dev->del_dir,
+					  _Y("deleted"), 0, 0);
+		yaffs_trace(YAFFS_TRACE_TRACING,
+			"yaffs: immediate deletion of file %d",
+			in->obj_id);
+		in->deleted = 1;
+		in->my_dev->n_deleted_files++;
+		if (dev->param.disable_soft_del || dev->param.is_yaffs2)
+			yaffs_resize_file(in, 0);
+		yaffs_soft_del_file(in);
+	} else {
+		ret_val =
+		    yaffs_change_obj_name(in, in->my_dev->unlinked_dir,
+					  _Y("unlinked"), 0, 0);
 	}
-	return retVal;
+	return ret_val;
 }
 
-int yaffs_DeleteFile(yaffs_Object * in)
+int yaffs_del_file(struct yaffs_obj *in)
 {
-	int retVal = YAFFS_OK;
+	int ret_val = YAFFS_OK;
+	int deleted;	/* Need to cache value on stack if in is freed */
+	struct yaffs_dev *dev = in->my_dev;
 
-	if (in->nDataChunks > 0) {
-		/* Use soft deletion if there is data in the file */
-		if (!in->unlinked) {
-			retVal = yaffs_UnlinkFile(in);
-		}
-		if (retVal == YAFFS_OK && in->unlinked && !in->deleted) {
+	if (dev->param.disable_soft_del || dev->param.is_yaffs2)
+		yaffs_resize_file(in, 0);
+
+	if (in->n_data_chunks > 0) {
+		/* Use soft deletion if there is data in the file.
+		 * That won't be the case if it has been resized to zero.
+		 */
+		if (!in->unlinked)
+			ret_val = yaffs_unlink_file_if_needed(in);
+
+		deleted = in->deleted;
+
+		if (ret_val == YAFFS_OK && in->unlinked && !in->deleted) {
 			in->deleted = 1;
-			in->myDev->nDeletedFiles++;
-			yaffs_SoftDeleteFile(in);
+			deleted = 1;
+			in->my_dev->n_deleted_files++;
+			yaffs_soft_del_file(in);
 		}
-		return in->deleted ? YAFFS_OK : YAFFS_FAIL;
+		return deleted ? YAFFS_OK : YAFFS_FAIL;
 	} else {
 		/* The file has no data chunks so we toss it immediately */
-		yaffs_FreeTnode(in->myDev, in->variant.fileVariant.top);
-		in->variant.fileVariant.top = NULL;
-		yaffs_DoGenericObjectDeletion(in);
+		yaffs_free_tnode(in->my_dev, in->variant.file_variant.top);
+		in->variant.file_variant.top = NULL;
+		yaffs_generic_obj_del(in);
 
 		return YAFFS_OK;
 	}
 }
 
-static int yaffs_DeleteDirectory(yaffs_Object * in)
+int yaffs_is_non_empty_dir(struct yaffs_obj *obj)
 {
-	/* First check that the directory is empty. */
-	if (list_empty(&in->variant.directoryVariant.children)) {
-		return yaffs_DoGenericObjectDeletion(in);
-	}
+	return (obj &&
+		obj->variant_type == YAFFS_OBJECT_TYPE_DIRECTORY) &&
+		!(list_empty(&obj->variant.dir_variant.children));
+}
 
-	return YAFFS_FAIL;
+static int yaffs_del_dir(struct yaffs_obj *obj)
+{
+	/* First check that the directory is empty. */
+	if (yaffs_is_non_empty_dir(obj))
+		return YAFFS_FAIL;
 
+	return yaffs_generic_obj_del(obj);
 }
 
-static int yaffs_DeleteSymLink(yaffs_Object * in)
+static int yaffs_del_symlink(struct yaffs_obj *in)
 {
-	YFREE(in->variant.symLinkVariant.alias);
+	kfree(in->variant.symlink_variant.alias);
+	in->variant.symlink_variant.alias = NULL;
 
-	return yaffs_DoGenericObjectDeletion(in);
+	return yaffs_generic_obj_del(in);
 }
 
-static int yaffs_DeleteHardLink(yaffs_Object * in)
+static int yaffs_del_link(struct yaffs_obj *in)
 {
-	/* remove this hardlink from the list assocaited with the equivalent
+	/* remove this hardlink from the list associated with the equivalent
 	 * object
 	 */
-	list_del(&in->hardLinks);
-	return yaffs_DoGenericObjectDeletion(in);
+	list_del_init(&in->hard_links);
+	return yaffs_generic_obj_del(in);
 }
 
-static void yaffs_DestroyObject(yaffs_Object * obj)
+int yaffs_del_obj(struct yaffs_obj *obj)
 {
-	switch (obj->variantType) {
+	int ret_val = -1;
+
+	switch (obj->variant_type) {
 	case YAFFS_OBJECT_TYPE_FILE:
-		yaffs_DeleteFile(obj);
+		ret_val = yaffs_del_file(obj);
 		break;
 	case YAFFS_OBJECT_TYPE_DIRECTORY:
-		yaffs_DeleteDirectory(obj);
+		if (!list_empty(&obj->variant.dir_variant.dirty)) {
+			yaffs_trace(YAFFS_TRACE_BACKGROUND,
+				"Remove object %d from dirty directories",
+				obj->obj_id);
+			list_del_init(&obj->variant.dir_variant.dirty);
+		}
+		return yaffs_del_dir(obj);
 		break;
 	case YAFFS_OBJECT_TYPE_SYMLINK:
-		yaffs_DeleteSymLink(obj);
+		ret_val = yaffs_del_symlink(obj);
 		break;
 	case YAFFS_OBJECT_TYPE_HARDLINK:
-		yaffs_DeleteHardLink(obj);
+		ret_val = yaffs_del_link(obj);
 		break;
 	case YAFFS_OBJECT_TYPE_SPECIAL:
-		yaffs_DoGenericObjectDeletion(obj);
+		ret_val = yaffs_generic_obj_del(obj);
 		break;
 	case YAFFS_OBJECT_TYPE_UNKNOWN:
+		ret_val = 0;
 		break;		/* should not happen. */
 	}
+	return ret_val;
 }
 
-static int yaffs_UnlinkWorker(yaffs_Object * obj)
+static int yaffs_unlink_worker(struct yaffs_obj *obj)
 {
+	int del_now = 0;
+
+	if (!obj)
+		return YAFFS_FAIL;
+
+	if (!obj->my_inode)
+		del_now = 1;
 
-	if (obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK) {
-		return yaffs_DeleteHardLink(obj);
-	} else if (!list_empty(&obj->hardLinks)) {
+	yaffs_update_parent(obj->parent);
+
+	if (obj->variant_type == YAFFS_OBJECT_TYPE_HARDLINK) {
+		return yaffs_del_link(obj);
+	} else if (!list_empty(&obj->hard_links)) {
 		/* Curve ball: We're unlinking an object that has a hardlink.
 		 *
 		 * This problem arises because we are not strictly following
@@ -5072,1638 +3975,531 @@ static int yaffs_UnlinkWorker(yaffs_Object * obj)
 		 * Instead, we do the following:
 		 * - Select a hardlink.
 		 * - Unhook it from the hard links
-		 * - Unhook it from its parent directory (so that the rename can work)
+		 * - Move it from its parent directory so that the rename works.
 		 * - Rename the object to the hardlink's name.
 		 * - Delete the hardlink
 		 */
 
-		yaffs_Object *hl;
-		int retVal;
+		struct yaffs_obj *hl;
+		struct yaffs_obj *parent;
+		int ret_val;
 		YCHAR name[YAFFS_MAX_NAME_LENGTH + 1];
 
-		hl = list_entry(obj->hardLinks.next, yaffs_Object, hardLinks);
+		hl = list_entry(obj->hard_links.next, struct yaffs_obj,
+				hard_links);
 
-		list_del_init(&hl->hardLinks);
-		list_del_init(&hl->siblings);
+		yaffs_get_obj_name(hl, name, YAFFS_MAX_NAME_LENGTH + 1);
+		parent = hl->parent;
 
-		yaffs_GetObjectName(hl, name, YAFFS_MAX_NAME_LENGTH + 1);
+		list_del_init(&hl->hard_links);
 
-		retVal = yaffs_ChangeObjectName(obj, hl->parent, name, 0, 0);
+		yaffs_add_obj_to_dir(obj->my_dev->unlinked_dir, hl);
 
-		if (retVal == YAFFS_OK) {
-			retVal = yaffs_DoGenericObjectDeletion(hl);
-		}
-		return retVal;
+		ret_val = yaffs_change_obj_name(obj, parent, name, 0, 0);
 
-	} else {
-		switch (obj->variantType) {
+		if (ret_val == YAFFS_OK)
+			ret_val = yaffs_generic_obj_del(hl);
+
+		return ret_val;
+
+	} else if (del_now) {
+		switch (obj->variant_type) {
 		case YAFFS_OBJECT_TYPE_FILE:
-			return yaffs_UnlinkFile(obj);
+			return yaffs_del_file(obj);
 			break;
 		case YAFFS_OBJECT_TYPE_DIRECTORY:
-			return yaffs_DeleteDirectory(obj);
+			list_del_init(&obj->variant.dir_variant.dirty);
+			return yaffs_del_dir(obj);
 			break;
 		case YAFFS_OBJECT_TYPE_SYMLINK:
-			return yaffs_DeleteSymLink(obj);
+			return yaffs_del_symlink(obj);
 			break;
 		case YAFFS_OBJECT_TYPE_SPECIAL:
-			return yaffs_DoGenericObjectDeletion(obj);
+			return yaffs_generic_obj_del(obj);
 			break;
 		case YAFFS_OBJECT_TYPE_HARDLINK:
 		case YAFFS_OBJECT_TYPE_UNKNOWN:
 		default:
 			return YAFFS_FAIL;
 		}
+	} else if (yaffs_is_non_empty_dir(obj)) {
+		return YAFFS_FAIL;
+	} else {
+		return yaffs_change_obj_name(obj, obj->my_dev->unlinked_dir,
+						_Y("unlinked"), 0, 0);
 	}
 }
 
-
-static int yaffs_UnlinkObject( yaffs_Object *obj)
+static int yaffs_unlink_obj(struct yaffs_obj *obj)
 {
-
-	if (obj && obj->unlinkAllowed) {
-		return yaffs_UnlinkWorker(obj);
-	}
+	if (obj && obj->unlink_allowed)
+		return yaffs_unlink_worker(obj);
 
 	return YAFFS_FAIL;
+}
 
+int yaffs_unlinker(struct yaffs_obj *dir, const YCHAR *name)
+{
+	struct yaffs_obj *obj;
+
+	obj = yaffs_find_by_name(dir, name);
+	return yaffs_unlink_obj(obj);
 }
-int yaffs_Unlink(yaffs_Object * dir, const YCHAR * name)
+
+/* Note:
+ * If old_name is NULL then we take old_dir as the object to be renamed.
+ */
+int yaffs_rename_obj(struct yaffs_obj *old_dir, const YCHAR *old_name,
+		     struct yaffs_obj *new_dir, const YCHAR *new_name)
 {
-	yaffs_Object *obj;
+	struct yaffs_obj *obj = NULL;
+	struct yaffs_obj *existing_target = NULL;
+	int force = 0;
+	int result;
+	struct yaffs_dev *dev;
+
+	if (!old_dir || old_dir->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) {
+		BUG();
+		return YAFFS_FAIL;
+	}
+	if (!new_dir || new_dir->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) {
+		BUG();
+		return YAFFS_FAIL;
+	}
+
+	dev = old_dir->my_dev;
+
+#ifdef CONFIG_YAFFS_CASE_INSENSITIVE
+	/* Special case for case insemsitive systems.
+	 * While look-up is case insensitive, the name isn't.
+	 * Therefore we might want to change x.txt to X.txt
+	 */
+	if (old_dir == new_dir &&
+		old_name && new_name &&
+		yaffs_strcmp(old_name, new_name) == 0)
+		force = 1;
+#endif
+
+	if (yaffs_strnlen(new_name, YAFFS_MAX_NAME_LENGTH + 1) >
+	    YAFFS_MAX_NAME_LENGTH)
+		/* ENAMETOOLONG */
+		return YAFFS_FAIL;
+
+	if (old_name)
+		obj = yaffs_find_by_name(old_dir, old_name);
+	else{
+		obj = old_dir;
+		old_dir = obj->parent;
+	}
+
+	if (obj && obj->rename_allowed) {
+		/* Now handle an existing target, if there is one */
+		existing_target = yaffs_find_by_name(new_dir, new_name);
+		if (yaffs_is_non_empty_dir(existing_target)) {
+			return YAFFS_FAIL;	/* ENOTEMPTY */
+		} else if (existing_target && existing_target != obj) {
+			/* Nuke the target first, using shadowing,
+			 * but only if it isn't the same object.
+			 *
+			 * Note we must disable gc here otherwise it can mess
+			 * up the shadowing.
+			 *
+			 */
+			dev->gc_disable = 1;
+			yaffs_change_obj_name(obj, new_dir, new_name, force,
+					      existing_target->obj_id);
+			existing_target->is_shadowed = 1;
+			yaffs_unlink_obj(existing_target);
+			dev->gc_disable = 0;
+		}
+
+		result = yaffs_change_obj_name(obj, new_dir, new_name, 1, 0);
 
-	obj = yaffs_FindObjectByName(dir, name);
-	return yaffs_UnlinkObject(obj);
+		yaffs_update_parent(old_dir);
+		if (new_dir != old_dir)
+			yaffs_update_parent(new_dir);
+
+		return result;
+	}
+	return YAFFS_FAIL;
 }
 
 /*----------------------- Initialisation Scanning ---------------------- */
 
-static void yaffs_HandleShadowedObject(yaffs_Device * dev, int objId,
-				       int backwardScanning)
+void yaffs_handle_shadowed_obj(struct yaffs_dev *dev, int obj_id,
+			       int backward_scanning)
 {
-	yaffs_Object *obj;
-
-	if (!backwardScanning) {
-		/* Handle YAFFS1 forward scanning case
-		 * For YAFFS1 we always do the deletion
-		 */
+	struct yaffs_obj *obj;
 
-	} else {
+	if (backward_scanning) {
 		/* Handle YAFFS2 case (backward scanning)
 		 * If the shadowed object exists then ignore.
 		 */
-		if (yaffs_FindObjectByNumber(dev, objId)) {
+		obj = yaffs_find_by_number(dev, obj_id);
+		if (obj)
 			return;
-		}
 	}
 
-	/* Let's create it (if it does not exist) assuming it is a file so that it can do shrinking etc.
+	/* Let's create it (if it does not exist) assuming it is a file so that
+	 * it can do shrinking etc.
 	 * We put it in unlinked dir to be cleaned up after the scanning
 	 */
 	obj =
-	    yaffs_FindOrCreateObjectByNumber(dev, objId,
-					     YAFFS_OBJECT_TYPE_FILE);
-	yaffs_AddObjectToDirectory(dev->unlinkedDir, obj);
-	obj->variant.fileVariant.shrinkSize = 0;
-	obj->valid = 1;		/* So that we don't read any other info for this file */
-
+	    yaffs_find_or_create_by_number(dev, obj_id, YAFFS_OBJECT_TYPE_FILE);
+	if (!obj)
+		return;
+	obj->is_shadowed = 1;
+	yaffs_add_obj_to_dir(dev->unlinked_dir, obj);
+	obj->variant.file_variant.shrink_size = 0;
+	obj->valid = 1;		/* So that we don't read any other info. */
 }
 
-typedef struct {
-	int seq;
-	int block;
-} yaffs_BlockIndex;
-
-
-static void yaffs_HardlinkFixup(yaffs_Device *dev, yaffs_Object *hardList)
+void yaffs_link_fixup(struct yaffs_dev *dev, struct list_head *hard_list)
 {
-	yaffs_Object *hl;
-	yaffs_Object *in;
-
-	while (hardList) {
-		hl = hardList;
-		hardList = (yaffs_Object *) (hardList->hardLinks.next);
+	struct list_head *lh;
+	struct list_head *save;
+	struct yaffs_obj *hl;
+	struct yaffs_obj *in;
 
-		in = yaffs_FindObjectByNumber(dev,
-					      hl->variant.hardLinkVariant.
-					      equivalentObjectId);
+	list_for_each_safe(lh, save, hard_list) {
+		hl = list_entry(lh, struct yaffs_obj, hard_links);
+		in = yaffs_find_by_number(dev,
+					hl->variant.hardlink_variant.equiv_id);
 
 		if (in) {
 			/* Add the hardlink pointers */
-			hl->variant.hardLinkVariant.equivalentObject = in;
-			list_add(&hl->hardLinks, &in->hardLinks);
+			hl->variant.hardlink_variant.equiv_obj = in;
+			list_add(&hl->hard_links, &in->hard_links);
 		} else {
 			/* Todo Need to report/handle this better.
 			 * Got a problem... hardlink to a non-existant object
 			 */
-			hl->variant.hardLinkVariant.equivalentObject = NULL;
-			INIT_LIST_HEAD(&hl->hardLinks);
-
+			hl->variant.hardlink_variant.equiv_obj = NULL;
+			INIT_LIST_HEAD(&hl->hard_links);
 		}
-
 	}
-
 }
 
-
-
-
-
-static int ybicmp(const void *a, const void *b){
-    register int aseq = ((yaffs_BlockIndex *)a)->seq;
-    register int bseq = ((yaffs_BlockIndex *)b)->seq;
-    register int ablock = ((yaffs_BlockIndex *)a)->block;
-    register int bblock = ((yaffs_BlockIndex *)b)->block;
-    if( aseq == bseq )
-	return ablock - bblock;
-    else
-	return aseq - bseq;
-
-}
-
-static int yaffs_Scan(yaffs_Device * dev)
+static void yaffs_strip_deleted_objs(struct yaffs_dev *dev)
 {
-	yaffs_ExtendedTags tags;
-	int blk;
-	int blockIterator;
-	int startIterator;
-	int endIterator;
-	int nBlocksToScan = 0;
-
-	int chunk;
-	int c;
-	int deleted;
-	yaffs_BlockState state;
-	yaffs_Object *hardList = NULL;
-	yaffs_BlockInfo *bi;
-	int sequenceNumber;
-	yaffs_ObjectHeader *oh;
-	yaffs_Object *in;
-	yaffs_Object *parent;
-	int nBlocks = dev->internalEndBlock - dev->internalStartBlock + 1;
-
-	int alloc_failed = 0;
-
-
-	__u8 *chunkData;
-
-	yaffs_BlockIndex *blockIndex = NULL;
-
-	if (dev->isYaffs2) {
-		T(YAFFS_TRACE_SCAN,
-		  (TSTR("yaffs_Scan is not for YAFFS2!" TENDSTR)));
-		return YAFFS_FAIL;
-	}
-
-	//TODO  Throw all the yaffs2 stuuf out of yaffs_Scan since it is only for yaffs1 format.
-
-	T(YAFFS_TRACE_SCAN,
-	  (TSTR("yaffs_Scan starts  intstartblk %d intendblk %d..." TENDSTR),
-	   dev->internalStartBlock, dev->internalEndBlock));
-
-	chunkData = yaffs_GetTempBuffer(dev, __LINE__);
-
-	dev->sequenceNumber = YAFFS_LOWEST_SEQUENCE_NUMBER;
-
-	if (dev->isYaffs2) {
-		blockIndex = YMALLOC(nBlocks * sizeof(yaffs_BlockIndex));
-		if(!blockIndex)
-			return YAFFS_FAIL;
-	}
-
-	/* Scan all the blocks to determine their state */
-	for (blk = dev->internalStartBlock; blk <= dev->internalEndBlock; blk++) {
-		bi = yaffs_GetBlockInfo(dev, blk);
-		yaffs_ClearChunkBits(dev, blk);
-		bi->pagesInUse = 0;
-		bi->softDeletions = 0;
-
-		yaffs_QueryInitialBlockState(dev, blk, &state, &sequenceNumber);
-
-		bi->blockState = state;
-		bi->sequenceNumber = sequenceNumber;
-
-		T(YAFFS_TRACE_SCAN_DEBUG,
-		  (TSTR("Block scanning block %d state %d seq %d" TENDSTR), blk,
-		   state, sequenceNumber));
-
-		if (state == YAFFS_BLOCK_STATE_DEAD) {
-			T(YAFFS_TRACE_BAD_BLOCKS,
-			  (TSTR("block %d is bad" TENDSTR), blk));
-		} else if (state == YAFFS_BLOCK_STATE_EMPTY) {
-			T(YAFFS_TRACE_SCAN_DEBUG,
-			  (TSTR("Block empty " TENDSTR)));
-			dev->nErasedBlocks++;
-			dev->nFreeChunks += dev->nChunksPerBlock;
-		} else if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING) {
-
-			/* Determine the highest sequence number */
-			if (dev->isYaffs2 &&
-			    sequenceNumber >= YAFFS_LOWEST_SEQUENCE_NUMBER &&
-			    sequenceNumber < YAFFS_HIGHEST_SEQUENCE_NUMBER) {
-
-				blockIndex[nBlocksToScan].seq = sequenceNumber;
-				blockIndex[nBlocksToScan].block = blk;
-
-				nBlocksToScan++;
-
-				if (sequenceNumber >= dev->sequenceNumber) {
-					dev->sequenceNumber = sequenceNumber;
-				}
-			} else if (dev->isYaffs2) {
-				/* TODO: Nasty sequence number! */
-				T(YAFFS_TRACE_SCAN,
-				  (TSTR
-				   ("Block scanning block %d has bad sequence number %d"
-				    TENDSTR), blk, sequenceNumber));
-
-			}
-		}
-	}
-
-	/* Sort the blocks
-	 * Dungy old bubble sort for now...
-	 */
-	if (dev->isYaffs2) {
-		yaffs_BlockIndex temp;
-		int i;
-		int j;
-
-		for (i = 0; i < nBlocksToScan; i++)
-			for (j = i + 1; j < nBlocksToScan; j++)
-				if (blockIndex[i].seq > blockIndex[j].seq) {
-					temp = blockIndex[j];
-					blockIndex[j] = blockIndex[i];
-					blockIndex[i] = temp;
-				}
-	}
-
-	/* Now scan the blocks looking at the data. */
-	if (dev->isYaffs2) {
-		startIterator = 0;
-		endIterator = nBlocksToScan - 1;
-		T(YAFFS_TRACE_SCAN_DEBUG,
-		  (TSTR("%d blocks to be scanned" TENDSTR), nBlocksToScan));
-	} else {
-		startIterator = dev->internalStartBlock;
-		endIterator = dev->internalEndBlock;
-	}
-
-	/* For each block.... */
-	for (blockIterator = startIterator; !alloc_failed && blockIterator <= endIterator;
-	     blockIterator++) {
-
-		if (dev->isYaffs2) {
-			/* get the block to scan in the correct order */
-			blk = blockIndex[blockIterator].block;
-		} else {
-			blk = blockIterator;
-		}
-
-		bi = yaffs_GetBlockInfo(dev, blk);
-		state = bi->blockState;
-
-		deleted = 0;
-
-		/* For each chunk in each block that needs scanning....*/
-		for (c = 0; !alloc_failed && c < dev->nChunksPerBlock &&
-		     state == YAFFS_BLOCK_STATE_NEEDS_SCANNING; c++) {
-			/* Read the tags and decide what to do */
-			chunk = blk * dev->nChunksPerBlock + c;
-
-			yaffs_ReadChunkWithTagsFromNAND(dev, chunk, NULL,
-							&tags);
-
-			/* Let's have a good look at this chunk... */
-
-			if (!dev->isYaffs2 && tags.chunkDeleted) {
-				/* YAFFS1 only...
-				 * A deleted chunk
-				 */
-				deleted++;
-				dev->nFreeChunks++;
-				/*T((" %d %d deleted\n",blk,c)); */
-			} else if (!tags.chunkUsed) {
-				/* An unassigned chunk in the block
-				 * This means that either the block is empty or
-				 * this is the one being allocated from
-				 */
-
-				if (c == 0) {
-					/* We're looking at the first chunk in the block so the block is unused */
-					state = YAFFS_BLOCK_STATE_EMPTY;
-					dev->nErasedBlocks++;
-				} else {
-					/* this is the block being allocated from */
-					T(YAFFS_TRACE_SCAN,
-					  (TSTR
-					   (" Allocating from %d %d" TENDSTR),
-					   blk, c));
-					state = YAFFS_BLOCK_STATE_ALLOCATING;
-					dev->allocationBlock = blk;
-					dev->allocationPage = c;
-					dev->allocationBlockFinder = blk;
-					/* Set it to here to encourage the allocator to go forth from here. */
-
-					/* Yaffs2 sanity check:
-					 * This should be the one with the highest sequence number
-					 */
-					if (dev->isYaffs2
-					    && (dev->sequenceNumber !=
-						bi->sequenceNumber)) {
-						T(YAFFS_TRACE_ALWAYS,
-						  (TSTR
-						   ("yaffs: Allocation block %d was not highest sequence id:"
-						    " block seq = %d, dev seq = %d"
-						    TENDSTR), blk,bi->sequenceNumber,dev->sequenceNumber));
-					}
-				}
-
-				dev->nFreeChunks += (dev->nChunksPerBlock - c);
-			} else if (tags.chunkId > 0) {
-				/* chunkId > 0 so it is a data chunk... */
-				unsigned int endpos;
-
-				yaffs_SetChunkBit(dev, blk, c);
-				bi->pagesInUse++;
-
-				in = yaffs_FindOrCreateObjectByNumber(dev,
-								      tags.
-								      objectId,
-								      YAFFS_OBJECT_TYPE_FILE);
-				/* PutChunkIntoFile checks for a clash (two data chunks with
-				 * the same chunkId).
-				 */
-
-				if(!in)
-					alloc_failed = 1;
-
-				if(in){
-					if(!yaffs_PutChunkIntoFile(in, tags.chunkId, chunk,1))
-						alloc_failed = 1;
-				}
-
-				endpos =
-				    (tags.chunkId - 1) * dev->nDataBytesPerChunk +
-				    tags.byteCount;
-				if (in &&
-				    in->variantType == YAFFS_OBJECT_TYPE_FILE
-				    && in->variant.fileVariant.scannedFileSize <
-				    endpos) {
-					in->variant.fileVariant.
-					    scannedFileSize = endpos;
-					if (!dev->useHeaderFileSize) {
-						in->variant.fileVariant.
-						    fileSize =
-						    in->variant.fileVariant.
-						    scannedFileSize;
-					}
-
-				}
-				/* T((" %d %d data %d %d\n",blk,c,tags.objectId,tags.chunkId));   */
-			} else {
-				/* chunkId == 0, so it is an ObjectHeader.
-				 * Thus, we read in the object header and make the object
-				 */
-				yaffs_SetChunkBit(dev, blk, c);
-				bi->pagesInUse++;
-
-				yaffs_ReadChunkWithTagsFromNAND(dev, chunk,
-								chunkData,
-								NULL);
-
-				oh = (yaffs_ObjectHeader *) chunkData;
-
-				in = yaffs_FindObjectByNumber(dev,
-							      tags.objectId);
-				if (in && in->variantType != oh->type) {
-					/* This should not happen, but somehow
-					 * Wev'e ended up with an objectId that has been reused but not yet
-					 * deleted, and worse still it has changed type. Delete the old object.
-					 */
-
-					yaffs_DestroyObject(in);
-
-					in = 0;
-				}
-
-				in = yaffs_FindOrCreateObjectByNumber(dev,
-								      tags.
-								      objectId,
-								      oh->type);
-
-				if(!in)
-					alloc_failed = 1;
-
-				if (in && oh->shadowsObject > 0) {
-					yaffs_HandleShadowedObject(dev,
-								   oh->
-								   shadowsObject,
-								   0);
-				}
-
-				if (in && in->valid) {
-					/* We have already filled this one. We have a duplicate and need to resolve it. */
-
-					unsigned existingSerial = in->serial;
-					unsigned newSerial = tags.serialNumber;
-
-					if (dev->isYaffs2 ||
-					    ((existingSerial + 1) & 3) ==
-					    newSerial) {
-						/* Use new one - destroy the exisiting one */
-						yaffs_DeleteChunk(dev,
-								  in->chunkId,
-								  1, __LINE__);
-						in->valid = 0;
-					} else {
-						/* Use existing - destroy this one. */
-						yaffs_DeleteChunk(dev, chunk, 1,
-								  __LINE__);
-					}
-				}
-
-				if (in && !in->valid &&
-				    (tags.objectId == YAFFS_OBJECTID_ROOT ||
-				     tags.objectId == YAFFS_OBJECTID_LOSTNFOUND)) {
-					/* We only load some info, don't fiddle with directory structure */
-					in->valid = 1;
-					in->variantType = oh->type;
-
-					in->yst_mode = oh->yst_mode;
-#ifdef CONFIG_YAFFS_WINCE
-					in->win_atime[0] = oh->win_atime[0];
-					in->win_ctime[0] = oh->win_ctime[0];
-					in->win_mtime[0] = oh->win_mtime[0];
-					in->win_atime[1] = oh->win_atime[1];
-					in->win_ctime[1] = oh->win_ctime[1];
-					in->win_mtime[1] = oh->win_mtime[1];
-#else
-					in->yst_uid = oh->yst_uid;
-					in->yst_gid = oh->yst_gid;
-					in->yst_atime = oh->yst_atime;
-					in->yst_mtime = oh->yst_mtime;
-					in->yst_ctime = oh->yst_ctime;
-					in->yst_rdev = oh->yst_rdev;
-#endif
-					in->chunkId = chunk;
-
-				} else if (in && !in->valid) {
-					/* we need to load this info */
-
-					in->valid = 1;
-					in->variantType = oh->type;
-
-					in->yst_mode = oh->yst_mode;
-#ifdef CONFIG_YAFFS_WINCE
-					in->win_atime[0] = oh->win_atime[0];
-					in->win_ctime[0] = oh->win_ctime[0];
-					in->win_mtime[0] = oh->win_mtime[0];
-					in->win_atime[1] = oh->win_atime[1];
-					in->win_ctime[1] = oh->win_ctime[1];
-					in->win_mtime[1] = oh->win_mtime[1];
-#else
-					in->yst_uid = oh->yst_uid;
-					in->yst_gid = oh->yst_gid;
-					in->yst_atime = oh->yst_atime;
-					in->yst_mtime = oh->yst_mtime;
-					in->yst_ctime = oh->yst_ctime;
-					in->yst_rdev = oh->yst_rdev;
-#endif
-					in->chunkId = chunk;
-
-					yaffs_SetObjectName(in, oh->name);
-					in->dirty = 0;
-
-					/* directory stuff...
-					 * hook up to parent
-					 */
-
-					parent =
-					    yaffs_FindOrCreateObjectByNumber
-					    (dev, oh->parentObjectId,
-					     YAFFS_OBJECT_TYPE_DIRECTORY);
-					if (parent->variantType ==
-					    YAFFS_OBJECT_TYPE_UNKNOWN) {
-						/* Set up as a directory */
-						parent->variantType =
-						    YAFFS_OBJECT_TYPE_DIRECTORY;
-						INIT_LIST_HEAD(&parent->variant.
-							       directoryVariant.
-							       children);
-					} else if (parent->variantType !=
-						   YAFFS_OBJECT_TYPE_DIRECTORY)
-					{
-						/* Hoosterman, another problem....
-						 * We're trying to use a non-directory as a directory
-						 */
-
-						T(YAFFS_TRACE_ERROR,
-						  (TSTR
-						   ("yaffs tragedy: attempting to use non-directory as"
-						    " a directory in scan. Put in lost+found."
-						    TENDSTR)));
-						parent = dev->lostNFoundDir;
-					}
-
-					yaffs_AddObjectToDirectory(parent, in);
-
-					if (0 && (parent == dev->deletedDir ||
-						  parent == dev->unlinkedDir)) {
-						in->deleted = 1;	/* If it is unlinked at start up then it wants deleting */
-						dev->nDeletedFiles++;
-					}
-					/* Note re hardlinks.
-					 * Since we might scan a hardlink before its equivalent object is scanned
-					 * we put them all in a list.
-					 * After scanning is complete, we should have all the objects, so we run through this
-					 * list and fix up all the chains.
-					 */
-
-					switch (in->variantType) {
-					case YAFFS_OBJECT_TYPE_UNKNOWN:
-						/* Todo got a problem */
-						break;
-					case YAFFS_OBJECT_TYPE_FILE:
-						if (dev->isYaffs2
-						    && oh->isShrink) {
-							/* Prune back the shrunken chunks */
-							yaffs_PruneResizedChunks
-							    (in, oh->fileSize);
-							/* Mark the block as having a shrinkHeader */
-							bi->hasShrinkHeader = 1;
-						}
-
-						if (dev->useHeaderFileSize)
-
-							in->variant.fileVariant.
-							    fileSize =
-							    oh->fileSize;
-
-						break;
-					case YAFFS_OBJECT_TYPE_HARDLINK:
-						in->variant.hardLinkVariant.
-						    equivalentObjectId =
-						    oh->equivalentObjectId;
-						in->hardLinks.next =
-						    (struct list_head *)
-						    hardList;
-						hardList = in;
-						break;
-					case YAFFS_OBJECT_TYPE_DIRECTORY:
-						/* Do nothing */
-						break;
-					case YAFFS_OBJECT_TYPE_SPECIAL:
-						/* Do nothing */
-						break;
-					case YAFFS_OBJECT_TYPE_SYMLINK:
-						in->variant.symLinkVariant.alias =
-						    yaffs_CloneString(oh->alias);
-						if(!in->variant.symLinkVariant.alias)
-							alloc_failed = 1;
-						break;
-					}
-
-					if (parent == dev->deletedDir) {
-						yaffs_DestroyObject(in);
-						bi->hasShrinkHeader = 1;
-					}
-				}
-			}
-		}
-
-		if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING) {
-			/* If we got this far while scanning, then the block is fully allocated.*/
-			state = YAFFS_BLOCK_STATE_FULL;
-		}
-
-		bi->blockState = state;
-
-		/* Now let's see if it was dirty */
-		if (bi->pagesInUse == 0 &&
-		    !bi->hasShrinkHeader &&
-		    bi->blockState == YAFFS_BLOCK_STATE_FULL) {
-			yaffs_BlockBecameDirty(dev, blk);
-		}
-
-	}
-
-	if (blockIndex) {
-		YFREE(blockIndex);
-	}
-
-
-	/* Ok, we've done all the scanning.
-	 * Fix up the hard link chains.
-	 * We should now have scanned all the objects, now it's time to add these
-	 * hardlinks.
+	/*
+	 *  Sort out state of unlinked and deleted objects after scanning.
 	 */
+	struct list_head *i;
+	struct list_head *n;
+	struct yaffs_obj *l;
 
-	yaffs_HardlinkFixup(dev,hardList);
+	if (dev->read_only)
+		return;
 
-	/* Handle the unlinked files. Since they were left in an unlinked state we should
-	 * just delete them.
-	 */
-	{
-		struct list_head *i;
-		struct list_head *n;
-
-		yaffs_Object *l;
-		/* Soft delete all the unlinked files */
-		list_for_each_safe(i, n,
-				   &dev->unlinkedDir->variant.directoryVariant.
-				   children) {
-			if (i) {
-				l = list_entry(i, yaffs_Object, siblings);
-				yaffs_DestroyObject(l);
-			}
-		}
+	/* Soft delete all the unlinked files */
+	list_for_each_safe(i, n,
+			   &dev->unlinked_dir->variant.dir_variant.children) {
+		l = list_entry(i, struct yaffs_obj, siblings);
+		yaffs_del_obj(l);
 	}
 
-	yaffs_ReleaseTempBuffer(dev, chunkData, __LINE__);
-
-	if(alloc_failed){
-		return YAFFS_FAIL;
+	list_for_each_safe(i, n, &dev->del_dir->variant.dir_variant.children) {
+		l = list_entry(i, struct yaffs_obj, siblings);
+		yaffs_del_obj(l);
 	}
-
-	T(YAFFS_TRACE_SCAN, (TSTR("yaffs_Scan ends" TENDSTR)));
-
-
-	return YAFFS_OK;
 }
 
-static void yaffs_CheckObjectDetailsLoaded(yaffs_Object *in)
-{
-	__u8 *chunkData;
-	yaffs_ObjectHeader *oh;
-	yaffs_Device *dev = in->myDev;
-	yaffs_ExtendedTags tags;
-
-	if(!in)
-		return;
-
-#if 0
-	T(YAFFS_TRACE_SCAN,(TSTR("details for object %d %s loaded" TENDSTR),
-		in->objectId,
-		in->lazyLoaded ? "not yet" : "already"));
-#endif
-
-	if(in->lazyLoaded){
-		in->lazyLoaded = 0;
-		chunkData = yaffs_GetTempBuffer(dev, __LINE__);
-
-		yaffs_ReadChunkWithTagsFromNAND(dev, in->chunkId,
-						chunkData, &tags);
-		oh = (yaffs_ObjectHeader *) chunkData;
-
-		in->yst_mode = oh->yst_mode;
-#ifdef CONFIG_YAFFS_WINCE
-		in->win_atime[0] = oh->win_atime[0];
-		in->win_ctime[0] = oh->win_ctime[0];
-		in->win_mtime[0] = oh->win_mtime[0];
-		in->win_atime[1] = oh->win_atime[1];
-		in->win_ctime[1] = oh->win_ctime[1];
-		in->win_mtime[1] = oh->win_mtime[1];
-#else
-		in->yst_uid = oh->yst_uid;
-		in->yst_gid = oh->yst_gid;
-		in->yst_atime = oh->yst_atime;
-		in->yst_mtime = oh->yst_mtime;
-		in->yst_ctime = oh->yst_ctime;
-		in->yst_rdev = oh->yst_rdev;
-
-#endif
-		yaffs_SetObjectName(in, oh->name);
-
-		if(in->variantType == YAFFS_OBJECT_TYPE_SYMLINK){
-			 in->variant.symLinkVariant.alias =
-						    yaffs_CloneString(oh->alias);
-		}
+/*
+ * This code iterates through all the objects making sure that they are rooted.
+ * Any unrooted objects are re-rooted in lost+found.
+ * An object needs to be in one of:
+ * - Directly under deleted, unlinked
+ * - Directly or indirectly under root.
+ *
+ * Note:
+ *  This code assumes that we don't ever change the current relationships
+ *  between directories:
+ *   root_dir->parent == unlinked_dir->parent == del_dir->parent == NULL
+ *   lost-n-found->parent == root_dir
+ *
+ * This fixes the problem where directories might have inadvertently been
+ * deleted leaving the object "hanging" without being rooted in the
+ * directory tree.
+ */
 
-		yaffs_ReleaseTempBuffer(dev,chunkData, __LINE__);
-	}
+static int yaffs_has_null_parent(struct yaffs_dev *dev, struct yaffs_obj *obj)
+{
+	return (obj == dev->del_dir ||
+		obj == dev->unlinked_dir || obj == dev->root_dir);
 }
 
-static int yaffs_ScanBackwards(yaffs_Device * dev)
+static void yaffs_fix_hanging_objs(struct yaffs_dev *dev)
 {
-	yaffs_ExtendedTags tags;
-	int blk;
-	int blockIterator;
-	int startIterator;
-	int endIterator;
-	int nBlocksToScan = 0;
-
-	int chunk;
-	int c;
-	yaffs_BlockState state;
-	yaffs_Object *hardList = NULL;
-	yaffs_BlockInfo *bi;
-	int sequenceNumber;
-	yaffs_ObjectHeader *oh;
-	yaffs_Object *in;
-	yaffs_Object *parent;
-	int nBlocks = dev->internalEndBlock - dev->internalStartBlock + 1;
-	int itsUnlinked;
-	__u8 *chunkData;
-
-	int fileSize;
-	int isShrink;
-	int foundChunksInBlock;
-	int equivalentObjectId;
-	int alloc_failed = 0;
-
-
-	yaffs_BlockIndex *blockIndex = NULL;
-	int altBlockIndex = 0;
-
-	if (!dev->isYaffs2) {
-		T(YAFFS_TRACE_SCAN,
-		  (TSTR("yaffs_ScanBackwards is only for YAFFS2!" TENDSTR)));
-		return YAFFS_FAIL;
-	}
-
-	T(YAFFS_TRACE_SCAN,
-	  (TSTR
-	   ("yaffs_ScanBackwards starts  intstartblk %d intendblk %d..."
-	    TENDSTR), dev->internalStartBlock, dev->internalEndBlock));
-
-
-	dev->sequenceNumber = YAFFS_LOWEST_SEQUENCE_NUMBER;
-
-	blockIndex = YMALLOC(nBlocks * sizeof(yaffs_BlockIndex));
-
-	if(!blockIndex) {
-		blockIndex = YMALLOC_ALT(nBlocks * sizeof(yaffs_BlockIndex));
-		altBlockIndex = 1;
-	}
-
-	if(!blockIndex) {
-		T(YAFFS_TRACE_SCAN,
-		  (TSTR("yaffs_Scan() could not allocate block index!" TENDSTR)));
-		return YAFFS_FAIL;
-	}
-
-	dev->blocksInCheckpoint = 0;
-
-	chunkData = yaffs_GetTempBuffer(dev, __LINE__);
-
-	/* Scan all the blocks to determine their state */
-	for (blk = dev->internalStartBlock; blk <= dev->internalEndBlock; blk++) {
-		bi = yaffs_GetBlockInfo(dev, blk);
-		yaffs_ClearChunkBits(dev, blk);
-		bi->pagesInUse = 0;
-		bi->softDeletions = 0;
-
-		yaffs_QueryInitialBlockState(dev, blk, &state, &sequenceNumber);
-
-		bi->blockState = state;
-		bi->sequenceNumber = sequenceNumber;
-
-		if(bi->sequenceNumber == YAFFS_SEQUENCE_CHECKPOINT_DATA)
-			bi->blockState = state = YAFFS_BLOCK_STATE_CHECKPOINT;
-
-		T(YAFFS_TRACE_SCAN_DEBUG,
-		  (TSTR("Block scanning block %d state %d seq %d" TENDSTR), blk,
-		   state, sequenceNumber));
-
-
-		if(state == YAFFS_BLOCK_STATE_CHECKPOINT){
-			dev->blocksInCheckpoint++;
-
-		} else if (state == YAFFS_BLOCK_STATE_DEAD) {
-			T(YAFFS_TRACE_BAD_BLOCKS,
-			  (TSTR("block %d is bad" TENDSTR), blk));
-		} else if (state == YAFFS_BLOCK_STATE_EMPTY) {
-			T(YAFFS_TRACE_SCAN_DEBUG,
-			  (TSTR("Block empty " TENDSTR)));
-			dev->nErasedBlocks++;
-			dev->nFreeChunks += dev->nChunksPerBlock;
-		} else if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING) {
-
-			/* Determine the highest sequence number */
-			if (dev->isYaffs2 &&
-			    sequenceNumber >= YAFFS_LOWEST_SEQUENCE_NUMBER &&
-			    sequenceNumber < YAFFS_HIGHEST_SEQUENCE_NUMBER) {
-
-				blockIndex[nBlocksToScan].seq = sequenceNumber;
-				blockIndex[nBlocksToScan].block = blk;
-
-				nBlocksToScan++;
-
-				if (sequenceNumber >= dev->sequenceNumber) {
-					dev->sequenceNumber = sequenceNumber;
-				}
-			} else if (dev->isYaffs2) {
-				/* TODO: Nasty sequence number! */
-				T(YAFFS_TRACE_SCAN,
-				  (TSTR
-				   ("Block scanning block %d has bad sequence number %d"
-				    TENDSTR), blk, sequenceNumber));
-
-			}
-		}
-	}
-
-	T(YAFFS_TRACE_SCAN,
-	(TSTR("%d blocks to be sorted..." TENDSTR), nBlocksToScan));
-
-
-
-	YYIELD();
-
-	/* Sort the blocks */
-#ifndef CONFIG_YAFFS_USE_OWN_SORT
-	{
-		/* Use qsort now. */
-		yaffs_qsort(blockIndex, nBlocksToScan, sizeof(yaffs_BlockIndex), ybicmp);
-	}
-#else
-	{
-		/* Dungy old bubble sort... */
-
-		yaffs_BlockIndex temp;
-		int i;
-		int j;
-
-		for (i = 0; i < nBlocksToScan; i++)
-			for (j = i + 1; j < nBlocksToScan; j++)
-				if (blockIndex[i].seq > blockIndex[j].seq) {
-					temp = blockIndex[j];
-					blockIndex[j] = blockIndex[i];
-					blockIndex[i] = temp;
-				}
-	}
-#endif
-
-	YYIELD();
-
-	T(YAFFS_TRACE_SCAN, (TSTR("...done" TENDSTR)));
-
-	/* Now scan the blocks looking at the data. */
-	startIterator = 0;
-	endIterator = nBlocksToScan - 1;
-	T(YAFFS_TRACE_SCAN_DEBUG,
-	  (TSTR("%d blocks to be scanned" TENDSTR), nBlocksToScan));
-
-	/* For each block.... backwards */
-	for (blockIterator = endIterator; !alloc_failed && blockIterator >= startIterator;
-	     blockIterator--) {
-		/* Cooperative multitasking! This loop can run for so
-		   long that watchdog timers expire. */
-		YYIELD();
-
-		/* get the block to scan in the correct order */
-		blk = blockIndex[blockIterator].block;
-
-		bi = yaffs_GetBlockInfo(dev, blk);
-
-
-		state = bi->blockState;
-
-		/* For each chunk in each block that needs scanning.... */
-		foundChunksInBlock = 0;
-		for (c = dev->nChunksPerBlock - 1;
-		     !alloc_failed && c >= 0 &&
-		     (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING ||
-		      state == YAFFS_BLOCK_STATE_ALLOCATING); c--) {
-			/* Scan backwards...
-			 * Read the tags and decide what to do
-			 */
-
-			chunk = blk * dev->nChunksPerBlock + c;
-
-			yaffs_ReadChunkWithTagsFromNAND(dev, chunk, NULL,
-							&tags);
-
-			/* Let's have a good look at this chunk... */
-
-			if (!tags.chunkUsed) {
-				/* An unassigned chunk in the block.
-				 * If there are used chunks after this one, then
-				 * it is a chunk that was skipped due to failing the erased
-				 * check. Just skip it so that it can be deleted.
-				 * But, more typically, We get here when this is an unallocated
-				 * chunk and his means that either the block is empty or
-				 * this is the one being allocated from
-				 */
-
-				if(foundChunksInBlock)
-				{
-					/* This is a chunk that was skipped due to failing the erased check */
-
-				} else if (c == 0) {
-					/* We're looking at the first chunk in the block so the block is unused */
-					state = YAFFS_BLOCK_STATE_EMPTY;
-					dev->nErasedBlocks++;
-				} else {
-					if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING ||
-					    state == YAFFS_BLOCK_STATE_ALLOCATING) {
-						if(dev->sequenceNumber == bi->sequenceNumber) {
-							/* this is the block being allocated from */
-
-							T(YAFFS_TRACE_SCAN,
-							  (TSTR
-							   (" Allocating from %d %d"
-							    TENDSTR), blk, c));
-
-							state = YAFFS_BLOCK_STATE_ALLOCATING;
-							dev->allocationBlock = blk;
-							dev->allocationPage = c;
-							dev->allocationBlockFinder = blk;
-						}
-						else {
-							/* This is a partially written block that is not
-							 * the current allocation block. This block must have
-							 * had a write failure, so set up for retirement.
-							 */
-
-							 bi->needsRetiring = 1;
-							 bi->gcPrioritise = 1;
-
-							 T(YAFFS_TRACE_ALWAYS,
-							 (TSTR("Partially written block %d being set for retirement" TENDSTR),
-							 blk));
-						}
-
-					}
-
-				}
-
-				dev->nFreeChunks++;
-
-			} else if (tags.chunkId > 0) {
-				/* chunkId > 0 so it is a data chunk... */
-				unsigned int endpos;
-				__u32 chunkBase =
-				    (tags.chunkId - 1) * dev->nDataBytesPerChunk;
-
-				foundChunksInBlock = 1;
-
-
-				yaffs_SetChunkBit(dev, blk, c);
-				bi->pagesInUse++;
-
-				in = yaffs_FindOrCreateObjectByNumber(dev,
-								      tags.
-								      objectId,
-								      YAFFS_OBJECT_TYPE_FILE);
-				if(!in){
-					/* Out of memory */
-					alloc_failed = 1;
-				}
-
-				if (in &&
-				    in->variantType == YAFFS_OBJECT_TYPE_FILE
-				    && chunkBase <
-				    in->variant.fileVariant.shrinkSize) {
-					/* This has not been invalidated by a resize */
-					if(!yaffs_PutChunkIntoFile(in, tags.chunkId,
-							       chunk, -1)){
-						alloc_failed = 1;
-					}
+	struct yaffs_obj *obj;
+	struct yaffs_obj *parent;
+	int i;
+	struct list_head *lh;
+	struct list_head *n;
+	int depth_limit;
+	int hanging;
 
-					/* File size is calculated by looking at the data chunks if we have not
-					 * seen an object header yet. Stop this practice once we find an object header.
-					 */
-					endpos =
-					    (tags.chunkId -
-					     1) * dev->nDataBytesPerChunk +
-					    tags.byteCount;
-
-					if (!in->valid &&	/* have not got an object header yet */
-					    in->variant.fileVariant.
-					    scannedFileSize < endpos) {
-						in->variant.fileVariant.
-						    scannedFileSize = endpos;
-						in->variant.fileVariant.
-						    fileSize =
-						    in->variant.fileVariant.
-						    scannedFileSize;
-					}
+	if (dev->read_only)
+		return;
 
-				} else if(in) {
-					/* This chunk has been invalidated by a resize, so delete */
-					yaffs_DeleteChunk(dev, chunk, 1, __LINE__);
+	/* Iterate through the objects in each hash entry,
+	 * looking at each object.
+	 * Make sure it is rooted.
+	 */
 
-				}
+	for (i = 0; i < YAFFS_NOBJECT_BUCKETS; i++) {
+		list_for_each_safe(lh, n, &dev->obj_bucket[i].list) {
+			obj = list_entry(lh, struct yaffs_obj, hash_link);
+			parent = obj->parent;
+
+			if (yaffs_has_null_parent(dev, obj)) {
+				/* These directories are not hanging */
+				hanging = 0;
+			} else if (!parent ||
+				   parent->variant_type !=
+				   YAFFS_OBJECT_TYPE_DIRECTORY) {
+				hanging = 1;
+			} else if (yaffs_has_null_parent(dev, parent)) {
+				hanging = 0;
 			} else {
-				/* chunkId == 0, so it is an ObjectHeader.
-				 * Thus, we read in the object header and make the object
+				/*
+				 * Need to follow the parent chain to
+				 * see if it is hanging.
 				 */
-				foundChunksInBlock = 1;
-
-				yaffs_SetChunkBit(dev, blk, c);
-				bi->pagesInUse++;
-
-				oh = NULL;
-				in = NULL;
-
-				if (tags.extraHeaderInfoAvailable) {
-					in = yaffs_FindOrCreateObjectByNumber
-					    (dev, tags.objectId,
-					     tags.extraObjectType);
-				}
-
-				if (!in ||
-#ifdef CONFIG_YAFFS_DISABLE_LAZY_LOAD
-				    !in->valid ||
-#endif
-				    tags.extraShadows ||
-				    (!in->valid &&
-				    (tags.objectId == YAFFS_OBJECTID_ROOT ||
-				     tags.objectId == YAFFS_OBJECTID_LOSTNFOUND))
-				    ) {
-
-					/* If we don't have  valid info then we need to read the chunk
-					 * TODO In future we can probably defer reading the chunk and
-					 * living with invalid data until needed.
-					 */
-
-					yaffs_ReadChunkWithTagsFromNAND(dev,
-									chunk,
-									chunkData,
-									NULL);
-
-					oh = (yaffs_ObjectHeader *) chunkData;
-
-					if (!in)
-						in = yaffs_FindOrCreateObjectByNumber(dev, tags.objectId, oh->type);
-
-				}
-
-				if (!in) {
-					/* TODO Hoosterman we have a problem! */
-					T(YAFFS_TRACE_ERROR,
-					  (TSTR
-					   ("yaffs tragedy: Could not make object for object  %d  "
-					    "at chunk %d during scan"
-					    TENDSTR), tags.objectId, chunk));
-
-				}
-
-				if (in->valid) {
-					/* We have already filled this one.
-					 * We have a duplicate that will be discarded, but
-					 * we first have to suck out resize info if it is a file.
-					 */
-
-					if ((in->variantType == YAFFS_OBJECT_TYPE_FILE) &&
-					     ((oh &&
-					       oh-> type == YAFFS_OBJECT_TYPE_FILE)||
-					      (tags.extraHeaderInfoAvailable  &&
-					       tags.extraObjectType == YAFFS_OBJECT_TYPE_FILE))
-					    ) {
-						__u32 thisSize =
-						    (oh) ? oh->fileSize : tags.
-						    extraFileLength;
-						__u32 parentObjectId =
-						    (oh) ? oh->
-						    parentObjectId : tags.
-						    extraParentObjectId;
-						unsigned isShrink =
-						    (oh) ? oh->isShrink : tags.
-						    extraIsShrinkHeader;
-
-						/* If it is deleted (unlinked at start also means deleted)
-						 * we treat the file size as being zeroed at this point.
-						 */
-						if (parentObjectId ==
-						    YAFFS_OBJECTID_DELETED
-						    || parentObjectId ==
-						    YAFFS_OBJECTID_UNLINKED) {
-							thisSize = 0;
-							isShrink = 1;
-						}
-
-						if (isShrink &&
-						    in->variant.fileVariant.
-						    shrinkSize > thisSize) {
-							in->variant.fileVariant.
-							    shrinkSize =
-							    thisSize;
-						}
-
-						if (isShrink) {
-							bi->hasShrinkHeader = 1;
-						}
-
-					}
-					/* Use existing - destroy this one. */
-					yaffs_DeleteChunk(dev, chunk, 1, __LINE__);
-
+				hanging = 0;
+				depth_limit = 100;
+
+				while (parent != dev->root_dir &&
+				       parent->parent &&
+				       parent->parent->variant_type ==
+				       YAFFS_OBJECT_TYPE_DIRECTORY &&
+				       depth_limit > 0) {
+					parent = parent->parent;
+					depth_limit--;
 				}
-
-				if (!in->valid &&
-				    (tags.objectId == YAFFS_OBJECTID_ROOT ||
-				     tags.objectId ==
-				     YAFFS_OBJECTID_LOSTNFOUND)) {
-					/* We only load some info, don't fiddle with directory structure */
-					in->valid = 1;
-
-					if(oh) {
-						in->variantType = oh->type;
-
-						in->yst_mode = oh->yst_mode;
-#ifdef CONFIG_YAFFS_WINCE
-						in->win_atime[0] = oh->win_atime[0];
-						in->win_ctime[0] = oh->win_ctime[0];
-						in->win_mtime[0] = oh->win_mtime[0];
-						in->win_atime[1] = oh->win_atime[1];
-						in->win_ctime[1] = oh->win_ctime[1];
-						in->win_mtime[1] = oh->win_mtime[1];
-#else
-						in->yst_uid = oh->yst_uid;
-						in->yst_gid = oh->yst_gid;
-						in->yst_atime = oh->yst_atime;
-						in->yst_mtime = oh->yst_mtime;
-						in->yst_ctime = oh->yst_ctime;
-						in->yst_rdev = oh->yst_rdev;
-
-#endif
-					} else {
-						in->variantType = tags.extraObjectType;
-						in->lazyLoaded = 1;
-					}
-
-					in->chunkId = chunk;
-
-				} else if (!in->valid) {
-					/* we need to load this info */
-
-					in->valid = 1;
-					in->chunkId = chunk;
-
-					if(oh) {
-						in->variantType = oh->type;
-
-						in->yst_mode = oh->yst_mode;
-#ifdef CONFIG_YAFFS_WINCE
-						in->win_atime[0] = oh->win_atime[0];
-						in->win_ctime[0] = oh->win_ctime[0];
-						in->win_mtime[0] = oh->win_mtime[0];
-						in->win_atime[1] = oh->win_atime[1];
-						in->win_ctime[1] = oh->win_ctime[1];
-						in->win_mtime[1] = oh->win_mtime[1];
-#else
-						in->yst_uid = oh->yst_uid;
-						in->yst_gid = oh->yst_gid;
-						in->yst_atime = oh->yst_atime;
-						in->yst_mtime = oh->yst_mtime;
-						in->yst_ctime = oh->yst_ctime;
-						in->yst_rdev = oh->yst_rdev;
-#endif
-
-						if (oh->shadowsObject > 0)
-							yaffs_HandleShadowedObject(dev,
-									   oh->
-									   shadowsObject,
-									   1);
-
-
-						yaffs_SetObjectName(in, oh->name);
-						parent =
-						    yaffs_FindOrCreateObjectByNumber
-							(dev, oh->parentObjectId,
-							 YAFFS_OBJECT_TYPE_DIRECTORY);
-
-						 fileSize = oh->fileSize;
-						 isShrink = oh->isShrink;
-						 equivalentObjectId = oh->equivalentObjectId;
-
-					}
-					else {
-						in->variantType = tags.extraObjectType;
-						parent =
-						    yaffs_FindOrCreateObjectByNumber
-							(dev, tags.extraParentObjectId,
-							 YAFFS_OBJECT_TYPE_DIRECTORY);
-						 fileSize = tags.extraFileLength;
-						 isShrink = tags.extraIsShrinkHeader;
-						 equivalentObjectId = tags.extraEquivalentObjectId;
-						in->lazyLoaded = 1;
-
-					}
-					in->dirty = 0;
-
-					/* directory stuff...
-					 * hook up to parent
-					 */
-
-					if (parent->variantType ==
-					    YAFFS_OBJECT_TYPE_UNKNOWN) {
-						/* Set up as a directory */
-						parent->variantType =
-						    YAFFS_OBJECT_TYPE_DIRECTORY;
-						INIT_LIST_HEAD(&parent->variant.
-							       directoryVariant.
-							       children);
-					} else if (parent->variantType !=
-						   YAFFS_OBJECT_TYPE_DIRECTORY)
-					{
-						/* Hoosterman, another problem....
-						 * We're trying to use a non-directory as a directory
-						 */
-
-						T(YAFFS_TRACE_ERROR,
-						  (TSTR
-						   ("yaffs tragedy: attempting to use non-directory as"
-						    " a directory in scan. Put in lost+found."
-						    TENDSTR)));
-						parent = dev->lostNFoundDir;
-					}
-
-					yaffs_AddObjectToDirectory(parent, in);
-
-					itsUnlinked = (parent == dev->deletedDir) ||
-						      (parent == dev->unlinkedDir);
-
-					if (isShrink) {
-						/* Mark the block as having a shrinkHeader */
-						bi->hasShrinkHeader = 1;
-					}
-
-					/* Note re hardlinks.
-					 * Since we might scan a hardlink before its equivalent object is scanned
-					 * we put them all in a list.
-					 * After scanning is complete, we should have all the objects, so we run
-					 * through this list and fix up all the chains.
-					 */
-
-					switch (in->variantType) {
-					case YAFFS_OBJECT_TYPE_UNKNOWN:
-						/* Todo got a problem */
-						break;
-					case YAFFS_OBJECT_TYPE_FILE:
-
-						if (in->variant.fileVariant.
-						    scannedFileSize < fileSize) {
-							/* This covers the case where the file size is greater
-							 * than where the data is
-							 * This will happen if the file is resized to be larger
-							 * than its current data extents.
-							 */
-							in->variant.fileVariant.fileSize = fileSize;
-							in->variant.fileVariant.scannedFileSize =
-							    in->variant.fileVariant.fileSize;
-						}
-
-						if (isShrink &&
-						    in->variant.fileVariant.shrinkSize > fileSize) {
-							in->variant.fileVariant.shrinkSize = fileSize;
-						}
-
-						break;
-					case YAFFS_OBJECT_TYPE_HARDLINK:
-						if(!itsUnlinked) {
-						  in->variant.hardLinkVariant.equivalentObjectId =
-						    equivalentObjectId;
-						  in->hardLinks.next =
-						    (struct list_head *) hardList;
-						  hardList = in;
-						}
-						break;
-					case YAFFS_OBJECT_TYPE_DIRECTORY:
-						/* Do nothing */
-						break;
-					case YAFFS_OBJECT_TYPE_SPECIAL:
-						/* Do nothing */
-						break;
-					case YAFFS_OBJECT_TYPE_SYMLINK:
-						if(oh){
-						   in->variant.symLinkVariant.alias =
-						    yaffs_CloneString(oh->
-								      alias);
-						   if(!in->variant.symLinkVariant.alias)
-							alloc_failed = 1;
-						}
-						break;
-					}
-
-				}
-
+				if (parent != dev->root_dir)
+					hanging = 1;
 			}
-
-		} /* End of scanning for each chunk */
-
-		if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING) {
-			/* If we got this far while scanning, then the block is fully allocated. */
-			state = YAFFS_BLOCK_STATE_FULL;
-		}
-
-		bi->blockState = state;
-
-		/* Now let's see if it was dirty */
-		if (bi->pagesInUse == 0 &&
-		    !bi->hasShrinkHeader &&
-		    bi->blockState == YAFFS_BLOCK_STATE_FULL) {
-			yaffs_BlockBecameDirty(dev, blk);
-		}
-
-	}
-
-	if (altBlockIndex)
-		YFREE_ALT(blockIndex);
-	else
-		YFREE(blockIndex);
-
-	/* Ok, we've done all the scanning.
-	 * Fix up the hard link chains.
-	 * We should now have scanned all the objects, now it's time to add these
-	 * hardlinks.
-	 */
-	yaffs_HardlinkFixup(dev,hardList);
-
-
-	/*
-	*  Sort out state of unlinked and deleted objects.
-	*/
-	{
-		struct list_head *i;
-		struct list_head *n;
-
-		yaffs_Object *l;
-
-		/* Soft delete all the unlinked files */
-		list_for_each_safe(i, n,
-				   &dev->unlinkedDir->variant.directoryVariant.
-				   children) {
-			if (i) {
-				l = list_entry(i, yaffs_Object, siblings);
-				yaffs_DestroyObject(l);
-			}
-		}
-
-		/* Soft delete all the deletedDir files */
-		list_for_each_safe(i, n,
-				   &dev->deletedDir->variant.directoryVariant.
-				   children) {
-			if (i) {
-				l = list_entry(i, yaffs_Object, siblings);
-				yaffs_DestroyObject(l);
-
+			if (hanging) {
+				yaffs_trace(YAFFS_TRACE_SCAN,
+					"Hanging object %d moved to lost and found",
+					obj->obj_id);
+				yaffs_add_obj_to_dir(dev->lost_n_found, obj);
 			}
 		}
 	}
-
-	yaffs_ReleaseTempBuffer(dev, chunkData, __LINE__);
-
-	if(alloc_failed){
-		return YAFFS_FAIL;
-	}
-
-	T(YAFFS_TRACE_SCAN, (TSTR("yaffs_ScanBackwards ends" TENDSTR)));
-
-	return YAFFS_OK;
 }
 
-/*------------------------------  Directory Functions ----------------------------- */
-
-static void yaffs_RemoveObjectFromDirectory(yaffs_Object * obj)
+/*
+ * Delete directory contents for cleaning up lost and found.
+ */
+static void yaffs_del_dir_contents(struct yaffs_obj *dir)
 {
-	yaffs_Device *dev = obj->myDev;
+	struct yaffs_obj *obj;
+	struct list_head *lh;
+	struct list_head *n;
 
-	if(dev && dev->removeObjectCallback)
-		dev->removeObjectCallback(obj);
+	if (dir->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY)
+		BUG();
 
-	list_del_init(&obj->siblings);
-	obj->parent = NULL;
+	list_for_each_safe(lh, n, &dir->variant.dir_variant.children) {
+		obj = list_entry(lh, struct yaffs_obj, siblings);
+		if (obj->variant_type == YAFFS_OBJECT_TYPE_DIRECTORY)
+			yaffs_del_dir_contents(obj);
+		yaffs_trace(YAFFS_TRACE_SCAN,
+			"Deleting lost_found object %d",
+			obj->obj_id);
+		yaffs_unlink_obj(obj);
+	}
 }
 
-
-static void yaffs_AddObjectToDirectory(yaffs_Object * directory,
-				       yaffs_Object * obj)
+static void yaffs_empty_l_n_f(struct yaffs_dev *dev)
 {
-
-	if (!directory) {
-		T(YAFFS_TRACE_ALWAYS,
-		  (TSTR
-		   ("tragedy: Trying to add an object to a null pointer directory"
-		    TENDSTR)));
-		YBUG();
-	}
-	if (directory->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) {
-		T(YAFFS_TRACE_ALWAYS,
-		  (TSTR
-		   ("tragedy: Trying to add an object to a non-directory"
-		    TENDSTR)));
-		YBUG();
-	}
-
-	if (obj->siblings.prev == NULL) {
-		/* Not initialised */
-		INIT_LIST_HEAD(&obj->siblings);
-
-	} else if (!list_empty(&obj->siblings)) {
-		/* If it is holed up somewhere else, un hook it */
-		yaffs_RemoveObjectFromDirectory(obj);
-	}
-	/* Now add it */
-	list_add(&obj->siblings, &directory->variant.directoryVariant.children);
-	obj->parent = directory;
-
-	if (directory == obj->myDev->unlinkedDir
-	    || directory == obj->myDev->deletedDir) {
-		obj->unlinked = 1;
-		obj->myDev->nUnlinkedFiles++;
-		obj->renameAllowed = 0;
-	}
+	yaffs_del_dir_contents(dev->lost_n_found);
 }
 
-yaffs_Object *yaffs_FindObjectByName(yaffs_Object * directory,
-				     const YCHAR * name)
+
+struct yaffs_obj *yaffs_find_by_name(struct yaffs_obj *directory,
+				     const YCHAR *name)
 {
 	int sum;
-
 	struct list_head *i;
 	YCHAR buffer[YAFFS_MAX_NAME_LENGTH + 1];
+	struct yaffs_obj *l;
 
-	yaffs_Object *l;
-
-	if (!name) {
+	if (!name)
 		return NULL;
-	}
 
 	if (!directory) {
-		T(YAFFS_TRACE_ALWAYS,
-		  (TSTR
-		   ("tragedy: yaffs_FindObjectByName: null pointer directory"
-		    TENDSTR)));
-		YBUG();
+		yaffs_trace(YAFFS_TRACE_ALWAYS,
+			"tragedy: yaffs_find_by_name: null pointer directory"
+			);
+		BUG();
+		return NULL;
 	}
-	if (directory->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) {
-		T(YAFFS_TRACE_ALWAYS,
-		  (TSTR
-		   ("tragedy: yaffs_FindObjectByName: non-directory" TENDSTR)));
-		YBUG();
+	if (directory->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) {
+		yaffs_trace(YAFFS_TRACE_ALWAYS,
+			"tragedy: yaffs_find_by_name: non-directory"
+			);
+		BUG();
 	}
 
-	sum = yaffs_CalcNameSum(name);
+	sum = yaffs_calc_name_sum(name);
 
-	list_for_each(i, &directory->variant.directoryVariant.children) {
-		if (i) {
-			l = list_entry(i, yaffs_Object, siblings);
+	list_for_each(i, &directory->variant.dir_variant.children) {
+		l = list_entry(i, struct yaffs_obj, siblings);
 
-			yaffs_CheckObjectDetailsLoaded(l);
+		if (l->parent != directory)
+			BUG();
 
-			/* Special case for lost-n-found */
-			if (l->objectId == YAFFS_OBJECTID_LOSTNFOUND) {
-				if (yaffs_strcmp(name, YAFFS_LOSTNFOUND_NAME) == 0) {
-					return l;
-				}
-			} else if (yaffs_SumCompare(l->sum, sum) || l->chunkId <= 0)
-			{
-				/* LostnFound cunk called Objxxx
-				 * Do a real check
-				 */
-				yaffs_GetObjectName(l, buffer,
-						    YAFFS_MAX_NAME_LENGTH);
-				if (yaffs_strncmp(name, buffer,YAFFS_MAX_NAME_LENGTH) == 0) {
-					return l;
-				}
+		yaffs_check_obj_details_loaded(l);
 
-			}
+		/* Special case for lost-n-found */
+		if (l->obj_id == YAFFS_OBJECTID_LOSTNFOUND) {
+			if (!yaffs_strcmp(name, YAFFS_LOSTNFOUND_NAME))
+				return l;
+		} else if (l->sum == sum || l->hdr_chunk <= 0) {
+			/* LostnFound chunk called Objxxx
+			 * Do a real check
+			 */
+			yaffs_get_obj_name(l, buffer,
+				YAFFS_MAX_NAME_LENGTH + 1);
+			if (!yaffs_strncmp(name, buffer, YAFFS_MAX_NAME_LENGTH))
+				return l;
 		}
 	}
-
 	return NULL;
 }
 
-
-#if 0
-int yaffs_ApplyToDirectoryChildren(yaffs_Object * theDir,
-				   int (*fn) (yaffs_Object *))
-{
-	struct list_head *i;
-	yaffs_Object *l;
-
-	if (!theDir) {
-		T(YAFFS_TRACE_ALWAYS,
-		  (TSTR
-		   ("tragedy: yaffs_FindObjectByName: null pointer directory"
-		    TENDSTR)));
-		YBUG();
-	}
-	if (theDir->variantType != YAFFS_OBJECT_TYPE_DIRECTORY) {
-		T(YAFFS_TRACE_ALWAYS,
-		  (TSTR
-		   ("tragedy: yaffs_FindObjectByName: non-directory" TENDSTR)));
-		YBUG();
-	}
-
-	list_for_each(i, &theDir->variant.directoryVariant.children) {
-		if (i) {
-			l = list_entry(i, yaffs_Object, siblings);
-			if (l && !fn(l)) {
-				return YAFFS_FAIL;
-			}
-		}
-	}
-
-	return YAFFS_OK;
-
-}
-#endif
-
 /* GetEquivalentObject dereferences any hard links to get to the
  * actual object.
  */
 
-yaffs_Object *yaffs_GetEquivalentObject(yaffs_Object * obj)
+struct yaffs_obj *yaffs_get_equivalent_obj(struct yaffs_obj *obj)
 {
-	if (obj && obj->variantType == YAFFS_OBJECT_TYPE_HARDLINK) {
-		/* We want the object id of the equivalent object, not this one */
-		obj = obj->variant.hardLinkVariant.equivalentObject;
-		yaffs_CheckObjectDetailsLoaded(obj);
+	if (obj && obj->variant_type == YAFFS_OBJECT_TYPE_HARDLINK) {
+		obj = obj->variant.hardlink_variant.equiv_obj;
+		yaffs_check_obj_details_loaded(obj);
 	}
 	return obj;
-
 }
 
-int yaffs_GetObjectName(yaffs_Object * obj, YCHAR * name, int buffSize)
-{
-	memset(name, 0, buffSize * sizeof(YCHAR));
-
-	yaffs_CheckObjectDetailsLoaded(obj);
+/*
+ *  A note or two on object names.
+ *  * If the object name is missing, we then make one up in the form objnnn
+ *
+ *  * ASCII names are stored in the object header's name field from byte zero
+ *  * Unicode names are historically stored starting from byte zero.
+ *
+ * Then there are automatic Unicode names...
+ * The purpose of these is to save names in a way that can be read as
+ * ASCII or Unicode names as appropriate, thus allowing a Unicode and ASCII
+ * system to share files.
+ *
+ * These automatic unicode are stored slightly differently...
+ *  - If the name can fit in the ASCII character space then they are saved as
+ *    ascii names as per above.
+ *  - If the name needs Unicode then the name is saved in Unicode
+ *    starting at oh->name[1].
 
-	if (obj->objectId == YAFFS_OBJECTID_LOSTNFOUND) {
-		yaffs_strncpy(name, YAFFS_LOSTNFOUND_NAME, buffSize - 1);
-	} else if (obj->chunkId <= 0) {
-		YCHAR locName[20];
+ */
+static void yaffs_fix_null_name(struct yaffs_obj *obj, YCHAR *name,
+				int buffer_size)
+{
+	/* Create an object name if we could not find one. */
+	if (yaffs_strnlen(name, YAFFS_MAX_NAME_LENGTH) == 0) {
+		YCHAR local_name[20];
+		YCHAR num_string[20];
+		YCHAR *x = &num_string[19];
+		unsigned v = obj->obj_id;
+		num_string[19] = 0;
+		while (v > 0) {
+			x--;
+			*x = '0' + (v % 10);
+			v /= 10;
+		}
 		/* make up a name */
-		yaffs_sprintf(locName, _Y("%s%d"), YAFFS_LOSTNFOUND_PREFIX,
-			      obj->objectId);
-		yaffs_strncpy(name, locName, buffSize - 1);
-
+		yaffs_strcpy(local_name, YAFFS_LOSTNFOUND_PREFIX);
+		yaffs_strcat(local_name, x);
+		yaffs_strncpy(name, local_name, buffer_size - 1);
 	}
-#ifdef CONFIG_YAFFS_SHORT_NAMES_IN_RAM
-	else if (obj->shortName[0]) {
-		yaffs_strcpy(name, obj->shortName);
-	}
-#endif
-	else {
-		__u8 *buffer = yaffs_GetTempBuffer(obj->myDev, __LINE__);
+}
 
-		yaffs_ObjectHeader *oh = (yaffs_ObjectHeader *) buffer;
+int yaffs_get_obj_name(struct yaffs_obj *obj, YCHAR *name, int buffer_size)
+{
+	memset(name, 0, buffer_size * sizeof(YCHAR));
+	yaffs_check_obj_details_loaded(obj);
+	if (obj->obj_id == YAFFS_OBJECTID_LOSTNFOUND) {
+		yaffs_strncpy(name, YAFFS_LOSTNFOUND_NAME, buffer_size - 1);
+	} else if (obj->short_name[0]) {
+		yaffs_strcpy(name, obj->short_name);
+	} else if (obj->hdr_chunk > 0) {
+		u8 *buffer = yaffs_get_temp_buffer(obj->my_dev);
 
-		memset(buffer, 0, obj->myDev->nDataBytesPerChunk);
+		struct yaffs_obj_hdr *oh = (struct yaffs_obj_hdr *)buffer;
 
-		if (obj->chunkId >= 0) {
-			yaffs_ReadChunkWithTagsFromNAND(obj->myDev,
-							obj->chunkId, buffer,
-							NULL);
+		memset(buffer, 0, obj->my_dev->data_bytes_per_chunk);
+
+		if (obj->hdr_chunk > 0) {
+			yaffs_rd_chunk_tags_nand(obj->my_dev,
+						 obj->hdr_chunk,
+						 buffer, NULL);
 		}
-		yaffs_strncpy(name, oh->name, buffSize - 1);
+		yaffs_load_name_from_oh(obj->my_dev, name, oh->name,
+					buffer_size);
 
-		yaffs_ReleaseTempBuffer(obj->myDev, buffer, __LINE__);
+		yaffs_release_temp_buffer(obj->my_dev, buffer);
 	}
 
-	return yaffs_strlen(name);
+	yaffs_fix_null_name(obj, name, buffer_size);
+
+	return yaffs_strnlen(name, YAFFS_MAX_NAME_LENGTH);
 }
 
-int yaffs_GetObjectFileLength(yaffs_Object * obj)
+loff_t yaffs_get_obj_length(struct yaffs_obj *obj)
 {
-
 	/* Dereference any hard linking */
-	obj = yaffs_GetEquivalentObject(obj);
+	obj = yaffs_get_equivalent_obj(obj);
 
-	if (obj->variantType == YAFFS_OBJECT_TYPE_FILE) {
-		return obj->variant.fileVariant.fileSize;
-	}
-	if (obj->variantType == YAFFS_OBJECT_TYPE_SYMLINK) {
-		return yaffs_strlen(obj->variant.symLinkVariant.alias);
+	if (obj->variant_type == YAFFS_OBJECT_TYPE_FILE)
+		return obj->variant.file_variant.file_size;
+	if (obj->variant_type == YAFFS_OBJECT_TYPE_SYMLINK) {
+		if (!obj->variant.symlink_variant.alias)
+			return 0;
+		return yaffs_strnlen(obj->variant.symlink_variant.alias,
+				     YAFFS_MAX_ALIAS_LENGTH);
 	} else {
 		/* Only a directory should drop through to here */
-		return obj->myDev->nDataBytesPerChunk;
+		return obj->my_dev->data_bytes_per_chunk;
 	}
 }
 
-int yaffs_GetObjectLinkCount(yaffs_Object * obj)
+int yaffs_get_obj_link_count(struct yaffs_obj *obj)
 {
 	int count = 0;
 	struct list_head *i;
 
-	if (!obj->unlinked) {
+	if (!obj->unlinked)
 		count++;	/* the object itself */
-	}
-	list_for_each(i, &obj->hardLinks) {
-		count++;	/* add the hard links; */
-	}
-	return count;
 
+	list_for_each(i, &obj->hard_links)
+	    count++;		/* add the hard links; */
+
+	return count;
 }
 
-int yaffs_GetObjectInode(yaffs_Object * obj)
+int yaffs_get_obj_inode(struct yaffs_obj *obj)
 {
-	obj = yaffs_GetEquivalentObject(obj);
+	obj = yaffs_get_equivalent_obj(obj);
 
-	return obj->objectId;
+	return obj->obj_id;
 }
 
-unsigned yaffs_GetObjectType(yaffs_Object * obj)
+unsigned yaffs_get_obj_type(struct yaffs_obj *obj)
 {
-	obj = yaffs_GetEquivalentObject(obj);
+	obj = yaffs_get_equivalent_obj(obj);
 
-	switch (obj->variantType) {
+	switch (obj->variant_type) {
 	case YAFFS_OBJECT_TYPE_FILE:
 		return DT_REG;
 		break;
@@ -6725,605 +4521,501 @@ unsigned yaffs_GetObjectType(yaffs_Object * obj)
 			return DT_BLK;
 		if (S_ISSOCK(obj->yst_mode))
 			return DT_SOCK;
+		return DT_REG;
+		break;
 	default:
 		return DT_REG;
 		break;
 	}
 }
 
-YCHAR *yaffs_GetSymlinkAlias(yaffs_Object * obj)
+YCHAR *yaffs_get_symlink_alias(struct yaffs_obj *obj)
 {
-	obj = yaffs_GetEquivalentObject(obj);
-	if (obj->variantType == YAFFS_OBJECT_TYPE_SYMLINK) {
-		return yaffs_CloneString(obj->variant.symLinkVariant.alias);
-	} else {
-		return yaffs_CloneString(_Y(""));
-	}
-}
-
-#ifndef CONFIG_YAFFS_WINCE
-
-int yaffs_SetAttributes(yaffs_Object * obj, struct iattr *attr)
-{
-	unsigned int valid = attr->ia_valid;
-
-	if (valid & ATTR_MODE)
-		obj->yst_mode = attr->ia_mode;
-	if (valid & ATTR_UID)
-		obj->yst_uid = attr->ia_uid;
-	if (valid & ATTR_GID)
-		obj->yst_gid = attr->ia_gid;
-
-	if (valid & ATTR_ATIME)
-		obj->yst_atime = Y_TIME_CONVERT(attr->ia_atime);
-	if (valid & ATTR_CTIME)
-		obj->yst_ctime = Y_TIME_CONVERT(attr->ia_ctime);
-	if (valid & ATTR_MTIME)
-		obj->yst_mtime = Y_TIME_CONVERT(attr->ia_mtime);
-
-	if (valid & ATTR_SIZE)
-		yaffs_ResizeFile(obj, attr->ia_size);
-
-	yaffs_UpdateObjectHeader(obj, NULL, 1, 0, 0);
-
-	return YAFFS_OK;
-
-}
-int yaffs_GetAttributes(yaffs_Object * obj, struct iattr *attr)
-{
-	unsigned int valid = 0;
-
-	attr->ia_mode = obj->yst_mode;
-	valid |= ATTR_MODE;
-	attr->ia_uid = obj->yst_uid;
-	valid |= ATTR_UID;
-	attr->ia_gid = obj->yst_gid;
-	valid |= ATTR_GID;
-
-	Y_TIME_CONVERT(attr->ia_atime) = obj->yst_atime;
-	valid |= ATTR_ATIME;
-	Y_TIME_CONVERT(attr->ia_ctime) = obj->yst_ctime;
-	valid |= ATTR_CTIME;
-	Y_TIME_CONVERT(attr->ia_mtime) = obj->yst_mtime;
-	valid |= ATTR_MTIME;
-
-	attr->ia_size = yaffs_GetFileSize(obj);
-	valid |= ATTR_SIZE;
-
-	attr->ia_valid = valid;
-
-	return YAFFS_OK;
-
-}
-
-#endif
-
-#if 0
-int yaffs_DumpObject(yaffs_Object * obj)
-{
-	YCHAR name[257];
-
-	yaffs_GetObjectName(obj, name, 256);
-
-	T(YAFFS_TRACE_ALWAYS,
-	  (TSTR
-	   ("Object %d, inode %d \"%s\"\n dirty %d valid %d serial %d sum %d"
-	    " chunk %d type %d size %d\n"
-	    TENDSTR), obj->objectId, yaffs_GetObjectInode(obj), name,
-	   obj->dirty, obj->valid, obj->serial, obj->sum, obj->chunkId,
-	   yaffs_GetObjectType(obj), yaffs_GetObjectFileLength(obj)));
-
-	return YAFFS_OK;
+	obj = yaffs_get_equivalent_obj(obj);
+	if (obj->variant_type == YAFFS_OBJECT_TYPE_SYMLINK)
+		return yaffs_clone_str(obj->variant.symlink_variant.alias);
+	else
+		return yaffs_clone_str(_Y(""));
 }
-#endif
 
-/*---------------------------- Initialisation code -------------------------------------- */
+/*--------------------------- Initialisation code -------------------------- */
 
-static int yaffs_CheckDevFunctions(const yaffs_Device * dev)
+static int yaffs_check_dev_fns(const struct yaffs_dev *dev)
 {
-
 	/* Common functions, gotta have */
-	if (!dev->eraseBlockInNAND || !dev->initialiseNAND)
+	if (!dev->param.erase_fn || !dev->param.initialise_flash_fn)
 		return 0;
 
-#ifdef CONFIG_YAFFS_YAFFS2
-
 	/* Can use the "with tags" style interface for yaffs1 or yaffs2 */
-	if (dev->writeChunkWithTagsToNAND &&
-	    dev->readChunkWithTagsFromNAND &&
-	    !dev->writeChunkToNAND &&
-	    !dev->readChunkFromNAND &&
-	    dev->markNANDBlockBad && dev->queryNANDBlock)
+	if (dev->param.write_chunk_tags_fn &&
+	    dev->param.read_chunk_tags_fn &&
+	    !dev->param.write_chunk_fn &&
+	    !dev->param.read_chunk_fn &&
+	    dev->param.bad_block_fn && dev->param.query_block_fn)
 		return 1;
-#endif
 
 	/* Can use the "spare" style interface for yaffs1 */
-	if (!dev->isYaffs2 &&
-	    !dev->writeChunkWithTagsToNAND &&
-	    !dev->readChunkWithTagsFromNAND &&
-	    dev->writeChunkToNAND &&
-	    dev->readChunkFromNAND &&
-	    !dev->markNANDBlockBad && !dev->queryNANDBlock)
+	if (!dev->param.is_yaffs2 &&
+	    !dev->param.write_chunk_tags_fn &&
+	    !dev->param.read_chunk_tags_fn &&
+	    dev->param.write_chunk_fn &&
+	    dev->param.read_chunk_fn &&
+	    !dev->param.bad_block_fn && !dev->param.query_block_fn)
 		return 1;
 
 	return 0;		/* bad */
 }
 
-
-static int yaffs_CreateInitialDirectories(yaffs_Device *dev)
-{
-	/* Initialise the unlinked, deleted, root and lost and found directories */
-
-	dev->lostNFoundDir = dev->rootDir =  NULL;
-	dev->unlinkedDir = dev->deletedDir = NULL;
-
-	dev->unlinkedDir =
-	    yaffs_CreateFakeDirectory(dev, YAFFS_OBJECTID_UNLINKED, S_IFDIR);
-
-	dev->deletedDir =
-	    yaffs_CreateFakeDirectory(dev, YAFFS_OBJECTID_DELETED, S_IFDIR);
-
-	dev->rootDir =
-	    yaffs_CreateFakeDirectory(dev, YAFFS_OBJECTID_ROOT,
-				      YAFFS_ROOT_MODE | S_IFDIR);
-	dev->lostNFoundDir =
-	    yaffs_CreateFakeDirectory(dev, YAFFS_OBJECTID_LOSTNFOUND,
-				      YAFFS_LOSTNFOUND_MODE | S_IFDIR);
-
-	if(dev->lostNFoundDir && dev->rootDir && dev->unlinkedDir && dev->deletedDir){
-		yaffs_AddObjectToDirectory(dev->rootDir, dev->lostNFoundDir);
+static int yaffs_create_initial_dir(struct yaffs_dev *dev)
+{
+	/* Initialise the unlinked, deleted, root and lost+found directories */
+	dev->lost_n_found = dev->root_dir = NULL;
+	dev->unlinked_dir = dev->del_dir = NULL;
+	dev->unlinked_dir =
+	    yaffs_create_fake_dir(dev, YAFFS_OBJECTID_UNLINKED, S_IFDIR);
+	dev->del_dir =
+	    yaffs_create_fake_dir(dev, YAFFS_OBJECTID_DELETED, S_IFDIR);
+	dev->root_dir =
+	    yaffs_create_fake_dir(dev, YAFFS_OBJECTID_ROOT,
+				  YAFFS_ROOT_MODE | S_IFDIR);
+	dev->lost_n_found =
+	    yaffs_create_fake_dir(dev, YAFFS_OBJECTID_LOSTNFOUND,
+				  YAFFS_LOSTNFOUND_MODE | S_IFDIR);
+
+	if (dev->lost_n_found && dev->root_dir && dev->unlinked_dir
+	    && dev->del_dir) {
+		yaffs_add_obj_to_dir(dev->root_dir, dev->lost_n_found);
 		return YAFFS_OK;
 	}
-
 	return YAFFS_FAIL;
 }
 
-int yaffs_GutsInitialise(yaffs_Device * dev)
+int yaffs_guts_initialise(struct yaffs_dev *dev)
 {
 	int init_failed = 0;
 	unsigned x;
 	int bits;
 
-	T(YAFFS_TRACE_TRACING, (TSTR("yaffs: yaffs_GutsInitialise()" TENDSTR)));
+	yaffs_trace(YAFFS_TRACE_TRACING, "yaffs: yaffs_guts_initialise()");
 
 	/* Check stuff that must be set */
 
 	if (!dev) {
-		T(YAFFS_TRACE_ALWAYS, (TSTR("yaffs: Need a device" TENDSTR)));
+		yaffs_trace(YAFFS_TRACE_ALWAYS,
+			"yaffs: Need a device"
+			);
+		return YAFFS_FAIL;
+	}
+
+	if (dev->is_mounted) {
+		yaffs_trace(YAFFS_TRACE_ALWAYS, "device already mounted");
 		return YAFFS_FAIL;
 	}
 
-	dev->internalStartBlock = dev->startBlock;
-	dev->internalEndBlock = dev->endBlock;
-	dev->blockOffset = 0;
-	dev->chunkOffset = 0;
-	dev->nFreeChunks = 0;
+	dev->internal_start_block = dev->param.start_block;
+	dev->internal_end_block = dev->param.end_block;
+	dev->block_offset = 0;
+	dev->chunk_offset = 0;
+	dev->n_free_chunks = 0;
+
+	dev->gc_block = 0;
 
-	if (dev->startBlock == 0) {
-		dev->internalStartBlock = dev->startBlock + 1;
-		dev->internalEndBlock = dev->endBlock + 1;
-		dev->blockOffset = 1;
-		dev->chunkOffset = dev->nChunksPerBlock;
+	if (dev->param.start_block == 0) {
+		dev->internal_start_block = dev->param.start_block + 1;
+		dev->internal_end_block = dev->param.end_block + 1;
+		dev->block_offset = 1;
+		dev->chunk_offset = dev->param.chunks_per_block;
 	}
 
 	/* Check geometry parameters. */
 
-	if ((dev->isYaffs2 && dev->nDataBytesPerChunk < 1024) ||
-	    (!dev->isYaffs2 && dev->nDataBytesPerChunk != 512) ||
-	     dev->nChunksPerBlock < 2 ||
-	     dev->nReservedBlocks < 2 ||
-	     dev->internalStartBlock <= 0 ||
-	     dev->internalEndBlock <= 0 ||
-	     dev->internalEndBlock <= (dev->internalStartBlock + dev->nReservedBlocks + 2)	// otherwise it is too small
-	    ) {
-		T(YAFFS_TRACE_ALWAYS,
-		  (TSTR
-		   ("yaffs: NAND geometry problems: chunk size %d, type is yaffs%s "
-		    TENDSTR), dev->nDataBytesPerChunk, dev->isYaffs2 ? "2" : ""));
+	if ((!dev->param.inband_tags && dev->param.is_yaffs2 &&
+		dev->param.total_bytes_per_chunk < 1024) ||
+		(!dev->param.is_yaffs2 &&
+			dev->param.total_bytes_per_chunk < 512) ||
+		(dev->param.inband_tags && !dev->param.is_yaffs2) ||
+		 dev->param.chunks_per_block < 2 ||
+		 dev->param.n_reserved_blocks < 2 ||
+		dev->internal_start_block <= 0 ||
+		dev->internal_end_block <= 0 ||
+		dev->internal_end_block <=
+		(dev->internal_start_block + dev->param.n_reserved_blocks + 2)
+		) {
+		/* otherwise it is too small */
+		yaffs_trace(YAFFS_TRACE_ALWAYS,
+			"NAND geometry problems: chunk size %d, type is yaffs%s, inband_tags %d ",
+			dev->param.total_bytes_per_chunk,
+			dev->param.is_yaffs2 ? "2" : "",
+			dev->param.inband_tags);
 		return YAFFS_FAIL;
 	}
 
-	if (yaffs_InitialiseNAND(dev) != YAFFS_OK) {
-		T(YAFFS_TRACE_ALWAYS,
-		  (TSTR("yaffs: InitialiseNAND failed" TENDSTR)));
+	if (yaffs_init_nand(dev) != YAFFS_OK) {
+		yaffs_trace(YAFFS_TRACE_ALWAYS, "InitialiseNAND failed");
 		return YAFFS_FAIL;
 	}
 
+	/* Sort out space for inband tags, if required */
+	if (dev->param.inband_tags)
+		dev->data_bytes_per_chunk =
+		    dev->param.total_bytes_per_chunk -
+		    sizeof(struct yaffs_packed_tags2_tags_only);
+	else
+		dev->data_bytes_per_chunk = dev->param.total_bytes_per_chunk;
+
 	/* Got the right mix of functions? */
-	if (!yaffs_CheckDevFunctions(dev)) {
+	if (!yaffs_check_dev_fns(dev)) {
 		/* Function missing */
-		T(YAFFS_TRACE_ALWAYS,
-		  (TSTR
-		   ("yaffs: device function(s) missing or wrong\n" TENDSTR)));
+		yaffs_trace(YAFFS_TRACE_ALWAYS,
+			"device function(s) missing or wrong");
 
 		return YAFFS_FAIL;
 	}
 
-	/* This is really a compilation check. */
-	if (!yaffs_CheckStructures()) {
-		T(YAFFS_TRACE_ALWAYS,
-		  (TSTR("yaffs_CheckStructures failed\n" TENDSTR)));
-		return YAFFS_FAIL;
-	}
-
-	if (dev->isMounted) {
-		T(YAFFS_TRACE_ALWAYS,
-		  (TSTR("yaffs: device already mounted\n" TENDSTR)));
-		return YAFFS_FAIL;
-	}
-
-	/* Finished with most checks. One or two more checks happen later on too. */
-
-	dev->isMounted = 1;
-
+	/* Finished with most checks. Further checks happen later on too. */
 
+	dev->is_mounted = 1;
 
 	/* OK now calculate a few things for the device */
 
 	/*
 	 *  Calculate all the chunk size manipulation numbers:
 	 */
-	 /* Start off assuming it is a power of 2 */
-	 dev->chunkShift = ShiftDiv(dev->nDataBytesPerChunk);
-	 dev->chunkMask = (1<<dev->chunkShift) - 1;
-
-	 if(dev->nDataBytesPerChunk == (dev->chunkMask + 1)){
-		/* Yes it is a power of 2, disable crumbs */
-		dev->crumbMask = 0;
-		dev->crumbShift = 0;
-		dev->crumbsPerChunk = 0;
-	 } else {
-		/* Not a power of 2, use crumbs instead */
-		dev->crumbShift = ShiftDiv(sizeof(yaffs_PackedTags2TagsPart));
-		dev->crumbMask = (1<<dev->crumbShift)-1;
-		dev->crumbsPerChunk = dev->nDataBytesPerChunk/(1 << dev->crumbShift);
-		dev->chunkShift = 0;
-		dev->chunkMask = 0;
-	}
-
+	x = dev->data_bytes_per_chunk;
+	/* We always use dev->chunk_shift and dev->chunk_div */
+	dev->chunk_shift = calc_shifts(x);
+	x >>= dev->chunk_shift;
+	dev->chunk_div = x;
+	/* We only use chunk mask if chunk_div is 1 */
+	dev->chunk_mask = (1 << dev->chunk_shift) - 1;
 
 	/*
-	 * Calculate chunkGroupBits.
-	 * We need to find the next power of 2 > than internalEndBlock
+	 * Calculate chunk_grp_bits.
+	 * We need to find the next power of 2 > than internal_end_block
 	 */
 
-	x = dev->nChunksPerBlock * (dev->internalEndBlock + 1);
+	x = dev->param.chunks_per_block * (dev->internal_end_block + 1);
 
-	bits = ShiftsGE(x);
+	bits = calc_shifts_ceiling(x);
 
 	/* Set up tnode width if wide tnodes are enabled. */
-	if(!dev->wideTnodesDisabled){
+	if (!dev->param.wide_tnodes_disabled) {
 		/* bits must be even so that we end up with 32-bit words */
-		if(bits & 1)
+		if (bits & 1)
 			bits++;
-		if(bits < 16)
-			dev->tnodeWidth = 16;
+		if (bits < 16)
+			dev->tnode_width = 16;
 		else
-			dev->tnodeWidth = bits;
+			dev->tnode_width = bits;
+	} else {
+		dev->tnode_width = 16;
 	}
-	else
-		dev->tnodeWidth = 16;
 
-	dev->tnodeMask = (1<<dev->tnodeWidth)-1;
+	dev->tnode_mask = (1 << dev->tnode_width) - 1;
 
 	/* Level0 Tnodes are 16 bits or wider (if wide tnodes are enabled),
 	 * so if the bitwidth of the
 	 * chunk range we're using is greater than 16 we need
-	 * to figure out chunk shift and chunkGroupSize
+	 * to figure out chunk shift and chunk_grp_size
 	 */
 
-	if (bits <= dev->tnodeWidth)
-		dev->chunkGroupBits = 0;
+	if (bits <= dev->tnode_width)
+		dev->chunk_grp_bits = 0;
 	else
-		dev->chunkGroupBits = bits - dev->tnodeWidth;
+		dev->chunk_grp_bits = bits - dev->tnode_width;
 
+	dev->tnode_size = (dev->tnode_width * YAFFS_NTNODES_LEVEL0) / 8;
+	if (dev->tnode_size < sizeof(struct yaffs_tnode))
+		dev->tnode_size = sizeof(struct yaffs_tnode);
 
-	dev->chunkGroupSize = 1 << dev->chunkGroupBits;
+	dev->chunk_grp_size = 1 << dev->chunk_grp_bits;
 
-	if (dev->nChunksPerBlock < dev->chunkGroupSize) {
+	if (dev->param.chunks_per_block < dev->chunk_grp_size) {
 		/* We have a problem because the soft delete won't work if
 		 * the chunk group size > chunks per block.
 		 * This can be remedied by using larger "virtual blocks".
 		 */
-		T(YAFFS_TRACE_ALWAYS,
-		  (TSTR("yaffs: chunk group too large\n" TENDSTR)));
+		yaffs_trace(YAFFS_TRACE_ALWAYS, "chunk group too large");
 
 		return YAFFS_FAIL;
 	}
 
-	/* OK, we've finished verifying the device, lets continue with initialisation */
+	/* Finished verifying the device, continue with initialisation */
 
 	/* More device initialisation */
-	dev->garbageCollections = 0;
-	dev->passiveGarbageCollections = 0;
-	dev->currentDirtyChecker = 0;
-	dev->bufferedBlock = -1;
-	dev->doingBufferedBlockRewrite = 0;
-	dev->nDeletedFiles = 0;
-	dev->nBackgroundDeletions = 0;
-	dev->nUnlinkedFiles = 0;
-	dev->eccFixed = 0;
-	dev->eccUnfixed = 0;
-	dev->tagsEccFixed = 0;
-	dev->tagsEccUnfixed = 0;
-	dev->nErasureFailures = 0;
-	dev->nErasedBlocks = 0;
-	dev->isDoingGC = 0;
-	dev->hasPendingPrioritisedGCs = 1; /* Assume the worst for now, will get fixed on first GC */
+	dev->all_gcs = 0;
+	dev->passive_gc_count = 0;
+	dev->oldest_dirty_gc_count = 0;
+	dev->bg_gcs = 0;
+	dev->gc_block_finder = 0;
+	dev->buffered_block = -1;
+	dev->doing_buffered_block_rewrite = 0;
+	dev->n_deleted_files = 0;
+	dev->n_bg_deletions = 0;
+	dev->n_unlinked_files = 0;
+	dev->n_ecc_fixed = 0;
+	dev->n_ecc_unfixed = 0;
+	dev->n_tags_ecc_fixed = 0;
+	dev->n_tags_ecc_unfixed = 0;
+	dev->n_erase_failures = 0;
+	dev->n_erased_blocks = 0;
+	dev->gc_disable = 0;
+	dev->has_pending_prioritised_gc = 1;
+		/* Assume the worst for now, will get fixed on first GC */
+	INIT_LIST_HEAD(&dev->dirty_dirs);
+	dev->oldest_dirty_seq = 0;
+	dev->oldest_dirty_block = 0;
 
 	/* Initialise temporary buffers and caches. */
-	if(!yaffs_InitialiseTempBuffers(dev))
+	if (!yaffs_init_tmp_buffers(dev))
 		init_failed = 1;
 
-	dev->srCache = NULL;
-	dev->gcCleanupList = NULL;
+	dev->cache = NULL;
+	dev->gc_cleanup_list = NULL;
 
-
-	if (!init_failed &&
-	    dev->nShortOpCaches > 0) {
+	if (!init_failed && dev->param.n_caches > 0) {
 		int i;
-		__u8 *buf;
-		int srCacheBytes = dev->nShortOpCaches * sizeof(yaffs_ChunkCache);
+		void *buf;
+		int cache_bytes =
+		    dev->param.n_caches * sizeof(struct yaffs_cache);
 
-		if (dev->nShortOpCaches > YAFFS_MAX_SHORT_OP_CACHES) {
-			dev->nShortOpCaches = YAFFS_MAX_SHORT_OP_CACHES;
-		}
+		if (dev->param.n_caches > YAFFS_MAX_SHORT_OP_CACHES)
+			dev->param.n_caches = YAFFS_MAX_SHORT_OP_CACHES;
 
-		dev->srCache = YMALLOC(srCacheBytes);
-		buf = (__u8 *)dev->srCache;
+		dev->cache = kmalloc(cache_bytes, GFP_NOFS);
 
-		if(dev->srCache)
-			memset(dev->srCache,0,srCacheBytes);
+		buf = (u8 *) dev->cache;
 
-		for (i = 0; i < dev->nShortOpCaches && buf; i++) {
-			dev->srCache[i].object = NULL;
-			dev->srCache[i].lastUse = 0;
-			dev->srCache[i].dirty = 0;
-			dev->srCache[i].data = buf = YMALLOC_DMA(dev->nDataBytesPerChunk);
+		if (dev->cache)
+			memset(dev->cache, 0, cache_bytes);
+
+		for (i = 0; i < dev->param.n_caches && buf; i++) {
+			dev->cache[i].object = NULL;
+			dev->cache[i].last_use = 0;
+			dev->cache[i].dirty = 0;
+			dev->cache[i].data = buf =
+			    kmalloc(dev->param.total_bytes_per_chunk, GFP_NOFS);
 		}
-		if(!buf)
+		if (!buf)
 			init_failed = 1;
 
-		dev->srLastUse = 0;
+		dev->cache_last_use = 0;
 	}
 
-	dev->cacheHits = 0;
+	dev->cache_hits = 0;
 
-	if(!init_failed){
-		dev->gcCleanupList = YMALLOC(dev->nChunksPerBlock * sizeof(__u32));
-		if(!dev->gcCleanupList)
+	if (!init_failed) {
+		dev->gc_cleanup_list =
+		    kmalloc(dev->param.chunks_per_block * sizeof(u32),
+					GFP_NOFS);
+		if (!dev->gc_cleanup_list)
 			init_failed = 1;
 	}
 
-	if (dev->isYaffs2) {
-		dev->useHeaderFileSize = 1;
-	}
-	if(!init_failed && !yaffs_InitialiseBlocks(dev))
+	if (dev->param.is_yaffs2)
+		dev->param.use_header_file_size = 1;
+
+	if (!init_failed && !yaffs_init_blocks(dev))
 		init_failed = 1;
 
-	yaffs_InitialiseTnodes(dev);
-	yaffs_InitialiseObjects(dev);
+	yaffs_init_tnodes_and_objs(dev);
 
-	if(!init_failed && !yaffs_CreateInitialDirectories(dev))
+	if (!init_failed && !yaffs_create_initial_dir(dev))
 		init_failed = 1;
 
+	if (!init_failed && dev->param.is_yaffs2 &&
+		!dev->param.disable_summary &&
+		!yaffs_summary_init(dev))
+		init_failed = 1;
 
-	if(!init_failed){
+	if (!init_failed) {
 		/* Now scan the flash. */
-		if (dev->isYaffs2) {
-			if(yaffs_CheckpointRestore(dev)) {
-				T(YAFFS_TRACE_ALWAYS,
-				  (TSTR("yaffs: restored from checkpoint" TENDSTR)));
+		if (dev->param.is_yaffs2) {
+			if (yaffs2_checkpt_restore(dev)) {
+				yaffs_check_obj_details_loaded(dev->root_dir);
+				yaffs_trace(YAFFS_TRACE_CHECKPOINT |
+					YAFFS_TRACE_MOUNT,
+					"yaffs: restored from checkpoint"
+					);
 			} else {
 
-				/* Clean up the mess caused by an aborted checkpoint load
-				 * and scan backwards.
+				/* Clean up the mess caused by an aborted
+				 * checkpoint load then scan backwards.
 				 */
-				yaffs_DeinitialiseBlocks(dev);
-				yaffs_DeinitialiseTnodes(dev);
-				yaffs_DeinitialiseObjects(dev);
+				yaffs_deinit_blocks(dev);
 
+				yaffs_deinit_tnodes_and_objs(dev);
 
-				dev->nErasedBlocks = 0;
-				dev->nFreeChunks = 0;
-				dev->allocationBlock = -1;
-				dev->allocationPage = -1;
-				dev->nDeletedFiles = 0;
-				dev->nUnlinkedFiles = 0;
-				dev->nBackgroundDeletions = 0;
-				dev->oldestDirtySequence = 0;
+				dev->n_erased_blocks = 0;
+				dev->n_free_chunks = 0;
+				dev->alloc_block = -1;
+				dev->alloc_page = -1;
+				dev->n_deleted_files = 0;
+				dev->n_unlinked_files = 0;
+				dev->n_bg_deletions = 0;
 
-				if(!init_failed && !yaffs_InitialiseBlocks(dev))
+				if (!init_failed && !yaffs_init_blocks(dev))
 					init_failed = 1;
 
-				yaffs_InitialiseTnodes(dev);
-				yaffs_InitialiseObjects(dev);
+				yaffs_init_tnodes_and_objs(dev);
 
-				if(!init_failed && !yaffs_CreateInitialDirectories(dev))
+				if (!init_failed
+				    && !yaffs_create_initial_dir(dev))
 					init_failed = 1;
 
-				if(!init_failed && !yaffs_ScanBackwards(dev))
+				if (!init_failed && !yaffs2_scan_backwards(dev))
 					init_failed = 1;
 			}
-		}else
-			if(!yaffs_Scan(dev))
-				init_failed = 1;
+		} else if (!yaffs1_scan(dev)) {
+			init_failed = 1;
+		}
+
+		yaffs_strip_deleted_objs(dev);
+		yaffs_fix_hanging_objs(dev);
+		if (dev->param.empty_lost_n_found)
+			yaffs_empty_l_n_f(dev);
 	}
 
-	if(init_failed){
+	if (init_failed) {
 		/* Clean up the mess */
-		T(YAFFS_TRACE_TRACING,
-		  (TSTR("yaffs: yaffs_GutsInitialise() aborted.\n" TENDSTR)));
+		yaffs_trace(YAFFS_TRACE_TRACING,
+		  "yaffs: yaffs_guts_initialise() aborted.");
 
-		yaffs_Deinitialise(dev);
+		yaffs_deinitialise(dev);
 		return YAFFS_FAIL;
 	}
 
 	/* Zero out stats */
-	dev->nPageReads = 0;
-	dev->nPageWrites = 0;
-	dev->nBlockErasures = 0;
-	dev->nGCCopies = 0;
-	dev->nRetriedWrites = 0;
+	dev->n_page_reads = 0;
+	dev->n_page_writes = 0;
+	dev->n_erasures = 0;
+	dev->n_gc_copies = 0;
+	dev->n_retried_writes = 0;
 
-	dev->nRetiredBlocks = 0;
+	dev->n_retired_blocks = 0;
 
-	yaffs_VerifyFreeChunks(dev);
-	yaffs_VerifyBlocks(dev);
+	yaffs_verify_free_chunks(dev);
+	yaffs_verify_blocks(dev);
 
+	/* Clean up any aborted checkpoint data */
+	if (!dev->is_checkpointed && dev->blocks_in_checkpt > 0)
+		yaffs2_checkpt_invalidate(dev);
 
-	T(YAFFS_TRACE_TRACING,
-	  (TSTR("yaffs: yaffs_GutsInitialise() done.\n" TENDSTR)));
+	yaffs_trace(YAFFS_TRACE_TRACING,
+	  "yaffs: yaffs_guts_initialise() done.");
 	return YAFFS_OK;
-
 }
 
-void yaffs_Deinitialise(yaffs_Device * dev)
+void yaffs_deinitialise(struct yaffs_dev *dev)
 {
-	if (dev->isMounted) {
+	if (dev->is_mounted) {
 		int i;
 
-		yaffs_DeinitialiseBlocks(dev);
-		yaffs_DeinitialiseTnodes(dev);
-		yaffs_DeinitialiseObjects(dev);
-		if (dev->nShortOpCaches > 0 &&
-		    dev->srCache) {
+		yaffs_deinit_blocks(dev);
+		yaffs_deinit_tnodes_and_objs(dev);
+		yaffs_summary_deinit(dev);
+
+		if (dev->param.n_caches > 0 && dev->cache) {
 
-			for (i = 0; i < dev->nShortOpCaches; i++) {
-				if(dev->srCache[i].data)
-					YFREE(dev->srCache[i].data);
-				dev->srCache[i].data = NULL;
+			for (i = 0; i < dev->param.n_caches; i++) {
+				kfree(dev->cache[i].data);
+				dev->cache[i].data = NULL;
 			}
 
-			YFREE(dev->srCache);
-			dev->srCache = NULL;
+			kfree(dev->cache);
+			dev->cache = NULL;
 		}
 
-		YFREE(dev->gcCleanupList);
+		kfree(dev->gc_cleanup_list);
 
-		for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) {
-			YFREE(dev->tempBuffer[i].buffer);
-		}
+		for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++)
+			kfree(dev->temp_buffer[i].buffer);
 
-		dev->isMounted = 0;
-	}
+		dev->is_mounted = 0;
 
+		if (dev->param.deinitialise_flash_fn)
+			dev->param.deinitialise_flash_fn(dev);
+	}
 }
 
-static int yaffs_CountFreeChunks(yaffs_Device * dev)
+int yaffs_count_free_chunks(struct yaffs_dev *dev)
 {
-	int nFree;
+	int n_free = 0;
 	int b;
+	struct yaffs_block_info *blk;
 
-	yaffs_BlockInfo *blk;
-
-	for (nFree = 0, b = dev->internalStartBlock; b <= dev->internalEndBlock;
-	     b++) {
-		blk = yaffs_GetBlockInfo(dev, b);
-
-		switch (blk->blockState) {
+	blk = dev->block_info;
+	for (b = dev->internal_start_block; b <= dev->internal_end_block; b++) {
+		switch (blk->block_state) {
 		case YAFFS_BLOCK_STATE_EMPTY:
 		case YAFFS_BLOCK_STATE_ALLOCATING:
 		case YAFFS_BLOCK_STATE_COLLECTING:
 		case YAFFS_BLOCK_STATE_FULL:
-			nFree +=
-			    (dev->nChunksPerBlock - blk->pagesInUse +
-			     blk->softDeletions);
+			n_free +=
+			    (dev->param.chunks_per_block - blk->pages_in_use +
+			     blk->soft_del_pages);
 			break;
 		default:
 			break;
 		}
-
+		blk++;
 	}
-
-	return nFree;
+	return n_free;
 }
 
-int yaffs_GetNumberOfFreeChunks(yaffs_Device * dev)
+int yaffs_get_n_free_chunks(struct yaffs_dev *dev)
 {
 	/* This is what we report to the outside world */
+	int n_free;
+	int n_dirty_caches;
+	int blocks_for_checkpt;
+	int i;
 
-	int nFree;
-	int nDirtyCacheChunks;
-	int blocksForCheckpoint;
-
-#if 1
-	nFree = dev->nFreeChunks;
-#else
-	nFree = yaffs_CountFreeChunks(dev);
-#endif
-
-	nFree += dev->nDeletedFiles;
+	n_free = dev->n_free_chunks;
+	n_free += dev->n_deleted_files;
 
-	/* Now count the number of dirty chunks in the cache and subtract those */
+	/* Now count and subtract the number of dirty chunks in the cache. */
 
-	{
-		int i;
-		for (nDirtyCacheChunks = 0, i = 0; i < dev->nShortOpCaches; i++) {
-			if (dev->srCache[i].dirty)
-				nDirtyCacheChunks++;
-		}
+	for (n_dirty_caches = 0, i = 0; i < dev->param.n_caches; i++) {
+		if (dev->cache[i].dirty)
+			n_dirty_caches++;
 	}
 
-	nFree -= nDirtyCacheChunks;
-
-	nFree -= ((dev->nReservedBlocks + 1) * dev->nChunksPerBlock);
+	n_free -= n_dirty_caches;
 
-	/* Now we figure out how much to reserve for the checkpoint and report that... */
-	blocksForCheckpoint = dev->nCheckpointReservedBlocks - dev->blocksInCheckpoint;
-	if(blocksForCheckpoint < 0)
-		blocksForCheckpoint = 0;
+	n_free -=
+	    ((dev->param.n_reserved_blocks + 1) * dev->param.chunks_per_block);
 
-	nFree -= (blocksForCheckpoint * dev->nChunksPerBlock);
+	/* Now figure checkpoint space and report that... */
+	blocks_for_checkpt = yaffs_calc_checkpt_blocks_required(dev);
 
-	if (nFree < 0)
-		nFree = 0;
+	n_free -= (blocks_for_checkpt * dev->param.chunks_per_block);
 
-	return nFree;
+	if (n_free < 0)
+		n_free = 0;
 
+	return n_free;
 }
 
-static int yaffs_freeVerificationFailures;
-
-static void yaffs_VerifyFreeChunks(yaffs_Device * dev)
+/*\
+ * Marshalling functions to get loff_t file sizes into aand out of
+ * object headers.
+ */
+void yaffs_oh_size_load(struct yaffs_obj_hdr *oh, loff_t fsize)
 {
-	int counted;
-	int difference;
-
-	if(yaffs_SkipVerification(dev))
-		return;
-
-	counted = yaffs_CountFreeChunks(dev);
-
-	difference = dev->nFreeChunks - counted;
-
-	if (difference) {
-		T(YAFFS_TRACE_ALWAYS,
-		  (TSTR("Freechunks verification failure %d %d %d" TENDSTR),
-		   dev->nFreeChunks, counted, difference));
-		yaffs_freeVerificationFailures++;
-	}
+	oh->file_size_low = (fsize & 0xFFFFFFFF);
+	oh->file_size_high = ((fsize >> 32) & 0xFFFFFFFF);
 }
 
-/*---------------------------------------- YAFFS test code ----------------------*/
-
-#define yaffs_CheckStruct(structure,syze, name) \
-	   if(sizeof(structure) != syze) \
-	       { \
-		 T(YAFFS_TRACE_ALWAYS,(TSTR("%s should be %d but is %d\n" TENDSTR),\
-		 name,syze,sizeof(structure))); \
-		 return YAFFS_FAIL; \
-		}
-
-static int yaffs_CheckStructures(void)
+loff_t yaffs_oh_to_size(struct yaffs_obj_hdr *oh)
 {
-/*      yaffs_CheckStruct(yaffs_Tags,8,"yaffs_Tags") */
-/*      yaffs_CheckStruct(yaffs_TagsUnion,8,"yaffs_TagsUnion") */
-/*      yaffs_CheckStruct(yaffs_Spare,16,"yaffs_Spare") */
-#ifndef CONFIG_YAFFS_TNODE_LIST_DEBUG
-	yaffs_CheckStruct(yaffs_Tnode, 2 * YAFFS_NTNODES_LEVEL0, "yaffs_Tnode")
-#endif
-	    yaffs_CheckStruct(yaffs_ObjectHeader, 512, "yaffs_ObjectHeader")
+	loff_t retval;
+
+	if (~(oh->file_size_high))
+		retval = (((loff_t) oh->file_size_high) << 32) |
+			(((loff_t) oh->file_size_low) & 0xFFFFFFFF);
+	else
+		retval = (loff_t) oh->file_size_low;
 
-	    return YAFFS_OK;
+	return retval;
 }
diff --git a/fs/yaffs2/yaffs_guts.h b/fs/yaffs2/yaffs_guts.h
index 1f75efd098..e3558c5a6d 100644
--- a/fs/yaffs2/yaffs_guts.h
+++ b/fs/yaffs2/yaffs_guts.h
@@ -1,7 +1,7 @@
 /*
  * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
  *
- * Copyright (C) 2002-2007 Aleph One Ltd.
+ * Copyright (C) 2002-2011 Aleph One Ltd.
  *   for Toby Churchill Ltd and Brightstar Engineering
  *
  * Created by Charles Manning <charles@aleph1.co.uk>
@@ -16,7 +16,6 @@
 #ifndef __YAFFS_GUTS_H__
 #define __YAFFS_GUTS_H__
 
-#include "devextras.h"
 #include "yportenv.h"
 
 #define YAFFS_OK	1
@@ -24,35 +23,48 @@
 
 /* Give us a  Y=0x59,
  * Give us an A=0x41,
- * Give us an FF=0xFF
+ * Give us an FF=0xff
  * Give us an S=0x53
  * And what have we got...
  */
-#define YAFFS_MAGIC			0x5941FF53
+#define YAFFS_MAGIC			0x5941ff53
 
-#define YAFFS_NTNODES_LEVEL0	  	16
+/*
+ * Tnodes form a tree with the tnodes in "levels"
+ * Levels greater than 0 hold 8 slots which point to other tnodes.
+ * Those at level 0 hold 16 slots which point to chunks in NAND.
+ *
+ * A maximum level of 8 thust supports files of size up to:
+ *
+ * 2^(3*MAX_LEVEL+4)
+ *
+ * Thus a max level of 8 supports files with up to 2^^28 chunks which gives
+ * a maximum file size of arounf 51Gbytees with 2k chunks.
+ */
+#define YAFFS_NTNODES_LEVEL0		16
 #define YAFFS_TNODES_LEVEL0_BITS	4
 #define YAFFS_TNODES_LEVEL0_MASK	0xf
 
-#define YAFFS_NTNODES_INTERNAL 		(YAFFS_NTNODES_LEVEL0 / 2)
-#define YAFFS_TNODES_INTERNAL_BITS 	(YAFFS_TNODES_LEVEL0_BITS - 1)
+#define YAFFS_NTNODES_INTERNAL		(YAFFS_NTNODES_LEVEL0 / 2)
+#define YAFFS_TNODES_INTERNAL_BITS	(YAFFS_TNODES_LEVEL0_BITS - 1)
 #define YAFFS_TNODES_INTERNAL_MASK	0x7
-#define YAFFS_TNODES_MAX_LEVEL		6
+#define YAFFS_TNODES_MAX_LEVEL		8
+#define YAFFS_TNODES_MAX_BITS		(YAFFS_TNODES_LEVEL0_BITS + \
+					YAFFS_TNODES_INTERNAL_BITS * \
+					YAFFS_TNODES_MAX_LEVEL)
+#define YAFFS_MAX_CHUNK_ID		((1 << YAFFS_TNODES_MAX_BITS) - 1)
 
-#ifndef CONFIG_YAFFS_NO_YAFFS1
+/* Constants for YAFFS1 mode */
 #define YAFFS_BYTES_PER_SPARE		16
 #define YAFFS_BYTES_PER_CHUNK		512
 #define YAFFS_CHUNK_SIZE_SHIFT		9
 #define YAFFS_CHUNKS_PER_BLOCK		32
-#define YAFFS_BYTES_PER_BLOCK		(YAFFS_CHUNKS_PER_BLOCK*YAFFS_BYTES_PER_CHUNK)
-#endif
+#define YAFFS_BYTES_PER_BLOCK	(YAFFS_CHUNKS_PER_BLOCK*YAFFS_BYTES_PER_CHUNK)
 
-#define YAFFS_MIN_YAFFS2_CHUNK_SIZE 	1024
+#define YAFFS_MIN_YAFFS2_CHUNK_SIZE	1024
 #define YAFFS_MIN_YAFFS2_SPARE_SIZE	32
 
-#define YAFFS_MAX_CHUNK_ID		0x000FFFFF
 
-#define YAFFS_UNUSED_OBJECT_ID		0x0003FFFF
 
 #define YAFFS_ALLOCATION_NOBJECTS	100
 #define YAFFS_ALLOCATION_NTNODES	100
@@ -60,10 +72,12 @@
 
 #define YAFFS_NOBJECT_BUCKETS		256
 
-
 #define YAFFS_OBJECT_SPACE		0x40000
+#define YAFFS_MAX_OBJECT_ID		(YAFFS_OBJECT_SPACE - 1)
 
-#define YAFFS_CHECKPOINT_VERSION 	3
+/* Binary data version stamps */
+#define YAFFS_SUMMARY_VERSION		1
+#define YAFFS_CHECKPOINT_VERSION	6
 
 #ifdef CONFIG_YAFFS_UNICODE
 #define YAFFS_MAX_NAME_LENGTH		127
@@ -81,16 +95,16 @@
 #define YAFFS_OBJECTID_UNLINKED		3
 #define YAFFS_OBJECTID_DELETED		4
 
-/* Sseudo object ids for checkpointing */
-#define YAFFS_OBJECTID_SB_HEADER	0x10
-#define YAFFS_OBJECTID_CHECKPOINT_DATA	0x20
-#define YAFFS_SEQUENCE_CHECKPOINT_DATA  0x21
+/* Fake object Id for summary data */
+#define YAFFS_OBJECTID_SUMMARY		0x10
 
-/* */
+/* Pseudo object ids for checkpointing */
+#define YAFFS_OBJECTID_CHECKPOINT_DATA	0x20
+#define YAFFS_SEQUENCE_CHECKPOINT_DATA	0x21
 
 #define YAFFS_MAX_SHORT_OP_CACHES	20
 
-#define YAFFS_N_TEMP_BUFFERS		4
+#define YAFFS_N_TEMP_BUFFERS		6
 
 /* We limit the number attempts at sucessfully saving a chunk of data.
  * Small-page devices have 32 pages per block; large-page devices have 64.
@@ -102,142 +116,136 @@
  * The range is limited slightly to help distinguish bad numbers from good.
  * This also allows us to perhaps in the future use special numbers for
  * special purposes.
- * EFFFFF00 allows the allocation of 8 blocks per second (~1Mbytes) for 15 years,
+ * EFFFFF00 allows the allocation of 8 blocks/second (~1Mbytes) for 15 years,
  * and is a larger number than the lifetime of a 2GB device.
  */
 #define YAFFS_LOWEST_SEQUENCE_NUMBER	0x00001000
-#define YAFFS_HIGHEST_SEQUENCE_NUMBER	0xEFFFFF00
+#define YAFFS_HIGHEST_SEQUENCE_NUMBER	0xefffff00
+
+/* Special sequence number for bad block that failed to be marked bad */
+#define YAFFS_SEQUENCE_BAD_BLOCK	0xffff0000
 
 /* ChunkCache is used for short read/write operations.*/
-typedef struct {
-	struct yaffs_ObjectStruct *object;
-	int chunkId;
-	int lastUse;
+struct yaffs_cache {
+	struct yaffs_obj *object;
+	int chunk_id;
+	int last_use;
 	int dirty;
-	int nBytes;		/* Only valid if the cache is dirty */
+	int n_bytes;		/* Only valid if the cache is dirty */
 	int locked;		/* Can't push out or flush while locked. */
-#ifdef CONFIG_YAFFS_YAFFS2
-	__u8 *data;
-#else
-	__u8 data[YAFFS_BYTES_PER_CHUNK];
-#endif
-} yaffs_ChunkCache;
-
-
+	u8 *data;
+};
 
-/* Tags structures in RAM
- * NB This uses bitfield. Bitfields should not straddle a u32 boundary otherwise
- * the structure size will get blown out.
+/* yaffs1 tags structures in RAM
+ * NB This uses bitfield. Bitfields should not straddle a u32 boundary
+ * otherwise the structure size will get blown out.
  */
 
-#ifndef CONFIG_YAFFS_NO_YAFFS1
-typedef struct {
-	unsigned chunkId:20;
-	unsigned serialNumber:2;
-	unsigned byteCount:10;
-	unsigned objectId:18;
+struct yaffs_tags {
+	unsigned chunk_id:20;
+	unsigned serial_number:2;
+	unsigned n_bytes_lsb:10;
+	unsigned obj_id:18;
 	unsigned ecc:12;
-	unsigned unusedStuff:2;
-
-} yaffs_Tags;
+	unsigned n_bytes_msb:2;
+};
 
-typedef union {
-	yaffs_Tags asTags;
-	__u8 asBytes[8];
-} yaffs_TagsUnion;
+union yaffs_tags_union {
+	struct yaffs_tags as_tags;
+	u8 as_bytes[8];
+};
 
-#endif
 
 /* Stuff used for extended tags in YAFFS2 */
 
-typedef enum {
+enum yaffs_ecc_result {
 	YAFFS_ECC_RESULT_UNKNOWN,
 	YAFFS_ECC_RESULT_NO_ERROR,
 	YAFFS_ECC_RESULT_FIXED,
 	YAFFS_ECC_RESULT_UNFIXED
-} yaffs_ECCResult;
+};
 
-typedef enum {
+enum yaffs_obj_type {
 	YAFFS_OBJECT_TYPE_UNKNOWN,
 	YAFFS_OBJECT_TYPE_FILE,
 	YAFFS_OBJECT_TYPE_SYMLINK,
 	YAFFS_OBJECT_TYPE_DIRECTORY,
 	YAFFS_OBJECT_TYPE_HARDLINK,
 	YAFFS_OBJECT_TYPE_SPECIAL
-} yaffs_ObjectType;
+};
 
 #define YAFFS_OBJECT_TYPE_MAX YAFFS_OBJECT_TYPE_SPECIAL
 
-typedef struct {
-
-	unsigned validMarker0;
-	unsigned chunkUsed;	/*  Status of the chunk: used or unused */
-	unsigned objectId;	/* If 0 then this is not part of an object (unused) */
-	unsigned chunkId;	/* If 0 then this is a header, else a data chunk */
-	unsigned byteCount;	/* Only valid for data chunks */
+struct yaffs_ext_tags {
+	unsigned chunk_used;	/*  Status of the chunk: used or unused */
+	unsigned obj_id;	/* If 0 this is not used */
+	unsigned chunk_id;	/* If 0 this is a header, else a data chunk */
+	unsigned n_bytes;	/* Only valid for data chunks */
 
 	/* The following stuff only has meaning when we read */
-	yaffs_ECCResult eccResult;
-	unsigned blockBad;
+	enum yaffs_ecc_result ecc_result;
+	unsigned block_bad;
 
 	/* YAFFS 1 stuff */
-	unsigned chunkDeleted;	/* The chunk is marked deleted */
-	unsigned serialNumber;	/* Yaffs1 2-bit serial number */
+	unsigned is_deleted;	/* The chunk is marked deleted */
+	unsigned serial_number;	/* Yaffs1 2-bit serial number */
 
 	/* YAFFS2 stuff */
-	unsigned sequenceNumber;	/* The sequence number of this block */
+	unsigned seq_number;	/* The sequence number of this block */
 
 	/* Extra info if this is an object header (YAFFS2 only) */
 
-	unsigned extraHeaderInfoAvailable;	/* There is extra info available if this is not zero */
-	unsigned extraParentObjectId;	/* The parent object */
-	unsigned extraIsShrinkHeader;	/* Is it a shrink header? */
-	unsigned extraShadows;		/* Does this shadow another object? */
-
-	yaffs_ObjectType extraObjectType;	/* What object type? */
+	unsigned extra_available;	/* Extra info available if not zero */
+	unsigned extra_parent_id;	/* The parent object */
+	unsigned extra_is_shrink;	/* Is it a shrink header? */
+	unsigned extra_shadows;	/* Does this shadow another object? */
 
-	unsigned extraFileLength;		/* Length if it is a file */
-	unsigned extraEquivalentObjectId;	/* Equivalent object Id if it is a hard link */
+	enum yaffs_obj_type extra_obj_type;	/* What object type? */
 
-	unsigned validMarker1;
-
-} yaffs_ExtendedTags;
+	loff_t extra_file_size;		/* Length if it is a file */
+	unsigned extra_equiv_id;	/* Equivalent object for a hard link */
+};
 
 /* Spare structure for YAFFS1 */
-typedef struct {
-	__u8 tagByte0;
-	__u8 tagByte1;
-	__u8 tagByte2;
-	__u8 tagByte3;
-	__u8 pageStatus;	/* set to 0 to delete the chunk */
-	__u8 blockStatus;
-	__u8 tagByte4;
-	__u8 tagByte5;
-	__u8 ecc1[3];
-	__u8 tagByte6;
-	__u8 tagByte7;
-	__u8 ecc2[3];
-} yaffs_Spare;
+struct yaffs_spare {
+	u8 tb0;
+	u8 tb1;
+	u8 tb2;
+	u8 tb3;
+	u8 page_status;		/* set to 0 to delete the chunk */
+	u8 block_status;
+	u8 tb4;
+	u8 tb5;
+	u8 ecc1[3];
+	u8 tb6;
+	u8 tb7;
+	u8 ecc2[3];
+};
 
 /*Special structure for passing through to mtd */
-struct yaffs_NANDSpare {
-	yaffs_Spare spare;
+struct yaffs_nand_spare {
+	struct yaffs_spare spare;
 	int eccres1;
 	int eccres2;
 };
 
 /* Block data in RAM */
 
-typedef enum {
+enum yaffs_block_state {
 	YAFFS_BLOCK_STATE_UNKNOWN = 0,
 
 	YAFFS_BLOCK_STATE_SCANNING,
-	YAFFS_BLOCK_STATE_NEEDS_SCANNING,
-	/* The block might have something on it (ie it is allocating or full, perhaps empty)
-	 * but it needs to be scanned to determine its true state.
-	 * This state is only valid during yaffs_Scan.
-	 * NB We tolerate empty because the pre-scanner might be incapable of deciding
-	 * However, if this state is returned on a YAFFS2 device, then we expect a sequence number
+	/* Being scanned */
+
+	YAFFS_BLOCK_STATE_NEEDS_SCAN,
+	/* The block might have something on it (ie it is allocating or full,
+	 * perhaps empty) but it needs to be scanned to determine its true
+	 * state.
+	 * This state is only valid during scanning.
+	 * NB We tolerate empty because the pre-scanner might be incapable of
+	 * deciding
+	 * However, if this state is returned on a YAFFS2 device,
+	 * then we expect a sequence number
 	 */
 
 	YAFFS_BLOCK_STATE_EMPTY,
@@ -247,123 +255,109 @@ typedef enum {
 	/* This block is partially allocated.
 	 * At least one page holds valid data.
 	 * This is the one currently being used for page
-	 * allocation. Should never be more than one of these
+	 * allocation. Should never be more than one of these.
+	 * If a block is only partially allocated at mount it is treated as
+	 * full.
 	 */
 
 	YAFFS_BLOCK_STATE_FULL,
 	/* All the pages in this block have been allocated.
+	 * If a block was only partially allocated when mounted we treat
+	 * it as fully allocated.
 	 */
 
 	YAFFS_BLOCK_STATE_DIRTY,
-	/* All pages have been allocated and deleted.
+	/* The block was full and now all chunks have been deleted.
 	 * Erase me, reuse me.
 	 */
 
 	YAFFS_BLOCK_STATE_CHECKPOINT,
-	/* This block is assigned to holding checkpoint data.
-	 */
+	/* This block is assigned to holding checkpoint data. */
 
 	YAFFS_BLOCK_STATE_COLLECTING,
 	/* This block is being garbage collected */
 
 	YAFFS_BLOCK_STATE_DEAD
-	/* This block has failed and is not in use */
-} yaffs_BlockState;
+	    /* This block has failed and is not in use */
+};
 
 #define	YAFFS_NUMBER_OF_BLOCK_STATES (YAFFS_BLOCK_STATE_DEAD + 1)
 
+struct yaffs_block_info {
+
+	int soft_del_pages:10;	/* number of soft deleted pages */
+	int pages_in_use:10;	/* number of pages in use */
+	unsigned block_state:4;	/* One of the above block states. */
+				/* NB use unsigned because enum is sometimes
+				 * an int */
+	u32 needs_retiring:1;	/* Data has failed on this block, */
+				/*need to get valid data off and retire*/
+	u32 skip_erased_check:1;/* Skip the erased check on this block */
+	u32 gc_prioritise:1;	/* An ECC check or blank check has failed.
+				   Block should be prioritised for GC */
+	u32 chunk_error_strikes:3;	/* How many times we've had ecc etc
+				failures on this block and tried to reuse it */
+	u32 has_summary:1;	/* The block has a summary */
+
+	u32 has_shrink_hdr:1;	/* This block has at least one shrink header */
+	u32 seq_number;		/* block sequence number for yaffs2 */
 
-typedef struct {
-
-	int softDeletions:10;	/* number of soft deleted pages */
-	int pagesInUse:10;	/* number of pages in use */
-	unsigned blockState:4;	/* One of the above block states. NB use unsigned because enum is sometimes an int */
-	__u32 needsRetiring:1;	/* Data has failed on this block, need to get valid data off */
-				/* and retire the block. */
-	__u32 skipErasedCheck: 1; /* If this is set we can skip the erased check on this block */
-	__u32 gcPrioritise: 1; 	/* An ECC check or blank check has failed on this block.
-				   It should be prioritised for GC */
-	__u32 chunkErrorStrikes:3; /* How many times we've had ecc etc failures on this block and tried to reuse it */
-
-#ifdef CONFIG_YAFFS_YAFFS2
-	__u32 hasShrinkHeader:1; /* This block has at least one shrink object header */
-	__u32 sequenceNumber;	 /* block sequence number for yaffs2 */
-#endif
-
-} yaffs_BlockInfo;
+};
 
 /* -------------------------- Object structure -------------------------------*/
 /* This is the object structure as stored on NAND */
 
-typedef struct {
-	yaffs_ObjectType type;
+struct yaffs_obj_hdr {
+	enum yaffs_obj_type type;
 
 	/* Apply to everything  */
-	int parentObjectId;
-	__u16 sum__NoLongerUsed;	/* checksum of name. No longer used */
+	int parent_obj_id;
+	u16 sum_no_longer_used;	/* checksum of name. No longer used */
 	YCHAR name[YAFFS_MAX_NAME_LENGTH + 1];
 
-	/* Thes following apply to directories, files, symlinks - not hard links */
-	__u32 yst_mode;		/* protection */
+	/* The following apply to all object types except for hard links */
+	u32 yst_mode;		/* protection */
 
-#ifdef CONFIG_YAFFS_WINCE
-	__u32 notForWinCE[5];
-#else
-	__u32 yst_uid;
-	__u32 yst_gid;
-	__u32 yst_atime;
-	__u32 yst_mtime;
-	__u32 yst_ctime;
-#endif
+	u32 yst_uid;
+	u32 yst_gid;
+	u32 yst_atime;
+	u32 yst_mtime;
+	u32 yst_ctime;
 
 	/* File size  applies to files only */
-	int fileSize;
+	u32 file_size_low;
 
 	/* Equivalent object id applies to hard links only. */
-	int equivalentObjectId;
+	int equiv_id;
 
 	/* Alias is for symlinks only. */
 	YCHAR alias[YAFFS_MAX_ALIAS_LENGTH + 1];
 
-	__u32 yst_rdev;		/* device stuff for block and char devices (major/min) */
+	u32 yst_rdev;	/* stuff for block and char devices (major/min) */
 
-#ifdef CONFIG_YAFFS_WINCE
-	__u32 win_ctime[2];
-	__u32 win_atime[2];
-	__u32 win_mtime[2];
-	__u32 roomToGrow[4];
-#else
-	__u32 roomToGrow[10];
-#endif
-
-	int shadowsObject;	/* This object header shadows the specified object if > 0 */
+	u32 win_ctime[2];
+	u32 win_atime[2];
+	u32 win_mtime[2];
 
-	/* isShrink applies to object headers written when we shrink the file (ie resize) */
-	__u32 isShrink;
+	u32 inband_shadowed_obj_id;
+	u32 inband_is_shrink;
 
-} yaffs_ObjectHeader;
+	u32 file_size_high;
+	u32 reserved[1];
+	int shadows_obj;	/* This object header shadows the
+				specified object if > 0 */
 
-/*--------------------------- Tnode -------------------------- */
-
-union yaffs_Tnode_union {
-#ifdef CONFIG_YAFFS_TNODE_LIST_DEBUG
-	union yaffs_Tnode_union *internal[YAFFS_NTNODES_INTERNAL + 1];
-#else
-	union yaffs_Tnode_union *internal[YAFFS_NTNODES_INTERNAL];
-#endif
-/*	__u16 level0[YAFFS_NTNODES_LEVEL0]; */
+	/* is_shrink applies to object headers written when wemake a hole. */
+	u32 is_shrink;
 
 };
 
-typedef union yaffs_Tnode_union yaffs_Tnode;
+/*--------------------------- Tnode -------------------------- */
 
-struct yaffs_TnodeList_struct {
-	struct yaffs_TnodeList_struct *next;
-	yaffs_Tnode *tnodes;
+struct yaffs_tnode {
+	struct yaffs_tnode *internal[YAFFS_NTNODES_INTERNAL];
 };
 
-typedef struct yaffs_TnodeList_struct yaffs_TnodeList;
-
 /*------------------------  Object -----------------------------*/
 /* An object can be one of:
  * - a directory (no data, has children links
@@ -372,537 +366,608 @@ typedef struct yaffs_TnodeList_struct yaffs_TnodeList;
  * - a hard link
  */
 
-typedef struct {
-	__u32 fileSize;
-	__u32 scannedFileSize;
-	__u32 shrinkSize;
-	int topLevel;
-	yaffs_Tnode *top;
-} yaffs_FileStructure;
+struct yaffs_file_var {
+	loff_t file_size;
+	loff_t scanned_size;
+	loff_t shrink_size;
+	int top_level;
+	struct yaffs_tnode *top;
+};
 
-typedef struct {
+struct yaffs_dir_var {
 	struct list_head children;	/* list of child links */
-} yaffs_DirectoryStructure;
+	struct list_head dirty;	/* Entry for list of dirty directories */
+};
 
-typedef struct {
+struct yaffs_symlink_var {
 	YCHAR *alias;
-} yaffs_SymLinkStructure;
-
-typedef struct {
-	struct yaffs_ObjectStruct *equivalentObject;
-	__u32 equivalentObjectId;
-} yaffs_HardLinkStructure;
-
-typedef union {
-	yaffs_FileStructure fileVariant;
-	yaffs_DirectoryStructure directoryVariant;
-	yaffs_SymLinkStructure symLinkVariant;
-	yaffs_HardLinkStructure hardLinkVariant;
-} yaffs_ObjectVariant;
-
-struct yaffs_ObjectStruct {
-	__u8 deleted:1;		/* This should only apply to unlinked files. */
-	__u8 softDeleted:1;	/* it has also been soft deleted */
-	__u8 unlinked:1;	/* An unlinked file. The file should be in the unlinked directory.*/
-	__u8 fake:1;		/* A fake object has no presence on NAND. */
-	__u8 renameAllowed:1;	/* Some objects are not allowed to be renamed. */
-	__u8 unlinkAllowed:1;
-	__u8 dirty:1;		/* the object needs to be written to flash */
-	__u8 valid:1;		/* When the file system is being loaded up, this
+};
+
+struct yaffs_hardlink_var {
+	struct yaffs_obj *equiv_obj;
+	u32 equiv_id;
+};
+
+union yaffs_obj_var {
+	struct yaffs_file_var file_variant;
+	struct yaffs_dir_var dir_variant;
+	struct yaffs_symlink_var symlink_variant;
+	struct yaffs_hardlink_var hardlink_variant;
+};
+
+struct yaffs_obj {
+	u8 deleted:1;		/* This should only apply to unlinked files. */
+	u8 soft_del:1;		/* it has also been soft deleted */
+	u8 unlinked:1;		/* An unlinked file.*/
+	u8 fake:1;		/* A fake object has no presence on NAND. */
+	u8 rename_allowed:1;	/* Some objects cannot be renamed. */
+	u8 unlink_allowed:1;
+	u8 dirty:1;		/* the object needs to be written to flash */
+	u8 valid:1;		/* When the file system is being loaded up, this
 				 * object might be created before the data
-				 * is available (ie. file data records appear before the header).
+				 * is available
+				 * ie. file data chunks encountered before
+				* the header.
 				 */
-	__u8 lazyLoaded:1;	/* This object has been lazy loaded and is missing some detail */
+	u8 lazy_loaded:1;	/* This object has been lazy loaded and
+				 * is missing some detail */
 
-	__u8 deferedFree:1;	/* For Linux kernel. Object is removed from NAND, but is
-				 * still in the inode cache. Free of object is defered.
+	u8 defered_free:1;	/* Object is removed from NAND, but is
+				 * still in the inode cache.
+				 * Free of object is defered.
 				 * until the inode is released.
 				 */
+	u8 being_created:1;	/* This object is still being created
+				 * so skip some verification checks. */
+	u8 is_shadowed:1;	/* This object is shadowed on the way
+				 * to being renamed. */
 
-	__u8 serial;		/* serial number of chunk in NAND. Cached here */
-	__u16 sum;		/* sum of the name to speed searching */
+	u8 xattr_known:1;	/* We know if this has object has xattribs
+				 * or not. */
+	u8 has_xattr:1;		/* This object has xattribs.
+				 * Only valid if xattr_known. */
 
-	struct yaffs_DeviceStruct *myDev;	/* The device I'm on */
+	u8 serial;		/* serial number of chunk in NAND.*/
+	u16 sum;		/* sum of the name to speed searching */
 
-	struct list_head hashLink;	/* list of objects in this hash bucket */
+	struct yaffs_dev *my_dev;	/* The device I'm on */
 
-	struct list_head hardLinks;	/* all the equivalent hard linked objects */
+	struct list_head hash_link;	/* list of objects in hash bucket */
+
+	struct list_head hard_links;	/* hard linked object chain*/
 
 	/* directory structure stuff */
 	/* also used for linking up the free list */
-	struct yaffs_ObjectStruct *parent;
+	struct yaffs_obj *parent;
 	struct list_head siblings;
 
 	/* Where's my object header in NAND? */
-	int chunkId;
+	int hdr_chunk;
 
-	int nDataChunks;	/* Number of data chunks attached to the file. */
+	int n_data_chunks;	/* Number of data chunks for this file. */
 
-	__u32 objectId;		/* the object id value */
+	u32 obj_id;		/* the object id value */
 
-	__u32 yst_mode;
+	u32 yst_mode;
 
-#ifdef CONFIG_YAFFS_SHORT_NAMES_IN_RAM
-	YCHAR shortName[YAFFS_SHORT_NAME_LENGTH + 1];
-#endif
-
-/* XXX U-BOOT XXX */
-/* #ifndef __KERNEL__ */
-	__u32 inUse;
-/* #endif */
+	YCHAR short_name[YAFFS_SHORT_NAME_LENGTH + 1];
 
 #ifdef CONFIG_YAFFS_WINCE
-	__u32 win_ctime[2];
-	__u32 win_mtime[2];
-	__u32 win_atime[2];
+	u32 win_ctime[2];
+	u32 win_mtime[2];
+	u32 win_atime[2];
 #else
-	__u32 yst_uid;
-	__u32 yst_gid;
-	__u32 yst_atime;
-	__u32 yst_mtime;
-	__u32 yst_ctime;
+	u32 yst_uid;
+	u32 yst_gid;
+	u32 yst_atime;
+	u32 yst_mtime;
+	u32 yst_ctime;
 #endif
 
-	__u32 yst_rdev;
+	u32 yst_rdev;
 
-/* XXX U-BOOT XXX */
-/* #ifndef __KERNEL__ */
-	struct inode *myInode;
-/* #endif */
+	void *my_inode;
 
-	yaffs_ObjectType variantType;
+	enum yaffs_obj_type variant_type;
 
-	yaffs_ObjectVariant variant;
+	union yaffs_obj_var variant;
 
 };
 
-typedef struct yaffs_ObjectStruct yaffs_Object;
-
-struct yaffs_ObjectList_struct {
-	yaffs_Object *objects;
-	struct yaffs_ObjectList_struct *next;
-};
-
-typedef struct yaffs_ObjectList_struct yaffs_ObjectList;
-
-typedef struct {
+struct yaffs_obj_bucket {
 	struct list_head list;
 	int count;
-} yaffs_ObjectBucket;
-
+};
 
-/* yaffs_CheckpointObject holds the definition of an object as dumped
+/* yaffs_checkpt_obj holds the definition of an object as dumped
  * by checkpointing.
  */
 
-typedef struct {
-	int structType;
-	__u32 objectId;
-	__u32 parentId;
-	int chunkId;
-
-	yaffs_ObjectType variantType:3;
-	__u8 deleted:1;
-	__u8 softDeleted:1;
-	__u8 unlinked:1;
-	__u8 fake:1;
-	__u8 renameAllowed:1;
-	__u8 unlinkAllowed:1;
-	__u8 serial;
-
-	int nDataChunks;
-	__u32 fileSizeOrEquivalentObjectId;
-
-}yaffs_CheckpointObject;
+struct yaffs_checkpt_obj {
+	int struct_type;
+	u32 obj_id;
+	u32 parent_id;
+	int hdr_chunk;
+	enum yaffs_obj_type variant_type:3;
+	u8 deleted:1;
+	u8 soft_del:1;
+	u8 unlinked:1;
+	u8 fake:1;
+	u8 rename_allowed:1;
+	u8 unlink_allowed:1;
+	u8 serial;
+	int n_data_chunks;
+	loff_t size_or_equiv_obj;
+};
 
 /*--------------------- Temporary buffers ----------------
  *
- * These are chunk-sized working buffers. Each device has a few
+ * These are chunk-sized working buffers. Each device has a few.
  */
 
-typedef struct {
-	__u8 *buffer;
-	int line;	/* track from whence this buffer was allocated */
-	int maxLine;
-} yaffs_TempBuffer;
+struct yaffs_buffer {
+	u8 *buffer;
+	int in_use;
+};
 
 /*----------------- Device ---------------------------------*/
 
-struct yaffs_DeviceStruct {
-	struct list_head devList;
-	const char *name;
-
-	/* Entry parameters set up way early. Yaffs sets up the rest.*/
-	int nDataBytesPerChunk;	/* Should be a power of 2 >= 512 */
-	int nChunksPerBlock;	/* does not need to be a power of 2 */
-	int nBytesPerSpare;	/* spare area size */
-	int startBlock;		/* Start block we're allowed to use */
-	int endBlock;		/* End block we're allowed to use */
-	int nReservedBlocks;	/* We want this tuneable so that we can reduce */
-				/* reserved blocks on NOR and RAM. */
-
-
-	/* Stuff used by the shared space checkpointing mechanism */
-	/* If this value is zero, then this mechanism is disabled */
-
-	int nCheckpointReservedBlocks; /* Blocks to reserve for checkpoint data */
-
-
+struct yaffs_param {
+	const YCHAR *name;
 
+	/*
+	 * Entry parameters set up way early. Yaffs sets up the rest.
+	 * The structure should be zeroed out before use so that unused
+	 * and defualt values are zero.
+	 */
 
-	int nShortOpCaches;	/* If <= 0, then short op caching is disabled, else
-				 * the number of short op caches (don't use too many)
+	int inband_tags;	/* Use unband tags */
+	u32 total_bytes_per_chunk;	/* Should be >= 512, does not need to
+					 be a power of 2 */
+	int chunks_per_block;	/* does not need to be a power of 2 */
+	int spare_bytes_per_chunk;	/* spare area size */
+	int start_block;	/* Start block we're allowed to use */
+	int end_block;		/* End block we're allowed to use */
+	int n_reserved_blocks;	/* Tuneable so that we can reduce
+				 * reserved blocks on NOR and RAM. */
+
+	int n_caches;		/* If <= 0, then short op caching is disabled,
+				 * else the number of short op caches.
 				 */
+	int use_nand_ecc;	/* Flag to decide whether or not to use
+				 * NAND driver ECC on data (yaffs1) */
+	int tags_9bytes;	/* Use 9 byte tags */
+	int no_tags_ecc;	/* Flag to decide whether or not to do ECC
+				 * on packed tags (yaffs2) */
 
-	int useHeaderFileSize;	/* Flag to determine if we should use file sizes from the header */
-
-	int useNANDECC;		/* Flag to decide whether or not to use NANDECC */
+	int is_yaffs2;		/* Use yaffs2 mode on this device */
 
-	void *genericDevice;	/* Pointer to device context
-				 * On an mtd this holds the mtd pointer.
-				 */
-	void *superBlock;
-
-	/* NAND access functions (Must be set before calling YAFFS)*/
-
-	int (*writeChunkToNAND) (struct yaffs_DeviceStruct * dev,
-				 int chunkInNAND, const __u8 * data,
-				 const yaffs_Spare * spare);
-	int (*readChunkFromNAND) (struct yaffs_DeviceStruct * dev,
-				  int chunkInNAND, __u8 * data,
-				  yaffs_Spare * spare);
-	int (*eraseBlockInNAND) (struct yaffs_DeviceStruct * dev,
-				 int blockInNAND);
-	int (*initialiseNAND) (struct yaffs_DeviceStruct * dev);
-
-#ifdef CONFIG_YAFFS_YAFFS2
-	int (*writeChunkWithTagsToNAND) (struct yaffs_DeviceStruct * dev,
-					 int chunkInNAND, const __u8 * data,
-					 const yaffs_ExtendedTags * tags);
-	int (*readChunkWithTagsFromNAND) (struct yaffs_DeviceStruct * dev,
-					  int chunkInNAND, __u8 * data,
-					  yaffs_ExtendedTags * tags);
-	int (*markNANDBlockBad) (struct yaffs_DeviceStruct * dev, int blockNo);
-	int (*queryNANDBlock) (struct yaffs_DeviceStruct * dev, int blockNo,
-			       yaffs_BlockState * state, int *sequenceNumber);
-#endif
+	int empty_lost_n_found;	/* Auto-empty lost+found directory on mount */
 
-	int isYaffs2;
+	int refresh_period;	/* How often to check for a block refresh */
 
-	/* The removeObjectCallback function must be supplied by OS flavours that
-	 * need it. The Linux kernel does not use this, but yaffs direct does use
-	 * it to implement the faster readdir
+	/* Checkpoint control. Can be set before or after initialisation */
+	u8 skip_checkpt_rd;
+	u8 skip_checkpt_wr;
+
+	int enable_xattr;	/* Enable xattribs */
+
+	/* NAND access functions (Must be set before calling YAFFS) */
+
+	int (*write_chunk_fn) (struct yaffs_dev *dev,
+			       int nand_chunk, const u8 *data,
+			       const struct yaffs_spare *spare);
+	int (*read_chunk_fn) (struct yaffs_dev *dev,
+			      int nand_chunk, u8 *data,
+			      struct yaffs_spare *spare);
+	int (*erase_fn) (struct yaffs_dev *dev, int flash_block);
+	int (*initialise_flash_fn) (struct yaffs_dev *dev);
+	int (*deinitialise_flash_fn) (struct yaffs_dev *dev);
+
+	/* yaffs2 mode functions */
+	int (*write_chunk_tags_fn) (struct yaffs_dev *dev,
+				    int nand_chunk, const u8 *data,
+				    const struct yaffs_ext_tags *tags);
+	int (*read_chunk_tags_fn) (struct yaffs_dev *dev,
+				   int nand_chunk, u8 *data,
+				   struct yaffs_ext_tags *tags);
+	int (*bad_block_fn) (struct yaffs_dev *dev, int block_no);
+	int (*query_block_fn) (struct yaffs_dev *dev, int block_no,
+			       enum yaffs_block_state *state,
+			       u32 *seq_number);
+
+	/* The remove_obj_fn function must be supplied by OS flavours that
+	 * need it.
+	 * yaffs direct uses it to implement the faster readdir.
+	 * Linux uses it to protect the directory during unlocking.
 	 */
-	void (*removeObjectCallback)(struct yaffs_ObjectStruct *obj);
+	void (*remove_obj_fn) (struct yaffs_obj *obj);
 
-	/* Callback to mark the superblock dirsty */
-	void (*markSuperBlockDirty)(void * superblock);
+	/* Callback to mark the superblock dirty */
+	void (*sb_dirty_fn) (struct yaffs_dev *dev);
 
-	int wideTnodesDisabled; /* Set to disable wide tnodes */
+	/*  Callback to control garbage collection. */
+	unsigned (*gc_control) (struct yaffs_dev *dev);
 
+	/* Debug control flags. Don't use unless you know what you're doing */
+	int use_header_file_size;	/* Flag to determine if we should use
+					 * file sizes from the header */
+	int disable_lazy_load;	/* Disable lazy loading on this device */
+	int wide_tnodes_disabled;	/* Set to disable wide tnodes */
+	int disable_soft_del;	/* yaffs 1 only: Set to disable the use of
+				 * softdeletion. */
 
-	/* End of stuff that must be set before initialisation. */
+	int defered_dir_update;	/* Set to defer directory updates */
 
-	/* Checkpoint control. Can be set before or after initialisation */
-	__u8 skipCheckpointRead;
-	__u8 skipCheckpointWrite;
+#ifdef CONFIG_YAFFS_AUTO_UNICODE
+	int auto_unicode;
+#endif
+	int always_check_erased;	/* Force chunk erased check always on */
 
-	/* Runtime parameters. Set up by YAFFS. */
+	int disable_summary;
 
-	__u16 chunkGroupBits;	/* 0 for devices <= 32MB. else log2(nchunks) - 16 */
-	__u16 chunkGroupSize;	/* == 2^^chunkGroupBits */
+	int max_objects;	/*
+				 * Set to limit the number of objects created.
+				 * 0 = no limit.
+				*/
+};
 
-	/* Stuff to support wide tnodes */
-	__u32 tnodeWidth;
-	__u32 tnodeMask;
+struct yaffs_dev {
+	struct yaffs_param param;
 
-	/* Stuff to support various file offses to chunk/offset translations */
-	/* "Crumbs" for nDataBytesPerChunk not being a power of 2 */
-	__u32 crumbMask;
-	__u32 crumbShift;
-	__u32 crumbsPerChunk;
+	/* Context storage. Holds extra OS specific data for this device */
 
-	/* Straight shifting for nDataBytesPerChunk being a power of 2 */
-	__u32 chunkShift;
-	__u32 chunkMask;
+	void *os_context;
+	void *driver_context;
 
+	struct list_head dev_list;
 
-/* XXX U-BOOT XXX */
-#if 0
-#ifndef __KERNEL__
+	/* Runtime parameters. Set up by YAFFS. */
+	int data_bytes_per_chunk;
 
-	struct semaphore sem;	/* Semaphore for waiting on erasure.*/
-	struct semaphore grossLock;	/* Gross locking semaphore */
-	void (*putSuperFunc) (struct super_block * sb);
-#endif
-#endif
-	__u8 *spareBuffer;	/* For mtdif2 use. Don't know the size of the buffer
-				 * at compile time so we have to allocate it.
+	/* Non-wide tnode stuff */
+	u16 chunk_grp_bits;	/* Number of bits that need to be resolved if
+				 * the tnodes are not wide enough.
 				 */
+	u16 chunk_grp_size;	/* == 2^^chunk_grp_bits */
 
-	int isMounted;
+	/* Stuff to support wide tnodes */
+	u32 tnode_width;
+	u32 tnode_mask;
+	u32 tnode_size;
 
-	int isCheckpointed;
+	/* Stuff for figuring out file offset to chunk conversions */
+	u32 chunk_shift;	/* Shift value */
+	u32 chunk_div;		/* Divisor after shifting: 1 for 2^n sizes */
+	u32 chunk_mask;		/* Mask to use for power-of-2 case */
 
+	int is_mounted;
+	int read_only;
+	int is_checkpointed;
 
 	/* Stuff to support block offsetting to support start block zero */
-	int internalStartBlock;
-	int internalEndBlock;
-	int blockOffset;
-	int chunkOffset;
-
+	int internal_start_block;
+	int internal_end_block;
+	int block_offset;
+	int chunk_offset;
 
 	/* Runtime checkpointing stuff */
-	int checkpointPageSequence;   /* running sequence number of checkpoint pages */
-	int checkpointByteCount;
-	int checkpointByteOffset;
-	__u8 *checkpointBuffer;
-	int checkpointOpenForWrite;
-	int blocksInCheckpoint;
-	int checkpointCurrentChunk;
-	int checkpointCurrentBlock;
-	int checkpointNextBlock;
-	int *checkpointBlockList;
-	int checkpointMaxBlocks;
-	__u32 checkpointSum;
-	__u32 checkpointXor;
+	int checkpt_page_seq;	/* running sequence number of checkpt pages */
+	int checkpt_byte_count;
+	int checkpt_byte_offs;
+	u8 *checkpt_buffer;
+	int checkpt_open_write;
+	int blocks_in_checkpt;
+	int checkpt_cur_chunk;
+	int checkpt_cur_block;
+	int checkpt_next_block;
+	int *checkpt_block_list;
+	int checkpt_max_blocks;
+	u32 checkpt_sum;
+	u32 checkpt_xor;
+
+	int checkpoint_blocks_required;	/* Number of blocks needed to store
+					 * current checkpoint set */
 
 	/* Block Info */
-	yaffs_BlockInfo *blockInfo;
-	__u8 *chunkBits;	/* bitmap of chunks in use */
-	unsigned blockInfoAlt:1;	/* was allocated using alternative strategy */
-	unsigned chunkBitsAlt:1;	/* was allocated using alternative strategy */
-	int chunkBitmapStride;	/* Number of bytes of chunkBits per block.
-				 * Must be consistent with nChunksPerBlock.
+	struct yaffs_block_info *block_info;
+	u8 *chunk_bits;		/* bitmap of chunks in use */
+	unsigned block_info_alt:1;	/* allocated using alternative alloc */
+	unsigned chunk_bits_alt:1;	/* allocated using alternative alloc */
+	int chunk_bit_stride;	/* Number of bytes of chunk_bits per block.
+				 * Must be consistent with chunks_per_block.
 				 */
 
-	int nErasedBlocks;
-	int allocationBlock;	/* Current block being allocated off */
-	__u32 allocationPage;
-	int allocationBlockFinder;	/* Used to search for next allocation block */
-
-	/* Runtime state */
-	int nTnodesCreated;
-	yaffs_Tnode *freeTnodes;
-	int nFreeTnodes;
-	yaffs_TnodeList *allocatedTnodeList;
-
-	int isDoingGC;
-
-	int nObjectsCreated;
-	yaffs_Object *freeObjects;
-	int nFreeObjects;
+	int n_erased_blocks;
+	int alloc_block;	/* Current block being allocated off */
+	u32 alloc_page;
+	int alloc_block_finder;	/* Used to search for next allocation block */
 
-	yaffs_ObjectList *allocatedObjectList;
+	/* Object and Tnode memory management */
+	void *allocator;
+	int n_obj;
+	int n_tnodes;
 
-	yaffs_ObjectBucket objectBucket[YAFFS_NOBJECT_BUCKETS];
+	int n_hardlinks;
 
-	int nFreeChunks;
+	struct yaffs_obj_bucket obj_bucket[YAFFS_NOBJECT_BUCKETS];
+	u32 bucket_finder;
 
-	int currentDirtyChecker;	/* Used to find current dirtiest block */
+	int n_free_chunks;
 
-	__u32 *gcCleanupList;	/* objects to delete at the end of a GC. */
-	int nonAggressiveSkip;	/* GC state/mode */
+	/* Garbage collection control */
+	u32 *gc_cleanup_list;	/* objects to delete at the end of a GC. */
+	u32 n_clean_ups;
 
-	/* Statistcs */
-	int nPageWrites;
-	int nPageReads;
-	int nBlockErasures;
-	int nErasureFailures;
-	int nGCCopies;
-	int garbageCollections;
-	int passiveGarbageCollections;
-	int nRetriedWrites;
-	int nRetiredBlocks;
-	int eccFixed;
-	int eccUnfixed;
-	int tagsEccFixed;
-	int tagsEccUnfixed;
-	int nDeletions;
-	int nUnmarkedDeletions;
-
-	int hasPendingPrioritisedGCs; /* We think this device might have pending prioritised gcs */
+	unsigned has_pending_prioritised_gc;	/* We think this device might
+						have pending prioritised gcs */
+	unsigned gc_disable;
+	unsigned gc_block_finder;
+	unsigned gc_dirtiest;
+	unsigned gc_pages_in_use;
+	unsigned gc_not_done;
+	unsigned gc_block;
+	unsigned gc_chunk;
+	unsigned gc_skip;
+	struct yaffs_summary_tags *gc_sum_tags;
 
 	/* Special directories */
-	yaffs_Object *rootDir;
-	yaffs_Object *lostNFoundDir;
-
-	/* Buffer areas for storing data to recover from write failures TODO
-	 *      __u8            bufferedData[YAFFS_CHUNKS_PER_BLOCK][YAFFS_BYTES_PER_CHUNK];
-	 *      yaffs_Spare bufferedSpare[YAFFS_CHUNKS_PER_BLOCK];
-	 */
-
-	int bufferedBlock;	/* Which block is buffered here? */
-	int doingBufferedBlockRewrite;
+	struct yaffs_obj *root_dir;
+	struct yaffs_obj *lost_n_found;
+
+	int buffered_block;	/* Which block is buffered here? */
+	int doing_buffered_block_rewrite;
+
+	struct yaffs_cache *cache;
+	int cache_last_use;
+
+	/* Stuff for background deletion and unlinked files. */
+	struct yaffs_obj *unlinked_dir;	/* Directory where unlinked and deleted
+					 files live. */
+	struct yaffs_obj *del_dir;	/* Directory where deleted objects are
+					sent to disappear. */
+	struct yaffs_obj *unlinked_deletion;	/* Current file being
+							background deleted. */
+	int n_deleted_files;	/* Count of files awaiting deletion; */
+	int n_unlinked_files;	/* Count of unlinked files. */
+	int n_bg_deletions;	/* Count of background deletions. */
+
+	/* Temporary buffer management */
+	struct yaffs_buffer temp_buffer[YAFFS_N_TEMP_BUFFERS];
+	int max_temp;
+	int temp_in_use;
+	int unmanaged_buffer_allocs;
+	int unmanaged_buffer_deallocs;
 
-	yaffs_ChunkCache *srCache;
-	int srLastUse;
-
-	int cacheHits;
+	/* yaffs2 runtime stuff */
+	unsigned seq_number;	/* Sequence number of currently
+					allocating block */
+	unsigned oldest_dirty_seq;
+	unsigned oldest_dirty_block;
+
+	/* Block refreshing */
+	int refresh_skip;	/* A skip down counter.
+				 * Refresh happens when this gets to zero. */
+
+	/* Dirty directory handling */
+	struct list_head dirty_dirs;	/* List of dirty directories */
+
+	/* Summary */
+	int chunks_per_summary;
+	struct yaffs_summary_tags *sum_tags;
+
+	/* Statistics */
+	u32 n_page_writes;
+	u32 n_page_reads;
+	u32 n_erasures;
+	u32 n_erase_failures;
+	u32 n_gc_copies;
+	u32 all_gcs;
+	u32 passive_gc_count;
+	u32 oldest_dirty_gc_count;
+	u32 n_gc_blocks;
+	u32 bg_gcs;
+	u32 n_retried_writes;
+	u32 n_retired_blocks;
+	u32 n_ecc_fixed;
+	u32 n_ecc_unfixed;
+	u32 n_tags_ecc_fixed;
+	u32 n_tags_ecc_unfixed;
+	u32 n_deletions;
+	u32 n_unmarked_deletions;
+	u32 refresh_count;
+	u32 cache_hits;
+	u32 tags_used;
+	u32 summary_used;
 
-	/* Stuff for background deletion and unlinked files.*/
-	yaffs_Object *unlinkedDir;	/* Directory where unlinked and deleted files live. */
-	yaffs_Object *deletedDir;	/* Directory where deleted objects are sent to disappear. */
-	yaffs_Object *unlinkedDeletion;	/* Current file being background deleted.*/
-	int nDeletedFiles;		/* Count of files awaiting deletion;*/
-	int nUnlinkedFiles;		/* Count of unlinked files. */
-	int nBackgroundDeletions;	/* Count of background deletions. */
+};
 
+/* The CheckpointDevice structure holds the device information that changes
+ *at runtime and must be preserved over unmount/mount cycles.
+ */
+struct yaffs_checkpt_dev {
+	int struct_type;
+	int n_erased_blocks;
+	int alloc_block;	/* Current block being allocated off */
+	u32 alloc_page;
+	int n_free_chunks;
 
-	yaffs_TempBuffer tempBuffer[YAFFS_N_TEMP_BUFFERS];
-	int maxTemp;
-	int unmanagedTempAllocations;
-	int unmanagedTempDeallocations;
+	int n_deleted_files;	/* Count of files awaiting deletion; */
+	int n_unlinked_files;	/* Count of unlinked files. */
+	int n_bg_deletions;	/* Count of background deletions. */
 
 	/* yaffs2 runtime stuff */
-	unsigned sequenceNumber;	/* Sequence number of currently allocating block */
-	unsigned oldestDirtySequence;
+	unsigned seq_number;	/* Sequence number of currently
+				 * allocating block */
 
 };
 
-typedef struct yaffs_DeviceStruct yaffs_Device;
-
-/* The static layout of bllock usage etc is stored in the super block header */
-typedef struct {
-	int StructType;
-	int version;
-	int checkpointStartBlock;
-	int checkpointEndBlock;
-	int startBlock;
-	int endBlock;
-	int rfu[100];
-} yaffs_SuperBlockHeader;
-
-/* The CheckpointDevice structure holds the device information that changes at runtime and
- * must be preserved over unmount/mount cycles.
- */
-typedef struct {
-	int structType;
-	int nErasedBlocks;
-	int allocationBlock;	/* Current block being allocated off */
-	__u32 allocationPage;
-	int nFreeChunks;
+struct yaffs_checkpt_validity {
+	int struct_type;
+	u32 magic;
+	u32 version;
+	u32 head;
+};
 
-	int nDeletedFiles;		/* Count of files awaiting deletion;*/
-	int nUnlinkedFiles;		/* Count of unlinked files. */
-	int nBackgroundDeletions;	/* Count of background deletions. */
+struct yaffs_shadow_fixer {
+	int obj_id;
+	int shadowed_id;
+	struct yaffs_shadow_fixer *next;
+};
 
-	/* yaffs2 runtime stuff */
-	unsigned sequenceNumber;	/* Sequence number of currently allocating block */
-	unsigned oldestDirtySequence;
-
-} yaffs_CheckpointDevice;
-
-
-typedef struct {
-    int structType;
-    __u32 magic;
-    __u32 version;
-    __u32 head;
-} yaffs_CheckpointValidity;
-
-/* Function to manipulate block info */
-static Y_INLINE yaffs_BlockInfo *yaffs_GetBlockInfo(yaffs_Device * dev, int blk)
-{
-	if (blk < dev->internalStartBlock || blk > dev->internalEndBlock) {
-		T(YAFFS_TRACE_ERROR,
-		  (TSTR
-		   ("**>> yaffs: getBlockInfo block %d is not valid" TENDSTR),
-		   blk));
-		YBUG();
-	}
-	return &dev->blockInfo[blk - dev->internalStartBlock];
-}
+/* Structure for doing xattr modifications */
+struct yaffs_xattr_mod {
+	int set;		/* If 0 then this is a deletion */
+	const YCHAR *name;
+	const void *data;
+	int size;
+	int flags;
+	int result;
+};
 
 /*----------------------- YAFFS Functions -----------------------*/
 
-int yaffs_GutsInitialise(yaffs_Device * dev);
-void yaffs_Deinitialise(yaffs_Device * dev);
+int yaffs_guts_initialise(struct yaffs_dev *dev);
+void yaffs_deinitialise(struct yaffs_dev *dev);
 
-int yaffs_GetNumberOfFreeChunks(yaffs_Device * dev);
+int yaffs_get_n_free_chunks(struct yaffs_dev *dev);
 
-int yaffs_RenameObject(yaffs_Object * oldDir, const YCHAR * oldName,
-		       yaffs_Object * newDir, const YCHAR * newName);
+int yaffs_rename_obj(struct yaffs_obj *old_dir, const YCHAR * old_name,
+		     struct yaffs_obj *new_dir, const YCHAR * new_name);
 
-int yaffs_Unlink(yaffs_Object * dir, const YCHAR * name);
-int yaffs_DeleteFile(yaffs_Object * obj);
+int yaffs_unlinker(struct yaffs_obj *dir, const YCHAR * name);
+int yaffs_del_obj(struct yaffs_obj *obj);
 
-int yaffs_GetObjectName(yaffs_Object * obj, YCHAR * name, int buffSize);
-int yaffs_GetObjectFileLength(yaffs_Object * obj);
-int yaffs_GetObjectInode(yaffs_Object * obj);
-unsigned yaffs_GetObjectType(yaffs_Object * obj);
-int yaffs_GetObjectLinkCount(yaffs_Object * obj);
-
-int yaffs_SetAttributes(yaffs_Object * obj, struct iattr *attr);
-int yaffs_GetAttributes(yaffs_Object * obj, struct iattr *attr);
+int yaffs_get_obj_name(struct yaffs_obj *obj, YCHAR * name, int buffer_size);
+loff_t yaffs_get_obj_length(struct yaffs_obj *obj);
+int yaffs_get_obj_inode(struct yaffs_obj *obj);
+unsigned yaffs_get_obj_type(struct yaffs_obj *obj);
+int yaffs_get_obj_link_count(struct yaffs_obj *obj);
 
 /* File operations */
-int yaffs_ReadDataFromFile(yaffs_Object * obj, __u8 * buffer, loff_t offset,
-			   int nBytes);
-int yaffs_WriteDataToFile(yaffs_Object * obj, const __u8 * buffer, loff_t offset,
-			  int nBytes, int writeThrough);
-int yaffs_ResizeFile(yaffs_Object * obj, loff_t newSize);
+int yaffs_file_rd(struct yaffs_obj *obj, u8 * buffer, loff_t offset,
+		  int n_bytes);
+int yaffs_wr_file(struct yaffs_obj *obj, const u8 * buffer, loff_t offset,
+		  int n_bytes, int write_trhrough);
+int yaffs_resize_file(struct yaffs_obj *obj, loff_t new_size);
+
+struct yaffs_obj *yaffs_create_file(struct yaffs_obj *parent,
+				    const YCHAR *name, u32 mode, u32 uid,
+				    u32 gid);
 
-yaffs_Object *yaffs_MknodFile(yaffs_Object * parent, const YCHAR * name,
-			      __u32 mode, __u32 uid, __u32 gid);
-int yaffs_FlushFile(yaffs_Object * obj, int updateTime);
+int yaffs_flush_file(struct yaffs_obj *obj, int update_time, int data_sync);
 
 /* Flushing and checkpointing */
-void yaffs_FlushEntireDeviceCache(yaffs_Device *dev);
+void yaffs_flush_whole_cache(struct yaffs_dev *dev);
 
-int yaffs_CheckpointSave(yaffs_Device *dev);
-int yaffs_CheckpointRestore(yaffs_Device *dev);
+int yaffs_checkpoint_save(struct yaffs_dev *dev);
+int yaffs_checkpoint_restore(struct yaffs_dev *dev);
 
 /* Directory operations */
-yaffs_Object *yaffs_MknodDirectory(yaffs_Object * parent, const YCHAR * name,
-				   __u32 mode, __u32 uid, __u32 gid);
-yaffs_Object *yaffs_FindObjectByName(yaffs_Object * theDir, const YCHAR * name);
-int yaffs_ApplyToDirectoryChildren(yaffs_Object * theDir,
-				   int (*fn) (yaffs_Object *));
-
-yaffs_Object *yaffs_FindObjectByNumber(yaffs_Device * dev, __u32 number);
+struct yaffs_obj *yaffs_create_dir(struct yaffs_obj *parent, const YCHAR *name,
+				   u32 mode, u32 uid, u32 gid);
+struct yaffs_obj *yaffs_find_by_name(struct yaffs_obj *the_dir,
+				     const YCHAR *name);
+struct yaffs_obj *yaffs_find_by_number(struct yaffs_dev *dev, u32 number);
 
 /* Link operations */
-yaffs_Object *yaffs_Link(yaffs_Object * parent, const YCHAR * name,
-			 yaffs_Object * equivalentObject);
+struct yaffs_obj *yaffs_link_obj(struct yaffs_obj *parent, const YCHAR *name,
+				 struct yaffs_obj *equiv_obj);
 
-yaffs_Object *yaffs_GetEquivalentObject(yaffs_Object * obj);
+struct yaffs_obj *yaffs_get_equivalent_obj(struct yaffs_obj *obj);
 
 /* Symlink operations */
-yaffs_Object *yaffs_MknodSymLink(yaffs_Object * parent, const YCHAR * name,
-				 __u32 mode, __u32 uid, __u32 gid,
-				 const YCHAR * alias);
-YCHAR *yaffs_GetSymlinkAlias(yaffs_Object * obj);
+struct yaffs_obj *yaffs_create_symlink(struct yaffs_obj *parent,
+				       const YCHAR *name, u32 mode, u32 uid,
+				       u32 gid, const YCHAR *alias);
+YCHAR *yaffs_get_symlink_alias(struct yaffs_obj *obj);
 
 /* Special inodes (fifos, sockets and devices) */
-yaffs_Object *yaffs_MknodSpecial(yaffs_Object * parent, const YCHAR * name,
-				 __u32 mode, __u32 uid, __u32 gid, __u32 rdev);
+struct yaffs_obj *yaffs_create_special(struct yaffs_obj *parent,
+				       const YCHAR *name, u32 mode, u32 uid,
+				       u32 gid, u32 rdev);
+
+int yaffs_set_xattrib(struct yaffs_obj *obj, const YCHAR *name,
+		      const void *value, int size, int flags);
+int yaffs_get_xattrib(struct yaffs_obj *obj, const YCHAR *name, void *value,
+		      int size);
+int yaffs_list_xattrib(struct yaffs_obj *obj, char *buffer, int size);
+int yaffs_remove_xattrib(struct yaffs_obj *obj, const YCHAR *name);
 
 /* Special directories */
-yaffs_Object *yaffs_Root(yaffs_Device * dev);
-yaffs_Object *yaffs_LostNFound(yaffs_Device * dev);
+struct yaffs_obj *yaffs_root(struct yaffs_dev *dev);
+struct yaffs_obj *yaffs_lost_n_found(struct yaffs_dev *dev);
 
-#ifdef CONFIG_YAFFS_WINCE
-/* CONFIG_YAFFS_WINCE special stuff */
-void yfsd_WinFileTimeNow(__u32 target[2]);
-#endif
+void yaffs_handle_defered_free(struct yaffs_obj *obj);
 
-/* XXX U-BOOT XXX */
-#if 0
-#ifndef __KERNEL__
-void yaffs_HandleDeferedFree(yaffs_Object * obj);
-#endif
-#endif
+void yaffs_update_dirty_dirs(struct yaffs_dev *dev);
 
-/* Debug dump  */
-int yaffs_DumpObject(yaffs_Object * obj);
+int yaffs_bg_gc(struct yaffs_dev *dev, unsigned urgency);
 
-void yaffs_GutsTest(yaffs_Device * dev);
+/* Debug dump  */
+int yaffs_dump_obj(struct yaffs_obj *obj);
+
+void yaffs_guts_test(struct yaffs_dev *dev);
+
+/* A few useful functions to be used within the core files*/
+void yaffs_chunk_del(struct yaffs_dev *dev, int chunk_id, int mark_flash,
+		     int lyn);
+int yaffs_check_ff(u8 *buffer, int n_bytes);
+void yaffs_handle_chunk_error(struct yaffs_dev *dev,
+			      struct yaffs_block_info *bi);
+
+u8 *yaffs_get_temp_buffer(struct yaffs_dev *dev);
+void yaffs_release_temp_buffer(struct yaffs_dev *dev, u8 *buffer);
+
+struct yaffs_obj *yaffs_find_or_create_by_number(struct yaffs_dev *dev,
+						 int number,
+						 enum yaffs_obj_type type);
+int yaffs_put_chunk_in_file(struct yaffs_obj *in, int inode_chunk,
+			    int nand_chunk, int in_scan);
+void yaffs_set_obj_name(struct yaffs_obj *obj, const YCHAR *name);
+void yaffs_set_obj_name_from_oh(struct yaffs_obj *obj,
+				const struct yaffs_obj_hdr *oh);
+void yaffs_add_obj_to_dir(struct yaffs_obj *directory, struct yaffs_obj *obj);
+YCHAR *yaffs_clone_str(const YCHAR *str);
+void yaffs_link_fixup(struct yaffs_dev *dev, struct list_head *hard_list);
+void yaffs_block_became_dirty(struct yaffs_dev *dev, int block_no);
+int yaffs_update_oh(struct yaffs_obj *in, const YCHAR *name,
+		    int force, int is_shrink, int shadows,
+		    struct yaffs_xattr_mod *xop);
+void yaffs_handle_shadowed_obj(struct yaffs_dev *dev, int obj_id,
+			       int backward_scanning);
+int yaffs_check_alloc_available(struct yaffs_dev *dev, int n_chunks);
+struct yaffs_tnode *yaffs_get_tnode(struct yaffs_dev *dev);
+struct yaffs_tnode *yaffs_add_find_tnode_0(struct yaffs_dev *dev,
+					   struct yaffs_file_var *file_struct,
+					   u32 chunk_id,
+					   struct yaffs_tnode *passed_tn);
+
+int yaffs_do_file_wr(struct yaffs_obj *in, const u8 *buffer, loff_t offset,
+		     int n_bytes, int write_trhrough);
+void yaffs_resize_file_down(struct yaffs_obj *obj, loff_t new_size);
+void yaffs_skip_rest_of_block(struct yaffs_dev *dev);
+
+int yaffs_count_free_chunks(struct yaffs_dev *dev);
+
+struct yaffs_tnode *yaffs_find_tnode_0(struct yaffs_dev *dev,
+				       struct yaffs_file_var *file_struct,
+				       u32 chunk_id);
+
+u32 yaffs_get_group_base(struct yaffs_dev *dev, struct yaffs_tnode *tn,
+			 unsigned pos);
+
+int yaffs_is_non_empty_dir(struct yaffs_obj *obj);
+
+void yaffs_addr_to_chunk(struct yaffs_dev *dev, loff_t addr,
+				int *chunk_out, u32 *offset_out);
+/*
+ * Marshalling functions to get loff_t file sizes into aand out of
+ * object headers.
+ */
+void yaffs_oh_size_load(struct yaffs_obj_hdr *oh, loff_t fsize);
+loff_t yaffs_oh_to_size(struct yaffs_obj_hdr *oh);
+loff_t yaffs_max_file_size(struct yaffs_dev *dev);
 
-/* A few useful functions */
-void yaffs_InitialiseTags(yaffs_ExtendedTags * tags);
-void yaffs_DeleteChunk(yaffs_Device * dev, int chunkId, int markNAND, int lyn);
-int yaffs_CheckFF(__u8 * buffer, int nBytes);
-void yaffs_HandleChunkError(yaffs_Device *dev, yaffs_BlockInfo *bi);
 
 #endif
diff --git a/fs/yaffs2/yaffs_list.h b/fs/yaffs2/yaffs_list.h
new file mode 100644
index 0000000000..a7afaea27b
--- /dev/null
+++ b/fs/yaffs2/yaffs_list.h
@@ -0,0 +1,126 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2011 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+/*
+ * This file is just holds extra declarations of macros that would normally
+ * be providesd in the Linux kernel. These macros have been written from
+ * scratch but are functionally equivalent to the Linux ones.
+ *
+ */
+
+#ifndef __YAFFS_LIST_H__
+#define __YAFFS_LIST_H__
+
+
+/*
+ * This is a simple doubly linked list implementation that matches the
+ * way the Linux kernel doubly linked list implementation works.
+ */
+
+struct list_head {
+	struct list_head *next; /* next in chain */
+	struct list_head *prev; /* previous in chain */
+};
+
+
+/* Initialise a static list */
+#define LIST_HEAD(name) \
+struct list_head name = { &(name), &(name)}
+
+
+
+/* Initialise a list head to an empty list */
+#define INIT_LIST_HEAD(p) \
+do { \
+	(p)->next = (p);\
+	(p)->prev = (p); \
+} while (0)
+
+
+/* Add an element to a list */
+static inline void list_add(struct list_head *new_entry,
+				struct list_head *list)
+{
+	struct list_head *list_next = list->next;
+
+	list->next = new_entry;
+	new_entry->prev = list;
+	new_entry->next = list_next;
+	list_next->prev = new_entry;
+
+}
+
+static inline void list_add_tail(struct list_head *new_entry,
+				 struct list_head *list)
+{
+	struct list_head *list_prev = list->prev;
+
+	list->prev = new_entry;
+	new_entry->next = list;
+	new_entry->prev = list_prev;
+	list_prev->next = new_entry;
+
+}
+
+
+/* Take an element out of its current list, with or without
+ * reinitialising the links.of the entry*/
+static inline void list_del(struct list_head *entry)
+{
+	struct list_head *list_next = entry->next;
+	struct list_head *list_prev = entry->prev;
+
+	list_next->prev = list_prev;
+	list_prev->next = list_next;
+
+}
+
+static inline void list_del_init(struct list_head *entry)
+{
+	list_del(entry);
+	entry->next = entry->prev = entry;
+}
+
+
+/* Test if the list is empty */
+static inline int list_empty(struct list_head *entry)
+{
+	return (entry->next == entry);
+}
+
+
+/* list_entry takes a pointer to a list entry and offsets it to that
+ * we can find a pointer to the object it is embedded in.
+ */
+
+
+#define list_entry(entry, type, member) \
+	((type *)((char *)(entry)-(unsigned long)(&((type *)NULL)->member)))
+
+
+/* list_for_each and list_for_each_safe  iterate over lists.
+ * list_for_each_safe uses temporary storage to make the list delete safe
+ */
+
+#define list_for_each(itervar, list) \
+	for (itervar = (list)->next; itervar != (list); itervar = itervar->next)
+
+#define list_for_each_safe(itervar, save_var, list) \
+	for (itervar = (list)->next, save_var = (list)->next->next; \
+		itervar != (list); \
+		itervar = save_var, save_var = save_var->next)
+
+
+#endif
diff --git a/fs/yaffs2/yaffs_mtdif.c b/fs/yaffs2/yaffs_mtdif.c
index d0e16d088e..db49052b38 100644
--- a/fs/yaffs2/yaffs_mtdif.c
+++ b/fs/yaffs2/yaffs_mtdif.c
@@ -14,9 +14,6 @@
 /* XXX U-BOOT XXX */
 #include <common.h>
 
-const char *yaffs_mtdif_c_version =
-    "$Id: yaffs_mtdif.c,v 1.19 2007/02/14 01:09:06 wookey Exp $";
-
 #include "yportenv.h"
 
 
@@ -27,72 +24,56 @@ const char *yaffs_mtdif_c_version =
 #include "linux/time.h"
 #include "linux/mtd/nand.h"
 
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18))
-static struct nand_oobinfo yaffs_oobinfo = {
-	.useecc = 1,
-	.eccbytes = 6,
-	.eccpos = {8, 9, 10, 13, 14, 15}
-};
-
-static struct nand_oobinfo yaffs_noeccinfo = {
-	.useecc = 0,
-};
-#endif
 
-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
-static inline void translate_spare2oob(const yaffs_Spare *spare, __u8 *oob)
+static inline void translate_spare2oob(const struct yaffs_spare *spare, u8 *oob)
 {
-	oob[0] = spare->tagByte0;
-	oob[1] = spare->tagByte1;
-	oob[2] = spare->tagByte2;
-	oob[3] = spare->tagByte3;
-	oob[4] = spare->tagByte4;
-	oob[5] = spare->tagByte5 & 0x3f;
-	oob[5] |= spare->blockStatus == 'Y' ? 0: 0x80;
-	oob[5] |= spare->pageStatus == 0 ? 0: 0x40;
-	oob[6] = spare->tagByte6;
-	oob[7] = spare->tagByte7;
+	oob[0] = spare->tb0;
+	oob[1] = spare->tb1;
+	oob[2] = spare->tb2;
+	oob[3] = spare->tb3;
+	oob[4] = spare->tb4;
+	oob[5] = spare->tb5 & 0x3f;
+	oob[5] |= spare->block_status == 'Y' ? 0 : 0x80;
+	oob[5] |= spare->page_status == 0 ? 0 : 0x40;
+	oob[6] = spare->tb6;
+	oob[7] = spare->tb7;
 }
 
-static inline void translate_oob2spare(yaffs_Spare *spare, __u8 *oob)
+static inline void translate_oob2spare(struct yaffs_spare *spare, u8 *oob)
 {
-	struct yaffs_NANDSpare *nspare = (struct yaffs_NANDSpare *)spare;
-	spare->tagByte0 = oob[0];
-	spare->tagByte1 = oob[1];
-	spare->tagByte2 = oob[2];
-	spare->tagByte3 = oob[3];
-	spare->tagByte4 = oob[4];
-	spare->tagByte5 = oob[5] == 0xff ? 0xff : oob[5] & 0x3f;
-	spare->blockStatus = oob[5] & 0x80 ? 0xff : 'Y';
-	spare->pageStatus = oob[5] & 0x40 ? 0xff : 0;
+	struct yaffs_nand_spare *nspare = (struct yaffs_nand_spare *)spare;
+	spare->tb0 = oob[0];
+	spare->tb1 = oob[1];
+	spare->tb2 = oob[2];
+	spare->tb3 = oob[3];
+	spare->tb4 = oob[4];
+	spare->tb5 = oob[5] == 0xff ? 0xff : oob[5] & 0x3f;
+	spare->block_status = oob[5] & 0x80 ? 0xff : 'Y';
+	spare->page_status = oob[5] & 0x40 ? 0xff : 0;
 	spare->ecc1[0] = spare->ecc1[1] = spare->ecc1[2] = 0xff;
-	spare->tagByte6 = oob[6];
-	spare->tagByte7 = oob[7];
+	spare->tb6 = oob[6];
+	spare->tb7 = oob[7];
 	spare->ecc2[0] = spare->ecc2[1] = spare->ecc2[2] = 0xff;
 
 	nspare->eccres1 = nspare->eccres2 = 0; /* FIXME */
 }
-#endif
 
-int nandmtd_WriteChunkToNAND(yaffs_Device * dev, int chunkInNAND,
-			     const __u8 * data, const yaffs_Spare * spare)
+
+int nandmtd_WriteChunkToNAND(struct yaffs_dev *dev, int chunkInNAND,
+			     const u8 *data, const struct yaffs_spare *spare)
 {
-	struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice);
-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
+	struct mtd_info *mtd = (struct mtd_info *)(dev->driver_context);
 	struct mtd_oob_ops ops;
-#endif
 	size_t dummy;
 	int retval = 0;
-
-	loff_t addr = ((loff_t) chunkInNAND) * dev->nDataBytesPerChunk;
-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
-	__u8 spareAsBytes[8]; /* OOB */
+	loff_t addr = ((loff_t) chunkInNAND) * dev->data_bytes_per_chunk;
+	u8 spareAsBytes[8]; /* OOB */
 
 	if (data && !spare)
-		retval = mtd->write(mtd, addr, dev->nDataBytesPerChunk,
+		retval = mtd->write(mtd, addr, dev->data_bytes_per_chunk,
 				&dummy, data);
 	else if (spare) {
-		if (dev->useNANDECC) {
+		if (dev->param.use_nand_ecc) {
 			translate_spare2oob(spare, spareAsBytes);
 			ops.mode = MTD_OOB_AUTO;
 			ops.ooblen = 8; /* temp hack */
@@ -100,37 +81,12 @@ int nandmtd_WriteChunkToNAND(yaffs_Device * dev, int chunkInNAND,
 			ops.mode = MTD_OOB_RAW;
 			ops.ooblen = YAFFS_BYTES_PER_SPARE;
 		}
-		ops.len = data ? dev->nDataBytesPerChunk : ops.ooblen;
+		ops.len = data ? dev->data_bytes_per_chunk : ops.ooblen;
 		ops.datbuf = (u8 *)data;
 		ops.ooboffs = 0;
 		ops.oobbuf = spareAsBytes;
 		retval = mtd->write_oob(mtd, addr, &ops);
 	}
-#else
-	__u8 *spareAsBytes = (__u8 *) spare;
-
-	if (data && spare) {
-		if (dev->useNANDECC)
-			retval =
-			    mtd->write_ecc(mtd, addr, dev->nDataBytesPerChunk,
-					   &dummy, data, spareAsBytes,
-					   &yaffs_oobinfo);
-		else
-			retval =
-			    mtd->write_ecc(mtd, addr, dev->nDataBytesPerChunk,
-					   &dummy, data, spareAsBytes,
-					   &yaffs_noeccinfo);
-	} else {
-		if (data)
-			retval =
-			    mtd->write(mtd, addr, dev->nDataBytesPerChunk, &dummy,
-				       data);
-		if (spare)
-			retval =
-			    mtd->write_oob(mtd, addr, YAFFS_BYTES_PER_SPARE,
-					   &dummy, spareAsBytes);
-	}
-#endif
 
 	if (retval == 0)
 		return YAFFS_OK;
@@ -138,69 +94,36 @@ int nandmtd_WriteChunkToNAND(yaffs_Device * dev, int chunkInNAND,
 		return YAFFS_FAIL;
 }
 
-int nandmtd_ReadChunkFromNAND(yaffs_Device * dev, int chunkInNAND, __u8 * data,
-			      yaffs_Spare * spare)
+int nandmtd_ReadChunkFromNAND(struct yaffs_dev *dev, int chunkInNAND, u8 *data,
+			      struct yaffs_spare *spare)
 {
-	struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice);
-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
+	struct mtd_info *mtd = (struct mtd_info *)(dev->driver_context);
 	struct mtd_oob_ops ops;
-#endif
 	size_t dummy;
 	int retval = 0;
 
-	loff_t addr = ((loff_t) chunkInNAND) * dev->nDataBytesPerChunk;
-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
-	__u8 spareAsBytes[8]; /* OOB */
+	loff_t addr = ((loff_t) chunkInNAND) * dev->data_bytes_per_chunk;
+	u8 spareAsBytes[8]; /* OOB */
 
 	if (data && !spare)
-		retval = mtd->read(mtd, addr, dev->nDataBytesPerChunk,
+		retval = mtd->read(mtd, addr, dev->data_bytes_per_chunk,
 				&dummy, data);
 	else if (spare) {
-		if (dev->useNANDECC) {
+		if (dev->param.use_nand_ecc) {
 			ops.mode = MTD_OOB_AUTO;
 			ops.ooblen = 8; /* temp hack */
 		} else {
 			ops.mode = MTD_OOB_RAW;
 			ops.ooblen = YAFFS_BYTES_PER_SPARE;
 		}
-		ops.len = data ? dev->nDataBytesPerChunk : ops.ooblen;
+		ops.len = data ? dev->data_bytes_per_chunk : ops.ooblen;
 		ops.datbuf = data;
 		ops.ooboffs = 0;
 		ops.oobbuf = spareAsBytes;
 		retval = mtd->read_oob(mtd, addr, &ops);
-		if (dev->useNANDECC)
+		if (dev->param.use_nand_ecc)
 			translate_oob2spare(spare, spareAsBytes);
 	}
-#else
-	__u8 *spareAsBytes = (__u8 *) spare;
-
-	if (data && spare) {
-		if (dev->useNANDECC) {
-			/* Careful, this call adds 2 ints */
-			/* to the end of the spare data.  Calling function */
-			/* should allocate enough memory for spare, */
-			/* i.e. [YAFFS_BYTES_PER_SPARE+2*sizeof(int)]. */
-			retval =
-			    mtd->read_ecc(mtd, addr, dev->nDataBytesPerChunk,
-					  &dummy, data, spareAsBytes,
-					  &yaffs_oobinfo);
-		} else {
-			retval =
-			    mtd->read_ecc(mtd, addr, dev->nDataBytesPerChunk,
-					  &dummy, data, spareAsBytes,
-					  &yaffs_noeccinfo);
-		}
-	} else {
-		if (data)
-			retval =
-			    mtd->read(mtd, addr, dev->nDataBytesPerChunk, &dummy,
-				      data);
-		if (spare)
-			retval =
-			    mtd->read_oob(mtd, addr, YAFFS_BYTES_PER_SPARE,
-					  &dummy, spareAsBytes);
-	}
-#endif
 
 	if (retval == 0)
 		return YAFFS_OK;
@@ -208,18 +131,18 @@ int nandmtd_ReadChunkFromNAND(yaffs_Device * dev, int chunkInNAND, __u8 * data,
 		return YAFFS_FAIL;
 }
 
-int nandmtd_EraseBlockInNAND(yaffs_Device * dev, int blockNumber)
+int nandmtd_EraseBlockInNAND(struct yaffs_dev *dev, int blockNumber)
 {
-	struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice);
+	struct mtd_info *mtd = (struct mtd_info *)(dev->driver_context);
 	__u32 addr =
-	    ((loff_t) blockNumber) * dev->nDataBytesPerChunk
-		* dev->nChunksPerBlock;
+	    ((loff_t) blockNumber) * dev->data_bytes_per_chunk
+		* dev->param.chunks_per_block;
 	struct erase_info ei;
 	int retval = 0;
 
 	ei.mtd = mtd;
 	ei.addr = addr;
-	ei.len = dev->nDataBytesPerChunk * dev->nChunksPerBlock;
+	ei.len = dev->data_bytes_per_chunk * dev->param.chunks_per_block;
 	ei.time = 1000;
 	ei.retries = 2;
 	ei.callback = NULL;
@@ -227,10 +150,6 @@ int nandmtd_EraseBlockInNAND(yaffs_Device * dev, int blockNumber)
 
 	/* Todo finish off the ei if required */
 
-/* XXX U-BOOT XXX */
-#if 0
-	sema_init(&dev->sem, 0);
-#endif
 
 	retval = mtd->erase(mtd, &ei);
 
@@ -240,7 +159,7 @@ int nandmtd_EraseBlockInNAND(yaffs_Device * dev, int blockNumber)
 		return YAFFS_FAIL;
 }
 
-int nandmtd_InitialiseNAND(yaffs_Device * dev)
+int nandmtd_InitialiseNAND(struct yaffs_dev *dev)
 {
 	return YAFFS_OK;
 }
diff --git a/fs/yaffs2/yaffs_mtdif.h b/fs/yaffs2/yaffs_mtdif.h
index 317600cac9..1a125823b6 100644
--- a/fs/yaffs2/yaffs_mtdif.h
+++ b/fs/yaffs2/yaffs_mtdif.h
@@ -18,10 +18,10 @@
 
 #include "yaffs_guts.h"
 
-int nandmtd_WriteChunkToNAND(yaffs_Device * dev, int chunkInNAND,
-			     const __u8 * data, const yaffs_Spare * spare);
-int nandmtd_ReadChunkFromNAND(yaffs_Device * dev, int chunkInNAND, __u8 * data,
-			      yaffs_Spare * spare);
-int nandmtd_EraseBlockInNAND(yaffs_Device * dev, int blockNumber);
-int nandmtd_InitialiseNAND(yaffs_Device * dev);
+int nandmtd_WriteChunkToNAND(struct yaffs_dev *dev, int chunkInNAND,
+			     const u8 *data, const struct yaffs_spare *spare);
+int nandmtd_ReadChunkFromNAND(struct yaffs_dev *dev, int chunkInNAND, u8 *data,
+			      struct yaffs_spare *spare);
+int nandmtd_EraseBlockInNAND(struct yaffs_dev *dev, int blockNumber);
+int nandmtd_InitialiseNAND(struct yaffs_dev *dev);
 #endif
diff --git a/fs/yaffs2/yaffs_mtdif2.c b/fs/yaffs2/yaffs_mtdif2.c
index f569b999f4..8135bcc0fe 100644
--- a/fs/yaffs2/yaffs_mtdif2.c
+++ b/fs/yaffs2/yaffs_mtdif2.c
@@ -17,11 +17,8 @@
 #include <common.h>
 #include "asm/errno.h"
 
-const char *yaffs_mtdif2_c_version =
-    "$Id: yaffs_mtdif2.c,v 1.17 2007/02/14 01:09:06 wookey Exp $";
-
 #include "yportenv.h"
-
+#include "yaffs_trace.h"
 
 #include "yaffs_mtdif2.h"
 
@@ -29,71 +26,64 @@ const char *yaffs_mtdif2_c_version =
 #include "linux/types.h"
 #include "linux/time.h"
 
+#include "yaffs_trace.h"
 #include "yaffs_packedtags2.h"
 
-int nandmtd2_WriteChunkWithTagsToNAND(yaffs_Device * dev, int chunkInNAND,
-				      const __u8 * data,
-				      const yaffs_ExtendedTags * tags)
-{
-	struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice);
-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
-	struct mtd_oob_ops ops;
-#else
-	size_t dummy;
-#endif
-	int retval = 0;
-
-	loff_t addr = ((loff_t) chunkInNAND) * dev->nDataBytesPerChunk;
-
-	yaffs_PackedTags2 pt;
+#define yaffs_dev_to_mtd(dev) ((struct mtd_info *)((dev)->driver_context))
+#define yaffs_dev_to_lc(dev) ((struct yaffs_linux_context *)((dev)->os_context))
 
-	T(YAFFS_TRACE_MTD,
-	  (TSTR
-	   ("nandmtd2_WriteChunkWithTagsToNAND chunk %d data %p tags %p"
-	    TENDSTR), chunkInNAND, data, tags));
 
-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
-	if (tags)
-		yaffs_PackTags2(&pt, tags);
-	else
-		BUG(); /* both tags and data should always be present */
-
-	if (data) {
-		ops.mode = MTD_OOB_AUTO;
-		ops.ooblen = sizeof(pt);
-		ops.len = dev->nDataBytesPerChunk;
-		ops.ooboffs = 0;
-		ops.datbuf = (__u8 *)data;
-		ops.oobbuf = (void *)&pt;
-		retval = mtd->write_oob(mtd, addr, &ops);
-	} else
-		BUG(); /* both tags and data should always be present */
-#else
-	if (tags) {
-		yaffs_PackTags2(&pt, tags);
-	}
+/* NB For use with inband tags....
+ * We assume that the data buffer is of size total_bytes_per_chunk so
+ * that we can also use it to load the tags.
+ */
+int nandmtd2_write_chunk_tags(struct yaffs_dev *dev, int nand_chunk,
+			      const u8 *data,
+			      const struct yaffs_ext_tags *tags)
+{
+	struct mtd_info *mtd = yaffs_dev_to_mtd(dev);
+	struct mtd_oob_ops ops;
 
-	if (data && tags) {
-		if (dev->useNANDECC)
-			retval =
-			    mtd->write_ecc(mtd, addr, dev->nDataBytesPerChunk,
-					   &dummy, data, (__u8 *) & pt, NULL);
-		else
-			retval =
-			    mtd->write_ecc(mtd, addr, dev->nDataBytesPerChunk,
-					   &dummy, data, (__u8 *) & pt, NULL);
+	int retval = 0;
+	loff_t addr;
+
+	struct yaffs_packed_tags2 pt;
+
+	int packed_tags_size =
+	    dev->param.no_tags_ecc ? sizeof(pt.t) : sizeof(pt);
+	void *packed_tags_ptr =
+	    dev->param.no_tags_ecc ? (void *)&pt.t : (void *)&pt;
+
+	yaffs_trace(YAFFS_TRACE_MTD,
+		"nandmtd2_write_chunk_tags chunk %d data %p tags %p",
+		nand_chunk, data, tags);
+
+	addr = ((loff_t) nand_chunk) * dev->param.total_bytes_per_chunk;
+
+	/* For yaffs2 writing there must be both data and tags.
+	 * If we're using inband tags, then the tags are stuffed into
+	 * the end of the data buffer.
+	 */
+	if (!data || !tags)
+		BUG();
+	else if (dev->param.inband_tags) {
+		struct yaffs_packed_tags2_tags_only *pt2tp;
+		pt2tp =
+		    (struct yaffs_packed_tags2_tags_only *)(data +
+							dev->
+							data_bytes_per_chunk);
+		yaffs_pack_tags2_tags_only(pt2tp, tags);
 	} else {
-		if (data)
-			retval =
-			    mtd->write(mtd, addr, dev->nDataBytesPerChunk, &dummy,
-				       data);
-		if (tags)
-			retval =
-			    mtd->write_oob(mtd, addr, mtd->oobsize, &dummy,
-					   (__u8 *) & pt);
-
+		yaffs_pack_tags2(&pt, tags, !dev->param.no_tags_ecc);
 	}
-#endif
+
+	ops.mode = MTD_OOB_AUTO;
+	ops.ooblen = (dev->param.inband_tags) ? 0 : packed_tags_size;
+	ops.len = dev->param.total_bytes_per_chunk;
+	ops.ooboffs = 0;
+	ops.datbuf = (u8 *) data;
+	ops.oobbuf = (dev->param.inband_tags) ? NULL : packed_tags_ptr;
+	retval = mtd->write_oob(mtd, addr, &ops);
 
 	if (retval == 0)
 		return YAFFS_OK;
@@ -101,88 +91,97 @@ int nandmtd2_WriteChunkWithTagsToNAND(yaffs_Device * dev, int chunkInNAND,
 		return YAFFS_FAIL;
 }
 
-int nandmtd2_ReadChunkWithTagsFromNAND(yaffs_Device * dev, int chunkInNAND,
-				       __u8 * data, yaffs_ExtendedTags * tags)
+int nandmtd2_read_chunk_tags(struct yaffs_dev *dev, int nand_chunk,
+			     u8 *data, struct yaffs_ext_tags *tags)
 {
-	struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice);
-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
+	struct mtd_info *mtd = yaffs_dev_to_mtd(dev);
+	u8 local_spare[128];
 	struct mtd_oob_ops ops;
-#endif
 	size_t dummy;
 	int retval = 0;
+	int local_data = 0;
+	struct yaffs_packed_tags2 pt;
+	loff_t addr = ((loff_t) nand_chunk) * dev->param.total_bytes_per_chunk;
+	int packed_tags_size =
+	    dev->param.no_tags_ecc ? sizeof(pt.t) : sizeof(pt);
+	void *packed_tags_ptr =
+	    dev->param.no_tags_ecc ? (void *)&pt.t : (void *)&pt;
+
+	yaffs_trace(YAFFS_TRACE_MTD,
+		"nandmtd2_read_chunk_tags chunk %d data %p tags %p",
+		nand_chunk, data, tags);
+
+	if (dev->param.inband_tags) {
+
+		if (!data) {
+			local_data = 1;
+			data = yaffs_get_temp_buffer(dev);
+		}
 
-	loff_t addr = ((loff_t) chunkInNAND) * dev->nDataBytesPerChunk;
-
-	yaffs_PackedTags2 pt;
-
-	T(YAFFS_TRACE_MTD,
-	  (TSTR
-	   ("nandmtd2_ReadChunkWithTagsFromNAND chunk %d data %p tags %p"
-	    TENDSTR), chunkInNAND, data, tags));
+	}
 
-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
-	if (data && !tags)
-		retval = mtd->read(mtd, addr, dev->nDataBytesPerChunk,
-				&dummy, data);
+	if (dev->param.inband_tags || (data && !tags))
+		retval = mtd->read(mtd, addr, dev->param.total_bytes_per_chunk,
+				   &dummy, data);
 	else if (tags) {
 		ops.mode = MTD_OOB_AUTO;
-		ops.ooblen = sizeof(pt);
-		ops.len = data ? dev->nDataBytesPerChunk : sizeof(pt);
+		ops.ooblen = packed_tags_size;
+		ops.len = data ? dev->data_bytes_per_chunk : packed_tags_size;
 		ops.ooboffs = 0;
 		ops.datbuf = data;
-		ops.oobbuf = dev->spareBuffer;
+		ops.oobbuf = local_spare;
 		retval = mtd->read_oob(mtd, addr, &ops);
 	}
-#else
-	if (data && tags) {
-		if (dev->useNANDECC) {
-			retval =
-			    mtd->read_ecc(mtd, addr, dev->nDataBytesPerChunk,
-					  &dummy, data, dev->spareBuffer,
-					  NULL);
-		} else {
-			retval =
-			    mtd->read_ecc(mtd, addr, dev->nDataBytesPerChunk,
-					  &dummy, data, dev->spareBuffer,
-					  NULL);
+
+	if (dev->param.inband_tags) {
+		if (tags) {
+			struct yaffs_packed_tags2_tags_only *pt2tp;
+			pt2tp =
+				(struct yaffs_packed_tags2_tags_only *)
+				&data[dev->data_bytes_per_chunk];
+			yaffs_unpack_tags2_tags_only(tags, pt2tp);
 		}
 	} else {
-		if (data)
-			retval =
-			    mtd->read(mtd, addr, dev->nDataBytesPerChunk, &dummy,
-				      data);
-		if (tags)
-			retval =
-			    mtd->read_oob(mtd, addr, mtd->oobsize, &dummy,
-					  dev->spareBuffer);
+		if (tags) {
+			memcpy(packed_tags_ptr,
+			       local_spare,
+			       packed_tags_size);
+			yaffs_unpack_tags2(tags, &pt, !dev->param.no_tags_ecc);
+		}
 	}
-#endif
-
-	memcpy(&pt, dev->spareBuffer, sizeof(pt));
-
-	if (tags)
-		yaffs_UnpackTags2(tags, &pt);
 
-	if(tags && retval == -EBADMSG && tags->eccResult == YAFFS_ECC_RESULT_NO_ERROR)
-		tags->eccResult = YAFFS_ECC_RESULT_UNFIXED;
+	if (local_data)
+		yaffs_release_temp_buffer(dev, data);
 
+	if (tags && retval == -EBADMSG
+	    && tags->ecc_result == YAFFS_ECC_RESULT_NO_ERROR) {
+		tags->ecc_result = YAFFS_ECC_RESULT_UNFIXED;
+		dev->n_ecc_unfixed++;
+	}
+	if (tags && retval == -EUCLEAN
+	    && tags->ecc_result == YAFFS_ECC_RESULT_NO_ERROR) {
+		tags->ecc_result = YAFFS_ECC_RESULT_FIXED;
+		dev->n_ecc_fixed++;
+	}
 	if (retval == 0)
 		return YAFFS_OK;
 	else
 		return YAFFS_FAIL;
 }
 
-int nandmtd2_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo)
+
+int nandmtd2_MarkNANDBlockBad(struct yaffs_dev *dev, int blockNo)
 {
-	struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice);
+	struct mtd_info *mtd = (struct mtd_info *)(dev->driver_context);
 	int retval;
-	T(YAFFS_TRACE_MTD,
-	  (TSTR("nandmtd2_MarkNANDBlockBad %d" TENDSTR), blockNo));
+
+	yaffs_trace(YAFFS_TRACE_MTD,
+		"nandmtd2_MarkNANDBlockBad %d", blockNo);
 
 	retval =
 	    mtd->block_markbad(mtd,
-			       blockNo * dev->nChunksPerBlock *
-			       dev->nDataBytesPerChunk);
+			       blockNo * dev->param.chunks_per_block *
+			       dev->data_bytes_per_chunk);
 
 	if (retval == 0)
 		return YAFFS_OK;
@@ -191,42 +190,40 @@ int nandmtd2_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo)
 
 }
 
-int nandmtd2_QueryNANDBlock(struct yaffs_DeviceStruct *dev, int blockNo,
-			    yaffs_BlockState * state, int *sequenceNumber)
+int nandmtd2_QueryNANDBlock(struct yaffs_dev *dev, int blockNo,
+			    enum yaffs_block_state *state, u32 *sequenceNumber)
 {
-	struct mtd_info *mtd = (struct mtd_info *)(dev->genericDevice);
+	struct mtd_info *mtd = (struct mtd_info *)(dev->driver_context);
 	int retval;
 
-	T(YAFFS_TRACE_MTD,
-	  (TSTR("nandmtd2_QueryNANDBlock %d" TENDSTR), blockNo));
+	yaffs_trace(YAFFS_TRACE_MTD, "nandmtd2_QueryNANDBlock %d", blockNo);
 	retval =
 	    mtd->block_isbad(mtd,
-			     blockNo * dev->nChunksPerBlock *
-			     dev->nDataBytesPerChunk);
+			     blockNo * dev->param.chunks_per_block *
+			     dev->data_bytes_per_chunk);
 
 	if (retval) {
-		T(YAFFS_TRACE_MTD, (TSTR("block is bad" TENDSTR)));
+		yaffs_trace(YAFFS_TRACE_MTD, "block is bad");
 
 		*state = YAFFS_BLOCK_STATE_DEAD;
 		*sequenceNumber = 0;
 	} else {
-		yaffs_ExtendedTags t;
-		nandmtd2_ReadChunkWithTagsFromNAND(dev,
-						   blockNo *
-						   dev->nChunksPerBlock, NULL,
-						   &t);
-
-		if (t.chunkUsed) {
-			*sequenceNumber = t.sequenceNumber;
-			*state = YAFFS_BLOCK_STATE_NEEDS_SCANNING;
+		struct yaffs_ext_tags t;
+		nandmtd2_read_chunk_tags(dev,
+					   blockNo *
+					   dev->param.chunks_per_block, NULL,
+					   &t);
+
+		if (t.chunk_used) {
+			*sequenceNumber = t.seq_number;
+			*state = YAFFS_BLOCK_STATE_NEEDS_SCAN;
 		} else {
 			*sequenceNumber = 0;
 			*state = YAFFS_BLOCK_STATE_EMPTY;
 		}
 	}
-	T(YAFFS_TRACE_MTD,
-	  (TSTR("block is bad seq %d state %d" TENDSTR), *sequenceNumber,
-	   *state));
+	yaffs_trace(YAFFS_TRACE_MTD, "block is bad seq %d state %d",
+			*sequenceNumber, *state);
 
 	if (retval == 0)
 		return YAFFS_OK;
diff --git a/fs/yaffs2/yaffs_mtdif2.h b/fs/yaffs2/yaffs_mtdif2.h
index b67ba52aa4..62be173633 100644
--- a/fs/yaffs2/yaffs_mtdif2.h
+++ b/fs/yaffs2/yaffs_mtdif2.h
@@ -17,13 +17,14 @@
 #define __YAFFS_MTDIF2_H__
 
 #include "yaffs_guts.h"
-int nandmtd2_WriteChunkWithTagsToNAND(yaffs_Device * dev, int chunkInNAND,
-				      const __u8 * data,
-				      const yaffs_ExtendedTags * tags);
-int nandmtd2_ReadChunkWithTagsFromNAND(yaffs_Device * dev, int chunkInNAND,
-				       __u8 * data, yaffs_ExtendedTags * tags);
-int nandmtd2_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo);
-int nandmtd2_QueryNANDBlock(struct yaffs_DeviceStruct *dev, int blockNo,
-			    yaffs_BlockState * state, int *sequenceNumber);
+
+int nandmtd2_write_chunk_tags(struct yaffs_dev *dev, int chunkInNAND,
+				      const u8 *data,
+				      const struct yaffs_ext_tags *tags);
+int nandmtd2_read_chunk_tags(struct yaffs_dev *dev, int chunkInNAND,
+				       u8 *data, struct yaffs_ext_tags *tags);
+int nandmtd2_MarkNANDBlockBad(struct yaffs_dev *dev, int blockNo);
+int nandmtd2_QueryNANDBlock(struct yaffs_dev *dev, int blockNo,
+			    enum yaffs_block_state *state, u32 *sequenceNumber);
 
 #endif
diff --git a/fs/yaffs2/yaffs_nameval.c b/fs/yaffs2/yaffs_nameval.c
new file mode 100644
index 0000000000..a20a3e47ce
--- /dev/null
+++ b/fs/yaffs2/yaffs_nameval.c
@@ -0,0 +1,208 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2011 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * This simple implementation of a name-value store assumes a small number of
+* values and fits into a small finite buffer.
+ *
+ * Each attribute is stored as a record:
+ *  sizeof(int) bytes   record size.
+ *  yaffs_strnlen+1 bytes name null terminated.
+ *  nbytes    value.
+ *  ----------
+ *  total size  stored in record size
+ *
+ * This code has not been tested with unicode yet.
+ */
+
+#include "yaffs_nameval.h"
+
+#include "yportenv.h"
+
+static int nval_find(const char *xb, int xb_size, const YCHAR *name,
+		     int *exist_size)
+{
+	int pos = 0;
+	int size;
+
+	memcpy(&size, xb, sizeof(int));
+	while (size > 0 && (size < xb_size) && (pos + size < xb_size)) {
+		if (!yaffs_strncmp((YCHAR *) (xb + pos + sizeof(int)),
+				name, size)) {
+			if (exist_size)
+				*exist_size = size;
+			return pos;
+		}
+		pos += size;
+		if (pos < xb_size - sizeof(int))
+			memcpy(&size, xb + pos, sizeof(int));
+		else
+			size = 0;
+	}
+	if (exist_size)
+		*exist_size = 0;
+	return -ENODATA;
+}
+
+static int nval_used(const char *xb, int xb_size)
+{
+	int pos = 0;
+	int size;
+
+	memcpy(&size, xb + pos, sizeof(int));
+	while (size > 0 && (size < xb_size) && (pos + size < xb_size)) {
+		pos += size;
+		if (pos < xb_size - sizeof(int))
+			memcpy(&size, xb + pos, sizeof(int));
+		else
+			size = 0;
+	}
+	return pos;
+}
+
+int nval_del(char *xb, int xb_size, const YCHAR *name)
+{
+	int pos = nval_find(xb, xb_size, name, NULL);
+	int size;
+
+	if (pos < 0 || pos >= xb_size)
+		return -ENODATA;
+
+	/* Find size, shift rest over this record,
+	 * then zero out the rest of buffer */
+	memcpy(&size, xb + pos, sizeof(int));
+	memcpy(xb + pos, xb + pos + size, xb_size - (pos + size));
+	memset(xb + (xb_size - size), 0, size);
+	return 0;
+}
+
+int nval_set(char *xb, int xb_size, const YCHAR *name, const char *buf,
+		int bsize, int flags)
+{
+	int pos;
+	int namelen = yaffs_strnlen(name, xb_size);
+	int reclen;
+	int size_exist = 0;
+	int space;
+	int start;
+
+	pos = nval_find(xb, xb_size, name, &size_exist);
+
+	if (flags & XATTR_CREATE && pos >= 0)
+		return -EEXIST;
+	if (flags & XATTR_REPLACE && pos < 0)
+		return -ENODATA;
+
+	start = nval_used(xb, xb_size);
+	space = xb_size - start + size_exist;
+
+	reclen = (sizeof(int) + namelen + 1 + bsize);
+
+	if (reclen > space)
+		return -ENOSPC;
+
+	if (pos >= 0) {
+		nval_del(xb, xb_size, name);
+		start = nval_used(xb, xb_size);
+	}
+
+	pos = start;
+
+	memcpy(xb + pos, &reclen, sizeof(int));
+	pos += sizeof(int);
+	yaffs_strncpy((YCHAR *) (xb + pos), name, reclen);
+	pos += (namelen + 1);
+	memcpy(xb + pos, buf, bsize);
+	return 0;
+}
+
+int nval_get(const char *xb, int xb_size, const YCHAR * name, char *buf,
+	     int bsize)
+{
+	int pos = nval_find(xb, xb_size, name, NULL);
+	int size;
+
+	if (pos >= 0 && pos < xb_size) {
+
+		memcpy(&size, xb + pos, sizeof(int));
+		pos += sizeof(int);	/* advance past record length */
+		size -= sizeof(int);
+
+		/* Advance over name string */
+		while (xb[pos] && size > 0 && pos < xb_size) {
+			pos++;
+			size--;
+		}
+		/*Advance over NUL */
+		pos++;
+		size--;
+
+		/* If bsize is zero then this is a size query.
+		 * Return the size, but don't copy.
+		 */
+		if (!bsize)
+			return size;
+
+		if (size <= bsize) {
+			memcpy(buf, xb + pos, size);
+			return size;
+		}
+	}
+	if (pos >= 0)
+		return -ERANGE;
+
+	return -ENODATA;
+}
+
+int nval_list(const char *xb, int xb_size, char *buf, int bsize)
+{
+	int pos = 0;
+	int size;
+	int name_len;
+	int ncopied = 0;
+	int filled = 0;
+
+	memcpy(&size, xb + pos, sizeof(int));
+	while (size > sizeof(int) &&
+		size <= xb_size &&
+		(pos + size) < xb_size &&
+		!filled) {
+		pos += sizeof(int);
+		size -= sizeof(int);
+		name_len = yaffs_strnlen((YCHAR *) (xb + pos), size);
+		if (ncopied + name_len + 1 < bsize) {
+			memcpy(buf, xb + pos, name_len * sizeof(YCHAR));
+			buf += name_len;
+			*buf = '\0';
+			buf++;
+			if (sizeof(YCHAR) > 1) {
+				*buf = '\0';
+				buf++;
+			}
+			ncopied += (name_len + 1);
+		} else {
+			filled = 1;
+		}
+		pos += size;
+		if (pos < xb_size - sizeof(int))
+			memcpy(&size, xb + pos, sizeof(int));
+		else
+			size = 0;
+	}
+	return ncopied;
+}
+
+int nval_hasvalues(const char *xb, int xb_size)
+{
+	return nval_used(xb, xb_size) > 0;
+}
diff --git a/fs/yaffs2/yaffs_malloc.h b/fs/yaffs2/yaffs_nameval.h
index 3ed6175163..951e64f872 100644
--- a/fs/yaffs2/yaffs_malloc.h
+++ b/fs/yaffs2/yaffs_nameval.h
@@ -1,8 +1,7 @@
-#ifndef __YAFFS_MALLOC_H__
 /*
  * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
  *
- * Copyright (C) 2002-2007 Aleph One Ltd.
+ * Copyright (C) 2002-2011 Aleph One Ltd.
  *   for Toby Churchill Ltd and Brightstar Engineering
  *
  * Created by Charles Manning <charles@aleph1.co.uk>
@@ -14,12 +13,16 @@
  * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
  */
 
-/* XXX U-BOOT XXX */
-#if 0
-#include <stdlib.h>
-#endif
+#ifndef __NAMEVAL_H__
+#define __NAMEVAL_H__
 
-void *yaffs_malloc(size_t size);
-void yaffs_free(void *ptr);
+#include "yportenv.h"
 
+int nval_del(char *xb, int xb_size, const YCHAR * name);
+int nval_set(char *xb, int xb_size, const YCHAR * name, const char *buf,
+	     int bsize, int flags);
+int nval_get(const char *xb, int xb_size, const YCHAR * name, char *buf,
+	     int bsize);
+int nval_list(const char *xb, int xb_size, char *buf, int bsize);
+int nval_hasvalues(const char *xb, int xb_size);
 #endif
diff --git a/fs/yaffs2/yaffs_nand.c b/fs/yaffs2/yaffs_nand.c
index ce048cc185..165d01004d 100644
--- a/fs/yaffs2/yaffs_nand.c
+++ b/fs/yaffs2/yaffs_nand.c
@@ -1,7 +1,7 @@
 /*
  * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
  *
- * Copyright (C) 2002-2007 Aleph One Ltd.
+ * Copyright (C) 2002-2011 Aleph One Ltd.
  *   for Toby Churchill Ltd and Brightstar Engineering
  *
  * Created by Charles Manning <charles@aleph1.co.uk>
@@ -11,124 +11,110 @@
  * published by the Free Software Foundation.
  */
 
-/* XXX U-BOOT XXX */
-#include <common.h>
-
-const char *yaffs_nand_c_version =
-    "$Id: yaffs_nand.c,v 1.7 2007/02/14 01:09:06 wookey Exp $";
-
 #include "yaffs_nand.h"
 #include "yaffs_tagscompat.h"
-#include "yaffs_tagsvalidity.h"
 
+#include "yaffs_getblockinfo.h"
+#include "yaffs_summary.h"
 
-int yaffs_ReadChunkWithTagsFromNAND(yaffs_Device * dev, int chunkInNAND,
-					   __u8 * buffer,
-					   yaffs_ExtendedTags * tags)
+int yaffs_rd_chunk_tags_nand(struct yaffs_dev *dev, int nand_chunk,
+			     u8 *buffer, struct yaffs_ext_tags *tags)
 {
 	int result;
-	yaffs_ExtendedTags localTags;
+	struct yaffs_ext_tags local_tags;
+	int flash_chunk = nand_chunk - dev->chunk_offset;
 
-	int realignedChunkInNAND = chunkInNAND - dev->chunkOffset;
+	dev->n_page_reads++;
 
-	/* If there are no tags provided, use local tags to get prioritised gc working */
-	if(!tags)
-		tags = &localTags;
+	/* If there are no tags provided use local tags. */
+	if (!tags)
+		tags = &local_tags;
 
-	if (dev->readChunkWithTagsFromNAND)
-		result = dev->readChunkWithTagsFromNAND(dev, realignedChunkInNAND, buffer,
-						      tags);
+	if (dev->param.read_chunk_tags_fn)
+		result =
+		    dev->param.read_chunk_tags_fn(dev, flash_chunk, buffer,
+						  tags);
 	else
-		result = yaffs_TagsCompatabilityReadChunkWithTagsFromNAND(dev,
-									realignedChunkInNAND,
-									buffer,
-									tags);
-	if(tags &&
-	   tags->eccResult > YAFFS_ECC_RESULT_NO_ERROR){
-
-		yaffs_BlockInfo *bi = yaffs_GetBlockInfo(dev, chunkInNAND/dev->nChunksPerBlock);
-		yaffs_HandleChunkError(dev,bi);
+		result = yaffs_tags_compat_rd(dev,
+					      flash_chunk, buffer, tags);
+	if (tags && tags->ecc_result > YAFFS_ECC_RESULT_NO_ERROR) {
+
+		struct yaffs_block_info *bi;
+		bi = yaffs_get_block_info(dev,
+					  nand_chunk /
+					  dev->param.chunks_per_block);
+		yaffs_handle_chunk_error(dev, bi);
 	}
-
 	return result;
 }
 
-int yaffs_WriteChunkWithTagsToNAND(yaffs_Device * dev,
-						   int chunkInNAND,
-						   const __u8 * buffer,
-						   yaffs_ExtendedTags * tags)
+int yaffs_wr_chunk_tags_nand(struct yaffs_dev *dev,
+				int nand_chunk,
+				const u8 *buffer, struct yaffs_ext_tags *tags)
 {
-	chunkInNAND -= dev->chunkOffset;
+	int result;
+	int flash_chunk = nand_chunk - dev->chunk_offset;
 
+	dev->n_page_writes++;
 
 	if (tags) {
-		tags->sequenceNumber = dev->sequenceNumber;
-		tags->chunkUsed = 1;
-		if (!yaffs_ValidateTags(tags)) {
-			T(YAFFS_TRACE_ERROR,
-			  (TSTR("Writing uninitialised tags" TENDSTR)));
-			YBUG();
-		}
-		T(YAFFS_TRACE_WRITE,
-		  (TSTR("Writing chunk %d tags %d %d" TENDSTR), chunkInNAND,
-		   tags->objectId, tags->chunkId));
+		tags->seq_number = dev->seq_number;
+		tags->chunk_used = 1;
+		yaffs_trace(YAFFS_TRACE_WRITE,
+			"Writing chunk %d tags %d %d",
+			nand_chunk, tags->obj_id, tags->chunk_id);
 	} else {
-		T(YAFFS_TRACE_ERROR, (TSTR("Writing with no tags" TENDSTR)));
-		YBUG();
+		yaffs_trace(YAFFS_TRACE_ERROR, "Writing with no tags");
+		BUG();
+		return YAFFS_FAIL;
 	}
 
-	if (dev->writeChunkWithTagsToNAND)
-		return dev->writeChunkWithTagsToNAND(dev, chunkInNAND, buffer,
-						     tags);
+	if (dev->param.write_chunk_tags_fn)
+		result = dev->param.write_chunk_tags_fn(dev, flash_chunk,
+							buffer, tags);
 	else
-		return yaffs_TagsCompatabilityWriteChunkWithTagsToNAND(dev,
-								       chunkInNAND,
-								       buffer,
-								       tags);
+		result = yaffs_tags_compat_wr(dev, flash_chunk, buffer, tags);
+
+	yaffs_summary_add(dev, tags, nand_chunk);
+
+	return result;
 }
 
-int yaffs_MarkBlockBad(yaffs_Device * dev, int blockNo)
+int yaffs_mark_bad(struct yaffs_dev *dev, int block_no)
 {
-	blockNo -= dev->blockOffset;
+	block_no -= dev->block_offset;
+	if (dev->param.bad_block_fn)
+		return dev->param.bad_block_fn(dev, block_no);
 
-;
-	if (dev->markNANDBlockBad)
-		return dev->markNANDBlockBad(dev, blockNo);
-	else
-		return yaffs_TagsCompatabilityMarkNANDBlockBad(dev, blockNo);
+	return yaffs_tags_compat_mark_bad(dev, block_no);
 }
 
-int yaffs_QueryInitialBlockState(yaffs_Device * dev,
-						 int blockNo,
-						 yaffs_BlockState * state,
-						 int *sequenceNumber)
+int yaffs_query_init_block_state(struct yaffs_dev *dev,
+				 int block_no,
+				 enum yaffs_block_state *state,
+				 u32 *seq_number)
 {
-	blockNo -= dev->blockOffset;
+	block_no -= dev->block_offset;
+	if (dev->param.query_block_fn)
+		return dev->param.query_block_fn(dev, block_no, state,
+						 seq_number);
 
-	if (dev->queryNANDBlock)
-		return dev->queryNANDBlock(dev, blockNo, state, sequenceNumber);
-	else
-		return yaffs_TagsCompatabilityQueryNANDBlock(dev, blockNo,
-							     state,
-							     sequenceNumber);
+	return yaffs_tags_compat_query_block(dev, block_no, state, seq_number);
 }
 
-
-int yaffs_EraseBlockInNAND(struct yaffs_DeviceStruct *dev,
-				  int blockInNAND)
+int yaffs_erase_block(struct yaffs_dev *dev, int flash_block)
 {
 	int result;
 
-	blockInNAND -= dev->blockOffset;
-
-
-	dev->nBlockErasures++;
-	result = dev->eraseBlockInNAND(dev, blockInNAND);
-
+	flash_block -= dev->block_offset;
+	dev->n_erasures++;
+	result = dev->param.erase_fn(dev, flash_block);
 	return result;
 }
 
-int yaffs_InitialiseNAND(struct yaffs_DeviceStruct *dev)
+int yaffs_init_nand(struct yaffs_dev *dev)
 {
-	return dev->initialiseNAND(dev);
+	if (dev->param.initialise_flash_fn)
+		return dev->param.initialise_flash_fn(dev);
+	return YAFFS_OK;
 }
diff --git a/fs/yaffs2/yaffs_nand.h b/fs/yaffs2/yaffs_nand.h
index f3bedcf35c..71346627fc 100644
--- a/fs/yaffs2/yaffs_nand.h
+++ b/fs/yaffs2/yaffs_nand.h
@@ -1,7 +1,7 @@
 /*
  * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
  *
- * Copyright (C) 2002-2007 Aleph One Ltd.
+ * Copyright (C) 2002-2011 Aleph One Ltd.
  *   for Toby Churchill Ltd and Brightstar Engineering
  *
  * Created by Charles Manning <charles@aleph1.co.uk>
@@ -17,27 +17,22 @@
 #define __YAFFS_NAND_H__
 #include "yaffs_guts.h"
 
+int yaffs_rd_chunk_tags_nand(struct yaffs_dev *dev, int nand_chunk,
+			     u8 *buffer, struct yaffs_ext_tags *tags);
 
+int yaffs_wr_chunk_tags_nand(struct yaffs_dev *dev,
+			     int nand_chunk,
+			     const u8 *buffer, struct yaffs_ext_tags *tags);
 
-int yaffs_ReadChunkWithTagsFromNAND(yaffs_Device * dev, int chunkInNAND,
-					   __u8 * buffer,
-					   yaffs_ExtendedTags * tags);
+int yaffs_mark_bad(struct yaffs_dev *dev, int block_no);
 
-int yaffs_WriteChunkWithTagsToNAND(yaffs_Device * dev,
-						   int chunkInNAND,
-						   const __u8 * buffer,
-						   yaffs_ExtendedTags * tags);
+int yaffs_query_init_block_state(struct yaffs_dev *dev,
+				 int block_no,
+				 enum yaffs_block_state *state,
+				 unsigned *seq_number);
 
-int yaffs_MarkBlockBad(yaffs_Device * dev, int blockNo);
+int yaffs_erase_block(struct yaffs_dev *dev, int flash_block);
 
-int yaffs_QueryInitialBlockState(yaffs_Device * dev,
-						 int blockNo,
-						 yaffs_BlockState * state,
-						 int *sequenceNumber);
-
-int yaffs_EraseBlockInNAND(struct yaffs_DeviceStruct *dev,
-				  int blockInNAND);
-
-int yaffs_InitialiseNAND(struct yaffs_DeviceStruct *dev);
+int yaffs_init_nand(struct yaffs_dev *dev);
 
 #endif
diff --git a/fs/yaffs2/yaffs_nandemul2k.h b/fs/yaffs2/yaffs_nandemul2k.h
index cd2e96f7ae..cb0c4e64de 100644
--- a/fs/yaffs2/yaffs_nandemul2k.h
+++ b/fs/yaffs2/yaffs_nandemul2k.h
@@ -1,7 +1,7 @@
 /*
  * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
  *
- * Copyright (C) 2002-2007 Aleph One Ltd.
+ * Copyright (C) 2002-2011 Aleph One Ltd.
  *   for Toby Churchill Ltd and Brightstar Engineering
  *
  * Created by Charles Manning <charles@aleph1.co.uk>
@@ -20,18 +20,18 @@
 
 #include "yaffs_guts.h"
 
-int nandemul2k_WriteChunkWithTagsToNAND(struct yaffs_DeviceStruct *dev,
-					int chunkInNAND, const __u8 * data,
-					yaffs_ExtendedTags * tags);
-int nandemul2k_ReadChunkWithTagsFromNAND(struct yaffs_DeviceStruct *dev,
-					 int chunkInNAND, __u8 * data,
-					 yaffs_ExtendedTags * tags);
-int nandemul2k_MarkNANDBlockBad(struct yaffs_DeviceStruct *dev, int blockNo);
-int nandemul2k_QueryNANDBlock(struct yaffs_DeviceStruct *dev, int blockNo,
-			      yaffs_BlockState * state, int *sequenceNumber);
-int nandemul2k_EraseBlockInNAND(struct yaffs_DeviceStruct *dev,
-				int blockInNAND);
-int nandemul2k_InitialiseNAND(struct yaffs_DeviceStruct *dev);
+int nandemul2k_WriteChunkWithTagsToNAND(struct yaffs_dev *dev,
+					int nand_chunk, const u8 *data,
+					const struct yaffs_ext_tags *tags);
+int nandemul2k_ReadChunkWithTagsFromNAND(struct yaffs_dev *dev,
+					 int nand_chunk, u8 *data,
+					 struct yaffs_ext_tags *tags);
+int nandemul2k_MarkNANDBlockBad(struct yaffs_dev *dev, int block_no);
+int nandemul2k_QueryNANDBlock(struct yaffs_dev *dev, int block_no,
+			      enum yaffs_block_state *state, u32 *seq_number);
+int nandemul2k_EraseBlockInNAND(struct yaffs_dev *dev,
+				int flash_block);
+int nandemul2k_InitialiseNAND(struct yaffs_dev *dev);
 int nandemul2k_GetBytesPerChunk(void);
 int nandemul2k_GetChunksPerBlock(void);
 int nandemul2k_GetNumberOfBlocks(void);
diff --git a/fs/yaffs2/yaffs_nandif.c b/fs/yaffs2/yaffs_nandif.c
new file mode 100644
index 0000000000..79b00ab3b7
--- /dev/null
+++ b/fs/yaffs2/yaffs_nandif.c
@@ -0,0 +1,251 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2011 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "yportenv.h"
+#include "yaffs_guts.h"
+
+
+#include "yaffs_nandif.h"
+#include "yaffs_packedtags2.h"
+
+#include "yramsim.h"
+
+#include "yaffs_trace.h"
+#include "yaffsfs.h"
+
+
+/* NB For use with inband tags....
+ * We assume that the data buffer is of size totalBytersPerChunk so that
+ * we can also use it to load the tags.
+ */
+int ynandif_WriteChunkWithTagsToNAND(struct yaffs_dev *dev, int nand_chunk,
+				      const u8 *data,
+				      const struct yaffs_ext_tags *tags)
+{
+
+	int retval = 0;
+	struct yaffs_packed_tags2 pt;
+	void *spare;
+	unsigned spareSize = 0;
+	struct ynandif_Geometry *geometry = (struct ynandif_Geometry *)(dev->driver_context);
+
+	yaffs_trace(YAFFS_TRACE_MTD,
+		"nandmtd2_WriteChunkWithTagsToNAND chunk %d data %p tags %p",
+		nand_chunk, data, tags);
+
+
+	/* For yaffs2 writing there must be both data and tags.
+	 * If we're using inband tags, then the tags are stuffed into
+	 * the end of the data buffer.
+	 */
+
+	if (dev->param.inband_tags) {
+		struct yaffs_packed_tags2_tags_only *pt2tp;
+
+		pt2tp = (struct yaffs_packed_tags2_tags_only *)
+			(data + dev->data_bytes_per_chunk);
+		yaffs_pack_tags2_tags_only(pt2tp, tags);
+		spare = NULL;
+		spareSize = 0;
+	} else {
+		yaffs_pack_tags2(&pt, tags, !dev->param.no_tags_ecc);
+		spare = &pt;
+		spareSize = sizeof(struct yaffs_packed_tags2);
+	}
+
+	retval = geometry->writeChunk(dev, nand_chunk,
+				data, dev->param.total_bytes_per_chunk,
+				spare, spareSize);
+
+	return retval;
+}
+
+int ynandif_ReadChunkWithTagsFromNAND(struct yaffs_dev *dev, int nand_chunk,
+				       u8 *data, struct yaffs_ext_tags *tags)
+{
+	struct yaffs_packed_tags2 pt;
+	int localData = 0;
+	void *spare = NULL;
+	unsigned spareSize;
+	int retval = 0;
+	int eccStatus; /* 0 = ok, 1 = fixed, -1 = unfixed */
+	struct ynandif_Geometry *geometry = (struct ynandif_Geometry *)(dev->driver_context);
+
+	yaffs_trace(YAFFS_TRACE_MTD,
+		"nandmtd2_ReadChunkWithTagsFromNAND chunk %d data %p tags %p",
+		nand_chunk, data, tags);
+
+	if (!tags) {
+		spare = NULL;
+		spareSize = 0;
+	} else if (dev->param.inband_tags) {
+
+		if (!data) {
+			localData = 1;
+			data = yaffs_get_temp_buffer(dev);
+		}
+		spare = NULL;
+		spareSize = 0;
+	} else {
+		spare = &pt;
+		spareSize = sizeof(struct yaffs_packed_tags2);
+	}
+
+	retval = geometry->readChunk(dev, nand_chunk,
+				 data,
+				 data ? dev->param.total_bytes_per_chunk : 0,
+				 spare, spareSize,
+				 &eccStatus);
+
+	if (dev->param.inband_tags) {
+		if (tags) {
+			struct yaffs_packed_tags2_tags_only *pt2tp;
+			pt2tp = (struct yaffs_packed_tags2_tags_only *)
+					&data[dev->data_bytes_per_chunk];
+			yaffs_unpack_tags2_tags_only(tags, pt2tp);
+		}
+	} else {
+		if (tags)
+			yaffs_unpack_tags2(tags, &pt, !dev->param.no_tags_ecc);
+	}
+
+	if (tags && tags->chunk_used) {
+		if (eccStatus < 0 ||
+		   tags->ecc_result == YAFFS_ECC_RESULT_UNFIXED)
+			tags->ecc_result = YAFFS_ECC_RESULT_UNFIXED;
+		else if (eccStatus > 0 ||
+			     tags->ecc_result == YAFFS_ECC_RESULT_FIXED)
+			tags->ecc_result = YAFFS_ECC_RESULT_FIXED;
+		else
+			tags->ecc_result = YAFFS_ECC_RESULT_NO_ERROR;
+	}
+
+	if (localData)
+		yaffs_release_temp_buffer(dev, data);
+
+	return retval;
+}
+
+int ynandif_MarkNANDBlockBad(struct yaffs_dev *dev, int blockId)
+{
+	struct ynandif_Geometry *geometry = (struct ynandif_Geometry *)(dev->driver_context);
+
+	return geometry->markBlockBad(dev, blockId);
+}
+
+int ynandif_EraseBlockInNAND(struct yaffs_dev *dev, int blockId)
+{
+	struct ynandif_Geometry *geometry = (struct ynandif_Geometry *)(dev->driver_context);
+
+	return geometry->eraseBlock(dev, blockId);
+
+}
+
+
+static int ynandif_IsBlockOk(struct yaffs_dev *dev, int blockId)
+{
+	struct ynandif_Geometry *geometry = (struct ynandif_Geometry *)(dev->driver_context);
+
+	return geometry->checkBlockOk(dev, blockId);
+}
+
+int ynandif_QueryNANDBlock(struct yaffs_dev *dev, int blockId,
+		enum yaffs_block_state *state, u32 *seq_number)
+{
+	unsigned chunkNo;
+	struct yaffs_ext_tags tags;
+
+	*seq_number = 0;
+
+	chunkNo = blockId * dev->param.chunks_per_block;
+
+	if (!ynandif_IsBlockOk(dev, blockId)) {
+		*state = YAFFS_BLOCK_STATE_DEAD;
+	} else {
+		ynandif_ReadChunkWithTagsFromNAND(dev, chunkNo, NULL, &tags);
+
+		if (!tags.chunk_used) {
+			*state = YAFFS_BLOCK_STATE_EMPTY;
+		} else {
+			*state = YAFFS_BLOCK_STATE_NEEDS_SCAN;
+			*seq_number = tags.seq_number;
+		}
+	}
+
+	return YAFFS_OK;
+}
+
+
+int ynandif_InitialiseNAND(struct yaffs_dev *dev)
+{
+	struct ynandif_Geometry *geometry = (struct ynandif_Geometry *)(dev->driver_context);
+
+	geometry->initialise(dev);
+
+	return YAFFS_OK;
+}
+
+int ynandif_Deinitialise_flash_fn(struct yaffs_dev *dev)
+{
+	struct ynandif_Geometry *geometry = (struct ynandif_Geometry *)(dev->driver_context);
+
+	geometry->deinitialise(dev);
+
+	return YAFFS_OK;
+}
+
+
+struct yaffs_dev *
+	yaffs_add_dev_from_geometry(const YCHAR *name,
+					const struct ynandif_Geometry *geometry)
+{
+	YCHAR *clonedName = malloc(sizeof(YCHAR) *
+				(strnlen(name, YAFFS_MAX_NAME_LENGTH)+1));
+	struct yaffs_dev *dev = malloc(sizeof(struct yaffs_dev));
+	struct yaffs_param *param;
+
+	if (dev && clonedName) {
+		memset(dev, 0, sizeof(struct yaffs_dev));
+		strcpy(clonedName, name);
+
+		param = &dev->param;
+
+		param->name = clonedName;
+		param->write_chunk_tags_fn = ynandif_WriteChunkWithTagsToNAND;
+		param->read_chunk_tags_fn = ynandif_ReadChunkWithTagsFromNAND;
+		param->erase_fn = ynandif_EraseBlockInNAND;
+		param->initialise_flash_fn = ynandif_InitialiseNAND;
+		param->query_block_fn = ynandif_QueryNANDBlock;
+		param->bad_block_fn = ynandif_MarkNANDBlockBad;
+		param->n_caches = 20;
+		param->start_block = geometry->start_block;
+		param->end_block   = geometry->end_block;
+		param->total_bytes_per_chunk  = geometry->dataSize;
+		param->spare_bytes_per_chunk  = geometry->spareSize;
+		param->inband_tags		  = geometry->inband_tags;
+		param->chunks_per_block	  = geometry->pagesPerBlock;
+		param->use_nand_ecc		  = geometry->hasECC;
+		param->is_yaffs2		  = geometry->useYaffs2;
+		param->n_reserved_blocks	  = 5;
+		dev->driver_context		  = (void *)geometry;
+
+		yaffs_add_device(dev);
+
+		return dev;
+	}
+
+	free(dev);
+	free(clonedName);
+
+	return NULL;
+}
diff --git a/fs/yaffs2/yaffs_nandif.h b/fs/yaffs2/yaffs_nandif.h
new file mode 100644
index 0000000000..e780f7f3b4
--- /dev/null
+++ b/fs/yaffs2/yaffs_nandif.h
@@ -0,0 +1,65 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2011 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+
+#ifndef __YNANDIF_H__
+#define __YNANDIF_H__
+
+#include "yaffs_guts.h"
+
+struct ynandif_Geometry {
+	unsigned start_block;
+	unsigned end_block;
+	unsigned dataSize;
+	unsigned spareSize;
+	unsigned pagesPerBlock;
+	unsigned hasECC;
+	unsigned inband_tags;
+	unsigned useYaffs2;
+
+	int (*initialise)(struct yaffs_dev *dev);
+	int (*deinitialise)(struct yaffs_dev *dev);
+
+	int (*readChunk) (struct yaffs_dev *dev,
+					  unsigned pageId,
+					  unsigned char *data,
+					  unsigned dataLength,
+					  unsigned char *spare,
+					  unsigned spareLength,
+					  int *eccStatus);
+	/* ECC status is set to 0 for OK, 1 for fixed, -1 for unfixed. */
+
+	int (*writeChunk)(struct yaffs_dev *dev,
+					  unsigned pageId,
+					  const unsigned char *data,
+					  unsigned dataLength,
+					  const unsigned char *spare,
+					  unsigned spareLength);
+
+	int (*eraseBlock)(struct yaffs_dev *dev, unsigned blockId);
+
+	int (*checkBlockOk)(struct yaffs_dev *dev, unsigned blockId);
+	int (*markBlockBad)(struct yaffs_dev *dev, unsigned blockId);
+
+	void *privateData;
+
+};
+
+struct yaffs_dev *
+	yaffs_add_dev_from_geometry(const YCHAR *name,
+					const struct ynandif_Geometry *geometry);
+
+
+#endif
diff --git a/fs/yaffs2/yaffs_tagsvalidity.h b/fs/yaffs2/yaffs_osglue.h
index 2fd0c24ed2..f629a4b59e 100644
--- a/fs/yaffs2/yaffs_tagsvalidity.h
+++ b/fs/yaffs2/yaffs_osglue.h
@@ -1,7 +1,7 @@
 /*
  * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
  *
- * Copyright (C) 2002-2007 Aleph One Ltd.
+ * Copyright (C) 2002-2011 Aleph One Ltd.
  *   for Toby Churchill Ltd and Brightstar Engineering
  *
  * Created by Charles Manning <charles@aleph1.co.uk>
@@ -13,12 +13,29 @@
  * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
  */
 
+/*
+ * Header file for using yaffs in an application via
+ * a direct interface.
+ */
+
+
+#ifndef __YAFFS_OSGLUE_H__
+#define __YAFFS_OSGLUE_H__
+
+
+#include "yportenv.h"
+
+void yaffsfs_Lock(void);
+void yaffsfs_Unlock(void);
+
+u32 yaffsfs_CurrentTime(void);
+
+void yaffsfs_SetError(int err);
+
+void *yaffsfs_malloc(size_t size);
+void yaffsfs_free(void *ptr);
 
-#ifndef __YAFFS_TAGS_VALIDITY_H__
-#define __YAFFS_TAGS_VALIDITY_H__
+void yaffsfs_OSInitialisation(void);
 
-#include "yaffs_guts.h"
 
-void yaffs_InitialiseTags(yaffs_ExtendedTags * tags);
-int yaffs_ValidateTags(yaffs_ExtendedTags * tags);
 #endif
diff --git a/fs/yaffs2/yaffs_packedtags1.c b/fs/yaffs2/yaffs_packedtags1.c
index a149431d4f..dd9a331d8f 100644
--- a/fs/yaffs2/yaffs_packedtags1.c
+++ b/fs/yaffs2/yaffs_packedtags1.c
@@ -1,7 +1,7 @@
 /*
  * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
  *
- * Copyright (C) 2002-2007 Aleph One Ltd.
+ * Copyright (C) 2002-2011 Aleph One Ltd.
  *   for Toby Churchill Ltd and Brightstar Engineering
  *
  * Created by Charles Manning <charles@aleph1.co.uk>
@@ -11,45 +11,46 @@
  * published by the Free Software Foundation.
  */
 
-/* XXX U-BOOT XXX */
-#include <common.h>
-
 #include "yaffs_packedtags1.h"
 #include "yportenv.h"
 
-void yaffs_PackTags1(yaffs_PackedTags1 * pt, const yaffs_ExtendedTags * t)
+static const u8 all_ff[20] = {
+	0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff
+};
+
+void yaffs_pack_tags1(struct yaffs_packed_tags1 *pt,
+		      const struct yaffs_ext_tags *t)
 {
-	pt->chunkId = t->chunkId;
-	pt->serialNumber = t->serialNumber;
-	pt->byteCount = t->byteCount;
-	pt->objectId = t->objectId;
+	pt->chunk_id = t->chunk_id;
+	pt->serial_number = t->serial_number;
+	pt->n_bytes = t->n_bytes;
+	pt->obj_id = t->obj_id;
 	pt->ecc = 0;
-	pt->deleted = (t->chunkDeleted) ? 0 : 1;
-	pt->unusedStuff = 0;
-	pt->shouldBeFF = 0xFFFFFFFF;
-
+	pt->deleted = (t->is_deleted) ? 0 : 1;
+	pt->unused_stuff = 0;
+	pt->should_be_ff = 0xffffffff;
 }
 
-void yaffs_UnpackTags1(yaffs_ExtendedTags * t, const yaffs_PackedTags1 * pt)
+void yaffs_unpack_tags1(struct yaffs_ext_tags *t,
+			const struct yaffs_packed_tags1 *pt)
 {
-	static const __u8 allFF[] =
-	    { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-0xff };
 
-	if (memcmp(allFF, pt, sizeof(yaffs_PackedTags1))) {
-		t->blockBad = 0;
-		if (pt->shouldBeFF != 0xFFFFFFFF) {
-			t->blockBad = 1;
-		}
-		t->chunkUsed = 1;
-		t->objectId = pt->objectId;
-		t->chunkId = pt->chunkId;
-		t->byteCount = pt->byteCount;
-		t->eccResult = YAFFS_ECC_RESULT_NO_ERROR;
-		t->chunkDeleted = (pt->deleted) ? 0 : 1;
-		t->serialNumber = pt->serialNumber;
+	if (memcmp(all_ff, pt, sizeof(struct yaffs_packed_tags1))) {
+		t->block_bad = 0;
+		if (pt->should_be_ff != 0xffffffff)
+			t->block_bad = 1;
+		t->chunk_used = 1;
+		t->obj_id = pt->obj_id;
+		t->chunk_id = pt->chunk_id;
+		t->n_bytes = pt->n_bytes;
+		t->ecc_result = YAFFS_ECC_RESULT_NO_ERROR;
+		t->is_deleted = (pt->deleted) ? 0 : 1;
+		t->serial_number = pt->serial_number;
 	} else {
-		memset(t, 0, sizeof(yaffs_ExtendedTags));
-
+		memset(t, 0, sizeof(struct yaffs_ext_tags));
 	}
 }
diff --git a/fs/yaffs2/yaffs_packedtags1.h b/fs/yaffs2/yaffs_packedtags1.h
index 776c5c256c..b80f0a5b15 100644
--- a/fs/yaffs2/yaffs_packedtags1.h
+++ b/fs/yaffs2/yaffs_packedtags1.h
@@ -1,7 +1,7 @@
 /*
  * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
  *
- * Copyright (C) 2002-2007 Aleph One Ltd.
+ * Copyright (C) 2002-2011 Aleph One Ltd.
  *   for Toby Churchill Ltd and Brightstar Engineering
  *
  * Created by Charles Manning <charles@aleph1.co.uk>
@@ -20,18 +20,20 @@
 
 #include "yaffs_guts.h"
 
-typedef struct {
-	unsigned chunkId:20;
-	unsigned serialNumber:2;
-	unsigned byteCount:10;
-	unsigned objectId:18;
+struct yaffs_packed_tags1 {
+	unsigned chunk_id:20;
+	unsigned serial_number:2;
+	unsigned n_bytes:10;
+	unsigned obj_id:18;
 	unsigned ecc:12;
 	unsigned deleted:1;
-	unsigned unusedStuff:1;
-	unsigned shouldBeFF;
+	unsigned unused_stuff:1;
+	unsigned should_be_ff;
 
-} yaffs_PackedTags1;
+};
 
-void yaffs_PackTags1(yaffs_PackedTags1 * pt, const yaffs_ExtendedTags * t);
-void yaffs_UnpackTags1(yaffs_ExtendedTags * t, const yaffs_PackedTags1 * pt);
+void yaffs_pack_tags1(struct yaffs_packed_tags1 *pt,
+		      const struct yaffs_ext_tags *t);
+void yaffs_unpack_tags1(struct yaffs_ext_tags *t,
+			const struct yaffs_packed_tags1 *pt);
 #endif
diff --git a/fs/yaffs2/yaffs_packedtags2.c b/fs/yaffs2/yaffs_packedtags2.c
index 474400999b..e1d18cc33c 100644
--- a/fs/yaffs2/yaffs_packedtags2.c
+++ b/fs/yaffs2/yaffs_packedtags2.c
@@ -1,7 +1,7 @@
 /*
  * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
  *
- * Copyright (C) 2002-2007 Aleph One Ltd.
+ * Copyright (C) 2002-2011 Aleph One Ltd.
  *   for Toby Churchill Ltd and Brightstar Engineering
  *
  * Created by Charles Manning <charles@aleph1.co.uk>
@@ -11,12 +11,9 @@
  * published by the Free Software Foundation.
  */
 
-/* XXX U-BOOT XXX */
-#include <common.h>
-
 #include "yaffs_packedtags2.h"
 #include "yportenv.h"
-#include "yaffs_tagsvalidity.h"
+#include "yaffs_trace.h"
 
 /* This code packs a set of extended tags into a binary structure for
  * NAND storage
@@ -27,159 +24,174 @@
  * This is defined by having the EXTRA_HEADER_INFO_FLAG set.
  */
 
-/* Extra flags applied to chunkId */
+/* Extra flags applied to chunk_id */
 
 #define EXTRA_HEADER_INFO_FLAG	0x80000000
 #define EXTRA_SHRINK_FLAG	0x40000000
 #define EXTRA_SHADOWS_FLAG	0x20000000
 #define EXTRA_SPARE_FLAGS	0x10000000
 
-#define ALL_EXTRA_FLAGS		0xF0000000
+#define ALL_EXTRA_FLAGS		0xf0000000
 
 /* Also, the top 4 bits of the object Id are set to the object type. */
 #define EXTRA_OBJECT_TYPE_SHIFT (28)
-#define EXTRA_OBJECT_TYPE_MASK  ((0x0F) << EXTRA_OBJECT_TYPE_SHIFT)
+#define EXTRA_OBJECT_TYPE_MASK  ((0x0f) << EXTRA_OBJECT_TYPE_SHIFT)
 
-static void yaffs_DumpPackedTags2(const yaffs_PackedTags2 * pt)
+static void yaffs_dump_packed_tags2_tags_only(
+				const struct yaffs_packed_tags2_tags_only *ptt)
 {
-	T(YAFFS_TRACE_MTD,
-	  (TSTR("packed tags obj %d chunk %d byte %d seq %d" TENDSTR),
-	   pt->t.objectId, pt->t.chunkId, pt->t.byteCount,
-	   pt->t.sequenceNumber));
+	yaffs_trace(YAFFS_TRACE_MTD,
+		"packed tags obj %d chunk %d byte %d seq %d",
+		ptt->obj_id, ptt->chunk_id, ptt->n_bytes, ptt->seq_number);
 }
 
-static void yaffs_DumpTags2(const yaffs_ExtendedTags * t)
+static void yaffs_dump_packed_tags2(const struct yaffs_packed_tags2 *pt)
 {
-	T(YAFFS_TRACE_MTD,
-	  (TSTR
-	   ("ext.tags eccres %d blkbad %d chused %d obj %d chunk%d byte "
-	    "%d del %d ser %d seq %d"
-	    TENDSTR), t->eccResult, t->blockBad, t->chunkUsed, t->objectId,
-	   t->chunkId, t->byteCount, t->chunkDeleted, t->serialNumber,
-	   t->sequenceNumber));
-
+	yaffs_dump_packed_tags2_tags_only(&pt->t);
 }
 
-void yaffs_PackTags2(yaffs_PackedTags2 * pt, const yaffs_ExtendedTags * t)
+static void yaffs_dump_tags2(const struct yaffs_ext_tags *t)
 {
-	pt->t.chunkId = t->chunkId;
-	pt->t.sequenceNumber = t->sequenceNumber;
-	pt->t.byteCount = t->byteCount;
-	pt->t.objectId = t->objectId;
+	yaffs_trace(YAFFS_TRACE_MTD,
+		"ext.tags eccres %d blkbad %d chused %d obj %d chunk%d byte %d del %d ser %d seq %d",
+		t->ecc_result, t->block_bad, t->chunk_used, t->obj_id,
+		t->chunk_id, t->n_bytes, t->is_deleted, t->serial_number,
+		t->seq_number);
 
-	if (t->chunkId == 0 && t->extraHeaderInfoAvailable) {
-		/* Store the extra header info instead */
-		/* We save the parent object in the chunkId */
-		pt->t.chunkId = EXTRA_HEADER_INFO_FLAG
-			| t->extraParentObjectId;
-		if (t->extraIsShrinkHeader) {
-			pt->t.chunkId |= EXTRA_SHRINK_FLAG;
-		}
-		if (t->extraShadows) {
-			pt->t.chunkId |= EXTRA_SHADOWS_FLAG;
-		}
+}
 
-		pt->t.objectId &= ~EXTRA_OBJECT_TYPE_MASK;
-		pt->t.objectId |=
-		    (t->extraObjectType << EXTRA_OBJECT_TYPE_SHIFT);
+static int yaffs_check_tags_extra_packable(const struct yaffs_ext_tags *t)
+{
+	if (t->chunk_id != 0 || !t->extra_available)
+		return 0;
+
+	/* Check if the file size is too long to store */
+	if (t->extra_obj_type == YAFFS_OBJECT_TYPE_FILE &&
+	    (t->extra_file_size >> 31) != 0)
+		return 0;
+	return 1;
+}
 
-		if (t->extraObjectType == YAFFS_OBJECT_TYPE_HARDLINK) {
-			pt->t.byteCount = t->extraEquivalentObjectId;
-		} else if (t->extraObjectType == YAFFS_OBJECT_TYPE_FILE) {
-			pt->t.byteCount = t->extraFileLength;
-		} else {
-			pt->t.byteCount = 0;
-		}
+void yaffs_pack_tags2_tags_only(struct yaffs_packed_tags2_tags_only *ptt,
+				const struct yaffs_ext_tags *t)
+{
+	ptt->chunk_id = t->chunk_id;
+	ptt->seq_number = t->seq_number;
+	ptt->n_bytes = t->n_bytes;
+	ptt->obj_id = t->obj_id;
+
+	/* Only store extra tags for object headers.
+	 * If it is a file then only store  if the file size is short\
+	 * enough to fit.
+	 */
+	if (yaffs_check_tags_extra_packable(t)) {
+		/* Store the extra header info instead */
+		/* We save the parent object in the chunk_id */
+		ptt->chunk_id = EXTRA_HEADER_INFO_FLAG | t->extra_parent_id;
+		if (t->extra_is_shrink)
+			ptt->chunk_id |= EXTRA_SHRINK_FLAG;
+		if (t->extra_shadows)
+			ptt->chunk_id |= EXTRA_SHADOWS_FLAG;
+
+		ptt->obj_id &= ~EXTRA_OBJECT_TYPE_MASK;
+		ptt->obj_id |= (t->extra_obj_type << EXTRA_OBJECT_TYPE_SHIFT);
+
+		if (t->extra_obj_type == YAFFS_OBJECT_TYPE_HARDLINK)
+			ptt->n_bytes = t->extra_equiv_id;
+		else if (t->extra_obj_type == YAFFS_OBJECT_TYPE_FILE)
+			ptt->n_bytes = (unsigned) t->extra_file_size;
+		else
+			ptt->n_bytes = 0;
 	}
 
-	yaffs_DumpPackedTags2(pt);
-	yaffs_DumpTags2(t);
-
-#ifndef YAFFS_IGNORE_TAGS_ECC
-	{
-		yaffs_ECCCalculateOther((unsigned char *)&pt->t,
-					sizeof(yaffs_PackedTags2TagsPart),
-					&pt->ecc);
-	}
-#endif
+	yaffs_dump_packed_tags2_tags_only(ptt);
+	yaffs_dump_tags2(t);
 }
 
-void yaffs_UnpackTags2(yaffs_ExtendedTags * t, yaffs_PackedTags2 * pt)
+void yaffs_pack_tags2(struct yaffs_packed_tags2 *pt,
+		      const struct yaffs_ext_tags *t, int tags_ecc)
 {
+	yaffs_pack_tags2_tags_only(&pt->t, t);
 
-	memset(t, 0, sizeof(yaffs_ExtendedTags));
+	if (tags_ecc)
+		yaffs_ecc_calc_other((unsigned char *)&pt->t,
+				    sizeof(struct yaffs_packed_tags2_tags_only),
+				    &pt->ecc);
+}
 
-	yaffs_InitialiseTags(t);
+void yaffs_unpack_tags2_tags_only(struct yaffs_ext_tags *t,
+				  struct yaffs_packed_tags2_tags_only *ptt)
+{
+	memset(t, 0, sizeof(struct yaffs_ext_tags));
+
+	if (ptt->seq_number == 0xffffffff)
+		return;
+
+	t->block_bad = 0;
+	t->chunk_used = 1;
+	t->obj_id = ptt->obj_id;
+	t->chunk_id = ptt->chunk_id;
+	t->n_bytes = ptt->n_bytes;
+	t->is_deleted = 0;
+	t->serial_number = 0;
+	t->seq_number = ptt->seq_number;
+
+	/* Do extra header info stuff */
+	if (ptt->chunk_id & EXTRA_HEADER_INFO_FLAG) {
+		t->chunk_id = 0;
+		t->n_bytes = 0;
+
+		t->extra_available = 1;
+		t->extra_parent_id = ptt->chunk_id & (~(ALL_EXTRA_FLAGS));
+		t->extra_is_shrink = ptt->chunk_id & EXTRA_SHRINK_FLAG ? 1 : 0;
+		t->extra_shadows = ptt->chunk_id & EXTRA_SHADOWS_FLAG ? 1 : 0;
+		t->extra_obj_type = ptt->obj_id >> EXTRA_OBJECT_TYPE_SHIFT;
+		t->obj_id &= ~EXTRA_OBJECT_TYPE_MASK;
+
+		if (t->extra_obj_type == YAFFS_OBJECT_TYPE_HARDLINK)
+			t->extra_equiv_id = ptt->n_bytes;
+		else
+			t->extra_file_size = ptt->n_bytes;
+	}
+	yaffs_dump_packed_tags2_tags_only(ptt);
+	yaffs_dump_tags2(t);
+}
 
-	if (pt->t.sequenceNumber != 0xFFFFFFFF) {
-		/* Page is in use */
-#ifdef YAFFS_IGNORE_TAGS_ECC
-		{
-			t->eccResult = YAFFS_ECC_RESULT_NO_ERROR;
-		}
-#else
-		{
-			yaffs_ECCOther ecc;
-			int result;
-			yaffs_ECCCalculateOther((unsigned char *)&pt->t,
-						sizeof
-						(yaffs_PackedTags2TagsPart),
-						&ecc);
-			result =
-			    yaffs_ECCCorrectOther((unsigned char *)&pt->t,
-						  sizeof
-						  (yaffs_PackedTags2TagsPart),
-						  &pt->ecc, &ecc);
-			switch(result){
-				case 0:
-					t->eccResult = YAFFS_ECC_RESULT_NO_ERROR;
-					break;
-				case 1:
-					t->eccResult = YAFFS_ECC_RESULT_FIXED;
-					break;
-				case -1:
-					t->eccResult = YAFFS_ECC_RESULT_UNFIXED;
-					break;
-				default:
-					t->eccResult = YAFFS_ECC_RESULT_UNKNOWN;
-			}
-		}
-#endif
-		t->blockBad = 0;
-		t->chunkUsed = 1;
-		t->objectId = pt->t.objectId;
-		t->chunkId = pt->t.chunkId;
-		t->byteCount = pt->t.byteCount;
-		t->chunkDeleted = 0;
-		t->serialNumber = 0;
-		t->sequenceNumber = pt->t.sequenceNumber;
-
-		/* Do extra header info stuff */
-
-		if (pt->t.chunkId & EXTRA_HEADER_INFO_FLAG) {
-			t->chunkId = 0;
-			t->byteCount = 0;
-
-			t->extraHeaderInfoAvailable = 1;
-			t->extraParentObjectId =
-			    pt->t.chunkId & (~(ALL_EXTRA_FLAGS));
-			t->extraIsShrinkHeader =
-			    (pt->t.chunkId & EXTRA_SHRINK_FLAG) ? 1 : 0;
-			t->extraShadows =
-			    (pt->t.chunkId & EXTRA_SHADOWS_FLAG) ? 1 : 0;
-			t->extraObjectType =
-			    pt->t.objectId >> EXTRA_OBJECT_TYPE_SHIFT;
-			t->objectId &= ~EXTRA_OBJECT_TYPE_MASK;
-
-			if (t->extraObjectType == YAFFS_OBJECT_TYPE_HARDLINK) {
-				t->extraEquivalentObjectId = pt->t.byteCount;
-			} else {
-				t->extraFileLength = pt->t.byteCount;
-			}
+void yaffs_unpack_tags2(struct yaffs_ext_tags *t, struct yaffs_packed_tags2 *pt,
+			int tags_ecc)
+{
+	enum yaffs_ecc_result ecc_result = YAFFS_ECC_RESULT_NO_ERROR;
+
+	if (pt->t.seq_number != 0xffffffff && tags_ecc) {
+		/* Chunk is in use and we need to do ECC */
+
+		struct yaffs_ecc_other ecc;
+		int result;
+		yaffs_ecc_calc_other((unsigned char *)&pt->t,
+				sizeof(struct yaffs_packed_tags2_tags_only),
+				&ecc);
+		result =
+		    yaffs_ecc_correct_other((unsigned char *)&pt->t,
+				sizeof(struct yaffs_packed_tags2_tags_only),
+				&pt->ecc, &ecc);
+		switch (result) {
+		case 0:
+			ecc_result = YAFFS_ECC_RESULT_NO_ERROR;
+			break;
+		case 1:
+			ecc_result = YAFFS_ECC_RESULT_FIXED;
+			break;
+		case -1:
+			ecc_result = YAFFS_ECC_RESULT_UNFIXED;
+			break;
+		default:
+			ecc_result = YAFFS_ECC_RESULT_UNKNOWN;
 		}
 	}
+	yaffs_unpack_tags2_tags_only(t, &pt->t);
 
-	yaffs_DumpPackedTags2(pt);
-	yaffs_DumpTags2(t);
+	t->ecc_result = ecc_result;
 
+	yaffs_dump_packed_tags2(pt);
+	yaffs_dump_tags2(t);
 }
diff --git a/fs/yaffs2/yaffs_packedtags2.h b/fs/yaffs2/yaffs_packedtags2.h
index c2242ffe76..675e719460 100644
--- a/fs/yaffs2/yaffs_packedtags2.h
+++ b/fs/yaffs2/yaffs_packedtags2.h
@@ -1,7 +1,7 @@
 /*
  * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
  *
- * Copyright (C) 2002-2007 Aleph One Ltd.
+ * Copyright (C) 2002-2011 Aleph One Ltd.
  *   for Toby Churchill Ltd and Brightstar Engineering
  *
  * Created by Charles Manning <charles@aleph1.co.uk>
@@ -21,18 +21,27 @@
 #include "yaffs_guts.h"
 #include "yaffs_ecc.h"
 
-typedef struct {
-	unsigned sequenceNumber;
-	unsigned objectId;
-	unsigned chunkId;
-	unsigned byteCount;
-} yaffs_PackedTags2TagsPart;
+struct yaffs_packed_tags2_tags_only {
+	unsigned seq_number;
+	unsigned obj_id;
+	unsigned chunk_id;
+	unsigned n_bytes;
+};
 
-typedef struct {
-	yaffs_PackedTags2TagsPart t;
-	yaffs_ECCOther ecc;
-} yaffs_PackedTags2;
+struct yaffs_packed_tags2 {
+	struct yaffs_packed_tags2_tags_only t;
+	struct yaffs_ecc_other ecc;
+};
 
-void yaffs_PackTags2(yaffs_PackedTags2 * pt, const yaffs_ExtendedTags * t);
-void yaffs_UnpackTags2(yaffs_ExtendedTags * t, yaffs_PackedTags2 * pt);
+/* Full packed tags with ECC, used for oob tags */
+void yaffs_pack_tags2(struct yaffs_packed_tags2 *pt,
+		      const struct yaffs_ext_tags *t, int tags_ecc);
+void yaffs_unpack_tags2(struct yaffs_ext_tags *t, struct yaffs_packed_tags2 *pt,
+			int tags_ecc);
+
+/* Only the tags part (no ECC for use with inband tags */
+void yaffs_pack_tags2_tags_only(struct yaffs_packed_tags2_tags_only *pt,
+				const struct yaffs_ext_tags *t);
+void yaffs_unpack_tags2_tags_only(struct yaffs_ext_tags *t,
+				  struct yaffs_packed_tags2_tags_only *pt);
 #endif
diff --git a/fs/yaffs2/yaffs_qsort.c b/fs/yaffs2/yaffs_qsort.c
index 4d56f96afb..afd1ffa799 100644
--- a/fs/yaffs2/yaffs_qsort.c
+++ b/fs/yaffs2/yaffs_qsort.c
@@ -27,58 +27,56 @@
  * SUCH DAMAGE.
  */
 
-/* XXX U-BOOT XXX */
-#include <common.h>
-
 #include "yportenv.h"
-//#include <linux/string.h>
+/* #include <linux/string.h> */
 
 /*
  * Qsort routine from Bentley & McIlroy's "Engineering a Sort Function".
  */
-#define swapcode(TYPE, parmi, parmj, n) { 		\
-	long i = (n) / sizeof (TYPE); 			\
-	register TYPE *pi = (TYPE *) (parmi); 		\
-	register TYPE *pj = (TYPE *) (parmj); 		\
-	do { 						\
+#define swapcode(TYPE, parmi, parmj, n) do {		\
+	long i = (n) / sizeof(TYPE);			\
+	register TYPE *pi = (TYPE *) (parmi);		\
+	register TYPE *pj = (TYPE *) (parmj);		\
+	do {						\
 		register TYPE	t = *pi;		\
 		*pi++ = *pj;				\
 		*pj++ = t;				\
 	} while (--i > 0);				\
-}
+} while (0)
 
 #define SWAPINIT(a, es) swaptype = ((char *)a - (char *)0) % sizeof(long) || \
-	es % sizeof(long) ? 2 : es == sizeof(long)? 0 : 1;
+	es % sizeof(long) ? 2 : es == sizeof(long) ? 0 : 1;
 
-static __inline void
+static inline void
 swapfunc(char *a, char *b, int n, int swaptype)
 {
 	if (swaptype <= 1)
-		swapcode(long, a, b, n)
+		swapcode(long, a, b, n);
 	else
-		swapcode(char, a, b, n)
+		swapcode(char, a, b, n);
 }
 
-#define swap(a, b)					\
+#define yswap(a, b) do {					\
 	if (swaptype == 0) {				\
 		long t = *(long *)(a);			\
 		*(long *)(a) = *(long *)(b);		\
 		*(long *)(b) = t;			\
 	} else						\
-		swapfunc(a, b, es, swaptype)
+		swapfunc(a, b, es, swaptype);		\
+} while (0)
 
-#define vecswap(a, b, n) 	if ((n) > 0) swapfunc(a, b, n, swaptype)
+#define vecswap(a, b, n)	if ((n) > 0) swapfunc(a, b, n, swaptype)
 
-static __inline char *
+static inline char *
 med3(char *a, char *b, char *c, int (*cmp)(const void *, const void *))
 {
 	return cmp(a, b) < 0 ?
-	       (cmp(b, c) < 0 ? b : (cmp(a, c) < 0 ? c : a ))
-	      :(cmp(b, c) > 0 ? b : (cmp(a, c) < 0 ? a : c ));
+		(cmp(b, c) < 0 ? b : (cmp(a, c) < 0 ? c : a))
+		: (cmp(b, c) > 0 ? b : (cmp(a, c) < 0 ? a : c));
 }
 
 #ifndef min
-#define min(a,b) (((a) < (b)) ? (a) : (b))
+#define min(a, b) (((a) < (b)) ? (a) : (b))
 #endif
 
 void
@@ -95,7 +93,7 @@ loop:	SWAPINIT(a, es);
 		for (pm = (char *)a + es; pm < (char *) a + n * es; pm += es)
 			for (pl = pm; pl > (char *) a && cmp(pl - es, pl) > 0;
 			     pl -= es)
-				swap(pl, pl - es);
+				yswap(pl, pl - es);
 		return;
 	}
 	pm = (char *)a + (n / 2) * es;
@@ -110,7 +108,7 @@ loop:	SWAPINIT(a, es);
 		}
 		pm = med3(pl, pm, pn, cmp);
 	}
-	swap(a, pm);
+	yswap(a, pm);
 	pa = pb = (char *)a + es;
 
 	pc = pd = (char *)a + (n - 1) * es;
@@ -118,7 +116,7 @@ loop:	SWAPINIT(a, es);
 		while (pb <= pc && (r = cmp(pb, a)) <= 0) {
 			if (r == 0) {
 				swap_cnt = 1;
-				swap(pa, pb);
+				yswap(pa, pb);
 				pa += es;
 			}
 			pb += es;
@@ -126,14 +124,14 @@ loop:	SWAPINIT(a, es);
 		while (pb <= pc && (r = cmp(pc, a)) >= 0) {
 			if (r == 0) {
 				swap_cnt = 1;
-				swap(pc, pd);
+				yswap(pc, pd);
 				pd -= es;
 			}
 			pc -= es;
 		}
 		if (pb > pc)
 			break;
-		swap(pb, pc);
+		yswap(pb, pc);
 		swap_cnt = 1;
 		pb += es;
 		pc -= es;
@@ -142,7 +140,7 @@ loop:	SWAPINIT(a, es);
 		for (pm = (char *) a + es; pm < (char *) a + n * es; pm += es)
 			for (pl = pm; pl > (char *) a && cmp(pl - es, pl) > 0;
 			     pl -= es)
-				swap(pl, pl - es);
+				yswap(pl, pl - es);
 		return;
 	}
 
@@ -151,9 +149,11 @@ loop:	SWAPINIT(a, es);
 	vecswap(a, pb - r, r);
 	r = min((long)(pd - pc), (long)(pn - pd - es));
 	vecswap(pb, pn - r, r);
-	if ((r = pb - pa) > es)
+	r = pb - pa;
+	if (r > es)
 		yaffs_qsort(a, r / es, es, cmp);
-	if ((r = pd - pc) > es) {
+	r = pd - pc;
+	if (r > es) {
 		/* Iterate rather than recurse to save stack space */
 		a = pn - r;
 		n = r / es;
diff --git a/fs/yaffs2/yaffs_qsort.h b/fs/yaffs2/yaffs_qsort.h
deleted file mode 100644
index 19083da51a..0000000000
--- a/fs/yaffs2/yaffs_qsort.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
- *
- * Copyright (C) 2002-2007 Aleph One Ltd.
- *   for Toby Churchill Ltd and Brightstar Engineering
- *
- * Created by Charles Manning <charles@aleph1.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License version 2.1 as
- * published by the Free Software Foundation.
- *
- * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
- */
-
-
-#ifndef __YAFFS_QSORT_H__
-#define __YAFFS_QSORT_H__
-
-extern void yaffs_qsort (void *const base, size_t total_elems, size_t size,
-		   int (*cmp)(const void *, const void *));
-
-#endif
diff --git a/fs/yaffs2/yaffs_ramdisk.h b/fs/yaffs2/yaffs_ramdisk.h
deleted file mode 100644
index 3cff8bee79..0000000000
--- a/fs/yaffs2/yaffs_ramdisk.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
- *
- * Copyright (C) 2002-2007 Aleph One Ltd.
- *   for Toby Churchill Ltd and Brightstar Engineering
- *
- * Created by Charles Manning <charles@aleph1.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License version 2.1 as
- * published by the Free Software Foundation.
- *
- * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
- */
-
-/*
- * yaffs_ramdisk.h: yaffs ram disk component
- */
-
-#ifndef __YAFFS_RAMDISK_H__
-#define __YAFFS_RAMDISK_H__
-
-
-#include "yaffs_guts.h"
-int yramdisk_EraseBlockInNAND(yaffs_Device *dev, int blockNumber);
-int yramdisk_WriteChunkWithTagsToNAND(yaffs_Device *dev,int chunkInNAND,const __u8 *data, yaffs_ExtendedTags *tags);
-int yramdisk_ReadChunkWithTagsFromNAND(yaffs_Device *dev,int chunkInNAND, __u8 *data, yaffs_ExtendedTags *tags);
-int yramdisk_EraseBlockInNAND(yaffs_Device *dev, int blockNumber);
-int yramdisk_InitialiseNAND(yaffs_Device *dev);
-int yramdisk_MarkNANDBlockBad(yaffs_Device *dev,int blockNumber);
-int yramdisk_QueryNANDBlock(yaffs_Device *dev, int blockNo, yaffs_BlockState *state, int *sequenceNumber);
-#endif
diff --git a/fs/yaffs2/yaffs_summary.c b/fs/yaffs2/yaffs_summary.c
new file mode 100644
index 0000000000..46e42f6d7d
--- /dev/null
+++ b/fs/yaffs2/yaffs_summary.c
@@ -0,0 +1,310 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2011 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* Summaries write the useful part of the tags for the chunks in a block into an
+ * an array which is written to the last n chunks of the block.
+ * Reading the summaries gives all the tags for the block in one read. Much
+ * faster.
+ *
+ * Chunks holding summaries are marked with tags making it look like
+ * they are part of a fake file.
+ *
+ * The summary could also be used during gc.
+ *
+ */
+
+#include "yaffs_summary.h"
+#include "yaffs_packedtags2.h"
+#include "yaffs_nand.h"
+#include "yaffs_getblockinfo.h"
+#include "yaffs_bitmap.h"
+
+/*
+ * The summary is built up in an array of summary tags.
+ * This gets written to the last one or two (maybe more) chunks in a block.
+ * A summary header is written as the first part of each chunk of summary data.
+ * The summary header must match or the summary is rejected.
+ */
+
+/* Summary tags don't need the sequence number because that is redundant. */
+struct yaffs_summary_tags {
+	unsigned obj_id;
+	unsigned chunk_id;
+	unsigned n_bytes;
+};
+
+/* Summary header */
+struct yaffs_summary_header {
+	unsigned version;	/* Must match current version */
+	unsigned block;		/* Must be this block */
+	unsigned seq;		/* Must be this sequence number */
+	unsigned sum;		/* Just add up all the bytes in the tags */
+};
+
+
+static void yaffs_summary_clear(struct yaffs_dev *dev)
+{
+	if (!dev->sum_tags)
+		return;
+	memset(dev->sum_tags, 0, dev->chunks_per_summary *
+		sizeof(struct yaffs_summary_tags));
+}
+
+
+void yaffs_summary_deinit(struct yaffs_dev *dev)
+{
+	kfree(dev->sum_tags);
+	dev->sum_tags = NULL;
+	kfree(dev->gc_sum_tags);
+	dev->gc_sum_tags = NULL;
+	dev->chunks_per_summary = 0;
+}
+
+int yaffs_summary_init(struct yaffs_dev *dev)
+{
+	int sum_bytes;
+	int chunks_used; /* Number of chunks used by summary */
+	int sum_tags_bytes;
+
+	sum_bytes = dev->param.chunks_per_block *
+			sizeof(struct yaffs_summary_tags);
+
+	chunks_used = (sum_bytes + dev->data_bytes_per_chunk - 1)/
+			(dev->data_bytes_per_chunk -
+				sizeof(struct yaffs_summary_header));
+
+	dev->chunks_per_summary = dev->param.chunks_per_block - chunks_used;
+	sum_tags_bytes = sizeof(struct yaffs_summary_tags) *
+				dev->chunks_per_summary;
+	dev->sum_tags = kmalloc(sum_tags_bytes, GFP_NOFS);
+	dev->gc_sum_tags = kmalloc(sum_tags_bytes, GFP_NOFS);
+	if (!dev->sum_tags || !dev->gc_sum_tags) {
+		yaffs_summary_deinit(dev);
+		return YAFFS_FAIL;
+	}
+
+	yaffs_summary_clear(dev);
+
+	return YAFFS_OK;
+}
+
+static unsigned yaffs_summary_sum(struct yaffs_dev *dev)
+{
+	u8 *sum_buffer = (u8 *)dev->sum_tags;
+	int i;
+	unsigned sum = 0;
+
+	i = sizeof(struct yaffs_summary_tags) *
+				dev->chunks_per_summary;
+	while (i > 0) {
+		sum += *sum_buffer;
+		sum_buffer++;
+		i--;
+	}
+
+	return sum;
+}
+
+static int yaffs_summary_write(struct yaffs_dev *dev, int blk)
+{
+	struct yaffs_ext_tags tags;
+	u8 *buffer;
+	u8 *sum_buffer = (u8 *)dev->sum_tags;
+	int n_bytes;
+	int chunk_in_nand;
+	int chunk_in_block;
+	int result;
+	int this_tx;
+	struct yaffs_summary_header hdr;
+	int sum_bytes_per_chunk = dev->data_bytes_per_chunk - sizeof(hdr);
+	struct yaffs_block_info *bi = yaffs_get_block_info(dev, blk);
+
+	buffer = yaffs_get_temp_buffer(dev);
+	n_bytes = sizeof(struct yaffs_summary_tags) *
+				dev->chunks_per_summary;
+	memset(&tags, 0, sizeof(struct yaffs_ext_tags));
+	tags.obj_id = YAFFS_OBJECTID_SUMMARY;
+	tags.chunk_id = 1;
+	chunk_in_block = dev->chunks_per_summary;
+	chunk_in_nand = dev->alloc_block * dev->param.chunks_per_block +
+						dev->chunks_per_summary;
+	hdr.version = YAFFS_SUMMARY_VERSION;
+	hdr.block = blk;
+	hdr.seq = bi->seq_number;
+	hdr.sum = yaffs_summary_sum(dev);
+
+	do {
+		this_tx = n_bytes;
+		if (this_tx > sum_bytes_per_chunk)
+			this_tx = sum_bytes_per_chunk;
+		memcpy(buffer, &hdr, sizeof(hdr));
+		memcpy(buffer + sizeof(hdr), sum_buffer, this_tx);
+		tags.n_bytes = this_tx + sizeof(hdr);
+		result = yaffs_wr_chunk_tags_nand(dev, chunk_in_nand,
+						buffer, &tags);
+
+		if (result != YAFFS_OK)
+			break;
+		yaffs_set_chunk_bit(dev, blk, chunk_in_block);
+		bi->pages_in_use++;
+		dev->n_free_chunks--;
+
+		n_bytes -= this_tx;
+		sum_buffer += this_tx;
+		chunk_in_nand++;
+		chunk_in_block++;
+		tags.chunk_id++;
+	} while (result == YAFFS_OK && n_bytes > 0);
+	yaffs_release_temp_buffer(dev, buffer);
+
+
+	if (result == YAFFS_OK)
+		bi->has_summary = 1;
+
+
+	return result;
+}
+
+int yaffs_summary_read(struct yaffs_dev *dev,
+			struct yaffs_summary_tags *st,
+			int blk)
+{
+	struct yaffs_ext_tags tags;
+	u8 *buffer;
+	u8 *sum_buffer = (u8 *)st;
+	int n_bytes;
+	int chunk_id;
+	int chunk_in_nand;
+	int chunk_in_block;
+	int result;
+	int this_tx;
+	struct yaffs_summary_header hdr;
+	struct yaffs_block_info *bi = yaffs_get_block_info(dev, blk);
+	int sum_bytes_per_chunk = dev->data_bytes_per_chunk - sizeof(hdr);
+
+	buffer = yaffs_get_temp_buffer(dev);
+	n_bytes = sizeof(struct yaffs_summary_tags) * dev->chunks_per_summary;
+	chunk_in_block = dev->chunks_per_summary;
+	chunk_in_nand = blk * dev->param.chunks_per_block +
+							dev->chunks_per_summary;
+	chunk_id = 1;
+	do {
+		this_tx = n_bytes;
+		if (this_tx > sum_bytes_per_chunk)
+			this_tx = sum_bytes_per_chunk;
+		result = yaffs_rd_chunk_tags_nand(dev, chunk_in_nand,
+						buffer, &tags);
+
+		if (tags.chunk_id != chunk_id ||
+			tags.obj_id != YAFFS_OBJECTID_SUMMARY ||
+			tags.chunk_used == 0 ||
+			tags.ecc_result > YAFFS_ECC_RESULT_FIXED ||
+			tags.n_bytes != (this_tx + sizeof(hdr)))
+				result = YAFFS_FAIL;
+		if (result != YAFFS_OK)
+			break;
+
+		if (st == dev->sum_tags) {
+			/* If we're scanning then update the block info */
+			yaffs_set_chunk_bit(dev, blk, chunk_in_block);
+			bi->pages_in_use++;
+		}
+		memcpy(&hdr, buffer, sizeof(hdr));
+		memcpy(sum_buffer, buffer + sizeof(hdr), this_tx);
+		n_bytes -= this_tx;
+		sum_buffer += this_tx;
+		chunk_in_nand++;
+		chunk_in_block++;
+		chunk_id++;
+	} while (result == YAFFS_OK && n_bytes > 0);
+	yaffs_release_temp_buffer(dev, buffer);
+
+	if (result == YAFFS_OK) {
+		/* Verify header */
+		if (hdr.version != YAFFS_SUMMARY_VERSION ||
+		    hdr.block != blk ||
+		    hdr.seq != bi->seq_number ||
+		    hdr.sum != yaffs_summary_sum(dev))
+			result = YAFFS_FAIL;
+	}
+
+	if (st == dev->sum_tags && result == YAFFS_OK)
+		bi->has_summary = 1;
+
+	return result;
+}
+
+int yaffs_summary_add(struct yaffs_dev *dev,
+			struct yaffs_ext_tags *tags,
+			int chunk_in_nand)
+{
+	struct yaffs_packed_tags2_tags_only tags_only;
+	struct yaffs_summary_tags *sum_tags;
+	int block_in_nand = chunk_in_nand / dev->param.chunks_per_block;
+	int chunk_in_block = chunk_in_nand % dev->param.chunks_per_block;
+
+	if (!dev->sum_tags)
+		return YAFFS_OK;
+
+	if (chunk_in_block >= 0 && chunk_in_block < dev->chunks_per_summary) {
+		yaffs_pack_tags2_tags_only(&tags_only, tags);
+		sum_tags = &dev->sum_tags[chunk_in_block];
+		sum_tags->chunk_id = tags_only.chunk_id;
+		sum_tags->n_bytes = tags_only.n_bytes;
+		sum_tags->obj_id = tags_only.obj_id;
+
+		if (chunk_in_block == dev->chunks_per_summary - 1) {
+			/* Time to write out the summary */
+			yaffs_summary_write(dev, block_in_nand);
+			yaffs_summary_clear(dev);
+			yaffs_skip_rest_of_block(dev);
+		}
+	}
+	return YAFFS_OK;
+}
+
+int yaffs_summary_fetch(struct yaffs_dev *dev,
+			struct yaffs_ext_tags *tags,
+			int chunk_in_block)
+{
+	struct yaffs_packed_tags2_tags_only tags_only;
+	struct yaffs_summary_tags *sum_tags;
+	if (chunk_in_block >= 0 && chunk_in_block < dev->chunks_per_summary) {
+		sum_tags = &dev->sum_tags[chunk_in_block];
+		tags_only.chunk_id = sum_tags->chunk_id;
+		tags_only.n_bytes = sum_tags->n_bytes;
+		tags_only.obj_id = sum_tags->obj_id;
+		yaffs_unpack_tags2_tags_only(tags, &tags_only);
+		return YAFFS_OK;
+	}
+	return YAFFS_FAIL;
+}
+
+void yaffs_summary_gc(struct yaffs_dev *dev, int blk)
+{
+	struct yaffs_block_info *bi = yaffs_get_block_info(dev, blk);
+	int i;
+
+	if (!bi->has_summary)
+		return;
+
+	for (i = dev->chunks_per_summary;
+	     i < dev->param.chunks_per_block;
+	     i++) {
+		if (yaffs_check_chunk_bit(dev, blk, i)) {
+			yaffs_clear_chunk_bit(dev, blk, i);
+			bi->pages_in_use--;
+			dev->n_free_chunks++;
+		}
+	}
+}
diff --git a/fs/yaffs2/yaffs_summary.h b/fs/yaffs2/yaffs_summary.h
new file mode 100644
index 0000000000..be141d0733
--- /dev/null
+++ b/fs/yaffs2/yaffs_summary.h
@@ -0,0 +1,37 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2011 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_SUMMARY_H__
+#define __YAFFS_SUMMARY_H__
+
+#include "yaffs_packedtags2.h"
+
+
+int yaffs_summary_init(struct yaffs_dev *dev);
+void yaffs_summary_deinit(struct yaffs_dev *dev);
+
+int yaffs_summary_add(struct yaffs_dev *dev,
+			struct yaffs_ext_tags *tags,
+			int chunk_in_block);
+int yaffs_summary_fetch(struct yaffs_dev *dev,
+			struct yaffs_ext_tags *tags,
+			int chunk_in_block);
+int yaffs_summary_read(struct yaffs_dev *dev,
+			struct yaffs_summary_tags *st,
+			int blk);
+void yaffs_summary_gc(struct yaffs_dev *dev, int blk);
+
+
+#endif
diff --git a/fs/yaffs2/yaffs_tagscompat.c b/fs/yaffs2/yaffs_tagscompat.c
index e872323b2f..9ac5896da3 100644
--- a/fs/yaffs2/yaffs_tagscompat.c
+++ b/fs/yaffs2/yaffs_tagscompat.c
@@ -1,7 +1,7 @@
 /*
  * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
  *
- * Copyright (C) 2002-2007 Aleph One Ltd.
+ * Copyright (C) 2002-2011 Aleph One Ltd.
  *   for Toby Churchill Ltd and Brightstar Engineering
  *
  * Created by Charles Manning <charles@aleph1.co.uk>
@@ -11,63 +11,27 @@
  * published by the Free Software Foundation.
  */
 
-/* XXX U-BOOT XXX */
-#include <common.h>
-
 #include "yaffs_guts.h"
 #include "yaffs_tagscompat.h"
 #include "yaffs_ecc.h"
+#include "yaffs_getblockinfo.h"
+#include "yaffs_trace.h"
+
+static void yaffs_handle_rd_data_error(struct yaffs_dev *dev, int nand_chunk);
 
-static void yaffs_HandleReadDataError(yaffs_Device * dev, int chunkInNAND);
-#ifdef NOTYET
-static void yaffs_CheckWrittenBlock(yaffs_Device * dev, int chunkInNAND);
-static void yaffs_HandleWriteChunkOk(yaffs_Device * dev, int chunkInNAND,
-				     const __u8 * data,
-				     const yaffs_Spare * spare);
-static void yaffs_HandleUpdateChunk(yaffs_Device * dev, int chunkInNAND,
-				    const yaffs_Spare * spare);
-static void yaffs_HandleWriteChunkError(yaffs_Device * dev, int chunkInNAND);
-#endif
-
-static const char yaffs_countBitsTable[256] = {
-	0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4,
-	1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
-	1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
-	2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
-	1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
-	2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
-	2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
-	3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
-	1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
-	2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
-	2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
-	3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
-	2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
-	3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
-	3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
-	4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8
-};
-
-int yaffs_CountBits(__u8 x)
-{
-	int retVal;
-	retVal = yaffs_countBitsTable[x];
-	return retVal;
-}
 
 /********** Tags ECC calculations  *********/
 
-void yaffs_CalcECC(const __u8 * data, yaffs_Spare * spare)
+void yaffs_calc_ecc(const u8 *data, struct yaffs_spare *spare)
 {
-	yaffs_ECCCalculate(data, spare->ecc1);
-	yaffs_ECCCalculate(&data[256], spare->ecc2);
+	yaffs_ecc_calc(data, spare->ecc1);
+	yaffs_ecc_calc(&data[256], spare->ecc2);
 }
 
-void yaffs_CalcTagsECC(yaffs_Tags * tags)
+void yaffs_calc_tags_ecc(struct yaffs_tags *tags)
 {
 	/* Calculate an ecc */
-
-	unsigned char *b = ((yaffs_TagsUnion *) tags)->asBytes;
+	unsigned char *b = ((union yaffs_tags_union *)tags)->as_bytes;
 	unsigned i, j;
 	unsigned ecc = 0;
 	unsigned bit = 0;
@@ -77,34 +41,31 @@ void yaffs_CalcTagsECC(yaffs_Tags * tags)
 	for (i = 0; i < 8; i++) {
 		for (j = 1; j & 0xff; j <<= 1) {
 			bit++;
-			if (b[i] & j) {
+			if (b[i] & j)
 				ecc ^= bit;
-			}
 		}
 	}
-
 	tags->ecc = ecc;
-
 }
 
-int yaffs_CheckECCOnTags(yaffs_Tags * tags)
+int yaffs_check_tags_ecc(struct yaffs_tags *tags)
 {
 	unsigned ecc = tags->ecc;
 
-	yaffs_CalcTagsECC(tags);
+	yaffs_calc_tags_ecc(tags);
 
 	ecc ^= tags->ecc;
 
 	if (ecc && ecc <= 64) {
 		/* TODO: Handle the failure better. Retire? */
-		unsigned char *b = ((yaffs_TagsUnion *) tags)->asBytes;
+		unsigned char *b = ((union yaffs_tags_union *)tags)->as_bytes;
 
 		ecc--;
 
 		b[ecc / 8] ^= (1 << (ecc & 7));
 
 		/* Now recvalc the ecc */
-		yaffs_CalcTagsECC(tags);
+		yaffs_calc_tags_ecc(tags);
 
 		return 1;	/* recovered error */
 	} else if (ecc) {
@@ -112,235 +73,202 @@ int yaffs_CheckECCOnTags(yaffs_Tags * tags)
 		/* TODO Need to do somethiong here */
 		return -1;	/* unrecovered error */
 	}
-
 	return 0;
 }
 
 /********** Tags **********/
 
-static void yaffs_LoadTagsIntoSpare(yaffs_Spare * sparePtr,
-				    yaffs_Tags * tagsPtr)
+static void yaffs_load_tags_to_spare(struct yaffs_spare *spare_ptr,
+				     struct yaffs_tags *tags_ptr)
 {
-	yaffs_TagsUnion *tu = (yaffs_TagsUnion *) tagsPtr;
-
-	yaffs_CalcTagsECC(tagsPtr);
-
-	sparePtr->tagByte0 = tu->asBytes[0];
-	sparePtr->tagByte1 = tu->asBytes[1];
-	sparePtr->tagByte2 = tu->asBytes[2];
-	sparePtr->tagByte3 = tu->asBytes[3];
-	sparePtr->tagByte4 = tu->asBytes[4];
-	sparePtr->tagByte5 = tu->asBytes[5];
-	sparePtr->tagByte6 = tu->asBytes[6];
-	sparePtr->tagByte7 = tu->asBytes[7];
+	union yaffs_tags_union *tu = (union yaffs_tags_union *)tags_ptr;
+
+	yaffs_calc_tags_ecc(tags_ptr);
+
+	spare_ptr->tb0 = tu->as_bytes[0];
+	spare_ptr->tb1 = tu->as_bytes[1];
+	spare_ptr->tb2 = tu->as_bytes[2];
+	spare_ptr->tb3 = tu->as_bytes[3];
+	spare_ptr->tb4 = tu->as_bytes[4];
+	spare_ptr->tb5 = tu->as_bytes[5];
+	spare_ptr->tb6 = tu->as_bytes[6];
+	spare_ptr->tb7 = tu->as_bytes[7];
 }
 
-static void yaffs_GetTagsFromSpare(yaffs_Device * dev, yaffs_Spare * sparePtr,
-				   yaffs_TagsUnion *tu)
+static void yaffs_get_tags_from_spare(struct yaffs_dev *dev,
+				      struct yaffs_spare *spare_ptr,
+				      struct yaffs_tags *tags_ptr)
 {
+	union yaffs_tags_union *tu = (union yaffs_tags_union *)tags_ptr;
 	int result;
 
-	tu->asBytes[0] = sparePtr->tagByte0;
-	tu->asBytes[1] = sparePtr->tagByte1;
-	tu->asBytes[2] = sparePtr->tagByte2;
-	tu->asBytes[3] = sparePtr->tagByte3;
-	tu->asBytes[4] = sparePtr->tagByte4;
-	tu->asBytes[5] = sparePtr->tagByte5;
-	tu->asBytes[6] = sparePtr->tagByte6;
-	tu->asBytes[7] = sparePtr->tagByte7;
-
-	result = yaffs_CheckECCOnTags(&tu->asTags);
-	if (result > 0) {
-		dev->tagsEccFixed++;
-	} else if (result < 0) {
-		dev->tagsEccUnfixed++;
-	}
+	tu->as_bytes[0] = spare_ptr->tb0;
+	tu->as_bytes[1] = spare_ptr->tb1;
+	tu->as_bytes[2] = spare_ptr->tb2;
+	tu->as_bytes[3] = spare_ptr->tb3;
+	tu->as_bytes[4] = spare_ptr->tb4;
+	tu->as_bytes[5] = spare_ptr->tb5;
+	tu->as_bytes[6] = spare_ptr->tb6;
+	tu->as_bytes[7] = spare_ptr->tb7;
+
+	result = yaffs_check_tags_ecc(tags_ptr);
+	if (result > 0)
+		dev->n_tags_ecc_fixed++;
+	else if (result < 0)
+		dev->n_tags_ecc_unfixed++;
 }
 
-static void yaffs_SpareInitialise(yaffs_Spare * spare)
+static void yaffs_spare_init(struct yaffs_spare *spare)
 {
-	memset(spare, 0xFF, sizeof(yaffs_Spare));
+	memset(spare, 0xff, sizeof(struct yaffs_spare));
 }
 
-static int yaffs_WriteChunkToNAND(struct yaffs_DeviceStruct *dev,
-				  int chunkInNAND, const __u8 * data,
-				  yaffs_Spare * spare)
+static int yaffs_wr_nand(struct yaffs_dev *dev,
+			 int nand_chunk, const u8 *data,
+			 struct yaffs_spare *spare)
 {
-	if (chunkInNAND < dev->startBlock * dev->nChunksPerBlock) {
-		T(YAFFS_TRACE_ERROR,
-		  (TSTR("**>> yaffs chunk %d is not valid" TENDSTR),
-		   chunkInNAND));
+	if (nand_chunk < dev->param.start_block * dev->param.chunks_per_block) {
+		yaffs_trace(YAFFS_TRACE_ERROR,
+			"**>> yaffs chunk %d is not valid",
+			nand_chunk);
 		return YAFFS_FAIL;
 	}
 
-	dev->nPageWrites++;
-	return dev->writeChunkToNAND(dev, chunkInNAND, data, spare);
+	return dev->param.write_chunk_fn(dev, nand_chunk, data, spare);
 }
 
-static int yaffs_ReadChunkFromNAND(struct yaffs_DeviceStruct *dev,
-				   int chunkInNAND,
-				   __u8 * data,
-				   yaffs_Spare * spare,
-				   yaffs_ECCResult * eccResult,
-				   int doErrorCorrection)
+static int yaffs_rd_chunk_nand(struct yaffs_dev *dev,
+			       int nand_chunk,
+			       u8 *data,
+			       struct yaffs_spare *spare,
+			       enum yaffs_ecc_result *ecc_result,
+			       int correct_errors)
 {
-	int retVal;
-	yaffs_Spare localSpare;
-
-	dev->nPageReads++;
+	int ret_val;
+	struct yaffs_spare local_spare;
 
-	if (!spare && data) {
+	if (!spare) {
 		/* If we don't have a real spare, then we use a local one. */
 		/* Need this for the calculation of the ecc */
-		spare = &localSpare;
+		spare = &local_spare;
 	}
 
-	if (!dev->useNANDECC) {
-		retVal = dev->readChunkFromNAND(dev, chunkInNAND, data, spare);
-		if (data && doErrorCorrection) {
+	if (!dev->param.use_nand_ecc) {
+		ret_val =
+		    dev->param.read_chunk_fn(dev, nand_chunk, data, spare);
+		if (data && correct_errors) {
 			/* Do ECC correction */
 			/* Todo handle any errors */
-			int eccResult1, eccResult2;
-			__u8 calcEcc[3];
-
-			yaffs_ECCCalculate(data, calcEcc);
-			eccResult1 =
-			    yaffs_ECCCorrect(data, spare->ecc1, calcEcc);
-			yaffs_ECCCalculate(&data[256], calcEcc);
-			eccResult2 =
-			    yaffs_ECCCorrect(&data[256], spare->ecc2, calcEcc);
-
-			if (eccResult1 > 0) {
-				T(YAFFS_TRACE_ERROR,
-				  (TSTR
-				   ("**>>yaffs ecc error fix performed on chunk %d:0"
-				    TENDSTR), chunkInNAND));
-				dev->eccFixed++;
-			} else if (eccResult1 < 0) {
-				T(YAFFS_TRACE_ERROR,
-				  (TSTR
-				   ("**>>yaffs ecc error unfixed on chunk %d:0"
-				    TENDSTR), chunkInNAND));
-				dev->eccUnfixed++;
+			int ecc_result1, ecc_result2;
+			u8 calc_ecc[3];
+
+			yaffs_ecc_calc(data, calc_ecc);
+			ecc_result1 =
+			    yaffs_ecc_correct(data, spare->ecc1, calc_ecc);
+			yaffs_ecc_calc(&data[256], calc_ecc);
+			ecc_result2 =
+			    yaffs_ecc_correct(&data[256], spare->ecc2,
+					      calc_ecc);
+
+			if (ecc_result1 > 0) {
+				yaffs_trace(YAFFS_TRACE_ERROR,
+					"**>>yaffs ecc error fix performed on chunk %d:0",
+					nand_chunk);
+				dev->n_ecc_fixed++;
+			} else if (ecc_result1 < 0) {
+				yaffs_trace(YAFFS_TRACE_ERROR,
+					"**>>yaffs ecc error unfixed on chunk %d:0",
+					nand_chunk);
+				dev->n_ecc_unfixed++;
 			}
 
-			if (eccResult2 > 0) {
-				T(YAFFS_TRACE_ERROR,
-				  (TSTR
-				   ("**>>yaffs ecc error fix performed on chunk %d:1"
-				    TENDSTR), chunkInNAND));
-				dev->eccFixed++;
-			} else if (eccResult2 < 0) {
-				T(YAFFS_TRACE_ERROR,
-				  (TSTR
-				   ("**>>yaffs ecc error unfixed on chunk %d:1"
-				    TENDSTR), chunkInNAND));
-				dev->eccUnfixed++;
+			if (ecc_result2 > 0) {
+				yaffs_trace(YAFFS_TRACE_ERROR,
+					"**>>yaffs ecc error fix performed on chunk %d:1",
+					nand_chunk);
+				dev->n_ecc_fixed++;
+			} else if (ecc_result2 < 0) {
+				yaffs_trace(YAFFS_TRACE_ERROR,
+					"**>>yaffs ecc error unfixed on chunk %d:1",
+					nand_chunk);
+				dev->n_ecc_unfixed++;
 			}
 
-			if (eccResult1 || eccResult2) {
+			if (ecc_result1 || ecc_result2) {
 				/* We had a data problem on this page */
-				yaffs_HandleReadDataError(dev, chunkInNAND);
+				yaffs_handle_rd_data_error(dev, nand_chunk);
 			}
 
-			if (eccResult1 < 0 || eccResult2 < 0)
-				*eccResult = YAFFS_ECC_RESULT_UNFIXED;
-			else if (eccResult1 > 0 || eccResult2 > 0)
-				*eccResult = YAFFS_ECC_RESULT_FIXED;
+			if (ecc_result1 < 0 || ecc_result2 < 0)
+				*ecc_result = YAFFS_ECC_RESULT_UNFIXED;
+			else if (ecc_result1 > 0 || ecc_result2 > 0)
+				*ecc_result = YAFFS_ECC_RESULT_FIXED;
 			else
-				*eccResult = YAFFS_ECC_RESULT_NO_ERROR;
+				*ecc_result = YAFFS_ECC_RESULT_NO_ERROR;
 		}
 	} else {
 		/* Must allocate enough memory for spare+2*sizeof(int) */
 		/* for ecc results from device. */
-		struct yaffs_NANDSpare nspare;
-		retVal =
-		    dev->readChunkFromNAND(dev, chunkInNAND, data,
-					   (yaffs_Spare *) & nspare);
-		memcpy(spare, &nspare, sizeof(yaffs_Spare));
-		if (data && doErrorCorrection) {
+		struct yaffs_nand_spare nspare;
+
+		memset(&nspare, 0, sizeof(nspare));
+
+		ret_val = dev->param.read_chunk_fn(dev, nand_chunk, data,
+						   (struct yaffs_spare *)
+						   &nspare);
+		memcpy(spare, &nspare, sizeof(struct yaffs_spare));
+		if (data && correct_errors) {
 			if (nspare.eccres1 > 0) {
-				T(YAFFS_TRACE_ERROR,
-				  (TSTR
-				   ("**>>mtd ecc error fix performed on chunk %d:0"
-				    TENDSTR), chunkInNAND));
+				yaffs_trace(YAFFS_TRACE_ERROR,
+					"**>>mtd ecc error fix performed on chunk %d:0",
+					nand_chunk);
 			} else if (nspare.eccres1 < 0) {
-				T(YAFFS_TRACE_ERROR,
-				  (TSTR
-				   ("**>>mtd ecc error unfixed on chunk %d:0"
-				    TENDSTR), chunkInNAND));
+				yaffs_trace(YAFFS_TRACE_ERROR,
+					"**>>mtd ecc error unfixed on chunk %d:0",
+					nand_chunk);
 			}
 
 			if (nspare.eccres2 > 0) {
-				T(YAFFS_TRACE_ERROR,
-				  (TSTR
-				   ("**>>mtd ecc error fix performed on chunk %d:1"
-				    TENDSTR), chunkInNAND));
+				yaffs_trace(YAFFS_TRACE_ERROR,
+					"**>>mtd ecc error fix performed on chunk %d:1",
+					nand_chunk);
 			} else if (nspare.eccres2 < 0) {
-				T(YAFFS_TRACE_ERROR,
-				  (TSTR
-				   ("**>>mtd ecc error unfixed on chunk %d:1"
-				    TENDSTR), chunkInNAND));
+				yaffs_trace(YAFFS_TRACE_ERROR,
+					"**>>mtd ecc error unfixed on chunk %d:1",
+					nand_chunk);
 			}
 
 			if (nspare.eccres1 || nspare.eccres2) {
 				/* We had a data problem on this page */
-				yaffs_HandleReadDataError(dev, chunkInNAND);
+				yaffs_handle_rd_data_error(dev, nand_chunk);
 			}
 
 			if (nspare.eccres1 < 0 || nspare.eccres2 < 0)
-				*eccResult = YAFFS_ECC_RESULT_UNFIXED;
+				*ecc_result = YAFFS_ECC_RESULT_UNFIXED;
 			else if (nspare.eccres1 > 0 || nspare.eccres2 > 0)
-				*eccResult = YAFFS_ECC_RESULT_FIXED;
+				*ecc_result = YAFFS_ECC_RESULT_FIXED;
 			else
-				*eccResult = YAFFS_ECC_RESULT_NO_ERROR;
+				*ecc_result = YAFFS_ECC_RESULT_NO_ERROR;
 
 		}
 	}
-	return retVal;
+	return ret_val;
 }
 
-#ifdef NOTYET
-static int yaffs_CheckChunkErased(struct yaffs_DeviceStruct *dev,
-				  int chunkInNAND)
-{
-
-	static int init = 0;
-	static __u8 cmpbuf[YAFFS_BYTES_PER_CHUNK];
-	static __u8 data[YAFFS_BYTES_PER_CHUNK];
-	/* Might as well always allocate the larger size for */
-	/* dev->useNANDECC == true; */
-	static __u8 spare[sizeof(struct yaffs_NANDSpare)];
-
-	dev->readChunkFromNAND(dev, chunkInNAND, data, (yaffs_Spare *) spare);
-
-	if (!init) {
-		memset(cmpbuf, 0xff, YAFFS_BYTES_PER_CHUNK);
-		init = 1;
-	}
-
-	if (memcmp(cmpbuf, data, YAFFS_BYTES_PER_CHUNK))
-		return YAFFS_FAIL;
-	if (memcmp(cmpbuf, spare, 16))
-		return YAFFS_FAIL;
-
-	return YAFFS_OK;
-
-}
-#endif
-
 /*
  * Functions for robustisizing
  */
 
-static void yaffs_HandleReadDataError(yaffs_Device * dev, int chunkInNAND)
+static void yaffs_handle_rd_data_error(struct yaffs_dev *dev, int nand_chunk)
 {
-	int blockInNAND = chunkInNAND / dev->nChunksPerBlock;
+	int flash_block = nand_chunk / dev->param.chunks_per_block;
 
 	/* Mark the block for retirement */
-	yaffs_GetBlockInfo(dev, blockInNAND)->needsRetiring = 1;
-	T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS,
-	  (TSTR("**>>Block %d marked for retirement" TENDSTR), blockInNAND));
+	yaffs_get_block_info(dev, flash_block + dev->block_offset)->
+		needs_retiring = 1;
+	yaffs_trace(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS,
+		"**>>Block %d marked for retirement",
+		flash_block);
 
 	/* TODO:
 	 * Just do a garbage collection on the affected block
@@ -349,184 +277,131 @@ static void yaffs_HandleReadDataError(yaffs_Device * dev, int chunkInNAND)
 	 */
 }
 
-#ifdef NOTYET
-static void yaffs_CheckWrittenBlock(yaffs_Device * dev, int chunkInNAND)
+int yaffs_tags_compat_wr(struct yaffs_dev *dev,
+			 int nand_chunk,
+			 const u8 *data, const struct yaffs_ext_tags *ext_tags)
 {
-}
+	struct yaffs_spare spare;
+	struct yaffs_tags tags;
 
-static void yaffs_HandleWriteChunkOk(yaffs_Device * dev, int chunkInNAND,
-				     const __u8 * data,
-				     const yaffs_Spare * spare)
-{
-}
+	yaffs_spare_init(&spare);
 
-static void yaffs_HandleUpdateChunk(yaffs_Device * dev, int chunkInNAND,
-				    const yaffs_Spare * spare)
-{
-}
+	if (ext_tags->is_deleted)
+		spare.page_status = 0;
+	else {
+		tags.obj_id = ext_tags->obj_id;
+		tags.chunk_id = ext_tags->chunk_id;
 
-static void yaffs_HandleWriteChunkError(yaffs_Device * dev, int chunkInNAND)
-{
-	int blockInNAND = chunkInNAND / dev->nChunksPerBlock;
-
-	/* Mark the block for retirement */
-	yaffs_GetBlockInfo(dev, blockInNAND)->needsRetiring = 1;
-	/* Delete the chunk */
-	yaffs_DeleteChunk(dev, chunkInNAND, 1, __LINE__);
-}
-
-static int yaffs_VerifyCompare(const __u8 * d0, const __u8 * d1,
-			       const yaffs_Spare * s0, const yaffs_Spare * s1)
-{
-
-	if (memcmp(d0, d1, YAFFS_BYTES_PER_CHUNK) != 0 ||
-	    s0->tagByte0 != s1->tagByte0 ||
-	    s0->tagByte1 != s1->tagByte1 ||
-	    s0->tagByte2 != s1->tagByte2 ||
-	    s0->tagByte3 != s1->tagByte3 ||
-	    s0->tagByte4 != s1->tagByte4 ||
-	    s0->tagByte5 != s1->tagByte5 ||
-	    s0->tagByte6 != s1->tagByte6 ||
-	    s0->tagByte7 != s1->tagByte7 ||
-	    s0->ecc1[0] != s1->ecc1[0] ||
-	    s0->ecc1[1] != s1->ecc1[1] ||
-	    s0->ecc1[2] != s1->ecc1[2] ||
-	    s0->ecc2[0] != s1->ecc2[0] ||
-	    s0->ecc2[1] != s1->ecc2[1] || s0->ecc2[2] != s1->ecc2[2]) {
-		return 0;
-	}
+		tags.n_bytes_lsb = ext_tags->n_bytes & (1024 - 1);
 
-	return 1;
-}
-#endif				/* NOTYET */
-
-int yaffs_TagsCompatabilityWriteChunkWithTagsToNAND(yaffs_Device * dev,
-						    int chunkInNAND,
-						    const __u8 * data,
-						    const yaffs_ExtendedTags *
-						    eTags)
-{
-	yaffs_Spare spare;
-	yaffs_Tags tags;
-
-	yaffs_SpareInitialise(&spare);
+		if (dev->data_bytes_per_chunk >= 1024)
+			tags.n_bytes_msb = (ext_tags->n_bytes >> 10) & 3;
+		else
+			tags.n_bytes_msb = 3;
 
-	if (eTags->chunkDeleted) {
-		spare.pageStatus = 0;
-	} else {
-		tags.objectId = eTags->objectId;
-		tags.chunkId = eTags->chunkId;
-		tags.byteCount = eTags->byteCount;
-		tags.serialNumber = eTags->serialNumber;
+		tags.serial_number = ext_tags->serial_number;
 
-		if (!dev->useNANDECC && data) {
-			yaffs_CalcECC(data, &spare);
-		}
-		yaffs_LoadTagsIntoSpare(&spare, &tags);
+		if (!dev->param.use_nand_ecc && data)
+			yaffs_calc_ecc(data, &spare);
 
+		yaffs_load_tags_to_spare(&spare, &tags);
 	}
-
-	return yaffs_WriteChunkToNAND(dev, chunkInNAND, data, &spare);
+	return yaffs_wr_nand(dev, nand_chunk, data, &spare);
 }
 
-int yaffs_TagsCompatabilityReadChunkWithTagsFromNAND(yaffs_Device * dev,
-						     int chunkInNAND,
-						     __u8 * data,
-						     yaffs_ExtendedTags * eTags)
+int yaffs_tags_compat_rd(struct yaffs_dev *dev,
+			 int nand_chunk,
+			 u8 *data, struct yaffs_ext_tags *ext_tags)
 {
-
-	yaffs_Spare spare;
-	yaffs_TagsUnion tags;
-	yaffs_ECCResult eccResult;
-
-	static yaffs_Spare spareFF;
+	struct yaffs_spare spare;
+	struct yaffs_tags tags;
+	enum yaffs_ecc_result ecc_result = YAFFS_ECC_RESULT_UNKNOWN;
+	static struct yaffs_spare spare_ff;
 	static int init;
+	int deleted;
 
 	if (!init) {
-		memset(&spareFF, 0xFF, sizeof(spareFF));
+		memset(&spare_ff, 0xff, sizeof(spare_ff));
 		init = 1;
 	}
 
-	if (yaffs_ReadChunkFromNAND
-	    (dev, chunkInNAND, data, &spare, &eccResult, 1)) {
-		/* eTags may be NULL */
-		if (eTags) {
-
-			int deleted =
-			    (yaffs_CountBits(spare.pageStatus) < 7) ? 1 : 0;
-
-			eTags->chunkDeleted = deleted;
-			eTags->eccResult = eccResult;
-			eTags->blockBad = 0;	/* We're reading it */
-			/* therefore it is not a bad block */
-			eTags->chunkUsed =
-			    (memcmp(&spareFF, &spare, sizeof(spareFF)) !=
-			     0) ? 1 : 0;
-
-			if (eTags->chunkUsed) {
-				yaffs_GetTagsFromSpare(dev, &spare, &tags);
-
-				eTags->objectId = tags.asTags.objectId;
-				eTags->chunkId = tags.asTags.chunkId;
-				eTags->byteCount = tags.asTags.byteCount;
-				eTags->serialNumber = tags.asTags.serialNumber;
-			}
-		}
+	if (!yaffs_rd_chunk_nand(dev, nand_chunk,
+					data, &spare, &ecc_result, 1))
+		return YAFFS_FAIL;
 
+	/* ext_tags may be NULL */
+	if (!ext_tags)
 		return YAFFS_OK;
-	} else {
-		return YAFFS_FAIL;
+
+	deleted = (hweight8(spare.page_status) < 7) ? 1 : 0;
+
+	ext_tags->is_deleted = deleted;
+	ext_tags->ecc_result = ecc_result;
+	ext_tags->block_bad = 0;	/* We're reading it */
+	/* therefore it is not a bad block */
+	ext_tags->chunk_used =
+		memcmp(&spare_ff, &spare, sizeof(spare_ff)) ? 1 : 0;
+
+	if (ext_tags->chunk_used) {
+		yaffs_get_tags_from_spare(dev, &spare, &tags);
+		ext_tags->obj_id = tags.obj_id;
+		ext_tags->chunk_id = tags.chunk_id;
+		ext_tags->n_bytes = tags.n_bytes_lsb;
+
+		if (dev->data_bytes_per_chunk >= 1024)
+			ext_tags->n_bytes |=
+				(((unsigned)tags.n_bytes_msb) << 10);
+
+		ext_tags->serial_number = tags.serial_number;
 	}
+
+	return YAFFS_OK;
 }
 
-int yaffs_TagsCompatabilityMarkNANDBlockBad(struct yaffs_DeviceStruct *dev,
-					    int blockInNAND)
+int yaffs_tags_compat_mark_bad(struct yaffs_dev *dev, int flash_block)
 {
+	struct yaffs_spare spare;
 
-	yaffs_Spare spare;
-
-	memset(&spare, 0xff, sizeof(yaffs_Spare));
+	memset(&spare, 0xff, sizeof(struct yaffs_spare));
 
-	spare.blockStatus = 'Y';
+	spare.block_status = 'Y';
 
-	yaffs_WriteChunkToNAND(dev, blockInNAND * dev->nChunksPerBlock, NULL,
-			       &spare);
-	yaffs_WriteChunkToNAND(dev, blockInNAND * dev->nChunksPerBlock + 1,
-			       NULL, &spare);
+	yaffs_wr_nand(dev, flash_block * dev->param.chunks_per_block, NULL,
+		      &spare);
+	yaffs_wr_nand(dev, flash_block * dev->param.chunks_per_block + 1,
+		      NULL, &spare);
 
 	return YAFFS_OK;
-
 }
 
-int yaffs_TagsCompatabilityQueryNANDBlock(struct yaffs_DeviceStruct *dev,
-					  int blockNo, yaffs_BlockState *
-					  state,
-					  int *sequenceNumber)
+int yaffs_tags_compat_query_block(struct yaffs_dev *dev,
+				  int block_no,
+				  enum yaffs_block_state *state,
+				  u32 *seq_number)
 {
-
-	yaffs_Spare spare0, spare1;
-	static yaffs_Spare spareFF;
+	struct yaffs_spare spare0, spare1;
+	static struct yaffs_spare spare_ff;
 	static int init;
-	yaffs_ECCResult dummy;
+	enum yaffs_ecc_result dummy;
 
 	if (!init) {
-		memset(&spareFF, 0xFF, sizeof(spareFF));
+		memset(&spare_ff, 0xff, sizeof(spare_ff));
 		init = 1;
 	}
 
-	*sequenceNumber = 0;
+	*seq_number = 0;
 
-	yaffs_ReadChunkFromNAND(dev, blockNo * dev->nChunksPerBlock, NULL,
-				&spare0, &dummy, 1);
-	yaffs_ReadChunkFromNAND(dev, blockNo * dev->nChunksPerBlock + 1, NULL,
-				&spare1, &dummy, 1);
+	yaffs_rd_chunk_nand(dev, block_no * dev->param.chunks_per_block, NULL,
+			    &spare0, &dummy, 1);
+	yaffs_rd_chunk_nand(dev, block_no * dev->param.chunks_per_block + 1,
+			    NULL, &spare1, &dummy, 1);
 
-	if (yaffs_CountBits(spare0.blockStatus & spare1.blockStatus) < 7)
+	if (hweight8(spare0.block_status & spare1.block_status) < 7)
 		*state = YAFFS_BLOCK_STATE_DEAD;
-	else if (memcmp(&spareFF, &spare0, sizeof(spareFF)) == 0)
+	else if (memcmp(&spare_ff, &spare0, sizeof(spare_ff)) == 0)
 		*state = YAFFS_BLOCK_STATE_EMPTY;
 	else
-		*state = YAFFS_BLOCK_STATE_NEEDS_SCANNING;
+		*state = YAFFS_BLOCK_STATE_NEEDS_SCAN;
 
 	return YAFFS_OK;
 }
diff --git a/fs/yaffs2/yaffs_tagscompat.h b/fs/yaffs2/yaffs_tagscompat.h
index a61e3ba14f..b3c6655772 100644
--- a/fs/yaffs2/yaffs_tagscompat.h
+++ b/fs/yaffs2/yaffs_tagscompat.h
@@ -1,7 +1,7 @@
 /*
  * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
  *
- * Copyright (C) 2002-2007 Aleph One Ltd.
+ * Copyright (C) 2002-2011 Aleph One Ltd.
  *   for Toby Churchill Ltd and Brightstar Engineering
  *
  * Created by Charles Manning <charles@aleph1.co.uk>
@@ -17,24 +17,20 @@
 #define __YAFFS_TAGSCOMPAT_H__
 
 #include "yaffs_guts.h"
-int yaffs_TagsCompatabilityWriteChunkWithTagsToNAND(yaffs_Device * dev,
-						    int chunkInNAND,
-						    const __u8 * data,
-						    const yaffs_ExtendedTags *
-						    tags);
-int yaffs_TagsCompatabilityReadChunkWithTagsFromNAND(yaffs_Device * dev,
-						     int chunkInNAND,
-						     __u8 * data,
-						     yaffs_ExtendedTags *
-						     tags);
-int yaffs_TagsCompatabilityMarkNANDBlockBad(struct yaffs_DeviceStruct *dev,
-					    int blockNo);
-int yaffs_TagsCompatabilityQueryNANDBlock(struct yaffs_DeviceStruct *dev,
-					  int blockNo, yaffs_BlockState *
-					  state, int *sequenceNumber);
+int yaffs_tags_compat_wr(struct yaffs_dev *dev,
+			 int nand_chunk,
+			 const u8 *data, const struct yaffs_ext_tags *tags);
+int yaffs_tags_compat_rd(struct yaffs_dev *dev,
+			 int nand_chunk,
+			 u8 *data, struct yaffs_ext_tags *tags);
+int yaffs_tags_compat_mark_bad(struct yaffs_dev *dev, int block_no);
+int yaffs_tags_compat_query_block(struct yaffs_dev *dev,
+				  int block_no,
+				  enum yaffs_block_state *state,
+				  u32 *seq_number);
 
-void yaffs_CalcTagsECC(yaffs_Tags * tags);
-int yaffs_CheckECCOnTags(yaffs_Tags * tags);
-int yaffs_CountBits(__u8 byte);
+void yaffs_calc_tags_ecc(struct yaffs_tags *tags);
+int yaffs_check_tags_ecc(struct yaffs_tags *tags);
+int yaffs_count_bits(u8 byte);
 
 #endif
diff --git a/fs/yaffs2/yaffs_tagsvalidity.c b/fs/yaffs2/yaffs_tagsvalidity.c
deleted file mode 100644
index f588d3aa21..0000000000
--- a/fs/yaffs2/yaffs_tagsvalidity.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
- *
- * Copyright (C) 2002-2007 Aleph One Ltd.
- *   for Toby Churchill Ltd and Brightstar Engineering
- *
- * Created by Charles Manning <charles@aleph1.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/* XXX U-BOOT XXX */
-#include <common.h>
-
-#include "yaffs_tagsvalidity.h"
-
-void yaffs_InitialiseTags(yaffs_ExtendedTags * tags)
-{
-	memset(tags, 0, sizeof(yaffs_ExtendedTags));
-	tags->validMarker0 = 0xAAAAAAAA;
-	tags->validMarker1 = 0x55555555;
-}
-
-int yaffs_ValidateTags(yaffs_ExtendedTags * tags)
-{
-	return (tags->validMarker0 == 0xAAAAAAAA &&
-		tags->validMarker1 == 0x55555555);
-
-}
diff --git a/fs/yaffs2/yaffs_trace.h b/fs/yaffs2/yaffs_trace.h
new file mode 100644
index 0000000000..fd26054d39
--- /dev/null
+++ b/fs/yaffs2/yaffs_trace.h
@@ -0,0 +1,57 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2011 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YTRACE_H__
+#define __YTRACE_H__
+
+extern unsigned int yaffs_trace_mask;
+extern unsigned int yaffs_wr_attempts;
+
+/*
+ * Tracing flags.
+ * The flags masked in YAFFS_TRACE_ALWAYS are always traced.
+ */
+
+#define YAFFS_TRACE_OS			0x00000002
+#define YAFFS_TRACE_ALLOCATE		0x00000004
+#define YAFFS_TRACE_SCAN		0x00000008
+#define YAFFS_TRACE_BAD_BLOCKS		0x00000010
+#define YAFFS_TRACE_ERASE		0x00000020
+#define YAFFS_TRACE_GC			0x00000040
+#define YAFFS_TRACE_WRITE		0x00000080
+#define YAFFS_TRACE_TRACING		0x00000100
+#define YAFFS_TRACE_DELETION		0x00000200
+#define YAFFS_TRACE_BUFFERS		0x00000400
+#define YAFFS_TRACE_NANDACCESS		0x00000800
+#define YAFFS_TRACE_GC_DETAIL		0x00001000
+#define YAFFS_TRACE_SCAN_DEBUG		0x00002000
+#define YAFFS_TRACE_MTD			0x00004000
+#define YAFFS_TRACE_CHECKPOINT		0x00008000
+
+#define YAFFS_TRACE_VERIFY		0x00010000
+#define YAFFS_TRACE_VERIFY_NAND		0x00020000
+#define YAFFS_TRACE_VERIFY_FULL		0x00040000
+#define YAFFS_TRACE_VERIFY_ALL		0x000f0000
+
+#define YAFFS_TRACE_SYNC		0x00100000
+#define YAFFS_TRACE_BACKGROUND		0x00200000
+#define YAFFS_TRACE_LOCK		0x00400000
+#define YAFFS_TRACE_MOUNT		0x00800000
+
+#define YAFFS_TRACE_ERROR		0x40000000
+#define YAFFS_TRACE_BUG			0x80000000
+#define YAFFS_TRACE_ALWAYS		0xf0000000
+
+#endif
diff --git a/fs/yaffs2/yaffs_uboot_glue.c b/fs/yaffs2/yaffs_uboot_glue.c
new file mode 100644
index 0000000000..e113e4039e
--- /dev/null
+++ b/fs/yaffs2/yaffs_uboot_glue.c
@@ -0,0 +1,464 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2007 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * yaffscfg.c  The configuration for the "direct" use of yaffs.
+ *
+ * This is set up for u-boot.
+ *
+ * This version now uses the ydevconfig mechanism to set up partitions.
+ */
+
+#include <common.h>
+
+#include <config.h>
+#include "nand.h"
+#include "yaffscfg.h"
+#include "yaffsfs.h"
+#include "yaffs_packedtags2.h"
+#include "yaffs_mtdif.h"
+#include "yaffs_mtdif2.h"
+#if 0
+#include <errno.h>
+#else
+#include "malloc.h"
+#endif
+
+unsigned yaffs_trace_mask = 0x0; /* Disable logging */
+static int yaffs_errno;
+
+
+void yaffs_bug_fn(const char *fn, int n)
+{
+	printf("yaffs bug at %s:%d\n", fn, n);
+}
+
+void *yaffsfs_malloc(size_t x)
+{
+	return malloc(x);
+}
+
+void yaffsfs_free(void *x)
+{
+	free(x);
+}
+
+void yaffsfs_SetError(int err)
+{
+	yaffs_errno = err;
+}
+
+int yaffsfs_GetLastError(void)
+{
+	return yaffs_errno;
+}
+
+
+int yaffsfs_GetError(void)
+{
+	return yaffs_errno;
+}
+
+void yaffsfs_Lock(void)
+{
+}
+
+void yaffsfs_Unlock(void)
+{
+}
+
+__u32 yaffsfs_CurrentTime(void)
+{
+	return 0;
+}
+
+void *yaffs_malloc(size_t size)
+{
+	return malloc(size);
+}
+
+void yaffs_free(void *ptr)
+{
+	free(ptr);
+}
+
+void yaffsfs_LocalInitialisation(void)
+{
+	/* No locking used */
+}
+
+
+static const char *yaffs_file_type_str(struct yaffs_stat *stat)
+{
+	switch (stat->st_mode & S_IFMT) {
+	case S_IFREG: return "regular file";
+	case S_IFDIR: return "directory";
+	case S_IFLNK: return "symlink";
+	default: return "unknown";
+	}
+}
+
+static const char *yaffs_error_str(void)
+{
+	int error = yaffsfs_GetLastError();
+
+	if (error < 0)
+		error = -error;
+
+	switch (error) {
+	case EBUSY: return "Busy";
+	case ENODEV: return "No such device";
+	case EINVAL: return "Invalid parameter";
+	case ENFILE: return "Too many open files";
+	case EBADF:  return "Bad handle";
+	case EACCES: return "Wrong permissions";
+	case EXDEV:  return "Not on same device";
+	case ENOENT: return "No such entry";
+	case ENOSPC: return "Device full";
+	case EROFS:  return "Read only file system";
+	case ERANGE: return "Range error";
+	case ENOTEMPTY: return "Not empty";
+	case ENAMETOOLONG: return "Name too long";
+	case ENOMEM: return "Out of memory";
+	case EFAULT: return "Fault";
+	case EEXIST: return "Name exists";
+	case ENOTDIR: return "Not a directory";
+	case EISDIR: return "Not permitted on a directory";
+	case ELOOP:  return "Symlink loop";
+	case 0: return "No error";
+	default: return "Unknown error";
+	}
+}
+
+extern nand_info_t nand_info[];
+
+void cmd_yaffs_tracemask(unsigned set, unsigned mask)
+{
+	if (set)
+		yaffs_trace_mask = mask;
+
+	printf("yaffs trace mask: %08x\n", yaffs_trace_mask);
+}
+
+static int yaffs_regions_overlap(int a, int b, int x, int y)
+{
+	return	(a <= x && x <= b) ||
+		(a <= y && y <= b) ||
+		(x <= a && a <= y) ||
+		(x <= b && b <= y);
+}
+
+void cmd_yaffs_devconfig(char *_mp, int flash_dev,
+			int start_block, int end_block)
+{
+	struct mtd_info *mtd = NULL;
+	struct yaffs_dev *dev = NULL;
+	struct yaffs_dev *chk;
+	char *mp = NULL;
+	struct nand_chip *chip;
+
+	dev = calloc(1, sizeof(*dev));
+	mp = strdup(_mp);
+
+	mtd = &nand_info[flash_dev];
+
+	if (!dev || !mp) {
+		/* Alloc error */
+		printf("Failed to allocate memory\n");
+		goto err;
+	}
+
+	if (flash_dev >= CONFIG_SYS_MAX_NAND_DEVICE) {
+		printf("Flash device invalid\n");
+		goto err;
+	}
+
+	if (end_block == 0)
+		end_block = mtd->size / mtd->erasesize - 1;
+
+	if (end_block < start_block) {
+		printf("Bad start/end\n");
+		goto err;
+	}
+
+	chip =  mtd->priv;
+
+	/* Check for any conflicts */
+	yaffs_dev_rewind();
+	while (1) {
+		chk = yaffs_next_dev();
+		if (!chk)
+			break;
+		if (strcmp(chk->param.name, mp) == 0) {
+			printf("Mount point name already used\n");
+			goto err;
+		}
+		if (chk->driver_context == mtd &&
+			yaffs_regions_overlap(
+				chk->param.start_block, chk->param.end_block,
+				start_block, end_block)) {
+			printf("Region overlaps with partition %s\n",
+				chk->param.name);
+			goto err;
+		}
+
+	}
+
+	/* Seems sane, so configure */
+	memset(dev, 0, sizeof(*dev));
+	dev->param.name = mp;
+	dev->driver_context = mtd;
+	dev->param.start_block = start_block;
+	dev->param.end_block = end_block;
+	dev->param.chunks_per_block = mtd->erasesize / mtd->writesize;
+	dev->param.total_bytes_per_chunk = mtd->writesize;
+	dev->param.is_yaffs2 = 1;
+	dev->param.use_nand_ecc = 1;
+	dev->param.n_reserved_blocks = 5;
+	if (chip->ecc.layout->oobavail < sizeof(struct yaffs_packed_tags2))
+		dev->param.inband_tags = 1;
+	dev->param.n_caches = 10;
+	dev->param.write_chunk_tags_fn = nandmtd2_write_chunk_tags;
+	dev->param.read_chunk_tags_fn = nandmtd2_read_chunk_tags;
+	dev->param.erase_fn = nandmtd_EraseBlockInNAND;
+	dev->param.initialise_flash_fn = nandmtd_InitialiseNAND;
+	dev->param.bad_block_fn = nandmtd2_MarkNANDBlockBad;
+	dev->param.query_block_fn = nandmtd2_QueryNANDBlock;
+
+	yaffs_add_device(dev);
+
+	printf("Configures yaffs mount %s: dev %d start block %d, end block %d %s\n",
+		mp, flash_dev, start_block, end_block,
+		dev->param.inband_tags ? "using inband tags" : "");
+	return;
+
+err:
+	free(dev);
+	free(mp);
+}
+
+void cmd_yaffs_dev_ls(void)
+{
+	struct yaffs_dev *dev;
+	int flash_dev;
+	int free_space;
+
+	yaffs_dev_rewind();
+
+	while (1) {
+		dev = yaffs_next_dev();
+		if (!dev)
+			return;
+		flash_dev =
+			((unsigned) dev->driver_context - (unsigned) nand_info)/
+				sizeof(nand_info[0]);
+		printf("%-10s %5d 0x%05x 0x%05x %s",
+			dev->param.name, flash_dev,
+			dev->param.start_block, dev->param.end_block,
+			dev->param.inband_tags ? "using inband tags, " : "");
+
+		free_space = yaffs_freespace(dev->param.name);
+		if (free_space < 0)
+			printf("not mounted\n");
+		else
+			printf("free 0x%x\n", free_space);
+
+	}
+}
+
+void make_a_file(char *yaffsName, char bval, int sizeOfFile)
+{
+	int outh;
+	int i;
+	unsigned char buffer[100];
+
+	outh = yaffs_open(yaffsName,
+				O_CREAT | O_RDWR | O_TRUNC,
+				S_IREAD | S_IWRITE);
+	if (outh < 0) {
+		printf("Error opening file: %d. %s\n", outh, yaffs_error_str());
+		return;
+	}
+
+	memset(buffer, bval, 100);
+
+	do {
+		i = sizeOfFile;
+		if (i > 100)
+			i = 100;
+		sizeOfFile -= i;
+
+		yaffs_write(outh, buffer, i);
+
+	} while (sizeOfFile > 0);
+
+
+	yaffs_close(outh);
+}
+
+void read_a_file(char *fn)
+{
+	int h;
+	int i = 0;
+	unsigned char b;
+
+	h = yaffs_open(fn, O_RDWR, 0);
+	if (h < 0) {
+		printf("File not found\n");
+		return;
+	}
+
+	while (yaffs_read(h, &b, 1) > 0) {
+		printf("%02x ", b);
+		i++;
+		if (i > 32) {
+			printf("\n");
+			i = 0;;
+		}
+	}
+	printf("\n");
+	yaffs_close(h);
+}
+
+void cmd_yaffs_mount(char *mp)
+{
+	int retval = yaffs_mount(mp);
+	if (retval < 0)
+		printf("Error mounting %s, return value: %d, %s\n", mp,
+			yaffsfs_GetError(), yaffs_error_str());
+}
+
+
+void cmd_yaffs_umount(char *mp)
+{
+	if (yaffs_unmount(mp) == -1)
+		printf("Error umounting %s, return value: %d, %s\n", mp,
+			yaffsfs_GetError(), yaffs_error_str());
+}
+
+void cmd_yaffs_write_file(char *yaffsName, char bval, int sizeOfFile)
+{
+	make_a_file(yaffsName, bval, sizeOfFile);
+}
+
+
+void cmd_yaffs_read_file(char *fn)
+{
+	read_a_file(fn);
+}
+
+
+void cmd_yaffs_mread_file(char *fn, char *addr)
+{
+	int h;
+	struct yaffs_stat s;
+
+	yaffs_stat(fn, &s);
+
+	printf("Copy %s to 0x%p... ", fn, addr);
+	h = yaffs_open(fn, O_RDWR, 0);
+	if (h < 0) {
+		printf("File not found\n");
+		return;
+	}
+
+	yaffs_read(h, addr, (int)s.st_size);
+	printf("\t[DONE]\n");
+
+	yaffs_close(h);
+}
+
+
+void cmd_yaffs_mwrite_file(char *fn, char *addr, int size)
+{
+	int outh;
+
+	outh = yaffs_open(fn, O_CREAT | O_RDWR | O_TRUNC, S_IREAD | S_IWRITE);
+	if (outh < 0)
+		printf("Error opening file: %d, %s\n", outh, yaffs_error_str());
+
+	yaffs_write(outh, addr, size);
+
+	yaffs_close(outh);
+}
+
+
+void cmd_yaffs_ls(const char *mountpt, int longlist)
+{
+	int i;
+	yaffs_DIR *d;
+	struct yaffs_dirent *de;
+	struct yaffs_stat stat;
+	char tempstr[255];
+
+	d = yaffs_opendir(mountpt);
+
+	if (!d) {
+		printf("opendir failed, %s\n", yaffs_error_str());
+		return;
+	}
+
+	for (i = 0; (de = yaffs_readdir(d)) != NULL; i++) {
+		if (longlist) {
+			sprintf(tempstr, "%s/%s", mountpt, de->d_name);
+			yaffs_lstat(tempstr, &stat);
+			printf("%-25s\t%7ld",
+					de->d_name,
+					(long)stat.st_size);
+			printf(" %5d %s\n",
+					stat.st_ino,
+					yaffs_file_type_str(&stat));
+		} else {
+			printf("%s\n", de->d_name);
+		}
+	}
+
+	yaffs_closedir(d);
+}
+
+
+void cmd_yaffs_mkdir(const char *dir)
+{
+	int retval = yaffs_mkdir(dir, 0);
+
+	if (retval < 0)
+		printf("yaffs_mkdir returning error: %d, %s\n",
+			retval, yaffs_error_str());
+}
+
+void cmd_yaffs_rmdir(const char *dir)
+{
+	int retval = yaffs_rmdir(dir);
+
+	if (retval < 0)
+		printf("yaffs_rmdir returning error: %d, %s\n",
+			retval, yaffs_error_str());
+}
+
+void cmd_yaffs_rm(const char *path)
+{
+	int retval = yaffs_unlink(path);
+
+	if (retval < 0)
+		printf("yaffs_unlink returning error: %d, %s\n",
+			retval, yaffs_error_str());
+}
+
+void cmd_yaffs_mv(const char *oldPath, const char *newPath)
+{
+	int retval = yaffs_rename(newPath, oldPath);
+
+	if (retval < 0)
+		printf("yaffs_unlink returning error: %d, %s\n",
+			retval, yaffs_error_str());
+}
diff --git a/fs/yaffs2/yaffs_verify.c b/fs/yaffs2/yaffs_verify.c
new file mode 100644
index 0000000000..97734a9e29
--- /dev/null
+++ b/fs/yaffs2/yaffs_verify.c
@@ -0,0 +1,526 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2011 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "yaffs_verify.h"
+#include "yaffs_trace.h"
+#include "yaffs_bitmap.h"
+#include "yaffs_getblockinfo.h"
+#include "yaffs_nand.h"
+
+int yaffs_skip_verification(struct yaffs_dev *dev)
+{
+	dev = dev;
+	return !(yaffs_trace_mask &
+		 (YAFFS_TRACE_VERIFY | YAFFS_TRACE_VERIFY_FULL));
+}
+
+static int yaffs_skip_full_verification(struct yaffs_dev *dev)
+{
+	dev = dev;
+	return !(yaffs_trace_mask & (YAFFS_TRACE_VERIFY_FULL));
+}
+
+static int yaffs_skip_nand_verification(struct yaffs_dev *dev)
+{
+	dev = dev;
+	return !(yaffs_trace_mask & (YAFFS_TRACE_VERIFY_NAND));
+}
+
+static const char * const block_state_name[] = {
+	"Unknown",
+	"Needs scan",
+	"Scanning",
+	"Empty",
+	"Allocating",
+	"Full",
+	"Dirty",
+	"Checkpoint",
+	"Collecting",
+	"Dead"
+};
+
+void yaffs_verify_blk(struct yaffs_dev *dev, struct yaffs_block_info *bi, int n)
+{
+	int actually_used;
+	int in_use;
+
+	if (yaffs_skip_verification(dev))
+		return;
+
+	/* Report illegal runtime states */
+	if (bi->block_state >= YAFFS_NUMBER_OF_BLOCK_STATES)
+		yaffs_trace(YAFFS_TRACE_VERIFY,
+			"Block %d has undefined state %d",
+			n, bi->block_state);
+
+	switch (bi->block_state) {
+	case YAFFS_BLOCK_STATE_UNKNOWN:
+	case YAFFS_BLOCK_STATE_SCANNING:
+	case YAFFS_BLOCK_STATE_NEEDS_SCAN:
+		yaffs_trace(YAFFS_TRACE_VERIFY,
+			"Block %d has bad run-state %s",
+			n, block_state_name[bi->block_state]);
+	}
+
+	/* Check pages in use and soft deletions are legal */
+
+	actually_used = bi->pages_in_use - bi->soft_del_pages;
+
+	if (bi->pages_in_use < 0 ||
+	    bi->pages_in_use > dev->param.chunks_per_block ||
+	    bi->soft_del_pages < 0 ||
+	    bi->soft_del_pages > dev->param.chunks_per_block ||
+	    actually_used < 0 || actually_used > dev->param.chunks_per_block)
+		yaffs_trace(YAFFS_TRACE_VERIFY,
+			"Block %d has illegal values pages_in_used %d soft_del_pages %d",
+			n, bi->pages_in_use, bi->soft_del_pages);
+
+	/* Check chunk bitmap legal */
+	in_use = yaffs_count_chunk_bits(dev, n);
+	if (in_use != bi->pages_in_use)
+		yaffs_trace(YAFFS_TRACE_VERIFY,
+			"Block %d has inconsistent values pages_in_use %d counted chunk bits %d",
+			n, bi->pages_in_use, in_use);
+}
+
+void yaffs_verify_collected_blk(struct yaffs_dev *dev,
+				struct yaffs_block_info *bi, int n)
+{
+	yaffs_verify_blk(dev, bi, n);
+
+	/* After collection the block should be in the erased state */
+
+	if (bi->block_state != YAFFS_BLOCK_STATE_COLLECTING &&
+	    bi->block_state != YAFFS_BLOCK_STATE_EMPTY) {
+		yaffs_trace(YAFFS_TRACE_ERROR,
+			"Block %d is in state %d after gc, should be erased",
+			n, bi->block_state);
+	}
+}
+
+void yaffs_verify_blocks(struct yaffs_dev *dev)
+{
+	int i;
+	int state_count[YAFFS_NUMBER_OF_BLOCK_STATES];
+	int illegal_states = 0;
+
+	if (yaffs_skip_verification(dev))
+		return;
+
+	memset(state_count, 0, sizeof(state_count));
+
+	for (i = dev->internal_start_block; i <= dev->internal_end_block; i++) {
+		struct yaffs_block_info *bi = yaffs_get_block_info(dev, i);
+		yaffs_verify_blk(dev, bi, i);
+
+		if (bi->block_state < YAFFS_NUMBER_OF_BLOCK_STATES)
+			state_count[bi->block_state]++;
+		else
+			illegal_states++;
+	}
+
+	yaffs_trace(YAFFS_TRACE_VERIFY,	"Block summary");
+
+	yaffs_trace(YAFFS_TRACE_VERIFY,
+		"%d blocks have illegal states",
+		illegal_states);
+	if (state_count[YAFFS_BLOCK_STATE_ALLOCATING] > 1)
+		yaffs_trace(YAFFS_TRACE_VERIFY,
+			"Too many allocating blocks");
+
+	for (i = 0; i < YAFFS_NUMBER_OF_BLOCK_STATES; i++)
+		yaffs_trace(YAFFS_TRACE_VERIFY,
+			"%s %d blocks",
+			block_state_name[i], state_count[i]);
+
+	if (dev->blocks_in_checkpt != state_count[YAFFS_BLOCK_STATE_CHECKPOINT])
+		yaffs_trace(YAFFS_TRACE_VERIFY,
+			"Checkpoint block count wrong dev %d count %d",
+			dev->blocks_in_checkpt,
+			state_count[YAFFS_BLOCK_STATE_CHECKPOINT]);
+
+	if (dev->n_erased_blocks != state_count[YAFFS_BLOCK_STATE_EMPTY])
+		yaffs_trace(YAFFS_TRACE_VERIFY,
+			"Erased block count wrong dev %d count %d",
+			dev->n_erased_blocks,
+			state_count[YAFFS_BLOCK_STATE_EMPTY]);
+
+	if (state_count[YAFFS_BLOCK_STATE_COLLECTING] > 1)
+		yaffs_trace(YAFFS_TRACE_VERIFY,
+			"Too many collecting blocks %d (max is 1)",
+			state_count[YAFFS_BLOCK_STATE_COLLECTING]);
+}
+
+/*
+ * Verify the object header. oh must be valid, but obj and tags may be NULL in
+ * which case those tests will not be performed.
+ */
+void yaffs_verify_oh(struct yaffs_obj *obj, struct yaffs_obj_hdr *oh,
+		     struct yaffs_ext_tags *tags, int parent_check)
+{
+	if (obj && yaffs_skip_verification(obj->my_dev))
+		return;
+
+	if (!(tags && obj && oh)) {
+		yaffs_trace(YAFFS_TRACE_VERIFY,
+			"Verifying object header tags %p obj %p oh %p",
+			tags, obj, oh);
+		return;
+	}
+
+	if (oh->type <= YAFFS_OBJECT_TYPE_UNKNOWN ||
+	    oh->type > YAFFS_OBJECT_TYPE_MAX)
+		yaffs_trace(YAFFS_TRACE_VERIFY,
+			"Obj %d header type is illegal value 0x%x",
+			tags->obj_id, oh->type);
+
+	if (tags->obj_id != obj->obj_id)
+		yaffs_trace(YAFFS_TRACE_VERIFY,
+			"Obj %d header mismatch obj_id %d",
+			tags->obj_id, obj->obj_id);
+
+	/*
+	 * Check that the object's parent ids match if parent_check requested.
+	 *
+	 * Tests do not apply to the root object.
+	 */
+
+	if (parent_check && tags->obj_id > 1 && !obj->parent)
+		yaffs_trace(YAFFS_TRACE_VERIFY,
+			"Obj %d header mismatch parent_id %d obj->parent is NULL",
+			tags->obj_id, oh->parent_obj_id);
+
+	if (parent_check && obj->parent &&
+	    oh->parent_obj_id != obj->parent->obj_id &&
+	    (oh->parent_obj_id != YAFFS_OBJECTID_UNLINKED ||
+	     obj->parent->obj_id != YAFFS_OBJECTID_DELETED))
+		yaffs_trace(YAFFS_TRACE_VERIFY,
+			"Obj %d header mismatch parent_id %d parent_obj_id %d",
+			tags->obj_id, oh->parent_obj_id,
+			obj->parent->obj_id);
+
+	if (tags->obj_id > 1 && oh->name[0] == 0)	/* Null name */
+		yaffs_trace(YAFFS_TRACE_VERIFY,
+			"Obj %d header name is NULL",
+			obj->obj_id);
+
+	if (tags->obj_id > 1 && ((u8) (oh->name[0])) == 0xff)	/* Junk name */
+		yaffs_trace(YAFFS_TRACE_VERIFY,
+			"Obj %d header name is 0xff",
+			obj->obj_id);
+}
+
+void yaffs_verify_file(struct yaffs_obj *obj)
+{
+	u32 x;
+	int required_depth;
+	int last_chunk;
+	u32 offset_in_chunk;
+	u32 the_chunk;
+
+	u32 i;
+	struct yaffs_dev *dev;
+	struct yaffs_ext_tags tags;
+	struct yaffs_tnode *tn;
+	u32 obj_id;
+
+	if (!obj)
+		return;
+
+	if (yaffs_skip_verification(obj->my_dev))
+		return;
+
+	dev = obj->my_dev;
+	obj_id = obj->obj_id;
+
+
+	/* Check file size is consistent with tnode depth */
+	yaffs_addr_to_chunk(dev, obj->variant.file_variant.file_size,
+				&last_chunk, &offset_in_chunk);
+	last_chunk++;
+	x = last_chunk >> YAFFS_TNODES_LEVEL0_BITS;
+	required_depth = 0;
+	while (x > 0) {
+		x >>= YAFFS_TNODES_INTERNAL_BITS;
+		required_depth++;
+	}
+
+	/* Check that the chunks in the tnode tree are all correct.
+	 * We do this by scanning through the tnode tree and
+	 * checking the tags for every chunk match.
+	 */
+
+	if (yaffs_skip_nand_verification(dev))
+		return;
+
+	for (i = 1; i <= last_chunk; i++) {
+		tn = yaffs_find_tnode_0(dev, &obj->variant.file_variant, i);
+
+		if (!tn)
+			continue;
+
+		the_chunk = yaffs_get_group_base(dev, tn, i);
+		if (the_chunk > 0) {
+			yaffs_rd_chunk_tags_nand(dev, the_chunk, NULL,
+						 &tags);
+			if (tags.obj_id != obj_id || tags.chunk_id != i)
+				yaffs_trace(YAFFS_TRACE_VERIFY,
+					"Object %d chunk_id %d NAND mismatch chunk %d tags (%d:%d)",
+					obj_id, i, the_chunk,
+					tags.obj_id, tags.chunk_id);
+		}
+	}
+}
+
+void yaffs_verify_link(struct yaffs_obj *obj)
+{
+	if (obj && yaffs_skip_verification(obj->my_dev))
+		return;
+
+	/* Verify sane equivalent object */
+}
+
+void yaffs_verify_symlink(struct yaffs_obj *obj)
+{
+	if (obj && yaffs_skip_verification(obj->my_dev))
+		return;
+
+	/* Verify symlink string */
+}
+
+void yaffs_verify_special(struct yaffs_obj *obj)
+{
+	if (obj && yaffs_skip_verification(obj->my_dev))
+		return;
+}
+
+void yaffs_verify_obj(struct yaffs_obj *obj)
+{
+	struct yaffs_dev *dev;
+	u32 chunk_min;
+	u32 chunk_max;
+	u32 chunk_id_ok;
+	u32 chunk_in_range;
+	u32 chunk_wrongly_deleted;
+	u32 chunk_valid;
+
+	if (!obj)
+		return;
+
+	if (obj->being_created)
+		return;
+
+	dev = obj->my_dev;
+
+	if (yaffs_skip_verification(dev))
+		return;
+
+	/* Check sane object header chunk */
+
+	chunk_min = dev->internal_start_block * dev->param.chunks_per_block;
+	chunk_max =
+	    (dev->internal_end_block + 1) * dev->param.chunks_per_block - 1;
+
+	chunk_in_range = (((unsigned)(obj->hdr_chunk)) >= chunk_min &&
+			  ((unsigned)(obj->hdr_chunk)) <= chunk_max);
+	chunk_id_ok = chunk_in_range || (obj->hdr_chunk == 0);
+	chunk_valid = chunk_in_range &&
+	    yaffs_check_chunk_bit(dev,
+				  obj->hdr_chunk / dev->param.chunks_per_block,
+				  obj->hdr_chunk % dev->param.chunks_per_block);
+	chunk_wrongly_deleted = chunk_in_range && !chunk_valid;
+
+	if (!obj->fake && (!chunk_id_ok || chunk_wrongly_deleted))
+		yaffs_trace(YAFFS_TRACE_VERIFY,
+			"Obj %d has chunk_id %d %s %s",
+			obj->obj_id, obj->hdr_chunk,
+			chunk_id_ok ? "" : ",out of range",
+			chunk_wrongly_deleted ? ",marked as deleted" : "");
+
+	if (chunk_valid && !yaffs_skip_nand_verification(dev)) {
+		struct yaffs_ext_tags tags;
+		struct yaffs_obj_hdr *oh;
+		u8 *buffer = yaffs_get_temp_buffer(dev);
+
+		oh = (struct yaffs_obj_hdr *)buffer;
+
+		yaffs_rd_chunk_tags_nand(dev, obj->hdr_chunk, buffer, &tags);
+
+		yaffs_verify_oh(obj, oh, &tags, 1);
+
+		yaffs_release_temp_buffer(dev, buffer);
+	}
+
+	/* Verify it has a parent */
+	if (obj && !obj->fake && (!obj->parent || obj->parent->my_dev != dev)) {
+		yaffs_trace(YAFFS_TRACE_VERIFY,
+			"Obj %d has parent pointer %p which does not look like an object",
+			obj->obj_id, obj->parent);
+	}
+
+	/* Verify parent is a directory */
+	if (obj->parent &&
+	    obj->parent->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) {
+		yaffs_trace(YAFFS_TRACE_VERIFY,
+			"Obj %d's parent is not a directory (type %d)",
+			obj->obj_id, obj->parent->variant_type);
+	}
+
+	switch (obj->variant_type) {
+	case YAFFS_OBJECT_TYPE_FILE:
+		yaffs_verify_file(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_SYMLINK:
+		yaffs_verify_symlink(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_DIRECTORY:
+		yaffs_verify_dir(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_HARDLINK:
+		yaffs_verify_link(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_SPECIAL:
+		yaffs_verify_special(obj);
+		break;
+	case YAFFS_OBJECT_TYPE_UNKNOWN:
+	default:
+		yaffs_trace(YAFFS_TRACE_VERIFY,
+			"Obj %d has illegaltype %d",
+		   obj->obj_id, obj->variant_type);
+		break;
+	}
+}
+
+void yaffs_verify_objects(struct yaffs_dev *dev)
+{
+	struct yaffs_obj *obj;
+	int i;
+	struct list_head *lh;
+
+	if (yaffs_skip_verification(dev))
+		return;
+
+	/* Iterate through the objects in each hash entry */
+
+	for (i = 0; i < YAFFS_NOBJECT_BUCKETS; i++) {
+		list_for_each(lh, &dev->obj_bucket[i].list) {
+			obj = list_entry(lh, struct yaffs_obj, hash_link);
+			yaffs_verify_obj(obj);
+		}
+	}
+}
+
+void yaffs_verify_obj_in_dir(struct yaffs_obj *obj)
+{
+	struct list_head *lh;
+	struct yaffs_obj *list_obj;
+	int count = 0;
+
+	if (!obj) {
+		yaffs_trace(YAFFS_TRACE_ALWAYS, "No object to verify");
+		BUG();
+		return;
+	}
+
+	if (yaffs_skip_verification(obj->my_dev))
+		return;
+
+	if (!obj->parent) {
+		yaffs_trace(YAFFS_TRACE_ALWAYS, "Object does not have parent");
+		BUG();
+		return;
+	}
+
+	if (obj->parent->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) {
+		yaffs_trace(YAFFS_TRACE_ALWAYS, "Parent is not directory");
+		BUG();
+	}
+
+	/* Iterate through the objects in each hash entry */
+
+	list_for_each(lh, &obj->parent->variant.dir_variant.children) {
+		list_obj = list_entry(lh, struct yaffs_obj, siblings);
+		yaffs_verify_obj(list_obj);
+		if (obj == list_obj)
+			count++;
+	}
+
+	if (count != 1) {
+		yaffs_trace(YAFFS_TRACE_ALWAYS,
+			"Object in directory %d times",
+			count);
+		BUG();
+	}
+}
+
+void yaffs_verify_dir(struct yaffs_obj *directory)
+{
+	struct list_head *lh;
+	struct yaffs_obj *list_obj;
+
+	if (!directory) {
+		BUG();
+		return;
+	}
+
+	if (yaffs_skip_full_verification(directory->my_dev))
+		return;
+
+	if (directory->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) {
+		yaffs_trace(YAFFS_TRACE_ALWAYS,
+			"Directory has wrong type: %d",
+			directory->variant_type);
+		BUG();
+	}
+
+	/* Iterate through the objects in each hash entry */
+
+	list_for_each(lh, &directory->variant.dir_variant.children) {
+		list_obj = list_entry(lh, struct yaffs_obj, siblings);
+		if (list_obj->parent != directory) {
+			yaffs_trace(YAFFS_TRACE_ALWAYS,
+				"Object in directory list has wrong parent %p",
+				list_obj->parent);
+			BUG();
+		}
+		yaffs_verify_obj_in_dir(list_obj);
+	}
+}
+
+static int yaffs_free_verification_failures;
+
+void yaffs_verify_free_chunks(struct yaffs_dev *dev)
+{
+	int counted;
+	int difference;
+
+	if (yaffs_skip_verification(dev))
+		return;
+
+	counted = yaffs_count_free_chunks(dev);
+
+	difference = dev->n_free_chunks - counted;
+
+	if (difference) {
+		yaffs_trace(YAFFS_TRACE_ALWAYS,
+			"Freechunks verification failure %d %d %d",
+			dev->n_free_chunks, counted, difference);
+		yaffs_free_verification_failures++;
+	}
+}
+
+int yaffs_verify_file_sane(struct yaffs_obj *in)
+{
+	in = in;
+	return YAFFS_OK;
+}
diff --git a/fs/yaffs2/yaffs_verify.h b/fs/yaffs2/yaffs_verify.h
new file mode 100644
index 0000000000..4f4af8d29a
--- /dev/null
+++ b/fs/yaffs2/yaffs_verify.h
@@ -0,0 +1,43 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2011 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_VERIFY_H__
+#define __YAFFS_VERIFY_H__
+
+#include "yaffs_guts.h"
+
+void yaffs_verify_blk(struct yaffs_dev *dev, struct yaffs_block_info *bi,
+		      int n);
+void yaffs_verify_collected_blk(struct yaffs_dev *dev,
+				struct yaffs_block_info *bi, int n);
+void yaffs_verify_blocks(struct yaffs_dev *dev);
+
+void yaffs_verify_oh(struct yaffs_obj *obj, struct yaffs_obj_hdr *oh,
+		     struct yaffs_ext_tags *tags, int parent_check);
+void yaffs_verify_file(struct yaffs_obj *obj);
+void yaffs_verify_link(struct yaffs_obj *obj);
+void yaffs_verify_symlink(struct yaffs_obj *obj);
+void yaffs_verify_special(struct yaffs_obj *obj);
+void yaffs_verify_obj(struct yaffs_obj *obj);
+void yaffs_verify_objects(struct yaffs_dev *dev);
+void yaffs_verify_obj_in_dir(struct yaffs_obj *obj);
+void yaffs_verify_dir(struct yaffs_obj *directory);
+void yaffs_verify_free_chunks(struct yaffs_dev *dev);
+
+int yaffs_verify_file_sane(struct yaffs_obj *obj);
+
+int yaffs_skip_verification(struct yaffs_dev *dev);
+
+#endif
diff --git a/fs/yaffs2/yaffs_yaffs1.c b/fs/yaffs2/yaffs_yaffs1.c
new file mode 100644
index 0000000000..357d8f75dd
--- /dev/null
+++ b/fs/yaffs2/yaffs_yaffs1.c
@@ -0,0 +1,419 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2011 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "yaffs_yaffs1.h"
+#include "yportenv.h"
+#include "yaffs_trace.h"
+#include "yaffs_bitmap.h"
+#include "yaffs_getblockinfo.h"
+#include "yaffs_nand.h"
+#include "yaffs_attribs.h"
+
+int yaffs1_scan(struct yaffs_dev *dev)
+{
+	struct yaffs_ext_tags tags;
+	int blk;
+	int chunk;
+	int c;
+	int deleted;
+	enum yaffs_block_state state;
+	LIST_HEAD(hard_list);
+	struct yaffs_block_info *bi;
+	u32 seq_number;
+	struct yaffs_obj_hdr *oh;
+	struct yaffs_obj *in;
+	struct yaffs_obj *parent;
+	int alloc_failed = 0;
+	struct yaffs_shadow_fixer *shadow_fixers = NULL;
+	u8 *chunk_data;
+
+	yaffs_trace(YAFFS_TRACE_SCAN,
+		"yaffs1_scan starts  intstartblk %d intendblk %d...",
+		dev->internal_start_block, dev->internal_end_block);
+
+	chunk_data = yaffs_get_temp_buffer(dev);
+
+	dev->seq_number = YAFFS_LOWEST_SEQUENCE_NUMBER;
+
+	/* Scan all the blocks to determine their state */
+	bi = dev->block_info;
+	for (blk = dev->internal_start_block; blk <= dev->internal_end_block;
+	     blk++) {
+		yaffs_clear_chunk_bits(dev, blk);
+		bi->pages_in_use = 0;
+		bi->soft_del_pages = 0;
+
+		yaffs_query_init_block_state(dev, blk, &state, &seq_number);
+
+		bi->block_state = state;
+		bi->seq_number = seq_number;
+
+		if (bi->seq_number == YAFFS_SEQUENCE_BAD_BLOCK)
+			bi->block_state = state = YAFFS_BLOCK_STATE_DEAD;
+
+		yaffs_trace(YAFFS_TRACE_SCAN_DEBUG,
+			"Block scanning block %d state %d seq %d",
+			blk, state, seq_number);
+
+		if (state == YAFFS_BLOCK_STATE_DEAD) {
+			yaffs_trace(YAFFS_TRACE_BAD_BLOCKS,
+				"block %d is bad", blk);
+		} else if (state == YAFFS_BLOCK_STATE_EMPTY) {
+			yaffs_trace(YAFFS_TRACE_SCAN_DEBUG, "Block empty ");
+			dev->n_erased_blocks++;
+			dev->n_free_chunks += dev->param.chunks_per_block;
+		}
+		bi++;
+	}
+
+	/* For each block.... */
+	for (blk = dev->internal_start_block;
+	     !alloc_failed && blk <= dev->internal_end_block; blk++) {
+
+		cond_resched();
+
+		bi = yaffs_get_block_info(dev, blk);
+		state = bi->block_state;
+
+		deleted = 0;
+
+		/* For each chunk in each block that needs scanning.... */
+		for (c = 0;
+			!alloc_failed && c < dev->param.chunks_per_block &&
+			state == YAFFS_BLOCK_STATE_NEEDS_SCAN; c++) {
+			/* Read the tags and decide what to do */
+			chunk = blk * dev->param.chunks_per_block + c;
+
+			yaffs_rd_chunk_tags_nand(dev, chunk, NULL, &tags);
+
+			/* Let's have a good look at this chunk... */
+
+			if (tags.ecc_result == YAFFS_ECC_RESULT_UNFIXED ||
+			    tags.is_deleted) {
+				/* YAFFS1 only...
+				 * A deleted chunk
+				 */
+				deleted++;
+				dev->n_free_chunks++;
+			} else if (!tags.chunk_used) {
+				/* An unassigned chunk in the block
+				 * This means that either the block is empty or
+				 * this is the one being allocated from
+				 */
+
+				if (c == 0) {
+					/* We're looking at the first chunk in
+					 *the block so the block is unused */
+					state = YAFFS_BLOCK_STATE_EMPTY;
+					dev->n_erased_blocks++;
+				} else {
+					/* this is the block being allocated */
+					yaffs_trace(YAFFS_TRACE_SCAN,
+						" Allocating from %d %d",
+						blk, c);
+					state = YAFFS_BLOCK_STATE_ALLOCATING;
+					dev->alloc_block = blk;
+					dev->alloc_page = c;
+					dev->alloc_block_finder = blk;
+
+				}
+
+				dev->n_free_chunks +=
+				    (dev->param.chunks_per_block - c);
+			} else if (tags.chunk_id > 0) {
+				/* chunk_id > 0 so it is a data chunk... */
+				unsigned int endpos;
+
+				yaffs_set_chunk_bit(dev, blk, c);
+				bi->pages_in_use++;
+
+				in = yaffs_find_or_create_by_number(dev,
+							tags.obj_id,
+							YAFFS_OBJECT_TYPE_FILE);
+				/* PutChunkIntoFile checks for a clash
+				 * (two data chunks with the same chunk_id).
+				 */
+
+				if (!in)
+					alloc_failed = 1;
+
+				if (in) {
+					if (!yaffs_put_chunk_in_file
+					    (in, tags.chunk_id, chunk, 1))
+						alloc_failed = 1;
+				}
+
+				endpos =
+				    (tags.chunk_id - 1) *
+				    dev->data_bytes_per_chunk +
+				    tags.n_bytes;
+				if (in &&
+				    in->variant_type ==
+				     YAFFS_OBJECT_TYPE_FILE &&
+				    in->variant.file_variant.scanned_size <
+				      endpos) {
+					in->variant.file_variant.scanned_size =
+					    endpos;
+					if (!dev->param.use_header_file_size) {
+						in->variant.
+						    file_variant.file_size =
+						    in->variant.
+						    file_variant.scanned_size;
+					}
+
+				}
+			} else {
+				/* chunk_id == 0, so it is an ObjectHeader.
+				 * Make the object
+				 */
+				yaffs_set_chunk_bit(dev, blk, c);
+				bi->pages_in_use++;
+
+				yaffs_rd_chunk_tags_nand(dev, chunk,
+							 chunk_data, NULL);
+
+				oh = (struct yaffs_obj_hdr *)chunk_data;
+
+				in = yaffs_find_by_number(dev, tags.obj_id);
+				if (in && in->variant_type != oh->type) {
+					/* This should not happen, but somehow
+					 * Wev'e ended up with an obj_id that
+					 * has been reused but not yet deleted,
+					 * and worse still it has changed type.
+					 * Delete the old object.
+					 */
+
+					yaffs_del_obj(in);
+					in = NULL;
+				}
+
+				in = yaffs_find_or_create_by_number(dev,
+								tags.obj_id,
+								oh->type);
+
+				if (!in)
+					alloc_failed = 1;
+
+				if (in && oh->shadows_obj > 0) {
+
+					struct yaffs_shadow_fixer *fixer;
+					fixer =
+						kmalloc(sizeof
+						(struct yaffs_shadow_fixer),
+						GFP_NOFS);
+					if (fixer) {
+						fixer->next = shadow_fixers;
+						shadow_fixers = fixer;
+						fixer->obj_id = tags.obj_id;
+						fixer->shadowed_id =
+						    oh->shadows_obj;
+						yaffs_trace(YAFFS_TRACE_SCAN,
+							" Shadow fixer: %d shadows %d",
+							fixer->obj_id,
+							fixer->shadowed_id);
+
+					}
+
+				}
+
+				if (in && in->valid) {
+					/* We have already filled this one.
+					 * We have a duplicate and need to
+					 * resolve it. */
+
+					unsigned existing_serial = in->serial;
+					unsigned new_serial =
+					    tags.serial_number;
+
+					if (((existing_serial + 1) & 3) ==
+					    new_serial) {
+						/* Use new one - destroy the
+						 * exisiting one */
+						yaffs_chunk_del(dev,
+								in->hdr_chunk,
+								1, __LINE__);
+						in->valid = 0;
+					} else {
+						/* Use existing - destroy
+						 * this one. */
+						yaffs_chunk_del(dev, chunk, 1,
+								__LINE__);
+					}
+				}
+
+				if (in && !in->valid &&
+				    (tags.obj_id == YAFFS_OBJECTID_ROOT ||
+				     tags.obj_id ==
+				     YAFFS_OBJECTID_LOSTNFOUND)) {
+					/* We only load some info, don't fiddle
+					 * with directory structure */
+					in->valid = 1;
+					in->variant_type = oh->type;
+
+					in->yst_mode = oh->yst_mode;
+					yaffs_load_attribs(in, oh);
+					in->hdr_chunk = chunk;
+					in->serial = tags.serial_number;
+
+				} else if (in && !in->valid) {
+					/* we need to load this info */
+
+					in->valid = 1;
+					in->variant_type = oh->type;
+
+					in->yst_mode = oh->yst_mode;
+					yaffs_load_attribs(in, oh);
+					in->hdr_chunk = chunk;
+					in->serial = tags.serial_number;
+
+					yaffs_set_obj_name_from_oh(in, oh);
+					in->dirty = 0;
+
+					/* directory stuff...
+					 * hook up to parent
+					 */
+
+					parent =
+					    yaffs_find_or_create_by_number
+					    (dev, oh->parent_obj_id,
+					     YAFFS_OBJECT_TYPE_DIRECTORY);
+					if (!parent)
+						alloc_failed = 1;
+					if (parent && parent->variant_type ==
+					    YAFFS_OBJECT_TYPE_UNKNOWN) {
+						/* Set up as a directory */
+						parent->variant_type =
+						    YAFFS_OBJECT_TYPE_DIRECTORY;
+						INIT_LIST_HEAD(&parent->
+							variant.dir_variant.
+							children);
+					} else if (!parent ||
+						parent->variant_type !=
+						YAFFS_OBJECT_TYPE_DIRECTORY) {
+						/* Hoosterman, a problem....
+						 * We're trying to use a
+						 * non-directory as a directory
+						 */
+
+						yaffs_trace(YAFFS_TRACE_ERROR,
+							"yaffs tragedy: attempting to use non-directory as a directory in scan. Put in lost+found."
+							);
+						parent = dev->lost_n_found;
+					}
+
+					yaffs_add_obj_to_dir(parent, in);
+
+					switch (in->variant_type) {
+					case YAFFS_OBJECT_TYPE_UNKNOWN:
+						/* Todo got a problem */
+						break;
+					case YAFFS_OBJECT_TYPE_FILE:
+						if (dev->param.
+						    use_header_file_size)
+							in->variant.
+							file_variant.file_size
+							= yaffs_oh_to_size(oh);
+						break;
+					case YAFFS_OBJECT_TYPE_HARDLINK:
+						in->variant.
+						    hardlink_variant.equiv_id =
+						    oh->equiv_id;
+						list_add(&in->hard_links,
+								&hard_list);
+						break;
+					case YAFFS_OBJECT_TYPE_DIRECTORY:
+						/* Do nothing */
+						break;
+					case YAFFS_OBJECT_TYPE_SPECIAL:
+						/* Do nothing */
+						break;
+					case YAFFS_OBJECT_TYPE_SYMLINK:
+						in->variant.symlink_variant.
+						    alias =
+						    yaffs_clone_str(oh->alias);
+						if (!in->variant.
+						    symlink_variant.alias)
+							alloc_failed = 1;
+						break;
+					}
+				}
+			}
+		}
+
+		if (state == YAFFS_BLOCK_STATE_NEEDS_SCAN) {
+			/* If we got this far while scanning,
+			 * then the block is fully allocated. */
+			state = YAFFS_BLOCK_STATE_FULL;
+		}
+
+		if (state == YAFFS_BLOCK_STATE_ALLOCATING) {
+			/* If the block was partially allocated then
+			 * treat it as fully allocated. */
+			state = YAFFS_BLOCK_STATE_FULL;
+			dev->alloc_block = -1;
+		}
+
+		bi->block_state = state;
+
+		/* Now let's see if it was dirty */
+		if (bi->pages_in_use == 0 &&
+		    !bi->has_shrink_hdr &&
+		    bi->block_state == YAFFS_BLOCK_STATE_FULL)
+			yaffs_block_became_dirty(dev, blk);
+	}
+
+	/* Ok, we've done all the scanning.
+	 * Fix up the hard link chains.
+	 * We should now have scanned all the objects, now it's time to add
+	 * these hardlinks.
+	 */
+
+	yaffs_link_fixup(dev, &hard_list);
+
+	/*
+	 * Fix up any shadowed objects.
+	 * There should not be more than one of these.
+	 */
+	{
+		struct yaffs_shadow_fixer *fixer;
+		struct yaffs_obj *obj;
+
+		while (shadow_fixers) {
+			fixer = shadow_fixers;
+			shadow_fixers = fixer->next;
+			/* Complete the rename transaction by deleting the
+			 * shadowed object then setting the object header
+			 to unshadowed.
+			 */
+			obj = yaffs_find_by_number(dev, fixer->shadowed_id);
+			if (obj)
+				yaffs_del_obj(obj);
+
+			obj = yaffs_find_by_number(dev, fixer->obj_id);
+
+			if (obj)
+				yaffs_update_oh(obj, NULL, 1, 0, 0, NULL);
+
+			kfree(fixer);
+		}
+	}
+
+	yaffs_release_temp_buffer(dev, chunk_data);
+
+	if (alloc_failed)
+		return YAFFS_FAIL;
+
+	yaffs_trace(YAFFS_TRACE_SCAN, "yaffs1_scan ends");
+
+	return YAFFS_OK;
+}
diff --git a/fs/yaffs2/yaffsinterface.h b/fs/yaffs2/yaffs_yaffs1.h
index 810837a32d..97e2fdd08a 100644
--- a/fs/yaffs2/yaffsinterface.h
+++ b/fs/yaffs2/yaffs_yaffs1.h
@@ -1,7 +1,7 @@
 /*
  * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
  *
- * Copyright (C) 2002-2007 Aleph One Ltd.
+ * Copyright (C) 2002-2011 Aleph One Ltd.
  *   for Toby Churchill Ltd and Brightstar Engineering
  *
  * Created by Charles Manning <charles@aleph1.co.uk>
@@ -13,9 +13,10 @@
  * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
  */
 
-#ifndef __YAFFSINTERFACE_H__
-#define __YAFFSINTERFACE_H__
+#ifndef __YAFFS_YAFFS1_H__
+#define __YAFFS_YAFFS1_H__
 
-int yaffs_Initialise(unsigned nBlocks);
+#include "yaffs_guts.h"
+int yaffs1_scan(struct yaffs_dev *dev);
 
 #endif
diff --git a/fs/yaffs2/yaffs_yaffs2.c b/fs/yaffs2/yaffs_yaffs2.c
new file mode 100644
index 0000000000..f76dcaeeb1
--- /dev/null
+++ b/fs/yaffs2/yaffs_yaffs2.c
@@ -0,0 +1,1526 @@
+/*
+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2011 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "yaffs_guts.h"
+#include "yaffs_trace.h"
+#include "yaffs_yaffs2.h"
+#include "yaffs_checkptrw.h"
+#include "yaffs_bitmap.h"
+#include "yaffs_nand.h"
+#include "yaffs_getblockinfo.h"
+#include "yaffs_verify.h"
+#include "yaffs_attribs.h"
+#include "yaffs_summary.h"
+
+/*
+ * Checkpoints are really no benefit on very small partitions.
+ *
+ * To save space on small partitions don't bother with checkpoints unless
+ * the partition is at least this big.
+ */
+#define YAFFS_CHECKPOINT_MIN_BLOCKS 60
+#define YAFFS_SMALL_HOLE_THRESHOLD 4
+
+/*
+ * Oldest Dirty Sequence Number handling.
+ */
+
+/* yaffs_calc_oldest_dirty_seq()
+ * yaffs2_find_oldest_dirty_seq()
+ * Calculate the oldest dirty sequence number if we don't know it.
+ */
+void yaffs_calc_oldest_dirty_seq(struct yaffs_dev *dev)
+{
+	int i;
+	unsigned seq;
+	unsigned block_no = 0;
+	struct yaffs_block_info *b;
+
+	if (!dev->param.is_yaffs2)
+		return;
+
+	/* Find the oldest dirty sequence number. */
+	seq = dev->seq_number + 1;
+	b = dev->block_info;
+	for (i = dev->internal_start_block; i <= dev->internal_end_block; i++) {
+		if (b->block_state == YAFFS_BLOCK_STATE_FULL &&
+		    (b->pages_in_use - b->soft_del_pages) <
+		    dev->param.chunks_per_block &&
+		    b->seq_number < seq) {
+			seq = b->seq_number;
+			block_no = i;
+		}
+		b++;
+	}
+
+	if (block_no) {
+		dev->oldest_dirty_seq = seq;
+		dev->oldest_dirty_block = block_no;
+	}
+}
+
+void yaffs2_find_oldest_dirty_seq(struct yaffs_dev *dev)
+{
+	if (!dev->param.is_yaffs2)
+		return;
+
+	if (!dev->oldest_dirty_seq)
+		yaffs_calc_oldest_dirty_seq(dev);
+}
+
+/*
+ * yaffs_clear_oldest_dirty_seq()
+ * Called when a block is erased or marked bad. (ie. when its seq_number
+ * becomes invalid). If the value matches the oldest then we clear
+ * dev->oldest_dirty_seq to force its recomputation.
+ */
+void yaffs2_clear_oldest_dirty_seq(struct yaffs_dev *dev,
+				   struct yaffs_block_info *bi)
+{
+
+	if (!dev->param.is_yaffs2)
+		return;
+
+	if (!bi || bi->seq_number == dev->oldest_dirty_seq) {
+		dev->oldest_dirty_seq = 0;
+		dev->oldest_dirty_block = 0;
+	}
+}
+
+/*
+ * yaffs2_update_oldest_dirty_seq()
+ * Update the oldest dirty sequence number whenever we dirty a block.
+ * Only do this if the oldest_dirty_seq is actually being tracked.
+ */
+void yaffs2_update_oldest_dirty_seq(struct yaffs_dev *dev, unsigned block_no,
+				    struct yaffs_block_info *bi)
+{
+	if (!dev->param.is_yaffs2)
+		return;
+
+	if (dev->oldest_dirty_seq) {
+		if (dev->oldest_dirty_seq > bi->seq_number) {
+			dev->oldest_dirty_seq = bi->seq_number;
+			dev->oldest_dirty_block = block_no;
+		}
+	}
+}
+
+int yaffs_block_ok_for_gc(struct yaffs_dev *dev, struct yaffs_block_info *bi)
+{
+
+	if (!dev->param.is_yaffs2)
+		return 1;	/* disqualification only applies to yaffs2. */
+
+	if (!bi->has_shrink_hdr)
+		return 1;	/* can gc */
+
+	yaffs2_find_oldest_dirty_seq(dev);
+
+	/* Can't do gc of this block if there are any blocks older than this
+	 * one that have discarded pages.
+	 */
+	return (bi->seq_number <= dev->oldest_dirty_seq);
+}
+
+/*
+ * yaffs2_find_refresh_block()
+ * periodically finds the oldest full block by sequence number for refreshing.
+ * Only for yaffs2.
+ */
+u32 yaffs2_find_refresh_block(struct yaffs_dev *dev)
+{
+	u32 b;
+	u32 oldest = 0;
+	u32 oldest_seq = 0;
+	struct yaffs_block_info *bi;
+
+	if (!dev->param.is_yaffs2)
+		return oldest;
+
+	/*
+	 * If refresh period < 10 then refreshing is disabled.
+	 */
+	if (dev->param.refresh_period < 10)
+		return oldest;
+
+	/*
+	 * Fix broken values.
+	 */
+	if (dev->refresh_skip > dev->param.refresh_period)
+		dev->refresh_skip = dev->param.refresh_period;
+
+	if (dev->refresh_skip > 0)
+		return oldest;
+
+	/*
+	 * Refresh skip is now zero.
+	 * We'll do a refresh this time around....
+	 * Update the refresh skip and find the oldest block.
+	 */
+	dev->refresh_skip = dev->param.refresh_period;
+	dev->refresh_count++;
+	bi = dev->block_info;
+	for (b = dev->internal_start_block; b <= dev->internal_end_block; b++) {
+
+		if (bi->block_state == YAFFS_BLOCK_STATE_FULL) {
+
+			if (oldest < 1 || bi->seq_number < oldest_seq) {
+				oldest = b;
+				oldest_seq = bi->seq_number;
+			}
+		}
+		bi++;
+	}
+
+	if (oldest > 0) {
+		yaffs_trace(YAFFS_TRACE_GC,
+			"GC refresh count %d selected block %d with seq_number %d",
+			dev->refresh_count, oldest, oldest_seq);
+	}
+
+	return oldest;
+}
+
+int yaffs2_checkpt_required(struct yaffs_dev *dev)
+{
+	int nblocks;
+
+	if (!dev->param.is_yaffs2)
+		return 0;
+
+	nblocks = dev->internal_end_block - dev->internal_start_block + 1;
+
+	return !dev->param.skip_checkpt_wr &&
+	    !dev->read_only && (nblocks >= YAFFS_CHECKPOINT_MIN_BLOCKS);
+}
+
+int yaffs_calc_checkpt_blocks_required(struct yaffs_dev *dev)
+{
+	int retval;
+	int n_bytes = 0;
+	int n_blocks;
+	int dev_blocks;
+
+	if (!dev->param.is_yaffs2)
+		return 0;
+
+	if (!dev->checkpoint_blocks_required && yaffs2_checkpt_required(dev)) {
+		/* Not a valid value so recalculate */
+		dev_blocks = dev->param.end_block - dev->param.start_block + 1;
+		n_bytes += sizeof(struct yaffs_checkpt_validity);
+		n_bytes += sizeof(struct yaffs_checkpt_dev);
+		n_bytes += dev_blocks * sizeof(struct yaffs_block_info);
+		n_bytes += dev_blocks * dev->chunk_bit_stride;
+		n_bytes +=
+		    (sizeof(struct yaffs_checkpt_obj) + sizeof(u32)) *
+		    dev->n_obj;
+		n_bytes += (dev->tnode_size + sizeof(u32)) * dev->n_tnodes;
+		n_bytes += sizeof(struct yaffs_checkpt_validity);
+		n_bytes += sizeof(u32);	/* checksum */
+
+		/* Round up and add 2 blocks to allow for some bad blocks,
+		 * so add 3 */
+
+		n_blocks =
+		    (n_bytes /
+		     (dev->data_bytes_per_chunk *
+		      dev->param.chunks_per_block)) + 3;
+
+		dev->checkpoint_blocks_required = n_blocks;
+	}
+
+	retval = dev->checkpoint_blocks_required - dev->blocks_in_checkpt;
+	if (retval < 0)
+		retval = 0;
+	return retval;
+}
+
+/*--------------------- Checkpointing --------------------*/
+
+static int yaffs2_wr_checkpt_validity_marker(struct yaffs_dev *dev, int head)
+{
+	struct yaffs_checkpt_validity cp;
+
+	memset(&cp, 0, sizeof(cp));
+
+	cp.struct_type = sizeof(cp);
+	cp.magic = YAFFS_MAGIC;
+	cp.version = YAFFS_CHECKPOINT_VERSION;
+	cp.head = (head) ? 1 : 0;
+
+	return (yaffs2_checkpt_wr(dev, &cp, sizeof(cp)) == sizeof(cp)) ? 1 : 0;
+}
+
+static int yaffs2_rd_checkpt_validity_marker(struct yaffs_dev *dev, int head)
+{
+	struct yaffs_checkpt_validity cp;
+	int ok;
+
+	ok = (yaffs2_checkpt_rd(dev, &cp, sizeof(cp)) == sizeof(cp));
+
+	if (ok)
+		ok = (cp.struct_type == sizeof(cp)) &&
+		    (cp.magic == YAFFS_MAGIC) &&
+		    (cp.version == YAFFS_CHECKPOINT_VERSION) &&
+		    (cp.head == ((head) ? 1 : 0));
+	return ok ? 1 : 0;
+}
+
+static void yaffs2_dev_to_checkpt_dev(struct yaffs_checkpt_dev *cp,
+				      struct yaffs_dev *dev)
+{
+	cp->n_erased_blocks = dev->n_erased_blocks;
+	cp->alloc_block = dev->alloc_block;
+	cp->alloc_page = dev->alloc_page;
+	cp->n_free_chunks = dev->n_free_chunks;
+
+	cp->n_deleted_files = dev->n_deleted_files;
+	cp->n_unlinked_files = dev->n_unlinked_files;
+	cp->n_bg_deletions = dev->n_bg_deletions;
+	cp->seq_number = dev->seq_number;
+
+}
+
+static void yaffs_checkpt_dev_to_dev(struct yaffs_dev *dev,
+				     struct yaffs_checkpt_dev *cp)
+{
+	dev->n_erased_blocks = cp->n_erased_blocks;
+	dev->alloc_block = cp->alloc_block;
+	dev->alloc_page = cp->alloc_page;
+	dev->n_free_chunks = cp->n_free_chunks;
+
+	dev->n_deleted_files = cp->n_deleted_files;
+	dev->n_unlinked_files = cp->n_unlinked_files;
+	dev->n_bg_deletions = cp->n_bg_deletions;
+	dev->seq_number = cp->seq_number;
+}
+
+static int yaffs2_wr_checkpt_dev(struct yaffs_dev *dev)
+{
+	struct yaffs_checkpt_dev cp;
+	u32 n_bytes;
+	u32 n_blocks = dev->internal_end_block - dev->internal_start_block + 1;
+	int ok;
+
+	/* Write device runtime values */
+	yaffs2_dev_to_checkpt_dev(&cp, dev);
+	cp.struct_type = sizeof(cp);
+
+	ok = (yaffs2_checkpt_wr(dev, &cp, sizeof(cp)) == sizeof(cp));
+	if (!ok)
+		return 0;
+
+	/* Write block info */
+	n_bytes = n_blocks * sizeof(struct yaffs_block_info);
+	ok = (yaffs2_checkpt_wr(dev, dev->block_info, n_bytes) == n_bytes);
+	if (!ok)
+		return 0;
+
+	/* Write chunk bits */
+	n_bytes = n_blocks * dev->chunk_bit_stride;
+	ok = (yaffs2_checkpt_wr(dev, dev->chunk_bits, n_bytes) == n_bytes);
+
+	return ok ? 1 : 0;
+}
+
+static int yaffs2_rd_checkpt_dev(struct yaffs_dev *dev)
+{
+	struct yaffs_checkpt_dev cp;
+	u32 n_bytes;
+	u32 n_blocks =
+	    (dev->internal_end_block - dev->internal_start_block + 1);
+	int ok;
+
+	ok = (yaffs2_checkpt_rd(dev, &cp, sizeof(cp)) == sizeof(cp));
+	if (!ok)
+		return 0;
+
+	if (cp.struct_type != sizeof(cp))
+		return 0;
+
+	yaffs_checkpt_dev_to_dev(dev, &cp);
+
+	n_bytes = n_blocks * sizeof(struct yaffs_block_info);
+
+	ok = (yaffs2_checkpt_rd(dev, dev->block_info, n_bytes) == n_bytes);
+
+	if (!ok)
+		return 0;
+
+	n_bytes = n_blocks * dev->chunk_bit_stride;
+
+	ok = (yaffs2_checkpt_rd(dev, dev->chunk_bits, n_bytes) == n_bytes);
+
+	return ok ? 1 : 0;
+}
+
+static void yaffs2_obj_checkpt_obj(struct yaffs_checkpt_obj *cp,
+				   struct yaffs_obj *obj)
+{
+	cp->obj_id = obj->obj_id;
+	cp->parent_id = (obj->parent) ? obj->parent->obj_id : 0;
+	cp->hdr_chunk = obj->hdr_chunk;
+	cp->variant_type = obj->variant_type;
+	cp->deleted = obj->deleted;
+	cp->soft_del = obj->soft_del;
+	cp->unlinked = obj->unlinked;
+	cp->fake = obj->fake;
+	cp->rename_allowed = obj->rename_allowed;
+	cp->unlink_allowed = obj->unlink_allowed;
+	cp->serial = obj->serial;
+	cp->n_data_chunks = obj->n_data_chunks;
+
+	if (obj->variant_type == YAFFS_OBJECT_TYPE_FILE)
+		cp->size_or_equiv_obj = obj->variant.file_variant.file_size;
+	else if (obj->variant_type == YAFFS_OBJECT_TYPE_HARDLINK)
+		cp->size_or_equiv_obj = obj->variant.hardlink_variant.equiv_id;
+}
+
+static int yaffs2_checkpt_obj_to_obj(struct yaffs_obj *obj,
+				     struct yaffs_checkpt_obj *cp)
+{
+	struct yaffs_obj *parent;
+
+	if (obj->variant_type != cp->variant_type) {
+		yaffs_trace(YAFFS_TRACE_ERROR,
+			"Checkpoint read object %d type %d chunk %d does not match existing object type %d",
+			cp->obj_id, cp->variant_type, cp->hdr_chunk,
+			obj->variant_type);
+		return 0;
+	}
+
+	obj->obj_id = cp->obj_id;
+
+	if (cp->parent_id)
+		parent = yaffs_find_or_create_by_number(obj->my_dev,
+						cp->parent_id,
+						YAFFS_OBJECT_TYPE_DIRECTORY);
+	else
+		parent = NULL;
+
+	if (parent) {
+		if (parent->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) {
+			yaffs_trace(YAFFS_TRACE_ALWAYS,
+				"Checkpoint read object %d parent %d type %d chunk %d Parent type, %d, not directory",
+				cp->obj_id, cp->parent_id,
+				cp->variant_type, cp->hdr_chunk,
+				parent->variant_type);
+			return 0;
+		}
+		yaffs_add_obj_to_dir(parent, obj);
+	}
+
+	obj->hdr_chunk = cp->hdr_chunk;
+	obj->variant_type = cp->variant_type;
+	obj->deleted = cp->deleted;
+	obj->soft_del = cp->soft_del;
+	obj->unlinked = cp->unlinked;
+	obj->fake = cp->fake;
+	obj->rename_allowed = cp->rename_allowed;
+	obj->unlink_allowed = cp->unlink_allowed;
+	obj->serial = cp->serial;
+	obj->n_data_chunks = cp->n_data_chunks;
+
+	if (obj->variant_type == YAFFS_OBJECT_TYPE_FILE)
+		obj->variant.file_variant.file_size = cp->size_or_equiv_obj;
+	else if (obj->variant_type == YAFFS_OBJECT_TYPE_HARDLINK)
+		obj->variant.hardlink_variant.equiv_id = cp->size_or_equiv_obj;
+
+	if (obj->hdr_chunk > 0)
+		obj->lazy_loaded = 1;
+	return 1;
+}
+
+static int yaffs2_checkpt_tnode_worker(struct yaffs_obj *in,
+				       struct yaffs_tnode *tn, u32 level,
+				       int chunk_offset)
+{
+	int i;
+	struct yaffs_dev *dev = in->my_dev;
+	int ok = 1;
+	u32 base_offset;
+
+	if (!tn)
+		return 1;
+
+	if (level > 0) {
+		for (i = 0; i < YAFFS_NTNODES_INTERNAL && ok; i++) {
+			if (!tn->internal[i])
+				continue;
+			ok = yaffs2_checkpt_tnode_worker(in,
+				 tn->internal[i],
+				 level - 1,
+				 (chunk_offset <<
+				  YAFFS_TNODES_INTERNAL_BITS) + i);
+		}
+		return ok;
+	}
+
+	/* Level 0 tnode */
+	base_offset = chunk_offset << YAFFS_TNODES_LEVEL0_BITS;
+	ok = (yaffs2_checkpt_wr(dev, &base_offset, sizeof(base_offset)) ==
+			sizeof(base_offset));
+	if (ok)
+		ok = (yaffs2_checkpt_wr(dev, tn, dev->tnode_size) ==
+			dev->tnode_size);
+
+	return ok;
+}
+
+static int yaffs2_wr_checkpt_tnodes(struct yaffs_obj *obj)
+{
+	u32 end_marker = ~0;
+	int ok = 1;
+
+	if (obj->variant_type != YAFFS_OBJECT_TYPE_FILE)
+		return ok;
+
+	ok = yaffs2_checkpt_tnode_worker(obj,
+					 obj->variant.file_variant.top,
+					 obj->variant.file_variant.
+					 top_level, 0);
+	if (ok)
+		ok = (yaffs2_checkpt_wr(obj->my_dev, &end_marker,
+				sizeof(end_marker)) == sizeof(end_marker));
+
+	return ok ? 1 : 0;
+}
+
+static int yaffs2_rd_checkpt_tnodes(struct yaffs_obj *obj)
+{
+	u32 base_chunk;
+	int ok = 1;
+	struct yaffs_dev *dev = obj->my_dev;
+	struct yaffs_file_var *file_stuct_ptr = &obj->variant.file_variant;
+	struct yaffs_tnode *tn;
+	int nread = 0;
+
+	ok = (yaffs2_checkpt_rd(dev, &base_chunk, sizeof(base_chunk)) ==
+	      sizeof(base_chunk));
+
+	while (ok && (~base_chunk)) {
+		nread++;
+		/* Read level 0 tnode */
+
+		tn = yaffs_get_tnode(dev);
+		if (tn)
+			ok = (yaffs2_checkpt_rd(dev, tn, dev->tnode_size) ==
+				dev->tnode_size);
+		else
+			ok = 0;
+
+		if (tn && ok)
+			ok = yaffs_add_find_tnode_0(dev,
+						    file_stuct_ptr,
+						    base_chunk, tn) ? 1 : 0;
+
+		if (ok)
+			ok = (yaffs2_checkpt_rd
+			      (dev, &base_chunk,
+			       sizeof(base_chunk)) == sizeof(base_chunk));
+	}
+
+	yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+		"Checkpoint read tnodes %d records, last %d. ok %d",
+		nread, base_chunk, ok);
+
+	return ok ? 1 : 0;
+}
+
+static int yaffs2_wr_checkpt_objs(struct yaffs_dev *dev)
+{
+	struct yaffs_obj *obj;
+	struct yaffs_checkpt_obj cp;
+	int i;
+	int ok = 1;
+	struct list_head *lh;
+
+	/* Iterate through the objects in each hash entry,
+	 * dumping them to the checkpointing stream.
+	 */
+
+	for (i = 0; ok && i < YAFFS_NOBJECT_BUCKETS; i++) {
+		list_for_each(lh, &dev->obj_bucket[i].list) {
+			obj = list_entry(lh, struct yaffs_obj, hash_link);
+			if (!obj->defered_free) {
+				yaffs2_obj_checkpt_obj(&cp, obj);
+				cp.struct_type = sizeof(cp);
+
+				yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+					"Checkpoint write object %d parent %d type %d chunk %d obj addr %p",
+					cp.obj_id, cp.parent_id,
+					cp.variant_type, cp.hdr_chunk, obj);
+
+				ok = (yaffs2_checkpt_wr(dev, &cp,
+						sizeof(cp)) == sizeof(cp));
+
+				if (ok &&
+					obj->variant_type ==
+					YAFFS_OBJECT_TYPE_FILE)
+					ok = yaffs2_wr_checkpt_tnodes(obj);
+			}
+		}
+	}
+
+	/* Dump end of list */
+	memset(&cp, 0xff, sizeof(struct yaffs_checkpt_obj));
+	cp.struct_type = sizeof(cp);
+
+	if (ok)
+		ok = (yaffs2_checkpt_wr(dev, &cp, sizeof(cp)) == sizeof(cp));
+
+	return ok ? 1 : 0;
+}
+
+static int yaffs2_rd_checkpt_objs(struct yaffs_dev *dev)
+{
+	struct yaffs_obj *obj;
+	struct yaffs_checkpt_obj cp;
+	int ok = 1;
+	int done = 0;
+	LIST_HEAD(hard_list);
+
+
+	while (ok && !done) {
+		ok = (yaffs2_checkpt_rd(dev, &cp, sizeof(cp)) == sizeof(cp));
+		if (cp.struct_type != sizeof(cp)) {
+			yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+				"struct size %d instead of %d ok %d",
+				cp.struct_type, (int)sizeof(cp), ok);
+			ok = 0;
+		}
+
+		yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+			"Checkpoint read object %d parent %d type %d chunk %d ",
+			cp.obj_id, cp.parent_id, cp.variant_type,
+			cp.hdr_chunk);
+
+		if (ok && cp.obj_id == ~0) {
+			done = 1;
+		} else if (ok) {
+			obj =
+			    yaffs_find_or_create_by_number(dev, cp.obj_id,
+							   cp.variant_type);
+			if (obj) {
+				ok = yaffs2_checkpt_obj_to_obj(obj, &cp);
+				if (!ok)
+					break;
+				if (obj->variant_type ==
+					YAFFS_OBJECT_TYPE_FILE) {
+					ok = yaffs2_rd_checkpt_tnodes(obj);
+				} else if (obj->variant_type ==
+					YAFFS_OBJECT_TYPE_HARDLINK) {
+					list_add(&obj->hard_links, &hard_list);
+				}
+			} else {
+				ok = 0;
+			}
+		}
+	}
+
+	if (ok)
+		yaffs_link_fixup(dev, &hard_list);
+
+	return ok ? 1 : 0;
+}
+
+static int yaffs2_wr_checkpt_sum(struct yaffs_dev *dev)
+{
+	u32 checkpt_sum;
+	int ok;
+
+	yaffs2_get_checkpt_sum(dev, &checkpt_sum);
+
+	ok = (yaffs2_checkpt_wr(dev, &checkpt_sum, sizeof(checkpt_sum)) ==
+		sizeof(checkpt_sum));
+
+	if (!ok)
+		return 0;
+
+	return 1;
+}
+
+static int yaffs2_rd_checkpt_sum(struct yaffs_dev *dev)
+{
+	u32 checkpt_sum0;
+	u32 checkpt_sum1;
+	int ok;
+
+	yaffs2_get_checkpt_sum(dev, &checkpt_sum0);
+
+	ok = (yaffs2_checkpt_rd(dev, &checkpt_sum1, sizeof(checkpt_sum1)) ==
+		sizeof(checkpt_sum1));
+
+	if (!ok)
+		return 0;
+
+	if (checkpt_sum0 != checkpt_sum1)
+		return 0;
+
+	return 1;
+}
+
+static int yaffs2_wr_checkpt_data(struct yaffs_dev *dev)
+{
+	int ok = 1;
+
+	if (!yaffs2_checkpt_required(dev)) {
+		yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+			"skipping checkpoint write");
+		ok = 0;
+	}
+
+	if (ok)
+		ok = yaffs2_checkpt_open(dev, 1);
+
+	if (ok) {
+		yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+			"write checkpoint validity");
+		ok = yaffs2_wr_checkpt_validity_marker(dev, 1);
+	}
+	if (ok) {
+		yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+			"write checkpoint device");
+		ok = yaffs2_wr_checkpt_dev(dev);
+	}
+	if (ok) {
+		yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+			"write checkpoint objects");
+		ok = yaffs2_wr_checkpt_objs(dev);
+	}
+	if (ok) {
+		yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+			"write checkpoint validity");
+		ok = yaffs2_wr_checkpt_validity_marker(dev, 0);
+	}
+
+	if (ok)
+		ok = yaffs2_wr_checkpt_sum(dev);
+
+	if (!yaffs_checkpt_close(dev))
+		ok = 0;
+
+	if (ok)
+		dev->is_checkpointed = 1;
+	else
+		dev->is_checkpointed = 0;
+
+	return dev->is_checkpointed;
+}
+
+static int yaffs2_rd_checkpt_data(struct yaffs_dev *dev)
+{
+	int ok = 1;
+
+	if (!dev->param.is_yaffs2)
+		ok = 0;
+
+	if (ok && dev->param.skip_checkpt_rd) {
+		yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+			"skipping checkpoint read");
+		ok = 0;
+	}
+
+	if (ok)
+		ok = yaffs2_checkpt_open(dev, 0); /* open for read */
+
+	if (ok) {
+		yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+			"read checkpoint validity");
+		ok = yaffs2_rd_checkpt_validity_marker(dev, 1);
+	}
+	if (ok) {
+		yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+			"read checkpoint device");
+		ok = yaffs2_rd_checkpt_dev(dev);
+	}
+	if (ok) {
+		yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+			"read checkpoint objects");
+		ok = yaffs2_rd_checkpt_objs(dev);
+	}
+	if (ok) {
+		yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+			"read checkpoint validity");
+		ok = yaffs2_rd_checkpt_validity_marker(dev, 0);
+	}
+
+	if (ok) {
+		ok = yaffs2_rd_checkpt_sum(dev);
+		yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+			"read checkpoint checksum %d", ok);
+	}
+
+	if (!yaffs_checkpt_close(dev))
+		ok = 0;
+
+	if (ok)
+		dev->is_checkpointed = 1;
+	else
+		dev->is_checkpointed = 0;
+
+	return ok ? 1 : 0;
+}
+
+void yaffs2_checkpt_invalidate(struct yaffs_dev *dev)
+{
+	if (dev->is_checkpointed || dev->blocks_in_checkpt > 0) {
+		dev->is_checkpointed = 0;
+		yaffs2_checkpt_invalidate_stream(dev);
+	}
+	if (dev->param.sb_dirty_fn)
+		dev->param.sb_dirty_fn(dev);
+}
+
+int yaffs_checkpoint_save(struct yaffs_dev *dev)
+{
+	yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+		"save entry: is_checkpointed %d",
+		dev->is_checkpointed);
+
+	yaffs_verify_objects(dev);
+	yaffs_verify_blocks(dev);
+	yaffs_verify_free_chunks(dev);
+
+	if (!dev->is_checkpointed) {
+		yaffs2_checkpt_invalidate(dev);
+		yaffs2_wr_checkpt_data(dev);
+	}
+
+	yaffs_trace(YAFFS_TRACE_CHECKPOINT | YAFFS_TRACE_MOUNT,
+		"save exit: is_checkpointed %d",
+		dev->is_checkpointed);
+
+	return dev->is_checkpointed;
+}
+
+int yaffs2_checkpt_restore(struct yaffs_dev *dev)
+{
+	int retval;
+
+	yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+		"restore entry: is_checkpointed %d",
+		dev->is_checkpointed);
+
+	retval = yaffs2_rd_checkpt_data(dev);
+
+	if (dev->is_checkpointed) {
+		yaffs_verify_objects(dev);
+		yaffs_verify_blocks(dev);
+		yaffs_verify_free_chunks(dev);
+	}
+
+	yaffs_trace(YAFFS_TRACE_CHECKPOINT,
+		"restore exit: is_checkpointed %d",
+		dev->is_checkpointed);
+
+	return retval;
+}
+
+int yaffs2_handle_hole(struct yaffs_obj *obj, loff_t new_size)
+{
+	/* if new_size > old_file_size.
+	 * We're going to be writing a hole.
+	 * If the hole is small then write zeros otherwise write a start
+	 * of hole marker.
+	 */
+	loff_t old_file_size;
+	loff_t increase;
+	int small_hole;
+	int result = YAFFS_OK;
+	struct yaffs_dev *dev = NULL;
+	u8 *local_buffer = NULL;
+	int small_increase_ok = 0;
+
+	if (!obj)
+		return YAFFS_FAIL;
+
+	if (obj->variant_type != YAFFS_OBJECT_TYPE_FILE)
+		return YAFFS_FAIL;
+
+	dev = obj->my_dev;
+
+	/* Bail out if not yaffs2 mode */
+	if (!dev->param.is_yaffs2)
+		return YAFFS_OK;
+
+	old_file_size = obj->variant.file_variant.file_size;
+
+	if (new_size <= old_file_size)
+		return YAFFS_OK;
+
+	increase = new_size - old_file_size;
+
+	if (increase < YAFFS_SMALL_HOLE_THRESHOLD * dev->data_bytes_per_chunk &&
+	    yaffs_check_alloc_available(dev, YAFFS_SMALL_HOLE_THRESHOLD + 1))
+		small_hole = 1;
+	else
+		small_hole = 0;
+
+	if (small_hole)
+		local_buffer = yaffs_get_temp_buffer(dev);
+
+	if (local_buffer) {
+		/* fill hole with zero bytes */
+		loff_t pos = old_file_size;
+		int this_write;
+		int written;
+		memset(local_buffer, 0, dev->data_bytes_per_chunk);
+		small_increase_ok = 1;
+
+		while (increase > 0 && small_increase_ok) {
+			this_write = increase;
+			if (this_write > dev->data_bytes_per_chunk)
+				this_write = dev->data_bytes_per_chunk;
+			written =
+			    yaffs_do_file_wr(obj, local_buffer, pos, this_write,
+					     0);
+			if (written == this_write) {
+				pos += this_write;
+				increase -= this_write;
+			} else {
+				small_increase_ok = 0;
+			}
+		}
+
+		yaffs_release_temp_buffer(dev, local_buffer);
+
+		/* If out of space then reverse any chunks we've added */
+		if (!small_increase_ok)
+			yaffs_resize_file_down(obj, old_file_size);
+	}
+
+	if (!small_increase_ok &&
+	    obj->parent &&
+	    obj->parent->obj_id != YAFFS_OBJECTID_UNLINKED &&
+	    obj->parent->obj_id != YAFFS_OBJECTID_DELETED) {
+		/* Write a hole start header with the old file size */
+		yaffs_update_oh(obj, NULL, 0, 1, 0, NULL);
+	}
+
+	return result;
+}
+
+struct yaffs_block_index {
+	int seq;
+	int block;
+};
+
+static int yaffs2_ybicmp(const void *a, const void *b)
+{
+	int aseq = ((struct yaffs_block_index *)a)->seq;
+	int bseq = ((struct yaffs_block_index *)b)->seq;
+	int ablock = ((struct yaffs_block_index *)a)->block;
+	int bblock = ((struct yaffs_block_index *)b)->block;
+
+	if (aseq == bseq)
+		return ablock - bblock;
+
+	return aseq - bseq;
+}
+
+static inline int yaffs2_scan_chunk(struct yaffs_dev *dev,
+		struct yaffs_block_info *bi,
+		int blk, int chunk_in_block,
+		int *found_chunks,
+		u8 *chunk_data,
+		struct list_head *hard_list,
+		int summary_available)
+{
+	struct yaffs_obj_hdr *oh;
+	struct yaffs_obj *in;
+	struct yaffs_obj *parent;
+	int equiv_id;
+	loff_t file_size;
+	int is_shrink;
+	int is_unlinked;
+	struct yaffs_ext_tags tags;
+	int alloc_failed = 0;
+	int chunk = blk * dev->param.chunks_per_block + chunk_in_block;
+	struct yaffs_file_var *file_var;
+	struct yaffs_hardlink_var *hl_var;
+	struct yaffs_symlink_var *sl_var;
+
+	if (summary_available) {
+		yaffs_summary_fetch(dev, &tags, chunk_in_block);
+		tags.seq_number = bi->seq_number;
+	}
+
+	if (!summary_available || tags.obj_id == 0) {
+		yaffs_rd_chunk_tags_nand(dev, chunk, NULL, &tags);
+		dev->tags_used++;
+	} else {
+		dev->summary_used++;
+	}
+
+	/* Let's have a good look at this chunk... */
+
+	if (!tags.chunk_used) {
+		/* An unassigned chunk in the block.
+		 * If there are used chunks after this one, then
+		 * it is a chunk that was skipped due to failing
+		 * the erased check. Just skip it so that it can
+		 * be deleted.
+		 * But, more typically, We get here when this is
+		 * an unallocated chunk and his means that
+		 * either the block is empty or this is the one
+		 * being allocated from
+		 */
+
+		if (*found_chunks) {
+			/* This is a chunk that was skipped due
+			 * to failing the erased check */
+		} else if (chunk_in_block == 0) {
+			/* We're looking at the first chunk in
+			 * the block so the block is unused */
+			bi->block_state = YAFFS_BLOCK_STATE_EMPTY;
+			dev->n_erased_blocks++;
+		} else {
+			if (bi->block_state == YAFFS_BLOCK_STATE_NEEDS_SCAN ||
+			    bi->block_state == YAFFS_BLOCK_STATE_ALLOCATING) {
+				if (dev->seq_number == bi->seq_number) {
+					/* Allocating from this block*/
+					yaffs_trace(YAFFS_TRACE_SCAN,
+					    " Allocating from %d %d",
+					    blk, chunk_in_block);
+
+					bi->block_state =
+						YAFFS_BLOCK_STATE_ALLOCATING;
+					dev->alloc_block = blk;
+					dev->alloc_page = chunk_in_block;
+					dev->alloc_block_finder = blk;
+				} else {
+					/* This is a partially written block
+					 * that is not the current
+					 * allocation block.
+					 */
+					yaffs_trace(YAFFS_TRACE_SCAN,
+						"Partially written block %d detected. gc will fix this.",
+						blk);
+				}
+			}
+		}
+
+		dev->n_free_chunks++;
+
+	} else if (tags.ecc_result ==
+		YAFFS_ECC_RESULT_UNFIXED) {
+		yaffs_trace(YAFFS_TRACE_SCAN,
+			" Unfixed ECC in chunk(%d:%d), chunk ignored",
+			blk, chunk_in_block);
+			dev->n_free_chunks++;
+	} else if (tags.obj_id > YAFFS_MAX_OBJECT_ID ||
+		   tags.chunk_id > YAFFS_MAX_CHUNK_ID ||
+		   tags.obj_id == YAFFS_OBJECTID_SUMMARY ||
+		   (tags.chunk_id > 0 &&
+		     tags.n_bytes > dev->data_bytes_per_chunk) ||
+		   tags.seq_number != bi->seq_number) {
+		yaffs_trace(YAFFS_TRACE_SCAN,
+			"Chunk (%d:%d) with bad tags:obj = %d, chunk_id = %d, n_bytes = %d, ignored",
+			blk, chunk_in_block, tags.obj_id,
+			tags.chunk_id, tags.n_bytes);
+		dev->n_free_chunks++;
+	} else if (tags.chunk_id > 0) {
+		/* chunk_id > 0 so it is a data chunk... */
+		loff_t endpos;
+		loff_t chunk_base = (tags.chunk_id - 1) *
+					dev->data_bytes_per_chunk;
+
+		*found_chunks = 1;
+
+		yaffs_set_chunk_bit(dev, blk, chunk_in_block);
+		bi->pages_in_use++;
+
+		in = yaffs_find_or_create_by_number(dev,
+					tags.obj_id,
+					YAFFS_OBJECT_TYPE_FILE);
+		if (!in)
+			/* Out of memory */
+			alloc_failed = 1;
+
+		if (in &&
+		    in->variant_type == YAFFS_OBJECT_TYPE_FILE &&
+		    chunk_base < in->variant.file_variant.shrink_size) {
+			/* This has not been invalidated by
+			 * a resize */
+			if (!yaffs_put_chunk_in_file(in, tags.chunk_id,
+								chunk, -1))
+				alloc_failed = 1;
+
+			/* File size is calculated by looking at
+			 * the data chunks if we have not
+			 * seen an object header yet.
+			 * Stop this practice once we find an
+			 * object header.
+			 */
+			endpos = chunk_base + tags.n_bytes;
+
+			if (!in->valid &&
+			    in->variant.file_variant.scanned_size < endpos) {
+				in->variant.file_variant.
+				    scanned_size = endpos;
+				in->variant.file_variant.
+				    file_size = endpos;
+			}
+		} else if (in) {
+			/* This chunk has been invalidated by a
+			 * resize, or a past file deletion
+			 * so delete the chunk*/
+			yaffs_chunk_del(dev, chunk, 1, __LINE__);
+		}
+	} else {
+		/* chunk_id == 0, so it is an ObjectHeader.
+		 * Thus, we read in the object header and make
+		 * the object
+		 */
+		*found_chunks = 1;
+
+		yaffs_set_chunk_bit(dev, blk, chunk_in_block);
+		bi->pages_in_use++;
+
+		oh = NULL;
+		in = NULL;
+
+		if (tags.extra_available) {
+			in = yaffs_find_or_create_by_number(dev,
+					tags.obj_id,
+					tags.extra_obj_type);
+			if (!in)
+				alloc_failed = 1;
+		}
+
+		if (!in ||
+		    (!in->valid && dev->param.disable_lazy_load) ||
+		    tags.extra_shadows ||
+		    (!in->valid && (tags.obj_id == YAFFS_OBJECTID_ROOT ||
+				 tags.obj_id == YAFFS_OBJECTID_LOSTNFOUND))) {
+
+			/* If we don't have  valid info then we
+			 * need to read the chunk
+			 * TODO In future we can probably defer
+			 * reading the chunk and living with
+			 * invalid data until needed.
+			 */
+
+			yaffs_rd_chunk_tags_nand(dev, chunk, chunk_data, NULL);
+
+			oh = (struct yaffs_obj_hdr *)chunk_data;
+
+			if (dev->param.inband_tags) {
+				/* Fix up the header if they got
+				 * corrupted by inband tags */
+				oh->shadows_obj =
+				    oh->inband_shadowed_obj_id;
+				oh->is_shrink =
+				    oh->inband_is_shrink;
+			}
+
+			if (!in) {
+				in = yaffs_find_or_create_by_number(dev,
+							tags.obj_id, oh->type);
+				if (!in)
+					alloc_failed = 1;
+			}
+		}
+
+		if (!in) {
+			/* TODO Hoosterman we have a problem! */
+			yaffs_trace(YAFFS_TRACE_ERROR,
+				"yaffs tragedy: Could not make object for object  %d at chunk %d during scan",
+				tags.obj_id, chunk);
+			return YAFFS_FAIL;
+		}
+
+		if (in->valid) {
+			/* We have already filled this one.
+			 * We have a duplicate that will be
+			 * discarded, but we first have to suck
+			 * out resize info if it is a file.
+			 */
+			if ((in->variant_type == YAFFS_OBJECT_TYPE_FILE) &&
+				((oh && oh->type == YAFFS_OBJECT_TYPE_FILE) ||
+				 (tags.extra_available &&
+				  tags.extra_obj_type == YAFFS_OBJECT_TYPE_FILE)
+				)) {
+				loff_t this_size = (oh) ?
+					yaffs_oh_to_size(oh) :
+					tags.extra_file_size;
+				u32 parent_obj_id = (oh) ?
+					oh->parent_obj_id :
+					tags.extra_parent_id;
+
+				is_shrink = (oh) ?
+					oh->is_shrink :
+					tags.extra_is_shrink;
+
+				/* If it is deleted (unlinked
+				 * at start also means deleted)
+				 * we treat the file size as
+				 * being zeroed at this point.
+				 */
+				if (parent_obj_id == YAFFS_OBJECTID_DELETED ||
+				    parent_obj_id == YAFFS_OBJECTID_UNLINKED) {
+					this_size = 0;
+					is_shrink = 1;
+				}
+
+				if (is_shrink &&
+				    in->variant.file_variant.shrink_size >
+				    this_size)
+					in->variant.file_variant.shrink_size =
+					this_size;
+
+				if (is_shrink)
+					bi->has_shrink_hdr = 1;
+			}
+			/* Use existing - destroy this one. */
+			yaffs_chunk_del(dev, chunk, 1, __LINE__);
+		}
+
+		if (!in->valid && in->variant_type !=
+		    (oh ? oh->type : tags.extra_obj_type))
+			yaffs_trace(YAFFS_TRACE_ERROR,
+				"yaffs tragedy: Bad object type, %d != %d, for object %d at chunk %d during scan",
+				oh ? oh->type : tags.extra_obj_type,
+				in->variant_type, tags.obj_id,
+				chunk);
+
+		if (!in->valid &&
+		    (tags.obj_id == YAFFS_OBJECTID_ROOT ||
+		     tags.obj_id == YAFFS_OBJECTID_LOSTNFOUND)) {
+			/* We only load some info, don't fiddle
+			 * with directory structure */
+			in->valid = 1;
+
+			if (oh) {
+				in->yst_mode = oh->yst_mode;
+				yaffs_load_attribs(in, oh);
+				in->lazy_loaded = 0;
+			} else {
+				in->lazy_loaded = 1;
+			}
+			in->hdr_chunk = chunk;
+
+		} else if (!in->valid) {
+			/* we need to load this info */
+			in->valid = 1;
+			in->hdr_chunk = chunk;
+			if (oh) {
+				in->variant_type = oh->type;
+				in->yst_mode = oh->yst_mode;
+				yaffs_load_attribs(in, oh);
+
+				if (oh->shadows_obj > 0)
+					yaffs_handle_shadowed_obj(dev,
+					     oh->shadows_obj, 1);
+
+				yaffs_set_obj_name_from_oh(in, oh);
+				parent = yaffs_find_or_create_by_number(dev,
+						oh->parent_obj_id,
+						YAFFS_OBJECT_TYPE_DIRECTORY);
+				file_size = yaffs_oh_to_size(oh);
+				is_shrink = oh->is_shrink;
+				equiv_id = oh->equiv_id;
+			} else {
+				in->variant_type = tags.extra_obj_type;
+				parent = yaffs_find_or_create_by_number(dev,
+						tags.extra_parent_id,
+						YAFFS_OBJECT_TYPE_DIRECTORY);
+				file_size = tags.extra_file_size;
+				is_shrink = tags.extra_is_shrink;
+				equiv_id = tags.extra_equiv_id;
+				in->lazy_loaded = 1;
+			}
+			in->dirty = 0;
+
+			if (!parent)
+				alloc_failed = 1;
+
+			/* directory stuff...
+			 * hook up to parent
+			 */
+
+			if (parent &&
+			    parent->variant_type == YAFFS_OBJECT_TYPE_UNKNOWN) {
+				/* Set up as a directory */
+				parent->variant_type =
+					YAFFS_OBJECT_TYPE_DIRECTORY;
+				INIT_LIST_HEAD(&parent->
+						variant.dir_variant.children);
+			} else if (!parent ||
+				   parent->variant_type !=
+					YAFFS_OBJECT_TYPE_DIRECTORY) {
+				/* Hoosterman, another problem....
+				 * Trying to use a non-directory as a directory
+				 */
+
+				yaffs_trace(YAFFS_TRACE_ERROR,
+					"yaffs tragedy: attempting to use non-directory as a directory in scan. Put in lost+found."
+					);
+				parent = dev->lost_n_found;
+			}
+			yaffs_add_obj_to_dir(parent, in);
+
+			is_unlinked = (parent == dev->del_dir) ||
+					(parent == dev->unlinked_dir);
+
+			if (is_shrink)
+				/* Mark the block */
+				bi->has_shrink_hdr = 1;
+
+			/* Note re hardlinks.
+			 * Since we might scan a hardlink before its equivalent
+			 * object is scanned we put them all in a list.
+			 * After scanning is complete, we should have all the
+			 * objects, so we run through this list and fix up all
+			 * the chains.
+			 */
+
+			switch (in->variant_type) {
+			case YAFFS_OBJECT_TYPE_UNKNOWN:
+				/* Todo got a problem */
+				break;
+			case YAFFS_OBJECT_TYPE_FILE:
+				file_var = &in->variant.file_variant;
+				if (file_var->scanned_size < file_size) {
+					/* This covers the case where the file
+					 * size is greater than the data held.
+					 * This will happen if the file is
+					 * resized to be larger than its
+					 * current data extents.
+					 */
+					file_var->file_size = file_size;
+					file_var->scanned_size = file_size;
+				}
+
+				if (file_var->shrink_size > file_size)
+					file_var->shrink_size = file_size;
+
+				break;
+			case YAFFS_OBJECT_TYPE_HARDLINK:
+				hl_var = &in->variant.hardlink_variant;
+				if (!is_unlinked) {
+					hl_var->equiv_id = equiv_id;
+					list_add(&in->hard_links, hard_list);
+				}
+				break;
+			case YAFFS_OBJECT_TYPE_DIRECTORY:
+				/* Do nothing */
+				break;
+			case YAFFS_OBJECT_TYPE_SPECIAL:
+				/* Do nothing */
+				break;
+			case YAFFS_OBJECT_TYPE_SYMLINK:
+				sl_var = &in->variant.symlink_variant;
+				if (oh) {
+					sl_var->alias =
+					    yaffs_clone_str(oh->alias);
+					if (!sl_var->alias)
+						alloc_failed = 1;
+				}
+				break;
+			}
+		}
+	}
+	return alloc_failed ? YAFFS_FAIL : YAFFS_OK;
+}
+
+int yaffs2_scan_backwards(struct yaffs_dev *dev)
+{
+	int blk;
+	int block_iter;
+	int start_iter;
+	int end_iter;
+	int n_to_scan = 0;
+	enum yaffs_block_state state;
+	int c;
+	LIST_HEAD(hard_list);
+	struct yaffs_block_info *bi;
+	u32 seq_number;
+	int n_blocks = dev->internal_end_block - dev->internal_start_block + 1;
+	u8 *chunk_data;
+	int found_chunks;
+	int alloc_failed = 0;
+	struct yaffs_block_index *block_index = NULL;
+	int alt_block_index = 0;
+	int summary_available;
+
+	yaffs_trace(YAFFS_TRACE_SCAN,
+		"yaffs2_scan_backwards starts  intstartblk %d intendblk %d...",
+		dev->internal_start_block, dev->internal_end_block);
+
+	dev->seq_number = YAFFS_LOWEST_SEQUENCE_NUMBER;
+
+	block_index =
+		kmalloc(n_blocks * sizeof(struct yaffs_block_index), GFP_NOFS);
+
+	if (!block_index) {
+		block_index =
+		    vmalloc(n_blocks * sizeof(struct yaffs_block_index));
+		alt_block_index = 1;
+	}
+
+	if (!block_index) {
+		yaffs_trace(YAFFS_TRACE_SCAN,
+			"yaffs2_scan_backwards() could not allocate block index!"
+			);
+		return YAFFS_FAIL;
+	}
+
+	dev->blocks_in_checkpt = 0;
+
+	chunk_data = yaffs_get_temp_buffer(dev);
+
+	/* Scan all the blocks to determine their state */
+	bi = dev->block_info;
+	for (blk = dev->internal_start_block; blk <= dev->internal_end_block;
+	     blk++) {
+		yaffs_clear_chunk_bits(dev, blk);
+		bi->pages_in_use = 0;
+		bi->soft_del_pages = 0;
+
+		yaffs_query_init_block_state(dev, blk, &state, &seq_number);
+
+		bi->block_state = state;
+		bi->seq_number = seq_number;
+
+		if (bi->seq_number == YAFFS_SEQUENCE_CHECKPOINT_DATA)
+			bi->block_state = YAFFS_BLOCK_STATE_CHECKPOINT;
+		if (bi->seq_number == YAFFS_SEQUENCE_BAD_BLOCK)
+			bi->block_state = YAFFS_BLOCK_STATE_DEAD;
+
+		yaffs_trace(YAFFS_TRACE_SCAN_DEBUG,
+			"Block scanning block %d state %d seq %d",
+			blk, bi->block_state, seq_number);
+
+		if (bi->block_state == YAFFS_BLOCK_STATE_CHECKPOINT) {
+			dev->blocks_in_checkpt++;
+
+		} else if (bi->block_state == YAFFS_BLOCK_STATE_DEAD) {
+			yaffs_trace(YAFFS_TRACE_BAD_BLOCKS,
+				"block %d is bad", blk);
+		} else if (bi->block_state == YAFFS_BLOCK_STATE_EMPTY) {
+			yaffs_trace(YAFFS_TRACE_SCAN_DEBUG, "Block empty ");
+			dev->n_erased_blocks++;
+			dev->n_free_chunks += dev->param.chunks_per_block;
+		} else if (bi->block_state ==
+				YAFFS_BLOCK_STATE_NEEDS_SCAN) {
+			/* Determine the highest sequence number */
+			if (seq_number >= YAFFS_LOWEST_SEQUENCE_NUMBER &&
+			    seq_number < YAFFS_HIGHEST_SEQUENCE_NUMBER) {
+				block_index[n_to_scan].seq = seq_number;
+				block_index[n_to_scan].block = blk;
+				n_to_scan++;
+				if (seq_number >= dev->seq_number)
+					dev->seq_number = seq_number;
+			} else {
+				/* TODO: Nasty sequence number! */
+				yaffs_trace(YAFFS_TRACE_SCAN,
+					"Block scanning block %d has bad sequence number %d",
+					blk, seq_number);
+			}
+		}
+		bi++;
+	}
+
+	yaffs_trace(YAFFS_TRACE_SCAN, "%d blocks to be sorted...", n_to_scan);
+
+	cond_resched();
+
+	/* Sort the blocks by sequence number */
+	sort(block_index, n_to_scan, sizeof(struct yaffs_block_index),
+		   yaffs2_ybicmp, NULL);
+
+	cond_resched();
+
+	yaffs_trace(YAFFS_TRACE_SCAN, "...done");
+
+	/* Now scan the blocks looking at the data. */
+	start_iter = 0;
+	end_iter = n_to_scan - 1;
+	yaffs_trace(YAFFS_TRACE_SCAN_DEBUG, "%d blocks to scan", n_to_scan);
+
+	/* For each block.... backwards */
+	for (block_iter = end_iter;
+	     !alloc_failed && block_iter >= start_iter;
+	     block_iter--) {
+		/* Cooperative multitasking! This loop can run for so
+		   long that watchdog timers expire. */
+		cond_resched();
+
+		/* get the block to scan in the correct order */
+		blk = block_index[block_iter].block;
+		bi = yaffs_get_block_info(dev, blk);
+
+		summary_available = yaffs_summary_read(dev, dev->sum_tags, blk);
+
+		/* For each chunk in each block that needs scanning.... */
+		found_chunks = 0;
+		if (summary_available)
+			c = dev->chunks_per_summary - 1;
+		else
+			c = dev->param.chunks_per_block - 1;
+
+		for (/* c is already initialised */;
+		     !alloc_failed && c >= 0 &&
+		     (bi->block_state == YAFFS_BLOCK_STATE_NEEDS_SCAN ||
+		      bi->block_state == YAFFS_BLOCK_STATE_ALLOCATING);
+		      c--) {
+			/* Scan backwards...
+			 * Read the tags and decide what to do
+			 */
+			if (yaffs2_scan_chunk(dev, bi, blk, c,
+					&found_chunks, chunk_data,
+					&hard_list, summary_available) ==
+					YAFFS_FAIL)
+				alloc_failed = 1;
+		}
+
+		if (bi->block_state == YAFFS_BLOCK_STATE_NEEDS_SCAN) {
+			/* If we got this far while scanning, then the block
+			 * is fully allocated. */
+			bi->block_state = YAFFS_BLOCK_STATE_FULL;
+		}
+
+		/* Now let's see if it was dirty */
+		if (bi->pages_in_use == 0 &&
+		    !bi->has_shrink_hdr &&
+		    bi->block_state == YAFFS_BLOCK_STATE_FULL) {
+			yaffs_block_became_dirty(dev, blk);
+		}
+	}
+
+	yaffs_skip_rest_of_block(dev);
+
+	if (alt_block_index)
+		vfree(block_index);
+	else
+		kfree(block_index);
+
+	/* Ok, we've done all the scanning.
+	 * Fix up the hard link chains.
+	 * We have scanned all the objects, now it's time to add these
+	 * hardlinks.
+	 */
+	yaffs_link_fixup(dev, &hard_list);
+
+	yaffs_release_temp_buffer(dev, chunk_data);
+
+	if (alloc_failed)
+		return YAFFS_FAIL;
+
+	yaffs_trace(YAFFS_TRACE_SCAN, "yaffs2_scan_backwards ends");
+
+	return YAFFS_OK;
+}
diff --git a/fs/yaffs2/yaffs_yaffs2.h b/fs/yaffs2/yaffs_yaffs2.h
new file mode 100644
index 0000000000..2363bfd8bc
--- /dev/null
+++ b/fs/yaffs2/yaffs_yaffs2.h
@@ -0,0 +1,39 @@
+/*
+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
+ *
+ * Copyright (C) 2002-2011 Aleph One Ltd.
+ *   for Toby Churchill Ltd and Brightstar Engineering
+ *
+ * Created by Charles Manning <charles@aleph1.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License version 2.1 as
+ * published by the Free Software Foundation.
+ *
+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL.
+ */
+
+#ifndef __YAFFS_YAFFS2_H__
+#define __YAFFS_YAFFS2_H__
+
+#include "yaffs_guts.h"
+
+void yaffs_calc_oldest_dirty_seq(struct yaffs_dev *dev);
+void yaffs2_find_oldest_dirty_seq(struct yaffs_dev *dev);
+void yaffs2_clear_oldest_dirty_seq(struct yaffs_dev *dev,
+				   struct yaffs_block_info *bi);
+void yaffs2_update_oldest_dirty_seq(struct yaffs_dev *dev, unsigned block_no,
+				    struct yaffs_block_info *bi);
+int yaffs_block_ok_for_gc(struct yaffs_dev *dev, struct yaffs_block_info *bi);
+u32 yaffs2_find_refresh_block(struct yaffs_dev *dev);
+int yaffs2_checkpt_required(struct yaffs_dev *dev);
+int yaffs_calc_checkpt_blocks_required(struct yaffs_dev *dev);
+
+void yaffs2_checkpt_invalidate(struct yaffs_dev *dev);
+int yaffs2_checkpt_save(struct yaffs_dev *dev);
+int yaffs2_checkpt_restore(struct yaffs_dev *dev);
+
+int yaffs2_handle_hole(struct yaffs_obj *obj, loff_t new_size);
+int yaffs2_scan_backwards(struct yaffs_dev *dev);
+
+#endif
diff --git a/fs/yaffs2/yaffscfg.c b/fs/yaffs2/yaffscfg.c
deleted file mode 100644
index 01399ea8a2..0000000000
--- a/fs/yaffs2/yaffscfg.c
+++ /dev/null
@@ -1,420 +0,0 @@
-/*
- * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
- *
- * Copyright (C) 2002-2007 Aleph One Ltd.
- *   for Toby Churchill Ltd and Brightstar Engineering
- *
- * Created by Charles Manning <charles@aleph1.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/*
- * yaffscfg.c  The configuration for the "direct" use of yaffs.
- *
- * This file is intended to be modified to your requirements.
- * There is no need to redistribute this file.
- */
-
-/* XXX U-BOOT XXX */
-#include <common.h>
-
-#include <config.h>
-#include "nand.h"
-#include "yaffscfg.h"
-#include "yaffsfs.h"
-#include "yaffs_packedtags2.h"
-#include "yaffs_mtdif.h"
-#include "yaffs_mtdif2.h"
-#if 0
-#include <errno.h>
-#else
-#include "malloc.h"
-#endif
-
-unsigned yaffs_traceMask = 0x0; /* Disable logging */
-static int yaffs_errno = 0;
-
-void yaffsfs_SetError(int err)
-{
-	//Do whatever to set error
-	yaffs_errno = err;
-}
-
-int yaffsfs_GetError(void)
-{
-	return yaffs_errno;
-}
-
-void yaffsfs_Lock(void)
-{
-}
-
-void yaffsfs_Unlock(void)
-{
-}
-
-__u32 yaffsfs_CurrentTime(void)
-{
-	return 0;
-}
-
-void *yaffs_malloc(size_t size)
-{
-	return malloc(size);
-}
-
-void yaffs_free(void *ptr)
-{
-	free(ptr);
-}
-
-void yaffsfs_LocalInitialisation(void)
-{
-	// Define locking semaphore.
-}
-
-// Configuration for:
-// /ram  2MB ramdisk
-// /boot 2MB boot disk (flash)
-// /flash 14MB flash disk (flash)
-// NB Though /boot and /flash occupy the same physical device they
-// are still disticnt "yaffs_Devices. You may think of these as "partitions"
-// using non-overlapping areas in the same device.
-//
-
-#include "yaffs_ramdisk.h"
-#include "yaffs_flashif.h"
-
-static int isMounted = 0;
-#define MOUNT_POINT "/flash"
-extern nand_info_t nand_info[];
-
-/* XXX U-BOOT XXX */
-#if 0
-static yaffs_Device ramDev;
-static yaffs_Device bootDev;
-static yaffs_Device flashDev;
-#endif
-
-static yaffsfs_DeviceConfiguration yaffsfs_config[] = {
-/* XXX U-BOOT XXX */
-#if 0
-	{ "/ram", &ramDev},
-	{ "/boot", &bootDev},
-	{ "/flash", &flashDev},
-#else
-	{ MOUNT_POINT, 0},
-#endif
-	{(void *)0,(void *)0}
-};
-
-
-int yaffs_StartUp(void)
-{
-	struct mtd_info *mtd = &nand_info[0];
-	int yaffsVersion = 2;
-	int nBlocks;
-
-	yaffs_Device *flashDev = calloc(1, sizeof(yaffs_Device));
-	yaffsfs_config[0].dev = flashDev;
-
-	/* store the mtd device for later use */
-	flashDev->genericDevice = mtd;
-
-	// Stuff to configure YAFFS
-	// Stuff to initialise anything special (eg lock semaphore).
-	yaffsfs_LocalInitialisation();
-
-	// Set up devices
-
-/* XXX U-BOOT XXX */
-#if 0
-	// /ram
-	ramDev.nBytesPerChunk = 512;
-	ramDev.nChunksPerBlock = 32;
-	ramDev.nReservedBlocks = 2; // Set this smaller for RAM
-	ramDev.startBlock = 1; // Can't use block 0
-	ramDev.endBlock = 127; // Last block in 2MB.
-	ramDev.useNANDECC = 1;
-	ramDev.nShortOpCaches = 0;	// Disable caching on this device.
-	ramDev.genericDevice = (void *) 0;	// Used to identify the device in fstat.
-	ramDev.writeChunkWithTagsToNAND = yramdisk_WriteChunkWithTagsToNAND;
-	ramDev.readChunkWithTagsFromNAND = yramdisk_ReadChunkWithTagsFromNAND;
-	ramDev.eraseBlockInNAND = yramdisk_EraseBlockInNAND;
-	ramDev.initialiseNAND = yramdisk_InitialiseNAND;
-
-	// /boot
-	bootDev.nBytesPerChunk = 612;
-	bootDev.nChunksPerBlock = 32;
-	bootDev.nReservedBlocks = 5;
-	bootDev.startBlock = 1; // Can't use block 0
-	bootDev.endBlock = 127; // Last block in 2MB.
-	bootDev.useNANDECC = 0; // use YAFFS's ECC
-	bootDev.nShortOpCaches = 10; // Use caches
-	bootDev.genericDevice = (void *) 1;	// Used to identify the device in fstat.
-	bootDev.writeChunkToNAND = yflash_WriteChunkToNAND;
-	bootDev.readChunkFromNAND = yflash_ReadChunkFromNAND;
-	bootDev.eraseBlockInNAND = yflash_EraseBlockInNAND;
-	bootDev.initialiseNAND = yflash_InitialiseNAND;
-#endif
-
-		// /flash
-	flashDev->nReservedBlocks = 5;
-//  flashDev->nShortOpCaches = (options.no_cache) ? 0 : 10;
-	flashDev->nShortOpCaches = 10; // Use caches
-	flashDev->useNANDECC = 0; // do not use YAFFS's ECC
-
-	if (yaffsVersion == 2)
-	{
-		flashDev->writeChunkWithTagsToNAND = nandmtd2_WriteChunkWithTagsToNAND;
-		flashDev->readChunkWithTagsFromNAND = nandmtd2_ReadChunkWithTagsFromNAND;
-		flashDev->markNANDBlockBad = nandmtd2_MarkNANDBlockBad;
-		flashDev->queryNANDBlock = nandmtd2_QueryNANDBlock;
-		flashDev->spareBuffer = YMALLOC(mtd->oobsize);
-		flashDev->isYaffs2 = 1;
-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
-		flashDev->nDataBytesPerChunk = mtd->writesize;
-		flashDev->nChunksPerBlock = mtd->erasesize / mtd->writesize;
-#else
-		flashDev->nDataBytesPerChunk = mtd->oobblock;
-		flashDev->nChunksPerBlock = mtd->erasesize / mtd->oobblock;
-#endif
-		nBlocks = mtd->size / mtd->erasesize;
-
-		flashDev->nCheckpointReservedBlocks = 10;
-		flashDev->startBlock = 0;
-		flashDev->endBlock = nBlocks - 1;
-	}
-	else
-	{
-		flashDev->writeChunkToNAND = nandmtd_WriteChunkToNAND;
-		flashDev->readChunkFromNAND = nandmtd_ReadChunkFromNAND;
-		flashDev->isYaffs2 = 0;
-		nBlocks = mtd->size / (YAFFS_CHUNKS_PER_BLOCK * YAFFS_BYTES_PER_CHUNK);
-		flashDev->startBlock = 320;
-		flashDev->endBlock = nBlocks - 1;
-		flashDev->nChunksPerBlock = YAFFS_CHUNKS_PER_BLOCK;
-		flashDev->nDataBytesPerChunk = YAFFS_BYTES_PER_CHUNK;
-	}
-
-	/* ... and common functions */
-	flashDev->eraseBlockInNAND = nandmtd_EraseBlockInNAND;
-	flashDev->initialiseNAND = nandmtd_InitialiseNAND;
-
-	yaffs_initialise(yaffsfs_config);
-
-	return 0;
-}
-
-
-void make_a_file(char *yaffsName,char bval,int sizeOfFile)
-{
-	int outh;
-	int i;
-	unsigned char buffer[100];
-
-	outh = yaffs_open(yaffsName, O_CREAT | O_RDWR | O_TRUNC, S_IREAD | S_IWRITE);
-	if (outh < 0)
-	{
-		printf("Error opening file: %d\n", outh);
-		return;
-	}
-
-	memset(buffer,bval,100);
-
-	do{
-		i = sizeOfFile;
-		if(i > 100) i = 100;
-		sizeOfFile -= i;
-
-		yaffs_write(outh,buffer,i);
-
-	} while (sizeOfFile > 0);
-
-
-	yaffs_close(outh);
-}
-
-void read_a_file(char *fn)
-{
-	int h;
-	int i = 0;
-	unsigned char b;
-
-	h = yaffs_open(fn, O_RDWR,0);
-	if(h<0)
-	{
-		printf("File not found\n");
-		return;
-	}
-
-	while(yaffs_read(h,&b,1)> 0)
-	{
-		printf("%02x ",b);
-		i++;
-		if(i > 32)
-		{
-		   printf("\n");
-		   i = 0;;
-		 }
-	}
-	printf("\n");
-	yaffs_close(h);
-}
-
-void cmd_yaffs_mount(char *mp)
-{
-	yaffs_StartUp();
-	int retval = yaffs_mount(mp);
-	if( retval != -1)
-		isMounted = 1;
-	else
-		printf("Error mounting %s, return value: %d\n", mp, yaffsfs_GetError());
-}
-
-static void checkMount(void)
-{
-	if( !isMounted )
-	{
-		cmd_yaffs_mount(MOUNT_POINT);
-	}
-}
-
-void cmd_yaffs_umount(char *mp)
-{
-	checkMount();
-	if( yaffs_unmount(mp) == -1)
-		printf("Error umounting %s, return value: %d\n", mp, yaffsfs_GetError());
-}
-
-void cmd_yaffs_write_file(char *yaffsName,char bval,int sizeOfFile)
-{
-	checkMount();
-	make_a_file(yaffsName,bval,sizeOfFile);
-}
-
-
-void cmd_yaffs_read_file(char *fn)
-{
-	checkMount();
-	read_a_file(fn);
-}
-
-
-void cmd_yaffs_mread_file(char *fn, char *addr)
-{
-	int h;
-	struct yaffs_stat s;
-
-	checkMount();
-
-	yaffs_stat(fn,&s);
-
-	printf ("Copy %s to 0x%p... ", fn, addr);
-	h = yaffs_open(fn, O_RDWR,0);
-	if(h<0)
-	{
-		printf("File not found\n");
-		return;
-	}
-
-	yaffs_read(h,addr,(int)s.st_size);
-	printf("\t[DONE]\n");
-
-	yaffs_close(h);
-}
-
-
-void cmd_yaffs_mwrite_file(char *fn, char *addr, int size)
-{
-	int outh;
-
-	checkMount();
-	outh = yaffs_open(fn, O_CREAT | O_RDWR | O_TRUNC, S_IREAD | S_IWRITE);
-	if (outh < 0)
-	{
-		printf("Error opening file: %d\n", outh);
-	}
-
-	yaffs_write(outh,addr,size);
-
-	yaffs_close(outh);
-}
-
-
-void cmd_yaffs_ls(const char *mountpt, int longlist)
-{
-	int i;
-	yaffs_DIR *d;
-	yaffs_dirent *de;
-	struct yaffs_stat stat;
-	char tempstr[255];
-
-	checkMount();
-	d = yaffs_opendir(mountpt);
-
-	if(!d)
-	{
-		printf("opendir failed\n");
-	}
-	else
-	{
-		for(i = 0; (de = yaffs_readdir(d)) != NULL; i++)
-		{
-			if (longlist)
-			{
-				sprintf(tempstr, "%s/%s", mountpt, de->d_name);
-				yaffs_stat(tempstr, &stat);
-				printf("%-25s\t%7ld\n",de->d_name, stat.st_size);
-			}
-			else
-			{
-				printf("%s\n",de->d_name);
-			}
-		}
-	}
-}
-
-
-void cmd_yaffs_mkdir(const char *dir)
-{
-	checkMount();
-
-	int retval = yaffs_mkdir(dir, 0);
-
-	if ( retval < 0)
-		printf("yaffs_mkdir returning error: %d\n", retval);
-}
-
-void cmd_yaffs_rmdir(const char *dir)
-{
-	checkMount();
-
-	int retval = yaffs_rmdir(dir);
-
-	if ( retval < 0)
-		printf("yaffs_rmdir returning error: %d\n", retval);
-}
-
-void cmd_yaffs_rm(const char *path)
-{
-	checkMount();
-
-	int retval = yaffs_unlink(path);
-
-	if ( retval < 0)
-		printf("yaffs_unlink returning error: %d\n", retval);
-}
-
-void cmd_yaffs_mv(const char *oldPath, const char *newPath)
-{
-	checkMount();
-
-	int retval = yaffs_rename(newPath, oldPath);
-
-	if ( retval < 0)
-		printf("yaffs_unlink returning error: %d\n", retval);
-}
diff --git a/fs/yaffs2/yaffscfg.h b/fs/yaffs2/yaffscfg.h
index 3503dc863f..718504eeac 100644
--- a/fs/yaffs2/yaffscfg.h
+++ b/fs/yaffs2/yaffscfg.h
@@ -1,7 +1,7 @@
 /*
  * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
  *
- * Copyright (C) 2002-2007 Aleph One Ltd.
+ * Copyright (C) 2002-2011 Aleph One Ltd.
  *   for Toby Churchill Ltd and Brightstar Engineering
  *
  * Created by Charles Manning <charles@aleph1.co.uk>
@@ -23,23 +23,16 @@
 #define __YAFFSCFG_H__
 
 
-#include "devextras.h"
+#include "yportenv.h"
 
-#define YAFFSFS_N_HANDLES 200
+#define YAFFSFS_N_HANDLES	100
+#define YAFFSFS_N_DSC		20
 
 
-typedef struct {
-	const char *prefix;
-	struct yaffs_DeviceStruct *dev;
-} yaffsfs_DeviceConfiguration;
+struct yaffsfs_DeviceConfiguration {
+	const YCHAR *prefix;
+	struct yaffs_dev *dev;
+};
 
 
-void yaffsfs_Lock(void);
-void yaffsfs_Unlock(void);
-
-__u32 yaffsfs_CurrentTime(void);
-
-void yaffsfs_SetError(int err);
-int yaffsfs_GetError(void);
-
 #endif
diff --git a/fs/yaffs2/yaffsfs.c b/fs/yaffs2/yaffsfs.c
index 111cb348c0..ac4a010bdf 100644
--- a/fs/yaffs2/yaffsfs.c
+++ b/fs/yaffs2/yaffsfs.c
@@ -1,7 +1,7 @@
 /*
  * YAFFS: Yet Another Flash File System. A NAND-flash specific file system.
  *
- * Copyright (C) 2002-2007 Aleph One Ltd.
+ * Copyright (C) 2002-2011 Aleph One Ltd.
  *   for Toby Churchill Ltd and Brightstar Engineering
  *
  * Created by Charles Manning <charles@aleph1.co.uk>
@@ -11,19 +11,11 @@
  * published by the Free Software Foundation.
  */
 
-/* XXX U-BOOT XXX */
-#include <common.h>
-#include <malloc.h>
-
 #include "yaffsfs.h"
 #include "yaffs_guts.h"
 #include "yaffscfg.h"
 #include "yportenv.h"
-
-/* XXX U-BOOT XXX */
-#if 0
-#include <string.h> // for memset
-#endif
+#include "yaffs_trace.h"
 
 #define YAFFSFS_MAX_SYMLINK_DEREFERENCES 5
 
@@ -31,452 +23,968 @@
 #define NULL ((void *)0)
 #endif
 
+/* YAFFSFS_RW_SIZE must be a power of 2 */
+#define YAFFSFS_RW_SHIFT (13)
+#define YAFFSFS_RW_SIZE  (1<<YAFFSFS_RW_SHIFT)
 
-const char *yaffsfs_c_version="$Id: yaffsfs.c,v 1.18 2007/07/18 19:40:38 charles Exp $";
-
-// configurationList is the list of devices that are supported
-static yaffsfs_DeviceConfiguration *yaffsfs_configurationList;
+/* Some forward references */
+static struct yaffs_obj *yaffsfs_FindObject(struct yaffs_obj *relativeDirectory,
+					    const YCHAR *path,
+					    int symDepth, int getEquiv,
+					    struct yaffs_obj **dirOut,
+					    int *notDir, int *loop);
 
+static void yaffsfs_RemoveObjectCallback(struct yaffs_obj *obj);
 
-/* Some forward references */
-static yaffs_Object *yaffsfs_FindObject(yaffs_Object *relativeDirectory, const char *path, int symDepth);
-static void yaffsfs_RemoveObjectCallback(yaffs_Object *obj);
+unsigned int yaffs_wr_attempts;
 
+/*
+ * Handle management.
+ * There are open inodes in struct yaffsfs_Inode.
+ * There are open file descriptors in yaffsfs_FileDes.
+ * There are open handles in yaffsfs_FileDes.
+ *
+ * Things are structured this way to be like the Linux VFS model
+ * so that interactions with the yaffs guts calls are similar.
+ * That means more common code paths and less special code.
+ * That means better testing etc.
+ *
+ * We have 3 layers because:
+ * A handle is different than an fd because you can use dup()
+ * to create a new handle that accesses the *same* fd. The two
+ * handles will use the same offset (part of the fd). We only close
+ * down the fd when there are no more handles accessing it.
+ *
+ * More than one fd can currently access one file, but each fd
+ * has its own permsiions and offset.
+ */
 
-// Handle management.
-//
+struct yaffsfs_Inode {
+	int count;		/* Number of handles accessing this inode */
+	struct yaffs_obj *iObj;
+};
+
+struct yaffsfs_FileDes {
+	u8 reading:1;
+	u8 writing:1;
+	u8 append:1;
+	u8 shareRead:1;
+	u8 shareWrite:1;
+	int inodeId:12;		/* Index to corresponding yaffsfs_Inode */
+	int handleCount:10;	/* Number of handles for this fd */
+	loff_t position;	/* current position in file */
+};
+
+struct yaffsfs_Handle {
+	short int fdId;
+	short int useCount;
+};
+
+
+struct yaffsfs_DirSearchContxt {
+	struct yaffs_dirent de;	/* directory entry */
+	YCHAR name[NAME_MAX + 1];	/* name of directory being searched */
+	struct yaffs_obj *dirObj;	/* ptr to directory being searched */
+	struct yaffs_obj *nextReturn;	/* obj  returned by next readddir */
+	struct list_head others;
+	int offset:20;
+	unsigned inUse:1;
+};
 
+static struct yaffsfs_DirSearchContxt yaffsfs_dsc[YAFFSFS_N_DSC];
+static struct yaffsfs_Inode yaffsfs_inode[YAFFSFS_N_HANDLES];
+static struct yaffsfs_FileDes yaffsfs_fd[YAFFSFS_N_HANDLES];
+static struct yaffsfs_Handle yaffsfs_handle[YAFFSFS_N_HANDLES];
 
-unsigned int yaffs_wr_attempts;
+static int yaffsfs_handlesInitialised;
 
-typedef struct
+unsigned yaffs_set_trace(unsigned tm)
 {
-	__u8  inUse:1;		// this handle is in use
-	__u8  readOnly:1;	// this handle is read only
-	__u8  append:1;		// append only
-	__u8  exclusive:1;	// exclusive
-	__u32 position;		// current position in file
-	yaffs_Object *obj;	// the object
-}yaffsfs_Handle;
+	yaffs_trace_mask = tm;
+	return yaffs_trace_mask;
+}
 
+unsigned yaffs_get_trace(void)
+{
+	return yaffs_trace_mask;
+}
 
-static yaffsfs_Handle yaffsfs_handle[YAFFSFS_N_HANDLES];
+/*
+ * yaffsfs_InitHandle
+ * Inilitalise handle management on start-up.
+ */
 
-// yaffsfs_InitHandle
-/// Inilitalise handles on start-up.
-//
-static int yaffsfs_InitHandles(void)
+static void yaffsfs_InitHandles(void)
 {
 	int i;
-	for(i = 0; i < YAFFSFS_N_HANDLES; i++)
-	{
-		yaffsfs_handle[i].inUse = 0;
-		yaffsfs_handle[i].obj = NULL;
-	}
-	return 0;
+	if (yaffsfs_handlesInitialised)
+		return;
+
+	memset(yaffsfs_inode, 0, sizeof(yaffsfs_inode));
+	memset(yaffsfs_fd, 0, sizeof(yaffsfs_fd));
+	memset(yaffsfs_handle, 0, sizeof(yaffsfs_handle));
+	memset(yaffsfs_dsc, 0, sizeof(yaffsfs_dsc));
+
+	for (i = 0; i < YAFFSFS_N_HANDLES; i++)
+		yaffsfs_fd[i].inodeId = -1;
+	for (i = 0; i < YAFFSFS_N_HANDLES; i++)
+		yaffsfs_handle[i].fdId = -1;
 }
 
-yaffsfs_Handle *yaffsfs_GetHandlePointer(int h)
+static struct yaffsfs_Handle *yaffsfs_HandleToPointer(int h)
 {
-	if(h < 0 || h >= YAFFSFS_N_HANDLES)
-	{
-		return NULL;
-	}
+	if (h >= 0 && h < YAFFSFS_N_HANDLES)
+		return &yaffsfs_handle[h];
+	return NULL;
+}
 
-	return &yaffsfs_handle[h];
+static struct yaffsfs_FileDes *yaffsfs_HandleToFileDes(int handle)
+{
+	struct yaffsfs_Handle *h = yaffsfs_HandleToPointer(handle);
+
+	if (h && h->useCount > 0 && h->fdId >= 0 && h->fdId < YAFFSFS_N_HANDLES)
+		return &yaffsfs_fd[h->fdId];
+
+	return NULL;
 }
 
-yaffs_Object *yaffsfs_GetHandleObject(int handle)
+static struct yaffsfs_Inode *yaffsfs_HandleToInode(int handle)
 {
-	yaffsfs_Handle *h = yaffsfs_GetHandlePointer(handle);
+	struct yaffsfs_FileDes *fd = yaffsfs_HandleToFileDes(handle);
 
-	if(h && h->inUse)
-	{
-		return h->obj;
-	}
+	if (fd && fd->handleCount > 0 &&
+	    fd->inodeId >= 0 && fd->inodeId < YAFFSFS_N_HANDLES)
+		return &yaffsfs_inode[fd->inodeId];
 
 	return NULL;
 }
 
+static struct yaffs_obj *yaffsfs_HandleToObject(int handle)
+{
+	struct yaffsfs_Inode *in = yaffsfs_HandleToInode(handle);
+
+	if (in)
+		return in->iObj;
+
+	return NULL;
+}
 
-//yaffsfs_GetHandle
-// Grab a handle (when opening a file)
-//
+/*
+ * yaffsfs_FindInodeIdForObject
+ * Find the inode entry for an object, if it exists.
+ */
 
-static int yaffsfs_GetHandle(void)
+static int yaffsfs_FindInodeIdForObject(struct yaffs_obj *obj)
 {
 	int i;
-	yaffsfs_Handle *h;
-
-	for(i = 0; i < YAFFSFS_N_HANDLES; i++)
-	{
-		h = yaffsfs_GetHandlePointer(i);
-		if(!h)
-		{
-			// todo bug: should never happen
+	int ret = -1;
+
+	if (obj)
+		obj = yaffs_get_equivalent_obj(obj);
+
+	/* Look for it in open inode table */
+	for (i = 0; i < YAFFSFS_N_HANDLES && ret < 0; i++) {
+		if (yaffsfs_inode[i].iObj == obj)
+			ret = i;
+	}
+	return ret;
+}
+
+/*
+ * yaffsfs_GetInodeIdForObject
+ * Grab an inode entry when opening a new inode.
+ */
+static int yaffsfs_GetInodeIdForObject(struct yaffs_obj *obj)
+{
+	int i;
+	int ret;
+	struct yaffsfs_Inode *in = NULL;
+
+	if (obj)
+		obj = yaffs_get_equivalent_obj(obj);
+
+	ret = yaffsfs_FindInodeIdForObject(obj);
+
+	for (i = 0; i < YAFFSFS_N_HANDLES && ret < 0; i++) {
+		if (!yaffsfs_inode[i].iObj)
+			ret = i;
+	}
+
+	if (ret >= 0) {
+		in = &yaffsfs_inode[ret];
+		if (!in->iObj)
+			in->count = 0;
+		in->iObj = obj;
+		in->count++;
+	}
+
+	return ret;
+}
+
+static int yaffsfs_CountHandles(struct yaffs_obj *obj)
+{
+	int i = yaffsfs_FindInodeIdForObject(obj);
+
+	if (i >= 0)
+		return yaffsfs_inode[i].count;
+	else
+		return 0;
+}
+
+static void yaffsfs_ReleaseInode(struct yaffsfs_Inode *in)
+{
+	struct yaffs_obj *obj;
+
+	obj = in->iObj;
+
+	if (obj->unlinked)
+		yaffs_del_obj(obj);
+
+	obj->my_inode = NULL;
+	in->iObj = NULL;
+
+}
+
+static void yaffsfs_PutInode(int inodeId)
+{
+	if (inodeId >= 0 && inodeId < YAFFSFS_N_HANDLES) {
+		struct yaffsfs_Inode *in = &yaffsfs_inode[inodeId];
+		in->count--;
+		if (in->count <= 0) {
+			yaffsfs_ReleaseInode(in);
+			in->count = 0;
 		}
-		if(!h->inUse)
-		{
-			memset(h,0,sizeof(yaffsfs_Handle));
-			h->inUse=1;
+	}
+}
+
+static int yaffsfs_NewHandle(struct yaffsfs_Handle **hptr)
+{
+	int i;
+	struct yaffsfs_Handle *h;
+
+	for (i = 0; i < YAFFSFS_N_HANDLES; i++) {
+		h = &yaffsfs_handle[i];
+		if (h->useCount < 1) {
+			memset(h, 0, sizeof(struct yaffsfs_Handle));
+			h->fdId = -1;
+			h->useCount = 1;
+			if (hptr)
+				*hptr = h;
 			return i;
 		}
 	}
 	return -1;
 }
 
-// yaffs_PutHandle
-// Let go of a handle (when closing a file)
-//
-static int yaffsfs_PutHandle(int handle)
+static int yaffsfs_NewHandleAndFileDes(void)
+{
+	int i;
+	struct yaffsfs_FileDes *fd;
+	struct yaffsfs_Handle *h = NULL;
+	int handle = yaffsfs_NewHandle(&h);
+
+	if (handle < 0)
+		return -1;
+
+	for (i = 0; i < YAFFSFS_N_HANDLES; i++) {
+		fd = &yaffsfs_fd[i];
+		if (fd->handleCount < 1) {
+			memset(fd, 0, sizeof(struct yaffsfs_FileDes));
+			fd->inodeId = -1;
+			fd->handleCount = 1;
+			h->fdId = i;
+			return handle;
+		}
+	}
+
+	/* Dump the handle because we could not get a fd */
+	h->useCount = 0;
+	return -1;
+}
+
+/*
+ * yaffs_get_handle
+ * Increase use of handle when reading/writing a file
+ * Also gets the file descriptor.
+ */
+
+static int yaffsfs_GetHandle(int handle)
 {
-	yaffsfs_Handle *h = yaffsfs_GetHandlePointer(handle);
+	struct yaffsfs_Handle *h = yaffsfs_HandleToPointer(handle);
 
-	if(h)
-	{
-		h->inUse = 0;
-		h->obj = NULL;
+	if (h && h->useCount > 0) {
+		h->useCount++;
+		return 0;
+	}
+	return -1;
+}
+
+/*
+ * yaffs_put_handle
+ * Let go of a handle when closing a file or aborting an open or
+ * ending a read or write.
+ */
+
+static int yaffsfs_PutFileDes(int fdId)
+{
+	struct yaffsfs_FileDes *fd;
+
+	if (fdId >= 0 && fdId < YAFFSFS_N_HANDLES) {
+		fd = &yaffsfs_fd[fdId];
+		fd->handleCount--;
+		if (fd->handleCount < 1) {
+			if (fd->inodeId >= 0) {
+				yaffsfs_PutInode(fd->inodeId);
+				fd->inodeId = -1;
+			}
+		}
 	}
 	return 0;
 }
 
+static int yaffsfs_PutHandle(int handle)
+{
+	struct yaffsfs_Handle *h = yaffsfs_HandleToPointer(handle);
 
+	if (h && h->useCount > 0) {
+		h->useCount--;
+		if (h->useCount < 1) {
+			yaffsfs_PutFileDes(h->fdId);
+			h->fdId = -1;
+		}
+	}
 
-// Stuff to search for a directory from a path
+	return 0;
+}
 
+static void yaffsfs_BreakDeviceHandles(struct yaffs_dev *dev)
+{
+	struct yaffsfs_FileDes *fd;
+	struct yaffsfs_Handle *h;
+	struct yaffs_obj *obj;
+	int i;
+	for (i = 0; i < YAFFSFS_N_HANDLES; i++) {
+		h = yaffsfs_HandleToPointer(i);
+		fd = yaffsfs_HandleToFileDes(i);
+		obj = yaffsfs_HandleToObject(i);
+		if (h && h->useCount > 0) {
+			h->useCount = 0;
+			h->fdId = 0;
+		}
+		if (fd && fd->handleCount > 0 && obj && obj->my_dev == dev) {
+			fd->handleCount = 0;
+			yaffsfs_PutInode(fd->inodeId);
+			fd->inodeId = -1;
+		}
+	}
+}
 
-int yaffsfs_Match(char a, char b)
+/*
+ *  Stuff to handle names.
+ */
+#ifdef CONFIG_YAFFS_CASE_INSENSITIVE
+
+static int yaffs_toupper(YCHAR a)
+{
+	if (a >= 'a' && a <= 'z')
+		return (a - 'a') + 'A';
+	else
+		return a;
+}
+
+int yaffsfs_Match(YCHAR a, YCHAR b)
+{
+	return (yaffs_toupper(a) == yaffs_toupper(b));
+}
+#else
+int yaffsfs_Match(YCHAR a, YCHAR b)
 {
-	// case sensitive
+	/* case sensitive */
 	return (a == b);
 }
+#endif
 
-// yaffsfs_FindDevice
-// yaffsfs_FindRoot
-// Scan the configuration list to find the root.
-// Curveballs: Should match paths that end in '/' too
-// Curveball2 Might have "/x/ and "/x/y". Need to return the longest match
-static yaffs_Device *yaffsfs_FindDevice(const char *path, char **restOfPath)
+int yaffsfs_IsPathDivider(YCHAR ch)
 {
-	yaffsfs_DeviceConfiguration *cfg = yaffsfs_configurationList;
-	const char *leftOver;
-	const char *p;
-	yaffs_Device *retval = NULL;
+	const YCHAR *str = YAFFS_PATH_DIVIDERS;
+
+	while (*str) {
+		if (*str == ch)
+			return 1;
+		str++;
+	}
+
+	return 0;
+}
+
+int yaffsfs_CheckNameLength(const char *name)
+{
+	int retVal = 0;
+
+	int nameLength = yaffs_strnlen(name, YAFFS_MAX_NAME_LENGTH + 1);
+
+	if (nameLength == 0) {
+		yaffsfs_SetError(-ENOENT);
+		retVal = -1;
+	} else if (nameLength > YAFFS_MAX_NAME_LENGTH) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		retVal = -1;
+	}
+
+	return retVal;
+}
+
+static int yaffsfs_alt_dir_path(const YCHAR *path, YCHAR **ret_path)
+{
+	YCHAR *alt_path = NULL;
+	int path_length;
+	int i;
+
+	/*
+	 * We don't have a definition for max path length.
+	 * We will use 3 * max name length instead.
+	 */
+	*ret_path = NULL;
+	path_length = yaffs_strnlen(path, (YAFFS_MAX_NAME_LENGTH + 1) * 3 + 1);
+
+	/* If the last character is a path divider, then we need to
+	 * trim it back so that the name look-up works properly.
+	 * eg. /foo/new_dir/ -> /foo/newdir
+	 * Curveball: Need to handle multiple path dividers:
+	 * eg. /foof/sdfse///// -> /foo/sdfse
+	 */
+	if (path_length > 0 && yaffsfs_IsPathDivider(path[path_length - 1])) {
+		alt_path = kmalloc(path_length + 1, 0);
+		if (!alt_path)
+			return -1;
+		yaffs_strcpy(alt_path, path);
+		for (i = path_length - 1;
+		     i >= 0 && yaffsfs_IsPathDivider(alt_path[i]); i--)
+			alt_path[i] = (YCHAR) 0;
+	}
+	*ret_path = alt_path;
+	return 0;
+}
+
+LIST_HEAD(yaffsfs_deviceList);
+
+/*
+ * yaffsfs_FindDevice
+ * yaffsfs_FindRoot
+ * Scan the configuration list to find the device
+ * Curveballs: Should match paths that end in '/' too
+ * Curveball2 Might have "/x/ and "/x/y". Need to return the longest match
+ */
+static struct yaffs_dev *yaffsfs_FindDevice(const YCHAR *path,
+					    YCHAR **restOfPath)
+{
+	struct list_head *cfg;
+	const YCHAR *leftOver;
+	const YCHAR *p;
+	struct yaffs_dev *retval = NULL;
+	struct yaffs_dev *dev = NULL;
 	int thisMatchLength;
 	int longestMatch = -1;
+	int matching;
 
-	// Check all configs, choose the one that:
-	// 1) Actually matches a prefix (ie /a amd /abc will not match
-	// 2) Matches the longest.
-	while(cfg && cfg->prefix && cfg->dev)
-	{
+	/*
+	 * Check all configs, choose the one that:
+	 * 1) Actually matches a prefix (ie /a amd /abc will not match
+	 * 2) Matches the longest.
+	 */
+	list_for_each(cfg, &yaffsfs_deviceList) {
+		dev = list_entry(cfg, struct yaffs_dev, dev_list);
 		leftOver = path;
-		p = cfg->prefix;
+		p = dev->param.name;
 		thisMatchLength = 0;
+		matching = 1;
+
+		while (matching && *p && *leftOver) {
+			/* Skip over any /s */
+			while (yaffsfs_IsPathDivider(*p))
+				p++;
+
+			/* Skip over any /s */
+			while (yaffsfs_IsPathDivider(*leftOver))
+				leftOver++;
+
+			/* Now match the text part */
+			while (matching &&
+			       *p && !yaffsfs_IsPathDivider(*p) &&
+			       *leftOver && !yaffsfs_IsPathDivider(*leftOver)) {
+				if (yaffsfs_Match(*p, *leftOver)) {
+					p++;
+					leftOver++;
+					thisMatchLength++;
+				} else {
+					matching = 0;
+				}
+			}
+		}
 
-		while(*p &&  //unmatched part of prefix
-		      strcmp(p,"/") && // the rest of the prefix is not / (to catch / at end)
-		      *leftOver &&
-		      yaffsfs_Match(*p,*leftOver))
-		{
-			p++;
+		/* Skip over any /s in leftOver */
+		while (yaffsfs_IsPathDivider(*leftOver))
 			leftOver++;
-			thisMatchLength++;
-		}
-		if((!*p || strcmp(p,"/") == 0) &&      // end of prefix
-		   (!*leftOver || *leftOver == '/') && // no more in this path name part
-		   (thisMatchLength > longestMatch))
-		{
-			// Matched prefix
-			*restOfPath = (char *)leftOver;
-			retval = cfg->dev;
+
+		/*Skip over any /s in p */
+		while (yaffsfs_IsPathDivider(*p))
+			p++;
+
+		/* p should now be at the end of the string if fully matched */
+		if (*p)
+			matching = 0;
+
+		if (matching && (thisMatchLength > longestMatch)) {
+			/* Matched prefix */
+			*restOfPath = (YCHAR *) leftOver;
+			retval = dev;
 			longestMatch = thisMatchLength;
 		}
-		cfg++;
+
 	}
 	return retval;
 }
 
-static yaffs_Object *yaffsfs_FindRoot(const char *path, char **restOfPath)
+static int yaffsfs_CheckPath(const YCHAR *path)
 {
+	int n = 0;
+	int divs = 0;
 
-	yaffs_Device *dev;
-
-	dev= yaffsfs_FindDevice(path,restOfPath);
-	if(dev && dev->isMounted)
-	{
-		return dev->rootDir;
+	while (*path && n < YAFFS_MAX_NAME_LENGTH && divs < 100) {
+		if (yaffsfs_IsPathDivider(*path)) {
+			n = 0;
+			divs++;
+		} else
+			n++;
+		path++;
 	}
+
+	return (*path) ? -1 : 0;
+}
+
+/* FindMountPoint only returns a dev entry if the path is a mount point */
+static struct yaffs_dev *yaffsfs_FindMountPoint(const YCHAR *path)
+{
+	struct yaffs_dev *dev;
+	YCHAR *restOfPath = NULL;
+
+	dev = yaffsfs_FindDevice(path, &restOfPath);
+	if (dev && restOfPath && *restOfPath)
+		dev = NULL;
+	return dev;
+}
+
+static struct yaffs_obj *yaffsfs_FindRoot(const YCHAR *path,
+					  YCHAR **restOfPath)
+{
+	struct yaffs_dev *dev;
+
+	dev = yaffsfs_FindDevice(path, restOfPath);
+	if (dev && dev->is_mounted)
+		return dev->root_dir;
+
 	return NULL;
 }
 
-static yaffs_Object *yaffsfs_FollowLink(yaffs_Object *obj,int symDepth)
+static struct yaffs_obj *yaffsfs_FollowLink(struct yaffs_obj *obj,
+					    int symDepth, int *loop)
 {
 
-	while(obj && obj->variantType == YAFFS_OBJECT_TYPE_SYMLINK)
-	{
-		char *alias = obj->variant.symLinkVariant.alias;
+	if (obj)
+		obj = yaffs_get_equivalent_obj(obj);
 
-		if(*alias == '/')
-		{
-			// Starts with a /, need to scan from root up
-			obj = yaffsfs_FindObject(NULL,alias,symDepth++);
-		}
+	while (obj && obj->variant_type == YAFFS_OBJECT_TYPE_SYMLINK) {
+		YCHAR *alias = obj->variant.symlink_variant.alias;
+
+		if (yaffsfs_IsPathDivider(*alias))
+			/* Starts with a /, need to scan from root up */
+			obj = yaffsfs_FindObject(NULL, alias, symDepth++,
+						 1, NULL, NULL, loop);
 		else
-		{
-			// Relative to here, so use the parent of the symlink as a start
-			obj = yaffsfs_FindObject(obj->parent,alias,symDepth++);
-		}
+			/*
+			 * Relative to here so use the parent of the
+			 * symlink as a start
+			 */
+			obj = yaffsfs_FindObject(obj->parent, alias, symDepth++,
+						 1, NULL, NULL, loop);
 	}
 	return obj;
 }
 
-
-// yaffsfs_FindDirectory
-// Parse a path to determine the directory and the name within the directory.
-//
-// eg. "/data/xx/ff" --> puts name="ff" and returns the directory "/data/xx"
-static yaffs_Object *yaffsfs_DoFindDirectory(yaffs_Object *startDir,const char *path,char **name,int symDepth)
+/*
+ * yaffsfs_FindDirectory
+ * Parse a path to determine the directory and the name within the directory.
+ *
+ * eg. "/data/xx/ff" --> puts name="ff" and returns the directory "/data/xx"
+ */
+static struct yaffs_obj *yaffsfs_DoFindDirectory(struct yaffs_obj *startDir,
+						 const YCHAR *path,
+						 YCHAR **name, int symDepth,
+						 int *notDir, int *loop)
 {
-	yaffs_Object *dir;
-	char *restOfPath;
-	char str[YAFFS_MAX_NAME_LENGTH+1];
+	struct yaffs_obj *dir;
+	YCHAR *restOfPath;
+	YCHAR str[YAFFS_MAX_NAME_LENGTH + 1];
 	int i;
 
-	if(symDepth > YAFFSFS_MAX_SYMLINK_DEREFERENCES)
-	{
+	if (symDepth > YAFFSFS_MAX_SYMLINK_DEREFERENCES) {
+		if (loop)
+			*loop = 1;
 		return NULL;
 	}
 
-	if(startDir)
-	{
+	if (startDir) {
 		dir = startDir;
-		restOfPath = (char *)path;
-	}
-	else
-	{
-		dir = yaffsfs_FindRoot(path,&restOfPath);
-	}
-
-	while(dir)
-	{
-		// parse off /.
-		// curve ball: also throw away surplus '/'
-		// eg. "/ram/x////ff" gets treated the same as "/ram/x/ff"
-		while(*restOfPath == '/')
-		{
-			restOfPath++; // get rid of '/'
-		}
+		restOfPath = (YCHAR *) path;
+	} else
+		dir = yaffsfs_FindRoot(path, &restOfPath);
+
+	while (dir) {
+		/*
+		 * parse off /.
+		 * curve ball: also throw away surplus '/'
+		 * eg. "/ram/x////ff" gets treated the same as "/ram/x/ff"
+		 */
+		while (yaffsfs_IsPathDivider(*restOfPath))
+			restOfPath++;	/* get rid of '/' */
 
 		*name = restOfPath;
 		i = 0;
 
-		while(*restOfPath && *restOfPath != '/')
-		{
-			if (i < YAFFS_MAX_NAME_LENGTH)
-			{
+		while (*restOfPath && !yaffsfs_IsPathDivider(*restOfPath)) {
+			if (i < YAFFS_MAX_NAME_LENGTH) {
 				str[i] = *restOfPath;
-				str[i+1] = '\0';
+				str[i + 1] = '\0';
 				i++;
 			}
 			restOfPath++;
 		}
 
-		if(!*restOfPath)
-		{
-			// got to the end of the string
+		if (!*restOfPath)
+			/* got to the end of the string */
 			return dir;
-		}
-		else
-		{
-			if(strcmp(str,".") == 0)
-			{
-				// Do nothing
-			}
-			else if(strcmp(str,"..") == 0)
-			{
+		else {
+			if (yaffs_strcmp(str, _Y(".")) == 0) {
+				/* Do nothing */
+			} else if (yaffs_strcmp(str, _Y("..")) == 0) {
 				dir = dir->parent;
-			}
-			else
-			{
-				dir = yaffs_FindObjectByName(dir,str);
-
-				while(dir && dir->variantType == YAFFS_OBJECT_TYPE_SYMLINK)
-				{
+			} else {
+				dir = yaffs_find_by_name(dir, str);
 
-					dir = yaffsfs_FollowLink(dir,symDepth);
+				dir = yaffsfs_FollowLink(dir, symDepth, loop);
 
-				}
-
-				if(dir && dir->variantType != YAFFS_OBJECT_TYPE_DIRECTORY)
-				{
+				if (dir && dir->variant_type !=
+				    YAFFS_OBJECT_TYPE_DIRECTORY) {
+					if (notDir)
+						*notDir = 1;
 					dir = NULL;
 				}
+
 			}
 		}
 	}
-	// directory did not exist.
+	/* directory did not exist. */
 	return NULL;
 }
 
-static yaffs_Object *yaffsfs_FindDirectory(yaffs_Object *relativeDirectory,const char *path,char **name,int symDepth)
+static struct yaffs_obj *yaffsfs_FindDirectory(struct yaffs_obj *relDir,
+					       const YCHAR *path,
+					       YCHAR **name,
+					       int symDepth,
+					       int *notDir, int *loop)
 {
-	return yaffsfs_DoFindDirectory(relativeDirectory,path,name,symDepth);
+	return yaffsfs_DoFindDirectory(relDir, path, name, symDepth, notDir,
+						loop);
 }
 
-// yaffsfs_FindObject turns a path for an existing object into the object
-//
-static yaffs_Object *yaffsfs_FindObject(yaffs_Object *relativeDirectory, const char *path,int symDepth)
+/*
+ * yaffsfs_FindObject turns a path for an existing object into the object
+ */
+static struct yaffs_obj *yaffsfs_FindObject(struct yaffs_obj *relDir,
+					    const YCHAR *path, int symDepth,
+					    int getEquiv,
+					    struct yaffs_obj **dirOut,
+					    int *notDir, int *loop)
 {
-	yaffs_Object *dir;
-	char *name;
+	struct yaffs_obj *dir;
+	struct yaffs_obj *obj;
+	YCHAR *name;
+
+	dir =
+	    yaffsfs_FindDirectory(relDir, path, &name, symDepth, notDir, loop);
+
+	if (dirOut)
+		*dirOut = dir;
+
+	if (dir && *name)
+		obj = yaffs_find_by_name(dir, name);
+	else
+		obj = dir;
+
+	if (getEquiv)
+		obj = yaffs_get_equivalent_obj(obj);
+
+	return obj;
+}
+
+/*************************************************************************
+ *	Start of yaffsfs visible functions.
+ *************************************************************************/
 
-	dir = yaffsfs_FindDirectory(relativeDirectory,path,&name,symDepth);
+int yaffs_dup(int handle)
+{
+	int newHandleNumber = -1;
+	struct yaffsfs_FileDes *existingFD = NULL;
+	struct yaffsfs_Handle *existingHandle = NULL;
+	struct yaffsfs_Handle *newHandle = NULL;
 
-	if(dir && *name)
-	{
-		return yaffs_FindObjectByName(dir,name);
+	yaffsfs_Lock();
+	existingHandle = yaffsfs_HandleToPointer(handle);
+	existingFD = yaffsfs_HandleToFileDes(handle);
+	if (existingFD)
+		newHandleNumber = yaffsfs_NewHandle(&newHandle);
+	if (newHandle) {
+		newHandle->fdId = existingHandle->fdId;
+		existingFD->handleCount++;
 	}
 
-	return dir;
+	yaffsfs_Unlock();
+
+	if (!existingFD)
+		yaffsfs_SetError(-EBADF);
+	else if (!newHandle)
+		yaffsfs_SetError(-ENOMEM);
+
+	return newHandleNumber;
+
 }
 
+static int yaffsfs_TooManyObjects(struct yaffs_dev *dev)
+{
+	int current_objects = dev->n_obj - dev->n_deleted_files;
 
+	if (dev->param.max_objects && current_objects > dev->param.max_objects)
+		return 1;
+	else
+		return 0;
+}
 
-int yaffs_open(const char *path, int oflag, int mode)
+int yaffs_open_sharing(const YCHAR *path, int oflag, int mode, int sharing)
 {
-	yaffs_Object *obj = NULL;
-	yaffs_Object *dir = NULL;
-	char *name;
+	struct yaffs_obj *obj = NULL;
+	struct yaffs_obj *dir = NULL;
+	YCHAR *name;
 	int handle = -1;
-	yaffsfs_Handle *h = NULL;
-	int alreadyOpen = 0;
-	int alreadyExclusive = 0;
+	struct yaffsfs_FileDes *fd = NULL;
 	int openDenied = 0;
 	int symDepth = 0;
 	int errorReported = 0;
+	int rwflags = oflag & (O_RDWR | O_RDONLY | O_WRONLY);
+	u8 shareRead = (sharing & YAFFS_SHARE_READ) ? 1 : 0;
+	u8 shareWrite = (sharing & YAFFS_SHARE_WRITE) ? 1 : 0;
+	u8 sharedReadAllowed;
+	u8 sharedWriteAllowed;
+	u8 alreadyReading;
+	u8 alreadyWriting;
+	u8 readRequested;
+	u8 writeRequested;
+	int notDir = 0;
+	int loop = 0;
 
-	int i;
+	if (!path) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
+
+	if (yaffsfs_CheckPath(path) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return -1;
+	}
+
+	/* O_EXCL only has meaning if O_CREAT is specified */
+	if (!(oflag & O_CREAT))
+		oflag &= ~(O_EXCL);
+
+	/* O_TRUNC has no meaning if (O_CREAT | O_EXCL) is specified */
+	if ((oflag & O_CREAT) & (oflag & O_EXCL))
+		oflag &= ~(O_TRUNC);
 
+	/* Todo: Are there any more flag combos to sanitise ? */
 
-	// todo sanity check oflag (eg. can't have O_TRUNC without WRONLY or RDWR
+	/* Figure out if reading or writing is requested */
 
+	readRequested = (rwflags == O_RDWR || rwflags == O_RDONLY) ? 1 : 0;
+	writeRequested = (rwflags == O_RDWR || rwflags == O_WRONLY) ? 1 : 0;
 
 	yaffsfs_Lock();
 
-	handle = yaffsfs_GetHandle();
+	handle = yaffsfs_NewHandleAndFileDes();
 
-	if(handle >= 0)
-	{
+	if (handle < 0) {
+		yaffsfs_SetError(-ENFILE);
+		errorReported = 1;
+	} else {
 
-		h = yaffsfs_GetHandlePointer(handle);
+		fd = yaffsfs_HandleToFileDes(handle);
 
+		/* try to find the exisiting object */
+		obj = yaffsfs_FindObject(NULL, path, 0, 1, NULL, NULL, NULL);
 
-		// try to find the exisiting object
-		obj = yaffsfs_FindObject(NULL,path,0);
+		obj = yaffsfs_FollowLink(obj, symDepth++, &loop);
 
-		if(obj && obj->variantType == YAFFS_OBJECT_TYPE_SYMLINK)
-		{
+		if (obj &&
+		    obj->variant_type != YAFFS_OBJECT_TYPE_FILE &&
+		    obj->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY)
+			obj = NULL;
 
-			obj = yaffsfs_FollowLink(obj,symDepth++);
-		}
+		if (obj) {
 
-		if(obj)
-		{
-			// Check if the object is already in use
-			alreadyOpen = alreadyExclusive = 0;
-
-			for(i = 0; i <= YAFFSFS_N_HANDLES; i++)
-			{
-
-				if(i != handle &&
-				   yaffsfs_handle[i].inUse &&
-				    obj == yaffsfs_handle[i].obj)
-				 {
-				 	alreadyOpen = 1;
-					if(yaffsfs_handle[i].exclusive)
-					{
-						alreadyExclusive = 1;
-					}
-				 }
-			}
+			/* The file already exists or it might be a directory */
 
-			if(((oflag & O_EXCL) && alreadyOpen) || alreadyExclusive)
-			{
+			/* A directory can't be opened as a file */
+			if (obj->variant_type == YAFFS_OBJECT_TYPE_DIRECTORY) {
 				openDenied = 1;
+				yaffsfs_SetError(-EISDIR);
+				errorReported = 1;
 			}
 
-			// Open should fail if O_CREAT and O_EXCL are specified
-			if((oflag & O_EXCL) && (oflag & O_CREAT))
-			{
+			/* Open should fail if O_CREAT and O_EXCL are specified
+			 * for a file that exists.
+			 */
+			if (!errorReported &&
+			    (oflag & O_EXCL) && (oflag & O_CREAT)) {
 				openDenied = 1;
 				yaffsfs_SetError(-EEXIST);
 				errorReported = 1;
 			}
 
-			// Check file permissions
-			if( (oflag & (O_RDWR | O_WRONLY)) == 0 &&     // ie O_RDONLY
-			   !(obj->yst_mode & S_IREAD))
-			{
+			/* Check file permissions */
+			if (readRequested && !(obj->yst_mode & S_IREAD))
 				openDenied = 1;
-			}
 
-			if( (oflag & O_RDWR) &&
-			   !(obj->yst_mode & S_IREAD))
-			{
+			if (writeRequested && !(obj->yst_mode & S_IWRITE))
 				openDenied = 1;
-			}
 
-			if( (oflag & (O_RDWR | O_WRONLY)) &&
-			   !(obj->yst_mode & S_IWRITE))
-			{
+			if (!errorReported && writeRequested &&
+			    obj->my_dev->read_only) {
 				openDenied = 1;
+				yaffsfs_SetError(-EROFS);
+				errorReported = 1;
 			}
 
-		}
+			if (openDenied && !errorReported) {
+				yaffsfs_SetError(-EACCES);
+				errorReported = 1;
+			}
+
+			/* Check sharing of an existing object. */
+			if (!openDenied) {
+				struct yaffsfs_FileDes *fdx;
+				int i;
+
+				sharedReadAllowed = 1;
+				sharedWriteAllowed = 1;
+				alreadyReading = 0;
+				alreadyWriting = 0;
+				for (i = 0; i < YAFFSFS_N_HANDLES; i++) {
+					fdx = &yaffsfs_fd[i];
+					if (fdx->handleCount > 0 &&
+					    fdx->inodeId >= 0 &&
+					    yaffsfs_inode[fdx->inodeId].iObj
+					    == obj) {
+						if (!fdx->shareRead)
+							sharedReadAllowed = 0;
+						if (!fdx->shareWrite)
+							sharedWriteAllowed = 0;
+						if (fdx->reading)
+							alreadyReading = 1;
+						if (fdx->writing)
+							alreadyWriting = 1;
+					}
+				}
 
-		else if((oflag & O_CREAT))
-		{
-			// Let's see if we can create this file
-			dir = yaffsfs_FindDirectory(NULL,path,&name,0);
-			if(dir)
-			{
-				obj = yaffs_MknodFile(dir,name,mode,0,0);
+				if ((!sharedReadAllowed && readRequested) ||
+				    (!shareRead && alreadyReading) ||
+				    (!sharedWriteAllowed && writeRequested) ||
+				    (!shareWrite && alreadyWriting)) {
+					openDenied = 1;
+					yaffsfs_SetError(-EBUSY);
+					errorReported = 1;
+				}
 			}
-			else
-			{
+
+		}
+
+		/* If we could not open an existing object, then let's see if
+		 * the directory exists. If not, error.
+		 */
+		if (!obj && !errorReported) {
+			dir = yaffsfs_FindDirectory(NULL, path, &name, 0,
+						    &notDir, &loop);
+			if (!dir && notDir) {
 				yaffsfs_SetError(-ENOTDIR);
+				errorReported = 1;
+			} else if (loop) {
+				yaffsfs_SetError(-ELOOP);
+				errorReported = 1;
+			} else if (!dir) {
+				yaffsfs_SetError(-ENOENT);
+				errorReported = 1;
 			}
 		}
 
-		if(obj && !openDenied)
-		{
-			h->obj = obj;
-			h->inUse = 1;
-	    	h->readOnly = (oflag & (O_WRONLY | O_RDWR)) ? 0 : 1;
-			h->append =  (oflag & O_APPEND) ? 1 : 0;
-			h->exclusive = (oflag & O_EXCL) ? 1 : 0;
-			h->position = 0;
-
-			obj->inUse++;
-			if((oflag & O_TRUNC) && !h->readOnly)
-			{
-				//todo truncate
-				yaffs_ResizeFile(obj,0);
+		if (!obj && dir && !errorReported && (oflag & O_CREAT)) {
+			/* Let's see if we can create this file */
+			if (dir->my_dev->read_only) {
+				yaffsfs_SetError(-EROFS);
+				errorReported = 1;
+			} else if (yaffsfs_TooManyObjects(dir->my_dev)) {
+				yaffsfs_SetError(-ENFILE);
+				errorReported = 1;
+			} else
+				obj = yaffs_create_file(dir, name, mode, 0, 0);
+
+			if (!obj && !errorReported) {
+				yaffsfs_SetError(-ENOSPC);
+				errorReported = 1;
 			}
+		}
 
+		if (!obj && dir && !errorReported && !(oflag & O_CREAT)) {
+			yaffsfs_SetError(-ENOENT);
+			errorReported = 1;
 		}
-		else
-		{
-			yaffsfs_PutHandle(handle);
-			if(!errorReported)
-			{
-				yaffsfs_SetError(-EACCESS);
-				errorReported = 1;
+
+		if (obj && !openDenied) {
+			int inodeId = yaffsfs_GetInodeIdForObject(obj);
+
+			if (inodeId < 0) {
+				/*
+				 * Todo: Fix any problem if inodes run out,
+				 * That can't happen if the number of inode
+				 * items >= number of handles.
+				 */
 			}
+
+			fd->inodeId = inodeId;
+			fd->reading = readRequested;
+			fd->writing = writeRequested;
+			fd->append = (oflag & O_APPEND) ? 1 : 0;
+			fd->position = 0;
+			fd->shareRead = shareRead;
+			fd->shareWrite = shareWrite;
+
+			/* Hook inode to object */
+			obj->my_inode = (void *)&yaffsfs_inode[inodeId];
+
+			if ((oflag & O_TRUNC) && fd->writing)
+				yaffs_resize_file(obj, 0);
+		} else {
+			yaffsfs_PutHandle(handle);
+			if (!errorReported)
+				yaffsfs_SetError(0);	/* Problem */
 			handle = -1;
 		}
-
 	}
 
 	yaffsfs_Unlock();
@@ -484,32 +992,68 @@ int yaffs_open(const char *path, int oflag, int mode)
 	return handle;
 }
 
-int yaffs_close(int fd)
+int yaffs_open(const YCHAR *path, int oflag, int mode)
 {
-	yaffsfs_Handle *h = NULL;
-	int retVal = 0;
+	return yaffs_open_sharing(path, oflag, mode,
+				  YAFFS_SHARE_READ | YAFFS_SHARE_WRITE);
+}
+
+int yaffs_Dofsync(int handle, int datasync)
+{
+	int retVal = -1;
+	struct yaffs_obj *obj;
 
 	yaffsfs_Lock();
 
-	h = yaffsfs_GetHandlePointer(fd);
+	obj = yaffsfs_HandleToObject(handle);
 
-	if(h && h->inUse)
-	{
-		// clean up
-		yaffs_FlushFile(h->obj,1);
-		h->obj->inUse--;
-		if(h->obj->inUse <= 0 && h->obj->unlinked)
-		{
-			yaffs_DeleteFile(h->obj);
-		}
-		yaffsfs_PutHandle(fd);
+	if (!obj)
+		yaffsfs_SetError(-EBADF);
+	else if (obj->my_dev->read_only)
+		yaffsfs_SetError(-EROFS);
+	else {
+		yaffs_flush_file(obj, 1, datasync);
 		retVal = 0;
 	}
-	else
-	{
-		// bad handle
+
+	yaffsfs_Unlock();
+
+	return retVal;
+}
+
+int yaffs_fsync(int handle)
+{
+	return yaffs_Dofsync(handle, 0);
+}
+
+int yaffs_flush(int handle)
+{
+	return yaffs_fsync(handle);
+}
+
+int yaffs_fdatasync(int handle)
+{
+	return yaffs_Dofsync(handle, 1);
+}
+
+int yaffs_close(int handle)
+{
+	struct yaffsfs_Handle *h = NULL;
+	struct yaffs_obj *obj = NULL;
+	int retVal = -1;
+
+	yaffsfs_Lock();
+
+	h = yaffsfs_HandleToPointer(handle);
+	obj = yaffsfs_HandleToObject(handle);
+
+	if (!h || !obj)
 		yaffsfs_SetError(-EBADF);
-		retVal = -1;
+	else {
+		/* clean up */
+		yaffs_flush_file(obj, 1, 0);
+		yaffsfs_PutHandle(handle);
+		retVal = 0;
 	}
 
 	yaffsfs_Unlock();
@@ -517,378 +1061,774 @@ int yaffs_close(int fd)
 	return retVal;
 }
 
-int yaffs_read(int fd, void *buf, unsigned int nbyte)
+int yaffsfs_do_read(int handle, void *vbuf, unsigned int nbyte,
+		    int isPread, loff_t offset)
 {
-	yaffsfs_Handle *h = NULL;
-	yaffs_Object *obj = NULL;
-	int pos = 0;
-	int nRead = -1;
-	int maxRead;
+	struct yaffsfs_FileDes *fd = NULL;
+	struct yaffs_obj *obj = NULL;
+	loff_t pos = 0;
+	loff_t startPos = 0;
+	loff_t endPos = 0;
+	int nRead = 0;
+	int nToRead = 0;
+	int totalRead = 0;
+	loff_t maxRead;
+	u8 *buf = (u8 *) vbuf;
+
+	if (!vbuf) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
 
 	yaffsfs_Lock();
-	h = yaffsfs_GetHandlePointer(fd);
-	obj = yaffsfs_GetHandleObject(fd);
+	fd = yaffsfs_HandleToFileDes(handle);
+	obj = yaffsfs_HandleToObject(handle);
 
-	if(!h || !obj)
-	{
-		// bad handle
+	if (!fd || !obj) {
+		/* bad handle */
 		yaffsfs_SetError(-EBADF);
-	}
-	else if( h && obj)
-	{
-		pos=  h->position;
-		if(yaffs_GetObjectFileLength(obj) > pos)
-		{
-			maxRead = yaffs_GetObjectFileLength(obj) - pos;
-		}
+		totalRead = -1;
+	} else if (!fd->reading) {
+		/* Not a reading handle */
+		yaffsfs_SetError(-EINVAL);
+		totalRead = -1;
+	} else if (nbyte > YAFFS_MAX_FILE_SIZE) {
+		yaffsfs_SetError(-EINVAL);
+		totalRead = -1;
+	} else {
+		if (isPread)
+			startPos = offset;
+		else
+			startPos = fd->position;
+
+		pos = startPos;
+
+		if (yaffs_get_obj_length(obj) > pos)
+			maxRead = yaffs_get_obj_length(obj) - pos;
 		else
-		{
 			maxRead = 0;
-		}
 
-		if(nbyte > maxRead)
-		{
+		if (nbyte > maxRead)
 			nbyte = maxRead;
+
+		yaffsfs_GetHandle(handle);
+
+		endPos = pos + nbyte;
+
+		if (pos < 0 || pos > YAFFS_MAX_FILE_SIZE ||
+		    nbyte > YAFFS_MAX_FILE_SIZE ||
+		    endPos < 0 || endPos > YAFFS_MAX_FILE_SIZE) {
+			totalRead = -1;
+			nbyte = 0;
 		}
 
+		while (nbyte > 0) {
+			nToRead = YAFFSFS_RW_SIZE -
+			    (pos & (YAFFSFS_RW_SIZE - 1));
+			if (nToRead > nbyte)
+				nToRead = nbyte;
+
+			/* Tricky bit...
+			 * Need to reverify object in case the device was
+			 * unmounted in another thread.
+			 */
+			obj = yaffsfs_HandleToObject(handle);
+			if (!obj)
+				nRead = 0;
+			else
+				nRead = yaffs_file_rd(obj, buf, pos, nToRead);
 
-		if(nbyte > 0)
-		{
-			nRead = yaffs_ReadDataFromFile(obj,buf,pos,nbyte);
-			if(nRead >= 0)
-			{
-				h->position = pos + nRead;
+			if (nRead > 0) {
+				totalRead += nRead;
+				pos += nRead;
+				buf += nRead;
 			}
+
+			if (nRead == nToRead)
+				nbyte -= nRead;
 			else
-			{
-				//todo error
+				nbyte = 0;	/* no more to read */
+
+			if (nbyte > 0) {
+				yaffsfs_Unlock();
+				yaffsfs_Lock();
 			}
+
 		}
-		else
-		{
-			nRead = 0;
+
+		yaffsfs_PutHandle(handle);
+
+		if (!isPread) {
+			if (totalRead >= 0)
+				fd->position = startPos + totalRead;
+			else
+				yaffsfs_SetError(-EINVAL);
 		}
 
 	}
 
 	yaffsfs_Unlock();
 
+	return (totalRead >= 0) ? totalRead : -1;
 
-	return (nRead >= 0) ? nRead : -1;
+}
 
+int yaffs_read(int handle, void *buf, unsigned int nbyte)
+{
+	return yaffsfs_do_read(handle, buf, nbyte, 0, 0);
 }
 
-int yaffs_write(int fd, const void *buf, unsigned int nbyte)
+int yaffs_pread(int handle, void *buf, unsigned int nbyte, loff_t offset)
 {
-	yaffsfs_Handle *h = NULL;
-	yaffs_Object *obj = NULL;
-	int pos = 0;
-	int nWritten = -1;
-	int writeThrough = 0;
+	return yaffsfs_do_read(handle, buf, nbyte, 1, offset);
+}
+
+int yaffsfs_do_write(int handle, const void *vbuf, unsigned int nbyte,
+		     int isPwrite, loff_t offset)
+{
+	struct yaffsfs_FileDes *fd = NULL;
+	struct yaffs_obj *obj = NULL;
+	loff_t pos = 0;
+	loff_t startPos = 0;
+	loff_t endPos;
+	int nWritten = 0;
+	int totalWritten = 0;
+	int write_trhrough = 0;
+	int nToWrite = 0;
+	const u8 *buf = (const u8 *)vbuf;
+
+	if (!vbuf) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
 
 	yaffsfs_Lock();
-	h = yaffsfs_GetHandlePointer(fd);
-	obj = yaffsfs_GetHandleObject(fd);
+	fd = yaffsfs_HandleToFileDes(handle);
+	obj = yaffsfs_HandleToObject(handle);
 
-	if(!h || !obj)
-	{
-		// bad handle
+	if (!fd || !obj) {
+		/* bad handle */
 		yaffsfs_SetError(-EBADF);
-	}
-	else if( h && obj && h->readOnly)
-	{
-		// todo error
-	}
-	else if( h && obj)
-	{
-		if(h->append)
-		{
-			pos =  yaffs_GetObjectFileLength(obj);
-		}
+		totalWritten = -1;
+	} else if (!fd->writing) {
+		yaffsfs_SetError(-EINVAL);
+		totalWritten = -1;
+	} else if (obj->my_dev->read_only) {
+		yaffsfs_SetError(-EROFS);
+		totalWritten = -1;
+	} else {
+		if (fd->append)
+			startPos = yaffs_get_obj_length(obj);
+		else if (isPwrite)
+			startPos = offset;
 		else
-		{
-			pos = h->position;
-		}
+			startPos = fd->position;
 
-		nWritten = yaffs_WriteDataToFile(obj,buf,pos,nbyte,writeThrough);
+		yaffsfs_GetHandle(handle);
+		pos = startPos;
+		endPos = pos + nbyte;
 
-		if(nWritten >= 0)
-		{
-			h->position = pos + nWritten;
+		if (pos < 0 || pos > YAFFS_MAX_FILE_SIZE ||
+		    nbyte > YAFFS_MAX_FILE_SIZE ||
+		    endPos < 0 || endPos > YAFFS_MAX_FILE_SIZE) {
+			totalWritten = -1;
+			nbyte = 0;
 		}
-		else
-		{
-			//todo error
+
+		while (nbyte > 0) {
+
+			nToWrite = YAFFSFS_RW_SIZE -
+			    (pos & (YAFFSFS_RW_SIZE - 1));
+			if (nToWrite > nbyte)
+				nToWrite = nbyte;
+
+			/* Tricky bit...
+			 * Need to reverify object in case the device was
+			 * remounted or unmounted in another thread.
+			 */
+			obj = yaffsfs_HandleToObject(handle);
+			if (!obj || obj->my_dev->read_only)
+				nWritten = 0;
+			else
+				nWritten =
+				    yaffs_wr_file(obj, buf, pos, nToWrite,
+						  write_trhrough);
+			if (nWritten > 0) {
+				totalWritten += nWritten;
+				pos += nWritten;
+				buf += nWritten;
+			}
+
+			if (nWritten == nToWrite)
+				nbyte -= nToWrite;
+			else
+				nbyte = 0;
+
+			if (nWritten < 1 && totalWritten < 1) {
+				yaffsfs_SetError(-ENOSPC);
+				totalWritten = -1;
+			}
+
+			if (nbyte > 0) {
+				yaffsfs_Unlock();
+				yaffsfs_Lock();
+			}
 		}
 
+		yaffsfs_PutHandle(handle);
+
+		if (!isPwrite) {
+			if (totalWritten > 0)
+				fd->position = startPos + totalWritten;
+			else
+				yaffsfs_SetError(-EINVAL);
+		}
 	}
 
 	yaffsfs_Unlock();
 
+	return (totalWritten >= 0) ? totalWritten : -1;
+}
+
+int yaffs_write(int fd, const void *buf, unsigned int nbyte)
+{
+	return yaffsfs_do_write(fd, buf, nbyte, 0, 0);
+}
+
+int yaffs_pwrite(int fd, const void *buf, unsigned int nbyte, loff_t offset)
+{
+	return yaffsfs_do_write(fd, buf, nbyte, 1, offset);
+}
+
+int yaffs_truncate(const YCHAR *path, loff_t new_size)
+{
+	struct yaffs_obj *obj = NULL;
+	struct yaffs_obj *dir = NULL;
+	int result = YAFFS_FAIL;
+	int notDir = 0;
+	int loop = 0;
+
+	if (!path) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
+
+	if (yaffsfs_CheckPath(path) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return -1;
+	}
+
+	yaffsfs_Lock();
 
-	return (nWritten >= 0) ? nWritten : -1;
+	obj = yaffsfs_FindObject(NULL, path, 0, 1, &dir, &notDir, &loop);
+	obj = yaffsfs_FollowLink(obj, 0, &loop);
 
+	if (!dir && notDir)
+		yaffsfs_SetError(-ENOTDIR);
+	else if (loop)
+		yaffsfs_SetError(-ELOOP);
+	else if (!dir || !obj)
+		yaffsfs_SetError(-ENOENT);
+	else if (obj->my_dev->read_only)
+		yaffsfs_SetError(-EROFS);
+	else if (obj->variant_type != YAFFS_OBJECT_TYPE_FILE)
+		yaffsfs_SetError(-EISDIR);
+	else if (obj->my_dev->read_only)
+		yaffsfs_SetError(-EROFS);
+	else if (new_size < 0 || new_size > YAFFS_MAX_FILE_SIZE)
+		yaffsfs_SetError(-EINVAL);
+	else
+		result = yaffs_resize_file(obj, new_size);
+
+	yaffsfs_Unlock();
+
+	return (result) ? 0 : -1;
 }
 
-int yaffs_truncate(int fd, off_t newSize)
+int yaffs_ftruncate(int handle, loff_t new_size)
 {
-	yaffsfs_Handle *h = NULL;
-	yaffs_Object *obj = NULL;
+	struct yaffsfs_FileDes *fd = NULL;
+	struct yaffs_obj *obj = NULL;
 	int result = 0;
 
 	yaffsfs_Lock();
-	h = yaffsfs_GetHandlePointer(fd);
-	obj = yaffsfs_GetHandleObject(fd);
+	fd = yaffsfs_HandleToFileDes(handle);
+	obj = yaffsfs_HandleToObject(handle);
 
-	if(!h || !obj)
-	{
-		// bad handle
+	if (!fd || !obj)
+		/* bad handle */
 		yaffsfs_SetError(-EBADF);
-	}
+	else if (!fd->writing)
+		yaffsfs_SetError(-EINVAL);
+	else if (obj->my_dev->read_only)
+		yaffsfs_SetError(-EROFS);
+	else if (new_size < 0 || new_size > YAFFS_MAX_FILE_SIZE)
+		yaffsfs_SetError(-EINVAL);
 	else
-	{
-		// resize the file
-		result = yaffs_ResizeFile(obj,newSize);
-	}
+		/* resize the file */
+		result = yaffs_resize_file(obj, new_size);
 	yaffsfs_Unlock();
 
-
 	return (result) ? 0 : -1;
 
 }
 
-off_t yaffs_lseek(int fd, off_t offset, int whence)
+loff_t yaffs_lseek(int handle, loff_t offset, int whence)
 {
-	yaffsfs_Handle *h = NULL;
-	yaffs_Object *obj = NULL;
-	int pos = -1;
-	int fSize = -1;
+	struct yaffsfs_FileDes *fd = NULL;
+	struct yaffs_obj *obj = NULL;
+	loff_t pos = -1;
+	loff_t fSize = -1;
 
 	yaffsfs_Lock();
-	h = yaffsfs_GetHandlePointer(fd);
-	obj = yaffsfs_GetHandleObject(fd);
+	fd = yaffsfs_HandleToFileDes(handle);
+	obj = yaffsfs_HandleToObject(handle);
 
-	if(!h || !obj)
-	{
-		// bad handle
+	if (!fd || !obj)
 		yaffsfs_SetError(-EBADF);
-	}
-	else if(whence == SEEK_SET)
-	{
-		if(offset >= 0)
-		{
-			pos = offset;
-		}
-	}
-	else if(whence == SEEK_CUR)
-	{
-		if( (h->position + offset) >= 0)
-		{
-			pos = (h->position + offset);
-		}
-	}
-	else if(whence == SEEK_END)
-	{
-		fSize = yaffs_GetObjectFileLength(obj);
-		if(fSize >= 0 && (fSize + offset) >= 0)
-		{
-			pos = fSize + offset;
+	else if (offset > YAFFS_MAX_FILE_SIZE)
+		yaffsfs_SetError(-EINVAL);
+	else {
+		if (whence == SEEK_SET) {
+			if (offset >= 0)
+				pos = offset;
+		} else if (whence == SEEK_CUR) {
+			if ((fd->position + offset) >= 0)
+				pos = (fd->position + offset);
+		} else if (whence == SEEK_END) {
+			fSize = yaffs_get_obj_length(obj);
+			if (fSize >= 0 && (fSize + offset) >= 0)
+				pos = fSize + offset;
 		}
-	}
 
-	if(pos >= 0)
-	{
-		h->position = pos;
-	}
-	else
-	{
-		// todo error
+		if (pos >= 0 && pos <= YAFFS_MAX_FILE_SIZE)
+			fd->position = pos;
+		else {
+			yaffsfs_SetError(-EINVAL);
+			pos = -1;
+		}
 	}
 
-
 	yaffsfs_Unlock();
 
 	return pos;
 }
 
-
-int yaffsfs_DoUnlink(const char *path,int isDirectory)
+int yaffsfs_DoUnlink(const YCHAR *path, int isDirectory)
 {
-	yaffs_Object *dir = NULL;
-	yaffs_Object *obj = NULL;
-	char *name;
+	struct yaffs_obj *dir = NULL;
+	struct yaffs_obj *obj = NULL;
+	YCHAR *name;
 	int result = YAFFS_FAIL;
+	int notDir = 0;
+	int loop = 0;
+
+	if (!path) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
+
+	if (yaffsfs_CheckPath(path) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return -1;
+	}
 
 	yaffsfs_Lock();
 
-	obj = yaffsfs_FindObject(NULL,path,0);
-	dir = yaffsfs_FindDirectory(NULL,path,&name,0);
-	if(!dir)
-	{
+	obj = yaffsfs_FindObject(NULL, path, 0, 0, NULL, NULL, NULL);
+	dir = yaffsfs_FindDirectory(NULL, path, &name, 0, &notDir, &loop);
+
+	if (!dir && notDir)
 		yaffsfs_SetError(-ENOTDIR);
-	}
-	else if(!obj)
-	{
+	else if (loop)
+		yaffsfs_SetError(-ELOOP);
+	else if (!dir)
 		yaffsfs_SetError(-ENOENT);
-	}
-	else if(!isDirectory && obj->variantType == YAFFS_OBJECT_TYPE_DIRECTORY)
-	{
+	else if (yaffs_strncmp(name, _Y("."), 2) == 0)
+		yaffsfs_SetError(-EINVAL);
+	else if (!obj)
+		yaffsfs_SetError(-ENOENT);
+	else if (obj->my_dev->read_only)
+		yaffsfs_SetError(-EROFS);
+	else if (!isDirectory &&
+		 obj->variant_type == YAFFS_OBJECT_TYPE_DIRECTORY)
 		yaffsfs_SetError(-EISDIR);
-	}
-	else if(isDirectory && obj->variantType != YAFFS_OBJECT_TYPE_DIRECTORY)
-	{
+	else if (isDirectory &&
+		 obj->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY)
 		yaffsfs_SetError(-ENOTDIR);
-	}
-	else
-	{
-		result = yaffs_Unlink(dir,name);
+	else if (isDirectory && obj == obj->my_dev->root_dir)
+		yaffsfs_SetError(-EBUSY);	/* Can't rmdir a root */
+	else {
+		result = yaffs_unlinker(dir, name);
 
-		if(result == YAFFS_FAIL && isDirectory)
-		{
+		if (result == YAFFS_FAIL && isDirectory)
 			yaffsfs_SetError(-ENOTEMPTY);
-		}
 	}
 
 	yaffsfs_Unlock();
 
-	// todo error
-
 	return (result == YAFFS_FAIL) ? -1 : 0;
 }
-int yaffs_rmdir(const char *path)
-{
-	return yaffsfs_DoUnlink(path,1);
-}
 
-int yaffs_unlink(const char *path)
+int yaffs_unlink(const YCHAR *path)
 {
-	return yaffsfs_DoUnlink(path,0);
+	return yaffsfs_DoUnlink(path, 0);
 }
 
-int yaffs_rename(const char *oldPath, const char *newPath)
+int yaffs_rename(const YCHAR *oldPath, const YCHAR *newPath)
 {
-	yaffs_Object *olddir = NULL;
-	yaffs_Object *newdir = NULL;
-	yaffs_Object *obj = NULL;
-	char *oldname;
-	char *newname;
-	int result= YAFFS_FAIL;
-	int renameAllowed = 1;
+	struct yaffs_obj *olddir = NULL;
+	struct yaffs_obj *newdir = NULL;
+	struct yaffs_obj *obj = NULL;
+	struct yaffs_obj *newobj = NULL;
+	YCHAR *oldname;
+	YCHAR *newname;
+	int result = YAFFS_FAIL;
+	int rename_allowed = 1;
+	int notOldDir = 0;
+	int notNewDir = 0;
+	int oldLoop = 0;
+	int newLoop = 0;
 
-	yaffsfs_Lock();
+	YCHAR *alt_newpath = NULL;
 
-	olddir = yaffsfs_FindDirectory(NULL,oldPath,&oldname,0);
-	newdir = yaffsfs_FindDirectory(NULL,newPath,&newname,0);
-	obj = yaffsfs_FindObject(NULL,oldPath,0);
+	if (!oldPath || !newPath) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
 
-	if(!olddir || !newdir || !obj)
-	{
-		// bad file
-		yaffsfs_SetError(-EBADF);
-		renameAllowed = 0;
+	if (yaffsfs_CheckPath(oldPath) < 0 || yaffsfs_CheckPath(newPath) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return -1;
 	}
-	else if(olddir->myDev != newdir->myDev)
-	{
-		// oops must be on same device
-		// todo error
-		yaffsfs_SetError(-EXDEV);
-		renameAllowed = 0;
+
+	if (yaffsfs_alt_dir_path(newPath, &alt_newpath) < 0) {
+		yaffsfs_SetError(-ENOMEM);
+		return -1;
 	}
-	else if(obj && obj->variantType == YAFFS_OBJECT_TYPE_DIRECTORY)
-	{
-		// It is a directory, check that it is not being renamed to
-		// being its own decendent.
-		// Do this by tracing from the new directory back to the root, checking for obj
+	if (alt_newpath)
+		newPath = alt_newpath;
 
-		yaffs_Object *xx = newdir;
+	yaffsfs_Lock();
 
-		while( renameAllowed && xx)
-		{
-			if(xx == obj)
-			{
-				renameAllowed = 0;
-			}
+	olddir = yaffsfs_FindDirectory(NULL, oldPath, &oldname, 0,
+				       &notOldDir, &oldLoop);
+	newdir = yaffsfs_FindDirectory(NULL, newPath, &newname, 0,
+				       &notNewDir, &newLoop);
+	obj = yaffsfs_FindObject(NULL, oldPath, 0, 0, NULL, NULL, NULL);
+	newobj = yaffsfs_FindObject(NULL, newPath, 0, 0, NULL, NULL, NULL);
+
+	/* If the object being renamed is a directory and the
+	 * path ended with a "/" then the olddir == obj.
+	 * We pass through NULL for the old name to tell the lower layers
+	 * to use olddir as the object.
+	 */
+
+	if (olddir == obj)
+		oldname = NULL;
+
+	if ((!olddir && notOldDir) || (!newdir && notNewDir)) {
+		yaffsfs_SetError(-ENOTDIR);
+		rename_allowed = 0;
+	} else if (oldLoop || newLoop) {
+		yaffsfs_SetError(-ELOOP);
+		rename_allowed = 0;
+	} else if (olddir && oldname &&
+			yaffs_strncmp(oldname, _Y("."), 2) == 0) {
+		yaffsfs_SetError(-EINVAL);
+		rename_allowed = 0;
+	} else if (!olddir || !newdir || !obj) {
+		yaffsfs_SetError(-ENOENT);
+		rename_allowed = 0;
+	} else if (obj->my_dev->read_only) {
+		yaffsfs_SetError(-EROFS);
+		rename_allowed = 0;
+	} else if (yaffs_is_non_empty_dir(newobj)) {
+		yaffsfs_SetError(-ENOTEMPTY);
+		rename_allowed = 0;
+	} else if (olddir->my_dev != newdir->my_dev) {
+		/* Rename must be on same device */
+		yaffsfs_SetError(-EXDEV);
+		rename_allowed = 0;
+	} else if (obj && obj->variant_type == YAFFS_OBJECT_TYPE_DIRECTORY) {
+		/*
+		 * It is a directory, check that it is not being renamed to
+		 * being its own decendent.
+		 * Do this by tracing from the new directory back to the root,
+		 * checking for obj
+		 */
+
+		struct yaffs_obj *xx = newdir;
+
+		while (rename_allowed && xx) {
+			if (xx == obj)
+				rename_allowed = 0;
 			xx = xx->parent;
 		}
-		if(!renameAllowed) yaffsfs_SetError(-EACCESS);
+		if (!rename_allowed)
+			yaffsfs_SetError(-EINVAL);
 	}
 
-	if(renameAllowed)
-	{
-		result = yaffs_RenameObject(olddir,oldname,newdir,newname);
-	}
+	if (rename_allowed)
+		result = yaffs_rename_obj(olddir, oldname, newdir, newname);
 
 	yaffsfs_Unlock();
 
+	kfree(alt_newpath);
+
 	return (result == YAFFS_FAIL) ? -1 : 0;
 }
 
-
-static int yaffsfs_DoStat(yaffs_Object *obj,struct yaffs_stat *buf)
+static int yaffsfs_DoStat(struct yaffs_obj *obj, struct yaffs_stat *buf)
 {
 	int retVal = -1;
 
-	if(obj)
-	{
-		obj = yaffs_GetEquivalentObject(obj);
-	}
+	obj = yaffs_get_equivalent_obj(obj);
 
-	if(obj && buf)
-	{
-    	buf->st_dev = (int)obj->myDev->genericDevice;
-    	buf->st_ino = obj->objectId;
-    	buf->st_mode = obj->yst_mode & ~S_IFMT; // clear out file type bits
+	if (obj && buf) {
+		buf->st_dev = (int)obj->my_dev->os_context;
+		buf->st_ino = obj->obj_id;
+		buf->st_mode = obj->yst_mode & ~S_IFMT;
 
-		if(obj->variantType == YAFFS_OBJECT_TYPE_DIRECTORY)
-		{
+		if (obj->variant_type == YAFFS_OBJECT_TYPE_DIRECTORY)
 			buf->st_mode |= S_IFDIR;
-		}
-		else if(obj->variantType == YAFFS_OBJECT_TYPE_SYMLINK)
-		{
+		else if (obj->variant_type == YAFFS_OBJECT_TYPE_SYMLINK)
 			buf->st_mode |= S_IFLNK;
-		}
-		else if(obj->variantType == YAFFS_OBJECT_TYPE_FILE)
-		{
+		else if (obj->variant_type == YAFFS_OBJECT_TYPE_FILE)
 			buf->st_mode |= S_IFREG;
-		}
 
-    	buf->st_nlink = yaffs_GetObjectLinkCount(obj);
-    	buf->st_uid = 0;
-    	buf->st_gid = 0;;
-    	buf->st_rdev = obj->yst_rdev;
-    	buf->st_size = yaffs_GetObjectFileLength(obj);
-		buf->st_blksize = obj->myDev->nDataBytesPerChunk;
-    	buf->st_blocks = (buf->st_size + buf->st_blksize -1)/buf->st_blksize;
-    	buf->yst_atime = obj->yst_atime;
-    	buf->yst_ctime = obj->yst_ctime;
-    	buf->yst_mtime = obj->yst_mtime;
+		buf->st_nlink = yaffs_get_obj_link_count(obj);
+		buf->st_uid = 0;
+		buf->st_gid = 0;
+		buf->st_rdev = obj->yst_rdev;
+		buf->st_size = yaffs_get_obj_length(obj);
+		buf->st_blksize = obj->my_dev->data_bytes_per_chunk;
+		buf->st_blocks = (buf->st_size + buf->st_blksize - 1) /
+		    buf->st_blksize;
+#if CONFIG_YAFFS_WINCE
+		buf->yst_wince_atime[0] = obj->win_atime[0];
+		buf->yst_wince_atime[1] = obj->win_atime[1];
+		buf->yst_wince_ctime[0] = obj->win_ctime[0];
+		buf->yst_wince_ctime[1] = obj->win_ctime[1];
+		buf->yst_wince_mtime[0] = obj->win_mtime[0];
+		buf->yst_wince_mtime[1] = obj->win_mtime[1];
+#else
+		buf->yst_atime = obj->yst_atime;
+		buf->yst_ctime = obj->yst_ctime;
+		buf->yst_mtime = obj->yst_mtime;
+#endif
 		retVal = 0;
 	}
 	return retVal;
 }
 
-static int yaffsfs_DoStatOrLStat(const char *path, struct yaffs_stat *buf,int doLStat)
+static int yaffsfs_DoStatOrLStat(const YCHAR *path,
+				 struct yaffs_stat *buf, int doLStat)
 {
-	yaffs_Object *obj;
+	struct yaffs_obj *obj = NULL;
+	struct yaffs_obj *dir = NULL;
+	int retVal = -1;
+	int notDir = 0;
+	int loop = 0;
+
+	if (!path || !buf) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
+
+	if (yaffsfs_CheckPath(path) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return -1;
+	}
+
+	yaffsfs_Lock();
+
+	obj = yaffsfs_FindObject(NULL, path, 0, 1, &dir, &notDir, &loop);
+
+	if (!doLStat && obj)
+		obj = yaffsfs_FollowLink(obj, 0, &loop);
+
+	if (!dir && notDir)
+		yaffsfs_SetError(-ENOTDIR);
+	else if (loop)
+		yaffsfs_SetError(-ELOOP);
+	else if (!dir || !obj)
+		yaffsfs_SetError(-ENOENT);
+	else
+		retVal = yaffsfs_DoStat(obj, buf);
+
+	yaffsfs_Unlock();
+
+	return retVal;
+
+}
+
+int yaffs_stat(const YCHAR *path, struct yaffs_stat *buf)
+{
+	return yaffsfs_DoStatOrLStat(path, buf, 0);
+}
+
+int yaffs_lstat(const YCHAR *path, struct yaffs_stat *buf)
+{
+	return yaffsfs_DoStatOrLStat(path, buf, 1);
+}
+
+int yaffs_fstat(int fd, struct yaffs_stat *buf)
+{
+	struct yaffs_obj *obj;
 
 	int retVal = -1;
 
+	if (!buf) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
+
 	yaffsfs_Lock();
-	obj = yaffsfs_FindObject(NULL,path,0);
+	obj = yaffsfs_HandleToObject(fd);
+
+	if (obj)
+		retVal = yaffsfs_DoStat(obj, buf);
+	else
+		/* bad handle */
+		yaffsfs_SetError(-EBADF);
+
+	yaffsfs_Unlock();
+
+	return retVal;
+}
+
+static int yaffsfs_DoUtime(struct yaffs_obj *obj,
+			   const struct yaffs_utimbuf *buf)
+{
+	int retVal = -1;
+	int result;
+
+	struct yaffs_utimbuf local;
+
+	obj = yaffs_get_equivalent_obj(obj);
+
+	if (obj && obj->my_dev->read_only) {
+		yaffsfs_SetError(-EROFS);
+		return -1;
+	}
+
+	if (!buf) {
+		local.actime = Y_CURRENT_TIME;
+		local.modtime = local.actime;
+		buf = &local;
+	}
 
-	if(!doLStat && obj)
-	{
-		obj = yaffsfs_FollowLink(obj,0);
+	if (obj) {
+		obj->yst_atime = buf->actime;
+		obj->yst_mtime = buf->modtime;
+		obj->dirty = 1;
+		result = yaffs_flush_file(obj, 0, 0);
+		retVal = result == YAFFS_OK ? 0 : -1;
+	}
+
+	return retVal;
+}
+
+int yaffs_utime(const YCHAR *path, const struct yaffs_utimbuf *buf)
+{
+	struct yaffs_obj *obj = NULL;
+	struct yaffs_obj *dir = NULL;
+	int retVal = -1;
+	int notDir = 0;
+	int loop = 0;
+
+	if (!path) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
 	}
 
-	if(obj)
-	{
-		retVal = yaffsfs_DoStat(obj,buf);
+	if (yaffsfs_CheckPath(path) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return -1;
 	}
+
+	yaffsfs_Lock();
+
+	obj = yaffsfs_FindObject(NULL, path, 0, 1, &dir, &notDir, &loop);
+
+	if (!dir && notDir)
+		yaffsfs_SetError(-ENOTDIR);
+	else if (loop)
+		yaffsfs_SetError(-ELOOP);
+	else if (!dir || !obj)
+		yaffsfs_SetError(-ENOENT);
 	else
-	{
-		// todo error not found
+		retVal = yaffsfs_DoUtime(obj, buf);
+
+	yaffsfs_Unlock();
+
+	return retVal;
+
+}
+
+int yaffs_futime(int fd, const struct yaffs_utimbuf *buf)
+{
+	struct yaffs_obj *obj;
+
+	int retVal = -1;
+
+	yaffsfs_Lock();
+	obj = yaffsfs_HandleToObject(fd);
+
+	if (obj)
+		retVal = yaffsfs_DoUtime(obj, buf);
+	else
+		/* bad handle */
+		yaffsfs_SetError(-EBADF);
+
+	yaffsfs_Unlock();
+
+	return retVal;
+}
+
+#ifndef CONFIG_YAFFS_WINCE
+/* xattrib functions */
+
+static int yaffs_do_setxattr(const YCHAR *path, const char *name,
+			     const void *data, int size, int flags, int follow)
+{
+	struct yaffs_obj *obj;
+	struct yaffs_obj *dir;
+	int notDir = 0;
+	int loop = 0;
+
+	int retVal = -1;
+
+	if (!path || !name || !data) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
+
+	if (yaffsfs_CheckPath(path) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return -1;
+	}
+
+	yaffsfs_Lock();
+
+	obj = yaffsfs_FindObject(NULL, path, 0, 1, &dir, &notDir, &loop);
+
+	if (follow)
+		obj = yaffsfs_FollowLink(obj, 0, &loop);
+
+	if (!dir && notDir)
+		yaffsfs_SetError(-ENOTDIR);
+	else if (loop)
+		yaffsfs_SetError(-ELOOP);
+	else if (!dir || !obj)
 		yaffsfs_SetError(-ENOENT);
+	else {
+		retVal = yaffs_set_xattrib(obj, name, data, size, flags);
+		if (retVal < 0) {
+			yaffsfs_SetError(retVal);
+			retVal = -1;
+		}
 	}
 
 	yaffsfs_Unlock();
@@ -897,33 +1837,41 @@ static int yaffsfs_DoStatOrLStat(const char *path, struct yaffs_stat *buf,int do
 
 }
 
-int yaffs_stat(const char *path, struct yaffs_stat *buf)
+int yaffs_setxattr(const YCHAR *path, const char *name,
+		   const void *data, int size, int flags)
 {
-	return yaffsfs_DoStatOrLStat(path,buf,0);
+	return yaffs_do_setxattr(path, name, data, size, flags, 1);
 }
 
-int yaffs_lstat(const char *path, struct yaffs_stat *buf)
+int yaffs_lsetxattr(const YCHAR *path, const char *name,
+		    const void *data, int size, int flags)
 {
-	return yaffsfs_DoStatOrLStat(path,buf,1);
+	return yaffs_do_setxattr(path, name, data, size, flags, 0);
 }
 
-int yaffs_fstat(int fd, struct yaffs_stat *buf)
+int yaffs_fsetxattr(int fd, const char *name,
+		    const void *data, int size, int flags)
 {
-	yaffs_Object *obj;
+	struct yaffs_obj *obj;
 
 	int retVal = -1;
 
+	if (!name || !data) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
+
 	yaffsfs_Lock();
-	obj = yaffsfs_GetHandleObject(fd);
+	obj = yaffsfs_HandleToObject(fd);
 
-	if(obj)
-	{
-		retVal = yaffsfs_DoStat(obj,buf);
-	}
-	else
-	{
-		// bad handle
+	if (!obj)
 		yaffsfs_SetError(-EBADF);
+	else {
+		retVal = yaffs_set_xattrib(obj, name, data, size, flags);
+		if (retVal < 0) {
+			yaffsfs_SetError(retVal);
+			retVal = -1;
+		}
 	}
 
 	yaffsfs_Unlock();
@@ -931,43 +1879,128 @@ int yaffs_fstat(int fd, struct yaffs_stat *buf)
 	return retVal;
 }
 
-static int yaffsfs_DoChMod(yaffs_Object *obj,mode_t mode)
+static int yaffs_do_getxattr(const YCHAR *path, const char *name,
+			     void *data, int size, int follow)
 {
-	int result = YAFFS_FAIL;
+	struct yaffs_obj *obj;
+	struct yaffs_obj *dir;
+	int retVal = -1;
+	int notDir = 0;
+	int loop = 0;
 
-	if(obj)
-	{
-		obj = yaffs_GetEquivalentObject(obj);
+	if (!path || !name || !data) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
 	}
 
-	if(obj)
-	{
-		obj->yst_mode = mode;
-		obj->dirty = 1;
-		result = yaffs_FlushFile(obj,0);
+	if (yaffsfs_CheckPath(path) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return -1;
 	}
 
-	return result == YAFFS_OK ? 0 : -1;
+	yaffsfs_Lock();
+
+	obj = yaffsfs_FindObject(NULL, path, 0, 1, &dir, &notDir, &loop);
+
+	if (follow)
+		obj = yaffsfs_FollowLink(obj, 0, &loop);
+
+	if (!dir && notDir)
+		yaffsfs_SetError(-ENOTDIR);
+	else if (loop)
+		yaffsfs_SetError(-ELOOP);
+	else if (!dir || !obj)
+		yaffsfs_SetError(-ENOENT);
+	else {
+		retVal = yaffs_get_xattrib(obj, name, data, size);
+		if (retVal < 0) {
+			yaffsfs_SetError(retVal);
+			retVal = -1;
+		}
+	}
+	yaffsfs_Unlock();
+
+	return retVal;
+
 }
 
+int yaffs_getxattr(const YCHAR *path, const char *name, void *data, int size)
+{
+	return yaffs_do_getxattr(path, name, data, size, 1);
+}
 
-int yaffs_chmod(const char *path, mode_t mode)
+int yaffs_lgetxattr(const YCHAR *path, const char *name, void *data, int size)
 {
-	yaffs_Object *obj;
+	return yaffs_do_getxattr(path, name, data, size, 0);
+}
+
+int yaffs_fgetxattr(int fd, const char *name, void *data, int size)
+{
+	struct yaffs_obj *obj;
 
 	int retVal = -1;
 
+	if (!name || !data) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
+
 	yaffsfs_Lock();
-	obj = yaffsfs_FindObject(NULL,path,0);
+	obj = yaffsfs_HandleToObject(fd);
 
-	if(obj)
-	{
-		retVal = yaffsfs_DoChMod(obj,mode);
+	if (obj) {
+		retVal = yaffs_get_xattrib(obj, name, data, size);
+		if (retVal < 0) {
+			yaffsfs_SetError(retVal);
+			retVal = -1;
+		}
+	} else
+		/* bad handle */
+		yaffsfs_SetError(-EBADF);
+
+	yaffsfs_Unlock();
+
+	return retVal;
+}
+
+static int yaffs_do_listxattr(const YCHAR *path, char *data,
+			      int size, int follow)
+{
+	struct yaffs_obj *obj = NULL;
+	struct yaffs_obj *dir = NULL;
+	int retVal = -1;
+	int notDir = 0;
+	int loop = 0;
+
+	if (!path || !data) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
 	}
-	else
-	{
-		// todo error not found
+
+	if (yaffsfs_CheckPath(path) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return -1;
+	}
+
+	yaffsfs_Lock();
+
+	obj = yaffsfs_FindObject(NULL, path, 0, 1, &dir, &notDir, &loop);
+
+	if (follow)
+		obj = yaffsfs_FollowLink(obj, 0, &loop);
+
+	if (!dir && notDir)
+		yaffsfs_SetError(-ENOTDIR);
+	else if (loop)
+		yaffsfs_SetError(-ELOOP);
+	else if (!dir || !obj)
 		yaffsfs_SetError(-ENOENT);
+	else {
+		retVal = yaffs_list_xattrib(obj, data, size);
+		if (retVal < 0) {
+			yaffsfs_SetError(retVal);
+			retVal = -1;
+		}
 	}
 
 	yaffsfs_Unlock();
@@ -976,317 +2009,906 @@ int yaffs_chmod(const char *path, mode_t mode)
 
 }
 
+int yaffs_listxattr(const YCHAR *path, char *data, int size)
+{
+	return yaffs_do_listxattr(path, data, size, 1);
+}
 
-int yaffs_fchmod(int fd, mode_t mode)
+int yaffs_llistxattr(const YCHAR *path, char *data, int size)
 {
-	yaffs_Object *obj;
+	return yaffs_do_listxattr(path, data, size, 0);
+}
+
+int yaffs_flistxattr(int fd, char *data, int size)
+{
+	struct yaffs_obj *obj;
 
 	int retVal = -1;
 
+	if (!data) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
+
 	yaffsfs_Lock();
-	obj = yaffsfs_GetHandleObject(fd);
+	obj = yaffsfs_HandleToObject(fd);
 
-	if(obj)
-	{
-		retVal = yaffsfs_DoChMod(obj,mode);
-	}
-	else
-	{
-		// bad handle
+	if (obj) {
+		retVal = yaffs_list_xattrib(obj, data, size);
+		if (retVal < 0) {
+			yaffsfs_SetError(retVal);
+			retVal = -1;
+		}
+	} else
+		/* bad handle */
 		yaffsfs_SetError(-EBADF);
+
+	yaffsfs_Unlock();
+
+	return retVal;
+}
+
+static int yaffs_do_removexattr(const YCHAR *path, const char *name,
+				int follow)
+{
+	struct yaffs_obj *obj = NULL;
+	struct yaffs_obj *dir = NULL;
+	int notDir = 0;
+	int loop = 0;
+	int retVal = -1;
+
+	if (!path || !name) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
+
+	if (yaffsfs_CheckPath(path) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return -1;
+	}
+
+	yaffsfs_Lock();
+
+	obj = yaffsfs_FindObject(NULL, path, 0, 1, &dir, &notDir, &loop);
+
+	if (follow)
+		obj = yaffsfs_FollowLink(obj, 0, &loop);
+
+	if (!dir && notDir)
+		yaffsfs_SetError(-ENOTDIR);
+	else if (loop)
+		yaffsfs_SetError(-ELOOP);
+	else if (!dir || !obj)
+		yaffsfs_SetError(-ENOENT);
+	else {
+		retVal = yaffs_remove_xattrib(obj, name);
+		if (retVal < 0) {
+			yaffsfs_SetError(retVal);
+			retVal = -1;
+		}
+	}
+
+	yaffsfs_Unlock();
+
+	return retVal;
+
+}
+
+int yaffs_removexattr(const YCHAR *path, const char *name)
+{
+	return yaffs_do_removexattr(path, name, 1);
+}
+
+int yaffs_lremovexattr(const YCHAR *path, const char *name)
+{
+	return yaffs_do_removexattr(path, name, 0);
+}
+
+int yaffs_fremovexattr(int fd, const char *name)
+{
+	struct yaffs_obj *obj;
+
+	int retVal = -1;
+
+	if (!name) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
 	}
 
+	yaffsfs_Lock();
+	obj = yaffsfs_HandleToObject(fd);
+
+	if (obj) {
+		retVal = yaffs_remove_xattrib(obj, name);
+		if (retVal < 0) {
+			yaffsfs_SetError(retVal);
+			retVal = -1;
+		}
+	} else
+		/* bad handle */
+		yaffsfs_SetError(-EBADF);
+
 	yaffsfs_Unlock();
 
 	return retVal;
 }
+#endif
+
+#ifdef CONFIG_YAFFS_WINCE
+int yaffs_get_wince_times(int fd, unsigned *wctime,
+			  unsigned *watime, unsigned *wmtime)
+{
+	struct yaffs_obj *obj;
+
+	int retVal = -1;
+
+	yaffsfs_Lock();
+	obj = yaffsfs_HandleToObject(fd);
+
+	if (obj) {
 
+		if (wctime) {
+			wctime[0] = obj->win_ctime[0];
+			wctime[1] = obj->win_ctime[1];
+		}
+		if (watime) {
+			watime[0] = obj->win_atime[0];
+			watime[1] = obj->win_atime[1];
+		}
+		if (wmtime) {
+			wmtime[0] = obj->win_mtime[0];
+			wmtime[1] = obj->win_mtime[1];
+		}
+
+		retVal = 0;
+	} else
+		/*  bad handle */
+		yaffsfs_SetError(-EBADF);
+
+	yaffsfs_Unlock();
 
-int yaffs_mkdir(const char *path, mode_t mode)
+	return retVal;
+}
+
+int yaffs_set_wince_times(int fd,
+			  const unsigned *wctime,
+			  const unsigned *watime, const unsigned *wmtime)
 {
-	yaffs_Object *parent = NULL;
-	yaffs_Object *dir = NULL;
-	char *name;
-	int retVal= -1;
+	struct yaffs_obj *obj;
+	int result;
+	int retVal = -1;
 
 	yaffsfs_Lock();
-	parent = yaffsfs_FindDirectory(NULL,path,&name,0);
-	if(parent)
-		dir = yaffs_MknodDirectory(parent,name,mode,0,0);
-	if(dir)
-	{
+	obj = yaffsfs_HandleToObject(fd);
+
+	if (obj) {
+
+		if (wctime) {
+			obj->win_ctime[0] = wctime[0];
+			obj->win_ctime[1] = wctime[1];
+		}
+		if (watime) {
+			obj->win_atime[0] = watime[0];
+			obj->win_atime[1] = watime[1];
+		}
+		if (wmtime) {
+			obj->win_mtime[0] = wmtime[0];
+			obj->win_mtime[1] = wmtime[1];
+		}
+
+		obj->dirty = 1;
+		result = yaffs_flush_file(obj, 0, 0);
 		retVal = 0;
+	} else
+		/* bad handle */
+		yaffsfs_SetError(-EBADF);
+
+	yaffsfs_Unlock();
+
+	return retVal;
+}
+
+#endif
+
+static int yaffsfs_DoChMod(struct yaffs_obj *obj, mode_t mode)
+{
+	int result = -1;
+
+	if (obj)
+		obj = yaffs_get_equivalent_obj(obj);
+
+	if (obj) {
+		obj->yst_mode = mode;
+		obj->dirty = 1;
+		result = yaffs_flush_file(obj, 0, 0);
+	}
+
+	return result == YAFFS_OK ? 0 : -1;
+}
+
+int yaffs_access(const YCHAR *path, int amode)
+{
+	struct yaffs_obj *obj = NULL;
+	struct yaffs_obj *dir = NULL;
+	int notDir = 0;
+	int loop = 0;
+	int retval = -1;
+
+	if (!path) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
 	}
+
+	if (yaffsfs_CheckPath(path) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return -1;
+	}
+
+	if (amode & ~(R_OK | W_OK | X_OK)) {
+		yaffsfs_SetError(-EINVAL);
+		return -1;
+	}
+
+	yaffsfs_Lock();
+
+	obj = yaffsfs_FindObject(NULL, path, 0, 1, &dir, &notDir, &loop);
+	obj = yaffsfs_FollowLink(obj, 0, &loop);
+
+	if (!dir && notDir)
+		yaffsfs_SetError(-ENOTDIR);
+	else if (loop)
+		yaffsfs_SetError(-ELOOP);
+	else if (!dir || !obj)
+		yaffsfs_SetError(-ENOENT);
+	else if ((amode & W_OK) && obj->my_dev->read_only)
+		yaffsfs_SetError(-EROFS);
+	else {
+		int access_ok = 1;
+
+		if ((amode & R_OK) && !(obj->yst_mode & S_IREAD))
+			access_ok = 0;
+		if ((amode & W_OK) && !(obj->yst_mode & S_IWRITE))
+			access_ok = 0;
+		if ((amode & X_OK) && !(obj->yst_mode & S_IEXEC))
+			access_ok = 0;
+
+		if (!access_ok)
+			yaffsfs_SetError(-EACCES);
+		else
+			retval = 0;
+	}
+
+	yaffsfs_Unlock();
+
+	return retval;
+
+}
+
+int yaffs_chmod(const YCHAR *path, mode_t mode)
+{
+	struct yaffs_obj *obj = NULL;
+	struct yaffs_obj *dir = NULL;
+	int retVal = -1;
+	int notDir = 0;
+	int loop = 0;
+
+	if (!path) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
+
+	if (yaffsfs_CheckPath(path) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return -1;
+	}
+
+	if (mode & ~(0777)) {
+		yaffsfs_SetError(-EINVAL);
+		return -1;
+	}
+
+	yaffsfs_Lock();
+
+	obj = yaffsfs_FindObject(NULL, path, 0, 1, &dir, &notDir, &loop);
+	obj = yaffsfs_FollowLink(obj, 0, &loop);
+
+	if (!dir && notDir)
+		yaffsfs_SetError(-ENOTDIR);
+	else if (loop)
+		yaffsfs_SetError(-ELOOP);
+	else if (!dir || !obj)
+		yaffsfs_SetError(-ENOENT);
+	else if (obj->my_dev->read_only)
+		yaffsfs_SetError(-EROFS);
 	else
-	{
-		yaffsfs_SetError(-ENOSPC); // just assume no space for now
-		retVal = -1;
+		retVal = yaffsfs_DoChMod(obj, mode);
+
+	yaffsfs_Unlock();
+
+	return retVal;
+
+}
+
+int yaffs_fchmod(int fd, mode_t mode)
+{
+	struct yaffs_obj *obj;
+	int retVal = -1;
+
+	if (mode & ~(0777)) {
+		yaffsfs_SetError(-EINVAL);
+		return -1;
 	}
 
+	yaffsfs_Lock();
+	obj = yaffsfs_HandleToObject(fd);
+
+	if (!obj)
+		yaffsfs_SetError(-EBADF);
+	else if (obj->my_dev->read_only)
+		yaffsfs_SetError(-EROFS);
+	else
+		retVal = yaffsfs_DoChMod(obj, mode);
+
 	yaffsfs_Unlock();
 
 	return retVal;
 }
 
-int yaffs_mount(const char *path)
+int yaffs_mkdir(const YCHAR *path, mode_t mode)
 {
-	int retVal=-1;
-	int result=YAFFS_FAIL;
-	yaffs_Device *dev=NULL;
-	char *dummy;
+	struct yaffs_obj *parent = NULL;
+	struct yaffs_obj *dir = NULL;
+	YCHAR *name;
+	YCHAR *alt_path = NULL;
+	int retVal = -1;
+	int notDir = 0;
+	int loop = 0;
 
-	T(YAFFS_TRACE_ALWAYS,("yaffs: Mounting %s\n",path));
+	if (!path) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
+
+	if (yaffsfs_CheckPath(path) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return -1;
+	}
+
+	if (yaffsfs_alt_dir_path(path, &alt_path) < 0) {
+		yaffsfs_SetError(-ENOMEM);
+		return -1;
+	}
+	if (alt_path)
+		path = alt_path;
 
 	yaffsfs_Lock();
-	dev = yaffsfs_FindDevice(path,&dummy);
-	if(dev)
-	{
-		if(!dev->isMounted)
-		{
-			result = yaffs_GutsInitialise(dev);
-			if(result == YAFFS_FAIL)
-			{
-				// todo error - mount failed
-				yaffsfs_SetError(-ENOMEM);
+	parent = yaffsfs_FindDirectory(NULL, path, &name, 0, &notDir, &loop);
+	if (!parent && notDir)
+		yaffsfs_SetError(-ENOTDIR);
+	else if (loop)
+		yaffsfs_SetError(-ELOOP);
+	else if (!parent)
+		yaffsfs_SetError(-ENOENT);
+	else if (yaffsfs_TooManyObjects(parent->my_dev))
+		yaffsfs_SetError(-ENFILE);
+	else if (yaffs_strnlen(name, 5) == 0) {
+		/* Trying to make the root itself */
+		yaffsfs_SetError(-EEXIST);
+	} else if (parent->my_dev->read_only)
+		yaffsfs_SetError(-EROFS);
+	else {
+		dir = yaffs_create_dir(parent, name, mode, 0, 0);
+		if (dir)
+			retVal = 0;
+		else if (yaffs_find_by_name(parent, name))
+			yaffsfs_SetError(-EEXIST);	/* name exists */
+		else
+			yaffsfs_SetError(-ENOSPC);	/* assume no space */
+	}
+
+	yaffsfs_Unlock();
+
+	kfree(alt_path);
+
+	return retVal;
+}
+
+int yaffs_rmdir(const YCHAR *path)
+{
+	int result;
+	YCHAR *alt_path;
+
+	if (!path) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
+
+	if (yaffsfs_CheckPath(path) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return -1;
+	}
+
+	if (yaffsfs_alt_dir_path(path, &alt_path) < 0) {
+		yaffsfs_SetError(-ENOMEM);
+		return -1;
+	}
+	if (alt_path)
+		path = alt_path;
+	result = yaffsfs_DoUnlink(path, 1);
+
+	kfree(alt_path);
+
+	return result;
+}
+
+void *yaffs_getdev(const YCHAR *path)
+{
+	struct yaffs_dev *dev = NULL;
+	YCHAR *dummy;
+	dev = yaffsfs_FindDevice(path, &dummy);
+	return (void *)dev;
+}
+
+int yaffs_mount_common(const YCHAR *path, int read_only, int skip_checkpt)
+{
+	int retVal = -1;
+	int result = YAFFS_FAIL;
+	struct yaffs_dev *dev = NULL;
+
+	if (!path) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
+
+	yaffs_trace(YAFFS_TRACE_MOUNT, "yaffs: Mounting %s", path);
+
+	if (yaffsfs_CheckPath(path) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return -1;
+	}
+
+	yaffsfs_Lock();
+
+	yaffsfs_InitHandles();
+
+	dev = yaffsfs_FindMountPoint(path);
+	if (dev) {
+		if (!dev->is_mounted) {
+			dev->read_only = read_only ? 1 : 0;
+			if (skip_checkpt) {
+				u8 skip = dev->param.skip_checkpt_rd;
+				dev->param.skip_checkpt_rd = 1;
+				result = yaffs_guts_initialise(dev);
+				dev->param.skip_checkpt_rd = skip;
+			} else {
+				result = yaffs_guts_initialise(dev);
 			}
+
+			if (result == YAFFS_FAIL)
+				yaffsfs_SetError(-ENOMEM);
 			retVal = result ? 0 : -1;
 
-		}
-		else
-		{
-			//todo error - already mounted.
+		} else
 			yaffsfs_SetError(-EBUSY);
-		}
-	}
-	else
-	{
-		// todo error - no device
+	} else
 		yaffsfs_SetError(-ENODEV);
-	}
+
 	yaffsfs_Unlock();
 	return retVal;
 
 }
 
-int yaffs_unmount(const char *path)
+int yaffs_mount2(const YCHAR *path, int readonly)
 {
-	int retVal=-1;
-	yaffs_Device *dev=NULL;
-	char *dummy;
+	return yaffs_mount_common(path, readonly, 0);
+}
+
+int yaffs_mount(const YCHAR *path)
+{
+	return yaffs_mount_common(path, 0, 0);
+}
+
+int yaffs_sync(const YCHAR *path)
+{
+	int retVal = -1;
+	struct yaffs_dev *dev = NULL;
+	YCHAR *dummy;
+
+	if (!path) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
+
+	if (yaffsfs_CheckPath(path) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return -1;
+	}
 
 	yaffsfs_Lock();
-	dev = yaffsfs_FindDevice(path,&dummy);
-	if(dev)
-	{
-		if(dev->isMounted)
-		{
-			int i;
-			int inUse;
+	dev = yaffsfs_FindDevice(path, &dummy);
+	if (dev) {
+		if (!dev->is_mounted)
+			yaffsfs_SetError(-EINVAL);
+		else if (dev->read_only)
+			yaffsfs_SetError(-EROFS);
+		else {
 
-			yaffs_FlushEntireDeviceCache(dev);
-			yaffs_CheckpointSave(dev);
+			yaffs_flush_whole_cache(dev);
+			yaffs_checkpoint_save(dev);
+			retVal = 0;
 
-			for(i = inUse = 0; i < YAFFSFS_N_HANDLES && !inUse; i++)
-			{
-				if(yaffsfs_handle[i].inUse && yaffsfs_handle[i].obj->myDev == dev)
-				{
-					inUse = 1; // the device is in use, can't unmount
-				}
-			}
+		}
+	} else
+		yaffsfs_SetError(-ENODEV);
 
-			if(!inUse)
-			{
-				yaffs_Deinitialise(dev);
+	yaffsfs_Unlock();
+	return retVal;
+}
+
+static int yaffsfs_IsDevBusy(struct yaffs_dev *dev)
+{
+	int i;
+	struct yaffs_obj *obj;
 
+	for (i = 0; i < YAFFSFS_N_HANDLES; i++) {
+		obj = yaffsfs_HandleToObject(i);
+		if (obj && obj->my_dev == dev)
+			return 1;
+	}
+	return 0;
+}
+
+int yaffs_remount(const YCHAR *path, int force, int read_only)
+{
+	int retVal = -1;
+	struct yaffs_dev *dev = NULL;
+
+	if (!path) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
+
+	if (yaffsfs_CheckPath(path) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return -1;
+	}
+
+	yaffsfs_Lock();
+	dev = yaffsfs_FindMountPoint(path);
+	if (dev) {
+		if (dev->is_mounted) {
+			yaffs_flush_whole_cache(dev);
+
+			if (force || !yaffsfs_IsDevBusy(dev)) {
+				if (read_only)
+					yaffs_checkpoint_save(dev);
+				dev->read_only = read_only ? 1 : 0;
 				retVal = 0;
-			}
-			else
-			{
-				// todo error can't unmount as files are open
+			} else
 				yaffsfs_SetError(-EBUSY);
-			}
 
-		}
-		else
-		{
-			//todo error - not mounted.
+		} else
 			yaffsfs_SetError(-EINVAL);
 
-		}
-	}
-	else
-	{
-		// todo error - no device
+	} else
 		yaffsfs_SetError(-ENODEV);
-	}
+
 	yaffsfs_Unlock();
 	return retVal;
 
 }
 
-loff_t yaffs_freespace(const char *path)
+int yaffs_unmount2(const YCHAR *path, int force)
 {
-	loff_t retVal=-1;
-	yaffs_Device *dev=NULL;
-	char *dummy;
+	int retVal = -1;
+	struct yaffs_dev *dev = NULL;
+
+	if (!path) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
+
+	if (yaffsfs_CheckPath(path) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return -1;
+	}
 
 	yaffsfs_Lock();
-	dev = yaffsfs_FindDevice(path,&dummy);
-	if(dev  && dev->isMounted)
-	{
-		retVal = yaffs_GetNumberOfFreeChunks(dev);
-		retVal *= dev->nDataBytesPerChunk;
+	dev = yaffsfs_FindMountPoint(path);
+	if (dev) {
+		if (dev->is_mounted) {
+			int inUse;
+			yaffs_flush_whole_cache(dev);
+			yaffs_checkpoint_save(dev);
+			inUse = yaffsfs_IsDevBusy(dev);
+			if (!inUse || force) {
+				if (inUse)
+					yaffsfs_BreakDeviceHandles(dev);
+				yaffs_deinitialise(dev);
+
+				retVal = 0;
+			} else
+				yaffsfs_SetError(-EBUSY);
+
+		} else
+			yaffsfs_SetError(-EINVAL);
+
+	} else
+		yaffsfs_SetError(-ENODEV);
+
+	yaffsfs_Unlock();
+	return retVal;
+
+}
+
+int yaffs_unmount(const YCHAR *path)
+{
+	return yaffs_unmount2(path, 0);
+}
+
+loff_t yaffs_freespace(const YCHAR *path)
+{
+	loff_t retVal = -1;
+	struct yaffs_dev *dev = NULL;
+	YCHAR *dummy;
 
+	if (!path) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
 	}
-	else
-	{
-		yaffsfs_SetError(-EINVAL);
+
+	if (yaffsfs_CheckPath(path) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return -1;
 	}
 
+	yaffsfs_Lock();
+	dev = yaffsfs_FindDevice(path, &dummy);
+	if (dev && dev->is_mounted) {
+		retVal = yaffs_get_n_free_chunks(dev);
+		retVal *= dev->data_bytes_per_chunk;
+
+	} else
+		yaffsfs_SetError(-EINVAL);
+
 	yaffsfs_Unlock();
 	return retVal;
 }
 
+loff_t yaffs_totalspace(const YCHAR *path)
+{
+	loff_t retVal = -1;
+	struct yaffs_dev *dev = NULL;
+	YCHAR *dummy;
 
+	if (!path) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
 
-void yaffs_initialise(yaffsfs_DeviceConfiguration *cfgList)
-{
+	if (yaffsfs_CheckPath(path) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return -1;
+	}
 
-	yaffsfs_DeviceConfiguration *cfg;
+	yaffsfs_Lock();
+	dev = yaffsfs_FindDevice(path, &dummy);
+	if (dev && dev->is_mounted) {
+		retVal = (dev->param.end_block - dev->param.start_block + 1) -
+		    dev->param.n_reserved_blocks;
+		retVal *= dev->param.chunks_per_block;
+		retVal *= dev->data_bytes_per_chunk;
+
+	} else
+		yaffsfs_SetError(-EINVAL);
+
+	yaffsfs_Unlock();
+	return retVal;
+}
 
-	yaffsfs_configurationList = cfgList;
+int yaffs_inodecount(const YCHAR *path)
+{
+	loff_t retVal = -1;
+	struct yaffs_dev *dev = NULL;
+	YCHAR *dummy;
 
-	yaffsfs_InitHandles();
+	if (!path) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
 
-	cfg = yaffsfs_configurationList;
+	if (yaffsfs_CheckPath(path) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return -1;
+	}
 
-	while(cfg && cfg->prefix && cfg->dev)
-	{
-		cfg->dev->isMounted = 0;
-		cfg->dev->removeObjectCallback = yaffsfs_RemoveObjectCallback;
-		cfg++;
+	yaffsfs_Lock();
+	dev = yaffsfs_FindDevice(path, &dummy);
+	if (dev && dev->is_mounted) {
+		int n_obj = dev->n_obj;
+		if (n_obj > dev->n_hardlinks)
+			retVal = n_obj - dev->n_hardlinks;
 	}
+
+	if (retVal < 0)
+		yaffsfs_SetError(-EINVAL);
+
+	yaffsfs_Unlock();
+	return retVal;
 }
 
+void yaffs_add_device(struct yaffs_dev *dev)
+{
+	struct list_head *cfg;
+	/* First check that the device is not in the list. */
+
+	list_for_each(cfg, &yaffsfs_deviceList) {
+		if (dev == list_entry(cfg, struct yaffs_dev, dev_list))
+			return;
+	}
+
+	dev->is_mounted = 0;
+	dev->param.remove_obj_fn = yaffsfs_RemoveObjectCallback;
 
-//
-// Directory search stuff.
+	if (!dev->dev_list.next)
+		INIT_LIST_HEAD(&dev->dev_list);
 
-//
-// Directory search context
-//
-// NB this is an opaque structure.
+	list_add(&dev->dev_list, &yaffsfs_deviceList);
+}
+
+void yaffs_remove_device(struct yaffs_dev *dev)
+{
+	list_del_init(&dev->dev_list);
+}
 
+/* Functions to iterate through devices. NB Use with extreme care! */
 
-typedef struct
+static struct list_head *dev_iterator;
+void yaffs_dev_rewind(void)
 {
-	__u32 magic;
-	yaffs_dirent de;		/* directory entry being used by this dsc */
-	char name[NAME_MAX+1];		/* name of directory being searched */
-	yaffs_Object *dirObj;		/* ptr to directory being searched */
-	yaffs_Object *nextReturn;	/* obj to be returned by next readddir */
-	int offset;
-	struct list_head others;
-} yaffsfs_DirectorySearchContext;
+	dev_iterator = yaffsfs_deviceList.next;
+}
+
+struct yaffs_dev *yaffs_next_dev(void)
+{
+	struct yaffs_dev *retval;
 
+	if (!dev_iterator)
+		return NULL;
+	if (dev_iterator == &yaffsfs_deviceList)
+		return NULL;
+
+	retval = list_entry(dev_iterator, struct yaffs_dev, dev_list);
+	dev_iterator = dev_iterator->next;
+	return retval;
+}
 
+/* Directory search stuff. */
 
 static struct list_head search_contexts;
 
-
-static void yaffsfs_SetDirRewound(yaffsfs_DirectorySearchContext *dsc)
+static void yaffsfs_SetDirRewound(struct yaffsfs_DirSearchContxt *dsc)
 {
-	if(dsc &&
-	   dsc->dirObj &&
-	   dsc->dirObj->variantType == YAFFS_OBJECT_TYPE_DIRECTORY){
+	if (dsc &&
+	    dsc->dirObj &&
+	    dsc->dirObj->variant_type == YAFFS_OBJECT_TYPE_DIRECTORY) {
 
-	   dsc->offset = 0;
+		dsc->offset = 0;
 
-	   if( list_empty(&dsc->dirObj->variant.directoryVariant.children)){
-	   	dsc->nextReturn = NULL;
-	   } else {
-	      	dsc->nextReturn = list_entry(dsc->dirObj->variant.directoryVariant.children.next,
-						yaffs_Object,siblings);
-	   }
+		if (list_empty(&dsc->dirObj->variant.dir_variant.children))
+			dsc->nextReturn = NULL;
+		else
+			dsc->nextReturn =
+			    list_entry(dsc->dirObj->variant.dir_variant.
+				       children.next, struct yaffs_obj,
+				       siblings);
 	} else {
 		/* Hey someone isn't playing nice! */
 	}
 }
 
-static void yaffsfs_DirAdvance(yaffsfs_DirectorySearchContext *dsc)
+static void yaffsfs_DirAdvance(struct yaffsfs_DirSearchContxt *dsc)
 {
-	if(dsc &&
-	   dsc->dirObj &&
-	   dsc->dirObj->variantType == YAFFS_OBJECT_TYPE_DIRECTORY){
-
-	   if( dsc->nextReturn == NULL ||
-	       list_empty(&dsc->dirObj->variant.directoryVariant.children)){
-	   	dsc->nextReturn = NULL;
-	   } else {
-		   struct list_head *next = dsc->nextReturn->siblings.next;
-
-		   if( next == &dsc->dirObj->variant.directoryVariant.children)
-	   		dsc->nextReturn = NULL; /* end of list */
-	   	   else
-		   	dsc->nextReturn = list_entry(next,yaffs_Object,siblings);
-	   }
+	if (dsc &&
+	    dsc->dirObj &&
+	    dsc->dirObj->variant_type == YAFFS_OBJECT_TYPE_DIRECTORY) {
+
+		if (dsc->nextReturn == NULL ||
+		    list_empty(&dsc->dirObj->variant.dir_variant.children))
+			dsc->nextReturn = NULL;
+		else {
+			struct list_head *next = dsc->nextReturn->siblings.next;
+
+			if (next == &dsc->dirObj->variant.dir_variant.children)
+				dsc->nextReturn = NULL;	/* end of list */
+			else
+				dsc->nextReturn = list_entry(next,
+							     struct yaffs_obj,
+							     siblings);
+		}
 	} else {
 		/* Hey someone isn't playing nice! */
 	}
 }
 
-static void yaffsfs_RemoveObjectCallback(yaffs_Object *obj)
+static void yaffsfs_RemoveObjectCallback(struct yaffs_obj *obj)
 {
 
 	struct list_head *i;
-	yaffsfs_DirectorySearchContext *dsc;
+	struct yaffsfs_DirSearchContxt *dsc;
 
 	/* if search contexts not initilised then skip */
-	if(!search_contexts.next)
+	if (!search_contexts.next)
 		return;
 
-	/* Iteratethrough the directory search contexts.
+	/* Iterate through the directory search contexts.
 	 * If any are the one being removed, then advance the dsc to
 	 * the next one to prevent a hanging ptr.
 	 */
-	 list_for_each(i, &search_contexts) {
+	list_for_each(i, &search_contexts) {
 		if (i) {
-			dsc = list_entry(i, yaffsfs_DirectorySearchContext,others);
-			if(dsc->nextReturn == obj)
+			dsc = list_entry(i, struct yaffsfs_DirSearchContxt,
+					 others);
+			if (dsc->nextReturn == obj)
 				yaffsfs_DirAdvance(dsc);
 		}
 	}
 
 }
 
-yaffs_DIR *yaffs_opendir(const char *dirname)
+yaffs_DIR *yaffs_opendir(const YCHAR *dirname)
 {
 	yaffs_DIR *dir = NULL;
- 	yaffs_Object *obj = NULL;
-	yaffsfs_DirectorySearchContext *dsc = NULL;
+	struct yaffs_obj *obj = NULL;
+	struct yaffsfs_DirSearchContxt *dsc = NULL;
+	int notDir = 0;
+	int loop = 0;
+
+	if (!dirname) {
+		yaffsfs_SetError(-EFAULT);
+		return NULL;
+	}
+
+	if (yaffsfs_CheckPath(dirname) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return NULL;
+	}
 
 	yaffsfs_Lock();
 
-	obj = yaffsfs_FindObject(NULL,dirname,0);
+	obj = yaffsfs_FindObject(NULL, dirname, 0, 1, NULL, &notDir, &loop);
+
+	if (!obj && notDir)
+		yaffsfs_SetError(-ENOTDIR);
+	else if (loop)
+		yaffsfs_SetError(-ELOOP);
+	else if (!obj)
+		yaffsfs_SetError(-ENOENT);
+	else if (obj->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY)
+		yaffsfs_SetError(-ENOTDIR);
+	else {
+		int i;
+
+		for (i = 0, dsc = NULL; i < YAFFSFS_N_DSC && !dsc; i++) {
+			if (!yaffsfs_dsc[i].inUse)
+				dsc = &yaffsfs_dsc[i];
+		}
 
-	if(obj && obj->variantType == YAFFS_OBJECT_TYPE_DIRECTORY)
-	{
+		dir = (yaffs_DIR *) dsc;
 
-		dsc = YMALLOC(sizeof(yaffsfs_DirectorySearchContext));
-		dir = (yaffs_DIR *)dsc;
-		if(dsc)
-		{
-			memset(dsc,0,sizeof(yaffsfs_DirectorySearchContext));
-			dsc->magic = YAFFS_MAGIC;
+		if (dsc) {
+			memset(dsc, 0, sizeof(struct yaffsfs_DirSearchContxt));
+			dsc->inUse = 1;
 			dsc->dirObj = obj;
-			strncpy(dsc->name,dirname,NAME_MAX);
+			yaffs_strncpy(dsc->name, dirname, NAME_MAX);
 			INIT_LIST_HEAD(&dsc->others);
 
-			if(!search_contexts.next)
+			if (!search_contexts.next)
 				INIT_LIST_HEAD(&search_contexts);
 
-			list_add(&dsc->others,&search_contexts);
-			yaffsfs_SetDirRewound(dsc);		}
+			list_add(&dsc->others, &search_contexts);
+			yaffsfs_SetDirRewound(dsc);
+		}
 
 	}
 
@@ -1295,35 +2917,34 @@ yaffs_DIR *yaffs_opendir(const char *dirname)
 	return dir;
 }
 
-struct yaffs_dirent *yaffs_readdir(yaffs_DIR *dirp)
+struct yaffs_dirent *yaffs_readdir(yaffs_DIR * dirp)
 {
-	yaffsfs_DirectorySearchContext *dsc = (yaffsfs_DirectorySearchContext *)dirp;
+	struct yaffsfs_DirSearchContxt *dsc;
 	struct yaffs_dirent *retVal = NULL;
 
+	dsc = (struct yaffsfs_DirSearchContxt *) dirp;
 	yaffsfs_Lock();
 
-	if(dsc && dsc->magic == YAFFS_MAGIC){
+	if (dsc && dsc->inUse) {
 		yaffsfs_SetError(0);
-		if(dsc->nextReturn){
-			dsc->de.d_ino = yaffs_GetEquivalentObject(dsc->nextReturn)->objectId;
+		if (dsc->nextReturn) {
+			dsc->de.d_ino =
+			    yaffs_get_equivalent_obj(dsc->nextReturn)->obj_id;
 			dsc->de.d_dont_use = (unsigned)dsc->nextReturn;
 			dsc->de.d_off = dsc->offset++;
-			yaffs_GetObjectName(dsc->nextReturn,dsc->de.d_name,NAME_MAX);
-			if(strlen(dsc->de.d_name) == 0)
-			{
-				// this should not happen!
-				strcpy(dsc->de.d_name,"zz");
+			yaffs_get_obj_name(dsc->nextReturn,
+					   dsc->de.d_name, NAME_MAX);
+			if (yaffs_strnlen(dsc->de.d_name, NAME_MAX + 1) == 0) {
+				/* this should not happen! */
+				yaffs_strcpy(dsc->de.d_name, _Y("zz"));
 			}
 			dsc->de.d_reclen = sizeof(struct yaffs_dirent);
 			retVal = &dsc->de;
 			yaffsfs_DirAdvance(dsc);
 		} else
 			retVal = NULL;
-	}
-	else
-	{
+	} else
 		yaffsfs_SetError(-EBADF);
-	}
 
 	yaffsfs_Unlock();
 
@@ -1331,10 +2952,11 @@ struct yaffs_dirent *yaffs_readdir(yaffs_DIR *dirp)
 
 }
 
-
 void yaffs_rewinddir(yaffs_DIR *dirp)
 {
-	yaffsfs_DirectorySearchContext *dsc = (yaffsfs_DirectorySearchContext *)dirp;
+	struct yaffsfs_DirSearchContxt *dsc;
+
+	dsc = (struct yaffsfs_DirSearchContxt *) dirp;
 
 	yaffsfs_Lock();
 
@@ -1343,41 +2965,67 @@ void yaffs_rewinddir(yaffs_DIR *dirp)
 	yaffsfs_Unlock();
 }
 
-
 int yaffs_closedir(yaffs_DIR *dirp)
 {
-	yaffsfs_DirectorySearchContext *dsc = (yaffsfs_DirectorySearchContext *)dirp;
+	struct yaffsfs_DirSearchContxt *dsc;
+
+	dsc = (struct yaffsfs_DirSearchContxt *) dirp;
+
+	if (!dsc) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
 
 	yaffsfs_Lock();
-	dsc->magic = 0;
-	list_del(&dsc->others); /* unhook from list */
-	YFREE(dsc);
+	dsc->inUse = 0;
+	list_del(&dsc->others);	/* unhook from list */
 	yaffsfs_Unlock();
 	return 0;
 }
 
-// end of directory stuff
-
+/* End of directory stuff */
 
-int yaffs_symlink(const char *oldpath, const char *newpath)
+int yaffs_symlink(const YCHAR *oldpath, const YCHAR *newpath)
 {
-	yaffs_Object *parent = NULL;
-	yaffs_Object *obj;
-	char *name;
-	int retVal= -1;
-	int mode = 0; // ignore for now
+	struct yaffs_obj *parent = NULL;
+	struct yaffs_obj *obj;
+	YCHAR *name;
+	int retVal = -1;
+	int mode = 0;		/* ignore for now */
+	int notDir = 0;
+	int loop = 0;
 
-	yaffsfs_Lock();
-	parent = yaffsfs_FindDirectory(NULL,newpath,&name,0);
-	obj = yaffs_MknodSymLink(parent,name,mode,0,0,oldpath);
-	if(obj)
-	{
-		retVal = 0;
+	if (!oldpath || !newpath) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
 	}
-	else
-	{
-		yaffsfs_SetError(-ENOSPC); // just assume no space for now
-		retVal = -1;
+
+	if (yaffsfs_CheckPath(newpath) < 0 || yaffsfs_CheckPath(oldpath) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return -1;
+	}
+
+	yaffsfs_Lock();
+	parent = yaffsfs_FindDirectory(NULL, newpath, &name, 0, &notDir, &loop);
+	if (!parent && notDir)
+		yaffsfs_SetError(-ENOTDIR);
+	else if (loop)
+		yaffsfs_SetError(-ELOOP);
+	else if (!parent || yaffs_strnlen(name, 5) < 1)
+		yaffsfs_SetError(-ENOENT);
+	else if (yaffsfs_TooManyObjects(parent->my_dev))
+		yaffsfs_SetError(-ENFILE);
+	else if (parent->my_dev->read_only)
+		yaffsfs_SetError(-EROFS);
+	else if (parent) {
+		obj = yaffs_create_symlink(parent, name, mode, 0, 0, oldpath);
+		if (obj)
+			retVal = 0;
+		else if (yaffsfs_FindObject
+			 (NULL, newpath, 0, 0, NULL, NULL, NULL))
+			yaffsfs_SetError(-EEXIST);
+		else
+			yaffsfs_SetError(-ENOSPC);
 	}
 
 	yaffsfs_Unlock();
@@ -1386,90 +3034,98 @@ int yaffs_symlink(const char *oldpath, const char *newpath)
 
 }
 
-int yaffs_readlink(const char *path, char *buf, int bufsiz)
+int yaffs_readlink(const YCHAR *path, YCHAR *buf, int bufsiz)
 {
-	yaffs_Object *obj = NULL;
-	int retVal;
+	struct yaffs_obj *obj = NULL;
+	struct yaffs_obj *dir = NULL;
+	int retVal = -1;
+	int notDir = 0;
+	int loop = 0;
 
+	if (!path || !buf) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
 
 	yaffsfs_Lock();
 
-	obj = yaffsfs_FindObject(NULL,path,0);
+	obj = yaffsfs_FindObject(NULL, path, 0, 1, &dir, &notDir, &loop);
 
-	if(!obj)
-	{
+	if (!dir && notDir)
+		yaffsfs_SetError(-ENOTDIR);
+	else if (loop)
+		yaffsfs_SetError(-ELOOP);
+	else if (!dir || !obj)
 		yaffsfs_SetError(-ENOENT);
-		retVal = -1;
-	}
-	else if(obj->variantType != YAFFS_OBJECT_TYPE_SYMLINK)
-	{
+	else if (obj->variant_type != YAFFS_OBJECT_TYPE_SYMLINK)
 		yaffsfs_SetError(-EINVAL);
-		retVal = -1;
-	}
-	else
-	{
-		char *alias = obj->variant.symLinkVariant.alias;
-		memset(buf,0,bufsiz);
-		strncpy(buf,alias,bufsiz - 1);
+	else {
+		YCHAR *alias = obj->variant.symlink_variant.alias;
+		memset(buf, 0, bufsiz);
+		yaffs_strncpy(buf, alias, bufsiz - 1);
 		retVal = 0;
 	}
 	yaffsfs_Unlock();
 	return retVal;
 }
 
-int yaffs_link(const char *oldpath, const char *newpath)
+int yaffs_link(const YCHAR *oldpath, const YCHAR *linkpath)
 {
-	// Creates a link called newpath to existing oldpath
-	yaffs_Object *obj = NULL;
-	yaffs_Object *target = NULL;
-	int retVal = 0;
+	/* Creates a link called newpath to existing oldpath */
+	struct yaffs_obj *obj = NULL;
+	struct yaffs_obj *lnk = NULL;
+	struct yaffs_obj *obj_dir = NULL;
+	struct yaffs_obj *lnk_dir = NULL;
+	int retVal = -1;
+	int notDirObj = 0;
+	int notDirLnk = 0;
+	int objLoop = 0;
+	int lnkLoop = 0;
+	YCHAR *newname;
+
+	if (!oldpath || !linkpath) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
 
+	if (yaffsfs_CheckPath(linkpath) < 0 || yaffsfs_CheckPath(oldpath) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return -1;
+	}
 
 	yaffsfs_Lock();
 
-	obj = yaffsfs_FindObject(NULL,oldpath,0);
-	target = yaffsfs_FindObject(NULL,newpath,0);
+	obj = yaffsfs_FindObject(NULL, oldpath, 0, 1,
+				 &obj_dir, &notDirObj, &objLoop);
+	lnk = yaffsfs_FindObject(NULL, linkpath, 0, 0, NULL, NULL, NULL);
+	lnk_dir = yaffsfs_FindDirectory(NULL, linkpath, &newname,
+					0, &notDirLnk, &lnkLoop);
 
-	if(!obj)
-	{
+	if ((!obj_dir && notDirObj) || (!lnk_dir && notDirLnk))
+		yaffsfs_SetError(-ENOTDIR);
+	else if (objLoop || lnkLoop)
+		yaffsfs_SetError(-ELOOP);
+	else if (!obj_dir || !lnk_dir || !obj)
 		yaffsfs_SetError(-ENOENT);
-		retVal = -1;
-	}
-	else if(target)
-	{
+	else if (obj->my_dev->read_only)
+		yaffsfs_SetError(-EROFS);
+	else if (yaffsfs_TooManyObjects(obj->my_dev))
+		yaffsfs_SetError(-ENFILE);
+	else if (lnk)
 		yaffsfs_SetError(-EEXIST);
-		retVal = -1;
-	}
-	else
-	{
-		yaffs_Object *newdir = NULL;
-		yaffs_Object *link = NULL;
-
-		char *newname;
-
-		newdir = yaffsfs_FindDirectory(NULL,newpath,&newname,0);
+	else if (lnk_dir->my_dev != obj->my_dev)
+		yaffsfs_SetError(-EXDEV);
+	else {
+		retVal = yaffsfs_CheckNameLength(newname);
 
-		if(!newdir)
-		{
-			yaffsfs_SetError(-ENOTDIR);
-			retVal = -1;
-		}
-		else if(newdir->myDev != obj->myDev)
-		{
-			yaffsfs_SetError(-EXDEV);
-			retVal = -1;
-		}
-		if(newdir && strlen(newname) > 0)
-		{
-			link = yaffs_Link(newdir,newname,obj);
-			if(link)
+		if (retVal == 0) {
+			lnk = yaffs_link_obj(lnk_dir, newname, obj);
+			if (lnk)
 				retVal = 0;
-			else
-			{
+			else {
 				yaffsfs_SetError(-ENOSPC);
 				retVal = -1;
 			}
-
 		}
 	}
 	yaffsfs_Unlock();
@@ -1477,34 +3133,84 @@ int yaffs_link(const char *oldpath, const char *newpath)
 	return retVal;
 }
 
-int yaffs_mknod(const char *pathname, mode_t mode, dev_t dev);
+int yaffs_mknod(const YCHAR *pathname, mode_t mode, dev_t dev)
+{
+	pathname = pathname;
+	mode = mode;
+	dev = dev;
+
+	yaffsfs_SetError(-EINVAL);
+	return -1;
+}
+
+/*
+ * D E B U G   F U N C T I O N S
+ */
 
-int yaffs_DumpDevStruct(const char *path)
+/*
+ * yaffs_n_handles()
+ * Returns number of handles attached to the object
+ */
+int yaffs_n_handles(const YCHAR *path)
 {
-	char *rest;
+	struct yaffs_obj *obj;
+
+	if (!path) {
+		yaffsfs_SetError(-EFAULT);
+		return -1;
+	}
 
-	yaffs_Object *obj = yaffsfs_FindRoot(path,&rest);
+	if (yaffsfs_CheckPath(path) < 0) {
+		yaffsfs_SetError(-ENAMETOOLONG);
+		return -1;
+	}
 
-	if(obj)
-	{
-		yaffs_Device *dev = obj->myDev;
+	obj = yaffsfs_FindObject(NULL, path, 0, 1, NULL, NULL, NULL);
+
+	if (obj)
+		return yaffsfs_CountHandles(obj);
+	else
+		return -1;
+}
+
+int yaffs_get_error(void)
+{
+	return yaffsfs_GetLastError();
+}
+
+int yaffs_set_error(int error)
+{
+	yaffsfs_SetError(error);
+	return 0;
+}
+
+int yaffs_dump_dev(const YCHAR *path)
+{
+#if 1
+	path = path;
+#else
+	YCHAR *rest;
+
+	struct yaffs_obj *obj = yaffsfs_FindRoot(path, &rest);
+
+	if (obj) {
+		struct yaffs_dev *dev = obj->my_dev;
 
 		printf("\n"
-			   "nPageWrites.......... %d\n"
-			   "nPageReads........... %d\n"
-			   "nBlockErasures....... %d\n"
-			   "nGCCopies............ %d\n"
-			   "garbageCollections... %d\n"
-			   "passiveGarbageColl'ns %d\n"
-			   "\n",
-				dev->nPageWrites,
-				dev->nPageReads,
-				dev->nBlockErasures,
-				dev->nGCCopies,
-				dev->garbageCollections,
-				dev->passiveGarbageCollections
-		);
+		       "n_page_writes.......... %d\n"
+		       "n_page_reads........... %d\n"
+		       "n_erasures....... %d\n"
+		       "n_gc_copies............ %d\n"
+		       "garbageCollections... %d\n"
+		       "passiveGarbageColl'ns %d\n"
+		       "\n",
+		       dev->n_page_writes,
+		       dev->n_page_reads,
+		       dev->n_erasures,
+		       dev->n_gc_copies,
+		       dev->garbageCollections, dev->passiveGarbageCollections);
 
 	}
+#endif
 	return 0;
 }
diff --git a/fs/yaffs2/yaffsfs.h b/fs/yaffs2/yaffsfs.h
index 95e7a914b3..f2c7666625 100644
--- a/fs/yaffs2/yaffsfs.h
+++ b/fs/yaffs2/yaffsfs.h
@@ -1,7 +1,7 @@
 /*
  * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
  *
- * Copyright (C) 2002-2007 Aleph One Ltd.
+ * Copyright (C) 2002-2011 Aleph One Ltd.
  *   for Toby Churchill Ltd and Brightstar Engineering
  *
  * Created by Charles Manning <charles@aleph1.co.uk>
@@ -26,206 +26,184 @@
 #include "yportenv.h"
 
 
-//typedef long off_t;
-//typedef long dev_t;
-//typedef unsigned long mode_t;
-
-
 #ifndef NAME_MAX
 #define NAME_MAX	256
 #endif
 
-#ifndef O_RDONLY
-#define O_RDONLY	00
-#endif
-
-#ifndef O_WRONLY
-#define O_WRONLY	01
-#endif
-
-#ifndef O_RDWR
-#define O_RDWR		02
-#endif
+#define YAFFS_MAX_FILE_SIZE (0x800000000LL - 1)
 
-#ifndef O_CREAT
-#define O_CREAT 	0100
-#endif
 
-#ifndef O_EXCL
-#define O_EXCL		0200
-#endif
-
-#ifndef O_TRUNC
-#define O_TRUNC		01000
-#endif
+struct yaffs_dirent {
+	long d_ino;			/* inode number */
+	off_t d_off;			/* offset to this dirent */
+	unsigned short d_reclen;	/* length of this dirent */
+	YUCHAR d_type;			/* type of this record */
+	YCHAR d_name[NAME_MAX+1];	/* file name (null-terminated) */
+	unsigned d_dont_use;		/* debug: not for public consumption */
+};
 
-#ifndef O_APPEND
-#define O_APPEND	02000
+typedef struct opaque_structure yaffs_DIR;
+
+
+
+struct yaffs_stat {
+	int		st_dev;		/* device */
+	int		st_ino;		/* inode */
+	unsigned	st_mode;	/* protection */
+	int		st_nlink;	/* number of hard links */
+	int		st_uid;		/* user ID of owner */
+	int		st_gid;		/* group ID of owner */
+	unsigned	st_rdev;	/* device type (if inode device) */
+	loff_t		st_size;	/* total size, in bytes */
+	unsigned long	st_blksize;	/* blocksize for filesystem I/O */
+	unsigned long	st_blocks;	/* number of blocks allocated */
+#ifdef CONFIG_YAFFS_WINCE
+	/* Special 64-bit times for WinCE */
+	unsigned long	yst_wince_atime[2];
+	unsigned long	yst_wince_mtime[2];
+	unsigned long	yst_wince_ctime[2];
+#else
+	unsigned long	yst_atime;	/* time of last access */
+	unsigned long	yst_mtime;	/* time of last modification */
+	unsigned long	yst_ctime;	/* time of last change */
 #endif
+};
 
-#ifndef SEEK_SET
-#define SEEK_SET	0
-#endif
 
-#ifndef SEEK_CUR
-#define SEEK_CUR	1
-#endif
+struct yaffs_utimbuf {
+	unsigned long actime;
+	unsigned long modtime;
+};
 
-#ifndef SEEK_END
-#define SEEK_END	2
-#endif
 
-#ifndef EBUSY
-#define EBUSY	16
-#endif
+int yaffs_open(const YCHAR *path, int oflag, int mode) ;
 
-#ifndef ENODEV
-#define ENODEV	19
-#endif
-
-#ifndef EINVAL
-#define EINVAL	22
-#endif
+int yaffs_close(int fd) ;
+int yaffs_fsync(int fd) ;
+int yaffs_fdatasync(int fd) ;
+int yaffs_flush(int fd) ; /* same as yaffs_fsync() */
 
-#ifndef EBADF
-#define EBADF	9
-#endif
+int yaffs_access(const YCHAR *path, int amode);
 
-#ifndef EACCESS
-#define EACCESS	13
-#endif
+int yaffs_dup(int fd);
 
-#ifndef EXDEV
-#define EXDEV	18
-#endif
+int yaffs_read(int fd, void *buf, unsigned int nbyte) ;
+int yaffs_write(int fd, const void *buf, unsigned int nbyte) ;
 
-#ifndef ENOENT
-#define ENOENT	2
-#endif
+int yaffs_pread(int fd, void *buf, unsigned int nbyte, loff_t offset);
+int yaffs_pwrite(int fd, const void *buf, unsigned int nbyte, loff_t offset);
 
-#ifndef ENOSPC
-#define ENOSPC	28
-#endif
+loff_t yaffs_lseek(int fd, loff_t offset, int whence) ;
 
-#ifndef ENOTEMPTY
-#define ENOTEMPTY 39
-#endif
+int yaffs_truncate(const YCHAR *path, loff_t new_size);
+int yaffs_ftruncate(int fd, loff_t new_size);
 
-#ifndef ENOMEM
-#define ENOMEM 12
-#endif
+int yaffs_unlink(const YCHAR *path) ;
+int yaffs_rename(const YCHAR *oldPath, const YCHAR *newPath) ;
 
-#ifndef EEXIST
-#define EEXIST 17
-#endif
+int yaffs_stat(const YCHAR *path, struct yaffs_stat *buf) ;
+int yaffs_lstat(const YCHAR *path, struct yaffs_stat *buf) ;
+int yaffs_fstat(int fd, struct yaffs_stat *buf) ;
 
-#ifndef ENOTDIR
-#define ENOTDIR 20
-#endif
+int yaffs_utime(const YCHAR *path, const struct yaffs_utimbuf *buf);
+int yaffs_futime(int fd, const struct yaffs_utimbuf *buf);
 
-#ifndef EISDIR
-#define EISDIR 21
-#endif
 
+int yaffs_setxattr(const char *path, const char *name,
+			const void *data, int size, int flags);
+int yaffs_lsetxattr(const char *path, const char *name,
+			const void *data, int size, int flags);
+int yaffs_fsetxattr(int fd, const char *name,
+			const void *data, int size, int flags);
 
-// Mode flags
+int yaffs_getxattr(const char *path, const char *name,
+			void *data, int size);
+int yaffs_lgetxattr(const char *path, const char *name,
+			void *data, int size);
+int yaffs_fgetxattr(int fd, const char *name,
+			void *data, int size);
 
-#ifndef S_IFMT
-#define S_IFMT		0170000
-#endif
+int yaffs_removexattr(const char *path, const char *name);
+int yaffs_lremovexattr(const char *path, const char *name);
+int yaffs_fremovexattr(int fd, const char *name);
 
-#ifndef S_IFLNK
-#define S_IFLNK		0120000
-#endif
+int yaffs_listxattr(const char *path, char *list, int size);
+int yaffs_llistxattr(const char *path, char *list, int size);
+int yaffs_flistxattr(int fd, char *list, int size);
 
-#ifndef S_IFDIR
-#define S_IFDIR		0040000
-#endif
 
-#ifndef S_IFREG
-#define S_IFREG		0100000
-#endif
+#ifdef CONFIG_YAFFS_WINCE
 
-#ifndef S_IREAD
-#define S_IREAD		0000400
-#endif
+int yaffs_set_wince_times(int fd,
+			const unsigned *wctime,
+			const unsigned *watime,
+			const unsigned *wmtime);
+int yaffs_get_wince_times(int fd,
+			unsigned *wctime,
+			unsigned *watime,
+			unsigned *wmtime);
 
-#ifndef S_IWRITE
-#define	S_IWRITE	0000200
 #endif
 
+int yaffs_chmod(const YCHAR *path, mode_t mode);
+int yaffs_fchmod(int fd, mode_t mode);
 
+int yaffs_mkdir(const YCHAR *path, mode_t mode) ;
+int yaffs_rmdir(const YCHAR *path) ;
 
+yaffs_DIR *yaffs_opendir(const YCHAR *dirname) ;
+struct yaffs_dirent *yaffs_readdir(yaffs_DIR *dirp) ;
+void yaffs_rewinddir(yaffs_DIR *dirp) ;
+int yaffs_closedir(yaffs_DIR *dirp) ;
 
-struct yaffs_dirent{
-    long d_ino;                 /* inode number */
-    off_t d_off;                /* offset to this dirent */
-    unsigned short d_reclen;    /* length of this d_name */
-    char d_name [NAME_MAX+1];   /* file name (null-terminated) */
-    unsigned d_dont_use;	/* debug pointer, not for public consumption */
-};
-
-typedef struct yaffs_dirent yaffs_dirent;
-
-
-typedef struct __opaque yaffs_DIR;
-
+int yaffs_mount(const YCHAR *path) ;
+int yaffs_mount2(const YCHAR *path, int read_only);
+int yaffs_mount_common(const YCHAR *path, int read_only, int skip_checkpt);
 
+int yaffs_unmount(const YCHAR *path) ;
+int yaffs_unmount2(const YCHAR *path, int force);
+int yaffs_remount(const YCHAR *path, int force, int read_only);
 
-struct yaffs_stat{
-    int		      st_dev;      /* device */
-    int           st_ino;      /* inode */
-    mode_t        st_mode;     /* protection */
-    int           st_nlink;    /* number of hard links */
-    int           st_uid;      /* user ID of owner */
-    int           st_gid;      /* group ID of owner */
-    unsigned      st_rdev;     /* device type (if inode device) */
-    off_t         st_size;     /* total size, in bytes */
-    unsigned long st_blksize;  /* blocksize for filesystem I/O */
-    unsigned long st_blocks;   /* number of blocks allocated */
-    unsigned long yst_atime;    /* time of last access */
-    unsigned long yst_mtime;    /* time of last modification */
-    unsigned long yst_ctime;    /* time of last change */
-};
 
-int yaffs_open(const char *path, int oflag, int mode) ;
-int yaffs_read(int fd, void *buf, unsigned int nbyte) ;
-int yaffs_write(int fd, const void *buf, unsigned int nbyte) ;
-int yaffs_close(int fd) ;
-off_t yaffs_lseek(int fd, off_t offset, int whence) ;
-int yaffs_truncate(int fd, off_t newSize);
+int yaffs_sync(const YCHAR *path) ;
 
-int yaffs_unlink(const char *path) ;
-int yaffs_rename(const char *oldPath, const char *newPath) ;
+int yaffs_symlink(const YCHAR *oldpath, const YCHAR *newpath);
+int yaffs_readlink(const YCHAR *path, YCHAR *buf, int bufsiz);
 
-int yaffs_stat(const char *path, struct yaffs_stat *buf) ;
-int yaffs_lstat(const char *path, struct yaffs_stat *buf) ;
-int yaffs_fstat(int fd, struct yaffs_stat *buf) ;
+int yaffs_link(const YCHAR *oldpath, const YCHAR *newpath);
+int yaffs_mknod(const YCHAR *pathname, mode_t mode, dev_t dev);
 
-int yaffs_chmod(const char *path, mode_t mode);
-int yaffs_fchmod(int fd, mode_t mode);
+loff_t yaffs_freespace(const YCHAR *path);
+loff_t yaffs_totalspace(const YCHAR *path);
 
-int yaffs_mkdir(const char *path, mode_t mode) ;
-int yaffs_rmdir(const char *path) ;
+int yaffs_inodecount(const YCHAR *path);
 
-yaffs_DIR *yaffs_opendir(const char *dirname) ;
-struct yaffs_dirent *yaffs_readdir(yaffs_DIR *dirp) ;
-void yaffs_rewinddir(yaffs_DIR *dirp) ;
-int yaffs_closedir(yaffs_DIR *dirp) ;
+int yaffs_n_handles(const YCHAR *path);
 
-int yaffs_mount(const char *path) ;
-int yaffs_unmount(const char *path) ;
+#define YAFFS_SHARE_READ  1
+#define YAFFS_SHARE_WRITE 2
+int yaffs_open_sharing(const YCHAR *path, int oflag, int mode, int shareMode);
 
-int yaffs_symlink(const char *oldpath, const char *newpath);
-int yaffs_readlink(const char *path, char *buf, int bufsiz);
+struct yaffs_dev;
+void yaffs_add_device(struct yaffs_dev *dev);
 
-int yaffs_link(const char *oldpath, const char *newpath);
-int yaffs_mknod(const char *pathname, mode_t mode, dev_t dev);
+int yaffs_start_up(void);
+int yaffsfs_GetLastError(void);
 
-loff_t yaffs_freespace(const char *path);
+/* Functions to iterate through devices. NB Use with extreme care! */
+void yaffs_dev_rewind(void);
+struct yaffs_dev *yaffs_next_dev(void);
 
-void yaffs_initialise(yaffsfs_DeviceConfiguration *configList);
+/* Function to get the last error */
+int yaffs_get_error(void);
+const char *yaffs_error_to_str(int err);
 
-int yaffs_StartUp(void);
+/* Function only for debugging */
+void *yaffs_getdev(const YCHAR *path);
+int yaffs_dump_dev(const YCHAR *path);
+int yaffs_set_error(int error);
 
+/* Trace control functions */
+unsigned  yaffs_set_trace(unsigned tm);
+unsigned  yaffs_get_trace(void);
 #endif
diff --git a/fs/yaffs2/ydirectenv.h b/fs/yaffs2/ydirectenv.h
index b555810844..c2ffbfd56d 100644
--- a/fs/yaffs2/ydirectenv.h
+++ b/fs/yaffs2/ydirectenv.h
@@ -1,7 +1,7 @@
 /*
  * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
  *
- * Copyright (C) 2002-2007 Aleph One Ltd.
+ * Copyright (C) 2002-2011 Aleph One Ltd.
  *   for Toby Churchill Ltd and Brightstar Engineering
  *
  * Created by Charles Manning <charles@aleph1.co.uk>
@@ -20,73 +20,65 @@
 #ifndef __YDIRECTENV_H__
 #define __YDIRECTENV_H__
 
-/* Direct interface */
+#include <common.h>
+#include <malloc.h>
+#include <linux/compat.h>
 
-#include "devextras.h"
+#include "yaffs_osglue.h"
+
+void yaffs_bug_fn(const char *file_name, int line_no);
 
-/* XXX U-BOOT XXX */
-#if 0
-#include "stdlib.h"
-#include "stdio.h"
-#include "string.h"
-#include "assert.h"
-#endif
-#include "yaffs_malloc.h"
 
-/* XXX U-BOOT XXX */
-#if 0
-#define YBUG() assert(1)
-#endif
 
 #define YCHAR char
 #define YUCHAR unsigned char
 #define _Y(x) x
-#define yaffs_strcpy(a,b)    strcpy(a,b)
-#define yaffs_strncpy(a,b,c) strncpy(a,b,c)
-#define yaffs_strncmp(a,b,c) strncmp(a,b,c)
-#define yaffs_strlen(s)	     strlen(s)
-#define yaffs_sprintf	     sprintf
-#define yaffs_toupper(a)     toupper(a)
-
-#ifdef NO_Y_INLINE
-#define Y_INLINE
+
+#define yaffs_strcat(a, b)	strcat(a, b)
+#define yaffs_strcpy(a, b)	strcpy(a, b)
+#define yaffs_strncpy(a, b, c)	strncpy(a, b, c)
+#define yaffs_strnlen(s, m)	strnlen(s, m)
+#ifdef CONFIG_YAFFS_CASE_INSENSITIVE
+#define yaffs_strcmp(a, b)	strcasecmp(a, b)
+#define yaffs_strncmp(a, b, c)	strncasecmp(a, b, c)
 #else
-#define Y_INLINE inline
+#define yaffs_strcmp(a, b)	strcmp(a, b)
+#define yaffs_strncmp(a, b, c)	strncmp(a, b, c)
 #endif
 
-#define YMALLOC(x) yaffs_malloc(x)
-#define YFREE(x)   free(x)
-#define YMALLOC_ALT(x) yaffs_malloc(x)
-#define YFREE_ALT(x)   free(x)
 
-#define YMALLOC_DMA(x) yaffs_malloc(x)
+void yaffs_qsort(void *aa, size_t n, size_t es,
+		int (*cmp)(const void *, const void *));
 
-#define YYIELD()  do {} while(0)
+#define sort(base, n, sz, cmp_fn, swp) yaffs_qsort(base, n, sz, cmp_fn)
 
+#define YAFFS_PATH_DIVIDERS  "/"
 
+#ifdef NO_inline
+#define inline
+#endif
 
-//#define YINFO(s) YPRINTF(( __FILE__ " %d %s\n",__LINE__,s))
-//#define YALERT(s) YINFO(s)
-
+#define cond_resched()  do {} while (0)
 
-#define TENDSTR "\n"
-#define TSTR(x) x
-#define TOUT(p) printf p
+#define yaffs_trace(msk, fmt, ...) do { \
+	if (yaffs_trace_mask & (msk)) \
+		printf("yaffs: " fmt "\n", ##__VA_ARGS__); \
+} while (0)
 
 
 #define YAFFS_LOSTNFOUND_NAME		"lost+found"
 #define YAFFS_LOSTNFOUND_PREFIX		"obj"
-//#define YPRINTF(x) printf x
 
 #include "yaffscfg.h"
 
 #define Y_CURRENT_TIME yaffsfs_CurrentTime()
 #define Y_TIME_CONVERT(x) x
 
-#define YAFFS_ROOT_MODE				0666
+#define YAFFS_ROOT_MODE			0666
 #define YAFFS_LOSTNFOUND_MODE		0666
 
-#define yaffs_SumCompare(x,y) ((x) == (y))
-#define yaffs_strcmp(a,b) strcmp(a,b)
+#include "yaffs_list.h"
+
+#include "yaffsfs.h"
 
 #endif
diff --git a/fs/yaffs2/yportenv.h b/fs/yaffs2/yportenv.h
index bbab14d503..251eba0792 100644
--- a/fs/yaffs2/yportenv.h
+++ b/fs/yaffs2/yportenv.h
@@ -1,7 +1,7 @@
 /*
  * YAFFS: Yet another Flash File System . A NAND-flash specific file system.
  *
- * Copyright (C) 2002-2007 Aleph One Ltd.
+ * Copyright (C) 2002-2011 Aleph One Ltd.
  *   for Toby Churchill Ltd and Brightstar Engineering
  *
  * Created by Charles Manning <charles@aleph1.co.uk>
@@ -17,82 +17,63 @@
 #ifndef __YPORTENV_H__
 #define __YPORTENV_H__
 
-/* XXX U-BOOT XXX */
-#ifndef CONFIG_YAFFS_DIRECT
-#define CONFIG_YAFFS_DIRECT
+#include <linux/types.h>
+
+/* Definition of types */
+#ifdef CONFIG_YAFFS_DEFINES_TYPES
+typedef unsigned char u8;
+typedef unsigned short u16;
+typedef unsigned u32;
 #endif
 
-#if defined CONFIG_YAFFS_WINCE
 
-#include "ywinceenv.h"
+#ifdef CONFIG_YAFFS_PROVIDE_DEFS
+/* File types */
+
+
+#define DT_UNKNOWN	0
+#define DT_FIFO		1
+#define DT_CHR		2
+#define DT_DIR		4
+#define DT_BLK		6
+#define DT_REG		8
+#define DT_LNK		10
+#define DT_SOCK		12
+#define DT_WHT		14
+
+
+/*
+ * Attribute flags.
+ * These are or-ed together to select what has been changed.
+ */
+#define ATTR_MODE	1
+#define ATTR_UID	2
+#define ATTR_GID	4
+#define ATTR_SIZE	8
+#define ATTR_ATIME	16
+#define ATTR_MTIME	32
+#define ATTR_CTIME	64
+
+struct iattr {
+	unsigned int ia_valid;
+	unsigned ia_mode;
+	unsigned ia_uid;
+	unsigned ia_gid;
+	unsigned ia_size;
+	unsigned ia_atime;
+	unsigned ia_mtime;
+	unsigned ia_ctime;
+	unsigned int ia_attr_flags;
+};
 
-/* XXX U-BOOT XXX */
-#elif  0 /* defined __KERNEL__ */
-
-#include "moduleconfig.h"
-
-/* Linux kernel */
-#include <linux/version.h>
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19))
-#include <linux/config.h>
-#endif
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/string.h>
-#include <linux/slab.h>
-#include <linux/vmalloc.h>
-
-#define YCHAR char
-#define YUCHAR unsigned char
-#define _Y(x)     x
-#define yaffs_strcpy(a,b)    strcpy(a,b)
-#define yaffs_strncpy(a,b,c) strncpy(a,b,c)
-#define yaffs_strncmp(a,b,c) strncmp(a,b,c)
-#define yaffs_strlen(s)	     strlen(s)
-#define yaffs_sprintf	     sprintf
-#define yaffs_toupper(a)     toupper(a)
-
-#define Y_INLINE inline
-
-#define YAFFS_LOSTNFOUND_NAME		"lost+found"
-#define YAFFS_LOSTNFOUND_PREFIX		"obj"
-
-/* #define YPRINTF(x) printk x */
-#define YMALLOC(x) kmalloc(x,GFP_KERNEL)
-#define YFREE(x)   kfree(x)
-#define YMALLOC_ALT(x) vmalloc(x)
-#define YFREE_ALT(x)   vfree(x)
-#define YMALLOC_DMA(x) YMALLOC(x)
-
-// KR - added for use in scan so processes aren't blocked indefinitely.
-#define YYIELD() schedule()
-
-#define YAFFS_ROOT_MODE			0666
-#define YAFFS_LOSTNFOUND_MODE		0666
-
-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0))
-#define Y_CURRENT_TIME CURRENT_TIME.tv_sec
-#define Y_TIME_CONVERT(x) (x).tv_sec
-#else
-#define Y_CURRENT_TIME CURRENT_TIME
-#define Y_TIME_CONVERT(x) (x)
 #endif
 
-#define yaffs_SumCompare(x,y) ((x) == (y))
-#define yaffs_strcmp(a,b) strcmp(a,b)
 
-#define TENDSTR "\n"
-#define TSTR(x) KERN_WARNING x
-#define TOUT(p) printk p
 
-#define yaffs_trace(mask, fmt, args...) \
-	do { if ((mask) & (yaffs_traceMask|YAFFS_TRACE_ERROR)) \
-		printk(KERN_WARNING "yaffs: " fmt, ## args); \
-	} while (0)
+#if defined CONFIG_YAFFS_WINCE
+
+#include "ywinceenv.h"
 
-#define compile_time_assertion(assertion) \
-	({ int x = __builtin_choose_expr(assertion, 0, (void)0); (void) x; })
 
 #elif defined CONFIG_YAFFS_DIRECT
 
@@ -101,93 +82,228 @@
 
 #elif defined CONFIG_YAFFS_UTIL
 
-/* Stuff for YAFFS utilities */
+#include "yutilsenv.h"
 
-#include "stdlib.h"
-#include "stdio.h"
-#include "string.h"
+#else
+/* Should have specified a configuration type */
+#error Unknown configuration
 
-#include "devextras.h"
+#endif
 
-#define YMALLOC(x) malloc(x)
-#define YFREE(x)   free(x)
-#define YMALLOC_ALT(x) malloc(x)
-#define YFREE_ALT(x) free(x)
+#if defined(CONFIG_YAFFS_DIRECT) || defined(CONFIG_YAFFS_WINCE)
 
-#define YCHAR char
-#define YUCHAR unsigned char
-#define _Y(x)     x
-#define yaffs_strcpy(a,b)    strcpy(a,b)
-#define yaffs_strncpy(a,b,c) strncpy(a,b,c)
-#define yaffs_strlen(s)	     strlen(s)
-#define yaffs_sprintf	     sprintf
-#define yaffs_toupper(a)     toupper(a)
+#ifdef CONFIG_YAFFSFS_PROVIDE_VALUES
 
-#define Y_INLINE inline
+#ifndef O_RDONLY
+#define O_RDONLY	00
+#endif
 
-/* #define YINFO(s) YPRINTF(( __FILE__ " %d %s\n",__LINE__,s)) */
-/* #define YALERT(s) YINFO(s) */
+#ifndef O_WRONLY
+#define O_WRONLY	01
+#endif
 
-#define TENDSTR "\n"
-#define TSTR(x) x
-#define TOUT(p) printf p
+#ifndef O_RDWR
+#define O_RDWR		02
+#endif
 
-#define YAFFS_LOSTNFOUND_NAME		"lost+found"
-#define YAFFS_LOSTNFOUND_PREFIX		"obj"
-/* #define YPRINTF(x) printf x */
+#ifndef O_CREAT
+#define O_CREAT		0100
+#endif
 
-#define YAFFS_ROOT_MODE				0666
-#define YAFFS_LOSTNFOUND_MODE		0666
+#ifndef O_EXCL
+#define O_EXCL		0200
+#endif
 
-#define yaffs_SumCompare(x,y) ((x) == (y))
-#define yaffs_strcmp(a,b) strcmp(a,b)
+#ifndef O_TRUNC
+#define O_TRUNC		01000
+#endif
 
-#else
-/* Should have specified a configuration type */
-#error Unknown configuration
+#ifndef O_APPEND
+#define O_APPEND	02000
+#endif
 
+#ifndef SEEK_SET
+#define SEEK_SET	0
 #endif
 
-/* see yaffs_fs.c */
-extern unsigned int yaffs_traceMask;
-extern unsigned int yaffs_wr_attempts;
+#ifndef SEEK_CUR
+#define SEEK_CUR	1
+#endif
 
-/*
- * Tracing flags.
- * The flags masked in YAFFS_TRACE_ALWAYS are always traced.
- */
+#ifndef SEEK_END
+#define SEEK_END	2
+#endif
+
+#ifndef EBUSY
+#define EBUSY	16
+#endif
+
+#ifndef ENODEV
+#define ENODEV	19
+#endif
+
+#ifndef EINVAL
+#define EINVAL	22
+#endif
+
+#ifndef ENFILE
+#define ENFILE	23
+#endif
+
+#ifndef EBADF
+#define EBADF	9
+#endif
+
+#ifndef EACCES
+#define EACCES	13
+#endif
+
+#ifndef EXDEV
+#define EXDEV	18
+#endif
+
+#ifndef ENOENT
+#define ENOENT	2
+#endif
+
+#ifndef ENOSPC
+#define ENOSPC	28
+#endif
+
+#ifndef EROFS
+#define EROFS	30
+#endif
+
+#ifndef ERANGE
+#define ERANGE 34
+#endif
+
+#ifndef ENODATA
+#define ENODATA 61
+#endif
+
+#ifndef ENOTEMPTY
+#define ENOTEMPTY 39
+#endif
+
+#ifndef ENAMETOOLONG
+#define ENAMETOOLONG 36
+#endif
+
+#ifndef ENOMEM
+#define ENOMEM 12
+#endif
+
+#ifndef EFAULT
+#define EFAULT 14
+#endif
+
+#ifndef EEXIST
+#define EEXIST 17
+#endif
+
+#ifndef ENOTDIR
+#define ENOTDIR 20
+#endif
+
+#ifndef EISDIR
+#define EISDIR 21
+#endif
+
+#ifndef ELOOP
+#define ELOOP	40
+#endif
+
+
+/* Mode flags */
+
+#ifndef S_IFMT
+#define S_IFMT		0170000
+#endif
+
+#ifndef S_IFSOCK
+#define S_IFSOCK	0140000
+#endif
+
+#ifndef S_IFIFO
+#define S_IFIFO		0010000
+#endif
+
+#ifndef S_IFCHR
+#define S_IFCHR		0020000
+#endif
+
+#ifndef S_IFBLK
+#define S_IFBLK		0060000
+#endif
+
+#ifndef S_IFLNK
+#define S_IFLNK		0120000
+#endif
+
+#ifndef S_IFDIR
+#define S_IFDIR		0040000
+#endif
+
+#ifndef S_IFREG
+#define S_IFREG		0100000
+#endif
+
+#define S_ISSOCK(m)	(((m) & S_IFMT) == S_IFSOCK)
+#define S_ISLNK(m)	(((m) & S_IFMT) == S_IFLNK)
+#define S_ISDIR(m)	(((m) & S_IFMT) == S_IFDIR)
+#define S_ISREG(m)	(((m) & S_IFMT) == S_IFREG)
+#define S_ISBLK(m)	(((m) & S_IFMT) == S_IFBLK)
+#define S_ISCHR(m)	(((m) & S_IFMT) == S_IFCHR)
+#define S_ISFIFO(m)	(((m) & S_IFMT) == S_IFIFO)
+
+
+#ifndef S_IREAD
+#define S_IREAD		0000400
+#endif
+
+#ifndef S_IWRITE
+#define	S_IWRITE	0000200
+#endif
+
+#ifndef S_IEXEC
+#define	S_IEXEC	0000100
+#endif
+
+#ifndef XATTR_CREATE
+#define XATTR_CREATE 1
+#endif
+
+#ifndef XATTR_REPLACE
+#define XATTR_REPLACE 2
+#endif
+
+#ifndef R_OK
+#define R_OK	4
+#define W_OK	2
+#define X_OK	1
+#define F_OK	0
+#endif
+
+#else
+#include <errno.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#endif
+
+#endif
+
+#ifndef Y_DUMP_STACK
+#define Y_DUMP_STACK() do { } while (0)
+#endif
 
-#define YAFFS_TRACE_OS			0x00000002
-#define YAFFS_TRACE_ALLOCATE		0x00000004
-#define YAFFS_TRACE_SCAN		0x00000008
-#define YAFFS_TRACE_BAD_BLOCKS		0x00000010
-#define YAFFS_TRACE_ERASE		0x00000020
-#define YAFFS_TRACE_GC			0x00000040
-#define YAFFS_TRACE_WRITE		0x00000080
-#define YAFFS_TRACE_TRACING		0x00000100
-#define YAFFS_TRACE_DELETION		0x00000200
-#define YAFFS_TRACE_BUFFERS		0x00000400
-#define YAFFS_TRACE_NANDACCESS		0x00000800
-#define YAFFS_TRACE_GC_DETAIL		0x00001000
-#define YAFFS_TRACE_SCAN_DEBUG		0x00002000
-#define YAFFS_TRACE_MTD			0x00004000
-#define YAFFS_TRACE_CHECKPOINT		0x00008000
-
-#define YAFFS_TRACE_VERIFY		0x00010000
-#define YAFFS_TRACE_VERIFY_NAND		0x00020000
-#define YAFFS_TRACE_VERIFY_FULL		0x00040000
-#define YAFFS_TRACE_VERIFY_ALL		0x000F0000
-
-
-#define YAFFS_TRACE_ERROR		0x40000000
-#define YAFFS_TRACE_BUG			0x80000000
-#define YAFFS_TRACE_ALWAYS		0xF0000000
-
-
-#define T(mask,p) do{ if((mask) & (yaffs_traceMask | YAFFS_TRACE_ALWAYS)) TOUT(p);} while(0)
-
-#ifndef CONFIG_YAFFS_WINCE
-#define YBUG() T(YAFFS_TRACE_BUG,(TSTR("==>> yaffs bug: " __FILE__ " %d" TENDSTR),__LINE__))
+#ifndef BUG
+#define BUG() do {\
+	yaffs_trace(YAFFS_TRACE_BUG,\
+		"==>> yaffs bug: " __FILE__ " %d",\
+		__LINE__);\
+	Y_DUMP_STACK();\
+} while (0)
 #endif
 
 #endif
diff --git a/include/.gitignore b/include/.gitignore
deleted file mode 100644
index 7cd3e90700..0000000000
--- a/include/.gitignore
+++ /dev/null
@@ -1,6 +0,0 @@
-/autoconf.mk*
-/asm
-/bmp_logo.h
-/bmp_logo_data.h
-/config.h
-/config.mk
diff --git a/include/aes.h b/include/aes.h
new file mode 100644
index 0000000000..41b0db29c1
--- /dev/null
+++ b/include/aes.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010 - 2011 NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _AES_REF_H_
+#define _AES_REF_H_
+
+/*
+ * AES encryption library, with small code size, supporting only 128-bit AES
+ *
+ * AES is a stream cipher which works a block at a time, with each block
+ * in this case being AES_KEY_LENGTH bytes.
+ */
+
+enum {
+	AES_STATECOLS	= 4,	/* columns in the state & expanded key */
+	AES_KEYCOLS	= 4,	/* columns in a key */
+	AES_ROUNDS	= 10,	/* rounds in encryption */
+
+	AES_KEY_LENGTH	= 128 / 8,
+	AES_EXPAND_KEY_LENGTH	= 4 * AES_STATECOLS * (AES_ROUNDS + 1),
+};
+
+/**
+ * Expand a key into a key schedule, which is then used for the other
+ * operations.
+ *
+ * \param key		Key, of length AES_KEY_LENGTH bytes
+ * \param expkey	Buffer to place expanded key, AES_EXPAND_KEY_LENGTH
+ */
+void aes_expand_key(u8 *key, u8 *expkey);
+
+/**
+ * Encrypt a single block of data
+ *
+ * in		Input data
+ * expkey	Expanded key to use for encryption (from aes_expand_key())
+ * out		Output data
+ */
+void aes_encrypt(u8 *in, u8 *expkey, u8 *out);
+
+/**
+ * Decrypt a single block of data
+ *
+ * in		Input data
+ * expkey	Expanded key to use for decryption (from aes_expand_key())
+ * out		Output data
+ */
+void aes_decrypt(u8 *in, u8 *expkey, u8 *out);
+
+#endif /* _AES_REF_H_ */
diff --git a/include/ahci.h b/include/ahci.h
index 465ea7fcbb..c4fb9e79a5 100644
--- a/include/ahci.h
+++ b/include/ahci.h
@@ -30,12 +30,13 @@
 #define AHCI_PCI_BAR		0x24
 #define AHCI_MAX_SG		56 /* hardware max is 64K */
 #define AHCI_CMD_SLOT_SZ	32
+#define AHCI_MAX_CMD_SLOT	32
 #define AHCI_RX_FIS_SZ		256
 #define AHCI_CMD_TBL_HDR	0x80
 #define AHCI_CMD_TBL_CDB	0x40
 #define AHCI_CMD_TBL_SZ		AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16)
-#define AHCI_PORT_PRIV_DMA_SZ	AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ	\
-				+ AHCI_RX_FIS_SZ
+#define AHCI_PORT_PRIV_DMA_SZ	(AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \
+				AHCI_CMD_TBL_SZ	+ AHCI_RX_FIS_SZ)
 #define AHCI_CMD_ATAPI		(1 << 5)
 #define AHCI_CMD_WRITE		(1 << 6)
 #define AHCI_CMD_PREFETCH	(1 << 7)
diff --git a/include/android/android_boot.h b/include/android/android_boot.h
new file mode 100644
index 0000000000..1dd8d19fcc
--- /dev/null
+++ b/include/android/android_boot.h
@@ -0,0 +1,6 @@
+#ifndef _ANDROID_BOOT_H_
+#define _ANDROID_BOOT_H_
+
+void creat_atags(unsigned taddr, const char *cmdline, unsigned raddr, unsigned rsize);
+void boot_linux(unsigned kaddr,unsigned taddr);
+#endif
diff --git a/include/android/android_bootimg.h b/include/android/android_bootimg.h
new file mode 100644
index 0000000000..422d1c11dc
--- /dev/null
+++ b/include/android/android_bootimg.h
@@ -0,0 +1,103 @@
+/* tools/mkbootimg/bootimg.h
+**
+** Copyright 2007, The Android Open Source Project
+**
+** Licensed under the Apache License, Version 2.0 (the "License"); 
+** you may not use this file except in compliance with the License. 
+** You may obtain a copy of the License at 
+**
+**     http://www.apache.org/licenses/LICENSE-2.0 
+**
+** Unless required by applicable law or agreed to in writing, software 
+** distributed under the License is distributed on an "AS IS" BASIS, 
+** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 
+** See the License for the specific language governing permissions and 
+** limitations under the License.
+*/
+
+#ifndef _BOOT_IMAGE_H_
+#define _BOOT_IMAGE_H_
+
+typedef struct boot_img_hdr boot_img_hdr;
+
+#define BOOT_MAGIC "ANDROID!"
+#define BOOT_MAGIC_SIZE 8
+#define BOOT_NAME_SIZE 16
+#define BOOT_ARGS_SIZE 512
+
+struct boot_img_hdr
+{
+    unsigned char magic[BOOT_MAGIC_SIZE];
+
+    unsigned kernel_size;  /* size in bytes */
+    unsigned kernel_addr;  /* physical load addr */
+
+    unsigned ramdisk_size; /* size in bytes */
+    unsigned ramdisk_addr; /* physical load addr */
+
+    unsigned second_size;  /* size in bytes */
+    unsigned second_addr;  /* physical load addr */
+
+    unsigned tags_addr;    /* physical addr for kernel tags */
+    unsigned page_size;    /* flash page size we assume */
+    unsigned unused[2];    /* future expansion: should be 0 */
+
+    unsigned char name[BOOT_NAME_SIZE]; /* asciiz product name */
+    
+    unsigned char cmdline[BOOT_ARGS_SIZE];
+
+    unsigned id[8]; /* timestamp / checksum / sha1 / etc */
+};
+
+/*
+** +-----------------+ 
+** | boot header     | 1 page
+** +-----------------+
+** | kernel          | n pages  
+** +-----------------+
+** | ramdisk         | m pages  
+** +-----------------+
+** | second stage    | o pages
+** +-----------------+
+**
+** n = (kernel_size + page_size - 1) / page_size
+** m = (ramdisk_size + page_size - 1) / page_size
+** o = (second_size + page_size - 1) / page_size
+**
+** 0. all entities are page_size aligned in flash
+** 1. kernel and ramdisk are required (size != 0)
+** 2. second is optional (second_size == 0 -> no second)
+** 3. load each element (kernel, ramdisk, second) at
+**    the specified physical address (kernel_addr, etc)
+** 4. prepare tags at tag_addr.  kernel_args[] is
+**    appended to the kernel commandline in the tags.
+** 5. r0 = 0, r1 = MACHINE_TYPE, r2 = tags_addr
+** 6. if second_size != 0: jump to second_addr
+**    else: jump to kernel_addr
+*/
+
+#if 0
+typedef struct ptentry ptentry;
+
+struct ptentry {
+    char name[16];      /* asciiz partition name    */
+    unsigned start;     /* starting block number    */
+    unsigned length;    /* length in blocks         */
+    unsigned flags;     /* set to zero              */
+};
+
+/* MSM Partition Table ATAG
+**
+** length: 2 + 7 * n
+** atag:   0x4d534d70
+**         <ptentry> x n
+*/
+#endif
+void normal_mode(void);
+void recovery_mode(void);
+void fastboot_mode(void);
+void dloader_mode(void);
+void charge_mode(void);
+void vlx_mode(void);
+
+#endif
diff --git a/include/android/android_recovery.h b/include/android/android_recovery.h
new file mode 100644
index 0000000000..f76358fd08
--- /dev/null
+++ b/include/android/android_recovery.h
@@ -0,0 +1,77 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+ *   * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _BOOTLOADER_RECOVERY_H
+#define _BOOTLOADER_RECOVERY_H
+
+#define UPDATE_MAGIC       "MSM-RADIO-UPDATE"
+#define UPDATE_MAGIC_SIZE  16
+#define UPDATE_VERSION     0x00010000
+
+
+/* Recovery Message */
+struct recovery_message {
+	char command[32];
+	char status[32];
+	char recovery[1024];
+};
+
+
+struct update_header {
+	unsigned char MAGIC[UPDATE_MAGIC_SIZE];
+
+	unsigned version;
+	unsigned size;
+
+	unsigned image_offset;
+	unsigned image_length;
+
+	unsigned bitmap_width;
+	unsigned bitmap_height;
+	unsigned bitmap_bpp;
+
+	unsigned busy_bitmap_offset;
+	unsigned busy_bitmap_length;
+
+	unsigned fail_bitmap_offset;
+	unsigned fail_bitmap_length;
+};
+
+
+
+int get_recovery_message(struct recovery_message *out);
+int set_recovery_message(const struct recovery_message *in);
+
+int read_update_header_for_bootloader(struct update_header *header);
+int update_firmware_image (struct update_header *header, char *name);
+
+int recovery_init (void);
+
+extern unsigned boot_into_recovery;
+
+#endif
diff --git a/include/android/boot_mode.h b/include/android/boot_mode.h
new file mode 100644
index 0000000000..46277e1aca
--- /dev/null
+++ b/include/android/boot_mode.h
@@ -0,0 +1,41 @@
+#ifndef _BOOT_MODE_H_
+#define _BOOT_MODE_H_
+
+void normal_mode(void);
+void recovery_mode(void);
+void update_mode(void);
+void charge_mode(void);
+void dloader_mode(void);
+void fastboot_mode(void);
+void alarm_mode(void);
+void calibration_detect(int key);
+void engtest_mode(void);
+void sleep_mode(void);
+int is_bat_low(void);
+int alarm_flag_check(void);
+
+#define RECOVERY_MODE   0x77665502
+#define FASTBOOT_MODE   0x77665500
+#define NORMAL_MODE   0x77665503
+#define ALARM_MODE   0x77665504
+#define SLEEP_MODE   0x77665505
+
+#define BOOT_NORAML 0xf1
+#define BOOT_FASTBOOT 0xf2
+#define BOOT_RECOVERY 0xf3
+#define BOOT_CALIBRATE 0xf4
+#define BOOT_DLOADER 0xf5
+#define BOOT_CHARGE 0xf6
+#define BOOT_UPDATE 0xf7
+
+#define KEY_FASTBOOT 0x2f
+#define KEY_RECOVERY 0x3f
+#define KEY_ENGTEST 0x4f
+#define KEY_UPDATE 0x5f
+
+#define BACKLIGHT_ON 1
+#define BACKLIGHT_OFF 0
+
+extern unsigned int check_key_boot(uint32_t key);
+extern void vlx_nand_boot(char * kernel_pname, char * cmdline, int backlight_set);
+#endif
diff --git a/include/asm b/include/asm
new file mode 120000
index 0000000000..b37ecc899d
--- /dev/null
+++ b/include/asm
@@ -0,0 +1 @@
+../arch/arm/include/asm
\ No newline at end of file
diff --git a/include/autoconf.mk b/include/autoconf.mk
new file mode 100644
index 0000000000..df79076e11
--- /dev/null
+++ b/include/autoconf.mk
@@ -0,0 +1,171 @@
+CONFIG_TRAP_SIZE=0x00c0
+CONFIG_CMD_FAT=y
+CONFIG_SYS_NAND_U_BOOT_OFFS="(CONFIG_SPL_NAND_OFFS + CONFIG_SPL_MAX_SIZE + CONFIG_MTD_PTBL_SIZE)"
+CONFIG_ARMV7=y
+CONFIG_CMD_ITEST=y
+CONFIG_CMD_EDITENV=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SYS_MAX_NAND_DEVICE=y
+CONFIG_SYS_NAND_U_BOOT_DST="(CONFIG_SYS_TEXT_BASE - 64)"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NAND_RDA=y
+CONFIG_CMD_CRC32=y
+CONFIG_SYS_LONGHELP=y
+CONFIG_SPL_BOARD_INFO_ADDR="(CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CONFIG_SPL_BOARD_INFO_SIZE)"
+CONFIG_SYS_LOAD_ADDR="(PHYS_SDRAM_1 + 0x02000000)"
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_SPL_NAND_OFFS="(NAND_START_ADDR)"
+CONFIG_STACKSIZE="(256*1024)"
+CONFIG_BOOTDELAY=y
+CONFIG_SYS_NAND_BASE="(PHYS_SDRAM_1 + 0x00800000)"
+CONFIG_SYS_HELP_CMD_WIDTH=8
+CONFIG_NR_DRAM_BANKS=y
+CONFIG_EFI_PARTITION=y
+CONFIG_CMD_SAVES=y
+CONFIG_SYS_CBSIZE=1024
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_CMD_UBI=y
+CONFIG_BOOTM_LINUX=y
+CONFIG_USB_FASTBOOT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SYS_CACHELINE_SIZE=32
+CONFIG_MMC=y
+CONFIG_SPL_XMODEM_LOAD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_SDMMC_BOOT=y
+CONFIG_REVISION_TAG=y
+CONFIG_SPL_EMMC_SUPPORT=y
+CONFIG_CMD_MISC=y
+CONFIG_ZERO_BOOTDELAY_CHECK=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SYS_SRAM_BASE=0x00100000
+CONFIG_ENV_SIZE="(16 << 10)"
+CONFIG_CMD_HWFLOW=y
+CONFIG_MDCOM=y
+CONFIG_SYS_EMMC_U_BOOT_OFFS="(CONFIG_SPL_EMMC_OFFS + CONFIG_SPL_MAX_SIZE + CONFIG_MTD_PTBL_SIZE)"
+CONFIG_SYS_MALLOC_LEN="(0x10000 + 16*1024*1024)"
+CONFIG_INITRD_TAG=y
+CONFIG_SYS_HZ_CLOCK=2000000
+CONFIG_RDA_FACTORY=y
+CONFIG_SYS_TEXT_BASE=0x80008000
+CONFIG_SPL_CHECK_IMAGE=y
+CONFIG_SPL_TEXT_BASE=0x00100100
+CONFIG_MTD_PTBL_OFFS="(CONFIG_SPL_NAND_OFFS + CONFIG_SPL_MAX_SIZE)"
+CONFIG_MMC_DEV_NAME="mmc0"
+CONFIG_CMD_NAND=y
+CONFIG_USB_DEVICE=y
+CONFIG_BOOTARGS="mem="MK_STR(MEM_SIZE)"M console=ttyS0," MK_STR(CONFIG_BAUDRATE)  "root=/dev/ram rw rdinit=/init"
+CONFIG_CMD_NAND_YAFFS=y
+CONFIG_CMD_MEMORY=y
+CONFIG_SYS_MAXARGS=16
+CONFIG_UIMAGEHDR_SIZE=0x40
+CONFIG_CMD_RUN=y
+CONFIG_SYS_PBSIZE="(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)"
+CONFIG_BOARDDIR="board/rda/rda8810"
+CONFIG_SPL_STACK="CONFIG_SPL_BOARD_INFO_ADDR"
+CONFIG_UBOOT_VARIANT_DEBUG=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_DDR_CAL_VAL_SIZE=0x10
+CONFIG_SYS_NAND_U_BOOT_SIZE="(CONFIG_SYS_BOOTLOADER_MAX_SIZE - CONFIG_MTD_PTBL_SIZE - CONFIG_SPL_MAX_SIZE - CONFIG_SPL_NAND_OFFS)"
+CONFIG_CMD_EXT2=y
+CONFIG_BOOTCOMMAND="mux_config; mmc dev 0; ext2load mmc 0:1 ${script_addr} boot.scr && source ${script_addr};echo Running boot script failed;"
+CONFIG_CMD_MDCOM=y
+CONFIG_SPL_NAND_LOAD=y
+CONFIG_CRC32_VERIFY=y
+CONFIG_SYS_NAND_MAX_CHIPS=y
+CONFIG_SYS_BOOT_RAMDISK_HIGH=y
+CONFIG_SPL_NAND_SIMPLE=y
+CONFIG_ZLIB=y
+CONFIG_RDA_PRDINFO=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_BOOTD=y
+CONFIG_CMD_BOOTM=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_SYS_SRAM_SIZE=0x00010000
+CONFIG_MUSB_UDC=y
+CONFIG_SYS_BARGSIZE="CONFIG_SYS_CBSIZE"
+CONFIG_SYS_HZ=1000
+CONFIG_DOS_PARTITION=y
+CONFIG_GZIP=y
+CONFIG_BOOTSTAGE_USER_COUNT=20
+CONFIG_CMD_FPGA=y
+CONFIG_MIN_PARTITION_NUM=0
+CONFIG_SYS_BAUDRATE_TABLE="{ 9600, 38400, 115200, 921600 }"
+CONFIG_SYS_EMMC_U_BOOT_SIZE="(CONFIG_SYS_BOOTLOADER_MAX_SIZE - CONFIG_MTD_PTBL_SIZE - CONFIG_SPL_MAX_SIZE - CONFIG_SPL_EMMC_OFFS)"
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_IMAGE_SUPPORT=y
+CONFIG_MMC_DEV_NUM=0
+CONFIG_SYS_HUSH_PARSER=y
+CONFIG_SIGNATURE_CHECK_IMAGE=y
+CONFIG_MX_CYCLIC=y
+CONFIG_SYS_SDRAM_BASE="(PHYS_SDRAM_1)"
+CONFIG_SPL_EMMC_OFFS=0x20000
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SYS_PROMPT_HUSH_PS2="> "
+CONFIG_SYS_EMMC_U_BOOT_DST="(CONFIG_SYS_TEXT_BASE - 64)"
+CONFIG_CMD_ECHO=y
+CONFIG_GENERIC_MMC=y
+CONFIG_MTD_PTBL_SIZE="((SPL_APPENDING_TO-CONFIG_SPL_MAX_SIZE/1024)*1024)"
+CONFIG_CMD_PRDINFO=y
+CONFIG_USE_ARCH_MEMCPY=y
+CONFIG_RDA_MMC=y
+CONFIG_EXTRA_ENV_SETTINGS="script_addr=81000000\0modem_addr=82000000\0factorydata_addr=83000000\0kernel_addr=84000000\0initrd_addr=85000000\0boot_device=mmc\0"
+CONFIG_SPL_LOAD_ADDRESS="(CONFIG_SYS_SRAM_BASE + CONFIG_TRAP_SIZE)"
+CONFIG_CMD_FASTBOOT=y
+CONFIG_SYS_INIT_SP_ADDR="(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)"
+CONFIG_CMD_ASKENV=y
+CONFIG_BAUDRATE=921600
+CONFIG_SYS_XMODEM_U_BOOT_DST="(CONFIG_SYS_TEXT_BASE - 64)"
+CONFIG_CMDLINE_TAG=y
+CONFIG_SPL_NAND_MIDDLE_DATA_BUFFER="(PHYS_SDRAM_1 + 0x01000000)"
+CONFIG_MAX_PARTITION_NUM=20
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_DDR_CAL_SEC_OFFS="CONFIG_SPL_MAX_SIZE - CONFIG_DDR_CAL_VAL_SIZE - 0x100"
+CONFIG_CMD_IMPORTENV=y
+CONFIG_CMD_EXPORTENV=y
+CONFIG_PARTITIONS=y
+CONFIG_SYS_MEMTEST_END="(PHYS_SDRAM_1 + 0x00800000 + 16*1024*1024)"
+CONFIG_CMD_UBIFS=y
+CONFIG_EXTFS_USER_IMAGES=y
+CONFIG_SYS_EMMC_U_BOOT_START="CONFIG_SYS_TEXT_BASE"
+CONFIG_USBD_HS=y
+CONFIG_SYS_NO_FLASH=y
+CONFIG_SYS_DEF_EEPROM_ADDR=0
+CONFIG_SYS_XMODEM_U_BOOT_START="CONFIG_SYS_TEXT_BASE"
+CONFIG_SPL_MAX_SIZE=49152
+CONFIG_MACH_TYPE="(5002)"
+CONFIG_RDA_USB_SERIAL=y
+CONFIG_SPL_THUMB_BUILD=y
+CONFIG_SPL=y
+CONFIG_MTD_DEVICE=y
+CONFIG_CMD_SOURCE=y
+CONFIG_SYS_PROMPT="RDA > "
+CONFIG_EXTFS_SYSTEM_IMAGE=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_USB_RDA=y
+CONFIG_NAND_RDA_V1=y
+CONFIG_SETUP_MEMORY_TAGS=y
+CONFIG_CMD_PDL2=y
+CONFIG_SYS_MEMTEST_START="(PHYS_SDRAM_1 + 0x00800000)"
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADS=y
+CONFIG_CMD_IMI=y
+CONFIG_RDA_MUX_CONFIG=y
+CONFIG_MUSB_DMA=y
+CONFIG_LMB=y
+CONFIG_ARM=y
+CONFIG_RBTREE=y
+CONFIG_CMD_DIAG=y
+CONFIG_SYS_BOOTLOADER_MAX_SIZE="(1024*1024)"
+CONFIG_SYS_NAND_PAGE_2K=y
+CONFIG_SPL_CODE_MAX_SIZE=48880
+CONFIG_LZO=y
+CONFIG_SYS_NAND_LARGEPAGE=y
+CONFIG_CMD_MMC=y
+CONFIG_SPL_BOARD_INFO_SIZE=512
+CONFIG_SYS_NAND_U_BOOT_START="CONFIG_SYS_TEXT_BASE"
+CONFIG_MACH_RDA8810=y
+CONFIG_SPL_EMMC_LOAD=y
diff --git a/include/autoconf.mk.dep b/include/autoconf.mk.dep
new file mode 100644
index 0000000000..b326967b26
--- /dev/null
+++ b/include/autoconf.mk.dep
@@ -0,0 +1,55 @@
+include/autoconf.mk: include/common.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/config.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/config_cmd_defaults.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/config_defaults.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/configs/rda8810.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/configs/rda_config_defaults.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/rda/tgt_ap_board_config.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/rda/tgt_ap_clock_config.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/rda/ddr_timing/8810p_16x2_260m_ddr2_u08.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/config_cmd_default.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/asm/arch/mtdparts_def.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/rda/tgt_ap_flash_parts.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/asm/config.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/asm-offsets.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/linux/bitops.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/asm/types.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/asm/bitops.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/asm/proc/system.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/linux/config.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/linux/types.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/linux/posix_types.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/linux/stddef.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/asm/posix_types.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/linux/string.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/asm/string.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/asm/ptrace.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/asm/proc/ptrace.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/include/stdarg.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/errno.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/asm-generic/errno.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/part.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/ide.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/part_efi.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/flash.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/image.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/compiler.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/include/stddef.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/asm/byteorder.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/linux/byteorder/little_endian.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/linux/byteorder/swab.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/linux/byteorder/generic.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/lmb.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/asm/u-boot.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/command.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/asm/global_data.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/asm/mach-types.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/asm/setup.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/asm/u-boot-arm.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/vsprintf.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/u-boot/crc.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/net.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/asm/cache.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/asm/system.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/bootstage.h \
+ /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/include/environment.h
diff --git a/include/common.h b/include/common.h
index 4b5841ef47..c679296877 100644
--- a/include/common.h
+++ b/include/common.h
@@ -112,6 +112,7 @@ typedef volatile unsigned char	vu_char;
 #include <asm/arch/hardware.h>
 #endif
 
+#include <errno.h>
 #include <part.h>
 #include <flash.h>
 #include <image.h>
@@ -222,6 +223,31 @@ typedef void (interrupt_handler_t)(void *);
 #define MIN(x, y)  min(x, y)
 #define MAX(x, y)  max(x, y)
 
+/*
+ * Return the absolute value of a number.
+ *
+ * This handles unsigned and signed longs, ints, shorts and chars.  For all
+ * input types abs() returns a signed long.
+ *
+ * For 64-bit types, use abs64()
+ */
+#define abs(x) ({						\
+		long ret;					\
+		if (sizeof(x) == sizeof(long)) {		\
+			long __x = (x);				\
+			ret = (__x < 0) ? -__x : __x;		\
+		} else {					\
+			int __x = (x);				\
+			ret = (__x < 0) ? -__x : __x;		\
+		}						\
+		ret;						\
+	})
+
+#define abs64(x) ({				\
+		s64 __x = (x);			\
+		(__x < 0) ? -__x : __x;		\
+	})
+
 #if defined(CONFIG_ENV_IS_EMBEDDED)
 #define TOTAL_MALLOC_LEN	CONFIG_SYS_MALLOC_LEN
 #elif ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \
@@ -704,13 +730,6 @@ int gunzip(void *, int, unsigned char *, unsigned long *);
 int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp,
 						int stoponerr, int offset);
 
-/* lib/net_utils.c */
-#include <net.h>
-static inline IPaddr_t getenv_IPaddr (char *var)
-{
-	return (string_to_ip(getenv(var)));
-}
-
 /* lib/qsort.c */
 void qsort(void *base, size_t nmemb, size_t size,
 	   int(*compar)(const void *, const void *));
@@ -779,6 +798,13 @@ void	fputc(int file, const char c);
 int	ftstc(int file);
 int	fgetc(int file);
 
+/* lib/net_utils.c */
+#include <net.h>
+static inline IPaddr_t getenv_IPaddr(char *var)
+{
+	return string_to_ip(getenv(var));
+}
+
 /*
  * CONSOLE multiplexing.
  */
@@ -794,6 +820,10 @@ int	pcmcia_init (void);
 
 #include <bootstage.h>
 
+#ifdef CONFIG_SHOW_ACTIVITY
+void show_activity(int arg);
+#endif
+
 /* Multicore arch functions */
 #ifdef CONFIG_MP
 int cpu_status(int nr);
diff --git a/include/config.h b/include/config.h
new file mode 100644
index 0000000000..5d9cc1dded
--- /dev/null
+++ b/include/config.h
@@ -0,0 +1,6 @@
+/* Automatically generated - do not edit */
+#define CONFIG_BOARDDIR board/rda/rda8810
+#include <config_cmd_defaults.h>
+#include <config_defaults.h>
+#include <configs/rda8810.h>
+#include <asm/config.h>
diff --git a/include/config.mk b/include/config.mk
new file mode 100644
index 0000000000..659146438c
--- /dev/null
+++ b/include/config.mk
@@ -0,0 +1,5 @@
+ARCH   = arm
+CPU    = armv7
+BOARD  = rda8810
+VENDOR = rda
+SOC    = rda
diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h
index 2c6b8295fb..55f4f7a30b 100644
--- a/include/config_cmd_all.h
+++ b/include/config_cmd_all.h
@@ -15,7 +15,6 @@
 
 #define CONFIG_CMD_AMBAPP	/* AMBA Plug & Play Bus print utility */
 #define CONFIG_CMD_ASKENV	/* ask for env variable		*/
-#define CONFIG_CMD_AT91_SPIMUX	/* AT91 MMC/SPI Mux Support     */
 #define CONFIG_CMD_BDI		/* bdinfo			*/
 #define CONFIG_CMD_BEDBUG	/* Include BedBug Debugger	*/
 #define CONFIG_CMD_BMP		/* BMP support			*/
diff --git a/include/configs/HWW1U1A.h b/include/configs/HWW1U1A.h
index 01597b965b..f08d78b91c 100644
--- a/include/configs/HWW1U1A.h
+++ b/include/configs/HWW1U1A.h
@@ -422,7 +422,7 @@ const char *hww1u1a_get_ps1(void);
 #define CONFIG_MD5
 #define CONFIG_SHA1
 #define CONFIG_CMD_MD5SUM
-#define CONFIG_CMD_SHA1
+#define CONFIG_CMD_SHA1SUM
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_SETEXPR
 
diff --git a/include/configs/MBX.h b/include/configs/MBX.h
index cb5b023b58..79780bd1a3 100644
--- a/include/configs/MBX.h
+++ b/include/configs/MBX.h
@@ -87,7 +87,6 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_NET
-#define CONFIG_CMD_DFL
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_PCMCIA
 #define CONFIG_CMD_IDE
diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h
index 619a8002a7..84ba78f9e9 100644
--- a/include/configs/MigoR.h
+++ b/include/configs/MigoR.h
@@ -38,7 +38,6 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_NFS
-#define CONFIG_CMD_DFL
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_SAVEENV
 
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index f2d33668d8..08fc4e8427 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -181,7 +181,7 @@
 
 /* DDR Setup */
 #define CONFIG_FSL_DDR3
-#define CONFIG_DDR_RAW_TIMING
+#define CONFIG_SYS_DDR_RAW_TIMING
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_SPD_BUS_NUM		1
 #define SPD_EEPROM_ADDRESS		0x52
diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h
index e057b1f945..e632d1bd37 100644
--- a/include/configs/P1023RDS.h
+++ b/include/configs/P1023RDS.h
@@ -310,9 +310,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_OF_BOARD_SETUP
 #define CONFIG_OF_STDOUT_VIA_ALIAS
 
-#define CONFIG_SYS_64BIT_VSPRINTF
-#define CONFIG_SYS_64BIT_STRTOUL
-
 /* new uImage format support */
 #define CONFIG_FIT
 #define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
diff --git a/include/configs/P2020COME.h b/include/configs/P2020COME.h
index 365322c6a5..28122ecc11 100644
--- a/include/configs/P2020COME.h
+++ b/include/configs/P2020COME.h
@@ -416,8 +416,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #endif
 
 /* Misc Extra Settings */
-#define CONFIG_SYS_64BIT_VSPRINTF	1
-#define CONFIG_SYS_64BIT_STRTOUL	1
 #define CONFIG_CMD_DHCP			1
 
 #define CONFIG_CMD_DATE			1
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index da98f8f027..fe39d4e6e6 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -96,6 +96,11 @@
 	#define CONFIG_SYS_MMC_ENV_DEV          0
 	#define CONFIG_ENV_SIZE			0x2000
 	#define CONFIG_ENV_OFFSET		(512 * 1097)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET		(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #else
 	#define CONFIG_ENV_IS_IN_FLASH
 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE \
@@ -186,10 +191,11 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
 #endif
 
-#define CONFIG_SYS_BR0_PRELIM \
+#define CONFIG_SYS_FLASH_BR_PRELIM \
 		(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
-				| OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
+#define CONFIG_SYS_FLASH_OR_PRELIM \
+		((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
+		 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 
 #define CONFIG_FSL_CPLD
 #define CPLD_BASE		0xffdf0000	/* CPLD registers */
@@ -221,6 +227,53 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_RAMBOOT
 #endif
 
+#define CONFIG_NAND_FSL_ELBC
+/* Nand Flash */
+#ifdef CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BASE		0xffa00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+
+#define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+			       | BR_PS_8	       /* Port Size = 8 bit */ \
+			       | BR_MS_FCM	       /* MSEL = FCM */ \
+			       | BR_V)		       /* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000	      /* length 256K */ \
+			       | OR_FCM_PGS	       /* Large Page*/ \
+			       | OR_FCM_CSCT \
+			       | OR_FCM_CST \
+			       | OR_FCM_CHT \
+			       | OR_FCM_SCY_1 \
+			       | OR_FCM_TRLX \
+			       | OR_FCM_EHTR)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#endif /* CONFIG_NAND_FSL_ELBC */
+
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
diff --git a/include/configs/adp-ag102.h b/include/configs/adp-ag102.h
new file mode 100644
index 0000000000..a4628e4343
--- /dev/null
+++ b/include/configs/adp-ag102.h
@@ -0,0 +1,375 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/ag102.h>
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_ADP_AG102
+
+#define CONFIG_USE_INTERRUPT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_MEM_REMAP
+#endif
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE	0x04200000
+#else
+#define CONFIG_SYS_TEXT_BASE	0x00000000
+#endif
+
+/*
+ * Timer
+ */
+
+/*
+ * According to the discussion in u-boot mailing list before,
+ * CONFIG_SYS_HZ at 1000 is mandatory.
+ */
+#define CONFIG_SYS_HZ		1000
+#define CONFIG_SYS_CLK_FREQ	(66000000 * 2)
+#define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ
+
+/*
+ * Use Externel CLOCK or PCLK
+ */
+#undef CONFIG_FTRTC010_EXTCLK
+
+#ifndef CONFIG_FTRTC010_EXTCLK
+#define CONFIG_FTRTC010_PCLK
+#endif
+
+#ifdef CONFIG_FTRTC010_EXTCLK
+#define TIMER_CLOCK	32768			/* CONFIG_FTRTC010_EXTCLK */
+#else
+#define TIMER_CLOCK	CONFIG_SYS_HZ		/* CONFIG_FTRTC010_PCLK */
+#endif
+
+#define TIMER_LOAD_VAL	0xffffffff
+
+/*
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*
+ * Real Time Clock Divider
+ * RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+ */
+#define OSC_5MHZ			(5*1000000)
+#define OSC_CLK				(2*OSC_5MHZ)
+#define RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+
+/*
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART */
+#define CONFIG_BAUDRATE			38400
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_01_BASE
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK		33000000	/* AG102 */
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Ethernet
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_MAX_ADDR	32	/* this comes from <linux/phy.h> */
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_FTGMAC100
+#define CONFIG_FTGMAC100_EGIGA
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * SD (MMC) controller
+ */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FTSDC010
+#define CONFIG_FTSDC010_NUMBER		1
+#define CONFIG_FTSDC010_SDIO
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+
+/*
+ * PCI
+ */
+#define CONFIG_PCI
+#define CONFIG_FTPCI100
+#define CONFIG_FTPCI100_MEM_BASE        0xa0000000
+#define CONFIG_FTPCI100_IO_SIZE         FTPCI100_BASE_IO_SIZE(256) /* 256M */
+#define CONFIG_FTPCI100_MEM_SIZE        FTPCI100_MEM_SIZE(128)  /* 128M */
+#define CONFIG_FTPCI100_MEM_BASE_SIZE1  0x50
+
+#define CONFIG_PCI_MEM_BUS	0xa0000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x01000000		/* 256M */
+
+#define CONFIG_PCI_IO_BUS	0x90000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x00100000		/* 1M */
+
+/*
+ * USB
+ */
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+#if defined(CONFIG_FTPCI100)
+#define __io /* enable outl & inl */
+#define CONFIG_CMD_USB
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS      5
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_PCI_EHCI_DEVICE 0
+#define CONFIG_USB_EHCI_PCI
+#define CONFIG_PREBOOT                          "usb start;"
+#endif /* #if defiend(CONFIG_FTPCI100) */
+#endif /* #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) */
+
+/*
+ * IDE/ATA stuff
+ */
+#define __io
+#define CONFIG_IDE_AHB
+#define CONFIG_IDE_FTIDE020
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT	1	/* preinit for ide		*/
+
+/* max: 2 IDE busses */
+#define CONFIG_SYS_IDE_MAXBUS		1	/* origin: 2 */
+/* max: 2 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* origin: (MAXBUS * 2) */
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_FTIDE020S_BASE
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE1_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* for data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* for normal regs access */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* for alternate regs */
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"NDS32 # "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS	16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+
+/*
+ * size in bytes reserved for initial data
+*/
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * AHB Controller configuration
+ */
+#define CONFIG_FTAHBC020S
+
+#ifdef CONFIG_FTAHBC020S
+#include <faraday/ftahbc020s.h>
+
+/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE	0x100
+
+/*
+ * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
+ * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
+ * in C language.
+ */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
+	(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
+					 FTAHBC020S_SLAVE_BSR_SIZE(0xb))
+#endif
+
+/*
+ * Watchdog
+ */
+#define CONFIG_FTWDT010_WATCHDOG
+
+/*
+ * PCU Power Control Unit configuration
+ */
+#define CONFIG_ANDES_PCU
+
+#ifdef CONFIG_ANDES_PCU
+#include <andestech/andes_pcu.h>
+
+#endif
+
+/*
+ * DDR DRAM controller configuration
+ */
+#define CONFIG_DWCDDR21MCTL
+
+#ifdef CONFIG_DWCDDR21MCTL
+#include <synopsys/dwcddr21mctl.h>
+/* DCR:
+ *   2GB: 0x000025d2, 2GB (1Gb x8 2 ranks) Micron/innoDisk/Transcend
+ *   1GB: 0x000021d2, 1GB (1Gb x8 1 rank) Micron/Transcend/innoDisk
+ * 512MB: 0x000025cc, Micron 512MB (512Mb x16 2 ranks)
+ * 512MB: 0x000021ca, Trenscend/innoDisk 512MB (512Mb x8 1 rank)
+ * 256MB: 0x000020d4, Micron 256MB (1Gb x16 1 ranks)
+ */
+#define CONFIG_SYS_DWCDDR21MCTL_CCR	0x00020004
+#define CONFIG_SYS_DWCDDR21MCTL_CCR2	(DWCDDR21MCTL_CCR_DTT(0x1)	| \
+					DWCDDR21MCTL_CCR_DFTLM(0x4)	| \
+					DWCDDR21MCTL_CCR_HOSTEN(0x1))
+
+/* 0x04: 0x000020d4 */
+#define CONFIG_SYS_DWCDDR21MCTL_DCR	0x000020ca
+
+/* 0x08: 0x0000000f */
+#define CONFIG_SYS_DWCDDR21MCTL_IOCR	0x0000000f
+
+/* 0x10: 0x00034812 */
+#define CONFIG_SYS_DWCDDR21MCTL_DRR	(DWCDDR21MCTL_DRR_TRFC(0x12)	| \
+					DWCDDR21MCTL_DRR_TRFPRD(0x0348))
+/* 0x24 */
+#define CONFIG_SYS_DWCDDR21MCTL_DLLCR0	DWCDDR21MCTL_DLLCR_PHASE(0x0)
+
+/* 0x4c: 0x00000040 */
+#define CONFIG_SYS_DWCDDR21MCTL_RSLR0	0x00000040
+
+/* 0x5c: 0x000055CF */
+#define CONFIG_SYS_DWCDDR21MCTL_RDGR0	0x000055cf
+
+/* 0xa4: 0x00100000 */
+#define CONFIG_SYS_DWCDDR21MCTL_DTAR	(DWCDDR21MCTL_DTAR_DTBANK(0x0)	| \
+					DWCDDR21MCTL_DTAR_DTROW(0x0100)	| \
+					DWCDDR21MCTL_DTAR_DTCOL(0x0))
+/* 0x1f0: 0x00000852 */
+#define CONFIG_SYS_DWCDDR21MCTL_MR	(DWCDDR21MCTL_MR_WR(0x4)	| \
+					DWCDDR21MCTL_MR_CL(0x5)		| \
+					DWCDDR21MCTL_MR_BL(0x2))
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
+#define PHYS_SDRAM_0		0x00000000	/* SDRAM Bank #1 */
+#if defined(CONFIG_MEM_REMAP)
+#define PHYS_SDRAM_0_AT_INIT	0x80000000	/* SDRAM Bank #1 before remap*/
+#endif
+#else	/* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
+#define PHYS_SDRAM_0		0x80000000	/* SDRAM Bank #1 */
+#endif
+
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_0_SIZE	0x10000000	/* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0
+
+#ifdef CONFIG_MEM_REMAP
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
+					GENERATED_GBL_DATA_SIZE)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+					GENERATED_GBL_DATA_SIZE)
+#endif /* CONFIG_MEM_REMAP */
+
+/*
+ * Load address and memory test area should agree with
+ * board/faraday/a320/config.mk
+ * Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x0CF00000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + 0x03F00000)
+
+/*
+ * Static memory controller configuration
+ */
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			4096
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index b0dd2f0af6..827a6159f2 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -146,7 +146,7 @@
 #define CONFIG_CMD_MMC		/* MMC support			*/
 #define CONFIG_CMD_NAND		/* NAND support			*/
 #define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
+#undef CONFIG_CMD_PING
 
 #undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
 #undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
@@ -174,7 +174,6 @@
 
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
 							/* NAND devices */
-#define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
 
 #define CONFIG_JFFS2_NAND
 /* nand device jffs2 lives on */
@@ -326,7 +325,7 @@
 #define CONFIG_SPL
 #define CONFIG_SPL_NAND_SIMPLE
 #define CONFIG_SPL_TEXT_BASE		0x40200800
-#define CONFIG_SPL_MAX_SIZE		(45 * 1024)
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
 
 #define CONFIG_SPL_BSS_START_ADDR	0x80000000
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index b5f75d1e8d..6766ee23d3 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -145,7 +145,7 @@
 #define CONFIG_CMD_MMC		/* MMC support			*/
 #define CONFIG_CMD_NAND		/* NAND support			*/
 #define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
+#undef CONFIG_CMD_PING
 
 #undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
 #undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
@@ -173,8 +173,6 @@
 
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
 							/* NAND devices */
-#define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
-
 #define CONFIG_JFFS2_NAND
 /* nand device jffs2 lives on */
 #define CONFIG_JFFS2_DEV		"nand0"
@@ -326,7 +324,7 @@
 #define CONFIG_SPL
 #define CONFIG_SPL_NAND_SIMPLE
 #define CONFIG_SPL_TEXT_BASE		0x40200800
-#define CONFIG_SPL_MAX_SIZE		(45 * 1024)
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
 
 #define CONFIG_SPL_BSS_START_ADDR	0x80000000
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index 83992461f9..f424e5a5bd 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -283,8 +283,6 @@
 #define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
 #define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PD15
 #define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PA22
-
-#define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
 #endif
 
 /* Ethernet */
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index 6a02188108..159857d32f 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -107,7 +107,6 @@
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_IMI
 #undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_AUTOSCRIPT
 #undef CONFIG_CMD_LOADS
 
 #define CONFIG_CMD_PING
diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h
index 99856ebfdf..71faf1cc9f 100644
--- a/include/configs/cam_enc_4xx.h
+++ b/include/configs/cam_enc_4xx.h
@@ -37,7 +37,7 @@
 
 #define CONFIG_HOSTNAME			cam_enc_4xx
 
-#define	BOARD_LATE_INIT
+#define	CONFIG_BOARD_LATE_INIT
 #define CONFIG_CAM_ENC_LED_MASK		0x0fc00000
 
 /* Memory Info */
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index fe91c10409..b28bd8e313 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -156,6 +156,7 @@
 #define CONFIG_DRIVER_OMAP34XX_I2C
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_I2C_MULTI_BUS
 
 /*
  * TWL4030
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 77dd0a2d1e..8ed37a58c2 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -33,6 +33,15 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
 #endif
 
+#ifdef CONFIG_SRIOBOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIOBOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
 /* High Level Configuration Options */
 #define CONFIG_BOOKE
 #define CONFIG_E500			/* BOOKE e500 family */
@@ -68,7 +77,9 @@
 #define CONFIG_ENV_OVERWRITE
 
 #ifdef CONFIG_SYS_NO_FLASH
+#ifndef CONFIG_SRIOBOOT_SLAVE
 #define CONFIG_ENV_IS_NOWHERE
+#endif
 #else
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
@@ -97,6 +108,12 @@
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
 #define CONFIG_ENV_OFFSET		(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIOBOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
 #else
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
@@ -373,6 +390,54 @@
 #define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
 
 /*
+ * SRIOBOOT - MASTER
+ */
+#ifdef CONFIG_SRIOBOOT_MASTER
+/* master port for srioboot*/
+#define CONFIG_SRIOBOOT_MASTER_PORT 0
+/* #define CONFIG_SRIOBOOT_MASTER_PORT 1 */
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 0xfef080000ull
+#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 0xfff80000ull
+#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE 0x80000	/* 512K */
+#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 0xfef080000ull
+#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff80000ull
+/*
+ * for slave UCODE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS 0xfef020000ull
+#define CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS 0x3ffe00000ull
+#define CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE 0x10000	/* 64K */
+/*
+ * for slave ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS 0xfef060000ull
+#define CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS 0x3ffe20000ull
+#define CONFIG_SRIOBOOT_SLAVE_ENV_SIZE 0x20000	/* 128K */
+/* slave core release by master*/
+#define CONFIG_SRIOBOOT_SLAVE_HOLDOFF
+#define CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK 0x00000001 /* release core 0 */
+#endif
+
+/*
+ * SRIOBOOT - SLAVE
+ */
+#ifdef CONFIG_SRIOBOOT_SLAVE
+/* slave port for srioboot */
+#define CONFIG_SRIOBOOT_SLAVE_PORT0
+/* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */
+#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR)
+#endif
+
+/*
  * eSPI - Enhanced SPI
  */
 #define CONFIG_FSL_ESPI
@@ -492,6 +557,16 @@
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIOBOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO outbound window->master inbound window->master LAW->
+ * the ucode address in master's NOR flash.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xFFE00000
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEF000000
diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h
index 4532e4f4fd..781878ef39 100644
--- a/include/configs/da830evm.h
+++ b/include/configs/da830evm.h
@@ -111,7 +111,6 @@
 #define CONFIG_SYS_NAND_CS		3
 #define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 #define CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
 #define CONFIG_SYS_CLE_MASK		0x10
 #define CONFIG_SYS_ALE_MASK		0x8
 #define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
diff --git a/include/configs/debris.h b/include/configs/debris.h
index 60c7c4058f..303630d7d7 100644
--- a/include/configs/debris.h
+++ b/include/configs/debris.h
@@ -148,7 +148,7 @@
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_KGBD
+#define CONFIG_CMD_KGDB
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SAVES
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
new file mode 100644
index 0000000000..9f15ffb0fd
--- /dev/null
+++ b/include/configs/devkit3250.h
@@ -0,0 +1,117 @@
+/*
+ * Embest/Timll DevKit3250 board configuration file
+ *
+ * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __CONFIG_DEVKIT3250_H__
+#define __CONFIG_DEVKIT3250_H__
+
+/* SoC and board defines */
+#include <asm/sizes.h>
+#include <asm/arch/cpu.h>
+
+/*
+ * Define DevKit3250 machine type by hand until it lands in mach-types
+ */
+#define MACH_TYPE_DEVKIT3250		3697
+#define CONFIG_MACH_TYPE		MACH_TYPE_DEVKIT3250
+
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/*
+ * Memory configurations
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_STACKSIZE		SZ_32K
+#define CONFIG_SYS_MALLOC_LEN		SZ_1M
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+#define CONFIG_SYS_SDRAM_BASE		EMC_DYCS0_BASE
+#define CONFIG_SYS_SDRAM_SIZE		SZ_64M
+#define CONFIG_SYS_TEXT_BASE		0x83FA0000
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + SZ_32K)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - SZ_1M)
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_32K)
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_4K \
+					 - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_SYS_LPC32XX_UART		2   /* UART2 */
+#define CONFIG_BAUDRATE			115200
+
+/*
+ * NOR Flash
+ */
+#define CONFIG_CMD_FLASH
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	71
+#define CONFIG_SYS_FLASH_BASE		EMC_CS0_BASE
+#define CONFIG_SYS_FLASH_SIZE		SZ_4M
+#define CONFIG_SYS_FLASH_CFI
+
+/*
+ * U-Boot General Configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_PBSIZE		\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			SZ_128K
+
+/*
+ * U-Boot Commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
+
+/*
+ * Boot Linux
+ */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_BOOTDELAY		3
+
+#define CONFIG_BOOTFILE			"uImage"
+#define CONFIG_BOOTARGS			"console=ttyS2,115200n8"
+#define CONFIG_LOADADDR			0x80008000
+
+/*
+ * Include SoC specific configuration
+ */
+#include <asm/arch/config.h>
+
+#endif  /* __CONFIG_DEVKIT3250_H__*/
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index eb7c376780..248a5b2fa3 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -324,7 +324,7 @@
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
 
 #define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
-#define CONFIG_SPL_MAX_SIZE		0xB400  /* 45 K */
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
 
 #define CONFIG_SPL_BSS_START_ADDR       0x80000500 /* leave space for bootargs*/
diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h
index d5173349c4..1f660235f0 100644
--- a/include/configs/digsy_mtc.h
+++ b/include/configs/digsy_mtc.h
@@ -119,7 +119,6 @@
 #ifdef CONFIG_VIDEO
 #define CONFIG_CMD_BMP
 #endif
-#define CONFIG_CMD_DFL
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DHCP
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index 146819712d..2cd20279be 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -34,10 +34,12 @@
  * Include common defines/options for all AMCC eval boards
  */
 #define CONFIG_HOSTNAME		dlvsion-10g
-#define CONFIG_IDENT_STRING	" dlvision-10g 0.02"
+#define CONFIG_IDENT_STRING	" dlvision-10g 0.03"
 #include "amcc-common.h"
 
-#define CONFIG_BOARD_EARLY_INIT_F	/* call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
 #define CONFIG_LAST_STAGE_INIT
 
 #define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
@@ -80,6 +82,7 @@
  * Commands additional to the ones defined in amcc-common.h
  */
 #define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DTT
 #undef CONFIG_CMD_EEPROM
 
 /*
@@ -115,7 +118,7 @@
 
 /* Temp sensor/hwmon/dtt */
 #define CONFIG_DTT_LM63		1	/* National LM63	*/
-#define CONFIG_DTT_SENSORS	{ 0x4c, 0x4e }	/* Sensor addresses	*/
+#define CONFIG_DTT_SENSORS	{ 0x4c, 0x4e, 0x18 } /* Sensor addresses */
 #define CONFIG_DTT_PWM_LOOKUPTABLE	\
 		{ { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\
 		  { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h
index 0f2f9a2743..76f9eeaed8 100644
--- a/include/configs/dreamplug.h
+++ b/include/configs/dreamplug.h
@@ -148,4 +148,6 @@
  */
 #define CONFIG_DISPLAY_CPUINFO
 
+#define CONFIG_OF_LIBFDT
+
 #endif /* _CONFIG_DREAMPLUG_H */
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index e059b30826..88b085d4a7 100644
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
@@ -31,7 +31,7 @@
 #define	CONFIG_SYS_USE_NAND
 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
 #define CONFIG_BOARD_EARLY_INIT_F
-#define BOARD_LATE_INIT
+#define CONFIG_BOARD_LATE_INIT
 #define CONFIG_VIDEO
 #define CONFIG_PREBOOT
 
@@ -203,7 +203,6 @@
 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 #define	CONFIG_SYS_NAND_USE_FLASH_BBT
 #define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
-#define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
 #endif
 
 /* SPI Flash */
diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h
index eb05e2a0b0..21c471adf6 100644
--- a/include/configs/eb_cpux9k2.h
+++ b/include/configs/eb_cpux9k2.h
@@ -288,8 +288,6 @@
 #define CONFIG_SYS_NAND_BASE		0x40000000
 #define CONFIG_SYS_NAND_DBW_8		1
 
-#define CONFIG_SYS_64BIT_VSPRINTF	1
-
 /* Status LED's */
 
 #define CONFIG_STATUS_LED		1
diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h
index f19360d501..221d3e055d 100644
--- a/include/configs/ep8260.h
+++ b/include/configs/ep8260.h
@@ -325,7 +325,6 @@
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_SNTP
 
-#undef CONFIG_CMD_DCR
 #undef CONFIG_CMD_XIMG
 
 /* Where do the internal registers live? */
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index f046a587be..dd7c73f3c7 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -48,8 +48,6 @@
 /* Set TEXT at the beginning of the NOR flash */
 #define CONFIG_SYS_TEXT_BASE	0xA0000000
 
-#define CONFIG_SYS_64BIT_VSPRINTF
-
 /* This is required to setup the ESDC controller */
 #define CONFIG_BOARD_EARLY_INIT_F
 
diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h
index 3c59ff4922..9efbb8e34c 100644
--- a/include/configs/gdppc440etx.h
+++ b/include/configs/gdppc440etx.h
@@ -50,6 +50,10 @@
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* call board_early_init_f*/
 #define CONFIG_MISC_INIT_R		1	/* call misc_init_r()     */
 
+#undef CONFIG_ZERO_BOOTDELAY_CHECK     /* ignore keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED          /* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h
index 462cc7e16c..efff3098a5 100644
--- a/include/configs/gplugd.h
+++ b/include/configs/gplugd.h
@@ -70,7 +70,6 @@
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_I2C
-#define CONFIG_CMD_AUTOSCRIPT
 #undef CONFIG_CMD_FPGA
 #define CONFIG_CMD_USB
 #define CONFIG_CMD_EXT2
diff --git a/include/configs/hawkboard.h b/include/configs/hawkboard.h
index 0859371387..6d2d4fb91d 100644
--- a/include/configs/hawkboard.h
+++ b/include/configs/hawkboard.h
@@ -127,7 +127,6 @@
 #define CFG_DAVINCI_STD_NAND_LAYOUT
 #define CONFIG_SYS_NAND_CS		3
 #define CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
 /* Max number of NAND devices */
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BASE_LIST	{ 0x62000000, }
diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h
new file mode 100644
index 0000000000..85856f290e
--- /dev/null
+++ b/include/configs/ib62x0.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright (C) 2011-2012
+ * Gerald Kerma <dreagle@doukki.net>
+ * Luka Perkov <uboot@lukaperkov.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _CONFIG_IB62x0_H
+#define _CONFIG_IB62x0_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	" RaidSonic ICY BOX IB-NAS62x0"
+
+/*
+ * High level configuration options
+ */
+#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
+#define CONFIG_KIRKWOOD			/* SOC Family Name */
+#define CONFIG_KW88F6281		/* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Machine type
+ */
+#define CONFIG_MACH_TYPE	MACH_TYPE_NAS6210
+
+/*
+ * Compression configuration
+ */
+#define CONFIG_BZIP2
+#define CONFIG_LZMA
+#define CONFIG_LZO
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* declare no flash (NOR/SPI) */
+#define CONFIG_SYS_MVFS
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT	"ib62x0 => "
+
+/*
+ * Environment variables configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#define CONFIG_ENV_SIZE		0x20000
+#define CONFIG_ENV_OFFSET	0x80000
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND \
+	"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; "	\
+	"ubi part root; "						\
+	"ubifsmount root; "						\
+	"ubifsload 0x800000 ${kernel}; "				\
+	"ubifsload 0x1100000 ${initrd}; "				\
+	"bootm 0x800000 0x1100000"
+
+#define CONFIG_MTDPARTS				\
+	"mtdparts=orion_nand:"			\
+	"0x80000@0x0(uboot),"			\
+	"0x20000@0x80000(uboot_env),"		\
+	"-@0xa0000(root)\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"console=console=ttyS0,115200\0"				\
+	"mtdids=nand0=orion_nand\0"					\
+	"mtdparts="CONFIG_MTDPARTS					\
+	"kernel=/boot/uImage\0"						\
+	"initrd=/boot/uInitrd\0"					\
+	"bootargs_root=ubi.mtd=2 root=ubi0:root rootfstype=ubifs\0"
+
+/*
+ * Ethernet driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR	0
+#undef CONFIG_RESET_PHY_R
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA driver configuration
+ */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_IDE_PREINIT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MVSATA_IDE_USE_PORT0
+#define CONFIG_MVSATA_IDE_USE_PORT1
+#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
+#define CONFIG_SYS_ATA_IDE1_OFFSET	MV_SATA_PORT1_OFFSET
+#endif /* CONFIG_CMD_IDE */
+
+/*
+ * RTC driver configuration
+ */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_MV
+#endif /* CONFIG_CMD_DATE */
+
+/*
+ * File system
+ */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+
+#endif /* _CONFIG_IB62x0_H */
diff --git a/include/configs/igep0030.h b/include/configs/igep0030.h
deleted file mode 100644
index bf39ba56d7..0000000000
--- a/include/configs/igep0030.h
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
- * (C) Copyright 2010
- * ISEE 2007 SL, <www.iseebcn.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-#include <asm/sizes.h>
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_OMAP		1	/* in a TI OMAP core */
-#define CONFIG_OMAP34XX		1	/* which is a 34XX */
-#define CONFIG_OMAP3_IGEP0030	1	/* working with IGEP0030 */
-
-#define CONFIG_SDRC	/* The chip has SDRC controller */
-
-#include <asm/arch/cpu.h>
-#include <asm/arch/omap3.h>
-
-/*
- * Display CPU and Board information
- */
-#define CONFIG_DISPLAY_CPUINFO		1
-#define CONFIG_DISPLAY_BOARDINFO	1
-
-/* Clock Defines */
-#define V_OSCK			26000000	/* Clock output from T2 */
-#define V_SCLK			(V_OSCK >> 1)
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_INITRD_TAG		1
-#define CONFIG_REVISION_TAG		1
-
-#define CONFIG_OF_LIBFDT		1
-
-/*
- * NS16550 Configuration
- */
-
-#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
-
-/* select serial console configuration */
-#define CONFIG_CONS_INDEX		3
-#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
-#define CONFIG_SERIAL3			3
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, 115200}
-#define CONFIG_GENERIC_MMC		1
-#define CONFIG_MMC			1
-#define CONFIG_OMAP_HSMMC		1
-#define CONFIG_DOS_PARTITION		1
-
-/* USB */
-#define CONFIG_MUSB_UDC			1
-#define CONFIG_USB_OMAP3		1
-#define CONFIG_TWL4030_USB		1
-
-/* USB device configuration */
-#define CONFIG_USB_DEVICE		1
-#define CONFIG_USB_TTY			1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
-
-/* Change these to suit your needs */
-#define CONFIG_USBD_VENDORID		0x0451
-#define CONFIG_USBD_PRODUCTID		0x5678
-#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
-#define CONFIG_USBD_PRODUCT_NAME	"IGEP"
-
-/* commands to include */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
-#define CONFIG_CMD_FAT		/* FAT support			*/
-#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
-#define CONFIG_CMD_MMC		/* MMC support			*/
-#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
-#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands	*/
-#define CONFIG_MTD_DEVICE
-
-#undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
-#undef CONFIG_CMD_NFS		/* nfs				*/
-#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
-#undef CONFIG_CMD_IMLS		/* List all found images	*/
-
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_HARD_I2C			1
-#define CONFIG_SYS_I2C_SPEED		100000
-#define CONFIG_SYS_I2C_SLAVE		1
-#define CONFIG_SYS_I2C_BUS		0
-#define CONFIG_SYS_I2C_BUS_SELECT	1
-#define CONFIG_DRIVER_OMAP34XX_I2C	1
-
-/*
- * TWL4030
- */
-#define CONFIG_TWL4030_POWER		1
-
-#define CONFIG_BOOTDELAY		3
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"usbtty=cdc_acm\0" \
-	"loadaddr=0x82000000\0" \
-	"usbtty=cdc_acm\0" \
-	"console=ttyS2,115200n8\0" \
-	"mpurate=500\0" \
-	"vram=12M\0" \
-	"dvimode=1024x768MR-16@60\0" \
-	"defaultdisplay=dvi\0" \
-	"mmcdev=0\0" \
-	"mmcroot=/dev/mmcblk0p2 rw\0" \
-	"mmcrootfstype=ext3 rootwait\0" \
-	"nandroot=/dev/mtdblock4 rw\0" \
-	"nandrootfstype=jffs2\0" \
-	"mmcargs=setenv bootargs console=${console} " \
-		"mpurate=${mpurate} " \
-		"vram=${vram} " \
-		"omapfb.mode=dvi:${dvimode} " \
-		"omapfb.debug=y " \
-		"omapdss.def_disp=${defaultdisplay} " \
-		"root=${mmcroot} " \
-		"rootfstype=${mmcrootfstype}\0" \
-	"nandargs=setenv bootargs console=${console} " \
-		"mpurate=${mpurate} " \
-		"vram=${vram} " \
-		"omapfb.mode=dvi:${dvimode} " \
-		"omapfb.debug=y " \
-		"omapdss.def_disp=${defaultdisplay} " \
-		"root=${nandroot} " \
-		"rootfstype=${nandrootfstype}\0" \
-	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
-	"bootscript=echo Running bootscript from mmc ...; " \
-		"source ${loadaddr}\0" \
-	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
-	"mmcboot=echo Booting from mmc ...; " \
-		"run mmcargs; " \
-		"bootm ${loadaddr}\0" \
-	"nandboot=echo Booting from onenand ...; " \
-		"run nandargs; " \
-		"onenand read ${loadaddr} 280000 400000; " \
-		"bootm ${loadaddr}\0" \
-
-#define CONFIG_BOOTCOMMAND \
-	"if mmc rescan ${mmcdev}; then " \
-		"if run loadbootscript; then " \
-			"run bootscript; " \
-		"else " \
-			"if run loaduimage; then " \
-				"run mmcboot; " \
-			"else run nandboot; " \
-			"fi; " \
-		"fi; " \
-	"else run nandboot; fi"
-
-#define CONFIG_AUTO_COMPLETE		1
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-#define CONFIG_SYS_PROMPT		"U-Boot # "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
-					sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
-
-#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
-								/* works on */
-#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
-					0x01F00000) /* 31MB */
-
-#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
-							/* load address */
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
-
-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
-#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ			1000
-
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
-
-/*
- * Physical Memory Map
- *
- */
-#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
-#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 meg */
-#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
-
-/*
- * FLASH and environment organization
- */
-
-#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M /* Configure the PISMO */
-
-#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
-
-#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
-
-#define CONFIG_ENV_IS_IN_ONENAND	1
-#define CONFIG_ENV_SIZE			(512 << 10) /* Total Size Environment */
-#define CONFIG_ENV_ADDR			ONENAND_ENV_OFFSET
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE	0x800
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/igep0020.h b/include/configs/igep00x0.h
index c2fcdffdae..a99f332a85 100644
--- a/include/configs/igep0020.h
+++ b/include/configs/igep00x0.h
@@ -1,5 +1,7 @@
 /*
- * (C) Copyright 2010
+ * Common configuration settings for IGEP technology based boards
+ *
+ * (C) Copyright 2012
  * ISEE 2007 SL, <www.iseebcn.com>
  *
  * This program is free software; you can redistribute it and/or
@@ -18,8 +20,9 @@
  * MA 02111-1307 USA
  */
 
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __IGEP00X0_H
+#define __IGEP00X0_H
+
 #include <asm/sizes.h>
 
 /*
@@ -27,7 +30,6 @@
  */
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
-#define CONFIG_OMAP3_IGEP0020	1	/* working with IGEP0020 */
 
 #define CONFIG_SDRC	/* The chip has SDRC controller */
 
@@ -72,7 +74,8 @@
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, 115200}
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
+					115200}
 #define CONFIG_GENERIC_MMC		1
 #define CONFIG_MMC			1
 #define CONFIG_OMAP_HSMMC		1
@@ -133,7 +136,7 @@
 	"loadaddr=0x82000000\0" \
 	"usbtty=cdc_acm\0" \
 	"console=ttyS2,115200n8\0" \
-	"mpurate=500\0" \
+	"mpurate=auto\0" \
 	"vram=12M\0" \
 	"dvimode=1024x768MR-16@60\0" \
 	"defaultdisplay=dvi\0" \
@@ -158,9 +161,9 @@
 		"omapdss.def_disp=${defaultdisplay} " \
 		"root=${nandroot} " \
 		"rootfstype=${nandrootfstype}\0" \
-	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
-	"bootscript=echo Running bootscript from mmc ...; " \
-		"source ${loadaddr}\0" \
+	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
 	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
@@ -172,15 +175,19 @@
 
 #define CONFIG_BOOTCOMMAND \
 	"if mmc rescan ${mmcdev}; then " \
-		"if run loadbootscript; then " \
-			"run bootscript; " \
-		"else " \
-			"if run loaduimage; then " \
-				"run mmcboot; " \
-			"else run nandboot; " \
-			"fi; " \
-		"fi; " \
-	"else run nandboot; fi"
+		"echo SD/MMC found on device ${mmcdev};" \
+		"if run loadbootenv; then " \
+			"run importbootenv;" \
+		"fi;" \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...;" \
+			"run uenvcmd;" \
+		"fi;" \
+		"if run loaduimage; then " \
+			"run mmcboot;" \
+		"fi;" \
+	"fi;" \
+	"run nandboot;" \
 
 #define CONFIG_AUTO_COMPLETE		1
 
@@ -269,4 +276,4 @@
 					 CONFIG_SYS_INIT_RAM_SIZE - \
 					 GENERATED_GBL_DATA_SIZE)
 
-#endif /* __CONFIG_H */
+#endif /* __IGEP00X0_H */
diff --git a/include/configs/ima3-mx53.h b/include/configs/ima3-mx53.h
new file mode 100644
index 0000000000..ea48d64635
--- /dev/null
+++ b/include/configs/ima3-mx53.h
@@ -0,0 +1,269 @@
+/*
+ * (C) Copyright 2012, Stefano Babic <sbabic@denx.de>
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX53-EVK Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* SOC type must be included before imx-regs.h */
+#define CONFIG_MX53
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+
+#define CONFIG_SYS_MX5_HCLK		24000000
+#define CONFIG_SYS_MX5_CLK32		32768
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_OF_LIBFDT
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Enable GPIOs */
+#define CONFIG_MXC_GPIO
+
+/* UART */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART4_BASE_ADDR
+
+/* MMC */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+
+/* Ethernet on FEC */
+#define CONFIG_NET_MULTI
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR		0x01
+#define CONFIG_PHY_ADDR			CONFIG_FEC_MXC_PHYADDR
+#define CONFIG_RESET_PHY_R
+#define CONFIG_FEC_MXC_NO_ANEG
+#define CONFIG_PRIME	"FEC0"
+
+/* SPI */
+#define CONFIG_HARD_SPI
+#define CONFIG_MXC_SPI
+#define CONFIG_DEFAULT_SPI_BUS		1
+#define CONFIG_DEFAULT_SPI_MODE		SPI_MODE_0
+
+/* SPI FLASH - not used for environment */
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_CS		(IOMUX_TO_GPIO(MX53_PIN_CSI0_D11) \
+						 << 8) | 0
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED		25000000
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+
+/* Command definition */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_GPIO
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_LOADADDR		0x70800000	/* loadaddr env var */
+#define CONFIG_SYS_TEXT_BASE    0xf0001400 /* uboot in nor flash */
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		"IMA3 MX53 U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START       0x70000000
+#define CONFIG_SYS_MEMTEST_END         0x10000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ		1000
+#define CONFIG_CMDLINE_EDITING
+
+/* Stack sizes */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(1024 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define MTDIDS_DEFAULT		"nor0=f0000000.flash"
+
+/* FLASH and environment organization */
+
+#define CONFIG_SYS_FLASH_BASE		0xF0000000
+#define CONFIG_SYS_FLASH_CFI		/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER		/* Use the common driver */
+#define CONFIG_FLASH_CFI_MTD		/* with MTD support */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	1024
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+
+#define CONFIG_ENV_SIZE        (8 * 1024)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+					CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+
+#define HOSTNAME ima3-mx53
+#define xstr(s)	str(s)
+#define str(s)	#s
+
+#define CONFIG_HOSTNAME ima3-mx53
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram0 rw\0"			\
+	"addip_sta=setenv bootargs ${bootargs} "			\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
+	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
+		"else run addip_sta;fi\0"	\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=${console},${baudrate}\0"			\
+	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
+	"console=ttymxc3\0"						\
+	"loadaddr=70800000\0"						\
+	"kernel_addr_r=70800000\0"					\
+	"ramdisk_addr_r=71000000\0"					\
+	"hostname=" xstr(CONFIG_HOSTNAME) "\0"				\
+	"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0"			\
+	"ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0"		\
+	"mmcargs=setenv bootargs root=${mmcroot} "			\
+		"rootfstype=${mmcrootfstype}\0"				\
+	"mmcroot=/dev/mmcblk0p3 rw\0"					\
+	"mmcboot=echo Booting from mmc ...; "				\
+		"run mmcargs addip addtty addmtd addmisc mmcload;"	\
+		"bootm\0"						\
+	"mmcload=fatload mmc ${mmcdev}:${mmcpart} "			\
+		"${loadaddr} ${uimage}\0"				\
+	"mmcrootfstype=ext3 rootwait\0"					\
+	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_self_load=tftp ${ramdisk_addr_r} ${ramdisk_file};"		\
+		"tftp ${kernel_addr_r} ${bootfile}\0"			\
+	"net_self=if run net_self_load;then "				\
+		"run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
+		"else echo Images not loades;fi\0"			\
+	"satargs=setenv bootargs root=/dev/sda1\0"			\
+	"satafile=boot/uImage\0"					\
+	"ssdboot=echo Booting from ssd ...; "				\
+		"run satargs addip addtty addmtd addmisc;"		\
+		"sata init;ext2load sata 0:1 ${kernel_addr_r} "		\
+		"${satafile};bootm\0"					\
+	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.imx\0"			\
+	"uimage=uImage\0"						\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"uboot_addr=0xf0001000\0"					\
+	"update=protect off 0xf0000000 +60000;"				\
+		"erase ${uboot_addr} +60000;"				\
+		"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0"		\
+	"upd=if run load;then echo Updating u-boot;if run update;"	\
+		"then echo U-Boot updated;"				\
+			"else echo Error updating u-boot !;"		\
+			"echo Board without bootloader !!;"		\
+		"fi;"							\
+		"else echo U-Boot not downloaded..exiting;fi\0"		\
+	"bootcmd=run net_nfs\0"
+
+
+#define CONFIG_CMD_SATA
+#ifdef CONFIG_CMD_SATA
+	#define CONFIG_DWC_AHSATA
+	#define CONFIG_SYS_SATA_MAX_DEVICE      1
+	#define CONFIG_DWC_AHSATA_PORT_ID       0
+	#define CONFIG_DWC_AHSATA_BASE_ADDR     SATA_BASE_ADDR
+	#define CONFIG_LBA48
+	#define CONFIG_LIBATA
+#endif
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h
index 2af4e7af31..c1f1aa6a8a 100644
--- a/include/configs/imx27lite-common.h
+++ b/include/configs/imx27lite-common.h
@@ -153,7 +153,6 @@
 #define CONFIG_SYS_NAND_BASE		0xd8000000
 #define CONFIG_JFFS2_NAND
 #define CONFIG_MXC_NAND_HWECC
-#define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
 
 /*
  * SD/MMC
diff --git a/include/configs/intip.h b/include/configs/intip.h
index 92b65af7c9..33364a843e 100644
--- a/include/configs/intip.h
+++ b/include/configs/intip.h
@@ -37,10 +37,10 @@
 #define CONFIG_460EX		1	/* Specific PPC460EX		*/
 #ifdef CONFIG_DEVCONCENTER
 #define CONFIG_HOSTNAME		devconcenter
-#define CONFIG_IDENT_STRING	" devconcenter 0.05"
+#define CONFIG_IDENT_STRING	" devconcenter 0.06"
 #else
 #define CONFIG_HOSTNAME		intip
-#define CONFIG_IDENT_STRING	" intip 0.05"
+#define CONFIG_IDENT_STRING	" intip 0.06"
 #endif
 #define CONFIG_440		1
 #define CONFIG_4xx		1	/* ... PPC4xx family */
diff --git a/include/configs/io.h b/include/configs/io.h
index 9d2a87d22d..03661cce2d 100644
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -34,11 +34,13 @@
  * Include common defines/options for all AMCC eval boards
  */
 #define CONFIG_HOSTNAME		io
-#define CONFIG_IDENT_STRING	" io 0.04"
+#define CONFIG_IDENT_STRING	" io 0.05"
 #include "amcc-common.h"
 
-#define CONFIG_BOARD_EARLY_INIT_F	/* call board_early_init_f */
-#define CONFIG_LAST_STAGE_INIT		/* call last_stage_init */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+#define CONFIG_LAST_STAGE_INIT
 
 #define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
 
@@ -48,6 +50,10 @@
 #define PLLMR0_DEFAULT PLLMR0_266_133_66
 #define PLLMR1_DEFAULT PLLMR1_266_133_66
 
+#undef CONFIG_ZERO_BOOTDELAY_CHECK	/* ignore keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
 /* new uImage format support */
 #define CONFIG_FIT
 #define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
@@ -76,6 +82,7 @@
  * Commands additional to the ones defined in amcc-common.h
  */
 #define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DTT
 #undef CONFIG_CMD_EEPROM
 
 /*
diff --git a/include/configs/io64.h b/include/configs/io64.h
index 51b2dd1c13..887aaefd39 100644
--- a/include/configs/io64.h
+++ b/include/configs/io64.h
@@ -53,7 +53,7 @@
  * Include common defines/options for all AMCC eval boards
  */
 #define CONFIG_HOSTNAME		io64
-#define CONFIG_IDENT_STRING	" io64 0.01"
+#define CONFIG_IDENT_STRING	" io64 0.02"
 #include "amcc-common.h"
 
 #define CONFIG_BOARD_EARLY_INIT_F
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 9fcc6430cd..7f8825bed1 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -34,10 +34,11 @@
  * Include common defines/options for all AMCC eval boards
  */
 #define CONFIG_HOSTNAME		iocon
-#define CONFIG_IDENT_STRING	" iocon 0.03"
+#define CONFIG_IDENT_STRING	" iocon 0.04"
 #include "amcc-common.h"
 
-#define CONFIG_BOARD_EARLY_INIT_F	/* call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_LAST_STAGE_INIT
 
 #define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
@@ -48,6 +49,10 @@
 #define PLLMR0_DEFAULT PLLMR0_266_133_66
 #define PLLMR1_DEFAULT PLLMR1_266_133_66
 
+#undef CONFIG_ZERO_BOOTDELAY_CHECK	/* ignore keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
 /* new uImage format support */
 #define CONFIG_FIT
 #define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h
index f72ee02abf..d644fea22f 100644
--- a/include/configs/jadecpu.h
+++ b/include/configs/jadecpu.h
@@ -130,7 +130,6 @@
 #undef CONFIG_CMD_XIMG
 
 #define CONFIG_CMD_BMP
-#define CONFIG_CMD_CAN
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_FAT
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index 621dbb8fa6..d505a41de4 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -447,7 +447,6 @@
  */
 #define CONFIG_CMD_CHIP_CONFIG
 #define CONFIG_CMD_DATE
-#define CONFIG_CMD_LOG
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SNTP
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index a6f2864c65..68215fda9d 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -435,7 +435,6 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_LOG
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_NFS
diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
index 012381a500..c62f4d01fd 100644
--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
@@ -43,6 +43,8 @@
 #define	CONFIG_ARCH_CPU_INIT
 #define	CONFIG_ARCH_MISC_INIT
 
+#define CONFIG_OF_LIBFDT
+
 /*
  * SPL
  */
@@ -52,6 +54,7 @@
 #define	CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds"
 #define	CONFIG_SPL_LIBCOMMON_SUPPORT
 #define	CONFIG_SPL_LIBGENERIC_SUPPORT
+#define	CONFIG_SPL_GPIO_SUPPORT
 
 /*
  * U-Boot Commands
@@ -84,7 +87,7 @@
  */
 #define	CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
 #define	PHYS_SDRAM_1			0x40000000	/* Base address */
-#define	PHYS_SDRAM_1_SIZE		0x40000000	/* Max 1 GB RAM */
+#define	PHYS_SDRAM_1_SIZE		0x20000000	/* Max 512 MB RAM */
 #define	CONFIG_STACKSIZE		0x00010000	/* 128 KB stack */
 #define	CONFIG_SYS_MALLOC_LEN		0x00400000	/* 4 MB for malloc */
 #define	CONFIG_SYS_GBL_DATA_SIZE	128		/* Initial data */
@@ -279,6 +282,7 @@
 #define	CONFIG_BOOTCOMMAND	"run bootcmd_net"
 #define	CONFIG_LOADADDR		0x42000000
 #define	CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+#define	CONFIG_OF_LIBFDT
 
 /*
  * Extra Environments
@@ -286,6 +290,7 @@
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"update_nand_full_filename=u-boot.nand\0"			\
 	"update_nand_firmware_filename=u-boot.sb\0"			\
+	"update_sd_firmware_filename=u-boot.sd\0"			\
 	"update_nand_firmware_maxsz=0x100000\0"				\
 	"update_nand_stride=0x40\0"	/* MX28 datasheet ch. 12.12 */	\
 	"update_nand_count=0x4\0"	/* MX28 datasheet ch. 12.12 */	\
@@ -312,6 +317,14 @@
 		"nand erase ${fcb_sz} ${fw_sz} ; "			\
 		"nand write ${loadaddr} ${fcb_sz} ${filesize} ; "	\
 		"nand write ${loadaddr} ${fw_off} ${filesize} ; "	\
+		"fi\0"							\
+	"update_sd_firmware="		/* Update the SD firmware partition */ \
+		"if mmc rescan ; then "					\
+		"if tftp ${update_sd_firmware_filename} ; then "	\
+		"setexpr fw_sz ${filesize} / 0x200 ; "	/* SD block size */ \
+		"setexpr fw_sz ${fw_sz} + 1 ; "				\
+		"mmc write ${loadaddr} 0x800 ${fw_sz} ; "		\
+		"fi ; "							\
 		"fi\0"
 
 #endif /* __M28_H__ */
diff --git a/include/configs/makalu.h b/include/configs/makalu.h
index fcc789d714..6c1b136659 100644
--- a/include/configs/makalu.h
+++ b/include/configs/makalu.h
@@ -252,7 +252,6 @@
  */
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_DTT
-#define CONFIG_CMD_LOG
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SNTP
 
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index 1315c3ceb8..f6a83a8505 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -171,8 +171,6 @@
 
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
 							/* NAND devices */
-#define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
-
 #define CONFIG_JFFS2_NAND
 /* nand device jffs2 lives on */
 #define CONFIG_JFFS2_DEV		"nand0"
@@ -327,7 +325,7 @@
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
 
 #define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
-#define CONFIG_SPL_MAX_SIZE		(45 << 10)
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
 
 /* move malloc and bss high to prevent clashing with the main image */
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index d6197bc610..db1e87d69c 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -164,7 +164,6 @@
 # define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
 # define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIO_PORTD, 15
 # define CONFIG_SYS_NAND_READY_PIN		AT91_PIO_PORTA, 22
-# define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
 #endif
 
 /* Ethernet */
diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h
index 7cf641fd13..f1104902be 100644
--- a/include/configs/ms7722se.h
+++ b/include/configs/ms7722se.h
@@ -35,7 +35,6 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_PING
-#define CONFIG_CMD_DFL
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_SAVEENV
diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h
index 03f52f3905..52e15cce87 100644
--- a/include/configs/ms7750se.h
+++ b/include/configs/ms7750se.h
@@ -38,7 +38,6 @@
  */
 /*#include <config_cmd_default.h>*/
 
-#define CONFIG_CMD_DFL
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_SAVEENV
 
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index 1a6379176b..27b489902b 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h
@@ -132,7 +132,6 @@
  */
 #ifdef CONFIG_CMD_NAND
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define CONFIG_SYS_64BIT_VSPRINTF      /* needed for nand_util.c */
 #endif
 
 /*
diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h
index d1ba02b6ee..7210b6e80f 100644
--- a/include/configs/mx25pdk.h
+++ b/include/configs/mx25pdk.h
@@ -65,7 +65,6 @@
 #define CONFIG_ENV_IS_NOWHERE
 
 #define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_64BIT_VSPRINTF
 
 /* U-Boot general configuration */
 #define CONFIG_SYS_PROMPT	"MX25PDK U-Boot > "
diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
index 02f3366ed2..0c18e5022a 100644
--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
@@ -46,6 +46,7 @@
 #define CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds"
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
 
 /*
  * U-Boot Commands
@@ -67,6 +68,7 @@
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_USB
+#define CONFIG_CMD_BOOTZ
 
 /*
  * Memory configurations
@@ -148,6 +150,16 @@
 #endif
 
 /*
+ * NAND Driver
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_MXS
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x60000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#endif
+
+/*
  * Ethernet on SOC (FEC)
  */
 #ifdef	CONFIG_CMD_NET
@@ -225,6 +237,7 @@
 #define CONFIG_BOOTCOMMAND	"run bootcmd_net"
 #define CONFIG_LOADADDR	0x42000000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+#define CONFIG_OF_LIBFDT
 
 /*
  * Extra Environments
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index 49d440b9ae..6ce97bc69f 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -99,6 +99,7 @@
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_DATE
 #define CONFIG_CMD_NAND
+#define CONFIG_CMD_BOOTZ
 
 /*
  * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index de4b954a52..bd57baa808 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -39,8 +39,6 @@
 #define CONFIG_SYS_TEXT_BASE	0xA0000000
 #define CONFIG_SYS_CACHELINE_SIZE	32
 
-#define CONFIG_SYS_64BIT_VSPRINTF
-
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_LATE_INIT
 
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 34a4edd41e..eab0e27fb5 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -27,7 +27,6 @@
 
 #define CONFIG_SYS_MX5_HCLK	24000000
 #define CONFIG_SYS_MX5_CLK32		32768
-#define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_MACH_TYPE	MACH_TYPE_MX53_LOCO
@@ -42,7 +41,9 @@
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
 
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
 #define CONFIG_MXC_GPIO
+#define CONFIG_REVISION_TAG
 
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE	UART1_BASE
@@ -56,6 +57,7 @@
 #define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
 #define CONFIG_DOS_PARTITION
 
 /* Eth Configs */
@@ -85,6 +87,21 @@
 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS	0
 
+/* I2C Configs */
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_MX53_PORT1
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		0xfe
+
+/* PMIC Controller */
+#define CONFIG_PMIC
+#define CONFIG_PMIC_I2C
+#define CONFIG_DIALOG_PMIC
+#define CONFIG_PMIC_FSL
+#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR	0x48
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR	0x8
+
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX		1
@@ -193,4 +210,14 @@
 
 #define CONFIG_OF_LIBFDT
 
+#define CONFIG_CMD_SATA
+#ifdef CONFIG_CMD_SATA
+	#define CONFIG_DWC_AHSATA
+	#define CONFIG_SYS_SATA_MAX_DEVICE      1
+	#define CONFIG_DWC_AHSATA_PORT_ID       0
+	#define CONFIG_DWC_AHSATA_BASE_ADDR     SATA_BASE_ADDR
+	#define CONFIG_LBA48
+	#define CONFIG_LIBATA
+#endif
+
 #endif				/* __CONFIG_H */
diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
index e83aec6c21..90652c6629 100644
--- a/include/configs/mx6qarm2.h
+++ b/include/configs/mx6qarm2.h
@@ -168,6 +168,7 @@
 #define CONFIG_SYS_MMC_ENV_DEV		1
 
 #define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
 
 #define CONFIG_SYS_DCACHE_OFF
 
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index 3f7e51d877..feabc05a47 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -42,6 +42,7 @@
 
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
 #define CONFIG_MXC_GPIO
 
 #define CONFIG_MXC_UART
@@ -71,6 +72,19 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
+#define CONFIG_CMD_SATA
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
@@ -110,6 +124,8 @@
 
 #define CONFIG_BOOTDELAY	       3
 
+#define CONFIG_PREBOOT                 ""
+
 #define CONFIG_LOADADDR			       0x10800000
 #define CONFIG_SYS_TEXT_BASE	       0x17800000
 
@@ -211,6 +227,7 @@
 #endif
 
 #define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
 
 #define CONFIG_SYS_DCACHE_OFF
 
diff --git a/include/configs/neo.h b/include/configs/neo.h
index 8de5aaf1ed..38b5becc2e 100644
--- a/include/configs/neo.h
+++ b/include/configs/neo.h
@@ -35,9 +35,13 @@
  * Include common defines/options for all AMCC eval boards
  */
 #define CONFIG_HOSTNAME		neo
+#define CONFIG_IDENT_STRING	" neo 0.01"
 #include "amcc-common.h"
 
-#define CONFIG_BOARD_EARLY_INIT_F 	/* call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+#define CONFIG_LAST_STAGE_INIT
 
 #define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
 
@@ -149,53 +153,53 @@
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector		*/
-#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
-#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+#define CONFIG_ENV_ADDR		0xFFF00000
+#define	CONFIG_ENV_SIZE		0x20000	/* Total Size of Environment Sector */
 
 /* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR_REDUND	0xFFF20000
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 #endif
 
 /*
  * PPC405 GPIO Configuration
  */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /*				GPIO	Alternate1	*/	\
-{											\
-/* GPIO Core 0 */									\
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast    	*/	\
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1	TS1E		*/	\
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2	TS2E		*/	\
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3	TS1O		*/	\
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4	TS2O		*/	\
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO5	TS3		*/	\
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6	TS4		*/	\
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO7	TS5		*/	\
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8	TS6		*/	\
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9	TrcClk		*/	\
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10	PerCS1		*/	\
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11	PerCS2		*/	\
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12	PerCS3		*/	\
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13	PerCS4		*/	\
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14	PerAddr03   	*/	\
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15	PerAddr04   	*/	\
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16	PerAddr05   	*/	\
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17	IRQ0	    	*/	\
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18	IRQ1	    	*/	\
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19	IRQ2	    	*/	\
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20	IRQ3	    	*/	\
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21	IRQ4	    	*/	\
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22	IRQ5	    	*/	\
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23	IRQ6	    	*/	\
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24	UART0_DCD   	*/	\
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR	*/	\
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI	*/	\
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR	*/	\
-{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx    	*/	\
-{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx	*/	\
-{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0  	*/	\
-{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1  	*/	\
-}											\
+#define CONFIG_SYS_4xx_GPIO_TABLE { \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1	TS1E	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2	TS2E	   */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3	TS1O	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4	TS2O	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5	TS3	   */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6	TS4	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO7	TS5	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8	TS6	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9	TrcClk	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10	PerCS1	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11	PerCS2	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12	PerCS3	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13	PerCS4	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14	PerAddr03  */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15	PerAddr04  */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16	PerAddr05  */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17	IRQ0	   */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18	IRQ1	   */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19	IRQ2	   */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20	IRQ3	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21	IRQ4	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22	IRQ5	   */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23	IRQ6	   */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24	UART0_DCD  */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR  */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR  */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1 */ \
+} \
 }
 
 /*
@@ -226,12 +230,22 @@
 #define CONFIG_SYS_EBC_PB1CR		0xFB85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
 
 /* Memory Bank 2 (FPGA) initialization                 */
-#define CONFIG_FPGA_BASE	0x7f100000
+#define CONFIG_SYS_FPGA0_BASE		0x7f100000
 #define CONFIG_SYS_EBC_PB2AP		0x92015480
 #define CONFIG_SYS_EBC_PB2CR		0x7f11a000  /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
 
+#define CONFIG_SYS_FPGA_BASE(k)		CONFIG_SYS_FPGA0_BASE
+
+#define CONFIG_SYS_FPGA_COUNT		1
+
 /* Memory Bank 3 (Latches) initialization                      */
+#define CONFIG_SYS_LATCH_BASE		0x7f200000
 #define CONFIG_SYS_EBC_PB3AP		0x92015480
 #define CONFIG_SYS_EBC_PB3CR		0x7f21a000  /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
 
+#define CONFIG_SYS_LATCH0_RESET		0xffff
+#define CONFIG_SYS_LATCH0_BOOT		0xffff
+#define CONFIG_SYS_LATCH1_RESET		0xffbf
+#define CONFIG_SYS_LATCH1_BOOT		0xffff
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index ddeb4146f7..b891ee4925 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -399,7 +399,7 @@
 #define CONFIG_SPL
 #define CONFIG_SPL_NAND_SIMPLE
 #define CONFIG_SPL_TEXT_BASE		0x40200800
-#define CONFIG_SPL_MAX_SIZE		(45 * 1024)
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
 
 #define CONFIG_SPL_BSS_START_ADDR	0x80000000
@@ -410,6 +410,7 @@
 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
 
+#define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #define CONFIG_SPL_I2C_SUPPORT
diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h
index 4910ddaa83..7b21a5c8c4 100644
--- a/include/configs/omap3_evm_common.h
+++ b/include/configs/omap3_evm_common.h
@@ -282,12 +282,13 @@
 /* Defines for SPL */
 #define CONFIG_SPL
 #define CONFIG_SPL_TEXT_BASE		0x40200800
-#define CONFIG_SPL_MAX_SIZE		(45 * 1024)	/* 45 KB */
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
 
 #define CONFIG_SPL_BSS_START_ADDR	0x80000000
 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
 
+#define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #define CONFIG_SPL_I2C_SUPPORT
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 01360f6cbd..4ac17cc636 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -122,7 +122,7 @@
 #define CONFIG_CMD_NET      /* bootp, tftpboot, rarpboot    */
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
-#define CONFIG_CMD_SETECPR	/* Evaluate expressions		*/
+#define CONFIG_CMD_SETEXPR	/* Evaluate expressions		*/
 
 #undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
 #undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index 64adc7455c..a0a7a1c42a 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -303,7 +303,7 @@
 #define CONFIG_SPL
 #define CONFIG_SPL_NAND_SIMPLE
 #define CONFIG_SPL_TEXT_BASE		0x40200800
-#define CONFIG_SPL_MAX_SIZE		(45 * 1024)
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
 
 /* move malloc and bss high to prevent clashing with the main image */
@@ -317,6 +317,7 @@
 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
 
+#define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #define CONFIG_SPL_I2C_SUPPORT
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index 4df5f5dac5..d02f338437 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -174,8 +174,7 @@
 	"usbtty=cdc_acm\0" \
 	"loadaddr=0x82000000\0" \
 	"bootargs=ubi.mtd=4 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs " \
-	"rw rootflags=bulk_read console=ttyS0,115200n8 " \
-	"vram=6272K omapfb.vram=0:3000K\0" \
+		"rw rootflags=bulk_read vram=6272K omapfb.vram=0:3000K\0" \
 	"mtdparts=" MTDPARTS_DEFAULT "\0" \
 
 #define CONFIG_BOOTCOMMAND \
diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
index a989721afc..072e17bab8 100644
--- a/include/configs/omap4_common.h
+++ b/include/configs/omap4_common.h
@@ -35,7 +35,6 @@
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP44XX		1	/* which is a 44XX */
 #define CONFIG_OMAP4430		1	/* which is in a 4430 */
-#define CONFIG_ARCH_CPU_INIT
 
 /* Get CPU defs */
 #include <asm/arch/cpu.h>
@@ -106,7 +105,6 @@
 #define CONFIG_GENERIC_MMC		1
 #define CONFIG_MMC			1
 #define CONFIG_OMAP_HSMMC		1
-#define CONFIG_SYS_MMC_SET_DEV		1
 #define CONFIG_DOS_PARTITION		1
 
 
@@ -151,6 +149,7 @@
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
 	"console=ttyO2,115200n8\0" \
+	"fdt_high=0xffffffff\0" \
 	"usbtty=cdc_acm\0" \
 	"vram=16M\0" \
 	"mmcdev=0\0" \
@@ -287,4 +286,6 @@
 
 #define CONFIG_SYS_ENABLE_PADS_ALL
 
+#define CONFIG_SYS_THUMB_BUILD
+
 #endif /* __CONFIG_OMAP4_COMMON_H */
diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h
index a8dfef321d..d3a2438e28 100644
--- a/include/configs/omap5912osk.h
+++ b/include/configs/omap5912osk.h
@@ -44,8 +44,6 @@
 
 #undef CONFIG_USE_IRQ	/* we don't need IRQ/FIQ stuff */
 
-#define CONFIG_MISC_INIT_R
-
 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
 #define CONFIG_SETUP_MEMORY_TAGS	1
 #define CONFIG_INITRD_TAG      1       /* Required for ramdisk support */
diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h
index d3d526310e..38b5028060 100644
--- a/include/configs/omap5_evm.h
+++ b/include/configs/omap5_evm.h
@@ -38,7 +38,6 @@
 #define CONFIG_OMAP54XX	/* which is a 54XX */
 #define CONFIG_OMAP5430	/* which is in a 5430 */
 #define CONFIG_5430EVM	/* working with EVM */
-#define CONFIG_ARCH_CPU_INIT
 
 /* Get CPU defs */
 #include <asm/arch/cpu.h>
@@ -49,8 +48,10 @@
 #define CONFIG_DISPLAY_BOARDINFO
 
 /* Clock Defines */
-#define V_OSCK	38400000 /* Clock output from T2 */
+#define V_OSCK			19200000	/* Clock output from T2 */
 #define V_SCLK	V_OSCK
+#define CONFIG_SYS_CLOCKS_ENABLE_ALL	1	/* Enable all clocks */
+#define CONFIG_SYS_ENABLE_PADS_ALL	1	/* Enable all PADS for now */
 
 #undef CONFIG_USE_IRQ	/* no support for IRQs */
 #define CONFIG_MISC_INIT_R
@@ -97,9 +98,10 @@
 #define CONFIG_DRIVER_OMAP34XX_I2C
 #define CONFIG_I2C_MULTI_BUS
 
-/* TWL6030 */
-#define CONFIG_TWL6030_POWER
-#define CONFIG_CMD_BAT
+/* TWL6035 */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_TWL6035_POWER
+#endif
 
 /* MMC */
 #define CONFIG_GENERIC_MMC
@@ -111,14 +113,8 @@
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		1	/* SLOT2: eMMC(1) */
 #define CONFIG_ENV_OFFSET		0xE0000
+#define CONFIG_CMD_SAVEENV
 
-/* USB */
-#define CONFIG_MUSB_UDC
-#define CONFIG_USB_OMAP3
-
-/* USB device configuration */
-#define CONFIG_USB_DEVICE
-#define CONFIG_USB_TTY
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
 /* Flash */
@@ -154,7 +150,7 @@
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
-	"console=ttyS2,115200n8\0" \
+	"console=ttyO2,115200n8\0" \
 	"usbtty=cdc_acm\0" \
 	"vram=16M\0" \
 	"mmcdev=0\0" \
@@ -250,8 +246,8 @@
 
 /* Defines for SPL */
 #define CONFIG_SPL
-#define CONFIG_SPL_TEXT_BASE		0x40304350
-#define CONFIG_SPL_MAX_SIZE		0x1E000	/* 120K */
+#define CONFIG_SPL_TEXT_BASE		0x40300350
+#define CONFIG_SPL_MAX_SIZE		0x19000	/* 100K */
 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
 
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
diff --git a/include/configs/omap730p2.h b/include/configs/omap730p2.h
index 26e7e1f1e0..f7900e0d83 100644
--- a/include/configs/omap730p2.h
+++ b/include/configs/omap730p2.h
@@ -49,8 +49,6 @@
 
 #undef CONFIG_USE_IRQ			     /* we don't need IRQ/FIQ stuff */
 
-#define CONFIG_MISC_INIT_R
-
 #define CONFIG_CMDLINE_TAG	   1	     /* enable passing of ATAGs	 */
 #define CONFIG_SETUP_MEMORY_TAGS   1
 
diff --git a/include/configs/origen.h b/include/configs/origen.h
index 8ede82575c..d4d0f84be6 100644
--- a/include/configs/origen.h
+++ b/include/configs/origen.h
@@ -69,9 +69,10 @@
 #define EXYNOS4_DEFAULT_UART_OFFSET	0x020000
 
 /* SD/MMC configuration */
-#define CONFIG_GENERIC_MMC		1
-#define CONFIG_MMC			1
-#define CONFIG_S5P_MMC			1
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_S5P_SDHCI
 
 /* PWM */
 #define CONFIG_PWM			1
@@ -82,7 +83,7 @@
 /* Command definition*/
 #include <config_cmd_default.h>
 
-#define CONFIG_CMD_PING
+#undef CONFIG_CMD_PING
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MMC
diff --git a/include/configs/otc570.h b/include/configs/otc570.h
index b322c775a1..85993789b9 100644
--- a/include/configs/otc570.h
+++ b/include/configs/otc570.h
@@ -215,7 +215,6 @@
 # define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
 # define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIO_PORTD, 15
 # define CONFIG_SYS_NAND_READY_PIN		AT91_PIO_PORTA, 22
-# define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
 #endif
 
 /* Ethernet */
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 3098c5acfe..04fd8d07f5 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -184,7 +184,7 @@
 #define CONFIG_ENV_OVERWRITE
 
 #define CONFIG_CMD_SATA
-#define CONFIG_SATA_SIL3114
+#define CONFIG_SATA_SIL
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_LIBATA
 #define CONFIG_LBA48
@@ -227,7 +227,7 @@
 
 /* DDR Setup */
 #define CONFIG_FSL_DDR3
-#define CONFIG_DDR_RAW_TIMING
+#define CONFIG_SYS_DDR_RAW_TIMING
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_SPD_BUS_NUM 1
 #define SPD_EEPROM_ADDRESS 0x52
@@ -534,9 +534,6 @@
 #define CONFIG_OF_BOARD_SETUP
 #define CONFIG_OF_STDOUT_VIA_ALIAS
 
-#define CONFIG_SYS_64BIT_VSPRINTF
-#define CONFIG_SYS_64BIT_STRTOUL
-
 /* new uImage format support */
 #define CONFIG_FIT
 #define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h
new file mode 100644
index 0000000000..df46be5469
--- /dev/null
+++ b/include/configs/pogo_e02.h
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2012
+ * David Purdy <david.c.purdy@gmail.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _CONFIG_POGO_E02_H
+#define _CONFIG_POGO_E02_H
+
+/*
+ * Machine type definition and ID
+ */
+#define MACH_TYPE_POGO_E02		3542
+#define CONFIG_MACH_TYPE		MACH_TYPE_POGO_E02
+#define CONFIG_IDENT_STRING		"\nPogo E02"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
+#define CONFIG_KIRKWOOD			/* SOC Family Name */
+#define CONFIG_KW88F6281		/* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#define CONFIG_SYS_MVFS
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* Remove or override few declarations from mv-common.h */
+#undef CONFIG_SYS_PROMPT	/* previously defined in mv-common.h */
+#define CONFIG_SYS_PROMPT	"PogoE02> "
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* 128K */
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE			0x20000	/* 128k */
+#define CONFIG_ENV_OFFSET		0x60000	/* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND \
+	"setenv bootargs $(bootargs_console); " \
+	"run bootcmd_usb; " \
+	"bootm 0x00800000 0x01100000"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"mtdparts=mtdparts=orion_nand:1M(u-boot),4M(uImage)," \
+	"32M(rootfs),-(data)\0"\
+	"mtdids=nand0=orion_nand\0"\
+	"bootargs_console=console=ttyS0,115200\0" \
+	"bootcmd_usb=usb start; ext2load usb 0:1 0x00800000 /uImage; " \
+	"ext2load usb 0:1 0x01100000 /uInitrd\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR	0
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * File system
+ */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_LZO
+
+#endif /* _CONFIG_POGO_E02_H */
diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h
index dc5ec3aa82..5d0c385987 100644
--- a/include/configs/quad100hd.h
+++ b/include/configs/quad100hd.h
@@ -69,7 +69,6 @@
 #define CONFIG_CMD_I2C
 #undef CONFIG_CMD_IRQ
 #define CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_LOG
 #undef CONFIG_CMD_MII
 #define CONFIG_CMD_NAND
 #undef CONFIG_CMD_PING
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
index 0ce3fa864c..9cdfc147e9 100644
--- a/include/configs/r2dplus.h
+++ b/include/configs/r2dplus.h
@@ -15,7 +15,6 @@
  */
 #include <config_cmd_default.h>
 
-#define CONFIG_CMD_DFL
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_PCI
diff --git a/include/configs/rda8810.h b/include/configs/rda8810.h
new file mode 100644
index 0000000000..8e63b43f55
--- /dev/null
+++ b/include/configs/rda8810.h
@@ -0,0 +1,25 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/rda_config_defaults.h>
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_RDA8810
+
+#define CONFIG_MACH_TYPE (5002)
+
+/*
+ * Flash & Environment
+ */
+/* #define CONFIG_NAND_RDA_DMA */
+#define CONFIG_NAND_RDA_V1		/* V1 for rda8810, rda8850 */
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+
+// Enable RDA signed bootloader:
+#define CONFIG_SIGNATURE_CHECK_IMAGE
+
+#define CONFIG_SYS_CACHELINE_SIZE		32
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/rda8810e.h b/include/configs/rda8810e.h
new file mode 100644
index 0000000000..998739f9fa
--- /dev/null
+++ b/include/configs/rda8810e.h
@@ -0,0 +1,28 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/rda_config_defaults.h>
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_RDA8810E
+/* #define CONFIG_RDA_FPGA */
+
+/*
+ * Flash & Environment
+ */
+/* #define CONFIG_NAND_RDA_DMA */
+#define CONFIG_NAND_RDA_V2		/* V2 for rda8810e, rda8820 */
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+
+#define NAND_IO_RECONFIG_WORKROUND
+
+#ifdef _TGT_AP_HW_TEST_ENABLE
+/* force to run hardware test when pdl2 is running */
+//#define CONFIG_PDL_FORCE_HW_TEST
+/* test list */
+#define CONFIG_VPU_TEST
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/rda8810h.h b/include/configs/rda8810h.h
new file mode 100644
index 0000000000..65121133fc
--- /dev/null
+++ b/include/configs/rda8810h.h
@@ -0,0 +1,40 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/rda_config_defaults.h>
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_RDA8810H
+#define CONFIG_RDA_FPGA
+
+/*
+ * Flash & Environment
+ */
+/* #define CONFIG_NAND_RDA_DMA */
+#define CONFIG_NAND_RDA_V3
+#define CONFIG_SYS_NAND_MAX_CHIPS	4
+
+#define NAND_IO_RECONFIG_WORKROUND
+
+/* Enable RDA signed bootloader:*/
+/* #define CONFIG_SIGNATURE_CHECK_IMAGE */
+
+#ifdef _TGT_AP_HW_TEST_ENABLE
+/* force to run hardware test when pdl2 is running */
+//#define CONFIG_PDL_FORCE_HW_TEST
+/* test list */
+#define CONFIG_VPU_TEST
+/* #define CONFIG_DDR_TEST */
+/* #define CONFIG_TIMER_TEST */
+/* #define CONFIG_UART_TEST */
+/* #define CONFIG_GIC_TEST */
+/* #define CONFIG_CACHE_TEST */
+/* #define CONFIG_MIPI_LOOP_TEST */
+/* #define CONFIG_I2C_TEST */
+#endif
+
+#define CONFIG_SYS_CACHELINE_SIZE		64
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/rda8820.h b/include/configs/rda8820.h
new file mode 100644
index 0000000000..e9c2e2ad42
--- /dev/null
+++ b/include/configs/rda8820.h
@@ -0,0 +1,19 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/rda_config_defaults.h>
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_RDA8820
+#define CONFIG_RDA_FPGA
+
+/*
+ * Flash & Environment
+ */
+/* #define CONFIG_NAND_RDA_DMA */
+#define CONFIG_NAND_RDA_V2		/* V2 for rda8810e, rda8820 */
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/rda8850.h b/include/configs/rda8850.h
new file mode 100644
index 0000000000..3e44ff658c
--- /dev/null
+++ b/include/configs/rda8850.h
@@ -0,0 +1,19 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/rda_config_defaults.h>
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_RDA8850
+/* #define CONFIG_RDA_FPGA */
+
+/*
+ * Flash & Environment
+ */
+/* #define CONFIG_NAND_RDA_DMA */
+#define CONFIG_NAND_RDA_V1		/* V1 for rda8810, rda8850 */
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/rda8850e.h b/include/configs/rda8850e.h
new file mode 100644
index 0000000000..7f628e0ef7
--- /dev/null
+++ b/include/configs/rda8850e.h
@@ -0,0 +1,37 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/rda_config_defaults.h>
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_RDA8850E
+/*#define CONFIG_RDA_FPGA*/
+
+/* Enable RDA signed bootloader:*/
+/* #define CONFIG_SIGNATURE_CHECK_IMAGE */
+
+/*
+ * Flash & Environment
+ */
+/* #define CONFIG_NAND_RDA_DMA */
+#define CONFIG_NAND_RDA_V3		/* V3 for rda8850e*/
+#define CONFIG_SYS_NAND_MAX_CHIPS	4
+
+#define CONFIG_SYS_CACHELINE_SIZE		64
+
+#ifdef _TGT_AP_HW_TEST_ENABLE
+#define CONFIG_VPU_TEST
+/* #define CONFIG_DDR_TEST */
+/* #define CONFIG_TIMER_TEST */
+/* #define CONFIG_UART_TEST */
+/* #define CONFIG_GIC_TEST */
+/* #define CONFIG_CACHE_TEST */
+/* #define CONFIG_MIPI_LOOP_TEST */
+/* #define CONFIG_I2C_TEST */
+#endif
+
+#define CONFIG_USB_ACM_TWO_CHANS 1
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/rda_config_defaults.h b/include/configs/rda_config_defaults.h
new file mode 100644
index 0000000000..84cc9bf308
--- /dev/null
+++ b/include/configs/rda_config_defaults.h
@@ -0,0 +1,411 @@
+#ifndef __RDA_CONFIG_H__
+#define __RDA_CONFIG_H__
+
+#include <rda/tgt_ap_board_config.h>
+#include <rda/tgt_ap_clock_config.h>
+#define MEM_SIZE			_TGT_AP_OS_MEM_SIZE
+
+/*
+ * Board
+ */
+#define CONFIG_RDA_MUX_CONFIG		1
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_ARMV7
+#define CONFIG_SYS_HZ_CLOCK		2000000       /* 2M */
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE		0x80008000
+/* #define CONFIG_SYS_ICACHE_OFF */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_NEON_OFF */
+
+/* Display CPU and Board Info */
+#define CONFIG_DISPLAY_CPUINFO 		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN		(0x10000 + 16*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1			(0x80000000) /* DRAM Start */
+#define PHYS_SDRAM_1_SIZE		((MEM_SIZE) << 20)
+
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x00800000)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END 		(PHYS_SDRAM_1 + 0x00800000 + 16*1024*1024)
+
+/* spl need 20k bytes for nand one page data load (max size is 16k page size) */
+#define CONFIG_SPL_NAND_MIDDLE_DATA_BUFFER	(PHYS_SDRAM_1 + 0x01000000)
+
+#define CONFIG_NR_DRAM_BANKS		1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE		(256*1024) /* regular stack */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_BAUDRATE			921600 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE 	{ 9600, 38400, 115200, 921600 }
+
+/*
+ * SD/MMC
+ */
+#define CONFIG_MMC
+#define CONFIG_EFI_PARTITION
+#define CONFIG_DOS_PARTITION
+/*#define CONFIG_RDA_MMC_LEGACY*/
+#define CONFIG_GENERIC_MMC
+#define CONFIG_RDA_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+/*
+ * ROM in U0B chips cannot provide information on the booting media, whereas
+ * SPL and U-BOOT must know the media type. The macro, CONFIG_SDMMC_BOOT,
+ * is introduced to tell SPL and U-BOOT that this is a SDMMC boot.
+ * The macro will be obsoleted for future chips, after ROM is updated to
+ * provide such information.
+ */
+/*#define CONFIG_SDMMC_BOOT*/
+
+#ifdef CONFIG_SDMMC_BOOT /* sdcard */
+#define CONFIG_MMC_DEV_NUM	0
+#define CONFIG_MMC_DEV_NAME	"mmc0"
+#else /* emmc */
+#define CONFIG_MMC_DEV_NUM	1
+#define CONFIG_MMC_DEV_NAME	"mmc1"
+#endif
+
+/*
+ * Misc drivers
+ */
+#define CONFIG_RDA_FACTORY	1
+#define CONFIG_RDA_PRDINFO	1
+#define CONFIG_CMD_PRDINFO	1
+
+/*
+ * I2C Configuration
+ */
+
+/*
+ * Flash & Environment
+ */
+#define CONFIG_NAND_RDA
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_PAGE_2K
+
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#define CONFIG_SYS_NAND_BASE		(PHYS_SDRAM_1 + 0x00800000)
+
+/*
+ * Console configuration
+ */
+#define CONFIG_SYS_PROMPT		"RDA > " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE		1024 /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */
+#define CONFIG_SYS_LOAD_ADDR		(PHYS_SDRAM_1 + 0x02000000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/*
+ * USB Configuration
+ */
+/*
+#define CONFIG_MUSB_HCD	1
+*/
+#define CONFIG_MUSB_UDC	1
+#define CONFIG_USB_RDA
+
+#ifdef CONFIG_MUSB_HCD
+#define MUSB_NO_MULTIPOINT
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_FAT_WRITE
+#endif
+/*
+ *USB Gadget Configuration
+ */
+#ifdef CONFIG_MUSB_UDC
+#define CONFIG_RDA_USB_SERIAL
+#define CONFIG_USB_DEVICE
+#define CONFIG_USBD_HS
+#endif
+
+/*
+ * U-BOOT only configurations
+ */
+#ifndef CONFIG_SPL_BUILD
+
+#ifdef UBIFS_SYSTEM_IMAGE
+#define CONFIG_UBIFS_SYSTEM_IMAGE	1
+#endif
+
+#ifdef UBIFS_USER_IMAGES
+#define CONFIG_UBIFS_USER_IMAGES	1
+#endif
+
+#ifdef EXTFS_SYSTEM_IMAGE
+#define CONFIG_EXTFS_SYSTEM_IMAGE	1
+#endif
+
+#ifdef EXTFS_USER_IMAGES
+#define CONFIG_EXTFS_USER_IMAGES	1
+#endif
+/*#define CONFIG_SYS_NAND_BASE_LIST	{ (PHYS_SDRAM_1 + 0x00800000), } */
+
+/*
+ * U-boot USB Configuration
+ */
+
+#ifdef CONFIG_MUSB_UDC
+#define CONFIG_USB_FASTBOOT
+#define CONFIG_MUSB_DMA
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_CMD_PDL2
+#define SCRATCH_ADDR			(PHYS_SDRAM_1 + 0x02000000)	/* leave 32M for boot and test */
+#define FB_DOWNLOAD_BUF_SIZE		(PHYS_SDRAM_1_SIZE - 0x02000000 - 0x800000)	/* 216M */
+#endif
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#include <asm/arch/mtdparts_def.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_HWFLOW
+
+/* modem commands */
+#define CONFIG_CMD_MDCOM
+
+#ifdef CONFIG_NAND_RDA
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+/*
+#define CONFIG_MTD_DEBUG
+#define CONFIG_MTD_DEBUG_VERBOSE 3
+*/
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_YAFFS
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_SOURCE
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_RBTREE
+
+/*#define CONFIG_YAFFS2*/
+#define MTDIDS_DEFAULT			"nand0=rda_nand"
+#define MTDPARTS_DEFAULT		"mtdparts=rda_nand:"MTDPARTS_DEF
+#define MTDPARTS_KERNEL_DEFAULT		"mtdparts=rda_nand:"MTDPARTS_KERNEL_DEF
+#endif
+
+/*
+ * U-BOOT library
+ */
+#define CONFIG_USE_ARCH_MEMCPY		1
+/*
+ * communication code between modem and ap
+ */
+#define CONFIG_MDCOM
+
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#undef CONFIG_CMD_DNS
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_RARP
+#undef CONFIG_CMD_SNTP
+
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_SF
+#undef CONFIG_CMD_SAVEENV
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_CONSOLE
+
+#undef CONFIG_BOOTM_NETBSD
+#undef CONFIG_BOOTM_RTEMS
+
+#define CONFIG_LZO
+
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR		(PHYS_SDRAM_1 + 0x100)
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+// #define CONFIG_SERIAL_TAG
+
+/* The delay to check whether to stop auto boot */
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"script_addr=81000000\0" \
+	"modem_addr=82000000\0" \
+	"factorydata_addr=83000000\0" \
+	"kernel_addr=84000000\0" \
+	"initrd_addr=85000000\0" \
+	"boot_device=mmc\0" \
+	""
+
+#define CONFIG_BOOTARGS			\
+	"mem="MK_STR(MEM_SIZE)"M "		\
+	"console=ttyS0," MK_STR(CONFIG_BAUDRATE) " "	\
+	"root=/dev/ram rw "		\
+	"rdinit=/init"
+
+#define CONFIG_BOOTCOMMAND		\
+	"mux_config; "		\
+	"mmc dev 0; "		\
+	"ext2load mmc 0:1 ${script_addr} boot.scr && source ${script_addr};" \
+	"echo Running boot script failed;"
+
+#endif /* !CONFIG_SPL_BUILD */
+
+#if !defined(CONFIG_USE_NAND) && \
+	!defined(CONFIG_USE_NOR) && \
+	!defined(CONFIG_USE_SPIFLASH)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE			(16 << 10)
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ENV
+#endif
+
+/* additions for new relocation code, must added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Defines for SPL
+ */
+#define CONFIG_SPL
+#define CONFIG_SYS_SRAM_BASE		0x00100000
+#define CONFIG_SYS_SRAM_SIZE		0x00010000  /* 64k */
+#define CONFIG_SPL_TEXT_BASE		0x00100100  /* first 4k leave for boot_rom bss */
+/*
+ * SPL Build for thumb code
+ */
+#define CONFIG_SPL_THUMB_BUILD		1
+/*
+ the spl code should be 48 KB,and must be aligned to page offset
+*/
+/* In nand driver V3,
+ the first page of nand is nand parameter,
+ it is invisible to uplayer except for nand dump command,
+ so we also think that spl offset is 0.
+ need add one page offset when read and write bootloader in nand driver v3.
+ In nand driver V1,
+ spl offset must be 0.
+*/
+#define NAND_START_ADDR  0
+#define CONFIG_SPL_NAND_OFFS		(NAND_START_ADDR)
+#define CONFIG_SPL_MAX_SIZE		49152
+
+#define CONFIG_UIMAGEHDR_SIZE		0x40
+
+#ifdef _TGT_AP_DDR_AUTO_CALI_ENABLE
+#define CONFIG_DDR_CAL_VAL_SIZE	0x10
+#define CONFIG_SPL_CODE_MAX_SIZE		48880	//CONFIG_SPL_MAX_SIZE -  CONFIG_DDR_CAL_VAL_SIZE - 0x100
+#else
+#define CONFIG_DDR_CAL_VAL_SIZE	0
+#define CONFIG_SPL_CODE_MAX_SIZE		48896	//CONFIG_SPL_MAX_SIZE -  0x100
+#endif
+
+#define CONFIG_SPL_BOARD_INFO_SIZE		512
+#define CONFIG_SPL_BOARD_INFO_ADDR		(CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CONFIG_SPL_BOARD_INFO_SIZE)
+
+#define CONFIG_TRAP_SIZE		0x00c0
+#define CONFIG_SPL_LOAD_ADDRESS 	(CONFIG_SYS_SRAM_BASE + CONFIG_TRAP_SIZE)
+
+#define CONFIG_SPL_STACK		CONFIG_SPL_BOARD_INFO_ADDR
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+#define CONFIG_SPL_IMAGE_SUPPORT
+
+#define CONFIG_MTD_PTBL_OFFS		(CONFIG_SPL_NAND_OFFS + CONFIG_SPL_MAX_SIZE)
+#define CONFIG_MTD_PTBL_SIZE		((SPL_APPENDING_TO-CONFIG_SPL_MAX_SIZE/1024)*1024)
+#define CONFIG_SYS_BOOTLOADER_MAX_SIZE	(1024*1024)
+
+#ifndef CONFIG_RDA_PDL
+/* Check uimage*/
+#define CONFIG_SPL_CHECK_IMAGE
+
+/* NAND boot */
+#define CONFIG_SPL_NAND_LOAD
+/* EMMC boot */
+#define CONFIG_SPL_EMMC_LOAD
+/* XMODME boot */
+#define CONFIG_SPL_XMODEM_LOAD
+
+/* XMODEM load configs */
+#ifdef CONFIG_SPL_XMODEM_LOAD
+#define CONFIG_SYS_XMODEM_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_XMODEM_U_BOOT_DST 	(CONFIG_SYS_TEXT_BASE - 64)
+#endif
+
+/*
+ * NAND load configs
+*/
+#ifdef CONFIG_SPL_NAND_LOAD
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_SIMPLE
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 	(CONFIG_SPL_NAND_OFFS + CONFIG_SPL_MAX_SIZE + CONFIG_MTD_PTBL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 	(CONFIG_SYS_BOOTLOADER_MAX_SIZE - CONFIG_MTD_PTBL_SIZE - CONFIG_SPL_MAX_SIZE - CONFIG_SPL_NAND_OFFS)
+#define CONFIG_SYS_NAND_U_BOOT_DST 	(CONFIG_SYS_TEXT_BASE - 64)
+#endif /* CONFIG_SPL_NAND_LOAD */
+
+/*
+ * EMMC load configs
+ */
+#ifdef CONFIG_SPL_EMMC_LOAD
+#define CONFIG_SPL_EMMC_SUPPORT
+
+#define CONFIG_SPL_EMMC_OFFS		0x20000
+
+#define CONFIG_SYS_EMMC_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_EMMC_U_BOOT_OFFS 	(CONFIG_SPL_EMMC_OFFS + CONFIG_SPL_MAX_SIZE + CONFIG_MTD_PTBL_SIZE)
+#define CONFIG_SYS_EMMC_U_BOOT_SIZE 	(CONFIG_SYS_BOOTLOADER_MAX_SIZE - CONFIG_MTD_PTBL_SIZE - CONFIG_SPL_MAX_SIZE - CONFIG_SPL_EMMC_OFFS)
+#define CONFIG_SYS_EMMC_U_BOOT_DST 	(CONFIG_SYS_TEXT_BASE - 64)
+#endif /* CONFIG_SPL_EMMC_LOAD */
+
+#else /* CONFIG_RDA_PDL */
+
+#define CONFIG_SPL_USB_SUPPORT
+#define CONFIG_SPL_MUSB_UDC_SUPPORT
+#define CONFIG_SPL_RDA_PDL
+
+#endif /* CONFIG_RDA_PDL */
+
+#define CONIFG_DDR_CAL_VAL_FLAG	0xA1B2
+#define CONFIG_DDR_CAL_SEC_OFFS	CONFIG_SPL_MAX_SIZE - CONFIG_DDR_CAL_VAL_SIZE - 0x100
+#endif /* __RDA_CONFIG_H__ */
diff --git a/include/configs/rdaarm926ejs.h b/include/configs/rdaarm926ejs.h
new file mode 100644
index 0000000000..aac6b05f29
--- /dev/null
+++ b/include/configs/rdaarm926ejs.h
@@ -0,0 +1,218 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_RDAARM926EJS
+#define CONFIG_ARM926EJS		/* arm926ejs CPU core */
+#define CONFIG_SYS_HZ_CLOCK		16384
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE		0x84008000
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1		0x84000000 /* DDR Start */
+#define PHYS_SDRAM_1_SIZE	(64 << 20) /* SDRAM size 32MB */
+#define CONFIG_MAX_RAM_BANK_SIZE (64 << 20) /* max size from RDA */
+
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x00800000)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END 	(PHYS_SDRAM_1 + 0x00800000 + 16*1024*1024)
+
+#define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE	(256*1024) /* regular stack */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_BAUDRATE		921600		/* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE 	{ 9600, 38400, 115200, 921600 }
+
+/*
+ * SD/MMC
+ */
+#define CONFIG_MMC
+#define CONFIG_DOS_PARTITION
+/*#define CONFIG_RDA_MMC_LEGACY*/
+#define CONFIG_GENERIC_MMC
+#define CONFIG_RDA_MMC
+
+/*
+ * I2C Configuration
+ */
+
+/*
+ * Flash & Environment
+ */
+#define CONFIG_NAND_RDA
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+/*#define CONFIG_SYS_NAND_HW_ECC*/
+/*#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST*/
+#define CONFIG_SYS_NAND_PAGE_2K
+
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_NAND_BASE		0x01a26000 
+/*#define CONFIG_SYS_NAND_BASE_LIST	{ 0x01a26000, } */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+
+/*
+ * Network & Ethernet Configuration
+ */
+
+/*
+ *USB Gadget Configuration
+ */
+
+#define CONFIG_USB_RDA
+#define CONFIG_MUSB_UDC
+/*
+#define CONFIG_USB_TTY
+*/
+#define CONFIG_USB_DEVICE
+#define CONFIG_USBD_HS
+#define CONFIG_USB_FASTBOOT
+#define CONFIG_CMD_FASTBOOT
+/*
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_RDA
+#define CONFIG_USB_FASTBOOT
+#define CONFIG_CMD_FASTBOOT
+*/
+#define SCRATCH_ADDR	0x86000000
+#define FB_DOWNLOAD_BUF_SIZE	(100*1024*1024)
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_BOOTFILE		"uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT	"RDA > " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/*
+ * Environment settings
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"usbtty=cdc_acm\0"
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS		\
+	"mem=64M console=ttyS0,115200n8 root=/dev/ram rw rdinit=/linuxrc init=/init "
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MMC
+
+#ifdef CONFIG_NAND_RDA
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_YAFFS
+/*#define CONFIG_CMD_UBI*/
+/*#define CONFIG_CMD_UBIFS*/ 
+#define CONFIG_YAFFS2 
+#define CONFIG_RBTREE
+#define MTDIDS_DEFAULT      "nand0=rda_nand"
+#define MTDPARTS_DEFAULT    "mtdparts=rda_nand:128k@0(preloader)," \
+                            "256k(config)," \
+                            "128k(u-boot_env)," \
+                            "512k(test_image)," \
+                            "1M(u-boot)," \
+                            "6M(kernel)," \
+                            "504M(system)," \
+                            "-(data)"
+#endif
+
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#undef CONFIG_CMD_DNS
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_RARP
+#undef CONFIG_CMD_SNTP
+
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_SF
+#undef CONFIG_CMD_SAVEENV
+
+#if !defined(CONFIG_USE_NAND) && \
+	!defined(CONFIG_USE_NOR) && \
+	!defined(CONFIG_USE_SPIFLASH)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE		(16 << 10)
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ENV
+#endif
+
+/* additions for new relocation code, must added to all boards */
+#define CONFIG_SYS_SDRAM_BASE	0x84000000
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
+					GENERATED_GBL_DATA_SIZE)
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SYS_SRAM_BASE	0x01c00000
+#define CONFIG_SYS_SRAM_SIZE	0x00008000  /* 32k */
+#define CONFIG_SPL_TEXT_BASE	0x01c01000  /* first 4k leave for boot_rom bss */
+#define CONFIG_SPL_MAX_SIZE		(20 * 1024)	/* 8 KB for stack */
+#define CONFIG_SPL_STACK		(CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE)
+
+#define CONFIG_SPL_BSS_START_ADDR	CONFIG_SYS_SRAM_BASE  /* reuse boot_rom bss */
+#define CONFIG_SPL_BSS_MAX_SIZE	0x1000		/* 4 KB */
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+/*#define CONFIG_SPL_LIBDISK_SUPPORT*/
+/*#define CONFIG_SPL_I2C_SUPPORT*/
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+/*#define CONFIG_SPL_MMC_SUPPORT*/
+/*#define CONFIG_SPL_FAT_SUPPORT*/
+#define CONFIG_SPL_SERIAL_SUPPORT
+/*#define CONFIG_SPL_NAND_SUPPORT*/
+/*#define CONFIG_SPL_POWER_SUPPORT*/
+/*#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"*/
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index 56b5547fd2..e133a17259 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -63,9 +63,10 @@
 #define CONFIG_BAUDRATE			115200
 
 /* MMC */
-#define CONFIG_GENERIC_MMC		1
-#define CONFIG_MMC			1
-#define CONFIG_S5P_MMC			1
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_S5P_SDHCI
 
 /* PWM */
 #define CONFIG_PWM			1
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index 13012756ab..00db374182 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -66,9 +66,10 @@
 #define CONFIG_BAUDRATE		115200
 
 /* MMC */
-#define CONFIG_GENERIC_MMC	1
-#define CONFIG_MMC		1
-#define CONFIG_S5P_MMC		1
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_S5P_SDHCI
 
 /* PWM */
 #define CONFIG_PWM			1
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index ae075e786e..46d42281b7 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -25,6 +25,14 @@
 #define __CONFIG_H
 
 #include <asm/sizes.h>
+
+/* LP0 suspend / resume */
+#define CONFIG_TEGRA2_LP0
+#define CONFIG_AES
+#define CONFIG_TEGRA_PMU
+#define CONFIG_TPS6586X_POWER
+#define CONFIG_TEGRA_CLOCK_SCALING
+
 #include "tegra2-common.h"
 
 /* Enable fdt support for Seaboard. Flash the image in u-boot-dtb.bin */
@@ -92,4 +100,12 @@
 #define CONFIG_USB_STORAGE
 #define CONFIG_CMD_USB
 
+/* Enable keyboard */
+#define CONFIG_TEGRA2_KEYBOARD
+#define CONFIG_KEYBOARD
+
+#undef TEGRA2_DEVICE_SETTINGS
+#define TEGRA2_DEVICE_SETTINGS	"stdin=serial,tegra-kbc\0" \
+					"stdout=serial\0" \
+					"stderr=serial\0"
 #endif /* __CONFIG_H */
diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h
index 73d2a87596..708bff7bb7 100644
--- a/include/configs/sh7757lcr.h
+++ b/include/configs/sh7757lcr.h
@@ -41,7 +41,6 @@
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_NFS
-#define CONFIG_CMD_DFL
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_RUN
diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h
index 1e71bcc3ef..9c32bfc58b 100644
--- a/include/configs/sh7785lcr.h
+++ b/include/configs/sh7785lcr.h
@@ -37,7 +37,6 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_NFS
-#define CONFIG_CMD_DFL
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_RUN
 #define CONFIG_CMD_SAVEENV
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
index 9659f9ebd9..0f63040d25 100644
--- a/include/configs/smdk5250.h
+++ b/include/configs/smdk5250.h
@@ -78,7 +78,8 @@
 /* SD/MMC configuration */
 #define CONFIG_GENERIC_MMC
 #define CONFIG_MMC
-#define CONFIG_S5P_MMC
+#define CONFIG_SDHCI
+#define CONFIG_S5P_SDHCI
 
 #define CONFIG_BOARD_EARLY_INIT_F
 
diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h
index 93c25da1cf..702134bda3 100644
--- a/include/configs/smdkv310.h
+++ b/include/configs/smdkv310.h
@@ -68,9 +68,10 @@
 #define EXYNOS4_DEFAULT_UART_OFFSET	0x010000
 
 /* SD/MMC configuration */
-#define CONFIG_GENERIC_MMC		1
-#define CONFIG_MMC			1
-#define CONFIG_S5P_MMC			1
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_S5P_SDHCI
 
 /* PWM */
 #define CONFIG_PWM			1
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index 5fef8cce80..ab1b33209e 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -41,7 +41,7 @@
 
 /* I2C driver configuration */
 #define CONFIG_HARD_I2C
-#define CONFIG_SPEAR_I2C
+#define CONFIG_DW_I2C
 #define CONFIG_SYS_I2C_SPEED			400000
 #define CONFIG_SYS_I2C_SLAVE			0x02
 
@@ -196,7 +196,6 @@
 #define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
 #define CONFIG_SYS_LOAD_ADDR			0x00800000
 #define CONFIG_SYS_CONSOLE_INFO_QUIET		1
-#define CONFIG_SYS_64BIT_VSPRINTF		1
 
 #define CONFIG_EXTRA_ENV_SETTINGS		CONFIG_EXTRA_ENV_USBTTY
 
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index 4c4321d2ff..3fc2c44349 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -146,7 +146,6 @@
 
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
 							/* NAND devices */
-#define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
 
 #define CONFIG_AUTO_COMPLETE
 
@@ -258,7 +257,7 @@
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
 
 #define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
-#define CONFIG_SPL_MAX_SIZE		(45 << 10)	/* 45 K */
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
 
 #define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h
index 837f859c7c..068ce8855f 100644
--- a/include/configs/tegra2-common.h
+++ b/include/configs/tegra2-common.h
@@ -26,6 +26,14 @@
 #include <asm/sizes.h>
 
 /*
+ * QUOTE(m) will evaluate to a string version of the value of the macro m
+ * passed in.  The extra level of indirection here is to first evaluate the
+ * macro m before applying the quoting operator.
+ */
+#define QUOTE_(m)       #m
+#define QUOTE(m)        QUOTE_(m)
+
+/*
  * High Level Configuration Options
  */
 #define CONFIG_ARMCORTEXA9		/* This is an ARM V7 CPU core */
@@ -50,6 +58,15 @@
 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
 #define CONFIG_OF_LIBFDT		/* enable passing of devicetree */
 
+#ifdef CONFIG_TEGRA2_LP0
+#define TEGRA_LP0_ADDR			0x1C406000
+#define TEGRA_LP0_SIZE			0x2000
+#define TEGRA_LP0_VEC \
+	"lp0_vec=" QUOTE(TEGRA_LP0_SIZE) "@" QUOTE(TEGRA_LP0_ADDR) " "
+#else
+#define TEGRA_LP0_VEC
+#endif
+
 /* Environment */
 #define CONFIG_ENV_SIZE			0x2000	/* Total Size Environment */
 
@@ -115,11 +132,18 @@
 
 #define CONFIG_SYS_NO_FLASH
 
-/* Environment information */
+/* Environment information, boards can override if required */
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define TEGRA2_DEVICE_SETTINGS	"stdin=serial\0" \
+					"stdout=serial\0" \
+					"stderr=serial\0"
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"console=ttyS0,115200n8\0" \
 	"mem=" TEGRA2_SYSMEM "\0" \
 	"smpflag=smp\0" \
+	TEGRA2_DEVICE_SETTINGS
 
 #define CONFIG_LOADADDR		0x408000	/* def. location for kernel */
 #define CONFIG_BOOTDELAY	2		/* -1 to disable auto boot */
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 10f11d9579..ef6510e67d 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -53,7 +53,6 @@
 
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
 #define CONFIG_REVISION_TAG
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_SKIP_LOWLEVEL_INIT
@@ -74,7 +73,8 @@
 /* MMC */
 #define CONFIG_GENERIC_MMC
 #define CONFIG_MMC
-#define CONFIG_S5P_MMC
+#define CONFIG_S5P_SDHCI
+#define CONFIG_SDHCI
 
 /* PWM */
 #define CONFIG_PWM
@@ -174,9 +174,9 @@
 /* TRATS has 2 banks of DRAM */
 #define CONFIG_NR_DRAM_BANKS	2
 #define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE	/* LDDDR2 DMC 0 */
-#define PHYS_SDRAM_1_SIZE	(256 << 20)		/* 256 MB in CS 0 */
+#define PHYS_SDRAM_1_SIZE	(512 << 20)		/* 512 MB in CS 0 */
 #define PHYS_SDRAM_2		0x50000000		/* LPDDR2 DMC 1 */
-#define PHYS_SDRAM_2_SIZE	(256 << 20)		/* 256 MB in CS 0 */
+#define PHYS_SDRAM_2_SIZE	(512 << 20)		/* 512 MB in CS 0 */
 
 #define CONFIG_SYS_MEM_TOP_HIDE		(1 << 20)	/* ram console */
 
@@ -208,10 +208,18 @@
 
 #define CONFIG_PMIC
 #define CONFIG_PMIC_I2C
-#define CONFIG_PMIC_MAX8998
+#define CONFIG_PMIC_MAX8997
 
 #define CONFIG_USB_GADGET
 #define CONFIG_USB_GADGET_S3C_UDC_OTG
 #define CONFIG_USB_GADGET_DUALSPEED
 
+/* LCD */
+#define CONFIG_EXYNOS_FB
+#define CONFIG_LCD
+#define CONFIG_FB_ADDR		0x52504000
+#define CONFIG_S6E8AX0
+#define CONFIG_EXYNOS_MIPI_DSIM
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(1280 * 720 * 4)
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index 801a24fd88..9955fca476 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -278,6 +278,7 @@
 #define CONFIG_SPL
 #define CONFIG_SPL_NAND_SIMPLE
 
+#define CONFIG_SPL_BOARD_INIT
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #define CONFIG_SPL_I2C_SUPPORT
@@ -293,7 +294,7 @@
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
 
 #define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
-#define CONFIG_SPL_MAX_SIZE		0xB400  /* 45 K */
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
 
 #define CONFIG_SPL_BSS_START_ADDR	0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
diff --git a/include/configs/tx25.h b/include/configs/tx25.h
index 87bd8a6756..3dfafa5077 100644
--- a/include/configs/tx25.h
+++ b/include/configs/tx25.h
@@ -117,8 +117,6 @@
 #define CONFIG_MXC_NAND_HWECC
 #define CONFIG_SYS_NAND_LARGEPAGE
 
-#define CONFIG_SYS_64BIT_VSPRINTF
-
 /* U-Boot general configuration */
 #define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size  */
diff --git a/include/configs/u8500_href.h b/include/configs/u8500_href.h
index 4747fbd351..95028de059 100644
--- a/include/configs/u8500_href.h
+++ b/include/configs/u8500_href.h
@@ -95,7 +95,6 @@
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EMMC
 #define CONFIG_CMD_SOURCE
 #define CONFIG_CMD_I2C
 
diff --git a/include/configs/zeus.h b/include/configs/zeus.h
index 63279b01ce..2556e3b3ef 100644
--- a/include/configs/zeus.h
+++ b/include/configs/zeus.h
@@ -78,7 +78,6 @@
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_LOG
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_NFS
diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h
index 599d5bb42a..d7ce6c64de 100644
--- a/include/configs/zmx25.h
+++ b/include/configs/zmx25.h
@@ -93,8 +93,6 @@
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_CACHE
 
-#define CONFIG_SYS_64BIT_VSPRINTF
-
 /*
  * Additional command
  */
diff --git a/include/dialog_pmic.h b/include/dialog_pmic.h
new file mode 100644
index 0000000000..8d43585e24
--- /dev/null
+++ b/include/dialog_pmic.h
@@ -0,0 +1,187 @@
+/*
+ * da9053 register declarations.
+ *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __DIALOG_PMIC_H__
+#define __DIALOG_PMIC_H__
+
+enum {
+	DA9053_PAGECON0_REG = 0,
+	DA9053_STATUSA_REG,
+	DA9053_STATUSB_REG,
+	DA9053_STATUSC_REG,
+	DA9053_STATUSD_REG,
+	DA9053_EVENTA_REG,
+	DA9053_EVENTB_REG,
+	DA9053_EVENTC_REG,
+	DA9053_EVENTD_REG,
+	DA9053_FAULTLOG_REG,
+	DA9053_IRQMASKA_REG,
+	DA9053_IRQMASKB_REG,
+	DA9053_IRQMASKC_REG,
+	DA9053_IRQMASKD_REG,
+	DA9053_CONTROLA_REG,
+	DA9053_CONTROLB_REG,
+	DA9053_CONTROLC_REG,
+	DA9053_CONTROLD_REG,
+	DA9053_PDDIS_REG,
+	DA9053_INTERFACE_REG,
+	DA9053_RESET_REG,
+	DA9053_GPIO0001_REG,
+	DA9053_GPIO0203_REG,
+	DA9053_GPIO0405_REG,
+	DA9053_GPIO0607_REG,
+	DA9053_GPIO0809_REG,
+	DA9053_GPIO1011_REG,
+	DA9053_GPIO1213_REG,
+	DA9053_GPIO1415_REG,
+	DA9053_ID01_REG,
+	DA9053_ID23_REG,
+	DA9053_ID45_REG,
+	DA9053_ID67_REG,
+	DA9053_ID89_REG,
+	DA9053_ID1011_REG,
+	DA9053_ID1213_REG,
+	DA9053_ID1415_REG,
+	DA9053_ID1617_REG,
+	DA9053_ID1819_REG,
+	DA9053_ID2021_REG,
+	DA9053_SEQSTATUS_REG,
+	DA9053_SEQA_REG,
+	DA9053_SEQB_REG,
+	DA9053_SEQTIMER_REG,
+	DA9053_BUCKA_REG,
+	DA9053_BUCKB_REG,
+	DA9053_BUCKCORE_REG,
+	DA9053_BUCKPRO_REG,
+	DA9053_BUCKMEM_REG,
+	DA9053_BUCKPERI_REG,
+	DA9053_LDO1_REG,
+	DA9053_LDO2_REG,
+	DA9053_LDO3_REG,
+	DA9053_LDO4_REG,
+	DA9053_LDO5_REG,
+	DA9053_LDO6_REG,
+	DA9053_LDO7_REG,
+	DA9053_LDO8_REG,
+	DA9053_LDO9_REG,
+	DA9053_LDO10_REG,
+	DA9053_SUPPLY_REG,
+	DA9053_PULLDOWN_REG,
+	DA9053_CHGBUCK_REG,
+	DA9053_WAITCONT_REG,
+	DA9053_ISET_REG,
+	DA9053_BATCHG_REG,
+	DA9053_CHGCONT_REG,
+	DA9053_INPUTCONT_REG,
+	DA9053_CHGTIME_REG,
+	DA9053_BBATCONT_REG,
+	DA9053_BOOST_REG,
+	DA9053_LEDCONT_REG,
+	DA9053_LEDMIN123_REG,
+	DA9053_LED1CONF_REG,
+	DA9053_LED2CONF_REG,
+	DA9053_LED3CONF_REG,
+	DA9053_LED1CONT_REG,
+	DA9053_LED2CONT_REG,
+	DA9053_LED3CONT_REG,
+	DA9053_LED4CONT_REG,
+	DA9053_LED5CONT_REG,
+	DA9053_ADCMAN_REG,
+	DA9053_ADCCONT_REG,
+	DA9053_ADCRESL_REG,
+	DA9053_ADCRESH_REG,
+	DA9053_VDDRES_REG,
+	DA9053_VDDMON_REG,
+	DA9053_ICHGAV_REG,
+	DA9053_ICHGTHD_REG,
+	DA9053_ICHGEND_REG,
+	DA9053_TBATRES_REG,
+	DA9053_TBATHIGHP_REG,
+	DA9053_TBATHIGHIN_REG,
+	DA9053_TBATLOW_REG,
+	DA9053_TOFFSET_REG,
+	DA9053_ADCIN4RES_REG,
+	DA9053_AUTO4HIGH_REG,
+	DA9053_AUTO4LOW_REG,
+	DA9053_ADCIN5RES_REG,
+	DA9053_AUTO5HIGH_REG,
+	DA9053_AUTO5LOW_REG,
+	DA9053_ADCIN6RES_REG,
+	DA9053_AUTO6HIGH_REG,
+	DA9053_AUTO6LOW_REG,
+	DA9053_TJUNCRES_REG,
+	DA9053_TSICONTA_REG,
+	DA9053_TSICONTB_REG,
+	DA9053_TSIXMSB_REG,
+	DA9053_TSIYMSB_REG,
+	DA9053_TSILSB_REG,
+	DA9053_TSIZMSB_REG,
+	DA9053_COUNTS_REG,
+	DA9053_COUNTMI_REG,
+	DA9053_COUNTH_REG,
+	DA9053_COUNTD_REG,
+	DA9053_COUNTMO_REG,
+	DA9053_COUNTY_REG,
+	DA9053_ALARMMI_REG,
+	DA9053_ALARMH_REG,
+	DA9053_ALARMD_REG,
+	DA9053_ALARMMO_REG,
+	DA9053_ALARMY_REG,
+	DA9053_SECONDA_REG,
+	DA9053_SECONDB_REG,
+	DA9053_SECONDC_REG,
+	DA9053_SECONDD_REG,
+	DA9053_PAGECON128_REG,
+	DA9053_CHIPID_REG,
+	DA9053_CONFIGID_REG,
+	DA9053_OTPCONT_REG,
+	DA9053_OSCTRIM_REG,
+	DA9053_GPID0_REG,
+	DA9053_GPID1_REG,
+	DA9053_GPID2_REG,
+	DA9053_GPID3_REG,
+	DA9053_GPID4_REG,
+	DA9053_GPID5_REG,
+	DA9053_GPID6_REG,
+	DA9053_GPID7_REG,
+	DA9053_GPID8_REG,
+	DA9053_GPID9_REG,
+	DIALOG_NUM_OF_REGS,
+};
+
+#define DA_BUCKCORE_VBCORE_1_250V		0x1E
+
+/* BUCKCORE REGISTER */
+#define DA9052_BUCKCORE_BCORECONF               (1 << 7)
+#define DA9052_BUCKCORE_BCOREEN                 (1 << 6)
+#define DA9052_BUCKCORE_VBCORE                  63
+
+/* SUPPLY REGISTER */
+#define DA9052_SUPPLY_VLOCK                     (1 << 7)
+#define DA9052_SUPPLY_VMEMSWEN                  (1 << 6)
+#define DA9052_SUPPLY_VPERISWEN                 (1 << 5)
+#define DA9052_SUPPLY_VLDO3GO                   (1 << 4)
+#define DA9052_SUPPLY_VLDO2GO                   (1 << 3)
+#define DA9052_SUPPLY_VBMEMGO                   (1 << 2)
+#define DA9052_SUPPLY_VBPROGO                   (1 << 1)
+#define DA9052_SUPPLY_VBCOREGO                  (1 << 0)
+
+#endif /* __DIALOG_PMIC_H__ */
diff --git a/include/fat.h b/include/fat.h
index 4c92442fd3..f1b4a0d97c 100644
--- a/include/fat.h
+++ b/include/fat.h
@@ -178,12 +178,12 @@ typedef struct dir_slot {
 typedef struct {
 	__u8	*fatbuf;	/* Current FAT buffer */
 	int	fatsize;	/* Size of FAT in bits */
-	__u16	fatlength;	/* Length of FAT in sectors */
+	__u32	fatlength;	/* Length of FAT in sectors */
 	__u16	fat_sect;	/* Starting sector of the FAT */
-	__u16	rootdir_sect;	/* Start sector of root directory */
+	__u32	rootdir_sect;	/* Start sector of root directory */
 	__u16	sect_size;	/* Size of sectors in bytes */
 	__u16	clust_size;	/* Size of clusters in sectors */
-	short	data_begin;	/* The sector of the first cluster, can be negative */
+	int	data_begin;	/* The sector of the first cluster, can be negative */
 	int	fatbufnum;	/* Used by get_fatent, init to -1 */
 } fsdata;
 
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 171c628485..fab577ed32 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -60,6 +60,9 @@ enum fdt_compat_id {
 	COMPAT_NVIDIA_TEGRA20_USB,	/* Tegra2 USB port */
 	COMPAT_NVIDIA_TEGRA20_I2C,	/* Tegra2 i2c */
 	COMPAT_NVIDIA_TEGRA20_DVC,	/* Tegra2 dvc (really just i2c) */
+	COMPAT_NVIDIA_TEGRA20_EMC,	/* Tegra2 memory controller */
+	COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra2 memory timing table */
+	COMPAT_NVIDIA_TEGRA20_KBC,	/* Tegra2 Keyboard */
 
 	COMPAT_COUNT,
 };
@@ -117,6 +120,23 @@ int fdtdec_next_compatible(const void *blob, int node,
 		enum fdt_compat_id id);
 
 /**
+ * Find the next compatible subnode for a peripheral.
+ *
+ * Do the first call with node set to the parent and depth = 0. This
+ * function will return the offset of the next compatible node. Next time
+ * you call this function, pass the node value returned last time, with
+ * depth unchanged, and the next node will be provided.
+ *
+ * @param blob		FDT blob to use
+ * @param node		Start node for search
+ * @param id		Compatible ID to look for (enum fdt_compat_id)
+ * @param depthp	Current depth (set to 0 before first call)
+ * @return offset of next compatible node, or -FDT_ERR_NOTFOUND if no more
+ */
+int fdtdec_next_compatible_subnode(const void *blob, int node,
+		enum fdt_compat_id id, int *depthp);
+
+/**
  * Look up an address property in a node and return it as an address.
  * The property must hold either one address with no trailing data or
  * one address with a length. This is only tested on 32-bit machines.
@@ -272,6 +292,25 @@ int fdtdec_get_int_array(const void *blob, int node, const char *prop_name,
 		u32 *array, int count);
 
 /**
+ * Look up a property in a node and return a pointer to its contents as a
+ * unsigned int array of given length. The property must have at least enough
+ * data for the array ('count' cells). It may have more, but this will be
+ * ignored. The data is not copied.
+ *
+ * Note that you must access elements of the array with fdt32_to_cpu(),
+ * since the elements will be big endian even on a little endian machine.
+ *
+ * @param blob		FDT blob
+ * @param node		node to examine
+ * @param prop_name	name of property to find
+ * @param count		number of array elements
+ * @return pointer to array if found, or NULL if the property is not
+ *		found or there is not enough data
+ */
+const u32 *fdtdec_locate_array(const void *blob, int node,
+			       const char *prop_name, int count);
+
+/**
  * Look up a boolean property in a node and return it.
  *
  * A boolean properly is true if present in the device tree and false if not
@@ -311,3 +350,35 @@ int fdtdec_decode_gpio(const void *blob, int node, const char *prop_name,
  * @return 0 if all ok or gpio was FDT_GPIO_NONE; -1 on error
  */
 int fdtdec_setup_gpio(struct fdt_gpio_state *gpio);
+
+/*
+ * Look up a property in a node and return its contents in a byte
+ * array of given length. The property must have at least enough data for
+ * the array (count bytes). It may have more, but this will be ignored.
+ *
+ * @param blob		FDT blob
+ * @param node		node to examine
+ * @param prop_name	name of property to find
+ * @param array		array to fill with data
+ * @param count		number of array elements
+ * @return 0 if ok, or -FDT_ERR_MISSING if the property is not found,
+ *		or -FDT_ERR_BADLAYOUT if not enough data
+ */
+int fdtdec_get_byte_array(const void *blob, int node, const char *prop_name,
+		u8 *array, int count);
+
+/**
+ * Look up a property in a node and return a pointer to its contents as a
+ * byte array of given length. The property must have at least enough data
+ * for the array (count bytes). It may have more, but this will be ignored.
+ * The data is not copied.
+ *
+ * @param blob		FDT blob
+ * @param node		node to examine
+ * @param prop_name	name of property to find
+ * @param count		number of array elements
+ * @return pointer to byte array if found, or NULL if the property is not
+ *		found or there is not enough data
+ */
+const u8 *fdtdec_locate_byte_array(const void *blob, int node,
+			     const char *prop_name, int count);
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 8418bf7f47..0e265584bd 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -34,12 +34,13 @@
 #define SYSCTL_INITA		0x08000000
 #define SYSCTL_TIMEOUT_MASK	0x000f0000
 #define SYSCTL_CLOCK_MASK	0x0000fff0
-#define SYSCTL_RSTA		0x01000000
 #define SYSCTL_CKEN		0x00000008
 #define SYSCTL_PEREN		0x00000004
 #define SYSCTL_HCKEN		0x00000002
 #define SYSCTL_IPGEN		0x00000001
 #define SYSCTL_RSTA		0x01000000
+#define SYSCTL_RSTC		0x02000000
+#define SYSCTL_RSTD		0x04000000
 
 #define IRQSTAT			0x0002e030
 #define IRQSTAT_DMAE		(0x10000000)
@@ -85,6 +86,7 @@
 #define IRQSTATEN_CC		(0x00000001)
 
 #define PRSSTAT			0x0002e024
+#define PRSSTAT_DAT0		(0x01000000)
 #define PRSSTAT_CLSL		(0x00800000)
 #define PRSSTAT_WPSPL		(0x00080000)
 #define PRSSTAT_CDPL		(0x00040000)
diff --git a/include/fsl_pmic.h b/include/fsl_pmic.h
index 742f2e19f9..64c1e2ef65 100644
--- a/include/fsl_pmic.h
+++ b/include/fsl_pmic.h
@@ -122,4 +122,15 @@ enum {
 /* Interrupt status 1 */
 #define RTCRSTI		(1 << 7)
 
+/* MC34708 Definitions */
+#define SWx_VOLT_MASK_MC34708	0x3F
+#define SWx_1_250V_MC34708	0x30
+#define SWx_1_300V_MC34708	0x34
+#define TIMER_MASK_MC34708	0x300
+#define TIMER_4S_MC34708	0x100
+#define VUSBSEL_MC34708		(1 << 2)
+#define VUSBEN_MC34708		(1 << 3)
+#define SWBST_CTRL		31
+#define SWBST_AUTO		0x8
+
 #endif
diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index 949864c0f2..1758d7445e 100644
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -35,20 +35,20 @@ enum {
 int get_fpga_state(unsigned dev);
 void print_fpga_state(unsigned dev);
 
-typedef struct ihs_gpio {
+struct ihs_gpio {
 	u16 read;
 	u16 clear;
 	u16 set;
-} ihs_gpio_t;
+};
 
-typedef struct ihs_i2c {
+struct ihs_i2c {
 	u16 write_mailbox;
 	u16 write_mailbox_ext;
 	u16 read_mailbox;
 	u16 read_mailbox_ext;
-} ihs_i2c_t;
+};
 
-typedef struct ihs_osd {
+struct ihs_osd {
 	u16 version;
 	u16 features;
 	u16 control;
@@ -56,10 +56,21 @@ typedef struct ihs_osd {
 	u16 xy_scale;
 	u16 x_pos;
 	u16 y_pos;
-} ihs_osd_t;
+};
+
+#ifdef CONFIG_NEO
+struct ihs_fpga {
+	u16 reflection_low;	/* 0x0000 */
+	u16 versions;		/* 0x0002 */
+	u16 fpga_features;	/* 0x0004 */
+	u16 fpga_version;	/* 0x0006 */
+	u16 reserved_0[8187];	/* 0x0008 */
+	u16 reflection_high;	/* 0x3ffe */
+};
+#endif
 
 #ifdef CONFIG_IO
-typedef struct ihs_fpga {
+struct ihs_fpga {
 	u16 reflection_low;	/* 0x0000 */
 	u16 versions;		/* 0x0002 */
 	u16 fpga_features;	/* 0x0004 */
@@ -68,11 +79,11 @@ typedef struct ihs_fpga {
 	u16 quad_serdes_reset;	/* 0x0012 */
 	u16 reserved_1[8181];	/* 0x0014 */
 	u16 reflection_high;	/* 0x3ffe */
-} ihs_fpga_t;
+};
 #endif
 
 #ifdef CONFIG_IO64
-typedef struct ihs_fpga {
+struct ihs_fpga {
 	u16 reflection_low;	/* 0x0000 */
 	u16 versions;		/* 0x0002 */
 	u16 fpga_features;	/* 0x0004 */
@@ -87,30 +98,30 @@ typedef struct ihs_fpga {
 	u16 ch0_hicb_config_int;/* 0x0502 */
 	u16 reserved_3[7549];	/* 0x0504 */
 	u16 reflection_high;	/* 0x3ffe */
-} ihs_fpga_t;
+};
 #endif
 
 #ifdef CONFIG_IOCON
-typedef struct ihs_fpga {
+struct ihs_fpga {
 	u16 reflection_low;	/* 0x0000 */
 	u16 versions;		/* 0x0002 */
 	u16 fpga_version;	/* 0x0004 */
 	u16 fpga_features;	/* 0x0006 */
 	u16 reserved_0[6];	/* 0x0008 */
-	ihs_gpio_t gpio;	/* 0x0014 */
+	struct ihs_gpio gpio;	/* 0x0014 */
 	u16 mpc3w_control;	/* 0x001a */
 	u16 reserved_1[19];	/* 0x001c */
 	u16 videocontrol;	/* 0x0042 */
 	u16 reserved_2[93];	/* 0x0044 */
 	u16 reflection_high;	/* 0x00fe */
-	ihs_osd_t osd;		/* 0x0100 */
-	u16 reserved_3[88];	/* 0x010e */
+	struct ihs_osd osd;	/* 0x0100 */
+	u16 reserved_3[889];	/* 0x010e */
 	u16 videomem;		/* 0x0800 */
-} ihs_fpga_t;
+};
 #endif
 
 #ifdef CONFIG_DLVISION_10G
-typedef struct ihs_fpga {
+struct ihs_fpga {
 	u16 reflection_low;	/* 0x0000 */
 	u16 versions;		/* 0x0002 */
 	u16 fpga_version;	/* 0x0004 */
@@ -118,16 +129,16 @@ typedef struct ihs_fpga {
 	u16 reserved_0[10];	/* 0x0008 */
 	u16 extended_interrupt; /* 0x001c */
 	u16 reserved_1[9];	/* 0x001e */
-	ihs_i2c_t i2c;		/* 0x0030 */
+	struct ihs_i2c i2c;	/* 0x0030 */
 	u16 reserved_2[16];	/* 0x0038 */
 	u16 mpc3w_control;	/* 0x0058 */
 	u16 reserved_3[34];	/* 0x005a */
 	u16 videocontrol;	/* 0x009e */
 	u16 reserved_4[176];	/* 0x00a0 */
-	ihs_osd_t osd;		/* 0x0200 */
+	struct ihs_osd osd;	/* 0x0200 */
 	u16 reserved_5[761];	/* 0x020e */
 	u16 videomem;		/* 0x0800 */
-} ihs_fpga_t;
+};
 #endif
 
 #endif
diff --git a/include/ide.h b/include/ide.h
index 8ecc9dd3a5..0424d045a1 100644
--- a/include/ide.h
+++ b/include/ide.h
@@ -2,31 +2,16 @@
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef	_IDE_H
 #define _IDE_H
 
-#define	IDE_BUS(dev)	(dev >> 1)
+#define IDE_BUS(dev)	(dev / (CONFIG_SYS_IDE_MAXDEVICE / CONFIG_SYS_IDE_MAXBUS))
 
 #define	ATA_CURR_BASE(dev)	(CONFIG_SYS_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)])
+extern ulong ide_bus_offset[];
 
 #ifdef CONFIG_IDE_LED
 
@@ -42,8 +27,12 @@
 
 #ifdef CONFIG_SYS_64BIT_LBA
 typedef uint64_t lbaint_t;
+#define LBAF "%llx"
+#define LBAFU "%llu"
 #else
 typedef ulong lbaint_t;
+#define LBAF "%lx"
+#define LBAFU "%lu"
 #endif
 
 /*
@@ -51,8 +40,17 @@ typedef ulong lbaint_t;
  */
 
 void ide_init(void);
-ulong ide_read(int device, lbaint_t blknr, ulong blkcnt, void *buffer);
-ulong ide_write(int device, lbaint_t blknr, ulong blkcnt, const void *buffer);
+ulong ide_read(int device, lbaint_t blknr, lbaint_t blkcnt, void *buffer);
+ulong ide_write(int device, lbaint_t blknr, lbaint_t blkcnt,
+		const void *buffer);
+
+#ifdef CONFIG_IDE_PREINIT
+int ide_preinit(void);
+#endif
+
+#ifdef CONFIG_IDE_INIT_POSTRESET
+int ide_init_postreset(void);
+#endif
 
 #if defined(CONFIG_OF_IDE_FIXUP)
 int ide_device_present(int dev);
@@ -62,6 +60,23 @@ int ide_device_present(int dev);
 unsigned char ide_read_register(int dev, unsigned int port);
 void ide_write_register(int dev, unsigned int port, unsigned char val);
 void ide_read_data(int dev, ulong *sect_buf, int words);
-void ide_write_data(int dev, ulong *sect_buf, int words);
+void ide_write_data(int dev, const ulong *sect_buf, int words);
 #endif
+
+/*
+ * I/O function overrides
+ */
+void ide_input_swap_data(int dev, ulong *sect_buf, int words);
+void ide_input_data(int dev, ulong *sect_buf, int words);
+void ide_output_data(int dev, const ulong *sect_buf, int words);
+void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts);
+void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts);
+
+/**
+ * board_start_ide() - Start up the board IDE interfac
+ *
+ * @return 0 if ok
+ */
+int board_start_ide(void);
+
 #endif /* _IDE_H */
diff --git a/include/image.h b/include/image.h
index a1c6e4e9ad..aa9daa2deb 100644
--- a/include/image.h
+++ b/include/image.h
@@ -531,9 +531,9 @@ static inline int image_check_target_arch(const image_header_t *hdr)
 #define FIT_MAX_HASH_LEN	20	/* max(crc32_len(4), sha1_len(20)) */
 
 /* cmdline argument format parsing */
-inline int fit_parse_conf(const char *spec, ulong addr_curr,
+int fit_parse_conf(const char *spec, ulong addr_curr,
 		ulong *addr, const char **conf_name);
-inline int fit_parse_subimage(const char *spec, ulong addr_curr,
+int fit_parse_subimage(const char *spec, ulong addr_curr,
 		ulong *addr, const char **image_name);
 
 void fit_print_contents(const void *fit);
diff --git a/include/input.h b/include/input.h
new file mode 100644
index 0000000000..31b1ef9603
--- /dev/null
+++ b/include/input.h
@@ -0,0 +1,147 @@
+/*
+ * Keyboard input helper functions (too small to be called a layer)
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _INPUT_H
+#define _INPUT_H
+
+enum {
+	INPUT_MAX_MODIFIERS	= 4,
+	INPUT_BUFFER_LEN	= 16,
+};
+
+enum {
+	/* Keyboard LEDs */
+	INPUT_LED_SCROLL	= 1 << 0,
+	INPUT_LED_CAPS		= 1 << 1,
+	INPUT_LED_NUM		= 1 << 2,
+};
+
+/*
+ * This table translates key codes to ASCII. Most of the entries are ASCII
+ * codes, but entries after KEY_FIRST_MOD indicate that this key is a
+ * modifier key, like shift, ctrl. KEY_FIRST_MOD + MOD_SHIFT is the shift
+ * key, for example.
+ */
+struct input_key_xlate {
+	/* keycode of the modifiers which select this table, -1 if none */
+	int left_keycode;
+	int right_keycode;
+	const uchar *xlate;	/* keycode to ASCII table */
+	int num_entries;	/* number of entries in this table */
+};
+
+struct input_config {
+	uchar fifo[INPUT_BUFFER_LEN];
+	int fifo_in, fifo_out;
+
+	/* Which modifiers are active (1 bit for each MOD_... value) */
+	uchar modifiers;
+	uchar flags;		/* active state keys (FLAGS_...) */
+	uchar leds;		/* active LEDS (INPUT_LED_...) */
+	uchar num_tables;	/* number of modifier tables */
+	int prev_keycodes[INPUT_BUFFER_LEN];	/* keys held last time */
+	int num_prev_keycodes;	/* number of prev keys */
+	struct input_key_xlate table[INPUT_MAX_MODIFIERS];
+
+	/**
+	 * Function the input helper calls to scan the keyboard
+	 *
+	 * @param config	Input state
+	 * @return 0 if no keys read, otherwise number of keys read, or 1 if
+	 *		unknown
+	 */
+	int (*read_keys)(struct input_config *config);
+	unsigned int next_repeat_ms;	/* Next time we repeat a key */
+	unsigned int repeat_delay_ms;	/* Time before autorepeat starts */
+	unsigned int repeat_rate_ms;	/* Autorepeat rate in ms */
+};
+
+struct stdio_dev;
+
+/**
+ * Convert a list of key codes into ASCII and send them
+ *
+ * @param config	Input state
+ * @param keycode	List of key codes to examine
+ * @param num_keycodes	Number of key codes
+ */
+int input_send_keycodes(struct input_config *config, int keycode[], int count);
+
+/**
+ * Add a new key translation table to the input
+ *
+ * @param config	Input state
+ * @param left_keycode	Key to hold to get into this table
+ * @param right_keycode	Another key to hold to get into this table
+ * @param xlate		Conversion table from key codes to ASCII
+ * @param num_entries	Number of entries in xlate table
+ */
+int input_add_table(struct input_config *config, int left_keycode,
+		    int right_keycode, const uchar *xlate, int num_entries);
+
+/**
+ * Test if keys are available to be read
+ *
+ * @param config	Input state
+ * @return 0 if no keys available, 1 if keys are available
+ */
+int input_tstc(struct input_config *config);
+
+/**
+ * Read a key
+ *
+ * TODO: U-Boot wants 0 for no key, but Ctrl-@ is a valid key...
+ *
+ * @param config	Input state
+ * @return key, or 0 if no key, or -1 if error
+ */
+int input_getc(struct input_config *config);
+
+/**
+ * Register a new device with stdio and switch to it if wanted
+ *
+ * @param dev	Pointer to device
+ * @return 0 if ok, -1 on error
+ */
+int input_stdio_register(struct stdio_dev *dev);
+
+/**
+ * Set up the input handler with basic key maps.
+ *
+ * @param config	Input state
+ * @param leds		Initial LED value (INPUT_LED_ mask), 0 suggested
+ * @param repeat_delay_ms	Delay before key auto-repeat starts (in ms)
+ * @param repeat_rate_ms	Delay between successive key repeats (in ms)
+ * @return 0 if ok, -1 on error
+ */
+int input_init(struct input_config *config, int leds, int repeat_delay_ms,
+	       int repeat_rate_ms);
+
+#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+extern int overwrite_console(void);
+#define OVERWRITE_CONSOLE overwrite_console()
+#else
+#define OVERWRITE_CONSOLE 0
+#endif /* CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE */
+
+#endif
diff --git a/include/jffs2/load_kernel.h b/include/jffs2/load_kernel.h
index 906eb3d3cd..23bb4ae0a3 100644
--- a/include/jffs2/load_kernel.h
+++ b/include/jffs2/load_kernel.h
@@ -46,11 +46,12 @@ struct part_info {
 	struct list_head link;
 	char *name;			/* partition name */
 	u8 auto_name;			/* set to 1 for generated name */
-	u32 size;			/* total size of the partition */
-	u32 offset;			/* offset within device */
+	u64 size;			/* total size of the partition */
+	u64 offset;			/* offset within device */
 	void *jffs2_priv;		/* used internaly by jffs2 */
 	u32 mask_flags;			/* kernel MTD mask flags */
 	u32 sector_size;		/* size of sector */
+	int dirty;			/* if true, the mtd has been wrotten data*/
 	struct mtd_device *dev;		/* parent device */
 };
 
@@ -58,7 +59,7 @@ struct mtdids {
 	struct list_head link;
 	u8 type;			/* device type */
 	u8 num;				/* device number */
-	u32 size;			/* device size */
+	u64 size;			/* device size */
 	char *mtd_id;			/* linux kernel device id */
 };
 
@@ -79,5 +80,6 @@ extern int mtdparts_init(void);
 extern int find_dev_and_part(const char *id, struct mtd_device **dev,
 				u8 *part_num, struct part_info **part);
 extern struct mtd_device *device_find(u8 type, u8 num);
+int mtdparts_clear_all_dirty(struct mtd_device *dev);
 
 #endif /* load_kernel_h */
diff --git a/include/key_matrix.h b/include/key_matrix.h
new file mode 100644
index 0000000000..f41331407d
--- /dev/null
+++ b/include/key_matrix.h
@@ -0,0 +1,99 @@
+/*
+ * Keyboard matrix helper functions
+ *
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _KEY_MATRIX_H
+#define _KEY_MATRIX_H
+
+#include <common.h>
+
+/* Information about a matrix keyboard */
+struct key_matrix {
+	/* Dimensions of the keyboard matrix, in rows and columns */
+	int num_rows;
+	int num_cols;
+	int key_count;	/* number of keys in the matrix (= rows * cols) */
+
+	/*
+	 * Information about keycode mappings. The plain_keycode array must
+	 * exist but fn may be NULL in which case it is not decoded.
+	 */
+	const u8 *plain_keycode;        /* key code for each row / column */
+	const u8 *fn_keycode;           /* ...when Fn held down */
+	int fn_pos;                     /* position of Fn key in key (or -1) */
+};
+
+/* Information about a particular key (row, column pair) in the matrix */
+struct key_matrix_key {
+	uint8_t row;	/* row number (0 = first) */
+	uint8_t col;	/* column number (0 = first) */
+	uint8_t valid;	/* 1 if valid, 0 to ignore this */
+};
+
+/**
+ * Decode a set of pressed keys into key codes
+ *
+ * Given a list of keys that are pressed, this converts this list into
+ * a list of key codes. Each of the keys has a valid flag, which can be
+ * used to mark a particular key as invalid (so that it is ignored).
+ *
+ * The plain keymap is used, unless the Fn key is detected along the way,
+ * at which point we switch to the Fn key map.
+ *
+ * If key ghosting is detected, we simply ignore the keys and return 0.
+ *
+ * @param config        Keyboard matrix config
+ * @param keys		List of keys to process (each is row, col)
+ * @param num_keys	Number of keys to process
+ * @param keycode	Returns a list of key codes, decoded from input
+ * @param max_keycodes	Size of key codes array (suggest 8)
+ *
+ */
+int key_matrix_decode(struct key_matrix *config, struct key_matrix_key *keys,
+		      int num_keys, int keycode[], int max_keycodes);
+
+/**
+ * Read the keyboard configuration out of the fdt.
+ *
+ * Decode properties of named "linux,<type>keymap" where <type> is either
+ * empty, or "fn-". Then set up the plain key map (and the FN keymap if
+ * present).
+ *
+ * @param config        Keyboard matrix config
+ * @param blob          FDT blob
+ * @param node          Node containing compatible data
+ * @return 0 if ok, -1 on error
+ */
+int key_matrix_decode_fdt(struct key_matrix *config, const void *blob,
+			  int node);
+
+/**
+ * Set up a new key matrix.
+ *
+ * @param config	Keyboard matrix config
+ * @param rows		Number of rows in key matrix
+ * @param cols		Number of columns in key matrix
+ * @return 0 if ok, -1 on error
+ */
+int key_matrix_init(struct key_matrix *config, int rows, int cols);
+
+#endif
diff --git a/include/lcd.h b/include/lcd.h
index d95feeb791..3d9ef16710 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -183,6 +183,70 @@ typedef struct vidinfo {
 	u_long	mmio;		/* Memory mapped registers */
 } vidinfo_t;
 
+#elif defined(CONFIG_EXYNOS_FB)
+
+enum {
+	FIMD_RGB_INTERFACE = 1,
+	FIMD_CPU_INTERFACE = 2,
+};
+
+typedef struct vidinfo {
+	ushort vl_col;		/* Number of columns (i.e. 640) */
+	ushort vl_row;		/* Number of rows (i.e. 480) */
+	ushort vl_width;	/* Width of display area in millimeters */
+	ushort vl_height;	/* Height of display area in millimeters */
+
+	/* LCD configuration register */
+	u_char vl_freq;		/* Frequency */
+	u_char vl_clkp;		/* Clock polarity */
+	u_char vl_oep;		/* Output Enable polarity */
+	u_char vl_hsp;		/* Horizontal Sync polarity */
+	u_char vl_vsp;		/* Vertical Sync polarity */
+	u_char vl_dp;		/* Data polarity */
+	u_char vl_bpix;		/* Bits per pixel */
+
+	/* Horizontal control register. Timing from data sheet */
+	u_char vl_hspw;		/* Horz sync pulse width */
+	u_char vl_hfpd;		/* Wait before of line */
+	u_char vl_hbpd;		/* Wait end of line */
+
+	/* Vertical control register. */
+	u_char	vl_vspw;	/* Vertical sync pulse width */
+	u_char	vl_vfpd;	/* Wait before of frame */
+	u_char	vl_vbpd;	/* Wait end of frame */
+	u_char  vl_cmd_allow_len; /* Wait end of frame */
+
+	void (*cfg_gpio)(void);
+	void (*backlight_on)(unsigned int onoff);
+	void (*reset_lcd)(void);
+	void (*lcd_power_on)(void);
+	void (*cfg_ldo)(void);
+	void (*enable_ldo)(unsigned int onoff);
+	void (*mipi_power)(void);
+	void (*backlight_reset)(void);
+
+	unsigned int win_id;
+	unsigned int init_delay;
+	unsigned int power_on_delay;
+	unsigned int reset_delay;
+	unsigned int interface_mode;
+	unsigned int mipi_enabled;
+	unsigned int cs_setup;
+	unsigned int wr_setup;
+	unsigned int wr_act;
+	unsigned int wr_hold;
+
+	/* parent clock name(MPLL, EPLL or VPLL) */
+	unsigned int pclk_name;
+	/* ratio value for source clock from parent clock. */
+	unsigned int sclk_div;
+
+	unsigned int dual_lcd_enabled;
+
+} vidinfo_t;
+
+void init_panel_info(vidinfo_t *vid);
+
 #else
 
 typedef struct vidinfo {
diff --git a/include/linux/mtd/compat.h b/include/linux/compat.h
index 39c693f7a8..593b07f4b5 100644
--- a/include/linux/mtd/compat.h
+++ b/include/linux/compat.h
@@ -48,5 +48,8 @@
 #define BUG_ON(condition) do { if (condition) BUG(); } while(0)
 #endif /* BUG */
 
+#define WARN_ON(x) if (x) {printf("WARNING in %s line %d\n" \
+				  , __FILE__, __LINE__); }
+
 #define PAGE_SIZE	4096
 #endif
diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h
index 73dcf804bc..ad6627787c 100644
--- a/include/linux/compiler-gcc.h
+++ b/include/linux/compiler-gcc.h
@@ -44,9 +44,10 @@
  */
 #if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \
     !defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4)
-# define inline		inline		__attribute__((always_inline))
-# define __inline__	__inline__	__attribute__((always_inline))
-# define __inline	__inline	__attribute__((always_inline))
+/* XXX: check __GNUC_STDC_INLINE__, fix line length */
+# define inline		inline		__attribute__((always_inline)) __attribute__((__gnu_inline__))
+# define __inline__	__inline__	__attribute__((always_inline)) __attribute__((__gnu_inline__))
+# define __inline	__inline	__attribute__((always_inline)) __attribute__((__gnu_inline__))
 #endif
 
 #define __deprecated			__attribute__((deprecated))
diff --git a/include/linux/compiler-gcc5.h b/include/linux/compiler-gcc5.h
new file mode 100644
index 0000000000..c8c5659525
--- /dev/null
+++ b/include/linux/compiler-gcc5.h
@@ -0,0 +1,65 @@
+#ifndef __LINUX_COMPILER_H
+#error "Please don't include <linux/compiler-gcc5.h> directly, include <linux/compiler.h> instead."
+#endif
+
+#define __used				__attribute__((__used__))
+#define __must_check			__attribute__((warn_unused_result))
+#define __compiler_offsetof(a, b)	__builtin_offsetof(a, b)
+
+/* Mark functions as cold. gcc will assume any path leading to a call
+   to them will be unlikely.  This means a lot of manual unlikely()s
+   are unnecessary now for any paths leading to the usual suspects
+   like BUG(), printk(), panic() etc. [but let's keep them for now for
+   older compilers]
+
+   Early snapshots of gcc 4.3 don't support this and we can't detect this
+   in the preprocessor, but we can live with this because they're unreleased.
+   Maketime probing would be overkill here.
+
+   gcc also has a __attribute__((__hot__)) to move hot functions into
+   a special section, but I don't see any sense in this right now in
+   the kernel context */
+#define __cold			__attribute__((__cold__))
+
+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
+
+#ifndef __CHECKER__
+# define __compiletime_warning(message) __attribute__((warning(message)))
+# define __compiletime_error(message) __attribute__((error(message)))
+#endif /* __CHECKER__ */
+
+/*
+ * Mark a position in code as unreachable.  This can be used to
+ * suppress control flow warnings after asm blocks that transfer
+ * control elsewhere.
+ *
+ * Early snapshots of gcc 4.5 don't support this and we can't detect
+ * this in the preprocessor, but we can live with this because they're
+ * unreleased.  Really, we need to have autoconf for the kernel.
+ */
+#define unreachable() __builtin_unreachable()
+
+/* Mark a function definition as prohibited from being cloned. */
+#define __noclone	__attribute__((__noclone__))
+
+/*
+ * Tell the optimizer that something else uses this function or variable.
+ */
+#define __visible __attribute__((externally_visible))
+
+/*
+ * GCC 'asm goto' miscompiles certain code sequences:
+ *
+ *   http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670
+ *
+ * Work it around via a compiler barrier quirk suggested by Jakub Jelinek.
+ *
+ * (asm goto is automatically volatile - the naming reflects this.)
+ */
+#define asm_volatile_goto(x...)	do { asm goto(x); asm (""); } while (0)
+
+#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP
+#define __HAVE_BUILTIN_BSWAP32__
+#define __HAVE_BUILTIN_BSWAP64__
+#define __HAVE_BUILTIN_BSWAP16__
+#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */
diff --git a/include/linux/compiler-gcc6.h b/include/linux/compiler-gcc6.h
new file mode 100644
index 0000000000..a3d00d8d31
--- /dev/null
+++ b/include/linux/compiler-gcc6.h
@@ -0,0 +1,66 @@
+#ifndef __LINUX_COMPILER_H
+#error "Please don't include <linux/compiler-gcc6.h> directly, include <linux/compiler.h> instead."
+#endif
+
+#define __used				__attribute__((__used__))
+#define __must_check			__attribute__((warn_unused_result))
+#define __compiler_offsetof(a, b)	__builtin_offsetof(a, b)
+
+/* Mark functions as cold. gcc will assume any path leading to a call
+   to them will be unlikely.  This means a lot of manual unlikely()s
+   are unnecessary now for any paths leading to the usual suspects
+   like BUG(), printk(), panic() etc. [but let's keep them for now for
+   older compilers]
+
+   Early snapshots of gcc 4.3 don't support this and we can't detect this
+   in the preprocessor, but we can live with this because they're unreleased.
+   Maketime probing would be overkill here.
+
+   gcc also has a __attribute__((__hot__)) to move hot functions into
+   a special section, but I don't see any sense in this right now in
+   the kernel context */
+#define __cold			__attribute__((__cold__))
+
+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
+
+#ifndef __CHECKER__
+# define __compiletime_warning(message) __attribute__((warning(message)))
+# define __compiletime_error(message) __attribute__((error(message)))
+#endif /* __CHECKER__ */
+
+/*
+ * Mark a position in code as unreachable.  This can be used to
+ * suppress control flow warnings after asm blocks that transfer
+ * control elsewhere.
+ *
+ * Early snapshots of gcc 4.5 don't support this and we can't detect
+ * this in the preprocessor, but we can live with this because they're
+ * unreleased.  Really, we need to have autoconf for the kernel.
+ */
+#define unreachable() __builtin_unreachable()
+
+/* Mark a function definition as prohibited from being cloned. */
+#define __noclone	__attribute__((__noclone__))
+
+/*
+ * Tell the optimizer that something else uses this function or variable.
+ */
+#define __visible __attribute__((externally_visible))
+
+/*
+ * GCC 'asm goto' miscompiles certain code sequences:
+ *
+ *   http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670
+ *
+ * Work it around via a compiler barrier quirk suggested by Jakub Jelinek.
+ * Fixed in GCC 4.8.2 and later versions.
+ *
+ * (asm goto is automatically volatile - the naming reflects this.)
+ */
+#define asm_volatile_goto(x...)	do { asm goto(x); asm (""); } while (0)
+
+#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP
+#define __HAVE_BUILTIN_BSWAP32__
+#define __HAVE_BUILTIN_BSWAP64__
+#define __HAVE_BUILTIN_BSWAP16__
+#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */
diff --git a/include/linux/err.h b/include/linux/err.h
index 4e08c4fe68..96c0c72baa 100644
--- a/include/linux/err.h
+++ b/include/linux/err.h
@@ -5,7 +5,7 @@
 #if 0
 #include <linux/compiler.h>
 #else
-#include <linux/mtd/compat.h>
+#include <linux/compat.h>
 #endif
 
 #include <asm/errno.h>
diff --git a/include/linux/input.h b/include/linux/input.h
new file mode 100644
index 0000000000..44aec763dc
--- /dev/null
+++ b/include/linux/input.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 1999-2002 Vojtech Pavlik
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+
+#ifndef _LINUX_INPUT_H
+#define _LINUX_INPUT_H
+
+/*
+ * Keys and buttons
+ *
+ * Most of the keys/buttons are modeled after USB HUT 1.12
+ * (see http://www.usb.org/developers/hidpage).
+ * Abbreviations in the comments:
+ * AC - Application Control
+ * AL - Application Launch Button
+ * SC - System Control
+ */
+
+#define KEY_RESERVED		0
+#define KEY_ESC			1
+#define KEY_1			2
+#define KEY_2			3
+#define KEY_3			4
+#define KEY_4			5
+#define KEY_5			6
+#define KEY_6			7
+#define KEY_7			8
+#define KEY_8			9
+#define KEY_9			10
+#define KEY_0			11
+#define KEY_MINUS		12
+#define KEY_EQUAL		13
+#define KEY_BACKSPACE		14
+#define KEY_TAB			15
+#define KEY_Q			16
+#define KEY_W			17
+#define KEY_E			18
+#define KEY_R			19
+#define KEY_T			20
+#define KEY_Y			21
+#define KEY_U			22
+#define KEY_I			23
+#define KEY_O			24
+#define KEY_P			25
+#define KEY_LEFTBRACE		26
+#define KEY_RIGHTBRACE		27
+#define KEY_ENTER		28
+#define KEY_LEFTCTRL		29
+#define KEY_A			30
+#define KEY_S			31
+#define KEY_D			32
+#define KEY_F			33
+#define KEY_G			34
+#define KEY_H			35
+#define KEY_J			36
+#define KEY_K			37
+#define KEY_L			38
+#define KEY_SEMICOLON		39
+#define KEY_APOSTROPHE		40
+#define KEY_GRAVE		41
+#define KEY_LEFTSHIFT		42
+#define KEY_BACKSLASH		43
+#define KEY_Z			44
+#define KEY_X			45
+#define KEY_C			46
+#define KEY_V			47
+#define KEY_B			48
+#define KEY_N			49
+#define KEY_M			50
+#define KEY_COMMA		51
+#define KEY_DOT			52
+#define KEY_SLASH		53
+#define KEY_RIGHTSHIFT		54
+#define KEY_KPASTERISK		55
+#define KEY_LEFTALT		56
+#define KEY_SPACE		57
+#define KEY_CAPSLOCK		58
+#define KEY_F1			59
+#define KEY_F2			60
+#define KEY_F3			61
+#define KEY_F4			62
+#define KEY_F5			63
+#define KEY_F6			64
+#define KEY_F7			65
+#define KEY_F8			66
+#define KEY_F9			67
+#define KEY_F10			68
+#define KEY_NUMLOCK		69
+#define KEY_SCROLLLOCK		70
+#define KEY_KP7			71
+#define KEY_KP8			72
+#define KEY_KP9			73
+#define KEY_KPMINUS		74
+#define KEY_KP4			75
+#define KEY_KP5			76
+#define KEY_KP6			77
+#define KEY_KPPLUS		78
+#define KEY_KP1			79
+#define KEY_KP2			80
+#define KEY_KP3			81
+#define KEY_KP0			82
+#define KEY_KPDOT		83
+
+#define KEY_ZENKAKUHANKAKU	85
+#define KEY_102ND		86
+#define KEY_F11			87
+#define KEY_F12			88
+#define KEY_RO			89
+#define KEY_KATAKANA		90
+#define KEY_HIRAGANA		91
+#define KEY_HENKAN		92
+#define KEY_KATAKANAHIRAGANA	93
+#define KEY_MUHENKAN		94
+#define KEY_KPJPCOMMA		95
+#define KEY_KPENTER		96
+#define KEY_RIGHTCTRL		97
+#define KEY_KPSLASH		98
+#define KEY_SYSRQ		99
+#define KEY_RIGHTALT		100
+#define KEY_LINEFEED		101
+#define KEY_HOME		102
+#define KEY_UP			103
+#define KEY_PAGEUP		104
+#define KEY_LEFT		105
+#define KEY_RIGHT		106
+#define KEY_END			107
+#define KEY_DOWN		108
+#define KEY_PAGEDOWN		109
+#define KEY_INSERT		110
+#define KEY_DELETE		111
+#define KEY_MACRO		112
+#define KEY_MUTE		113
+#define KEY_VOLUMEDOWN		114
+#define KEY_VOLUMEUP		115
+#define KEY_POWER		116	/* SC System Power Down */
+#define KEY_KPEQUAL		117
+#define KEY_KPPLUSMINUS		118
+#define KEY_PAUSE		119
+#define KEY_SCALE		120	/* AL Compiz Scale (Expose) */
+
+#define KEY_KPCOMMA		121
+#define KEY_HANGEUL		122
+#define KEY_HANGUEL		KEY_HANGEUL
+#define KEY_HANJA		123
+#define KEY_YEN			124
+#define KEY_LEFTMETA		125
+#define KEY_RIGHTMETA		126
+#define KEY_COMPOSE		127
+#define KEY_FN			0x1d0
+
+#endif
diff --git a/include/linux/linkage.h b/include/linux/linkage.h
index ed4cf6cbcd..7b749bbda7 100644
--- a/include/linux/linkage.h
+++ b/include/linux/linkage.h
@@ -44,8 +44,13 @@
 #define SYMBOL_NAME_LABEL(X)	X:
 #endif
 
+#ifndef __ALIGN
 #define __ALIGN .align		4
+#endif
+
+#ifndef __ALIGN_STR
 #define __ALIGN_STR		".align 4"
+#endif
 
 #ifdef __ASSEMBLY__
 
@@ -67,7 +72,7 @@
 
 #ifndef ENDPROC
 #define ENDPROC(name) \
-	.type name, @function; \
+	.type name STT_FUNC; \
 	END(name)
 #endif
 
diff --git a/include/linux/mtd/mtd-abi.h b/include/linux/mtd/mtd-abi.h
index 8d5f60c75e..5991157065 100644
--- a/include/linux/mtd/mtd-abi.h
+++ b/include/linux/mtd/mtd-abi.h
@@ -8,7 +8,7 @@
 #define __MTD_ABI_H__
 
 #if 1
-#include <linux/mtd/compat.h>
+#include <linux/compat.h>
 #endif
 
 struct erase_info_user {
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 141c96024c..dbcc05ae86 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -236,6 +236,11 @@ struct mtd_info {
 	void (*put_device) (struct mtd_info *mtd);
 };
 
+static inline int is_power_of_2(unsigned long n)
+{
+	return (n != 0 && ((n & (n - 1)) == 0));
+}
+
 static inline uint32_t mtd_div_by_eb(uint64_t sz, struct mtd_info *mtd)
 {
 	do_div(sz, mtd->erasesize);
@@ -247,6 +252,30 @@ static inline uint32_t mtd_mod_by_eb(uint64_t sz, struct mtd_info *mtd)
 	return do_div(sz, mtd->erasesize);
 }
 
+static inline uint32_t mtd_div_by_ws(uint64_t sz, struct mtd_info *mtd)
+{
+	do_div(sz, mtd->writesize);
+	return sz;
+}
+
+static inline uint32_t mtd_mod_by_ws(uint64_t sz, struct mtd_info *mtd)
+{
+	return do_div(sz, mtd->writesize);
+}
+
+static inline uint32_t mtd_div_by_var(uint64_t sz, uint32_t var)
+{
+	(void)(((typeof((var)) *)0) == ((uint32_t *)0));
+	do_div(sz, var);
+	return sz;
+}
+
+static inline uint32_t mtd_mod_by_var(uint64_t sz, uint32_t var)
+{
+	(void)(((typeof((var)) *)0) == ((uint32_t *)0));
+	return do_div(sz, var);
+}
+
 	/* Kernel-side ioctl definitions */
 
 extern int add_mtd_device(struct mtd_info *mtd);
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index da6fa184c3..eb580f3e99 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -20,7 +20,7 @@
 
 #include "config.h"
 
-#include "linux/mtd/compat.h"
+#include "linux/compat.h"
 #include "linux/mtd/mtd.h"
 #include "linux/mtd/bbm.h"
 
@@ -47,7 +47,7 @@ extern void nand_wait_ready(struct mtd_info *mtd);
  * adjust this accordingly.
  */
 #define NAND_MAX_OOBSIZE	576
-#define NAND_MAX_PAGESIZE	8192
+#define NAND_MAX_PAGESIZE	16384
 
 /*
  * Constants for hardware specific CLE/ALE/NCE function
@@ -480,6 +480,7 @@ struct nand_chip {
 	void __iomem *IO_ADDR_R;
 	void __iomem *IO_ADDR_W;
 
+	void (*read_nand_ID)(struct mtd_info *mtd);
 	uint8_t (*read_byte)(struct mtd_info *mtd);
 	u16 (*read_word)(struct mtd_info *mtd);
 	void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
@@ -556,6 +557,7 @@ struct nand_chip {
 #define NAND_MFR_HYNIX		0xad
 #define NAND_MFR_MICRON		0x2c
 #define NAND_MFR_AMD		0x01
+#define NAND_MFR_ESMT		0xc8
 
 /**
  * struct nand_flash_dev - NAND Flash Device ID Structure
@@ -671,6 +673,35 @@ struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
 	return chip->priv;
 }
 
+static inline uint32_t mtd_div_by_cs(uint64_t sz, struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+
+	if(chip->chipsize >> 32){
+		//assume the chipsize is not out of 4096TB(4*1024*1024*GB)
+		//4096TB is 52bits.
+		sz >>= 20;
+		do_div(sz, chip->chipsize >> 20);
+	}else{
+		do_div(sz, chip->chipsize);
+	}
+	return sz;
+}
+
+static inline uint32_t mtd_mod_by_cs(uint64_t sz, struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+
+	if(chip->chipsize >> 32){
+		//assume the chipsize is not out of 4096TB(4*1024*1024*GB)
+		//4096TB is 52bits.
+		sz >>= 20;
+		return do_div(sz, chip->chipsize >> 20);
+	}else{
+		return do_div(sz, chip->chipsize);
+	}
+}
+
 /* Standard NAND functions from nand_base.c */
 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h
index bb4a4a6b28..e7b63ddd10 100644
--- a/include/linux/mtd/onenand.h
+++ b/include/linux/mtd/onenand.h
@@ -17,7 +17,7 @@
 /* Note: The header order is impoertant */
 #include <onenand_uboot.h>
 
-#include <linux/mtd/compat.h>
+#include <linux/compat.h>
 #include <linux/mtd/bbm.h>
 
 #define MAX_DIES		2
diff --git a/include/linux/usb/ch9.h b/include/linux/usb/ch9.h
index 49b748337a..ce1d1e10ba 100644
--- a/include/linux/usb/ch9.h
+++ b/include/linux/usb/ch9.h
@@ -204,28 +204,6 @@ struct usb_descriptor_header {
 	__u8  bDescriptorType;
 } __attribute__ ((packed));
 
-
-/*-------------------------------------------------------------------------*/
-
-/* USB_DT_DEVICE: Device descriptor */
-struct usb_device_descriptor {
-	__u8  bLength;
-	__u8  bDescriptorType;
-
-	__le16 bcdUSB;
-	__u8  bDeviceClass;
-	__u8  bDeviceSubClass;
-	__u8  bDeviceProtocol;
-	__u8  bMaxPacketSize0;
-	__le16 idVendor;
-	__le16 idProduct;
-	__le16 bcdDevice;
-	__u8  iManufacturer;
-	__u8  iProduct;
-	__u8  iSerialNumber;
-	__u8  bNumConfigurations;
-} __attribute__ ((packed));
-
 #define USB_DT_DEVICE_SIZE		18
 
 
@@ -282,56 +260,11 @@ struct usb_config_descriptor {
 #define USB_CONFIG_ATT_WAKEUP		(1 << 5)	/* can wakeup */
 #define USB_CONFIG_ATT_BATTERY		(1 << 4)	/* battery powered */
 
-/*-------------------------------------------------------------------------*/
-
-/* USB_DT_STRING: String descriptor */
-struct usb_string_descriptor {
-	__u8  bLength;
-	__u8  bDescriptorType;
-
-	__le16 wData[1];		/* UTF-16LE encoded */
-} __attribute__ ((packed));
-
 /* note that "string" zero is special, it holds language codes that
  * the device supports, not Unicode characters.
  */
 
-/*-------------------------------------------------------------------------*/
-
-/* USB_DT_INTERFACE: Interface descriptor */
-struct usb_interface_descriptor {
-	__u8  bLength;
-	__u8  bDescriptorType;
-
-	__u8  bInterfaceNumber;
-	__u8  bAlternateSetting;
-	__u8  bNumEndpoints;
-	__u8  bInterfaceClass;
-	__u8  bInterfaceSubClass;
-	__u8  bInterfaceProtocol;
-	__u8  iInterface;
-} __attribute__ ((packed));
-
 #define USB_DT_INTERFACE_SIZE		9
-
-/*-------------------------------------------------------------------------*/
-
-/* USB_DT_ENDPOINT: Endpoint descriptor */
-struct usb_endpoint_descriptor {
-	__u8  bLength;
-	__u8  bDescriptorType;
-
-	__u8  bEndpointAddress;
-	__u8  bmAttributes;
-	__le16 wMaxPacketSize;
-	__u8  bInterval;
-
-	/* NOTE:  these two are _only_ in audio endpoints. */
-	/* use USB_DT_ENDPOINT*_SIZE in bLength, not sizeof. */
-	__u8  bRefresh;
-	__u8  bSynchAddress;
-} __attribute__ ((packed));
-
 #define USB_DT_ENDPOINT_SIZE		7
 #define USB_DT_ENDPOINT_AUDIO_SIZE	9	/* Audio extension */
 
diff --git a/include/linux/usb/composite.h b/include/linux/usb/composite.h
new file mode 100644
index 0000000000..53cb095507
--- /dev/null
+++ b/include/linux/usb/composite.h
@@ -0,0 +1,350 @@
+/*
+ * composite.h -- framework for usb gadgets which are composite devices
+ *
+ * Copyright (C) 2006-2008 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef	__LINUX_USB_COMPOSITE_H
+#define	__LINUX_USB_COMPOSITE_H
+
+/*
+ * This framework is an optional layer on top of the USB Gadget interface,
+ * making it easier to build (a) Composite devices, supporting multiple
+ * functions within any single configuration, and (b) Multi-configuration
+ * devices, also supporting multiple functions but without necessarily
+ * having more than one function per configuration.
+ *
+ * Example:  a device with a single configuration supporting both network
+ * link and mass storage functions is a composite device.  Those functions
+ * might alternatively be packaged in individual configurations, but in
+ * the composite model the host can use both functions at the same time.
+ */
+
+#include <common.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <usb/lin_gadget_compat.h>
+
+struct usb_configuration;
+
+/**
+ * struct usb_function - describes one function of a configuration
+ * @name: For diagnostics, identifies the function.
+ * @strings: tables of strings, keyed by identifiers assigned during bind()
+ *	and by language IDs provided in control requests
+ * @descriptors: Table of full (or low) speed descriptors, using interface and
+ *	string identifiers assigned during @bind().  If this pointer is null,
+ *	the function will not be available at full speed (or at low speed).
+ * @hs_descriptors: Table of high speed descriptors, using interface and
+ *	string identifiers assigned during @bind().  If this pointer is null,
+ *	the function will not be available at high speed.
+ * @config: assigned when @usb_add_function() is called; this is the
+ *	configuration with which this function is associated.
+ * @bind: Before the gadget can register, all of its functions bind() to the
+ *	available resources including string and interface identifiers used
+ *	in interface or class descriptors; endpoints; I/O buffers; and so on.
+ * @unbind: Reverses @bind; called as a side effect of unregistering the
+ *	driver which added this function.
+ * @set_alt: (REQUIRED) Reconfigures altsettings; function drivers may
+ *	initialize usb_ep.driver data at this time (when it is used).
+ *	Note that setting an interface to its current altsetting resets
+ *	interface state, and that all interfaces have a disabled state.
+ * @get_alt: Returns the active altsetting.  If this is not provided,
+ *	then only altsetting zero is supported.
+ * @disable: (REQUIRED) Indicates the function should be disabled.  Reasons
+ *	include host resetting or reconfiguring the gadget, and disconnection.
+ * @setup: Used for interface-specific control requests.
+ * @suspend: Notifies functions when the host stops sending USB traffic.
+ * @resume: Notifies functions when the host restarts USB traffic.
+ *
+ * A single USB function uses one or more interfaces, and should in most
+ * cases support operation at both full and high speeds.  Each function is
+ * associated by @usb_add_function() with a one configuration; that function
+ * causes @bind() to be called so resources can be allocated as part of
+ * setting up a gadget driver.  Those resources include endpoints, which
+ * should be allocated using @usb_ep_autoconfig().
+ *
+ * To support dual speed operation, a function driver provides descriptors
+ * for both high and full speed operation.  Except in rare cases that don't
+ * involve bulk endpoints, each speed needs different endpoint descriptors.
+ *
+ * Function drivers choose their own strategies for managing instance data.
+ * The simplest strategy just declares it "static', which means the function
+ * can only be activated once.  If the function needs to be exposed in more
+ * than one configuration at a given speed, it needs to support multiple
+ * usb_function structures (one for each configuration).
+ *
+ * A more complex strategy might encapsulate a @usb_function structure inside
+ * a driver-specific instance structure to allows multiple activations.  An
+ * example of multiple activations might be a CDC ACM function that supports
+ * two or more distinct instances within the same configuration, providing
+ * several independent logical data links to a USB host.
+ */
+struct usb_function {
+	const char			*name;
+	struct usb_gadget_strings	**strings;
+	struct usb_descriptor_header	**descriptors;
+	struct usb_descriptor_header	**hs_descriptors;
+
+	struct usb_configuration	*config;
+
+	/* REVISIT:  bind() functions can be marked __init, which
+	 * makes trouble for section mismatch analysis.  See if
+	 * we can't restructure things to avoid mismatching.
+	 * Related:  unbind() may kfree() but bind() won't...
+	 */
+
+	/* configuration management:  bind/unbind */
+	int			(*bind)(struct usb_configuration *,
+					struct usb_function *);
+	void			(*unbind)(struct usb_configuration *,
+					struct usb_function *);
+
+	/* runtime state management */
+	int			(*set_alt)(struct usb_function *,
+					unsigned interface, unsigned alt);
+	int			(*get_alt)(struct usb_function *,
+					unsigned interface);
+	void			(*disable)(struct usb_function *);
+	int			(*setup)(struct usb_function *,
+					const struct usb_ctrlrequest *);
+	void			(*suspend)(struct usb_function *);
+	void			(*resume)(struct usb_function *);
+
+	/* private: */
+	/* internals */
+	struct list_head		list;
+	DECLARE_BITMAP(endpoints, 32);
+};
+
+int usb_add_function(struct usb_configuration *, struct usb_function *);
+
+int usb_function_deactivate(struct usb_function *);
+int usb_function_activate(struct usb_function *);
+
+int usb_interface_id(struct usb_configuration *, struct usb_function *);
+
+/**
+ * ep_choose - select descriptor endpoint at current device speed
+ * @g: gadget, connected and running at some speed
+ * @hs: descriptor to use for high speed operation
+ * @fs: descriptor to use for full or low speed operation
+ */
+static inline struct usb_endpoint_descriptor *
+ep_choose(struct usb_gadget *g, struct usb_endpoint_descriptor *hs,
+		struct usb_endpoint_descriptor *fs)
+{
+	if (gadget_is_dualspeed(g) && g->speed == USB_SPEED_HIGH)
+		return hs;
+	return fs;
+}
+
+#define	MAX_CONFIG_INTERFACES		16	/* arbitrary; max 255 */
+
+/**
+ * struct usb_configuration - represents one gadget configuration
+ * @label: For diagnostics, describes the configuration.
+ * @strings: Tables of strings, keyed by identifiers assigned during @bind()
+ *	and by language IDs provided in control requests.
+ * @descriptors: Table of descriptors preceding all function descriptors.
+ *	Examples include OTG and vendor-specific descriptors.
+ * @bind: Called from @usb_add_config() to allocate resources unique to this
+ *	configuration and to call @usb_add_function() for each function used.
+ * @unbind: Reverses @bind; called as a side effect of unregistering the
+ *	driver which added this configuration.
+ * @setup: Used to delegate control requests that aren't handled by standard
+ *	device infrastructure or directed at a specific interface.
+ * @bConfigurationValue: Copied into configuration descriptor.
+ * @iConfiguration: Copied into configuration descriptor.
+ * @bmAttributes: Copied into configuration descriptor.
+ * @bMaxPower: Copied into configuration descriptor.
+ * @cdev: assigned by @usb_add_config() before calling @bind(); this is
+ *	the device associated with this configuration.
+ *
+ * Configurations are building blocks for gadget drivers structured around
+ * function drivers.  Simple USB gadgets require only one function and one
+ * configuration, and handle dual-speed hardware by always providing the same
+ * functionality.  Slightly more complex gadgets may have more than one
+ * single-function configuration at a given speed; or have configurations
+ * that only work at one speed.
+ *
+ * Composite devices are, by definition, ones with configurations which
+ * include more than one function.
+ *
+ * The lifecycle of a usb_configuration includes allocation, initialization
+ * of the fields described above, and calling @usb_add_config() to set up
+ * internal data and bind it to a specific device.  The configuration's
+ * @bind() method is then used to initialize all the functions and then
+ * call @usb_add_function() for them.
+ *
+ * Those functions would normally be independant of each other, but that's
+ * not mandatory.  CDC WMC devices are an example where functions often
+ * depend on other functions, with some functions subsidiary to others.
+ * Such interdependency may be managed in any way, so long as all of the
+ * descriptors complete by the time the composite driver returns from
+ * its bind() routine.
+ */
+struct usb_configuration {
+	const char			*label;
+	struct usb_gadget_strings	**strings;
+	const struct usb_descriptor_header **descriptors;
+
+	/* REVISIT:  bind() functions can be marked __init, which
+	 * makes trouble for section mismatch analysis.  See if
+	 * we can't restructure things to avoid mismatching...
+	 */
+
+	/* configuration management:  bind/unbind */
+	int			(*bind)(struct usb_configuration *);
+	void			(*unbind)(struct usb_configuration *);
+	int			(*setup)(struct usb_configuration *,
+					const struct usb_ctrlrequest *);
+
+	/* fields in the config descriptor */
+	u8			bConfigurationValue;
+	u8			iConfiguration;
+	u8			bmAttributes;
+	u8			bMaxPower;
+
+	struct usb_composite_dev	*cdev;
+
+	/* private: */
+	/* internals */
+	struct list_head	list;
+	struct list_head	functions;
+	u8			next_interface_id;
+	unsigned		highspeed:1;
+	unsigned		fullspeed:1;
+	struct usb_function	*interface[MAX_CONFIG_INTERFACES];
+};
+
+int usb_add_config(struct usb_composite_dev *,
+		struct usb_configuration *);
+
+/**
+ * struct usb_composite_driver - groups configurations into a gadget
+ * @name: For diagnostics, identifies the driver.
+ * @dev: Template descriptor for the device, including default device
+ *	identifiers.
+ * @strings: tables of strings, keyed by identifiers assigned during bind()
+ *	and language IDs provided in control requests
+ * @bind: (REQUIRED) Used to allocate resources that are shared across the
+ *	whole device, such as string IDs, and add its configurations using
+ *	@usb_add_config().  This may fail by returning a negative errno
+ *	value; it should return zero on successful initialization.
+ * @unbind: Reverses @bind(); called as a side effect of unregistering
+ *	this driver.
+ * @disconnect: optional driver disconnect method
+ * @suspend: Notifies when the host stops sending USB traffic,
+ *	after function notifications
+ * @resume: Notifies configuration when the host restarts USB traffic,
+ *	before function notifications
+ *
+ * Devices default to reporting self powered operation.  Devices which rely
+ * on bus powered operation should report this in their @bind() method.
+ *
+ * Before returning from @bind, various fields in the template descriptor
+ * may be overridden.  These include the idVendor/idProduct/bcdDevice values
+ * normally to bind the appropriate host side driver, and the three strings
+ * (iManufacturer, iProduct, iSerialNumber) normally used to provide user
+ * meaningful device identifiers.  (The strings will not be defined unless
+ * they are defined in @dev and @strings.)  The correct ep0 maxpacket size
+ * is also reported, as defined by the underlying controller driver.
+ */
+struct usb_composite_driver {
+	const char				*name;
+	const struct usb_device_descriptor	*dev;
+	struct usb_gadget_strings		**strings;
+
+	/* REVISIT:  bind() functions can be marked __init, which
+	 * makes trouble for section mismatch analysis.  See if
+	 * we can't restructure things to avoid mismatching...
+	 */
+
+	int			(*bind)(struct usb_composite_dev *);
+	int			(*unbind)(struct usb_composite_dev *);
+
+	void			(*disconnect)(struct usb_composite_dev *);
+
+	/* global suspend hooks */
+	void			(*suspend)(struct usb_composite_dev *);
+	void			(*resume)(struct usb_composite_dev *);
+};
+
+extern int usb_composite_register(struct usb_composite_driver *);
+extern void usb_composite_unregister(struct usb_composite_driver *);
+
+
+/**
+ * struct usb_composite_device - represents one composite usb gadget
+ * @gadget: read-only, abstracts the gadget's usb peripheral controller
+ * @req: used for control responses; buffer is pre-allocated
+ * @bufsiz: size of buffer pre-allocated in @req
+ * @config: the currently active configuration
+ *
+ * One of these devices is allocated and initialized before the
+ * associated device driver's bind() is called.
+ *
+ * OPEN ISSUE:  it appears that some WUSB devices will need to be
+ * built by combining a normal (wired) gadget with a wireless one.
+ * This revision of the gadget framework should probably try to make
+ * sure doing that won't hurt too much.
+ *
+ * One notion for how to handle Wireless USB devices involves:
+ * (a) a second gadget here, discovery mechanism TBD, but likely
+ *     needing separate "register/unregister WUSB gadget" calls;
+ * (b) updates to usb_gadget to include flags "is it wireless",
+ *     "is it wired", plus (presumably in a wrapper structure)
+ *     bandgroup and PHY info;
+ * (c) presumably a wireless_ep wrapping a usb_ep, and reporting
+ *     wireless-specific parameters like maxburst and maxsequence;
+ * (d) configurations that are specific to wireless links;
+ * (e) function drivers that understand wireless configs and will
+ *     support wireless for (additional) function instances;
+ * (f) a function to support association setup (like CBAF), not
+ *     necessarily requiring a wireless adapter;
+ * (g) composite device setup that can create one or more wireless
+ *     configs, including appropriate association setup support;
+ * (h) more, TBD.
+ */
+struct usb_composite_dev {
+	struct usb_gadget		*gadget;
+	struct usb_request		*req;
+	unsigned			bufsiz;
+
+	struct usb_configuration	*config;
+
+	/* private: */
+	/* internals */
+	unsigned int			suspended:1;
+	struct usb_device_descriptor	desc;
+	struct list_head		configs;
+	struct usb_composite_driver	*driver;
+	u8				next_string_id;
+
+	/* the gadget driver won't enable the data pullup
+	 * while the deactivation count is nonzero.
+	 */
+	unsigned			deactivations;
+};
+
+extern int usb_string_id(struct usb_composite_dev *c);
+extern int usb_string_ids_tab(struct usb_composite_dev *c,
+			      struct usb_string *str);
+extern int usb_string_ids_n(struct usb_composite_dev *c, unsigned n);
+
+#endif	/* __LINUX_USB_COMPOSITE_H */
diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h
index 275cb5fe15..eba865ea09 100644
--- a/include/linux/usb/gadget.h
+++ b/include/linux/usb/gadget.h
@@ -411,6 +411,7 @@ struct usb_gadget_ops {
 
 struct device {
 	void		*driver_data;	/* data private to the driver */
+	void            *device_data;   /* data private to the device */
 };
 
 /**
@@ -481,6 +482,11 @@ static inline void *get_gadget_data(struct usb_gadget *gadget)
 	return gadget->dev.driver_data;
 }
 
+static inline struct usb_gadget *dev_to_usb_gadget(struct device *dev)
+{
+	return container_of(dev, struct usb_gadget, dev);
+}
+
 /* iterates the non-control endpoints; 'tmp' is a struct usb_ep pointer */
 #define gadget_for_each_ep(tmp, gadget) \
 	list_for_each_entry(tmp, &(gadget)->ep_list, ep_list)
diff --git a/include/max8997_pmic.h b/include/max8997_pmic.h
new file mode 100644
index 0000000000..17ae24ea6a
--- /dev/null
+++ b/include/max8997_pmic.h
@@ -0,0 +1,190 @@
+/*
+ *  Copyright (C) 2011 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MAX8997_PMIC_H_
+#define __MAX8997_PMIC_H_
+
+/* MAX 8997 registers */
+enum {
+	MAX8997_REG_PMIC_ID0	= 0x00,
+	MAX8997_REG_PMIC_ID1	= 0x01,
+	MAX8997_REG_INTSRC	= 0x02,
+	MAX8997_REG_INT1	= 0x03,
+	MAX8997_REG_INT2	= 0x04,
+	MAX8997_REG_INT3	= 0x05,
+	MAX8997_REG_INT4	= 0x06,
+
+	MAX8997_REG_INT1MSK	= 0x08,
+	MAX8997_REG_INT2MSK	= 0x09,
+	MAX8997_REG_INT3MSK	= 0x0a,
+	MAX8997_REG_INT4MSK	= 0x0b,
+
+	MAX8997_REG_STATUS1	= 0x0d,
+	MAX8997_REG_STATUS2	= 0x0e,
+	MAX8997_REG_STATUS3	= 0x0f,
+	MAX8997_REG_STATUS4	= 0x10,
+
+	MAX8997_REG_MAINCON1	= 0x13,
+	MAX8997_REG_MAINCON2	= 0x14,
+	MAX8997_REG_BUCKRAMP	= 0x15,
+
+	MAX8997_REG_BUCK1CTRL	= 0x18,
+	MAX8997_REG_BUCK1DVS1	= 0x19,
+	MAX8997_REG_BUCK1DVS2	= 0x1a,
+	MAX8997_REG_BUCK1DVS3	= 0x1b,
+	MAX8997_REG_BUCK1DVS4	= 0x1c,
+	MAX8997_REG_BUCK1DVS5	= 0x1d,
+	MAX8997_REG_BUCK1DVS6	= 0x1e,
+	MAX8997_REG_BUCK1DVS7	= 0x1f,
+	MAX8997_REG_BUCK1DVS8	= 0x20,
+	MAX8997_REG_BUCK2CTRL	= 0x21,
+	MAX8997_REG_BUCK2DVS1	= 0x22,
+	MAX8997_REG_BUCK2DVS2	= 0x23,
+	MAX8997_REG_BUCK2DVS3	= 0x24,
+	MAX8997_REG_BUCK2DVS4	= 0x25,
+	MAX8997_REG_BUCK2DVS5	= 0x26,
+	MAX8997_REG_BUCK2DVS6	= 0x27,
+	MAX8997_REG_BUCK2DVS7	= 0x28,
+	MAX8997_REG_BUCK2DVS8	= 0x29,
+	MAX8997_REG_BUCK3CTRL	= 0x2a,
+	MAX8997_REG_BUCK3DVS	= 0x2b,
+	MAX8997_REG_BUCK4CTRL	= 0x2c,
+	MAX8997_REG_BUCK4DVS	= 0x2d,
+	MAX8997_REG_BUCK5CTRL	= 0x2e,
+	MAX8997_REG_BUCK5DVS1	= 0x2f,
+	MAX8997_REG_BUCK5DVS2	= 0x30,
+	MAX8997_REG_BUCK5DVS3	= 0x31,
+	MAX8997_REG_BUCK5DVS4	= 0x32,
+	MAX8997_REG_BUCK5DVS5	= 0x33,
+	MAX8997_REG_BUCK5DVS6	= 0x34,
+	MAX8997_REG_BUCK5DVS7	= 0x35,
+	MAX8997_REG_BUCK5DVS8	= 0x36,
+	MAX8997_REG_BUCK6CTRL	= 0x37,
+	MAX8997_REG_BUCK6BPSKIPCTRL	= 0x38,
+	MAX8997_REG_BUCK7CTRL	= 0x39,
+	MAX8997_REG_BUCK7DVS	= 0x3a,
+	MAX8997_REG_LDO1CTRL	= 0x3b,
+	MAX8997_REG_LDO2CTRL	= 0x3c,
+	MAX8997_REG_LDO3CTRL	= 0x3d,
+	MAX8997_REG_LDO4CTRL	= 0x3e,
+	MAX8997_REG_LDO5CTRL	= 0x3f,
+	MAX8997_REG_LDO6CTRL	= 0x40,
+	MAX8997_REG_LDO7CTRL	= 0x41,
+	MAX8997_REG_LDO8CTRL	= 0x42,
+	MAX8997_REG_LDO9CTRL	= 0x43,
+	MAX8997_REG_LDO10CTRL	= 0x44,
+	MAX8997_REG_LDO11CTRL	= 0x45,
+	MAX8997_REG_LDO12CTRL	= 0x46,
+	MAX8997_REG_LDO13CTRL	= 0x47,
+	MAX8997_REG_LDO14CTRL	= 0x48,
+	MAX8997_REG_LDO15CTRL	= 0x49,
+	MAX8997_REG_LDO16CTRL	= 0x4a,
+	MAX8997_REG_LDO17CTRL	= 0x4b,
+	MAX8997_REG_LDO18CTRL	= 0x4c,
+	MAX8997_REG_LDO21CTRL	= 0x4d,
+
+	MAX8997_REG_MBCCTRL1	= 0x50,
+	MAX8997_REG_MBCCTRL2	= 0x51,
+	MAX8997_REG_MBCCTRL3	= 0x52,
+	MAX8997_REG_MBCCTRL4	= 0x53,
+	MAX8997_REG_MBCCTRL5	= 0x54,
+	MAX8997_REG_MBCCTRL6	= 0x55,
+	MAX8997_REG_OTPCGHCVS	= 0x56,
+
+	MAX8997_REG_SAFEOUTCTRL	= 0x5a,
+
+	MAX8997_REG_LBCNFG1	= 0x5e,
+	MAX8997_REG_LBCNFG2	= 0x5f,
+	MAX8997_REG_BBCCTRL	= 0x60,
+
+	MAX8997_REG_FLASH1_CUR	= 0x63, /* 0x63 ~ 0x6e for FLASH */
+	MAX8997_REG_FLASH2_CUR	= 0x64,
+	MAX8997_REG_MOVIE_CUR	= 0x65,
+	MAX8997_REG_GSMB_CUR	= 0x66,
+	MAX8997_REG_BOOST_CNTL	= 0x67,
+	MAX8997_REG_LEN_CNTL	= 0x68,
+	MAX8997_REG_FLASH_CNTL	= 0x69,
+	MAX8997_REG_WDT_CNTL	= 0x6a,
+	MAX8997_REG_MAXFLASH1	= 0x6b,
+	MAX8997_REG_MAXFLASH2	= 0x6c,
+	MAX8997_REG_FLASHSTATUS	= 0x6d,
+	MAX8997_REG_FLASHSTATUSMASK	= 0x6e,
+
+	MAX8997_REG_GPIOCNTL1	= 0x70,
+	MAX8997_REG_GPIOCNTL2	= 0x71,
+	MAX8997_REG_GPIOCNTL3	= 0x72,
+	MAX8997_REG_GPIOCNTL4	= 0x73,
+	MAX8997_REG_GPIOCNTL5	= 0x74,
+	MAX8997_REG_GPIOCNTL6	= 0x75,
+	MAX8997_REG_GPIOCNTL7	= 0x76,
+	MAX8997_REG_GPIOCNTL8	= 0x77,
+	MAX8997_REG_GPIOCNTL9	= 0x78,
+	MAX8997_REG_GPIOCNTL10	= 0x79,
+	MAX8997_REG_GPIOCNTL11	= 0x7a,
+	MAX8997_REG_GPIOCNTL12	= 0x7b,
+
+	MAX8997_REG_LDO1CONFIG	= 0x80,
+	MAX8997_REG_LDO2CONFIG	= 0x81,
+	MAX8997_REG_LDO3CONFIG	= 0x82,
+	MAX8997_REG_LDO4CONFIG	= 0x83,
+	MAX8997_REG_LDO5CONFIG	= 0x84,
+	MAX8997_REG_LDO6CONFIG	= 0x85,
+	MAX8997_REG_LDO7CONFIG	= 0x86,
+	MAX8997_REG_LDO8CONFIG	= 0x87,
+	MAX8997_REG_LDO9CONFIG	= 0x88,
+	MAX8997_REG_LDO10CONFIG	= 0x89,
+	MAX8997_REG_LDO11CONFIG	= 0x8a,
+	MAX8997_REG_LDO12CONFIG	= 0x8b,
+	MAX8997_REG_LDO13CONFIG	= 0x8c,
+	MAX8997_REG_LDO14CONFIG	= 0x8d,
+	MAX8997_REG_LDO15CONFIG	= 0x8e,
+	MAX8997_REG_LDO16CONFIG	= 0x8f,
+	MAX8997_REG_LDO17CONFIG	= 0x90,
+	MAX8997_REG_LDO18CONFIG	= 0x91,
+	MAX8997_REG_LDO21CONFIG	= 0x92,
+
+	MAX8997_REG_DVSOKTIMER1	= 0x97,
+	MAX8997_REG_DVSOKTIMER2	= 0x98,
+	MAX8997_REG_DVSOKTIMER4	= 0x99,
+	MAX8997_REG_DVSOKTIMER5	= 0x9a,
+
+	PMIC_NUM_OF_REGS = 0x9b,
+};
+
+#define ENSAFEOUT1 (1 << 6)
+#define ENSAFEOUT2 (1 << 7)
+
+#define MAX8997_I2C_ADDR        (0xCC >> 1)
+#define MAX8997_RTC_ADDR	(0x0C >> 1)
+#define MAX8997_MUIC_ADDR	(0x4A >> 1)
+#define MAX8997_FG_ADDR	(0x6C >> 1)
+
+enum {
+	LDO_OFF = 0,
+	LDO_ON = 1,
+
+	DIS_LDO = (0x00 << 6),
+	EN_LDO = (0x3 << 6),
+};
+
+#endif /* __MAX8997_PMIC_H_ */
diff --git a/include/max8998_pmic.h b/include/max8998_pmic.h
index 10c892a51d..ca21f882c2 100644
--- a/include/max8998_pmic.h
+++ b/include/max8998_pmic.h
@@ -75,6 +75,7 @@ enum {
 };
 
 #define MAX8998_LDO3		(1 << 2)
+#define MAX8998_LDO4		(1 << 1)
 #define MAX8998_LDO8		(1 << 5)
 #define MAX8998_SAFEOUT1	(1 << 4)
 
diff --git a/include/mmc.h b/include/mmc.h
index f52df70ad4..70a54034a9 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -4,48 +4,43 @@
  *
  * Based (loosely) on the Linux code
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef _MMC_H_
 #define _MMC_H_
 
 #include <linux/list.h>
+#include <linux/compiler.h>
 
 #define SD_VERSION_SD	0x20000
-#define SD_VERSION_2	(SD_VERSION_SD | 0x20)
-#define SD_VERSION_1_0	(SD_VERSION_SD | 0x10)
-#define SD_VERSION_1_10	(SD_VERSION_SD | 0x1a)
+#define SD_VERSION_3	(SD_VERSION_SD | 0x300)
+#define SD_VERSION_2	(SD_VERSION_SD | 0x200)
+#define SD_VERSION_1_0	(SD_VERSION_SD | 0x100)
+#define SD_VERSION_1_10	(SD_VERSION_SD | 0x10a)
 #define MMC_VERSION_MMC		0x10000
 #define MMC_VERSION_UNKNOWN	(MMC_VERSION_MMC)
-#define MMC_VERSION_1_2		(MMC_VERSION_MMC | 0x12)
-#define MMC_VERSION_1_4		(MMC_VERSION_MMC | 0x14)
-#define MMC_VERSION_2_2		(MMC_VERSION_MMC | 0x22)
-#define MMC_VERSION_3		(MMC_VERSION_MMC | 0x30)
-#define MMC_VERSION_4		(MMC_VERSION_MMC | 0x40)
-
-#define MMC_MODE_HS		0x001
-#define MMC_MODE_HS_52MHz	0x010
-#define MMC_MODE_4BIT		0x100
-#define MMC_MODE_8BIT		0x200
-#define MMC_MODE_SPI		0x400
-#define MMC_MODE_HC		0x800
+#define MMC_VERSION_1_2		(MMC_VERSION_MMC | 0x102)
+#define MMC_VERSION_1_4		(MMC_VERSION_MMC | 0x104)
+#define MMC_VERSION_2_2		(MMC_VERSION_MMC | 0x202)
+#define MMC_VERSION_3		(MMC_VERSION_MMC | 0x300)
+#define MMC_VERSION_4		(MMC_VERSION_MMC | 0x400)
+#define MMC_VERSION_4_1		(MMC_VERSION_MMC | 0x401)
+#define MMC_VERSION_4_2		(MMC_VERSION_MMC | 0x402)
+#define MMC_VERSION_4_3		(MMC_VERSION_MMC | 0x403)
+#define MMC_VERSION_4_41	(MMC_VERSION_MMC | 0x429)
+#define MMC_VERSION_4_5		(MMC_VERSION_MMC | 0x405)
+
+#define MMC_MODE_HS		(1 << 0)
+#define MMC_MODE_HS_52MHz	(1 << 1)
+#define MMC_MODE_4BIT		(1 << 2)
+#define MMC_MODE_8BIT		(1 << 3)
+#define MMC_MODE_SPI		(1 << 4)
+#define MMC_MODE_HC		(1 << 5)
+#define MMC_MODE_DDR_52MHz	(1 << 6)
+
+#define MMC_MODE_MASK_WIDTH_BITS (MMC_MODE_4BIT | MMC_MODE_8BIT)
+#define MMC_MODE_WIDTH_BITS_SHIFT 8
 
 #define SD_DATA_4BIT	0x00040000
 
@@ -58,6 +53,8 @@
 #define UNUSABLE_ERR		-17 /* Unusable Card */
 #define COMM_ERR		-18 /* Communications Error */
 #define TIMEOUT			-19
+#define IN_PROGRESS		-20 /* operation is in progress */
+#define SWITCH_ERR		-21 /* Card reports failure to switch mode */
 
 #define MMC_CMD_GO_IDLE_STATE		0
 #define MMC_CMD_SEND_OP_COND		1
@@ -74,6 +71,7 @@
 #define MMC_CMD_SET_BLOCKLEN		16
 #define MMC_CMD_READ_SINGLE_BLOCK	17
 #define MMC_CMD_READ_MULTIPLE_BLOCK	18
+#define MMC_CMD_SET_BLOCK_COUNT         23
 #define MMC_CMD_WRITE_SINGLE_BLOCK	24
 #define MMC_CMD_WRITE_MULTIPLE_BLOCK	25
 #define MMC_CMD_ERASE_GROUP_START	35
@@ -82,6 +80,11 @@
 #define MMC_CMD_APP_CMD			55
 #define MMC_CMD_SPI_READ_OCR		58
 #define MMC_CMD_SPI_CRC_ON_OFF		59
+#define MMC_CMD_RES_MAN			62
+
+#define MMC_CMD62_ARG1			0xefac62ec
+#define MMC_CMD62_ARG2			0xcbaea7
+
 
 #define SD_CMD_SEND_RELATIVE_ADDR	3
 #define SD_CMD_SWITCH_FUNC		6
@@ -108,6 +111,7 @@
 #define SECURE_ERASE		0x80000000
 
 #define MMC_STATUS_MASK		(~0x0206BF7F)
+#define MMC_STATUS_SWITCH_ERROR	(1 << 7)
 #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
 #define MMC_STATUS_CURR_STATE	(0xf << 9)
 #define MMC_STATUS_ERROR	(1 << 19)
@@ -147,15 +151,21 @@
 /*
  * EXT_CSD fields
  */
+#define EXT_CSD_GP_SIZE_MULT		143	/* R/W */
+#define EXT_CSD_PARTITIONS_ATTRIBUTE	156	/* R/W */
 #define EXT_CSD_PARTITIONING_SUPPORT	160	/* RO */
+#define EXT_CSD_RPMB_MULT		168	/* RO */
 #define EXT_CSD_ERASE_GROUP_DEF		175	/* R/W */
+#define EXT_CSD_BOOT_BUS_WIDTH		177
 #define EXT_CSD_PART_CONF		179	/* R/W */
 #define EXT_CSD_BUS_WIDTH		183	/* R/W */
 #define EXT_CSD_HS_TIMING		185	/* R/W */
 #define EXT_CSD_REV			192	/* RO */
 #define EXT_CSD_CARD_TYPE		196	/* RO */
 #define EXT_CSD_SEC_CNT			212	/* RO, 4 bytes */
+#define EXT_CSD_HC_WP_GRP_SIZE		221	/* RO */
 #define EXT_CSD_HC_ERASE_GRP_SIZE	224	/* RO */
+#define EXT_CSD_BOOT_MULT		226	/* RO */
 
 /*
  * EXT_CSD field definitions
@@ -167,10 +177,26 @@
 
 #define EXT_CSD_CARD_TYPE_26	(1 << 0)	/* Card can run at 26MHz */
 #define EXT_CSD_CARD_TYPE_52	(1 << 1)	/* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_DDR_1_8V	(1 << 2)
+#define EXT_CSD_CARD_TYPE_DDR_1_2V	(1 << 3)
+#define EXT_CSD_CARD_TYPE_DDR_52	(EXT_CSD_CARD_TYPE_DDR_1_8V \
+					| EXT_CSD_CARD_TYPE_DDR_1_2V)
 
 #define EXT_CSD_BUS_WIDTH_1	0	/* Card is in 1 bit mode */
 #define EXT_CSD_BUS_WIDTH_4	1	/* Card is in 4 bit mode */
 #define EXT_CSD_BUS_WIDTH_8	2	/* Card is in 8 bit mode */
+#define EXT_CSD_DDR_BUS_WIDTH_4	5	/* Card is in 4 bit DDR mode */
+#define EXT_CSD_DDR_BUS_WIDTH_8	6	/* Card is in 8 bit DDR mode */
+
+#define EXT_CSD_BOOT_ACK_ENABLE			(1 << 6)
+#define EXT_CSD_BOOT_PARTITION_ENABLE		(1 << 3)
+#define EXT_CSD_PARTITION_ACCESS_ENABLE		(1 << 0)
+#define EXT_CSD_PARTITION_ACCESS_DISABLE	(0 << 0)
+
+#define EXT_CSD_BOOT_ACK(x)		(x << 6)
+#define EXT_CSD_BOOT_PART_NUM(x)	(x << 3)
+#define EXT_CSD_PARTITION_ACCESS(x)	(x << 0)
+
 
 #define R1_ILLEGAL_COMMAND		(1 << 22)
 #define R1_APP_CMD			(1 << 5)
@@ -195,6 +221,26 @@
 #define MMCPART_NOAVAILABLE	(0xff)
 #define PART_ACCESS_MASK	(0x7)
 #define PART_SUPPORT		(0x1)
+#define PART_ENH_ATTRIB		(0x1f)
+
+/*
+ * MMC Flash Manufacturer ID Codes
+ */
+#define MMC_MFR_TOSHIBA		0x11
+#define MMC_MFR_SAMSUNG		0x15
+#define MMC_MFR_SANDISK		0x45
+#define MMC_MFR_HYNIX		0x90
+#define MMC_MFR_MICRON		0x13
+#define MMC_MFR_MICRON1		0xfe
+#define MMC_MFR_GIGADEVICE	0xC8
+
+/* Maximum block size for MMC */
+#define MMC_MAX_BLOCK_LEN	512
+
+/* The number of MMC physical partitions.  These consist of:
+ * boot partitions (2), general purpose partitions (4) in MMC v4.4.
+ */
+#define MMC_NUM_BOOT_PARTITION	2
 
 struct mmc_cid {
 	unsigned long psn;
@@ -205,54 +251,14 @@ struct mmc_cid {
 	char pnm[7];
 };
 
-/*
- * WARNING!
- *
- * This structure is used by atmel_mci.c only.
- * It works for the AVR32 architecture but NOT
- * for ARM/AT91 architectures.
- * Its use is highly depreciated.
- * After the atmel_mci.c driver for AVR32 has
- * been replaced this structure will be removed.
- */
-struct mmc_csd
-{
-	u8	csd_structure:2,
-		spec_vers:4,
-		rsvd1:2;
-	u8	taac;
-	u8	nsac;
-	u8	tran_speed;
-	u16	ccc:12,
-		read_bl_len:4;
-	u64	read_bl_partial:1,
-		write_blk_misalign:1,
-		read_blk_misalign:1,
-		dsr_imp:1,
-		rsvd2:2,
-		c_size:12,
-		vdd_r_curr_min:3,
-		vdd_r_curr_max:3,
-		vdd_w_curr_min:3,
-		vdd_w_curr_max:3,
-		c_size_mult:3,
-		sector_size:5,
-		erase_grp_size:5,
-		wp_grp_size:5,
-		wp_grp_enable:1,
-		default_ecc:2,
-		r2w_factor:3,
-		write_bl_len:4,
-		write_bl_partial:1,
-		rsvd3:5;
-	u8	file_format_grp:1,
-		copy:1,
-		perm_write_protect:1,
-		tmp_write_protect:1,
-		file_format:2,
-		ecc:2;
-	u8	crc:7;
-	u8	one:1;
+/**
+ * struct mmc_manufacturers - MMC Flash Manufacturer ID Structure
+ * @name:	Manufacturer name
+ * @id:		manufacturer ID code of device.
+*/
+struct mmc_manufacturers {
+	int id;
+	char *name;
 };
 
 struct mmc_cmd {
@@ -260,7 +266,6 @@ struct mmc_cmd {
 	uint resp_type;
 	uint cmdarg;
 	uint response[4];
-	uint flags;
 };
 
 struct mmc_data {
@@ -299,19 +304,30 @@ struct mmc {
 	uint write_bl_len;
 	uint erase_grp_size;
 	u64 capacity;
+	u64 capacity_user;
+	u64 capacity_boot;
+	u64 capacity_rpmb;
+	u64 capacity_gp[4];
 	block_dev_desc_t block_dev;
 	int (*send_cmd)(struct mmc *mmc,
 			struct mmc_cmd *cmd, struct mmc_data *data);
 	void (*set_ios)(struct mmc *mmc);
 	int (*init)(struct mmc *mmc);
 	int (*getcd)(struct mmc *mmc);
+	int (*getwp)(struct mmc *mmc);
 	uint b_max;
+	char op_cond_pending;	/* 1 if we are waiting on an op_cond command */
+	char init_in_progress;	/* 1 if we have done mmc_start_init() */
+	char preinit;		/* start init as early as possible */
+	uint op_cond_response;	/* the response byte from the last op_cond */
 };
 
 int mmc_register(struct mmc *mmc);
 int mmc_initialize(bd_t *bis);
 int mmc_init(struct mmc *mmc);
 int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
+int mmc_write(struct mmc *mmc, u64 to, uchar *buf, int size);
+int mmc_erase(unsigned int from, unsigned int size);
 void mmc_set_clock(struct mmc *mmc, uint clock);
 struct mmc *find_mmc_device(int dev_num);
 int mmc_set_dev(int dev_num);
@@ -320,9 +336,45 @@ int get_mmc_num(void);
 int board_mmc_getcd(struct mmc *mmc);
 int mmc_switch_part(int dev_num, unsigned int part_num);
 int mmc_getcd(struct mmc *mmc);
+int mmc_getwp(struct mmc *mmc);
+void spl_mmc_load(void) __noreturn;
+/* Function to change the size of boot partition and rpmb partitions */
+int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
+					unsigned long rpmbsize);
+/* Function to send commands to open/close the specified boot partition */
+int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
+
+/**
+ * Start device initialization and return immediately; it does not block on
+ * polling OCR (operation condition register) status.  Then you should call
+ * mmc_init, which would block on polling OCR status and complete the device
+ * initializatin.
+ *
+ * @param mmc	Pointer to a MMC device struct
+ * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
+ */
+int mmc_start_init(struct mmc *mmc);
+
+/**
+ * Set preinit flag of mmc device.
+ *
+ * This will cause the device to be pre-inited during mmc_initialize(),
+ * which may save boot time if the device is not accessed until later.
+ * Some eMMC devices take 200-300ms to init, but unfortunately they
+ * must be sent a series of commands to even get them to start preparing
+ * for operation.
+ *
+ * @param mmc		Pointer to a MMC device struct
+ * @param preinit	preinit flag value
+ */
+void mmc_set_preinit(struct mmc *mmc, int preinit);
 
 #ifdef CONFIG_GENERIC_MMC
+#ifdef CONFIG_MMC_SPI
 #define mmc_host_is_spi(mmc)	((mmc)->host_caps & MMC_MODE_SPI)
+#else
+#define mmc_host_is_spi(mmc)	0
+#endif
 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
 #else
 int mmc_legacy_init(int verbose);
diff --git a/include/mmc/mmcpart.h b/include/mmc/mmcpart.h
new file mode 100644
index 0000000000..285eb7cdf8
--- /dev/null
+++ b/include/mmc/mmcpart.h
@@ -0,0 +1,36 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+ *   * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MMC_PARTITION_PARSER_H__
+#define __MMC_PARTITION_PARSER_H__
+#include <mmc.h>
+
+int mmc_parts_init(void);
+int mmc_parts_format(void);
+#endif
+
diff --git a/include/mmc/sparse.h b/include/mmc/sparse.h
new file mode 100644
index 0000000000..ecd0edee2e
--- /dev/null
+++ b/include/mmc/sparse.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2010 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+typedef struct sparse_header {
+  uint32_t  	magic;		/* 0xed26ff3a */
+  uint16_t	major_version;	/* (0x1) - reject images with higher major versions */
+  uint16_t	minor_version;	/* (0x0) - allow images with higer minor versions */
+  uint16_t	file_hdr_sz;	/* 28 bytes for first revision of the file format */
+  uint16_t	chunk_hdr_sz;	/* 12 bytes for first revision of the file format */
+  uint32_t	blk_sz;		/* block size in bytes, must be a multiple of 4 (4096) */
+  uint32_t	total_blks;	/* total blocks in the non-sparse output image */
+  uint32_t	total_chunks;	/* total chunks in the sparse input image */
+  uint32_t	image_checksum; /* CRC32 checksum of the original data, counting "don't care" */
+				/* as 0. Standard 802.3 polynomial, use a Public Domain */
+				/* table implementation */
+} sparse_header_t;
+
+#define SPARSE_HEADER_MAGIC	0xed26ff3a
+
+#define CHUNK_TYPE_RAW		0xCAC1
+#define CHUNK_TYPE_FILL		0xCAC2
+#define CHUNK_TYPE_DONT_CARE	0xCAC3
+#define CHUNK_TYPE_CRC		0xCAC4
+
+typedef struct chunk_header {
+  uint16_t	chunk_type;	/* 0xCAC1 -> raw; 0xCAC2 -> fill; 0xCAC3 -> don't care */
+  uint16_t	reserved1;
+  uint32_t	chunk_sz;	/* in blocks in output image */
+  uint32_t	total_sz;	/* in bytes of chunk input file including chunk header and data */
+} chunk_header_t;
+
+/* Following a Raw or Fill chunk is data.  For a Raw chunk, it's the data in chunk_sz * blk_sz.
+ *  For a Fill chunk, it's 4 bytes of the fill data.
+ */
+
diff --git a/include/mtd/nand/rda_nand.h b/include/mtd/nand/rda_nand.h
new file mode 100644
index 0000000000..58edd54687
--- /dev/null
+++ b/include/mtd/nand/rda_nand.h
@@ -0,0 +1,121 @@
+#ifndef __RDA_NAND_H__
+#define __RDA_NAND_H__
+
+#include <asm/arch-rda/rda_sys.h>
+
+typedef enum
+{
+    NAND_MSG_LEN_1K        = 0,
+    NAND_MSG_LEN_2K        = 1,
+    NAND_MSG_LEN_4K        = 2,
+    NAND_MSG_LEN_1152      = 3
+} NAND_ECC_MSG_LEN_TYPE;
+
+typedef enum
+{
+    NAND_OOB_LEN_32         = 0,
+    NAND_OOB_LEN_16         = 1
+} NAND_OOB_LEN_TYPE;
+
+typedef enum
+{
+    NAND_BUS_WIDTH_8BIT     = 0,
+    NAND_BUS_WIDTH_16BIT    = 1
+} NAND_BUS_WIDTH_TYPE;
+
+typedef union
+{
+    struct{
+        unsigned short pagesize:2;
+        unsigned short eccmode:4;
+        unsigned short eccmsglen:2;
+        unsigned short ooblen:1;
+    };
+    unsigned short reg;
+}EFUSE_NAND_INFO_T;
+
+typedef enum
+{
+    NAND_PARAMETER_BY_GPIO         = 0,
+    NAND_PARAMETER_BY_NAND        = 1
+} NAND_PARAMETER_MODE_TYPE;
+
+/*************************************************************/
+
+#define RDA_EFUSE_INDEX_NAND_INFO        (4)
+
+/*
+  Fuse layout:low 9 bit
+	O.MM.VVVV.NN
+  NN: NAND_PAGE_TYPE
+  VVVV:NAND_ECC_TYPE
+  MM:NAND_ECC_MSG_LEN
+  O:OOB LEN
+*/
+/* define bit for rda nand info config */
+#define RDA_NAND_PAGESIZE_INDEX(n)         (((n)&0x3)<<0)
+#define RDA_NAND_GET_PAGESIZE(r)     (((r)>>0)&0x3)
+#define RDA_NAND_ECCMODE(n)         (((n)&0xF)<<2)
+#define RDA_NAND_GET_ECCMODE(r)     (((r)>>2)&0xF)
+#define RDA_NAND_ECCMSGLEN(n)         (((n)&0x3)<<6)
+#define RDA_NAND_GET_ECCMSGLEN(r)     (((r)>>6)&0x3)
+#define RDA_NAND_OOBLEN(n)         (((n)&0x1)<<8)
+#define RDA_NAND_GET_OOBLEN(r)     (((r)>>8)&0x1)
+/**************************************************************/
+
+struct rda_nand_info {
+	int type;
+	int hard_ecc_hec;
+	int ecc_mode;
+	int bus_width_16;
+	int page_num_per_block;
+
+	int page_size;
+	int erase_size;
+	int page_shift;
+	int oob_size;
+
+	int vir_page_size;
+	int vir_erase_size;
+	int vir_page_shift;
+	int vir_oob_size;
+
+	int cmd;
+	int col_addr;
+	int page_addr;
+	int read_ptr;
+	u32 byte_buf[4];	// for read_id, status, etc
+	int index;
+	int write_ptr;
+	void __iomem *nand_data_phys;
+	u8 dma_ch;
+	unsigned long master_clk;
+	unsigned long clk;
+	int cmd_flag;
+
+	u8 spl_adjust_ratio;
+	/*specially for nand dump command to read first 16K of nand v3.*/
+	u8 dump_debug_flag;
+	/*8810:8K/16k setting*/
+	/*nand_use_type = 1: 8K used as 2 4k or 3K*/
+	/*nand_use_type = 3: 16K used as 4 4k or 3K*/
+	/*nand_use_type = 0: 2K or  4k*/
+	u8  nand_use_type;
+	int logic_page_size;
+	int logic_oob_size;
+	int logic_operate_time;
+	/* rda8850e use*/
+	int page_total_num;
+	unsigned short flash_oob_off;
+	unsigned short message_len;
+	u32	bch_data;
+	u32	bch_oob;
+	u16 ecc_mode_bak;
+	u16 max_eccmode_support;
+	u8 type_bak;
+	NAND_PARAMETER_MODE_TYPE parameter_mode_select;
+	u32 spl_logic_pageaddr;
+	u32 boot_logic_end_pageaddr;
+};
+#endif
+
diff --git a/include/nand.h b/include/nand.h
index 8b3a1a77a3..3b9d510ad1 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -37,7 +37,7 @@
 
 extern void nand_init(void);
 
-#include <linux/mtd/compat.h>
+#include <linux/compat.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 
@@ -53,22 +53,24 @@ typedef struct mtd_info nand_info_t;
 extern int nand_curr_device;
 extern nand_info_t nand_info[];
 
-static inline int nand_read(nand_info_t *info, loff_t ofs, size_t *len, u_char *buf)
+static inline int nand_read(nand_info_t * info, loff_t ofs, size_t * len,
+			    u_char * buf)
 {
-	return info->read(info, ofs, *len, (size_t *)len, buf);
+	return info->read(info, ofs, *len, (size_t *) len, buf);
 }
 
-static inline int nand_write(nand_info_t *info, loff_t ofs, size_t *len, u_char *buf)
+static inline int nand_write(nand_info_t * info, loff_t ofs, size_t * len,
+			     u_char * buf)
 {
-	return info->write(info, ofs, *len, (size_t *)len, buf);
+	return info->write(info, ofs, *len, (size_t *) len, buf);
 }
 
-static inline int nand_block_isbad(nand_info_t *info, loff_t ofs)
+static inline int nand_block_isbad(nand_info_t * info, loff_t ofs)
 {
 	return info->block_isbad(info, ofs);
 }
 
-static inline int nand_erase(nand_info_t *info, loff_t off, size_t size)
+static inline int nand_erase(nand_info_t * info, loff_t off, size_t size)
 {
 	struct erase_info instr;
 
@@ -80,7 +82,6 @@ static inline int nand_erase(nand_info_t *info, loff_t off, size_t size)
 	return info->erase(info, &instr);
 }
 
-
 /*****************************************************************************
  * declarations from nand_util.c
  ****************************************************************************/
@@ -104,7 +105,7 @@ typedef struct nand_write_options nand_write_options_t;
 typedef struct mtd_oob_ops mtd_oob_ops_t;
 
 struct nand_read_options {
-	u_char *buffer;		/* memory block in which read image is written*/
+	u_char *buffer;		/* memory block in which read image is written */
 	ulong length;		/* number of bytes to read */
 	ulong offset;		/* start address in NAND */
 	int quiet;		/* don't display progress messages */
@@ -128,42 +129,55 @@ struct nand_erase_options {
 
 typedef struct nand_erase_options nand_erase_options_t;
 
-int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
-		       u_char *buffer);
-
-#define WITH_YAFFS_OOB	(1 << 0) /* whether write with yaffs format. This flag
-				  * is a 'mode' meaning it cannot be mixed with
-				  * other flags */
-#define WITH_DROP_FFS	(1 << 1) /* drop trailing all-0xff pages */
-
-int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
-			u_char *buffer, int flags);
-int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts);
+int nand_read_skip_bad(nand_info_t * nand, loff_t offset, size_t * length,
+		       u_char * buffer);
+
+#define WITH_YAFFS_OOB	(1 << 0)	/* whether write with yaffs format. This flag
+					 * is a 'mode' meaning it cannot be mixed with
+					 * other flags */
+#define WITH_DROP_FFS	(1 << 1)	/* drop trailing all-0xff pages */
+
+int nand_erase_opts(nand_info_t * meminfo, const nand_erase_options_t * opts);
+int nand_write_skip_bad(nand_info_t * nand, loff_t offset, size_t * length,
+			u_char * buffer, int flags);
+int nand_write_skip_bad_new(nand_info_t * nand, loff_t offset, size_t * length,
+			    loff_t max_limit, u_char * buffer,
+			    int flags, u32 * skip_blocks);
+int nand_write_unsparse(nand_info_t * nand, loff_t offset, size_t * length,
+			loff_t max_limit, u_char * buffer,
+			int flags, u32 * skip_blocks);
+int nand_read_skip_bad_new(nand_info_t * nand, loff_t offset, size_t * length,
+			   u_char * buffer, u32 * skip_blocks);
 
 #define NAND_LOCK_STATUS_TIGHT	0x01
 #define NAND_LOCK_STATUS_LOCK	0x02
 #define NAND_LOCK_STATUS_UNLOCK 0x04
 
-int nand_lock( nand_info_t *meminfo, int tight );
-int nand_unlock( nand_info_t *meminfo, ulong start, ulong length );
-int nand_get_lock_status(nand_info_t *meminfo, loff_t offset);
+int nand_lock(nand_info_t * meminfo, int tight);
+int nand_unlock(nand_info_t * meminfo, ulong start, ulong length);
+int nand_get_lock_status(nand_info_t * meminfo, loff_t offset);
 
-int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst);
+int nand_spl_load_image(uint64_t offs, uint64_t size, void *dst);
 void nand_deselect(void);
-
+int nand_spl_read_skip_bad(uint64_t offs, uint64_t size, u8 * dst,
+			   u32 * skip_blocks);
+void nand_spl_mtd_info(u32 * page_size, u32 * block_size);
+#ifdef CONFIG_RDA_FPGA
+void nand_dirty_block_erase(int page);
+#endif
 #ifdef CONFIG_SYS_NAND_SELECT_DEVICE
 void board_nand_select_device(struct nand_chip *nand, int chip);
 #endif
 
-__attribute__((noreturn)) void nand_boot(void);
+void nand_boot(void);
 
 #endif
 
 #ifdef CONFIG_ENV_OFFSET_OOB
-#define ENV_OOB_MARKER 0x30425645 /*"EVB0" in little-endian -- offset is stored
-				    as block number*/
-#define ENV_OOB_MARKER_OLD 0x30564e45 /*"ENV0" in little-endian -- offset is
-					stored as byte number */
+#define ENV_OOB_MARKER 0x30425645	/*"EVB0" in little-endian -- offset is stored
+					   as block number */
+#define ENV_OOB_MARKER_OLD 0x30564e45	/*"ENV0" in little-endian -- offset is
+					   stored as byte number */
 #define ENV_OFFSET_SIZE 8
-int get_nand_env_oob(nand_info_t *nand, unsigned long *result);
+int get_nand_env_oob(nand_info_t * nand, unsigned long *result);
 #endif
diff --git a/include/net.h b/include/net.h
index ee11f82ccc..a092f291bb 100644
--- a/include/net.h
+++ b/include/net.h
@@ -19,6 +19,10 @@
 #include <asm/cache.h>
 #include <asm/byteorder.h>	/* for nton* / ntoh* stuff */
 
+#define DEBUG_LL_STATE 0	/* Link local state machine changes */
+#define DEBUG_DEV_PKT 0		/* Packets or info directed to the device */
+#define DEBUG_NET_PKT 0		/* Packets on info on the network at large */
+#define DEBUG_INT_STATE 0	/* Internal network state changes */
 
 /*
  *	The number of receive packet buffers, and the required packet buffer
@@ -80,14 +84,14 @@ struct eth_device {
 	int iobase;
 	int state;
 
-	int  (*init) (struct eth_device*, bd_t*);
-	int  (*send) (struct eth_device*, volatile void* packet, int length);
-	int  (*recv) (struct eth_device*);
-	void (*halt) (struct eth_device*);
+	int  (*init) (struct eth_device *, bd_t *);
+	int  (*send) (struct eth_device *, void *packet, int length);
+	int  (*recv) (struct eth_device *);
+	void (*halt) (struct eth_device *);
 #ifdef CONFIG_MCAST_TFTP
-	int (*mcast) (struct eth_device*, u32 ip, u8 set);
+	int (*mcast) (struct eth_device *, u32 ip, u8 set);
 #endif
-	int  (*write_hwaddr) (struct eth_device*);
+	int  (*write_hwaddr) (struct eth_device *);
 	struct eth_device *next;
 	int index;
 	void *priv;
@@ -101,7 +105,7 @@ extern void eth_set_current(void);		/* set nterface to ethcur var */
 extern struct eth_device *eth_get_dev(void);	/* get the current device MAC */
 extern struct eth_device *eth_get_dev_by_name(const char *devname);
 extern struct eth_device *eth_get_dev_by_index(int index); /* get dev @ index */
-extern int eth_get_dev_index (void);		/* get the device index */
+extern int eth_get_dev_index(void);		/* get the device index */
 extern void eth_parse_enetaddr(const char *addr, uchar *enetaddr);
 extern int eth_getenv_enetaddr(char *name, uchar *enetaddr);
 extern int eth_setenv_enetaddr(char *name, const uchar *enetaddr);
@@ -120,10 +124,11 @@ extern int eth_getenv_enetaddr_by_index(const char *base_name, int index,
 
 extern int usb_eth_initialize(bd_t *bi);
 extern int eth_init(bd_t *bis);			/* Initialize the device */
-extern int eth_send(volatile void *packet, int length);	   /* Send a packet */
+extern int eth_send(void *packet, int length);	   /* Send a packet */
 
 #ifdef CONFIG_API
-extern int eth_receive(volatile void *packet, int length); /* Receive a packet*/
+extern int eth_receive(void *packet, int length); /* Receive a packet*/
+extern void (*push_packet)(void *packet, int length);
 #endif
 extern int eth_rx(void);			/* Check for received packets */
 extern void eth_halt(void);			/* stop SCC */
@@ -142,8 +147,8 @@ int eth_write_hwaddr(struct eth_device *dev, const char *base_name,
 		     int eth_number);
 
 #ifdef CONFIG_MCAST_TFTP
-int eth_mcast_join( IPaddr_t mcast_addr, u8 join);
-u32 ether_crc (size_t len, unsigned char const *p);
+int eth_mcast_join(IPaddr_t mcast_addr, u8 join);
+u32 ether_crc(size_t len, unsigned char const *p);
 #endif
 
 
@@ -155,7 +160,17 @@ u32 ether_crc (size_t len, unsigned char const *p);
 /*
  *	Ethernet header
  */
-typedef struct {
+
+struct ethernet_hdr {
+	uchar		et_dest[6];	/* Destination node		*/
+	uchar		et_src[6];	/* Source node			*/
+	ushort		et_protlen;	/* Protocol or length		*/
+};
+
+/* Ethernet header size */
+#define ETHER_HDR_SIZE	(sizeof(struct ethernet_hdr))
+
+struct e802_hdr {
 	uchar		et_dest[6];	/* Destination node		*/
 	uchar		et_src[6];	/* Source node			*/
 	ushort		et_protlen;	/* Protocol or length		*/
@@ -166,23 +181,24 @@ typedef struct {
 	uchar		et_snap2;
 	uchar		et_snap3;
 	ushort		et_prot;	/* 802 protocol			*/
-} Ethernet_t;
+};
 
-#define ETHER_HDR_SIZE	14		/* Ethernet header size		*/
-#define E802_HDR_SIZE	22		/* 802 ethernet header size	*/
+/* 802 + SNAP + ethernet header size */
+#define E802_HDR_SIZE	(sizeof(struct e802_hdr))
 
 /*
- *	Ethernet header
+ *	Virtual LAN Ethernet header
  */
-typedef struct {
+struct vlan_ethernet_hdr {
 	uchar		vet_dest[6];	/* Destination node		*/
 	uchar		vet_src[6];	/* Source node			*/
 	ushort		vet_vlan_type;	/* PROT_VLAN			*/
 	ushort		vet_tag;	/* TAG of VLAN			*/
 	ushort		vet_type;	/* protocol type		*/
-} VLAN_Ethernet_t;
+};
 
-#define VLAN_ETHER_HDR_SIZE	18	/* VLAN Ethernet header size	*/
+/* VLAN Ethernet header size */
+#define VLAN_ETHER_HDR_SIZE	(sizeof(struct vlan_ethernet_hdr))
 
 #define PROT_IP		0x0800		/* IP protocol			*/
 #define PROT_ARP	0x0806		/* IP ARP protocol		*/
@@ -195,7 +211,7 @@ typedef struct {
 /*
  *	Internet Protocol (IP) header.
  */
-typedef struct {
+struct ip_hdr {
 	uchar		ip_hl_v;	/* header length and version	*/
 	uchar		ip_tos;		/* type of service		*/
 	ushort		ip_len;		/* total length			*/
@@ -206,11 +222,7 @@ typedef struct {
 	ushort		ip_sum;		/* checksum			*/
 	IPaddr_t	ip_src;		/* Source IP address		*/
 	IPaddr_t	ip_dst;		/* Destination IP address	*/
-	ushort		udp_src;	/* UDP source port		*/
-	ushort		udp_dst;	/* UDP destination port		*/
-	ushort		udp_len;	/* Length of UDP packet		*/
-	ushort		udp_xsum;	/* Checksum			*/
-} IP_t;
+};
 
 #define IP_OFFS		0x1fff /* ip offset *= 8 */
 #define IP_FLAGS	0xe000 /* first 3 bits */
@@ -218,20 +230,42 @@ typedef struct {
 #define IP_FLAGS_DFRAG	0x4000 /* don't fragments */
 #define IP_FLAGS_MFRAG	0x2000 /* more fragments */
 
-#define IP_HDR_SIZE_NO_UDP	(sizeof (IP_t) - 8)
-#define IP_HDR_SIZE		(sizeof (IP_t))
+#define IP_HDR_SIZE		(sizeof(struct ip_hdr))
+
+/*
+ *	Internet Protocol (IP) + UDP header.
+ */
+struct ip_udp_hdr {
+	uchar		ip_hl_v;	/* header length and version	*/
+	uchar		ip_tos;		/* type of service		*/
+	ushort		ip_len;		/* total length			*/
+	ushort		ip_id;		/* identification		*/
+	ushort		ip_off;		/* fragment offset field	*/
+	uchar		ip_ttl;		/* time to live			*/
+	uchar		ip_p;		/* protocol			*/
+	ushort		ip_sum;		/* checksum			*/
+	IPaddr_t	ip_src;		/* Source IP address		*/
+	IPaddr_t	ip_dst;		/* Destination IP address	*/
+	ushort		udp_src;	/* UDP source port		*/
+	ushort		udp_dst;	/* UDP destination port		*/
+	ushort		udp_len;	/* Length of UDP packet		*/
+	ushort		udp_xsum;	/* Checksum			*/
+};
 
+#define IP_UDP_HDR_SIZE		(sizeof(struct ip_udp_hdr))
+#define UDP_HDR_SIZE		(IP_UDP_HDR_SIZE - IP_HDR_SIZE)
 
 /*
  *	Address Resolution Protocol (ARP) header.
  */
-typedef struct
-{
+struct arp_hdr {
 	ushort		ar_hrd;		/* Format of hardware address	*/
 #   define ARP_ETHER	    1		/* Ethernet  hardware address	*/
 	ushort		ar_pro;		/* Format of protocol address	*/
 	uchar		ar_hln;		/* Length of hardware address	*/
+#   define ARP_HLEN	6
 	uchar		ar_pln;		/* Length of protocol address	*/
+#   define ARP_PLEN	4
 	ushort		ar_op;		/* Operation			*/
 #   define ARPOP_REQUEST    1		/* Request  to resolve  address	*/
 #   define ARPOP_REPLY	    2		/* Response to previous request	*/
@@ -245,13 +279,17 @@ typedef struct
 	 * specific hardware/protocol combinations.
 	 */
 	uchar		ar_data[0];
+#define ar_sha		ar_data[0]
+#define ar_spa		ar_data[ARP_HLEN]
+#define ar_tha		ar_data[ARP_HLEN + ARP_PLEN]
+#define ar_tpa		ar_data[ARP_HLEN + ARP_PLEN + ARP_HLEN]
 #if 0
 	uchar		ar_sha[];	/* Sender hardware address	*/
 	uchar		ar_spa[];	/* Sender protocol address	*/
 	uchar		ar_tha[];	/* Target hardware address	*/
 	uchar		ar_tpa[];	/* Target protocol address	*/
 #endif /* 0 */
-} ARP_t;
+};
 
 #define ARP_HDR_SIZE	(8+20)		/* Size assuming ethernet	*/
 
@@ -270,7 +308,7 @@ typedef struct
 /* Codes for NOT_REACH */
 #define ICMP_NOT_REACH_PORT	3	/* Port unreachable		*/
 
-typedef struct icmphdr {
+struct icmp_hdr {
 	uchar		type;
 	uchar		code;
 	ushort		checksum;
@@ -286,8 +324,10 @@ typedef struct icmphdr {
 		} frag;
 		uchar data[0];
 	} un;
-} ICMP_t;
+};
 
+#define ICMP_HDR_SIZE		(sizeof(struct icmp_hdr))
+#define IP_ICMP_HDR_SIZE	(IP_HDR_SIZE + ICMP_HDR_SIZE)
 
 /*
  * Maximum packet size; used to allocate packet storage.
@@ -326,54 +366,44 @@ typedef struct icmphdr {
 
 /* net.c */
 /** BOOTP EXTENTIONS **/
-extern IPaddr_t		NetOurGatewayIP;	/* Our gateway IP addresse	*/
-extern IPaddr_t		NetOurSubnetMask;	/* Our subnet mask (0 = unknown)*/
-extern IPaddr_t		NetOurDNSIP;	 /* Our Domain Name Server (0 = unknown)*/
+extern IPaddr_t NetOurGatewayIP;	/* Our gateway IP address */
+extern IPaddr_t NetOurSubnetMask;	/* Our subnet mask (0 = unknown) */
+extern IPaddr_t NetOurDNSIP;	/* Our Domain Name Server (0 = unknown) */
 #if defined(CONFIG_BOOTP_DNS2)
-extern IPaddr_t		NetOurDNS2IP;	 /* Our 2nd Domain Name Server (0 = unknown)*/
+extern IPaddr_t NetOurDNS2IP;	/* Our 2nd Domain Name Server (0 = unknown) */
 #endif
-extern char		NetOurNISDomain[32];	/* Our NIS domain		*/
-extern char		NetOurHostName[32];	/* Our hostname			*/
-extern char		NetOurRootPath[64];	/* Our root path		*/
-extern ushort		NetBootFileSize;	/* Our boot file size in blocks	*/
+extern char	NetOurNISDomain[32];	/* Our NIS domain */
+extern char	NetOurHostName[32];	/* Our hostname */
+extern char	NetOurRootPath[64];	/* Our root path */
+extern ushort	NetBootFileSize;	/* Our boot file size in blocks */
 /** END OF BOOTP EXTENTIONS **/
-extern ulong		NetBootFileXferSize;	/* size of bootfile in bytes	*/
-extern uchar		NetOurEther[6];		/* Our ethernet address		*/
-extern uchar		NetServerEther[6];	/* Boot server enet address	*/
-extern IPaddr_t		NetOurIP;		/* Our    IP addr (0 = unknown)	*/
-extern IPaddr_t		NetServerIP;		/* Server IP addr (0 = unknown)	*/
-extern volatile uchar * NetTxPacket;		/* THE transmit packet		*/
-extern volatile uchar * NetRxPackets[PKTBUFSRX];/* Receive packets		*/
-extern volatile uchar * NetRxPacket;		/* Current receive packet	*/
-extern int		NetRxPacketLen;		/* Current rx packet length	*/
-extern unsigned		NetIPID;		/* IP ID (counting)		*/
-extern uchar		NetBcastAddr[6];	/* Ethernet boardcast address	*/
+extern ulong		NetBootFileXferSize;	/* size of bootfile in bytes */
+extern uchar		NetOurEther[6];		/* Our ethernet address */
+extern uchar		NetServerEther[6];	/* Boot server enet address */
+extern IPaddr_t		NetOurIP;	/* Our    IP addr (0 = unknown) */
+extern IPaddr_t		NetServerIP;	/* Server IP addr (0 = unknown) */
+extern uchar		*NetTxPacket;		/* THE transmit packet */
+extern uchar		*NetRxPackets[PKTBUFSRX]; /* Receive packets */
+extern uchar		*NetRxPacket;		/* Current receive packet */
+extern int		NetRxPacketLen;		/* Current rx packet length */
+extern unsigned		NetIPID;		/* IP ID (counting) */
+extern uchar		NetBcastAddr[6];	/* Ethernet boardcast address */
 extern uchar		NetEtherNullAddr[6];
 
-#define VLAN_NONE	4095			/* untagged			*/
-#define VLAN_IDMASK	0x0fff			/* mask of valid vlan id	*/
-extern ushort		NetOurVLAN;		/* Our VLAN			*/
-extern ushort		NetOurNativeVLAN;	/* Our Native VLAN		*/
-
-extern uchar		NetCDPAddr[6];		/* Ethernet CDP address		*/
-extern ushort		CDPNativeVLAN;		/* CDP returned native VLAN	*/
-extern ushort		CDPApplianceVLAN;	/* CDP returned appliance VLAN	*/
-
-extern int		NetState;		/* Network loop state		*/
-#define NETLOOP_CONTINUE	1
-#define NETLOOP_RESTART		2
-#define NETLOOP_SUCCESS		3
-#define NETLOOP_FAIL		4
+#define VLAN_NONE	4095			/* untagged */
+#define VLAN_IDMASK	0x0fff			/* mask of valid vlan id */
+extern ushort		NetOurVLAN;		/* Our VLAN */
+extern ushort		NetOurNativeVLAN;	/* Our Native VLAN */
 
-extern int		NetRestartWrap;		/* Tried all network devices	*/
+extern int		NetRestartWrap;		/* Tried all network devices */
 
 enum proto_t {
 	BOOTP, RARP, ARP, TFTPGET, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP,
-	TFTPSRV, TFTPPUT
+	TFTPSRV, TFTPPUT, LINKLOCAL
 };
 
 /* from net/net.c */
-extern char	BootFile[128];			/* Boot File name		*/
+extern char	BootFile[128];			/* Boot File name */
 
 #if defined(CONFIG_CMD_DNS)
 extern char *NetDNSResolve;		/* The host to resolve  */
@@ -381,21 +411,36 @@ extern char *NetDNSenvvar;		/* the env var to put the ip into */
 #endif
 
 #if defined(CONFIG_CMD_PING)
-extern IPaddr_t	NetPingIP;			/* the ip address to ping		*/
+extern IPaddr_t	NetPingIP;			/* the ip address to ping */
 #endif
 
 #if defined(CONFIG_CMD_CDP)
 /* when CDP completes these hold the return values */
-extern ushort CDPNativeVLAN;
-extern ushort CDPApplianceVLAN;
+extern ushort CDPNativeVLAN;		/* CDP returned native VLAN */
+extern ushort CDPApplianceVLAN;		/* CDP returned appliance VLAN */
+
+/*
+ * Check for a CDP packet by examining the received MAC address field
+ */
+static inline int is_cdp_packet(const uchar *et_addr)
+{
+	extern const uchar NetCDPAddr[6];
+
+	return memcmp(et_addr, NetCDPAddr, 6) == 0;
+}
 #endif
 
 #if defined(CONFIG_CMD_SNTP)
-extern IPaddr_t	NetNtpServerIP;			/* the ip address to NTP	*/
-extern int NetTimeOffset;			/* offset time from UTC		*/
+extern IPaddr_t	NetNtpServerIP;			/* the ip address to NTP */
+extern int NetTimeOffset;			/* offset time from UTC */
+#endif
+
+#if defined(CONFIG_MCAST_TFTP)
+extern IPaddr_t Mcast_addr;
 #endif
 
 /* Initialize the network adapter */
+extern void net_init(void);
 extern int NetLoop(enum proto_t);
 
 /* Shutdown adapters and cleanup */
@@ -408,28 +453,67 @@ extern void	NetStartAgain(void);
 extern int	NetEthHdrSize(void);
 
 /* Set ethernet header; returns the size of the header */
-extern int	NetSetEther(volatile uchar *, uchar *, uint);
+extern int NetSetEther(uchar *, uchar *, uint);
+extern int net_update_ether(struct ethernet_hdr *et, uchar *addr, uint prot);
 
 /* Set IP header */
-extern void	NetSetIP(volatile uchar *, IPaddr_t, int, int, int);
+extern void net_set_ip_header(uchar *pkt, IPaddr_t dest, IPaddr_t source);
+extern void net_set_udp_header(uchar *pkt, IPaddr_t dest, int dport,
+				int sport, int len);
 
 /* Checksum */
-extern int	NetCksumOk(uchar *, int);	/* Return true if cksum OK	*/
-extern uint	NetCksum(uchar *, int);		/* Calculate the checksum	*/
-
-/* Set callbacks */
-extern void	NetSetHandler(rxhand_f *);	/* Set RX packet handler	*/
+extern int	NetCksumOk(uchar *, int);	/* Return true if cksum OK */
+extern uint	NetCksum(uchar *, int);		/* Calculate the checksum */
+
+/* Callbacks */
+extern rxhand_f *net_get_udp_handler(void);	/* Get UDP RX packet handler */
+extern void net_set_udp_handler(rxhand_f *);	/* Set UDP RX packet handler */
+extern rxhand_f *net_get_arp_handler(void);	/* Get ARP RX packet handler */
+extern void net_set_arp_handler(rxhand_f *);	/* Set ARP RX packet handler */
 extern void net_set_icmp_handler(rxhand_icmp_f *f); /* Set ICMP RX handler */
-extern void	NetSetTimeout(ulong, thand_f *);/* Set timeout handler		*/
+extern void	NetSetTimeout(ulong, thand_f *);/* Set timeout handler */
+
+/* Network loop state */
+enum net_loop_state {
+	NETLOOP_CONTINUE,
+	NETLOOP_RESTART,
+	NETLOOP_SUCCESS,
+	NETLOOP_FAIL
+};
+static inline void net_set_state(enum net_loop_state state)
+{
+	extern enum net_loop_state net_state;
 
-/* Transmit "NetTxPacket" */
-extern void	NetSendPacket(volatile uchar *, int);
+	debug_cond(DEBUG_INT_STATE, "--- NetState set to %d\n", state);
+	net_state = state;
+}
 
-/* Transmit UDP packet, performing ARP request if needed */
-extern int	NetSendUDPPacket(uchar *ether, IPaddr_t dest, int dport, int sport, int len);
+/* Transmit a packet */
+static inline void NetSendPacket(uchar *pkt, int len)
+{
+	(void) eth_send(pkt, len);
+}
+
+/*
+ * Transmit "NetTxPacket" as UDP packet, performing ARP request if needed
+ *  (ether will be populated)
+ *
+ * @param ether Raw packet buffer
+ * @param dest IP address to send the datagram to
+ * @param dport Destination UDP port
+ * @param sport Source UDP port
+ * @param payload_len Length of data after the UDP header
+ */
+extern int NetSendUDPPacket(uchar *ether, IPaddr_t dest, int dport,
+			int sport, int payload_len);
 
 /* Processes a received packet */
-extern void	NetReceive(volatile uchar *, int);
+extern void NetReceive(uchar *, int);
+
+#ifdef CONFIG_NETCONSOLE
+void NcStart(void);
+int nc_input_packet(uchar *pkt, unsigned dest, unsigned src, unsigned len);
+#endif
 
 /*
  * Check if autoload is enabled. If so, use either NFS or TFTP to download
@@ -445,10 +529,11 @@ void net_auto_load(void);
  * footprint in our tests.
  */
 /* return IP *in network byteorder* */
-static inline IPaddr_t NetReadIP(volatile void *from)
+static inline IPaddr_t NetReadIP(void *from)
 {
 	IPaddr_t ip;
-	memcpy((void*)&ip, (void*)from, sizeof(ip));
+
+	memcpy((void *)&ip, (void *)from, sizeof(ip));
 	return ip;
 }
 
@@ -456,26 +541,27 @@ static inline IPaddr_t NetReadIP(volatile void *from)
 static inline ulong NetReadLong(ulong *from)
 {
 	ulong l;
-	memcpy((void*)&l, (void*)from, sizeof(l));
+
+	memcpy((void *)&l, (void *)from, sizeof(l));
 	return l;
 }
 
 /* write IP *in network byteorder* */
 static inline void NetWriteIP(void *to, IPaddr_t ip)
 {
-	memcpy(to, (void*)&ip, sizeof(ip));
+	memcpy(to, (void *)&ip, sizeof(ip));
 }
 
 /* copy IP */
-static inline void NetCopyIP(volatile void *to, void *from)
+static inline void NetCopyIP(void *to, void *from)
 {
-	memcpy((void*)to, from, sizeof(IPaddr_t));
+	memcpy((void *)to, from, sizeof(IPaddr_t));
 }
 
 /* copy ulong */
 static inline void NetCopyLong(ulong *to, ulong *from)
 {
-	memcpy((void*)to, (void*)from, sizeof(ulong));
+	memcpy((void *)to, (void *)from, sizeof(ulong));
 }
 
 /**
@@ -498,7 +584,7 @@ static inline int is_zero_ether_addr(const u8 *addr)
  */
 static inline int is_multicast_ether_addr(const u8 *addr)
 {
-	return (0x01 & addr[0]);
+	return 0x01 & addr[0];
 }
 
 /*
@@ -509,7 +595,8 @@ static inline int is_multicast_ether_addr(const u8 *addr)
  */
 static inline int is_broadcast_ether_addr(const u8 *addr)
 {
-	return (addr[0] & addr[1] & addr[2] & addr[3] & addr[4] & addr[5]) == 0xff;
+	return (addr[0] & addr[1] & addr[2] & addr[3] & addr[4] & addr[5]) ==
+		0xff;
 }
 
 /*
@@ -529,13 +616,13 @@ static inline int is_valid_ether_addr(const u8 *addr)
 }
 
 /* Convert an IP address to a string */
-extern void	ip_to_string (IPaddr_t x, char *s);
+extern void ip_to_string(IPaddr_t x, char *s);
 
 /* Convert a string to ip address */
 extern IPaddr_t string_to_ip(const char *s);
 
 /* Convert a VLAN id to a string */
-extern void	VLAN_to_string (ushort x, char *s);
+extern void VLAN_to_string(ushort x, char *s);
 
 /* Convert a string to a vlan id */
 extern ushort string_to_VLAN(const char *s);
@@ -544,7 +631,7 @@ extern ushort string_to_VLAN(const char *s);
 extern ushort getenv_VLAN(char *);
 
 /* copy a filename (allow for "..." notation, limit length) */
-extern void	copy_filename (char *dst, const char *src, int size);
+extern void copy_filename(char *dst, const char *src, int size);
 
 /* get a random source port */
 extern unsigned int random_port(void);
diff --git a/include/part.h b/include/part.h
index 182776791d..eda896d471 100644
--- a/include/part.h
+++ b/include/part.h
@@ -2,23 +2,7 @@
  * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef _PART_H
 #define _PART_H
@@ -36,25 +20,34 @@ typedef struct block_dev_desc {
 #ifdef CONFIG_LBA48
 	unsigned char	lba48;		/* device can use 48bit addr (ATA/ATAPI v7) */
 #endif
-	lbaint_t		lba;		/* number of blocks */
+	lbaint_t	lba;		/* number of blocks */
 	unsigned long	blksz;		/* block size */
+	int		log2blksz;	/* for convenience: log2(blksz) */
 	char		vendor [40+1];	/* IDE model, SCSI Vendor */
 	char		product[20+1];	/* IDE Serial no, SCSI product */
 	char		revision[8+1];	/* firmware revision */
 	unsigned long	(*block_read)(int dev,
-				      unsigned long start,
+				      lbaint_t start,
 				      lbaint_t blkcnt,
 				      void *buffer);
 	unsigned long	(*block_write)(int dev,
-				       unsigned long start,
+				       lbaint_t start,
 				       lbaint_t blkcnt,
 				       const void *buffer);
 	unsigned long   (*block_erase)(int dev,
-				       unsigned long start,
+				       lbaint_t start,
 				       lbaint_t blkcnt);
 	void		*priv;		/* driver private struct pointer */
 }block_dev_desc_t;
 
+#define BLOCK_CNT(size, block_dev_desc) (PAD_COUNT(size, block_dev_desc->blksz))
+#define PAD_TO_BLOCKSIZE(size, block_dev_desc) \
+	(PAD_SIZE(size, block_dev_desc->blksz))
+#define LOG2(x) (((x & 0xaaaaaaaa) ? 1 : 0) + ((x & 0xcccccccc) ? 2 : 0) + \
+		 ((x & 0xf0f0f0f0) ? 4 : 0) + ((x & 0xff00ff00) ? 8 : 0) + \
+		 ((x & 0xffff0000) ? 16 : 0))
+#define LOG2_INVALID(type) ((type)((sizeof(type)<<3)-1))
+
 /* Interface types: */
 #define IF_TYPE_UNKNOWN		0
 #define IF_TYPE_IDE		1
@@ -88,16 +81,21 @@ typedef struct block_dev_desc {
 #define DEV_TYPE_OPDISK		0x07	/* optical disk */
 
 typedef struct disk_partition {
-	ulong	start;		/* # of first block in partition	*/
-	ulong	size;		/* number of blocks in partition	*/
+	lbaint_t	start;	/* # of first block in partition	*/
+	lbaint_t	size;	/* number of blocks in partition	*/
 	ulong	blksz;		/* block size in bytes			*/
 	uchar	name[32];	/* partition name			*/
 	uchar	type[32];	/* string type description		*/
+	int	bootable;	/* Active/Bootable flag is set		*/
+#ifdef CONFIG_PARTITION_UUIDS
+	char	uuid[37];	/* filesystem UUID as string, if exists	*/
+#endif
 } disk_partition_t;
 
 /* Misc _get_dev functions */
 #ifdef CONFIG_PARTITIONS
-block_dev_desc_t* get_dev(char* ifname, int dev);
+block_dev_desc_t *get_dev(const char *ifname, int dev);
+block_dev_desc_t *get_dev_by_name(char *devname);
 block_dev_desc_t* ide_get_dev(int dev);
 block_dev_desc_t* sata_get_dev(int dev);
 block_dev_desc_t* scsi_get_dev(int dev);
@@ -107,12 +105,58 @@ block_dev_desc_t* systemace_get_dev(int dev);
 block_dev_desc_t* mg_disk_get_dev(int dev);
 
 /* disk/part.c */
+/* Refer to doc/README.partition_funcs for information about these functions. */
+int get_partition_by_name(block_dev_desc_t *dev, const char *partition_name,
+				disk_partition_t *partition);
+int partition_erase_pre(disk_partition_t *ptn);
+int partition_erase_post(disk_partition_t *ptn);
+int partition_read_pre(disk_partition_t *ptn);
+int partition_read_post(disk_partition_t *ptn);
+int partition_write_pre(disk_partition_t *ptn);
+int partition_write_post(disk_partition_t *ptn);
+int partition_erase_blks(block_dev_desc_t *dev, disk_partition_t *partition,
+				lbaint_t *blkcnt);
+int partition_erase_bytes(block_dev_desc_t *dev, disk_partition_t *partition,
+				loff_t *bytecnt);
+#ifdef CONFIG_MD5
+void partition_md5_helper(block_dev_desc_t *dev, lbaint_t blk_start,
+				lbaint_t *blkcnt, unsigned char md5[16]);
+int partition_md5_blks(block_dev_desc_t *dev, disk_partition_t *partition,
+				lbaint_t *blkcnt, unsigned char md5[16]);
+int partition_md5_bytes(block_dev_desc_t *dev, disk_partition_t *partition,
+				loff_t *bytecnt, unsigned char md5[16]);
+#endif /* CONFIG_MD5 */
+int partition_read_blks(block_dev_desc_t *dev, disk_partition_t *partition,
+				lbaint_t *blkcnt, void *buffer);
+int partition_read_bytes(block_dev_desc_t *dev, disk_partition_t *partition,
+				loff_t *bytecnt, void *buffer);
+int partition_write_blks(block_dev_desc_t *dev, disk_partition_t *partition,
+				lbaint_t *blkcnt, const void *buffer);
+int partition_write_bytes(block_dev_desc_t *dev, disk_partition_t *partition,
+				loff_t *bytecnt, const void *buffer);
+int partition_unsparse(block_dev_desc_t *dev, disk_partition_t *ptn,
+		unsigned char *source, lbaint_t sector, lbaint_t num_blks);
+disk_partition_t *partition_find_ptn(const char *name);
 int get_partition_info (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
 void print_part (block_dev_desc_t *dev_desc);
 void  init_part (block_dev_desc_t *dev_desc);
 void dev_print(block_dev_desc_t *dev_desc);
+int get_device(const char *ifname, const char *dev_str,
+	       block_dev_desc_t **dev_desc);
+int get_device_and_partition(const char *ifname, const char *dev_part_str,
+			     block_dev_desc_t **dev_desc,
+			     disk_partition_t *info, int allow_whole_dev);
+#ifndef CONFIG_MIN_PARTITION_NUM
+#define CONFIG_MIN_PARTITION_NUM 0
+#endif
+#ifndef CONFIG_MAX_PARTITION_NUM
+#define CONFIG_MAX_PARTITION_NUM 20
+#endif
 #else
-static inline block_dev_desc_t* get_dev(char* ifname, int dev) { return NULL; }
+static inline block_dev_desc_t *get_dev(const char *ifname, int dev)
+{ return NULL; }
+static inline block_dev_desc_t *get_dev_by_name(char* ifname,
+				int dev) { return NULL; }
 static inline block_dev_desc_t* ide_get_dev(int dev) { return NULL; }
 static inline block_dev_desc_t* sata_get_dev(int dev) { return NULL; }
 static inline block_dev_desc_t* scsi_get_dev(int dev) { return NULL; }
@@ -120,12 +164,76 @@ static inline block_dev_desc_t* usb_stor_get_dev(int dev) { return NULL; }
 static inline block_dev_desc_t* mmc_get_dev(int dev) { return NULL; }
 static inline block_dev_desc_t* systemace_get_dev(int dev) { return NULL; }
 static inline block_dev_desc_t* mg_disk_get_dev(int dev) { return NULL; }
-
+static inline block_dev_desc_t *nand_get_dev(int dev) { return NULL; }
+static inline int get_partition_by_name(block_dev_desc_t *dev,
+				const char *partition_name,
+				disk_partition_t *partition) { return -ENODEV; }
+static inline int partition_erase_pre(disk_partition_t *ptn)
+							{ return -ENODEV; }
+static inline int partition_erase_post(disk_partition_t *ptn)
+							{ return -ENODEV; }
+static inline int partition_read_pre(disk_partition_t *ptn)
+							{ return -ENODEV; }
+static inline int partition_read_post(disk_partition_t *ptn)
+							{ return -ENODEV; }
+static inline int partition_write_pre(disk_partition_t *ptn)
+							{ return -ENODEV; }
+static inline int partition_write_post(disk_partition_t *ptn)
+							{ return -ENODEV; }
+static inline int partition_erase_blks(block_dev_desc_t *dev,
+				disk_partition_t *partition,
+				lbaint_t *blkcnt) { return -ENODEV; }
+static inline int partition_erase_bytes(block_dev_desc_t *dev,
+				disk_partition_t *partition,
+				loff_t *bytecnt) { return -ENODEV; }
+#ifdef CONFIG_MD5
+static inline void partition_md5_helper(block_dev_desc_t *dev,
+				lbaint_t blk_start, lbaint_t *blkcnt,
+				unsigned char md5[16]) { *blkcnt = 0; }
+static inline int partition_md5_blks(block_dev_desc_t *dev,
+				disk_partition_t *partition, lbaint_t *blkcnt,
+				unsigned char md5[16]) { return -ENODEV; }
+static inline int partition_md5_bytes(block_dev_desc_t *dev,
+				disk_partition_t *partition, loff_t *bytecnt,
+				unsigned char md5[16]) { return -ENODEV; }
+#endif /* CONFIG_MD5 */
+static inline int partition_read_blks(block_dev_desc_t *dev,
+				disk_partition_t *partition, lbaint_t *blkcnt,
+				void *buffer) { return -ENODEV; }
+static inline int partition_read_bytes(block_dev_desc_t *dev,
+				disk_partition_t *partition, loff_t *bytecnt,
+				void *buffer) { return -ENODEV; }
+static inline int partition_write_blks(block_dev_desc_t *dev,
+				disk_partition_t *partition, lbaint_t *blkcnt,
+				const void *buffer) { return -ENODEV; }
+static inline int partition_write_bytes(block_dev_desc_t *dev,
+				disk_partition_t *partition, loff_t *bytecnt,
+				const void *buffer) { return -ENODEV; }
+int partition_unsparse(block_dev_desc_t *dev, disk_partition_t *ptn,
+		unsigned char *source, lbaint_t sector, lbaint_t num_blks)
+				{ return -ENODEV;}
+disk_partition_t *partition_find_ptn(const char *name)
+				{ return NULL;}
 static inline int get_partition_info (block_dev_desc_t * dev_desc, int part,
 	disk_partition_t *info) { return -1; }
 static inline void print_part (block_dev_desc_t *dev_desc) {}
 static inline void  init_part (block_dev_desc_t *dev_desc) {}
 static inline void dev_print(block_dev_desc_t *dev_desc) {}
+static inline int get_device(const char *ifname, const char *dev_str,
+	       block_dev_desc_t **dev_desc)
+{ return -1; }
+static inline int get_device_and_partition(const char *ifname,
+					   const char *dev_part_str,
+					   block_dev_desc_t **dev_desc,
+					   disk_partition_t *info,
+					   int allow_whole_dev)
+{ *dev_desc = NULL; return -1; }
+#ifndef CONFIG_MIN_PARTITION_NUM
+#define CONFIG_MIN_PARTITION_NUM 0
+#endif
+#ifndef CONFIG_MAX_PARTITION_NUM
+#define CONFIG_MAX_PARTITION_NUM 0
+#endif
 #endif
 
 #ifdef CONFIG_MAC_PARTITION
@@ -157,10 +265,62 @@ int   test_part_amiga (block_dev_desc_t *dev_desc);
 #endif
 
 #ifdef CONFIG_EFI_PARTITION
+#include <part_efi.h>
 /* disk/part_efi.c */
 int get_partition_info_efi (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
 void print_part_efi (block_dev_desc_t *dev_desc);
 int   test_part_efi (block_dev_desc_t *dev_desc);
+
+/**
+ * write_gpt_table() - Write the GUID Partition Table to disk
+ *
+ * @param dev_desc - block device descriptor
+ * @param gpt_h - pointer to GPT header representation
+ * @param gpt_e - pointer to GPT partition table entries
+ *
+ * @return - zero on success, otherwise error
+ */
+int write_gpt_table(block_dev_desc_t *dev_desc,
+		  gpt_header *gpt_h, gpt_entry *gpt_e);
+
+/**
+ * gpt_fill_pte(): Fill the GPT partition table entry
+ *
+ * @param gpt_h - GPT header representation
+ * @param gpt_e - GPT partition table entries
+ * @param partitions - list of partitions
+ * @param parts - number of partitions
+ *
+ * @return zero on success
+ */
+int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e,
+		disk_partition_t *partitions, int parts);
+
+/**
+ * gpt_fill_header(): Fill the GPT header
+ *
+ * @param dev_desc - block device descriptor
+ * @param gpt_h - GPT header representation
+ * @param str_guid - disk guid string representation
+ * @param parts_count - number of partitions
+ *
+ * @return - error on str_guid conversion error
+ */
+int gpt_fill_header(block_dev_desc_t *dev_desc, gpt_header *gpt_h,
+		char *str_guid, int parts_count);
+
+/**
+ * gpt_restore(): Restore GPT partition table
+ *
+ * @param dev_desc - block device descriptor
+ * @param str_disk_guid - disk GUID
+ * @param partitions - list of partitions
+ * @param parts - number of partitions
+ *
+ * @return zero on success
+ */
+int gpt_restore(block_dev_desc_t *dev_desc, char *str_disk_guid,
+		disk_partition_t *partitions, const int parts_count);
 #endif
 
 #endif /* _PART_H */
diff --git a/disk/part_efi.h b/include/part_efi.h
index 5903e7c812..5903e7c812 100644
--- a/disk/part_efi.h
+++ b/include/part_efi.h
diff --git a/include/pdl.h b/include/pdl.h
new file mode 100644
index 0000000000..679460a45a
--- /dev/null
+++ b/include/pdl.h
@@ -0,0 +1,13 @@
+#ifndef __PDL_H_
+#define __PDL_H_
+
+extern int pdl_dbg_pdl;
+extern int pdl_vdbg_pdl;
+extern int pdl_dbg_usb_ep0;
+extern int pdl_dbg_usb_serial;
+extern int pdl_dbg_rw_check;
+extern int pdl_dbg_factory_part;
+
+int pdl_main(void);
+int pdl_mode_get(void);
+#endif
diff --git a/include/pmic.h b/include/pmic.h
index 52a1526d95..6a05b40aef 100644
--- a/include/pmic.h
+++ b/include/pmic.h
@@ -55,6 +55,7 @@ struct pmic {
 };
 
 int pmic_init(void);
+int pmic_dialog_init(void);
 int check_reg(u32 reg);
 struct pmic *get_pmic(void);
 int pmic_probe(struct pmic *p);
diff --git a/include/rda/ddr_timing/8810p_16x2_156m_ddr2.h b/include/rda/ddr_timing/8810p_16x2_156m_ddr2.h
new file mode 100644
index 0000000000..becc4cf0ec
--- /dev/null
+++ b/include/rda/ddr_timing/8810p_16x2_156m_ddr2.h
@@ -0,0 +1,84 @@
+#define DDR_TIMIMG_NAME			"8810p_16x2_156m_ddr2"
+
+#define PMU_VBUCK1_VAL			9
+#define PMU_VBUCK3_VAL			10
+
+#define DDR_VTT_VAL			1
+
+#define	DDR_CHAN_1_VALID_VAL		1
+#define	DDR_CHAN_2_VALID_VAL		1
+#define	DDR_CHAN_3_VALID_VAL		1
+#define	DDR_CHAN_4_VALID_VAL		1
+
+#define DDR_TIMING_100H_VAL		0x0000
+#define DDR_TIMING_101H_VAL		0x0000
+#define DDR_TIMING_102H_VAL		0x0000
+#define DDR_TIMING_103H_VAL		0x64b0
+#define DDR_TIMING_104H_VAL		0x3333
+
+#define DDR_TIMING_105H_VAL		0x3333
+#define DDR_TIMING_106H_VAL		0x0463
+#define DDR_TIMING_107H_VAL		0x1144
+#define DDR_TIMING_108H_VAL		0x0000
+
+#define DDR_TIMING_109H_VAL		0x1101
+#define DDR_TIMING_10AH_VAL		0x0001
+#define DDR_TIMING_10BH_VAL		0x0003
+
+#define DDR_TIMING_120H_VAL		0x0000
+#define DDR_TIMING_121H_VAL		0x0000
+#define DDR_TIMING_122H_VAL		0x0000
+#define DDR_TIMING_123H_VAL		0x64b0
+#define DDR_TIMING_124H_VAL		0x3333
+
+#define DDR_TIMING_125H_VAL		0x3333
+#define DDR_TIMING_126H_VAL		0x0463
+#define DDR_TIMING_127H_VAL		0x1144
+#define DDR_TIMING_128H_VAL		0x0000
+#define DDR_TIMING_129H_VAL		0x1101
+#define DDR_TIMING_12AH_VAL		0x0001
+#define DDR_TIMING_12BH_VAL		0x0003
+
+#define DDR_TIMING_140H_VAL		0x0000
+#define DDR_TIMING_141H_VAL		0x0000
+#define DDR_TIMING_142H_VAL		0x0000
+#define DDR_TIMING_143H_VAL		0x64b0
+#define DDR_TIMING_144H_VAL		0x3333
+#define DDR_TIMING_145H_VAL		0x3333
+#define DDR_TIMING_146H_VAL		0x0463
+#define DDR_TIMING_147H_VAL		0x1144
+#define DDR_TIMING_148H_VAL		0x0000
+#define DDR_TIMING_149H_VAL		0x1101
+#define DDR_TIMING_14AH_VAL		0x0001
+#define DDR_TIMING_14BH_VAL		0x0003
+
+
+#define DDR_TIMING_161H_VAL		0x0000
+#define DDR_TIMING_162H_VAL		0x0000
+#define DDR_TIMING_163H_VAL		0x64b0
+#define DDR_TIMING_164H_VAL		0x3333
+#define DDR_TIMING_165H_VAL		0x3333
+#define DDR_TIMING_166H_VAL		0x0463
+#define DDR_TIMING_167H_VAL		0x1144
+#define DDR_TIMING_168H_VAL		0x0000
+#define DDR_TIMING_169H_VAL		0x1101
+#define DDR_TIMING_16AH_VAL		0x0001
+#define DDR_TIMING_16BH_VAL		0x0003
+
+#define DDR_TIMING_180H_VAL		0x3336
+#define DDR_TIMING_181H_VAL		0x3333
+#define DDR_TIMING_182H_VAL		0x3333
+#define DDR_TIMING_183H_VAL		0x3333
+#define DDR_TIMING_184H_VAL		0x3333
+#define DDR_TIMING_185H_VAL		0x3333
+#define DDR_TIMING_186H_VAL		0x3333
+#define DDR_TIMING_187H_VAL		0x3333
+#define DDR_TIMING_188H_VAL		0x0001
+#define DDR_TIMING_189H_VAL		0x0000
+#define DDR_TIMING_18AH_VAL		0x1144
+#define DDR_TIMING_18BH_VAL		0x0013
+#define DDR_TIMING_18CH_VAL		0x0000
+
+#define DDR_TIMING_160H_VAL		0x0000
+#define DDR_TIMING_69H_VAL			0x0009
+
diff --git a/include/rda/ddr_timing/8810p_16x2_200m_ddr2.h b/include/rda/ddr_timing/8810p_16x2_200m_ddr2.h
new file mode 100644
index 0000000000..86b8b26142
--- /dev/null
+++ b/include/rda/ddr_timing/8810p_16x2_200m_ddr2.h
@@ -0,0 +1,84 @@
+#define DDR_TIMIMG_NAME			"8810p_16x2_200m_ddr2"
+
+#define PMU_VBUCK1_VAL			9
+#define PMU_VBUCK3_VAL			10
+
+#define DDR_VTT_VAL			1
+
+#define	DDR_CHAN_1_VALID_VAL		1
+#define	DDR_CHAN_2_VALID_VAL		1
+#define	DDR_CHAN_3_VALID_VAL		1
+#define	DDR_CHAN_4_VALID_VAL		1
+
+#define DDR_TIMING_100H_VAL		0x0000
+#define DDR_TIMING_101H_VAL		0x0000
+#define DDR_TIMING_102H_VAL		0x0000
+#define DDR_TIMING_103H_VAL		0x24b0
+#define DDR_TIMING_104H_VAL		0x3333
+
+#define DDR_TIMING_105H_VAL		0x3333
+#define DDR_TIMING_106H_VAL		0x0763
+#define DDR_TIMING_107H_VAL		0x1144
+#define DDR_TIMING_108H_VAL		0x0000
+
+#define DDR_TIMING_109H_VAL		0x1101
+#define DDR_TIMING_10AH_VAL		0x0001
+#define DDR_TIMING_10BH_VAL		0x0003
+
+#define DDR_TIMING_120H_VAL		0x0000
+#define DDR_TIMING_121H_VAL		0x0000
+#define DDR_TIMING_122H_VAL		0x0000
+#define DDR_TIMING_123H_VAL		0x24b0
+#define DDR_TIMING_124H_VAL		0x3333
+
+#define DDR_TIMING_125H_VAL		0x3333
+#define DDR_TIMING_126H_VAL		0x0763
+#define DDR_TIMING_127H_VAL		0x1144
+#define DDR_TIMING_128H_VAL		0x0000
+#define DDR_TIMING_129H_VAL		0x1101
+#define DDR_TIMING_12AH_VAL		0x0001
+#define DDR_TIMING_12BH_VAL		0x0003
+
+#define DDR_TIMING_140H_VAL		0x0000
+#define DDR_TIMING_141H_VAL		0x0000
+#define DDR_TIMING_142H_VAL		0x0000
+#define DDR_TIMING_143H_VAL		0x24b0
+#define DDR_TIMING_144H_VAL		0x3333
+#define DDR_TIMING_145H_VAL		0x3333
+#define DDR_TIMING_146H_VAL		0x0763
+#define DDR_TIMING_147H_VAL		0x1144
+#define DDR_TIMING_148H_VAL		0x0000
+#define DDR_TIMING_149H_VAL		0x1101
+#define DDR_TIMING_14AH_VAL		0x0001
+#define DDR_TIMING_14BH_VAL		0x0003
+
+
+#define DDR_TIMING_161H_VAL		0x0000
+#define DDR_TIMING_162H_VAL		0x0000
+#define DDR_TIMING_163H_VAL		0x24b0
+#define DDR_TIMING_164H_VAL		0x3333
+#define DDR_TIMING_165H_VAL		0x3333
+#define DDR_TIMING_166H_VAL		0x0763
+#define DDR_TIMING_167H_VAL		0x1144
+#define DDR_TIMING_168H_VAL		0x0000
+#define DDR_TIMING_169H_VAL		0x1101
+#define DDR_TIMING_16AH_VAL		0x0001
+#define DDR_TIMING_16BH_VAL		0x0003
+
+#define DDR_TIMING_180H_VAL		0x3336
+#define DDR_TIMING_181H_VAL		0x3333
+#define DDR_TIMING_182H_VAL		0x3333
+#define DDR_TIMING_183H_VAL		0x3333
+#define DDR_TIMING_184H_VAL		0x3333
+#define DDR_TIMING_185H_VAL		0x3333
+#define DDR_TIMING_186H_VAL		0x3333
+#define DDR_TIMING_187H_VAL		0x3333
+#define DDR_TIMING_188H_VAL		0x0001
+#define DDR_TIMING_189H_VAL		0x0000
+#define DDR_TIMING_18AH_VAL		0x1144
+#define DDR_TIMING_18BH_VAL		0x0015
+#define DDR_TIMING_18CH_VAL		0x0000
+
+#define DDR_TIMING_160H_VAL		0x0000
+#define DDR_TIMING_69H_VAL			0x0009
+
diff --git a/include/rda/ddr_timing/8810p_16x2_260m_ddr2_u08.h b/include/rda/ddr_timing/8810p_16x2_260m_ddr2_u08.h
new file mode 100644
index 0000000000..59c2c897c3
--- /dev/null
+++ b/include/rda/ddr_timing/8810p_16x2_260m_ddr2_u08.h
@@ -0,0 +1,84 @@
+#define DDR_TIMIMG_NAME			"8810p_16x2_260m_ddr2_u08"
+
+#define PMU_VBUCK1_VAL			9
+#define PMU_VBUCK3_VAL			10
+
+#define DDR_VTT_VAL			1
+
+#define	DDR_CHAN_1_VALID_VAL		1
+#define	DDR_CHAN_2_VALID_VAL		1
+#define	DDR_CHAN_3_VALID_VAL		1
+#define	DDR_CHAN_4_VALID_VAL		1
+
+#define DDR_TIMING_100H_VAL		0x0000
+#define DDR_TIMING_101H_VAL		0x0000
+#define DDR_TIMING_102H_VAL		0x0000
+#define DDR_TIMING_103H_VAL		0x24b0
+#define DDR_TIMING_104H_VAL		0x3333
+
+#define DDR_TIMING_105H_VAL		0x3333
+#define DDR_TIMING_106H_VAL		0x0263
+#define DDR_TIMING_107H_VAL		0x1144
+#define DDR_TIMING_108H_VAL		0x0000
+
+#define DDR_TIMING_109H_VAL		0x1101
+#define DDR_TIMING_10AH_VAL		0x0001
+#define DDR_TIMING_10BH_VAL		0x0003
+
+#define DDR_TIMING_120H_VAL		0x0000
+#define DDR_TIMING_121H_VAL		0x0000
+#define DDR_TIMING_122H_VAL		0x0000
+#define DDR_TIMING_123H_VAL		0x24b0
+#define DDR_TIMING_124H_VAL		0x3333
+
+#define DDR_TIMING_125H_VAL		0x3333
+#define DDR_TIMING_126H_VAL		0x0263
+#define DDR_TIMING_127H_VAL		0x1144
+#define DDR_TIMING_128H_VAL		0x0000
+#define DDR_TIMING_129H_VAL		0x1101
+#define DDR_TIMING_12AH_VAL		0x0001
+#define DDR_TIMING_12BH_VAL		0x0003
+
+#define DDR_TIMING_140H_VAL		0x0000
+#define DDR_TIMING_141H_VAL		0x0000
+#define DDR_TIMING_142H_VAL		0x0000
+#define DDR_TIMING_143H_VAL		0x24b0
+#define DDR_TIMING_144H_VAL		0x3333
+#define DDR_TIMING_145H_VAL		0x3333
+#define DDR_TIMING_146H_VAL		0x0263
+#define DDR_TIMING_147H_VAL		0x1144
+#define DDR_TIMING_148H_VAL		0x0000
+#define DDR_TIMING_149H_VAL		0x1101
+#define DDR_TIMING_14AH_VAL		0x0001
+#define DDR_TIMING_14BH_VAL		0x0003
+
+
+#define DDR_TIMING_161H_VAL		0x0000
+#define DDR_TIMING_162H_VAL		0x0000
+#define DDR_TIMING_163H_VAL		0x24b0
+#define DDR_TIMING_164H_VAL		0x3333
+#define DDR_TIMING_165H_VAL		0x3333
+#define DDR_TIMING_166H_VAL		0x0263
+#define DDR_TIMING_167H_VAL		0x1144
+#define DDR_TIMING_168H_VAL		0x0000
+#define DDR_TIMING_169H_VAL		0x1101
+#define DDR_TIMING_16AH_VAL		0x0001
+#define DDR_TIMING_16BH_VAL		0x0003
+
+#define DDR_TIMING_180H_VAL		0x6666
+#define DDR_TIMING_181H_VAL		0x3333
+#define DDR_TIMING_182H_VAL		0x3333
+#define DDR_TIMING_183H_VAL		0x3333
+#define DDR_TIMING_184H_VAL		0x3333
+#define DDR_TIMING_185H_VAL		0x3333
+#define DDR_TIMING_186H_VAL		0x3333
+#define DDR_TIMING_187H_VAL		0x3333
+#define DDR_TIMING_188H_VAL		0x0001
+#define DDR_TIMING_189H_VAL		0x0000
+#define DDR_TIMING_18AH_VAL		0x1144
+#define DDR_TIMING_18BH_VAL		0x0010
+#define DDR_TIMING_18CH_VAL		0x0000
+
+#define DDR_TIMING_160H_VAL		0x0000
+#define DDR_TIMING_69H_VAL			0x0009
+
diff --git a/include/rda/rda_panel_comm.h b/include/rda/rda_panel_comm.h
new file mode 100644
index 0000000000..ab9e211d2b
--- /dev/null
+++ b/include/rda/rda_panel_comm.h
@@ -0,0 +1,204 @@
+#ifndef __RDA_PANEL_COMM_H
+#define __RDA_PANEL_COMM_H
+
+/* 
+****************************************************************
+ please do not change the format
+ panle name should follow rule : mode_name
+ mode can be: rgb/mcu/dsi
+ name is the actual panel name
+****************************************************************
+*/
+#define VGA_LCDD_DISP_X		480
+#define VGA_LCDD_DISP_Y		640
+
+#define QVGA_LCDD_DISP_X	240
+#define QVGA_LCDD_DISP_Y	320
+
+#define HVGA_LCDD_DISP_X	320
+#define HVGA_LCDD_DISP_Y	480
+
+#define SVGA_LCDD_DISP_X	600
+#define	SVGA_LCDD_DSIP_Y	800
+
+#define WVGA_LCDD_DISP_X	480
+#define WVGA_LCDD_DISP_Y	800
+
+#define WQVGA_LCDD_DISP_X	240
+#define WQVGA_LCDD_DISP_Y	400
+
+#define FWVGA_LCDD_DISP_X	480
+#define FWVGA_LCDD_DISP_Y	854
+
+#define FWQVGA_LCDD_DSIP_X	240
+#define FWQVGA_LCDD_DSIP_Y	432
+
+#define SWVGA_LCDD_DISP_X	600
+#define SWVGA_LCDD_DISP_Y	1024
+
+#define HD_LCDD_DISP_X		720
+#define HD_LCDD_DISP_Y		1280
+
+#define qHD_LCDD_DISP_X		540
+#define qHD_LCDD_DISP_Y		960
+
+#define QHD_LCDD_DISP_X		1440
+#define QHD_LCDD_DISP_Y		2560
+
+#define AUTO_LCDD_WVGA_DISP_X	480
+#define AUTO_LCDD_WVGA_DISP_Y	800
+
+/* definition for panel ili9486l */
+#define ILI9486L_PANEL_NAME		"rgb_ili9486l"
+
+/* definition for panel ili9488l */
+#define ILI9488L_PANEL_NAME		"rgb_ili9488l"
+
+/* definition for panel ili9488l */
+#define ILI9488L_MCU_PANEL_NAME		"mcu_ili9488l"
+
+/* definition for panel ili9488l */
+#define ILI9488_MCU_PANEL_NAME		"mcu_ili9488"
+
+/* definition for panel r61581b */
+#define R61581B_MCU_PANEL_NAME		"mcu_r61581b"
+
+/* definition for panel rm68140 */
+#define RM68140_MCU_PANEL_NAME         "mcu_rm68140"
+
+/* definition for panel ili9806c */
+#define ILI9806C_PANEL_NAME		"rgb_ili9806c"
+
+/* definition for panel ili9806h mcu */
+#define ILI9806H_MCU_PANEL_NAME		"mcu_ili9806h"
+
+#define ILI9806G_MCU_PANEL_NAME		"mcu_ili9806g"
+
+/* definition for panel hx8664 */
+#define HX8664_PANEL_NAME		"rgb_hx8664"
+
+/* definition for panel hx8363*/
+#define HX8363_MCU_PANEL_NAME		"mcu_hx8363"
+
+/* definition for panel truly1p6365 */
+#define TRYLYLP6365_PANEL_NAME		"rgb_truly1p6365"
+
+/* definition for panel nt35510 */
+#define NT35510_PANEL_NAME		"rgb_nt35510"
+#define NT35510_MCU_PANEL_NAME		"mcu_nt35510"
+
+/* definition for panel nt35510s */
+#define NT35510S_MCU_PANEL_NAME		"mcu_nt35510s"
+
+/* definition for panel nt35510 */
+#define NT35310_PANEL_NAME		"rgb_nt35310"
+#define NT35310_MCU_PANEL_NAME		"mcu_nt35310"
+
+/* definition for panel hx8357 */
+#define HX8357_MCU_PANEL_NAME		"mcu_hx8357"
+
+/* definition for panel ili9327 */
+#define ILI9327_PANEL_NAME		"mcu_ili9327"
+
+/* definition for panel kd070d10 */
+#define JB070SZ03A_PANEL_NAME		"rgb_jb070sz03a"
+
+/* definition for panel kd070d10 */
+#define KD070D10_PANEL_NAME		"rgb_kd070d10"
+
+/* definition for panel t50bmpl10 */
+#define T50BMPL10_PANEL_NAME		"rgb_t50bmpl10"
+
+/* definition for panel wy070ml521cp18b */
+#define WY070ML521CP18B_PANEL_NAME	"rgb_wy070ml521cp18b"
+
+/* definition for panel wy070ml521cp21a */
+#define WY070ML521CP21A_PANEL_NAME	"rgb_wy070ml521cp21a"
+
+/* definition for panel r70 */
+#define R70_PANEL_NAME			"rgb_r70"
+
+/* definition for panel otm8019a use mcu interface */
+#define OTM8019A_PANEL_NAME		"rgb_otm8019a"
+
+/* definition for panel otm8019a use mipi interface */
+#define OTM8019A_MIPI_PANEL_NAME	"mipi_otm8019a"
+#define OTM8019A_BOE397_MIPI_PANEL_NAME	"mipi_otm8019a_boe397"
+#define OTM8019A_CPT45_MIPI_PANEL_NAME  "mipi_otm8019a_cpt45"
+
+/* definition for panel jd9161ba */
+#define JD9161BA_PANEL_NAME              "rgb_jd9161ba"
+
+/* definition for panel himax8379c */
+#define HIMAX_8379C_MIPI_PANEL_NAME	"mipi_himax_8379c"
+#define HX8379C_BOE397_MIPI_PANEL_NAME	"mipi_hx8379c_boe397"
+#define HX8379C_CPT45_MIPI_PANEL_NAME	"mipi_hx8379c_cpt45"
+
+/* definition for panel rm68180 */
+#define RM68180_MCU_PANEL_NAME		"mcu_rm68180"
+
+/* definition for panel st7796 */
+#define ST7796_MCU_PANEL_NAME		"mcu_st7796"
+
+/* definition for panel rm68172 */
+#define RM68172_MIPI_PANEL_NAME		"mipi_rm68172"
+
+/* definitoin for panel st7796s */
+#define ST7796S_BOE35_MIPI_PANEL_NAME	"mipi_st7796s_boe35"
+
+/* definitoin for panel jd9161ba mipi */
+#define JD9161BA_MIPI_PANEL_NAME        "mipi_jd9161ba"
+
+/* definition for panel sgt mipi */
+#define ILI9806E_MIPI_PANEL_NAME	"mipi_ili9806e"
+
+/*define auto detect lcd panel*/
+#define AUTO_DET_LCD_PANEL_NAME		"auto"
+
+
+#define DEFAULT_PANEL_LIST " "
+#define AUTO_DETECT_SUPPORTED_PANEL_NUM -1
+#define AUTO_DETECT_SUPPORTED_PANEL_LIST  DEFAULT_PANEL_LIST
+
+
+#define RDA_PANEL_SUPPORT_LIST		\
+	ILI9486L_PANEL_NAME		\
+	ILI9488L_PANEL_NAME		\
+	ILI9806C_PANEL_NAME		\
+	ILI9488_MCU_PANEL_NAME		\
+	RM68140_MCU_PANEL_NAME		\
+	R61581B_MCU_PANEL_NAME		\
+	HX8664_PANEL_NAME		\
+	HX8363_MCU_PANEL_NAME		\
+	HX8357_MCU_PANEL_NAME    	\
+	TRYLYLP6365_PANEL_NAME		\
+	NT35510_PANEL_NAME		\
+	NT35510_MCU_PANEL_NAME		\
+	NT35310_MCU_PANEL_NAME		\
+	NT35510S_MCU_PANEL_NAME		\
+	ILI9327_PANEL_NAME		\
+	JB070SZ03A_PANEL_NAME		\
+	KD070D10_PANEL_NAME		\
+	T50BMPL10_PANEL_NAME		\
+	WY070ML521CP18B_PANEL_NAME	\
+	WY070ML521CP21A_PANEL_NAME	\
+	ILI9806H_MCU_PANEL_NAME		\
+	ILI9806G_MCU_PANEL_NAME		\
+        R70_PANEL_NAME          	\
+	OTM8019A_PANEL_NAME       	\
+	JD9161BA_PANEL_NAME       	\
+	OTM8019A_MIPI_PANEL_NAME	\
+	RM68180_MCU_PANEL_NAME		\
+        ST7796_MCU_PANEL_NAME		\
+	RM68172_MIPI_PANEL_NAME		\
+	HX8379C_BOE397_MIPI_PANEL_NAME  \
+	OTM8019A_BOE397_MIPI_PANEL_NAME	\
+	ST7796S_BOE35_MIPI_PANEL_NAME	\
+	HX8379C_CPT45_MIPI_PANEL_NAME	\
+	OTM8019A_CPT45_MIPI_PANEL_NAME	\
+	JD9161BA_MIPI_PANEL_NAME	\
+	ILI9806E_MIPI_PANEL_NAME		\
+        AUTO_DET_LCD_PANEL_NAME
+
+#define ASPACE(S)	S" "
+#endif /* __TGT_AP_PANEL_SETTING_H */
diff --git a/include/rda/tgt_ap_board_config.h b/include/rda/tgt_ap_board_config.h
new file mode 100644
index 0000000000..88c4e02a8f
--- /dev/null
+++ b/include/rda/tgt_ap_board_config.h
@@ -0,0 +1,108 @@
+#ifndef _TGT_AP_BOARD_CFG_H_
+#define _TGT_AP_BOARD_CFG_H_
+
+#define EXTRA_BOOTCOMMAND "selinux=1 androidboot.selinux=permissive"
+
+/* MEM Size, in MBytes */
+#define _TGT_AP_MEM_SIZE		256
+#define _TGT_AP_VPU_MEM_SIZE		16
+#define _TGT_AP_CAM_MEM_SIZE		4
+#define _TGT_AP_GFX_MEM_SIZE		0
+#define _TGT_AP_OS_MEM_SIZE		236
+
+#define _TGT_AP_GFX_MEM_BASE	(_TGT_AP_OS_MEM_SIZE)
+#define _TGT_AP_CAM_MEM_BASE	(_TGT_AP_GFX_MEM_BASE + _TGT_AP_GFX_MEM_SIZE)
+#define _TGT_AP_VPU_MEM_BASE	(_TGT_AP_CAM_MEM_BASE + _TGT_AP_CAM_MEM_SIZE)
+
+#if ((_TGT_AP_VPU_MEM_BASE + _TGT_AP_VPU_MEM_SIZE) != _TGT_AP_MEM_SIZE)
+#error "Invalid memory size configuration"
+#endif
+
+/* usb otg function */
+#define _TGT_AP_USB_OTG_ENABLE
+
+/* NAND clock in MHz */
+#define _TGT_AP_NAND_CLOCK		(30000000)
+
+/* SPI NAND clock in MHz: 64000000/80000000/100000000*/
+#define _TGT_AP_SPI_NAND_CLOCK		(80000000)
+/* SPI NAND read delay from flash to controller */
+/* need change according different HW board */
+#define _TGT_AP_SPI_NAND_READDELAY (4)
+
+/* ADMMC clock */
+#define _TGT_AP_SDMMC1_MAX_FREQ		(30000000)/*3*/
+#define _TGT_AP_SDMMC1_MCLK_INV		(1)
+#define _TGT_AP_SDMMC1_MCLK_ADJ		(1)
+#define _TGT_AP_SDMMC2_MAX_FREQ		(20000000)/*2*/
+#define _TGT_AP_SDMMC2_MCLK_INV		(1)
+#define _TGT_AP_SDMMC2_MCLK_ADJ		(3)
+#define _TGT_AP_SDMMC3_MAX_FREQ		(30000000)/*3*/
+#define _TGT_AP_SDMMC3_MCLK_ADJ		(0)
+
+/* I2C clocks */
+#define _TGT_AP_I2C0_CLOCK		(100000)
+#define _TGT_AP_I2C1_CLOCK		(400000)
+#define _TGT_AP_I2C2_CLOCK		(200000)
+
+/*
+ * I2C addresses (Only keep non-RDA peripherals )
+ */
+#define _TGT_AP_I2C_BUS_ID_TS		(2)
+#  define _DEF_I2C_ADDR_TS_GSL168X	(0x40)
+#  define _DEF_I2C_ADDR_TS_MSG2133	(0x26)
+
+#  define _DEF_I2C_ADDR_TS_FT6x06	(0x38)
+#  define _DEF_I2C_ADDR_TS_IT7252       (0x46)
+#  define _DEF_I2C_ADDR_TS_GTP868       (0x5d)
+#  define _DEF_I2C_ADDR_TS_ICN831X      (0x40)
+/* NO need to define ADDR, this is determined by customer driver */
+/* #define _TGT_AP_I2C_ADDR_TS */
+
+#define _TGT_AP_I2C_BUS_ID_GSENSOR	(2)
+#  define _DEF_I2C_ADDR_GSENSOR_MMA7760	(0x4c)
+#  define _DEF_I2C_ADDR_GSENSOR_STK8312	(0x3d)
+#  define _DEF_I2C_ADDR_GSENSOR_MMA865X	(0x1D)
+/* Notice : when SA0=1, the MMA8452 slave address is 0x1D, and when SA0 = 0,
+    the address is 0x1C */
+#  define _DEF_I2C_ADDR_GSENSOR_MMA845X (0x1D)
+#  define _DEF_I2C_ADDR_GSENSOR_MXC622X (0x15)
+
+/* gsensor position to lcd */
+#define _TGT_AP_GSENSOR_POSITION 1 
+
+/* NO need to define ADDR, this is determined by customer driver */
+/* #define _TGT_AP_I2C_ADDR_GSENSOR */
+
+#define _TGT_AP_I2C_BUS_ID_LSENSOR	(2)
+#  define _DEF_I2C_ADDR_LSENSOR_STK3x1x	(0x48)
+/* NO need to define ADDR, this is determined by customer driver */
+/* #define _TGT_AP_I2C_ADDR_LSENSOR */
+
+#define _TGT_AP_I2C_BUS_ID_WIFI		(0)
+/* No Address defination, as rda5990 address is not changable */
+
+#define _TGT_AP_I2C_BUS_ID_ATV		(0)
+/* No Address defination, as rda5888 address is not changable */
+
+#define _TGT_AP_I2C_BUS_ID_CAM		(0)
+
+/* LED defination */
+#define _TGT_AP_LED_RED 		(1) 
+/* # define _TGT_AP_LED_RED_KB		(1) */
+# define _TGT_AP_LED_RED_FLASH	(1)
+/* #define _TGT_AP_LED_GREEN		(1)*/
+/* # define _TGT_AP_LED_GREEN_KB 	(1) */
+/* # define _TGT_AP_LED_GREEN_FLASH	(1) */
+#define _TGT_AP_LED_BLUE		(1)
+# define _TGT_AP_LED_BLUE_KB		(1)
+/*# define _TGT_AP_LED_BLUE_FLASH	(1) */
+
+/*#define _TGT_AP_BOARD_HAS_ATV*/
+
+#define CONFIG_SDMMC_BOOT 1
+#define _TGT_AP_VIBRATOR_POWER_ON   (1)
+# define _TGT_AP_VIBRATOR_TIME       (300)
+
+#endif /*_TGT_AP_BOARD_CFG_H_*/
+
diff --git a/include/rda/tgt_ap_clock_config.h b/include/rda/tgt_ap_clock_config.h
new file mode 100644
index 0000000000..00afaa4fd9
--- /dev/null
+++ b/include/rda/tgt_ap_clock_config.h
@@ -0,0 +1,80 @@
+#ifndef _TGT_AP_CLOCK_CFG_H_
+#define _TGT_AP_CLOCK_CFG_H_
+
+/*
+ * PLL Freqs
+ */
+#define _TGT_AP_PLL_CPU_FREQ    (988)
+#define _TGT_AP_PLL_BUS_FREQ    (800)
+#define _TGT_AP_PLL_MEM_FREQ    (260)
+#define _TGT_AP_PLL_USB_FREQ    (480)
+
+/*
+ * DDR settings
+ */
+/* DDR clock rate (data rate double this number) */
+#define _TGT_AP_DDR_TYPE        2
+#if (_TGT_AP_PLL_MEM_FREQ == 400) \
+	|| (_TGT_AP_PLL_MEM_FREQ == 351) \
+	|| (_TGT_AP_PLL_MEM_FREQ == 312) \
+	|| (_TGT_AP_PLL_MEM_FREQ == 260) \
+	|| (_TGT_AP_PLL_MEM_FREQ == 290) \
+	|| (_TGT_AP_PLL_MEM_FREQ == 200) \
+	|| (_TGT_AP_PLL_MEM_FREQ == 156) \
+	|| (_TGT_AP_PLL_MEM_FREQ == 100)
+#define _TGT_AP_DDR_CLOCK       _TGT_AP_PLL_MEM_FREQ
+#else
+#error "Invalid DDR_CLOCK"
+#endif
+//#define _TGT_AP_DDR_LOWPWR
+#define _TGT_AP_DDR_ODT         (2)
+#define _TGT_AP_DDR_RON         (0)
+#define _TGT_AP_DDR_CHIP_BITS   (0)
+/* DDR bus width, valid value are 8, 16 or 32 */
+#define _TGT_AP_DDR_WIDTH       (32)
+#if (_TGT_AP_DDR_WIDTH == 8)
+#define _TGT_AP_DDR_MEM_BITS    (0)
+#elif (_TGT_AP_DDR_WIDTH == 16)
+#define _TGT_AP_DDR_MEM_BITS    (1)
+#elif (_TGT_AP_DDR_WIDTH == 32)
+#define _TGT_AP_DDR_MEM_BITS    (2)
+#else
+#error "Invalid DDR WIDTH"
+#endif
+#define _TGT_AP_DDR_BANK_BITS   (3)
+#define _TGT_AP_DDR_ROW_BITS    (3)
+#define _TGT_AP_DDR_COL_BITS    (1)
+
+/*DDR auto calibration function control */
+#define _TGT_AP_DDR_AUTO_CALI_ENABLE 1
+
+/* DDR timing */
+//#include "ddr_timing/micron_16x1_260m_U04_R7629_zhangxian.h"
+//#include "ddr_timing/8810m_16x2_260m_ddr2.h"
+//#include "ddr_timing/8810m_16x2_290m_ddr2.h"
+#if (_TGT_AP_PLL_MEM_FREQ == 260)
+#include "ddr_timing/8810p_16x2_260m_ddr2_u08.h"
+#elif (_TGT_AP_PLL_MEM_FREQ == 200)
+#include "ddr_timing/8810p_16x2_200m_ddr2.h"
+#elif (_TGT_AP_PLL_MEM_FREQ == 156)
+#include "ddr_timing/8810p_16x2_156m_ddr2.h"
+#else
+#error "Invalid DDR_CLOCK"
+#endif
+/*
+ * CLK settings
+ */
+#define _TGT_AP_CLK_CPU         (0x001F)
+#define _TGT_AP_CLK_AXI         (0x001E)
+#define _TGT_AP_CLK_GCG         (0x001E)
+#define _TGT_AP_CLK_AHB1        (0x001A)
+#define _TGT_AP_CLK_APB1        (0x001A)
+#define _TGT_AP_CLK_APB2        (0x001A)
+#define _TGT_AP_CLK_MEM         (0x0000)
+#define _TGT_AP_CLK_GPU         (0x001A)
+#define _TGT_AP_CLK_VPU         (0x001C)
+#define _TGT_AP_CLK_VOC         (0x001A)
+#define _TGT_AP_CLK_SFLSH       (0x001D)
+
+#endif //_TGT_AP_CLOCK_CFG_H_
+
diff --git a/include/rda/tgt_ap_flash_parts.h b/include/rda/tgt_ap_flash_parts.h
new file mode 100644
index 0000000000..b69636b281
--- /dev/null
+++ b/include/rda/tgt_ap_flash_parts.h
@@ -0,0 +1,26 @@
+#ifndef __TGT_AP_FLASH_PARTS_H__
+#define __TGT_AP_FLASH_PARTS_H__
+
+#define MTDPARTS_DEF			\
+		"2M@128K(bootloader),"	\
+		"2M(factorydata),"	\
+		"2M(misc),"	        \
+		"4M(modem),"		\
+		"8M(boot),"		\
+		"10M(recovery),"		\
+		MTDPARTS_ANDROID_DEF
+
+#define MTDPARTS_ANDROID_DEF		\
+		"300M(system),"		\
+		"300M(vendor),"     \
+		"-(userdata)"
+
+/*
+kernel  need handle mtd from 0, so define a dummy partions whose
+size is bootloader+factorydata+modem+boot+recovery
+*/
+#define MTDPARTS_KERNEL_DEF		\
+		"28M@0(dummy),"		\
+		MTDPARTS_ANDROID_DEF
+#endif
+
diff --git a/include/rda/tgt_ap_gpio_setting.h b/include/rda/tgt_ap_gpio_setting.h
new file mode 100644
index 0000000000..97da0a16be
--- /dev/null
+++ b/include/rda/tgt_ap_gpio_setting.h
@@ -0,0 +1,41 @@
+#ifndef _TGT_AP_GPIO_SETTING_H_
+#define _TGT_AP_GPIO_SETTING_H_
+
+#define _TGT_AP_GPIO_TOUCH_RESET        GPO_2
+#define _TGT_AP_GPIO_TOUCH_IRQ          GPIO_B3
+
+//#define _TGT_AP_GPIO_CAM_RESET
+//#define _TGT_AP_GPIO_CAM_PWDN0
+//#define _TGT_AP_GPIO_CAM_PWDN1		GPIO_B3 //C23 in fact
+//#define _TGT_AP_GPIO_CAM_FLASH
+//#define _TGT_AP_GPIO_CAM_EN
+
+#define _TGT_AP_GPIO_MMC_HOTPLUG    GPIO_B4
+
+#define _TGT_AP_GPIO_LCD_RESET          GPO_3
+
+#define _TGT_AP_GPIO_HEADSET_DETECT     GPIO_A7
+
+//#define _TGT_AP_GPIO_USB_DETECT         GPIO_B7
+
+#define _TGT_AP_GPIO_VOLUME_UP          GPIO_D6
+#define _TGT_AP_GPIO_VOLUME_DOWN        GPIO_D5
+
+#define _TGT_AP_GPIO_WIFI               GPIO_B2
+#define _TGT_AP_GPIO_BT_HOST_WAKE       GPIO_B1
+
+#define _TGT_AP_GPIO_USBID_CTRL         GPO_1
+#define _TGT_AP_GPIO_PLUGIN_CTRL        GPIO_B5
+
+/*#define _TGT_AP_GPIO_USB_ID			GPIO_D7*/
+#define _TGT_AP_GPIO_OTG_DETECT GPIO_D7
+#define _TGT_AP_GPIO_USB_VBUS_SWITCH	GPIO_A17
+/*#define _TGT_AP_GPIO_GSENSOR_WAKE       GPIO_A2*/
+/*
+
+
+#define _TGT_AP_GPIO_EXT_AUD_CLASSK_ENABLE	GPIO_A3
+# define _TGT_AP_EXT_AUD_CLASSK_MODE	4
+*/
+#endif // _TGT_AP_GPIO_SETTING_H_
+
diff --git a/include/rda/tgt_ap_headset_setting.h b/include/rda/tgt_ap_headset_setting.h
new file mode 100644
index 0000000000..4a62cbdf99
--- /dev/null
+++ b/include/rda/tgt_ap_headset_setting.h
@@ -0,0 +1,67 @@
+#ifndef __TGT_AP_HEADSET_SETTING_H
+#define __TGT_AP_HEADSET_SETTING_H
+
+/* notice
+ * 1. when ap do vmic gpadc detect, headset ( or headphone ) will be detected according to first gpadc value
+ * 2. when ap donot do vmic gpadc detect, headset ( or headphone ) will be treated as headset only ( for now )
+ * 3. when ap donot do vmic gpadc detect, only on key will be processed.
+*/
+
+// used always
+// open this if ap do gpadc detect, or modem will report key to ap ( only KEY_MEDIA now )
+#define AP_DETECT_VMIC_GPADC 1
+
+// used when ap donot do gpadc detect
+// key code ( input.h ) that report when key down or up
+#define HEADSET_KEY_REPORT KEY_MEDIA
+
+// used always
+// 0 means gpio low when no headset, or high
+#define HEADSET_OUT_GPIO_STATE 1
+
+// used when ap do gpadc detect
+// VMIC gpadc channel
+#define AP_VMIC_GPADC_CHANNEL 0
+
+// used when ap do gpadc detect
+// debounce value
+#define HEADSET_GPADC_DEBOUNCE_VALUE 200
+
+// used when ap do gpadc detect
+// FIXME, should sync with modem PMD_POWER_ID_T
+#define BP_PMD_POWER_EARPIECE 9
+
+// used when ap do gpadc detect
+// under this value ,we think this is a headphone
+#define DETECT_HEADPHON_MAX_VALUE 0xFF
+
+// used when ap do gpadc detect
+// when MODEM_REPORT_KEY_ADC define, we need give right min adc value and max adc value
+// keycode in input.h (kernel) : min adc value : max adc value
+#define HEADSET_KEY_CAPS \
+	{KEY_MEDIA, 0x0, 0x70}, \
+	{KEY_VOLUMEUP, 0x80, 0xC0}, \
+	{KEY_VOLUMEDOWN, 0x130, 0x170},
+
+// used when ap do gpadc detect
+#define GPADC_DETECT_DELAY_MSECS 80
+// used when ap do gpadc detect
+#define GPADC_DETECT_DEBOUNCE_DELAY_MSECS 60
+
+// used always
+// for irq debounce
+#define GPIO_IRQ_DETECT_DEBOUNCE_DELAY_MSECS 200
+
+// used always
+// for out debounce
+#define GPIO_OUT_DETECT_DEBOUNCE_DELAY_MSECS 200
+
+//////////////////////////// need not change ////////////////////////////////
+#define RDA_HEADSET_KEYPAD_NAME "rda-headset-keypad"
+#define RDA_HEADSET_DETECT_NAME "h2w"
+
+#define RDA_HEADSET_DETECT_STATE_OUT "0"
+#define RDA_HEADSET_DETECT_STATE_HEADSET "1"
+#define RDA_HEADSET_DETECT_STATE_HEADPHONE "2"
+
+#endif
diff --git a/include/rda/tgt_ap_panel_setting.h b/include/rda/tgt_ap_panel_setting.h
new file mode 100644
index 0000000000..a414aedfe0
--- /dev/null
+++ b/include/rda/tgt_ap_panel_setting.h
@@ -0,0 +1,26 @@
+#ifndef __TGT_AP_PANEL_SETTING_H
+#define __TGT_AP_PANEL_SETTING_H
+
+#include <rda/rda_panel_comm.h>
+
+/* ***************************************************************
+   * The above list all the panel rda support, the following line to
+   * select panel
+   ***************************************************************
+*/
+
+#define PANEL_NAME	AUTO_DET_LCD_PANEL_NAME
+#define PANEL_XSIZE	WVGA_LCDD_DISP_X
+#define PANEL_YSIZE	WVGA_LCDD_DISP_Y
+
+/* for multiple panel support, user can set AUTO_DETECR_SUPPORTED_PANEL_NUM to -1 and let kernel lookup all panel */
+#undef AUTO_DETECT_SUPPORTED_PANEL_NUM
+#undef AUTO_DETECT_SUPPORTED_PANEL_LIST
+
+#define AUTO_DETECT_SUPPORTED_PANEL_NUM  1
+
+#define AUTO_DETECT_SUPPORTED_PANEL_LIST \
+		ILI9806G_MCU_PANEL_NAME
+
+#define TARGET_AP_PANEL_ILI9806G_MCU	1
+#endif /* __TGT_AP_PANEL_SETTING_H */
diff --git a/include/rda/tgt_ap_ts_setting.h b/include/rda/tgt_ap_ts_setting.h
new file mode 100644
index 0000000000..1f0cc48956
--- /dev/null
+++ b/include/rda/tgt_ap_ts_setting.h
@@ -0,0 +1,8 @@
+#ifndef __TGT_AP_TS_SETTING_H
+#define __TGT_AP_TS_SETTING_H
+
+#include "rda_ts_comm.h"
+
+/* #define TGT_AP_TS_FW_RELOAD		(1) */
+
+#endif
diff --git a/include/rda/tgt_app_cfg.h b/include/rda/tgt_app_cfg.h
new file mode 100644
index 0000000000..26cfbee78d
--- /dev/null
+++ b/include/rda/tgt_app_cfg.h
@@ -0,0 +1,91 @@
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//            Copyright (C) 2003-2009, Coolsand Technologies, Inc.            //
+//                            All Rights Reserved                             //
+//                                                                            //
+//      This source code is the property of Coolsand Technologies and is      //
+//      confidential.  Any  modification, distribution,  reproduction or      //
+//      exploitation  of  any content of this file is totally forbidden,      //
+//      except  with the  written permission  of  Coolsand Technologies.      //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+/// @file tgt_app_cfg.h                                                       //
+/// That file describes the configuration of the application for this target  //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+
+#ifndef _TGT_APP_CFG_H_
+#define _TGT_APP_CFG_H_
+// Partition count.
+#define DSM_PART_COUNT   2
+// =============================================================================
+// TGT_DSM_PART_CONFIG
+// -----------------------------------------------------------------------------
+// This structure describes the DSM(Data Storage Mangage) configuration.
+/// Field description:
+/// szPartName: Partition name string,the max size is 15 bytes.
+/// eDevType: can be either DSM_MEM_DEV_FLASH for onboard flash combo or DSM_MEM_DEV_TFLASH
+/// eCheckLevel: VDS Module cheking level.
+//                        DSM_CHECK_LEVEL1: Check the PBD writing and PB Writing.
+//                        DSM_CHECK_LEVEL2: Check the PDB writing only.
+//                        DSM_CHECK_LEVEL3: Not check.
+/// uSecCnt: Number of sector used by this partition (when relevant)
+/// uRsvBlkCnt: Number of reseved block. When want the write speed speedy, increase this field value.
+/// eModuleId: Module identification.
+//                    DSM_MODULE_FS_ROOT: FS Moudle for root directory.
+//                    DSM_MODULE_FS:   FS Moudle for mounting device.
+//                    DSM_MODULE_SMS: SMS_DM Module.
+//                    DSM_MODULE_REG: REG Module
+// =============================================================================
+
+#define TGT_DSM_PART_CONFIG                                             \
+{                                                                       \
+     {                                                                   \
+         .szPartName  = "VDS0",                                          \
+         .eDevType    = DSM_MEM_DEV_FLASH,                               \
+         .eCheckLevel = DSM_CHECK_LEVEL_1,                               \
+         .uSecCnt     = 3,                                               \
+         .uRsvBlkCnt  = 1,                                               \
+         .eModuleId   = DSM_MODULE_FS_ROOT                               \
+     },                                                                  \
+    {                                                                   \
+        .szPartName  = "CSW",                                           \
+        .eDevType    = DSM_MEM_DEV_FLASH,                               \
+        .eCheckLevel = DSM_CHECK_LEVEL_1,                               \
+        .uSecCnt     = 27,                                              \
+        .uRsvBlkCnt  = 1,                                               \
+        .eModuleId   = DSM_MODULE_CSW                                   \
+    },                                                                  \
+}
+
+#define TGT_DSM_CONFIG                                                  \
+{                                                                       \
+    .dsmPartitionInfo = TGT_DSM_PART_CONFIG ,                           \
+    .dsmPartitionNumber = DSM_PART_COUNT                                \
+}
+
+
+// =============================================================================
+// TGT_CSW_MEM_CONFIG
+// -----------------------------------------------------------------------------
+/// This structure describes the user heap size
+/// cswHeapSize: Size of the heap available for csw
+/// cosHeapSize: Size of the heap available for mmi
+// =============================================================================
+#define TGT_CSW_CONFIG                                                  \
+{                                                                       \
+  .cswHeapSize = 400*1024,                                              \
+  .cosHeapSize = 650*1024                                               \
+}
+
+// =============================================================================
+// TGT_UCTLS_CONFIG
+// -----------------------------------------------------------------------------
+/// Default List of services
+// =============================================================================
+#include "uctls_tgt_params.h"
+
+
+#endif //_TGT_APP_CFG_H_
diff --git a/include/rda/tgt_board_cfg.h b/include/rda/tgt_board_cfg.h
new file mode 100644
index 0000000000..09e82a55f2
--- /dev/null
+++ b/include/rda/tgt_board_cfg.h
@@ -0,0 +1,726 @@
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//            Copyright (C) 2003-2007, Coolsand Technologies, Inc.            //
+//                            All Rights Reserved                             //
+//                                                                            //
+//      This source code is the property of Coolsand Technologies and is      //
+//      confidential.  Any  modification, distribution,  reproduction or      //
+//      exploitation  of  any content of this file is totally forbidden,      //
+//      except  with the  written permission  of  Coolsand Technologies.      //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+/// @file tgt_board_config.h
+/// That file describes the configuration of the board drivers for the specific
+/// gallite g33 target.
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+
+#ifndef _TGT_BOARD_CFG_H_
+#define _TGT_BOARD_CFG_H_
+
+
+
+// #############################################################################
+// #                                                                           #
+// #                      CHIP AND MANDATORY DRIVERS                           #
+// #                                                                           #
+// #############################################################################
+
+
+
+
+// =============================================================================
+// TGT_HAL_CONFIG
+// =============================================================================
+#include "tgt_gpio_setting.h"
+
+// =============================================================================
+// Chip version
+// =============================================================================
+#define TGT_HAL_CHIP_VERSION 1
+
+// =============================================================================
+// RF CLK FREQUENCY
+// =============================================================================
+#define TGT_HAL_RF_CLK_FREQ     HAL_SYS_FREQ_26M
+
+// =============================================================================
+// TGT_HAL_CAM_CFG
+// -----------------------------------------------------------------------------
+// This fills the structure HAL_CFG_CAM_T
+// =============================================================================
+#ifndef TGT_HAL_CAM_CFG
+#define TGT_HAL_CAM_CFG                                                 \
+{                                                                       \
+    .camUsed            = TRUE,                                         \
+    .camRstActiveH      = FALSE,                                        \
+    .camPdnActiveH      = TRUE,                                         \
+    .camPdnRemap        = GPIO_NONE,                                    \
+    .camRstRemap        = GPIO_NONE,                                    \
+    .camCsiId           = HAL_CAM_CSI_NONE,                             \
+    .cam1Used           = FALSE,                                        \
+    .cam1RstActiveH     = FALSE,                                        \
+    .cam1PdnActiveH     = TRUE,                                         \
+    .cam1PdnRemap       = GPIO_NONE,                                    \
+    .cam1RstRemap       = GPIO_NONE,                                    \
+    .cam1CsiId          = HAL_CAM_CSI_NONE,                             \
+    .camMode            = HAL_CAM_MODE_PARALLEL,                        \
+}
+#endif
+
+// =============================================================================
+// TGT_HAL_PWM_CFG
+// -----------------------------------------------------------------------------
+/// This structure describes the PWM configuration for a given target.
+/// The first field identify which PWL is used for GLOW (if any).
+/// The lasts fields tell wether the pin corresponding to PWM output
+/// is actually used as PWM output and not as something else (for
+/// instance as a GPIO).
+// =============================================================================
+#ifndef TGT_HAL_PWM_CFG
+#define TGT_HAL_PWM_CFG                                                 \
+{                                                                       \
+    .pwl0Used           = TRUE,                                         \
+    .pwl1Used           = FALSE,                                        \
+    .pwtUsed            = FALSE,                                        \
+    .lpgUsed            = FALSE                                         \
+}
+#endif
+
+// =============================================================================
+// HAL_CFG_I2C_T
+// -----------------------------------------------------------------------------
+/// This structure describes the I2C configuration for a given target. The
+/// fields tell wether the corresponding I2C pins are actually used
+/// for I2C and not as something else (for instance as a GPIO).
+// =============================================================================
+#ifndef TGT_HAL_I2C_CFG
+#define TGT_HAL_I2C_CFG                                                 \
+{                                                                       \
+    .i2cUsed             = TRUE,                                        \
+    .i2c2Used            = TRUE,                                       \
+    .i2c2PinsCam         = FALSE,                                       \
+    .i2c3Used            = TRUE,                                        \
+}
+#endif
+
+// =============================================================================
+// TGT_HAL_I2S_CFG
+// -----------------------------------------------------------------------------
+/// This structure describes the I2S configuration for a given target. The
+/// fields tell wether the corresponding I2S pin is actually used
+/// for I2S and not as something else (for instance as a GPIO).
+// =============================================================================
+#ifndef TGT_HAL_I2S_CFG
+#define TGT_HAL_I2S_CFG                                                 \
+{                                                                       \
+    .doUsed             = TRUE,                                         \
+    .di0Used            = TRUE,                                         \
+    .di1Used            = FALSE,                                        \
+    .di2Used            = FALSE,                                        \
+}
+#endif
+
+// =============================================================================
+// TGT_HAL_UART_CFG
+// -----------------------------------------------------------------------------
+/// Used to describes a configuration for used pin by an UART for a given target.
+// =============================================================================
+#ifndef TGT_HAL_UART_CFG
+#define TGT_HAL_UART_CFG                                                \
+{                                                                       \
+    HAL_UART_CONFIG_FLOWCONTROL,                                        \
+    HAL_UART_CONFIG_DATA,                                               \
+    HAL_UART_CONFIG_FLOWCONTROL,                                        \
+}
+#endif
+
+// =============================================================================
+// TGT_HAL_MODEM_SPI_CFG
+// -----------------------------------------------------------------------------
+/// This structure describes the SPI configuration for a given target. The first
+/// fields tell wether the pin corresponding to chip select is actually used
+/// as a chip select and not as something else (for instance as a GPIO).
+/// Then, the polarity of the Chip Select is given. It is only relevant
+/// if the corresponding Chip Select is used as a Chip Select.
+/// Finally which pin is used as input, Can be none, one or the other.
+/// On most chip configuration the input 0 (di0) is on the output pin: SPI_DIO
+// =============================================================================
+#ifndef TGT_HAL_MODEM_SPI_CFG
+#define TGT_HAL_MODEM_SPI_CFG                                           \
+{                                                                       \
+    {                                                                   \
+    .cs0Used            = FALSE,                                        \
+    .cs1Used            = FALSE,                                        \
+    .cs2Used            = FALSE,                                        \
+    .cs3Used            = FALSE,                                        \
+    .cs0ActiveLow       = TRUE,                                         \
+    .cs1ActiveLow       = TRUE,                                         \
+    .cs2ActiveLow       = TRUE,                                         \
+    .cs3ActiveLow       = TRUE,                                         \
+    .di0Used            = TRUE,                                         \
+    .di1Used            = FALSE,                                        \
+    },                                                                  \
+}
+#endif
+
+// =============================================================================
+// TGT_HAL_SPI_CFG
+// -----------------------------------------------------------------------------
+/// This structure describes the SPI configuration for a given target. The first
+/// fields tell wether the pin corresponding to chip select is actually used
+/// as a chip select and not as something else (for instance as a GPIO).
+/// Then, the polarity of the Chip Select is given. It is only relevant
+/// if the corresponding Chip Select is used as a Chip Select.
+/// Finally which pin is used as input, Can be none, one or the other.
+/// On most chip configuration the input 0 (di0) is on the output pin: SPI_DIO
+// =============================================================================
+#ifndef TGT_HAL_SPI_CFG
+#define TGT_HAL_SPI_CFG                                                 \
+{                                                                       \
+    {                                                                   \
+    .cs0Used            = FALSE,                                         \
+    .cs1Used            = FALSE,                                        \
+    .cs2Used            = FALSE,                                        \
+    .cs3Used            = FALSE,                                        \
+    .cs0ActiveLow       = TRUE,                                         \
+    .cs1ActiveLow       = TRUE,                                         \
+    .cs2ActiveLow       = TRUE,                                         \
+    .cs3ActiveLow       = TRUE,                                         \
+    .di0Used            = TRUE,                                         \
+    .di1Used            = FALSE,                                        \
+    },                                                                  \
+    {                                                                   \
+    .cs0Used            = FALSE,                                        \
+    .cs1Used            = FALSE,                                        \
+    .cs2Used            = FALSE,                                        \
+    .cs3Used            = FALSE,                                        \
+    .cs0ActiveLow       = TRUE,                                         \
+    .cs1ActiveLow       = TRUE,                                         \
+    .cs2ActiveLow       = TRUE,                                         \
+    .cs3ActiveLow       = TRUE,                                         \
+    .di0Used            = TRUE,                                         \
+    .di1Used            = FALSE,                                        \
+    },                                                                  \
+}
+#endif
+
+// =============================================================================
+// TGT_HAL_SDMMC_CFG
+// -----------------------------------------------------------------------------
+/// This structure describes the SDMMC configuration for a given target. The
+/// fields tell wether the corresponding I2S pin is actually used
+/// for I2S and not as something else (for instance as a GPIO).
+// =============================================================================
+#ifndef TGT_HAL_SDMMC_CFG
+#define TGT_HAL_SDMMC_CFG                                               \
+{                                                                       \
+    .sdmmcUsed          = TRUE,                                         \
+    .sdmmc2Used         = TRUE,                                         \
+    .sdmmc3Used         = TRUE,                                        \
+}
+#endif
+
+// =============================================================================
+// TGT_HAL_GOUDA_CFG
+// -----------------------------------------------------------------------------
+/// This structure describes the GOUDA configuration for a given target.
+/// The first fields tell wether the pin corresponding to chip select is
+/// actually used as a chip select and not as something else (for instance
+/// as a GPIO). If none are used, the GOUDA is considered unused.
+// =============================================================================
+#ifndef TGT_HAL_GOUDA_CFG
+#define TGT_HAL_GOUDA_CFG                                               \
+{                                                                       \
+    .cs0Used            = TRUE,                                        \
+    .cs1Used            = FALSE,                                        \
+    .lcd16_23Cam        = FALSE,                                        \
+    .lcdMode            = HAL_LCD_MODE_PARALLEL_16BIT,                  \
+}
+#endif
+
+// =============================================================================
+// TGT_HAL_IO_DRIVE
+// -----------------------------------------------------------------------------
+/// This structure describes the IO Drive configuration for a given target.
+// =============================================================================
+#ifndef TGT_HAL_IO_DRIVE
+#define TGT_HAL_IO_DRIVE                                                \
+{                                                                       \
+    {                                                                   \
+        .vDdrDomain     = 4,                                            \
+        .vPsram1Domain  = 4,                                            \
+        .vPsram2Domain  = 4,                                            \
+        .vNFlashDomain  = 2,                                            \
+        .vLcd1Domain    = 4,                                            \
+        .vLcd2Domain    = 4,                                            \
+        .vSDat1Domain   = 3,                                            \
+        .vSDat2Domain   = 3,                                            \
+        .vCamDomain     = 0,                                            \
+        .vSim1Domain    = 0,                                            \
+        .vSim2Domain    = 0,                                            \
+        .vSim3Domain    = 0,                                            \
+        .vGpioDomain    = 0,                                            \
+    }                                                                   \
+}
+#endif
+
+// =============================================================================
+// TGT_HAL_CONFIG
+// =============================================================================
+#ifndef TGT_HAL_CONFIG
+#define TGT_HAL_CONFIG                                                  \
+{                                                                       \
+    .chipVersion        = TGT_HAL_CHIP_VERSION,                         \
+    .rfClkFreq          = TGT_HAL_RF_CLK_FREQ,                          \
+    .useLpsCo1          = FALSE,                                        \
+    .keyInMask          = 0x00,                                         \
+    .keyOutMask         = 0x00,                                         \
+    .pwmCfg             = TGT_HAL_PWM_CFG,                              \
+    .i2cCfg             = TGT_HAL_I2C_CFG,                              \
+    .i2sCfg             = TGT_HAL_I2S_CFG,                              \
+    .uartCfg            = TGT_HAL_UART_CFG,                             \
+    .modemSpiCfg        = TGT_HAL_MODEM_SPI_CFG,                        \
+    .spiCfg             = TGT_HAL_SPI_CFG,                              \
+    .sdmmcCfg           = TGT_HAL_SDMMC_CFG,                            \
+    .camCfg             = TGT_HAL_CAM_CFG,                              \
+    .goudaCfg           = TGT_HAL_GOUDA_CFG,                            \
+    .parallelNandUsed   = -1,                                         \
+    .hostUartUsed       = FALSE,                                         \
+    .hostClkUsed        = FALSE,                                        \
+    .clkOutUsed         = TRUE,                                         \
+    .useClk32k          = FALSE,                                        \
+    .noConnectGpio_C    = TGT_HAL_NO_CONNECT_GPIO_C,                    \
+    .usedGpio_C         = TGT_HAL_USED_GPIO_C,                          \
+    .usedTco            = TGT_HAL_USED_TCO,                             \
+    .noConnectGpio_A    = TGT_AP_HAL_NO_CONNECT_GPIO_A,                 \
+    .usedGpio_A         = TGT_AP_HAL_USED_GPIO_A,                       \
+    .usedGpo_A          = TGT_AP_HAL_USED_GPO_A,                        \
+    .noConnectGpio_B    = TGT_AP_HAL_NO_CONNECT_GPIO_B,                 \
+    .usedGpio_B         = TGT_AP_HAL_USED_GPIO_B,                       \
+    .noConnectGpio_D    = TGT_AP_HAL_NO_CONNECT_GPIO_D,                 \
+    .usedGpio_D         = TGT_AP_HAL_USED_GPIO_D,                       \
+    .ioDrive            = TGT_HAL_IO_DRIVE                              \
+}
+#endif
+
+
+// =============================================================================
+// KEY Mapping
+// =============================================================================
+#ifndef KEY_MAP
+
+#define KEY_ROW_NUM 8
+#define KEY_COL_NUM 8
+
+#define TGT_KEY_NB (KEY_ROW_NUM * KEY_COL_NUM)
+
+#define KEY_MAP                                                           \
+{                                                                         \
+    KP_STAR, KP_7, KP_4, KP_1, KP_UP , KP_UNMAPPED, KP_UNMAPPED, KP_UNMAPPED, \
+    KP_0, KP_8, KP_5, KP_2, KP_DW, KP_UNMAPPED, KP_UNMAPPED, KP_UNMAPPED, \
+    KP_POUND,KP_9, KP_6, KP_3, KP_RT , KP_UNMAPPED, KP_UNMAPPED, KP_UNMAPPED, \
+    KP_DEL, KP_SR, KP_BACK ,KP_OK ,KP_LT , KP_UNMAPPED, KP_UNMAPPED, KP_UNMAPPED, \
+    KP_FM, KP_SL, KP_UNMAPPED, KP_UNMAPPED, KP_VD, KP_UNMAPPED, KP_UNMAPPED, KP_UNMAPPED, \
+    KP_UNMAPPED, KP_UNMAPPED, KP_UNMAPPED, KP_UNMAPPED, KP_UNMAPPED, KP_UNMAPPED, KP_UNMAPPED, KP_UNMAPPED, \
+    KP_UNMAPPED, KP_UNMAPPED, KP_UNMAPPED, KP_UNMAPPED, KP_UNMAPPED, KP_UNMAPPED, KP_UNMAPPED, KP_UNMAPPED, \
+    KP_SND, KP_END, KP_UNMAPPED, KP_UNMAPPED, KP_UNMAPPED, KP_UNMAPPED, KP_UNMAPPED, KP_UNMAPPED, \
+}
+#endif // KEY_MAP
+
+
+#ifndef KEY_BOOT_DOWNLOAD
+
+#define KEY_BOOT_DOWNLOAD { KP_0, KP_OK, }
+
+#endif // KEY_BOOT_DOWNLOAD
+
+
+// =============================================================================
+// RFD config
+// =============================================================================
+#ifndef TGT_RFD_CONFIG
+#define TGT_RFD_CONFIG
+
+#include "hal_tcu.h"
+#define TGT_XCV_CONFIG    {.RST = TCO_UNUSED, .PDN  = TCO(11)              }
+#define TGT_PA_CONFIG     {.ENA = TCO_UNUSED, .TXEN = TCO_UNUSED, .BS  = TCO_UNUSED }
+#define TGT_SW_CONFIG     {.SW1 = TCO(2), .SW2  = TCO(3), .SW3 = TCO(4) }
+
+// Note: Some XCV maybe have different control pin names, so someone who develop
+//       the target configuration should explain the pin usage as below.
+//
+// FIXME Fix that with proper knowledge !
+// PA->ENA is VLOGIC pin for SKY77518, MODEN for TQM4002, MOD for RDA6216
+// PA-TXEN is BIAS for RDA6216 ?
+//
+#endif // TGT_RFD_CONFIG
+
+
+// =============================================================================
+// PMD config
+// -----------------------------------------------------------------------------
+/// This fills the structure PMD_CONFIG_T
+// =============================================================================
+#ifndef TGT_PMD_CONFIG
+
+#define TGT_PMD_CONFIG                                                  \
+    {                                                                   \
+        .power =                                                        \
+        {                                                               \
+            { /* PMD_POWER_MIC          : Micro bias enable */          \
+                .ldo            = {  .opal = PMD_LDO_MIC},              \
+                .polarity       = TRUE,                                 \
+                .shared         = TRUE, /* with PMD_POWER_EARPIECE */   \
+                .powerOnState   = FALSE,                                \
+            },                                                          \
+            { /* PMD_POWER_CAMERA       : Camera LDO enable */          \
+                .ldo            = { .opal = PMD_LDO_CAM|PMD_LDO_RF},    \
+                .polarity       = TRUE,                                 \
+                .shared         = FALSE,                                \
+                .powerOnState   = FALSE,                                \
+            },                                                          \
+            { /* PMD_POWER_AUDIO        : Audio LDO enable */           \
+                .ldo            = { .opal = PMD_LDO_ABB},               \
+                .polarity       = TRUE,                                 \
+                .shared         = FALSE,                                \
+                .powerOnState   = FALSE,                                \
+            },                                                          \
+            { /* PMD_POWER_STEREO_DAC   : Stereo DAC LDO enable */      \
+                .ldo            = { .opal = PMD_LDO_NONE},              \
+                .polarity       = TRUE,                                 \
+                .shared         = FALSE,                                \
+                .powerOnState   = FALSE,                                \
+            },                                                          \
+            { /* PMD_POWER_LOUD_SPEAKER : Loud Speaker enable */        \
+                .ldo            = { .pin = { .gpioId = HAL_GPIO_NONE/*1*/ } },  \
+                .polarity       = TRUE,                                 \
+                .shared         = FALSE,                                \
+                .powerOnState   = FALSE,                                \
+            },                                                          \
+            { /* PMD_POWER_PA           : RF Power Amplifier */         \
+                .ldo            = { .opal = PMD_LDO_NONE},              \
+                .polarity       = TRUE,                                 \
+                .shared         = FALSE,                                \
+                .powerOnState   = FALSE,                                \
+            },                                                          \
+            { /* PMD_POWER_USB          : USB LDOs enable */            \
+                .ldo            = { .opal = PMD_LDO_USB},               \
+                .polarity       = TRUE,                                 \
+                .shared         = FALSE,                                \
+                .powerOnState   = FALSE,                                \
+            },                                                          \
+            { /* PMD_POWER_SDMMC        : SD/MMC LDO enable */          \
+                .ldo            = { .opal = PMD_LDO_MMC},               \
+                .polarity       = TRUE,                                 \
+                .shared         = FALSE,                                \
+                .powerOnState   = FALSE,                                \
+            },                                                          \
+            { /* PMD_POWER_FM           : FM LDO enable */              \
+                .ldo            = { .opal = PMD_LDO_ABB},               \
+                .polarity       = TRUE,                                 \
+                .shared         = FALSE,                                \
+                .powerOnState   = FALSE,                                \
+            },                                                          \
+            { /* PMD_POWER_EARPIECE     : Ear Piece Micro bias enable */\
+                .ldo            = { .opal = PMD_LDO_MIC},               \
+                .polarity       = TRUE,                                 \
+                .shared         = TRUE, /* with PMD_POWER_MIC */        \
+                .powerOnState   = FALSE,                                \
+            },                                                          \
+            { /* PMD_POWER_BT           : BlueTooth LDOs enable */      \
+                .ldo            = { .opal = PMD_LDO_NONE},              \
+                .polarity       = TRUE,                                 \
+                .shared         = FALSE,                                \
+                .powerOnState   = FALSE,                                \
+            },                                                          \
+            { /* PMD_POWER_CAMERA_FLASH : Camera Flash Light enable */  \
+                .ldo            = { .pin = {.gpoId = HAL_GPO_0}},       \
+                .polarity       = TRUE,                                 \
+                .shared         = FALSE,                                \
+                .powerOnState   = FALSE,                                \
+            },                                                          \
+            { /* PMD_POWER_LCD          : (main) LCD LDO enable */      \
+                .ldo            = { .opal = PMD_LDO_LCD|PMD_LDO_RF},               \
+                .polarity       = TRUE,                                 \
+                .shared         = FALSE,                                \
+                .powerOnState   = FALSE,                                \
+            },                                                          \
+            { /* PMD_POWER_I2C          : I2C LDO enable */             \
+                /* Inside this chip, if I2C2 is used, and it is     */  \
+                /*   multiplexed on camera pins, PMD_LDO_CAM must   */  \
+                /*   be specified here to supply power to I2C2 I/O. */  \
+                /* On this board, if any LDO (except for always-on  */  \
+                /*   LDOs like vPad) supplies power to I2C pull-up  */  \
+                /*   resistor, it must be specified here too.       */  \
+                .ldo            = { .opal = PMD_LDO_NONE},              \
+                .polarity       = TRUE,                                 \
+                .shared         = FALSE,                                \
+                .powerOnState   = FALSE,                                \
+            },                                                          \
+        },                                                              \
+        .level =                                                        \
+        {                                                               \
+            { /* PMD_LEVEL_SIM          : Sim class voltage */          \
+                .type           = PMD_LEVEL_TYPE_NONE,                  \
+                .ldo            = { .opal = PMD_LDO_NONE},              \
+                .powerOnState   = 0,                                    \
+            },                                                          \
+            { /* PMD_LEVEL_KEYPAD       : KeyPad Back Light level */    \
+                .type           = PMD_LEVEL_TYPE_OPAL,                  \
+                .ldo            = { .pin = { .gpoId  = HAL_GPO_NONE}},  \
+                .powerOnState   = 0,                                    \
+            },                                                          \
+            { /* PMD_LEVEL_LCD          : (main) LCD Back Light level*/ \
+                .type           = PMD_LEVEL_TYPE_BACKLIGHT,             \
+                .ldo            = { .opal = PMD_LDO_NONE},              \
+                .powerOnState   = 0,                                    \
+            },                                                          \
+            { /* PMD_LEVEL_SUB_LCD      : Sub LCD Back Light level */   \
+                .type           = PMD_LEVEL_TYPE_NONE,                  \
+                .ldo            = { .opal = PMD_LDO_NONE},              \
+                .powerOnState   = 0,                                    \
+            },                                                          \
+            { /* PMD_LEVEL_LED0         : LED0 Light level */           \
+                .type           = PMD_LEVEL_TYPE_OPAL,                  \
+                .ldo            = { .opal = PMD_LDO_NONE},              \
+                .powerOnState   = 0,                                    \
+            },                                                          \
+            { /* PMD_LEVEL_LED1         : LED1 Light level */           \
+                .type           = PMD_LEVEL_TYPE_OPAL,                  \
+                .ldo            = { .opal = PMD_LDO_NONE},              \
+                .powerOnState   = 0,                                    \
+            },                                                          \
+            { /* PMD_LEVEL_LED2         : LED2 Light level */           \
+                .type           = PMD_LEVEL_TYPE_OPAL,                  \
+                .ldo            = { .opal = PMD_LDO_NONE},              \
+                .powerOnState   = 0,                                    \
+            },                                                          \
+            { /* PMD_LEVEL_LED3         : LED3 Light level */           \
+                .type           = PMD_LEVEL_TYPE_OPAL,                  \
+                .ldo            = { .pin = { .gpioId  = HAL_GPIO_NONE}}, \
+                .powerOnState   = 0,                                    \
+            },                                                          \
+            { /* PMD_LEVEL_VIBRATOR     : Vibrator control level */     \
+                .type           = PMD_LEVEL_TYPE_LDO,                   \
+                .ldo            = { .opal = PMD_LDO_VIBR},              \
+                .powerOnState   = 0,                                    \
+            },                                                          \
+            { /* PMD_LEVEL_LOUD_SPEAKER : loudspeaker gain */           \
+                .type           = PMD_LEVEL_TYPE_NONE,                  \
+                .ldo            = { .opal = PMD_LDO_NONE},              \
+                .powerOnState   = 0,                                    \
+            },                                                          \
+        },                                                              \
+        /* If any LDO is configured in ldoEnableNormal, it cannot   */  \
+        /*   be controlled as a POWER or LEVEL LDO any more.        */  \
+        .ldoEnableNormal             = 0,                               \
+        .ldoEnableLowPower           = 0,                               \
+        .ldoCamIs2_8                 = TRUE,                            \
+        .ldoLcdIs2_8                 = TRUE,                            \
+        .ldoMMCIsHigh                = TRUE,                            \
+        .ldoIbrIsHigh                = FALSE,                           \
+        .ldoRfIs2_8                  = TRUE,                            \
+        .ldoPadIs2_8                 = TRUE,                            \
+        .lowerVPadLowPower           = FALSE,                           \
+        .vBuck1LowPower              = 6,                               \
+        .vBuck3LowPower              = 12,                              \
+        .vBuck4Usage                 = PMD_VBUCK4_USAGE_2P8V,           \
+        .vBuck4LowPower              = 13,                              \
+        .vSim3Usage                  = PMD_VSIM3_USAGE_2P8V_ALWAYS_ON,             \
+        .batteryGpadcChannel         = HAL_ANA_GPADC_CHAN_7,            \
+        .batteryLevelChargeTermMV    = 4200,                            \
+        .batteryLevelRechargeMV      = 4160,                            \
+        .batteryLevelFullMV          = 4160,                            \
+        .batteryChargeTimeout        = 6 HOURS,                         \
+        .batteryOffsetHighActivityMV = 45,                              \
+        .batteryOffsetPowerDownChargeMV = -150,                         \
+        .powerOnVoltageMV            = 3400,                            \
+        .powerDownVoltageMV          = 3400,                            \
+        .batteryChargeCurrent        = PMD_CHARGER_1200MA,              \
+        .batteryChargeCurrentOnUsb   = PMD_CHARGER_1200MA,              \
+        .batteryTsDetect             = FALSE,                           \
+        .chargerGpadcChannel         = HAL_ANA_GPADC_CHAN_6,            \
+        .chargerLevelUpperLimit      = 6500,                            \
+        .chargerOffsetBackToNormal   = -200,                            \
+        .temperatureGpadcChannel     = HAL_ANA_GPADC_CHAN_1,            \
+        .temperatureUpperLimit       = 0,                              \
+        .temperatureOffsetBackToNormal = -7,                           \
+        .batteryMVScreenAntiFlicker  = 3600,                            \
+        .batteryOffsetScreenNormal   = 100,                             \
+        .earpieceDetectGpio          = HAL_GPIO_NONE,                   \
+        .earpieceGpadcChannel        = HAL_ANA_GPADC_CHAN_0,            \
+    }
+
+#define TGT_PMD_BATT_CAP_CURVE_STEP_MV  20
+
+#define TGT_PMD_BATT_CAP_CURVE_ARRAY                                    \
+ { 0,  0,  0,  0,  0,  0,  1,  3,  6,  8,                             \
+   9, 10, 11, 12, 14, 18, 24, 30, 36, 42,                               \
+  48, 53, 58, 63, 66, 71, 75, 78, 80, 83,                               \
+  85, 87, 89, 91, 93, 95, 97, 99, 100 }
+
+#define TGT_PMD_TEMPERATURE_CURVE_ARRAY                                 \
+    { { 50, 33220 }, { 57, 25060 } }
+
+#endif // TGT_PMD_CONFIG
+
+
+// =============================================================================
+// TGT_AUD_CONFIG
+// -----------------------------------------------------------------------------
+/// Audio interface configuration
+// =============================================================================
+#ifndef TGT_AUD_CONFIG
+#define TGT_AUD_CONFIG
+
+#define TGT_AUD_CONFIG_RECEIVER_DRIVER             CodecGallite // Ti
+#define TGT_AUD_CONFIG_RECEIVER_PARAM              0
+#define TGT_AUD_CONFIG_RECEIVER_OUTPUT_PATH        AUD_SPK_RECEIVER
+#define TGT_AUD_CONFIG_RECEIVER_OUTPUT_TYPE        AUD_SPEAKER_STEREO
+#define TGT_AUD_CONFIG_RECEIVER_INPUT_PATH         AUD_MIC_RECEIVER
+
+#define TGT_AUD_CONFIG_EAR_PIECE_DRIVER            CodecGallite // Ti
+#define TGT_AUD_CONFIG_EAR_PIECE_PARAM             0
+#define TGT_AUD_CONFIG_EAR_PIECE_OUTPUT_PATH       AUD_SPK_EAR_PIECE
+#define TGT_AUD_CONFIG_EAR_PIECE_OUTPUT_TYPE       AUD_SPEAKER_STEREO
+#define TGT_AUD_CONFIG_EAR_PIECE_INPUT_PATH        AUD_MIC_EAR_PIECE
+
+#define TGT_AUD_CONFIG_LOUD_SPEAKER_DRIVER         CodecGallite // Ti
+#define TGT_AUD_CONFIG_LOUD_SPEAKER_PARAM          0
+#define TGT_AUD_CONFIG_LOUD_SPEAKER_OUTPUT_PATH    AUD_SPK_LOUD_SPEAKER //AUD_SPK_EAR_PIECE
+#define TGT_AUD_CONFIG_LOUD_SPEAKER_OUTPUT_TYPE    AUD_SPEAKER_STEREO
+#define TGT_AUD_CONFIG_LOUD_SPEAKER_INPUT_PATH     AUD_MIC_LOUD_SPEAKER
+
+#define TGT_AUD_CONFIG_BT_DRIVER                   Bt
+#define TGT_AUD_CONFIG_BT_PARAM                    0
+#define TGT_AUD_CONFIG_BT_OUTPUT_PATH              AUD_SPK_EAR_PIECE
+#define TGT_AUD_CONFIG_BT_OUTPUT_TYPE              AUD_SPEAKER_STEREO
+#define TGT_AUD_CONFIG_BT_INPUT_PATH               AUD_MIC_RECEIVER
+
+#define TGT_AUD_CONFIG_FM_DRIVER                   Fm
+#define TGT_AUD_CONFIG_FM_PARAM                    0
+#define TGT_AUD_CONFIG_FM_OUTPUT_PATH              AUD_SPK_EAR_PIECE
+#define TGT_AUD_CONFIG_FM_OUTPUT_TYPE              AUD_SPEAKER_STEREO
+#define TGT_AUD_CONFIG_FM_INPUT_PATH               AUD_MIC_RECEIVER
+
+//atv aud config
+#define TGT_AUD_CONFIG_TV_DRIVER                   Tv
+#define TGT_AUD_CONFIG_TV_PARAM                    0
+#define TGT_AUD_CONFIG_TV_OUTPUT_PATH              AUD_SPK_EAR_PIECE
+#define TGT_AUD_CONFIG_TV_OUTPUT_TYPE              AUD_SPEAKER_STEREO
+#define TGT_AUD_CONFIG_TV_INPUT_PATH               AUD_MIC_RECEIVER
+
+#endif // TGT_AUD_CONFIG
+
+
+// #############################################################################
+// #                                                                           #
+// #                           OPTIONNAL DRIVERS                               #
+// #                                                                           #
+// #############################################################################
+
+#ifdef TGT_WITH_TS_MODEL_rda1203_gallite
+// =============================================================================
+// TSD config
+// -----------------------------------------------------------------------------
+/// This fills the TSD_CONFIG_T structure
+// =============================================================================
+#ifndef TGT_TSD_CONFIG
+#define TGT_TSD_CONFIG                                                  \
+    {                                                                   \
+        .penGpio        = HAL_GPIO_NONE,                                \
+        .debounceTime   = 5*HAL_TICK1S/1000,                            \
+        .downPeriod     = 3,                                            \
+        .upPeriod       = 3,                                            \
+        .maxError       = 0x50                                          \
+    }
+
+#endif // TGT_TSD_CONFIG
+#endif // TGT_WITH_TS_MODEL_rda1203_gallite
+
+#ifdef TGT_WITH_TS_MODEL_rda8810_ap
+#ifndef TGT_TSD_CONFIG
+#define TGT_TSD_CONFIG                                                  \
+    {                                                                   \
+        .penGpio        = HAL_GPIO_2,                                \
+        .debounceTime   = 1*HAL_TICK1S/1000,                            \
+        .downPeriod     = 3,                                            \
+        .upPeriod       = 3,                                            \
+        .maxError       = 0x50                                          \
+    }
+
+#endif // TGT_TSD_CONFIG
+#endif // TGT_WITH_TS_MODEL_rda8810_ap
+
+#ifdef TGT_WITH_TS_MODEL_rda8810_ap_gtp868
+#ifndef TGT_TSD_CONFIG
+#define TGT_TSD_CONFIG                                                  \
+    {                                                                   \
+        .penGpio        = HAL_GPIO_2,                                \
+        .debounceTime   = 1*HAL_TICK1S/1000,                            \
+        .downPeriod     = 3,                                            \
+        .upPeriod       = 3,                                            \
+        .maxError       = 0x50                                          \
+    }
+
+#endif // TGT_TSD_CONFIG
+#endif // TGT_WITH_TS_MODEL_rda8810_ap_gtp868
+
+#ifdef TGT_WITH_TS_MODEL_ap_msg2133
+#ifndef TGT_TSD_CONFIG
+#define TGT_TSD_CONFIG                                                  \
+    {                                                                   \
+        .ts_Gpio_int       = HAL_GPIO_1,                                          \
+        .ts_Gpio_rst      = HAL_GPIO_24,                                         \
+        .rst_pd_level      = 1,                                          \
+        .int_pd_level      = 1,                                          \
+        .i2c_id      = 0x26,                                          \
+        .ts_int_rise      = FALSE,                                          \
+    }
+
+#endif // TGT_TSD_CONFIG
+#endif // TGT_WITH_TS_MODEL_rda8810_ap_gtp868
+
+
+#ifdef TGT_WITH_GPIOI2C_MODEL_i2c_gpio
+// =============================================================================
+//  GPIO I2C config
+// -----------------------------------------------------------------------------
+/// This fills the GPIOI2C CONFIG_T structure
+// =============================================================================
+#ifndef TGT_GPIOI2C_CONFIG
+#define TGT_GPIOI2C_CONFIG                                              \
+    {                                                                   \
+	.i2c_gpio_Bps       = GPIO_I2C_BPS_80K ,                        \
+        .scl_i2c_gpio       = HAL_GPIO_4 ,                             \
+        .scl_i2c_gpo        = HAL_GPO_NONE ,                            \
+        .sda_i2c            = HAL_GPIO_5                               \
+    }
+#endif // TGT_GPIOI2C_CONFIG
+#endif // TGT_WITH_GPIOI2C_MODEL_i2c_gpio
+
+// ?d config
+// -----------------------------------------------------------------------------
+/// @todo add other driver configuration here if needed
+// =============================================================================
+
+
+// #############################################################################
+// #                                                                           #
+// #                                 SERVICES                                  #
+// #                                                                           #
+// #############################################################################
+
+
+// =============================================================================
+// ?s config
+// -----------------------------------------------------------------------------
+/// @todo add other service configuration here if needed
+// =============================================================================
+
+
+#endif //_TGT_BOARD_CFG_H_
+
diff --git a/include/rda/tgt_gpio_setting.h b/include/rda/tgt_gpio_setting.h
new file mode 100644
index 0000000000..829ea56b07
--- /dev/null
+++ b/include/rda/tgt_gpio_setting.h
@@ -0,0 +1,714 @@
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+//            Copyright (C) 2003-2007, Coolsand Technologies, Inc.            //
+//                            All Rights Reserved                             //
+//                                                                            //
+//      This source code is the property of Coolsand Technologies and is      //
+//      confidential.  Any  modification, distribution,  reproduction or      //
+//      exploitation  of  any content of this file is totally forbidden,      //
+//      except  with the  written permission  of  Coolsand Technologies.      //
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+//                                                                            //
+/// @file tgt_ap_gpio_setting.h
+/// That file describes the configuration of the AP board gpio setting for the specific
+/// 8810 base target.
+//                                                                            //
+////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __TGT_GPIO_SETTING_H__
+#define __TGT_GPIO_SETTING_H__
+
+//Compare to BB_GPIO_mapping
+#define AS_ALT_FUNC     0
+/// pin used as it's GPIO function
+#define AS_GPIO         1
+/// GPIO not connected, set to driving 0 for low power
+#define NOT_CONNECTED   2
+
+// -----------------------------------------------------------------------------
+// GPIO(0)
+#define TGT_HAL_GPIO_C_0_USED AS_GPIO
+// GPIO(1)  // GPIO_C1 INT:nil:nil:nil
+#define TGT_HAL_GPIO_C_1_USED AS_GPIO
+// GPIO(2)  // GPIO_C2 INT:nil:nil:nil
+#define TGT_HAL_GPIO_C_2_USED NOT_CONNECTED
+// GPIO(3)  // GPIO_C3 INT:nil:nil:nil
+#define TGT_HAL_GPIO_C_3_USED NOT_CONNECTED
+// GPIO(4)  // GPIO_C4 INT:nil:nil:nil
+#define TGT_HAL_GPIO_C_4_USED AS_GPIO
+// GPIO(5)  // GPIO_C5 INT:nil:nil:nil
+#define TGT_HAL_GPIO_C_5_USED AS_GPIO
+// GPIO(6)  // UART1 Receive Data:nil:nil:nil
+#define TGT_HAL_GPIO_C_6_USED AS_ALT_FUNC
+// GPIO(7)  // HST_RXD:GPIO_7:UART2_RXD-UART1_DTR
+#define TGT_HAL_GPIO_C_7_USED AS_ALT_FUNC
+// GPIO(8)  // HST_TXD:GPIO_8:UART2_TXD-UART1 Data Carrier Detect
+#define TGT_HAL_GPIO_C_8_USED AS_ALT_FUNC
+// GPIO(9)  // SD CLK:nil:nil:nil
+#define TGT_HAL_GPIO_C_9_USED AS_ALT_FUNC
+// GPIO(10) // SD CMD:nil:nil:nil
+#define TGT_HAL_GPIO_C_10_USED AS_ALT_FUNC
+// GPIO(11) // SD data0:nil:nil:nil
+#define TGT_HAL_GPIO_C_11_USED AS_ALT_FUNC
+// GPIO(12) // SD data1:nil:nil:nil
+#define TGT_HAL_GPIO_C_12_USED AS_ALT_FUNC
+// GPIO(13) // SD data2:nil:nil:nil
+#define TGT_HAL_GPIO_C_13_USED AS_ALT_FUNC
+// GPIO(14) // SD data3:nil:nil:nil
+#define TGT_HAL_GPIO_C_14_USED AS_ALT_FUNC
+// GPIO(15) // SD CLK:nil:nil:nil
+#define TGT_HAL_GPIO_C_15_USED AS_ALT_FUNC
+// GPIO(16) // SD CMD:nil:nil:nil
+#define TGT_HAL_GPIO_C_16_USED AS_ALT_FUNC
+// GPIO(17) // SD data0:nil:nil:nil
+#define TGT_HAL_GPIO_C_17_USED AS_ALT_FUNC
+// GPIO(18) // SD data1:nil:nil:nil
+#define TGT_HAL_GPIO_C_18_USED AS_ALT_FUNC
+// GPIO(19) // SD data2:nil:nil:nil
+#define TGT_HAL_GPIO_C_19_USED AS_ALT_FUNC
+// GPIO(20) // SD data3:nil:nil:nil
+#define TGT_HAL_GPIO_C_20_USED AS_ALT_FUNC
+// GPIO(21) // SPI1_CLK:SPI_BB_CLK:nil:nil
+#define TGT_HAL_GPIO_C_21_USED AS_ALT_FUNC
+// GPIO(22) // SPI1_CS_0:SPI_BB_CS_0:nil:nil
+#define TGT_HAL_GPIO_C_22_USED AS_ALT_FUNC
+// GPIO(23) // SPI1_DIO:SPI_BB_DIO:nil:nil
+#define TGT_HAL_GPIO_C_23_USED AS_ALT_FUNC
+// GPIO(24) // SPI1_DI:SPI_BB_DI:nil:nil
+#define TGT_HAL_GPIO_C_24_USED AS_GPIO
+// GPIO(25) // GPIO_C25:SIM2_RST:nil:nil
+#define TGT_HAL_GPIO_C_25_USED AS_ALT_FUNC
+// GPIO(26) // GPIO_C26:SIM2_CLK:nil:nil
+#define TGT_HAL_GPIO_C_26_USED AS_ALT_FUNC
+// GPIO(27) // GPIO_C27:SIM2_DIO:nil:nil
+//#define TGT_HAL_GPIO_C_27_USED AS_ALT_FUNC
+#define TGT_HAL_GPIO_C_27_USED AS_GPIO
+// GPIO(28) // GPIO_C28:SIM3_RST:nil:nil
+//#define TGT_HAL_GPIO_C_28_USED AS_ALT_FUNC
+#define TGT_HAL_GPIO_C_28_USED AS_ALT_FUNC
+// GPIO(29) // GPIO_C29:SIM3_CLK:nil:nil
+#define TGT_HAL_GPIO_C_29_USED AS_ALT_FUNC
+// GPIO(30) // GPIO_C30:SIM3_DIO:nil:nil
+//#define TGT_HAL_GPIO_C_30_USED AS_ALT_FUNC
+#define TGT_HAL_GPIO_C_30_USED AS_GPIO
+// GPIO(31) // LCD DATA
+#define TGT_HAL_GPIO_C_31_USED AS_ALT_FUNC
+
+// -----------------------------------------------------------------------------
+// Each TCO can be assigned one of the following values:
+// 0 : unused
+// 1 : used
+// -----------------------------------------------------------------------------
+// TCO(0)   // GPIO_B3 INT--KEYOUT_0--TCO_0
+#define TGT_HAL_TCO_0_USED 0
+// TCO(1)   // GPIO_B4 INT--KEYOUT_1--TCO_1
+#define TGT_HAL_TCO_1_USED 0
+// TCO(2)   // GPIO_B5 INT--KEYOUT_2--TCO_2
+#define TGT_HAL_TCO_2_USED 0
+// TCO(3)
+#define TGT_HAL_TCO_3_USED 0
+// TCO(4)
+#define TGT_HAL_TCO_4_USED 0
+// TCO(5)
+#define TGT_HAL_TCO_5_USED 0
+// TCO(6)
+#define TGT_HAL_TCO_6_USED 0
+// TCO(7)
+#define TGT_HAL_TCO_7_USED 0
+// TCO(8)
+#define TGT_HAL_TCO_8_USED 0
+// TCO(9)
+#define TGT_HAL_TCO_9_USED 0
+// TCO(10)
+#define TGT_HAL_TCO_10_USED 0
+// TCO(11)
+#define TGT_HAL_TCO_11_USED 0
+
+// -----------------------------------------------------------------------------
+// GPIO(0)  // GPIO_A0 INT:I2C2_SCL:nil:Monitor_0
+#define TGT_AP_HAL_GPIO_A_0_USED AS_ALT_FUNC
+// GPIO(1)  // GPIO_A1 INT:I2C2_SDA:nil:Monitor_1
+#define TGT_AP_HAL_GPIO_A_1_USED AS_ALT_FUNC
+// GPIO(2)  // GPIO_A2 INT:SPI2_CLK:nil:Monitor_2
+#define TGT_AP_HAL_GPIO_A_2_USED AS_GPIO
+// GPIO(3)  // GPIO_A3 INT:SPI2_DIO:nil:Monitor_3
+#define TGT_AP_HAL_GPIO_A_3_USED AS_GPIO
+// GPIO(4)  // GPIO_A4 INT:SPI2_DI:nil:Monitor_4
+#define TGT_AP_HAL_GPIO_A_4_USED AS_GPIO
+// GPIO(5)  // GPIO_A5 INT:SPI2_CS_0:nil:Monitor_5
+#define TGT_AP_HAL_GPIO_A_5_USED AS_GPIO
+// GPIO(6)  // GPIO_A6 INT:SPI2_CS_1:KEYIN_3:Monitor_6
+#define TGT_AP_HAL_GPIO_A_6_USED AS_GPIO
+// GPIO(7)  // GPIO_A7 INT:KEYIN_4:LPSCO_1:Monitor_7
+#define TGT_AP_HAL_GPIO_A_7_USED AS_GPIO
+// GPIO(8)  // GPIO_A8:Clock Output
+#define TGT_AP_HAL_GPIO_A_8_USED AS_ALT_FUNC
+// GPIO(9)  // Audio BCK:nil:nil:nil
+#define TGT_AP_HAL_GPIO_A_9_USED AS_ALT_FUNC
+// GPIO(10) // Audio LRCK:DAI_CLK:DAI_SIMPLE_CLK:nil
+#define TGT_AP_HAL_GPIO_A_10_USED AS_ALT_FUNC
+// GPIO(11) // Audio Serial Data In 0:DAI_DI:DAI_SIMPLE_DI:nil
+#define TGT_AP_HAL_GPIO_A_11_USED AS_ALT_FUNC
+// GPIO(12) // Audio Serial Data In 1:DAI_RST:DAI_SIMPLE_RST:nil
+#define TGT_AP_HAL_GPIO_A_12_USED NOT_CONNECTED
+// GPIO(13) // Audio Serial Data Out:DAI_DO:DAI_SIMPLE_DO:nil
+#define TGT_AP_HAL_GPIO_A_13_USED AS_ALT_FUNC
+// GPIO(14) // UART1 Transmit Data:nil:nil:nil
+#define TGT_AP_HAL_GPIO_A_14_USED AS_ALT_FUNC
+// GPIO(15) // UART1 Clear To Send:KEYIN_7:nil:nil
+#define TGT_AP_HAL_GPIO_A_15_USED AS_ALT_FUNC
+// GPIO(16) // UART1 Request To Send:KEYOUT_7:nil:nil
+#define TGT_AP_HAL_GPIO_A_16_USED AS_ALT_FUNC
+// GPIO(17) // SPI1_CS_1:SPI_BB_CS_1:nil:nil
+#define TGT_AP_HAL_GPIO_A_17_USED AS_GPIO
+// GPIO(18) // LCD DATA6:DSI_D2_P:nil:nil
+#define TGT_AP_HAL_GPIO_A_18_USED AS_GPIO
+// GPIO(19) // LCD DATA7:DSI_D2_N:nil:nil
+#define TGT_AP_HAL_GPIO_A_19_USED AS_GPIO
+// GPIO(20) // LCD_WR:DSI_D3_P:lcd_rgb_de:M_SPI_D3
+#define TGT_AP_HAL_GPIO_A_20_USED AS_GPIO
+// GPIO(21) // LCD_RS:DSI_D3_N:lcd_rgb_hsync:M_SPI_D2
+#define TGT_AP_HAL_GPIO_A_21_USED AS_GPIO
+// GPIO(22) // LCD_RD:SPI_LCD_SDC:lcd_rgb_vsync:M_SPI_D1
+#define TGT_AP_HAL_GPIO_A_22_USED AS_GPIO
+// GPIO(22) // LCD_FMARK:SPI_LCD_CLK:lcd_rgb_clk:M_SPI_CLK
+#define TGT_AP_HAL_GPIO_A_23_USED AS_GPIO
+// GPIO(24) // LCD_DATA_8:NFD_8:nil:nil
+#define TGT_AP_HAL_GPIO_A_24_USED AS_GPIO
+// GPIO(25) // LCD_DATA_9:NFD_9:nil:nil
+#define TGT_AP_HAL_GPIO_A_25_USED NOT_CONNECTED
+// GPIO(26) // LCD_DATA_10:NFD_10:nil:nil
+#define TGT_AP_HAL_GPIO_A_26_USED NOT_CONNECTED
+// GPIO(27) // LCD_DATA_11:NFD_11:nil:nil
+#define TGT_AP_HAL_GPIO_A_27_USED NOT_CONNECTED
+// GPIO(28) // LCD_DATA_12:NFD_12:nil:nil
+#define TGT_AP_HAL_GPIO_A_28_USED NOT_CONNECTED
+// GPIO(29) // LCD_DATA_13:NFD_13:nil:nil
+#define TGT_AP_HAL_GPIO_A_29_USED NOT_CONNECTED
+// GPIO(30) // LCD_DATA_14:NFD_14:nil:nil
+#define TGT_AP_HAL_GPIO_A_30_USED NOT_CONNECTED
+// GPIO(31) // LCD_DATA_15:NFD_15:nil:nil
+#define TGT_AP_HAL_GPIO_A_31_USED NOT_CONNECTED
+
+// ::::::::::::::::::::::::::::::::::::::-
+// GPIO(0)  // GPIO_B0 INT:KEYIN_0:KEYIN_0:Monitor_8
+#define TGT_AP_HAL_GPIO_B_0_USED NOT_CONNECTED
+// GPIO(1)  // GPIO_B1 INT:KEYIN_1:SPI1_CS_2:Monitor_9
+#define TGT_AP_HAL_GPIO_B_1_USED AS_GPIO
+// GPIO(2)  // GPIO_B2 INT:KEYIN_2:I2S_DI_2:Monitor_10
+#define TGT_AP_HAL_GPIO_B_2_USED AS_GPIO
+// GPIO(3)  // GPIO_B3 INT:KEYOUT_0:TCO_0:Monitor_11
+#define TGT_AP_HAL_GPIO_B_3_USED AS_GPIO
+// GPIO(4)  // GPIO_B4 INT:KEYOUT_1:TCO_1:Monitor_12
+#define TGT_AP_HAL_GPIO_B_4_USED NOT_CONNECTED
+// GPIO(5)  // GPIO_B5 INT:KEYOUT_2:TCO_2:Monitor_13
+#define TGT_AP_HAL_GPIO_B_5_USED AS_GPIO
+// GPIO(6)  // GPIO_B6 INT:I2C3_SCL:KEYOUT_3:Monitor_14
+#define TGT_AP_HAL_GPIO_B_6_USED AS_ALT_FUNC
+// GPIO(7)  // GPIO_B7 INT:I2C3_SDA:KEYOUT_4:Monitor_15
+#define TGT_AP_HAL_GPIO_B_7_USED AS_ALT_FUNC
+// GPIO(8)  // UART2_CTS:KEYIN_6:UART1 Data Set Ready:nil
+#define TGT_AP_HAL_GPIO_B_8_USED NOT_CONNECTED
+// GPIO(9)  // UART2_RTS:KEYOUT_6:UART1 Ring Indicator:nil
+#define TGT_AP_HAL_GPIO_B_9_USED NOT_CONNECTED
+// GPIO(10) // CAM_RST:I2C2_SCL:nil:nil
+#define TGT_AP_HAL_GPIO_B_10_USED AS_GPIO
+// GPIO(11) // CAM_PDN:I2C2_SDA:nil:nil
+#define TGT_AP_HAL_GPIO_B_11_USED AS_GPIO
+// GPIO(12) // CAM_CLK:nil:nil:nil
+#define TGT_AP_HAL_GPIO_B_12_USED AS_ALT_FUNC
+// GPIO(13) // CAM_VSYNC:CSI1_CLK_P:M_SPI_CLK:nil
+#define TGT_AP_HAL_GPIO_B_13_USED AS_ALT_FUNC
+// GPIO(14) // CAM_HREF:CSI2_CLK_P:nil:nil
+#define TGT_AP_HAL_GPIO_B_14_USED AS_ALT_FUNC
+// GPIO(15) // CAM_PCLK:CSI2_CLK_N:SPI_CAM_SCK:nil
+#define TGT_AP_HAL_GPIO_B_15_USED AS_ALT_FUNC
+// GPIO(16) // CAM_Data 0:CSI2_D0_P:SPI_CAM_DI/d0:nil
+#define TGT_AP_HAL_GPIO_B_16_USED AS_ALT_FUNC
+// GPIO(17) // CAM_Data 1:CSI2_D0_N:SPI_CAM_OF/d1:nil
+#define TGT_AP_HAL_GPIO_B_17_USED AS_ALT_FUNC
+// GPIO(18) // CAM_Data 2:CSI2_D1_P:SPI_CAM_RD/d2:nil
+#define TGT_AP_HAL_GPIO_B_18_USED AS_ALT_FUNC
+// GPIO(19) // CAM_Data 3:CSI2_D1_N:SPI_CAM_SSN/d3:nil
+#define TGT_AP_HAL_GPIO_B_19_USED AS_ALT_FUNC
+// GPIO(20) // CAM_Data 4:CSI1_D0_P:M_SPI_D0:nil
+#define TGT_AP_HAL_GPIO_B_20_USED AS_ALT_FUNC
+// GPIO(21) // CAM_Data 5:CSI1_D0_N:M_SPI_D1:nil
+#define TGT_AP_HAL_GPIO_B_21_USED AS_ALT_FUNC
+// GPIO(22) // CAM_Data 6:CSI1_D1_P:M_SPI_D2:nil
+#define TGT_AP_HAL_GPIO_B_22_USED AS_ALT_FUNC
+// GPIO(23) // CAM_Data 7:CSI1_D1_N:M_SPI_D3:nil
+#define TGT_AP_HAL_GPIO_B_23_USED AS_ALT_FUNC
+// GPIO(24) // SPI Flash CS0:CSI1_CLK_N:nil:nil
+//#define TGT_AP_HAL_GPIO_B_24_USED NOT_CONNECTED
+#define TGT_AP_HAL_GPIO_B_24_USED AS_GPIO
+// GPIO(25) // NFCLE:GPIO_B25
+#define TGT_AP_HAL_GPIO_B_25_USED AS_ALT_FUNC
+// GPIO(26) // NFWEN:GPIO_B26
+#define TGT_AP_HAL_GPIO_B_26_USED AS_ALT_FUNC
+// GPIO(27) // NFWPN:GPIO_B27
+#define TGT_AP_HAL_GPIO_B_27_USED AS_ALT_FUNC
+// GPIO(28) // NFREN:GPIO_B28
+#define TGT_AP_HAL_GPIO_B_28_USED AS_ALT_FUNC
+// GPIO(29) // NFRB:GPIO_B29
+#define TGT_AP_HAL_GPIO_B_29_USED AS_ALT_FUNC
+// GPIO(30) // I2C1_SCL:nil-nil-nil
+#define TGT_AP_HAL_GPIO_B_30_USED AS_ALT_FUNC
+// GPIO(31) // I2C1_SDA:nil-nil-nil
+#define TGT_AP_HAL_GPIO_B_31_USED AS_ALT_FUNC
+
+// ::::::::::::::::::::::::::::::::::::::-
+// GPIO(0)  // UART3_RXD:GPIO_D0 INT:nil:nil
+#define TGT_AP_HAL_GPIO_D_0_USED AS_ALT_FUNC
+// GPIO(1)  // UART3_TXD:GPIO_D1 INT:nil:nil
+#define TGT_AP_HAL_GPIO_D_1_USED AS_ALT_FUNC
+// GPIO(2)  // UART3_CTS:GPIO_D2 INT:nil:nil
+#define TGT_AP_HAL_GPIO_D_2_USED AS_ALT_FUNC
+// GPIO(3)  // UART3_RTS:GPIO_D3 INT:nil:nil
+#define TGT_AP_HAL_GPIO_D_3_USED AS_ALT_FUNC
+// GPIO(4)  // NFDQS:GPIO_D4 INT:nil:nil
+#define TGT_AP_HAL_GPIO_D_4_USED AS_ALT_FUNC
+// GPIO(5)  // Volume down
+#define TGT_AP_HAL_GPIO_D_5_USED AS_GPIO
+// GPIO(6)  // Volume up
+#define TGT_AP_HAL_GPIO_D_6_USED AS_GPIO
+// GPIO(7)
+#define TGT_AP_HAL_GPIO_D_7_USED AS_ALT_FUNC
+// GPIO(8)
+#define TGT_AP_HAL_GPIO_D_8_USED AS_ALT_FUNC
+// GPIO(9)
+#define TGT_AP_HAL_GPIO_D_9_USED AS_ALT_FUNC
+// GPIO(10)
+#define TGT_AP_HAL_GPIO_D_10_USED AS_ALT_FUNC
+// GPIO(11)
+#define TGT_AP_HAL_GPIO_D_11_USED AS_ALT_FUNC
+// GPIO(12)
+#define TGT_AP_HAL_GPIO_D_12_USED AS_ALT_FUNC
+// GPIO(13)
+#define TGT_AP_HAL_GPIO_D_13_USED AS_ALT_FUNC
+// GPIO(14)
+#define TGT_AP_HAL_GPIO_D_14_USED AS_ALT_FUNC
+// GPIO(15)
+#define TGT_AP_HAL_GPIO_D_15_USED AS_ALT_FUNC
+// GPIO(16)
+#define TGT_AP_HAL_GPIO_D_16_USED AS_ALT_FUNC
+// GPIO(17)
+#define TGT_AP_HAL_GPIO_D_17_USED AS_ALT_FUNC
+// GPIO(18)
+#define TGT_AP_HAL_GPIO_D_18_USED AS_ALT_FUNC
+// GPIO(19)
+#define TGT_AP_HAL_GPIO_D_19_USED AS_ALT_FUNC
+// GPIO(20)
+#define TGT_AP_HAL_GPIO_D_20_USED AS_ALT_FUNC
+// GPIO(21)
+#define TGT_AP_HAL_GPIO_D_21_USED AS_ALT_FUNC
+// GPIO(22)
+#define TGT_AP_HAL_GPIO_D_22_USED AS_ALT_FUNC
+// GPIO(23)
+#define TGT_AP_HAL_GPIO_D_23_USED AS_ALT_FUNC
+// GPIO(24)
+#define TGT_AP_HAL_GPIO_D_24_USED AS_ALT_FUNC
+// GPIO(25)
+#define TGT_AP_HAL_GPIO_D_25_USED AS_ALT_FUNC
+// GPIO(26)
+#define TGT_AP_HAL_GPIO_D_26_USED AS_ALT_FUNC
+// GPIO(27)
+#define TGT_AP_HAL_GPIO_D_27_USED AS_ALT_FUNC
+// GPIO(28)
+#define TGT_AP_HAL_GPIO_D_28_USED AS_ALT_FUNC
+// GPIO(29)
+#define TGT_AP_HAL_GPIO_D_29_USED AS_ALT_FUNC
+// GPIO(30)
+#define TGT_AP_HAL_GPIO_D_30_USED AS_ALT_FUNC
+// GPIO(31)
+#define TGT_AP_HAL_GPIO_D_31_USED AS_ALT_FUNC
+
+// ::::::::::::::::::::::::::::::::::::::-
+// Each GPO can be assigned one of the following values:
+// 0 : unused
+// 1 : used
+// ::::::::::::::::::::::::::::::::::::::-
+// GPO(0)   // GPO 0:PWT:KEYIN_5
+#define TGT_AP_HAL_GPO_A_0_USED 1
+// GPO(1)   // GPO 1:LPG:KEYOUT_5
+#define TGT_AP_HAL_GPO_A_1_USED 1
+// GPO(2)   // GPO 2:PWL_1:CLK_32K
+#define TGT_AP_HAL_GPO_A_2_USED 1
+// GPO(3)   // LCD CS_1:SPI_LCD_CS:GPO_3
+#define TGT_AP_HAL_GPO_A_3_USED 1
+// GPO(4)   // LCD CS_0:SPI_LCD_DIO:GPO_4
+#define TGT_AP_HAL_GPO_A_4_USED 0
+// GPO(5)
+#define TGT_AP_HAL_GPO_A_5_USED 0
+// GPO(6)
+#define TGT_AP_HAL_GPO_A_6_USED 0
+// GPO(7)
+#define TGT_AP_HAL_GPO_A_7_USED 0
+// GPO(8)
+#define TGT_AP_HAL_GPO_A_8_USED 0
+// GPO(9)
+#define TGT_AP_HAL_GPO_A_9_USED 0
+
+// =============================================================================
+//  GPIO pins that can be GPIO_C but are not connected on the board
+//  any pin described here will be driven low all the time for power optimization
+//  It's actually computed from the TGT_HAL_GPIO_C_xx_USED macros above.
+//  DO NOT MODIFY !
+// =============================================================================
+#define TGT_HAL_NO_CONNECT_GPIO_C         ( \
+    ((TGT_HAL_GPIO_C_0_USED & 2) >> 1)    | \
+    (TGT_HAL_GPIO_C_1_USED & 2)           | \
+    ((TGT_HAL_GPIO_C_2_USED & 2) << 1)    | \
+    ((TGT_HAL_GPIO_C_3_USED & 2) << 2)    | \
+    ((TGT_HAL_GPIO_C_4_USED & 2) << 3)    | \
+    ((TGT_HAL_GPIO_C_5_USED & 2) << 4)    | \
+    ((TGT_HAL_GPIO_C_6_USED & 2) << 5)    | \
+    ((TGT_HAL_GPIO_C_7_USED & 2) << 6)    | \
+    ((TGT_HAL_GPIO_C_8_USED & 2) << 7)    | \
+    ((TGT_HAL_GPIO_C_9_USED & 2) << 8)    | \
+    ((TGT_HAL_GPIO_C_10_USED & 2) << 9)   | \
+    ((TGT_HAL_GPIO_C_11_USED & 2) << 10)  | \
+    ((TGT_HAL_GPIO_C_12_USED & 2) << 11)  | \
+    ((TGT_HAL_GPIO_C_13_USED & 2) << 12)  | \
+    ((TGT_HAL_GPIO_C_14_USED & 2) << 13)  | \
+    ((TGT_HAL_GPIO_C_15_USED & 2) << 14)  | \
+    ((TGT_HAL_GPIO_C_16_USED & 2) << 15)  | \
+    ((TGT_HAL_GPIO_C_17_USED & 2) << 16)  | \
+    ((TGT_HAL_GPIO_C_18_USED & 2) << 17)  | \
+    ((TGT_HAL_GPIO_C_19_USED & 2) << 18)  | \
+    ((TGT_HAL_GPIO_C_20_USED & 2) << 19)  | \
+    ((TGT_HAL_GPIO_C_21_USED & 2) << 20)  | \
+    ((TGT_HAL_GPIO_C_22_USED & 2) << 21)  | \
+    ((TGT_HAL_GPIO_C_23_USED & 2) << 22)  | \
+    ((TGT_HAL_GPIO_C_24_USED & 2) << 23)  | \
+    ((TGT_HAL_GPIO_C_25_USED & 2) << 24)  | \
+    ((TGT_HAL_GPIO_C_26_USED & 2) << 25)  | \
+    ((TGT_HAL_GPIO_C_27_USED & 2) << 26)  | \
+    ((TGT_HAL_GPIO_C_28_USED & 2) << 27)  | \
+    ((TGT_HAL_GPIO_C_29_USED & 2) << 28)  | \
+    ((TGT_HAL_GPIO_C_30_USED & 2) << 29)  | \
+    ((TGT_HAL_GPIO_C_31_USED & 2) << 30)  )
+
+
+// =============================================================================
+//  GPIO pins that are actually used as GPIO_C
+//  It's actually computed from the TGT_HAL_GPIO_C_xx_USED macros above.
+//  DO NOT MODIFY !
+// =============================================================================
+#define TGT_HAL_USED_GPIO_C               ( \
+    (TGT_HAL_GPIO_C_0_USED & 1)           | \
+    ((TGT_HAL_GPIO_C_1_USED & 1) << 1)    | \
+    ((TGT_HAL_GPIO_C_2_USED & 1) << 2)    | \
+    ((TGT_HAL_GPIO_C_3_USED & 1) << 3)    | \
+    ((TGT_HAL_GPIO_C_4_USED & 1) << 4)    | \
+    ((TGT_HAL_GPIO_C_5_USED & 1) << 5)    | \
+    ((TGT_HAL_GPIO_C_6_USED & 1) << 6)    | \
+    ((TGT_HAL_GPIO_C_7_USED & 1) << 7)    | \
+    ((TGT_HAL_GPIO_C_8_USED & 1) << 8)    | \
+    ((TGT_HAL_GPIO_C_9_USED & 1) << 9)    | \
+    ((TGT_HAL_GPIO_C_10_USED & 1) << 10)  | \
+    ((TGT_HAL_GPIO_C_11_USED & 1) << 11)  | \
+    ((TGT_HAL_GPIO_C_12_USED & 1) << 12)  | \
+    ((TGT_HAL_GPIO_C_13_USED & 1) << 13)  | \
+    ((TGT_HAL_GPIO_C_14_USED & 1) << 14)  | \
+    ((TGT_HAL_GPIO_C_15_USED & 1) << 15)  | \
+    ((TGT_HAL_GPIO_C_16_USED & 1) << 16)  | \
+    ((TGT_HAL_GPIO_C_17_USED & 1) << 17)  | \
+    ((TGT_HAL_GPIO_C_18_USED & 1) << 18)  | \
+    ((TGT_HAL_GPIO_C_19_USED & 1) << 19)  | \
+    ((TGT_HAL_GPIO_C_20_USED & 1) << 20)  | \
+    ((TGT_HAL_GPIO_C_21_USED & 1) << 21)  | \
+    ((TGT_HAL_GPIO_C_22_USED & 1) << 22)  | \
+    ((TGT_HAL_GPIO_C_23_USED & 1) << 23)  | \
+    ((TGT_HAL_GPIO_C_24_USED & 1) << 24)  | \
+    ((TGT_HAL_GPIO_C_25_USED & 1) << 25)  | \
+    ((TGT_HAL_GPIO_C_26_USED & 1) << 26)  | \
+    ((TGT_HAL_GPIO_C_27_USED & 1) << 27)  | \
+    ((TGT_HAL_GPIO_C_28_USED & 1) << 28)  | \
+    ((TGT_HAL_GPIO_C_29_USED & 1) << 29)  | \
+    ((TGT_HAL_GPIO_C_30_USED & 1) << 30)  | \
+    ((TGT_HAL_GPIO_C_31_USED & 1) << 31)  )
+
+// =============================================================================
+//  TCO pins that are actually used as TCO
+//  It's actually computed from the TGT_HAL_TCO_xx_USED macros above.
+//  DO NOT MODIFY !
+// =============================================================================
+#define TGT_HAL_USED_TCO                ( \
+    (TGT_HAL_TCO_0_USED & 1)            | \
+    ((TGT_HAL_TCO_1_USED & 1) << 1)     | \
+    ((TGT_HAL_TCO_2_USED & 1) << 2)     | \
+    ((TGT_HAL_TCO_3_USED & 1) << 3)     | \
+    ((TGT_HAL_TCO_4_USED & 1) << 4)     | \
+    ((TGT_HAL_TCO_5_USED & 1) << 5)     | \
+    ((TGT_HAL_TCO_6_USED & 1) << 6)     | \
+    ((TGT_HAL_TCO_7_USED & 1) << 7)     | \
+    ((TGT_HAL_TCO_8_USED & 1) << 8)     | \
+    ((TGT_HAL_TCO_9_USED & 1) << 9)     | \
+    ((TGT_HAL_TCO_10_USED & 1) << 10)   | \
+    ((TGT_HAL_TCO_11_USED & 1) << 11)   )
+
+// =============================================================================
+//  GPIO pins that can be GPIO but are not connected on the board
+//  any pin described here will be driven low all the time for power optimization
+//  It's actually computed from the TGT_AP_HAL_GPIO_A_xx_USED macros above.
+//  DO NOT MODIFY !
+// =============================================================================
+#define TGT_AP_HAL_NO_CONNECT_GPIO_A         ( \
+    ((TGT_AP_HAL_GPIO_A_0_USED & 2) >> 1)    | \
+    (TGT_AP_HAL_GPIO_A_1_USED & 2)           | \
+    ((TGT_AP_HAL_GPIO_A_2_USED & 2) << 1)    | \
+    ((TGT_AP_HAL_GPIO_A_3_USED & 2) << 2)    | \
+    ((TGT_AP_HAL_GPIO_A_4_USED & 2) << 3)    | \
+    ((TGT_AP_HAL_GPIO_A_5_USED & 2) << 4)    | \
+    ((TGT_AP_HAL_GPIO_A_6_USED & 2) << 5)    | \
+    ((TGT_AP_HAL_GPIO_A_7_USED & 2) << 6)    | \
+    ((TGT_AP_HAL_GPIO_A_8_USED & 2) << 7)    | \
+    ((TGT_AP_HAL_GPIO_A_9_USED & 2) << 8)    | \
+    ((TGT_AP_HAL_GPIO_A_10_USED & 2) << 9)   | \
+    ((TGT_AP_HAL_GPIO_A_11_USED & 2) << 10)  | \
+    ((TGT_AP_HAL_GPIO_A_12_USED & 2) << 11)  | \
+    ((TGT_AP_HAL_GPIO_A_13_USED & 2) << 12)  | \
+    ((TGT_AP_HAL_GPIO_A_14_USED & 2) << 13)  | \
+    ((TGT_AP_HAL_GPIO_A_15_USED & 2) << 14)  | \
+    ((TGT_AP_HAL_GPIO_A_16_USED & 2) << 15)  | \
+    ((TGT_AP_HAL_GPIO_A_17_USED & 2) << 16)  | \
+    ((TGT_AP_HAL_GPIO_A_18_USED & 2) << 17)  | \
+    ((TGT_AP_HAL_GPIO_A_19_USED & 2) << 18)  | \
+    ((TGT_AP_HAL_GPIO_A_20_USED & 2) << 19)  | \
+    ((TGT_AP_HAL_GPIO_A_21_USED & 2) << 20)  | \
+    ((TGT_AP_HAL_GPIO_A_22_USED & 2) << 21)  | \
+    ((TGT_AP_HAL_GPIO_A_23_USED & 2) << 22)  | \
+    ((TGT_AP_HAL_GPIO_A_24_USED & 2) << 23)  | \
+    ((TGT_AP_HAL_GPIO_A_25_USED & 2) << 24)  | \
+    ((TGT_AP_HAL_GPIO_A_26_USED & 2) << 25)  | \
+    ((TGT_AP_HAL_GPIO_A_27_USED & 2) << 26)  | \
+    ((TGT_AP_HAL_GPIO_A_28_USED & 2) << 27)  | \
+    ((TGT_AP_HAL_GPIO_A_29_USED & 2) << 28)  | \
+    ((TGT_AP_HAL_GPIO_A_30_USED & 2) << 29)  | \
+    ((TGT_AP_HAL_GPIO_A_31_USED & 2) << 30)  )
+
+
+// =============================================================================
+//  GPIO pins that are actually used as GPIO
+//  It's actually computed from the TGT_AP_HAL_GPIO_A_xx_USED macros above.
+//  DO NOT MODIFY !
+// =============================================================================
+#define TGT_AP_HAL_USED_GPIO_A               ( \
+    (TGT_AP_HAL_GPIO_A_0_USED & 1)           | \
+    ((TGT_AP_HAL_GPIO_A_1_USED & 1) << 1)    | \
+    ((TGT_AP_HAL_GPIO_A_2_USED & 1) << 2)    | \
+    ((TGT_AP_HAL_GPIO_A_3_USED & 1) << 3)    | \
+    ((TGT_AP_HAL_GPIO_A_4_USED & 1) << 4)    | \
+    ((TGT_AP_HAL_GPIO_A_5_USED & 1) << 5)    | \
+    ((TGT_AP_HAL_GPIO_A_6_USED & 1) << 6)    | \
+    ((TGT_AP_HAL_GPIO_A_7_USED & 1) << 7)    | \
+    ((TGT_AP_HAL_GPIO_A_8_USED & 1) << 8)    | \
+    ((TGT_AP_HAL_GPIO_A_9_USED & 1) << 9)    | \
+    ((TGT_AP_HAL_GPIO_A_10_USED & 1) << 10)  | \
+    ((TGT_AP_HAL_GPIO_A_11_USED & 1) << 11)  | \
+    ((TGT_AP_HAL_GPIO_A_12_USED & 1) << 12)  | \
+    ((TGT_AP_HAL_GPIO_A_13_USED & 1) << 13)  | \
+    ((TGT_AP_HAL_GPIO_A_14_USED & 1) << 14)  | \
+    ((TGT_AP_HAL_GPIO_A_15_USED & 1) << 15)  | \
+    ((TGT_AP_HAL_GPIO_A_16_USED & 1) << 16)  | \
+    ((TGT_AP_HAL_GPIO_A_17_USED & 1) << 17)  | \
+    ((TGT_AP_HAL_GPIO_A_18_USED & 1) << 18)  | \
+    ((TGT_AP_HAL_GPIO_A_19_USED & 1) << 19)  | \
+    ((TGT_AP_HAL_GPIO_A_20_USED & 1) << 20)  | \
+    ((TGT_AP_HAL_GPIO_A_21_USED & 1) << 21)  | \
+    ((TGT_AP_HAL_GPIO_A_22_USED & 1) << 22)  | \
+    ((TGT_AP_HAL_GPIO_A_23_USED & 1) << 23)  | \
+    ((TGT_AP_HAL_GPIO_A_24_USED & 1) << 24)  | \
+    ((TGT_AP_HAL_GPIO_A_25_USED & 1) << 25)  | \
+    ((TGT_AP_HAL_GPIO_A_26_USED & 1) << 26)  | \
+    ((TGT_AP_HAL_GPIO_A_27_USED & 1) << 27)  | \
+    ((TGT_AP_HAL_GPIO_A_28_USED & 1) << 28)  | \
+    ((TGT_AP_HAL_GPIO_A_29_USED & 1) << 29)  | \
+    ((TGT_AP_HAL_GPIO_A_30_USED & 1) << 30)  | \
+    ((TGT_AP_HAL_GPIO_A_31_USED & 1) << 31)  )
+
+// =============================================================================
+//  GPIO pins that can be GPIO but are not connected on the board
+//  any pin described here will be driven low all the time for power optimization
+//  It's actually computed from the TGT_AP_HAL_GPIO_B_xx_USED macros above.
+//  DO NOT MODIFY !
+// =============================================================================
+#define TGT_AP_HAL_NO_CONNECT_GPIO_B         ( \
+    ((TGT_AP_HAL_GPIO_B_0_USED & 2) >> 1)    | \
+    (TGT_AP_HAL_GPIO_B_1_USED & 2)           | \
+    ((TGT_AP_HAL_GPIO_B_2_USED & 2) << 1)    | \
+    ((TGT_AP_HAL_GPIO_B_3_USED & 2) << 2)    | \
+    ((TGT_AP_HAL_GPIO_B_4_USED & 2) << 3)    | \
+    ((TGT_AP_HAL_GPIO_B_5_USED & 2) << 4)    | \
+    ((TGT_AP_HAL_GPIO_B_6_USED & 2) << 5)    | \
+    ((TGT_AP_HAL_GPIO_B_7_USED & 2) << 6)    | \
+    ((TGT_AP_HAL_GPIO_B_8_USED & 2) << 7)    | \
+    ((TGT_AP_HAL_GPIO_B_9_USED & 2) << 8)    | \
+    ((TGT_AP_HAL_GPIO_B_10_USED & 2) << 9)   | \
+    ((TGT_AP_HAL_GPIO_B_11_USED & 2) << 10)  | \
+    ((TGT_AP_HAL_GPIO_B_12_USED & 2) << 11)  | \
+    ((TGT_AP_HAL_GPIO_B_13_USED & 2) << 12)  | \
+    ((TGT_AP_HAL_GPIO_B_14_USED & 2) << 13)  | \
+    ((TGT_AP_HAL_GPIO_B_15_USED & 2) << 14)  | \
+    ((TGT_AP_HAL_GPIO_B_16_USED & 2) << 15)  | \
+    ((TGT_AP_HAL_GPIO_B_17_USED & 2) << 16)  | \
+    ((TGT_AP_HAL_GPIO_B_18_USED & 2) << 17)  | \
+    ((TGT_AP_HAL_GPIO_B_19_USED & 2) << 18)  | \
+    ((TGT_AP_HAL_GPIO_B_20_USED & 2) << 19)  | \
+    ((TGT_AP_HAL_GPIO_B_21_USED & 2) << 20)  | \
+    ((TGT_AP_HAL_GPIO_B_22_USED & 2) << 21)  | \
+    ((TGT_AP_HAL_GPIO_B_23_USED & 2) << 22)  | \
+    ((TGT_AP_HAL_GPIO_B_24_USED & 2) << 23)  | \
+    ((TGT_AP_HAL_GPIO_B_25_USED & 2) << 24)  | \
+    ((TGT_AP_HAL_GPIO_B_26_USED & 2) << 25)  | \
+    ((TGT_AP_HAL_GPIO_B_27_USED & 2) << 26)  | \
+    ((TGT_AP_HAL_GPIO_B_28_USED & 2) << 27)  | \
+    ((TGT_AP_HAL_GPIO_B_29_USED & 2) << 28)  | \
+    ((TGT_AP_HAL_GPIO_B_30_USED & 2) << 29)  | \
+    ((TGT_AP_HAL_GPIO_B_31_USED & 2) << 30)  )
+
+
+// =============================================================================
+//  GPIO pins that are actually used as GPIO
+//  It's actually computed from the TGT_AP_HAL_GPIO_B_xx_USED macros above.
+//  DO NOT MODIFY !
+// =============================================================================
+#define TGT_AP_HAL_USED_GPIO_B               ( \
+    (TGT_AP_HAL_GPIO_B_0_USED & 1)           | \
+    ((TGT_AP_HAL_GPIO_B_1_USED & 1) << 1)    | \
+    ((TGT_AP_HAL_GPIO_B_2_USED & 1) << 2)    | \
+    ((TGT_AP_HAL_GPIO_B_3_USED & 1) << 3)    | \
+    ((TGT_AP_HAL_GPIO_B_4_USED & 1) << 4)    | \
+    ((TGT_AP_HAL_GPIO_B_5_USED & 1) << 5)    | \
+    ((TGT_AP_HAL_GPIO_B_6_USED & 1) << 6)    | \
+    ((TGT_AP_HAL_GPIO_B_7_USED & 1) << 7)    | \
+    ((TGT_AP_HAL_GPIO_B_8_USED & 1) << 8)    | \
+    ((TGT_AP_HAL_GPIO_B_9_USED & 1) << 9)    | \
+    ((TGT_AP_HAL_GPIO_B_10_USED & 1) << 10)  | \
+    ((TGT_AP_HAL_GPIO_B_11_USED & 1) << 11)  | \
+    ((TGT_AP_HAL_GPIO_B_12_USED & 1) << 12)  | \
+    ((TGT_AP_HAL_GPIO_B_13_USED & 1) << 13)  | \
+    ((TGT_AP_HAL_GPIO_B_14_USED & 1) << 14)  | \
+    ((TGT_AP_HAL_GPIO_B_15_USED & 1) << 15)  | \
+    ((TGT_AP_HAL_GPIO_B_16_USED & 1) << 16)  | \
+    ((TGT_AP_HAL_GPIO_B_17_USED & 1) << 17)  | \
+    ((TGT_AP_HAL_GPIO_B_18_USED & 1) << 18)  | \
+    ((TGT_AP_HAL_GPIO_B_19_USED & 1) << 19)  | \
+    ((TGT_AP_HAL_GPIO_B_20_USED & 1) << 20)  | \
+    ((TGT_AP_HAL_GPIO_B_21_USED & 1) << 21)  | \
+    ((TGT_AP_HAL_GPIO_B_22_USED & 1) << 22)  | \
+    ((TGT_AP_HAL_GPIO_B_23_USED & 1) << 23)  | \
+    ((TGT_AP_HAL_GPIO_B_24_USED & 1) << 24)  | \
+    ((TGT_AP_HAL_GPIO_B_25_USED & 1) << 25)  | \
+    ((TGT_AP_HAL_GPIO_B_26_USED & 1) << 26)  | \
+    ((TGT_AP_HAL_GPIO_B_27_USED & 1) << 27)  | \
+    ((TGT_AP_HAL_GPIO_B_28_USED & 1) << 28)  | \
+    ((TGT_AP_HAL_GPIO_B_29_USED & 1) << 29)  | \
+    ((TGT_AP_HAL_GPIO_B_30_USED & 1) << 30)  | \
+    ((TGT_AP_HAL_GPIO_B_31_USED & 1) << 31)  )
+
+
+
+// =============================================================================
+//  GPIO pins that can be GPIO but are not connected on the board
+//  any pin described here will be driven low all the time for power optimization
+//  It's actually computed from the TGT_AP_HAL_GPIO_D_xx_USED macros above.
+//  DO NOT MODIFY !
+// =============================================================================
+#define TGT_AP_HAL_NO_CONNECT_GPIO_D         ( \
+    ((TGT_AP_HAL_GPIO_D_0_USED & 2) >> 1)    | \
+    (TGT_AP_HAL_GPIO_D_1_USED & 2)           | \
+    ((TGT_AP_HAL_GPIO_D_2_USED & 2) << 1)    | \
+    ((TGT_AP_HAL_GPIO_D_3_USED & 2) << 2)    | \
+    ((TGT_AP_HAL_GPIO_D_4_USED & 2) << 3)    | \
+    ((TGT_AP_HAL_GPIO_D_5_USED & 2) << 4)    | \
+    ((TGT_AP_HAL_GPIO_D_6_USED & 2) << 5)    | \
+    ((TGT_AP_HAL_GPIO_D_7_USED & 2) << 6)    | \
+    ((TGT_AP_HAL_GPIO_D_8_USED & 2) << 7)    | \
+    ((TGT_AP_HAL_GPIO_D_9_USED & 2) << 8)    | \
+    ((TGT_AP_HAL_GPIO_D_10_USED & 2) << 9)   | \
+    ((TGT_AP_HAL_GPIO_D_11_USED & 2) << 10)  | \
+    ((TGT_AP_HAL_GPIO_D_12_USED & 2) << 11)  | \
+    ((TGT_AP_HAL_GPIO_D_13_USED & 2) << 12)  | \
+    ((TGT_AP_HAL_GPIO_D_14_USED & 2) << 13)  | \
+    ((TGT_AP_HAL_GPIO_D_15_USED & 2) << 14)  | \
+    ((TGT_AP_HAL_GPIO_D_16_USED & 2) << 15)  | \
+    ((TGT_AP_HAL_GPIO_D_17_USED & 2) << 16)  | \
+    ((TGT_AP_HAL_GPIO_D_18_USED & 2) << 17)  | \
+    ((TGT_AP_HAL_GPIO_D_19_USED & 2) << 18)  | \
+    ((TGT_AP_HAL_GPIO_D_20_USED & 2) << 19)  | \
+    ((TGT_AP_HAL_GPIO_D_21_USED & 2) << 20)  | \
+    ((TGT_AP_HAL_GPIO_D_22_USED & 2) << 21)  | \
+    ((TGT_AP_HAL_GPIO_D_23_USED & 2) << 22)  | \
+    ((TGT_AP_HAL_GPIO_D_24_USED & 2) << 23)  | \
+    ((TGT_AP_HAL_GPIO_D_25_USED & 2) << 24)  | \
+    ((TGT_AP_HAL_GPIO_D_26_USED & 2) << 25)  | \
+    ((TGT_AP_HAL_GPIO_D_27_USED & 2) << 26)  | \
+    ((TGT_AP_HAL_GPIO_D_28_USED & 2) << 27)  | \
+    ((TGT_AP_HAL_GPIO_D_29_USED & 2) << 28)  | \
+    ((TGT_AP_HAL_GPIO_D_30_USED & 2) << 29)  | \
+    ((TGT_AP_HAL_GPIO_D_31_USED & 2) << 30)  )
+
+
+// =============================================================================
+//  GPIO pins that are actually used as GPIO
+//  It's actually computed from the TGT_AP_HAL_GPIO_D_xx_USED macros above.
+//  DO NOT MODIFY !
+// =============================================================================
+#define TGT_AP_HAL_USED_GPIO_D               ( \
+    (TGT_AP_HAL_GPIO_D_0_USED & 1)           | \
+    ((TGT_AP_HAL_GPIO_D_1_USED & 1) << 1)    | \
+    ((TGT_AP_HAL_GPIO_D_2_USED & 1) << 2)    | \
+    ((TGT_AP_HAL_GPIO_D_3_USED & 1) << 3)    | \
+    ((TGT_AP_HAL_GPIO_D_4_USED & 1) << 4)    | \
+    ((TGT_AP_HAL_GPIO_D_5_USED & 1) << 5)    | \
+    ((TGT_AP_HAL_GPIO_D_6_USED & 1) << 6)    | \
+    ((TGT_AP_HAL_GPIO_D_7_USED & 1) << 7)    | \
+    ((TGT_AP_HAL_GPIO_D_8_USED & 1) << 8)    | \
+    ((TGT_AP_HAL_GPIO_D_9_USED & 1) << 9)    | \
+    ((TGT_AP_HAL_GPIO_D_10_USED & 1) << 10)  | \
+    ((TGT_AP_HAL_GPIO_D_11_USED & 1) << 11)  | \
+    ((TGT_AP_HAL_GPIO_D_12_USED & 1) << 12)  | \
+    ((TGT_AP_HAL_GPIO_D_13_USED & 1) << 13)  | \
+    ((TGT_AP_HAL_GPIO_D_14_USED & 1) << 14)  | \
+    ((TGT_AP_HAL_GPIO_D_15_USED & 1) << 15)  | \
+    ((TGT_AP_HAL_GPIO_D_16_USED & 1) << 16)  | \
+    ((TGT_AP_HAL_GPIO_D_17_USED & 1) << 17)  | \
+    ((TGT_AP_HAL_GPIO_D_18_USED & 1) << 18)  | \
+    ((TGT_AP_HAL_GPIO_D_19_USED & 1) << 19)  | \
+    ((TGT_AP_HAL_GPIO_D_20_USED & 1) << 20)  | \
+    ((TGT_AP_HAL_GPIO_D_21_USED & 1) << 21)  | \
+    ((TGT_AP_HAL_GPIO_D_22_USED & 1) << 22)  | \
+    ((TGT_AP_HAL_GPIO_D_23_USED & 1) << 23)  | \
+    ((TGT_AP_HAL_GPIO_D_24_USED & 1) << 24)  | \
+    ((TGT_AP_HAL_GPIO_D_25_USED & 1) << 25)  | \
+    ((TGT_AP_HAL_GPIO_D_26_USED & 1) << 26)  | \
+    ((TGT_AP_HAL_GPIO_D_27_USED & 1) << 27)  | \
+    ((TGT_AP_HAL_GPIO_D_28_USED & 1) << 28)  | \
+    ((TGT_AP_HAL_GPIO_D_29_USED & 1) << 29)  | \
+    ((TGT_AP_HAL_GPIO_D_30_USED & 1) << 30)  | \
+    ((TGT_AP_HAL_GPIO_D_31_USED & 1) << 31)  )
+
+
+// =============================================================================
+//  GPO pins that are actually used as GPO_A
+//  It's actually computed from the TGT_AP_HAL_GPO_A_xx_USED macros above.
+//  DO NOT MODIFY !
+// =============================================================================
+#define TGT_AP_HAL_USED_GPO_A                ( \
+    (TGT_AP_HAL_GPO_A_0_USED & 1)            | \
+    ((TGT_AP_HAL_GPO_A_1_USED & 1) << 1)     | \
+    ((TGT_AP_HAL_GPO_A_2_USED & 1) << 2)     | \
+    ((TGT_AP_HAL_GPO_A_3_USED & 1) << 3)     | \
+    ((TGT_AP_HAL_GPO_A_4_USED & 1) << 4)     | \
+    ((TGT_AP_HAL_GPO_A_5_USED & 1) << 5)     | \
+    ((TGT_AP_HAL_GPO_A_6_USED & 1) << 6)     | \
+    ((TGT_AP_HAL_GPO_A_7_USED & 1) << 7)     | \
+    ((TGT_AP_HAL_GPO_A_8_USED & 1) << 8)     | \
+    ((TGT_AP_HAL_GPO_A_9_USED & 1) << 9)     )
+
+
+#endif
diff --git a/include/rda/tgt_types.h b/include/rda/tgt_types.h
new file mode 100644
index 0000000000..f2e222fd8a
--- /dev/null
+++ b/include/rda/tgt_types.h
@@ -0,0 +1,261 @@
+/*
+ * Copyright (C) 2013 RDA Microelectronics Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef _TGT_TYPES_H_
+#define _TGT_TYPES_H_
+
+#define KEY_MAP
+#define KEY_BOOT_DOWNLOAD
+#define TGT_RFD_CONFIG
+#define TGT_PMD_CONFIG
+#define TGT_AUD_CONFIG
+
+typedef unsigned char BOOL;
+
+// =============================================================================
+// HAL_LCD_MODE_T
+// -----------------------------------------------------------------------------
+/// The LCD interface modes.
+// =============================================================================
+typedef enum
+{
+    HAL_LCD_MODE_SPI,
+    HAL_LCD_MODE_PARALLEL_16BIT,
+    HAL_LCD_MODE_DSI,
+    HAL_LCD_MODE_RGB_16BIT,
+    HAL_LCD_MODE_RGB_24BIT,
+
+    HAL_LCD_MODE_QTY,
+} HAL_LCD_MODE_T;
+
+// =============================================================================
+// HAL_CAM_MODE_T
+// -----------------------------------------------------------------------------
+/// The camera interface modes.
+// =============================================================================
+typedef enum
+{
+    HAL_CAM_MODE_PARALLEL,
+    HAL_CAM_MODE_SPI,
+    HAL_CAM_MODE_CSI,
+
+    HAL_CAM_MODE_QTY,
+} HAL_CAM_MODE_T;
+
+// =============================================================================
+// HAL_CAM_CSI_ID_T
+// -----------------------------------------------------------------------------
+/// The camera CSI IDs.
+// =============================================================================
+typedef enum
+{
+    HAL_CAM_CSI_NONE,
+    HAL_CAM_CSI_1,
+    HAL_CAM_CSI_2,
+
+    HAL_CAM_CSI_ID_QTY,
+} HAL_CAM_CSI_ID_T;
+
+// =============================================================================
+// HAL_CFG_SDMMC_T
+// -----------------------------------------------------------------------------
+/// This structure describes the SDMMC configuration for a given target.
+// =============================================================================
+typedef struct
+{
+    /// The sdmmc is used.
+    BOOL sdmmcUsed :1;
+    /// The sdmmc2 is used.
+    BOOL sdmmc2Used :1;
+    /// The sdmmc3 is used.
+    BOOL sdmmc3Used :1;
+} HAL_CFG_SDMMC_T;
+
+// =============================================================================
+// HAL_CFG_CAM_T
+// -----------------------------------------------------------------------------
+/// This structure describes the camera configuration for a given target.
+/// The first field identify if camera is used.
+/// The second and third field is the RemapFlag which identify if camera PDN/RST
+/// need to be remapped to other GPIOs instead of default (GPIO_5 and GPIO_4),
+/// for the first camera sensor.
+/// The fourth and fifth field is the remapped pin when RemapFlag is set, for the
+/// first camera sensor.
+/// The sixth and seventh fields are used to describe which GPIOs are used for
+/// the PDN/RST lines of the optional second camera sensor. This second camera
+/// sensor can only be used on with GPIOs to control its PDN and RST lines.
+// =============================================================================
+typedef struct
+{
+    /// \c TRUE if the rear camera is used
+    BOOL            camUsed :1;
+    /// The polarity of the Power DowN line, for the rear sensor.
+    BOOL            camPdnActiveH :1;
+    /// The polarity of the Reset line, for the rear sensor.
+    BOOL            camRstActiveH :1;
+    /// The remapped GPIO controlling PDN (-1 if not remapped), for the rear sensor.
+    INT32           camPdnRemap;
+    /// The remapped GPIO controlling RST (-1 if not remapped), for the rear sensor.
+    INT32           camRstRemap;
+    /// The CSI ID (valid only if camera mode is CSI)
+    HAL_CAM_CSI_ID_T camCsiId;
+    /// \c TRUE if the front camera is used
+    BOOL            cam1Used :1;
+    /// The polarity of the Power DowN line, for the front sensor.
+    BOOL            cam1PdnActiveH :1;
+    /// The polarity of the Reset line, for the front sensor.
+    BOOL            cam1RstActiveH :1;
+    /// The remapped GPIO controlling PDN (-1 if not remapped), for the front sensor.
+    INT32           cam1PdnRemap;
+    /// The remapped GPIO controlling RST (-1 if not remapped), for the front sensor.
+    INT32           cam1RstRemap;
+    /// The CSI ID (valid only if camera mode is CSI)
+    HAL_CAM_CSI_ID_T cam1CsiId;
+    /// The camera interface mode
+    HAL_CAM_MODE_T  camMode;
+} HAL_CFG_CAM_T;
+
+// =============================================================================
+// HAL_CFG_PWM_T
+// -----------------------------------------------------------------------------
+/// This structure describes the PWM configuration for a given target.
+/// The fields tell wether the pin corresponding to PWM output
+/// is actually used as PWM output and not as something else (for
+/// instance as a GPIO).
+// =============================================================================
+typedef struct
+{
+    /// \c TRUE if the PWL0 is used
+    BOOL pwl0Used :1;
+    /// \c TRUE if the PWL1 is used
+    BOOL pwl1Used :1;
+    /// \c TRUE if the PWT is used
+    BOOL pwtUsed :1;
+    /// \c TRUE if the LPG is used
+    BOOL lpgUsed :1;
+} HAL_CFG_PWM_T;
+
+// =============================================================================
+// HAL_CFG_I2C_T
+// -----------------------------------------------------------------------------
+/// This structure describes the I2C configuration for a given target. The
+/// fields tell wether the corresponding I2C pins are actually used
+/// for I2C and not as something else (for instance as a GPIO).
+// =============================================================================
+typedef struct
+{
+    /// \c TRUE if the I2C pins are used
+    BOOL i2cUsed :1;
+    /// \c TRUE if the I2C2 pins are used
+    BOOL i2c2Used :1;
+    /// \c TRUE if the I2C2 pins are used from cam pins
+    BOOL i2c2PinsCam :1;
+    /// \c TRUE if the I2C3 pins are used
+    BOOL i2c3Used :1;
+} HAL_CFG_I2C_T;
+
+// =============================================================================
+// HAL_CFG_I2S_T
+// -----------------------------------------------------------------------------
+/// This structure describes the I2S configuration for a given target. The
+/// fields tell wether the corresponding I2S pin is actually used
+/// for I2S and not as something else (for instance as a GPIO).
+// =============================================================================
+typedef struct
+{
+    /// \c TRUE if the data out pin is used
+    BOOL doUsed :1;
+    BOOL :3;
+    /// \c TRUE if corresponding input is used
+    BOOL di0Used :1;
+    BOOL di1Used :1;
+    BOOL di2Used :1;
+} HAL_CFG_I2S_T;
+
+// =============================================================================
+// HAL_UART_CONFIG_T
+// -----------------------------------------------------------------------------
+/// Used to describes a configuration for used pin by an UART for a given target.
+// =============================================================================
+typedef enum
+{
+    /// invalid
+    HAL_UART_CONFIG_INVALID = 0,
+
+    /// UART is not used
+    HAL_UART_CONFIG_NONE,
+
+    /// UART use only data lines (TXD & RXD)
+    HAL_UART_CONFIG_DATA,
+
+    /// UART use data and flow control lines (TXD, RXD, RTS & CTS)
+    HAL_UART_CONFIG_FLOWCONTROL,
+
+    /// UART use all lines (TXD, RXD, RTS, CTS, RI, DSR, DCD & DTR)
+    HAL_UART_CONFIG_MODEM,
+
+    HAL_UART_CONFIG_QTY
+} HAL_UART_CONFIG_T;
+
+// =============================================================================
+// HAL_CFG_SPI_T
+// -----------------------------------------------------------------------------
+/// This structure describes the SPI configuration for a given target. The first
+/// fields tell wether the pin corresponding to chip select is actually used
+/// as a chip select and not as something else (for instance as a GPIO).
+/// Then, the polarity of the Chip Select is given. It is only relevant
+/// if the corresponding Chip Select is used as a Chip Select.
+/// Finally which pin is used as input, Can be none, one or the other.
+/// On most chip configuration the input 0 (di0) is on the output pin: SPI_DIO
+// =============================================================================
+typedef struct
+{
+    /// \c TRUE if the corresponding pin is used as a Chip Select.
+    BOOL cs0Used :1;
+    BOOL cs1Used :1;
+    BOOL cs2Used :1;
+    BOOL cs3Used :1;
+    /// \c TRUE if the first edge is falling
+    BOOL cs0ActiveLow :1;
+    BOOL cs1ActiveLow :1;
+    BOOL cs2ActiveLow :1;
+    BOOL cs3ActiveLow :1;
+    /// \c TRUE if corresponding input is used
+    BOOL di0Used :1;
+    BOOL di1Used :1;
+} HAL_CFG_SPI_T;
+
+// =============================================================================
+// HAL_CFG_GOUDA_T
+// -----------------------------------------------------------------------------
+/// This structure describes the GOUDA configuration for a given target.
+/// The first fields tell wether the pin corresponding to chip select is
+/// actually used as a chip select and not as something else (for instance
+/// as a GPIO). If none are used, the GOUDA is considered unused.
+// =============================================================================
+typedef struct
+{
+    /// \c TRUE if the corresponding pin is used as a Chip Select.
+    BOOL cs0Used :1;
+    BOOL cs1Used :1;
+    /// \c TRUE if LCD 16-23 bits are from camera, FALSE from NAND
+    BOOL lcd16_23Cam :1;
+    /// \c LCD interface mode
+    HAL_LCD_MODE_T lcdMode;
+} HAL_CFG_GOUDA_T;
+
+#endif // _TGT_TYPES_H_
diff --git a/include/scsi.h b/include/scsi.h
index c52759c788..89ae45f8e8 100644
--- a/include/scsi.h
+++ b/include/scsi.h
@@ -26,7 +26,9 @@
 
 typedef struct SCSI_cmd_block{
 	unsigned char		cmd[16];					/* command				   */
-	unsigned char		sense_buf[64];		/* for request sense */
+	/* for request sense */
+	unsigned char		sense_buf[64]
+		__attribute__((aligned(ARCH_DMA_MINALIGN)));
 	unsigned char		status;						/* SCSI Status			 */
 	unsigned char		target;						/* Target ID				 */
 	unsigned char		lun;							/* Target LUN        */
diff --git a/include/sdhci.h b/include/sdhci.h
index 800f9d9c07..9d37183243 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -216,6 +216,9 @@
  */
 #define SDHCI_QUIRK_32BIT_DMA_ADDR	(1 << 0)
 #define SDHCI_QUIRK_REG32_RW		(1 << 1)
+#define SDHCI_QUIRK_BROKEN_R1B		(1 << 2)
+#define SDHCI_QUIRK_NO_HISPD_BIT	(1 << 3)
+#define SDHCI_QUIRK_BROKEN_VOLTAGE	(1 << 4)
 
 /* to make gcc happy */
 struct sdhci_host;
@@ -240,10 +243,14 @@ struct sdhci_host {
 	char *name;
 	void *ioaddr;
 	unsigned int quirks;
+	unsigned int host_caps;
 	unsigned int version;
 	unsigned int clock;
 	struct mmc *mmc;
 	const struct sdhci_ops *ops;
+
+	void (*set_control_reg)(struct sdhci_host *host);
+	uint	voltages;
 };
 
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
diff --git a/include/tegra-kbc.h b/include/tegra-kbc.h
new file mode 100644
index 0000000000..f331c79c9d
--- /dev/null
+++ b/include/tegra-kbc.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __include_tegra_kbc_h__
+#define __include_tegra_kbc_h__
+
+#include <common.h>
+
+#define KEY_IS_MODIFIER(key) ((key) >= KEY_FIRST_MODIFIER)
+
+struct kbc_tegra {
+	u32 control;
+	u32 interrupt;
+	u32 row_cfg[4];
+	u32 col_cfg[3];
+	u32 timeout_dly;
+	u32 init_dly;
+	u32 rpt_dly;
+	u32 kp_ent[2];
+	u32 row_mask[16];
+};
+
+#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+extern int overwrite_console(void);
+#define OVERWRITE_CONSOLE overwrite_console()
+#else
+#define OVERWRITE_CONSOLE 0
+#endif /* CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE */
+
+#endif /* __include_tegra_kbc_h__ */
diff --git a/include/tps6586x.h b/include/tps6586x.h
new file mode 100644
index 0000000000..ab880823a3
--- /dev/null
+++ b/include/tps6586x.h
@@ -0,0 +1,68 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __H_
+#define _TPS6586X_H_
+
+enum {
+	/* SM0-2 PWM/PFM Mode Selection */
+	TPS6586X_PWM_SM0	= 1 << 0,
+	TPS6586X_PWM_SM1	= 1 << 1,
+	TPS6586X_PWM_SM2	= 1 << 2,
+};
+
+/**
+ * Enable PWM mode for selected SM0-2
+ *
+ * @param mask	Mask of synchronous converter to enable (TPS6586X_PWM_...)
+ * @return 0 if ok, -1 on error
+ */
+int tps6586x_set_pwm_mode(int mask);
+
+/**
+ * Adjust SM0 and SM1 voltages to the given targets in incremental steps.
+ *
+ * @param sm0_target	Target voltage for SM0 in 25mW units, 0=725mV, 31=1.5V
+ * @param sm1_target	Target voltage for SM1 in 25mW units, 0=725mV, 31=1.5V
+ * @param step		Amount to change voltage in each step, in 25mW units
+ * @param rate		Slew ratein mV/us: 0=instantly, 1=0.11, 2=0.22,
+ *			3=0.44, 4=0.88, 5=1.76, 6=3.52, 7=7.04
+ * @param min_sm0_over_sm1	Minimum amount by which sm0 must exceed sm1.
+ *			If this condition is not met, no adjustment will be
+ *			done and an error will be reported. Use -1 to skip
+ *			this check.
+ * @return 0 if ok, -1 on error
+ */
+int tps6586x_adjust_sm0_sm1(int sm0_target, int sm1_target, int step, int rate,
+			    int min_sm0_over_sm1);
+
+/**
+ * Set up the TPS6586X I2C bus number. This will be used for all operations
+ * on the device. This function must be called before using other functions.
+ *
+ * @param bus	I2C bus number containing the TPS6586X chip
+ * @return 0 (always succeeds)
+ */
+int tps6586x_init(int bus);
+
+#endif	/* _TPS6586X_H_ */
diff --git a/include/twl6035.h b/include/twl6035.h
new file mode 100644
index 0000000000..e21ddbaf22
--- /dev/null
+++ b/include/twl6035.h
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+/* I2C chip addresses */
+#define TWL6035_CHIP_ADDR	0x48
+
+/* 0x1XY translates to page 1, register address 0xXY */
+#define LDO9_CTRL		0x60
+#define LDO9_VOLTAGE		0x61
+
+/* Bit field definitions for LDOx_CTRL */
+#define LDO_ON			(1 << 4)
+#define LDO_MODE_SLEEP		(1 << 2)
+#define LDO_MODE_ACTIVE		(1 << 0)
+
+int twl6035_i2c_write_u8(u8 chip_no, u8 val, u8 reg);
+int twl6035_i2c_read_u8(u8 chip_no, u8 *val, u8 reg);
+void twl6035_init_settings(void);
+void twl6035_mmc1_poweron_ldo(void);
diff --git a/include/u-boot/md5.h b/include/u-boot/md5.h
index 08924cce3c..e09c16a6e3 100644
--- a/include/u-boot/md5.h
+++ b/include/u-boot/md5.h
@@ -11,7 +11,10 @@
 struct MD5Context {
 	__u32 buf[4];
 	__u32 bits[2];
-	unsigned char in[64];
+	union {
+		unsigned char in[64];
+		__u32 in32[16];
+	};
 };
 
 /*
diff --git a/include/u-boot/zlib.h b/include/u-boot/zlib.h
index fb2708186d..fbb08a3287 100644
--- a/include/u-boot/zlib.h
+++ b/include/u-boot/zlib.h
@@ -691,6 +691,9 @@ ZEXTERN int ZEXPORT inflateInit2_ OF((z_streamp strm, int  windowBits,
 	struct internal_state {int dummy;}; /* hack for buggy compilers */
 #endif
 
+extern void *gzalloc(void *, unsigned, unsigned);
+extern void gzfree(void *, void *, unsigned);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/include/ubi_uboot.h b/include/ubi_uboot.h
index 69006e250a..5ccd1130ea 100644
--- a/include/ubi_uboot.h
+++ b/include/ubi_uboot.h
@@ -39,7 +39,7 @@ do {									\
 
 /* configurable */
 #define CONFIG_MTD_UBI_WL_THRESHOLD	4096
-#define CONFIG_MTD_UBI_BEB_RESERVE	1
+#define CONFIG_MTD_UBI_BEB_RESERVE	6
 #define UBI_IO_DEBUG			0
 
 /* debug options (Linux: drivers/mtd/ubi/Kconfig.debug) */
@@ -57,10 +57,6 @@ do {									\
 #define put_device(...)
 #define ubi_sysfs_init(...)		0
 #define ubi_sysfs_close(...)		do { } while (0)
-static inline int is_power_of_2(unsigned long n)
-{
-	return (n != 0 && ((n & (n - 1)) == 0));
-}
 
 /* FIXME */
 #define MKDEV(...)			0
diff --git a/include/usb.h b/include/usb.h
index 48e4bcda54..46db5c29a2 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -109,7 +109,9 @@ struct usb_device {
 	int epmaxpacketout[16];		/* OUTput endpoint specific maximums */
 
 	int configno;			/* selected config number */
-	struct usb_device_descriptor descriptor; /* Device Descriptor */
+	/* Device Descriptor */
+	struct usb_device_descriptor descriptor
+		__attribute__((aligned(ARCH_DMA_MINALIGN)));
 	struct usb_config config; /* config descriptor */
 
 	int have_langid;		/* whether string_langid is valid yet */
@@ -139,7 +141,8 @@ struct usb_device {
 	defined(CONFIG_USB_SL811HS) || defined(CONFIG_USB_ISP116X_HCD) || \
 	defined(CONFIG_USB_R8A66597_HCD) || defined(CONFIG_USB_DAVINCI) || \
 	defined(CONFIG_USB_OMAP3) || defined(CONFIG_USB_DA8XX) || \
-	defined(CONFIG_USB_BLACKFIN) || defined(CONFIG_USB_AM35X)
+	defined(CONFIG_USB_BLACKFIN) || defined(CONFIG_USB_AM35X) || \
+	defined(CONFIG_USB_RDA)
 
 int usb_lowlevel_init(void);
 int usb_lowlevel_stop(void);
diff --git a/include/usb/lin_gadget_compat.h b/include/usb/lin_gadget_compat.h
index fce3be7e80..5bdcb8d797 100644
--- a/include/usb/lin_gadget_compat.h
+++ b/include/usb/lin_gadget_compat.h
@@ -23,6 +23,8 @@
 #ifndef __LIN_COMPAT_H__
 #define __LIN_COMPAT_H__
 
+#include <linux/compat.h>
+
 /* common */
 #define spin_lock_init(...)
 #define spin_lock(...)
@@ -36,26 +38,31 @@
 #define mutex_lock(...)
 #define mutex_unlock(...)
 
-#define WARN_ON(x) if (x) {printf("WARNING in %s line %d\n" \
-				  , __FILE__, __LINE__); }
-
-#define KERN_WARNING
-#define KERN_ERR
-#define KERN_NOTICE
-#define KERN_DEBUG
-
 #define GFP_KERNEL	0
 
 #define IRQ_HANDLED	1
 
 #define ENOTSUPP	524	/* Operation is not supported */
 
-#define kmalloc(size, type) memalign(CONFIG_SYS_CACHELINE_SIZE, size)
-#define kfree(addr) free(addr)
-#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); })
+#define BITS_PER_BYTE				8
+#define BITS_TO_LONGS(nr) \
+	DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
+#define DECLARE_BITMAP(name, bits) \
+	unsigned long name[BITS_TO_LONGS(bits)]
+
+#define small_const_nbits(nbits) \
+	(__builtin_constant_p(nbits) && (nbits) <= BITS_PER_LONG)
+
+static inline void bitmap_zero(unsigned long *dst, int nbits)
+{
+	if (small_const_nbits(nbits))
+		*dst = 0UL;
+	else {
+		int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long);
+		memset(dst, 0, len);
+	}
+}
 
-#define __iomem
-#define min_t min
 #define dma_cache_maint(addr, size, mode) cache_flush()
 void cache_flush(void);
 
diff --git a/include/usb/musb_dma.h b/include/usb/musb_dma.h
new file mode 100644
index 0000000000..4d61df2249
--- /dev/null
+++ b/include/usb/musb_dma.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __MUSB_DMA_H__
+#define __MUSB_DMA_H__
+
+
+int configure_dma_channel(u32 epnum, u16 packet_sz, u8 mode,
+                                u32 dma_addr, u32 len, int tx);
+int wait_dma_xfer_done(void);
+#endif /* __MUSB_DMA_H__ */
diff --git a/include/usb/musb_udc.h b/include/usb/musb_udc.h
index be808fd516..c56d958f65 100644
--- a/include/usb/musb_udc.h
+++ b/include/usb/musb_udc.h
@@ -35,9 +35,17 @@ void udc_enable(struct usb_device_instance *device);
 void udc_disable(void);
 void udc_startup_events(struct usb_device_instance *device);
 int udc_init(void);
+void udc_power_on(void);
+void udc_power_off(void);
+int udc_soft_init(void);
+void udc_hot_startup(struct usb_device_instance *device);
+unsigned int udc_chars_in_rxfifo(unsigned int ep);
+void poll_rx_ep(unsigned int ep);
+int udc_is_initialized(void);
+
 
 /* usbtty */
-#ifdef CONFIG_USB_TTY
+//#ifdef CONFIG_USB_TTY
 
 #define EP0_MAX_PACKET_SIZE	64 /* MUSB_EP0_FIFOSIZE */
 #define UDC_INT_ENDPOINT	1
@@ -47,7 +55,14 @@ int udc_init(void);
 #define UDC_IN_ENDPOINT		3
 #define UDC_IN_PACKET_SIZE	64
 #define UDC_BULK_PACKET_SIZE	64
+#define UDC_BULK_HS_PACKET_SIZE	512
+
+#ifdef CONFIG_USB_ACM_TWO_CHANS
+#define UDC_INT_ENDPOINT2	4
+#define UDC_OUT_ENDPOINT2	3
+#define UDC_IN_ENDPOINT2	2
+#endif
 
-#endif /* CONFIG_USB_TTY */
+//#endif /* CONFIG_USB_TTY */
 
 #endif /* __MUSB_UDC_H__ */
diff --git a/include/usb/s3c_udc.h b/include/usb/s3c_udc.h
index 6c973b6995..6a8fd44244 100644
--- a/include/usb/s3c_udc.h
+++ b/include/usb/s3c_udc.h
@@ -24,6 +24,7 @@
 
 #include <asm/errno.h>
 #include <linux/usb/ch9.h>
+#include <usbdescriptors.h>
 #include <linux/usb/gadget.h>
 #include <linux/list.h>
 #include <usb/lin_gadget_compat.h>
@@ -111,54 +112,6 @@ extern struct s3c_udc *the_controller;
 #define ep_index(EP) ((EP)->bEndpointAddress&0xF)
 #define ep_maxpacket(EP) ((EP)->ep.maxpacket)
 
-/*-------------------------------------------------------------------------*/
-/* #define DEBUG_UDC */
-#ifdef DEBUG_UDC
-#define DBG(stuff...)		printf("udc: " stuff)
-#else
-#define DBG(stuff...)		do {} while (0)
-#endif
-
-#ifdef DEBUG_S3C_UDC_SETUP
-#define DEBUG_SETUP(fmt, args...) printk(fmt, ##args)
-#else
-#define DEBUG_SETUP(fmt, args...) do {} while (0)
-#endif
-
-#ifdef DEBUG_S3C_UDC_EP0
-#define DEBUG_EP0(fmt, args...) printk(fmt, ##args)
-#else
-#define DEBUG_EP0(fmt, args...) do {} while (0)
-#endif
-
-#ifdef DEBUG_S3C_UDC_ISR
-#define DEBUG_ISR	1
-#else
-#define DEBUG_ISR	0
-#endif
-
-#ifdef DEBUG_S3C_UDC_OUT_EP
-#define DEBUG_OUT_EP(fmt, args...) printk(fmt, ##args)
-#else
-#define DEBUG_OUT_EP(fmt, args...) do {} while (0)
-#endif
-
-#ifdef DEBUG_S3C_UDC_IN_EP
-#define DEBUG_IN_EP	1
-#else
-#define DEBUG_IN_EP	0
-#endif
-
-#if defined(DEBUG_S3C_UDC_SETUP) || defined(DEBUG_S3C_UDC_EP0) || \
-	defined(DEBUG_S3C_UDC_ISR) || defined(DEBUG_S3C_UDC_OUT_EP) || \
-	defined(DEBUG_S3C_UDC_IN_EP) || defined(DEBUG_S3C_UDC)
-#define DEBUG
-#endif
-
-#define ERR(stuff...)		printf("ERR udc: " stuff)
-#define WARN(stuff...)		printf("WARNING udc: " stuff)
-#define INFO(stuff...)		printf("INFO udc: " stuff)
-
 extern void otg_phy_init(struct s3c_udc *dev);
 extern void otg_phy_off(struct s3c_udc *dev);
 
diff --git a/include/usb/usbserial.h b/include/usb/usbserial.h
new file mode 100644
index 0000000000..7484f3d426
--- /dev/null
+++ b/include/usb/usbserial.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2003
+ * Gerry Hamel, geh@ti.com, Texas Instruments
+ *
+ * (C) Copyright 2006
+ * Bryan O'Donoghue, bodonoghue@codehermit.ie, CodeHermit
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
+ *
+ */
+
+#ifndef __USB_SERIAL_H__
+#define __USB_SERIAL_H__
+
+#define USB_ACM_CHAN_0	0
+#define USB_ACM_CHAN_1	1
+
+int usbser_tstc (int chan);
+int usbser_getc (int chan);
+void usbser_putc (int chan, const char c);
+int usbser_read(int chan, unsigned char *_buf, unsigned int len);
+int usbser_write(int chan, const unsigned char *_buf, unsigned int len);
+int drv_usbser_init (void);
+
+#endif
diff --git a/include/usbdescriptors.h b/include/usbdescriptors.h
index de1069f0ea..6f9d41d376 100644
--- a/include/usbdescriptors.h
+++ b/include/usbdescriptors.h
@@ -213,6 +213,18 @@ struct usb_interface_descriptor {
 	u8 iInterface;
 } __attribute__ ((packed));
 
+/* usb interface association descriptor (IAD) */
+struct usb_function_descriptor {
+	u8 bLength;
+	u8 bDescriptorType;	/* 0x0B */
+	u8 bFirstInterface;
+	u8 bInterfaceCount;
+	u8 bFunctionClass;
+	u8 bFunctionSubClass;
+	u8 bFunctionProtocol;
+	u8 iFunction;
+} __attribute__ ((packed));
+
 struct usb_configuration_descriptor {
 	u8 bLength;
 	u8 bDescriptorType;	/* 0x2 */
diff --git a/include/usbdevice.h b/include/usbdevice.h
index 3edaf8bcc2..2243356993 100644
--- a/include/usbdevice.h
+++ b/include/usbdevice.h
@@ -33,7 +33,7 @@
 
 #include <common.h>
 #include "usbdescriptors.h"
-
+#include "pdl.h"
 
 #define MAX_URBS_QUEUED 5
 
@@ -474,8 +474,8 @@ typedef struct urb_link {
  * allocated for receiving data for an endpoint and used to call the
  * function driver to inform it that data has arrived.
  */
-
-#define URB_BUF_SIZE 128 /* in linux we'd malloc this, but in u-boot we prefer static data */
+/* change to 256 for high speed, the buffer is 2bytes width yingchun*/
+#define URB_BUF_SIZE 512 /* in linux we'd malloc this, but in u-boot we prefer static data */
 struct urb {
 
 	struct usb_endpoint_instance *endpoint;
@@ -488,11 +488,13 @@ struct urb {
 	u8* buffer;
 	unsigned int buffer_length;
 	unsigned int actual_length;
+	unsigned int req_length;
+	int use_dma;
 
 	urb_send_status_t status;
 	int data;
 
-	u16 buffer_data[URB_BUF_SIZE];	/* data received (OUT) or being sent (IN) */
+	u8  *buffer_data;	/* data received (OUT) or being sent (IN) */
 };
 
 /* Endpoint configuration
@@ -643,6 +645,10 @@ struct urb *first_urb_detached (urb_link * hd);
 void urb_append (urb_link * hd, struct urb *urb);
 
 struct urb *usbd_alloc_urb (struct usb_device_instance *device, struct usb_endpoint_instance *endpoint);
+int usbd_init_urb (struct urb *urb, struct usb_device_instance *device,
+	    struct usb_endpoint_instance *endpoint, u8 *buf, unsigned int len);
+int usbd_setup_urb(struct urb *urb, u8 *buf, u32 len, int dma);
+void usbd_free_urb(struct urb *urb);
 void	    usbd_dealloc_urb (struct urb *urb);
 
 /*
@@ -687,6 +693,7 @@ void usbd_tx_complete (struct usb_endpoint_instance *endpoint);
 #ifdef DEBUG
 static inline void print_urb(struct urb *u)
 {
+	if (!pdl_dbg_usb_ep0) return;
 	serial_printf("urb %p\n", (u));
 	serial_printf("\tendpoint %p\n", u->endpoint);
 	serial_printf("\tdevice %p\n", u->device);
@@ -699,6 +706,7 @@ static inline void print_urb(struct urb *u)
 
 static inline void print_usb_device_request(struct usb_device_request *r)
 {
+	if (!pdl_dbg_usb_ep0) return;
 	serial_printf("usb request\n");
 	serial_printf("\tbmRequestType 0x%2.2x\n", r->bmRequestType);
 	if ((r->bmRequestType & USB_REQ_DIRECTION_MASK) == 0)
diff --git a/include/version.h b/include/version.h
index c908bd3013..9f3fbf3de0 100644
--- a/include/version.h
+++ b/include/version.h
@@ -24,11 +24,11 @@
 #ifndef	__VERSION_H__
 #define	__VERSION_H__
 
-#include <timestamp.h>
-
-#ifndef DO_DEPS_ONLY
-#include "generated/version_autogenerated.h"
-#endif
+// Only include:
+//	#include "generated/version_autogenerated.h"
+// in files that directly use the version macros:
+// 	PLAIN_VERSION, U_BOOT_VERSION, CC_VERSION_STRING, LD_VERSION_STRING
+//	or U_BOOT_VERSION_STRING
 
 #ifndef CONFIG_IDENT_STRING
 #define CONFIG_IDENT_STRING ""
diff --git a/lib/Makefile b/lib/Makefile
index a0fec60a13..c6d3f639fe 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -28,6 +28,7 @@ LIB	= $(obj)libgeneric.o
 ifndef CONFIG_SPL_BUILD
 COBJS-$(CONFIG_ADDR_MAP) += addr_map.o
 COBJS-$(CONFIG_BCH) += bch.o
+COBJS-$(CONFIG_AES) += aes.o
 COBJS-$(CONFIG_BZIP2) += bzlib.o
 COBJS-$(CONFIG_BZIP2) += bzlib_crctable.o
 COBJS-$(CONFIG_BZIP2) += bzlib_decompress.o
@@ -58,6 +59,7 @@ endif
 
 ifdef CONFIG_SPL_BUILD
 COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o
+COBJS-$(CONFIG_SPL_IMAGE_SUPPORT) += crc32.o
 endif
 COBJS-y += ctype.o
 COBJS-y += div64.o
diff --git a/lib/aes.c b/lib/aes.c
new file mode 100644
index 0000000000..7da9edb7e6
--- /dev/null
+++ b/lib/aes.c
@@ -0,0 +1,598 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2011 NVIDIA Corporation www.nvidia.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * advanced encryption standard
+ * author: karl malbrain, malbrain@yahoo.com
+ *
+ * This work, including the source code, documentation
+ * and related data, is placed into the public domain.
+ *
+ * The orginal author is Karl Malbrain.
+ *
+ * THIS SOFTWARE IS PROVIDED AS-IS WITHOUT WARRANTY
+ * OF ANY KIND, NOT EVEN THE IMPLIED WARRANTY OF
+ * MERCHANTABILITY. THE AUTHOR OF THIS SOFTWARE,
+ * ASSUMES _NO_ RESPONSIBILITY FOR ANY CONSEQUENCE
+ * RESULTING FROM THE USE, MODIFICATION, OR
+ * REDISTRIBUTION OF THIS SOFTWARE.
+*/
+
+#include <common.h>
+#include "aes.h"
+
+/* forward s-box */
+static const u8 sbox[256] = {
+	0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5,
+	0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76,
+	0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0,
+	0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0,
+	0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc,
+	0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15,
+	0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a,
+	0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75,
+	0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0,
+	0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84,
+	0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b,
+	0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf,
+	0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85,
+	0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8,
+	0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5,
+	0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2,
+	0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17,
+	0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73,
+	0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88,
+	0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb,
+	0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c,
+	0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79,
+	0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9,
+	0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08,
+	0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6,
+	0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a,
+	0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e,
+	0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e,
+	0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94,
+	0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf,
+	0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68,
+	0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
+};
+
+/* inverse s-box */
+static const u8 inv_sbox[256] = {
+	0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38,
+	0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb,
+	0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87,
+	0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb,
+	0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d,
+	0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e,
+	0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2,
+	0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25,
+	0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16,
+	0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92,
+	0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda,
+	0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84,
+	0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a,
+	0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06,
+	0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02,
+	0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b,
+	0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea,
+	0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73,
+	0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85,
+	0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e,
+	0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89,
+	0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b,
+	0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20,
+	0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4,
+	0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31,
+	0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f,
+	0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d,
+	0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef,
+	0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0,
+	0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61,
+	0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26,
+	0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d
+};
+
+/* combined Xtimes2[Sbox[]] */
+static const u8 x2_sbox[256] = {
+	0xc6, 0xf8, 0xee, 0xf6, 0xff, 0xd6, 0xde, 0x91,
+	0x60, 0x02, 0xce, 0x56, 0xe7, 0xb5, 0x4d, 0xec,
+	0x8f, 0x1f, 0x89, 0xfa, 0xef, 0xb2, 0x8e, 0xfb,
+	0x41, 0xb3, 0x5f, 0x45, 0x23, 0x53, 0xe4, 0x9b,
+	0x75, 0xe1, 0x3d, 0x4c, 0x6c, 0x7e, 0xf5, 0x83,
+	0x68, 0x51, 0xd1, 0xf9, 0xe2, 0xab, 0x62, 0x2a,
+	0x08, 0x95, 0x46, 0x9d, 0x30, 0x37, 0x0a, 0x2f,
+	0x0e, 0x24, 0x1b, 0xdf, 0xcd, 0x4e, 0x7f, 0xea,
+	0x12, 0x1d, 0x58, 0x34, 0x36, 0xdc, 0xb4, 0x5b,
+	0xa4, 0x76, 0xb7, 0x7d, 0x52, 0xdd, 0x5e, 0x13,
+	0xa6, 0xb9, 0x00, 0xc1, 0x40, 0xe3, 0x79, 0xb6,
+	0xd4, 0x8d, 0x67, 0x72, 0x94, 0x98, 0xb0, 0x85,
+	0xbb, 0xc5, 0x4f, 0xed, 0x86, 0x9a, 0x66, 0x11,
+	0x8a, 0xe9, 0x04, 0xfe, 0xa0, 0x78, 0x25, 0x4b,
+	0xa2, 0x5d, 0x80, 0x05, 0x3f, 0x21, 0x70, 0xf1,
+	0x63, 0x77, 0xaf, 0x42, 0x20, 0xe5, 0xfd, 0xbf,
+	0x81, 0x18, 0x26, 0xc3, 0xbe, 0x35, 0x88, 0x2e,
+	0x93, 0x55, 0xfc, 0x7a, 0xc8, 0xba, 0x32, 0xe6,
+	0xc0, 0x19, 0x9e, 0xa3, 0x44, 0x54, 0x3b, 0x0b,
+	0x8c, 0xc7, 0x6b, 0x28, 0xa7, 0xbc, 0x16, 0xad,
+	0xdb, 0x64, 0x74, 0x14, 0x92, 0x0c, 0x48, 0xb8,
+	0x9f, 0xbd, 0x43, 0xc4, 0x39, 0x31, 0xd3, 0xf2,
+	0xd5, 0x8b, 0x6e, 0xda, 0x01, 0xb1, 0x9c, 0x49,
+	0xd8, 0xac, 0xf3, 0xcf, 0xca, 0xf4, 0x47, 0x10,
+	0x6f, 0xf0, 0x4a, 0x5c, 0x38, 0x57, 0x73, 0x97,
+	0xcb, 0xa1, 0xe8, 0x3e, 0x96, 0x61, 0x0d, 0x0f,
+	0xe0, 0x7c, 0x71, 0xcc, 0x90, 0x06, 0xf7, 0x1c,
+	0xc2, 0x6a, 0xae, 0x69, 0x17, 0x99, 0x3a, 0x27,
+	0xd9, 0xeb, 0x2b, 0x22, 0xd2, 0xa9, 0x07, 0x33,
+	0x2d, 0x3c, 0x15, 0xc9, 0x87, 0xaa, 0x50, 0xa5,
+	0x03, 0x59, 0x09, 0x1a, 0x65, 0xd7, 0x84, 0xd0,
+	0x82, 0x29, 0x5a, 0x1e, 0x7b, 0xa8, 0x6d, 0x2c
+};
+
+/* combined Xtimes3[Sbox[]] */
+static const u8 x3_sbox[256] = {
+	0xa5, 0x84, 0x99, 0x8d, 0x0d, 0xbd, 0xb1, 0x54,
+	0x50, 0x03, 0xa9, 0x7d, 0x19, 0x62, 0xe6, 0x9a,
+	0x45, 0x9d, 0x40, 0x87, 0x15, 0xeb, 0xc9, 0x0b,
+	0xec, 0x67, 0xfd, 0xea, 0xbf, 0xf7, 0x96, 0x5b,
+	0xc2, 0x1c, 0xae, 0x6a, 0x5a, 0x41, 0x02, 0x4f,
+	0x5c, 0xf4, 0x34, 0x08, 0x93, 0x73, 0x53, 0x3f,
+	0x0c, 0x52, 0x65, 0x5e, 0x28, 0xa1, 0x0f, 0xb5,
+	0x09, 0x36, 0x9b, 0x3d, 0x26, 0x69, 0xcd, 0x9f,
+	0x1b, 0x9e, 0x74, 0x2e, 0x2d, 0xb2, 0xee, 0xfb,
+	0xf6, 0x4d, 0x61, 0xce, 0x7b, 0x3e, 0x71, 0x97,
+	0xf5, 0x68, 0x00, 0x2c, 0x60, 0x1f, 0xc8, 0xed,
+	0xbe, 0x46, 0xd9, 0x4b, 0xde, 0xd4, 0xe8, 0x4a,
+	0x6b, 0x2a, 0xe5, 0x16, 0xc5, 0xd7, 0x55, 0x94,
+	0xcf, 0x10, 0x06, 0x81, 0xf0, 0x44, 0xba, 0xe3,
+	0xf3, 0xfe, 0xc0, 0x8a, 0xad, 0xbc, 0x48, 0x04,
+	0xdf, 0xc1, 0x75, 0x63, 0x30, 0x1a, 0x0e, 0x6d,
+	0x4c, 0x14, 0x35, 0x2f, 0xe1, 0xa2, 0xcc, 0x39,
+	0x57, 0xf2, 0x82, 0x47, 0xac, 0xe7, 0x2b, 0x95,
+	0xa0, 0x98, 0xd1, 0x7f, 0x66, 0x7e, 0xab, 0x83,
+	0xca, 0x29, 0xd3, 0x3c, 0x79, 0xe2, 0x1d, 0x76,
+	0x3b, 0x56, 0x4e, 0x1e, 0xdb, 0x0a, 0x6c, 0xe4,
+	0x5d, 0x6e, 0xef, 0xa6, 0xa8, 0xa4, 0x37, 0x8b,
+	0x32, 0x43, 0x59, 0xb7, 0x8c, 0x64, 0xd2, 0xe0,
+	0xb4, 0xfa, 0x07, 0x25, 0xaf, 0x8e, 0xe9, 0x18,
+	0xd5, 0x88, 0x6f, 0x72, 0x24, 0xf1, 0xc7, 0x51,
+	0x23, 0x7c, 0x9c, 0x21, 0xdd, 0xdc, 0x86, 0x85,
+	0x90, 0x42, 0xc4, 0xaa, 0xd8, 0x05, 0x01, 0x12,
+	0xa3, 0x5f, 0xf9, 0xd0, 0x91, 0x58, 0x27, 0xb9,
+	0x38, 0x13, 0xb3, 0x33, 0xbb, 0x70, 0x89, 0xa7,
+	0xb6, 0x22, 0x92, 0x20, 0x49, 0xff, 0x78, 0x7a,
+	0x8f, 0xf8, 0x80, 0x17, 0xda, 0x31, 0xc6, 0xb8,
+	0xc3, 0xb0, 0x77, 0x11, 0xcb, 0xfc, 0xd6, 0x3a
+};
+
+/*
+ * modular multiplication tables based on:
+ *
+ * Xtime2[x] = (x & 0x80 ? 0x1b : 0) ^ (x + x)
+ * Xtime3[x] = x^Xtime2[x];
+ */
+static const u8 x_time_9[256] = {
+	0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f,
+	0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
+	0x90, 0x99, 0x82, 0x8b, 0xb4, 0xbd, 0xa6, 0xaf,
+	0xd8, 0xd1, 0xca, 0xc3, 0xfc, 0xf5, 0xee, 0xe7,
+	0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04,
+	0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
+	0xab, 0xa2, 0xb9, 0xb0, 0x8f, 0x86, 0x9d, 0x94,
+	0xe3, 0xea, 0xf1, 0xf8, 0xc7, 0xce, 0xd5, 0xdc,
+	0x76, 0x7f, 0x64, 0x6d, 0x52, 0x5b, 0x40, 0x49,
+	0x3e, 0x37, 0x2c, 0x25, 0x1a, 0x13, 0x08, 0x01,
+	0xe6, 0xef, 0xf4, 0xfd, 0xc2, 0xcb, 0xd0, 0xd9,
+	0xae, 0xa7, 0xbc, 0xb5, 0x8a, 0x83, 0x98, 0x91,
+	0x4d, 0x44, 0x5f, 0x56, 0x69, 0x60, 0x7b, 0x72,
+	0x05, 0x0c, 0x17, 0x1e, 0x21, 0x28, 0x33, 0x3a,
+	0xdd, 0xd4, 0xcf, 0xc6, 0xf9, 0xf0, 0xeb, 0xe2,
+	0x95, 0x9c, 0x87, 0x8e, 0xb1, 0xb8, 0xa3, 0xaa,
+	0xec, 0xe5, 0xfe, 0xf7, 0xc8, 0xc1, 0xda, 0xd3,
+	0xa4, 0xad, 0xb6, 0xbf, 0x80, 0x89, 0x92, 0x9b,
+	0x7c, 0x75, 0x6e, 0x67, 0x58, 0x51, 0x4a, 0x43,
+	0x34, 0x3d, 0x26, 0x2f, 0x10, 0x19, 0x02, 0x0b,
+	0xd7, 0xde, 0xc5, 0xcc, 0xf3, 0xfa, 0xe1, 0xe8,
+	0x9f, 0x96, 0x8d, 0x84, 0xbb, 0xb2, 0xa9, 0xa0,
+	0x47, 0x4e, 0x55, 0x5c, 0x63, 0x6a, 0x71, 0x78,
+	0x0f, 0x06, 0x1d, 0x14, 0x2b, 0x22, 0x39, 0x30,
+	0x9a, 0x93, 0x88, 0x81, 0xbe, 0xb7, 0xac, 0xa5,
+	0xd2, 0xdb, 0xc0, 0xc9, 0xf6, 0xff, 0xe4, 0xed,
+	0x0a, 0x03, 0x18, 0x11, 0x2e, 0x27, 0x3c, 0x35,
+	0x42, 0x4b, 0x50, 0x59, 0x66, 0x6f, 0x74, 0x7d,
+	0xa1, 0xa8, 0xb3, 0xba, 0x85, 0x8c, 0x97, 0x9e,
+	0xe9, 0xe0, 0xfb, 0xf2, 0xcd, 0xc4, 0xdf, 0xd6,
+	0x31, 0x38, 0x23, 0x2a, 0x15, 0x1c, 0x07, 0x0e,
+	0x79, 0x70, 0x6b, 0x62, 0x5d, 0x54, 0x4f, 0x46
+};
+
+static const u8 x_time_b[256] = {
+	0x00, 0x0b, 0x16, 0x1d, 0x2c, 0x27, 0x3a, 0x31,
+	0x58, 0x53, 0x4e, 0x45, 0x74, 0x7f, 0x62, 0x69,
+	0xb0, 0xbb, 0xa6, 0xad, 0x9c, 0x97, 0x8a, 0x81,
+	0xe8, 0xe3, 0xfe, 0xf5, 0xc4, 0xcf, 0xd2, 0xd9,
+	0x7b, 0x70, 0x6d, 0x66, 0x57, 0x5c, 0x41, 0x4a,
+	0x23, 0x28, 0x35, 0x3e, 0x0f, 0x04, 0x19, 0x12,
+	0xcb, 0xc0, 0xdd, 0xd6, 0xe7, 0xec, 0xf1, 0xfa,
+	0x93, 0x98, 0x85, 0x8e, 0xbf, 0xb4, 0xa9, 0xa2,
+	0xf6, 0xfd, 0xe0, 0xeb, 0xda, 0xd1, 0xcc, 0xc7,
+	0xae, 0xa5, 0xb8, 0xb3, 0x82, 0x89, 0x94, 0x9f,
+	0x46, 0x4d, 0x50, 0x5b, 0x6a, 0x61, 0x7c, 0x77,
+	0x1e, 0x15, 0x08, 0x03, 0x32, 0x39, 0x24, 0x2f,
+	0x8d, 0x86, 0x9b, 0x90, 0xa1, 0xaa, 0xb7, 0xbc,
+	0xd5, 0xde, 0xc3, 0xc8, 0xf9, 0xf2, 0xef, 0xe4,
+	0x3d, 0x36, 0x2b, 0x20, 0x11, 0x1a, 0x07, 0x0c,
+	0x65, 0x6e, 0x73, 0x78, 0x49, 0x42, 0x5f, 0x54,
+	0xf7, 0xfc, 0xe1, 0xea, 0xdb, 0xd0, 0xcd, 0xc6,
+	0xaf, 0xa4, 0xb9, 0xb2, 0x83, 0x88, 0x95, 0x9e,
+	0x47, 0x4c, 0x51, 0x5a, 0x6b, 0x60, 0x7d, 0x76,
+	0x1f, 0x14, 0x09, 0x02, 0x33, 0x38, 0x25, 0x2e,
+	0x8c, 0x87, 0x9a, 0x91, 0xa0, 0xab, 0xb6, 0xbd,
+	0xd4, 0xdf, 0xc2, 0xc9, 0xf8, 0xf3, 0xee, 0xe5,
+	0x3c, 0x37, 0x2a, 0x21, 0x10, 0x1b, 0x06, 0x0d,
+	0x64, 0x6f, 0x72, 0x79, 0x48, 0x43, 0x5e, 0x55,
+	0x01, 0x0a, 0x17, 0x1c, 0x2d, 0x26, 0x3b, 0x30,
+	0x59, 0x52, 0x4f, 0x44, 0x75, 0x7e, 0x63, 0x68,
+	0xb1, 0xba, 0xa7, 0xac, 0x9d, 0x96, 0x8b, 0x80,
+	0xe9, 0xe2, 0xff, 0xf4, 0xc5, 0xce, 0xd3, 0xd8,
+	0x7a, 0x71, 0x6c, 0x67, 0x56, 0x5d, 0x40, 0x4b,
+	0x22, 0x29, 0x34, 0x3f, 0x0e, 0x05, 0x18, 0x13,
+	0xca, 0xc1, 0xdc, 0xd7, 0xe6, 0xed, 0xf0, 0xfb,
+	0x92, 0x99, 0x84, 0x8f, 0xbe, 0xb5, 0xa8, 0xa3
+};
+
+static const u8 x_time_d[256] = {
+	0x00, 0x0d, 0x1a, 0x17, 0x34, 0x39, 0x2e, 0x23,
+	0x68, 0x65, 0x72, 0x7f, 0x5c, 0x51, 0x46, 0x4b,
+	0xd0, 0xdd, 0xca, 0xc7, 0xe4, 0xe9, 0xfe, 0xf3,
+	0xb8, 0xb5, 0xa2, 0xaf, 0x8c, 0x81, 0x96, 0x9b,
+	0xbb, 0xb6, 0xa1, 0xac, 0x8f, 0x82, 0x95, 0x98,
+	0xd3, 0xde, 0xc9, 0xc4, 0xe7, 0xea, 0xfd, 0xf0,
+	0x6b, 0x66, 0x71, 0x7c, 0x5f, 0x52, 0x45, 0x48,
+	0x03, 0x0e, 0x19, 0x14, 0x37, 0x3a, 0x2d, 0x20,
+	0x6d, 0x60, 0x77, 0x7a, 0x59, 0x54, 0x43, 0x4e,
+	0x05, 0x08, 0x1f, 0x12, 0x31, 0x3c, 0x2b, 0x26,
+	0xbd, 0xb0, 0xa7, 0xaa, 0x89, 0x84, 0x93, 0x9e,
+	0xd5, 0xd8, 0xcf, 0xc2, 0xe1, 0xec, 0xfb, 0xf6,
+	0xd6, 0xdb, 0xcc, 0xc1, 0xe2, 0xef, 0xf8, 0xf5,
+	0xbe, 0xb3, 0xa4, 0xa9, 0x8a, 0x87, 0x90, 0x9d,
+	0x06, 0x0b, 0x1c, 0x11, 0x32, 0x3f, 0x28, 0x25,
+	0x6e, 0x63, 0x74, 0x79, 0x5a, 0x57, 0x40, 0x4d,
+	0xda, 0xd7, 0xc0, 0xcd, 0xee, 0xe3, 0xf4, 0xf9,
+	0xb2, 0xbf, 0xa8, 0xa5, 0x86, 0x8b, 0x9c, 0x91,
+	0x0a, 0x07, 0x10, 0x1d, 0x3e, 0x33, 0x24, 0x29,
+	0x62, 0x6f, 0x78, 0x75, 0x56, 0x5b, 0x4c, 0x41,
+	0x61, 0x6c, 0x7b, 0x76, 0x55, 0x58, 0x4f, 0x42,
+	0x09, 0x04, 0x13, 0x1e, 0x3d, 0x30, 0x27, 0x2a,
+	0xb1, 0xbc, 0xab, 0xa6, 0x85, 0x88, 0x9f, 0x92,
+	0xd9, 0xd4, 0xc3, 0xce, 0xed, 0xe0, 0xf7, 0xfa,
+	0xb7, 0xba, 0xad, 0xa0, 0x83, 0x8e, 0x99, 0x94,
+	0xdf, 0xd2, 0xc5, 0xc8, 0xeb, 0xe6, 0xf1, 0xfc,
+	0x67, 0x6a, 0x7d, 0x70, 0x53, 0x5e, 0x49, 0x44,
+	0x0f, 0x02, 0x15, 0x18, 0x3b, 0x36, 0x21, 0x2c,
+	0x0c, 0x01, 0x16, 0x1b, 0x38, 0x35, 0x22, 0x2f,
+	0x64, 0x69, 0x7e, 0x73, 0x50, 0x5d, 0x4a, 0x47,
+	0xdc, 0xd1, 0xc6, 0xcb, 0xe8, 0xe5, 0xf2, 0xff,
+	0xb4, 0xb9, 0xae, 0xa3, 0x80, 0x8d, 0x9a, 0x97
+};
+
+static const u8 x_time_e[256] = {
+	0x00, 0x0e, 0x1c, 0x12, 0x38, 0x36, 0x24, 0x2a,
+	0x70, 0x7e, 0x6c, 0x62, 0x48, 0x46, 0x54, 0x5a,
+	0xe0, 0xee, 0xfc, 0xf2, 0xd8, 0xd6, 0xc4, 0xca,
+	0x90, 0x9e, 0x8c, 0x82, 0xa8, 0xa6, 0xb4, 0xba,
+	0xdb, 0xd5, 0xc7, 0xc9, 0xe3, 0xed, 0xff, 0xf1,
+	0xab, 0xa5, 0xb7, 0xb9, 0x93, 0x9d, 0x8f, 0x81,
+	0x3b, 0x35, 0x27, 0x29, 0x03, 0x0d, 0x1f, 0x11,
+	0x4b, 0x45, 0x57, 0x59, 0x73, 0x7d, 0x6f, 0x61,
+	0xad, 0xa3, 0xb1, 0xbf, 0x95, 0x9b, 0x89, 0x87,
+	0xdd, 0xd3, 0xc1, 0xcf, 0xe5, 0xeb, 0xf9, 0xf7,
+	0x4d, 0x43, 0x51, 0x5f, 0x75, 0x7b, 0x69, 0x67,
+	0x3d, 0x33, 0x21, 0x2f, 0x05, 0x0b, 0x19, 0x17,
+	0x76, 0x78, 0x6a, 0x64, 0x4e, 0x40, 0x52, 0x5c,
+	0x06, 0x08, 0x1a, 0x14, 0x3e, 0x30, 0x22, 0x2c,
+	0x96, 0x98, 0x8a, 0x84, 0xae, 0xa0, 0xb2, 0xbc,
+	0xe6, 0xe8, 0xfa, 0xf4, 0xde, 0xd0, 0xc2, 0xcc,
+	0x41, 0x4f, 0x5d, 0x53, 0x79, 0x77, 0x65, 0x6b,
+	0x31, 0x3f, 0x2d, 0x23, 0x09, 0x07, 0x15, 0x1b,
+	0xa1, 0xaf, 0xbd, 0xb3, 0x99, 0x97, 0x85, 0x8b,
+	0xd1, 0xdf, 0xcd, 0xc3, 0xe9, 0xe7, 0xf5, 0xfb,
+	0x9a, 0x94, 0x86, 0x88, 0xa2, 0xac, 0xbe, 0xb0,
+	0xea, 0xe4, 0xf6, 0xf8, 0xd2, 0xdc, 0xce, 0xc0,
+	0x7a, 0x74, 0x66, 0x68, 0x42, 0x4c, 0x5e, 0x50,
+	0x0a, 0x04, 0x16, 0x18, 0x32, 0x3c, 0x2e, 0x20,
+	0xec, 0xe2, 0xf0, 0xfe, 0xd4, 0xda, 0xc8, 0xc6,
+	0x9c, 0x92, 0x80, 0x8e, 0xa4, 0xaa, 0xb8, 0xb6,
+	0x0c, 0x02, 0x10, 0x1e, 0x34, 0x3a, 0x28, 0x26,
+	0x7c, 0x72, 0x60, 0x6e, 0x44, 0x4a, 0x58, 0x56,
+	0x37, 0x39, 0x2b, 0x25, 0x0f, 0x01, 0x13, 0x1d,
+	0x47, 0x49, 0x5b, 0x55, 0x7f, 0x71, 0x63, 0x6d,
+	0xd7, 0xd9, 0xcb, 0xc5, 0xef, 0xe1, 0xf3, 0xfd,
+	0xa7, 0xa9, 0xbb, 0xb5, 0x9f, 0x91, 0x83, 0x8d
+};
+
+/*
+ * Exchanges columns in each of 4 rows
+ * row0 - unchanged, row1- shifted left 1,
+ * row2 - shifted left 2 and row3 - shifted left 3
+ */
+static void shift_rows(u8 *state)
+{
+	u8 tmp;
+
+	/* just substitute row 0 */
+	state[0] = sbox[state[0]];
+	state[4] = sbox[state[4]];
+	state[8] = sbox[state[8]];
+	state[12] = sbox[state[12]];
+
+	/* rotate row 1 */
+	tmp = sbox[state[1]];
+	state[1] = sbox[state[5]];
+	state[5] = sbox[state[9]];
+	state[9] = sbox[state[13]];
+	state[13] = tmp;
+
+	/* rotate row 2 */
+	tmp = sbox[state[2]];
+	state[2] = sbox[state[10]];
+	state[10] = tmp;
+	tmp = sbox[state[6]];
+	state[6] = sbox[state[14]];
+	state[14] = tmp;
+
+	/* rotate row 3 */
+	tmp = sbox[state[15]];
+	state[15] = sbox[state[11]];
+	state[11] = sbox[state[7]];
+	state[7] = sbox[state[3]];
+	state[3] = tmp;
+}
+
+/*
+ * restores columns in each of 4 rows
+ * row0 - unchanged, row1- shifted right 1,
+ * row2 - shifted right 2 and row3 - shifted right 3
+ */
+static void inv_shift_rows(u8 *state)
+{
+	u8 tmp;
+
+	/* restore row 0 */
+	state[0] = inv_sbox[state[0]];
+	state[4] = inv_sbox[state[4]];
+	state[8] = inv_sbox[state[8]];
+	state[12] = inv_sbox[state[12]];
+
+	/* restore row 1 */
+	tmp = inv_sbox[state[13]];
+	state[13] = inv_sbox[state[9]];
+	state[9] = inv_sbox[state[5]];
+	state[5] = inv_sbox[state[1]];
+	state[1] = tmp;
+
+	/* restore row 2 */
+	tmp = inv_sbox[state[2]];
+	state[2] = inv_sbox[state[10]];
+	state[10] = tmp;
+	tmp = inv_sbox[state[6]];
+	state[6] = inv_sbox[state[14]];
+	state[14] = tmp;
+
+	/* restore row 3 */
+	tmp = inv_sbox[state[3]];
+	state[3] = inv_sbox[state[7]];
+	state[7] = inv_sbox[state[11]];
+	state[11] = inv_sbox[state[15]];
+	state[15] = tmp;
+}
+
+/* recombine and mix each row in a column */
+static void mix_sub_columns(u8 *state)
+{
+	u8 tmp[4 * AES_STATECOLS];
+
+	/* mixing column 0 */
+	tmp[0] = x2_sbox[state[0]] ^ x3_sbox[state[5]] ^
+		 sbox[state[10]] ^ sbox[state[15]];
+	tmp[1] = sbox[state[0]] ^ x2_sbox[state[5]] ^
+		 x3_sbox[state[10]] ^ sbox[state[15]];
+	tmp[2] = sbox[state[0]] ^ sbox[state[5]] ^
+		 x2_sbox[state[10]] ^ x3_sbox[state[15]];
+	tmp[3] = x3_sbox[state[0]] ^ sbox[state[5]] ^
+		 sbox[state[10]] ^ x2_sbox[state[15]];
+
+	/* mixing column 1 */
+	tmp[4] = x2_sbox[state[4]] ^ x3_sbox[state[9]] ^
+		 sbox[state[14]] ^ sbox[state[3]];
+	tmp[5] = sbox[state[4]] ^ x2_sbox[state[9]] ^
+		 x3_sbox[state[14]] ^ sbox[state[3]];
+	tmp[6] = sbox[state[4]] ^ sbox[state[9]] ^
+		 x2_sbox[state[14]] ^ x3_sbox[state[3]];
+	tmp[7] = x3_sbox[state[4]] ^ sbox[state[9]] ^
+		 sbox[state[14]] ^ x2_sbox[state[3]];
+
+	/* mixing column 2 */
+	tmp[8] = x2_sbox[state[8]] ^ x3_sbox[state[13]] ^
+		 sbox[state[2]] ^ sbox[state[7]];
+	tmp[9] = sbox[state[8]] ^ x2_sbox[state[13]] ^
+		 x3_sbox[state[2]] ^ sbox[state[7]];
+	tmp[10] = sbox[state[8]] ^ sbox[state[13]] ^
+		  x2_sbox[state[2]] ^ x3_sbox[state[7]];
+	tmp[11] = x3_sbox[state[8]] ^ sbox[state[13]] ^
+		  sbox[state[2]] ^ x2_sbox[state[7]];
+
+	/* mixing column 3 */
+	tmp[12] = x2_sbox[state[12]] ^ x3_sbox[state[1]] ^
+		  sbox[state[6]] ^ sbox[state[11]];
+	tmp[13] = sbox[state[12]] ^ x2_sbox[state[1]] ^
+		  x3_sbox[state[6]] ^ sbox[state[11]];
+	tmp[14] = sbox[state[12]] ^ sbox[state[1]] ^
+		  x2_sbox[state[6]] ^ x3_sbox[state[11]];
+	tmp[15] = x3_sbox[state[12]] ^ sbox[state[1]] ^
+		  sbox[state[6]] ^ x2_sbox[state[11]];
+
+	memcpy(state, tmp, sizeof(tmp));
+}
+
+/* restore and un-mix each row in a column */
+static void inv_mix_sub_columns(u8 *state)
+{
+	u8 tmp[4 * AES_STATECOLS];
+	int  i;
+
+	/* restore column 0 */
+	tmp[0] = x_time_e[state[0]] ^ x_time_b[state[1]] ^
+		 x_time_d[state[2]] ^ x_time_9[state[3]];
+	tmp[5] = x_time_9[state[0]] ^ x_time_e[state[1]] ^
+		 x_time_b[state[2]] ^ x_time_d[state[3]];
+	tmp[10] = x_time_d[state[0]] ^ x_time_9[state[1]] ^
+		  x_time_e[state[2]] ^ x_time_b[state[3]];
+	tmp[15] = x_time_b[state[0]] ^ x_time_d[state[1]] ^
+		  x_time_9[state[2]] ^ x_time_e[state[3]];
+
+	/* restore column 1 */
+	tmp[4] = x_time_e[state[4]] ^ x_time_b[state[5]] ^
+		 x_time_d[state[6]] ^ x_time_9[state[7]];
+	tmp[9] = x_time_9[state[4]] ^ x_time_e[state[5]] ^
+		 x_time_b[state[6]] ^ x_time_d[state[7]];
+	tmp[14] = x_time_d[state[4]] ^ x_time_9[state[5]] ^
+		  x_time_e[state[6]] ^ x_time_b[state[7]];
+	tmp[3] = x_time_b[state[4]] ^ x_time_d[state[5]] ^
+		 x_time_9[state[6]] ^ x_time_e[state[7]];
+
+	/* restore column 2 */
+	tmp[8] = x_time_e[state[8]] ^ x_time_b[state[9]] ^
+		 x_time_d[state[10]] ^ x_time_9[state[11]];
+	tmp[13] = x_time_9[state[8]] ^ x_time_e[state[9]] ^
+		  x_time_b[state[10]] ^ x_time_d[state[11]];
+	tmp[2] = x_time_d[state[8]] ^ x_time_9[state[9]] ^
+		 x_time_e[state[10]] ^ x_time_b[state[11]];
+	tmp[7] = x_time_b[state[8]] ^ x_time_d[state[9]] ^
+		 x_time_9[state[10]] ^ x_time_e[state[11]];
+
+	/* restore column 3 */
+	tmp[12] = x_time_e[state[12]] ^ x_time_b[state[13]] ^
+		  x_time_d[state[14]] ^ x_time_9[state[15]];
+	tmp[1] = x_time_9[state[12]] ^ x_time_e[state[13]] ^
+		 x_time_b[state[14]] ^ x_time_d[state[15]];
+	tmp[6] = x_time_d[state[12]] ^ x_time_9[state[13]] ^
+		 x_time_e[state[14]] ^ x_time_b[state[15]];
+	tmp[11] = x_time_b[state[12]] ^ x_time_d[state[13]] ^
+		  x_time_9[state[14]] ^ x_time_e[state[15]];
+
+	for (i = 0; i < 4 * AES_STATECOLS; i++)
+		state[i] = inv_sbox[tmp[i]];
+}
+
+/*
+ * encrypt/decrypt columns of the key
+ * n.b. you can replace this with byte-wise xor if you wish.
+ */
+static void add_round_key(u32 *state, u32 *key)
+{
+	int idx;
+
+	for (idx = 0; idx < 4; idx++)
+		state[idx] ^= key[idx];
+}
+
+static u8 rcon[11] = {
+	0x00, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36
+};
+
+/* produce AES_STATECOLS bytes for each round */
+void aes_expand_key(u8 *key, u8 *expkey)
+{
+	u8 tmp0, tmp1, tmp2, tmp3, tmp4;
+	u32 idx;
+
+	memcpy(expkey, key, AES_KEYCOLS * 4);
+
+	for (idx = AES_KEYCOLS; idx < AES_STATECOLS * (AES_ROUNDS + 1); idx++) {
+		tmp0 = expkey[4*idx - 4];
+		tmp1 = expkey[4*idx - 3];
+		tmp2 = expkey[4*idx - 2];
+		tmp3 = expkey[4*idx - 1];
+		if (!(idx % AES_KEYCOLS)) {
+			tmp4 = tmp3;
+			tmp3 = sbox[tmp0];
+			tmp0 = sbox[tmp1] ^ rcon[idx / AES_KEYCOLS];
+			tmp1 = sbox[tmp2];
+			tmp2 = sbox[tmp4];
+		} else if ((AES_KEYCOLS > 6) && (idx % AES_KEYCOLS == 4)) {
+			tmp0 = sbox[tmp0];
+			tmp1 = sbox[tmp1];
+			tmp2 = sbox[tmp2];
+			tmp3 = sbox[tmp3];
+		}
+
+		expkey[4*idx+0] = expkey[4*idx - 4*AES_KEYCOLS + 0] ^ tmp0;
+		expkey[4*idx+1] = expkey[4*idx - 4*AES_KEYCOLS + 1] ^ tmp1;
+		expkey[4*idx+2] = expkey[4*idx - 4*AES_KEYCOLS + 2] ^ tmp2;
+		expkey[4*idx+3] = expkey[4*idx - 4*AES_KEYCOLS + 3] ^ tmp3;
+	}
+}
+
+/* encrypt one 128 bit block */
+void aes_encrypt(u8 *in, u8 *expkey, u8 *out)
+{
+	u8 state[AES_STATECOLS * 4];
+	u32 round;
+
+	memcpy(state, in, AES_STATECOLS * 4);
+	add_round_key((u32 *)state, (u32 *)expkey);
+
+	for (round = 1; round < AES_ROUNDS + 1; round++) {
+		if (round < AES_ROUNDS)
+			mix_sub_columns(state);
+		else
+			shift_rows(state);
+
+		add_round_key((u32 *)state,
+			      (u32 *)expkey + round * AES_STATECOLS);
+	}
+
+	memcpy(out, state, sizeof(state));
+}
+
+void aes_decrypt(u8 *in, u8 *expkey, u8 *out)
+{
+	u8 state[AES_STATECOLS * 4];
+	int round;
+
+	memcpy(state, in, sizeof(state));
+
+	add_round_key((u32 *)state,
+		      (u32 *)expkey + AES_ROUNDS * AES_STATECOLS);
+	inv_shift_rows(state);
+
+	for (round = AES_ROUNDS; round--; ) {
+		add_round_key((u32 *)state,
+			      (u32 *)expkey + round * AES_STATECOLS);
+		if (round)
+			inv_mix_sub_columns(state);
+	}
+
+	memcpy(out, state, sizeof(state));
+}
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index bdec1a0d96..cc09e06c73 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -40,6 +40,9 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(NVIDIA_TEGRA20_USB, "nvidia,tegra20-ehci"),
 	COMPAT(NVIDIA_TEGRA20_I2C, "nvidia,tegra20-i2c"),
 	COMPAT(NVIDIA_TEGRA20_DVC, "nvidia,tegra20-i2c-dvc"),
+	COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),
+	COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),
+	COMPAT(NVIDIA_TEGRA20_KBC, "nvidia,tegra20-kbc"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)
@@ -133,6 +136,21 @@ int fdtdec_next_compatible(const void *blob, int node,
 	return fdt_node_offset_by_compatible(blob, node, compat_names[id]);
 }
 
+int fdtdec_next_compatible_subnode(const void *blob, int node,
+		enum fdt_compat_id id, int *depthp)
+{
+	do {
+		node = fdt_next_node(blob, node, depthp);
+	} while (*depthp > 1);
+
+	/* If this is a direct subnode, and compatible, return it */
+	if (*depthp == 1 && 0 == fdt_node_check_compatible(
+						blob, node, compat_names[id]))
+		return node;
+
+	return -FDT_ERR_NOTFOUND;
+}
+
 int fdtdec_next_alias(const void *blob, const char *name,
 		enum fdt_compat_id id, int *upto)
 {
@@ -363,6 +381,17 @@ int fdtdec_get_int_array(const void *blob, int node, const char *prop_name,
 	return err;
 }
 
+const u32 *fdtdec_locate_array(const void *blob, int node,
+			       const char *prop_name, int count)
+{
+	const u32 *cell;
+	int err;
+
+	cell = get_prop_check_min_len(blob, node, prop_name,
+				      sizeof(u32) * count, &err);
+	return err ? NULL : cell;
+}
+
 int fdtdec_get_bool(const void *blob, int node, const char *prop_name)
 {
 	const s32 *cell;
@@ -448,3 +477,27 @@ int fdtdec_setup_gpio(struct fdt_gpio_state *gpio)
 		return -1;
 	return 0;
 }
+
+int fdtdec_get_byte_array(const void *blob, int node, const char *prop_name,
+		u8 *array, int count)
+{
+	const u8 *cell;
+	int err;
+
+	cell = get_prop_check_min_len(blob, node, prop_name, count, &err);
+	if (!err)
+		memcpy(array, cell, count);
+	return err;
+}
+
+const u8 *fdtdec_locate_byte_array(const void *blob, int node,
+			     const char *prop_name, int count)
+{
+	const u8 *cell;
+	int err;
+
+	cell = get_prop_check_min_len(blob, node, prop_name, count, &err);
+	if (err)
+		return NULL;
+	return cell;
+}
diff --git a/lib/gunzip.c b/lib/gunzip.c
index 8b16b2495f..99a8ab0287 100644
--- a/lib/gunzip.c
+++ b/lib/gunzip.c
@@ -36,10 +36,7 @@
 #define RESERVED		0xe0
 #define DEFLATED		8
 
-void *zalloc(void *, unsigned, unsigned);
-void zfree(void *, void *, unsigned);
-
-void *zalloc(void *x, unsigned items, unsigned size)
+void *gzalloc(void *x, unsigned items, unsigned size)
 {
 	void *p;
 
@@ -51,7 +48,7 @@ void *zalloc(void *x, unsigned items, unsigned size)
 	return (p);
 }
 
-void zfree(void *x, void *addr, unsigned nb)
+void gzfree(void *x, void *addr, unsigned nb)
 {
 	free (addr);
 }
@@ -94,8 +91,8 @@ int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp,
 	z_stream s;
 	int r;
 
-	s.zalloc = zalloc;
-	s.zfree = zfree;
+	s.zalloc = gzalloc;
+	s.zfree = gzfree;
 
 	r = inflateInit2(&s, -MAX_WBITS);
 	if (r != Z_OK) {
diff --git a/lib/md5.c b/lib/md5.c
index 81a09e3f90..2ae4a06319 100644
--- a/lib/md5.c
+++ b/lib/md5.c
@@ -153,8 +153,8 @@ MD5Final(unsigned char digest[16], struct MD5Context *ctx)
 	byteReverse(ctx->in, 14);
 
 	/* Append length in bits and transform */
-	((__u32 *) ctx->in)[14] = ctx->bits[0];
-	((__u32 *) ctx->in)[15] = ctx->bits[1];
+	ctx->in32[14] = ctx->bits[0];
+	ctx->in32[15] = ctx->bits[1];
 
 	MD5Transform(ctx->buf, (__u32 *) ctx->in);
 	byteReverse((unsigned char *) ctx->buf, 4);
diff --git a/nand_spl/board/rda/rda8810/Makefile b/nand_spl/board/rda/rda8810/Makefile
new file mode 100644
index 0000000000..a66f12a3dc
--- /dev/null
+++ b/nand_spl/board/rda/rda8810/Makefile
@@ -0,0 +1,79 @@
+#
+# (C) Copyright 2009 DENX Software Engineering
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundatio; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+CONFIG_NAND_SPL	= y
+PAD_TO	:= 2048
+
+include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
+
+nandobj	:= $(OBJTREE)/nand_spl/
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
+	   $(LDFLAGS_FINAL)
+AFLAGS	+= -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
+CFLAGS	+= -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
+
+SOBJS	= start.o
+COBJS	= nand_boot_fsl_nfc.o spl.o
+
+SRCS	:= $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c
+SRCS	+= $(SRCTREE)/arch/arm/cpu/armv7/start.S
+SRCS	+= $(SRCTREE)/arch/arm/cpu/armv7/spl.c
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS	:= $(SOBJS) $(COBJS)
+LNDIR	:= $(nandobj)board/$(BOARDDIR)
+
+ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+
+all:	$(obj).depend $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl:	$(OBJS) $(nandobj)u-boot.lds
+	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
+		-Map $(nandobj)u-boot-spl.map \
+		-o $@
+
+$(nandobj)u-boot.lds: $(LDSCRIPT)
+	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+
+#########################################################################
+
+$(obj)%.o:	$(SRCTREE)/arch/arm/cpu/armv7/%.S
+	$(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o:	$(SRCTREE)/arch/arm/cpu/armv7/%.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+
+$(obj)%.o:	$(SRCTREE)/nand_spl/%.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/nand_spl/board/rda/rda8810/u-boot.lds b/nand_spl/board/rda/rda8810/u-boot.lds
new file mode 100644
index 0000000000..8bbc3c92be
--- /dev/null
+++ b/nand_spl/board/rda/rda8810/u-boot.lds
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		start.o			(.text)
+		nand_boot_fsl_nfc.o	(.text)
+		*(.text)
+		. = 2K;
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data)
+	}
+
+	. = ALIGN(4);
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	}
+
+	.dynsym : {
+		__dynsym_start = .;
+		*(.dynsym)
+	}
+
+	_end = .;
+
+	.bss __rel_dyn_start (OVERLAY) : {
+		__bss_start = .;
+		*(.bss)
+		 . = ALIGN(4);
+		__bss_end__ = .;
+	}
+
+	/DISCARD/ : { *(.bss*) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynsym*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.hash*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}
diff --git a/nand_spl/board/rda/rdaarm926ejs/Makefile b/nand_spl/board/rda/rdaarm926ejs/Makefile
new file mode 100644
index 0000000000..736385eb32
--- /dev/null
+++ b/nand_spl/board/rda/rdaarm926ejs/Makefile
@@ -0,0 +1,79 @@
+#
+# (C) Copyright 2009 DENX Software Engineering
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundatio; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+CONFIG_NAND_SPL	= y
+PAD_TO	:= 2048
+
+include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
+
+nandobj	:= $(OBJTREE)/nand_spl/
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
+	   $(LDFLAGS_FINAL)
+AFLAGS	+= -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
+CFLAGS	+= -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
+
+SOBJS	= start.o
+COBJS	= nand_boot_fsl_nfc.o spl.o
+
+SRCS	:= $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c
+SRCS	+= $(SRCTREE)/arch/arm/cpu/arm926ejs/start.S
+SRCS	+= $(SRCTREE)/arch/arm/cpu/arm926ejs/spl.c
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS	:= $(SOBJS) $(COBJS)
+LNDIR	:= $(nandobj)board/$(BOARDDIR)
+
+ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+
+all:	$(obj).depend $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl:	$(OBJS) $(nandobj)u-boot.lds
+	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
+		-Map $(nandobj)u-boot-spl.map \
+		-o $@
+
+$(nandobj)u-boot.lds: $(LDSCRIPT)
+	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+
+#########################################################################
+
+$(obj)%.o:	$(SRCTREE)/arch/arm/cpu/arm926ejs/%.S
+	$(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o:	$(SRCTREE)/arch/arm/cpu/arm926ejs/%.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+
+$(obj)%.o:	$(SRCTREE)/nand_spl/%.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/nand_spl/board/rda/rdaarm926ejs/u-boot.lds b/nand_spl/board/rda/rdaarm926ejs/u-boot.lds
new file mode 100644
index 0000000000..8bbc3c92be
--- /dev/null
+++ b/nand_spl/board/rda/rdaarm926ejs/u-boot.lds
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		start.o			(.text)
+		nand_boot_fsl_nfc.o	(.text)
+		*(.text)
+		. = 2K;
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data)
+	}
+
+	. = ALIGN(4);
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	}
+
+	.dynsym : {
+		__dynsym_start = .;
+		*(.dynsym)
+	}
+
+	_end = .;
+
+	.bss __rel_dyn_start (OVERLAY) : {
+		__bss_start = .;
+		*(.bss)
+		 . = ALIGN(4);
+		__bss_end__ = .;
+	}
+
+	/DISCARD/ : { *(.bss*) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynsym*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.hash*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}
diff --git a/net/Makefile b/net/Makefile
index 0544f6bacd..526468718a 100644
--- a/net/Makefile
+++ b/net/Makefile
@@ -27,16 +27,22 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)libnet.o
 
+COBJS-$(CONFIG_CMD_NET)  += arp.o
 COBJS-$(CONFIG_CMD_NET)  += bootp.o
+COBJS-$(CONFIG_CMD_CDP)  += cdp.o
 COBJS-$(CONFIG_CMD_DNS)  += dns.o
 COBJS-$(CONFIG_CMD_NET)  += eth.o
+COBJS-$(CONFIG_CMD_LINK_LOCAL) += link_local.o
 COBJS-$(CONFIG_CMD_NET)  += net.o
+COBJS-$(CONFIG_BOOTP_RANDOM_DELAY) += net_rand.o
+COBJS-$(CONFIG_CMD_LINK_LOCAL) += net_rand.o
 COBJS-$(CONFIG_CMD_NFS)  += nfs.o
+COBJS-$(CONFIG_CMD_PING) += ping.o
 COBJS-$(CONFIG_CMD_RARP) += rarp.o
 COBJS-$(CONFIG_CMD_SNTP) += sntp.o
 COBJS-$(CONFIG_CMD_NET)  += tftp.o
 
-COBJS	:= $(COBJS-y)
+COBJS	:= $(sort $(COBJS-y))
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 
diff --git a/net/arp.c b/net/arp.c
new file mode 100644
index 0000000000..bac4cab5ef
--- /dev/null
+++ b/net/arp.c
@@ -0,0 +1,236 @@
+/*
+ *	Copied from Linux Monitor (LiMon) - Networking.
+ *
+ *	Copyright 1994 - 2000 Neil Russell.
+ *	(See License)
+ *	Copyright 2000 Roland Borde
+ *	Copyright 2000 Paolo Scaffardi
+ *	Copyright 2000-2002 Wolfgang Denk, wd@denx.de
+ */
+
+#include <common.h>
+
+#include "arp.h"
+
+#ifndef	CONFIG_ARP_TIMEOUT
+/* Milliseconds before trying ARP again */
+# define ARP_TIMEOUT		5000UL
+#else
+# define ARP_TIMEOUT		CONFIG_ARP_TIMEOUT
+#endif
+
+
+#ifndef	CONFIG_NET_RETRY_COUNT
+# define ARP_TIMEOUT_COUNT	5	/* # of timeouts before giving up  */
+#else
+# define ARP_TIMEOUT_COUNT	CONFIG_NET_RETRY_COUNT
+#endif
+
+IPaddr_t	NetArpWaitPacketIP;
+IPaddr_t	NetArpWaitReplyIP;
+/* MAC address of waiting packet's destination */
+uchar	       *NetArpWaitPacketMAC;
+int		NetArpWaitTxPacketSize;
+ulong		NetArpWaitTimerStart;
+int		NetArpWaitTry;
+
+uchar	       *NetArpTxPacket;	/* THE ARP transmit packet */
+uchar		NetArpPacketBuf[PKTSIZE_ALIGN + PKTALIGN];
+
+void ArpInit(void)
+{
+	/* XXX problem with bss workaround */
+	NetArpWaitPacketMAC = NULL;
+	NetArpWaitPacketIP = 0;
+	NetArpWaitReplyIP = 0;
+	NetArpWaitTxPacketSize = 0;
+	NetArpTxPacket = &NetArpPacketBuf[0] + (PKTALIGN - 1);
+	NetArpTxPacket -= (ulong)NetArpTxPacket % PKTALIGN;
+}
+
+void arp_raw_request(IPaddr_t sourceIP, const uchar *targetEther,
+	IPaddr_t targetIP)
+{
+	uchar *pkt;
+	struct arp_hdr *arp;
+	int eth_hdr_size;
+
+	debug_cond(DEBUG_DEV_PKT, "ARP broadcast %d\n", NetArpWaitTry);
+
+	pkt = NetArpTxPacket;
+
+	eth_hdr_size = NetSetEther(pkt, NetBcastAddr, PROT_ARP);
+	pkt += eth_hdr_size;
+
+	arp = (struct arp_hdr *) pkt;
+
+	arp->ar_hrd = htons(ARP_ETHER);
+	arp->ar_pro = htons(PROT_IP);
+	arp->ar_hln = ARP_HLEN;
+	arp->ar_pln = ARP_PLEN;
+	arp->ar_op = htons(ARPOP_REQUEST);
+
+	memcpy(&arp->ar_sha, NetOurEther, ARP_HLEN);	/* source ET addr */
+	NetWriteIP(&arp->ar_spa, sourceIP);		/* source IP addr */
+	memcpy(&arp->ar_tha, targetEther, ARP_HLEN);	/* target ET addr */
+	NetWriteIP(&arp->ar_tpa, targetIP);		/* target IP addr */
+
+	NetSendPacket(NetArpTxPacket, eth_hdr_size + ARP_HDR_SIZE);
+}
+
+void ArpRequest(void)
+{
+	if ((NetArpWaitPacketIP & NetOurSubnetMask) !=
+	    (NetOurIP & NetOurSubnetMask)) {
+		if (NetOurGatewayIP == 0) {
+			puts("## Warning: gatewayip needed but not set\n");
+			NetArpWaitReplyIP = NetArpWaitPacketIP;
+		} else {
+			NetArpWaitReplyIP = NetOurGatewayIP;
+		}
+	} else {
+		NetArpWaitReplyIP = NetArpWaitPacketIP;
+	}
+
+	arp_raw_request(NetOurIP, NetEtherNullAddr, NetArpWaitReplyIP);
+}
+
+void ArpTimeoutCheck(void)
+{
+	ulong t;
+
+	if (!NetArpWaitPacketIP)
+		return;
+
+	t = get_timer(0);
+
+	/* check for arp timeout */
+	if ((t - NetArpWaitTimerStart) > ARP_TIMEOUT) {
+		NetArpWaitTry++;
+
+		if (NetArpWaitTry >= ARP_TIMEOUT_COUNT) {
+			puts("\nARP Retry count exceeded; starting again\n");
+			NetArpWaitTry = 0;
+			NetStartAgain();
+		} else {
+			NetArpWaitTimerStart = t;
+			ArpRequest();
+		}
+	}
+}
+
+void ArpReceive(struct ethernet_hdr *et, struct ip_udp_hdr *ip, int len)
+{
+	struct arp_hdr *arp;
+	IPaddr_t reply_ip_addr;
+	uchar *pkt;
+	int eth_hdr_size;
+
+	/*
+	 * We have to deal with two types of ARP packets:
+	 * - REQUEST packets will be answered by sending  our
+	 *   IP address - if we know it.
+	 * - REPLY packates are expected only after we asked
+	 *   for the TFTP server's or the gateway's ethernet
+	 *   address; so if we receive such a packet, we set
+	 *   the server ethernet address
+	 */
+	debug_cond(DEBUG_NET_PKT, "Got ARP\n");
+
+	arp = (struct arp_hdr *)ip;
+	if (len < ARP_HDR_SIZE) {
+		printf("bad length %d < %d\n", len, ARP_HDR_SIZE);
+		return;
+	}
+	if (ntohs(arp->ar_hrd) != ARP_ETHER)
+		return;
+	if (ntohs(arp->ar_pro) != PROT_IP)
+		return;
+	if (arp->ar_hln != ARP_HLEN)
+		return;
+	if (arp->ar_pln != ARP_PLEN)
+		return;
+
+	if (NetOurIP == 0)
+		return;
+
+	if (NetReadIP(&arp->ar_tpa) != NetOurIP)
+		return;
+
+	switch (ntohs(arp->ar_op)) {
+	case ARPOP_REQUEST:
+		/* reply with our IP address */
+		debug_cond(DEBUG_DEV_PKT, "Got ARP REQUEST, return our IP\n");
+		pkt = (uchar *)et;
+		eth_hdr_size = net_update_ether(et, et->et_src, PROT_ARP);
+		pkt += eth_hdr_size;
+		arp->ar_op = htons(ARPOP_REPLY);
+		memcpy(&arp->ar_tha, &arp->ar_sha, ARP_HLEN);
+		NetCopyIP(&arp->ar_tpa, &arp->ar_spa);
+		memcpy(&arp->ar_sha, NetOurEther, ARP_HLEN);
+		NetCopyIP(&arp->ar_spa, &NetOurIP);
+
+#ifdef CONFIG_CMD_LINK_LOCAL
+		/*
+		 * Work-around for brain-damaged Cisco equipment with
+		 *   arp-proxy enabled.
+		 *
+		 *   If the requesting IP is not on our subnet, wait 5ms to
+		 *   reply to ARP request so that our reply will overwrite
+		 *   the arp-proxy's instead of the other way around.
+		 */
+		if ((NetReadIP(&arp->ar_tpa) & NetOurSubnetMask) !=
+		    (NetReadIP(&arp->ar_spa) & NetOurSubnetMask))
+			udelay(5000);
+#endif
+		NetSendPacket((uchar *)et, eth_hdr_size + ARP_HDR_SIZE);
+		return;
+
+	case ARPOP_REPLY:		/* arp reply */
+		/* are we waiting for a reply */
+		if (!NetArpWaitPacketIP)
+			break;
+
+#ifdef CONFIG_KEEP_SERVERADDR
+		if (NetServerIP == NetArpWaitPacketIP) {
+			char buf[20];
+			sprintf(buf, "%pM", arp->ar_sha);
+			setenv("serveraddr", buf);
+		}
+#endif
+
+		reply_ip_addr = NetReadIP(&arp->ar_spa);
+
+		/* matched waiting packet's address */
+		if (reply_ip_addr == NetArpWaitReplyIP) {
+			debug_cond(DEBUG_DEV_PKT,
+				"Got ARP REPLY, set eth addr (%pM)\n",
+				arp->ar_data);
+
+			/* save address for later use */
+			if (NetArpWaitPacketMAC != NULL)
+				memcpy(NetArpWaitPacketMAC,
+				       &arp->ar_sha, ARP_HLEN);
+
+			net_get_arp_handler()((uchar *)arp, 0, reply_ip_addr,
+				0, len);
+
+			/* set the mac address in the waiting packet's header
+			   and transmit it */
+			memcpy(((struct ethernet_hdr *)NetTxPacket)->et_dest,
+				&arp->ar_sha, ARP_HLEN);
+			NetSendPacket(NetTxPacket, NetArpWaitTxPacketSize);
+
+			/* no arp request pending now */
+			NetArpWaitPacketIP = 0;
+			NetArpWaitTxPacketSize = 0;
+			NetArpWaitPacketMAC = NULL;
+
+		}
+		return;
+	default:
+		debug("Unexpected ARP opcode 0x%x\n",
+		      ntohs(arp->ar_op));
+		return;
+	}
+}
diff --git a/net/arp.h b/net/arp.h
new file mode 100644
index 0000000000..bfd57e0105
--- /dev/null
+++ b/net/arp.h
@@ -0,0 +1,30 @@
+/*
+ *	Copied from Linux Monitor (LiMon) - Networking.
+ *
+ *	Copyright 1994 - 2000 Neil Russell.
+ *	(See License)
+ *	Copyright 2000 Roland Borde
+ *	Copyright 2000 Paolo Scaffardi
+ *	Copyright 2000-2002 Wolfgang Denk, wd@denx.de
+ */
+
+#ifndef __ARP_H__
+#define __ARP_H__
+
+#include <common.h>
+
+extern IPaddr_t	NetArpWaitPacketIP;
+/* MAC address of waiting packet's destination */
+extern uchar *NetArpWaitPacketMAC;
+extern int NetArpWaitTxPacketSize;
+extern ulong NetArpWaitTimerStart;
+extern int NetArpWaitTry;
+
+void ArpInit(void);
+void ArpRequest(void);
+void arp_raw_request(IPaddr_t sourceIP, const uchar *targetEther,
+	IPaddr_t targetIP);
+void ArpTimeoutCheck(void);
+void ArpReceive(struct ethernet_hdr *et, struct ip_udp_hdr *ip, int len);
+
+#endif /* __ARP_H__ */
diff --git a/net/bootp.c b/net/bootp.c
index 9e324769db..0f0867b1c4 100644
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -12,39 +12,36 @@
 #include <command.h>
 #include <net.h>
 #include "bootp.h"
+#include "net_rand.h"
 #include "tftp.h"
 #include "nfs.h"
 #ifdef CONFIG_STATUS_LED
 #include <status_led.h>
 #endif
-#include <linux/compiler.h>
 
-#define BOOTP_VENDOR_MAGIC	0x63825363	/* RFC1048 Magic Cookie		*/
+#define BOOTP_VENDOR_MAGIC	0x63825363	/* RFC1048 Magic Cookie */
 
 #define TIMEOUT		5000UL	/* Milliseconds before trying BOOTP again */
 #ifndef CONFIG_NET_RETRY_COUNT
-# define TIMEOUT_COUNT	5		/* # of timeouts before giving up  */
+# define TIMEOUT_COUNT	5		/* # of timeouts before giving up */
 #else
 # define TIMEOUT_COUNT	(CONFIG_NET_RETRY_COUNT)
 #endif
 
-#define PORT_BOOTPS	67		/* BOOTP server UDP port		*/
-#define PORT_BOOTPC	68		/* BOOTP client UDP port		*/
+#define PORT_BOOTPS	67		/* BOOTP server UDP port */
+#define PORT_BOOTPC	68		/* BOOTP client UDP port */
 
-#ifndef CONFIG_DHCP_MIN_EXT_LEN		/* minimal length of extension list	*/
+#ifndef CONFIG_DHCP_MIN_EXT_LEN		/* minimal length of extension list */
 #define CONFIG_DHCP_MIN_EXT_LEN 64
 #endif
 
 ulong		BootpID;
 int		BootpTry;
-#ifdef CONFIG_BOOTP_RANDOM_DELAY
-ulong		seed1, seed2;
-#endif
 
 #if defined(CONFIG_CMD_DHCP)
 dhcp_state_t dhcp_state = INIT;
-unsigned long dhcp_leasetime = 0;
-IPaddr_t NetDHCPServerIP = 0;
+unsigned long dhcp_leasetime;
+IPaddr_t NetDHCPServerIP;
 static void DhcpHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src,
 			unsigned len);
 
@@ -64,37 +61,29 @@ static char *dhcpmsg2str(int type)
 	}
 }
 #endif
-
-#if defined(CONFIG_BOOTP_VENDOREX)
-extern u8 *dhcp_vendorex_prep (u8 *e); /*rtn new e after add own opts. */
-extern u8 *dhcp_vendorex_proc (u8 *e); /*rtn next e if mine,else NULL  */
-#endif
-
 #endif
 
 static int BootpCheckPkt(uchar *pkt, unsigned dest, unsigned src, unsigned len)
 {
-	Bootp_t *bp = (Bootp_t *) pkt;
+	struct Bootp_t *bp = (struct Bootp_t *) pkt;
 	int retval = 0;
 
 	if (dest != PORT_BOOTPC || src != PORT_BOOTPS)
 		retval = -1;
-	else if (len < sizeof (Bootp_t) - OPT_SIZE)
+	else if (len < sizeof(struct Bootp_t) - OPT_FIELD_SIZE)
 		retval = -2;
 	else if (bp->bp_op != OP_BOOTREQUEST &&
-	    bp->bp_op != OP_BOOTREPLY &&
-	    bp->bp_op != DHCP_OFFER &&
-	    bp->bp_op != DHCP_ACK &&
-	    bp->bp_op != DHCP_NAK ) {
+			bp->bp_op != OP_BOOTREPLY &&
+			bp->bp_op != DHCP_OFFER &&
+			bp->bp_op != DHCP_ACK &&
+			bp->bp_op != DHCP_NAK)
 		retval = -3;
-	}
 	else if (bp->bp_htype != HWT_ETHER)
 		retval = -4;
 	else if (bp->bp_hlen != HWL_ETHER)
 		retval = -5;
-	else if (NetReadLong((ulong*)&bp->bp_id) != BootpID) {
+	else if (NetReadLong((ulong *)&bp->bp_id) != BootpID)
 		retval = -6;
-	}
 
 	debug("Filtering pkt = %d\n", retval);
 
@@ -104,19 +93,19 @@ static int BootpCheckPkt(uchar *pkt, unsigned dest, unsigned src, unsigned len)
 /*
  * Copy parameters of interest from BOOTP_REPLY/DHCP_OFFER packet
  */
-static void BootpCopyNetParams(Bootp_t *bp)
+static void BootpCopyNetParams(struct Bootp_t *bp)
 {
-	__maybe_unused IPaddr_t tmp_ip;
-
-	NetCopyIP(&NetOurIP, &bp->bp_yiaddr);
 #if !defined(CONFIG_BOOTP_SERVERIP)
+	IPaddr_t tmp_ip;
+
 	NetCopyIP(&tmp_ip, &bp->bp_siaddr);
 	if (tmp_ip != 0)
 		NetCopyIP(&NetServerIP, &bp->bp_siaddr);
-	memcpy (NetServerEther, ((Ethernet_t *)NetRxPacket)->et_src, 6);
+	memcpy(NetServerEther, ((struct ethernet_hdr *)NetRxPacket)->et_src, 6);
 #endif
+	NetCopyIP(&NetOurIP, &bp->bp_yiaddr);
 	if (strlen(bp->bp_file) > 0)
-		copy_filename (BootFile, bp->bp_file, sizeof(BootFile));
+		copy_filename(BootFile, bp->bp_file, sizeof(BootFile));
 
 	debug("Bootfile: %s\n", BootFile);
 
@@ -124,97 +113,95 @@ static void BootpCopyNetParams(Bootp_t *bp)
 	 * don't delete exising entry when BOOTP / DHCP reply does
 	 * not contain a new value
 	 */
-	if (*BootFile) {
-		setenv ("bootfile", BootFile);
-	}
+	if (*BootFile)
+		setenv("bootfile", BootFile);
 }
 
-static int truncate_sz (const char *name, int maxlen, int curlen)
+static int truncate_sz(const char *name, int maxlen, int curlen)
 {
 	if (curlen >= maxlen) {
-		printf("*** WARNING: %s is too long (%d - max: %d) - truncated\n",
-			name, curlen, maxlen);
+		printf("*** WARNING: %s is too long (%d - max: %d)"
+			" - truncated\n", name, curlen, maxlen);
 		curlen = maxlen - 1;
 	}
-	return (curlen);
+	return curlen;
 }
 
 #if !defined(CONFIG_CMD_DHCP)
 
-static void BootpVendorFieldProcess (u8 * ext)
+static void BootpVendorFieldProcess(u8 *ext)
 {
 	int size = *(ext + 1);
 
 	debug("[BOOTP] Processing extension %d... (%d bytes)\n", *ext,
-		   *(ext + 1));
+		*(ext + 1));
 
 	NetBootFileSize = 0;
 
 	switch (*ext) {
 		/* Fixed length fields */
-	case 1:			/* Subnet mask					*/
+	case 1:			/* Subnet mask */
 		if (NetOurSubnetMask == 0)
-			NetCopyIP (&NetOurSubnetMask, (IPaddr_t *) (ext + 2));
+			NetCopyIP(&NetOurSubnetMask, (IPaddr_t *) (ext + 2));
 		break;
-	case 2:			/* Time offset - Not yet supported		*/
+	case 2:			/* Time offset - Not yet supported */
 		break;
 		/* Variable length fields */
-	case 3:			/* Gateways list				*/
-		if (NetOurGatewayIP == 0) {
-			NetCopyIP (&NetOurGatewayIP, (IPaddr_t *) (ext + 2));
-		}
+	case 3:			/* Gateways list */
+		if (NetOurGatewayIP == 0)
+			NetCopyIP(&NetOurGatewayIP, (IPaddr_t *) (ext + 2));
 		break;
-	case 4:			/* Time server - Not yet supported		*/
+	case 4:			/* Time server - Not yet supported */
 		break;
-	case 5:			/* IEN-116 name server - Not yet supported	*/
+	case 5:			/* IEN-116 name server - Not yet supported */
 		break;
 	case 6:
-		if (NetOurDNSIP == 0) {
-			NetCopyIP (&NetOurDNSIP, (IPaddr_t *) (ext + 2));
-		}
+		if (NetOurDNSIP == 0)
+			NetCopyIP(&NetOurDNSIP, (IPaddr_t *) (ext + 2));
 #if defined(CONFIG_BOOTP_DNS2)
-		if ((NetOurDNS2IP == 0) && (size > 4)) {
-			NetCopyIP (&NetOurDNS2IP, (IPaddr_t *) (ext + 2 + 4));
-		}
+		if ((NetOurDNS2IP == 0) && (size > 4))
+			NetCopyIP(&NetOurDNS2IP, (IPaddr_t *) (ext + 2 + 4));
 #endif
 		break;
-	case 7:			/* Log server - Not yet supported		*/
+	case 7:			/* Log server - Not yet supported */
 		break;
-	case 8:			/* Cookie/Quote server - Not yet supported	*/
+	case 8:			/* Cookie/Quote server - Not yet supported */
 		break;
-	case 9:			/* LPR server - Not yet supported		*/
+	case 9:			/* LPR server - Not yet supported */
 		break;
-	case 10:		/* Impress server - Not yet supported		*/
+	case 10:		/* Impress server - Not yet supported */
 		break;
-	case 11:		/* RPL server - Not yet supported		*/
+	case 11:		/* RPL server - Not yet supported */
 		break;
-	case 12:		/* Host name					*/
+	case 12:		/* Host name */
 		if (NetOurHostName[0] == 0) {
-			size = truncate_sz ("Host Name", sizeof (NetOurHostName), size);
-			memcpy (&NetOurHostName, ext + 2, size);
+			size = truncate_sz("Host Name",
+				sizeof(NetOurHostName), size);
+			memcpy(&NetOurHostName, ext + 2, size);
 			NetOurHostName[size] = 0;
 		}
 		break;
-	case 13:		/* Boot file size				*/
+	case 13:		/* Boot file size */
 		if (size == 2)
-			NetBootFileSize = ntohs (*(ushort *) (ext + 2));
+			NetBootFileSize = ntohs(*(ushort *) (ext + 2));
 		else if (size == 4)
-			NetBootFileSize = ntohl (*(ulong *) (ext + 2));
+			NetBootFileSize = ntohl(*(ulong *) (ext + 2));
 		break;
-	case 14:		/* Merit dump file - Not yet supported		*/
+	case 14:		/* Merit dump file - Not yet supported */
 		break;
-	case 15:		/* Domain name - Not yet supported		*/
+	case 15:		/* Domain name - Not yet supported */
 		break;
-	case 16:		/* Swap server - Not yet supported		*/
+	case 16:		/* Swap server - Not yet supported */
 		break;
-	case 17:		/* Root path					*/
+	case 17:		/* Root path */
 		if (NetOurRootPath[0] == 0) {
-			size = truncate_sz ("Root Path", sizeof (NetOurRootPath), size);
-			memcpy (&NetOurRootPath, ext + 2, size);
+			size = truncate_sz("Root Path",
+				sizeof(NetOurRootPath), size);
+			memcpy(&NetOurRootPath, ext + 2, size);
 			NetOurRootPath[size] = 0;
 		}
 		break;
-	case 18:		/* Extension path - Not yet supported		*/
+	case 18:		/* Extension path - Not yet supported */
 		/*
 		 * This can be used to send the information of the
 		 * vendor area in another file that the client can
@@ -222,10 +209,11 @@ static void BootpVendorFieldProcess (u8 * ext)
 		 */
 		break;
 		/* IP host layer fields */
-	case 40:		/* NIS Domain name				*/
+	case 40:		/* NIS Domain name */
 		if (NetOurNISDomain[0] == 0) {
-			size = truncate_sz ("NIS Domain Name", sizeof (NetOurNISDomain), size);
-			memcpy (&NetOurNISDomain, ext + 2, size);
+			size = truncate_sz("NIS Domain Name",
+				sizeof(NetOurNISDomain), size);
+			memcpy(&NetOurNISDomain, ext + 2, size);
 			NetOurNISDomain[size] = 0;
 		}
 		break;
@@ -235,7 +223,7 @@ static void BootpVendorFieldProcess (u8 * ext)
 		break;
 #endif
 		/* Application layer fields */
-	case 43:		/* Vendor specific info - Not yet supported	*/
+	case 43:		/* Vendor specific info - Not yet supported */
 		/*
 		 * Binary information to exchange specific
 		 * product information.
@@ -245,7 +233,7 @@ static void BootpVendorFieldProcess (u8 * ext)
 	}
 }
 
-static void BootpVendorProcess (u8 * ext, int size)
+static void BootpVendorProcess(u8 *ext, int size)
 {
 	u8 *end = ext + size;
 
@@ -259,11 +247,11 @@ static void BootpVendorProcess (u8 * ext, int size)
 
 			ext += ext[1] + 2;
 			if (ext <= end)
-				BootpVendorFieldProcess (opt);
+				BootpVendorFieldProcess(opt);
 		}
 	}
 
-	debug("[BOOTP] Received fields: \n");
+	debug("[BOOTP] Received fields:\n");
 	if (NetOurSubnetMask)
 		debug("NetOurSubnetMask : %pI4\n", &NetOurSubnetMask);
 
@@ -298,27 +286,28 @@ static void
 BootpHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src,
 	     unsigned len)
 {
-	Bootp_t *bp;
+	struct Bootp_t *bp;
 
 	debug("got BOOTP packet (src=%d, dst=%d, len=%d want_len=%zu)\n",
-		src, dest, len, sizeof (Bootp_t));
+		src, dest, len, sizeof(struct Bootp_t));
 
-	bp = (Bootp_t *)pkt;
+	bp = (struct Bootp_t *)pkt;
 
-	if (BootpCheckPkt(pkt, dest, src, len)) /* Filter out pkts we don't want */
+	/* Filter out pkts we don't want */
+	if (BootpCheckPkt(pkt, dest, src, len))
 		return;
 
 	/*
 	 *	Got a good BOOTP reply.	 Copy the data into our variables.
 	 */
 #ifdef CONFIG_STATUS_LED
-	status_led_set (STATUS_LED_BOOT, STATUS_LED_OFF);
+	status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
 #endif
 
 	BootpCopyNetParams(bp);		/* Store net parameters from reply */
 
 	/* Retrieve extended information (we must parse the vendor area) */
-	if (NetReadLong((ulong*)&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC))
+	if (NetReadLong((ulong *)&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC))
 		BootpVendorProcess((uchar *)&bp->bp_vend[4], len);
 
 	NetSetTimeout(0, (thand_f *)0);
@@ -337,11 +326,16 @@ static void
 BootpTimeout(void)
 {
 	if (BootpTry >= TIMEOUT_COUNT) {
-		puts ("\nRetry count exceeded; starting again\n");
-		NetStartAgain ();
+#ifdef CONFIG_BOOTP_MAY_FAIL
+		puts("\nRetry count exceeded\n");
+		NetSetState(NETLOOP_FAIL);
+#else
+		puts("\nRetry count exceeded; starting again\n");
+		NetStartAgain();
+#endif
 	} else {
-		NetSetTimeout (TIMEOUT, BootpTimeout);
-		BootpRequest ();
+		NetSetTimeout(TIMEOUT, BootpTimeout);
+		BootpRequest();
 	}
 }
 
@@ -349,7 +343,8 @@ BootpTimeout(void)
  *	Initialize BOOTP extension fields in the request.
  */
 #if defined(CONFIG_CMD_DHCP)
-static int DhcpExtended (u8 * e, int message_type, IPaddr_t ServerID, IPaddr_t RequestedIP)
+static int DhcpExtended(u8 *e, int message_type, IPaddr_t ServerID,
+			IPaddr_t RequestedIP)
 {
 	u8 *start = e;
 	u8 *cnt;
@@ -377,11 +372,11 @@ static int DhcpExtended (u8 * e, int message_type, IPaddr_t ServerID, IPaddr_t R
 
 	*e++ = 57;		/* Maximum DHCP Message Size */
 	*e++ = 2;
-	*e++ = (576 - 312 + OPT_SIZE) >> 8;
-	*e++ = (576 - 312 + OPT_SIZE) & 0xff;
+	*e++ = (576 - 312 + OPT_FIELD_SIZE) >> 8;
+	*e++ = (576 - 312 + OPT_FIELD_SIZE) & 0xff;
 
 	if (ServerID) {
-		int tmp = ntohl (ServerID);
+		int tmp = ntohl(ServerID);
 
 		*e++ = 54;	/* ServerID */
 		*e++ = 4;
@@ -392,7 +387,7 @@ static int DhcpExtended (u8 * e, int message_type, IPaddr_t ServerID, IPaddr_t R
 	}
 
 	if (RequestedIP) {
-		int tmp = ntohl (RequestedIP);
+		int tmp = ntohl(RequestedIP);
 
 		*e++ = 50;	/* Requested IP */
 		*e++ = 4;
@@ -402,12 +397,13 @@ static int DhcpExtended (u8 * e, int message_type, IPaddr_t ServerID, IPaddr_t R
 		*e++ = tmp & 0xff;
 	}
 #if defined(CONFIG_BOOTP_SEND_HOSTNAME)
-	if ((hostname = getenv ("hostname"))) {
-		int hostnamelen = strlen (hostname);
+	hostname = getenv("hostname");
+	if (hostname) {
+		int hostnamelen = strlen(hostname);
 
 		*e++ = 12;	/* Hostname */
 		*e++ = hostnamelen;
-		memcpy (e, hostname, hostnamelen);
+		memcpy(e, hostname, hostnamelen);
 		e += hostnamelen;
 	}
 #endif
@@ -448,7 +444,8 @@ static int DhcpExtended (u8 * e, int message_type, IPaddr_t ServerID, IPaddr_t R
 #endif
 
 #if defined(CONFIG_BOOTP_VENDOREX)
-	if ((x = dhcp_vendorex_prep (e)))
+	x = dhcp_vendorex_prep(e);
+	if (x)
 		return x - start;
 #endif
 
@@ -508,9 +505,9 @@ static int DhcpExtended (u8 * e, int message_type, IPaddr_t ServerID, IPaddr_t R
 
 #else
 /*
- *	Warning: no field size check - change CONFIG_BOOTP_* at your own risk!
+ * Warning: no field size check - change CONFIG_BOOTP_* at your own risk!
  */
-static int BootpExtended (u8 * e)
+static int BootpExtended(u8 *e)
 {
 	u8 *start = e;
 
@@ -526,8 +523,8 @@ static int BootpExtended (u8 * e)
 
 	*e++ = 57;		/* Maximum DHCP Message Size */
 	*e++ = 2;
-	*e++ = (576 - 312 + OPT_SIZE) >> 16;
-	*e++ = (576 - 312 + OPT_SIZE) & 0xff;
+	*e++ = (576 - 312 + OPT_FIELD_SIZE) >> 16;
+	*e++ = (576 - 312 + OPT_FIELD_SIZE) & 0xff;
 #endif
 
 #if defined(CONFIG_BOOTP_SUBNETMASK)
@@ -584,11 +581,15 @@ static int BootpExtended (u8 * e)
 #endif
 
 void
-BootpRequest (void)
+BootpRequest(void)
 {
-	volatile uchar *pkt, *iphdr;
-	Bootp_t *bp;
-	int ext_len, pktlen, iplen;
+	uchar *pkt, *iphdr;
+	struct Bootp_t *bp;
+	int extlen, pktlen, iplen;
+	int eth_hdr_size;
+#ifdef CONFIG_BOOTP_RANDOM_DELAY
+	ulong i, rand_ms;
+#endif
 
 	bootstage_mark_name(BOOTSTAGE_ID_BOOTP_START, "bootp_start");
 #if defined(CONFIG_CMD_DHCP)
@@ -596,82 +597,40 @@ BootpRequest (void)
 #endif
 
 #ifdef CONFIG_BOOTP_RANDOM_DELAY		/* Random BOOTP delay */
-	unsigned char bi_enetaddr[6];
-	int   reg;
-	ulong tst1, tst2, sum, m_mask, m_value = 0;
-
-	if (BootpTry ==0) {
-		/* get our mac */
-		eth_getenv_enetaddr("ethaddr", bi_enetaddr);
-
-		debug("BootpRequest => Our Mac: ");
-		for (reg=0; reg<6; reg++)
-			debug("%x%c", bi_enetaddr[reg], reg==5 ? '\n' : ':');
-
-		/* Mac-Manipulation 2 get seed1 */
-		tst1=0;
-		tst2=0;
-		for (reg=2; reg<6; reg++) {
-			tst1 = tst1 << 8;
-			tst1 = tst1 | bi_enetaddr[reg];
-		}
-		for (reg=0; reg<2; reg++) {
-			tst2 = tst2 | bi_enetaddr[reg];
-			tst2 = tst2 << 8;
-		}
-
-		seed1 = tst1^tst2;
-
-		/* Mirror seed1*/
-		m_mask=0x1;
-		for (reg=1;reg<=32;reg++) {
-			m_value |= (m_mask & seed1);
-			seed1 = seed1 >> 1;
-			m_value = m_value << 1;
-		}
-		seed1 = m_value;
-		seed2 = 0xB78D0945;
-	}
-
-	/* Random Number Generator */
+	if (BootpTry == 0)
+		srand_mac();
 
-	for (reg=0;reg<=0;reg++) {
-		sum = seed1 + seed2;
-		if (sum < seed1 || sum < seed2)
-			sum++;
-		seed2 = seed1;
-		seed1 = sum;
+	if (BootpTry <= 2)	/* Start with max 1024 * 1ms */
+		rand_ms = rand() >> (22 - BootpTry);
+	else		/* After 3rd BOOTP request max 8192 * 1ms */
+		rand_ms = rand() >> 19;
 
-		if (BootpTry<=2) {	/* Start with max 1024 * 1ms */
-			sum = sum >> (22-BootpTry);
-		} else {		/*After 3rd BOOTP request max 8192 * 1ms */
-			sum = sum >> 19;
-		}
-	}
-
-	printf ("Random delay: %ld ms...\n", sum);
-	for (reg=0; reg <sum; reg++) {
+	printf("Random delay: %ld ms...\n", rand_ms);
+	for (i = 0; i < rand_ms; i++)
 		udelay(1000); /*Wait 1ms*/
-	}
+
 #endif	/* CONFIG_BOOTP_RANDOM_DELAY */
 
 	printf("BOOTP broadcast %d\n", ++BootpTry);
 	pkt = NetTxPacket;
-	memset ((void*)pkt, 0, PKTSIZE);
+	memset((void *)pkt, 0, PKTSIZE);
 
-	pkt += NetSetEther(pkt, NetBcastAddr, PROT_IP);
+	eth_hdr_size = NetSetEther(pkt, NetBcastAddr, PROT_IP);
+	pkt += eth_hdr_size;
 
 	/*
-	 * Next line results in incorrect packet size being transmitted, resulting
-	 * in errors in some DHCP servers, reporting missing bytes.  Size must be
-	 * set in packet header after extension length has been determined.
+	 * Next line results in incorrect packet size being transmitted,
+	 * resulting in errors in some DHCP servers, reporting missing bytes.
+	 * Size must be set in packet header after extension length has been
+	 * determined.
 	 * C. Hallinan, DS4.COM, Inc.
 	 */
-	/* NetSetIP(pkt, 0xFFFFFFFFL, PORT_BOOTPS, PORT_BOOTPC, sizeof (Bootp_t)); */
-	iphdr = pkt;	/* We need this later for NetSetIP() */
-	pkt += IP_HDR_SIZE;
+	/* net_set_udp_header(pkt, 0xFFFFFFFFL, PORT_BOOTPS, PORT_BOOTPC,
+		sizeof (struct Bootp_t)); */
+	iphdr = pkt;	/* We need this later for net_set_udp_header() */
+	pkt += IP_UDP_HDR_SIZE;
 
-	bp = (Bootp_t *)pkt;
+	bp = (struct Bootp_t *)pkt;
 	bp->bp_op = OP_BOOTREQUEST;
 	bp->bp_htype = HWT_ETHER;
 	bp->bp_hlen = HWL_ETHER;
@@ -681,14 +640,14 @@ BootpRequest (void)
 	NetWriteIP(&bp->bp_yiaddr, 0);
 	NetWriteIP(&bp->bp_siaddr, 0);
 	NetWriteIP(&bp->bp_giaddr, 0);
-	memcpy (bp->bp_chaddr, NetOurEther, 6);
-	copy_filename (bp->bp_file, BootFile, sizeof(bp->bp_file));
+	memcpy(bp->bp_chaddr, NetOurEther, 6);
+	copy_filename(bp->bp_file, BootFile, sizeof(bp->bp_file));
 
 	/* Request additional information from the BOOTP/DHCP server */
 #if defined(CONFIG_CMD_DHCP)
-	ext_len = DhcpExtended((u8 *)bp->bp_vend, DHCP_DISCOVER, 0, 0);
+	extlen = DhcpExtended((u8 *)bp->bp_vend, DHCP_DISCOVER, 0, 0);
 #else
-	ext_len = BootpExtended((u8 *)bp->bp_vend);
+	extlen = BootpExtended((u8 *)bp->bp_vend);
 #endif
 
 	/*
@@ -707,22 +666,22 @@ BootpRequest (void)
 	 * Calculate proper packet lengths taking into account the
 	 * variable size of the options field
 	 */
-	pktlen = ((int)(pkt-NetTxPacket)) + BOOTP_HDR_SIZE - sizeof(bp->bp_vend) + ext_len;
-	iplen = BOOTP_HDR_SIZE - sizeof(bp->bp_vend) + ext_len;
-	NetSetIP(iphdr, 0xFFFFFFFFL, PORT_BOOTPS, PORT_BOOTPC, iplen);
+	iplen = BOOTP_HDR_SIZE - OPT_FIELD_SIZE + extlen;
+	pktlen = eth_hdr_size + IP_UDP_HDR_SIZE + iplen;
+	net_set_udp_header(iphdr, 0xFFFFFFFFL, PORT_BOOTPS, PORT_BOOTPC, iplen);
 	NetSetTimeout(SELECT_TIMEOUT, BootpTimeout);
 
 #if defined(CONFIG_CMD_DHCP)
 	dhcp_state = SELECTING;
-	NetSetHandler(DhcpHandler);
+	net_set_udp_handler(DhcpHandler);
 #else
-	NetSetHandler(BootpHandler);
+	net_set_udp_handler(BootpHandler);
 #endif
 	NetSendPacket(NetTxPacket, pktlen);
 }
 
 #if defined(CONFIG_CMD_DHCP)
-static void DhcpOptionsProcess (uchar * popt, Bootp_t *bp)
+static void DhcpOptionsProcess(uchar *popt, struct Bootp_t *bp)
 {
 	uchar *end = popt + BOOTP_HDR_SIZE;
 	int oplen, size;
@@ -734,50 +693,51 @@ static void DhcpOptionsProcess (uchar * popt, Bootp_t *bp)
 		oplen = *(popt + 1);
 		switch (*popt) {
 		case 1:
-			NetCopyIP (&NetOurSubnetMask, (popt + 2));
+			NetCopyIP(&NetOurSubnetMask, (popt + 2));
 			break;
 #if defined(CONFIG_CMD_SNTP) && defined(CONFIG_BOOTP_TIMEOFFSET)
 		case 2:		/* Time offset	*/
 			to_ptr = &NetTimeOffset;
-			NetCopyLong ((ulong *)to_ptr, (ulong *)(popt + 2));
-			NetTimeOffset = ntohl (NetTimeOffset);
+			NetCopyLong((ulong *)to_ptr, (ulong *)(popt + 2));
+			NetTimeOffset = ntohl(NetTimeOffset);
 			break;
 #endif
 		case 3:
-			NetCopyIP (&NetOurGatewayIP, (popt + 2));
+			NetCopyIP(&NetOurGatewayIP, (popt + 2));
 			break;
 		case 6:
-			NetCopyIP (&NetOurDNSIP, (popt + 2));
+			NetCopyIP(&NetOurDNSIP, (popt + 2));
 #if defined(CONFIG_BOOTP_DNS2)
-			if (*(popt + 1) > 4) {
-				NetCopyIP (&NetOurDNS2IP, (popt + 2 + 4));
-			}
+			if (*(popt + 1) > 4)
+				NetCopyIP(&NetOurDNS2IP, (popt + 2 + 4));
 #endif
 			break;
 		case 12:
-			size = truncate_sz ("Host Name", sizeof (NetOurHostName), oplen);
-			memcpy (&NetOurHostName, popt + 2, size);
+			size = truncate_sz("Host Name",
+				sizeof(NetOurHostName), oplen);
+			memcpy(&NetOurHostName, popt + 2, size);
 			NetOurHostName[size] = 0;
 			break;
 		case 15:	/* Ignore Domain Name Option */
 			break;
 		case 17:
-			size = truncate_sz ("Root Path", sizeof (NetOurRootPath), oplen);
-			memcpy (&NetOurRootPath, popt + 2, size);
+			size = truncate_sz("Root Path",
+				sizeof(NetOurRootPath), oplen);
+			memcpy(&NetOurRootPath, popt + 2, size);
 			NetOurRootPath[size] = 0;
 			break;
 #if defined(CONFIG_CMD_SNTP) && defined(CONFIG_BOOTP_NTPSERVER)
 		case 42:	/* NTP server IP */
-			NetCopyIP (&NetNtpServerIP, (popt + 2));
+			NetCopyIP(&NetNtpServerIP, (popt + 2));
 			break;
 #endif
 		case 51:
-			NetCopyLong (&dhcp_leasetime, (ulong *) (popt + 2));
+			NetCopyLong(&dhcp_leasetime, (ulong *) (popt + 2));
 			break;
 		case 53:	/* Ignore Message Type Option */
 			break;
 		case 54:
-			NetCopyIP (&NetDHCPServerIP, (popt + 2));
+			NetCopyIP(&NetDHCPServerIP, (popt + 2));
 			break;
 		case 58:	/* Ignore Renewal Time Option */
 			break;
@@ -792,7 +752,7 @@ static void DhcpOptionsProcess (uchar * popt, Bootp_t *bp)
 			 * pass the bootp packet pointer into here as the
 			 * second arg
 			 */
-			size = truncate_sz ("Opt Boot File",
+			size = truncate_sz("Opt Boot File",
 					    sizeof(bp->bp_file),
 					    oplen);
 			if (bp->bp_file[0] == '\0' && size > 0) {
@@ -813,10 +773,11 @@ static void DhcpOptionsProcess (uchar * popt, Bootp_t *bp)
 			break;
 		default:
 #if defined(CONFIG_BOOTP_VENDOREX)
-			if (dhcp_vendorex_proc (popt))
+			if (dhcp_vendorex_proc(popt))
 				break;
 #endif
-			printf ("*** Unhandled DHCP Option in OFFER/ACK: %d\n", *popt);
+			printf("*** Unhandled DHCP Option in OFFER/ACK:"
+				" %d\n", *popt);
 			break;
 		}
 		popt += oplen + 2;	/* Process next option */
@@ -825,42 +786,44 @@ static void DhcpOptionsProcess (uchar * popt, Bootp_t *bp)
 
 static int DhcpMessageType(unsigned char *popt)
 {
-	if (NetReadLong((ulong*)popt) != htonl(BOOTP_VENDOR_MAGIC))
+	if (NetReadLong((ulong *)popt) != htonl(BOOTP_VENDOR_MAGIC))
 		return -1;
 
 	popt += 4;
-	while ( *popt != 0xff ) {
-		if ( *popt == 53 )	/* DHCP Message Type */
+	while (*popt != 0xff) {
+		if (*popt == 53)	/* DHCP Message Type */
 			return *(popt + 2);
 		popt += *(popt + 1) + 2;	/* Scan through all options */
 	}
 	return -1;
 }
 
-static void DhcpSendRequestPkt(Bootp_t *bp_offer)
+static void DhcpSendRequestPkt(struct Bootp_t *bp_offer)
 {
-	volatile uchar *pkt, *iphdr;
-	Bootp_t *bp;
+	uchar *pkt, *iphdr;
+	struct Bootp_t *bp;
 	int pktlen, iplen, extlen;
+	int eth_hdr_size;
 	IPaddr_t OfferedIP;
 
 	debug("DhcpSendRequestPkt: Sending DHCPREQUEST\n");
 	pkt = NetTxPacket;
-	memset ((void*)pkt, 0, PKTSIZE);
+	memset((void *)pkt, 0, PKTSIZE);
 
-	pkt += NetSetEther(pkt, NetBcastAddr, PROT_IP);
+	eth_hdr_size = NetSetEther(pkt, NetBcastAddr, PROT_IP);
+	pkt += eth_hdr_size;
 
-	iphdr = pkt;		/* We'll need this later to set proper pkt size */
-	pkt += IP_HDR_SIZE;
+	iphdr = pkt;	/* We'll need this later to set proper pkt size */
+	pkt += IP_UDP_HDR_SIZE;
 
-	bp = (Bootp_t *)pkt;
+	bp = (struct Bootp_t *)pkt;
 	bp->bp_op = OP_BOOTREQUEST;
 	bp->bp_htype = HWT_ETHER;
 	bp->bp_hlen = HWL_ETHER;
 	bp->bp_hops = 0;
 	bp->bp_secs = htons(get_timer(0) / 1000);
-	/* Do not set the client IP, your IP, or server IP yet, since it hasn't been ACK'ed by
-	 * the server yet */
+	/* Do not set the client IP, your IP, or server IP yet, since it
+	 * hasn't been ACK'ed by the server yet */
 
 	/*
 	 * RFC3046 requires Relay Agents to discard packets with
@@ -868,7 +831,7 @@ static void DhcpSendRequestPkt(Bootp_t *bp_offer)
 	 */
 	NetWriteIP(&bp->bp_giaddr, 0);
 
-	memcpy (bp->bp_chaddr, NetOurEther, 6);
+	memcpy(bp->bp_chaddr, NetOurEther, 6);
 
 	/*
 	 * ID is the id of the OFFER packet
@@ -882,16 +845,17 @@ static void DhcpSendRequestPkt(Bootp_t *bp_offer)
 
 	/* Copy offered IP into the parameters request list */
 	NetCopyIP(&OfferedIP, &bp_offer->bp_yiaddr);
-	extlen = DhcpExtended((u8 *)bp->bp_vend, DHCP_REQUEST, NetDHCPServerIP, OfferedIP);
+	extlen = DhcpExtended((u8 *)bp->bp_vend, DHCP_REQUEST,
+		NetDHCPServerIP, OfferedIP);
 
-	pktlen = ((int)(pkt-NetTxPacket)) + BOOTP_HDR_SIZE - sizeof(bp->bp_vend) + extlen;
-	iplen = BOOTP_HDR_SIZE - sizeof(bp->bp_vend) + extlen;
-	NetSetIP(iphdr, 0xFFFFFFFFL, PORT_BOOTPS, PORT_BOOTPC, iplen);
+	iplen = BOOTP_HDR_SIZE - OPT_FIELD_SIZE + extlen;
+	pktlen = eth_hdr_size + IP_UDP_HDR_SIZE + iplen;
+	net_set_udp_header(iphdr, 0xFFFFFFFFL, PORT_BOOTPS, PORT_BOOTPC, iplen);
 
-	debug("Transmitting DHCPREQUEST packet: len = %d\n", pktlen);
 #ifdef CONFIG_BOOTP_DHCP_REQUEST_DELAY
 	udelay(CONFIG_BOOTP_DHCP_REQUEST_DELAY);
 #endif	/* CONFIG_BOOTP_DHCP_REQUEST_DELAY */
+	debug("Transmitting DHCPREQUEST packet: len = %d\n", pktlen);
 	NetSendPacket(NetTxPacket, pktlen);
 }
 
@@ -902,36 +866,38 @@ static void
 DhcpHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src,
 	    unsigned len)
 {
-	Bootp_t *bp = (Bootp_t *)pkt;
+	struct Bootp_t *bp = (struct Bootp_t *)pkt;
 
 	debug("DHCPHandler: got packet: (src=%d, dst=%d, len=%d) state: %d\n",
 		src, dest, len, dhcp_state);
 
-	if (BootpCheckPkt(pkt, dest, src, len)) /* Filter out pkts we don't want */
+	/* Filter out pkts we don't want */
+	if (BootpCheckPkt(pkt, dest, src, len))
 		return;
 
-	debug("DHCPHandler: got DHCP packet: (src=%d, dst=%d, len=%d) state: %d\n",
-		src, dest, len, dhcp_state);
+	debug("DHCPHandler: got DHCP packet: (src=%d, dst=%d, len=%d) state:"
+		" %d\n", src, dest, len, dhcp_state);
 
 	switch (dhcp_state) {
 	case SELECTING:
 		/*
 		 * Wait an appropriate time for any potential DHCPOFFER packets
-		 * to arrive.  Then select one, and generate DHCPREQUEST response.
-		 * If filename is in format we recognize, assume it is a valid
-		 * OFFER from a server we want.
+		 * to arrive.  Then select one, and generate DHCPREQUEST
+		 * response.  If filename is in format we recognize, assume it
+		 * is a valid OFFER from a server we want.
 		 */
 		debug("DHCP: state=SELECTING bp_file: \"%s\"\n", bp->bp_file);
 #ifdef CONFIG_SYS_BOOTFILE_PREFIX
 		if (strncmp(bp->bp_file,
 			    CONFIG_SYS_BOOTFILE_PREFIX,
-			    strlen(CONFIG_SYS_BOOTFILE_PREFIX)) == 0 ) {
+			    strlen(CONFIG_SYS_BOOTFILE_PREFIX)) == 0) {
 #endif	/* CONFIG_SYS_BOOTFILE_PREFIX */
 
 			debug("TRANSITIONING TO REQUESTING STATE\n");
 			dhcp_state = REQUESTING;
 
-			if (NetReadLong((ulong*)&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC))
+			if (NetReadLong((ulong *)&bp->bp_vend[0]) ==
+						htonl(BOOTP_VENDOR_MAGIC))
 				DhcpOptionsProcess((u8 *)&bp->bp_vend[4], bp);
 
 			NetSetTimeout(TIMEOUT, BootpTimeout);
@@ -945,14 +911,17 @@ DhcpHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src,
 	case REQUESTING:
 		debug("DHCP State: REQUESTING\n");
 
-		if ( DhcpMessageType((u8 *)bp->bp_vend) == DHCP_ACK ) {
-			if (NetReadLong((ulong*)&bp->bp_vend[0]) == htonl(BOOTP_VENDOR_MAGIC))
+		if (DhcpMessageType((u8 *)bp->bp_vend) == DHCP_ACK) {
+			if (NetReadLong((ulong *)&bp->bp_vend[0]) ==
+						htonl(BOOTP_VENDOR_MAGIC))
 				DhcpOptionsProcess((u8 *)&bp->bp_vend[4], bp);
-			BootpCopyNetParams(bp); /* Store net params from reply */
+			/* Store net params from reply */
+			BootpCopyNetParams(bp);
 			dhcp_state = BOUND;
-			printf ("DHCP client bound to address %pI4\n", &NetOurIP);
+			printf("DHCP client bound to address %pI4\n",
+				&NetOurIP);
 			bootstage_mark_name(BOOTSTAGE_ID_BOOTP_STOP,
-					    "bootp_stop");
+				"bootp_stop");
 
 			net_auto_load();
 			return;
@@ -962,7 +931,7 @@ DhcpHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src,
 		/* DHCP client bound to address */
 		break;
 	default:
-		puts ("DHCP: INVALID STATE\n");
+		puts("DHCP: INVALID STATE\n");
 		break;
 	}
 
diff --git a/net/bootp.h b/net/bootp.h
index 50625abea1..ecbcc4d509 100644
--- a/net/bootp.h
+++ b/net/bootp.h
@@ -10,7 +10,7 @@
 #define __BOOTP_H__
 
 #ifndef __NET_H__
-#include	<net.h>
+#include <net.h>
 #endif /* __NET_H__ */
 
 /**********************************************************************/
@@ -19,36 +19,39 @@
  *	BOOTP header.
  */
 #if defined(CONFIG_CMD_DHCP)
-#define OPT_SIZE 312	/* Minimum DHCP Options size per RFC2131 - results in 576 byte pkt */
+/* Minimum DHCP Options size per RFC2131 - results in 576 byte pkt */
+#define OPT_FIELD_SIZE 312
+#if defined(CONFIG_BOOTP_VENDOREX)
+extern u8 *dhcp_vendorex_prep(u8 *e); /*rtn new e after add own opts. */
+extern u8 *dhcp_vendorex_proc(u8 *e); /*rtn next e if mine,else NULL  */
+#endif
 #else
-#define OPT_SIZE 64
+#define OPT_FIELD_SIZE 64
 #endif
 
-typedef struct
-{
-	uchar		bp_op;		/* Operation				*/
+struct Bootp_t {
+	uchar		bp_op;		/* Operation			*/
 # define OP_BOOTREQUEST	1
 # define OP_BOOTREPLY	2
-	uchar		bp_htype;	/* Hardware type			*/
+	uchar		bp_htype;	/* Hardware type		*/
 # define HWT_ETHER	1
-	uchar		bp_hlen;	/* Hardware address length		*/
+	uchar		bp_hlen;	/* Hardware address length	*/
 # define HWL_ETHER	6
-	uchar		bp_hops;	/* Hop count (gateway thing)		*/
-	ulong		bp_id;		/* Transaction ID			*/
-	ushort		bp_secs;	/* Seconds since boot			*/
-	ushort		bp_spare1;	/* Alignment				*/
-	IPaddr_t	bp_ciaddr;	/* Client IP address			*/
-	IPaddr_t	bp_yiaddr;	/* Your (client) IP address		*/
-	IPaddr_t	bp_siaddr;	/* Server IP address			*/
-	IPaddr_t	bp_giaddr;	/* Gateway IP address			*/
-	uchar		bp_chaddr[16];	/* Client hardware address		*/
-	char		bp_sname[64];	/* Server host name			*/
-	char		bp_file[128];	/* Boot file name			*/
-	char		bp_vend[OPT_SIZE];	/* Vendor information			*/
-}	Bootp_t;
-
-#define BOOTP_HDR_SIZE	sizeof (Bootp_t)
-#define BOOTP_SIZE	(ETHER_HDR_SIZE + IP_HDR_SIZE + BOOTP_HDR_SIZE)
+	uchar		bp_hops;	/* Hop count (gateway thing)	*/
+	ulong		bp_id;		/* Transaction ID		*/
+	ushort		bp_secs;	/* Seconds since boot		*/
+	ushort		bp_spare1;	/* Alignment			*/
+	IPaddr_t	bp_ciaddr;	/* Client IP address		*/
+	IPaddr_t	bp_yiaddr;	/* Your (client) IP address	*/
+	IPaddr_t	bp_siaddr;	/* Server IP address		*/
+	IPaddr_t	bp_giaddr;	/* Gateway IP address		*/
+	uchar		bp_chaddr[16];	/* Client hardware address	*/
+	char		bp_sname[64];	/* Server host name		*/
+	char		bp_file[128];	/* Boot file name		*/
+	char		bp_vend[OPT_FIELD_SIZE]; /* Vendor information	*/
+};
+
+#define BOOTP_HDR_SIZE	sizeof(struct Bootp_t)
 
 /**********************************************************************/
 /*
@@ -56,16 +59,13 @@ typedef struct
  */
 
 /* bootp.c */
-extern ulong	BootpID;		/* ID of cur BOOTP request		*/
-extern char	BootFile[128];		/* Boot file name			*/
+extern ulong	BootpID;		/* ID of cur BOOTP request	*/
+extern char	BootFile[128];		/* Boot file name		*/
 extern int	BootpTry;
-#ifdef CONFIG_BOOTP_RANDOM_DELAY
-extern ulong	seed1, seed2;		/* seed for random BOOTP delay		*/
-#endif
 
 
 /* Send a BOOTP request */
-extern void	BootpRequest (void);
+extern void BootpRequest(void);
 
 /****************** DHCP Support *********************/
 extern void DhcpRequest(void);
diff --git a/net/cdp.c b/net/cdp.c
new file mode 100644
index 0000000000..3d9559eb3b
--- /dev/null
+++ b/net/cdp.c
@@ -0,0 +1,366 @@
+/*
+ *	Copied from Linux Monitor (LiMon) - Networking.
+ *
+ *	Copyright 1994 - 2000 Neil Russell.
+ *	(See License)
+ *	Copyright 2000 Roland Borde
+ *	Copyright 2000 Paolo Scaffardi
+ *	Copyright 2000-2002 Wolfgang Denk, wd@denx.de
+ */
+
+#include <common.h>
+#include <net.h>
+#if defined(CONFIG_CDP_VERSION)
+#include <timestamp.h>
+#endif
+
+#include "cdp.h"
+
+/* Ethernet bcast address */
+const uchar NetCDPAddr[6] = { 0x01, 0x00, 0x0c, 0xcc, 0xcc, 0xcc };
+
+#define CDP_DEVICE_ID_TLV		0x0001
+#define CDP_ADDRESS_TLV			0x0002
+#define CDP_PORT_ID_TLV			0x0003
+#define CDP_CAPABILITIES_TLV		0x0004
+#define CDP_VERSION_TLV			0x0005
+#define CDP_PLATFORM_TLV		0x0006
+#define CDP_NATIVE_VLAN_TLV		0x000a
+#define CDP_APPLIANCE_VLAN_TLV		0x000e
+#define CDP_TRIGGER_TLV			0x000f
+#define CDP_POWER_CONSUMPTION_TLV	0x0010
+#define CDP_SYSNAME_TLV			0x0014
+#define CDP_SYSOBJECT_TLV		0x0015
+#define CDP_MANAGEMENT_ADDRESS_TLV	0x0016
+
+#define CDP_TIMEOUT			250UL	/* one packet every 250ms */
+
+static int CDPSeq;
+static int CDPOK;
+
+ushort CDPNativeVLAN;
+ushort CDPApplianceVLAN;
+
+static const uchar CDP_SNAP_hdr[8] = {
+	0xAA, 0xAA, 0x03, 0x00, 0x00, 0x0C, 0x20, 0x00 };
+
+static ushort
+CDP_compute_csum(const uchar *buff, ushort len)
+{
+	ushort csum;
+	int     odd;
+	ulong   result = 0;
+	ushort  leftover;
+	ushort *p;
+
+	if (len > 0) {
+		odd = 1 & (ulong)buff;
+		if (odd) {
+			result = *buff << 8;
+			len--;
+			buff++;
+		}
+		while (len > 1) {
+			p = (ushort *)buff;
+			result += *p++;
+			buff = (uchar *)p;
+			if (result & 0x80000000)
+				result = (result & 0xFFFF) + (result >> 16);
+			len -= 2;
+		}
+		if (len) {
+			leftover = (signed short)(*(const signed char *)buff);
+			/*
+			 * CISCO SUCKS big time! (and blows too):
+			 * CDP uses the IP checksum algorithm with a twist;
+			 * for the last byte it *sign* extends and sums.
+			 */
+			result = (result & 0xffff0000) |
+				 ((result + leftover) & 0x0000ffff);
+		}
+		while (result >> 16)
+			result = (result & 0xFFFF) + (result >> 16);
+
+		if (odd)
+			result = ((result >> 8) & 0xff) |
+				 ((result & 0xff) << 8);
+	}
+
+	/* add up 16-bit and 17-bit words for 17+c bits */
+	result = (result & 0xffff) + (result >> 16);
+	/* add up 16-bit and 2-bit for 16+c bit */
+	result = (result & 0xffff) + (result >> 16);
+	/* add up carry.. */
+	result = (result & 0xffff) + (result >> 16);
+
+	/* negate */
+	csum = ~(ushort)result;
+
+	/* run time endian detection */
+	if (csum != htons(csum))	/* little endian */
+		csum = htons(csum);
+
+	return csum;
+}
+
+static int
+CDPSendTrigger(void)
+{
+	uchar *pkt;
+	ushort *s;
+	ushort *cp;
+	struct ethernet_hdr *et;
+	int len;
+	ushort chksum;
+#if	defined(CONFIG_CDP_DEVICE_ID) || defined(CONFIG_CDP_PORT_ID)   || \
+	defined(CONFIG_CDP_VERSION)   || defined(CONFIG_CDP_PLATFORM)
+	char buf[32];
+#endif
+
+	pkt = NetTxPacket;
+	et = (struct ethernet_hdr *)pkt;
+
+	/* NOTE: trigger sent not on any VLAN */
+
+	/* form ethernet header */
+	memcpy(et->et_dest, NetCDPAddr, 6);
+	memcpy(et->et_src, NetOurEther, 6);
+
+	pkt += ETHER_HDR_SIZE;
+
+	/* SNAP header */
+	memcpy((uchar *)pkt, CDP_SNAP_hdr, sizeof(CDP_SNAP_hdr));
+	pkt += sizeof(CDP_SNAP_hdr);
+
+	/* CDP header */
+	*pkt++ = 0x02;				/* CDP version 2 */
+	*pkt++ = 180;				/* TTL */
+	s = (ushort *)pkt;
+	cp = s;
+	/* checksum (0 for later calculation) */
+	*s++ = htons(0);
+
+	/* CDP fields */
+#ifdef CONFIG_CDP_DEVICE_ID
+	*s++ = htons(CDP_DEVICE_ID_TLV);
+	*s++ = htons(CONFIG_CDP_DEVICE_ID);
+	sprintf(buf, CONFIG_CDP_DEVICE_ID_PREFIX "%pm", NetOurEther);
+	memcpy((uchar *)s, buf, 16);
+	s += 16 / 2;
+#endif
+
+#ifdef CONFIG_CDP_PORT_ID
+	*s++ = htons(CDP_PORT_ID_TLV);
+	memset(buf, 0, sizeof(buf));
+	sprintf(buf, CONFIG_CDP_PORT_ID, eth_get_dev_index());
+	len = strlen(buf);
+	if (len & 1)	/* make it even */
+		len++;
+	*s++ = htons(len + 4);
+	memcpy((uchar *)s, buf, len);
+	s += len / 2;
+#endif
+
+#ifdef CONFIG_CDP_CAPABILITIES
+	*s++ = htons(CDP_CAPABILITIES_TLV);
+	*s++ = htons(8);
+	*(ulong *)s = htonl(CONFIG_CDP_CAPABILITIES);
+	s += 2;
+#endif
+
+#ifdef CONFIG_CDP_VERSION
+	*s++ = htons(CDP_VERSION_TLV);
+	memset(buf, 0, sizeof(buf));
+	strcpy(buf, CONFIG_CDP_VERSION);
+	len = strlen(buf);
+	if (len & 1)	/* make it even */
+		len++;
+	*s++ = htons(len + 4);
+	memcpy((uchar *)s, buf, len);
+	s += len / 2;
+#endif
+
+#ifdef CONFIG_CDP_PLATFORM
+	*s++ = htons(CDP_PLATFORM_TLV);
+	memset(buf, 0, sizeof(buf));
+	strcpy(buf, CONFIG_CDP_PLATFORM);
+	len = strlen(buf);
+	if (len & 1)	/* make it even */
+		len++;
+	*s++ = htons(len + 4);
+	memcpy((uchar *)s, buf, len);
+	s += len / 2;
+#endif
+
+#ifdef CONFIG_CDP_TRIGGER
+	*s++ = htons(CDP_TRIGGER_TLV);
+	*s++ = htons(8);
+	*(ulong *)s = htonl(CONFIG_CDP_TRIGGER);
+	s += 2;
+#endif
+
+#ifdef CONFIG_CDP_POWER_CONSUMPTION
+	*s++ = htons(CDP_POWER_CONSUMPTION_TLV);
+	*s++ = htons(6);
+	*s++ = htons(CONFIG_CDP_POWER_CONSUMPTION);
+#endif
+
+	/* length of ethernet packet */
+	len = (uchar *)s - ((uchar *)NetTxPacket + ETHER_HDR_SIZE);
+	et->et_protlen = htons(len);
+
+	len = ETHER_HDR_SIZE + sizeof(CDP_SNAP_hdr);
+	chksum = CDP_compute_csum((uchar *)NetTxPacket + len,
+				  (uchar *)s - (NetTxPacket + len));
+	if (chksum == 0)
+		chksum = 0xFFFF;
+	*cp = htons(chksum);
+
+	NetSendPacket(NetTxPacket, (uchar *)s - NetTxPacket);
+	return 0;
+}
+
+static void
+CDPTimeout(void)
+{
+	CDPSeq++;
+
+	if (CDPSeq < 3) {
+		NetSetTimeout(CDP_TIMEOUT, CDPTimeout);
+		CDPSendTrigger();
+		return;
+	}
+
+	/* if not OK try again */
+	if (!CDPOK)
+		NetStartAgain();
+	else
+		net_set_state(NETLOOP_SUCCESS);
+}
+
+void cdp_receive(const uchar *pkt, unsigned len)
+{
+	const uchar *t;
+	const ushort *ss;
+	ushort type, tlen;
+	ushort vlan, nvlan;
+
+	/* minimum size? */
+	if (len < sizeof(CDP_SNAP_hdr) + 4)
+		goto pkt_short;
+
+	/* check for valid CDP SNAP header */
+	if (memcmp(pkt, CDP_SNAP_hdr, sizeof(CDP_SNAP_hdr)) != 0)
+		return;
+
+	pkt += sizeof(CDP_SNAP_hdr);
+	len -= sizeof(CDP_SNAP_hdr);
+
+	/* Version of CDP protocol must be >= 2 and TTL != 0 */
+	if (pkt[0] < 0x02 || pkt[1] == 0)
+		return;
+
+	/*
+	 * if version is greater than 0x02 maybe we'll have a problem;
+	 * output a warning
+	 */
+	if (pkt[0] != 0x02)
+		printf("**WARNING: CDP packet received with a protocol version "
+				"%d > 2\n", pkt[0] & 0xff);
+
+	if (CDP_compute_csum(pkt, len) != 0)
+		return;
+
+	pkt += 4;
+	len -= 4;
+
+	vlan = htons(-1);
+	nvlan = htons(-1);
+	while (len > 0) {
+		if (len < 4)
+			goto pkt_short;
+
+		ss = (const ushort *)pkt;
+		type = ntohs(ss[0]);
+		tlen = ntohs(ss[1]);
+		if (tlen > len)
+			goto pkt_short;
+
+		pkt += tlen;
+		len -= tlen;
+
+		ss += 2;	/* point ss to the data of the TLV */
+		tlen -= 4;
+
+		switch (type) {
+		case CDP_DEVICE_ID_TLV:
+			break;
+		case CDP_ADDRESS_TLV:
+			break;
+		case CDP_PORT_ID_TLV:
+			break;
+		case CDP_CAPABILITIES_TLV:
+			break;
+		case CDP_VERSION_TLV:
+			break;
+		case CDP_PLATFORM_TLV:
+			break;
+		case CDP_NATIVE_VLAN_TLV:
+			nvlan = *ss;
+			break;
+		case CDP_APPLIANCE_VLAN_TLV:
+			t = (const uchar *)ss;
+			while (tlen > 0) {
+				if (tlen < 3)
+					goto pkt_short;
+
+				ss = (const ushort *)(t + 1);
+
+#ifdef CONFIG_CDP_APPLIANCE_VLAN_TYPE
+				if (t[0] == CONFIG_CDP_APPLIANCE_VLAN_TYPE)
+					vlan = *ss;
+#else
+				/* XXX will this work; dunno */
+				vlan = ntohs(*ss);
+#endif
+				t += 3; tlen -= 3;
+			}
+			break;
+		case CDP_TRIGGER_TLV:
+			break;
+		case CDP_POWER_CONSUMPTION_TLV:
+			break;
+		case CDP_SYSNAME_TLV:
+			break;
+		case CDP_SYSOBJECT_TLV:
+			break;
+		case CDP_MANAGEMENT_ADDRESS_TLV:
+			break;
+		}
+	}
+
+	CDPApplianceVLAN = vlan;
+	CDPNativeVLAN = nvlan;
+
+	CDPOK = 1;
+	return;
+
+ pkt_short:
+	printf("** CDP packet is too short\n");
+	return;
+}
+
+void
+CDPStart(void)
+{
+	printf("Using %s device\n", eth_get_name());
+	CDPSeq = 0;
+	CDPOK = 0;
+
+	CDPNativeVLAN = htons(-1);
+	CDPApplianceVLAN = htons(-1);
+
+	NetSetTimeout(CDP_TIMEOUT, CDPTimeout);
+
+	CDPSendTrigger();
+}
diff --git a/net/cdp.h b/net/cdp.h
new file mode 100644
index 0000000000..ec7315af79
--- /dev/null
+++ b/net/cdp.h
@@ -0,0 +1,21 @@
+/*
+ *	Copied from Linux Monitor (LiMon) - Networking.
+ *
+ *	Copyright 1994 - 2000 Neil Russell.
+ *	(See License)
+ *	Copyright 2000 Roland Borde
+ *	Copyright 2000 Paolo Scaffardi
+ *	Copyright 2000-2002 Wolfgang Denk, wd@denx.de
+ */
+
+#if defined(CONFIG_CMD_CDP)
+
+#ifndef __CDP_H__
+#define __CDP_H__
+
+void CDPStart(void);
+/* Process a received CDP packet */
+void cdp_receive(const uchar *pkt, unsigned len);
+
+#endif /* __CDP_H__ */
+#endif
diff --git a/net/dns.c b/net/dns.c
index 7a3f1f9768..ff9ddffc9d 100644
--- a/net/dns.c
+++ b/net/dns.c
@@ -45,7 +45,7 @@ DnsSend(void)
 	enum dns_query_type qtype = DNS_A_RECORD;
 
 	name = NetDNSResolve;
-	pkt = p = (uchar *)(NetTxPacket + NetEthHdrSize() + IP_HDR_SIZE);
+	pkt = p = (uchar *)(NetTxPacket + NetEthHdrSize() + IP_UDP_HDR_SIZE);
 
 	/* Prepare DNS packet header */
 	header           = (struct header *) pkt;
@@ -98,7 +98,7 @@ static void
 DnsTimeout(void)
 {
 	puts("Timeout\n");
-	NetState = NETLOOP_FAIL;
+	net_set_state(NETLOOP_FAIL);
 }
 
 static void
@@ -128,7 +128,7 @@ DnsHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src, unsigned len)
 	/* Received 0 answers */
 	if (header->nanswers == 0) {
 		puts("DNS: host not found\n");
-		NetState = NETLOOP_SUCCESS;
+		net_set_state(NETLOOP_SUCCESS);
 		return;
 	}
 
@@ -141,7 +141,7 @@ DnsHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src, unsigned len)
 	/* We sent query class 1, query type 1 */
 	if (&p[5] > e || get_unaligned_be16(p+1) != DNS_A_RECORD) {
 		puts("DNS: response was not an A record\n");
-		NetState = NETLOOP_SUCCESS;
+		net_set_state(NETLOOP_SUCCESS);
 		return;
 	}
 
@@ -191,7 +191,7 @@ DnsHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src, unsigned len)
 			puts("server responded with invalid IP number\n");
 	}
 
-	NetState = NETLOOP_SUCCESS;
+	net_set_state(NETLOOP_SUCCESS);
 }
 
 void
@@ -200,7 +200,7 @@ DnsStart(void)
 	debug("%s\n", __func__);
 
 	NetSetTimeout(DNS_TIMEOUT, DnsTimeout);
-	NetSetHandler(DnsHandler);
+	net_set_udp_handler(DnsHandler);
 
 	DnsSend();
 }
diff --git a/net/eth.c b/net/eth.c
index 3eeb908a35..d9a643073d 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -82,14 +82,12 @@ int cpu_eth_init(bd_t *bis) __attribute__((weak, alias("__def_eth_init")));
 int board_eth_init(bd_t *bis) __attribute__((weak, alias("__def_eth_init")));
 
 #ifdef CONFIG_API
-extern void (*push_packet)(volatile void *, int);
-
 static struct {
 	uchar data[PKTSIZE];
 	int length;
 } eth_rcv_bufs[PKTBUFSRX];
 
-static unsigned int eth_rcv_current = 0, eth_rcv_last = 0;
+static unsigned int eth_rcv_current, eth_rcv_last;
 #endif
 
 static struct eth_device *eth_devices, *eth_current;
@@ -141,11 +139,10 @@ struct eth_device *eth_get_dev_by_index(int index)
 	return target_dev;
 }
 
-int eth_get_dev_index (void)
+int eth_get_dev_index(void)
 {
-	if (!eth_current) {
+	if (!eth_current)
 		return -1;
-	}
 
 	return eth_current->index;
 }
@@ -176,7 +173,7 @@ int eth_write_hwaddr(struct eth_device *dev, const char *base_name,
 
 	if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) {
 		if (memcmp(dev->enetaddr, "\0\0\0\0\0\0", 6) &&
-			memcmp(dev->enetaddr, env_enetaddr, 6)) {
+				memcmp(dev->enetaddr, env_enetaddr, 6)) {
 			printf("\nWarning: %s MAC addresses don't match:\n",
 				dev->name);
 			printf("Address in SROM is         %pM\n",
@@ -189,10 +186,9 @@ int eth_write_hwaddr(struct eth_device *dev, const char *base_name,
 	}
 
 	if (dev->write_hwaddr &&
-		!eth_mac_skip(eth_number) &&
-		is_valid_ether_addr(dev->enetaddr)) {
+			!eth_mac_skip(eth_number) &&
+			is_valid_ether_addr(dev->enetaddr))
 		ret = dev->write_hwaddr(dev);
-	}
 
 	return ret;
 }
@@ -200,7 +196,7 @@ int eth_write_hwaddr(struct eth_device *dev, const char *base_name,
 int eth_register(struct eth_device *dev)
 {
 	struct eth_device *d;
-	static int index = 0;
+	static int index;
 
 	assert(strlen(dev->name) < sizeof(dev->name));
 
@@ -208,7 +204,7 @@ int eth_register(struct eth_device *dev)
 		eth_current = eth_devices = dev;
 		eth_current_changed();
 	} else {
-		for (d=eth_devices; d->next!=eth_devices; d=d->next)
+		for (d = eth_devices; d->next != eth_devices; d = d->next)
 			;
 		d->next = dev;
 	}
@@ -249,6 +245,14 @@ int eth_unregister(struct eth_device *dev)
 	return 0;
 }
 
+static void eth_env_init(bd_t *bis)
+{
+	const char *s;
+
+	if ((s = getenv("bootfile")) != NULL)
+		copy_filename(BootFile, s, sizeof(BootFile));
+}
+
 int eth_initialize(bd_t *bis)
 {
 	int num_devices = 0;
@@ -264,6 +268,8 @@ int eth_initialize(bd_t *bis)
 	phy_init();
 #endif
 
+	eth_env_init(bis);
+
 	/*
 	 * If board-specific initialization exists, call it.
 	 * If not, call a CPU-specific one
@@ -278,36 +284,37 @@ int eth_initialize(bd_t *bis)
 		printf("Net Initialization Skipped\n");
 
 	if (!eth_devices) {
-		puts ("No ethernet found.\n");
+		puts("No ethernet found.\n");
 		bootstage_error(BOOTSTAGE_ID_NET_ETH_START);
 	} else {
 		struct eth_device *dev = eth_devices;
-		char *ethprime = getenv ("ethprime");
+		char *ethprime = getenv("ethprime");
 
 		bootstage_mark(BOOTSTAGE_ID_NET_ETH_INIT);
 		do {
 			if (dev->index)
-				puts (", ");
+				puts(", ");
 
 			printf("%s", dev->name);
 
-			if (ethprime && strcmp (dev->name, ethprime) == 0) {
+			if (ethprime && strcmp(dev->name, ethprime) == 0) {
 				eth_current = dev;
-				puts (" [PRIME]");
+				puts(" [PRIME]");
 			}
 
 			if (strchr(dev->name, ' '))
-				puts("\nWarning: eth device name has a space!\n");
+				puts("\nWarning: eth device name has a space!"
+					"\n");
 
 			if (eth_write_hwaddr(dev, "eth", dev->index))
 				puts("\nWarning: failed to set MAC address\n");
 
 			dev = dev->next;
 			num_devices++;
-		} while(dev != eth_devices);
+		} while (dev != eth_devices);
 
 		eth_current_changed();
-		putc ('\n');
+		putc('\n');
 	}
 
 	return num_devices;
@@ -318,9 +325,9 @@ int eth_initialize(bd_t *bis)
  * mcast_addr: multicast ipaddr from which multicast Mac is made
  * join: 1=join, 0=leave.
  */
-int eth_mcast_join( IPaddr_t mcast_ip, u8 join)
+int eth_mcast_join(IPaddr_t mcast_ip, u8 join)
 {
- u8 mcast_mac[6];
+	u8 mcast_mac[6];
 	if (!eth_current || !eth_current->mcast)
 		return -1;
 	mcast_mac[5] = htonl(mcast_ip) & 0xff;
@@ -337,7 +344,7 @@ int eth_mcast_join( IPaddr_t mcast_ip, u8 join)
  * some other adapter -- hash tables
  */
 #define CRCPOLY_LE 0xedb88320
-u32 ether_crc (size_t len, unsigned char const *p)
+u32 ether_crc(size_t len, unsigned char const *p)
 {
 	int i;
 	u32 crc;
@@ -364,7 +371,7 @@ int eth_init(bd_t *bis)
 	struct eth_device *old_current, *dev;
 
 	if (!eth_current) {
-		puts ("No ethernet found.\n");
+		puts("No ethernet found.\n");
 		return -1;
 	}
 
@@ -384,7 +391,7 @@ int eth_init(bd_t *bis)
 	do {
 		debug("Trying %s\n", eth_current->name);
 
-		if (eth_current->init(eth_current,bis) >= 0) {
+		if (eth_current->init(eth_current, bis) >= 0) {
 			eth_current->state = ETH_STATE_ACTIVE;
 
 			return 0;
@@ -407,7 +414,7 @@ void eth_halt(void)
 	eth_current->state = ETH_STATE_PASSIVE;
 }
 
-int eth_send(volatile void *packet, int length)
+int eth_send(void *packet, int length)
 {
 	if (!eth_current)
 		return -1;
@@ -424,9 +431,9 @@ int eth_rx(void)
 }
 
 #ifdef CONFIG_API
-static void eth_save_packet(volatile void *packet, int length)
+static void eth_save_packet(void *packet, int length)
 {
-	volatile char *p = packet;
+	char *p = packet;
 	int i;
 
 	if ((eth_rcv_last+1) % PKTBUFSRX == eth_rcv_current)
@@ -442,9 +449,9 @@ static void eth_save_packet(volatile void *packet, int length)
 	eth_rcv_last = (eth_rcv_last + 1) % PKTBUFSRX;
 }
 
-int eth_receive(volatile void *packet, int length)
+int eth_receive(void *packet, int length)
 {
-	volatile char *p = packet;
+	char *p = packet;
 	void *pp = push_packet;
 	int i;
 
@@ -472,38 +479,36 @@ int eth_receive(volatile void *packet, int length)
 
 void eth_try_another(int first_restart)
 {
-	static struct eth_device *first_failed = NULL;
+	static struct eth_device *first_failed;
 	char *ethrotate;
 
 	/*
 	 * Do not rotate between network interfaces when
 	 * 'ethrotate' variable is set to 'no'.
 	 */
-	if (((ethrotate = getenv ("ethrotate")) != NULL) &&
-	    (strcmp(ethrotate, "no") == 0))
+	ethrotate = getenv("ethrotate");
+	if ((ethrotate != NULL) && (strcmp(ethrotate, "no") == 0))
 		return;
 
 	if (!eth_current)
 		return;
 
-	if (first_restart) {
+	if (first_restart)
 		first_failed = eth_current;
-	}
 
 	eth_current = eth_current->next;
 
 	eth_current_changed();
 
-	if (first_failed == eth_current) {
+	if (first_failed == eth_current)
 		NetRestartWrap = 1;
-	}
 }
 
 void eth_set_current(void)
 {
-	static char *act = NULL;
-	static int  env_changed_id = 0;
-	struct eth_device* old_current;
+	static char *act;
+	static int  env_changed_id;
+	struct eth_device *old_current;
 	int	env_id;
 
 	if (!eth_current)	/* XXX no current */
@@ -526,7 +531,7 @@ void eth_set_current(void)
 	eth_current_changed();
 }
 
-char *eth_get_name (void)
+char *eth_get_name(void)
 {
-	return (eth_current ? eth_current->name : "unknown");
+	return eth_current ? eth_current->name : "unknown";
 }
diff --git a/net/link_local.c b/net/link_local.c
new file mode 100644
index 0000000000..336286395b
--- /dev/null
+++ b/net/link_local.c
@@ -0,0 +1,334 @@
+/*
+ * RFC3927 ZeroConf IPv4 Link-Local addressing
+ * (see <http://www.zeroconf.org/>)
+ *
+ * Copied from BusyBox - networking/zcip.c
+ *
+ * Copyright (C) 2003 by Arthur van Hoff (avh@strangeberry.com)
+ * Copyright (C) 2004 by David Brownell
+ * Copyright (C) 2010 by Joe Hershberger
+ *
+ * Licensed under the GPL v2 or later
+ */
+
+#include <common.h>
+#include <net.h>
+#include "arp.h"
+#include "net_rand.h"
+
+/* We don't need more than 32 bits of the counter */
+#define MONOTONIC_MS() ((unsigned)get_timer(0) * (1000 / CONFIG_SYS_HZ))
+
+enum {
+/* 169.254.0.0 */
+	LINKLOCAL_ADDR = 0xa9fe0000,
+
+	IN_CLASSB_NET = 0xffff0000,
+	IN_CLASSB_HOST = 0x0000ffff,
+
+/* protocol timeout parameters, specified in seconds */
+	PROBE_WAIT = 1,
+	PROBE_MIN = 1,
+	PROBE_MAX = 2,
+	PROBE_NUM = 3,
+	MAX_CONFLICTS = 10,
+	RATE_LIMIT_INTERVAL = 60,
+	ANNOUNCE_WAIT = 2,
+	ANNOUNCE_NUM = 2,
+	ANNOUNCE_INTERVAL = 2,
+	DEFEND_INTERVAL = 10
+};
+
+/* States during the configuration process. */
+static enum ll_state_t {
+	PROBE = 0,
+	RATE_LIMIT_PROBE,
+	ANNOUNCE,
+	MONITOR,
+	DEFEND,
+	DISABLED
+} state = DISABLED;
+
+static IPaddr_t ip;
+static int timeout_ms = -1;
+static unsigned deadline_ms;
+static unsigned conflicts;
+static unsigned nprobes;
+static unsigned nclaims;
+static int ready;
+
+static void link_local_timeout(void);
+
+/**
+ * Pick a random link local IP address on 169.254/16, except that
+ * the first and last 256 addresses are reserved.
+ */
+static IPaddr_t pick(void)
+{
+	unsigned tmp;
+
+	do {
+		tmp = rand() & IN_CLASSB_HOST;
+	} while (tmp > (IN_CLASSB_HOST - 0x0200));
+	return (IPaddr_t) htonl((LINKLOCAL_ADDR + 0x0100) + tmp);
+}
+
+/**
+ * Return milliseconds of random delay, up to "secs" seconds.
+ */
+static inline unsigned random_delay_ms(unsigned secs)
+{
+	return rand() % (secs * 1000);
+}
+
+static void configure_wait(void)
+{
+	if (timeout_ms == -1)
+		return;
+
+	/* poll, being ready to adjust current timeout */
+	if (!timeout_ms)
+		timeout_ms = random_delay_ms(PROBE_WAIT);
+
+	/* set deadline_ms to the point in time when we timeout */
+	deadline_ms = MONOTONIC_MS() + timeout_ms;
+
+	debug_cond(DEBUG_DEV_PKT, "...wait %d %s nprobes=%u, nclaims=%u\n",
+			timeout_ms, eth_get_name(), nprobes, nclaims);
+
+	NetSetTimeout(timeout_ms, link_local_timeout);
+}
+
+void link_local_start(void)
+{
+	ip = getenv_IPaddr("llipaddr");
+	if (ip != 0 && (ip & IN_CLASSB_NET) != LINKLOCAL_ADDR) {
+		puts("invalid link address");
+		net_set_state(NETLOOP_FAIL);
+		return;
+	}
+	NetOurSubnetMask = IN_CLASSB_NET;
+
+	srand_mac();
+	if (ip == 0)
+		ip = pick();
+
+	state = PROBE;
+	timeout_ms = 0;
+	conflicts = 0;
+	nprobes = 0;
+	nclaims = 0;
+	ready = 0;
+
+	configure_wait();
+}
+
+static void link_local_timeout(void)
+{
+	switch (state) {
+	case PROBE:
+		/* timeouts in the PROBE state mean no conflicting ARP packets
+		   have been received, so we can progress through the states */
+		if (nprobes < PROBE_NUM) {
+			nprobes++;
+			debug_cond(DEBUG_LL_STATE, "probe/%u %s@%pI4\n",
+					nprobes, eth_get_name(), &ip);
+			arp_raw_request(0, NetEtherNullAddr, ip);
+			timeout_ms = PROBE_MIN * 1000;
+			timeout_ms += random_delay_ms(PROBE_MAX - PROBE_MIN);
+		} else {
+			/* Switch to announce state */
+			state = ANNOUNCE;
+			nclaims = 0;
+			debug_cond(DEBUG_LL_STATE, "announce/%u %s@%pI4\n",
+					nclaims, eth_get_name(), &ip);
+			arp_raw_request(ip, NetOurEther, ip);
+			timeout_ms = ANNOUNCE_INTERVAL * 1000;
+		}
+		break;
+	case RATE_LIMIT_PROBE:
+		/* timeouts in the RATE_LIMIT_PROBE state mean no conflicting
+		   ARP packets have been received, so we can move immediately
+		   to the announce state */
+		state = ANNOUNCE;
+		nclaims = 0;
+		debug_cond(DEBUG_LL_STATE, "announce/%u %s@%pI4\n",
+				nclaims, eth_get_name(), &ip);
+		arp_raw_request(ip, NetOurEther, ip);
+		timeout_ms = ANNOUNCE_INTERVAL * 1000;
+		break;
+	case ANNOUNCE:
+		/* timeouts in the ANNOUNCE state mean no conflicting ARP
+		   packets have been received, so we can progress through
+		   the states */
+		if (nclaims < ANNOUNCE_NUM) {
+			nclaims++;
+			debug_cond(DEBUG_LL_STATE, "announce/%u %s@%pI4\n",
+					nclaims, eth_get_name(), &ip);
+			arp_raw_request(ip, NetOurEther, ip);
+			timeout_ms = ANNOUNCE_INTERVAL * 1000;
+		} else {
+			/* Switch to monitor state */
+			state = MONITOR;
+			printf("Successfully assigned %pI4\n", &ip);
+			NetCopyIP(&NetOurIP, &ip);
+			ready = 1;
+			conflicts = 0;
+			timeout_ms = -1;
+			/* Never timeout in the monitor state */
+			NetSetTimeout(0, NULL);
+
+			/* NOTE: all other exit paths should deconfig ... */
+			net_set_state(NETLOOP_SUCCESS);
+			return;
+		}
+		break;
+	case DEFEND:
+		/* We won!  No ARP replies, so just go back to monitor */
+		state = MONITOR;
+		timeout_ms = -1;
+		conflicts = 0;
+		break;
+	default:
+		/* Invalid, should never happen.  Restart the whole protocol */
+		state = PROBE;
+		ip = pick();
+		timeout_ms = 0;
+		nprobes = 0;
+		nclaims = 0;
+		break;
+	}
+	configure_wait();
+}
+
+void link_local_receive_arp(struct arp_hdr *arp, int len)
+{
+	int source_ip_conflict;
+	int target_ip_conflict;
+
+	if (state == DISABLED)
+		return;
+
+	/* We need to adjust the timeout in case we didn't receive a
+	   conflicting packet. */
+	if (timeout_ms > 0) {
+		unsigned diff = deadline_ms - MONOTONIC_MS();
+		if ((int)(diff) < 0) {
+			/* Current time is greater than the expected timeout
+			   time. This should never happen */
+			debug_cond(DEBUG_LL_STATE,
+				"missed an expected timeout\n");
+			timeout_ms = 0;
+		} else {
+			debug_cond(DEBUG_INT_STATE, "adjusting timeout\n");
+			timeout_ms = diff | 1; /* never 0 */
+		}
+	}
+/*
+ * XXX Don't bother with ethernet link just yet
+	if ((fds[0].revents & POLLIN) == 0) {
+		if (fds[0].revents & POLLERR) {
+			// FIXME: links routinely go down;
+			// this shouldn't necessarily exit.
+			bb_error_msg("iface %s is down", eth_get_name());
+			if (ready) {
+				run(argv, "deconfig", &ip);
+			}
+			return EXIT_FAILURE;
+		}
+		continue;
+	}
+*/
+
+	debug_cond(DEBUG_INT_STATE, "%s recv arp type=%d, op=%d,\n",
+		eth_get_name(), ntohs(arp->ar_pro),
+		ntohs(arp->ar_op));
+	debug_cond(DEBUG_INT_STATE, "\tsource=%pM %pI4\n",
+		&arp->ar_sha,
+		&arp->ar_spa);
+	debug_cond(DEBUG_INT_STATE, "\ttarget=%pM %pI4\n",
+		&arp->ar_tha,
+		&arp->ar_tpa);
+
+	if (arp->ar_op != htons(ARPOP_REQUEST)
+	 && arp->ar_op != htons(ARPOP_REPLY)
+	) {
+		configure_wait();
+		return;
+	}
+
+	source_ip_conflict = 0;
+	target_ip_conflict = 0;
+
+	if (memcmp(&arp->ar_spa, &ip, ARP_PLEN) == 0
+	 && memcmp(&arp->ar_sha, NetOurEther, ARP_HLEN) != 0
+	) {
+		source_ip_conflict = 1;
+	}
+	if (arp->ar_op == htons(ARPOP_REQUEST)
+	 && memcmp(&arp->ar_tpa, &ip, ARP_PLEN) == 0
+	 && memcmp(&arp->ar_tha, NetOurEther, ARP_HLEN) != 0
+	) {
+		target_ip_conflict = 1;
+	}
+
+	debug_cond(DEBUG_NET_PKT,
+		"state = %d, source ip conflict = %d, target ip conflict = "
+		"%d\n", state, source_ip_conflict, target_ip_conflict);
+	switch (state) {
+	case PROBE:
+	case ANNOUNCE:
+		/* When probing or announcing, check for source IP conflicts
+		   and other hosts doing ARP probes (target IP conflicts). */
+		if (source_ip_conflict || target_ip_conflict) {
+			conflicts++;
+			state = PROBE;
+			if (conflicts >= MAX_CONFLICTS) {
+				debug("%s ratelimit\n", eth_get_name());
+				timeout_ms = RATE_LIMIT_INTERVAL * 1000;
+				state = RATE_LIMIT_PROBE;
+			}
+
+			/* restart the whole protocol */
+			ip = pick();
+			timeout_ms = 0;
+			nprobes = 0;
+			nclaims = 0;
+		}
+		break;
+	case MONITOR:
+		/* If a conflict, we try to defend with a single ARP probe */
+		if (source_ip_conflict) {
+			debug("monitor conflict -- defending\n");
+			state = DEFEND;
+			timeout_ms = DEFEND_INTERVAL * 1000;
+			arp_raw_request(ip, NetOurEther, ip);
+		}
+		break;
+	case DEFEND:
+		/* Well, we tried.  Start over (on conflict) */
+		if (source_ip_conflict) {
+			state = PROBE;
+			debug("defend conflict -- starting over\n");
+			ready = 0;
+			NetOurIP = 0;
+
+			/* restart the whole protocol */
+			ip = pick();
+			timeout_ms = 0;
+			nprobes = 0;
+			nclaims = 0;
+		}
+		break;
+	default:
+		/* Invalid, should never happen.  Restart the whole protocol */
+		debug("invalid state -- starting over\n");
+		state = PROBE;
+		ip = pick();
+		timeout_ms = 0;
+		nprobes = 0;
+		nclaims = 0;
+		break;
+	}
+	configure_wait();
+}
diff --git a/net/link_local.h b/net/link_local.h
new file mode 100644
index 0000000000..bb998164df
--- /dev/null
+++ b/net/link_local.h
@@ -0,0 +1,24 @@
+/*
+ * RFC3927 ZeroConf IPv4 Link-Local addressing
+ * (see <http://www.zeroconf.org/>)
+ *
+ * Copied from BusyBox - networking/zcip.c
+ *
+ * Copyright (C) 2003 by Arthur van Hoff (avh@strangeberry.com)
+ * Copyright (C) 2004 by David Brownell
+ *
+ * Licensed under the GPL v2 or later
+ */
+
+#if defined(CONFIG_CMD_LINK_LOCAL)
+
+#ifndef __LINK_LOCAL_H__
+#define __LINK_LOCAL_H__
+
+#include <common.h>
+
+void link_local_receive_arp(struct arp_hdr *arp, int len);
+void link_local_start(void);
+
+#endif /* __LINK_LOCAL_H__ */
+#endif
diff --git a/net/net.c b/net/net.c
index c5acf8ff6e..9de7d92643 100644
--- a/net/net.c
+++ b/net/net.c
@@ -23,6 +23,12 @@
  *			- name of bootfile
  *	Next step:	ARP
  *
+ * LINK_LOCAL:
+ *
+ *	Prerequisites:	- own ethernet address
+ *	We want:	- own IP address
+ *	Next step:	ARP
+ *
  * RARP:
  *
  *	Prerequisites:	- own ethernet address
@@ -75,45 +81,31 @@
 
 
 #include <common.h>
-#include <watchdog.h>
 #include <command.h>
 #include <net.h>
+#if defined(CONFIG_STATUS_LED)
+#include <miiphy.h>
+#include <status_led.h>
+#endif
+#include <watchdog.h>
+#include <linux/compiler.h>
+#include "arp.h"
 #include "bootp.h"
-#include "tftp.h"
-#ifdef CONFIG_CMD_RARP
-#include "rarp.h"
+#include "cdp.h"
+#if defined(CONFIG_CMD_DNS)
+#include "dns.h"
 #endif
+#include "link_local.h"
 #include "nfs.h"
-#ifdef CONFIG_STATUS_LED
-#include <status_led.h>
-#include <miiphy.h>
-#endif
+#include "ping.h"
+#include "rarp.h"
 #if defined(CONFIG_CMD_SNTP)
 #include "sntp.h"
 #endif
-#if defined(CONFIG_CDP_VERSION)
-#include <timestamp.h>
-#endif
-#if defined(CONFIG_CMD_DNS)
-#include "dns.h"
-#endif
+#include "tftp.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef	CONFIG_ARP_TIMEOUT
-/* Milliseconds before trying ARP again */
-# define ARP_TIMEOUT		5000UL
-#else
-# define ARP_TIMEOUT		CONFIG_ARP_TIMEOUT
-#endif
-
-
-#ifndef	CONFIG_NET_RETRY_COUNT
-# define ARP_TIMEOUT_COUNT	5	/* # of timeouts before giving up  */
-#else
-# define ARP_TIMEOUT_COUNT	CONFIG_NET_RETRY_COUNT
-#endif
-
 /** BOOTP EXTENTIONS **/
 
 /* Our subnet mask (0=unknown) */
@@ -152,7 +144,7 @@ IPaddr_t	NetOurIP;
 /* Server IP addr (0 = unknown) */
 IPaddr_t	NetServerIP;
 /* Current receive packet */
-volatile uchar *NetRxPacket;
+uchar *NetRxPacket;
 /* Current rx packet length */
 int		NetRxPacketLen;
 /* IP packet ID */
@@ -161,14 +153,10 @@ unsigned	NetIPID;
 uchar		NetBcastAddr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 uchar		NetEtherNullAddr[6];
 #ifdef CONFIG_API
-void		(*push_packet)(volatile void *, int len) = 0;
-#endif
-#if defined(CONFIG_CMD_CDP)
-/* Ethernet bcast address */
-uchar		NetCDPAddr[6] = { 0x01, 0x00, 0x0c, 0xcc, 0xcc, 0xcc };
+void		(*push_packet)(void *, int len) = 0;
 #endif
 /* Network loop state */
-int		NetState;
+enum net_loop_state net_state;
 /* Tried all network devices */
 int		NetRestartWrap;
 /* Network loop restarted */
@@ -185,17 +173,6 @@ ushort		NetOurNativeVLAN = 0xFFFF;
 /* Boot File name */
 char		BootFile[128];
 
-#if defined(CONFIG_CMD_PING)
-/* the ip address to ping */
-IPaddr_t	NetPingIP;
-
-static void PingStart(void);
-#endif
-
-#if defined(CONFIG_CMD_CDP)
-static void CDPStart(void);
-#endif
-
 #if defined(CONFIG_CMD_SNTP)
 /* NTP server IP address */
 IPaddr_t	NetNtpServerIP;
@@ -203,20 +180,18 @@ IPaddr_t	NetNtpServerIP;
 int		NetTimeOffset;
 #endif
 
-#ifdef CONFIG_NETCONSOLE
-void NcStart(void);
-int nc_input_packet(uchar *pkt, unsigned dest, unsigned src, unsigned len);
-#endif
-
-volatile uchar	PktBuf[(PKTBUFSRX+1) * PKTSIZE_ALIGN + PKTALIGN];
+uchar PktBuf[(PKTBUFSRX+1) * PKTSIZE_ALIGN + PKTALIGN];
 
 /* Receive packet */
-volatile uchar *NetRxPackets[PKTBUFSRX];
+uchar *NetRxPackets[PKTBUFSRX];
 
-/* Current RX packet handler */
-static rxhand_f *packetHandler;
+/* Current UDP RX packet handler */
+static rxhand_f *udp_packet_handler;
+/* Current ARP RX packet handler */
+static rxhand_f *arp_packet_handler;
 #ifdef CONFIG_CMD_TFTPPUT
-static rxhand_icmp_f *packet_icmp_handler;	/* Current ICMP rx handler */
+/* Current ICMP rx handler */
+static rxhand_icmp_f *packet_icmp_handler;
 #endif
 /* Current timeout handler */
 static thand_f *timeHandler;
@@ -225,7 +200,7 @@ static ulong	timeStart;
 /* Current timeout value */
 static ulong	timeDelta;
 /* THE transmit packet */
-volatile uchar *NetTxPacket;
+uchar *NetTxPacket;
 
 static int net_check_prereq(enum proto_t protocol);
 
@@ -233,82 +208,6 @@ static int NetTryCount;
 
 /**********************************************************************/
 
-IPaddr_t	NetArpWaitPacketIP;
-IPaddr_t	NetArpWaitReplyIP;
-/* MAC address of waiting packet's destination */
-uchar	       *NetArpWaitPacketMAC;
-/* THE transmit packet */
-uchar	       *NetArpWaitTxPacket;
-int		NetArpWaitTxPacketSize;
-uchar		NetArpWaitPacketBuf[PKTSIZE_ALIGN + PKTALIGN];
-ulong		NetArpWaitTimerStart;
-int		NetArpWaitTry;
-
-void ArpRequest(void)
-{
-	volatile uchar *pkt;
-	ARP_t *arp;
-
-	debug("ARP broadcast %d\n", NetArpWaitTry);
-
-	pkt = NetTxPacket;
-
-	pkt += NetSetEther(pkt, NetBcastAddr, PROT_ARP);
-
-	arp = (ARP_t *) pkt;
-
-	arp->ar_hrd = htons(ARP_ETHER);
-	arp->ar_pro = htons(PROT_IP);
-	arp->ar_hln = 6;
-	arp->ar_pln = 4;
-	arp->ar_op = htons(ARPOP_REQUEST);
-
-	/* source ET addr */
-	memcpy(&arp->ar_data[0], NetOurEther, 6);
-	/* source IP addr */
-	NetWriteIP((uchar *) &arp->ar_data[6], NetOurIP);
-	/* dest ET addr = 0 */
-	memset(&arp->ar_data[10], '\0', 6);
-	if ((NetArpWaitPacketIP & NetOurSubnetMask) !=
-	    (NetOurIP & NetOurSubnetMask)) {
-		if (NetOurGatewayIP == 0) {
-			puts("## Warning: gatewayip needed but not set\n");
-			NetArpWaitReplyIP = NetArpWaitPacketIP;
-		} else {
-			NetArpWaitReplyIP = NetOurGatewayIP;
-		}
-	} else {
-		NetArpWaitReplyIP = NetArpWaitPacketIP;
-	}
-
-	NetWriteIP((uchar *) &arp->ar_data[16], NetArpWaitReplyIP);
-	(void) eth_send(NetTxPacket, (pkt - NetTxPacket) + ARP_HDR_SIZE);
-}
-
-void ArpTimeoutCheck(void)
-{
-	ulong t;
-
-	if (!NetArpWaitPacketIP)
-		return;
-
-	t = get_timer(0);
-
-	/* check for arp timeout */
-	if ((t - NetArpWaitTimerStart) > ARP_TIMEOUT) {
-		NetArpWaitTry++;
-
-		if (NetArpWaitTry >= ARP_TIMEOUT_COUNT) {
-			puts("\nARP Retry count exceeded; starting again\n");
-			NetArpWaitTry = 0;
-			NetStartAgain();
-		} else {
-			NetArpWaitTimerStart = t;
-			ArpRequest();
-		}
-	}
-}
-
 /*
  * Check if autoload is enabled. If so, use either NFS or TFTP to download
  * the boot file.
@@ -323,7 +222,7 @@ void net_auto_load(void)
 			 * Just use BOOTP/RARP to configure system;
 			 * Do not use TFTP to load the bootfile.
 			 */
-			NetState = NETLOOP_SUCCESS;
+			net_set_state(NETLOOP_SUCCESS);
 			return;
 		}
 #if defined(CONFIG_CMD_NFS)
@@ -339,16 +238,14 @@ void net_auto_load(void)
 	TftpStart(TFTPGET);
 }
 
-static void NetInitLoop(enum proto_t protocol)
+static void NetInitLoop(void)
 {
 	static int env_changed_id;
-	bd_t *bd = gd->bd;
 	int env_id = get_env_id();
 
 	/* update only when the environment has changed */
 	if (env_changed_id != env_id) {
 		NetOurIP = getenv_IPaddr("ipaddr");
-		NetCopyIP(&bd->bi_ip_addr, &NetOurIP);
 		NetOurGatewayIP = getenv_IPaddr("gatewayip");
 		NetOurSubnetMask = getenv_IPaddr("netmask");
 		NetServerIP = getenv_IPaddr("serverip");
@@ -363,6 +260,43 @@ static void NetInitLoop(enum proto_t protocol)
 	return;
 }
 
+static void net_clear_handlers(void)
+{
+	net_set_udp_handler(NULL);
+	net_set_arp_handler(NULL);
+	NetSetTimeout(0, NULL);
+}
+
+static void net_cleanup_loop(void)
+{
+	net_clear_handlers();
+}
+
+void net_init(void)
+{
+	static int first_call = 1;
+
+	if (first_call) {
+		/*
+		 *	Setup packet buffers, aligned correctly.
+		 */
+		int i;
+
+		NetTxPacket = &PktBuf[0] + (PKTALIGN - 1);
+		NetTxPacket -= (ulong)NetTxPacket % PKTALIGN;
+		for (i = 0; i < PKTBUFSRX; i++)
+			NetRxPackets[i] = NetTxPacket + (i + 1) * PKTSIZE_ALIGN;
+
+		ArpInit();
+		net_clear_handlers();
+
+		/* Only need to setup buffer pointers once. */
+		first_call = 0;
+	}
+
+	NetInitLoop();
+}
+
 /**********************************************************************/
 /*
  *	Main network processing loop.
@@ -375,34 +309,11 @@ int NetLoop(enum proto_t protocol)
 
 	NetRestarted = 0;
 	NetDevExists = 0;
-
-	/* XXX problem with bss workaround */
-	NetArpWaitPacketMAC = NULL;
-	NetArpWaitTxPacket = NULL;
-	NetArpWaitPacketIP = 0;
-	NetArpWaitReplyIP = 0;
-	NetArpWaitTxPacket = NULL;
-	NetTxPacket = NULL;
 	NetTryCount = 1;
-
-	if (!NetTxPacket) {
-		int	i;
-		/*
-		 *	Setup packet buffers, aligned correctly.
-		 */
-		NetTxPacket = &PktBuf[0] + (PKTALIGN - 1);
-		NetTxPacket -= (ulong)NetTxPacket % PKTALIGN;
-		for (i = 0; i < PKTBUFSRX; i++)
-			NetRxPackets[i] = NetTxPacket + (i+1)*PKTSIZE_ALIGN;
-	}
-
-	if (!NetArpWaitTxPacket) {
-		NetArpWaitTxPacket = &NetArpWaitPacketBuf[0] + (PKTALIGN - 1);
-		NetArpWaitTxPacket -= (ulong)NetArpWaitTxPacket % PKTALIGN;
-		NetArpWaitTxPacketSize = 0;
-	}
+	debug_cond(DEBUG_INT_STATE, "--- NetLoop Entry\n");
 
 	bootstage_mark_name(BOOTSTAGE_ID_ETH_START, "eth_start");
+	net_init();
 	eth_halt();
 	eth_set_current();
 	if (eth_init(bd) < 0) {
@@ -413,14 +324,15 @@ int NetLoop(enum proto_t protocol)
 restart:
 	memcpy(NetOurEther, eth_get_dev()->enetaddr, 6);
 
-	NetState = NETLOOP_CONTINUE;
+	net_set_state(NETLOOP_CONTINUE);
 
 	/*
 	 *	Start the ball rolling with the given start function.  From
 	 *	here on, this code is a state machine driven by received
 	 *	packets and timer events.
 	 */
-	NetInitLoop(protocol);
+	debug_cond(DEBUG_INT_STATE, "--- NetLoop Init\n");
+	NetInitLoop();
 
 	switch (net_check_prereq(protocol)) {
 	case 1:
@@ -471,7 +383,7 @@ restart:
 #endif
 #if defined(CONFIG_CMD_PING)
 		case PING:
-			PingStart();
+			ping_start();
 			break;
 #endif
 #if defined(CONFIG_CMD_NFS)
@@ -499,6 +411,11 @@ restart:
 			DnsStart();
 			break;
 #endif
+#if defined(CONFIG_CMD_LINK_LOCAL)
+		case LINKLOCAL:
+			link_local_start();
+			break;
+#endif
 		default:
 			break;
 		}
@@ -522,15 +439,12 @@ restart:
 
 	/*
 	 *	Main packet reception loop.  Loop receiving packets until
-	 *	someone sets `NetState' to a state that terminates.
+	 *	someone sets `net_state' to a state that terminates.
 	 */
 	for (;;) {
 		WATCHDOG_RESET();
 #ifdef CONFIG_SHOW_ACTIVITY
-		{
-			extern void show_activity(int arg);
-			show_activity(1);
-		}
+		show_activity(1);
 #endif
 		/*
 		 *	Check the ethernet for a new packet.  The ethernet
@@ -542,8 +456,15 @@ restart:
 		 *	Abort if ctrl-c was pressed.
 		 */
 		if (ctrlc()) {
+			/* cancel any ARP that may not have completed */
+			NetArpWaitPacketIP = 0;
+
+			net_cleanup_loop();
 			eth_halt();
 			puts("\nAbort\n");
+			/* include a debug print as well incase the debug
+			   messages are directed to stderr */
+			debug_cond(DEBUG_INT_STATE, "--- NetLoop Abort!\n");
 			goto done;
 		}
 
@@ -571,19 +492,21 @@ restart:
 			}
 #endif /* CONFIG_SYS_FAULT_ECHO_LINK_DOWN, ... */
 #endif /* CONFIG_MII, ... */
+			debug_cond(DEBUG_INT_STATE, "--- NetLoop timeout\n");
 			x = timeHandler;
 			timeHandler = (thand_f *)0;
 			(*x)();
 		}
 
 
-		switch (NetState) {
+		switch (net_state) {
 
 		case NETLOOP_RESTART:
 			NetRestarted = 1;
 			goto restart;
 
 		case NETLOOP_SUCCESS:
+			net_cleanup_loop();
 			if (NetBootFileXferSize > 0) {
 				char buf[20];
 				printf("Bytes transferred = %ld (%lx hex)\n",
@@ -597,17 +520,23 @@ restart:
 			}
 			eth_halt();
 			ret = NetBootFileXferSize;
+			debug_cond(DEBUG_INT_STATE, "--- NetLoop Success!\n");
 			goto done;
 
 		case NETLOOP_FAIL:
+			net_cleanup_loop();
+			debug_cond(DEBUG_INT_STATE, "--- NetLoop Fail!\n");
 			goto done;
+
+		case NETLOOP_CONTINUE:
+			continue;
 		}
 	}
 
 done:
 #ifdef CONFIG_CMD_TFTPPUT
 	/* Clear out the handlers */
-	NetSetHandler(NULL);
+	net_set_udp_handler(NULL);
 	net_set_icmp_handler(NULL);
 #endif
 	return ret;
@@ -618,14 +547,7 @@ done:
 static void
 startAgainTimeout(void)
 {
-	NetState = NETLOOP_RESTART;
-}
-
-static void
-startAgainHandler(uchar *pkt, unsigned dest, IPaddr_t sip,
-		  unsigned src, unsigned len)
-{
-	/* Totally ignore the packet */
+	net_set_state(NETLOOP_RESTART);
 }
 
 void NetStartAgain(void)
@@ -649,7 +571,7 @@ void NetStartAgain(void)
 
 	if ((!retry_forever) && (NetTryCount >= retrycnt)) {
 		eth_halt();
-		NetState = NETLOOP_FAIL;
+		net_set_state(NETLOOP_FAIL);
 		return;
 	}
 
@@ -664,12 +586,12 @@ void NetStartAgain(void)
 		NetRestartWrap = 0;
 		if (NetDevExists) {
 			NetSetTimeout(10000UL, startAgainTimeout);
-			NetSetHandler(startAgainHandler);
+			net_set_udp_handler(NULL);
 		} else {
-			NetState = NETLOOP_FAIL;
+			net_set_state(NETLOOP_FAIL);
 		}
 	} else {
-		NetState = NETLOOP_RESTART;
+		net_set_state(NETLOOP_RESTART);
 	}
 }
 
@@ -678,10 +600,38 @@ void NetStartAgain(void)
  *	Miscelaneous bits.
  */
 
-void
-NetSetHandler(rxhand_f *f)
+static void dummy_handler(uchar *pkt, unsigned dport,
+			IPaddr_t sip, unsigned sport,
+			unsigned len)
+{
+}
+
+rxhand_f *net_get_udp_handler(void)
+{
+	return udp_packet_handler;
+}
+
+void net_set_udp_handler(rxhand_f *f)
+{
+	debug_cond(DEBUG_INT_STATE, "--- NetLoop UDP handler set (%p)\n", f);
+	if (f == NULL)
+		udp_packet_handler = dummy_handler;
+	else
+		udp_packet_handler = f;
+}
+
+rxhand_f *net_get_arp_handler(void)
 {
-	packetHandler = f;
+	return arp_packet_handler;
+}
+
+void net_set_arp_handler(rxhand_f *f)
+{
+	debug_cond(DEBUG_INT_STATE, "--- NetLoop ARP handler set (%p)\n", f);
+	if (f == NULL)
+		arp_packet_handler = dummy_handler;
+	else
+		arp_packet_handler = f;
 }
 
 #ifdef CONFIG_CMD_TFTPPUT
@@ -695,25 +645,29 @@ void
 NetSetTimeout(ulong iv, thand_f *f)
 {
 	if (iv == 0) {
+		debug_cond(DEBUG_INT_STATE,
+			"--- NetLoop timeout handler cancelled\n");
 		timeHandler = (thand_f *)0;
 	} else {
+		debug_cond(DEBUG_INT_STATE,
+			"--- NetLoop timeout handler set (%p)\n", f);
 		timeHandler = f;
 		timeStart = get_timer(0);
 		timeDelta = iv;
 	}
 }
 
-
-void
-NetSendPacket(volatile uchar *pkt, int len)
-{
-	(void) eth_send(pkt, len);
-}
-
-int
-NetSendUDPPacket(uchar *ether, IPaddr_t dest, int dport, int sport, int len)
+int NetSendUDPPacket(uchar *ether, IPaddr_t dest, int dport, int sport,
+		int payload_len)
 {
 	uchar *pkt;
+	int eth_hdr_size;
+	int pkt_hdr_size;
+
+	/* make sure the NetTxPacket is initialized (NetInit() was called) */
+	assert(NetTxPacket != NULL);
+	if (NetTxPacket == NULL)
+		return -1;
 
 	/* convert to new style broadcast */
 	if (dest == 0)
@@ -723,487 +677,37 @@ NetSendUDPPacket(uchar *ether, IPaddr_t dest, int dport, int sport, int len)
 	if (dest == 0xFFFFFFFF)
 		ether = NetBcastAddr;
 
-	/*
-	 * if MAC address was not discovered yet, save the packet and do
-	 * an ARP request
-	 */
-	if (memcmp(ether, NetEtherNullAddr, 6) == 0) {
+	pkt = (uchar *)NetTxPacket;
+
+	eth_hdr_size = NetSetEther(pkt, ether, PROT_IP);
+	pkt += eth_hdr_size;
+	net_set_udp_header(pkt, dest, dport, sport, payload_len);
+	pkt_hdr_size = eth_hdr_size + IP_UDP_HDR_SIZE;
 
-		debug("sending ARP for %08x\n", dest);
+	/* if MAC address was not discovered yet, do an ARP request */
+	if (memcmp(ether, NetEtherNullAddr, 6) == 0) {
+		debug_cond(DEBUG_DEV_PKT, "sending ARP for %pI4\n", &dest);
 
+		/* save the ip and eth addr for the packet to send after arp */
 		NetArpWaitPacketIP = dest;
 		NetArpWaitPacketMAC = ether;
 
-		pkt = NetArpWaitTxPacket;
-		pkt += NetSetEther(pkt, NetArpWaitPacketMAC, PROT_IP);
-
-		NetSetIP(pkt, dest, dport, sport, len);
-		memcpy(pkt + IP_HDR_SIZE, (uchar *)NetTxPacket +
-		       (pkt - (uchar *)NetArpWaitTxPacket) + IP_HDR_SIZE, len);
-
 		/* size of the waiting packet */
-		NetArpWaitTxPacketSize = (pkt - NetArpWaitTxPacket) +
-			IP_HDR_SIZE + len;
+		NetArpWaitTxPacketSize = pkt_hdr_size + payload_len;
 
 		/* and do the ARP request */
 		NetArpWaitTry = 1;
 		NetArpWaitTimerStart = get_timer(0);
 		ArpRequest();
 		return 1;	/* waiting */
+	} else {
+		debug_cond(DEBUG_DEV_PKT, "sending UDP to %pI4/%pM\n",
+			&dest, ether);
+		NetSendPacket(NetTxPacket, pkt_hdr_size + payload_len);
+		return 0;	/* transmitted */
 	}
-
-	debug("sending UDP to %08x/%pM\n", dest, ether);
-
-	pkt = (uchar *)NetTxPacket;
-	pkt += NetSetEther(pkt, ether, PROT_IP);
-	NetSetIP(pkt, dest, dport, sport, len);
-	(void) eth_send(NetTxPacket, (pkt - NetTxPacket) + IP_HDR_SIZE + len);
-
-	return 0;	/* transmitted */
-}
-
-#if defined(CONFIG_CMD_PING)
-static ushort PingSeqNo;
-
-int PingSend(void)
-{
-	static uchar mac[6];
-	volatile IP_t *ip;
-	volatile ushort *s;
-	uchar *pkt;
-
-	/* XXX always send arp request */
-
-	memcpy(mac, NetEtherNullAddr, 6);
-
-	debug("sending ARP for %08x\n", NetPingIP);
-
-	NetArpWaitPacketIP = NetPingIP;
-	NetArpWaitPacketMAC = mac;
-
-	pkt = NetArpWaitTxPacket;
-	pkt += NetSetEther(pkt, mac, PROT_IP);
-
-	ip = (volatile IP_t *)pkt;
-
-	/*
-	 * Construct an IP and ICMP header.
-	 * (need to set no fragment bit - XXX)
-	 */
-	/* IP_HDR_SIZE / 4 (not including UDP) */
-	ip->ip_hl_v  = 0x45;
-	ip->ip_tos   = 0;
-	ip->ip_len   = htons(IP_HDR_SIZE_NO_UDP + 8);
-	ip->ip_id    = htons(NetIPID++);
-	ip->ip_off   = htons(IP_FLAGS_DFRAG);	/* Don't fragment */
-	ip->ip_ttl   = 255;
-	ip->ip_p     = 0x01;		/* ICMP */
-	ip->ip_sum   = 0;
-	/* already in network byte order */
-	NetCopyIP((void *)&ip->ip_src, &NetOurIP);
-	/* - "" - */
-	NetCopyIP((void *)&ip->ip_dst, &NetPingIP);
-	ip->ip_sum   = ~NetCksum((uchar *)ip, IP_HDR_SIZE_NO_UDP / 2);
-
-	s = &ip->udp_src;		/* XXX ICMP starts here */
-	s[0] = htons(0x0800);		/* echo-request, code */
-	s[1] = 0;			/* checksum */
-	s[2] = 0;			/* identifier */
-	s[3] = htons(PingSeqNo++);	/* sequence number */
-	s[1] = ~NetCksum((uchar *)s, 8/2);
-
-	/* size of the waiting packet */
-	NetArpWaitTxPacketSize =
-		(pkt - NetArpWaitTxPacket) + IP_HDR_SIZE_NO_UDP + 8;
-
-	/* and do the ARP request */
-	NetArpWaitTry = 1;
-	NetArpWaitTimerStart = get_timer(0);
-	ArpRequest();
-	return 1;	/* waiting */
-}
-
-static void
-PingTimeout(void)
-{
-	eth_halt();
-	NetState = NETLOOP_FAIL;	/* we did not get the reply */
-}
-
-static void
-PingHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src,
-	    unsigned len)
-{
-	if (sip != NetPingIP)
-		return;
-
-	NetState = NETLOOP_SUCCESS;
-}
-
-static void PingStart(void)
-{
-	printf("Using %s device\n", eth_get_name());
-	NetSetTimeout(10000UL, PingTimeout);
-	NetSetHandler(PingHandler);
-
-	PingSend();
-}
-#endif
-
-#if defined(CONFIG_CMD_CDP)
-
-#define CDP_DEVICE_ID_TLV		0x0001
-#define CDP_ADDRESS_TLV			0x0002
-#define CDP_PORT_ID_TLV			0x0003
-#define CDP_CAPABILITIES_TLV		0x0004
-#define CDP_VERSION_TLV			0x0005
-#define CDP_PLATFORM_TLV		0x0006
-#define CDP_NATIVE_VLAN_TLV		0x000a
-#define CDP_APPLIANCE_VLAN_TLV		0x000e
-#define CDP_TRIGGER_TLV			0x000f
-#define CDP_POWER_CONSUMPTION_TLV	0x0010
-#define CDP_SYSNAME_TLV			0x0014
-#define CDP_SYSOBJECT_TLV		0x0015
-#define CDP_MANAGEMENT_ADDRESS_TLV	0x0016
-
-#define CDP_TIMEOUT			250UL	/* one packet every 250ms */
-
-static int CDPSeq;
-static int CDPOK;
-
-ushort CDPNativeVLAN;
-ushort CDPApplianceVLAN;
-
-static const uchar CDP_SNAP_hdr[8] = { 0xAA, 0xAA, 0x03, 0x00, 0x00, 0x0C, 0x20,
-				       0x00 };
-
-static ushort CDP_compute_csum(const uchar *buff, ushort len)
-{
-	ushort csum;
-	int     odd;
-	ulong   result = 0;
-	ushort  leftover;
-	ushort *p;
-
-	if (len > 0) {
-		odd = 1 & (ulong)buff;
-		if (odd) {
-			result = *buff << 8;
-			len--;
-			buff++;
-		}
-		while (len > 1) {
-			p = (ushort *)buff;
-			result += *p++;
-			buff = (uchar *)p;
-			if (result & 0x80000000)
-				result = (result & 0xFFFF) + (result >> 16);
-			len -= 2;
-		}
-		if (len) {
-			leftover = (signed short)(*(const signed char *)buff);
-			/* CISCO SUCKS big time! (and blows too):
-			 * CDP uses the IP checksum algorithm with a twist;
-			 * for the last byte it *sign* extends and sums.
-			 */
-			result = (result & 0xffff0000) |
-				 ((result + leftover) & 0x0000ffff);
-		}
-		while (result >> 16)
-			result = (result & 0xFFFF) + (result >> 16);
-
-		if (odd)
-			result = ((result >> 8) & 0xff) |
-				 ((result & 0xff) << 8);
-	}
-
-	/* add up 16-bit and 17-bit words for 17+c bits */
-	result = (result & 0xffff) + (result >> 16);
-	/* add up 16-bit and 2-bit for 16+c bit */
-	result = (result & 0xffff) + (result >> 16);
-	/* add up carry.. */
-	result = (result & 0xffff) + (result >> 16);
-
-	/* negate */
-	csum = ~(ushort)result;
-
-	/* run time endian detection */
-	if (csum != htons(csum))	/* little endian */
-		csum = htons(csum);
-
-	return csum;
 }
 
-int CDPSendTrigger(void)
-{
-	volatile uchar *pkt;
-	volatile ushort *s;
-	volatile ushort *cp;
-	Ethernet_t *et;
-	int len;
-	ushort chksum;
-#if	defined(CONFIG_CDP_DEVICE_ID) || defined(CONFIG_CDP_PORT_ID)   || \
-	defined(CONFIG_CDP_VERSION)   || defined(CONFIG_CDP_PLATFORM)
-	char buf[32];
-#endif
-
-	pkt = NetTxPacket;
-	et = (Ethernet_t *)pkt;
-
-	/* NOTE: trigger sent not on any VLAN */
-
-	/* form ethernet header */
-	memcpy(et->et_dest, NetCDPAddr, 6);
-	memcpy(et->et_src, NetOurEther, 6);
-
-	pkt += ETHER_HDR_SIZE;
-
-	/* SNAP header */
-	memcpy((uchar *)pkt, CDP_SNAP_hdr, sizeof(CDP_SNAP_hdr));
-	pkt += sizeof(CDP_SNAP_hdr);
-
-	/* CDP header */
-	*pkt++ = 0x02;				/* CDP version 2 */
-	*pkt++ = 180;				/* TTL */
-	s = (volatile ushort *)pkt;
-	cp = s;
-	/* checksum (0 for later calculation) */
-	*s++ = htons(0);
-
-	/* CDP fields */
-#ifdef CONFIG_CDP_DEVICE_ID
-	*s++ = htons(CDP_DEVICE_ID_TLV);
-	*s++ = htons(CONFIG_CDP_DEVICE_ID);
-	sprintf(buf, CONFIG_CDP_DEVICE_ID_PREFIX "%pm", NetOurEther);
-	memcpy((uchar *)s, buf, 16);
-	s += 16 / 2;
-#endif
-
-#ifdef CONFIG_CDP_PORT_ID
-	*s++ = htons(CDP_PORT_ID_TLV);
-	memset(buf, 0, sizeof(buf));
-	sprintf(buf, CONFIG_CDP_PORT_ID, eth_get_dev_index());
-	len = strlen(buf);
-	if (len & 1)	/* make it even */
-		len++;
-	*s++ = htons(len + 4);
-	memcpy((uchar *)s, buf, len);
-	s += len / 2;
-#endif
-
-#ifdef CONFIG_CDP_CAPABILITIES
-	*s++ = htons(CDP_CAPABILITIES_TLV);
-	*s++ = htons(8);
-	*(ulong *)s = htonl(CONFIG_CDP_CAPABILITIES);
-	s += 2;
-#endif
-
-#ifdef CONFIG_CDP_VERSION
-	*s++ = htons(CDP_VERSION_TLV);
-	memset(buf, 0, sizeof(buf));
-	strcpy(buf, CONFIG_CDP_VERSION);
-	len = strlen(buf);
-	if (len & 1)	/* make it even */
-		len++;
-	*s++ = htons(len + 4);
-	memcpy((uchar *)s, buf, len);
-	s += len / 2;
-#endif
-
-#ifdef CONFIG_CDP_PLATFORM
-	*s++ = htons(CDP_PLATFORM_TLV);
-	memset(buf, 0, sizeof(buf));
-	strcpy(buf, CONFIG_CDP_PLATFORM);
-	len = strlen(buf);
-	if (len & 1)	/* make it even */
-		len++;
-	*s++ = htons(len + 4);
-	memcpy((uchar *)s, buf, len);
-	s += len / 2;
-#endif
-
-#ifdef CONFIG_CDP_TRIGGER
-	*s++ = htons(CDP_TRIGGER_TLV);
-	*s++ = htons(8);
-	*(ulong *)s = htonl(CONFIG_CDP_TRIGGER);
-	s += 2;
-#endif
-
-#ifdef CONFIG_CDP_POWER_CONSUMPTION
-	*s++ = htons(CDP_POWER_CONSUMPTION_TLV);
-	*s++ = htons(6);
-	*s++ = htons(CONFIG_CDP_POWER_CONSUMPTION);
-#endif
-
-	/* length of ethernet packet */
-	len = (uchar *)s - ((uchar *)NetTxPacket + ETHER_HDR_SIZE);
-	et->et_protlen = htons(len);
-
-	len = ETHER_HDR_SIZE + sizeof(CDP_SNAP_hdr);
-	chksum = CDP_compute_csum((uchar *)NetTxPacket + len,
-				  (uchar *)s - (NetTxPacket + len));
-	if (chksum == 0)
-		chksum = 0xFFFF;
-	*cp = htons(chksum);
-
-	(void) eth_send(NetTxPacket, (uchar *)s - NetTxPacket);
-	return 0;
-}
-
-static void
-CDPTimeout(void)
-{
-	CDPSeq++;
-
-	if (CDPSeq < 3) {
-		NetSetTimeout(CDP_TIMEOUT, CDPTimeout);
-		CDPSendTrigger();
-		return;
-	}
-
-	/* if not OK try again */
-	if (!CDPOK)
-		NetStartAgain();
-	else
-		NetState = NETLOOP_SUCCESS;
-}
-
-static void
-CDPDummyHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src,
-		unsigned len)
-{
-	/* nothing */
-}
-
-static void
-CDPHandler(const uchar *pkt, unsigned len)
-{
-	const uchar *t;
-	const ushort *ss;
-	ushort type, tlen;
-	ushort vlan, nvlan;
-
-	/* minimum size? */
-	if (len < sizeof(CDP_SNAP_hdr) + 4)
-		goto pkt_short;
-
-	/* check for valid CDP SNAP header */
-	if (memcmp(pkt, CDP_SNAP_hdr, sizeof(CDP_SNAP_hdr)) != 0)
-		return;
-
-	pkt += sizeof(CDP_SNAP_hdr);
-	len -= sizeof(CDP_SNAP_hdr);
-
-	/* Version of CDP protocol must be >= 2 and TTL != 0 */
-	if (pkt[0] < 0x02 || pkt[1] == 0)
-		return;
-
-	/*
-	 * if version is greater than 0x02 maybe we'll have a problem;
-	 * output a warning
-	 */
-	if (pkt[0] != 0x02)
-		printf("** WARNING: CDP packet received with a protocol version %d > 2\n",
-				pkt[0] & 0xff);
-
-	if (CDP_compute_csum(pkt, len) != 0)
-		return;
-
-	pkt += 4;
-	len -= 4;
-
-	vlan = htons(-1);
-	nvlan = htons(-1);
-	while (len > 0) {
-		if (len < 4)
-			goto pkt_short;
-
-		ss = (const ushort *)pkt;
-		type = ntohs(ss[0]);
-		tlen = ntohs(ss[1]);
-		if (tlen > len)
-			goto pkt_short;
-
-		pkt += tlen;
-		len -= tlen;
-
-		ss += 2;	/* point ss to the data of the TLV */
-		tlen -= 4;
-
-		switch (type) {
-		case CDP_DEVICE_ID_TLV:
-			break;
-		case CDP_ADDRESS_TLV:
-			break;
-		case CDP_PORT_ID_TLV:
-			break;
-		case CDP_CAPABILITIES_TLV:
-			break;
-		case CDP_VERSION_TLV:
-			break;
-		case CDP_PLATFORM_TLV:
-			break;
-		case CDP_NATIVE_VLAN_TLV:
-			nvlan = *ss;
-			break;
-		case CDP_APPLIANCE_VLAN_TLV:
-			t = (const uchar *)ss;
-			while (tlen > 0) {
-				if (tlen < 3)
-					goto pkt_short;
-
-				ss = (const ushort *)(t + 1);
-
-#ifdef CONFIG_CDP_APPLIANCE_VLAN_TYPE
-				if (t[0] == CONFIG_CDP_APPLIANCE_VLAN_TYPE)
-					vlan = *ss;
-#else
-				/* XXX will this work; dunno */
-				vlan = ntohs(*ss);
-#endif
-				t += 3; tlen -= 3;
-			}
-			break;
-		case CDP_TRIGGER_TLV:
-			break;
-		case CDP_POWER_CONSUMPTION_TLV:
-			break;
-		case CDP_SYSNAME_TLV:
-			break;
-		case CDP_SYSOBJECT_TLV:
-			break;
-		case CDP_MANAGEMENT_ADDRESS_TLV:
-			break;
-		}
-	}
-
-	CDPApplianceVLAN = vlan;
-	CDPNativeVLAN = nvlan;
-
-	CDPOK = 1;
-	return;
-
- pkt_short:
-	printf("** CDP packet is too short\n");
-	return;
-}
-
-static void CDPStart(void)
-{
-	printf("Using %s device\n", eth_get_name());
-	CDPSeq = 0;
-	CDPOK = 0;
-
-	CDPNativeVLAN = htons(-1);
-	CDPApplianceVLAN = htons(-1);
-
-	NetSetTimeout(CDP_TIMEOUT, CDPTimeout);
-	NetSetHandler(CDPDummyHandler);
-
-	CDPSendTrigger();
-}
-#endif
-
 #ifdef CONFIG_IP_DEFRAG
 /*
  * This function collects fragments in a single packet, according
@@ -1223,7 +727,7 @@ static void CDPStart(void)
 static struct rpc_t rpc_specimen;
 #define IP_PKTSIZE (CONFIG_NET_MAXDEFRAG + sizeof(rpc_specimen.u.reply))
 
-#define IP_MAXUDP (IP_PKTSIZE - IP_HDR_SIZE_NO_UDP)
+#define IP_MAXUDP (IP_PKTSIZE - IP_HDR_SIZE)
 
 /*
  * this is the packet being assembled, either data or frag control.
@@ -1237,22 +741,22 @@ struct hole {
 	u16 unused;
 };
 
-static IP_t *__NetDefragment(IP_t *ip, int *lenp)
+static struct ip_udp_hdr *__NetDefragment(struct ip_udp_hdr *ip, int *lenp)
 {
-	static uchar pkt_buff[IP_PKTSIZE] __attribute__((aligned(PKTALIGN)));
+	static uchar pkt_buff[IP_PKTSIZE] __aligned(PKTALIGN);
 	static u16 first_hole, total_len;
 	struct hole *payload, *thisfrag, *h, *newh;
-	IP_t *localip = (IP_t *)pkt_buff;
+	struct ip_udp_hdr *localip = (struct ip_udp_hdr *)pkt_buff;
 	uchar *indata = (uchar *)ip;
 	int offset8, start, len, done = 0;
 	u16 ip_off = ntohs(ip->ip_off);
 
 	/* payload starts after IP header, this fragment is in there */
-	payload = (struct hole *)(pkt_buff + IP_HDR_SIZE_NO_UDP);
+	payload = (struct hole *)(pkt_buff + IP_HDR_SIZE);
 	offset8 =  (ip_off & IP_OFFS);
 	thisfrag = payload + offset8;
 	start = offset8 * 8;
-	len = ntohs(ip->ip_len) - IP_HDR_SIZE_NO_UDP;
+	len = ntohs(ip->ip_len) - IP_HDR_SIZE;
 
 	if (start + len > IP_MAXUDP) /* fragment extends too far */
 		return NULL;
@@ -1265,7 +769,7 @@ static IP_t *__NetDefragment(IP_t *ip, int *lenp)
 		payload[0].prev_hole = 0;
 		first_hole = 0;
 		/* any IP header will work, copy the first we received */
-		memcpy(localip, ip, IP_HDR_SIZE_NO_UDP);
+		memcpy(localip, ip, IP_HDR_SIZE);
 	}
 
 	/*
@@ -1348,16 +852,16 @@ static IP_t *__NetDefragment(IP_t *ip, int *lenp)
 	}
 
 	/* finally copy this fragment and possibly return whole packet */
-	memcpy((uchar *)thisfrag, indata + IP_HDR_SIZE_NO_UDP, len);
+	memcpy((uchar *)thisfrag, indata + IP_HDR_SIZE, len);
 	if (!done)
 		return NULL;
 
 	localip->ip_len = htons(total_len);
-	*lenp = total_len + IP_HDR_SIZE_NO_UDP;
+	*lenp = total_len + IP_HDR_SIZE;
 	return localip;
 }
 
-static inline IP_t *NetDefragment(IP_t *ip, int *lenp)
+static inline struct ip_udp_hdr *NetDefragment(struct ip_udp_hdr *ip, int *lenp)
 {
 	u16 ip_off = ntohs(ip->ip_off);
 	if (!(ip_off & (IP_OFFS | IP_FLAGS_MFRAG)))
@@ -1367,7 +871,7 @@ static inline IP_t *NetDefragment(IP_t *ip, int *lenp)
 
 #else /* !CONFIG_IP_DEFRAG */
 
-static inline IP_t *NetDefragment(IP_t *ip, int *lenp)
+static inline struct ip_udp_hdr *NetDefragment(struct ip_udp_hdr *ip, int *lenp)
 {
 	u16 ip_off = ntohs(ip->ip_off);
 	if (!(ip_off & (IP_OFFS | IP_FLAGS_MFRAG)))
@@ -1382,9 +886,10 @@ static inline IP_t *NetDefragment(IP_t *ip, int *lenp)
  *
  * @parma ip	IP packet containing the ICMP
  */
-static void receive_icmp(IP_t *ip, int len, IPaddr_t src_ip, Ethernet_t *et)
+static void receive_icmp(struct ip_udp_hdr *ip, int len,
+			IPaddr_t src_ip, struct ethernet_hdr *et)
 {
-	ICMP_t *icmph = (ICMP_t *)&ip->udp_src;
+	struct icmp_hdr *icmph = (struct icmp_hdr *)&ip->udp_src;
 
 	switch (icmph->type) {
 	case ICMP_REDIRECT:
@@ -1393,41 +898,10 @@ static void receive_icmp(IP_t *ip, int len, IPaddr_t src_ip, Ethernet_t *et)
 		printf(" ICMP Host Redirect to %pI4 ",
 			&icmph->un.gateway);
 		break;
+	default:
 #if defined(CONFIG_CMD_PING)
-	case ICMP_ECHO_REPLY:
-		/*
-			* IP header OK.  Pass the packet to the
-			* current handler.
-			*/
-		/*
-		 * XXX point to ip packet - should this use
-		 * packet_icmp_handler?
-		 */
-		(*packetHandler)((uchar *)ip, 0, src_ip, 0, 0);
-		break;
-	case ICMP_ECHO_REQUEST:
-		debug("Got ICMP ECHO REQUEST, return %d bytes\n",
-			ETHER_HDR_SIZE + len);
-
-		memcpy(&et->et_dest[0], &et->et_src[0], 6);
-		memcpy(&et->et_src[0], NetOurEther, 6);
-
-		ip->ip_sum = 0;
-		ip->ip_off = 0;
-		NetCopyIP((void *)&ip->ip_dst, &ip->ip_src);
-		NetCopyIP((void *)&ip->ip_src, &NetOurIP);
-		ip->ip_sum = ~NetCksum((uchar *)ip,
-					IP_HDR_SIZE_NO_UDP >> 1);
-
-		icmph->type = ICMP_ECHO_REPLY;
-		icmph->checksum = 0;
-		icmph->checksum = ~NetCksum((uchar *)icmph,
-			(len - IP_HDR_SIZE_NO_UDP) >> 1);
-		(void) eth_send((uchar *)et,
-				ETHER_HDR_SIZE + len);
-		break;
+		ping_receive(et, ip, len);
 #endif
-	default:
 #ifdef CONFIG_CMD_TFTPPUT
 		if (packet_icmp_handler)
 			packet_icmp_handler(icmph->type, icmph->code,
@@ -1439,25 +913,23 @@ static void receive_icmp(IP_t *ip, int len, IPaddr_t src_ip, Ethernet_t *et)
 }
 
 void
-NetReceive(volatile uchar *inpkt, int len)
+NetReceive(uchar *inpkt, int len)
 {
-	Ethernet_t *et;
-	IP_t	*ip;
-	ARP_t	*arp;
-	IPaddr_t tmp;
+	struct ethernet_hdr *et;
+	struct ip_udp_hdr *ip;
+	IPaddr_t dst_ip;
 	IPaddr_t src_ip;
-	int	x;
-	uchar *pkt;
+	int eth_proto;
 #if defined(CONFIG_CMD_CDP)
 	int iscdp;
 #endif
 	ushort cti = 0, vlanid = VLAN_NONE, myvlanid, mynvlanid;
 
-	debug("packet received\n");
+	debug_cond(DEBUG_NET_PKT, "packet received\n");
 
 	NetRxPacket = inpkt;
 	NetRxPacketLen = len;
-	et = (Ethernet_t *)inpkt;
+	et = (struct ethernet_hdr *)inpkt;
 
 	/* too small packet? */
 	if (len < ETHER_HDR_SIZE)
@@ -1472,7 +944,7 @@ NetReceive(volatile uchar *inpkt, int len)
 
 #if defined(CONFIG_CMD_CDP)
 	/* keep track if packet is CDP */
-	iscdp = memcmp(et->et_dest, NetCDPAddr, 6) == 0;
+	iscdp = is_cdp_packet(et->et_dest);
 #endif
 
 	myvlanid = ntohs(NetOurVLAN);
@@ -1482,27 +954,28 @@ NetReceive(volatile uchar *inpkt, int len)
 	if (mynvlanid == (ushort)-1)
 		mynvlanid = VLAN_NONE;
 
-	x = ntohs(et->et_protlen);
+	eth_proto = ntohs(et->et_protlen);
 
-	debug("packet received\n");
-
-	if (x < 1514) {
+	if (eth_proto < 1514) {
+		struct e802_hdr *et802 = (struct e802_hdr *)et;
 		/*
-		 *	Got a 802 packet.  Check the other protocol field.
+		 *	Got a 802.2 packet.  Check the other protocol field.
+		 *	XXX VLAN over 802.2+SNAP not implemented!
 		 */
-		x = ntohs(et->et_prot);
+		eth_proto = ntohs(et802->et_prot);
 
-		ip = (IP_t *)(inpkt + E802_HDR_SIZE);
+		ip = (struct ip_udp_hdr *)(inpkt + E802_HDR_SIZE);
 		len -= E802_HDR_SIZE;
 
-	} else if (x != PROT_VLAN) {	/* normal packet */
-		ip = (IP_t *)(inpkt + ETHER_HDR_SIZE);
+	} else if (eth_proto != PROT_VLAN) {	/* normal packet */
+		ip = (struct ip_udp_hdr *)(inpkt + ETHER_HDR_SIZE);
 		len -= ETHER_HDR_SIZE;
 
 	} else {			/* VLAN packet */
-		VLAN_Ethernet_t *vet = (VLAN_Ethernet_t *)et;
+		struct vlan_ethernet_hdr *vet =
+			(struct vlan_ethernet_hdr *)et;
 
-		debug("VLAN packet received\n");
+		debug_cond(DEBUG_NET_PKT, "VLAN packet received\n");
 
 		/* too small packet? */
 		if (len < VLAN_ETHER_HDR_SIZE)
@@ -1518,17 +991,17 @@ NetReceive(volatile uchar *inpkt, int len)
 
 		cti = ntohs(vet->vet_tag);
 		vlanid = cti & VLAN_IDMASK;
-		x = ntohs(vet->vet_type);
+		eth_proto = ntohs(vet->vet_type);
 
-		ip = (IP_t *)(inpkt + VLAN_ETHER_HDR_SIZE);
+		ip = (struct ip_udp_hdr *)(inpkt + VLAN_ETHER_HDR_SIZE);
 		len -= VLAN_ETHER_HDR_SIZE;
 	}
 
-	debug("Receive from protocol 0x%x\n", x);
+	debug_cond(DEBUG_NET_PKT, "Receive from protocol 0x%x\n", eth_proto);
 
 #if defined(CONFIG_CMD_CDP)
 	if (iscdp) {
-		CDPHandler((uchar *)ip, len);
+		cdp_receive((uchar *)ip, len);
 		return;
 	}
 #endif
@@ -1541,141 +1014,33 @@ NetReceive(volatile uchar *inpkt, int len)
 			return;
 	}
 
-	switch (x) {
+	switch (eth_proto) {
 
 	case PROT_ARP:
-		/*
-		 * We have to deal with two types of ARP packets:
-		 * - REQUEST packets will be answered by sending  our
-		 *   IP address - if we know it.
-		 * - REPLY packates are expected only after we asked
-		 *   for the TFTP server's or the gateway's ethernet
-		 *   address; so if we receive such a packet, we set
-		 *   the server ethernet address
-		 */
-		debug("Got ARP\n");
-
-		arp = (ARP_t *)ip;
-		if (len < ARP_HDR_SIZE) {
-			printf("bad length %d < %d\n", len, ARP_HDR_SIZE);
-			return;
-		}
-		if (ntohs(arp->ar_hrd) != ARP_ETHER)
-			return;
-		if (ntohs(arp->ar_pro) != PROT_IP)
-			return;
-		if (arp->ar_hln != 6)
-			return;
-		if (arp->ar_pln != 4)
-			return;
-
-		if (NetOurIP == 0)
-			return;
-
-		if (NetReadIP(&arp->ar_data[16]) != NetOurIP)
-			return;
-
-		switch (ntohs(arp->ar_op)) {
-		case ARPOP_REQUEST:
-			/* reply with our IP address */
-			debug("Got ARP REQUEST, return our IP\n");
-			pkt = (uchar *)et;
-			pkt += NetSetEther(pkt, et->et_src, PROT_ARP);
-			arp->ar_op = htons(ARPOP_REPLY);
-			memcpy(&arp->ar_data[10], &arp->ar_data[0], 6);
-			NetCopyIP(&arp->ar_data[16], &arp->ar_data[6]);
-			memcpy(&arp->ar_data[0], NetOurEther, 6);
-			NetCopyIP(&arp->ar_data[6], &NetOurIP);
-			(void) eth_send((uchar *)et,
-					(pkt - (uchar *)et) + ARP_HDR_SIZE);
-			return;
-
-		case ARPOP_REPLY:		/* arp reply */
-			/* are we waiting for a reply */
-			if (!NetArpWaitPacketIP || !NetArpWaitPacketMAC)
-				break;
-
-#ifdef CONFIG_KEEP_SERVERADDR
-			if (NetServerIP == NetArpWaitPacketIP) {
-				char buf[20];
-				sprintf(buf, "%pM", arp->ar_data);
-				setenv("serveraddr", buf);
-			}
-#endif
-
-			debug("Got ARP REPLY, set server/gtwy eth addr (%pM)\n",
-				arp->ar_data);
-
-			tmp = NetReadIP(&arp->ar_data[6]);
-
-			/* matched waiting packet's address */
-			if (tmp == NetArpWaitReplyIP) {
-				debug("Got it\n");
-				/* save address for later use */
-				memcpy(NetArpWaitPacketMAC,
-				       &arp->ar_data[0], 6);
-
-#ifdef CONFIG_NETCONSOLE
-				(*packetHandler)(0, 0, 0, 0, 0);
-#endif
-				/* modify header, and transmit it */
-				memcpy(((Ethernet_t *)NetArpWaitTxPacket)->et_dest, NetArpWaitPacketMAC, 6);
-				(void) eth_send(NetArpWaitTxPacket,
-						NetArpWaitTxPacketSize);
-
-				/* no arp request pending now */
-				NetArpWaitPacketIP = 0;
-				NetArpWaitTxPacketSize = 0;
-				NetArpWaitPacketMAC = NULL;
-
-			}
-			return;
-		default:
-			debug("Unexpected ARP opcode 0x%x\n",
-			      ntohs(arp->ar_op));
-			return;
-		}
+		ArpReceive(et, ip, len);
 		break;
 
 #ifdef CONFIG_CMD_RARP
 	case PROT_RARP:
-		debug("Got RARP\n");
-		arp = (ARP_t *)ip;
-		if (len < ARP_HDR_SIZE) {
-			printf("bad length %d < %d\n", len, ARP_HDR_SIZE);
-			return;
-		}
-
-		if ((ntohs(arp->ar_op) != RARPOP_REPLY) ||
-			(ntohs(arp->ar_hrd) != ARP_ETHER)   ||
-			(ntohs(arp->ar_pro) != PROT_IP)     ||
-			(arp->ar_hln != 6) || (arp->ar_pln != 4)) {
-
-			puts("invalid RARP header\n");
-		} else {
-			NetCopyIP(&NetOurIP, &arp->ar_data[16]);
-			if (NetServerIP == 0)
-				NetCopyIP(&NetServerIP, &arp->ar_data[6]);
-			memcpy(NetServerEther, &arp->ar_data[0], 6);
-
-			(*packetHandler)(0, 0, 0, 0, 0);
-		}
+		rarp_receive(ip, len);
 		break;
 #endif
 	case PROT_IP:
-		debug("Got IP\n");
+		debug_cond(DEBUG_NET_PKT, "Got IP\n");
 		/* Before we start poking the header, make sure it is there */
-		if (len < IP_HDR_SIZE) {
-			debug("len bad %d < %lu\n", len, (ulong)IP_HDR_SIZE);
+		if (len < IP_UDP_HDR_SIZE) {
+			debug("len bad %d < %lu\n", len,
+				(ulong)IP_UDP_HDR_SIZE);
 			return;
 		}
 		/* Check the packet length */
 		if (len < ntohs(ip->ip_len)) {
-			printf("len bad %d < %d\n", len, ntohs(ip->ip_len));
+			debug("len bad %d < %d\n", len, ntohs(ip->ip_len));
 			return;
 		}
 		len = ntohs(ip->ip_len);
-		debug("len=%d, v=%02x\n", len, ip->ip_hl_v & 0xff);
+		debug_cond(DEBUG_NET_PKT, "len=%d, v=%02x\n",
+			len, ip->ip_hl_v & 0xff);
 
 		/* Can't deal with anything except IPv4 */
 		if ((ip->ip_hl_v & 0xf0) != 0x40)
@@ -1684,15 +1049,15 @@ NetReceive(volatile uchar *inpkt, int len)
 		if ((ip->ip_hl_v & 0x0f) > 0x05)
 			return;
 		/* Check the Checksum of the header */
-		if (!NetCksumOk((uchar *)ip, IP_HDR_SIZE_NO_UDP / 2)) {
-			puts("checksum bad\n");
+		if (!NetCksumOk((uchar *)ip, IP_HDR_SIZE / 2)) {
+			debug("checksum bad\n");
 			return;
 		}
 		/* If it is not for us, ignore it */
-		tmp = NetReadIP(&ip->ip_dst);
-		if (NetOurIP && tmp != NetOurIP && tmp != 0xFFFFFFFF) {
+		dst_ip = NetReadIP(&ip->ip_dst);
+		if (NetOurIP && dst_ip != NetOurIP && dst_ip != 0xFFFFFFFF) {
 #ifdef CONFIG_MCAST_TFTP
-			if (Mcast_addr != tmp)
+			if (Mcast_addr != dst_ip)
 #endif
 				return;
 		}
@@ -1734,6 +1099,10 @@ NetReceive(volatile uchar *inpkt, int len)
 			return;
 		}
 
+		debug_cond(DEBUG_DEV_PKT,
+			"received UDP (to=%pI4, from=%pI4, len=%d)\n",
+			&dst_ip, &src_ip, len);
+
 #ifdef CONFIG_UDP_CHECKSUM
 		if (ip->udp_xsum != 0) {
 			ulong   xsum;
@@ -1778,19 +1147,19 @@ NetReceive(volatile uchar *inpkt, int len)
 
 
 #ifdef CONFIG_NETCONSOLE
-		nc_input_packet((uchar *)ip + IP_HDR_SIZE,
-						ntohs(ip->udp_dst),
-						ntohs(ip->udp_src),
-						ntohs(ip->udp_len) - 8);
+		nc_input_packet((uchar *)ip + IP_UDP_HDR_SIZE,
+					ntohs(ip->udp_dst),
+					ntohs(ip->udp_src),
+					ntohs(ip->udp_len) - UDP_HDR_SIZE);
 #endif
 		/*
 		 *	IP header OK.  Pass the packet to the current handler.
 		 */
-		(*packetHandler)((uchar *)ip + IP_HDR_SIZE,
-						ntohs(ip->udp_dst),
-						src_ip,
-						ntohs(ip->udp_src),
-						ntohs(ip->udp_len) - 8);
+		(*udp_packet_handler)((uchar *)ip + IP_UDP_HDR_SIZE,
+				ntohs(ip->udp_dst),
+				src_ip,
+				ntohs(ip->udp_src),
+				ntohs(ip->udp_len) - UDP_HDR_SIZE);
 		break;
 	}
 }
@@ -1855,8 +1224,8 @@ common:
 	case BOOTP:
 	case CDP:
 	case DHCP:
+	case LINKLOCAL:
 		if (memcmp(NetOurEther, "\0\0\0\0\0\0", 6) == 0) {
-			extern int eth_get_dev_index(void);
 			int num = eth_get_dev_index();
 
 			switch (num) {
@@ -1918,9 +1287,9 @@ NetEthHdrSize(void)
 }
 
 int
-NetSetEther(volatile uchar *xet, uchar * addr, uint prot)
+NetSetEther(uchar *xet, uchar * addr, uint prot)
 {
-	Ethernet_t *et = (Ethernet_t *)xet;
+	struct ethernet_hdr *et = (struct ethernet_hdr *)xet;
 	ushort myvlanid;
 
 	myvlanid = ntohs(NetOurVLAN);
@@ -1933,7 +1302,8 @@ NetSetEther(volatile uchar *xet, uchar * addr, uint prot)
 		et->et_protlen = htons(prot);
 		return ETHER_HDR_SIZE;
 	} else {
-		VLAN_Ethernet_t *vet = (VLAN_Ethernet_t *)xet;
+		struct vlan_ethernet_hdr *vet =
+			(struct vlan_ethernet_hdr *)xet;
 
 		vet->vet_vlan_type = htons(PROT_VLAN);
 		vet->vet_tag = htons((0 << 5) | (myvlanid & VLAN_IDMASK));
@@ -1942,41 +1312,72 @@ NetSetEther(volatile uchar *xet, uchar * addr, uint prot)
 	}
 }
 
-void
-NetSetIP(volatile uchar *xip, IPaddr_t dest, int dport, int sport, int len)
+int net_update_ether(struct ethernet_hdr *et, uchar *addr, uint prot)
 {
-	IP_t *ip = (IP_t *)xip;
+	ushort protlen;
 
-	/*
-	 *	If the data is an odd number of bytes, zero the
-	 *	byte after the last byte so that the checksum
-	 *	will work.
-	 */
-	if (len & 1)
-		xip[IP_HDR_SIZE + len] = 0;
+	memcpy(et->et_dest, addr, 6);
+	memcpy(et->et_src, NetOurEther, 6);
+	protlen = ntohs(et->et_protlen);
+	if (protlen == PROT_VLAN) {
+		struct vlan_ethernet_hdr *vet =
+			(struct vlan_ethernet_hdr *)et;
+		vet->vet_type = htons(prot);
+		return VLAN_ETHER_HDR_SIZE;
+	} else if (protlen > 1514) {
+		et->et_protlen = htons(prot);
+		return ETHER_HDR_SIZE;
+	} else {
+		/* 802.2 + SNAP */
+		struct e802_hdr *et802 = (struct e802_hdr *)et;
+		et802->et_prot = htons(prot);
+		return E802_HDR_SIZE;
+	}
+}
+
+void net_set_ip_header(uchar *pkt, IPaddr_t dest, IPaddr_t source)
+{
+	struct ip_udp_hdr *ip = (struct ip_udp_hdr *)pkt;
 
 	/*
-	 *	Construct an IP and UDP header.
-	 *	(need to set no fragment bit - XXX)
+	 *	Construct an IP header.
 	 */
 	/* IP_HDR_SIZE / 4 (not including UDP) */
 	ip->ip_hl_v  = 0x45;
 	ip->ip_tos   = 0;
-	ip->ip_len   = htons(IP_HDR_SIZE + len);
+	ip->ip_len   = htons(IP_HDR_SIZE);
 	ip->ip_id    = htons(NetIPID++);
 	ip->ip_off   = htons(IP_FLAGS_DFRAG);	/* Don't fragment */
 	ip->ip_ttl   = 255;
-	ip->ip_p     = 17;		/* UDP */
 	ip->ip_sum   = 0;
 	/* already in network byte order */
-	NetCopyIP((void *)&ip->ip_src, &NetOurIP);
-	/* - "" - */
+	NetCopyIP((void *)&ip->ip_src, &source);
+	/* already in network byte order */
 	NetCopyIP((void *)&ip->ip_dst, &dest);
+}
+
+void net_set_udp_header(uchar *pkt, IPaddr_t dest, int dport, int sport,
+			int len)
+{
+	struct ip_udp_hdr *ip = (struct ip_udp_hdr *)pkt;
+
+	/*
+	 *	If the data is an odd number of bytes, zero the
+	 *	byte after the last byte so that the checksum
+	 *	will work.
+	 */
+	if (len & 1)
+		pkt[IP_UDP_HDR_SIZE + len] = 0;
+
+	net_set_ip_header(pkt, dest, NetOurIP);
+	ip->ip_len   = htons(IP_UDP_HDR_SIZE + len);
+	ip->ip_p     = IPPROTO_UDP;
+	ip->ip_sum   = ~NetCksum((uchar *)ip, IP_HDR_SIZE >> 1);
+
 	ip->udp_src  = htons(sport);
 	ip->udp_dst  = htons(dport);
-	ip->udp_len  = htons(8 + len);
+	ip->udp_len  = htons(UDP_HDR_SIZE + len);
 	ip->udp_xsum = 0;
-	ip->ip_sum   = ~NetCksum((uchar *)ip, IP_HDR_SIZE_NO_UDP / 2);
 }
 
 void copy_filename(char *dst, const char *src, int size)
diff --git a/net/net_rand.c b/net/net_rand.c
new file mode 100644
index 0000000000..5387abadcf
--- /dev/null
+++ b/net/net_rand.c
@@ -0,0 +1,68 @@
+/*
+ *	Based on LiMon - BOOTP.
+ *
+ *	Copyright 1994, 1995, 2000 Neil Russell.
+ *	(See License)
+ *	Copyright 2000 Roland Borde
+ *	Copyright 2000 Paolo Scaffardi
+ *	Copyright 2000-2004 Wolfgang Denk, wd@denx.de
+ */
+
+#include <common.h>
+#include <net.h>
+#include "net_rand.h"
+
+static ulong seed1, seed2;
+
+void srand_mac(void)
+{
+	ulong tst1, tst2, m_mask;
+	ulong m_value = 0;
+	int reg;
+	unsigned char bi_enetaddr[6];
+
+	/* get our mac */
+	eth_getenv_enetaddr("ethaddr", bi_enetaddr);
+
+	debug("BootpRequest => Our Mac: ");
+	for (reg = 0; reg < 6; reg++)
+		debug("%x%c", bi_enetaddr[reg], reg == 5 ? '\n' : ':');
+
+	/* Mac-Manipulation 2 get seed1 */
+	tst1 = 0;
+	tst2 = 0;
+	for (reg = 2; reg < 6; reg++) {
+		tst1 = tst1 << 8;
+		tst1 = tst1 | bi_enetaddr[reg];
+	}
+	for (reg = 0; reg < 2; reg++) {
+		tst2 = tst2 | bi_enetaddr[reg];
+		tst2 = tst2 << 8;
+	}
+
+	seed1 = tst1^tst2;
+
+	/* Mirror seed1*/
+	m_mask = 0x1;
+	for (reg = 1; reg <= 32; reg++) {
+		m_value |= (m_mask & seed1);
+		seed1 = seed1 >> 1;
+		m_value = m_value << 1;
+	}
+	seed1 = m_value;
+	seed2 = 0xb78d0945;
+}
+
+unsigned long rand(void)
+{
+	ulong sum;
+
+	/* Random Number Generator */
+	sum = seed1 + seed2;
+	if (sum < seed1 || sum < seed2)
+		sum++;
+	seed2 = seed1;
+	seed1 = sum;
+
+	return sum;
+}
diff --git a/net/net_rand.h b/net/net_rand.h
new file mode 100644
index 0000000000..c98db64280
--- /dev/null
+++ b/net/net_rand.h
@@ -0,0 +1,26 @@
+/*
+ *	Copied from LiMon - BOOTP.
+ *
+ *	Copyright 1994, 1995, 2000 Neil Russell.
+ *	(See License)
+ *	Copyright 2000 Paolo Scaffardi
+ */
+
+#ifndef __NET_RAND_H__
+#define __NET_RAND_H__
+
+#define RAND_MAX 0xffffffff
+
+/*
+ * Seed the random number generator using the eth0 MAC address
+ */
+void srand_mac(void);
+
+/*
+ * Get a random number (after seeding with MAC address)
+ *
+ * @return random number
+ */
+unsigned long rand(void);
+
+#endif /* __NET_RAND_H__ */
diff --git a/net/nfs.c b/net/nfs.c
index b5b482c3f3..5b9976354c 100644
--- a/net/nfs.c
+++ b/net/nfs.c
@@ -33,15 +33,15 @@
 #define NFS_RETRY_COUNT 30
 #define NFS_TIMEOUT 2000UL
 
-static int fs_mounted = 0;
-static unsigned long rpc_id = 0;
+static int fs_mounted;
+static unsigned long rpc_id;
 static int nfs_offset = -1;
 static int nfs_len;
 
 static char dirfh[NFS_FHSIZE];	/* file handle of directory */
 static char filefh[NFS_FHSIZE]; /* file handle of kernel image */
 
-static int	NfsDownloadState;
+static enum net_loop_state nfs_download_state;
 static IPaddr_t NfsServerIP;
 static int	NfsSrvMountPort;
 static int	NfsSrvNfsPort;
@@ -61,14 +61,14 @@ static char *nfs_filename;
 static char *nfs_path;
 static char nfs_path_buff[2048];
 
-static __inline__ int
-store_block (uchar * src, unsigned offset, unsigned len)
+static inline int
+store_block(uchar *src, unsigned offset, unsigned len)
 {
 	ulong newsize = offset + len;
 #ifdef CONFIG_SYS_DIRECT_FLASH_NFS
 	int i, rc = 0;
 
-	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		/* start address in flash? */
 		if (load_addr + offset >= flash_info[i].start[0]) {
 			rc = 1;
@@ -77,15 +77,15 @@ store_block (uchar * src, unsigned offset, unsigned len)
 	}
 
 	if (rc) { /* Flash is destination for this packet */
-		rc = flash_write ((uchar *)src, (ulong)(load_addr+offset), len);
+		rc = flash_write((uchar *)src, (ulong)(load_addr+offset), len);
 		if (rc) {
-			flash_perror (rc);
+			flash_perror(rc);
 			return -1;
 		}
 	} else
 #endif /* CONFIG_SYS_DIRECT_FLASH_NFS */
 	{
-		(void)memcpy ((void *)(load_addr + offset), src, len);
+		(void)memcpy((void *)(load_addr + offset), src, len);
 	}
 
 	if (NetBootFileXferSize < (offset+len))
@@ -94,7 +94,7 @@ store_block (uchar * src, unsigned offset, unsigned len)
 }
 
 static char*
-basename (char *path)
+basename(char *path)
 {
 	char *fname;
 
@@ -110,11 +110,11 @@ basename (char *path)
 }
 
 static char*
-dirname (char *path)
+dirname(char *path)
 {
 	char *fname;
 
-	fname = basename (path);
+	fname = basename(path);
 	--fname;
 	*fname = '\0';
 	return path;
@@ -123,14 +123,14 @@ dirname (char *path)
 /**************************************************************************
 RPC_ADD_CREDENTIALS - Add RPC authentication/verifier entries
 **************************************************************************/
-static long *rpc_add_credentials (long *p)
+static long *rpc_add_credentials(long *p)
 {
 	int hl;
 	int hostnamelen;
 	char hostname[256];
 
-	strcpy (hostname, "");
-	hostnamelen=strlen (hostname);
+	strcpy(hostname, "");
+	hostnamelen = strlen(hostname);
 
 	/* Here's the executive summary on authentication requirements of the
 	 * various NFS server implementations:	Linux accepts both AUTH_NONE
@@ -148,10 +148,9 @@ static long *rpc_add_credentials (long *p)
 	*p++ = htonl(hl+20);		/* auth length */
 	*p++ = htonl(0);		/* stamp */
 	*p++ = htonl(hostnamelen);	/* hostname string */
-	if (hostnamelen & 3) {
+	if (hostnamelen & 3)
 		*(p + hostnamelen / 4) = 0; /* add zero padding */
-	}
-	memcpy (p, hostname, hostnamelen);
+	memcpy(p, hostname, hostnamelen);
 	p += hl / 4;
 	*p++ = 0;			/* uid */
 	*p++ = 0;			/* gid */
@@ -168,7 +167,7 @@ static long *rpc_add_credentials (long *p)
 RPC_LOOKUP - Lookup RPC Port numbers
 **************************************************************************/
 static void
-rpc_req (int rpc_prog, int rpc_proc, uint32_t *data, int datalen)
+rpc_req(int rpc_prog, int rpc_proc, uint32_t *data, int datalen)
 {
 	struct rpc_t pkt;
 	unsigned long id;
@@ -186,11 +185,12 @@ rpc_req (int rpc_prog, int rpc_proc, uint32_t *data, int datalen)
 	p = (uint32_t *)&(pkt.u.call.data);
 
 	if (datalen)
-		memcpy ((char *)p, (char *)data, datalen*sizeof(uint32_t));
+		memcpy((char *)p, (char *)data, datalen*sizeof(uint32_t));
 
 	pktlen = (char *)p + datalen*sizeof(uint32_t) - (char *)&pkt;
 
-	memcpy ((char *)NetTxPacket + NetEthHdrSize() + IP_HDR_SIZE, (char *)&pkt, pktlen);
+	memcpy((char *)NetTxPacket + NetEthHdrSize() + IP_UDP_HDR_SIZE,
+		(char *)&pkt, pktlen);
 
 	if (rpc_prog == PROG_PORTMAP)
 		sport = SUNRPC_PORT;
@@ -199,14 +199,15 @@ rpc_req (int rpc_prog, int rpc_proc, uint32_t *data, int datalen)
 	else
 		sport = NfsSrvNfsPort;
 
-	NetSendUDPPacket (NetServerEther, NfsServerIP, sport, NfsOurPort, pktlen);
+	NetSendUDPPacket(NetServerEther, NfsServerIP, sport, NfsOurPort,
+		pktlen);
 }
 
 /**************************************************************************
 RPC_LOOKUP - Lookup RPC Port numbers
 **************************************************************************/
 static void
-rpc_lookup_req (int prog, int ver)
+rpc_lookup_req(int prog, int ver)
 {
 	uint32_t data[16];
 
@@ -217,56 +218,56 @@ rpc_lookup_req (int prog, int ver)
 	data[6] = htonl(17);	/* IP_UDP */
 	data[7] = 0;
 
-	rpc_req (PROG_PORTMAP, PORTMAP_GETPORT, data, 8);
+	rpc_req(PROG_PORTMAP, PORTMAP_GETPORT, data, 8);
 }
 
 /**************************************************************************
 NFS_MOUNT - Mount an NFS Filesystem
 **************************************************************************/
 static void
-nfs_mount_req (char *path)
+nfs_mount_req(char *path)
 {
 	uint32_t data[1024];
 	uint32_t *p;
 	int len;
 	int pathlen;
 
-	pathlen = strlen (path);
+	pathlen = strlen(path);
 
 	p = &(data[0]);
 	p = (uint32_t *)rpc_add_credentials((long *)p);
 
 	*p++ = htonl(pathlen);
-	if (pathlen & 3) *(p + pathlen / 4) = 0;
-	memcpy (p, path, pathlen);
+	if (pathlen & 3)
+		*(p + pathlen / 4) = 0;
+	memcpy(p, path, pathlen);
 	p += (pathlen + 3) / 4;
 
 	len = (uint32_t *)p - (uint32_t *)&(data[0]);
 
-	rpc_req (PROG_MOUNT, MOUNT_ADDENTRY, data, len);
+	rpc_req(PROG_MOUNT, MOUNT_ADDENTRY, data, len);
 }
 
 /**************************************************************************
 NFS_UMOUNTALL - Unmount all our NFS Filesystems on the Server
 **************************************************************************/
 static void
-nfs_umountall_req (void)
+nfs_umountall_req(void)
 {
 	uint32_t data[1024];
 	uint32_t *p;
 	int len;
 
-	if ((NfsSrvMountPort == -1) || (!fs_mounted)) {
+	if ((NfsSrvMountPort == -1) || (!fs_mounted))
 		/* Nothing mounted, nothing to umount */
 		return;
-	}
 
 	p = &(data[0]);
-	p = (uint32_t *)rpc_add_credentials ((long *)p);
+	p = (uint32_t *)rpc_add_credentials((long *)p);
 
 	len = (uint32_t *)p - (uint32_t *)&(data[0]);
 
-	rpc_req (PROG_MOUNT, MOUNT_UMOUNTALL, data, len);
+	rpc_req(PROG_MOUNT, MOUNT_UMOUNTALL, data, len);
 }
 
 /***************************************************************************
@@ -277,65 +278,66 @@ nfs_umountall_req (void)
  * so that inside the nfs() function a recursion can be done.
  **************************************************************************/
 static void
-nfs_readlink_req (void)
+nfs_readlink_req(void)
 {
 	uint32_t data[1024];
 	uint32_t *p;
 	int len;
 
 	p = &(data[0]);
-	p = (uint32_t *)rpc_add_credentials ((long *)p);
+	p = (uint32_t *)rpc_add_credentials((long *)p);
 
-	memcpy (p, filefh, NFS_FHSIZE);
+	memcpy(p, filefh, NFS_FHSIZE);
 	p += (NFS_FHSIZE / 4);
 
 	len = (uint32_t *)p - (uint32_t *)&(data[0]);
 
-	rpc_req (PROG_NFS, NFS_READLINK, data, len);
+	rpc_req(PROG_NFS, NFS_READLINK, data, len);
 }
 
 /**************************************************************************
 NFS_LOOKUP - Lookup Pathname
 **************************************************************************/
 static void
-nfs_lookup_req (char *fname)
+nfs_lookup_req(char *fname)
 {
 	uint32_t data[1024];
 	uint32_t *p;
 	int len;
 	int fnamelen;
 
-	fnamelen = strlen (fname);
+	fnamelen = strlen(fname);
 
 	p = &(data[0]);
-	p = (uint32_t *)rpc_add_credentials ((long *)p);
+	p = (uint32_t *)rpc_add_credentials((long *)p);
 
-	memcpy (p, dirfh, NFS_FHSIZE);
+	memcpy(p, dirfh, NFS_FHSIZE);
 	p += (NFS_FHSIZE / 4);
 	*p++ = htonl(fnamelen);
-	if (fnamelen & 3) *(p + fnamelen / 4) = 0;
-	memcpy (p, fname, fnamelen);
+	if (fnamelen & 3)
+		*(p + fnamelen / 4) = 0;
+	memcpy(p, fname, fnamelen);
 	p += (fnamelen + 3) / 4;
 
 	len = (uint32_t *)p - (uint32_t *)&(data[0]);
 
-	rpc_req (PROG_NFS, NFS_LOOKUP, data, len);
+	rpc_req(PROG_NFS, NFS_LOOKUP, data, len);
 }
 
 /**************************************************************************
 NFS_READ - Read File on NFS Server
 **************************************************************************/
 static void
-nfs_read_req (int offset, int readlen)
+nfs_read_req(int offset, int readlen)
 {
 	uint32_t data[1024];
 	uint32_t *p;
 	int len;
 
 	p = &(data[0]);
-	p = (uint32_t *)rpc_add_credentials ((long *)p);
+	p = (uint32_t *)rpc_add_credentials((long *)p);
 
-	memcpy (p, filefh, NFS_FHSIZE);
+	memcpy(p, filefh, NFS_FHSIZE);
 	p += (NFS_FHSIZE / 4);
 	*p++ = htonl(offset);
 	*p++ = htonl(readlen);
@@ -343,7 +345,7 @@ nfs_read_req (int offset, int readlen)
 
 	len = (uint32_t *)p - (uint32_t *)&(data[0]);
 
-	rpc_req (PROG_NFS, NFS_READ, data, len);
+	rpc_req(PROG_NFS, NFS_READ, data, len);
 }
 
 /**************************************************************************
@@ -351,31 +353,31 @@ RPC request dispatcher
 **************************************************************************/
 
 static void
-NfsSend (void)
+NfsSend(void)
 {
 	debug("%s\n", __func__);
 
 	switch (NfsState) {
 	case STATE_PRCLOOKUP_PROG_MOUNT_REQ:
-		rpc_lookup_req (PROG_MOUNT, 1);
+		rpc_lookup_req(PROG_MOUNT, 1);
 		break;
 	case STATE_PRCLOOKUP_PROG_NFS_REQ:
-		rpc_lookup_req (PROG_NFS, 2);
+		rpc_lookup_req(PROG_NFS, 2);
 		break;
 	case STATE_MOUNT_REQ:
-		nfs_mount_req (nfs_path);
+		nfs_mount_req(nfs_path);
 		break;
 	case STATE_UMOUNT_REQ:
-		nfs_umountall_req ();
+		nfs_umountall_req();
 		break;
 	case STATE_LOOKUP_REQ:
-		nfs_lookup_req (nfs_filename);
+		nfs_lookup_req(nfs_filename);
 		break;
 	case STATE_READ_REQ:
-		nfs_read_req (nfs_offset, nfs_len);
+		nfs_read_req(nfs_offset, nfs_len);
 		break;
 	case STATE_READLINK_REQ:
-		nfs_readlink_req ();
+		nfs_readlink_req();
 		break;
 	}
 }
@@ -385,11 +387,11 @@ Handlers for the reply from server
 **************************************************************************/
 
 static int
-rpc_lookup_reply (int prog, uchar *pkt, unsigned len)
+rpc_lookup_reply(int prog, uchar *pkt, unsigned len)
 {
 	struct rpc_t rpc_pkt;
 
-	memcpy ((unsigned char *)&rpc_pkt, pkt, len);
+	memcpy((unsigned char *)&rpc_pkt, pkt, len);
 
 	debug("%s\n", __func__);
 
@@ -398,9 +400,8 @@ rpc_lookup_reply (int prog, uchar *pkt, unsigned len)
 
 	if (rpc_pkt.u.reply.rstatus  ||
 	    rpc_pkt.u.reply.verifier ||
-	    rpc_pkt.u.reply.astatus) {
+	    rpc_pkt.u.reply.astatus)
 		return -1;
-	}
 
 	switch (prog) {
 	case PROG_MOUNT:
@@ -415,13 +416,13 @@ rpc_lookup_reply (int prog, uchar *pkt, unsigned len)
 }
 
 static int
-nfs_mount_reply (uchar *pkt, unsigned len)
+nfs_mount_reply(uchar *pkt, unsigned len)
 {
 	struct rpc_t rpc_pkt;
 
 	debug("%s\n", __func__);
 
-	memcpy ((unsigned char *)&rpc_pkt, pkt, len);
+	memcpy((unsigned char *)&rpc_pkt, pkt, len);
 
 	if (ntohl(rpc_pkt.u.reply.id) != rpc_id)
 		return -1;
@@ -429,48 +430,46 @@ nfs_mount_reply (uchar *pkt, unsigned len)
 	if (rpc_pkt.u.reply.rstatus  ||
 	    rpc_pkt.u.reply.verifier ||
 	    rpc_pkt.u.reply.astatus  ||
-	    rpc_pkt.u.reply.data[0]) {
+	    rpc_pkt.u.reply.data[0])
 		return -1;
-	}
 
 	fs_mounted = 1;
-	memcpy (dirfh, rpc_pkt.u.reply.data + 1, NFS_FHSIZE);
+	memcpy(dirfh, rpc_pkt.u.reply.data + 1, NFS_FHSIZE);
 
 	return 0;
 }
 
 static int
-nfs_umountall_reply (uchar *pkt, unsigned len)
+nfs_umountall_reply(uchar *pkt, unsigned len)
 {
 	struct rpc_t rpc_pkt;
 
 	debug("%s\n", __func__);
 
-	memcpy ((unsigned char *)&rpc_pkt, pkt, len);
+	memcpy((unsigned char *)&rpc_pkt, pkt, len);
 
 	if (ntohl(rpc_pkt.u.reply.id) != rpc_id)
 		return -1;
 
 	if (rpc_pkt.u.reply.rstatus  ||
 	    rpc_pkt.u.reply.verifier ||
-	    rpc_pkt.u.reply.astatus) {
+	    rpc_pkt.u.reply.astatus)
 		return -1;
-	}
 
 	fs_mounted = 0;
-	memset (dirfh, 0, sizeof(dirfh));
+	memset(dirfh, 0, sizeof(dirfh));
 
 	return 0;
 }
 
 static int
-nfs_lookup_reply (uchar *pkt, unsigned len)
+nfs_lookup_reply(uchar *pkt, unsigned len)
 {
 	struct rpc_t rpc_pkt;
 
 	debug("%s\n", __func__);
 
-	memcpy ((unsigned char *)&rpc_pkt, pkt, len);
+	memcpy((unsigned char *)&rpc_pkt, pkt, len);
 
 	if (ntohl(rpc_pkt.u.reply.id) != rpc_id)
 		return -1;
@@ -478,24 +477,23 @@ nfs_lookup_reply (uchar *pkt, unsigned len)
 	if (rpc_pkt.u.reply.rstatus  ||
 	    rpc_pkt.u.reply.verifier ||
 	    rpc_pkt.u.reply.astatus  ||
-	    rpc_pkt.u.reply.data[0]) {
+	    rpc_pkt.u.reply.data[0])
 		return -1;
-	}
 
-	memcpy (filefh, rpc_pkt.u.reply.data + 1, NFS_FHSIZE);
+	memcpy(filefh, rpc_pkt.u.reply.data + 1, NFS_FHSIZE);
 
 	return 0;
 }
 
 static int
-nfs_readlink_reply (uchar *pkt, unsigned len)
+nfs_readlink_reply(uchar *pkt, unsigned len)
 {
 	struct rpc_t rpc_pkt;
 	int rlen;
 
 	debug("%s\n", __func__);
 
-	memcpy ((unsigned char *)&rpc_pkt, pkt, len);
+	memcpy((unsigned char *)&rpc_pkt, pkt, len);
 
 	if (ntohl(rpc_pkt.u.reply.id) != rpc_id)
 		return -1;
@@ -503,34 +501,34 @@ nfs_readlink_reply (uchar *pkt, unsigned len)
 	if (rpc_pkt.u.reply.rstatus  ||
 	    rpc_pkt.u.reply.verifier ||
 	    rpc_pkt.u.reply.astatus  ||
-	    rpc_pkt.u.reply.data[0]) {
+	    rpc_pkt.u.reply.data[0])
 		return -1;
-	}
 
-	rlen = ntohl (rpc_pkt.u.reply.data[1]); /* new path length */
+	rlen = ntohl(rpc_pkt.u.reply.data[1]); /* new path length */
 
 	if (*((char *)&(rpc_pkt.u.reply.data[2])) != '/') {
 		int pathlen;
-		strcat (nfs_path, "/");
+		strcat(nfs_path, "/");
 		pathlen = strlen(nfs_path);
-		memcpy (nfs_path+pathlen, (uchar *)&(rpc_pkt.u.reply.data[2]), rlen);
+		memcpy(nfs_path + pathlen, (uchar *)&(rpc_pkt.u.reply.data[2]),
+			rlen);
 		nfs_path[pathlen + rlen] = 0;
 	} else {
-		memcpy (nfs_path, (uchar *)&(rpc_pkt.u.reply.data[2]), rlen);
+		memcpy(nfs_path, (uchar *)&(rpc_pkt.u.reply.data[2]), rlen);
 		nfs_path[rlen] = 0;
 	}
 	return 0;
 }
 
 static int
-nfs_read_reply (uchar *pkt, unsigned len)
+nfs_read_reply(uchar *pkt, unsigned len)
 {
 	struct rpc_t rpc_pkt;
 	int rlen;
 
 	debug("%s\n", __func__);
 
-	memcpy ((uchar *)&rpc_pkt, pkt, sizeof(rpc_pkt.u.reply));
+	memcpy((uchar *)&rpc_pkt, pkt, sizeof(rpc_pkt.u.reply));
 
 	if (ntohl(rpc_pkt.u.reply.id) != rpc_id)
 		return -1;
@@ -539,24 +537,22 @@ nfs_read_reply (uchar *pkt, unsigned len)
 	    rpc_pkt.u.reply.verifier ||
 	    rpc_pkt.u.reply.astatus  ||
 	    rpc_pkt.u.reply.data[0]) {
-		if (rpc_pkt.u.reply.rstatus) {
+		if (rpc_pkt.u.reply.rstatus)
 			return -9999;
-		}
-		if (rpc_pkt.u.reply.astatus) {
+		if (rpc_pkt.u.reply.astatus)
 			return -9999;
-		}
-		return -ntohl(rpc_pkt.u.reply.data[0]);;
+		return -ntohl(rpc_pkt.u.reply.data[0]);
 	}
 
-	if ((nfs_offset!=0) && !((nfs_offset) % (NFS_READ_SIZE/2*10*HASHES_PER_LINE))) {
-		puts ("\n\t ");
-	}
-	if (!(nfs_offset % ((NFS_READ_SIZE/2)*10))) {
-		putc ('#');
-	}
+	if ((nfs_offset != 0) && !((nfs_offset) %
+			(NFS_READ_SIZE / 2 * 10 * HASHES_PER_LINE)))
+		puts("\n\t ");
+	if (!(nfs_offset % ((NFS_READ_SIZE / 2) * 10)))
+		putc('#');
 
 	rlen = ntohl(rpc_pkt.u.reply.data[18]);
-	if ( store_block ((uchar *)pkt+sizeof(rpc_pkt.u.reply), nfs_offset, rlen) )
+	if (store_block((uchar *)pkt + sizeof(rpc_pkt.u.reply),
+			nfs_offset, rlen))
 		return -9999;
 
 	return rlen;
@@ -567,15 +563,15 @@ Interfaces of U-BOOT
 **************************************************************************/
 
 static void
-NfsTimeout (void)
+NfsTimeout(void)
 {
-	if ( ++NfsTimeoutCount > NFS_RETRY_COUNT ) {
-		puts ("\nRetry count exceeded; starting again\n");
-		NetStartAgain ();
+	if (++NfsTimeoutCount > NFS_RETRY_COUNT) {
+		puts("\nRetry count exceeded; starting again\n");
+		NetStartAgain();
 	} else {
 		puts("T ");
-		NetSetTimeout (NFS_TIMEOUT, NfsTimeout);
-		NfsSend ();
+		NetSetTimeout(NFS_TIMEOUT, NfsTimeout);
+		NfsSend();
 	}
 }
 
@@ -586,86 +582,87 @@ NfsHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src, unsigned len)
 
 	debug("%s\n", __func__);
 
-	if (dest != NfsOurPort) return;
+	if (dest != NfsOurPort)
+		return;
 
 	switch (NfsState) {
 	case STATE_PRCLOOKUP_PROG_MOUNT_REQ:
-		rpc_lookup_reply (PROG_MOUNT, pkt, len);
+		rpc_lookup_reply(PROG_MOUNT, pkt, len);
 		NfsState = STATE_PRCLOOKUP_PROG_NFS_REQ;
-		NfsSend ();
+		NfsSend();
 		break;
 
 	case STATE_PRCLOOKUP_PROG_NFS_REQ:
-		rpc_lookup_reply (PROG_NFS, pkt, len);
+		rpc_lookup_reply(PROG_NFS, pkt, len);
 		NfsState = STATE_MOUNT_REQ;
-		NfsSend ();
+		NfsSend();
 		break;
 
 	case STATE_MOUNT_REQ:
 		if (nfs_mount_reply(pkt, len)) {
-			puts ("*** ERROR: Cannot mount\n");
+			puts("*** ERROR: Cannot mount\n");
 			/* just to be sure... */
 			NfsState = STATE_UMOUNT_REQ;
-			NfsSend ();
+			NfsSend();
 		} else {
 			NfsState = STATE_LOOKUP_REQ;
-			NfsSend ();
+			NfsSend();
 		}
 		break;
 
 	case STATE_UMOUNT_REQ:
 		if (nfs_umountall_reply(pkt, len)) {
-			puts ("*** ERROR: Cannot umount\n");
-			NetState = NETLOOP_FAIL;
+			puts("*** ERROR: Cannot umount\n");
+			net_set_state(NETLOOP_FAIL);
 		} else {
-			puts ("\ndone\n");
-			NetState = NfsDownloadState;
+			puts("\ndone\n");
+			net_set_state(nfs_download_state);
 		}
 		break;
 
 	case STATE_LOOKUP_REQ:
 		if (nfs_lookup_reply(pkt, len)) {
-			puts ("*** ERROR: File lookup fail\n");
+			puts("*** ERROR: File lookup fail\n");
 			NfsState = STATE_UMOUNT_REQ;
-			NfsSend ();
+			NfsSend();
 		} else {
 			NfsState = STATE_READ_REQ;
 			nfs_offset = 0;
 			nfs_len = NFS_READ_SIZE;
-			NfsSend ();
+			NfsSend();
 		}
 		break;
 
 	case STATE_READLINK_REQ:
 		if (nfs_readlink_reply(pkt, len)) {
-			puts ("*** ERROR: Symlink fail\n");
+			puts("*** ERROR: Symlink fail\n");
 			NfsState = STATE_UMOUNT_REQ;
-			NfsSend ();
+			NfsSend();
 		} else {
 			debug("Symlink --> %s\n", nfs_path);
-			nfs_filename = basename (nfs_path);
-			nfs_path     = dirname (nfs_path);
+			nfs_filename = basename(nfs_path);
+			nfs_path     = dirname(nfs_path);
 
 			NfsState = STATE_MOUNT_REQ;
-			NfsSend ();
+			NfsSend();
 		}
 		break;
 
 	case STATE_READ_REQ:
-		rlen = nfs_read_reply (pkt, len);
-		NetSetTimeout (NFS_TIMEOUT, NfsTimeout);
+		rlen = nfs_read_reply(pkt, len);
+		NetSetTimeout(NFS_TIMEOUT, NfsTimeout);
 		if (rlen > 0) {
 			nfs_offset += rlen;
-			NfsSend ();
-		}
-		else if ((rlen == -NFSERR_ISDIR)||(rlen == -NFSERR_INVAL)) {
+			NfsSend();
+		} else if ((rlen == -NFSERR_ISDIR) || (rlen == -NFSERR_INVAL)) {
 			/* symbolic link */
 			NfsState = STATE_READLINK_REQ;
-			NfsSend ();
+			NfsSend();
 		} else {
-			if ( ! rlen ) NfsDownloadState = NETLOOP_SUCCESS;
+			if (!rlen)
+				nfs_download_state = NETLOOP_SUCCESS;
 			NfsState = STATE_UMOUNT_REQ;
-			NfsSend ();
+			NfsSend();
 		}
 		break;
 	}
@@ -673,17 +670,17 @@ NfsHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src, unsigned len)
 
 
 void
-NfsStart (void)
+NfsStart(void)
 {
 	debug("%s\n", __func__);
-	NfsDownloadState = NETLOOP_FAIL;
+	nfs_download_state = NETLOOP_FAIL;
 
 	NfsServerIP = NetServerIP;
 	nfs_path = (char *)nfs_path_buff;
 
 	if (nfs_path == NULL) {
-		NetState = NETLOOP_FAIL;
-		puts ("*** ERROR: Fail allocate memory\n");
+		net_set_state(NETLOOP_FAIL);
+		puts("*** ERROR: Fail allocate memory\n");
 		return;
 	}
 
@@ -692,29 +689,29 @@ NfsStart (void)
 			NetOurIP & 0xFF,
 			(NetOurIP >>  8) & 0xFF,
 			(NetOurIP >> 16) & 0xFF,
-			(NetOurIP >> 24) & 0xFF	);
-		strcpy (nfs_path, default_filename);
+			(NetOurIP >> 24) & 0xFF);
+		strcpy(nfs_path, default_filename);
 
-		printf ("*** Warning: no boot file name; using '%s'\n",
+		printf("*** Warning: no boot file name; using '%s'\n",
 			nfs_path);
 	} else {
-		char *p=BootFile;
+		char *p = BootFile;
 
-		p = strchr (p, ':');
+		p = strchr(p, ':');
 
 		if (p != NULL) {
-			NfsServerIP = string_to_ip (BootFile);
+			NfsServerIP = string_to_ip(BootFile);
 			++p;
-			strcpy (nfs_path, p);
+			strcpy(nfs_path, p);
 		} else {
-			strcpy (nfs_path, BootFile);
+			strcpy(nfs_path, BootFile);
 		}
 	}
 
-	nfs_filename = basename (nfs_path);
-	nfs_path     = dirname (nfs_path);
+	nfs_filename = basename(nfs_path);
+	nfs_path     = dirname(nfs_path);
 
-	printf ("Using %s device\n", eth_get_name());
+	printf("Using %s device\n", eth_get_name());
 
 	printf("File transfer via NFS from server %pI4"
 		"; our IP address is %pI4", &NfsServerIP, &NetOurIP);
@@ -725,19 +722,20 @@ NfsStart (void)
 		IPaddr_t ServerNet  = NetServerIP & NetOurSubnetMask;
 
 		if (OurNet != ServerNet)
-			printf("; sending through gateway %pI4", &NetOurGatewayIP);
+			printf("; sending through gateway %pI4",
+				&NetOurGatewayIP);
 	}
-	printf ("\nFilename '%s/%s'.", nfs_path, nfs_filename);
+	printf("\nFilename '%s/%s'.", nfs_path, nfs_filename);
 
 	if (NetBootFileSize) {
-		printf (" Size is 0x%x Bytes = ", NetBootFileSize<<9);
-		print_size (NetBootFileSize<<9, "");
+		printf(" Size is 0x%x Bytes = ", NetBootFileSize<<9);
+		print_size(NetBootFileSize<<9, "");
 	}
-	printf ("\nLoad address: 0x%lx\n"
+	printf("\nLoad address: 0x%lx\n"
 		"Loading: *\b", load_addr);
 
-	NetSetTimeout (NFS_TIMEOUT, NfsTimeout);
-	NetSetHandler (NfsHandler);
+	NetSetTimeout(NFS_TIMEOUT, NfsTimeout);
+	net_set_udp_handler(NfsHandler);
 
 	NfsTimeoutCount = 0;
 	NfsState = STATE_PRCLOOKUP_PROG_MOUNT_REQ;
@@ -747,7 +745,7 @@ NfsStart (void)
 	NfsOurPort = 1000;
 
 	/* zero out server ether in case the server ip has changed */
-	memset (NetServerEther, 0, 6);
+	memset(NetServerEther, 0, 6);
 
-	NfsSend ();
+	NfsSend();
 }
diff --git a/net/nfs.h b/net/nfs.h
index de8a0c64c0..a5a1b432e6 100644
--- a/net/nfs.h
+++ b/net/nfs.h
@@ -72,7 +72,7 @@ struct rpc_t {
 		} reply;
 	} u;
 };
-extern void	NfsStart (void);	/* Begin NFS */
+extern void NfsStart(void);	/* Begin NFS */
 
 
 /**********************************************************************/
diff --git a/net/ping.c b/net/ping.c
new file mode 100644
index 0000000000..0710b9228d
--- /dev/null
+++ b/net/ping.c
@@ -0,0 +1,115 @@
+/*
+ *	Copied from Linux Monitor (LiMon) - Networking.
+ *
+ *	Copyright 1994 - 2000 Neil Russell.
+ *	(See License)
+ *	Copyright 2000 Roland Borde
+ *	Copyright 2000 Paolo Scaffardi
+ *	Copyright 2000-2002 Wolfgang Denk, wd@denx.de
+ */
+
+#include "ping.h"
+#include "arp.h"
+
+static ushort PingSeqNo;
+
+/* The ip address to ping */
+IPaddr_t NetPingIP;
+
+static void set_icmp_header(uchar *pkt, IPaddr_t dest)
+{
+	/*
+	 *	Construct an IP and ICMP header.
+	 */
+	struct ip_hdr *ip = (struct ip_hdr *)pkt;
+	struct icmp_hdr *icmp = (struct icmp_hdr *)(pkt + IP_HDR_SIZE);
+
+	net_set_ip_header(pkt, dest, NetOurIP);
+
+	ip->ip_len   = htons(IP_ICMP_HDR_SIZE);
+	ip->ip_p     = IPPROTO_ICMP;
+	ip->ip_sum   = ~NetCksum((uchar *)ip, IP_HDR_SIZE >> 1);
+
+	icmp->type = ICMP_ECHO_REQUEST;
+	icmp->code = 0;
+	icmp->checksum = 0;
+	icmp->un.echo.id = 0;
+	icmp->un.echo.sequence = htons(PingSeqNo++);
+	icmp->checksum = ~NetCksum((uchar *)icmp, ICMP_HDR_SIZE	>> 1);
+}
+
+static int ping_send(void)
+{
+	uchar *pkt;
+	int eth_hdr_size;
+
+	/* XXX always send arp request */
+
+	debug_cond(DEBUG_DEV_PKT, "sending ARP for %pI4\n", &NetPingIP);
+
+	NetArpWaitPacketIP = NetPingIP;
+
+	eth_hdr_size = NetSetEther(NetTxPacket, NetEtherNullAddr, PROT_IP);
+	pkt = (uchar *)NetTxPacket + eth_hdr_size;
+
+	set_icmp_header(pkt, NetPingIP);
+
+	/* size of the waiting packet */
+	NetArpWaitTxPacketSize = eth_hdr_size + IP_ICMP_HDR_SIZE;
+
+	/* and do the ARP request */
+	NetArpWaitTry = 1;
+	NetArpWaitTimerStart = get_timer(0);
+	ArpRequest();
+	return 1;	/* waiting */
+}
+
+static void ping_timeout(void)
+{
+	eth_halt();
+	net_set_state(NETLOOP_FAIL);	/* we did not get the reply */
+}
+
+void ping_start(void)
+{
+	printf("Using %s device\n", eth_get_name());
+	NetSetTimeout(10000UL, ping_timeout);
+
+	ping_send();
+}
+
+void ping_receive(struct ethernet_hdr *et, struct ip_udp_hdr *ip, int len)
+{
+	struct icmp_hdr *icmph = (struct icmp_hdr *)&ip->udp_src;
+	IPaddr_t src_ip;
+	int eth_hdr_size;
+
+	switch (icmph->type) {
+	case ICMP_ECHO_REPLY:
+		src_ip = NetReadIP((void *)&ip->ip_src);
+		if (src_ip == NetPingIP)
+			net_set_state(NETLOOP_SUCCESS);
+		return;
+	case ICMP_ECHO_REQUEST:
+		eth_hdr_size = net_update_ether(et, et->et_src, PROT_IP);
+
+		debug_cond(DEBUG_DEV_PKT, "Got ICMP ECHO REQUEST, return "
+			"%d bytes\n", eth_hdr_size + len);
+
+		ip->ip_sum = 0;
+		ip->ip_off = 0;
+		NetCopyIP((void *)&ip->ip_dst, &ip->ip_src);
+		NetCopyIP((void *)&ip->ip_src, &NetOurIP);
+		ip->ip_sum = ~NetCksum((uchar *)ip,
+				       IP_HDR_SIZE >> 1);
+
+		icmph->type = ICMP_ECHO_REPLY;
+		icmph->checksum = 0;
+		icmph->checksum = ~NetCksum((uchar *)icmph,
+			(len - IP_HDR_SIZE) >> 1);
+		NetSendPacket((uchar *)et, eth_hdr_size + len);
+		return;
+/*	default:
+		return;*/
+	}
+}
diff --git a/net/ping.h b/net/ping.h
new file mode 100644
index 0000000000..fd8d8d9778
--- /dev/null
+++ b/net/ping.h
@@ -0,0 +1,34 @@
+/*
+ *	Copied from Linux Monitor (LiMon) - Networking.
+ *
+ *	Copyright 1994 - 2000 Neil Russell.
+ *	(See License)
+ *	Copyright 2000 Roland Borde
+ *	Copyright 2000 Paolo Scaffardi
+ *	Copyright 2000-2002 Wolfgang Denk, wd@denx.de
+ */
+
+#if defined(CONFIG_CMD_PING)
+
+#ifndef __PING_H__
+#define __PING_H__
+
+#include <common.h>
+#include <net.h>
+
+/*
+ * Initialize ping (beginning of netloop)
+ */
+void ping_start(void);
+
+/*
+ * Deal with the receipt of a ping packet
+ *
+ * @param et Ethernet header in packet
+ * @param ip IP header in the same packet
+ * @param len Packet length
+ */
+void ping_receive(struct ethernet_hdr *et, struct ip_udp_hdr *ip, int len);
+
+#endif /* __PING_H__ */
+#endif
diff --git a/net/rarp.c b/net/rarp.c
index 097f970f44..49185b4e14 100644
--- a/net/rarp.c
+++ b/net/rarp.c
@@ -29,73 +29,88 @@
 #include "rarp.h"
 #include "tftp.h"
 
-#define TIMEOUT		5000UL	/* Milliseconds before trying BOOTP again */
+#define TIMEOUT 5000UL /* Milliseconds before trying BOOTP again */
 #ifndef	CONFIG_NET_RETRY_COUNT
-# define TIMEOUT_COUNT	5		/* # of timeouts before giving up  */
+#define TIMEOUT_COUNT 5 /* # of timeouts before giving up  */
 #else
-# define TIMEOUT_COUNT  (CONFIG_NET_RETRY_COUNT)
+#define TIMEOUT_COUNT (CONFIG_NET_RETRY_COUNT)
 #endif
 
-
-int		RarpTry;
+int RarpTry;
 
 /*
  *	Handle a RARP received packet.
  */
-static void
-RarpHandler(uchar *dummi0, unsigned dummi1, IPaddr_t sip, unsigned dummi2,
-	    unsigned dummi3)
+void rarp_receive(struct ip_udp_hdr *ip, unsigned len)
 {
-	debug("Got good RARP\n");
-	net_auto_load();
+	struct arp_hdr *arp;
+
+	debug_cond(DEBUG_NET_PKT, "Got RARP\n");
+	arp = (struct arp_hdr *)ip;
+	if (len < ARP_HDR_SIZE) {
+		printf("bad length %d < %d\n", len, ARP_HDR_SIZE);
+		return;
+	}
+
+	if ((ntohs(arp->ar_op) != RARPOP_REPLY) ||
+		(ntohs(arp->ar_hrd) != ARP_ETHER)   ||
+		(ntohs(arp->ar_pro) != PROT_IP)     ||
+		(arp->ar_hln != 6) || (arp->ar_pln != 4)) {
+
+		puts("invalid RARP header\n");
+	} else {
+		NetCopyIP(&NetOurIP, &arp->ar_data[16]);
+		if (NetServerIP == 0)
+			NetCopyIP(&NetServerIP, &arp->ar_data[6]);
+		memcpy(NetServerEther, &arp->ar_data[0], 6);
+		debug_cond(DEBUG_DEV_PKT, "Got good RARP\n");
+		net_auto_load();
+	}
 }
 
 
 /*
  *	Timeout on BOOTP request.
  */
-static void
-RarpTimeout(void)
+static void RarpTimeout(void)
 {
 	if (RarpTry >= TIMEOUT_COUNT) {
-		puts ("\nRetry count exceeded; starting again\n");
-		NetStartAgain ();
+		puts("\nRetry count exceeded; starting again\n");
+		NetStartAgain();
 	} else {
-		NetSetTimeout (TIMEOUT, RarpTimeout);
-		RarpRequest ();
+		NetSetTimeout(TIMEOUT, RarpTimeout);
+		RarpRequest();
 	}
 }
 
 
-void
-RarpRequest (void)
+void RarpRequest(void)
 {
-	int i;
-	volatile uchar *pkt;
-	ARP_t *	rarp;
+	uchar *pkt;
+	struct arp_hdr *rarp;
+	int eth_hdr_size;
 
 	printf("RARP broadcast %d\n", ++RarpTry);
 	pkt = NetTxPacket;
 
-	pkt += NetSetEther(pkt, NetBcastAddr, PROT_RARP);
+	eth_hdr_size = NetSetEther(pkt, NetBcastAddr, PROT_RARP);
+	pkt += eth_hdr_size;
 
-	rarp = (ARP_t *)pkt;
+	rarp = (struct arp_hdr *)pkt;
 
-	rarp->ar_hrd = htons (ARP_ETHER);
-	rarp->ar_pro = htons (PROT_IP);
+	rarp->ar_hrd = htons(ARP_ETHER);
+	rarp->ar_pro = htons(PROT_IP);
 	rarp->ar_hln = 6;
 	rarp->ar_pln = 4;
-	rarp->ar_op  = htons (RARPOP_REQUEST);
-	memcpy (&rarp->ar_data[0],  NetOurEther, 6);	/* source ET addr */
-	memcpy (&rarp->ar_data[6],  &NetOurIP,   4);	/* source IP addr */
-	memcpy (&rarp->ar_data[10], NetOurEther, 6);	/* dest ET addr = source ET addr ??*/
-	/* dest. IP addr set to broadcast */
-	for (i = 0; i <= 3; i++) {
-		rarp->ar_data[16 + i] = 0xff;
-	}
+	rarp->ar_op  = htons(RARPOP_REQUEST);
+	memcpy(&rarp->ar_data[0],  NetOurEther, 6);	/* source ET addr */
+	memcpy(&rarp->ar_data[6],  &NetOurIP,   4);	/* source IP addr */
+	/* dest ET addr = source ET addr ??*/
+	memcpy(&rarp->ar_data[10], NetOurEther, 6);
+	/* dest IP addr set to broadcast */
+	memset(&rarp->ar_data[16], 0xff,        4);
 
-	NetSendPacket(NetTxPacket, (pkt - NetTxPacket) + ARP_HDR_SIZE);
+	NetSendPacket(NetTxPacket, eth_hdr_size + ARP_HDR_SIZE);
 
 	NetSetTimeout(TIMEOUT, RarpTimeout);
-	NetSetHandler(RarpHandler);
 }
diff --git a/net/rarp.h b/net/rarp.h
index 0c16d46668..ebd748ea4e 100644
--- a/net/rarp.h
+++ b/net/rarp.h
@@ -21,24 +21,25 @@
  * MA 02111-1307 USA
  */
 
+#if defined(CONFIG_CMD_RARP)
 
 #ifndef __RARP_H__
 #define __RARP_H__
 
-#ifndef __NET_H__
 #include <net.h>
-#endif /* __NET_H__ */
-
 
 /**********************************************************************/
 /*
  *	Global functions and variables.
  */
 
-extern int	RarpTry;
+extern int RarpTry;
 
-extern void RarpRequest (void);	/* Send a RARP request */
+/* Process the receipt of a RARP packet */
+extern void rarp_receive(struct ip_udp_hdr *ip, unsigned len);
+extern void RarpRequest(void);	/* Send a RARP request */
 
 /**********************************************************************/
 
 #endif /* __RARP_H__ */
+#endif
diff --git a/net/sntp.c b/net/sntp.c
index 82f2fe6cd1..5de19526e6 100644
--- a/net/sntp.c
+++ b/net/sntp.c
@@ -17,7 +17,7 @@
 static int SntpOurPort;
 
 static void
-SntpSend (void)
+SntpSend(void)
 {
 	struct sntp_pkt_t pkt;
 	int pktlen = SNTP_PACKET_LEN;
@@ -25,25 +25,27 @@ SntpSend (void)
 
 	debug("%s\n", __func__);
 
-	memset (&pkt, 0, sizeof(pkt));
+	memset(&pkt, 0, sizeof(pkt));
 
 	pkt.li = NTP_LI_NOLEAP;
 	pkt.vn = NTP_VERSION;
 	pkt.mode = NTP_MODE_CLIENT;
 
-	memcpy ((char *)NetTxPacket + NetEthHdrSize() + IP_HDR_SIZE, (char *)&pkt, pktlen);
+	memcpy((char *)NetTxPacket + NetEthHdrSize() + IP_UDP_HDR_SIZE,
+		(char *)&pkt, pktlen);
 
 	SntpOurPort = 10000 + (get_timer(0) % 4096);
 	sport = NTP_SERVICE_PORT;
 
-	NetSendUDPPacket (NetServerEther, NetNtpServerIP, sport, SntpOurPort, pktlen);
+	NetSendUDPPacket(NetServerEther, NetNtpServerIP, sport, SntpOurPort,
+		pktlen);
 }
 
 static void
-SntpTimeout (void)
+SntpTimeout(void)
 {
-	puts ("Timeout\n");
-	NetState = NETLOOP_FAIL;
+	puts("Timeout\n");
+	net_set_state(NETLOOP_FAIL);
 	return;
 }
 
@@ -57,33 +59,34 @@ SntpHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src,
 
 	debug("%s\n", __func__);
 
-	if (dest != SntpOurPort) return;
+	if (dest != SntpOurPort)
+		return;
 
 	/*
 	 * As the RTC's used in U-Boot sepport second resolution only
 	 * we simply ignore the sub-second field.
 	 */
-	memcpy (&seconds, &rpktp->transmit_timestamp, sizeof(ulong));
+	memcpy(&seconds, &rpktp->transmit_timestamp, sizeof(ulong));
 
 	to_tm(ntohl(seconds) - 2208988800UL + NetTimeOffset, &tm);
 #if defined(CONFIG_CMD_DATE)
-	rtc_set (&tm);
+	rtc_set(&tm);
 #endif
-	printf ("Date: %4d-%02d-%02d Time: %2d:%02d:%02d\n",
+	printf("Date: %4d-%02d-%02d Time: %2d:%02d:%02d\n",
 		tm.tm_year, tm.tm_mon, tm.tm_mday,
 		tm.tm_hour, tm.tm_min, tm.tm_sec);
 
-	NetState = NETLOOP_SUCCESS;
+	net_set_state(NETLOOP_SUCCESS);
 }
 
 void
-SntpStart (void)
+SntpStart(void)
 {
 	debug("%s\n", __func__);
 
-	NetSetTimeout (SNTP_TIMEOUT, SntpTimeout);
-	NetSetHandler(SntpHandler);
-	memset (NetServerEther, 0, 6);
+	NetSetTimeout(SNTP_TIMEOUT, SntpTimeout);
+	net_set_udp_handler(SntpHandler);
+	memset(NetServerEther, 0, sizeof(NetServerEther));
 
-	SntpSend ();
+	SntpSend();
 }
diff --git a/net/sntp.h b/net/sntp.h
index 8a097bfa38..1d0046e94b 100644
--- a/net/sntp.h
+++ b/net/sntp.h
@@ -56,6 +56,6 @@ struct sntp_pkt_t {
 	unsigned long long transmit_timestamp;
 };
 
-extern void	SntpStart (void);	/* Begin SNTP */
+extern void SntpStart(void);	/* Begin SNTP */
 
 #endif /* __SNTP_H__ */
diff --git a/net/tftp.c b/net/tftp.c
index 7aa3e23c95..b2e08b4bfb 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -11,6 +11,9 @@
 #include <net.h>
 #include "tftp.h"
 #include "bootp.h"
+#ifdef CONFIG_SYS_DIRECT_FLASH_TFTP
+#include <flash.h>
+#endif
 
 /* Well known TFTP port # */
 #define WELL_KNOWN_PORT	69
@@ -112,10 +115,6 @@ static char default_filename[DEFAULT_NAME_LEN];
 
 static char tftp_filename[MAX_LEN];
 
-#ifdef CONFIG_SYS_DIRECT_FLASH_TFTP
-extern flash_info_t flash_info[];
-#endif
-
 /* 512 is poor choice for ethernet, MTU is typically 1500.
  * Minus eth.hdrs thats 1468.  Can get 2x better throughput with
  * almost-MTU block sizes.  At least try... fall back to 512 if need be.
@@ -137,7 +136,6 @@ static unsigned *Bitmap;
 static int PrevBitmapHole, Mapsize = MTFTP_BITMAPSIZE;
 static uchar ProhibitMcast, MasterClient;
 static uchar Multicast;
-extern IPaddr_t Mcast_addr;
 static int Mcast_port;
 static ulong TftpEndingBlock; /* can get 'last' block before done..*/
 
@@ -157,7 +155,7 @@ mcast_cleanup(void)
 
 #endif	/* CONFIG_MCAST_TFTP */
 
-static __inline__ void
+static inline void
 store_block(unsigned block, uchar *src, unsigned len)
 {
 	ulong offset = block * TftpBlkSize + TftpBlockWrapOffset;
@@ -179,11 +177,10 @@ store_block(unsigned block, uchar *src, unsigned len)
 		rc = flash_write((char *)src, (ulong)(load_addr+offset), len);
 		if (rc) {
 			flash_perror(rc);
-			NetState = NETLOOP_FAIL;
+			net_set_state(NETLOOP_FAIL);
 			return;
 		}
-	}
-	else
+	} else
 #endif /* CONFIG_SYS_DIRECT_FLASH_TFTP */
 	{
 		(void)memcpy((void *)(load_addr + offset), src, len);
@@ -303,16 +300,16 @@ static void tftp_complete(void)
 	}
 #endif
 	puts("\ndone\n");
-	NetState = NETLOOP_SUCCESS;
+	net_set_state(NETLOOP_SUCCESS);
 }
 
 static void
 TftpSend(void)
 {
 	uchar *pkt;
-	volatile uchar *xp;
-	int		len = 0;
-	volatile ushort *s;
+	uchar *xp;
+	int len = 0;
+	ushort *s;
 
 #ifdef CONFIG_MCAST_TFTP
 	/* Multicast TFTP.. non-MasterClients do not ACK data. */
@@ -325,7 +322,7 @@ TftpSend(void)
 	 *	We will always be sending some sort of packet, so
 	 *	cobble together the packet headers now.
 	 */
-	pkt = (uchar *)(NetTxPacket + NetEthHdrSize() + IP_HDR_SIZE);
+	pkt = NetTxPacket + NetEthHdrSize() + IP_UDP_HDR_SIZE;
 
 	switch (TftpState) {
 	case STATE_SEND_RRQ:
@@ -357,12 +354,14 @@ TftpSend(void)
 				0, TftpBlkSizeOption, 0);
 #ifdef CONFIG_MCAST_TFTP
 		/* Check all preconditions before even trying the option */
-		if (!ProhibitMcast
-		 && (Bitmap = malloc(Mapsize))
-		 && eth_get_dev()->mcast) {
-			free(Bitmap);
-			Bitmap = NULL;
-			pkt += sprintf((char *)pkt, "multicast%c%c", 0, 0);
+		if (!ProhibitMcast) {
+			Bitmap = malloc(Mapsize);
+			if (Bitmap && eth_get_dev()->mcast) {
+				free(Bitmap);
+				Bitmap = NULL;
+				pkt += sprintf((char *)pkt, "multicast%c%c",
+					0, 0);
+			}
 		}
 #endif /* CONFIG_MCAST_TFTP */
 		len = pkt - xp;
@@ -628,10 +627,9 @@ TftpHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src,
 			if (MasterClient && (TftpBlock >= TftpEndingBlock)) {
 				puts("\nMulticast tftp done\n");
 				mcast_cleanup();
-				NetState = NETLOOP_SUCCESS;
+				net_set_state(NETLOOP_SUCCESS);
 			}
-		}
-		else
+		} else
 #endif
 		if (len < TftpBlkSize)
 			tftp_complete();
@@ -646,7 +644,7 @@ TftpHandler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src,
 		case TFTP_ERR_ACCESS_DENIED:
 			puts("Not retrying...\n");
 			eth_halt();
-			NetState = NETLOOP_FAIL;
+			net_set_state(NETLOOP_FAIL);
 			break;
 		case TFTP_ERR_UNDEFINED:
 		case TFTP_ERR_DISK_FULL:
@@ -780,7 +778,7 @@ void TftpStart(enum proto_t protocol)
 	TftpTimeoutCountMax = TftpRRQTimeoutCountMax;
 
 	NetSetTimeout(TftpTimeoutMSecs, TftpTimeout);
-	NetSetHandler(TftpHandler);
+	net_set_udp_handler(TftpHandler);
 #ifdef CONFIG_CMD_TFTPPUT
 	net_set_icmp_handler(icmp_handler);
 #endif
@@ -842,7 +840,7 @@ TftpStartServer(void)
 #endif
 
 	TftpState = STATE_RECV_WRQ;
-	NetSetHandler(TftpHandler);
+	net_set_udp_handler(TftpHandler);
 }
 #endif /* CONFIG_CMD_TFTPSRV */
 
diff --git a/net/tftp.h b/net/tftp.h
index c51aa253c4..18e4c9c25d 100644
--- a/net/tftp.h
+++ b/net/tftp.h
@@ -19,7 +19,7 @@
 void TftpStart(enum proto_t protocol);	/* Begin TFTP get/put */
 
 #ifdef CONFIG_CMD_TFTPSRV
-extern void	TftpStartServer(void);	/* Wait for incoming TFTP put */
+extern void TftpStartServer(void);	/* Wait for incoming TFTP put */
 #endif
 
 /**********************************************************************/
diff --git a/pdl/common/Makefile b/pdl/common/Makefile
new file mode 100644
index 0000000000..527445b73a
--- /dev/null
+++ b/pdl/common/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+CPPFLAGS  += -I ../include/
+CFLAGS  += -I ../include -mno-unaligned-access
+LIB	:= $(obj)libpdl_common.o
+
+COBJS-y := packet.o pdl_channel.o pdl_channel_usb.o pdl_debug.o pdl_engine.o pdl.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/pdl/common/packet.c b/pdl/common/packet.c
new file mode 100644
index 0000000000..669d83cc52
--- /dev/null
+++ b/pdl/common/packet.c
@@ -0,0 +1,301 @@
+//#define DEBUG
+
+#include <asm/types.h>
+#include <common.h>
+#include "packet.h"
+#include "pdl_channel.h"
+#include <linux/string.h>
+#include "pdl_debug.h"
+#include "cmd_defs.h"
+#include <asm/unaligned.h>
+
+static enum {
+    PKT_IDLE = 0,
+    PKT_HEAD,
+    PKT_DATA,
+    PKT_ERROR
+} pkt_state;
+
+const static char *pdl_device_rsp[] = {
+	[ACK] =	"device ack",
+	[PACKET_ERROR] = "packet error",
+	[INVALID_CMD] = "invalid cmd",
+	[UNKNOWN_CMD] = "unknown cmd",
+	[INVALID_ADDR] = "invalid address",
+	[INVALID_BAUDRATE] = "invalid baudrate",
+	[INVALID_PARTITION] = "invalid partition",
+	[INVALID_SIZE] = "invalid size",
+	[WAIT_TIMEOUT] = "wait timeout",
+	[VERIFY_ERROR] = "verify error",
+	[CHECKSUM_ERROR] = "checksum error",
+	[OPERATION_FAILED] = "operation failed",
+	[DEVICE_ERROR] = "device error",
+	[NO_MEMORY] = "no memory",
+	[DEVICE_INCOMPATIBLE] = "device incompatible",
+	[HW_TEST_ERROR] = "hardware test error",
+	[MD5_ERROR] = "md5 error",
+	[ACK_AGAIN_ERASE] = "ack again erase",
+	[ACK_AGAIN_FLASH] = "ack again flash",
+	[MAX_RSP] = "max response",
+};
+
+static int pkt_error = 0;
+static unsigned char cmd_buf[PDL_MAX_PKT_SIZE] __attribute__((__aligned__(32)));
+static struct pdl_channel *channel;
+
+int pdl_init_packet_channel(void)
+{
+	channel = pdl_get_channel();
+	return 0;
+}
+
+/*
+  * return value: 1,   get packet ok;
+  *		0,   not a host packet;
+  *		-1, something error, check pkt_error for true cause;
+  *		-2, don't get any packet
+  */
+int pdl_get_cmd_packet(struct pdl_packet *pkt)
+{
+	u32 pkt_size = 0;
+	u32 hdrsz = sizeof(struct packet_header);
+	u32 cmd_hdrsz = sizeof(struct command_header);
+	u32 bufsz = 0, totalsz = 0;
+	int i, wait = 0;
+
+	if (!pkt) {
+		pdl_error("packet error\n");
+		return -1;
+	}
+
+	if (!channel->tstc())
+		return -2;
+
+	/* looking for HOST_PACKET_TAG 0xAE */
+	while (1) {
+		bufsz = channel->tstc();
+		if (!bufsz)
+			return -2;
+		channel->read(cmd_buf, bufsz);
+		if (cmd_buf[0] == HOST_PACKET_TAG) {
+			/*pdl_info("Found host packet tag, %u bytes\n", bufsz);*/
+			break;
+		} else {
+			pdl_dbg("Drop a %u bytes packet:", bufsz);
+			for(i = 0; i < 8; i++)
+				pdl_dbg(" %02x", cmd_buf[i]);
+			pdl_dbg("\n");
+		}
+	}
+	totalsz = bufsz;
+
+	/* is a valid packet header? */
+	if (totalsz < hdrsz) {
+		pdl_error("Invaild packet, it's too small (%u bytes)\n", totalsz);
+		pkt_state = PKT_IDLE;
+		return -2;
+	}
+
+	/* packet header check */
+	pkt_state = PKT_HEAD;
+	memcpy(&pkt_size, &cmd_buf[1], 4);
+	if (cmd_buf[5] != HOST_PACKET_FLOWID ||
+		pkt_size > PDL_MAX_PKT_SIZE ||
+		pkt_size < sizeof(u32)) {
+		pdl_error("Invalid packet, flowid 0x%x, pkt_size %u\n",
+				cmd_buf[5], pkt_size);
+		pdl_dbg("packet data:");
+		for (i = 0; i < 8; i++)
+			pdl_dbg(" %02x", cmd_buf[i]);
+		pdl_dbg("\n");
+
+		pkt_state = PKT_IDLE;
+		return -2;
+	}
+	/*pdl_info("Got command packet, packet size %u bytes\n", pkt_size);*/
+
+	/* get all data */
+	if (pkt_size > totalsz - hdrsz) {
+		wait = 0;
+		while (1) {
+			bufsz = channel->tstc();
+			if (bufsz) {
+				u32 last = pkt_size - (totalsz - hdrsz);
+				bufsz = (bufsz > last) ? last : bufsz;
+				channel->read(&cmd_buf[totalsz], bufsz);
+				totalsz += bufsz;
+				wait = 0;
+				if (bufsz == last)
+					break;
+			} else {
+				if (wait++ >= 1000) {
+					pdl_error("wait packet data timeout, got %u bytes, need %u\n",
+								totalsz - hdrsz, pkt_size);
+					pkt_error = PACKET_ERROR;
+					return -1;
+				}
+				udelay(1000);
+			}
+		}
+	}
+
+	pkt_state = PKT_DATA;
+	memset(pkt, 0, sizeof(struct pdl_packet));
+	if (pkt_size < cmd_hdrsz) {
+		memcpy(pkt, &cmd_buf[hdrsz], pkt_size);
+	} else {
+		memcpy(pkt, &cmd_buf[hdrsz], cmd_hdrsz);
+		pkt->data = &cmd_buf[hdrsz+cmd_hdrsz];
+
+		/* packet data crc checking, if have 4 bytes crc in tail */
+		if (pkt_size >= cmd_hdrsz + pkt->cmd_header.data_size + sizeof(u32)) {
+			i = hdrsz + cmd_hdrsz + pkt->cmd_header.data_size;
+			u32 crc = 0, crc_now = 0;
+			memcpy(&crc, &cmd_buf[i], sizeof(u32));
+			crc_now = crc32(0, pkt->data, pkt->cmd_header.data_size);
+			if (crc != crc_now) {
+				pdl_error("packet data crc verify failed, expect %#x, got %#x\n", crc, crc_now);
+				pkt_error = CHECKSUM_ERROR;
+				return -1;
+			}
+		}
+	}
+	return 1;
+}
+
+
+int pdl_get_connect_packet(struct pdl_packet *pkt, u32 timeout)
+{
+	char ch = 0;
+	u8 header_buf[sizeof(struct packet_header)];
+	u32 pkt_size = 0;
+	u32 cnt = timeout; //timeout is in ms;
+
+	while (cnt) {
+		if(!channel->tstc()) {
+			mdelay(1);
+			//pdl_error("try to get\n");
+			cnt--;
+			continue;
+		}
+
+		ch = channel->getchar();
+		if (ch == HOST_PACKET_TAG) {
+			pkt_state = PKT_HEAD;
+			break;
+		} else {
+			pdl_info("oops, get 0x%x\n", ch);
+			continue;
+		}
+	}
+
+	if (cnt == 0 ) {
+		pkt_error = WAIT_TIMEOUT;
+		pdl_error("get connect timeout\n");
+		return -1;
+	}
+	header_buf[0] = ch;
+	while (1) {
+		u8 flowid;
+
+		switch (pkt_state) {
+		case PKT_IDLE:
+			break;
+		case PKT_HEAD:
+			channel->read(&header_buf[1], 5);
+			flowid = header_buf[5];
+			pkt_size = 0;
+			if (flowid == HOST_PACKET_FLOWID) {
+				//ok, this is the header
+				memcpy(&pkt_size, &header_buf[1], 4);
+				pkt_size = le32_to_cpu(pkt_size);
+				pkt_state = PKT_DATA;
+				pdl_vdbg("header right data_size 0x%x\n", pkt_size);
+			} else {
+				pkt_state = PKT_IDLE;
+				return 0;
+			}
+			break;
+		case PKT_DATA:
+			//diff the command data size and packet data size,check if it correct;
+			if (pkt_size >  (sizeof(struct command_header) + 1)) {
+				pkt_error = INVALID_SIZE;
+				return -1;
+			}
+			channel->read(cmd_buf, pkt_size);
+			memcpy(pkt, cmd_buf, sizeof(struct command_header));
+
+			pdl_vdbg("pkt cmd type 0x%x data start 0x%x, size %x\n",
+				pkt->cmd_header.cmd_type,
+				pkt->cmd_header.data_addr,
+				pkt->cmd_header.data_size);
+			return 1;
+		case PKT_ERROR:
+			break;
+		}
+	}
+	return 1;
+}
+/*
+static void pdl_put_packet(struct packet *pkt)
+{
+}
+*/
+void pdl_put_cmd_packet(struct pdl_packet *pkt)
+{
+	memset(pkt, 0, sizeof (struct pdl_packet));
+	pkt_state = PKT_IDLE;
+	pkt_error = 0;
+}
+
+int pdl_get_packet_error(void)
+{
+	return pkt_error;
+}
+
+static int pdl_send_data(const u8 *data, u32 size, u8 flowid)
+{
+	struct packet_header *header = (struct packet_header *)cmd_buf;
+	int hdr_sz = sizeof(struct packet_header);
+
+	if(size > PDL_MAX_PKT_SIZE - hdr_sz) {
+		pdl_error("packet size is too large.\n");
+		return -1;
+	}
+
+	memset(cmd_buf, PDL_MAX_PKT_SIZE, 0);
+	memcpy(&cmd_buf[hdr_sz], data, size);
+
+	header->tag = PACKET_TAG;
+	header->flowid = flowid;
+	/* carefully, header->pkt_size may be unaligned */
+	put_unaligned(size, &header->pkt_size); /* header->pkt_size = size; */
+
+	channel->write(cmd_buf, hdr_sz + size);
+	return 0;
+}
+
+void pdl_send_rsp(int rsp)
+{
+	/*
+	 * if wait timeout, the client may be exit, we dont send
+	 * this error, for the new client will get a extra error
+	 * response
+	*/
+	if (rsp == WAIT_TIMEOUT)
+		return;
+
+	if (rsp != ACK) {
+		if (rsp < ACK || rsp > MAX_RSP)
+			rsp = DEVICE_ERROR;
+		pdl_info("send rsp '%s'\n", pdl_device_rsp[rsp]);
+	}
+
+	pdl_send_data((const u8 *)&rsp, sizeof(int), (rsp == ACK) ? FLOWID_ACK : FLOWID_ERROR);
+	pdl_dbg("send rsp '%s'\n", pdl_device_rsp[rsp]);
+}
+
+int pdl_send_pkt(const u8 *data, u32 size)
+{
+	return pdl_send_data(data, size, FLOWID_DATA);
+}
diff --git a/pdl/common/pdl.c b/pdl/common/pdl.c
new file mode 100644
index 0000000000..e3bbe27cba
--- /dev/null
+++ b/pdl/common/pdl.c
@@ -0,0 +1,28 @@
+#include <common.h>
+#include <asm/arch/hwcfg.h>
+#include <asm/arch/rda_sys.h>
+#include <pdl.h>
+
+int pdl_dbg_pdl = 0;
+int pdl_vdbg_pdl = 0;
+int pdl_dbg_usb_ep0 = 0;
+int pdl_dbg_usb_serial = 0;
+int pdl_dbg_rw_check = 0;
+int pdl_dbg_factory_part = 0;
+
+/*
+  check if should start pdl utilities
+*/
+int pdl_mode_get(void)
+{
+	u16 swcfg = rda_swcfg_get();
+
+	/*
+	if hwconfig is in force download and swcofing is not
+	in calibration mode
+	*/
+	if (rda_bm_is_download() && !(swcfg & RDA_SW_CFG_BIT_4))
+		return 1;
+	else
+		return 0;
+}
diff --git a/pdl/common/pdl_channel.c b/pdl/common/pdl_channel.c
new file mode 100644
index 0000000000..313535423c
--- /dev/null
+++ b/pdl/common/pdl_channel.c
@@ -0,0 +1,39 @@
+
+#include "pdl_channel.h"
+#include "pdl_debug.h"
+
+static struct pdl_channel *serial_channel = NULL;
+
+void pdl_channel_register(struct pdl_channel *channel)
+{
+	if (channel) {
+		serial_channel = channel;
+	} else {
+		pdl_error("channel cannot register\n");
+	}
+
+	return;
+}
+
+struct pdl_channel *pdl_get_channel(void)
+{
+	return serial_channel;
+}
+
+static struct pdl_channel *debug_channel = NULL;
+
+void pdl_debug_channel_register(struct pdl_channel *channel)
+{
+	if (channel) {
+		debug_channel = channel;
+	} else {
+		pdl_error("debug channel cannot register\n");
+	}
+
+	return;
+}
+
+struct pdl_channel *pdl_get_debug_channel(void)
+{
+	return debug_channel;
+}
diff --git a/pdl/common/pdl_channel_usb.c b/pdl/common/pdl_channel_usb.c
new file mode 100644
index 0000000000..1bd7d55527
--- /dev/null
+++ b/pdl/common/pdl_channel_usb.c
@@ -0,0 +1,85 @@
+#include <usb/usbserial.h>
+#include "pdl_channel.h"
+#include "pdl_debug.h"
+
+static int usbser_ch0_tstc (void)
+{
+	return usbser_tstc(USB_ACM_CHAN_0);
+}
+
+static int usbser_ch0_getc (void)
+{
+	return usbser_getc(USB_ACM_CHAN_0);
+}
+
+static void usbser_ch0_putc (const char c)
+{
+	usbser_putc(USB_ACM_CHAN_0, c);
+}
+
+static int usbser_ch0_read(unsigned char *_buf, unsigned int len)
+{
+	return usbser_read(USB_ACM_CHAN_0, _buf, len);
+}
+
+static int usbser_ch0_write(const unsigned char *_buf, unsigned int len)
+{
+	return usbser_write(USB_ACM_CHAN_0, _buf, len);
+}
+
+static struct pdl_channel usb_channel = {
+	.getchar = usbser_ch0_getc,
+	.putchar = usbser_ch0_putc,
+	.tstc = usbser_ch0_tstc,
+	.read = usbser_ch0_read,
+	.write = usbser_ch0_write,
+	.priv = NULL
+};
+
+#ifdef CONFIG_USB_ACM_TWO_CHANS
+
+static int usbser_ch1_tstc (void)
+{
+	return usbser_tstc(USB_ACM_CHAN_1);
+}
+
+static int usbser_ch1_getc (void)
+{
+	return usbser_getc(USB_ACM_CHAN_1);
+}
+
+static void usbser_ch1_putc (const char c)
+{
+	usbser_putc(USB_ACM_CHAN_1, c);
+}
+
+static int usbser_ch1_read(unsigned char *_buf, unsigned int len)
+{
+	return usbser_read(USB_ACM_CHAN_1, _buf, len);
+}
+
+static int usbser_ch1_write(const unsigned char *_buf, unsigned int len)
+{
+	return usbser_write(USB_ACM_CHAN_1, _buf, len);
+}
+
+static struct pdl_channel usb_channel2 = {
+	.getchar = usbser_ch1_getc,
+	.putchar = usbser_ch1_putc,
+	.tstc = usbser_ch1_tstc,
+	.read = usbser_ch1_read,
+	.write = usbser_ch1_write,
+	.priv = NULL,
+};
+
+#endif //CONFIG_USB_ACM_TWO_CHANS
+
+void pdl_usb_channel_register(void)
+{
+#ifdef CONFIG_USB_ACM_TWO_CHANS
+	pdl_debug_channel_register(&usb_channel2);
+#endif
+
+	pdl_channel_register(&usb_channel);
+}
+
diff --git a/pdl/common/pdl_debug.c b/pdl/common/pdl_debug.c
new file mode 100644
index 0000000000..07b812bce0
--- /dev/null
+++ b/pdl/common/pdl_debug.c
@@ -0,0 +1,48 @@
+#include <common.h>
+#include <malloc.h>
+#include <stdio_dev.h>
+#include "pdl.h"
+#include "pdl_debug.h"
+#include "pdl_channel.h"
+
+char *pdl_log_buff = NULL;
+static void pdl_serial_puts(const char *s)
+{
+	struct pdl_channel *dbg_ch = pdl_get_debug_channel();
+
+	/* save print string to log buffer */
+	if(pdl_log_buff) {
+		int a = strlen(pdl_log_buff);
+		int b = strlen(s);
+
+		if(a + b < PDL_LOG_MAX_SIZE)
+			strcpy(&pdl_log_buff[a], s);
+	}
+
+	serial_puts(s);
+
+	if(pdl_dbg_usb_serial && dbg_ch)
+		dbg_ch->write((const unsigned char *)s, strlen(s)+1);
+}
+
+struct stdio_dev *search_device(int flags, const char *name);
+void pdl_init_serial(void)
+{
+	struct stdio_dev *dev = search_device (DEV_FLAGS_OUTPUT, "serial");
+	if(!dev)
+		return;
+	dev->puts = pdl_serial_puts;
+
+	if(!pdl_log_buff) {
+		pdl_log_buff = malloc(PDL_LOG_MAX_SIZE);
+		pdl_log_buff[0] = '\0';
+	}
+}
+void pdl_release_serial(void)
+{
+	struct stdio_dev *dev = search_device (DEV_FLAGS_OUTPUT, "serial");
+	if(!dev)
+		return;
+	dev->puts = serial_puts;
+}
+
diff --git a/pdl/common/pdl_engine.c b/pdl/common/pdl_engine.c
new file mode 100644
index 0000000000..2e4c5d3745
--- /dev/null
+++ b/pdl/common/pdl_engine.c
@@ -0,0 +1,141 @@
+//#define DEBUG
+#include <common.h>
+#include <asm/types.h>
+#include "cmd_defs.h"
+#include <asm/arch/rda_sys.h>
+#include "packet.h"
+#include "pdl_engine.h"
+#include "pdl_debug.h"
+
+static struct pdl_cmd cmd_handler_table[MAX_CMD];
+
+#define cmd_is_valid(cmd) ((cmd >= MIN_CMD) && (cmd < MAX_CMD))
+
+static const char *pdl_commands[MAX_CMD] = {
+	[CONNECT] = "connect",
+	[ERASE_FLASH] = "erase flash",
+	[ERASE_PARTITION] = "erase partition",
+	[ERASE_ALL] = "erase all",
+	[START_DATA] = "start data",
+	[MID_DATA] = "midst data",
+	[END_DATA] = "end data",
+	[EXEC_DATA] = "execute data",
+	[READ_FLASH] = "read flash",
+	[READ_PARTITION] = "read partition",
+	[NORMAL_RESET] = "normal reset",
+	[READ_CHIPID] = "read chipid",
+	[SET_BAUDRATE] = "set baudrate",
+	[FORMAT_FLASH] = "format flash",
+	[READ_PARTITION_TABLE] = "read partition table",
+	[READ_IMAGE_ATTR] = "read image attribute",
+	[GET_VERSION] = "get version",
+	[SET_FACTMODE] = "set factory mode",
+	[SET_CALIBMODE] = "set calibration mode",
+	[SET_PDL_DBG] = "set pdl debuglevel",
+	[CHECK_PARTITION_TABLE] = "check partition table",
+	[POWER_OFF] = "power off",
+	[IMAGE_LIST] = "download image list",
+	[GET_SECURITY] = "get security capabilities",
+	[HW_TEST] = "hardware test",
+	[GET_PDL_LOG] = "get pdl log",
+	[DOWNLOAD_FINISH] = "download finish",
+};
+
+int pdl_cmd_register(int cmd_type, pdl_cmd_handler handler)
+{
+	if (!cmd_is_valid(cmd_type))
+		return -1;
+
+	cmd_handler_table[cmd_type].handler = handler;
+	return 0;
+}
+
+int pdl_handle_connect(u32 timeout)
+{
+	struct pdl_packet pkt;
+	int cmd;
+	int res;
+
+	res = pdl_get_connect_packet(&pkt, timeout);
+	if (res != 1) {
+		return -1;
+	}
+
+	cmd = pkt.cmd_header.cmd_type;
+	if (cmd == CONNECT)
+		cmd_handler_table[cmd].handler(&pkt, 0);
+	else
+		goto err;
+
+	pdl_put_cmd_packet(&pkt);
+	return 0;
+err:
+	pdl_put_cmd_packet(&pkt);
+	return -1;
+}
+
+#define CONNECT_TIMEOUT  180000	/*3 minutes*/
+static void pdl_command_loop(void)
+{
+	struct pdl_packet pkt;
+	int res;
+	u32 cmd;
+	int error;
+	int cnt = CONNECT_TIMEOUT;
+	int check_connect = 1;
+
+	while (1) {
+		res = pdl_get_cmd_packet(&pkt);
+		if (res == -2) {
+			if (!check_connect) {
+				mdelay(1);
+				continue;
+			} else if (--cnt > 0) {
+				mdelay(1);
+				continue;
+			}
+
+			if (cnt <= 0) {
+				pdl_error("PDL get command timeout...\n");
+				break;
+			}
+		}
+		if (check_connect)
+			check_connect = 0;
+
+		if (res == 0)
+			continue;
+
+		//if error send response to pc.
+		if (res == -1) {
+			error = pdl_get_packet_error();
+			pdl_send_rsp(error);
+			pdl_put_cmd_packet(&pkt);
+			continue;
+		}
+		cmd = pkt.cmd_header.cmd_type;
+
+		if (!cmd_is_valid(cmd)) {
+			pdl_send_rsp(INVALID_CMD);
+			pdl_put_cmd_packet(&pkt);
+			continue;
+		}
+
+		pdl_dbg("get and exec cmd '%s'\n", pdl_commands[cmd]);
+
+		if (cmd_handler_table[cmd].handler)
+			res = cmd_handler_table[cmd].handler(&pkt, 0);
+		pdl_put_cmd_packet(&pkt);
+	}
+
+	pdl_info("shutdown machine...\n");
+	shutdown_system();
+}
+
+int pdl_handler(void *arg)
+{
+	for (;;) {
+		pdl_command_loop();
+	}
+	return 0;
+}
diff --git a/pdl/include/cmd_defs.h b/pdl/include/cmd_defs.h
new file mode 100644
index 0000000000..1ca9adcabc
--- /dev/null
+++ b/pdl/include/cmd_defs.h
@@ -0,0 +1,77 @@
+#ifndef _CMD_DEFS_H_
+#define _CMD_DEFS_H_
+#include "packet.h"
+
+enum pdl_cmd_type{
+	MIN_CMD = 0,
+	CONNECT = MIN_CMD,
+	ERASE_FLASH,
+	ERASE_PARTITION,
+	ERASE_ALL,
+	START_DATA,
+	MID_DATA,
+	END_DATA,
+	EXEC_DATA,
+	READ_FLASH,
+	READ_PARTITION,
+	NORMAL_RESET,
+	READ_CHIPID,
+	SET_BAUDRATE,
+	FORMAT_FLASH,
+	READ_PARTITION_TABLE,
+	READ_IMAGE_ATTR,
+	GET_VERSION,
+	SET_FACTMODE,
+	SET_CALIBMODE,
+	SET_PDL_DBG,
+	CHECK_PARTITION_TABLE,
+	POWER_OFF,
+	IMAGE_LIST,
+	GET_SWCFG_REG,
+	SET_SWCFG_REG,
+	GET_HWCFG_REG,
+	SET_HWCFG_REG,
+	EXIT_AND_RELOAD,
+	GET_SECURITY,
+	HW_TEST,
+	GET_PDL_LOG,
+	DOWNLOAD_FINISH,
+	MAX_CMD
+};
+
+enum pdl_rsp {
+	ACK = 0,
+	//from PC command
+	PACKET_ERROR,
+	INVALID_CMD,
+	UNKNOWN_CMD,
+	INVALID_ADDR,
+	INVALID_BAUDRATE,
+	INVALID_PARTITION,
+	INVALID_SIZE,
+	WAIT_TIMEOUT,
+	//from phone
+	VERIFY_ERROR,
+	CHECKSUM_ERROR,
+	OPERATION_FAILED,
+	//phone internal
+	DEVICE_ERROR, //DDR,NAND init errors
+	NO_MEMORY,
+	DEVICE_INCOMPATIBLE,
+	HW_TEST_ERROR,
+	MD5_ERROR,
+	ACK_AGAIN_ERASE,
+	ACK_AGAIN_FLASH,
+	MAX_RSP
+};
+
+#define PDL_DBG_PDL		(0x1<<0)
+#define PDL_DBG_USB_EP0		(0x1<<1)
+#define PDL_DBG_USB_SERIAL	(0x1<<2)
+#define PDL_DBG_RW_CHECK	(0x1<<3)
+#define PDL_DBG_FACTORY_PART	(0x1<<4)
+#define PDL_DBG_PDL_VERBOSE	(0x1<<5)
+#define PDL_EXTENDED_STATUS	(0x1<<7)
+
+#endif
+
diff --git a/pdl/include/config.h b/pdl/include/config.h
new file mode 100644
index 0000000000..b2d37705ab
--- /dev/null
+++ b/pdl/include/config.h
@@ -0,0 +1,11 @@
+#ifndef __PDL_CONFIG_H__
+#define __PDL_CONFIG_H__
+
+#ifdef CONFIG_SPL_BUILD
+# define CONFIG_RDA_PDL1
+#else
+# define CONFIG_RDA_PDL2
+#endif
+
+#endif // __PDL_CONFIG_H__
+
diff --git a/pdl/include/packet.h b/pdl/include/packet.h
new file mode 100644
index 0000000000..c261eba161
--- /dev/null
+++ b/pdl/include/packet.h
@@ -0,0 +1,63 @@
+#ifndef _PACKET_H_
+#define _PACKET_H_
+#include "config.h"
+
+/* host define, for receiving packet */
+#define HOST_PACKET_TAG 0xAE
+#define HOST_PACKET_FLOWID 0xFF
+
+/* client define, for sending packet */
+#define PACKET_TAG		0xAE
+#define FLOWID_DATA		0xBB
+#define FLOWID_ACK		0xFF
+#define FLOWID_ERROR	0xEE
+
+/*
+ * for yaffs image, the packet length must be aligned to the (page_size+oob)
+ */
+#if defined(CONFIG_RDA_PDL2)
+# define PDL_MAX_DATA_SIZE  270336  //(256*(1024 + 32)) == (64 * 4224)
+#elif defined(CONFIG_RDA_PDL1)
+# define PDL_MAX_DATA_SIZE (4*1024)
+#else
+#error "no valid pdl config"
+#endif
+
+
+struct packet_header {
+	u8 tag;
+	u32 pkt_size;
+	u8 flowid;
+}__attribute__((packed));
+
+struct command_header {
+	u32 cmd_type;
+	u32 data_addr;
+	u32 data_size;
+};
+
+#define PDL_MAX_PKT_SIZE (PDL_MAX_DATA_SIZE + \
+		sizeof(struct command_header) + sizeof(struct packet_header))
+
+struct pdl_packet {
+	struct command_header cmd_header;
+	u8 *data;
+};
+
+
+struct packet{
+	struct packet_header pkt_header;
+	struct pdl_packet *pdl_pkt;
+	int state;
+};
+
+int  pdl_get_cmd_packet(struct pdl_packet *pkt);
+void pdl_put_cmd_packet(struct pdl_packet *pkt);
+int pdl_get_connect_packet(struct pdl_packet *pkt, u32 timeout);
+
+void pdl_send_rsp(int rsp);
+int pdl_send_pkt(const u8 *data, u32 size);
+int pdl_get_packet_error(void);
+int pdl_init_packet_channel(void);
+#endif
+
diff --git a/pdl/include/pdl_channel.h b/pdl/include/pdl_channel.h
new file mode 100644
index 0000000000..731878d729
--- /dev/null
+++ b/pdl/include/pdl_channel.h
@@ -0,0 +1,28 @@
+#ifndef _PDL_CHANNEL_H_
+#define _PDL_CHANNEL_H_
+
+struct pdl_channel {
+	int (*read) (unsigned char *buf, unsigned int len);
+	int (*getchar) (void);
+	int (*tstc) (void);
+	int (*write) (const unsigned char *buf, unsigned int len);
+	void (*putchar) (const char ch);
+	void   *priv;
+};
+
+/* get the current pdl data channel */
+struct pdl_channel *pdl_get_channel(void);
+/* register the pdl data channel */
+void pdl_channel_register(struct pdl_channel *channel);
+
+/* get the current pdl debug channel */
+struct pdl_channel *pdl_get_debug_channel(void);
+/* register the pdl debug channel */
+void pdl_debug_channel_register(struct pdl_channel *channel);
+
+/* register the usb serial channel 0 as the pdl data channel.
+   if defined, register the usb serial channel 1 as the pdl debug channel. */
+void pdl_usb_channel_register(void);
+
+#endif
+
diff --git a/pdl/include/pdl_command.h b/pdl/include/pdl_command.h
new file mode 100644
index 0000000000..08e8b66bed
--- /dev/null
+++ b/pdl/include/pdl_command.h
@@ -0,0 +1,15 @@
+#ifndef _PDL_COMMAND_H_
+#define _PDL_COMMAND_H_
+#include "config.h"
+#include "packet.h"
+
+
+#if defined(CONFIG_RDA_PDL1)
+#include "../pdl-1/pdl1_command.h"
+#elif defined(CONFIG_RDA_PDL2)
+#include "../pdl-2/pdl2_command.h"
+#else
+#error "no valid pdl"
+#endif
+
+#endif
diff --git a/pdl/include/pdl_debug.h b/pdl/include/pdl_debug.h
new file mode 100644
index 0000000000..d908e7a28f
--- /dev/null
+++ b/pdl/include/pdl_debug.h
@@ -0,0 +1,28 @@
+#ifndef _PDL_DEBUG_H_
+#define _PDL_DEBUG_H_
+
+#include <serial.h>
+
+#define PDL_LOG_MAX_SIZE		(512*1024)
+
+extern char *pdl_log_buff;
+void pdl_init_serial(void);
+void pdl_release_serial(void);
+
+#define pdl_error printf
+#define pdl_info printf
+
+extern int pdl_dbg_pdl;
+#define pdl_dbg(str...) \
+	do {	\
+	if (pdl_dbg_pdl) \
+		printf(str); \
+	} while(0)
+
+extern int pdl_vdbg_pdl;
+#define pdl_vdbg(str...) \
+	do {	\
+	if (pdl_vdbg_pdl) \
+		printf(str); \
+	} while(0)
+#endif
diff --git a/pdl/include/pdl_engine.h b/pdl/include/pdl_engine.h
new file mode 100644
index 0000000000..84f07797f6
--- /dev/null
+++ b/pdl/include/pdl_engine.h
@@ -0,0 +1,12 @@
+#ifndef _PDL_ENGINE_H_
+#define _PDL_ENGINE_H_
+
+typedef int (*pdl_cmd_handler)(struct pdl_packet *pkt, void *arg); 
+struct pdl_cmd { 
+        pdl_cmd_handler handler; 
+}; 
+ 
+int pdl_cmd_register(int cmd_type, pdl_cmd_handler handler); 
+int pdl_handler(void *arg);
+int pdl_handle_connect(u32 timeout);
+#endif
diff --git a/pdl/pdl-1/Makefile b/pdl/pdl-1/Makefile
new file mode 100644
index 0000000000..ec7032182d
--- /dev/null
+++ b/pdl/pdl-1/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	:= $(obj)libpdl_stage.o
+CPPFLAGS  += -I ../include
+CFLAGS  += -I ../include -mno-unaligned-access
+
+COBJS-$(CONFIG_SPL_RDA_PDL) += pdl_command.o pdl_main.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/pdl/pdl-1/pdl1_command.h b/pdl/pdl-1/pdl1_command.h
new file mode 100644
index 0000000000..12407f6034
--- /dev/null
+++ b/pdl/pdl-1/pdl1_command.h
@@ -0,0 +1,13 @@
+#ifndef _PDL1_COMMAND_H_
+#define _PDL1_COMMAND_H_
+
+int sys_connect(struct pdl_packet *packet, void *arg);
+int data_start(struct pdl_packet *packet, void *arg);
+int data_midst(struct pdl_packet *packet, void *arg);
+int data_end(struct pdl_packet *packet, void *arg);
+int data_exec(struct pdl_packet *packet, void *arg);
+int get_pdl_version(struct pdl_packet *packet, void *arg);
+int reset_machine(struct pdl_packet *packet, void *arg);
+int get_pdl_security(struct pdl_packet *packet, void *arg);
+
+#endif
diff --git a/pdl/pdl-1/pdl_command.c b/pdl/pdl-1/pdl_command.c
new file mode 100644
index 0000000000..3eb4769410
--- /dev/null
+++ b/pdl/pdl-1/pdl_command.c
@@ -0,0 +1,176 @@
+#include <common.h>
+#include "packet.h"
+#include <linux/string.h>
+#include "cmd_defs.h"
+#include "pdl_debug.h"
+#include <asm/arch/rda_sys.h>
+#include <asm/arch/rda_crypto.h>
+
+struct dl_file_info {
+	unsigned long start_address;
+	unsigned long total_size;
+	unsigned long recv_size;
+	unsigned long next_address;
+};
+
+static struct dl_file_info exec_file;
+
+
+int sys_connect(struct pdl_packet *packet, void *arg)
+{
+	pdl_info("connect with pc\n");
+	pdl_send_rsp(ACK);
+	return 0;
+}
+
+int data_start(struct pdl_packet *packet, void *arg)
+{
+	unsigned long start_addr = packet->cmd_header.data_addr;
+	unsigned long file_size = packet->cmd_header.data_size;
+
+#if 0
+	if ((start_addr < MEMORY_START) || (start_addr >= MEMORY_START + MEMORY_SIZE)) {
+		pdl_send_rsp(INVALID_ADDR);
+		return 0;
+	}
+
+	if ((start_addr + file_size) > (MEMORY_START + MEMORY_SIZE)) {
+		pdl_send_rsp(INVALID_SIZE);
+		return 0;
+	}
+#endif
+	pdl_info("start addr %lx, file size %lx\n", start_addr, file_size);
+
+	exec_file.start_address = start_addr;
+	exec_file.total_size = file_size;
+	exec_file.recv_size = 0;
+	exec_file.next_address = start_addr;
+
+//	memset((void*)start_addr, 0, file_size);
+	pdl_send_rsp(ACK);
+	return 0;
+}
+
+int data_midst(struct pdl_packet *packet, void *arg)
+{
+	short data_len = packet->cmd_header.data_size;
+
+	if ((exec_file.recv_size + data_len) > exec_file.total_size) {
+		pdl_send_rsp(INVALID_SIZE);
+		return 0;
+	}
+
+	memcpy((void *)exec_file.next_address, packet->data, data_len);
+	exec_file.next_address += data_len;
+	exec_file.recv_size += data_len;
+
+	pdl_dbg("write to addr %lx, receive size %ld\n", exec_file.next_address,
+				 exec_file.recv_size);
+	pdl_send_rsp(ACK);
+	return 0;
+}
+
+int data_end(struct pdl_packet *packet, void *arg)
+{
+	pdl_info("receive pdl2 finish\n");
+	pdl_send_rsp(ACK);
+	return 0;
+}
+
+static unsigned long
+do_go_exec (ulong (*entry)(int, char * const []), int argc, char * const argv[])
+{
+        return entry (argc, argv);
+}
+
+int data_exec(struct pdl_packet *packet, void *arg)
+{
+#ifdef  CONFIG_SIGNATURE_CHECK_IMAGE
+	pdl_info("Verify executable 0x%lx, #%ld\n", 
+	         exec_file.start_address,exec_file.recv_size);
+	if (image_sign_verify((const void *)exec_file.start_address,
+	                      exec_file.recv_size)) {
+		printf("Verify failed, aborting execute.\n");
+		pdl_send_rsp(VERIFY_ERROR);
+		return 0;
+	}
+#endif
+	pdl_info("Execute download from 0x%lx\n", exec_file.start_address);
+	do_go_exec((void *)exec_file.start_address, 1, NULL);
+	return 0;
+}
+
+int get_pdl_version(struct pdl_packet *packet, void *arg)
+{
+	static const unsigned char pdl1_version[] = "PDL1";
+
+	pdl_info("get pdl version\n");
+
+	pdl_send_pkt(pdl1_version, sizeof(pdl1_version));
+	return 0;
+}
+
+#include <asm/arch/rom_api_trampolin.h>
+
+int get_pdl_security(struct pdl_packet *packet, void *arg)
+{
+	struct {
+		char buffer[16];
+		struct chip_id chip_id;
+		struct chip_security_context chip_security_context;
+		struct chip_unique_id chip_unique_id;
+		struct pubkey pubkey;
+		u8     random[32];
+	} response;
+
+	pdl_info("get pdl security\n");
+
+	memset(&response, 0, sizeof(response));
+
+	if (memcmp(romapi->magic, "RDA API", 8) == 0) {
+		int n;
+		get_chip_id(&response.chip_id);
+		get_chip_unique(&response.chip_unique_id);
+		n = get_chip_security_context(&response.chip_security_context,
+		                              &response.pubkey);
+		get_chip_true_random(response.random, 32);
+		sprintf(response.buffer, "RDASEC: v%d/%d", romapi->version, n);
+	}
+	else
+		sprintf(response.buffer, "RDASEC: none");
+
+	pdl_send_pkt((const u8 *)&response, sizeof(response));
+
+	return 0;
+}
+
+
+int reset_machine(struct pdl_packet *packet, void *arg)
+{
+	u8 reboot_mode = REBOOT_TO_NORMAL_MODE;
+
+	pdl_info("reset machine....\n");
+
+	if (packet->cmd_header.data_size == 1) {
+		reboot_mode = packet->data[0];
+	}
+	switch (reboot_mode) {
+		case REBOOT_TO_NORMAL_MODE:
+		case REBOOT_TO_DOWNLOAD_MODE:
+		case REBOOT_TO_FASTBOOT_MODE:
+		case REBOOT_TO_RECOVERY_MODE:
+		case REBOOT_TO_CALIB_MODE:
+			break;
+		default:
+			reboot_mode = REBOOT_TO_NORMAL_MODE;
+	}
+
+	pdl_info("reboot_mode: %d\n", reboot_mode);
+	pdl_send_rsp(ACK); // cheat and send ack before reset
+
+	rda_reboot(reboot_mode);
+
+	/*should never here */
+	return 0;
+}
+
diff --git a/pdl/pdl-1/pdl_main.c b/pdl/pdl-1/pdl_main.c
new file mode 100644
index 0000000000..242745297d
--- /dev/null
+++ b/pdl/pdl-1/pdl_main.c
@@ -0,0 +1,34 @@
+#include <common.h>
+#include "pdl_command.h"
+#include "packet.h"
+#include "cmd_defs.h"
+#include "pdl_engine.h"
+#include "pdl_debug.h"
+#include "pdl_channel.h"
+
+int pdl_main(void)
+{
+	pdl_info("start PDL1 main loop\n");
+	pdl_usb_channel_register();
+	pdl_init_packet_channel();
+
+	pdl_cmd_register(CONNECT, sys_connect);
+	pdl_cmd_register(START_DATA, data_start);
+	pdl_cmd_register(MID_DATA, data_midst);
+	pdl_cmd_register(END_DATA, data_end);
+	pdl_cmd_register(EXEC_DATA, data_exec);
+	pdl_cmd_register(NORMAL_RESET, reset_machine);
+	pdl_cmd_register(GET_VERSION, get_pdl_version);
+	pdl_cmd_register(GET_SECURITY, get_pdl_security);
+
+#if 0
+	serial_puts("wait for connect....\n");
+	if (pdl_handle_connect(CONNECT_TIMEOUT) != 0){
+		pdl_error("cannot handle connect\n");
+		return -1;
+	}
+#endif
+	pdl_send_rsp(ACK);
+	pdl_handler(NULL);
+	return 0;
+}
diff --git a/pdl/pdl-2/Makefile b/pdl/pdl-2/Makefile
new file mode 100644
index 0000000000..f342eddcc4
--- /dev/null
+++ b/pdl/pdl-2/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	:= $(obj)libpdl_stage.o
+CPPFLAGS  += -I ../include
+CFLAGS  += -I ../include -mno-unaligned-access
+
+COBJS-y += pdl_command.o pdl_main.o pdl_nand.o
+COBJS-$(CONFIG_GENERIC_MMC) += pdl_emmc.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/pdl/pdl-2/pdl2_command.h b/pdl/pdl-2/pdl2_command.h
new file mode 100644
index 0000000000..a89efe42fa
--- /dev/null
+++ b/pdl/pdl-2/pdl2_command.h
@@ -0,0 +1,26 @@
+#ifndef _PDL2_COMMAND_H_
+#define _PDL2_COMMAND_H_
+
+int pdl_command_init(void);
+int sys_connect(struct pdl_packet *packet, void *arg);
+int data_start(struct pdl_packet *packet, void *arg);
+int data_midst(struct pdl_packet *packet, void *arg);
+int data_end(struct pdl_packet *packet, void *arg);
+int data_exec(struct pdl_packet *packet, void *arg);
+int read_partition(struct pdl_packet *packet, void *arg);
+int read_partition_table(struct pdl_packet *packet, void *arg);
+int format_flash(struct pdl_packet *packet, void *arg);
+int read_image_attr(struct pdl_packet *packet, void *arg);
+int erase_partition(struct pdl_packet *packet, void *arg);
+int get_pdl_version(struct pdl_packet *packet, void *arg);
+int reset_machine(struct pdl_packet *packet, void *arg);
+int poweroff_machine(struct pdl_packet *packet, void *arg);
+int set_pdl_dbg(struct pdl_packet *packet, void *arg);
+int check_partition_table(struct pdl_packet *packet, void *arg);
+int recv_image_list(struct pdl_packet *packet, void *arg);
+int get_pdl_security(struct pdl_packet *packet, void *arg);
+int hw_test(struct pdl_packet *packet, void *arg);
+int get_pdl_log(struct pdl_packet *packet, void *arg);
+int download_finish(struct pdl_packet *packet, void *arg);
+
+#endif
diff --git a/pdl/pdl-2/pdl_command.c b/pdl/pdl-2/pdl_command.c
new file mode 100644
index 0000000000..a6c06c17b0
--- /dev/null
+++ b/pdl/pdl-2/pdl_command.c
@@ -0,0 +1,571 @@
+#include <common.h>
+#include <version.h>
+#include <asm/types.h>
+#include "packet.h"
+#include <linux/string.h>
+#include <malloc.h>
+#include <asm/arch/mtdparts_def.h>
+#include <asm/arch/rda_sys.h>
+#include <asm/arch/rda_crypto.h>
+#include <asm/arch/hw_test.h>
+#include <asm/arch/prdinfo.h>
+#include "cmd_defs.h"
+#include "pdl_debug.h"
+#include "pdl.h"
+#include "pdl_command.h"
+#include "pdl_nand.h"
+#include "pdl_emmc.h"
+#include <linux/mtd/mtd.h>
+
+#define MAX_PART_NAME	30
+#define MAX_TEST_LIST_SIZE		60
+
+#ifdef CONFIG_PDL_FORCE_HW_TEST_FULL
+static int hw_tested = 0;
+static int hw_test_run(const char *test_list, int fast_mode);
+#endif
+
+uint8_t pdl_extended_status = 0;
+
+static int media_type = MEDIA_NAND;
+int sys_connect(struct pdl_packet *packet, void *arg)
+{
+	pdl_info("connect with pc\n");
+	pdl_send_rsp(ACK);
+	return 0;
+}
+
+struct exec_file_info {
+	unsigned long start_address;
+	unsigned long total_size;
+	unsigned long recv_size;
+	unsigned long next_address;
+};
+static struct exec_file_info exec_file;
+static int frame_count = -1;
+
+int data_start(struct pdl_packet *packet, void *arg)
+{
+	unsigned long start_addr = packet->cmd_header.data_addr;
+	unsigned long file_size = packet->cmd_header.data_size;
+	int ret;
+	char part_name[MAX_PART_NAME + 1] = {'\0'};
+
+	strncpy(part_name, (char *)packet->data, MAX_PART_NAME);
+	frame_count = -1;
+
+#ifdef CONFIG_PDL_FORCE_HW_TEST_FULL
+	if(!hw_tested &&
+		strstr(part_name, "system")) {
+		ret = hw_test_run("all", 0);
+		if(ret) {
+			pdl_send_rsp(ret);
+			return 0;
+		}
+		hw_tested = 1;
+	}
+#endif
+
+	if (strlen(part_name) == 0) {
+		pdl_info("invalid partition name\n");
+		pdl_send_rsp(INVALID_PARTITION);
+		return -1;
+	}
+
+
+	/* the image is pdl1.bin or pdl2.bin */
+	memset(&exec_file, 0, sizeof(exec_file));
+	if(strncmp(part_name, "pdl", 3) == 0 ||
+		strncmp(part_name, "PDL", 3) == 0) {
+		exec_file.start_address = start_addr;
+		exec_file.total_size = file_size;
+		exec_file.recv_size = 0;
+		exec_file.next_address = start_addr;
+
+		pdl_send_rsp(ACK);
+		return 0;
+	}
+
+	if (media_type == MEDIA_MMC)
+		ret = emmc_data_start(part_name, file_size);
+	else
+		ret = nand_data_start(part_name, file_size);
+	if (ret) {
+		pdl_send_rsp(ret);
+		return -1;
+	}
+
+	pdl_send_rsp(ACK);
+	return 0;
+}
+
+int data_midst(struct pdl_packet *packet, void *arg)
+{
+	u32 size = packet->cmd_header.data_size;
+	int ret;
+	u32 frame_num = packet->cmd_header.data_addr;
+
+	/* pdl1.bin or pdl2.bin */
+	if(exec_file.total_size > 0) {
+		if ((exec_file.recv_size + size) > exec_file.total_size) {
+			pdl_send_rsp(INVALID_SIZE);
+			return 0;
+		}
+
+		memcpy((void *)exec_file.next_address, packet->data, size);
+		exec_file.next_address += size;
+		exec_file.recv_size += size;
+
+		pdl_dbg("write to addr %lx, receive size %ld\n", exec_file.next_address,
+					 exec_file.recv_size);
+
+		pdl_send_rsp(ACK);
+		return 0;
+	}
+
+	/* check frame number */
+	if(frame_count >= 0) {
+		if(frame_num < frame_count) { /* ignore this frame */
+			pdl_send_rsp(ACK);
+			return 0;
+		}
+		if(frame_num > frame_count) {
+			pdl_send_rsp(PACKET_ERROR);
+			pdl_error("expect frame %d, not %d\n", frame_count, frame_num);
+			return -1;
+		}
+	} else {
+		frame_count = frame_num;
+	}
+
+	pdl_dbg("frame count %u\n", frame_count);
+	frame_count++;
+	if (media_type == MEDIA_MMC)
+		ret = emmc_data_midst(packet->data, size);
+	else
+		ret = nand_data_midst(packet->data, size);
+	if (ret) {
+		pdl_send_rsp(ret);
+		return -1;
+	}
+
+	pdl_send_rsp(ACK);
+	return 0;
+}
+
+int data_end(struct pdl_packet *packet, void *arg)
+{
+	int ret;
+	uint32_t data_size = packet->cmd_header.data_size;
+	uint32_t data_crc = 0;
+
+	/* pdl1.bin or pdl2.bin */
+	if(exec_file.total_size > 0) {
+		pdl_info("receive pdl1/pdl2 finish\n");
+		pdl_send_rsp(ACK);
+		return 0;
+	}
+
+	frame_count = -1;
+	if(data_size == 4)
+		memcpy((void *)&data_crc, (void *)packet->data, 4);
+
+	if (media_type == MEDIA_MMC)
+		ret = emmc_data_end(data_crc);
+	else
+		ret = nand_data_end(data_crc);
+	if (ret) {
+		pdl_send_rsp(ret);
+		return -1;
+	}
+
+	pdl_send_rsp(ACK);
+	return 0;
+}
+
+static unsigned long
+do_go_exec (ulong (*entry)(int, char * const []), int argc, char * const argv[])
+{
+        return entry (argc, argv);
+}
+
+int data_exec(struct pdl_packet *packet, void *arg)
+{
+#ifdef  CONFIG_SIGNATURE_CHECK_IMAGE
+	pdl_info("Verify executable 0x%lx, #%ld\n",
+	         exec_file.start_address,exec_file.recv_size);
+	if (image_sign_verify((const void *)exec_file.start_address,
+	                      exec_file.recv_size)) {
+		printf("Verify failed, aborting execute.\n");
+		pdl_send_rsp(VERIFY_ERROR);
+		return 0;
+	}
+#endif
+	pdl_info("Execute download from 0x%lx\n", exec_file.start_address);
+	do_go_exec((void *)exec_file.start_address, 1, NULL);
+	return 0;
+}
+
+int read_partition(struct pdl_packet *packet, void *arg)
+{
+	size_t size = packet->cmd_header.data_size;
+	char part_name[MAX_PART_NAME + 1] = {'\0'};
+	int ret;
+	size_t actual_len = 0;
+	unsigned char *data;
+
+	strncpy(part_name, (char *)packet->data, MAX_PART_NAME);
+	if (strlen(part_name) == 0) {
+		pdl_info("invalid partition name\n");
+		pdl_send_rsp(INVALID_PARTITION);
+		return -1;
+	}
+
+	pdl_info("%s from %s\n", __func__, part_name);
+
+	data = malloc(size);
+	if (!data) {
+		pdl_info("no memory!\n");
+		pdl_send_rsp(NO_MEMORY);
+		return -1;
+	}
+
+	if (media_type == MEDIA_MMC)
+		ret = emmc_read_partition(part_name, data, size,
+				&actual_len);
+	else
+		ret = nand_read_partition(part_name, data, size,
+				&actual_len);
+	if (ret) {
+		pdl_send_rsp(ret);
+		ret = -1;
+		goto out;
+	}
+
+	pdl_send_pkt(data, actual_len);
+	pdl_dbg("send ok\n");
+out:
+	free(data);
+	return ret;
+}
+
+extern int mtdparts_ptbl_check(int *same);
+extern int mmc_check_parts(int *same);
+int check_partition_table(struct pdl_packet *packet, void *arg)
+{
+	int ret;
+	int same = 0;
+	unsigned char data;
+
+	if (media_type == MEDIA_MMC)
+		ret = mmc_check_parts(&same);
+	else
+		ret = mtdparts_ptbl_check(&same);
+
+	if(ret) {
+		pdl_send_rsp(DEVICE_ERROR);
+		return -1;
+	}
+
+	data = (u8)(same & 0xff);
+	pdl_send_pkt(&data, 1);
+	return 0;
+}
+
+int read_partition_table(struct pdl_packet *packet, void *arg)
+{
+	u32 size;
+	const char *parts = getenv("mtdparts");
+
+	pdl_info("%s, parts %s\n", __func__, parts);
+
+	size = strlen(parts);
+	pdl_send_pkt((const u8*)parts, size);
+	return 0;
+}
+extern struct mtd_device *current_mtd_dev;
+
+int format_flash(struct pdl_packet *packet, void *arg)
+{
+	int ret;
+
+	pdl_info("format the whole flash part\n");
+
+	if (media_type == MEDIA_MMC)
+		ret = emmc_format_flash();
+	else
+		ret = nand_format_flash();
+	if (ret) {
+		pdl_send_rsp(ret);
+		return -1;
+	}
+
+#ifdef CONFIG_PDL_FORCE_HW_TEST_FULL
+	if(!hw_tested) {
+		ret = hw_test_run("all", 0);
+		if(ret) {
+			pdl_send_rsp(ret);
+			return 0;
+		}
+		hw_tested = 1;
+	}
+#endif
+
+	pdl_send_rsp(ACK);
+	return 0;
+}
+
+int read_image_attr(struct pdl_packet *packet, void *arg)
+{
+	const char attrs[] = IMAGE_ATTR;
+
+	pdl_info("fs image attrs: %s\n", attrs);
+
+	pdl_send_pkt((const u8*)attrs, sizeof(attrs));
+	return 0;
+}
+
+int erase_partition(struct pdl_packet *packet, void *arg)
+{
+	int ret;
+	char part_name[MAX_PART_NAME + 1] = {'\0'};
+
+	strncpy(part_name, (char *)packet->data, MAX_PART_NAME);
+
+	if (strlen(part_name) == 0) {
+		pdl_info("invalid partition name\n");
+		pdl_send_rsp(INVALID_PARTITION);
+		return -1;
+	}
+
+	if (media_type == MEDIA_MMC)
+		ret = emmc_erase_partition(part_name);
+	else
+		ret = nand_erase_partition(part_name);
+	if (ret) {
+		pdl_send_rsp(ret);
+		return -1;
+	}
+
+	/* if the part is 'userdata', erase 'fat' part also */
+	if (strcmp(part_name, "userdata") == 0) {
+		strcpy(part_name, "fat");
+		if (media_type == MEDIA_MMC)
+			emmc_erase_partition(part_name);
+		else
+			nand_erase_partition(part_name);
+	}
+
+	pdl_send_rsp(ACK);
+	return 0;
+}
+
+int get_pdl_version(struct pdl_packet *packet, void *arg)
+{
+	u32 flag = packet->cmd_header.data_addr;
+	u32 size;
+#define MAX_VER_LEN	100
+	char str[MAX_VER_LEN+1];
+
+	memset(str, 0, MAX_VER_LEN + 1);
+	strncpy(str, version_string, MAX_VER_LEN);
+
+#ifdef BUILD_DISPLAY_ID
+	/* return BUILD_DISPLAY_ID instead of pdl version */
+	if(flag == 1)
+		strncpy(str, BUILD_DISPLAY_ID, MAX_VER_LEN);
+#endif
+
+	pdl_info("send version string: [%s]\n", str);
+
+	size = strlen(str) + 1;
+	pdl_send_pkt((const u8*)str, size);
+	return 0;
+}
+
+int reset_machine(struct pdl_packet *packet, void *arg)
+{
+	pdl_info("reset machine....\n");
+
+	u8 reboot_mode = REBOOT_TO_NORMAL_MODE;
+	if (packet->cmd_header.data_size == 1) {
+		reboot_mode = packet->data[0];
+	}
+	switch (reboot_mode) {
+		case REBOOT_TO_NORMAL_MODE:
+		case REBOOT_TO_DOWNLOAD_MODE:
+		case REBOOT_TO_FASTBOOT_MODE:
+		case REBOOT_TO_RECOVERY_MODE:
+		case REBOOT_TO_CALIB_MODE:
+			break;
+		default:
+			reboot_mode = REBOOT_TO_NORMAL_MODE;
+	}
+
+	pdl_info("reboot_mode: %d\n", reboot_mode);
+	pdl_send_rsp(ACK); // cheat and send ack before reset
+
+	rda_reboot(reboot_mode);
+
+	/* should never here */
+	return 0;
+}
+
+int poweroff_machine(struct pdl_packet *packet, void *arg)
+{
+	pdl_info("waiting USB cable plug out...\n");
+	while(usb_cable_connected()){
+		mdelay(20);
+	}
+	pdl_info("machine power off...\n");
+	shutdown_system();
+	return 0;
+}
+
+int recv_image_list(struct pdl_packet *packet, void *arg)
+{
+	pdl_info("receive download image list...\n");
+	pdl_info("\t%s\n", (char *)packet->data);
+	prdinfo_init((char *)packet->data);
+	pdl_send_rsp(ACK);
+	return 0;
+}
+
+static int hw_test_run(const char *test_list, int fast_mode)
+{
+	int __attribute__((unused)) test_all = 0;
+
+	if(!test_list)
+		return HW_TEST_ERROR;
+
+	if(strcmp(test_list, "all") == 0)
+		test_all = 1;
+
+	pdl_info("start %s hardware test...[%s]\n", fast_mode ? "fast" : "full", test_list);
+
+#ifdef CONFIG_VPU_STA_TEST
+	if(test_all || strstr(test_list, "vpu")) {
+		vpu_sta_test(fast_mode ? 10 : 200);
+		pdl_info("VPU stable test..pass!\n");
+	}
+#endif
+
+#ifdef CONFIG_VPU_MD5_TEST
+	if(test_all || strstr(test_list, "vpu_md5")) {
+		int ret = vpu_md5_test(fast_mode ? 10 : 200);
+		if(ret)
+			return MD5_ERROR;
+		pdl_info("VPU MD5 test..pass!\n");
+	}
+#endif
+
+#ifdef CONFIG_CPU_TEST
+	if(test_all || strstr(test_list, "cpu")) {
+		cpu_pll_test(fast_mode ? 2000 : 4000);
+		pdl_info("CPU test..pass!\n");
+	}
+#endif
+
+	pdl_info("end %s hardware test.\n", fast_mode ? "fast" : "full");
+	return ACK;
+}
+
+int hw_test(struct pdl_packet *packet, void *arg)
+{
+	unsigned long param_size = packet->cmd_header.data_size;
+	char test_list[MAX_TEST_LIST_SIZE + 1] = {'\0'};
+	int ret = 0;
+
+	if(param_size > 0)
+		strncpy(test_list, (char *)packet->data, MAX_TEST_LIST_SIZE);
+	else
+		strcpy(test_list, "all");
+
+	ret = hw_test_run(test_list, 0);
+	pdl_send_rsp(ret);
+	return 0;
+}
+
+int get_pdl_log(struct pdl_packet *packet, void *arg)
+{
+	u32 size;
+
+	pdl_info("get pdl log\n");
+
+	size = strlen(pdl_log_buff) + 1;
+	pdl_send_pkt((const u8*)pdl_log_buff, size);
+	return 0;
+}
+
+int download_finish(struct pdl_packet *packet, void *arg)
+{
+	u32 ftm_tag = packet->cmd_header.data_addr;
+	pdl_info("download finish!\n");
+
+	prdinfo_set_pdl_result(1, ftm_tag);
+	pdl_send_rsp(ACK);
+	return 0;
+}
+
+int set_pdl_dbg(struct pdl_packet *packet, void *arg)
+{
+	u32 dbg_settings = packet->cmd_header.data_addr;
+
+	pdl_info("%s, dbg_settings :%x\n", __func__, dbg_settings);
+
+	if (dbg_settings & PDL_DBG_PDL) {
+		pdl_info("open pdl debug\n");
+		pdl_dbg_pdl = 1;
+	}
+
+	if (dbg_settings & PDL_DBG_PDL_VERBOSE) {
+		pdl_info("open pdl verbose debug\n");
+		pdl_dbg_pdl = 1;
+		pdl_vdbg_pdl = 1;
+	}
+
+	if (dbg_settings & PDL_DBG_USB_EP0) {
+		pdl_info("open pdl usb ep0 debug\n");
+		pdl_dbg_usb_ep0 = 1;
+	}
+
+	if (dbg_settings & PDL_DBG_RW_CHECK) {
+		pdl_info("open pdl flash write/read/compare debug\n");
+		pdl_dbg_rw_check = 1;
+	}
+
+	if (dbg_settings & PDL_DBG_USB_SERIAL) {
+		pdl_info("open pdl usb serial debug\n");
+		pdl_dbg_usb_serial = 1;
+	}
+
+	if (dbg_settings & PDL_DBG_FACTORY_PART) {
+		pdl_info("open pdl factory part debug\n");
+		pdl_dbg_factory_part = 1;
+	}
+	if (dbg_settings & PDL_EXTENDED_STATUS) {
+		pdl_info("Enable extended status\n");
+		pdl_extended_status = 1;
+	}
+
+	pdl_send_rsp(ACK);
+	return 0;
+}
+
+int pdl_command_init(void)
+{
+	int ret;
+
+	media_type = rda_media_get();
+	if (media_type == MEDIA_MMC) {
+		ret = pdl_emmc_init();
+	} else {
+		ret = pdl_nand_init();
+	}
+
+#ifdef CONFIG_PDL_FORCE_HW_TEST
+	ret = hw_test_run("all", 1);
+#endif
+
+	return ret;
+}
diff --git a/pdl/pdl-2/pdl_emmc.c b/pdl/pdl-2/pdl_emmc.c
new file mode 100644
index 0000000000..d07be8c07d
--- /dev/null
+++ b/pdl/pdl-2/pdl_emmc.c
@@ -0,0 +1,340 @@
+#include <common.h>
+#include <asm/types.h>
+#include "packet.h"
+#include <linux/string.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <part.h>
+#include <mmc/sparse.h>
+#include <mmc/mmcpart.h>
+#include <asm/arch/rda_sys.h>
+#include <asm/arch/factory.h>
+#include <asm/arch/prdinfo.h>
+#include "cmd_defs.h"
+#include "pdl_debug.h"
+#include "pdl.h"
+#include "pdl_command.h"
+
+#define MAX_PART_NAME	30
+struct dl_file_info {
+	disk_partition_t *ptn;
+	uchar *start_addr;
+	u64 total_size;
+	u64 recv_size;
+	char part_name[MAX_PART_NAME];
+};
+
+static struct dl_file_info dl_file;
+
+static uchar *download_buf;
+static unsigned long download_max_size;
+static block_dev_desc_t *mmc_blkdev = NULL;
+
+int emmc_data_start(const char *part_name, unsigned long file_size)
+{
+	disk_partition_t *ptn = 0;
+	int blksz_shift;
+
+	ptn = partition_find_ptn(part_name);
+	if(!ptn) {
+		/* init/update partition table */
+		mmc_parts_format();
+		/* read again */
+		ptn = partition_find_ptn(part_name);
+		if(!ptn) {
+			int i;
+			pdl_info("invalid mtd part:%s  ",part_name);
+			for (i = 0; i < MAX_PART_NAME; i++)
+				pdl_info(" 0x%x ", part_name[i]);
+			pdl_info("\n");
+			return INVALID_PARTITION;
+		}
+	}
+
+	blksz_shift = LOG2(ptn->blksz);
+	pdl_info("found part '%s' start: 0x%lx length: 0x%lx bytes\n",
+		  ptn->name, ptn->start, (ptn->size << blksz_shift));
+
+	memset(&dl_file, 0, sizeof(dl_file));
+	strncpy(dl_file.part_name, part_name, MAX_PART_NAME);
+
+	if (file_size > (ptn->size << blksz_shift)) {
+		pdl_info("%s, download file too large, the size is:%ld\n",
+			__func__, file_size);
+		pdl_info("but the mmc part %s 's size is %ld\n",
+			ptn->name, ptn->size << blksz_shift);
+		return INVALID_SIZE;
+	}
+
+	dl_file.ptn = ptn;
+	dl_file.total_size = file_size;
+	dl_file.start_addr = download_buf;
+	dl_file.recv_size = 0;
+
+	return 0;
+}
+
+int emmc_data_midst(u8 *data, size_t size)
+{
+	if (!size) {
+		pdl_error("oops, send the zero length packet\n");
+		return INVALID_SIZE;
+	}
+	if (((dl_file.recv_size + size) > dl_file.total_size) ||
+		(dl_file.recv_size + size) > download_max_size) {
+		pdl_error("transfer size error receive (%lld), file (%lld)\n",
+			dl_file.recv_size + size, dl_file.total_size);
+		return INVALID_SIZE;
+	}
+
+	pdl_dbg("writing 0x%x bytes to offset: 0x%p\n",
+		size,  dl_file.start_addr);
+
+	memcpy(dl_file.start_addr, data, size);
+
+	dl_file.start_addr += size;
+	dl_file.recv_size += size;
+
+	return 0;
+}
+
+int emmc_data_end(uint32_t crc)
+{
+	sparse_header_t *sparse_header = (sparse_header_t *)download_buf;
+	disk_partition_t *ptn = dl_file.ptn;
+	loff_t write_bytes = dl_file.recv_size;
+	int ret;
+
+	if (!strcmp(dl_file.part_name, "factorydata")) {
+		pdl_info("flash to mmc part %s\n", ptn->name);
+		ret = factory_update_all(download_buf, dl_file.recv_size);
+		if (ret) {
+			pdl_error("oops, flash to mmc error %d\n", ret);
+			return OPERATION_FAILED;
+		}
+		return 0;
+	}
+
+	if (!strcmp(dl_file.part_name, PRDINFO_PART_NAME)) {
+		pdl_info("flash to mmc part %s\n", ptn->name);
+		ret = prdinfo_update_all((char *)download_buf, dl_file.recv_size);
+		if (ret) {
+			pdl_error("oops, flash to mmc error %d\n", ret);
+			return OPERATION_FAILED;
+		}
+		return 0;
+	}
+
+	/* verify data crc before write to mmc */
+	if(crc) {
+		uint32_t new_crc = crc32(0, (unsigned char *)download_buf, write_bytes);
+		if(crc != new_crc) {
+			pdl_info("CRC verify failed, expect %#x, got %#x.\n", crc, new_crc);
+			return CHECKSUM_ERROR;
+		} else {
+			pdl_info("CRC verify success, %#x.\n", crc);
+		}
+	}
+
+	/* Using to judge if ext4 file system */
+	if (sparse_header->magic != SPARSE_HEADER_MAGIC) {
+		pdl_info("flash to mmc part %s\n", ptn->name);
+		ret = partition_write_bytes(mmc_blkdev, ptn,
+			&write_bytes, download_buf);
+	} else {
+		pdl_info("unsparese flash part %s start %lx, size %ld blks\n",
+				ptn->name, ptn->start, ptn->size);
+		ret = partition_unsparse(mmc_blkdev, ptn, download_buf,
+			ptn->start, ptn->size);
+	}
+	if (ret) {
+		pdl_error("oops, flash to mmc error %d\n", ret);
+		return OPERATION_FAILED;
+	}
+
+	prdinfo_set_pdl_image_download_result((char *)ptn->name, 1);
+	pdl_info("END: total flashed %lld to mmc\n", write_bytes);
+	return 0;
+}
+
+
+int emmc_read_partition(const char *part_name, unsigned char *data, size_t size,
+			size_t *actual_len)
+{
+	disk_partition_t *ptn;
+	loff_t read_bytes = size;
+	int ret;
+
+	if(!mmc_blkdev) {
+		mmc_blkdev = get_dev_by_name(CONFIG_MMC_DEV_NAME);
+		if (!mmc_blkdev)
+			return DEVICE_ERROR;
+	}
+
+	ptn = partition_find_ptn(part_name);
+	if(!ptn) {
+		/* init/update partition table */
+		mmc_parts_format();
+		/* read again */
+		ptn = partition_find_ptn(part_name);
+		if(!ptn) {
+			pdl_error("partition table doesn't exist");
+			return INVALID_PARTITION;
+		}
+	}
+
+	pdl_dbg("%s from %s\n", __func__, part_name);
+
+	if (!strcmp(part_name, "factorydata")) {
+		size = factory_get_all(data);
+		if (size == 0) {
+			pdl_error("read from emmc error\n");
+			return DEVICE_ERROR;
+		}
+	} else  {
+		ret = partition_read_bytes(mmc_blkdev, ptn, &read_bytes, data);
+		if(ret < 0) {
+			pdl_error("read from emmc error\n");
+			return DEVICE_ERROR;
+		}
+	}
+	if(actual_len)
+		*actual_len = size;
+
+	pdl_dbg("read actrual %d ok \n", *actual_len);
+	return 0;
+}
+
+int emmc_write_partition(const char *part_name, unsigned char *data, size_t size)
+{
+	disk_partition_t *ptn;
+	loff_t write_bytes = size;
+	int ret;
+
+	if(!mmc_blkdev) {
+		mmc_blkdev = get_dev_by_name(CONFIG_MMC_DEV_NAME);
+		if (!mmc_blkdev)
+			return DEVICE_ERROR;
+	}
+
+	ptn = partition_find_ptn(part_name);
+	if(!ptn) {
+		/* init/update partition table */
+		mmc_parts_format();
+		/* read again */
+		ptn = partition_find_ptn(part_name);
+		if(!ptn) {
+			pdl_error("partition table doesn't exist");
+			return INVALID_PARTITION;
+		}
+	}
+
+	pdl_dbg("%s write to %s\n", __func__, part_name);
+
+	if (!strcmp(part_name, "factorydata")) {
+		return factory_update_all(data, size);
+	} else  {
+		ret = partition_write_bytes(mmc_blkdev, ptn, &write_bytes, data);
+		if(ret < 0) {
+			pdl_error("write to emmc error\n");
+			return DEVICE_ERROR;
+		}
+	}
+
+	pdl_dbg("write actrual %u ok \n", size);
+	return 0;
+}
+
+extern struct mtd_device *current_mtd_dev;
+
+int emmc_format_flash(void)
+{
+	int ret;
+	lbaint_t start = 0;
+	lbaint_t count = 0;
+	disk_partition_t *ptn_old, *ptn_new;
+
+	if (!mmc_blkdev) {
+		mmc_blkdev = get_dev_by_name(CONFIG_MMC_DEV_NAME);
+		if (!mmc_blkdev)
+			return DEVICE_ERROR;
+	}
+	count = mmc_blkdev->lba;
+
+	ptn_old = partition_find_ptn("factorydata");
+	factory_load();
+
+	pdl_info("refresh partition table\n");
+	ret = mmc_parts_format();
+	if (ret) {
+		pdl_error("refresh partition table fail %d\n", ret);
+		return DEVICE_ERROR;
+	}
+
+	/* if 'factorydata' part is not changed, don't
+	   erase '0' offset to the end offset of 'factorydata' */
+	ptn_new = partition_find_ptn("factorydata");
+	if (ptn_old && ptn_new) {
+		if(ptn_old->start == ptn_new->start &&
+			ptn_old->size == ptn_new->size)
+			start = ptn_new->start + ptn_new->size;
+	}
+
+	count -= start;
+	pdl_info("format the whole mmc, from %ld, %ld blocks\n", start, count);
+	ret = mmc_blkdev->block_erase(CONFIG_MMC_DEV_NUM, start, count);
+	if (ret != count) {
+		pdl_error("mmc format partition fail %d\n", ret);
+		return DEVICE_ERROR;
+	}
+
+	/* if 'factorydata' was erased, write back */
+	if (!start)
+		factory_burn();
+
+	return 0;
+}
+
+int emmc_erase_partition(const char *part_name)
+{
+	disk_partition_t *ptn;
+	int ret;
+
+	if(!mmc_blkdev) {
+		mmc_blkdev = get_dev_by_name(CONFIG_MMC_DEV_NAME);
+		if (!mmc_blkdev)
+			return DEVICE_ERROR;
+	}
+
+	ptn = partition_find_ptn(part_name);
+	if(!ptn) {
+		/* init/update partition table */
+		mmc_parts_format();
+		/* read again */
+		ptn = partition_find_ptn(part_name);
+		if(!ptn) {
+			pdl_error("partition table doesn't exist");
+			return INVALID_PARTITION;
+		}
+	}
+
+	pdl_info("erase the mmc part %s\n", part_name);
+	ret = partition_erase_blks(mmc_blkdev, ptn, &ptn->size);
+	if (ret) {
+		pdl_error("erase parttion fail\n");
+		return DEVICE_ERROR;
+	}
+	return 0;
+}
+
+int pdl_emmc_init(void)
+{
+	download_buf = (unsigned char *)SCRATCH_ADDR;
+	download_max_size = FB_DOWNLOAD_BUF_SIZE;
+	mmc_blkdev = get_dev_by_name(CONFIG_MMC_DEV_NAME);
+	if (!mmc_blkdev)
+		return DEVICE_ERROR;
+	pdl_dbg("download buffer %p, max size %ld\n", download_buf, download_max_size);
+	return 0;
+}
+
diff --git a/pdl/pdl-2/pdl_emmc.h b/pdl/pdl-2/pdl_emmc.h
new file mode 100644
index 0000000000..de70bdb45c
--- /dev/null
+++ b/pdl/pdl-2/pdl_emmc.h
@@ -0,0 +1,14 @@
+#ifndef __PDL_EMMC_H_
+#define __PDL_EMMC_H_
+
+int emmc_data_start(const char *part_name, unsigned long file_size);
+int emmc_data_midst(u8 *data, size_t size);
+int emmc_data_end(uint32_t crc);
+int emmc_read_partition(const char *part_name, unsigned char *data, size_t size,
+			size_t *actual_len);
+int emmc_write_partition(const char *part_name, unsigned char *data, size_t size);
+int emmc_format_flash(void);
+int emmc_erase_partition(const char *part_name);
+int pdl_emmc_init(void);
+#endif
+
diff --git a/pdl/pdl-2/pdl_main.c b/pdl/pdl-2/pdl_main.c
new file mode 100644
index 0000000000..4bbe2b072f
--- /dev/null
+++ b/pdl/pdl-2/pdl_main.c
@@ -0,0 +1,66 @@
+#include <asm/types.h>
+#include <common.h>
+#include <command.h>
+#include <asm/arch/rda_sys.h>
+#include <malloc.h>
+#include "pdl_command.h"
+#include "packet.h"
+#include "cmd_defs.h"
+#include "pdl_engine.h"
+#include "pdl_debug.h"
+#include "pdl_channel.h"
+#include <usb/usbserial.h>
+
+int pdl_main(void)
+{
+	int ret = 0;
+	pdl_info("start pdl2...\n");
+
+	drv_usbser_init();
+	pdl_usb_channel_register();
+	pdl_init_packet_channel();
+	ret = pdl_command_init();
+	if(ret) {
+		pdl_info("pdl init failed, power down..\n");
+		pdl_send_rsp(ret);
+		shutdown_system();
+	}
+
+	/* hack serial_puts(), to save all prints to log buffer */
+	pdl_init_serial();
+
+	pdl_cmd_register(CONNECT, sys_connect);
+	pdl_cmd_register(START_DATA, data_start);
+	pdl_cmd_register(MID_DATA, data_midst);
+	pdl_cmd_register(END_DATA, data_end);
+	pdl_cmd_register(EXEC_DATA, data_exec);
+	pdl_cmd_register(READ_PARTITION, read_partition);
+	pdl_cmd_register(READ_PARTITION_TABLE, read_partition_table);
+	pdl_cmd_register(FORMAT_FLASH, format_flash);
+	pdl_cmd_register(READ_IMAGE_ATTR, read_image_attr);
+	pdl_cmd_register(ERASE_PARTITION, erase_partition);
+	pdl_cmd_register(NORMAL_RESET, reset_machine);
+	pdl_cmd_register(POWER_OFF, poweroff_machine);
+	pdl_cmd_register(GET_VERSION, get_pdl_version);
+	pdl_cmd_register(SET_PDL_DBG, set_pdl_dbg);
+	pdl_cmd_register(CHECK_PARTITION_TABLE, check_partition_table);
+	pdl_cmd_register(IMAGE_LIST, recv_image_list);
+	pdl_cmd_register(HW_TEST, hw_test);
+	pdl_cmd_register(GET_PDL_LOG, get_pdl_log);
+	pdl_cmd_register(DOWNLOAD_FINISH, download_finish);
+
+	pdl_send_rsp(ACK);
+	pdl_handler(NULL);
+	return 0;
+}
+
+#if defined(CONFIG_CMD_PDL2)
+int do_pdl2(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
+{
+	pdl_main();
+	return 0;
+}
+
+U_BOOT_CMD(pdl2, 1, 1, do_pdl2,
+           "android fastboot protocol", "flash image to nand");
+#endif
diff --git a/pdl/pdl-2/pdl_nand.c b/pdl/pdl-2/pdl_nand.c
new file mode 100644
index 0000000000..db364e9e0f
--- /dev/null
+++ b/pdl/pdl-2/pdl_nand.c
@@ -0,0 +1,685 @@
+#include <common.h>
+#include <asm/types.h>
+#include "packet.h"
+#include <linux/string.h>
+#include <jffs2/load_kernel.h>
+#include <nand.h>
+#include <malloc.h>
+#include <asm/arch/spl_board_info.h>
+#include <asm/arch/mtdparts_def.h>
+#include <asm/arch/rda_sys.h>
+#include <asm/arch/factory.h>
+#include <asm/arch/prdinfo.h>
+#include "cmd_defs.h"
+#include "pdl_debug.h"
+#include "pdl.h"
+#include "pdl_command.h"
+#include "pdl_nand.h"
+#include <linux/mtd/nand.h>
+#include <mtd/nand/rda_nand.h>
+
+#define MAX_PART_NAME	30
+
+struct dl_file_info {
+	struct mtd_info *nand;
+
+	struct part_info *part;
+	unsigned long start_offset; /* partition start offset on flash */
+	unsigned long end_offset; /* partition end offset on flash */
+	unsigned long write_offset; /* write offset on flash */
+
+	unsigned char *download_bufp; /* download buffer pointer */
+	unsigned long download_size; /* data size in download buffer */
+
+	unsigned long total_size; /* image file size */
+	unsigned long recv_size; /* received data size */
+
+	char part_name[MAX_PART_NAME];
+	char vol_name[MAX_PART_NAME];
+};
+
+static struct dl_file_info dl_file;
+static unsigned char *download_buf;
+static unsigned long download_max_size = (24 * 1024 *1024);
+
+extern int mtdparts_init_default(void);
+extern int mtdparts_init_from_ptbl(void);
+extern int mtdparts_save_ptbl(int need_erase);
+
+static int __erase_partition(nand_info_t *nand,
+				struct part_info *part)
+{
+	nand_erase_options_t opts;
+	int ret;
+
+	pdl_info("%s: erase part '%s', offset 0x%llx size 0x%llx\n", __func__,
+			part->name, part->offset, part->size);
+	memset(&opts, 0, sizeof(opts));
+	opts.offset = (loff_t) part->offset;
+	opts.length = (loff_t) part->size;
+	opts.jffs2 = 0;
+	opts.quiet = 0;
+
+	pdl_dbg("opts off  0x%08x\n", (uint32_t) opts.offset);
+	pdl_dbg("opts size 0x%08x\n", (uint32_t) opts.length);
+	ret = nand_erase_opts(nand, &opts);
+	if (!ret) {
+		part->dirty = 0;
+	}
+	return ret;
+}
+
+static int pdl_ubi_start_write(void)
+{
+	int ret = 0;
+
+	/* prepart to write ubi volume image, system/vendor partition */
+#ifdef MTDPARTS_UBI_DEF
+	pdl_info("init ubi part '%s'\n", dl_file.part_name);
+	ret = ubi_part_scan(dl_file.part_name);
+	if(ret) {
+		pdl_info("ubi init failed.\n");
+		return OPERATION_FAILED;
+	}
+
+	ret = ubi_check_default_vols(MTDPARTS_UBI_DEF);
+	if(ret) {
+		pdl_info("ubi volumes check failed.\n");
+		return OPERATION_FAILED;
+	}
+
+	ret = ubi_prepare_write_vol(dl_file.vol_name, dl_file.total_size);
+#endif
+
+	return ret;
+}
+
+typedef enum {
+	PART_RAW = 0,
+	PART_FACTORYDATA,
+	PART_PRDINFO,
+	PART_UBI_VOL,
+} PART_TYPE;
+static int update_part_type = PART_RAW;
+int nand_data_start(const char *part_name, unsigned long file_size)
+{
+	struct part_info *part;
+	struct mtd_device *dev;
+	u8 part_num;
+	int ret;
+
+	update_part_type = PART_RAW;
+	memset(&dl_file, 0, sizeof(dl_file));
+	strncpy(dl_file.part_name, part_name, MAX_PART_NAME-1);
+	strncpy(dl_file.vol_name, part_name, MAX_PART_NAME-1);
+
+#ifdef MTDPARTS_UBI_DEF /* all ubi volumes are in one ubi part */
+	if(strstr(MTDPARTS_UBI_DEF, part_name)) {
+		strncpy(dl_file.part_name, MTDPARTS_UBI_PART_NAME, MAX_PART_NAME-1);
+		strncpy(dl_file.vol_name, part_name, MAX_PART_NAME-1);
+		pdl_info("'%s' is a ubi volume in '%s' part.\n",
+						dl_file.vol_name, dl_file.part_name);
+		update_part_type = PART_UBI_VOL;
+	}
+#endif
+
+	ret = find_dev_and_part(dl_file.part_name, &dev, &part_num, &part);
+	if (ret) {
+		int i;
+		pdl_info("invalid mtd part:%s  ", dl_file.part_name);
+		for (i = 0; i < MAX_PART_NAME; i++)
+			pdl_info(" 0x%x ", dl_file.part_name[i]);
+		pdl_info("\n");
+		return (INVALID_PARTITION);
+	}
+
+	pdl_info("found part '%s' offset: 0x%llx length: 0x%llx id: %d is %s\n",
+		  part->name, part->offset, part->size, dev->id->num,
+		  part->dirty ? "dirty" : "clean");
+	dl_file.part = part;
+	dl_file.end_offset = part->offset + part->size;
+	dl_file.nand = &nand_info[dev->id->num];
+
+	if (file_size > part->size) {
+		pdl_info("%s, download file too large, the size is:%ld\n",
+			__func__, file_size);
+		pdl_info("but the mtd part %s 's size is %llu\n",
+			part->name, part->size);
+		return INVALID_SIZE;
+	}
+
+	if (!strcmp(part->name, "factorydata")) {
+		pdl_dbg("update factorydata\n");
+		update_part_type = PART_FACTORYDATA;
+	} else if (!strcmp(part->name, PRDINFO_PART_NAME)) {
+		pdl_dbg("update prdinfo\n");
+		update_part_type = PART_PRDINFO;
+	}
+	//erase the mtd part;
+	if (part->dirty
+			&& (update_part_type == PART_RAW)
+		) {
+		ret = __erase_partition(dl_file.nand, part);
+		if (ret) {
+			pdl_info("erase mtd partitions error\n");
+			return DEVICE_ERROR;
+		}
+	}
+	/*now we'll write data to the partition, so dirty the part */
+	part->dirty = 1;
+
+	dl_file.total_size = file_size;
+	dl_file.start_offset = part->offset;
+	dl_file.write_offset = part->offset;
+	dl_file.download_bufp = download_buf;
+	dl_file.recv_size = 0;
+	dl_file.download_size = 0;
+
+	if((update_part_type == PART_UBI_VOL) && pdl_ubi_start_write()) {
+		pdl_error("can't write ubi volume %s\n", dl_file.vol_name);
+		return DEVICE_ERROR;
+	}
+
+	return 0;
+}
+
+#ifdef _TGT_AP_DDR_AUTO_CALI_ENABLE
+static void add_ddr_cal_val_to_bootloader(void)
+{
+	struct nand_chip *chip = dl_file.nand->priv;
+	struct rda_nand_info *info = chip->priv;
+	unsigned int cal_addr_flag_offs;
+	spl_bd_t * spl_board_info = (spl_bd_t *)CONFIG_SPL_BOARD_INFO_ADDR;
+	u16 ddr_cal[2] = {0};
+	if (strcmp(dl_file.part->name, "bootloader") == 0){
+		if (spl_board_info->spl_ddr_cal_info.ddr_auto_cal_flag == CONIFG_DDR_CAL_VAL_FLAG)
+			ddr_cal[0] = spl_board_info->spl_ddr_cal_info.ddr_auto_cal_flag;
+			ddr_cal[1] = spl_board_info->spl_ddr_cal_info.ddr_auto_cal_val[0];
+			/*SPL is 2K in every nand page, hardware limit in 8810 chip*/
+			cal_addr_flag_offs = (((spl_board_info->spl_ddr_cal_info.ddr_auto_cal_offs / 2048)
+							* 2048) * info->spl_adjust_ratio) / 2  +
+							(spl_board_info->spl_ddr_cal_info.ddr_auto_cal_offs % 2048);
+			memcpy((void *)(download_buf + cal_addr_flag_offs),
+				 (void *)ddr_cal, 4);
+	}
+}
+#endif
+
+static int pdl_nand_data_write(int data_end)
+{
+	unsigned int bad_blocks = 0;
+	unsigned long write_bytes = dl_file.download_size;
+	int ret = 0;
+
+	pdl_info("flash data to '%s', size %lu bytes.\n",
+			dl_file.vol_name, write_bytes);
+
+	/* write ubi volume image, system/vendor partition */
+	if(update_part_type == PART_UBI_VOL) {
+#ifdef MTDPARTS_UBI_DEF
+		ret = ubi_do_write_vol(dl_file.vol_name, download_buf, dl_file.download_size);
+
+		/* clear download buffer position & size */
+		dl_file.download_bufp = download_buf;
+		dl_file.download_size = 0;
+
+		if(data_end)
+			ubi_finish_write_vol(dl_file.vol_name);
+#endif
+
+	} else if (update_part_type == PART_FACTORYDATA) {
+		ret = factory_update_all(download_buf, write_bytes);
+	} else if (update_part_type == PART_PRDINFO) {
+		ret = prdinfo_update_all((char *)download_buf, write_bytes);
+	} else {
+
+#ifdef _TGT_AP_DDR_AUTO_CALI_ENABLE
+		/* add DDR calibration value to bootloader image, it's a hack, FIXME */
+		add_ddr_cal_val_to_bootloader();
+#endif
+
+		ret = nand_write_skip_bad_new(dl_file.nand, dl_file.write_offset,
+				(size_t *)&write_bytes,
+				dl_file.end_offset,
+				download_buf,
+				0, &bad_blocks);
+
+		/* clear download buffer position & size */
+		dl_file.download_bufp = download_buf;
+		dl_file.download_size = 0;
+		/* update write offset */
+		dl_file.write_offset += write_bytes;
+		dl_file.write_offset += bad_blocks * dl_file.nand->erasesize;
+
+	}
+	if (ret) {
+		pdl_error("oops, flash to nand error %d\n", ret);
+		return OPERATION_FAILED;
+	}
+
+	return 0;
+}
+
+int nand_data_midst(u8 *data, size_t size)
+{
+	int ret;
+	extern uint8_t pdl_extended_status;
+
+	if (!size) {
+		pdl_error("oops, send the zero length packet\n");
+		return INVALID_SIZE;
+	}
+	if (((dl_file.recv_size + size) > dl_file.total_size)) {
+		pdl_error("transfer size error receive (%lu), file (%lu)\n",
+			dl_file.recv_size + size, dl_file.total_size);
+		return INVALID_SIZE;
+	}
+
+	/* if buffer is full */
+	if((dl_file.download_size + size) > download_max_size) {
+		if (pdl_extended_status)
+			pdl_send_rsp(ACK_AGAIN_FLASH);
+		ret = pdl_nand_data_write(0);
+		if(ret) {
+			pdl_info("ERROR: '%s' partition write failed.\n", dl_file.part_name);
+			return ret;
+		}
+	}
+
+	pdl_dbg("writing 0x%x bytes to offset: 0x%08lx\n",
+		size,  (unsigned long)dl_file.download_bufp);
+
+	/* save data to buffer */
+	memcpy(dl_file.download_bufp, data, size);
+
+	dl_file.download_bufp += size;
+	dl_file.download_size += size;
+	dl_file.recv_size += size;
+
+	return 0;
+}
+
+static int pdl_nand_data_verify(uint32_t crc)
+{
+	unsigned int bad_blocks = 0;
+	unsigned long read_bytes = 0;
+	unsigned long total_size = dl_file.recv_size;
+	unsigned long read_offset = 0;
+	uint32_t new_crc = 0;
+	int ret = 0;
+
+	if(!crc)
+		return 0;
+
+	/* read back data from nand, for crc verify */
+	pdl_info("Read back data from flash to do CRC verify.\n");
+
+	if(update_part_type == PART_UBI_VOL) {
+#ifdef MTDPARTS_UBI_DEF
+		while(1) {
+			read_bytes = (total_size > download_max_size) ? download_max_size : total_size;
+			ret = ubi_read_vol(dl_file.vol_name, read_offset, download_buf, read_bytes);
+			if(ret)
+				break;
+
+			new_crc = crc32(new_crc, download_buf, read_bytes);
+
+			if(read_bytes >= total_size)
+				break;
+			total_size -= read_bytes;
+			read_offset += read_bytes;
+		}
+#endif
+
+	} else if (update_part_type == PART_RAW) {
+		read_offset = dl_file.start_offset;
+		while(1) {
+			read_bytes = (total_size > download_max_size) ? download_max_size : total_size;
+			ret = nand_read_skip_bad_new(dl_file.nand, read_offset,
+						(size_t *)&read_bytes, download_buf, &bad_blocks);
+			if(ret)
+				break;
+
+			new_crc = crc32(new_crc, download_buf, read_bytes);
+
+			if(read_bytes >= total_size)
+				break;
+			total_size -= read_bytes;
+			read_offset += read_bytes + (bad_blocks * dl_file.nand->erasesize);
+		}
+
+	} else {
+		return 0;
+	}
+
+	if (ret) {
+		pdl_error("oops, read data from nand error %d\n", ret);
+		return OPERATION_FAILED;
+	}
+
+	if(crc != new_crc) {
+		pdl_info("CRC verify failed, expect %#x, got %#x.\n", crc, new_crc);
+		return CHECKSUM_ERROR;
+	} else {
+		pdl_info("CRC verify success, %#x.\n", crc);
+	}
+
+	return 0;
+}
+
+int nand_data_end(uint32_t crc)
+{
+	int ret;
+
+	/* force to verify CRC, ignore bootloader/factorydata */
+	if ((strcmp(dl_file.part->name, "bootloader") == 0 ||
+		 strcmp(dl_file.part->name, "factorydata") == 0) ||
+		 strcmp(dl_file.part->name, PRDINFO_PART_NAME) == 0) {
+		crc = 0;
+	} else if(!crc) {
+		pdl_info("ERROR: CRC checking is necessary!");
+		pdl_info("ERROR: please use the new version of download tools.\n");
+		return CHECKSUM_ERROR;
+	}
+
+	ret = pdl_nand_data_write(1);
+	if(ret) {
+		pdl_info("ERROR: '%s' partition write failed.\n", dl_file.part_name);
+		return ret;
+	}
+
+	ret = pdl_nand_data_verify(crc);
+	if(ret) {
+		pdl_info("ERROR: '%s' partition data verify failed.\n", dl_file.part_name);
+		return ret;
+	}
+
+	pdl_info("END: total flashed %ld to nand\n", dl_file.recv_size);
+
+	dl_file.download_bufp = download_buf;
+	dl_file.download_size = 0;
+	update_part_type = PART_RAW;
+
+	/* the mtd partition table is saved in 'bootloader' partition,
+	 * if 'bootloader' is updated, need to re-write the partition table. */
+	if(strcmp(dl_file.part->name, "bootloader") == 0) {
+		mtdparts_save_ptbl(1);
+	}
+
+	prdinfo_set_pdl_image_download_result(dl_file.part->name, 1);
+	return 0;
+}
+
+
+int nand_read_partition(const char *part_name, u8 *data, size_t size,
+			size_t *actual_len)
+{
+	struct part_info *part = NULL;
+        u8 part_num;
+	struct mtd_info *nand = NULL;
+	struct mtd_device *dev;
+	int ret;
+
+	if(size > download_max_size) {
+		pdl_info("can't read partition '%s', size is too large\n", part_name);
+		return OPERATION_FAILED;
+	}
+
+#ifdef MTDPARTS_UBI_DEF /* all ubi volumes are in one ubi part */
+	if(strstr(MTDPARTS_UBI_DEF, part_name)) {
+		size_t vol_size = ubi_sizeof_vol(part_name);
+		size = (size > vol_size) ? vol_size: size;
+		pdl_info("'%s' is a ubi volume in '%s' part, of size %zu.\n",
+			 part_name, MTDPARTS_UBI_PART_NAME, vol_size);
+		ret = ubi_part_scan(MTDPARTS_UBI_PART_NAME);
+		if(ret) {
+			pdl_info("ubi init failed.\n");
+			return OPERATION_FAILED;
+		}
+
+		ret = ubi_read_vol(part_name, 0, data, size);
+		if(ret) {
+			pdl_info("read ubi volume error: %s\n", part_name);
+			return DEVICE_ERROR;
+		}
+		if(actual_len)
+			*actual_len = size;
+		pdl_info("read volume %s ok, %u bytes\n", part_name, size);
+		return 0;
+	}
+#endif
+
+	ret = find_dev_and_part(part_name, &dev, &part_num, &part);
+	if (ret) {
+		pdl_error("%s: invalid mtd part '%s'\n",__func__, part_name);
+		return INVALID_PARTITION;
+	}
+
+	pdl_info("%s: read %#x bytes from '%s'\n", __func__, size, part_name);
+	nand = &nand_info[dev->id->num];
+	pdl_dbg("found part '%s' offset: 0x%llx length: %d/%llu id: %d\n",
+		  part->name, part->offset, size, part->size, dev->id->num);
+
+	size = (size < part->size) ? size : part->size;
+
+	if (!strcmp(part_name, "factorydata")) {
+		size = factory_get_all(data);
+		if (size <= 0 ) {
+			return DEVICE_ERROR;
+		}
+	} else {
+		ret = nand_read_skip_bad(nand, part->offset, &size,
+			(u_char *)data);
+		if(ret < 0) {
+			pdl_error("%s: read from nand error\n", __func__);
+			return DEVICE_ERROR;
+		}
+	}
+	if(actual_len)
+		*actual_len = size;
+
+	pdl_dbg("%s: done!", __func__);
+	return 0;
+}
+
+int nand_write_partition(const char *part_name, unsigned char *data, size_t size)
+{
+	struct part_info *part = NULL;
+	u8 part_num;
+	struct mtd_info *nand = NULL;
+	struct mtd_device *dev;
+	int ret;
+	u32 bad_blocks = 0;
+
+	ret = find_dev_and_part(part_name, &dev, &part_num, &part);
+	if (ret) {
+		pdl_error("%s: invalid mtd part '%s'\n",__func__, part_name);
+		return INVALID_PARTITION;
+	}
+
+	pdl_info("%s: write %#x bytes to '%s'\n", __func__, size, part_name);
+	nand = &nand_info[dev->id->num];
+	pdl_dbg("found part '%s' offset: 0x%llx length: %d/%llu id: %d\n",
+		  part->name, part->offset, size, part->size, dev->id->num);
+
+	size = (size < part->size) ? size : part->size;
+
+	if (!strcmp(part_name, "factorydata")) {
+		return factory_update_all(data, size);
+	} else {
+		ret = nand_write_skip_bad_new(nand, part->offset, &size,
+			part->offset + part->size,
+			(u_char *)data, 0, &bad_blocks);
+		part->dirty = 1;
+		if(ret < 0) {
+			pdl_error("%s: write to nand error.\n", __func__);
+			return DEVICE_ERROR;
+		}
+	}
+
+	pdl_dbg("%s: done!\n", __func__);
+	return 0;
+}
+
+extern struct mtd_device *current_mtd_dev;
+
+extern int mtdparts_ptbl_check_factorydata(int *same);
+int nand_format_flash(void)
+{
+	nand_erase_options_t opts;
+	nand_info_t *nand;
+	u8 nand_num= 0;
+	int same = 0;
+
+	/* re-init partition table by default */
+	if(mtdparts_init_default()) {
+		pdl_info("mtdparts init failed, abandon flash format..\n");
+		return DEVICE_ERROR;
+	}
+
+	pdl_info("format the whole flash part\n");
+	if (!current_mtd_dev) {
+		pdl_info("%s mtd device info error\n", __func__);
+		return DEVICE_ERROR;
+	}
+	/*
+	 *erase all flash parts
+	 */
+	nand_num = current_mtd_dev->id->num;
+	nand = &nand_info[nand_num];
+	if (!nand) {
+		pdl_info("%s mtd device info error\n", __func__);
+		return DEVICE_ERROR;
+	}
+	memset(&opts, 0, sizeof(opts));
+	opts.offset = 0;
+	opts.length = (loff_t) nand->size;
+	opts.jffs2 = 0;
+	opts.quiet = 0;
+	opts.scrub = 1;
+
+	/* if partition bootloader & factorydata is not changed, don't erase them */
+	mtdparts_ptbl_check_factorydata(&same);
+	if(same) {
+		struct part_info *part;
+		struct mtd_device *dev;
+		u8 part_num;
+		int ret = find_dev_and_part("factorydata", &dev, &part_num, &part);
+		if (!ret) {
+			opts.offset = part->offset + part->size;
+			opts.length -= opts.offset;
+		}
+	}
+	factory_load();
+
+	pdl_dbg("opts off  0x%08x\n", (uint32_t) opts.offset);
+	pdl_dbg("opts size 0x%08x\n", (uint32_t) opts.length);
+	pdl_dbg("nand write size 0x%08x\n", nand->writesize);
+	pdl_info("erase 0x%llx bytes to '%s' offset: 0x%llx\n",
+		  opts.length, nand->name, opts.offset);
+	nand_erase_opts(nand, &opts);
+	mtdparts_clear_all_dirty(current_mtd_dev);
+
+	/* enable dirty for bootloader & factorydata part, if need */
+	if(opts.offset > 0) {
+		struct part_info *part;
+		struct mtd_device *dev;
+		u8 part_num;
+		int ret = find_dev_and_part("bootloader", &dev, &part_num, &part);
+		if (!ret) {
+			part->dirty = 1;
+		}
+		ret = find_dev_and_part("factorydata", &dev, &part_num, &part);
+		if (!ret) {
+			part->dirty = 1;
+		}
+	}
+
+	/* if 'factorydata' was erased, write back */
+	if (opts.offset <= 0)
+		factory_burn();
+
+	return 0;
+}
+
+int nand_erase_partition(const char *part_name)
+{
+	struct part_info *part;
+	struct mtd_device *dev;
+	u8 part_num;
+	int ret;
+	struct mtd_info *nand;
+
+#ifdef MTDPARTS_UBI_DEF /* all ubi volumes are in one ubi part */
+	if(strstr(MTDPARTS_UBI_DEF, part_name)) {
+		pdl_info("'%s' is a ubi volume in '%s' part, erase volume.\n",
+						part_name, MTDPARTS_UBI_PART_NAME);
+		ret = ubi_part_scan(MTDPARTS_UBI_PART_NAME);
+		if(ret) {
+			pdl_info("ubi init failed.\n");
+			return OPERATION_FAILED;
+		}
+
+		ret = ubi_erase_vol((char *)part_name);
+		if(ret) {
+			pdl_info("erase ubi volume error: %s\n", part_name);
+			return DEVICE_ERROR;
+		}
+		pdl_info("erase ubi volume ok: %s\n", part_name);
+		return 0;
+	}
+#endif
+
+	ret = find_dev_and_part(part_name, &dev, &part_num, &part);
+	if (ret) {
+		pdl_error("%s: invalid mtd part '%s'\n", __func__, part_name);
+		return INVALID_PARTITION;
+	}
+
+	pdl_dbg("%s: erase part '%s'\n", __func__, part_name);
+	pdl_dbg("found part '%s' offset: 0x%llx length: 0x%llx id: %d\n",
+		  part->name, part->offset, part->size, dev->id->num);
+	nand = &nand_info[dev->id->num];
+
+	//erase the mtd part;
+	ret = __erase_partition(nand, part);
+	if (ret) {
+		pdl_error("%s: erase part error\n", __func__);
+		return DEVICE_ERROR;
+	}
+
+	pdl_dbg("%s: done!", __func__);
+	return 0;
+}
+
+int pdl_nand_init(void)
+{
+	int ret;
+	download_buf = (unsigned char *)SCRATCH_ADDR;
+	download_max_size = 24*1024*1024;//FB_DOWNLOAD_BUF_SIZE;
+	pdl_dbg("download buffer %p, max size %ld\n", download_buf, download_max_size);
+
+	ret = mtdparts_init_from_ptbl();
+	/* if fail to load partition table, try default */
+	if(ret) {
+		ret = mtdparts_init_default();
+	}
+	if(ret) {
+		return DEVICE_ERROR;
+	}
+
+	/* check page size */
+#ifdef NAND_PAGE_SIZE
+	if(current_mtd_dev) {
+		nand_info_t *nand = &nand_info[current_mtd_dev->id->num];
+		if(nand->writesize != NAND_PAGE_SIZE) {
+			pdl_info("nand page size is %#x, expect %#x, not compatible.\n",
+					nand->writesize, NAND_PAGE_SIZE);
+			return DEVICE_INCOMPATIBLE;
+		}
+	}
+#endif
+
+	return 0;
+}
+
diff --git a/pdl/pdl-2/pdl_nand.h b/pdl/pdl-2/pdl_nand.h
new file mode 100644
index 0000000000..21df6c7ae3
--- /dev/null
+++ b/pdl/pdl-2/pdl_nand.h
@@ -0,0 +1,31 @@
+#ifndef __PDL_NAND_H_
+#define __PDL_NAND_H_
+
+int nand_data_start(const char *part_name, unsigned long file_size);
+int nand_data_midst(u8 *data, size_t size);
+int nand_data_end(uint32_t crc);
+int nand_read_partition(const char *part_name, unsigned char *data,
+		size_t size, size_t *actual_len);
+int nand_write_partition(const char *part_name, unsigned char *data,
+		size_t size);
+int nand_format_flash(void);
+int nand_erase_partition(const char *part_name);
+
+int pdl_nand_init(void);
+
+#ifdef MTDPARTS_UBI_DEF
+int ubi_part_scan(const char *part_name);
+int ubi_check_default_vols(const char *ubi_default_str);
+int ubi_erase_vol(const char *vol_name);
+int ubi_read_vol(const char *vol_name, loff_t offp, void *buf, size_t size);
+int ubi_update_vol(const char *vol_name, void *buf, size_t size);
+size_t ubi_sizeof_vol(const char *vol_name);
+
+/* write a volume by multi parts. */
+int ubi_prepare_write_vol(const char *volume, size_t size);
+int ubi_do_write_vol(const char *volume, void *buf, size_t size);
+int ubi_finish_write_vol(const char *volume);
+#endif
+
+#endif
+
diff --git a/slt.mk b/slt.mk
new file mode 100644
index 0000000000..1589f5b784
--- /dev/null
+++ b/slt.mk
@@ -0,0 +1,36 @@
+#
+# Copyright (C) 2007 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+TARGET_PLATFORM := $(TARGET_BOARD_PLATFORM)
+TARGET_BOARD := slt
+
+# enable internal storage by virtual FAT partition on nand
+TARGET_FAT_ON_NAND := false
+
+# enable internal storage by FAT partition with NFTL
+TARGET_FAT_NFTL := false
+
+TARGET_SYSTEMIMAGE_USE_EXT4 := true
+TARGET_USERIMAGES_USE_EXT4 := true
+
+BOARD_SYSTEMIMAGE_FILE_SYSTEM_TYPE := ext4
+BOARD_VENDORIMAGE_FILE_SYSTEM_TYPE := ext4
+
+PRODUCT_NAME := $(TARGET_BOARD)
+PRODUCT_DEVICE := $(TARGET_BOARD)
+PRODUCT_MODEL := RDA SmartPhone
+PRODUCT_BRAND := RDA
+PRODUCT_MANUFACTURER := Rdamicro
diff --git a/spl/.gitignore b/spl/.gitignore
deleted file mode 100644
index 7c8814709f..0000000000
--- a/spl/.gitignore
+++ /dev/null
@@ -1,4 +0,0 @@
-u-boot-spl
-u-boot-spl.bin
-u-boot-spl.lds
-u-boot-spl.map
diff --git a/spl/Makefile b/spl/Makefile
index ea7d4750fb..6c1b96a127 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -54,9 +54,14 @@ LIBS-$(CONFIG_SPL_FAT_SUPPORT) += fs/fat/libfat.o
 LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/libgeneric.o
 LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/libpower.o
 LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/libnand.o
+LIBS-$(CONFIG_SPL_EMMC_SUPPORT) += drivers/mmc/libmmc.o
 LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/libonenand.o
 LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/libdma.o
 LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/memory.o
+LIBS-$(CONFIG_SPL_USB_SUPPORT) += drivers/usb/gadget/libusb_gadget.o
+LIBS-$(CONFIG_SPL_MUSB_UDC_SUPPORT) += drivers/usb/musb/libusb_musb.o
+LIBS-$(CONFIG_SPL_RDA_PDL) += pdl/common/libpdl_common.o
+LIBS-$(CONFIG_SPL_RDA_PDL) += pdl/pdl-1/libpdl_stage.o
 
 ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
@@ -108,7 +113,7 @@ $(OBJTREE)/MLO:	$(obj)u-boot-spl.bin
 		-a $(CONFIG_SPL_TEXT_BASE) -d $< $@
 endif
 
-ALL-y	+= $(obj)u-boot-spl.bin
+ALL-y	+= $(obj)u-boot-spl.bin $(obj)u-boot-spl.img
 
 ifdef CONFIG_SAMSUNG
 ALL-y	+= $(obj)$(BOARD)-spl.bin
@@ -124,6 +129,20 @@ endif
 
 $(obj)u-boot-spl.bin:	$(obj)u-boot-spl
 	$(OBJCOPY) $(OBJCFLAGS) -O binary $< $@
+	@spl_size=`stat -c%s $@` && \
+	if [ "$$spl_size" -gt $(CONFIG_SPL_CODE_MAX_SIZE) ] ; then \
+	    echo "Error: $@ code size ($$spl_size) " \
+	         "larger than max size ($(CONFIG_SPL_CODE_MAX_SIZE))"; \
+	exit 1; \
+	fi
+
+$(obj)u-boot-spl.img:	$(obj)u-boot-spl.bin
+		$(XECHO)
+		$(XECHO) "	GEN	$(@F)"
+		$(OBJTREE)/tools/mkimage -A $(ARCH) -T standalone -C none \
+		-O u-boot -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) \
+		-n 'u-boot-spl' \
+		-d $< $@ $(STDOUT_NULL)
 
 GEN_UBOOT = \
 	UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) | \
@@ -136,13 +155,17 @@ $(obj)u-boot-spl:	depend $(START) $(LIBS) $(obj)u-boot-spl.lds
 	$(GEN_UBOOT)
 
 $(START):	depend
+	$(XECHO)
+	$(XECHO) "	MAKE	$(subst $(SPLTREE)/,,$@)"
 	$(MAKE) -C $(SRCTREE)/$(START_PATH) $@
 
 $(LIBS):	depend
+	$(XECHO)
+	$(XECHO) "	MAKE	$(dir $(subst $(SPLTREE)/,,$@))"
 	$(MAKE) -C $(SRCTREE)$(dir $(subst $(SPLTREE),,$@))
 
 $(obj)u-boot-spl.lds: $(LDSCRIPT) depend
-	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - < $< > $@
+	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -D__ASSEMBLY__ -P - < $< > $@
 
 depend:	$(obj).depend
 .PHONY: depend
diff --git a/spl/u-boot-spl b/spl/u-boot-spl
new file mode 100755
index 0000000000..2de8edc34d
--- /dev/null
+++ b/spl/u-boot-spl
diff --git a/spl/u-boot-spl.lds b/spl/u-boot-spl.lds
new file mode 100644
index 0000000000..001fde2269
--- /dev/null
+++ b/spl/u-boot-spl.lds
@@ -0,0 +1,44 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00100100;
+ . = ALIGN(4);
+ .text :
+ {
+  __start = .;
+  arch/arm/cpu/armv7/start.o (.text)
+   *(.text)
+ }
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+ . = ALIGN(4);
+ .data : {
+  *(.data)
+ }
+ . = ALIGN(4);
+ . = .;
+ . = ALIGN(4);
+ __image_copy_end = .;
+ _end = .;
+ . = __start + 49152 - 0x10 - 0x100;
+ . = ALIGN(4);
+ .ddrcal : {
+  __ddrcal_start = .;
+  . = __ddrcal_start + 0x10;
+  __ddrcal_end = .;
+ }
+ . = .;
+ . = ALIGN(4);
+ .bss :
+ {
+  . = ALIGN(4);
+  __bss_start = .;
+  *(.bss*)
+  . = ALIGN(4);
+  __bss_end__ = .;
+  ASSERT((ABSOLUTE(__bss_end__) < 0x00110000 - 512), "too big data in spl, don't exceed intrenal ram");
+
+ }
+}
diff --git a/spl/u-boot-spl.map b/spl/u-boot-spl.map
new file mode 100644
index 0000000000..10aff4ae0b
--- /dev/null
+++ b/spl/u-boot-spl.map
@@ -0,0 +1,2274 @@
+Archive member included because of file (symbol)
+
+/xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_udivsi3.o)
+                              arch/arm/cpu/armv7/rda/librda.o (__aeabi_uidiv)
+/xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_divsi3.o)
+                              drivers/mtd/nand/libnand.o (__aeabi_idiv)
+/xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_lshrdi3.o)
+                              drivers/mmc/libmmc.o (__aeabi_llsr)
+/xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_ashrdi3.o)
+                              drivers/mtd/nand/libnand.o (__aeabi_lasr)
+/xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_ashldi3.o)
+                              drivers/mmc/libmmc.o (__aeabi_llsl)
+/xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_aeabi_uldivmod.o)
+                              arch/arm/cpu/armv7/rda/librda.o (__aeabi_uldivmod)
+/xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_dvmd_lnx.o)
+                              /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_udivsi3.o) (__aeabi_idiv0)
+/xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(bpabi.o)
+                              /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_aeabi_uldivmod.o) (__gnu_uldivmod_helper)
+/xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_divdi3.o)
+                              /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(bpabi.o) (__divdi3)
+/xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_udivdi3.o)
+                              /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(bpabi.o) (__udivdi3)
+
+Discarded input sections
+
+ .data          0x00000000        0x0 arch/arm/cpu/armv7/start.o
+ .bss           0x00000000        0x0 arch/arm/cpu/armv7/start.o
+ .text          0x00000000        0x0 arch/arm/cpu/armv7/libarmv7.o
+ .text.v7_maint_dcache_all
+                0x00000000       0xbe arch/arm/cpu/armv7/libarmv7.o
+ .text.invalidate_dcache_all
+                0x00000000       0x10 arch/arm/cpu/armv7/libarmv7.o
+ .text.flush_dcache_all
+                0x00000000       0x10 arch/arm/cpu/armv7/libarmv7.o
+ .text.arm_init_before_mmu
+                0x00000000       0x22 arch/arm/cpu/armv7/libarmv7.o
+ .text.invalidate_icache_all
+                0x00000000       0x14 arch/arm/cpu/armv7/libarmv7.o
+ .text.__v7_outer_cache_enable
+                0x00000000        0x2 arch/arm/cpu/armv7/libarmv7.o
+ .text.__v7_outer_cache_disable
+                0x00000000        0x2 arch/arm/cpu/armv7/libarmv7.o
+ .text.__v7_outer_cache_flush_all
+                0x00000000        0x2 arch/arm/cpu/armv7/libarmv7.o
+ .text.__v7_outer_cache_inval_all
+                0x00000000        0x2 arch/arm/cpu/armv7/libarmv7.o
+ .text.cleanup_before_linux
+                0x00000000       0x1a arch/arm/cpu/armv7/libarmv7.o
+ .text.sdelay   0x00000000        0x6 arch/arm/cpu/armv7/libarmv7.o
+ .text.sr32     0x00000000       0x1c arch/arm/cpu/armv7/libarmv7.o
+ .text.wait_on_value
+                0x00000000       0x1a arch/arm/cpu/armv7/libarmv7.o
+ .data          0x00000000        0x0 arch/arm/cpu/armv7/libarmv7.o
+ .bss           0x00000000        0x0 arch/arm/cpu/armv7/libarmv7.o
+ .text          0x00000000        0x0 arch/arm/cpu/armv7/rda/librda.o
+ .text.timer_init
+                0x00000000       0x18 arch/arm/cpu/armv7/rda/librda.o
+ .text.reset_timer
+                0x00000000        0xe arch/arm/cpu/armv7/rda/librda.o
+ .text.usec2ticks
+                0x00000000        0x4 arch/arm/cpu/armv7/rda/librda.o
+ .text.ticks2usec
+                0x00000000        0x4 arch/arm/cpu/armv7/rda/librda.o
+ .text.get_tbclk
+                0x00000000        0x8 arch/arm/cpu/armv7/rda/librda.o
+ .text._serial_set_baudrate
+                0x00000000       0x10 arch/arm/cpu/armv7/rda/librda.o
+ .text._serial_disable_rtscts
+                0x00000000       0x10 arch/arm/cpu/armv7/rda/librda.o
+ .text._serial_init
+                0x00000000       0x20 arch/arm/cpu/armv7/rda/librda.o
+ .text._serial_deinit
+                0x00000000       0x10 arch/arm/cpu/armv7/rda/librda.o
+ .text._serial_tstc
+                0x00000000       0x10 arch/arm/cpu/armv7/rda/librda.o
+ .text.hwflow_onoff
+                0x00000000       0x24 arch/arm/cpu/armv7/rda/librda.o
+ .text.serial_setbrg
+                0x00000000        0x2 arch/arm/cpu/armv7/rda/librda.o
+ .text.hal_IfcOpen
+                0x00000000       0x18 arch/arm/cpu/armv7/rda/librda.o
+ .text.hal_IfcGetOwner
+                0x00000000       0x14 arch/arm/cpu/armv7/rda/librda.o
+ .text.enable_neon
+                0x00000000       0x50 arch/arm/cpu/armv7/rda/librda.o
+ .text.enable_caches
+                0x00000000       0x30 arch/arm/cpu/armv7/rda/librda.o
+ .text.print_cpuinfo
+                0x00000000       0x10 arch/arm/cpu/armv7/rda/librda.o
+ .text.rda_prod_id_get
+                0x00000000        0xc arch/arm/cpu/armv7/rda/librda.o
+ .text.rda_bond_id_get
+                0x00000000       0x10 arch/arm/cpu/armv7/rda/librda.o
+ .text.shutdown_system
+                0x00000000       0x14 arch/arm/cpu/armv7/rda/librda.o
+ .text.enable_vibrator
+                0x00000000       0x40 arch/arm/cpu/armv7/rda/librda.o
+ .text.enable_charger
+                0x00000000       0x30 arch/arm/cpu/armv7/rda/librda.o
+ .text.print_cur_time
+                0x00000000       0x3c arch/arm/cpu/armv7/rda/librda.o
+ .bss           0x00000000        0x0 arch/arm/cpu/armv7/rda/librda.o
+ .bss.hwflow    0x00000000        0x4 arch/arm/cpu/armv7/rda/librda.o
+ .text          0x00000000        0x0 arch/arm/lib/libarm.o
+ .text.__flush_cache
+                0x00000000        0x2 arch/arm/lib/libarm.o
+ .text.__flush_dcache_all
+                0x00000000        0xa arch/arm/lib/libarm.o
+ .text.__enable_caches
+                0x00000000        0xc arch/arm/lib/libarm.o
+ .text.cp_delay
+                0x00000000       0x18 arch/arm/lib/libarm.o
+ .text.cache_enable
+                0x00000000       0x8a arch/arm/lib/libarm.o
+ .text.cache_disable
+                0x00000000       0x28 arch/arm/lib/libarm.o
+ .text.__arm_init_before_mmu
+                0x00000000        0x2 arch/arm/lib/libarm.o
+ .text.icache_enable
+                0x00000000        0x8 arch/arm/lib/libarm.o
+ .text.icache_disable
+                0x00000000        0x8 arch/arm/lib/libarm.o
+ .text.icache_status
+                0x00000000        0xa arch/arm/lib/libarm.o
+ .text.dcache_enable
+                0x00000000        0x6 arch/arm/lib/libarm.o
+ .text.dcache_disable
+                0x00000000        0x6 arch/arm/lib/libarm.o
+ .text.dcache_status
+                0x00000000        0xa arch/arm/lib/libarm.o
+ .rodata.str1.1
+                0x00000000       0x1d arch/arm/lib/libarm.o
+ .data          0x00000000        0x0 arch/arm/lib/libarm.o
+ .bss           0x00000000        0x0 arch/arm/lib/libarm.o
+ .comment       0x00000000       0xca arch/arm/lib/libarm.o
+ .note.GNU-stack
+                0x00000000        0x0 arch/arm/lib/libarm.o
+ .ARM.attributes
+                0x00000000       0x2f arch/arm/lib/libarm.o
+ .debug_aranges
+                0x00000000       0x98 arch/arm/lib/libarm.o
+ .debug_info    0x00000000      0x7fb arch/arm/lib/libarm.o
+ .debug_abbrev  0x00000000      0x2a1 arch/arm/lib/libarm.o
+ .debug_line    0x00000000      0x310 arch/arm/lib/libarm.o
+ .debug_frame   0x00000000      0x110 arch/arm/lib/libarm.o
+ .debug_str     0x00000000      0x511 arch/arm/lib/libarm.o
+ .debug_loc     0x00000000      0x244 arch/arm/lib/libarm.o
+ .debug_ranges  0x00000000       0x78 arch/arm/lib/libarm.o
+ .text          0x00000000        0x0 board/rda/common/librda.o
+ .text.dram_init
+                0x00000000        0xc board/rda/common/librda.o
+ .text.dram_init_banksize
+                0x00000000       0x12 board/rda/common/librda.o
+ .text.checkboard
+                0x00000000       0x10 board/rda/common/librda.o
+ .text.get_board_rev
+                0x00000000        0x4 board/rda/common/librda.o
+ .text.board_init
+                0x00000000       0x18 board/rda/common/librda.o
+ .rodata.str1.1
+                0x00000000       0x10 board/rda/common/librda.o
+ .data          0x00000000        0x0 board/rda/common/librda.o
+ .bss           0x00000000        0x0 board/rda/common/librda.o
+ .comment       0x00000000       0xca board/rda/common/librda.o
+ .note.GNU-stack
+                0x00000000        0x0 board/rda/common/librda.o
+ .ARM.attributes
+                0x00000000       0x2f board/rda/common/librda.o
+ .debug_aranges
+                0x00000000       0x58 board/rda/common/librda.o
+ .debug_info    0x00000000      0x67f board/rda/common/librda.o
+ .debug_abbrev  0x00000000      0x245 board/rda/common/librda.o
+ .debug_line    0x00000000      0x28e board/rda/common/librda.o
+ .debug_frame   0x00000000       0x78 board/rda/common/librda.o
+ .debug_str     0x00000000      0x562 board/rda/common/librda.o
+ .debug_loc     0x00000000       0x20 board/rda/common/librda.o
+ .debug_ranges  0x00000000       0x38 board/rda/common/librda.o
+ .text          0x00000000        0x0 board/rda/rda8810/librda8810.o
+ .rodata.g_reg_cache
+                0x00000000        0x4 board/rda/rda8810/librda8810.o
+ .data          0x00000000        0x0 board/rda/rda8810/librda8810.o
+ .bss           0x00000000        0x0 board/rda/rda8810/librda8810.o
+ .text          0x00000000        0x0 common/libcommon.o
+ .text.console_setfile
+                0x00000000       0x60 common/libcommon.o
+ .text.serial_printf
+                0x00000000       0x30 common/libcommon.o
+ .text.fprintf  0x00000000       0x34 common/libcommon.o
+ .text.vprintf  0x00000000       0x2a common/libcommon.o
+ .text.ctrlc    0x00000000       0x34 common/libcommon.o
+ .text.disable_ctrlc
+                0x00000000       0x10 common/libcommon.o
+ .text.had_ctrlc
+                0x00000000        0xc common/libcommon.o
+ .text.clear_ctrlc
+                0x00000000        0xc common/libcommon.o
+ .text.dbg      0x00000000        0x6 common/libcommon.o
+ .text.search_device
+                0x00000000       0x16 common/libcommon.o
+ .text.console_assign
+                0x00000000       0x2c common/libcommon.o
+ .text.console_init_f
+                0x00000000        0xa common/libcommon.o
+ .text.stdio_print_current_devices
+                0x00000000       0x7c common/libcommon.o
+ .text.console_init_r
+                0x00000000       0x80 common/libcommon.o
+ .text.sbrk     0x00000000       0x4c common/libcommon.o
+ .text.mem_malloc_init
+                0x00000000       0x28 common/libcommon.o
+ .text.malloc_trim
+                0x00000000       0x88 common/libcommon.o
+ .text.free     0x00000000      0x164 common/libcommon.o
+ .text.cfree    0x00000000        0x4 common/libcommon.o
+ .text.malloc   0x00000000      0x3e0 common/libcommon.o
+ .text.calloc   0x00000000       0x88 common/libcommon.o
+ .text.memalign
+                0x00000000       0xcc common/libcommon.o
+ .text.pvalloc  0x00000000       0x14 common/libcommon.o
+ .text.valloc   0x00000000        0xa common/libcommon.o
+ .text.realloc  0x00000000      0x2b0 common/libcommon.o
+ .text.malloc_usable_size
+                0x00000000       0x2a common/libcommon.o
+ .text.mallopt  0x00000000       0x3c common/libcommon.o
+ .text.image_check_magic
+                0x00000000       0x18 common/libcommon.o
+ .text.image_multi_count
+                0x00000000       0x12 common/libcommon.o
+ .text.image_multi_getimg
+                0x00000000       0x5c common/libcommon.o
+ .text.getenv_yesno
+                0x00000000       0x16 common/libcommon.o
+ .text.getenv_bootm_low
+                0x00000000       0x20 common/libcommon.o
+ .text.getenv_bootm_size
+                0x00000000       0x3c common/libcommon.o
+ .text.getenv_bootm_mapsize
+                0x00000000       0x20 common/libcommon.o
+ .text.memmove_wd
+                0x00000000        0xa common/libcommon.o
+ .text.genimg_print_size
+                0x00000000       0x24 common/libcommon.o
+ .text.get_table_entry_name
+                0x00000000       0x18 common/libcommon.o
+ .text.genimg_get_os_name
+                0x00000000       0x14 common/libcommon.o
+ .text.genimg_get_arch_name
+                0x00000000       0x14 common/libcommon.o
+ .text.genimg_get_type_name
+                0x00000000       0x14 common/libcommon.o
+ .text.genimg_get_comp_name
+                0x00000000       0x14 common/libcommon.o
+ .text.image_print_contents
+                0x00000000       0xf8 common/libcommon.o
+ .text.get_table_entry_id
+                0x00000000       0x26 common/libcommon.o
+ .text.genimg_get_os_id
+                0x00000000       0x14 common/libcommon.o
+ .text.genimg_get_arch_id
+                0x00000000       0x14 common/libcommon.o
+ .text.genimg_get_type_id
+                0x00000000       0x14 common/libcommon.o
+ .text.genimg_get_comp_id
+                0x00000000       0x14 common/libcommon.o
+ .text.genimg_get_format
+                0x00000000        0xe common/libcommon.o
+ .text.genimg_get_image
+                0x00000000        0x2 common/libcommon.o
+ .text.genimg_has_config
+                0x00000000        0x4 common/libcommon.o
+ .text.boot_get_ramdisk
+                0x00000000      0x17c common/libcommon.o
+ .text.boot_ramdisk_high
+                0x00000000       0xc4 common/libcommon.o
+ .text.get_ram_size
+                0x00000000       0xa2 common/libcommon.o
+ .text.stdio_get_list
+                0x00000000        0x8 common/libcommon.o
+ .text.stdio_get_by_name
+                0x00000000       0x34 common/libcommon.o
+ .text.stdio_clone
+                0x00000000       0x30 common/libcommon.o
+ .text.stdio_register
+                0x00000000       0x28 common/libcommon.o
+ .text.stdio_init
+                0x00000000       0x5c common/libcommon.o
+ .text.CYGACC_COMM_IF_PUTC
+                0x00000000        0x6 common/libcommon.o
+ .rodata.uimage_comp
+                0x00000000       0x48 common/libcommon.o
+ .rodata.uimage_os
+                0x00000000       0x30 common/libcommon.o
+ .rodata.uimage_arch
+                0x00000000       0x48 common/libcommon.o
+ .rodata.uimage_type
+                0x00000000       0xc0 common/libcommon.o
+ .data          0x00000000        0x0 common/libcommon.o
+ .data.av_      0x00000000      0x408 common/libcommon.o
+ .data.mmap_threshold
+                0x00000000        0x4 common/libcommon.o
+ .data.sbrk_base
+                0x00000000        0x4 common/libcommon.o
+ .data.trim_threshold
+                0x00000000        0x4 common/libcommon.o
+ .data.stdio_names
+                0x00000000        0xc common/libcommon.o
+ .bss           0x00000000        0x0 common/libcommon.o
+ .bss.ctrlc_was_pressed
+                0x00000000        0x4 common/libcommon.o
+ .bss.ctrlc_disabled
+                0x00000000        0x4 common/libcommon.o
+ .bss.max_total_mem
+                0x00000000        0x4 common/libcommon.o
+ .bss.mem_malloc_brk
+                0x00000000        0x4 common/libcommon.o
+ .bss.max_sbrked_mem
+                0x00000000        0x4 common/libcommon.o
+ .bss.current_mallinfo
+                0x00000000       0x28 common/libcommon.o
+ .bss.mem_malloc_end
+                0x00000000        0x4 common/libcommon.o
+ .bss.top_pad   0x00000000        0x4 common/libcommon.o
+ .bss.mem_malloc_start
+                0x00000000        0x4 common/libcommon.o
+ .bss.n_mmaps_max
+                0x00000000        0x4 common/libcommon.o
+ .bss.devs      0x00000000       0x3c common/libcommon.o
+ .text          0x00000000        0x0 drivers/mmc/libmmc.o
+ .text.board_mmc_getwp
+                0x00000000        0x6 drivers/mmc/libmmc.o
+ .text.mmc_getwp
+                0x00000000       0x1c drivers/mmc/libmmc.o
+ .text.mmc_send_cmd
+                0x00000000        0xa drivers/mmc/libmmc.o
+ .text.mmc_switch_part
+                0x00000000       0x34 drivers/mmc/libmmc.o
+ .text.mmc_get_dev
+                0x00000000       0x1c drivers/mmc/libmmc.o
+ .text.print_mmc_devices
+                0x00000000       0x48 drivers/mmc/libmmc.o
+ .text.get_mmc_num
+                0x00000000        0xc drivers/mmc/libmmc.o
+ .text.mmc_set_preinit
+                0x00000000        0x6 drivers/mmc/libmmc.o
+ .text.hal_getticks
+                0x00000000        0x4 drivers/mmc/libmmc.o
+ .text.hal_get_op_status
+                0x00000000        0xa drivers/mmc/libmmc.o
+ .text.mmc_read
+                0x00000000       0x48 drivers/mmc/libmmc.o
+ .text.mmc_write
+                0x00000000       0x48 drivers/mmc/libmmc.o
+ .data          0x00000000        0x0 drivers/mmc/libmmc.o
+ .bss           0x00000000        0x0 drivers/mmc/libmmc.o
+ .text          0x00000000        0x0 drivers/mtd/nand/libnand.o
+ .text.nand_spl_mtd_info
+                0x00000000       0x10 drivers/mtd/nand/libnand.o
+ .text.nand_deselect
+                0x00000000       0x1c drivers/mtd/nand/libnand.o
+ .text.nand_calculate_ecc
+                0x00000000       0xbc drivers/mtd/nand/libnand.o
+ .text.nand_correct_data
+                0x00000000       0xc0 drivers/mtd/nand/libnand.o
+ .text.is_power_of_2
+                0x00000000        0xe drivers/mtd/nand/libnand.o
+ .text.nand_release_device
+                0x00000000       0x10 drivers/mtd/nand/libnand.o
+ .text.nand_read_byte
+                0x00000000        0xa drivers/mtd/nand/libnand.o
+ .text.nand_read_byte16
+                0x00000000        0xe drivers/mtd/nand/libnand.o
+ .text.nand_read_word
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+ .rodata.clk_div_map
+                0x00107d75       0x20 drivers/mtd/nand/libnand.o
+ .rodata.emmc_mclk_adj_inv
+                0x00107d95       0x20 drivers/mmc/libmmc.o
+ .rodata.keyindex_map
+                0x00107db5       0x10 arch/arm/cpu/armv7/rda/librda.o
+ .rodata.str1.1
+                0x00107dc5       0x65 arch/arm/cpu/armv7/libarmv7.o
+ .rodata.str1.1
+                0x00107e2a      0x32a arch/arm/cpu/armv7/rda/librda.o
+                                0x33c (size before relaxing)
+ .rodata.str1.1
+                0x00108154      0x27b board/rda/rda8810/librda8810.o
+                                0x284 (size before relaxing)
+ .rodata.str1.1
+                0x001083cf      0x637 common/libcommon.o
+                                0x65d (size before relaxing)
+ .rodata.str1.1
+                0x00108a06      0x4ce drivers/mmc/libmmc.o
+                                0x4d4 (size before relaxing)
+ .rodata.str1.1
+                0x00108ed4      0x907 drivers/mtd/nand/libnand.o
+                                0x949 (size before relaxing)
+ .rodata.str1.1
+                0x001097db       0x30 lib/libgeneric.o
+ .rodata.str1.1
+                0x0010980b       0x1b /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/spl/arch/arm/lib/eabi_compat.o
+
+.ARM.exidx      0x00109828       0x28
+ .ARM.exidx     0x00109828       0x10 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(bpabi.o)
+ .ARM.exidx     0x00109838        0x8 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_divdi3.o)
+ .ARM.exidx     0x00109840       0x10 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_udivdi3.o)
+                                  0x8 (size before relaxing)
+
+.rel.dyn        0x00109850        0x0
+ .rel.iplt      0x00000000        0x0 arch/arm/cpu/armv7/start.o
+                0x00109850                . = ALIGN (0x4)
+
+.data           0x00109850       0x98
+ *(.data)
+ .data          0x00109850       0x98 arch/arm/cpu/armv7/rda/librda.o
+
+.igot.plt       0x001098e8        0x0
+ .igot.plt      0x00000000        0x0 arch/arm/cpu/armv7/start.o
+
+.data.hwp_ispi  0x001098e8        0x4
+ .data.hwp_ispi
+                0x001098e8        0x4 arch/arm/cpu/armv7/rda/librda.o
+
+.data.clock_default_config
+                0x001098ec       0xbc
+ .data.clock_default_config
+                0x001098ec       0xbc board/rda/rda8810/librda8810.o
+
+.data.pll_freq_table
+                0x001099a8      0x168
+ .data.pll_freq_table
+                0x001099a8      0x168 board/rda/rda8810/librda8810.o
+
+.data.g_debug_ddr3
+                0x00109b10        0x1
+ .data.g_debug_ddr3
+                0x00109b10        0x1 board/rda/rda8810/librda8810.o
+                0x00109b10                g_debug_ddr3
+
+.data.cur_dev_num
+                0x00109b14        0x4
+ .data.cur_dev_num
+                0x00109b14        0x4 drivers/mmc/libmmc.o
+
+.data.rda_nand_oob_64
+                0x00109b18      0x248
+ .data.rda_nand_oob_64
+                0x00109b18      0x248 drivers/mtd/nand/libnand.o
+
+.data.rda_nand_oob_512
+                0x00109d60      0x248
+ .data.rda_nand_oob_512
+                0x00109d60      0x248 drivers/mtd/nand/libnand.o
+
+.data.rda_nand_oob_256
+                0x00109fa8      0x248
+ .data.rda_nand_oob_256
+                0x00109fa8      0x248 drivers/mtd/nand/libnand.o
+
+.data.rda_nand_oob_128
+                0x0010a1f0      0x248
+ .data.rda_nand_oob_128
+                0x0010a1f0      0x248 drivers/mtd/nand/libnand.o
+
+.data.spi_nand_oob_64
+                0x0010a438      0x248
+ .data.spi_nand_oob_64
+                0x0010a438      0x248 drivers/mtd/nand/libnand.o
+
+.data.spi_bbt_main_descr
+                0x0010a680       0x24
+ .data.spi_bbt_main_descr
+                0x0010a680       0x24 drivers/mtd/nand/libnand.o
+
+.data.spi_nand_oob_128
+                0x0010a6a4      0x248
+ .data.spi_nand_oob_128
+                0x0010a6a4      0x248 drivers/mtd/nand/libnand.o
+
+.data.spi_bbt_mirror_descr
+                0x0010a8ec       0x24
+ .data.spi_bbt_mirror_descr
+                0x0010a8ec       0x24 drivers/mtd/nand/libnand.o
+
+.data.bbt_pattern
+                0x0010a910        0x4
+ .data.bbt_pattern
+                0x0010a910        0x4 drivers/mtd/nand/libnand.o
+
+.data.mirror_pattern
+                0x0010a914        0x4
+ .data.mirror_pattern
+                0x0010a914        0x4 drivers/mtd/nand/libnand.o
+                0x0010a918                . = ALIGN (0x4)
+                0x0010a918                . = .
+                0x0010a918                . = ALIGN (0x4)
+                0x0010a918                __image_copy_end = .
+                0x0010a918                _end = .
+                0x0010bff0                . = (((__start + 0xc000) - 0x10) - 0x100)
+                0x0010bff0                . = ALIGN (0x4)
+
+.ddrcal         0x0010bff0       0x10
+                0x0010bff0                __ddrcal_start = .
+                0x0010c000                . = (__ddrcal_start + 0x10)
+ *fill*         0x0010bff0       0x10 00
+                0x0010c000                __ddrcal_end = .
+                0x0010c000                . = .
+                0x0010c000                . = ALIGN (0x4)
+
+.bss            0x0010c000      0xad8
+                0x0010c000                . = ALIGN (0x4)
+                0x0010c000                __bss_start = .
+ *(.bss*)
+ .bss.g_halModuleIfcChannelOwner
+                0x0010c000       0x1c arch/arm/cpu/armv7/rda/librda.o
+                0x0010c000                g_halModuleIfcChannelOwner
+ .bss.usb_in_use
+                0x0010c01c        0x4 board/rda/rda8810/librda8810.o
+ .bss.spl_text_start_addr
+                0x0010c020        0x4 board/rda/rda8810/librda8810.o
+ .bss.g_clock_config
+                0x0010c024        0x4 board/rda/rda8810/librda8810.o
+ .bss.rda2_result
+                0x0010c028        0x8 board/rda/rda8810/librda8810.o
+ .bss.ddr_cal_val_start_addr
+                0x0010c030        0x4 board/rda/rda8810/librda8810.o
+ .bss.pll_patch_multi2
+                0x0010c034        0x4 board/rda/rda8810/librda8810.o
+ .bss.g_reg_cnt
+                0x0010c038        0x2 board/rda/rda8810/librda8810.o
+                0x0010c038                g_reg_cnt
+ *fill*         0x0010c03a        0x2 00
+ .bss.stdio_devices
+                0x0010c03c        0xc common/libcommon.o
+                0x0010c03c                stdio_devices
+ .bss.xyz       0x0010c048      0x43c common/libcommon.o
+ .bss.boot_mmc  0x0010c484        0x4 drivers/mmc/libmmc.o
+ .bss.mmc_devices
+                0x0010c488        0x8 drivers/mmc/libmmc.o
+ .bss.mmc_host_dev
+                0x0010c490       0x18 drivers/mmc/libmmc.o
+                0x0010c490                mmc_host_dev
+ .bss.mmc_device_glob
+                0x0010c4a8      0x2e0 drivers/mmc/libmmc.o
+                0x0010c4a8                mmc_device_glob
+ .bss.rda_ddr_mode
+                0x0010c788        0x4 drivers/mmc/libmmc.o
+ .bss.oob.3892  0x0010c78c       0x20 drivers/mtd/nand/libnand.o
+ *fill*         0x0010c7ac        0x4 00
+ .bss.mtd       0x0010c7b0       0xa8 drivers/mtd/nand/libnand.o
+ .bss.nand_chip
+                0x0010c858      0x130 drivers/mtd/nand/libnand.o
+ .bss.rda_nand_info.4530
+                0x0010c988       0xa4 drivers/mtd/nand/libnand.o
+ .bss.spi_nand_flash_quad_enable
+                0x0010ca2c        0x1 drivers/mtd/nand/libnand.o
+ *fill*         0x0010ca2d        0x3 00
+ .bss.rda_nand_info.4588
+                0x0010ca30       0xa4 drivers/mtd/nand/libnand.o
+ .bss.flash_intf_spi
+                0x0010cad4        0x4 drivers/mtd/nand/libnand.o
+                0x0010cad8                . = ALIGN (0x4)
+                0x0010cad8                __bss_end__ = .
+                0x00000001                ASSERT ((ABSOLUTE (__bss_end__) < 0x10fe00), too big data in spl, don't exceed intrenal ram)
+Address of section .text set to 0x100100
+LOAD arch/arm/cpu/armv7/start.o
+START GROUP
+LOAD arch/arm/cpu/armv7/libarmv7.o
+LOAD arch/arm/cpu/armv7/rda/librda.o
+LOAD arch/arm/lib/libarm.o
+LOAD board/rda/common/librda.o
+LOAD board/rda/rda8810/librda8810.o
+LOAD common/libcommon.o
+LOAD drivers/mmc/libmmc.o
+LOAD drivers/mtd/nand/libnand.o
+LOAD drivers/serial/libserial.o
+LOAD lib/libgeneric.o
+END GROUP
+LOAD /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/spl/arch/arm/lib/eabi_compat.o
+LOAD /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a
+OUTPUT(u-boot-spl elf32-littlearm)
+
+.ARM.attributes
+                0x00000000       0x31
+ .ARM.attributes
+                0x00000000       0x21 arch/arm/cpu/armv7/start.o
+ .ARM.attributes
+                0x00000021       0x2f arch/arm/cpu/armv7/libarmv7.o
+ .ARM.attributes
+                0x00000050       0x2f arch/arm/cpu/armv7/rda/librda.o
+ .ARM.attributes
+                0x0000007f       0x2f board/rda/rda8810/librda8810.o
+ .ARM.attributes
+                0x000000ae       0x2f common/libcommon.o
+ .ARM.attributes
+                0x000000dd       0x2f drivers/mmc/libmmc.o
+ .ARM.attributes
+                0x0000010c       0x2f drivers/mtd/nand/libnand.o
+ .ARM.attributes
+                0x0000013b       0x2f lib/libgeneric.o
+ .ARM.attributes
+                0x0000016a       0x2f /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/spl/arch/arm/lib/eabi_compat.o
+ .ARM.attributes
+                0x00000199       0x23 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_udivsi3.o)
+ .ARM.attributes
+                0x000001bc       0x23 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_divsi3.o)
+ .ARM.attributes
+                0x000001df       0x23 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_lshrdi3.o)
+ .ARM.attributes
+                0x00000202       0x23 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_ashldi3.o)
+ .ARM.attributes
+                0x00000225       0x23 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_aeabi_uldivmod.o)
+ .ARM.attributes
+                0x00000248       0x23 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_dvmd_lnx.o)
+ .ARM.attributes
+                0x0000026b       0x35 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(bpabi.o)
+ .ARM.attributes
+                0x000002a0       0x35 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_divdi3.o)
+ .ARM.attributes
+                0x000002d5       0x35 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_udivdi3.o)
+
+.comment        0x00000000       0x64
+ .comment       0x00000000       0x64 arch/arm/cpu/armv7/libarmv7.o
+                                0x12f (size before relaxing)
+ .comment       0x00000000      0x3f2 arch/arm/cpu/armv7/rda/librda.o
+ .comment       0x00000000      0x12f board/rda/rda8810/librda8810.o
+ .comment       0x00000000      0x25e common/libcommon.o
+ .comment       0x00000000      0x12f drivers/mmc/libmmc.o
+ .comment       0x00000000      0x2c3 drivers/mtd/nand/libnand.o
+ .comment       0x00000000      0x2c3 lib/libgeneric.o
+ .comment       0x00000000       0x65 /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/spl/arch/arm/lib/eabi_compat.o
+
+.note.GNU-stack
+                0x00000000        0x0
+ .note.GNU-stack
+                0x00000000        0x0 arch/arm/cpu/armv7/libarmv7.o
+ .note.GNU-stack
+                0x00000000        0x0 arch/arm/cpu/armv7/rda/librda.o
+ .note.GNU-stack
+                0x00000000        0x0 board/rda/rda8810/librda8810.o
+ .note.GNU-stack
+                0x00000000        0x0 common/libcommon.o
+ .note.GNU-stack
+                0x00000000        0x0 drivers/mmc/libmmc.o
+ .note.GNU-stack
+                0x00000000        0x0 drivers/mtd/nand/libnand.o
+ .note.GNU-stack
+                0x00000000        0x0 lib/libgeneric.o
+ .note.GNU-stack
+                0x00000000        0x0 /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/spl/arch/arm/lib/eabi_compat.o
+ .note.GNU-stack
+                0x00000000        0x0 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_udivsi3.o)
+ .note.GNU-stack
+                0x00000000        0x0 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_divsi3.o)
+ .note.GNU-stack
+                0x00000000        0x0 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_lshrdi3.o)
+ .note.GNU-stack
+                0x00000000        0x0 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_ashldi3.o)
+ .note.GNU-stack
+                0x00000000        0x0 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_aeabi_uldivmod.o)
+ .note.GNU-stack
+                0x00000000        0x0 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_dvmd_lnx.o)
+ .note.GNU-stack
+                0x00000000        0x0 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(bpabi.o)
+ .note.GNU-stack
+                0x00000000        0x0 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_divdi3.o)
+ .note.GNU-stack
+                0x00000000        0x0 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_udivdi3.o)
+
+.debug_line     0x00000000     0x82d0
+ .debug_line    0x00000000       0x9a arch/arm/cpu/armv7/start.o
+ .debug_line    0x0000009a      0x429 arch/arm/cpu/armv7/libarmv7.o
+ .debug_line    0x000004c3     0x15f1 arch/arm/cpu/armv7/rda/librda.o
+ .debug_line    0x00001ab4      0x884 board/rda/rda8810/librda8810.o
+ .debug_line    0x00002338     0x163c common/libcommon.o
+ .debug_line    0x00003974     0x1145 drivers/mmc/libmmc.o
+ .debug_line    0x00004ab9     0x28c3 drivers/mtd/nand/libnand.o
+ .debug_line    0x0000737c      0xeb2 lib/libgeneric.o
+ .debug_line    0x0000822e       0xa2 /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/spl/arch/arm/lib/eabi_compat.o
+
+.debug_info     0x00000000    0x1edee
+ .debug_info    0x00000000       0x73 arch/arm/cpu/armv7/start.o
+ .debug_info    0x00000073      0xb3f arch/arm/cpu/armv7/libarmv7.o
+ .debug_info    0x00000bb2     0x4ed8 arch/arm/cpu/armv7/rda/librda.o
+ .debug_info    0x00005a8a     0x2598 board/rda/rda8810/librda8810.o
+ .debug_info    0x00008022     0x4392 common/libcommon.o
+ .debug_info    0x0000c3b4     0x506c drivers/mmc/libmmc.o
+ .debug_info    0x00011420     0xbc5a drivers/mtd/nand/libnand.o
+ .debug_info    0x0001d07a     0x1c74 lib/libgeneric.o
+ .debug_info    0x0001ecee      0x100 /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/spl/arch/arm/lib/eabi_compat.o
+
+.debug_abbrev   0x00000000     0x5862
+ .debug_abbrev  0x00000000       0x14 arch/arm/cpu/armv7/start.o
+ .debug_abbrev  0x00000014      0x3ff arch/arm/cpu/armv7/libarmv7.o
+ .debug_abbrev  0x00000413     0x13cc arch/arm/cpu/armv7/rda/librda.o
+ .debug_abbrev  0x000017df      0x61e board/rda/rda8810/librda8810.o
+ .debug_abbrev  0x00001dfd     0x105a common/libcommon.o
+ .debug_abbrev  0x00002e57      0xcb3 drivers/mmc/libmmc.o
+ .debug_abbrev  0x00003b0a     0x1437 drivers/mtd/nand/libnand.o
+ .debug_abbrev  0x00004f41      0x88f lib/libgeneric.o
+ .debug_abbrev  0x000057d0       0x92 /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/spl/arch/arm/lib/eabi_compat.o
+
+.debug_aranges  0x00000000     0x10f0
+ .debug_aranges
+                0x00000000       0x20 arch/arm/cpu/armv7/start.o
+ .debug_aranges
+                0x00000020       0xe8 arch/arm/cpu/armv7/libarmv7.o
+ .debug_aranges
+                0x00000108      0x348 arch/arm/cpu/armv7/rda/librda.o
+ .debug_aranges
+                0x00000450       0xd8 board/rda/rda8810/librda8810.o
+ .debug_aranges
+                0x00000528      0x318 common/libcommon.o
+ .debug_aranges
+                0x00000840      0x1d8 drivers/mmc/libmmc.o
+ .debug_aranges
+                0x00000a18      0x4a0 drivers/mtd/nand/libnand.o
+ .debug_aranges
+                0x00000eb8      0x208 lib/libgeneric.o
+ .debug_aranges
+                0x000010c0       0x30 /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/spl/arch/arm/lib/eabi_compat.o
+
+.debug_frame    0x00000000     0x2d60
+ .debug_frame   0x00000000      0x1e8 arch/arm/cpu/armv7/libarmv7.o
+ .debug_frame   0x000001e8      0x694 arch/arm/cpu/armv7/rda/librda.o
+ .debug_frame   0x0000087c      0x230 board/rda/rda8810/librda8810.o
+ .debug_frame   0x00000aac      0x808 common/libcommon.o
+ .debug_frame   0x000012b4      0x52c drivers/mmc/libmmc.o
+ .debug_frame   0x000017e0      0xed0 drivers/mtd/nand/libnand.o
+ .debug_frame   0x000026b0      0x564 lib/libgeneric.o
+ .debug_frame   0x00002c14       0x48 /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/spl/arch/arm/lib/eabi_compat.o
+ .debug_frame   0x00002c5c       0x20 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_udivsi3.o)
+ .debug_frame   0x00002c7c       0x20 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_divsi3.o)
+ .debug_frame   0x00002c9c       0x54 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(bpabi.o)
+ .debug_frame   0x00002cf0       0x38 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_divdi3.o)
+ .debug_frame   0x00002d28       0x38 /xspace/OpenSource/GitHubLinux/OrangePi_i96/toolchain/bin/../lib/gcc/arm-linux-gnueabi/4.6.3/libgcc.a(_udivdi3.o)
+
+.debug_str      0x00000000     0x68d1
+ .debug_str     0x00000000      0x436 arch/arm/cpu/armv7/libarmv7.o
+                                0x75e (size before relaxing)
+ .debug_str     0x00000436     0x1866 arch/arm/cpu/armv7/rda/librda.o
+                               0x33de (size before relaxing)
+ .debug_str     0x00001c9c      0xb47 board/rda/rda8810/librda8810.o
+                               0x1a7e (size before relaxing)
+ .debug_str     0x000027e3     0x1858 common/libcommon.o
+                               0x273f (size before relaxing)
+ .debug_str     0x0000403b      0xb12 drivers/mmc/libmmc.o
+                               0x1ea6 (size before relaxing)
+ .debug_str     0x00004b4d     0x1a36 drivers/mtd/nand/libnand.o
+                               0x4c06 (size before relaxing)
+ .debug_str     0x00006583      0x2c6 lib/libgeneric.o
+                                0xb16 (size before relaxing)
+ .debug_str     0x00006849       0x88 /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/spl/arch/arm/lib/eabi_compat.o
+                                0x18a (size before relaxing)
+
+.debug_loc      0x00000000    0x12a4c
+ .debug_loc     0x00000000      0x6b0 arch/arm/cpu/armv7/libarmv7.o
+ .debug_loc     0x000006b0     0x134f arch/arm/cpu/armv7/rda/librda.o
+ .debug_loc     0x000019ff     0x1356 board/rda/rda8810/librda8810.o
+ .debug_loc     0x00002d55     0x365d common/libcommon.o
+ .debug_loc     0x000063b2     0x2aca drivers/mmc/libmmc.o
+ .debug_loc     0x00008e7c     0x7634 drivers/mtd/nand/libnand.o
+ .debug_loc     0x000104b0     0x255e lib/libgeneric.o
+ .debug_loc     0x00012a0e       0x3e /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/spl/arch/arm/lib/eabi_compat.o
+
+.debug_ranges   0x00000000     0x21d0
+ .debug_ranges  0x00000000      0x160 arch/arm/cpu/armv7/libarmv7.o
+ .debug_ranges  0x00000160      0x380 arch/arm/cpu/armv7/rda/librda.o
+ .debug_ranges  0x000004e0      0x278 board/rda/rda8810/librda8810.o
+ .debug_ranges  0x00000758      0x488 common/libcommon.o
+ .debug_ranges  0x00000be0      0xa88 drivers/mmc/libmmc.o
+ .debug_ranges  0x00001668      0x950 drivers/mtd/nand/libnand.o
+ .debug_ranges  0x00001fb8      0x1f8 lib/libgeneric.o
+ .debug_ranges  0x000021b0       0x20 /xspace/OpenSource/GitHubLinux/OrangePi_i96/uboot/spl/arch/arm/lib/eabi_compat.o
diff --git a/target-device.def b/target-device.def
new file mode 100644
index 0000000000..94ce14adc7
--- /dev/null
+++ b/target-device.def
@@ -0,0 +1,745 @@
+
+#######################################
+## PART A
+##-------------------------------------
+## 芯片描述信息
+#######################################
+
+
+#=====================================
+##  1 ##
+######## 芯片描述信息 ########
+
+## ASIC type: gallite/8808/8809/8810
+CT_ASIC         ?= 8810
+
+## Chip package for different sram size:
+## CT1128: 0Mbit sram
+## CT1129/CT8852D/CT8853D/CT8852M/CT8853M/CT8852A/CT8853A: 16Mbit sram
+## CT1130/CT8852B/CT8853B/RDA8810: 32Mbit sram
+## CT1131/CT8852C/CT8853C/CT8851C: 64Mbit sram
+CT_CHIP_PKG 	?= RDA8810
+
+## Chip die type:
+## 8805/8806 (if CT_ASIC is gallite)
+## or set to null (otherwise)
+CT_CHIP_DIE 	?= 
+
+CHARGERCURRENT_ADJUST_DYNAMIC ?= 1
+
+#######################################
+## PART B
+##-------------------------------------
+## 驱动描述信息
+#######################################
+
+
+## 注意1：除非特别说明，module的名字必须和edrv目录下面的目录名保持一致，
+## 否则编译的时候找不到对应的目标。如果edrv下面没有相关的目录，
+## 说明暂时没有这个设备的驱动，需要驱动工程师自己去开发一个新的驱动，
+## 驱动程序可以根据设备的SPEC参考已有的驱动进行修改。
+
+
+#=====================================
+##  2 ##
+######## 触屏驱动 ########
+
+## 芯片集成，需要则设置为rda1203_gallite，否则设置为空
+TSD_MODEL       ?=
+
+
+#=====================================
+##  3 ##
+######## FM驱动 ########
+
+## rda5802e_gallite (如果使用8805/8806芯片集成的FM模块)
+## rda5888e
+## (如果使用rda5888s，也需要配成rda5888e)
+## rda5888h
+## rda5876
+## rda5802na
+FM_MODEL        ?= 
+
+## 如果使用I2S，则设置为1；
+## 如果使用LINE-IN，则设置为0
+FM_USING_I2S    ?= 0
+
+## FM使用的32K时钟管脚: 1/0
+## 1: 32K_CLK pin
+## 0: CLK_OUT pin
+FM_USE_32K_CLK_PIN ?= 0
+
+## FM使用外置拉杆天线（不需要插入耳机收听）
+#MMI_EXPORT_FLAG += FM_RADIO_WITH_EXTERNAL_ANT
+
+
+#=====================================
+##  4 ##
+######## FLASH驱动 ########
+
+## ADMUX MCP
+##
+## Normal MCP
+##
+## SPI Flash (RAM is packaged inside baseband chip)
+##1 <General> flsh_spi32m     32
+##  <General> flsh_spi32x2m   64
+##  <General> flsh_spi64m     64
+##  <General> flsh_spi64x2m   128
+##  <General> flsh_spi128m    128
+##
+## Modem RAM
+##1 <General> modem_ram
+FLSH_MODEL      ?= modem_ram
+
+## Flash model interface: parallel/spi
+FLSH_IF         ?= 
+
+## EBC CLK cfg:__52MHz__/__78MHz__/__104MHz__/__156MHz__
+SYS_MEMD_EBC_CLK ?= __104MHz__
+
+## SPI Flash SPI CLK cfg:__52MHz__/__78MHz__/__104MHz__/__156MHz__
+ifeq "$(strip ${FLSH_IF})" "spi"
+SYS_MEMD_FLSH_SPI_CLK ?= __78MHz__
+endif # (${FLSH_IF},)
+
+## Ram is ADMUX or not
+ifeq "$(strip ${CT_ASIC_CFG})" "chip"
+TARGET_EXPORT_FLAG    += MEMD_RAM_IS_ADMUX
+## Flash is ADMUX or not 
+#TARGET_EXPORT_FLAG    += MEMD_FLASH_IS_ADMUX
+## Ram support burst mode or not
+TARGET_EXPORT_FLAG    += MEMD_RAM_IS_BURST
+## Flash support burst mode or not
+#TARGET_EXPORT_FLAG    += MEMD_FLASH_IS_BURST
+else
+#TARGET_EXPORT_FLAG    += MEMD_RAM_PAGE_MODE
+TARGET_EXPORT_FLAG    += FPGA_PSRAM_MICRON
+endif
+
+#=====================================
+##  5 ##
+######## LCD驱动 ########
+
+##	1 QVGA	240*320
+##	hx8347 lgdp4532 st7781 ssd1297 spfd5408b
+##	hx8367 s6d1121 st7787 ili9320
+##	otm3225 ili9325 ili9328 ili9340
+##	s6d04h0a01(无id寄存器)
+##	2 QCIF	176*220
+##	hx8340b kc20 r61503v otm2201a
+##	ili9225 lgb4525b r61503vr otm2201h
+##	ili9225b ili9225br s6d0164 dc2200
+##	3 QQVGA	128*160
+##	ili9163 s6b33bf st7669v s6d0144
+##	st7735 hx8345a fd54124bv
+## （支持自适应选择，可以同时设置多个驱动）
+
+## MainLCD
+LCD_MODEL       ?=  
+
+## LCD interface: gouda/slcd
+LCD_IF          ?= 
+
+## GOUDA can support serial LCD starting from 8808
+ifeq "$(strip ${LCD_IF})" "gouda"
+USE_SPI_LCD     ?= 0
+endif
+
+## Define LCD resolution:
+## LCDSIZE_128_160/LCDSIZE_176_220/LCDSIZE_240_320
+GLOBAL_EXPORT_FLAG += LCDSIZE_128_160
+
+## 将QQVGA放大到QCIF
+#GLOBAL_EXPORT_FLAG    += LCD_SCALE_128_160_TO_176_220
+
+## SubLCD
+SUBLCD_MODEL	?= 
+
+ifneq "$(strip ${SUBLCD_MODEL})" ""
+## SubLCD interface: gouda/slcd
+SUBLCD_IF       ?= gouda
+
+## GOUDA can support serial LCD starting from 8808
+ifeq "$(strip ${SUBLCD_IF})" "gouda"
+USE_SPI_SUBLCD  ?= 0
+endif
+
+## Define SUB LCD resolution
+## SUBLCDSIZE_128_128/SUBLCDSIZE_96_64/SUBLCDSIZE_64_96
+GLOBAL_EXPORT_FLAG += SUBLCDSIZE_128_128
+endif # SUBLCD_MODEL
+
+## Whether to enable charge pump to avoid screen flicker
+## (If enabled, AUD_SPK_LINE_CLASS_MODE must be set to class_k)
+LCD_BACKLIGHT_CHARGE_PUMP ?= 0
+
+
+#=====================================
+##  6 ##
+######## CAMERA驱动 ########
+
+##1 OmniVision OV7660 VGA
+##  OmniVision OV7670 VGA
+##  OmniVision OV7675 VGA
+##2 GalaxyCore GC0306 VGA
+##  GalaxyCore GC0307 VGA
+##  GalaxyCore GC0309 VGA
+##3 BYD BYD3503 VGA
+##  BYD BYD3603 VGA
+##  BYD BYD3703 VGA
+##4 HYNIX YACBAA0SDDAS VGA
+##  HYNIX HYA10S VGA
+##5 SET SIV100B VGA
+##6 Superpix SP80818 VGA  
+## （支持自适应选择，可以同时设置多个驱动）
+CAMERA_MODEL    ?= 
+
+## Camera model interface: parallel/spi
+## 对于spi接口，8805/8806只支持pas6175与sp0828，
+##     而且必须与串口LCD配合使用；
+##     后续芯片(8808及以后)则无此限制。
+## 对于gc6113串口摄像头，需要使用并口模拟串口时，
+##     接口需配置成parallel，而且不能与串口LCD配合使用;
+##     8805/8806只支持并口模拟串口的方式；
+##     后续芯片(8808及以后)则无此限制。
+CAMERA_IF       ?= 
+
+## 支持双camera
+#TARGET_EXPORT_FLAG += SUPPORT_DUAL_CAMERA
+
+## 是否支持大照片拍摄(要求有足够内存)
+GLOBAL_EXPORT_FLAG += MEM_3216_CAMERA_LARGE_MODE
+
+## 使用8w sensor时，必须打开；
+## 如果ULC（3216）项目中使用30w sensor，建议打开;
+## 注意不能和_CAM_SPECIAL_GC6113_同时定义
+TARGET_EXPORT_FLAG += _CAM_SMALL_MEM_
+
+
+#=====================================
+##  7 ##
+######## 蓝牙驱动 ########
+
+## rda5870
+## rda5872
+## rda5875
+## rda5876 (如果使用rda5875y，也需要配置成rda5876)
+##（支持自适应选择，可以同时设置多个驱动）
+BT_MODEL        ?= 
+
+ifneq "$(strip ${BT_MODEL})" ""
+## 当不支持A2DP的时候需要定义这个宏
+#GLOBAL_EXPORT_FLAG += __BT_NO_A2DP_PROFILE__
+
+## Define BT crystal flag
+BT_SHARE_CRYSTAL ?= 1
+
+## 蓝牙使用的32K时钟管脚: 1/0
+## 1: 32K_CLK pin
+## 0: CLK_OUT pin
+BT_USE_32K_CLK_PIN ?= 0
+endif # (${BT_MODEL},)
+
+#TARGET_EXPORT_FLAG += __BT_PCM_OVER_UART__
+
+
+#=====================================
+##  8 ##
+######## 模拟电视驱动 ########
+
+## rda5888e (如果使用rda5888s，也需要配置成rda5888e)
+## rda5888h
+## rda5888he
+ATV_MODEL       ?= 
+
+## If 5888h or 5888he then USING I2S need set 0
+#TV_USING_I2S    ?= 0
+
+## 模拟电视使用的32K时钟管脚: 1/0
+## 1: 32K_CLK pin
+## 0: CLK_OUT pin
+TV_USE_32K_CLK_PIN ?= 0
+
+
+#=====================================
+##  9 ##
+######## T卡驱动 ########
+
+## Interface: sdmmc/spi
+MCD_IF          ?= 
+
+
+#=====================================
+## 10 ##
+######## 软I2C驱动 ########
+
+## 当配置了这项为i2c_gpio之后，会使用GPIO来软件模拟I2C接口;
+## 不使用软件模拟时设置为空
+I2C_MODEL       ?=
+
+
+#=====================================
+## 11 ##
+######## GSENSOR驱动 ########
+
+## mma7660fc
+## mma7660fc_gpio
+GSENSOR_MODEL   ?= 
+
+
+#=====================================
+## 12 ##
+######## SIM卡驱动 ########
+
+## 8805: rda1203_gallite(2卡驱动), threesimd（3卡驱动），fourdimd（4卡驱动）
+## 8806/8808: rda1203_gallite_CT1129
+DUALSIM_MODEL   ?= rda1203_gallite_CT1129
+
+## 支持的多卡的数量***
+NUMBER_OF_SIM   ?= 2
+
+## 支持多卡的卡序排列***
+USER_SIM_ORDER  ?= 1 2
+
+## 如果用了SIM switch开关，就打开此宏
+ifeq "$(strip ${CT_CHIP_DIE})" "8805"
+#TARGET_EXPORT_FLAG    += SIM_SWITCH_USED
+endif
+
+## Whether to support USIM
+USIM_SUPPORT ?= 1
+
+
+#=====================================
+## 13 ##
+######## 音频驱动 #########
+
+## MIC电路是否采用节省电容器的方案（是填1；否则填0）
+MIC_CAPLESS_MODE ?= 1
+
+## The usage of L&R speaker lines: both, left, right
+AUD_SPK_LINE_USAGE ?= both
+
+## Whether to enable speaker line L-R-double mode
+AUD_SPK_LINE_L_R_DOUBLE ?= 1
+
+## Whether to enable headphone charge pump mode
+## (If enabled, AUD_SPK_LINE_CLASS_MODE must be set to class_k)
+HEADPHONE_CHARGE_PUMP ?= 0
+
+## Select speaker class mode: class_ab, class_d, class_k
+## (If LCD_BACKLIGHT_CHARGE_PUMP or HEADPHONE_CHARGE_PUMP is
+## enabled, class_k must be selected)
+AUD_SPK_LINE_CLASS_MODE ?= class_d
+
+## Receiver uses one speaker line (using left line by default)
+#TARGET_EXPORT_FLAG    += RECV_USE_SPK_LINE
+
+## If using right line, the following macro should be added as well
+#TARGET_EXPORT_FLAG    += RECV_USE_SPK_LINE_R
+
+## Alleviate the "pop" sound on loud speaker for some external audio PAs
+#TARGET_EXPORT_FLAG    += AUD_SPK_ON_WITH_LCD
+
+# ABB headphone detection
+#TARGET_EXPORT_FLAG += ABB_HP_DETECT
+
+
+#=====================================
+## 14 ##
+######## 射频驱动 #########
+
+## pasw_rda6231
+## pasw_rda6625
+PA_MODEL        ?= pasw_rda6231
+
+## RF优化选项
+## 若XCV直接控制PA与SW的可以打开此宏，若TCO控制则必须关掉此宏（请先咨询FAE）
+TARGET_EXPORT_FLAG += INTERNAL_XCV_CONTROL_PASW
+TARGET_EXPORT_FLAG += __RF_RDAPASW_TWOBAND_AS_FOURBAND__
+
+## PA RAMP电容是否使用220pF: 1/0
+PA_VRAMP_220PF ?= 1
+
+
+#=====================================
+## 15 ##
+######## WIFI驱动 #########
+
+## rdawifi
+WIFI_MODEL      ?= 
+
+## WIFI使用的32K时钟管脚: 1/0
+## 1: 32K_CLK pin
+## 0: CLK_OUT pin
+WIFI_USE_32K_CLK_PIN ?= 0
+
+
+#=====================================
+## 16 ##
+######## 32K时钟配置 #########
+
+## 基带芯片是否使用外部晶体提供的32K时钟（XTAL32K_IN管脚）：1/0
+## （注意：8805/8806芯片不需要配置此选项）
+USE_EXT_XTAL_32K ?= 0
+
+
+#=====================================
+## 17 ##
+######## GPRS支持 ########
+
+## 1为支持GPRS，0为不支持
+GPRS_SUPPORT ?= 1
+EGPRS_SUPPORT ?= 1
+
+## 1为支持PPP，0为不支持
+PPP_SUPPORT ?= 1
+
+## 当运行camera/video player/video recorder等应用时不自动下载彩信内容，
+## 只下载彩信通知，用户可以之后手动下载彩信内容
+## 对于读写速度较慢的flash，需要定义
+#GLOBAL_EXPORT_FLAG += MANUAL_DOWNLOAD_MMS
+
+
+#=====================================
+## 18 ##
+######## 射频校准屏幕显示支持 ########
+
+## Screen display in RF calibration: 1/0
+## 如果不在这里设置，CES_DISPLAY会在platform/calib被默认设置为1;
+## 对于ULC项目可以将其设置为0，以节省flash空间
+CES_DISPLAY ?= 0
+
+
+#######################################
+## PART C
+##-------------------------------------
+## 应用描述信息
+#######################################
+
+
+#=====================================
+## 19 ##
+######## 资源包 ########
+
+## 选择application/target_res目录下的资源包；
+## 设置为空则选择系统默认的资源包
+CT_ERES ?= g021_441_3216
+
+
+#=====================================
+## 20 ##
+######## ULC选项 ########
+
+## 是否启用ULC: YES/NO (注意都是大写字母!)
+TARGET_MEM_ULC_3216 ?= YES
+
+
+#=====================================
+## 21 ##
+######## 空间压缩 ########
+
+## 是否启用压缩代码: yes/no
+CT_COMPRESS_CODE_SECTION ?= no
+
+## 是否启用字符串资源压缩
+MMI_EXPORT_FLAG += COMPRESS_OPTIMIZE_FLASH_SIZE
+MMI_EXPORT_FLAG += COMPRESS_USE_LZMA
+
+ifeq "$(strip ${CT_COMPRESS_CODE_SECTION})" "yes"
+## Compression state: 3232/3264/6464 or set to null
+COMPRESS_STATE ?= 
+## Compression strategy (please consult FAE):
+## 1/2 or set to null
+COMPRESS_STRATEGY ?= 
+
+#TARGET_EXPORT_FLAG += __CODE_DECOMPRESS_WITH_VOC__
+endif
+
+#=====================================
+## 22 ##
+######## USB支持类型 ########
+
+## umss_storage_flashmc表示支持FLASH和T卡U盘
+## umss_storage_mc 表示仅支持T卡U盘
+UCTLS_SERVICE   ?= umss_storage_flashmc
+
+
+#=====================================
+## 23 ##
+######## 多国语言设置 ########
+
+SUPPORT_MULTI_LANG_FRENCH			:= NO	#French
+SUPPORT_MULTI_LANG_ITALIAN			:= NO	#Italian
+SUPPORT_MULTI_LANG_VIETNAMESE		:= NO	#Vietnamese
+SUPPORT_MULTI_LANG_RUSSIAN			:= NO	#Russian
+SUPPORT_MULTI_LANG_ARABIC			:= NO	#Arabic
+SUPPORT_MULTI_LANG_THAI				:= NO	#Thai
+SUPPORT_MULTI_LANG_SM_CHINESE		:= YES	#SM Chinese,NOTE: can't work together with TR chinese
+SUPPORT_MULTI_LANG_TR_CHINESE		:= NO	#TR Chinese,NOTE: can't work together with SM chinese
+SUPPORT_MULTI_LANG_GERMAN			:= NO	#German
+SUPPORT_MULTI_LANG_SPANISH			:= NO	#Spanish
+SUPPORT_MULTI_LANG_PORTUGUESE		:= NO	#Portuguese
+SUPPORT_MULTI_LANG_PERSIAN			:= NO	#Persian
+SUPPORT_MULTI_LANG_URDU				:= NO	#Urdu
+SUPPORT_MULTI_LANG_TURKISH			:= NO	#Turkish
+SUPPORT_MULTI_LANG_INDONESIAN		:= NO	#Indonesian
+SUPPORT_MULTI_LANG_MALAY			:= NO	#Malay
+SUPPORT_MULTI_LANG_ZULU				:= NO	#Zulu
+SUPPORT_MULTI_LANG_XHOSA			:= NO	#Xshosa
+SUPPORT_MULTI_LANG_SWAHILI			:= NO	#Swahili
+SUPPORT_MULTI_LANG_CZECH			:= NO	#Czech
+SUPPORT_MULTI_LANG_POLISH			:= NO	#Polish
+SUPPORT_MULTI_LANG_HUNGARIAN		:= NO	#Hungarian
+SUPPORT_MULTI_LANG_NORWEGIAN		:= NO	#Norwegian
+SUPPORT_MULTI_LANG_SLOVAK			:= NO	#Slovak
+SUPPORT_MULTI_LANG_DUTCH			:= NO	#Dutch
+SUPPORT_MULTI_LANG_SWEDISH			:= NO	#Swedish
+SUPPORT_MULTI_LANG_CROATIAN			:= NO	#Croatian
+SUPPORT_MULTI_LANG_SLOVENIAN		:= NO	#Slovenian
+SUPPORT_MULTI_LANG_AFRIKAANS		:= NO	#Afrikaans
+SUPPORT_MULTI_LANG_LITHUANIAN		:= NO	#Lithuanian
+SUPPORT_MULTI_LANG_LATVIAN			:= NO	#Latvian
+SUPPORT_MULTI_LANG_ESTONIAN			:= NO	#Estonian
+SUPPORT_MULTI_LANG_MOLDOVAN			:= NO	#Moldovan
+SUPPORT_MULTI_LANG_ALBANIAN			:= NO	#Albanian 
+SUPPORT_MULTI_LANG_CA_FRENCH		:= NO	#Ca_French
+SUPPORT_MULTI_LANG_SA_SPANISH		:= NO	#Latin.Am.Spanish
+SUPPORT_MULTI_LANG_SA_PORTUGUESE	:= NO	#Brazil.Portuguese
+SUPPORT_MULTI_LANG_SESOTHO			:= NO	#Sesotho
+SUPPORT_MULTI_LANG_TAGALOG			:= NO	#Tagalog
+SUPPORT_MULTI_LANG_UK_ENGLISH		:= NO	#UK Eenglish
+SUPPORT_MULTI_LANG_YORUBA			:= NO	#Yoruba
+SUPPORT_MULTI_LANG_AZERBAIJANI		:= NO	#Azerbaijani
+SUPPORT_MULTI_LANG_CATALAN			:= NO	#Catalan
+SUPPORT_MULTI_LANG_ICELANDIC		:= NO	#Icelandic
+SUPPORT_MULTI_LANG_DANISH			:= NO	#Danish
+SUPPORT_MULTI_LANG_FINNISH			:= NO	#Finnish
+SUPPORT_MULTI_LANG_ROMANIAN			:= NO	#Romanian
+SUPPORT_MULTI_LANG_HAUSA			:= NO	#Hausa
+SUPPORT_MULTI_LANG_BULGARIAN		:= NO	#Bulgarian
+SUPPORT_MULTI_LANG_UKRAINIAN		:= NO	#Ukrainian
+SUPPORT_MULTI_LANG_MACEDONIAN		:= NO	#Macedonian
+SUPPORT_MULTI_LANG_SERBIAN			:= NO	#Serbian
+SUPPORT_MULTI_LANG_GREEK			:= NO	#Greek
+SUPPORT_MULTI_LANG_HEBREW			:= NO	#Hebrew
+SUPPORT_MULTI_LANG_UYGHUR			:= NO	#Uyghur
+
+#these languages support need open IndicLanguages macro
+SUPPORT_MULTI_LANG_INDIC_LANGUAGES 	:= NO
+SUPPORT_MULTI_LANG_HINDI          	:= NO	 #Hindi
+SUPPORT_MULTI_LANG_TELUGU         	:= NO    #Telugu
+SUPPORT_MULTI_LANG_PUNJABI        	:= NO    #Punjabi
+SUPPORT_MULTI_LANG_BENGALI        	:= NO    #Bengali
+SUPPORT_MULTI_LANG_MARATHI        	:= NO    #Marathi
+SUPPORT_MULTI_LANG_MYANMAR			:= NO    #Mayanmar
+SUPPORT_MULTI_LANG_TAMIL          	:= NO    #Tamil
+SUPPORT_MULTI_LANG_ASSAMESE			:= NO	 #Assamese
+SUPPORT_MULTI_LANG_ORIYA          	:= NO    #Malay
+SUPPORT_MULTI_LANG_KANNADA        	:= NO    #Malay
+SUPPORT_MULTI_LANG_MALAYALAM      	:= NO    #Malay
+
+#################################################################
+
+#=====================================
+## 24 ##
+######## 文件系统 ########
+
+## 当使用的FLASH为单BANKFLASH的时候，需要打开
+#TARGET_EXPORT_FLAG += USER_DATA_CACHE_SUPPORT
+#TARGET_EXPORT_FLAG += FACT_SETTING_CACHE_SUPPORT
+
+## 将文件系统REG区和sms区合并为CSW区，
+## 节省代码空间，客户无需修改,
+## 若存储的SMS数较多则需要注销此宏
+TARGET_EXPORT_FLAG += _REG_SMS_MERGE
+
+
+#=====================================
+## 25 ##
+######## 功能选项 ########
+
+## Video player功能: 1/0
+## 如果不在这里设置，VIDEO_PLAYER_SUPPORT会在后面被默认设置为1;
+## 对于ULC项目可以将其设置为0，取消video player功能以节省flash空间
+#VIDEO_PLAYER_SUPPORT ?= 0
+
+## sound recorder功能: 1/0
+SOUND_RECORDER_SUPPORT ?= 0
+
+## Video recorder功能: 1/0
+VIDEO_RECORDER_SUPPORT ?= 0
+
+ifeq "$(strip ${VIDEO_RECORDER_SUPPORT})" "1"
+##
+## VDOREC_MODE_QVGA: QVGA(320x240) recording
+## VDOREC_MODE_VGA: VGA(640x480) recording
+## If neither is declared, QQVGA(160x120) recording by default
+## Neither macro is recommended to declare unless on 8808 platform
+##
+#GLOBAL_EXPORT_FLAG += VDOREC_MODE_VGA
+
+##
+## VIDREC_FAST_RECORDING: 15 frames per second, only available for QVGA/QQVGA recording
+## If it is not declared, 10 fps for QVGA/QQVGA by default.
+##
+#GLOBAL_EXPORT_FLAG += VIDREC_FAST_RECORDING
+endif
+
+## 使用camera模拟2d sensor: 1/0
+ifneq "$(strip ${CAMERA_MODEL})" ""
+CAM_MD_SUPPORT ?= 0
+endif
+
+## 魔音功能: 1/0
+MAGIC_AE_SUPPORT ?= 0
+
+## RMVB播放解码支持: 1/0
+## 此功能需求的内存较大，总共约760KB
+MEDIA_RM_SUPPORT ?= 0
+
+## MIDI播放支持: 1/0
+MEDIA_MIDI_SUPPORT ?= 0
+
+## display a picture early when power on 
+#GLOBAL_EXPORT_FLAG += __DISPLAY_POWERON_LOGO__
+
+## 支持T卡热插拔
+#MMI_EXPORT_FLAG       += __TFLASH_MOUNT_DYNAMIC__
+
+## 这个宏开关，用来控制是否支持自动记录按键信息，
+## 通常用于记录出问题之前的按键信息，方便工程人员复现问题
+## 打开这个宏会额外占用大约9KByte的空间，可以根据实际情况
+## 考虑是否打开这个功能
+#MMI_EXPORT_FLAG += AUTO_TEST_KEYPRESS_RECORD_SUPPORT
+
+## 定义短消息和电话本的条目
+## PHONE_SMS_ENTRY_COUNT表征FLASH上多卡项目总计SMS容量，
+## 单卡数目为PHONE_SMS_ENTRY_COUNT/SIM_COUNT
+## SIM_SMS_ENTRY_COUNT表征SIM卡上最大SMS容量，请勿修改
+GLOBAL_EXPORT_FLAG += PHONE_SMS_ENTRY_COUNT=100
+GLOBAL_EXPORT_FLAG += SIM_SMS_ENTRY_COUNT=255
+GLOBAL_EXPORT_FLAG += PHONE_PHB_ENTRY_COUNT=50
+
+## 电话本选项
+#MMI_EXPORT_FLAG += __MMI_PHB_SLIM_OPTIONAL_FIELD__
+#MMI_EXPORT_FLAG += __PHB_CALLER_IMAGE_SAVE_PATH_ONLY__
+
+
+#######################################
+## PART D
+##-------------------------------------
+## 编译调试描述信息
+#######################################
+
+
+#=====================================
+## 26 ##
+######## 编译优化选项 ########
+
+## 编译代码空间优化
+CT_OPT ?= dbg_size
+
+## 编译时候遇到warnning不停止编译
+WITHOUT_WERROR ?= 1
+
+# Export board information to lod: yes/no
+EXPORT_BOARD_INFO ?= yes
+# User defined board information
+EXPORT_BOARD_FLAGS ?= PM_MODEL ATV_MODEL FM_MODEL
+
+
+#=====================================
+## 27 ##
+######## 调试选项 ########
+
+## 通过SPI调试射频寄存器参数
+TARGET_EXPORT_FLAG += SPI_REG_DEBUG
+
+## For FS debug ,open ASSERT in FS layer
+TARGET_EXPORT_FLAG += _FS_DEBUG
+
+## Profile
+## Enable this macro if profile is needed in any module
+TARGET_EXPORT_FLAG += HAL_PROFILE_ON_BUFFER
+## Individual modules
+TARGET_EXPORT_FLAG += SX_PROFILING
+TARGET_EXPORT_FLAG += PAL_PROFILING
+TARGET_EXPORT_FLAG += HAL_PROFILING
+TARGET_EXPORT_FLAG += STK_PROFILING
+TARGET_EXPORT_FLAG += AT_PROFILING
+#TARGET_EXPORT_FLAG += PMD_PROFILING
+#TARGET_EXPORT_FLAG += TSD_PROFILING
+#TARGET_EXPORT_FLAG += DUALSIMD_PROFILING
+
+## Trace
+## Disable this macro if trace is needed in any module
+#TARGET_EXPORT_FLAG += SXS_NO_PRINTF
+## Individual modules
+TARGET_EXPORT_FLAG += MMI_NO_TRACE
+#TARGET_EXPORT_FLAG += CSW_NO_TRACE
+TARGET_EXPORT_FLAG += MCI_NO_TRACE
+TARGET_EXPORT_FLAG += STACK_NO_PRINTF
+#TARGET_EXPORT_FLAG += HAL_NO_PRINTF
+#TARGET_EXPORT_FLAG += PAL_NO_TRACE
+TARGET_EXPORT_FLAG += VOIS_NO_PRINTF
+#TARGET_EXPORT_FLAG += EDRV_NO_TRACE
+TARGET_EXPORT_FLAG += CALIB_NO_PRINTF
+TARGET_EXPORT_FLAG += UCTLS_NO_PRINTF
+TARGET_EXPORT_FLAG += UMSS_NO_PRINTF
+TARGET_EXPORT_FLAG += ARS_NO_PRINTF
+TARGET_EXPORT_FLAG += RFD_NO_TRACE
+## Dump
+#TARGET_EXPORT_FLAG += SXS_NO_DUMP
+
+## 系统启动时，尽早打开trace
+#TARGET_EXPORT_FLAG += EARLY_TRACE_OPEN
+
+
+#######################################
+## PART E
+##-------------------------------------
+## 项目定制信息
+#######################################
+
+
+#=====================================
+## 28 ##
+######## 与资源包相关的设置 ######
+
+## 是否需要下面这些设置取决于CT_ERES指定的资源包
+
+## 日历
+#MMI_EXPORT_FLAG += CALENDAR_SUPPORT
+## 任务
+#MMI_EXPORT_FLAG += TODOLIST_SUPPORT
+## 工具箱
+#MMI_EXPORT_FLAG += ORGANIZER_SUPPORT
+
+## More ...
+
+
+
+#=====================================
+## 29 ##
+######## 项目特有功能 ######
+
+#GLOBAL_EXPORT_FLAG += PROJ_XXX
+#TARGET_EXPORT_FLAG  += lcd_line_8_low
+
+#GLOBAL_EXPORT_FLAG += __MMI_NEW_NVRAM_INTERFACE__
+
+# Support remote keypad simulation
+TARGET_EXPORT_FLAG += REMOTE_KEYPAD_SIMU
+
+GLOBAL_EXPORT_FLAG += XCV_USE_LNA
+
+#######################################
+## PART Z
+##-------------------------------------
+## 通用设置，请勿修改，并保证此部分在文件的最后
+#######################################
+
+include ${SOFT_WORKDIR}/target/target_common.def
+
diff --git a/tools/.gitignore b/tools/.gitignore
deleted file mode 100644
index e4d2c2f55e..0000000000
--- a/tools/.gitignore
+++ /dev/null
@@ -1,18 +0,0 @@
-/bmp_logo
-/envcrc
-/gen_eth_addr
-/img2srec
-/mkenvimage
-/mkimage
-/mpc86x_clk
-/mxsboot
-/ncb
-/ncp
-/ubsha1
-/inca-swap-bytes
-/*.exe
-/easylogo/easylogo
-/env/crc32.c
-/env/fw_printenv
-/gdb/gdbcont
-/gdb/gdbsend
diff --git a/tools/checkpatch.pl b/tools/checkpatch.pl
index 2048a449b5..2048a449b5 100755..100644
--- a/tools/checkpatch.pl
+++ b/tools/checkpatch.pl
diff --git a/tools/checkstack.pl b/tools/checkstack.pl
index c1cdc0a92a..c1cdc0a92a 100755..100644
--- a/tools/checkstack.pl
+++ b/tools/checkstack.pl
diff --git a/tools/gcc-version.sh b/tools/gcc-version.sh
new file mode 100755
index 0000000000..debecb5561
--- /dev/null
+++ b/tools/gcc-version.sh
@@ -0,0 +1,32 @@
+#!/bin/sh
+#
+# gcc-version [-p] gcc-command
+#
+# Prints the gcc version of `gcc-command' in a canonical 4-digit form
+# such as `0295' for gcc-2.95, `0303' for gcc-3.3, etc.
+#
+# With the -p option, prints the patchlevel as well, for example `029503' for
+# gcc-2.95.3, `030301' for gcc-3.3.1, etc.
+#
+
+if [ "$1" = "-p" ] ; then
+	with_patchlevel=1;
+	shift;
+fi
+
+compiler="$*"
+
+if [ ${#compiler} -eq 0 ]; then
+	echo "Error: No compiler specified."
+	printf "Usage:\n\t$0 <gcc-command>\n"
+	exit 1
+fi
+
+MAJOR=$(echo __GNUC__ | $compiler -E -xc - | tail -n 1)
+MINOR=$(echo __GNUC_MINOR__ | $compiler -E -xc - | tail -n 1)
+if [ "x$with_patchlevel" != "x" ] ; then
+	PATCHLEVEL=$(echo __GNUC_PATCHLEVEL__ | $compiler -E -xc - | tail -n 1)
+	printf "%02d%02d%02d\\n" $MAJOR $MINOR $PATCHLEVEL
+else
+	printf "%02d%02d\\n" $MAJOR $MINOR
+fi
diff --git a/tools/img2srec b/tools/img2srec
new file mode 100755
index 0000000000..7dd8e0c972
--- /dev/null
+++ b/tools/img2srec
diff --git a/tools/jtagconsole b/tools/jtagconsole
index d404fac5e8..d404fac5e8 100755..100644
--- a/tools/jtagconsole
+++ b/tools/jtagconsole
diff --git a/tools/mkenvimage b/tools/mkenvimage
new file mode 100755
index 0000000000..b2233a13a1
--- /dev/null
+++ b/tools/mkenvimage
diff --git a/tools/mkenvimage.c b/tools/mkenvimage.c
index bfc4eb636b..1a53e20f87 100644
--- a/tools/mkenvimage.c
+++ b/tools/mkenvimage.c
@@ -41,7 +41,7 @@
 
 #include "compiler.h"
 #include <u-boot/crc.h>
-#include <version.h>
+#include "generated/version_autogenerated.h"
 
 #define CRC_SIZE sizeof(uint32_t)
 
diff --git a/tools/mkimage b/tools/mkimage
new file mode 100755
index 0000000000..9dd3476908
--- /dev/null
+++ b/tools/mkimage
diff --git a/tools/mkimage.c b/tools/mkimage.c
index eeb1b10668..597147d141 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -23,7 +23,7 @@
 
 #include "mkimage.h"
 #include <image.h>
-#include <version.h>
+#include "generated/version_autogenerated.h"
 
 static void copy_file(int, const char *, int);
 static void usage(void);
diff --git a/tools/mkrdaimage.sh b/tools/mkrdaimage.sh
new file mode 100755
index 0000000000..c9573242b6
--- /dev/null
+++ b/tools/mkrdaimage.sh
@@ -0,0 +1,113 @@
+#!/bin/bash
+
+#bootloader layout
+
+#normal bootloader(for pagesize_is_power_of_2)
+#################################
+#                               #
+# 48K (spl.img + padding 0)     #
+#                               #
+#                               #
+#################################
+#                               #
+#                               #
+# 24K resevered for part table  #
+#     (fill 0)                  #
+#                               #
+#################################
+#                               #
+#                               #
+# u-boot                        #
+#                               #
+#                               #
+#################################
+
+#pagesize not aligned bootloader(pagesize is 12288, not power_of_2)
+#e.g. 12k pagesize
+#################################
+#                               #
+# spl(1st 2k)                   #
+#                               #
+#                               #
+#################################
+#                               #
+# 10K (padding with 0xff)       #
+#                               #
+#                               #
+#################################
+#                               #
+# spl(2nd 2k)                   #
+#                               #
+#                               #
+#################################
+#                               #
+# 10K (padding with 0xff)       #
+#                               #
+#                               #
+#################################
+#                               #
+# ....                          #
+#                               #
+#                               #
+#################################
+#                               #
+# spl(24th 2k)                  #
+#                               #
+#                               #
+#################################
+#                               #
+# 10K (padding with 0xff)       #
+#                               #
+#                               #
+#################################
+#                               #
+#                               #
+# 24K resevered for part table  #
+#     (fill 0)                  #
+#                               #
+#################################
+#                               #
+#                               #
+# u-boot                        #
+#                               #
+#                               #
+#################################
+pagesize=$1
+spl_image=$2
+uboot_image=$3
+spl_append_to=$4
+output_image=$5
+#expand the spl to whole 48k
+dd if=/dev/zero ibs=1k count=48 of=spl-padding.img obs=1k conv=sync  >& /dev/null
+dd if=$spl_image of=spl-padding.img bs=2k conv=notrunc >& /dev/null
+
+temp_image=tmp_image
+if [ $pagesize -eq 12288 ]
+then :
+	#segments is the max_sizeof_spl(48K) / 2k(romcode's real pagesize)
+	segments=24
+	i=0
+	iblock=0
+	oblock=0
+	tr "\000" "\377" < /dev/zero | dd ibs=12k count=26 of=$temp_image conv=sync
+	while [ $i -lt $segments ]
+	do
+		#echo "read " "spl-padding.img" " pos " $iblock
+		#echo "write to " $temp_image " pos " $oblock
+		dd if=spl-padding.img of=$temp_image ibs=1k skip=$iblock obs=1k\
+			seek=$oblock count=2 conv=notrunc >& /dev/null
+		i=$[$i + 1]
+		iblock=$[$iblock + 2]
+		oblock=$[$oblock + 12]
+	done
+	#echo "write to " $temp_image " pos " $oblock
+	dd if=/dev/zero of=$temp_image ibs=1k obs=1k seek=$oblock count=24 \
+			conv=notrunc >& /dev/null
+else #this is normal case
+	dd if=/dev/zero ibs=1k count=$spl_append_to of=$temp_image obs=1k \
+			conv=sync >& /dev/null
+	dd if=spl-padding.img of=$temp_image bs=2k conv=notrunc >& /dev/null
+fi
+cat $temp_image $uboot_image > $output_image
+rm -rf $temp_image spl-padding.img
+
diff --git a/tools/netconsole b/tools/netconsole
index c8109bb095..c8109bb095 100755..100644
--- a/tools/netconsole
+++ b/tools/netconsole
diff --git a/tools/patman/.gitignore b/tools/patman/.gitignore
deleted file mode 100644
index 0d20b6487c..0000000000
--- a/tools/patman/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-*.pyc
diff --git a/tools/patman/README b/tools/patman/README
index 587c97fc88..7ba9e804d5 100644
--- a/tools/patman/README
+++ b/tools/patman/README
@@ -93,17 +93,17 @@ How to run it
 
 First do a dry run:
 
-$ ./tools/scripts/patman/patman -n
+$ ./tools/patman/patman -n
 
 If it can't detect the upstream branch, try telling it how many patches
 there are in your series:
 
-$ ./tools/scripts/patman/patman -n -c5
+$ ./tools/patman/patman -n -c5
 
 This will create patch files in your current directory and tell you who
 it is thinking of sending them to. Take a look at the patch files.
 
-$ ./tools/scripts/patman/patman -n -c5 -s1
+$ ./tools/patman/patman -n -c5 -s1
 
 Similar to the above, but skip the first commit and take the next 5. This
 is useful if your top commit is for setting up testing.
@@ -197,7 +197,7 @@ patch series and see how the patches turn out.
 Where Patches Are Sent
 ======================
 
-Once the patches are created, patman sends them using gti send-email. The
+Once the patches are created, patman sends them using git send-email. The
 whole series is sent to the recipients in Series-to: and Series-cc.
 You can Cc individual patches to other people with the Cc: tag. Tags in the
 subject are also picked up to Cc patches. For example, a commit like this:
diff --git a/tools/patman/patman b/tools/patman/patman
index 6cc3d7a56a..6cc3d7a56a 120000..100644
--- a/tools/patman/patman
+++ b/tools/patman/patman
diff --git a/tools/patman/patman.py b/tools/patman/patman.py
index cfe06d0823..cfe06d0823 100755..100644
--- a/tools/patman/patman.py
+++ b/tools/patman/patman.py
diff --git a/tools/scripts/README b/tools/scripts/README
index 046c1d411c..046c1d411c 100644..100755
--- a/tools/scripts/README
+++ b/tools/scripts/README
diff --git a/tools/scripts/define2mk.sed b/tools/scripts/define2mk.sed
index 13e2845e76..13e2845e76 100644..100755
--- a/tools/scripts/define2mk.sed
+++ b/tools/scripts/define2mk.sed
diff --git a/tools/scripts/dot.kermrc b/tools/scripts/dot.kermrc
index 0fc6c15d35..0fc6c15d35 100644..100755
--- a/tools/scripts/dot.kermrc
+++ b/tools/scripts/dot.kermrc
diff --git a/tools/scripts/flash_param b/tools/scripts/flash_param
index 847f99e1eb..847f99e1eb 100644..100755
--- a/tools/scripts/flash_param
+++ b/tools/scripts/flash_param
diff --git a/tools/scripts/send_cmd b/tools/scripts/send_cmd
index 4131331f03..4131331f03 100644..100755
--- a/tools/scripts/send_cmd
+++ b/tools/scripts/send_cmd
diff --git a/tools/scripts/send_image b/tools/scripts/send_image
index 9b89d6b059..9b89d6b059 100644..100755
--- a/tools/scripts/send_image
+++ b/tools/scripts/send_image