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| author | Daniel Thompson <daniel.thompson@linaro.org> | 2017-07-30 08:09:38 +0100 |
|---|---|---|
| committer | Daniel Thompson <daniel.thompson@linaro.org> | 2017-07-31 17:26:26 +0100 |
| commit | d5fbf297ca6842d0e104740220efbc1c1c08a168 (patch) | |
| tree | ec730cbfa76e9c40fb8c232712c8baae192b5b3e | |
| parent | 9bcead947759f21e17341e1cbbe3efec62b5dd82 (diff) | |
include: rda: ddr_timing: 8810p_16x2_260m_ddr2_u08: RDA support
| -rw-r--r-- | include/rda/ddr_timing/8810p_16x2_260m_ddr2_u08.h | 84 |
1 files changed, 84 insertions, 0 deletions
diff --git a/include/rda/ddr_timing/8810p_16x2_260m_ddr2_u08.h b/include/rda/ddr_timing/8810p_16x2_260m_ddr2_u08.h new file mode 100644 index 0000000000..59c2c897c3 --- /dev/null +++ b/include/rda/ddr_timing/8810p_16x2_260m_ddr2_u08.h @@ -0,0 +1,84 @@ +#define DDR_TIMIMG_NAME "8810p_16x2_260m_ddr2_u08" + +#define PMU_VBUCK1_VAL 9 +#define PMU_VBUCK3_VAL 10 + +#define DDR_VTT_VAL 1 + +#define DDR_CHAN_1_VALID_VAL 1 +#define DDR_CHAN_2_VALID_VAL 1 +#define DDR_CHAN_3_VALID_VAL 1 +#define DDR_CHAN_4_VALID_VAL 1 + +#define DDR_TIMING_100H_VAL 0x0000 +#define DDR_TIMING_101H_VAL 0x0000 +#define DDR_TIMING_102H_VAL 0x0000 +#define DDR_TIMING_103H_VAL 0x24b0 +#define DDR_TIMING_104H_VAL 0x3333 + +#define DDR_TIMING_105H_VAL 0x3333 +#define DDR_TIMING_106H_VAL 0x0263 +#define DDR_TIMING_107H_VAL 0x1144 +#define DDR_TIMING_108H_VAL 0x0000 + +#define DDR_TIMING_109H_VAL 0x1101 +#define DDR_TIMING_10AH_VAL 0x0001 +#define DDR_TIMING_10BH_VAL 0x0003 + +#define DDR_TIMING_120H_VAL 0x0000 +#define DDR_TIMING_121H_VAL 0x0000 +#define DDR_TIMING_122H_VAL 0x0000 +#define DDR_TIMING_123H_VAL 0x24b0 +#define DDR_TIMING_124H_VAL 0x3333 + +#define DDR_TIMING_125H_VAL 0x3333 +#define DDR_TIMING_126H_VAL 0x0263 +#define DDR_TIMING_127H_VAL 0x1144 +#define DDR_TIMING_128H_VAL 0x0000 +#define DDR_TIMING_129H_VAL 0x1101 +#define DDR_TIMING_12AH_VAL 0x0001 +#define DDR_TIMING_12BH_VAL 0x0003 + +#define DDR_TIMING_140H_VAL 0x0000 +#define DDR_TIMING_141H_VAL 0x0000 +#define DDR_TIMING_142H_VAL 0x0000 +#define DDR_TIMING_143H_VAL 0x24b0 +#define DDR_TIMING_144H_VAL 0x3333 +#define DDR_TIMING_145H_VAL 0x3333 +#define DDR_TIMING_146H_VAL 0x0263 +#define DDR_TIMING_147H_VAL 0x1144 +#define DDR_TIMING_148H_VAL 0x0000 +#define DDR_TIMING_149H_VAL 0x1101 +#define DDR_TIMING_14AH_VAL 0x0001 +#define DDR_TIMING_14BH_VAL 0x0003 + + +#define DDR_TIMING_161H_VAL 0x0000 +#define DDR_TIMING_162H_VAL 0x0000 +#define DDR_TIMING_163H_VAL 0x24b0 +#define DDR_TIMING_164H_VAL 0x3333 +#define DDR_TIMING_165H_VAL 0x3333 +#define DDR_TIMING_166H_VAL 0x0263 +#define DDR_TIMING_167H_VAL 0x1144 +#define DDR_TIMING_168H_VAL 0x0000 +#define DDR_TIMING_169H_VAL 0x1101 +#define DDR_TIMING_16AH_VAL 0x0001 +#define DDR_TIMING_16BH_VAL 0x0003 + +#define DDR_TIMING_180H_VAL 0x6666 +#define DDR_TIMING_181H_VAL 0x3333 +#define DDR_TIMING_182H_VAL 0x3333 +#define DDR_TIMING_183H_VAL 0x3333 +#define DDR_TIMING_184H_VAL 0x3333 +#define DDR_TIMING_185H_VAL 0x3333 +#define DDR_TIMING_186H_VAL 0x3333 +#define DDR_TIMING_187H_VAL 0x3333 +#define DDR_TIMING_188H_VAL 0x0001 +#define DDR_TIMING_189H_VAL 0x0000 +#define DDR_TIMING_18AH_VAL 0x1144 +#define DDR_TIMING_18BH_VAL 0x0010 +#define DDR_TIMING_18CH_VAL 0x0000 + +#define DDR_TIMING_160H_VAL 0x0000 +#define DDR_TIMING_69H_VAL 0x0009 + |