From 3b2039b26619745a736b896caf8df05a2a15df3a Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 12:42:30 +1000 Subject: m68knommu: make 528x QSPI platform addressing consistent If we make all QSPI (SPI protocol) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and code and use a single setup for all. So modify the ColdFire 528x QSPI addressing so that: . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used . move chip select definitions (CS) to appropriate header Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m528xsim.h | 13 +++++++++++++ arch/m68k/include/asm/mcfqspi.h | 4 +--- 2 files changed, 14 insertions(+), 3 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h index a363c648b97..e4581a4a103 100644 --- a/arch/m68k/include/asm/m528xsim.h +++ b/arch/m68k/include/asm/m528xsim.h @@ -51,6 +51,8 @@ #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) +#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) + /* * SDRAM configuration registers. */ @@ -81,6 +83,17 @@ #define MCFFEC_BASE0 (MCF_IPSBAR + 0x00001000) #define MCFFEC_SIZE0 0x800 +/* + * QSPI module. + */ +#define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340) +#define MCFQSPI_SIZE 0x40 + +#define MCFQSPI_CS0 147 +#define MCFQSPI_CS1 148 +#define MCFQSPI_CS2 149 +#define MCFQSPI_CS3 150 + /* * GPIO registers */ diff --git a/arch/m68k/include/asm/mcfqspi.h b/arch/m68k/include/asm/mcfqspi.h index 57fcbc2c0da..f3d9640f788 100644 --- a/arch/m68k/include/asm/mcfqspi.h +++ b/arch/m68k/include/asm/mcfqspi.h @@ -21,9 +21,7 @@ #ifndef mcfqspi_h #define mcfqspi_h -#if defined(CONFIG_M528x) -#define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340) -#elif defined(CONFIG_M532x) +#if defined(CONFIG_M532x) #define MCFQSPI_IOBASE 0xFC058000 #endif #define MCFQSPI_IOSIZE 0x40 -- cgit v1.2.3