From 9517746131f62294ddd922bcd288415be5104c23 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 23 Jan 2012 13:25:56 +1000 Subject: m68knommu: make persistent clock code consistent with m68k The read_persistent_clock() code is different on m68knommu, for really no reason. With a few changes to support function names and some code re-organization the code can be made the same. This will make it easier to merge the arch/m68k/kernel/time.c for m68k and m68knommu in a future patch. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/machdep.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/machdep.h b/arch/m68k/include/asm/machdep.h index 789f3b2de0e..3bfa7df3572 100644 --- a/arch/m68k/include/asm/machdep.h +++ b/arch/m68k/include/asm/machdep.h @@ -22,8 +22,6 @@ extern unsigned int (*mach_get_ss)(void); extern int (*mach_get_rtc_pll)(struct rtc_pll_info *); extern int (*mach_set_rtc_pll)(struct rtc_pll_info *); extern int (*mach_set_clock_mmss)(unsigned long); -extern void (*mach_gettod)(int *year, int *mon, int *day, int *hour, - int *min, int *sec); extern void (*mach_reset)( void ); extern void (*mach_halt)( void ); extern void (*mach_power_off)( void ); -- cgit v1.2.3 From 35aefb2645d1ae7576699b2d7b66d6c9503113fc Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Mon, 23 Jan 2012 15:34:58 +1000 Subject: m68knommu: modify timer init code to make it consistent with m68k code With a few small changes we can make the m68knommu timer init code the same as the m68k code. By using the mach_sched_init function pointer and reworking the current timer initializers to keep track of the common m68k timer_interrupt() handler we end up with almost identical code for m68knommu. This will allow us to more easily merge the mmu and non-mmu m68k time.c in future patches. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/machdep.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/machdep.h b/arch/m68k/include/asm/machdep.h index 3bfa7df3572..825c1c81319 100644 --- a/arch/m68k/include/asm/machdep.h +++ b/arch/m68k/include/asm/machdep.h @@ -33,9 +33,8 @@ extern void (*mach_l2_flush) (int); extern void (*mach_beep) (unsigned int, unsigned int); /* Hardware clock functions */ -extern void hw_timer_init(void); +extern void hw_timer_init(irq_handler_t handler); extern unsigned long hw_timer_offset(void); -extern irqreturn_t arch_timer_interrupt(int irq, void *dummy); extern void config_BSP(char *command, int len); -- cgit v1.2.3 From 8400ca322e2fb6771d2adfc05a745b8872af038d Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 00:10:48 +1000 Subject: m68knommu: make 5206 UART platform addressing consistent If we make all UART addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 5206 UART addressing so that: . UARTs are numbered from 0 up . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m5206sim.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h index 9015eadd5c0..69722366b08 100644 --- a/arch/m68k/include/asm/m5206sim.h +++ b/arch/m68k/include/asm/m5206sim.h @@ -100,11 +100,11 @@ #define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */ #if defined(CONFIG_NETtel) -#define MCFUART_BASE1 0x180 /* Base address of UART1 */ -#define MCFUART_BASE2 0x140 /* Base address of UART2 */ +#define MCFUART_BASE0 (MCF_MBAR + 0x180) /* Base address UART0 */ +#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */ #else -#define MCFUART_BASE1 0x140 /* Base address of UART1 */ -#define MCFUART_BASE2 0x180 /* Base address of UART2 */ +#define MCFUART_BASE0 (MCF_MBAR + 0x140) /* Base address UART0 */ +#define MCFUART_BASE1 (MCF_MBAR + 0x180) /* Base address UART1 */ #endif /* @@ -112,6 +112,8 @@ */ #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ +#define MCF_IRQ_UART0 73 /* UART0 */ +#define MCF_IRQ_UART1 74 /* UART1 */ /* * Generic GPIO -- cgit v1.2.3 From ffc203bc19eda0e58fea1bdf8172f313f26f8722 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 00:21:18 +1000 Subject: m68knommu: make 520x UART platform addressing consistent If we make all UART addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 520x UART addressing so that: . UARTs are numbered from 0 up . use a common name for IRQs used Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m520xsim.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h index eda62de7e60..41ed4dc8d73 100644 --- a/arch/m68k/include/asm/m520xsim.h +++ b/arch/m68k/include/asm/m520xsim.h @@ -50,6 +50,10 @@ #define MCFINT_QSPI 31 /* Interrupt number for QSPI */ #define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ +#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) +#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) +#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) + /* * SDRAM configuration registers. */ @@ -144,9 +148,9 @@ /* * UART module. */ -#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */ -#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */ -#define MCFUART_BASE3 0xFC068000 /* Base address of UART2 */ +#define MCFUART_BASE0 0xFC060000 /* Base address of UART0 */ +#define MCFUART_BASE1 0xFC064000 /* Base address of UART1 */ +#define MCFUART_BASE2 0xFC068000 /* Base address of UART2 */ /* * FEC module. -- cgit v1.2.3 From 13682af34914b553505cce3e417f76b35a0f8d01 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 00:25:28 +1000 Subject: m68knommu: make 523x UART platform addressing consistent If we make all UART addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 523x UART addressing so that: . UARTs are numbered from 0 up . use a common name for IRQs used Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m523xsim.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h index 6235921eca4..919d115bd16 100644 --- a/arch/m68k/include/asm/m523xsim.h +++ b/arch/m68k/include/asm/m523xsim.h @@ -35,9 +35,15 @@ #define MCFINT_VECBASE 64 /* Vector base number */ #define MCFINT_UART0 13 /* Interrupt number for UART0 */ +#define MCFINT_UART1 14 /* Interrupt number for UART1 */ +#define MCFINT_UART2 15 /* Interrupt number for UART2 */ #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ +#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) +#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) +#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) + /* * SDRAM configuration registers. */ @@ -59,9 +65,9 @@ /* * UART module. */ -#define MCFUART_BASE1 (MCF_IPSBAR + 0x200) -#define MCFUART_BASE2 (MCF_IPSBAR + 0x240) -#define MCFUART_BASE3 (MCF_IPSBAR + 0x280) +#define MCFUART_BASE0 (MCF_IPSBAR + 0x200) +#define MCFUART_BASE1 (MCF_IPSBAR + 0x240) +#define MCFUART_BASE2 (MCF_IPSBAR + 0x280) /* * FEC ethernet module. -- cgit v1.2.3 From e8f69e545e51b9f2870d64082db533557b8d0d09 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 00:28:18 +1000 Subject: m68knommu: make 5249 UART platform addressing consistent If we make all UART addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 5249 UART addressing so that: . UARTs are numbered from 0 up . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m5249sim.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h index 805714ca8d7..3e31508619c 100644 --- a/arch/m68k/include/asm/m5249sim.h +++ b/arch/m68k/include/asm/m5249sim.h @@ -76,8 +76,8 @@ /* * UART module. */ -#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ -#define MCFUART_BASE2 0x200 /* Base address of UART2 */ +#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */ +#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */ /* * DMA unit base addresses. @@ -108,6 +108,9 @@ #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ +#define MCF_IRQ_UART0 73 /* UART0 */ +#define MCF_IRQ_UART1 74 /* UART1 */ + /* * General purpose IO registers (in MBAR2). */ -- cgit v1.2.3 From 023e0555a91988a67868077bf0fb1084d3745293 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 00:30:37 +1000 Subject: m68knommu: make 5272 UART platform addressing consistent If we make all UART addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 5272 UART addressing so that: . UARTs are numbered from 0 up . base addresses are absolute (not relative to MBAR peripheral register) Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m5272sim.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h index 759c2b07a99..5c71bd4c746 100644 --- a/arch/m68k/include/asm/m5272sim.h +++ b/arch/m68k/include/asm/m5272sim.h @@ -68,8 +68,8 @@ #define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ #define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ -#define MCFUART_BASE1 0x100 /* Base address of UART1 */ -#define MCFUART_BASE2 0x140 /* Base address of UART2 */ +#define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */ +#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */ #define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */ #define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */ @@ -101,8 +101,8 @@ #define MCF_IRQ_TIMER2 70 /* Timer 2 */ #define MCF_IRQ_TIMER3 71 /* Timer 3 */ #define MCF_IRQ_TIMER4 72 /* Timer 4 */ -#define MCF_IRQ_UART1 73 /* UART 1 */ -#define MCF_IRQ_UART2 74 /* UART 2 */ +#define MCF_IRQ_UART0 73 /* UART 0 */ +#define MCF_IRQ_UART1 74 /* UART 1 */ #define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */ #define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */ #define MCF_IRQ_USB0 77 /* USB Endpoint 0 */ -- cgit v1.2.3 From 20e681fdfa077b6a4e0fb777f10aa3c4bf34ece8 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 00:33:31 +1000 Subject: m68knommu: make 527x UART platform addressing consistent If we make all UART addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 527x UART addressing so that: . UARTs are numbered from 0 up . use a common name for IRQs used Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m527xsim.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h index 758810ef91e..7399968b2ef 100644 --- a/arch/m68k/include/asm/m527xsim.h +++ b/arch/m68k/include/asm/m527xsim.h @@ -40,6 +40,10 @@ #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ +#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) +#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) +#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) + /* * SDRAM configuration registers. */ @@ -72,9 +76,9 @@ /* * UART module. */ -#define MCFUART_BASE1 (MCF_IPSBAR + 0x200) -#define MCFUART_BASE2 (MCF_IPSBAR + 0x240) -#define MCFUART_BASE3 (MCF_IPSBAR + 0x280) +#define MCFUART_BASE0 (MCF_IPSBAR + 0x200) +#define MCFUART_BASE1 (MCF_IPSBAR + 0x240) +#define MCFUART_BASE2 (MCF_IPSBAR + 0x280) /* * FEC ethernet module. -- cgit v1.2.3 From 909159feb3415afc6300281c9dfa856aa3875c32 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 00:36:03 +1000 Subject: m68knommu: make 5307 UART platform addressing consistent If we make all UART addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 5307 UART addressing so that: . UARTs are numbered from 0 up . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m5307sim.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h index 8f8609fcc9b..3bc3adaa7ee 100644 --- a/arch/m68k/include/asm/m5307sim.h +++ b/arch/m68k/include/asm/m5307sim.h @@ -117,11 +117,11 @@ * UART module. */ #if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3) -#define MCFUART_BASE1 0x200 /* Base address of UART1 */ -#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */ +#define MCFUART_BASE0 (MCF_MBAR + 0x200) /* Base address UART0 */ +#define MCFUART_BASE1 (MCF_MBAR + 0x1c0) /* Base address UART1 */ #else -#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ -#define MCFUART_BASE2 0x200 /* Base address of UART2 */ +#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */ +#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */ #endif /* @@ -176,6 +176,8 @@ */ #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ +#define MCF_IRQ_UART0 73 /* UART0 */ +#define MCF_IRQ_UART1 74 /* UART1 */ /****************************************************************************/ #endif /* m5307sim_h */ -- cgit v1.2.3 From f8bb5327a8aae4469563b2e47b6cef1bd2eb3555 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 00:39:04 +1000 Subject: m68knommu: make 528x UART platform addressing consistent If we make all UART addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 528x UART addressing so that: . UARTs are numbered from 0 up . use a common name for IRQs used Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m528xsim.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h index d798bd5df56..a5f0c14b47d 100644 --- a/arch/m68k/include/asm/m528xsim.h +++ b/arch/m68k/include/asm/m528xsim.h @@ -35,9 +35,15 @@ #define MCFINT_VECBASE 64 /* Vector base number */ #define MCFINT_UART0 13 /* Interrupt number for UART0 */ +#define MCFINT_UART1 14 /* Interrupt number for UART1 */ +#define MCFINT_UART2 15 /* Interrupt number for UART2 */ #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ #define MCFINT_PIT1 55 /* Interrupt number for PIT1 */ +#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) +#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) +#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) + /* * SDRAM configuration registers. */ @@ -58,9 +64,9 @@ /* * UART module. */ -#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000200) -#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000240) -#define MCFUART_BASE3 (MCF_IPSBAR + 0x00000280) +#define MCFUART_BASE0 (MCF_IPSBAR + 0x00000200) +#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000240) +#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000280) /* * FEC ethernet module. -- cgit v1.2.3 From 35b7cf22c6b2481f7c425f30898214f73376834d Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 00:41:07 +1000 Subject: m68knommu: make 532x UART platform addressing consistent If we make all UART addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 532x UART addressing so that: . UARTs are numbered from 0 up . use a common name for IRQs used Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m532xsim.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h index ba4cc784f57..f963d64c94e 100644 --- a/arch/m68k/include/asm/m532xsim.h +++ b/arch/m68k/include/asm/m532xsim.h @@ -25,6 +25,10 @@ #define MCFINT_UART2 28 /* Interrupt number for UART2 */ #define MCFINT_QSPI 31 /* Interrupt number for QSPI */ +#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) +#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) +#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) + #define MCF_WTM_WCR MCF_REG16(0xFC098000) /* @@ -82,9 +86,9 @@ /* * UART module. */ -#define MCFUART_BASE1 0xFC060000 /* Base address of UART1 */ -#define MCFUART_BASE2 0xFC064000 /* Base address of UART2 */ -#define MCFUART_BASE3 0xFC068000 /* Base address of UART3 */ +#define MCFUART_BASE0 0xFC060000 /* Base address of UART1 */ +#define MCFUART_BASE1 0xFC064000 /* Base address of UART2 */ +#define MCFUART_BASE2 0xFC068000 /* Base address of UART3 */ /* * Timer module. -- cgit v1.2.3 From 69d23b610a04e269d6a094e6f3e37d85d6b2784a Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 00:43:13 +1000 Subject: m68knommu: make 5407 UART platform addressing consistent If we make all UART addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 5407 UART addressing so that: . UARTs are numbered from 0 up . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m5407sim.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h index 51e00b00b8a..79f58dd6a83 100644 --- a/arch/m68k/include/asm/m5407sim.h +++ b/arch/m68k/include/asm/m5407sim.h @@ -85,8 +85,8 @@ #define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ #define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ -#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ -#define MCFUART_BASE2 0x200 /* Base address of UART2 */ +#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */ +#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */ #define MCFSIM_PADDR (MCF_MBAR + 0x244) #define MCFSIM_PADAT (MCF_MBAR + 0x248) @@ -139,6 +139,8 @@ */ #define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ #define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ +#define MCF_IRQ_UART0 73 /* UART0 */ +#define MCF_IRQ_UART1 74 /* UART1 */ /****************************************************************************/ #endif /* m5407sim_h */ -- cgit v1.2.3 From bbbeeaf2f74b634c95af3492e4958e752966eaa5 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 00:46:37 +1000 Subject: m68knommu: make 54xx UART platform addressing consistent If we make all UART addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 54xx UART addressing so that: . UARTs are numbered from 0 up . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m54xxsim.h | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h index 1ed8bfb0277..ae56b8848a9 100644 --- a/arch/m68k/include/asm/m54xxsim.h +++ b/arch/m68k/include/asm/m54xxsim.h @@ -31,16 +31,20 @@ /* * UART module. */ -#define MCFUART_BASE1 0x8600 /* Base address of UART1 */ -#define MCFUART_BASE2 0x8700 /* Base address of UART2 */ -#define MCFUART_BASE3 0x8800 /* Base address of UART3 */ -#define MCFUART_BASE4 0x8900 /* Base address of UART4 */ +#define MCFUART_BASE0 (MCF_MBAR + 0x8600) /* Base address UART0 */ +#define MCFUART_BASE1 (MCF_MBAR + 0x8700) /* Base address UART1 */ +#define MCFUART_BASE2 (MCF_MBAR + 0x8800) /* Base address UART2 */ +#define MCFUART_BASE3 (MCF_MBAR + 0x8900) /* Base address UART3 */ /* * Define system peripheral IRQ usage. */ -#define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */ -#define MCF_IRQ_PROFILER (64 + 53) /* Slice Timer 1 */ +#define MCF_IRQ_TIMER (MCFINT_VECBASE + 54) /* Slice Timer 0 */ +#define MCF_IRQ_PROFILER (MCFINT_VECBASE + 53) /* Slice Timer 1 */ +#define MCF_IRQ_UART0 (MCFINT_VECBASE + 35) +#define MCF_IRQ_UART1 (MCFINT_VECBASE + 34) +#define MCF_IRQ_UART2 (MCFINT_VECBASE + 33) +#define MCF_IRQ_UART3 (MCFINT_VECBASE + 32) /* * Generic GPIO support -- cgit v1.2.3 From 55148f6f886a1b77dba1a5c3169208606827b9db Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 01:23:35 +1000 Subject: m68knommu: merge common ColdFire UART IRQ setup Some ColdFire CPU UART hardware modules can configure the IRQ they use. Currently the same setup code is duplicated in the init code for each of these ColdFire CPUs. Merge all this code to a single instance. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/mcfuart.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h index 2abedff0a69..2d3bc774b3c 100644 --- a/arch/m68k/include/asm/mcfuart.h +++ b/arch/m68k/include/asm/mcfuart.h @@ -41,7 +41,10 @@ struct mcf_platform_uart { #define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */ #define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */ #define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ -#else +#endif +#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ + defined(CONFIG_M5249) || defined(CONFIG_M5307) || \ + defined(CONFIG_M5407) #define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */ #endif #define MCFUART_UIPR 0x34 /* Input Port (r) */ -- cgit v1.2.3 From d4e08372e385169fdd3cb8cccd1f37892fd216d9 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 10:05:34 +1000 Subject: m68knommu: make 520x FEC platform addressing consistent If we make all FEC (ethernet) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 520x FEC addressing so that: . FECs are numbered from 0 up . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m520xsim.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h index 41ed4dc8d73..b83cee2dfda 100644 --- a/arch/m68k/include/asm/m520xsim.h +++ b/arch/m68k/include/asm/m520xsim.h @@ -48,12 +48,19 @@ #define MCFINT_UART1 27 /* Interrupt number for UART1 */ #define MCFINT_UART2 28 /* Interrupt number for UART2 */ #define MCFINT_QSPI 31 /* Interrupt number for QSPI */ +#define MCFINT_FECRX0 36 /* Interrupt number for FEC RX */ +#define MCFINT_FECTX0 40 /* Interrupt number for FEC RX */ +#define MCFINT_FECENTC0 42 /* Interrupt number for FEC RX */ #define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) +#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) +#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) +#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) + /* * SDRAM configuration registers. */ @@ -155,8 +162,8 @@ /* * FEC module. */ -#define MCFFEC_BASE 0xFC030000 /* Base of FEC ethernet */ -#define MCFFEC_SIZE 0x800 /* Register set size */ +#define MCFFEC_BASE0 0xFC030000 /* Base of FEC ethernet */ +#define MCFFEC_SIZE0 0x800 /* Register set size */ /* * Reset Control Unit. -- cgit v1.2.3 From 21634593b42308631788359cba9d7671383ae762 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 10:10:13 +1000 Subject: m68knommu: make 523x FEC platform addressing consistent If we make all FEC (ethernet) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 523x FEC addressing so that: . FECs are numbered from 0 up . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m523xsim.h | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h index 919d115bd16..e1988dd372f 100644 --- a/arch/m68k/include/asm/m523xsim.h +++ b/arch/m68k/include/asm/m523xsim.h @@ -37,13 +37,20 @@ #define MCFINT_UART0 13 /* Interrupt number for UART0 */ #define MCFINT_UART1 14 /* Interrupt number for UART1 */ #define MCFINT_UART2 15 /* Interrupt number for UART2 */ -#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ +#define MCFINT_FECRX0 23 /* Interrupt number for FEC */ +#define MCFINT_FECTX0 27 /* Interrupt number for FEC */ +#define MCFINT_FECENTC0 29 /* Interrupt number for FEC */ +#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) +#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) +#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) +#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) + /* * SDRAM configuration registers. */ @@ -72,8 +79,8 @@ /* * FEC ethernet module. */ -#define MCFFEC_BASE (MCF_IPSBAR + 0x1000) -#define MCFFEC_SIZE 0x800 +#define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000) +#define MCFFEC_SIZE0 0x800 /* * GPIO module. -- cgit v1.2.3 From 9a11b493edcc4b740bac5ccbe9167e4ef12e4668 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 10:13:36 +1000 Subject: m68knommu: make 5272 FEC platform addressing consistent If we make all FEC (ethernet) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 5272 FEC addressing so that: . FECs are numbered from 0 up . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m5272sim.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h index 5c71bd4c746..a58f1760d85 100644 --- a/arch/m68k/include/asm/m5272sim.h +++ b/arch/m68k/include/asm/m5272sim.h @@ -88,6 +88,9 @@ #define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */ #define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */ +#define MCFFEC_BASE0 (MCF_MBAR + 0x840) /* Base FEC ethernet */ +#define MCFFEC_SIZE0 0x1d0 + /* * Define system peripheral IRQ usage. */ @@ -114,9 +117,9 @@ #define MCF_IRQ_USB6 83 /* USB Endpoint 6 */ #define MCF_IRQ_USB7 84 /* USB Endpoint 7 */ #define MCF_IRQ_DMA 85 /* DMA Controller */ -#define MCF_IRQ_ERX 86 /* Ethernet Receiver */ -#define MCF_IRQ_ETX 87 /* Ethernet Transmitter */ -#define MCF_IRQ_ENTC 88 /* Ethernet Non-Time Critical */ +#define MCF_IRQ_FECRX0 86 /* Ethernet Receiver */ +#define MCF_IRQ_FECTX0 87 /* Ethernet Transmitter */ +#define MCF_IRQ_FECENTC0 88 /* Ethernet Non-Time Critical */ #define MCF_IRQ_QSPI 89 /* Queued Serial Interface */ #define MCF_IRQ_EINT5 90 /* External Interrupt 5 */ #define MCF_IRQ_EINT6 91 /* External Interrupt 6 */ -- cgit v1.2.3 From 308bfc12ddfd6b812a13d784b012e5d04fba9394 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 10:17:42 +1000 Subject: m68knommu: make 527x FEC platform addressing consistent If we make all FEC (ethernet) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 527x FEC addressing so that: . FECs are numbered from 0 up . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m527xsim.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h index 7399968b2ef..59bb776a5e3 100644 --- a/arch/m68k/include/asm/m527xsim.h +++ b/arch/m68k/include/asm/m527xsim.h @@ -38,12 +38,27 @@ #define MCFINT_UART1 14 /* Interrupt number for UART1 */ #define MCFINT_UART2 15 /* Interrupt number for UART2 */ #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ +#define MCFINT_FECRX0 23 /* Interrupt number for FEC0 */ +#define MCFINT_FECTX0 27 /* Interrupt number for FEC0 */ +#define MCFINT_FECENTC0 29 /* Interrupt number for FEC0 */ #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ +#define MCFINT2_VECBASE 128 /* Vector base number 2 */ +#define MCFINT2_FECRX1 23 /* Interrupt number for FEC1 */ +#define MCFINT2_FECTX1 27 /* Interrupt number for FEC1 */ +#define MCFINT2_FECENTC1 29 /* Interrupt number for FEC1 */ + #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) +#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) +#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) +#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) +#define MCF_IRQ_FECRX1 (MCFINT2_VECBASE + MCFINT2_FECRX1) +#define MCF_IRQ_FECTX1 (MCFINT2_VECBASE + MCFINT2_FECTX1) +#define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1) + /* * SDRAM configuration registers. */ -- cgit v1.2.3 From 4f8f9fb8cbb759207ff2437b904c77565180ee5a Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 10:20:02 +1000 Subject: m68knommu: make 528x FEC platform addressing consistent If we make all FEC (ethernet) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 528x FEC addressing so that: . FECs are numbered from 0 up . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m528xsim.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h index a5f0c14b47d..a363c648b97 100644 --- a/arch/m68k/include/asm/m528xsim.h +++ b/arch/m68k/include/asm/m528xsim.h @@ -38,12 +38,19 @@ #define MCFINT_UART1 14 /* Interrupt number for UART1 */ #define MCFINT_UART2 15 /* Interrupt number for UART2 */ #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ +#define MCFINT_FECRX0 23 /* Interrupt number for FEC */ +#define MCFINT_FECTX0 27 /* Interrupt number for FEC */ +#define MCFINT_FECENTC0 29 /* Interrupt number for FEC */ #define MCFINT_PIT1 55 /* Interrupt number for PIT1 */ #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) +#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) +#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) +#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) + /* * SDRAM configuration registers. */ @@ -71,8 +78,8 @@ /* * FEC ethernet module. */ -#define MCFFEC_BASE (MCF_IPSBAR + 0x00001000) -#define MCFFEC_SIZE 0x800 +#define MCFFEC_BASE0 (MCF_IPSBAR + 0x00001000) +#define MCFFEC_SIZE0 0x800 /* * GPIO registers -- cgit v1.2.3 From 504695479ecce2a89955b52c332b0eeec75be8e8 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 10:23:01 +1000 Subject: m68knommu: make 532x FEC platform addressing consistent If we make all FEC (ethernet) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and use a single setup for all. So modify the ColdFire 532x FEC addressing so that: . FECs are numbered from 0 up . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m532xsim.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h index f963d64c94e..f1c4fa80657 100644 --- a/arch/m68k/include/asm/m532xsim.h +++ b/arch/m68k/include/asm/m532xsim.h @@ -24,11 +24,18 @@ #define MCFINT_UART1 27 /* Interrupt number for UART1 */ #define MCFINT_UART2 28 /* Interrupt number for UART2 */ #define MCFINT_QSPI 31 /* Interrupt number for QSPI */ +#define MCFINT_FECRX0 36 /* Interrupt number for FEC */ +#define MCFINT_FECTX0 40 /* Interrupt number for FEC */ +#define MCFINT_FECENTC0 42 /* Interrupt number for FEC */ #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) +#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) +#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) +#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) + #define MCF_WTM_WCR MCF_REG16(0xFC098000) /* @@ -90,6 +97,12 @@ #define MCFUART_BASE1 0xFC064000 /* Base address of UART2 */ #define MCFUART_BASE2 0xFC068000 /* Base address of UART3 */ +/* + * FEC module. + */ +#define MCFFEC_BASE0 0xFC030000 /* Base address of FEC0 */ +#define MCFFEC_SIZE0 0x800 /* Size of FEC0 region */ + /* * Timer module. */ -- cgit v1.2.3 From a4e2e2ac08f73dedeabecb9e1141a05889591b7b Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 12:32:52 +1000 Subject: m68knommu: make 520x QSPI platform addressing consistent If we make all QSPI (SPI protocol) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and code and use a single setup for all. So modify the ColdFire 520x QSPI addressing so that: . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used . move chip select definitions (CS) to appropriate header Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m520xsim.h | 12 ++++++++++++ arch/m68k/include/asm/mcfqspi.h | 2 -- 2 files changed, 12 insertions(+), 2 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h index b83cee2dfda..17f2aab9cf9 100644 --- a/arch/m68k/include/asm/m520xsim.h +++ b/arch/m68k/include/asm/m520xsim.h @@ -61,6 +61,8 @@ #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) +#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) + /* * SDRAM configuration registers. */ @@ -165,6 +167,16 @@ #define MCFFEC_BASE0 0xFC030000 /* Base of FEC ethernet */ #define MCFFEC_SIZE0 0x800 /* Register set size */ +/* + * QSPI module. + */ +#define MCFQSPI_BASE 0xFC05C000 /* Base of QSPI module */ +#define MCFQSPI_SIZE 0x40 /* Register set size */ + +#define MCFQSPI_CS0 46 +#define MCFQSPI_CS1 47 +#define MCFQSPI_CS2 27 + /* * Reset Control Unit. */ diff --git a/arch/m68k/include/asm/mcfqspi.h b/arch/m68k/include/asm/mcfqspi.h index 7fe631972f1..34a531ed2bd 100644 --- a/arch/m68k/include/asm/mcfqspi.h +++ b/arch/m68k/include/asm/mcfqspi.h @@ -25,8 +25,6 @@ #define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340) #elif defined(CONFIG_M5249) #define MCFQSPI_IOBASE (MCF_MBAR + 0x300) -#elif defined(CONFIG_M520x) -#define MCFQSPI_IOBASE 0xFC05C000 #elif defined(CONFIG_M532x) #define MCFQSPI_IOBASE 0xFC058000 #endif -- cgit v1.2.3 From 36d175a4b249235927d75fb681484bd97cc4ea41 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 12:36:38 +1000 Subject: m68knommu: make 523x QSPI platform addressing consistent If we make all QSPI (SPI protocol) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and code and use a single setup for all. So modify the ColdFire 523x QSPI addressing so that: . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used . move chip select definitions (CS) to appropriate header Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m523xsim.h | 13 +++++++++++++ arch/m68k/include/asm/mcfqspi.h | 2 +- 2 files changed, 14 insertions(+), 1 deletion(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h index e1988dd372f..f2d21cef094 100644 --- a/arch/m68k/include/asm/m523xsim.h +++ b/arch/m68k/include/asm/m523xsim.h @@ -51,6 +51,8 @@ #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) +#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) + /* * SDRAM configuration registers. */ @@ -82,6 +84,17 @@ #define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000) #define MCFFEC_SIZE0 0x800 +/* + * QSPI module. + */ +#define MCFQSPI_BASE (MCF_IPSBAR + 0x340) +#define MCFQSPI_SIZE 0x40 + +#define MCFQSPI_CS0 91 +#define MCFQSPI_CS1 92 +#define MCFQSPI_CS2 103 +#define MCFQSPI_CS3 99 + /* * GPIO module. */ diff --git a/arch/m68k/include/asm/mcfqspi.h b/arch/m68k/include/asm/mcfqspi.h index 34a531ed2bd..62148b72825 100644 --- a/arch/m68k/include/asm/mcfqspi.h +++ b/arch/m68k/include/asm/mcfqspi.h @@ -21,7 +21,7 @@ #ifndef mcfqspi_h #define mcfqspi_h -#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) +#if defined(CONFIG_M527x) || defined(CONFIG_M528x) #define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340) #elif defined(CONFIG_M5249) #define MCFQSPI_IOBASE (MCF_MBAR + 0x300) -- cgit v1.2.3 From 2424f549020b6f87ea3b6e89fd7bd26ddf1f717b Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 12:38:40 +1000 Subject: m68knommu: make 5249 QSPI platform addressing consistent If we make all QSPI (SPI protocol) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and code and use a single setup for all. So modify the ColdFire 5249 QSPI addressing so that: . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used . move chip select definitions (CS) to appropriate header Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m5249sim.h | 11 +++++++++++ arch/m68k/include/asm/mcfqspi.h | 2 -- 2 files changed, 11 insertions(+), 2 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h index 3e31508619c..7f0c2c3660f 100644 --- a/arch/m68k/include/asm/m5249sim.h +++ b/arch/m68k/include/asm/m5249sim.h @@ -79,6 +79,17 @@ #define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */ #define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */ +/* + * QSPI module. + */ +#define MCFQSPI_BASE (MCF_MBAR + 0x300) /* Base address QSPI */ +#define MCFQSPI_SIZE 0x40 /* Register set size */ + +#define MCFQSPI_CS0 29 +#define MCFQSPI_CS1 24 +#define MCFQSPI_CS2 21 +#define MCFQSPI_CS3 22 + /* * DMA unit base addresses. */ diff --git a/arch/m68k/include/asm/mcfqspi.h b/arch/m68k/include/asm/mcfqspi.h index 62148b72825..e9a7e1a2c99 100644 --- a/arch/m68k/include/asm/mcfqspi.h +++ b/arch/m68k/include/asm/mcfqspi.h @@ -23,8 +23,6 @@ #if defined(CONFIG_M527x) || defined(CONFIG_M528x) #define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340) -#elif defined(CONFIG_M5249) -#define MCFQSPI_IOBASE (MCF_MBAR + 0x300) #elif defined(CONFIG_M532x) #define MCFQSPI_IOBASE 0xFC058000 #endif -- cgit v1.2.3 From 6c84a60eb98911cb376cf0a340f811401f3b29a4 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 12:40:37 +1000 Subject: m68knommu: make 527x QSPI platform addressing consistent If we make all QSPI (SPI protocol) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and code and use a single setup for all. So modify the ColdFire 527x QSPI addressing so that: . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used . move chip select definitions (CS) to appropriate header Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m527xsim.h | 24 ++++++++++++++++++++++++ arch/m68k/include/asm/mcfqspi.h | 2 +- 2 files changed, 25 insertions(+), 1 deletion(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h index 59bb776a5e3..f1c5b2c8d44 100644 --- a/arch/m68k/include/asm/m527xsim.h +++ b/arch/m68k/include/asm/m527xsim.h @@ -59,6 +59,8 @@ #define MCF_IRQ_FECTX1 (MCFINT2_VECBASE + MCFINT2_FECTX1) #define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1) +#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) + /* * SDRAM configuration registers. */ @@ -103,6 +105,28 @@ #define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800) #define MCFFEC_SIZE1 0x800 +/* + * QSPI module. + */ +#define MCFQSPI_BASE (MCF_IPSBAR + 0x340) +#define MCFQSPI_SIZE 0x40 + +#ifdef CONFIG_M5271 +#define MCFQSPI_CS0 91 +#define MCFQSPI_CS1 92 +#define MCFQSPI_CS2 99 +#define MCFQSPI_CS3 103 +#endif +#ifdef CONFIG_M5275 +#define MCFQSPI_CS0 59 +#define MCFQSPI_CS1 60 +#define MCFQSPI_CS2 61 +#define MCFQSPI_CS3 62 +#endif + +/* + * GPIO module. + */ #ifdef CONFIG_M5271 #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) diff --git a/arch/m68k/include/asm/mcfqspi.h b/arch/m68k/include/asm/mcfqspi.h index e9a7e1a2c99..57fcbc2c0da 100644 --- a/arch/m68k/include/asm/mcfqspi.h +++ b/arch/m68k/include/asm/mcfqspi.h @@ -21,7 +21,7 @@ #ifndef mcfqspi_h #define mcfqspi_h -#if defined(CONFIG_M527x) || defined(CONFIG_M528x) +#if defined(CONFIG_M528x) #define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340) #elif defined(CONFIG_M532x) #define MCFQSPI_IOBASE 0xFC058000 -- cgit v1.2.3 From 3b2039b26619745a736b896caf8df05a2a15df3a Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 12:42:30 +1000 Subject: m68knommu: make 528x QSPI platform addressing consistent If we make all QSPI (SPI protocol) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and code and use a single setup for all. So modify the ColdFire 528x QSPI addressing so that: . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used . move chip select definitions (CS) to appropriate header Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m528xsim.h | 13 +++++++++++++ arch/m68k/include/asm/mcfqspi.h | 4 +--- 2 files changed, 14 insertions(+), 3 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h index a363c648b97..e4581a4a103 100644 --- a/arch/m68k/include/asm/m528xsim.h +++ b/arch/m68k/include/asm/m528xsim.h @@ -51,6 +51,8 @@ #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) +#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) + /* * SDRAM configuration registers. */ @@ -81,6 +83,17 @@ #define MCFFEC_BASE0 (MCF_IPSBAR + 0x00001000) #define MCFFEC_SIZE0 0x800 +/* + * QSPI module. + */ +#define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340) +#define MCFQSPI_SIZE 0x40 + +#define MCFQSPI_CS0 147 +#define MCFQSPI_CS1 148 +#define MCFQSPI_CS2 149 +#define MCFQSPI_CS3 150 + /* * GPIO registers */ diff --git a/arch/m68k/include/asm/mcfqspi.h b/arch/m68k/include/asm/mcfqspi.h index 57fcbc2c0da..f3d9640f788 100644 --- a/arch/m68k/include/asm/mcfqspi.h +++ b/arch/m68k/include/asm/mcfqspi.h @@ -21,9 +21,7 @@ #ifndef mcfqspi_h #define mcfqspi_h -#if defined(CONFIG_M528x) -#define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340) -#elif defined(CONFIG_M532x) +#if defined(CONFIG_M532x) #define MCFQSPI_IOBASE 0xFC058000 #endif #define MCFQSPI_IOSIZE 0x40 -- cgit v1.2.3 From ed8a2798f6cff0dc68ca7d5800279525aa310fd0 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sat, 24 Dec 2011 12:44:45 +1000 Subject: m68knommu: make 532x QSPI platform addressing consistent If we make all QSPI (SPI protocol) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and code and use a single setup for all. So modify the ColdFire 532x QSPI addressing so that: . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used . move chip select definitions (CS) to appropriate header Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m532xsim.h | 12 ++++++++++++ arch/m68k/include/asm/mcfqspi.h | 5 ----- 2 files changed, 12 insertions(+), 5 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h index f1c4fa80657..29b66e21413 100644 --- a/arch/m68k/include/asm/m532xsim.h +++ b/arch/m68k/include/asm/m532xsim.h @@ -36,6 +36,8 @@ #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) +#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) + #define MCF_WTM_WCR MCF_REG16(0xFC098000) /* @@ -103,6 +105,16 @@ #define MCFFEC_BASE0 0xFC030000 /* Base address of FEC0 */ #define MCFFEC_SIZE0 0x800 /* Size of FEC0 region */ +/* + * QSPI module. + */ +#define MCFQSPI_BASE 0xFC058000 /* Base address of QSPI */ +#define MCFQSPI_SIZE 0x40 /* Size of QSPI region */ + +#define MCFQSPI_CS0 84 +#define MCFQSPI_CS1 85 +#define MCFQSPI_CS2 86 + /* * Timer module. */ diff --git a/arch/m68k/include/asm/mcfqspi.h b/arch/m68k/include/asm/mcfqspi.h index f3d9640f788..7b51416ccae 100644 --- a/arch/m68k/include/asm/mcfqspi.h +++ b/arch/m68k/include/asm/mcfqspi.h @@ -21,11 +21,6 @@ #ifndef mcfqspi_h #define mcfqspi_h -#if defined(CONFIG_M532x) -#define MCFQSPI_IOBASE 0xFC058000 -#endif -#define MCFQSPI_IOSIZE 0x40 - /** * struct mcfqspi_cs_control - chip select control for the coldfire qspi driver * @setup: setup the control; allocate gpio's, etc. May be NULL. -- cgit v1.2.3 From 320de7d01c19b6181c592fe8c69b00646ff28962 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sun, 19 Feb 2012 16:27:23 +1000 Subject: m68knommu: make 523x CPU reset register addressing consistent If we make all MCF_RCR (CPU reset register) addressing consistent across all ColdFire CPU family members that use it then we will be able to remove the duplicated copies of the code that use it. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m523xsim.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h index f2d21cef094..075062d4eec 100644 --- a/arch/m68k/include/asm/m523xsim.h +++ b/arch/m68k/include/asm/m523xsim.h @@ -65,8 +65,8 @@ /* * Reset Control Unit (relative to IPSBAR). */ -#define MCF_RCR 0x110000 -#define MCF_RSR 0x110001 +#define MCF_RCR (MCF_IPSBAR + 0x110000) +#define MCF_RSR (MCF_IPSBAR + 0x110001) #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ -- cgit v1.2.3 From 0b2a2139056a05dde934e715739c361d8c01e523 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sun, 19 Feb 2012 16:33:11 +1000 Subject: m68knommu: make 527x CPU reset register addressing consistent If we make all MCF_RCR (CPU reset register) addressing consistent across all ColdFire CPU family members that use it then we will be able to remove the duplicated copies of the code that use it. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m527xsim.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h index f1c5b2c8d44..83db8106f50 100644 --- a/arch/m68k/include/asm/m527xsim.h +++ b/arch/m68k/include/asm/m527xsim.h @@ -328,8 +328,8 @@ /* * Reset Control Unit (relative to IPSBAR). */ -#define MCF_RCR 0x110000 -#define MCF_RSR 0x110001 +#define MCF_RCR (MCF_IPSBAR + 0x110000) +#define MCF_RSR (MCF_IPSBAR + 0x110001) #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ -- cgit v1.2.3 From 645e5333ec9088da08a1db619561de9c93c70634 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Sun, 19 Feb 2012 16:34:58 +1000 Subject: m68knommu: make 528x CPU reset register addressing consistent If we make all MCF_RCR (CPU reset register) addressing consistent across all ColdFire CPU family members that use it then we will be able to remove the duplicated copies of the code that use it. Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m528xsim.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/m68k/include') diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h index e4581a4a103..569476fba18 100644 --- a/arch/m68k/include/asm/m528xsim.h +++ b/arch/m68k/include/asm/m528xsim.h @@ -272,8 +272,8 @@ /* * Reset Control Unit (relative to IPSBAR). */ -#define MCF_RCR 0x110000 -#define MCF_RSR 0x110001 +#define MCF_RCR (MCF_IPSBAR + 0x110000) +#define MCF_RSR (MCF_IPSBAR + 0x110001) #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ -- cgit v1.2.3