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authorkongzizaixian <xweikong@hotmail.com>2015-11-08 17:46:16 +0800
committerkongzizaixian <xweikong@hotmail.com>2015-11-08 17:46:16 +0800
commit4495c689c476d1d9ccb1fa1f33e30ebb30e93be8 (patch)
tree742aa1106bea5c7f6943cd7cc2be87b2a7b2f841
parentbb3e34558f7e2ec280114c585ff5afde63787ad1 (diff)
parentd880643119ede4cf58c7e577d3f292ad61a7e341 (diff)
Merge pull request #10 from kongzizaixian/master
HiKey: boot ubunt system by SD card
-rw-r--r--Documentation/devicetree/bindings/mfd/hi6552.txt75
-rw-r--r--Documentation/devicetree/bindings/regulator/hi6220-mtcmos.txt29
-rw-r--r--arch/arm64/Kconfig6
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts65
-rw-r--r--arch/arm64/boot/dts/hisilicon/hi6220.dtsi649
-rw-r--r--arch/arm64/boot/dts/hisilicon/hikey-gpio.dtsi607
-rw-r--r--arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi684
-rw-r--r--arch/arm64/configs/defconfig15
-rw-r--r--drivers/mfd/Kconfig7
-rw-r--r--drivers/mfd/Makefile1
-rw-r--r--drivers/mfd/hi655x-pmic.c392
-rw-r--r--drivers/mmc/host/dw_mmc-k3.c100
-rw-r--r--drivers/mmc/host/dw_mmc.h2
-rw-r--r--drivers/regulator/Kconfig13
-rw-r--r--drivers/regulator/Makefile3
-rw-r--r--drivers/regulator/hi6220-mtcmos.c268
-rw-r--r--drivers/regulator/hi655x-regulator.c515
-rw-r--r--include/dt-bindings/pinctrl/hisi.h59
-rw-r--r--include/linux/mfd/hi6552_pmic.h49
-rw-r--r--include/linux/mfd/hi655x-pmic.h49
-rw-r--r--include/linux/regulator/hi655x-regulator.h39
21 files changed, 3618 insertions, 9 deletions
diff --git a/Documentation/devicetree/bindings/mfd/hi6552.txt b/Documentation/devicetree/bindings/mfd/hi6552.txt
new file mode 100644
index 000000000000..8cbd46fab79b
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/hi6552.txt
@@ -0,0 +1,75 @@
+* Hisilicon hi6552 Power Management Integrated Circuit (PMIC)
+
+hi6552 consists of a large and varied group of sub-devices:
+
+Device Supply Names Description
+------ ------------ -----------
+hi6552-powerkey : : Powerkey
+hi6552-regulator-pmic : : Regulators
+hi6552-usbvbus : : USB plug detection
+hi6552-pmu-rtc : : RTC
+hi6552-coul : : Coulomb
+
+Required properties:
+- compatible : Should be "hisilicon,hi6552-pmic-driver"
+- reg: Base address of PMIC on hi6220 soc
+- #interrupt-cells: Should be 2, is the local IRQ number for hi6552.
+- interrupt-controller: hi6552 has internal IRQs (has own IRQ domain).
+- pmu_irq_gpio: should be &gpio_pmu_irq_n, is the IRQ gpio of hi6552.
+
+Example:
+ pmic: pmic@F8000000 {
+ compatible = "hisilicon,hi6552-pmic-driver";
+ reg = <0x0 0xF8000000 0x0 0x1000>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ pmu_irq_gpio = <&gpio_pmu_irq_n>;
+ status = "ok";
+ ponkey:ponkey@b1{
+ compatible = "hisilicon,hi6552-powerkey";
+ interrupt-parent = <&pmic>;
+ interrupts = <6 0>, <5 0>, <4 0>;
+ interrupt-names = "down", "up", "hold 1s";
+ };
+ coul: coul@1 {
+ compatible = "hisilicon,hi6552-coul";
+ interrupt-parent = <&pmic>;
+ interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
+ interrupt-names = "cl_int_i", "cl_out_i", "cl_in_i", "vbat_int_i";
+ battery_product_index = <0>;
+ status = "ok";
+ };
+ rtc: rtc@1 {
+ compatible = "hisilicon,hi6552-pmu-rtc";
+ interrupt-parent = <&pmic>;
+ interrupts = <20 0>;
+ interrupt-names = "hi6552_pmu_rtc";
+ board_id = <1>;
+ };
+ usbvbus:usbvbus@b2{
+ compatible = "hisilicon,hi6552-usbvbus";
+ interrupt-parent = <&pmic>;
+ interrupts = <9 0>, <8 0>;
+ interrupt-names = "connect", "disconnect";
+ };
+ ldo2: regulator@a21 {
+ compatible = "hisilicon,hi6552-regulator-pmic";
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3200000>;
+ hisilicon,valid-modes-mask = <0x02>;
+ hisilicon,valid-ops-mask = <0x01d>;
+ hisilicon,initial-mode = <0x02>;
+ hisilicon,regulator-type = <0x01>;
+
+ hisilicon,off-on-delay = <120>;
+ hisilicon,ctrl-regs = <0x029 0x02a 0x02b>;
+ hisilicon,ctrl-data = <0x1 0x1>;
+ hisilicon,vset-regs = <0x072>;
+ hisilicon,vset-data = <0 0x3>;
+ hisilicon,regulator-n-vol = <8>;
+ hisilicon,vset-table = <2500000>,<2600000>,<2700000>,<2800000>,<2900000>,<3000000>,<3100000>,<3200000>;
+ hisilicon,num_consumer_supplies = <1>;
+ hisilicon,consumer-supplies = "sensor_analog";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/regulator/hi6220-mtcmos.txt b/Documentation/devicetree/bindings/regulator/hi6220-mtcmos.txt
new file mode 100644
index 000000000000..720bdfc02fd1
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/hi6220-mtcmos.txt
@@ -0,0 +1,29 @@
+
+Required parent device properties:
+- compatible:
+ - "hisilicon,hi6xxx-mtcmos-driver"
+- hisilicon,mtcmos-steady-us: The time to wait for power steady
+- hisilicon,mtcmos-sc-on-base: address of hi6220 soc control register
+
+Required child device properties:
+- regulator-name: The name of mtcmos
+- hisilicon,ctrl-regs: offset of ctrl-regs
+- hisilicon,ctrl-data: the bit to ctrl the regulator
+
+Example:
+ mtcmos {
+ compatible = "hisilicon,hi6220-mtcmos-driver";
+ hisilicon,mtcmos-steady-us = <10>;
+ hisilicon,mtcmos-sc-on-base = <0xf7800000>;
+
+ mtcmos1: regulator@a1{
+ regulator-name = "G3D_PD_VDD";
+ hisilicon,ctrl-regs = <0x830 0x834 0x83c>;
+ hisilicon,ctrl-data = <1 0x1>;
+ };
+ mtcmos2: regulator@a2{
+ regulator-name = "SOC_MED";
+ hisilicon,ctrl-regs = <0x830 0x834 0x83c>;
+ hisilicon,ctrl-data = <2 0x1>;
+ };
+ };
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index f7c536e58a17..0e25ce9d99c7 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -288,7 +288,13 @@ config ARCH_ZYNQMP
config ARCH_HISI
bool "Hisilicon SoC Family"
+ select PINCTRL
+ select PINCTRL_SINGLE
+ select ARCH_REQUIRE_GPIOLIB
+ select GPIO_PL061
select COMMON_CLK_HI6220
+ select MFD_HI655X_PMIC
+ select REGULATOR_HI655X
help
This enables support for Hisilicon ARMv8 Family of SoCs.
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
index 8876bb6bd541..a84cf3065234 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -10,6 +10,8 @@
/memreserve/ 0x00000000 0x07400000;
/memreserve/ 0x0740f000 0x1000;
+#include "hikey-pinctrl.dtsi"
+#include "hikey-gpio.dtsi"
#include "hi6220.dtsi"
/ {
@@ -22,6 +24,10 @@
aliases {
serial0 = &uart0;
+ serial3 = &uart3;
+ mshc0 = &dwmmc_0;
+ mshc1 = &dwmmc_1;
+ mshc2 = &dwmmc_2;
};
chosen {
@@ -33,4 +39,63 @@
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x40000000>;
};
+
+ smb {
+ uart0: uart@f8015000 { /* console */
+ status = "ok";
+ };
+
+ uart1: uart@f7111000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pmx_func
+ &uart1_cfg_func1 &uart1_cfg_func2>;
+ status = "ok";
+ };
+
+ uart2: uart@f7112000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
+ status = "ok";
+ };
+
+ uart3: uart@f7113000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
+ status = "ok";
+ };
+
+ uart4: uart@f7114000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
+ status = "ok";
+ };
+ };
+
+ dwmmc_0: dwmmc0@f723d000 {
+ bus-width = <0x8>;
+ vmmc-supply = <&ldo19>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
+ &emmc_cfg_func &emmc_rst_cfg_func>;
+ };
+
+ dwmmc_1: dwmmc1@f723e000 {
+ bus-width = <0x4>;
+ disable-wp;
+ cd-gpios = <&gpio1 0 1>;
+ pinctrl-names = "default", "idle";
+ pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
+ pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
+ };
+
+ dwmmc_2: dwmmc2@f723f000 {
+ bus-width = <0x4>;
+ broken-cd;
+ non-removable;
+ /* WL_EN */
+ pinctrl-names = "default", "idle";
+ pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
+ pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
+ };
+
};
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index e70f35313f07..44c6d6cef347 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -133,6 +133,7 @@
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
+ interrupts = <1 9 0xf04>;
};
ao_ctrl: ao_ctrl {
@@ -214,7 +215,655 @@
interrupts = <0 36 4>;
clocks = <&clock_ao HI6220_UART0_PCLK>;
clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ uart3: uart@f7113000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xf7113000 0x0 0x1000>;
+ interrupts = <0 39 4>;
+ reset-controller-reg = <0x330 0x334 0x338 7>;
+ clocks = <&clock_sys HI6220_UART3_PCLK>;
+ clock-names = "apb_pclk";
+ clk-enable-flag = <0>;
+ fifo-deep-size = <16>;
+ status = "ok";
+ };
+
+ uart4: uart@f7114000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xf7114000 0x0 0x1000>;
+ interrupts = <0 40 4>;
+ reset-controller-reg = <0x330 0x334 0x338 8>;
+ clocks = <&clock_sys HI6220_UART4_PCLK>;
+ clock-names = "apb_pclk";
+ clk-enable-flag = <0>;
+ fifo-deep-size = <16>;
+ status = "disabled";
+ };
+
+ dma0: dma@f7370000 {
+ compatible = "hisilicon,k3-dma-1.0";
+ reg = <0x0 0xf7370000 0x0 0x1000>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ dma-requests = <32>;
+ interrupts = <0 84 4>;
+ clocks = <&clock_sys HI6220_EDMAC_ACLK>;
+ dma-no-cci;
+ dma-type = "hi6220_dma";
+ status = "ok";
+ };
+
+ pmx0: pinmux@f7010000 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0xf7010000 0x0 0x27c>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #gpio-range-cells = <3>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <7>;
+ pinctrl-single,gpio-range = <
+ &range 0 1 1
+ &range 2 24 1
+ &range 28 8 1
+ &range 43 21 1
+ &range 74 6 1
+ &range 80 42 0
+ &range 122 1 1
+ &range 126 33 1
+ >;
+ range: gpio-range {
+ #pinctrl-single,gpio-range-cells = <3>;
+ };
+ };
+
+ pmx1: pinmux@f7010800 {
+ compatible = "pinconf-single";
+ reg = <0x0 0xf7010800 0x0 0x28c>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ };
+
+ pmx2: pinmux@f8001800 {
+ compatible = "pinconf-single";
+ reg = <0x0 0xf8001800 0x0 0x78>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ };
+
+ gpio0: gpio@0xf8011000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf8011000 0x0 0x1000>;
+ interrupts = <0 52 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&clock_ao HI6220_CLK_TCXO>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio1: gpio@0xf8012000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf8012000 0x0 0x1000>;
+ interrupts = <0 53 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&clock_ao HI6220_CLK_TCXO>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio2: gpio@0xf8013000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf8013000 0x0 0x1000>;
+ interrupts = <0 54 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&clock_ao HI6220_CLK_TCXO>;
+ clock-names = "apb_pclk";
status = "ok";
};
+
+ gpio3: gpio@0xf8014000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf8014000 0x0 0x1000>;
+ interrupts = <0 55 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 80 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&clock_ao HI6220_CLK_TCXO>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio4: gpio@0xf7020000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf7020000 0x0 0x1000>;
+ interrupts = <0 56 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 88 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&clock_ao HI6220_CLK_TCXO>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio5: gpio@0xf7021000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf7021000 0x0 0x1000>;
+ interrupts = <0 57 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 96 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&clock_ao HI6220_CLK_TCXO>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio6: gpio@0xf7022000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf7022000 0x0 0x1000>;
+ interrupts = <0 58 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 104 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&clock_ao HI6220_CLK_TCXO>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio7: gpio@0xf7023000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf7023000 0x0 0x1000>;
+ interrupts = <0 59 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 112 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&clock_ao HI6220_CLK_TCXO>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio8: gpio@0xf7024000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf7024000 0x0 0x1000>;
+ interrupts = <0 60 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&clock_ao HI6220_CLK_TCXO>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio9: gpio@0xf7025000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf7025000 0x0 0x1000>;
+ interrupts = <0 61 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 8 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&clock_ao HI6220_CLK_TCXO>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio10: gpio@0xf7026000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf7026000 0x0 0x1000>;
+ interrupts = <0 62 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&clock_ao HI6220_CLK_TCXO>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio11: gpio@0xf7027000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf7027000 0x0 0x1000>;
+ interrupts = <0 63 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&clock_ao HI6220_CLK_TCXO>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio12: gpio@0xf7028000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf7028000 0x0 0x1000>;
+ interrupts = <0 64 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&clock_ao HI6220_CLK_TCXO>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio13: gpio@0xf7029000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf7029000 0x0 0x1000>;
+ interrupts = <0 65 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 48 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&clock_ao HI6220_CLK_TCXO>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio14: gpio@0xf702A000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf702A000 0x0 0x1000>;
+ interrupts = <0 66 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 56 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&clock_ao HI6220_CLK_TCXO>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio15: gpio@0xf702B000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf702B000 0x0 0x1000>;
+ interrupts = <0 67 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <
+ &pmx0 0 74 6
+ &pmx0 6 122 1
+ &pmx0 7 126 1
+ >;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&clock_ao HI6220_CLK_TCXO>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio16: gpio@0xf702C000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf702C000 0x0 0x1000>;
+ interrupts = <0 68 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 127 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&clock_ao HI6220_CLK_TCXO>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio17: gpio@0xf702D000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf702D000 0x0 0x1000>;
+ interrupts = <0 69 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 135 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&clock_ao HI6220_CLK_TCXO>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio18: gpio@0xf702E000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf702E000 0x0 0x1000>;
+ interrupts = <0 70 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 143 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&clock_ao HI6220_CLK_TCXO>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+
+ gpio19: gpio@0xf702f000{
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf702f000 0x0 0x1000>;
+ interrupts = <0 71 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 151 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&clock_ao HI6220_CLK_TCXO>;
+ clock-names = "apb_pclk";
+ status = "ok";
+ };
+ };
+
+ pmic: pmic@F8000000 {
+ compatible = "hisilicon,hi6552-pmic-driver";
+ reg = <0x0 0xf8000000 0x0 0x1000>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ pmu_irq_gpio = <&gpio_pmu_irq_n>;
+ status = "ok";
+ ponkey:ponkey@b1{
+ compatible = "hisilicon,hi6552-powerkey";
+ interrupt-parent = <&pmic>;
+ interrupts = <6 0>, <5 0>, <4 0>;
+ interrupt-names = "down", "up", "hold 1s";
+ };
+ coul: coul@1 {
+ compatible = "hisilicon,hi6552-coul";
+ interrupt-parent = <&pmic>;
+ interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
+ interrupt-names = "cl_int_i", "cl_out_i", "cl_in_i", "vbat_int_i";
+ battery_product_index = <0>;
+ status = "ok";
+ };
+ rtc: rtc@1 {
+ compatible = "hisilicon,hi6552-pmu-rtc";
+ interrupt-parent = <&pmic>;
+ interrupts = <20 0>;
+ interrupt-names = "hi6552_pmu_rtc";
+ board_id = <1>;
+ };
+ ldo2: regulator@a21 {
+ compatible = "hisilicon,hi6552-regulator-pmic";
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3200000>;
+ hisilicon,valid-modes-mask = <0x02>;
+ hisilicon,valid-ops-mask = <0x01d>;
+ hisilicon,initial-mode = <0x02>;
+ hisilicon,regulator-type = <0x01>;
+
+ hisilicon,off-on-delay = <120>;
+ hisilicon,ctrl-regs = <0x029 0x02a 0x02b>;
+ hisilicon,ctrl-data = <0x1 0x1>;
+ hisilicon,vset-regs = <0x072>;
+ hisilicon,vset-data = <0 0x3>;
+ hisilicon,regulator-n-vol = <8>;
+ hisilicon,vset-table = <2500000>,<2600000>,<2700000>,<2800000>,<2900000>,<3000000>,<3100000>,<3200000>;
+ hisilicon,num_consumer_supplies = <1>;
+ hisilicon,consumer-supplies = "sensor_analog";
+ };
+ ldo7: regulator@a26 {
+ compatible = "hisilicon,hi6552-regulator-pmic";
+ regulator-name = "ldo7";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ hisilicon,valid-modes-mask = <0x0a>;
+ hisilicon,valid-ops-mask = <0x01d>;
+ hisilicon,initial-mode = <0x02>;
+ hisilicon,regulator-type = <0x01>;
+
+ hisilicon,off-on-delay = <120>;
+ hisilicon,ctrl-regs = <0x029 0x02a 0x02b>;
+ hisilicon,ctrl-data = <0x6 0x1>;
+ hisilicon,vset-regs = <0x078>;
+ hisilicon,vset-data = <0 0x3>;
+ hisilicon,regulator-n-vol = <8>;
+ hisilicon,vset-table = <1800000>,<1850000>,<2850000>,<2900000>,<3000000>,<3100000>,<3200000>,<3300000>;
+ hisilicon,num_consumer_supplies = <1>;
+ hisilicon,consumer-supplies = "sd_card_io";
+ };
+ ldo10: regulator@a29 {
+ compatible = "hisilicon,hi6552-regulator-pmic";
+ regulator-name = "ldo10";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ hisilicon,valid-modes-mask = <0x0a>;
+ hisilicon,valid-ops-mask = <0x01d>;
+ hisilicon,initial-mode = <0x02>;
+ hisilicon,regulator-type = <0x01>;
+
+ hisilicon,off-on-delay = <360>;
+ hisilicon,ctrl-regs = <0x02c 0x02d 0x02e>;
+ hisilicon,ctrl-data = <0x1 0x1>;
+ hisilicon,vset-regs = <0x07b>;
+ hisilicon,vset-data = <0 0x3>;
+ hisilicon,regulator-n-vol = <8>;
+ hisilicon,vset-table = <1800000>,<1850000>,<1900000>,<2750000>,<2800000>,<2850000>,<2900000>,<3000000>;
+ hisilicon,num_consumer_supplies = <1>;
+ hisilicon,consumer-supplies = "sd_card";
+ };
+ ldo13: regulator@a32 {
+ compatible = "hisilicon,hi6552-regulator-pmic";
+ regulator-name = "ldo13";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <1950000>;
+ hisilicon,valid-modes-mask = <0x0a>;
+ hisilicon,valid-ops-mask = <0x01d>;
+ hisilicon,initial-mode = <0x02>;
+ hisilicon,regulator-type = <0x01>;
+
+ hisilicon,off-on-delay = <120>;
+ hisilicon,ctrl-regs = <0x02c 0x02d 0x02e>;
+ hisilicon,ctrl-data = <0x4 0x1>;
+ hisilicon,vset-regs = <0x07e>;
+ hisilicon,vset-data = <0 0x3>;
+ hisilicon,regulator-n-vol = <8>;
+ hisilicon,vset-table = <1600000>,<1650000>,<1700000>,<1750000>,<1800000>,<1850000>,<1900000>,<1950000>;
+ hisilicon,num_consumer_supplies = <3>;
+ hisilicon,consumer-supplies = "scamera_core","mcamera_io","scamera_io";
+ };
+ ldo14: regulator@a33 {
+ compatible = "hisilicon,hi6552-regulator-pmic";
+ regulator-name = "ldo14";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3200000>;
+ hisilicon,valid-modes-mask = <0x02>;
+ hisilicon,valid-ops-mask = <0x01d>;
+ hisilicon,initial-mode = <0x02>;
+ hisilicon,regulator-type = <0x01>;
+
+ hisilicon,off-on-delay = <120>;
+ hisilicon,ctrl-regs = <0x02c 0x02d 0x02e>;
+ hisilicon,ctrl-data = <0x5 0x1>;
+ hisilicon,vset-regs = <0x07f>;
+ hisilicon,vset-data = <0 0x3>;
+ hisilicon,regulator-n-vol = <8>;
+ hisilicon,vset-table = <2500000>,<2600000>,<2700000>,<2800000>,<2900000>,<3000000>,<3100000>,<3200000>;
+ hisilicon,num_consumer_supplies = <3>;
+ hisilicon,consumer-supplies = "scamera_avdd","mcamera_avdd","mcamera_vcm";
+ };
+ ldo15: regulator@a34 {
+ compatible = "hisilicon,hi6552-regulator-pmic";
+ regulator-name = "ldo15";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ hisilicon,valid-modes-mask = <0x0a>;
+ hisilicon,valid-ops-mask = <0x01d>;
+ hisilicon,initial-mode = <0x02>;
+ hisilicon,regulator-type = <0x01>;
+
+ hisilicon,off-on-delay = <120>;
+ hisilicon,ctrl-regs = <0x02c 0x02d 0x02e>;
+ hisilicon,ctrl-data = <0x6 0x1>;
+ hisilicon,vset-regs = <0x080>;
+ hisilicon,vset-data = <0 0x3>;
+ hisilicon,regulator-n-vol = <8>;
+ hisilicon,vset-table = <1600000>,<1650000>,<1700000>,<1750000>,<1800000>,<1850000>,<1900000>,<1950000>;
+ hisilicon,num_consumer_supplies = <1>;
+ hisilicon,consumer-supplies = "codec_analog";
+ };
+ ldo17: regulator@a36 {
+ compatible = "hisilicon,hi6552-regulator-pmic";
+ regulator-name = "ldo17";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3200000>;
+ hisilicon,valid-modes-mask = <0x02>;
+ hisilicon,valid-ops-mask = <0x01d>;
+ hisilicon,initial-mode = <0x02>;
+ hisilicon,regulator-type = <0x01>;
+
+ hisilicon,off-on-delay = <120>;
+ hisilicon,ctrl-regs = <0x02f 0x030 0x031>;
+ hisilicon,ctrl-data = <0x0 0x1>;
+ hisilicon,vset-regs = <0x082>;
+ hisilicon,vset-data = <0 0x3>;
+ hisilicon,regulator-n-vol = <8>;
+ hisilicon,vset-table = <2500000>,<2600000>,<2700000>,<2800000>,<2900000>,<3000000>,<3100000>,<3200000>;
+ hisilicon,num_consumer_supplies = <1>;
+ hisilicon,consumer-supplies = "vibrator";
+ };
+ ldo19: regulator@a38 {
+ compatible = "hisilicon,hi6552-regulator-pmic";
+ regulator-name = "ldo19";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3000000>;
+ hisilicon,valid-modes-mask = <0x0a>;
+ hisilicon,valid-ops-mask = <0x01d>;
+ hisilicon,initial-mode = <0x02>;
+ hisilicon,regulator-type = <0x01>;
+
+ hisilicon,off-on-delay = <360>;
+ hisilicon,ctrl-regs = <0x02f 0x030 0x031>;
+ hisilicon,ctrl-data = <0x2 0x1>;
+ hisilicon,vset-regs = <0x084>;
+ hisilicon,vset-data = <0 0x3>;
+ hisilicon,regulator-n-vol = <8>;
+ hisilicon,vset-table = <1800000>,<1850000>,<1900000>,<2750000>,<2800000>,<2850000>,<2900000>,<3000000>;
+ hisilicon,num_consumer_supplies = <1>;
+ hisilicon,consumer-supplies = "emmc_vddm";
+ };
+ ldo21: regulator@a40 {
+ compatible = "hisilicon,hi6552-regulator-pmic";
+ regulator-name = "ldo21";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-always-on;
+ hisilicon,valid-modes-mask = <0x02>;
+ hisilicon,valid-ops-mask = <0x01d>;
+ hisilicon,initial-mode = <0x02>;
+ hisilicon,regulator-type = <0x01>;
+
+ hisilicon,off-on-delay = <120>;
+ hisilicon,ctrl-regs = <0x02f 0x030 0x031>;
+ hisilicon,ctrl-data = <0x4 0x1>;
+ hisilicon,vset-regs = <0x086>;
+ hisilicon,vset-data = <0 0x3>;
+ hisilicon,regulator-n-vol = <8>;
+ hisilicon,vset-table = <1650000>,<1700000>,<1750000>,<1800000>,<1850000>,<1900000>,<1950000>,<2000000>;
+ };
+ ldo22: regulator@a41 {
+ compatible = "hisilicon,hi6552-regulator-pmic";
+ regulator-name = "ldo22";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
+ regulator-always-on;
+ hisilicon,valid-modes-mask = <0x02>;
+ hisilicon,valid-ops-mask = <0x01d>;
+ hisilicon,initial-mode = <0x02>;
+ hisilicon,regulator-type = <0x01>;
+
+ hisilicon,off-on-delay = <120>;
+ hisilicon,ctrl-regs = <0x02f 0x030 0x031>;
+ hisilicon,ctrl-data = <0x5 0x1>;
+ hisilicon,vset-regs = <0x087>;
+ hisilicon,vset-data = <0 0x3>;
+ hisilicon,regulator-n-vol = <8>;
+ hisilicon,vset-table = <900000>,<1000000>,<1050000>,<1100000>,<1150000>,<1175000>,<1185000>,<1200000>;
+ hisilicon,num_consumer_supplies = <1>;
+ hisilicon,consumer-supplies = "mcamera_core";
+ };
+ };
+
+ dwmmc_0: dwmmc0@f723d000 {
+ compatible = "hisilicon,hi6220-dw-mshc";
+ num-slots = <0x1>;
+ board-mmc-bus-clk = <0x0>;
+ cap-mmc-highspeed;
+ non-removable;
+ reg = <0x0 0xf723d000 0x0 0x1000>;
+ interrupts = <0x0 0x48 0x4>;
+ clocks = <&clock_sys HI6220_MMC0_CIUCLK>, <&clock_sys HI6220_MMC0_CLK>;
+ clock-names = "ciu", "biu";
+ vmmc-supply = <&ldo19>;
+ };
+
+ dwmmc_1: dwmmc1@f723e000 {
+ compatible = "hisilicon,hi6220-dw-mshc";
+ num-slots = <0x1>;
+ board-mmc-bus-clk = <0x0>;
+ card-detect-delay = <200>;
+ hisilicon,peripheral-syscon = <&ao_ctrl>;
+ cap-sd-highspeed;
+ reg = <0x0 0xf723e000 0x0 0x1000>;
+ interrupts = <0x0 0x49 0x4>;
+ clocks = <&clock_sys HI6220_MMC1_CIUCLK>, <&clock_sys HI6220_MMC1_CLK>;
+ clock-names = "ciu", "biu";
+ vqmmc-supply = <&ldo7>;
+ vmmc-supply = <&ldo10>;
+ };
+
+ dwmmc_2: dwmmc2@f723f000 {
+ compatible = "hisilicon,hisi-dw-mshc";
+ num-slots = <0x1>;
+ board-mmc-bus-clk = <0x0>;
+ reg = <0x0 0xf723f000 0x0 0x1000>;
+ interrupts = <0x0 0x4a 0x4>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ clocks = <&clock_sys HI6220_MMC2_CIUCLK>, <&clock_sys HI6220_MMC2_CLK>;
+ clock-names = "ciu", "biu";
+ };
+
+ mtcmos {
+ compatible = "hisilicon,hi6220-mtcmos-driver";
+ hisilicon,mtcmos-steady-us = <10>;
+ hisilicon,mtcmos-sc-on-base = <0xf7800000>;
+ hisilicon,mtcmos-acpu-on-base = <0xf65a0000>;
+
+ mtcmos1: regulator@a1{
+ regulator-name = "G3D_PD_VDD";
+ hisilicon,ctrl-regs = <0x830 0x834 0x83c>;
+ hisilicon,ctrl-data = <1 0x1>;
+ };
+ mtcmos2: regulator@a2{
+ regulator-name = "SOC_MED";
+ hisilicon,ctrl-regs = <0x830 0x834 0x83c>;
+ hisilicon,ctrl-data = <2 0x1>;
+ };
};
};
diff --git a/arch/arm64/boot/dts/hisilicon/hikey-gpio.dtsi b/arch/arm64/boot/dts/hisilicon/hikey-gpio.dtsi
new file mode 100644
index 000000000000..8be51ca93f96
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hikey-gpio.dtsi
@@ -0,0 +1,607 @@
+/ {
+ gpio_rstout_n:gpio_rstout_n {
+ gpios;
+ };
+ gpio_pmu_peri_en:gpio_pmu_peri_en {
+ gpios;
+ };
+ gpio_sysclk0_en:gpio_sysclk0_en {
+ gpios;
+ };
+ gpio_jtag_tdo:gpio_jtag_tdo {
+ gpios;
+ };
+ /* LCB: PWR_HOLD_GPIO0_0 */
+ gpio_pwr_hold:gpio_pwr_hold {
+ gpios = <&gpio0 0 0>;
+ };
+ /* LCB: DSI_SEL_GPIO0_1 */
+ gpio_dsi_sel:gpio_dsi_sel {
+ gpios = <&gpio0 1 0>;
+ };
+ /* LCB: USB_HUB_RESET_N_GPIO0_2 */
+ gpio_usb_hub_reset_n:gpio_usb_hub_reset_n {
+ gpios = <&gpio0 2 0>;
+ };
+ /* LCB: USB_SEL_GPIO0_3 */
+ gpio_usb_sel:gpio_usb_sel {
+ gpios = <&gpio0 3 0>;
+ };
+ /* LCB: HDMI_PD_GPIO0_4 */
+ gpio_hdmi_pd:gpio_hdmi_pd {
+ gpios = <&gpio0 4 0>;
+ };
+ /* LCB: WL_REG_ON_GPIO0_5 */
+ gpio_wl_en:gpio_wl_en {
+ gpios = <&gpio0 5 0>;
+ };
+ /* LCB: PWRON_DET_GPIO0_6 */
+ gpio_pwron_det:gpio_pwron_det {
+ gpios = <&gpio0 6 0>;
+ };
+ /* LCB: 5V_HUB_EN_GPIO0_7 */
+ gpio_usb_dev_det:gpio_usb_dev_det {
+ gpios = <&gpio0 7 0>;
+ };
+ /* LCB: SD_DET_GPIO1_0 */
+ gpio_sd_det:gpio_sd_det {
+ gpios = <&gpio1 0 0>;
+ };
+ /* LCB: HDMI_INT_GPIO1_1 */
+ gpio_hdmi_int:gpio_hdmi_int {
+ gpios = <&gpio1 1 0>;
+ };
+ /* LCB: PMU_IRQ_N_GPIO1_2 */
+ gpio_pmu_irq_n:gpio_pmu_irq_n {
+ gpios = <&gpio1 2 0>;
+ };
+ /* LCB: WL_HOST_WAKE_GPIO1_3 */
+ gpio_wl_host_wake:gpio_wl_host_wake {
+ gpios = <&gpio1 3 0>;
+ };
+ gpio_nfc_int:gpio_nfc_int {
+ gpios = <&gpio1 4 0>;
+ };
+ gpio_unused_001:gpio_unused_001 {
+ gpios = <&gpio1 5 0>;
+ };
+ /* LCB: BT_REG_ON_GPIO1_7 */
+ gpio_bt_reg_on:gpio_bt_reg_on {
+ gpios = <&gpio1 7 0>;
+ };
+ /* LCB: GPIO2_0, J2 */
+ gpio_j2_2_0:gpio_j2_2_0 {
+ gpios = <&gpio2 0 0>;
+ };
+ /* LCB: GPIO2_1, J2 */
+ gpio_j2_2_1:gpio_j2_2_1 {
+ gpios = <&gpio2 1 0>;
+ };
+ /* LCB: GPIO2_2, J2 */
+ gpio_j2_2_2:gpio_j2_2_2 {
+ gpios = <&gpio2 2 0>;
+ };
+ /* LCB: GPIO2_3, J2 */
+ gpio_j2_2_3:gpio_j2_2_3 {
+ gpios = <&gpio2 3 0>;
+ };
+ /* LCB: GPIO2_4, J2 */
+ gpio_j2_2_4:gpio_j2_2_4 {
+ gpios = <&gpio2 4 0>;
+ };
+ /* LCB: USB_ID_DET_GPIO2_5 */
+ gpio_usb_id_det:gpio_usb_id_det {
+ gpios = <&gpio2 5 0>;
+ };
+ /* LCB: USB_VBUS_DET_GPIO2_6 */
+ gpio_vbus_det:gpio_vbus_det {
+ gpios = <&gpio2 6 0>;
+ };
+ /* LCB: GPIO2_7, J2 */
+ gpio_j2_2_7:gpio_j2_2_7 {
+ gpios = <&gpio2 7 0>;
+ };
+ gpio_rf_reset0:gpio_rf_reset0 {
+ gpios;
+ };
+ gpio_rf_reset1:gpio_rf_reset1 {
+ gpios;
+ };
+ gpio_boot_sel:gpio_boot_sel {
+ gpios = <&gpio10 0 0>;
+ };
+ gpio_pmu_ssi:gpio_pmu_ssi {
+ gpios;
+ };
+ gpio_gps_ref_clk:gpio_gps_ref_clk {
+ gpios = <&gpio8 2 0>;
+ };
+ gpio_sd_clk:gpio_sd_clk {
+ gpios = <&gpio8 3 0>;
+ };
+ gpio_sd_cmd:gpio_sd_cmd {
+ gpios = <&gpio8 4 0>;
+ };
+ gpio_sd_data0:gpio_sd_data0 {
+ gpios = <&gpio8 5 0>;
+ };
+ gpio_sd_data1:gpio_sd_data1 {
+ gpios = <&gpio8 6 0>;
+ };
+ gpio_sd_data2:gpio_sd_data2 {
+ gpios = <&gpio8 7 0>;
+ };
+ gpio_sd_data3:gpio_sd_data3 {
+ gpios = <&gpio9 0 0>;
+ };
+ gpio_unused_002:gpio_unused_002 {
+ gpios;
+ };
+ gpio_mcam_pwdn:gpio_mcam_pwdn {
+ gpios = <&gpio9 1 0>;
+ };
+ gpio_vcm_pwdn:gpio_vcm_pwdn {
+ gpios = <&gpio9 2 0>;
+ };
+ gpio_scam_pwdn:gpio_scam_pwdn {
+ gpios = <&gpio9 3 0>;
+ };
+ gpio_cam_id0:gpio_cam_id0 {
+ gpios = <&gpio9 4 0>;
+ };
+ gpio_cam_id1:gpio_cam_id1 {
+ gpios = <&gpio9 5 0>;
+ };
+ gpio_flash_strobe:gpio_flash_strobe {
+ gpios = <&gpio9 6 0>;
+ };
+ gpio_mcam_mclk:gpio_mcam_mclk {
+ gpios = <&gpio9 7 0>;
+ };
+ gpio_scam_mclk:gpio_scam_mclk {
+ gpios = <&gpio10 1 0>;
+ };
+ gpio_cam_reset0:gpio_cam_reset0 {
+ gpios = <&gpio10 2 0>;
+ };
+ gpio_cam_reset1:gpio_cam_reset1 {
+ gpios = <&gpio10 3 0>;
+ };
+ gpio_tp_rst_n:gpio_tp_rst_n {
+ gpios = <&gpio10 4 0>;
+ };
+ gpio_unused_003:gpio_unused_003 {
+ gpios = <&gpio10 5 0>;
+ };
+ gpio_isp_sda0:gpio_isp_sda0 {
+ gpios = <&gpio10 6 0>;
+ };
+ gpio_isp_scl0:gpio_isp_scl0 {
+ gpios = <&gpio10 7 0>;
+ };
+ gpio_isp_sda1:gpio_isp_sda1 {
+ gpios = <&gpio11 0 0>;
+ };
+ gpio_isp_scl1:gpio_isp_scl1 {
+ gpios = <&gpio11 1 0>;
+ };
+ gpio_mdm_rst:gpio_mdm_rst {
+ gpios = <&gpio11 2 0>;
+ };
+ gpio_hkadc_ssi:gpio_hkadc_ssi {
+ gpios;
+ };
+ gpio_codec_clk:gpio_codec_clk {
+ gpios;
+ };
+ gpio_ap_wakeup_mdm:gpio_ap_wakeup_mdm {
+ gpios = <&gpio11 3 0>;
+ };
+ gpio_codec_sync:gpio_codec_sync {
+ gpios = <&gpio11 4 0>;
+ };
+ gpio_codec_datain:gpio_codec_datain {
+ gpios = <&gpio11 5 0>;
+ };
+ gpio_codec_dataout:gpio_codec_dataout {
+ gpios = <&gpio11 6 0>;
+ };
+ gpio_fm_xclk:gpio_fm_xclk {
+ gpios = <&gpio11 7 0>;
+ };
+ gpio_fm_xfs:gpio_fm_xfs {
+ gpios = <&gpio12 0 0>;
+ };
+ gpio_fm_di:gpio_fm_di {
+ gpios = <&gpio12 1 0>;
+ };
+ gpio_fm_do:gpio_fm_do {
+ gpios = <&gpio12 2 0>;
+ };
+ gpio_bt_xclk:gpio_bt_xclk {
+ gpios;
+ };
+ gpio_bt_xfs:gpio_bt_xfs {
+ gpios;
+ };
+ gpio_bt_di:gpio_bt_di {
+ gpios;
+ };
+ gpio_bt_do:gpio_bt_do {
+ gpios;
+ };
+ gpio_usim0_clk:gpio_usim0_clk {
+ gpios;
+ };
+ gpio_usim0_data:gpio_usim0_data {
+ gpios;
+ };
+ gpio_usim0_rst:gpio_usim0_rst {
+ gpios;
+ };
+ gpio_usim1_clk:gpio_usim1_clk {
+ gpios = <&gpio12 3 0>;
+ };
+ gpio_usim1_data:gpio_usim1_data {
+ gpios = <&gpio12 4 0>;
+ };
+ gpio_usim1_rst:gpio_usim1_rst {
+ gpios = <&gpio12 5 0>;
+ };
+ gpio_unused_004:gpio_unused_004 {
+ gpios = <&gpio12 6 0>;
+ };
+ gpio_unused_005:gpio_unused_005 {
+ gpios = <&gpio12 7 0>;
+ };
+ gpio_uart0_rxd:gpio_uart0_rxd {
+ gpios = <&gpio13 0 0>;
+ };
+ gpio_uart0_txd:gpio_uart0_txd {
+ gpios = <&gpio13 1 0>;
+ };
+ gpio_bt_uart_cts_n:gpio_bt_uart_cts_n {
+ gpios = <&gpio13 2 0>;
+ };
+ gpio_bt_uart_rts_n:gpio_bt_uart_rts_n {
+ gpios = <&gpio13 3 0>;
+ };
+ gpio_bt_uart_rxd:gpio_bt_uart_rxd {
+ gpios = <&gpio13 4 0>;
+ };
+ gpio_bt_uart_txd:gpio_bt_uart_txd {
+ gpios = <&gpio13 5 0>;
+ };
+ gpio_gps_uart_cts_n:gpio_gps_uart_cts_n {
+ gpios = <&gpio13 6 0>;
+ };
+ gpio_gps_uart_rts_n:gpio_gps_uart_rts_n {
+ gpios = <&gpio13 7 0>;
+ };
+ gpio_gps_uart_rxd:gpio_gps_uart_rxd {
+ gpios = <&gpio14 0 0>;
+ };
+ gpio_gps_uart_txd:gpio_gps_uart_txd {
+ gpios = <&gpio14 1 0>;
+ };
+ gpio_i2c0_scl:gpio_i2c0_scl {
+ gpios = <&gpio14 2 0>;
+ };
+ gpio_i2c0_sda:gpio_i2c0_sda {
+ gpios = <&gpio14 3 0>;
+ };
+ gpio_i2c1_scl:gpio_i2c1_scl {
+ gpios = <&gpio14 4 0>;
+ };
+ gpio_i2c1_sda:gpio_i2c1_sda {
+ gpios = <&gpio14 5 0>;
+ };
+ gpio_i2c2_scl:gpio_i2c2_scl {
+ gpios = <&gpio14 6 0>;
+ };
+ gpio_i2c2_sda:gpio_i2c2_sda {
+ gpios = <&gpio14 7 0>;
+ };
+ gpio_emmc_clk:gpio_emmc_clk {
+ gpios;
+ };
+ gpio_emmc_cmd:gpio_emmc_cmd {
+ gpios;
+ };
+ gpio_emmc_data0:gpio_emmc_data0 {
+ gpios;
+ };
+ gpio_emmc_data1:gpio_emmc_data1 {
+ gpios;
+ };
+ gpio_emmc_data2:gpio_emmc_data2 {
+ gpios;
+ };
+ gpio_emmc_data3:gpio_emmc_data3 {
+ gpios;
+ };
+ gpio_emmc_data4:gpio_emmc_data4 {
+ gpios;
+ };
+ gpio_emmc_data5:gpio_emmc_data5 {
+ gpios;
+ };
+ gpio_emmc_data6:gpio_emmc_data6 {
+ gpios;
+ };
+ gpio_emmc_data7:gpio_emmc_data7 {
+ gpios;
+ };
+ gpio_emmc_rst_n:gpio_emmc_rst_n {
+ gpios;
+ };
+ gpio_unused_006:gpio_unused_006 {
+ gpios;
+ };
+ gpio_sdio_clk:gpio_sdio_clk {
+ gpios = <&gpio15 0 0>;
+ };
+ gpio_sdio_cmd:gpio_sdio_cmd {
+ gpios = <&gpio15 1 0>;
+ };
+ gpio_sdio_data0:gpio_sdio_data0 {
+ gpios = <&gpio15 2 0>;
+ };
+ gpio_sdio_data1:gpio_sdio_data1 {
+ gpios = <&gpio15 3 0>;
+ };
+ gpio_sdio_data2:gpio_sdio_data2 {
+ gpios = <&gpio15 4 0>;
+ };
+ gpio_sdio_data3:gpio_sdio_data3 {
+ gpios = <&gpio15 5 0>;
+ };
+ gpio_unused_007:gpio_unused_007 {
+ gpios;
+ };
+ /* LCB: GPIO3_0, on J15, as general purpose input */
+ gpio_j15_3_0:gpio_j15_3_0 {
+ gpios = <&gpio3 0 0>;
+ };
+ gpio_jtag_sel0:gpio_jtag_sel0 {
+ gpios = <&gpio3 1 0>;
+ };
+ gpio_jtag_sel1:gpio_jtag_sel1 {
+ gpios = <&gpio3 2 0>;
+ };
+ gpio_lcd_rst_n:gpio_lcd_rst_n {
+ gpios = <&gpio3 3 0>;
+ };
+ gpio_aux_ssi0:gpio_aux_ssi0 {
+ gpios = <&gpio3 4 0>;
+ };
+ /* LCB: WLAN_ACTIVE_GPIO3_5, connects to led, as general purpose */
+ gpio_wlan_active_led:gpio_wlan_active_led {
+ gpios = <&gpio3 5 0>;
+ };
+ gpio_unused_008:gpio_unused_008 {
+ gpios = <&gpio3 6 0>;
+ };
+ gpio_ap_wakeup_bt:gpio_ap_wakeup_bt {
+ gpios = <&gpio3 7 0>;
+ };
+ /* LCB: USER_LED1_GPIO4_0 */
+ gpio_user_led_1:gpio_user_led_1 {
+ gpios = <&gpio4 0 0>;
+ };
+ /* LCB: USER_LED1_GPIO4_1 */
+ gpio_user_led_2:gpio_user_led_2 {
+ gpios = <&gpio4 1 0>;
+ };
+ /* LCB: USER_LED1_GPIO4_2 */
+ gpio_user_led_3:gpio_user_led_3 {
+ gpios = <&gpio4 2 0>;
+ };
+ /* LCB: USER_LED1_GPIO4_3 */
+ gpio_user_led_4:gpio_user_led_4 {
+ gpios = <&gpio4 3 0>;
+ };
+ gpio_i2c3_scl:gpio_i2c3_scl {
+ gpios = <&gpio4 4 0>;
+ };
+ gpio_i2c3_sda:gpio_i2c3_sda {
+ gpios = <&gpio4 5 0>;
+ };
+ gpio_wlan_bt_priority:gpio_wlan_bt_priority {
+ gpios = <&gpio4 6 0>;
+ };
+ /* LCB: BT_ACTIVE_GPIO4_7, connects to led, as general purpose */
+ gpio_bt_active_led:gpio_bt_active_led {
+ gpios = <&gpio4 7 0>;
+ };
+ gpio_uart3_cts_n:gpio_uart3_cts_n {
+ gpios = <&gpio5 0 0>;
+ };
+ gpio_uart3_rts_n:gpio_uart3_rts_n {
+ gpios = <&gpio5 1 0>;
+ };
+ gpio_uart3_rxd:gpio_uart3_rxd {
+ gpios = <&gpio5 2 0>;
+ };
+ gpio_uart3_txd:gpio_uart3_txd {
+ gpios = <&gpio5 3 0>;
+ };
+ gpio_aux_ssi1:gpio_aux_ssi1 {
+ gpios = <&gpio5 4 0>;
+ };
+ gpio_unused_009:gpio_unused_009 {
+ gpios = <&gpio5 5 0>;
+ };
+ gpio_modem_pcm_xclk:gpio_modem_pcm_xclk {
+ gpios = <&gpio5 6 0>;
+ };
+ gpio_modem_pcm_xfs:gpio_modem_pcm_xfs {
+ gpios = <&gpio5 7 0>;
+ };
+ gpio_spi0_di:gpio_spi0_di {
+ gpios = <&gpio6 0 0>;
+ };
+ gpio_spi0_do:gpio_spi0_do {
+ gpios = <&gpio6 1 0>;
+ };
+ gpio_spi0_cs_n:gpio_spi0_cs_n {
+ gpios = <&gpio6 2 0>;
+ };
+ gpio_spi0_clk:gpio_spi0_clk {
+ gpios = <&gpio6 3 0>;
+ };
+ gpio_lte_tx_active:gpio_lte_tx_active {
+ gpios = <&gpio6 4 0>;
+ };
+ gpio_lte_rx_active:gpio_lte_rx_active {
+ gpios = <&gpio6 5 0>;
+ };
+ gpio_lcd_id0:gpio_lcd_id0 {
+ gpios = <&gpio6 6 0>;
+ };
+ /* LCB: GPIO6_7_DSI_TE0 */
+ gpio_dsi_te0:gpio_dsi_te0 {
+ gpios = <&gpio6 7 0>;
+ };
+ gpio_lcd_id1:gpio_lcd_id1 {
+ gpios = <&gpio7 0 0>;
+ };
+ gpio_volume1_n:gpio_volume1_n {
+ gpios = <&gpio7 1 0>;
+ };
+ gpio_uart5_rxd:gpio_uart5_rxd {
+ gpios = <&gpio7 2 0>;
+ };
+ gpio_uart5_txd:gpio_uart5_txd {
+ gpios = <&gpio7 3 0>;
+ };
+ gpio_modem_pcm_di:gpio_modem_pcm_di {
+ gpios = <&gpio7 4 0>;
+ };
+ gpio_modem_pcm_do:gpio_modem_pcm_do {
+ gpios = <&gpio7 5 0>;
+ };
+ gpio_uart4_rxd:gpio_uart4_rxd {
+ gpios = <&gpio7 6 0>;
+ };
+ gpio_uart4_txd:gpio_uart4_txd {
+ gpios = <&gpio7 7 0>;
+ };
+ gpio_ap_wakeup_wl:gpio_ap_wakeup_wl {
+ gpios = <&gpio8 0 0>;
+ };
+ gpio_mdm_pwr_en:gpio_mdm_pwr_en {
+ gpios = <&gpio8 1 0>;
+ };
+ gpio_tcxo0_afc:gpio_tcxo0_afc {
+ gpios = <&gpio15 6 0>;
+ };
+ gpio_rf_ssi0:gpio_rf_ssi0 {
+ gpios;
+ };
+ gpio_rf_tcvr_on0:gpio_rf_tcvr_on0 {
+ gpios;
+ };
+ gpio_rf_mipi_clk0:gpio_rf_mipi_clk0 {
+ gpios;
+ };
+ gpio_rf_mipi_data0:gpio_rf_mipi_data0 {
+ gpios = <&gpio15 7 0>;
+ };
+ gpio_flash_mask:gpio_flash_mask {
+ gpios = <&gpio16 0 0>;
+ };
+ gpio_gps_blanking:gpio_gps_blanking {
+ gpios = <&gpio16 1 0>;
+ };
+ gpio_rf_gpio_2:gpio_rf_gpio_2 {
+ gpios = <&gpio16 2 0>;
+ };
+ gpio_rf_gpio_3:gpio_rf_gpio_3 {
+ gpios = <&gpio16 3 0>;
+ };
+ gpio_rf_gpio_4:gpio_rf_gpio_4 {
+ gpios = <&gpio16 4 0>;
+ };
+ gpio_rf_gpio_5:gpio_rf_gpio_5 {
+ gpios = <&gpio16 5 0>;
+ };
+ gpio_rf_gpio_6:gpio_rf_gpio_6 {
+ gpios = <&gpio16 6 0>;
+ };
+ gpio_rf_gpio_7:gpio_rf_gpio_7 {
+ gpios = <&gpio16 7 0>;
+ };
+ gpio_rf_gpio_8:gpio_rf_gpio_8 {
+ gpios = <&gpio17 0 0>;
+ };
+ gpio_rf_gpio_9:gpio_rf_gpio_9 {
+ gpios = <&gpio17 1 0>;
+ };
+ gpio_rf_gpio_10:gpio_rf_gpio_10 {
+ gpios = <&gpio17 2 0>;
+ };
+ gpio_rf_gpio_11:gpio_rf_gpio_11 {
+ gpios = <&gpio17 3 0>;
+ };
+ gpio_rf_gpio_12:gpio_rf_gpio_12 {
+ gpios = <&gpio17 4 0>;
+ };
+ gpio_rf_gpio_13:gpio_rf_gpio_13 {
+ gpios = <&gpio17 5 0>;
+ };
+ gpio_rf_gpio_14:gpio_rf_gpio_14 {
+ gpios = <&gpio17 6 0>;
+ };
+ gpio_rf_gpio_15:gpio_rf_gpio_15 {
+ gpios = <&gpio17 7 0>;
+ };
+ gpio_rf_gpio_16:gpio_rf_gpio_16 {
+ gpios = <&gpio18 0 0>;
+ };
+ gpio_rf_gpio_17:gpio_rf_gpio_17 {
+ gpios = <&gpio18 1 0>;
+ };
+ gpio_rf_gpio_18:gpio_rf_gpio_18 {
+ gpios = <&gpio18 2 0>;
+ };
+ gpio_rf_gpio_19:gpio_rf_gpio_19 {
+ gpios = <&gpio18 3 0>;
+ };
+ gpio_rf_gpio_20:gpio_rf_gpio_20 {
+ gpios = <&gpio18 4 0>;
+ };
+ gpio_rf_gpio_21:gpio_rf_gpio_21 {
+ gpios = <&gpio18 5 0>;
+ };
+ gpio_rf_gpio_22:gpio_rf_gpio_22 {
+ gpios = <&gpio18 6 0>;
+ };
+ gpio_rf_gpio_23:gpio_rf_gpio_23 {
+ gpios = <&gpio18 7 0>;
+ };
+ gpio_rf_gpio_24:gpio_rf_gpio_24 {
+ gpios = <&gpio19 0 0>;
+ };
+ gpio_rf_gpio_25:gpio_rf_gpio_25 {
+ gpios = <&gpio19 1 0>;
+ };
+ gpio_rf_gpio_26:gpio_rf_gpio_26 {
+ gpios = <&gpio19 2 0>;
+ };
+ gpio_rf_ssi1:gpio_rf_ssi1 {
+ gpios = <&gpio19 3 0>;
+ };
+ gpio_rf_tcvr_on1:gpio_rf_tcvr_on1 {
+ gpios = <&gpio19 4 0>;
+ };
+ gpio_rf_gpio_29:gpio_rf_gpio_29 {
+ gpios = <&gpio19 5 0>;
+ };
+ gpio_rf_gpio_30:gpio_rf_gpio_30 {
+ gpios = <&gpio19 6 0>;
+ };
+ gpio_apt_pdm0:gpio_apt_pdm0 {
+ gpios = <&gpio19 7 0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi
new file mode 100644
index 000000000000..68332362b6cf
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi
@@ -0,0 +1,684 @@
+/*
+ * pinctrl dts fils for Hislicon HiKey development board
+ *
+ */
+#include <dt-bindings/pinctrl/hisi.h>
+
+/ {
+ smb {
+ pmx0: pinmux@f7010000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &boot_sel_pmx_func
+ &hkadc_ssi_pmx_func
+ &codec_clk_pmx_func
+ &pwm_in_pmx_func
+ &bl_pwm_pmx_func
+ >;
+
+ boot_sel_pmx_func: boot_sel_pmx_func {
+ pinctrl-single,pins = <
+ 0x0 MUX_M0 /* BOOT_SEL (IOMG000) */
+ >;
+ };
+
+ emmc_pmx_func: emmc_pmx_func {
+ pinctrl-single,pins = <
+ 0x100 MUX_M0 /* EMMC_CLK (IOMG064) */
+ 0x104 MUX_M0 /* EMMC_CMD (IOMG065) */
+ 0x108 MUX_M0 /* EMMC_DATA0 (IOMG066) */
+ 0x10c MUX_M0 /* EMMC_DATA1 (IOMG067) */
+ 0x110 MUX_M0 /* EMMC_DATA2 (IOMG068) */
+ 0x114 MUX_M0 /* EMMC_DATA3 (IOMG069) */
+ 0x118 MUX_M0 /* EMMC_DATA4 (IOMG070) */
+ 0x11c MUX_M0 /* EMMC_DATA5 (IOMG071) */
+ 0x120 MUX_M0 /* EMMC_DATA6 (IOMG072) */
+ 0x124 MUX_M0 /* EMMC_DATA7 (IOMG073) */
+ >;
+ };
+
+ sd_pmx_func: sd_pmx_func {
+ pinctrl-single,pins = <
+ 0xc MUX_M0 /* SD_CLK (IOMG003) */
+ 0x10 MUX_M0 /* SD_CMD (IOMG004) */
+ 0x14 MUX_M0 /* SD_DATA0 (IOMG005) */
+ 0x18 MUX_M0 /* SD_DATA1 (IOMG006) */
+ 0x1c MUX_M0 /* SD_DATA2 (IOMG007) */
+ 0x20 MUX_M0 /* SD_DATA3 (IOMG008) */
+ >;
+ };
+ sd_pmx_idle: sd_pmx_idle {
+ pinctrl-single,pins = <
+ 0xc MUX_M1 /* SD_CLK (IOMG003) */
+ 0x10 MUX_M1 /* SD_CMD (IOMG004) */
+ 0x14 MUX_M1 /* SD_DATA0 (IOMG005) */
+ 0x18 MUX_M1 /* SD_DATA1 (IOMG006) */
+ 0x1c MUX_M1 /* SD_DATA2 (IOMG007) */
+ 0x20 MUX_M1 /* SD_DATA3 (IOMG008) */
+ >;
+ };
+
+ sdio_pmx_func: sdio_pmx_func {
+ pinctrl-single,pins = <
+ 0x128 MUX_M0 /* SDIO_CLK (IOMG074) */
+ 0x12c MUX_M0 /* SDIO_CMD (IOMG075) */
+ 0x130 MUX_M0 /* SDIO_DATA0 (IOMG076) */
+ 0x134 MUX_M0 /* SDIO_DATA1 (IOMG077) */
+ 0x138 MUX_M0 /* SDIO_DATA2 (IOMG078) */
+ 0x13c MUX_M0 /* SDIO_DATA3 (IOMG079) */
+ >;
+ };
+ sdio_pmx_idle: sdio_pmx_idle {
+ pinctrl-single,pins = <
+ 0x128 MUX_M1 /* SDIO_CLK (IOMG074) */
+ 0x12c MUX_M1 /* SDIO_CMD (IOMG075) */
+ 0x130 MUX_M1 /* SDIO_DATA0 (IOMG076) */
+ 0x134 MUX_M1 /* SDIO_DATA1 (IOMG077) */
+ 0x138 MUX_M1 /* SDIO_DATA2 (IOMG078) */
+ 0x13c MUX_M1 /* SDIO_DATA3 (IOMG079) */
+ >;
+ };
+
+ isp_pmx_func: isp_pmx_func {
+ pinctrl-single,pins = <
+ 0x24 MUX_M0 /* ISP_PWDN0 (IOMG009) */
+ 0x28 MUX_M0 /* ISP_PWDN1 (IOMG010) */
+ 0x2c MUX_M0 /* ISP_PWDN2 (IOMG011) */
+ 0x30 MUX_M1 /* ISP_SHUTTER0 (IOMG012) */
+ 0x34 MUX_M1 /* ISP_SHUTTER1 (IOMG013) */
+ 0x38 MUX_M1 /* ISP_PWM (IOMG014) */
+ 0x3c MUX_M0 /* ISP_CCLK0 (IOMG015) */
+ 0x40 MUX_M0 /* ISP_CCLK1 (IOMG016) */
+ 0x44 MUX_M0 /* ISP_RESETB0 (IOMG017) */
+ 0x48 MUX_M0 /* ISP_RESETB1 (IOMG018) */
+ 0x4c MUX_M1 /* ISP_STROBE0 (IOMG019) */
+ 0x50 MUX_M1 /* ISP_STROBE1 (IOMG020) */
+ 0x54 MUX_M0 /* ISP_SDA0 (IOMG021) */
+ 0x58 MUX_M0 /* ISP_SCL0 (IOMG022) */
+ 0x5c MUX_M0 /* ISP_SDA1 (IOMG023) */
+ 0x60 MUX_M0 /* ISP_SCL1 (IOMG024) */
+ >;
+ };
+
+ hkadc_ssi_pmx_func: hkadc_ssi_pmx_func {
+ pinctrl-single,pins = <
+ 0x68 MUX_M0 /* HKADC_SSI (IOMG026) */
+ >;
+ };
+
+ codec_clk_pmx_func: codec_clk_pmx_func {
+ pinctrl-single,pins = <
+ 0x6c MUX_M0 /* CODEC_CLK (IOMG027) */
+ >;
+ };
+
+ codec_pmx_func: codec_pmx_func {
+ pinctrl-single,pins = <
+ 0x70 MUX_M1 /* DMIC_CLK (IOMG028) */
+ 0x74 MUX_M0 /* CODEC_SYNC (IOMG029) */
+ 0x78 MUX_M0 /* CODEC_DI (IOMG030) */
+ 0x7c MUX_M0 /* CODEC_DO (IOMG031) */
+ >;
+ };
+
+ fm_pmx_func: fm_pmx_func {
+ pinctrl-single,pins = <
+ 0x80 MUX_M1 /* FM_XCLK (IOMG032) */
+ 0x84 MUX_M1 /* FM_XFS (IOMG033) */
+ 0x88 MUX_M1 /* FM_DI (IOMG034) */
+ 0x8c MUX_M1 /* FM_DO (IOMG035) */
+ >;
+ };
+
+ bt_pmx_func: bt_pmx_func {
+ pinctrl-single,pins = <
+ 0x90 MUX_M0 /* BT_XCLK (IOMG036) */
+ 0x94 MUX_M0 /* BT_XFS (IOMG037) */
+ 0x98 MUX_M0 /* BT_DI (IOMG038) */
+ 0x9c MUX_M0 /* BT_DO (IOMG039) */
+ >;
+ };
+
+ pwm_in_pmx_func: pwm_in_pmx_func {
+ pinctrl-single,pins = <
+ 0xb8 MUX_M1 /* PWM_IN (IOMG046) */
+ >;
+ };
+
+ bl_pwm_pmx_func: bl_pwm_pmx_func {
+ pinctrl-single,pins = <
+ 0xbc MUX_M1 /* BL_PWM (IOMG047) */
+ >;
+ };
+
+ uart0_pmx_func: uart0_pmx_func {
+ pinctrl-single,pins = <
+ 0xc0 MUX_M0 /* UART0_RXD (IOMG048) */
+ 0xc4 MUX_M0 /* UART0_TXD (IOMG049) */
+ >;
+ };
+
+ uart1_pmx_func: uart1_pmx_func {
+ pinctrl-single,pins = <
+ 0xc8 MUX_M0 /* UART1_CTS_N (IOMG050) */
+ 0xcc MUX_M0 /* UART1_RTS_N (IOMG051) */
+ 0xd0 MUX_M0 /* UART1_RXD (IOMG052) */
+ 0xd4 MUX_M0 /* UART1_TXD (IOMG053) */
+ >;
+ };
+
+ uart2_pmx_func: uart2_pmx_func {
+ pinctrl-single,pins = <
+ 0xd8 MUX_M0 /* UART2_CTS_N (IOMG054) */
+ 0xdc MUX_M0 /* UART2_RTS_N (IOMG055) */
+ 0xe0 MUX_M0 /* UART2_RXD (IOMG056) */
+ 0xe4 MUX_M0 /* UART2_TXD (IOMG057) */
+ >;
+ };
+
+ uart3_pmx_func: uart3_pmx_func {
+ pinctrl-single,pins = <
+ 0x180 MUX_M1 /* UART3_CTS_N (IOMG096) */
+ 0x184 MUX_M1 /* UART3_RTS_N (IOMG097) */
+ 0x188 MUX_M1 /* UART3_RXD (IOMG098) */
+ 0x18c MUX_M1 /* UART3_TXD (IOMG099) */
+ >;
+ };
+
+ uart4_pmx_func: uart4_pmx_func {
+ pinctrl-single,pins = <
+ 0x1d0 MUX_M1 /* UART4_CTS_N (IOMG116) */
+ 0x1d4 MUX_M1 /* UART4_RTS_N (IOMG117) */
+ 0x1d8 MUX_M1 /* UART4_RXD (IOMG118) */
+ 0x1dc MUX_M1 /* UART4_TXD (IOMG119) */
+ >;
+ };
+
+ uart5_pmx_func: uart5_pmx_func {
+ pinctrl-single,pins = <
+ 0x1c8 MUX_M1 /* UART5_RXD (IOMG114) */
+ 0x1cc MUX_M1 /* UART5_TXD (IOMG115) */
+ >;
+ };
+
+ i2c0_pmx_func: i2c0_pmx_func {
+ pinctrl-single,pins = <
+ 0xe8 MUX_M0 /* I2C0_SCL (IOMG058) */
+ 0xec MUX_M0 /* I2C0_SDA (IOMG059) */
+ >;
+ };
+
+ i2c1_pmx_func: i2c1_pmx_func {
+ pinctrl-single,pins = <
+ 0xf0 MUX_M0 /* I2C1_SCL (IOMG060) */
+ 0xf4 MUX_M0 /* I2C1_SDA (IOMG061) */
+ >;
+ };
+
+ i2c2_pmx_func: i2c2_pmx_func {
+ pinctrl-single,pins = <
+ 0xf8 MUX_M0 /* I2C2_SCL (IOMG062) */
+ 0xfc MUX_M0 /* I2C2_SDA (IOMG063) */
+ >;
+ };
+ };
+
+ pmx1: pinmux@f7010800 {
+
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &boot_sel_cfg_func
+ &hkadc_ssi_cfg_func
+ &codec_clk_cfg_func
+ &pwm_in_cfg_func
+ &bl_pwm_cfg_func
+ >;
+
+ boot_sel_cfg_func: boot_sel_cfg_func {
+ pinctrl-single,pins = <
+ 0x0 0x0 /* BOOT_SEL (IOCFG000) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ hkadc_ssi_cfg_func: hkadc_ssi_cfg_func {
+ pinctrl-single,pins = <
+ 0x6c 0x0 /* HKADC_SSI (IOCFG027) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ emmc_clk_cfg_func: emmc_clk_cfg_func {
+ pinctrl-single,pins = <
+ 0x104 0x0 /* EMMC_CLK (IOCFG065) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
+ };
+
+ emmc_cfg_func: emmc_cfg_func {
+ pinctrl-single,pins = <
+ 0x108 0x0 /* EMMC_CMD (IOCFG066) */
+ 0x10c 0x0 /* EMMC_DATA0 (IOCFG067) */
+ 0x110 0x0 /* EMMC_DATA1 (IOCFG068) */
+ 0x114 0x0 /* EMMC_DATA2 (IOCFG069) */
+ 0x118 0x0 /* EMMC_DATA3 (IOCFG070) */
+ 0x11c 0x0 /* EMMC_DATA4 (IOCFG071) */
+ 0x120 0x0 /* EMMC_DATA5 (IOCFG072) */
+ 0x124 0x0 /* EMMC_DATA6 (IOCFG073) */
+ 0x128 0x0 /* EMMC_DATA7 (IOCFG074) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
+ };
+
+ emmc_rst_cfg_func: emmc_rst_cfg_func {
+ pinctrl-single,pins = <
+ 0x12c 0x0 /* EMMC_RST_N (IOCFG075) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
+ };
+
+ sd_clk_cfg_func: sd_clk_cfg_func {
+ pinctrl-single,pins = <
+ 0xc 0x0 /* SD_CLK (IOCFG003) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_10MA DRIVE_MASK>;
+ };
+ sd_clk_cfg_idle: sd_clk_cfg_idle {
+ pinctrl-single,pins = <
+ 0xc 0x0 /* SD_CLK (IOCFG003) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ sd_cfg_func: sd_cfg_func {
+ pinctrl-single,pins = <
+ 0x10 0x0 /* SD_CMD (IOCFG004) */
+ 0x14 0x0 /* SD_DATA0 (IOCFG005) */
+ 0x18 0x0 /* SD_DATA1 (IOCFG006) */
+ 0x1c 0x0 /* SD_DATA2 (IOCFG007) */
+ 0x20 0x0 /* SD_DATA3 (IOCFG008) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
+ };
+ sd_cfg_idle: sd_cfg_idle {
+ pinctrl-single,pins = <
+ 0x10 0x0 /* SD_CMD (IOCFG004) */
+ 0x14 0x0 /* SD_DATA0 (IOCFG005) */
+ 0x18 0x0 /* SD_DATA1 (IOCFG006) */
+ 0x1c 0x0 /* SD_DATA2 (IOCFG007) */
+ 0x20 0x0 /* SD_DATA3 (IOCFG008) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ sdio_clk_cfg_func: sdio_clk_cfg_func {
+ pinctrl-single,pins = <
+ 0x134 0x0 /* SDIO_CLK (IOCFG077) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
+ };
+ sdio_clk_cfg_idle: sdio_clk_cfg_idle {
+ pinctrl-single,pins = <
+ 0x134 0x0 /* SDIO_CLK (IOCFG077) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ sdio_cfg_func: sdio_cfg_func {
+ pinctrl-single,pins = <
+ 0x138 0x0 /* SDIO_CMD (IOCFG078) */
+ 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */
+ 0x140 0x0 /* SDIO_DATA1 (IOCFG080) */
+ 0x144 0x0 /* SDIO_DATA2 (IOCFG081) */
+ 0x148 0x0 /* SDIO_DATA3 (IOCFG082) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
+ };
+ sdio_cfg_idle: sdio_cfg_idle {
+ pinctrl-single,pins = <
+ 0x138 0x0 /* SDIO_CMD (IOCFG078) */
+ 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */
+ 0x140 0x0 /* SDIO_DATA1 (IOCFG080) */
+ 0x144 0x0 /* SDIO_DATA2 (IOCFG081) */
+ 0x148 0x0 /* SDIO_DATA3 (IOCFG082) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ isp_cfg_func1: isp_cfg_func1 {
+ pinctrl-single,pins = <
+ 0x28 0x0 /* ISP_PWDN0 (IOCFG010) */
+ 0x2c 0x0 /* ISP_PWDN1 (IOCFG011) */
+ 0x30 0x0 /* ISP_PWDN2 (IOCFG012) */
+ 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */
+ 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */
+ 0x3c 0x0 /* ISP_PWM (IOCFG015) */
+ 0x40 0x0 /* ISP_CCLK0 (IOCFG016) */
+ 0x44 0x0 /* ISP_CCLK1 (IOCFG017) */
+ 0x48 0x0 /* ISP_RESETB0 (IOCFG018) */
+ 0x4c 0x0 /* ISP_RESETB1 (IOCFG019) */
+ 0x50 0x0 /* ISP_STROBE0 (IOCFG020) */
+ 0x58 0x0 /* ISP_SDA0 (IOCFG022) */
+ 0x5c 0x0 /* ISP_SCL0 (IOCFG023) */
+ 0x60 0x0 /* ISP_SDA1 (IOCFG024) */
+ 0x64 0x0 /* ISP_SCL1 (IOCFG025) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+ isp_cfg_idle1: isp_cfg_idle1 {
+ pinctrl-single,pins = <
+ 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */
+ 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ isp_cfg_func2: isp_cfg_func2 {
+ pinctrl-single,pins = <
+ 0x54 0x0 /* ISP_STROBE1 (IOCFG021) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ codec_clk_cfg_func: codec_clk_cfg_func {
+ pinctrl-single,pins = <
+ 0x70 0x0 /* CODEC_CLK (IOCFG028) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
+ };
+ codec_clk_cfg_idle: codec_clk_cfg_idle {
+ pinctrl-single,pins = <
+ 0x70 0x0 /* CODEC_CLK (IOCFG028) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ codec_cfg_func1: codec_cfg_func1 {
+ pinctrl-single,pins = <
+ 0x74 0x0 /* DMIC_CLK (IOCFG029) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ codec_cfg_func2: codec_cfg_func2 {
+ pinctrl-single,pins = <
+ 0x78 0x0 /* CODEC_SYNC (IOCFG030) */
+ 0x7c 0x0 /* CODEC_DI (IOCFG031) */
+ 0x80 0x0 /* CODEC_DO (IOCFG032) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
+ };
+ codec_cfg_idle2: codec_cfg_idle2 {
+ pinctrl-single,pins = <
+ 0x78 0x0 /* CODEC_SYNC (IOCFG030) */
+ 0x7c 0x0 /* CODEC_DI (IOCFG031) */
+ 0x80 0x0 /* CODEC_DO (IOCFG032) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ fm_cfg_func: fm_cfg_func {
+ pinctrl-single,pins = <
+ 0x84 0x0 /* FM_XCLK (IOCFG033) */
+ 0x88 0x0 /* FM_XFS (IOCFG034) */
+ 0x8c 0x0 /* FM_DI (IOCFG035) */
+ 0x90 0x0 /* FM_DO (IOCFG036) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ bt_cfg_func: bt_cfg_func {
+ pinctrl-single,pins = <
+ 0x94 0x0 /* BT_XCLK (IOCFG037) */
+ 0x98 0x0 /* BT_XFS (IOCFG038) */
+ 0x9c 0x0 /* BT_DI (IOCFG039) */
+ 0xa0 0x0 /* BT_DO (IOCFG040) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+ bt_cfg_idle: bt_cfg_idle {
+ pinctrl-single,pins = <
+ 0x94 0x0 /* BT_XCLK (IOCFG037) */
+ 0x98 0x0 /* BT_XFS (IOCFG038) */
+ 0x9c 0x0 /* BT_DI (IOCFG039) */
+ 0xa0 0x0 /* BT_DO (IOCFG040) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ pwm_in_cfg_func: pwm_in_cfg_func {
+ pinctrl-single,pins = <
+ 0xbc 0x0 /* PWM_IN (IOCFG047) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ bl_pwm_cfg_func: bl_pwm_cfg_func {
+ pinctrl-single,pins = <
+ 0xc0 0x0 /* BL_PWM (IOCFG048) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ uart0_cfg_func1: uart0_cfg_func1 {
+ pinctrl-single,pins = <
+ 0xc4 0x0 /* UART0_RXD (IOCFG049) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ uart0_cfg_func2: uart0_cfg_func2 {
+ pinctrl-single,pins = <
+ 0xc8 0x0 /* UART0_TXD (IOCFG050) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
+ };
+
+ uart1_cfg_func1: uart1_cfg_func1 {
+ pinctrl-single,pins = <
+ 0xcc 0x0 /* UART1_CTS_N (IOCFG051) */
+ 0xd4 0x0 /* UART1_RXD (IOCFG053) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ uart1_cfg_func2: uart1_cfg_func2 {
+ pinctrl-single,pins = <
+ 0xd0 0x0 /* UART1_RTS_N (IOCFG052) */
+ 0xd8 0x0 /* UART1_TXD (IOCFG054) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ uart2_cfg_func: uart2_cfg_func {
+ pinctrl-single,pins = <
+ 0xdc 0x0 /* UART2_CTS_N (IOCFG055) */
+ 0xe0 0x0 /* UART2_RTS_N (IOCFG056) */
+ 0xe4 0x0 /* UART2_RXD (IOCFG057) */
+ 0xe8 0x0 /* UART2_TXD (IOCFG058) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ uart3_cfg_func: uart3_cfg_func {
+ pinctrl-single,pins = <
+ 0x190 0x0 /* UART3_CTS_N (IOCFG100) */
+ 0x194 0x0 /* UART3_RTS_N (IOCFG101) */
+ 0x198 0x0 /* UART3_RXD (IOCFG102) */
+ 0x19c 0x0 /* UART3_TXD (IOCFG103) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ uart4_cfg_func: uart4_cfg_func {
+ pinctrl-single,pins = <
+ 0x1e0 0x0 /* UART4_CTS_N (IOCFG120) */
+ 0x1e4 0x0 /* UART4_RTS_N (IOCFG121) */
+ 0x1e8 0x0 /* UART4_RXD (IOCFG122) */
+ 0x1ec 0x0 /* UART4_TXD (IOCFG123) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ uart5_cfg_func: uart5_cfg_func {
+ pinctrl-single,pins = <
+ 0x1d8 0x0 /* UART4_RXD (IOCFG118) */
+ 0x1dc 0x0 /* UART4_TXD (IOCFG119) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ i2c0_cfg_func: i2c0_cfg_func {
+ pinctrl-single,pins = <
+ 0xec 0x0 /* I2C0_SCL (IOCFG059) */
+ 0xf0 0x0 /* I2C0_SDA (IOCFG060) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ i2c1_cfg_func: i2c1_cfg_func {
+ pinctrl-single,pins = <
+ 0xf4 0x0 /* I2C1_SCL (IOCFG061) */
+ 0xf8 0x0 /* I2C1_SDA (IOCFG062) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ i2c2_cfg_func: i2c2_cfg_func {
+ pinctrl-single,pins = <
+ 0xfc 0x0 /* I2C2_SCL (IOCFG063) */
+ 0x100 0x0 /* I2C2_SDA (IOCFG064) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+ };
+
+ pmx2: pinmux@f8001800 {
+
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &rstout_n_cfg_func
+ >;
+
+ rstout_n_cfg_func: rstout_n_cfg_func {
+ pinctrl-single,pins = <
+ 0x0 0x0 /* RSTOUT_N (IOCFG000) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ pmu_peri_en_cfg_func: pmu_peri_en_cfg_func {
+ pinctrl-single,pins = <
+ 0x4 0x0 /* PMU_PERI_EN (IOCFG001) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ sysclk0_en_cfg_func: sysclk0_en_cfg_func {
+ pinctrl-single,pins = <
+ 0x8 0x0 /* SYSCLK0_EN (IOCFG002) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+
+ jtag_tdo_cfg_func: jtag_tdo_cfg_func {
+ pinctrl-single,pins = <
+ 0xc 0x0 /* JTAG_TDO (IOCFG003) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
+ };
+
+ rf_reset_cfg_func: rf_reset_cfg_func {
+ pinctrl-single,pins = <
+ 0x70 0x0 /* RF_RESET0 (IOCFG028) */
+ 0x74 0x0 /* RF_RESET1 (IOCFG029) */
+ >;
+ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 42b0b9228cda..7f90c6d9aabe 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -3961,6 +3961,7 @@ CONFIG_MFD_WM831X_SPI=y
CONFIG_MFD_WM8350=y
CONFIG_MFD_WM8350_I2C=y
CONFIG_MFD_WM8994=m
+CONFIG_MFD_HI655X_PMIC=y
CONFIG_MFD_VEXPRESS_SYSREG=y
CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
@@ -4042,6 +4043,8 @@ CONFIG_REGULATOR_WM831X=m
CONFIG_REGULATOR_WM8350=m
CONFIG_REGULATOR_WM8400=m
CONFIG_REGULATOR_WM8994=m
+CONFIG_REGULATOR_HI6220=y
+CONFIG_REGULATOR_HI655X=y
CONFIG_MEDIA_SUPPORT=m
#
@@ -5639,15 +5642,15 @@ CONFIG_UWB=m
CONFIG_UWB_HWA=m
CONFIG_UWB_WHCI=m
CONFIG_UWB_I1480U=m
-CONFIG_MMC=m
+CONFIG_MMC=y
# CONFIG_MMC_DEBUG is not set
# CONFIG_MMC_CLKGATE is not set
#
# MMC/SD/SDIO Card Drivers
#
-CONFIG_MMC_BLOCK=m
-CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=64
CONFIG_MMC_BLOCK_BOUNCE=y
CONFIG_SDIO_UART=m
# CONFIG_MMC_TEST is not set
@@ -5669,11 +5672,11 @@ CONFIG_MMC_TIFM_SD=m
CONFIG_MMC_SPI=m
CONFIG_MMC_CB710=m
CONFIG_MMC_VIA_SDMMC=m
-CONFIG_MMC_DW=m
+CONFIG_MMC_DW=y
CONFIG_MMC_DW_IDMAC=y
-CONFIG_MMC_DW_PLTFM=m
+CONFIG_MMC_DW_PLTFM=y
CONFIG_MMC_DW_EXYNOS=m
-CONFIG_MMC_DW_K3=m
+CONFIG_MMC_DW_K3=y
CONFIG_MMC_DW_PCI=m
CONFIG_MMC_VUB300=m
CONFIG_MMC_USHC=m
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index d5ad04dad081..78456525376a 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1430,6 +1430,13 @@ config MFD_STW481X
in various ST Microelectronics and ST-Ericsson embedded
Nomadik series.
+config MFD_HI655X_PMIC
+ tristate "HiSilicon Hi655X series pmic driver"
+ depends on ARCH_HISI
+ select MFD_CORE
+ help
+ Select this option to enable Hisilicon hi655x series pmic driver.
+
menu "Multimedia Capabilities Port drivers"
depends on ARCH_SA1100
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 0e5cfeba107c..7289209b0a1a 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -174,6 +174,7 @@ obj-$(CONFIG_MFD_VEXPRESS_SYSREG) += vexpress-sysreg.o
obj-$(CONFIG_MFD_RETU) += retu-mfd.o
obj-$(CONFIG_MFD_AS3711) += as3711.o
obj-$(CONFIG_MFD_AS3722) += as3722.o
+obj-$(CONFIG_MFD_HI655X_PMIC) += hi655x-pmic.o
obj-$(CONFIG_MFD_STW481X) += stw481x.o
obj-$(CONFIG_MFD_IPAQ_MICRO) += ipaq-micro.o
obj-$(CONFIG_MFD_MENF21BMC) += menf21bmc.o
diff --git a/drivers/mfd/hi655x-pmic.c b/drivers/mfd/hi655x-pmic.c
new file mode 100644
index 000000000000..a0910345f6b6
--- /dev/null
+++ b/drivers/mfd/hi655x-pmic.c
@@ -0,0 +1,392 @@
+/*
+ * Hisilicon Hi655x series PMIC driver
+ *
+ * Copyright (c) 2015 Hisilicon Co. Ltd
+ *
+ * Author:
+ * Dongbin Yu <yudongbin@huawei.com>
+ * Bintian Wang <bintian.wang@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/slab.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/types.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/hardirq.h>
+#include <linux/of_gpio.h>
+#include <linux/platform_device.h>
+#include <linux/of_platform.h>
+#include <linux/irqdomain.h>
+#include <linux/mfd/hi655x-pmic.h>
+
+static void __iomem *PMUSSI_BASE_ADDR;
+
+#define PMUSSI_REG(addr) ((char *)PMUSSI_BASE_ADDR + ((addr) << 2))
+
+#define DEBUG_PMIC_GPIO
+
+struct hi655x_pmic {
+ struct resource *res;
+ struct device *dev;
+ spinlock_t ssi_hw_lock;
+ struct clk *clk;
+ struct irq_domain *domain;
+ int irq;
+ int gpio;
+ unsigned int irqs[HI655x_NR_IRQ];
+ unsigned int ver;
+};
+
+static struct hi655x_pmic *pmic_dev;
+
+unsigned char hi655x_pmic_reg_read (unsigned int addr)
+{
+ unsigned char val;
+ val = *(volatile unsigned char*)PMUSSI_REG(addr);
+ return val;
+}
+EXPORT_SYMBOL(hi655x_pmic_reg_read);
+
+void hi655x_pmic_reg_write (unsigned int addr, unsigned char val)
+{
+ *(volatile unsigned char*)PMUSSI_REG(addr) = val;
+}
+EXPORT_SYMBOL(hi655x_pmic_reg_write);
+
+unsigned char hi655x_pmic_reg_read_ex (void *pmu_base, unsigned int addr)
+{
+ unsigned char val;
+ val = *(volatile unsigned char*)PMUSSI_REG_EX(pmu_base, addr);
+ return val;
+}
+EXPORT_SYMBOL(hi655x_pmic_reg_read_ex);
+
+void hi655x_pmic_reg_write_ex(void *pmu_base, unsigned int addr, unsigned char val)
+{
+ *(volatile unsigned char*)PMUSSI_REG_EX(pmu_base, addr) = val;
+}
+EXPORT_SYMBOL(hi655x_pmic_reg_write_ex);
+
+static struct of_device_id of_hi655x_pmic_child_match_tbl[] = {
+ { .compatible = "hisilicon,hi6552-regulator-pmic", },
+ { .compatible = "hisilicon,hi6552-powerkey", },
+ { .compatible = "hisilicon,hi6552-usbvbus", },
+ { .compatible = "hisilicon,hi6552-coul", },
+ { .compatible = "hisilicon,hi6552-pmu-rtc", },
+ { .compatible = "hisilicon,hi6552-pmic-mntn", },
+ { /* end */ }
+};
+
+static struct of_device_id of_hi655x_pmic_match_tbl[] = {
+ { .compatible = "hisilicon,hi6552-pmic-driver", },
+ { /* end */ }
+};
+
+unsigned int hi655x_pmic_get_version(void)
+{
+ unsigned int uvalue = 0;
+ uvalue = (unsigned int)hi655x_pmic_reg_read(HI655x_VER_REG);
+ uvalue = uvalue & HI655x_REG_WIDTH;
+
+ return uvalue;
+}
+
+static int hi655x_pmic_version_check(void)
+{
+ int ret = SSI_DEVICE_ERR;
+ int ver = 0;
+
+ ver = hi655x_pmic_get_version();
+ if ((ver >= PMU_VER_START) && (ver <= PMU_VER_END))
+ return SSI_DEVICE_OK;
+
+ return ret;
+}
+
+static irqreturn_t hi655x_pmic_irq_handler(int irq, void *data)
+{
+ struct hi655x_pmic *pmic = (struct hi655x_pmic *)data;
+ unsigned long pending;
+ unsigned int ret = IRQ_NONE;
+ int i, offset;
+
+ for (i = 0; i < HI655x_IRQ_ARRAY; i++) {
+ pending = hi655x_pmic_reg_read((i + HI655x_IRQ_STAT_BASE));
+ pending &= HI655x_REG_WIDTH;
+ if (pending != 0)
+ pr_debug("pending[%d]=0x%lx\n\r", i, pending);
+
+ /* clear pmic-sub-interrupt */
+ hi655x_pmic_reg_write((i + HI655x_IRQ_STAT_BASE), pending);
+
+ if (pending) {
+ for_each_set_bit(offset, &pending, HI655x_BITS)
+ generic_handle_irq(pmic->irqs[offset + i * HI655x_BITS]);
+ ret = IRQ_HANDLED;
+ }
+ }
+
+ return ret;
+}
+
+static void hi655x_pmic_irq_mask(struct irq_data *d)
+{
+ u32 data, offset;
+ unsigned long pmic_spin_flag = 0;
+ offset = ((irqd_to_hwirq(d) >> 3) + HI655x_IRQ_MASK_BASE);
+
+ spin_lock_irqsave(&pmic_dev->ssi_hw_lock, pmic_spin_flag);
+ data = hi655x_pmic_reg_read(offset);
+ data |= (1 << (irqd_to_hwirq(d) & 0x07));
+ hi655x_pmic_reg_write(offset, data);
+ spin_unlock_irqrestore(&pmic_dev->ssi_hw_lock, pmic_spin_flag);
+}
+
+static void hi655x_pmic_irq_unmask(struct irq_data *d)
+{
+ u32 data, offset;
+ unsigned long pmic_spin_flag = 0;
+ offset = ((irqd_to_hwirq(d) >> 3) + HI655x_IRQ_MASK_BASE);
+
+ spin_lock_irqsave(&pmic_dev->ssi_hw_lock, pmic_spin_flag);
+ data = hi655x_pmic_reg_read(offset);
+ data &= ~(1 << (irqd_to_hwirq(d) & 0x07));
+ hi655x_pmic_reg_write(offset, data);
+ spin_unlock_irqrestore(&pmic_dev->ssi_hw_lock, pmic_spin_flag);
+}
+
+static struct irq_chip hi655x_pmic_irqchip = {
+ .name = "hisi-hi655x-pmic-irqchip",
+ .irq_mask = hi655x_pmic_irq_mask,
+ .irq_unmask = hi655x_pmic_irq_unmask,
+};
+
+static int hi655x_pmic_irq_map(struct irq_domain *d, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ struct hi655x_pmic *pmic = d->host_data;
+
+ irq_set_chip_and_handler_name(virq, &hi655x_pmic_irqchip,
+ handle_simple_irq, "hisi-hi655x-pmic-irqchip");
+ irq_set_chip_data(virq, pmic);
+ irq_set_irq_type(virq, IRQ_TYPE_NONE);
+
+ return 0;
+}
+
+static struct irq_domain_ops hi655x_domain_ops = {
+ .map = hi655x_pmic_irq_map,
+ .xlate = irq_domain_xlate_twocell,
+};
+
+static inline void hi655x_pmic_clear_int(void)
+{
+ int addr;
+
+ for (addr = HI655x_IRQ_STAT_BASE; addr < (HI655x_IRQ_STAT_BASE + HI655x_IRQ_ARRAY); addr++)
+ hi655x_pmic_reg_write(addr, HI655x_IRQ_CLR);
+}
+
+static inline void hi655x_pmic_mask_int(void)
+{
+ int addr;
+
+ for (addr = HI655x_IRQ_MASK_BASE; addr < (HI655x_IRQ_MASK_BASE + HI655x_IRQ_ARRAY); addr++)
+ hi655x_pmic_reg_write(addr, HI655x_IRQ_MASK);
+}
+
+static int hi655x_pmic_probe(struct platform_device *pdev)
+{
+ int i = 0;
+ int ret = 0 ;
+ int dev_stat = 0;
+ unsigned int virq = 0;
+ int pmu_on = 1;
+ enum of_gpio_flags gpio_flags;
+ struct device_node *gpio_np = NULL;
+
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct hi655x_pmic *pmic = NULL;
+
+ /*
+ * this is new feature in kernel 3.10
+ */
+ pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
+ if (!pmic) {
+ printk("cannot allocate hi655x_pmic device info\n");
+ return -ENOMEM;
+ }
+ pmic_dev = pmic;
+
+ /* init spin lock */
+ spin_lock_init(&pmic->ssi_hw_lock);
+
+ pmic->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!pmic->res) {
+ printk("platform_get_resource err\n");
+ return -ENOENT;
+ }
+ if (!devm_request_mem_region(dev, pmic->res->start,
+ resource_size(pmic->res),
+ pdev->name)) {
+ printk("cannot claim register memory\n");
+ return -ENOMEM;
+ }
+ PMUSSI_BASE_ADDR = ioremap(pmic->res->start,
+ resource_size(pmic->res));
+ if (!PMUSSI_BASE_ADDR) {
+ printk("cannot map register memory\n");
+ return -ENOMEM;
+ }
+
+ /* confirm the pmu version */
+ pmic->ver = hi655x_pmic_get_version();
+ if ((pmic->ver < PMU_VER_START) || (pmic->ver > PMU_VER_END)) {
+ pr_err("it is wrong pmu version\n");
+ pmu_on = 0;
+ }
+
+ hi655x_pmic_reg_write(0x1b5, 0xff);
+
+#ifdef DEBUG_PMIC_GPIO
+ /*
+ * must finish the gpio&irq is function
+ */
+ gpio_np = of_parse_phandle(np, "pmu_irq_gpio", 0);
+ if (!gpio_np) {
+ dev_err(dev, "can't parse property\n");
+ return -ENOENT;
+ }
+ pmic->gpio = of_get_gpio_flags(gpio_np, 0, &gpio_flags);
+ if (pmic->gpio < 0) {
+ dev_err(dev, "failed to of_get_gpio_flags %d\n", pmic->gpio);
+ return pmic->gpio;
+ }
+ if (!gpio_is_valid(pmic->gpio)) {
+ dev_err(dev, "it is invalid gpio %d\n", pmic->gpio);
+ return -EINVAL;
+ }
+
+ ret = gpio_request_one(pmic->gpio, GPIOF_IN, "hi655x_pmic_irq");
+ if (ret < 0) {
+ pr_err("failed to request gpio %d, ret:%d\n", pmic->gpio, ret);
+ return ret;
+ }
+ pmic->irq = gpio_to_irq(pmic->gpio);
+#endif
+
+ /* clear PMIC sub-interrupt */
+ hi655x_pmic_clear_int();
+
+ /* mask PMIC sub-interrupt */
+ hi655x_pmic_mask_int();
+
+ /* register irq domain */
+ pmic->domain = irq_domain_add_simple(np, HI655x_NR_IRQ, 0,
+ &hi655x_domain_ops, pmic);
+ if (!pmic->domain) {
+ pr_err("in %s failed irq domain add simple!\n", __func__);
+ ret = -ENODEV;
+ return ret;
+ }
+
+ for (i = 0; i < HI655x_NR_IRQ; i++) {
+ virq = irq_create_mapping(pmic->domain, i);
+ if (0 == virq) {
+ printk("Failed mapping hwirq\n");
+ ret = -ENOSPC;
+ return ret;
+ }
+ pmic->irqs[i] = virq;
+ }
+
+ /* Check the GPIO status is high */
+ if (pmu_on) {
+ ret = request_threaded_irq(pmic->irq, hi655x_pmic_irq_handler, NULL,
+ IRQF_TRIGGER_LOW | IRQF_SHARED | IRQF_NO_SUSPEND,
+ "hi655x-pmic-irq", pmic);
+ if (ret < 0) {
+ pr_err("*************could not claim pmic %d\n", ret);
+ ret = -ENODEV;
+ return ret;
+ }
+ }
+
+ pmic->dev = dev;
+
+ /* bind pmic to device */
+ platform_set_drvdata(pdev, pmic);
+
+ /* populate sub nodes */
+ of_platform_populate(np, of_hi655x_pmic_child_match_tbl, NULL, dev);
+
+ dev_stat = hi655x_pmic_version_check();
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int hi655x_pmic_suspend(struct platform_device *pdev, pm_message_t pm)
+{
+ return 0;
+}
+
+static int hi655x_pmic_resume(struct platform_device *pdev)
+{
+ return 0;
+}
+#endif
+
+static struct platform_driver pmic_driver = {
+ .driver = {
+ .name = "hisi,hi655x-pmic",
+ .owner = THIS_MODULE,
+ .of_match_table = of_hi655x_pmic_match_tbl,
+ },
+ .probe = hi655x_pmic_probe,
+#ifdef CONFIG_PM
+ .suspend = hi655x_pmic_suspend,
+ .resume = hi655x_pmic_resume,
+#endif
+};
+
+static int __init hi655x_pmic_init(void)
+{
+ int ret = 0;
+
+ ret = platform_driver_register(&pmic_driver);
+ if (ret) {
+ printk("%s: platform_driver_register failed %d\n",
+ __func__, ret);
+ }
+
+ return ret;
+}
+
+static void __exit hi655x_pmic_exit(void)
+{
+ platform_driver_unregister(&pmic_driver);
+}
+
+module_init(hi655x_pmic_init);
+module_exit(hi655x_pmic_exit);
+
+MODULE_AUTHOR("Dongbin Yu <yudongbin@huawei.com>");
+MODULE_DESCRIPTION("Hisilicon HI655x PMU SSI interface driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mmc/host/dw_mmc-k3.c b/drivers/mmc/host/dw_mmc-k3.c
index 650f9cc3f7a6..5ba0b0f09f81 100644
--- a/drivers/mmc/host/dw_mmc-k3.c
+++ b/drivers/mmc/host/dw_mmc-k3.c
@@ -8,16 +8,28 @@
* (at your option) any later version.
*/
-#include <linux/module.h>
-#include <linux/platform_device.h>
#include <linux/clk.h>
+#include <linux/mfd/syscon.h>
#include <linux/mmc/host.h>
#include <linux/mmc/dw_mmc.h>
+#include <linux/module.h>
#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
#include "dw_mmc.h"
#include "dw_mmc-pltfm.h"
+#define AO_SCTRL_SEL18 BIT(10)
+#define AO_SCTRL_CTRL3 0x40C
+
+#define SDMMC_CMD_DISABLE_BOOT BIT(26)
+
+struct k3_priv {
+ struct regmap *reg;
+};
+
static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios)
{
int ret;
@@ -33,8 +45,92 @@ static const struct dw_mci_drv_data k3_drv_data = {
.set_ios = dw_mci_k3_set_ios,
};
+static int dw_mci_hi6220_parse_dt(struct dw_mci *host)
+{
+ struct k3_priv *priv;
+
+ priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->reg = syscon_regmap_lookup_by_phandle(host->dev->of_node,
+ "hisilicon,peripheral-syscon");
+ if (IS_ERR(priv->reg))
+ priv->reg = NULL;
+
+ host->priv = priv;
+ return 0;
+}
+
+static int dw_mci_hi6220_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+ struct dw_mci_slot *slot = mmc_priv(mmc);
+ struct k3_priv *priv;
+ struct dw_mci *host;
+ int min_uv, max_uv;
+ int ret;
+
+ host = slot->host;
+ priv = host->priv;
+
+ if (!priv || !priv->reg)
+ return 0;
+
+ if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
+ ret = regmap_update_bits(priv->reg, AO_SCTRL_CTRL3,
+ AO_SCTRL_SEL18, 0);
+ min_uv = 3000000;
+ max_uv = 3000000;
+ } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
+ ret = regmap_update_bits(priv->reg, AO_SCTRL_CTRL3,
+ AO_SCTRL_SEL18, AO_SCTRL_SEL18);
+ min_uv = 1800000;
+ max_uv = 1800000;
+ } else {
+ dev_dbg(host->dev, "voltage not supported\n");
+ return -EINVAL;
+ }
+
+ if (ret) {
+ dev_dbg(host->dev, "switch voltage failed\n");
+ return ret;
+ }
+
+ if (IS_ERR_OR_NULL(mmc->supply.vqmmc))
+ return 0;
+
+ ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv);
+ if (ret) {
+ dev_dbg(host->dev, "Regulator set error %d: %d - %d\n",
+ ret, min_uv, max_uv);
+ return ret;
+ }
+ return 0;
+}
+
+static void dw_mci_hi6220_set_ios(struct dw_mci *host, struct mmc_ios *ios)
+{
+ int ret;
+ unsigned int clock;
+
+ clock = (ios->clock <= 25000000) ? 25000000 : ios->clock;
+
+ ret = clk_set_rate(host->biu_clk, clock);
+ if (ret)
+ dev_warn(host->dev, "failed to set rate %uHz\n", clock);
+
+ host->bus_hz = clk_get_rate(host->biu_clk);
+}
+
+static const struct dw_mci_drv_data hi6220_data = {
+ .switch_voltage = dw_mci_hi6220_switch_voltage,
+ .set_ios = dw_mci_hi6220_set_ios,
+ .parse_dt = dw_mci_hi6220_parse_dt,
+};
+
static const struct of_device_id dw_mci_k3_match[] = {
{ .compatible = "hisilicon,hi4511-dw-mshc", .data = &k3_drv_data, },
+ { .compatible = "hisilicon,hi6220-dw-mshc", .data = &hi6220_data, },
{},
};
MODULE_DEVICE_TABLE(of, dw_mci_k3_match);
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index f45ab91de339..c7236170bf98 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -287,5 +287,7 @@ struct dw_mci_drv_data {
int (*execute_tuning)(struct dw_mci_slot *slot);
int (*prepare_hs400_tuning)(struct dw_mci *host,
struct mmc_ios *ios);
+ int (*switch_voltage)(struct mmc_host *mmc,
+ struct mmc_ios *ios);
};
#endif /* _DW_MMC_H_ */
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index a6f116aa5235..b629c9ccf423 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -750,5 +750,18 @@ config REGULATOR_WM8994
This driver provides support for the voltage regulators on the
WM8994 CODEC.
+config REGULATOR_HI6220
+ tristate "Hisilicon Hi6220 MTCMOS"
+ depends on ARCH_HISI
+ help
+ This driver provides support for the mtcmos regulators on the
+ Hisilicon Hi6220 chip.
+
+config REGULATOR_HI655X
+ tristate "Hisilicon HI655X PMIC regulators"
+ depends on ARCH_HISI
+ help
+ This driver provides support for the voltage regulators of the
+ Hisilicon PMIC device.
endif
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 2c4da15e1545..30b5b3d5d2c3 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -98,6 +98,7 @@ obj-$(CONFIG_REGULATOR_WM831X) += wm831x-ldo.o
obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o
obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o
obj-$(CONFIG_REGULATOR_WM8994) += wm8994-regulator.o
-
+obj-$(CONFIG_REGULATOR_HI6220) += hi6220-mtcmos.o
+obj-$(CONFIG_REGULATOR_HI655X) += hi655x-regulator.o
ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
diff --git a/drivers/regulator/hi6220-mtcmos.c b/drivers/regulator/hi6220-mtcmos.c
new file mode 100644
index 000000000000..883a32fb37e8
--- /dev/null
+++ b/drivers/regulator/hi6220-mtcmos.c
@@ -0,0 +1,268 @@
+/*
+ * Device driver for MTCMOS DRIVER in HI6220 SOC
+ *
+ * Copyright (c) 2011 Hisilicon Co. Ltd
+ *
+ */
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/of_regulator.h>
+#include <linux/delay.h>
+#include <linux/time.h>
+
+enum {
+ HI6220_MTCMOS1,
+ HI6220_MTCMOS2,
+ HI6220_RG_MAX,
+};
+
+struct hi6220_mtcmos_ctrl_regs {
+ unsigned int enable_reg;
+ unsigned int disable_reg;
+ unsigned int status_reg;
+};
+
+struct hi6220_mtcmos_ctrl_data {
+ int shift;
+ unsigned int mask;
+};
+
+struct hi6220_mtcmos_info {
+ struct regulator_desc rdesc;
+ struct hi6220_mtcmos_ctrl_regs ctrl_regs;
+ struct hi6220_mtcmos_ctrl_data ctrl_data;
+};
+
+struct hi6220_mtcmos {
+ struct regulator_dev *rdev[HI6220_RG_MAX];
+ void __iomem *sc_on_regs;
+ int mtcmos_steady_time;
+ spinlock_t mtcmos_spin_lock;
+};
+
+static int hi6220_mtcmos_is_on(struct hi6220_mtcmos *mtcmos,
+ unsigned int regs, unsigned int mask, int shift)
+{
+ unsigned int ret;
+ unsigned long mtcmos_spin_flag = 0;
+
+ spin_lock_irqsave(&mtcmos->mtcmos_spin_lock, mtcmos_spin_flag);
+ ret = readl(mtcmos->sc_on_regs + regs);
+ spin_unlock_irqrestore(&mtcmos->mtcmos_spin_lock, mtcmos_spin_flag);
+
+ ret &= (mask << shift);
+ return !!ret;
+}
+
+int hi6220_mtcmos_on(struct hi6220_mtcmos *mtcmos,
+ unsigned int regs, unsigned int mask, int shift)
+{
+ unsigned long mtcmos_spin_flag = 0;
+
+ spin_lock_irqsave(&mtcmos->mtcmos_spin_lock, mtcmos_spin_flag);
+ writel(mask << shift, mtcmos->sc_on_regs + regs);
+ udelay(mtcmos->mtcmos_steady_time);
+ spin_unlock_irqrestore(&mtcmos->mtcmos_spin_lock, mtcmos_spin_flag);
+
+ return 0;
+}
+
+int hi6220_mtcmos_off(struct hi6220_mtcmos *mtcmos,
+ unsigned int regs, unsigned int mask, int shift)
+{
+ unsigned long mtcmos_spin_flag = 0;
+
+ spin_lock_irqsave(&mtcmos->mtcmos_spin_lock, mtcmos_spin_flag);
+ writel(mask << shift, mtcmos->sc_on_regs + regs);
+ udelay(mtcmos->mtcmos_steady_time);
+ spin_unlock_irqrestore(&mtcmos->mtcmos_spin_lock,
+ mtcmos_spin_flag);
+
+ return 0;
+}
+
+static int hi6220_regulator_mtcmos_is_enabled(struct regulator_dev *rdev)
+{
+ int ret;
+ struct hi6220_mtcmos_info *sreg = rdev_get_drvdata(rdev);
+ struct platform_device *pdev =
+ container_of(rdev->dev.parent, struct platform_device, dev);
+ struct hi6220_mtcmos *mtcmos = platform_get_drvdata(pdev);
+ struct hi6220_mtcmos_ctrl_regs *ctrl_regs = &(sreg->ctrl_regs);
+ struct hi6220_mtcmos_ctrl_data *ctrl_data = &(sreg->ctrl_data);
+
+ ret = hi6220_mtcmos_is_on(mtcmos, ctrl_regs->status_reg,
+ ctrl_data->mask, ctrl_data->shift);
+ return ret;
+}
+
+static int hi6220_regulator_mtcmos_enabled(struct regulator_dev *rdev)
+{
+ int ret;
+ struct hi6220_mtcmos_info *sreg = rdev_get_drvdata(rdev);
+ struct platform_device *pdev =
+ container_of(rdev->dev.parent, struct platform_device, dev);
+ struct hi6220_mtcmos *mtcmos = platform_get_drvdata(pdev);
+ struct hi6220_mtcmos_ctrl_regs *ctrl_regs = &(sreg->ctrl_regs);
+ struct hi6220_mtcmos_ctrl_data *ctrl_data = &(sreg->ctrl_data);
+
+ ret = hi6220_mtcmos_on(mtcmos, ctrl_regs->enable_reg,
+ ctrl_data->mask, ctrl_data->shift);
+ if (0 == hi6220_mtcmos_is_on(mtcmos, ctrl_regs->status_reg,
+ ctrl_data->mask, ctrl_data->shift)) {
+ return -1;
+ }
+ return ret;
+}
+
+static int hi6220_regulator_mtcmos_disabled(struct regulator_dev *rdev)
+{
+ int ret;
+ struct hi6220_mtcmos_info *sreg = rdev_get_drvdata(rdev);
+ struct platform_device *pdev =
+ container_of(rdev->dev.parent, struct platform_device, dev);
+ struct hi6220_mtcmos *mtcmos = platform_get_drvdata(pdev);
+ struct hi6220_mtcmos_ctrl_regs *ctrl_regs = &(sreg->ctrl_regs);
+ struct hi6220_mtcmos_ctrl_data *ctrl_data = &(sreg->ctrl_data);
+
+ ret = hi6220_mtcmos_off(mtcmos, ctrl_regs->disable_reg,
+ ctrl_data->mask, ctrl_data->shift);
+
+ return ret;
+}
+
+static struct regulator_ops hi6220_mtcmos_mtcmos_rops = {
+ .is_enabled = hi6220_regulator_mtcmos_is_enabled,
+ .enable = hi6220_regulator_mtcmos_enabled,
+ .disable = hi6220_regulator_mtcmos_disabled,
+};
+
+#define HI6220_MTCMOS(vreg) \
+{ \
+ .rdesc = { \
+ .name = #vreg, \
+ .ops = &hi6220_mtcmos_mtcmos_rops, \
+ .type = REGULATOR_VOLTAGE, \
+ .owner = THIS_MODULE, \
+ }, \
+}
+
+static struct hi6220_mtcmos_info hi6220_mtcmos_info[] = {
+ HI6220_MTCMOS(MTCMOS1),
+ HI6220_MTCMOS(MTCMOS2),
+};
+
+static struct of_regulator_match hi6220_mtcmos_matches[] = {
+ { .name = "mtcmos1",
+ .driver_data = &hi6220_mtcmos_info[HI6220_MTCMOS1], },
+ { .name = "mtcmos2",
+ .driver_data = &hi6220_mtcmos_info[HI6220_MTCMOS2], },
+};
+
+static int hi6220_mtcmos_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct hi6220_mtcmos *mtcmos;
+ const __be32 *sc_on_regs = NULL;
+ void __iomem *regs;
+ struct device *dev;
+ struct device_node *np, *child;
+ int count, i;
+ struct regulator_config config = { };
+ struct regulator_init_data *init_data;
+ struct hi6220_mtcmos_info *sreg;
+
+ dev = &pdev->dev;
+ np = dev->of_node;
+ mtcmos = devm_kzalloc(dev,
+ sizeof(struct hi6220_mtcmos), GFP_KERNEL);
+ if (!mtcmos) {
+ dev_err(dev, "cannot allocate hi6220_mtcmos device info\n");
+ return -ENOMEM;
+ }
+
+ spin_lock_init((spinlock_t *)&mtcmos->mtcmos_spin_lock);
+ sc_on_regs = of_get_property(np, "hisilicon,mtcmos-sc-on-base", NULL);
+ if (sc_on_regs) {
+ regs = ioremap(be32_to_cpu(*sc_on_regs), 0x1000);
+ mtcmos->sc_on_regs = regs;
+ }
+ ret = of_property_read_u32(np, "hisilicon,mtcmos-steady-us",
+ &mtcmos->mtcmos_steady_time);
+
+ count = of_regulator_match(&pdev->dev, np,
+ hi6220_mtcmos_matches,
+ ARRAY_SIZE(hi6220_mtcmos_matches));
+
+ for (i = 0; i < HI6220_RG_MAX; i++) {
+ init_data = hi6220_mtcmos_matches[i].init_data;
+ if (!init_data)
+ continue;
+ sreg = hi6220_mtcmos_matches[i].driver_data;
+ config.dev = &pdev->dev;
+ config.init_data = init_data;
+ config.driver_data = sreg;
+ config.of_node = hi6220_mtcmos_matches[i].of_node;
+ child = config.of_node;
+
+ ret = of_property_read_u32_array(child, "hisilicon,ctrl-regs",
+ (unsigned int *)(&sreg->ctrl_regs), 0x3);
+ ret = of_property_read_u32_array(child, "hisilicon,ctrl-data",
+ (unsigned int *)(&sreg->ctrl_data), 0x2);
+
+ mtcmos->rdev[i] = regulator_register(&sreg->rdesc, &config);
+ if (IS_ERR(mtcmos->rdev[i])) {
+ ret = PTR_ERR(mtcmos->rdev[i]);
+ dev_err(&pdev->dev, "failed to register mtcmos %s\n",
+ sreg->rdesc.name);
+ while (--i >= 0)
+ regulator_unregister(mtcmos->rdev[i]);
+
+ return ret;
+ }
+ }
+
+ platform_set_drvdata(pdev, mtcmos);
+ return 0;
+}
+
+static struct of_device_id of_hi6220_mtcmos_match_tbl[] = {
+ { .compatible = "hisilicon,hi6220-mtcmos-driver", },
+ {}
+};
+
+static struct platform_driver mtcmos_driver = {
+ .driver = {
+ .name = "hisi_hi6220_mtcmos",
+ .owner = THIS_MODULE,
+ .of_match_table = of_hi6220_mtcmos_match_tbl,
+ },
+ .probe = hi6220_mtcmos_probe,
+};
+
+static int __init hi6220_mtcmos_init(void)
+{
+ return platform_driver_register(&mtcmos_driver);
+}
+
+static void __exit hi6220_mtcmos_exit(void)
+{
+ platform_driver_unregister(&mtcmos_driver);
+}
+
+fs_initcall(hi6220_mtcmos_init);
+module_exit(hi6220_mtcmos_exit);
+
+MODULE_AUTHOR("Baixing Quan<quanbaixing@huawei.com>");
+MODULE_DESCRIPTION("HI6220 MTCMOS interface driver");
+MODULE_LICENSE("GPL V2");
diff --git a/drivers/regulator/hi655x-regulator.c b/drivers/regulator/hi655x-regulator.c
new file mode 100644
index 000000000000..6424a2e92342
--- /dev/null
+++ b/drivers/regulator/hi655x-regulator.c
@@ -0,0 +1,515 @@
+/*
+ * Hisilicon HI655X PMIC regulator driver
+ *
+ * Copyright (c) 2015 Hisilicon Co. Ltd.
+ *
+ * Author:
+ * Dongbin Yu <yudongbin@huawei.com>
+ * Bintian Wang <bintian.wang@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/of_regulator.h>
+#include <linux/delay.h>
+#include <linux/time.h>
+#include <linux/regulator/hi655x-regulator.h>
+#include <linux/mfd/hi655x-pmic.h>
+
+#define FORMAT_SSI_PMUREG(base, reg) (*(volatile unsigned int *)((char *)base + (reg)))
+#define BSP_REG_SETBITS(base, reg, pos, bits, val) \
+ ((FORMAT_SSI_PMUREG(base, reg) = (FORMAT_SSI_PMUREG(base, reg) \
+ & (~((((unsigned int)1 << (bits)) - 1) << (pos)))) \
+ | ((unsigned int)((val) & (((unsigned int)1 << (bits)) - 1)) << (pos))))
+
+#define BSP_REG_GETBITS(base, reg, pos, bits) \
+ (((FORMAT_SSI_PMUREG(base, reg) >> (pos)) \
+ &(((unsigned int)1 << (bits)) - 1)))
+
+struct hi655x_regulator {
+ int status; /* this property in child node */
+ unsigned int off_on_delay; /* this property in parent node */
+ enum hi655x_regulator_type type; /* this property in child node */
+ int regulator_id;
+
+ /* this property must be unify which is in child node */
+ struct hi655x_regulator_ctrl_regs ctrl_regs;
+ struct hi655x_regulator_ctrl_data ctrl_data;
+
+ struct hi655x_regulator_vset_regs vset_regs;
+ struct hi655x_regulator_vset_data vset_data;
+ unsigned int vol_numb;
+ unsigned int *vset_table;
+ struct regulator_desc rdesc;
+ int (*dt_parse)(struct hi655x_regulator*, struct platform_device*);
+};
+
+static int hi655x_regulator_pmic_is_enabled(struct regulator_dev *rdev)
+{
+ int ret = 0;
+ unsigned char value_u8 = 0;
+
+ struct hi655x_regulator *sreg = rdev_get_drvdata(rdev);
+ struct hi655x_regulator_ctrl_regs *ctrl_regs = &(sreg->ctrl_regs);
+ struct hi655x_regulator_ctrl_data *ctrl_data = &(sreg->ctrl_data);
+
+ /*
+ * regulator is all set,but the pmu is only subset.
+ * maybe this "buck"/"ldo"/"lvs" is not contrl by a core.
+ * and in regulator have a "status" member ("okey" or "disable").
+ */
+ value_u8 = hi655x_pmic_reg_read(ctrl_regs->status_reg);
+ ret = ((int)BSP_REG_GETBITS(&value_u8, 0, ctrl_data->shift, ctrl_data->mask) & 0xff);
+
+ return ret;
+}
+
+static int hi655x_regulator_pmic_enable(struct regulator_dev *rdev)
+{
+ int ret = 0;
+ unsigned char value_u8 = 0;
+ unsigned int value_u32 = 0;
+ struct hi655x_regulator *sreg = rdev_get_drvdata(rdev);
+ struct hi655x_regulator_ctrl_regs *ctrl_regs = &(sreg->ctrl_regs);
+ struct hi655x_regulator_ctrl_data *ctrl_data = &(sreg->ctrl_data);
+
+ BSP_REG_SETBITS(&value_u32, 0, ctrl_data->shift, ctrl_data->mask, 0x1);
+ value_u8 = (unsigned char)value_u32;
+ hi655x_pmic_reg_write(ctrl_regs->enable_reg, value_u8);
+ udelay(sreg->off_on_delay);
+
+ return ret;
+}
+
+static int hi655x_regulator_pmic_disable(struct regulator_dev *rdev)
+{
+ int ret = 0;
+ int flag = 1;
+ unsigned char value_u8 = 0;
+ unsigned int value_u32 = 0;
+
+ struct hi655x_regulator *sreg = rdev_get_drvdata(rdev);
+ struct hi655x_regulator_ctrl_regs *ctrl_regs = &(sreg->ctrl_regs);
+ struct hi655x_regulator_ctrl_data *ctrl_data = &(sreg->ctrl_data);
+
+ /*
+ * regulator is all set,but the pmu is only subset.
+ * maybe this "buck"/"ldo"/"lvs" is not contrl by a core.
+ * and in regulator have a "status" member (okey or disable).
+ * maybe we can del some regulator which is not contrl by core.
+ */
+ if (sreg->type == PMIC_BOOST_TYPE)
+ flag = 0;
+
+ BSP_REG_SETBITS(&value_u32, 0, ctrl_data->shift, ctrl_data->mask, flag);
+ value_u8 = (unsigned char)value_u32;
+ hi655x_pmic_reg_write(ctrl_regs->disable_reg, value_u8);
+
+ return ret;
+}
+
+static int hi655x_regulator_pmic_list_voltage_linear(struct regulator_dev *rdev,
+ unsigned int selector)
+{
+ struct hi655x_regulator *sreg = rdev_get_drvdata(rdev);
+ /*
+ * regulator is all set,but the pmu is only subset.
+ * maybe this "buck"/"ldo"/"lvs" is not contrl by a core.
+ * and in regulator have a "status" member (okey or disable).
+ * maybe we can del some regulator which is not contrl by core.
+ * we will return min_uV
+ */
+ if (sreg->type == PMIC_LVS_TYPE)
+ return 900000;
+
+ if (selector >= sreg->vol_numb) {
+ printk("selector err %s %d \n", __func__, __LINE__);
+ return -1;
+ }
+
+ return sreg->vset_table[selector];
+}
+
+static int hi655x_regulator_pmic_get_voltage(struct regulator_dev *rdev)
+{
+ int index = 0;
+ unsigned int value_u32 = 0;
+ struct hi655x_regulator *sreg = rdev_get_drvdata(rdev);
+ struct hi655x_regulator_vset_regs *vset_regs = &(sreg->vset_regs);
+ struct hi655x_regulator_vset_data *vset_data = &(sreg->vset_data);
+
+ if (sreg->type == PMIC_LVS_TYPE)
+ return 900000;
+
+ value_u32 = (unsigned int)hi655x_pmic_reg_read(vset_regs->vset_reg) & 0xff;
+ index = ((unsigned int)BSP_REG_GETBITS(&value_u32, 0, vset_data->shift, vset_data->mask) & 0xff);
+
+ return sreg->vset_table[index];
+}
+
+static int hi655x_regulator_pmic_set_voltage(struct regulator_dev *rdev,
+ int min_uV, int max_uV, unsigned *selector)
+{
+ int i = 0;
+ int ret = 0;
+ int vol = 0;
+ unsigned char value_u8 = 0;
+ unsigned int value_u32 = 0;
+
+ struct hi655x_regulator *sreg = rdev_get_drvdata(rdev);
+ struct hi655x_regulator_vset_regs *vset_regs = &(sreg->vset_regs);
+ struct hi655x_regulator_vset_data *vset_data = &(sreg->vset_data);
+
+ if (sreg->type == PMIC_LVS_TYPE)
+ return 0;
+ /*
+ * search the matched vol and get its index
+ */
+ for (i = 0; i < sreg->vol_numb; i++) {
+ vol = sreg->vset_table[i];
+
+ if ((vol >= min_uV) && (vol <= max_uV))
+ break;
+ }
+
+ if (i == sreg->vol_numb)
+ return -1;
+
+ value_u32 = (unsigned int)hi655x_pmic_reg_read(vset_regs->vset_reg) & 0xff;
+ BSP_REG_SETBITS(&value_u32, 0, vset_data->shift, vset_data->mask, i);
+ value_u8 = (unsigned char)value_u32;
+ hi655x_pmic_reg_write(vset_regs->vset_reg, value_u8);
+
+ *selector = i;
+
+ return ret;
+}
+
+static unsigned int hi655x_regulator_pmic_get_mode(struct regulator_dev *rdev)
+{
+ return REGULATOR_MODE_NORMAL;
+}
+
+static int hi655x_regulator_pmic_set_mode(struct regulator_dev *rdev,
+ unsigned int mode)
+{
+ return 0;
+}
+
+static unsigned int hi655x_regulator_pmic_get_optimum_mode(struct regulator_dev *rdev,
+ int input_uV, int output_uV, int load_uA)
+{
+ return REGULATOR_MODE_NORMAL;
+}
+
+static int hi655x_set_current_limit(struct regulator_dev *rdev,
+ int min_uA, int max_uA)
+{
+ return 0;
+}
+
+static int hi655x_get_current_limit(struct regulator_dev *rdev)
+{
+ return 0;
+}
+
+static struct regulator_ops hi655x_regulator_pmic_rops = {
+ .is_enabled = hi655x_regulator_pmic_is_enabled,
+ .enable = hi655x_regulator_pmic_enable,
+ .disable = hi655x_regulator_pmic_disable,
+ .list_voltage = hi655x_regulator_pmic_list_voltage_linear,
+ .get_voltage = hi655x_regulator_pmic_get_voltage,
+ .set_voltage = hi655x_regulator_pmic_set_voltage,
+ .get_mode = hi655x_regulator_pmic_get_mode,
+ .set_mode = hi655x_regulator_pmic_set_mode,
+ .get_optimum_mode = hi655x_regulator_pmic_get_optimum_mode,
+ .set_current_limit = hi655x_set_current_limit,
+ .get_current_limit = hi655x_get_current_limit,
+};
+
+static int hi655x_regualtor_dt_parse_common(struct hi655x_regulator *sreg,
+ struct platform_device *pdev)
+{
+ return 0;
+}
+
+static int hi655x_regualtor_pmic_dt_parse(struct hi655x_regulator *sreg,
+ struct platform_device *pdev)
+{
+ int ret;
+ ret = hi655x_regualtor_dt_parse_common(sreg, pdev);
+
+ return ret;
+}
+
+static const struct hi655x_regulator hi655x_regulator_pmic = {
+ .rdesc = {
+ .ops = &hi655x_regulator_pmic_rops,
+ .type = REGULATOR_VOLTAGE,
+ .owner = THIS_MODULE,
+ },
+ .dt_parse = hi655x_regualtor_pmic_dt_parse,
+};
+
+static struct of_device_id of_hi655x_regulator_match_tbl[] = {
+ {
+ .compatible = "hisilicon,hi6552-regulator-pmic",
+ .data = &hi655x_regulator_pmic,
+ },
+ { /* end */ }
+};
+
+static struct regulator_init_data *fake_of_get_regulator_init_data(struct device *dev,
+ struct device_node *np)
+{
+ struct regulator_init_data *init_data = NULL;
+ const __be32 *num_consumer_supplies = NULL;
+ struct regulator_consumer_supply *consumer_supplies = NULL;
+ int consumer_id = 0;
+
+ init_data = devm_kzalloc(dev, sizeof(*init_data), GFP_KERNEL);
+ if (!init_data)
+ return NULL;
+
+ init_data->supply_regulator = of_get_property(np, "hisilicon,regulator-supply", NULL);
+
+ num_consumer_supplies = of_get_property(np, "hisilicon,num_consumer_supplies", NULL);
+ if ((NULL == num_consumer_supplies) || (0 == *num_consumer_supplies)) {
+ dev_warn(dev, "%s no consumer_supplies \n", __func__);
+ return init_data;
+ }
+
+ init_data->num_consumer_supplies = be32_to_cpu(*num_consumer_supplies);
+ init_data->consumer_supplies = (struct regulator_consumer_supply *)devm_kzalloc(dev,
+ init_data->num_consumer_supplies * sizeof(struct regulator_consumer_supply), GFP_KERNEL);
+ if (NULL == init_data->consumer_supplies) {
+ dev_err(dev, "%s devm_kzalloc consumer_supplies err\n", __func__);
+ return NULL;
+ }
+
+ consumer_supplies = init_data->consumer_supplies ;
+
+ for (consumer_id = 0; consumer_id < init_data->num_consumer_supplies;
+ consumer_id++, consumer_supplies++) {
+ int ret = of_property_read_string_index(np, "hisilicon,consumer-supplies", consumer_id, &consumer_supplies->supply);
+ if (ret)
+ dev_err(dev, "\n %s of_property_read_string_index consumer-supplies err\n", np->name);
+ }
+
+ return init_data;
+}
+
+static int fake_of_get_regulator_constraint(struct regulation_constraints *constraints,
+ struct device_node *np)
+{
+ const __be32 *min_uV, *max_uV;
+ unsigned int *valid_modes_mask;
+ unsigned int *valid_ops_mask;
+ unsigned int *initial_mode;
+
+ if (!np)
+ return -1;
+
+ if (!constraints)
+ return -1;
+
+ constraints->name = of_get_property(np, "regulator-name", NULL);
+
+ min_uV = of_get_property(np, "regulator-min-microvolt", NULL);
+ if (min_uV) {
+ (constraints)->min_uV = be32_to_cpu(*min_uV);
+ (constraints)->min_uA = be32_to_cpu(*min_uV);
+ }
+
+ max_uV = of_get_property(np, "regulator-max-microvolt", NULL);
+ if (max_uV) {
+ constraints->max_uV = be32_to_cpu(*max_uV);
+ constraints->max_uA = be32_to_cpu(*max_uV);
+ }
+
+ valid_modes_mask = (unsigned int *)of_get_property(np, "hisilicon,valid-modes-mask", NULL);
+ if (valid_modes_mask)
+ constraints->valid_modes_mask = be32_to_cpu(*valid_modes_mask);
+
+ valid_ops_mask = (unsigned int *)of_get_property(np, "hisilicon,valid-ops-mask", NULL);
+ if (valid_ops_mask)
+ constraints->valid_ops_mask = be32_to_cpu(*valid_ops_mask);
+
+ initial_mode = (unsigned int *)of_get_property(np, "hisilicon,initial-mode", NULL);
+ if (initial_mode)
+ constraints->initial_mode = be32_to_cpu(*initial_mode);
+
+ constraints->always_on = !!(of_find_property(np, "regulator-always-on", NULL));
+
+ constraints->boot_on = !!(of_find_property(np, "regulator-boot-on", NULL));
+
+ return 0;
+}
+
+static int fake_of_get_regulator_sreg(struct hi655x_regulator *sreg, struct device *dev,
+ struct device_node *np)
+{
+ int *vol_numb;
+ unsigned int *off_on_delay;
+ enum hi655x_regulator_type *regulator_type;
+ const char *status = NULL;
+ unsigned int *vset_table = NULL;
+ int *regulator_id;
+
+ status = of_get_property(np, "hisilicon,regulator-status", NULL);
+ if (status)
+ sreg->status = !(strcmp(status, "okey"));
+
+ regulator_type = (enum hi655x_regulator_type *)of_get_property(np, "hisilicon,regulator-type", NULL);
+ if (regulator_type)
+ sreg->type = be32_to_cpu(*regulator_type);
+
+ off_on_delay = (unsigned int *)of_get_property(np, "hisilicon,off-on-delay", NULL);
+ if (off_on_delay)
+ sreg->off_on_delay = be32_to_cpu(*off_on_delay);
+
+ of_property_read_u32_array(np, "hisilicon,ctrl-regs", (unsigned int *)(&sreg->ctrl_regs), 0x3);
+
+ of_property_read_u32_array(np, "hisilicon,ctrl-data", (unsigned int *)(&sreg->ctrl_data), 0x2);
+
+ of_property_read_u32_array(np, "hisilicon,vset-regs", (unsigned int *)(&sreg->vset_regs), 0x1);
+
+ of_property_read_u32_array(np, "hisilicon,vset-data", (unsigned int *)(&sreg->vset_data), 0x2);
+
+ vol_numb = (int *)of_get_property(np, "hisilicon,regulator-n-vol", NULL);
+ if (vol_numb)
+ sreg->vol_numb = be32_to_cpu(*vol_numb);
+
+ regulator_id = (int *)of_get_property(np, "hisilicon,hisi-scharger-regulator-id", NULL);
+ if (regulator_id)
+ sreg->regulator_id = be32_to_cpu(*regulator_id);
+
+ vset_table = devm_kzalloc(dev, sreg->vol_numb * sizeof(int), GFP_KERNEL);
+ if (!vset_table)
+ return -1;
+
+ of_property_read_u32_array(np, "hisilicon,vset-table", (unsigned int *)vset_table, sreg->vol_numb);
+ sreg->vset_table = vset_table;
+
+ return 0;
+}
+
+static int hi655x_regulator_probe(struct platform_device *pdev)
+{
+ int ret = 0;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct regulator_dev *rdev = NULL;
+ struct regulator_desc *rdesc = NULL;
+ struct hi655x_regulator *sreg = NULL;
+ struct regulator_init_data *initdata = NULL;
+ const struct of_device_id *match = NULL;
+ const struct hi655x_regulator *template = NULL;
+ struct regulator_config config = { };
+
+ /* to check which type of regulator this is */
+ match = of_match_device(of_hi655x_regulator_match_tbl, &pdev->dev);
+
+ if (NULL == match) {
+ dev_err(dev, "of match hi655x regulator fail!\n\r");
+ return -EINVAL;
+ }
+
+ /*tempdev is regulator device*/
+ template = match->data;
+
+ /*just for getting "std regulator node" value-key about constraint*/
+ initdata = fake_of_get_regulator_init_data(dev, np);
+ if (!initdata) {
+ dev_err(dev, "get regulator init data error !\n");
+ return -EINVAL;
+ }
+
+ ret = fake_of_get_regulator_constraint(&initdata->constraints, np);
+ if (!!ret) {
+ dev_err(dev, "get regulator constraint error !\n");
+ return -EINVAL;
+ }
+
+ /* TODO:hi655x regulator supports two modes */
+ sreg = kmemdup(template, sizeof(*sreg), GFP_KERNEL);
+ if (!sreg)
+ return -ENOMEM;
+
+ if (0 != fake_of_get_regulator_sreg(sreg, dev, np)) {
+ kfree(sreg);
+ return -EINVAL;
+ }
+
+ rdesc = &sreg->rdesc;
+ rdesc->n_voltages = sreg->vol_numb;
+ rdesc->name = initdata->constraints.name;
+ rdesc->id = sreg->regulator_id;
+ rdesc->min_uV = initdata->constraints.min_uV;
+
+ /* to parse device tree data for regulator specific */
+ config.dev = &pdev->dev;
+ config.init_data = initdata;
+ config.driver_data = sreg;
+ config.of_node = pdev->dev.of_node;
+
+ /* register regulator */
+ rdev = regulator_register(rdesc, &config);
+ if (IS_ERR(rdev)) {
+ dev_err(dev, "regulator failed to register %s\n", rdesc->name);
+ ret = PTR_ERR(rdev);
+ return -EINVAL;
+ }
+
+ platform_set_drvdata(pdev, rdev);
+
+ return ret;
+}
+
+static int hi655x_regulator_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static struct platform_driver hi655x_regulator_driver = {
+ .driver = {
+ .name = "hi655x_regulator",
+ .owner = THIS_MODULE,
+ .of_match_table = of_hi655x_regulator_match_tbl,
+ },
+ .probe = hi655x_regulator_probe,
+ .remove = hi655x_regulator_remove,
+};
+
+static int __init hi655x_regulator_init(void)
+{
+ return platform_driver_register(&hi655x_regulator_driver);
+}
+
+static void __exit hi655x_regulator_exit(void)
+{
+ platform_driver_unregister(&hi655x_regulator_driver);
+}
+
+fs_initcall(hi655x_regulator_init);
+module_exit(hi655x_regulator_exit);
+
+MODULE_AUTHOR("Dongbin Yu <yudongbin@huawei.com>");
+MODULE_DESCRIPTION("Hisilicon HI655X PMIC regulator driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/dt-bindings/pinctrl/hisi.h b/include/dt-bindings/pinctrl/hisi.h
new file mode 100644
index 000000000000..38f1ea879ea1
--- /dev/null
+++ b/include/dt-bindings/pinctrl/hisi.h
@@ -0,0 +1,59 @@
+/*
+ * This header provides constants for hisilicon pinctrl bindings.
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ * Copyright (c) 2015 Linaro Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_HISI_H
+#define _DT_BINDINGS_PINCTRL_HISI_H
+
+/* iomg bit definition */
+#define MUX_M0 0
+#define MUX_M1 1
+#define MUX_M2 2
+#define MUX_M3 3
+#define MUX_M4 4
+#define MUX_M5 5
+#define MUX_M6 6
+#define MUX_M7 7
+
+/* iocg bit definition */
+#define PULL_MASK (3)
+#define PULL_DIS (0)
+#define PULL_UP (1 << 0)
+#define PULL_DOWN (1 << 1)
+
+/* drive strength definition */
+#define DRIVE_MASK (7 << 4)
+#define DRIVE1_02MA (0 << 4)
+#define DRIVE1_04MA (1 << 4)
+#define DRIVE1_08MA (2 << 4)
+#define DRIVE1_10MA (3 << 4)
+#define DRIVE2_02MA (0 << 4)
+#define DRIVE2_04MA (1 << 4)
+#define DRIVE2_08MA (2 << 4)
+#define DRIVE2_10MA (3 << 4)
+#define DRIVE3_04MA (0 << 4)
+#define DRIVE3_08MA (1 << 4)
+#define DRIVE3_12MA (2 << 4)
+#define DRIVE3_16MA (3 << 4)
+#define DRIVE3_20MA (4 << 4)
+#define DRIVE3_24MA (5 << 4)
+#define DRIVE3_32MA (6 << 4)
+#define DRIVE3_40MA (7 << 4)
+#define DRIVE4_02MA (0 << 4)
+#define DRIVE4_04MA (2 << 4)
+#define DRIVE4_08MA (4 << 4)
+#define DRIVE4_10MA (6 << 4)
+
+#endif
diff --git a/include/linux/mfd/hi6552_pmic.h b/include/linux/mfd/hi6552_pmic.h
new file mode 100644
index 000000000000..91f75dd21003
--- /dev/null
+++ b/include/linux/mfd/hi6552_pmic.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2015 Hisilicon Co. Ltd.
+ *
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __PMUSSI_DRV_H
+#define __PMUSSI_DRV_H
+
+#define HI6552_BITS (8)
+
+/*numb of sub-interrupt*/
+#define HI6552_NR_IRQ (32)
+
+#define HI6552_IRQ_STAT_BASE (0x003)
+#define HI6552_IRQ_MASK_BASE (0x007)
+#define HI6552_IRQ_ARRAY (4)
+#define HI6552_IRQ_MASK (0xFF)
+#define HI6552_IRQ_CLR (0xFF)
+
+#define HI6552_VER_REG (0x000)
+#define HI6552_REG_WIDTH (0xFF)
+
+#define PMU_VER_START 0x10
+#define PMU_VER_END 0x38
+
+#define SSI_DEVICE_OK 1
+#define SSI_DEVICE_ERR 0
+
+#define PMUSSI_REG_EX(pmu_base, reg_addr) (((reg_addr) << 2) + (char *)pmu_base)
+
+unsigned char hi6552_pmic_reg_read(unsigned int addr);
+void hi6552_pmic_reg_write(unsigned int addr, unsigned char val);
+unsigned char hi6552_pmic_reg_read_ex(void *pmu_base, unsigned int addr);
+void hi6552_pmic_reg_write_ex (void *pmu_base, unsigned int addr, unsigned char val);
+int *hi6552_pmic_get_buck_vol_table(int id);
+unsigned int hi6552_pmic_get_version(void);
+int hi6552_pmic_device_stat_notify(char *dev_name, int dev_stat);
+
+#endif
diff --git a/include/linux/mfd/hi655x-pmic.h b/include/linux/mfd/hi655x-pmic.h
new file mode 100644
index 000000000000..bd66f7f74727
--- /dev/null
+++ b/include/linux/mfd/hi655x-pmic.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2015 Hisilicon Co. Ltd.
+ *
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __PMUSSI_DRV_H
+#define __PMUSSI_DRV_H
+
+#define HI655x_BITS (8)
+
+/*numb of sub-interrupt*/
+#define HI655x_NR_IRQ (32)
+
+#define HI655x_IRQ_STAT_BASE (0x003)
+#define HI655x_IRQ_MASK_BASE (0x007)
+#define HI655x_IRQ_ARRAY (4)
+#define HI655x_IRQ_MASK (0xFF)
+#define HI655x_IRQ_CLR (0xFF)
+
+#define HI655x_VER_REG (0x000)
+#define HI655x_REG_WIDTH (0xFF)
+
+#define PMU_VER_START 0x10
+#define PMU_VER_END 0x38
+
+#define SSI_DEVICE_OK 1
+#define SSI_DEVICE_ERR 0
+
+#define PMUSSI_REG_EX(pmu_base, reg_addr) (((reg_addr) << 2) + (char *)pmu_base)
+
+unsigned char hi655x_pmic_reg_read(unsigned int addr);
+void hi655x_pmic_reg_write(unsigned int addr, unsigned char val);
+unsigned char hi655x_pmic_reg_read_ex(void *pmu_base, unsigned int addr);
+void hi655x_pmic_reg_write_ex (void *pmu_base, unsigned int addr, unsigned char val);
+int *hi655x_pmic_get_buck_vol_table(int id);
+unsigned int hi655x_pmic_get_version(void);
+int hi655x_pmic_device_stat_notify(char *dev_name, int dev_stat);
+
+#endif
diff --git a/include/linux/regulator/hi655x-regulator.h b/include/linux/regulator/hi655x-regulator.h
new file mode 100644
index 000000000000..3398d7efab6d
--- /dev/null
+++ b/include/linux/regulator/hi655x-regulator.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2015 Hisilicon Co. Ltd.
+ *
+ */
+
+#ifndef __HISI_HI655X_REGULATOR_H__
+#define __HISI_HI655X_REGULATOR_H__
+
+enum hi655x_regulator_type {
+ PMIC_BUCK_TYPE = 0,
+ PMIC_LDO_TYPE = 1,
+ PMIC_LVS_TYPE = 2,
+ PMIC_BOOST_TYPE = 3,
+ MTCMOS_SC_ON_TYPE = 4,
+ MTCMOS_ACPU_ON_TYPE = 5,
+ SCHARGE_TYPE = 6,
+};
+
+struct hi655x_regulator_ctrl_regs {
+ unsigned int enable_reg;
+ unsigned int disable_reg;
+ unsigned int status_reg;
+};
+
+struct hi655x_regulator_vset_regs {
+ unsigned int vset_reg;
+};
+
+struct hi655x_regulator_ctrl_data {
+ int shift;
+ unsigned int mask;
+};
+
+struct hi655x_regulator_vset_data {
+ int shift;
+ unsigned int mask;
+};
+
+#endif