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// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP Mini Configuration
*
* (C) Copyright 2018, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
*/
/dts-v1/;
/ {
model = "ZynqMP MINI EMMC0";
compatible = "xlnx,zynqmp";
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &dcc;
mmc0 = &sdhci0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x20000000>;
};
dcc: dcc {
compatible = "arm,dcc";
status = "disabled";
u-boot,dm-pre-reloc;
};
clk_xin: clk_xin {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
firmware {
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
#power-domain-cells = <1>;
method = "smc";
u-boot,dm-pre-reloc;
zynqmp_power: zynqmp-power {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-power";
mboxes = <&ipi_mailbox_pmu1 0>,
<&ipi_mailbox_pmu1 1>;
mbox-names = "tx", "rx";
};
};
};
zynqmp_ipi: zynqmp_ipi {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-ipi-mailbox";
xlnx,ipi-id = <0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
ipi_mailbox_pmu1: mailbox@ff990400 {
u-boot,dm-pre-reloc;
reg = <0x0 0xff9905c0 0x0 0x20>,
<0x0 0xff9905e0 0x0 0x20>,
<0x0 0xff990e80 0x0 0x20>,
<0x0 0xff990ea0 0x0 0x20>;
reg-names = "local_request_region",
"local_response_region",
"remote_request_region",
"remote_response_region";
#mbox-cells = <1>;
xlnx,ipi-id = <4>;
};
};
amba: amba {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
sdhci0: sdhci@ff160000 {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
non-removable;
bus-width = <8>;
reg = <0x0 0xff160000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&clk_xin &clk_xin>;
xlnx,device_id = <0>;
};
};
};
&dcc {
status = "okay";
};
&sdhci0 {
status = "okay";
};
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