diff options
author | Christopher Collins <ccollins@apache.org> | 2016-08-23 17:35:28 -0700 |
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committer | Christopher Collins <ccollins@apache.org> | 2016-08-23 17:35:28 -0700 |
commit | 70987f7d2e3c791132509f08566fe77de34142ac (patch) | |
tree | 269ca9b857f65c22b8f2b93560466984f96091e5 /hw/bsp/stm32f4discovery/f407.cfg | |
parent | 0d9c8f30efbe2dba00b21d9185e9db8e36cd579e (diff) | |
parent | 665e22f5722d6348c1b260192e27f69d855b58fd (diff) |
Merge branch 'develop' - in preparation for
backwards-compatibility-breaking changes to develop.
* develop: (290 commits)
sim compiler - replace objsize with size
Fix warnings reported by clang.
MYNEWT-329
MYNEWT-354
STM32f407 discovery board BSP
mbedtls; use smaller version of SHA256.
boot; boot loader does not need to call os_init() anymore, as bsp_init() has been exported.
boot; app does not need the dependency to mbedtls
slinky; time-based waits must use OS_TICKS_PER_SEC.
bootutil; adjust unit tests to work with status upkeep outside sys/config.
bootutil; was returning wrong image header in response when swithing images. Add boot_set_req() routine for unit test use.
boot/bootutil; remove debug console use from bootloader.
bootutil/imgmgr; output of boot now shows the fallback image.
imgmgr; automatically confirm image as good for now.
bootutil; add 'confirm' step, telling that image was confirmed as good. Otherwise next restart we'll go back to old image.
bootutil; make status element size depend on flash alignment restrictions.
boot, imgmgr; return the slot number for test image.
bootutil; move routines reading boot-copy-status from loader.c to bootutil_misc.c.
boot; return full flash location of status bytes, instead of just offset.
boot; don't use NFFS or FCB for keeping status. Interim commit.
...
Diffstat (limited to 'hw/bsp/stm32f4discovery/f407.cfg')
-rw-r--r-- | hw/bsp/stm32f4discovery/f407.cfg | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/hw/bsp/stm32f4discovery/f407.cfg b/hw/bsp/stm32f4discovery/f407.cfg new file mode 100644 index 00000000..7c46d8ba --- /dev/null +++ b/hw/bsp/stm32f4discovery/f407.cfg @@ -0,0 +1,82 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +# script for stm32f4x family + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32f4x +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +# By default use 64kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x10000 +} + +# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz +# +# Since we may be running of an RC oscilator, we crank down the speed a +# bit more to be on the safe side. Perhaps superstition, but if are +# running off a crystal, we can run closer to the limit. Note +# that there can be a pretty wide band where things are more or less stable. +adapter_khz 1000 + +adapter_nsrst_delay 100 +jtag_ntrst_delay 100 + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # See STM Document RM0090 + # Section 32.6.2 - corresponds to Cortex-M4 r0p1 + set _CPUTAPID 0x4ba00477 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +if { [info exists BSTAPID] } { + set _BSTAPID $BSTAPID +} else { + # See STM Document RM0090 + # Section 32.6.3 + set _BSTAPID 0x06413041 +} +jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME + +# if srst is not fitted use SYSRESETREQ to +# perform a soft reset +cortex_m3 reset_config sysresetreq |