diff options
author | Jose Marinho <jose.marinho@arm.com> | 2021-07-29 15:17:28 +0100 |
---|---|---|
committer | Jose Marinho <jose.marinho@arm.com> | 2021-07-30 09:52:18 +0100 |
commit | 62eb3d181651ccfe38bce980caef931009367cfc (patch) | |
tree | 1b1837e08c5498b1b06d98659c60952c8b9d64f8 | |
parent | 4ec637200bdaed9a4ba62caff9c17f928914fd61 (diff) |
Enable A/B FIP in the qemu platform
-rw-r--r-- | drivers/auth/auth_mod.c | 2 | ||||
-rw-r--r-- | plat/qemu/common/qemu_io_storage.c | 57 | ||||
-rw-r--r-- | plat/qemu/qemu/include/platform_def.h | 4 | ||||
-rw-r--r-- | plat/qemu/qemu/platform.mk | 3 |
4 files changed, 62 insertions, 4 deletions
diff --git a/drivers/auth/auth_mod.c b/drivers/auth/auth_mod.c index 26d03d3b0..917ee4a28 100644 --- a/drivers/auth/auth_mod.c +++ b/drivers/auth/auth_mod.c @@ -287,7 +287,7 @@ static int auth_nvctr(const auth_method_param_nv_ctr_t *param, return 1; } else if (*cert_nv_ctr > plat_nv_ctr) { #if PSA_FWU_SUPPORT && IMAGE_BL2 - is_trial_run = fwu_metadata_is_trial_run_state(); + is_trial_run = fwu_is_trial_run_state(); #endif /* PSA_FWU_SUPPORT && IMAGE_BL2 */ *need_nv_ctr_upgrade = !is_trial_run; } diff --git a/plat/qemu/common/qemu_io_storage.c b/plat/qemu/common/qemu_io_storage.c index 1107e443f..f777501ed 100644 --- a/plat/qemu/common/qemu_io_storage.c +++ b/plat/qemu/common/qemu_io_storage.c @@ -9,6 +9,7 @@ #include <platform_def.h> +#include <drivers/fwu/fwu_metadata.h> #include <common/bl_common.h> #include <common/debug.h> #include <drivers/io/io_driver.h> @@ -53,11 +54,16 @@ static const io_dev_connector_t *enc_dev_con; static uintptr_t enc_dev_handle; #endif -static const io_block_spec_t fip_block_spec = { +static io_block_spec_t fip_block_spec = { .offset = PLAT_QEMU_FIP_BASE, .length = PLAT_QEMU_FIP_MAX_SIZE }; +static io_block_spec_t metadata_block_spec = { + .offset = 0x600000, + .length = 0x1000 +}; + static const io_uuid_spec_t bl2_uuid_spec = { .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2, }; @@ -206,6 +212,11 @@ static const struct plat_io_policy policies[] = { (uintptr_t)&bl2_uuid_spec, open_fip }, + [FWU_METADATA_IMAGE_ID] = { + &memmap_dev_handle, + (uintptr_t)&metadata_block_spec, + open_memmap + }, #if ENCRYPT_BL31 && !defined(DECRYPTION_SUPPORT_none) [BL31_IMAGE_ID] = { &enc_dev_handle, @@ -301,6 +312,50 @@ static const struct plat_io_policy policies[] = { #endif /* TRUSTED_BOARD_BOOT */ }; +int plat_fwu_set_metadata_image_source(unsigned int image_id, + uintptr_t *handle, + uintptr_t *image_spec) +{ + int result = -1; + struct plat_io_policy const *policy; + + assert((image_id == FWU_METADATA_IMAGE_ID) || + (image_id == BKUP_FWU_METADATA_IMAGE_ID)); + + policy = &policies[FWU_METADATA_IMAGE_ID]; + + if (image_id == FWU_METADATA_IMAGE_ID) + metadata_block_spec.offset = 0x600000; + else + metadata_block_spec.offset = 0x680000; + + *image_spec = (uintptr_t)&metadata_block_spec; + *handle = *policy->dev_handle; + + result = 0; + + return result; +} + +/* + * Select FIP A or FIP B depending on the active_index value in the metadata. + * TODO: Obtain the offset to set in the image spec based on the GPT information. + */ +void plat_fwu_set_images_source(struct fwu_metadata *metadata) +{ + uint32_t active_idx; + + active_idx = metadata->active_index; + + if (active_idx == 0) { + INFO("FIP A selected\n"); + fip_block_spec.offset = PLAT_QEMU_FIP_BASE_A; + } else { + INFO("FIP B selected\n"); + fip_block_spec.offset = PLAT_QEMU_FIP_BASE_B; + } +} + static int open_fip(const uintptr_t spec) { int result; diff --git a/plat/qemu/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h index fbcaa63a8..0e4b5df0a 100644 --- a/plat/qemu/qemu/include/platform_def.h +++ b/plat/qemu/qemu/include/platform_def.h @@ -210,6 +210,8 @@ #define QEMU_FLASH1_SIZE 0x04000000 #define PLAT_QEMU_FIP_BASE 0x00040000 +#define PLAT_QEMU_FIP_BASE_A PLAT_QEMU_FIP_BASE +#define PLAT_QEMU_FIP_BASE_B 0x00280000 #define PLAT_QEMU_FIP_MAX_SIZE 0x00400000 #define DEVICE0_BASE 0x08000000 @@ -220,12 +222,10 @@ /* * GIC related constants */ - #define GICD_BASE 0x8000000 #define GICC_BASE 0x8010000 #define GICR_BASE 0x80A0000 - #define QEMU_IRQ_SEC_SGI_0 8 #define QEMU_IRQ_SEC_SGI_1 9 #define QEMU_IRQ_SEC_SGI_2 10 diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk index a3b353f74..321516aff 100644 --- a/plat/qemu/qemu/platform.mk +++ b/plat/qemu/qemu/platform.mk @@ -69,6 +69,7 @@ ifneq (${TRUSTED_BOARD_BOOT},0) drivers/auth/tbbr/tbbr_cot_bl1.c BL2_SOURCES += ${AUTH_SOURCES} \ + drivers/fwu/fwu.c \ plat/common/tbbr/plat_tbbr.c \ ${PLAT_QEMU_COMMON_PATH}/qemu_trusted_boot.c \ $(PLAT_QEMU_COMMON_PATH)/qemu_rotpk.S \ @@ -200,6 +201,8 @@ ifneq ($(ENABLE_STACK_PROTECTOR), 0) PLAT_BL_COMMON_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_stack_protector.c endif +PSA_FWU_SUPPORT := 1 + BL32_RAM_LOCATION := tdram ifeq (${BL32_RAM_LOCATION}, tsram) BL32_RAM_LOCATION_ID = SEC_SRAM_ID |