diff options
| author | Olivier Masse <olivier.masse@nxp.com> | 2021-02-11 12:11:23 +0100 |
|---|---|---|
| committer | lei zhou <lei.zhou@linaro.org> | 2022-11-28 16:09:17 -0500 |
| commit | 816b5a6dd63fad7937928e50857c51bdde3f3b11 (patch) | |
| tree | 587ddcd33a8c94848c77520c48870f8eb3af0ff2 | |
| parent | a6a0df986b5f89f2b2072122afba050cbbed897f (diff) | |
MMIOT-193 : Setup CSU: VPU access in TZ only
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
| -rw-r--r-- | plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c index 69e0cfa2e..73c3859e7 100644 --- a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c +++ b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c @@ -166,6 +166,20 @@ static const struct imx_rdc_cfg rdc_cfg[] = { }; #endif +static const struct imx_csu_cfg csu_cfg_conf[] = { + /* peripherals csl setting */ +#ifdef CFG_SECURE_HANTRO_VPU + CSU_CSLx(CSU_CSL_VPU_SEC, CSU_SEC_LEVEL_4, LOCKED), +#endif + /* master HP0~1 */ + + /* SA setting */ + + /* HP control setting */ + + /* Sentinel */ + {0} +}; /* set RDC settings */ static void bl31_imx_rdc_setup(void) @@ -226,6 +240,10 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff); } +#if !defined (CSU_RDC_TEST) + imx_csu_init(csu_cfg_conf); +#endif + imx_aipstz_init(aipstz); imx8m_caam_init(); |