path: root/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c

/*
 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#include <assert.h>
#include <stdbool.h>

#include <platform_def.h>

#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <context.h>
#include <drivers/arm/tzc380.h>
#include <drivers/console.h>
#include <drivers/generic_delay_timer.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/mmio.h>
#ifdef IMX_ANDROID_BUILD
#include <lib/xlat_tables/xlat_tables.h>
#else
#include <lib/xlat_tables/xlat_tables_v2.h>
#endif
#include <plat/common/platform.h>

#include <dram.h>
#include <gpc.h>
#include <imx_aipstz.h>
#include <imx_uart.h>
#include <imx_rdc.h>
#include <imx8m_caam.h>
#include <imx8m_csu.h>
#include <imx8m_snvs.h>
#include <plat_imx8.h>

#define TRUSTY_PARAMS_LEN_BYTES      (4096*2)

static const mmap_region_t imx_mmap[] = {
	MAP_REGION_FLAT(GPV_BASE, GPV_SIZE, MT_DEVICE | MT_RW), /* GPV map */
	MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM map */
	MAP_REGION_FLAT(OCRAM_S_BASE, OCRAM_S_SIZE, MT_MEMORY | MT_RW), /* ROM map */
	MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */
	MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), /* GIC map */
	MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW), /* DDRMIX map */
	MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
	MAP_REGION_FLAT(IMX_CAAM_RAM_BASE, IMX_CAAM_RAM_SIZE, MT_MEMORY | MT_RW), /* CAMM RAM */
	MAP_REGION_FLAT(IMX_NS_OCRAM_BASE, IMX_NS_OCRAM_SIZE, MT_MEMORY | MT_RW), /* NS OCRAM */
	MAP_REGION_FLAT(IMX_TCM_BASE, IMX_TCM_SIZE, MT_MEMORY | MT_RW | MT_NS), /* TCM */
	{0},
};

static const struct aipstz_cfg aipstz[] = {
	{AIPSTZ1_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
	{AIPSTZ2_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
	{AIPSTZ3_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
	{AIPSTZ4_BASE, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
	{0},
};

static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;

#if defined (CSU_RDC_TEST)
static void csu_rdc_test(void);
#endif

static uint32_t imx_soc_revision;

int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
				u_register_t x3)
{
	return imx_soc_revision;
}

#define ANAMIX_DIGPROG		0x6c
#define ROM_SOC_INFO_A0		0x800
#define ROM_SOC_INFO_B0		0x83C
#define OCOTP_SOC_INFO_B1	0x40

static void imx8mq_soc_info_init(void)
{
	uint32_t rom_version;
	uint32_t ocotp_val;

	imx_soc_revision = mmio_read_32(IMX_ANAMIX_BASE + ANAMIX_DIGPROG);
	rom_version = mmio_read_8(IMX_ROM_BASE + ROM_SOC_INFO_A0);
	if (rom_version == 0x10)
		return;

	rom_version = mmio_read_8(IMX_ROM_BASE + ROM_SOC_INFO_B0);
	if (rom_version == 0x20) {
		imx_soc_revision &= ~0xff;
		imx_soc_revision |= rom_version;
		return;
	}

	/* 0xff0055aa is magic number for B1 */
	ocotp_val = mmio_read_32(IMX_OCOTP_BASE + OCOTP_SOC_INFO_B1);
	if (ocotp_val == 0xff0055aa) {
		imx_soc_revision &= ~0xff;
		if (rom_version == 0x22)
		    imx_soc_revision |= 0x22;
		else
		    imx_soc_revision |= 0x21;
		return;
	}
}

#define IMX_DDR_BASE 0x40000000

#ifdef CFG_RDC_SECURE_DATA_PATH
#if defined(DECRYPTED_BUFFER_START) && defined(DECRYPTED_BUFFER_LEN)
#define DECRYPTED_BUFFER_END   	DECRYPTED_BUFFER_START + DECRYPTED_BUFFER_LEN
#endif

#if defined(DECODED_BUFFER_START) && defined(DECODED_BUFFER_LEN)
#define DECODED_BUFFER_END		DECODED_BUFFER_START + DECODED_BUFFER_LEN
#endif
#endif // CFG_RDC_SECURE_DATA_PATH

#if !defined(DECRYPTED_BUFFER_END) && !defined(DECODED_BUFFER_END)
#define RDC_DISABLED
#else
static const struct imx_rdc_cfg rdc_cfg[] = {
	/* Master domain assignment */
	RDC_MDAn(RDC_MDA_A53, DID0 | LCK),
	RDC_MDAn(RDC_MDA_CAAM, DID0 | LCK),
	RDC_MDAn(RDC_MDA_GPU, DID1 | LCK),
	RDC_MDAn(RDC_MDA_VPU_DEC, DID2 | LCK),
	RDC_MDAn(RDC_MDA_DCSS, DID3| LCK),

	/* peripherals domain permission */

	/* memory region */

	/*
	 * Need to substact offset 0x40000000 from CPU address when
	 * programming rdc region for i.mx8mq.
	 */

#if defined(DECRYPTED_BUFFER_START) && !defined(CFG_SECURE_HANTRO_VPU)
	/* Domain 2 no write access to memory region below decrypted video */
	/* Prevent VPU to decode outside secure decoded buffer */
	RDC_MEM_REGIONn(2, 0x0, (uint32_t)DECRYPTED_BUFFER_START - IMX_DDR_BASE, 0xC00000EF),
#endif // DECRYPTED_BUFFER_START

#ifdef DECRYPTED_BUFFER_END
	/* Domain 0 memory region W decrypted video */
	/* Domain 2 memory region R decrypted video */
	RDC_MEM_REGIONn(0, (uint32_t)DECRYPTED_BUFFER_START - IMX_DDR_BASE, (uint32_t)DECRYPTED_BUFFER_END - IMX_DDR_BASE, 0xC0000021),
#endif // DECRYPTED_BUFFER_END

#ifdef DECODED_BUFFER_END
	/* Domain 2+3 memory region R/W decoded video */
	RDC_MEM_REGIONn(1, (uint32_t)DECODED_BUFFER_START - IMX_DDR_BASE, (uint32_t)DECODED_BUFFER_END - IMX_DDR_BASE, 0xC00000F0),

#ifndef CFG_SECURE_HANTRO_VPU
	/* Domain 2 no write access to memory region above decoded video */
	RDC_MEM_REGIONn(3, (uint32_t)DECODED_BUFFER_END - IMX_DDR_BASE, 0x100000000 - IMX_DDR_BASE, 0xC00000EF),
#endif // CFG_SECURE_HANTRO_VPU

#endif // DECODED_BUFFER_END

	/* Sentinel */
	{0},
};
#endif

static const struct imx_csu_cfg csu_cfg_conf[] = {
	/* peripherals csl setting */
#ifdef CFG_SECURE_HANTRO_VPU
	CSU_CSLx(CSU_CSL_VPU_SEC, CSU_SEC_LEVEL_4, LOCKED),
#endif	
#ifdef DRM_SDP_HDCP_TA
	CSU_CSLx(CSU_CSL_HDMI_SEC, CSU_SEC_LEVEL_5, LOCKED),
	CSU_CSLx(CSU_CSL_HDMI_CTRL, CSU_SEC_LEVEL_5, LOCKED),
#endif
	/* master HP0~1 */

	/* SA setting */

	/* HP control setting */

	/* Sentinel */
	{0}
};

/* set RDC settings */
static void bl31_imx_rdc_setup(void)
{
#ifdef RDC_DISABLED
	NOTICE("RDC off \n");
#else
	imx_rdc_init(rdc_cfg);
#endif // RDC_DISABLED
}

/* get SPSR for BL33 entry */
static uint32_t get_spsr_for_bl33_entry(void)
{
	unsigned long el_status;
	unsigned long mode;
	uint32_t spsr;

	/* figure out what mode we enter the non-secure world */
	el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
	el_status &= ID_AA64PFR0_ELX_MASK;

	mode = (el_status) ? MODE_EL2 : MODE_EL1;

	spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
	return spsr;
}

static void bl31_tzc380_setup(void)
{
	unsigned int val;

	val = mmio_read_32(IMX_IOMUX_GPR_BASE + IOMUXC_GPR10);
	if ((val & GPR_TZASC_EN) != GPR_TZASC_EN)
		return;

	tzc380_init(IMX_TZASC_BASE);
	/*
	 * Need to substact offset 0x40000000 from CPU address when
	 * programming tzasc region for i.mx8mq. Enable 1G-5G S/NS RW
	 */
	tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) |
				TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
}

struct bl31_configs {
        bool       tee_presence;
        const char *config_1;
        uint32_t   config_2;
};
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
			u_register_t arg2, u_register_t arg3)
{
	int i;

	/* enable CSU NS access permission */
	for (i = 0; i < 64; i++) {
		mmio_write_32(IMX_CSU_BASE + i * 4, 0xffffffff);
	}

#if !defined (CSU_RDC_TEST)
	imx_csu_init(csu_cfg_conf);
#endif

	imx_aipstz_init(aipstz);

	imx8m_caam_init();

#if DEBUG_CONSOLE
	static console_t console;

	console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
		IMX_CONSOLE_BAUDRATE, &console);
	
#endif
	/*
	 * tell BL3-1 where the non-secure software image is located
	 * and the entry state information.
	 */
	bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
	bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);

#if defined(SPD_opteed) || defined(SPD_trusty)
	/* Populate entry point information for BL32 */
	SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
	SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);

	/*
	 *  Note: arg1 passed from bl31_entrypoint(X0, X1/arg1, ....) when SPL invokes
	 *  bl31_image_entry(X0, X1, ...). SPL will use arg1 to pass bl31_configs'
	 *  address into BL31.
	 *  If arg1 is NULL, means no OP-TEE & bl31_configs were detected by SPL.
	 */
	struct bl31_configs *configs = (struct bl31_configs *)arg1;
	bl32_image_ep_info.pc = (!configs->tee_presence)? 0 : BL32_BASE;
	bl32_image_ep_info.spsr = 0;

	/* Pass TEE base and size to bl33 */
#if defined(DECRYPTED_BUFFER_START) && defined(DECODED_BUFFER_LEN) && defined(DECRYPTED_BUFFER_LEN)
	/* Integrate SDP */
	bl33_image_ep_info.args.arg1 = DECRYPTED_BUFFER_START;
	bl33_image_ep_info.args.arg2 = BL32_SIZE + DECRYPTED_BUFFER_LEN + DECODED_BUFFER_LEN;
#else
	bl33_image_ep_info.args.arg1 = BL32_BASE;
	bl33_image_ep_info.args.arg2 = BL32_SIZE;
#endif

#ifdef SPD_trusty
	bl32_image_ep_info.args.arg0 = BL32_SIZE;
	bl32_image_ep_info.args.arg1 = BL32_BASE;
#else
	/* Make sure memory is clean */
	mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0);
	bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
	bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
	VERBOSE("bl31_early_platform_setup2 arg0/arg1/arg2/arg3 = (%ld, 0x%p, %ld, %ld). \n", (long)arg0, (void *)arg1, (long)arg2, (long)bl32_image_ep_info.args.arg4);
#endif
#endif

#if !defined(SPD_opteed) && !defined(SPD_trusty)
	enable_snvs_privileged_access();
#endif

	bl31_tzc380_setup();

#if defined (CSU_RDC_TEST)
	csu_rdc_test();
#endif

	bl31_imx_rdc_setup();

}

void bl31_plat_arch_setup(void)
{
	mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE),
		MT_MEMORY | MT_RW | MT_SECURE);
	mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE),
		MT_MEMORY | MT_RO | MT_SECURE);

	// Map TEE memory
	mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW);

	mmap_add(imx_mmap);

#if USE_COHERENT_MEM
	mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
		BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
		MT_DEVICE | MT_RW | MT_SECURE);
#endif
	/* setup xlat table */
	init_xlat_tables();
	/* enable the MMU */
	enable_mmu_el3(0);
}

void bl31_platform_setup(void)
{
	generic_delay_timer_init();

	/* init the GICv3 cpu and distributor interface */
	plat_gic_driver_init();
	plat_gic_init();

	/* determine SOC revision for erratas */
	imx8mq_soc_info_init();

	/* gpc init */
	imx_gpc_init();

	dram_info_init(SAVED_DRAM_TIMING_BASE);
}

entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
{
	VERBOSE("bl31_plat_get_next_image_ep_info is %d %ld\n", type, (long)bl32_image_ep_info.args.arg4);

	if (type == NON_SECURE)
		return &bl33_image_ep_info;
	if (type == SECURE && bl32_image_ep_info.pc)
		return &bl32_image_ep_info;

	return NULL;
}

unsigned int plat_get_syscnt_freq2(void)
{
	return mmio_read_32(IMX_SCTR_BASE + CNTFID0_OFF);
}

void bl31_plat_runtime_setup(void)
{
	return;
}

#ifdef SPD_trusty
void plat_trusty_set_boot_args(aapcs64_params_t *args) {
	args->arg0 = BL32_SIZE;
	args->arg1 = BL32_BASE;
	args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
}
#endif

#if defined (CSU_RDC_TEST)
static const struct imx_rdc_cfg rdc_for_test[] = {
	/* Master domain assignment */

	/* peripherals domain permission */

	RDC_PDAPn(RDC_PDAP_CSU, D2R | D2W),

	/* memory region */

	/* Sentinel */
	{0},
};

static const struct imx_csu_cfg csu_cfg_for_test[] = {
	/* peripherals csl setting */
	CSU_CSLx(CSU_CSL_RDC, CSU_SEC_LEVEL_4, LOCKED),
	CSU_CSLx(CSU_CSL_CSU, CSU_SEC_LEVEL_4, LOCKED),
	/* master HP0~1 */

	/* SA setting */

	/* HP control setting */

	/* Sentinel */
	{0}
};

static void csu_rdc_test(void)
{
	imx_csu_init(csu_cfg_for_test);
	imx_rdc_init(rdc_for_test);
}
#endif