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| author | Tom Rini <trini@konsulko.com> | 2020-01-03 09:48:47 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-01-03 09:48:47 -0500 |
| commit | 8fbbec12f7d2c18f8883f3371cfca74a98b5dd87 (patch) | |
| tree | a0e6f0bd143fa9baefe2c927b7fe089ebe8d51d7 /arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h | |
| parent | 87f69f467a8335b171c71bf217d2625d515acd7c (diff) | |
| parent | 63618e71e89b3fc669d56bcb4389e70a6b3a4ea8 (diff) | |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next
- updates and fixes on ls1028a, lx2, ls1046a, MC-DPSPARSER support
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index 94ea99a349..4c54e3d3d5 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2015-2018 NXP + * Copyright 2015-2019 NXP * Copyright 2014 Freescale Semiconductor, Inc. * */ @@ -42,6 +42,10 @@ * -the MC is responsible for allocating and setting up 'isolation context * IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices. * + * - ECAM (integrated PCI) + * - U-Boot applies the value here to HW and does DT fix-up for both + * 'iommu-map' and 'msi-map' + * * On Chasis-3 SoCs stream IDs are programmed in AMQ registers (32-bits) for * each of the different bus masters. The relationship between * the AMQ registers and stream IDs is defined in the table below: @@ -83,14 +87,12 @@ /* PCI - programmed in PEXn_LUT */ #define FSL_PEX_STREAM_ID_START 7 -#ifdef CONFIG_ARCH_LX2160A -#define FSL_PEX_STREAM_ID_NUM (0x100) -#endif - #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1028A) #define FSL_PEX_STREAM_ID_END 22 #elif defined(CONFIG_ARCH_LS1088A) #define FSL_PEX_STREAM_ID_END 18 +#elif defined(CONFIG_ARCH_LX2160A) +#define FSL_PEX_STREAM_ID_END (0x100) #endif @@ -98,6 +100,10 @@ #define FSL_DPAA2_STREAM_ID_START 23 #define FSL_DPAA2_STREAM_ID_END 63 +/* PCI IEPs, this overlaps DPAA2 but these two are exclusive at least for now */ +#define FSL_ECAM_STREAM_ID_START 32 +#define FSL_ECAM_STREAM_ID_END 63 + #define FSL_SEC_STREAM_ID 64 #define FSL_SEC_JR1_STREAM_ID 65 #define FSL_SEC_JR2_STREAM_ID 66 |