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authoryroux <yroux@138bc75d-0d04-0410-961f-82ee72b054a4>2014-09-09 12:40:52 +0000
committeryroux <yroux@138bc75d-0d04-0410-961f-82ee72b054a4>2014-09-09 12:40:52 +0000
commitcd89822ad243f4ff8624f55f911241adcb53b48a (patch)
tree19ed14e128a048fc4ba721da9646b448d5c6b6c5
parentf9316beac133c7644c9ff4d7c281e7ef52d55fc6 (diff)
2014-09-09 Venkataramanan Kumar <venkataramanan.kumar@linaro.org>
Backport from trunk r215004. 2014-09-07 Venkataramanan Kumar <venkataramanan.kumar@linaro.org> PR target/63190 * config/aarch64/aarch64.md (stack_protect_test_<mode>) Add register constraint for operand0 and remove write only modifier from operand3. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@215069 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r--gcc/ChangeLog.linaro9
-rw-r--r--gcc/config/aarch64/aarch64.md4
2 files changed, 11 insertions, 2 deletions
diff --git a/gcc/ChangeLog.linaro b/gcc/ChangeLog.linaro
index fa66219b762..ab978ca993e 100644
--- a/gcc/ChangeLog.linaro
+++ b/gcc/ChangeLog.linaro
@@ -1,3 +1,12 @@
+2014-09-09 Venkataramanan Kumar <venkataramanan.kumar@linaro.org>
+
+ Backport from trunk r215004.
+ 2014-09-07 Venkataramanan Kumar <venkataramanan.kumar@linaro.org>
+
+ PR target/63190
+ * config/aarch64/aarch64.md (stack_protect_test_<mode>) Add register
+ constraint for operand0 and remove write only modifier from operand3.
+
2014-09-09 Michael Collison <michael.collison@linaro.org>
Backport from trunk r212178
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 74d271aeadf..38d919edc51 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -3967,11 +3967,11 @@
})
(define_insn "stack_protect_test_<mode>"
- [(set (match_operand:PTR 0 "register_operand")
+ [(set (match_operand:PTR 0 "register_operand" "=r")
(unspec:PTR [(match_operand:PTR 1 "memory_operand" "m")
(match_operand:PTR 2 "memory_operand" "m")]
UNSPEC_SP_TEST))
- (clobber (match_scratch:PTR 3 "=&r"))]
+ (clobber (match_scratch:PTR 3 "&r"))]
""
"ldr\t%<w>3, %x1\;ldr\t%<w>0, %x2\;eor\t%<w>0, %<w>3, %<w>0"
[(set_attr "length" "12")