diff options
| author | sandra <sandra@138bc75d-0d04-0410-961f-82ee72b054a4> | 2006-05-12 13:53:27 +0000 |
|---|---|---|
| committer | sandra <sandra@138bc75d-0d04-0410-961f-82ee72b054a4> | 2006-05-12 13:53:27 +0000 |
| commit | 301f5dae3f962bd28c9724b74c42c47277b44c7e (patch) | |
| tree | 45e3737a3b19d08135b5f466c936faf77a3bffb6 | |
| parent | f81f318e44530a289cca61078be0babc34ee8307 (diff) | |
Implement clz using ff1 instruction on ColdFire architectures that support it
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/csl/coldfire-4_1@113723 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | ChangeLog.csl | 7 | ||||
| -rw-r--r-- | gcc/config/m68k/m68k.h | 4 | ||||
| -rw-r--r-- | gcc/config/m68k/m68k.md | 9 | ||||
| -rw-r--r-- | gcc/longlong.h | 5 |
4 files changed, 25 insertions, 0 deletions
diff --git a/ChangeLog.csl b/ChangeLog.csl index c2bce035871..3cc3512c751 100644 --- a/ChangeLog.csl +++ b/ChangeLog.csl @@ -1,3 +1,10 @@ +2006-05-12 Sandra Loosemore <sandra@codesourcery.com> + + * gcc/config/m68k/m68k.md ("clzsi2"): Define for ColdFire + architectures that support ff1 instruction. + * gcc/config/m68k/m68k.h (CLZ_DEFINED_VALUE_AT_ZERO): Ditto. + * gcc/longlong.h (count_leading_zeros, COUNT_LEADING_ZEROS_0): Ditto. + 2006-05-11 Richard Sandiford <richard@codesourcery.com> gcc/ diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h index 6e4498e6845..65b18dbff7b 100644 --- a/gcc/config/m68k/m68k.h +++ b/gcc/config/m68k/m68k.h @@ -852,6 +852,10 @@ __transfer_from_trampoline () \ #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 +/* The ColdFire FF1 instruction returns 32 for zero. */ +#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ + ((VALUE) = 32, 1) + #define STORE_FLAG_VALUE (-1) #define Pmode SImode diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md index 2dfdc2edcb0..044d7a0d485 100644 --- a/gcc/config/m68k/m68k.md +++ b/gcc/config/m68k/m68k.md @@ -3986,6 +3986,15 @@ return "f<FP:prec>abs%.<FP:prec> %1,%0"; }) +;; bit indexing instructions + +;; ColdFire ff1 instruction implements clz. +(define_insn "clzsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (clz:SI (match_operand:SI 1 "register_operand" "0")))] + "m68k_arch_isaaplus || m68k_arch_isac" + "ff1 %0") + ;; one complement instructions ;; "one_cmpldi2" is mainly here to help combine(). diff --git a/gcc/longlong.h b/gcc/longlong.h index cdcabed6a40..fbe3438565d 100644 --- a/gcc/longlong.h +++ b/gcc/longlong.h @@ -521,6 +521,11 @@ UDItype __umulsidi3 (USItype, USItype); __asm__ ("bfffo %1{%b2:%b2},%0" \ : "=d" ((USItype) (count)) \ : "od" ((USItype) (x)), "n" (0)) +/* Some ColdFire architectures have a ff1 instruction supported via + __builtin_clz. */ +#elif defined (__mcfisaaplus__) || defined (__mcfisac__) +#define count_leading_zeros(count,x) ((count) = __builtin_clz (x)) +#define COUNT_LEADING_ZEROS_0 32 #endif #endif /* mc68000 */ |