checkpoint

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/ibm/addr@262602 138bc75d-0d04-0410-961f-82ee72b054a4

2 files changed, 38 insertions, 20 deletions

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 0ac5a7d9eb9..3b9c242cdb7 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,5 +1,15 @@
 2018-07-12  Michael Meissner  <meissner@linux.ibm.com>
 
+	* config/rs6000/rs6000.md (LADDR_GSTORE): Delete, not currently
+	used.
+	(LADDR_FSTORE): Likewise.
+	(LADDR_VSTORE): Likewise.
+	(large_mov<mode>_store): Change all stores to split the ADDIS and
+	store into separate insns, rather than keeping them in a single
+	insn.
+
+2018-07-12  Michael Meissner  <meissner@linux.ibm.com>
+
 	* config/rs6000/constraints.md (wC constraint): Define new
 	constraints for large memory operations, and non-large memory
 	operations.
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 9211808daef..65303af2476 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -717,11 +717,6 @@
 (define_mode_attr LADDR_FLOAD	[(SF "lfs")   (DF "lfd")])
 (define_mode_attr LADDR_VLOAD	[(SF "lxssp") (DF "lxsd")])
 
-;; Attribute for the store instruction for GPRs, FPRs, and Altivec registers.
-(define_mode_attr LADDR_GSTORE [(SF "stw")    (DF "std")])
-(define_mode_attr LADDR_FSTORE [(SF "stfs")   (DF "stfd")])
-(define_mode_attr LADDR_VSTORE [(SF "stxssp") (DF "stxsd)")])
-
 ;; Insns for large addresses.
 
 (define_insn "large_mov<mode>_load"
@@ -768,19 +763,28 @@
   [(set_attr "length" "8")
    (set_attr "type" "load")])
 
-(define_insn "large_mov<mode>_store"
+(define_insn_and_split "large_mov<mode>_store"
   [(set (match_operand:QHSI 0 "large_mem_operand" "=wC")
 	(match_operand:QHSI 1 "int_reg_operand"  "r"))
    (unspec [(const_int 0)] UNSPEC_LADDR_STORE)
    (clobber (match_scratch:DI 2 "=&b"))]
   "TARGET_LARGE_ADDRESS && TARGET_POWERPC64"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 2)
+	(match_dup 3))
+   (set (match_dup 4)
+	(match_dup 1))]
 {
+  rtx hi, lo, new_addr;
   rtx mem = operands[0];
-  rtx reg = operands[1];
-  rtx tmp = operands[2];
+  rtx addr = XEXP (mem, 0);
+  rtx tmp_reg = operands[2];
+  enum rtx_code add_code = split_large_address_hilo (addr, &hi, &lo);
 
-  output_large_address_load_store (reg, mem, tmp, "st<wd>");
-  return "";
+  new_addr = gen_rtx_fmt_ee (add_code, Pmode, tmp_reg, lo);
+  operands[3] = hi;
+  operands[4] = replace_equiv_address (mem, new_addr);
 }
   [(set_attr "length" "8")
    (set_attr "type" "store")])
@@ -872,24 +876,28 @@
   [(set_attr "length" "8")
    (set_attr "type" "fpload,fpload,load")])
 
-(define_insn "large_mov<mode>_store"
+(define_insn_and_split "large_mov<mode>_store"
   [(set (match_operand:SFDF 0 "large_mem_operand" "=wC,wC,wC")
 	(match_operand:SFDF 1 "gpc_reg_operand"  "d,wb,*r"))
    (unspec [(const_int 0)] UNSPEC_LADDR_STORE)
    (clobber (match_scratch:DI 2 "=b,b,&b"))]
   "TARGET_LARGE_ADDRESS && TARGET_POWERPC64"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 2)
+	(match_dup 3))
+   (set (match_dup 4)
+	(match_dup 1))]
 {
+  rtx hi, lo, new_addr;
   rtx mem = operands[0];
-  rtx reg = operands[1];
-  rtx tmp = operands[2];
-  static const char *const store[3] = {
-    "<LADDR_FSTORE>",
-    "<LADDR_VSTORE>",
-    "<LADDR_GSTORE>"
-  };
+  rtx addr = XEXP (mem, 0);
+  rtx tmp_reg = operands[2];
+  enum rtx_code add_code = split_large_address_hilo (addr, &hi, &lo);
 
-  output_large_address_load_store (reg, mem, tmp, store[which_alternative]);
-  return "";
+  new_addr = gen_rtx_fmt_ee (add_code, Pmode, tmp_reg, lo);
+  operands[3] = hi;
+  operands[4] = replace_equiv_address (mem, new_addr);
 }
   [(set_attr "length" "8")
    (set_attr "type" "fpstore,fpstore,store")])