gcc:

2017-03-10  Will Schmidt <will_schmidt@vnet.ibm.com>

     PR target/79941
     * config/rs6000/rs6000.c (builtin_function_type): Add VMUL*U[HB]
     entries to the case statement that marks unsigned arguments to
     overloaded functions.

testsuite:
2017-03-10  Will Schmidt <will_schmidt@vnet.ibm.com>

     PR target/79941
     * gcc.target/powerpc/fold-vec-mult-even_odd_misc.c: New test.
     * gcc.target/powerpc/fold-vec-mult-even_odd_char.c: New test.
     * gcc.target/powerpc/fold-vec-mult-even_odd_short.c: New test.




git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@246040 138bc75d-0d04-0410-961f-82ee72b054a4

6 files changed, 154 insertions, 0 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 19e68375cca..3cbc63d69f9 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2017-03-10  Will Schmidt <will_schmidt@vnet.ibm.com>
+ 
+	PR target/79941
+	* config/rs6000/rs6000.c (builtin_function_type): Add VMUL*U[HB]
+	entries to the case statement that marks unsigned arguments to
+	overloaded functions.
+
 2017-03-10  Kelvin Nilsen  <kelvin@gcc.gnu.org>
 
 	* config/rs6000/rs6000.c (rs6000_option_override_internal): Fix
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 6618481ee3b..4371b00d79e 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -18530,6 +18530,10 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
     case ALTIVEC_BUILTIN_VMULEUH_UNS:
     case ALTIVEC_BUILTIN_VMULOUB_UNS:
     case ALTIVEC_BUILTIN_VMULOUH_UNS:
+    case ALTIVEC_BUILTIN_VMULEUB:
+    case ALTIVEC_BUILTIN_VMULEUH:
+    case ALTIVEC_BUILTIN_VMULOUB:
+    case ALTIVEC_BUILTIN_VMULOUH:
     case CRYPTO_BUILTIN_VCIPHER:
     case CRYPTO_BUILTIN_VCIPHERLAST:
     case CRYPTO_BUILTIN_VNCIPHER:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index bd5919f9649..b23426f0e9c 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2017-03-10  Will Schmidt <will_schmidt@vnet.ibm.com>
+    
+	PR target/79941
+	* gcc.target/powerpc/fold-vec-mult-even_odd_misc.c: New test.
+	* gcc.target/powerpc/fold-vec-mult-even_odd_char.c: New test.
+	* gcc.target/powerpc/fold-vec-mult-even_odd_short.c: New test.
+
 2017-03-10  Marek Polacek  <polacek@redhat.com>
 
 	PR c++/79967
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-char.c
new file mode 100644
index 00000000000..02d9789f86f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-char.c
@@ -0,0 +1,38 @@
+/* Verify that overloaded built-ins for vec_mule,vec_mulo with char
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector signed short
+test_even (vector signed char x, vector signed char y)
+{
+  return vec_mule (x, y);
+}
+
+vector unsigned short
+test_uns_even (vector unsigned char x, vector unsigned char y)
+{
+  return vec_mule (x, y);
+}
+
+vector signed short
+test_odd (vector signed char x, vector signed char y)
+{
+  return vec_mulo (x, y);
+}
+
+vector unsigned short
+test_uns_odd (vector unsigned char x, vector unsigned char y)
+{
+  return vec_mulo (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vmuleub" 1 } } */
+/* { dg-final { scan-assembler-times "vmulesb" 1 } } */
+/* { dg-final { scan-assembler-times "vmuloub" 1 } } */
+/* { dg-final { scan-assembler-times "vmulosb" 1 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c
new file mode 100644
index 00000000000..4bb61853169
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-misc.c
@@ -0,0 +1,61 @@
+/* PR target/79941 */
+
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx -O2 -save-temps" } */
+
+#include <altivec.h>
+
+__attribute__((noinline)) void 
+test_eub_char ()
+{
+  volatile vector unsigned char v0 = {1, 0, 0, 0, 0, 0, 0, 0};
+  volatile vector unsigned char v1 = {0xff, 0, 0, 0, 0, 0, 0, 0};
+  vector unsigned short res = vec_vmuleub (v0, v1);
+  if (res[0] != (unsigned short)v0[0] * (unsigned short)v1[0])
+    __builtin_abort ();
+}
+
+__attribute__((noinline)) void 
+test_oub_char ()
+{
+  volatile vector unsigned char v0 = {0, 1, 0, 0, 0, 0, 0, 0};
+  volatile vector unsigned char v1 = {0, 0xff, 0, 0, 0, 0, 0, 0};
+  vector unsigned short res = vec_vmuloub (v0, v1);
+  if (res[0] != (unsigned short)v0[1] * (unsigned short)v1[1])
+    __builtin_abort ();
+}
+
+__attribute__((noinline)) void 
+test_euh_short ()
+{
+  volatile vector unsigned short v0 = {1, 0, 0, 0};
+  volatile vector unsigned short v1 = {0xff, 0, 0, 0};
+  vector unsigned int res = vec_vmuleuh (v0, v1);
+  if (res[0] != (unsigned int)v0[0] * (unsigned int)v1[0])
+    __builtin_abort ();
+}
+
+__attribute__((noinline)) void 
+test_ouh_short ()
+{
+  volatile vector unsigned short v0 = {0, 1, 0, 0};
+  volatile vector unsigned short v1 = {0, 0xff, 0, 0};
+  vector unsigned int res = vec_vmulouh (v0, v1);
+  if (res[0] != (unsigned int)v0[1] * (unsigned int)v1[1])
+    __builtin_abort ();
+}
+
+int main ()
+{
+  test_eub_char();
+  test_oub_char();
+  test_euh_short();
+  test_ouh_short();
+}
+
+/* { dg-final { scan-assembler-times "vmuleub" 1 } } */
+/* { dg-final { scan-assembler-times "vmuloub" 1 } } */
+/* { dg-final { scan-assembler-times "vmuleuh" 1 } } */
+/* { dg-final { scan-assembler-times "vmulouh" 1 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-short.c
new file mode 100644
index 00000000000..79b44d530e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mule-short.c
@@ -0,0 +1,37 @@
+/* Verify that overloaded built-ins for vec_mule,vec_mulo with short
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector signed int
+test_even (vector signed short x, vector signed short y)
+{
+  return vec_mule (x, y);
+}
+
+vector unsigned int
+test_uns_even (vector unsigned short x, vector unsigned short y)
+{
+  return vec_mule (x, y);
+}
+
+vector signed int
+test_odd (vector signed short x, vector signed short y)
+{
+  return vec_mulo (x, y);
+}
+
+vector unsigned int
+test_uns_odd (vector unsigned short x, vector unsigned short y)
+{
+  return vec_mulo (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vmuleuh" 1 } } */
+/* { dg-final { scan-assembler-times "vmulesh" 1 } } */
+/* { dg-final { scan-assembler-times "vmulouh" 1 } } */
+/* { dg-final { scan-assembler-times "vmulosh" 1 } } */