Remove VSX load/store with update support

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/ibm/gcc-4_3-branch@151937 138bc75d-0d04-0410-961f-82ee72b054a4

4 files changed, 40 insertions, 74 deletions

diff --git a/gcc/ChangeLog.ibm b/gcc/ChangeLog.ibm
index 6c4421eb338..2f5456c7245 100644
--- a/gcc/ChangeLog.ibm
+++ b/gcc/ChangeLog.ibm
@@ -1,3 +1,37 @@
+2009-09-21  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	* target-def.h (TARGET_VECTORIZE): Remove extra spacing at the end
+	of the line.
+
+	* config/rs6000/rs6000.c (rs6000_legitimate_address_p): Drop
+	support for VSX memory reference instructions with update.
+	* config/rs6000/vsx.md (vsx_mov<mode>): Ditto.
+	(vsx_movti): Ditto.
+	(VSX_U): Delete, no longer need with load/store with update
+	removed.
+	(VSbit): Ditto.
+	(VStype_load_update): Ditto.
+	(VStype_store_update): Ditto.
+	(vsx_load<VSX_U:mode>_update_<P:mptrsize>): Ditto.
+	(vsx_store<VSX_U:mode>_update_<P:mptrsize>): Ditto.
+
+2009-09-17  Revital Eres  <eres@il.ibm.com>
+
+	* doc/tm.texi (TARGET_SUPPORT_VECTOR_MISALIGNMENT): Document.
+	* targhooks.c (default_builtin_support_vector_misalignment):
+	New builtin function.
+	* targhooks.h (default_builtin_support_vector_misalignment):
+	Declare.
+	* target.h (builtin_support_vector_misalignment):
+	New field in struct gcc_target.
+	* tree-vectorizer.c (vect_supportable_dr_alignment): Call
+	new builtin function.
+	* target-def.h (TARGET_SUPPORT_VECTOR_MISALIGNMENT):
+	Define.
+	* config/rs6000/rs6000.c
+	(rs6000_builtin_support_vector_misalignment): New function.
+	(TARGET_SUPPORT_VECTOR_MISALIGNMENT): Define.
+
 2009-09-17  Michael Meissner  <meissner@linux.vnet.ibm.com>
 
 	Merge up to 151807.
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 0c9d96fc2df..ba9089b8844 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -5580,12 +5580,6 @@ rs6000_legitimate_address_p (enum machine_mode mode, rtx x, bool reg_ok_strict)
       && legitimate_indexed_address_p (x, reg_ok_strict))
     return 1;
   if (GET_CODE (x) == PRE_MODIFY
-      && VECTOR_MEM_VSX_P (mode)
-      && TARGET_UPDATE
-      && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)
-      && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
-    return 1;
-  if (GET_CODE (x) == PRE_MODIFY
       && mode != TImode
       && mode != TFmode
       && mode != TDmode
@@ -5593,7 +5587,7 @@ rs6000_legitimate_address_p (enum machine_mode mode, rtx x, bool reg_ok_strict)
 	  || TARGET_POWERPC64
 	  || ((mode != DFmode && mode != DDmode) || TARGET_E500_DOUBLE))
       && (TARGET_POWERPC64 || mode != DImode)
-      && !VECTOR_MEM_ALTIVEC_P (mode)
+      && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
       && !SPE_VECTOR_MODE (mode)
       /* Restrict addressing for DI because of our SUBREG hackery.  */
       && !(TARGET_E500_DOUBLE
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 1d8fc71d51c..9125f1a60f7 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -38,9 +38,6 @@
 ;; it to use gprs as well as vsx registers.
 (define_mode_iterator VSX_M [V16QI V8HI V4SI V2DI V4SF V2DF])
 
-;; Iterator for types for load/store with update
-(define_mode_iterator VSX_U [V16QI V8HI V4SI V2DI V4SF V2DF TI DF])
-
 ;; Map into the appropriate load/store name based on the type
 (define_mode_attr VSm  [(V16QI "vw4")
 			(V8HI  "vw4")
@@ -108,10 +105,6 @@
 		       (V2DF "d")
 		       (DF   "d")])
 
-;; Bitsize for DF load with update
-(define_mode_attr VSbit [(SI "32")
-			 (DI "64")])
-
 ;; Map into either s or v, depending on whether this is a scalar or vector
 ;; operation
 (define_mode_attr VSv	[(V16QI "v")
@@ -186,26 +179,6 @@
 			     (V8HI	"HI")
 			     (V16QI	"QI")])
 			     
-;; Appropriate type for load + update
-(define_mode_attr VStype_load_update [(V16QI "vecload")
-				      (V8HI  "vecload")
-				      (V4SI  "vecload")
-				      (V4SF  "vecload")
-				      (V2DI  "vecload")
-				      (V2DF  "vecload")
-				      (TI    "vecload")
-				      (DF    "fpload")])
-
-;; Appropriate type for store + update
-(define_mode_attr VStype_store_update [(V16QI "vecstore")
-				       (V8HI  "vecstore")
-				       (V4SI  "vecstore")
-				       (V4SF  "vecstore")
-				       (V2DI  "vecstore")
-				       (V2DF  "vecstore")
-				       (TI    "vecstore")
-				       (DF    "fpstore")])
-
 ;; Constants for creating unspecs
 (define_constants
   [(UNSPEC_VSX_CONCAT		500)
@@ -245,11 +218,11 @@
     {
     case 0:
     case 3:
-      return "stx<VSm>%U0x %x1,%y0";
+      return "stx<VSm>x %x1,%y0";
 
     case 1:
     case 4:
-      return "lx<VSm>%U0x %x0,%y1";
+      return "lx<VSm>x %x0,%y1";
 
     case 2:
     case 5:
@@ -291,10 +264,10 @@
   switch (which_alternative)
     {
     case 0:
-      return "stxvd2%U0x %x1,%y0";
+      return "stxvd2x %x1,%y0";
 
     case 1:
-      return "lxvd2%U0x %x0,%y1";
+      return "lxvd2x %x0,%y1";
 
     case 2:
       return "xxlor %x0,%x1,%x1";
@@ -322,41 +295,6 @@
 }
   [(set_attr "type" "vecstore,vecload,vecsimple,*,*,*,vecsimple,*,vecstore,vecload")])
 
-;; Load/store with update
-;; Define insns that do load or store with update.  Because VSX only has
-;; reg+reg addressing, pre-decrement or pre-increment is unlikely to be
-;; generated.
-;;
-;; In all these cases, we use operands 0 and 1 for the register being
-;; incremented because those are the operands that local-alloc will
-;; tie and these are the pair most likely to be tieable (and the ones
-;; that will benefit the most).
-
-(define_insn "*vsx_load<VSX_U:mode>_update_<P:mptrsize>"
-  [(set (match_operand:VSX_U 3 "vsx_register_operand" "=<VSr>,?wa")
-	(mem:VSX_U (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
-			   (match_operand:P 2 "gpc_reg_operand" "r,r"))))
-   (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
-	(plus:P (match_dup 1)
-		(match_dup 2)))]
-  "<P:tptrsize> && TARGET_UPDATE && VECTOR_MEM_VSX_P (<MODE>mode)"
-  "lx<VSm>ux %x3,%0,%2"
-  [(set_attr "type" "<VSX_U:VStype_load_update>")])
-
-(define_insn "*vsx_store<mode>_update_<P:mptrsize>"
-  [(set (mem:VSX_U (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
-			   (match_operand:P 2 "gpc_reg_operand" "r,r")))
-	(match_operand:VSX_U 3 "gpc_reg_operand" "<VSr>,?wa"))
-   (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
-	(plus:P (match_dup 1)
-		(match_dup 2)))]
-  "<P:tptrsize> && TARGET_UPDATE && VECTOR_MEM_VSX_P (<MODE>mode)"
-  "stx<VSm>ux %x3,%0,%2"
-  [(set_attr "type" "<VSX_U:VStype_store_update>")])
-
-;; We may need to have a varient on the pattern for use in the prologue
-;; that doesn't depend on TARGET_UPDATE.
-
 
 ;; VSX scalar and vector floating point arithmetic instructions
 (define_insn "*vsx_add<mode>3"
diff --git a/gcc/target-def.h b/gcc/target-def.h
index 8f1d2e8db79..b94f289a535 100644
--- a/gcc/target-def.h
+++ b/gcc/target-def.h
@@ -376,7 +376,7 @@
     TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD,				\
     TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST,			\
     TARGET_VECTOR_ALIGNMENT_REACHABLE,					\
-    TARGET_SUPPORT_VECTOR_MISALIGNMENT					\		
+    TARGET_SUPPORT_VECTOR_MISALIGNMENT					\
   }
 
 #define TARGET_DEFAULT_TARGET_FLAGS 0