diff options
| author | meissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4> | 2009-05-01 22:06:11 +0000 |
|---|---|---|
| committer | meissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4> | 2009-05-01 22:06:11 +0000 |
| commit | 165f7d99d851e353b0459244269c21157fda4ad3 (patch) | |
| tree | 80e176d3fcc8ba08e7513784295a7266186aaacd | |
| parent | 98f9079c895735bc5f1ee58b27caa9669557579e (diff) | |
more vector alignment cleanups
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/ibm/gcc-4_3-branch@147046 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/config/rs6000/vector.md | 12 | ||||
| -rw-r--r-- | gcc/config/rs6000/vsx.md | 8 |
2 files changed, 9 insertions, 11 deletions
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index 8b4656c4bdb..ba27731c90f 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -778,15 +778,21 @@ (match_operand:VEC_K 1 "vlogical_operand" "") (match_operand:VEC_K 2 "vlogical_operand" "") (match_operand:V16QI 3 "vlogical_operand" "")] - "VECTOR_MEM_ALTIVEC_P (<MODE>mode) - || ((<MODE>mode == V16QImode || <MODE>mode == V8HImode) - && VECTOR_MEM_VSX_P (<MODE>mode))" + "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)" { emit_insn (gen_altivec_vperm_<mode> (operands[0], operands[1], operands[2], operands[3])); DONE; }) +;; Under VSX, vectors of 4/8 byte alignments do not need to be aligned +;; since the load already handles it. +(define_expand "movmisalign<mode>" + [(set (match_operand:VEC_N 0 "vfloat_operand" "") + (match_operand:VEC_N 1 "vfloat_operand" ""))] + "VECTOR_MEM_VSX_P (<MODE>mode)" + "") + ;; Vector shift left in bits. Currently supported ony for shift ;; amounts that can be expressed as byte shifts (divisible by 8). diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 470350e5ec2..5a0a425a83e 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -360,14 +360,6 @@ ;; We may need to have a varient on the pattern for use in the prologue ;; that doesn't depend on TARGET_UPDATE. - -;; Under VSX, vectors of 4/8 byte alignments do not need to be aligned -;; since the load already handles it. -(define_expand "movmisalign<mode>" - [(set (match_operand:VSX_N 0 "vsx_register_operand" "") - (match_operand:VSX_N 1 "vsx_register_operand" ""))] - "VECTOR_MEM_VSX_P (<MODE>mode)" - "") ;; VSX scalar and vector floating point arithmetic instructions (define_insn "*vsx_add<mode>3" |