Fix glibc build problem; Add hooks for vector realignment; fix a few testsuite failures

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/ibm/gcc-4_3-branch@147039 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 86 insertions, 0 deletions

diff --git a/gcc/ChangeLog.ibm b/gcc/ChangeLog.ibm
index 82aa936b27f..de0d08d8cb4 100644
--- a/gcc/ChangeLog.ibm
+++ b/gcc/ChangeLog.ibm
@@ -1,3 +1,89 @@
+2009-05-01  Michael Meissner  <meissner@linux.vnet.ibm.com>
+	    Revital1 Eres <ERES@il.ibm.com>
+
+	Backport from 05-01 power7-meissner branch:
+	* config/rs6000/rs6000-c.c (rs6000_macro_to_expand): Do not expand
+	__vector if it is not followed by a known identifier.
+
+	* config/rs6000/rs6000.c (rs6000_emit_vector_cond_expr): Don't
+	call unsigned_condition, just manually recognize the unsigned
+	condition tests.  Return NULL_RTX for unhandled conditions.
+
+	* config/rs6000/vector.md (VEC_K, VEC_N): New iterator for vector
+	alignment support.
+	(vec_pack_trunc_v2df): Use vfloat_operand, vint_operand, or
+	vlogical_operand instead of vsx_register.
+	(vec_pack_sfix_trunc_v2df): Ditto.
+	(vec_unpacks_hi_v4sf): Ditto.
+	(vec_unpacks_lo_vv4sf): Ditto.
+	(vec_unpacks_float_hi_v4si): Ditto.
+	(vec_unpacks_float_lo_v4si): Ditto.
+	(vec_unpacku_float_hi_v4si): Ditto.
+	(vec_unpacku_float_lo_v4si): Ditto.
+	(vec_realign_load_<mode>): Move here from altivec.md.  Generate a
+	vperm instruction instead of being an alias that does the same
+	thing.
+	(movmisalign<mode>): New insns, VSX vectors with 4/8 byte
+	alignments don't need realignment support.
+	(vec_shl_<mode>): Move here from altivec.md.
+	(vec_shr_<mode>): Ditto.
+
+	* config/rs6000/altivec.md (altivec_vsldoi_<mode>): Define for all
+	vector types.
+	(vec_shl_<mode>): Move to vector.md.
+	(vec_shr_<mode>): Ditto.
+	(vec_realign_load_<mode>): Ditto.
+
+	* config/rs6000/vector.md (vector_select_<mode>): Rename from
+	vector_vsel_<mode>.  Use mode of CCmode on the NE operator.
+	(vector_select_<mode>_uns): Clone vector_select_<mode> for
+	unsigned types.
+
+	* config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Map both of
+	the A and M types of multiply/add builtins to the internal name
+	without either A/M, since the compiler will pick the appropriate
+	instruction based on the registers allocated.
+
+	* config/rs6000/rs6000.c (builtin_mode_to_type): Add support for
+	unsigned types.
+	(struct builtin_hash_struct): Ditto.
+	(rs6000_init_builtins): Ditto.
+	(builtin_hash_function): Ditto.
+	(builtin_hash_eq): Ditto.
+	(builtin_function_type): Add an argument for the builtin function
+	code.  For functions that take or produce unsigned types, use an
+	unsigned type instead of a signed types to make things type
+	correct.  Change callers.
+	(rs6000_builtin_vec_perm): Add support for unsigned vector permute
+	functions.
+	(bdesc_3arg): Ditto.
+	(rs6000_emit_vector_cond): Ditto.
+
+	* config/rs6000/vsx.md (vsx_xxsel<mode>): Make NE operator have
+	CCmode mode.
+	(vsx_xxsel<mode>_uns): Clone vsx_xxsel<mode> to make unsigned
+	varients.
+
+	* config/rs6000/rs6000.h (ALTIVEC_BUILTIN_VSEL*): Add unsigned
+	variants.
+	(ALTIVEC_BUILTIN_VPERM*): Ditto.
+	(VSX_BUILTIN_XXSEL*): Ditto.
+	(VSX_BUILTIN_VPERM*): Ditto.
+
+	* config/rs6000/altivec.md (UNSPEC_VPERM_UNS): New unspec constant.
+	(altivec_vsel<mode>): Use CCmode for NE mode.
+	(altivec_vsel<mode>_uns): Clone from altivec_vsel<mode> for
+	unsigned types.
+	(altivec_vperm<mode>_uns): New insn for vperm on unsigned types.
+
+	* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Add
+	enum casts to make code type correct for C++.
+	(bdesc_altivec_preds): Use CODE_FOR_nothing instead of 0.
+	(struct builtin_hash_struct): Change to new-style GTY markers.
+	(builtin_hash_table): Ditto.
+	(builtin_function_type): Make call to htab_find_slot be type
+	correct.
+
 2009-04-27  Michael Meissner  <meissner@linux.vnet.ibm.com>
 
 	Backport from 04-27 power7-meissner branch (optimization of